[RESEND PATCH v2 2/2] clk: meson-g12a: Add EE Clock controller driver
jian.hu at amlogic.com
Tue Jul 17 05:20:48 PDT 2018
On 2018/7/16 19:00, Jerome Brunet wrote:
> On Mon, 2018-07-16 at 16:11 +0800, Jian Hu wrote:
>> Add a Clock driver for the Everything-Else part
>> of the Amlogic Meson-G12A SoC.
>> Signed-off-by: Jian Hu <jian.hu at amlogic.com>
> Point raised about fdiv gates remains un-answered.
> Please address all the point raised before reposting your patches.
So sorry, I have missed the question of fixed div gates.
You are right, g12a has gates in front of these fdivX clock, And they
are controlled by bit 20 to 25 in HHI_FIX_PLL_CNTL1 register. The
details are in the attachment which I have marked.
clock gate control bit
Maybe it is not clear in your datasheet.
I will update the code for this.
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