[PATCH 2/3] clk: meson: add sub EMMC clock dt-bindings IDs

Yixun Lan yixun.lan at amlogic.com
Tue Jul 3 00:36:46 PDT 2018


Hi Broris

 thanks for your quick response, and see my comments below

On 07/03/18 15:21, Boris Brezillon wrote:
> On Tue, 3 Jul 2018 14:57:15 +0000
> Yixun Lan <yixun.lan at amlogic.com> wrote:
> 
>> Add two clock bindings IDs which provided by the EMMC clock controller,
>> These two clocks will be used by EMMC or NAND driver.
>>
>> Signed-off-by: Yixun Lan <yixun.lan at amlogic.com>
>> ---
>>  include/dt-bindings/clock/emmc-clkc.h | 14 ++++++++++++++
>>  1 file changed, 14 insertions(+)
>>  create mode 100644 include/dt-bindings/clock/emmc-clkc.h
>>
>> diff --git a/include/dt-bindings/clock/emmc-clkc.h b/include/dt-bindings/clock/emmc-clkc.h
>> new file mode 100644
>> index 000000000000..d9972c400e58
>> --- /dev/null
>> +++ b/include/dt-bindings/clock/emmc-clkc.h
>> @@ -0,0 +1,14 @@
>> +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
>> +/*
>> + * Meson EMMC sub clock tree IDs
>> + *
>> + * Copyright (c) 2018 Amlogic, Inc. All rights reserved.
>> + */
>> +
>> +#ifndef __EMMC_CLKC_H
>> +#define __EMMC_CLKC_H
>> +
>> +#define CLKID_EMMC_C_MUX				0
> 
> Looks like the MUX clk is the parent of the DIV one, and I guess the clk
> driver is able to select the best parent+div pair for a requested rate.
> Do you really need to expose the MUX to users?
> 

Yes, It's true, the mux is parent of the div clock.

while testing for the NAND driver, I find it's kind of loose about the
parent of the clock, so selecting the div (and let CCF decide freely) is
actually works fine

but for the EMMC driver, especially when running at high clock, it's
kind of picky about the parent of the clock, so the driver may want to
manually choose the parent of the mux clock (example fclk_div2 here).
That's why I'm exporting this clock ID.


>> +#define CLKID_EMMC_C_DIV				1
>> +
>> +#endif
> 
> .
> 




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