From stefan.wahren at i2se.com  Mon Apr  2 13:27:12 2018
From: stefan.wahren at i2se.com (Stefan Wahren)
Date: Mon, 2 Apr 2018 22:27:12 +0200 (CEST)
Subject: [PATCH] usb: core: phy: Fix usb_phy_roothub_add_phy if
 GENERIC_PHY=n
In-Reply-To: <CAFBinCBX-tZpEexdv-muR9cEzFM3aLfFbeUGXo+xx4QYuiyT2A@mail.gmail.com>
References: <1522524508-4670-1-git-send-email-stefan.wahren@i2se.com>
 <CAFBinCBX-tZpEexdv-muR9cEzFM3aLfFbeUGXo+xx4QYuiyT2A@mail.gmail.com>
Message-ID: <1793237046.74634.1522700832210@email.1und1.de>

Hi Martin,

> Martin Blumenstingl <martin.blumenstingl at googlemail.com> hat am 31. M?rz 2018 um 22:12 geschrieben:
> 
> 
> Hello Stefan,
> 
> On Sat, Mar 31, 2018 at 9:28 PM, Stefan Wahren <stefan.wahren at i2se.com> wrote:
> > If the generic PHY support is disabled the stub of devm_of_phy_get_by_index
> > returns ENOSYS. This corner case isn't handled properly by
> > usb_phy_roothub_add_phy and at least breaks USB support on Raspberry Pi
> > (bcm2835_defconfig):
> >
> >     dwc2 20980000.usb: dwc2_hcd_init() FAILED, returning -38
> >     dwc2: probe of 20980000.usb failed with error -38
> thank you for reporting and proposing a fix!
> 
> > Fixes: 07dbff0ddbd8 ("usb: core: add a wrapper for the USB PHYs on the HCD")
> > Signed-off-by: Stefan Wahren <stefan.wahren at i2se.com>
> > ---
> >  drivers/usb/core/phy.c | 2 +-
> >  1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git a/drivers/usb/core/phy.c b/drivers/usb/core/phy.c
> > index 09b7c43..c89e9be 100644
> > --- a/drivers/usb/core/phy.c
> > +++ b/drivers/usb/core/phy.c
> > @@ -39,7 +39,7 @@ static int usb_phy_roothub_add_phy(struct device *dev, int index,
> >         struct phy *phy = devm_of_phy_get_by_index(dev, dev->of_node, index);
> >
> >         if (IS_ERR_OR_NULL(phy)) {
> > -               if (!phy || PTR_ERR(phy) == -ENODEV)
> > +               if (!phy || PTR_ERR(phy) == -ENODEV || PTR_ERR(phy) == -ENOSYS)
> >                         return 0;
> >                 else
> >                         return PTR_ERR(phy);
> > --
> > 2.7.4
> I have three patches pending, one of them (the patch from [1]) touches
> the same function:
> - "usb: core: phy: fix return value of usb_phy_roothub_exit()" [0]
> - "usb: core: split usb_phy_roothub_{init, alloc}" [1]
> - "usb: core: use phy_exit during suspend if wake up is not supported" [2]
> 
> maybe we should make it more explicit that the whole code is only
> useful if CONFIG_GENERIC_PHY is enabled
> what do you think about adding the following two lines at the
> beginning of usb_phy_roothub_alloc (after patch [1] is applied, before
> this function was basically called usb_phy_roothub_init)
>     if (!IS_ENABLED(CONFIG_GENERIC_PHY))
>         return NULL;
> 
> this should even allow the compiler to optimize away some unused code

sounds reasonable to me.

Regards
Stefan

> 
> 
> Regards
> Martin
> 
> 
> [0] https://patchwork.kernel.org/patch/10306053/
> [1] https://patchwork.kernel.org/patch/10311701/
> [2] https://patchwork.kernel.org/patch/10311703/


From hverkuil at xs4all.nl  Tue Apr  3 01:27:01 2018
From: hverkuil at xs4all.nl (Hans Verkuil)
Date: Tue, 3 Apr 2018 10:27:01 +0200
Subject: [PATCHv2 1/3] dt-bindings: display: dw_hdmi.txt: add cec-disable
 property
In-Reply-To: <20180326072830.iphtbw5mkeciv4kj@rob-hp-laptop>
References: <20180323125915.13986-1-hverkuil@xs4all.nl>
 <20180323125915.13986-2-hverkuil@xs4all.nl>
 <20180326072830.iphtbw5mkeciv4kj@rob-hp-laptop>
Message-ID: <05e7ade1-89be-0f0f-18a5-88ff0310a70b@xs4all.nl>

On 27/03/18 00:25, Rob Herring wrote:
> On Fri, Mar 23, 2018 at 01:59:13PM +0100, Hans Verkuil wrote:
>> From: Hans Verkuil <hans.verkuil at cisco.com>
>>
>> Some boards have both a DesignWare and their own CEC controller.
>> The CEC pin is only hooked up to their own CEC controller and not
>> to the DW controller.
>>
>> Add the cec-disable property to disable the DW CEC controller.
>>
>> This particular situation happens on Amlogic boards that have their
>> own meson CEC controller.
> 
> Seems like we could avoid this by describing how the CEC line is hooked 
> up which could be needed for other reasons.

So there are three situations:

1) The cec pin is connected to the DW HDMI TX. That's already supported.
2) The cec pin is not connected at all, but the CEC IP is instantiated.
   We need the cec-disable property for that. This simply states that the
   CEC pin is not connected.
3) The cec pin is connected to an HDMI RX. We do not support this at the
   moment. If we want to support this, then we need a 'hdmi-rx' phandle
   that points to the HDMI receiver that the CEC pin is associated with.
   This will be similar to the already existing 'hdmi-phandle' property
   used to associate a CEC driver with an HDMI transmitter. In hindsight
   it would have been better if 'hdmi-phandle' was named 'hdmi-tx' :-(

I can make a binding proposal for 3, but I have no hardware to test it,
so I think it is better to add this only when someone has hardware. It
will require quite a few changes to the driver and likely also the CEC core.

Regards,

	Hans

> 
>>
>> Signed-off-by: Hans Verkuil <hans.verkuil at cisco.com>
>> Acked-by: Neil Armstrong <narmstrong at baylibre.com>
>> ---
>>  Documentation/devicetree/bindings/display/bridge/dw_hdmi.txt | 3 +++
>>  1 file changed, 3 insertions(+)



From narmstrong at baylibre.com  Tue Apr  3 02:40:49 2018
From: narmstrong at baylibre.com (Neil Armstrong)
Date: Tue,  3 Apr 2018 11:40:49 +0200
Subject: [PATCH v2 u-boot 0/2] reset: Add get/assert/deassert/release for bulk
 of reset signals
Message-ID: <1522748451-21209-1-git-send-email-narmstrong@baylibre.com>

This patch adds a "bulk" API to the reset API in order to get/deassert/
assert/release a group of reset signals associated with a device.

This bulk API will avoid adding a copy of the same code to manage
a group of reset signals in drivers.

This serie and the "clk bulk" serie is necessary and suggested by Marek Vasut
for the "Add USB Support for Amlogic Meson GXL SoCs" to avoid adding the same
code to manage a bulk of clocks and resets in another driver.
I will push a RFC code to update the other drivers having a similar
code pattern when these patches are merged.

The second patch adds the bulk reset API tests for the sandbox test suite.

Changes since v1 :
 - Add sandbox tests

Neil Armstrong (2):
  reset: Add get/assert/deassert/release for bulk of reset signals
  reset: add sandbox test for bulk API

 arch/sandbox/include/asm/reset.h   |  4 ++
 drivers/reset/reset-uclass.c       | 60 +++++++++++++++++++++++
 drivers/reset/sandbox-reset-test.c | 29 +++++++++++
 drivers/reset/sandbox-reset.c      |  2 +-
 include/reset.h                    | 99 ++++++++++++++++++++++++++++++++++++++
 test/dm/reset.c                    | 33 +++++++++++++
 6 files changed, 226 insertions(+), 1 deletion(-)

-- 
2.7.4



From narmstrong at baylibre.com  Tue Apr  3 02:40:51 2018
From: narmstrong at baylibre.com (Neil Armstrong)
Date: Tue,  3 Apr 2018 11:40:51 +0200
Subject: [PATCH v2 u-boot 2/2] reset: add sandbox test for bulk API
In-Reply-To: <1522748451-21209-1-git-send-email-narmstrong@baylibre.com>
References: <1522748451-21209-1-git-send-email-narmstrong@baylibre.com>
Message-ID: <1522748451-21209-3-git-send-email-narmstrong@baylibre.com>

This patch adds the bulk reset API tests for the sandbox test suite.

Unlike the main test, it also check the "other" reset signal using the bulk API
and checks if the resets are correctly asserted/deasserted.

To allow the bulk API to work, and avoid changing the DT, the number of resets
of the sandbox reset controller has been bumped to 101 for the "other" reset
line to be valid.

Signed-off-by: Neil Armstrong <narmstrong at baylibre.com>
---
 arch/sandbox/include/asm/reset.h   |  4 ++++
 drivers/reset/sandbox-reset-test.c | 29 +++++++++++++++++++++++++++++
 drivers/reset/sandbox-reset.c      |  2 +-
 test/dm/reset.c                    | 33 +++++++++++++++++++++++++++++++++
 4 files changed, 67 insertions(+), 1 deletion(-)

diff --git a/arch/sandbox/include/asm/reset.h b/arch/sandbox/include/asm/reset.h
index 7146aa5..0cd7702 100644
--- a/arch/sandbox/include/asm/reset.h
+++ b/arch/sandbox/include/asm/reset.h
@@ -14,8 +14,12 @@ struct udevice;
 int sandbox_reset_query(struct udevice *dev, unsigned long id);
 
 int sandbox_reset_test_get(struct udevice *dev);
+int sandbox_reset_test_get_bulk(struct udevice *dev);
 int sandbox_reset_test_assert(struct udevice *dev);
+int sandbox_reset_test_assert_bulk(struct udevice *dev);
 int sandbox_reset_test_deassert(struct udevice *dev);
+int sandbox_reset_test_deassert_bulk(struct udevice *dev);
 int sandbox_reset_test_free(struct udevice *dev);
+int sandbox_reset_test_release_bulk(struct udevice *dev);
 
 #endif
diff --git a/drivers/reset/sandbox-reset-test.c b/drivers/reset/sandbox-reset-test.c
index e37d6c9..f0ceaa0 100644
--- a/drivers/reset/sandbox-reset-test.c
+++ b/drivers/reset/sandbox-reset-test.c
@@ -12,6 +12,7 @@
 
 struct sandbox_reset_test {
 	struct reset_ctl ctl;
+	struct reset_ctl_bulk bulk;
 };
 
 int sandbox_reset_test_get(struct udevice *dev)
@@ -21,6 +22,13 @@ int sandbox_reset_test_get(struct udevice *dev)
 	return reset_get_by_name(dev, "test", &sbrt->ctl);
 }
 
+int sandbox_reset_test_get_bulk(struct udevice *dev)
+{
+	struct sandbox_reset_test *sbrt = dev_get_priv(dev);
+
+	return reset_get_bulk(dev, &sbrt->bulk);
+}
+
 int sandbox_reset_test_assert(struct udevice *dev)
 {
 	struct sandbox_reset_test *sbrt = dev_get_priv(dev);
@@ -28,6 +36,13 @@ int sandbox_reset_test_assert(struct udevice *dev)
 	return reset_assert(&sbrt->ctl);
 }
 
+int sandbox_reset_test_assert_bulk(struct udevice *dev)
+{
+	struct sandbox_reset_test *sbrt = dev_get_priv(dev);
+
+	return reset_assert_bulk(&sbrt->bulk);
+}
+
 int sandbox_reset_test_deassert(struct udevice *dev)
 {
 	struct sandbox_reset_test *sbrt = dev_get_priv(dev);
@@ -35,6 +50,13 @@ int sandbox_reset_test_deassert(struct udevice *dev)
 	return reset_deassert(&sbrt->ctl);
 }
 
+int sandbox_reset_test_deassert_bulk(struct udevice *dev)
+{
+	struct sandbox_reset_test *sbrt = dev_get_priv(dev);
+
+	return reset_deassert_bulk(&sbrt->bulk);
+}
+
 int sandbox_reset_test_free(struct udevice *dev)
 {
 	struct sandbox_reset_test *sbrt = dev_get_priv(dev);
@@ -42,6 +64,13 @@ int sandbox_reset_test_free(struct udevice *dev)
 	return reset_free(&sbrt->ctl);
 }
 
+int sandbox_reset_test_release_bulk(struct udevice *dev)
+{
+	struct sandbox_reset_test *sbrt = dev_get_priv(dev);
+
+	return reset_release_bulk(&sbrt->bulk);
+}
+
 static const struct udevice_id sandbox_reset_test_ids[] = {
 	{ .compatible = "sandbox,reset-ctl-test" },
 	{ }
diff --git a/drivers/reset/sandbox-reset.c b/drivers/reset/sandbox-reset.c
index 4258af5..c310749 100644
--- a/drivers/reset/sandbox-reset.c
+++ b/drivers/reset/sandbox-reset.c
@@ -10,7 +10,7 @@
 #include <asm/io.h>
 #include <asm/reset.h>
 
-#define SANDBOX_RESET_SIGNALS 3
+#define SANDBOX_RESET_SIGNALS 101
 
 struct sandbox_reset_signal {
 	bool asserted;
diff --git a/test/dm/reset.c b/test/dm/reset.c
index 0ae8031..8dc0023 100644
--- a/test/dm/reset.c
+++ b/test/dm/reset.c
@@ -13,6 +13,9 @@
 /* This must match the specifier for mbox-names="test" in the DT node */
 #define TEST_RESET_ID 2
 
+/* This is the other reset phandle specifier handled by bulk */
+#define OTHER_RESET_ID 2
+
 static int dm_test_reset(struct unit_test_state *uts)
 {
 	struct udevice *dev_reset;
@@ -37,3 +40,33 @@ static int dm_test_reset(struct unit_test_state *uts)
 	return 0;
 }
 DM_TEST(dm_test_reset, DM_TESTF_SCAN_FDT);
+
+static int dm_test_reset_bulk(struct unit_test_state *uts)
+{
+	struct udevice *dev_reset;
+	struct udevice *dev_test;
+
+	ut_assertok(uclass_get_device_by_name(UCLASS_RESET, "reset-ctl",
+					      &dev_reset));
+	ut_asserteq(0, sandbox_reset_query(dev_reset, TEST_RESET_ID));
+	ut_asserteq(0, sandbox_reset_query(dev_reset, OTHER_RESET_ID));
+
+	ut_assertok(uclass_get_device_by_name(UCLASS_MISC, "reset-ctl-test",
+					      &dev_test));
+	ut_assertok(sandbox_reset_test_get_bulk(dev_test));
+
+	ut_assertok(sandbox_reset_test_assert_bulk(dev_test));
+	ut_asserteq(1, sandbox_reset_query(dev_reset, TEST_RESET_ID));
+	ut_asserteq(1, sandbox_reset_query(dev_reset, OTHER_RESET_ID));
+
+	ut_assertok(sandbox_reset_test_deassert_bulk(dev_test));
+	ut_asserteq(0, sandbox_reset_query(dev_reset, TEST_RESET_ID));
+	ut_asserteq(0, sandbox_reset_query(dev_reset, OTHER_RESET_ID));
+
+	ut_assertok(sandbox_reset_test_release_bulk(dev_test));
+	ut_asserteq(1, sandbox_reset_query(dev_reset, TEST_RESET_ID));
+	ut_asserteq(1, sandbox_reset_query(dev_reset, OTHER_RESET_ID));
+
+	return 0;
+}
+DM_TEST(dm_test_reset_bulk, DM_TESTF_SCAN_FDT);
-- 
2.7.4



From narmstrong at baylibre.com  Tue Apr  3 02:40:50 2018
From: narmstrong at baylibre.com (Neil Armstrong)
Date: Tue,  3 Apr 2018 11:40:50 +0200
Subject: [PATCH v2 u-boot 1/2] reset: Add get/assert/deassert/release for bulk
 of reset signals
In-Reply-To: <1522748451-21209-1-git-send-email-narmstrong@baylibre.com>
References: <1522748451-21209-1-git-send-email-narmstrong@baylibre.com>
Message-ID: <1522748451-21209-2-git-send-email-narmstrong@baylibre.com>

This patch adds a "bulk" API to the reset API in order to get/deassert/
assert/release a group of reset signals associated with a device.

This bulk API will avoid adding a copy of the same code to manage
a group of reset signals in drivers.

Signed-off-by: Neil Armstrong <narmstrong at baylibre.com>
---
 drivers/reset/reset-uclass.c | 60 +++++++++++++++++++++++++++
 include/reset.h              | 99 ++++++++++++++++++++++++++++++++++++++++++++
 2 files changed, 159 insertions(+)

diff --git a/drivers/reset/reset-uclass.c b/drivers/reset/reset-uclass.c
index 307a297..9a5c9c9 100644
--- a/drivers/reset/reset-uclass.c
+++ b/drivers/reset/reset-uclass.c
@@ -81,6 +81,40 @@ int reset_get_by_index(struct udevice *dev, int index,
 	return 0;
 }
 
+int reset_get_bulk(struct udevice *dev, struct reset_ctl_bulk *bulk)
+{
+	int i, ret, err, count;
+	
+	bulk->count = 0;
+
+	count = dev_count_phandle_with_args(dev, "resets", "#reset-cells");
+	if (!count)
+		return 0;
+
+	bulk->resets = devm_kcalloc(dev, count, sizeof(struct reset_ctl),
+				    GFP_KERNEL);
+	if (!bulk->resets)
+		return -ENOMEM;
+
+	for (i = 0; i < count; i++) {
+		ret = reset_get_by_index(dev, i, &bulk->resets[i]);
+		if (ret < 0)
+			goto bulk_get_err;
+
+		++bulk->count;
+	}
+
+	return 0;
+
+bulk_get_err:
+	err = reset_release_all(bulk->resets, bulk->count);
+	if (err)
+		debug("%s: could release all resets for %p\n",
+		      __func__, dev);
+
+	return ret;
+}
+
 int reset_get_by_name(struct udevice *dev, const char *name,
 		     struct reset_ctl *reset_ctl)
 {
@@ -126,6 +160,19 @@ int reset_assert(struct reset_ctl *reset_ctl)
 	return ops->rst_assert(reset_ctl);
 }
 
+int reset_assert_bulk(struct reset_ctl_bulk *bulk)
+{
+	int i, ret;
+
+	for (i = 0; i < bulk->count; i++) {
+		ret = reset_assert(&bulk->resets[i]);
+		if (ret < 0)
+			return ret;
+	}
+
+	return 0;
+}
+
 int reset_deassert(struct reset_ctl *reset_ctl)
 {
 	struct reset_ops *ops = reset_dev_ops(reset_ctl->dev);
@@ -135,6 +182,19 @@ int reset_deassert(struct reset_ctl *reset_ctl)
 	return ops->rst_deassert(reset_ctl);
 }
 
+int reset_deassert_bulk(struct reset_ctl_bulk *bulk)
+{
+	int i, ret;
+
+	for (i = 0; i < bulk->count; i++) {
+		ret = reset_deassert(&bulk->resets[i]);
+		if (ret < 0)
+			return ret;
+	}
+
+	return 0;
+}
+
 int reset_release_all(struct reset_ctl *reset_ctl, int count)
 {
 	int i, ret;
diff --git a/include/reset.h b/include/reset.h
index 7185ade..d38f176 100644
--- a/include/reset.h
+++ b/include/reset.h
@@ -60,6 +60,24 @@ struct reset_ctl {
 	unsigned long id;
 };
 
+/**
+ * struct reset_ctl_bulk - A handle to (allowing control of) a bulk of reset
+ * signals.
+ *
+ * Clients provide storage for the reset control bulk. The content of the
+ * structure is managed solely by the reset API. A reset control bulk struct is
+ * initialized by "get"ing the reset control bulk struct.
+ * The reset control bulk struct is passed to all other bulk reset APIs to apply
+ * the API to all the reset signals in the bulk struct.
+ *
+ * @resets: An array of reset signal handles handles.
+ * @count: The number of reset signal handles in the reset array.
+ */
+struct reset_ctl_bulk {
+	struct reset_ctl *resets;
+	unsigned int count;
+};
+
 #ifdef CONFIG_DM_RESET
 /**
  * reset_get_by_index - Get/request a reset signal by integer index.
@@ -81,6 +99,22 @@ int reset_get_by_index(struct udevice *dev, int index,
 		       struct reset_ctl *reset_ctl);
 
 /**
+ * reset_get_bulk - Get/request all reset signals of a device.
+ *
+ * This looks up and requests all reset signals of the client device; each
+ * device is assumed to have n reset signals associated with it somehow,
+ * and this function finds and requests all of them in a separate structure.
+ * The mapping of client device reset signals indices to provider reset signals
+ * may be via device-tree properties, board-provided mapping tables, or some
+ * other mechanism.
+ *
+ * @dev:	The client device.
+ * @bulk	A pointer to a reset control bulk struct to initialize.
+ * @return 0 if OK, or a negative error code.
+ */
+int reset_get_bulk(struct udevice *dev, struct reset_ctl_bulk *bulk);
+
+/**
  * reset_get_by_name - Get/request a reset signal by name.
  *
  * This looks up and requests a reset signal. The name is relative to the
@@ -132,6 +166,21 @@ int reset_free(struct reset_ctl *reset_ctl);
 int reset_assert(struct reset_ctl *reset_ctl);
 
 /**
+ * reset_assert_bulk - Assert all reset signals in a reset control bulk struct.
+ *
+ * This function will assert the specified reset signals in a reset control
+ * bulk struct, thus resetting the affected HW module(s). Depending on the
+ * reset controller hardware, the reset signals will either stay asserted
+ * until reset_deassert_bulk() is called, or the hardware may autonomously
+ * clear the reset signals itself.
+ *
+ * @bulk:	A reset control bulk struct that was previously successfully
+ *		requested by reset_get_bulk().
+ * @return 0 if OK, or a negative error code.
+ */
+int reset_assert_bulk(struct reset_ctl_bulk *bulk);
+
+/**
  * reset_deassert - Deassert a reset signal.
  *
  * This function will deassert the specified reset signal, thus releasing the
@@ -145,6 +194,20 @@ int reset_assert(struct reset_ctl *reset_ctl);
 int reset_deassert(struct reset_ctl *reset_ctl);
 
 /**
+ * reset_deassert_bulk - Deassert all reset signals in a reset control bulk
+ * struct.
+ *
+ * This function will deassert the specified reset signals in a reset control
+ * bulk struct, thus releasing the affected HW modules() from reset, and
+ * allowing them to continue normal operation.
+ *
+ * @bulk:	A reset control bulk struct that was previously successfully
+ *		requested by reset_get_bulk().
+ * @return 0 if OK, or a negative error code.
+ */
+int reset_deassert_bulk(struct reset_ctl_bulk *bulk);
+
+/**
  * reset_release_all - Assert/Free an array of previously requested resets.
  *
  * For each reset contained in the reset array, this function will check if
@@ -156,6 +219,23 @@ int reset_deassert(struct reset_ctl *reset_ctl);
  * @return 0 if OK, or a negative error code.
  */
 int reset_release_all(struct reset_ctl *reset_ctl, int count);
+
+/**
+ * reset_release_bulk - Assert/Free an array of previously requested reset
+ * signals in a reset control bulk struct.
+ *
+ * For each reset contained in the reset control bulk struct, this function
+ * will check if reset has been previously requested and then will assert
+ * and free it.
+ *
+ * @bulk:	A reset control bulk struct that was previously successfully
+ *		requested by reset_get_bulk().
+ * @return 0 if OK, or a negative error code.
+ */
+static inline int reset_release_bulk(struct reset_ctl_bulk *bulk)
+{
+	return reset_release_all(bulk->resets, bulk->count);
+}
 #else
 static inline int reset_get_by_index(struct udevice *dev, int index,
 				     struct reset_ctl *reset_ctl)
@@ -163,6 +243,11 @@ static inline int reset_get_by_index(struct udevice *dev, int index,
 	return -ENOTSUPP;
 }
 
+static inline int reset_get_bulk(struct udevice *dev, struct clk_bulk *bulk)
+{
+	return -ENOTSUPP;
+}
+
 static inline int reset_get_by_name(struct udevice *dev, const char *name,
 				    struct reset_ctl *reset_ctl)
 {
@@ -179,16 +264,30 @@ static inline int reset_assert(struct reset_ctl *reset_ctl)
 	return 0;
 }
 
+static inline int reset_assert_bulk(struct reset_ctl_bulk *bulk)
+{
+	return 0;
+}
+
 static inline int reset_deassert(struct reset_ctl *reset_ctl)
 {
 	return 0;
 }
 
+static inline int reset_deassert_bulk(struct reset_ctl_bulk *bulk)
+{
+	return 0;
+}
+
 static inline int reset_release_all(struct reset_ctl *reset_ctl, int count)
 {
 	return 0;
 }
 
+static inline int reset_release_bulk(struct clk_bulk *bulk)
+{
+	return 0;
+}
 #endif
 
 #endif
-- 
2.7.4



From narmstrong at baylibre.com  Tue Apr  3 02:44:17 2018
From: narmstrong at baylibre.com (Neil Armstrong)
Date: Tue,  3 Apr 2018 11:44:17 +0200
Subject: [PATCH v2 u-boot 0/2] clk: Add get/enable/disable/release for a bulk
 of clocks
Message-ID: <1522748659-21622-1-git-send-email-narmstrong@baylibre.com>

This patch adds a "bulk" API to the clock API in order to get/enable/disable
/release a group of clocks associated with a device.

This bulk API will avoid adding a copy of the same code to manage
a group of clocks in drivers.

This serie and the "reset bulk" serie is necessary and suggested by Marek Vasut
for the "Add USB Support for Amlogic Meson GXL SoCs" to avoid adding the same
code to manage a bulk of clocks and resets in another driver.
I will push a RFC code to update the other drivers having a similar
code pattern when these patches are merged.

The second patch adds the bulk clock API tests for the sandbox test suite.

Changes since v1 :
 - Add sandbox tests

Neil Armstrong (2):
  clk: Add get/enable/disable/release for a bulk of clocks
  clk: add sandbox test for bulk API

 arch/sandbox/include/asm/clk.h | 32 +++++++++++++++++++
 drivers/clk/clk-uclass.c       | 59 ++++++++++++++++++++++++++++++++++
 drivers/clk/clk_sandbox_test.c | 29 +++++++++++++++++
 include/clk.h                  | 72 +++++++++++++++++++++++++++++++++++++++++-
 test/dm/clk.c                  | 38 ++++++++++++++++++++++
 5 files changed, 229 insertions(+), 1 deletion(-)

-- 
2.7.4



From narmstrong at baylibre.com  Tue Apr  3 02:44:18 2018
From: narmstrong at baylibre.com (Neil Armstrong)
Date: Tue,  3 Apr 2018 11:44:18 +0200
Subject: [PATCH v2 u-boot 1/2] clk: Add get/enable/disable/release for a bulk
 of clocks
In-Reply-To: <1522748659-21622-1-git-send-email-narmstrong@baylibre.com>
References: <1522748659-21622-1-git-send-email-narmstrong@baylibre.com>
Message-ID: <1522748659-21622-2-git-send-email-narmstrong@baylibre.com>

This patch adds a "bulk" API to the clock API in order to get/enable/disable
/release a group of clocks associated with a device.

This bulk API will avoid adding a copy of the same code to manage
a group of clocks in drivers.

Signed-off-by: Neil Armstrong <narmstrong at baylibre.com>
---
 drivers/clk/clk-uclass.c | 59 +++++++++++++++++++++++++++++++++++++++
 include/clk.h            | 72 +++++++++++++++++++++++++++++++++++++++++++++++-
 2 files changed, 130 insertions(+), 1 deletion(-)

diff --git a/drivers/clk/clk-uclass.c b/drivers/clk/clk-uclass.c
index ad76379..6e99b3b 100644
--- a/drivers/clk/clk-uclass.c
+++ b/drivers/clk/clk-uclass.c
@@ -104,6 +104,39 @@ int clk_get_by_index(struct udevice *dev, int index, struct clk *clk)
 	return clk_get_by_indexed_prop(dev, "clocks", index, clk);
 }
 
+int clk_get_bulk(struct udevice *dev, struct clk_bulk *bulk)
+{
+	int i, ret, err, count;
+	
+	bulk->count = 0;
+
+	count = dev_count_phandle_with_args(dev, "clocks", "#clock-cells");
+	if (!count)
+		return 0;
+
+	bulk->clks = devm_kcalloc(dev, count, sizeof(struct clk), GFP_KERNEL);
+	if (!bulk->clks)
+		return -ENOMEM;
+
+	for (i = 0; i < count; i++) {
+		ret = clk_get_by_index(dev, i, &bulk->clks[i]);
+		if (ret < 0)
+			goto bulk_get_err;
+
+		++bulk->count;
+	}
+
+	return 0;
+
+bulk_get_err:
+	err = clk_release_all(bulk->clks, bulk->count);
+	if (err)
+		debug("%s: could release all clocks for %p\n",
+		      __func__, dev);
+
+	return ret;
+}
+
 static int clk_set_default_parents(struct udevice *dev)
 {
 	struct clk clk, parent_clk;
@@ -336,6 +369,19 @@ int clk_enable(struct clk *clk)
 	return ops->enable(clk);
 }
 
+int clk_enable_bulk(struct clk_bulk *bulk)
+{
+	int i, ret;
+
+	for (i = 0; i < bulk->count; i++) {
+		ret = clk_enable(&bulk->clks[i]);
+		if (ret < 0 && ret != -ENOSYS)
+			return ret;
+	}
+
+	return 0;
+}
+
 int clk_disable(struct clk *clk)
 {
 	const struct clk_ops *ops = clk_dev_ops(clk->dev);
@@ -348,6 +394,19 @@ int clk_disable(struct clk *clk)
 	return ops->disable(clk);
 }
 
+int clk_disable_bulk(struct clk_bulk *bulk)
+{
+	int i, ret;
+
+	for (i = 0; i < bulk->count; i++) {
+		ret = clk_disable(&bulk->clks[i]);
+		if (ret < 0 && ret != -ENOSYS)
+			return ret;
+	}
+
+	return 0;
+}
+
 UCLASS_DRIVER(clk) = {
 	.id		= UCLASS_CLK,
 	.name		= "clk",
diff --git a/include/clk.h b/include/clk.h
index a7d95d3..b3a9fce 100644
--- a/include/clk.h
+++ b/include/clk.h
@@ -60,6 +60,23 @@ struct clk {
 	unsigned long id;
 };
 
+/**
+ * struct clk_bulk - A handle to (allowing control of) a bulk of clocks.
+ *
+ * Clients provide storage for the clock bulk. The content of the structure is
+ * managed solely by the clock API. A clock bulk struct is
+ * initialized by "get"ing the clock bulk struct.
+ * The clock bulk struct is passed to all other bulk clock APIs to apply
+ * the API to all the clock in the bulk struct.
+ *
+ * @clks: An array of clock handles.
+ * @count: The number of clock handles in the clks array.
+ */
+struct clk_bulk {
+	struct clk *clks;
+	unsigned int count;
+};
+
 #if CONFIG_IS_ENABLED(OF_CONTROL) && CONFIG_IS_ENABLED(CLK)
 struct phandle_1_arg;
 int clk_get_by_index_platdata(struct udevice *dev, int index,
@@ -83,6 +100,21 @@ int clk_get_by_index_platdata(struct udevice *dev, int index,
 int clk_get_by_index(struct udevice *dev, int index, struct clk *clk);
 
 /**
+ * clock_get_bulk - Get/request all clocks of a device.
+ *
+ * This looks up and requests all clocks of the client device; each device is
+ * assumed to have n clocks associated with it somehow, and this function finds
+ * and requests all of them in a separate structure. The mapping of client
+ * device clock indices to provider clocks may be via device-tree properties,
+ * board-provided mapping tables, or some other mechanism.
+ *
+ * @dev:	The client device.
+ * @bulk	A pointer to a clock bulk struct to initialize.
+ * @return 0 if OK, or a negative error code.
+ */
+int clk_get_bulk(struct udevice *dev, struct clk_bulk *bulk);
+
+/**
  * clock_get_by_name - Get/request a clock by name.
  *
  * This looks up and requests a clock. The name is relative to the client
@@ -120,6 +152,11 @@ static inline int clk_get_by_index(struct udevice *dev, int index,
 	return -ENOSYS;
 }
 
+static inline int clk_get_bulk(struct udevice *dev, struct clk_bulk *bulk)
+{
+	return -ENOSYS;
+}
+
 static inline int clk_get_by_name(struct udevice *dev, const char *name,
 			   struct clk *clk)
 {
@@ -130,7 +167,6 @@ static inline int clk_release_all(struct clk *clk, int count)
 {
 	return -ENOSYS;
 }
-
 #endif
 
 #if (CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)) && \
@@ -151,6 +187,22 @@ static inline int clk_set_defaults(struct udevice *dev)
 #endif
 
 /**
+ * clk_release_bulk() - Disable (turn off)/Free an array of previously
+ * requested clocks in a clock bulk struct.
+ *
+ * For each clock contained in the clock bulk struct, this function will check
+ * if clock has been previously requested and then will disable and free it.
+ *
+ * @clk:	A clock bulk struct that was previously successfully
+ *		requested by clk_get_bulk().
+ * @return zero on success, or -ve error code.
+ */
+static inline int clk_release_bulk(struct clk_bulk *bulk)
+{
+	return clk_release_all(bulk->clks, bulk->count);
+}
+
+/**
  * clk_request - Request a clock by provider-specific ID.
  *
  * This requests a clock using a provider-specific ID. Generally, this function
@@ -215,6 +267,15 @@ int clk_set_parent(struct clk *clk, struct clk *parent);
 int clk_enable(struct clk *clk);
 
 /**
+ * clk_enable_bulk() - Enable (turn on) all clocks in a clock bulk struct.
+ *
+ * @bulk:	A clock bulk struct that was previously successfully requested
+ *		by clk_get_bulk().
+ * @return zero on success, or -ve error code.
+ */
+int clk_enable_bulk(struct clk_bulk *bulk);
+
+/**
  * clk_disable() - Disable (turn off) a clock.
  *
  * @clk:	A clock struct that was previously successfully requested by
@@ -223,6 +284,15 @@ int clk_enable(struct clk *clk);
  */
 int clk_disable(struct clk *clk);
 
+/**
+ * clk_disable_bulk() - Disable (turn off) all clocks in a clock bulk struct.
+ *
+ * @bulk:	A clock bulk struct that was previously successfully requested
+ *		by clk_get_bulk().
+ * @return zero on success, or -ve error code.
+ */
+int clk_disable_bulk(struct clk_bulk *bulk);
+
 int soc_clk_dump(void);
 
 #endif
-- 
2.7.4



From narmstrong at baylibre.com  Tue Apr  3 02:44:19 2018
From: narmstrong at baylibre.com (Neil Armstrong)
Date: Tue,  3 Apr 2018 11:44:19 +0200
Subject: [PATCH v2 u-boot 2/2] clk: add sandbox test for bulk API
In-Reply-To: <1522748659-21622-1-git-send-email-narmstrong@baylibre.com>
References: <1522748659-21622-1-git-send-email-narmstrong@baylibre.com>
Message-ID: <1522748659-21622-3-git-send-email-narmstrong@baylibre.com>

This patch adds the bulk clock API tests for the sandbox test suite.

It's very similar to the main test but only uses the _bulk() API and
checks if the clocks are correctly enabled/disabled.

Signed-off-by: Neil Armstrong <narmstrong at baylibre.com>
---
 arch/sandbox/include/asm/clk.h | 32 ++++++++++++++++++++++++++++++++
 drivers/clk/clk_sandbox_test.c | 29 +++++++++++++++++++++++++++++
 test/dm/clk.c                  | 38 ++++++++++++++++++++++++++++++++++++++
 3 files changed, 99 insertions(+)

diff --git a/arch/sandbox/include/asm/clk.h b/arch/sandbox/include/asm/clk.h
index 9dc6c81..01b5ba4 100644
--- a/arch/sandbox/include/asm/clk.h
+++ b/arch/sandbox/include/asm/clk.h
@@ -64,6 +64,14 @@ int sandbox_clk_query_enable(struct udevice *dev, int id);
  */
 int sandbox_clk_test_get(struct udevice *dev);
 /**
+ * sandbox_clk_test_get_bulk - Ask the sandbox clock test device to request its
+ * clocks with the bulk clk API.
+ *
+ * @dev:	The sandbox clock test (client) devivce.
+ * @return:	0 if OK, or a negative error code.
+ */
+int sandbox_clk_test_get_bulk(struct udevice *dev);
+/**
  * sandbox_clk_test_get_rate - Ask the sandbox clock test device to query a
  * clock's rate.
  *
@@ -91,6 +99,14 @@ ulong sandbox_clk_test_set_rate(struct udevice *dev, int id, ulong rate);
  */
 int sandbox_clk_test_enable(struct udevice *dev, int id);
 /**
+ * sandbox_clk_test_enable_bulk - Ask the sandbox clock test device to enable
+ * all clocks in it's clock bulk struct.
+ *
+ * @dev:	The sandbox clock test (client) devivce.
+ * @return:	0 if OK, or a negative error code.
+ */
+int sandbox_clk_test_enable_bulk(struct udevice *dev);
+/**
  * sandbox_clk_test_disable - Ask the sandbox clock test device to disable a
  * clock.
  *
@@ -100,6 +116,14 @@ int sandbox_clk_test_enable(struct udevice *dev, int id);
  */
 int sandbox_clk_test_disable(struct udevice *dev, int id);
 /**
+ * sandbox_clk_test_disable_bulk - Ask the sandbox clock test device to disable
+ * all clocks in it's clock bulk struct.
+ *
+ * @dev:	The sandbox clock test (client) devivce.
+ * @return:	0 if OK, or a negative error code.
+ */
+int sandbox_clk_test_disable_bulk(struct udevice *dev);
+/**
  * sandbox_clk_test_free - Ask the sandbox clock test device to free its
  * clocks.
  *
@@ -107,5 +131,13 @@ int sandbox_clk_test_disable(struct udevice *dev, int id);
  * @return:	0 if OK, or a negative error code.
  */
 int sandbox_clk_test_free(struct udevice *dev);
+/**
+ * sandbox_clk_test_release_bulk - Ask the sandbox clock test device to release
+ * all clocks in it's clock bulk struct.
+ *
+ * @dev:	The sandbox clock test (client) devivce.
+ * @return:	0 if OK, or a negative error code.
+ */
+int sandbox_clk_test_release_bulk(struct udevice *dev);
 
 #endif
diff --git a/drivers/clk/clk_sandbox_test.c b/drivers/clk/clk_sandbox_test.c
index 999100d..d089881 100644
--- a/drivers/clk/clk_sandbox_test.c
+++ b/drivers/clk/clk_sandbox_test.c
@@ -11,6 +11,7 @@
 
 struct sandbox_clk_test {
 	struct clk clks[SANDBOX_CLK_TEST_ID_COUNT];
+	struct clk_bulk bulk;
 };
 
 static const char * const sandbox_clk_test_names[] = {
@@ -34,6 +35,13 @@ int sandbox_clk_test_get(struct udevice *dev)
 	return 0;
 }
 
+int sandbox_clk_test_get_bulk(struct udevice *dev)
+{
+	struct sandbox_clk_test *sbct = dev_get_priv(dev);
+
+	return clk_get_bulk(dev, &sbct->bulk);
+}
+
 ulong sandbox_clk_test_get_rate(struct udevice *dev, int id)
 {
 	struct sandbox_clk_test *sbct = dev_get_priv(dev);
@@ -64,6 +72,13 @@ int sandbox_clk_test_enable(struct udevice *dev, int id)
 	return clk_enable(&sbct->clks[id]);
 }
 
+int sandbox_clk_test_enable_bulk(struct udevice *dev)
+{
+	struct sandbox_clk_test *sbct = dev_get_priv(dev);
+
+	return clk_enable_bulk(&sbct->bulk);
+}
+
 int sandbox_clk_test_disable(struct udevice *dev, int id)
 {
 	struct sandbox_clk_test *sbct = dev_get_priv(dev);
@@ -74,6 +89,13 @@ int sandbox_clk_test_disable(struct udevice *dev, int id)
 	return clk_disable(&sbct->clks[id]);
 }
 
+int sandbox_clk_test_disable_bulk(struct udevice *dev)
+{
+	struct sandbox_clk_test *sbct = dev_get_priv(dev);
+
+	return clk_disable_bulk(&sbct->bulk);
+}
+
 int sandbox_clk_test_free(struct udevice *dev)
 {
 	struct sandbox_clk_test *sbct = dev_get_priv(dev);
@@ -88,6 +110,13 @@ int sandbox_clk_test_free(struct udevice *dev)
 	return 0;
 }
 
+int sandbox_clk_test_release_bulk(struct udevice *dev)
+{
+	struct sandbox_clk_test *sbct = dev_get_priv(dev);
+
+	return clk_release_bulk(&sbct->bulk);
+}
+
 static const struct udevice_id sandbox_clk_test_ids[] = {
 	{ .compatible = "sandbox,clk-test" },
 	{ }
diff --git a/test/dm/clk.c b/test/dm/clk.c
index 712a1e6..95716f8 100644
--- a/test/dm/clk.c
+++ b/test/dm/clk.c
@@ -101,3 +101,41 @@ static int dm_test_clk(struct unit_test_state *uts)
 	return 0;
 }
 DM_TEST(dm_test_clk, DM_TESTF_SCAN_FDT);
+
+static int dm_test_clk_bulk(struct unit_test_state *uts)
+{
+	struct udevice *dev_clk, *dev_test;
+	ulong rate;
+
+	ut_assertok(uclass_get_device_by_name(UCLASS_CLK, "clk-sbox",
+					      &dev_clk));
+	ut_assertok(uclass_get_device_by_name(UCLASS_MISC, "clk-test",
+					      &dev_test));
+	ut_assertok(sandbox_clk_test_get_bulk(dev_test));
+
+	ut_asserteq(0, sandbox_clk_query_enable(dev_clk, SANDBOX_CLK_ID_SPI));
+	ut_asserteq(0, sandbox_clk_query_enable(dev_clk, SANDBOX_CLK_ID_I2C));
+
+	/* Fixed clock does not support enable, thus should not fail */
+	ut_assertok(sandbox_clk_test_enable_bulk(dev_test));
+	ut_asserteq(1, sandbox_clk_query_enable(dev_clk, SANDBOX_CLK_ID_SPI));
+	ut_asserteq(1, sandbox_clk_query_enable(dev_clk, SANDBOX_CLK_ID_I2C));
+
+	/* Fixed clock does not support disable, thus should not fail */
+	ut_assertok(sandbox_clk_test_disable_bulk(dev_test));
+	ut_asserteq(0, sandbox_clk_query_enable(dev_clk, SANDBOX_CLK_ID_SPI));
+	ut_asserteq(0, sandbox_clk_query_enable(dev_clk, SANDBOX_CLK_ID_I2C));
+
+	/* Fixed clock does not support enable, thus should not fail */
+	ut_assertok(sandbox_clk_test_enable_bulk(dev_test));
+	ut_asserteq(1, sandbox_clk_query_enable(dev_clk, SANDBOX_CLK_ID_SPI));
+	ut_asserteq(1, sandbox_clk_query_enable(dev_clk, SANDBOX_CLK_ID_I2C));
+
+	/* Fixed clock does not support disable, thus should not fail */
+	ut_assertok(sandbox_clk_test_release_bulk(dev_test));
+	ut_asserteq(0, sandbox_clk_query_enable(dev_clk, SANDBOX_CLK_ID_SPI));
+	ut_asserteq(0, sandbox_clk_query_enable(dev_clk, SANDBOX_CLK_ID_I2C));
+
+	return 0;
+}
+DM_TEST(dm_test_clk_bulk, DM_TESTF_SCAN_FDT);
-- 
2.7.4



From yixun.lan at amlogic.com  Tue Apr  3 03:06:48 2018
From: yixun.lan at amlogic.com (Yixun Lan)
Date: Tue, 3 Apr 2018 18:06:48 +0800
Subject: [PATCH 0/3] mmc: meson-axg: initial support for AXG SoC platform
Message-ID: <20180403100652.41056-1-yixun.lan@amlogic.com>

   The patches series try to enable basic eMMC support in the Meson-AXG platfrom.

   Currently HS200 mode is tested with clock running at 166MHz, since
not all boards are stable to running 200MHz (due to tuning phase error),
we will further improve the tuning phase driver in the future,
but in my opiton, this patch series itself is pretty good to go.

Nan Li (3):
  mmc: dt-bindings: update bindings doc to support Meson-AXG SoC
  mmc: meson-axg: add support for the Meson-AXG platform
  mmc: meson: update doc to support Meson-AXG platform

 .../devicetree/bindings/mmc/amlogic,meson-gx.txt   |  1 +
 drivers/mmc/host/Kconfig                           |  4 +-
 drivers/mmc/host/meson-gx-mmc.c                    | 63 ++++++++++++++++++----
 3 files changed, 55 insertions(+), 13 deletions(-)

-- 
2.16.2



From yixun.lan at amlogic.com  Tue Apr  3 03:06:49 2018
From: yixun.lan at amlogic.com (Yixun Lan)
Date: Tue, 3 Apr 2018 18:06:49 +0800
Subject: [PATCH 1/3] mmc: dt-bindings: update bindings doc to support
 Meson-AXG SoC
In-Reply-To: <20180403100652.41056-1-yixun.lan@amlogic.com>
References: <20180403100652.41056-1-yixun.lan@amlogic.com>
Message-ID: <20180403100652.41056-2-yixun.lan@amlogic.com>

From: Nan Li <nan.li at amlogic.com>

Update the documentation to list support for Meson-AXG SoC explicitly.
The new binding string is necessary since this SoC introduce a few
IP difference comparing to previous old generation.

Signed-off-by: Nan Li <nan.li at amlogic.com>
Signed-off-by: Yixun Lan <yixun.lan at amlogic.com>
---
 Documentation/devicetree/bindings/mmc/amlogic,meson-gx.txt | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/mmc/amlogic,meson-gx.txt b/Documentation/devicetree/bindings/mmc/amlogic,meson-gx.txt
index 50bf611a4d2c..5add8d7d855f 100644
--- a/Documentation/devicetree/bindings/mmc/amlogic,meson-gx.txt
+++ b/Documentation/devicetree/bindings/mmc/amlogic,meson-gx.txt
@@ -12,6 +12,7 @@ Required properties:
   - "amlogic,meson-gxbb-mmc"
   - "amlogic,meson-gxl-mmc"
   - "amlogic,meson-gxm-mmc"
+  - "amlogic,meson-axg-mmc"
 - clocks     : A list of phandle + clock-specifier pairs for the clocks listed in clock-names.
 - clock-names: Should contain the following:
 	"core" - Main peripheral bus clock
-- 
2.16.2



From yixun.lan at amlogic.com  Tue Apr  3 03:06:50 2018
From: yixun.lan at amlogic.com (Yixun Lan)
Date: Tue, 3 Apr 2018 18:06:50 +0800
Subject: [PATCH 2/3] mmc: meson-axg: add support for the Meson-AXG platform
In-Reply-To: <20180403100652.41056-1-yixun.lan@amlogic.com>
References: <20180403100652.41056-1-yixun.lan@amlogic.com>
Message-ID: <20180403100652.41056-3-yixun.lan@amlogic.com>

From: Nan Li <nan.li at amlogic.com>

Introduce the compatible data to cover the register offset & mask
change of the eMMC controller in Amlogic's Meson-AXG SoC.

Signed-off-by: Nan Li <nan.li at amlogic.com>
Signed-off-by: Yixun Lan <yixun.lan at amlogic.com>
---
 drivers/mmc/host/meson-gx-mmc.c | 61 ++++++++++++++++++++++++++++++++++-------
 1 file changed, 51 insertions(+), 10 deletions(-)

diff --git a/drivers/mmc/host/meson-gx-mmc.c b/drivers/mmc/host/meson-gx-mmc.c
index 4f972b879fe6..56c90542ac29 100644
--- a/drivers/mmc/host/meson-gx-mmc.c
+++ b/drivers/mmc/host/meson-gx-mmc.c
@@ -47,15 +47,29 @@
 #define   CLK_CORE_PHASE_MASK GENMASK(9, 8)
 #define   CLK_TX_PHASE_MASK GENMASK(11, 10)
 #define   CLK_RX_PHASE_MASK GENMASK(13, 12)
-#define   CLK_TX_DELAY_MASK GENMASK(19, 16)
-#define   CLK_RX_DELAY_MASK GENMASK(23, 20)
+#define   CLK_V2_TX_DELAY_MASK GENMASK(19, 16)
+#define   CLK_V2_RX_DELAY_MASK GENMASK(23, 20)
+#define   CLK_V2_ALWAYS_ON BIT(24)
+
+#define   CLK_V3_TX_DELAY_MASK GENMASK(21, 16)
+#define   CLK_V3_RX_DELAY_MASK GENMASK(27, 22)
+#define   CLK_V3_ALWAYS_ON BIT(28)
+
 #define   CLK_DELAY_STEP_PS 200
 #define   CLK_PHASE_STEP 30
 #define   CLK_PHASE_POINT_NUM (360 / CLK_PHASE_STEP)
-#define   CLK_ALWAYS_ON BIT(24)
+
+#define   CLK_TX_DELAY_MASK(h)		(h->data->tx_delay_mask)
+#define   CLK_RX_DELAY_MASK(h)		(h->data->rx_delay_mask)
+#define   CLK_ALWAYS_ON(h)		(h->data->always_on)
 
 #define SD_EMMC_DELAY 0x4
 #define SD_EMMC_ADJUST 0x8
+
+#define SD_EMMC_DELAY1 0x4
+#define SD_EMMC_DELAY2 0x8
+#define SD_EMMC_V3_ADJUST 0xc
+
 #define SD_EMMC_CALOUT 0x10
 #define SD_EMMC_START 0x40
 #define   START_DESC_INIT BIT(0)
@@ -122,6 +136,12 @@
 
 #define MUX_CLK_NUM_PARENTS 2
 
+struct meson_mmc_data {
+	unsigned int tx_delay_mask;
+	unsigned int rx_delay_mask;
+	unsigned int always_on;
+};
+
 struct sd_emmc_desc {
 	u32 cmd_cfg;
 	u32 cmd_arg;
@@ -131,6 +151,7 @@ struct sd_emmc_desc {
 
 struct meson_host {
 	struct	device		*dev;
+	struct	meson_mmc_data *data;
 	struct	mmc_host	*mmc;
 	struct	mmc_command	*cmd;
 
@@ -474,7 +495,7 @@ static int meson_mmc_clk_init(struct meson_host *host)
 
 	/* init SD_EMMC_CLOCK to sane defaults w/min clock rate */
 	clk_reg = 0;
-	clk_reg |= CLK_ALWAYS_ON;
+	clk_reg |= CLK_ALWAYS_ON(host);
 	clk_reg |= CLK_DIV_MASK;
 	writel(clk_reg, host->regs + SD_EMMC_CLOCK);
 
@@ -574,7 +595,7 @@ static int meson_mmc_clk_init(struct meson_host *host)
 
 	tx->reg = host->regs + SD_EMMC_CLOCK;
 	tx->phase_mask = CLK_TX_PHASE_MASK;
-	tx->delay_mask = CLK_TX_DELAY_MASK;
+	tx->delay_mask = CLK_TX_DELAY_MASK(host);
 	tx->delay_step_ps = CLK_DELAY_STEP_PS;
 	tx->hw.init = &init;
 
@@ -597,7 +618,7 @@ static int meson_mmc_clk_init(struct meson_host *host)
 
 	rx->reg = host->regs + SD_EMMC_CLOCK;
 	rx->phase_mask = CLK_RX_PHASE_MASK;
-	rx->delay_mask = CLK_RX_DELAY_MASK;
+	rx->delay_mask = CLK_RX_DELAY_MASK(host);
 	rx->delay_step_ps = CLK_DELAY_STEP_PS;
 	rx->hw.init = &init;
 
@@ -1184,6 +1205,13 @@ static int meson_mmc_probe(struct platform_device *pdev)
 		goto free_host;
 	}
 
+	host->data = (struct meson_mmc_data *)
+		of_device_get_match_data(&pdev->dev);
+	if (!host->data) {
+		ret = -EINVAL;
+		goto free_host;
+	}
+
 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 	host->regs = devm_ioremap_resource(&pdev->dev, res);
 	if (IS_ERR(host->regs)) {
@@ -1315,11 +1343,24 @@ static int meson_mmc_remove(struct platform_device *pdev)
 	return 0;
 }
 
+static const struct meson_mmc_data meson_gx_data = {
+	.tx_delay_mask	= CLK_V2_TX_DELAY_MASK,
+	.rx_delay_mask	= CLK_V2_RX_DELAY_MASK,
+	.always_on	= CLK_V2_ALWAYS_ON,
+};
+
+static const struct meson_mmc_data meson_axg_data = {
+	.tx_delay_mask	= CLK_V3_TX_DELAY_MASK,
+	.rx_delay_mask	= CLK_V3_RX_DELAY_MASK,
+	.always_on	= CLK_V3_ALWAYS_ON,
+};
+
 static const struct of_device_id meson_mmc_of_match[] = {
-	{ .compatible = "amlogic,meson-gx-mmc", },
-	{ .compatible = "amlogic,meson-gxbb-mmc", },
-	{ .compatible = "amlogic,meson-gxl-mmc", },
-	{ .compatible = "amlogic,meson-gxm-mmc", },
+	{ .compatible = "amlogic,meson-gx-mmc",		.data = &meson_gx_data },
+	{ .compatible = "amlogic,meson-gxbb-mmc", 	.data = &meson_gx_data },
+	{ .compatible = "amlogic,meson-gxl-mmc",	.data = &meson_gx_data },
+	{ .compatible = "amlogic,meson-gxm-mmc",	.data = &meson_gx_data },
+	{ .compatible = "amlogic,meson-axg-mmc",	.data = &meson_axg_data },
 	{}
 };
 MODULE_DEVICE_TABLE(of, meson_mmc_of_match);
-- 
2.16.2



From yixun.lan at amlogic.com  Tue Apr  3 03:06:51 2018
From: yixun.lan at amlogic.com (Yixun Lan)
Date: Tue, 3 Apr 2018 18:06:51 +0800
Subject: [PATCH 3/3] mmc: meson: update doc to support Meson-AXG platform
In-Reply-To: <20180403100652.41056-1-yixun.lan@amlogic.com>
References: <20180403100652.41056-1-yixun.lan@amlogic.com>
Message-ID: <20180403100652.41056-4-yixun.lan@amlogic.com>

From: Nan Li <nan.li at amlogic.com>

Explicitly update the docomentation to support the Meson-AXG platform.

Signed-off-by: Nan Li <nan.li at amlogic.com>
Signed-off-by: Yixun Lan <yixun.lan at amlogic.com>
---
 drivers/mmc/host/Kconfig        | 4 ++--
 drivers/mmc/host/meson-gx-mmc.c | 2 +-
 2 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/mmc/host/Kconfig b/drivers/mmc/host/Kconfig
index 620c2d90a646..751090d1d94c 100644
--- a/drivers/mmc/host/Kconfig
+++ b/drivers/mmc/host/Kconfig
@@ -345,11 +345,11 @@ config MMC_SDHCI_IPROC
 	  If unsure, say N.
 
 config MMC_MESON_GX
-	tristate "Amlogic S905/GX* SD/MMC Host Controller support"
+	tristate "Amlogic S905/GX*/AXG SD/MMC Host Controller support"
 	depends on ARCH_MESON && MMC
 	help
 	  This selects support for the Amlogic SD/MMC Host Controller
-	  found on the S905/GX* family of SoCs.  This controller is
+	  found on the S905/GX*/AXG family of SoCs.  This controller is
 	  MMC 5.1 compliant and supports SD, eMMC and SDIO interfaces.
 
 	  If you have a controller with this interface, say Y here.
diff --git a/drivers/mmc/host/meson-gx-mmc.c b/drivers/mmc/host/meson-gx-mmc.c
index 56c90542ac29..55bbd67177df 100644
--- a/drivers/mmc/host/meson-gx-mmc.c
+++ b/drivers/mmc/host/meson-gx-mmc.c
@@ -1376,6 +1376,6 @@ static struct platform_driver meson_mmc_driver = {
 
 module_platform_driver(meson_mmc_driver);
 
-MODULE_DESCRIPTION("Amlogic S905*/GX* SD/eMMC driver");
+MODULE_DESCRIPTION("Amlogic S905*/GX*/AXG SD/eMMC driver");
 MODULE_AUTHOR("Kevin Hilman <khilman at baylibre.com>");
 MODULE_LICENSE("GPL v2");
-- 
2.16.2



From yixun.lan at amlogic.com  Tue Apr  3 03:26:51 2018
From: yixun.lan at amlogic.com (Yixun Lan)
Date: Tue, 3 Apr 2018 18:26:51 +0800
Subject: [PATCH] ARM64: dts: meson-axg: enable the eMMC controller
Message-ID: <20180403102651.60340-1-yixun.lan@amlogic.com>

From: Nan Li <nan.li at amlogic.com>

The IP of eMMC controller in AXG is similiar to Meson-GX series.
Here we add the initial support of the HS200 mode with
clock running at 166MHz (to be safe), since we found some eMMC chip
fail to run at 200MHz due to tunning phase error.

Signed-off-by: Nan Li <nan.li at amlogic.com>
Signed-off-by: Yixun Lan <yixun.lan at amlogic.com>

---
Hi Kevin
  Please note this patch actually depend on the eMMC driver here [0].
  Still a few problem to solve, to improve the tuning phase driver to make
the clock running at 200MHz, and to further support the HS400 mode.
Anyway, this patch itself is quite independent.

[0] http://lkml.kernel.org/r/20180403100652.41056-1-yixun.lan at amlogic.com
---
 arch/arm64/boot/dts/amlogic/meson-axg-s400.dts | 58 ++++++++++++++++++
 arch/arm64/boot/dts/amlogic/meson-axg.dtsi     | 81 ++++++++++++++++++++++++++
 2 files changed, 139 insertions(+)

diff --git a/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts b/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts
index 57eedced5a51..f67d4e47e641 100644
--- a/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts
+++ b/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts
@@ -15,6 +15,44 @@
 		serial0 = &uart_AO;
 		serial1 = &uart_A;
 	};
+
+	vddio_boot: regulator-vddio_boot {
+		compatible = "regulator-fixed";
+		regulator-name = "VDDIO_BOOT";
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <1800000>;
+	};
+
+	vddao_3v3: regulator-vddao_3v3 {
+		compatible = "regulator-fixed";
+		regulator-name = "VDDAO_3V3";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+	};
+
+	vddio_ao18: regulator-vddio_ao18 {
+		compatible = "regulator-fixed";
+		regulator-name = "VDDIO_AO18";
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <1800000>;
+	};
+
+	vcc_3v3: regulator-vcc_3v3 {
+		compatible = "regulator-fixed";
+		regulator-name = "VCC_3V3";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+	};
+
+	emmc_pwrseq: emmc-pwrseq {
+		compatible = "mmc-pwrseq-emmc";
+		reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>;
+	};
+
+	sdio_pwrseq: sdio-pwrseq {
+		compatible = "mmc-pwrseq-simple";
+		reset-gpios = <&gpio GPIOX_6 GPIO_ACTIVE_LOW>;
+	};
 };
 
 &ethmac {
@@ -47,3 +85,23 @@
 	pinctrl-0 = <&i2c1_z_pins>;
 	pinctrl-names = "default";
 };
+
+/* emmc storage */
+&sd_emmc_c {
+	status = "okay";
+	pinctrl-0 = <&emmc_pins>;
+	pinctrl-1 = <&emmc_clk_gate_pins>;
+	pinctrl-names = "default", "clk-gate";
+
+	bus-width = <8>;
+	cap-sd-highspeed;
+	cap-mmc-highspeed;
+	max-frequency = <180000000>;
+	non-removable;
+	disable-wp;
+	mmc-ddr-1_8v;
+	mmc-hs200-1_8v;
+
+	vmmc-supply = <&vcc_3v3>;
+	vqmmc-supply = <&vddio_boot>;
+};
diff --git a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
index b58808eb3cc8..52d65643d4b7 100644
--- a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
@@ -113,6 +113,36 @@
 		#size-cells = <2>;
 		ranges;
 
+		apb: apb at ffe00000 {
+			compatible = "simple-bus";
+			reg = <0x0 0xffe00000 0x0 0x200000>;
+			#address-cells = <2>;
+			#size-cells = <2>;
+			ranges = <0x0 0x0 0x0 0xffe00000 0x0 0x200000>;
+
+			sd_emmc_b: sd at 5000 {
+				compatible = "amlogic,meson-axg-mmc";
+				reg = <0x0 0x5000 0x0 0x2000>;
+				interrupts = <GIC_SPI 217 IRQ_TYPE_EDGE_RISING>;
+				status = "disabled";
+				clocks = <&clkc CLKID_SD_EMMC_B>,
+					<&clkc CLKID_SD_EMMC_B_CLK0>,
+					<&clkc CLKID_FCLK_DIV2>;
+				clock-names = "core", "clkin0", "clkin1";
+			};
+
+			sd_emmc_c: mmc at 7000 {
+				compatible = "amlogic,meson-axg-mmc";
+				reg = <0x0 0x7000 0x0 0x2000>;
+				interrupts = <GIC_SPI 218 IRQ_TYPE_EDGE_RISING>;
+				status = "disabled";
+				clocks = <&clkc CLKID_SD_EMMC_C>,
+					<&clkc CLKID_SD_EMMC_C_CLK0>,
+					<&clkc CLKID_FCLK_DIV2>;
+				clock-names = "core", "clkin0", "clkin1";
+			};
+		};
+
 		cbus: bus at ffd00000 {
 			compatible = "simple-bus";
 			reg = <0x0 0xffd00000 0x0 0x25000>;
@@ -309,6 +339,57 @@
 					gpio-ranges = <&pinctrl_periphs 0 0 86>;
 				};
 
+				emmc_pins: emmc {
+					mux {
+						groups = "emmc_nand_d0",
+							"emmc_nand_d1",
+							"emmc_nand_d2",
+							"emmc_nand_d3",
+							"emmc_nand_d4",
+							"emmc_nand_d5",
+							"emmc_nand_d6",
+							"emmc_nand_d7",
+							"emmc_clk",
+							"emmc_cmd",
+							"emmc_ds";
+						function = "emmc";
+					};
+				};
+
+				emmc_clk_gate_pins: emmc_clk_gate {
+					mux {
+						groups = "BOOT_8";
+						function = "gpio_periphs";
+					};
+					cfg-pull-down {
+						pins = "BOOT_8";
+						bias-pull-down;
+					};
+				};
+
+				sdio_pins: sdio {
+					mux {
+						groups = "sdio_d0",
+							"sdio_d1",
+							"sdio_d2",
+							"sdio_d3",
+							"sdio_cmd",
+							"sdio_clk";
+						function = "sdio";
+					};
+				};
+
+				sdio_clk_gate_pins: sdio_clk_gate {
+					mux {
+						groups = "GPIOX_4";
+						function = "gpio_periphs";
+					};
+					cfg-pull-down {
+						pins = "GPIOX_4";
+						bias-pull-down;
+					};
+				};
+
 				eth_rmii_x_pins: eth-x-rmii {
 					mux {
 						groups = "eth_mdio_x",
-- 
2.16.2



From sjg at chromium.org  Tue Apr  3 10:53:24 2018
From: sjg at chromium.org (Simon Glass)
Date: Wed, 4 Apr 2018 01:53:24 +0800
Subject: [PATCH v2 u-boot 2/2] reset: add sandbox test for bulk API
In-Reply-To: <1522748451-21209-3-git-send-email-narmstrong@baylibre.com>
References: <1522748451-21209-1-git-send-email-narmstrong@baylibre.com>
 <1522748451-21209-3-git-send-email-narmstrong@baylibre.com>
Message-ID: <CAPnjgZ0+M8pXpi+YYZReY+hgeXv+XTCDuooxkYYegaXVT_O38w@mail.gmail.com>

On 3 April 2018 at 17:40, Neil Armstrong <narmstrong at baylibre.com> wrote:
> This patch adds the bulk reset API tests for the sandbox test suite.
>
> Unlike the main test, it also check the "other" reset signal using the bulk API
> and checks if the resets are correctly asserted/deasserted.
>
> To allow the bulk API to work, and avoid changing the DT, the number of resets
> of the sandbox reset controller has been bumped to 101 for the "other" reset
> line to be valid.

Does it need to be 101, or would, say, 5 be enough?

>
> Signed-off-by: Neil Armstrong <narmstrong at baylibre.com>
> ---
>  arch/sandbox/include/asm/reset.h   |  4 ++++
>  drivers/reset/sandbox-reset-test.c | 29 +++++++++++++++++++++++++++++
>  drivers/reset/sandbox-reset.c      |  2 +-
>  test/dm/reset.c                    | 33 +++++++++++++++++++++++++++++++++
>  4 files changed, 67 insertions(+), 1 deletion(-)

Reviewed-by: Simon Glass <sjg at chromium.org>


From sjg at chromium.org  Tue Apr  3 10:53:34 2018
From: sjg at chromium.org (Simon Glass)
Date: Wed, 4 Apr 2018 01:53:34 +0800
Subject: [PATCH v2 u-boot 1/2] reset: Add get/assert/deassert/release for
 bulk of reset signals
In-Reply-To: <1522748451-21209-2-git-send-email-narmstrong@baylibre.com>
References: <1522748451-21209-1-git-send-email-narmstrong@baylibre.com>
 <1522748451-21209-2-git-send-email-narmstrong@baylibre.com>
Message-ID: <CAPnjgZ3curpxg443ZuQjmX2nAYkxMFq2SsYVpUJy4UFwx1Hcew@mail.gmail.com>

On 3 April 2018 at 17:40, Neil Armstrong <narmstrong at baylibre.com> wrote:
> This patch adds a "bulk" API to the reset API in order to get/deassert/
> assert/release a group of reset signals associated with a device.
>
> This bulk API will avoid adding a copy of the same code to manage
> a group of reset signals in drivers.
>
> Signed-off-by: Neil Armstrong <narmstrong at baylibre.com>
> ---
>  drivers/reset/reset-uclass.c | 60 +++++++++++++++++++++++++++
>  include/reset.h              | 99 ++++++++++++++++++++++++++++++++++++++++++++
>  2 files changed, 159 insertions(+)

Reviewed-by: Simon Glass <sjg at chromium.org>


From sjg at chromium.org  Tue Apr  3 10:53:43 2018
From: sjg at chromium.org (Simon Glass)
Date: Wed, 4 Apr 2018 01:53:43 +0800
Subject: [PATCH v2 u-boot 1/2] clk: Add get/enable/disable/release for a
 bulk of clocks
In-Reply-To: <1522748659-21622-2-git-send-email-narmstrong@baylibre.com>
References: <1522748659-21622-1-git-send-email-narmstrong@baylibre.com>
 <1522748659-21622-2-git-send-email-narmstrong@baylibre.com>
Message-ID: <CAPnjgZ1MzxP+OBT4AkSV9G2MN5PQ0_AKMiqpp-B+W0bzEZrOPQ@mail.gmail.com>

On 3 April 2018 at 17:44, Neil Armstrong <narmstrong at baylibre.com> wrote:
> This patch adds a "bulk" API to the clock API in order to get/enable/disable
> /release a group of clocks associated with a device.
>
> This bulk API will avoid adding a copy of the same code to manage
> a group of clocks in drivers.
>
> Signed-off-by: Neil Armstrong <narmstrong at baylibre.com>
> ---
>  drivers/clk/clk-uclass.c | 59 +++++++++++++++++++++++++++++++++++++++
>  include/clk.h            | 72 +++++++++++++++++++++++++++++++++++++++++++++++-
>  2 files changed, 130 insertions(+), 1 deletion(-)

Reviewed-by: Simon Glass <sjg at chromium.org>


From sjg at chromium.org  Tue Apr  3 10:54:00 2018
From: sjg at chromium.org (Simon Glass)
Date: Wed, 4 Apr 2018 01:54:00 +0800
Subject: [PATCH v2 u-boot 2/2] clk: add sandbox test for bulk API
In-Reply-To: <1522748659-21622-3-git-send-email-narmstrong@baylibre.com>
References: <1522748659-21622-1-git-send-email-narmstrong@baylibre.com>
 <1522748659-21622-3-git-send-email-narmstrong@baylibre.com>
Message-ID: <CAPnjgZ1bxgpoaxkNxnEQ0Sh7Cg2XrbmjC=Da2fCs1nfbf5VuEg@mail.gmail.com>

On 3 April 2018 at 17:44, Neil Armstrong <narmstrong at baylibre.com> wrote:
> This patch adds the bulk clock API tests for the sandbox test suite.
>
> It's very similar to the main test but only uses the _bulk() API and
> checks if the clocks are correctly enabled/disabled.
>
> Signed-off-by: Neil Armstrong <narmstrong at baylibre.com>
> ---
>  arch/sandbox/include/asm/clk.h | 32 ++++++++++++++++++++++++++++++++
>  drivers/clk/clk_sandbox_test.c | 29 +++++++++++++++++++++++++++++
>  test/dm/clk.c                  | 38 ++++++++++++++++++++++++++++++++++++++
>  3 files changed, 99 insertions(+)

Reviewed-by: Simon Glass <sjg at chromium.org>


From lkp at intel.com  Tue Apr  3 11:26:31 2018
From: lkp at intel.com (kbuild test robot)
Date: Wed, 4 Apr 2018 02:26:31 +0800
Subject: [PATCH] ARM64: dts: meson-axg: enable the eMMC controller
In-Reply-To: <20180403102651.60340-1-yixun.lan@amlogic.com>
References: <20180403102651.60340-1-yixun.lan@amlogic.com>
Message-ID: <201804040211.7wh3FnSx%fengguang.wu@intel.com>

Hi Nan,

Thank you for the patch! Yet something to improve:

[auto build test ERROR on next-20180403]
[cannot apply to robh/for-next v4.16 v4.16-rc7 v4.16-rc6 v4.16]
[if your patch is applied to the wrong git tree, please drop us a note to help improve the system]

url:    https://github.com/0day-ci/linux/commits/Yixun-Lan/ARM64-dts-meson-axg-enable-the-eMMC-controller/20180403-224314
config: arm64-allyesconfig (attached as .config)
compiler: aarch64-linux-gnu-gcc (Debian 7.2.0-11) 7.2.0
reproduce:
        wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
        chmod +x ~/bin/make.cross
        # save the attached .config to linux build tree
        make.cross ARCH=arm64 

All errors (new ones prefixed by >>):

>> Error: arch/arm64/boot/dts/amlogic/meson-axg-s400.dts:49.24-25 syntax error
   FATAL ERROR: Unable to parse input tree

---
0-DAY kernel test infrastructure                Open Source Technology Center
https://lists.01.org/pipermail/kbuild-all                   Intel Corporation
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From narmstrong at baylibre.com  Wed Apr  4 01:45:22 2018
From: narmstrong at baylibre.com (Neil Armstrong)
Date: Wed, 4 Apr 2018 10:45:22 +0200
Subject: [PATCH v2 u-boot 2/2] reset: add sandbox test for bulk API
In-Reply-To: <CAPnjgZ0+M8pXpi+YYZReY+hgeXv+XTCDuooxkYYegaXVT_O38w@mail.gmail.com>
References: <1522748451-21209-1-git-send-email-narmstrong@baylibre.com>
 <1522748451-21209-3-git-send-email-narmstrong@baylibre.com>
 <CAPnjgZ0+M8pXpi+YYZReY+hgeXv+XTCDuooxkYYegaXVT_O38w@mail.gmail.com>
Message-ID: <15fe8854-324c-fa49-c26e-eac86ab84f85@baylibre.com>

On 03/04/2018 19:53, Simon Glass wrote:
> On 3 April 2018 at 17:40, Neil Armstrong <narmstrong at baylibre.com> wrote:
>> This patch adds the bulk reset API tests for the sandbox test suite.
>>
>> Unlike the main test, it also check the "other" reset signal using the bulk API
>> and checks if the resets are correctly asserted/deasserted.
>>
>> To allow the bulk API to work, and avoid changing the DT, the number of resets
>> of the sandbox reset controller has been bumped to 101 for the "other" reset
>> line to be valid.
> 
> Does it need to be 101, or would, say, 5 be enough?

It could stay at 3, but a dts change should be needed since it declares :

resets = <&resetc 100>, <&resetc 2>;
reset-names = "other", "test";

> 
>>
>> Signed-off-by: Neil Armstrong <narmstrong at baylibre.com>
>> ---
>>  arch/sandbox/include/asm/reset.h   |  4 ++++
>>  drivers/reset/sandbox-reset-test.c | 29 +++++++++++++++++++++++++++++
>>  drivers/reset/sandbox-reset.c      |  2 +-
>>  test/dm/reset.c                    | 33 +++++++++++++++++++++++++++++++++
>>  4 files changed, 67 insertions(+), 1 deletion(-)
> 
> Reviewed-by: Simon Glass <sjg at chromium.org>
> 



From hias at horus.com  Wed Apr  4 04:44:01 2018
From: hias at horus.com (Matthias Reichl)
Date: Wed, 4 Apr 2018 13:44:01 +0200
Subject: [PATCH 0/3] Improve latency of IR decoding
In-Reply-To: <20180328183028.bqqp55ser24lucf2@camel2.lan>
References: <cover.1521901953.git.sean@mess.org>
 <20180328183028.bqqp55ser24lucf2@camel2.lan>
Message-ID: <20180404114401.llnimwz2wqwxpkhw@camel2.lan>

Hi Sean,

On Wed, Mar 28, 2018 at 08:30:29PM +0200, Matthias Reichl wrote:
> Hi Sean,
> 
> On Sat, Mar 24, 2018 at 02:50:42PM +0000, Sean Young wrote:
> > The current IR decoding is much too slow. Many IR protocols rely on
> > a trailing space for decoding (e.g. rc-6 needs to know when the bits
> > end). The trailing space is generated by the IR timeout, and if this
> > is longer than required, keys can be perceived as sticky and slugish.
> > 
> > The other issue the keyup timer. IR has no concept of a keyup message,
> > this is implied by the absence of IR. So, minimising the timeout for
> > this further improves the handling.
> > 
> > With these patches in place, using IR with the builtin decoders is much
> > improved and feels very snappy.
> 
> thanks a lot for the patches!
> 
> I didn't have much time to test yet, but quick checks on
> Amlogic/meson-ir (kernel 4.16-rc7 + media tree + your patches)
> and Raspberry Pi (RPi foundation kernel 4.14 + my backport of
> your patches) look really promising.
> 
> I found one issue, though, in ir-sharp-decoder.c max_space must
> be set to SHARP_ECHO_SPACE - otherwise we get a timeout between
> the normal and inverted message part and decoding fails.
> 
> One thing I'm wondering is if the keyup timer marging might
> be too tight now. Basically we have just the fixed 10ms marging
> from idle timeout. The repeat periods of the protocols are rather
> accurate/strict, so (programmable) remotes not sticking to the
> official timing might cause repeated keyup/down events if they
> are repeating a tad to slow.
> 
> I'm not sure if this could be an issue, but maybe we should
> add a safety margin to the repeat periods as well? For example
> 10 or 20 percent of the specced repeat periods. What do you think?
> 
> To get some more test coverage I've asked my colleague to
> include my backport patch in the LibreELEC testbuilds for
> x86 and RPi. We've got some 500 regular users of these so if
> something's not working we should find out soon.

Quick update: testing so far went really smooth, no issues reported
since we included the backport patch in LibreELEC testbuilds.

Quote from https://github.com/LibreELEC/LibreELEC.tv/pull/2623#issuecomment-377897518
> This is in my nightly test builds since 28 March, and no problems reported so far.
>
> On my NUC with Harmony One/RC6 remote these commits are working just fine.

I've been using LibreELEC on RPi with the patch (using a gpio ir
receiver and a Hauppauge RC-5 remote) since then and everything
was fine as well.

so long,

Hias

> I just hope I
> didn't mess up the backport... Here's the link to my 4.14 patch:
> 
> https://github.com/HiassofT/LibreELEC.tv/blob/le9-ir-latency/packages/linux/patches/default/linux-999-improve-ir-timeout-handling.patch
> 
> so long & thanks,
> 
> Hias
> 
> > 
> > Sean Young (3):
> >   media: rc: set timeout to smallest value required by enabled protocols
> >   media: rc: add ioctl to get the current timeout
> >   media: rc: per-protocol repeat period and minimum keyup timer
> > 
> >  Documentation/media/uapi/rc/lirc-func.rst          |  1 +
> >  .../media/uapi/rc/lirc-set-rec-timeout.rst         | 14 +++--
> >  drivers/media/cec/cec-core.c                       |  2 +-
> >  drivers/media/rc/ir-imon-decoder.c                 |  1 +
> >  drivers/media/rc/ir-jvc-decoder.c                  |  1 +
> >  drivers/media/rc/ir-mce_kbd-decoder.c              |  1 +
> >  drivers/media/rc/ir-nec-decoder.c                  |  1 +
> >  drivers/media/rc/ir-rc5-decoder.c                  |  1 +
> >  drivers/media/rc/ir-rc6-decoder.c                  |  1 +
> >  drivers/media/rc/ir-sanyo-decoder.c                |  1 +
> >  drivers/media/rc/ir-sharp-decoder.c                |  1 +
> >  drivers/media/rc/ir-sony-decoder.c                 |  1 +
> >  drivers/media/rc/ir-xmp-decoder.c                  |  1 +
> >  drivers/media/rc/lirc_dev.c                        |  9 ++-
> >  drivers/media/rc/rc-core-priv.h                    |  1 +
> >  drivers/media/rc/rc-ir-raw.c                       | 31 +++++++++-
> >  drivers/media/rc/rc-main.c                         | 68 +++++++++++-----------
> >  include/uapi/linux/lirc.h                          |  6 ++
> >  18 files changed, 101 insertions(+), 41 deletions(-)
> > 
> > -- 
> > 2.14.3
> > 


From yamada.masahiro at socionext.com  Wed Apr  4 05:10:28 2018
From: yamada.masahiro at socionext.com (Masahiro Yamada)
Date: Wed, 4 Apr 2018 21:10:28 +0900
Subject: [usb-next PATCH v11 3/8] usb: core: add a wrapper for the USB
 PHYs on the HCD
In-Reply-To: <20180303214309.25643-4-martin.blumenstingl@googlemail.com>
References: <20180303214309.25643-1-martin.blumenstingl@googlemail.com>
 <20180303214309.25643-4-martin.blumenstingl@googlemail.com>
Message-ID: <CAK7LNARM=F3Ey0aO9PiNftxkcLVo4z10jdrkSrQE1f74nK1=Ng@mail.gmail.com>

2018-03-04 6:43 GMT+09:00 Martin Blumenstingl
<martin.blumenstingl at googlemail.com>:
> Many SoC platforms have separate devices for the USB PHY which are
> registered through the generic PHY framework. These PHYs have to be
> enabled to make the USB controller actually work. They also have to be
> disabled again on shutdown/suspend.
>
> Currently (at least) the following HCI platform drivers are using custom
> code to obtain all PHYs via devicetree for the roothub/controller and
> disable/enable them when required:
> - ehci-platform.c has ehci_platform_power_{on,off}
> - xhci-mtk.c has xhci_mtk_phy_{init,exit,power_on,power_off}
> - ohci-platform.c has ohci_platform_power_{on,off}
>
> With this new wrapper the USB PHYs can be specified directly in the
> USB controller's devicetree node (just like on the drivers listed
> above). This allows SoCs like the Amlogic Meson GXL family to operate
> correctly once this is wired up correctly. These SoCs use a dwc3
> controller and require all USB PHYs to be initialized (if one of the USB
> PHYs it not initialized then none of USB port works at all).
>
> Signed-off-by: Martin Blumenstingl <martin.blumenstingl at googlemail.com>
> Tested-by: Yixun Lan <yixun.lan at amlogic.com>
> Cc: Neil Armstrong <narmstrong at baylibre.com>
> Cc: Chunfeng Yun <chunfeng.yun at mediatek.com>
> ---
>  drivers/usb/core/Makefile |   2 +-
>  drivers/usb/core/phy.c    | 158 ++++++++++++++++++++++++++++++++++++++++++++++
>  drivers/usb/core/phy.h    |   7 ++
>  3 files changed, 166 insertions(+), 1 deletion(-)
>  create mode 100644 drivers/usb/core/phy.c
>  create mode 100644 drivers/usb/core/phy.h
>
> diff --git a/drivers/usb/core/Makefile b/drivers/usb/core/Makefile
> index 92c9cefb4317..18e874b0441e 100644
> --- a/drivers/usb/core/Makefile
> +++ b/drivers/usb/core/Makefile
> @@ -6,7 +6,7 @@
>  usbcore-y := usb.o hub.o hcd.o urb.o message.o driver.o
>  usbcore-y += config.o file.o buffer.o sysfs.o endpoint.o
>  usbcore-y += devio.o notify.o generic.o quirks.o devices.o
> -usbcore-y += port.o
> +usbcore-y += phy.o port.o
>
>  usbcore-$(CONFIG_OF)           += of.o
>  usbcore-$(CONFIG_USB_PCI)              += hcd-pci.o
> diff --git a/drivers/usb/core/phy.c b/drivers/usb/core/phy.c
> new file mode 100644
> index 000000000000..09b7c43c0ea4
> --- /dev/null
> +++ b/drivers/usb/core/phy.c
> @@ -0,0 +1,158 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * A wrapper for multiple PHYs which passes all phy_* function calls to
> + * multiple (actual) PHY devices. This is comes handy when initializing
> + * all PHYs on a HCD and to keep them all in the same state.
> + *
> + * Copyright (C) 2018 Martin Blumenstingl <martin.blumenstingl at googlemail.com>
> + */
> +
> +#include <linux/device.h>
> +#include <linux/list.h>
> +#include <linux/phy/phy.h>
> +#include <linux/of.h>
> +
> +#include "phy.h"
> +
> +struct usb_phy_roothub {
> +       struct phy              *phy;
> +       struct list_head        list;
> +};
> +
> +static struct usb_phy_roothub *usb_phy_roothub_alloc(struct device *dev)
> +{
> +       struct usb_phy_roothub *roothub_entry;
> +
> +       roothub_entry = devm_kzalloc(dev, sizeof(*roothub_entry), GFP_KERNEL);
> +       if (!roothub_entry)
> +               return ERR_PTR(-ENOMEM);
> +
> +       INIT_LIST_HEAD(&roothub_entry->list);
> +
> +       return roothub_entry;
> +}
> +
> +static int usb_phy_roothub_add_phy(struct device *dev, int index,
> +                                  struct list_head *list)
> +{
> +       struct usb_phy_roothub *roothub_entry;
> +       struct phy *phy = devm_of_phy_get_by_index(dev, dev->of_node, index);
> +
> +       if (IS_ERR_OR_NULL(phy)) {
> +               if (!phy || PTR_ERR(phy) == -ENODEV)
> +                       return 0;
> +               else
> +                       return PTR_ERR(phy);
> +       }
> +
> +       roothub_entry = usb_phy_roothub_alloc(dev);
> +       if (IS_ERR(roothub_entry))
> +               return PTR_ERR(roothub_entry);
> +
> +       roothub_entry->phy = phy;
> +
> +       list_add_tail(&roothub_entry->list, list);
> +
> +       return 0;
> +}
> +
> +struct usb_phy_roothub *usb_phy_roothub_init(struct device *dev)
> +{
> +       struct usb_phy_roothub *phy_roothub;
> +       struct usb_phy_roothub *roothub_entry;
> +       struct list_head *head;
> +       int i, num_phys, err;
> +
> +       num_phys = of_count_phandle_with_args(dev->of_node, "phys",
> +                                             "#phy-cells");
> +       if (num_phys <= 0)
> +               return NULL;
> +
> +       phy_roothub = usb_phy_roothub_alloc(dev);
> +       if (IS_ERR(phy_roothub))
> +               return phy_roothub;
> +
> +       for (i = 0; i < num_phys; i++) {
> +               err = usb_phy_roothub_add_phy(dev, i, &phy_roothub->list);
> +               if (err)
> +                       goto err_out;
> +       }
> +
> +       head = &phy_roothub->list;


I think phy_roothub->phy is always empty,
and only phy_roothub->list is used.


I just wondered if we can directly put 'struct list_head' into
'struct usb_hcd'.





> diff --git a/drivers/usb/core/phy.h b/drivers/usb/core/phy.h
> new file mode 100644
> index 000000000000..6fde59bfbff8
> --- /dev/null
> +++ b/drivers/usb/core/phy.h
> @@ -0,0 +1,7 @@
> +struct usb_phy_roothub;

struct device;

is also needed for usb_phy_roothub_init().



> +struct usb_phy_roothub *usb_phy_roothub_init(struct device *dev);
> +int usb_phy_roothub_exit(struct usb_phy_roothub *phy_roothub);
> +
> +int usb_phy_roothub_power_on(struct usb_phy_roothub *phy_roothub);
> +void usb_phy_roothub_power_off(struct usb_phy_roothub *phy_roothub);


Better to add an include guard?
SPDX-License-Identifier for this header too?




-- 
Best Regards
Masahiro Yamada


From ulf.hansson at linaro.org  Wed Apr  4 05:46:27 2018
From: ulf.hansson at linaro.org (Ulf Hansson)
Date: Wed, 4 Apr 2018 14:46:27 +0200
Subject: [PATCH 0/3] mmc: meson-axg: initial support for AXG SoC platform
In-Reply-To: <20180403100652.41056-1-yixun.lan@amlogic.com>
References: <20180403100652.41056-1-yixun.lan@amlogic.com>
Message-ID: <CAPDyKFpf=Mzryr6wijndKt4Hx48nSGSzyysqAABRGu8_vzGj6g@mail.gmail.com>

On 3 April 2018 at 12:06, Yixun Lan <yixun.lan at amlogic.com> wrote:
>    The patches series try to enable basic eMMC support in the Meson-AXG platfrom.
>
>    Currently HS200 mode is tested with clock running at 166MHz, since
> not all boards are stable to running 200MHz (due to tuning phase error),
> we will further improve the tuning phase driver in the future,
> but in my opiton, this patch series itself is pretty good to go.
>
> Nan Li (3):
>   mmc: dt-bindings: update bindings doc to support Meson-AXG SoC
>   mmc: meson-axg: add support for the Meson-AXG platform
>   mmc: meson: update doc to support Meson-AXG platform
>
>  .../devicetree/bindings/mmc/amlogic,meson-gx.txt   |  1 +
>  drivers/mmc/host/Kconfig                           |  4 +-
>  drivers/mmc/host/meson-gx-mmc.c                    | 63 ++++++++++++++++++----
>  3 files changed, 55 insertions(+), 13 deletions(-)
>
> --
> 2.16.2
>

Queued up for 3.18, thanks!

Kind regards
Uffe


From sean at mess.org  Wed Apr  4 11:42:43 2018
From: sean at mess.org (Sean Young)
Date: Wed, 4 Apr 2018 19:42:43 +0100
Subject: [PATCH 0/3] Improve latency of IR decoding
In-Reply-To: <20180404114401.llnimwz2wqwxpkhw@camel2.lan>
References: <cover.1521901953.git.sean@mess.org>
 <20180328183028.bqqp55ser24lucf2@camel2.lan>
 <20180404114401.llnimwz2wqwxpkhw@camel2.lan>
Message-ID: <20180404184243.rreugkxz5vxjkoay@gofer.mess.org>

Hi Matthias,

On Wed, Apr 04, 2018 at 01:44:01PM +0200, Matthias Reichl wrote:
> On Wed, Mar 28, 2018 at 08:30:29PM +0200, Matthias Reichl wrote:
> > Hi Sean,
> > 
> > On Sat, Mar 24, 2018 at 02:50:42PM +0000, Sean Young wrote:
> > > The current IR decoding is much too slow. Many IR protocols rely on
> > > a trailing space for decoding (e.g. rc-6 needs to know when the bits
> > > end). The trailing space is generated by the IR timeout, and if this
> > > is longer than required, keys can be perceived as sticky and slugish.
> > > 
> > > The other issue the keyup timer. IR has no concept of a keyup message,
> > > this is implied by the absence of IR. So, minimising the timeout for
> > > this further improves the handling.
> > > 
> > > With these patches in place, using IR with the builtin decoders is much
> > > improved and feels very snappy.
> > 
> > thanks a lot for the patches!
> > 
> > I didn't have much time to test yet, but quick checks on
> > Amlogic/meson-ir (kernel 4.16-rc7 + media tree + your patches)
> > and Raspberry Pi (RPi foundation kernel 4.14 + my backport of
> > your patches) look really promising.
> > 
> > I found one issue, though, in ir-sharp-decoder.c max_space must
> > be set to SHARP_ECHO_SPACE - otherwise we get a timeout between
> > the normal and inverted message part and decoding fails.

Thanks for spotting that -- you're right!

> > One thing I'm wondering is if the keyup timer marging might
> > be too tight now. Basically we have just the fixed 10ms marging
> > from idle timeout. The repeat periods of the protocols are rather
> > accurate/strict, so (programmable) remotes not sticking to the
> > official timing might cause repeated keyup/down events if they
> > are repeating a tad to slow.

This does need some further thought. There might be delays in the
scheduling of the rc decoding thread or the IR hardware might be slow
delivering new IR pulse data (e.g. fifo like hardware, e.g. winbond-cir).

> > I'm not sure if this could be an issue, but maybe we should
> > add a safety margin to the repeat periods as well? For example
> > 10 or 20 percent of the specced repeat periods. What do you think?
> > 
> > To get some more test coverage I've asked my colleague to
> > include my backport patch in the LibreELEC testbuilds for
> > x86 and RPi. We've got some 500 regular users of these so if
> > something's not working we should find out soon.
> 
> Quick update: testing so far went really smooth, no issues reported
> since we included the backport patch in LibreELEC testbuilds.
> 
> Quote from https://github.com/LibreELEC/LibreELEC.tv/pull/2623#issuecomment-377897518

Thank you so much for including the patches in the LibreELEC test builds,
that really is a great test! 

> > This is in my nightly test builds since 28 March, and no problems reported so far.
> >
> > On my NUC with Harmony One/RC6 remote these commits are working just fine.
> 
> I've been using LibreELEC on RPi with the patch (using a gpio ir
> receiver and a Hauppauge RC-5 remote) since then and everything
> was fine as well.

That's great. I'd like to do some more testing with various bits of hardware
and test all the protocols.

Thanks,

Sean


From b.galvani at gmail.com  Wed Apr  4 13:40:24 2018
From: b.galvani at gmail.com (Beniamino Galvani)
Date: Wed, 4 Apr 2018 22:40:24 +0200
Subject: [PATCH u-boot 1/2] ARM: meson: rename GXBB to GX
In-Reply-To: <1522230877-21267-2-git-send-email-narmstrong@baylibre.com>
References: <1522230877-21267-1-git-send-email-narmstrong@baylibre.com>
 <1522230877-21267-2-git-send-email-narmstrong@baylibre.com>
Message-ID: <20180404204024.GA12177@gmail.com>

On Wed, Mar 28, 2018 at 11:54:36AM +0200, Neil Armstrong wrote:
> Taking into account the Amlogic Family name starts with GX, including
> the GXBB, GXL and GXM SoCs.
> 
> Signed-off-by: Neil Armstrong <narmstrong at baylibre.com>

Hi,

looks good to me, but perhaps can you align again register values and
other macros in gx.h?

Beniamino


From b.galvani at gmail.com  Wed Apr  4 13:49:53 2018
From: b.galvani at gmail.com (Beniamino Galvani)
Date: Wed, 4 Apr 2018 22:49:53 +0200
Subject: [PATCH u-boot 2/2] ARM: meson: Add cpu info display for GX SoCs
In-Reply-To: <1522230877-21267-3-git-send-email-narmstrong@baylibre.com>
References: <1522230877-21267-1-git-send-email-narmstrong@baylibre.com>
 <1522230877-21267-3-git-send-email-narmstrong@baylibre.com>
Message-ID: <20180404204953.GA12368@gmail.com>

On Wed, Mar 28, 2018 at 11:54:37AM +0200, Neil Armstrong wrote:
> The Amlogic SoCs have a registers containing the die revision
> and packaging type to determine the SoC family and package marketing
> name like S905X for the GXL SoC Family.
> This code is taken for the Linux meson-gx-socinfo driver and adapted
> to U-Boot printing.
> 
> Signed-off-by: Neil Armstrong <narmstrong at baylibre.com>
> ---
>  arch/arm/include/asm/arch-meson/gx.h |   1 +
>  arch/arm/mach-meson/Makefile         |   2 +-
>  arch/arm/mach-meson/cpu_info.c       | 105 +++++++++++++++++++++++++++++++++++
>  configs/khadas-vim_defconfig         |   2 +-
>  configs/libretech-cc_defconfig       |   2 +-
>  configs/odroid-c2_defconfig          |   2 +-
>  configs/odroid_defconfig             |   1 +
>  configs/p212_defconfig               |   2 +-
>  8 files changed, 112 insertions(+), 5 deletions(-)
>  create mode 100644 arch/arm/mach-meson/cpu_info.c
> 
> diff --git a/arch/arm/include/asm/arch-meson/gx.h b/arch/arm/include/asm/arch-meson/gx.h
> index 7930efd..6d5b4ea 100644
> --- a/arch/arm/include/asm/arch-meson/gx.h
> +++ b/arch/arm/include/asm/arch-meson/gx.h
> @@ -17,6 +17,7 @@
>  /* Always-On Peripherals registers */
>  #define GX_AO_ADDR(off)	(GX_AOBUS_BASE + ((off) << 2))
>  
> +#define GX_AO_SEC_SD_CFG8	GX_AO_ADDR(0x88)
>  #define GX_AO_SEC_GP_CFG0	GX_AO_ADDR(0x90)
>  #define GX_AO_SEC_GP_CFG3	GX_AO_ADDR(0x93)
>  #define GX_AO_SEC_GP_CFG4	GX_AO_ADDR(0x94)
> diff --git a/arch/arm/mach-meson/Makefile b/arch/arm/mach-meson/Makefile
> index b4e8dde..5a01ff0 100644
> --- a/arch/arm/mach-meson/Makefile
> +++ b/arch/arm/mach-meson/Makefile
> @@ -4,4 +4,4 @@
>  # SPDX-License-Identifier:	GPL-2.0+
>  #
>  
> -obj-y += board.o sm.o eth.o
> +obj-y += board.o sm.o eth.o cpu_info.o
> diff --git a/arch/arm/mach-meson/cpu_info.c b/arch/arm/mach-meson/cpu_info.c
> new file mode 100644
> index 0000000..657768f
> --- /dev/null
> +++ b/arch/arm/mach-meson/cpu_info.c
> @@ -0,0 +1,105 @@
> +/*
> + * Copyright (C) 2018 BayLibre, SAS
> + * Author: Neil Armstrong <narmstrong at baylibre.com>
> + *
> + * SPDX-License-Identifier:	GPL-2.0+
> + */
> +
> +#include <common.h>
> +#include <asm/io.h>
> +#include <linux/bitfield.h>
> +#include <asm/arch/gx.h>
> +
> +#ifdef CONFIG_DISPLAY_CPUINFO
> +
> +#define SOCINFO_MAJOR	GENMASK(31, 24)
> +#define SOCINFO_PACK	GENMASK(23, 16)
> +#define SOCINFO_MINOR	GENMASK(15, 8)
> +#define SOCINFO_MISC	GENMASK(7, 0)
> +
> +static const struct meson_gx_soc_id {
> +	const char *name;
> +	unsigned int id;
> +} soc_ids[] = {
> +	{ "GXBB", 0x1f },
> +	{ "GXTVBB", 0x20 },
> +	{ "GXL", 0x21 },
> +	{ "GXM", 0x22 },
> +	{ "TXL", 0x23 },
> +};
> +
> +static const struct meson_gx_package_id {
> +	const char *name;
> +	unsigned int major_id;
> +	unsigned int pack_id;
> +} soc_packages[] = {
> +	{ "S905", 0x1f, 0 },
> +	{ "S905M", 0x1f, 0x20 },
> +	{ "S905D", 0x21, 0 },
> +	{ "S905X", 0x21, 0x80 },
> +	{ "S905L", 0x21, 0xc0 },
> +	{ "S905M2", 0x21, 0xe0 },
> +	{ "S912", 0x22, 0 },
> +};
> +
> +static inline unsigned int socinfo_to_major(u32 socinfo)
> +{
> +	return FIELD_GET(SOCINFO_MAJOR, socinfo);
> +}
> +
> +static inline unsigned int socinfo_to_minor(u32 socinfo)
> +{
> +	return FIELD_GET(SOCINFO_MINOR, socinfo);
> +}
> +
> +static inline unsigned int socinfo_to_pack(u32 socinfo)
> +{
> +	return FIELD_GET(SOCINFO_PACK, socinfo);
> +}
> +
> +static inline unsigned int socinfo_to_misc(u32 socinfo)
> +{
> +	return FIELD_GET(SOCINFO_MISC, socinfo);
> +}
> +
> +static const char *socinfo_to_package_id(u32 socinfo)
> +{
> +	unsigned int pack = socinfo_to_pack(socinfo) & 0xf0;
> +	unsigned int major = socinfo_to_major(socinfo);
> +	int i;
> +
> +	for (i = 0 ; i < ARRAY_SIZE(soc_packages) ; ++i) {
> +		if (soc_packages[i].major_id == major &&
> +		    soc_packages[i].pack_id == pack)
> +			return soc_packages[i].name;
> +	}
> +
> +	return "Unknown";
> +}
> +
> +static const char *socinfo_to_soc_id(u32 socinfo)
> +{
> +	unsigned int id = socinfo_to_major(socinfo);
> +	int i;
> +
> +	for (i = 0 ; i < ARRAY_SIZE(soc_ids) ; ++i) {
> +		if (soc_ids[i].id == id)
> +			return soc_ids[i].name;
> +	}
> +
> +	return "Unknown";
> +}
> +
> +int print_cpuinfo(void)
> +{
> +	u32 socinfo = readl(GX_AO_SEC_SD_CFG8);

Perhaps, add a blank line between declarations and code? checkpatch
issues a warning about this.

> +	printf("CPU: Amlogic Meson %s (%s) rev %x:%x (%x:%x)\n",
> +		socinfo_to_soc_id(socinfo),
> +		socinfo_to_package_id(socinfo),
> +		socinfo_to_major(socinfo),
> +		socinfo_to_minor(socinfo),
> +		socinfo_to_pack(socinfo),
> +		socinfo_to_misc(socinfo));
> +	return 0;
> +}
> +#endif /* CONFIG_DISPLAY_CPUINFO */
> diff --git a/configs/khadas-vim_defconfig b/configs/khadas-vim_defconfig
> index a0b3f8d..970d373 100644
> --- a/configs/khadas-vim_defconfig
> +++ b/configs/khadas-vim_defconfig
> @@ -7,7 +7,7 @@ CONFIG_IDENT_STRING=" khadas-vim"
>  CONFIG_DEFAULT_DEVICE_TREE="meson-gxl-s905x-khadas-vim"
>  CONFIG_DEBUG_UART=y
>  CONFIG_OF_BOARD_SETUP=y
> -# CONFIG_DISPLAY_CPUINFO is not set
> +CONFIG_DISPLAY_CPUINFO=y
>  # CONFIG_DISPLAY_BOARDINFO is not set
>  # CONFIG_CMD_BDI is not set
>  # CONFIG_CMD_IMI is not set
> diff --git a/configs/libretech-cc_defconfig b/configs/libretech-cc_defconfig
> index a7177b9..cfbba30 100644
> --- a/configs/libretech-cc_defconfig
> +++ b/configs/libretech-cc_defconfig
> @@ -7,7 +7,7 @@ CONFIG_IDENT_STRING=" libretech-cc"
>  CONFIG_DEFAULT_DEVICE_TREE="meson-gxl-s905x-libretech-cc"
>  CONFIG_DEBUG_UART=y
>  CONFIG_OF_BOARD_SETUP=y
> -# CONFIG_DISPLAY_CPUINFO is not set
> +CONFIG_DISPLAY_CPUINFO=y
>  # CONFIG_DISPLAY_BOARDINFO is not set
>  # CONFIG_CMD_BDI is not set
>  # CONFIG_CMD_IMI is not set
> diff --git a/configs/odroid-c2_defconfig b/configs/odroid-c2_defconfig
> index 49461aa..657b647 100644
> --- a/configs/odroid-c2_defconfig
> +++ b/configs/odroid-c2_defconfig
> @@ -7,7 +7,7 @@ CONFIG_IDENT_STRING=" odroid-c2"
>  CONFIG_DEFAULT_DEVICE_TREE="meson-gxbb-odroidc2"
>  CONFIG_DEBUG_UART=y
>  CONFIG_OF_BOARD_SETUP=y
> -# CONFIG_DISPLAY_CPUINFO is not set
> +CONFIG_DISPLAY_CPUINFO=y
>  # CONFIG_DISPLAY_BOARDINFO is not set
>  # CONFIG_CMD_BDI is not set
>  # CONFIG_CMD_IMI is not set
> diff --git a/configs/odroid_defconfig b/configs/odroid_defconfig
> index 810874d..251bf38 100644
> --- a/configs/odroid_defconfig
> +++ b/configs/odroid_defconfig
> @@ -56,3 +56,4 @@ CONFIG_USB_HOST_ETHER=y
>  CONFIG_USB_ETHER_SMSC95XX=y
>  CONFIG_LIB_HW_RAND=y
>  CONFIG_ERRNO_STR=y
> +CONFIG_DISPLAY_CPUINFO=y

Odroid is not an Amlogic board.

With these 2 issues fixed: Reviewed-by: Beniamino Galvani <b.galvani at gmail.com>

Beniamino


From yixun.lan at amlogic.com  Wed Apr  4 18:25:06 2018
From: yixun.lan at amlogic.com (Yixun Lan)
Date: Thu, 5 Apr 2018 09:25:06 +0800
Subject: [PATCH] ARM64: dts: meson-axg: enable the eMMC controller
In-Reply-To: <201804040211.7wh3FnSx%fengguang.wu@intel.com>
References: <20180403102651.60340-1-yixun.lan@amlogic.com>
 <201804040211.7wh3FnSx%fengguang.wu@intel.com>
Message-ID: <05e90560-46a7-7e4f-c4cf-13d8d6e754b3@amlogic.com>

Hi Kevin

On 04/04/2018 02:26 AM, kbuild test robot wrote:
> Hi Nan,
> 
> Thank you for the patch! Yet something to improve:
> 
> [auto build test ERROR on next-20180403]
> [cannot apply to robh/for-next v4.16 v4.16-rc7 v4.16-rc6 v4.16]
> [if your patch is applied to the wrong git tree, please drop us a note to help improve the system]
> 
> url:    https://github.com/0day-ci/linux/commits/Yixun-Lan/ARM64-dts-meson-axg-enable-the-eMMC-controller/20180403-224314
> config: arm64-allyesconfig (attached as .config)
> compiler: aarch64-linux-gnu-gcc (Debian 7.2.0-11) 7.2.0
> reproduce:
>         wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
>         chmod +x ~/bin/make.cross
>         # save the attached .config to linux build tree
>         make.cross ARCH=arm64 
> 
> All errors (new ones prefixed by >>):
> 
>>> Error: arch/arm64/boot/dts/amlogic/meson-axg-s400.dts:49.24-25 syntax error
>    FATAL ERROR: Unable to parse input tree
> 
> ---
> 0-DAY kernel test infrastructure                Open Source Technology Center
> https://lists.01.org/pipermail/kbuild-all                   Intel Corporation
> 

oops, need to add this header (I fail to do a last check when rebase to
the dt64 branch)

+#include <dt-bindings/gpio/meson-axg-gpio.h>

will send a patch v2

Yixun



From rogerq at ti.com  Thu Apr  5 01:47:11 2018
From: rogerq at ti.com (Roger Quadros)
Date: Thu, 5 Apr 2018 11:47:11 +0300
Subject: [PATCH usb-next v4 0/2] fix HCD PHY suspend handling
In-Reply-To: <20180327212621.3400-1-martin.blumenstingl@googlemail.com>
References: <20180327212621.3400-1-martin.blumenstingl@googlemail.com>
Message-ID: <851bcd3a-9ff6-e0ac-579a-a4973c619818@ti.com>

Greg,

On 28/03/18 00:26, Martin Blumenstingl wrote:
> This is a follow-up to my previous series "initialize (multiple) PHYs
> for a HCD": [0].
> 
> Roger Quadros reported [1] that it "is breaking low power cases on TI
> SoCs when USB is in host mode". He further explains that "Not doing the
> phy_exit() here [when entering suspend] leaves the clocks enabled on
> our SoC and we're no longer able to reach low power states on system
> suspend."
> Chunfeng Yun from Mediatek noted [2] that we cannot unconditionally call
> phy_exit while entering system suspend, because this would "disconnect
> plugged devices on MTK platforms, due to re-initialize u2 phys when
> resume"
> 
> In the discussion (which followed Roger's bug report: [1]) Roger,
> Chunfeng and me came to the conclusion that we can fix suspend on the
> TI SoCs without breaking it on the Mediatek SoCs by extending the
> suspend and resume code in usb/core/phy.c by checking whether the USB
> controller can wake up the system (which is the case for the Mediatek
> MTU3 controller, but now for the dwc3 controller used on the TI SoCs):
> - if the controller can wake up the system (Mediatek MTU3 use-case) we
>   only call usb_phy_roothub_power_off (which calls phy_power_off) when
>   entering system suspend
> - if the controller however cannot wake up the system (dwc3 on TI SoCs)
>   we additionally call usb_phy_roothub_exit (which calls phy_exit) when
>   entering system suspend
> - (we undo the previous steps during system resume)
> 
> The goal of this series is to fix the issue reported by Roger without
> breaking suspend/resume on the Mediatek SoCs.
> Since I neither have a TI nor a Mediatek device I am sending this as
> RFC. I have tested it on an Amlogic Meson GXM board (Khadas VIM2) which
> does NOT support suspend/resume yet.
> 
> this should be applied on top of [3] "usb: core: phy: fix return value
> of usb_phy_roothub_exit()" (even though there's no strict dependency,
> this is the order I wrote the patches in).
> 
> changes since RFC v3 at [6]:
> - added Chunfeng Yun's Tested-by and Roger Quadros' Reviewed-by (thank
>   you!)
> - dropped RFC prefix
> 
> changes since RFC v2 at [5]:
> - add missing INIT_LIST_HEAD call in usb_phy_roothub_add_phy (affects
>   patch #1 - spotted by Roger Quadros, thank you!)
> - fixed swapped conditions using device_may_wakeup() in
>   usb_phy_roothub_resume because we need to call usb_phy_roothub_init
>   if the controller cannot wake up the device (affects patch #2, spotted
>   by Chunfeng Yun, thank you!)
> - simplified the error condition to "undo" usb_phy_roothub_init if
>   usb_phy_roothub_power_on failed in usb_phy_roothub_resume (suggested
>   by Chunfeng Yun)
> - updated the commit message (using Roger's wording) because (quote from
>   Roger "it doesn't prevent the system from entering suspend but just
>   prevents the system from reaching lowest power levels in the suspend
>   state."
> 
> Changes since RFC v1 (blob attachments) at [4]:
> - use device_may_wakeup instead of device_can_wakeup as suggested by
>   Roger Quadros
> - use the controller device from hcd->self.controller as suggested by
>   Chunfeng Yun
> - compile time fixes thanks to Roger Quadros
> - if usb_phy_roothub_power_on in usb_phy_roothub_resume failes then
>   we now call usb_phy_roothub_exit to keep the PHYs in the correct
>   state if usb_phy_roothub_resume partially failed
> 
> 
> [0] http://lists.infradead.org/pipermail/linux-amlogic/2018-March/006599.html
> [1] http://lists.infradead.org/pipermail/linux-amlogic/2018-March/006737.html
> [2] http://lists.infradead.org/pipermail/linux-amlogic/2018-March/006758.html
> [3] http://lists.infradead.org/pipermail/linux-amlogic/2018-March/006819.html
> [4] http://lists.infradead.org/pipermail/linux-amlogic/2018-March/006794.html
> [5] http://lists.infradead.org/pipermail/linux-amlogic/2018-March/006820.html
> [6] http://lists.infradead.org/pipermail/linux-amlogic/2018-March/006847.html
> 
> Martin Blumenstingl (2):
>   usb: core: split usb_phy_roothub_{init,alloc}
>   usb: core: use phy_exit during suspend if wake up is not supported

Gentle ping on this one. Without this system suspend/resume is broken on TI platforms.

> 
>  drivers/usb/core/hcd.c | 18 +++++++----
>  drivers/usb/core/phy.c | 88 +++++++++++++++++++++++++++++++++++---------------
>  drivers/usb/core/phy.h |  9 +++++-
>  3 files changed, 82 insertions(+), 33 deletions(-)
> 

-- 
cheers,
-roger

Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki. Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki


From gregkh at linuxfoundation.org  Thu Apr  5 06:38:15 2018
From: gregkh at linuxfoundation.org (Greg KH)
Date: Thu, 5 Apr 2018 15:38:15 +0200
Subject: [PATCH usb-next v4 0/2] fix HCD PHY suspend handling
In-Reply-To: <851bcd3a-9ff6-e0ac-579a-a4973c619818@ti.com>
References: <20180327212621.3400-1-martin.blumenstingl@googlemail.com>
 <851bcd3a-9ff6-e0ac-579a-a4973c619818@ti.com>
Message-ID: <20180405133815.GC21390@kroah.com>

On Thu, Apr 05, 2018 at 11:47:11AM +0300, Roger Quadros wrote:
> Greg,
> 
> On 28/03/18 00:26, Martin Blumenstingl wrote:
> > This is a follow-up to my previous series "initialize (multiple) PHYs
> > for a HCD": [0].
> > 
> > Roger Quadros reported [1] that it "is breaking low power cases on TI
> > SoCs when USB is in host mode". He further explains that "Not doing the
> > phy_exit() here [when entering suspend] leaves the clocks enabled on
> > our SoC and we're no longer able to reach low power states on system
> > suspend."
> > Chunfeng Yun from Mediatek noted [2] that we cannot unconditionally call
> > phy_exit while entering system suspend, because this would "disconnect
> > plugged devices on MTK platforms, due to re-initialize u2 phys when
> > resume"
> > 
> > In the discussion (which followed Roger's bug report: [1]) Roger,
> > Chunfeng and me came to the conclusion that we can fix suspend on the
> > TI SoCs without breaking it on the Mediatek SoCs by extending the
> > suspend and resume code in usb/core/phy.c by checking whether the USB
> > controller can wake up the system (which is the case for the Mediatek
> > MTU3 controller, but now for the dwc3 controller used on the TI SoCs):
> > - if the controller can wake up the system (Mediatek MTU3 use-case) we
> >   only call usb_phy_roothub_power_off (which calls phy_power_off) when
> >   entering system suspend
> > - if the controller however cannot wake up the system (dwc3 on TI SoCs)
> >   we additionally call usb_phy_roothub_exit (which calls phy_exit) when
> >   entering system suspend
> > - (we undo the previous steps during system resume)
> > 
> > The goal of this series is to fix the issue reported by Roger without
> > breaking suspend/resume on the Mediatek SoCs.
> > Since I neither have a TI nor a Mediatek device I am sending this as
> > RFC. I have tested it on an Amlogic Meson GXM board (Khadas VIM2) which
> > does NOT support suspend/resume yet.
> > 
> > this should be applied on top of [3] "usb: core: phy: fix return value
> > of usb_phy_roothub_exit()" (even though there's no strict dependency,
> > this is the order I wrote the patches in).
> > 
> > changes since RFC v3 at [6]:
> > - added Chunfeng Yun's Tested-by and Roger Quadros' Reviewed-by (thank
> >   you!)
> > - dropped RFC prefix
> > 
> > changes since RFC v2 at [5]:
> > - add missing INIT_LIST_HEAD call in usb_phy_roothub_add_phy (affects
> >   patch #1 - spotted by Roger Quadros, thank you!)
> > - fixed swapped conditions using device_may_wakeup() in
> >   usb_phy_roothub_resume because we need to call usb_phy_roothub_init
> >   if the controller cannot wake up the device (affects patch #2, spotted
> >   by Chunfeng Yun, thank you!)
> > - simplified the error condition to "undo" usb_phy_roothub_init if
> >   usb_phy_roothub_power_on failed in usb_phy_roothub_resume (suggested
> >   by Chunfeng Yun)
> > - updated the commit message (using Roger's wording) because (quote from
> >   Roger "it doesn't prevent the system from entering suspend but just
> >   prevents the system from reaching lowest power levels in the suspend
> >   state."
> > 
> > Changes since RFC v1 (blob attachments) at [4]:
> > - use device_may_wakeup instead of device_can_wakeup as suggested by
> >   Roger Quadros
> > - use the controller device from hcd->self.controller as suggested by
> >   Chunfeng Yun
> > - compile time fixes thanks to Roger Quadros
> > - if usb_phy_roothub_power_on in usb_phy_roothub_resume failes then
> >   we now call usb_phy_roothub_exit to keep the PHYs in the correct
> >   state if usb_phy_roothub_resume partially failed
> > 
> > 
> > [0] http://lists.infradead.org/pipermail/linux-amlogic/2018-March/006599.html
> > [1] http://lists.infradead.org/pipermail/linux-amlogic/2018-March/006737.html
> > [2] http://lists.infradead.org/pipermail/linux-amlogic/2018-March/006758.html
> > [3] http://lists.infradead.org/pipermail/linux-amlogic/2018-March/006819.html
> > [4] http://lists.infradead.org/pipermail/linux-amlogic/2018-March/006794.html
> > [5] http://lists.infradead.org/pipermail/linux-amlogic/2018-March/006820.html
> > [6] http://lists.infradead.org/pipermail/linux-amlogic/2018-March/006847.html
> > 
> > Martin Blumenstingl (2):
> >   usb: core: split usb_phy_roothub_{init,alloc}
> >   usb: core: use phy_exit during suspend if wake up is not supported
> 
> Gentle ping on this one. Without this system suspend/resume is broken on TI platforms.

Sorry, this missed my merge window, I can pick it up after 4.17-rc1 is
out.

thanks,

greg k-h


From martin.blumenstingl at googlemail.com  Thu Apr  5 13:04:01 2018
From: martin.blumenstingl at googlemail.com (Martin Blumenstingl)
Date: Thu, 5 Apr 2018 22:04:01 +0200
Subject: [usb-next PATCH v11 3/8] usb: core: add a wrapper for the USB
 PHYs on the HCD
In-Reply-To: <CAK7LNARM=F3Ey0aO9PiNftxkcLVo4z10jdrkSrQE1f74nK1=Ng@mail.gmail.com>
References: <20180303214309.25643-1-martin.blumenstingl@googlemail.com>
 <20180303214309.25643-4-martin.blumenstingl@googlemail.com>
 <CAK7LNARM=F3Ey0aO9PiNftxkcLVo4z10jdrkSrQE1f74nK1=Ng@mail.gmail.com>
Message-ID: <CAFBinCCRhJLxOCz6_a23XnVcSo35MpE8huA8keNFBrWmr_mR=A@mail.gmail.com>

Hello,

(great to hear that this might be useful on Socionext SoCs as well :))

On Wed, Apr 4, 2018 at 2:10 PM, Masahiro Yamada
<yamada.masahiro at socionext.com> wrote:
> 2018-03-04 6:43 GMT+09:00 Martin Blumenstingl
> <martin.blumenstingl at googlemail.com>:
>> Many SoC platforms have separate devices for the USB PHY which are
>> registered through the generic PHY framework. These PHYs have to be
>> enabled to make the USB controller actually work. They also have to be
>> disabled again on shutdown/suspend.
>>
>> Currently (at least) the following HCI platform drivers are using custom
>> code to obtain all PHYs via devicetree for the roothub/controller and
>> disable/enable them when required:
>> - ehci-platform.c has ehci_platform_power_{on,off}
>> - xhci-mtk.c has xhci_mtk_phy_{init,exit,power_on,power_off}
>> - ohci-platform.c has ohci_platform_power_{on,off}
>>
>> With this new wrapper the USB PHYs can be specified directly in the
>> USB controller's devicetree node (just like on the drivers listed
>> above). This allows SoCs like the Amlogic Meson GXL family to operate
>> correctly once this is wired up correctly. These SoCs use a dwc3
>> controller and require all USB PHYs to be initialized (if one of the USB
>> PHYs it not initialized then none of USB port works at all).
>>
>> Signed-off-by: Martin Blumenstingl <martin.blumenstingl at googlemail.com>
>> Tested-by: Yixun Lan <yixun.lan at amlogic.com>
>> Cc: Neil Armstrong <narmstrong at baylibre.com>
>> Cc: Chunfeng Yun <chunfeng.yun at mediatek.com>
>> ---
>>  drivers/usb/core/Makefile |   2 +-
>>  drivers/usb/core/phy.c    | 158 ++++++++++++++++++++++++++++++++++++++++++++++
>>  drivers/usb/core/phy.h    |   7 ++
>>  3 files changed, 166 insertions(+), 1 deletion(-)
>>  create mode 100644 drivers/usb/core/phy.c
>>  create mode 100644 drivers/usb/core/phy.h
>>
>> diff --git a/drivers/usb/core/Makefile b/drivers/usb/core/Makefile
>> index 92c9cefb4317..18e874b0441e 100644
>> --- a/drivers/usb/core/Makefile
>> +++ b/drivers/usb/core/Makefile
>> @@ -6,7 +6,7 @@
>>  usbcore-y := usb.o hub.o hcd.o urb.o message.o driver.o
>>  usbcore-y += config.o file.o buffer.o sysfs.o endpoint.o
>>  usbcore-y += devio.o notify.o generic.o quirks.o devices.o
>> -usbcore-y += port.o
>> +usbcore-y += phy.o port.o
>>
>>  usbcore-$(CONFIG_OF)           += of.o
>>  usbcore-$(CONFIG_USB_PCI)              += hcd-pci.o
>> diff --git a/drivers/usb/core/phy.c b/drivers/usb/core/phy.c
>> new file mode 100644
>> index 000000000000..09b7c43c0ea4
>> --- /dev/null
>> +++ b/drivers/usb/core/phy.c
>> @@ -0,0 +1,158 @@
>> +// SPDX-License-Identifier: GPL-2.0+
>> +/*
>> + * A wrapper for multiple PHYs which passes all phy_* function calls to
>> + * multiple (actual) PHY devices. This is comes handy when initializing
>> + * all PHYs on a HCD and to keep them all in the same state.
>> + *
>> + * Copyright (C) 2018 Martin Blumenstingl <martin.blumenstingl at googlemail.com>
>> + */
>> +
>> +#include <linux/device.h>
>> +#include <linux/list.h>
>> +#include <linux/phy/phy.h>
>> +#include <linux/of.h>
>> +
>> +#include "phy.h"
>> +
>> +struct usb_phy_roothub {
>> +       struct phy              *phy;
>> +       struct list_head        list;
>> +};
>> +
>> +static struct usb_phy_roothub *usb_phy_roothub_alloc(struct device *dev)
>> +{
>> +       struct usb_phy_roothub *roothub_entry;
>> +
>> +       roothub_entry = devm_kzalloc(dev, sizeof(*roothub_entry), GFP_KERNEL);
>> +       if (!roothub_entry)
>> +               return ERR_PTR(-ENOMEM);
>> +
>> +       INIT_LIST_HEAD(&roothub_entry->list);
>> +
>> +       return roothub_entry;
>> +}
>> +
>> +static int usb_phy_roothub_add_phy(struct device *dev, int index,
>> +                                  struct list_head *list)
>> +{
>> +       struct usb_phy_roothub *roothub_entry;
>> +       struct phy *phy = devm_of_phy_get_by_index(dev, dev->of_node, index);
>> +
>> +       if (IS_ERR_OR_NULL(phy)) {
>> +               if (!phy || PTR_ERR(phy) == -ENODEV)
>> +                       return 0;
>> +               else
>> +                       return PTR_ERR(phy);
>> +       }
>> +
>> +       roothub_entry = usb_phy_roothub_alloc(dev);
>> +       if (IS_ERR(roothub_entry))
>> +               return PTR_ERR(roothub_entry);
>> +
>> +       roothub_entry->phy = phy;
>> +
>> +       list_add_tail(&roothub_entry->list, list);
>> +
>> +       return 0;
>> +}
>> +
>> +struct usb_phy_roothub *usb_phy_roothub_init(struct device *dev)
>> +{
>> +       struct usb_phy_roothub *phy_roothub;
>> +       struct usb_phy_roothub *roothub_entry;
>> +       struct list_head *head;
>> +       int i, num_phys, err;
>> +
>> +       num_phys = of_count_phandle_with_args(dev->of_node, "phys",
>> +                                             "#phy-cells");
>> +       if (num_phys <= 0)
>> +               return NULL;
>> +
>> +       phy_roothub = usb_phy_roothub_alloc(dev);
>> +       if (IS_ERR(phy_roothub))
>> +               return phy_roothub;
>> +
>> +       for (i = 0; i < num_phys; i++) {
>> +               err = usb_phy_roothub_add_phy(dev, i, &phy_roothub->list);
>> +               if (err)
>> +                       goto err_out;
>> +       }
>> +
>> +       head = &phy_roothub->list;
>
>
> I think phy_roothub->phy is always empty,
> and only phy_roothub->list is used.
>
>
> I just wondered if we can directly put 'struct list_head' into
> 'struct usb_hcd'.
maybe you can try it and send a patch (note: please wait until
v4.17-rc2-ish because there are some fixes that will be applied by
Greg after v4.17-rc1 is out, as well as the issues you noted below)?
I believe it's not critical so there's plenty of time to get it into v4.18

>> diff --git a/drivers/usb/core/phy.h b/drivers/usb/core/phy.h
>> new file mode 100644
>> index 000000000000..6fde59bfbff8
>> --- /dev/null
>> +++ b/drivers/usb/core/phy.h
>> @@ -0,0 +1,7 @@
>> +struct usb_phy_roothub;
>
> struct device;
>
> is also needed for usb_phy_roothub_init().
do you think that I should still fix this in 4.17?

>> +struct usb_phy_roothub *usb_phy_roothub_init(struct device *dev);
>> +int usb_phy_roothub_exit(struct usb_phy_roothub *phy_roothub);
>> +
>> +int usb_phy_roothub_power_on(struct usb_phy_roothub *phy_roothub);
>> +void usb_phy_roothub_power_off(struct usb_phy_roothub *phy_roothub);
>
>
> Better to add an include guard?
> SPDX-License-Identifier for this header too?
good catch - I'll send a patch for this too (along with the missing
forward declaration for struct device)


Regards
Martin


From martin.blumenstingl at googlemail.com  Thu Apr  5 13:08:23 2018
From: martin.blumenstingl at googlemail.com (Martin Blumenstingl)
Date: Thu, 5 Apr 2018 22:08:23 +0200
Subject: [PATCH usb-next v4 0/2] fix HCD PHY suspend handling
In-Reply-To: <20180405133815.GC21390@kroah.com>
References: <20180327212621.3400-1-martin.blumenstingl@googlemail.com>
 <851bcd3a-9ff6-e0ac-579a-a4973c619818@ti.com>
 <20180405133815.GC21390@kroah.com>
Message-ID: <CAFBinCC6TQEyWdtSuqHsejy5b1EXXaJdyUegVTNVqxy9DcuBpw@mail.gmail.com>

Hi Greg,

On Thu, Apr 5, 2018 at 3:38 PM, Greg KH <gregkh at linuxfoundation.org> wrote:
> On Thu, Apr 05, 2018 at 11:47:11AM +0300, Roger Quadros wrote:
>> Greg,
>>
>> On 28/03/18 00:26, Martin Blumenstingl wrote:
>> > This is a follow-up to my previous series "initialize (multiple) PHYs
>> > for a HCD": [0].
>> >
>> > Roger Quadros reported [1] that it "is breaking low power cases on TI
>> > SoCs when USB is in host mode". He further explains that "Not doing the
>> > phy_exit() here [when entering suspend] leaves the clocks enabled on
>> > our SoC and we're no longer able to reach low power states on system
>> > suspend."
>> > Chunfeng Yun from Mediatek noted [2] that we cannot unconditionally call
>> > phy_exit while entering system suspend, because this would "disconnect
>> > plugged devices on MTK platforms, due to re-initialize u2 phys when
>> > resume"
>> >
>> > In the discussion (which followed Roger's bug report: [1]) Roger,
>> > Chunfeng and me came to the conclusion that we can fix suspend on the
>> > TI SoCs without breaking it on the Mediatek SoCs by extending the
>> > suspend and resume code in usb/core/phy.c by checking whether the USB
>> > controller can wake up the system (which is the case for the Mediatek
>> > MTU3 controller, but now for the dwc3 controller used on the TI SoCs):
>> > - if the controller can wake up the system (Mediatek MTU3 use-case) we
>> >   only call usb_phy_roothub_power_off (which calls phy_power_off) when
>> >   entering system suspend
>> > - if the controller however cannot wake up the system (dwc3 on TI SoCs)
>> >   we additionally call usb_phy_roothub_exit (which calls phy_exit) when
>> >   entering system suspend
>> > - (we undo the previous steps during system resume)
>> >
>> > The goal of this series is to fix the issue reported by Roger without
>> > breaking suspend/resume on the Mediatek SoCs.
>> > Since I neither have a TI nor a Mediatek device I am sending this as
>> > RFC. I have tested it on an Amlogic Meson GXM board (Khadas VIM2) which
>> > does NOT support suspend/resume yet.
>> >
>> > this should be applied on top of [3] "usb: core: phy: fix return value
>> > of usb_phy_roothub_exit()" (even though there's no strict dependency,
>> > this is the order I wrote the patches in).
>> >
>> > changes since RFC v3 at [6]:
>> > - added Chunfeng Yun's Tested-by and Roger Quadros' Reviewed-by (thank
>> >   you!)
>> > - dropped RFC prefix
>> >
>> > changes since RFC v2 at [5]:
>> > - add missing INIT_LIST_HEAD call in usb_phy_roothub_add_phy (affects
>> >   patch #1 - spotted by Roger Quadros, thank you!)
>> > - fixed swapped conditions using device_may_wakeup() in
>> >   usb_phy_roothub_resume because we need to call usb_phy_roothub_init
>> >   if the controller cannot wake up the device (affects patch #2, spotted
>> >   by Chunfeng Yun, thank you!)
>> > - simplified the error condition to "undo" usb_phy_roothub_init if
>> >   usb_phy_roothub_power_on failed in usb_phy_roothub_resume (suggested
>> >   by Chunfeng Yun)
>> > - updated the commit message (using Roger's wording) because (quote from
>> >   Roger "it doesn't prevent the system from entering suspend but just
>> >   prevents the system from reaching lowest power levels in the suspend
>> >   state."
>> >
>> > Changes since RFC v1 (blob attachments) at [4]:
>> > - use device_may_wakeup instead of device_can_wakeup as suggested by
>> >   Roger Quadros
>> > - use the controller device from hcd->self.controller as suggested by
>> >   Chunfeng Yun
>> > - compile time fixes thanks to Roger Quadros
>> > - if usb_phy_roothub_power_on in usb_phy_roothub_resume failes then
>> >   we now call usb_phy_roothub_exit to keep the PHYs in the correct
>> >   state if usb_phy_roothub_resume partially failed
>> >
>> >
>> > [0] http://lists.infradead.org/pipermail/linux-amlogic/2018-March/006599.html
>> > [1] http://lists.infradead.org/pipermail/linux-amlogic/2018-March/006737.html
>> > [2] http://lists.infradead.org/pipermail/linux-amlogic/2018-March/006758.html
>> > [3] http://lists.infradead.org/pipermail/linux-amlogic/2018-March/006819.html
>> > [4] http://lists.infradead.org/pipermail/linux-amlogic/2018-March/006794.html
>> > [5] http://lists.infradead.org/pipermail/linux-amlogic/2018-March/006820.html
>> > [6] http://lists.infradead.org/pipermail/linux-amlogic/2018-March/006847.html
>> >
>> > Martin Blumenstingl (2):
>> >   usb: core: split usb_phy_roothub_{init,alloc}
>> >   usb: core: use phy_exit during suspend if wake up is not supported
>>
>> Gentle ping on this one. Without this system suspend/resume is broken on TI platforms.
>
> Sorry, this missed my merge window, I can pick it up after 4.17-rc1 is
> out.
do you want me to re-send this based on v4.17-rc1 (once it's out)?
I can re-spin this series so it includes:
a) "usb: core: phy: fix return value of usb_phy_roothub_exit()" [0]
b) the two patches from this series (they apply on top of [0])
c) a missing forward declaration as well as a missing include guard
(and a SPDX-License-Identifier) as suggested by Masahiro Yamada in [1]

(patches for c) are neither written nor posted yet, but they're minor
and I can prepare and test them during the weekend)

just let me know whether you would like to take these three series
individually or whether you would like them all in one "usb: core:
phy: fixes for v4.17" series


Regards
Martin


[0] http://lists.infradead.org/pipermail/linux-amlogic/2018-March/006819.html
[1] http://lists.infradead.org/pipermail/linux-amlogic/2018-April/006975.html


From gregkh at linuxfoundation.org  Thu Apr  5 13:13:54 2018
From: gregkh at linuxfoundation.org (Greg KH)
Date: Thu, 5 Apr 2018 22:13:54 +0200
Subject: [PATCH usb-next v4 0/2] fix HCD PHY suspend handling
In-Reply-To: <CAFBinCC6TQEyWdtSuqHsejy5b1EXXaJdyUegVTNVqxy9DcuBpw@mail.gmail.com>
References: <20180327212621.3400-1-martin.blumenstingl@googlemail.com>
 <851bcd3a-9ff6-e0ac-579a-a4973c619818@ti.com>
 <20180405133815.GC21390@kroah.com>
 <CAFBinCC6TQEyWdtSuqHsejy5b1EXXaJdyUegVTNVqxy9DcuBpw@mail.gmail.com>
Message-ID: <20180405201354.GA3840@kroah.com>

On Thu, Apr 05, 2018 at 10:08:23PM +0200, Martin Blumenstingl wrote:
> Hi Greg,
> 
> On Thu, Apr 5, 2018 at 3:38 PM, Greg KH <gregkh at linuxfoundation.org> wrote:
> > On Thu, Apr 05, 2018 at 11:47:11AM +0300, Roger Quadros wrote:
> >> Greg,
> >>
> >> On 28/03/18 00:26, Martin Blumenstingl wrote:
> >> > This is a follow-up to my previous series "initialize (multiple) PHYs
> >> > for a HCD": [0].
> >> >
> >> > Roger Quadros reported [1] that it "is breaking low power cases on TI
> >> > SoCs when USB is in host mode". He further explains that "Not doing the
> >> > phy_exit() here [when entering suspend] leaves the clocks enabled on
> >> > our SoC and we're no longer able to reach low power states on system
> >> > suspend."
> >> > Chunfeng Yun from Mediatek noted [2] that we cannot unconditionally call
> >> > phy_exit while entering system suspend, because this would "disconnect
> >> > plugged devices on MTK platforms, due to re-initialize u2 phys when
> >> > resume"
> >> >
> >> > In the discussion (which followed Roger's bug report: [1]) Roger,
> >> > Chunfeng and me came to the conclusion that we can fix suspend on the
> >> > TI SoCs without breaking it on the Mediatek SoCs by extending the
> >> > suspend and resume code in usb/core/phy.c by checking whether the USB
> >> > controller can wake up the system (which is the case for the Mediatek
> >> > MTU3 controller, but now for the dwc3 controller used on the TI SoCs):
> >> > - if the controller can wake up the system (Mediatek MTU3 use-case) we
> >> >   only call usb_phy_roothub_power_off (which calls phy_power_off) when
> >> >   entering system suspend
> >> > - if the controller however cannot wake up the system (dwc3 on TI SoCs)
> >> >   we additionally call usb_phy_roothub_exit (which calls phy_exit) when
> >> >   entering system suspend
> >> > - (we undo the previous steps during system resume)
> >> >
> >> > The goal of this series is to fix the issue reported by Roger without
> >> > breaking suspend/resume on the Mediatek SoCs.
> >> > Since I neither have a TI nor a Mediatek device I am sending this as
> >> > RFC. I have tested it on an Amlogic Meson GXM board (Khadas VIM2) which
> >> > does NOT support suspend/resume yet.
> >> >
> >> > this should be applied on top of [3] "usb: core: phy: fix return value
> >> > of usb_phy_roothub_exit()" (even though there's no strict dependency,
> >> > this is the order I wrote the patches in).
> >> >
> >> > changes since RFC v3 at [6]:
> >> > - added Chunfeng Yun's Tested-by and Roger Quadros' Reviewed-by (thank
> >> >   you!)
> >> > - dropped RFC prefix
> >> >
> >> > changes since RFC v2 at [5]:
> >> > - add missing INIT_LIST_HEAD call in usb_phy_roothub_add_phy (affects
> >> >   patch #1 - spotted by Roger Quadros, thank you!)
> >> > - fixed swapped conditions using device_may_wakeup() in
> >> >   usb_phy_roothub_resume because we need to call usb_phy_roothub_init
> >> >   if the controller cannot wake up the device (affects patch #2, spotted
> >> >   by Chunfeng Yun, thank you!)
> >> > - simplified the error condition to "undo" usb_phy_roothub_init if
> >> >   usb_phy_roothub_power_on failed in usb_phy_roothub_resume (suggested
> >> >   by Chunfeng Yun)
> >> > - updated the commit message (using Roger's wording) because (quote from
> >> >   Roger "it doesn't prevent the system from entering suspend but just
> >> >   prevents the system from reaching lowest power levels in the suspend
> >> >   state."
> >> >
> >> > Changes since RFC v1 (blob attachments) at [4]:
> >> > - use device_may_wakeup instead of device_can_wakeup as suggested by
> >> >   Roger Quadros
> >> > - use the controller device from hcd->self.controller as suggested by
> >> >   Chunfeng Yun
> >> > - compile time fixes thanks to Roger Quadros
> >> > - if usb_phy_roothub_power_on in usb_phy_roothub_resume failes then
> >> >   we now call usb_phy_roothub_exit to keep the PHYs in the correct
> >> >   state if usb_phy_roothub_resume partially failed
> >> >
> >> >
> >> > [0] http://lists.infradead.org/pipermail/linux-amlogic/2018-March/006599.html
> >> > [1] http://lists.infradead.org/pipermail/linux-amlogic/2018-March/006737.html
> >> > [2] http://lists.infradead.org/pipermail/linux-amlogic/2018-March/006758.html
> >> > [3] http://lists.infradead.org/pipermail/linux-amlogic/2018-March/006819.html
> >> > [4] http://lists.infradead.org/pipermail/linux-amlogic/2018-March/006794.html
> >> > [5] http://lists.infradead.org/pipermail/linux-amlogic/2018-March/006820.html
> >> > [6] http://lists.infradead.org/pipermail/linux-amlogic/2018-March/006847.html
> >> >
> >> > Martin Blumenstingl (2):
> >> >   usb: core: split usb_phy_roothub_{init,alloc}
> >> >   usb: core: use phy_exit during suspend if wake up is not supported
> >>
> >> Gentle ping on this one. Without this system suspend/resume is broken on TI platforms.
> >
> > Sorry, this missed my merge window, I can pick it up after 4.17-rc1 is
> > out.
> do you want me to re-send this based on v4.17-rc1 (once it's out)?
> I can re-spin this series so it includes:
> a) "usb: core: phy: fix return value of usb_phy_roothub_exit()" [0]
> b) the two patches from this series (they apply on top of [0])
> c) a missing forward declaration as well as a missing include guard
> (and a SPDX-License-Identifier) as suggested by Masahiro Yamada in [1]
> 
> (patches for c) are neither written nor posted yet, but they're minor
> and I can prepare and test them during the weekend)
> 
> just let me know whether you would like to take these three series
> individually or whether you would like them all in one "usb: core:
> phy: fixes for v4.17" series

Yes, please respin and resend.

thanks,

greg k-h


From yamada.masahiro at socionext.com  Thu Apr  5 20:48:12 2018
From: yamada.masahiro at socionext.com (Masahiro Yamada)
Date: Fri, 6 Apr 2018 12:48:12 +0900
Subject: [usb-next PATCH v11 3/8] usb: core: add a wrapper for the USB
 PHYs on the HCD
In-Reply-To: <CAFBinCCRhJLxOCz6_a23XnVcSo35MpE8huA8keNFBrWmr_mR=A@mail.gmail.com>
References: <20180303214309.25643-1-martin.blumenstingl@googlemail.com>
 <20180303214309.25643-4-martin.blumenstingl@googlemail.com>
 <CAK7LNARM=F3Ey0aO9PiNftxkcLVo4z10jdrkSrQE1f74nK1=Ng@mail.gmail.com>
 <CAFBinCCRhJLxOCz6_a23XnVcSo35MpE8huA8keNFBrWmr_mR=A@mail.gmail.com>
Message-ID: <CAK7LNASN4mgSVXw425CEuFzJdgmgiv=u9h7T+_zSbqU7dwRRcA@mail.gmail.com>

2018-04-06 5:04 GMT+09:00 Martin Blumenstingl
<martin.blumenstingl at googlemail.com>:
> Hello,
>
> (great to hear that this might be useful on Socionext SoCs as well :))
>
> On Wed, Apr 4, 2018 at 2:10 PM, Masahiro Yamada
> <yamada.masahiro at socionext.com> wrote:
>> 2018-03-04 6:43 GMT+09:00 Martin Blumenstingl
>> <martin.blumenstingl at googlemail.com>:
>>> Many SoC platforms have separate devices for the USB PHY which are
>>> registered through the generic PHY framework. These PHYs have to be
>>> enabled to make the USB controller actually work. They also have to be
>>> disabled again on shutdown/suspend.
>>>
>>> Currently (at least) the following HCI platform drivers are using custom
>>> code to obtain all PHYs via devicetree for the roothub/controller and
>>> disable/enable them when required:
>>> - ehci-platform.c has ehci_platform_power_{on,off}
>>> - xhci-mtk.c has xhci_mtk_phy_{init,exit,power_on,power_off}
>>> - ohci-platform.c has ohci_platform_power_{on,off}
>>>
>>> With this new wrapper the USB PHYs can be specified directly in the
>>> USB controller's devicetree node (just like on the drivers listed
>>> above). This allows SoCs like the Amlogic Meson GXL family to operate
>>> correctly once this is wired up correctly. These SoCs use a dwc3
>>> controller and require all USB PHYs to be initialized (if one of the USB
>>> PHYs it not initialized then none of USB port works at all).
>>>
>>> Signed-off-by: Martin Blumenstingl <martin.blumenstingl at googlemail.com>
>>> Tested-by: Yixun Lan <yixun.lan at amlogic.com>
>>> Cc: Neil Armstrong <narmstrong at baylibre.com>
>>> Cc: Chunfeng Yun <chunfeng.yun at mediatek.com>
>>> ---
>>>  drivers/usb/core/Makefile |   2 +-
>>>  drivers/usb/core/phy.c    | 158 ++++++++++++++++++++++++++++++++++++++++++++++
>>>  drivers/usb/core/phy.h    |   7 ++
>>>  3 files changed, 166 insertions(+), 1 deletion(-)
>>>  create mode 100644 drivers/usb/core/phy.c
>>>  create mode 100644 drivers/usb/core/phy.h
>>>
>>> diff --git a/drivers/usb/core/Makefile b/drivers/usb/core/Makefile
>>> index 92c9cefb4317..18e874b0441e 100644
>>> --- a/drivers/usb/core/Makefile
>>> +++ b/drivers/usb/core/Makefile
>>> @@ -6,7 +6,7 @@
>>>  usbcore-y := usb.o hub.o hcd.o urb.o message.o driver.o
>>>  usbcore-y += config.o file.o buffer.o sysfs.o endpoint.o
>>>  usbcore-y += devio.o notify.o generic.o quirks.o devices.o
>>> -usbcore-y += port.o
>>> +usbcore-y += phy.o port.o
>>>
>>>  usbcore-$(CONFIG_OF)           += of.o
>>>  usbcore-$(CONFIG_USB_PCI)              += hcd-pci.o
>>> diff --git a/drivers/usb/core/phy.c b/drivers/usb/core/phy.c
>>> new file mode 100644
>>> index 000000000000..09b7c43c0ea4
>>> --- /dev/null
>>> +++ b/drivers/usb/core/phy.c
>>> @@ -0,0 +1,158 @@
>>> +// SPDX-License-Identifier: GPL-2.0+
>>> +/*
>>> + * A wrapper for multiple PHYs which passes all phy_* function calls to
>>> + * multiple (actual) PHY devices. This is comes handy when initializing
>>> + * all PHYs on a HCD and to keep them all in the same state.
>>> + *
>>> + * Copyright (C) 2018 Martin Blumenstingl <martin.blumenstingl at googlemail.com>
>>> + */
>>> +
>>> +#include <linux/device.h>
>>> +#include <linux/list.h>
>>> +#include <linux/phy/phy.h>
>>> +#include <linux/of.h>
>>> +
>>> +#include "phy.h"
>>> +
>>> +struct usb_phy_roothub {
>>> +       struct phy              *phy;
>>> +       struct list_head        list;
>>> +};
>>> +
>>> +static struct usb_phy_roothub *usb_phy_roothub_alloc(struct device *dev)
>>> +{
>>> +       struct usb_phy_roothub *roothub_entry;
>>> +
>>> +       roothub_entry = devm_kzalloc(dev, sizeof(*roothub_entry), GFP_KERNEL);
>>> +       if (!roothub_entry)
>>> +               return ERR_PTR(-ENOMEM);
>>> +
>>> +       INIT_LIST_HEAD(&roothub_entry->list);
>>> +
>>> +       return roothub_entry;
>>> +}
>>> +
>>> +static int usb_phy_roothub_add_phy(struct device *dev, int index,
>>> +                                  struct list_head *list)
>>> +{
>>> +       struct usb_phy_roothub *roothub_entry;
>>> +       struct phy *phy = devm_of_phy_get_by_index(dev, dev->of_node, index);
>>> +
>>> +       if (IS_ERR_OR_NULL(phy)) {
>>> +               if (!phy || PTR_ERR(phy) == -ENODEV)
>>> +                       return 0;
>>> +               else
>>> +                       return PTR_ERR(phy);
>>> +       }
>>> +
>>> +       roothub_entry = usb_phy_roothub_alloc(dev);
>>> +       if (IS_ERR(roothub_entry))
>>> +               return PTR_ERR(roothub_entry);
>>> +
>>> +       roothub_entry->phy = phy;
>>> +
>>> +       list_add_tail(&roothub_entry->list, list);
>>> +
>>> +       return 0;
>>> +}
>>> +
>>> +struct usb_phy_roothub *usb_phy_roothub_init(struct device *dev)
>>> +{
>>> +       struct usb_phy_roothub *phy_roothub;
>>> +       struct usb_phy_roothub *roothub_entry;
>>> +       struct list_head *head;
>>> +       int i, num_phys, err;
>>> +
>>> +       num_phys = of_count_phandle_with_args(dev->of_node, "phys",
>>> +                                             "#phy-cells");
>>> +       if (num_phys <= 0)
>>> +               return NULL;
>>> +
>>> +       phy_roothub = usb_phy_roothub_alloc(dev);
>>> +       if (IS_ERR(phy_roothub))
>>> +               return phy_roothub;
>>> +
>>> +       for (i = 0; i < num_phys; i++) {
>>> +               err = usb_phy_roothub_add_phy(dev, i, &phy_roothub->list);
>>> +               if (err)
>>> +                       goto err_out;
>>> +       }
>>> +
>>> +       head = &phy_roothub->list;
>>
>>
>> I think phy_roothub->phy is always empty,
>> and only phy_roothub->list is used.
>>
>>
>> I just wondered if we can directly put 'struct list_head' into
>> 'struct usb_hcd'.
> maybe you can try it and send a patch (note: please wait until
> v4.17-rc2-ish because there are some fixes that will be applied by
> Greg after v4.17-rc1 is out, as well as the issues you noted below)?
> I believe it's not critical so there's plenty of time to get it into v4.18

Oh, I was misunderstanding - I thought this patch series was under review.
(Greg does not post patch-apply announce to ML.)

I see this in linux-next now.

When will this be available in Linus' tree?   In the current MW?

Sure, I can send a patch after some flaws are ironed-out.





-- 
Best Regards
Masahiro Yamada


From martin.blumenstingl at googlemail.com  Thu Apr  5 22:15:10 2018
From: martin.blumenstingl at googlemail.com (Martin Blumenstingl)
Date: Fri, 6 Apr 2018 07:15:10 +0200
Subject: [usb-next PATCH v11 3/8] usb: core: add a wrapper for the USB
 PHYs on the HCD
In-Reply-To: <CAK7LNASN4mgSVXw425CEuFzJdgmgiv=u9h7T+_zSbqU7dwRRcA@mail.gmail.com>
References: <20180303214309.25643-1-martin.blumenstingl@googlemail.com>
 <20180303214309.25643-4-martin.blumenstingl@googlemail.com>
 <CAK7LNARM=F3Ey0aO9PiNftxkcLVo4z10jdrkSrQE1f74nK1=Ng@mail.gmail.com>
 <CAFBinCCRhJLxOCz6_a23XnVcSo35MpE8huA8keNFBrWmr_mR=A@mail.gmail.com>
 <CAK7LNASN4mgSVXw425CEuFzJdgmgiv=u9h7T+_zSbqU7dwRRcA@mail.gmail.com>
Message-ID: <CAFBinCDThyLeeHaB4WrtCCf_91jf68MohaUF7UbdgWxBDBq6LQ@mail.gmail.com>

On Fri, Apr 6, 2018 at 5:48 AM, Masahiro Yamada
<yamada.masahiro at socionext.com> wrote:
> 2018-04-06 5:04 GMT+09:00 Martin Blumenstingl
> <martin.blumenstingl at googlemail.com>:
>> Hello,
>>
>> (great to hear that this might be useful on Socionext SoCs as well :))
>>
>> On Wed, Apr 4, 2018 at 2:10 PM, Masahiro Yamada
>> <yamada.masahiro at socionext.com> wrote:
>>> 2018-03-04 6:43 GMT+09:00 Martin Blumenstingl
>>> <martin.blumenstingl at googlemail.com>:
>>>> Many SoC platforms have separate devices for the USB PHY which are
>>>> registered through the generic PHY framework. These PHYs have to be
>>>> enabled to make the USB controller actually work. They also have to be
>>>> disabled again on shutdown/suspend.
>>>>
>>>> Currently (at least) the following HCI platform drivers are using custom
>>>> code to obtain all PHYs via devicetree for the roothub/controller and
>>>> disable/enable them when required:
>>>> - ehci-platform.c has ehci_platform_power_{on,off}
>>>> - xhci-mtk.c has xhci_mtk_phy_{init,exit,power_on,power_off}
>>>> - ohci-platform.c has ohci_platform_power_{on,off}
>>>>
>>>> With this new wrapper the USB PHYs can be specified directly in the
>>>> USB controller's devicetree node (just like on the drivers listed
>>>> above). This allows SoCs like the Amlogic Meson GXL family to operate
>>>> correctly once this is wired up correctly. These SoCs use a dwc3
>>>> controller and require all USB PHYs to be initialized (if one of the USB
>>>> PHYs it not initialized then none of USB port works at all).
>>>>
>>>> Signed-off-by: Martin Blumenstingl <martin.blumenstingl at googlemail.com>
>>>> Tested-by: Yixun Lan <yixun.lan at amlogic.com>
>>>> Cc: Neil Armstrong <narmstrong at baylibre.com>
>>>> Cc: Chunfeng Yun <chunfeng.yun at mediatek.com>
>>>> ---
>>>>  drivers/usb/core/Makefile |   2 +-
>>>>  drivers/usb/core/phy.c    | 158 ++++++++++++++++++++++++++++++++++++++++++++++
>>>>  drivers/usb/core/phy.h    |   7 ++
>>>>  3 files changed, 166 insertions(+), 1 deletion(-)
>>>>  create mode 100644 drivers/usb/core/phy.c
>>>>  create mode 100644 drivers/usb/core/phy.h
>>>>
>>>> diff --git a/drivers/usb/core/Makefile b/drivers/usb/core/Makefile
>>>> index 92c9cefb4317..18e874b0441e 100644
>>>> --- a/drivers/usb/core/Makefile
>>>> +++ b/drivers/usb/core/Makefile
>>>> @@ -6,7 +6,7 @@
>>>>  usbcore-y := usb.o hub.o hcd.o urb.o message.o driver.o
>>>>  usbcore-y += config.o file.o buffer.o sysfs.o endpoint.o
>>>>  usbcore-y += devio.o notify.o generic.o quirks.o devices.o
>>>> -usbcore-y += port.o
>>>> +usbcore-y += phy.o port.o
>>>>
>>>>  usbcore-$(CONFIG_OF)           += of.o
>>>>  usbcore-$(CONFIG_USB_PCI)              += hcd-pci.o
>>>> diff --git a/drivers/usb/core/phy.c b/drivers/usb/core/phy.c
>>>> new file mode 100644
>>>> index 000000000000..09b7c43c0ea4
>>>> --- /dev/null
>>>> +++ b/drivers/usb/core/phy.c
>>>> @@ -0,0 +1,158 @@
>>>> +// SPDX-License-Identifier: GPL-2.0+
>>>> +/*
>>>> + * A wrapper for multiple PHYs which passes all phy_* function calls to
>>>> + * multiple (actual) PHY devices. This is comes handy when initializing
>>>> + * all PHYs on a HCD and to keep them all in the same state.
>>>> + *
>>>> + * Copyright (C) 2018 Martin Blumenstingl <martin.blumenstingl at googlemail.com>
>>>> + */
>>>> +
>>>> +#include <linux/device.h>
>>>> +#include <linux/list.h>
>>>> +#include <linux/phy/phy.h>
>>>> +#include <linux/of.h>
>>>> +
>>>> +#include "phy.h"
>>>> +
>>>> +struct usb_phy_roothub {
>>>> +       struct phy              *phy;
>>>> +       struct list_head        list;
>>>> +};
>>>> +
>>>> +static struct usb_phy_roothub *usb_phy_roothub_alloc(struct device *dev)
>>>> +{
>>>> +       struct usb_phy_roothub *roothub_entry;
>>>> +
>>>> +       roothub_entry = devm_kzalloc(dev, sizeof(*roothub_entry), GFP_KERNEL);
>>>> +       if (!roothub_entry)
>>>> +               return ERR_PTR(-ENOMEM);
>>>> +
>>>> +       INIT_LIST_HEAD(&roothub_entry->list);
>>>> +
>>>> +       return roothub_entry;
>>>> +}
>>>> +
>>>> +static int usb_phy_roothub_add_phy(struct device *dev, int index,
>>>> +                                  struct list_head *list)
>>>> +{
>>>> +       struct usb_phy_roothub *roothub_entry;
>>>> +       struct phy *phy = devm_of_phy_get_by_index(dev, dev->of_node, index);
>>>> +
>>>> +       if (IS_ERR_OR_NULL(phy)) {
>>>> +               if (!phy || PTR_ERR(phy) == -ENODEV)
>>>> +                       return 0;
>>>> +               else
>>>> +                       return PTR_ERR(phy);
>>>> +       }
>>>> +
>>>> +       roothub_entry = usb_phy_roothub_alloc(dev);
>>>> +       if (IS_ERR(roothub_entry))
>>>> +               return PTR_ERR(roothub_entry);
>>>> +
>>>> +       roothub_entry->phy = phy;
>>>> +
>>>> +       list_add_tail(&roothub_entry->list, list);
>>>> +
>>>> +       return 0;
>>>> +}
>>>> +
>>>> +struct usb_phy_roothub *usb_phy_roothub_init(struct device *dev)
>>>> +{
>>>> +       struct usb_phy_roothub *phy_roothub;
>>>> +       struct usb_phy_roothub *roothub_entry;
>>>> +       struct list_head *head;
>>>> +       int i, num_phys, err;
>>>> +
>>>> +       num_phys = of_count_phandle_with_args(dev->of_node, "phys",
>>>> +                                             "#phy-cells");
>>>> +       if (num_phys <= 0)
>>>> +               return NULL;
>>>> +
>>>> +       phy_roothub = usb_phy_roothub_alloc(dev);
>>>> +       if (IS_ERR(phy_roothub))
>>>> +               return phy_roothub;
>>>> +
>>>> +       for (i = 0; i < num_phys; i++) {
>>>> +               err = usb_phy_roothub_add_phy(dev, i, &phy_roothub->list);
>>>> +               if (err)
>>>> +                       goto err_out;
>>>> +       }
>>>> +
>>>> +       head = &phy_roothub->list;
>>>
>>>
>>> I think phy_roothub->phy is always empty,
>>> and only phy_roothub->list is used.
>>>
>>>
>>> I just wondered if we can directly put 'struct list_head' into
>>> 'struct usb_hcd'.
>> maybe you can try it and send a patch (note: please wait until
>> v4.17-rc2-ish because there are some fixes that will be applied by
>> Greg after v4.17-rc1 is out, as well as the issues you noted below)?
>> I believe it's not critical so there's plenty of time to get it into v4.18
>
> Oh, I was misunderstanding - I thought this patch series was under review.
> (Greg does not post patch-apply announce to ML.)
>
> I see this in linux-next now.
>
> When will this be available in Linus' tree?   In the current MW?
this is already available in Linus' tree. the commit for this specific
patch (#3) is known as 07dbff0ddbd86c

> Sure, I can send a patch after some flaws are ironed-out.
great, thank you!
could you also let me know once you have tested this on one of your SoCs?


Regards
Martin


From yamada.masahiro at socionext.com  Fri Apr  6 01:28:52 2018
From: yamada.masahiro at socionext.com (Masahiro Yamada)
Date: Fri, 6 Apr 2018 17:28:52 +0900
Subject: [usb-next PATCH v11 3/8] usb: core: add a wrapper for the USB
 PHYs on the HCD
In-Reply-To: <CAFBinCDThyLeeHaB4WrtCCf_91jf68MohaUF7UbdgWxBDBq6LQ@mail.gmail.com>
References: <20180303214309.25643-1-martin.blumenstingl@googlemail.com>
 <20180303214309.25643-4-martin.blumenstingl@googlemail.com>
 <CAK7LNARM=F3Ey0aO9PiNftxkcLVo4z10jdrkSrQE1f74nK1=Ng@mail.gmail.com>
 <CAFBinCCRhJLxOCz6_a23XnVcSo35MpE8huA8keNFBrWmr_mR=A@mail.gmail.com>
 <CAK7LNASN4mgSVXw425CEuFzJdgmgiv=u9h7T+_zSbqU7dwRRcA@mail.gmail.com>
 <CAFBinCDThyLeeHaB4WrtCCf_91jf68MohaUF7UbdgWxBDBq6LQ@mail.gmail.com>
Message-ID: <CAK7LNAQ=ke2MJVx2Fs-bSAO40QT7ceMNfPXJy2AOREfNb_7r_g@mail.gmail.com>

2018-04-06 14:15 GMT+09:00 Martin Blumenstingl
<martin.blumenstingl at googlemail.com>:

>>
>> When will this be available in Linus' tree?   In the current MW?
> this is already available in Linus' tree. the commit for this specific
> patch (#3) is known as 07dbff0ddbd86c


Oh, great!  Thank you.



>> Sure, I can send a patch after some flaws are ironed-out.
> great, thank you!
> could you also let me know once you have tested this on one of your SoCs?

I will.





-- 
Best Regards
Masahiro Yamada


From sboyd at kernel.org  Fri Apr  6 11:39:22 2018
From: sboyd at kernel.org (Stephen Boyd)
Date: Fri, 06 Apr 2018 11:39:22 -0700
Subject: [PATCH v3 1/6] clk: meson: aoclk: refactor common code into
 dedicated file
In-Reply-To: <20180328025050.221585-2-yixun.lan@amlogic.com>
References: <20180328025050.221585-1-yixun.lan@amlogic.com>
 <20180328025050.221585-2-yixun.lan@amlogic.com>
Message-ID: <152303996277.94378.9360089743935547432@swboyd.mtv.corp.google.com>

Quoting Yixun Lan (2018-03-27 19:50:45)
> diff --git a/drivers/clk/meson/gxbb-aoclk.c b/drivers/clk/meson/gxbb-aoclk.c
> index 9ec23ae9a219..5a922639a264 100644
> --- a/drivers/clk/meson/gxbb-aoclk.c
> +++ b/drivers/clk/meson/gxbb-aoclk.c
> @@ -165,38 +135,39 @@ static int gxbb_aoclkc_probe(struct platform_device *pdev)
>                 return -ENODEV;
>         }
>  
> -       /* Reset Controller */
> -       rstc->regmap = regmap;
> -       rstc->data = gxbb_aoclk_reset;
> -       rstc->reset.ops = &gxbb_aoclk_reset_ops;
> -       rstc->reset.nr_resets = ARRAY_SIZE(gxbb_aoclk_reset);
> -       rstc->reset.of_node = dev->of_node;
> -       ret = devm_reset_controller_register(dev, &rstc->reset);
> -
> -       /*
> -        * Populate regmap and register all clks
> -        */
> -       for (clkid = 0; clkid < ARRAY_SIZE(gxbb_aoclk_gate); clkid++) {
> -               gxbb_aoclk_gate[clkid]->map = regmap;
> -
> -               ret = devm_clk_hw_register(dev,
> -                                          gxbb_aoclk_onecell_data.hws[clkid]);
> -               if (ret)
> -                       return ret;
> -       }
> -
>         /* Specific clocks */
>         cec_32k_ao.regmap = regmap;
>         ret = devm_clk_hw_register(dev, &cec_32k_ao.hw);
> -       if (ret)
> +       if (ret) {
> +               dev_err(&pdev->dev, "clk cec_32k_ao register failed.\n");
>                 return ret;
> +       }
> +
> +       return 0;
> +}
> +
> +static struct meson_aoclk_data gxbb_aoclkc_data = {

Can this be const?

> +       .reset_reg      = AO_RTI_GEN_CNTL_REG0,
> +       .num_reset      = ARRAY_SIZE(gxbb_aoclk_reset),
> +       .reset          = gxbb_aoclk_reset,
> +       .num_clks       = ARRAY_SIZE(gxbb_aoclk_gate),
> +       .clks           = gxbb_aoclk_gate,
> +       .hw_data        = &gxbb_aoclk_onecell_data,
> +};
> +
> diff --git a/drivers/clk/meson/meson-aoclk.c b/drivers/clk/meson/meson-aoclk.c
> new file mode 100644
> index 000000000000..36067c801f7b
> --- /dev/null
> +++ b/drivers/clk/meson/meson-aoclk.c
> @@ -0,0 +1,79 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Amlogic Meson-AXG Clock Controller Driver
> + *
> + * Copyright (c) 2016 BayLibre, SAS.
> + * Author: Neil Armstrong <narmstrong at baylibre.com>
> + *
> + * Copyright (c) 2018 Amlogic, inc.
> + * Author: Qiufang Dai <qiufang.dai at amlogic.com>
> + * Author: Yixun Lan <yixun.lan at amlogic.com>
> + */
> +
> +#include <linux/platform_device.h>
> +#include <linux/reset-controller.h>
> +#include <linux/mfd/syscon.h>
> +#include <linux/init.h>
> +#include <linux/of_device.h>
> +#include "clk-regmap.h"
> +#include "meson-aoclk.h"
> +
> +static int meson_aoclk_do_reset(struct reset_controller_dev *rcdev,
> +                              unsigned long id)
> +{
> +       struct meson_aoclk_reset_controller *rstc =
> +               container_of(rcdev, struct meson_aoclk_reset_controller, reset);
> +
> +       return regmap_write(rstc->regmap, rstc->data->reset_reg,
> +                           BIT(rstc->data->reset[id]));
> +}
> +
> +static const struct reset_control_ops meson_aoclk_reset_ops = {
> +       .reset = meson_aoclk_do_reset,
> +};
> +
> +int meson_aoclkc_probe(struct platform_device *pdev)
> +{
> +       struct meson_aoclk_reset_controller *rstc;
> +       struct meson_aoclk_data *data;
> +       struct device *dev = &pdev->dev;
> +       struct regmap *regmap;
> +       int ret, clkid;
> +
> +       data = (struct meson_aoclk_data *)
> +               of_device_get_match_data(dev);
> +       if (!data)
> +               return -ENODEV;
> +
> +       rstc = devm_kzalloc(dev, sizeof(*rstc), GFP_KERNEL);
> +       if (!rstc)
> +               return -ENOMEM;
> +
> +       regmap = syscon_node_to_regmap(of_get_parent(dev->of_node));
> +       if (IS_ERR(regmap)) {
> +               dev_err(dev, "failed to get regmap\n");
> +               return -ENODEV;
> +       }
> +
> +       /* Reset Controller */
> +       rstc->data = data;
> +       rstc->regmap = regmap;
> +       rstc->reset.ops = &meson_aoclk_reset_ops;
> +       rstc->reset.nr_resets = data->num_reset,
> +       rstc->reset.of_node = dev->of_node;
> +       ret = devm_reset_controller_register(dev, &rstc->reset);

Please check the return value here.

> +
> +       /*
> +        * Populate regmap and register all clks
> +        */
> +       for (clkid = 0; clkid < data->num_clks; clkid++) {
> +               data->clks[clkid]->map = regmap;
> +
> +               ret = devm_clk_hw_register(dev, data->hw_data->hws[clkid]);
> +               if (ret)
> +                       return ret;
> +       }
> +
> +       return of_clk_add_hw_provider(dev->of_node, of_clk_hw_onecell_get,
> +               data->hw_data);

Use devm_ variant?

I suppose because code is moving in this patch that it would be better
to make improvements in another patch so that this patch is a pure code
movement change instead of a movement + improvement change.


From sboyd at kernel.org  Fri Apr  6 13:07:52 2018
From: sboyd at kernel.org (Stephen Boyd)
Date: Fri, 06 Apr 2018 13:07:52 -0700
Subject: [PATCH v3 4/6] clk: meson-axg: Add AO Clock and Reset controller
 driver
In-Reply-To: <20180328025050.221585-5-yixun.lan@amlogic.com>
References: <20180328025050.221585-1-yixun.lan@amlogic.com>
 <20180328025050.221585-5-yixun.lan@amlogic.com>
Message-ID: <152304527293.94378.2019634000949753214@swboyd.mtv.corp.google.com>

Quoting Yixun Lan (2018-03-27 19:50:48)
> +       [CLKID_AO_SAR_ADC_CLK]  = &axg_saradc_gate,
> +};
> +
> +static struct clk_hw_onecell_data axg_aoclk_onecell_data = {

const?

> +       .hws = {
> +               [CLKID_AO_REMOTE]       = &remote_ao.hw,
> +               [CLKID_AO_I2C_MASTER]   = &i2c_master_ao.hw,
> +               [CLKID_AO_I2C_SLAVE]    = &i2c_slave_ao.hw,
> +               [CLKID_AO_UART1]        = &uart1_ao.hw,
> +               [CLKID_AO_UART2]        = &uart2_ao.hw,
> +               [CLKID_AO_IR_BLASTER]   = &ir_blaster_ao.hw,
> +               [CLKID_AO_SAR_ADC]      = &saradc_ao.hw,
> +               [CLKID_AO_CLK81]        = &ao_clk81.hw,
> +               [CLKID_AO_SAR_ADC_SEL]  = &axg_saradc_mux.hw,
> +               [CLKID_AO_SAR_ADC_DIV]  = &axg_saradc_div.hw,
> +               [CLKID_AO_SAR_ADC_CLK]  = &axg_saradc_gate.hw,
> +       },
> +       .num = NR_CLKS,
> +};
> +
> +static struct meson_aoclk_data axg_aoclkc_data = {

const?

> +       .reset_reg      = AO_RTI_GEN_CNTL_REG0,
> +       .num_reset      = ARRAY_SIZE(axg_aoclk_reset),
> +       .reset          = axg_aoclk_reset,
> +       .num_clks       = ARRAY_SIZE(axg_aoclk_regmap),
> +       .clks           = axg_aoclk_regmap,
> +       .hw_data        = &axg_aoclk_onecell_data,
> +};


From yixun.lan at amlogic.com  Sat Apr  7 20:00:57 2018
From: yixun.lan at amlogic.com (Yixun Lan)
Date: Sun, 8 Apr 2018 11:00:57 +0800
Subject: [PATCH v3 1/6] clk: meson: aoclk: refactor common code into
 dedicated file
In-Reply-To: <152303996277.94378.9360089743935547432@swboyd.mtv.corp.google.com>
References: <20180328025050.221585-1-yixun.lan@amlogic.com>
 <20180328025050.221585-2-yixun.lan@amlogic.com>
 <152303996277.94378.9360089743935547432@swboyd.mtv.corp.google.com>
Message-ID: <9b56df24-7906-f539-51ec-b9f8b785e020@amlogic.com>

HI Stephen
 thanks for the review

On 04/07/18 02:39, Stephen Boyd wrote:
> Quoting Yixun Lan (2018-03-27 19:50:45)
>> diff --git a/drivers/clk/meson/gxbb-aoclk.c b/drivers/clk/meson/gxbb-aoclk.c
>> index 9ec23ae9a219..5a922639a264 100644
>> --- a/drivers/clk/meson/gxbb-aoclk.c
>> +++ b/drivers/clk/meson/gxbb-aoclk.c
>> @@ -165,38 +135,39 @@ static int gxbb_aoclkc_probe(struct platform_device *pdev)
>>                 return -ENODEV;
>>         }
>>  
>> -       /* Reset Controller */
>> -       rstc->regmap = regmap;
>> -       rstc->data = gxbb_aoclk_reset;
>> -       rstc->reset.ops = &gxbb_aoclk_reset_ops;
>> -       rstc->reset.nr_resets = ARRAY_SIZE(gxbb_aoclk_reset);
>> -       rstc->reset.of_node = dev->of_node;
>> -       ret = devm_reset_controller_register(dev, &rstc->reset);
>> -
>> -       /*
>> -        * Populate regmap and register all clks
>> -        */
>> -       for (clkid = 0; clkid < ARRAY_SIZE(gxbb_aoclk_gate); clkid++) {
>> -               gxbb_aoclk_gate[clkid]->map = regmap;
>> -
>> -               ret = devm_clk_hw_register(dev,
>> -                                          gxbb_aoclk_onecell_data.hws[clkid]);
>> -               if (ret)
>> -                       return ret;
>> -       }
>> -
>>         /* Specific clocks */
>>         cec_32k_ao.regmap = regmap;
>>         ret = devm_clk_hw_register(dev, &cec_32k_ao.hw);
>> -       if (ret)
>> +       if (ret) {
>> +               dev_err(&pdev->dev, "clk cec_32k_ao register failed.\n");
>>                 return ret;
>> +       }
>> +
>> +       return 0;
>> +}
>> +
>> +static struct meson_aoclk_data gxbb_aoclkc_data = {
> 
> Can this be const?
> 
sure, I'll update at v4
>> +       .reset_reg      = AO_RTI_GEN_CNTL_REG0,
>> +       .num_reset      = ARRAY_SIZE(gxbb_aoclk_reset),
>> +       .reset          = gxbb_aoclk_reset,
>> +       .num_clks       = ARRAY_SIZE(gxbb_aoclk_gate),
>> +       .clks           = gxbb_aoclk_gate,
>> +       .hw_data        = &gxbb_aoclk_onecell_data,
>> +};
>> +
>> diff --git a/drivers/clk/meson/meson-aoclk.c b/drivers/clk/meson/meson-aoclk.c
>> new file mode 100644
>> index 000000000000..36067c801f7b
>> --- /dev/null
>> +++ b/drivers/clk/meson/meson-aoclk.c
>> @@ -0,0 +1,79 @@
>> +// SPDX-License-Identifier: GPL-2.0+
>> +/*
>> + * Amlogic Meson-AXG Clock Controller Driver
>> + *
>> + * Copyright (c) 2016 BayLibre, SAS.
>> + * Author: Neil Armstrong <narmstrong at baylibre.com>
>> + *
>> + * Copyright (c) 2018 Amlogic, inc.
>> + * Author: Qiufang Dai <qiufang.dai at amlogic.com>
>> + * Author: Yixun Lan <yixun.lan at amlogic.com>
>> + */
>> +
>> +#include <linux/platform_device.h>
>> +#include <linux/reset-controller.h>
>> +#include <linux/mfd/syscon.h>
>> +#include <linux/init.h>
>> +#include <linux/of_device.h>
>> +#include "clk-regmap.h"
>> +#include "meson-aoclk.h"
>> +
>> +static int meson_aoclk_do_reset(struct reset_controller_dev *rcdev,
>> +                              unsigned long id)
>> +{
>> +       struct meson_aoclk_reset_controller *rstc =
>> +               container_of(rcdev, struct meson_aoclk_reset_controller, reset);
>> +
>> +       return regmap_write(rstc->regmap, rstc->data->reset_reg,
>> +                           BIT(rstc->data->reset[id]));
>> +}
>> +
>> +static const struct reset_control_ops meson_aoclk_reset_ops = {
>> +       .reset = meson_aoclk_do_reset,
>> +};
>> +
>> +int meson_aoclkc_probe(struct platform_device *pdev)
>> +{
>> +       struct meson_aoclk_reset_controller *rstc;
>> +       struct meson_aoclk_data *data;
>> +       struct device *dev = &pdev->dev;
>> +       struct regmap *regmap;
>> +       int ret, clkid;
>> +
>> +       data = (struct meson_aoclk_data *)
>> +               of_device_get_match_data(dev);
>> +       if (!data)
>> +               return -ENODEV;
>> +
>> +       rstc = devm_kzalloc(dev, sizeof(*rstc), GFP_KERNEL);
>> +       if (!rstc)
>> +               return -ENOMEM;
>> +
>> +       regmap = syscon_node_to_regmap(of_get_parent(dev->of_node));
>> +       if (IS_ERR(regmap)) {
>> +               dev_err(dev, "failed to get regmap\n");
>> +               return -ENODEV;
>> +       }
>> +
>> +       /* Reset Controller */
>> +       rstc->data = data;
>> +       rstc->regmap = regmap;
>> +       rstc->reset.ops = &meson_aoclk_reset_ops;
>> +       rstc->reset.nr_resets = data->num_reset,
>> +       rstc->reset.of_node = dev->of_node;
>> +       ret = devm_reset_controller_register(dev, &rstc->reset);
> 
> Please check the return value here.
> 
will do, thanks for pointing out this

>> +
>> +       /*
>> +        * Populate regmap and register all clks
>> +        */
>> +       for (clkid = 0; clkid < data->num_clks; clkid++) {
>> +               data->clks[clkid]->map = regmap;
>> +
>> +               ret = devm_clk_hw_register(dev, data->hw_data->hws[clkid]);
>> +               if (ret)
>> +                       return ret;
>> +       }
>> +
>> +       return of_clk_add_hw_provider(dev->of_node, of_clk_hw_onecell_get,
>> +               data->hw_data);
> 
> Use devm_ variant?
> 
sure
> I suppose because code is moving in this patch that it would be better
> to make improvements in another patch so that this patch is a pure code
> movement change instead of a movement + improvement change.
> 
I think it's a good idea to fix this in another independent patch

also I will address the comments you raised in another mail thread

Yixun



From yixun.lan at amlogic.com  Sat Apr  7 20:19:31 2018
From: yixun.lan at amlogic.com (Yixun Lan)
Date: Sun, 8 Apr 2018 11:19:31 +0800
Subject: [PATCH v4 0/7] clk: meson-axg: Add AO Cloclk and Reset driver
Message-ID: <20180408031938.153474-1-yixun.lan@amlogic.com>

  This patch try to add AO clock and Reset driver for Amlogic's
Meson-AXG SoC.
  Please note that patch 7 need to wait for the DTS changes[3] merged
into mainline first, otherwise it will break the serial console.

 patch 1: factor the common code into a dedicated file
 patch 3-5: add the aoclk driver for AXG SoC
 patch 6-7: drop unnecessary clock flags

changes since v3 at [4]: 
 - add 'const' contraint to the read-only data
 - switch to devm_of_clk_add_hw_provider API
 - check return value of devm_reset_controller_register

changes since v2 at [2]: 
 - rework meson_aoclkc_probe() which leverage the of_match_data
 - merge patch 5-6 into this series
 - seperate DTS patch, will send to Kevin Hilman independently
 
changes since v1 at [0]: 
 - rebase to clk-meson's branch 'next/drivers' [1]
 - fix license, update to BSD-3-Clause
 - drop un-used include header file

[0] https://lkml.kernel.org/r/20180209070026.193879-1-yixun.lan at amlogic.com
[1] git://github.com/BayLibre/clk-meson.git branch: next-drivers
[2] https://lkml.kernel.org/r/20180323143816.200573-1-yixun.lan at amlogic.com
[3] https://lkml.kernel.org/r/20180326081809.49493-4-yixun.lan at amlogic.com
[4] https://lkml.kernel.org/r/20180328025050.221585-1-yixun.lan at amlogic.com


Qiufang Dai (1):
  clk: meson-axg: Add AO Clock and Reset controller driver

Yixun Lan (6):
  clk: meson: aoclk: refactor common code into dedicated file
  clk: meson: migrate to devm_of_clk_add_hw_provider API
  dt-bindings: clock: axg-aoclkc: New binding for Meson-AXG SoC
  dt-bindings: clock: reset: Add AXG AO Clock and Reset Bindings
  clk: meson: drop CLK_SET_RATE_PARENT flag
  clk: meson: drop CLK_IGNORE_UNUSED flag

 .../bindings/clock/amlogic,gxbb-aoclkc.txt         |   1 +
 drivers/clk/meson/Makefile                         |   4 +-
 drivers/clk/meson/axg-aoclk.c                      | 163 +++++++++++++++++++++
 drivers/clk/meson/axg-aoclk.h                      |  31 ++++
 drivers/clk/meson/gxbb-aoclk.c                     |  92 ++++--------
 drivers/clk/meson/gxbb-aoclk.h                     |   7 +
 drivers/clk/meson/meson-aoclk.c                    |  83 +++++++++++
 drivers/clk/meson/meson-aoclk.h                    |  35 +++++
 include/dt-bindings/clock/axg-aoclkc.h             |  26 ++++
 include/dt-bindings/reset/axg-aoclkc.h             |  20 +++
 10 files changed, 399 insertions(+), 63 deletions(-)
 create mode 100644 drivers/clk/meson/axg-aoclk.c
 create mode 100644 drivers/clk/meson/axg-aoclk.h
 create mode 100644 drivers/clk/meson/meson-aoclk.c
 create mode 100644 drivers/clk/meson/meson-aoclk.h
 create mode 100644 include/dt-bindings/clock/axg-aoclkc.h
 create mode 100644 include/dt-bindings/reset/axg-aoclkc.h

-- 
2.15.1



From yixun.lan at amlogic.com  Sat Apr  7 20:19:32 2018
From: yixun.lan at amlogic.com (Yixun Lan)
Date: Sun, 8 Apr 2018 11:19:32 +0800
Subject: [PATCH v4 1/7] clk: meson: aoclk: refactor common code into dedicated
 file
In-Reply-To: <20180408031938.153474-1-yixun.lan@amlogic.com>
References: <20180408031938.153474-1-yixun.lan@amlogic.com>
Message-ID: <20180408031938.153474-2-yixun.lan@amlogic.com>

We try to refactor the common code into one dedicated file,
while preparing to add new Meson-AXG aoclk driver, this would
help us to better share the code by all aoclk drivers.

Suggested-by: Jerome Brunet <jbrunet at baylibre.com>
Signed-off-by: Yixun Lan <yixun.lan at amlogic.com>
---
 drivers/clk/meson/Makefile      |  2 +-
 drivers/clk/meson/gxbb-aoclk.c  | 91 ++++++++++++++---------------------------
 drivers/clk/meson/gxbb-aoclk.h  |  7 ++++
 drivers/clk/meson/meson-aoclk.c | 83 +++++++++++++++++++++++++++++++++++++
 drivers/clk/meson/meson-aoclk.h | 35 ++++++++++++++++
 5 files changed, 157 insertions(+), 61 deletions(-)
 create mode 100644 drivers/clk/meson/meson-aoclk.c
 create mode 100644 drivers/clk/meson/meson-aoclk.h

diff --git a/drivers/clk/meson/Makefile b/drivers/clk/meson/Makefile
index ffee82e60b7a..555ab9c6ab64 100644
--- a/drivers/clk/meson/Makefile
+++ b/drivers/clk/meson/Makefile
@@ -4,6 +4,6 @@
 
 obj-$(CONFIG_COMMON_CLK_AMLOGIC) += clk-pll.o clk-mpll.o clk-audio-divider.o
 obj-$(CONFIG_COMMON_CLK_MESON8B) += meson8b.o
-obj-$(CONFIG_COMMON_CLK_GXBB)	 += gxbb.o gxbb-aoclk.o gxbb-aoclk-32k.o
+obj-$(CONFIG_COMMON_CLK_GXBB)	 += gxbb.o meson-aoclk.o gxbb-aoclk.o gxbb-aoclk-32k.o
 obj-$(CONFIG_COMMON_CLK_AXG)	 += axg.o
 obj-$(CONFIG_COMMON_CLK_REGMAP_MESON)	+= clk-regmap.o
diff --git a/drivers/clk/meson/gxbb-aoclk.c b/drivers/clk/meson/gxbb-aoclk.c
index 9ec23ae9a219..59db8e92f8cf 100644
--- a/drivers/clk/meson/gxbb-aoclk.c
+++ b/drivers/clk/meson/gxbb-aoclk.c
@@ -52,39 +52,13 @@
  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */
-#include <linux/clk-provider.h>
-#include <linux/of_address.h>
 #include <linux/platform_device.h>
 #include <linux/reset-controller.h>
 #include <linux/mfd/syscon.h>
-#include <linux/regmap.h>
 #include <linux/init.h>
-#include <linux/delay.h>
-#include <dt-bindings/clock/gxbb-aoclkc.h>
-#include <dt-bindings/reset/gxbb-aoclkc.h>
 #include "clk-regmap.h"
 #include "gxbb-aoclk.h"
 
-struct gxbb_aoclk_reset_controller {
-	struct reset_controller_dev reset;
-	unsigned int *data;
-	struct regmap *regmap;
-};
-
-static int gxbb_aoclk_do_reset(struct reset_controller_dev *rcdev,
-			       unsigned long id)
-{
-	struct gxbb_aoclk_reset_controller *reset =
-		container_of(rcdev, struct gxbb_aoclk_reset_controller, reset);
-
-	return regmap_write(reset->regmap, AO_RTI_GEN_CNTL_REG0,
-			    BIT(reset->data[id]));
-}
-
-static const struct reset_control_ops gxbb_aoclk_reset_ops = {
-	.reset = gxbb_aoclk_do_reset,
-};
-
 #define GXBB_AO_GATE(_name, _bit)					\
 static struct clk_regmap _name##_ao = {					\
 	.data = &(struct clk_regmap_gate_data) {			\
@@ -117,7 +91,7 @@ static struct aoclk_cec_32k cec_32k_ao = {
 	},
 };
 
-static unsigned int gxbb_aoclk_reset[] = {
+static const unsigned int gxbb_aoclk_reset[] = {
 	[RESET_AO_REMOTE] = 16,
 	[RESET_AO_I2C_MASTER] = 18,
 	[RESET_AO_I2C_SLAVE] = 19,
@@ -135,7 +109,7 @@ static struct clk_regmap *gxbb_aoclk_gate[] = {
 	[CLKID_AO_IR_BLASTER] = &ir_blaster_ao,
 };
 
-static struct clk_hw_onecell_data gxbb_aoclk_onecell_data = {
+static const struct clk_hw_onecell_data gxbb_aoclk_onecell_data = {
 	.hws = {
 		[CLKID_AO_REMOTE] = &remote_ao.hw,
 		[CLKID_AO_I2C_MASTER] = &i2c_master_ao.hw,
@@ -145,19 +119,15 @@ static struct clk_hw_onecell_data gxbb_aoclk_onecell_data = {
 		[CLKID_AO_IR_BLASTER] = &ir_blaster_ao.hw,
 		[CLKID_AO_CEC_32K] = &cec_32k_ao.hw,
 	},
-	.num = 7,
+	.num = NR_CLKS,
 };
 
-static int gxbb_aoclkc_probe(struct platform_device *pdev)
+static int gxbb_aoclkc_register_specific_clk(
+		struct platform_device *pdev)
 {
-	struct gxbb_aoclk_reset_controller *rstc;
 	struct device *dev = &pdev->dev;
 	struct regmap *regmap;
-	int ret, clkid;
-
-	rstc = devm_kzalloc(dev, sizeof(*rstc), GFP_KERNEL);
-	if (!rstc)
-		return -ENOMEM;
+	int ret;
 
 	regmap = syscon_node_to_regmap(of_get_parent(dev->of_node));
 	if (IS_ERR(regmap)) {
@@ -165,38 +135,39 @@ static int gxbb_aoclkc_probe(struct platform_device *pdev)
 		return -ENODEV;
 	}
 
-	/* Reset Controller */
-	rstc->regmap = regmap;
-	rstc->data = gxbb_aoclk_reset;
-	rstc->reset.ops = &gxbb_aoclk_reset_ops;
-	rstc->reset.nr_resets = ARRAY_SIZE(gxbb_aoclk_reset);
-	rstc->reset.of_node = dev->of_node;
-	ret = devm_reset_controller_register(dev, &rstc->reset);
-
-	/*
-	 * Populate regmap and register all clks
-	 */
-	for (clkid = 0; clkid < ARRAY_SIZE(gxbb_aoclk_gate); clkid++) {
-		gxbb_aoclk_gate[clkid]->map = regmap;
-
-		ret = devm_clk_hw_register(dev,
-					   gxbb_aoclk_onecell_data.hws[clkid]);
-		if (ret)
-			return ret;
-	}
-
 	/* Specific clocks */
 	cec_32k_ao.regmap = regmap;
 	ret = devm_clk_hw_register(dev, &cec_32k_ao.hw);
-	if (ret)
+	if (ret) {
+		dev_err(&pdev->dev, "clk cec_32k_ao register failed.\n");
 		return ret;
+	}
+
+	return 0;
+}
+
+static const struct meson_aoclk_data gxbb_aoclkc_data = {
+	.reset_reg	= AO_RTI_GEN_CNTL_REG0,
+	.num_reset	= ARRAY_SIZE(gxbb_aoclk_reset),
+	.reset		= gxbb_aoclk_reset,
+	.num_clks	= ARRAY_SIZE(gxbb_aoclk_gate),
+	.clks		= gxbb_aoclk_gate,
+	.hw_data	= &gxbb_aoclk_onecell_data,
+};
+
+static int gxbb_aoclkc_probe(struct platform_device *pdev)
+{
+	if (gxbb_aoclkc_register_specific_clk(pdev))
+		return -ENODEV;
 
-	return of_clk_add_hw_provider(dev->of_node, of_clk_hw_onecell_get,
-			&gxbb_aoclk_onecell_data);
+	return meson_aoclkc_probe(pdev);
 }
 
 static const struct of_device_id gxbb_aoclkc_match_table[] = {
-	{ .compatible = "amlogic,meson-gx-aoclkc" },
+	{
+		.compatible	= "amlogic,meson-gx-aoclkc",
+		.data		= &gxbb_aoclkc_data,
+	},
 	{ }
 };
 
diff --git a/drivers/clk/meson/gxbb-aoclk.h b/drivers/clk/meson/gxbb-aoclk.h
index badc4c22b4ee..b031f1a0213e 100644
--- a/drivers/clk/meson/gxbb-aoclk.h
+++ b/drivers/clk/meson/gxbb-aoclk.h
@@ -8,6 +8,10 @@
 #ifndef __GXBB_AOCLKC_H
 #define __GXBB_AOCLKC_H
 
+#include "meson-aoclk.h"
+
+#define NR_CLKS	7
+
 /* AO Configuration Clock registers offsets */
 #define AO_RTI_PWR_CNTL_REG1	0x0c
 #define AO_RTI_PWR_CNTL_REG0	0x10
@@ -26,4 +30,7 @@ struct aoclk_cec_32k {
 
 extern const struct clk_ops meson_aoclk_cec_32k_ops;
 
+#include <dt-bindings/clock/gxbb-aoclkc.h>
+#include <dt-bindings/reset/gxbb-aoclkc.h>
+
 #endif /* __GXBB_AOCLKC_H */
diff --git a/drivers/clk/meson/meson-aoclk.c b/drivers/clk/meson/meson-aoclk.c
new file mode 100644
index 000000000000..14862c22e20d
--- /dev/null
+++ b/drivers/clk/meson/meson-aoclk.c
@@ -0,0 +1,83 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Amlogic Meson-AXG Clock Controller Driver
+ *
+ * Copyright (c) 2016 BayLibre, SAS.
+ * Author: Neil Armstrong <narmstrong at baylibre.com>
+ *
+ * Copyright (c) 2018 Amlogic, inc.
+ * Author: Qiufang Dai <qiufang.dai at amlogic.com>
+ * Author: Yixun Lan <yixun.lan at amlogic.com>
+ */
+
+#include <linux/platform_device.h>
+#include <linux/reset-controller.h>
+#include <linux/mfd/syscon.h>
+#include <linux/init.h>
+#include <linux/of_device.h>
+#include "clk-regmap.h"
+#include "meson-aoclk.h"
+
+static int meson_aoclk_do_reset(struct reset_controller_dev *rcdev,
+			       unsigned long id)
+{
+	struct meson_aoclk_reset_controller *rstc =
+		container_of(rcdev, struct meson_aoclk_reset_controller, reset);
+
+	return regmap_write(rstc->regmap, rstc->data->reset_reg,
+			    BIT(rstc->data->reset[id]));
+}
+
+static const struct reset_control_ops meson_aoclk_reset_ops = {
+	.reset = meson_aoclk_do_reset,
+};
+
+int meson_aoclkc_probe(struct platform_device *pdev)
+{
+	struct meson_aoclk_reset_controller *rstc;
+	struct meson_aoclk_data *data;
+	struct device *dev = &pdev->dev;
+	struct regmap *regmap;
+	int ret, clkid;
+
+	data = (struct meson_aoclk_data *)
+		of_device_get_match_data(dev);
+	if (!data)
+		return -ENODEV;
+
+	rstc = devm_kzalloc(dev, sizeof(*rstc), GFP_KERNEL);
+	if (!rstc)
+		return -ENOMEM;
+
+	regmap = syscon_node_to_regmap(of_get_parent(dev->of_node));
+	if (IS_ERR(regmap)) {
+		dev_err(dev, "failed to get regmap\n");
+		return -ENODEV;
+	}
+
+	/* Reset Controller */
+	rstc->data = data;
+	rstc->regmap = regmap;
+	rstc->reset.ops = &meson_aoclk_reset_ops;
+	rstc->reset.nr_resets = data->num_reset,
+	rstc->reset.of_node = dev->of_node;
+	ret = devm_reset_controller_register(dev, &rstc->reset);
+	if (ret) {
+		dev_err(dev, "failed to register reset controller\n");
+		return ret;
+	}
+
+	/*
+	 * Populate regmap and register all clks
+	 */
+	for (clkid = 0; clkid < data->num_clks; clkid++) {
+		data->clks[clkid]->map = regmap;
+
+		ret = devm_clk_hw_register(dev, data->hw_data->hws[clkid]);
+		if (ret)
+			return ret;
+	}
+
+	return of_clk_add_hw_provider(dev->of_node, of_clk_hw_onecell_get,
+		(void *) data->hw_data);
+}
diff --git a/drivers/clk/meson/meson-aoclk.h b/drivers/clk/meson/meson-aoclk.h
new file mode 100644
index 000000000000..f0fba19fff0a
--- /dev/null
+++ b/drivers/clk/meson/meson-aoclk.h
@@ -0,0 +1,35 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2017 BayLibre, SAS
+ * Author: Neil Armstrong <narmstrong at baylibre.com>
+ *
+ * Copyright (c) 2018 Amlogic, inc.
+ * Author: Qiufang Dai <qiufang.dai at amlogic.com>
+ * Author: Yixun Lan <yixun.lan at amlogic.com>
+ */
+
+#ifndef __MESON_AOCLK_H__
+#define __MESON_AOCLK_H__
+
+#include <linux/platform_device.h>
+#include <linux/reset-controller.h>
+#include "clk-regmap.h"
+
+struct meson_aoclk_data {
+	const unsigned int		reset_reg;
+	const int			num_reset;
+	const unsigned int		*reset;
+	int				num_clks;
+	struct clk_regmap		**clks;
+	const struct clk_hw_onecell_data	*hw_data;
+};
+
+struct meson_aoclk_reset_controller {
+	struct reset_controller_dev	reset;
+	const struct meson_aoclk_data	*data;
+	struct regmap			*regmap;
+};
+
+int meson_aoclkc_probe(struct platform_device *pdev);
+#endif
+
-- 
2.15.1



From yixun.lan at amlogic.com  Sat Apr  7 20:19:33 2018
From: yixun.lan at amlogic.com (Yixun Lan)
Date: Sun, 8 Apr 2018 11:19:33 +0800
Subject: [PATCH v4 2/7] clk: meson: migrate to devm_of_clk_add_hw_provider API
In-Reply-To: <20180408031938.153474-1-yixun.lan@amlogic.com>
References: <20180408031938.153474-1-yixun.lan@amlogic.com>
Message-ID: <20180408031938.153474-3-yixun.lan@amlogic.com>

There is a protential memory leak, as of_clk_del_provider is
never called if of_clk_add_hw_provider has been executed.
Fix this by using devm variant API.

Suggested-by: Stephen Boyd <sboyd at kernel.org>
Signed-off-by: Yixun Lan <yixun.lan at amlogic.com>
---
 drivers/clk/meson/meson-aoclk.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/clk/meson/meson-aoclk.c b/drivers/clk/meson/meson-aoclk.c
index 14862c22e20d..14a1e46a4de6 100644
--- a/drivers/clk/meson/meson-aoclk.c
+++ b/drivers/clk/meson/meson-aoclk.c
@@ -78,6 +78,6 @@ int meson_aoclkc_probe(struct platform_device *pdev)
 			return ret;
 	}
 
-	return of_clk_add_hw_provider(dev->of_node, of_clk_hw_onecell_get,
+	return devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get,
 		(void *) data->hw_data);
 }
-- 
2.15.1



From yixun.lan at amlogic.com  Sat Apr  7 20:19:34 2018
From: yixun.lan at amlogic.com (Yixun Lan)
Date: Sun, 8 Apr 2018 11:19:34 +0800
Subject: [PATCH v4 3/7] dt-bindings: clock: axg-aoclkc: New binding for
 Meson-AXG SoC
In-Reply-To: <20180408031938.153474-1-yixun.lan@amlogic.com>
References: <20180408031938.153474-1-yixun.lan@amlogic.com>
Message-ID: <20180408031938.153474-4-yixun.lan@amlogic.com>

Update the dt-binding documentation to support new compatible string
for the Amlogic's Meson-AXG SoC.

Reviewed-by: Rob Herring <robh at kernel.org>
Signed-off-by: Yixun Lan <yixun.lan at amlogic.com>
---
 Documentation/devicetree/bindings/clock/amlogic,gxbb-aoclkc.txt | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/clock/amlogic,gxbb-aoclkc.txt b/Documentation/devicetree/bindings/clock/amlogic,gxbb-aoclkc.txt
index 786dc39ca904..3a880528030e 100644
--- a/Documentation/devicetree/bindings/clock/amlogic,gxbb-aoclkc.txt
+++ b/Documentation/devicetree/bindings/clock/amlogic,gxbb-aoclkc.txt
@@ -9,6 +9,7 @@ Required Properties:
 	- GXBB (S905) : "amlogic,meson-gxbb-aoclkc"
 	- GXL (S905X, S905D) : "amlogic,meson-gxl-aoclkc"
 	- GXM (S912) : "amlogic,meson-gxm-aoclkc"
+	- AXG (A113D, A113X) : "amlogic,meson-axg-aoclkc"
 	followed by the common "amlogic,meson-gx-aoclkc"
 
 - #clock-cells: should be 1.
-- 
2.15.1



From yixun.lan at amlogic.com  Sat Apr  7 20:19:35 2018
From: yixun.lan at amlogic.com (Yixun Lan)
Date: Sun, 8 Apr 2018 11:19:35 +0800
Subject: [PATCH v4 4/7] dt-bindings: clock: reset: Add AXG AO Clock and Reset
 Bindings
In-Reply-To: <20180408031938.153474-1-yixun.lan@amlogic.com>
References: <20180408031938.153474-1-yixun.lan@amlogic.com>
Message-ID: <20180408031938.153474-5-yixun.lan@amlogic.com>

Add dt-bindings headers for the Meson-AXG's AO clock and
reset controller.

Reviewed-by: Rob Herring <robh at kernel.org>
Signed-off-by: Yixun Lan <yixun.lan at amlogic.com>
---
 include/dt-bindings/clock/axg-aoclkc.h | 26 ++++++++++++++++++++++++++
 include/dt-bindings/reset/axg-aoclkc.h | 20 ++++++++++++++++++++
 2 files changed, 46 insertions(+)
 create mode 100644 include/dt-bindings/clock/axg-aoclkc.h
 create mode 100644 include/dt-bindings/reset/axg-aoclkc.h

diff --git a/include/dt-bindings/clock/axg-aoclkc.h b/include/dt-bindings/clock/axg-aoclkc.h
new file mode 100644
index 000000000000..61955016a55b
--- /dev/null
+++ b/include/dt-bindings/clock/axg-aoclkc.h
@@ -0,0 +1,26 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */
+/*
+ * Copyright (c) 2016 BayLibre, SAS
+ * Author: Neil Armstrong <narmstrong at baylibre.com>
+ *
+ * Copyright (c) 2018 Amlogic, inc.
+ * Author: Qiufang Dai <qiufang.dai at amlogic.com>
+ */
+
+#ifndef DT_BINDINGS_CLOCK_AMLOGIC_MESON_AXG_AOCLK
+#define DT_BINDINGS_CLOCK_AMLOGIC_MESON_AXG_AOCLK
+
+#define CLKID_AO_REMOTE		0
+#define CLKID_AO_I2C_MASTER	1
+#define CLKID_AO_I2C_SLAVE	2
+#define CLKID_AO_UART1		3
+#define CLKID_AO_UART2		4
+#define CLKID_AO_IR_BLASTER	5
+#define CLKID_AO_SAR_ADC	6
+#define CLKID_AO_CLK81		7
+#define CLKID_AO_SAR_ADC_SEL	8
+#define CLKID_AO_SAR_ADC_DIV	9
+#define CLKID_AO_SAR_ADC_CLK	10
+#define CLKID_AO_ALT_XTAL	11
+
+#endif
diff --git a/include/dt-bindings/reset/axg-aoclkc.h b/include/dt-bindings/reset/axg-aoclkc.h
new file mode 100644
index 000000000000..d342c0b6b2a7
--- /dev/null
+++ b/include/dt-bindings/reset/axg-aoclkc.h
@@ -0,0 +1,20 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */
+/*
+ * Copyright (c) 2016 BayLibre, SAS
+ * Author: Neil Armstrong <narmstrong at baylibre.com>
+ *
+ * Copyright (c) 2018 Amlogic, inc.
+ * Author: Qiufang Dai <qiufang.dai at amlogic.com>
+ */
+
+#ifndef DT_BINDINGS_RESET_AMLOGIC_MESON_AXG_AOCLK
+#define DT_BINDINGS_RESET_AMLOGIC_MESON_AXG_AOCLK
+
+#define RESET_AO_REMOTE		0
+#define RESET_AO_I2C_MASTER	1
+#define RESET_AO_I2C_SLAVE	2
+#define RESET_AO_UART1		3
+#define RESET_AO_UART2		4
+#define RESET_AO_IR_BLASTER	5
+
+#endif
-- 
2.15.1



From yixun.lan at amlogic.com  Sat Apr  7 20:19:36 2018
From: yixun.lan at amlogic.com (Yixun Lan)
Date: Sun, 8 Apr 2018 11:19:36 +0800
Subject: [PATCH v4 5/7] clk: meson-axg: Add AO Clock and Reset controller
 driver
In-Reply-To: <20180408031938.153474-1-yixun.lan@amlogic.com>
References: <20180408031938.153474-1-yixun.lan@amlogic.com>
Message-ID: <20180408031938.153474-6-yixun.lan@amlogic.com>

From: Qiufang Dai <qiufang.dai at amlogic.com>

Adds a Clock and Reset controller driver for the Always-On part
of the Amlogic Meson-AXG SoC.

Signed-off-by: Qiufang Dai <qiufang.dai at amlogic.com>
Signed-off-by: Yixun Lan <yixun.lan at amlogic.com>
---
 drivers/clk/meson/Makefile    |   2 +-
 drivers/clk/meson/axg-aoclk.c | 164 ++++++++++++++++++++++++++++++++++++++++++
 drivers/clk/meson/axg-aoclk.h |  31 ++++++++
 3 files changed, 196 insertions(+), 1 deletion(-)
 create mode 100644 drivers/clk/meson/axg-aoclk.c
 create mode 100644 drivers/clk/meson/axg-aoclk.h

diff --git a/drivers/clk/meson/Makefile b/drivers/clk/meson/Makefile
index 555ab9c6ab64..fa6d1e36cef6 100644
--- a/drivers/clk/meson/Makefile
+++ b/drivers/clk/meson/Makefile
@@ -5,5 +5,5 @@
 obj-$(CONFIG_COMMON_CLK_AMLOGIC) += clk-pll.o clk-mpll.o clk-audio-divider.o
 obj-$(CONFIG_COMMON_CLK_MESON8B) += meson8b.o
 obj-$(CONFIG_COMMON_CLK_GXBB)	 += gxbb.o meson-aoclk.o gxbb-aoclk.o gxbb-aoclk-32k.o
-obj-$(CONFIG_COMMON_CLK_AXG)	 += axg.o
+obj-$(CONFIG_COMMON_CLK_AXG)	 += axg.o meson-aoclk.o axg-aoclk.o
 obj-$(CONFIG_COMMON_CLK_REGMAP_MESON)	+= clk-regmap.o
diff --git a/drivers/clk/meson/axg-aoclk.c b/drivers/clk/meson/axg-aoclk.c
new file mode 100644
index 000000000000..cb56d809d3df
--- /dev/null
+++ b/drivers/clk/meson/axg-aoclk.c
@@ -0,0 +1,164 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Amlogic Meson-AXG Clock Controller Driver
+ *
+ * Copyright (c) 2016 Baylibre SAS.
+ * Author: Michael Turquette <mturquette at baylibre.com>
+ *
+ * Copyright (c) 2018 Amlogic, inc.
+ * Author: Qiufang Dai <qiufang.dai at amlogic.com>
+ */
+#include <linux/clk-provider.h>
+#include <linux/platform_device.h>
+#include <linux/reset-controller.h>
+#include <linux/mfd/syscon.h>
+#include <linux/init.h>
+#include "clkc.h"
+#include "axg-aoclk.h"
+
+#define AXG_AO_GATE(_name, _bit)					\
+static struct clk_regmap _name##_ao = {					\
+	.data = &(struct clk_regmap_gate_data) {			\
+		.offset = (AO_RTI_GEN_CNTL_REG0),			\
+		.bit_idx = (_bit),					\
+	},								\
+	.hw.init = &(struct clk_init_data) {				\
+		.name = #_name "_ao",					\
+		.ops = &clk_regmap_gate_ops,				\
+		.parent_names = (const char *[]){ "clk81" },		\
+		.num_parents = 1,					\
+		.flags = CLK_IGNORE_UNUSED,				\
+	},								\
+}
+
+AXG_AO_GATE(remote, 0);
+AXG_AO_GATE(i2c_master, 1);
+AXG_AO_GATE(i2c_slave, 2);
+AXG_AO_GATE(uart1, 3);
+AXG_AO_GATE(uart2, 5);
+AXG_AO_GATE(ir_blaster, 6);
+AXG_AO_GATE(saradc, 7);
+
+static struct clk_regmap ao_clk81 = {
+	.data = &(struct clk_regmap_mux_data) {
+		.offset = AO_RTI_PWR_CNTL_REG0,
+		.mask = 0x1,
+		.shift = 8,
+	},
+	.hw.init = &(struct clk_init_data){
+		.name = "ao_clk81",
+		.ops = &clk_regmap_mux_ro_ops,
+		.parent_names = (const char *[]){ "clk81", "ao_alt_xtal"},
+		.num_parents = 2,
+	},
+};
+
+static struct clk_regmap axg_saradc_mux = {
+	.data = &(struct clk_regmap_mux_data) {
+		.offset = AO_SAR_CLK,
+		.mask = 0x3,
+		.shift = 9,
+	},
+	.hw.init = &(struct clk_init_data){
+		.name = "axg_saradc_mux",
+		.ops = &clk_regmap_mux_ops,
+		.parent_names = (const char *[]){ "xtal", "ao_clk81" },
+		.num_parents = 2,
+	},
+};
+
+static struct clk_regmap axg_saradc_div = {
+	.data = &(struct clk_regmap_div_data) {
+		.offset = AO_SAR_CLK,
+		.shift = 0,
+		.width = 8,
+	},
+	.hw.init = &(struct clk_init_data){
+		.name = "axg_saradc_div",
+		.ops = &clk_regmap_divider_ops,
+		.parent_names = (const char *[]){ "axg_saradc_mux" },
+		.num_parents = 1,
+		.flags = CLK_SET_RATE_PARENT,
+	},
+};
+
+static struct clk_regmap axg_saradc_gate = {
+	.data = &(struct clk_regmap_gate_data) {
+		.offset = AO_SAR_CLK,
+		.bit_idx = 8,
+	},
+	.hw.init = &(struct clk_init_data){
+		.name = "axg_saradc_gate",
+		.ops = &clk_regmap_gate_ops,
+		.parent_names = (const char *[]){ "axg_saradc_div" },
+		.num_parents = 1,
+		.flags = CLK_SET_RATE_PARENT,
+	},
+};
+
+static const unsigned int axg_aoclk_reset[] = {
+	[RESET_AO_REMOTE] = 16,
+	[RESET_AO_I2C_MASTER] = 18,
+	[RESET_AO_I2C_SLAVE] = 19,
+	[RESET_AO_UART1] = 17,
+	[RESET_AO_UART2] = 22,
+	[RESET_AO_IR_BLASTER] = 23,
+};
+
+static struct clk_regmap *axg_aoclk_regmap[] = {
+	[CLKID_AO_REMOTE]	= &remote_ao,
+	[CLKID_AO_I2C_MASTER]	= &i2c_master_ao,
+	[CLKID_AO_I2C_SLAVE]	= &i2c_slave_ao,
+	[CLKID_AO_UART1]	= &uart1_ao,
+	[CLKID_AO_UART2]	= &uart2_ao,
+	[CLKID_AO_IR_BLASTER]	= &ir_blaster_ao,
+	[CLKID_AO_SAR_ADC]	= &saradc_ao,
+	[CLKID_AO_CLK81]	= &ao_clk81,
+	[CLKID_AO_SAR_ADC_SEL]	= &axg_saradc_mux,
+	[CLKID_AO_SAR_ADC_DIV]	= &axg_saradc_div,
+	[CLKID_AO_SAR_ADC_CLK]	= &axg_saradc_gate,
+};
+
+static const struct clk_hw_onecell_data axg_aoclk_onecell_data = {
+	.hws = {
+		[CLKID_AO_REMOTE]	= &remote_ao.hw,
+		[CLKID_AO_I2C_MASTER]	= &i2c_master_ao.hw,
+		[CLKID_AO_I2C_SLAVE]	= &i2c_slave_ao.hw,
+		[CLKID_AO_UART1]	= &uart1_ao.hw,
+		[CLKID_AO_UART2]	= &uart2_ao.hw,
+		[CLKID_AO_IR_BLASTER]	= &ir_blaster_ao.hw,
+		[CLKID_AO_SAR_ADC]	= &saradc_ao.hw,
+		[CLKID_AO_CLK81]	= &ao_clk81.hw,
+		[CLKID_AO_SAR_ADC_SEL]	= &axg_saradc_mux.hw,
+		[CLKID_AO_SAR_ADC_DIV]	= &axg_saradc_div.hw,
+		[CLKID_AO_SAR_ADC_CLK]	= &axg_saradc_gate.hw,
+	},
+	.num = NR_CLKS,
+};
+
+static const struct meson_aoclk_data axg_aoclkc_data = {
+	.reset_reg	= AO_RTI_GEN_CNTL_REG0,
+	.num_reset	= ARRAY_SIZE(axg_aoclk_reset),
+	.reset		= axg_aoclk_reset,
+	.num_clks	= ARRAY_SIZE(axg_aoclk_regmap),
+	.clks		= axg_aoclk_regmap,
+	.hw_data	= &axg_aoclk_onecell_data,
+};
+
+static const struct of_device_id axg_aoclkc_match_table[] = {
+	{
+		.compatible	= "amlogic,meson-axg-aoclkc",
+		.data		= &axg_aoclkc_data,
+	},
+	{ }
+};
+
+static struct platform_driver axg_aoclkc_driver = {
+	.probe		= meson_aoclkc_probe,
+	.driver		= {
+		.name	= "axg-aoclkc",
+		.of_match_table = axg_aoclkc_match_table,
+	},
+};
+
+builtin_platform_driver(axg_aoclkc_driver);
diff --git a/drivers/clk/meson/axg-aoclk.h b/drivers/clk/meson/axg-aoclk.h
new file mode 100644
index 000000000000..396cd3023064
--- /dev/null
+++ b/drivers/clk/meson/axg-aoclk.h
@@ -0,0 +1,31 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2017 BayLibre, SAS
+ * Author: Neil Armstrong <narmstrong at baylibre.com>
+ *
+ * Copyright (c) 2018 Amlogic, inc.
+ * Author: Qiufang Dai <qiufang.dai at amlogic.com>
+ */
+
+#ifndef __AXG_AOCLKC_H
+#define __AXG_AOCLKC_H
+
+#include "meson-aoclk.h"
+
+#define NR_CLKS	11
+/* AO Configuration Clock registers offsets
+ * Register offsets from the data sheet must be multiplied by 4.
+ */
+#define AO_RTI_PWR_CNTL_REG1	0x0C
+#define AO_RTI_PWR_CNTL_REG0	0x10
+#define AO_RTI_GEN_CNTL_REG0	0x40
+#define AO_OSCIN_CNTL		0x58
+#define AO_CRT_CLK_CNTL1	0x68
+#define AO_SAR_CLK		0x90
+#define AO_RTC_ALT_CLK_CNTL0	0x94
+#define AO_RTC_ALT_CLK_CNTL1	0x98
+
+#include <dt-bindings/clock/axg-aoclkc.h>
+#include <dt-bindings/reset/axg-aoclkc.h>
+
+#endif /* __AXG_AOCLKC_H */
-- 
2.15.1



From yixun.lan at amlogic.com  Sat Apr  7 20:19:37 2018
From: yixun.lan at amlogic.com (Yixun Lan)
Date: Sun, 8 Apr 2018 11:19:37 +0800
Subject: [PATCH v4 6/7] clk: meson: drop CLK_SET_RATE_PARENT flag
In-Reply-To: <20180408031938.153474-1-yixun.lan@amlogic.com>
References: <20180408031938.153474-1-yixun.lan@amlogic.com>
Message-ID: <20180408031938.153474-7-yixun.lan@amlogic.com>

The clk81 is not expected to be changed, so drop this flag.

Signed-off-by: Yixun Lan <yixun.lan at amlogic.com>
---
 drivers/clk/meson/gxbb-aoclk.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/clk/meson/gxbb-aoclk.c b/drivers/clk/meson/gxbb-aoclk.c
index 59db8e92f8cf..0a2641d6fd33 100644
--- a/drivers/clk/meson/gxbb-aoclk.c
+++ b/drivers/clk/meson/gxbb-aoclk.c
@@ -70,7 +70,7 @@ static struct clk_regmap _name##_ao = {					\
 		.ops = &clk_regmap_gate_ops,				\
 		.parent_names = (const char *[]){ "clk81" },		\
 		.num_parents = 1,					\
-		.flags = (CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED),	\
+		.flags = CLK_IGNORE_UNUSED,				\
 	},								\
 }
 
-- 
2.15.1



From yixun.lan at amlogic.com  Sat Apr  7 20:19:38 2018
From: yixun.lan at amlogic.com (Yixun Lan)
Date: Sun, 8 Apr 2018 11:19:38 +0800
Subject: [PATCH v4 7/7] clk: meson: drop CLK_IGNORE_UNUSED flag
In-Reply-To: <20180408031938.153474-1-yixun.lan@amlogic.com>
References: <20180408031938.153474-1-yixun.lan@amlogic.com>
Message-ID: <20180408031938.153474-8-yixun.lan@amlogic.com>

Rely on drivers to request the clock explicitly.

Previous the kernel will leave the clock on while
bootloader adready initilized the clock, this wasn't
optimal way, so fix it here.

Signed-off-by: Yixun Lan <yixun.lan at amlogic.com>
---
 drivers/clk/meson/axg-aoclk.c  | 1 -
 drivers/clk/meson/gxbb-aoclk.c | 1 -
 2 files changed, 2 deletions(-)

diff --git a/drivers/clk/meson/axg-aoclk.c b/drivers/clk/meson/axg-aoclk.c
index cb56d809d3df..8457b64b9b7c 100644
--- a/drivers/clk/meson/axg-aoclk.c
+++ b/drivers/clk/meson/axg-aoclk.c
@@ -27,7 +27,6 @@ static struct clk_regmap _name##_ao = {					\
 		.ops = &clk_regmap_gate_ops,				\
 		.parent_names = (const char *[]){ "clk81" },		\
 		.num_parents = 1,					\
-		.flags = CLK_IGNORE_UNUSED,				\
 	},								\
 }
 
diff --git a/drivers/clk/meson/gxbb-aoclk.c b/drivers/clk/meson/gxbb-aoclk.c
index 0a2641d6fd33..aa655044011a 100644
--- a/drivers/clk/meson/gxbb-aoclk.c
+++ b/drivers/clk/meson/gxbb-aoclk.c
@@ -70,7 +70,6 @@ static struct clk_regmap _name##_ao = {					\
 		.ops = &clk_regmap_gate_ops,				\
 		.parent_names = (const char *[]){ "clk81" },		\
 		.num_parents = 1,					\
-		.flags = CLK_IGNORE_UNUSED,				\
 	},								\
 }
 
-- 
2.15.1



From yixun.lan at amlogic.com  Sun Apr  8 04:36:47 2018
From: yixun.lan at amlogic.com (Yixun Lan)
Date: Sun, 8 Apr 2018 11:36:47 +0000
Subject: [PATCH v2] ARM64: dts: meson-axg: enable the eMMC controller
Message-ID: <20180408113647.13543-1-yixun.lan@amlogic.com>

From: Nan Li <nan.li at amlogic.com>

The IP of eMMC controller in AXG is similiar to Meson-GX series.
Here we add the initial support of the HS200 mode with
clock running at 166MHz (to be safe), since we found some eMMC chip
fail to run at 200MHz due to tunning phase error.

Signed-off-by: Nan Li <nan.li at amlogic.com>
Signed-off-by: Yixun Lan <yixun.lan at amlogic.com>

---
Hi Kevin
  Please note this patch actually depend on the eMMC driver here [0].
  Still a few problem to solve, to improve the tuning phase driver to make
the clock running at 200MHz, and to further support the HS400 mode.
Anyway, this patch itself is quite independent.

changes since v1 at [1]:
 - fix missing gpio dt-bindings header

[0] http://lkml.kernel.org/r/20180403100652.41056-1-yixun.lan at amlogic.com
[1] http://lkml.kernel.org/r/20180403102651.60340-1-yixun.lan at amlogic.com
---
 arch/arm64/boot/dts/amlogic/meson-axg-s400.dts | 58 ++++++++++++++++++
 arch/arm64/boot/dts/amlogic/meson-axg.dtsi     | 82 ++++++++++++++++++++++++++
 2 files changed, 140 insertions(+)

diff --git a/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts b/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts
index 57eedced5a51..f67d4e47e641 100644
--- a/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts
+++ b/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts
@@ -15,6 +15,44 @@
 		serial0 = &uart_AO;
 		serial1 = &uart_A;
 	};
+
+	vddio_boot: regulator-vddio_boot {
+		compatible = "regulator-fixed";
+		regulator-name = "VDDIO_BOOT";
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <1800000>;
+	};
+
+	vddao_3v3: regulator-vddao_3v3 {
+		compatible = "regulator-fixed";
+		regulator-name = "VDDAO_3V3";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+	};
+
+	vddio_ao18: regulator-vddio_ao18 {
+		compatible = "regulator-fixed";
+		regulator-name = "VDDIO_AO18";
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <1800000>;
+	};
+
+	vcc_3v3: regulator-vcc_3v3 {
+		compatible = "regulator-fixed";
+		regulator-name = "VCC_3V3";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+	};
+
+	emmc_pwrseq: emmc-pwrseq {
+		compatible = "mmc-pwrseq-emmc";
+		reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>;
+	};
+
+	sdio_pwrseq: sdio-pwrseq {
+		compatible = "mmc-pwrseq-simple";
+		reset-gpios = <&gpio GPIOX_6 GPIO_ACTIVE_LOW>;
+	};
 };
 
 &ethmac {
@@ -47,3 +85,23 @@
 	pinctrl-0 = <&i2c1_z_pins>;
 	pinctrl-names = "default";
 };
+
+/* emmc storage */
+&sd_emmc_c {
+	status = "okay";
+	pinctrl-0 = <&emmc_pins>;
+	pinctrl-1 = <&emmc_clk_gate_pins>;
+	pinctrl-names = "default", "clk-gate";
+
+	bus-width = <8>;
+	cap-sd-highspeed;
+	cap-mmc-highspeed;
+	max-frequency = <180000000>;
+	non-removable;
+	disable-wp;
+	mmc-ddr-1_8v;
+	mmc-hs200-1_8v;
+
+	vmmc-supply = <&vcc_3v3>;
+	vqmmc-supply = <&vddio_boot>;
+};
diff --git a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
index b58808eb3cc8..cb70778c323c 100644
--- a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
@@ -7,6 +7,7 @@
 #include <dt-bindings/interrupt-controller/irq.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 #include <dt-bindings/clock/axg-clkc.h>
+#include <dt-bindings/gpio/meson-axg-gpio.h>
 
 / {
 	compatible = "amlogic,meson-axg";
@@ -113,6 +114,36 @@
 		#size-cells = <2>;
 		ranges;
 
+		apb: apb at ffe00000 {
+			compatible = "simple-bus";
+			reg = <0x0 0xffe00000 0x0 0x200000>;
+			#address-cells = <2>;
+			#size-cells = <2>;
+			ranges = <0x0 0x0 0x0 0xffe00000 0x0 0x200000>;
+
+			sd_emmc_b: sd at 5000 {
+				compatible = "amlogic,meson-axg-mmc";
+				reg = <0x0 0x5000 0x0 0x2000>;
+				interrupts = <GIC_SPI 217 IRQ_TYPE_EDGE_RISING>;
+				status = "disabled";
+				clocks = <&clkc CLKID_SD_EMMC_B>,
+					<&clkc CLKID_SD_EMMC_B_CLK0>,
+					<&clkc CLKID_FCLK_DIV2>;
+				clock-names = "core", "clkin0", "clkin1";
+			};
+
+			sd_emmc_c: mmc at 7000 {
+				compatible = "amlogic,meson-axg-mmc";
+				reg = <0x0 0x7000 0x0 0x2000>;
+				interrupts = <GIC_SPI 218 IRQ_TYPE_EDGE_RISING>;
+				status = "disabled";
+				clocks = <&clkc CLKID_SD_EMMC_C>,
+					<&clkc CLKID_SD_EMMC_C_CLK0>,
+					<&clkc CLKID_FCLK_DIV2>;
+				clock-names = "core", "clkin0", "clkin1";
+			};
+		};
+
 		cbus: bus at ffd00000 {
 			compatible = "simple-bus";
 			reg = <0x0 0xffd00000 0x0 0x25000>;
@@ -309,6 +340,57 @@
 					gpio-ranges = <&pinctrl_periphs 0 0 86>;
 				};
 
+				emmc_pins: emmc {
+					mux {
+						groups = "emmc_nand_d0",
+							"emmc_nand_d1",
+							"emmc_nand_d2",
+							"emmc_nand_d3",
+							"emmc_nand_d4",
+							"emmc_nand_d5",
+							"emmc_nand_d6",
+							"emmc_nand_d7",
+							"emmc_clk",
+							"emmc_cmd",
+							"emmc_ds";
+						function = "emmc";
+					};
+				};
+
+				emmc_clk_gate_pins: emmc_clk_gate {
+					mux {
+						groups = "BOOT_8";
+						function = "gpio_periphs";
+					};
+					cfg-pull-down {
+						pins = "BOOT_8";
+						bias-pull-down;
+					};
+				};
+
+				sdio_pins: sdio {
+					mux {
+						groups = "sdio_d0",
+							"sdio_d1",
+							"sdio_d2",
+							"sdio_d3",
+							"sdio_cmd",
+							"sdio_clk";
+						function = "sdio";
+					};
+				};
+
+				sdio_clk_gate_pins: sdio_clk_gate {
+					mux {
+						groups = "GPIOX_4";
+						function = "gpio_periphs";
+					};
+					cfg-pull-down {
+						pins = "GPIOX_4";
+						bias-pull-down;
+					};
+				};
+
 				eth_rmii_x_pins: eth-x-rmii {
 					mux {
 						groups = "eth_mdio_x",
-- 
2.16.2



From yixun.lan at amlogic.com  Sun Apr  8 07:56:57 2018
From: yixun.lan at amlogic.com (Yixun Lan)
Date: Sun, 8 Apr 2018 14:56:57 +0000
Subject: [PATCH 0/3] irqchip: meson-gpio: add support for Meson-AXG SoCs
Message-ID: <20180408145700.23520-1-yixun.lan@amlogic.com>

  This series try to add GPIO interrupt controller support for Meson-AXG SoCs.
  The first patch is a trivial typo fix, I can fold the first two patches
together if necessary.

Yixun Lan (3):
  dt-bindings: interrupt-controller: fix the double quotes
  dt-bindings: interrupt-controller: New binding for Meson-AXG SoC
  irqchip/meson-gpio: add support for Meson-AXG SoCs

 .../bindings/interrupt-controller/amlogic,meson-gpio-intc.txt | 11 ++++++-----
 drivers/irqchip/irq-meson-gpio.c                              |  5 +++++
 2 files changed, 11 insertions(+), 5 deletions(-)

-- 
2.16.2



From yixun.lan at amlogic.com  Sun Apr  8 07:56:58 2018
From: yixun.lan at amlogic.com (Yixun Lan)
Date: Sun, 8 Apr 2018 14:56:58 +0000
Subject: [PATCH 1/3] dt-bindings: interrupt-controller: fix the double quotes
In-Reply-To: <20180408145700.23520-1-yixun.lan@amlogic.com>
References: <20180408145700.23520-1-yixun.lan@amlogic.com>
Message-ID: <20180408145700.23520-2-yixun.lan@amlogic.com>

The double quotes seems not ASCII type, fix it here.

Signed-off-by: Yixun Lan <yixun.lan at amlogic.com>
---
 .../bindings/interrupt-controller/amlogic,meson-gpio-intc.txt  | 10 +++++-----
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/Documentation/devicetree/bindings/interrupt-controller/amlogic,meson-gpio-intc.txt b/Documentation/devicetree/bindings/interrupt-controller/amlogic,meson-gpio-intc.txt
index a83f9a5734ca..c753d99d43db 100644
--- a/Documentation/devicetree/bindings/interrupt-controller/amlogic,meson-gpio-intc.txt
+++ b/Documentation/devicetree/bindings/interrupt-controller/amlogic,meson-gpio-intc.txt
@@ -9,11 +9,11 @@ number of interrupt exposed depends on the SoC.
 
 Required properties:
 
-- compatible : must have "amlogic,meson8-gpio-intc? and either
-   ?amlogic,meson8-gpio-intc? for meson8 SoCs (S802) or
-   ?amlogic,meson8b-gpio-intc? for meson8b SoCs (S805) or
-   ?amlogic,meson-gxbb-gpio-intc? for GXBB SoCs (S905) or
-   ?amlogic,meson-gxl-gpio-intc? for GXL SoCs (S905X, S912)
+- compatible : must have "amlogic,meson8-gpio-intc" and either
+    "amlogic,meson8-gpio-intc" for meson8 SoCs (S802) or
+    "amlogic,meson8b-gpio-intc" for meson8b SoCs (S805) or
+    "amlogic,meson-gxbb-gpio-intc" for GXBB SoCs (S905) or
+    "amlogic,meson-gxl-gpio-intc" for GXL SoCs (S905X, S912)
 - interrupt-parent : a phandle to the GIC the interrupts are routed to.
    Usually this is provided at the root level of the device tree as it is
    common to most of the SoC.
-- 
2.16.2



From yixun.lan at amlogic.com  Sun Apr  8 07:56:59 2018
From: yixun.lan at amlogic.com (Yixun Lan)
Date: Sun, 8 Apr 2018 14:56:59 +0000
Subject: [PATCH 2/3] dt-bindings: interrupt-controller: New binding for
 Meson-AXG SoC
In-Reply-To: <20180408145700.23520-1-yixun.lan@amlogic.com>
References: <20180408145700.23520-1-yixun.lan@amlogic.com>
Message-ID: <20180408145700.23520-3-yixun.lan@amlogic.com>

Update the dt-binding documentation to support new compatible string
for the GPIO interrupt controller which found in Amlogic's Meson-AXG SoC.

Signed-off-by: Yixun Lan <yixun.lan at amlogic.com>
---
 .../devicetree/bindings/interrupt-controller/amlogic,meson-gpio-intc.txt | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/interrupt-controller/amlogic,meson-gpio-intc.txt b/Documentation/devicetree/bindings/interrupt-controller/amlogic,meson-gpio-intc.txt
index c753d99d43db..89674ad8a097 100644
--- a/Documentation/devicetree/bindings/interrupt-controller/amlogic,meson-gpio-intc.txt
+++ b/Documentation/devicetree/bindings/interrupt-controller/amlogic,meson-gpio-intc.txt
@@ -14,6 +14,7 @@ Required properties:
     "amlogic,meson8b-gpio-intc" for meson8b SoCs (S805) or
     "amlogic,meson-gxbb-gpio-intc" for GXBB SoCs (S905) or
     "amlogic,meson-gxl-gpio-intc" for GXL SoCs (S905X, S912)
+    "amlogic,meson-axg-gpio-intc" for AXG SoCs (A113D, A113X)
 - interrupt-parent : a phandle to the GIC the interrupts are routed to.
    Usually this is provided at the root level of the device tree as it is
    common to most of the SoC.
-- 
2.16.2



From yixun.lan at amlogic.com  Sun Apr  8 07:57:00 2018
From: yixun.lan at amlogic.com (Yixun Lan)
Date: Sun, 8 Apr 2018 14:57:00 +0000
Subject: [PATCH 3/3] irqchip/meson-gpio: add support for Meson-AXG SoCs
In-Reply-To: <20180408145700.23520-1-yixun.lan@amlogic.com>
References: <20180408145700.23520-1-yixun.lan@amlogic.com>
Message-ID: <20180408145700.23520-4-yixun.lan@amlogic.com>

The Meson-AXG SoC uses the same GPIO interrupt controller IP block as the other
Meson SoCs. A total of 100 pins can be spied on, which is the sum of:
- 255:100 Undefined(no interrupt)
- 99:84, 16 pins on bank GPIOY
- 83:61, 23 pins on bank GPIOX
- 60:40, 21 pins on bank GPIOA
- 39:25, 15 pins on bank BOOT
- 24:14, 11 pins on bank GPIOZ
- 13:0 , 14 pins in the AO domain

Signed-off-by: Yixun Lan <yixun.lan at amlogic.com>
---
 drivers/irqchip/irq-meson-gpio.c | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/drivers/irqchip/irq-meson-gpio.c b/drivers/irqchip/irq-meson-gpio.c
index a59bdbc0b9bb..7b531fd075b8 100644
--- a/drivers/irqchip/irq-meson-gpio.c
+++ b/drivers/irqchip/irq-meson-gpio.c
@@ -63,11 +63,16 @@ static const struct meson_gpio_irq_params gxl_params = {
 	.nr_hwirq = 110,
 };
 
+static const struct meson_gpio_irq_params axg_params = {
+	.nr_hwirq = 100,
+};
+
 static const struct of_device_id meson_irq_gpio_matches[] = {
 	{ .compatible = "amlogic,meson8-gpio-intc", .data = &meson8_params },
 	{ .compatible = "amlogic,meson8b-gpio-intc", .data = &meson8b_params },
 	{ .compatible = "amlogic,meson-gxbb-gpio-intc", .data = &gxbb_params },
 	{ .compatible = "amlogic,meson-gxl-gpio-intc", .data = &gxl_params },
+	{ .compatible = "amlogic,meson-axg-gpio-intc", .data = &axg_params },
 	{ }
 };
 
-- 
2.16.2



From yixun.lan at amlogic.com  Sun Apr  8 08:10:45 2018
From: yixun.lan at amlogic.com (Yixun Lan)
Date: Sun, 8 Apr 2018 15:10:45 +0000
Subject: [PATCH] ARM64: dts: meson-axg: add GPIO interrupt controller support
Message-ID: <20180408151045.1138-1-yixun.lan@amlogic.com>

Add the GPIO interrupt controller driver which found in the Amlogic's
Meson-AXG SoC, the controller share the similar ASIC IP as other meson SoCs.

Signed-off-by: Yixun Lan <yixun.lan at amlogic.com>

---
Hi Kevin
 Please note this patch depend on the GPIO interrupt driver here[0]

[0] http://lkml.kernel.org/r/20180408145700.23520-1-yixun.lan at amlogic.com
---
 arch/arm64/boot/dts/amlogic/meson-axg.dtsi | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
index b58808eb3cc8..c1105065de99 100644
--- a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
@@ -120,6 +120,15 @@
 			#size-cells = <2>;
 			ranges = <0x0 0x0 0x0 0xffd00000 0x0 0x25000>;
 
+			gpio_intc: interrupt-controller at f080 {
+				compatible = "amlogic,meson-gpio-intc";
+				reg = <0x0 0xf080 0x0 0x10>;
+				interrupt-controller;
+				#interrupt-cells = <2>;
+				amlogic,channel-interrupts = <64 65 66 67 68 69 70 71>;
+				status = "disabled";
+			};
+
 			pwm_ab: pwm at 1b000 {
 				compatible = "amlogic,meson-axg-ee-pwm";
 				reg = <0x0 0x1b000 0x0 0x20>;
-- 
2.16.2



From sjg at chromium.org  Sun Apr  8 06:50:40 2018
From: sjg at chromium.org (Simon Glass)
Date: Sun, 8 Apr 2018 09:50:40 -0400
Subject: [PATCH u-boot 2/2] ARM: meson: Add cpu info display for GX SoCs
In-Reply-To: <1522230877-21267-3-git-send-email-narmstrong@baylibre.com>
References: <1522230877-21267-1-git-send-email-narmstrong@baylibre.com>
 <1522230877-21267-3-git-send-email-narmstrong@baylibre.com>
Message-ID: <CAPnjgZ0w9v6_6Qiw0uzKzFcTOMThtcQ6C6Q0gnKfHnX9ZZihUQ@mail.gmail.com>

Hi,

On 28 March 2018 at 05:54, Neil Armstrong <narmstrong at baylibre.com> wrote:
> The Amlogic SoCs have a registers containing the die revision
> and packaging type to determine the SoC family and package marketing
> name like S905X for the GXL SoC Family.
> This code is taken for the Linux meson-gx-socinfo driver and adapted
> to U-Boot printing.
>
> Signed-off-by: Neil Armstrong <narmstrong at baylibre.com>
> ---
>  arch/arm/include/asm/arch-meson/gx.h |   1 +
>  arch/arm/mach-meson/Makefile         |   2 +-
>  arch/arm/mach-meson/cpu_info.c       | 105 +++++++++++++++++++++++++++++++++++
>  configs/khadas-vim_defconfig         |   2 +-
>  configs/libretech-cc_defconfig       |   2 +-
>  configs/odroid-c2_defconfig          |   2 +-
>  configs/odroid_defconfig             |   1 +
>  configs/p212_defconfig               |   2 +-
>  8 files changed, 112 insertions(+), 5 deletions(-)
>  create mode 100644 arch/arm/mach-meson/cpu_info.c

Please can you use driver model's CPU interface for this?

Regards,
Simon


From sjg at chromium.org  Sun Apr  8 06:56:54 2018
From: sjg at chromium.org (Simon Glass)
Date: Sun, 8 Apr 2018 09:56:54 -0400
Subject: [PATCH v2 u-boot 2/2] reset: add sandbox test for bulk API
In-Reply-To: <15fe8854-324c-fa49-c26e-eac86ab84f85@baylibre.com>
References: <1522748451-21209-1-git-send-email-narmstrong@baylibre.com>
 <1522748451-21209-3-git-send-email-narmstrong@baylibre.com>
 <CAPnjgZ0+M8pXpi+YYZReY+hgeXv+XTCDuooxkYYegaXVT_O38w@mail.gmail.com>
 <15fe8854-324c-fa49-c26e-eac86ab84f85@baylibre.com>
Message-ID: <CAPnjgZ3rfvq-j2qPFH0fH3zb40A4_Ocd3+Tc30+yBr8wAGGk0w@mail.gmail.com>

Hi Neil,

On 4 April 2018 at 04:45, Neil Armstrong <narmstrong at baylibre.com> wrote:
> On 03/04/2018 19:53, Simon Glass wrote:
>> On 3 April 2018 at 17:40, Neil Armstrong <narmstrong at baylibre.com> wrote:
>>> This patch adds the bulk reset API tests for the sandbox test suite.
>>>
>>> Unlike the main test, it also check the "other" reset signal using the bulk API
>>> and checks if the resets are correctly asserted/deasserted.
>>>
>>> To allow the bulk API to work, and avoid changing the DT, the number of resets
>>> of the sandbox reset controller has been bumped to 101 for the "other" reset
>>> line to be valid.
>>
>> Does it need to be 101, or would, say, 5 be enough?
>
> It could stay at 3, but a dts change should be needed since it declares :
>
> resets = <&resetc 100>, <&resetc 2>;
> reset-names = "other", "test";

Well that is fine if you want to change test.dts - you just need to
make sure you keep the intent.

But you've explained the reason, and it's fine to keep this patch as
is, if you like.

Regards,
Simon


From sean at mess.org  Sun Apr  8 14:19:35 2018
From: sean at mess.org (Sean Young)
Date: Sun,  8 Apr 2018 22:19:35 +0100
Subject: [PATCH v2 0/7] Improve latency of IR decoding
Message-ID: <cover.1523221902.git.sean@mess.org>

The current IR decoding is much too slow. Many IR protocols rely on
a trailing space for decoding (e.g. rc-6 needs to know when the bits
end). The trailing space is generated by the IR timeout, and if this
is longer than required, buttons can feel slow to respond.

The other issue is the keyup timer. IR has no concept of a keyup message,
this is implied by the absence of IR. So, minimising the timeout for
this makes buttons less "sticky"; the are released much quicker.

With these patches in place, using IR with the builtin decoders is much
improved and feels very snappy.

Changes since v1:
 - lost more testing
 - fixed various issues with mce decoder
 - fixed mceusb so it can use better timeout too

Sean Young (7):
  media: rc: set timeout to smallest value required by enabled protocols
  media: rc: add ioctl to get the current timeout
  media: rc: per-protocol repeat period and minimum keyup timer
  media: rc: mce_kbd decoder: low timeout values cause double keydowns
  media: rc: mce_kbd protocol encodes two scancodes
  media: rc: mce_kbd decoder: fix stuck keys
  media: rc: mceusb: allow the timeout to be configurable

 Documentation/media/uapi/rc/lirc-func.rst          |  1 +
 .../media/uapi/rc/lirc-set-rec-timeout.rst         | 14 +++--
 drivers/media/cec/cec-core.c                       |  2 +-
 drivers/media/rc/ir-imon-decoder.c                 |  1 +
 drivers/media/rc/ir-jvc-decoder.c                  |  1 +
 drivers/media/rc/ir-mce_kbd-decoder.c              | 36 +++++++-----
 drivers/media/rc/ir-nec-decoder.c                  |  1 +
 drivers/media/rc/ir-rc5-decoder.c                  |  1 +
 drivers/media/rc/ir-rc6-decoder.c                  |  1 +
 drivers/media/rc/ir-sanyo-decoder.c                |  1 +
 drivers/media/rc/ir-sharp-decoder.c                |  1 +
 drivers/media/rc/ir-sony-decoder.c                 |  1 +
 drivers/media/rc/ir-xmp-decoder.c                  |  1 +
 drivers/media/rc/lirc_dev.c                        |  9 ++-
 drivers/media/rc/mceusb.c                          | 22 +++++++
 drivers/media/rc/rc-core-priv.h                    |  1 +
 drivers/media/rc/rc-ir-raw.c                       | 31 +++++++++-
 drivers/media/rc/rc-main.c                         | 68 +++++++++++-----------
 include/uapi/linux/lirc.h                          |  6 ++
 19 files changed, 144 insertions(+), 55 deletions(-)

-- 
2.14.3



From sean at mess.org  Sun Apr  8 14:19:39 2018
From: sean at mess.org (Sean Young)
Date: Sun,  8 Apr 2018 22:19:39 +0100
Subject: [PATCH v2 4/7] media: rc: mce_kbd decoder: low timeout values cause
 double keydowns
In-Reply-To: <cover.1523221902.git.sean@mess.org>
References: <cover.1523221902.git.sean@mess.org>
Message-ID: <e5bf02f1961fc60e84b74a76a0a7472f4029db26.1523221902.git.sean@mess.org>

The mce keyboard repeats pressed keys every 100ms. If the IR timeout
is set to less than that, we send key up events before the repeat
arrives, so we have key up/key down for each IR repeat.

The keyboard ends any sequence with a 0 scancode, in which case all keys
are cleared so there is no need to run the timeout timer: it only exists
for the case that the final 0 was not received.

Signed-off-by: Sean Young <sean at mess.org>
---
 drivers/media/rc/ir-mce_kbd-decoder.c | 12 +++++++-----
 1 file changed, 7 insertions(+), 5 deletions(-)

diff --git a/drivers/media/rc/ir-mce_kbd-decoder.c b/drivers/media/rc/ir-mce_kbd-decoder.c
index ae4b980c4a16..230b9397aa11 100644
--- a/drivers/media/rc/ir-mce_kbd-decoder.c
+++ b/drivers/media/rc/ir-mce_kbd-decoder.c
@@ -322,11 +322,13 @@ static int ir_mce_kbd_decode(struct rc_dev *dev, struct ir_raw_event ev)
 			scancode = data->body & 0xffff;
 			dev_dbg(&dev->dev, "keyboard data 0x%08x\n",
 				data->body);
-			if (dev->timeout)
-				delay = usecs_to_jiffies(dev->timeout / 1000);
-			else
-				delay = msecs_to_jiffies(100);
-			mod_timer(&data->rx_timeout, jiffies + delay);
+			if (scancode) {
+				delay = nsecs_to_jiffies(dev->timeout) +
+					msecs_to_jiffies(100);
+				mod_timer(&data->rx_timeout, jiffies + delay);
+			} else {
+				del_timer(&data->rx_timeout);
+			}
 			/* Pass data to keyboard buffer parser */
 			ir_mce_kbd_process_keyboard_data(dev, scancode);
 			lsc.rc_proto = RC_PROTO_MCIR2_KBD;
-- 
2.14.3



From sean at mess.org  Sun Apr  8 14:19:37 2018
From: sean at mess.org (Sean Young)
Date: Sun,  8 Apr 2018 22:19:37 +0100
Subject: [PATCH v2 2/7] media: rc: add ioctl to get the current timeout
In-Reply-To: <cover.1523221902.git.sean@mess.org>
References: <cover.1523221902.git.sean@mess.org>
Message-ID: <d2f593f1e78429702036c0a7647c5057d979b7af.1523221902.git.sean@mess.org>

Since the kernel now modifies the timeout, make it possible to retrieve
the current value.

Signed-off-by: Sean Young <sean at mess.org>
---
 Documentation/media/uapi/rc/lirc-func.rst            |  1 +
 Documentation/media/uapi/rc/lirc-set-rec-timeout.rst | 14 +++++++++-----
 drivers/media/rc/lirc_dev.c                          |  7 +++++++
 include/uapi/linux/lirc.h                            |  6 ++++++
 4 files changed, 23 insertions(+), 5 deletions(-)

diff --git a/Documentation/media/uapi/rc/lirc-func.rst b/Documentation/media/uapi/rc/lirc-func.rst
index ddb4620de294..9656423a3f28 100644
--- a/Documentation/media/uapi/rc/lirc-func.rst
+++ b/Documentation/media/uapi/rc/lirc-func.rst
@@ -17,6 +17,7 @@ LIRC Function Reference
     lirc-get-rec-resolution
     lirc-set-send-duty-cycle
     lirc-get-timeout
+    lirc-get-rec-timeout
     lirc-set-rec-timeout
     lirc-set-rec-carrier
     lirc-set-rec-carrier-range
diff --git a/Documentation/media/uapi/rc/lirc-set-rec-timeout.rst b/Documentation/media/uapi/rc/lirc-set-rec-timeout.rst
index b3e16bbdbc90..a833a6a4c25a 100644
--- a/Documentation/media/uapi/rc/lirc-set-rec-timeout.rst
+++ b/Documentation/media/uapi/rc/lirc-set-rec-timeout.rst
@@ -1,19 +1,23 @@
 .. -*- coding: utf-8; mode: rst -*-
 
 .. _lirc_set_rec_timeout:
+.. _lirc_get_rec_timeout:
 
-**************************
-ioctl LIRC_SET_REC_TIMEOUT
-**************************
+***************************************************
+ioctl LIRC_GET_REC_TIMEOUT and LIRC_SET_REC_TIMEOUT
+***************************************************
 
 Name
 ====
 
-LIRC_SET_REC_TIMEOUT - sets the integer value for IR inactivity timeout.
+LIRC_GET_REC_TIMEOUT/LIRC_SET_REC_TIMEOUT - Get/set the integer value for IR inactivity timeout.
 
 Synopsis
 ========
 
+.. c:function:: int ioctl( int fd, LIRC_GET_REC_TIMEOUT, __u32 *timeout )
+    :name: LIRC_GET_REC_TIMEOUT
+
 .. c:function:: int ioctl( int fd, LIRC_SET_REC_TIMEOUT, __u32 *timeout )
     :name: LIRC_SET_REC_TIMEOUT
 
@@ -30,7 +34,7 @@ Arguments
 Description
 ===========
 
-Sets the integer value for IR inactivity timeout.
+Get and set the integer value for IR inactivity timeout.
 
 If supported by the hardware, setting it to 0  disables all hardware timeouts
 and data should be reported as soon as possible. If the exact value
diff --git a/drivers/media/rc/lirc_dev.c b/drivers/media/rc/lirc_dev.c
index 247e6fc3dc0c..6b4755e9fa25 100644
--- a/drivers/media/rc/lirc_dev.c
+++ b/drivers/media/rc/lirc_dev.c
@@ -575,6 +575,13 @@ static long ir_lirc_ioctl(struct file *file, unsigned int cmd,
 		}
 		break;
 
+	case LIRC_GET_REC_TIMEOUT:
+		if (!dev->timeout)
+			ret = -ENOTTY;
+		else
+			val = DIV_ROUND_UP(dev->timeout, 1000);
+		break;
+
 	case LIRC_SET_REC_TIMEOUT_REPORTS:
 		if (!dev->timeout)
 			ret = -ENOTTY;
diff --git a/include/uapi/linux/lirc.h b/include/uapi/linux/lirc.h
index f189931042a7..6b319581882f 100644
--- a/include/uapi/linux/lirc.h
+++ b/include/uapi/linux/lirc.h
@@ -133,6 +133,12 @@
 
 #define LIRC_SET_WIDEBAND_RECEIVER     _IOW('i', 0x00000023, __u32)
 
+/*
+ * Return the recording timeout, which is either set by
+ * the ioctl LIRC_SET_REC_TIMEOUT or by the kernel after setting the protocols.
+ */
+#define LIRC_GET_REC_TIMEOUT	       _IOR('i', 0x00000024, __u32)
+
 /*
  * struct lirc_scancode - decoded scancode with protocol for use with
  *	LIRC_MODE_SCANCODE
-- 
2.14.3



From sean at mess.org  Sun Apr  8 14:19:38 2018
From: sean at mess.org (Sean Young)
Date: Sun,  8 Apr 2018 22:19:38 +0100
Subject: [PATCH v2 3/7] media: rc: per-protocol repeat period and minimum
 keyup timer
In-Reply-To: <cover.1523221902.git.sean@mess.org>
References: <cover.1523221902.git.sean@mess.org>
Message-ID: <e2fd13000586bb0a4e7a2cc07e69ad08319e3519.1523221902.git.sean@mess.org>

Each IR protocol has its own repeat period. We can minimise the keyup
timer to be the protocol period + IR timeout. This makes keys less
"sticky" and makes IR more reactive and nicer to use.

This feature was previously attempted in commit d57ea877af38 ("media: rc:
per-protocol repeat period"), but that did not take the IR timeout into
account, and had to be reverted.

Signed-off-by: Sean Young <sean at mess.org>
---
 drivers/media/cec/cec-core.c |  2 +-
 drivers/media/rc/lirc_dev.c  |  2 +-
 drivers/media/rc/rc-main.c   | 56 +++++++++++++++++++++++---------------------
 3 files changed, 31 insertions(+), 29 deletions(-)

diff --git a/drivers/media/cec/cec-core.c b/drivers/media/cec/cec-core.c
index b0c87f9ea08f..b278ab90b387 100644
--- a/drivers/media/cec/cec-core.c
+++ b/drivers/media/cec/cec-core.c
@@ -322,7 +322,7 @@ struct cec_adapter *cec_allocate_adapter(const struct cec_adap_ops *ops,
 	adap->rc->allowed_protocols = RC_PROTO_BIT_CEC;
 	adap->rc->priv = adap;
 	adap->rc->map_name = RC_MAP_CEC;
-	adap->rc->timeout = MS_TO_NS(100);
+	adap->rc->timeout = MS_TO_NS(550);
 #endif
 	return adap;
 }
diff --git a/drivers/media/rc/lirc_dev.c b/drivers/media/rc/lirc_dev.c
index 6b4755e9fa25..cc58ed78462f 100644
--- a/drivers/media/rc/lirc_dev.c
+++ b/drivers/media/rc/lirc_dev.c
@@ -583,7 +583,7 @@ static long ir_lirc_ioctl(struct file *file, unsigned int cmd,
 		break;
 
 	case LIRC_SET_REC_TIMEOUT_REPORTS:
-		if (!dev->timeout)
+		if (dev->driver_type != RC_DRIVER_IR_RAW)
 			ret = -ENOTTY;
 		else
 			fh->send_timeout_reports = !!val;
diff --git a/drivers/media/rc/rc-main.c b/drivers/media/rc/rc-main.c
index 6a720e9c7aa8..9f4df60f62e1 100644
--- a/drivers/media/rc/rc-main.c
+++ b/drivers/media/rc/rc-main.c
@@ -26,50 +26,50 @@ static const struct {
 	unsigned int repeat_period;
 	unsigned int scancode_bits;
 } protocols[] = {
-	[RC_PROTO_UNKNOWN] = { .name = "unknown", .repeat_period = 250 },
-	[RC_PROTO_OTHER] = { .name = "other", .repeat_period = 250 },
+	[RC_PROTO_UNKNOWN] = { .name = "unknown", .repeat_period = 125 },
+	[RC_PROTO_OTHER] = { .name = "other", .repeat_period = 125 },
 	[RC_PROTO_RC5] = { .name = "rc-5",
-		.scancode_bits = 0x1f7f, .repeat_period = 250 },
+		.scancode_bits = 0x1f7f, .repeat_period = 114 },
 	[RC_PROTO_RC5X_20] = { .name = "rc-5x-20",
-		.scancode_bits = 0x1f7f3f, .repeat_period = 250 },
+		.scancode_bits = 0x1f7f3f, .repeat_period = 114 },
 	[RC_PROTO_RC5_SZ] = { .name = "rc-5-sz",
-		.scancode_bits = 0x2fff, .repeat_period = 250 },
+		.scancode_bits = 0x2fff, .repeat_period = 114 },
 	[RC_PROTO_JVC] = { .name = "jvc",
-		.scancode_bits = 0xffff, .repeat_period = 250 },
+		.scancode_bits = 0xffff, .repeat_period = 125 },
 	[RC_PROTO_SONY12] = { .name = "sony-12",
-		.scancode_bits = 0x1f007f, .repeat_period = 250 },
+		.scancode_bits = 0x1f007f, .repeat_period = 100 },
 	[RC_PROTO_SONY15] = { .name = "sony-15",
-		.scancode_bits = 0xff007f, .repeat_period = 250 },
+		.scancode_bits = 0xff007f, .repeat_period = 100 },
 	[RC_PROTO_SONY20] = { .name = "sony-20",
-		.scancode_bits = 0x1fff7f, .repeat_period = 250 },
+		.scancode_bits = 0x1fff7f, .repeat_period = 100 },
 	[RC_PROTO_NEC] = { .name = "nec",
-		.scancode_bits = 0xffff, .repeat_period = 250 },
+		.scancode_bits = 0xffff, .repeat_period = 110 },
 	[RC_PROTO_NECX] = { .name = "nec-x",
-		.scancode_bits = 0xffffff, .repeat_period = 250 },
+		.scancode_bits = 0xffffff, .repeat_period = 110 },
 	[RC_PROTO_NEC32] = { .name = "nec-32",
-		.scancode_bits = 0xffffffff, .repeat_period = 250 },
+		.scancode_bits = 0xffffffff, .repeat_period = 110 },
 	[RC_PROTO_SANYO] = { .name = "sanyo",
-		.scancode_bits = 0x1fffff, .repeat_period = 250 },
+		.scancode_bits = 0x1fffff, .repeat_period = 125 },
 	[RC_PROTO_MCIR2_KBD] = { .name = "mcir2-kbd",
-		.scancode_bits = 0xffff, .repeat_period = 250 },
+		.scancode_bits = 0xffff, .repeat_period = 100 },
 	[RC_PROTO_MCIR2_MSE] = { .name = "mcir2-mse",
-		.scancode_bits = 0x1fffff, .repeat_period = 250 },
+		.scancode_bits = 0x1fffff, .repeat_period = 100 },
 	[RC_PROTO_RC6_0] = { .name = "rc-6-0",
-		.scancode_bits = 0xffff, .repeat_period = 250 },
+		.scancode_bits = 0xffff, .repeat_period = 114 },
 	[RC_PROTO_RC6_6A_20] = { .name = "rc-6-6a-20",
-		.scancode_bits = 0xfffff, .repeat_period = 250 },
+		.scancode_bits = 0xfffff, .repeat_period = 114 },
 	[RC_PROTO_RC6_6A_24] = { .name = "rc-6-6a-24",
-		.scancode_bits = 0xffffff, .repeat_period = 250 },
+		.scancode_bits = 0xffffff, .repeat_period = 114 },
 	[RC_PROTO_RC6_6A_32] = { .name = "rc-6-6a-32",
-		.scancode_bits = 0xffffffff, .repeat_period = 250 },
+		.scancode_bits = 0xffffffff, .repeat_period = 114 },
 	[RC_PROTO_RC6_MCE] = { .name = "rc-6-mce",
-		.scancode_bits = 0xffff7fff, .repeat_period = 250 },
+		.scancode_bits = 0xffff7fff, .repeat_period = 114 },
 	[RC_PROTO_SHARP] = { .name = "sharp",
-		.scancode_bits = 0x1fff, .repeat_period = 250 },
-	[RC_PROTO_XMP] = { .name = "xmp", .repeat_period = 250 },
-	[RC_PROTO_CEC] = { .name = "cec", .repeat_period = 550 },
+		.scancode_bits = 0x1fff, .repeat_period = 125 },
+	[RC_PROTO_XMP] = { .name = "xmp", .repeat_period = 125 },
+	[RC_PROTO_CEC] = { .name = "cec", .repeat_period = 0 },
 	[RC_PROTO_IMON] = { .name = "imon",
-		.scancode_bits = 0x7fffffff, .repeat_period = 250 },
+		.scancode_bits = 0x7fffffff, .repeat_period = 114 },
 };
 
 /* Used to keep track of known keymaps */
@@ -690,7 +690,8 @@ static void ir_timer_repeat(struct timer_list *t)
 void rc_repeat(struct rc_dev *dev)
 {
 	unsigned long flags;
-	unsigned int timeout = protocols[dev->last_protocol].repeat_period;
+	unsigned int timeout = nsecs_to_jiffies(dev->timeout) +
+		msecs_to_jiffies(protocols[dev->last_protocol].repeat_period);
 	struct lirc_scancode sc = {
 		.scancode = dev->last_scancode, .rc_proto = dev->last_protocol,
 		.keycode = dev->keypressed ? dev->last_keycode : KEY_RESERVED,
@@ -706,7 +707,7 @@ void rc_repeat(struct rc_dev *dev)
 	input_sync(dev->input_dev);
 
 	if (dev->keypressed) {
-		dev->keyup_jiffies = jiffies + msecs_to_jiffies(timeout);
+		dev->keyup_jiffies = jiffies + timeout;
 		mod_timer(&dev->timer_keyup, dev->keyup_jiffies);
 	}
 
@@ -801,7 +802,7 @@ void rc_keydown(struct rc_dev *dev, enum rc_proto protocol, u32 scancode,
 	ir_do_keydown(dev, protocol, scancode, keycode, toggle);
 
 	if (dev->keypressed) {
-		dev->keyup_jiffies = jiffies +
+		dev->keyup_jiffies = jiffies + nsecs_to_jiffies(dev->timeout) +
 			msecs_to_jiffies(protocols[protocol].repeat_period);
 		mod_timer(&dev->timer_keyup, dev->keyup_jiffies);
 	}
@@ -1647,6 +1648,7 @@ struct rc_dev *rc_allocate_device(enum rc_driver_type type)
 		dev->input_dev->setkeycode = ir_setkeycode;
 		input_set_drvdata(dev->input_dev, dev);
 
+		dev->timeout = IR_DEFAULT_TIMEOUT;
 		timer_setup(&dev->timer_keyup, ir_timer_keyup, 0);
 		timer_setup(&dev->timer_repeat, ir_timer_repeat, 0);
 
-- 
2.14.3



From sean at mess.org  Sun Apr  8 14:19:36 2018
From: sean at mess.org (Sean Young)
Date: Sun,  8 Apr 2018 22:19:36 +0100
Subject: [PATCH v2 1/7] media: rc: set timeout to smallest value required by
 enabled protocols
In-Reply-To: <cover.1523221902.git.sean@mess.org>
References: <cover.1523221902.git.sean@mess.org>
Message-ID: <88fe6a3110a122855b5d336d74aee778fd15616f.1523221902.git.sean@mess.org>

The longer the IR timeout, the longer the rc device waits until delivering
the trailing space. So, by reducing this timeout, we reduce the delay for
the last scancode to be delivered.

Note that the lirc daemon disables all protocols, in which case we revert
back to the default value.

Signed-off-by: Sean Young <sean at mess.org>
---
 drivers/media/rc/ir-imon-decoder.c    |  1 +
 drivers/media/rc/ir-jvc-decoder.c     |  1 +
 drivers/media/rc/ir-mce_kbd-decoder.c |  1 +
 drivers/media/rc/ir-nec-decoder.c     |  1 +
 drivers/media/rc/ir-rc5-decoder.c     |  1 +
 drivers/media/rc/ir-rc6-decoder.c     |  1 +
 drivers/media/rc/ir-sanyo-decoder.c   |  1 +
 drivers/media/rc/ir-sharp-decoder.c   |  1 +
 drivers/media/rc/ir-sony-decoder.c    |  1 +
 drivers/media/rc/ir-xmp-decoder.c     |  1 +
 drivers/media/rc/rc-core-priv.h       |  1 +
 drivers/media/rc/rc-ir-raw.c          | 31 ++++++++++++++++++++++++++++++-
 drivers/media/rc/rc-main.c            | 12 ++++++------
 13 files changed, 47 insertions(+), 7 deletions(-)

diff --git a/drivers/media/rc/ir-imon-decoder.c b/drivers/media/rc/ir-imon-decoder.c
index a1ff06a26542..9024b359e5ee 100644
--- a/drivers/media/rc/ir-imon-decoder.c
+++ b/drivers/media/rc/ir-imon-decoder.c
@@ -170,6 +170,7 @@ static struct ir_raw_handler imon_handler = {
 	.decode		= ir_imon_decode,
 	.encode		= ir_imon_encode,
 	.carrier	= 38000,
+	.max_space	= IMON_UNIT * IMON_BITS * 2,
 };
 
 static int __init ir_imon_decode_init(void)
diff --git a/drivers/media/rc/ir-jvc-decoder.c b/drivers/media/rc/ir-jvc-decoder.c
index 8cb68ae43282..190c690b14f8 100644
--- a/drivers/media/rc/ir-jvc-decoder.c
+++ b/drivers/media/rc/ir-jvc-decoder.c
@@ -213,6 +213,7 @@ static struct ir_raw_handler jvc_handler = {
 	.decode		= ir_jvc_decode,
 	.encode		= ir_jvc_encode,
 	.carrier	= 38000,
+	.max_space	= JVC_TRAILER_SPACE,
 };
 
 static int __init ir_jvc_decode_init(void)
diff --git a/drivers/media/rc/ir-mce_kbd-decoder.c b/drivers/media/rc/ir-mce_kbd-decoder.c
index c110984ca671..ae4b980c4a16 100644
--- a/drivers/media/rc/ir-mce_kbd-decoder.c
+++ b/drivers/media/rc/ir-mce_kbd-decoder.c
@@ -475,6 +475,7 @@ static struct ir_raw_handler mce_kbd_handler = {
 	.raw_register	= ir_mce_kbd_register,
 	.raw_unregister	= ir_mce_kbd_unregister,
 	.carrier	= 36000,
+	.max_space	= MCIR2_MAX_LEN,
 };
 
 static int __init ir_mce_kbd_decode_init(void)
diff --git a/drivers/media/rc/ir-nec-decoder.c b/drivers/media/rc/ir-nec-decoder.c
index 21647b809e6f..fac12f867a81 100644
--- a/drivers/media/rc/ir-nec-decoder.c
+++ b/drivers/media/rc/ir-nec-decoder.c
@@ -253,6 +253,7 @@ static struct ir_raw_handler nec_handler = {
 	.decode		= ir_nec_decode,
 	.encode		= ir_nec_encode,
 	.carrier	= 38000,
+	.max_space	= NEC_TRAILER_SPACE,
 };
 
 static int __init ir_nec_decode_init(void)
diff --git a/drivers/media/rc/ir-rc5-decoder.c b/drivers/media/rc/ir-rc5-decoder.c
index 74d3b859c3a2..711068c8de90 100644
--- a/drivers/media/rc/ir-rc5-decoder.c
+++ b/drivers/media/rc/ir-rc5-decoder.c
@@ -274,6 +274,7 @@ static struct ir_raw_handler rc5_handler = {
 	.decode		= ir_rc5_decode,
 	.encode		= ir_rc5_encode,
 	.carrier	= 36000,
+	.max_space	= RC5_TRAILER,
 };
 
 static int __init ir_rc5_decode_init(void)
diff --git a/drivers/media/rc/ir-rc6-decoder.c b/drivers/media/rc/ir-rc6-decoder.c
index 8314da32453f..9cc4820878c7 100644
--- a/drivers/media/rc/ir-rc6-decoder.c
+++ b/drivers/media/rc/ir-rc6-decoder.c
@@ -394,6 +394,7 @@ static struct ir_raw_handler rc6_handler = {
 	.decode		= ir_rc6_decode,
 	.encode		= ir_rc6_encode,
 	.carrier	= 36000,
+	.max_space	= RC6_SUFFIX_SPACE,
 };
 
 static int __init ir_rc6_decode_init(void)
diff --git a/drivers/media/rc/ir-sanyo-decoder.c b/drivers/media/rc/ir-sanyo-decoder.c
index 4efe6db5376a..e72787b446c9 100644
--- a/drivers/media/rc/ir-sanyo-decoder.c
+++ b/drivers/media/rc/ir-sanyo-decoder.c
@@ -210,6 +210,7 @@ static struct ir_raw_handler sanyo_handler = {
 	.decode		= ir_sanyo_decode,
 	.encode		= ir_sanyo_encode,
 	.carrier	= 38000,
+	.max_space	= SANYO_TRAILER_SPACE,
 };
 
 static int __init ir_sanyo_decode_init(void)
diff --git a/drivers/media/rc/ir-sharp-decoder.c b/drivers/media/rc/ir-sharp-decoder.c
index 6a38c50566a4..e7e3841a6eb0 100644
--- a/drivers/media/rc/ir-sharp-decoder.c
+++ b/drivers/media/rc/ir-sharp-decoder.c
@@ -226,6 +226,7 @@ static struct ir_raw_handler sharp_handler = {
 	.decode		= ir_sharp_decode,
 	.encode		= ir_sharp_encode,
 	.carrier	= 38000,
+	.max_space	= SHARP_ECHO_SPACE,
 };
 
 static int __init ir_sharp_decode_init(void)
diff --git a/drivers/media/rc/ir-sony-decoder.c b/drivers/media/rc/ir-sony-decoder.c
index 6764ec9de646..598bae8d8ffb 100644
--- a/drivers/media/rc/ir-sony-decoder.c
+++ b/drivers/media/rc/ir-sony-decoder.c
@@ -224,6 +224,7 @@ static struct ir_raw_handler sony_handler = {
 	.decode		= ir_sony_decode,
 	.encode		= ir_sony_encode,
 	.carrier	= 40000,
+	.max_space	= SONY_TRAILER_SPACE,
 };
 
 static int __init ir_sony_decode_init(void)
diff --git a/drivers/media/rc/ir-xmp-decoder.c b/drivers/media/rc/ir-xmp-decoder.c
index 58b47af1a763..e005a75a86fe 100644
--- a/drivers/media/rc/ir-xmp-decoder.c
+++ b/drivers/media/rc/ir-xmp-decoder.c
@@ -199,6 +199,7 @@ static int ir_xmp_decode(struct rc_dev *dev, struct ir_raw_event ev)
 static struct ir_raw_handler xmp_handler = {
 	.protocols	= RC_PROTO_BIT_XMP,
 	.decode		= ir_xmp_decode,
+	.max_space	= XMP_TRAILER_SPACE,
 };
 
 static int __init ir_xmp_decode_init(void)
diff --git a/drivers/media/rc/rc-core-priv.h b/drivers/media/rc/rc-core-priv.h
index e0e6a17460f6..8c38941295b8 100644
--- a/drivers/media/rc/rc-core-priv.h
+++ b/drivers/media/rc/rc-core-priv.h
@@ -37,6 +37,7 @@ struct ir_raw_handler {
 	int (*encode)(enum rc_proto protocol, u32 scancode,
 		      struct ir_raw_event *events, unsigned int max);
 	u32 carrier;
+	u32 max_space;
 
 	/* These two should only be used by the mce kbd decoder */
 	int (*raw_register)(struct rc_dev *dev);
diff --git a/drivers/media/rc/rc-ir-raw.c b/drivers/media/rc/rc-ir-raw.c
index 374f83105a23..1ce008dc7f47 100644
--- a/drivers/media/rc/rc-ir-raw.c
+++ b/drivers/media/rc/rc-ir-raw.c
@@ -233,7 +233,36 @@ ir_raw_get_allowed_protocols(void)
 
 static int change_protocol(struct rc_dev *dev, u64 *rc_proto)
 {
-	/* the caller will update dev->enabled_protocols */
+	struct ir_raw_handler *handler;
+	u32 timeout = 0;
+
+	if (!dev->max_timeout)
+		return 0;
+
+	mutex_lock(&ir_raw_handler_lock);
+	list_for_each_entry(handler, &ir_raw_handler_list, list) {
+		if (handler->protocols & *rc_proto) {
+			if (timeout < handler->max_space)
+				timeout = handler->max_space;
+		}
+	}
+	mutex_unlock(&ir_raw_handler_lock);
+
+	if (timeout == 0)
+		timeout = IR_DEFAULT_TIMEOUT;
+	else
+		timeout += MS_TO_NS(20);
+
+	if (timeout < dev->min_timeout)
+		timeout = dev->min_timeout;
+	else if (timeout > dev->max_timeout)
+		timeout = dev->max_timeout;
+
+	if (dev->s_timeout)
+		dev->s_timeout(dev, timeout);
+	else
+		dev->timeout = timeout;
+
 	return 0;
 }
 
diff --git a/drivers/media/rc/rc-main.c b/drivers/media/rc/rc-main.c
index b67be33bd62f..6a720e9c7aa8 100644
--- a/drivers/media/rc/rc-main.c
+++ b/drivers/media/rc/rc-main.c
@@ -1241,6 +1241,9 @@ static ssize_t store_protocols(struct device *device,
 	if (rc < 0)
 		goto out;
 
+	if (dev->driver_type == RC_DRIVER_IR_RAW)
+		ir_raw_load_modules(&new_protocols);
+
 	rc = dev->change_protocol(dev, &new_protocols);
 	if (rc < 0) {
 		dev_dbg(&dev->dev, "Error setting protocols to 0x%llx\n",
@@ -1248,9 +1251,6 @@ static ssize_t store_protocols(struct device *device,
 		goto out;
 	}
 
-	if (dev->driver_type == RC_DRIVER_IR_RAW)
-		ir_raw_load_modules(&new_protocols);
-
 	if (new_protocols != old_protocols) {
 		*current_protocols = new_protocols;
 		dev_dbg(&dev->dev, "Protocols changed to 0x%llx\n",
@@ -1735,6 +1735,9 @@ static int rc_prepare_rx_device(struct rc_dev *dev)
 	if (dev->driver_type == RC_DRIVER_SCANCODE && !dev->change_protocol)
 		dev->enabled_protocols = dev->allowed_protocols;
 
+	if (dev->driver_type == RC_DRIVER_IR_RAW)
+		ir_raw_load_modules(&rc_proto);
+
 	if (dev->change_protocol) {
 		rc = dev->change_protocol(dev, &rc_proto);
 		if (rc < 0)
@@ -1742,9 +1745,6 @@ static int rc_prepare_rx_device(struct rc_dev *dev)
 		dev->enabled_protocols = rc_proto;
 	}
 
-	if (dev->driver_type == RC_DRIVER_IR_RAW)
-		ir_raw_load_modules(&rc_proto);
-
 	set_bit(EV_KEY, dev->input_dev->evbit);
 	set_bit(EV_REP, dev->input_dev->evbit);
 	set_bit(EV_MSC, dev->input_dev->evbit);
-- 
2.14.3



From sean at mess.org  Sun Apr  8 14:19:41 2018
From: sean at mess.org (Sean Young)
Date: Sun,  8 Apr 2018 22:19:41 +0100
Subject: [PATCH v2 6/7] media: rc: mce_kbd decoder: fix stuck keys
In-Reply-To: <cover.1523221902.git.sean@mess.org>
References: <cover.1523221902.git.sean@mess.org>
Message-ID: <6e04a64c9be3f571f4927f0ffada67be5071db88.1523221902.git.sean@mess.org>

The MCE Remote sends a 0 scancode when keys are released. If this is not
received or decoded, then keys can get "stuck"; the keyup event is not
sent since the input_sync() is missing from the timeout handler.

Cc: stable at vger.kernel.org
Signed-off-by: Sean Young <sean at mess.org>
---
 drivers/media/rc/ir-mce_kbd-decoder.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/media/rc/ir-mce_kbd-decoder.c b/drivers/media/rc/ir-mce_kbd-decoder.c
index dcdba83290d2..a6adf54461e9 100644
--- a/drivers/media/rc/ir-mce_kbd-decoder.c
+++ b/drivers/media/rc/ir-mce_kbd-decoder.c
@@ -130,6 +130,8 @@ static void mce_kbd_rx_timeout(struct timer_list *t)
 
 	for (i = 0; i < MCIR2_MASK_KEYS_START; i++)
 		input_report_key(raw->mce_kbd.idev, kbd_keycodes[i], 0);
+
+	input_sync(raw->mce_kbd.idev);
 }
 
 static enum mce_kbd_mode mce_kbd_mode(struct mce_kbd_dec *data)
-- 
2.14.3



From sean at mess.org  Sun Apr  8 14:19:42 2018
From: sean at mess.org (Sean Young)
Date: Sun,  8 Apr 2018 22:19:42 +0100
Subject: [PATCH v2 7/7] media: rc: mceusb: allow the timeout to be configurable
In-Reply-To: <cover.1523221902.git.sean@mess.org>
References: <cover.1523221902.git.sean@mess.org>
Message-ID: <02b5dac3b27169c6e6a4a070a2569b33fef47bbe.1523221902.git.sean@mess.org>

mceusb devices have a default timeout of 100ms, but this can be changed.

Signed-off-by: Sean Young <sean at mess.org>
---
 drivers/media/rc/mceusb.c | 22 ++++++++++++++++++++++
 1 file changed, 22 insertions(+)

diff --git a/drivers/media/rc/mceusb.c b/drivers/media/rc/mceusb.c
index 69ba57372c05..c97cb2eb1c5f 100644
--- a/drivers/media/rc/mceusb.c
+++ b/drivers/media/rc/mceusb.c
@@ -982,6 +982,25 @@ static int mceusb_set_tx_carrier(struct rc_dev *dev, u32 carrier)
 	return 0;
 }
 
+static int mceusb_set_timeout(struct rc_dev *dev, unsigned int timeout)
+{
+	u8 cmdbuf[4] = { MCE_CMD_PORT_IR, MCE_CMD_SETIRTIMEOUT, 0, 0 };
+	struct mceusb_dev *ir = dev->priv;
+	unsigned int units;
+
+	units = DIV_ROUND_CLOSEST(timeout, US_TO_NS(MCE_TIME_UNIT));
+
+	cmdbuf[2] = units >> 8;
+	cmdbuf[3] = units;
+
+	mce_async_out(ir, cmdbuf, sizeof(cmdbuf));
+
+	/* get receiver timeout value */
+	mce_async_out(ir, GET_RX_TIMEOUT, sizeof(GET_RX_TIMEOUT));
+
+	return 0;
+}
+
 /*
  * Select or deselect the 2nd receiver port.
  * Second receiver is learning mode, wide-band, short-range receiver.
@@ -1415,7 +1434,10 @@ static struct rc_dev *mceusb_init_rc_dev(struct mceusb_dev *ir)
 	rc->dev.parent = dev;
 	rc->priv = ir;
 	rc->allowed_protocols = RC_PROTO_BIT_ALL_IR_DECODER;
+	rc->min_timeout = US_TO_NS(MCE_TIME_UNIT);
 	rc->timeout = MS_TO_NS(100);
+	rc->max_timeout = 10 * IR_DEFAULT_TIMEOUT;
+	rc->s_timeout = mceusb_set_timeout;
 	if (!ir->flags.no_tx) {
 		rc->s_tx_mask = mceusb_set_tx_mask;
 		rc->s_tx_carrier = mceusb_set_tx_carrier;
-- 
2.14.3



From sean at mess.org  Sun Apr  8 14:19:40 2018
From: sean at mess.org (Sean Young)
Date: Sun,  8 Apr 2018 22:19:40 +0100
Subject: [PATCH v2 5/7] media: rc: mce_kbd protocol encodes two scancodes
In-Reply-To: <cover.1523221902.git.sean@mess.org>
References: <cover.1523221902.git.sean@mess.org>
Message-ID: <83e420c4229770af4a014c0c8034384ab15dde1e.1523221902.git.sean@mess.org>

If two keys are pressed, then both keys are encoded in the scancode. This
makes the mce keyboard more responsive.

Signed-off-by: Sean Young <sean at mess.org>
---
 drivers/media/rc/ir-mce_kbd-decoder.c | 21 ++++++++++++---------
 drivers/media/rc/rc-main.c            |  2 +-
 2 files changed, 13 insertions(+), 10 deletions(-)

diff --git a/drivers/media/rc/ir-mce_kbd-decoder.c b/drivers/media/rc/ir-mce_kbd-decoder.c
index 230b9397aa11..dcdba83290d2 100644
--- a/drivers/media/rc/ir-mce_kbd-decoder.c
+++ b/drivers/media/rc/ir-mce_kbd-decoder.c
@@ -147,13 +147,14 @@ static enum mce_kbd_mode mce_kbd_mode(struct mce_kbd_dec *data)
 static void ir_mce_kbd_process_keyboard_data(struct rc_dev *dev, u32 scancode)
 {
 	struct mce_kbd_dec *data = &dev->raw->mce_kbd;
-	u8 keydata   = (scancode >> 8) & 0xff;
+	u8 keydata1  = (scancode >> 8) & 0xff;
+	u8 keydata2  = (scancode >> 16) & 0xff;
 	u8 shiftmask = scancode & 0xff;
-	unsigned char keycode, maskcode;
+	unsigned char maskcode;
 	int i, keystate;
 
-	dev_dbg(&dev->dev, "keyboard: keydata = 0x%02x, shiftmask = 0x%02x\n",
-		keydata, shiftmask);
+	dev_dbg(&dev->dev, "keyboard: keydata2 = 0x%02x, keydata1 = 0x%02x, shiftmask = 0x%02x\n",
+		keydata2, keydata1, shiftmask);
 
 	for (i = 0; i < 7; i++) {
 		maskcode = kbd_keycodes[MCIR2_MASK_KEYS_START + i];
@@ -164,10 +165,12 @@ static void ir_mce_kbd_process_keyboard_data(struct rc_dev *dev, u32 scancode)
 		input_report_key(data->idev, maskcode, keystate);
 	}
 
-	if (keydata) {
-		keycode = kbd_keycodes[keydata];
-		input_report_key(data->idev, keycode, 1);
-	} else {
+	if (keydata1)
+		input_report_key(data->idev, kbd_keycodes[keydata1], 1);
+	if (keydata2)
+		input_report_key(data->idev, kbd_keycodes[keydata2], 1);
+
+	if (!keydata1 && !keydata2) {
 		for (i = 0; i < MCIR2_MASK_KEYS_START; i++)
 			input_report_key(data->idev, kbd_keycodes[i], 0);
 	}
@@ -319,7 +322,7 @@ static int ir_mce_kbd_decode(struct rc_dev *dev, struct ir_raw_event ev)
 
 		switch (data->wanted_bits) {
 		case MCIR2_KEYBOARD_NBITS:
-			scancode = data->body & 0xffff;
+			scancode = data->body & 0xffffff;
 			dev_dbg(&dev->dev, "keyboard data 0x%08x\n",
 				data->body);
 			if (scancode) {
diff --git a/drivers/media/rc/rc-main.c b/drivers/media/rc/rc-main.c
index 9f4df60f62e1..b7071bde670a 100644
--- a/drivers/media/rc/rc-main.c
+++ b/drivers/media/rc/rc-main.c
@@ -51,7 +51,7 @@ static const struct {
 	[RC_PROTO_SANYO] = { .name = "sanyo",
 		.scancode_bits = 0x1fffff, .repeat_period = 125 },
 	[RC_PROTO_MCIR2_KBD] = { .name = "mcir2-kbd",
-		.scancode_bits = 0xffff, .repeat_period = 100 },
+		.scancode_bits = 0xffffff, .repeat_period = 100 },
 	[RC_PROTO_MCIR2_MSE] = { .name = "mcir2-mse",
 		.scancode_bits = 0x1fffff, .repeat_period = 100 },
 	[RC_PROTO_RC6_0] = { .name = "rc-6-0",
-- 
2.14.3



From martin.blumenstingl at googlemail.com  Sun Apr  8 14:27:42 2018
From: martin.blumenstingl at googlemail.com (Martin Blumenstingl)
Date: Sun,  8 Apr 2018 23:27:42 +0200
Subject: [PATCH usb v5 5/6] usb: core: phy: add missing forward declaration
 for "struct device"
In-Reply-To: <20180408212743.22934-1-martin.blumenstingl@googlemail.com>
References: <20180408212743.22934-1-martin.blumenstingl@googlemail.com>
Message-ID: <20180408212743.22934-6-martin.blumenstingl@googlemail.com>

Currently hcd.c is the only consumer of the usb_phy_roothub logic. This
already includes the required header files so struct device is known.
However, future consumers might not know about struct device.
Add a forward declaration for struct device to fix potential future
consumers which don't include any of the struct device API headers.

Fixes: 07dbff0ddbd86c ("usb: core: add a wrapper for the USB PHYs on the HCD")
Suggested-by: Masahiro Yamada <yamada.masahiro at socionext.com>
Signed-off-by: Martin Blumenstingl <martin.blumenstingl at googlemail.com>
---
 drivers/usb/core/phy.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/usb/core/phy.h b/drivers/usb/core/phy.h
index 605555901d44..bbc969383074 100644
--- a/drivers/usb/core/phy.h
+++ b/drivers/usb/core/phy.h
@@ -1,3 +1,4 @@
+struct device;
 struct usb_phy_roothub;
 
 struct usb_phy_roothub *usb_phy_roothub_alloc(struct device *dev);
-- 
2.17.0



From martin.blumenstingl at googlemail.com  Sun Apr  8 14:27:37 2018
From: martin.blumenstingl at googlemail.com (Martin Blumenstingl)
Date: Sun,  8 Apr 2018 23:27:37 +0200
Subject: [PATCH usb v5 0/6] usb/core/phy fixes for v4.17
Message-ID: <20180408212743.22934-1-martin.blumenstingl@googlemail.com>

This is a follow-up to my previous series "initialize (multiple) PHYs
for a HCD": [0].

Roger Quadros reported [1] that it "is breaking low power cases on TI
SoCs when USB is in host mode". He further explains that "Not doing the
phy_exit() here [when entering suspend] leaves the clocks enabled on
our SoC and we're no longer able to reach low power states on system
suspend."
Chunfeng Yun from Mediatek noted [2] that we cannot unconditionally call
phy_exit while entering system suspend, because this would "disconnect
plugged devices on MTK platforms, due to re-initialize u2 phys when
resume"

In the discussion (which followed Roger's bug report: [1]) Roger,
Chunfeng and me came to the conclusion that we can fix suspend on the
TI SoCs without breaking it on the Mediatek SoCs by extending the
suspend and resume code in usb/core/phy.c by checking whether the USB
controller can wake up the system (which is the case for the Mediatek
MTU3 controller, but now for the dwc3 controller used on the TI SoCs):
- if the controller can wake up the system (Mediatek MTU3 use-case) we
  only call usb_phy_roothub_power_off (which calls phy_power_off) when
  entering system suspend
- if the controller however cannot wake up the system (dwc3 on TI SoCs)
  we additionally call usb_phy_roothub_exit (which calls phy_exit) when
  entering system suspend
- (we undo the previous steps during system resume)

The goal of this series is to fix the issue reported by Roger without
breaking suspend/resume on the Mediatek SoCs.
Since I neither have a TI nor a Mediatek device I am sending this as
RFC. I have tested it on an Amlogic Meson GXM board (Khadas VIM2) which
does NOT support suspend/resume yet.

Additionally Stefan Wahren reported [7] that booting on a Raspberry Pi
with CONFIG_GENERIC_PHY being disabled (which is the case for
bcm2835_defconfig) breaks USB. A fix for this is also included.


changes since v4 at [8]
- updated series title since it now includes fixes for other
  functionality than suspend
- rebased on top of f8cf2f16a7c95a from Linus' tree -> I will re-send
  an updated version once v4.17-rc1 is out, I just sent it early to
  get some feedback early!
- included patch [3] "usb: core: phy: fix return value of
  usb_phy_roothub_exit()" in this series
- fix the logic if CONFIG_GENERIC_PHY is disabled (as reported by
  Stefan Wahren, new patch #4)
- two minor coding style fixes as suggested by Masahiro Yamada (new
  patches #4 and #5)

changes since RFC v3 at [6]:
- added Chunfeng Yun's Tested-by and Roger Quadros' Reviewed-by (thank
  you!)
- dropped RFC prefix

changes since RFC v2 at [5]:
- add missing INIT_LIST_HEAD call in usb_phy_roothub_add_phy (affects
  patch #1 - spotted by Roger Quadros, thank you!)
- fixed swapped conditions using device_may_wakeup() in
  usb_phy_roothub_resume because we need to call usb_phy_roothub_init
  if the controller cannot wake up the device (affects patch #2, spotted
  by Chunfeng Yun, thank you!)
- simplified the error condition to "undo" usb_phy_roothub_init if
  usb_phy_roothub_power_on failed in usb_phy_roothub_resume (suggested
  by Chunfeng Yun)
- updated the commit message (using Roger's wording) because (quote from
  Roger "it doesn't prevent the system from entering suspend but just
  prevents the system from reaching lowest power levels in the suspend
  state."

Changes since RFC v1 (blob attachments) at [4]:
- use device_may_wakeup instead of device_can_wakeup as suggested by
  Roger Quadros
- use the controller device from hcd->self.controller as suggested by
  Chunfeng Yun
- compile time fixes thanks to Roger Quadros
- if usb_phy_roothub_power_on in usb_phy_roothub_resume failes then
  we now call usb_phy_roothub_exit to keep the PHYs in the correct
  state if usb_phy_roothub_resume partially failed


[0] http://lists.infradead.org/pipermail/linux-amlogic/2018-March/006599.html
[1] http://lists.infradead.org/pipermail/linux-amlogic/2018-March/006737.html
[2] http://lists.infradead.org/pipermail/linux-amlogic/2018-March/006758.html
[3] http://lists.infradead.org/pipermail/linux-amlogic/2018-March/006819.html
[4] http://lists.infradead.org/pipermail/linux-amlogic/2018-March/006794.html
[5] http://lists.infradead.org/pipermail/linux-amlogic/2018-March/006820.html
[6] http://lists.infradead.org/pipermail/linux-amlogic/2018-March/006847.html
[7] https://www.spinics.net/lists/linux-usb/msg167472.html
[8] http://lists.infradead.org/pipermail/linux-amlogic/2018-March/006882.html


Martin Blumenstingl (6):
  usb: core: phy: fix return value of usb_phy_roothub_exit()
  usb: core: split usb_phy_roothub_{init,alloc}
  usb: core: use phy_exit during suspend if wake up is not supported
  usb: core: phy: make it a no-op if CONFIG_GENERIC_PHY is disabled
  usb: core: phy: add missing forward declaration for "struct device"
  usb: core: phy: add the SPDX-License-Identifier and include guard

 drivers/usb/core/hcd.c | 18 +++++---
 drivers/usb/core/phy.c | 93 ++++++++++++++++++++++++++++++------------
 drivers/usb/core/phy.h | 22 +++++++++-
 3 files changed, 99 insertions(+), 34 deletions(-)

-- 
2.17.0



From martin.blumenstingl at googlemail.com  Sun Apr  8 14:27:38 2018
From: martin.blumenstingl at googlemail.com (Martin Blumenstingl)
Date: Sun,  8 Apr 2018 23:27:38 +0200
Subject: [PATCH usb v5 1/6] usb: core: phy: fix return value of
 usb_phy_roothub_exit()
In-Reply-To: <20180408212743.22934-1-martin.blumenstingl@googlemail.com>
References: <20180408212743.22934-1-martin.blumenstingl@googlemail.com>
Message-ID: <20180408212743.22934-2-martin.blumenstingl@googlemail.com>

usb_phy_roothub_exit() should return the error code from the phy_exit()
call if exiting the PHY failed.
However, since a wrong variable is used usb_phy_roothub_exit() currently
always returns 0, even if one of the phy_exit calls returned an error.
Clang also reports this bug:
kernel/drivers/usb/core/phy.c:114:8: warning: explicitly assigning value of
variable of type 'int' to itself [-Wself-assign] error, forbidden
warning: phy.c:114

Fix this by assigning the error code from phy_exit() to the "ret"
variable to propagate the error correctly.

Fixes: 07dbff0ddbd86c ("usb: core: add a wrapper for the USB PHYs on the HCD")
Signed-off-by: Martin Blumenstingl <martin.blumenstingl at googlemail.com>
Signed-off-by: Rishabh Bhatnagar <rishabhb at codeaurora.org>
---
 drivers/usb/core/phy.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/usb/core/phy.c b/drivers/usb/core/phy.c
index 09b7c43c0ea4..f19aaa3c899c 100644
--- a/drivers/usb/core/phy.c
+++ b/drivers/usb/core/phy.c
@@ -111,7 +111,7 @@ int usb_phy_roothub_exit(struct usb_phy_roothub *phy_roothub)
 	list_for_each_entry(roothub_entry, head, list) {
 		err = phy_exit(roothub_entry->phy);
 		if (err)
-			ret = ret;
+			ret = err;
 	}
 
 	return ret;
-- 
2.17.0



From martin.blumenstingl at googlemail.com  Sun Apr  8 14:27:39 2018
From: martin.blumenstingl at googlemail.com (Martin Blumenstingl)
Date: Sun,  8 Apr 2018 23:27:39 +0200
Subject: [PATCH usb v5 2/6] usb: core: split usb_phy_roothub_{init,alloc}
In-Reply-To: <20180408212743.22934-1-martin.blumenstingl@googlemail.com>
References: <20180408212743.22934-1-martin.blumenstingl@googlemail.com>
Message-ID: <20180408212743.22934-3-martin.blumenstingl@googlemail.com>

Before this patch usb_phy_roothub_init served two purposes (from a
caller's point of view - like hcd.c):
- parsing the PHYs and allocating the list entries
- calling phy_init on each list entry

While this worked so far it has one disadvantage: if we need to call
phy_init for each PHY instance then the existing code cannot be re-used.
Solve this by splitting off usb_phy_roothub_alloc which only parses the
PHYs and allocates the list entries.
usb_phy_roothub_init then gets a struct usb_phy_roothub and only calls
phy_init on each PHY instance (along with the corresponding cleanup if
that failed somewhere).

This is a preparation step for adding proper suspend support for some
hardware that requires phy_exit to be called during suspend and phy_init
to be called during resume.

Signed-off-by: Martin Blumenstingl <martin.blumenstingl at googlemail.com>
Tested-by: Chunfeng Yun <chunfeng.yun at mediatek.com>
Reviewed-by: Roger Quadros <rogerq at ti.com>
---
 drivers/usb/core/hcd.c | 10 +++++---
 drivers/usb/core/phy.c | 53 +++++++++++++++++++++---------------------
 drivers/usb/core/phy.h |  4 +++-
 3 files changed, 37 insertions(+), 30 deletions(-)

diff --git a/drivers/usb/core/hcd.c b/drivers/usb/core/hcd.c
index 777036ae6367..15b0418e3b6a 100644
--- a/drivers/usb/core/hcd.c
+++ b/drivers/usb/core/hcd.c
@@ -2758,12 +2758,16 @@ int usb_add_hcd(struct usb_hcd *hcd,
 	}
 
 	if (!hcd->skip_phy_initialization && usb_hcd_is_primary_hcd(hcd)) {
-		hcd->phy_roothub = usb_phy_roothub_init(hcd->self.sysdev);
+		hcd->phy_roothub = usb_phy_roothub_alloc(hcd->self.sysdev);
 		if (IS_ERR(hcd->phy_roothub)) {
 			retval = PTR_ERR(hcd->phy_roothub);
-			goto err_phy_roothub_init;
+			goto err_phy_roothub_alloc;
 		}
 
+		retval = usb_phy_roothub_init(hcd->phy_roothub);
+		if (retval)
+			goto err_phy_roothub_alloc;
+
 		retval = usb_phy_roothub_power_on(hcd->phy_roothub);
 		if (retval)
 			goto err_usb_phy_roothub_power_on;
@@ -2936,7 +2940,7 @@ int usb_add_hcd(struct usb_hcd *hcd,
 	usb_phy_roothub_power_off(hcd->phy_roothub);
 err_usb_phy_roothub_power_on:
 	usb_phy_roothub_exit(hcd->phy_roothub);
-err_phy_roothub_init:
+err_phy_roothub_alloc:
 	if (hcd->remove_phy && hcd->usb_phy) {
 		usb_phy_shutdown(hcd->usb_phy);
 		usb_put_phy(hcd->usb_phy);
diff --git a/drivers/usb/core/phy.c b/drivers/usb/core/phy.c
index f19aaa3c899c..44f008cda7a8 100644
--- a/drivers/usb/core/phy.c
+++ b/drivers/usb/core/phy.c
@@ -19,19 +19,6 @@ struct usb_phy_roothub {
 	struct list_head	list;
 };
 
-static struct usb_phy_roothub *usb_phy_roothub_alloc(struct device *dev)
-{
-	struct usb_phy_roothub *roothub_entry;
-
-	roothub_entry = devm_kzalloc(dev, sizeof(*roothub_entry), GFP_KERNEL);
-	if (!roothub_entry)
-		return ERR_PTR(-ENOMEM);
-
-	INIT_LIST_HEAD(&roothub_entry->list);
-
-	return roothub_entry;
-}
-
 static int usb_phy_roothub_add_phy(struct device *dev, int index,
 				   struct list_head *list)
 {
@@ -45,9 +32,11 @@ static int usb_phy_roothub_add_phy(struct device *dev, int index,
 			return PTR_ERR(phy);
 	}
 
-	roothub_entry = usb_phy_roothub_alloc(dev);
-	if (IS_ERR(roothub_entry))
-		return PTR_ERR(roothub_entry);
+	roothub_entry = devm_kzalloc(dev, sizeof(*roothub_entry), GFP_KERNEL);
+	if (!roothub_entry)
+		return -ENOMEM;
+
+	INIT_LIST_HEAD(&roothub_entry->list);
 
 	roothub_entry->phy = phy;
 
@@ -56,11 +45,9 @@ static int usb_phy_roothub_add_phy(struct device *dev, int index,
 	return 0;
 }
 
-struct usb_phy_roothub *usb_phy_roothub_init(struct device *dev)
+struct usb_phy_roothub *usb_phy_roothub_alloc(struct device *dev)
 {
 	struct usb_phy_roothub *phy_roothub;
-	struct usb_phy_roothub *roothub_entry;
-	struct list_head *head;
 	int i, num_phys, err;
 
 	num_phys = of_count_phandle_with_args(dev->of_node, "phys",
@@ -68,16 +55,31 @@ struct usb_phy_roothub *usb_phy_roothub_init(struct device *dev)
 	if (num_phys <= 0)
 		return NULL;
 
-	phy_roothub = usb_phy_roothub_alloc(dev);
-	if (IS_ERR(phy_roothub))
-		return phy_roothub;
+	phy_roothub = devm_kzalloc(dev, sizeof(*phy_roothub), GFP_KERNEL);
+	if (!phy_roothub)
+		return ERR_PTR(-ENOMEM);
+
+	INIT_LIST_HEAD(&phy_roothub->list);
 
 	for (i = 0; i < num_phys; i++) {
 		err = usb_phy_roothub_add_phy(dev, i, &phy_roothub->list);
 		if (err)
-			goto err_out;
+			return ERR_PTR(err);
 	}
 
+	return phy_roothub;
+}
+EXPORT_SYMBOL_GPL(usb_phy_roothub_alloc);
+
+int usb_phy_roothub_init(struct usb_phy_roothub *phy_roothub)
+{
+	struct usb_phy_roothub *roothub_entry;
+	struct list_head *head;
+	int err;
+
+	if (!phy_roothub)
+		return 0;
+
 	head = &phy_roothub->list;
 
 	list_for_each_entry(roothub_entry, head, list) {
@@ -86,14 +88,13 @@ struct usb_phy_roothub *usb_phy_roothub_init(struct device *dev)
 			goto err_exit_phys;
 	}
 
-	return phy_roothub;
+	return 0;
 
 err_exit_phys:
 	list_for_each_entry_continue_reverse(roothub_entry, head, list)
 		phy_exit(roothub_entry->phy);
 
-err_out:
-	return ERR_PTR(err);
+	return err;
 }
 EXPORT_SYMBOL_GPL(usb_phy_roothub_init);
 
diff --git a/drivers/usb/core/phy.h b/drivers/usb/core/phy.h
index 6fde59bfbff8..eb31253201ad 100644
--- a/drivers/usb/core/phy.h
+++ b/drivers/usb/core/phy.h
@@ -1,6 +1,8 @@
 struct usb_phy_roothub;
 
-struct usb_phy_roothub *usb_phy_roothub_init(struct device *dev);
+struct usb_phy_roothub *usb_phy_roothub_alloc(struct device *dev);
+
+int usb_phy_roothub_init(struct usb_phy_roothub *phy_roothub);
 int usb_phy_roothub_exit(struct usb_phy_roothub *phy_roothub);
 
 int usb_phy_roothub_power_on(struct usb_phy_roothub *phy_roothub);
-- 
2.17.0



From martin.blumenstingl at googlemail.com  Sun Apr  8 14:27:41 2018
From: martin.blumenstingl at googlemail.com (Martin Blumenstingl)
Date: Sun,  8 Apr 2018 23:27:41 +0200
Subject: [PATCH usb v5 4/6] usb: core: phy: make it a no-op if
 CONFIG_GENERIC_PHY is disabled
In-Reply-To: <20180408212743.22934-1-martin.blumenstingl@googlemail.com>
References: <20180408212743.22934-1-martin.blumenstingl@googlemail.com>
Message-ID: <20180408212743.22934-5-martin.blumenstingl@googlemail.com>

If the generic PHY support is disabled the stub of devm_of_phy_get_by_index
returns ENOSYS. This corner case isn't handled properly by
usb_phy_roothub_add_phy and at least breaks USB support on Raspberry Pi
(bcm2835_defconfig):

    dwc2 20980000.usb: dwc2_hcd_init() FAILED, returning -38
    dwc2: probe of 20980000.usb failed with error -38

Let usb_phy_roothub_alloc() return in case CONFIG_GENERIC_PHY is
disabled to fix this issue (compilers might even be smart enough to
optimize away most of the code within usb_phy_roothub_alloc and
usb_phy_roothub_add_phy if CONFIG_GENERIC_PHY is disabled). All
existing usb_phy_roothub_* functions are already NULL-safe, so no
special handling is required there.

Fixes: 07dbff0ddbd8 ("usb: core: add a wrapper for the USB PHYs on the HCD")
Reported-by: Stefan Wahren <stefan.wahren at i2se.com>
Signed-off-by: Martin Blumenstingl <martin.blumenstingl at googlemail.com>
---
 drivers/usb/core/phy.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/usb/core/phy.c b/drivers/usb/core/phy.c
index a39d9bb26a4f..9879767452a2 100644
--- a/drivers/usb/core/phy.c
+++ b/drivers/usb/core/phy.c
@@ -50,6 +50,9 @@ struct usb_phy_roothub *usb_phy_roothub_alloc(struct device *dev)
 	struct usb_phy_roothub *phy_roothub;
 	int i, num_phys, err;
 
+	if (!IS_ENABLED(CONFIG_GENERIC_PHY))
+		return NULL;
+
 	num_phys = of_count_phandle_with_args(dev->of_node, "phys",
 					      "#phy-cells");
 	if (num_phys <= 0)
-- 
2.17.0



From martin.blumenstingl at googlemail.com  Sun Apr  8 14:27:40 2018
From: martin.blumenstingl at googlemail.com (Martin Blumenstingl)
Date: Sun,  8 Apr 2018 23:27:40 +0200
Subject: [PATCH usb v5 3/6] usb: core: use phy_exit during suspend if wake up
 is not supported
In-Reply-To: <20180408212743.22934-1-martin.blumenstingl@googlemail.com>
References: <20180408212743.22934-1-martin.blumenstingl@googlemail.com>
Message-ID: <20180408212743.22934-4-martin.blumenstingl@googlemail.com>

If the USB controller can wake up the system (which is the case for
example with the Mediatek USB3 IP) then we must not call phy_exit during
suspend to ensure that the USB controller doesn't have to re-enumerate
the devices during resume.
However, if the USB controller cannot wake up the system (which is the
case for example on various TI platforms using a dwc3 controller) then
we must call phy_exit during suspend. Otherwise the PHY driver keeps the
clocks enabled, which prevents the system from reaching the lowest power
levels in the suspend state.

Solve this by introducing two new functions in the PHY wrapper which are
dedicated to the suspend and resume handling.
If the controller can wake up the system the new usb_phy_roothub_suspend
function will simply call usb_phy_roothub_power_off. However, if wake up
is not supported by the controller it will also call
usb_phy_roothub_exit.
The also new usb_phy_roothub_resume function takes care of calling
usb_phy_roothub_init (if the controller can't wake up the system) in
addition to usb_phy_roothub_power_on.

Fixes: 07dbff0ddbd86c ("usb: core: add a wrapper for the USB PHYs on the HCD")
Fixes: 178a0bce05cbc1 ("usb: core: hcd: integrate the PHY wrapper into the HCD core")
Reported-by: Roger Quadros <rogerq at ti.com>
Suggested-by: Roger Quadros <rogerq at ti.com>
Suggested-by: Chunfeng Yun <chunfeng.yun at mediatek.com>
Signed-off-by: Martin Blumenstingl <martin.blumenstingl at googlemail.com>
Tested-by: Chunfeng Yun <chunfeng.yun at mediatek.com>
Reviewed-by: Roger Quadros <rogerq at ti.com>
---
 drivers/usb/core/hcd.c |  8 +++++---
 drivers/usb/core/phy.c | 35 +++++++++++++++++++++++++++++++++++
 drivers/usb/core/phy.h |  5 +++++
 3 files changed, 45 insertions(+), 3 deletions(-)

diff --git a/drivers/usb/core/hcd.c b/drivers/usb/core/hcd.c
index 15b0418e3b6a..78bae4ecd68b 100644
--- a/drivers/usb/core/hcd.c
+++ b/drivers/usb/core/hcd.c
@@ -2262,7 +2262,8 @@ int hcd_bus_suspend(struct usb_device *rhdev, pm_message_t msg)
 		hcd->state = HC_STATE_SUSPENDED;
 
 		if (!PMSG_IS_AUTO(msg))
-			usb_phy_roothub_power_off(hcd->phy_roothub);
+			usb_phy_roothub_suspend(hcd->self.sysdev,
+						hcd->phy_roothub);
 
 		/* Did we race with a root-hub wakeup event? */
 		if (rhdev->do_remote_wakeup) {
@@ -2302,7 +2303,8 @@ int hcd_bus_resume(struct usb_device *rhdev, pm_message_t msg)
 	}
 
 	if (!PMSG_IS_AUTO(msg)) {
-		status = usb_phy_roothub_power_on(hcd->phy_roothub);
+		status = usb_phy_roothub_resume(hcd->self.sysdev,
+						hcd->phy_roothub);
 		if (status)
 			return status;
 	}
@@ -2344,7 +2346,7 @@ int hcd_bus_resume(struct usb_device *rhdev, pm_message_t msg)
 		}
 	} else {
 		hcd->state = old_state;
-		usb_phy_roothub_power_off(hcd->phy_roothub);
+		usb_phy_roothub_suspend(hcd->self.sysdev, hcd->phy_roothub);
 		dev_dbg(&rhdev->dev, "bus %s fail, err %d\n",
 				"resume", status);
 		if (status != -ESHUTDOWN)
diff --git a/drivers/usb/core/phy.c b/drivers/usb/core/phy.c
index 44f008cda7a8..a39d9bb26a4f 100644
--- a/drivers/usb/core/phy.c
+++ b/drivers/usb/core/phy.c
@@ -157,3 +157,38 @@ void usb_phy_roothub_power_off(struct usb_phy_roothub *phy_roothub)
 		phy_power_off(roothub_entry->phy);
 }
 EXPORT_SYMBOL_GPL(usb_phy_roothub_power_off);
+
+int usb_phy_roothub_suspend(struct device *controller_dev,
+			    struct usb_phy_roothub *phy_roothub)
+{
+	usb_phy_roothub_power_off(phy_roothub);
+
+	/* keep the PHYs initialized so the device can wake up the system */
+	if (device_may_wakeup(controller_dev))
+		return 0;
+
+	return usb_phy_roothub_exit(phy_roothub);
+}
+EXPORT_SYMBOL_GPL(usb_phy_roothub_suspend);
+
+int usb_phy_roothub_resume(struct device *controller_dev,
+			   struct usb_phy_roothub *phy_roothub)
+{
+	int err;
+
+	/* if the device can't wake up the system _exit was called */
+	if (!device_may_wakeup(controller_dev)) {
+		err = usb_phy_roothub_init(phy_roothub);
+		if (err)
+			return err;
+	}
+
+	err = usb_phy_roothub_power_on(phy_roothub);
+
+	/* undo _init if _power_on failed */
+	if (err && !device_may_wakeup(controller_dev))
+		usb_phy_roothub_exit(phy_roothub);
+
+	return err;
+}
+EXPORT_SYMBOL_GPL(usb_phy_roothub_resume);
diff --git a/drivers/usb/core/phy.h b/drivers/usb/core/phy.h
index eb31253201ad..605555901d44 100644
--- a/drivers/usb/core/phy.h
+++ b/drivers/usb/core/phy.h
@@ -7,3 +7,8 @@ int usb_phy_roothub_exit(struct usb_phy_roothub *phy_roothub);
 
 int usb_phy_roothub_power_on(struct usb_phy_roothub *phy_roothub);
 void usb_phy_roothub_power_off(struct usb_phy_roothub *phy_roothub);
+
+int usb_phy_roothub_suspend(struct device *controller_dev,
+			    struct usb_phy_roothub *phy_roothub);
+int usb_phy_roothub_resume(struct device *controller_dev,
+			   struct usb_phy_roothub *phy_roothub);
-- 
2.17.0



From martin.blumenstingl at googlemail.com  Sun Apr  8 14:27:43 2018
From: martin.blumenstingl at googlemail.com (Martin Blumenstingl)
Date: Sun,  8 Apr 2018 23:27:43 +0200
Subject: [PATCH usb v5 6/6] usb: core: phy: add the SPDX-License-Identifier
 and include guard
In-Reply-To: <20180408212743.22934-1-martin.blumenstingl@googlemail.com>
References: <20180408212743.22934-1-martin.blumenstingl@googlemail.com>
Message-ID: <20180408212743.22934-7-martin.blumenstingl@googlemail.com>

This clarifies the license of the code. While here also add an include
guard to the header file.

Fixes: 07dbff0ddbd86c ("usb: core: add a wrapper for the USB PHYs on the HCD")
Suggested-by: Masahiro Yamada <yamada.masahiro at socionext.com>
Signed-off-by: Martin Blumenstingl <martin.blumenstingl at googlemail.com>
---
 drivers/usb/core/phy.h | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/drivers/usb/core/phy.h b/drivers/usb/core/phy.h
index bbc969383074..8451a7e88d38 100644
--- a/drivers/usb/core/phy.h
+++ b/drivers/usb/core/phy.h
@@ -1,3 +1,13 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * USB roothub wrapper
+ *
+ * Copyright (C) 2018 Martin Blumenstingl <martin.blumenstingl at googlemail.com>
+ */
+
+#ifndef __USB_CORE_PHY_H_
+#define __USB_CORE_PHY_H_
+
 struct device;
 struct usb_phy_roothub;
 
@@ -13,3 +23,5 @@ int usb_phy_roothub_suspend(struct device *controller_dev,
 			    struct usb_phy_roothub *phy_roothub);
 int usb_phy_roothub_resume(struct device *controller_dev,
 			   struct usb_phy_roothub *phy_roothub);
+
+#endif /* __USB_CORE_PHY_H_ */
-- 
2.17.0



From jbrunet at baylibre.com  Mon Apr  9 05:03:45 2018
From: jbrunet at baylibre.com (Jerome Brunet)
Date: Mon, 09 Apr 2018 14:03:45 +0200
Subject: [PATCH v4 2/7] clk: meson: migrate to
 devm_of_clk_add_hw_provider API
In-Reply-To: <20180408031938.153474-3-yixun.lan@amlogic.com>
References: <20180408031938.153474-1-yixun.lan@amlogic.com>
 <20180408031938.153474-3-yixun.lan@amlogic.com>
Message-ID: <1523275425.2764.20.camel@baylibre.com>

On Sun, 2018-04-08 at 11:19 +0800, Yixun Lan wrote:
> There is a protential memory leak, as of_clk_del_provider is
> never called if of_clk_add_hw_provider has been executed.
> Fix this by using devm variant API.
> 
> Suggested-by: Stephen Boyd <sboyd at kernel.org>
> Signed-off-by: Yixun Lan <yixun.lan at amlogic.com>

Please make this the 1st patch of the series and add the proper fixes tag.

> ---
>  drivers/clk/meson/meson-aoclk.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/clk/meson/meson-aoclk.c b/drivers/clk/meson/meson-aoclk.c
> index 14862c22e20d..14a1e46a4de6 100644
> --- a/drivers/clk/meson/meson-aoclk.c
> +++ b/drivers/clk/meson/meson-aoclk.c
> @@ -78,6 +78,6 @@ int meson_aoclkc_probe(struct platform_device *pdev)
>  			return ret;
>  	}
>  
> -	return of_clk_add_hw_provider(dev->of_node, of_clk_hw_onecell_get,
> +	return devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get,
>  		(void *) data->hw_data);
>  }



From jbrunet at baylibre.com  Mon Apr  9 05:08:49 2018
From: jbrunet at baylibre.com (Jerome Brunet)
Date: Mon, 09 Apr 2018 14:08:49 +0200
Subject: [PATCH v4 1/7] clk: meson: aoclk: refactor common code into
 dedicated file
In-Reply-To: <20180408031938.153474-2-yixun.lan@amlogic.com>
References: <20180408031938.153474-1-yixun.lan@amlogic.com>
 <20180408031938.153474-2-yixun.lan@amlogic.com>
Message-ID: <1523275729.2764.25.camel@baylibre.com>

On Sun, 2018-04-08 at 11:19 +0800, Yixun Lan wrote:
> We try to refactor the common code into one dedicated file,
> while preparing to add new Meson-AXG aoclk driver, this would
> help us to better share the code by all aoclk drivers.
> 
> Suggested-by: Jerome Brunet <jbrunet at baylibre.com>
> Signed-off-by: Yixun Lan <yixun.lan at amlogic.com>
> ---
>  drivers/clk/meson/Makefile      |  2 +-
>  drivers/clk/meson/gxbb-aoclk.c  | 91 ++++++++++++++---------------------------
>  drivers/clk/meson/gxbb-aoclk.h  |  7 ++++
>  drivers/clk/meson/meson-aoclk.c | 83 +++++++++++++++++++++++++++++++++++++
>  drivers/clk/meson/meson-aoclk.h | 35 ++++++++++++++++
>  5 files changed, 157 insertions(+), 61 deletions(-)
>  create mode 100644 drivers/clk/meson/meson-aoclk.c
>  create mode 100644 drivers/clk/meson/meson-aoclk.h
> 
> diff --git a/drivers/clk/meson/Makefile b/drivers/clk/meson/Makefile
> index ffee82e60b7a..555ab9c6ab64 100644
> --- a/drivers/clk/meson/Makefile
> +++ b/drivers/clk/meson/Makefile
> @@ -4,6 +4,6 @@
>  
>  obj-$(CONFIG_COMMON_CLK_AMLOGIC) += clk-pll.o clk-mpll.o clk-audio-divider.o
>  obj-$(CONFIG_COMMON_CLK_MESON8B) += meson8b.o
> -obj-$(CONFIG_COMMON_CLK_GXBB)	 += gxbb.o gxbb-aoclk.o gxbb-aoclk-32k.o
> +obj-$(CONFIG_COMMON_CLK_GXBB)	 += gxbb.o meson-aoclk.o gxbb-aoclk.o gxbb-aoclk-32k.o
                                                      ^
This is not going to end well ========================|


>  obj-$(CONFIG_COMMON_CLK_AXG)	 += axg.o
>  obj-$(CONFIG_COMMON_CLK_REGMAP_MESON)	+= clk-regmap.o
> diff --git a/drivers/clk/meson/gxbb-aoclk.c b/drivers/clk/meson/gxbb-aoclk.c
> index 9ec23ae9a219..59db8e92f8cf 100644
> --- a/drivers/clk/meson/gxbb-aoclk.c
> +++ b/drivers/clk/meson/gxbb-aoclk.c
> @@ -52,39 +52,13 @@
>   * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
>   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
>   */
> -#include <linux/clk-provider.h>
> -#include <linux/of_address.h>
>  #include <linux/platform_device.h>
>  #include <linux/reset-controller.h>
>  #include <linux/mfd/syscon.h>
> -#include <linux/regmap.h>
>  #include <linux/init.h>
> -#include <linux/delay.h>
> -#include <dt-bindings/clock/gxbb-aoclkc.h>
> -#include <dt-bindings/reset/gxbb-aoclkc.h>
>  #include "clk-regmap.h"
>  #include "gxbb-aoclk.h"
>  
> -struct gxbb_aoclk_reset_controller {
> -	struct reset_controller_dev reset;
> -	unsigned int *data;
> -	struct regmap *regmap;
> -};
> -
> -static int gxbb_aoclk_do_reset(struct reset_controller_dev *rcdev,
> -			       unsigned long id)
> -{
> -	struct gxbb_aoclk_reset_controller *reset =
> -		container_of(rcdev, struct gxbb_aoclk_reset_controller, reset);
> -
> -	return regmap_write(reset->regmap, AO_RTI_GEN_CNTL_REG0,
> -			    BIT(reset->data[id]));
> -}
> -
> -static const struct reset_control_ops gxbb_aoclk_reset_ops = {
> -	.reset = gxbb_aoclk_do_reset,
> -};
> -
>  #define GXBB_AO_GATE(_name, _bit)					\
>  static struct clk_regmap _name##_ao = {					\
>  	.data = &(struct clk_regmap_gate_data) {			\
> @@ -117,7 +91,7 @@ static struct aoclk_cec_32k cec_32k_ao = {
>  	},
>  };
>  
> -static unsigned int gxbb_aoclk_reset[] = {
> +static const unsigned int gxbb_aoclk_reset[] = {
>  	[RESET_AO_REMOTE] = 16,
>  	[RESET_AO_I2C_MASTER] = 18,
>  	[RESET_AO_I2C_SLAVE] = 19,
> @@ -135,7 +109,7 @@ static struct clk_regmap *gxbb_aoclk_gate[] = {
>  	[CLKID_AO_IR_BLASTER] = &ir_blaster_ao,
>  };
>  
> -static struct clk_hw_onecell_data gxbb_aoclk_onecell_data = {
> +static const struct clk_hw_onecell_data gxbb_aoclk_onecell_data = {
>  	.hws = {
>  		[CLKID_AO_REMOTE] = &remote_ao.hw,
>  		[CLKID_AO_I2C_MASTER] = &i2c_master_ao.hw,
> @@ -145,19 +119,15 @@ static struct clk_hw_onecell_data gxbb_aoclk_onecell_data = {
>  		[CLKID_AO_IR_BLASTER] = &ir_blaster_ao.hw,
>  		[CLKID_AO_CEC_32K] = &cec_32k_ao.hw,
>  	},
> -	.num = 7,
> +	.num = NR_CLKS,
>  };
>  
> -static int gxbb_aoclkc_probe(struct platform_device *pdev)
> +static int gxbb_aoclkc_register_specific_clk(

Please call this something more explicit, gxbb_register_cec_ao_32k for example

> +		struct platform_device *pdev)

Why do you put this on a new line ? it was not over 80 char ...

>  {
> -	struct gxbb_aoclk_reset_controller *rstc;
>  	struct device *dev = &pdev->dev;
>  	struct regmap *regmap;
> -	int ret, clkid;
> -
> -	rstc = devm_kzalloc(dev, sizeof(*rstc), GFP_KERNEL);
> -	if (!rstc)
> -		return -ENOMEM;
> +	int ret;
>  
>  	regmap = syscon_node_to_regmap(of_get_parent(dev->of_node));
>  	if (IS_ERR(regmap)) {
> @@ -165,38 +135,39 @@ static int gxbb_aoclkc_probe(struct platform_device *pdev)
>  		return -ENODEV;
>  	}
>  
> -	/* Reset Controller */
> -	rstc->regmap = regmap;
> -	rstc->data = gxbb_aoclk_reset;
> -	rstc->reset.ops = &gxbb_aoclk_reset_ops;
> -	rstc->reset.nr_resets = ARRAY_SIZE(gxbb_aoclk_reset);
> -	rstc->reset.of_node = dev->of_node;
> -	ret = devm_reset_controller_register(dev, &rstc->reset);
> -
> -	/*
> -	 * Populate regmap and register all clks
> -	 */
> -	for (clkid = 0; clkid < ARRAY_SIZE(gxbb_aoclk_gate); clkid++) {
> -		gxbb_aoclk_gate[clkid]->map = regmap;
> -
> -		ret = devm_clk_hw_register(dev,
> -					   gxbb_aoclk_onecell_data.hws[clkid]);
> -		if (ret)
> -			return ret;
> -	}
> -
>  	/* Specific clocks */
>  	cec_32k_ao.regmap = regmap;
>  	ret = devm_clk_hw_register(dev, &cec_32k_ao.hw);
> -	if (ret)
> +	if (ret) {
> +		dev_err(&pdev->dev, "clk cec_32k_ao register failed.\n");
>  		return ret;
> +	}
> +
> +	return 0;
> +}
> +
> +static const struct meson_aoclk_data gxbb_aoclkc_data = {
> +	.reset_reg	= AO_RTI_GEN_CNTL_REG0,
> +	.num_reset	= ARRAY_SIZE(gxbb_aoclk_reset),
> +	.reset		= gxbb_aoclk_reset,
> +	.num_clks	= ARRAY_SIZE(gxbb_aoclk_gate),
> +	.clks		= gxbb_aoclk_gate,
> +	.hw_data	= &gxbb_aoclk_onecell_data,
> +};
> +
> +static int gxbb_aoclkc_probe(struct platform_device *pdev)
> +{
> +	if (gxbb_aoclkc_register_specific_clk(pdev))
> +		return -ENODEV;

It is not OK to just put your error code like that. If a function, such as
devm_clk_hw_register() return an error, you should fwd that error code.

>  
> -	return of_clk_add_hw_provider(dev->of_node, of_clk_hw_onecell_get,
> -			&gxbb_aoclk_onecell_data);
> +	return meson_aoclkc_probe(pdev);
>  }
>  
>  static const struct of_device_id gxbb_aoclkc_match_table[] = {
> -	{ .compatible = "amlogic,meson-gx-aoclkc" },
> +	{
> +		.compatible	= "amlogic,meson-gx-aoclkc",
> +		.data		= &gxbb_aoclkc_data,
> +	},
>  	{ }
>  };
>  
> diff --git a/drivers/clk/meson/gxbb-aoclk.h b/drivers/clk/meson/gxbb-aoclk.h
> index badc4c22b4ee..b031f1a0213e 100644
> --- a/drivers/clk/meson/gxbb-aoclk.h
> +++ b/drivers/clk/meson/gxbb-aoclk.h
> @@ -8,6 +8,10 @@
>  #ifndef __GXBB_AOCLKC_H
>  #define __GXBB_AOCLKC_H
>  
> +#include "meson-aoclk.h"
> +
> +#define NR_CLKS	7
> +
>  /* AO Configuration Clock registers offsets */
>  #define AO_RTI_PWR_CNTL_REG1	0x0c
>  #define AO_RTI_PWR_CNTL_REG0	0x10
> @@ -26,4 +30,7 @@ struct aoclk_cec_32k {
>  
>  extern const struct clk_ops meson_aoclk_cec_32k_ops;
>  
> +#include <dt-bindings/clock/gxbb-aoclkc.h>
> +#include <dt-bindings/reset/gxbb-aoclkc.h>
> +
>  #endif /* __GXBB_AOCLKC_H */
> diff --git a/drivers/clk/meson/meson-aoclk.c b/drivers/clk/meson/meson-aoclk.c
> new file mode 100644
> index 000000000000..14862c22e20d
> --- /dev/null
> +++ b/drivers/clk/meson/meson-aoclk.c
> @@ -0,0 +1,83 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Amlogic Meson-AXG Clock Controller Driver
> + *
> + * Copyright (c) 2016 BayLibre, SAS.
> + * Author: Neil Armstrong <narmstrong at baylibre.com>
> + *
> + * Copyright (c) 2018 Amlogic, inc.
> + * Author: Qiufang Dai <qiufang.dai at amlogic.com>
> + * Author: Yixun Lan <yixun.lan at amlogic.com>
> + */
> +
> +#include <linux/platform_device.h>
> +#include <linux/reset-controller.h>
> +#include <linux/mfd/syscon.h>
> +#include <linux/init.h>
> +#include <linux/of_device.h>
> +#include "clk-regmap.h"
> +#include "meson-aoclk.h"
> +
> +static int meson_aoclk_do_reset(struct reset_controller_dev *rcdev,
> +			       unsigned long id)
> +{
> +	struct meson_aoclk_reset_controller *rstc =
> +		container_of(rcdev, struct meson_aoclk_reset_controller, reset);
> +
> +	return regmap_write(rstc->regmap, rstc->data->reset_reg,
> +			    BIT(rstc->data->reset[id]));
> +}
> +
> +static const struct reset_control_ops meson_aoclk_reset_ops = {
> +	.reset = meson_aoclk_do_reset,
> +};
> +
> +int meson_aoclkc_probe(struct platform_device *pdev)
> +{
> +	struct meson_aoclk_reset_controller *rstc;
> +	struct meson_aoclk_data *data;
> +	struct device *dev = &pdev->dev;
> +	struct regmap *regmap;
> +	int ret, clkid;
> +
> +	data = (struct meson_aoclk_data *)
> +		of_device_get_match_data(dev);

Again, line would not be over 80 char ...

> +	if (!data)
> +		return -ENODEV;
> +
> +	rstc = devm_kzalloc(dev, sizeof(*rstc), GFP_KERNEL);
> +	if (!rstc)
> +		return -ENOMEM;
> +
> +	regmap = syscon_node_to_regmap(of_get_parent(dev->of_node));
> +	if (IS_ERR(regmap)) {
> +		dev_err(dev, "failed to get regmap\n");
> +		return -ENODEV;

Same as above, you can't decide to return error code like this ... use PTR_ERR.

> +	}
> +
> +	/* Reset Controller */
> +	rstc->data = data;
> +	rstc->regmap = regmap;
> +	rstc->reset.ops = &meson_aoclk_reset_ops;
> +	rstc->reset.nr_resets = data->num_reset,
> +	rstc->reset.of_node = dev->of_node;
> +	ret = devm_reset_controller_register(dev, &rstc->reset);
> +	if (ret) {
> +		dev_err(dev, "failed to register reset controller\n");
> +		return ret;
> +	}
> +
> +	/*
> +	 * Populate regmap and register all clks
> +	 */
> +	for (clkid = 0; clkid < data->num_clks; clkid++) {
> +		data->clks[clkid]->map = regmap;
> +
> +		ret = devm_clk_hw_register(dev, data->hw_data->hws[clkid]);
> +		if (ret)
> +			return ret;
> +	}
> +
> +	return of_clk_add_hw_provider(dev->of_node, of_clk_hw_onecell_get,
> +		(void *) data->hw_data);
> +}
> diff --git a/drivers/clk/meson/meson-aoclk.h b/drivers/clk/meson/meson-aoclk.h
> new file mode 100644
> index 000000000000..f0fba19fff0a
> --- /dev/null
> +++ b/drivers/clk/meson/meson-aoclk.h
> @@ -0,0 +1,35 @@
> +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
> +/*
> + * Copyright (c) 2017 BayLibre, SAS
> + * Author: Neil Armstrong <narmstrong at baylibre.com>
> + *
> + * Copyright (c) 2018 Amlogic, inc.
> + * Author: Qiufang Dai <qiufang.dai at amlogic.com>
> + * Author: Yixun Lan <yixun.lan at amlogic.com>
> + */
> +
> +#ifndef __MESON_AOCLK_H__
> +#define __MESON_AOCLK_H__
> +
> +#include <linux/platform_device.h>
> +#include <linux/reset-controller.h>
> +#include "clk-regmap.h"
> +
> +struct meson_aoclk_data {
> +	const unsigned int		reset_reg;
> +	const int			num_reset;
> +	const unsigned int		*reset;
> +	int				num_clks;
> +	struct clk_regmap		**clks;
> +	const struct clk_hw_onecell_data	*hw_data;

If you align structure member names, please do it for all them.

> +};
> +
> +struct meson_aoclk_reset_controller {
> +	struct reset_controller_dev	reset;
> +	const struct meson_aoclk_data	*data;
> +	struct regmap			*regmap;
> +};
> +
> +int meson_aoclkc_probe(struct platform_device *pdev);
> +#endif
> +



From jbrunet at baylibre.com  Mon Apr  9 05:08:55 2018
From: jbrunet at baylibre.com (Jerome Brunet)
Date: Mon, 09 Apr 2018 14:08:55 +0200
Subject: [PATCH v4 5/7] clk: meson-axg: Add AO Clock and Reset
 controller driver
In-Reply-To: <20180408031938.153474-6-yixun.lan@amlogic.com>
References: <20180408031938.153474-1-yixun.lan@amlogic.com>
 <20180408031938.153474-6-yixun.lan@amlogic.com>
Message-ID: <1523275735.2764.26.camel@baylibre.com>

On Sun, 2018-04-08 at 11:19 +0800, Yixun Lan wrote:
> From: Qiufang Dai <qiufang.dai at amlogic.com>
> 
> Adds a Clock and Reset controller driver for the Always-On part
> of the Amlogic Meson-AXG SoC.
> 
> Signed-off-by: Qiufang Dai <qiufang.dai at amlogic.com>
> Signed-off-by: Yixun Lan <yixun.lan at amlogic.com>
> ---
>  drivers/clk/meson/Makefile    |   2 +-
>  drivers/clk/meson/axg-aoclk.c | 164 ++++++++++++++++++++++++++++++++++++++++++
>  drivers/clk/meson/axg-aoclk.h |  31 ++++++++
>  3 files changed, 196 insertions(+), 1 deletion(-)
>  create mode 100644 drivers/clk/meson/axg-aoclk.c
>  create mode 100644 drivers/clk/meson/axg-aoclk.h
> 
> diff --git a/drivers/clk/meson/Makefile b/drivers/clk/meson/Makefile
> index 555ab9c6ab64..fa6d1e36cef6 100644
> --- a/drivers/clk/meson/Makefile
> +++ b/drivers/clk/meson/Makefile
> @@ -5,5 +5,5 @@
>  obj-$(CONFIG_COMMON_CLK_AMLOGIC) += clk-pll.o clk-mpll.o clk-audio-divider.o
>  obj-$(CONFIG_COMMON_CLK_MESON8B) += meson8b.o
>  obj-$(CONFIG_COMMON_CLK_GXBB)	 += gxbb.o meson-aoclk.o gxbb-aoclk.o gxbb-aoclk-32k.o
> -obj-$(CONFIG_COMMON_CLK_AXG)	 += axg.o
> +obj-$(CONFIG_COMMON_CLK_AXG)	 += axg.o meson-aoclk.o axg-aoclk.o
                                             ^
As hinted in patch 1, not ending well =======|

You are putting this object in 2 modules.
What you should have done is :
- Add a Kconfig CONFIG_COMMON_CLK_MESON_AO (same as CONFIG_COMMON_CLK_AMLOGIC)
selected by GXBB and AXG.
- Compile meson-aoclk.o according to this new configuration

>  obj-$(CONFIG_COMMON_CLK_REGMAP_MESON)	+= clk-regmap.o
> diff --git a/drivers/clk/meson/axg-aoclk.c b/drivers/clk/meson/axg-aoclk.c
> new file mode 100644
> index 000000000000..cb56d809d3df
> --- /dev/null
> +++ b/drivers/clk/meson/axg-aoclk.c
> @@ -0,0 +1,164 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Amlogic Meson-AXG Clock Controller Driver
> + *
> + * Copyright (c) 2016 Baylibre SAS.
> + * Author: Michael Turquette <mturquette at baylibre.com>
> + *
> + * Copyright (c) 2018 Amlogic, inc.
> + * Author: Qiufang Dai <qiufang.dai at amlogic.com>
> + */
> +#include <linux/clk-provider.h>
> +#include <linux/platform_device.h>
> +#include <linux/reset-controller.h>
> +#include <linux/mfd/syscon.h>
> +#include <linux/init.h>
> +#include "clkc.h"
> +#include "axg-aoclk.h"
> +
> +#define AXG_AO_GATE(_name, _bit)					\
> +static struct clk_regmap _name##_ao = {					\
> +	.data = &(struct clk_regmap_gate_data) {			\
> +		.offset = (AO_RTI_GEN_CNTL_REG0),			\
> +		.bit_idx = (_bit),					\
> +	},								\
> +	.hw.init = &(struct clk_init_data) {				\
> +		.name = #_name "_ao",					\
> +		.ops = &clk_regmap_gate_ops,				\
> +		.parent_names = (const char *[]){ "clk81" },		\
> +		.num_parents = 1,					\
> +		.flags = CLK_IGNORE_UNUSED,				\
> +	},								\
> +}
> +
> +AXG_AO_GATE(remote, 0);
> +AXG_AO_GATE(i2c_master, 1);
> +AXG_AO_GATE(i2c_slave, 2);
> +AXG_AO_GATE(uart1, 3);
> +AXG_AO_GATE(uart2, 5);
> +AXG_AO_GATE(ir_blaster, 6);
> +AXG_AO_GATE(saradc, 7);
> +
> +static struct clk_regmap ao_clk81 = {
> +	.data = &(struct clk_regmap_mux_data) {
> +		.offset = AO_RTI_PWR_CNTL_REG0,
> +		.mask = 0x1,
> +		.shift = 8,
> +	},
> +	.hw.init = &(struct clk_init_data){
> +		.name = "ao_clk81",
> +		.ops = &clk_regmap_mux_ro_ops,
> +		.parent_names = (const char *[]){ "clk81", "ao_alt_xtal"},
> +		.num_parents = 2,
> +	},
> +};
> +
> +static struct clk_regmap axg_saradc_mux = {
> +	.data = &(struct clk_regmap_mux_data) {
> +		.offset = AO_SAR_CLK,
> +		.mask = 0x3,
> +		.shift = 9,
> +	},
> +	.hw.init = &(struct clk_init_data){
> +		.name = "axg_saradc_mux",
> +		.ops = &clk_regmap_mux_ops,
> +		.parent_names = (const char *[]){ "xtal", "ao_clk81" },
> +		.num_parents = 2,
> +	},
> +};
> +
> +static struct clk_regmap axg_saradc_div = {
> +	.data = &(struct clk_regmap_div_data) {
> +		.offset = AO_SAR_CLK,
> +		.shift = 0,
> +		.width = 8,
> +	},
> +	.hw.init = &(struct clk_init_data){
> +		.name = "axg_saradc_div",
> +		.ops = &clk_regmap_divider_ops,
> +		.parent_names = (const char *[]){ "axg_saradc_mux" },
> +		.num_parents = 1,
> +		.flags = CLK_SET_RATE_PARENT,
> +	},
> +};
> +
> +static struct clk_regmap axg_saradc_gate = {
> +	.data = &(struct clk_regmap_gate_data) {
> +		.offset = AO_SAR_CLK,
> +		.bit_idx = 8,
> +	},
> +	.hw.init = &(struct clk_init_data){
> +		.name = "axg_saradc_gate",
> +		.ops = &clk_regmap_gate_ops,
> +		.parent_names = (const char *[]){ "axg_saradc_div" },
> +		.num_parents = 1,
> +		.flags = CLK_SET_RATE_PARENT,
> +	},
> +};
> +
> +static const unsigned int axg_aoclk_reset[] = {
> +	[RESET_AO_REMOTE] = 16,
> +	[RESET_AO_I2C_MASTER] = 18,
> +	[RESET_AO_I2C_SLAVE] = 19,
> +	[RESET_AO_UART1] = 17,
> +	[RESET_AO_UART2] = 22,
> +	[RESET_AO_IR_BLASTER] = 23,
> +};
> +
> +static struct clk_regmap *axg_aoclk_regmap[] = {
> +	[CLKID_AO_REMOTE]	= &remote_ao,
> +	[CLKID_AO_I2C_MASTER]	= &i2c_master_ao,
> +	[CLKID_AO_I2C_SLAVE]	= &i2c_slave_ao,
> +	[CLKID_AO_UART1]	= &uart1_ao,
> +	[CLKID_AO_UART2]	= &uart2_ao,
> +	[CLKID_AO_IR_BLASTER]	= &ir_blaster_ao,
> +	[CLKID_AO_SAR_ADC]	= &saradc_ao,
> +	[CLKID_AO_CLK81]	= &ao_clk81,
> +	[CLKID_AO_SAR_ADC_SEL]	= &axg_saradc_mux,
> +	[CLKID_AO_SAR_ADC_DIV]	= &axg_saradc_div,
> +	[CLKID_AO_SAR_ADC_CLK]	= &axg_saradc_gate,
> +};
> +
> +static const struct clk_hw_onecell_data axg_aoclk_onecell_data = {
> +	.hws = {
> +		[CLKID_AO_REMOTE]	= &remote_ao.hw,
> +		[CLKID_AO_I2C_MASTER]	= &i2c_master_ao.hw,
> +		[CLKID_AO_I2C_SLAVE]	= &i2c_slave_ao.hw,
> +		[CLKID_AO_UART1]	= &uart1_ao.hw,
> +		[CLKID_AO_UART2]	= &uart2_ao.hw,
> +		[CLKID_AO_IR_BLASTER]	= &ir_blaster_ao.hw,
> +		[CLKID_AO_SAR_ADC]	= &saradc_ao.hw,
> +		[CLKID_AO_CLK81]	= &ao_clk81.hw,
> +		[CLKID_AO_SAR_ADC_SEL]	= &axg_saradc_mux.hw,
> +		[CLKID_AO_SAR_ADC_DIV]	= &axg_saradc_div.hw,
> +		[CLKID_AO_SAR_ADC_CLK]	= &axg_saradc_gate.hw,
> +	},
> +	.num = NR_CLKS,
> +};
> +
> +static const struct meson_aoclk_data axg_aoclkc_data = {
> +	.reset_reg	= AO_RTI_GEN_CNTL_REG0,
> +	.num_reset	= ARRAY_SIZE(axg_aoclk_reset),
> +	.reset		= axg_aoclk_reset,
> +	.num_clks	= ARRAY_SIZE(axg_aoclk_regmap),
> +	.clks		= axg_aoclk_regmap,
> +	.hw_data	= &axg_aoclk_onecell_data,
> +};
> +
> +static const struct of_device_id axg_aoclkc_match_table[] = {
> +	{
> +		.compatible	= "amlogic,meson-axg-aoclkc",
> +		.data		= &axg_aoclkc_data,
> +	},
> +	{ }
> +};
> +
> +static struct platform_driver axg_aoclkc_driver = {
> +	.probe		= meson_aoclkc_probe,
> +	.driver		= {
> +		.name	= "axg-aoclkc",
> +		.of_match_table = axg_aoclkc_match_table,
> +	},
> +};
> +
> +builtin_platform_driver(axg_aoclkc_driver);
> diff --git a/drivers/clk/meson/axg-aoclk.h b/drivers/clk/meson/axg-aoclk.h
> new file mode 100644
> index 000000000000..396cd3023064
> --- /dev/null
> +++ b/drivers/clk/meson/axg-aoclk.h
> @@ -0,0 +1,31 @@
> +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
> +/*
> + * Copyright (c) 2017 BayLibre, SAS
> + * Author: Neil Armstrong <narmstrong at baylibre.com>
> + *
> + * Copyright (c) 2018 Amlogic, inc.
> + * Author: Qiufang Dai <qiufang.dai at amlogic.com>
> + */
> +
> +#ifndef __AXG_AOCLKC_H
> +#define __AXG_AOCLKC_H
> +
> +#include "meson-aoclk.h"
> +
> +#define NR_CLKS	11
> +/* AO Configuration Clock registers offsets
> + * Register offsets from the data sheet must be multiplied by 4.
> + */
> +#define AO_RTI_PWR_CNTL_REG1	0x0C
> +#define AO_RTI_PWR_CNTL_REG0	0x10
> +#define AO_RTI_GEN_CNTL_REG0	0x40
> +#define AO_OSCIN_CNTL		0x58
> +#define AO_CRT_CLK_CNTL1	0x68
> +#define AO_SAR_CLK		0x90
> +#define AO_RTC_ALT_CLK_CNTL0	0x94
> +#define AO_RTC_ALT_CLK_CNTL1	0x98
> +
> +#include <dt-bindings/clock/axg-aoclkc.h>
> +#include <dt-bindings/reset/axg-aoclkc.h>
> +
> +#endif /* __AXG_AOCLKC_H */



From narmstrong at baylibre.com  Mon Apr  9 06:47:46 2018
From: narmstrong at baylibre.com (Neil Armstrong)
Date: Mon, 9 Apr 2018 15:47:46 +0200
Subject: [PATCH u-boot 2/2] ARM: meson: Add cpu info display for GX SoCs
In-Reply-To: <20180404204953.GA12368@gmail.com>
References: <1522230877-21267-1-git-send-email-narmstrong@baylibre.com>
 <1522230877-21267-3-git-send-email-narmstrong@baylibre.com>
 <20180404204953.GA12368@gmail.com>
Message-ID: <492995cc-3679-54a5-cc47-4eed68f11da5@baylibre.com>

On 04/04/2018 22:49, Beniamino Galvani wrote:
> On Wed, Mar 28, 2018 at 11:54:37AM +0200, Neil Armstrong wrote:
>> The Amlogic SoCs have a registers containing the die revision
>> and packaging type to determine the SoC family and package marketing
>> name like S905X for the GXL SoC Family.
>> This code is taken for the Linux meson-gx-socinfo driver and adapted
>> to U-Boot printing.
>>
>> Signed-off-by: Neil Armstrong <narmstrong at baylibre.com>
>> ---
>>  arch/arm/include/asm/arch-meson/gx.h |   1 +
>>  arch/arm/mach-meson/Makefile         |   2 +-
>>  arch/arm/mach-meson/cpu_info.c       | 105 +++++++++++++++++++++++++++++++++++
>>  configs/khadas-vim_defconfig         |   2 +-
>>  configs/libretech-cc_defconfig       |   2 +-
>>  configs/odroid-c2_defconfig          |   2 +-
>>  configs/odroid_defconfig             |   1 +
>>  configs/p212_defconfig               |   2 +-
>>  8 files changed, 112 insertions(+), 5 deletions(-)
>>  create mode 100644 arch/arm/mach-meson/cpu_info.c
>>
>> diff --git a/arch/arm/include/asm/arch-meson/gx.h b/arch/arm/include/asm/arch-meson/gx.h
>> index 7930efd..6d5b4ea 100644
>> --- a/arch/arm/include/asm/arch-meson/gx.h
>> +++ b/arch/arm/include/asm/arch-meson/gx.h
>> @@ -17,6 +17,7 @@
>>  /* Always-On Peripherals registers */
>>  #define GX_AO_ADDR(off)	(GX_AOBUS_BASE + ((off) << 2))
>>  
>> +#define GX_AO_SEC_SD_CFG8	GX_AO_ADDR(0x88)
>>  #define GX_AO_SEC_GP_CFG0	GX_AO_ADDR(0x90)
>>  #define GX_AO_SEC_GP_CFG3	GX_AO_ADDR(0x93)
>>  #define GX_AO_SEC_GP_CFG4	GX_AO_ADDR(0x94)
>> diff --git a/arch/arm/mach-meson/Makefile b/arch/arm/mach-meson/Makefile
>> index b4e8dde..5a01ff0 100644
>> --- a/arch/arm/mach-meson/Makefile
>> +++ b/arch/arm/mach-meson/Makefile
>> @@ -4,4 +4,4 @@
>>  # SPDX-License-Identifier:	GPL-2.0+
>>  #
>>  
>> -obj-y += board.o sm.o eth.o
>> +obj-y += board.o sm.o eth.o cpu_info.o
>> diff --git a/arch/arm/mach-meson/cpu_info.c b/arch/arm/mach-meson/cpu_info.c
>> new file mode 100644
>> index 0000000..657768f
>> --- /dev/null
>> +++ b/arch/arm/mach-meson/cpu_info.c
>> @@ -0,0 +1,105 @@
>> +/*
>> + * Copyright (C) 2018 BayLibre, SAS
>> + * Author: Neil Armstrong <narmstrong at baylibre.com>
>> + *
>> + * SPDX-License-Identifier:	GPL-2.0+
>> + */
>> +
>> +#include <common.h>
>> +#include <asm/io.h>
>> +#include <linux/bitfield.h>
>> +#include <asm/arch/gx.h>
>> +
>> +#ifdef CONFIG_DISPLAY_CPUINFO
>> +
>> +#define SOCINFO_MAJOR	GENMASK(31, 24)
>> +#define SOCINFO_PACK	GENMASK(23, 16)
>> +#define SOCINFO_MINOR	GENMASK(15, 8)
>> +#define SOCINFO_MISC	GENMASK(7, 0)
>> +
>> +static const struct meson_gx_soc_id {
>> +	const char *name;
>> +	unsigned int id;
>> +} soc_ids[] = {
>> +	{ "GXBB", 0x1f },
>> +	{ "GXTVBB", 0x20 },
>> +	{ "GXL", 0x21 },
>> +	{ "GXM", 0x22 },
>> +	{ "TXL", 0x23 },
>> +};
>> +
>> +static const struct meson_gx_package_id {
>> +	const char *name;
>> +	unsigned int major_id;
>> +	unsigned int pack_id;
>> +} soc_packages[] = {
>> +	{ "S905", 0x1f, 0 },
>> +	{ "S905M", 0x1f, 0x20 },
>> +	{ "S905D", 0x21, 0 },
>> +	{ "S905X", 0x21, 0x80 },
>> +	{ "S905L", 0x21, 0xc0 },
>> +	{ "S905M2", 0x21, 0xe0 },
>> +	{ "S912", 0x22, 0 },
>> +};
>> +
>> +static inline unsigned int socinfo_to_major(u32 socinfo)
>> +{
>> +	return FIELD_GET(SOCINFO_MAJOR, socinfo);
>> +}
>> +
>> +static inline unsigned int socinfo_to_minor(u32 socinfo)
>> +{
>> +	return FIELD_GET(SOCINFO_MINOR, socinfo);
>> +}
>> +
>> +static inline unsigned int socinfo_to_pack(u32 socinfo)
>> +{
>> +	return FIELD_GET(SOCINFO_PACK, socinfo);
>> +}
>> +
>> +static inline unsigned int socinfo_to_misc(u32 socinfo)
>> +{
>> +	return FIELD_GET(SOCINFO_MISC, socinfo);
>> +}
>> +
>> +static const char *socinfo_to_package_id(u32 socinfo)
>> +{
>> +	unsigned int pack = socinfo_to_pack(socinfo) & 0xf0;
>> +	unsigned int major = socinfo_to_major(socinfo);
>> +	int i;
>> +
>> +	for (i = 0 ; i < ARRAY_SIZE(soc_packages) ; ++i) {
>> +		if (soc_packages[i].major_id == major &&
>> +		    soc_packages[i].pack_id == pack)
>> +			return soc_packages[i].name;
>> +	}
>> +
>> +	return "Unknown";
>> +}
>> +
>> +static const char *socinfo_to_soc_id(u32 socinfo)
>> +{
>> +	unsigned int id = socinfo_to_major(socinfo);
>> +	int i;
>> +
>> +	for (i = 0 ; i < ARRAY_SIZE(soc_ids) ; ++i) {
>> +		if (soc_ids[i].id == id)
>> +			return soc_ids[i].name;
>> +	}
>> +
>> +	return "Unknown";
>> +}
>> +
>> +int print_cpuinfo(void)
>> +{
>> +	u32 socinfo = readl(GX_AO_SEC_SD_CFG8);
> 
> Perhaps, add a blank line between declarations and code? checkpatch
> issues a warning about this.

Ok

> 
>> +	printf("CPU: Amlogic Meson %s (%s) rev %x:%x (%x:%x)\n",
>> +		socinfo_to_soc_id(socinfo),
>> +		socinfo_to_package_id(socinfo),
>> +		socinfo_to_major(socinfo),
>> +		socinfo_to_minor(socinfo),
>> +		socinfo_to_pack(socinfo),
>> +		socinfo_to_misc(socinfo));
>> +	return 0;
>> +}
>> +#endif /* CONFIG_DISPLAY_CPUINFO */
>> diff --git a/configs/khadas-vim_defconfig b/configs/khadas-vim_defconfig
>> index a0b3f8d..970d373 100644
>> --- a/configs/khadas-vim_defconfig
>> +++ b/configs/khadas-vim_defconfig
>> @@ -7,7 +7,7 @@ CONFIG_IDENT_STRING=" khadas-vim"
>>  CONFIG_DEFAULT_DEVICE_TREE="meson-gxl-s905x-khadas-vim"
>>  CONFIG_DEBUG_UART=y
>>  CONFIG_OF_BOARD_SETUP=y
>> -# CONFIG_DISPLAY_CPUINFO is not set
>> +CONFIG_DISPLAY_CPUINFO=y
>>  # CONFIG_DISPLAY_BOARDINFO is not set
>>  # CONFIG_CMD_BDI is not set
>>  # CONFIG_CMD_IMI is not set
>> diff --git a/configs/libretech-cc_defconfig b/configs/libretech-cc_defconfig
>> index a7177b9..cfbba30 100644
>> --- a/configs/libretech-cc_defconfig
>> +++ b/configs/libretech-cc_defconfig
>> @@ -7,7 +7,7 @@ CONFIG_IDENT_STRING=" libretech-cc"
>>  CONFIG_DEFAULT_DEVICE_TREE="meson-gxl-s905x-libretech-cc"
>>  CONFIG_DEBUG_UART=y
>>  CONFIG_OF_BOARD_SETUP=y
>> -# CONFIG_DISPLAY_CPUINFO is not set
>> +CONFIG_DISPLAY_CPUINFO=y
>>  # CONFIG_DISPLAY_BOARDINFO is not set
>>  # CONFIG_CMD_BDI is not set
>>  # CONFIG_CMD_IMI is not set
>> diff --git a/configs/odroid-c2_defconfig b/configs/odroid-c2_defconfig
>> index 49461aa..657b647 100644
>> --- a/configs/odroid-c2_defconfig
>> +++ b/configs/odroid-c2_defconfig
>> @@ -7,7 +7,7 @@ CONFIG_IDENT_STRING=" odroid-c2"
>>  CONFIG_DEFAULT_DEVICE_TREE="meson-gxbb-odroidc2"
>>  CONFIG_DEBUG_UART=y
>>  CONFIG_OF_BOARD_SETUP=y
>> -# CONFIG_DISPLAY_CPUINFO is not set
>> +CONFIG_DISPLAY_CPUINFO=y
>>  # CONFIG_DISPLAY_BOARDINFO is not set
>>  # CONFIG_CMD_BDI is not set
>>  # CONFIG_CMD_IMI is not set
>> diff --git a/configs/odroid_defconfig b/configs/odroid_defconfig
>> index 810874d..251bf38 100644
>> --- a/configs/odroid_defconfig
>> +++ b/configs/odroid_defconfig
>> @@ -56,3 +56,4 @@ CONFIG_USB_HOST_ETHER=y
>>  CONFIG_USB_ETHER_SMSC95XX=y
>>  CONFIG_LIB_HW_RAND=y
>>  CONFIG_ERRNO_STR=y
>> +CONFIG_DISPLAY_CPUINFO=y
> 
> Odroid is not an Amlogic board.

Oops, will remove it.

> 
> With these 2 issues fixed: Reviewed-by: Beniamino Galvani <b.galvani at gmail.com>
> 
> Beniamino
> 



From narmstrong at baylibre.com  Mon Apr  9 06:48:17 2018
From: narmstrong at baylibre.com (Neil Armstrong)
Date: Mon, 9 Apr 2018 15:48:17 +0200
Subject: [PATCH u-boot 2/2] ARM: meson: Add cpu info display for GX SoCs
In-Reply-To: <CAPnjgZ0w9v6_6Qiw0uzKzFcTOMThtcQ6C6Q0gnKfHnX9ZZihUQ@mail.gmail.com>
References: <1522230877-21267-1-git-send-email-narmstrong@baylibre.com>
 <1522230877-21267-3-git-send-email-narmstrong@baylibre.com>
 <CAPnjgZ0w9v6_6Qiw0uzKzFcTOMThtcQ6C6Q0gnKfHnX9ZZihUQ@mail.gmail.com>
Message-ID: <04c1ed50-fce8-077e-46e7-4d34ddff2da4@baylibre.com>

On 08/04/2018 15:50, Simon Glass wrote:
> Hi,
> 
> On 28 March 2018 at 05:54, Neil Armstrong <narmstrong at baylibre.com> wrote:
>> The Amlogic SoCs have a registers containing the die revision
>> and packaging type to determine the SoC family and package marketing
>> name like S905X for the GXL SoC Family.
>> This code is taken for the Linux meson-gx-socinfo driver and adapted
>> to U-Boot printing.
>>
>> Signed-off-by: Neil Armstrong <narmstrong at baylibre.com>
>> ---
>>  arch/arm/include/asm/arch-meson/gx.h |   1 +
>>  arch/arm/mach-meson/Makefile         |   2 +-
>>  arch/arm/mach-meson/cpu_info.c       | 105 +++++++++++++++++++++++++++++++++++
>>  configs/khadas-vim_defconfig         |   2 +-
>>  configs/libretech-cc_defconfig       |   2 +-
>>  configs/odroid-c2_defconfig          |   2 +-
>>  configs/odroid_defconfig             |   1 +
>>  configs/p212_defconfig               |   2 +-
>>  8 files changed, 112 insertions(+), 5 deletions(-)
>>  create mode 100644 arch/arm/mach-meson/cpu_info.c
> 
> Please can you use driver model's CPU interface for this?
> 
> Regards,
> Simon
> 

You are right, I totally missed this one.

Neil


From narmstrong at baylibre.com  Mon Apr  9 06:48:42 2018
From: narmstrong at baylibre.com (Neil Armstrong)
Date: Mon, 9 Apr 2018 15:48:42 +0200
Subject: [PATCH u-boot 1/2] ARM: meson: rename GXBB to GX
In-Reply-To: <20180404204024.GA12177@gmail.com>
References: <1522230877-21267-1-git-send-email-narmstrong@baylibre.com>
 <1522230877-21267-2-git-send-email-narmstrong@baylibre.com>
 <20180404204024.GA12177@gmail.com>
Message-ID: <05455689-9f45-0e67-c582-2ac34c217a82@baylibre.com>

On 04/04/2018 22:40, Beniamino Galvani wrote:
> On Wed, Mar 28, 2018 at 11:54:36AM +0200, Neil Armstrong wrote:
>> Taking into account the Amlogic Family name starts with GX, including
>> the GXBB, GXL and GXM SoCs.
>>
>> Signed-off-by: Neil Armstrong <narmstrong at baylibre.com>
> 
> Hi,
> 
> looks good to me, but perhaps can you align again register values and
> other macros in gx.h?
> 
> Beniamino
> 

Will do,

Neil


From jbrunet at baylibre.com  Mon Apr  9 06:59:20 2018
From: jbrunet at baylibre.com (Jerome Brunet)
Date: Mon,  9 Apr 2018 15:59:20 +0200
Subject: [PATCH 1/2] clk: honor CLK_MUX_ROUND_CLOSEST in generic clk mux
In-Reply-To: <20180409135921.5617-1-jbrunet@baylibre.com>
References: <20180409135921.5617-1-jbrunet@baylibre.com>
Message-ID: <20180409135921.5617-2-jbrunet@baylibre.com>

CLK_MUX_ROUND_CLOSEST is part of the clk_mux documentation but clk_mux
directly calls __clk_mux_determine_rate(), which overrides the flag.
As result, if clk_mux is instantiated with CLK_MUX_ROUND_CLOSEST, the
flag will be ignored and the clock rounded down.

To solve this, this patch expose clk_mux_determine_rate_flags() in the
clk-provider API and uses it in the determine_rate() callback of clk_mux.

Fixes: 15a02c1f6dd7 ("clk: Add __clk_mux_determine_rate_closest")
Signed-off-by: Jerome Brunet <jbrunet at baylibre.com>
---
 drivers/clk/clk-mux.c        | 10 +++++++++-
 drivers/clk/clk.c            |  7 ++++---
 include/linux/clk-provider.h |  3 +++
 3 files changed, 16 insertions(+), 4 deletions(-)

diff --git a/drivers/clk/clk-mux.c b/drivers/clk/clk-mux.c
index ac4a042f8658..1628b93655ed 100644
--- a/drivers/clk/clk-mux.c
+++ b/drivers/clk/clk-mux.c
@@ -112,10 +112,18 @@ static int clk_mux_set_parent(struct clk_hw *hw, u8 index)
 	return 0;
 }
 
+static int clk_mux_determine_rate(struct clk_hw *hw,
+				  struct clk_rate_request *req)
+{
+	struct clk_mux *mux = to_clk_mux(hw);
+
+	return clk_mux_determine_rate_flags(hw, req, mux->flags);
+}
+
 const struct clk_ops clk_mux_ops = {
 	.get_parent = clk_mux_get_parent,
 	.set_parent = clk_mux_set_parent,
-	.determine_rate = __clk_mux_determine_rate,
+	.determine_rate = clk_mux_determine_rate,
 };
 EXPORT_SYMBOL_GPL(clk_mux_ops);
 
diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c
index ea67ac81c6f9..7af555f0e60c 100644
--- a/drivers/clk/clk.c
+++ b/drivers/clk/clk.c
@@ -426,9 +426,9 @@ static bool mux_is_better_rate(unsigned long rate, unsigned long now,
 	return now <= rate && now > best;
 }
 
-static int
-clk_mux_determine_rate_flags(struct clk_hw *hw, struct clk_rate_request *req,
-			     unsigned long flags)
+int clk_mux_determine_rate_flags(struct clk_hw *hw,
+				 struct clk_rate_request *req,
+				 unsigned long flags)
 {
 	struct clk_core *core = hw->core, *parent, *best_parent = NULL;
 	int i, num_parents, ret;
@@ -488,6 +488,7 @@ clk_mux_determine_rate_flags(struct clk_hw *hw, struct clk_rate_request *req,
 
 	return 0;
 }
+EXPORT_SYMBOL_GPL(clk_mux_determine_rate_flags);
 
 struct clk *__clk_lookup(const char *name)
 {
diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h
index 210a890008f9..1d25e149c1c5 100644
--- a/include/linux/clk-provider.h
+++ b/include/linux/clk-provider.h
@@ -765,6 +765,9 @@ int __clk_mux_determine_rate(struct clk_hw *hw,
 int __clk_determine_rate(struct clk_hw *core, struct clk_rate_request *req);
 int __clk_mux_determine_rate_closest(struct clk_hw *hw,
 				     struct clk_rate_request *req);
+int clk_mux_determine_rate_flags(struct clk_hw *hw,
+				 struct clk_rate_request *req,
+				 unsigned long flags);
 void clk_hw_reparent(struct clk_hw *hw, struct clk_hw *new_parent);
 void clk_hw_set_rate_range(struct clk_hw *hw, unsigned long min_rate,
 			   unsigned long max_rate);
-- 
2.14.3



From jbrunet at baylibre.com  Mon Apr  9 06:59:19 2018
From: jbrunet at baylibre.com (Jerome Brunet)
Date: Mon,  9 Apr 2018 15:59:19 +0200
Subject: [PATCH 0/2] clk: honor CLK_MUX_ROUND_CLOSEST in mux
Message-ID: <20180409135921.5617-1-jbrunet@baylibre.com>

CLK_MUX_ROUND_CLOSEST is part of clk_mux and meson's clk_regmap
documentation, so it should be honored by the determine_rate() callback.

It is note the case ATM. The series fixes this problem.

Jerome Brunet (2):
  clk: honor CLK_MUX_ROUND_CLOSEST in generic clk mux
  clk: meson: honor CLK_MUX_ROUND_CLOSEST in clk_regmap

 drivers/clk/clk-mux.c          | 10 +++++++++-
 drivers/clk/clk.c              |  7 ++++---
 drivers/clk/meson/clk-regmap.c | 11 ++++++++++-
 include/linux/clk-provider.h   |  3 +++
 4 files changed, 26 insertions(+), 5 deletions(-)

-- 
2.14.3



From jbrunet at baylibre.com  Mon Apr  9 06:59:21 2018
From: jbrunet at baylibre.com (Jerome Brunet)
Date: Mon,  9 Apr 2018 15:59:21 +0200
Subject: [PATCH 2/2] clk: meson: honor CLK_MUX_ROUND_CLOSEST in clk_regmap
In-Reply-To: <20180409135921.5617-1-jbrunet@baylibre.com>
References: <20180409135921.5617-1-jbrunet@baylibre.com>
Message-ID: <20180409135921.5617-3-jbrunet@baylibre.com>

Using __clk_mux_determine_rate effectively ignores CLK_MUX_ROUND_CLOSEST
if set the related clk_regmap mux instance.

Use clk_mux_determine_rate_flags() to make sure the flag is honored.

Fixes: ea11dda9e091 ("clk: meson: add regmap clocks")
Signed-off-by: Jerome Brunet <jbrunet at baylibre.com>
---
 drivers/clk/meson/clk-regmap.c | 11 ++++++++++-
 1 file changed, 10 insertions(+), 1 deletion(-)

diff --git a/drivers/clk/meson/clk-regmap.c b/drivers/clk/meson/clk-regmap.c
index 3645fdb62343..ab7a3556f5b2 100644
--- a/drivers/clk/meson/clk-regmap.c
+++ b/drivers/clk/meson/clk-regmap.c
@@ -153,10 +153,19 @@ static int clk_regmap_mux_set_parent(struct clk_hw *hw, u8 index)
 				  val << mux->shift);
 }
 
+static int clk_regmap_mux_determine_rate(struct clk_hw *hw,
+					 struct clk_rate_request *req)
+{
+	struct clk_regmap *clk = to_clk_regmap(hw);
+	struct clk_regmap_mux_data *mux = clk_get_regmap_mux_data(clk);
+
+	return clk_mux_determine_rate_flags(hw, req, mux->flags);
+}
+
 const struct clk_ops clk_regmap_mux_ops = {
 	.get_parent = clk_regmap_mux_get_parent,
 	.set_parent = clk_regmap_mux_set_parent,
-	.determine_rate = __clk_mux_determine_rate,
+	.determine_rate = clk_regmap_mux_determine_rate,
 };
 EXPORT_SYMBOL_GPL(clk_regmap_mux_ops);
 
-- 
2.14.3



From yixun.lan at amlogic.com  Mon Apr  9 07:29:39 2018
From: yixun.lan at amlogic.com (Yixun Lan)
Date: Mon, 9 Apr 2018 22:29:39 +0800
Subject: [PATCH v4 1/7] clk: meson: aoclk: refactor common code into
 dedicated file
In-Reply-To: <1523275729.2764.25.camel@baylibre.com>
References: <20180408031938.153474-1-yixun.lan@amlogic.com>
 <20180408031938.153474-2-yixun.lan@amlogic.com>
 <1523275729.2764.25.camel@baylibre.com>
Message-ID: <12349f2f-39c8-517c-42d0-758d41e97a25@amlogic.com>

Hi Jerome

thanks for the review, I will fix them in next version

On 04/09/2018 08:08 PM, Jerome Brunet wrote:
> On Sun, 2018-04-08 at 11:19 +0800, Yixun Lan wrote:
>> We try to refactor the common code into one dedicated file,
>> while preparing to add new Meson-AXG aoclk driver, this would
>> help us to better share the code by all aoclk drivers.
>>
>> Suggested-by: Jerome Brunet <jbrunet at baylibre.com>
>> Signed-off-by: Yixun Lan <yixun.lan at amlogic.com>
>> ---
>>  drivers/clk/meson/Makefile      |  2 +-
>>  drivers/clk/meson/gxbb-aoclk.c  | 91 ++++++++++++++---------------------------
>>  drivers/clk/meson/gxbb-aoclk.h  |  7 ++++
>>  drivers/clk/meson/meson-aoclk.c | 83 +++++++++++++++++++++++++++++++++++++
>>  drivers/clk/meson/meson-aoclk.h | 35 ++++++++++++++++
>>  5 files changed, 157 insertions(+), 61 deletions(-)
>>  create mode 100644 drivers/clk/meson/meson-aoclk.c
>>  create mode 100644 drivers/clk/meson/meson-aoclk.h
>>
>> diff --git a/drivers/clk/meson/Makefile b/drivers/clk/meson/Makefile
>> index ffee82e60b7a..555ab9c6ab64 100644
>> --- a/drivers/clk/meson/Makefile
>> +++ b/drivers/clk/meson/Makefile
>> @@ -4,6 +4,6 @@
>>  
>>  obj-$(CONFIG_COMMON_CLK_AMLOGIC) += clk-pll.o clk-mpll.o clk-audio-divider.o
>>  obj-$(CONFIG_COMMON_CLK_MESON8B) += meson8b.o
>> -obj-$(CONFIG_COMMON_CLK_GXBB)	 += gxbb.o gxbb-aoclk.o gxbb-aoclk-32k.o
>> +obj-$(CONFIG_COMMON_CLK_GXBB)	 += gxbb.o meson-aoclk.o gxbb-aoclk.o gxbb-aoclk-32k.o
>                                                       ^
> This is not going to end well ========================|
> 
will address this
> 
>>  obj-$(CONFIG_COMMON_CLK_AXG)	 += axg.o
>>  obj-$(CONFIG_COMMON_CLK_REGMAP_MESON)	+= clk-regmap.o
>> diff --git a/drivers/clk/meson/gxbb-aoclk.c b/drivers/clk/meson/gxbb-aoclk.c
>> index 9ec23ae9a219..59db8e92f8cf 100644
>> --- a/drivers/clk/meson/gxbb-aoclk.c
>> +++ b/drivers/clk/meson/gxbb-aoclk.c
>> @@ -52,39 +52,13 @@
>>   * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
>>   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
>>   */
>> -#include <linux/clk-provider.h>
>> -#include <linux/of_address.h>
>>  #include <linux/platform_device.h>
>>  #include <linux/reset-controller.h>
>>  #include <linux/mfd/syscon.h>
>> -#include <linux/regmap.h>
>>  #include <linux/init.h>
>> -#include <linux/delay.h>
>> -#include <dt-bindings/clock/gxbb-aoclkc.h>
>> -#include <dt-bindings/reset/gxbb-aoclkc.h>
>>  #include "clk-regmap.h"
>>  #include "gxbb-aoclk.h"
>>  
>> -struct gxbb_aoclk_reset_controller {
>> -	struct reset_controller_dev reset;
>> -	unsigned int *data;
>> -	struct regmap *regmap;
>> -};
>> -
>> -static int gxbb_aoclk_do_reset(struct reset_controller_dev *rcdev,
>> -			       unsigned long id)
>> -{
>> -	struct gxbb_aoclk_reset_controller *reset =
>> -		container_of(rcdev, struct gxbb_aoclk_reset_controller, reset);
>> -
>> -	return regmap_write(reset->regmap, AO_RTI_GEN_CNTL_REG0,
>> -			    BIT(reset->data[id]));
>> -}
>> -
>> -static const struct reset_control_ops gxbb_aoclk_reset_ops = {
>> -	.reset = gxbb_aoclk_do_reset,
>> -};
>> -
>>  #define GXBB_AO_GATE(_name, _bit)					\
>>  static struct clk_regmap _name##_ao = {					\
>>  	.data = &(struct clk_regmap_gate_data) {			\
>> @@ -117,7 +91,7 @@ static struct aoclk_cec_32k cec_32k_ao = {
>>  	},
>>  };
>>  
>> -static unsigned int gxbb_aoclk_reset[] = {
>> +static const unsigned int gxbb_aoclk_reset[] = {
>>  	[RESET_AO_REMOTE] = 16,
>>  	[RESET_AO_I2C_MASTER] = 18,
>>  	[RESET_AO_I2C_SLAVE] = 19,
>> @@ -135,7 +109,7 @@ static struct clk_regmap *gxbb_aoclk_gate[] = {
>>  	[CLKID_AO_IR_BLASTER] = &ir_blaster_ao,
>>  };
>>  
>> -static struct clk_hw_onecell_data gxbb_aoclk_onecell_data = {
>> +static const struct clk_hw_onecell_data gxbb_aoclk_onecell_data = {
>>  	.hws = {
>>  		[CLKID_AO_REMOTE] = &remote_ao.hw,
>>  		[CLKID_AO_I2C_MASTER] = &i2c_master_ao.hw,
>> @@ -145,19 +119,15 @@ static struct clk_hw_onecell_data gxbb_aoclk_onecell_data = {
>>  		[CLKID_AO_IR_BLASTER] = &ir_blaster_ao.hw,
>>  		[CLKID_AO_CEC_32K] = &cec_32k_ao.hw,
>>  	},
>> -	.num = 7,
>> +	.num = NR_CLKS,
>>  };
>>  
>> -static int gxbb_aoclkc_probe(struct platform_device *pdev)
>> +static int gxbb_aoclkc_register_specific_clk(
> 
> Please call this something more explicit, gxbb_register_cec_ao_32k for example
> 
ok

>> +		struct platform_device *pdev)
> 
> Why do you put this on a new line ? it was not over 80 char ...
> 
>>  {
>> -	struct gxbb_aoclk_reset_controller *rstc;
>>  	struct device *dev = &pdev->dev;
>>  	struct regmap *regmap;
>> -	int ret, clkid;
>> -
>> -	rstc = devm_kzalloc(dev, sizeof(*rstc), GFP_KERNEL);
>> -	if (!rstc)
>> -		return -ENOMEM;
>> +	int ret;
>>  
>>  	regmap = syscon_node_to_regmap(of_get_parent(dev->of_node));
>>  	if (IS_ERR(regmap)) {
>> @@ -165,38 +135,39 @@ static int gxbb_aoclkc_probe(struct platform_device *pdev)
>>  		return -ENODEV;
>>  	}
>>  
>> -	/* Reset Controller */
>> -	rstc->regmap = regmap;
>> -	rstc->data = gxbb_aoclk_reset;
>> -	rstc->reset.ops = &gxbb_aoclk_reset_ops;
>> -	rstc->reset.nr_resets = ARRAY_SIZE(gxbb_aoclk_reset);
>> -	rstc->reset.of_node = dev->of_node;
>> -	ret = devm_reset_controller_register(dev, &rstc->reset);
>> -
>> -	/*
>> -	 * Populate regmap and register all clks
>> -	 */
>> -	for (clkid = 0; clkid < ARRAY_SIZE(gxbb_aoclk_gate); clkid++) {
>> -		gxbb_aoclk_gate[clkid]->map = regmap;
>> -
>> -		ret = devm_clk_hw_register(dev,
>> -					   gxbb_aoclk_onecell_data.hws[clkid]);
>> -		if (ret)
>> -			return ret;
>> -	}
>> -
>>  	/* Specific clocks */
>>  	cec_32k_ao.regmap = regmap;
>>  	ret = devm_clk_hw_register(dev, &cec_32k_ao.hw);
>> -	if (ret)
>> +	if (ret) {
>> +		dev_err(&pdev->dev, "clk cec_32k_ao register failed.\n");
>>  		return ret;
>> +	}
>> +
>> +	return 0;
>> +}
>> +
>> +static const struct meson_aoclk_data gxbb_aoclkc_data = {
>> +	.reset_reg	= AO_RTI_GEN_CNTL_REG0,
>> +	.num_reset	= ARRAY_SIZE(gxbb_aoclk_reset),
>> +	.reset		= gxbb_aoclk_reset,
>> +	.num_clks	= ARRAY_SIZE(gxbb_aoclk_gate),
>> +	.clks		= gxbb_aoclk_gate,
>> +	.hw_data	= &gxbb_aoclk_onecell_data,
>> +};
>> +
>> +static int gxbb_aoclkc_probe(struct platform_device *pdev)
>> +{
>> +	if (gxbb_aoclkc_register_specific_clk(pdev))
>> +		return -ENODEV;
> 
> It is not OK to just put your error code like that. If a function, such as
> devm_clk_hw_register() return an error, you should fwd that error code.
> 
ok, will do

>>  
>> -	return of_clk_add_hw_provider(dev->of_node, of_clk_hw_onecell_get,
>> -			&gxbb_aoclk_onecell_data);
>> +	return meson_aoclkc_probe(pdev);
>>  }
>>  
>>  static const struct of_device_id gxbb_aoclkc_match_table[] = {
>> -	{ .compatible = "amlogic,meson-gx-aoclkc" },
>> +	{
>> +		.compatible	= "amlogic,meson-gx-aoclkc",
>> +		.data		= &gxbb_aoclkc_data,
>> +	},
>>  	{ }
>>  };
>>  
>> diff --git a/drivers/clk/meson/gxbb-aoclk.h b/drivers/clk/meson/gxbb-aoclk.h
>> index badc4c22b4ee..b031f1a0213e 100644
>> --- a/drivers/clk/meson/gxbb-aoclk.h
>> +++ b/drivers/clk/meson/gxbb-aoclk.h
>> @@ -8,6 +8,10 @@
>>  #ifndef __GXBB_AOCLKC_H
>>  #define __GXBB_AOCLKC_H
>>  
>> +#include "meson-aoclk.h"
>> +
>> +#define NR_CLKS	7
>> +
>>  /* AO Configuration Clock registers offsets */
>>  #define AO_RTI_PWR_CNTL_REG1	0x0c
>>  #define AO_RTI_PWR_CNTL_REG0	0x10
>> @@ -26,4 +30,7 @@ struct aoclk_cec_32k {
>>  
>>  extern const struct clk_ops meson_aoclk_cec_32k_ops;
>>  
>> +#include <dt-bindings/clock/gxbb-aoclkc.h>
>> +#include <dt-bindings/reset/gxbb-aoclkc.h>
>> +
>>  #endif /* __GXBB_AOCLKC_H */
>> diff --git a/drivers/clk/meson/meson-aoclk.c b/drivers/clk/meson/meson-aoclk.c
>> new file mode 100644
>> index 000000000000..14862c22e20d
>> --- /dev/null
>> +++ b/drivers/clk/meson/meson-aoclk.c
>> @@ -0,0 +1,83 @@
>> +// SPDX-License-Identifier: GPL-2.0+
>> +/*
>> + * Amlogic Meson-AXG Clock Controller Driver
>> + *
>> + * Copyright (c) 2016 BayLibre, SAS.
>> + * Author: Neil Armstrong <narmstrong at baylibre.com>
>> + *
>> + * Copyright (c) 2018 Amlogic, inc.
>> + * Author: Qiufang Dai <qiufang.dai at amlogic.com>
>> + * Author: Yixun Lan <yixun.lan at amlogic.com>
>> + */
>> +
>> +#include <linux/platform_device.h>
>> +#include <linux/reset-controller.h>
>> +#include <linux/mfd/syscon.h>
>> +#include <linux/init.h>
>> +#include <linux/of_device.h>
>> +#include "clk-regmap.h"
>> +#include "meson-aoclk.h"
>> +
>> +static int meson_aoclk_do_reset(struct reset_controller_dev *rcdev,
>> +			       unsigned long id)
>> +{
>> +	struct meson_aoclk_reset_controller *rstc =
>> +		container_of(rcdev, struct meson_aoclk_reset_controller, reset);
>> +
>> +	return regmap_write(rstc->regmap, rstc->data->reset_reg,
>> +			    BIT(rstc->data->reset[id]));
>> +}
>> +
>> +static const struct reset_control_ops meson_aoclk_reset_ops = {
>> +	.reset = meson_aoclk_do_reset,
>> +};
>> +
>> +int meson_aoclkc_probe(struct platform_device *pdev)
>> +{
>> +	struct meson_aoclk_reset_controller *rstc;
>> +	struct meson_aoclk_data *data;
>> +	struct device *dev = &pdev->dev;
>> +	struct regmap *regmap;
>> +	int ret, clkid;
>> +
>> +	data = (struct meson_aoclk_data *)
>> +		of_device_get_match_data(dev);
> 
> Again, line would not be over 80 char ...
> 
will adjust
>> +	if (!data)
>> +		return -ENODEV;
>> +
>> +	rstc = devm_kzalloc(dev, sizeof(*rstc), GFP_KERNEL);
>> +	if (!rstc)
>> +		return -ENOMEM;
>> +
>> +	regmap = syscon_node_to_regmap(of_get_parent(dev->of_node));
>> +	if (IS_ERR(regmap)) {
>> +		dev_err(dev, "failed to get regmap\n");
>> +		return -ENODEV;
> 
> Same as above, you can't decide to return error code like this ... use PTR_ERR.
> 
ok

>> +	}
>> +
>> +	/* Reset Controller */
>> +	rstc->data = data;
>> +	rstc->regmap = regmap;
>> +	rstc->reset.ops = &meson_aoclk_reset_ops;
>> +	rstc->reset.nr_resets = data->num_reset,
>> +	rstc->reset.of_node = dev->of_node;
>> +	ret = devm_reset_controller_register(dev, &rstc->reset);
>> +	if (ret) {
>> +		dev_err(dev, "failed to register reset controller\n");
>> +		return ret;
>> +	}
>> +
>> +	/*
>> +	 * Populate regmap and register all clks
>> +	 */
>> +	for (clkid = 0; clkid < data->num_clks; clkid++) {
>> +		data->clks[clkid]->map = regmap;
>> +
>> +		ret = devm_clk_hw_register(dev, data->hw_data->hws[clkid]);
>> +		if (ret)
>> +			return ret;
>> +	}
>> +
>> +	return of_clk_add_hw_provider(dev->of_node, of_clk_hw_onecell_get,
>> +		(void *) data->hw_data);
>> +}
>> diff --git a/drivers/clk/meson/meson-aoclk.h b/drivers/clk/meson/meson-aoclk.h
>> new file mode 100644
>> index 000000000000..f0fba19fff0a
>> --- /dev/null
>> +++ b/drivers/clk/meson/meson-aoclk.h
>> @@ -0,0 +1,35 @@
>> +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
>> +/*
>> + * Copyright (c) 2017 BayLibre, SAS
>> + * Author: Neil Armstrong <narmstrong at baylibre.com>
>> + *
>> + * Copyright (c) 2018 Amlogic, inc.
>> + * Author: Qiufang Dai <qiufang.dai at amlogic.com>
>> + * Author: Yixun Lan <yixun.lan at amlogic.com>
>> + */
>> +
>> +#ifndef __MESON_AOCLK_H__
>> +#define __MESON_AOCLK_H__
>> +
>> +#include <linux/platform_device.h>
>> +#include <linux/reset-controller.h>
>> +#include "clk-regmap.h"
>> +
>> +struct meson_aoclk_data {
>> +	const unsigned int		reset_reg;
>> +	const int			num_reset;
>> +	const unsigned int		*reset;
>> +	int				num_clks;
>> +	struct clk_regmap		**clks;
>> +	const struct clk_hw_onecell_data	*hw_data;
> 
> If you align structure member names, please do it for all them.
> 
ok,
>> +};
>> +
>> +struct meson_aoclk_reset_controller {
>> +	struct reset_controller_dev	reset;
>> +	const struct meson_aoclk_data	*data;
>> +	struct regmap			*regmap;
>> +};
>> +
>> +int meson_aoclkc_probe(struct platform_device *pdev);
>> +#endif
>> +
> 
> .
> 



From yixun.lan at amlogic.com  Mon Apr  9 07:37:42 2018
From: yixun.lan at amlogic.com (Yixun Lan)
Date: Mon, 9 Apr 2018 22:37:42 +0800
Subject: [PATCH v5 0/7] clk: meson-axg: Add AO Cloclk and Reset driver
Message-ID: <20180409143749.71197-1-yixun.lan@amlogic.com>

  This patch try to add AO clock and Reset driver for Amlogic's
Meson-AXG SoC.
  Please note that patch 7 need to wait for the DTS changes[3] merged
into mainline first, otherwise it will break the serial console.

 patch 2: factor the common code into a dedicated file
 patch 3-5: add the aoclk driver for AXG SoC
 patch 6-7: drop unnecessary clock flags

changes since v4 at [5]: 
 - fix return err
 - introduce CONFIG_COMMON_CLK_MESON_AO
 - format/style minor fix

changes since v3 at [4]: 
 - add 'const' contraint to the read-only data
 - switch to devm_of_clk_add_hw_provider API
 - check return value of devm_reset_controller_register

changes since v2 at [2]: 
 - rework meson_aoclkc_probe() which leverage the of_match_data
 - merge patch 5-6 into this series
 - seperate DTS patch, will send to Kevin Hilman independently
 
changes since v1 at [0]: 
 - rebase to clk-meson's branch 'next/drivers' [1]
 - fix license, update to BSD-3-Clause
 - drop un-used include header file

[0] https://lkml.kernel.org/r/20180209070026.193879-1-yixun.lan at amlogic.com
[1] git://github.com/BayLibre/clk-meson.git branch: next-drivers
[2] https://lkml.kernel.org/r/20180323143816.200573-1-yixun.lan at amlogic.com
[3] https://lkml.kernel.org/r/20180326081809.49493-4-yixun.lan at amlogic.com
[4] https://lkml.kernel.org/r/20180328025050.221585-1-yixun.lan at amlogic.com
[5] https://lkml.kernel.org/r/20180408031938.153474-1-yixun.lan at amlogic.com

Qiufang Dai (1):
  clk: meson-axg: Add AO Clock and Reset controller driver

Yixun Lan (6):
  clk: meson: migrate to devm_of_clk_add_hw_provider API
  clk: meson: aoclk: refactor common code into dedicated file
  dt-bindings: clock: axg-aoclkc: New binding for Meson-AXG SoC
  dt-bindings: clock: reset: Add AXG AO Clock and Reset Bindings
  clk: meson: drop CLK_SET_RATE_PARENT flag
  clk: meson: drop CLK_IGNORE_UNUSED flag

 .../bindings/clock/amlogic,gxbb-aoclkc.txt         |   1 +
 drivers/clk/meson/Kconfig                          |   8 +
 drivers/clk/meson/Makefile                         |   3 +-
 drivers/clk/meson/axg-aoclk.c                      | 163 +++++++++++++++++++++
 drivers/clk/meson/axg-aoclk.h                      |  31 ++++
 drivers/clk/meson/gxbb-aoclk.c                     |  92 ++++--------
 drivers/clk/meson/gxbb-aoclk.h                     |   7 +
 drivers/clk/meson/meson-aoclk.c                    |  82 +++++++++++
 drivers/clk/meson/meson-aoclk.h                    |  35 +++++
 include/dt-bindings/clock/axg-aoclkc.h             |  26 ++++
 include/dt-bindings/reset/axg-aoclkc.h             |  20 +++
 11 files changed, 406 insertions(+), 62 deletions(-)
 create mode 100644 drivers/clk/meson/axg-aoclk.c
 create mode 100644 drivers/clk/meson/axg-aoclk.h
 create mode 100644 drivers/clk/meson/meson-aoclk.c
 create mode 100644 drivers/clk/meson/meson-aoclk.h
 create mode 100644 include/dt-bindings/clock/axg-aoclkc.h
 create mode 100644 include/dt-bindings/reset/axg-aoclkc.h

-- 
2.15.1



From yixun.lan at amlogic.com  Mon Apr  9 07:37:43 2018
From: yixun.lan at amlogic.com (Yixun Lan)
Date: Mon, 9 Apr 2018 22:37:43 +0800
Subject: [PATCH v5 1/7] clk: meson: migrate to devm_of_clk_add_hw_provider API
In-Reply-To: <20180409143749.71197-1-yixun.lan@amlogic.com>
References: <20180409143749.71197-1-yixun.lan@amlogic.com>
Message-ID: <20180409143749.71197-2-yixun.lan@amlogic.com>

There is a protential memory leak, as of_clk_del_provider is
never called if of_clk_add_hw_provider has been executed.
Fix this by using devm variant API.

Fixes: f8c11f79912d ("clk: meson: Add GXBB AO Clock and Reset controller driver")
Suggested-by: Stephen Boyd <sboyd at kernel.org>
Signed-off-by: Yixun Lan <yixun.lan at amlogic.com>
---
 drivers/clk/meson/gxbb-aoclk.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/clk/meson/gxbb-aoclk.c b/drivers/clk/meson/gxbb-aoclk.c
index 9ec23ae9a219..eebb580b9e0f 100644
--- a/drivers/clk/meson/gxbb-aoclk.c
+++ b/drivers/clk/meson/gxbb-aoclk.c
@@ -191,7 +191,7 @@ static int gxbb_aoclkc_probe(struct platform_device *pdev)
 	if (ret)
 		return ret;
 
-	return of_clk_add_hw_provider(dev->of_node, of_clk_hw_onecell_get,
+	return devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get,
 			&gxbb_aoclk_onecell_data);
 }
 
-- 
2.15.1



From yixun.lan at amlogic.com  Mon Apr  9 07:37:44 2018
From: yixun.lan at amlogic.com (Yixun Lan)
Date: Mon, 9 Apr 2018 22:37:44 +0800
Subject: [PATCH v5 2/7] clk: meson: aoclk: refactor common code into dedicated
 file
In-Reply-To: <20180409143749.71197-1-yixun.lan@amlogic.com>
References: <20180409143749.71197-1-yixun.lan@amlogic.com>
Message-ID: <20180409143749.71197-3-yixun.lan@amlogic.com>

We try to refactor the common code into one dedicated file,
while preparing to add new Meson-AXG aoclk driver, this would
help us to better share the code by all aoclk drivers.

Suggested-by: Jerome Brunet <jbrunet at baylibre.com>
Signed-off-by: Yixun Lan <yixun.lan at amlogic.com>
---
 drivers/clk/meson/Kconfig       |  7 ++++
 drivers/clk/meson/Makefile      |  1 +
 drivers/clk/meson/gxbb-aoclk.c  | 91 ++++++++++++++---------------------------
 drivers/clk/meson/gxbb-aoclk.h  |  7 ++++
 drivers/clk/meson/meson-aoclk.c | 82 +++++++++++++++++++++++++++++++++++++
 drivers/clk/meson/meson-aoclk.h | 35 ++++++++++++++++
 6 files changed, 163 insertions(+), 60 deletions(-)
 create mode 100644 drivers/clk/meson/meson-aoclk.c
 create mode 100644 drivers/clk/meson/meson-aoclk.h

diff --git a/drivers/clk/meson/Kconfig b/drivers/clk/meson/Kconfig
index d5cbec522aec..fddc7ec7b820 100644
--- a/drivers/clk/meson/Kconfig
+++ b/drivers/clk/meson/Kconfig
@@ -3,6 +3,12 @@ config COMMON_CLK_AMLOGIC
 	depends on OF
 	depends on ARCH_MESON || COMPILE_TEST
 
+config COMMON_CLK_MESON_AO
+	bool
+	depends on OF
+	depends on ARCH_MESON || COMPILE_TEST
+	select COMMON_CLK_REGMAP_MESON
+
 config COMMON_CLK_REGMAP_MESON
 	bool
 	select REGMAP
@@ -21,6 +27,7 @@ config COMMON_CLK_GXBB
 	bool
 	depends on COMMON_CLK_AMLOGIC
 	select RESET_CONTROLLER
+	select COMMON_CLK_MESON_AO
 	select COMMON_CLK_REGMAP_MESON
 	select MFD_SYSCON
 	help
diff --git a/drivers/clk/meson/Makefile b/drivers/clk/meson/Makefile
index ffee82e60b7a..0a8df284f4e7 100644
--- a/drivers/clk/meson/Makefile
+++ b/drivers/clk/meson/Makefile
@@ -3,6 +3,7 @@
 #
 
 obj-$(CONFIG_COMMON_CLK_AMLOGIC) += clk-pll.o clk-mpll.o clk-audio-divider.o
+obj-$(CONFIG_COMMON_CLK_MESON_AO) += meson-aoclk.o
 obj-$(CONFIG_COMMON_CLK_MESON8B) += meson8b.o
 obj-$(CONFIG_COMMON_CLK_GXBB)	 += gxbb.o gxbb-aoclk.o gxbb-aoclk-32k.o
 obj-$(CONFIG_COMMON_CLK_AXG)	 += axg.o
diff --git a/drivers/clk/meson/gxbb-aoclk.c b/drivers/clk/meson/gxbb-aoclk.c
index eebb580b9e0f..f2e0640a7f74 100644
--- a/drivers/clk/meson/gxbb-aoclk.c
+++ b/drivers/clk/meson/gxbb-aoclk.c
@@ -52,39 +52,13 @@
  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */
-#include <linux/clk-provider.h>
-#include <linux/of_address.h>
 #include <linux/platform_device.h>
 #include <linux/reset-controller.h>
 #include <linux/mfd/syscon.h>
-#include <linux/regmap.h>
 #include <linux/init.h>
-#include <linux/delay.h>
-#include <dt-bindings/clock/gxbb-aoclkc.h>
-#include <dt-bindings/reset/gxbb-aoclkc.h>
 #include "clk-regmap.h"
 #include "gxbb-aoclk.h"
 
-struct gxbb_aoclk_reset_controller {
-	struct reset_controller_dev reset;
-	unsigned int *data;
-	struct regmap *regmap;
-};
-
-static int gxbb_aoclk_do_reset(struct reset_controller_dev *rcdev,
-			       unsigned long id)
-{
-	struct gxbb_aoclk_reset_controller *reset =
-		container_of(rcdev, struct gxbb_aoclk_reset_controller, reset);
-
-	return regmap_write(reset->regmap, AO_RTI_GEN_CNTL_REG0,
-			    BIT(reset->data[id]));
-}
-
-static const struct reset_control_ops gxbb_aoclk_reset_ops = {
-	.reset = gxbb_aoclk_do_reset,
-};
-
 #define GXBB_AO_GATE(_name, _bit)					\
 static struct clk_regmap _name##_ao = {					\
 	.data = &(struct clk_regmap_gate_data) {			\
@@ -117,7 +91,7 @@ static struct aoclk_cec_32k cec_32k_ao = {
 	},
 };
 
-static unsigned int gxbb_aoclk_reset[] = {
+static const unsigned int gxbb_aoclk_reset[] = {
 	[RESET_AO_REMOTE] = 16,
 	[RESET_AO_I2C_MASTER] = 18,
 	[RESET_AO_I2C_SLAVE] = 19,
@@ -135,7 +109,7 @@ static struct clk_regmap *gxbb_aoclk_gate[] = {
 	[CLKID_AO_IR_BLASTER] = &ir_blaster_ao,
 };
 
-static struct clk_hw_onecell_data gxbb_aoclk_onecell_data = {
+static const struct clk_hw_onecell_data gxbb_aoclk_onecell_data = {
 	.hws = {
 		[CLKID_AO_REMOTE] = &remote_ao.hw,
 		[CLKID_AO_I2C_MASTER] = &i2c_master_ao.hw,
@@ -145,58 +119,55 @@ static struct clk_hw_onecell_data gxbb_aoclk_onecell_data = {
 		[CLKID_AO_IR_BLASTER] = &ir_blaster_ao.hw,
 		[CLKID_AO_CEC_32K] = &cec_32k_ao.hw,
 	},
-	.num = 7,
+	.num = NR_CLKS,
 };
 
-static int gxbb_aoclkc_probe(struct platform_device *pdev)
+static int gxbb_register_cec_ao_32k(struct platform_device *pdev)
 {
-	struct gxbb_aoclk_reset_controller *rstc;
 	struct device *dev = &pdev->dev;
 	struct regmap *regmap;
-	int ret, clkid;
-
-	rstc = devm_kzalloc(dev, sizeof(*rstc), GFP_KERNEL);
-	if (!rstc)
-		return -ENOMEM;
+	int ret;
 
 	regmap = syscon_node_to_regmap(of_get_parent(dev->of_node));
 	if (IS_ERR(regmap)) {
 		dev_err(dev, "failed to get regmap\n");
-		return -ENODEV;
-	}
-
-	/* Reset Controller */
-	rstc->regmap = regmap;
-	rstc->data = gxbb_aoclk_reset;
-	rstc->reset.ops = &gxbb_aoclk_reset_ops;
-	rstc->reset.nr_resets = ARRAY_SIZE(gxbb_aoclk_reset);
-	rstc->reset.of_node = dev->of_node;
-	ret = devm_reset_controller_register(dev, &rstc->reset);
-
-	/*
-	 * Populate regmap and register all clks
-	 */
-	for (clkid = 0; clkid < ARRAY_SIZE(gxbb_aoclk_gate); clkid++) {
-		gxbb_aoclk_gate[clkid]->map = regmap;
-
-		ret = devm_clk_hw_register(dev,
-					   gxbb_aoclk_onecell_data.hws[clkid]);
-		if (ret)
-			return ret;
+		return PTR_ERR(regmap);
 	}
 
 	/* Specific clocks */
 	cec_32k_ao.regmap = regmap;
 	ret = devm_clk_hw_register(dev, &cec_32k_ao.hw);
+	if (ret) {
+		dev_err(&pdev->dev, "clk cec_32k_ao register failed.\n");
+		return ret;
+	}
+
+	return 0;
+}
+
+static const struct meson_aoclk_data gxbb_aoclkc_data = {
+	.reset_reg	= AO_RTI_GEN_CNTL_REG0,
+	.num_reset	= ARRAY_SIZE(gxbb_aoclk_reset),
+	.reset		= gxbb_aoclk_reset,
+	.num_clks	= ARRAY_SIZE(gxbb_aoclk_gate),
+	.clks		= gxbb_aoclk_gate,
+	.hw_data	= &gxbb_aoclk_onecell_data,
+};
+
+static int gxbb_aoclkc_probe(struct platform_device *pdev)
+{
+	int ret = gxbb_register_cec_ao_32k(pdev);
 	if (ret)
 		return ret;
 
-	return devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get,
-			&gxbb_aoclk_onecell_data);
+	return meson_aoclkc_probe(pdev);
 }
 
 static const struct of_device_id gxbb_aoclkc_match_table[] = {
-	{ .compatible = "amlogic,meson-gx-aoclkc" },
+	{
+		.compatible	= "amlogic,meson-gx-aoclkc",
+		.data		= &gxbb_aoclkc_data,
+	},
 	{ }
 };
 
diff --git a/drivers/clk/meson/gxbb-aoclk.h b/drivers/clk/meson/gxbb-aoclk.h
index badc4c22b4ee..b031f1a0213e 100644
--- a/drivers/clk/meson/gxbb-aoclk.h
+++ b/drivers/clk/meson/gxbb-aoclk.h
@@ -8,6 +8,10 @@
 #ifndef __GXBB_AOCLKC_H
 #define __GXBB_AOCLKC_H
 
+#include "meson-aoclk.h"
+
+#define NR_CLKS	7
+
 /* AO Configuration Clock registers offsets */
 #define AO_RTI_PWR_CNTL_REG1	0x0c
 #define AO_RTI_PWR_CNTL_REG0	0x10
@@ -26,4 +30,7 @@ struct aoclk_cec_32k {
 
 extern const struct clk_ops meson_aoclk_cec_32k_ops;
 
+#include <dt-bindings/clock/gxbb-aoclkc.h>
+#include <dt-bindings/reset/gxbb-aoclkc.h>
+
 #endif /* __GXBB_AOCLKC_H */
diff --git a/drivers/clk/meson/meson-aoclk.c b/drivers/clk/meson/meson-aoclk.c
new file mode 100644
index 000000000000..74338ef0a62b
--- /dev/null
+++ b/drivers/clk/meson/meson-aoclk.c
@@ -0,0 +1,82 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Amlogic Meson-AXG Clock Controller Driver
+ *
+ * Copyright (c) 2016 BayLibre, SAS.
+ * Author: Neil Armstrong <narmstrong at baylibre.com>
+ *
+ * Copyright (c) 2018 Amlogic, inc.
+ * Author: Qiufang Dai <qiufang.dai at amlogic.com>
+ * Author: Yixun Lan <yixun.lan at amlogic.com>
+ */
+
+#include <linux/platform_device.h>
+#include <linux/reset-controller.h>
+#include <linux/mfd/syscon.h>
+#include <linux/init.h>
+#include <linux/of_device.h>
+#include "clk-regmap.h"
+#include "meson-aoclk.h"
+
+static int meson_aoclk_do_reset(struct reset_controller_dev *rcdev,
+			       unsigned long id)
+{
+	struct meson_aoclk_reset_controller *rstc =
+		container_of(rcdev, struct meson_aoclk_reset_controller, reset);
+
+	return regmap_write(rstc->regmap, rstc->data->reset_reg,
+			    BIT(rstc->data->reset[id]));
+}
+
+static const struct reset_control_ops meson_aoclk_reset_ops = {
+	.reset = meson_aoclk_do_reset,
+};
+
+int meson_aoclkc_probe(struct platform_device *pdev)
+{
+	struct meson_aoclk_reset_controller *rstc;
+	struct meson_aoclk_data *data;
+	struct device *dev = &pdev->dev;
+	struct regmap *regmap;
+	int ret, clkid;
+
+	data = (struct meson_aoclk_data *) of_device_get_match_data(dev);
+	if (!data)
+		return -ENODEV;
+
+	rstc = devm_kzalloc(dev, sizeof(*rstc), GFP_KERNEL);
+	if (!rstc)
+		return -ENOMEM;
+
+	regmap = syscon_node_to_regmap(of_get_parent(dev->of_node));
+	if (IS_ERR(regmap)) {
+		dev_err(dev, "failed to get regmap\n");
+		return PTR_ERR(regmap);
+	}
+
+	/* Reset Controller */
+	rstc->data = data;
+	rstc->regmap = regmap;
+	rstc->reset.ops = &meson_aoclk_reset_ops;
+	rstc->reset.nr_resets = data->num_reset,
+	rstc->reset.of_node = dev->of_node;
+	ret = devm_reset_controller_register(dev, &rstc->reset);
+	if (ret) {
+		dev_err(dev, "failed to register reset controller\n");
+		return ret;
+	}
+
+	/*
+	 * Populate regmap and register all clks
+	 */
+	for (clkid = 0; clkid < data->num_clks; clkid++) {
+		data->clks[clkid]->map = regmap;
+
+		ret = devm_clk_hw_register(dev, data->hw_data->hws[clkid]);
+		if (ret)
+			return ret;
+	}
+
+	return devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get,
+		(void *) data->hw_data);
+}
diff --git a/drivers/clk/meson/meson-aoclk.h b/drivers/clk/meson/meson-aoclk.h
new file mode 100644
index 000000000000..ec59e027dd37
--- /dev/null
+++ b/drivers/clk/meson/meson-aoclk.h
@@ -0,0 +1,35 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2017 BayLibre, SAS
+ * Author: Neil Armstrong <narmstrong at baylibre.com>
+ *
+ * Copyright (c) 2018 Amlogic, inc.
+ * Author: Qiufang Dai <qiufang.dai at amlogic.com>
+ * Author: Yixun Lan <yixun.lan at amlogic.com>
+ */
+
+#ifndef __MESON_AOCLK_H__
+#define __MESON_AOCLK_H__
+
+#include <linux/platform_device.h>
+#include <linux/reset-controller.h>
+#include "clk-regmap.h"
+
+struct meson_aoclk_data {
+	const unsigned int			reset_reg;
+	const int				num_reset;
+	const unsigned int			*reset;
+	int					num_clks;
+	struct clk_regmap			**clks;
+	const struct clk_hw_onecell_data	*hw_data;
+};
+
+struct meson_aoclk_reset_controller {
+	struct reset_controller_dev		reset;
+	const struct meson_aoclk_data		*data;
+	struct regmap				*regmap;
+};
+
+int meson_aoclkc_probe(struct platform_device *pdev);
+#endif
+
-- 
2.15.1



From yixun.lan at amlogic.com  Mon Apr  9 07:37:45 2018
From: yixun.lan at amlogic.com (Yixun Lan)
Date: Mon, 9 Apr 2018 22:37:45 +0800
Subject: [PATCH v5 3/7] dt-bindings: clock: axg-aoclkc: New binding for
 Meson-AXG SoC
In-Reply-To: <20180409143749.71197-1-yixun.lan@amlogic.com>
References: <20180409143749.71197-1-yixun.lan@amlogic.com>
Message-ID: <20180409143749.71197-4-yixun.lan@amlogic.com>

Update the dt-binding documentation to support new compatible string
for the Amlogic's Meson-AXG SoC.

Reviewed-by: Rob Herring <robh at kernel.org>
Signed-off-by: Yixun Lan <yixun.lan at amlogic.com>
---
 Documentation/devicetree/bindings/clock/amlogic,gxbb-aoclkc.txt | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/clock/amlogic,gxbb-aoclkc.txt b/Documentation/devicetree/bindings/clock/amlogic,gxbb-aoclkc.txt
index 786dc39ca904..3a880528030e 100644
--- a/Documentation/devicetree/bindings/clock/amlogic,gxbb-aoclkc.txt
+++ b/Documentation/devicetree/bindings/clock/amlogic,gxbb-aoclkc.txt
@@ -9,6 +9,7 @@ Required Properties:
 	- GXBB (S905) : "amlogic,meson-gxbb-aoclkc"
 	- GXL (S905X, S905D) : "amlogic,meson-gxl-aoclkc"
 	- GXM (S912) : "amlogic,meson-gxm-aoclkc"
+	- AXG (A113D, A113X) : "amlogic,meson-axg-aoclkc"
 	followed by the common "amlogic,meson-gx-aoclkc"
 
 - #clock-cells: should be 1.
-- 
2.15.1



From yixun.lan at amlogic.com  Mon Apr  9 07:37:46 2018
From: yixun.lan at amlogic.com (Yixun Lan)
Date: Mon, 9 Apr 2018 22:37:46 +0800
Subject: [PATCH v5 4/7] dt-bindings: clock: reset: Add AXG AO Clock and Reset
 Bindings
In-Reply-To: <20180409143749.71197-1-yixun.lan@amlogic.com>
References: <20180409143749.71197-1-yixun.lan@amlogic.com>
Message-ID: <20180409143749.71197-5-yixun.lan@amlogic.com>

Add dt-bindings headers for the Meson-AXG's AO clock and
reset controller.

Reviewed-by: Rob Herring <robh at kernel.org>
Signed-off-by: Yixun Lan <yixun.lan at amlogic.com>
---
 include/dt-bindings/clock/axg-aoclkc.h | 26 ++++++++++++++++++++++++++
 include/dt-bindings/reset/axg-aoclkc.h | 20 ++++++++++++++++++++
 2 files changed, 46 insertions(+)
 create mode 100644 include/dt-bindings/clock/axg-aoclkc.h
 create mode 100644 include/dt-bindings/reset/axg-aoclkc.h

diff --git a/include/dt-bindings/clock/axg-aoclkc.h b/include/dt-bindings/clock/axg-aoclkc.h
new file mode 100644
index 000000000000..61955016a55b
--- /dev/null
+++ b/include/dt-bindings/clock/axg-aoclkc.h
@@ -0,0 +1,26 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */
+/*
+ * Copyright (c) 2016 BayLibre, SAS
+ * Author: Neil Armstrong <narmstrong at baylibre.com>
+ *
+ * Copyright (c) 2018 Amlogic, inc.
+ * Author: Qiufang Dai <qiufang.dai at amlogic.com>
+ */
+
+#ifndef DT_BINDINGS_CLOCK_AMLOGIC_MESON_AXG_AOCLK
+#define DT_BINDINGS_CLOCK_AMLOGIC_MESON_AXG_AOCLK
+
+#define CLKID_AO_REMOTE		0
+#define CLKID_AO_I2C_MASTER	1
+#define CLKID_AO_I2C_SLAVE	2
+#define CLKID_AO_UART1		3
+#define CLKID_AO_UART2		4
+#define CLKID_AO_IR_BLASTER	5
+#define CLKID_AO_SAR_ADC	6
+#define CLKID_AO_CLK81		7
+#define CLKID_AO_SAR_ADC_SEL	8
+#define CLKID_AO_SAR_ADC_DIV	9
+#define CLKID_AO_SAR_ADC_CLK	10
+#define CLKID_AO_ALT_XTAL	11
+
+#endif
diff --git a/include/dt-bindings/reset/axg-aoclkc.h b/include/dt-bindings/reset/axg-aoclkc.h
new file mode 100644
index 000000000000..d342c0b6b2a7
--- /dev/null
+++ b/include/dt-bindings/reset/axg-aoclkc.h
@@ -0,0 +1,20 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */
+/*
+ * Copyright (c) 2016 BayLibre, SAS
+ * Author: Neil Armstrong <narmstrong at baylibre.com>
+ *
+ * Copyright (c) 2018 Amlogic, inc.
+ * Author: Qiufang Dai <qiufang.dai at amlogic.com>
+ */
+
+#ifndef DT_BINDINGS_RESET_AMLOGIC_MESON_AXG_AOCLK
+#define DT_BINDINGS_RESET_AMLOGIC_MESON_AXG_AOCLK
+
+#define RESET_AO_REMOTE		0
+#define RESET_AO_I2C_MASTER	1
+#define RESET_AO_I2C_SLAVE	2
+#define RESET_AO_UART1		3
+#define RESET_AO_UART2		4
+#define RESET_AO_IR_BLASTER	5
+
+#endif
-- 
2.15.1



From yixun.lan at amlogic.com  Mon Apr  9 07:37:47 2018
From: yixun.lan at amlogic.com (Yixun Lan)
Date: Mon, 9 Apr 2018 22:37:47 +0800
Subject: [PATCH v5 5/7] clk: meson-axg: Add AO Clock and Reset controller
 driver
In-Reply-To: <20180409143749.71197-1-yixun.lan@amlogic.com>
References: <20180409143749.71197-1-yixun.lan@amlogic.com>
Message-ID: <20180409143749.71197-6-yixun.lan@amlogic.com>

From: Qiufang Dai <qiufang.dai at amlogic.com>

Adds a Clock and Reset controller driver for the Always-On part
of the Amlogic Meson-AXG SoC.

Signed-off-by: Qiufang Dai <qiufang.dai at amlogic.com>
Signed-off-by: Yixun Lan <yixun.lan at amlogic.com>
---
 drivers/clk/meson/Kconfig     |   1 +
 drivers/clk/meson/Makefile    |   2 +-
 drivers/clk/meson/axg-aoclk.c | 164 ++++++++++++++++++++++++++++++++++++++++++
 drivers/clk/meson/axg-aoclk.h |  31 ++++++++
 4 files changed, 197 insertions(+), 1 deletion(-)
 create mode 100644 drivers/clk/meson/axg-aoclk.c
 create mode 100644 drivers/clk/meson/axg-aoclk.h

diff --git a/drivers/clk/meson/Kconfig b/drivers/clk/meson/Kconfig
index fddc7ec7b820..815659eebea3 100644
--- a/drivers/clk/meson/Kconfig
+++ b/drivers/clk/meson/Kconfig
@@ -38,6 +38,7 @@ config COMMON_CLK_AXG
 	bool
 	depends on COMMON_CLK_AMLOGIC
 	select RESET_CONTROLLER
+	select COMMON_CLK_MESON_AO
 	select COMMON_CLK_REGMAP_MESON
 	select MFD_SYSCON
 	help
diff --git a/drivers/clk/meson/Makefile b/drivers/clk/meson/Makefile
index 0a8df284f4e7..d0d13aeb369a 100644
--- a/drivers/clk/meson/Makefile
+++ b/drivers/clk/meson/Makefile
@@ -6,5 +6,5 @@ obj-$(CONFIG_COMMON_CLK_AMLOGIC) += clk-pll.o clk-mpll.o clk-audio-divider.o
 obj-$(CONFIG_COMMON_CLK_MESON_AO) += meson-aoclk.o
 obj-$(CONFIG_COMMON_CLK_MESON8B) += meson8b.o
 obj-$(CONFIG_COMMON_CLK_GXBB)	 += gxbb.o gxbb-aoclk.o gxbb-aoclk-32k.o
-obj-$(CONFIG_COMMON_CLK_AXG)	 += axg.o
+obj-$(CONFIG_COMMON_CLK_AXG)	 += axg.o axg-aoclk.o
 obj-$(CONFIG_COMMON_CLK_REGMAP_MESON)	+= clk-regmap.o
diff --git a/drivers/clk/meson/axg-aoclk.c b/drivers/clk/meson/axg-aoclk.c
new file mode 100644
index 000000000000..cb56d809d3df
--- /dev/null
+++ b/drivers/clk/meson/axg-aoclk.c
@@ -0,0 +1,164 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Amlogic Meson-AXG Clock Controller Driver
+ *
+ * Copyright (c) 2016 Baylibre SAS.
+ * Author: Michael Turquette <mturquette at baylibre.com>
+ *
+ * Copyright (c) 2018 Amlogic, inc.
+ * Author: Qiufang Dai <qiufang.dai at amlogic.com>
+ */
+#include <linux/clk-provider.h>
+#include <linux/platform_device.h>
+#include <linux/reset-controller.h>
+#include <linux/mfd/syscon.h>
+#include <linux/init.h>
+#include "clkc.h"
+#include "axg-aoclk.h"
+
+#define AXG_AO_GATE(_name, _bit)					\
+static struct clk_regmap _name##_ao = {					\
+	.data = &(struct clk_regmap_gate_data) {			\
+		.offset = (AO_RTI_GEN_CNTL_REG0),			\
+		.bit_idx = (_bit),					\
+	},								\
+	.hw.init = &(struct clk_init_data) {				\
+		.name = #_name "_ao",					\
+		.ops = &clk_regmap_gate_ops,				\
+		.parent_names = (const char *[]){ "clk81" },		\
+		.num_parents = 1,					\
+		.flags = CLK_IGNORE_UNUSED,				\
+	},								\
+}
+
+AXG_AO_GATE(remote, 0);
+AXG_AO_GATE(i2c_master, 1);
+AXG_AO_GATE(i2c_slave, 2);
+AXG_AO_GATE(uart1, 3);
+AXG_AO_GATE(uart2, 5);
+AXG_AO_GATE(ir_blaster, 6);
+AXG_AO_GATE(saradc, 7);
+
+static struct clk_regmap ao_clk81 = {
+	.data = &(struct clk_regmap_mux_data) {
+		.offset = AO_RTI_PWR_CNTL_REG0,
+		.mask = 0x1,
+		.shift = 8,
+	},
+	.hw.init = &(struct clk_init_data){
+		.name = "ao_clk81",
+		.ops = &clk_regmap_mux_ro_ops,
+		.parent_names = (const char *[]){ "clk81", "ao_alt_xtal"},
+		.num_parents = 2,
+	},
+};
+
+static struct clk_regmap axg_saradc_mux = {
+	.data = &(struct clk_regmap_mux_data) {
+		.offset = AO_SAR_CLK,
+		.mask = 0x3,
+		.shift = 9,
+	},
+	.hw.init = &(struct clk_init_data){
+		.name = "axg_saradc_mux",
+		.ops = &clk_regmap_mux_ops,
+		.parent_names = (const char *[]){ "xtal", "ao_clk81" },
+		.num_parents = 2,
+	},
+};
+
+static struct clk_regmap axg_saradc_div = {
+	.data = &(struct clk_regmap_div_data) {
+		.offset = AO_SAR_CLK,
+		.shift = 0,
+		.width = 8,
+	},
+	.hw.init = &(struct clk_init_data){
+		.name = "axg_saradc_div",
+		.ops = &clk_regmap_divider_ops,
+		.parent_names = (const char *[]){ "axg_saradc_mux" },
+		.num_parents = 1,
+		.flags = CLK_SET_RATE_PARENT,
+	},
+};
+
+static struct clk_regmap axg_saradc_gate = {
+	.data = &(struct clk_regmap_gate_data) {
+		.offset = AO_SAR_CLK,
+		.bit_idx = 8,
+	},
+	.hw.init = &(struct clk_init_data){
+		.name = "axg_saradc_gate",
+		.ops = &clk_regmap_gate_ops,
+		.parent_names = (const char *[]){ "axg_saradc_div" },
+		.num_parents = 1,
+		.flags = CLK_SET_RATE_PARENT,
+	},
+};
+
+static const unsigned int axg_aoclk_reset[] = {
+	[RESET_AO_REMOTE] = 16,
+	[RESET_AO_I2C_MASTER] = 18,
+	[RESET_AO_I2C_SLAVE] = 19,
+	[RESET_AO_UART1] = 17,
+	[RESET_AO_UART2] = 22,
+	[RESET_AO_IR_BLASTER] = 23,
+};
+
+static struct clk_regmap *axg_aoclk_regmap[] = {
+	[CLKID_AO_REMOTE]	= &remote_ao,
+	[CLKID_AO_I2C_MASTER]	= &i2c_master_ao,
+	[CLKID_AO_I2C_SLAVE]	= &i2c_slave_ao,
+	[CLKID_AO_UART1]	= &uart1_ao,
+	[CLKID_AO_UART2]	= &uart2_ao,
+	[CLKID_AO_IR_BLASTER]	= &ir_blaster_ao,
+	[CLKID_AO_SAR_ADC]	= &saradc_ao,
+	[CLKID_AO_CLK81]	= &ao_clk81,
+	[CLKID_AO_SAR_ADC_SEL]	= &axg_saradc_mux,
+	[CLKID_AO_SAR_ADC_DIV]	= &axg_saradc_div,
+	[CLKID_AO_SAR_ADC_CLK]	= &axg_saradc_gate,
+};
+
+static const struct clk_hw_onecell_data axg_aoclk_onecell_data = {
+	.hws = {
+		[CLKID_AO_REMOTE]	= &remote_ao.hw,
+		[CLKID_AO_I2C_MASTER]	= &i2c_master_ao.hw,
+		[CLKID_AO_I2C_SLAVE]	= &i2c_slave_ao.hw,
+		[CLKID_AO_UART1]	= &uart1_ao.hw,
+		[CLKID_AO_UART2]	= &uart2_ao.hw,
+		[CLKID_AO_IR_BLASTER]	= &ir_blaster_ao.hw,
+		[CLKID_AO_SAR_ADC]	= &saradc_ao.hw,
+		[CLKID_AO_CLK81]	= &ao_clk81.hw,
+		[CLKID_AO_SAR_ADC_SEL]	= &axg_saradc_mux.hw,
+		[CLKID_AO_SAR_ADC_DIV]	= &axg_saradc_div.hw,
+		[CLKID_AO_SAR_ADC_CLK]	= &axg_saradc_gate.hw,
+	},
+	.num = NR_CLKS,
+};
+
+static const struct meson_aoclk_data axg_aoclkc_data = {
+	.reset_reg	= AO_RTI_GEN_CNTL_REG0,
+	.num_reset	= ARRAY_SIZE(axg_aoclk_reset),
+	.reset		= axg_aoclk_reset,
+	.num_clks	= ARRAY_SIZE(axg_aoclk_regmap),
+	.clks		= axg_aoclk_regmap,
+	.hw_data	= &axg_aoclk_onecell_data,
+};
+
+static const struct of_device_id axg_aoclkc_match_table[] = {
+	{
+		.compatible	= "amlogic,meson-axg-aoclkc",
+		.data		= &axg_aoclkc_data,
+	},
+	{ }
+};
+
+static struct platform_driver axg_aoclkc_driver = {
+	.probe		= meson_aoclkc_probe,
+	.driver		= {
+		.name	= "axg-aoclkc",
+		.of_match_table = axg_aoclkc_match_table,
+	},
+};
+
+builtin_platform_driver(axg_aoclkc_driver);
diff --git a/drivers/clk/meson/axg-aoclk.h b/drivers/clk/meson/axg-aoclk.h
new file mode 100644
index 000000000000..396cd3023064
--- /dev/null
+++ b/drivers/clk/meson/axg-aoclk.h
@@ -0,0 +1,31 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2017 BayLibre, SAS
+ * Author: Neil Armstrong <narmstrong at baylibre.com>
+ *
+ * Copyright (c) 2018 Amlogic, inc.
+ * Author: Qiufang Dai <qiufang.dai at amlogic.com>
+ */
+
+#ifndef __AXG_AOCLKC_H
+#define __AXG_AOCLKC_H
+
+#include "meson-aoclk.h"
+
+#define NR_CLKS	11
+/* AO Configuration Clock registers offsets
+ * Register offsets from the data sheet must be multiplied by 4.
+ */
+#define AO_RTI_PWR_CNTL_REG1	0x0C
+#define AO_RTI_PWR_CNTL_REG0	0x10
+#define AO_RTI_GEN_CNTL_REG0	0x40
+#define AO_OSCIN_CNTL		0x58
+#define AO_CRT_CLK_CNTL1	0x68
+#define AO_SAR_CLK		0x90
+#define AO_RTC_ALT_CLK_CNTL0	0x94
+#define AO_RTC_ALT_CLK_CNTL1	0x98
+
+#include <dt-bindings/clock/axg-aoclkc.h>
+#include <dt-bindings/reset/axg-aoclkc.h>
+
+#endif /* __AXG_AOCLKC_H */
-- 
2.15.1



From yixun.lan at amlogic.com  Mon Apr  9 07:37:48 2018
From: yixun.lan at amlogic.com (Yixun Lan)
Date: Mon, 9 Apr 2018 22:37:48 +0800
Subject: [PATCH v5 6/7] clk: meson: drop CLK_SET_RATE_PARENT flag
In-Reply-To: <20180409143749.71197-1-yixun.lan@amlogic.com>
References: <20180409143749.71197-1-yixun.lan@amlogic.com>
Message-ID: <20180409143749.71197-7-yixun.lan@amlogic.com>

The clk81 is not expected to be changed, so drop this flag.

Signed-off-by: Yixun Lan <yixun.lan at amlogic.com>
---
 drivers/clk/meson/gxbb-aoclk.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/clk/meson/gxbb-aoclk.c b/drivers/clk/meson/gxbb-aoclk.c
index f2e0640a7f74..b3c90a17c0e0 100644
--- a/drivers/clk/meson/gxbb-aoclk.c
+++ b/drivers/clk/meson/gxbb-aoclk.c
@@ -70,7 +70,7 @@ static struct clk_regmap _name##_ao = {					\
 		.ops = &clk_regmap_gate_ops,				\
 		.parent_names = (const char *[]){ "clk81" },		\
 		.num_parents = 1,					\
-		.flags = (CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED),	\
+		.flags = CLK_IGNORE_UNUSED,				\
 	},								\
 }
 
-- 
2.15.1



From yixun.lan at amlogic.com  Mon Apr  9 07:37:49 2018
From: yixun.lan at amlogic.com (Yixun Lan)
Date: Mon, 9 Apr 2018 22:37:49 +0800
Subject: [PATCH v5 7/7] clk: meson: drop CLK_IGNORE_UNUSED flag
In-Reply-To: <20180409143749.71197-1-yixun.lan@amlogic.com>
References: <20180409143749.71197-1-yixun.lan@amlogic.com>
Message-ID: <20180409143749.71197-8-yixun.lan@amlogic.com>

Rely on drivers to request the clock explicitly.

Previous the kernel will leave the clock on while
bootloader adready initilized the clock, this wasn't
optimal way, so fix it here.

Signed-off-by: Yixun Lan <yixun.lan at amlogic.com>
---
 drivers/clk/meson/axg-aoclk.c  | 1 -
 drivers/clk/meson/gxbb-aoclk.c | 1 -
 2 files changed, 2 deletions(-)

diff --git a/drivers/clk/meson/axg-aoclk.c b/drivers/clk/meson/axg-aoclk.c
index cb56d809d3df..8457b64b9b7c 100644
--- a/drivers/clk/meson/axg-aoclk.c
+++ b/drivers/clk/meson/axg-aoclk.c
@@ -27,7 +27,6 @@ static struct clk_regmap _name##_ao = {					\
 		.ops = &clk_regmap_gate_ops,				\
 		.parent_names = (const char *[]){ "clk81" },		\
 		.num_parents = 1,					\
-		.flags = CLK_IGNORE_UNUSED,				\
 	},								\
 }
 
diff --git a/drivers/clk/meson/gxbb-aoclk.c b/drivers/clk/meson/gxbb-aoclk.c
index b3c90a17c0e0..2327eb609fbe 100644
--- a/drivers/clk/meson/gxbb-aoclk.c
+++ b/drivers/clk/meson/gxbb-aoclk.c
@@ -70,7 +70,6 @@ static struct clk_regmap _name##_ao = {					\
 		.ops = &clk_regmap_gate_ops,				\
 		.parent_names = (const char *[]){ "clk81" },		\
 		.num_parents = 1,					\
-		.flags = CLK_IGNORE_UNUSED,				\
 	},								\
 }
 
-- 
2.15.1



From jbrunet at baylibre.com  Mon Apr  9 07:54:29 2018
From: jbrunet at baylibre.com (Jerome Brunet)
Date: Mon,  9 Apr 2018 16:54:29 +0200
Subject: [PATCH] pinctrl: meson: axg: add tdm pins
Message-ID: <20180409145429.16619-1-jbrunet@baylibre.com>

Add the information related to the tdm pins of the A113D SoC

Signed-off-by: Jerome Brunet <jbrunet at baylibre.com>
---
 drivers/pinctrl/meson/pinctrl-meson-axg.c | 107 ++++++++++++++++++++++++++++++
 1 file changed, 107 insertions(+)

diff --git a/drivers/pinctrl/meson/pinctrl-meson-axg.c b/drivers/pinctrl/meson/pinctrl-meson-axg.c
index 4b91ff74779b..11dc23fde6d5 100644
--- a/drivers/pinctrl/meson/pinctrl-meson-axg.c
+++ b/drivers/pinctrl/meson/pinctrl-meson-axg.c
@@ -312,6 +312,47 @@ static const unsigned int pdm_din1_pins[] = {GPIOA_16};
 static const unsigned int pdm_din2_pins[] = {GPIOA_17};
 static const unsigned int pdm_din3_pins[] = {GPIOA_18};
 
+/* mclk */
+static const unsigned int mclk_c_pins[] = {GPIOA_0};
+static const unsigned int mclk_b_pins[] = {GPIOA_1};
+
+/* tdm */
+static const unsigned int tdma_sclk_pins[] = {GPIOX_12};
+static const unsigned int tdma_sclk_slv_pins[] = {GPIOX_12};
+static const unsigned int tdma_fs_pins[] = {GPIOX_13};
+static const unsigned int tdma_fs_slv_pins[] = {GPIOX_13};
+static const unsigned int tdma_din0_pins[] = {GPIOX_14};
+static const unsigned int tdma_dout0_x14_pins[] = {GPIOX_14};
+static const unsigned int tdma_dout0_x15_pins[] = {GPIOX_15};
+static const unsigned int tdma_dout1_pins[] = {GPIOX_15};
+static const unsigned int tdma_din1_pins[] = {GPIOX_15};
+
+static const unsigned int tdmc_sclk_pins[] = {GPIOA_2};
+static const unsigned int tdmc_sclk_slv_pins[] = {GPIOA_2};
+static const unsigned int tdmc_fs_pins[] = {GPIOA_3};
+static const unsigned int tdmc_fs_slv_pins[] = {GPIOA_3};
+static const unsigned int tdmc_din0_pins[] = {GPIOA_4};
+static const unsigned int tdmc_dout0_pins[] = {GPIOA_4};
+static const unsigned int tdmc_din1_pins[] = {GPIOA_5};
+static const unsigned int tdmc_dout1_pins[] = {GPIOA_5};
+static const unsigned int tdmc_din2_pins[] = {GPIOA_6};
+static const unsigned int tdmc_dout2_pins[] = {GPIOA_6};
+static const unsigned int tdmc_din3_pins[] = {GPIOA_7};
+static const unsigned int tdmc_dout3_pins[] = {GPIOA_7};
+
+static const unsigned int tdmb_sclk_pins[] = {GPIOA_8};
+static const unsigned int tdmb_sclk_slv_pins[] = {GPIOA_8};
+static const unsigned int tdmb_fs_pins[] = {GPIOA_9};
+static const unsigned int tdmb_fs_slv_pins[] = {GPIOA_9};
+static const unsigned int tdmb_din0_pins[] = {GPIOA_10};
+static const unsigned int tdmb_dout0_pins[] = {GPIOA_10};
+static const unsigned int tdmb_din1_pins[] = {GPIOA_11};
+static const unsigned int tdmb_dout1_pins[] = {GPIOA_11};
+static const unsigned int tdmb_din2_pins[] = {GPIOA_12};
+static const unsigned int tdmb_dout2_pins[] = {GPIOA_12};
+static const unsigned int tdmb_din3_pins[] = {GPIOA_13};
+static const unsigned int tdmb_dout3_pins[] = {GPIOA_13};
+
 static struct meson_pmx_group meson_axg_periphs_groups[] = {
 	GPIO_GROUP(GPIOZ_0),
 	GPIO_GROUP(GPIOZ_1),
@@ -495,6 +536,15 @@ static struct meson_pmx_group meson_axg_periphs_groups[] = {
 	GROUP(eth_rx_dv_x, 4),
 	GROUP(eth_mdio_x, 4),
 	GROUP(eth_mdc_x, 4),
+	GROUP(tdma_sclk, 1),
+	GROUP(tdma_sclk_slv, 2),
+	GROUP(tdma_fs, 1),
+	GROUP(tdma_fs_slv, 2),
+	GROUP(tdma_din0, 1),
+	GROUP(tdma_dout0_x14, 2),
+	GROUP(tdma_dout0_x15, 1),
+	GROUP(tdma_dout1, 2),
+	GROUP(tdma_din1, 3),
 
 	/* bank GPIOY */
 	GROUP(eth_txd0_y, 1),
@@ -544,6 +594,32 @@ static struct meson_pmx_group meson_axg_periphs_groups[] = {
 	GROUP(pdm_din1, 1),
 	GROUP(pdm_din2, 1),
 	GROUP(pdm_din3, 1),
+	GROUP(mclk_c, 1),
+	GROUP(mclk_b, 1),
+	GROUP(tdmc_sclk, 1),
+	GROUP(tdmc_sclk_slv, 2),
+	GROUP(tdmc_fs, 1),
+	GROUP(tdmc_fs_slv, 2),
+	GROUP(tdmc_din0, 2),
+	GROUP(tdmc_dout0, 1),
+	GROUP(tdmc_din1, 2),
+	GROUP(tdmc_dout1, 1),
+	GROUP(tdmc_din2, 2),
+	GROUP(tdmc_dout2, 1),
+	GROUP(tdmc_din3, 2),
+	GROUP(tdmc_dout3, 1),
+	GROUP(tdmb_sclk, 1),
+	GROUP(tdmb_sclk_slv, 2),
+	GROUP(tdmb_fs, 1),
+	GROUP(tdmb_fs_slv, 2),
+	GROUP(tdmb_din0, 2),
+	GROUP(tdmb_dout0, 1),
+	GROUP(tdmb_din1, 2),
+	GROUP(tdmb_dout1, 1),
+	GROUP(tdmb_din2, 2),
+	GROUP(tdmb_dout2, 1),
+	GROUP(tdmb_din3, 2),
+	GROUP(tdmb_dout3, 1),
 };
 
 /* uart_ao_a */
@@ -845,6 +921,32 @@ static const char * const jtag_ao_groups[] = {
 	"jtag_ao_tdi", "jtag_ao_tdo", "jtag_ao_clk", "jtag_ao_tms",
 };
 
+static const char * const mclk_c_groups[] = {
+	"mclk_c",
+};
+
+static const char * const mclk_b_groups[] = {
+	"mclk_b",
+};
+
+static const char * const tdma_groups[] = {
+	"tdma_sclk", "tdma_sclk_slv", "tdma_fs", "tdma_fs_slv",
+	"tdma_din0", "tdma_dout0_x14", "tdma_dout0_x15", "tdma_dout1",
+	"tdma_din1",
+};
+
+static const char * const tdmc_groups[] = {
+	"tdmc_sclk", "tdmc_sclk_slv", "tdmc_fs", "tdmc_fs_slv",
+	"tdmc_din0", "tdmc_dout0", "tdmc_din1",	"tdmc_dout1",
+	"tdmc_din2", "tdmc_dout2", "tdmc_din3",	"tdmc_dout3",
+};
+
+static const char * const tdmb_groups[] = {
+	"tdmb_sclk", "tdmb_sclk_slv", "tdmb_fs", "tdmb_fs_slv",
+	"tdmb_din0", "tdmb_dout0", "tdmb_din1",	"tdmb_dout1",
+	"tdmb_din2", "tdmb_dout2", "tdmb_din3",	"tdmb_dout3",
+};
+
 static struct meson_pmx_func meson_axg_periphs_functions[] = {
 	FUNCTION(gpio_periphs),
 	FUNCTION(emmc),
@@ -870,6 +972,11 @@ static struct meson_pmx_func meson_axg_periphs_functions[] = {
 	FUNCTION(spdif_in),
 	FUNCTION(jtag_ee),
 	FUNCTION(pdm),
+	FUNCTION(mclk_b),
+	FUNCTION(mclk_c),
+	FUNCTION(tdma),
+	FUNCTION(tdmb),
+	FUNCTION(tdmc),
 };
 
 static struct meson_pmx_func meson_axg_aobus_functions[] = {
-- 
2.14.3



From j-keerthy at ti.com  Mon Apr  9 21:06:15 2018
From: j-keerthy at ti.com (Keerthy)
Date: Tue, 10 Apr 2018 09:36:15 +0530
Subject: [PATCH usb v5 0/6] usb/core/phy fixes for v4.17
In-Reply-To: <20180408212743.22934-1-martin.blumenstingl@googlemail.com>
References: <20180408212743.22934-1-martin.blumenstingl@googlemail.com>
Message-ID: <84fa5dd7-de41-18b5-d772-095545dc1c63@ti.com>



On Monday 09 April 2018 02:57 AM, Martin Blumenstingl wrote:
> This is a follow-up to my previous series "initialize (multiple) PHYs
> for a HCD": [0].
> 
> Roger Quadros reported [1] that it "is breaking low power cases on TI
> SoCs when USB is in host mode". He further explains that "Not doing the
> phy_exit() here [when entering suspend] leaves the clocks enabled on
> our SoC and we're no longer able to reach low power states on system
> suspend."
> Chunfeng Yun from Mediatek noted [2] that we cannot unconditionally call
> phy_exit while entering system suspend, because this would "disconnect
> plugged devices on MTK platforms, due to re-initialize u2 phys when
> resume"
> 
> In the discussion (which followed Roger's bug report: [1]) Roger,
> Chunfeng and me came to the conclusion that we can fix suspend on the
> TI SoCs without breaking it on the Mediatek SoCs by extending the
> suspend and resume code in usb/core/phy.c by checking whether the USB
> controller can wake up the system (which is the case for the Mediatek
> MTU3 controller, but now for the dwc3 controller used on the TI SoCs):
> - if the controller can wake up the system (Mediatek MTU3 use-case) we
>   only call usb_phy_roothub_power_off (which calls phy_power_off) when
>   entering system suspend
> - if the controller however cannot wake up the system (dwc3 on TI SoCs)
>   we additionally call usb_phy_roothub_exit (which calls phy_exit) when
>   entering system suspend
> - (we undo the previous steps during system resume)
> 
> The goal of this series is to fix the issue reported by Roger without
> breaking suspend/resume on the Mediatek SoCs.
> Since I neither have a TI nor a Mediatek device I am sending this as
> RFC. I have tested it on an Amlogic Meson GXM board (Khadas VIM2) which
> does NOT support suspend/resume yet.
> 
> Additionally Stefan Wahren reported [7] that booting on a Raspberry Pi
> with CONFIG_GENERIC_PHY being disabled (which is the case for
> bcm2835_defconfig) breaks USB. A fix for this is also included.
> 

FWIW

The series fixes suspend/resume on TI AM437X-GP-EVM platform.

Tested-by: Keerthy <j-keerthy at ti.com>

Regards,
Keerthy
> 
> changes since v4 at [8]
> - updated series title since it now includes fixes for other
>   functionality than suspend
> - rebased on top of f8cf2f16a7c95a from Linus' tree -> I will re-send
>   an updated version once v4.17-rc1 is out, I just sent it early to
>   get some feedback early!
> - included patch [3] "usb: core: phy: fix return value of
>   usb_phy_roothub_exit()" in this series
> - fix the logic if CONFIG_GENERIC_PHY is disabled (as reported by
>   Stefan Wahren, new patch #4)
> - two minor coding style fixes as suggested by Masahiro Yamada (new
>   patches #4 and #5)
> 
> changes since RFC v3 at [6]:
> - added Chunfeng Yun's Tested-by and Roger Quadros' Reviewed-by (thank
>   you!)
> - dropped RFC prefix
> 
> changes since RFC v2 at [5]:
> - add missing INIT_LIST_HEAD call in usb_phy_roothub_add_phy (affects
>   patch #1 - spotted by Roger Quadros, thank you!)
> - fixed swapped conditions using device_may_wakeup() in
>   usb_phy_roothub_resume because we need to call usb_phy_roothub_init
>   if the controller cannot wake up the device (affects patch #2, spotted
>   by Chunfeng Yun, thank you!)
> - simplified the error condition to "undo" usb_phy_roothub_init if
>   usb_phy_roothub_power_on failed in usb_phy_roothub_resume (suggested
>   by Chunfeng Yun)
> - updated the commit message (using Roger's wording) because (quote from
>   Roger "it doesn't prevent the system from entering suspend but just
>   prevents the system from reaching lowest power levels in the suspend
>   state."
> 
> Changes since RFC v1 (blob attachments) at [4]:
> - use device_may_wakeup instead of device_can_wakeup as suggested by
>   Roger Quadros
> - use the controller device from hcd->self.controller as suggested by
>   Chunfeng Yun
> - compile time fixes thanks to Roger Quadros
> - if usb_phy_roothub_power_on in usb_phy_roothub_resume failes then
>   we now call usb_phy_roothub_exit to keep the PHYs in the correct
>   state if usb_phy_roothub_resume partially failed
> 
> 
> [0] http://lists.infradead.org/pipermail/linux-amlogic/2018-March/006599.html
> [1] http://lists.infradead.org/pipermail/linux-amlogic/2018-March/006737.html
> [2] http://lists.infradead.org/pipermail/linux-amlogic/2018-March/006758.html
> [3] http://lists.infradead.org/pipermail/linux-amlogic/2018-March/006819.html
> [4] http://lists.infradead.org/pipermail/linux-amlogic/2018-March/006794.html
> [5] http://lists.infradead.org/pipermail/linux-amlogic/2018-March/006820.html
> [6] http://lists.infradead.org/pipermail/linux-amlogic/2018-March/006847.html
> [7] https://www.spinics.net/lists/linux-usb/msg167472.html
> [8] http://lists.infradead.org/pipermail/linux-amlogic/2018-March/006882.html
> 
> 
> Martin Blumenstingl (6):
>   usb: core: phy: fix return value of usb_phy_roothub_exit()
>   usb: core: split usb_phy_roothub_{init,alloc}
>   usb: core: use phy_exit during suspend if wake up is not supported
>   usb: core: phy: make it a no-op if CONFIG_GENERIC_PHY is disabled
>   usb: core: phy: add missing forward declaration for "struct device"
>   usb: core: phy: add the SPDX-License-Identifier and include guard
> 
>  drivers/usb/core/hcd.c | 18 +++++---
>  drivers/usb/core/phy.c | 93 ++++++++++++++++++++++++++++++------------
>  drivers/usb/core/phy.h | 22 +++++++++-
>  3 files changed, 99 insertions(+), 34 deletions(-)
> 


From narmstrong at baylibre.com  Tue Apr 10 06:51:01 2018
From: narmstrong at baylibre.com (Neil Armstrong)
Date: Tue, 10 Apr 2018 15:51:01 +0200
Subject: [PATCH u-boot 2/2] ARM: meson: Add cpu info display for GX SoCs
In-Reply-To: <CAPnjgZ0w9v6_6Qiw0uzKzFcTOMThtcQ6C6Q0gnKfHnX9ZZihUQ@mail.gmail.com>
References: <1522230877-21267-1-git-send-email-narmstrong@baylibre.com>
 <1522230877-21267-3-git-send-email-narmstrong@baylibre.com>
 <CAPnjgZ0w9v6_6Qiw0uzKzFcTOMThtcQ6C6Q0gnKfHnX9ZZihUQ@mail.gmail.com>
Message-ID: <08220462-5c2e-0858-31bb-c899d8801350@baylibre.com>

On 08/04/2018 15:50, Simon Glass wrote:
> Hi,
> 
> On 28 March 2018 at 05:54, Neil Armstrong <narmstrong at baylibre.com> wrote:
>> The Amlogic SoCs have a registers containing the die revision
>> and packaging type to determine the SoC family and package marketing
>> name like S905X for the GXL SoC Family.
>> This code is taken for the Linux meson-gx-socinfo driver and adapted
>> to U-Boot printing.
>>
>> Signed-off-by: Neil Armstrong <narmstrong at baylibre.com>
>> ---
>>  arch/arm/include/asm/arch-meson/gx.h |   1 +
>>  arch/arm/mach-meson/Makefile         |   2 +-
>>  arch/arm/mach-meson/cpu_info.c       | 105 +++++++++++++++++++++++++++++++++++
>>  configs/khadas-vim_defconfig         |   2 +-
>>  configs/libretech-cc_defconfig       |   2 +-
>>  configs/odroid-c2_defconfig          |   2 +-
>>  configs/odroid_defconfig             |   1 +
>>  configs/p212_defconfig               |   2 +-
>>  8 files changed, 112 insertions(+), 5 deletions(-)
>>  create mode 100644 arch/arm/mach-meson/cpu_info.c
> 
> Please can you use driver model's CPU interface for this?
> 
> Regards,
> Simon
> 

Hi Simon,

The CPU uclass is designed for the /cpu/* nodes, here we fetch the SoC information
in some /soc/ subnodes which cannot be used with the current CPU uclass and
won't be probed before relocation.

Either I push is as a MISC driver (with the pre-reloc issue) or we leave this in mach-meson.

What do you think ?

Thanks,
Neil


From sjg at chromium.org  Tue Apr 10 07:37:18 2018
From: sjg at chromium.org (Simon Glass)
Date: Tue, 10 Apr 2018 10:37:18 -0400
Subject: [PATCH u-boot 2/2] ARM: meson: Add cpu info display for GX SoCs
In-Reply-To: <08220462-5c2e-0858-31bb-c899d8801350@baylibre.com>
References: <1522230877-21267-1-git-send-email-narmstrong@baylibre.com>
 <1522230877-21267-3-git-send-email-narmstrong@baylibre.com>
 <CAPnjgZ0w9v6_6Qiw0uzKzFcTOMThtcQ6C6Q0gnKfHnX9ZZihUQ@mail.gmail.com>
 <08220462-5c2e-0858-31bb-c899d8801350@baylibre.com>
Message-ID: <CAPnjgZ1p30RsGntT59gDQ9xrTFo0TH6Wkv5EL8sf0q6QF45rPQ@mail.gmail.com>

Hi Neil,

On 10 April 2018 at 09:51, Neil Armstrong <narmstrong at baylibre.com> wrote:
> On 08/04/2018 15:50, Simon Glass wrote:
>> Hi,
>>
>> On 28 March 2018 at 05:54, Neil Armstrong <narmstrong at baylibre.com> wrote:
>>> The Amlogic SoCs have a registers containing the die revision
>>> and packaging type to determine the SoC family and package marketing
>>> name like S905X for the GXL SoC Family.
>>> This code is taken for the Linux meson-gx-socinfo driver and adapted
>>> to U-Boot printing.
>>>
>>> Signed-off-by: Neil Armstrong <narmstrong at baylibre.com>
>>> ---
>>>  arch/arm/include/asm/arch-meson/gx.h |   1 +
>>>  arch/arm/mach-meson/Makefile         |   2 +-
>>>  arch/arm/mach-meson/cpu_info.c       | 105 +++++++++++++++++++++++++++++++++++
>>>  configs/khadas-vim_defconfig         |   2 +-
>>>  configs/libretech-cc_defconfig       |   2 +-
>>>  configs/odroid-c2_defconfig          |   2 +-
>>>  configs/odroid_defconfig             |   1 +
>>>  configs/p212_defconfig               |   2 +-
>>>  8 files changed, 112 insertions(+), 5 deletions(-)
>>>  create mode 100644 arch/arm/mach-meson/cpu_info.c
>>
>> Please can you use driver model's CPU interface for this?
>>
>> Regards,
>> Simon
>>
>
> Hi Simon,
>
> The CPU uclass is designed for the /cpu/* nodes, here we fetch the SoC information
> in some /soc/ subnodes which cannot be used with the current CPU uclass and
> won't be probed before relocation.
>
> Either I push is as a MISC driver (with the pre-reloc issue) or we leave this in mach-meson.
>
> What do you think ?

Do you think it could search both /cpu and /soc ? They seem to be
fairly equivalent. Is that the only problem?

>
> Thanks,
> Neil

Regards,
Simon


From hias at horus.com  Tue Apr 10 10:53:43 2018
From: hias at horus.com (Matthias Reichl)
Date: Tue, 10 Apr 2018 19:53:43 +0200
Subject: [PATCH v2 0/7] Improve latency of IR decoding
In-Reply-To: <cover.1523221902.git.sean@mess.org>
References: <cover.1523221902.git.sean@mess.org>
Message-ID: <20180410175343.hu423iejripoqdkj@camel2.lan>

Hi Sean,

On Sun, Apr 08, 2018 at 10:19:35PM +0100, Sean Young wrote:
> The current IR decoding is much too slow. Many IR protocols rely on
> a trailing space for decoding (e.g. rc-6 needs to know when the bits
> end). The trailing space is generated by the IR timeout, and if this
> is longer than required, buttons can feel slow to respond.
> 
> The other issue is the keyup timer. IR has no concept of a keyup message,
> this is implied by the absence of IR. So, minimising the timeout for
> this makes buttons less "sticky"; the are released much quicker.
> 
> With these patches in place, using IR with the builtin decoders is much
> improved and feels very snappy.
> 
> Changes since v1:
>  - lost more testing
>  - fixed various issues with mce decoder
>  - fixed mceusb so it can use better timeout too

thanks, this version is working fine with meson-ir and gpio-rc-recv
(latter on RPi). I mainly tested it with rc-5 remotes so far, more
will follow and I'll update LibreELEC in a day or two to include
the v2 series.

Also thanks a lot for the mce_kbd fixes, I was just going to dig
into the decoder (we received a bug report about stuck keys with
mce_kbd last week), your patches can in just at the right time :)

I had a closer look at ir-mce_kbd-decoder.c and noticed 2 things
(which can be handled separately):

It looks like the input_sync call in the state machine error
path is not necessary:

out:
	dev_dbg(&dev->dev, "failed at state %i (%uus %s)\n",
		data->state, TO_US(ev.duration), TO_STR(ev.pulse));
	data->state = STATE_INACTIVE;
	input_sync(data->idev);
	return -EINVAL;

If I followed the code paths correctly states that generate
input events won't go to out, only paths were no events are
generated jump to out - but better verify that, I could have
missed something.

The other thing I noticed is that there's no spinlock synchronizing
the events from the timeout callback with the ones from the state
machine - like keylock in rc-main. So the code could potentially
be racy (if the timeout fires while the state machine is outputting
events).

so long,

Hias

> 
> Sean Young (7):
>   media: rc: set timeout to smallest value required by enabled protocols
>   media: rc: add ioctl to get the current timeout
>   media: rc: per-protocol repeat period and minimum keyup timer
>   media: rc: mce_kbd decoder: low timeout values cause double keydowns
>   media: rc: mce_kbd protocol encodes two scancodes
>   media: rc: mce_kbd decoder: fix stuck keys
>   media: rc: mceusb: allow the timeout to be configurable
> 
>  Documentation/media/uapi/rc/lirc-func.rst          |  1 +
>  .../media/uapi/rc/lirc-set-rec-timeout.rst         | 14 +++--
>  drivers/media/cec/cec-core.c                       |  2 +-
>  drivers/media/rc/ir-imon-decoder.c                 |  1 +
>  drivers/media/rc/ir-jvc-decoder.c                  |  1 +
>  drivers/media/rc/ir-mce_kbd-decoder.c              | 36 +++++++-----
>  drivers/media/rc/ir-nec-decoder.c                  |  1 +
>  drivers/media/rc/ir-rc5-decoder.c                  |  1 +
>  drivers/media/rc/ir-rc6-decoder.c                  |  1 +
>  drivers/media/rc/ir-sanyo-decoder.c                |  1 +
>  drivers/media/rc/ir-sharp-decoder.c                |  1 +
>  drivers/media/rc/ir-sony-decoder.c                 |  1 +
>  drivers/media/rc/ir-xmp-decoder.c                  |  1 +
>  drivers/media/rc/lirc_dev.c                        |  9 ++-
>  drivers/media/rc/mceusb.c                          | 22 +++++++
>  drivers/media/rc/rc-core-priv.h                    |  1 +
>  drivers/media/rc/rc-ir-raw.c                       | 31 +++++++++-
>  drivers/media/rc/rc-main.c                         | 68 +++++++++++-----------
>  include/uapi/linux/lirc.h                          |  6 ++
>  19 files changed, 144 insertions(+), 55 deletions(-)
> 
> -- 
> 2.14.3
> 


From sean at mess.org  Tue Apr 10 11:39:43 2018
From: sean at mess.org (Sean Young)
Date: Tue, 10 Apr 2018 19:39:43 +0100
Subject: [PATCH v2 0/7] Improve latency of IR decoding
In-Reply-To: <20180410175343.hu423iejripoqdkj@camel2.lan>
References: <cover.1523221902.git.sean@mess.org>
 <20180410175343.hu423iejripoqdkj@camel2.lan>
Message-ID: <20180410183943.riwpqphvthuigpmz@gofer.mess.org>

On Tue, Apr 10, 2018 at 07:53:43PM +0200, Matthias Reichl wrote:
> Hi Sean,
> 
> On Sun, Apr 08, 2018 at 10:19:35PM +0100, Sean Young wrote:
> > The current IR decoding is much too slow. Many IR protocols rely on
> > a trailing space for decoding (e.g. rc-6 needs to know when the bits
> > end). The trailing space is generated by the IR timeout, and if this
> > is longer than required, buttons can feel slow to respond.
> > 
> > The other issue is the keyup timer. IR has no concept of a keyup message,
> > this is implied by the absence of IR. So, minimising the timeout for
> > this makes buttons less "sticky"; the are released much quicker.
> > 
> > With these patches in place, using IR with the builtin decoders is much
> > improved and feels very snappy.
> > 
> > Changes since v1:
> >  - lost more testing
> >  - fixed various issues with mce decoder
> >  - fixed mceusb so it can use better timeout too
> 
> thanks, this version is working fine with meson-ir and gpio-rc-recv
> (latter on RPi). I mainly tested it with rc-5 remotes so far, more
> will follow and I'll update LibreELEC in a day or two to include
> the v2 series.

Thanks again for testing!

> Also thanks a lot for the mce_kbd fixes, I was just going to dig
> into the decoder (we received a bug report about stuck keys with
> mce_kbd last week), your patches can in just at the right time :)
> 
> I had a closer look at ir-mce_kbd-decoder.c and noticed 2 things
> (which can be handled separately):
> 
> It looks like the input_sync call in the state machine error
> path is not necessary:
> 
> out:
> 	dev_dbg(&dev->dev, "failed at state %i (%uus %s)\n",
> 		data->state, TO_US(ev.duration), TO_STR(ev.pulse));
> 	data->state = STATE_INACTIVE;
> 	input_sync(data->idev);
> 	return -EINVAL;
> 
> If I followed the code paths correctly states that generate
> input events won't go to out, only paths were no events are
> generated jump to out - but better verify that, I could have
> missed something.

The input_sync() patch is in mce_kbd_rx_timeout() code path, which
doesn't go through this. Hopefully it should fix the keys stuck
issue.

> The other thing I noticed is that there's no spinlock synchronizing
> the events from the timeout callback with the ones from the state
> machine - like keylock in rc-main. So the code could potentially
> be racy (if the timeout fires while the state machine is outputting
> events).

This timeout is for sending keyups in case no keyup is received from
the keyboard via input_report_key(). The input system does locking
for us (see drivers/input/input.c:436).


Sean


From hias at horus.com  Tue Apr 10 12:24:19 2018
From: hias at horus.com (Matthias Reichl)
Date: Tue, 10 Apr 2018 21:24:19 +0200
Subject: [PATCH v2 0/7] Improve latency of IR decoding
In-Reply-To: <20180410183943.riwpqphvthuigpmz@gofer.mess.org>
References: <cover.1523221902.git.sean@mess.org>
 <20180410175343.hu423iejripoqdkj@camel2.lan>
 <20180410183943.riwpqphvthuigpmz@gofer.mess.org>
Message-ID: <20180410192419.wqiqgd7kpdigavf4@camel2.lan>

On Tue, Apr 10, 2018 at 07:39:43PM +0100, Sean Young wrote:
> On Tue, Apr 10, 2018 at 07:53:43PM +0200, Matthias Reichl wrote:
> > Hi Sean,
> > 
> > On Sun, Apr 08, 2018 at 10:19:35PM +0100, Sean Young wrote:
> > > The current IR decoding is much too slow. Many IR protocols rely on
> > > a trailing space for decoding (e.g. rc-6 needs to know when the bits
> > > end). The trailing space is generated by the IR timeout, and if this
> > > is longer than required, buttons can feel slow to respond.
> > > 
> > > The other issue is the keyup timer. IR has no concept of a keyup message,
> > > this is implied by the absence of IR. So, minimising the timeout for
> > > this makes buttons less "sticky"; the are released much quicker.
> > > 
> > > With these patches in place, using IR with the builtin decoders is much
> > > improved and feels very snappy.
> > > 
> > > Changes since v1:
> > >  - lost more testing
> > >  - fixed various issues with mce decoder
> > >  - fixed mceusb so it can use better timeout too
> > 
> > thanks, this version is working fine with meson-ir and gpio-rc-recv
> > (latter on RPi). I mainly tested it with rc-5 remotes so far, more
> > will follow and I'll update LibreELEC in a day or two to include
> > the v2 series.
> 
> Thanks again for testing!
> 
> > Also thanks a lot for the mce_kbd fixes, I was just going to dig
> > into the decoder (we received a bug report about stuck keys with
> > mce_kbd last week), your patches can in just at the right time :)
> > 
> > I had a closer look at ir-mce_kbd-decoder.c and noticed 2 things
> > (which can be handled separately):
> > 
> > It looks like the input_sync call in the state machine error
> > path is not necessary:
> > 
> > out:
> > 	dev_dbg(&dev->dev, "failed at state %i (%uus %s)\n",
> > 		data->state, TO_US(ev.duration), TO_STR(ev.pulse));
> > 	data->state = STATE_INACTIVE;
> > 	input_sync(data->idev);
> > 	return -EINVAL;
> > 
> > If I followed the code paths correctly states that generate
> > input events won't go to out, only paths were no events are
> > generated jump to out - but better verify that, I could have
> > missed something.
> 
> The input_sync() patch is in mce_kbd_rx_timeout() code path, which
> doesn't go through this. Hopefully it should fix the keys stuck
> issue.

Yes, I saw that and the input_sync() in mce_kbd_rx_timeout() fixed
this (I could verify that locally).

What I meant is that the input_sync() in the snippet above, which
isn't touched by your patches, doesn't seem necessary, as the
code paths that lead to there don't submit input events. The
happy paths (successful key/mouse event and keyup) call input_sync()
at the end of STATE_FINISHED:

		lsc.scancode = scancode;
		ir_lirc_scancode_event(dev, &lsc);
		data->state = STATE_INACTIVE;
		input_event(data->idev, EV_MSC, MSC_SCAN, scancode);
		input_sync(data->idev);
		return 0;

> > The other thing I noticed is that there's no spinlock synchronizing
> > the events from the timeout callback with the ones from the state
> > machine - like keylock in rc-main. So the code could potentially
> > be racy (if the timeout fires while the state machine is outputting
> > events).
> 
> This timeout is for sending keyups in case no keyup is received from
> the keyboard via input_report_key(). The input system does locking
> for us (see drivers/input/input.c:436).

The synchronization code in rc-main looks like it's used to make
code blocks that eg call input_report_key and input_sync do that
in an atomic way (plus there's the special handling of keyup_jiffies
to prevent a race betwen the keyup timeout callback and new
decoded scancodes.

As both the timeout callback and the state machine send out
multiple key events and end them with input_sync it looks to me
like we'd need to make that atomic as well. Otherwise we could
have eg timeout running, starting to report a bunch of shift
and other keys as up, then interruption by a new key/scancode
calling input_report_key down plus input_sync and then timeout
resuming and reporting the rest of the keys down and again
do input_sync().

so long,

Hias


From trini at konsulko.com  Wed Apr 11 07:04:44 2018
From: trini at konsulko.com (Tom Rini)
Date: Wed, 11 Apr 2018 10:04:44 -0400
Subject: [U-Boot,u-boot] reset: Add Amlogic Meson Reset Controller
In-Reply-To: <1522328125-13670-1-git-send-email-narmstrong@baylibre.com>
References: <1522328125-13670-1-git-send-email-narmstrong@baylibre.com>
Message-ID: <20180411140444.GW10996@bill-the-cat.ec.rr.com>

On Thu, Mar 29, 2018 at 02:55:25PM +0200, Neil Armstrong wrote:

> The Amlogic Meson SoCs embeds up to 256 reset lines, add the corresponding
> driver.
> 
> Signed-off-by: Neil Armstrong <narmstrong at baylibre.com>

Applied to u-boot/master, thanks!

-- 
Tom
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From trini at konsulko.com  Wed Apr 11 07:04:50 2018
From: trini at konsulko.com (Tom Rini)
Date: Wed, 11 Apr 2018 10:04:50 -0400
Subject: [U-Boot] serial: meson: Update compatible with new Linux bindings
In-Reply-To: <1522328162-13786-1-git-send-email-narmstrong@baylibre.com>
References: <1522328162-13786-1-git-send-email-narmstrong@baylibre.com>
Message-ID: <20180411140450.GX10996@bill-the-cat.ec.rr.com>

On Thu, Mar 29, 2018 at 02:56:02PM +0200, Neil Armstrong wrote:

> The Amlogic Meson SoCs serial bindings were not written when serial
> support was pushed into Linux and U-Boot.
> A clean bindings document has been merged into Linux tree to correctly
> handle the multiple clocks feeding the serial peripheral.
> This update the U-Boot serial_meson driver with the new compatible
> string for Amlogic Meson GX Socs.
> 
> Signed-off-by: Neil Armstrong <narmstrong at baylibre.com>
> Reviewed-by: Simon Glass <sjg at chromium.org>

Applied to u-boot/master, thanks!

-- 
Tom
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From trini at konsulko.com  Wed Apr 11 07:05:18 2018
From: trini at konsulko.com (Tom Rini)
Date: Wed, 11 Apr 2018 10:05:18 -0400
Subject: [U-Boot, v2, u-boot, 1/2] reset: Add get/assert/deassert/release
 for bulk of reset signals
In-Reply-To: <1522748451-21209-2-git-send-email-narmstrong@baylibre.com>
References: <1522748451-21209-2-git-send-email-narmstrong@baylibre.com>
Message-ID: <20180411140518.GC10996@bill-the-cat.ec.rr.com>

On Tue, Apr 03, 2018 at 11:40:50AM +0200, Neil Armstrong wrote:

> This patch adds a "bulk" API to the reset API in order to get/deassert/
> assert/release a group of reset signals associated with a device.
> 
> This bulk API will avoid adding a copy of the same code to manage
> a group of reset signals in drivers.
> 
> Signed-off-by: Neil Armstrong <narmstrong at baylibre.com>
> Reviewed-by: Simon Glass <sjg at chromium.org>

Applied to u-boot/master, thanks!

-- 
Tom
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From trini at konsulko.com  Wed Apr 11 07:05:24 2018
From: trini at konsulko.com (Tom Rini)
Date: Wed, 11 Apr 2018 10:05:24 -0400
Subject: [U-Boot,v2,u-boot,2/2] reset: add sandbox test for bulk API
In-Reply-To: <1522748451-21209-3-git-send-email-narmstrong@baylibre.com>
References: <1522748451-21209-3-git-send-email-narmstrong@baylibre.com>
Message-ID: <20180411140524.GD10996@bill-the-cat.ec.rr.com>

On Tue, Apr 03, 2018 at 11:40:51AM +0200, Neil Armstrong wrote:

> This patch adds the bulk reset API tests for the sandbox test suite.
> 
> Unlike the main test, it also check the "other" reset signal using the bulk API
> and checks if the resets are correctly asserted/deasserted.
> 
> To allow the bulk API to work, and avoid changing the DT, the number of resets
> of the sandbox reset controller has been bumped to 101 for the "other" reset
> line to be valid.
> 
> Signed-off-by: Neil Armstrong <narmstrong at baylibre.com>
> Reviewed-by: Simon Glass <sjg at chromium.org>

Applied to u-boot/master, thanks!

-- 
Tom
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From trini at konsulko.com  Wed Apr 11 07:05:28 2018
From: trini at konsulko.com (Tom Rini)
Date: Wed, 11 Apr 2018 10:05:28 -0400
Subject: [U-Boot, v2, u-boot, 1/2] clk: Add get/enable/disable/release
 for a bulk of clocks
In-Reply-To: <1522748659-21622-2-git-send-email-narmstrong@baylibre.com>
References: <1522748659-21622-2-git-send-email-narmstrong@baylibre.com>
Message-ID: <20180411140528.GE10996@bill-the-cat.ec.rr.com>

On Tue, Apr 03, 2018 at 11:44:18AM +0200, Neil Armstrong wrote:

> This patch adds a "bulk" API to the clock API in order to get/enable/disable
> /release a group of clocks associated with a device.
> 
> This bulk API will avoid adding a copy of the same code to manage
> a group of clocks in drivers.
> 
> Signed-off-by: Neil Armstrong <narmstrong at baylibre.com>
> Reviewed-by: Simon Glass <sjg at chromium.org>

Applied to u-boot/master, thanks!

-- 
Tom
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From trini at konsulko.com  Wed Apr 11 07:05:33 2018
From: trini at konsulko.com (Tom Rini)
Date: Wed, 11 Apr 2018 10:05:33 -0400
Subject: [U-Boot,v2,u-boot,2/2] clk: add sandbox test for bulk API
In-Reply-To: <1522748659-21622-3-git-send-email-narmstrong@baylibre.com>
References: <1522748659-21622-3-git-send-email-narmstrong@baylibre.com>
Message-ID: <20180411140533.GF10996@bill-the-cat.ec.rr.com>

On Tue, Apr 03, 2018 at 11:44:19AM +0200, Neil Armstrong wrote:

> This patch adds the bulk clock API tests for the sandbox test suite.
> 
> It's very similar to the main test but only uses the _bulk() API and
> checks if the clocks are correctly enabled/disabled.
> 
> Signed-off-by: Neil Armstrong <narmstrong at baylibre.com>
> Reviewed-by: Simon Glass <sjg at chromium.org>

Applied to u-boot/master, thanks!

-- 
Tom
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From narmstrong at baylibre.com  Wed Apr 11 07:29:06 2018
From: narmstrong at baylibre.com (Neil Armstrong)
Date: Wed, 11 Apr 2018 16:29:06 +0200
Subject: [PATCH v2 u-boot 2/3] usb: host: dwc3: Add support for multiple PHYs
In-Reply-To: <1523456947-4242-1-git-send-email-narmstrong@baylibre.com>
References: <1523456947-4242-1-git-send-email-narmstrong@baylibre.com>
Message-ID: <1523456947-4242-3-git-send-email-narmstrong@baylibre.com>

DWC3 Ips can have more than 1 PHY for USB2 and 1 PHY for USB3, add support
for a generic number of PHYs and adapt the code to handle a generic
number of PHYs.

Signed-off-by: Neil Armstrong <narmstrong at baylibre.com>
---
 drivers/usb/host/xhci-dwc3.c | 113 +++++++++++++++++++++++++------------------
 1 file changed, 66 insertions(+), 47 deletions(-)

diff --git a/drivers/usb/host/xhci-dwc3.c b/drivers/usb/host/xhci-dwc3.c
index 1022dd5..c100735 100644
--- a/drivers/usb/host/xhci-dwc3.c
+++ b/drivers/usb/host/xhci-dwc3.c
@@ -22,8 +22,8 @@
 DECLARE_GLOBAL_DATA_PTR;
 
 struct xhci_dwc3_platdata {
-	struct phy usb_phy;
-	struct phy usb3_phy;
+	struct phy *usb_phys;
+	int num_phys;
 };
 
 void dwc3_set_mode(struct dwc3 *dwc3_reg, u32 mode)
@@ -113,45 +113,82 @@ void dwc3_set_fladj(struct dwc3 *dwc3_reg, u32 val)
 }
 
 #ifdef CONFIG_DM_USB
-static int xhci_dwc3_setup_phy(struct udevice *dev, int index, struct phy *phy)
+static int xhci_dwc3_setup_phy(struct udevice *dev, int count)
 {
-	int ret = 0;
+	struct xhci_dwc3_platdata *plat = dev_get_platdata(dev);
+	int i, ret;
+
+	if (!count)
+		return 0;
 
-	ret = generic_phy_get_by_index(dev, index, phy);
-	if (ret) {
-		if (ret != -ENOENT) {
-			pr_err("Failed to get USB PHY for %s\n", dev->name);
+	plat->usb_phys = devm_kcalloc(dev, count, sizeof(struct phy),
+					GFP_KERNEL);
+	if (!plat->usb_phys)
+		return -ENOMEM;
+
+	for (i = 0; i < count; i++) {
+		ret = generic_phy_get_by_index(dev, i, &plat->usb_phys[i]);
+		if (ret && ret != -ENOENT) {
+			pr_err("Failed to get USB PHY%d for %s\n",
+			       i, dev->name);
 			return ret;
 		}
-	} else {
-		ret = generic_phy_init(phy);
+
+		++plat->num_phys;
+	}
+	
+	for (i = 0; i < plat->num_phys; i++) {
+		ret = generic_phy_init(&plat->usb_phys[i]);
 		if (ret) {
-			pr_err("Can't init USB PHY for %s\n", dev->name);
-			return ret;
+			pr_err("Can't init USB PHY%d for %s\n",
+			       i, dev->name);
+			goto phys_init_err;
 		}
-		ret = generic_phy_power_on(phy);
+	}
+	
+	for (i = 0; i < plat->num_phys; i++) {
+		ret = generic_phy_power_on(&plat->usb_phys[i]);
 		if (ret) {
-			pr_err("Can't power on USB PHY for %s\n", dev->name);
-			generic_phy_exit(phy);
-			return ret;
+			pr_err("Can't power USB PHY%d for %s\n",
+			       i, dev->name);
+			goto phys_poweron_err;
 		}
 	}
 
 	return 0;
+
+
+phys_poweron_err:
+	for (; i >= 0; i--)
+		generic_phy_power_off(&plat->usb_phys[i]);
+
+	for (i = 0; i < plat->num_phys; i++)
+		generic_phy_exit(&plat->usb_phys[i]);
+
+	return ret;
+
+phys_init_err:
+	for (; i >= 0; i--)
+		generic_phy_exit(&plat->usb_phys[i]);
+
+	return ret;
 }
 
-static int xhci_dwc3_shutdown_phy(struct phy *phy)
+static int xhci_dwc3_shutdown_phy(struct udevice *dev)
 {
-	int ret = 0;
+	struct xhci_dwc3_platdata *plat = dev_get_platdata(dev);
+	int i, ret;
 
-	if (generic_phy_valid(phy)) {
-		ret = generic_phy_power_off(phy);
-		if (ret)
-			return ret;
+	for (i = 0; i < plat->num_phys; i++) {
+		if (!generic_phy_valid(&plat->usb_phys[i]))
+			continue;
 
-		ret = generic_phy_exit(phy);
-		if (ret)
-			return ret;
+		ret = generic_phy_power_off(&plat->usb_phys[i]);
+		ret |= generic_phy_exit(&plat->usb_phys[i]);
+		if (ret) {
+			pr_err("Can't shutdown USB PHY%d for %s\n",
+				i, dev->name);
+		}
 	}
 
 	return 0;
@@ -159,7 +196,6 @@ static int xhci_dwc3_shutdown_phy(struct phy *phy)
 
 static int xhci_dwc3_probe(struct udevice *dev)
 {
-	struct xhci_dwc3_platdata *plat = dev_get_platdata(dev);
 	struct xhci_hcor *hcor;
 	struct xhci_hccr *hccr;
 	struct dwc3 *dwc3_reg;
@@ -170,18 +206,10 @@ static int xhci_dwc3_probe(struct udevice *dev)
 	hcor = (struct xhci_hcor *)((uintptr_t)hccr +
 			HC_LENGTH(xhci_readl(&(hccr)->cr_capbase)));
 
-	ret = xhci_dwc3_setup_phy(dev, 0, &plat->usb_phy);
-	if (ret) {
-		pr_err("Failed to setup USB PHY for %s\n", dev->name);
+	ret = xhci_dwc3_setup_phy(dev, dev_count_phandle_with_args(
+						dev, "phys", "#phy-cells"));
+	if (ret)
 		return ret;
-	}
-
-	ret = xhci_dwc3_setup_phy(dev, 1, &plat->usb3_phy);
-	if (ret) {
-		pr_err("Failed to setup USB3 PHY for %s\n", dev->name);
-		xhci_dwc3_shutdown_phy(&plat->usb_phy);
-		return ret;
-	}
 
 	dwc3_reg = (struct dwc3 *)((char *)(hccr) + DWC3_REG_OFFSET);
 
@@ -199,16 +227,7 @@ static int xhci_dwc3_probe(struct udevice *dev)
 
 static int xhci_dwc3_remove(struct udevice *dev)
 {
-	struct xhci_dwc3_platdata *plat = dev_get_platdata(dev);
-	int ret;
-
-	ret = xhci_dwc3_shutdown_phy(&plat->usb_phy);
-	if (ret)
-		pr_err("Can't shutdown USB PHY for %s\n", dev->name);
-
-	ret = xhci_dwc3_shutdown_phy(&plat->usb3_phy);
-	if (ret)
-		pr_err("Can't shutdown USB3 PHY for %s\n", dev->name);
+	xhci_dwc3_shutdown_phy(dev);
 
 	return xhci_deregister(dev);
 }
-- 
2.7.4



From narmstrong at baylibre.com  Wed Apr 11 07:29:04 2018
From: narmstrong at baylibre.com (Neil Armstrong)
Date: Wed, 11 Apr 2018 16:29:04 +0200
Subject: [PATCH v2 u-boot 0/3] Add USB Support for Amlogic Meson GXL SoCs
Message-ID: <1523456947-4242-1-git-send-email-narmstrong@baylibre.com>

This patchset adds support for USB for the Amlogic Meson GXL SoCs following
the work done for Linux by Martin Blumenstingl at [1] [2] [3].

The support consist of :
 - A port of dwc3-of-simple from Linux to U-boot
 - A change to support more than 2 PHYs in the DWC3 DM driver
 - An USB2 PHY Driver and an USB3 PHY Driver

The DWC3 Controller has up to 4 PHYs connected :
 - 2 USB2 PHYs and an USB3 PHY for GXL SoCs
 - 3 USB2 PHYs and an USB3 PHY for the GXM SoC Variant
This is enabled by the "usb: host: dwc3: Add support for multiple PHYs" patch.
This patch is based on the "xhci-dwc3: Couple of fixes for USB3 support"
serie from Vignesh R, on the u-boot-usb tree.

The DWC3 Controller glue is generic enough to use the dwc3-of-simple from Linux
and can be easily ported to U-Boot as a Simple-Bus with Glue-Specific clocks
and Reset lines setup.

This depends on the recently applied :
 - clk: Add get/enable/disable/release for a bulk of clocks at [4]
 - reset: Add get/assert/deassert/release for bulk of reset signals at [5]
in order to manage the clocks and resets of the Glue in a clean fashion.

The USB PHY driver supports the standard generic PHY interface and supports
the power-on/off calls and set the Host mode by default.
They are based on the excellent work from Martin Blumenstingl merged in linux.

Changes since v1:
 - switch to submitted clk/reset bulk API
 - splitted dwc3 multiple phy init error between poweroff & exit

[1] https://lkml.kernel.org/r/20180303184700.21480-1-martin.blumenstingl at googlemail.com
[2] https://lkml.kernel.org/r/20180128202245.25021-1-martin.blumenstingl at googlemail.com
[3] https://lkml.kernel.org/r/20180303214309.25643-1-martin.blumenstingl at googlemail.com
[4] http://lists.infradead.org/pipermail/linux-amlogic/2018-April/006952.html
[5] http://lists.infradead.org/pipermail/linux-amlogic/2018-April/006949.html

Neil Armstrong (3):
  usb: host: Add simple of glue driver for DWC3 USB Controllers
    integration
  usb: host: dwc3: Add support for multiple PHYs
  phy: Add Amlogic Meson USB2 & USB3 Generic PHY drivers

 drivers/phy/Kconfig               |   8 ++
 drivers/phy/Makefile              |   1 +
 drivers/phy/meson-gxl-usb2.c      | 238 ++++++++++++++++++++++++++++++++++++++
 drivers/phy/meson-gxl-usb3.c      | 201 ++++++++++++++++++++++++++++++++
 drivers/usb/host/Kconfig          |   7 ++
 drivers/usb/host/Makefile         |   1 +
 drivers/usb/host/dwc3-of-simple.c | 123 ++++++++++++++++++++
 drivers/usb/host/xhci-dwc3.c      | 113 ++++++++++--------
 8 files changed, 645 insertions(+), 47 deletions(-)
 create mode 100644 drivers/phy/meson-gxl-usb2.c
 create mode 100644 drivers/phy/meson-gxl-usb3.c
 create mode 100644 drivers/usb/host/dwc3-of-simple.c

-- 
2.7.4



From narmstrong at baylibre.com  Wed Apr 11 07:29:05 2018
From: narmstrong at baylibre.com (Neil Armstrong)
Date: Wed, 11 Apr 2018 16:29:05 +0200
Subject: [PATCH v2 u-boot 1/3] usb: host: Add simple of glue driver for DWC3
 USB Controllers integration
In-Reply-To: <1523456947-4242-1-git-send-email-narmstrong@baylibre.com>
References: <1523456947-4242-1-git-send-email-narmstrong@baylibre.com>
Message-ID: <1523456947-4242-2-git-send-email-narmstrong@baylibre.com>

This is a port of the dwc3-of-simple driver from Linux to enable/deassert
clock and resets of a simple DWC3 Controller HW glue.

Signed-off-by: Neil Armstrong <narmstrong at baylibre.com>
---
 drivers/usb/host/Kconfig          |   7 +++
 drivers/usb/host/Makefile         |   1 +
 drivers/usb/host/dwc3-of-simple.c | 123 ++++++++++++++++++++++++++++++++++++++
 3 files changed, 131 insertions(+)
 create mode 100644 drivers/usb/host/dwc3-of-simple.c

diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig
index a7249b7..6caa615 100644
--- a/drivers/usb/host/Kconfig
+++ b/drivers/usb/host/Kconfig
@@ -21,6 +21,13 @@ config USB_XHCI_DWC3
 	  Say Y or if your system has a Dual Role SuperSpeed
 	  USB controller based on the DesignWare USB3 IP Core.
 
+config USB_XHCI_DWC3_OF_SIMPLE
+	bool "DesignWare USB3 DRD Generic OF Simple Glue Layer"
+	select MISC
+	help
+	  Support USB2/3 functionality in simple SoC integrations with
+	  USB controller based on the DesignWare USB3 IP Core.
+
 config USB_XHCI_MVEBU
 	bool "MVEBU USB 3.0 support"
 	default y
diff --git a/drivers/usb/host/Makefile b/drivers/usb/host/Makefile
index 9819489..abe4f90 100644
--- a/drivers/usb/host/Makefile
+++ b/drivers/usb/host/Makefile
@@ -49,6 +49,7 @@ obj-$(CONFIG_USB_EHCI_ZYNQ) += ehci-zynq.o
 # xhci
 obj-$(CONFIG_USB_XHCI_HCD) += xhci.o xhci-mem.o xhci-ring.o
 obj-$(CONFIG_USB_XHCI_DWC3) += xhci-dwc3.o
+obj-$(CONFIG_USB_XHCI_DWC3_OF_SIMPLE) += dwc3-of-simple.o
 obj-$(CONFIG_USB_XHCI_ROCKCHIP) += xhci-rockchip.o
 obj-$(CONFIG_USB_XHCI_ZYNQMP) += xhci-zynqmp.o
 obj-$(CONFIG_USB_XHCI_KEYSTONE) += xhci-keystone.o
diff --git a/drivers/usb/host/dwc3-of-simple.c b/drivers/usb/host/dwc3-of-simple.c
new file mode 100644
index 0000000..9abe450
--- /dev/null
+++ b/drivers/usb/host/dwc3-of-simple.c
@@ -0,0 +1,123 @@
+/*
+ * dwc3-of-simple.c - OF glue layer for simple integrations
+ *
+ * Copyright (c) 2015 Texas Instruments Incorporated - http://www.ti.com
+ *
+ * Author: Felipe Balbi <balbi at ti.com>
+ *
+ * Copyright (C) 2018 BayLibre, SAS
+ * Author: Neil Armstrong <narmstron at baylibre.com>
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <fdtdec.h>
+#include <reset.h>
+#include <clk.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct dwc3_of_simple {
+#if CONFIG_IS_ENABLED(CLK)
+	struct clk_bulk		clks;
+#endif
+#if CONFIG_IS_ENABLED(DM_RESET)
+	struct reset_ctl_bulk	resets;
+#endif
+};
+
+#if CONFIG_IS_ENABLED(DM_RESET)
+static int dwc3_of_simple_reset_init(struct udevice *dev,
+				     struct dwc3_of_simple *simple)
+{
+	int ret;
+
+	ret = reset_get_bulk(dev, &simple->resets);
+	if (ret)
+		return ret;
+
+	ret = reset_deassert_bulk(&simple->resets);
+	if (ret) {
+		reset_release_bulk(&simple->resets);
+		return ret;
+	}
+
+	return 0;
+}
+#endif
+
+#if CONFIG_IS_ENABLED(CLK)
+static int dwc3_of_simple_clk_init(struct udevice *dev,
+				   struct dwc3_of_simple *simple)
+{
+	int ret;
+
+	ret = clk_get_bulk(dev, &simple->clks);
+	if (ret)
+		return ret;
+
+	ret = clk_enable_bulk(&simple->clks);
+	if (ret) {
+		clk_release_bulk(&simple->clks);
+		return ret;
+	}
+
+	return 0;
+}
+#endif
+
+static int dwc3_of_simple_probe(struct udevice *dev)
+{
+#if CONFIG_IS_ENABLED(DM_RESET) || CONFIG_IS_ENABLED(CLK)
+	struct dwc3_of_simple *simple = dev_get_platdata(dev);
+	int ret;
+#endif
+
+#if CONFIG_IS_ENABLED(CLK)
+	ret = dwc3_of_simple_clk_init(dev, simple);
+	if (ret)
+		return ret;
+#endif
+
+#if CONFIG_IS_ENABLED(DM_RESET)
+	ret = dwc3_of_simple_reset_init(dev, simple);
+	if (ret)
+		return ret;
+#endif
+
+	return 0;
+}
+
+static int dwc3_of_simple_remove(struct udevice *dev)
+{
+#if CONFIG_IS_ENABLED(DM_RESET) || CONFIG_IS_ENABLED(CLK)
+	struct dwc3_of_simple *simple = dev_get_platdata(dev);
+#endif
+
+#if CONFIG_IS_ENABLED(DM_RESET)
+	reset_release_bulk(&simple->resets);
+#endif
+
+#if CONFIG_IS_ENABLED(CLK)
+	clk_release_bulk(&simple->clks);
+#endif
+
+	return dm_scan_fdt_dev(dev);
+}
+
+static const struct udevice_id dwc3_of_simple_ids[] = {
+	{ .compatible = "amlogic,meson-gxl-dwc3" },
+	{ }
+};
+
+U_BOOT_DRIVER(dwc3_of_simple) = {
+	.name = "dwc3-of-simple",
+	.id = UCLASS_SIMPLE_BUS,
+	.of_match = dwc3_of_simple_ids,
+	.probe = dwc3_of_simple_probe,
+	.remove = dwc3_of_simple_remove,
+	.platdata_auto_alloc_size = sizeof(struct dwc3_of_simple),
+	.flags = DM_FLAG_ALLOC_PRIV_DMA,
+};
-- 
2.7.4



From narmstrong at baylibre.com  Wed Apr 11 07:29:07 2018
From: narmstrong at baylibre.com (Neil Armstrong)
Date: Wed, 11 Apr 2018 16:29:07 +0200
Subject: [PATCH v2 u-boot 3/3] phy: Add Amlogic Meson USB2 & USB3 Generic PHY
 drivers
In-Reply-To: <1523456947-4242-1-git-send-email-narmstrong@baylibre.com>
References: <1523456947-4242-1-git-send-email-narmstrong@baylibre.com>
Message-ID: <1523456947-4242-4-git-send-email-narmstrong@baylibre.com>

The Amlogic Meson GXL and GXM (simple variant) embeds up to 3 USB2 PHYs
and an USB3 PHY. This patch adds drivers for these for the standard generic
PHY interface and supports the power-on/off calls and set the Host mode by
default.
They are based on the excellent work from Martin Blumenstingl merged in linux.

Signed-off-by: Neil Armstrong <narmstrong at baylibre.com>
---
 drivers/phy/Kconfig          |   8 ++
 drivers/phy/Makefile         |   1 +
 drivers/phy/meson-gxl-usb2.c | 238 +++++++++++++++++++++++++++++++++++++++++++
 drivers/phy/meson-gxl-usb3.c | 201 ++++++++++++++++++++++++++++++++++++
 4 files changed, 448 insertions(+)
 create mode 100644 drivers/phy/meson-gxl-usb2.c
 create mode 100644 drivers/phy/meson-gxl-usb3.c

diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
index 3b9a09c..99a6d95 100644
--- a/drivers/phy/Kconfig
+++ b/drivers/phy/Kconfig
@@ -85,4 +85,12 @@ config STI_USB_PHY
 	  used by USB2 and USB3 Host controllers available on
 	  STiH407 SoC families.
 
+config MESON_GXL_USB_PHY
+	bool "Amlogic Meson GXL USB PHYs"
+	depends on PHY && ARCH_MESON && MESON_GXL
+	imply REGMAP
+	help
+	  This is the generic phy driver for the Amlogic Meson GXL
+	  USB2 and USB3 PHYS.
+
 endmenu
diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
index 668040b..6c1610e 100644
--- a/drivers/phy/Makefile
+++ b/drivers/phy/Makefile
@@ -10,3 +10,4 @@ obj-$(CONFIG_$(SPL_)NOP_PHY) += nop-phy.o
 obj-$(CONFIG_PHY_SANDBOX) += sandbox-phy.o
 obj-$(CONFIG_$(SPL_)PIPE3_PHY) += ti-pipe3-phy.o
 obj-$(CONFIG_STI_USB_PHY) += sti_usb_phy.o
+obj-$(CONFIG_MESON_GXL_USB_PHY) += meson-gxl-usb2.o meson-gxl-usb3.o
diff --git a/drivers/phy/meson-gxl-usb2.c b/drivers/phy/meson-gxl-usb2.c
new file mode 100644
index 0000000..15c9c89
--- /dev/null
+++ b/drivers/phy/meson-gxl-usb2.c
@@ -0,0 +1,238 @@
+/*
+ * Meson GXL and GXM USB2 PHY driver
+ *
+ * Copyright (C) 2017 Martin Blumenstingl <martin.blumenstingl at googlemail.com>
+ * Copyright (C) 2018 BayLibre, SAS
+ * Author: Neil Armstrong <narmstron at baylibre.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <bitfield.h>
+#include <dm.h>
+#include <errno.h>
+#include <generic-phy.h>
+#include <regmap.h>
+#include <power/regulator.h>
+#include <clk.h>
+
+#include <linux/bitops.h>
+#include <linux/compat.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* bits [31:27] are read-only */
+#define U2P_R0							0x0
+	#define U2P_R0_BYPASS_SEL				BIT(0)
+	#define U2P_R0_BYPASS_DM_EN				BIT(1)
+	#define U2P_R0_BYPASS_DP_EN				BIT(2)
+	#define U2P_R0_TXBITSTUFF_ENH				BIT(3)
+	#define U2P_R0_TXBITSTUFF_EN				BIT(4)
+	#define U2P_R0_DM_PULLDOWN				BIT(5)
+	#define U2P_R0_DP_PULLDOWN				BIT(6)
+	#define U2P_R0_DP_VBUS_VLD_EXT_SEL			BIT(7)
+	#define U2P_R0_DP_VBUS_VLD_EXT				BIT(8)
+	#define U2P_R0_ADP_PRB_EN				BIT(9)
+	#define U2P_R0_ADP_DISCHARGE				BIT(10)
+	#define U2P_R0_ADP_CHARGE				BIT(11)
+	#define U2P_R0_DRV_VBUS					BIT(12)
+	#define U2P_R0_ID_PULLUP				BIT(13)
+	#define U2P_R0_LOOPBACK_EN_B				BIT(14)
+	#define U2P_R0_OTG_DISABLE				BIT(15)
+	#define U2P_R0_COMMON_ONN				BIT(16)
+	#define U2P_R0_FSEL_MASK				GENMASK(19, 17)
+	#define U2P_R0_REF_CLK_SEL_MASK				GENMASK(21, 20)
+	#define U2P_R0_POWER_ON_RESET				BIT(22)
+	#define U2P_R0_V_ATE_TEST_EN_B_MASK			GENMASK(24, 23)
+	#define U2P_R0_ID_SET_ID_DQ				BIT(25)
+	#define U2P_R0_ATE_RESET				BIT(26)
+	#define U2P_R0_FSV_MINUS				BIT(27)
+	#define U2P_R0_FSV_PLUS					BIT(28)
+	#define U2P_R0_BYPASS_DM_DATA				BIT(29)
+	#define U2P_R0_BYPASS_DP_DATA				BIT(30)
+
+#define U2P_R1							0x4
+	#define U2P_R1_BURN_IN_TEST				BIT(0)
+	#define U2P_R1_ACA_ENABLE				BIT(1)
+	#define U2P_R1_DCD_ENABLE				BIT(2)
+	#define U2P_R1_VDAT_SRC_EN_B				BIT(3)
+	#define U2P_R1_VDAT_DET_EN_B				BIT(4)
+	#define U2P_R1_CHARGES_SEL				BIT(5)
+	#define U2P_R1_TX_PREEMP_PULSE_TUNE			BIT(6)
+	#define U2P_R1_TX_PREEMP_AMP_TUNE_MASK			GENMASK(8, 7)
+	#define U2P_R1_TX_RES_TUNE_MASK				GENMASK(10, 9)
+	#define U2P_R1_TX_RISE_TUNE_MASK			GENMASK(12, 11)
+	#define U2P_R1_TX_VREF_TUNE_MASK			GENMASK(16, 13)
+	#define U2P_R1_TX_FSLS_TUNE_MASK			GENMASK(20, 17)
+	#define U2P_R1_TX_HSXV_TUNE_MASK			GENMASK(22, 21)
+	#define U2P_R1_OTG_TUNE_MASK				GENMASK(25, 23)
+	#define U2P_R1_SQRX_TUNE_MASK				GENMASK(28, 26)
+	#define U2P_R1_COMP_DIS_TUNE_MASK			GENMASK(31, 29)
+
+/* bits [31:14] are read-only */
+#define U2P_R2							0x8
+	#define U2P_R2_TESTDATA_IN_MASK				GENMASK(7, 0)
+	#define U2P_R2_TESTADDR_MASK				GENMASK(11, 8)
+	#define U2P_R2_TESTDATA_OUT_SEL				BIT(12)
+	#define U2P_R2_TESTCLK					BIT(13)
+	#define U2P_R2_TESTDATA_OUT_MASK			GENMASK(17, 14)
+	#define U2P_R2_ACA_PIN_RANGE_C				BIT(18)
+	#define U2P_R2_ACA_PIN_RANGE_B				BIT(19)
+	#define U2P_R2_ACA_PIN_RANGE_A				BIT(20)
+	#define U2P_R2_ACA_PIN_GND				BIT(21)
+	#define U2P_R2_ACA_PIN_FLOAT				BIT(22)
+	#define U2P_R2_CHARGE_DETECT				BIT(23)
+	#define U2P_R2_DEVICE_SESSION_VALID			BIT(24)
+	#define U2P_R2_ADP_PROBE				BIT(25)
+	#define U2P_R2_ADP_SENSE				BIT(26)
+	#define U2P_R2_SESSION_END				BIT(27)
+	#define U2P_R2_VBUS_VALID				BIT(28)
+	#define U2P_R2_B_VALID					BIT(29)
+	#define U2P_R2_A_VALID					BIT(30)
+	#define U2P_R2_ID_DIG					BIT(31)
+
+#define U2P_R3							0xc
+
+#define RESET_COMPLETE_TIME				500
+
+struct phy_meson_gxl_usb2_priv {
+	struct regmap		*regmap;
+#if CONFIG_IS_ENABLED(DM_REGULATOR)
+	struct udevice		*phy_supply;
+#endif
+#if CONFIG_IS_ENABLED(CLK)
+	struct clk		clk;
+#endif
+};
+
+static void phy_meson_gxl_usb2_reset(struct phy_meson_gxl_usb2_priv *priv)
+{
+	uint val;
+
+	regmap_read(priv->regmap, U2P_R0, &val);
+
+	/* reset the PHY and wait until settings are stabilized */
+	val |= U2P_R0_POWER_ON_RESET;
+	regmap_write(priv->regmap, U2P_R0, val);
+	udelay(RESET_COMPLETE_TIME);
+
+	val &= ~U2P_R0_POWER_ON_RESET;
+	regmap_write(priv->regmap, U2P_R0, val);
+	udelay(RESET_COMPLETE_TIME);
+}
+
+static void
+phy_meson_gxl_usb2_set_host_mode(struct phy_meson_gxl_usb2_priv *priv)
+{
+	uint val;
+
+	regmap_read(priv->regmap, U2P_R0, &val);
+	val |= U2P_R0_DM_PULLDOWN;
+	val |= U2P_R0_DP_PULLDOWN;
+	val &= ~U2P_R0_ID_PULLUP;
+	regmap_write(priv->regmap, U2P_R0, val);
+
+	phy_meson_gxl_usb2_reset(priv);
+}
+
+static int phy_meson_gxl_usb2_power_on(struct phy *phy)
+{
+	struct udevice *dev = phy->dev;
+	struct phy_meson_gxl_usb2_priv *priv = dev_get_priv(dev);
+	uint val;
+
+	regmap_read(priv->regmap, U2P_R0, &val);
+	/* power on the PHY by taking it out of reset mode */
+	val &= ~U2P_R0_POWER_ON_RESET;
+	regmap_write(priv->regmap, U2P_R0, val);
+
+	phy_meson_gxl_usb2_set_host_mode(priv);
+
+#if CONFIG_IS_ENABLED(DM_REGULATOR)
+	if (priv->phy_supply) {
+		int ret = regulator_set_enable(priv->phy_supply, true);
+		if (ret)
+			return ret;
+	}
+#endif
+
+	return 0;
+}
+
+static int phy_meson_gxl_usb2_power_off(struct phy *phy)
+{
+	struct udevice *dev = phy->dev;
+	struct phy_meson_gxl_usb2_priv *priv = dev_get_priv(dev);
+	uint val;
+
+	regmap_read(priv->regmap, U2P_R0, &val);
+	/* power off the PHY by putting it into reset mode */
+	val |= U2P_R0_POWER_ON_RESET;
+	regmap_write(priv->regmap, U2P_R0, val);
+
+#if CONFIG_IS_ENABLED(DM_REGULATOR)
+	if (priv->phy_supply) {
+		int ret = regulator_set_enable(priv->phy_supply, false);
+		if (ret) {
+			pr_err("Error disabling PHY supply\n");
+			return ret;
+		}
+	}
+#endif
+
+	return 0;
+}
+
+struct phy_ops meson_gxl_usb2_phy_ops = {
+	.power_on = phy_meson_gxl_usb2_power_on,
+	.power_off = phy_meson_gxl_usb2_power_off,
+};
+
+int meson_gxl_usb2_phy_probe(struct udevice *dev)
+{
+	struct phy_meson_gxl_usb2_priv *priv = dev_get_priv(dev);
+	int ret;
+
+	ret = regmap_init_mem(dev, &priv->regmap);
+	if (ret)
+		return ret;
+
+#if CONFIG_IS_ENABLED(CLK)
+	ret = clk_get_by_index(dev, 0, &priv->clk);
+	if (ret < 0)
+		return ret;
+
+	ret = clk_enable(&priv->clk);
+	if (ret && ret != -ENOSYS && ret != -ENOTSUPP) {
+		pr_err("failed to enable PHY clock\n");
+		clk_free(&priv->clk);
+		return ret;
+	}
+#endif
+
+#if CONFIG_IS_ENABLED(DM_REGULATOR)
+	ret = device_get_supply_regulator(dev, "phy-supply", &priv->phy_supply);
+	if (ret && ret != -ENOENT) {
+		pr_err("Failed to get PHY regulator\n");
+		return ret;
+	}
+#endif
+
+	return 0;
+}
+
+static const struct udevice_id meson_gxl_usb2_phy_ids[] = {
+	{ .compatible = "amlogic,meson-gxl-usb2-phy" },
+	{ }
+};
+
+U_BOOT_DRIVER(meson_gxl_usb2_phy) = {
+	.name = "meson_gxl_usb2_phy",
+	.id = UCLASS_PHY,
+	.of_match = meson_gxl_usb2_phy_ids,
+	.probe = meson_gxl_usb2_phy_probe,
+	.ops = &meson_gxl_usb2_phy_ops,
+	.priv_auto_alloc_size = sizeof(struct phy_meson_gxl_usb2_priv),
+};
diff --git a/drivers/phy/meson-gxl-usb3.c b/drivers/phy/meson-gxl-usb3.c
new file mode 100644
index 0000000..a385fbd
--- /dev/null
+++ b/drivers/phy/meson-gxl-usb3.c
@@ -0,0 +1,201 @@
+/*
+ * Meson GXL USB3 PHY driver
+ *
+ * Copyright (C) 2018 Martin Blumenstingl <martin.blumenstingl at googlemail.com>
+ * Copyright (C) 2018 BayLibre, SAS
+ * Author: Neil Armstrong <narmstron at baylibre.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <bitfield.h>
+#include <dm.h>
+#include <errno.h>
+#include <generic-phy.h>
+#include <regmap.h>
+#include <clk.h>
+
+#include <linux/bitops.h>
+#include <linux/compat.h>
+#include <linux/bitfield.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define USB_R0							0x00
+	#define USB_R0_P30_FSEL_MASK				GENMASK(5, 0)
+	#define USB_R0_P30_PHY_RESET				BIT(6)
+	#define USB_R0_P30_TEST_POWERDOWN_HSP			BIT(7)
+	#define USB_R0_P30_TEST_POWERDOWN_SSP			BIT(8)
+	#define USB_R0_P30_ACJT_LEVEL_MASK			GENMASK(13, 9)
+	#define USB_R0_P30_TX_BOOST_LEVEL_MASK			GENMASK(16, 14)
+	#define USB_R0_P30_LANE0_TX2RX_LOOPBACK			BIT(17)
+	#define USB_R0_P30_LANE0_EXT_PCLK_REQ			BIT(18)
+	#define USB_R0_P30_PCS_RX_LOS_MASK_VAL_MASK		GENMASK(28, 19)
+	#define USB_R0_U2D_SS_SCALEDOWN_MODE_MASK		GENMASK(30, 29)
+	#define USB_R0_U2D_ACT					BIT(31)
+
+#define USB_R1							0x04
+	#define USB_R1_U3H_BIGENDIAN_GS				BIT(0)
+	#define USB_R1_U3H_PME_ENABLE				BIT(1)
+	#define USB_R1_U3H_HUB_PORT_OVERCURRENT_MASK		GENMASK(6, 2)
+	#define USB_R1_U3H_HUB_PORT_PERM_ATTACH_MASK		GENMASK(11, 7)
+	#define USB_R1_U3H_HOST_U2_PORT_DISABLE_MASK		GENMASK(15, 12)
+	#define USB_R1_U3H_HOST_U3_PORT_DISABLE			BIT(16)
+	#define USB_R1_U3H_HOST_PORT_POWER_CONTROL_PRESENT	BIT(17)
+	#define USB_R1_U3H_HOST_MSI_ENABLE			BIT(18)
+	#define USB_R1_U3H_FLADJ_30MHZ_REG_MASK			GENMASK(24, 19)
+	#define USB_R1_P30_PCS_TX_SWING_FULL_MASK		GENMASK(31, 25)
+
+#define USB_R2							0x08
+	#define USB_R2_P30_CR_DATA_IN_MASK			GENMASK(15, 0)
+	#define USB_R2_P30_CR_READ				BIT(16)
+	#define USB_R2_P30_CR_WRITE				BIT(17)
+	#define USB_R2_P30_CR_CAP_ADDR				BIT(18)
+	#define USB_R2_P30_CR_CAP_DATA				BIT(19)
+	#define USB_R2_P30_PCS_TX_DEEMPH_3P5DB_MASK		GENMASK(25, 20)
+	#define USB_R2_P30_PCS_TX_DEEMPH_6DB_MASK		GENMASK(31, 26)
+
+#define USB_R3							0x0c
+	#define USB_R3_P30_SSC_ENABLE				BIT(0)
+	#define USB_R3_P30_SSC_RANGE_MASK			GENMASK(3, 1)
+	#define USB_R3_P30_SSC_REF_CLK_SEL_MASK			GENMASK(12, 4)
+	#define USB_R3_P30_REF_SSP_EN				BIT(13)
+	#define USB_R3_P30_LOS_BIAS_MASK			GENMASK(18, 16)
+	#define USB_R3_P30_LOS_LEVEL_MASK			GENMASK(23, 19)
+	#define USB_R3_P30_MPLL_MULTIPLIER_MASK			GENMASK(30, 24)
+
+#define USB_R4							0x10
+	#define USB_R4_P21_PORT_RESET_0				BIT(0)
+	#define USB_R4_P21_SLEEP_M0				BIT(1)
+	#define USB_R4_MEM_PD_MASK				GENMASK(3, 2)
+	#define USB_R4_P21_ONLY					BIT(4)
+
+#define USB_R5							0x14
+	#define USB_R5_ID_DIG_SYNC				BIT(0)
+	#define USB_R5_ID_DIG_REG				BIT(1)
+	#define USB_R5_ID_DIG_CFG_MASK				GENMASK(3, 2)
+	#define USB_R5_ID_DIG_EN_0				BIT(4)
+	#define USB_R5_ID_DIG_EN_1				BIT(5)
+	#define USB_R5_ID_DIG_CURR				BIT(6)
+	#define USB_R5_ID_DIG_IRQ				BIT(7)
+	#define USB_R5_ID_DIG_TH_MASK				GENMASK(15, 8)
+	#define USB_R5_ID_DIG_CNT_MASK				GENMASK(23, 16)
+
+/* read-only register */
+#define USB_R6							0x18
+	#define USB_R6_P30_CR_DATA_OUT_MASK			GENMASK(15, 0)
+	#define USB_R6_P30_CR_ACK				BIT(16)
+
+struct phy_meson_gxl_usb3_priv {
+	struct regmap		*regmap;
+#if CONFIG_IS_ENABLED(CLK)
+	struct clk		clk;
+#endif
+};
+
+static int
+phy_meson_gxl_usb3_set_host_mode(struct phy_meson_gxl_usb3_priv *priv)
+{
+	uint val;
+
+	regmap_read(priv->regmap, USB_R0, &val);
+	val &= ~USB_R0_U2D_ACT;
+	regmap_write(priv->regmap, USB_R0, val);
+
+	regmap_read(priv->regmap, USB_R4, &val);
+	val &= ~USB_R4_P21_SLEEP_M0;
+	regmap_write(priv->regmap, USB_R4, val);
+
+	return 0;
+}
+
+static int phy_meson_gxl_usb3_power_on(struct phy *phy)
+{
+	struct udevice *dev = phy->dev;
+	struct phy_meson_gxl_usb3_priv *priv = dev_get_priv(dev);
+	uint val;
+
+	regmap_read(priv->regmap, USB_R5, &val);
+	val |= USB_R5_ID_DIG_EN_0;
+	val |= USB_R5_ID_DIG_EN_1;
+	val &= ~USB_R5_ID_DIG_TH_MASK;
+	val |= FIELD_PREP(USB_R5_ID_DIG_TH_MASK, 0xff);
+	regmap_write(priv->regmap, USB_R5, val);
+
+	return phy_meson_gxl_usb3_set_host_mode(priv);
+}
+
+static int phy_meson_gxl_usb3_power_off(struct phy *phy)
+{
+	struct udevice *dev = phy->dev;
+	struct phy_meson_gxl_usb3_priv *priv = dev_get_priv(dev);
+	uint val;
+
+	regmap_read(priv->regmap, USB_R5, &val);
+	val &= ~USB_R5_ID_DIG_EN_0;
+	val &= ~USB_R5_ID_DIG_EN_1;
+	regmap_write(priv->regmap, USB_R5, val);
+
+	return 0;
+}
+
+static int phy_meson_gxl_usb3_init(struct phy *phy)
+{
+	struct udevice *dev = phy->dev;
+	struct phy_meson_gxl_usb3_priv *priv = dev_get_priv(dev);
+	uint val;
+
+	regmap_read(priv->regmap, USB_R1, &val);
+	val &= ~USB_R1_U3H_FLADJ_30MHZ_REG_MASK;
+	val |= FIELD_PREP(USB_R1_U3H_FLADJ_30MHZ_REG_MASK, 0x20);
+	regmap_write(priv->regmap, USB_R1, val);
+
+	return 0;
+}
+
+struct phy_ops meson_gxl_usb3_phy_ops = {
+	.init = phy_meson_gxl_usb3_init,
+	.power_on = phy_meson_gxl_usb3_power_on,
+	.power_off = phy_meson_gxl_usb3_power_off,
+};
+
+int meson_gxl_usb3_phy_probe(struct udevice *dev)
+{
+	struct phy_meson_gxl_usb3_priv *priv = dev_get_priv(dev);
+	int ret;
+
+	ret = regmap_init_mem(dev, &priv->regmap);
+	if (ret)
+		return ret;
+	
+#if CONFIG_IS_ENABLED(CLK)
+	ret = clk_get_by_index(dev, 0, &priv->clk);
+	if (ret < 0)
+		return ret;
+
+	ret = clk_enable(&priv->clk);
+	if (ret && ret != -ENOSYS && ret != -ENOTSUPP) {
+		pr_err("failed to enable PHY clock\n");
+		clk_free(&priv->clk);
+		return ret;
+	}
+#endif
+
+	return 0;
+}
+
+static const struct udevice_id meson_gxl_usb3_phy_ids[] = {
+	{ .compatible = "amlogic,meson-gxl-usb3-phy" },
+	{ }
+};
+
+U_BOOT_DRIVER(meson_gxl_usb3_phy) = {
+	.name = "meson_gxl_usb3_phy",
+	.id = UCLASS_PHY,
+	.of_match = meson_gxl_usb3_phy_ids,
+	.probe = meson_gxl_usb3_phy_probe,
+	.ops = &meson_gxl_usb3_phy_ops,
+	.priv_auto_alloc_size = sizeof(struct phy_meson_gxl_usb3_priv),
+};
-- 
2.7.4



From narmstrong at baylibre.com  Wed Apr 11 07:39:08 2018
From: narmstrong at baylibre.com (Neil Armstrong)
Date: Wed, 11 Apr 2018 16:39:08 +0200
Subject: [U-Boot] [PATCH 1/1] mmc: avoid division by zero in
 meson_mmc_config_clock - Please, consider for v2018.05-rc2
In-Reply-To: <09934d93-81d3-077e-6b1d-95ecd30e90e1@gmx.de>
References: <20180317224936.2040-1-xypron.glpk@gmx.de>
 <87muz6i716.fsf@aikidev.net> <c2793855-dd0e-343f-7a81-a318a6cee97c@gmx.de>
 <09934d93-81d3-077e-6b1d-95ecd30e90e1@gmx.de>
Message-ID: <e3f276ba-586f-5435-0447-3e00efba5411@baylibre.com>

Hi Jaehoon,

On 10/04/2018 18:01, Heinrich Schuchardt wrote:
> On 03/24/2018 03:57 PM, Heinrich Schuchardt wrote:
>> On 03/18/2018 01:03 AM, Vagrant Cascadian wrote:
>>> On 2018-03-17, Heinrich Schuchardt wrote:
>>>> The Odroid C2 fails to read from mmc with U-Boot v2018.03.
>>>> The change avoids a division by zero.
>>>>
>>>> The fix was suggested by Jaehoon in
>>>> https://lists.denx.de/pipermail/u-boot/2018-January/318577.html
>>>
>>> Thanks!
>>>
>>> Works for me with odroid-c2 on u-boot 2018.03.
>>>
>>> Without the patch, mmc access immediately hangs the board.
>>>
>>> Tested-by: Vagrant Cascadian <vagrant at debian.org>
>>>
>>>
>>> live well,
>>>   vagrant
>>>
>>>> Reported-by: Vagrant Cascadian <vagrant at debian.org>
>>>> Suggested-by: Jaehoon Chung <jh80.chung at samsung.com>
>>>> Signed-off-by: Heinrich Schuchardt <xypron.glpk at gmx.de>
>>>> ---
[...]
>>>> -- 
>>>> 2.14.2
>>
>> Hello Jaehoon,
>>
>> will you pick the patch?
>>
>> Best regards
>>
>> Heinrich
>>
> 
> Hello Jaehoon,
> 
> since v2018.03 the Odroid C2 cannot be booted with U-Boot. This patch
> fixes it and has been adopted by Debian:
> https://packages.debian.org/de/buster/u-boot
> 
> Could you, please, consider it for v2018.05-rc2.
> 
> Best regards
> 
> Heinrich
> 
It also affects the other Amlogic platforms : P212, LibreTech-CC and Khadas-Vim, thus 2018.03 is broken for these platforms.

Thanks,
Neil


From marex at denx.de  Wed Apr 11 07:37:30 2018
From: marex at denx.de (Marek Vasut)
Date: Wed, 11 Apr 2018 16:37:30 +0200
Subject: [PATCH v2 u-boot 1/3] usb: host: Add simple of glue driver for
 DWC3 USB Controllers integration
In-Reply-To: <1523456947-4242-2-git-send-email-narmstrong@baylibre.com>
References: <1523456947-4242-1-git-send-email-narmstrong@baylibre.com>
 <1523456947-4242-2-git-send-email-narmstrong@baylibre.com>
Message-ID: <f073d38e-1196-6bd6-0081-fcf4f87c7fd6@denx.de>

On 04/11/2018 04:29 PM, Neil Armstrong wrote:
> This is a port of the dwc3-of-simple driver from Linux to enable/deassert
> clock and resets of a simple DWC3 Controller HW glue.
> 
> Signed-off-by: Neil Armstrong <narmstrong at baylibre.com>

Looks good, except can we reduce the number of ifdefs, ie. by using
empty functions if DM_* is not defined ?

> ---
>  drivers/usb/host/Kconfig          |   7 +++
>  drivers/usb/host/Makefile         |   1 +
>  drivers/usb/host/dwc3-of-simple.c | 123 ++++++++++++++++++++++++++++++++++++++
>  3 files changed, 131 insertions(+)
>  create mode 100644 drivers/usb/host/dwc3-of-simple.c
> 
> diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig
> index a7249b7..6caa615 100644
> --- a/drivers/usb/host/Kconfig
> +++ b/drivers/usb/host/Kconfig
> @@ -21,6 +21,13 @@ config USB_XHCI_DWC3
>  	  Say Y or if your system has a Dual Role SuperSpeed
>  	  USB controller based on the DesignWare USB3 IP Core.
>  
> +config USB_XHCI_DWC3_OF_SIMPLE
> +	bool "DesignWare USB3 DRD Generic OF Simple Glue Layer"
> +	select MISC
> +	help
> +	  Support USB2/3 functionality in simple SoC integrations with
> +	  USB controller based on the DesignWare USB3 IP Core.
> +
>  config USB_XHCI_MVEBU
>  	bool "MVEBU USB 3.0 support"
>  	default y
> diff --git a/drivers/usb/host/Makefile b/drivers/usb/host/Makefile
> index 9819489..abe4f90 100644
> --- a/drivers/usb/host/Makefile
> +++ b/drivers/usb/host/Makefile
> @@ -49,6 +49,7 @@ obj-$(CONFIG_USB_EHCI_ZYNQ) += ehci-zynq.o
>  # xhci
>  obj-$(CONFIG_USB_XHCI_HCD) += xhci.o xhci-mem.o xhci-ring.o
>  obj-$(CONFIG_USB_XHCI_DWC3) += xhci-dwc3.o
> +obj-$(CONFIG_USB_XHCI_DWC3_OF_SIMPLE) += dwc3-of-simple.o
>  obj-$(CONFIG_USB_XHCI_ROCKCHIP) += xhci-rockchip.o
>  obj-$(CONFIG_USB_XHCI_ZYNQMP) += xhci-zynqmp.o
>  obj-$(CONFIG_USB_XHCI_KEYSTONE) += xhci-keystone.o
> diff --git a/drivers/usb/host/dwc3-of-simple.c b/drivers/usb/host/dwc3-of-simple.c
> new file mode 100644
> index 0000000..9abe450
> --- /dev/null
> +++ b/drivers/usb/host/dwc3-of-simple.c
> @@ -0,0 +1,123 @@
> +/*
> + * dwc3-of-simple.c - OF glue layer for simple integrations
> + *
> + * Copyright (c) 2015 Texas Instruments Incorporated - http://www.ti.com
> + *
> + * Author: Felipe Balbi <balbi at ti.com>
> + *
> + * Copyright (C) 2018 BayLibre, SAS
> + * Author: Neil Armstrong <narmstron at baylibre.com>
> + *
> + * SPDX-License-Identifier:     GPL-2.0+
> + */
> +
> +#include <common.h>
> +#include <dm.h>
> +#include <fdtdec.h>
> +#include <reset.h>
> +#include <clk.h>
> +
> +DECLARE_GLOBAL_DATA_PTR;
> +
> +struct dwc3_of_simple {
> +#if CONFIG_IS_ENABLED(CLK)
> +	struct clk_bulk		clks;
> +#endif
> +#if CONFIG_IS_ENABLED(DM_RESET)
> +	struct reset_ctl_bulk	resets;
> +#endif
> +};
> +
> +#if CONFIG_IS_ENABLED(DM_RESET)
> +static int dwc3_of_simple_reset_init(struct udevice *dev,
> +				     struct dwc3_of_simple *simple)
> +{
> +	int ret;
> +
> +	ret = reset_get_bulk(dev, &simple->resets);
> +	if (ret)
> +		return ret;
> +
> +	ret = reset_deassert_bulk(&simple->resets);
> +	if (ret) {
> +		reset_release_bulk(&simple->resets);
> +		return ret;
> +	}
> +
> +	return 0;
> +}
> +#endif
> +
> +#if CONFIG_IS_ENABLED(CLK)
> +static int dwc3_of_simple_clk_init(struct udevice *dev,
> +				   struct dwc3_of_simple *simple)
> +{
> +	int ret;
> +
> +	ret = clk_get_bulk(dev, &simple->clks);
> +	if (ret)
> +		return ret;
> +
> +	ret = clk_enable_bulk(&simple->clks);
> +	if (ret) {
> +		clk_release_bulk(&simple->clks);
> +		return ret;
> +	}
> +
> +	return 0;
> +}
> +#endif
> +
> +static int dwc3_of_simple_probe(struct udevice *dev)
> +{
> +#if CONFIG_IS_ENABLED(DM_RESET) || CONFIG_IS_ENABLED(CLK)
> +	struct dwc3_of_simple *simple = dev_get_platdata(dev);
> +	int ret;
> +#endif
> +
> +#if CONFIG_IS_ENABLED(CLK)
> +	ret = dwc3_of_simple_clk_init(dev, simple);
> +	if (ret)
> +		return ret;
> +#endif
> +
> +#if CONFIG_IS_ENABLED(DM_RESET)
> +	ret = dwc3_of_simple_reset_init(dev, simple);
> +	if (ret)
> +		return ret;
> +#endif
> +
> +	return 0;
> +}
> +
> +static int dwc3_of_simple_remove(struct udevice *dev)
> +{
> +#if CONFIG_IS_ENABLED(DM_RESET) || CONFIG_IS_ENABLED(CLK)
> +	struct dwc3_of_simple *simple = dev_get_platdata(dev);
> +#endif
> +
> +#if CONFIG_IS_ENABLED(DM_RESET)
> +	reset_release_bulk(&simple->resets);
> +#endif
> +
> +#if CONFIG_IS_ENABLED(CLK)
> +	clk_release_bulk(&simple->clks);
> +#endif
> +
> +	return dm_scan_fdt_dev(dev);
> +}
> +
> +static const struct udevice_id dwc3_of_simple_ids[] = {
> +	{ .compatible = "amlogic,meson-gxl-dwc3" },
> +	{ }
> +};
> +
> +U_BOOT_DRIVER(dwc3_of_simple) = {
> +	.name = "dwc3-of-simple",
> +	.id = UCLASS_SIMPLE_BUS,
> +	.of_match = dwc3_of_simple_ids,
> +	.probe = dwc3_of_simple_probe,
> +	.remove = dwc3_of_simple_remove,
> +	.platdata_auto_alloc_size = sizeof(struct dwc3_of_simple),
> +	.flags = DM_FLAG_ALLOC_PRIV_DMA,
> +};
> 


-- 
Best regards,
Marek Vasut


From narmstrong at baylibre.com  Wed Apr 11 07:53:34 2018
From: narmstrong at baylibre.com (Neil Armstrong)
Date: Wed, 11 Apr 2018 16:53:34 +0200
Subject: [PATCH v2 u-boot 1/3] usb: host: Add simple of glue driver for
 DWC3 USB Controllers integration
In-Reply-To: <f073d38e-1196-6bd6-0081-fcf4f87c7fd6@denx.de>
References: <1523456947-4242-1-git-send-email-narmstrong@baylibre.com>
 <1523456947-4242-2-git-send-email-narmstrong@baylibre.com>
 <f073d38e-1196-6bd6-0081-fcf4f87c7fd6@denx.de>
Message-ID: <b4c270c1-201d-70b6-8a34-d458e211bb25@baylibre.com>

Hi Marek,

On 11/04/2018 16:37, Marek Vasut wrote:
> On 04/11/2018 04:29 PM, Neil Armstrong wrote:
>> This is a port of the dwc3-of-simple driver from Linux to enable/deassert
>> clock and resets of a simple DWC3 Controller HW glue.
>>
>> Signed-off-by: Neil Armstrong <narmstrong at baylibre.com>
> 
> Looks good, except can we reduce the number of ifdefs, ie. by using
> empty functions if DM_* is not defined ?

For reset, yes, for clock only the get_bulk and release_bulk...

Should I re-spin ?

Neil
> 
>> ---
>>  drivers/usb/host/Kconfig          |   7 +++
>>  drivers/usb/host/Makefile         |   1 +
>>  drivers/usb/host/dwc3-of-simple.c | 123 ++++++++++++++++++++++++++++++++++++++
>>  3 files changed, 131 insertions(+)
>>  create mode 100644 drivers/usb/host/dwc3-of-simple.c
>>
>> diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig
>> index a7249b7..6caa615 100644
>> --- a/drivers/usb/host/Kconfig
>> +++ b/drivers/usb/host/Kconfig
>> @@ -21,6 +21,13 @@ config USB_XHCI_DWC3
>>  	  Say Y or if your system has a Dual Role SuperSpeed
>>  	  USB controller based on the DesignWare USB3 IP Core.
>>  
>> +config USB_XHCI_DWC3_OF_SIMPLE
>> +	bool "DesignWare USB3 DRD Generic OF Simple Glue Layer"
>> +	select MISC
>> +	help
>> +	  Support USB2/3 functionality in simple SoC integrations with
>> +	  USB controller based on the DesignWare USB3 IP Core.
>> +
>>  config USB_XHCI_MVEBU
>>  	bool "MVEBU USB 3.0 support"
>>  	default y
>> diff --git a/drivers/usb/host/Makefile b/drivers/usb/host/Makefile
>> index 9819489..abe4f90 100644
>> --- a/drivers/usb/host/Makefile
>> +++ b/drivers/usb/host/Makefile
>> @@ -49,6 +49,7 @@ obj-$(CONFIG_USB_EHCI_ZYNQ) += ehci-zynq.o
>>  # xhci
>>  obj-$(CONFIG_USB_XHCI_HCD) += xhci.o xhci-mem.o xhci-ring.o
>>  obj-$(CONFIG_USB_XHCI_DWC3) += xhci-dwc3.o
>> +obj-$(CONFIG_USB_XHCI_DWC3_OF_SIMPLE) += dwc3-of-simple.o
>>  obj-$(CONFIG_USB_XHCI_ROCKCHIP) += xhci-rockchip.o
>>  obj-$(CONFIG_USB_XHCI_ZYNQMP) += xhci-zynqmp.o
>>  obj-$(CONFIG_USB_XHCI_KEYSTONE) += xhci-keystone.o
>> diff --git a/drivers/usb/host/dwc3-of-simple.c b/drivers/usb/host/dwc3-of-simple.c
>> new file mode 100644
>> index 0000000..9abe450
>> --- /dev/null
>> +++ b/drivers/usb/host/dwc3-of-simple.c
>> @@ -0,0 +1,123 @@
>> +/*
>> + * dwc3-of-simple.c - OF glue layer for simple integrations
>> + *
>> + * Copyright (c) 2015 Texas Instruments Incorporated - http://www.ti.com
>> + *
>> + * Author: Felipe Balbi <balbi at ti.com>
>> + *
>> + * Copyright (C) 2018 BayLibre, SAS
>> + * Author: Neil Armstrong <narmstron at baylibre.com>
>> + *
>> + * SPDX-License-Identifier:     GPL-2.0+
>> + */
>> +
>> +#include <common.h>
>> +#include <dm.h>
>> +#include <fdtdec.h>
>> +#include <reset.h>
>> +#include <clk.h>
>> +
>> +DECLARE_GLOBAL_DATA_PTR;
>> +
>> +struct dwc3_of_simple {
>> +#if CONFIG_IS_ENABLED(CLK)
>> +	struct clk_bulk		clks;
>> +#endif
>> +#if CONFIG_IS_ENABLED(DM_RESET)
>> +	struct reset_ctl_bulk	resets;
>> +#endif
>> +};
>> +
>> +#if CONFIG_IS_ENABLED(DM_RESET)
>> +static int dwc3_of_simple_reset_init(struct udevice *dev,
>> +				     struct dwc3_of_simple *simple)
>> +{
>> +	int ret;
>> +
>> +	ret = reset_get_bulk(dev, &simple->resets);
>> +	if (ret)
>> +		return ret;
>> +
>> +	ret = reset_deassert_bulk(&simple->resets);
>> +	if (ret) {
>> +		reset_release_bulk(&simple->resets);
>> +		return ret;
>> +	}
>> +
>> +	return 0;
>> +}
>> +#endif
>> +
>> +#if CONFIG_IS_ENABLED(CLK)
>> +static int dwc3_of_simple_clk_init(struct udevice *dev,
>> +				   struct dwc3_of_simple *simple)
>> +{
>> +	int ret;
>> +
>> +	ret = clk_get_bulk(dev, &simple->clks);
>> +	if (ret)
>> +		return ret;
>> +
>> +	ret = clk_enable_bulk(&simple->clks);
>> +	if (ret) {
>> +		clk_release_bulk(&simple->clks);
>> +		return ret;
>> +	}
>> +
>> +	return 0;
>> +}
>> +#endif
>> +
>> +static int dwc3_of_simple_probe(struct udevice *dev)
>> +{
>> +#if CONFIG_IS_ENABLED(DM_RESET) || CONFIG_IS_ENABLED(CLK)
>> +	struct dwc3_of_simple *simple = dev_get_platdata(dev);
>> +	int ret;
>> +#endif
>> +
>> +#if CONFIG_IS_ENABLED(CLK)
>> +	ret = dwc3_of_simple_clk_init(dev, simple);
>> +	if (ret)
>> +		return ret;
>> +#endif
>> +
>> +#if CONFIG_IS_ENABLED(DM_RESET)
>> +	ret = dwc3_of_simple_reset_init(dev, simple);
>> +	if (ret)
>> +		return ret;
>> +#endif
>> +
>> +	return 0;
>> +}
>> +
>> +static int dwc3_of_simple_remove(struct udevice *dev)
>> +{
>> +#if CONFIG_IS_ENABLED(DM_RESET) || CONFIG_IS_ENABLED(CLK)
>> +	struct dwc3_of_simple *simple = dev_get_platdata(dev);
>> +#endif
>> +
>> +#if CONFIG_IS_ENABLED(DM_RESET)
>> +	reset_release_bulk(&simple->resets);
>> +#endif
>> +
>> +#if CONFIG_IS_ENABLED(CLK)
>> +	clk_release_bulk(&simple->clks);
>> +#endif
>> +
>> +	return dm_scan_fdt_dev(dev);
>> +}
>> +
>> +static const struct udevice_id dwc3_of_simple_ids[] = {
>> +	{ .compatible = "amlogic,meson-gxl-dwc3" },
>> +	{ }
>> +};
>> +
>> +U_BOOT_DRIVER(dwc3_of_simple) = {
>> +	.name = "dwc3-of-simple",
>> +	.id = UCLASS_SIMPLE_BUS,
>> +	.of_match = dwc3_of_simple_ids,
>> +	.probe = dwc3_of_simple_probe,
>> +	.remove = dwc3_of_simple_remove,
>> +	.platdata_auto_alloc_size = sizeof(struct dwc3_of_simple),
>> +	.flags = DM_FLAG_ALLOC_PRIV_DMA,
>> +};
>>
> 
> 



From marex at denx.de  Wed Apr 11 07:59:39 2018
From: marex at denx.de (Marek Vasut)
Date: Wed, 11 Apr 2018 16:59:39 +0200
Subject: [PATCH v2 u-boot 1/3] usb: host: Add simple of glue driver for
 DWC3 USB Controllers integration
In-Reply-To: <b4c270c1-201d-70b6-8a34-d458e211bb25@baylibre.com>
References: <1523456947-4242-1-git-send-email-narmstrong@baylibre.com>
 <1523456947-4242-2-git-send-email-narmstrong@baylibre.com>
 <f073d38e-1196-6bd6-0081-fcf4f87c7fd6@denx.de>
 <b4c270c1-201d-70b6-8a34-d458e211bb25@baylibre.com>
Message-ID: <2b758956-b970-8675-c4db-28f878524a63@denx.de>

On 04/11/2018 04:53 PM, Neil Armstrong wrote:
> Hi Marek,
> 
> On 11/04/2018 16:37, Marek Vasut wrote:
>> On 04/11/2018 04:29 PM, Neil Armstrong wrote:
>>> This is a port of the dwc3-of-simple driver from Linux to enable/deassert
>>> clock and resets of a simple DWC3 Controller HW glue.
>>>
>>> Signed-off-by: Neil Armstrong <narmstrong at baylibre.com>
>>
>> Looks good, except can we reduce the number of ifdefs, ie. by using
>> empty functions if DM_* is not defined ?
> 
> For reset, yes, for clock only the get_bulk and release_bulk...

Any reduction of the omnipresent ifdefs would be nice.

> Should I re-spin ?

That'd be nice, thanks.

-- 
Best regards,
Marek Vasut


From narmstrong at baylibre.com  Wed Apr 11 08:07:59 2018
From: narmstrong at baylibre.com (Neil Armstrong)
Date: Wed, 11 Apr 2018 17:07:59 +0200
Subject: [PATCH v3 u-boot 0/3] Add USB Support for Amlogic Meson GXL SoCs
Message-ID: <1523459282-12235-1-git-send-email-narmstrong@baylibre.com>

This patchset adds support for USB for the Amlogic Meson GXL SoCs following
the work done for Linux by Martin Blumenstingl at [1] [2] [3].

The support consist of :
 - A port of dwc3-of-simple from Linux to U-boot
 - A change to support more than 2 PHYs in the DWC3 DM driver
 - An USB2 PHY Driver and an USB3 PHY Driver

The DWC3 Controller has up to 4 PHYs connected :
 - 2 USB2 PHYs and an USB3 PHY for GXL SoCs
 - 3 USB2 PHYs and an USB3 PHY for the GXM SoC Variant
This is enabled by the "usb: host: dwc3: Add support for multiple PHYs" patch.
This patch is based on the "xhci-dwc3: Couple of fixes for USB3 support"
serie from Vignesh R, on the u-boot-usb tree.

The DWC3 Controller glue is generic enough to use the dwc3-of-simple from Linux
and can be easily ported to U-Boot as a Simple-Bus with Glue-Specific clocks
and Reset lines setup.

This depends on the recently applied :
 - clk: Add get/enable/disable/release for a bulk of clocks at [4]
 - reset: Add get/assert/deassert/release for bulk of reset signals at [5]
in order to manage the clocks and resets of the Glue in a clean fashion.

The USB PHY driver supports the standard generic PHY interface and supports
the power-on/off calls and set the Host mode by default.
They are based on the excellent work from Martin Blumenstingl merged in linux.

Changes since v2:
 - Drop #if and use the empty stubs for clock & reset API

Changes since v1:
 - switch to submitted clk/reset bulk API
 - splitted dwc3 multiple phy init error between poweroff & exit

[1] https://lkml.kernel.org/r/20180303184700.21480-1-martin.blumenstingl at googlemail.com
[2] https://lkml.kernel.org/r/20180128202245.25021-1-martin.blumenstingl at googlemail.com
[3] https://lkml.kernel.org/r/20180303214309.25643-1-martin.blumenstingl at googlemail.com
[4] http://lists.infradead.org/pipermail/linux-amlogic/2018-April/006952.html
[5] http://lists.infradead.org/pipermail/linux-amlogic/2018-April/006949.html

Neil Armstrong (3):
  usb: host: Add simple of glue driver for DWC3 USB Controllers
    integration
  usb: host: dwc3: Add support for multiple PHYs
  phy: Add Amlogic Meson USB2 & USB3 Generic PHY drivers

 drivers/phy/Kconfig               |   8 ++
 drivers/phy/Makefile              |   1 +
 drivers/phy/meson-gxl-usb2.c      | 238 ++++++++++++++++++++++++++++++++++++++
 drivers/phy/meson-gxl-usb3.c      | 201 ++++++++++++++++++++++++++++++++
 drivers/usb/host/Kconfig          |   7 ++
 drivers/usb/host/Makefile         |   1 +
 drivers/usb/host/dwc3-of-simple.c | 109 +++++++++++++++++
 drivers/usb/host/xhci-dwc3.c      | 113 ++++++++++--------
 8 files changed, 631 insertions(+), 47 deletions(-)
 create mode 100644 drivers/phy/meson-gxl-usb2.c
 create mode 100644 drivers/phy/meson-gxl-usb3.c
 create mode 100644 drivers/usb/host/dwc3-of-simple.c

-- 
2.7.4



From narmstrong at baylibre.com  Wed Apr 11 08:08:00 2018
From: narmstrong at baylibre.com (Neil Armstrong)
Date: Wed, 11 Apr 2018 17:08:00 +0200
Subject: [PATCH v3 u-boot 1/3] usb: host: Add simple of glue driver for DWC3
 USB Controllers integration
In-Reply-To: <1523459282-12235-1-git-send-email-narmstrong@baylibre.com>
References: <1523459282-12235-1-git-send-email-narmstrong@baylibre.com>
Message-ID: <1523459282-12235-2-git-send-email-narmstrong@baylibre.com>

This is a port of the dwc3-of-simple driver from Linux to enable/deassert
clock and resets of a simple DWC3 Controller HW glue.

Signed-off-by: Neil Armstrong <narmstrong at baylibre.com>
---
 drivers/usb/host/Kconfig          |   7 +++
 drivers/usb/host/Makefile         |   1 +
 drivers/usb/host/dwc3-of-simple.c | 109 ++++++++++++++++++++++++++++++++++++++
 3 files changed, 117 insertions(+)
 create mode 100644 drivers/usb/host/dwc3-of-simple.c

diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig
index a7249b7..6caa615 100644
--- a/drivers/usb/host/Kconfig
+++ b/drivers/usb/host/Kconfig
@@ -21,6 +21,13 @@ config USB_XHCI_DWC3
 	  Say Y or if your system has a Dual Role SuperSpeed
 	  USB controller based on the DesignWare USB3 IP Core.
 
+config USB_XHCI_DWC3_OF_SIMPLE
+	bool "DesignWare USB3 DRD Generic OF Simple Glue Layer"
+	select MISC
+	help
+	  Support USB2/3 functionality in simple SoC integrations with
+	  USB controller based on the DesignWare USB3 IP Core.
+
 config USB_XHCI_MVEBU
 	bool "MVEBU USB 3.0 support"
 	default y
diff --git a/drivers/usb/host/Makefile b/drivers/usb/host/Makefile
index 9819489..abe4f90 100644
--- a/drivers/usb/host/Makefile
+++ b/drivers/usb/host/Makefile
@@ -49,6 +49,7 @@ obj-$(CONFIG_USB_EHCI_ZYNQ) += ehci-zynq.o
 # xhci
 obj-$(CONFIG_USB_XHCI_HCD) += xhci.o xhci-mem.o xhci-ring.o
 obj-$(CONFIG_USB_XHCI_DWC3) += xhci-dwc3.o
+obj-$(CONFIG_USB_XHCI_DWC3_OF_SIMPLE) += dwc3-of-simple.o
 obj-$(CONFIG_USB_XHCI_ROCKCHIP) += xhci-rockchip.o
 obj-$(CONFIG_USB_XHCI_ZYNQMP) += xhci-zynqmp.o
 obj-$(CONFIG_USB_XHCI_KEYSTONE) += xhci-keystone.o
diff --git a/drivers/usb/host/dwc3-of-simple.c b/drivers/usb/host/dwc3-of-simple.c
new file mode 100644
index 0000000..54a5f60
--- /dev/null
+++ b/drivers/usb/host/dwc3-of-simple.c
@@ -0,0 +1,109 @@
+/*
+ * dwc3-of-simple.c - OF glue layer for simple integrations
+ *
+ * Copyright (c) 2015 Texas Instruments Incorporated - http://www.ti.com
+ *
+ * Author: Felipe Balbi <balbi at ti.com>
+ *
+ * Copyright (C) 2018 BayLibre, SAS
+ * Author: Neil Armstrong <narmstron at baylibre.com>
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <fdtdec.h>
+#include <reset.h>
+#include <clk.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct dwc3_of_simple {
+	struct clk_bulk		clks;
+	struct reset_ctl_bulk	resets;
+};
+
+static int dwc3_of_simple_reset_init(struct udevice *dev,
+				     struct dwc3_of_simple *simple)
+{
+	int ret;
+
+	ret = reset_get_bulk(dev, &simple->resets);
+	if (ret == -ENOTSUPP)
+		return 0;
+	else if (ret)
+		return ret;
+
+	ret = reset_deassert_bulk(&simple->resets);
+	if (ret) {
+		reset_release_bulk(&simple->resets);
+		return ret;
+	}
+
+	return 0;
+}
+
+static int dwc3_of_simple_clk_init(struct udevice *dev,
+				   struct dwc3_of_simple *simple)
+{
+	int ret;
+
+	ret = clk_get_bulk(dev, &simple->clks);
+	if (ret == -ENOTSUPP)
+		return 0;
+	if (ret)
+		return ret;
+
+#if CONFIG_IS_ENABLED(CLK)
+	ret = clk_enable_bulk(&simple->clks);
+	if (ret) {
+		clk_release_bulk(&simple->clks);
+		return ret;
+	}
+#endif
+
+	return 0;
+}
+
+static int dwc3_of_simple_probe(struct udevice *dev)
+{
+	struct dwc3_of_simple *simple = dev_get_platdata(dev);
+	int ret;
+
+	ret = dwc3_of_simple_clk_init(dev, simple);
+	if (ret)
+		return ret;
+
+	ret = dwc3_of_simple_reset_init(dev, simple);
+	if (ret)
+		return ret;
+
+	return 0;
+}
+
+static int dwc3_of_simple_remove(struct udevice *dev)
+{
+	struct dwc3_of_simple *simple = dev_get_platdata(dev);
+
+	reset_release_bulk(&simple->resets);
+
+	clk_release_bulk(&simple->clks);
+
+	return dm_scan_fdt_dev(dev);
+}
+
+static const struct udevice_id dwc3_of_simple_ids[] = {
+	{ .compatible = "amlogic,meson-gxl-dwc3" },
+	{ }
+};
+
+U_BOOT_DRIVER(dwc3_of_simple) = {
+	.name = "dwc3-of-simple",
+	.id = UCLASS_SIMPLE_BUS,
+	.of_match = dwc3_of_simple_ids,
+	.probe = dwc3_of_simple_probe,
+	.remove = dwc3_of_simple_remove,
+	.platdata_auto_alloc_size = sizeof(struct dwc3_of_simple),
+	.flags = DM_FLAG_ALLOC_PRIV_DMA,
+};
-- 
2.7.4



From narmstrong at baylibre.com  Wed Apr 11 08:08:01 2018
From: narmstrong at baylibre.com (Neil Armstrong)
Date: Wed, 11 Apr 2018 17:08:01 +0200
Subject: [PATCH v3 u-boot 2/3] usb: host: dwc3: Add support for multiple PHYs
In-Reply-To: <1523459282-12235-1-git-send-email-narmstrong@baylibre.com>
References: <1523459282-12235-1-git-send-email-narmstrong@baylibre.com>
Message-ID: <1523459282-12235-3-git-send-email-narmstrong@baylibre.com>

DWC3 Ips can have more than 1 PHY for USB2 and 1 PHY for USB3, add support
for a generic number of PHYs and adapt the code to handle a generic
number of PHYs.

Signed-off-by: Neil Armstrong <narmstrong at baylibre.com>
---
 drivers/usb/host/xhci-dwc3.c | 113 +++++++++++++++++++++++++------------------
 1 file changed, 66 insertions(+), 47 deletions(-)

diff --git a/drivers/usb/host/xhci-dwc3.c b/drivers/usb/host/xhci-dwc3.c
index 1022dd5..c100735 100644
--- a/drivers/usb/host/xhci-dwc3.c
+++ b/drivers/usb/host/xhci-dwc3.c
@@ -22,8 +22,8 @@
 DECLARE_GLOBAL_DATA_PTR;
 
 struct xhci_dwc3_platdata {
-	struct phy usb_phy;
-	struct phy usb3_phy;
+	struct phy *usb_phys;
+	int num_phys;
 };
 
 void dwc3_set_mode(struct dwc3 *dwc3_reg, u32 mode)
@@ -113,45 +113,82 @@ void dwc3_set_fladj(struct dwc3 *dwc3_reg, u32 val)
 }
 
 #ifdef CONFIG_DM_USB
-static int xhci_dwc3_setup_phy(struct udevice *dev, int index, struct phy *phy)
+static int xhci_dwc3_setup_phy(struct udevice *dev, int count)
 {
-	int ret = 0;
+	struct xhci_dwc3_platdata *plat = dev_get_platdata(dev);
+	int i, ret;
+
+	if (!count)
+		return 0;
 
-	ret = generic_phy_get_by_index(dev, index, phy);
-	if (ret) {
-		if (ret != -ENOENT) {
-			pr_err("Failed to get USB PHY for %s\n", dev->name);
+	plat->usb_phys = devm_kcalloc(dev, count, sizeof(struct phy),
+					GFP_KERNEL);
+	if (!plat->usb_phys)
+		return -ENOMEM;
+
+	for (i = 0; i < count; i++) {
+		ret = generic_phy_get_by_index(dev, i, &plat->usb_phys[i]);
+		if (ret && ret != -ENOENT) {
+			pr_err("Failed to get USB PHY%d for %s\n",
+			       i, dev->name);
 			return ret;
 		}
-	} else {
-		ret = generic_phy_init(phy);
+
+		++plat->num_phys;
+	}
+	
+	for (i = 0; i < plat->num_phys; i++) {
+		ret = generic_phy_init(&plat->usb_phys[i]);
 		if (ret) {
-			pr_err("Can't init USB PHY for %s\n", dev->name);
-			return ret;
+			pr_err("Can't init USB PHY%d for %s\n",
+			       i, dev->name);
+			goto phys_init_err;
 		}
-		ret = generic_phy_power_on(phy);
+	}
+	
+	for (i = 0; i < plat->num_phys; i++) {
+		ret = generic_phy_power_on(&plat->usb_phys[i]);
 		if (ret) {
-			pr_err("Can't power on USB PHY for %s\n", dev->name);
-			generic_phy_exit(phy);
-			return ret;
+			pr_err("Can't power USB PHY%d for %s\n",
+			       i, dev->name);
+			goto phys_poweron_err;
 		}
 	}
 
 	return 0;
+
+
+phys_poweron_err:
+	for (; i >= 0; i--)
+		generic_phy_power_off(&plat->usb_phys[i]);
+
+	for (i = 0; i < plat->num_phys; i++)
+		generic_phy_exit(&plat->usb_phys[i]);
+
+	return ret;
+
+phys_init_err:
+	for (; i >= 0; i--)
+		generic_phy_exit(&plat->usb_phys[i]);
+
+	return ret;
 }
 
-static int xhci_dwc3_shutdown_phy(struct phy *phy)
+static int xhci_dwc3_shutdown_phy(struct udevice *dev)
 {
-	int ret = 0;
+	struct xhci_dwc3_platdata *plat = dev_get_platdata(dev);
+	int i, ret;
 
-	if (generic_phy_valid(phy)) {
-		ret = generic_phy_power_off(phy);
-		if (ret)
-			return ret;
+	for (i = 0; i < plat->num_phys; i++) {
+		if (!generic_phy_valid(&plat->usb_phys[i]))
+			continue;
 
-		ret = generic_phy_exit(phy);
-		if (ret)
-			return ret;
+		ret = generic_phy_power_off(&plat->usb_phys[i]);
+		ret |= generic_phy_exit(&plat->usb_phys[i]);
+		if (ret) {
+			pr_err("Can't shutdown USB PHY%d for %s\n",
+				i, dev->name);
+		}
 	}
 
 	return 0;
@@ -159,7 +196,6 @@ static int xhci_dwc3_shutdown_phy(struct phy *phy)
 
 static int xhci_dwc3_probe(struct udevice *dev)
 {
-	struct xhci_dwc3_platdata *plat = dev_get_platdata(dev);
 	struct xhci_hcor *hcor;
 	struct xhci_hccr *hccr;
 	struct dwc3 *dwc3_reg;
@@ -170,18 +206,10 @@ static int xhci_dwc3_probe(struct udevice *dev)
 	hcor = (struct xhci_hcor *)((uintptr_t)hccr +
 			HC_LENGTH(xhci_readl(&(hccr)->cr_capbase)));
 
-	ret = xhci_dwc3_setup_phy(dev, 0, &plat->usb_phy);
-	if (ret) {
-		pr_err("Failed to setup USB PHY for %s\n", dev->name);
+	ret = xhci_dwc3_setup_phy(dev, dev_count_phandle_with_args(
+						dev, "phys", "#phy-cells"));
+	if (ret)
 		return ret;
-	}
-
-	ret = xhci_dwc3_setup_phy(dev, 1, &plat->usb3_phy);
-	if (ret) {
-		pr_err("Failed to setup USB3 PHY for %s\n", dev->name);
-		xhci_dwc3_shutdown_phy(&plat->usb_phy);
-		return ret;
-	}
 
 	dwc3_reg = (struct dwc3 *)((char *)(hccr) + DWC3_REG_OFFSET);
 
@@ -199,16 +227,7 @@ static int xhci_dwc3_probe(struct udevice *dev)
 
 static int xhci_dwc3_remove(struct udevice *dev)
 {
-	struct xhci_dwc3_platdata *plat = dev_get_platdata(dev);
-	int ret;
-
-	ret = xhci_dwc3_shutdown_phy(&plat->usb_phy);
-	if (ret)
-		pr_err("Can't shutdown USB PHY for %s\n", dev->name);
-
-	ret = xhci_dwc3_shutdown_phy(&plat->usb3_phy);
-	if (ret)
-		pr_err("Can't shutdown USB3 PHY for %s\n", dev->name);
+	xhci_dwc3_shutdown_phy(dev);
 
 	return xhci_deregister(dev);
 }
-- 
2.7.4



From narmstrong at baylibre.com  Wed Apr 11 08:08:02 2018
From: narmstrong at baylibre.com (Neil Armstrong)
Date: Wed, 11 Apr 2018 17:08:02 +0200
Subject: [PATCH v3 u-boot 3/3] phy: Add Amlogic Meson USB2 & USB3 Generic PHY
 drivers
In-Reply-To: <1523459282-12235-1-git-send-email-narmstrong@baylibre.com>
References: <1523459282-12235-1-git-send-email-narmstrong@baylibre.com>
Message-ID: <1523459282-12235-4-git-send-email-narmstrong@baylibre.com>

The Amlogic Meson GXL and GXM (simple variant) embeds up to 3 USB2 PHYs
and an USB3 PHY. This patch adds drivers for these for the standard generic
PHY interface and supports the power-on/off calls and set the Host mode by
default.
They are based on the excellent work from Martin Blumenstingl merged in linux.

Signed-off-by: Neil Armstrong <narmstrong at baylibre.com>
---
 drivers/phy/Kconfig          |   8 ++
 drivers/phy/Makefile         |   1 +
 drivers/phy/meson-gxl-usb2.c | 238 +++++++++++++++++++++++++++++++++++++++++++
 drivers/phy/meson-gxl-usb3.c | 201 ++++++++++++++++++++++++++++++++++++
 4 files changed, 448 insertions(+)
 create mode 100644 drivers/phy/meson-gxl-usb2.c
 create mode 100644 drivers/phy/meson-gxl-usb3.c

diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
index 3b9a09c..99a6d95 100644
--- a/drivers/phy/Kconfig
+++ b/drivers/phy/Kconfig
@@ -85,4 +85,12 @@ config STI_USB_PHY
 	  used by USB2 and USB3 Host controllers available on
 	  STiH407 SoC families.
 
+config MESON_GXL_USB_PHY
+	bool "Amlogic Meson GXL USB PHYs"
+	depends on PHY && ARCH_MESON && MESON_GXL
+	imply REGMAP
+	help
+	  This is the generic phy driver for the Amlogic Meson GXL
+	  USB2 and USB3 PHYS.
+
 endmenu
diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
index 668040b..6c1610e 100644
--- a/drivers/phy/Makefile
+++ b/drivers/phy/Makefile
@@ -10,3 +10,4 @@ obj-$(CONFIG_$(SPL_)NOP_PHY) += nop-phy.o
 obj-$(CONFIG_PHY_SANDBOX) += sandbox-phy.o
 obj-$(CONFIG_$(SPL_)PIPE3_PHY) += ti-pipe3-phy.o
 obj-$(CONFIG_STI_USB_PHY) += sti_usb_phy.o
+obj-$(CONFIG_MESON_GXL_USB_PHY) += meson-gxl-usb2.o meson-gxl-usb3.o
diff --git a/drivers/phy/meson-gxl-usb2.c b/drivers/phy/meson-gxl-usb2.c
new file mode 100644
index 0000000..15c9c89
--- /dev/null
+++ b/drivers/phy/meson-gxl-usb2.c
@@ -0,0 +1,238 @@
+/*
+ * Meson GXL and GXM USB2 PHY driver
+ *
+ * Copyright (C) 2017 Martin Blumenstingl <martin.blumenstingl at googlemail.com>
+ * Copyright (C) 2018 BayLibre, SAS
+ * Author: Neil Armstrong <narmstron at baylibre.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <bitfield.h>
+#include <dm.h>
+#include <errno.h>
+#include <generic-phy.h>
+#include <regmap.h>
+#include <power/regulator.h>
+#include <clk.h>
+
+#include <linux/bitops.h>
+#include <linux/compat.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* bits [31:27] are read-only */
+#define U2P_R0							0x0
+	#define U2P_R0_BYPASS_SEL				BIT(0)
+	#define U2P_R0_BYPASS_DM_EN				BIT(1)
+	#define U2P_R0_BYPASS_DP_EN				BIT(2)
+	#define U2P_R0_TXBITSTUFF_ENH				BIT(3)
+	#define U2P_R0_TXBITSTUFF_EN				BIT(4)
+	#define U2P_R0_DM_PULLDOWN				BIT(5)
+	#define U2P_R0_DP_PULLDOWN				BIT(6)
+	#define U2P_R0_DP_VBUS_VLD_EXT_SEL			BIT(7)
+	#define U2P_R0_DP_VBUS_VLD_EXT				BIT(8)
+	#define U2P_R0_ADP_PRB_EN				BIT(9)
+	#define U2P_R0_ADP_DISCHARGE				BIT(10)
+	#define U2P_R0_ADP_CHARGE				BIT(11)
+	#define U2P_R0_DRV_VBUS					BIT(12)
+	#define U2P_R0_ID_PULLUP				BIT(13)
+	#define U2P_R0_LOOPBACK_EN_B				BIT(14)
+	#define U2P_R0_OTG_DISABLE				BIT(15)
+	#define U2P_R0_COMMON_ONN				BIT(16)
+	#define U2P_R0_FSEL_MASK				GENMASK(19, 17)
+	#define U2P_R0_REF_CLK_SEL_MASK				GENMASK(21, 20)
+	#define U2P_R0_POWER_ON_RESET				BIT(22)
+	#define U2P_R0_V_ATE_TEST_EN_B_MASK			GENMASK(24, 23)
+	#define U2P_R0_ID_SET_ID_DQ				BIT(25)
+	#define U2P_R0_ATE_RESET				BIT(26)
+	#define U2P_R0_FSV_MINUS				BIT(27)
+	#define U2P_R0_FSV_PLUS					BIT(28)
+	#define U2P_R0_BYPASS_DM_DATA				BIT(29)
+	#define U2P_R0_BYPASS_DP_DATA				BIT(30)
+
+#define U2P_R1							0x4
+	#define U2P_R1_BURN_IN_TEST				BIT(0)
+	#define U2P_R1_ACA_ENABLE				BIT(1)
+	#define U2P_R1_DCD_ENABLE				BIT(2)
+	#define U2P_R1_VDAT_SRC_EN_B				BIT(3)
+	#define U2P_R1_VDAT_DET_EN_B				BIT(4)
+	#define U2P_R1_CHARGES_SEL				BIT(5)
+	#define U2P_R1_TX_PREEMP_PULSE_TUNE			BIT(6)
+	#define U2P_R1_TX_PREEMP_AMP_TUNE_MASK			GENMASK(8, 7)
+	#define U2P_R1_TX_RES_TUNE_MASK				GENMASK(10, 9)
+	#define U2P_R1_TX_RISE_TUNE_MASK			GENMASK(12, 11)
+	#define U2P_R1_TX_VREF_TUNE_MASK			GENMASK(16, 13)
+	#define U2P_R1_TX_FSLS_TUNE_MASK			GENMASK(20, 17)
+	#define U2P_R1_TX_HSXV_TUNE_MASK			GENMASK(22, 21)
+	#define U2P_R1_OTG_TUNE_MASK				GENMASK(25, 23)
+	#define U2P_R1_SQRX_TUNE_MASK				GENMASK(28, 26)
+	#define U2P_R1_COMP_DIS_TUNE_MASK			GENMASK(31, 29)
+
+/* bits [31:14] are read-only */
+#define U2P_R2							0x8
+	#define U2P_R2_TESTDATA_IN_MASK				GENMASK(7, 0)
+	#define U2P_R2_TESTADDR_MASK				GENMASK(11, 8)
+	#define U2P_R2_TESTDATA_OUT_SEL				BIT(12)
+	#define U2P_R2_TESTCLK					BIT(13)
+	#define U2P_R2_TESTDATA_OUT_MASK			GENMASK(17, 14)
+	#define U2P_R2_ACA_PIN_RANGE_C				BIT(18)
+	#define U2P_R2_ACA_PIN_RANGE_B				BIT(19)
+	#define U2P_R2_ACA_PIN_RANGE_A				BIT(20)
+	#define U2P_R2_ACA_PIN_GND				BIT(21)
+	#define U2P_R2_ACA_PIN_FLOAT				BIT(22)
+	#define U2P_R2_CHARGE_DETECT				BIT(23)
+	#define U2P_R2_DEVICE_SESSION_VALID			BIT(24)
+	#define U2P_R2_ADP_PROBE				BIT(25)
+	#define U2P_R2_ADP_SENSE				BIT(26)
+	#define U2P_R2_SESSION_END				BIT(27)
+	#define U2P_R2_VBUS_VALID				BIT(28)
+	#define U2P_R2_B_VALID					BIT(29)
+	#define U2P_R2_A_VALID					BIT(30)
+	#define U2P_R2_ID_DIG					BIT(31)
+
+#define U2P_R3							0xc
+
+#define RESET_COMPLETE_TIME				500
+
+struct phy_meson_gxl_usb2_priv {
+	struct regmap		*regmap;
+#if CONFIG_IS_ENABLED(DM_REGULATOR)
+	struct udevice		*phy_supply;
+#endif
+#if CONFIG_IS_ENABLED(CLK)
+	struct clk		clk;
+#endif
+};
+
+static void phy_meson_gxl_usb2_reset(struct phy_meson_gxl_usb2_priv *priv)
+{
+	uint val;
+
+	regmap_read(priv->regmap, U2P_R0, &val);
+
+	/* reset the PHY and wait until settings are stabilized */
+	val |= U2P_R0_POWER_ON_RESET;
+	regmap_write(priv->regmap, U2P_R0, val);
+	udelay(RESET_COMPLETE_TIME);
+
+	val &= ~U2P_R0_POWER_ON_RESET;
+	regmap_write(priv->regmap, U2P_R0, val);
+	udelay(RESET_COMPLETE_TIME);
+}
+
+static void
+phy_meson_gxl_usb2_set_host_mode(struct phy_meson_gxl_usb2_priv *priv)
+{
+	uint val;
+
+	regmap_read(priv->regmap, U2P_R0, &val);
+	val |= U2P_R0_DM_PULLDOWN;
+	val |= U2P_R0_DP_PULLDOWN;
+	val &= ~U2P_R0_ID_PULLUP;
+	regmap_write(priv->regmap, U2P_R0, val);
+
+	phy_meson_gxl_usb2_reset(priv);
+}
+
+static int phy_meson_gxl_usb2_power_on(struct phy *phy)
+{
+	struct udevice *dev = phy->dev;
+	struct phy_meson_gxl_usb2_priv *priv = dev_get_priv(dev);
+	uint val;
+
+	regmap_read(priv->regmap, U2P_R0, &val);
+	/* power on the PHY by taking it out of reset mode */
+	val &= ~U2P_R0_POWER_ON_RESET;
+	regmap_write(priv->regmap, U2P_R0, val);
+
+	phy_meson_gxl_usb2_set_host_mode(priv);
+
+#if CONFIG_IS_ENABLED(DM_REGULATOR)
+	if (priv->phy_supply) {
+		int ret = regulator_set_enable(priv->phy_supply, true);
+		if (ret)
+			return ret;
+	}
+#endif
+
+	return 0;
+}
+
+static int phy_meson_gxl_usb2_power_off(struct phy *phy)
+{
+	struct udevice *dev = phy->dev;
+	struct phy_meson_gxl_usb2_priv *priv = dev_get_priv(dev);
+	uint val;
+
+	regmap_read(priv->regmap, U2P_R0, &val);
+	/* power off the PHY by putting it into reset mode */
+	val |= U2P_R0_POWER_ON_RESET;
+	regmap_write(priv->regmap, U2P_R0, val);
+
+#if CONFIG_IS_ENABLED(DM_REGULATOR)
+	if (priv->phy_supply) {
+		int ret = regulator_set_enable(priv->phy_supply, false);
+		if (ret) {
+			pr_err("Error disabling PHY supply\n");
+			return ret;
+		}
+	}
+#endif
+
+	return 0;
+}
+
+struct phy_ops meson_gxl_usb2_phy_ops = {
+	.power_on = phy_meson_gxl_usb2_power_on,
+	.power_off = phy_meson_gxl_usb2_power_off,
+};
+
+int meson_gxl_usb2_phy_probe(struct udevice *dev)
+{
+	struct phy_meson_gxl_usb2_priv *priv = dev_get_priv(dev);
+	int ret;
+
+	ret = regmap_init_mem(dev, &priv->regmap);
+	if (ret)
+		return ret;
+
+#if CONFIG_IS_ENABLED(CLK)
+	ret = clk_get_by_index(dev, 0, &priv->clk);
+	if (ret < 0)
+		return ret;
+
+	ret = clk_enable(&priv->clk);
+	if (ret && ret != -ENOSYS && ret != -ENOTSUPP) {
+		pr_err("failed to enable PHY clock\n");
+		clk_free(&priv->clk);
+		return ret;
+	}
+#endif
+
+#if CONFIG_IS_ENABLED(DM_REGULATOR)
+	ret = device_get_supply_regulator(dev, "phy-supply", &priv->phy_supply);
+	if (ret && ret != -ENOENT) {
+		pr_err("Failed to get PHY regulator\n");
+		return ret;
+	}
+#endif
+
+	return 0;
+}
+
+static const struct udevice_id meson_gxl_usb2_phy_ids[] = {
+	{ .compatible = "amlogic,meson-gxl-usb2-phy" },
+	{ }
+};
+
+U_BOOT_DRIVER(meson_gxl_usb2_phy) = {
+	.name = "meson_gxl_usb2_phy",
+	.id = UCLASS_PHY,
+	.of_match = meson_gxl_usb2_phy_ids,
+	.probe = meson_gxl_usb2_phy_probe,
+	.ops = &meson_gxl_usb2_phy_ops,
+	.priv_auto_alloc_size = sizeof(struct phy_meson_gxl_usb2_priv),
+};
diff --git a/drivers/phy/meson-gxl-usb3.c b/drivers/phy/meson-gxl-usb3.c
new file mode 100644
index 0000000..a385fbd
--- /dev/null
+++ b/drivers/phy/meson-gxl-usb3.c
@@ -0,0 +1,201 @@
+/*
+ * Meson GXL USB3 PHY driver
+ *
+ * Copyright (C) 2018 Martin Blumenstingl <martin.blumenstingl at googlemail.com>
+ * Copyright (C) 2018 BayLibre, SAS
+ * Author: Neil Armstrong <narmstron at baylibre.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <bitfield.h>
+#include <dm.h>
+#include <errno.h>
+#include <generic-phy.h>
+#include <regmap.h>
+#include <clk.h>
+
+#include <linux/bitops.h>
+#include <linux/compat.h>
+#include <linux/bitfield.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define USB_R0							0x00
+	#define USB_R0_P30_FSEL_MASK				GENMASK(5, 0)
+	#define USB_R0_P30_PHY_RESET				BIT(6)
+	#define USB_R0_P30_TEST_POWERDOWN_HSP			BIT(7)
+	#define USB_R0_P30_TEST_POWERDOWN_SSP			BIT(8)
+	#define USB_R0_P30_ACJT_LEVEL_MASK			GENMASK(13, 9)
+	#define USB_R0_P30_TX_BOOST_LEVEL_MASK			GENMASK(16, 14)
+	#define USB_R0_P30_LANE0_TX2RX_LOOPBACK			BIT(17)
+	#define USB_R0_P30_LANE0_EXT_PCLK_REQ			BIT(18)
+	#define USB_R0_P30_PCS_RX_LOS_MASK_VAL_MASK		GENMASK(28, 19)
+	#define USB_R0_U2D_SS_SCALEDOWN_MODE_MASK		GENMASK(30, 29)
+	#define USB_R0_U2D_ACT					BIT(31)
+
+#define USB_R1							0x04
+	#define USB_R1_U3H_BIGENDIAN_GS				BIT(0)
+	#define USB_R1_U3H_PME_ENABLE				BIT(1)
+	#define USB_R1_U3H_HUB_PORT_OVERCURRENT_MASK		GENMASK(6, 2)
+	#define USB_R1_U3H_HUB_PORT_PERM_ATTACH_MASK		GENMASK(11, 7)
+	#define USB_R1_U3H_HOST_U2_PORT_DISABLE_MASK		GENMASK(15, 12)
+	#define USB_R1_U3H_HOST_U3_PORT_DISABLE			BIT(16)
+	#define USB_R1_U3H_HOST_PORT_POWER_CONTROL_PRESENT	BIT(17)
+	#define USB_R1_U3H_HOST_MSI_ENABLE			BIT(18)
+	#define USB_R1_U3H_FLADJ_30MHZ_REG_MASK			GENMASK(24, 19)
+	#define USB_R1_P30_PCS_TX_SWING_FULL_MASK		GENMASK(31, 25)
+
+#define USB_R2							0x08
+	#define USB_R2_P30_CR_DATA_IN_MASK			GENMASK(15, 0)
+	#define USB_R2_P30_CR_READ				BIT(16)
+	#define USB_R2_P30_CR_WRITE				BIT(17)
+	#define USB_R2_P30_CR_CAP_ADDR				BIT(18)
+	#define USB_R2_P30_CR_CAP_DATA				BIT(19)
+	#define USB_R2_P30_PCS_TX_DEEMPH_3P5DB_MASK		GENMASK(25, 20)
+	#define USB_R2_P30_PCS_TX_DEEMPH_6DB_MASK		GENMASK(31, 26)
+
+#define USB_R3							0x0c
+	#define USB_R3_P30_SSC_ENABLE				BIT(0)
+	#define USB_R3_P30_SSC_RANGE_MASK			GENMASK(3, 1)
+	#define USB_R3_P30_SSC_REF_CLK_SEL_MASK			GENMASK(12, 4)
+	#define USB_R3_P30_REF_SSP_EN				BIT(13)
+	#define USB_R3_P30_LOS_BIAS_MASK			GENMASK(18, 16)
+	#define USB_R3_P30_LOS_LEVEL_MASK			GENMASK(23, 19)
+	#define USB_R3_P30_MPLL_MULTIPLIER_MASK			GENMASK(30, 24)
+
+#define USB_R4							0x10
+	#define USB_R4_P21_PORT_RESET_0				BIT(0)
+	#define USB_R4_P21_SLEEP_M0				BIT(1)
+	#define USB_R4_MEM_PD_MASK				GENMASK(3, 2)
+	#define USB_R4_P21_ONLY					BIT(4)
+
+#define USB_R5							0x14
+	#define USB_R5_ID_DIG_SYNC				BIT(0)
+	#define USB_R5_ID_DIG_REG				BIT(1)
+	#define USB_R5_ID_DIG_CFG_MASK				GENMASK(3, 2)
+	#define USB_R5_ID_DIG_EN_0				BIT(4)
+	#define USB_R5_ID_DIG_EN_1				BIT(5)
+	#define USB_R5_ID_DIG_CURR				BIT(6)
+	#define USB_R5_ID_DIG_IRQ				BIT(7)
+	#define USB_R5_ID_DIG_TH_MASK				GENMASK(15, 8)
+	#define USB_R5_ID_DIG_CNT_MASK				GENMASK(23, 16)
+
+/* read-only register */
+#define USB_R6							0x18
+	#define USB_R6_P30_CR_DATA_OUT_MASK			GENMASK(15, 0)
+	#define USB_R6_P30_CR_ACK				BIT(16)
+
+struct phy_meson_gxl_usb3_priv {
+	struct regmap		*regmap;
+#if CONFIG_IS_ENABLED(CLK)
+	struct clk		clk;
+#endif
+};
+
+static int
+phy_meson_gxl_usb3_set_host_mode(struct phy_meson_gxl_usb3_priv *priv)
+{
+	uint val;
+
+	regmap_read(priv->regmap, USB_R0, &val);
+	val &= ~USB_R0_U2D_ACT;
+	regmap_write(priv->regmap, USB_R0, val);
+
+	regmap_read(priv->regmap, USB_R4, &val);
+	val &= ~USB_R4_P21_SLEEP_M0;
+	regmap_write(priv->regmap, USB_R4, val);
+
+	return 0;
+}
+
+static int phy_meson_gxl_usb3_power_on(struct phy *phy)
+{
+	struct udevice *dev = phy->dev;
+	struct phy_meson_gxl_usb3_priv *priv = dev_get_priv(dev);
+	uint val;
+
+	regmap_read(priv->regmap, USB_R5, &val);
+	val |= USB_R5_ID_DIG_EN_0;
+	val |= USB_R5_ID_DIG_EN_1;
+	val &= ~USB_R5_ID_DIG_TH_MASK;
+	val |= FIELD_PREP(USB_R5_ID_DIG_TH_MASK, 0xff);
+	regmap_write(priv->regmap, USB_R5, val);
+
+	return phy_meson_gxl_usb3_set_host_mode(priv);
+}
+
+static int phy_meson_gxl_usb3_power_off(struct phy *phy)
+{
+	struct udevice *dev = phy->dev;
+	struct phy_meson_gxl_usb3_priv *priv = dev_get_priv(dev);
+	uint val;
+
+	regmap_read(priv->regmap, USB_R5, &val);
+	val &= ~USB_R5_ID_DIG_EN_0;
+	val &= ~USB_R5_ID_DIG_EN_1;
+	regmap_write(priv->regmap, USB_R5, val);
+
+	return 0;
+}
+
+static int phy_meson_gxl_usb3_init(struct phy *phy)
+{
+	struct udevice *dev = phy->dev;
+	struct phy_meson_gxl_usb3_priv *priv = dev_get_priv(dev);
+	uint val;
+
+	regmap_read(priv->regmap, USB_R1, &val);
+	val &= ~USB_R1_U3H_FLADJ_30MHZ_REG_MASK;
+	val |= FIELD_PREP(USB_R1_U3H_FLADJ_30MHZ_REG_MASK, 0x20);
+	regmap_write(priv->regmap, USB_R1, val);
+
+	return 0;
+}
+
+struct phy_ops meson_gxl_usb3_phy_ops = {
+	.init = phy_meson_gxl_usb3_init,
+	.power_on = phy_meson_gxl_usb3_power_on,
+	.power_off = phy_meson_gxl_usb3_power_off,
+};
+
+int meson_gxl_usb3_phy_probe(struct udevice *dev)
+{
+	struct phy_meson_gxl_usb3_priv *priv = dev_get_priv(dev);
+	int ret;
+
+	ret = regmap_init_mem(dev, &priv->regmap);
+	if (ret)
+		return ret;
+	
+#if CONFIG_IS_ENABLED(CLK)
+	ret = clk_get_by_index(dev, 0, &priv->clk);
+	if (ret < 0)
+		return ret;
+
+	ret = clk_enable(&priv->clk);
+	if (ret && ret != -ENOSYS && ret != -ENOTSUPP) {
+		pr_err("failed to enable PHY clock\n");
+		clk_free(&priv->clk);
+		return ret;
+	}
+#endif
+
+	return 0;
+}
+
+static const struct udevice_id meson_gxl_usb3_phy_ids[] = {
+	{ .compatible = "amlogic,meson-gxl-usb3-phy" },
+	{ }
+};
+
+U_BOOT_DRIVER(meson_gxl_usb3_phy) = {
+	.name = "meson_gxl_usb3_phy",
+	.id = UCLASS_PHY,
+	.of_match = meson_gxl_usb3_phy_ids,
+	.probe = meson_gxl_usb3_phy_probe,
+	.ops = &meson_gxl_usb3_phy_ops,
+	.priv_auto_alloc_size = sizeof(struct phy_meson_gxl_usb3_priv),
+};
-- 
2.7.4



From narmstrong at baylibre.com  Wed Apr 11 08:13:45 2018
From: narmstrong at baylibre.com (Neil Armstrong)
Date: Wed, 11 Apr 2018 17:13:45 +0200
Subject: [PATCH v2 u-boot] ARM: meson: rename GXBB to GX
Message-ID: <1523459625-16446-1-git-send-email-narmstrong@baylibre.com>

Taking into account the Amlogic Family name starts with GX, including
the GXBB, GXL and GXM SoCs.

Signed-off-by: Neil Armstrong <narmstrong at baylibre.com>
---

Changes since v1:
 - Resent as single patch since cpuinfo needs further work
 - Aligned the defines in gx.h

 arch/arm/include/asm/arch-meson/gx.h      | 70 +++++++++++++++++++++++++++++++
 arch/arm/include/asm/arch-meson/gxbb.h    | 70 -------------------------------
 arch/arm/mach-meson/board.c               | 28 ++++++-------
 arch/arm/mach-meson/eth.c                 | 24 +++++------
 arch/arm/mach-meson/sm.c                  |  2 +-
 board/amlogic/khadas-vim/khadas-vim.c     |  2 +-
 board/amlogic/libretech-cc/libretech-cc.c |  6 +--
 board/amlogic/odroid-c2/odroid-c2.c       | 10 ++---
 board/amlogic/p212/p212.c                 |  2 +-
 include/configs/khadas-vim.h              |  2 +-
 include/configs/libretech-cc.h            |  2 +-
 include/configs/meson-gx-common.h         | 47 +++++++++++++++++++++
 include/configs/meson-gxbb-common.h       | 47 ---------------------
 include/configs/odroid-c2.h               |  2 +-
 include/configs/p212.h                    |  2 +-
 15 files changed, 158 insertions(+), 158 deletions(-)
 create mode 100644 arch/arm/include/asm/arch-meson/gx.h
 delete mode 100644 arch/arm/include/asm/arch-meson/gxbb.h
 create mode 100644 include/configs/meson-gx-common.h
 delete mode 100644 include/configs/meson-gxbb-common.h

diff --git a/arch/arm/include/asm/arch-meson/gx.h b/arch/arm/include/asm/arch-meson/gx.h
new file mode 100644
index 0000000..2b311cd
--- /dev/null
+++ b/arch/arm/include/asm/arch-meson/gx.h
@@ -0,0 +1,70 @@
+/*
+ * (C) Copyright 2016 - Beniamino Galvani <b.galvani at gmail.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __GX_H__
+#define __GX_H__
+
+#define GX_FIRMWARE_MEM_SIZE		0x1000000
+
+#define GX_AOBUS_BASE			0xc8100000
+#define GX_PERIPHS_BASE			0xc8834400
+#define GX_HIU_BASE			0xc883c000
+#define GX_ETH_BASE			0xc9410000
+
+/* Always-On Peripherals registers */
+#define GX_AO_ADDR(off)			(GX_AOBUS_BASE + ((off) << 2))
+
+#define GX_AO_SEC_GP_CFG0		GX_AO_ADDR(0x90)
+#define GX_AO_SEC_GP_CFG3		GX_AO_ADDR(0x93)
+#define GX_AO_SEC_GP_CFG4		GX_AO_ADDR(0x94)
+#define GX_AO_SEC_GP_CFG5		GX_AO_ADDR(0x95)
+
+#define GX_AO_MEM_SIZE_MASK		0xFFFF0000
+#define GX_AO_MEM_SIZE_SHIFT		16
+#define GX_AO_BL31_RSVMEM_SIZE_MASK	0xFFFF0000
+#define GX_AO_BL31_RSVMEM_SIZE_SHIFT	16
+#define GX_AO_BL32_RSVMEM_SIZE_MASK	0xFFFF
+
+/* Peripherals registers */
+#define GX_PERIPHS_ADDR(off)		(GX_PERIPHS_BASE + ((off) << 2))
+
+/* GPIO registers 0 to 6 */
+#define _GX_GPIO_OFF(n)			((n) == 6 ? 0x08 : 0x0c + 3 * (n))
+#define GX_GPIO_EN(n)			GX_PERIPHS_ADDR(_GX_GPIO_OFF(n) + 0)
+#define GX_GPIO_IN(n)			GX_PERIPHS_ADDR(_GX_GPIO_OFF(n) + 1)
+#define GX_GPIO_OUT(n)			GX_PERIPHS_ADDR(_GX_GPIO_OFF(n) + 2)
+
+#define GX_ETH_REG_0			GX_PERIPHS_ADDR(0x50)
+#define GX_ETH_REG_1			GX_PERIPHS_ADDR(0x51)
+#define GX_ETH_REG_2			GX_PERIPHS_ADDR(0x56)
+#define GX_ETH_REG_3			GX_PERIPHS_ADDR(0x57)
+
+#define GX_ETH_REG_0_PHY_INTF		BIT(0)
+#define GX_ETH_REG_0_TX_PHASE(x)	(((x) & 3) << 5)
+#define GX_ETH_REG_0_TX_RATIO(x)	(((x) & 7) << 7)
+#define GX_ETH_REG_0_PHY_CLK_EN		BIT(10)
+#define GX_ETH_REG_0_INVERT_RMII_CLK	BIT(11)
+#define GX_ETH_REG_0_CLK_EN		BIT(12)
+
+/* HIU registers */
+#define GX_HIU_ADDR(off)		(GX_HIU_BASE + ((off) << 2))
+
+#define GX_MEM_PD_REG_0			GX_HIU_ADDR(0x40)
+
+/* Ethernet memory power domain */
+#define GX_MEM_PD_REG_0_ETH_MASK	(BIT(2) | BIT(3))
+
+/* Clock gates */
+#define GX_GCLK_MPEG_0			GX_HIU_ADDR(0x50)
+#define GX_GCLK_MPEG_1			GX_HIU_ADDR(0x51)
+#define GX_GCLK_MPEG_2			GX_HIU_ADDR(0x52)
+#define GX_GCLK_MPEG_OTHER		GX_HIU_ADDR(0x53)
+#define GX_GCLK_MPEG_AO			GX_HIU_ADDR(0x54)
+
+#define GX_GCLK_MPEG_0_I2C		BIT(9)
+#define GX_GCLK_MPEG_1_ETH		BIT(3)
+
+#endif /* __GX_H__ */
diff --git a/arch/arm/include/asm/arch-meson/gxbb.h b/arch/arm/include/asm/arch-meson/gxbb.h
deleted file mode 100644
index ef63dea..0000000
--- a/arch/arm/include/asm/arch-meson/gxbb.h
+++ /dev/null
@@ -1,70 +0,0 @@
-/*
- * (C) Copyright 2016 - Beniamino Galvani <b.galvani at gmail.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef __GXBB_H__
-#define __GXBB_H__
-
-#define GXBB_FIRMWARE_MEM_SIZE	0x1000000
-
-#define GXBB_AOBUS_BASE		0xc8100000
-#define GXBB_PERIPHS_BASE	0xc8834400
-#define GXBB_HIU_BASE		0xc883c000
-#define GXBB_ETH_BASE		0xc9410000
-
-/* Always-On Peripherals registers */
-#define GXBB_AO_ADDR(off)	(GXBB_AOBUS_BASE + ((off) << 2))
-
-#define GXBB_AO_SEC_GP_CFG0	GXBB_AO_ADDR(0x90)
-#define GXBB_AO_SEC_GP_CFG3	GXBB_AO_ADDR(0x93)
-#define GXBB_AO_SEC_GP_CFG4	GXBB_AO_ADDR(0x94)
-#define GXBB_AO_SEC_GP_CFG5	GXBB_AO_ADDR(0x95)
-
-#define GXBB_AO_MEM_SIZE_MASK	0xFFFF0000
-#define GXBB_AO_MEM_SIZE_SHIFT	16
-#define GXBB_AO_BL31_RSVMEM_SIZE_MASK	0xFFFF0000
-#define GXBB_AO_BL31_RSVMEM_SIZE_SHIFT	16
-#define GXBB_AO_BL32_RSVMEM_SIZE_MASK	0xFFFF
-
-/* Peripherals registers */
-#define GXBB_PERIPHS_ADDR(off)	(GXBB_PERIPHS_BASE + ((off) << 2))
-
-/* GPIO registers 0 to 6 */
-#define _GXBB_GPIO_OFF(n)	((n) == 6 ? 0x08 : 0x0c + 3 * (n))
-#define GXBB_GPIO_EN(n)		GXBB_PERIPHS_ADDR(_GXBB_GPIO_OFF(n) + 0)
-#define GXBB_GPIO_IN(n)		GXBB_PERIPHS_ADDR(_GXBB_GPIO_OFF(n) + 1)
-#define GXBB_GPIO_OUT(n)	GXBB_PERIPHS_ADDR(_GXBB_GPIO_OFF(n) + 2)
-
-#define GXBB_ETH_REG_0		GXBB_PERIPHS_ADDR(0x50)
-#define GXBB_ETH_REG_1		GXBB_PERIPHS_ADDR(0x51)
-#define GXBB_ETH_REG_2		GXBB_PERIPHS_ADDR(0x56)
-#define GXBB_ETH_REG_3		GXBB_PERIPHS_ADDR(0x57)
-
-#define GXBB_ETH_REG_0_PHY_INTF		BIT(0)
-#define GXBB_ETH_REG_0_TX_PHASE(x)	(((x) & 3) << 5)
-#define GXBB_ETH_REG_0_TX_RATIO(x)	(((x) & 7) << 7)
-#define GXBB_ETH_REG_0_PHY_CLK_EN	BIT(10)
-#define GXBB_ETH_REG_0_INVERT_RMII_CLK	BIT(11)
-#define GXBB_ETH_REG_0_CLK_EN		BIT(12)
-
-/* HIU registers */
-#define GXBB_HIU_ADDR(off)	(GXBB_HIU_BASE + ((off) << 2))
-
-#define GXBB_MEM_PD_REG_0	GXBB_HIU_ADDR(0x40)
-
-/* Ethernet memory power domain */
-#define GXBB_MEM_PD_REG_0_ETH_MASK	(BIT(2) | BIT(3))
-
-/* Clock gates */
-#define GXBB_GCLK_MPEG_0	GXBB_HIU_ADDR(0x50)
-#define GXBB_GCLK_MPEG_1	GXBB_HIU_ADDR(0x51)
-#define GXBB_GCLK_MPEG_2	GXBB_HIU_ADDR(0x52)
-#define GXBB_GCLK_MPEG_OTHER	GXBB_HIU_ADDR(0x53)
-#define GXBB_GCLK_MPEG_AO	GXBB_HIU_ADDR(0x54)
-
-#define GXBB_GCLK_MPEG_0_I2C   BIT(9)
-#define GXBB_GCLK_MPEG_1_ETH	BIT(3)
-
-#endif /* __GXBB_H__ */
diff --git a/arch/arm/mach-meson/board.c b/arch/arm/mach-meson/board.c
index b6d3a17..0693d9d 100644
--- a/arch/arm/mach-meson/board.c
+++ b/arch/arm/mach-meson/board.c
@@ -7,7 +7,7 @@
 #include <common.h>
 #include <linux/libfdt.h>
 #include <linux/err.h>
-#include <asm/arch/gxbb.h>
+#include <asm/arch/gx.h>
 #include <asm/arch/sm.h>
 #include <asm/armv8/mmu.h>
 #include <asm/unaligned.h>
@@ -40,8 +40,8 @@ int dram_init(void)
 phys_size_t get_effective_memsize(void)
 {
 	/* Size is reported in MiB, convert it in bytes */
-	return ((readl(GXBB_AO_SEC_GP_CFG0) & GXBB_AO_MEM_SIZE_MASK)
-			>> GXBB_AO_MEM_SIZE_SHIFT) * SZ_1M;
+	return ((readl(GX_AO_SEC_GP_CFG0) & GX_AO_MEM_SIZE_MASK)
+			>> GX_AO_MEM_SIZE_SHIFT) * SZ_1M;
 }
 
 static void meson_board_add_reserved_memory(void *fdt, u64 start, u64 size)
@@ -72,27 +72,27 @@ void meson_gx_init_reserved_memory(void *fdt)
 	 * - AO_SEC_GP_CFG4: bl32 physical start address, can be NULL
 	 */
 
-	reg = readl(GXBB_AO_SEC_GP_CFG3);
+	reg = readl(GX_AO_SEC_GP_CFG3);
 
-	bl31_size = ((reg & GXBB_AO_BL31_RSVMEM_SIZE_MASK)
-			>> GXBB_AO_BL31_RSVMEM_SIZE_SHIFT) * SZ_1K;
-	bl32_size = (reg & GXBB_AO_BL32_RSVMEM_SIZE_MASK) * SZ_1K;
+	bl31_size = ((reg & GX_AO_BL31_RSVMEM_SIZE_MASK)
+			>> GX_AO_BL31_RSVMEM_SIZE_SHIFT) * SZ_1K;
+	bl32_size = (reg & GX_AO_BL32_RSVMEM_SIZE_MASK) * SZ_1K;
 
-	bl31_start = readl(GXBB_AO_SEC_GP_CFG5);
-	bl32_start = readl(GXBB_AO_SEC_GP_CFG4);
+	bl31_start = readl(GX_AO_SEC_GP_CFG5);
+	bl32_start = readl(GX_AO_SEC_GP_CFG4);
 
 	/*
-	 * Early Meson GXBB Firmware revisions did not provide the reserved
+	 * Early Meson GX Firmware revisions did not provide the reserved
 	 * memory zones in the registers, keep fixed memory zone handling.
 	 */
-	if (IS_ENABLED(CONFIG_MESON_GXBB) &&
+	if (IS_ENABLED(CONFIG_MESON_GX) &&
 	    !reg && !bl31_start && !bl32_start) {
 		bl31_start = 0x10000000;
 		bl31_size = 0x200000;
 	}
 
 	/* Add first 16MiB reserved zone */
-	meson_board_add_reserved_memory(fdt, 0, GXBB_FIRMWARE_MEM_SIZE);
+	meson_board_add_reserved_memory(fdt, 0, GX_FIRMWARE_MEM_SIZE);
 
 	/* Add BL31 reserved zone */
 	if (bl31_start && bl31_size)
@@ -108,7 +108,7 @@ void reset_cpu(ulong addr)
 	psci_system_reset();
 }
 
-static struct mm_region gxbb_mem_map[] = {
+static struct mm_region gx_mem_map[] = {
 	{
 		.virt = 0x0UL,
 		.phys = 0x0UL,
@@ -128,4 +128,4 @@ static struct mm_region gxbb_mem_map[] = {
 	}
 };
 
-struct mm_region *mem_map = gxbb_mem_map;
+struct mm_region *mem_map = gx_mem_map;
diff --git a/arch/arm/mach-meson/eth.c b/arch/arm/mach-meson/eth.c
index 8c6577b..8050bfa 100644
--- a/arch/arm/mach-meson/eth.c
+++ b/arch/arm/mach-meson/eth.c
@@ -8,7 +8,7 @@
 #include <common.h>
 #include <dm.h>
 #include <asm/io.h>
-#include <asm/arch/gxbb.h>
+#include <asm/arch/gx.h>
 #include <asm/arch/eth.h>
 #include <phy.h>
 
@@ -23,23 +23,23 @@ void meson_gx_eth_init(phy_interface_t mode, unsigned int flags)
 	case PHY_INTERFACE_MODE_RGMII_RXID:
 	case PHY_INTERFACE_MODE_RGMII_TXID:
 		/* Set RGMII mode */
-		setbits_le32(GXBB_ETH_REG_0, GXBB_ETH_REG_0_PHY_INTF |
-			     GXBB_ETH_REG_0_TX_PHASE(1) |
-			     GXBB_ETH_REG_0_TX_RATIO(4) |
-			     GXBB_ETH_REG_0_PHY_CLK_EN |
-			     GXBB_ETH_REG_0_CLK_EN);
+		setbits_le32(GX_ETH_REG_0, GX_ETH_REG_0_PHY_INTF |
+			     GX_ETH_REG_0_TX_PHASE(1) |
+			     GX_ETH_REG_0_TX_RATIO(4) |
+			     GX_ETH_REG_0_PHY_CLK_EN |
+			     GX_ETH_REG_0_CLK_EN);
 		break;
 
 	case PHY_INTERFACE_MODE_RMII:
 		/* Set RMII mode */
-		out_le32(GXBB_ETH_REG_0, GXBB_ETH_REG_0_INVERT_RMII_CLK |
-					 GXBB_ETH_REG_0_CLK_EN);
+		out_le32(GX_ETH_REG_0, GX_ETH_REG_0_INVERT_RMII_CLK |
+					 GX_ETH_REG_0_CLK_EN);
 
 		/* Use GXL RMII Internal PHY */
 		if (IS_ENABLED(CONFIG_MESON_GXL) &&
 		    (flags & MESON_GXL_USE_INTERNAL_RMII_PHY)) {
-			writel(0x10110181, GXBB_ETH_REG_2);
-			writel(0xe40908ff, GXBB_ETH_REG_3);
+			writel(0x10110181, GX_ETH_REG_2);
+			writel(0xe40908ff, GX_ETH_REG_3);
 		}
 
 		break;
@@ -50,6 +50,6 @@ void meson_gx_eth_init(phy_interface_t mode, unsigned int flags)
 	}
 
 	/* Enable power and clock gate */
-	setbits_le32(GXBB_GCLK_MPEG_1, GXBB_GCLK_MPEG_1_ETH);
-	clrbits_le32(GXBB_MEM_PD_REG_0, GXBB_MEM_PD_REG_0_ETH_MASK);
+	setbits_le32(GX_GCLK_MPEG_1, GX_GCLK_MPEG_1_ETH);
+	clrbits_le32(GX_MEM_PD_REG_0, GX_MEM_PD_REG_0_ETH_MASK);
 }
diff --git a/arch/arm/mach-meson/sm.c b/arch/arm/mach-meson/sm.c
index 1b35a22..b374031 100644
--- a/arch/arm/mach-meson/sm.c
+++ b/arch/arm/mach-meson/sm.c
@@ -7,7 +7,7 @@
  */
 
 #include <common.h>
-#include <asm/arch/gxbb.h>
+#include <asm/arch/gx.h>
 #include <linux/kernel.h>
 
 #define FN_GET_SHARE_MEM_INPUT_BASE	0x82000020
diff --git a/board/amlogic/khadas-vim/khadas-vim.c b/board/amlogic/khadas-vim/khadas-vim.c
index 83b1b6e..c23ddab 100644
--- a/board/amlogic/khadas-vim/khadas-vim.c
+++ b/board/amlogic/khadas-vim/khadas-vim.c
@@ -9,7 +9,7 @@
 #include <dm.h>
 #include <environment.h>
 #include <asm/io.h>
-#include <asm/arch/gxbb.h>
+#include <asm/arch/gx.h>
 #include <asm/arch/mem.h>
 #include <asm/arch/sm.h>
 #include <asm/arch/eth.h>
diff --git a/board/amlogic/libretech-cc/libretech-cc.c b/board/amlogic/libretech-cc/libretech-cc.c
index 5795340..36fda46 100644
--- a/board/amlogic/libretech-cc/libretech-cc.c
+++ b/board/amlogic/libretech-cc/libretech-cc.c
@@ -9,7 +9,7 @@
 #include <dm.h>
 #include <environment.h>
 #include <asm/io.h>
-#include <asm/arch/gxbb.h>
+#include <asm/arch/gx.h>
 #include <asm/arch/sm.h>
 #include <asm/arch/eth.h>
 #include <asm/arch/mem.h>
@@ -34,8 +34,8 @@ int misc_init_r(void)
 			  MESON_GXL_USE_INTERNAL_RMII_PHY);
 
 	/* Enable power and clock gate */
-	setbits_le32(GXBB_GCLK_MPEG_1, GXBB_GCLK_MPEG_1_ETH);
-	clrbits_le32(GXBB_MEM_PD_REG_0, GXBB_MEM_PD_REG_0_ETH_MASK);
+	setbits_le32(GX_GCLK_MPEG_1, GX_GCLK_MPEG_1_ETH);
+	clrbits_le32(GX_MEM_PD_REG_0, GX_MEM_PD_REG_0_ETH_MASK);
 
 	if (!eth_env_get_enetaddr("ethaddr", mac_addr)) {
 		len = meson_sm_read_efuse(EFUSE_MAC_OFFSET,
diff --git a/board/amlogic/odroid-c2/odroid-c2.c b/board/amlogic/odroid-c2/odroid-c2.c
index 8645f22..0ec0771 100644
--- a/board/amlogic/odroid-c2/odroid-c2.c
+++ b/board/amlogic/odroid-c2/odroid-c2.c
@@ -8,7 +8,7 @@
 #include <dm.h>
 #include <environment.h>
 #include <asm/io.h>
-#include <asm/arch/gxbb.h>
+#include <asm/arch/gx.h>
 #include <asm/arch/sm.h>
 #include <asm/arch/eth.h>
 #include <asm/arch/mem.h>
@@ -32,13 +32,13 @@ int misc_init_r(void)
 	meson_gx_eth_init(PHY_INTERFACE_MODE_RGMII, 0);
 
 	/* Enable power and clock gate */
-	setbits_le32(GXBB_GCLK_MPEG_0, GXBB_GCLK_MPEG_0_I2C);
+	setbits_le32(GX_GCLK_MPEG_0, GX_GCLK_MPEG_0_I2C);
 
 	/* Reset PHY on GPIOZ_14 */
-	clrbits_le32(GXBB_GPIO_EN(3), BIT(14));
-	clrbits_le32(GXBB_GPIO_OUT(3), BIT(14));
+	clrbits_le32(GX_GPIO_EN(3), BIT(14));
+	clrbits_le32(GX_GPIO_OUT(3), BIT(14));
 	mdelay(10);
-	setbits_le32(GXBB_GPIO_OUT(3), BIT(14));
+	setbits_le32(GX_GPIO_OUT(3), BIT(14));
 
 	if (!eth_env_get_enetaddr("ethaddr", mac_addr)) {
 		len = meson_sm_read_efuse(EFUSE_MAC_OFFSET,
diff --git a/board/amlogic/p212/p212.c b/board/amlogic/p212/p212.c
index 7c0abbc..10f6b23 100644
--- a/board/amlogic/p212/p212.c
+++ b/board/amlogic/p212/p212.c
@@ -9,7 +9,7 @@
 #include <dm.h>
 #include <environment.h>
 #include <asm/io.h>
-#include <asm/arch/gxbb.h>
+#include <asm/arch/gx.h>
 #include <asm/arch/sm.h>
 #include <asm/arch/eth.h>
 #include <asm/arch/mem.h>
diff --git a/include/configs/khadas-vim.h b/include/configs/khadas-vim.h
index f44b388..8f14208 100644
--- a/include/configs/khadas-vim.h
+++ b/include/configs/khadas-vim.h
@@ -14,6 +14,6 @@
 
 #define MESON_FDTFILE_SETTING "fdtfile=amlogic/meson-gxl-s905x-khadas-vim.dtb\0"
 
-#include <configs/meson-gxbb-common.h>
+#include <configs/meson-gx-common.h>
 
 #endif /* __CONFIG_H */
diff --git a/include/configs/libretech-cc.h b/include/configs/libretech-cc.h
index 08dfb30..897a697 100644
--- a/include/configs/libretech-cc.h
+++ b/include/configs/libretech-cc.h
@@ -14,6 +14,6 @@
 
 #define MESON_FDTFILE_SETTING "fdtfile=amlogic/meson-gxl-s905x-libretech-cc.dtb\0"
 
-#include <configs/meson-gxbb-common.h>
+#include <configs/meson-gx-common.h>
 
 #endif /* __CONFIG_H */
diff --git a/include/configs/meson-gx-common.h b/include/configs/meson-gx-common.h
new file mode 100644
index 0000000..1131643
--- /dev/null
+++ b/include/configs/meson-gx-common.h
@@ -0,0 +1,47 @@
+/*
+ * Configuration for Amlogic Meson GX SoCs
+ * (C) Copyright 2016 Beniamino Galvani <b.galvani at gmail.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __MESON_GX_COMMON_CONFIG_H
+#define __MESON_GX_COMMON_CONFIG_H
+
+#define CONFIG_CPU_ARMV8
+#define CONFIG_REMAKE_ELF
+#define CONFIG_NR_DRAM_BANKS		1
+#define CONFIG_ENV_SIZE			0x2000
+#define CONFIG_SYS_MAXARGS		32
+#define CONFIG_SYS_MALLOC_LEN		(32 << 20)
+#define CONFIG_SYS_CBSIZE		1024
+
+#define CONFIG_SYS_SDRAM_BASE		0
+#define CONFIG_SYS_INIT_SP_ADDR		0x20000000
+#define CONFIG_SYS_LOAD_ADDR		CONFIG_SYS_TEXT_BASE
+
+/* Generic Interrupt Controller Definitions */
+#define GICD_BASE			0xc4301000
+#define GICC_BASE			0xc4302000
+
+#define BOOT_TARGET_DEVICES(func) \
+	func(MMC, mmc, 0) \
+	func(MMC, mmc, 1) \
+	func(MMC, mmc, 2) \
+	func(PXE, pxe, na) \
+	func(DHCP, dhcp, na)
+
+#include <config_distro_bootcmd.h>
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"fdt_addr_r=0x01000000\0" \
+	"scriptaddr=0x1f000000\0" \
+	"kernel_addr_r=0x01080000\0" \
+	"pxefile_addr_r=0x01080000\0" \
+	"ramdisk_addr_r=0x13000000\0" \
+	MESON_FDTFILE_SETTING \
+	BOOTENV
+
+#define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* 64 MiB */
+
+#endif /* __MESON_GX_COMMON_CONFIG_H */
diff --git a/include/configs/meson-gxbb-common.h b/include/configs/meson-gxbb-common.h
deleted file mode 100644
index 5794bc0..0000000
--- a/include/configs/meson-gxbb-common.h
+++ /dev/null
@@ -1,47 +0,0 @@
-/*
- * Configuration for Amlogic Meson GXBB SoCs
- * (C) Copyright 2016 Beniamino Galvani <b.galvani at gmail.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef __MESON_GXBB_COMMON_CONFIG_H
-#define __MESON_GXBB_COMMON_CONFIG_H
-
-#define CONFIG_CPU_ARMV8
-#define CONFIG_REMAKE_ELF
-#define CONFIG_NR_DRAM_BANKS		1
-#define CONFIG_ENV_SIZE			0x2000
-#define CONFIG_SYS_MAXARGS		32
-#define CONFIG_SYS_MALLOC_LEN		(32 << 20)
-#define CONFIG_SYS_CBSIZE		1024
-
-#define CONFIG_SYS_SDRAM_BASE		0
-#define CONFIG_SYS_INIT_SP_ADDR		0x20000000
-#define CONFIG_SYS_LOAD_ADDR		CONFIG_SYS_TEXT_BASE
-
-/* Generic Interrupt Controller Definitions */
-#define GICD_BASE			0xc4301000
-#define GICC_BASE			0xc4302000
-
-#define BOOT_TARGET_DEVICES(func) \
-	func(MMC, mmc, 0) \
-	func(MMC, mmc, 1) \
-	func(MMC, mmc, 2) \
-	func(PXE, pxe, na) \
-	func(DHCP, dhcp, na)
-
-#include <config_distro_bootcmd.h>
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
-	"fdt_addr_r=0x01000000\0" \
-	"scriptaddr=0x1f000000\0" \
-	"kernel_addr_r=0x01080000\0" \
-	"pxefile_addr_r=0x01080000\0" \
-	"ramdisk_addr_r=0x13000000\0" \
-	MESON_FDTFILE_SETTING \
-	BOOTENV
-
-#define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* 64 MiB */
-
-#endif /* __MESON_GXBB_COMMON_CONFIG_H */
diff --git a/include/configs/odroid-c2.h b/include/configs/odroid-c2.h
index ff30a8a..d9914af 100644
--- a/include/configs/odroid-c2.h
+++ b/include/configs/odroid-c2.h
@@ -14,6 +14,6 @@
 
 #define MESON_FDTFILE_SETTING "fdtfile=amlogic/meson-gxbb-odroidc2.dtb\0"
 
-#include <configs/meson-gxbb-common.h>
+#include <configs/meson-gx-common.h>
 
 #endif /* __CONFIG_H */
diff --git a/include/configs/p212.h b/include/configs/p212.h
index a087d86..a950da3 100644
--- a/include/configs/p212.h
+++ b/include/configs/p212.h
@@ -16,6 +16,6 @@
 
 #define MESON_FDTFILE_SETTING "fdtfile=amlogic/meson-gxl-s905x-p212.dtb\0"
 
-#include <configs/meson-gxbb-common.h>
+#include <configs/meson-gx-common.h>
 
 #endif /* __CONFIG_H */
-- 
2.7.4



From marex at denx.de  Wed Apr 11 08:20:32 2018
From: marex at denx.de (Marek Vasut)
Date: Wed, 11 Apr 2018 17:20:32 +0200
Subject: [PATCH v3 u-boot 0/3] Add USB Support for Amlogic Meson GXL SoCs
In-Reply-To: <1523459282-12235-1-git-send-email-narmstrong@baylibre.com>
References: <1523459282-12235-1-git-send-email-narmstrong@baylibre.com>
Message-ID: <b83361a6-66ef-5d48-5bf6-7dabbc6a0352@denx.de>

On 04/11/2018 05:07 PM, Neil Armstrong wrote:
> This patchset adds support for USB for the Amlogic Meson GXL SoCs following
> the work done for Linux by Martin Blumenstingl at [1] [2] [3].
> 
> The support consist of :
>  - A port of dwc3-of-simple from Linux to U-boot
>  - A change to support more than 2 PHYs in the DWC3 DM driver
>  - An USB2 PHY Driver and an USB3 PHY Driver
> 
> The DWC3 Controller has up to 4 PHYs connected :
>  - 2 USB2 PHYs and an USB3 PHY for GXL SoCs
>  - 3 USB2 PHYs and an USB3 PHY for the GXM SoC Variant
> This is enabled by the "usb: host: dwc3: Add support for multiple PHYs" patch.
> This patch is based on the "xhci-dwc3: Couple of fixes for USB3 support"
> serie from Vignesh R, on the u-boot-usb tree.
> 
> The DWC3 Controller glue is generic enough to use the dwc3-of-simple from Linux
> and can be easily ported to U-Boot as a Simple-Bus with Glue-Specific clocks
> and Reset lines setup.
> 
> This depends on the recently applied :
>  - clk: Add get/enable/disable/release for a bulk of clocks at [4]
>  - reset: Add get/assert/deassert/release for bulk of reset signals at [5]
> in order to manage the clocks and resets of the Glue in a clean fashion.
> 
> The USB PHY driver supports the standard generic PHY interface and supports
> the power-on/off calls and set the Host mode by default.
> They are based on the excellent work from Martin Blumenstingl merged in linux.
> 
> Changes since v2:
>  - Drop #if and use the empty stubs for clock & reset API
> 
> Changes since v1:
>  - switch to submitted clk/reset bulk API
>  - splitted dwc3 multiple phy init error between poweroff & exit
> 

Applied all, thanks.

-- 
Best regards,
Marek Vasut


From narmstrong at baylibre.com  Wed Apr 11 08:40:39 2018
From: narmstrong at baylibre.com (Neil Armstrong)
Date: Wed, 11 Apr 2018 17:40:39 +0200
Subject: [PATCH u-boot 0/2] ARM64: meson: Sync DT and Bindings with Linux 4.16
Message-ID: <1523461241-30436-1-git-send-email-narmstrong@baylibre.com>

Synchronize the Amlogic Meson GX Device Tree and bindings with Linux 4.16 to
beneficiate with the new DT nodes.

The pinctrl bindings has changed since 4.13, so the pinctrl driver must be
updated with the changes.

Neil Armstrong (2):
  ARM64: meson: Sync DT and Bindings with Linux 4.16
  pinctrl: meson: Update pinmux with new Linux bindings

 arch/arm/dts/meson-gx.dtsi                    |  87 ++++++++++-----
 arch/arm/dts/meson-gxbb-odroidc2.dts          |  56 ++++++++--
 arch/arm/dts/meson-gxbb.dtsi                  | 137 ++++++++++++++++++++++--
 arch/arm/dts/meson-gxl-s905x-khadas-vim.dts   |  63 +++++++++++
 arch/arm/dts/meson-gxl-s905x-libretech-cc.dts | 108 ++++++++++++++++++-
 arch/arm/dts/meson-gxl-s905x-p212.dts         |   7 ++
 arch/arm/dts/meson-gxl-s905x-p212.dtsi        |  24 ++++-
 arch/arm/dts/meson-gxl.dtsi                   | 147 ++++++++++++++++++++++++--
 drivers/pinctrl/meson/pinctrl-meson-gxbb.c    |  12 +--
 drivers/pinctrl/meson/pinctrl-meson-gxl.c     |  14 +--
 include/dt-bindings/clock/gxbb-aoclkc.h       |   1 +
 include/dt-bindings/clock/gxbb-clkc.h         |  75 +++++++++++++
 include/dt-bindings/gpio/meson-gxbb-gpio.h    |   2 +-
 include/dt-bindings/gpio/meson-gxl-gpio.h     |   2 +-
 14 files changed, 658 insertions(+), 77 deletions(-)

-- 
2.7.4



From narmstrong at baylibre.com  Wed Apr 11 08:40:40 2018
From: narmstrong at baylibre.com (Neil Armstrong)
Date: Wed, 11 Apr 2018 17:40:40 +0200
Subject: [PATCH u-boot 1/2] ARM64: meson: Sync DT and Bindings with Linux 4.16
In-Reply-To: <1523461241-30436-1-git-send-email-narmstrong@baylibre.com>
References: <1523461241-30436-1-git-send-email-narmstrong@baylibre.com>
Message-ID: <1523461241-30436-2-git-send-email-narmstrong@baylibre.com>

Synchronize the Linux Device Tree for Amlogic Meson GX boards from Linux 4.16.0.

Signed-off-by: Neil Armstrong <narmstrong at baylibre.com>
---
 arch/arm/dts/meson-gx.dtsi                    |  87 ++++++++++-----
 arch/arm/dts/meson-gxbb-odroidc2.dts          |  56 ++++++++--
 arch/arm/dts/meson-gxbb.dtsi                  | 137 ++++++++++++++++++++++--
 arch/arm/dts/meson-gxl-s905x-khadas-vim.dts   |  63 +++++++++++
 arch/arm/dts/meson-gxl-s905x-libretech-cc.dts | 108 ++++++++++++++++++-
 arch/arm/dts/meson-gxl-s905x-p212.dts         |   7 ++
 arch/arm/dts/meson-gxl-s905x-p212.dtsi        |  24 ++++-
 arch/arm/dts/meson-gxl.dtsi                   | 147 ++++++++++++++++++++++++--
 include/dt-bindings/clock/gxbb-aoclkc.h       |   1 +
 include/dt-bindings/clock/gxbb-clkc.h         |  75 +++++++++++++
 include/dt-bindings/gpio/meson-gxbb-gpio.h    |   2 +-
 include/dt-bindings/gpio/meson-gxl-gpio.h     |   2 +-
 12 files changed, 645 insertions(+), 64 deletions(-)

diff --git a/arch/arm/dts/meson-gx.dtsi b/arch/arm/dts/meson-gx.dtsi
index 738ed68..4ee2e79 100644
--- a/arch/arm/dts/meson-gx.dtsi
+++ b/arch/arm/dts/meson-gx.dtsi
@@ -211,32 +211,39 @@
 		#size-cells = <2>;
 		ranges;
 
-		cbus: cbus at c1100000 {
+		cbus: bus at c1100000 {
 			compatible = "simple-bus";
 			reg = <0x0 0xc1100000 0x0 0x100000>;
 			#address-cells = <2>;
 			#size-cells = <2>;
 			ranges = <0x0 0x0 0x0 0xc1100000 0x0 0x100000>;
 
+			gpio_intc: interrupt-controller at 9880 {
+				compatible = "amlogic,meson-gpio-intc";
+				reg = <0x0 0x9880 0x0 0x10>;
+				interrupt-controller;
+				#interrupt-cells = <2>;
+				amlogic,channel-interrupts = <64 65 66 67 68 69 70 71>;
+				status = "disabled";
+			};
+
 			reset: reset-controller at 4404 {
 				compatible = "amlogic,meson-gx-reset", "amlogic,meson-gxbb-reset";
-				reg = <0x0 0x04404 0x0 0x20>;
+				reg = <0x0 0x04404 0x0 0x9c>;
 				#reset-cells = <1>;
 			};
 
 			uart_A: serial at 84c0 {
-				compatible = "amlogic,meson-uart";
-				reg = <0x0 0x84c0 0x0 0x14>;
+				compatible = "amlogic,meson-gx-uart";
+				reg = <0x0 0x84c0 0x0 0x18>;
 				interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>;
-				clocks = <&xtal>;
 				status = "disabled";
 			};
 
 			uart_B: serial at 84dc {
-				compatible = "amlogic,meson-uart";
-				reg = <0x0 0x84dc 0x0 0x14>;
+				compatible = "amlogic,meson-gx-uart";
+				reg = <0x0 0x84dc 0x0 0x18>;
 				interrupts = <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>;
-				clocks = <&xtal>;
 				status = "disabled";
 			};
 
@@ -279,10 +286,9 @@
 			};
 
 			uart_C: serial at 8700 {
-				compatible = "amlogic,meson-uart";
-				reg = <0x0 0x8700 0x0 0x14>;
+				compatible = "amlogic,meson-gx-uart";
+				reg = <0x0 0x8700 0x0 0x18>;
 				interrupts = <GIC_SPI 93 IRQ_TYPE_EDGE_RISING>;
-				clocks = <&xtal>;
 				status = "disabled";
 			};
 
@@ -360,33 +366,53 @@
 			};
 		};
 
-		aobus: aobus at c8100000 {
+		aobus: bus at c8100000 {
 			compatible = "simple-bus";
 			reg = <0x0 0xc8100000 0x0 0x100000>;
 			#address-cells = <2>;
 			#size-cells = <2>;
 			ranges = <0x0 0x0 0x0 0xc8100000 0x0 0x100000>;
 
-			clkc_AO: clock-controller at 040 {
-				compatible = "amlogic,gx-aoclkc", "amlogic,gxbb-aoclkc";
-				reg = <0x0 0x00040 0x0 0x4>;
-				#clock-cells = <1>;
-				#reset-cells = <1>;
+			sysctrl_AO: sys-ctrl at 0 {
+				compatible = "amlogic,meson-gx-ao-sysctrl", "syscon", "simple-mfd";
+				reg =  <0x0 0x0 0x0 0x100>;
+
+				pwrc_vpu: power-controller-vpu {
+					compatible = "amlogic,meson-gx-pwrc-vpu";
+					#power-domain-cells = <0>;
+					amlogic,hhi-sysctrl = <&sysctrl>;
+				};
+
+				clkc_AO: clock-controller {
+					compatible = "amlogic,meson-gx-aoclkc";
+					#clock-cells = <1>;
+					#reset-cells = <1>;
+				};
+			};
+
+			cec_AO: cec at 100 {
+				compatible = "amlogic,meson-gx-ao-cec";
+				reg = <0x0 0x00100 0x0 0x14>;
+				interrupts = <GIC_SPI 199 IRQ_TYPE_EDGE_RISING>;
+			};
+
+			sec_AO: ao-secure at 140 {
+				compatible = "amlogic,meson-gx-ao-secure", "syscon";
+				reg = <0x0 0x140 0x0 0x140>;
+				amlogic,has-chip-id;
 			};
 
 			uart_AO: serial at 4c0 {
-				compatible = "amlogic,meson-uart";
-				reg = <0x0 0x004c0 0x0 0x14>;
+				compatible = "amlogic,meson-gx-uart", "amlogic,meson-ao-uart";
+				reg = <0x0 0x004c0 0x0 0x18>;
 				interrupts = <GIC_SPI 193 IRQ_TYPE_EDGE_RISING>;
-				clocks = <&xtal>;
 				status = "disabled";
 			};
 
 			uart_AO_B: serial at 4e0 {
-				compatible = "amlogic,meson-uart";
-				reg = <0x0 0x004e0 0x0 0x14>;
+				compatible = "amlogic,meson-gx-uart", "amlogic,meson-ao-uart";
+				reg = <0x0 0x004e0 0x0 0x18>;
 				interrupts = <GIC_SPI 197 IRQ_TYPE_EDGE_RISING>;
-				clocks = <&xtal>;
 				status = "disabled";
 			};
 
@@ -427,19 +453,24 @@
 			};
 		};
 
-		hiubus: hiubus at c883c000 {
+		hiubus: bus at c883c000 {
 			compatible = "simple-bus";
 			reg = <0x0 0xc883c000 0x0 0x2000>;
 			#address-cells = <2>;
 			#size-cells = <2>;
 			ranges = <0x0 0x0 0x0 0xc883c000 0x0 0x2000>;
 
+			sysctrl: system-controller at 0 {
+				compatible = "amlogic,meson-gx-hhi-sysctrl", "syscon", "simple-mfd";
+				reg = <0 0 0 0x400>;
+			};
+
 			mailbox: mailbox at 404 {
 				compatible = "amlogic,meson-gx-mhu", "amlogic,meson-gxbb-mhu";
 				reg = <0 0x404 0 0x4c>;
-				interrupts = <0 208 IRQ_TYPE_EDGE_RISING>,
-					     <0 209 IRQ_TYPE_EDGE_RISING>,
-					     <0 210 IRQ_TYPE_EDGE_RISING>;
+				interrupts = <GIC_SPI 208 IRQ_TYPE_EDGE_RISING>,
+					     <GIC_SPI 209 IRQ_TYPE_EDGE_RISING>,
+					     <GIC_SPI 210 IRQ_TYPE_EDGE_RISING>;
 				#mbox-cells = <1>;
 			};
 		};
@@ -448,7 +479,7 @@
 			compatible = "amlogic,meson-gx-dwmac", "amlogic,meson-gxbb-dwmac", "snps,dwmac";
 			reg = <0x0 0xc9410000 0x0 0x10000
 			       0x0 0xc8834540 0x0 0x4>;
-			interrupts = <0 8 1>;
+			interrupts = <GIC_SPI 8 IRQ_TYPE_EDGE_RISING>;
 			interrupt-names = "macirq";
 			status = "disabled";
 		};
diff --git a/arch/arm/dts/meson-gxbb-odroidc2.dts b/arch/arm/dts/meson-gxbb-odroidc2.dts
index d147c85..ee4ada6 100644
--- a/arch/arm/dts/meson-gxbb-odroidc2.dts
+++ b/arch/arm/dts/meson-gxbb-odroidc2.dts
@@ -50,7 +50,7 @@
 / {
 	compatible = "hardkernel,odroid-c2", "amlogic,meson-gxbb";
 	model = "Hardkernel ODROID-C2";
-	
+
 	aliases {
 		serial0 = &uart_AO;
 	};
@@ -135,6 +135,24 @@
 		compatible = "mmc-pwrseq-emmc";
 		reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>;
 	};
+
+	hdmi-connector {
+		compatible = "hdmi-connector";
+		type = "a";
+
+		port {
+			hdmi_connector_in: endpoint {
+				remote-endpoint = <&hdmi_tx_tmds_out>;
+			};
+		};
+	};
+};
+
+&cec_AO {
+	status = "okay";
+	pinctrl-0 = <&ao_cec_pins>;
+	pinctrl-names = "default";
+	hdmi-phandle = <&hdmi_tx>;
 };
 
 &ethmac {
@@ -156,7 +174,11 @@
 		#size-cells = <0>;
 
 		eth_phy0: ethernet-phy at 0 {
+			/* Realtek RTL8211F (0x001cc916) */
 			reg = <0>;
+			interrupt-parent = <&gpio_intc>;
+			/* MAC_INTR on GPIOZ_15 */
+			interrupts = <29 IRQ_TYPE_LEVEL_LOW>;
 			eee-broken-1000t;
 		};
 	};
@@ -177,6 +199,18 @@
 	};
 };
 
+&hdmi_tx {
+	status = "okay";
+	pinctrl-0 = <&hdmi_hpd_pins>, <&hdmi_i2c_pins>;
+	pinctrl-names = "default";
+};
+
+&hdmi_tx_tmds_port {
+	hdmi_tx_tmds_out: endpoint {
+		remote-endpoint = <&hdmi_connector_in>;
+	};
+};
+
 &i2c_A {
 	status = "okay";
 	pinctrl-0 = <&i2c_a_pins>;
@@ -194,7 +228,9 @@
 			  "USB HUB nRESET", "USB OTG Power En",
 			  "J7 Header Pin2", "IR In", "J7 Header Pin4",
 			  "J7 Header Pin6", "J7 Header Pin5", "J7 Header Pin7",
-			  "HDMI CEC", "SYS LED";
+			  "HDMI CEC", "SYS LED",
+			  /* GPIO_TEST_N */
+			  "";
 };
 
 &pinctrl_periphs {
@@ -233,11 +269,9 @@
 			  "J2 Header Pin12", "J2 Header Pin13",
 			  "J2 Header Pin8", "J2 Header Pin10",
 			  "", "", "", "", "",
-			  "J2 Header Pin11", "", "J2 Header Pin7",
+			  "J2 Header Pin11", "", "J2 Header Pin7", "",
 			  /* Bank GPIOCLK */
-			  "", "", "", "",
-			  /* GPIO_TEST_N */
-			  "";
+			  "", "", "", "";
 };
 
 &saradc {
@@ -253,7 +287,8 @@
 &sd_emmc_b {
 	status = "okay";
 	pinctrl-0 = <&sdcard_pins>;
-	pinctrl-names = "default";
+	pinctrl-1 = <&sdcard_clk_gate_pins>;
+	pinctrl-names = "default", "clk-gate";
 
 	bus-width = <4>;
 	cap-sd-highspeed;
@@ -270,11 +305,11 @@
 /* eMMC */
 &sd_emmc_c {
 	status = "okay";
-	pinctrl-0 = <&emmc_pins>;
-	pinctrl-names = "default";
+	pinctrl-0 = <&emmc_pins>, <&emmc_ds_pins>;
+	pinctrl-1 = <&emmc_clk_gate_pins>;
+	pinctrl-names = "default", "clk-gate";
 
 	bus-width = <8>;
-	cap-sd-highspeed;
 	max-frequency = <200000000>;
 	non-removable;
 	disable-wp;
@@ -300,6 +335,7 @@
 
 &usb1_phy {
 	status = "okay";
+	phy-supply = <&usb_otg_pwr>;
 };
 
 &usb0 {
diff --git a/arch/arm/dts/meson-gxbb.dtsi b/arch/arm/dts/meson-gxbb.dtsi
index 17d3efd..3290a4d 100644
--- a/arch/arm/dts/meson-gxbb.dtsi
+++ b/arch/arm/dts/meson-gxbb.dtsi
@@ -307,6 +307,15 @@
 	};
 };
 
+&cec_AO {
+	clocks = <&clkc_AO CLKID_AO_CEC_32K>;
+	clock-names = "core";
+};
+
+&clkc_AO {
+	compatible = "amlogic,meson-gxbb-aoclkc", "amlogic,meson-gx-aoclkc";
+};
+
 &ethmac {
 	clocks = <&clkc CLKID_ETH>,
 		 <&clkc CLKID_FCLK_DIV2>,
@@ -314,6 +323,12 @@
 	clock-names = "stmmaceth", "clkin0", "clkin1";
 };
 
+&gpio_intc {
+	compatible = "amlogic,meson-gpio-intc",
+		     "amlogic,meson-gxbb-gpio-intc";
+	status = "okay";
+};
+
 &hdmi_tx {
 	compatible = "amlogic,meson-gxbb-dw-hdmi", "amlogic,meson-gx-dw-hdmi";
 	resets = <&reset RESET_HDMITX_CAPB3>,
@@ -370,19 +385,36 @@
 			reg-names = "mux", "pull", "pull-enable", "gpio";
 			gpio-controller;
 			#gpio-cells = <2>;
-			gpio-ranges = <&pinctrl_periphs 0 14 120>;
+			gpio-ranges = <&pinctrl_periphs 0 0 119>;
 		};
 
 		emmc_pins: emmc {
 			mux {
 				groups = "emmc_nand_d07",
 				       "emmc_cmd",
-				       "emmc_clk",
-				       "emmc_ds";
+				       "emmc_clk";
+				function = "emmc";
+			};
+		};
+
+		emmc_ds_pins: emmc-ds {
+			mux {
+				groups = "emmc_ds";
 				function = "emmc";
 			};
 		};
 
+		emmc_clk_gate_pins: emmc_clk_gate {
+			mux {
+				groups = "BOOT_8";
+				function = "gpio_periphs";
+			};
+			cfg-pull-down {
+				pins = "BOOT_8";
+				bias-pull-down;
+			};
+		};
+
 		nor_pins: nor {
 			mux {
 				groups = "nor_d",
@@ -421,6 +453,17 @@
 			};
 		};
 
+		sdcard_clk_gate_pins: sdcard_clk_gate {
+			mux {
+				groups = "CARD_2";
+				function = "gpio_periphs";
+			};
+			cfg-pull-down {
+				pins = "CARD_2";
+				bias-pull-down;
+			};
+		};
+
 		sdio_pins: sdio {
 			mux {
 				groups = "sdio_d0",
@@ -433,6 +476,17 @@
 			};
 		};
 
+		sdio_clk_gate_pins: sdio_clk_gate {
+			mux {
+				groups = "GPIOX_4";
+				function = "gpio_periphs";
+			};
+			cfg-pull-down {
+				pins = "GPIOX_4";
+				bias-pull-down;
+			};
+		};
+
 		sdio_irq_pins: sdio_irq {
 			mux {
 				groups = "sdio_irq";
@@ -640,33 +694,74 @@
 	};
 };
 
+&pwrc_vpu {
+	resets = <&reset RESET_VIU>,
+		 <&reset RESET_VENC>,
+		 <&reset RESET_VCBUS>,
+		 <&reset RESET_BT656>,
+		 <&reset RESET_DVIN_RESET>,
+		 <&reset RESET_RDMA>,
+		 <&reset RESET_VENCI>,
+		 <&reset RESET_VENCP>,
+		 <&reset RESET_VDAC>,
+		 <&reset RESET_VDI6>,
+		 <&reset RESET_VENCL>,
+		 <&reset RESET_VID_LOCK>;
+	clocks = <&clkc CLKID_VPU>,
+	         <&clkc CLKID_VAPB>;
+	clock-names = "vpu", "vapb";
+	/*
+	 * VPU clocking is provided by two identical clock paths
+	 * VPU_0 and VPU_1 muxed to a single clock by a glitch
+	 * free mux to safely change frequency while running.
+	 * Same for VAPB but with a final gate after the glitch free mux.
+	 */
+	assigned-clocks = <&clkc CLKID_VPU_0_SEL>,
+			  <&clkc CLKID_VPU_0>,
+			  <&clkc CLKID_VPU>, /* Glitch free mux */
+			  <&clkc CLKID_VAPB_0_SEL>,
+			  <&clkc CLKID_VAPB_0>,
+			  <&clkc CLKID_VAPB_SEL>; /* Glitch free mux */
+	assigned-clock-parents = <&clkc CLKID_FCLK_DIV3>,
+				 <0>, /* Do Nothing */
+				 <&clkc CLKID_VPU_0>,
+				 <&clkc CLKID_FCLK_DIV4>,
+				 <0>, /* Do Nothing */
+				 <&clkc CLKID_VAPB_0>;
+	assigned-clock-rates = <0>, /* Do Nothing */
+			       <666666666>,
+			       <0>, /* Do Nothing */
+			       <0>, /* Do Nothing */
+			       <250000000>,
+			       <0>; /* Do Nothing */
+};
+
 &saradc {
 	compatible = "amlogic,meson-gxbb-saradc", "amlogic,meson-saradc";
 	clocks = <&xtal>,
 		 <&clkc CLKID_SAR_ADC>,
-		 <&clkc CLKID_SANA>,
 		 <&clkc CLKID_SAR_ADC_CLK>,
 		 <&clkc CLKID_SAR_ADC_SEL>;
-	clock-names = "clkin", "core", "sana", "adc_clk", "adc_sel";
+	clock-names = "clkin", "core", "adc_clk", "adc_sel";
 };
 
 &sd_emmc_a {
 	clocks = <&clkc CLKID_SD_EMMC_A>,
-		 <&xtal>,
+		 <&clkc CLKID_SD_EMMC_A_CLK0>,
 		 <&clkc CLKID_FCLK_DIV2>;
 	clock-names = "core", "clkin0", "clkin1";
 };
 
 &sd_emmc_b {
 	clocks = <&clkc CLKID_SD_EMMC_B>,
-		 <&xtal>,
+		 <&clkc CLKID_SD_EMMC_B_CLK0>,
 		 <&clkc CLKID_FCLK_DIV2>;
 	clock-names = "core", "clkin0", "clkin1";
 };
 
 &sd_emmc_c {
 	clocks = <&clkc CLKID_SD_EMMC_C>,
-		 <&xtal>,
+		 <&clkc CLKID_SD_EMMC_C_CLK0>,
 		 <&clkc CLKID_FCLK_DIV2>;
 	clock-names = "core", "clkin0", "clkin1";
 };
@@ -682,6 +777,32 @@
 	clocks = <&clkc CLKID_SPI>;
 };
 
+&uart_A {
+	clocks = <&xtal>, <&clkc CLKID_UART0>, <&xtal>;
+	clock-names = "xtal", "pclk", "baud";
+};
+
+&uart_AO {
+	clocks = <&xtal>, <&clkc CLKID_CLK81>, <&xtal>;
+	clock-names = "xtal", "pclk", "baud";
+};
+
+&uart_AO_B {
+	clocks = <&xtal>, <&clkc CLKID_CLK81>, <&xtal>;
+	clock-names = "xtal", "pclk", "baud";
+};
+
+&uart_B {
+	clocks = <&xtal>, <&clkc CLKID_UART1>, <&xtal>;
+	clock-names = "xtal", "pclk", "baud";
+};
+
+&uart_C {
+	clocks = <&xtal>, <&clkc CLKID_UART2>, <&xtal>;
+	clock-names = "xtal", "pclk", "baud";
+};
+
 &vpu {
 	compatible = "amlogic,meson-gxbb-vpu", "amlogic,meson-gx-vpu";
+	power-domains = <&pwrc_vpu>;
 };
diff --git a/arch/arm/dts/meson-gxl-s905x-khadas-vim.dts b/arch/arm/dts/meson-gxl-s905x-khadas-vim.dts
index 94567eb..71a6e1c 100644
--- a/arch/arm/dts/meson-gxl-s905x-khadas-vim.dts
+++ b/arch/arm/dts/meson-gxl-s905x-khadas-vim.dts
@@ -67,6 +67,13 @@
 	};
 };
 
+&cec_AO {
+	status = "okay";
+	pinctrl-0 = <&ao_cec_pins>;
+	pinctrl-names = "default";
+	hdmi-phandle = <&hdmi_tx>;
+};
+
 &hdmi_tx {
 	status = "okay";
 	pinctrl-0 = <&hdmi_hpd_pins>, <&hdmi_i2c_pins>;
@@ -105,6 +112,62 @@
 	linux,rc-map-name = "rc-geekbox";
 };
 
+&pinctrl_aobus {
+	gpio-line-names = "UART TX",
+			  "UART RX",
+			  "Power Key In",
+			  "J9 Header Pin35",
+			  "J9 Header Pin16",
+			  "J9 Header Pin15",
+			  "J9 Header Pin33",
+			  "IR In",
+			  "HDMI CEC",
+			  "SYS LED",
+			  /* GPIO_TEST_N */
+			  "";
+};
+
+&pinctrl_periphs {
+	gpio-line-names = /* Bank GPIOZ */
+			  "", "", "", "", "", "", "",
+			  "", "", "", "", "", "", "",
+			  "Power OFF",
+			  "VCCK Enable",
+			  /* Bank GPIOH */
+			  "HDMI HPD", "HDMI SDA", "HDMI SCL",
+			  "HDMI_5V_EN", "SPDIF",
+			  "J9 Header Pin37",
+			  "J9 Header Pin30",
+			  "J9 Header Pin29",
+			  "J9 Header Pin32",
+			  "J9 Header Pin31",
+			  /* Bank BOOT */
+			  "eMMC D0", "eMMC D1", "eMMC D2", "eMMC D3",
+			  "eMMC D4", "eMMC D5", "eMMC D6", "eMMC D7",
+			  "eMMC Clk", "eMMC Reset", "eMMC CMD",
+			  "", "BOOT_MODE", "", "", "eMMC Data Strobe",
+			  /* Bank CARD */
+			  "SDCard D1", "SDCard D0", "SDCard CLK", "SDCard CMD",
+			  "SDCard D3", "SDCard D2", "SDCard Det",
+			  /* Bank GPIODV */
+			  "", "", "", "", "", "", "", "", "", "", "", "",
+			  "", "", "", "", "", "", "", "", "", "", "", "",
+			  "I2C A SDA", "I2C A SCK", "I2C B SDA", "I2C B SCK",
+			  "VCCK Regulator", "VDDEE Regulator",
+			  /* Bank GPIOX */
+			  "WIFI SDIO D0", "WIFI SDIO D1", "WIFI SDIO D2",
+			  "WIFI SDIO D3", "WIFI SDIO CLK", "WIFI SDIO CMD",
+			  "WIFI Power Enable", "WIFI WAKE HOST",
+			  "Bluetooth PCM DOUT", "Bluetooth PCM DIN",
+			  "Bluetooth PCM SYNC", "Bluetooth PCM CLK",
+			  "Bluetooth UART TX", "Bluetooth UART RX",
+			  "Bluetooth UART CTS", "Bluetooth UART RTS",
+			  "WIFI 32K", "Bluetooth Enable",
+			  "Bluetooth WAKE HOST",
+			  /* Bank GPIOCLK */
+			  "", "J9 Header Pin39";
+};
+
 &pwm_AO_ab {
 	status = "okay";
 	pinctrl-0 = <&pwm_ao_a_3_pins>, <&pwm_ao_b_pins>;
diff --git a/arch/arm/dts/meson-gxl-s905x-libretech-cc.dts b/arch/arm/dts/meson-gxl-s905x-libretech-cc.dts
index 266fbcf..9671f1e 100644
--- a/arch/arm/dts/meson-gxl-s905x-libretech-cc.dts
+++ b/arch/arm/dts/meson-gxl-s905x-libretech-cc.dts
@@ -72,6 +72,18 @@
 		reg = <0x0 0x0 0x0 0x80000000>;
 	};
 
+	hdmi_5v: regulator-hdmi-5v {
+		compatible = "regulator-fixed";
+
+		regulator-name = "HDMI_5V";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+
+		gpio = <&gpio GPIOH_3 GPIO_ACTIVE_HIGH>;
+		enable-active-high;
+		regulator-always-on;
+	};
+
 	vcc_3v3: regulator-vcc_3v3 {
 		compatible = "regulator-fixed";
 		regulator-name = "VCC_3V3";
@@ -91,6 +103,16 @@
 
 		states = <3300000 0>,
 			 <1800000 1>;
+
+		regulator-settling-time-up-us = <200>;
+		regulator-settling-time-down-us = <50000>;
+	};
+
+	vddio_ao18: regulator-vddio_ao18 {
+		compatible = "regulator-fixed";
+		regulator-name = "VDDIO_AO18";
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <1800000>;
 	};
 
 	vddio_boot: regulator-vddio_boot {
@@ -101,6 +123,13 @@
 	};
 };
 
+&cec_AO {
+	status = "okay";
+	pinctrl-0 = <&ao_cec_pins>;
+	pinctrl-names = "default";
+	hdmi-phandle = <&hdmi_tx>;
+};
+
 &cvbs_vdac_port {
 	cvbs_vdac_out: endpoint {
 		remote-endpoint = <&cvbs_connector_in>;
@@ -111,6 +140,11 @@
 	status = "okay";
 };
 
+&internal_phy {
+	pinctrl-0 = <&eth_link_led_pins>, <&eth_act_led_pins>;
+	pinctrl-names = "default";
+};
+
 &ir {
 	status = "okay";
 	pinctrl-0 = <&remote_input_ao_pins>;
@@ -129,14 +163,80 @@
 	};
 };
 
+&pinctrl_aobus {
+	gpio-line-names = "UART TX",
+			  "UART RX",
+			  "Blue LED",
+			  "SDCard Voltage Switch",
+			  "7J1 Header Pin5",
+			  "7J1 Header Pin3",
+			  "7J1 Header Pin12",
+			  "IR In",
+			  "9J3 Switch HDMI CEC/7J1 Header Pin11",
+			  "7J1 Header Pin13",
+			  /* GPIO_TEST_N */
+			  "7J1 Header Pin15";
+};
+
+&pinctrl_periphs {
+	gpio-line-names = /* Bank GPIOZ */
+			  "", "", "", "", "", "", "",
+			  "", "", "", "", "", "", "",
+			  "Eth Link LED", "Eth Activity LED",
+			  /* Bank GPIOH */
+			  "HDMI HPD", "HDMI SDA", "HDMI SCL",
+			  "HDMI_5V_EN", "9J1 Header Pin2",
+			  "Analog Audio Mute",
+			  "2J3 Header Pin6",
+			  "2J3 Header Pin5",
+			  "2J3 Header Pin4",
+			  "2J3 Header Pin3",
+			  /* Bank BOOT */
+			  "eMMC D0", "eMMC D1", "eMMC D2", "eMMC D3",
+			  "eMMC D4", "eMMC D5", "eMMC D6", "eMMC D7",
+			  "eMMC Clk", "eMMC Reset", "eMMC CMD",
+			  "ALT BOOT MODE", "", "", "", "eMMC Data Strobe",
+			  /* Bank CARD */
+			  "SDCard D1", "SDCard D0", "SDCard CLK", "SDCard CMD",
+			  "SDCard D3", "SDCard D2", "SDCard Det",
+			  /* Bank GPIODV */
+			  "", "", "", "", "", "", "", "", "", "", "", "",
+			  "", "", "", "", "", "", "", "", "", "", "", "",
+			  "Green LED", "VCCK Enable",
+			  "7J1 Header Pin27", "7J1 Header Pin28",
+			  "VCCK Regulator", "VDDEE Regulator",
+			  /* Bank GPIOX */
+			  "7J1 Header Pin22", "7J1 Header Pin26",
+			  "7J1 Header Pin36", "7J1 Header Pin38",
+			  "7J1 Header Pin40", "7J1 Header Pin37",
+			  "7J1 Header Pin33", "7J1 Header Pin35",
+			  "7J1 Header Pin19", "7J1 Header Pin21",
+			  "7J1 Header Pin24", "7J1 Header Pin23",
+			  "7J1 Header Pin8", "7J1 Header Pin10",
+			  "7J1 Header Pin16", "7J1 Header Pin18",
+			  "7J1 Header Pin32", "7J1 Header Pin29",
+			  "7J1 Header Pin31",
+			  /* Bank GPIOCLK */
+			  "7J1 Header Pin7", "";
+};
+
+&saradc {
+	status = "okay";
+	vref-supply = <&vddio_ao18>;
+};
+
 /* SD card */
 &sd_emmc_b {
 	status = "okay";
 	pinctrl-0 = <&sdcard_pins>;
-	pinctrl-names = "default";
+	pinctrl-1 = <&sdcard_clk_gate_pins>;
+	pinctrl-names = "default", "clk-gate";
 
 	bus-width = <4>;
 	cap-sd-highspeed;
+	sd-uhs-sdr12;
+	sd-uhs-sdr25;
+	sd-uhs-sdr50;
 	max-frequency = <100000000>;
 	disable-wp;
 
@@ -150,11 +250,13 @@
 /* eMMC */
 &sd_emmc_c {
 	status = "okay";
-	pinctrl-0 = <&emmc_pins>;
-	pinctrl-names = "default";
+	pinctrl-0 = <&emmc_pins>, <&emmc_ds_pins>;
+	pinctrl-1 = <&emmc_clk_gate_pins>;
+	pinctrl-names = "default", "clk-gate";
 
 	bus-width = <8>;
 	cap-mmc-highspeed;
+	mmc-ddr-3_3v;
 	max-frequency = <50000000>;
 	non-removable;
 	disable-wp;
diff --git a/arch/arm/dts/meson-gxl-s905x-p212.dts b/arch/arm/dts/meson-gxl-s905x-p212.dts
index 6ab17c1..6e2bf85 100644
--- a/arch/arm/dts/meson-gxl-s905x-p212.dts
+++ b/arch/arm/dts/meson-gxl-s905x-p212.dts
@@ -71,6 +71,13 @@
 	};
 };
 
+&cec_AO {
+	status = "okay";
+	pinctrl-0 = <&ao_cec_pins>;
+	pinctrl-names = "default";
+	hdmi-phandle = <&hdmi_tx>;
+};
+
 &cvbs_vdac_port {
 	cvbs_vdac_out: endpoint {
 		remote-endpoint = <&cvbs_connector_in>;
diff --git a/arch/arm/dts/meson-gxl-s905x-p212.dtsi b/arch/arm/dts/meson-gxl-s905x-p212.dtsi
index f3eea8e..7005068 100644
--- a/arch/arm/dts/meson-gxl-s905x-p212.dtsi
+++ b/arch/arm/dts/meson-gxl-s905x-p212.dtsi
@@ -28,6 +28,18 @@
 		reg = <0x0 0x0 0x0 0x80000000>;
 	};
 
+	hdmi_5v: regulator-hdmi-5v {
+		compatible = "regulator-fixed";
+
+		regulator-name = "HDMI_5V";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+
+		gpio = <&gpio GPIOH_3 GPIO_ACTIVE_HIGH>;
+		enable-active-high;
+		regulator-always-on;
+	};
+
 	vddio_boot: regulator-vddio_boot {
 		compatible = "regulator-fixed";
 		regulator-name = "VDDIO_BOOT";
@@ -95,7 +107,8 @@
 &sd_emmc_a {
 	status = "okay";
 	pinctrl-0 = <&sdio_pins>;
-	pinctrl-names = "default";
+	pinctrl-1 = <&sdio_clk_gate_pins>;
+	pinctrl-names = "default", "clk-gate";
 	#address-cells = <1>;
 	#size-cells = <0>;
 
@@ -116,7 +129,8 @@
 &sd_emmc_b {
 	status = "okay";
 	pinctrl-0 = <&sdcard_pins>;
-	pinctrl-names = "default";
+	pinctrl-1 = <&sdcard_clk_gate_pins>;
+	pinctrl-names = "default", "clk-gate";
 
 	bus-width = <4>;
 	cap-sd-highspeed;
@@ -133,11 +147,11 @@
 /* eMMC */
 &sd_emmc_c {
 	status = "okay";
-	pinctrl-0 = <&emmc_pins>;
-	pinctrl-names = "default";
+	pinctrl-0 = <&emmc_pins>, <&emmc_ds_pins>;
+	pinctrl-1 = <&emmc_clk_gate_pins>;
+	pinctrl-names = "default", "clk-gate";
 
 	bus-width = <8>;
-	cap-sd-highspeed;
 	cap-mmc-highspeed;
 	max-frequency = <200000000>;
 	non-removable;
diff --git a/arch/arm/dts/meson-gxl.dtsi b/arch/arm/dts/meson-gxl.dtsi
index 8d4f316..c851411 100644
--- a/arch/arm/dts/meson-gxl.dtsi
+++ b/arch/arm/dts/meson-gxl.dtsi
@@ -43,11 +43,20 @@
 
 #include "meson-gx.dtsi"
 #include <dt-bindings/clock/gxbb-clkc.h>
+#include <dt-bindings/clock/gxbb-aoclkc.h>
 #include <dt-bindings/gpio/meson-gxl-gpio.h>
 #include <dt-bindings/reset/amlogic,meson-gxbb-reset.h>
 
 / {
 	compatible = "amlogic,meson-gxl";
+
+	reserved-memory {
+		/* Alternate 3 MiB reserved for ARM Trusted Firmware (BL31) */
+		secmon_reserved_alt: secmon at 5000000 {
+			reg = <0x0 0x05000000 0x0 0x300000>;
+			no-map;
+		};
+	};
 };
 
 &ethmac {
@@ -207,6 +216,21 @@
 	};
 };
 
+&cec_AO {
+	clocks = <&clkc_AO CLKID_AO_CEC_32K>;
+	clock-names = "core";
+};
+
+&clkc_AO {
+	compatible = "amlogic,meson-gxl-aoclkc", "amlogic,meson-gx-aoclkc";
+};
+
+&gpio_intc {
+	compatible = "amlogic,meson-gpio-intc",
+		     "amlogic,meson-gxl-gpio-intc";
+	status = "okay";
+};
+
 &hdmi_tx {
 	compatible = "amlogic,meson-gxl-dw-hdmi", "amlogic,meson-gx-dw-hdmi";
 	resets = <&reset RESET_HDMITX_CAPB3>,
@@ -258,19 +282,36 @@
 			reg-names = "mux", "pull", "pull-enable", "gpio";
 			gpio-controller;
 			#gpio-cells = <2>;
-			gpio-ranges = <&pinctrl_periphs 0 10 101>;
+			gpio-ranges = <&pinctrl_periphs 0 0 100>;
 		};
 
 		emmc_pins: emmc {
 			mux {
 				groups = "emmc_nand_d07",
 				       "emmc_cmd",
-				       "emmc_clk",
-				       "emmc_ds";
+				       "emmc_clk";
 				function = "emmc";
 			};
 		};
 
+		emmc_ds_pins: emmc-ds {
+			mux {
+				groups = "emmc_ds";
+				function = "emmc";
+			};
+		};
+
+		emmc_clk_gate_pins: emmc_clk_gate {
+			mux {
+				groups = "BOOT_8";
+				function = "gpio_periphs";
+			};
+			cfg-pull-down {
+				pins = "BOOT_8";
+				bias-pull-down;
+			};
+		};
+
 		nor_pins: nor {
 			mux {
 				groups = "nor_d",
@@ -309,6 +350,17 @@
 			};
 		};
 
+		sdcard_clk_gate_pins: sdcard_clk_gate {
+			mux {
+				groups = "CARD_2";
+				function = "gpio_periphs";
+			};
+			cfg-pull-down {
+				pins = "CARD_2";
+				bias-pull-down;
+			};
+		};
+
 		sdio_pins: sdio {
 			mux {
 				groups = "sdio_d0",
@@ -321,6 +373,17 @@
 			};
 		};
 
+		sdio_clk_gate_pins: sdio_clk_gate {
+			mux {
+				groups = "GPIOX_4";
+				function = "gpio_periphs";
+			};
+			cfg-pull-down {
+				pins = "GPIOX_4";
+				bias-pull-down;
+			};
+		};
+
 		sdio_irq_pins: sdio_irq {
 			mux {
 				groups = "sdio_irq";
@@ -568,6 +631,7 @@
 
 			internal_phy: ethernet-phy at 8 {
 				compatible = "ethernet-phy-id0181.4400", "ethernet-phy-ieee802.3-c22";
+				interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
 				reg = <8>;
 				max-speed = <100>;
 			};
@@ -581,33 +645,74 @@
 	};
 };
 
+&pwrc_vpu {
+	resets = <&reset RESET_VIU>,
+		 <&reset RESET_VENC>,
+		 <&reset RESET_VCBUS>,
+		 <&reset RESET_BT656>,
+		 <&reset RESET_DVIN_RESET>,
+		 <&reset RESET_RDMA>,
+		 <&reset RESET_VENCI>,
+		 <&reset RESET_VENCP>,
+		 <&reset RESET_VDAC>,
+		 <&reset RESET_VDI6>,
+		 <&reset RESET_VENCL>,
+		 <&reset RESET_VID_LOCK>;
+	clocks = <&clkc CLKID_VPU>,
+	         <&clkc CLKID_VAPB>;
+	clock-names = "vpu", "vapb";
+	/*
+	 * VPU clocking is provided by two identical clock paths
+	 * VPU_0 and VPU_1 muxed to a single clock by a glitch
+	 * free mux to safely change frequency while running.
+	 * Same for VAPB but with a final gate after the glitch free mux.
+	 */
+	assigned-clocks = <&clkc CLKID_VPU_0_SEL>,
+			  <&clkc CLKID_VPU_0>,
+			  <&clkc CLKID_VPU>, /* Glitch free mux */
+			  <&clkc CLKID_VAPB_0_SEL>,
+			  <&clkc CLKID_VAPB_0>,
+			  <&clkc CLKID_VAPB_SEL>; /* Glitch free mux */
+	assigned-clock-parents = <&clkc CLKID_FCLK_DIV3>,
+				 <0>, /* Do Nothing */
+				 <&clkc CLKID_VPU_0>,
+				 <&clkc CLKID_FCLK_DIV4>,
+				 <0>, /* Do Nothing */
+				 <&clkc CLKID_VAPB_0>;
+	assigned-clock-rates = <0>, /* Do Nothing */
+			       <666666666>,
+			       <0>, /* Do Nothing */
+			       <0>, /* Do Nothing */
+			       <250000000>,
+			       <0>; /* Do Nothing */
+};
+
 &saradc {
 	compatible = "amlogic,meson-gxl-saradc", "amlogic,meson-saradc";
 	clocks = <&xtal>,
 		 <&clkc CLKID_SAR_ADC>,
-		 <&clkc CLKID_SANA>,
 		 <&clkc CLKID_SAR_ADC_CLK>,
 		 <&clkc CLKID_SAR_ADC_SEL>;
-	clock-names = "clkin", "core", "sana", "adc_clk", "adc_sel";
+	clock-names = "clkin", "core", "adc_clk", "adc_sel";
 };
 
 &sd_emmc_a {
 	clocks = <&clkc CLKID_SD_EMMC_A>,
-		 <&xtal>,
+		 <&clkc CLKID_SD_EMMC_A_CLK0>,
 		 <&clkc CLKID_FCLK_DIV2>;
 	clock-names = "core", "clkin0", "clkin1";
 };
 
 &sd_emmc_b {
 	clocks = <&clkc CLKID_SD_EMMC_B>,
-		 <&xtal>,
+		 <&clkc CLKID_SD_EMMC_B_CLK0>,
 		 <&clkc CLKID_FCLK_DIV2>;
        clock-names = "core", "clkin0", "clkin1";
 };
 
 &sd_emmc_c {
 	clocks = <&clkc CLKID_SD_EMMC_C>,
-		 <&xtal>,
+		 <&clkc CLKID_SD_EMMC_C_CLK0>,
 		 <&clkc CLKID_FCLK_DIV2>;
 	clock-names = "core", "clkin0", "clkin1";
 };
@@ -623,6 +728,32 @@
 	clocks = <&clkc CLKID_SPI>;
 };
 
+&uart_A {
+	clocks = <&xtal>, <&clkc CLKID_UART0>, <&xtal>;
+	clock-names = "xtal", "pclk", "baud";
+};
+
+&uart_AO {
+	clocks = <&xtal>, <&clkc CLKID_CLK81>, <&xtal>;
+	clock-names = "xtal", "pclk", "baud";
+};
+
+&uart_AO_B {
+	clocks = <&xtal>, <&clkc CLKID_CLK81>, <&xtal>;
+	clock-names = "xtal", "pclk", "baud";
+};
+
+&uart_B {
+	clocks = <&xtal>, <&clkc CLKID_UART1>, <&xtal>;
+	clock-names = "xtal", "pclk", "baud";
+};
+
+&uart_C {
+	clocks = <&xtal>, <&clkc CLKID_UART2>, <&xtal>;
+	clock-names = "xtal", "pclk", "baud";
+};
+
 &vpu {
 	compatible = "amlogic,meson-gxl-vpu", "amlogic,meson-gx-vpu";
+	power-domains = <&pwrc_vpu>;
 };
diff --git a/include/dt-bindings/clock/gxbb-aoclkc.h b/include/dt-bindings/clock/gxbb-aoclkc.h
index 3175148..9d15e22 100644
--- a/include/dt-bindings/clock/gxbb-aoclkc.h
+++ b/include/dt-bindings/clock/gxbb-aoclkc.h
@@ -62,5 +62,6 @@
 #define CLKID_AO_UART1		3
 #define CLKID_AO_UART2		4
 #define CLKID_AO_IR_BLASTER	5
+#define CLKID_AO_CEC_32K	6
 
 #endif
diff --git a/include/dt-bindings/clock/gxbb-clkc.h b/include/dt-bindings/clock/gxbb-clkc.h
index e3e9f79..8ba99a5 100644
--- a/include/dt-bindings/clock/gxbb-clkc.h
+++ b/include/dt-bindings/clock/gxbb-clkc.h
@@ -1,3 +1,4 @@
+/* SPDX-License-Identifier: GPL-2.0 */
 /*
  * GXBB clock tree IDs
  */
@@ -5,37 +6,96 @@
 #ifndef __GXBB_CLKC_H
 #define __GXBB_CLKC_H
 
+#define CLKID_SYS_PLL		0
 #define CLKID_HDMI_PLL		2
+#define CLKID_FIXED_PLL		3
 #define CLKID_FCLK_DIV2		4
 #define CLKID_FCLK_DIV3		5
 #define CLKID_FCLK_DIV4		6
+#define CLKID_FCLK_DIV5		7
+#define CLKID_FCLK_DIV7		8
 #define CLKID_GP0_PLL		9
 #define CLKID_CLK81		12
+#define CLKID_MPLL0		13
+#define CLKID_MPLL1		14
 #define CLKID_MPLL2		15
+#define CLKID_DDR		16
+#define CLKID_DOS		17
+#define CLKID_ISA		18
+#define CLKID_PL301		19
+#define CLKID_PERIPHS		20
 #define CLKID_SPICC		21
 #define CLKID_I2C		22
 #define CLKID_SAR_ADC		23
+#define CLKID_SMART_CARD	24
 #define CLKID_RNG0		25
 #define CLKID_UART0		26
+#define CLKID_SDHC		27
+#define CLKID_STREAM		28
+#define CLKID_ASYNC_FIFO	29
+#define CLKID_SDIO		30
+#define CLKID_ABUF		31
+#define CLKID_HIU_IFACE		32
+#define CLKID_ASSIST_MISC	33
 #define CLKID_SPI		34
 #define CLKID_ETH		36
+#define CLKID_I2S_SPDIF		35
+#define CLKID_DEMUX		37
 #define CLKID_AIU_GLUE		38
 #define CLKID_IEC958		39
 #define CLKID_I2S_OUT		40
+#define CLKID_AMCLK		41
+#define CLKID_AIFIFO2		42
+#define CLKID_MIXER		43
 #define CLKID_MIXER_IFACE	44
+#define CLKID_ADC		45
+#define CLKID_BLKMV		46
 #define CLKID_AIU		47
 #define CLKID_UART1		48
+#define CLKID_G2D		49
 #define CLKID_USB0		50
 #define CLKID_USB1		51
+#define CLKID_RESET		52
+#define CLKID_NAND		53
+#define CLKID_DOS_PARSER	54
 #define CLKID_USB		55
+#define CLKID_VDIN1		56
+#define CLKID_AHB_ARB0		57
+#define CLKID_EFUSE		58
+#define CLKID_BOOT_ROM		59
+#define CLKID_AHB_DATA_BUS	60
+#define CLKID_AHB_CTRL_BUS	61
+#define CLKID_HDMI_INTR_SYNC	62
 #define CLKID_HDMI_PCLK		63
 #define CLKID_USB1_DDR_BRIDGE	64
 #define CLKID_USB0_DDR_BRIDGE	65
+#define CLKID_MMC_PCLK		66
+#define CLKID_DVIN		67
 #define CLKID_UART2		68
 #define CLKID_SANA		69
+#define CLKID_VPU_INTR		70
+#define CLKID_SEC_AHB_AHB3_BRIDGE 71
+#define CLKID_CLK81_A53		72
+#define CLKID_VCLK2_VENCI0	73
+#define CLKID_VCLK2_VENCI1	74
+#define CLKID_VCLK2_VENCP0	75
+#define CLKID_VCLK2_VENCP1	76
 #define CLKID_GCLK_VENCI_INT0	77
+#define CLKID_GCLK_VENCI_INT	78
+#define CLKID_DAC_CLK		79
 #define CLKID_AOCLK_GATE	80
 #define CLKID_IEC958_GATE	81
+#define CLKID_ENC480P		82
+#define CLKID_RNG1		83
+#define CLKID_GCLK_VENCI_INT1	84
+#define CLKID_VCLK2_VENCLMCC	85
+#define CLKID_VCLK2_VENCL	86
+#define CLKID_VCLK_OTHER	87
+#define CLKID_EDP		88
+#define CLKID_AO_MEDIA_CPU	89
+#define CLKID_AO_AHB_SRAM	90
+#define CLKID_AO_AHB_BUS	91
+#define CLKID_AO_IFACE		92
 #define CLKID_AO_I2C		93
 #define CLKID_SD_EMMC_A		94
 #define CLKID_SD_EMMC_B		95
@@ -50,5 +110,20 @@
 #define CLKID_CTS_AMCLK		107
 #define CLKID_CTS_MCLK_I958	110
 #define CLKID_CTS_I958		113
+#define CLKID_32K_CLK		114
+#define CLKID_SD_EMMC_A_CLK0	119
+#define CLKID_SD_EMMC_B_CLK0	122
+#define CLKID_SD_EMMC_C_CLK0	125
+#define CLKID_VPU_0_SEL		126
+#define CLKID_VPU_0		128
+#define CLKID_VPU_1_SEL		129
+#define CLKID_VPU_1		131
+#define CLKID_VPU		132
+#define CLKID_VAPB_0_SEL	133
+#define CLKID_VAPB_0		135
+#define CLKID_VAPB_1_SEL	136
+#define CLKID_VAPB_1		138
+#define CLKID_VAPB_SEL		139
+#define CLKID_VAPB		140
 
 #endif /* __GXBB_CLKC_H */
diff --git a/include/dt-bindings/gpio/meson-gxbb-gpio.h b/include/dt-bindings/gpio/meson-gxbb-gpio.h
index 58654fd..43a68a1 100644
--- a/include/dt-bindings/gpio/meson-gxbb-gpio.h
+++ b/include/dt-bindings/gpio/meson-gxbb-gpio.h
@@ -29,6 +29,7 @@
 #define	GPIOAO_11	11
 #define	GPIOAO_12	12
 #define	GPIOAO_13	13
+#define	GPIO_TEST_N	14
 
 #define	GPIOZ_0		0
 #define	GPIOZ_1		1
@@ -149,6 +150,5 @@
 #define	GPIOCLK_1	116
 #define	GPIOCLK_2	117
 #define	GPIOCLK_3	118
-#define	GPIO_TEST_N	119
 
 #endif
diff --git a/include/dt-bindings/gpio/meson-gxl-gpio.h b/include/dt-bindings/gpio/meson-gxl-gpio.h
index 684d0d7..01f2a2a 100644
--- a/include/dt-bindings/gpio/meson-gxl-gpio.h
+++ b/include/dt-bindings/gpio/meson-gxl-gpio.h
@@ -25,6 +25,7 @@
 #define	GPIOAO_7	7
 #define	GPIOAO_8	8
 #define	GPIOAO_9	9
+#define	GPIO_TEST_N	10
 
 #define	GPIOZ_0		0
 #define	GPIOZ_1		1
@@ -126,6 +127,5 @@
 #define	GPIOX_18	97
 #define	GPIOCLK_0	98
 #define	GPIOCLK_1	99
-#define	GPIO_TEST_N	100
 
 #endif
-- 
2.7.4



From jjhiblot at ti.com  Wed Apr 11 08:49:14 2018
From: jjhiblot at ti.com (Jean-Jacques Hiblot)
Date: Wed, 11 Apr 2018 17:49:14 +0200
Subject: [U-Boot] [PATCH v2 u-boot 1/2] reset: Add
 get/assert/deassert/release for bulk of reset signals
In-Reply-To: <1522748451-21209-2-git-send-email-narmstrong@baylibre.com>
References: <1522748451-21209-1-git-send-email-narmstrong@baylibre.com>
 <1522748451-21209-2-git-send-email-narmstrong@baylibre.com>
Message-ID: <9998be38-4919-f857-f12e-ac6b77e6e6bf@ti.com>

Hi Neil,

while trying to test your patches on dwc3, I ran into a compilation issue.

On 03/04/2018 11:40, Neil Armstrong wrote:
> This patch adds a "bulk" API to the reset API in order to get/deassert/
> assert/release a group of reset signals associated with a device.
>
> This bulk API will avoid adding a copy of the same code to manage
> a group of reset signals in drivers.
>
> Signed-off-by: Neil Armstrong <narmstrong at baylibre.com>
> ---
>   drivers/reset/reset-uclass.c | 60 +++++++++++++++++++++++++++
>   include/reset.h              | 99 ++++++++++++++++++++++++++++++++++++++++++++
>   2 files changed, 159 insertions(+)
>
> diff --git a/drivers/reset/reset-uclass.c b/drivers/reset/reset-uclass.c
> index 307a297..9a5c9c9 100644
> --- a/drivers/reset/reset-uclass.c
> +++ b/drivers/reset/reset-uclass.c
> @@ -81,6 +81,40 @@ int reset_get_by_index(struct udevice *dev, int index,
>   	return 0;
>   }
>   
> +int reset_get_bulk(struct udevice *dev, struct reset_ctl_bulk *bulk)
> +{
> +	int i, ret, err, count;
> +	
> +	bulk->count = 0;
> +
> +	count = dev_count_phandle_with_args(dev, "resets", "#reset-cells");
> +	if (!count)
> +		return 0;
> +
> +	bulk->resets = devm_kcalloc(dev, count, sizeof(struct reset_ctl),
> +				    GFP_KERNEL);
> +	if (!bulk->resets)
> +		return -ENOMEM;
> +
> +	for (i = 0; i < count; i++) {
> +		ret = reset_get_by_index(dev, i, &bulk->resets[i]);
> +		if (ret < 0)
> +			goto bulk_get_err;
> +
> +		++bulk->count;
> +	}
> +
> +	return 0;
> +
> +bulk_get_err:
> +	err = reset_release_all(bulk->resets, bulk->count);
> +	if (err)
> +		debug("%s: could release all resets for %p\n",
> +		      __func__, dev);
> +
> +	return ret;
> +}
> +
>   int reset_get_by_name(struct udevice *dev, const char *name,
>   		     struct reset_ctl *reset_ctl)
>   {
> @@ -126,6 +160,19 @@ int reset_assert(struct reset_ctl *reset_ctl)
>   	return ops->rst_assert(reset_ctl);
>   }
>   
> +int reset_assert_bulk(struct reset_ctl_bulk *bulk)
> +{
> +	int i, ret;
> +
> +	for (i = 0; i < bulk->count; i++) {
> +		ret = reset_assert(&bulk->resets[i]);
> +		if (ret < 0)
> +			return ret;
> +	}
> +
> +	return 0;
> +}
> +
>   int reset_deassert(struct reset_ctl *reset_ctl)
>   {
>   	struct reset_ops *ops = reset_dev_ops(reset_ctl->dev);
> @@ -135,6 +182,19 @@ int reset_deassert(struct reset_ctl *reset_ctl)
>   	return ops->rst_deassert(reset_ctl);
>   }
>   
> +int reset_deassert_bulk(struct reset_ctl_bulk *bulk)
> +{
> +	int i, ret;
> +
> +	for (i = 0; i < bulk->count; i++) {
> +		ret = reset_deassert(&bulk->resets[i]);
> +		if (ret < 0)
> +			return ret;
> +	}
> +
> +	return 0;
> +}
> +
>   int reset_release_all(struct reset_ctl *reset_ctl, int count)
>   {
>   	int i, ret;
> diff --git a/include/reset.h b/include/reset.h
> index 7185ade..d38f176 100644
> --- a/include/reset.h
> +++ b/include/reset.h
> @@ -60,6 +60,24 @@ struct reset_ctl {
>   	unsigned long id;
>   };
>   
> +/**
> + * struct reset_ctl_bulk - A handle to (allowing control of) a bulk of reset
> + * signals.
> + *
> + * Clients provide storage for the reset control bulk. The content of the
> + * structure is managed solely by the reset API. A reset control bulk struct is
> + * initialized by "get"ing the reset control bulk struct.
> + * The reset control bulk struct is passed to all other bulk reset APIs to apply
> + * the API to all the reset signals in the bulk struct.
> + *
> + * @resets: An array of reset signal handles handles.
> + * @count: The number of reset signal handles in the reset array.
> + */
> +struct reset_ctl_bulk {
> +	struct reset_ctl *resets;
> +	unsigned int count;
> +};
> +
>   #ifdef CONFIG_DM_RESET
>   /**
>    * reset_get_by_index - Get/request a reset signal by integer index.
> @@ -81,6 +99,22 @@ int reset_get_by_index(struct udevice *dev, int index,
>   		       struct reset_ctl *reset_ctl);
>   
>   /**
> + * reset_get_bulk - Get/request all reset signals of a device.
> + *
> + * This looks up and requests all reset signals of the client device; each
> + * device is assumed to have n reset signals associated with it somehow,
> + * and this function finds and requests all of them in a separate structure.
> + * The mapping of client device reset signals indices to provider reset signals
> + * may be via device-tree properties, board-provided mapping tables, or some
> + * other mechanism.
> + *
> + * @dev:	The client device.
> + * @bulk	A pointer to a reset control bulk struct to initialize.
> + * @return 0 if OK, or a negative error code.
> + */
> +int reset_get_bulk(struct udevice *dev, struct reset_ctl_bulk *bulk);
> +
> +/**
>    * reset_get_by_name - Get/request a reset signal by name.
>    *
>    * This looks up and requests a reset signal. The name is relative to the
> @@ -132,6 +166,21 @@ int reset_free(struct reset_ctl *reset_ctl);
>   int reset_assert(struct reset_ctl *reset_ctl);
>   
>   /**
> + * reset_assert_bulk - Assert all reset signals in a reset control bulk struct.
> + *
> + * This function will assert the specified reset signals in a reset control
> + * bulk struct, thus resetting the affected HW module(s). Depending on the
> + * reset controller hardware, the reset signals will either stay asserted
> + * until reset_deassert_bulk() is called, or the hardware may autonomously
> + * clear the reset signals itself.
> + *
> + * @bulk:	A reset control bulk struct that was previously successfully
> + *		requested by reset_get_bulk().
> + * @return 0 if OK, or a negative error code.
> + */
> +int reset_assert_bulk(struct reset_ctl_bulk *bulk);
> +
> +/**
>    * reset_deassert - Deassert a reset signal.
>    *
>    * This function will deassert the specified reset signal, thus releasing the
> @@ -145,6 +194,20 @@ int reset_assert(struct reset_ctl *reset_ctl);
>   int reset_deassert(struct reset_ctl *reset_ctl);
>   
>   /**
> + * reset_deassert_bulk - Deassert all reset signals in a reset control bulk
> + * struct.
> + *
> + * This function will deassert the specified reset signals in a reset control
> + * bulk struct, thus releasing the affected HW modules() from reset, and
> + * allowing them to continue normal operation.
> + *
> + * @bulk:	A reset control bulk struct that was previously successfully
> + *		requested by reset_get_bulk().
> + * @return 0 if OK, or a negative error code.
> + */
> +int reset_deassert_bulk(struct reset_ctl_bulk *bulk);
> +
> +/**
>    * reset_release_all - Assert/Free an array of previously requested resets.
>    *
>    * For each reset contained in the reset array, this function will check if
> @@ -156,6 +219,23 @@ int reset_deassert(struct reset_ctl *reset_ctl);
>    * @return 0 if OK, or a negative error code.
>    */
>   int reset_release_all(struct reset_ctl *reset_ctl, int count);
> +
> +/**
> + * reset_release_bulk - Assert/Free an array of previously requested reset
> + * signals in a reset control bulk struct.
> + *
> + * For each reset contained in the reset control bulk struct, this function
> + * will check if reset has been previously requested and then will assert
> + * and free it.
> + *
> + * @bulk:	A reset control bulk struct that was previously successfully
> + *		requested by reset_get_bulk().
> + * @return 0 if OK, or a negative error code.
> + */
> +static inline int reset_release_bulk(struct reset_ctl_bulk *bulk)
> +{
> +	return reset_release_all(bulk->resets, bulk->count);
> +}
>   #else
>   static inline int reset_get_by_index(struct udevice *dev, int index,
>   				     struct reset_ctl *reset_ctl)
> @@ -163,6 +243,11 @@ static inline int reset_get_by_index(struct udevice *dev, int index,
>   	return -ENOTSUPP;
>   }
>   
> +static inline int reset_get_bulk(struct udevice *dev, struct clk_bulk *bulk)
Should be struct reset_ctl_bulk instead of struct clk_bulk
> +{
> +	return -ENOTSUPP;
> +}
> +
>   static inline int reset_get_by_name(struct udevice *dev, const char *name,
>   				    struct reset_ctl *reset_ctl)
>   {
> @@ -179,16 +264,30 @@ static inline int reset_assert(struct reset_ctl *reset_ctl)
>   	return 0;
>   }
>   
> +static inline int reset_assert_bulk(struct reset_ctl_bulk *bulk)
> +{
> +	return 0;
> +}
> +
>   static inline int reset_deassert(struct reset_ctl *reset_ctl)
>   {
>   	return 0;
>   }
>   
> +static inline int reset_deassert_bulk(struct reset_ctl_bulk *bulk)
> +{
> +	return 0;
> +}
> +
>   static inline int reset_release_all(struct reset_ctl *reset_ctl, int count)
>   {
>   	return 0;
>   }
>   
> +static inline int reset_release_bulk(struct clk_bulk *bulk)
ditto.

Jean-Jacques
> +{
> +	return 0;
> +}
>   #endif
>   
>   #endif



From narmstrong at baylibre.com  Wed Apr 11 08:40:41 2018
From: narmstrong at baylibre.com (Neil Armstrong)
Date: Wed, 11 Apr 2018 17:40:41 +0200
Subject: [PATCH u-boot 2/2] pinctrl: meson: Update pinmux with new Linux
 bindings
In-Reply-To: <1523461241-30436-1-git-send-email-narmstrong@baylibre.com>
References: <1523461241-30436-1-git-send-email-narmstrong@baylibre.com>
Message-ID: <1523461241-30436-3-git-send-email-narmstrong@baylibre.com>

The pinctrl bindings has changed for Amlogic Meson SoCs since Linux 4.13,
update the pinctrl driver to take this in account.

Signed-off-by: Neil Armstrong <narmstrong at baylibre.com>
---
 drivers/pinctrl/meson/pinctrl-meson-gxbb.c | 12 ++++++------
 drivers/pinctrl/meson/pinctrl-meson-gxl.c  | 14 +++++++-------
 2 files changed, 13 insertions(+), 13 deletions(-)

diff --git a/drivers/pinctrl/meson/pinctrl-meson-gxbb.c b/drivers/pinctrl/meson/pinctrl-meson-gxbb.c
index 87c9912..928356f 100644
--- a/drivers/pinctrl/meson/pinctrl-meson-gxbb.c
+++ b/drivers/pinctrl/meson/pinctrl-meson-gxbb.c
@@ -14,7 +14,7 @@
 
 #include "pinctrl-meson.h"
 
-#define EE_OFF	14
+#define EE_OFF	15
 
 static const unsigned int emmc_nand_d07_pins[] = {
 	PIN(BOOT_0, EE_OFF), PIN(BOOT_1, EE_OFF), PIN(BOOT_2, EE_OFF),
@@ -319,8 +319,6 @@ static const char * const gpio_periphs_groups[] = {
 	"GPIOX_10", "GPIOX_11", "GPIOX_12", "GPIOX_13", "GPIOX_14",
 	"GPIOX_15", "GPIOX_16", "GPIOX_17", "GPIOX_18", "GPIOX_19",
 	"GPIOX_20", "GPIOX_21", "GPIOX_22",
-
-	"GPIO_TEST_N",
 };
 
 static const char * const emmc_groups[] = {
@@ -355,6 +353,8 @@ static const char * const gpio_aobus_groups[] = {
 	"GPIOAO_0", "GPIOAO_1", "GPIOAO_2", "GPIOAO_3", "GPIOAO_4",
 	"GPIOAO_5", "GPIOAO_6", "GPIOAO_7", "GPIOAO_8", "GPIOAO_9",
 	"GPIOAO_10", "GPIOAO_11", "GPIOAO_12", "GPIOAO_13",
+
+	"GPIO_TEST_N",
 };
 
 static const char * const uart_ao_groups[] = {
@@ -410,11 +410,11 @@ static struct meson_bank meson_gxbb_aobus_banks[] = {
 
 struct meson_pinctrl_data meson_gxbb_periphs_pinctrl_data = {
 	.name		= "periphs-banks",
-	.pin_base	= 14,
+	.pin_base	= 15,
 	.groups		= meson_gxbb_periphs_groups,
 	.funcs		= meson_gxbb_periphs_functions,
 	.banks		= meson_gxbb_periphs_banks,
-	.num_pins	= 120,
+	.num_pins	= 119,
 	.num_groups	= ARRAY_SIZE(meson_gxbb_periphs_groups),
 	.num_funcs	= ARRAY_SIZE(meson_gxbb_periphs_functions),
 	.num_banks	= ARRAY_SIZE(meson_gxbb_periphs_banks),
@@ -426,7 +426,7 @@ struct meson_pinctrl_data meson_gxbb_aobus_pinctrl_data = {
 	.groups		= meson_gxbb_aobus_groups,
 	.funcs		= meson_gxbb_aobus_functions,
 	.banks		= meson_gxbb_aobus_banks,
-	.num_pins	= 14,
+	.num_pins	= 15,
 	.num_groups	= ARRAY_SIZE(meson_gxbb_aobus_groups),
 	.num_funcs	= ARRAY_SIZE(meson_gxbb_aobus_functions),
 	.num_banks	= ARRAY_SIZE(meson_gxbb_aobus_banks),
diff --git a/drivers/pinctrl/meson/pinctrl-meson-gxl.c b/drivers/pinctrl/meson/pinctrl-meson-gxl.c
index eebfaa9..fdc379b 100644
--- a/drivers/pinctrl/meson/pinctrl-meson-gxl.c
+++ b/drivers/pinctrl/meson/pinctrl-meson-gxl.c
@@ -14,7 +14,7 @@
 
 #include "pinctrl-meson.h"
 
-#define EE_OFF	10
+#define EE_OFF	11
 
 static const unsigned int emmc_nand_d07_pins[] = {
 	PIN(BOOT_0, EE_OFF), PIN(BOOT_1, EE_OFF), PIN(BOOT_2, EE_OFF),
@@ -290,7 +290,7 @@ static struct meson_pmx_group meson_gxl_periphs_groups[] = {
 	GPIO_GROUP(GPIOCLK_0, EE_OFF),
 	GPIO_GROUP(GPIOCLK_1, EE_OFF),
 
-	GPIO_GROUP(GPIO_TEST_N, EE_OFF),
+	GPIO_GROUP(GPIO_TEST_N, 0),
 
 	/* Bank X */
 	GROUP(sdio_d0,		5,	31),
@@ -472,8 +472,6 @@ static const char * const gpio_periphs_groups[] = {
 	"GPIOX_5", "GPIOX_6", "GPIOX_7", "GPIOX_8", "GPIOX_9",
 	"GPIOX_10", "GPIOX_11", "GPIOX_12", "GPIOX_13", "GPIOX_14",
 	"GPIOX_15", "GPIOX_16", "GPIOX_17", "GPIOX_18",
-
-	"GPIO_TEST_N",
 };
 
 static const char * const emmc_groups[] = {
@@ -588,6 +586,8 @@ static const char * const tsin_a_groups[] = {
 static const char * const gpio_aobus_groups[] = {
 	"GPIOAO_0", "GPIOAO_1", "GPIOAO_2", "GPIOAO_3", "GPIOAO_4",
 	"GPIOAO_5", "GPIOAO_6", "GPIOAO_7", "GPIOAO_8", "GPIOAO_9",
+
+	"GPIO_TEST_N",
 };
 
 static const char * const uart_ao_groups[] = {
@@ -692,11 +692,11 @@ static struct meson_bank meson_gxl_aobus_banks[] = {
 
 struct meson_pinctrl_data meson_gxl_periphs_pinctrl_data = {
 	.name		= "periphs-banks",
-	.pin_base	= 10,
+	.pin_base	= 11,
 	.groups		= meson_gxl_periphs_groups,
 	.funcs		= meson_gxl_periphs_functions,
 	.banks		= meson_gxl_periphs_banks,
-	.num_pins	= 101,
+	.num_pins	= 100,
 	.num_groups	= ARRAY_SIZE(meson_gxl_periphs_groups),
 	.num_funcs	= ARRAY_SIZE(meson_gxl_periphs_functions),
 	.num_banks	= ARRAY_SIZE(meson_gxl_periphs_banks),
@@ -708,7 +708,7 @@ struct meson_pinctrl_data meson_gxl_aobus_pinctrl_data = {
 	.groups		= meson_gxl_aobus_groups,
 	.funcs		= meson_gxl_aobus_functions,
 	.banks		= meson_gxl_aobus_banks,
-	.num_pins	= 10,
+	.num_pins	= 11,
 	.num_groups	= ARRAY_SIZE(meson_gxl_aobus_groups),
 	.num_funcs	= ARRAY_SIZE(meson_gxl_aobus_functions),
 	.num_banks	= ARRAY_SIZE(meson_gxl_aobus_banks),
-- 
2.7.4



From jjhiblot at ti.com  Wed Apr 11 09:17:51 2018
From: jjhiblot at ti.com (Jean-Jacques Hiblot)
Date: Wed, 11 Apr 2018 18:17:51 +0200
Subject: [U-Boot] [PATCH v3 u-boot 1/3] usb: host: Add simple of glue
 driver for DWC3 USB Controllers integration
In-Reply-To: <1523459282-12235-2-git-send-email-narmstrong@baylibre.com>
References: <1523459282-12235-1-git-send-email-narmstrong@baylibre.com>
 <1523459282-12235-2-git-send-email-narmstrong@baylibre.com>
Message-ID: <75bafa27-9f08-7d3d-91a2-6b2878df16ae@ti.com>



On 11/04/2018 17:08, Neil Armstrong wrote:
> This is a port of the dwc3-of-simple driver from Linux to enable/deassert
> clock and resets of a simple DWC3 Controller HW glue.
>
> Signed-off-by: Neil Armstrong <narmstrong at baylibre.com>
> ---
>   drivers/usb/host/Kconfig          |   7 +++
>   drivers/usb/host/Makefile         |   1 +
>   drivers/usb/host/dwc3-of-simple.c | 109 ++++++++++++++++++++++++++++++++++++++
>   3 files changed, 117 insertions(+)
>   create mode 100644 drivers/usb/host/dwc3-of-simple.c
>
> diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig
> index a7249b7..6caa615 100644
> --- a/drivers/usb/host/Kconfig
> +++ b/drivers/usb/host/Kconfig
> @@ -21,6 +21,13 @@ config USB_XHCI_DWC3
>   	  Say Y or if your system has a Dual Role SuperSpeed
>   	  USB controller based on the DesignWare USB3 IP Core.
>   
> +config USB_XHCI_DWC3_OF_SIMPLE
> +	bool "DesignWare USB3 DRD Generic OF Simple Glue Layer"
> +	select MISC
> +	help
> +	  Support USB2/3 functionality in simple SoC integrations with
> +	  USB controller based on the DesignWare USB3 IP Core.
> +
>   config USB_XHCI_MVEBU
>   	bool "MVEBU USB 3.0 support"
>   	default y
> diff --git a/drivers/usb/host/Makefile b/drivers/usb/host/Makefile
> index 9819489..abe4f90 100644
> --- a/drivers/usb/host/Makefile
> +++ b/drivers/usb/host/Makefile
> @@ -49,6 +49,7 @@ obj-$(CONFIG_USB_EHCI_ZYNQ) += ehci-zynq.o
>   # xhci
>   obj-$(CONFIG_USB_XHCI_HCD) += xhci.o xhci-mem.o xhci-ring.o
>   obj-$(CONFIG_USB_XHCI_DWC3) += xhci-dwc3.o
> +obj-$(CONFIG_USB_XHCI_DWC3_OF_SIMPLE) += dwc3-of-simple.o
>   obj-$(CONFIG_USB_XHCI_ROCKCHIP) += xhci-rockchip.o
>   obj-$(CONFIG_USB_XHCI_ZYNQMP) += xhci-zynqmp.o
>   obj-$(CONFIG_USB_XHCI_KEYSTONE) += xhci-keystone.o
> diff --git a/drivers/usb/host/dwc3-of-simple.c b/drivers/usb/host/dwc3-of-simple.c
> new file mode 100644
> index 0000000..54a5f60
> --- /dev/null
> +++ b/drivers/usb/host/dwc3-of-simple.c
> @@ -0,0 +1,109 @@
> +/*
> + * dwc3-of-simple.c - OF glue layer for simple integrations
> + *
> + * Copyright (c) 2015 Texas Instruments Incorporated - http://www.ti.com
> + *
> + * Author: Felipe Balbi <balbi at ti.com>
> + *
> + * Copyright (C) 2018 BayLibre, SAS
> + * Author: Neil Armstrong <narmstron at baylibre.com>
> + *
> + * SPDX-License-Identifier:     GPL-2.0+
> + */
> +
> +#include <common.h>
> +#include <dm.h>
> +#include <fdtdec.h>
> +#include <reset.h>
> +#include <clk.h>
> +
> +DECLARE_GLOBAL_DATA_PTR;
> +
> +struct dwc3_of_simple {
> +	struct clk_bulk		clks;
> +	struct reset_ctl_bulk	resets;
> +};
> +
> +static int dwc3_of_simple_reset_init(struct udevice *dev,
> +				     struct dwc3_of_simple *simple)
> +{
> +	int ret;
> +
> +	ret = reset_get_bulk(dev, &simple->resets);
> +	if (ret == -ENOTSUPP)
> +		return 0;
> +	else if (ret)
> +		return ret;
> +
> +	ret = reset_deassert_bulk(&simple->resets);
> +	if (ret) {
> +		reset_release_bulk(&simple->resets);
> +		return ret;
> +	}
> +
> +	return 0;
> +}
> +
> +static int dwc3_of_simple_clk_init(struct udevice *dev,
> +				   struct dwc3_of_simple *simple)
> +{
> +	int ret;
> +
> +	ret = clk_get_bulk(dev, &simple->clks);
> +	if (ret == -ENOTSUPP)

Must be ENOSYS instead of ENOTSUPP, otherwise probe fails on platform not using the clk framework

tested-by: Jean-Jacques hiblot <jjhiblot at ti.com>

> +		return 0;
> +	if (ret)
> +		return ret;
> +
> +#if CONFIG_IS_ENABLED(CLK)
> +	ret = clk_enable_bulk(&simple->clks);
> +	if (ret) {
> +		clk_release_bulk(&simple->clks);
> +		return ret;
> +	}
> +#endif
> +
> +	return 0;
> +}
> +
> +static int dwc3_of_simple_probe(struct udevice *dev)
> +{
> +	struct dwc3_of_simple *simple = dev_get_platdata(dev);
> +	int ret;
> +
> +	ret = dwc3_of_simple_clk_init(dev, simple);
> +	if (ret)
> +		return ret;
> +
> +	ret = dwc3_of_simple_reset_init(dev, simple);
> +	if (ret)
> +		return ret;
> +
> +	return 0;
> +}
> +
> +static int dwc3_of_simple_remove(struct udevice *dev)
> +{
> +	struct dwc3_of_simple *simple = dev_get_platdata(dev);
> +
> +	reset_release_bulk(&simple->resets);
> +
> +	clk_release_bulk(&simple->clks);
> +
> +	return dm_scan_fdt_dev(dev);
> +}
> +
> +static const struct udevice_id dwc3_of_simple_ids[] = {
> +	{ .compatible = "amlogic,meson-gxl-dwc3" },
> +	{ }
> +};
> +
> +U_BOOT_DRIVER(dwc3_of_simple) = {
> +	.name = "dwc3-of-simple",
> +	.id = UCLASS_SIMPLE_BUS,
> +	.of_match = dwc3_of_simple_ids,
> +	.probe = dwc3_of_simple_probe,
> +	.remove = dwc3_of_simple_remove,
> +	.platdata_auto_alloc_size = sizeof(struct dwc3_of_simple),
> +	.flags = DM_FLAG_ALLOC_PRIV_DMA,
> +};



From narmstrong at baylibre.com  Thu Apr 12 01:03:19 2018
From: narmstrong at baylibre.com (Neil Armstrong)
Date: Thu, 12 Apr 2018 10:03:19 +0200
Subject: [PATCH] reset: fix bulk API when DM_RESET is disabled
Message-ID: <1523520199-12341-1-git-send-email-narmstrong@baylibre.com>

In the commit "reset: Add get/assert/deassert/release for bulk of reset signals"
the disabled reset_release_bulk() and reset_get_bulk() used the wrong
struct clk_bulk instead of struct reset_ctl_bulk.

Fixes: 0c28233903b5 ("reset: Add get/assert/deassert/release for bulk of reset signals")
Reported-by: Jean-Jacques Hiblot <jjhiblot at ti.com>
Signed-off-by: Neil Armstrong <narmstrong at baylibre.com>
---
 include/reset.h | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/include/reset.h b/include/reset.h
index d38f176..ae247ce 100644
--- a/include/reset.h
+++ b/include/reset.h
@@ -243,7 +243,8 @@ static inline int reset_get_by_index(struct udevice *dev, int index,
 	return -ENOTSUPP;
 }
 
-static inline int reset_get_bulk(struct udevice *dev, struct clk_bulk *bulk)
+static inline int reset_get_bulk(struct udevice *dev,
+				 struct reset_ctl_bulk *bulk)
 {
 	return -ENOTSUPP;
 }
@@ -284,7 +285,7 @@ static inline int reset_release_all(struct reset_ctl *reset_ctl, int count)
 	return 0;
 }
 
-static inline int reset_release_bulk(struct clk_bulk *bulk)
+static inline int reset_release_bulk(struct reset_ctl_bulk *bulk)
 {
 	return 0;
 }
-- 
2.7.4



From narmstrong at baylibre.com  Thu Apr 12 01:05:50 2018
From: narmstrong at baylibre.com (Neil Armstrong)
Date: Thu, 12 Apr 2018 10:05:50 +0200
Subject: [U-Boot] [PATCH v3 u-boot 1/3] usb: host: Add simple of glue
 driver for DWC3 USB Controllers integration
In-Reply-To: <75bafa27-9f08-7d3d-91a2-6b2878df16ae@ti.com>
References: <1523459282-12235-1-git-send-email-narmstrong@baylibre.com>
 <1523459282-12235-2-git-send-email-narmstrong@baylibre.com>
 <75bafa27-9f08-7d3d-91a2-6b2878df16ae@ti.com>
Message-ID: <873d3df8-787e-27ec-3d66-73d723ee7ddb@baylibre.com>

Hi Jean-Jacques,

On 11/04/2018 18:17, Jean-Jacques Hiblot wrote:
> 
> 
> On 11/04/2018 17:08, Neil Armstrong wrote:
>> This is a port of the dwc3-of-simple driver from Linux to enable/deassert
>> clock and resets of a simple DWC3 Controller HW glue.
>>
>> Signed-off-by: Neil Armstrong <narmstrong at baylibre.com>
>> ---
>> ? drivers/usb/host/Kconfig????????? |?? 7 +++
>> ? drivers/usb/host/Makefile???????? |?? 1 +
>> ? drivers/usb/host/dwc3-of-simple.c | 109 ++++++++++++++++++++++++++++++++++++++
>> ? 3 files changed, 117 insertions(+)
>> ? create mode 100644 drivers/usb/host/dwc3-of-simple.c
>>
>> diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig
>> index a7249b7..6caa615 100644
>> --- a/drivers/usb/host/Kconfig
>> +++ b/drivers/usb/host/Kconfig
>> @@ -21,6 +21,13 @@ config USB_XHCI_DWC3
[...]

>> +
>> +static int dwc3_of_simple_clk_init(struct udevice *dev,
>> +?????????????????? struct dwc3_of_simple *simple)
>> +{
>> +??? int ret;
>> +
>> +??? ret = clk_get_bulk(dev, &simple->clks);
>> +??? if (ret == -ENOTSUPP)
> 
> Must be ENOSYS instead of ENOTSUPP, otherwise probe fails on platform not using the clk framework

You are right, I naively used the same between reset and clock...

> 
> tested-by: Jean-Jacques hiblot <jjhiblot at ti.com>
> 
>> +??????? return 0;
>> +??? if (ret)
>> +??????? return ret;
>> +
>> +#if CONFIG_IS_ENABLED(CLK)
>> +??? ret = clk_enable_bulk(&simple->clks);
>> +??? if (ret) {
>> +??????? clk_release_bulk(&simple->clks);
>> +??????? return ret;
>> +??? }
>> +#endif
>> +
>> +??? return 0;
>> +}

[...]
Thanks,
Neil


From ben.dooks at codethink.co.uk  Thu Apr 12 01:07:40 2018
From: ben.dooks at codethink.co.uk (Ben Dooks)
Date: Thu, 12 Apr 2018 09:07:40 +0100
Subject: [U-Boot] [PATCH v3 u-boot 1/3] usb: host: Add simple of glue
 driver for DWC3 USB Controllers integration
In-Reply-To: <873d3df8-787e-27ec-3d66-73d723ee7ddb@baylibre.com>
References: <1523459282-12235-1-git-send-email-narmstrong@baylibre.com>
 <1523459282-12235-2-git-send-email-narmstrong@baylibre.com>
 <75bafa27-9f08-7d3d-91a2-6b2878df16ae@ti.com>
 <873d3df8-787e-27ec-3d66-73d723ee7ddb@baylibre.com>
Message-ID: <f4963195-8279-a22d-9a9f-6ee6fa740bc7@codethink.co.uk>

On 12/04/18 09:05, Neil Armstrong wrote:
> Hi Jean-Jacques,
> 
> On 11/04/2018 18:17, Jean-Jacques Hiblot wrote:
>>
>>
>> On 11/04/2018 17:08, Neil Armstrong wrote:
>>> This is a port of the dwc3-of-simple driver from Linux to enable/deassert
>>> clock and resets of a simple DWC3 Controller HW glue.
>>>
>>> Signed-off-by: Neil Armstrong <narmstrong at baylibre.com>
>>> ---
>>>  ? drivers/usb/host/Kconfig????????? |?? 7 +++
>>>  ? drivers/usb/host/Makefile???????? |?? 1 +
>>>  ? drivers/usb/host/dwc3-of-simple.c | 109 ++++++++++++++++++++++++++++++++++++++
>>>  ? 3 files changed, 117 insertions(+)
>>>  ? create mode 100644 drivers/usb/host/dwc3-of-simple.c
>>>
>>> diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig
>>> index a7249b7..6caa615 100644
>>> --- a/drivers/usb/host/Kconfig
>>> +++ b/drivers/usb/host/Kconfig
>>> @@ -21,6 +21,13 @@ config USB_XHCI_DWC3
> [...]
> 
>>> +
>>> +static int dwc3_of_simple_clk_init(struct udevice *dev,
>>> +?????????????????? struct dwc3_of_simple *simple)
>>> +{
>>> +??? int ret;
>>> +
>>> +??? ret = clk_get_bulk(dev, &simple->clks);
>>> +??? if (ret == -ENOTSUPP)
>>
>> Must be ENOSYS instead of ENOTSUPP, otherwise probe fails on platform not using the clk framework
> 
> You are right, I naively used the same between reset and clock...
> 
>>
>> tested-by: Jean-Jacques hiblot <jjhiblot at ti.com>
>>
>>> +??????? return 0;
>>> +??? if (ret)
>>> +??????? return ret;
>>> +
>>> +#if CONFIG_IS_ENABLED(CLK)
>>> +??? ret = clk_enable_bulk(&simple->clks);
>>> +??? if (ret) {
>>> +??????? clk_release_bulk(&simple->clks);
>>> +??????? return ret;
>>> +??? }
>>> +#endif
>>> +
>>> +??? return 0;
>>> +}

Is the above #if CONFIG_IS_ENABLED(CLK) avoidable?

> 
> [...]
> Thanks,
> Neil
> 
> _______________________________________________
> linux-amlogic mailing list
> linux-amlogic at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-amlogic
> 


-- 
Ben Dooks				http://www.codethink.co.uk/
Senior Engineer				Codethink - Providing Genius


From narmstrong at baylibre.com  Thu Apr 12 01:08:17 2018
From: narmstrong at baylibre.com (Neil Armstrong)
Date: Thu, 12 Apr 2018 10:08:17 +0200
Subject: [U-Boot] [PATCH v3 u-boot 1/3] usb: host: Add simple of glue
 driver for DWC3 USB Controllers integration
In-Reply-To: <f4963195-8279-a22d-9a9f-6ee6fa740bc7@codethink.co.uk>
References: <1523459282-12235-1-git-send-email-narmstrong@baylibre.com>
 <1523459282-12235-2-git-send-email-narmstrong@baylibre.com>
 <75bafa27-9f08-7d3d-91a2-6b2878df16ae@ti.com>
 <873d3df8-787e-27ec-3d66-73d723ee7ddb@baylibre.com>
 <f4963195-8279-a22d-9a9f-6ee6fa740bc7@codethink.co.uk>
Message-ID: <80253c6e-862d-fada-6be2-07500e5a7653@baylibre.com>

On 12/04/2018 10:07, Ben Dooks wrote:
> On 12/04/18 09:05, Neil Armstrong wrote:
>> Hi Jean-Jacques,
>>
>> On 11/04/2018 18:17, Jean-Jacques Hiblot wrote:
>>>
>>>
>>> On 11/04/2018 17:08, Neil Armstrong wrote:
>>>> This is a port of the dwc3-of-simple driver from Linux to enable/deassert
>>>> clock and resets of a simple DWC3 Controller HW glue.
>>>>
>>>> Signed-off-by: Neil Armstrong <narmstrong at baylibre.com>
>>>> ---
>>>> ?? drivers/usb/host/Kconfig????????? |?? 7 +++
>>>> ?? drivers/usb/host/Makefile???????? |?? 1 +
>>>> ?? drivers/usb/host/dwc3-of-simple.c | 109 ++++++++++++++++++++++++++++++++++++++
>>>> ?? 3 files changed, 117 insertions(+)
>>>> ?? create mode 100644 drivers/usb/host/dwc3-of-simple.c
>>>>
>>>> diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig
>>>> index a7249b7..6caa615 100644
>>>> --- a/drivers/usb/host/Kconfig
>>>> +++ b/drivers/usb/host/Kconfig
>>>> @@ -21,6 +21,13 @@ config USB_XHCI_DWC3
>> [...]
>>
>>>> +
>>>> +static int dwc3_of_simple_clk_init(struct udevice *dev,
>>>> +?????????????????? struct dwc3_of_simple *simple)
>>>> +{
>>>> +??? int ret;
>>>> +
>>>> +??? ret = clk_get_bulk(dev, &simple->clks);
>>>> +??? if (ret == -ENOTSUPP)
>>>
>>> Must be ENOSYS instead of ENOTSUPP, otherwise probe fails on platform not using the clk framework
>>
>> You are right, I naively used the same between reset and clock...
>>
>>>
>>> tested-by: Jean-Jacques hiblot <jjhiblot at ti.com>
>>>
>>>> +??????? return 0;
>>>> +??? if (ret)
>>>> +??????? return ret;
>>>> +
>>>> +#if CONFIG_IS_ENABLED(CLK)
>>>> +??? ret = clk_enable_bulk(&simple->clks);
>>>> +??? if (ret) {
>>>> +??????? clk_release_bulk(&simple->clks);
>>>> +??????? return ret;
>>>> +??? }
>>>> +#endif
>>>> +
>>>> +??? return 0;
>>>> +}
> 
> Is the above #if CONFIG_IS_ENABLED(CLK) avoidable?

No unless some changes in clk.h

Neil

> 
>>
>> [...]
>> Thanks,
>> Neil
>>
>> _______________________________________________
>> linux-amlogic mailing list
>> linux-amlogic at lists.infradead.org
>> http://lists.infradead.org/mailman/listinfo/linux-amlogic
>>
> 
> 



From narmstrong at baylibre.com  Thu Apr 12 01:13:50 2018
From: narmstrong at baylibre.com (Neil Armstrong)
Date: Thu, 12 Apr 2018 10:13:50 +0200
Subject: [PATCH] usb: dwc3-of-simple: fix error check of clk_get_bulk when
 disabled
Message-ID: <1523520830-13468-1-git-send-email-narmstrong@baylibre.com>

The disabled clk API returns -ENOSYS unlike the reset API returning -ENOTSUPP.

Fixes: ca7fdc8b1267 ("usb: host: Add simple of glue driver for DWC3 USB Controllers integration")
Reported-by: Jean-Jacques Hiblot <jjhiblot at ti.com>
Signed-off-by: Neil Armstrong <narmstrong at baylibre.com>
---
 drivers/usb/host/dwc3-of-simple.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/usb/host/dwc3-of-simple.c b/drivers/usb/host/dwc3-of-simple.c
index 54a5f60..1f08208 100644
--- a/drivers/usb/host/dwc3-of-simple.c
+++ b/drivers/usb/host/dwc3-of-simple.c
@@ -50,7 +50,7 @@ static int dwc3_of_simple_clk_init(struct udevice *dev,
 	int ret;
 
 	ret = clk_get_bulk(dev, &simple->clks);
-	if (ret == -ENOTSUPP)
+	if (ret == -ENOSYS)
 		return 0;
 	if (ret)
 		return ret;
-- 
2.7.4



From narmstrong at baylibre.com  Thu Apr 12 01:14:57 2018
From: narmstrong at baylibre.com (Neil Armstrong)
Date: Thu, 12 Apr 2018 10:14:57 +0200
Subject: [U-Boot] [PATCH v2 u-boot 1/2] reset: Add
 get/assert/deassert/release for bulk of reset signals
In-Reply-To: <9998be38-4919-f857-f12e-ac6b77e6e6bf@ti.com>
References: <1522748451-21209-1-git-send-email-narmstrong@baylibre.com>
 <1522748451-21209-2-git-send-email-narmstrong@baylibre.com>
 <9998be38-4919-f857-f12e-ac6b77e6e6bf@ti.com>
Message-ID: <b1c6ae2c-c948-f309-7b11-368973a4249b@baylibre.com>

On 11/04/2018 17:49, Jean-Jacques Hiblot wrote:
> Hi Neil,
> 
> while trying to test your patches on dwc3, I ran into a compilation issue.
> 
> On 03/04/2018 11:40, Neil Armstrong wrote:
>> This patch adds a "bulk" API to the reset API in order to get/deassert/
>> assert/release a group of reset signals associated with a device.
>>
>> This bulk API will avoid adding a copy of the same code to manage
>> a group of reset signals in drivers.
>>
>> Signed-off-by: Neil Armstrong <narmstrong at baylibre.com>
>> ---
>> ? drivers/reset/reset-uclass.c | 60 +++++++++++++++++++++++++++
>> ? include/reset.h????????????? | 99 ++++++++++++++++++++++++++++++++++++++++++++
>> ? 2 files changed, 159 insertions(+)
>>
>> diff --git a/drivers/reset/reset-uclass.c b/drivers/reset/reset-uclass.c
>> index 307a297..9a5c9c9 100644
>> --- a/drivers/reset/reset-uclass.c
>> +++ b/drivers/reset/reset-uclass.c
>> @@ -81,6 +81,40 @@ int reset_get_by_index(struct udevice *dev, int index,
>> ????? return 0;
>> ? }
>> ? +int reset_get_bulk(struct udevice *dev, struct reset_ctl_bulk *bulk)
>> +{
>> +??? int i, ret, err, count;
>> +???
>> +??? bulk->count = 0;
>> +
>> +??? count = dev_count_phandle_with_args(dev, "resets", "#reset-cells");
>> +??? if (!count)
>> +??????? return 0;
>> +
>> +??? bulk->resets = devm_kcalloc(dev, count, sizeof(struct reset_ctl),
>> +??????????????????? GFP_KERNEL);
>> +??? if (!bulk->resets)
>> +??????? return -ENOMEM;
>> +
>> +??? for (i = 0; i < count; i++) {
>> +??????? ret = reset_get_by_index(dev, i, &bulk->resets[i]);
>> +??????? if (ret < 0)
>> +??????????? goto bulk_get_err;
>> +
>> +??????? ++bulk->count;
>> +??? }
>> +
>> +??? return 0;
>> +
>> +bulk_get_err:
>> +??? err = reset_release_all(bulk->resets, bulk->count);
>> +??? if (err)
>> +??????? debug("%s: could release all resets for %p\n",
>> +????????????? __func__, dev);
>> +
>> +??? return ret;
>> +}
>> +
>> ? int reset_get_by_name(struct udevice *dev, const char *name,
>> ?????????????? struct reset_ctl *reset_ctl)
>> ? {
>> @@ -126,6 +160,19 @@ int reset_assert(struct reset_ctl *reset_ctl)
>> ????? return ops->rst_assert(reset_ctl);
>> ? }
>> ? +int reset_assert_bulk(struct reset_ctl_bulk *bulk)
>> +{
>> +??? int i, ret;
>> +
>> +??? for (i = 0; i < bulk->count; i++) {
>> +??????? ret = reset_assert(&bulk->resets[i]);
>> +??????? if (ret < 0)
>> +??????????? return ret;
>> +??? }
>> +
>> +??? return 0;
>> +}
>> +
>> ? int reset_deassert(struct reset_ctl *reset_ctl)
>> ? {
>> ????? struct reset_ops *ops = reset_dev_ops(reset_ctl->dev);
>> @@ -135,6 +182,19 @@ int reset_deassert(struct reset_ctl *reset_ctl)
>> ????? return ops->rst_deassert(reset_ctl);
>> ? }
>> ? +int reset_deassert_bulk(struct reset_ctl_bulk *bulk)
>> +{
>> +??? int i, ret;
>> +
>> +??? for (i = 0; i < bulk->count; i++) {
>> +??????? ret = reset_deassert(&bulk->resets[i]);
>> +??????? if (ret < 0)
>> +??????????? return ret;
>> +??? }
>> +
>> +??? return 0;
>> +}
>> +
>> ? int reset_release_all(struct reset_ctl *reset_ctl, int count)
>> ? {
>> ????? int i, ret;
>> diff --git a/include/reset.h b/include/reset.h
>> index 7185ade..d38f176 100644
>> --- a/include/reset.h
>> +++ b/include/reset.h
>> @@ -60,6 +60,24 @@ struct reset_ctl {
>> ????? unsigned long id;
>> ? };
>> ? +/**
>> + * struct reset_ctl_bulk - A handle to (allowing control of) a bulk of reset
>> + * signals.
>> + *
>> + * Clients provide storage for the reset control bulk. The content of the
>> + * structure is managed solely by the reset API. A reset control bulk struct is
>> + * initialized by "get"ing the reset control bulk struct.
>> + * The reset control bulk struct is passed to all other bulk reset APIs to apply
>> + * the API to all the reset signals in the bulk struct.
>> + *
>> + * @resets: An array of reset signal handles handles.
>> + * @count: The number of reset signal handles in the reset array.
>> + */
>> +struct reset_ctl_bulk {
>> +??? struct reset_ctl *resets;
>> +??? unsigned int count;
>> +};
>> +
>> ? #ifdef CONFIG_DM_RESET
>> ? /**
>> ?? * reset_get_by_index - Get/request a reset signal by integer index.
>> @@ -81,6 +99,22 @@ int reset_get_by_index(struct udevice *dev, int index,
>> ???????????????? struct reset_ctl *reset_ctl);
>> ? ? /**
>> + * reset_get_bulk - Get/request all reset signals of a device.
>> + *
>> + * This looks up and requests all reset signals of the client device; each
>> + * device is assumed to have n reset signals associated with it somehow,
>> + * and this function finds and requests all of them in a separate structure.
>> + * The mapping of client device reset signals indices to provider reset signals
>> + * may be via device-tree properties, board-provided mapping tables, or some
>> + * other mechanism.
>> + *
>> + * @dev:??? The client device.
>> + * @bulk??? A pointer to a reset control bulk struct to initialize.
>> + * @return 0 if OK, or a negative error code.
>> + */
>> +int reset_get_bulk(struct udevice *dev, struct reset_ctl_bulk *bulk);
>> +
>> +/**
>> ?? * reset_get_by_name - Get/request a reset signal by name.
>> ?? *
>> ?? * This looks up and requests a reset signal. The name is relative to the
>> @@ -132,6 +166,21 @@ int reset_free(struct reset_ctl *reset_ctl);
>> ? int reset_assert(struct reset_ctl *reset_ctl);
>> ? ? /**
>> + * reset_assert_bulk - Assert all reset signals in a reset control bulk struct.
>> + *
>> + * This function will assert the specified reset signals in a reset control
>> + * bulk struct, thus resetting the affected HW module(s). Depending on the
>> + * reset controller hardware, the reset signals will either stay asserted
>> + * until reset_deassert_bulk() is called, or the hardware may autonomously
>> + * clear the reset signals itself.
>> + *
>> + * @bulk:??? A reset control bulk struct that was previously successfully
>> + *??????? requested by reset_get_bulk().
>> + * @return 0 if OK, or a negative error code.
>> + */
>> +int reset_assert_bulk(struct reset_ctl_bulk *bulk);
>> +
>> +/**
>> ?? * reset_deassert - Deassert a reset signal.
>> ?? *
>> ?? * This function will deassert the specified reset signal, thus releasing the
>> @@ -145,6 +194,20 @@ int reset_assert(struct reset_ctl *reset_ctl);
>> ? int reset_deassert(struct reset_ctl *reset_ctl);
>> ? ? /**
>> + * reset_deassert_bulk - Deassert all reset signals in a reset control bulk
>> + * struct.
>> + *
>> + * This function will deassert the specified reset signals in a reset control
>> + * bulk struct, thus releasing the affected HW modules() from reset, and
>> + * allowing them to continue normal operation.
>> + *
>> + * @bulk:??? A reset control bulk struct that was previously successfully
>> + *??????? requested by reset_get_bulk().
>> + * @return 0 if OK, or a negative error code.
>> + */
>> +int reset_deassert_bulk(struct reset_ctl_bulk *bulk);
>> +
>> +/**
>> ?? * reset_release_all - Assert/Free an array of previously requested resets.
>> ?? *
>> ?? * For each reset contained in the reset array, this function will check if
>> @@ -156,6 +219,23 @@ int reset_deassert(struct reset_ctl *reset_ctl);
>> ?? * @return 0 if OK, or a negative error code.
>> ?? */
>> ? int reset_release_all(struct reset_ctl *reset_ctl, int count);
>> +
>> +/**
>> + * reset_release_bulk - Assert/Free an array of previously requested reset
>> + * signals in a reset control bulk struct.
>> + *
>> + * For each reset contained in the reset control bulk struct, this function
>> + * will check if reset has been previously requested and then will assert
>> + * and free it.
>> + *
>> + * @bulk:??? A reset control bulk struct that was previously successfully
>> + *??????? requested by reset_get_bulk().
>> + * @return 0 if OK, or a negative error code.
>> + */
>> +static inline int reset_release_bulk(struct reset_ctl_bulk *bulk)
>> +{
>> +??? return reset_release_all(bulk->resets, bulk->count);
>> +}
>> ? #else
>> ? static inline int reset_get_by_index(struct udevice *dev, int index,
>> ?????????????????????? struct reset_ctl *reset_ctl)
>> @@ -163,6 +243,11 @@ static inline int reset_get_by_index(struct udevice *dev, int index,
>> ????? return -ENOTSUPP;
>> ? }
>> ? +static inline int reset_get_bulk(struct udevice *dev, struct clk_bulk *bulk)
> Should be struct reset_ctl_bulk instead of struct clk_bulk
>> +{
>> +??? return -ENOTSUPP;
>> +}
>> +
>> ? static inline int reset_get_by_name(struct udevice *dev, const char *name,
>> ????????????????????? struct reset_ctl *reset_ctl)
>> ? {
>> @@ -179,16 +264,30 @@ static inline int reset_assert(struct reset_ctl *reset_ctl)
>> ????? return 0;
>> ? }
>> ? +static inline int reset_assert_bulk(struct reset_ctl_bulk *bulk)
>> +{
>> +??? return 0;
>> +}
>> +
>> ? static inline int reset_deassert(struct reset_ctl *reset_ctl)
>> ? {
>> ????? return 0;
>> ? }
>> ? +static inline int reset_deassert_bulk(struct reset_ctl_bulk *bulk)
>> +{
>> +??? return 0;
>> +}
>> +
>> ? static inline int reset_release_all(struct reset_ctl *reset_ctl, int count)
>> ? {
>> ????? return 0;
>> ? }
>> ? +static inline int reset_release_bulk(struct clk_bulk *bulk)
> ditto.
> 
> Jean-Jacques
>> +{
>> +??? return 0;
>> +}
>> ? #endif
>> ? ? #endif
> 

You are right, I will push a fix ASAP.

Neil


From marex at denx.de  Thu Apr 12 01:47:35 2018
From: marex at denx.de (Marek Vasut)
Date: Thu, 12 Apr 2018 10:47:35 +0200
Subject: [PATCH] usb: dwc3-of-simple: fix error check of clk_get_bulk when
 disabled
In-Reply-To: <1523520830-13468-1-git-send-email-narmstrong@baylibre.com>
References: <1523520830-13468-1-git-send-email-narmstrong@baylibre.com>
Message-ID: <8730a78f-7755-5816-b014-33595f208c0e@denx.de>

On 04/12/2018 10:13 AM, Neil Armstrong wrote:
> The disabled clk API returns -ENOSYS unlike the reset API returning -ENOTSUPP.
> 
> Fixes: ca7fdc8b1267 ("usb: host: Add simple of glue driver for DWC3 USB Controllers integration")
> Reported-by: Jean-Jacques Hiblot <jjhiblot at ti.com>
> Signed-off-by: Neil Armstrong <narmstrong at baylibre.com>
> ---
>  drivers/usb/host/dwc3-of-simple.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/usb/host/dwc3-of-simple.c b/drivers/usb/host/dwc3-of-simple.c
> index 54a5f60..1f08208 100644
> --- a/drivers/usb/host/dwc3-of-simple.c
> +++ b/drivers/usb/host/dwc3-of-simple.c
> @@ -50,7 +50,7 @@ static int dwc3_of_simple_clk_init(struct udevice *dev,
>  	int ret;
>  
>  	ret = clk_get_bulk(dev, &simple->clks);
> -	if (ret == -ENOTSUPP)
> +	if (ret == -ENOSYS)
>  		return 0;
>  	if (ret)
>  		return ret;
> 

Applied, thanks

-- 
Best regards,
Marek Vasut


From sjg at chromium.org  Thu Apr 12 09:41:50 2018
From: sjg at chromium.org (Simon Glass)
Date: Thu, 12 Apr 2018 10:41:50 -0600
Subject: [PATCH] reset: fix bulk API when DM_RESET is disabled
In-Reply-To: <1523520199-12341-1-git-send-email-narmstrong@baylibre.com>
References: <1523520199-12341-1-git-send-email-narmstrong@baylibre.com>
Message-ID: <CAPnjgZ3SY1DV4XUz6KZMhngAKkSq82WFzs0f-vubgMap4XOqJQ@mail.gmail.com>

On 12 April 2018 at 02:03, Neil Armstrong <narmstrong at baylibre.com> wrote:
> In the commit "reset: Add get/assert/deassert/release for bulk of reset signals"
> the disabled reset_release_bulk() and reset_get_bulk() used the wrong
> struct clk_bulk instead of struct reset_ctl_bulk.
>
> Fixes: 0c28233903b5 ("reset: Add get/assert/deassert/release for bulk of reset signals")
> Reported-by: Jean-Jacques Hiblot <jjhiblot at ti.com>
> Signed-off-by: Neil Armstrong <narmstrong at baylibre.com>
> ---
>  include/reset.h | 5 +++--
>  1 file changed, 3 insertions(+), 2 deletions(-)

Reviewed-by: Simon Glass <sjg at chromium.org>

We don't have build coverage for this at the moment I suppose. It
would be a bit of pain to add that with sandbox, although I wonder if
it could be done with some horrible #define hackery in a C file that
includes this header?

- Simon


From sean at mess.org  Thu Apr 12 15:02:40 2018
From: sean at mess.org (Sean Young)
Date: Thu, 12 Apr 2018 23:02:40 +0100
Subject: [PATCH v2 0/7] Improve latency of IR decoding
In-Reply-To: <20180410192419.wqiqgd7kpdigavf4@camel2.lan>
References: <cover.1523221902.git.sean@mess.org>
 <20180410175343.hu423iejripoqdkj@camel2.lan>
 <20180410183943.riwpqphvthuigpmz@gofer.mess.org>
 <20180410192419.wqiqgd7kpdigavf4@camel2.lan>
Message-ID: <20180412220240.sixzptbdnimbjnam@gofer.mess.org>

On Tue, Apr 10, 2018 at 09:24:19PM +0200, Matthias Reichl wrote:
> On Tue, Apr 10, 2018 at 07:39:43PM +0100, Sean Young wrote:
> > On Tue, Apr 10, 2018 at 07:53:43PM +0200, Matthias Reichl wrote:
> > > Hi Sean,
> > > 
> > > On Sun, Apr 08, 2018 at 10:19:35PM +0100, Sean Young wrote:
> > > > The current IR decoding is much too slow. Many IR protocols rely on
> > > > a trailing space for decoding (e.g. rc-6 needs to know when the bits
> > > > end). The trailing space is generated by the IR timeout, and if this
> > > > is longer than required, buttons can feel slow to respond.
> > > > 
> > > > The other issue is the keyup timer. IR has no concept of a keyup message,
> > > > this is implied by the absence of IR. So, minimising the timeout for
> > > > this makes buttons less "sticky"; the are released much quicker.
> > > > 
> > > > With these patches in place, using IR with the builtin decoders is much
> > > > improved and feels very snappy.
> > > > 
> > > > Changes since v1:
> > > >  - lost more testing
> > > >  - fixed various issues with mce decoder
> > > >  - fixed mceusb so it can use better timeout too
> > > 
> > > thanks, this version is working fine with meson-ir and gpio-rc-recv
> > > (latter on RPi). I mainly tested it with rc-5 remotes so far, more
> > > will follow and I'll update LibreELEC in a day or two to include
> > > the v2 series.
> > 
> > Thanks again for testing!
> > 
> > > Also thanks a lot for the mce_kbd fixes, I was just going to dig
> > > into the decoder (we received a bug report about stuck keys with
> > > mce_kbd last week), your patches can in just at the right time :)
> > > 
> > > I had a closer look at ir-mce_kbd-decoder.c and noticed 2 things
> > > (which can be handled separately):
> > > 
> > > It looks like the input_sync call in the state machine error
> > > path is not necessary:
> > > 
> > > out:
> > > 	dev_dbg(&dev->dev, "failed at state %i (%uus %s)\n",
> > > 		data->state, TO_US(ev.duration), TO_STR(ev.pulse));
> > > 	data->state = STATE_INACTIVE;
> > > 	input_sync(data->idev);
> > > 	return -EINVAL;
> > > 
> > > If I followed the code paths correctly states that generate
> > > input events won't go to out, only paths were no events are
> > > generated jump to out - but better verify that, I could have
> > > missed something.
> > 
> > The input_sync() patch is in mce_kbd_rx_timeout() code path, which
> > doesn't go through this. Hopefully it should fix the keys stuck
> > issue.
> 
> Yes, I saw that and the input_sync() in mce_kbd_rx_timeout() fixed
> this (I could verify that locally).
> 
> What I meant is that the input_sync() in the snippet above, which
> isn't touched by your patches, doesn't seem necessary, as the
> code paths that lead to there don't submit input events. The
> happy paths (successful key/mouse event and keyup) call input_sync()
> at the end of STATE_FINISHED:
> 
> 		lsc.scancode = scancode;
> 		ir_lirc_scancode_event(dev, &lsc);
> 		data->state = STATE_INACTIVE;
> 		input_event(data->idev, EV_MSC, MSC_SCAN, scancode);
> 		input_sync(data->idev);
> 		return 0;

Yes, you're completely right.

> > > The other thing I noticed is that there's no spinlock synchronizing
> > > the events from the timeout callback with the ones from the state
> > > machine - like keylock in rc-main. So the code could potentially
> > > be racy (if the timeout fires while the state machine is outputting
> > > events).
> > 
> > This timeout is for sending keyups in case no keyup is received from
> > the keyboard via input_report_key(). The input system does locking
> > for us (see drivers/input/input.c:436).
> 
> The synchronization code in rc-main looks like it's used to make
> code blocks that eg call input_report_key and input_sync do that
> in an atomic way (plus there's the special handling of keyup_jiffies
> to prevent a race betwen the keyup timeout callback and new
> decoded scancodes.
> 
> As both the timeout callback and the state machine send out
> multiple key events and end them with input_sync it looks to me
> like we'd need to make that atomic as well. Otherwise we could
> have eg timeout running, starting to report a bunch of shift
> and other keys as up, then interruption by a new key/scancode
> calling input_report_key down plus input_sync and then timeout
> resuming and reporting the rest of the keys down and again
> do input_sync().

Again I stand corrected. I'm just testing some patches now for this.

Thanks for being patient and explaining that again :)

Sean


From robh at kernel.org  Fri Apr 13 10:18:53 2018
From: robh at kernel.org (Rob Herring)
Date: Fri, 13 Apr 2018 12:18:53 -0500
Subject: [PATCH 1/3] dt-bindings: interrupt-controller: fix the double
 quotes
In-Reply-To: <20180408145700.23520-2-yixun.lan@amlogic.com>
References: <20180408145700.23520-1-yixun.lan@amlogic.com>
 <20180408145700.23520-2-yixun.lan@amlogic.com>
Message-ID: <20180413171853.5blruiakambnzsgr@rob-hp-laptop>

On Sun, Apr 08, 2018 at 02:56:58PM +0000, Yixun Lan wrote:
> The double quotes seems not ASCII type, fix it here.
> 
> Signed-off-by: Yixun Lan <yixun.lan at amlogic.com>
> ---
>  .../bindings/interrupt-controller/amlogic,meson-gpio-intc.txt  | 10 +++++-----
>  1 file changed, 5 insertions(+), 5 deletions(-)

Reviewed-by: Rob Herring <robh at kernel.org>



From robh at kernel.org  Fri Apr 13 10:20:55 2018
From: robh at kernel.org (Rob Herring)
Date: Fri, 13 Apr 2018 12:20:55 -0500
Subject: [PATCH 2/3] dt-bindings: interrupt-controller: New binding for
 Meson-AXG SoC
In-Reply-To: <20180408145700.23520-3-yixun.lan@amlogic.com>
References: <20180408145700.23520-1-yixun.lan@amlogic.com>
 <20180408145700.23520-3-yixun.lan@amlogic.com>
Message-ID: <20180413172055.waibtio6qbltdv4a@rob-hp-laptop>

On Sun, Apr 08, 2018 at 02:56:59PM +0000, Yixun Lan wrote:
> Update the dt-binding documentation to support new compatible string
> for the GPIO interrupt controller which found in Amlogic's Meson-AXG SoC.
> 
> Signed-off-by: Yixun Lan <yixun.lan at amlogic.com>
> ---
>  .../devicetree/bindings/interrupt-controller/amlogic,meson-gpio-intc.txt | 1 +
>  1 file changed, 1 insertion(+)

Reviewed-by: Rob Herring <robh at kernel.org>



From khoroshilov at ispras.ru  Fri Apr 13 14:39:46 2018
From: khoroshilov at ispras.ru (Alexey Khoroshilov)
Date: Sat, 14 Apr 2018 00:39:46 +0300
Subject: [PATCH] spi: meson-axg: Fix error handling in meson_spicc_probe()
Message-ID: <1523655586-4163-1-git-send-email-khoroshilov@ispras.ru>

If devm_spi_register_master() fails in meson_spicc_probe(),
spicc->core is left undisabled. The patch fixes that.

Found by Linux Driver Verification project (linuxtesting.org).

Signed-off-by: Alexey Khoroshilov <khoroshilov at ispras.ru>
---
 drivers/spi/spi-meson-spicc.c | 11 ++++++++---
 1 file changed, 8 insertions(+), 3 deletions(-)

diff --git a/drivers/spi/spi-meson-spicc.c b/drivers/spi/spi-meson-spicc.c
index 5c82910e3480..7fe4488ace57 100644
--- a/drivers/spi/spi-meson-spicc.c
+++ b/drivers/spi/spi-meson-spicc.c
@@ -574,10 +574,15 @@ static int meson_spicc_probe(struct platform_device *pdev)
 		master->max_speed_hz = rate >> 2;
 
 	ret = devm_spi_register_master(&pdev->dev, master);
-	if (!ret)
-		return 0;
+	if (ret) {
+		dev_err(&pdev->dev, "spi master registration failed\n");
+		goto out_clk;
+	}
 
-	dev_err(&pdev->dev, "spi master registration failed\n");
+	return 0;
+
+out_clk:
+	clk_disable_unprepare(spicc->core);
 
 out_master:
 	spi_master_put(master);
-- 
2.7.4



From marex at denx.de  Fri Apr 13 17:11:38 2018
From: marex at denx.de (Marek Vasut)
Date: Sat, 14 Apr 2018 02:11:38 +0200
Subject: [U-Boot, v2, u-boot, 1/2] reset: Add get/assert/deassert/release
 for bulk of reset signals
In-Reply-To: <20180411140518.GC10996@bill-the-cat.ec.rr.com>
References: <1522748451-21209-2-git-send-email-narmstrong@baylibre.com>
 <20180411140518.GC10996@bill-the-cat.ec.rr.com>
Message-ID: <0c8c73af-7a00-128a-1193-a0d797e708fc@denx.de>

On 04/11/2018 04:05 PM, Tom Rini wrote:
> On Tue, Apr 03, 2018 at 11:40:50AM +0200, Neil Armstrong wrote:
> 
>> This patch adds a "bulk" API to the reset API in order to get/deassert/
>> assert/release a group of reset signals associated with a device.
>>
>> This bulk API will avoid adding a copy of the same code to manage
>> a group of reset signals in drivers.
>>
>> Signed-off-by: Neil Armstrong <narmstrong at baylibre.com>
>> Reviewed-by: Simon Glass <sjg at chromium.org>
> 
> Applied to u-boot/master, thanks!

Breaks building of designware_i2c.c and also isn't checkpatch clean.

ERROR: trailing whitespace
#90: FILE: drivers/reset/reset-uclass.c:87:
+^I$

total: 1 errors, 0 warnings, 0 checks, 229 lines checked

-- 
Best regards,
Marek Vasut


From trini at konsulko.com  Sat Apr 14 06:51:10 2018
From: trini at konsulko.com (Tom Rini)
Date: Sat, 14 Apr 2018 09:51:10 -0400
Subject: [U-Boot, v2, u-boot, 1/2] reset: Add get/assert/deassert/release
 for bulk of reset signals
In-Reply-To: <0c8c73af-7a00-128a-1193-a0d797e708fc@denx.de>
References: <1522748451-21209-2-git-send-email-narmstrong@baylibre.com>
 <20180411140518.GC10996@bill-the-cat.ec.rr.com>
 <0c8c73af-7a00-128a-1193-a0d797e708fc@denx.de>
Message-ID: <20180414135110.GA5346@bill-the-cat.ec.rr.com>

On Sat, Apr 14, 2018 at 02:11:38AM +0200, Marek Vasut wrote:
> On 04/11/2018 04:05 PM, Tom Rini wrote:
> > On Tue, Apr 03, 2018 at 11:40:50AM +0200, Neil Armstrong wrote:
> > 
> >> This patch adds a "bulk" API to the reset API in order to get/deassert/
> >> assert/release a group of reset signals associated with a device.
> >>
> >> This bulk API will avoid adding a copy of the same code to manage
> >> a group of reset signals in drivers.
> >>
> >> Signed-off-by: Neil Armstrong <narmstrong at baylibre.com>
> >> Reviewed-by: Simon Glass <sjg at chromium.org>
> > 
> > Applied to u-boot/master, thanks!
> 
> Breaks building of designware_i2c.c and also isn't checkpatch clean.

For which platform?

> ERROR: trailing whitespace
> #90: FILE: drivers/reset/reset-uclass.c:87:
> +^I$
> 
> total: 1 errors, 0 warnings, 0 checks, 229 lines checked

Yes, I probably ought to see about getting checkpatch to fixup issues
like that automatically.

-- 
Tom
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From jbrunet at baylibre.com  Mon Apr 16 02:59:12 2018
From: jbrunet at baylibre.com (Jerome Brunet)
Date: Mon, 16 Apr 2018 11:59:12 +0200
Subject: [PATCH v5 4/7] dt-bindings: clock: reset: Add AXG AO Clock and
 Reset Bindings
In-Reply-To: <20180409143749.71197-5-yixun.lan@amlogic.com>
References: <20180409143749.71197-1-yixun.lan@amlogic.com>
 <20180409143749.71197-5-yixun.lan@amlogic.com>
Message-ID: <1523872752.2601.26.camel@baylibre.com>

On Mon, 2018-04-09 at 22:37 +0800, Yixun Lan wrote:
> Add dt-bindings headers for the Meson-AXG's AO clock and
> reset controller.
> 
> Reviewed-by: Rob Herring <robh at kernel.org>
> Signed-off-by: Yixun Lan <yixun.lan at amlogic.com>
> ---
>  include/dt-bindings/clock/axg-aoclkc.h | 26 ++++++++++++++++++++++++++
>  include/dt-bindings/reset/axg-aoclkc.h | 20 ++++++++++++++++++++
>  2 files changed, 46 insertions(+)
>  create mode 100644 include/dt-bindings/clock/axg-aoclkc.h
>  create mode 100644 include/dt-bindings/reset/axg-aoclkc.h

Hi Philipp,

Is OK if we take this through clock tree ?
The related reset controller is actually part of a clock controller driver.

Best Regards
Jerome

> 
> diff --git a/include/dt-bindings/clock/axg-aoclkc.h b/include/dt-bindings/clock/axg-aoclkc.h
> new file mode 100644
> index 000000000000..61955016a55b
> --- /dev/null
> +++ b/include/dt-bindings/clock/axg-aoclkc.h
> @@ -0,0 +1,26 @@
> +/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */
> +/*
> + * Copyright (c) 2016 BayLibre, SAS
> + * Author: Neil Armstrong <narmstrong at baylibre.com>
> + *
> + * Copyright (c) 2018 Amlogic, inc.
> + * Author: Qiufang Dai <qiufang.dai at amlogic.com>
> + */
> +
> +#ifndef DT_BINDINGS_CLOCK_AMLOGIC_MESON_AXG_AOCLK
> +#define DT_BINDINGS_CLOCK_AMLOGIC_MESON_AXG_AOCLK
> +
> +#define CLKID_AO_REMOTE		0
> +#define CLKID_AO_I2C_MASTER	1
> +#define CLKID_AO_I2C_SLAVE	2
> +#define CLKID_AO_UART1		3
> +#define CLKID_AO_UART2		4
> +#define CLKID_AO_IR_BLASTER	5
> +#define CLKID_AO_SAR_ADC	6
> +#define CLKID_AO_CLK81		7
> +#define CLKID_AO_SAR_ADC_SEL	8
> +#define CLKID_AO_SAR_ADC_DIV	9
> +#define CLKID_AO_SAR_ADC_CLK	10
> +#define CLKID_AO_ALT_XTAL	11
> +
> +#endif
> diff --git a/include/dt-bindings/reset/axg-aoclkc.h b/include/dt-bindings/reset/axg-aoclkc.h
> new file mode 100644
> index 000000000000..d342c0b6b2a7
> --- /dev/null
> +++ b/include/dt-bindings/reset/axg-aoclkc.h
> @@ -0,0 +1,20 @@
> +/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */
> +/*
> + * Copyright (c) 2016 BayLibre, SAS
> + * Author: Neil Armstrong <narmstrong at baylibre.com>
> + *
> + * Copyright (c) 2018 Amlogic, inc.
> + * Author: Qiufang Dai <qiufang.dai at amlogic.com>
> + */
> +
> +#ifndef DT_BINDINGS_RESET_AMLOGIC_MESON_AXG_AOCLK
> +#define DT_BINDINGS_RESET_AMLOGIC_MESON_AXG_AOCLK
> +
> +#define RESET_AO_REMOTE		0
> +#define RESET_AO_I2C_MASTER	1
> +#define RESET_AO_I2C_SLAVE	2
> +#define RESET_AO_UART1		3
> +#define RESET_AO_UART2		4
> +#define RESET_AO_IR_BLASTER	5
> +
> +#endif



From p.zabel at pengutronix.de  Mon Apr 16 03:09:10 2018
From: p.zabel at pengutronix.de (Philipp Zabel)
Date: Mon, 16 Apr 2018 12:09:10 +0200
Subject: [PATCH v5 4/7] dt-bindings: clock: reset: Add AXG AO Clock and
 Reset Bindings
In-Reply-To: <1523872752.2601.26.camel@baylibre.com>
References: <20180409143749.71197-1-yixun.lan@amlogic.com>
 <20180409143749.71197-5-yixun.lan@amlogic.com>
 <1523872752.2601.26.camel@baylibre.com>
Message-ID: <1523873350.5918.6.camel@pengutronix.de>

Hi Jerome,

On Mon, 2018-04-16 at 11:59 +0200, Jerome Brunet wrote:
> On Mon, 2018-04-09 at 22:37 +0800, Yixun Lan wrote:
> > Add dt-bindings headers for the Meson-AXG's AO clock and
> > reset controller.
> > 
> > Reviewed-by: Rob Herring <robh at kernel.org>
> > Signed-off-by: Yixun Lan <yixun.lan at amlogic.com>
> > ---
> >  include/dt-bindings/clock/axg-aoclkc.h | 26 ++++++++++++++++++++++++++
> >  include/dt-bindings/reset/axg-aoclkc.h | 20 ++++++++++++++++++++
> >  2 files changed, 46 insertions(+)
> >  create mode 100644 include/dt-bindings/clock/axg-aoclkc.h
> >  create mode 100644 include/dt-bindings/reset/axg-aoclkc.h
> 
> Hi Philipp,
> 
> Is OK if we take this through clock tree ?
> The related reset controller is actually part of a clock controller driver.

Absolutely, this should go in together with the driver.
I see no risk of merge conflicts here.

Acked-by: Philipp Zabel <p.zabel at pengutronix.de>

regards
Philipp


From jbrunet at baylibre.com  Mon Apr 16 03:38:04 2018
From: jbrunet at baylibre.com (Jerome Brunet)
Date: Mon, 16 Apr 2018 12:38:04 +0200
Subject: [PATCH v5 2/7] clk: meson: aoclk: refactor common code into
 dedicated file
In-Reply-To: <20180409143749.71197-3-yixun.lan@amlogic.com>
References: <20180409143749.71197-1-yixun.lan@amlogic.com>
 <20180409143749.71197-3-yixun.lan@amlogic.com>
Message-ID: <1523875084.2601.28.camel@baylibre.com>

On Mon, 2018-04-09 at 22:37 +0800, Yixun Lan wrote:
> We try to refactor the common code into one dedicated file,
> while preparing to add new Meson-AXG aoclk driver, this would
> help us to better share the code by all aoclk drivers.
> 
> Suggested-by: Jerome Brunet <jbrunet at baylibre.com>
> Signed-off-by: Yixun Lan <yixun.lan at amlogic.com>
> ---
>  drivers/clk/meson/Kconfig       |  7 ++++
>  drivers/clk/meson/Makefile      |  1 +
>  drivers/clk/meson/gxbb-aoclk.c  | 91 ++++++++++++++---------------------------
>  drivers/clk/meson/gxbb-aoclk.h  |  7 ++++
>  drivers/clk/meson/meson-aoclk.c | 82 +++++++++++++++++++++++++++++++++++++
>  drivers/clk/meson/meson-aoclk.h | 35 ++++++++++++++++
>  6 files changed, 163 insertions(+), 60 deletions(-)
>  create mode 100644 drivers/clk/meson/meson-aoclk.c
>  create mode 100644 drivers/clk/meson/meson-aoclk.h
> 
> diff --git a/drivers/clk/meson/Kconfig b/drivers/clk/meson/Kconfig
> index d5cbec522aec..fddc7ec7b820 100644
> --- a/drivers/clk/meson/Kconfig
> +++ b/drivers/clk/meson/Kconfig
> @@ -3,6 +3,12 @@ config COMMON_CLK_AMLOGIC
>  	depends on OF
>  	depends on ARCH_MESON || COMPILE_TEST
>  
> +config COMMON_CLK_MESON_AO
> +	bool
> +	depends on OF
> +	depends on ARCH_MESON || COMPILE_TEST
> +	select COMMON_CLK_REGMAP_MESON
> +
>  config COMMON_CLK_REGMAP_MESON
>  	bool
>  	select REGMAP
> @@ -21,6 +27,7 @@ config COMMON_CLK_GXBB
>  	bool
>  	depends on COMMON_CLK_AMLOGIC
>  	select RESET_CONTROLLER
> +	select COMMON_CLK_MESON_AO
>  	select COMMON_CLK_REGMAP_MESON
>  	select MFD_SYSCON
>  	help
> diff --git a/drivers/clk/meson/Makefile b/drivers/clk/meson/Makefile
> index ffee82e60b7a..0a8df284f4e7 100644
> --- a/drivers/clk/meson/Makefile
> +++ b/drivers/clk/meson/Makefile
> @@ -3,6 +3,7 @@
>  #
>  
>  obj-$(CONFIG_COMMON_CLK_AMLOGIC) += clk-pll.o clk-mpll.o clk-audio-divider.o
> +obj-$(CONFIG_COMMON_CLK_MESON_AO) += meson-aoclk.o
>  obj-$(CONFIG_COMMON_CLK_MESON8B) += meson8b.o
>  obj-$(CONFIG_COMMON_CLK_GXBB)	 += gxbb.o gxbb-aoclk.o gxbb-aoclk-32k.o
>  obj-$(CONFIG_COMMON_CLK_AXG)	 += axg.o
> diff --git a/drivers/clk/meson/gxbb-aoclk.c b/drivers/clk/meson/gxbb-aoclk.c
> index eebb580b9e0f..f2e0640a7f74 100644
> --- a/drivers/clk/meson/gxbb-aoclk.c
> +++ b/drivers/clk/meson/gxbb-aoclk.c
> @@ -52,39 +52,13 @@
>   * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
>   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
>   */
> -#include <linux/clk-provider.h>
> -#include <linux/of_address.h>
>  #include <linux/platform_device.h>
>  #include <linux/reset-controller.h>
>  #include <linux/mfd/syscon.h>
> -#include <linux/regmap.h>
>  #include <linux/init.h>
> -#include <linux/delay.h>
> -#include <dt-bindings/clock/gxbb-aoclkc.h>
> -#include <dt-bindings/reset/gxbb-aoclkc.h>
>  #include "clk-regmap.h"
>  #include "gxbb-aoclk.h"
>  
> -struct gxbb_aoclk_reset_controller {
> -	struct reset_controller_dev reset;
> -	unsigned int *data;
> -	struct regmap *regmap;
> -};
> -
> -static int gxbb_aoclk_do_reset(struct reset_controller_dev *rcdev,
> -			       unsigned long id)
> -{
> -	struct gxbb_aoclk_reset_controller *reset =
> -		container_of(rcdev, struct gxbb_aoclk_reset_controller, reset);
> -
> -	return regmap_write(reset->regmap, AO_RTI_GEN_CNTL_REG0,
> -			    BIT(reset->data[id]));
> -}
> -
> -static const struct reset_control_ops gxbb_aoclk_reset_ops = {
> -	.reset = gxbb_aoclk_do_reset,
> -};
> -
>  #define GXBB_AO_GATE(_name, _bit)					\
>  static struct clk_regmap _name##_ao = {					\
>  	.data = &(struct clk_regmap_gate_data) {			\
> @@ -117,7 +91,7 @@ static struct aoclk_cec_32k cec_32k_ao = {
>  	},
>  };
>  
> -static unsigned int gxbb_aoclk_reset[] = {
> +static const unsigned int gxbb_aoclk_reset[] = {
>  	[RESET_AO_REMOTE] = 16,
>  	[RESET_AO_I2C_MASTER] = 18,
>  	[RESET_AO_I2C_SLAVE] = 19,
> @@ -135,7 +109,7 @@ static struct clk_regmap *gxbb_aoclk_gate[] = {
>  	[CLKID_AO_IR_BLASTER] = &ir_blaster_ao,
>  };
>  
> -static struct clk_hw_onecell_data gxbb_aoclk_onecell_data = {
> +static const struct clk_hw_onecell_data gxbb_aoclk_onecell_data = {
>  	.hws = {
>  		[CLKID_AO_REMOTE] = &remote_ao.hw,
>  		[CLKID_AO_I2C_MASTER] = &i2c_master_ao.hw,
> @@ -145,58 +119,55 @@ static struct clk_hw_onecell_data gxbb_aoclk_onecell_data = {
>  		[CLKID_AO_IR_BLASTER] = &ir_blaster_ao.hw,
>  		[CLKID_AO_CEC_32K] = &cec_32k_ao.hw,
>  	},
> -	.num = 7,
> +	.num = NR_CLKS,
>  };
>  
> -static int gxbb_aoclkc_probe(struct platform_device *pdev)
> +static int gxbb_register_cec_ao_32k(struct platform_device *pdev)
>  {
> -	struct gxbb_aoclk_reset_controller *rstc;
>  	struct device *dev = &pdev->dev;
>  	struct regmap *regmap;
> -	int ret, clkid;
> -
> -	rstc = devm_kzalloc(dev, sizeof(*rstc), GFP_KERNEL);
> -	if (!rstc)
> -		return -ENOMEM;
> +	int ret;
>  
>  	regmap = syscon_node_to_regmap(of_get_parent(dev->of_node));
>  	if (IS_ERR(regmap)) {
>  		dev_err(dev, "failed to get regmap\n");
> -		return -ENODEV;
> -	}
> -
> -	/* Reset Controller */
> -	rstc->regmap = regmap;
> -	rstc->data = gxbb_aoclk_reset;
> -	rstc->reset.ops = &gxbb_aoclk_reset_ops;
> -	rstc->reset.nr_resets = ARRAY_SIZE(gxbb_aoclk_reset);
> -	rstc->reset.of_node = dev->of_node;
> -	ret = devm_reset_controller_register(dev, &rstc->reset);
> -
> -	/*
> -	 * Populate regmap and register all clks
> -	 */
> -	for (clkid = 0; clkid < ARRAY_SIZE(gxbb_aoclk_gate); clkid++) {
> -		gxbb_aoclk_gate[clkid]->map = regmap;
> -
> -		ret = devm_clk_hw_register(dev,
> -					   gxbb_aoclk_onecell_data.hws[clkid]);
> -		if (ret)
> -			return ret;
> +		return PTR_ERR(regmap);
>  	}
>  
>  	/* Specific clocks */
>  	cec_32k_ao.regmap = regmap;
>  	ret = devm_clk_hw_register(dev, &cec_32k_ao.hw);
> +	if (ret) {
> +		dev_err(&pdev->dev, "clk cec_32k_ao register failed.\n");
> +		return ret;
> +	}
> +
> +	return 0;
> +}
> +
> +static const struct meson_aoclk_data gxbb_aoclkc_data = {
> +	.reset_reg	= AO_RTI_GEN_CNTL_REG0,
> +	.num_reset	= ARRAY_SIZE(gxbb_aoclk_reset),
> +	.reset		= gxbb_aoclk_reset,
> +	.num_clks	= ARRAY_SIZE(gxbb_aoclk_gate),
> +	.clks		= gxbb_aoclk_gate,
> +	.hw_data	= &gxbb_aoclk_onecell_data,
> +};
> +
> +static int gxbb_aoclkc_probe(struct platform_device *pdev)
> +{
> +	int ret = gxbb_register_cec_ao_32k(pdev);
>  	if (ret)
>  		return ret;
>  
> -	return devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get,
> -			&gxbb_aoclk_onecell_data);
> +	return meson_aoclkc_probe(pdev);
>  }
>  
>  static const struct of_device_id gxbb_aoclkc_match_table[] = {
> -	{ .compatible = "amlogic,meson-gx-aoclkc" },
> +	{
> +		.compatible	= "amlogic,meson-gx-aoclkc",
> +		.data		= &gxbb_aoclkc_data,
> +	},
>  	{ }
>  };
>  
> diff --git a/drivers/clk/meson/gxbb-aoclk.h b/drivers/clk/meson/gxbb-aoclk.h
> index badc4c22b4ee..b031f1a0213e 100644
> --- a/drivers/clk/meson/gxbb-aoclk.h
> +++ b/drivers/clk/meson/gxbb-aoclk.h
> @@ -8,6 +8,10 @@
>  #ifndef __GXBB_AOCLKC_H
>  #define __GXBB_AOCLKC_H
>  
> +#include "meson-aoclk.h"
> +
> +#define NR_CLKS	7
> +
>  /* AO Configuration Clock registers offsets */
>  #define AO_RTI_PWR_CNTL_REG1	0x0c
>  #define AO_RTI_PWR_CNTL_REG0	0x10
> @@ -26,4 +30,7 @@ struct aoclk_cec_32k {
>  
>  extern const struct clk_ops meson_aoclk_cec_32k_ops;
>  
> +#include <dt-bindings/clock/gxbb-aoclkc.h>
> +#include <dt-bindings/reset/gxbb-aoclkc.h>
> +
>  #endif /* __GXBB_AOCLKC_H */
> diff --git a/drivers/clk/meson/meson-aoclk.c b/drivers/clk/meson/meson-aoclk.c
> new file mode 100644
> index 000000000000..74338ef0a62b
> --- /dev/null
> +++ b/drivers/clk/meson/meson-aoclk.c
> @@ -0,0 +1,82 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Amlogic Meson-AXG Clock Controller Driver
> + *
> + * Copyright (c) 2016 BayLibre, SAS.
> + * Author: Neil Armstrong <narmstrong at baylibre.com>
> + *
> + * Copyright (c) 2018 Amlogic, inc.
> + * Author: Qiufang Dai <qiufang.dai at amlogic.com>
> + * Author: Yixun Lan <yixun.lan at amlogic.com>
> + */
> +
> +#include <linux/platform_device.h>
> +#include <linux/reset-controller.h>
> +#include <linux/mfd/syscon.h>
> +#include <linux/init.h>
> +#include <linux/of_device.h>
> +#include "clk-regmap.h"
> +#include "meson-aoclk.h"
> +
> +static int meson_aoclk_do_reset(struct reset_controller_dev *rcdev,
> +			       unsigned long id)
> +{
> +	struct meson_aoclk_reset_controller *rstc =
> +		container_of(rcdev, struct meson_aoclk_reset_controller, reset);
> +
> +	return regmap_write(rstc->regmap, rstc->data->reset_reg,
> +			    BIT(rstc->data->reset[id]));
> +}
> +
> +static const struct reset_control_ops meson_aoclk_reset_ops = {
> +	.reset = meson_aoclk_do_reset,
> +};
> +
> +int meson_aoclkc_probe(struct platform_device *pdev)
> +{
> +	struct meson_aoclk_reset_controller *rstc;
> +	struct meson_aoclk_data *data;
> +	struct device *dev = &pdev->dev;
> +	struct regmap *regmap;
> +	int ret, clkid;
> +
> +	data = (struct meson_aoclk_data *) of_device_get_match_data(dev);
> +	if (!data)
> +		return -ENODEV;
> +
> +	rstc = devm_kzalloc(dev, sizeof(*rstc), GFP_KERNEL);
> +	if (!rstc)
> +		return -ENOMEM;
> +
> +	regmap = syscon_node_to_regmap(of_get_parent(dev->of_node));
> +	if (IS_ERR(regmap)) {
> +		dev_err(dev, "failed to get regmap\n");
> +		return PTR_ERR(regmap);
> +	}
> +
> +	/* Reset Controller */
> +	rstc->data = data;
> +	rstc->regmap = regmap;
> +	rstc->reset.ops = &meson_aoclk_reset_ops;
> +	rstc->reset.nr_resets = data->num_reset,
> +	rstc->reset.of_node = dev->of_node;
> +	ret = devm_reset_controller_register(dev, &rstc->reset);
> +	if (ret) {
> +		dev_err(dev, "failed to register reset controller\n");
> +		return ret;
> +	}
> +
> +	/*
> +	 * Populate regmap and register all clks
> +	 */
> +	for (clkid = 0; clkid < data->num_clks; clkid++) {
> +		data->clks[clkid]->map = regmap;
> +
> +		ret = devm_clk_hw_register(dev, data->hw_data->hws[clkid]);
> +		if (ret)
> +			return ret;
> +	}
> +
> +	return devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get,
> +		(void *) data->hw_data);
> +}

Missing new line here. Please run checkpatch and pay attention to git warnings
about whitespace errors.

> diff --git a/drivers/clk/meson/meson-aoclk.h b/drivers/clk/meson/meson-aoclk.h
> new file mode 100644
> index 000000000000..ec59e027dd37
> --- /dev/null
> +++ b/drivers/clk/meson/meson-aoclk.h
> @@ -0,0 +1,35 @@
> +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
> +/*
> + * Copyright (c) 2017 BayLibre, SAS
> + * Author: Neil Armstrong <narmstrong at baylibre.com>
> + *
> + * Copyright (c) 2018 Amlogic, inc.
> + * Author: Qiufang Dai <qiufang.dai at amlogic.com>
> + * Author: Yixun Lan <yixun.lan at amlogic.com>
> + */
> +
> +#ifndef __MESON_AOCLK_H__
> +#define __MESON_AOCLK_H__
> +
> +#include <linux/platform_device.h>
> +#include <linux/reset-controller.h>
> +#include "clk-regmap.h"
> +
> +struct meson_aoclk_data {
> +	const unsigned int			reset_reg;
> +	const int				num_reset;
> +	const unsigned int			*reset;
> +	int					num_clks;
> +	struct clk_regmap			**clks;
> +	const struct clk_hw_onecell_data	*hw_data;
> +};
> +
> +struct meson_aoclk_reset_controller {
> +	struct reset_controller_dev		reset;
> +	const struct meson_aoclk_data		*data;
> +	struct regmap				*regmap;
> +};
> +
> +int meson_aoclkc_probe(struct platform_device *pdev);
> +#endif
> +



From jbrunet at baylibre.com  Mon Apr 16 04:34:50 2018
From: jbrunet at baylibre.com (Jerome Brunet)
Date: Mon, 16 Apr 2018 13:34:50 +0200
Subject: [PATCH v5 2/7] clk: meson: aoclk: refactor common code into
 dedicated file
In-Reply-To: <20180409143749.71197-3-yixun.lan@amlogic.com>
References: <20180409143749.71197-1-yixun.lan@amlogic.com>
 <20180409143749.71197-3-yixun.lan@amlogic.com>
Message-ID: <1523878490.2601.34.camel@baylibre.com>

On Mon, 2018-04-09 at 22:37 +0800, Yixun Lan wrote:
> We try to refactor the common code into one dedicated file,
> while preparing to add new Meson-AXG aoclk driver, this would
> help us to better share the code by all aoclk drivers.
> 
> Suggested-by: Jerome Brunet <jbrunet at baylibre.com>
> Signed-off-by: Yixun Lan <yixun.lan at amlogic.com>
> ---
>  drivers/clk/meson/Kconfig       |  7 ++++
>  drivers/clk/meson/Makefile      |  1 +
>  drivers/clk/meson/gxbb-aoclk.c  | 91 ++++++++++++++---------------------------
>  drivers/clk/meson/gxbb-aoclk.h  |  7 ++++
>  drivers/clk/meson/meson-aoclk.c | 82 +++++++++++++++++++++++++++++++++++++
>  drivers/clk/meson/meson-aoclk.h | 35 ++++++++++++++++
>  6 files changed, 163 insertions(+), 60 deletions(-)
>  create mode 100644 drivers/clk/meson/meson-aoclk.c
>  create mode 100644 drivers/clk/meson/meson-aoclk.h
> 
> diff --git a/drivers/clk/meson/Kconfig b/drivers/clk/meson/Kconfig
> index d5cbec522aec..fddc7ec7b820 100644
> --- a/drivers/clk/meson/Kconfig
> +++ b/drivers/clk/meson/Kconfig
> @@ -3,6 +3,12 @@ config COMMON_CLK_AMLOGIC
>  	depends on OF
>  	depends on ARCH_MESON || COMPILE_TEST
>  
> +config COMMON_CLK_MESON_AO
> +	bool
> +	depends on OF
> +	depends on ARCH_MESON || COMPILE_TEST
> +	select COMMON_CLK_REGMAP_MESON
> +
>  config COMMON_CLK_REGMAP_MESON
>  	bool
>  	select REGMAP
> @@ -21,6 +27,7 @@ config COMMON_CLK_GXBB
>  	bool
>  	depends on COMMON_CLK_AMLOGIC
>  	select RESET_CONTROLLER
> +	select COMMON_CLK_MESON_AO
>  	select COMMON_CLK_REGMAP_MESON
>  	select MFD_SYSCON
>  	help
> diff --git a/drivers/clk/meson/Makefile b/drivers/clk/meson/Makefile
> index ffee82e60b7a..0a8df284f4e7 100644
> --- a/drivers/clk/meson/Makefile
> +++ b/drivers/clk/meson/Makefile
> @@ -3,6 +3,7 @@
>  #
>  
>  obj-$(CONFIG_COMMON_CLK_AMLOGIC) += clk-pll.o clk-mpll.o clk-audio-divider.o
> +obj-$(CONFIG_COMMON_CLK_MESON_AO) += meson-aoclk.o
>  obj-$(CONFIG_COMMON_CLK_MESON8B) += meson8b.o
>  obj-$(CONFIG_COMMON_CLK_GXBB)	 += gxbb.o gxbb-aoclk.o gxbb-aoclk-32k.o
>  obj-$(CONFIG_COMMON_CLK_AXG)	 += axg.o
> diff --git a/drivers/clk/meson/gxbb-aoclk.c b/drivers/clk/meson/gxbb-aoclk.c
> index eebb580b9e0f..f2e0640a7f74 100644
> --- a/drivers/clk/meson/gxbb-aoclk.c
> +++ b/drivers/clk/meson/gxbb-aoclk.c
> @@ -52,39 +52,13 @@
>   * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
>   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
>   */
> -#include <linux/clk-provider.h>
> -#include <linux/of_address.h>
>  #include <linux/platform_device.h>

>  #include <linux/reset-controller.h>
Not required anymore

>  #include <linux/mfd/syscon.h>
> -#include <linux/regmap.h>
>  #include <linux/init.h>
Not required

> -#include <linux/delay.h>

> -#include <dt-bindings/clock/gxbb-aoclkc.h>
> -#include <dt-bindings/reset/gxbb-aoclkc.h>
Please keep these 2 here

>  #include "clk-regmap.h"
>  #include "gxbb-aoclk.h"
>  
> -struct gxbb_aoclk_reset_controller {
> -	struct reset_controller_dev reset;
> -	unsigned int *data;
> -	struct regmap *regmap;
> -};
> -
> -static int gxbb_aoclk_do_reset(struct reset_controller_dev *rcdev,
> -			       unsigned long id)
> -{
> -	struct gxbb_aoclk_reset_controller *reset =
> -		container_of(rcdev, struct gxbb_aoclk_reset_controller, reset);
> -
> -	return regmap_write(reset->regmap, AO_RTI_GEN_CNTL_REG0,
> -			    BIT(reset->data[id]));
> -}
> -
> -static const struct reset_control_ops gxbb_aoclk_reset_ops = {
> -	.reset = gxbb_aoclk_do_reset,
> -};
> -
>  #define GXBB_AO_GATE(_name, _bit)					\
>  static struct clk_regmap _name##_ao = {					\
>  	.data = &(struct clk_regmap_gate_data) {			\
> @@ -117,7 +91,7 @@ static struct aoclk_cec_32k cec_32k_ao = {
>  	},
>  };
>  
> -static unsigned int gxbb_aoclk_reset[] = {
> +static const unsigned int gxbb_aoclk_reset[] = {
>  	[RESET_AO_REMOTE] = 16,
>  	[RESET_AO_I2C_MASTER] = 18,
>  	[RESET_AO_I2C_SLAVE] = 19,
> @@ -135,7 +109,7 @@ static struct clk_regmap *gxbb_aoclk_gate[] = {
>  	[CLKID_AO_IR_BLASTER] = &ir_blaster_ao,
>  };
>  
> -static struct clk_hw_onecell_data gxbb_aoclk_onecell_data = {
> +static const struct clk_hw_onecell_data gxbb_aoclk_onecell_data = {
>  	.hws = {
>  		[CLKID_AO_REMOTE] = &remote_ao.hw,
>  		[CLKID_AO_I2C_MASTER] = &i2c_master_ao.hw,
> @@ -145,58 +119,55 @@ static struct clk_hw_onecell_data gxbb_aoclk_onecell_data = {
>  		[CLKID_AO_IR_BLASTER] = &ir_blaster_ao.hw,
>  		[CLKID_AO_CEC_32K] = &cec_32k_ao.hw,
>  	},
> -	.num = 7,
> +	.num = NR_CLKS,
>  };
>  
> -static int gxbb_aoclkc_probe(struct platform_device *pdev)
> +static int gxbb_register_cec_ao_32k(struct platform_device *pdev)
>  {
> -	struct gxbb_aoclk_reset_controller *rstc;
>  	struct device *dev = &pdev->dev;
>  	struct regmap *regmap;
> -	int ret, clkid;
> -
> -	rstc = devm_kzalloc(dev, sizeof(*rstc), GFP_KERNEL);
> -	if (!rstc)
> -		return -ENOMEM;
> +	int ret;
>  
>  	regmap = syscon_node_to_regmap(of_get_parent(dev->of_node));
>  	if (IS_ERR(regmap)) {
>  		dev_err(dev, "failed to get regmap\n");
> -		return -ENODEV;
> -	}
> -
> -	/* Reset Controller */
> -	rstc->regmap = regmap;
> -	rstc->data = gxbb_aoclk_reset;
> -	rstc->reset.ops = &gxbb_aoclk_reset_ops;
> -	rstc->reset.nr_resets = ARRAY_SIZE(gxbb_aoclk_reset);
> -	rstc->reset.of_node = dev->of_node;
> -	ret = devm_reset_controller_register(dev, &rstc->reset);
> -
> -	/*
> -	 * Populate regmap and register all clks
> -	 */
> -	for (clkid = 0; clkid < ARRAY_SIZE(gxbb_aoclk_gate); clkid++) {
> -		gxbb_aoclk_gate[clkid]->map = regmap;
> -
> -		ret = devm_clk_hw_register(dev,
> -					   gxbb_aoclk_onecell_data.hws[clkid]);
> -		if (ret)
> -			return ret;
> +		return PTR_ERR(regmap);
>  	}
>  
>  	/* Specific clocks */
>  	cec_32k_ao.regmap = regmap;
>  	ret = devm_clk_hw_register(dev, &cec_32k_ao.hw);
> +	if (ret) {
> +		dev_err(&pdev->dev, "clk cec_32k_ao register failed.\n");
> +		return ret;
> +	}
> +
> +	return 0;
> +}
> +
> +static const struct meson_aoclk_data gxbb_aoclkc_data = {
> +	.reset_reg	= AO_RTI_GEN_CNTL_REG0,
> +	.num_reset	= ARRAY_SIZE(gxbb_aoclk_reset),
> +	.reset		= gxbb_aoclk_reset,
> +	.num_clks	= ARRAY_SIZE(gxbb_aoclk_gate),
> +	.clks		= gxbb_aoclk_gate,
> +	.hw_data	= &gxbb_aoclk_onecell_data,
> +};
> +
> +static int gxbb_aoclkc_probe(struct platform_device *pdev)
> +{
> +	int ret = gxbb_register_cec_ao_32k(pdev);
>  	if (ret)
>  		return ret;
>  
> -	return devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get,
> -			&gxbb_aoclk_onecell_data);
> +	return meson_aoclkc_probe(pdev);
>  }
>  
>  static const struct of_device_id gxbb_aoclkc_match_table[] = {
> -	{ .compatible = "amlogic,meson-gx-aoclkc" },
> +	{
> +		.compatible	= "amlogic,meson-gx-aoclkc",
> +		.data		= &gxbb_aoclkc_data,
> +	},
>  	{ }
>  };
>  
> diff --git a/drivers/clk/meson/gxbb-aoclk.h b/drivers/clk/meson/gxbb-aoclk.h
> index badc4c22b4ee..b031f1a0213e 100644
> --- a/drivers/clk/meson/gxbb-aoclk.h
> +++ b/drivers/clk/meson/gxbb-aoclk.h
> @@ -8,6 +8,10 @@
>  #ifndef __GXBB_AOCLKC_H
>  #define __GXBB_AOCLKC_H
>  
> +#include "meson-aoclk.h"

You are not using any of the structure defined in meson-aoclk.h in here.
Why do you include this here ?

> +
> +#define NR_CLKS	7
> +
>  /* AO Configuration Clock registers offsets */
>  #define AO_RTI_PWR_CNTL_REG1	0x0c
>  #define AO_RTI_PWR_CNTL_REG0	0x10
> @@ -26,4 +30,7 @@ struct aoclk_cec_32k {
>  
>  extern const struct clk_ops meson_aoclk_cec_32k_ops;
>  
> +#include <dt-bindings/clock/gxbb-aoclkc.h>
> +#include <dt-bindings/reset/gxbb-aoclkc.h>
Please drop this.

> +
>  #endif /* __GXBB_AOCLKC_H */
> diff --git a/drivers/clk/meson/meson-aoclk.c b/drivers/clk/meson/meson-aoclk.c
> new file mode 100644
> index 000000000000..74338ef0a62b
> --- /dev/null
> +++ b/drivers/clk/meson/meson-aoclk.c
> @@ -0,0 +1,82 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Amlogic Meson-AXG Clock Controller Driver
> + *
> + * Copyright (c) 2016 BayLibre, SAS.
> + * Author: Neil Armstrong <narmstrong at baylibre.com>
> + *
> + * Copyright (c) 2018 Amlogic, inc.
> + * Author: Qiufang Dai <qiufang.dai at amlogic.com>
> + * Author: Yixun Lan <yixun.lan at amlogic.com>
> + */
> +
> +#include <linux/platform_device.h>
> +#include <linux/reset-controller.h>
> +#include <linux/mfd/syscon.h>
> +#include <linux/init.h>
Not required

> +#include <linux/of_device.h>
> +#include "clk-regmap.h"
> +#include "meson-aoclk.h"
> +
> +static int meson_aoclk_do_reset(struct reset_controller_dev *rcdev,
> +			       unsigned long id)
> +{
> +	struct meson_aoclk_reset_controller *rstc =
> +		container_of(rcdev, struct meson_aoclk_reset_controller, reset);
> +
> +	return regmap_write(rstc->regmap, rstc->data->reset_reg,
> +			    BIT(rstc->data->reset[id]));
> +}
> +
> +static const struct reset_control_ops meson_aoclk_reset_ops = {
> +	.reset = meson_aoclk_do_reset,
> +};
> +
> +int meson_aoclkc_probe(struct platform_device *pdev)
> +{
> +	struct meson_aoclk_reset_controller *rstc;
> +	struct meson_aoclk_data *data;
> +	struct device *dev = &pdev->dev;
> +	struct regmap *regmap;
> +	int ret, clkid;
> +
> +	data = (struct meson_aoclk_data *) of_device_get_match_data(dev);
> +	if (!data)
> +		return -ENODEV;
> +
> +	rstc = devm_kzalloc(dev, sizeof(*rstc), GFP_KERNEL);
> +	if (!rstc)
> +		return -ENOMEM;
> +
> +	regmap = syscon_node_to_regmap(of_get_parent(dev->of_node));
> +	if (IS_ERR(regmap)) {
> +		dev_err(dev, "failed to get regmap\n");
> +		return PTR_ERR(regmap);
> +	}
> +
> +	/* Reset Controller */
> +	rstc->data = data;
> +	rstc->regmap = regmap;
> +	rstc->reset.ops = &meson_aoclk_reset_ops;
> +	rstc->reset.nr_resets = data->num_reset,
> +	rstc->reset.of_node = dev->of_node;
> +	ret = devm_reset_controller_register(dev, &rstc->reset);
> +	if (ret) {
> +		dev_err(dev, "failed to register reset controller\n");
> +		return ret;
> +	}
> +
> +	/*
> +	 * Populate regmap and register all clks
> +	 */
> +	for (clkid = 0; clkid < data->num_clks; clkid++) {
> +		data->clks[clkid]->map = regmap;
> +
> +		ret = devm_clk_hw_register(dev, data->hw_data->hws[clkid]);
> +		if (ret)
> +			return ret;
> +	}
> +
> +	return devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get,
> +		(void *) data->hw_data);
> +}
> diff --git a/drivers/clk/meson/meson-aoclk.h b/drivers/clk/meson/meson-aoclk.h
> new file mode 100644
> index 000000000000..ec59e027dd37
> --- /dev/null
> +++ b/drivers/clk/meson/meson-aoclk.h
> @@ -0,0 +1,35 @@
> +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
> +/*
> + * Copyright (c) 2017 BayLibre, SAS
> + * Author: Neil Armstrong <narmstrong at baylibre.com>
> + *
> + * Copyright (c) 2018 Amlogic, inc.
> + * Author: Qiufang Dai <qiufang.dai at amlogic.com>
> + * Author: Yixun Lan <yixun.lan at amlogic.com>
> + */
> +
> +#ifndef __MESON_AOCLK_H__
> +#define __MESON_AOCLK_H__
> +
> +#include <linux/platform_device.h>
> +#include <linux/reset-controller.h>
> +#include "clk-regmap.h"
> +
> +struct meson_aoclk_data {
> +	const unsigned int			reset_reg;
> +	const int				num_reset;
> +	const unsigned int			*reset;
> +	int					num_clks;
> +	struct clk_regmap			**clks;
> +	const struct clk_hw_onecell_data	*hw_data;
> +};
> +
> +struct meson_aoclk_reset_controller {
> +	struct reset_controller_dev		reset;
> +	const struct meson_aoclk_data		*data;
> +	struct regmap				*regmap;
> +};
> +
> +int meson_aoclkc_probe(struct platform_device *pdev);
> +#endif
> +



From jbrunet at baylibre.com  Mon Apr 16 04:45:39 2018
From: jbrunet at baylibre.com (Jerome Brunet)
Date: Mon, 16 Apr 2018 13:45:39 +0200
Subject: [PATCH v5 5/7] clk: meson-axg: Add AO Clock and Reset
 controller driver
In-Reply-To: <20180409143749.71197-6-yixun.lan@amlogic.com>
References: <20180409143749.71197-1-yixun.lan@amlogic.com>
 <20180409143749.71197-6-yixun.lan@amlogic.com>
Message-ID: <1523879139.2601.40.camel@baylibre.com>

On Mon, 2018-04-09 at 22:37 +0800, Yixun Lan wrote:
> From: Qiufang Dai <qiufang.dai at amlogic.com>
> 
> Adds a Clock and Reset controller driver for the Always-On part
> of the Amlogic Meson-AXG SoC.
> 
> Signed-off-by: Qiufang Dai <qiufang.dai at amlogic.com>
> Signed-off-by: Yixun Lan <yixun.lan at amlogic.com>
> ---
>  drivers/clk/meson/Kconfig     |   1 +
>  drivers/clk/meson/Makefile    |   2 +-
>  drivers/clk/meson/axg-aoclk.c | 164 ++++++++++++++++++++++++++++++++++++++++++
>  drivers/clk/meson/axg-aoclk.h |  31 ++++++++
>  4 files changed, 197 insertions(+), 1 deletion(-)
>  create mode 100644 drivers/clk/meson/axg-aoclk.c
>  create mode 100644 drivers/clk/meson/axg-aoclk.h
> 
> diff --git a/drivers/clk/meson/Kconfig b/drivers/clk/meson/Kconfig
> index fddc7ec7b820..815659eebea3 100644
> --- a/drivers/clk/meson/Kconfig
> +++ b/drivers/clk/meson/Kconfig
> @@ -38,6 +38,7 @@ config COMMON_CLK_AXG
>  	bool
>  	depends on COMMON_CLK_AMLOGIC
>  	select RESET_CONTROLLER
> +	select COMMON_CLK_MESON_AO
>  	select COMMON_CLK_REGMAP_MESON
>  	select MFD_SYSCON
>  	help
> diff --git a/drivers/clk/meson/Makefile b/drivers/clk/meson/Makefile
> index 0a8df284f4e7..d0d13aeb369a 100644
> --- a/drivers/clk/meson/Makefile
> +++ b/drivers/clk/meson/Makefile
> @@ -6,5 +6,5 @@ obj-$(CONFIG_COMMON_CLK_AMLOGIC) += clk-pll.o clk-mpll.o clk-audio-divider.o
>  obj-$(CONFIG_COMMON_CLK_MESON_AO) += meson-aoclk.o
>  obj-$(CONFIG_COMMON_CLK_MESON8B) += meson8b.o
>  obj-$(CONFIG_COMMON_CLK_GXBB)	 += gxbb.o gxbb-aoclk.o gxbb-aoclk-32k.o
> -obj-$(CONFIG_COMMON_CLK_AXG)	 += axg.o
> +obj-$(CONFIG_COMMON_CLK_AXG)	 += axg.o axg-aoclk.o
>  obj-$(CONFIG_COMMON_CLK_REGMAP_MESON)	+= clk-regmap.o
> diff --git a/drivers/clk/meson/axg-aoclk.c b/drivers/clk/meson/axg-aoclk.c
> new file mode 100644
> index 000000000000..cb56d809d3df
> --- /dev/null
> +++ b/drivers/clk/meson/axg-aoclk.c
> @@ -0,0 +1,164 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Amlogic Meson-AXG Clock Controller Driver
> + *
> + * Copyright (c) 2016 Baylibre SAS.
> + * Author: Michael Turquette <mturquette at baylibre.com>
> + *
> + * Copyright (c) 2018 Amlogic, inc.
> + * Author: Qiufang Dai <qiufang.dai at amlogic.com>
> + */
> +#include <linux/clk-provider.h>
> +#include <linux/platform_device.h>
> +#include <linux/reset-controller.h>
> +#include <linux/mfd/syscon.h>
> +#include <linux/init.h>
Not required 

> +#include "clkc.h"
Why do you need this? looks like clk-regmap.h would be enough here ?

> +#include "axg-aoclk.h"
> +
> +#define AXG_AO_GATE(_name, _bit)					\
> +static struct clk_regmap _name##_ao = {					\
> +	.data = &(struct clk_regmap_gate_data) {			\
> +		.offset = (AO_RTI_GEN_CNTL_REG0),			\
> +		.bit_idx = (_bit),					\
> +	},								\
> +	.hw.init = &(struct clk_init_data) {				\
> +		.name = #_name "_ao",					\
> +		.ops = &clk_regmap_gate_ops,				\
> +		.parent_names = (const char *[]){ "clk81" },		\
> +		.num_parents = 1,					\
> +		.flags = CLK_IGNORE_UNUSED,				\
> +	},								\
> +}
> +
> +AXG_AO_GATE(remote, 0);
> +AXG_AO_GATE(i2c_master, 1);
> +AXG_AO_GATE(i2c_slave, 2);
> +AXG_AO_GATE(uart1, 3);
> +AXG_AO_GATE(uart2, 5);
> +AXG_AO_GATE(ir_blaster, 6);
> +AXG_AO_GATE(saradc, 7);
> +
> +static struct clk_regmap ao_clk81 = {
> +	.data = &(struct clk_regmap_mux_data) {
> +		.offset = AO_RTI_PWR_CNTL_REG0,
> +		.mask = 0x1,
> +		.shift = 8,
> +	},
> +	.hw.init = &(struct clk_init_data){
> +		.name = "ao_clk81",
> +		.ops = &clk_regmap_mux_ro_ops,
> +		.parent_names = (const char *[]){ "clk81", "ao_alt_xtal"},
> +		.num_parents = 2,
> +	},
> +};
> +
> +static struct clk_regmap axg_saradc_mux = {
> +	.data = &(struct clk_regmap_mux_data) {
> +		.offset = AO_SAR_CLK,
> +		.mask = 0x3,
> +		.shift = 9,
> +	},
> +	.hw.init = &(struct clk_init_data){
> +		.name = "axg_saradc_mux",
> +		.ops = &clk_regmap_mux_ops,
> +		.parent_names = (const char *[]){ "xtal", "ao_clk81" },
> +		.num_parents = 2,
> +	},
> +};
> +
> +static struct clk_regmap axg_saradc_div = {
> +	.data = &(struct clk_regmap_div_data) {
> +		.offset = AO_SAR_CLK,
> +		.shift = 0,
> +		.width = 8,
> +	},
> +	.hw.init = &(struct clk_init_data){
> +		.name = "axg_saradc_div",
> +		.ops = &clk_regmap_divider_ops,
> +		.parent_names = (const char *[]){ "axg_saradc_mux" },
> +		.num_parents = 1,
> +		.flags = CLK_SET_RATE_PARENT,
> +	},
> +};
> +
> +static struct clk_regmap axg_saradc_gate = {
> +	.data = &(struct clk_regmap_gate_data) {
> +		.offset = AO_SAR_CLK,
> +		.bit_idx = 8,
> +	},
> +	.hw.init = &(struct clk_init_data){
> +		.name = "axg_saradc_gate",
> +		.ops = &clk_regmap_gate_ops,
> +		.parent_names = (const char *[]){ "axg_saradc_div" },
> +		.num_parents = 1,
> +		.flags = CLK_SET_RATE_PARENT,
> +	},
> +};
> +
> +static const unsigned int axg_aoclk_reset[] = {
> +	[RESET_AO_REMOTE] = 16,
> +	[RESET_AO_I2C_MASTER] = 18,
> +	[RESET_AO_I2C_SLAVE] = 19,
> +	[RESET_AO_UART1] = 17,
> +	[RESET_AO_UART2] = 22,
> +	[RESET_AO_IR_BLASTER] = 23,
> +};
> +
> +static struct clk_regmap *axg_aoclk_regmap[] = {
> +	[CLKID_AO_REMOTE]	= &remote_ao,
> +	[CLKID_AO_I2C_MASTER]	= &i2c_master_ao,
> +	[CLKID_AO_I2C_SLAVE]	= &i2c_slave_ao,
> +	[CLKID_AO_UART1]	= &uart1_ao,
> +	[CLKID_AO_UART2]	= &uart2_ao,
> +	[CLKID_AO_IR_BLASTER]	= &ir_blaster_ao,
> +	[CLKID_AO_SAR_ADC]	= &saradc_ao,
> +	[CLKID_AO_CLK81]	= &ao_clk81,
> +	[CLKID_AO_SAR_ADC_SEL]	= &axg_saradc_mux,
> +	[CLKID_AO_SAR_ADC_DIV]	= &axg_saradc_div,
> +	[CLKID_AO_SAR_ADC_CLK]	= &axg_saradc_gate,

Naming is not very consistent here, sometimes ao at beginning, sometimes the
end, with or w/o axg.

I would prefer if you prefix everything with axg_ao[clk] 
ex: axg_aoclk_remote, axg_aoclk_saradc_mux, etc ...

> +};
> +
> +static const struct clk_hw_onecell_data axg_aoclk_onecell_data = {
> +	.hws = {
> +		[CLKID_AO_REMOTE]	= &remote_ao.hw,
> +		[CLKID_AO_I2C_MASTER]	= &i2c_master_ao.hw,
> +		[CLKID_AO_I2C_SLAVE]	= &i2c_slave_ao.hw,
> +		[CLKID_AO_UART1]	= &uart1_ao.hw,
> +		[CLKID_AO_UART2]	= &uart2_ao.hw,
> +		[CLKID_AO_IR_BLASTER]	= &ir_blaster_ao.hw,
> +		[CLKID_AO_SAR_ADC]	= &saradc_ao.hw,
> +		[CLKID_AO_CLK81]	= &ao_clk81.hw,
> +		[CLKID_AO_SAR_ADC_SEL]	= &axg_saradc_mux.hw,
> +		[CLKID_AO_SAR_ADC_DIV]	= &axg_saradc_div.hw,
> +		[CLKID_AO_SAR_ADC_CLK]	= &axg_saradc_gate.hw,
> +	},
> +	.num = NR_CLKS,
> +};
> +
> +static const struct meson_aoclk_data axg_aoclkc_data = {
> +	.reset_reg	= AO_RTI_GEN_CNTL_REG0,
> +	.num_reset	= ARRAY_SIZE(axg_aoclk_reset),
> +	.reset		= axg_aoclk_reset,
> +	.num_clks	= ARRAY_SIZE(axg_aoclk_regmap),
> +	.clks		= axg_aoclk_regmap,
> +	.hw_data	= &axg_aoclk_onecell_data,
> +};
> +
> +static const struct of_device_id axg_aoclkc_match_table[] = {
> +	{
> +		.compatible	= "amlogic,meson-axg-aoclkc",
> +		.data		= &axg_aoclkc_data,
> +	},
> +	{ }
> +};
> +
> +static struct platform_driver axg_aoclkc_driver = {
> +	.probe		= meson_aoclkc_probe,
> +	.driver		= {
> +		.name	= "axg-aoclkc",
> +		.of_match_table = axg_aoclkc_match_table,
> +	},
> +};
> +
> +builtin_platform_driver(axg_aoclkc_driver);
> diff --git a/drivers/clk/meson/axg-aoclk.h b/drivers/clk/meson/axg-aoclk.h
> new file mode 100644
> index 000000000000..396cd3023064
> --- /dev/null
> +++ b/drivers/clk/meson/axg-aoclk.h
> @@ -0,0 +1,31 @@
> +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
> +/*
> + * Copyright (c) 2017 BayLibre, SAS
> + * Author: Neil Armstrong <narmstrong at baylibre.com>
> + *
> + * Copyright (c) 2018 Amlogic, inc.
> + * Author: Qiufang Dai <qiufang.dai at amlogic.com>
> + */
> +
> +#ifndef __AXG_AOCLKC_H
> +#define __AXG_AOCLKC_H
> +
> +#include "meson-aoclk.h"
> +
> +#define NR_CLKS	11
> +/* AO Configuration Clock registers offsets
> + * Register offsets from the data sheet must be multiplied by 4.
> + */
> +#define AO_RTI_PWR_CNTL_REG1	0x0C
> +#define AO_RTI_PWR_CNTL_REG0	0x10
> +#define AO_RTI_GEN_CNTL_REG0	0x40
> +#define AO_OSCIN_CNTL		0x58
> +#define AO_CRT_CLK_CNTL1	0x68
> +#define AO_SAR_CLK		0x90
> +#define AO_RTC_ALT_CLK_CNTL0	0x94
> +#define AO_RTC_ALT_CLK_CNTL1	0x98
> +
> +#include <dt-bindings/clock/axg-aoclkc.h>
> +#include <dt-bindings/reset/axg-aoclkc.h>
> +
> +#endif /* __AXG_AOCLKC_H */



From sboyd at kernel.org  Mon Apr 16 09:24:54 2018
From: sboyd at kernel.org (Stephen Boyd)
Date: Mon, 16 Apr 2018 09:24:54 -0700
Subject: [PATCH 0/2] clk: honor CLK_MUX_ROUND_CLOSEST in mux
In-Reply-To: <20180409135921.5617-1-jbrunet@baylibre.com>
References: <20180409135921.5617-1-jbrunet@baylibre.com>
Message-ID: <152389589448.51482.15489333464741262913@swboyd.mtv.corp.google.com>

Quoting Jerome Brunet (2018-04-09 06:59:19)
> CLK_MUX_ROUND_CLOSEST is part of clk_mux and meson's clk_regmap
> documentation, so it should be honored by the determine_rate() callback.
> 
> It is note the case ATM. The series fixes this problem.

I'll apply these for clk-fixes.


From jbrunet at baylibre.com  Mon Apr 16 23:40:35 2018
From: jbrunet at baylibre.com (Jerome Brunet)
Date: Tue, 17 Apr 2018 08:40:35 +0200
Subject: [PATCH] ARM64: dts: meson-axg: add tdm pins
Message-ID: <20180417064035.28776-1-jbrunet@baylibre.com>

Add tdm pins to amlogic's A113 device tree

Signed-off-by: Jerome Brunet <jbrunet at baylibre.com>
---
 arch/arm64/boot/dts/amlogic/meson-axg.dtsi | 245 +++++++++++++++++++++++++++++
 1 file changed, 245 insertions(+)

diff --git a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
index b58808eb3cc8..74013965e86a 100644
--- a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
@@ -660,6 +660,251 @@
 						function = "uart_ao_b_z";
 					};
 				};
+
+				mclk_b_pins: mclk_b {
+					mux {
+						groups = "mclk_b";
+						function = "mclk_b";
+					};
+				};
+
+				mclk_c_pins: mclk_c {
+					mux {
+						groups = "mclk_c";
+						function = "mclk_c";
+					};
+				};
+
+				tdma_sclk_pins: tdma_sclk {
+					mux {
+						groups = "tdma_sclk";
+						function = "tdma";
+					};
+				};
+
+				tdma_sclk_slv_pins: tdma_sclk_slv {
+					mux {
+						groups = "tdma_sclk_slv";
+						function = "tdma";
+					};
+				};
+
+				tdma_fs_pins: tdma_fs {
+					mux {
+						groups = "tdma_fs";
+						function = "tdma";
+					};
+				};
+
+				tdma_fs_slv_pins: tdma_fs_slv {
+					mux {
+						groups = "tdma_fs_slv";
+						function = "tdma";
+					};
+				};
+
+				tdma_din0_pins: tdma_din0 {
+					mux {
+						groups = "tdma_din0";
+						function = "tdma";
+					};
+				};
+
+				tdma_dout0_x14_pins: tdma_dout0_x14 {
+					mux {
+						groups = "tdma_dout0_x14";
+						function = "tdma";
+					};
+				};
+
+				tdma_dout0_x15_pins: tdma_dout0_x15 {
+					mux {
+						groups = "tdma_dout0_x15";
+						function = "tdma";
+					};
+				};
+
+				tdma_dout1_pins: tdma_dout1 {
+					mux {
+						groups = "tdma_dout1";
+						function = "tdma";
+					};
+				};
+
+				tdma_din1_pins: tdma_din1 {
+					mux {
+						groups = "tdma_din1";
+						function = "tdma";
+					};
+				};
+
+				tdmb_sclk_pins: tdmb_sclk {
+					mux {
+						groups = "tdmb_sclk";
+						function = "tdmb";
+					};
+				};
+
+				tdmb_sclk_slv_pins: tdmb_sclk_slv {
+					mux {
+						groups = "tdmb_sclk_slv";
+						function = "tdmb";
+					};
+				};
+
+				tdmb_fs_pins: tdmb_fs {
+					mux {
+						groups = "tdmb_fs";
+						function = "tdmb";
+					};
+				};
+
+				tdmb_fs_slv_pins: tdmb_fs_slv {
+					mux {
+						groups = "tdmb_fs_slv";
+						function = "tdmb";
+					};
+				};
+
+				tdmb_din0_pins: tdmb_din0 {
+					mux {
+						groups = "tdmb_din0";
+						function = "tdmb";
+					};
+				};
+
+				tdmb_dout0_pins: tdmb_dout0 {
+					mux {
+						groups = "tdmb_dout0";
+						function = "tdmb";
+					};
+				};
+
+				tdmb_din1_pins: tdmb_din1 {
+					mux {
+						groups = "tdmb_din1";
+						function = "tdmb";
+					};
+				};
+
+				tdmb_dout1_pins: tdmb_dout1 {
+					mux {
+						groups = "tdmb_dout1";
+						function = "tdmb";
+					};
+				};
+
+				tdmb_din2_pins: tdmb_din2 {
+					mux {
+						groups = "tdmb_din2";
+						function = "tdmb";
+					};
+				};
+
+				tdmb_dout2_pins: tdmb_dout2 {
+					mux {
+						groups = "tdmb_dout2";
+						function = "tdmb";
+					};
+				};
+
+				tdmb_din3_pins: tdmb_din3 {
+					mux {
+						groups = "tdmb_din3";
+						function = "tdmb";
+					};
+				};
+
+				tdmb_dout3_pins: tdmb_dout3 {
+					mux {
+						groups = "tdmb_dout3";
+						function = "tdmb";
+					};
+				};
+
+				tdmc_sclk_pins: tdmc_sclk {
+					mux {
+						groups = "tdmc_sclk";
+						function = "tdmc";
+					};
+				};
+
+				tdmc_sclk_slv_pins: tdmc_sclk_slv {
+					mux {
+						groups = "tdmc_sclk_slv";
+						function = "tdmc";
+					};
+				};
+
+				tdmc_fs_pins: tdmc_fs {
+					mux {
+						groups = "tdmc_fs";
+						function = "tdmc";
+					};
+				};
+
+				tdmc_fs_slv_pins: tdmc_fs_slv {
+					mux {
+						groups = "tdmc_fs_slv";
+						function = "tdmc";
+					};
+				};
+
+				tdmc_din0_pins: tdmc_din0 {
+					mux {
+						groups = "tdmc_din0";
+						function = "tdmc";
+					};
+				};
+
+				tdmc_dout0_pins: tdmc_dout0 {
+					mux {
+						groups = "tdmc_dout0";
+						function = "tdmc";
+					};
+				};
+
+				tdmc_din1_pins: tdmc_din1 {
+					mux {
+						groups = "tdmc_din1";
+						function = "tdmc";
+					};
+				};
+
+				tdmc_dout1_pins: tdmc_dout1 {
+					mux {
+						groups = "tdmc_dout1";
+						function = "tdmc";
+					};
+				};
+
+				tdmc_din2_pins: tdmc_din2 {
+					mux {
+						groups = "tdmc_din2";
+						function = "tdmc";
+					};
+				};
+
+				tdmc_dout2_pins: tdmc_dout2 {
+					mux {
+						groups = "tdmc_dout2";
+						function = "tdmc";
+					};
+				};
+
+				tdmc_din3_pins: tdmc_din3 {
+					mux {
+						groups = "tdmc_din3";
+						function = "tdmc";
+					};
+				};
+
+				tdmc_dout3_pins: tdmc_dout3 {
+					mux {
+						groups = "tdmc_dout3";
+						function = "tdmc";
+					};
+				};
 			};
 		};
 
-- 
2.14.3



From narmstrong at baylibre.com  Tue Apr 17 00:34:18 2018
From: narmstrong at baylibre.com (Neil Armstrong)
Date: Tue, 17 Apr 2018 09:34:18 +0200
Subject: [PATCH] reset: fix bulk API when DM_RESET is disabled
In-Reply-To: <CAPnjgZ3SY1DV4XUz6KZMhngAKkSq82WFzs0f-vubgMap4XOqJQ@mail.gmail.com>
References: <1523520199-12341-1-git-send-email-narmstrong@baylibre.com>
 <CAPnjgZ3SY1DV4XUz6KZMhngAKkSq82WFzs0f-vubgMap4XOqJQ@mail.gmail.com>
Message-ID: <c43b9188-2a6d-c433-a977-112cc9c0fb58@baylibre.com>

On 12/04/2018 18:41, Simon Glass wrote:
> On 12 April 2018 at 02:03, Neil Armstrong <narmstrong at baylibre.com> wrote:
>> In the commit "reset: Add get/assert/deassert/release for bulk of reset signals"
>> the disabled reset_release_bulk() and reset_get_bulk() used the wrong
>> struct clk_bulk instead of struct reset_ctl_bulk.
>>
>> Fixes: 0c28233903b5 ("reset: Add get/assert/deassert/release for bulk of reset signals")
>> Reported-by: Jean-Jacques Hiblot <jjhiblot at ti.com>
>> Signed-off-by: Neil Armstrong <narmstrong at baylibre.com>
>> ---
>>  include/reset.h | 5 +++--
>>  1 file changed, 3 insertions(+), 2 deletions(-)
> 
> Reviewed-by: Simon Glass <sjg at chromium.org>
> 
> We don't have build coverage for this at the moment I suppose. It
> would be a bit of pain to add that with sandbox, although I wonder if
> it could be done with some horrible #define hackery in a C file that
> includes this header?
> 
> - Simon
> 

It could but it will be horrible indeed.

Neil


From yixun.lan at amlogic.com  Tue Apr 17 01:16:39 2018
From: yixun.lan at amlogic.com (Yixun Lan)
Date: Tue, 17 Apr 2018 16:16:39 +0800
Subject: [PATCH v5 2/7] clk: meson: aoclk: refactor common code into
 dedicated file
In-Reply-To: <1523875084.2601.28.camel@baylibre.com>
References: <20180409143749.71197-1-yixun.lan@amlogic.com>
 <20180409143749.71197-3-yixun.lan@amlogic.com>
 <1523875084.2601.28.camel@baylibre.com>
Message-ID: <759078f5-fcbf-9ef1-6945-67d9d951d8eb@amlogic.com>

Hi Jerome

On 04/16/18 18:38, Jerome Brunet wrote:
>> +	 */
>> +	for (clkid = 0; clkid < data->num_clks; clkid++) {
>> +		data->clks[clkid]->map = regmap;
>> +
>> +		ret = devm_clk_hw_register(dev, data->hw_data->hws[clkid]);
>> +		if (ret)
>> +			return ret;
>> +	}
>> +
>> +	return devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get,
>> +		(void *) data->hw_data);
>> +}
> Missing new line here. Please run checkpatch and pay attention to git warnings
> about whitespace errors.
> 


I think we actually need to avoid this extra new line, or what's the
benefits with new line?

and besides? I didn't see any complaint from checkpatch.pl ..

 ./scripts/checkpatch.pl
0002-clk-meson-aoclk-refactor-common-code-into-dedicated-.patch
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#235:
new file mode 100644

total: 0 errors, 1 warnings, 302 lines checked

NOTE: For some of the reported defects, checkpatch may be able to
      mechanically convert to the typical style using --fix or
--fix-inplace.

0002-clk-meson-aoclk-refactor-common-code-into-dedicated-.patch has
style problems, please review.

NOTE: If any of the errors are false positives, please report
      them to the maintainer, see CHECKPATCH in MAINTAINERS.


Yixun


From yixun.lan at amlogic.com  Tue Apr 17 01:17:59 2018
From: yixun.lan at amlogic.com (Yixun Lan)
Date: Tue, 17 Apr 2018 16:17:59 +0800
Subject: [PATCH v5 2/7] clk: meson: aoclk: refactor common code into
 dedicated file
In-Reply-To: <1523878490.2601.34.camel@baylibre.com>
References: <20180409143749.71197-1-yixun.lan@amlogic.com>
 <20180409143749.71197-3-yixun.lan@amlogic.com>
 <1523878490.2601.34.camel@baylibre.com>
Message-ID: <461c1979-4d1f-0fcd-3323-d9cb4359b26d@amlogic.com>

Hi jerome

On 04/16/18 19:34, Jerome Brunet wrote:
> On Mon, 2018-04-09 at 22:37 +0800, Yixun Lan wrote:
>> We try to refactor the common code into one dedicated file,
>> while preparing to add new Meson-AXG aoclk driver, this would
>> help us to better share the code by all aoclk drivers.
>>
>> Suggested-by: Jerome Brunet <jbrunet at baylibre.com>
>> Signed-off-by: Yixun Lan <yixun.lan at amlogic.com>
>> ---
>>  drivers/clk/meson/Kconfig       |  7 ++++
>>  drivers/clk/meson/Makefile      |  1 +
>>  drivers/clk/meson/gxbb-aoclk.c  | 91 ++++++++++++++---------------------------
>>  drivers/clk/meson/gxbb-aoclk.h  |  7 ++++
>>  drivers/clk/meson/meson-aoclk.c | 82 +++++++++++++++++++++++++++++++++++++
>>  drivers/clk/meson/meson-aoclk.h | 35 ++++++++++++++++
>>  6 files changed, 163 insertions(+), 60 deletions(-)
>>  create mode 100644 drivers/clk/meson/meson-aoclk.c
>>  create mode 100644 drivers/clk/meson/meson-aoclk.h
>>
>> diff --git a/drivers/clk/meson/Kconfig b/drivers/clk/meson/Kconfig
>> index d5cbec522aec..fddc7ec7b820 100644
>> --- a/drivers/clk/meson/Kconfig
>> +++ b/drivers/clk/meson/Kconfig
>> @@ -3,6 +3,12 @@ config COMMON_CLK_AMLOGIC
>>  	depends on OF
>>  	depends on ARCH_MESON || COMPILE_TEST
>>  
>> +config COMMON_CLK_MESON_AO
>> +	bool
>> +	depends on OF
>> +	depends on ARCH_MESON || COMPILE_TEST
>> +	select COMMON_CLK_REGMAP_MESON
>> +
>>  config COMMON_CLK_REGMAP_MESON
>>  	bool
>>  	select REGMAP
>> @@ -21,6 +27,7 @@ config COMMON_CLK_GXBB
>>  	bool
>>  	depends on COMMON_CLK_AMLOGIC
>>  	select RESET_CONTROLLER
>> +	select COMMON_CLK_MESON_AO
>>  	select COMMON_CLK_REGMAP_MESON
>>  	select MFD_SYSCON
>>  	help
>> diff --git a/drivers/clk/meson/Makefile b/drivers/clk/meson/Makefile
>> index ffee82e60b7a..0a8df284f4e7 100644
>> --- a/drivers/clk/meson/Makefile
>> +++ b/drivers/clk/meson/Makefile
>> @@ -3,6 +3,7 @@
>>  #
>>  
>>  obj-$(CONFIG_COMMON_CLK_AMLOGIC) += clk-pll.o clk-mpll.o clk-audio-divider.o
>> +obj-$(CONFIG_COMMON_CLK_MESON_AO) += meson-aoclk.o
>>  obj-$(CONFIG_COMMON_CLK_MESON8B) += meson8b.o
>>  obj-$(CONFIG_COMMON_CLK_GXBB)	 += gxbb.o gxbb-aoclk.o gxbb-aoclk-32k.o
>>  obj-$(CONFIG_COMMON_CLK_AXG)	 += axg.o
>> diff --git a/drivers/clk/meson/gxbb-aoclk.c b/drivers/clk/meson/gxbb-aoclk.c
>> index eebb580b9e0f..f2e0640a7f74 100644
>> --- a/drivers/clk/meson/gxbb-aoclk.c
>> +++ b/drivers/clk/meson/gxbb-aoclk.c
>> @@ -52,39 +52,13 @@
>>   * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
>>   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
>>   */
>> -#include <linux/clk-provider.h>
>> -#include <linux/of_address.h>
>>  #include <linux/platform_device.h>
> 
>>  #include <linux/reset-controller.h>
> Not required anymore
> 
will remove

>>  #include <linux/mfd/syscon.h>
>> -#include <linux/regmap.h>
>>  #include <linux/init.h>
> Not required
> 
will remove
>> -#include <linux/delay.h>
> 
>> -#include <dt-bindings/clock/gxbb-aoclkc.h>
>> -#include <dt-bindings/reset/gxbb-aoclkc.h>
> Please keep these 2 here
> 
 see comments below
>>  #include "clk-regmap.h"
>>  #include "gxbb-aoclk.h"
>>  
>> -struct gxbb_aoclk_reset_controller {
>> -	struct reset_controller_dev reset;
>> -	unsigned int *data;
>> -	struct regmap *regmap;
>> -};
>> -
>> -static int gxbb_aoclk_do_reset(struct reset_controller_dev *rcdev,
>> -			       unsigned long id)
>> -{
>> -	struct gxbb_aoclk_reset_controller *reset =
>> -		container_of(rcdev, struct gxbb_aoclk_reset_controller, reset);
>> -
>> -	return regmap_write(reset->regmap, AO_RTI_GEN_CNTL_REG0,
>> -			    BIT(reset->data[id]));
>> -}
>> -
>> -static const struct reset_control_ops gxbb_aoclk_reset_ops = {
>> -	.reset = gxbb_aoclk_do_reset,
>> -};
>> -
>>  #define GXBB_AO_GATE(_name, _bit)					\
>>  static struct clk_regmap _name##_ao = {					\
>>  	.data = &(struct clk_regmap_gate_data) {			\
>> @@ -117,7 +91,7 @@ static struct aoclk_cec_32k cec_32k_ao = {
>>  	},
>>  };
>>  
>> -static unsigned int gxbb_aoclk_reset[] = {
>> +static const unsigned int gxbb_aoclk_reset[] = {
>>  	[RESET_AO_REMOTE] = 16,
>>  	[RESET_AO_I2C_MASTER] = 18,
>>  	[RESET_AO_I2C_SLAVE] = 19,
>> @@ -135,7 +109,7 @@ static struct clk_regmap *gxbb_aoclk_gate[] = {
>>  	[CLKID_AO_IR_BLASTER] = &ir_blaster_ao,
>>  };
>>  
>> -static struct clk_hw_onecell_data gxbb_aoclk_onecell_data = {
>> +static const struct clk_hw_onecell_data gxbb_aoclk_onecell_data = {
>>  	.hws = {
>>  		[CLKID_AO_REMOTE] = &remote_ao.hw,
>>  		[CLKID_AO_I2C_MASTER] = &i2c_master_ao.hw,
>> @@ -145,58 +119,55 @@ static struct clk_hw_onecell_data gxbb_aoclk_onecell_data = {
>>  		[CLKID_AO_IR_BLASTER] = &ir_blaster_ao.hw,
>>  		[CLKID_AO_CEC_32K] = &cec_32k_ao.hw,
>>  	},
>> -	.num = 7,
>> +	.num = NR_CLKS,
>>  };
>>  
>> -static int gxbb_aoclkc_probe(struct platform_device *pdev)
>> +static int gxbb_register_cec_ao_32k(struct platform_device *pdev)
>>  {
>> -	struct gxbb_aoclk_reset_controller *rstc;
>>  	struct device *dev = &pdev->dev;
>>  	struct regmap *regmap;
>> -	int ret, clkid;
>> -
>> -	rstc = devm_kzalloc(dev, sizeof(*rstc), GFP_KERNEL);
>> -	if (!rstc)
>> -		return -ENOMEM;
>> +	int ret;
>>  
>>  	regmap = syscon_node_to_regmap(of_get_parent(dev->of_node));
>>  	if (IS_ERR(regmap)) {
>>  		dev_err(dev, "failed to get regmap\n");
>> -		return -ENODEV;
>> -	}
>> -
>> -	/* Reset Controller */
>> -	rstc->regmap = regmap;
>> -	rstc->data = gxbb_aoclk_reset;
>> -	rstc->reset.ops = &gxbb_aoclk_reset_ops;
>> -	rstc->reset.nr_resets = ARRAY_SIZE(gxbb_aoclk_reset);
>> -	rstc->reset.of_node = dev->of_node;
>> -	ret = devm_reset_controller_register(dev, &rstc->reset);
>> -
>> -	/*
>> -	 * Populate regmap and register all clks
>> -	 */
>> -	for (clkid = 0; clkid < ARRAY_SIZE(gxbb_aoclk_gate); clkid++) {
>> -		gxbb_aoclk_gate[clkid]->map = regmap;
>> -
>> -		ret = devm_clk_hw_register(dev,
>> -					   gxbb_aoclk_onecell_data.hws[clkid]);
>> -		if (ret)
>> -			return ret;
>> +		return PTR_ERR(regmap);
>>  	}
>>  
>>  	/* Specific clocks */
>>  	cec_32k_ao.regmap = regmap;
>>  	ret = devm_clk_hw_register(dev, &cec_32k_ao.hw);
>> +	if (ret) {
>> +		dev_err(&pdev->dev, "clk cec_32k_ao register failed.\n");
>> +		return ret;
>> +	}
>> +
>> +	return 0;
>> +}
>> +
>> +static const struct meson_aoclk_data gxbb_aoclkc_data = {
>> +	.reset_reg	= AO_RTI_GEN_CNTL_REG0,
>> +	.num_reset	= ARRAY_SIZE(gxbb_aoclk_reset),
>> +	.reset		= gxbb_aoclk_reset,
>> +	.num_clks	= ARRAY_SIZE(gxbb_aoclk_gate),
>> +	.clks		= gxbb_aoclk_gate,
>> +	.hw_data	= &gxbb_aoclk_onecell_data,
>> +};
>> +
>> +static int gxbb_aoclkc_probe(struct platform_device *pdev)
>> +{
>> +	int ret = gxbb_register_cec_ao_32k(pdev);
>>  	if (ret)
>>  		return ret;
>>  
>> -	return devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get,
>> -			&gxbb_aoclk_onecell_data);
>> +	return meson_aoclkc_probe(pdev);
>>  }
>>  
>>  static const struct of_device_id gxbb_aoclkc_match_table[] = {
>> -	{ .compatible = "amlogic,meson-gx-aoclkc" },
>> +	{
>> +		.compatible	= "amlogic,meson-gx-aoclkc",
>> +		.data		= &gxbb_aoclkc_data,
>> +	},
>>  	{ }
>>  };
>>  
>> diff --git a/drivers/clk/meson/gxbb-aoclk.h b/drivers/clk/meson/gxbb-aoclk.h
>> index badc4c22b4ee..b031f1a0213e 100644
>> --- a/drivers/clk/meson/gxbb-aoclk.h
>> +++ b/drivers/clk/meson/gxbb-aoclk.h
>> @@ -8,6 +8,10 @@
>>  #ifndef __GXBB_AOCLKC_H
>>  #define __GXBB_AOCLKC_H
>>  
>> +#include "meson-aoclk.h"
> 
> You are not using any of the structure defined in meson-aoclk.h in here.
> Why do you include this here ?
> 
my initial intention was trying to avoid inlcude it in gxbb-aoclk.c
I could move to gxbb-aoclk.c if you prefer?

>> +
>> +#define NR_CLKS	7
>> +
>>  /* AO Configuration Clock registers offsets */
>>  #define AO_RTI_PWR_CNTL_REG1	0x0c
>>  #define AO_RTI_PWR_CNTL_REG0	0x10
>> @@ -26,4 +30,7 @@ struct aoclk_cec_32k {
>>  
>>  extern const struct clk_ops meson_aoclk_cec_32k_ops;
>>  
>> +#include <dt-bindings/clock/gxbb-aoclkc.h>
>> +#include <dt-bindings/reset/gxbb-aoclkc.h>
> Please drop this.
> 
according to your last comment[1], you suggested to put these files
here? and I thought it was a good idea..

or do you think it's kind of messy if we put too many private files into
the C file (which has similar functionality and can be squashed together
?) ..


[1] https://lkml.kernel.org/r/1518449571.2883.30.camel at baylibre.com

> +#include <dt-bindings/clock/axg-aoclkc.h>
> +#include <dt-bindings/reset/axg-aoclkc.h>

I think those should be included in the same fashion as axg.h, gxbb.h and
meson8.h ... which is at the end of the private header.


>> +
>>  #endif /* __GXBB_AOCLKC_H */
>> diff --git a/drivers/clk/meson/meson-aoclk.c b/drivers/clk/meson/meson-aoclk.c
>> new file mode 100644
>> index 000000000000..74338ef0a62b
>> --- /dev/null
>> +++ b/drivers/clk/meson/meson-aoclk.c
>> @@ -0,0 +1,82 @@
>> +// SPDX-License-Identifier: GPL-2.0+
>> +/*
>> + * Amlogic Meson-AXG Clock Controller Driver
>> + *
>> + * Copyright (c) 2016 BayLibre, SAS.
>> + * Author: Neil Armstrong <narmstrong at baylibre.com>
>> + *
>> + * Copyright (c) 2018 Amlogic, inc.
>> + * Author: Qiufang Dai <qiufang.dai at amlogic.com>
>> + * Author: Yixun Lan <yixun.lan at amlogic.com>
>> + */
>> +
>> +#include <linux/platform_device.h>
>> +#include <linux/reset-controller.h>
>> +#include <linux/mfd/syscon.h>
>> +#include <linux/init.h>
> Not required
> 
will drop it

>> +#include <linux/of_device.h>
>> +#include "clk-regmap.h"
>> +#include "meson-aoclk.h"
>> +
>> +static int meson_aoclk_do_reset(struct reset_controller_dev *rcdev,
>> +			       unsigned long id)
>> +{
>> +	struct meson_aoclk_reset_controller *rstc =
>> +		container_of(rcdev, struct meson_aoclk_reset_controller, reset);
>> +
>> +	return regmap_write(rstc->regmap, rstc->data->reset_reg,
>> +			    BIT(rstc->data->reset[id]));
>> +}
>> +
>> +static const struct reset_control_ops meson_aoclk_reset_ops = {
>> +	.reset = meson_aoclk_do_reset,
>> +};
>> +
>> +int meson_aoclkc_probe(struct platform_device *pdev)
>> +{
>> +	struct meson_aoclk_reset_controller *rstc;
>> +	struct meson_aoclk_data *data;
>> +	struct device *dev = &pdev->dev;
>> +	struct regmap *regmap;
>> +	int ret, clkid;
>> +
>> +	data = (struct meson_aoclk_data *) of_device_get_match_data(dev);
>> +	if (!data)
>> +		return -ENODEV;
>> +
>> +	rstc = devm_kzalloc(dev, sizeof(*rstc), GFP_KERNEL);
>> +	if (!rstc)
>> +		return -ENOMEM;
>> +
>> +	regmap = syscon_node_to_regmap(of_get_parent(dev->of_node));
>> +	if (IS_ERR(regmap)) {
>> +		dev_err(dev, "failed to get regmap\n");
>> +		return PTR_ERR(regmap);
>> +	}
>> +
>> +	/* Reset Controller */
>> +	rstc->data = data;
>> +	rstc->regmap = regmap;
>> +	rstc->reset.ops = &meson_aoclk_reset_ops;
>> +	rstc->reset.nr_resets = data->num_reset,
>> +	rstc->reset.of_node = dev->of_node;
>> +	ret = devm_reset_controller_register(dev, &rstc->reset);
>> +	if (ret) {
>> +		dev_err(dev, "failed to register reset controller\n");
>> +		return ret;
>> +	}
>> +
>> +	/*
>> +	 * Populate regmap and register all clks
>> +	 */
>> +	for (clkid = 0; clkid < data->num_clks; clkid++) {
>> +		data->clks[clkid]->map = regmap;
>> +
>> +		ret = devm_clk_hw_register(dev, data->hw_data->hws[clkid]);
>> +		if (ret)
>> +			return ret;
>> +	}
>> +
>> +	return devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get,
>> +		(void *) data->hw_data);
>> +}
>> diff --git a/drivers/clk/meson/meson-aoclk.h b/drivers/clk/meson/meson-aoclk.h
>> new file mode 100644
>> index 000000000000..ec59e027dd37
>> --- /dev/null
>> +++ b/drivers/clk/meson/meson-aoclk.h
>> @@ -0,0 +1,35 @@
>> +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
>> +/*
>> + * Copyright (c) 2017 BayLibre, SAS
>> + * Author: Neil Armstrong <narmstrong at baylibre.com>
>> + *
>> + * Copyright (c) 2018 Amlogic, inc.
>> + * Author: Qiufang Dai <qiufang.dai at amlogic.com>
>> + * Author: Yixun Lan <yixun.lan at amlogic.com>
>> + */
>> +
>> +#ifndef __MESON_AOCLK_H__
>> +#define __MESON_AOCLK_H__
>> +
>> +#include <linux/platform_device.h>
>> +#include <linux/reset-controller.h>
>> +#include "clk-regmap.h"
>> +
>> +struct meson_aoclk_data {
>> +	const unsigned int			reset_reg;
>> +	const int				num_reset;
>> +	const unsigned int			*reset;
>> +	int					num_clks;
>> +	struct clk_regmap			**clks;
>> +	const struct clk_hw_onecell_data	*hw_data;
>> +};
>> +
>> +struct meson_aoclk_reset_controller {
>> +	struct reset_controller_dev		reset;
>> +	const struct meson_aoclk_data		*data;
>> +	struct regmap				*regmap;
>> +};
>> +
>> +int meson_aoclkc_probe(struct platform_device *pdev);
>> +#endif
>> +
> 
> .
> 



From yixun.lan at amlogic.com  Tue Apr 17 01:18:30 2018
From: yixun.lan at amlogic.com (Yixun Lan)
Date: Tue, 17 Apr 2018 16:18:30 +0800
Subject: [PATCH v5 5/7] clk: meson-axg: Add AO Clock and Reset controller
 driver
In-Reply-To: <1523879139.2601.40.camel@baylibre.com>
References: <20180409143749.71197-1-yixun.lan@amlogic.com>
 <20180409143749.71197-6-yixun.lan@amlogic.com>
 <1523879139.2601.40.camel@baylibre.com>
Message-ID: <c06f4174-67ae-6d47-5881-1d5259e60bf7@amlogic.com>

Hi Jerome:

see my comments below

On 04/16/18 19:45, Jerome Brunet wrote:
> On Mon, 2018-04-09 at 22:37 +0800, Yixun Lan wrote:
>> From: Qiufang Dai <qiufang.dai at amlogic.com>
>>
>> Adds a Clock and Reset controller driver for the Always-On part
>> of the Amlogic Meson-AXG SoC.
>>
>> Signed-off-by: Qiufang Dai <qiufang.dai at amlogic.com>
>> Signed-off-by: Yixun Lan <yixun.lan at amlogic.com>
>> ---
>>  drivers/clk/meson/Kconfig     |   1 +
>>  drivers/clk/meson/Makefile    |   2 +-
>>  drivers/clk/meson/axg-aoclk.c | 164 ++++++++++++++++++++++++++++++++++++++++++
>>  drivers/clk/meson/axg-aoclk.h |  31 ++++++++
>>  4 files changed, 197 insertions(+), 1 deletion(-)
>>  create mode 100644 drivers/clk/meson/axg-aoclk.c
>>  create mode 100644 drivers/clk/meson/axg-aoclk.h
>>
>> diff --git a/drivers/clk/meson/Kconfig b/drivers/clk/meson/Kconfig
>> index fddc7ec7b820..815659eebea3 100644
>> --- a/drivers/clk/meson/Kconfig
>> +++ b/drivers/clk/meson/Kconfig
>> @@ -38,6 +38,7 @@ config COMMON_CLK_AXG
>>  	bool
>>  	depends on COMMON_CLK_AMLOGIC
>>  	select RESET_CONTROLLER
>> +	select COMMON_CLK_MESON_AO
>>  	select COMMON_CLK_REGMAP_MESON
>>  	select MFD_SYSCON
>>  	help
>> diff --git a/drivers/clk/meson/Makefile b/drivers/clk/meson/Makefile
>> index 0a8df284f4e7..d0d13aeb369a 100644
>> --- a/drivers/clk/meson/Makefile
>> +++ b/drivers/clk/meson/Makefile
>> @@ -6,5 +6,5 @@ obj-$(CONFIG_COMMON_CLK_AMLOGIC) += clk-pll.o clk-mpll.o clk-audio-divider.o
>>  obj-$(CONFIG_COMMON_CLK_MESON_AO) += meson-aoclk.o
>>  obj-$(CONFIG_COMMON_CLK_MESON8B) += meson8b.o
>>  obj-$(CONFIG_COMMON_CLK_GXBB)	 += gxbb.o gxbb-aoclk.o gxbb-aoclk-32k.o
>> -obj-$(CONFIG_COMMON_CLK_AXG)	 += axg.o
>> +obj-$(CONFIG_COMMON_CLK_AXG)	 += axg.o axg-aoclk.o
>>  obj-$(CONFIG_COMMON_CLK_REGMAP_MESON)	+= clk-regmap.o
>> diff --git a/drivers/clk/meson/axg-aoclk.c b/drivers/clk/meson/axg-aoclk.c
>> new file mode 100644
>> index 000000000000..cb56d809d3df
>> --- /dev/null
>> +++ b/drivers/clk/meson/axg-aoclk.c
>> @@ -0,0 +1,164 @@
>> +// SPDX-License-Identifier: GPL-2.0+
>> +/*
>> + * Amlogic Meson-AXG Clock Controller Driver
>> + *
>> + * Copyright (c) 2016 Baylibre SAS.
>> + * Author: Michael Turquette <mturquette at baylibre.com>
>> + *
>> + * Copyright (c) 2018 Amlogic, inc.
>> + * Author: Qiufang Dai <qiufang.dai at amlogic.com>
>> + */
>> +#include <linux/clk-provider.h>
>> +#include <linux/platform_device.h>
>> +#include <linux/reset-controller.h>
>> +#include <linux/mfd/syscon.h>
>> +#include <linux/init.h>
> Not required 
> 
will remove it

>> +#include "clkc.h"
> Why do you need this? looks like clk-regmap.h would be enough here ?
> 
you right, I will adjust

>> +#include "axg-aoclk.h"
>> +
>> +#define AXG_AO_GATE(_name, _bit)					\
>> +static struct clk_regmap _name##_ao = {					\
>> +	.data = &(struct clk_regmap_gate_data) {			\
>> +		.offset = (AO_RTI_GEN_CNTL_REG0),			\
>> +		.bit_idx = (_bit),					\
>> +	},								\
>> +	.hw.init = &(struct clk_init_data) {				\
>> +		.name = #_name "_ao",					\
>> +		.ops = &clk_regmap_gate_ops,				\
>> +		.parent_names = (const char *[]){ "clk81" },		\
>> +		.num_parents = 1,					\
>> +		.flags = CLK_IGNORE_UNUSED,				\
>> +	},								\
>> +}
>> +
>> +AXG_AO_GATE(remote, 0);
>> +AXG_AO_GATE(i2c_master, 1);
>> +AXG_AO_GATE(i2c_slave, 2);
>> +AXG_AO_GATE(uart1, 3);
>> +AXG_AO_GATE(uart2, 5);
>> +AXG_AO_GATE(ir_blaster, 6);
>> +AXG_AO_GATE(saradc, 7);
>> +
>> +static struct clk_regmap ao_clk81 = {
>> +	.data = &(struct clk_regmap_mux_data) {
>> +		.offset = AO_RTI_PWR_CNTL_REG0,
>> +		.mask = 0x1,
>> +		.shift = 8,
>> +	},
>> +	.hw.init = &(struct clk_init_data){
>> +		.name = "ao_clk81",
>> +		.ops = &clk_regmap_mux_ro_ops,
>> +		.parent_names = (const char *[]){ "clk81", "ao_alt_xtal"},
>> +		.num_parents = 2,
>> +	},
>> +};
>> +
>> +static struct clk_regmap axg_saradc_mux = {
>> +	.data = &(struct clk_regmap_mux_data) {
>> +		.offset = AO_SAR_CLK,
>> +		.mask = 0x3,
>> +		.shift = 9,
>> +	},
>> +	.hw.init = &(struct clk_init_data){
>> +		.name = "axg_saradc_mux",
>> +		.ops = &clk_regmap_mux_ops,
>> +		.parent_names = (const char *[]){ "xtal", "ao_clk81" },
>> +		.num_parents = 2,
>> +	},
>> +};
>> +
>> +static struct clk_regmap axg_saradc_div = {
>> +	.data = &(struct clk_regmap_div_data) {
>> +		.offset = AO_SAR_CLK,
>> +		.shift = 0,
>> +		.width = 8,
>> +	},
>> +	.hw.init = &(struct clk_init_data){
>> +		.name = "axg_saradc_div",
>> +		.ops = &clk_regmap_divider_ops,
>> +		.parent_names = (const char *[]){ "axg_saradc_mux" },
>> +		.num_parents = 1,
>> +		.flags = CLK_SET_RATE_PARENT,
>> +	},
>> +};
>> +
>> +static struct clk_regmap axg_saradc_gate = {
>> +	.data = &(struct clk_regmap_gate_data) {
>> +		.offset = AO_SAR_CLK,
>> +		.bit_idx = 8,
>> +	},
>> +	.hw.init = &(struct clk_init_data){
>> +		.name = "axg_saradc_gate",
>> +		.ops = &clk_regmap_gate_ops,
>> +		.parent_names = (const char *[]){ "axg_saradc_div" },
>> +		.num_parents = 1,
>> +		.flags = CLK_SET_RATE_PARENT,
>> +	},
>> +};
>> +
>> +static const unsigned int axg_aoclk_reset[] = {
>> +	[RESET_AO_REMOTE] = 16,
>> +	[RESET_AO_I2C_MASTER] = 18,
>> +	[RESET_AO_I2C_SLAVE] = 19,
>> +	[RESET_AO_UART1] = 17,
>> +	[RESET_AO_UART2] = 22,
>> +	[RESET_AO_IR_BLASTER] = 23,
>> +};
>> +
>> +static struct clk_regmap *axg_aoclk_regmap[] = {
>> +	[CLKID_AO_REMOTE]	= &remote_ao,
>> +	[CLKID_AO_I2C_MASTER]	= &i2c_master_ao,
>> +	[CLKID_AO_I2C_SLAVE]	= &i2c_slave_ao,
>> +	[CLKID_AO_UART1]	= &uart1_ao,
>> +	[CLKID_AO_UART2]	= &uart2_ao,
>> +	[CLKID_AO_IR_BLASTER]	= &ir_blaster_ao,
>> +	[CLKID_AO_SAR_ADC]	= &saradc_ao,
>> +	[CLKID_AO_CLK81]	= &ao_clk81,
>> +	[CLKID_AO_SAR_ADC_SEL]	= &axg_saradc_mux,
>> +	[CLKID_AO_SAR_ADC_DIV]	= &axg_saradc_div,
>> +	[CLKID_AO_SAR_ADC_CLK]	= &axg_saradc_gate,
> 
> Naming is not very consistent here, sometimes ao at beginning, sometimes the
> end, with or w/o axg.
> 
> I would prefer if you prefix everything with axg_ao[clk] 
> ex: axg_aoclk_remote, axg_aoclk_saradc_mux, etc ...
> 
I will adjust this..

but. I'd like to make short as 'axg_ao_' prefix
since we've already adopt this, see drivers/clk/meson/axg.c:823

does this sounds good to you?

>> +};
>> +
>> +static const struct clk_hw_onecell_data axg_aoclk_onecell_data = {
>> +	.hws = {
>> +		[CLKID_AO_REMOTE]	= &remote_ao.hw,
>> +		[CLKID_AO_I2C_MASTER]	= &i2c_master_ao.hw,
>> +		[CLKID_AO_I2C_SLAVE]	= &i2c_slave_ao.hw,
>> +		[CLKID_AO_UART1]	= &uart1_ao.hw,
>> +		[CLKID_AO_UART2]	= &uart2_ao.hw,
>> +		[CLKID_AO_IR_BLASTER]	= &ir_blaster_ao.hw,
>> +		[CLKID_AO_SAR_ADC]	= &saradc_ao.hw,
>> +		[CLKID_AO_CLK81]	= &ao_clk81.hw,
>> +		[CLKID_AO_SAR_ADC_SEL]	= &axg_saradc_mux.hw,
>> +		[CLKID_AO_SAR_ADC_DIV]	= &axg_saradc_div.hw,
>> +		[CLKID_AO_SAR_ADC_CLK]	= &axg_saradc_gate.hw,
>> +	},
>> +	.num = NR_CLKS,
>> +};
>> +
>> +static const struct meson_aoclk_data axg_aoclkc_data = {
>> +	.reset_reg	= AO_RTI_GEN_CNTL_REG0,
>> +	.num_reset	= ARRAY_SIZE(axg_aoclk_reset),
>> +	.reset		= axg_aoclk_reset,
>> +	.num_clks	= ARRAY_SIZE(axg_aoclk_regmap),
>> +	.clks		= axg_aoclk_regmap,
>> +	.hw_data	= &axg_aoclk_onecell_data,
>> +};
>> +
>> +static const struct of_device_id axg_aoclkc_match_table[] = {
>> +	{
>> +		.compatible	= "amlogic,meson-axg-aoclkc",
>> +		.data		= &axg_aoclkc_data,
>> +	},
>> +	{ }
>> +};
>> +
>> +static struct platform_driver axg_aoclkc_driver = {
>> +	.probe		= meson_aoclkc_probe,
>> +	.driver		= {
>> +		.name	= "axg-aoclkc",
>> +		.of_match_table = axg_aoclkc_match_table,
>> +	},
>> +};
>> +
>> +builtin_platform_driver(axg_aoclkc_driver);
>> diff --git a/drivers/clk/meson/axg-aoclk.h b/drivers/clk/meson/axg-aoclk.h
>> new file mode 100644
>> index 000000000000..396cd3023064
>> --- /dev/null
>> +++ b/drivers/clk/meson/axg-aoclk.h
>> @@ -0,0 +1,31 @@
>> +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
>> +/*
>> + * Copyright (c) 2017 BayLibre, SAS
>> + * Author: Neil Armstrong <narmstrong at baylibre.com>
>> + *
>> + * Copyright (c) 2018 Amlogic, inc.
>> + * Author: Qiufang Dai <qiufang.dai at amlogic.com>
>> + */
>> +
>> +#ifndef __AXG_AOCLKC_H
>> +#define __AXG_AOCLKC_H
>> +
>> +#include "meson-aoclk.h"
>> +
>> +#define NR_CLKS	11
>> +/* AO Configuration Clock registers offsets
>> + * Register offsets from the data sheet must be multiplied by 4.
>> + */
>> +#define AO_RTI_PWR_CNTL_REG1	0x0C
>> +#define AO_RTI_PWR_CNTL_REG0	0x10
>> +#define AO_RTI_GEN_CNTL_REG0	0x40
>> +#define AO_OSCIN_CNTL		0x58
>> +#define AO_CRT_CLK_CNTL1	0x68
>> +#define AO_SAR_CLK		0x90
>> +#define AO_RTC_ALT_CLK_CNTL0	0x94
>> +#define AO_RTC_ALT_CLK_CNTL1	0x98
>> +
>> +#include <dt-bindings/clock/axg-aoclkc.h>
>> +#include <dt-bindings/reset/axg-aoclkc.h>
>> +
>> +#endif /* __AXG_AOCLKC_H */
> 
> .
> 



From yixun.lan at amlogic.com  Tue Apr 17 10:08:24 2018
From: yixun.lan at amlogic.com (Yixun Lan)
Date: Tue, 17 Apr 2018 17:08:24 +0000
Subject: [PATCH] pinctrl: meson-axg: fix the range of aobus bank
Message-ID: <20180417170824.18670-1-yixun.lan@amlogic.com>

The GPIOAO bank is range from GPIOAO_0 to GPIOAO_13.

Fixes: 83c566806a68 ("pinctrl: meson-axg: Add new pinctrl driver for Meson AXG SoC")
Reported-by: Xingyu Chen <xingyu.chen at amlogic.com>
Signed-off-by: Yixun Lan <yixun.lan at amlogic.com>
---
 drivers/pinctrl/meson/pinctrl-meson-axg.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/pinctrl/meson/pinctrl-meson-axg.c b/drivers/pinctrl/meson/pinctrl-meson-axg.c
index 4b91ff74779b..99a6ceac8e53 100644
--- a/drivers/pinctrl/meson/pinctrl-meson-axg.c
+++ b/drivers/pinctrl/meson/pinctrl-meson-axg.c
@@ -898,7 +898,7 @@ static struct meson_bank meson_axg_periphs_banks[] = {
 
 static struct meson_bank meson_axg_aobus_banks[] = {
 	/*   name    first      last      irq	pullen  pull    dir     out     in  */
-	BANK("AO",   GPIOAO_0,  GPIOAO_9, 0, 13, 0,  16,  0, 0,  0,  0,  0, 16,  1,  0),
+	BANK("AO",   GPIOAO_0,  GPIOAO_13, 0, 13, 0,  16,  0, 0,  0,  0,  0, 16,  1,  0),
 };
 
 static struct meson_pmx_bank meson_axg_periphs_pmx_banks[] = {
-- 
2.17.0



From narmstrong at baylibre.com  Tue Apr 17 02:30:22 2018
From: narmstrong at baylibre.com (Neil Armstrong)
Date: Tue, 17 Apr 2018 11:30:22 +0200
Subject: [PATCH] reset: fix reset_get_bulk when phandle error
Message-ID: <1523957422-16552-1-git-send-email-narmstrong@baylibre.com>

This fixes the Coverity Defect CID 175348 when dev_count_phandle_with_args()
returns a negative value.

Fixes: 0c28233903b5 ("reset: Add get/assert/deassert/release for bulk of reset signals")
Signed-off-by: Neil Armstrong <narmstrong at baylibre.com>
---
 drivers/reset/reset-uclass.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/reset/reset-uclass.c b/drivers/reset/reset-uclass.c
index 9a5c9c9..fa4f653 100644
--- a/drivers/reset/reset-uclass.c
+++ b/drivers/reset/reset-uclass.c
@@ -88,8 +88,8 @@ int reset_get_bulk(struct udevice *dev, struct reset_ctl_bulk *bulk)
 	bulk->count = 0;
 
 	count = dev_count_phandle_with_args(dev, "resets", "#reset-cells");
-	if (!count)
-		return 0;
+	if (count < 1)
+		return count;
 
 	bulk->resets = devm_kcalloc(dev, count, sizeof(struct reset_ctl),
 				    GFP_KERNEL);
-- 
2.7.4



From narmstrong at baylibre.com  Tue Apr 17 02:30:31 2018
From: narmstrong at baylibre.com (Neil Armstrong)
Date: Tue, 17 Apr 2018 11:30:31 +0200
Subject: [PATCH] clk: fix clk_get_bulk when phandle error
Message-ID: <1523957431-16612-1-git-send-email-narmstrong@baylibre.com>

This fixes the Coverity Defect CID 175347 when dev_count_phandle_with_args()
returns a negative value.

Fixes: a855be87da49 ("clk: Add get/enable/disable/release for a bulk of clocks")
Signed-off-by: Neil Armstrong <narmstrong at baylibre.com>
---
 drivers/clk/clk-uclass.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/clk/clk-uclass.c b/drivers/clk/clk-uclass.c
index 6e99b3b..53f418b 100644
--- a/drivers/clk/clk-uclass.c
+++ b/drivers/clk/clk-uclass.c
@@ -111,8 +111,8 @@ int clk_get_bulk(struct udevice *dev, struct clk_bulk *bulk)
 	bulk->count = 0;
 
 	count = dev_count_phandle_with_args(dev, "clocks", "#clock-cells");
-	if (!count)
-		return 0;
+	if (count < 1)
+		return count;
 
 	bulk->clks = devm_kcalloc(dev, count, sizeof(struct clk), GFP_KERNEL);
 	if (!bulk->clks)
-- 
2.7.4



From jbrunet at baylibre.com  Tue Apr 17 07:15:33 2018
From: jbrunet at baylibre.com (Jerome Brunet)
Date: Tue, 17 Apr 2018 16:15:33 +0200
Subject: [PATCH v5 2/7] clk: meson: aoclk: refactor common code into
 dedicated file
In-Reply-To: <759078f5-fcbf-9ef1-6945-67d9d951d8eb@amlogic.com>
References: <20180409143749.71197-1-yixun.lan@amlogic.com>
 <20180409143749.71197-3-yixun.lan@amlogic.com>
 <1523875084.2601.28.camel@baylibre.com>
 <759078f5-fcbf-9ef1-6945-67d9d951d8eb@amlogic.com>
Message-ID: <1523974533.2601.95.camel@baylibre.com>

On Tue, 2018-04-17 at 16:16 +0800, Yixun Lan wrote:
> Hi Jerome
> 
> On 04/16/18 18:38, Jerome Brunet wrote:
> > > +	 */
> > > +	for (clkid = 0; clkid < data->num_clks; clkid++) {
> > > +		data->clks[clkid]->map = regmap;
> > > +
> > > +		ret = devm_clk_hw_register(dev, data->hw_data->hws[clkid]);
> > > +		if (ret)
> > > +			return ret;
> > > +	}
> > > +
> > > +	return devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get,
> > > +		(void *) data->hw_data);
> > > +}
> > 
> > Missing new line here. Please run checkpatch and pay attention to git warnings
> > about whitespace errors.
> > 
> 

Google this if you want, As far as I know the C language requires it and makes
things nice when I cat the file.

Anyway, I don't make those rules, It is just how it is.

> 
> I think we actually need to avoid this extra new line, or what's the
> benefits with new line?
> 
> and besides? I didn't see any complaint from checkpatch.pl ..
> 
>  ./scripts/checkpatch.pl
> 0002-clk-meson-aoclk-refactor-common-code-into-dedicated-.patch
> WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
> #235:
> new file mode 100644
> 
> total: 0 errors, 1 warnings, 302 lines checked
> 
> NOTE: For some of the reported defects, checkpatch may be able to
>       mechanically convert to the typical style using --fix or
> --fix-inplace.
> 
> 0002-clk-meson-aoclk-refactor-common-code-into-dedicated-.patch has
> style problems, please review.
> 
> NOTE: If any of the errors are false positives, please report
>       them to the maintainer, see CHECKPATCH in MAINTAINERS.
> 
> 
> Yixun



From hias at horus.com  Tue Apr 17 12:14:57 2018
From: hias at horus.com (Matthias Reichl)
Date: Tue, 17 Apr 2018 21:14:57 +0200
Subject: [PATCH v2 7/7] media: rc: mceusb: allow the timeout to be
 configurable
In-Reply-To: <02b5dac3b27169c6e6a4a070a2569b33fef47bbe.1523221902.git.sean@mess.org>
References: <cover.1523221902.git.sean@mess.org>
 <02b5dac3b27169c6e6a4a070a2569b33fef47bbe.1523221902.git.sean@mess.org>
Message-ID: <20180417191457.fhgsdega2kjqw3t2@camel2.lan>

Hi Sean!

On Sun, Apr 08, 2018 at 10:19:42PM +0100, Sean Young wrote:
> mceusb devices have a default timeout of 100ms, but this can be changed.

We finally added a backport of the v2 series (and also the mce_kbd
series) to LibreELEC yesterday and ratcher quickly received 2 bugreports
from users using mceusb receivers.

Local testing on RPi/gpio-ir and Intel NUC/ite-cir was fine, I've
been using the v2 series for over a week without issues on
LibreELEC (RPi with kernel 4.14).

Here are the links to the bugreports and logs:
https://forum.kodi.tv/showthread.php?tid=298461&pid=2726684#pid2726684
https://forum.kodi.tv/showthread.php?tid=298462&pid=2726690#pid2726690

Both users are using similar mceusb receivers:

Log 1:
[    6.418218] rc rc0: Media Center Ed. eHome Infrared Remote Transceiver (147a:e017) as /devices/platform/soc/3f980000.usb/usb1/1-1/1-1.3/1-1.3:1.0/rc/rc0
[    6.418358] input: Media Center Ed. eHome Infrared Remote Transceiver (147a:e017) as /devices/platform/soc/3f980000.usb/usb1/1-1/1-1.3/1-1.3:1.0/rc/rc0/input0
[    6.419443] rc rc0: lirc_dev: driver ir-lirc-codec (mceusb) registered at minor = 0
[    6.608114] mceusb 1-1.3:1.0: Registered Formosa21 SnowflakeEmulation with mce emulator interface version 1
[    6.608125] mceusb 1-1.3:1.0: 0 tx ports (0x0 cabled) and 1 rx sensors (0x1 active)

Log 2:
[    3.023361] rc rc0: Media Center Ed. eHome Infrared Remote Transceiver (147a:e03e) as /devices/pci0000:00/0000:00:14.0/usb1/1-10/1-10:1.0/rc/rc0
[    3.023393] input: Media Center Ed. eHome Infrared Remote Transceiver (147a:e03e) as /devices/pci0000:00/0000:00:14.0/usb1/1-10/1-10:1.0/rc/rc0/input11
[    3.023868] rc rc0: lirc_dev: driver ir-lirc-codec (mceusb) registered at minor = 0
[    3.119384] input: eventlircd as /devices/virtual/input/input21
[    3.138625] ip6_tables: (C) 2000-2006 Netfilter Core Team
[    3.196830] mceusb 1-10:1.0: Registered Formosa21 eHome Infrared Transceiver with mce emulator interface version 2
[    3.196836] mceusb 1-10:1.0: 0 tx ports (0x0 cabled) and 1 rx sensors (0x1 active)

In both cases ir-keytable doesn't report any scancodes and the
ir-ctl -r output contains very odd long space values where I'd expect
a short timeout instead:

gap between messages:
space 800
pulse 450
space 16777215
space 25400
pulse 2650
space 800

end of last message:
space 800
pulse 450
space 16777215
timeout 31750

This patch applied cleanly on 4.14 and the mceusb history from
4.14 to media/master looked rather unsuspicious. I'm not 100% sure
if I might have missed a dependency when backporting the patch
or if this is indeed an issue of this patch on these particular
(or maybe some more) mceusb receivers.

so long,

Hias

> Signed-off-by: Sean Young <sean at mess.org>
> ---
>  drivers/media/rc/mceusb.c | 22 ++++++++++++++++++++++
>  1 file changed, 22 insertions(+)
> 
> diff --git a/drivers/media/rc/mceusb.c b/drivers/media/rc/mceusb.c
> index 69ba57372c05..c97cb2eb1c5f 100644
> --- a/drivers/media/rc/mceusb.c
> +++ b/drivers/media/rc/mceusb.c
> @@ -982,6 +982,25 @@ static int mceusb_set_tx_carrier(struct rc_dev *dev, u32 carrier)
>  	return 0;
>  }
>  
> +static int mceusb_set_timeout(struct rc_dev *dev, unsigned int timeout)
> +{
> +	u8 cmdbuf[4] = { MCE_CMD_PORT_IR, MCE_CMD_SETIRTIMEOUT, 0, 0 };
> +	struct mceusb_dev *ir = dev->priv;
> +	unsigned int units;
> +
> +	units = DIV_ROUND_CLOSEST(timeout, US_TO_NS(MCE_TIME_UNIT));
> +
> +	cmdbuf[2] = units >> 8;
> +	cmdbuf[3] = units;
> +
> +	mce_async_out(ir, cmdbuf, sizeof(cmdbuf));
> +
> +	/* get receiver timeout value */
> +	mce_async_out(ir, GET_RX_TIMEOUT, sizeof(GET_RX_TIMEOUT));
> +
> +	return 0;
> +}
> +
>  /*
>   * Select or deselect the 2nd receiver port.
>   * Second receiver is learning mode, wide-band, short-range receiver.
> @@ -1415,7 +1434,10 @@ static struct rc_dev *mceusb_init_rc_dev(struct mceusb_dev *ir)
>  	rc->dev.parent = dev;
>  	rc->priv = ir;
>  	rc->allowed_protocols = RC_PROTO_BIT_ALL_IR_DECODER;
> +	rc->min_timeout = US_TO_NS(MCE_TIME_UNIT);
>  	rc->timeout = MS_TO_NS(100);
> +	rc->max_timeout = 10 * IR_DEFAULT_TIMEOUT;
> +	rc->s_timeout = mceusb_set_timeout;
>  	if (!ir->flags.no_tx) {
>  		rc->s_tx_mask = mceusb_set_tx_mask;
>  		rc->s_tx_carrier = mceusb_set_tx_carrier;
> -- 
> 2.14.3
> 


From sean at mess.org  Wed Apr 18 04:24:29 2018
From: sean at mess.org (Sean Young)
Date: Wed, 18 Apr 2018 12:24:29 +0100
Subject: [PATCH v2 7/7] media: rc: mceusb: allow the timeout to be
 configurable
In-Reply-To: <20180417191457.fhgsdega2kjqw3t2@camel2.lan>
References: <cover.1523221902.git.sean@mess.org>
 <02b5dac3b27169c6e6a4a070a2569b33fef47bbe.1523221902.git.sean@mess.org>
 <20180417191457.fhgsdega2kjqw3t2@camel2.lan>
Message-ID: <20180418112428.zk3lmdxoqv46weph@gofer.mess.org>

Hello Hias,

On Tue, Apr 17, 2018 at 09:14:57PM +0200, Matthias Reichl wrote:
> On Sun, Apr 08, 2018 at 10:19:42PM +0100, Sean Young wrote:
> > mceusb devices have a default timeout of 100ms, but this can be changed.
> 
> We finally added a backport of the v2 series (and also the mce_kbd
> series) to LibreELEC yesterday and ratcher quickly received 2 bugreports
> from users using mceusb receivers.
> 
> Local testing on RPi/gpio-ir and Intel NUC/ite-cir was fine, I've
> been using the v2 series for over a week without issues on
> LibreELEC (RPi with kernel 4.14).
> 
> Here are the links to the bugreports and logs:
> https://forum.kodi.tv/showthread.php?tid=298461&pid=2726684#pid2726684
> https://forum.kodi.tv/showthread.php?tid=298462&pid=2726690#pid2726690
> 
> Both users are using similar mceusb receivers:
> 
> Log 1:
> [    6.418218] rc rc0: Media Center Ed. eHome Infrared Remote Transceiver (147a:e017) as /devices/platform/soc/3f980000.usb/usb1/1-1/1-1.3/1-1.3:1.0/rc/rc0
> [    6.418358] input: Media Center Ed. eHome Infrared Remote Transceiver (147a:e017) as /devices/platform/soc/3f980000.usb/usb1/1-1/1-1.3/1-1.3:1.0/rc/rc0/input0
> [    6.419443] rc rc0: lirc_dev: driver ir-lirc-codec (mceusb) registered at minor = 0
> [    6.608114] mceusb 1-1.3:1.0: Registered Formosa21 SnowflakeEmulation with mce emulator interface version 1
> [    6.608125] mceusb 1-1.3:1.0: 0 tx ports (0x0 cabled) and 1 rx sensors (0x1 active)
> 
> Log 2:
> [    3.023361] rc rc0: Media Center Ed. eHome Infrared Remote Transceiver (147a:e03e) as /devices/pci0000:00/0000:00:14.0/usb1/1-10/1-10:1.0/rc/rc0
> [    3.023393] input: Media Center Ed. eHome Infrared Remote Transceiver (147a:e03e) as /devices/pci0000:00/0000:00:14.0/usb1/1-10/1-10:1.0/rc/rc0/input11
> [    3.023868] rc rc0: lirc_dev: driver ir-lirc-codec (mceusb) registered at minor = 0
> [    3.119384] input: eventlircd as /devices/virtual/input/input21
> [    3.138625] ip6_tables: (C) 2000-2006 Netfilter Core Team
> [    3.196830] mceusb 1-10:1.0: Registered Formosa21 eHome Infrared Transceiver with mce emulator interface version 2
> [    3.196836] mceusb 1-10:1.0: 0 tx ports (0x0 cabled) and 1 rx sensors (0x1 active)
> 
> In both cases ir-keytable doesn't report any scancodes and the
> ir-ctl -r output contains very odd long space values where I'd expect
> a short timeout instead:
> 
> gap between messages:
> space 800
> pulse 450
> space 16777215
> space 25400
> pulse 2650
> space 800
> 
> end of last message:
> space 800
> pulse 450
> space 16777215
> timeout 31750
> 
> This patch applied cleanly on 4.14 and the mceusb history from
> 4.14 to media/master looked rather unsuspicious. I'm not 100% sure
> if I might have missed a dependency when backporting the patch
> or if this is indeed an issue of this patch on these particular
> (or maybe some more) mceusb receivers.

Thanks again for a great bug report and analysis! So, it seems with the
shorter timeout, some mceusb devices add a specific "timeout" code to
the IR data stream (0x80) rather than a space. The current mceusb code
resets the decoders in this case, causing the IR decoders to reset and
lirc to report a space of 0xffffff.

Turns out that one of my mceusb devices also suffers from this, I don't
know how I missed this. Anyway hopefully this will solve the problem.


Thanks

Sean

>From 92d27b206e51993e927dc0b3aba210a621eef3d0 Mon Sep 17 00:00:00 2001
From: Sean Young <sean at mess.org>
Date: Wed, 18 Apr 2018 10:36:25 +0100
Subject: [PATCH] media: rc: mceusb: IR of length 0 means IR timeout, not reset

The last usb packet with IR data will end with 0x80 (MCE_IRDATA_TRAILER).
If we reset the decoder state at this point, IR decoding can fail.

Signed-off-by: Sean Young <sean at mess.org>
---
 drivers/media/rc/mceusb.c | 7 ++++++-
 1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/drivers/media/rc/mceusb.c b/drivers/media/rc/mceusb.c
index c97cb2eb1c5f..5c0bf61fae26 100644
--- a/drivers/media/rc/mceusb.c
+++ b/drivers/media/rc/mceusb.c
@@ -1201,7 +1201,12 @@ static void mceusb_process_ir_data(struct mceusb_dev *ir, int buf_len)
 			if (ir->rem) {
 				ir->parser_state = PARSE_IRDATA;
 			} else {
-				ir_raw_event_reset(ir->rc);
+				init_ir_raw_event(&rawir);
+				rawir.timeout = 1;
+				rawir.duration = ir->rc->timeout;
+				if (ir_raw_event_store_with_filter(ir->rc,
+								   &rawir))
+					event = true;
 				ir->pulse_tunit = 0;
 				ir->pulse_count = 0;
 			}
-- 
2.14.3



From hias at horus.com  Wed Apr 18 10:42:29 2018
From: hias at horus.com (Matthias Reichl)
Date: Wed, 18 Apr 2018 19:42:29 +0200
Subject: [PATCH v2 7/7] media: rc: mceusb: allow the timeout to be
 configurable
In-Reply-To: <20180418112428.zk3lmdxoqv46weph@gofer.mess.org>
References: <cover.1523221902.git.sean@mess.org>
 <02b5dac3b27169c6e6a4a070a2569b33fef47bbe.1523221902.git.sean@mess.org>
 <20180417191457.fhgsdega2kjqw3t2@camel2.lan>
 <20180418112428.zk3lmdxoqv46weph@gofer.mess.org>
Message-ID: <20180418174229.jurjnyqbtkyctjvb@camel2.lan>

Hi Sean,

On Wed, Apr 18, 2018 at 12:24:29PM +0100, Sean Young wrote:
> Hello Hias,
> 
> On Tue, Apr 17, 2018 at 09:14:57PM +0200, Matthias Reichl wrote:
> > On Sun, Apr 08, 2018 at 10:19:42PM +0100, Sean Young wrote:
> > > mceusb devices have a default timeout of 100ms, but this can be changed.
> > 
> > We finally added a backport of the v2 series (and also the mce_kbd
> > series) to LibreELEC yesterday and ratcher quickly received 2 bugreports
> > from users using mceusb receivers.
> > 
> > Local testing on RPi/gpio-ir and Intel NUC/ite-cir was fine, I've
> > been using the v2 series for over a week without issues on
> > LibreELEC (RPi with kernel 4.14).
> > 
> > Here are the links to the bugreports and logs:
> > https://forum.kodi.tv/showthread.php?tid=298461&pid=2726684#pid2726684
> > https://forum.kodi.tv/showthread.php?tid=298462&pid=2726690#pid2726690
> > 
> > Both users are using similar mceusb receivers:
> > 
> > Log 1:
> > [    6.418218] rc rc0: Media Center Ed. eHome Infrared Remote Transceiver (147a:e017) as /devices/platform/soc/3f980000.usb/usb1/1-1/1-1.3/1-1.3:1.0/rc/rc0
> > [    6.418358] input: Media Center Ed. eHome Infrared Remote Transceiver (147a:e017) as /devices/platform/soc/3f980000.usb/usb1/1-1/1-1.3/1-1.3:1.0/rc/rc0/input0
> > [    6.419443] rc rc0: lirc_dev: driver ir-lirc-codec (mceusb) registered at minor = 0
> > [    6.608114] mceusb 1-1.3:1.0: Registered Formosa21 SnowflakeEmulation with mce emulator interface version 1
> > [    6.608125] mceusb 1-1.3:1.0: 0 tx ports (0x0 cabled) and 1 rx sensors (0x1 active)
> > 
> > Log 2:
> > [    3.023361] rc rc0: Media Center Ed. eHome Infrared Remote Transceiver (147a:e03e) as /devices/pci0000:00/0000:00:14.0/usb1/1-10/1-10:1.0/rc/rc0
> > [    3.023393] input: Media Center Ed. eHome Infrared Remote Transceiver (147a:e03e) as /devices/pci0000:00/0000:00:14.0/usb1/1-10/1-10:1.0/rc/rc0/input11
> > [    3.023868] rc rc0: lirc_dev: driver ir-lirc-codec (mceusb) registered at minor = 0
> > [    3.119384] input: eventlircd as /devices/virtual/input/input21
> > [    3.138625] ip6_tables: (C) 2000-2006 Netfilter Core Team
> > [    3.196830] mceusb 1-10:1.0: Registered Formosa21 eHome Infrared Transceiver with mce emulator interface version 2
> > [    3.196836] mceusb 1-10:1.0: 0 tx ports (0x0 cabled) and 1 rx sensors (0x1 active)
> > 
> > In both cases ir-keytable doesn't report any scancodes and the
> > ir-ctl -r output contains very odd long space values where I'd expect
> > a short timeout instead:
> > 
> > gap between messages:
> > space 800
> > pulse 450
> > space 16777215
> > space 25400
> > pulse 2650
> > space 800
> > 
> > end of last message:
> > space 800
> > pulse 450
> > space 16777215
> > timeout 31750
> > 
> > This patch applied cleanly on 4.14 and the mceusb history from
> > 4.14 to media/master looked rather unsuspicious. I'm not 100% sure
> > if I might have missed a dependency when backporting the patch
> > or if this is indeed an issue of this patch on these particular
> > (or maybe some more) mceusb receivers.
> 
> Thanks again for a great bug report and analysis! So, it seems with the
> shorter timeout, some mceusb devices add a specific "timeout" code to
> the IR data stream (0x80) rather than a space. The current mceusb code
> resets the decoders in this case, causing the IR decoders to reset and
> lirc to report a space of 0xffffff.
> 
> Turns out that one of my mceusb devices also suffers from this, I don't
> know how I missed this. Anyway hopefully this will solve the problem.

Thanks a lot for the quick fix!

I can't test myself as I don't have the hardware, but we will
include the patch in tonight's LibreELEC build and I asked the
users to test it. I'll keep you posted about the outcome.

so long,

Hias

> 
> 
> Thanks
> 
> Sean
> 
> >>From 92d27b206e51993e927dc0b3aba210a621eef3d0 Mon Sep 17 00:00:00 2001
> From: Sean Young <sean at mess.org>
> Date: Wed, 18 Apr 2018 10:36:25 +0100
> Subject: [PATCH] media: rc: mceusb: IR of length 0 means IR timeout, not reset
> 
> The last usb packet with IR data will end with 0x80 (MCE_IRDATA_TRAILER).
> If we reset the decoder state at this point, IR decoding can fail.
> 
> Signed-off-by: Sean Young <sean at mess.org>
> ---
>  drivers/media/rc/mceusb.c | 7 ++++++-
>  1 file changed, 6 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/media/rc/mceusb.c b/drivers/media/rc/mceusb.c
> index c97cb2eb1c5f..5c0bf61fae26 100644
> --- a/drivers/media/rc/mceusb.c
> +++ b/drivers/media/rc/mceusb.c
> @@ -1201,7 +1201,12 @@ static void mceusb_process_ir_data(struct mceusb_dev *ir, int buf_len)
>  			if (ir->rem) {
>  				ir->parser_state = PARSE_IRDATA;
>  			} else {
> -				ir_raw_event_reset(ir->rc);
> +				init_ir_raw_event(&rawir);
> +				rawir.timeout = 1;
> +				rawir.duration = ir->rc->timeout;
> +				if (ir_raw_event_store_with_filter(ir->rc,
> +								   &rawir))
> +					event = true;
>  				ir->pulse_tunit = 0;
>  				ir->pulse_count = 0;
>  			}
> -- 
> 2.14.3
> 


From martin.blumenstingl at googlemail.com  Wed Apr 18 12:39:50 2018
From: martin.blumenstingl at googlemail.com (Martin Blumenstingl)
Date: Wed, 18 Apr 2018 21:39:50 +0200
Subject: [PATCH usb v6 5/6] usb: core: phy: add missing forward declaration
 for "struct device"
In-Reply-To: <20180418193951.17922-1-martin.blumenstingl@googlemail.com>
References: <20180418193951.17922-1-martin.blumenstingl@googlemail.com>
Message-ID: <20180418193951.17922-6-martin.blumenstingl@googlemail.com>

Currently hcd.c is the only consumer of the usb_phy_roothub logic. This
already includes the required header files so struct device is known.
However, future consumers might not know about struct device.
Add a forward declaration for struct device to fix potential future
consumers which don't include any of the struct device API headers.

Fixes: 07dbff0ddbd86c ("usb: core: add a wrapper for the USB PHYs on the HCD")
Suggested-by: Masahiro Yamada <yamada.masahiro at socionext.com>
Signed-off-by: Martin Blumenstingl <martin.blumenstingl at googlemail.com>
---
 drivers/usb/core/phy.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/usb/core/phy.h b/drivers/usb/core/phy.h
index 605555901d44..bbc969383074 100644
--- a/drivers/usb/core/phy.h
+++ b/drivers/usb/core/phy.h
@@ -1,3 +1,4 @@
+struct device;
 struct usb_phy_roothub;
 
 struct usb_phy_roothub *usb_phy_roothub_alloc(struct device *dev);
-- 
2.17.0



From martin.blumenstingl at googlemail.com  Wed Apr 18 12:39:48 2018
From: martin.blumenstingl at googlemail.com (Martin Blumenstingl)
Date: Wed, 18 Apr 2018 21:39:48 +0200
Subject: [PATCH usb v6 3/6] usb: core: use phy_exit during suspend if wake up
 is not supported
In-Reply-To: <20180418193951.17922-1-martin.blumenstingl@googlemail.com>
References: <20180418193951.17922-1-martin.blumenstingl@googlemail.com>
Message-ID: <20180418193951.17922-4-martin.blumenstingl@googlemail.com>

If the USB controller can wake up the system (which is the case for
example with the Mediatek USB3 IP) then we must not call phy_exit during
suspend to ensure that the USB controller doesn't have to re-enumerate
the devices during resume.
However, if the USB controller cannot wake up the system (which is the
case for example on various TI platforms using a dwc3 controller) then
we must call phy_exit during suspend. Otherwise the PHY driver keeps the
clocks enabled, which prevents the system from reaching the lowest power
levels in the suspend state.

Solve this by introducing two new functions in the PHY wrapper which are
dedicated to the suspend and resume handling.
If the controller can wake up the system the new usb_phy_roothub_suspend
function will simply call usb_phy_roothub_power_off. However, if wake up
is not supported by the controller it will also call
usb_phy_roothub_exit.
The also new usb_phy_roothub_resume function takes care of calling
usb_phy_roothub_init (if the controller can't wake up the system) in
addition to usb_phy_roothub_power_on.

Fixes: 07dbff0ddbd86c ("usb: core: add a wrapper for the USB PHYs on the HCD")
Fixes: 178a0bce05cbc1 ("usb: core: hcd: integrate the PHY wrapper into the HCD core")
Reported-by: Roger Quadros <rogerq at ti.com>
Suggested-by: Roger Quadros <rogerq at ti.com>
Suggested-by: Chunfeng Yun <chunfeng.yun at mediatek.com>
Signed-off-by: Martin Blumenstingl <martin.blumenstingl at googlemail.com>
Tested-by: Chunfeng Yun <chunfeng.yun at mediatek.com>
Reviewed-by: Roger Quadros <rogerq at ti.com>
Tested-by: Keerthy <j-keerthy at ti.com>
---
 drivers/usb/core/hcd.c |  8 +++++---
 drivers/usb/core/phy.c | 35 +++++++++++++++++++++++++++++++++++
 drivers/usb/core/phy.h |  5 +++++
 3 files changed, 45 insertions(+), 3 deletions(-)

diff --git a/drivers/usb/core/hcd.c b/drivers/usb/core/hcd.c
index 15b0418e3b6a..78bae4ecd68b 100644
--- a/drivers/usb/core/hcd.c
+++ b/drivers/usb/core/hcd.c
@@ -2262,7 +2262,8 @@ int hcd_bus_suspend(struct usb_device *rhdev, pm_message_t msg)
 		hcd->state = HC_STATE_SUSPENDED;
 
 		if (!PMSG_IS_AUTO(msg))
-			usb_phy_roothub_power_off(hcd->phy_roothub);
+			usb_phy_roothub_suspend(hcd->self.sysdev,
+						hcd->phy_roothub);
 
 		/* Did we race with a root-hub wakeup event? */
 		if (rhdev->do_remote_wakeup) {
@@ -2302,7 +2303,8 @@ int hcd_bus_resume(struct usb_device *rhdev, pm_message_t msg)
 	}
 
 	if (!PMSG_IS_AUTO(msg)) {
-		status = usb_phy_roothub_power_on(hcd->phy_roothub);
+		status = usb_phy_roothub_resume(hcd->self.sysdev,
+						hcd->phy_roothub);
 		if (status)
 			return status;
 	}
@@ -2344,7 +2346,7 @@ int hcd_bus_resume(struct usb_device *rhdev, pm_message_t msg)
 		}
 	} else {
 		hcd->state = old_state;
-		usb_phy_roothub_power_off(hcd->phy_roothub);
+		usb_phy_roothub_suspend(hcd->self.sysdev, hcd->phy_roothub);
 		dev_dbg(&rhdev->dev, "bus %s fail, err %d\n",
 				"resume", status);
 		if (status != -ESHUTDOWN)
diff --git a/drivers/usb/core/phy.c b/drivers/usb/core/phy.c
index 44f008cda7a8..a39d9bb26a4f 100644
--- a/drivers/usb/core/phy.c
+++ b/drivers/usb/core/phy.c
@@ -157,3 +157,38 @@ void usb_phy_roothub_power_off(struct usb_phy_roothub *phy_roothub)
 		phy_power_off(roothub_entry->phy);
 }
 EXPORT_SYMBOL_GPL(usb_phy_roothub_power_off);
+
+int usb_phy_roothub_suspend(struct device *controller_dev,
+			    struct usb_phy_roothub *phy_roothub)
+{
+	usb_phy_roothub_power_off(phy_roothub);
+
+	/* keep the PHYs initialized so the device can wake up the system */
+	if (device_may_wakeup(controller_dev))
+		return 0;
+
+	return usb_phy_roothub_exit(phy_roothub);
+}
+EXPORT_SYMBOL_GPL(usb_phy_roothub_suspend);
+
+int usb_phy_roothub_resume(struct device *controller_dev,
+			   struct usb_phy_roothub *phy_roothub)
+{
+	int err;
+
+	/* if the device can't wake up the system _exit was called */
+	if (!device_may_wakeup(controller_dev)) {
+		err = usb_phy_roothub_init(phy_roothub);
+		if (err)
+			return err;
+	}
+
+	err = usb_phy_roothub_power_on(phy_roothub);
+
+	/* undo _init if _power_on failed */
+	if (err && !device_may_wakeup(controller_dev))
+		usb_phy_roothub_exit(phy_roothub);
+
+	return err;
+}
+EXPORT_SYMBOL_GPL(usb_phy_roothub_resume);
diff --git a/drivers/usb/core/phy.h b/drivers/usb/core/phy.h
index eb31253201ad..605555901d44 100644
--- a/drivers/usb/core/phy.h
+++ b/drivers/usb/core/phy.h
@@ -7,3 +7,8 @@ int usb_phy_roothub_exit(struct usb_phy_roothub *phy_roothub);
 
 int usb_phy_roothub_power_on(struct usb_phy_roothub *phy_roothub);
 void usb_phy_roothub_power_off(struct usb_phy_roothub *phy_roothub);
+
+int usb_phy_roothub_suspend(struct device *controller_dev,
+			    struct usb_phy_roothub *phy_roothub);
+int usb_phy_roothub_resume(struct device *controller_dev,
+			   struct usb_phy_roothub *phy_roothub);
-- 
2.17.0



From martin.blumenstingl at googlemail.com  Wed Apr 18 12:39:45 2018
From: martin.blumenstingl at googlemail.com (Martin Blumenstingl)
Date: Wed, 18 Apr 2018 21:39:45 +0200
Subject: [PATCH usb v6 0/6] usb/core/phy fixes for v4.17
Message-ID: <20180418193951.17922-1-martin.blumenstingl@googlemail.com>

This is a follow-up to my previous series "initialize (multiple) PHYs
for a HCD": [0].

Roger Quadros reported [1] that it "is breaking low power cases on TI
SoCs when USB is in host mode". He further explains that "Not doing the
phy_exit() here [when entering suspend] leaves the clocks enabled on
our SoC and we're no longer able to reach low power states on system
suspend."
Chunfeng Yun from Mediatek noted [2] that we cannot unconditionally call
phy_exit while entering system suspend, because this would "disconnect
plugged devices on MTK platforms, due to re-initialize u2 phys when
resume"

In the discussion (which followed Roger's bug report: [1]) Roger,
Chunfeng and me came to the conclusion that we can fix suspend on the
TI SoCs without breaking it on the Mediatek SoCs by extending the
suspend and resume code in usb/core/phy.c by checking whether the USB
controller can wake up the system (which is the case for the Mediatek
MTU3 controller, but now for the dwc3 controller used on the TI SoCs):
- if the controller can wake up the system (Mediatek MTU3 use-case) we
  only call usb_phy_roothub_power_off (which calls phy_power_off) when
  entering system suspend
- if the controller however cannot wake up the system (dwc3 on TI SoCs)
  we additionally call usb_phy_roothub_exit (which calls phy_exit) when
  entering system suspend
- (we undo the previous steps during system resume)

The goal of this series is to fix the issue reported by Roger without
breaking suspend/resume on the Mediatek SoCs.
Since I neither have a TI nor a Mediatek device I am sending this as
RFC. I have tested it on an Amlogic Meson GXM board (Khadas VIM2) which
does NOT support suspend/resume yet.

Additionally Stefan Wahren reported [7] that booting on a Raspberry Pi
with CONFIG_GENERIC_PHY being disabled (which is the case for
bcm2835_defconfig) breaks USB. A fix for this is also included.


changes since v5 at [9]
- rebased on top of v4.17-rc1
- added Keerthy's Tested-by to the first three patches (thank you!)
- fixed a checkpatch warning (which was introduced in v4.17-rc1's
  checkpatch.pl) in patch #6 by using "/* SPDX-License-Identifier"
  instead of "// SPDX-License-Identifier"

changes since v4 at [8]
- updated series title since it now includes fixes for other
  functionality than suspend
- rebased on top of f8cf2f16a7c95a from Linus' tree -> I will re-send
  an updated version once v4.17-rc1 is out, I just sent it early to
  get some feedback early!
- included patch [3] "usb: core: phy: fix return value of
  usb_phy_roothub_exit()" in this series
- fix the logic if CONFIG_GENERIC_PHY is disabled (as reported by
  Stefan Wahren, new patch #4)
- two minor coding style fixes as suggested by Masahiro Yamada (new
  patches #4 and #5)

changes since RFC v3 at [6]:
- added Chunfeng Yun's Tested-by and Roger Quadros' Reviewed-by (thank
  you!)
- dropped RFC prefix

changes since RFC v2 at [5]:
- add missing INIT_LIST_HEAD call in usb_phy_roothub_add_phy (affects
  patch #1 - spotted by Roger Quadros, thank you!)
- fixed swapped conditions using device_may_wakeup() in
  usb_phy_roothub_resume because we need to call usb_phy_roothub_init
  if the controller cannot wake up the device (affects patch #2, spotted
  by Chunfeng Yun, thank you!)
- simplified the error condition to "undo" usb_phy_roothub_init if
  usb_phy_roothub_power_on failed in usb_phy_roothub_resume (suggested
  by Chunfeng Yun)
- updated the commit message (using Roger's wording) because (quote from
  Roger "it doesn't prevent the system from entering suspend but just
  prevents the system from reaching lowest power levels in the suspend
  state."

Changes since RFC v1 (blob attachments) at [4]:
- use device_may_wakeup instead of device_can_wakeup as suggested by
  Roger Quadros
- use the controller device from hcd->self.controller as suggested by
  Chunfeng Yun
- compile time fixes thanks to Roger Quadros
- if usb_phy_roothub_power_on in usb_phy_roothub_resume failes then
  we now call usb_phy_roothub_exit to keep the PHYs in the correct
  state if usb_phy_roothub_resume partially failed


[0] http://lists.infradead.org/pipermail/linux-amlogic/2018-March/006599.html
[1] http://lists.infradead.org/pipermail/linux-amlogic/2018-March/006737.html
[2] http://lists.infradead.org/pipermail/linux-amlogic/2018-March/006758.html
[3] http://lists.infradead.org/pipermail/linux-amlogic/2018-March/006819.html
[4] http://lists.infradead.org/pipermail/linux-amlogic/2018-March/006794.html
[5] http://lists.infradead.org/pipermail/linux-amlogic/2018-March/006820.html
[6] http://lists.infradead.org/pipermail/linux-amlogic/2018-March/006847.html
[7] https://www.spinics.net/lists/linux-usb/msg167472.html
[8] http://lists.infradead.org/pipermail/linux-amlogic/2018-March/006882.html
[9] http://lists.infradead.org/pipermail/linux-amlogic/2018-April/007009.html

Martin Blumenstingl (6):
  usb: core: phy: fix return value of usb_phy_roothub_exit()
  usb: core: split usb_phy_roothub_{init,alloc}
  usb: core: use phy_exit during suspend if wake up is not supported
  usb: core: phy: make it a no-op if CONFIG_GENERIC_PHY is disabled
  usb: core: phy: add missing forward declaration for "struct device"
  usb: core: phy: add the SPDX-License-Identifier and include guard

 drivers/usb/core/hcd.c | 18 +++++---
 drivers/usb/core/phy.c | 93 ++++++++++++++++++++++++++++++------------
 drivers/usb/core/phy.h | 22 +++++++++-
 3 files changed, 99 insertions(+), 34 deletions(-)

-- 
2.17.0



From martin.blumenstingl at googlemail.com  Wed Apr 18 12:39:47 2018
From: martin.blumenstingl at googlemail.com (Martin Blumenstingl)
Date: Wed, 18 Apr 2018 21:39:47 +0200
Subject: [PATCH usb v6 2/6] usb: core: split usb_phy_roothub_{init,alloc}
In-Reply-To: <20180418193951.17922-1-martin.blumenstingl@googlemail.com>
References: <20180418193951.17922-1-martin.blumenstingl@googlemail.com>
Message-ID: <20180418193951.17922-3-martin.blumenstingl@googlemail.com>

Before this patch usb_phy_roothub_init served two purposes (from a
caller's point of view - like hcd.c):
- parsing the PHYs and allocating the list entries
- calling phy_init on each list entry

While this worked so far it has one disadvantage: if we need to call
phy_init for each PHY instance then the existing code cannot be re-used.
Solve this by splitting off usb_phy_roothub_alloc which only parses the
PHYs and allocates the list entries.
usb_phy_roothub_init then gets a struct usb_phy_roothub and only calls
phy_init on each PHY instance (along with the corresponding cleanup if
that failed somewhere).

This is a preparation step for adding proper suspend support for some
hardware that requires phy_exit to be called during suspend and phy_init
to be called during resume.

Signed-off-by: Martin Blumenstingl <martin.blumenstingl at googlemail.com>
Tested-by: Chunfeng Yun <chunfeng.yun at mediatek.com>
Reviewed-by: Roger Quadros <rogerq at ti.com>
Tested-by: Keerthy <j-keerthy at ti.com>
---
 drivers/usb/core/hcd.c | 10 +++++---
 drivers/usb/core/phy.c | 53 +++++++++++++++++++++---------------------
 drivers/usb/core/phy.h |  4 +++-
 3 files changed, 37 insertions(+), 30 deletions(-)

diff --git a/drivers/usb/core/hcd.c b/drivers/usb/core/hcd.c
index 777036ae6367..15b0418e3b6a 100644
--- a/drivers/usb/core/hcd.c
+++ b/drivers/usb/core/hcd.c
@@ -2758,12 +2758,16 @@ int usb_add_hcd(struct usb_hcd *hcd,
 	}
 
 	if (!hcd->skip_phy_initialization && usb_hcd_is_primary_hcd(hcd)) {
-		hcd->phy_roothub = usb_phy_roothub_init(hcd->self.sysdev);
+		hcd->phy_roothub = usb_phy_roothub_alloc(hcd->self.sysdev);
 		if (IS_ERR(hcd->phy_roothub)) {
 			retval = PTR_ERR(hcd->phy_roothub);
-			goto err_phy_roothub_init;
+			goto err_phy_roothub_alloc;
 		}
 
+		retval = usb_phy_roothub_init(hcd->phy_roothub);
+		if (retval)
+			goto err_phy_roothub_alloc;
+
 		retval = usb_phy_roothub_power_on(hcd->phy_roothub);
 		if (retval)
 			goto err_usb_phy_roothub_power_on;
@@ -2936,7 +2940,7 @@ int usb_add_hcd(struct usb_hcd *hcd,
 	usb_phy_roothub_power_off(hcd->phy_roothub);
 err_usb_phy_roothub_power_on:
 	usb_phy_roothub_exit(hcd->phy_roothub);
-err_phy_roothub_init:
+err_phy_roothub_alloc:
 	if (hcd->remove_phy && hcd->usb_phy) {
 		usb_phy_shutdown(hcd->usb_phy);
 		usb_put_phy(hcd->usb_phy);
diff --git a/drivers/usb/core/phy.c b/drivers/usb/core/phy.c
index f19aaa3c899c..44f008cda7a8 100644
--- a/drivers/usb/core/phy.c
+++ b/drivers/usb/core/phy.c
@@ -19,19 +19,6 @@ struct usb_phy_roothub {
 	struct list_head	list;
 };
 
-static struct usb_phy_roothub *usb_phy_roothub_alloc(struct device *dev)
-{
-	struct usb_phy_roothub *roothub_entry;
-
-	roothub_entry = devm_kzalloc(dev, sizeof(*roothub_entry), GFP_KERNEL);
-	if (!roothub_entry)
-		return ERR_PTR(-ENOMEM);
-
-	INIT_LIST_HEAD(&roothub_entry->list);
-
-	return roothub_entry;
-}
-
 static int usb_phy_roothub_add_phy(struct device *dev, int index,
 				   struct list_head *list)
 {
@@ -45,9 +32,11 @@ static int usb_phy_roothub_add_phy(struct device *dev, int index,
 			return PTR_ERR(phy);
 	}
 
-	roothub_entry = usb_phy_roothub_alloc(dev);
-	if (IS_ERR(roothub_entry))
-		return PTR_ERR(roothub_entry);
+	roothub_entry = devm_kzalloc(dev, sizeof(*roothub_entry), GFP_KERNEL);
+	if (!roothub_entry)
+		return -ENOMEM;
+
+	INIT_LIST_HEAD(&roothub_entry->list);
 
 	roothub_entry->phy = phy;
 
@@ -56,11 +45,9 @@ static int usb_phy_roothub_add_phy(struct device *dev, int index,
 	return 0;
 }
 
-struct usb_phy_roothub *usb_phy_roothub_init(struct device *dev)
+struct usb_phy_roothub *usb_phy_roothub_alloc(struct device *dev)
 {
 	struct usb_phy_roothub *phy_roothub;
-	struct usb_phy_roothub *roothub_entry;
-	struct list_head *head;
 	int i, num_phys, err;
 
 	num_phys = of_count_phandle_with_args(dev->of_node, "phys",
@@ -68,16 +55,31 @@ struct usb_phy_roothub *usb_phy_roothub_init(struct device *dev)
 	if (num_phys <= 0)
 		return NULL;
 
-	phy_roothub = usb_phy_roothub_alloc(dev);
-	if (IS_ERR(phy_roothub))
-		return phy_roothub;
+	phy_roothub = devm_kzalloc(dev, sizeof(*phy_roothub), GFP_KERNEL);
+	if (!phy_roothub)
+		return ERR_PTR(-ENOMEM);
+
+	INIT_LIST_HEAD(&phy_roothub->list);
 
 	for (i = 0; i < num_phys; i++) {
 		err = usb_phy_roothub_add_phy(dev, i, &phy_roothub->list);
 		if (err)
-			goto err_out;
+			return ERR_PTR(err);
 	}
 
+	return phy_roothub;
+}
+EXPORT_SYMBOL_GPL(usb_phy_roothub_alloc);
+
+int usb_phy_roothub_init(struct usb_phy_roothub *phy_roothub)
+{
+	struct usb_phy_roothub *roothub_entry;
+	struct list_head *head;
+	int err;
+
+	if (!phy_roothub)
+		return 0;
+
 	head = &phy_roothub->list;
 
 	list_for_each_entry(roothub_entry, head, list) {
@@ -86,14 +88,13 @@ struct usb_phy_roothub *usb_phy_roothub_init(struct device *dev)
 			goto err_exit_phys;
 	}
 
-	return phy_roothub;
+	return 0;
 
 err_exit_phys:
 	list_for_each_entry_continue_reverse(roothub_entry, head, list)
 		phy_exit(roothub_entry->phy);
 
-err_out:
-	return ERR_PTR(err);
+	return err;
 }
 EXPORT_SYMBOL_GPL(usb_phy_roothub_init);
 
diff --git a/drivers/usb/core/phy.h b/drivers/usb/core/phy.h
index 6fde59bfbff8..eb31253201ad 100644
--- a/drivers/usb/core/phy.h
+++ b/drivers/usb/core/phy.h
@@ -1,6 +1,8 @@
 struct usb_phy_roothub;
 
-struct usb_phy_roothub *usb_phy_roothub_init(struct device *dev);
+struct usb_phy_roothub *usb_phy_roothub_alloc(struct device *dev);
+
+int usb_phy_roothub_init(struct usb_phy_roothub *phy_roothub);
 int usb_phy_roothub_exit(struct usb_phy_roothub *phy_roothub);
 
 int usb_phy_roothub_power_on(struct usb_phy_roothub *phy_roothub);
-- 
2.17.0



From martin.blumenstingl at googlemail.com  Wed Apr 18 12:39:46 2018
From: martin.blumenstingl at googlemail.com (Martin Blumenstingl)
Date: Wed, 18 Apr 2018 21:39:46 +0200
Subject: [PATCH usb v6 1/6] usb: core: phy: fix return value of
 usb_phy_roothub_exit()
In-Reply-To: <20180418193951.17922-1-martin.blumenstingl@googlemail.com>
References: <20180418193951.17922-1-martin.blumenstingl@googlemail.com>
Message-ID: <20180418193951.17922-2-martin.blumenstingl@googlemail.com>

usb_phy_roothub_exit() should return the error code from the phy_exit()
call if exiting the PHY failed.
However, since a wrong variable is used usb_phy_roothub_exit() currently
always returns 0, even if one of the phy_exit calls returned an error.
Clang also reports this bug:
kernel/drivers/usb/core/phy.c:114:8: warning: explicitly assigning value of
variable of type 'int' to itself [-Wself-assign] error, forbidden
warning: phy.c:114

Fix this by assigning the error code from phy_exit() to the "ret"
variable to propagate the error correctly.

Fixes: 07dbff0ddbd86c ("usb: core: add a wrapper for the USB PHYs on the HCD")
Signed-off-by: Martin Blumenstingl <martin.blumenstingl at googlemail.com>
Signed-off-by: Rishabh Bhatnagar <rishabhb at codeaurora.org>
Tested-by: Keerthy <j-keerthy at ti.com>
---
 drivers/usb/core/phy.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/usb/core/phy.c b/drivers/usb/core/phy.c
index 09b7c43c0ea4..f19aaa3c899c 100644
--- a/drivers/usb/core/phy.c
+++ b/drivers/usb/core/phy.c
@@ -111,7 +111,7 @@ int usb_phy_roothub_exit(struct usb_phy_roothub *phy_roothub)
 	list_for_each_entry(roothub_entry, head, list) {
 		err = phy_exit(roothub_entry->phy);
 		if (err)
-			ret = ret;
+			ret = err;
 	}
 
 	return ret;
-- 
2.17.0



From martin.blumenstingl at googlemail.com  Wed Apr 18 12:39:49 2018
From: martin.blumenstingl at googlemail.com (Martin Blumenstingl)
Date: Wed, 18 Apr 2018 21:39:49 +0200
Subject: [PATCH usb v6 4/6] usb: core: phy: make it a no-op if
 CONFIG_GENERIC_PHY is disabled
In-Reply-To: <20180418193951.17922-1-martin.blumenstingl@googlemail.com>
References: <20180418193951.17922-1-martin.blumenstingl@googlemail.com>
Message-ID: <20180418193951.17922-5-martin.blumenstingl@googlemail.com>

If the generic PHY support is disabled the stub of devm_of_phy_get_by_index
returns ENOSYS. This corner case isn't handled properly by
usb_phy_roothub_add_phy and at least breaks USB support on Raspberry Pi
(bcm2835_defconfig):

    dwc2 20980000.usb: dwc2_hcd_init() FAILED, returning -38
    dwc2: probe of 20980000.usb failed with error -38

Let usb_phy_roothub_alloc() return in case CONFIG_GENERIC_PHY is
disabled to fix this issue (compilers might even be smart enough to
optimize away most of the code within usb_phy_roothub_alloc and
usb_phy_roothub_add_phy if CONFIG_GENERIC_PHY is disabled). All
existing usb_phy_roothub_* functions are already NULL-safe, so no
special handling is required there.

Fixes: 07dbff0ddbd8 ("usb: core: add a wrapper for the USB PHYs on the HCD")
Reported-by: Stefan Wahren <stefan.wahren at i2se.com>
Signed-off-by: Martin Blumenstingl <martin.blumenstingl at googlemail.com>
---
 drivers/usb/core/phy.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/usb/core/phy.c b/drivers/usb/core/phy.c
index a39d9bb26a4f..9879767452a2 100644
--- a/drivers/usb/core/phy.c
+++ b/drivers/usb/core/phy.c
@@ -50,6 +50,9 @@ struct usb_phy_roothub *usb_phy_roothub_alloc(struct device *dev)
 	struct usb_phy_roothub *phy_roothub;
 	int i, num_phys, err;
 
+	if (!IS_ENABLED(CONFIG_GENERIC_PHY))
+		return NULL;
+
 	num_phys = of_count_phandle_with_args(dev->of_node, "phys",
 					      "#phy-cells");
 	if (num_phys <= 0)
-- 
2.17.0



From martin.blumenstingl at googlemail.com  Wed Apr 18 12:39:51 2018
From: martin.blumenstingl at googlemail.com (Martin Blumenstingl)
Date: Wed, 18 Apr 2018 21:39:51 +0200
Subject: [PATCH usb v6 6/6] usb: core: phy: add the SPDX-License-Identifier
 and include guard
In-Reply-To: <20180418193951.17922-1-martin.blumenstingl@googlemail.com>
References: <20180418193951.17922-1-martin.blumenstingl@googlemail.com>
Message-ID: <20180418193951.17922-7-martin.blumenstingl@googlemail.com>

This clarifies the license of the code. While here also add an include
guard to the header file.

Fixes: 07dbff0ddbd86c ("usb: core: add a wrapper for the USB PHYs on the HCD")
Suggested-by: Masahiro Yamada <yamada.masahiro at socionext.com>
Signed-off-by: Martin Blumenstingl <martin.blumenstingl at googlemail.com>
---
 drivers/usb/core/phy.h | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/drivers/usb/core/phy.h b/drivers/usb/core/phy.h
index bbc969383074..88a3c037e9df 100644
--- a/drivers/usb/core/phy.h
+++ b/drivers/usb/core/phy.h
@@ -1,3 +1,13 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * USB roothub wrapper
+ *
+ * Copyright (C) 2018 Martin Blumenstingl <martin.blumenstingl at googlemail.com>
+ */
+
+#ifndef __USB_CORE_PHY_H_
+#define __USB_CORE_PHY_H_
+
 struct device;
 struct usb_phy_roothub;
 
@@ -13,3 +23,5 @@ int usb_phy_roothub_suspend(struct device *controller_dev,
 			    struct usb_phy_roothub *phy_roothub);
 int usb_phy_roothub_resume(struct device *controller_dev,
 			   struct usb_phy_roothub *phy_roothub);
+
+#endif /* __USB_CORE_PHY_H_ */
-- 
2.17.0



From khilman at baylibre.com  Wed Apr 18 15:43:04 2018
From: khilman at baylibre.com (Kevin Hilman)
Date: Wed, 18 Apr 2018 15:43:04 -0700
Subject: [GIT PULL] Amlogic fixes for v4.17-rc
Message-ID: <7hbmeg5e6f.fsf@baylibre.com>

Arnd, Olof,

Technically, this is more "late" than "fixes", but I have excuses...

1) I was on vacation, but more importantly,
2) There were last minute driver issues that got sorted out after I sent
the main batch v4.17 DT pull requests.  Those issues (USB
suspend/resume) have now been sorted out and merged for v4.17-rc, so I'm
sending this series to enable USB for Amlogic.

This has been tested on Amlogic SoCs on top of v4.17-rc1.

Please pull for v4.17-rc,

Thanks,

Kevin

The following changes since commit 60cc43fc888428bb2f18f08997432d426a243338:

  Linux 4.17-rc1 (2018-04-15 18:24:20 -0700)

are available in the git repository at:

  https://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-amlogic.git tags/amlogic-fixes

for you to fetch changes up to 4b7b0d7b25538d2ad421a1041267d5208d3425bc:

  ARM64: dts: meson-gxm-khadas-vim2: enable the USB controller (2018-04-18 10:24:34 -0700)

----------------------------------------------------------------
Amlogic fixes for v4.17-rc1
- add / enable USB host support for GX boards

----------------------------------------------------------------
Martin Blumenstingl (7):
      ARM64: dts: meson-gxl: add USB host support
      ARM64: dts: meson-gxm: add GXM specific USB host configuration
      ARM64: dts: meson-gxl-s905x-p212: enable the USB controller
      ARM64: dts: meson-gx-p23x-q20x: enable the USB controller
      ARM64: dts: meson-gxl-s905x-libretech-cc: enable the USB controller
      ARM64: dts: meson-gxl-nexbox-a95x: enable the USB controller
      ARM64: dts: meson-gxm-khadas-vim2: enable the USB controller

 arch/arm64/boot/dts/amlogic/meson-gx-p23x-q20x.dtsi          |  4 ++++
 arch/arm64/boot/dts/amlogic/meson-gxl-s905x-libretech-cc.dts | 12 ++++++++++++
 arch/arm64/boot/dts/amlogic/meson-gxl-s905x-nexbox-a95x.dts  |  4 ++++
 arch/arm64/boot/dts/amlogic/meson-gxl-s905x-p212.dtsi        |  4 ++++
 arch/arm64/boot/dts/amlogic/meson-gxl.dtsi                   | 61 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
 arch/arm64/boot/dts/amlogic/meson-gxm-khadas-vim2.dts        |  4 ++++
 arch/arm64/boot/dts/amlogic/meson-gxm.dtsi                   | 17 +++++++++++++++++
 7 files changed, 106 insertions(+)


From narmstrong at baylibre.com  Thu Apr 19 01:18:35 2018
From: narmstrong at baylibre.com (Neil Armstrong)
Date: Thu, 19 Apr 2018 10:18:35 +0200
Subject: [PATCH] drm: bridge: dw-hdmi: Fix overflow workaround for Amlogic
 Meson GX SoCs
In-Reply-To: <1519386277-25902-1-git-send-email-narmstrong@baylibre.com>
References: <1519386277-25902-1-git-send-email-narmstrong@baylibre.com>
Message-ID: <3b17d17b-cf3d-be54-2462-191e4f2af653@baylibre.com>

Hi Greg,

On 23/02/2018 12:44, Neil Armstrong wrote:
> The Amlogic Meson GX SoCs, embedded the v2.01a controller, has been also
> identified needing this workaround.
> This patch adds the corresponding version to enable a single iteration for
> this specific version.
> 
> Fixes: be41fc55f1aa ("drm: bridge: dw-hdmi: Handle overflow workaround based on device version")
> Signed-off-by: Neil Armstrong <narmstrong at baylibre.com>

This patch is now present in linux master as commit 9c305eb442f3b371fc722ade827bbf673514123e
Could it be selected for 4.14 ?
The patch has been reworked to apply for 4.17 as indicated in the commit log, but the original patch will apply over 4.14.

Thanks,
Neil

> ---
>  drivers/gpu/drm/bridge/synopsys/dw-hdmi.c | 3 +++
>  1 file changed, 3 insertions(+)
> 
> diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
> index a38db40..f5018f9 100644
> --- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
> +++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
> @@ -1637,6 +1637,8 @@ static void dw_hdmi_clear_overflow(struct dw_hdmi *hdmi)
>  	 * (and possibly on the platform). So far only i.MX6Q (v1.30a) and
>  	 * i.MX6DL (v1.31a) have been identified as needing the workaround, with
>  	 * 4 and 1 iterations respectively.
> +	 * The Amlogic Meson GX SoCs (v2.01a) have been identifies as needing
> +	 * the workaround with a single iteration.
>  	 */
>  
>  	switch (hdmi->version) {
> @@ -1644,6 +1646,7 @@ static void dw_hdmi_clear_overflow(struct dw_hdmi *hdmi)
>  		count = 4;
>  		break;
>  	case 0x131a:
> +	case 0x201a:
>  		count = 1;
>  		break;
>  	default:
> 



From greg at kroah.com  Thu Apr 19 01:27:51 2018
From: greg at kroah.com (Greg KH)
Date: Thu, 19 Apr 2018 10:27:51 +0200
Subject: [PATCH] drm: bridge: dw-hdmi: Fix overflow workaround for
 Amlogic Meson GX SoCs
In-Reply-To: <3b17d17b-cf3d-be54-2462-191e4f2af653@baylibre.com>
References: <1519386277-25902-1-git-send-email-narmstrong@baylibre.com>
 <3b17d17b-cf3d-be54-2462-191e4f2af653@baylibre.com>
Message-ID: <20180419082751.GA23187@kroah.com>

On Thu, Apr 19, 2018 at 10:18:35AM +0200, Neil Armstrong wrote:
> Hi Greg,
> 
> On 23/02/2018 12:44, Neil Armstrong wrote:
> > The Amlogic Meson GX SoCs, embedded the v2.01a controller, has been also
> > identified needing this workaround.
> > This patch adds the corresponding version to enable a single iteration for
> > this specific version.
> > 
> > Fixes: be41fc55f1aa ("drm: bridge: dw-hdmi: Handle overflow workaround based on device version")
> > Signed-off-by: Neil Armstrong <narmstrong at baylibre.com>
> 
> This patch is now present in linux master as commit 9c305eb442f3b371fc722ade827bbf673514123e
> Could it be selected for 4.14 ?
> The patch has been reworked to apply for 4.17 as indicated in the commit log, but the original patch will apply over 4.14.

I don't have any "original" patch here, I just tried applying it to
4.16.y and 4.14.y and it did not work.  Can you please provide a working
backport?

thanks,

greg k-h


From narmstrong at baylibre.com  Thu Apr 19 01:54:08 2018
From: narmstrong at baylibre.com (Neil Armstrong)
Date: Thu, 19 Apr 2018 10:54:08 +0200
Subject: [PATCH stable] drm: bridge: dw-hdmi: Fix overflow workaround for
 Amlogic Meson GX SoCs
Message-ID: <1524128048-11086-1-git-send-email-narmstrong@baylibre.com>

commit 9c305eb442f3b371fc722ade827bbf673514123e upstream

The Amlogic Meson GX SoCs, embedded the v2.01a controller, has been also
identified needing this workaround.
This patch adds the corresponding version to enable a single iteration for
this specific version.

Fixes: be41fc55f1aa ("drm: bridge: dw-hdmi: Handle overflow workaround based on device version")
Acked-by: Archit Taneja <architt at codeaurora.org>
[narmstrong: s/identifies/identified and rebased against Jernej's change]
Signed-off-by: Neil Armstrong <narmstrong at baylibre.com>
Link: https://patchwork.freedesktop.org/patch/msgid/1519386277-25902-1-git-send-email-narmstrong at baylibre.com
[narmstrong: v4.14 to v4.16 backport]
Cc: <stable at vger.kernel.org> # 4.14.x
---
 drivers/gpu/drm/bridge/synopsys/dw-hdmi.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
index bf14214..4db31b8 100644
--- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
+++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
@@ -1634,6 +1634,8 @@ static void dw_hdmi_clear_overflow(struct dw_hdmi *hdmi)
 	 * (and possibly on the platform). So far only i.MX6Q (v1.30a) and
 	 * i.MX6DL (v1.31a) have been identified as needing the workaround, with
 	 * 4 and 1 iterations respectively.
+	 * The Amlogic Meson GX SoCs (v2.01a) have been identified as needing
+	 * the workaround with a single iteration.
 	 */
 
 	switch (hdmi->version) {
@@ -1641,6 +1643,7 @@ static void dw_hdmi_clear_overflow(struct dw_hdmi *hdmi)
 		count = 4;
 		break;
 	case 0x131a:
+	case 0x201a:
 		count = 1;
 		break;
 	default:
-- 
2.7.4



From yixun.lan at amlogic.com  Thu Apr 19 06:54:19 2018
From: yixun.lan at amlogic.com (Yixun Lan)
Date: Thu, 19 Apr 2018 21:54:19 +0800
Subject: [PATCH v6 0/7] clk: meson-axg: Add AO Cloclk and Reset driver
Message-ID: <20180419135426.155794-1-yixun.lan@amlogic.com>

  This patch try to add AO clock and Reset driver for Amlogic's
Meson-AXG SoC.
  Please note that patch 7 need to wait for the DTS changes[3] merged
into mainline first, otherwise it will break the serial console.

 patch 2: factor the common code into a dedicated file
 patch 3-5: add the aoclk driver for AXG SoC
 patch 6-7: drop unnecessary clock flags

changes since v5 at [6]: 
 - drop unnecessary header files
 - add 'axg_aoclk' prefix to clk driver, make them more consistent
 - add missing end new line..

changes since v4 at [5]: 
 - fix return err
 - introduce CONFIG_COMMON_CLK_MESON_AO
 - format/style minor fix

changes since v3 at [4]: 
 - add 'const' contraint to the read-only data
 - switch to devm_of_clk_add_hw_provider API
 - check return value of devm_reset_controller_register

changes since v2 at [2]: 
 - rework meson_aoclkc_probe() which leverage the of_match_data
 - merge patch 5-6 into this series
 - seperate DTS patch, will send to Kevin Hilman independently
 
changes since v1 at [0]: 
 - rebase to clk-meson's branch 'next/drivers' [1]
 - fix license, update to BSD-3-Clause
 - drop un-used include header file

[0] https://lkml.kernel.org/r/20180209070026.193879-1-yixun.lan at amlogic.com
[1] git://github.com/BayLibre/clk-meson.git branch: next-drivers
[2] https://lkml.kernel.org/r/20180323143816.200573-1-yixun.lan at amlogic.com
[3] https://lkml.kernel.org/r/20180326081809.49493-4-yixun.lan at amlogic.com
[4] https://lkml.kernel.org/r/20180328025050.221585-1-yixun.lan at amlogic.com
[5] https://lkml.kernel.org/r/20180408031938.153474-1-yixun.lan at amlogic.com
[6] https://lkml.kernel.org/r/20180409143749.71197-1-yixun.lan at amlogic.com


Qiufang Dai (1):
  clk: meson-axg: Add AO Clock and Reset controller driver

Yixun Lan (6):
  clk: meson: migrate to devm_of_clk_add_hw_provider API
  clk: meson: aoclk: refactor common code into dedicated file
  dt-bindings: clock: axg-aoclkc: New binding for Meson-AXG SoC
  dt-bindings: clock: reset: Add AXG AO Clock and Reset Bindings
  clk: meson: drop CLK_SET_RATE_PARENT flag
  clk: meson: drop CLK_IGNORE_UNUSED flag

 .../bindings/clock/amlogic,gxbb-aoclkc.txt         |   1 +
 drivers/clk/meson/Kconfig                          |   8 +
 drivers/clk/meson/Makefile                         |   3 +-
 drivers/clk/meson/axg-aoclk.c                      | 164 +++++++++++++++++++++
 drivers/clk/meson/axg-aoclk.h                      |  30 ++++
 drivers/clk/meson/gxbb-aoclk.c                     |  96 +++++-------
 drivers/clk/meson/gxbb-aoclk.h                     |   6 +
 drivers/clk/meson/meson-aoclk.c                    |  82 +++++++++++
 drivers/clk/meson/meson-aoclk.h                    |  35 +++++
 include/dt-bindings/clock/axg-aoclkc.h             |  26 ++++
 include/dt-bindings/reset/axg-aoclkc.h             |  20 +++
 11 files changed, 407 insertions(+), 64 deletions(-)
 create mode 100644 drivers/clk/meson/axg-aoclk.c
 create mode 100644 drivers/clk/meson/axg-aoclk.h
 create mode 100644 drivers/clk/meson/meson-aoclk.c
 create mode 100644 drivers/clk/meson/meson-aoclk.h
 create mode 100644 include/dt-bindings/clock/axg-aoclkc.h
 create mode 100644 include/dt-bindings/reset/axg-aoclkc.h

-- 
2.15.1



From yixun.lan at amlogic.com  Thu Apr 19 06:54:20 2018
From: yixun.lan at amlogic.com (Yixun Lan)
Date: Thu, 19 Apr 2018 21:54:20 +0800
Subject: [PATCH v6 1/7] clk: meson: migrate to devm_of_clk_add_hw_provider API
In-Reply-To: <20180419135426.155794-1-yixun.lan@amlogic.com>
References: <20180419135426.155794-1-yixun.lan@amlogic.com>
Message-ID: <20180419135426.155794-2-yixun.lan@amlogic.com>

There is a protential memory leak, as of_clk_del_provider is
never called if of_clk_add_hw_provider has been executed.
Fix this by using devm variant API.

Fixes: f8c11f79912d ("clk: meson: Add GXBB AO Clock and Reset controller driver")
Suggested-by: Stephen Boyd <sboyd at kernel.org>
Signed-off-by: Yixun Lan <yixun.lan at amlogic.com>
---
 drivers/clk/meson/gxbb-aoclk.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/clk/meson/gxbb-aoclk.c b/drivers/clk/meson/gxbb-aoclk.c
index 9ec23ae9a219..eebb580b9e0f 100644
--- a/drivers/clk/meson/gxbb-aoclk.c
+++ b/drivers/clk/meson/gxbb-aoclk.c
@@ -191,7 +191,7 @@ static int gxbb_aoclkc_probe(struct platform_device *pdev)
 	if (ret)
 		return ret;
 
-	return of_clk_add_hw_provider(dev->of_node, of_clk_hw_onecell_get,
+	return devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get,
 			&gxbb_aoclk_onecell_data);
 }
 
-- 
2.15.1



From yixun.lan at amlogic.com  Thu Apr 19 06:54:21 2018
From: yixun.lan at amlogic.com (Yixun Lan)
Date: Thu, 19 Apr 2018 21:54:21 +0800
Subject: [PATCH v6 2/7] clk: meson: aoclk: refactor common code into dedicated
 file
In-Reply-To: <20180419135426.155794-1-yixun.lan@amlogic.com>
References: <20180419135426.155794-1-yixun.lan@amlogic.com>
Message-ID: <20180419135426.155794-3-yixun.lan@amlogic.com>

We try to refactor the common code into one dedicated file,
while preparing to add new Meson-AXG aoclk driver, this would
help us to better share the code by all aoclk drivers.

Suggested-by: Jerome Brunet <jbrunet at baylibre.com>
Signed-off-by: Yixun Lan <yixun.lan at amlogic.com>
---
 drivers/clk/meson/Kconfig       |  7 +++
 drivers/clk/meson/Makefile      |  1 +
 drivers/clk/meson/gxbb-aoclk.c  | 95 ++++++++++++++---------------------------
 drivers/clk/meson/gxbb-aoclk.h  |  6 +++
 drivers/clk/meson/meson-aoclk.c | 82 +++++++++++++++++++++++++++++++++++
 drivers/clk/meson/meson-aoclk.h | 35 +++++++++++++++
 6 files changed, 164 insertions(+), 62 deletions(-)
 create mode 100644 drivers/clk/meson/meson-aoclk.c
 create mode 100644 drivers/clk/meson/meson-aoclk.h

diff --git a/drivers/clk/meson/Kconfig b/drivers/clk/meson/Kconfig
index d5cbec522aec..fddc7ec7b820 100644
--- a/drivers/clk/meson/Kconfig
+++ b/drivers/clk/meson/Kconfig
@@ -3,6 +3,12 @@ config COMMON_CLK_AMLOGIC
 	depends on OF
 	depends on ARCH_MESON || COMPILE_TEST
 
+config COMMON_CLK_MESON_AO
+	bool
+	depends on OF
+	depends on ARCH_MESON || COMPILE_TEST
+	select COMMON_CLK_REGMAP_MESON
+
 config COMMON_CLK_REGMAP_MESON
 	bool
 	select REGMAP
@@ -21,6 +27,7 @@ config COMMON_CLK_GXBB
 	bool
 	depends on COMMON_CLK_AMLOGIC
 	select RESET_CONTROLLER
+	select COMMON_CLK_MESON_AO
 	select COMMON_CLK_REGMAP_MESON
 	select MFD_SYSCON
 	help
diff --git a/drivers/clk/meson/Makefile b/drivers/clk/meson/Makefile
index ffee82e60b7a..0a8df284f4e7 100644
--- a/drivers/clk/meson/Makefile
+++ b/drivers/clk/meson/Makefile
@@ -3,6 +3,7 @@
 #
 
 obj-$(CONFIG_COMMON_CLK_AMLOGIC) += clk-pll.o clk-mpll.o clk-audio-divider.o
+obj-$(CONFIG_COMMON_CLK_MESON_AO) += meson-aoclk.o
 obj-$(CONFIG_COMMON_CLK_MESON8B) += meson8b.o
 obj-$(CONFIG_COMMON_CLK_GXBB)	 += gxbb.o gxbb-aoclk.o gxbb-aoclk-32k.o
 obj-$(CONFIG_COMMON_CLK_AXG)	 += axg.o
diff --git a/drivers/clk/meson/gxbb-aoclk.c b/drivers/clk/meson/gxbb-aoclk.c
index eebb580b9e0f..c785ee7586d1 100644
--- a/drivers/clk/meson/gxbb-aoclk.c
+++ b/drivers/clk/meson/gxbb-aoclk.c
@@ -52,39 +52,12 @@
  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */
-#include <linux/clk-provider.h>
-#include <linux/of_address.h>
 #include <linux/platform_device.h>
-#include <linux/reset-controller.h>
 #include <linux/mfd/syscon.h>
-#include <linux/regmap.h>
-#include <linux/init.h>
-#include <linux/delay.h>
-#include <dt-bindings/clock/gxbb-aoclkc.h>
-#include <dt-bindings/reset/gxbb-aoclkc.h>
 #include "clk-regmap.h"
+#include "meson-aoclk.h"
 #include "gxbb-aoclk.h"
 
-struct gxbb_aoclk_reset_controller {
-	struct reset_controller_dev reset;
-	unsigned int *data;
-	struct regmap *regmap;
-};
-
-static int gxbb_aoclk_do_reset(struct reset_controller_dev *rcdev,
-			       unsigned long id)
-{
-	struct gxbb_aoclk_reset_controller *reset =
-		container_of(rcdev, struct gxbb_aoclk_reset_controller, reset);
-
-	return regmap_write(reset->regmap, AO_RTI_GEN_CNTL_REG0,
-			    BIT(reset->data[id]));
-}
-
-static const struct reset_control_ops gxbb_aoclk_reset_ops = {
-	.reset = gxbb_aoclk_do_reset,
-};
-
 #define GXBB_AO_GATE(_name, _bit)					\
 static struct clk_regmap _name##_ao = {					\
 	.data = &(struct clk_regmap_gate_data) {			\
@@ -117,7 +90,7 @@ static struct aoclk_cec_32k cec_32k_ao = {
 	},
 };
 
-static unsigned int gxbb_aoclk_reset[] = {
+static const unsigned int gxbb_aoclk_reset[] = {
 	[RESET_AO_REMOTE] = 16,
 	[RESET_AO_I2C_MASTER] = 18,
 	[RESET_AO_I2C_SLAVE] = 19,
@@ -135,7 +108,7 @@ static struct clk_regmap *gxbb_aoclk_gate[] = {
 	[CLKID_AO_IR_BLASTER] = &ir_blaster_ao,
 };
 
-static struct clk_hw_onecell_data gxbb_aoclk_onecell_data = {
+static const struct clk_hw_onecell_data gxbb_aoclk_onecell_data = {
 	.hws = {
 		[CLKID_AO_REMOTE] = &remote_ao.hw,
 		[CLKID_AO_I2C_MASTER] = &i2c_master_ao.hw,
@@ -145,58 +118,55 @@ static struct clk_hw_onecell_data gxbb_aoclk_onecell_data = {
 		[CLKID_AO_IR_BLASTER] = &ir_blaster_ao.hw,
 		[CLKID_AO_CEC_32K] = &cec_32k_ao.hw,
 	},
-	.num = 7,
+	.num = NR_CLKS,
 };
 
-static int gxbb_aoclkc_probe(struct platform_device *pdev)
+static int gxbb_register_cec_ao_32k(struct platform_device *pdev)
 {
-	struct gxbb_aoclk_reset_controller *rstc;
 	struct device *dev = &pdev->dev;
 	struct regmap *regmap;
-	int ret, clkid;
-
-	rstc = devm_kzalloc(dev, sizeof(*rstc), GFP_KERNEL);
-	if (!rstc)
-		return -ENOMEM;
+	int ret;
 
 	regmap = syscon_node_to_regmap(of_get_parent(dev->of_node));
 	if (IS_ERR(regmap)) {
 		dev_err(dev, "failed to get regmap\n");
-		return -ENODEV;
-	}
-
-	/* Reset Controller */
-	rstc->regmap = regmap;
-	rstc->data = gxbb_aoclk_reset;
-	rstc->reset.ops = &gxbb_aoclk_reset_ops;
-	rstc->reset.nr_resets = ARRAY_SIZE(gxbb_aoclk_reset);
-	rstc->reset.of_node = dev->of_node;
-	ret = devm_reset_controller_register(dev, &rstc->reset);
-
-	/*
-	 * Populate regmap and register all clks
-	 */
-	for (clkid = 0; clkid < ARRAY_SIZE(gxbb_aoclk_gate); clkid++) {
-		gxbb_aoclk_gate[clkid]->map = regmap;
-
-		ret = devm_clk_hw_register(dev,
-					   gxbb_aoclk_onecell_data.hws[clkid]);
-		if (ret)
-			return ret;
+		return PTR_ERR(regmap);
 	}
 
 	/* Specific clocks */
 	cec_32k_ao.regmap = regmap;
 	ret = devm_clk_hw_register(dev, &cec_32k_ao.hw);
+	if (ret) {
+		dev_err(&pdev->dev, "clk cec_32k_ao register failed.\n");
+		return ret;
+	}
+
+	return 0;
+}
+
+static const struct meson_aoclk_data gxbb_aoclkc_data = {
+	.reset_reg	= AO_RTI_GEN_CNTL_REG0,
+	.num_reset	= ARRAY_SIZE(gxbb_aoclk_reset),
+	.reset		= gxbb_aoclk_reset,
+	.num_clks	= ARRAY_SIZE(gxbb_aoclk_gate),
+	.clks		= gxbb_aoclk_gate,
+	.hw_data	= &gxbb_aoclk_onecell_data,
+};
+
+static int gxbb_aoclkc_probe(struct platform_device *pdev)
+{
+	int ret = gxbb_register_cec_ao_32k(pdev);
 	if (ret)
 		return ret;
 
-	return devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get,
-			&gxbb_aoclk_onecell_data);
+	return meson_aoclkc_probe(pdev);
 }
 
 static const struct of_device_id gxbb_aoclkc_match_table[] = {
-	{ .compatible = "amlogic,meson-gx-aoclkc" },
+	{
+		.compatible	= "amlogic,meson-gx-aoclkc",
+		.data		= &gxbb_aoclkc_data,
+	},
 	{ }
 };
 
@@ -208,3 +178,4 @@ static struct platform_driver gxbb_aoclkc_driver = {
 	},
 };
 builtin_platform_driver(gxbb_aoclkc_driver);
+
diff --git a/drivers/clk/meson/gxbb-aoclk.h b/drivers/clk/meson/gxbb-aoclk.h
index badc4c22b4ee..9193f7661345 100644
--- a/drivers/clk/meson/gxbb-aoclk.h
+++ b/drivers/clk/meson/gxbb-aoclk.h
@@ -8,6 +8,8 @@
 #ifndef __GXBB_AOCLKC_H
 #define __GXBB_AOCLKC_H
 
+#define NR_CLKS	7
+
 /* AO Configuration Clock registers offsets */
 #define AO_RTI_PWR_CNTL_REG1	0x0c
 #define AO_RTI_PWR_CNTL_REG0	0x10
@@ -26,4 +28,8 @@ struct aoclk_cec_32k {
 
 extern const struct clk_ops meson_aoclk_cec_32k_ops;
 
+#include <dt-bindings/clock/gxbb-aoclkc.h>
+#include <dt-bindings/reset/gxbb-aoclkc.h>
+
 #endif /* __GXBB_AOCLKC_H */
+
diff --git a/drivers/clk/meson/meson-aoclk.c b/drivers/clk/meson/meson-aoclk.c
new file mode 100644
index 000000000000..963ab87d1da7
--- /dev/null
+++ b/drivers/clk/meson/meson-aoclk.c
@@ -0,0 +1,82 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Amlogic Meson-AXG Clock Controller Driver
+ *
+ * Copyright (c) 2016 BayLibre, SAS.
+ * Author: Neil Armstrong <narmstrong at baylibre.com>
+ *
+ * Copyright (c) 2018 Amlogic, inc.
+ * Author: Qiufang Dai <qiufang.dai at amlogic.com>
+ * Author: Yixun Lan <yixun.lan at amlogic.com>
+ */
+
+#include <linux/platform_device.h>
+#include <linux/reset-controller.h>
+#include <linux/mfd/syscon.h>
+#include <linux/of_device.h>
+#include "clk-regmap.h"
+#include "meson-aoclk.h"
+
+static int meson_aoclk_do_reset(struct reset_controller_dev *rcdev,
+			       unsigned long id)
+{
+	struct meson_aoclk_reset_controller *rstc =
+		container_of(rcdev, struct meson_aoclk_reset_controller, reset);
+
+	return regmap_write(rstc->regmap, rstc->data->reset_reg,
+			    BIT(rstc->data->reset[id]));
+}
+
+static const struct reset_control_ops meson_aoclk_reset_ops = {
+	.reset = meson_aoclk_do_reset,
+};
+
+int meson_aoclkc_probe(struct platform_device *pdev)
+{
+	struct meson_aoclk_reset_controller *rstc;
+	struct meson_aoclk_data *data;
+	struct device *dev = &pdev->dev;
+	struct regmap *regmap;
+	int ret, clkid;
+
+	data = (struct meson_aoclk_data *) of_device_get_match_data(dev);
+	if (!data)
+		return -ENODEV;
+
+	rstc = devm_kzalloc(dev, sizeof(*rstc), GFP_KERNEL);
+	if (!rstc)
+		return -ENOMEM;
+
+	regmap = syscon_node_to_regmap(of_get_parent(dev->of_node));
+	if (IS_ERR(regmap)) {
+		dev_err(dev, "failed to get regmap\n");
+		return PTR_ERR(regmap);
+	}
+
+	/* Reset Controller */
+	rstc->data = data;
+	rstc->regmap = regmap;
+	rstc->reset.ops = &meson_aoclk_reset_ops;
+	rstc->reset.nr_resets = data->num_reset,
+	rstc->reset.of_node = dev->of_node;
+	ret = devm_reset_controller_register(dev, &rstc->reset);
+	if (ret) {
+		dev_err(dev, "failed to register reset controller\n");
+		return ret;
+	}
+
+	/*
+	 * Populate regmap and register all clks
+	 */
+	for (clkid = 0; clkid < data->num_clks; clkid++) {
+		data->clks[clkid]->map = regmap;
+
+		ret = devm_clk_hw_register(dev, data->hw_data->hws[clkid]);
+		if (ret)
+			return ret;
+	}
+
+	return devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get,
+		(void *) data->hw_data);
+}
+
diff --git a/drivers/clk/meson/meson-aoclk.h b/drivers/clk/meson/meson-aoclk.h
new file mode 100644
index 000000000000..ec59e027dd37
--- /dev/null
+++ b/drivers/clk/meson/meson-aoclk.h
@@ -0,0 +1,35 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2017 BayLibre, SAS
+ * Author: Neil Armstrong <narmstrong at baylibre.com>
+ *
+ * Copyright (c) 2018 Amlogic, inc.
+ * Author: Qiufang Dai <qiufang.dai at amlogic.com>
+ * Author: Yixun Lan <yixun.lan at amlogic.com>
+ */
+
+#ifndef __MESON_AOCLK_H__
+#define __MESON_AOCLK_H__
+
+#include <linux/platform_device.h>
+#include <linux/reset-controller.h>
+#include "clk-regmap.h"
+
+struct meson_aoclk_data {
+	const unsigned int			reset_reg;
+	const int				num_reset;
+	const unsigned int			*reset;
+	int					num_clks;
+	struct clk_regmap			**clks;
+	const struct clk_hw_onecell_data	*hw_data;
+};
+
+struct meson_aoclk_reset_controller {
+	struct reset_controller_dev		reset;
+	const struct meson_aoclk_data		*data;
+	struct regmap				*regmap;
+};
+
+int meson_aoclkc_probe(struct platform_device *pdev);
+#endif
+
-- 
2.15.1



From yixun.lan at amlogic.com  Thu Apr 19 06:54:22 2018
From: yixun.lan at amlogic.com (Yixun Lan)
Date: Thu, 19 Apr 2018 21:54:22 +0800
Subject: [PATCH v6 3/7] dt-bindings: clock: axg-aoclkc: New binding for
 Meson-AXG SoC
In-Reply-To: <20180419135426.155794-1-yixun.lan@amlogic.com>
References: <20180419135426.155794-1-yixun.lan@amlogic.com>
Message-ID: <20180419135426.155794-4-yixun.lan@amlogic.com>

Update the dt-binding documentation to support new compatible string
for the Amlogic's Meson-AXG SoC.

Reviewed-by: Rob Herring <robh at kernel.org>
Signed-off-by: Yixun Lan <yixun.lan at amlogic.com>
---
 Documentation/devicetree/bindings/clock/amlogic,gxbb-aoclkc.txt | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/clock/amlogic,gxbb-aoclkc.txt b/Documentation/devicetree/bindings/clock/amlogic,gxbb-aoclkc.txt
index 786dc39ca904..3a880528030e 100644
--- a/Documentation/devicetree/bindings/clock/amlogic,gxbb-aoclkc.txt
+++ b/Documentation/devicetree/bindings/clock/amlogic,gxbb-aoclkc.txt
@@ -9,6 +9,7 @@ Required Properties:
 	- GXBB (S905) : "amlogic,meson-gxbb-aoclkc"
 	- GXL (S905X, S905D) : "amlogic,meson-gxl-aoclkc"
 	- GXM (S912) : "amlogic,meson-gxm-aoclkc"
+	- AXG (A113D, A113X) : "amlogic,meson-axg-aoclkc"
 	followed by the common "amlogic,meson-gx-aoclkc"
 
 - #clock-cells: should be 1.
-- 
2.15.1



From yixun.lan at amlogic.com  Thu Apr 19 06:54:23 2018
From: yixun.lan at amlogic.com (Yixun Lan)
Date: Thu, 19 Apr 2018 21:54:23 +0800
Subject: [PATCH v6 4/7] dt-bindings: clock: reset: Add AXG AO Clock and Reset
 Bindings
In-Reply-To: <20180419135426.155794-1-yixun.lan@amlogic.com>
References: <20180419135426.155794-1-yixun.lan@amlogic.com>
Message-ID: <20180419135426.155794-5-yixun.lan@amlogic.com>

Add dt-bindings headers for the Meson-AXG's AO clock and
reset controller.

Reviewed-by: Rob Herring <robh at kernel.org>
Signed-off-by: Yixun Lan <yixun.lan at amlogic.com>
---
 include/dt-bindings/clock/axg-aoclkc.h | 26 ++++++++++++++++++++++++++
 include/dt-bindings/reset/axg-aoclkc.h | 20 ++++++++++++++++++++
 2 files changed, 46 insertions(+)
 create mode 100644 include/dt-bindings/clock/axg-aoclkc.h
 create mode 100644 include/dt-bindings/reset/axg-aoclkc.h

diff --git a/include/dt-bindings/clock/axg-aoclkc.h b/include/dt-bindings/clock/axg-aoclkc.h
new file mode 100644
index 000000000000..61955016a55b
--- /dev/null
+++ b/include/dt-bindings/clock/axg-aoclkc.h
@@ -0,0 +1,26 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */
+/*
+ * Copyright (c) 2016 BayLibre, SAS
+ * Author: Neil Armstrong <narmstrong at baylibre.com>
+ *
+ * Copyright (c) 2018 Amlogic, inc.
+ * Author: Qiufang Dai <qiufang.dai at amlogic.com>
+ */
+
+#ifndef DT_BINDINGS_CLOCK_AMLOGIC_MESON_AXG_AOCLK
+#define DT_BINDINGS_CLOCK_AMLOGIC_MESON_AXG_AOCLK
+
+#define CLKID_AO_REMOTE		0
+#define CLKID_AO_I2C_MASTER	1
+#define CLKID_AO_I2C_SLAVE	2
+#define CLKID_AO_UART1		3
+#define CLKID_AO_UART2		4
+#define CLKID_AO_IR_BLASTER	5
+#define CLKID_AO_SAR_ADC	6
+#define CLKID_AO_CLK81		7
+#define CLKID_AO_SAR_ADC_SEL	8
+#define CLKID_AO_SAR_ADC_DIV	9
+#define CLKID_AO_SAR_ADC_CLK	10
+#define CLKID_AO_ALT_XTAL	11
+
+#endif
diff --git a/include/dt-bindings/reset/axg-aoclkc.h b/include/dt-bindings/reset/axg-aoclkc.h
new file mode 100644
index 000000000000..d342c0b6b2a7
--- /dev/null
+++ b/include/dt-bindings/reset/axg-aoclkc.h
@@ -0,0 +1,20 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */
+/*
+ * Copyright (c) 2016 BayLibre, SAS
+ * Author: Neil Armstrong <narmstrong at baylibre.com>
+ *
+ * Copyright (c) 2018 Amlogic, inc.
+ * Author: Qiufang Dai <qiufang.dai at amlogic.com>
+ */
+
+#ifndef DT_BINDINGS_RESET_AMLOGIC_MESON_AXG_AOCLK
+#define DT_BINDINGS_RESET_AMLOGIC_MESON_AXG_AOCLK
+
+#define RESET_AO_REMOTE		0
+#define RESET_AO_I2C_MASTER	1
+#define RESET_AO_I2C_SLAVE	2
+#define RESET_AO_UART1		3
+#define RESET_AO_UART2		4
+#define RESET_AO_IR_BLASTER	5
+
+#endif
-- 
2.15.1



From yixun.lan at amlogic.com  Thu Apr 19 06:54:24 2018
From: yixun.lan at amlogic.com (Yixun Lan)
Date: Thu, 19 Apr 2018 21:54:24 +0800
Subject: [PATCH v6 5/7] clk: meson-axg: Add AO Clock and Reset controller
 driver
In-Reply-To: <20180419135426.155794-1-yixun.lan@amlogic.com>
References: <20180419135426.155794-1-yixun.lan@amlogic.com>
Message-ID: <20180419135426.155794-6-yixun.lan@amlogic.com>

From: Qiufang Dai <qiufang.dai at amlogic.com>

Adds a Clock and Reset controller driver for the Always-On part
of the Amlogic Meson-AXG SoC.

Signed-off-by: Qiufang Dai <qiufang.dai at amlogic.com>
Signed-off-by: Yixun Lan <yixun.lan at amlogic.com>
---
 drivers/clk/meson/Kconfig     |   1 +
 drivers/clk/meson/Makefile    |   2 +-
 drivers/clk/meson/axg-aoclk.c | 165 ++++++++++++++++++++++++++++++++++++++++++
 drivers/clk/meson/axg-aoclk.h |  30 ++++++++
 4 files changed, 197 insertions(+), 1 deletion(-)
 create mode 100644 drivers/clk/meson/axg-aoclk.c
 create mode 100644 drivers/clk/meson/axg-aoclk.h

diff --git a/drivers/clk/meson/Kconfig b/drivers/clk/meson/Kconfig
index fddc7ec7b820..815659eebea3 100644
--- a/drivers/clk/meson/Kconfig
+++ b/drivers/clk/meson/Kconfig
@@ -38,6 +38,7 @@ config COMMON_CLK_AXG
 	bool
 	depends on COMMON_CLK_AMLOGIC
 	select RESET_CONTROLLER
+	select COMMON_CLK_MESON_AO
 	select COMMON_CLK_REGMAP_MESON
 	select MFD_SYSCON
 	help
diff --git a/drivers/clk/meson/Makefile b/drivers/clk/meson/Makefile
index 0a8df284f4e7..d0d13aeb369a 100644
--- a/drivers/clk/meson/Makefile
+++ b/drivers/clk/meson/Makefile
@@ -6,5 +6,5 @@ obj-$(CONFIG_COMMON_CLK_AMLOGIC) += clk-pll.o clk-mpll.o clk-audio-divider.o
 obj-$(CONFIG_COMMON_CLK_MESON_AO) += meson-aoclk.o
 obj-$(CONFIG_COMMON_CLK_MESON8B) += meson8b.o
 obj-$(CONFIG_COMMON_CLK_GXBB)	 += gxbb.o gxbb-aoclk.o gxbb-aoclk-32k.o
-obj-$(CONFIG_COMMON_CLK_AXG)	 += axg.o
+obj-$(CONFIG_COMMON_CLK_AXG)	 += axg.o axg-aoclk.o
 obj-$(CONFIG_COMMON_CLK_REGMAP_MESON)	+= clk-regmap.o
diff --git a/drivers/clk/meson/axg-aoclk.c b/drivers/clk/meson/axg-aoclk.c
new file mode 100644
index 000000000000..a5d00ef12268
--- /dev/null
+++ b/drivers/clk/meson/axg-aoclk.c
@@ -0,0 +1,165 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Amlogic Meson-AXG Clock Controller Driver
+ *
+ * Copyright (c) 2016 Baylibre SAS.
+ * Author: Michael Turquette <mturquette at baylibre.com>
+ *
+ * Copyright (c) 2018 Amlogic, inc.
+ * Author: Qiufang Dai <qiufang.dai at amlogic.com>
+ */
+#include <linux/clk-provider.h>
+#include <linux/platform_device.h>
+#include <linux/reset-controller.h>
+#include <linux/mfd/syscon.h>
+#include "clk-regmap.h"
+#include "meson-aoclk.h"
+#include "axg-aoclk.h"
+
+#define AXG_AO_GATE(_name, _bit)					\
+static struct clk_regmap axg_aoclk_##_name = {					\
+	.data = &(struct clk_regmap_gate_data) {			\
+		.offset = (AO_RTI_GEN_CNTL_REG0),			\
+		.bit_idx = (_bit),					\
+	},								\
+	.hw.init = &(struct clk_init_data) {				\
+		.name =  "axg_ao_" #_name,					\
+		.ops = &clk_regmap_gate_ops,				\
+		.parent_names = (const char *[]){ "clk81" },		\
+		.num_parents = 1,					\
+		.flags = CLK_IGNORE_UNUSED,				\
+	},								\
+}
+
+AXG_AO_GATE(remote, 0);
+AXG_AO_GATE(i2c_master, 1);
+AXG_AO_GATE(i2c_slave, 2);
+AXG_AO_GATE(uart1, 3);
+AXG_AO_GATE(uart2, 5);
+AXG_AO_GATE(ir_blaster, 6);
+AXG_AO_GATE(saradc, 7);
+
+static struct clk_regmap axg_aoclk_clk81 = {
+	.data = &(struct clk_regmap_mux_data) {
+		.offset = AO_RTI_PWR_CNTL_REG0,
+		.mask = 0x1,
+		.shift = 8,
+	},
+	.hw.init = &(struct clk_init_data){
+		.name = "axg_ao_clk81",
+		.ops = &clk_regmap_mux_ro_ops,
+		.parent_names = (const char *[]){ "clk81", "ao_alt_xtal"},
+		.num_parents = 2,
+	},
+};
+
+static struct clk_regmap axg_aoclk_saradc_mux = {
+	.data = &(struct clk_regmap_mux_data) {
+		.offset = AO_SAR_CLK,
+		.mask = 0x3,
+		.shift = 9,
+	},
+	.hw.init = &(struct clk_init_data){
+		.name = "axg_ao_saradc_mux",
+		.ops = &clk_regmap_mux_ops,
+		.parent_names = (const char *[]){ "xtal", "axg_ao_clk81" },
+		.num_parents = 2,
+	},
+};
+
+static struct clk_regmap axg_aoclk_saradc_div = {
+	.data = &(struct clk_regmap_div_data) {
+		.offset = AO_SAR_CLK,
+		.shift = 0,
+		.width = 8,
+	},
+	.hw.init = &(struct clk_init_data){
+		.name = "axg_ao_saradc_div",
+		.ops = &clk_regmap_divider_ops,
+		.parent_names = (const char *[]){ "axg_ao_saradc_mux" },
+		.num_parents = 1,
+		.flags = CLK_SET_RATE_PARENT,
+	},
+};
+
+static struct clk_regmap axg_aoclk_saradc_gate = {
+	.data = &(struct clk_regmap_gate_data) {
+		.offset = AO_SAR_CLK,
+		.bit_idx = 8,
+	},
+	.hw.init = &(struct clk_init_data){
+		.name = "axg_ao_saradc_gate",
+		.ops = &clk_regmap_gate_ops,
+		.parent_names = (const char *[]){ "axg_ao_saradc_div" },
+		.num_parents = 1,
+		.flags = CLK_SET_RATE_PARENT,
+	},
+};
+
+static const unsigned int axg_aoclk_reset[] = {
+	[RESET_AO_REMOTE]	= 16,
+	[RESET_AO_I2C_MASTER]	= 18,
+	[RESET_AO_I2C_SLAVE]	= 19,
+	[RESET_AO_UART1]	= 17,
+	[RESET_AO_UART2]	= 22,
+	[RESET_AO_IR_BLASTER]	= 23,
+};
+
+static struct clk_regmap *axg_aoclk_regmap[] = {
+	[CLKID_AO_REMOTE]	= &axg_aoclk_remote,
+	[CLKID_AO_I2C_MASTER]	= &axg_aoclk_i2c_master,
+	[CLKID_AO_I2C_SLAVE]	= &axg_aoclk_i2c_slave,
+	[CLKID_AO_UART1]	= &axg_aoclk_uart1,
+	[CLKID_AO_UART2]	= &axg_aoclk_uart2,
+	[CLKID_AO_IR_BLASTER]	= &axg_aoclk_ir_blaster,
+	[CLKID_AO_SAR_ADC]	= &axg_aoclk_saradc,
+	[CLKID_AO_CLK81]	= &axg_aoclk_clk81,
+	[CLKID_AO_SAR_ADC_SEL]	= &axg_aoclk_saradc_mux,
+	[CLKID_AO_SAR_ADC_DIV]	= &axg_aoclk_saradc_div,
+	[CLKID_AO_SAR_ADC_CLK]	= &axg_aoclk_saradc_gate,
+};
+
+static const struct clk_hw_onecell_data axg_aoclk_onecell_data = {
+	.hws = {
+		[CLKID_AO_REMOTE]	= &axg_aoclk_remote.hw,
+		[CLKID_AO_I2C_MASTER]	= &axg_aoclk_i2c_master.hw,
+		[CLKID_AO_I2C_SLAVE]	= &axg_aoclk_i2c_slave.hw,
+		[CLKID_AO_UART1]	= &axg_aoclk_uart1.hw,
+		[CLKID_AO_UART2]	= &axg_aoclk_uart2.hw,
+		[CLKID_AO_IR_BLASTER]	= &axg_aoclk_ir_blaster.hw,
+		[CLKID_AO_SAR_ADC]	= &axg_aoclk_saradc.hw,
+		[CLKID_AO_CLK81]	= &axg_aoclk_clk81.hw,
+		[CLKID_AO_SAR_ADC_SEL]	= &axg_aoclk_saradc_mux.hw,
+		[CLKID_AO_SAR_ADC_DIV]	= &axg_aoclk_saradc_div.hw,
+		[CLKID_AO_SAR_ADC_CLK]	= &axg_aoclk_saradc_gate.hw,
+	},
+	.num = NR_CLKS,
+};
+
+static const struct meson_aoclk_data axg_aoclkc_data = {
+	.reset_reg	= AO_RTI_GEN_CNTL_REG0,
+	.num_reset	= ARRAY_SIZE(axg_aoclk_reset),
+	.reset		= axg_aoclk_reset,
+	.num_clks	= ARRAY_SIZE(axg_aoclk_regmap),
+	.clks		= axg_aoclk_regmap,
+	.hw_data	= &axg_aoclk_onecell_data,
+};
+
+static const struct of_device_id axg_aoclkc_match_table[] = {
+	{
+		.compatible	= "amlogic,meson-axg-aoclkc",
+		.data		= &axg_aoclkc_data,
+	},
+	{ }
+};
+
+static struct platform_driver axg_aoclkc_driver = {
+	.probe		= meson_aoclkc_probe,
+	.driver		= {
+		.name	= "axg-aoclkc",
+		.of_match_table = axg_aoclkc_match_table,
+	},
+};
+
+builtin_platform_driver(axg_aoclkc_driver);
+
diff --git a/drivers/clk/meson/axg-aoclk.h b/drivers/clk/meson/axg-aoclk.h
new file mode 100644
index 000000000000..1ec338090bc7
--- /dev/null
+++ b/drivers/clk/meson/axg-aoclk.h
@@ -0,0 +1,30 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2017 BayLibre, SAS
+ * Author: Neil Armstrong <narmstrong at baylibre.com>
+ *
+ * Copyright (c) 2018 Amlogic, inc.
+ * Author: Qiufang Dai <qiufang.dai at amlogic.com>
+ */
+
+#ifndef __AXG_AOCLKC_H
+#define __AXG_AOCLKC_H
+
+#define NR_CLKS	11
+/* AO Configuration Clock registers offsets
+ * Register offsets from the data sheet must be multiplied by 4.
+ */
+#define AO_RTI_PWR_CNTL_REG1	0x0C
+#define AO_RTI_PWR_CNTL_REG0	0x10
+#define AO_RTI_GEN_CNTL_REG0	0x40
+#define AO_OSCIN_CNTL		0x58
+#define AO_CRT_CLK_CNTL1	0x68
+#define AO_SAR_CLK		0x90
+#define AO_RTC_ALT_CLK_CNTL0	0x94
+#define AO_RTC_ALT_CLK_CNTL1	0x98
+
+#include <dt-bindings/clock/axg-aoclkc.h>
+#include <dt-bindings/reset/axg-aoclkc.h>
+
+#endif /* __AXG_AOCLKC_H */
+
-- 
2.15.1



From yixun.lan at amlogic.com  Thu Apr 19 06:54:25 2018
From: yixun.lan at amlogic.com (Yixun Lan)
Date: Thu, 19 Apr 2018 21:54:25 +0800
Subject: [PATCH v6 6/7] clk: meson: drop CLK_SET_RATE_PARENT flag
In-Reply-To: <20180419135426.155794-1-yixun.lan@amlogic.com>
References: <20180419135426.155794-1-yixun.lan@amlogic.com>
Message-ID: <20180419135426.155794-7-yixun.lan@amlogic.com>

The clk81 is not expected to be changed, so drop this flag.

Signed-off-by: Yixun Lan <yixun.lan at amlogic.com>
---
 drivers/clk/meson/gxbb-aoclk.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/clk/meson/gxbb-aoclk.c b/drivers/clk/meson/gxbb-aoclk.c
index c785ee7586d1..e145ebcdef38 100644
--- a/drivers/clk/meson/gxbb-aoclk.c
+++ b/drivers/clk/meson/gxbb-aoclk.c
@@ -69,7 +69,7 @@ static struct clk_regmap _name##_ao = {					\
 		.ops = &clk_regmap_gate_ops,				\
 		.parent_names = (const char *[]){ "clk81" },		\
 		.num_parents = 1,					\
-		.flags = (CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED),	\
+		.flags = CLK_IGNORE_UNUSED,				\
 	},								\
 }
 
-- 
2.15.1



From yixun.lan at amlogic.com  Thu Apr 19 06:54:26 2018
From: yixun.lan at amlogic.com (Yixun Lan)
Date: Thu, 19 Apr 2018 21:54:26 +0800
Subject: [PATCH v6 7/7] clk: meson: drop CLK_IGNORE_UNUSED flag
In-Reply-To: <20180419135426.155794-1-yixun.lan@amlogic.com>
References: <20180419135426.155794-1-yixun.lan@amlogic.com>
Message-ID: <20180419135426.155794-8-yixun.lan@amlogic.com>

Rely on drivers to request the clock explicitly.

Previous the kernel will leave the clock on while
bootloader adready initilized the clock, this wasn't
optimal way, so fix it here.

Signed-off-by: Yixun Lan <yixun.lan at amlogic.com>
---
 drivers/clk/meson/axg-aoclk.c  | 1 -
 drivers/clk/meson/gxbb-aoclk.c | 1 -
 2 files changed, 2 deletions(-)

diff --git a/drivers/clk/meson/axg-aoclk.c b/drivers/clk/meson/axg-aoclk.c
index a5d00ef12268..d68b3e8ef483 100644
--- a/drivers/clk/meson/axg-aoclk.c
+++ b/drivers/clk/meson/axg-aoclk.c
@@ -27,7 +27,6 @@ static struct clk_regmap axg_aoclk_##_name = {					\
 		.ops = &clk_regmap_gate_ops,				\
 		.parent_names = (const char *[]){ "clk81" },		\
 		.num_parents = 1,					\
-		.flags = CLK_IGNORE_UNUSED,				\
 	},								\
 }
 
diff --git a/drivers/clk/meson/gxbb-aoclk.c b/drivers/clk/meson/gxbb-aoclk.c
index e145ebcdef38..c4d6027653a3 100644
--- a/drivers/clk/meson/gxbb-aoclk.c
+++ b/drivers/clk/meson/gxbb-aoclk.c
@@ -69,7 +69,6 @@ static struct clk_regmap _name##_ao = {					\
 		.ops = &clk_regmap_gate_ops,				\
 		.parent_names = (const char *[]){ "clk81" },		\
 		.num_parents = 1,					\
-		.flags = CLK_IGNORE_UNUSED,				\
 	},								\
 }
 
-- 
2.15.1



From jbrunet at baylibre.com  Thu Apr 19 07:13:26 2018
From: jbrunet at baylibre.com (Jerome Brunet)
Date: Thu, 19 Apr 2018 16:13:26 +0200
Subject: [PATCH 0/2] nvmem: meson-efuse: add write support
In-Reply-To: <20180316150113.9779-1-jbrunet@baylibre.com>
References: <20180316150113.9779-1-jbrunet@baylibre.com>
Message-ID: <1524147206.2601.104.camel@baylibre.com>

On Fri, 2018-03-16 at 16:01 +0100, Jerome Brunet wrote:
> This changeset adds write support to meson efuse driver.
> The first patch just changes the way the nvmem data are allocated w/o
> any functional changes. The second patches actually adds write support.
> 
> The memory being an OTP, it is safer if it remains read-only by default,
> which is why I also submitted this DT patch [0].
> 
> If a user knows what he is doing, it should be easy to remove the
> read-only property from the board DT. This can be done in u-boot, before
> starting linux:
> 
>  > fdt rm /efuse read-only
> 
> Tested on the gxl libretech-cc

Hi Srinivas,

Is this patchset ok with you ? Do you want to me to change something ?

Regards
Jerome

> 
> [0]: https://lkml.kernel.org/r/20180316145021.8517-1-jbrunet at baylibre.com
> 
> Jerome Brunet (2):
>   nvmem: meson-efuse: remove econfig global
>   nvmem: meson-efuse: add write support
> 
>  drivers/nvmem/meson-efuse.c | 37 +++++++++++++++++++++++++++----------
>  1 file changed, 27 insertions(+), 10 deletions(-)
> 



From srinivas.kandagatla at linaro.org  Thu Apr 19 07:29:24 2018
From: srinivas.kandagatla at linaro.org (Srinivas Kandagatla)
Date: Thu, 19 Apr 2018 15:29:24 +0100
Subject: [PATCH 0/2] nvmem: meson-efuse: add write support
In-Reply-To: <1524147206.2601.104.camel@baylibre.com>
References: <20180316150113.9779-1-jbrunet@baylibre.com>
 <1524147206.2601.104.camel@baylibre.com>
Message-ID: <75866a94-c6e4-6537-b7d1-b5cae0519e61@linaro.org>



On 19/04/18 15:13, Jerome Brunet wrote:
> On Fri, 2018-03-16 at 16:01 +0100, Jerome Brunet wrote:
>> This changeset adds write support to meson efuse driver.
>> The first patch just changes the way the nvmem data are allocated w/o
>> any functional changes. The second patches actually adds write support.
>>
>> The memory being an OTP, it is safer if it remains read-only by default,
>> which is why I also submitted this DT patch [0].
>>
>> If a user knows what he is doing, it should be easy to remove the
>> read-only property from the board DT. This can be done in u-boot, before
>> starting linux:
>>
>>   > fdt rm /efuse read-only
>>
>> Tested on the gxl libretech-cc
> 
> Hi Srinivas,
> 
> Is this patchset ok with you ? Do you want to me to change something ?
> 
Patches look good to me, Can you rebase them on top of 4.17, I will send 
it to Greg once rc4 is out.

thanks,
srini
> Regards
> Jerome
> 
>>
>> [0]: https://lkml.kernel.org/r/20180316145021.8517-1-jbrunet at baylibre.com
>>
>> Jerome Brunet (2):
>>    nvmem: meson-efuse: remove econfig global
>>    nvmem: meson-efuse: add write support
>>
>>   drivers/nvmem/meson-efuse.c | 37 +++++++++++++++++++++++++++----------
>>   1 file changed, 27 insertions(+), 10 deletions(-)
>>
> 


From khilman at baylibre.com  Thu Apr 19 07:48:37 2018
From: khilman at baylibre.com (Kevin Hilman)
Date: Thu, 19 Apr 2018 07:48:37 -0700
Subject: [PATCH v2 0/7] Meson GXL/GXM USB host mode support
In-Reply-To: <5c162f08-e285-c8c3-6021-0071e5ae4a2d@baylibre.com> (Neil
 Armstrong's message of "Wed, 28 Mar 2018 10:18:03 +0200")
References: <20180326211748.16488-1-martin.blumenstingl@googlemail.com>
 <CAFBinCDfjRaMOOXbSx8j1yNpRrovyf+wZBF2=cwyQD7HN2RMHw@mail.gmail.com>
 <5c162f08-e285-c8c3-6021-0071e5ae4a2d@baylibre.com>
Message-ID: <7h7ep35k1m.fsf@baylibre.com>

Neil Armstrong <narmstrong at baylibre.com> writes:

> On 27/03/2018 23:33, Martin Blumenstingl wrote:
>> On Mon, Mar 26, 2018 at 11:17 PM, Martin Blumenstingl
>> <martin.blumenstingl at googlemail.com> wrote:
>>> the goal of this series is to enable USB host mode on Meson GXL and GXM.
>>> there are four dependencies to get this working:
>>> 1. "improvements and fixes for the phy-meson-gxl-usb2 driver" from [0]
>>>    (this is already queued for v4.17 and part of linux-next)
>>> 2. "DWC3 support for Amlogic Meson AXG and GXL SoCs from" [1] (this is
>>>    also queued for v4.17 and part of linux-next)
>>> 3. "initialize (multiple) PHYs for a HCD" from [3] (this is also queued
>>>    for v4.17 and part of linux-next)
>>> 4. "Meson GXL USB3 PHY driver" from [3] (this is also queued for v4.17
>>>    and part of linux-next)
>>> there is a soft dependency on the following series (currently dependency
>>> #3 from above breaks suspend on some TI SoCs, so there's a risk that #3
>>> will get reverted if the following series doesn't fix it):
>>> 5. "fix HCD PHY suspend handling" from [4] (not queued for v4.17 yet)
>> I just re-sent the series for dependency #5 in version 4: [0]
>> version 4 includes a Tested-by and Reviewed-by of the Mediatek and TI
>> USB maintainers. so chances are good that all pre-conditions for this
>> (USB on GXL/GXM devicetree) series will make it into v4.17
>
> Hi,
>
> I think these should go into 4.17 anyway since the DT nodes are conform to all bindings.
>

I've queued these, and will first attempt to get them early in
v4.17-rc.  If that doesn't work, They'll be first in the queue for
v4.18/dt64.

Kevin


From khilman at baylibre.com  Thu Apr 19 10:41:20 2018
From: khilman at baylibre.com (Kevin Hilman)
Date: Thu, 19 Apr 2018 10:41:20 -0700
Subject: [PATCH 0/4] ARM64: dts: meson: hhi syscon and clock controllers
In-Reply-To: <20180315115545.1884-1-jbrunet@baylibre.com> (Jerome Brunet's
 message of "Thu, 15 Mar 2018 12:55:41 +0100")
References: <20180315115545.1884-1-jbrunet@baylibre.com>
Message-ID: <7h1sfb5c1r.fsf@baylibre.com>

Jerome Brunet <jbrunet at baylibre.com> writes:

> The HHI register region provides more than just clocks. Several drivers may
> need to access this region, such as the clock controllers and the display
> driver.
>
> Meson-gx clock controllers has been developed and merged before we knew the
> hhi could be needed elsewhere, which is why it requests the region directly.
> Meson-axg was built following the model of meson-gx.
>
> To fix this situation, the clock controller should be a child of the hhi
> system controllers. The hhi system controller node already exists on meson-gx.
> It needs to be added on the axg.
>
> This changeset depends on [0]. This dependency has been merged in
> clk-next. A topic branch is available here [1]

As the dependencies are now merged for v4.17, applying this to
v4.18/dt64,

Thanks,

Kevin


From khilman at baylibre.com  Thu Apr 19 10:42:40 2018
From: khilman at baylibre.com (Kevin Hilman)
Date: Thu, 19 Apr 2018 10:42:40 -0700
Subject: [PATCH 0/2] nvmem: meson-efuse: add write support
In-Reply-To: <20180316150113.9779-1-jbrunet@baylibre.com> (Jerome Brunet's
 message of "Fri, 16 Mar 2018 16:01:11 +0100")
References: <20180316150113.9779-1-jbrunet@baylibre.com>
Message-ID: <7hwox33xf3.fsf@baylibre.com>

Jerome Brunet <jbrunet at baylibre.com> writes:

> This changeset adds write support to meson efuse driver.
> The first patch just changes the way the nvmem data are allocated w/o
> any functional changes. The second patches actually adds write support.
>
> The memory being an OTP, it is safer if it remains read-only by default,
> which is why I also submitted this DT patch [0].
>
> If a user knows what he is doing, it should be easy to remove the
> read-only property from the board DT. This can be done in u-boot, before
> starting linux:
>
>  > fdt rm /efuse read-only
>
> Tested on the gxl libretech-cc

For the series,

Reviewed-by: Kevin Hilman <khilman at baylibre.com>


From khilman at baylibre.com  Thu Apr 19 10:58:52 2018
From: khilman at baylibre.com (Kevin Hilman)
Date: Thu, 19 Apr 2018 10:58:52 -0700
Subject: [PATCH v2] ARM64: dts: meson-axg: enable the eMMC controller
In-Reply-To: <20180408113647.13543-1-yixun.lan@amlogic.com> (Yixun Lan's
 message of "Sun, 8 Apr 2018 11:36:47 +0000")
References: <20180408113647.13543-1-yixun.lan@amlogic.com>
Message-ID: <7ho9if3wo3.fsf@baylibre.com>

Yixun Lan <yixun.lan at amlogic.com> writes:

> From: Nan Li <nan.li at amlogic.com>
>
> The IP of eMMC controller in AXG is similiar to Meson-GX series.
> Here we add the initial support of the HS200 mode with
> clock running at 166MHz (to be safe), since we found some eMMC chip
> fail to run at 200MHz due to tunning phase error.
>
> Signed-off-by: Nan Li <nan.li at amlogic.com>
> Signed-off-by: Yixun Lan <yixun.lan at amlogic.com>

Applied to v4.18/dt64

> ---
> Hi Kevin
>   Please note this patch actually depend on the eMMC driver here [0].
>   Still a few problem to solve, to improve the tuning phase driver to make
> the clock running at 200MHz, and to further support the HS400 mode.
> Anyway, this patch itself is quite independent.

The driver changes are queued for v4.18 also.  Good!

Kevin


From khilman at baylibre.com  Thu Apr 19 11:01:52 2018
From: khilman at baylibre.com (Kevin Hilman)
Date: Thu, 19 Apr 2018 11:01:52 -0700
Subject: [PATCH] ARM64: dts: meson-axg: add GPIO interrupt controller
 support
In-Reply-To: <20180408151045.1138-1-yixun.lan@amlogic.com> (Yixun Lan's
 message of "Sun, 8 Apr 2018 15:10:45 +0000")
References: <20180408151045.1138-1-yixun.lan@amlogic.com>
Message-ID: <7hh8o73wj3.fsf@baylibre.com>

Yixun Lan <yixun.lan at amlogic.com> writes:

> Add the GPIO interrupt controller driver which found in the Amlogic's
> Meson-AXG SoC, the controller share the similar ASIC IP as other meson SoCs.
>
> Signed-off-by: Yixun Lan <yixun.lan at amlogic.com>

Applied to v4.18/dt64,

> ---
> Hi Kevin
>  Please note this patch depend on the GPIO interrupt driver here[0]

Thanks for noting the dependencies.

Kevin

> [0] http://lkml.kernel.org/r/20180408145700.23520-1-yixun.lan at amlogic.com
> ---
>  arch/arm64/boot/dts/amlogic/meson-axg.dtsi | 9 +++++++++
>  1 file changed, 9 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
> index b58808eb3cc8..c1105065de99 100644
> --- a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
> +++ b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
> @@ -120,6 +120,15 @@
>  			#size-cells = <2>;
>  			ranges = <0x0 0x0 0x0 0xffd00000 0x0 0x25000>;
>  
> +			gpio_intc: interrupt-controller at f080 {
> +				compatible = "amlogic,meson-gpio-intc";
> +				reg = <0x0 0xf080 0x0 0x10>;
> +				interrupt-controller;
> +				#interrupt-cells = <2>;
> +				amlogic,channel-interrupts = <64 65 66 67 68 69 70 71>;
> +				status = "disabled";
> +			};
> +
>  			pwm_ab: pwm at 1b000 {
>  				compatible = "amlogic,meson-axg-ee-pwm";
>  				reg = <0x0 0x1b000 0x0 0x20>;


From khilman at baylibre.com  Thu Apr 19 11:07:32 2018
From: khilman at baylibre.com (Kevin Hilman)
Date: Thu, 19 Apr 2018 11:07:32 -0700
Subject: [PATCH] pinctrl: meson-axg: fix the range of aobus bank
In-Reply-To: <20180417170824.18670-1-yixun.lan@amlogic.com> (Yixun Lan's
 message of "Tue, 17 Apr 2018 17:08:24 +0000")
References: <20180417170824.18670-1-yixun.lan@amlogic.com>
Message-ID: <7hd0yv3w9n.fsf@baylibre.com>

Yixun Lan <yixun.lan at amlogic.com> writes:

> The GPIOAO bank is range from GPIOAO_0 to GPIOAO_13.
>
> Fixes: 83c566806a68 ("pinctrl: meson-axg: Add new pinctrl driver for Meson AXG SoC")
> Reported-by: Xingyu Chen <xingyu.chen at amlogic.com>
> Signed-off-by: Yixun Lan <yixun.lan at amlogic.com>

Acked-by: Kevin Hilman <khilman at baylibre.com>

> ---
>  drivers/pinctrl/meson/pinctrl-meson-axg.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/pinctrl/meson/pinctrl-meson-axg.c b/drivers/pinctrl/meson/pinctrl-meson-axg.c
> index 4b91ff74779b..99a6ceac8e53 100644
> --- a/drivers/pinctrl/meson/pinctrl-meson-axg.c
> +++ b/drivers/pinctrl/meson/pinctrl-meson-axg.c
> @@ -898,7 +898,7 @@ static struct meson_bank meson_axg_periphs_banks[] = {
>  
>  static struct meson_bank meson_axg_aobus_banks[] = {
>  	/*   name    first      last      irq	pullen  pull    dir     out     in  */
> -	BANK("AO",   GPIOAO_0,  GPIOAO_9, 0, 13, 0,  16,  0, 0,  0,  0,  0, 16,  1,  0),
> +	BANK("AO",   GPIOAO_0,  GPIOAO_13, 0, 13, 0,  16,  0, 0,  0,  0,  0, 16,  1,  0),
>  };
>  
>  static struct meson_pmx_bank meson_axg_periphs_pmx_banks[] = {


From hias at horus.com  Thu Apr 19 15:17:23 2018
From: hias at horus.com (Matthias Reichl)
Date: Fri, 20 Apr 2018 00:17:23 +0200
Subject: [PATCH v2 7/7] media: rc: mceusb: allow the timeout to be
 configurable
In-Reply-To: <20180418174229.jurjnyqbtkyctjvb@camel2.lan>
References: <cover.1523221902.git.sean@mess.org>
 <02b5dac3b27169c6e6a4a070a2569b33fef47bbe.1523221902.git.sean@mess.org>
 <20180417191457.fhgsdega2kjqw3t2@camel2.lan>
 <20180418112428.zk3lmdxoqv46weph@gofer.mess.org>
 <20180418174229.jurjnyqbtkyctjvb@camel2.lan>
Message-ID: <20180419221723.s6kx7nip6ue2d43o@camel2.lan>

Hi Sean,

On Wed, Apr 18, 2018 at 07:42:29PM +0200, Matthias Reichl wrote:
> Hi Sean,
> 
> On Wed, Apr 18, 2018 at 12:24:29PM +0100, Sean Young wrote:
> > Hello Hias,
> > 
> > On Tue, Apr 17, 2018 at 09:14:57PM +0200, Matthias Reichl wrote:
> > > On Sun, Apr 08, 2018 at 10:19:42PM +0100, Sean Young wrote:
> > > > mceusb devices have a default timeout of 100ms, but this can be changed.
> > > 
> > > We finally added a backport of the v2 series (and also the mce_kbd
> > > series) to LibreELEC yesterday and ratcher quickly received 2 bugreports
> > > from users using mceusb receivers.
> > > 
> > > Local testing on RPi/gpio-ir and Intel NUC/ite-cir was fine, I've
> > > been using the v2 series for over a week without issues on
> > > LibreELEC (RPi with kernel 4.14).
> > > 
> > > Here are the links to the bugreports and logs:
> > > https://forum.kodi.tv/showthread.php?tid=298461&pid=2726684#pid2726684
> > > https://forum.kodi.tv/showthread.php?tid=298462&pid=2726690#pid2726690
> > > 
> > > Both users are using similar mceusb receivers:
> > > 
> > > Log 1:
> > > [    6.418218] rc rc0: Media Center Ed. eHome Infrared Remote Transceiver (147a:e017) as /devices/platform/soc/3f980000.usb/usb1/1-1/1-1.3/1-1.3:1.0/rc/rc0
> > > [    6.418358] input: Media Center Ed. eHome Infrared Remote Transceiver (147a:e017) as /devices/platform/soc/3f980000.usb/usb1/1-1/1-1.3/1-1.3:1.0/rc/rc0/input0
> > > [    6.419443] rc rc0: lirc_dev: driver ir-lirc-codec (mceusb) registered at minor = 0
> > > [    6.608114] mceusb 1-1.3:1.0: Registered Formosa21 SnowflakeEmulation with mce emulator interface version 1
> > > [    6.608125] mceusb 1-1.3:1.0: 0 tx ports (0x0 cabled) and 1 rx sensors (0x1 active)
> > > 
> > > Log 2:
> > > [    3.023361] rc rc0: Media Center Ed. eHome Infrared Remote Transceiver (147a:e03e) as /devices/pci0000:00/0000:00:14.0/usb1/1-10/1-10:1.0/rc/rc0
> > > [    3.023393] input: Media Center Ed. eHome Infrared Remote Transceiver (147a:e03e) as /devices/pci0000:00/0000:00:14.0/usb1/1-10/1-10:1.0/rc/rc0/input11
> > > [    3.023868] rc rc0: lirc_dev: driver ir-lirc-codec (mceusb) registered at minor = 0
> > > [    3.119384] input: eventlircd as /devices/virtual/input/input21
> > > [    3.138625] ip6_tables: (C) 2000-2006 Netfilter Core Team
> > > [    3.196830] mceusb 1-10:1.0: Registered Formosa21 eHome Infrared Transceiver with mce emulator interface version 2
> > > [    3.196836] mceusb 1-10:1.0: 0 tx ports (0x0 cabled) and 1 rx sensors (0x1 active)
> > > 
> > > In both cases ir-keytable doesn't report any scancodes and the
> > > ir-ctl -r output contains very odd long space values where I'd expect
> > > a short timeout instead:
> > > 
> > > gap between messages:
> > > space 800
> > > pulse 450
> > > space 16777215
> > > space 25400
> > > pulse 2650
> > > space 800
> > > 
> > > end of last message:
> > > space 800
> > > pulse 450
> > > space 16777215
> > > timeout 31750
> > > 
> > > This patch applied cleanly on 4.14 and the mceusb history from
> > > 4.14 to media/master looked rather unsuspicious. I'm not 100% sure
> > > if I might have missed a dependency when backporting the patch
> > > or if this is indeed an issue of this patch on these particular
> > > (or maybe some more) mceusb receivers.
> > 
> > Thanks again for a great bug report and analysis! So, it seems with the
> > shorter timeout, some mceusb devices add a specific "timeout" code to
> > the IR data stream (0x80) rather than a space. The current mceusb code
> > resets the decoders in this case, causing the IR decoders to reset and
> > lirc to report a space of 0xffffff.
> > 
> > Turns out that one of my mceusb devices also suffers from this, I don't
> > know how I missed this. Anyway hopefully this will solve the problem.
> 
> Thanks a lot for the quick fix!
> 
> I can't test myself as I don't have the hardware, but we will
> include the patch in tonight's LibreELEC build and I asked the
> users to test it. I'll keep you posted about the outcome.

One of the affected users reported back that the fix worked fine!

I'm keeping an eye on further reports but so far I'd say everything's
working really well.

Great job and thanks a lot for the improvements!

so long,

Hias

> 
> so long,
> 
> Hias
> 
> > 
> > 
> > Thanks
> > 
> > Sean
> > 
> > >>From 92d27b206e51993e927dc0b3aba210a621eef3d0 Mon Sep 17 00:00:00 2001
> > From: Sean Young <sean at mess.org>
> > Date: Wed, 18 Apr 2018 10:36:25 +0100
> > Subject: [PATCH] media: rc: mceusb: IR of length 0 means IR timeout, not reset
> > 
> > The last usb packet with IR data will end with 0x80 (MCE_IRDATA_TRAILER).
> > If we reset the decoder state at this point, IR decoding can fail.
> > 
> > Signed-off-by: Sean Young <sean at mess.org>
> > ---
> >  drivers/media/rc/mceusb.c | 7 ++++++-
> >  1 file changed, 6 insertions(+), 1 deletion(-)
> > 
> > diff --git a/drivers/media/rc/mceusb.c b/drivers/media/rc/mceusb.c
> > index c97cb2eb1c5f..5c0bf61fae26 100644
> > --- a/drivers/media/rc/mceusb.c
> > +++ b/drivers/media/rc/mceusb.c
> > @@ -1201,7 +1201,12 @@ static void mceusb_process_ir_data(struct mceusb_dev *ir, int buf_len)
> >  			if (ir->rem) {
> >  				ir->parser_state = PARSE_IRDATA;
> >  			} else {
> > -				ir_raw_event_reset(ir->rc);
> > +				init_ir_raw_event(&rawir);
> > +				rawir.timeout = 1;
> > +				rawir.duration = ir->rc->timeout;
> > +				if (ir_raw_event_store_with_filter(ir->rc,
> > +								   &rawir))
> > +					event = true;
> >  				ir->pulse_tunit = 0;
> >  				ir->pulse_count = 0;
> >  			}
> > -- 
> > 2.14.3
> > 


From ulf.hansson at linaro.org  Thu Apr 19 23:55:47 2018
From: ulf.hansson at linaro.org (Ulf Hansson)
Date: Fri, 20 Apr 2018 08:55:47 +0200
Subject: [PATCH v2] ARM64: dts: meson-axg: enable the eMMC controller
In-Reply-To: <7ho9if3wo3.fsf@baylibre.com>
References: <20180408113647.13543-1-yixun.lan@amlogic.com>
 <7ho9if3wo3.fsf@baylibre.com>
Message-ID: <CAPDyKFpcmO7LYuyuNPcYmzeDyq_AXDH5W4Y9dByTL-B+DGZSqg@mail.gmail.com>

On 19 April 2018 at 19:58, Kevin Hilman <khilman at baylibre.com> wrote:
> Yixun Lan <yixun.lan at amlogic.com> writes:
>
>> From: Nan Li <nan.li at amlogic.com>
>>
>> The IP of eMMC controller in AXG is similiar to Meson-GX series.
>> Here we add the initial support of the HS200 mode with
>> clock running at 166MHz (to be safe), since we found some eMMC chip
>> fail to run at 200MHz due to tunning phase error.
>>
>> Signed-off-by: Nan Li <nan.li at amlogic.com>
>> Signed-off-by: Yixun Lan <yixun.lan at amlogic.com>
>
> Applied to v4.18/dt64
>
>> ---
>> Hi Kevin
>>   Please note this patch actually depend on the eMMC driver here [0].
>>   Still a few problem to solve, to improve the tuning phase driver to make
>> the clock running at 200MHz, and to further support the HS400 mode.
>> Anyway, this patch itself is quite independent.
>
> The driver changes are queued for v4.18 also.  Good!

Right, may I consider that as an ack? :-)

Kind regards
Uffe

>
> Kevin
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel


From jbrunet at baylibre.com  Fri Apr 20 02:56:01 2018
From: jbrunet at baylibre.com (Jerome Brunet)
Date: Fri, 20 Apr 2018 11:56:01 +0200
Subject: [PATCH 0/2] clk: meson: mpll: add round closest support
Message-ID: <20180420095603.29964-1-jbrunet@baylibre.com>

ATM, the mpll driver can only round the requested rate down, even if
rounding up would have provided a better approximation of the requested
rate.

This patchset adds a flag to enable rounding to the closest rate possible,
even if it means rounding up.

The flag is then enabled on the axg platform to improve the rates provided
to the audio subsystem.

Jerome Brunet (2):
  clk: meson: mpll: add round closest support
  clk: meson: axg: let mpll clocks round closest

 drivers/clk/meson/axg.c      |  4 ++++
 drivers/clk/meson/clk-mpll.c | 25 ++++++++++++++++++++-----
 drivers/clk/meson/clkc.h     |  3 +++
 3 files changed, 27 insertions(+), 5 deletions(-)

-- 
2.14.3



From jbrunet at baylibre.com  Fri Apr 20 02:56:02 2018
From: jbrunet at baylibre.com (Jerome Brunet)
Date: Fri, 20 Apr 2018 11:56:02 +0200
Subject: [PATCH 1/2] clk: meson: mpll: add round closest support
In-Reply-To: <20180420095603.29964-1-jbrunet@baylibre.com>
References: <20180420095603.29964-1-jbrunet@baylibre.com>
Message-ID: <20180420095603.29964-2-jbrunet@baylibre.com>

Allow the mpll driver to round the requested rate up if
CLK_MESON_MPLL_ROUND_CLOSEST is set and it provides a rate closer to the
requested rate.

Signed-off-by: Jerome Brunet <jbrunet at baylibre.com>
---
 drivers/clk/meson/clk-mpll.c | 25 ++++++++++++++++++++-----
 drivers/clk/meson/clkc.h     |  3 +++
 2 files changed, 23 insertions(+), 5 deletions(-)

diff --git a/drivers/clk/meson/clk-mpll.c b/drivers/clk/meson/clk-mpll.c
index 0df1227b65b3..4e5283eb892a 100644
--- a/drivers/clk/meson/clk-mpll.c
+++ b/drivers/clk/meson/clk-mpll.c
@@ -89,10 +89,23 @@ static long rate_from_params(unsigned long parent_rate,
 static void params_from_rate(unsigned long requested_rate,
 			     unsigned long parent_rate,
 			     unsigned int *sdm,
-			     unsigned int *n2)
+			     unsigned int *n2,
+			     u8 flags)
 {
 	uint64_t div = parent_rate;
-	unsigned long rem = do_div(div, requested_rate);
+	uint64_t frac = do_div(div, requested_rate);
+	unsigned long rem;
+
+	frac *= SDM_DEN;
+	rem = do_div(frac, requested_rate);
+
+	/* Should we round up ? */
+	if (flags & CLK_MESON_MPLL_ROUND_CLOSEST
+	    && rem > (requested_rate / 2)) {
+		frac = (frac + 1) % SDM_DEN;
+		if (frac == 0)
+			div += 1;
+	}
 
 	if (div < N2_MIN) {
 		*n2 = N2_MIN;
@@ -102,7 +115,7 @@ static void params_from_rate(unsigned long requested_rate,
 		*sdm = SDM_DEN - 1;
 	} else {
 		*n2 = div;
-		*sdm = DIV_ROUND_UP_ULL((u64)rem * SDM_DEN, requested_rate);
+		*sdm = frac;
 	}
 }
 
@@ -125,9 +138,11 @@ static long mpll_round_rate(struct clk_hw *hw,
 			    unsigned long rate,
 			    unsigned long *parent_rate)
 {
+	struct clk_regmap *clk = to_clk_regmap(hw);
+	struct meson_clk_mpll_data *mpll = meson_clk_mpll_data(clk);
 	unsigned int sdm, n2;
 
-	params_from_rate(rate, *parent_rate, &sdm, &n2);
+	params_from_rate(rate, *parent_rate, &sdm, &n2, mpll->flags);
 	return rate_from_params(*parent_rate, sdm, n2);
 }
 
@@ -140,7 +155,7 @@ static int mpll_set_rate(struct clk_hw *hw,
 	unsigned int sdm, n2;
 	unsigned long flags = 0;
 
-	params_from_rate(rate, parent_rate, &sdm, &n2);
+	params_from_rate(rate, parent_rate, &sdm, &n2, mpll->flags);
 
 	if (mpll->lock)
 		spin_lock_irqsave(mpll->lock, flags);
diff --git a/drivers/clk/meson/clkc.h b/drivers/clk/meson/clkc.h
index 8fe73c4edca8..8cc265cd3d2b 100644
--- a/drivers/clk/meson/clkc.h
+++ b/drivers/clk/meson/clkc.h
@@ -97,8 +97,11 @@ struct meson_clk_mpll_data {
 	struct parm ssen;
 	struct parm misc;
 	spinlock_t *lock;
+	u8 flags;
 };
 
+#define CLK_MESON_MPLL_ROUND_CLOSEST	BIT(0)
+
 struct meson_clk_audio_div_data {
 	struct parm div;
 	u8 flags;
-- 
2.14.3



From jbrunet at baylibre.com  Fri Apr 20 02:56:03 2018
From: jbrunet at baylibre.com (Jerome Brunet)
Date: Fri, 20 Apr 2018 11:56:03 +0200
Subject: [PATCH 2/2] clk: meson: axg: let mpll clocks round closest
In-Reply-To: <20180420095603.29964-1-jbrunet@baylibre.com>
References: <20180420095603.29964-1-jbrunet@baylibre.com>
Message-ID: <20180420095603.29964-3-jbrunet@baylibre.com>

Let the mpll dividers achieve the closest rate possible, even if
it means rounding the requested rate up.

This is done to improve the accuracy of the rates provided by these
plls to the audio subsystem

Signed-off-by: Jerome Brunet <jbrunet at baylibre.com>
---
 drivers/clk/meson/axg.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/drivers/clk/meson/axg.c b/drivers/clk/meson/axg.c
index 5f5d468c1efe..bd4dbc696b88 100644
--- a/drivers/clk/meson/axg.c
+++ b/drivers/clk/meson/axg.c
@@ -461,6 +461,7 @@ static struct clk_regmap axg_mpll0_div = {
 			.width	 = 1,
 		},
 		.lock = &meson_clk_lock,
+		.flags = CLK_MESON_MPLL_ROUND_CLOSEST,
 	},
 	.hw.init = &(struct clk_init_data){
 		.name = "mpll0_div",
@@ -507,6 +508,7 @@ static struct clk_regmap axg_mpll1_div = {
 			.width	 = 1,
 		},
 		.lock = &meson_clk_lock,
+		.flags = CLK_MESON_MPLL_ROUND_CLOSEST,
 	},
 	.hw.init = &(struct clk_init_data){
 		.name = "mpll1_div",
@@ -553,6 +555,7 @@ static struct clk_regmap axg_mpll2_div = {
 			.width	 = 1,
 		},
 		.lock = &meson_clk_lock,
+		.flags = CLK_MESON_MPLL_ROUND_CLOSEST,
 	},
 	.hw.init = &(struct clk_init_data){
 		.name = "mpll2_div",
@@ -599,6 +602,7 @@ static struct clk_regmap axg_mpll3_div = {
 			.width	 = 1,
 		},
 		.lock = &meson_clk_lock,
+		.flags = CLK_MESON_MPLL_ROUND_CLOSEST,
 	},
 	.hw.init = &(struct clk_init_data){
 		.name = "mpll3_div",
-- 
2.14.3



From narmstrong at baylibre.com  Sat Apr 21 05:50:06 2018
From: narmstrong at baylibre.com (Neil Armstrong)
Date: Sat, 21 Apr 2018 14:50:06 +0200
Subject: [PATCH] clk: meson: add the video decoder clocks
In-Reply-To: <CAHStOZ7m+8xSX=k5k-LwmgZy6Ja4MFwsVjMy-FeoG=2c0rpm2g@mail.gmail.com>
References: <CAHStOZ7m+8xSX=k5k-LwmgZy6Ja4MFwsVjMy-FeoG=2c0rpm2g@mail.gmail.com>
Message-ID: <928202bc-0dea-5eb4-264b-7774b5a31de1@baylibre.com>

Hi Maxime,

On 21/04/2018 10:18, Maxime Jourdan wrote:
> In preparation for the V4L2 M2M driver, add the clocks for
> VDEC_1 and VDEC_HEVC to gxbb.
> 
> Signed-off-by: Maxime Jourdan <maxi.jourdan at wanadoo.fr <mailto:maxi.jourdan at wanadoo.fr>>

Send it in text-only, HTML is forbidden ! It breaks all the formatting and other stuff.

Use git- send-email for that, or other tools like patman or git-series.

Next time also CC linux-kernel at vger.kernel.org and linux-arm-kernel at lists.infradead.org !

> ---
> ?drivers/clk/meson/gxbb.c? ? ? ? ? ? ? | 112 ++++++++++++++++++++++++++
> ?drivers/clk/meson/gxbb.h? ? ? ? ? ? ? |? ?4 +-
> ?include/dt-bindings/clock/gxbb-clkc.h |? ?4 +
> ?3 files changed, 119 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/clk/meson/gxbb.c b/drivers/clk/meson/gxbb.c
> index b1e4d9557610..f9d7ab9c924e 100644
> --- a/drivers/clk/meson/gxbb.c
> +++ b/drivers/clk/meson/gxbb.c
> @@ -1543,6 +1543,100 @@ static struct clk_regmap gxbb_vapb = {
> ?},
> ?};
> ?
> +/* VDEC clocks */
> +
> +static const char * const gxbb_vdec_parent_names[] = {
> +"fclk_div4", "fclk_div3", "fclk_div5", "fclk_div7"
> +};
> +
> +static struct clk_regmap gxbb_vdec_1_sel = {
> +.data = &(struct clk_regmap_mux_data){
> +.offset = HHI_VDEC_CLK_CNTL,
> +.mask = 0x3,
> +.shift = 9,
> +},
> +.hw.init = &(struct clk_init_data){
> +.name = "vdec_1_sel",
> +.ops = &clk_regmap_mux_ops,
> +.parent_names = gxbb_vdec_parent_names,
> +.num_parents = ARRAY_SIZE(gxbb_vdec_parent_names),
> +.flags = CLK_SET_RATE_NO_REPARENT,
> +},
> +};
> +
> +static struct clk_regmap gxbb_vdec_1_div = {
> +.data = &(struct clk_regmap_div_data){
> +.offset = HHI_VDEC_CLK_CNTL,
> +.shift = 0,
> +.width = 7,
> +},
> +.hw.init = &(struct clk_init_data){
> +.name = "vdec_1_div",
> +.ops = &clk_regmap_divider_ops,
> +.parent_names = (const char *[]){ "vdec_1_sel" },
> +.num_parents = 1,
> +.flags = CLK_SET_RATE_PARENT,
> +},
> +};
> +
> +static struct clk_regmap gxbb_vdec_1 = {
> +.data = &(struct clk_regmap_gate_data){
> +.offset = HHI_VDEC_CLK_CNTL,
> +.bit_idx = 8,
> +},
> +.hw.init = &(struct clk_init_data) {
> +.name = "vdec_1",
> +.ops = &clk_regmap_gate_ops,
> +.parent_names = (const char *[]){ "vdec_1_div" },
> +.num_parents = 1,
> +.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
> +},
> +};
> +
> +static struct clk_regmap gxbb_vdec_hevc_sel = {
> +.data = &(struct clk_regmap_mux_data){
> +.offset = HHI_VDEC2_CLK_CNTL,
> +.mask = 0x3,
> +.shift = 25,
> +},
> +.hw.init = &(struct clk_init_data){
> +.name = "vdec_hevc_sel",
> +.ops = &clk_regmap_mux_ops,
> +.parent_names = gxbb_vdec_parent_names,
> +.num_parents = ARRAY_SIZE(gxbb_vdec_parent_names),
> +.flags = CLK_SET_RATE_NO_REPARENT,
> +},
> +};
> +
> +static struct clk_regmap gxbb_vdec_hevc_div = {
> +.data = &(struct clk_regmap_div_data){
> +.offset = HHI_VDEC2_CLK_CNTL,
> +.shift = 16,
> +.width = 7,
> +},
> +.hw.init = &(struct clk_init_data){
> +.name = "vdec_hevc_div",
> +.ops = &clk_regmap_divider_ops,
> +.parent_names = (const char *[]){ "vdec_hevc_sel" },
> +.num_parents = 1,
> +.flags = CLK_SET_RATE_PARENT,
> +},
> +};
> +
> +static struct clk_regmap gxbb_vdec_hevc = {
> +.data = &(struct clk_regmap_gate_data){
> +.offset = HHI_VDEC2_CLK_CNTL,
> +.bit_idx = 24,
> +},
> +.hw.init = &(struct clk_init_data) {
> +.name = "vdec_hevc",
> +.ops = &clk_regmap_gate_ops,
> +.parent_names = (const char *[]){ "vdec_hevc_div" },
> +.num_parents = 1,
> +.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
> +},
> +};
> +
> ?/* Everything Else (EE) domain gates */
> ?static MESON_GATE(gxbb_ddr, HHI_GCLK_MPEG0, 0);
> ?static MESON_GATE(gxbb_dos, HHI_GCLK_MPEG0, 1);
> @@ -1786,6 +1880,12 @@ static struct clk_hw_onecell_data gxbb_hw_onecell_data = {
> ?[CLKID_FCLK_DIV4_DIV]? ? = &gxbb_fclk_div4_div.hw,
> ?[CLKID_FCLK_DIV5_DIV]? ? = &gxbb_fclk_div5_div.hw,
> ?[CLKID_FCLK_DIV7_DIV]? ? = &gxbb_fclk_div7_div.hw,
> +[CLKID_VDEC_1_SEL]? ? = &gxbb_vdec_1_sel.hw,
> +[CLKID_VDEC_1_DIV]? ? = &gxbb_vdec_1_div.hw,
> +[CLKID_VDEC_1]? ? = &gxbb_vdec_1.hw,
> +[CLKID_VDEC_HEVC_SEL]? ? = &gxbb_vdec_hevc_sel.hw,
> +[CLKID_VDEC_HEVC_DIV]? ? = &gxbb_vdec_hevc_div.hw,
> +[CLKID_VDEC_HEVC]? ? = &gxbb_vdec_hevc.hw,
> ?[NR_CLKS]? ? = NULL,
> ?},
> ?.num = NR_CLKS,
> @@ -1942,6 +2042,12 @@ static struct clk_hw_onecell_data gxl_hw_onecell_data = {
> ?[CLKID_FCLK_DIV4_DIV]? ? = &gxbb_fclk_div4_div.hw,
> ?[CLKID_FCLK_DIV5_DIV]? ? = &gxbb_fclk_div5_div.hw,
> ?[CLKID_FCLK_DIV7_DIV]? ? = &gxbb_fclk_div7_div.hw,
> +[CLKID_VDEC_1_SEL]? ? = &gxbb_vdec_1_sel.hw,
> +[CLKID_VDEC_1_DIV]? ? = &gxbb_vdec_1_div.hw,
> +[CLKID_VDEC_1]? ? = &gxbb_vdec_1.hw,
> +[CLKID_VDEC_HEVC_SEL]? ? = &gxbb_vdec_hevc_sel.hw,
> +[CLKID_VDEC_HEVC_DIV]? ? = &gxbb_vdec_hevc_div.hw,
> +[CLKID_VDEC_HEVC]? ? = &gxbb_vdec_hevc.hw,
> ?[NR_CLKS]? ? = NULL,
> ?},
> ?.num = NR_CLKS,
> @@ -2100,6 +2206,12 @@ static struct clk_regmap *const gx_clk_regmaps[] = {
> ?&gxbb_fclk_div4,
> ?&gxbb_fclk_div5,
> ?&gxbb_fclk_div7,
> +&gxbb_vdec_1_sel,
> +&gxbb_vdec_1_div,
> +&gxbb_vdec_1,
> +&gxbb_vdec_hevc_sel,
> +&gxbb_vdec_hevc_div,
> +&gxbb_vdec_hevc,
> ?};
> ?
> ?struct clkc_data {
> diff --git a/drivers/clk/meson/gxbb.h b/drivers/clk/meson/gxbb.h
> index 9febf3f03739..ae21d235355a 100644
> --- a/drivers/clk/meson/gxbb.h
> +++ b/drivers/clk/meson/gxbb.h
> @@ -204,8 +204,10 @@
> ?#define CLKID_FCLK_DIV4_DIV? 148
> ?#define CLKID_FCLK_DIV5_DIV? 149
> ?#define CLKID_FCLK_DIV7_DIV? 150
> +#define CLKID_VDEC_1_DIV? 152
> +#define CLKID_VDEC_HEVC_DIV? 155
> ?
> -#define NR_CLKS? 151
> +#define NR_CLKS? 157
> ?
> ?/* include the CLKIDs that have been made part of the DT binding */
> ?#include <dt-bindings/clock/gxbb-clkc.h>
> diff --git a/include/dt-bindings/clock/gxbb-clkc.h b/include/dt-bindings/clock/gxbb-clkc.h
> index 8ba99a5e3fd3..ae7f6be747e4 100644
> --- a/include/dt-bindings/clock/gxbb-clkc.h
> +++ b/include/dt-bindings/clock/gxbb-clkc.h
> @@ -125,5 +125,9 @@
> ?#define CLKID_VAPB_1138
> ?#define CLKID_VAPB_SEL139
> ?#define CLKID_VAPB140
> +#define CLKID_VDEC_1_SEL151
> +#define CLKID_VDEC_1153
> +#define CLKID_VDEC_HEVC_SEL154
> +#define CLKID_VDEC_HEVC156
> ?
> ?#endif /* __GXBB_CLKC_H */
> --?
> 2.17.0
> 
> 

Otherwise, looks good for me !

Simply resend with "[PATCH RESEND]" in the subject so I can apply it to the clk-meson tree.

Neil


From hias at horus.com  Sat Apr 21 06:18:52 2018
From: hias at horus.com (Matthias Reichl)
Date: Sat, 21 Apr 2018 15:18:52 +0200
Subject: [PATCH v2 7/7] media: rc: mceusb: allow the timeout to be
 configurable
In-Reply-To: <20180419221723.s6kx7nip6ue2d43o@camel2.lan>
References: <cover.1523221902.git.sean@mess.org>
 <02b5dac3b27169c6e6a4a070a2569b33fef47bbe.1523221902.git.sean@mess.org>
 <20180417191457.fhgsdega2kjqw3t2@camel2.lan>
 <20180418112428.zk3lmdxoqv46weph@gofer.mess.org>
 <20180418174229.jurjnyqbtkyctjvb@camel2.lan>
 <20180419221723.s6kx7nip6ue2d43o@camel2.lan>
Message-ID: <20180421131852.2zrn7qp3ir4kyqvf@camel2.lan>

Hi Sean,

On Fri, Apr 20, 2018 at 12:17:23AM +0200, Matthias Reichl wrote:
> One of the affected users reported back that the fix worked fine!
> 
> I'm keeping an eye on further reports but so far I'd say everything's
> working really well.

Another bug report came in, button press results in multiple
key down/up events
https://forum.kodi.tv/showthread.php?tid=298461&pid=2727837#pid2727837
(and following posts).

ir-ctl -r output looks fine to me, but ir-keytable -t output suggests
we'll need a margin between raw timeout and key up timeout:

https://pastebin.com/6RTSGXvp
2199.824106: event type EV_MSC(0x04): scancode = 0x800f0419
2199.824106: event type EV_KEY(0x01) key_down: KEY_STOP(0x0080)
2199.824106: event type EV_SYN(0x00).
2199.887081: event type EV_KEY(0x01) key_up: KEY_STOP(0x0080)
2199.887081: event type EV_MSC(0x04): scancode = 0x800f0422
2199.887081: event type EV_KEY(0x01) key_down: KEY_OK(0x0160)
2199.887081: event type EV_SYN(0x00).
2200.029804: event type EV_KEY(0x01) key_up: KEY_OK(0x0160)
2200.029804: event type EV_SYN(0x00).

so long,

Hias


From hias at horus.com  Sat Apr 21 10:41:21 2018
From: hias at horus.com (Matthias Reichl)
Date: Sat, 21 Apr 2018 19:41:21 +0200
Subject: [PATCH v2 7/7] media: rc: mceusb: allow the timeout to be
 configurable
In-Reply-To: <20180421131852.2zrn7qp3ir4kyqvf@camel2.lan>
References: <cover.1523221902.git.sean@mess.org>
 <02b5dac3b27169c6e6a4a070a2569b33fef47bbe.1523221902.git.sean@mess.org>
 <20180417191457.fhgsdega2kjqw3t2@camel2.lan>
 <20180418112428.zk3lmdxoqv46weph@gofer.mess.org>
 <20180418174229.jurjnyqbtkyctjvb@camel2.lan>
 <20180419221723.s6kx7nip6ue2d43o@camel2.lan>
 <20180421131852.2zrn7qp3ir4kyqvf@camel2.lan>
Message-ID: <20180421174121.xcztgoaw2pspj3zv@camel2.lan>

On Sat, Apr 21, 2018 at 03:18:52PM +0200, Matthias Reichl wrote:
> Hi Sean,
> 
> On Fri, Apr 20, 2018 at 12:17:23AM +0200, Matthias Reichl wrote:
> > One of the affected users reported back that the fix worked fine!
> > 
> > I'm keeping an eye on further reports but so far I'd say everything's
> > working really well.
> 
> Another bug report came in, button press results in multiple
> key down/up events
> https://forum.kodi.tv/showthread.php?tid=298461&pid=2727837#pid2727837
> (and following posts).
> 
> ir-ctl -r output looks fine to me, but ir-keytable -t output suggests
> we'll need a margin between raw timeout and key up timeout:
> 
> https://pastebin.com/6RTSGXvp
> 2199.824106: event type EV_MSC(0x04): scancode = 0x800f0419
> 2199.824106: event type EV_KEY(0x01) key_down: KEY_STOP(0x0080)
> 2199.824106: event type EV_SYN(0x00).
> 2199.887081: event type EV_KEY(0x01) key_up: KEY_STOP(0x0080)
> 2199.887081: event type EV_MSC(0x04): scancode = 0x800f0422
> 2199.887081: event type EV_KEY(0x01) key_down: KEY_OK(0x0160)
> 2199.887081: event type EV_SYN(0x00).
> 2200.029804: event type EV_KEY(0x01) key_up: KEY_OK(0x0160)
> 2200.029804: event type EV_SYN(0x00).

Sorry, just noticed I snipped off the interesting part, here
is the rest:

2200.036070: event type EV_MSC(0x04): scancode = 0x800f0422
2200.036070: event type EV_KEY(0x01) key_down: KEY_OK(0x0160)
2200.036070: event type EV_SYN(0x00).
2200.143067: event type EV_MSC(0x04): scancode = 0x800f0422
2200.143067: event type EV_SYN(0x00).
2200.206061: event type EV_MSC(0x04): scancode = 0x800f0422
2200.206061: event type EV_SYN(0x00).
2200.346472: event type EV_KEY(0x01) key_up: KEY_OK(0x0160)
2200.346472: event type EV_SYN(0x00).

I looked at the log again, and now it doesn't make much sense
to me.

I'm not exactly sure what happened with the first KEY_OK
scancode, that seems to have been decoded ~60ms after the
KEY_STOP scancode (.887 vs .824).

The second KEY_OK scancode was decoded ~ 150ms after the first,
(and caused the problem), delay to third is 107ms, to fourth 63ms.

I'll ask the user to change batteries on the remote and check
if the reception is OK, could be that this was a false alarm.

Adding some margin (maybe 20-50ms) for keyup could still make
sense though, as currently we have basically just the timeout
as margin, which can be quite low and round to 1-2 jiffies.

so long,

Hias


From jbrunet at baylibre.com  Sat Apr 21 13:19:53 2018
From: jbrunet at baylibre.com (Jerome Brunet)
Date: Sat, 21 Apr 2018 22:19:53 +0200
Subject: [PATCH] clk: meson: add the video decoder clocks
In-Reply-To: <CAHStOZ7m+8xSX=k5k-LwmgZy6Ja4MFwsVjMy-FeoG=2c0rpm2g@mail.gmail.com>
References: <CAHStOZ7m+8xSX=k5k-LwmgZy6Ja4MFwsVjMy-FeoG=2c0rpm2g@mail.gmail.com>
Message-ID: <1524341993.2601.131.camel@baylibre.com>

On Sat, 2018-04-21 at 10:18 +0200, Maxime Jourdan wrote:
> In preparation for the V4L2 M2M driver, add the clocks for
> VDEC_1 and VDEC_HEVC to gxbb.
> 
> Signed-off-by: Maxime Jourdan <maxi.jourdan at wanadoo.fr>

a few other comments, in addition to what neil pointed out.

> ---
>  drivers/clk/meson/gxbb.c              | 112 ++++++++++++++++++++++++++
>  drivers/clk/meson/gxbb.h              |   4 +-
>  include/dt-bindings/clock/gxbb-clkc.h |   4 +
>  3 files changed, 119 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/clk/meson/gxbb.c b/drivers/clk/meson/gxbb.c
> index b1e4d9557610..f9d7ab9c924e 100644
> --- a/drivers/clk/meson/gxbb.c
> +++ b/drivers/clk/meson/gxbb.c
> @@ -1543,6 +1543,100 @@ static struct clk_regmap gxbb_vapb = {
>  	},
>  };
>  
> +/* VDEC clocks */
> +
> +static const char * const gxbb_vdec_parent_names[] = {
> +	"fclk_div4", "fclk_div3", "fclk_div5", "fclk_div7"
> +};
> +
> +static struct clk_regmap gxbb_vdec_1_sel = {
> +	.data = &(struct clk_regmap_mux_data){
> +		.offset = HHI_VDEC_CLK_CNTL,
> +		.mask = 0x3,
> +		.shift = 9,
> +	},
> +	.hw.init = &(struct clk_init_data){
> +		.name = "vdec_1_sel",
> +		.ops = &clk_regmap_mux_ops,
> +		.parent_names = gxbb_vdec_parent_names,
> +		.num_parents = ARRAY_SIZE(gxbb_vdec_parent_names),
> +		.flags = CLK_SET_RATE_NO_REPARENT,

Looks like you are/will be controlling the mux manually from your driver.
Any particular reason for doing so ?

Looking at the possible parent, you may as well call clk_set_rate() on the leaf
clock with 500Mhz, 666Mhz, etc ... it would accomplish the same thing but :
* You would need to get only one clock in your driver
* You don't need to manage the topology of the clock tree in your driver, which
could be interresting  if your driver ends up supporting more than GXBB.

> +	},
> +};
> +
> +static struct clk_regmap gxbb_vdec_1_div = {
> +	.data = &(struct clk_regmap_div_data){
> +		.offset = HHI_VDEC_CLK_CNTL,
> +		.shift = 0,
> +		.width = 7,
> +	},
> +	.hw.init = &(struct clk_init_data){
> +		.name = "vdec_1_div",
> +		.ops = &clk_regmap_divider_ops,
> +		.parent_names = (const char *[]){ "vdec_1_sel" },
> +		.num_parents = 1,
> +		.flags = CLK_SET_RATE_PARENT,
> +	},
> +};
> +
> +static struct clk_regmap gxbb_vdec_1 = {
> +	.data = &(struct clk_regmap_gate_data){
> +		.offset = HHI_VDEC_CLK_CNTL,
> +		.bit_idx = 8,
> +	},
> +	.hw.init = &(struct clk_init_data) {
> +		.name = "vdec_1",
> +		.ops = &clk_regmap_gate_ops,
> +		.parent_names = (const char *[]){ "vdec_1_div" },
> +		.num_parents = 1,
> +		.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,

Any particular reason for using CLK_IGNORE_UNUSED ?

You should only need CLK_IGNORE_UNUSED when the clock is left on by the
bootloader, and you need it stay that way until the driver load.

It allows to skip the clk_disable_unused() mechanism of CCF but I don't think
the video decoder should require this, unless I missed something.

> +	},
> +};
> +
> +static struct clk_regmap gxbb_vdec_hevc_sel = {
> +	.data = &(struct clk_regmap_mux_data){
> +		.offset = HHI_VDEC2_CLK_CNTL,
> +		.mask = 0x3,
> +		.shift = 25,
> +	},
> +	.hw.init = &(struct clk_init_data){
> +		.name = "vdec_hevc_sel",
> +		.ops = &clk_regmap_mux_ops,
> +		.parent_names = gxbb_vdec_parent_names,
> +		.num_parents = ARRAY_SIZE(gxbb_vdec_parent_names),
> +		.flags = CLK_SET_RATE_NO_REPARENT,
> +	},
> +};
> +
> +static struct clk_regmap gxbb_vdec_hevc_div = {
> +	.data = &(struct clk_regmap_div_data){
> +		.offset = HHI_VDEC2_CLK_CNTL,
> +		.shift = 16,
> +		.width = 7,
> +	},
> +	.hw.init = &(struct clk_init_data){
> +		.name = "vdec_hevc_div",
> +		.ops = &clk_regmap_divider_ops,
> +		.parent_names = (const char *[]){ "vdec_hevc_sel" },
> +		.num_parents = 1,
> +		.flags = CLK_SET_RATE_PARENT,
> +	},
> +};
> +
> +static struct clk_regmap gxbb_vdec_hevc = {
> +	.data = &(struct clk_regmap_gate_data){
> +		.offset = HHI_VDEC2_CLK_CNTL,
> +		.bit_idx = 24,
> +	},
> +	.hw.init = &(struct clk_init_data) {
> +		.name = "vdec_hevc",
> +		.ops = &clk_regmap_gate_ops,
> +		.parent_names = (const char *[]){ "vdec_hevc_div" },
> +		.num_parents = 1,
> +		.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
> +	},
> +};
> +
>  /* Everything Else (EE) domain gates */
>  static MESON_GATE(gxbb_ddr, HHI_GCLK_MPEG0, 0);
>  static MESON_GATE(gxbb_dos, HHI_GCLK_MPEG0, 1);
> @@ -1786,6 +1880,12 @@ static struct clk_hw_onecell_data gxbb_hw_onecell_data = {
>  		[CLKID_FCLK_DIV4_DIV]	    = &gxbb_fclk_div4_div.hw,
>  		[CLKID_FCLK_DIV5_DIV]	    = &gxbb_fclk_div5_div.hw,
>  		[CLKID_FCLK_DIV7_DIV]	    = &gxbb_fclk_div7_div.hw,
> +		[CLKID_VDEC_1_SEL]	    = &gxbb_vdec_1_sel.hw,
> +		[CLKID_VDEC_1_DIV]	    = &gxbb_vdec_1_div.hw,
> +		[CLKID_VDEC_1]		    = &gxbb_vdec_1.hw,
> +		[CLKID_VDEC_HEVC_SEL]	    = &gxbb_vdec_hevc_sel.hw,
> +		[CLKID_VDEC_HEVC_DIV]	    = &gxbb_vdec_hevc_div.hw,
> +		[CLKID_VDEC_HEVC]	    = &gxbb_vdec_hevc.hw,
>  		[NR_CLKS]		    = NULL,
>  	},
>  	.num = NR_CLKS,
> @@ -1942,6 +2042,12 @@ static struct clk_hw_onecell_data gxl_hw_onecell_data = {
>  		[CLKID_FCLK_DIV4_DIV]	    = &gxbb_fclk_div4_div.hw,
>  		[CLKID_FCLK_DIV5_DIV]	    = &gxbb_fclk_div5_div.hw,
>  		[CLKID_FCLK_DIV7_DIV]	    = &gxbb_fclk_div7_div.hw,
> +		[CLKID_VDEC_1_SEL]	    = &gxbb_vdec_1_sel.hw,
> +		[CLKID_VDEC_1_DIV]	    = &gxbb_vdec_1_div.hw,
> +		[CLKID_VDEC_1]		    = &gxbb_vdec_1.hw,
> +		[CLKID_VDEC_HEVC_SEL]	    = &gxbb_vdec_hevc_sel.hw,
> +		[CLKID_VDEC_HEVC_DIV]	    = &gxbb_vdec_hevc_div.hw,
> +		[CLKID_VDEC_HEVC]	    = &gxbb_vdec_hevc.hw,
>  		[NR_CLKS]		    = NULL,
>  	},
>  	.num = NR_CLKS,
> @@ -2100,6 +2206,12 @@ static struct clk_regmap *const gx_clk_regmaps[] = {
>  	&gxbb_fclk_div4,
>  	&gxbb_fclk_div5,
>  	&gxbb_fclk_div7,
> +	&gxbb_vdec_1_sel,
> +	&gxbb_vdec_1_div,
> +	&gxbb_vdec_1,
> +	&gxbb_vdec_hevc_sel,
> +	&gxbb_vdec_hevc_div,
> +	&gxbb_vdec_hevc,
>  };
>  
>  struct clkc_data {
> diff --git a/drivers/clk/meson/gxbb.h b/drivers/clk/meson/gxbb.h
> index 9febf3f03739..ae21d235355a 100644
> --- a/drivers/clk/meson/gxbb.h
> +++ b/drivers/clk/meson/gxbb.h
> @@ -204,8 +204,10 @@
>  #define CLKID_FCLK_DIV4_DIV	  148
>  #define CLKID_FCLK_DIV5_DIV	  149
>  #define CLKID_FCLK_DIV7_DIV	  150
> +#define CLKID_VDEC_1_DIV	  152
> +#define CLKID_VDEC_HEVC_DIV	  155
>  
> -#define NR_CLKS			  151
> +#define NR_CLKS			  157
>  

We prefer to get the DT binding part in a separate patch, it makes the platform
maintainer's life easier.

>  /* include the CLKIDs that have been made part of the DT binding */
>  #include <dt-bindings/clock/gxbb-clkc.h>
> diff --git a/include/dt-bindings/clock/gxbb-clkc.h b/include/dt-bindings/clock/gxbb-clkc.h
> index 8ba99a5e3fd3..ae7f6be747e4 100644
> --- a/include/dt-bindings/clock/gxbb-clkc.h
> +++ b/include/dt-bindings/clock/gxbb-clkc.h
> @@ -125,5 +125,9 @@
>  #define CLKID_VAPB_1		138
>  #define CLKID_VAPB_SEL		139
>  #define CLKID_VAPB		140
> +#define CLKID_VDEC_1_SEL	151
> +#define CLKID_VDEC_1		153
> +#define CLKID_VDEC_HEVC_SEL	154
> +#define CLKID_VDEC_HEVC	156
>  
>  #endif /* __GXBB_CLKC_H */
> -- 
> 2.17.0
> 
> 



From martin.blumenstingl at googlemail.com  Sun Apr 22 03:28:43 2018
From: martin.blumenstingl at googlemail.com (Martin Blumenstingl)
Date: Sun, 22 Apr 2018 12:28:43 +0200
Subject: [PATCH clk-fixes] clk: meson: meson8b: fix meson8b_fclk_div3_div
 clock name
Message-ID: <20180422102843.31238-1-martin.blumenstingl@googlemail.com>

The names of all fclk divider gate clocks follow the naming schema
"fclk_divN" and the name of all fclk fixed dividers follow the naming
schema "fclk_divN_div".
There's one exception to this rule: meson8b_fclk_div3_div's name is
"fclk_div_div3". It's child clock meson8b_fclk_div3 however references
it as "fclk_div3_div" (following the naming schema explained above).

Fix the naming of the meson8b_fclk_div3_div clock to follow the naming
schema. This also fixes serial console on my Meson8m2 board because
"clk81" uses fclk_div3 as parent. However, since the hierarchy stops at
meson8b_fclk_div3 there's no known parent clock and the rate of "clk81"
and all of it's children (UART clock, SDIO MMC controller clock, ...)
are all 0.

Fixes: 05f814402d6174 ("clk: meson: add fdiv clock gates")
Signed-off-by: Martin Blumenstingl <martin.blumenstingl at googlemail.com>
---
 drivers/clk/meson/meson8b.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/clk/meson/meson8b.c b/drivers/clk/meson/meson8b.c
index cc2992493e0b..2c4ff6192852 100644
--- a/drivers/clk/meson/meson8b.c
+++ b/drivers/clk/meson/meson8b.c
@@ -253,7 +253,7 @@ static struct clk_fixed_factor meson8b_fclk_div3_div = {
 	.mult = 1,
 	.div = 3,
 	.hw.init = &(struct clk_init_data){
-		.name = "fclk_div_div3",
+		.name = "fclk_div3_div",
 		.ops = &clk_fixed_factor_ops,
 		.parent_names = (const char *[]){ "fixed_pll" },
 		.num_parents = 1,
-- 
2.17.0



From martin.blumenstingl at googlemail.com  Sun Apr 22 03:33:38 2018
From: martin.blumenstingl at googlemail.com (Martin Blumenstingl)
Date: Sun, 22 Apr 2018 12:33:38 +0200
Subject: [PATCH v3 0/1] add support for the NAND clocks on Meson8b
Message-ID: <20180422103339.32608-1-martin.blumenstingl@googlemail.com>

This adds support for the NAND clocks found in the Meson8, Meson8b
and Meson8m2 SoCs.
The clocks consist of a simple gate, a divider and a mux. The mux
parents are not documented in the public S805 datasheet [0], so I
had to use a bit of math and take the vendor kernel as reference [1]
to find the actual parent clocks.
Some mux parents cannot be divided down without remainder to the
target clocks (as expected by the vendor NAND driver) these clocks
have the ROUND_CLOSEST flag set.

The new clocks are similar to gxbb_sd_emmc_c_clk0_sel,
gxbb_sd_emmc_c_clk0_div and gxbb_sd_emmc_c_clk0 on the GX SoCs.
Actual differences are:
- mux parents are re-ordered
- the gate is controlled by bit 8 (instead of bit 7 on GX)

Changes since v2 at [1]:
- rebased on top of v4.17-rc1 and updated the clocks to use the new
  clk_regmap framework (as all other clocks in meson8b.c)

Changes since v1 at [0]:
- rebased so it still applies in 2018
- dropped mux table (since the known parents are values 0..4)
- replaced CLK_SET_RATE_NO_REPARENT with CLK_SET_RATE_PARENT on the mux
- added CLK_SET_RATE_PARENT on the divider
- fixed width of the divider (it's 7 bits wide, ranging from bit 0 to 6
  while v1 only used a width of 6 bits)


[0] http://lists.infradead.org/pipermail/linux-amlogic/2017-April/003237.html
[1] http://lists.infradead.org/pipermail/linux-amlogic/2018-January/005934.html


Martin Blumenstingl (1):
  clk: meson: meson8b: add support for the NAND clocks

 drivers/clk/meson/meson8b.c              | 54 ++++++++++++++++++++++++
 drivers/clk/meson/meson8b.h              |  3 +-
 include/dt-bindings/clock/meson8b-clkc.h |  3 ++
 3 files changed, 59 insertions(+), 1 deletion(-)

-- 
2.17.0



From martin.blumenstingl at googlemail.com  Sun Apr 22 03:33:39 2018
From: martin.blumenstingl at googlemail.com (Martin Blumenstingl)
Date: Sun, 22 Apr 2018 12:33:39 +0200
Subject: [PATCH v3 1/1] clk: meson: meson8b: add support for the NAND clocks
In-Reply-To: <20180422103339.32608-1-martin.blumenstingl@googlemail.com>
References: <20180422103339.32608-1-martin.blumenstingl@googlemail.com>
Message-ID: <20180422103339.32608-2-martin.blumenstingl@googlemail.com>

This adds the NAND clocks (from the HHI_NAND_CLK_CNTL register) to the
Meson8b clock driver. There are three NAND clocks: a gate which enables
or disables the NAND clock, a mux and a divider (which divides the mux
output).
Unfortunately the public S805 datasheet does not document the mux
parents. However, the vendor kernel has a few hints for us which allows
us to make an educated guess about the clock parents. To do this we need
to have a look at set_nand_core_clk() from the vendor's NAND driver (see
[0]):
- XTAL = (4<<9) | (1<<8) | 0
- 160MHz = (0<<9) | (1<<8) | 3)
- 182MHz = (3<<9) | (1<<8) | 1)
- 212MHz = (1<<9) | (1<<8) | 3)
- 255MHz = (2<<9) | (1<<8) | 1)

While there is a comment for the XTAL parent (which indicates that it
should only be used for debugging) we have to do a bit of math for the
other parents: target_freq * divider = rate of parent clock
Bit 8 above is the enable bit, so we can ignore it here. Bits 11:9 are
the mux index and bits 6:0 are the 0-based divider (so we need to add
1). This gives us:
- mux 0 (160MHz * 4) = fclk_div4 (actual rate = 637.5MHz, off by 2.5MHz)
- mux 1 (212MHz * 4) = fclk_div3 (actual rate = 850MHz, off by 2MHz)
- mux 2 (255MHz * 2) = fclk_div5 (matches exactly 510MHz)
- mux 3 (182MHz * 2) = fclk_div7 (actual rate = 346.3MHz, off by 0.3MHz)

[0] https://github.com/khadas/linux/blob/9587681285cb/drivers/amlogic/amlnf/dev/amlnf_ctrl.c#L314

Signed-off-by: Martin Blumenstingl <martin.blumenstingl at googlemail.com>
---
 drivers/clk/meson/meson8b.c              | 54 ++++++++++++++++++++++++
 drivers/clk/meson/meson8b.h              |  3 +-
 include/dt-bindings/clock/meson8b-clkc.h |  3 ++
 3 files changed, 59 insertions(+), 1 deletion(-)

diff --git a/drivers/clk/meson/meson8b.c b/drivers/clk/meson/meson8b.c
index 2c4ff6192852..3f726ff73261 100644
--- a/drivers/clk/meson/meson8b.c
+++ b/drivers/clk/meson/meson8b.c
@@ -639,6 +639,54 @@ static struct clk_regmap meson8b_cpu_clk = {
 	},
 };
 
+static struct clk_regmap meson8b_nand_clk_sel = {
+	.data = &(struct clk_regmap_mux_data){
+		.offset = HHI_NAND_CLK_CNTL,
+		.mask = 0x7,
+		.shift = 9,
+		.flags = CLK_MUX_ROUND_CLOSEST,
+	},
+	.hw.init = &(struct clk_init_data){
+		.name = "nand_clk_sel",
+		.ops = &clk_regmap_mux_ops,
+		/* FIXME all other parents are unknown: */
+		.parent_names = (const char *[]){ "fclk_div4", "fclk_div3",
+			"fclk_div5", "fclk_div7", "xtal" },
+		.num_parents = 5,
+		.flags = CLK_SET_RATE_PARENT,
+	},
+};
+
+static struct clk_regmap meson8b_nand_clk_div = {
+	.data = &(struct clk_regmap_div_data){
+		.offset =  HHI_NAND_CLK_CNTL,
+		.shift = 0,
+		.width = 7,
+		.flags = CLK_DIVIDER_ROUND_CLOSEST,
+	},
+	.hw.init = &(struct clk_init_data){
+		.name = "nand_clk_div",
+		.ops = &clk_regmap_divider_ops,
+		.parent_names = (const char *[]){ "nand_clk_sel" },
+		.num_parents = 1,
+		.flags = CLK_SET_RATE_PARENT,
+	},
+};
+
+static struct clk_regmap meson8b_nand_clk_gate = {
+	.data = &(struct clk_regmap_gate_data){
+		.offset = HHI_NAND_CLK_CNTL,
+		.bit_idx = 8,
+	},
+	.hw.init = &(struct clk_init_data){
+		.name = "nand_clk_gate",
+		.ops = &clk_regmap_gate_ops,
+		.parent_names = (const char *[]){ "nand_clk_div" },
+		.num_parents = 1,
+		.flags = CLK_SET_RATE_PARENT,
+	},
+};
+
 /* Everything Else (EE) domain gates */
 
 static MESON_GATE(meson8b_ddr, HHI_GCLK_MPEG0, 0);
@@ -834,6 +882,9 @@ static struct clk_hw_onecell_data meson8b_hw_onecell_data = {
 		[CLKID_FCLK_DIV4_DIV]	    = &meson8b_fclk_div4_div.hw,
 		[CLKID_FCLK_DIV5_DIV]	    = &meson8b_fclk_div5_div.hw,
 		[CLKID_FCLK_DIV7_DIV]	    = &meson8b_fclk_div7_div.hw,
+		[CLKID_NAND_SEL]	    = &meson8b_nand_clk_sel.hw,
+		[CLKID_NAND_DIV]	    = &meson8b_nand_clk_div.hw,
+		[CLKID_NAND_CLK]	    = &meson8b_nand_clk_gate.hw,
 		[CLK_NR_CLKS]		    = NULL,
 	},
 	.num = CLK_NR_CLKS,
@@ -939,6 +990,9 @@ static struct clk_regmap *const meson8b_clk_regmaps[] = {
 	&meson8b_fclk_div4,
 	&meson8b_fclk_div5,
 	&meson8b_fclk_div7,
+	&meson8b_nand_clk_sel,
+	&meson8b_nand_clk_div,
+	&meson8b_nand_clk_gate,
 };
 
 static const struct meson8b_clk_reset_line {
diff --git a/drivers/clk/meson/meson8b.h b/drivers/clk/meson/meson8b.h
index 6e414bd36981..96549837ea7c 100644
--- a/drivers/clk/meson/meson8b.h
+++ b/drivers/clk/meson/meson8b.h
@@ -40,6 +40,7 @@
 #define HHI_VID_CLK_CNTL		0x17c /* 0x5f offset in data sheet */
 #define HHI_VID_DIVIDER_CNTL		0x198 /* 0x66 offset in data sheet */
 #define HHI_SYS_CPU_CLK_CNTL0		0x19c /* 0x67 offset in data sheet */
+#define HHI_NAND_CLK_CNTL		0x25c /* 0x97 offset in data sheet */
 #define HHI_MPLL_CNTL			0x280 /* 0xa0 offset in data sheet */
 #define HHI_SYS_PLL_CNTL		0x300 /* 0xc0 offset in data sheet */
 #define HHI_VID_PLL_CNTL		0x320 /* 0xc8 offset in data sheet */
@@ -84,7 +85,7 @@
 #define CLKID_FCLK_DIV5_DIV	108
 #define CLKID_FCLK_DIV7_DIV	109
 
-#define CLK_NR_CLKS		110
+#define CLK_NR_CLKS		113
 
 /*
  * include the CLKID and RESETID that have
diff --git a/include/dt-bindings/clock/meson8b-clkc.h b/include/dt-bindings/clock/meson8b-clkc.h
index dea9d46d4fa7..434d7ba63801 100644
--- a/include/dt-bindings/clock/meson8b-clkc.h
+++ b/include/dt-bindings/clock/meson8b-clkc.h
@@ -102,5 +102,8 @@
 #define CLKID_MPLL0		93
 #define CLKID_MPLL1		94
 #define CLKID_MPLL2		95
+#define CLKID_NAND_SEL		110
+#define CLKID_NAND_DIV		111
+#define CLKID_NAND_CLK		112
 
 #endif /* __MESON8B_CLKC_H */
-- 
2.17.0



From martin.blumenstingl at googlemail.com  Sun Apr 22 03:38:03 2018
From: martin.blumenstingl at googlemail.com (Martin Blumenstingl)
Date: Sun, 22 Apr 2018 12:38:03 +0200
Subject: [PATCH 0/2] Amlogic 32-bit multi_v7_defconfig updates
Message-ID: <20180422103805.1324-1-martin.blumenstingl@googlemail.com>

Some boards come with a PMU (system power controller, such as the Ricoh
RN5T618). These need CONFIG_I2C_MESON built-in so the regulators can be
set up during boot.

Also enable CONFIG_PWM_MESON (as module) because some boards use it to
dim the LED and/or generate the 32.768 kHz clock for the SDIO wifi chip.

@Kevin: I assume that you'll take this through your tree, so no immediate
action from the arm-soc maintainers needed, right?


Martin Blumenstingl (2):
  arm: multi_v7_defconfig: enable the Amlogic Meson I2C driver
  ARM: multi_v7_defconfig: enable the Meson PWM controller

 arch/arm/configs/multi_v7_defconfig | 2 ++
 1 file changed, 2 insertions(+)

-- 
2.17.0



From martin.blumenstingl at googlemail.com  Sun Apr 22 03:38:04 2018
From: martin.blumenstingl at googlemail.com (Martin Blumenstingl)
Date: Sun, 22 Apr 2018 12:38:04 +0200
Subject: [PATCH 1/2] arm: multi_v7_defconfig: enable the Amlogic Meson I2C
 driver
In-Reply-To: <20180422103805.1324-1-martin.blumenstingl@googlemail.com>
References: <20180422103805.1324-1-martin.blumenstingl@googlemail.com>
Message-ID: <20180422103805.1324-2-martin.blumenstingl@googlemail.com>

Some boards come with a PMIC (system power controller, for example Ricoh
RN5T618) which is connected through I2C.
Enable the Meson I2C driver so the devices on the I2C bus can be
registered during boot.

Signed-off-by: Martin Blumenstingl <martin.blumenstingl at googlemail.com>
---
 arch/arm/configs/multi_v7_defconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/configs/multi_v7_defconfig b/arch/arm/configs/multi_v7_defconfig
index e6b3c96d4c09..19e60d562e5f 100644
--- a/arch/arm/configs/multi_v7_defconfig
+++ b/arch/arm/configs/multi_v7_defconfig
@@ -364,6 +364,7 @@ CONFIG_HVC_DRIVER=y
 CONFIG_VIRTIO_CONSOLE=y
 CONFIG_I2C_CHARDEV=y
 CONFIG_I2C_DAVINCI=y
+CONFIG_I2C_MESON=y
 CONFIG_I2C_MUX=y
 CONFIG_I2C_ARB_GPIO_CHALLENGE=m
 CONFIG_I2C_MUX_PCA954x=y
-- 
2.17.0



From martin.blumenstingl at googlemail.com  Sun Apr 22 03:38:05 2018
From: martin.blumenstingl at googlemail.com (Martin Blumenstingl)
Date: Sun, 22 Apr 2018 12:38:05 +0200
Subject: [PATCH 2/2] ARM: multi_v7_defconfig: enable the Meson PWM controller
In-Reply-To: <20180422103805.1324-1-martin.blumenstingl@googlemail.com>
References: <20180422103805.1324-1-martin.blumenstingl@googlemail.com>
Message-ID: <20180422103805.1324-3-martin.blumenstingl@googlemail.com>

This enables the Amlogic Meson PWM controller. It is used for a dimmable
LED on some devices. Additionally some devices use it to generate the
32.768 kHz (low power oscillator) clock.

Signed-off-by: Martin Blumenstingl <martin.blumenstingl at googlemail.com>
---
 arch/arm/configs/multi_v7_defconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/configs/multi_v7_defconfig b/arch/arm/configs/multi_v7_defconfig
index 19e60d562e5f..e8e4341e96c7 100644
--- a/arch/arm/configs/multi_v7_defconfig
+++ b/arch/arm/configs/multi_v7_defconfig
@@ -948,6 +948,7 @@ CONFIG_PWM_ATMEL=m
 CONFIG_PWM_ATMEL_HLCDC_PWM=m
 CONFIG_PWM_ATMEL_TCB=m
 CONFIG_PWM_FSL_FTM=m
+CONFIG_PWM_MESON=m
 CONFIG_PWM_RCAR=m
 CONFIG_PWM_RENESAS_TPU=y
 CONFIG_PWM_ROCKCHIP=m
-- 
2.17.0



From martin.blumenstingl at googlemail.com  Sun Apr 22 03:45:00 2018
From: martin.blumenstingl at googlemail.com (Martin Blumenstingl)
Date: Sun, 22 Apr 2018 12:45:00 +0200
Subject: [PATCH 0/2] add the ARM PMU on Meson8 and Meson8b
Message-ID: <20180422104502.2942-1-martin.blumenstingl@googlemail.com>

Meson8 uses Cortex-A9 cores and Meson8b uses Cortex-A5 cores. As most
Cortex-A5/A9 implementation these Amlogic SoCs also come with a
built-in PMU for counting cpu and cache events like cache misses and
hits.

Testing was done with:
# perf stat -a stress --cpu 4
(wait for ~8 seconds, then CTRL+C)
stress: info: [347] dispatching hogs: 4 cpu, 0 io, 0 vm, 0 hdd
stress: Interrupt

 Performance counter stats for 'system wide':

      33096.764000      cpu-clock (msec)          #    4.000 CPUs utilized
               587      context-switches          #    0.018 K/sec
                 6      cpu-migrations            #    0.000 K/sec
               146      page-faults               #    0.004 K/sec
       39601836695      cycles                    #    1.197 GHz
       28734941189      instructions              #    0.73  insn per cycle
        3326006882      branches                  #  100.493 M/sec
          12294901      branch-misses             #    0.37% of all branches

       8.274358000 seconds time elapsed

# grep arm-pmu /proc/interrupts 
 29:          7          0          0          0     GIC-0 169 Level     arm-pmu
 30:          0          7          0          0     GIC-0 170 Level     arm-pmu
 31:          0          0          7          0     GIC-0 185 Level     arm-pmu
 32:          0          0          0          7     GIC-0 186 Level     arm-pmu


Martin Blumenstingl (2):
  ARM: dts: meson8: add the cortex-a9-pmu compatible PMU
  ARM: dts: meson8b: add the cortex-a5-pmu compatible PMU

 arch/arm/boot/dts/meson8.dtsi  | 17 +++++++++++++----
 arch/arm/boot/dts/meson8b.dtsi | 17 +++++++++++++----
 2 files changed, 26 insertions(+), 8 deletions(-)

-- 
2.17.0



From martin.blumenstingl at googlemail.com  Sun Apr 22 03:45:01 2018
From: martin.blumenstingl at googlemail.com (Martin Blumenstingl)
Date: Sun, 22 Apr 2018 12:45:01 +0200
Subject: [PATCH 1/2] ARM: dts: meson8: add the cortex-a9-pmu compatible PMU
In-Reply-To: <20180422104502.2942-1-martin.blumenstingl@googlemail.com>
References: <20180422104502.2942-1-martin.blumenstingl@googlemail.com>
Message-ID: <20180422104502.2942-2-martin.blumenstingl@googlemail.com>

Enable the performance monitor unit on Meson8.

Signed-off-by: Martin Blumenstingl <martin.blumenstingl at googlemail.com>
---
 arch/arm/boot/dts/meson8.dtsi | 17 +++++++++++++----
 1 file changed, 13 insertions(+), 4 deletions(-)

diff --git a/arch/arm/boot/dts/meson8.dtsi b/arch/arm/boot/dts/meson8.dtsi
index dcc9292d2ffa..7b16ea61e914 100644
--- a/arch/arm/boot/dts/meson8.dtsi
+++ b/arch/arm/boot/dts/meson8.dtsi
@@ -57,7 +57,7 @@
 		#address-cells = <1>;
 		#size-cells = <0>;
 
-		cpu at 200 {
+		cpu0: cpu at 200 {
 			device_type = "cpu";
 			compatible = "arm,cortex-a9";
 			next-level-cache = <&L2>;
@@ -66,7 +66,7 @@
 			resets = <&clkc CLKC_RESET_CPU0_SOFT_RESET>;
 		};
 
-		cpu at 201 {
+		cpu1: cpu at 201 {
 			device_type = "cpu";
 			compatible = "arm,cortex-a9";
 			next-level-cache = <&L2>;
@@ -75,7 +75,7 @@
 			resets = <&clkc CLKC_RESET_CPU1_SOFT_RESET>;
 		};
 
-		cpu at 202 {
+		cpu2: cpu at 202 {
 			device_type = "cpu";
 			compatible = "arm,cortex-a9";
 			next-level-cache = <&L2>;
@@ -84,7 +84,7 @@
 			resets = <&clkc CLKC_RESET_CPU2_SOFT_RESET>;
 		};
 
-		cpu at 203 {
+		cpu3: cpu at 203 {
 			device_type = "cpu";
 			compatible = "arm,cortex-a9";
 			next-level-cache = <&L2>;
@@ -94,6 +94,15 @@
 		};
 	};
 
+	pmu {
+		compatible = "arm,cortex-a9-pmu";
+		interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
+	};
+
 	reserved-memory {
 		#address-cells = <1>;
 		#size-cells = <1>;
-- 
2.17.0



From martin.blumenstingl at googlemail.com  Sun Apr 22 03:45:02 2018
From: martin.blumenstingl at googlemail.com (Martin Blumenstingl)
Date: Sun, 22 Apr 2018 12:45:02 +0200
Subject: [PATCH 2/2] ARM: dts: meson8b: add the cortex-a5-pmu compatible PMU
In-Reply-To: <20180422104502.2942-1-martin.blumenstingl@googlemail.com>
References: <20180422104502.2942-1-martin.blumenstingl@googlemail.com>
Message-ID: <20180422104502.2942-3-martin.blumenstingl@googlemail.com>

Enable the performance monitor unit on Meson8b.

Signed-off-by: Martin Blumenstingl <martin.blumenstingl at googlemail.com>
---
 arch/arm/boot/dts/meson8b.dtsi | 17 +++++++++++++----
 1 file changed, 13 insertions(+), 4 deletions(-)

diff --git a/arch/arm/boot/dts/meson8b.dtsi b/arch/arm/boot/dts/meson8b.dtsi
index 553b82174604..6cfd7e225cee 100644
--- a/arch/arm/boot/dts/meson8b.dtsi
+++ b/arch/arm/boot/dts/meson8b.dtsi
@@ -55,7 +55,7 @@
 		#address-cells = <1>;
 		#size-cells = <0>;
 
-		cpu at 200 {
+		cpu0: cpu at 200 {
 			device_type = "cpu";
 			compatible = "arm,cortex-a5";
 			next-level-cache = <&L2>;
@@ -64,7 +64,7 @@
 			resets = <&clkc CLKC_RESET_CPU0_SOFT_RESET>;
 		};
 
-		cpu at 201 {
+		cpu1: cpu at 201 {
 			device_type = "cpu";
 			compatible = "arm,cortex-a5";
 			next-level-cache = <&L2>;
@@ -73,7 +73,7 @@
 			resets = <&clkc CLKC_RESET_CPU1_SOFT_RESET>;
 		};
 
-		cpu at 202 {
+		cpu2: cpu at 202 {
 			device_type = "cpu";
 			compatible = "arm,cortex-a5";
 			next-level-cache = <&L2>;
@@ -82,7 +82,7 @@
 			resets = <&clkc CLKC_RESET_CPU2_SOFT_RESET>;
 		};
 
-		cpu at 203 {
+		cpu3: cpu at 203 {
 			device_type = "cpu";
 			compatible = "arm,cortex-a5";
 			next-level-cache = <&L2>;
@@ -92,6 +92,15 @@
 		};
 	};
 
+	pmu {
+		compatible = "arm,cortex-a5-pmu";
+		interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
+	};
+
 	reserved-memory {
 		#address-cells = <1>;
 		#size-cells = <1>;
-- 
2.17.0



From martin.blumenstingl at googlemail.com  Sun Apr 22 03:53:27 2018
From: martin.blumenstingl at googlemail.com (Martin Blumenstingl)
Date: Sun, 22 Apr 2018 12:53:27 +0200
Subject: [PATCH 0/3] pinctrl: meson: add support for the Meson8m2 SoC
Message-ID: <20180422105330.4712-1-martin.blumenstingl@googlemail.com>

The Meson8m2 SoC is a variant of Meson8 with some updates from Meson8b
(such as the Gigabit capable DesignWare MAC).
It is mostly pin compatible with Meson8, only 10 (existing) CBUS pins
get an additional function. Four of these are Ethernet RXD2, RXD3, TXD2
and TXD3 (GPIOZ_0..GPIOZ_3) which are required when the board uses an
RGMII PHY. GPIODV_24 and GPIODV_25 provide "VGA" support on Meson8,
which doesn't seem to be supported on Meson8m2 anymore.
The other 4 are GPIOH_9 (reg 3 bit 19), CARD_4 (reg 8 bit 8),
CARD_5 (reg 8 bit 7) and GPIOY_3 (reg 3 bit 11). Their function is
currently unknown.

The AOBUS pins seem to be identical on Meson8 and Meson8m2. However,
since there's no official documentation I decided to add a new compatible
string.


Martin Blumenstingl (3):
  dt-bindings: pinctrl: meson: add support for the Meson8m2 SoC
  pinctrl: meson: meson8: add support for the Meson8m2 SoC
  pinctrl: meson: meson8: add the RGMII RXD2/RXD3 and TXD2/TXD3 signals

 .../bindings/pinctrl/meson,pinctrl.txt        |  2 ++
 drivers/pinctrl/meson/pinctrl-meson8.c        | 23 +++++++++++++++++--
 2 files changed, 23 insertions(+), 2 deletions(-)

-- 
2.17.0



From martin.blumenstingl at googlemail.com  Sun Apr 22 03:53:29 2018
From: martin.blumenstingl at googlemail.com (Martin Blumenstingl)
Date: Sun, 22 Apr 2018 12:53:29 +0200
Subject: [PATCH 2/3] pinctrl: meson: meson8: add support for the Meson8m2 SoC
In-Reply-To: <20180422105330.4712-1-martin.blumenstingl@googlemail.com>
References: <20180422105330.4712-1-martin.blumenstingl@googlemail.com>
Message-ID: <20180422105330.4712-3-martin.blumenstingl@googlemail.com>

Add Meson8m2 support to the existing Meson8 pinctrl driver. Since there
are only very few changes (Meson8m2 has an extra signal on 10 CBUS pins,
no other differences were found so far).
Add the new compatible strings for Meson8m2 to the existing Meson8
driver so we don't have to duplicate the whole driver.

Signed-off-by: Martin Blumenstingl <martin.blumenstingl at googlemail.com>
---
 drivers/pinctrl/meson/pinctrl-meson8.c | 10 +++++++++-
 1 file changed, 9 insertions(+), 1 deletion(-)

diff --git a/drivers/pinctrl/meson/pinctrl-meson8.c b/drivers/pinctrl/meson/pinctrl-meson8.c
index 49c7ce03547b..086082aeb796 100644
--- a/drivers/pinctrl/meson/pinctrl-meson8.c
+++ b/drivers/pinctrl/meson/pinctrl-meson8.c
@@ -1,5 +1,5 @@
 /*
- * Pin controller and GPIO driver for Amlogic Meson8.
+ * Pin controller and GPIO driver for Amlogic Meson8 and Meson8m2.
  *
  * Copyright (C) 2014 Beniamino Galvani <b.galvani at gmail.com>
  *
@@ -1080,6 +1080,14 @@ static const struct of_device_id meson8_pinctrl_dt_match[] = {
 		.compatible = "amlogic,meson8-aobus-pinctrl",
 		.data = &meson8_aobus_pinctrl_data,
 	},
+	{
+		.compatible = "amlogic,meson8m2-cbus-pinctrl",
+		.data = &meson8_cbus_pinctrl_data,
+	},
+	{
+		.compatible = "amlogic,meson8m2-aobus-pinctrl",
+		.data = &meson8_aobus_pinctrl_data,
+	},
 	{ },
 };
 
-- 
2.17.0



From martin.blumenstingl at googlemail.com  Sun Apr 22 03:53:28 2018
From: martin.blumenstingl at googlemail.com (Martin Blumenstingl)
Date: Sun, 22 Apr 2018 12:53:28 +0200
Subject: [PATCH 1/3] dt-bindings: pinctrl: meson: add support for the Meson8m2
 SoC
In-Reply-To: <20180422105330.4712-1-martin.blumenstingl@googlemail.com>
References: <20180422105330.4712-1-martin.blumenstingl@googlemail.com>
Message-ID: <20180422105330.4712-2-martin.blumenstingl@googlemail.com>

The Meson8m2 SoC is a variant of Meson8 with some updates from Meson8b
(such as the Gigabit capable DesignWare MAC).
It is mostly pin compatible with Meson8, only 10 (existing) CBUS pins
get an additional function (four of these are Ethernet RXD2, RXD3, TXD2
and TXD3 which are required when the board uses an RGMII PHY).
The AOBUS pins seem to be identical on Meson8 and Meson8m2.

Signed-off-by: Martin Blumenstingl <martin.blumenstingl at googlemail.com>
---
 Documentation/devicetree/bindings/pinctrl/meson,pinctrl.txt | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/Documentation/devicetree/bindings/pinctrl/meson,pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/meson,pinctrl.txt
index 2c12f9789116..54ecb8ab7788 100644
--- a/Documentation/devicetree/bindings/pinctrl/meson,pinctrl.txt
+++ b/Documentation/devicetree/bindings/pinctrl/meson,pinctrl.txt
@@ -3,8 +3,10 @@
 Required properties for the root node:
  - compatible: one of "amlogic,meson8-cbus-pinctrl"
 		      "amlogic,meson8b-cbus-pinctrl"
+		      "amlogic,meson8m2-cbus-pinctrl"
 		      "amlogic,meson8-aobus-pinctrl"
 		      "amlogic,meson8b-aobus-pinctrl"
+		      "amlogic,meson8m2-aobus-pinctrl"
 		      "amlogic,meson-gxbb-periphs-pinctrl"
 		      "amlogic,meson-gxbb-aobus-pinctrl"
 		      "amlogic,meson-gxl-periphs-pinctrl"
-- 
2.17.0



From martin.blumenstingl at googlemail.com  Sun Apr 22 03:53:30 2018
From: martin.blumenstingl at googlemail.com (Martin Blumenstingl)
Date: Sun, 22 Apr 2018 12:53:30 +0200
Subject: [PATCH 3/3] pinctrl: meson: meson8: add the RGMII RXD2/RXD3 and
 TXD2/TXD3 signals
In-Reply-To: <20180422105330.4712-1-martin.blumenstingl@googlemail.com>
References: <20180422105330.4712-1-martin.blumenstingl@googlemail.com>
Message-ID: <20180422105330.4712-4-martin.blumenstingl@googlemail.com>

These are only available on the Meson8m2 SoC (which uses the same
DesignWare Ethernet MAC as Meson8b).
The "eth_tx_clk_50m" signal either provides a 50MHz clock for the RMII
PHYs or the RGMII TX clock (as far as we know the frequency is
controlled by the PRG_ETHERNET registers in the Ethernet MAC "glue" IP
block).

Signed-off-by: Martin Blumenstingl <martin.blumenstingl at googlemail.com>
---
 drivers/pinctrl/meson/pinctrl-meson8.c | 13 ++++++++++++-
 1 file changed, 12 insertions(+), 1 deletion(-)

diff --git a/drivers/pinctrl/meson/pinctrl-meson8.c b/drivers/pinctrl/meson/pinctrl-meson8.c
index 086082aeb796..c6d79315218f 100644
--- a/drivers/pinctrl/meson/pinctrl-meson8.c
+++ b/drivers/pinctrl/meson/pinctrl-meson8.c
@@ -299,6 +299,10 @@ static const unsigned int spi_mosi_1_pins[]	= { GPIOZ_12 };
 static const unsigned int spi_miso_1_pins[]	= { GPIOZ_13 };
 static const unsigned int spi_ss2_1_pins[]	= { GPIOZ_14 };
 
+static const unsigned int eth_txd3_pins[]	= { GPIOZ_0 };
+static const unsigned int eth_txd2_pins[]	= { GPIOZ_1 };
+static const unsigned int eth_rxd3_pins[]	= { GPIOZ_2 };
+static const unsigned int eth_rxd2_pins[]	= { GPIOZ_3 };
 static const unsigned int eth_tx_clk_50m_pins[]	= { GPIOZ_4 };
 static const unsigned int eth_tx_en_pins[]	= { GPIOZ_5 };
 static const unsigned int eth_txd1_pins[]	= { GPIOZ_6 };
@@ -650,6 +654,12 @@ static struct meson_pmx_group meson8_cbus_groups[] = {
 	GROUP(eth_mdio,		6,	6),
 	GROUP(eth_mdc,		6,	5),
 
+	/* NOTE: the following four groups are only available on Meson8m2: */
+	GROUP(eth_rxd2,		6,	3),
+	GROUP(eth_rxd3,		6,	2),
+	GROUP(eth_txd2,		6,	1),
+	GROUP(eth_txd3,		6,	0),
+
 	GROUP(i2c_sda_a0,	5,	31),
 	GROUP(i2c_sck_a0,	5,	30),
 
@@ -877,7 +887,8 @@ static const char * const spi_groups[] = {
 static const char * const ethernet_groups[] = {
 	"eth_tx_clk_50m", "eth_tx_en", "eth_txd1",
 	"eth_txd0", "eth_rx_clk_in", "eth_rx_dv",
-	"eth_rxd1", "eth_rxd0", "eth_mdio", "eth_mdc"
+	"eth_rxd1", "eth_rxd0", "eth_mdio", "eth_mdc", "eth_rxd2",
+	"eth_rxd3", "eth_txd2", "eth_txd3"
 };
 
 static const char * const i2c_a_groups[] = {
-- 
2.17.0



From gregkh at linuxfoundation.org  Sun Apr 22 06:01:09 2018
From: gregkh at linuxfoundation.org (Greg KH)
Date: Sun, 22 Apr 2018 15:01:09 +0200
Subject: [PATCH usb v6 6/6] usb: core: phy: add the
 SPDX-License-Identifier and include guard
In-Reply-To: <20180418193951.17922-7-martin.blumenstingl@googlemail.com>
References: <20180418193951.17922-1-martin.blumenstingl@googlemail.com>
 <20180418193951.17922-7-martin.blumenstingl@googlemail.com>
Message-ID: <20180422130109.GA5781@kroah.com>

On Wed, Apr 18, 2018 at 09:39:51PM +0200, Martin Blumenstingl wrote:
> This clarifies the license of the code. While here also add an include
> guard to the header file.
> 
> Fixes: 07dbff0ddbd86c ("usb: core: add a wrapper for the USB PHYs on the HCD")
> Suggested-by: Masahiro Yamada <yamada.masahiro at socionext.com>
> Signed-off-by: Martin Blumenstingl <martin.blumenstingl at googlemail.com>
> ---
>  drivers/usb/core/phy.h | 12 ++++++++++++
>  1 file changed, 12 insertions(+)
> 
> diff --git a/drivers/usb/core/phy.h b/drivers/usb/core/phy.h
> index bbc969383074..88a3c037e9df 100644
> --- a/drivers/usb/core/phy.h
> +++ b/drivers/usb/core/phy.h
> @@ -1,3 +1,13 @@
> +/* SPDX-License-Identifier: GPL-2.0+ */

Do you _really_ mean GPLv2 or anything later?

I have to ask...

thanks,

greg k-h


From martin.blumenstingl at googlemail.com  Sun Apr 22 12:41:56 2018
From: martin.blumenstingl at googlemail.com (Martin Blumenstingl)
Date: Sun, 22 Apr 2018 21:41:56 +0200
Subject: [PATCH usb v6 6/6] usb: core: phy: add the SPDX-License-Identifier
 and include guard
In-Reply-To: <20180422130109.GA5781@kroah.com>
References: <20180418193951.17922-1-martin.blumenstingl@googlemail.com>
 <20180418193951.17922-7-martin.blumenstingl@googlemail.com>
 <20180422130109.GA5781@kroah.com>
Message-ID: <CAFBinCBv+zwjjjA_HeDY_e=aZwVpktzqM7wszZ-Ejvid+ZBe-A@mail.gmail.com>

Hi Greg,

On Sun, Apr 22, 2018 at 3:01 PM, Greg KH <gregkh at linuxfoundation.org> wrote:
> On Wed, Apr 18, 2018 at 09:39:51PM +0200, Martin Blumenstingl wrote:
>> This clarifies the license of the code. While here also add an include
>> guard to the header file.
>>
>> Fixes: 07dbff0ddbd86c ("usb: core: add a wrapper for the USB PHYs on the HCD")
>> Suggested-by: Masahiro Yamada <yamada.masahiro at socionext.com>
>> Signed-off-by: Martin Blumenstingl <martin.blumenstingl at googlemail.com>
>> ---
>>  drivers/usb/core/phy.h | 12 ++++++++++++
>>  1 file changed, 12 insertions(+)
>>
>> diff --git a/drivers/usb/core/phy.h b/drivers/usb/core/phy.h
>> index bbc969383074..88a3c037e9df 100644
>> --- a/drivers/usb/core/phy.h
>> +++ b/drivers/usb/core/phy.h
>> @@ -1,3 +1,13 @@
>> +/* SPDX-License-Identifier: GPL-2.0+ */
>
> Do you _really_ mean GPLv2 or anything later?
drivers/usb/core/hcd.c uses the same license identifier
that code is much more "valuable" than my few lines which manage a
list of PHYs - so I'm fine with "GPLv2 or anything later"

> I have to ask...
if you see any problems with this (for example that phy.h couldn't be
used from some special module with another license, ...) then please
let me know


Regards
Martin


From yixun.lan at amlogic.com  Mon Apr 23 07:57:29 2018
From: yixun.lan at amlogic.com (Yixun Lan)
Date: Mon, 23 Apr 2018 14:57:29 +0000
Subject: [PATCH] ARM64: dts: meson-axg: enable AP6255 wifi module
Message-ID: <20180423145729.14368-1-yixun.lan@amlogic.com>

The Meson-AXG S400 board is shipped with AP6255 wifi module,
which is actually using the brcmfmac 43455 driver.

Signed-off-by: Yixun Lan <yixun.lan at amlogic.com>
---
 .../arm64/boot/dts/amlogic/meson-axg-s400.dts | 44 ++++++++++++++++++-
 1 file changed, 43 insertions(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts b/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts
index f67d4e47e641..b3e1bdca32bb 100644
--- a/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts
+++ b/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts
@@ -51,7 +51,16 @@
 
 	sdio_pwrseq: sdio-pwrseq {
 		compatible = "mmc-pwrseq-simple";
-		reset-gpios = <&gpio GPIOX_6 GPIO_ACTIVE_LOW>;
+		reset-gpios = <&gpio GPIOX_7 GPIO_ACTIVE_LOW>;
+		clocks = <&wifi32k>;
+		clock-names = "ext_clock";
+	};
+
+	wifi32k: wifi32k {
+		compatible = "pwm-clock";
+		#clock-cells = <0>;
+		clock-frequency = <32768>;
+		pwms = <&pwm_ab 0 30518 0>; /* PWM_A at 32.768KHz */
 	};
 };
 
@@ -86,6 +95,12 @@
 	pinctrl-names = "default";
 };
 
+&pwm_ab {
+	status = "okay";
+	pinctrl-0 = <&pwm_a_x20_pins>;
+	pinctrl-names = "default";
+};
+
 /* emmc storage */
 &sd_emmc_c {
 	status = "okay";
@@ -105,3 +120,30 @@
 	vmmc-supply = <&vcc_3v3>;
 	vqmmc-supply = <&vddio_boot>;
 };
+
+/* wifi module */
+&sd_emmc_b {
+	status = "okay";
+	#address-cells = <1>;
+	#size-cells = <0>;
+
+	pinctrl-0 = <&sdio_pins>;
+	pinctrl-1 = <&sdio_clk_gate_pins>;
+	pinctrl-names = "default", "clk-gate";
+
+	bus-width = <4>;
+	cap-sd-highspeed;
+	max-frequency = <100000000>;
+	non-removable;
+	disable-wp;
+
+	mmc-pwrseq = <&sdio_pwrseq>;
+
+	vmmc-supply = <&vddao_3v3>;
+	vqmmc-supply = <&vddio_boot>;
+
+	brcmf: wifi at 1 {
+		reg = <1>;
+		compatible = "brcm,bcm4329-fmac";
+	};
+};
-- 
2.17.0



From yixun.lan at amlogic.com  Mon Apr 23 00:21:22 2018
From: yixun.lan at amlogic.com (Yixun Lan)
Date: Mon, 23 Apr 2018 15:21:22 +0800
Subject: dt-bindings: Invalid SPDX License Identifier
In-Reply-To: <alpine.DEB.2.21.1804222108120.6136@nanos.tec.linutronix.de>
References: <alpine.DEB.2.21.1804222108120.6136@nanos.tec.linutronix.de>
Message-ID: <795a50ff-d627-bcd5-950f-71e98016707e@amlogic.com>

Hi Thomas

On 04/23/18 03:14, Thomas Gleixner wrote:
> Yixun,
> 
> commit c16292578ffa437c77e17d5d3da20330a10b8a86
> Author: Yixun Lan <yixun.lan at amlogic.com>
> Date:   Fri Nov 10 16:46:49 2017 +0800
> 
>     dt-bindings: reset: Add bindings for the Meson-AXG SoC Reset Controller
>     
>     Add DT bindings for the Meson-AXG SoC Reset Controller include file,
>     and also slightly update documentation.
>     
>     Signed-off-by: Yixun Lan <yixun.lan at amlogic.com>
>     Reviewed-by: Neil Armstrong <narmstrong at baylibre.com>
>     Signed-off-by: Philipp Zabel <p.zabel at pengutronix.de>
> 
> Added the following SPDX-License-Identifier: (GPL-2.0+ OR BSD) in the
> middle of the top of file comment.
> 
> There are two problems with that:
> 
> 1) BSD is not a valid SPDX identifier. See https://spdx.org/licenses/
> 
>    You need to say which BSD variant you mean.
> 
> 2) Please put the License identifier to the place which is defined in
>    Documentation/process/licenses.rst, i.e. the first line of the dts file
>    and not to some random place.
> 

thanks for pointing this out

I will adjust the license to "GPL-2.0+ OR BSD-3-Clause" since this file
was copied from include/dt-bindings/reset/amlogic,meson-gxbb-reset.h
and it's a good idea to preserve the old license.

Yixun


From yixun.lan at amlogic.com  Mon Apr 23 08:29:07 2018
From: yixun.lan at amlogic.com (Yixun Lan)
Date: Mon, 23 Apr 2018 15:29:07 +0000
Subject: [PATCH] dt-bindings: reset: fix invalid SPDX license identifier
Message-ID: <20180423152907.5113-1-yixun.lan@amlogic.com>

This fix invalid SPDX license indentifier, also move it to
first top line according to documentation.

Link: https://lkml.org/lkml/2018/4/22/713
Fixes: c16292578ffa ("dt-bindings: reset: Add bindings for the Meson-AXG SoC Reset Controller")
Reported-by: Thomas Gleixner <tglx at linutronix.de>
Signed-off-by: Yixun Lan <yixun.lan at amlogic.com>
---
 include/dt-bindings/reset/amlogic,meson-axg-reset.h | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/include/dt-bindings/reset/amlogic,meson-axg-reset.h b/include/dt-bindings/reset/amlogic,meson-axg-reset.h
index ad6f55dabd6d..4a8e52f68fb7 100644
--- a/include/dt-bindings/reset/amlogic,meson-axg-reset.h
+++ b/include/dt-bindings/reset/amlogic,meson-axg-reset.h
@@ -1,3 +1,4 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */
 /*
  *
  * Copyright (c) 2016 BayLibre, SAS.
@@ -5,8 +6,6 @@
  *
  * Copyright (c) 2017 Amlogic, inc.
  * Author: Yixun Lan <yixun.lan at amlogic.com>
- *
- * SPDX-License-Identifier: (GPL-2.0+ OR BSD)
  */
 
 #ifndef _DT_BINDINGS_AMLOGIC_MESON_AXG_RESET_H
-- 
2.17.0



From geert+renesas at glider.be  Mon Apr 23 00:32:40 2018
From: geert+renesas at glider.be (Geert Uytterhoeven)
Date: Mon, 23 Apr 2018 09:32:40 +0200
Subject: [PATCH] dt-bindings: meson-uart: DT fix s/clocks-names/clock-names/
Message-ID: <1524468760-22912-1-git-send-email-geert+renesas@glider.be>

Signed-off-by: Geert Uytterhoeven <geert+renesas at glider.be>
---
 Documentation/devicetree/bindings/serial/amlogic,meson-uart.txt | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/serial/amlogic,meson-uart.txt b/Documentation/devicetree/bindings/serial/amlogic,meson-uart.txt
index 8ff65fa632fdedd7..c06c045126fc9070 100644
--- a/Documentation/devicetree/bindings/serial/amlogic,meson-uart.txt
+++ b/Documentation/devicetree/bindings/serial/amlogic,meson-uart.txt
@@ -21,7 +21,7 @@ Required properties:
 - interrupts : identifier to the device interrupt
 - clocks : a list of phandle + clock-specifier pairs, one for each
 	   entry in clock names.
-- clocks-names :
+- clock-names :
    * "xtal" for external xtal clock identifier
    * "pclk" for the bus core clock, either the clk81 clock or the gate clock
    * "baud" for the source of the baudrate generator, can be either the xtal
-- 
2.7.4



From gregkh at linuxfoundation.org  Mon Apr 23 00:39:35 2018
From: gregkh at linuxfoundation.org (Greg KH)
Date: Mon, 23 Apr 2018 09:39:35 +0200
Subject: [PATCH usb v6 6/6] usb: core: phy: add the
 SPDX-License-Identifier and include guard
In-Reply-To: <CAFBinCBv+zwjjjA_HeDY_e=aZwVpktzqM7wszZ-Ejvid+ZBe-A@mail.gmail.com>
References: <20180418193951.17922-1-martin.blumenstingl@googlemail.com>
 <20180418193951.17922-7-martin.blumenstingl@googlemail.com>
 <20180422130109.GA5781@kroah.com>
 <CAFBinCBv+zwjjjA_HeDY_e=aZwVpktzqM7wszZ-Ejvid+ZBe-A@mail.gmail.com>
Message-ID: <20180423073935.GA2484@kroah.com>

On Sun, Apr 22, 2018 at 09:41:56PM +0200, Martin Blumenstingl wrote:
> Hi Greg,
> 
> On Sun, Apr 22, 2018 at 3:01 PM, Greg KH <gregkh at linuxfoundation.org> wrote:
> > On Wed, Apr 18, 2018 at 09:39:51PM +0200, Martin Blumenstingl wrote:
> >> This clarifies the license of the code. While here also add an include
> >> guard to the header file.
> >>
> >> Fixes: 07dbff0ddbd86c ("usb: core: add a wrapper for the USB PHYs on the HCD")
> >> Suggested-by: Masahiro Yamada <yamada.masahiro at socionext.com>
> >> Signed-off-by: Martin Blumenstingl <martin.blumenstingl at googlemail.com>
> >> ---
> >>  drivers/usb/core/phy.h | 12 ++++++++++++
> >>  1 file changed, 12 insertions(+)
> >>
> >> diff --git a/drivers/usb/core/phy.h b/drivers/usb/core/phy.h
> >> index bbc969383074..88a3c037e9df 100644
> >> --- a/drivers/usb/core/phy.h
> >> +++ b/drivers/usb/core/phy.h
> >> @@ -1,3 +1,13 @@
> >> +/* SPDX-License-Identifier: GPL-2.0+ */
> >
> > Do you _really_ mean GPLv2 or anything later?
> drivers/usb/core/hcd.c uses the same license identifier
> that code is much more "valuable" than my few lines which manage a
> list of PHYs - so I'm fine with "GPLv2 or anything later"
> 
> > I have to ask...
> if you see any problems with this (for example that phy.h couldn't be
> used from some special module with another license, ...) then please
> let me know

Nope, that's fine, thanks for the quick response, I'll go apply this
now.

greg k-h


From tglx at linutronix.de  Mon Apr 23 00:45:10 2018
From: tglx at linutronix.de (Thomas Gleixner)
Date: Mon, 23 Apr 2018 09:45:10 +0200 (CEST)
Subject: [PATCH] dt-bindings: reset: fix invalid SPDX license
 identifier
In-Reply-To: <20180423152907.5113-1-yixun.lan@amlogic.com>
References: <20180423152907.5113-1-yixun.lan@amlogic.com>
Message-ID: <alpine.DEB.2.21.1804230939350.6136@nanos.tec.linutronix.de>

On Mon, 23 Apr 2018, Yixun Lan wrote:

> This fix invalid SPDX license indentifier, also move it to
> first top line according to documentation.
> 
> Link: https://lkml.org/lkml/2018/4/22/713

Please do not use lkml.org links. lkml.org is not always usable. Use;

 https://lkml.kernel.org/r/$MESSAGE-ID

instead. So this would be

 https://lkml.kernel.org/r/alpine.DEB.2.21.1804222108120.6136 at nanos.tec.linutronix.de

The reason is that kernel.org is very likely there as long as the kernel
exists, but random archives can vanish, change their URL, etc. The above
address is a redirector to the marc archive, but if that vanishes or stops
working the redirector can point to some other working archive.

> Fixes: c16292578ffa ("dt-bindings: reset: Add bindings for the Meson-AXG SoC Reset Controller")
> Reported-by: Thomas Gleixner <tglx at linutronix.de>
> Signed-off-by: Yixun Lan <yixun.lan at amlogic.com>
> ---
>  include/dt-bindings/reset/amlogic,meson-axg-reset.h | 3 +--
>  1 file changed, 1 insertion(+), 2 deletions(-)
> 
> diff --git a/include/dt-bindings/reset/amlogic,meson-axg-reset.h b/include/dt-bindings/reset/amlogic,meson-axg-reset.h
> index ad6f55dabd6d..4a8e52f68fb7 100644
> --- a/include/dt-bindings/reset/amlogic,meson-axg-reset.h
> +++ b/include/dt-bindings/reset/amlogic,meson-axg-reset.h
> @@ -1,3 +1,4 @@
> +/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */

Reviewed-by: Thomas Gleixner <tglx at linutronix.de>


From yixun.lan at amlogic.com  Mon Apr 23 01:12:29 2018
From: yixun.lan at amlogic.com (Yixun Lan)
Date: Mon, 23 Apr 2018 16:12:29 +0800
Subject: [PATCH] dt-bindings: reset: fix invalid SPDX license identifier
In-Reply-To: <alpine.DEB.2.21.1804230939350.6136@nanos.tec.linutronix.de>
References: <20180423152907.5113-1-yixun.lan@amlogic.com>
 <alpine.DEB.2.21.1804230939350.6136@nanos.tec.linutronix.de>
Message-ID: <2b97cdb5-6cd3-34fc-17e9-4df8cba82850@amlogic.com>

Hi Thomas
	
On 04/23/18 15:45, Thomas Gleixner wrote:
> On Mon, 23 Apr 2018, Yixun Lan wrote:
> 
>> This fix invalid SPDX license indentifier, also move it to
>> first top line according to documentation.
>>
>> Link: https://lkml.org/lkml/2018/4/22/713
> 
> Please do not use lkml.org links. lkml.org is not always usable. Use;
> 
>  https://lkml.kernel.org/r/$MESSAGE-ID
> 
> instead. So this would be
> 
>  https://lkml.kernel.org/r/alpine.DEB.2.21.1804222108120.6136 at nanos.tec.linutronix.de
> 
> The reason is that kernel.org is very likely there as long as the kernel
> exists, but random archives can vanish, change their URL, etc. The above
> address is a redirector to the marc archive, but if that vanishes or stops
> working the redirector can point to some other working archive.
> 
oh, never know the difference, thanks for the info

>> Fixes: c16292578ffa ("dt-bindings: reset: Add bindings for the Meson-AXG SoC Reset Controller")
>> Reported-by: Thomas Gleixner <tglx at linutronix.de>
>> Signed-off-by: Yixun Lan <yixun.lan at amlogic.com>
>> ---
>>  include/dt-bindings/reset/amlogic,meson-axg-reset.h | 3 +--
>>  1 file changed, 1 insertion(+), 2 deletions(-)
>>
>> diff --git a/include/dt-bindings/reset/amlogic,meson-axg-reset.h b/include/dt-bindings/reset/amlogic,meson-axg-reset.h
>> index ad6f55dabd6d..4a8e52f68fb7 100644
>> --- a/include/dt-bindings/reset/amlogic,meson-axg-reset.h
>> +++ b/include/dt-bindings/reset/amlogic,meson-axg-reset.h
>> @@ -1,3 +1,4 @@
>> +/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */
> 
> Reviewed-by: Thomas Gleixner <tglx at linutronix.de>
> 
thanks, I'll update



Yixun


From jbrunet at baylibre.com  Mon Apr 23 01:23:17 2018
From: jbrunet at baylibre.com (Jerome Brunet)
Date: Mon, 23 Apr 2018 10:23:17 +0200
Subject: [PATCH clk-fixes] clk: meson: meson8b: fix
 meson8b_fclk_div3_div clock name
In-Reply-To: <20180422102843.31238-1-martin.blumenstingl@googlemail.com>
References: <20180422102843.31238-1-martin.blumenstingl@googlemail.com>
Message-ID: <1524471797.4026.3.camel@baylibre.com>

On Sun, 2018-04-22 at 12:28 +0200, Martin Blumenstingl wrote:
> The names of all fclk divider gate clocks follow the naming schema
> "fclk_divN" and the name of all fclk fixed dividers follow the naming
> schema "fclk_divN_div".
> There's one exception to this rule: meson8b_fclk_div3_div's name is
> "fclk_div_div3". It's child clock meson8b_fclk_div3 however references
> it as "fclk_div3_div" (following the naming schema explained above).
> 
> Fix the naming of the meson8b_fclk_div3_div clock to follow the naming
> schema. This also fixes serial console on my Meson8m2 board because
> "clk81" uses fclk_div3 as parent. However, since the hierarchy stops at
> meson8b_fclk_div3 there's no known parent clock and the rate of "clk81"
> and all of it's children (UART clock, SDIO MMC controller clock, ...)
> are all 0.
> 
> Fixes: 05f814402d6174 ("clk: meson: add fdiv clock gates")
> Signed-off-by: Martin Blumenstingl <martin.blumenstingl at googlemail.com>

Oopss ... Thanks for fixing this Martin.

Reviewed-by: Jerome Brunet <jbrunet at baylibre.com>

Stephen, Do you mind taking this directly for fixes ? I can prepare a PR if you
prefer.

Regards
Jerome

> ---
>  drivers/clk/meson/meson8b.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/clk/meson/meson8b.c b/drivers/clk/meson/meson8b.c
> index cc2992493e0b..2c4ff6192852 100644
> --- a/drivers/clk/meson/meson8b.c
> +++ b/drivers/clk/meson/meson8b.c
> @@ -253,7 +253,7 @@ static struct clk_fixed_factor meson8b_fclk_div3_div = {
>  	.mult = 1,
>  	.div = 3,
>  	.hw.init = &(struct clk_init_data){
> -		.name = "fclk_div_div3",
> +		.name = "fclk_div3_div",
>  		.ops = &clk_fixed_factor_ops,
>  		.parent_names = (const char *[]){ "fixed_pll" },
>  		.num_parents = 1,



From yixun.lan at amlogic.com  Mon Apr 23 09:25:12 2018
From: yixun.lan at amlogic.com (Yixun Lan)
Date: Mon, 23 Apr 2018 16:25:12 +0000
Subject: [PATCH v2] dt-bindings: reset: fix invalid SPDX license identifier
Message-ID: <20180423162513.4564-1-yixun.lan@amlogic.com>

This fix invalid SPDX license indentifier, also move it to
first top line according to documentation.

Link: https://lkml.kernel.org/r/alpine.DEB.2.21.1804222108120.6136 at nanos.tec.linutronix.de
Fixes: c16292578ffa ("dt-bindings: reset: Add bindings for the Meson-AXG SoC Reset Controller")
Reviewed-by: Thomas Gleixner <tglx at linutronix.de>
Signed-off-by: Yixun Lan <yixun.lan at amlogic.com>

---
 Change since v1 at [1]:
  - update the Link URL
  - add Thomas' Reviewed-by

[1] https://lkml.kernel.org/r/20180423152907.5113-1-yixun.lan at amlogic.com
---
 include/dt-bindings/reset/amlogic,meson-axg-reset.h | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/include/dt-bindings/reset/amlogic,meson-axg-reset.h b/include/dt-bindings/reset/amlogic,meson-axg-reset.h
index ad6f55dabd6d..4a8e52f68fb7 100644
--- a/include/dt-bindings/reset/amlogic,meson-axg-reset.h
+++ b/include/dt-bindings/reset/amlogic,meson-axg-reset.h
@@ -1,3 +1,4 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */
 /*
  *
  * Copyright (c) 2016 BayLibre, SAS.
@@ -5,8 +6,6 @@
  *
  * Copyright (c) 2017 Amlogic, inc.
  * Author: Yixun Lan <yixun.lan at amlogic.com>
- *
- * SPDX-License-Identifier: (GPL-2.0+ OR BSD)
  */
 
 #ifndef _DT_BINDINGS_AMLOGIC_MESON_AXG_RESET_H
-- 
2.17.0



From jbrunet at baylibre.com  Mon Apr 23 01:33:29 2018
From: jbrunet at baylibre.com (Jerome Brunet)
Date: Mon, 23 Apr 2018 10:33:29 +0200
Subject: [PATCH v3 1/1] clk: meson: meson8b: add support for the NAND
 clocks
In-Reply-To: <20180422103339.32608-2-martin.blumenstingl@googlemail.com>
References: <20180422103339.32608-1-martin.blumenstingl@googlemail.com>
 <20180422103339.32608-2-martin.blumenstingl@googlemail.com>
Message-ID: <1524472409.4026.10.camel@baylibre.com>

On Sun, 2018-04-22 at 12:33 +0200, Martin Blumenstingl wrote:
> This adds the NAND clocks (from the HHI_NAND_CLK_CNTL register) to the
> Meson8b clock driver. There are three NAND clocks: a gate which enables
> or disables the NAND clock, a mux and a divider (which divides the mux
> output).
> Unfortunately the public S805 datasheet does not document the mux
> parents. However, the vendor kernel has a few hints for us which allows
> us to make an educated guess about the clock parents. To do this we need
> to have a look at set_nand_core_clk() from the vendor's NAND driver (see
> [0]):
> - XTAL = (4<<9) | (1<<8) | 0
> - 160MHz = (0<<9) | (1<<8) | 3)
> - 182MHz = (3<<9) | (1<<8) | 1)
> - 212MHz = (1<<9) | (1<<8) | 3)
> - 255MHz = (2<<9) | (1<<8) | 1)
> 
> While there is a comment for the XTAL parent (which indicates that it
> should only be used for debugging) we have to do a bit of math for the
> other parents: target_freq * divider = rate of parent clock
> Bit 8 above is the enable bit, so we can ignore it here. Bits 11:9 are
> the mux index and bits 6:0 are the 0-based divider (so we need to add
> 1). This gives us:
> - mux 0 (160MHz * 4) = fclk_div4 (actual rate = 637.5MHz, off by 2.5MHz)
> - mux 1 (212MHz * 4) = fclk_div3 (actual rate = 850MHz, off by 2MHz)
> - mux 2 (255MHz * 2) = fclk_div5 (matches exactly 510MHz)
> - mux 3 (182MHz * 2) = fclk_div7 (actual rate = 346.3MHz, off by 0.3MHz)
> 
> [0] https://github.com/khadas/linux/blob/9587681285cb/drivers/amlogic/amlnf/dev/amlnf_ctrl.c#L314
> 
> Signed-off-by: Martin Blumenstingl <martin.blumenstingl at googlemail.com>
> ---
>  drivers/clk/meson/meson8b.c              | 54 ++++++++++++++++++++++++
>  drivers/clk/meson/meson8b.h              |  3 +-
>  include/dt-bindings/clock/meson8b-clkc.h |  3 ++
>  3 files changed, 59 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/clk/meson/meson8b.c b/drivers/clk/meson/meson8b.c
> index 2c4ff6192852..3f726ff73261 100644
> --- a/drivers/clk/meson/meson8b.c
> +++ b/drivers/clk/meson/meson8b.c
> @@ -639,6 +639,54 @@ static struct clk_regmap meson8b_cpu_clk = {
>  	},
>  };
>  
> +static struct clk_regmap meson8b_nand_clk_sel = {
> +	.data = &(struct clk_regmap_mux_data){
> +		.offset = HHI_NAND_CLK_CNTL,
> +		.mask = 0x7,
> +		.shift = 9,
> +		.flags = CLK_MUX_ROUND_CLOSEST,

Maybe you have seen it already, but there was a problem with this flag, it was
ignored. Fix should land in this cycle.

https://lkml.kernel.org/r/152389589448.51482.15489333464741262913 at swboyd.mtv.cor
p.google.com

> +	},
> +	.hw.init = &(struct clk_init_data){
> +		.name = "nand_clk_sel",
> 

[...]

>  /*
>   * include the CLKID and RESETID that have
> diff --git a/include/dt-bindings/clock/meson8b-clkc.h b/include/dt-bindings/clock/meson8b-clkc.h
> index dea9d46d4fa7..434d7ba63801 100644
> --- a/include/dt-bindings/clock/meson8b-clkc.h
> +++ b/include/dt-bindings/clock/meson8b-clkc.h
> @@ -102,5 +102,8 @@
>  #define CLKID_MPLL0		93
>  #define CLKID_MPLL1		94
>  #define CLKID_MPLL2		95
> +#define CLKID_NAND_SEL		110
> +#define CLKID_NAND_DIV		111

Nitpick: Could put the bindings in separate patch ?
It makes our life easier if intend to push a DT patch using them in this cycle.

Also, do you need to expose the divider and the mux ?

Apart from this, patch looks good to me.

Acked-by: Jerome Brunet <jbrunet at baylibre.com>

> +#define CLKID_NAND_CLK		112
>  
>  #endif /* __MESON8B_CLKC_H */



From jbrunet at baylibre.com  Mon Apr 23 01:52:22 2018
From: jbrunet at baylibre.com (Jerome Brunet)
Date: Mon, 23 Apr 2018 10:52:22 +0200
Subject: [PATCH] clk: meson: add the video decoder clocks
In-Reply-To: <CAHStOZ6-jV9gAvJPfk+JKanoNWmWnYykN-u3HwpY9bgoJb1myQ@mail.gmail.com>
References: <CAHStOZ7m+8xSX=k5k-LwmgZy6Ja4MFwsVjMy-FeoG=2c0rpm2g@mail.gmail.com>
 <1524341993.2601.131.camel@baylibre.com>
 <CAHStOZ6-jV9gAvJPfk+JKanoNWmWnYykN-u3HwpY9bgoJb1myQ@mail.gmail.com>
Message-ID: <1524473542.4026.26.camel@baylibre.com>

On Sun, 2018-04-22 at 09:43 +0200, Maxime Jourdan wrote:
> Hi Neil, J?rome,

Beware, replies should also be plain text. Some mailing list will block your
mail if it is HTML.

Also, please avoid top posting - instead reply inside the orignal mail or after.

> 
> Thanks for the answers, I'll resubmit with proper formatting.
> 
> @J?rome: very valid points. The usage of the clk will indeed be through set_clk_rate on the leaf clock within the driver, so I don't need to expose the mux. If I want the mux automatically selected to provide the nearest target clock, should I keep  CLK_SET_RATE_NO_REPARENT ?
> 

Nope, CLK_SET_RATE_NO_REPARENT tells the clock framework to *keep* the same
parent clock of a clock when it tries to achieve the requested rate. You
actually want the opposite here, so you should drop this flag.

> CLK_IGNORE_UNUSED  doesn't seem like a required property indeed for those clocks.
> 
> Maxime
> 
> 
> 
> 2018-04-21 22:19 GMT+02:00 Jerome Brunet <jbrunet at baylibre.com>:
> > On Sat, 2018-04-21 at 10:18 +0200, Maxime Jourdan wrote:
> > > In preparation for the V4L2 M2M driver, add the clocks for
> > > VDEC_1 and VDEC_HEVC to gxbb.
> > > 
> > > Signed-off-by: Maxime Jourdan <maxi.jourdan at wanadoo.fr>
> > 
> > a few other comments, in addition to what neil pointed out.
> > 
> > > ---
> > >  drivers/clk/meson/gxbb.c              | 112 ++++++++++++++++++++++++++
> > >  drivers/clk/meson/gxbb.h              |   4 +-
> > >  include/dt-bindings/clock/gxbb-clkc.h |   4 +
> > >  3 files changed, 119 insertions(+), 1 deletion(-)
> > > 
> > > diff --git a/drivers/clk/meson/gxbb.c b/drivers/clk/meson/gxbb.c
> > > index b1e4d9557610..f9d7ab9c924e 100644
> > > --- a/drivers/clk/meson/gxbb.c
> > > +++ b/drivers/clk/meson/gxbb.c
> > > @@ -1543,6 +1543,100 @@ static struct clk_regmap gxbb_vapb = {
> > >       },
> > >  };
> > >  
> > > +/* VDEC clocks */
> > > +
> > > +static const char * const gxbb_vdec_parent_names[] = {
> > > +     "fclk_div4", "fclk_div3", "fclk_div5", "fclk_div7"
> > > +};
> > > +
> > > +static struct clk_regmap gxbb_vdec_1_sel = {
> > > +     .data = &(struct clk_regmap_mux_data){
> > > +             .offset = HHI_VDEC_CLK_CNTL,
> > > +             .mask = 0x3,
> > > +             .shift = 9,

.flags = CLK_MUX_ROUND_CLOSEST,

This will tell the clock framework it is allowed to round rate up if it provides
a better/closer result than rounding down. Otherwise a mux always round down
(means select the closest parent which rate is "< requested_rate")

> > > +     },
> > > +     .hw.init = &(struct clk_init_data){
> > > +             .name = "vdec_1_sel",
> > > +             .ops = &clk_regmap_mux_ops,
> > > +             .parent_names = gxbb_vdec_parent_names,
> > > +             .num_parents = ARRAY_SIZE(gxbb_vdec_parent_names),
> > > +             .flags = CLK_SET_RATE_NO_REPARENT,

I would replace this with:

.flags = CLK_SET_RATE_PARENT,

Not strictly necessary here, but it is a good practice when nothing prevents for
using it. It tells the clock framework to propagate the rate request to the
parent clock. It is especially interesting when the input clock can be adjusted.
Here the rate propagation will stop at the fdiv clocks, since they are fixed.

> > 
> > Looks like you are/will be controlling the mux manually from your driver.
> > Any particular reason for doing so ?
> > 
> > Looking at the possible parent, you may as well call clk_set_rate() on the leaf
> > clock with 500Mhz, 666Mhz, etc ... it would accomplish the same thing but :
> > * You would need to get only one clock in your driver
> > * You don't need to manage the topology of the clock tree in your driver, which
> > could be interresting  if your driver ends up supporting more than GXBB.
> > 
> > > +     },
> > > +};
> > > +
> > > +static struct clk_regmap gxbb_vdec_1_div = {
> > > +     .data = &(struct clk_regmap_div_data){
> > > +             .offset = HHI_VDEC_CLK_CNTL,
> > > +             .shift = 0,
> > > +             .width = 7,
> > > +     },
> > > +     .hw.init = &(struct clk_init_data){
> > > +             .name = "vdec_1_div",
> > > +             .ops = &clk_regmap_divider_ops,
> > > +             .parent_names = (const char *[]){ "vdec_1_sel" },
> > > +             .num_parents = 1,
> > > +             .flags = CLK_SET_RATE_PARENT,
> > > +     },
> > > +};
> > > +
> > > +static struct clk_regmap gxbb_vdec_1 = {
> > > +     .data = &(struct clk_regmap_gate_data){
> > > +             .offset = HHI_VDEC_CLK_CNTL,
> > > +             .bit_idx = 8,
> > > +     },
> > > +     .hw.init = &(struct clk_init_data) {
> > > +             .name = "vdec_1",
> > > +             .ops = &clk_regmap_gate_ops,
> > > +             .parent_names = (const char *[]){ "vdec_1_div" },
> > > +             .num_parents = 1,
> > > +             .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
> > 
> > Any particular reason for using CLK_IGNORE_UNUSED ?
> > 
> > You should only need CLK_IGNORE_UNUSED when the clock is left on by the
> > bootloader, and you need it stay that way until the driver load.
> > 
> > It allows to skip the clk_disable_unused() mechanism of CCF but I don't think
> > the video decoder should require this, unless I missed something.
> > 
> > > +     },
> > > +};
> > > +
> > > +static struct clk_regmap gxbb_vdec_hevc_sel = {
> > > +     .data = &(struct clk_regmap_mux_data){
> > > +             .offset = HHI_VDEC2_CLK_CNTL,
> > > +             .mask = 0x3,
> > > +             .shift = 25,
> > > +     },
> > > +     .hw.init = &(struct clk_init_data){
> > > +             .name = "vdec_hevc_sel",
> > > +             .ops = &clk_regmap_mux_ops,
> > > +             .parent_names = gxbb_vdec_parent_names,
> > > +             .num_parents = ARRAY_SIZE(gxbb_vdec_parent_names),
> > > +             .flags = CLK_SET_RATE_NO_REPARENT,
> > > +     },
> > > +};
> > > +
> > > +static struct clk_regmap gxbb_vdec_hevc_div = {
> > > +     .data = &(struct clk_regmap_div_data){
> > > +             .offset = HHI_VDEC2_CLK_CNTL,
> > > +             .shift = 16,
> > > +             .width = 7,
> > > +     },
> > > +     .hw.init = &(struct clk_init_data){
> > > +             .name = "vdec_hevc_div",
> > > +             .ops = &clk_regmap_divider_ops,
> > > +             .parent_names = (const char *[]){ "vdec_hevc_sel" },
> > > +             .num_parents = 1,
> > > +             .flags = CLK_SET_RATE_PARENT,
> > > +     },
> > > +};
> > > +
> > > +static struct clk_regmap gxbb_vdec_hevc = {
> > > +     .data = &(struct clk_regmap_gate_data){
> > > +             .offset = HHI_VDEC2_CLK_CNTL,
> > > +             .bit_idx = 24,
> > > +     },
> > > +     .hw.init = &(struct clk_init_data) {
> > > +             .name = "vdec_hevc",
> > > +             .ops = &clk_regmap_gate_ops,
> > > +             .parent_names = (const char *[]){ "vdec_hevc_div" },
> > > +             .num_parents = 1,
> > > +             .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
> > > +     },
> > > +};
> > > +
> > >  /* Everything Else (EE) domain gates */
> > >  static MESON_GATE(gxbb_ddr, HHI_GCLK_MPEG0, 0);
> > >  static MESON_GATE(gxbb_dos, HHI_GCLK_MPEG0, 1);
> > > @@ -1786,6 +1880,12 @@ static struct clk_hw_onecell_data gxbb_hw_onecell_data = {
> > >               [CLKID_FCLK_DIV4_DIV]       = &gxbb_fclk_div4_div.hw,
> > >               [CLKID_FCLK_DIV5_DIV]       = &gxbb_fclk_div5_div.hw,
> > >               [CLKID_FCLK_DIV7_DIV]       = &gxbb_fclk_div7_div.hw,
> > > +             [CLKID_VDEC_1_SEL]          = &gxbb_vdec_1_sel.hw,
> > > +             [CLKID_VDEC_1_DIV]          = &gxbb_vdec_1_div.hw,
> > > +             [CLKID_VDEC_1]              = &gxbb_vdec_1.hw,
> > > +             [CLKID_VDEC_HEVC_SEL]       = &gxbb_vdec_hevc_sel.hw,
> > > +             [CLKID_VDEC_HEVC_DIV]       = &gxbb_vdec_hevc_div.hw,
> > > +             [CLKID_VDEC_HEVC]           = &gxbb_vdec_hevc.hw,
> > >               [NR_CLKS]                   = NULL,
> > >       },
> > >       .num = NR_CLKS,
> > > @@ -1942,6 +2042,12 @@ static struct clk_hw_onecell_data gxl_hw_onecell_data = {
> > >               [CLKID_FCLK_DIV4_DIV]       = &gxbb_fclk_div4_div.hw,
> > >               [CLKID_FCLK_DIV5_DIV]       = &gxbb_fclk_div5_div.hw,
> > >               [CLKID_FCLK_DIV7_DIV]       = &gxbb_fclk_div7_div.hw,
> > > +             [CLKID_VDEC_1_SEL]          = &gxbb_vdec_1_sel.hw,
> > > +             [CLKID_VDEC_1_DIV]          = &gxbb_vdec_1_div.hw,
> > > +             [CLKID_VDEC_1]              = &gxbb_vdec_1.hw,
> > > +             [CLKID_VDEC_HEVC_SEL]       = &gxbb_vdec_hevc_sel.hw,
> > > +             [CLKID_VDEC_HEVC_DIV]       = &gxbb_vdec_hevc_div.hw,
> > > +             [CLKID_VDEC_HEVC]           = &gxbb_vdec_hevc.hw,
> > >               [NR_CLKS]                   = NULL,
> > >       },
> > >       .num = NR_CLKS,
> > > @@ -2100,6 +2206,12 @@ static struct clk_regmap *const gx_clk_regmaps[] = {
> > >       &gxbb_fclk_div4,
> > >       &gxbb_fclk_div5,
> > >       &gxbb_fclk_div7,
> > > +     &gxbb_vdec_1_sel,
> > > +     &gxbb_vdec_1_div,
> > > +     &gxbb_vdec_1,
> > > +     &gxbb_vdec_hevc_sel,
> > > +     &gxbb_vdec_hevc_div,
> > > +     &gxbb_vdec_hevc,
> > >  };
> > >  
> > >  struct clkc_data {
> > > diff --git a/drivers/clk/meson/gxbb.h b/drivers/clk/meson/gxbb.h
> > > index 9febf3f03739..ae21d235355a 100644
> > > --- a/drivers/clk/meson/gxbb.h
> > > +++ b/drivers/clk/meson/gxbb.h
> > > @@ -204,8 +204,10 @@
> > >  #define CLKID_FCLK_DIV4_DIV    148
> > >  #define CLKID_FCLK_DIV5_DIV    149
> > >  #define CLKID_FCLK_DIV7_DIV    150
> > > +#define CLKID_VDEC_1_DIV       152
> > > +#define CLKID_VDEC_HEVC_DIV    155
> > >  
> > > -#define NR_CLKS                        151
> > > +#define NR_CLKS                        157
> > >  
> > 
> > We prefer to get the DT binding part in a separate patch, it makes the platform
> > maintainer's life easier.
> > 
> > >  /* include the CLKIDs that have been made part of the DT binding */
> > >  #include <dt-bindings/clock/gxbb-clkc.h>
> > > diff --git a/include/dt-bindings/clock/gxbb-clkc.h b/include/dt-bindings/clock/gxbb-clkc.h
> > > index 8ba99a5e3fd3..ae7f6be747e4 100644
> > > --- a/include/dt-bindings/clock/gxbb-clkc.h
> > > +++ b/include/dt-bindings/clock/gxbb-clkc.h
> > > @@ -125,5 +125,9 @@
> > >  #define CLKID_VAPB_1         138
> > >  #define CLKID_VAPB_SEL               139
> > >  #define CLKID_VAPB           140
> > > +#define CLKID_VDEC_1_SEL     151
> > > +#define CLKID_VDEC_1         153
> > > +#define CLKID_VDEC_HEVC_SEL  154
> > > +#define CLKID_VDEC_HEVC      156
> > >  
> > >  #endif /* __GXBB_CLKC_H */
> > > -- 
> > > 2.17.0
> > > 
> > > 
> > 
> > --
> > To unsubscribe from this list: send the line "unsubscribe linux-clk" in
> > the body of a message to majordomo at vger.kernel.org
> > More majordomo info at  http://vger.kernel.org/majordomo-info.html
> 
> 



From jbrunet at baylibre.com  Mon Apr 23 05:41:49 2018
From: jbrunet at baylibre.com (Jerome Brunet)
Date: Mon, 23 Apr 2018 14:41:49 +0200
Subject: [PATCH v2 3/3] nvmem: meson-efuse: add write support
In-Reply-To: <20180423124149.3077-1-jbrunet@baylibre.com>
References: <20180423124149.3077-1-jbrunet@baylibre.com>
Message-ID: <20180423124149.3077-4-jbrunet@baylibre.com>

Add write support to the meson-gx efuse driver.
Beware, this efuse is one time programmable !

Reviewed-by: Kevin Hilman <khilman at baylibre.com>
Signed-off-by: Jerome Brunet <jbrunet at baylibre.com>
---
 drivers/nvmem/meson-efuse.c | 9 ++++++++-
 1 file changed, 8 insertions(+), 1 deletion(-)

diff --git a/drivers/nvmem/meson-efuse.c b/drivers/nvmem/meson-efuse.c
index 4623249dfd87..d769840d1e18 100644
--- a/drivers/nvmem/meson-efuse.c
+++ b/drivers/nvmem/meson-efuse.c
@@ -28,6 +28,13 @@ static int meson_efuse_read(void *context, unsigned int offset,
 				  bytes, 0, 0, 0);
 }
 
+static int meson_efuse_write(void *context, unsigned int offset,
+			     void *val, size_t bytes)
+{
+	return meson_sm_call_write((u8 *)val, bytes, SM_EFUSE_WRITE, offset,
+				   bytes, 0, 0, 0);
+}
+
 static const struct of_device_id meson_efuse_match[] = {
 	{ .compatible = "amlogic,meson-gxbb-efuse", },
 	{ /* sentinel */ },
@@ -52,8 +59,8 @@ static int meson_efuse_probe(struct platform_device *pdev)
 	econfig->name = dev_name(dev);
 	econfig->stride = 1;
 	econfig->word_size = 1;
-	econfig->read_only = true;
 	econfig->reg_read = meson_efuse_read;
+	econfig->reg_write = meson_efuse_write;
 	econfig->size = size;
 
 	nvmem = devm_nvmem_register(&pdev->dev, econfig);
-- 
2.14.3



From jbrunet at baylibre.com  Mon Apr 23 05:41:46 2018
From: jbrunet at baylibre.com (Jerome Brunet)
Date: Mon, 23 Apr 2018 14:41:46 +0200
Subject: [PATCH v2 0/3] nvmem: meson-efuse: add write support
Message-ID: <20180423124149.3077-1-jbrunet@baylibre.com>

This changeset adds write support to meson efuse driver.
The first patch just changes the way the nvmem data are allocated w/o
any functional changes. The second patches actually adds write support.

The memory being an OTP, it is safer if it remains read-only by default,
which is why I also submitted this DT patch [0]. It has now been merged by
Kevin.

If a user knows what he is doing, it should be easy to remove the
read-only property from the board DT. This can be done in u-boot, before
starting linux:

 > fdt rm /efuse read-only

Tested on the gxl libretech-cc

Changes since v1 [1]:
 - Remove un-necessary code in callbacks
 - Rebase on v4.17-rc1

[0]: https://lkml.kernel.org/r/20180316145021.8517-1-jbrunet at baylibre.com
[1]: https://lkml.kernel.org/r/20180316150113.9779-1-jbrunet at baylibre.com

Jerome Brunet (3):
  nvmem: meson-efuse: remove econfig global
  nvmem: meson-efuse: simplify read callback
  nvmem: meson-efuse: add write support

 drivers/nvmem/meson-efuse.c | 41 ++++++++++++++++++++++-------------------
 1 file changed, 22 insertions(+), 19 deletions(-)

-- 
2.14.3



From jbrunet at baylibre.com  Mon Apr 23 05:41:48 2018
From: jbrunet at baylibre.com (Jerome Brunet)
Date: Mon, 23 Apr 2018 14:41:48 +0200
Subject: [PATCH v2 2/3] nvmem: meson-efuse: simplify read callback
In-Reply-To: <20180423124149.3077-1-jbrunet@baylibre.com>
References: <20180423124149.3077-1-jbrunet@baylibre.com>
Message-ID: <20180423124149.3077-3-jbrunet@baylibre.com>

Most of the code and variables in the read callback is not necessary.
Keep only what is required.

Signed-off-by: Jerome Brunet <jbrunet at baylibre.com>
---
 drivers/nvmem/meson-efuse.c | 11 ++---------
 1 file changed, 2 insertions(+), 9 deletions(-)

diff --git a/drivers/nvmem/meson-efuse.c b/drivers/nvmem/meson-efuse.c
index 2df9b0094f45..4623249dfd87 100644
--- a/drivers/nvmem/meson-efuse.c
+++ b/drivers/nvmem/meson-efuse.c
@@ -24,15 +24,8 @@
 static int meson_efuse_read(void *context, unsigned int offset,
 			    void *val, size_t bytes)
 {
-	u8 *buf = val;
-	int ret;
-
-	ret = meson_sm_call_read(buf, bytes, SM_EFUSE_READ, offset,
-				 bytes, 0, 0, 0);
-	if (ret < 0)
-		return ret;
-
-	return 0;
+	return meson_sm_call_read((u8 *)val, bytes, SM_EFUSE_READ, offset,
+				  bytes, 0, 0, 0);
 }
 
 static const struct of_device_id meson_efuse_match[] = {
-- 
2.14.3



From jbrunet at baylibre.com  Mon Apr 23 05:41:47 2018
From: jbrunet at baylibre.com (Jerome Brunet)
Date: Mon, 23 Apr 2018 14:41:47 +0200
Subject: [PATCH v2 1/3] nvmem: meson-efuse: remove econfig global
In-Reply-To: <20180423124149.3077-1-jbrunet@baylibre.com>
References: <20180423124149.3077-1-jbrunet@baylibre.com>
Message-ID: <20180423124149.3077-2-jbrunet@baylibre.com>

Having a global structure holding a reference to the device
structure is not very nice. Allocate the econfig instead and fill
the nvmem information as before

Reviewed-by: Kevin Hilman <khilman at baylibre.com>
Signed-off-by: Jerome Brunet <jbrunet at baylibre.com>
---
 drivers/nvmem/meson-efuse.c | 25 ++++++++++++++-----------
 1 file changed, 14 insertions(+), 11 deletions(-)

diff --git a/drivers/nvmem/meson-efuse.c b/drivers/nvmem/meson-efuse.c
index 71823d1403c5..2df9b0094f45 100644
--- a/drivers/nvmem/meson-efuse.c
+++ b/drivers/nvmem/meson-efuse.c
@@ -35,13 +35,6 @@ static int meson_efuse_read(void *context, unsigned int offset,
 	return 0;
 }
 
-static struct nvmem_config econfig = {
-	.name = "meson-efuse",
-	.stride = 1,
-	.word_size = 1,
-	.read_only = true,
-};
-
 static const struct of_device_id meson_efuse_match[] = {
 	{ .compatible = "amlogic,meson-gxbb-efuse", },
 	{ /* sentinel */ },
@@ -50,17 +43,27 @@ MODULE_DEVICE_TABLE(of, meson_efuse_match);
 
 static int meson_efuse_probe(struct platform_device *pdev)
 {
+	struct device *dev = &pdev->dev;
 	struct nvmem_device *nvmem;
+	struct nvmem_config *econfig;
 	unsigned int size;
 
 	if (meson_sm_call(SM_EFUSE_USER_MAX, &size, 0, 0, 0, 0, 0) < 0)
 		return -EINVAL;
 
-	econfig.dev = &pdev->dev;
-	econfig.reg_read = meson_efuse_read;
-	econfig.size = size;
+	econfig = devm_kzalloc(dev, sizeof(*econfig), GFP_KERNEL);
+	if (!econfig)
+		return -ENOMEM;
+
+	econfig->dev = dev;
+	econfig->name = dev_name(dev);
+	econfig->stride = 1;
+	econfig->word_size = 1;
+	econfig->read_only = true;
+	econfig->reg_read = meson_efuse_read;
+	econfig->size = size;
 
-	nvmem = devm_nvmem_register(&pdev->dev, &econfig);
+	nvmem = devm_nvmem_register(&pdev->dev, econfig);
 
 	return PTR_ERR_OR_ZERO(nvmem);
 }
-- 
2.14.3



From narmstrong at baylibre.com  Mon Apr 23 07:19:23 2018
From: narmstrong at baylibre.com (Neil Armstrong)
Date: Mon, 23 Apr 2018 16:19:23 +0200
Subject: [PATCH u-boot] adc: add Amlogic Meson SAR ADC driver
Message-ID: <1524493163-20509-1-git-send-email-narmstrong@baylibre.com>

This patch adds the driver for the Amlogic Meson Successive Approximation
Register (SAR) A/D Converter based on the Linux IIO driver thanks to the
great work of Martin Blumenstingl.
The driver has been adapted to U-Boot and the ADC UClass.

This patch depends on the regmap "regmap: add regmap_update_bits() helper"
patch and has been tested using the newly introducted "adc" CLI command
in the "cmd: add ADC cli commands" patch.

Signed-off-by: Neil Armstrong <narmstrong at baylibre.com>
---
 drivers/adc/Kconfig        |  10 +
 drivers/adc/Makefile       |   1 +
 drivers/adc/meson-saradc.c | 724 +++++++++++++++++++++++++++++++++++++++++++++
 3 files changed, 735 insertions(+)
 create mode 100644 drivers/adc/meson-saradc.c

diff --git a/drivers/adc/Kconfig b/drivers/adc/Kconfig
index 8094420..93e27f1 100644
--- a/drivers/adc/Kconfig
+++ b/drivers/adc/Kconfig
@@ -29,6 +29,16 @@ config ADC_SANDBOX
 	  - 16-bit resolution
 	  - single and multi-channel conversion mode
 
+config SARADC_MESON
+	bool "Enable Amlogic Meson SARADC driver"
+	imply REGMAP
+	help
+	  This enables driver for Amlogic Meson SARADC.
+	  It provides:
+	  - 8 analog input channels
+	  - 1O or 12 bits resolution
+	  - Up to 1MSPS of sample rate
+
 config SARADC_ROCKCHIP
 	bool "Enable Rockchip SARADC driver"
 	help
diff --git a/drivers/adc/Makefile b/drivers/adc/Makefile
index 4b5aa69..95c93d4 100644
--- a/drivers/adc/Makefile
+++ b/drivers/adc/Makefile
@@ -9,3 +9,4 @@ obj-$(CONFIG_ADC) += adc-uclass.o
 obj-$(CONFIG_ADC_EXYNOS) += exynos-adc.o
 obj-$(CONFIG_ADC_SANDBOX) += sandbox.o
 obj-$(CONFIG_SARADC_ROCKCHIP) += rockchip-saradc.o
+obj-$(CONFIG_SARADC_MESON) += meson-saradc.o
diff --git a/drivers/adc/meson-saradc.c b/drivers/adc/meson-saradc.c
new file mode 100644
index 0000000..0df6f43
--- /dev/null
+++ b/drivers/adc/meson-saradc.c
@@ -0,0 +1,724 @@
+/*
+ * Copyright (C) 2017 Martin Blumenstingl <martin.blumenstingl at googlemail.com>
+ * Copyright (C) 2018 BayLibre, SAS
+ * Author: Neil Armstrong <narmstrong at baylibre.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ *
+ * Amlogic Meson Successive Approximation Register (SAR) A/D Converter
+ */
+
+#include <common.h>
+#include <adc.h>
+#include <clk.h>
+#include <dm.h>
+#include <regmap.h>
+#include <errno.h>
+#include <asm/io.h>
+#include <linux/math64.h>
+#include <linux/bitfield.h>
+
+#define MESON_SAR_ADC_REG0					0x00
+	#define MESON_SAR_ADC_REG0_PANEL_DETECT			BIT(31)
+	#define MESON_SAR_ADC_REG0_BUSY_MASK			GENMASK(30, 28)
+	#define MESON_SAR_ADC_REG0_DELTA_BUSY			BIT(30)
+	#define MESON_SAR_ADC_REG0_AVG_BUSY			BIT(29)
+	#define MESON_SAR_ADC_REG0_SAMPLE_BUSY			BIT(28)
+	#define MESON_SAR_ADC_REG0_FIFO_FULL			BIT(27)
+	#define MESON_SAR_ADC_REG0_FIFO_EMPTY			BIT(26)
+	#define MESON_SAR_ADC_REG0_FIFO_COUNT_MASK		GENMASK(25, 21)
+	#define MESON_SAR_ADC_REG0_ADC_BIAS_CTRL_MASK		GENMASK(20, 19)
+	#define MESON_SAR_ADC_REG0_CURR_CHAN_ID_MASK		GENMASK(18, 16)
+	#define MESON_SAR_ADC_REG0_ADC_TEMP_SEN_SEL		BIT(15)
+	#define MESON_SAR_ADC_REG0_SAMPLING_STOP		BIT(14)
+	#define MESON_SAR_ADC_REG0_CHAN_DELTA_EN_MASK		GENMASK(13, 12)
+	#define MESON_SAR_ADC_REG0_DETECT_IRQ_POL		BIT(10)
+	#define MESON_SAR_ADC_REG0_DETECT_IRQ_EN		BIT(9)
+	#define MESON_SAR_ADC_REG0_FIFO_CNT_IRQ_MASK		GENMASK(8, 4)
+	#define MESON_SAR_ADC_REG0_FIFO_IRQ_EN			BIT(3)
+	#define MESON_SAR_ADC_REG0_SAMPLING_START		BIT(2)
+	#define MESON_SAR_ADC_REG0_CONTINUOUS_EN		BIT(1)
+	#define MESON_SAR_ADC_REG0_SAMPLE_ENGINE_ENABLE		BIT(0)
+
+#define MESON_SAR_ADC_CHAN_LIST					0x04
+	#define MESON_SAR_ADC_CHAN_LIST_MAX_INDEX_MASK		GENMASK(26, 24)
+	#define MESON_SAR_ADC_CHAN_LIST_ENTRY_MASK(_chan)	\
+					(GENMASK(2, 0) << ((_chan) * 3))
+
+#define MESON_SAR_ADC_AVG_CNTL					0x08
+	#define MESON_SAR_ADC_AVG_CNTL_AVG_MODE_SHIFT(_chan)	\
+					(16 + ((_chan) * 2))
+	#define MESON_SAR_ADC_AVG_CNTL_AVG_MODE_MASK(_chan)	\
+					(GENMASK(17, 16) << ((_chan) * 2))
+	#define MESON_SAR_ADC_AVG_CNTL_NUM_SAMPLES_SHIFT(_chan)	\
+					(0 + ((_chan) * 2))
+	#define MESON_SAR_ADC_AVG_CNTL_NUM_SAMPLES_MASK(_chan)	\
+					(GENMASK(1, 0) << ((_chan) * 2))
+
+#define MESON_SAR_ADC_REG3					0x0c
+	#define MESON_SAR_ADC_REG3_CNTL_USE_SC_DLY		BIT(31)
+	#define MESON_SAR_ADC_REG3_CLK_EN			BIT(30)
+	#define MESON_SAR_ADC_REG3_BL30_INITIALIZED		BIT(28)
+	#define MESON_SAR_ADC_REG3_CTRL_CONT_RING_COUNTER_EN	BIT(27)
+	#define MESON_SAR_ADC_REG3_CTRL_SAMPLING_CLOCK_PHASE	BIT(26)
+	#define MESON_SAR_ADC_REG3_CTRL_CHAN7_MUX_SEL_MASK	GENMASK(25, 23)
+	#define MESON_SAR_ADC_REG3_DETECT_EN			BIT(22)
+	#define MESON_SAR_ADC_REG3_ADC_EN			BIT(21)
+	#define MESON_SAR_ADC_REG3_PANEL_DETECT_COUNT_MASK	GENMASK(20, 18)
+	#define MESON_SAR_ADC_REG3_PANEL_DETECT_FILTER_TB_MASK	GENMASK(17, 16)
+	#define MESON_SAR_ADC_REG3_ADC_CLK_DIV_SHIFT		10
+	#define MESON_SAR_ADC_REG3_ADC_CLK_DIV_WIDTH		5
+	#define MESON_SAR_ADC_REG3_BLOCK_DLY_SEL_MASK		GENMASK(9, 8)
+	#define MESON_SAR_ADC_REG3_BLOCK_DLY_MASK		GENMASK(7, 0)
+
+#define MESON_SAR_ADC_DELAY					0x10
+	#define MESON_SAR_ADC_DELAY_INPUT_DLY_SEL_MASK		GENMASK(25, 24)
+	#define MESON_SAR_ADC_DELAY_BL30_BUSY			BIT(15)
+	#define MESON_SAR_ADC_DELAY_KERNEL_BUSY			BIT(14)
+	#define MESON_SAR_ADC_DELAY_INPUT_DLY_CNT_MASK		GENMASK(23, 16)
+	#define MESON_SAR_ADC_DELAY_SAMPLE_DLY_SEL_MASK		GENMASK(9, 8)
+	#define MESON_SAR_ADC_DELAY_SAMPLE_DLY_CNT_MASK		GENMASK(7, 0)
+
+#define MESON_SAR_ADC_LAST_RD					0x14
+	#define MESON_SAR_ADC_LAST_RD_LAST_CHANNEL1_MASK	GENMASK(23, 16)
+	#define MESON_SAR_ADC_LAST_RD_LAST_CHANNEL0_MASK	GENMASK(9, 0)
+
+#define MESON_SAR_ADC_FIFO_RD					0x18
+	#define MESON_SAR_ADC_FIFO_RD_CHAN_ID_MASK		GENMASK(14, 12)
+	#define MESON_SAR_ADC_FIFO_RD_SAMPLE_VALUE_MASK		GENMASK(11, 0)
+
+#define MESON_SAR_ADC_AUX_SW					0x1c
+	#define MESON_SAR_ADC_AUX_SW_MUX_SEL_CHAN_SHIFT(_chan)	\
+					(8 + (((_chan) - 2) * 3))
+	#define MESON_SAR_ADC_AUX_SW_VREF_P_MUX			BIT(6)
+	#define MESON_SAR_ADC_AUX_SW_VREF_N_MUX			BIT(5)
+	#define MESON_SAR_ADC_AUX_SW_MODE_SEL			BIT(4)
+	#define MESON_SAR_ADC_AUX_SW_YP_DRIVE_SW		BIT(3)
+	#define MESON_SAR_ADC_AUX_SW_XP_DRIVE_SW		BIT(2)
+	#define MESON_SAR_ADC_AUX_SW_YM_DRIVE_SW		BIT(1)
+	#define MESON_SAR_ADC_AUX_SW_XM_DRIVE_SW		BIT(0)
+
+#define MESON_SAR_ADC_CHAN_10_SW				0x20
+	#define MESON_SAR_ADC_CHAN_10_SW_CHAN1_MUX_SEL_MASK	GENMASK(25, 23)
+	#define MESON_SAR_ADC_CHAN_10_SW_CHAN1_VREF_P_MUX	BIT(22)
+	#define MESON_SAR_ADC_CHAN_10_SW_CHAN1_VREF_N_MUX	BIT(21)
+	#define MESON_SAR_ADC_CHAN_10_SW_CHAN1_MODE_SEL		BIT(20)
+	#define MESON_SAR_ADC_CHAN_10_SW_CHAN1_YP_DRIVE_SW	BIT(19)
+	#define MESON_SAR_ADC_CHAN_10_SW_CHAN1_XP_DRIVE_SW	BIT(18)
+	#define MESON_SAR_ADC_CHAN_10_SW_CHAN1_YM_DRIVE_SW	BIT(17)
+	#define MESON_SAR_ADC_CHAN_10_SW_CHAN1_XM_DRIVE_SW	BIT(16)
+	#define MESON_SAR_ADC_CHAN_10_SW_CHAN0_MUX_SEL_MASK	GENMASK(9, 7)
+	#define MESON_SAR_ADC_CHAN_10_SW_CHAN0_VREF_P_MUX	BIT(6)
+	#define MESON_SAR_ADC_CHAN_10_SW_CHAN0_VREF_N_MUX	BIT(5)
+	#define MESON_SAR_ADC_CHAN_10_SW_CHAN0_MODE_SEL		BIT(4)
+	#define MESON_SAR_ADC_CHAN_10_SW_CHAN0_YP_DRIVE_SW	BIT(3)
+	#define MESON_SAR_ADC_CHAN_10_SW_CHAN0_XP_DRIVE_SW	BIT(2)
+	#define MESON_SAR_ADC_CHAN_10_SW_CHAN0_YM_DRIVE_SW	BIT(1)
+	#define MESON_SAR_ADC_CHAN_10_SW_CHAN0_XM_DRIVE_SW	BIT(0)
+
+#define MESON_SAR_ADC_DETECT_IDLE_SW				0x24
+	#define MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_SW_EN	BIT(26)
+	#define MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_MUX_MASK	GENMASK(25, 23)
+	#define MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_VREF_P_MUX	BIT(22)
+	#define MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_VREF_N_MUX	BIT(21)
+	#define MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_MODE_SEL	BIT(20)
+	#define MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_YP_DRIVE_SW	BIT(19)
+	#define MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_XP_DRIVE_SW	BIT(18)
+	#define MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_YM_DRIVE_SW	BIT(17)
+	#define MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_XM_DRIVE_SW	BIT(16)
+	#define MESON_SAR_ADC_DETECT_IDLE_SW_IDLE_MUX_SEL_MASK	GENMASK(9, 7)
+	#define MESON_SAR_ADC_DETECT_IDLE_SW_IDLE_VREF_P_MUX	BIT(6)
+	#define MESON_SAR_ADC_DETECT_IDLE_SW_IDLE_VREF_N_MUX	BIT(5)
+	#define MESON_SAR_ADC_DETECT_IDLE_SW_IDLE_MODE_SEL	BIT(4)
+	#define MESON_SAR_ADC_DETECT_IDLE_SW_IDLE_YP_DRIVE_SW	BIT(3)
+	#define MESON_SAR_ADC_DETECT_IDLE_SW_IDLE_XP_DRIVE_SW	BIT(2)
+	#define MESON_SAR_ADC_DETECT_IDLE_SW_IDLE_YM_DRIVE_SW	BIT(1)
+	#define MESON_SAR_ADC_DETECT_IDLE_SW_IDLE_XM_DRIVE_SW	BIT(0)
+
+#define MESON_SAR_ADC_DELTA_10					0x28
+	#define MESON_SAR_ADC_DELTA_10_TEMP_SEL			BIT(27)
+	#define MESON_SAR_ADC_DELTA_10_TS_REVE1			BIT(26)
+	#define MESON_SAR_ADC_DELTA_10_CHAN1_DELTA_VALUE_MASK	GENMASK(25, 16)
+	#define MESON_SAR_ADC_DELTA_10_TS_REVE0			BIT(15)
+	#define MESON_SAR_ADC_DELTA_10_TS_C_SHIFT		11
+	#define MESON_SAR_ADC_DELTA_10_TS_C_MASK		GENMASK(14, 11)
+	#define MESON_SAR_ADC_DELTA_10_TS_VBG_EN		BIT(10)
+	#define MESON_SAR_ADC_DELTA_10_CHAN0_DELTA_VALUE_MASK	GENMASK(9, 0)
+
+/*
+ * NOTE: registers from here are undocumented (the vendor Linux kernel driver
+ * and u-boot source served as reference). These only seem to be relevant on
+ * GXBB and newer.
+ */
+#define MESON_SAR_ADC_REG11					0x2c
+	#define MESON_SAR_ADC_REG11_BANDGAP_EN			BIT(13)
+
+#define MESON_SAR_ADC_REG13					0x34
+	#define MESON_SAR_ADC_REG13_12BIT_CALIBRATION_MASK	GENMASK(13, 8)
+
+#define MESON_SAR_ADC_MAX_FIFO_SIZE				32
+#define MESON_SAR_ADC_TIMEOUT					100 /* ms */
+
+#define NUM_CHANNELS						8
+
+#define MILLION							1000000
+
+struct meson_saradc_data {
+	int				num_bits;
+};
+
+struct meson_saradc_priv {
+	const struct meson_saradc_data	*data;
+	struct regmap			*regmap;
+	struct clk			core_clk;
+	struct clk			adc_clk;
+	bool				initialized;
+	int				active_channel;
+	int				calibbias;
+	int				calibscale;
+};
+
+static unsigned int
+meson_saradc_get_fifo_count(struct meson_saradc_priv *priv)
+{
+	u32 regval;
+
+	regmap_read(priv->regmap, MESON_SAR_ADC_REG0, &regval);
+
+	return FIELD_GET(MESON_SAR_ADC_REG0_FIFO_COUNT_MASK, regval);
+}
+
+static int meson_saradc_lock(struct meson_saradc_priv *priv)
+{
+	uint val, timeout = 10000;
+
+	/* prevent BL30 from using the SAR ADC while we are using it */
+	regmap_update_bits(priv->regmap, MESON_SAR_ADC_DELAY,
+			   MESON_SAR_ADC_DELAY_KERNEL_BUSY,
+			   MESON_SAR_ADC_DELAY_KERNEL_BUSY);
+
+	/*
+	 * wait until BL30 releases it's lock (so we can use the SAR ADC)
+	 */
+	do {
+		udelay(1);
+		regmap_read(priv->regmap, MESON_SAR_ADC_DELAY, &val);
+	} while (val & MESON_SAR_ADC_DELAY_BL30_BUSY && timeout--);
+
+	if (timeout < 0) {
+		printf("Timeout while waiting for BL30 unlock\n");
+		return -ETIMEDOUT;
+	}
+
+	return 0;
+}
+
+static void meson_saradc_unlock(struct meson_saradc_priv *priv)
+{
+	/* allow BL30 to use the SAR ADC again */
+	regmap_update_bits(priv->regmap, MESON_SAR_ADC_DELAY,
+			   MESON_SAR_ADC_DELAY_KERNEL_BUSY, 0);
+}
+
+static void meson_saradc_clear_fifo(struct meson_saradc_priv *priv)
+{
+	unsigned int count, tmp;
+
+	for (count = 0; count < MESON_SAR_ADC_MAX_FIFO_SIZE; count++) {
+		if (!meson_saradc_get_fifo_count(priv))
+			break;
+
+		regmap_read(priv->regmap, MESON_SAR_ADC_FIFO_RD, &tmp);
+	}
+}
+
+static int meson_saradc_calib_val(struct meson_saradc_priv *priv, int val)
+{
+	int tmp;
+
+	/* use val_calib = scale * val_raw + offset calibration function */
+	tmp = div_s64((s64)val * priv->calibscale, MILLION) + priv->calibbias;
+
+	return clamp(tmp, 0, (1 << priv->data->num_bits) - 1);
+}
+
+static int meson_saradc_wait_busy_clear(struct meson_saradc_priv *priv)
+{
+	uint regval, timeout = 10000;
+
+	/*
+	 * NOTE: we need a small delay before reading the status, otherwise
+	 * the sample engine may not have started internally (which would
+	 * seem to us that sampling is already finished).
+	 */
+	do {
+		udelay(1);
+		regmap_read(priv->regmap, MESON_SAR_ADC_REG0, &regval);
+	} while (FIELD_GET(MESON_SAR_ADC_REG0_BUSY_MASK, regval) && timeout--);
+
+	if (timeout < 0)
+		return -ETIMEDOUT;
+
+	return 0;
+}
+
+static int meson_saradc_read_raw_sample(struct meson_saradc_priv *priv,
+					unsigned int channel, uint *val)
+{
+	uint regval, fifo_chan, fifo_val, count;
+	int ret;
+
+	ret = meson_saradc_wait_busy_clear(priv);
+	if (ret)
+		return ret;
+
+	count = meson_saradc_get_fifo_count(priv);
+	if (count != 1) {
+		printf("ADC FIFO has %d element(s) instead of one\n", count);
+		return -EINVAL;
+	}
+
+	regmap_read(priv->regmap, MESON_SAR_ADC_FIFO_RD, &regval);
+	fifo_chan = FIELD_GET(MESON_SAR_ADC_FIFO_RD_CHAN_ID_MASK, regval);
+	if (fifo_chan != channel) {
+		printf("ADC FIFO entry belongs to channel %d instead of %d\n",
+		       fifo_chan, channel);
+		return -EINVAL;
+	}
+
+	fifo_val = FIELD_GET(MESON_SAR_ADC_FIFO_RD_SAMPLE_VALUE_MASK, regval);
+	fifo_val &= GENMASK(priv->data->num_bits - 1, 0);
+	*val = meson_saradc_calib_val(priv, fifo_val);
+
+	return 0;
+}
+
+static void meson_saradc_start_sample_engine(struct meson_saradc_priv *priv)
+{
+	regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG0,
+			   MESON_SAR_ADC_REG0_FIFO_IRQ_EN,
+			   MESON_SAR_ADC_REG0_FIFO_IRQ_EN);
+
+	regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG0,
+			   MESON_SAR_ADC_REG0_SAMPLE_ENGINE_ENABLE,
+			   MESON_SAR_ADC_REG0_SAMPLE_ENGINE_ENABLE);
+
+	regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG0,
+			   MESON_SAR_ADC_REG0_SAMPLING_START,
+			   MESON_SAR_ADC_REG0_SAMPLING_START);
+}
+
+static void meson_saradc_stop_sample_engine(struct meson_saradc_priv *priv)
+{
+	regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG0,
+			   MESON_SAR_ADC_REG0_FIFO_IRQ_EN, 0);
+
+	regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG0,
+			   MESON_SAR_ADC_REG0_SAMPLING_STOP,
+			   MESON_SAR_ADC_REG0_SAMPLING_STOP);
+
+	/* wait until all modules are stopped */
+	meson_saradc_wait_busy_clear(priv);
+
+	regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG0,
+			   MESON_SAR_ADC_REG0_SAMPLE_ENGINE_ENABLE, 0);
+}
+
+enum meson_saradc_avg_mode {
+	NO_AVERAGING = 0x0,
+	MEAN_AVERAGING = 0x1,
+	MEDIAN_AVERAGING = 0x2,
+};
+
+enum meson_saradc_num_samples {
+	ONE_SAMPLE = 0x0,
+	TWO_SAMPLES = 0x1,
+	FOUR_SAMPLES = 0x2,
+	EIGHT_SAMPLES = 0x3,
+};
+
+static void meson_saradc_set_averaging(struct meson_saradc_priv *priv,
+				       unsigned int channel,
+				       enum meson_saradc_avg_mode mode,
+				       enum meson_saradc_num_samples samples)
+{
+	int val;
+
+	val = samples << MESON_SAR_ADC_AVG_CNTL_NUM_SAMPLES_SHIFT(channel);
+	regmap_update_bits(priv->regmap, MESON_SAR_ADC_AVG_CNTL,
+			   MESON_SAR_ADC_AVG_CNTL_NUM_SAMPLES_MASK(channel),
+			   val);
+
+	val = mode << MESON_SAR_ADC_AVG_CNTL_AVG_MODE_SHIFT(channel);
+	regmap_update_bits(priv->regmap, MESON_SAR_ADC_AVG_CNTL,
+			   MESON_SAR_ADC_AVG_CNTL_AVG_MODE_MASK(channel), val);
+}
+
+static void meson_saradc_enable_channel(struct meson_saradc_priv *priv,
+					unsigned int channel)
+{
+	uint regval;
+
+	/*
+	 * the SAR ADC engine allows sampling multiple channels at the same
+	 * time. to keep it simple we're only working with one *internal*
+	 * channel, which starts counting at index 0 (which means: count = 1).
+	 */
+	regval = FIELD_PREP(MESON_SAR_ADC_CHAN_LIST_MAX_INDEX_MASK, 0);
+	regmap_update_bits(priv->regmap, MESON_SAR_ADC_CHAN_LIST,
+			   MESON_SAR_ADC_CHAN_LIST_MAX_INDEX_MASK, regval);
+
+	/* map channel index 0 to the channel which we want to read */
+	regval = FIELD_PREP(MESON_SAR_ADC_CHAN_LIST_ENTRY_MASK(0), channel);
+	regmap_update_bits(priv->regmap, MESON_SAR_ADC_CHAN_LIST,
+			   MESON_SAR_ADC_CHAN_LIST_ENTRY_MASK(0), regval);
+
+	regval = FIELD_PREP(MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_MUX_MASK,
+			    channel);
+	regmap_update_bits(priv->regmap, MESON_SAR_ADC_DETECT_IDLE_SW,
+			   MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_MUX_MASK,
+			   regval);
+
+	regval = FIELD_PREP(MESON_SAR_ADC_DETECT_IDLE_SW_IDLE_MUX_SEL_MASK,
+			    channel);
+	regmap_update_bits(priv->regmap, MESON_SAR_ADC_DETECT_IDLE_SW,
+			   MESON_SAR_ADC_DETECT_IDLE_SW_IDLE_MUX_SEL_MASK,
+			   regval);
+
+	if (channel == 6)
+		regmap_update_bits(priv->regmap, MESON_SAR_ADC_DELTA_10,
+				   MESON_SAR_ADC_DELTA_10_TEMP_SEL, 0);
+}
+
+static int meson_saradc_get_sample(struct meson_saradc_priv *priv,
+				   int chan, uint *val)
+{
+	int ret;
+
+	ret = meson_saradc_lock(priv);
+	if (ret)
+		return ret;
+
+	/* clear the FIFO to make sure we're not reading old values */
+	meson_saradc_clear_fifo(priv);
+
+	meson_saradc_set_averaging(priv, chan, MEAN_AVERAGING, EIGHT_SAMPLES);
+
+	meson_saradc_enable_channel(priv, chan);
+
+	meson_saradc_start_sample_engine(priv);
+	ret = meson_saradc_read_raw_sample(priv, chan, val);
+	meson_saradc_stop_sample_engine(priv);
+
+	meson_saradc_unlock(priv);
+
+	if (ret) {
+		printf("failed to read sample for channel %d: %d\n",
+		       chan, ret);
+		return ret;
+	}
+
+	return 0;
+}
+
+static int meson_saradc_channel_data(struct udevice *dev, int channel,
+				     unsigned int *data)
+{
+	struct meson_saradc_priv *priv = dev_get_priv(dev);
+
+	if (channel != priv->active_channel) {
+		pr_err("Requested channel is not active!");
+		return -EINVAL;
+	}
+
+	return meson_saradc_get_sample(priv, channel, data);
+}
+
+enum meson_saradc_chan7_mux_sel {
+	CHAN7_MUX_VSS = 0x0,
+	CHAN7_MUX_VDD_DIV4 = 0x1,
+	CHAN7_MUX_VDD_DIV2 = 0x2,
+	CHAN7_MUX_VDD_MUL3_DIV4 = 0x3,
+	CHAN7_MUX_VDD = 0x4,
+	CHAN7_MUX_CH7_INPUT = 0x7,
+};
+
+static void meson_saradc_set_chan7_mux(struct meson_saradc_priv *priv,
+				       enum meson_saradc_chan7_mux_sel sel)
+{
+	u32 regval;
+
+	regval = FIELD_PREP(MESON_SAR_ADC_REG3_CTRL_CHAN7_MUX_SEL_MASK, sel);
+	regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG3,
+			   MESON_SAR_ADC_REG3_CTRL_CHAN7_MUX_SEL_MASK, regval);
+
+	udelay(20);
+}
+
+static int meson_saradc_calib(struct meson_saradc_priv *priv)
+{
+	uint nominal0, nominal1, value0, value1;
+	int ret;
+
+	/* use points 25% and 75% for calibration */
+	nominal0 = (1 << priv->data->num_bits) / 4;
+	nominal1 = (1 << priv->data->num_bits) * 3 / 4;
+
+	meson_saradc_set_chan7_mux(priv, CHAN7_MUX_VDD_DIV4);
+	udelay(20);
+	ret = meson_saradc_get_sample(priv, 7, &value0);
+	if (ret < 0)
+		goto out;
+
+	meson_saradc_set_chan7_mux(priv, CHAN7_MUX_VDD_MUL3_DIV4);
+	udelay(20);
+	ret = meson_saradc_get_sample(priv, 7, &value1);
+	if (ret < 0)
+		goto out;
+
+	if (value1 <= value0) {
+		ret = -EINVAL;
+		goto out;
+	}
+
+	priv->calibscale = div_s64((nominal1 - nominal0) * (s64)MILLION,
+				   value1 - value0);
+	priv->calibbias = nominal0 - div_s64((s64)value0 * priv->calibscale,
+					     MILLION);
+	ret = 0;
+out:
+	meson_saradc_set_chan7_mux(priv, CHAN7_MUX_CH7_INPUT);
+
+	return ret;
+}
+
+static int meson_saradc_init(struct meson_saradc_priv *priv)
+{
+	uint regval;
+	int ret, i;
+
+	priv->calibscale = MILLION;
+
+	/*
+	 * make sure we start at CH7 input since the other muxes are only used
+	 * for internal calibration.
+	 */
+	meson_saradc_set_chan7_mux(priv, CHAN7_MUX_CH7_INPUT);
+
+	/*
+	 * leave sampling delay and the input clocks as configured by
+	 * BL30 to make sure BL30 gets the values it expects when
+	 * reading the temperature sensor.
+	 */
+	regmap_read(priv->regmap, MESON_SAR_ADC_REG3, &regval);
+	if (regval & MESON_SAR_ADC_REG3_BL30_INITIALIZED)
+		return 0;
+
+	meson_saradc_stop_sample_engine(priv);
+
+	/* update the channel 6 MUX to select the temperature sensor */
+	regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG0,
+			   MESON_SAR_ADC_REG0_ADC_TEMP_SEN_SEL,
+			   MESON_SAR_ADC_REG0_ADC_TEMP_SEN_SEL);
+
+	/* disable all channels by default */
+	regmap_write(priv->regmap, MESON_SAR_ADC_CHAN_LIST, 0x0);
+
+	regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG3,
+			   MESON_SAR_ADC_REG3_CTRL_SAMPLING_CLOCK_PHASE, 0);
+	regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG3,
+			   MESON_SAR_ADC_REG3_CNTL_USE_SC_DLY,
+			   MESON_SAR_ADC_REG3_CNTL_USE_SC_DLY);
+
+	/* delay between two samples = (10+1) * 1uS */
+	regmap_update_bits(priv->regmap, MESON_SAR_ADC_DELAY,
+			   MESON_SAR_ADC_DELAY_INPUT_DLY_CNT_MASK,
+			   FIELD_PREP(MESON_SAR_ADC_DELAY_SAMPLE_DLY_CNT_MASK,
+				      10));
+	regmap_update_bits(priv->regmap, MESON_SAR_ADC_DELAY,
+			   MESON_SAR_ADC_DELAY_SAMPLE_DLY_SEL_MASK,
+			   FIELD_PREP(MESON_SAR_ADC_DELAY_SAMPLE_DLY_SEL_MASK,
+				      0));
+
+	/* delay between two samples = (10+1) * 1uS */
+	regmap_update_bits(priv->regmap, MESON_SAR_ADC_DELAY,
+			   MESON_SAR_ADC_DELAY_INPUT_DLY_CNT_MASK,
+			   FIELD_PREP(MESON_SAR_ADC_DELAY_INPUT_DLY_CNT_MASK,
+				      10));
+	regmap_update_bits(priv->regmap, MESON_SAR_ADC_DELAY,
+			   MESON_SAR_ADC_DELAY_INPUT_DLY_SEL_MASK,
+			   FIELD_PREP(MESON_SAR_ADC_DELAY_INPUT_DLY_SEL_MASK,
+				      1));
+
+	/*
+	 * set up the input channel muxes in MESON_SAR_ADC_CHAN_10_SW
+	 * (0 = SAR_ADC_CH0, 1 = SAR_ADC_CH1)
+	 */
+	regval = FIELD_PREP(MESON_SAR_ADC_CHAN_10_SW_CHAN0_MUX_SEL_MASK, 0);
+	regmap_update_bits(priv->regmap, MESON_SAR_ADC_CHAN_10_SW,
+			   MESON_SAR_ADC_CHAN_10_SW_CHAN0_MUX_SEL_MASK,
+			   regval);
+	regval = FIELD_PREP(MESON_SAR_ADC_CHAN_10_SW_CHAN1_MUX_SEL_MASK, 1);
+	regmap_update_bits(priv->regmap, MESON_SAR_ADC_CHAN_10_SW,
+			   MESON_SAR_ADC_CHAN_10_SW_CHAN1_MUX_SEL_MASK,
+			   regval);
+
+	/*
+	 * set up the input channel muxes in MESON_SAR_ADC_AUX_SW
+	 * (2 = SAR_ADC_CH2, 3 = SAR_ADC_CH3, ...) and enable
+	 * MESON_SAR_ADC_AUX_SW_YP_DRIVE_SW and
+	 * MESON_SAR_ADC_AUX_SW_XP_DRIVE_SW like the vendor driver.
+	 */
+	regval = 0;
+	for (i = 2; i <= 7; i++)
+		regval |= i << MESON_SAR_ADC_AUX_SW_MUX_SEL_CHAN_SHIFT(i);
+	regval |= MESON_SAR_ADC_AUX_SW_YP_DRIVE_SW;
+	regval |= MESON_SAR_ADC_AUX_SW_XP_DRIVE_SW;
+	regmap_write(priv->regmap, MESON_SAR_ADC_AUX_SW, regval);
+
+	ret = meson_saradc_lock(priv);
+	if (ret)
+		return ret;
+
+#if CONFIG_IS_ENABLED(CLK)
+	ret = clk_enable(&priv->core_clk);
+	if (ret)
+		return ret;
+#endif
+
+	regval = FIELD_PREP(MESON_SAR_ADC_REG0_FIFO_CNT_IRQ_MASK, 1);
+	regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG0,
+			   MESON_SAR_ADC_REG0_FIFO_CNT_IRQ_MASK, regval);
+
+	regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG11,
+			   MESON_SAR_ADC_REG11_BANDGAP_EN,
+			   MESON_SAR_ADC_REG11_BANDGAP_EN);
+
+	regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG3,
+			   MESON_SAR_ADC_REG3_ADC_EN,
+			   MESON_SAR_ADC_REG3_ADC_EN);
+
+	udelay(5);
+
+#if CONFIG_IS_ENABLED(CLK)
+	ret = clk_enable(&priv->adc_clk);
+	if (ret)
+		return ret;
+#endif
+
+	meson_saradc_unlock(priv);
+
+	ret = meson_saradc_calib(priv);
+	if (ret) {
+		printf("calibration failed\n");
+		return -EIO;
+	}
+
+	return 0;
+}
+
+static int meson_saradc_start_channel(struct udevice *dev, int channel)
+{
+	struct meson_saradc_priv *priv = dev_get_priv(dev);
+
+	if (channel < 0 || channel >= NUM_CHANNELS) {
+		printf("Requested channel is invalid!");
+		return -EINVAL;
+	}
+
+	if (!priv->initialized) {
+		int ret;
+
+		ret = meson_saradc_init(priv);
+		if (ret)
+			return ret;
+
+		priv->initialized = true;
+	}
+
+	priv->active_channel = channel;
+
+	return 0;
+}
+
+static int meson_saradc_stop(struct udevice *dev)
+{
+	struct meson_saradc_priv *priv = dev_get_priv(dev);
+
+	priv->active_channel = -1;
+
+	return 0;
+}
+
+static int meson_saradc_probe(struct udevice *dev)
+{
+	struct meson_saradc_priv *priv = dev_get_priv(dev);
+	int ret;
+
+	ret = regmap_init_mem(dev, &priv->regmap);
+	if (ret)
+		return ret;
+
+#if CONFIG_IS_ENABLED(CLK)
+	ret = clk_get_by_name(dev, "core", &priv->core_clk);
+	if (ret)
+		return ret;
+
+	ret = clk_get_by_name(dev, "adc_clk", &priv->adc_clk);
+	if (ret)
+		return ret;
+#endif
+
+	priv->active_channel = -1;
+
+	return 0;
+}
+
+int meson_saradc_ofdata_to_platdata(struct udevice *dev)
+{
+	struct adc_uclass_platdata *uc_pdata = dev_get_uclass_platdata(dev);
+	struct meson_saradc_priv *priv = dev_get_priv(dev);
+
+	priv->data = (struct meson_saradc_data *)dev_get_driver_data(dev);
+
+	uc_pdata->data_mask = GENMASK(priv->data->num_bits - 1, 0);
+	uc_pdata->data_format = ADC_DATA_FORMAT_BIN;
+	uc_pdata->data_timeout_us = MESON_SAR_ADC_TIMEOUT * 1000;
+	uc_pdata->channel_mask = GENMASK(NUM_CHANNELS - 1, 0);
+
+	return 0;
+}
+
+static const struct adc_ops meson_saradc_ops = {
+	.start_channel = meson_saradc_start_channel,
+	.channel_data = meson_saradc_channel_data,
+	.stop = meson_saradc_stop,
+};
+
+static const struct meson_saradc_data gxbb_saradc_data = {
+	.num_bits = 10,
+};
+
+static const struct meson_saradc_data gxl_saradc_data = {
+	.num_bits = 12,
+};
+
+static const struct udevice_id meson_saradc_ids[] = {
+	{ .compatible = "amlogic,meson-gxbb-saradc",
+	  .data = (ulong)&gxbb_saradc_data },
+	{ .compatible = "amlogic,meson-gxl-saradc",
+	  .data = (ulong)&gxl_saradc_data },
+	{ .compatible = "amlogic,meson-gxm-saradc",
+	  .data = (ulong)&gxl_saradc_data },
+	{ }
+};
+
+U_BOOT_DRIVER(meson_saradc) = {
+	.name		= "meson_saradc",
+	.id		= UCLASS_ADC,
+	.of_match	= meson_saradc_ids,
+	.ops		= &meson_saradc_ops,
+	.probe		= meson_saradc_probe,
+	.ofdata_to_platdata = meson_saradc_ofdata_to_platdata,
+	.priv_auto_alloc_size = sizeof(struct meson_saradc_priv),
+};
-- 
2.7.4



From narmstrong at baylibre.com  Mon Apr 23 07:29:07 2018
From: narmstrong at baylibre.com (Neil Armstrong)
Date: Mon, 23 Apr 2018 16:29:07 +0200
Subject: Fwd: [U-Boot] [PATCH 1/1] mmc: avoid division by zero in
 meson_mmc_config_clock - Please, consider for v2018.05-rc2
In-Reply-To: <e3f276ba-586f-5435-0447-3e00efba5411@baylibre.com>
References: <e3f276ba-586f-5435-0447-3e00efba5411@baylibre.com>
Message-ID: <a1a6cf2d-93d9-4b0c-23c1-a0177d3b81ed@baylibre.com>


Hi All,

Sorry to top-post, but could this patch go into master for next release ?

Currently all the Amlogic boards are broken on master becaus eof this issue.

Thanks,
Neil

-------- Forwarded Message --------
Subject: Re: [U-Boot] [PATCH 1/1] mmc: avoid division by zero in meson_mmc_config_clock - Please, consider for v2018.05-rc2
Date: Wed, 11 Apr 2018 16:39:08 +0200
From: Neil Armstrong <narmstrong at baylibre.com>
Organization: Baylibre
To: Heinrich Schuchardt <xypron.glpk at gmx.de>, Jaehoon Chung <jh80.chung at samsung.com>
CC: Vagrant Cascadian <vagrant at debian.org>, u-boot at lists.denx.de, Tom Rini <trini at konsulko.com>, open list:ARM/Amlogic Meson... <linux-amlogic at lists.infradead.org>

Hi Jaehoon,

On 10/04/2018 18:01, Heinrich Schuchardt wrote:
> On 03/24/2018 03:57 PM, Heinrich Schuchardt wrote:
>> On 03/18/2018 01:03 AM, Vagrant Cascadian wrote:
>>> On 2018-03-17, Heinrich Schuchardt wrote:
>>>> The Odroid C2 fails to read from mmc with U-Boot v2018.03.
>>>> The change avoids a division by zero.
>>>>
>>>> The fix was suggested by Jaehoon in
>>>> https://lists.denx.de/pipermail/u-boot/2018-January/318577.html
>>>
>>> Thanks!
>>>
>>> Works for me with odroid-c2 on u-boot 2018.03.
>>>
>>> Without the patch, mmc access immediately hangs the board.
>>>
>>> Tested-by: Vagrant Cascadian <vagrant at debian.org>
>>>
>>>
>>> live well,
>>>   vagrant
>>>
>>>> Reported-by: Vagrant Cascadian <vagrant at debian.org>
>>>> Suggested-by: Jaehoon Chung <jh80.chung at samsung.com>
>>>> Signed-off-by: Heinrich Schuchardt <xypron.glpk at gmx.de>
>>>> ---
[...]
>>>> -- 
>>>> 2.14.2
>>
>> Hello Jaehoon,
>>
>> will you pick the patch?
>>
>> Best regards
>>
>> Heinrich
>>
> 
> Hello Jaehoon,
> 
> since v2018.03 the Odroid C2 cannot be booted with U-Boot. This patch
> fixes it and has been adopted by Debian:
> https://packages.debian.org/de/buster/u-boot
> 
> Could you, please, consider it for v2018.05-rc2.
> 
> Best regards
> 
> Heinrich
> 
It also affects the other Amlogic platforms : P212, LibreTech-CC and Khadas-Vim, thus 2018.03 is broken for these platforms.

Thanks,
Neil

-- 
Neil Armstrong
Embedded Linux Software Engineer
BayLibre - At the Heart of Embedded Linux
www.baylibre.com


From khilman at baylibre.com  Mon Apr 23 09:41:05 2018
From: khilman at baylibre.com (Kevin Hilman)
Date: Mon, 23 Apr 2018 09:41:05 -0700
Subject: [PATCH v2] ARM64: dts: meson-axg: enable the eMMC controller
In-Reply-To: <CAPDyKFpcmO7LYuyuNPcYmzeDyq_AXDH5W4Y9dByTL-B+DGZSqg@mail.gmail.com>
References: <20180408113647.13543-1-yixun.lan@amlogic.com>
 <7ho9if3wo3.fsf@baylibre.com>
 <CAPDyKFpcmO7LYuyuNPcYmzeDyq_AXDH5W4Y9dByTL-B+DGZSqg@mail.gmail.com>
Message-ID: <CAOi56cUwzrpA1AdRQE3gdW55my-_dqSNnwyEd4poUPjUkpaBag@mail.gmail.com>

On Thu, Apr 19, 2018 at 11:55 PM, Ulf Hansson <ulf.hansson at linaro.org> wrote:
> On 19 April 2018 at 19:58, Kevin Hilman <khilman at baylibre.com> wrote:
>> Yixun Lan <yixun.lan at amlogic.com> writes:
>>
>>> From: Nan Li <nan.li at amlogic.com>
>>>
>>> The IP of eMMC controller in AXG is similiar to Meson-GX series.
>>> Here we add the initial support of the HS200 mode with
>>> clock running at 166MHz (to be safe), since we found some eMMC chip
>>> fail to run at 200MHz due to tunning phase error.
>>>
>>> Signed-off-by: Nan Li <nan.li at amlogic.com>
>>> Signed-off-by: Yixun Lan <yixun.lan at amlogic.com>
>>
>> Applied to v4.18/dt64
>>
>>> ---
>>> Hi Kevin
>>>   Please note this patch actually depend on the eMMC driver here [0].
>>>   Still a few problem to solve, to improve the tuning phase driver to make
>>> the clock running at 200MHz, and to further support the HS400 mode.
>>> Anyway, this patch itself is quite independent.
>>
>> The driver changes are queued for v4.18 also.  Good!
>
> Right, may I consider that as an ack? :-)

I thought it was already merged while I was OoO, so I didn't bother to
reply with an ack, but if it's not too late, then yes:

Acked-by: Kevin Hilman <khilman at baylibre.com>

Kevin


From martin.blumenstingl at googlemail.com  Mon Apr 23 10:49:42 2018
From: martin.blumenstingl at googlemail.com (Martin Blumenstingl)
Date: Mon, 23 Apr 2018 19:49:42 +0200
Subject: [PATCH v3 1/1] clk: meson: meson8b: add support for the NAND
 clocks
In-Reply-To: <1524472409.4026.10.camel@baylibre.com>
References: <20180422103339.32608-1-martin.blumenstingl@googlemail.com>
 <20180422103339.32608-2-martin.blumenstingl@googlemail.com>
 <1524472409.4026.10.camel@baylibre.com>
Message-ID: <CAFBinCCKde+42PXzak8nuGEGTxwrvOVV7KDeoD1RkV_DjMdDOA@mail.gmail.com>

Hi Jerome,

On Mon, Apr 23, 2018 at 10:33 AM, Jerome Brunet <jbrunet at baylibre.com> wrote:
> On Sun, 2018-04-22 at 12:33 +0200, Martin Blumenstingl wrote:
>> This adds the NAND clocks (from the HHI_NAND_CLK_CNTL register) to the
>> Meson8b clock driver. There are three NAND clocks: a gate which enables
>> or disables the NAND clock, a mux and a divider (which divides the mux
>> output).
>> Unfortunately the public S805 datasheet does not document the mux
>> parents. However, the vendor kernel has a few hints for us which allows
>> us to make an educated guess about the clock parents. To do this we need
>> to have a look at set_nand_core_clk() from the vendor's NAND driver (see
>> [0]):
>> - XTAL = (4<<9) | (1<<8) | 0
>> - 160MHz = (0<<9) | (1<<8) | 3)
>> - 182MHz = (3<<9) | (1<<8) | 1)
>> - 212MHz = (1<<9) | (1<<8) | 3)
>> - 255MHz = (2<<9) | (1<<8) | 1)
>>
>> While there is a comment for the XTAL parent (which indicates that it
>> should only be used for debugging) we have to do a bit of math for the
>> other parents: target_freq * divider = rate of parent clock
>> Bit 8 above is the enable bit, so we can ignore it here. Bits 11:9 are
>> the mux index and bits 6:0 are the 0-based divider (so we need to add
>> 1). This gives us:
>> - mux 0 (160MHz * 4) = fclk_div4 (actual rate = 637.5MHz, off by 2.5MHz)
>> - mux 1 (212MHz * 4) = fclk_div3 (actual rate = 850MHz, off by 2MHz)
>> - mux 2 (255MHz * 2) = fclk_div5 (matches exactly 510MHz)
>> - mux 3 (182MHz * 2) = fclk_div7 (actual rate = 346.3MHz, off by 0.3MHz)
>>
>> [0] https://github.com/khadas/linux/blob/9587681285cb/drivers/amlogic/amlnf/dev/amlnf_ctrl.c#L314
>>
>> Signed-off-by: Martin Blumenstingl <martin.blumenstingl at googlemail.com>
>> ---
>>  drivers/clk/meson/meson8b.c              | 54 ++++++++++++++++++++++++
>>  drivers/clk/meson/meson8b.h              |  3 +-
>>  include/dt-bindings/clock/meson8b-clkc.h |  3 ++
>>  3 files changed, 59 insertions(+), 1 deletion(-)
>>
>> diff --git a/drivers/clk/meson/meson8b.c b/drivers/clk/meson/meson8b.c
>> index 2c4ff6192852..3f726ff73261 100644
>> --- a/drivers/clk/meson/meson8b.c
>> +++ b/drivers/clk/meson/meson8b.c
>> @@ -639,6 +639,54 @@ static struct clk_regmap meson8b_cpu_clk = {
>>       },
>>  };
>>
>> +static struct clk_regmap meson8b_nand_clk_sel = {
>> +     .data = &(struct clk_regmap_mux_data){
>> +             .offset = HHI_NAND_CLK_CNTL,
>> +             .mask = 0x7,
>> +             .shift = 9,
>> +             .flags = CLK_MUX_ROUND_CLOSEST,
>
> Maybe you have seen it already, but there was a problem with this flag, it was
> ignored. Fix should land in this cycle.
>
> https://lkml.kernel.org/r/152389589448.51482.15489333464741262913 at swboyd.mtv.cor
> p.google.com
yep, I've seen your fix (thank you!) so I decided to re-send this

>> +     },
>> +     .hw.init = &(struct clk_init_data){
>> +             .name = "nand_clk_sel",
>>
>
> [...]
>
>>  /*
>>   * include the CLKID and RESETID that have
>> diff --git a/include/dt-bindings/clock/meson8b-clkc.h b/include/dt-bindings/clock/meson8b-clkc.h
>> index dea9d46d4fa7..434d7ba63801 100644
>> --- a/include/dt-bindings/clock/meson8b-clkc.h
>> +++ b/include/dt-bindings/clock/meson8b-clkc.h
>> @@ -102,5 +102,8 @@
>>  #define CLKID_MPLL0          93
>>  #define CLKID_MPLL1          94
>>  #define CLKID_MPLL2          95
>> +#define CLKID_NAND_SEL               110
>> +#define CLKID_NAND_DIV               111
>
> Nitpick: Could put the bindings in separate patch ?
> It makes our life easier if intend to push a DT patch using them in this cycle.
OK, I'll split the patch (even though it's HIGHLY unlikely that the
NAND driver will make it anytime soon..)

> Also, do you need to expose the divider and the mux ?
I think only the most specific leaf (= gate clock) is needed, I'll
keep the mux and divider in the private header file

> Apart from this, patch looks good to me.
>
> Acked-by: Jerome Brunet <jbrunet at baylibre.com>
thank you!


Regards
Martin


From martin.blumenstingl at googlemail.com  Mon Apr 23 12:30:29 2018
From: martin.blumenstingl at googlemail.com (Martin Blumenstingl)
Date: Mon, 23 Apr 2018 21:30:29 +0200
Subject: [PATCH clk-fixes] clk: meson: meson8b: fix meson8b_cpu_clk parent
 clock name
Message-ID: <20180423193029.29428-1-martin.blumenstingl@googlemail.com>

meson8b_cpu_clk has two parent clocks:
- meson8b_xtal
- meson8b_cpu_scale_out_sel

The name of the "xtal" clock parent is specified correctly. However,
there is a typo in the name of the second parent clock. The
meson8b_cpu_scale_out_sel definition uses the name "cpu_scale_out_sel"
(which matches the name from the datasheet). However, the mux parent
definition uses the name "cpu_out_sel" which does not match any existing
clock.

Fixes: 251b6fd38bcb9c ("clk: meson: rework meson8b cpu clock")
Signed-off-by: Martin Blumenstingl <martin.blumenstingl at googlemail.com>
---
 drivers/clk/meson/meson8b.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/clk/meson/meson8b.c b/drivers/clk/meson/meson8b.c
index 2c4ff6192852..d0524ec71aad 100644
--- a/drivers/clk/meson/meson8b.c
+++ b/drivers/clk/meson/meson8b.c
@@ -632,7 +632,8 @@ static struct clk_regmap meson8b_cpu_clk = {
 	.hw.init = &(struct clk_init_data){
 		.name = "cpu_clk",
 		.ops = &clk_regmap_mux_ro_ops,
-		.parent_names = (const char *[]){ "xtal", "cpu_out_sel" },
+		.parent_names = (const char *[]){ "xtal",
+						  "cpu_scale_out_sel" },
 		.num_parents = 2,
 		.flags = (CLK_SET_RATE_PARENT |
 			  CLK_SET_RATE_NO_REPARENT),
-- 
2.17.0



From martin.blumenstingl at googlemail.com  Mon Apr 23 12:35:08 2018
From: martin.blumenstingl at googlemail.com (Martin Blumenstingl)
Date: Mon, 23 Apr 2018 21:35:08 +0200
Subject: [PATCH v4 1/2] dt-bindings: clock: meson8b: export the NAND clock
In-Reply-To: <20180423193509.30584-1-martin.blumenstingl@googlemail.com>
References: <20180423193509.30584-1-martin.blumenstingl@googlemail.com>
Message-ID: <20180423193509.30584-2-martin.blumenstingl@googlemail.com>

Export the NAND clock to the dt-bindings.

Signed-off-by: Martin Blumenstingl <martin.blumenstingl at googlemail.com>
Acked-by: Jerome Brunet <jbrunet at baylibre.com>
---
 include/dt-bindings/clock/meson8b-clkc.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/include/dt-bindings/clock/meson8b-clkc.h b/include/dt-bindings/clock/meson8b-clkc.h
index dea9d46d4fa7..a60f47b49231 100644
--- a/include/dt-bindings/clock/meson8b-clkc.h
+++ b/include/dt-bindings/clock/meson8b-clkc.h
@@ -102,5 +102,6 @@
 #define CLKID_MPLL0		93
 #define CLKID_MPLL1		94
 #define CLKID_MPLL2		95
+#define CLKID_NAND_CLK		112
 
 #endif /* __MESON8B_CLKC_H */
-- 
2.17.0



From martin.blumenstingl at googlemail.com  Mon Apr 23 12:35:07 2018
From: martin.blumenstingl at googlemail.com (Martin Blumenstingl)
Date: Mon, 23 Apr 2018 21:35:07 +0200
Subject: [PATCH v4 0/2] add support for the NAND clocks on Meson8b
Message-ID: <20180423193509.30584-1-martin.blumenstingl@googlemail.com>

This adds support for the NAND clocks found in the Meson8, Meson8b
and Meson8m2 SoCs.
The clocks consist of a simple gate, a divider and a mux. The mux
parents are not documented in the public S805 datasheet [0], so I
had to use a bit of math and take the vendor kernel as reference [1]
to find the actual parent clocks.
Some mux parents cannot be divided down without remainder to the
target clocks (as expected by the vendor NAND driver) these clocks
have the ROUND_CLOSEST flag set.

The new clocks are similar to gxbb_sd_emmc_c_clk0_sel,
gxbb_sd_emmc_c_clk0_div and gxbb_sd_emmc_c_clk0 on the GX SoCs.
Actual differences are:
- mux parents are re-ordered
- the gate is controlled by bit 8 (instead of bit 7 on GX)

Changes since v3 at [2]:
- move the dt-bindings change into a separate patch
- do not export the mux and the divider as we only need to manage the
  left clock (in our case: the gate - the common clock framework will
  take care of the rest)

Changes since v2 at [1]:
- rebased on top of v4.17-rc1 and updated the clocks to use the new
  clk_regmap framework (as all other clocks in meson8b.c)

Changes since v1 at [0]:
- rebased so it still applies in 2018
- dropped mux table (since the known parents are values 0..4)
- replaced CLK_SET_RATE_NO_REPARENT with CLK_SET_RATE_PARENT on the mux
- added CLK_SET_RATE_PARENT on the divider
- fixed width of the divider (it's 7 bits wide, ranging from bit 0 to 6
  while v1 only used a width of 6 bits)


[0] http://lists.infradead.org/pipermail/linux-amlogic/2017-April/003237.html
[1] http://lists.infradead.org/pipermail/linux-amlogic/2018-January/005934.html
[2] http://lists.infradead.org/pipermail/linux-amlogic/2018-April/007134.html

Martin Blumenstingl (2):
  dt-bindings: clock: meson8b: export the NAND clock
  clk: meson: meson8b: add support for the NAND clocks

 drivers/clk/meson/meson8b.c              | 54 ++++++++++++++++++++++++
 drivers/clk/meson/meson8b.h              |  5 ++-
 include/dt-bindings/clock/meson8b-clkc.h |  1 +
 3 files changed, 59 insertions(+), 1 deletion(-)

-- 
2.17.0



From martin.blumenstingl at googlemail.com  Mon Apr 23 12:35:09 2018
From: martin.blumenstingl at googlemail.com (Martin Blumenstingl)
Date: Mon, 23 Apr 2018 21:35:09 +0200
Subject: [PATCH v4 2/2] clk: meson: meson8b: add support for the NAND clocks
In-Reply-To: <20180423193509.30584-1-martin.blumenstingl@googlemail.com>
References: <20180423193509.30584-1-martin.blumenstingl@googlemail.com>
Message-ID: <20180423193509.30584-3-martin.blumenstingl@googlemail.com>

This adds the NAND clocks (from the HHI_NAND_CLK_CNTL register) to the
Meson8b clock driver. There are three NAND clocks: a gate which enables
or disables the NAND clock, a mux and a divider (which divides the mux
output).
Unfortunately the public S805 datasheet does not document the mux
parents. However, the vendor kernel has a few hints for us which allows
us to make an educated guess about the clock parents. To do this we need
to have a look at set_nand_core_clk() from the vendor's NAND driver (see
[0]):
- XTAL = (4<<9) | (1<<8) | 0
- 160MHz = (0<<9) | (1<<8) | 3)
- 182MHz = (3<<9) | (1<<8) | 1)
- 212MHz = (1<<9) | (1<<8) | 3)
- 255MHz = (2<<9) | (1<<8) | 1)

While there is a comment for the XTAL parent (which indicates that it
should only be used for debugging) we have to do a bit of math for the
other parents: target_freq * divider = rate of parent clock
Bit 8 above is the enable bit, so we can ignore it here. Bits 11:9 are
the mux index and bits 6:0 are the 0-based divider (so we need to add
1). This gives us:
- mux 0 (160MHz * 4) = fclk_div4 (actual rate = 637.5MHz, off by 2.5MHz)
- mux 1 (212MHz * 4) = fclk_div3 (actual rate = 850MHz, off by 2MHz)
- mux 2 (255MHz * 2) = fclk_div5 (matches exactly 510MHz)
- mux 3 (182MHz * 2) = fclk_div7 (actual rate = 346.3MHz, off by 0.3MHz)

[0] https://github.com/khadas/linux/blob/9587681285cb/drivers/amlogic/amlnf/dev/amlnf_ctrl.c#L314

Signed-off-by: Martin Blumenstingl <martin.blumenstingl at googlemail.com>
Acked-by: Jerome Brunet <jbrunet at baylibre.com>
---
 drivers/clk/meson/meson8b.c | 54 +++++++++++++++++++++++++++++++++++++
 drivers/clk/meson/meson8b.h |  5 +++-
 2 files changed, 58 insertions(+), 1 deletion(-)

diff --git a/drivers/clk/meson/meson8b.c b/drivers/clk/meson/meson8b.c
index d0524ec71aad..40068c1b5e80 100644
--- a/drivers/clk/meson/meson8b.c
+++ b/drivers/clk/meson/meson8b.c
@@ -640,6 +640,54 @@ static struct clk_regmap meson8b_cpu_clk = {
 	},
 };
 
+static struct clk_regmap meson8b_nand_clk_sel = {
+	.data = &(struct clk_regmap_mux_data){
+		.offset = HHI_NAND_CLK_CNTL,
+		.mask = 0x7,
+		.shift = 9,
+		.flags = CLK_MUX_ROUND_CLOSEST,
+	},
+	.hw.init = &(struct clk_init_data){
+		.name = "nand_clk_sel",
+		.ops = &clk_regmap_mux_ops,
+		/* FIXME all other parents are unknown: */
+		.parent_names = (const char *[]){ "fclk_div4", "fclk_div3",
+			"fclk_div5", "fclk_div7", "xtal" },
+		.num_parents = 5,
+		.flags = CLK_SET_RATE_PARENT,
+	},
+};
+
+static struct clk_regmap meson8b_nand_clk_div = {
+	.data = &(struct clk_regmap_div_data){
+		.offset =  HHI_NAND_CLK_CNTL,
+		.shift = 0,
+		.width = 7,
+		.flags = CLK_DIVIDER_ROUND_CLOSEST,
+	},
+	.hw.init = &(struct clk_init_data){
+		.name = "nand_clk_div",
+		.ops = &clk_regmap_divider_ops,
+		.parent_names = (const char *[]){ "nand_clk_sel" },
+		.num_parents = 1,
+		.flags = CLK_SET_RATE_PARENT,
+	},
+};
+
+static struct clk_regmap meson8b_nand_clk_gate = {
+	.data = &(struct clk_regmap_gate_data){
+		.offset = HHI_NAND_CLK_CNTL,
+		.bit_idx = 8,
+	},
+	.hw.init = &(struct clk_init_data){
+		.name = "nand_clk_gate",
+		.ops = &clk_regmap_gate_ops,
+		.parent_names = (const char *[]){ "nand_clk_div" },
+		.num_parents = 1,
+		.flags = CLK_SET_RATE_PARENT,
+	},
+};
+
 /* Everything Else (EE) domain gates */
 
 static MESON_GATE(meson8b_ddr, HHI_GCLK_MPEG0, 0);
@@ -835,6 +883,9 @@ static struct clk_hw_onecell_data meson8b_hw_onecell_data = {
 		[CLKID_FCLK_DIV4_DIV]	    = &meson8b_fclk_div4_div.hw,
 		[CLKID_FCLK_DIV5_DIV]	    = &meson8b_fclk_div5_div.hw,
 		[CLKID_FCLK_DIV7_DIV]	    = &meson8b_fclk_div7_div.hw,
+		[CLKID_NAND_SEL]	    = &meson8b_nand_clk_sel.hw,
+		[CLKID_NAND_DIV]	    = &meson8b_nand_clk_div.hw,
+		[CLKID_NAND_CLK]	    = &meson8b_nand_clk_gate.hw,
 		[CLK_NR_CLKS]		    = NULL,
 	},
 	.num = CLK_NR_CLKS,
@@ -940,6 +991,9 @@ static struct clk_regmap *const meson8b_clk_regmaps[] = {
 	&meson8b_fclk_div4,
 	&meson8b_fclk_div5,
 	&meson8b_fclk_div7,
+	&meson8b_nand_clk_sel,
+	&meson8b_nand_clk_div,
+	&meson8b_nand_clk_gate,
 };
 
 static const struct meson8b_clk_reset_line {
diff --git a/drivers/clk/meson/meson8b.h b/drivers/clk/meson/meson8b.h
index 6e414bd36981..a687dc60b6d0 100644
--- a/drivers/clk/meson/meson8b.h
+++ b/drivers/clk/meson/meson8b.h
@@ -40,6 +40,7 @@
 #define HHI_VID_CLK_CNTL		0x17c /* 0x5f offset in data sheet */
 #define HHI_VID_DIVIDER_CNTL		0x198 /* 0x66 offset in data sheet */
 #define HHI_SYS_CPU_CLK_CNTL0		0x19c /* 0x67 offset in data sheet */
+#define HHI_NAND_CLK_CNTL		0x25c /* 0x97 offset in data sheet */
 #define HHI_MPLL_CNTL			0x280 /* 0xa0 offset in data sheet */
 #define HHI_SYS_PLL_CNTL		0x300 /* 0xc0 offset in data sheet */
 #define HHI_VID_PLL_CNTL		0x320 /* 0xc8 offset in data sheet */
@@ -83,8 +84,10 @@
 #define CLKID_FCLK_DIV4_DIV	107
 #define CLKID_FCLK_DIV5_DIV	108
 #define CLKID_FCLK_DIV7_DIV	109
+#define CLKID_NAND_SEL		110
+#define CLKID_NAND_DIV		111
 
-#define CLK_NR_CLKS		110
+#define CLK_NR_CLKS		113
 
 /*
  * include the CLKID and RESETID that have
-- 
2.17.0



From jbrunet at baylibre.com  Mon Apr 23 12:38:03 2018
From: jbrunet at baylibre.com (Jerome Brunet)
Date: Mon, 23 Apr 2018 21:38:03 +0200
Subject: [PATCH clk-fixes] clk: meson: meson8b: fix
 meson8b_fclk_div3_div clock name
In-Reply-To: <1524471797.4026.3.camel@baylibre.com>
References: <20180422102843.31238-1-martin.blumenstingl@googlemail.com>
 <1524471797.4026.3.camel@baylibre.com>
Message-ID: <1524512283.4026.28.camel@baylibre.com>

On Mon, 2018-04-23 at 10:23 +0200, Jerome Brunet wrote:
> On Sun, 2018-04-22 at 12:28 +0200, Martin Blumenstingl wrote:
> > The names of all fclk divider gate clocks follow the naming schema
> > "fclk_divN" and the name of all fclk fixed dividers follow the naming
> > schema "fclk_divN_div".
> > There's one exception to this rule: meson8b_fclk_div3_div's name is
> > "fclk_div_div3". It's child clock meson8b_fclk_div3 however references
> > it as "fclk_div3_div" (following the naming schema explained above).
> > 
> > Fix the naming of the meson8b_fclk_div3_div clock to follow the naming
> > schema. This also fixes serial console on my Meson8m2 board because
> > "clk81" uses fclk_div3 as parent. However, since the hierarchy stops at
> > meson8b_fclk_div3 there's no known parent clock and the rate of "clk81"
> > and all of it's children (UART clock, SDIO MMC controller clock, ...)
> > are all 0.
> > 
> > Fixes: 05f814402d6174 ("clk: meson: add fdiv clock gates")
> > Signed-off-by: Martin Blumenstingl <martin.blumenstingl at googlemail.com>
> 
> Oopss ... Thanks for fixing this Martin.
> 
> Reviewed-by: Jerome Brunet <jbrunet at baylibre.com>
> 
> Stephen, Do you mind taking this directly for fixes ? I can prepare a PR if you
> prefer.

Nevermind, apparently I have another mistake of the same kind, so there is
another fix coming up.

I'?l make a PR 

> 
> Regards
> Jerome
> 
> > ---
> >  drivers/clk/meson/meson8b.c | 2 +-
> >  1 file changed, 1 insertion(+), 1 deletion(-)
> > 
> > diff --git a/drivers/clk/meson/meson8b.c b/drivers/clk/meson/meson8b.c
> > index cc2992493e0b..2c4ff6192852 100644
> > --- a/drivers/clk/meson/meson8b.c
> > +++ b/drivers/clk/meson/meson8b.c
> > @@ -253,7 +253,7 @@ static struct clk_fixed_factor meson8b_fclk_div3_div = {
> >  	.mult = 1,
> >  	.div = 3,
> >  	.hw.init = &(struct clk_init_data){
> > -		.name = "fclk_div_div3",
> > +		.name = "fclk_div3_div",
> >  		.ops = &clk_fixed_factor_ops,
> >  		.parent_names = (const char *[]){ "fixed_pll" },
> >  		.num_parents = 1,
> 
> 



From jbrunet at baylibre.com  Mon Apr 23 12:41:46 2018
From: jbrunet at baylibre.com (Jerome Brunet)
Date: Mon, 23 Apr 2018 21:41:46 +0200
Subject: [PATCH clk-fixes] clk: meson: meson8b: fix meson8b_cpu_clk
 parent clock name
In-Reply-To: <20180423193029.29428-1-martin.blumenstingl@googlemail.com>
References: <20180423193029.29428-1-martin.blumenstingl@googlemail.com>
Message-ID: <1524512506.4026.31.camel@baylibre.com>

On Mon, 2018-04-23 at 21:30 +0200, Martin Blumenstingl wrote:
> meson8b_cpu_clk has two parent clocks:
> - meson8b_xtal
> - meson8b_cpu_scale_out_sel
> 
> The name of the "xtal" clock parent is specified correctly. However,
> there is a typo in the name of the second parent clock. The
> meson8b_cpu_scale_out_sel definition uses the name "cpu_scale_out_sel"
> (which matches the name from the datasheet). However, the mux parent
> definition uses the name "cpu_out_sel" which does not match any existing
> clock.
> 
> Fixes: 251b6fd38bcb9c ("clk: meson: rework meson8b cpu clock")
> Signed-off-by: Martin Blumenstingl <martin.blumenstingl at googlemail.com>

Roohhh ... Sorry about that :(

I'll take it along with the other typo fix. Thx Martin !

> ---
>  drivers/clk/meson/meson8b.c | 3 ++-
>  1 file changed, 2 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/clk/meson/meson8b.c b/drivers/clk/meson/meson8b.c
> index 2c4ff6192852..d0524ec71aad 100644
> --- a/drivers/clk/meson/meson8b.c
> +++ b/drivers/clk/meson/meson8b.c
> @@ -632,7 +632,8 @@ static struct clk_regmap meson8b_cpu_clk = {
>  	.hw.init = &(struct clk_init_data){
>  		.name = "cpu_clk",
>  		.ops = &clk_regmap_mux_ro_ops,
> -		.parent_names = (const char *[]){ "xtal", "cpu_out_sel" },
> +		.parent_names = (const char *[]){ "xtal",
> +						  "cpu_scale_out_sel" },
>  		.num_parents = 2,
>  		.flags = (CLK_SET_RATE_PARENT |
>  			  CLK_SET_RATE_NO_REPARENT),



From ezequiel at vanguardiasur.com.ar  Tue Apr 24 07:04:25 2018
From: ezequiel at vanguardiasur.com.ar (Ezequiel Garcia)
Date: Tue, 24 Apr 2018 11:04:25 -0300
Subject: [PATCH 1/2] clk: honor CLK_MUX_ROUND_CLOSEST in generic clk mux
In-Reply-To: <20180409135921.5617-2-jbrunet@baylibre.com>
References: <20180409135921.5617-1-jbrunet@baylibre.com>
 <20180409135921.5617-2-jbrunet@baylibre.com>
Message-ID: <CAAEAJfDgGYu9WR5+qA-trQUTkb--bam=LLbhH+1N2OdrtBGLzA@mail.gmail.com>

On 9 April 2018 at 10:59, Jerome Brunet <jbrunet at baylibre.com> wrote:
>
> CLK_MUX_ROUND_CLOSEST is part of the clk_mux documentation but clk_mux
> directly calls __clk_mux_determine_rate(), which overrides the flag.
> As result, if clk_mux is instantiated with CLK_MUX_ROUND_CLOSEST, the
> flag will be ignored and the clock rounded down.
>
> To solve this, this patch expose clk_mux_determine_rate_flags() in the
> clk-provider API and uses it in the determine_rate() callback of clk_mux.
>
> Fixes: 15a02c1f6dd7 ("clk: Add __clk_mux_determine_rate_closest")
> Signed-off-by: Jerome Brunet <jbrunet at baylibre.com>
> ---
>  drivers/clk/clk-mux.c        | 10 +++++++++-
>  drivers/clk/clk.c            |  7 ++++---
>  include/linux/clk-provider.h |  3 +++
>  3 files changed, 16 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/clk/clk-mux.c b/drivers/clk/clk-mux.c
> index ac4a042f8658..1628b93655ed 100644
> --- a/drivers/clk/clk-mux.c
> +++ b/drivers/clk/clk-mux.c
> @@ -112,10 +112,18 @@ static int clk_mux_set_parent(struct clk_hw *hw, u8 index)
>         return 0;
>  }
>
> +static int clk_mux_determine_rate(struct clk_hw *hw,
> +                                 struct clk_rate_request *req)
> +{
> +       struct clk_mux *mux = to_clk_mux(hw);
> +
> +       return clk_mux_determine_rate_flags(hw, req, mux->flags);
> +}
> +
>  const struct clk_ops clk_mux_ops = {
>         .get_parent = clk_mux_get_parent,
>         .set_parent = clk_mux_set_parent,
> -       .determine_rate = __clk_mux_determine_rate,
> +       .determine_rate = clk_mux_determine_rate,
>  };
>  EXPORT_SYMBOL_GPL(clk_mux_ops);
>
> diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c
> index ea67ac81c6f9..7af555f0e60c 100644
> --- a/drivers/clk/clk.c
> +++ b/drivers/clk/clk.c
> @@ -426,9 +426,9 @@ static bool mux_is_better_rate(unsigned long rate, unsigned long now,
>         return now <= rate && now > best;
>  }
>
> -static int
> -clk_mux_determine_rate_flags(struct clk_hw *hw, struct clk_rate_request *req,
> -                            unsigned long flags)
> +int clk_mux_determine_rate_flags(struct clk_hw *hw,
> +                                struct clk_rate_request *req,
> +                                unsigned long flags)
>  {
>         struct clk_core *core = hw->core, *parent, *best_parent = NULL;
>         int i, num_parents, ret;
> @@ -488,6 +488,7 @@ clk_mux_determine_rate_flags(struct clk_hw *hw, struct clk_rate_request *req,
>
>         return 0;
>  }
> +EXPORT_SYMBOL_GPL(clk_mux_determine_rate_flags);
>

Why do we need to export this?

>  struct clk *__clk_lookup(const char *name)
>  {
> diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h
> index 210a890008f9..1d25e149c1c5 100644
> --- a/include/linux/clk-provider.h
> +++ b/include/linux/clk-provider.h
> @@ -765,6 +765,9 @@ int __clk_mux_determine_rate(struct clk_hw *hw,
>  int __clk_determine_rate(struct clk_hw *core, struct clk_rate_request *req);
>  int __clk_mux_determine_rate_closest(struct clk_hw *hw,
>                                      struct clk_rate_request *req);
> +int clk_mux_determine_rate_flags(struct clk_hw *hw,
> +                                struct clk_rate_request *req,
> +                                unsigned long flags);
>  void clk_hw_reparent(struct clk_hw *hw, struct clk_hw *new_parent);
>  void clk_hw_set_rate_range(struct clk_hw *hw, unsigned long min_rate,
>                            unsigned long max_rate);
> --
> 2.14.3
>

Reviewed-by: Ezequiel Garcia <ezequiel at collabora.com>

Thanks!
-- 
Ezequiel Garc?a, VanguardiaSur
www.vanguardiasur.com.ar


From maxi.jourdan at wanadoo.fr  Tue Apr 24 11:48:38 2018
From: maxi.jourdan at wanadoo.fr (Maxime Jourdan)
Date: Tue, 24 Apr 2018 20:48:38 +0200
Subject: [PATCH v2 2/2] clk: meson: gxbb: add the video decoder clocks
In-Reply-To: <20180424184838.3406-1-maxi.jourdan@wanadoo.fr>
References: <20180424184838.3406-1-maxi.jourdan@wanadoo.fr>
Message-ID: <20180424184838.3406-3-maxi.jourdan@wanadoo.fr>

Add the SEL/DIV/GATE for VDEC_1 and VDEC_HEVC.

Signed-off-by: Maxime Jourdan <maxi.jourdan at wanadoo.fr>
---
 drivers/clk/meson/gxbb.c | 114 +++++++++++++++++++++++++++++++++++++++
 drivers/clk/meson/gxbb.h |   6 ++-
 2 files changed, 119 insertions(+), 1 deletion(-)

diff --git a/drivers/clk/meson/gxbb.c b/drivers/clk/meson/gxbb.c
index b1e4d9557610..a893b1edda22 100644
--- a/drivers/clk/meson/gxbb.c
+++ b/drivers/clk/meson/gxbb.c
@@ -1543,6 +1543,102 @@ static struct clk_regmap gxbb_vapb = {
 	},
 };
 
+/* VDEC clocks */
+
+static const char * const gxbb_vdec_parent_names[] = {
+	"fclk_div4", "fclk_div3", "fclk_div5", "fclk_div7"
+};
+
+static struct clk_regmap gxbb_vdec_1_sel = {
+	.data = &(struct clk_regmap_mux_data){
+		.offset = HHI_VDEC_CLK_CNTL,
+		.mask = 0x3,
+		.shift = 9,
+		.flags = CLK_MUX_ROUND_CLOSEST,
+	},
+	.hw.init = &(struct clk_init_data){
+		.name = "vdec_1_sel",
+		.ops = &clk_regmap_mux_ops,
+		.parent_names = gxbb_vdec_parent_names,
+		.num_parents = ARRAY_SIZE(gxbb_vdec_parent_names),
+		.flags = CLK_SET_RATE_PARENT,
+	},
+};
+
+static struct clk_regmap gxbb_vdec_1_div = {
+	.data = &(struct clk_regmap_div_data){
+		.offset = HHI_VDEC_CLK_CNTL,
+		.shift = 0,
+		.width = 7,
+	},
+	.hw.init = &(struct clk_init_data){
+		.name = "vdec_1_div",
+		.ops = &clk_regmap_divider_ops,
+		.parent_names = (const char *[]){ "vdec_1_sel" },
+		.num_parents = 1,
+		.flags = CLK_SET_RATE_PARENT,
+	},
+};
+
+static struct clk_regmap gxbb_vdec_1 = {
+	.data = &(struct clk_regmap_gate_data){
+		.offset = HHI_VDEC_CLK_CNTL,
+		.bit_idx = 8,
+	},
+	.hw.init = &(struct clk_init_data) {
+		.name = "vdec_1",
+		.ops = &clk_regmap_gate_ops,
+		.parent_names = (const char *[]){ "vdec_1_div" },
+		.num_parents = 1,
+		.flags = CLK_SET_RATE_PARENT,
+	},
+};
+
+static struct clk_regmap gxbb_vdec_hevc_sel = {
+	.data = &(struct clk_regmap_mux_data){
+		.offset = HHI_VDEC2_CLK_CNTL,
+		.mask = 0x3,
+		.shift = 25,
+		.flags = CLK_MUX_ROUND_CLOSEST,
+	},
+	.hw.init = &(struct clk_init_data){
+		.name = "vdec_hevc_sel",
+		.ops = &clk_regmap_mux_ops,
+		.parent_names = gxbb_vdec_parent_names,
+		.num_parents = ARRAY_SIZE(gxbb_vdec_parent_names),
+		.flags = CLK_SET_RATE_PARENT,
+	},
+};
+
+static struct clk_regmap gxbb_vdec_hevc_div = {
+	.data = &(struct clk_regmap_div_data){
+		.offset = HHI_VDEC2_CLK_CNTL,
+		.shift = 16,
+		.width = 7,
+	},
+	.hw.init = &(struct clk_init_data){
+		.name = "vdec_hevc_div",
+		.ops = &clk_regmap_divider_ops,
+		.parent_names = (const char *[]){ "vdec_hevc_sel" },
+		.num_parents = 1,
+		.flags = CLK_SET_RATE_PARENT,
+	},
+};
+
+static struct clk_regmap gxbb_vdec_hevc = {
+	.data = &(struct clk_regmap_gate_data){
+		.offset = HHI_VDEC2_CLK_CNTL,
+		.bit_idx = 24,
+	},
+	.hw.init = &(struct clk_init_data) {
+		.name = "vdec_hevc",
+		.ops = &clk_regmap_gate_ops,
+		.parent_names = (const char *[]){ "vdec_hevc_div" },
+		.num_parents = 1,
+		.flags = CLK_SET_RATE_PARENT,
+	},
+};
+
 /* Everything Else (EE) domain gates */
 static MESON_GATE(gxbb_ddr, HHI_GCLK_MPEG0, 0);
 static MESON_GATE(gxbb_dos, HHI_GCLK_MPEG0, 1);
@@ -1786,6 +1882,12 @@ static struct clk_hw_onecell_data gxbb_hw_onecell_data = {
 		[CLKID_FCLK_DIV4_DIV]	    = &gxbb_fclk_div4_div.hw,
 		[CLKID_FCLK_DIV5_DIV]	    = &gxbb_fclk_div5_div.hw,
 		[CLKID_FCLK_DIV7_DIV]	    = &gxbb_fclk_div7_div.hw,
+		[CLKID_VDEC_1_SEL]	    = &gxbb_vdec_1_sel.hw,
+		[CLKID_VDEC_1_DIV]	    = &gxbb_vdec_1_div.hw,
+		[CLKID_VDEC_1]		    = &gxbb_vdec_1.hw,
+		[CLKID_VDEC_HEVC_SEL]	    = &gxbb_vdec_hevc_sel.hw,
+		[CLKID_VDEC_HEVC_DIV]	    = &gxbb_vdec_hevc_div.hw,
+		[CLKID_VDEC_HEVC]	    = &gxbb_vdec_hevc.hw,
 		[NR_CLKS]		    = NULL,
 	},
 	.num = NR_CLKS,
@@ -1942,6 +2044,12 @@ static struct clk_hw_onecell_data gxl_hw_onecell_data = {
 		[CLKID_FCLK_DIV4_DIV]	    = &gxbb_fclk_div4_div.hw,
 		[CLKID_FCLK_DIV5_DIV]	    = &gxbb_fclk_div5_div.hw,
 		[CLKID_FCLK_DIV7_DIV]	    = &gxbb_fclk_div7_div.hw,
+		[CLKID_VDEC_1_SEL]	    = &gxbb_vdec_1_sel.hw,
+		[CLKID_VDEC_1_DIV]	    = &gxbb_vdec_1_div.hw,
+		[CLKID_VDEC_1]		    = &gxbb_vdec_1.hw,
+		[CLKID_VDEC_HEVC_SEL]	    = &gxbb_vdec_hevc_sel.hw,
+		[CLKID_VDEC_HEVC_DIV]	    = &gxbb_vdec_hevc_div.hw,
+		[CLKID_VDEC_HEVC]	    = &gxbb_vdec_hevc.hw,
 		[NR_CLKS]		    = NULL,
 	},
 	.num = NR_CLKS,
@@ -2100,6 +2208,12 @@ static struct clk_regmap *const gx_clk_regmaps[] = {
 	&gxbb_fclk_div4,
 	&gxbb_fclk_div5,
 	&gxbb_fclk_div7,
+	&gxbb_vdec_1_sel,
+	&gxbb_vdec_1_div,
+	&gxbb_vdec_1,
+	&gxbb_vdec_hevc_sel,
+	&gxbb_vdec_hevc_div,
+	&gxbb_vdec_hevc,
 };
 
 struct clkc_data {
diff --git a/drivers/clk/meson/gxbb.h b/drivers/clk/meson/gxbb.h
index 9febf3f03739..b3ef54f65a9d 100644
--- a/drivers/clk/meson/gxbb.h
+++ b/drivers/clk/meson/gxbb.h
@@ -204,8 +204,12 @@
 #define CLKID_FCLK_DIV4_DIV	  148
 #define CLKID_FCLK_DIV5_DIV	  149
 #define CLKID_FCLK_DIV7_DIV	  150
+#define CLKID_VDEC_1_SEL	  151
+#define CLKID_VDEC_1_DIV	  152
+#define CLKID_VDEC_HEVC_SEL	  154
+#define CLKID_VDEC_HEVC_DIV	  155
 
-#define NR_CLKS			  151
+#define NR_CLKS			  157
 
 /* include the CLKIDs that have been made part of the DT binding */
 #include <dt-bindings/clock/gxbb-clkc.h>
-- 
2.17.0



From maxi.jourdan at wanadoo.fr  Tue Apr 24 11:48:36 2018
From: maxi.jourdan at wanadoo.fr (Maxime Jourdan)
Date: Tue, 24 Apr 2018 20:48:36 +0200
Subject: [PATCH v2 0/2] clk: meson: gxbb: add the video decoder clocks
Message-ID: <20180424184838.3406-1-maxi.jourdan@wanadoo.fr>

This adds the necessary clocks for VDEC_1 and VDEC_HEVC.

On Amlogic SoCs, VDEC1 is responsible for the decoding of:
MPEG 1/2/4, H.263, H.264, MJPEG, VC1, Real Video

VDEC_HEVC is responsible for the decoding of:
HEVC, VP9

Changes since v1:
 - Drop CLK_IGNORE_UNUSED flags
 - Change CLK_SET_RATE_NO_REPARENT to CLK_SET_RATE_PARENT for muxes
 - Add CLK_MUX_ROUND_CLOSEST for muxes

Maxime Jourdan (2):
  clk: meson: gxbb: expose VDEC_1 and VDEC_HEVC clocks
  clk: meson: gxbb: add the video decoder clocks

 drivers/clk/meson/gxbb.c              | 114 ++++++++++++++++++++++++++
 drivers/clk/meson/gxbb.h              |   6 +-
 include/dt-bindings/clock/gxbb-clkc.h |   2 +
 3 files changed, 121 insertions(+), 1 deletion(-)

-- 
2.17.0



From maxi.jourdan at wanadoo.fr  Tue Apr 24 11:48:37 2018
From: maxi.jourdan at wanadoo.fr (Maxime Jourdan)
Date: Tue, 24 Apr 2018 20:48:37 +0200
Subject: [PATCH v2 1/2] clk: meson: gxbb: expose VDEC_1 and VDEC_HEVC clocks
In-Reply-To: <20180424184838.3406-1-maxi.jourdan@wanadoo.fr>
References: <20180424184838.3406-1-maxi.jourdan@wanadoo.fr>
Message-ID: <20180424184838.3406-2-maxi.jourdan@wanadoo.fr>

Signed-off-by: Maxime Jourdan <maxi.jourdan at wanadoo.fr>
---
 include/dt-bindings/clock/gxbb-clkc.h | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/include/dt-bindings/clock/gxbb-clkc.h b/include/dt-bindings/clock/gxbb-clkc.h
index 8ba99a5e3fd3..7a892be90549 100644
--- a/include/dt-bindings/clock/gxbb-clkc.h
+++ b/include/dt-bindings/clock/gxbb-clkc.h
@@ -125,5 +125,7 @@
 #define CLKID_VAPB_1		138
 #define CLKID_VAPB_SEL		139
 #define CLKID_VAPB		140
+#define CLKID_VDEC_1		153
+#define CLKID_VDEC_HEVC		156
 
 #endif /* __GXBB_CLKC_H */
-- 
2.17.0



From jbrunet at baylibre.com  Wed Apr 25 02:52:54 2018
From: jbrunet at baylibre.com (Jerome Brunet)
Date: Wed, 25 Apr 2018 11:52:54 +0200
Subject: [GIT PULL] Amlogic clock fixes for v4.17-rc
Message-ID: <1524649974.4026.51.camel@baylibre.com>

Dear clock maintainers,

Below is a request to pull amlogic clock fixes for v4.17.
These changes fixes a few simple mistakes I did while reworking meson clock
providers in the last cycle.

Cheers

The following changes since commit 60cc43fc888428bb2f18f08997432d426a243338:

  Linux 4.17-rc1 (2018-04-15 18:24:20 -0700)

are available in the Git repository at:

  git://github.com/BayLibre/clk-meson.git tags/meson-clk-fixes-4.17-1

for you to fetch changes up to 5b33139b1a08eabcba7b39d8a4babd7fc2d3b534:

  clk: meson: meson8b: fix meson8b_cpu_clk parent clock name (2018-04-25
10:23:19 +0200)

----------------------------------------------------------------
First round of fixes for meson clocks targeted for v4.17
 - fix typos in two meson8 clock names
 - remove unused clock ops declaration

----------------------------------------------------------------
Martin Blumenstingl (2):
      clk: meson: meson8b: fix meson8b_fclk_div3_div clock name
      clk: meson: meson8b: fix meson8b_cpu_clk parent clock name

Yixun Lan (1):
      clk: meson: drop meson_aoclk_gate_regmap_ops

 drivers/clk/meson/gxbb-aoclk.h | 2 --
 drivers/clk/meson/meson8b.c    | 5 +++--
 2 files changed, 3 insertions(+), 4 deletions(-)


From jbrunet at baylibre.com  Wed Apr 25 02:59:56 2018
From: jbrunet at baylibre.com (Jerome Brunet)
Date: Wed, 25 Apr 2018 11:59:56 +0200
Subject: [PATCH 1/2] clk: honor CLK_MUX_ROUND_CLOSEST in generic clk mux
In-Reply-To: <CAAEAJfDgGYu9WR5+qA-trQUTkb--bam=LLbhH+1N2OdrtBGLzA@mail.gmail.com>
References: <20180409135921.5617-1-jbrunet@baylibre.com>
 <20180409135921.5617-2-jbrunet@baylibre.com>
 <CAAEAJfDgGYu9WR5+qA-trQUTkb--bam=LLbhH+1N2OdrtBGLzA@mail.gmail.com>
Message-ID: <1524650396.4026.55.camel@baylibre.com>

On Tue, 2018-04-24 at 11:04 -0300, Ezequiel Garcia wrote:
> >   }
> > +EXPORT_SYMBOL_GPL(clk_mux_determine_rate_flags);
> > 
> 
> Why do we need to export this?

Because any driver implementing some type of mux may use this function, and the
driver could be a module. I have one in the pipe right now.

It is the same as __clk_determine_rate(), __clk_mux_determine_rate_closest()


From jbrunet at baylibre.com  Wed Apr 25 03:07:23 2018
From: jbrunet at baylibre.com (Jerome Brunet)
Date: Wed, 25 Apr 2018 12:07:23 +0200
Subject: [PATCH v4 1/2] dt-bindings: clock: meson8b: export the NAND clock
In-Reply-To: <20180423193509.30584-2-martin.blumenstingl@googlemail.com>
References: <20180423193509.30584-1-martin.blumenstingl@googlemail.com>
 <20180423193509.30584-2-martin.blumenstingl@googlemail.com>
Message-ID: <1524650843.4026.58.camel@baylibre.com>

On Mon, 2018-04-23 at 21:35 +0200, Martin Blumenstingl wrote:
> Export the NAND clock to the dt-bindings.
> 
> Signed-off-by: Martin Blumenstingl <martin.blumenstingl at googlemail.com>
> Acked-by: Jerome Brunet <jbrunet at baylibre.com>
> ---
>  include/dt-bindings/clock/meson8b-clkc.h | 1 +
>  1 file changed, 1 insertion(+)

applied to next/headers.
Thx


From jbrunet at baylibre.com  Wed Apr 25 04:37:25 2018
From: jbrunet at baylibre.com (Jerome Brunet)
Date: Wed, 25 Apr 2018 13:37:25 +0200
Subject: [PATCH v2 1/2] clk: meson: gxbb: expose VDEC_1 and VDEC_HEVC
 clocks
In-Reply-To: <20180424184838.3406-2-maxi.jourdan@wanadoo.fr>
References: <20180424184838.3406-1-maxi.jourdan@wanadoo.fr>
 <20180424184838.3406-2-maxi.jourdan@wanadoo.fr>
Message-ID: <1524656245.4026.61.camel@baylibre.com>

On Tue, 2018-04-24 at 20:48 +0200, Maxime Jourdan wrote:
> Signed-off-by: Maxime Jourdan <maxi.jourdan at wanadoo.fr>

Even if the change is trivial, please add commit description.
I'll do it for you this time.

Applied to next/headers
Thx

> ---
>  include/dt-bindings/clock/gxbb-clkc.h | 2 ++
>  1 file changed, 2 insertions(+)
> 
> diff --git a/include/dt-bindings/clock/gxbb-clkc.h b/include/dt-bindings/clock/gxbb-clkc.h
> index 8ba99a5e3fd3..7a892be90549 100644
> --- a/include/dt-bindings/clock/gxbb-clkc.h
> +++ b/include/dt-bindings/clock/gxbb-clkc.h
> @@ -125,5 +125,7 @@
>  #define CLKID_VAPB_1		138
>  #define CLKID_VAPB_SEL		139
>  #define CLKID_VAPB		140
> +#define CLKID_VDEC_1		153
> +#define CLKID_VDEC_HEVC		156
>  
>  #endif /* __GXBB_CLKC_H */



From jbrunet at baylibre.com  Wed Apr 25 05:02:44 2018
From: jbrunet at baylibre.com (Jerome Brunet)
Date: Wed, 25 Apr 2018 14:02:44 +0200
Subject: [PATCH v4 2/2] clk: meson: meson8b: add support for the NAND
 clocks
In-Reply-To: <20180423193509.30584-3-martin.blumenstingl@googlemail.com>
References: <20180423193509.30584-1-martin.blumenstingl@googlemail.com>
 <20180423193509.30584-3-martin.blumenstingl@googlemail.com>
Message-ID: <1524657764.4026.62.camel@baylibre.com>

On Mon, 2018-04-23 at 21:35 +0200, Martin Blumenstingl wrote:
> This adds the NAND clocks (from the HHI_NAND_CLK_CNTL register) to the
> Meson8b clock driver. There are three NAND clocks: a gate which enables
> or disables the NAND clock, a mux and a divider (which divides the mux
> output).
> Unfortunately the public S805 datasheet does not document the mux
> parents. However, the vendor kernel has a few hints for us which allows
> us to make an educated guess about the clock parents. To do this we need
> to have a look at set_nand_core_clk() from the vendor's NAND driver (see
> [0]):
> - XTAL = (4<<9) | (1<<8) | 0
> - 160MHz = (0<<9) | (1<<8) | 3)
> - 182MHz = (3<<9) | (1<<8) | 1)
> - 212MHz = (1<<9) | (1<<8) | 3)
> - 255MHz = (2<<9) | (1<<8) | 1)
> 
> While there is a comment for the XTAL parent (which indicates that it
> should only be used for debugging) we have to do a bit of math for the
> other parents: target_freq * divider = rate of parent clock
> Bit 8 above is the enable bit, so we can ignore it here. Bits 11:9 are
> the mux index and bits 6:0 are the 0-based divider (so we need to add
> 1). This gives us:
> - mux 0 (160MHz * 4) = fclk_div4 (actual rate = 637.5MHz, off by 2.5MHz)
> - mux 1 (212MHz * 4) = fclk_div3 (actual rate = 850MHz, off by 2MHz)
> - mux 2 (255MHz * 2) = fclk_div5 (matches exactly 510MHz)
> - mux 3 (182MHz * 2) = fclk_div7 (actual rate = 346.3MHz, off by 0.3MHz)
> 
> [0] https://github.com/khadas/linux/blob/9587681285cb/drivers/amlogic/amlnf/dev/amlnf_ctrl.c#L314
> 
> Signed-off-by: Martin Blumenstingl <martin.blumenstingl at googlemail.com>

applied to next/drivers
Thx


From jbrunet at baylibre.com  Wed Apr 25 05:03:06 2018
From: jbrunet at baylibre.com (Jerome Brunet)
Date: Wed, 25 Apr 2018 14:03:06 +0200
Subject: [PATCH v2 2/2] clk: meson: gxbb: add the video decoder clocks
In-Reply-To: <20180424184838.3406-3-maxi.jourdan@wanadoo.fr>
References: <20180424184838.3406-1-maxi.jourdan@wanadoo.fr>
 <20180424184838.3406-3-maxi.jourdan@wanadoo.fr>
Message-ID: <1524657786.4026.63.camel@baylibre.com>

On Tue, 2018-04-24 at 20:48 +0200, Maxime Jourdan wrote:
> Add the SEL/DIV/GATE for VDEC_1 and VDEC_HEVC.
> 
> Signed-off-by: Maxime Jourdan <maxi.jourdan at wanadoo.fr>

Applied to next/drivers
Thx


From jbrunet at baylibre.com  Wed Apr 25 06:05:12 2018
From: jbrunet at baylibre.com (Jerome Brunet)
Date: Wed, 25 Apr 2018 15:05:12 +0200
Subject: [PATCH v6 0/7] clk: meson-axg: Add AO Cloclk and Reset driver
In-Reply-To: <20180419135426.155794-1-yixun.lan@amlogic.com>
References: <20180419135426.155794-1-yixun.lan@amlogic.com>
Message-ID: <1524661512.4026.67.camel@baylibre.com>

On Thu, 2018-04-19 at 21:54 +0800, Yixun Lan wrote:
>   This patch try to add AO clock and Reset driver for Amlogic's
> Meson-AXG SoC.
>   Please note that patch 7 need to wait for the DTS changes[3] merged
> into mainline first, otherwise it will break the serial console.
> 
>  patch 2: factor the common code into a dedicated file
>  patch 3-5: add the aoclk driver for AXG SoC
>  patch 6-7: drop unnecessary clock flags
> 
> changes since v5 at [6]: 
>  - drop unnecessary header files
>  - add 'axg_aoclk' prefix to clk driver, make them more consistent
>  - add missing end new line..
> 
> changes since v4 at [5]: 
>  - fix return err
>  - introduce CONFIG_COMMON_CLK_MESON_AO
>  - format/style minor fix
> 
> changes since v3 at [4]: 
>  - add 'const' contraint to the read-only data
>  - switch to devm_of_clk_add_hw_provider API
>  - check return value of devm_reset_controller_register
> 
> changes since v2 at [2]: 
>  - rework meson_aoclkc_probe() which leverage the of_match_data
>  - merge patch 5-6 into this series
>  - seperate DTS patch, will send to Kevin Hilman independently
>  
> changes since v1 at [0]: 
>  - rebase to clk-meson's branch 'next/drivers' [1]
>  - fix license, update to BSD-3-Clause
>  - drop un-used include header file
> 
> [0] https://lkml.kernel.org/r/20180209070026.193879-1-yixun.lan at amlogic.com
> [1] git://github.com/BayLibre/clk-meson.git branch: next-drivers
> [2] https://lkml.kernel.org/r/20180323143816.200573-1-yixun.lan at amlogic.com
> [3] https://lkml.kernel.org/r/20180326081809.49493-4-yixun.lan at amlogic.com
> [4] https://lkml.kernel.org/r/20180328025050.221585-1-yixun.lan at amlogic.com
> [5] https://lkml.kernel.org/r/20180408031938.153474-1-yixun.lan at amlogic.com
> [6] https://lkml.kernel.org/r/20180409143749.71197-1-yixun.lan at amlogic.com

Yixun

Please :
 - Fix checkpatch error in patch 5 
 - Collect Philip's Ack on patch 4
 - Remove the extra new lines at EOF in patch 2 (maybe others, I did not check
them all) - 1 new line at the end of each file, not 2.

Regards
Jerome




From yixun.lan at amlogic.com  Wed Apr 25 07:32:08 2018
From: yixun.lan at amlogic.com (Yixun Lan)
Date: Wed, 25 Apr 2018 22:32:08 +0800
Subject: [PATCH v6 0/7] clk: meson-axg: Add AO Cloclk and Reset driver
In-Reply-To: <1524661512.4026.67.camel@baylibre.com>
References: <20180419135426.155794-1-yixun.lan@amlogic.com>
 <1524661512.4026.67.camel@baylibre.com>
Message-ID: <2a307212-ea12-e7a1-cf6a-9fd7d9e9bb40@amlogic.com>

Hi Jerome:

On 04/25/2018 09:05 PM, Jerome Brunet wrote:
> On Thu, 2018-04-19 at 21:54 +0800, Yixun Lan wrote:
>>   This patch try to add AO clock and Reset driver for Amlogic's
>> Meson-AXG SoC.
>>   Please note that patch 7 need to wait for the DTS changes[3] merged
>> into mainline first, otherwise it will break the serial console.
>>
>>  patch 2: factor the common code into a dedicated file
>>  patch 3-5: add the aoclk driver for AXG SoC
>>  patch 6-7: drop unnecessary clock flags
>>
>> changes since v5 at [6]: 
>>  - drop unnecessary header files
>>  - add 'axg_aoclk' prefix to clk driver, make them more consistent
>>  - add missing end new line..
>>
>> changes since v4 at [5]: 
>>  - fix return err
>>  - introduce CONFIG_COMMON_CLK_MESON_AO
>>  - format/style minor fix
>>
>> changes since v3 at [4]: 
>>  - add 'const' contraint to the read-only data
>>  - switch to devm_of_clk_add_hw_provider API
>>  - check return value of devm_reset_controller_register
>>
>> changes since v2 at [2]: 
>>  - rework meson_aoclkc_probe() which leverage the of_match_data
>>  - merge patch 5-6 into this series
>>  - seperate DTS patch, will send to Kevin Hilman independently
>>  
>> changes since v1 at [0]: 
>>  - rebase to clk-meson's branch 'next/drivers' [1]
>>  - fix license, update to BSD-3-Clause
>>  - drop un-used include header file
>>
>> [0] https://lkml.kernel.org/r/20180209070026.193879-1-yixun.lan at amlogic.com
>> [1] git://github.com/BayLibre/clk-meson.git branch: next-drivers
>> [2] https://lkml.kernel.org/r/20180323143816.200573-1-yixun.lan at amlogic.com
>> [3] https://lkml.kernel.org/r/20180326081809.49493-4-yixun.lan at amlogic.com
>> [4] https://lkml.kernel.org/r/20180328025050.221585-1-yixun.lan at amlogic.com
>> [5] https://lkml.kernel.org/r/20180408031938.153474-1-yixun.lan at amlogic.com
>> [6] https://lkml.kernel.org/r/20180409143749.71197-1-yixun.lan at amlogic.com
> 
> Yixun
> 
> Please :
>  - Fix checkpatch error in patch 5 
>  - Collect Philip's Ack on patch 4
I've fixed above two

>  - Remove the extra new lines at EOF in patch 2 (maybe others, I did not check
> them all) - 1 new line at the end of each file, not 2.
> 

but, I just go back and check the patch, couldn't find any file which
end with 2 new lines at EOF, could you point me out?


Yixun




From jbrunet at baylibre.com  Wed Apr 25 09:33:03 2018
From: jbrunet at baylibre.com (Jerome Brunet)
Date: Wed, 25 Apr 2018 18:33:03 +0200
Subject: [PATCH 6/7] clk: meson: axg: document bindings for the audio clock
 controller
In-Reply-To: <20180425163304.10852-1-jbrunet@baylibre.com>
References: <20180425163304.10852-1-jbrunet@baylibre.com>
Message-ID: <20180425163304.10852-7-jbrunet@baylibre.com>

Add documentation for the device tree bindings of the audio clock
controller of the A113 based SoCs

Signed-off-by: Jerome Brunet <jbrunet at baylibre.com>
---
 .../bindings/clock/amlogic,axg-audio-clkc.txt      | 56 ++++++++++++++++++++++
 1 file changed, 56 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/clock/amlogic,axg-audio-clkc.txt

diff --git a/Documentation/devicetree/bindings/clock/amlogic,axg-audio-clkc.txt b/Documentation/devicetree/bindings/clock/amlogic,axg-audio-clkc.txt
new file mode 100644
index 000000000000..1b989ceda567
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/amlogic,axg-audio-clkc.txt
@@ -0,0 +1,56 @@
+* Amlogic AXG Audio Clock Controllers
+
+The Amlogic AXG audio clock controller generates and supplies clock to the
+other elements of the audio subsystem, such as fifos, i2s, spdif and pdm
+devices.
+
+Required Properties:
+
+- compatible	: should be "amlogic,axg-audio-clkc" for the A113X and A113D
+- reg		: physical base address of the clock controller and length of
+		  memory mapped region.
+- clocks	: a list of phandle + clock-specifier pairs for the clocks listed
+		  in clock-names.
+- clock-names	: must contain the following:
+		  * "pclk" - Main peripheral bus clock
+		  may contain the following:
+		  * "mst_in[0-7]" - 8 input plls to generate clock signals
+		  * "slv_sclk[0-9]" - 10 slave bit clocks provided by external
+				      components.
+		  * "slv_lrclk[0-9]" - 10 slave sample clocks provided by external
+				       components.
+- reset		: phandle of the internal reset line
+- #clock-cells	: should be 1.
+
+Each clock is assigned an identifier and client nodes can use this identifier
+to specify the clock which they consume. All available clocks are defined as
+preprocessor macros in the dt-bindings/clock/axg-audio-clkc.h header and can be
+used in device tree sources.
+
+Example:
+
+clkc_audio: clock-controller {
+	compatible = "amlogic,axg-audio-clkc";
+	reg = <0x0 0x0 0x0 0xb4>;
+	#clock-cells = <1>;
+
+	clocks = <&clkc CLKID_AUDIO>,
+		 <&clkc CLKID_MPLL0>,
+		 <&clkc CLKID_MPLL1>,
+		 <&clkc CLKID_MPLL2>,
+		 <&clkc CLKID_MPLL3>,
+		 <&clkc CLKID_HIFI_PLL>,
+		 <&clkc CLKID_FCLK_DIV3>,
+		 <&clkc CLKID_FCLK_DIV4>,
+		 <&clkc CLKID_GP0_PLL>;
+	clock-names = "pclk",
+		      "mst_in0",
+		      "mst_in1",
+		      "mst_in2",
+		      "mst_in3",
+		      "mst_in4",
+		      "mst_in5",
+		      "mst_in6",
+		      "mst_in7";
+	resets = <&reset RESET_AUDIO>;
+};
-- 
2.14.3



From jbrunet at baylibre.com  Wed Apr 25 09:32:57 2018
From: jbrunet at baylibre.com (Jerome Brunet)
Date: Wed, 25 Apr 2018 18:32:57 +0200
Subject: [PATCH 0/7] clk: meson: axg: add audio clock controller support
Message-ID: <20180425163304.10852-1-jbrunet@baylibre.com>

The purpose of this patchset is to add support for the clock controller
dedicated to the audio subsystem found on A113 based SoCs

The series depends on the CLK_MUX_ROUND_CLOSEST fixes [0] and the duty
cycle support [1] making their way into CCF.

First patch is a clean-up of the meson clk Kconfig.
Then, there is 3 clock provider drivers for clocks found in the audio
The last 3 are for the clock controller itself.

[0]: https://lkml.kernel.org/r/152389589448.51482.15489333464741262913 at swboyd.mtv.corp.google.com
[1]: https://lkml.kernel.org/r/20180420211141.28929-1-jbrunet at baylibre.com

Jerome Brunet (7):
  clk: meson: clean-up meson clock configuration
  clk: meson: add clk-phase clock driver
  clk: meson: add triple phase clock driver
  clk: meson: add axg audio sclk divider driver
  clk: meson: axg: export audio clock controller id bindings
  clk: meson: axg: document bindings for the audio clock controller
  clk: meson: axg: add the audio clock controller driver

 .../bindings/clock/amlogic,axg-audio-clkc.txt      |  56 ++
 drivers/clk/meson/Kconfig                          |  25 +-
 drivers/clk/meson/Makefile                         |   3 +
 drivers/clk/meson/axg-audio.c                      | 845 +++++++++++++++++++++
 drivers/clk/meson/axg-audio.h                      | 127 ++++
 drivers/clk/meson/clk-phase.c                      |  63 ++
 drivers/clk/meson/clk-triphase.c                   |  68 ++
 drivers/clk/meson/clkc-audio.h                     |  28 +
 drivers/clk/meson/clkc.h                           |   8 +
 drivers/clk/meson/sclk-div.c                       | 243 ++++++
 include/dt-bindings/clock/axg-audio-clkc.h         |  94 +++
 11 files changed, 1553 insertions(+), 7 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/clock/amlogic,axg-audio-clkc.txt
 create mode 100644 drivers/clk/meson/axg-audio.c
 create mode 100644 drivers/clk/meson/axg-audio.h
 create mode 100644 drivers/clk/meson/clk-phase.c
 create mode 100644 drivers/clk/meson/clk-triphase.c
 create mode 100644 drivers/clk/meson/clkc-audio.h
 create mode 100644 drivers/clk/meson/sclk-div.c
 create mode 100644 include/dt-bindings/clock/axg-audio-clkc.h

-- 
2.14.3



From jbrunet at baylibre.com  Wed Apr 25 09:32:58 2018
From: jbrunet at baylibre.com (Jerome Brunet)
Date: Wed, 25 Apr 2018 18:32:58 +0200
Subject: [PATCH 1/7] clk: meson: clean-up meson clock configuration
In-Reply-To: <20180425163304.10852-1-jbrunet@baylibre.com>
References: <20180425163304.10852-1-jbrunet@baylibre.com>
Message-ID: <20180425163304.10852-2-jbrunet@baylibre.com>

Clean the dependencies in meson clock Kconfig.
CLK_AMLOGIC should actually select CLK_REGMAP_MESON which it uses. Also,
each platform should select CLK_AMLOGIC, so everything is properly turned
on when the platform Kconfig enable each configuration flag

Signed-off-by: Jerome Brunet <jbrunet at baylibre.com>
---
 drivers/clk/meson/Kconfig | 11 ++++-------
 1 file changed, 4 insertions(+), 7 deletions(-)

diff --git a/drivers/clk/meson/Kconfig b/drivers/clk/meson/Kconfig
index d5cbec522aec..87d69573e172 100644
--- a/drivers/clk/meson/Kconfig
+++ b/drivers/clk/meson/Kconfig
@@ -1,7 +1,7 @@
 config COMMON_CLK_AMLOGIC
 	bool
-	depends on OF
 	depends on ARCH_MESON || COMPILE_TEST
+	select COMMON_CLK_REGMAP_MESON
 
 config COMMON_CLK_REGMAP_MESON
 	bool
@@ -9,9 +9,8 @@ config COMMON_CLK_REGMAP_MESON
 
 config COMMON_CLK_MESON8B
 	bool
-	depends on COMMON_CLK_AMLOGIC
+	select COMMON_CLK_AMLOGIC
 	select RESET_CONTROLLER
-	select COMMON_CLK_REGMAP_MESON
 	help
 	  Support for the clock controller on AmLogic S802 (Meson8),
 	  S805 (Meson8b) and S812 (Meson8m2) devices. Say Y if you
@@ -19,9 +18,8 @@ config COMMON_CLK_MESON8B
 
 config COMMON_CLK_GXBB
 	bool
-	depends on COMMON_CLK_AMLOGIC
+	select COMMON_CLK_AMLOGIC
 	select RESET_CONTROLLER
-	select COMMON_CLK_REGMAP_MESON
 	select MFD_SYSCON
 	help
 	  Support for the clock controller on AmLogic S905 devices, aka gxbb.
@@ -29,9 +27,8 @@ config COMMON_CLK_GXBB
 
 config COMMON_CLK_AXG
 	bool
-	depends on COMMON_CLK_AMLOGIC
+	select COMMON_CLK_AMLOGIC
 	select RESET_CONTROLLER
-	select COMMON_CLK_REGMAP_MESON
 	select MFD_SYSCON
 	help
 	  Support for the clock controller on AmLogic A113D devices, aka axg.
-- 
2.14.3



From jbrunet at baylibre.com  Wed Apr 25 09:33:01 2018
From: jbrunet at baylibre.com (Jerome Brunet)
Date: Wed, 25 Apr 2018 18:33:01 +0200
Subject: [PATCH 4/7] clk: meson: add axg audio sclk divider driver
In-Reply-To: <20180425163304.10852-1-jbrunet@baylibre.com>
References: <20180425163304.10852-1-jbrunet@baylibre.com>
Message-ID: <20180425163304.10852-5-jbrunet@baylibre.com>

Add a driver to control the clock divider found in the sample clock
generator of the axg audio clock controller.

The sclk divider accumulates specific features which make the generic
divider unsuitable to control it:
- zero based divider (div = val + 1), but zero value gates the clock,
  so minimum divider value is 2.
- lrclk variant may adjust the duty cycle depending the divider value
  and the 'hi' value.

Signed-off-by: Jerome Brunet <jbrunet at baylibre.com>
---
 drivers/clk/meson/Makefile     |   2 +-
 drivers/clk/meson/clkc-audio.h |   8 ++
 drivers/clk/meson/sclk-div.c   | 243 +++++++++++++++++++++++++++++++++++++++++
 3 files changed, 252 insertions(+), 1 deletion(-)
 create mode 100644 drivers/clk/meson/sclk-div.c

diff --git a/drivers/clk/meson/Makefile b/drivers/clk/meson/Makefile
index 64bb917fe1f0..f51b4754c31b 100644
--- a/drivers/clk/meson/Makefile
+++ b/drivers/clk/meson/Makefile
@@ -4,7 +4,7 @@
 
 obj-$(CONFIG_COMMON_CLK_AMLOGIC) += clk-pll.o clk-mpll.o clk-audio-divider.o
 obj-$(CONFIG_COMMON_CLK_AMLOGIC) += clk-phase.o
-obj-$(CONFIG_COMMON_CLK_AMLOGIC_AUDIO)	+= clk-triphase.o
+obj-$(CONFIG_COMMON_CLK_AMLOGIC_AUDIO)	+= clk-triphase.o sclk-div.o
 obj-$(CONFIG_COMMON_CLK_MESON8B) += meson8b.o
 obj-$(CONFIG_COMMON_CLK_GXBB)	 += gxbb.o gxbb-aoclk.o gxbb-aoclk-32k.o
 obj-$(CONFIG_COMMON_CLK_AXG)	 += axg.o
diff --git a/drivers/clk/meson/clkc-audio.h b/drivers/clk/meson/clkc-audio.h
index 286ff1201258..0a7c157ebf81 100644
--- a/drivers/clk/meson/clkc-audio.h
+++ b/drivers/clk/meson/clkc-audio.h
@@ -15,6 +15,14 @@ struct meson_clk_triphase_data {
 	struct parm ph2;
 };
 
+struct meson_sclk_div_data {
+	struct parm div;
+	struct parm hi;
+	unsigned int cached_div;
+	struct clk_duty cached_duty;
+};
+
 extern const struct clk_ops meson_clk_triphase_ops;
+extern const struct clk_ops meson_sclk_div_ops;
 
 #endif /* __MESON_CLKC_AUDIO_H */
diff --git a/drivers/clk/meson/sclk-div.c b/drivers/clk/meson/sclk-div.c
new file mode 100644
index 000000000000..8c0bc914a6d7
--- /dev/null
+++ b/drivers/clk/meson/sclk-div.c
@@ -0,0 +1,243 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2018 BayLibre, SAS.
+ * Author: Jerome Brunet <jbrunet at baylibre.com>
+ *
+ * Sample clock generator divider:
+ * This HW divider gates with value 0 but is otherwise a zero based divider:
+ *
+ * val >= 1
+ * divider = val + 1
+ *
+ * The duty cycle may also be set for the LR clock variant. The duty cycle
+ * ratio is:
+ *
+ * hi = [0 - val]
+ * duty_cycle = (1 + hi) / (1 + val)
+ */
+
+#include "clkc-audio.h"
+
+static inline struct meson_sclk_div_data *
+meson_sclk_div_data(struct clk_regmap *clk)
+{
+	return (struct meson_sclk_div_data *)clk->data;
+}
+
+static int sclk_div_maxval(struct meson_sclk_div_data *sclk)
+{
+	return (1 << sclk->div.width) - 1;
+}
+
+static int sclk_div_maxdiv(struct meson_sclk_div_data *sclk)
+{
+	return sclk_div_maxval(sclk) + 1;
+}
+
+static int sclk_div_getdiv(struct clk_hw *hw, unsigned long rate,
+			   unsigned long prate, int maxdiv)
+{
+	int div = DIV_ROUND_CLOSEST_ULL((u64)prate, rate);
+
+	return clamp(div, 2, maxdiv);
+}
+
+static int sclk_div_bestdiv(struct clk_hw *hw, unsigned long rate,
+			    unsigned long *prate,
+			    struct meson_sclk_div_data *sclk)
+{
+	struct clk_hw *parent = clk_hw_get_parent(hw);
+	int bestdiv = 0, i;
+	unsigned long maxdiv, now, parent_now;
+	unsigned long best = 0, best_parent = 0;
+
+	if (!rate)
+		rate = 1;
+
+	maxdiv = sclk_div_maxdiv(sclk);
+
+	if (!(clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT))
+		return sclk_div_getdiv(hw, rate, *prate, maxdiv);
+
+	/*
+	 * The maximum divider we can use without overflowing
+	 * unsigned long in rate * i below
+	 */
+	maxdiv = min(ULONG_MAX / rate, maxdiv);
+
+	for (i = 2; i <= maxdiv; i++) {
+		/*
+		 * It's the most ideal case if the requested rate can be
+		 * divided from parent clock without needing to change
+		 * parent rate, so return the divider immediately.
+		 */
+		if (rate * i == *prate)
+			return i;
+
+		parent_now = clk_hw_round_rate(parent, rate * i);
+		now = DIV_ROUND_UP_ULL((u64)parent_now, i);
+
+		if (abs(rate - now) < abs(rate - best)) {
+			bestdiv = i;
+			best = now;
+			best_parent = parent_now;
+		}
+	}
+
+	if (!bestdiv)
+		bestdiv = sclk_div_maxdiv(sclk);
+	else
+		*prate = best_parent;
+
+	return bestdiv;
+}
+
+static long sclk_div_round_rate(struct clk_hw *hw, unsigned long rate,
+				unsigned long *prate)
+{
+	struct clk_regmap *clk = to_clk_regmap(hw);
+	struct meson_sclk_div_data *sclk = meson_sclk_div_data(clk);
+	int div;
+
+	div = sclk_div_bestdiv(hw, rate, prate, sclk);
+
+	return DIV_ROUND_UP_ULL((u64)*prate, div);
+}
+
+static void sclk_apply_ratio(struct clk_regmap *clk,
+			     struct meson_sclk_div_data *sclk)
+{
+	unsigned int hi = DIV_ROUND_CLOSEST(sclk->cached_div *
+					    sclk->cached_duty.num,
+					    sclk->cached_duty.den);
+
+	if (hi)
+		hi -= 1;
+
+	meson_parm_write(clk->map, &sclk->hi, hi);
+}
+
+static int sclk_div_set_duty_cycle(struct clk_hw *hw,
+				   struct clk_duty *duty)
+{
+	struct clk_regmap *clk = to_clk_regmap(hw);
+	struct meson_sclk_div_data *sclk = meson_sclk_div_data(clk);
+
+	if (MESON_PARM_APPLICABLE(&sclk->hi)) {
+		memcpy(&sclk->cached_duty, duty, sizeof(*duty));
+		sclk_apply_ratio(clk, sclk);
+	}
+
+	return 0;
+}
+
+static int sclk_div_get_duty_cycle(struct clk_hw *hw,
+				   struct clk_duty *duty)
+{
+	struct clk_regmap *clk = to_clk_regmap(hw);
+	struct meson_sclk_div_data *sclk = meson_sclk_div_data(clk);
+	int hi;
+
+	if (!MESON_PARM_APPLICABLE(&sclk->hi)) {
+		duty->num = 1;
+		duty->den = 2;
+		return 0;
+	}
+
+	hi = meson_parm_read(clk->map, &sclk->hi);
+	duty->num = hi + 1;
+	duty->den = sclk->cached_div;
+	return 0;
+}
+
+static void sclk_apply_divider(struct clk_regmap *clk,
+			       struct meson_sclk_div_data *sclk)
+{
+	if (MESON_PARM_APPLICABLE(&sclk->hi))
+		sclk_apply_ratio(clk, sclk);
+
+	meson_parm_write(clk->map, &sclk->div, sclk->cached_div - 1);
+}
+
+static int sclk_div_set_rate(struct clk_hw *hw, unsigned long rate,
+			     unsigned long prate)
+{
+	struct clk_regmap *clk = to_clk_regmap(hw);
+	struct meson_sclk_div_data *sclk = meson_sclk_div_data(clk);
+	unsigned long maxdiv = sclk_div_maxdiv(sclk);
+
+	sclk->cached_div = sclk_div_getdiv(hw, rate, prate, maxdiv);
+
+	if (clk_hw_is_enabled(hw))
+		sclk_apply_divider(clk, sclk);
+
+	return 0;
+}
+
+static unsigned long sclk_div_recalc_rate(struct clk_hw *hw,
+					  unsigned long prate)
+{
+	struct clk_regmap *clk = to_clk_regmap(hw);
+	struct meson_sclk_div_data *sclk = meson_sclk_div_data(clk);
+
+	return DIV_ROUND_UP_ULL((u64)prate, sclk->cached_div);
+}
+
+static int sclk_div_enable(struct clk_hw *hw)
+{
+	struct clk_regmap *clk = to_clk_regmap(hw);
+	struct meson_sclk_div_data *sclk = meson_sclk_div_data(clk);
+
+	sclk_apply_divider(clk, sclk);
+
+	return 0;
+}
+
+static void sclk_div_disable(struct clk_hw *hw)
+{
+	struct clk_regmap *clk = to_clk_regmap(hw);
+	struct meson_sclk_div_data *sclk = meson_sclk_div_data(clk);
+
+	meson_parm_write(clk->map, &sclk->div, 0);
+}
+
+static int sclk_div_is_enabled(struct clk_hw *hw)
+{
+	struct clk_regmap *clk = to_clk_regmap(hw);
+	struct meson_sclk_div_data *sclk = meson_sclk_div_data(clk);
+
+	if (meson_parm_read(clk->map, &sclk->div))
+		return 1;
+
+	return 0;
+}
+
+static void sclk_div_init(struct clk_hw *hw)
+{
+	struct clk_regmap *clk = to_clk_regmap(hw);
+	struct meson_sclk_div_data *sclk = meson_sclk_div_data(clk);
+	unsigned int val;
+
+	val = meson_parm_read(clk->map, &sclk->div);
+
+	/* if the divider is initially disabled, assume max */
+	if (!val)
+		sclk->cached_div = sclk_div_maxdiv(sclk);
+	else
+		sclk->cached_div = val + 1;
+
+	sclk_div_get_duty_cycle(hw, &sclk->cached_duty);
+}
+
+const struct clk_ops meson_sclk_div_ops = {
+	.recalc_rate	= sclk_div_recalc_rate,
+	.round_rate	= sclk_div_round_rate,
+	.set_rate	= sclk_div_set_rate,
+	.enable		= sclk_div_enable,
+	.disable	= sclk_div_disable,
+	.is_enabled	= sclk_div_is_enabled,
+	.get_duty_cycle	= sclk_div_get_duty_cycle,
+	.set_duty_cycle = sclk_div_set_duty_cycle,
+	.init		= sclk_div_init,
+};
+EXPORT_SYMBOL_GPL(meson_sclk_div_ops);
-- 
2.14.3



From jbrunet at baylibre.com  Wed Apr 25 09:32:59 2018
From: jbrunet at baylibre.com (Jerome Brunet)
Date: Wed, 25 Apr 2018 18:32:59 +0200
Subject: [PATCH 2/7] clk: meson: add clk-phase clock driver
In-Reply-To: <20180425163304.10852-1-jbrunet@baylibre.com>
References: <20180425163304.10852-1-jbrunet@baylibre.com>
Message-ID: <20180425163304.10852-3-jbrunet@baylibre.com>

Add a driver based meson clk-regmap to control clock phase on
amlogic SoCs

Signed-off-by: Jerome Brunet <jbrunet at baylibre.com>
---
 drivers/clk/meson/Makefile    |  1 +
 drivers/clk/meson/clk-phase.c | 63 +++++++++++++++++++++++++++++++++++++++++++
 drivers/clk/meson/clkc.h      |  8 ++++++
 3 files changed, 72 insertions(+)
 create mode 100644 drivers/clk/meson/clk-phase.c

diff --git a/drivers/clk/meson/Makefile b/drivers/clk/meson/Makefile
index ffee82e60b7a..352fb848c406 100644
--- a/drivers/clk/meson/Makefile
+++ b/drivers/clk/meson/Makefile
@@ -3,6 +3,7 @@
 #
 
 obj-$(CONFIG_COMMON_CLK_AMLOGIC) += clk-pll.o clk-mpll.o clk-audio-divider.o
+obj-$(CONFIG_COMMON_CLK_AMLOGIC) += clk-phase.o
 obj-$(CONFIG_COMMON_CLK_MESON8B) += meson8b.o
 obj-$(CONFIG_COMMON_CLK_GXBB)	 += gxbb.o gxbb-aoclk.o gxbb-aoclk-32k.o
 obj-$(CONFIG_COMMON_CLK_AXG)	 += axg.o
diff --git a/drivers/clk/meson/clk-phase.c b/drivers/clk/meson/clk-phase.c
new file mode 100644
index 000000000000..96e70497ef1b
--- /dev/null
+++ b/drivers/clk/meson/clk-phase.c
@@ -0,0 +1,63 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2018 BayLibre, SAS.
+ * Author: Jerome Brunet <jbrunet at baylibre.com>
+ */
+
+#include <linux/clk-provider.h>
+#include "clkc.h"
+
+#define phase_step(_width) (360 / (1 << (_width)))
+
+static inline struct meson_clk_phase_data *
+meson_clk_phase_data(struct clk_regmap *clk)
+{
+	return (struct meson_clk_phase_data *)clk->data;
+}
+
+int meson_clk_degrees_from_val(unsigned int val, unsigned int width)
+{
+	return phase_step(width) * val;
+}
+EXPORT_SYMBOL_GPL(meson_clk_degrees_from_val);
+
+unsigned int meson_clk_degrees_to_val(int degrees, unsigned int width)
+{
+	unsigned int val = DIV_ROUND_CLOSEST(degrees, phase_step(width));
+
+	/*
+	 * This last calculation is here for cases when degrees is rounded
+	 * to 360, in which case val == (1 << width).
+	 */
+	return val % (1 << width);
+}
+EXPORT_SYMBOL_GPL(meson_clk_degrees_to_val);
+
+static int meson_clk_phase_get_phase(struct clk_hw *hw)
+{
+	struct clk_regmap *clk = to_clk_regmap(hw);
+	struct meson_clk_phase_data *phase = meson_clk_phase_data(clk);
+	unsigned int val;
+
+	val = meson_parm_read(clk->map, &phase->ph);
+
+	return meson_clk_degrees_from_val(val, phase->ph.width);
+}
+
+static int meson_clk_phase_set_phase(struct clk_hw *hw, int degrees)
+{
+	struct clk_regmap *clk = to_clk_regmap(hw);
+	struct meson_clk_phase_data *phase = meson_clk_phase_data(clk);
+	unsigned int val;
+
+	val = meson_clk_degrees_to_val(degrees, phase->ph.width);
+	meson_parm_write(clk->map, &phase->ph, val);
+
+	return 0;
+}
+
+const struct clk_ops meson_clk_phase_ops = {
+	.get_phase	= meson_clk_phase_get_phase,
+	.set_phase	= meson_clk_phase_set_phase,
+};
+EXPORT_SYMBOL_GPL(meson_clk_phase_ops);
diff --git a/drivers/clk/meson/clkc.h b/drivers/clk/meson/clkc.h
index 8fe73c4edca8..9a17d6705e0a 100644
--- a/drivers/clk/meson/clkc.h
+++ b/drivers/clk/meson/clkc.h
@@ -104,6 +104,13 @@ struct meson_clk_audio_div_data {
 	u8 flags;
 };
 
+struct meson_clk_phase_data {
+	struct parm ph;
+};
+
+int meson_clk_degrees_from_val(unsigned int val, unsigned int width);
+unsigned int meson_clk_degrees_to_val(int degrees, unsigned int width);
+
 #define MESON_GATE(_name, _reg, _bit)					\
 struct clk_regmap _name = {						\
 	.data = &(struct clk_regmap_gate_data){				\
@@ -127,5 +134,6 @@ extern const struct clk_ops meson_clk_mpll_ro_ops;
 extern const struct clk_ops meson_clk_mpll_ops;
 extern const struct clk_ops meson_clk_audio_divider_ro_ops;
 extern const struct clk_ops meson_clk_audio_divider_ops;
+extern const struct clk_ops meson_clk_phase_ops;
 
 #endif /* __CLKC_H */
-- 
2.14.3



From jbrunet at baylibre.com  Wed Apr 25 09:33:00 2018
From: jbrunet at baylibre.com (Jerome Brunet)
Date: Wed, 25 Apr 2018 18:33:00 +0200
Subject: [PATCH 3/7] clk: meson: add triple phase clock driver
In-Reply-To: <20180425163304.10852-1-jbrunet@baylibre.com>
References: <20180425163304.10852-1-jbrunet@baylibre.com>
Message-ID: <20180425163304.10852-4-jbrunet@baylibre.com>

Add a driver to control the output of the sample clock generator found
in the axg audio clock controller.

The goal of this driver is to coherently control the phase provided to
the different element using the sample clock generator. This simplify
the usage of the sample clock generator a lot, without comprising the
ability of the SoC.

Signed-off-by: Jerome Brunet <jbrunet at baylibre.com>
---
 drivers/clk/meson/Kconfig        |  5 +++
 drivers/clk/meson/Makefile       |  1 +
 drivers/clk/meson/clk-triphase.c | 68 ++++++++++++++++++++++++++++++++++++++++
 drivers/clk/meson/clkc-audio.h   | 20 ++++++++++++
 4 files changed, 94 insertions(+)
 create mode 100644 drivers/clk/meson/clk-triphase.c
 create mode 100644 drivers/clk/meson/clkc-audio.h

diff --git a/drivers/clk/meson/Kconfig b/drivers/clk/meson/Kconfig
index 87d69573e172..7f7fd6fb3809 100644
--- a/drivers/clk/meson/Kconfig
+++ b/drivers/clk/meson/Kconfig
@@ -3,6 +3,11 @@ config COMMON_CLK_AMLOGIC
 	depends on ARCH_MESON || COMPILE_TEST
 	select COMMON_CLK_REGMAP_MESON
 
+config COMMON_CLK_AMLOGIC_AUDIO
+	bool
+	depends on ARCH_MESON || COMPILE_TEST
+	select COMMON_CLK_AMLOGIC
+
 config COMMON_CLK_REGMAP_MESON
 	bool
 	select REGMAP
diff --git a/drivers/clk/meson/Makefile b/drivers/clk/meson/Makefile
index 352fb848c406..64bb917fe1f0 100644
--- a/drivers/clk/meson/Makefile
+++ b/drivers/clk/meson/Makefile
@@ -4,6 +4,7 @@
 
 obj-$(CONFIG_COMMON_CLK_AMLOGIC) += clk-pll.o clk-mpll.o clk-audio-divider.o
 obj-$(CONFIG_COMMON_CLK_AMLOGIC) += clk-phase.o
+obj-$(CONFIG_COMMON_CLK_AMLOGIC_AUDIO)	+= clk-triphase.o
 obj-$(CONFIG_COMMON_CLK_MESON8B) += meson8b.o
 obj-$(CONFIG_COMMON_CLK_GXBB)	 += gxbb.o gxbb-aoclk.o gxbb-aoclk-32k.o
 obj-$(CONFIG_COMMON_CLK_AXG)	 += axg.o
diff --git a/drivers/clk/meson/clk-triphase.c b/drivers/clk/meson/clk-triphase.c
new file mode 100644
index 000000000000..9508c03c73c1
--- /dev/null
+++ b/drivers/clk/meson/clk-triphase.c
@@ -0,0 +1,68 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2018 BayLibre, SAS.
+ * Author: Jerome Brunet <jbrunet at baylibre.com>
+ */
+
+#include <linux/clk-provider.h>
+#include "clkc-audio.h"
+
+/*
+ * This is a special clock for the audio controller.
+ * The phase of mst_sclk clock output can be controlled independently
+ * for the outside world (ph0), the tdmout (ph1) and tdmin (ph2).
+ * Controlling these 3 phases as just one makes things simpler and
+ * give the same clock view to all the element on the i2s bus.
+ * If necessary, we can still control the phase in the tdm block
+ * which makes these independent control redundant.
+ */
+static inline struct meson_clk_triphase_data *
+meson_clk_triphase_data(struct clk_regmap *clk)
+{
+	return (struct meson_clk_triphase_data *)clk->data;
+}
+
+static void meson_clk_triphase_sync(struct clk_hw *hw)
+{
+	struct clk_regmap *clk = to_clk_regmap(hw);
+	struct meson_clk_triphase_data *tph = meson_clk_triphase_data(clk);
+	unsigned int val;
+
+	/* Get phase 0 and sync it to phase 1 and 2 */
+	val = meson_parm_read(clk->map, &tph->ph0);
+	meson_parm_write(clk->map, &tph->ph1, val);
+	meson_parm_write(clk->map, &tph->ph2, val);
+}
+
+static int meson_clk_triphase_get_phase(struct clk_hw *hw)
+{
+	struct clk_regmap *clk = to_clk_regmap(hw);
+	struct meson_clk_triphase_data *tph = meson_clk_triphase_data(clk);
+	unsigned int val;
+
+	/* Phase are in sync, reading phase 0 is enough */
+	val = meson_parm_read(clk->map, &tph->ph0);
+
+	return meson_clk_degrees_from_val(val, tph->ph0.width);
+}
+
+static int meson_clk_triphase_set_phase(struct clk_hw *hw, int degrees)
+{
+	struct clk_regmap *clk = to_clk_regmap(hw);
+	struct meson_clk_triphase_data *tph = meson_clk_triphase_data(clk);
+	unsigned int val;
+
+	val = meson_clk_degrees_to_val(degrees, tph->ph0.width);
+	meson_parm_write(clk->map, &tph->ph0, val);
+	meson_parm_write(clk->map, &tph->ph1, val);
+	meson_parm_write(clk->map, &tph->ph2, val);
+
+	return 0;
+}
+
+const struct clk_ops meson_clk_triphase_ops = {
+	.init		= meson_clk_triphase_sync,
+	.get_phase	= meson_clk_triphase_get_phase,
+	.set_phase	= meson_clk_triphase_set_phase,
+};
+EXPORT_SYMBOL_GPL(meson_clk_triphase_ops);
diff --git a/drivers/clk/meson/clkc-audio.h b/drivers/clk/meson/clkc-audio.h
new file mode 100644
index 000000000000..286ff1201258
--- /dev/null
+++ b/drivers/clk/meson/clkc-audio.h
@@ -0,0 +1,20 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2018 BayLibre, SAS.
+ * Author: Jerome Brunet <jbrunet at baylibre.com>
+ */
+
+#ifndef __MESON_CLKC_AUDIO_H
+#define __MESON_CLKC_AUDIO_H
+
+#include "clkc.h"
+
+struct meson_clk_triphase_data {
+	struct parm ph0;
+	struct parm ph1;
+	struct parm ph2;
+};
+
+extern const struct clk_ops meson_clk_triphase_ops;
+
+#endif /* __MESON_CLKC_AUDIO_H */
-- 
2.14.3



From jbrunet at baylibre.com  Wed Apr 25 09:33:02 2018
From: jbrunet at baylibre.com (Jerome Brunet)
Date: Wed, 25 Apr 2018 18:33:02 +0200
Subject: [PATCH 5/7] clk: meson: axg: export audio clock controller id bindings
In-Reply-To: <20180425163304.10852-1-jbrunet@baylibre.com>
References: <20180425163304.10852-1-jbrunet@baylibre.com>
Message-ID: <20180425163304.10852-6-jbrunet@baylibre.com>

export the clock ids dt-bindings usable by the consumers of the axg
audio clock controller

Signed-off-by: Jerome Brunet <jbrunet at baylibre.com>
---
 include/dt-bindings/clock/axg-audio-clkc.h | 94 ++++++++++++++++++++++++++++++
 1 file changed, 94 insertions(+)
 create mode 100644 include/dt-bindings/clock/axg-audio-clkc.h

diff --git a/include/dt-bindings/clock/axg-audio-clkc.h b/include/dt-bindings/clock/axg-audio-clkc.h
new file mode 100644
index 000000000000..4426ae655858
--- /dev/null
+++ b/include/dt-bindings/clock/axg-audio-clkc.h
@@ -0,0 +1,94 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2018 Baylibre SAS.
+ * Author: Jerome Brunet <jbrunet at baylibre.com>
+ */
+
+#ifndef __AXG_AUDIO_CLKC_BINDINGS_H
+#define __AXG_AUDIO_CLKC_BINDINGS_H
+
+#define AUD_CLKID_SLV_SCLK0		9
+#define AUD_CLKID_SLV_SCLK1		10
+#define AUD_CLKID_SLV_SCLK2		11
+#define AUD_CLKID_SLV_SCLK3		12
+#define AUD_CLKID_SLV_SCLK4		13
+#define AUD_CLKID_SLV_SCLK5		14
+#define AUD_CLKID_SLV_SCLK6		15
+#define AUD_CLKID_SLV_SCLK7		16
+#define AUD_CLKID_SLV_SCLK8		17
+#define AUD_CLKID_SLV_SCLK9		18
+#define AUD_CLKID_SLV_LRCLK0		19
+#define AUD_CLKID_SLV_LRCLK1		20
+#define AUD_CLKID_SLV_LRCLK2		21
+#define AUD_CLKID_SLV_LRCLK3		22
+#define AUD_CLKID_SLV_LRCLK4		23
+#define AUD_CLKID_SLV_LRCLK5		24
+#define AUD_CLKID_SLV_LRCLK6		25
+#define AUD_CLKID_SLV_LRCLK7		26
+#define AUD_CLKID_SLV_LRCLK8		27
+#define AUD_CLKID_SLV_LRCLK9		28
+#define AUD_CLKID_DDR_ARB		29
+#define AUD_CLKID_PDM			30
+#define AUD_CLKID_TDMIN_A		31
+#define AUD_CLKID_TDMIN_B		32
+#define AUD_CLKID_TDMIN_C		33
+#define AUD_CLKID_TDMIN_LB		34
+#define AUD_CLKID_TDMOUT_A		35
+#define AUD_CLKID_TDMOUT_B		36
+#define AUD_CLKID_TDMOUT_C		37
+#define AUD_CLKID_FRDDR_A		38
+#define AUD_CLKID_FRDDR_B		39
+#define AUD_CLKID_FRDDR_C		40
+#define AUD_CLKID_TODDR_A		41
+#define AUD_CLKID_TODDR_B		42
+#define AUD_CLKID_TODDR_C		43
+#define AUD_CLKID_LOOPBACK		44
+#define AUD_CLKID_SPDIFIN		45
+#define AUD_CLKID_SPDIFOUT		46
+#define AUD_CLKID_RESAMPLE		47
+#define AUD_CLKID_POWER_DETECT		48
+#define AUD_CLKID_MST_A_MCLK		49
+#define AUD_CLKID_MST_B_MCLK		50
+#define AUD_CLKID_MST_C_MCLK		51
+#define AUD_CLKID_MST_D_MCLK		52
+#define AUD_CLKID_MST_E_MCLK		53
+#define AUD_CLKID_MST_F_MCLK		54
+#define AUD_CLKID_SPDIFOUT_CLK		55
+#define AUD_CLKID_SPDIFIN_CLK		56
+#define AUD_CLKID_PDM_DCLK		57
+#define AUD_CLKID_PDM_SYSCLK		58
+#define AUD_CLKID_MST_A_SCLK		79
+#define AUD_CLKID_MST_B_SCLK		80
+#define AUD_CLKID_MST_C_SCLK		81
+#define AUD_CLKID_MST_D_SCLK		82
+#define AUD_CLKID_MST_E_SCLK		83
+#define AUD_CLKID_MST_F_SCLK		84
+#define AUD_CLKID_MST_A_LRCLK		86
+#define AUD_CLKID_MST_B_LRCLK		87
+#define AUD_CLKID_MST_C_LRCLK		88
+#define AUD_CLKID_MST_D_LRCLK		89
+#define AUD_CLKID_MST_E_LRCLK		90
+#define AUD_CLKID_MST_F_LRCLK		91
+#define AUD_CLKID_TDMIN_A_SCLK_SEL	116
+#define AUD_CLKID_TDMIN_B_SCLK_SEL	117
+#define AUD_CLKID_TDMIN_C_SCLK_SEL	118
+#define AUD_CLKID_TDMIN_LB_SCLK_SEL	119
+#define AUD_CLKID_TDMOUT_A_SCLK_SEL	120
+#define AUD_CLKID_TDMOUT_B_SCLK_SEL	121
+#define AUD_CLKID_TDMOUT_C_SCLK_SEL	122
+#define AUD_CLKID_TDMIN_A_SCLK		123
+#define AUD_CLKID_TDMIN_B_SCLK		124
+#define AUD_CLKID_TDMIN_C_SCLK		125
+#define AUD_CLKID_TDMIN_LB_SCLK		126
+#define AUD_CLKID_TDMOUT_A_SCLK		127
+#define AUD_CLKID_TDMOUT_B_SCLK		128
+#define AUD_CLKID_TDMOUT_C_SCLK		129
+#define AUD_CLKID_TDMIN_A_LRCLK		130
+#define AUD_CLKID_TDMIN_B_LRCLK		131
+#define AUD_CLKID_TDMIN_C_LRCLK		132
+#define AUD_CLKID_TDMIN_LB_LRCLK	133
+#define AUD_CLKID_TDMOUT_A_LRCLK	134
+#define AUD_CLKID_TDMOUT_B_LRCLK	135
+#define AUD_CLKID_TDMOUT_C_LRCLK	136
+
+#endif /* __AXG_AUDIO_CLKC_BINDINGS_H */
-- 
2.14.3



From jbrunet at baylibre.com  Wed Apr 25 09:33:04 2018
From: jbrunet at baylibre.com (Jerome Brunet)
Date: Wed, 25 Apr 2018 18:33:04 +0200
Subject: [PATCH 7/7] clk: meson: axg: add the audio clock controller driver
In-Reply-To: <20180425163304.10852-1-jbrunet@baylibre.com>
References: <20180425163304.10852-1-jbrunet@baylibre.com>
Message-ID: <20180425163304.10852-8-jbrunet@baylibre.com>

The axg audio clock controller is the clock generation unit for the
amlogic audio subsystem of A113 based SoCs. It may be clocked by 8
different plls provided by the primary clock controller and also by
10 slave bit clocks and 10 slave sample clocks which may be provided
by external components, such as audio codecs, through the SoC pads.

It contains several muxes, dividers and gates which are fed into the
the different devices of the audio subsystem.

Signed-off-by: Jerome Brunet <jbrunet at baylibre.com>
---
 drivers/clk/meson/Kconfig     |   9 +
 drivers/clk/meson/Makefile    |   1 +
 drivers/clk/meson/axg-audio.c | 845 ++++++++++++++++++++++++++++++++++++++++++
 drivers/clk/meson/axg-audio.h | 127 +++++++
 4 files changed, 982 insertions(+)
 create mode 100644 drivers/clk/meson/axg-audio.c
 create mode 100644 drivers/clk/meson/axg-audio.h

diff --git a/drivers/clk/meson/Kconfig b/drivers/clk/meson/Kconfig
index 7f7fd6fb3809..006fa1204e5b 100644
--- a/drivers/clk/meson/Kconfig
+++ b/drivers/clk/meson/Kconfig
@@ -38,3 +38,12 @@ config COMMON_CLK_AXG
 	help
 	  Support for the clock controller on AmLogic A113D devices, aka axg.
 	  Say Y if you want peripherals and CPU frequency scaling to work.
+
+config COMMON_CLK_AXG_AUDIO
+	tristate "Meson AXG Audio Clock Controller Driver"
+	depends on COMMON_CLK_AXG
+	select COMMON_CLK_AMLOGIC_AUDIO
+	select MFD_SYSCON
+	help
+	  Support for the audio clock controller on AmLogic A113D devices,
+	  aka axg, Say Y if you want audio subsystem to work.
diff --git a/drivers/clk/meson/Makefile b/drivers/clk/meson/Makefile
index f51b4754c31b..1ab89b627586 100644
--- a/drivers/clk/meson/Makefile
+++ b/drivers/clk/meson/Makefile
@@ -8,4 +8,5 @@ obj-$(CONFIG_COMMON_CLK_AMLOGIC_AUDIO)	+= clk-triphase.o sclk-div.o
 obj-$(CONFIG_COMMON_CLK_MESON8B) += meson8b.o
 obj-$(CONFIG_COMMON_CLK_GXBB)	 += gxbb.o gxbb-aoclk.o gxbb-aoclk-32k.o
 obj-$(CONFIG_COMMON_CLK_AXG)	 += axg.o
+obj-$(CONFIG_COMMON_CLK_AXG_AUDIO)	+= axg-audio.o
 obj-$(CONFIG_COMMON_CLK_REGMAP_MESON)	+= clk-regmap.o
diff --git a/drivers/clk/meson/axg-audio.c b/drivers/clk/meson/axg-audio.c
new file mode 100644
index 000000000000..830c13ccd819
--- /dev/null
+++ b/drivers/clk/meson/axg-audio.c
@@ -0,0 +1,845 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2018 BayLibre, SAS.
+ * Author: Jerome Brunet <jbrunet at baylibre.com>
+ */
+
+#include <linux/clk.h>
+#include <linux/clk-provider.h>
+#include <linux/init.h>
+#include <linux/of_device.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/regmap.h>
+#include <linux/reset.h>
+#include <linux/slab.h>
+
+#include "clkc-audio.h"
+#include "axg-audio.h"
+
+#define AXG_MST_IN_COUNT	8
+#define AXG_SLV_SCLK_COUNT	10
+#define AXG_SLV_LRCLK_COUNT	10
+
+#define AXG_AUD_GATE(_name, _reg, _bit, _pname, _iflags)		\
+struct clk_regmap axg_##_name = {					\
+	.data = &(struct clk_regmap_gate_data){				\
+		.offset = (_reg),					\
+		.bit_idx = (_bit),					\
+	},								\
+	.hw.init = &(struct clk_init_data) {				\
+		.name = "axg_"#_name,					\
+		.ops = &clk_regmap_gate_ops,				\
+		.parent_names = (const char *[]){ _pname },		\
+		.num_parents = 1,					\
+		.flags = CLK_DUTY_CYCLE_PARENT | (_iflags),		\
+	},								\
+}
+
+#define AXG_AUD_MUX(_name, _reg, _mask, _shift, _dflags, _pnames, _iflags) \
+struct clk_regmap axg_##_name = {					\
+	.data = &(struct clk_regmap_mux_data){				\
+		.offset = (_reg),					\
+		.mask = (_mask),					\
+		.shift = (_shift),					\
+		.flags = (_dflags),					\
+	},								\
+	.hw.init = &(struct clk_init_data){				\
+		.name = "axg_"#_name,					\
+		.ops = &clk_regmap_mux_ops,				\
+		.parent_names = (_pnames),				\
+		.num_parents = ARRAY_SIZE(_pnames),			\
+		.flags = CLK_DUTY_CYCLE_PARENT | (_iflags),		\
+	},								\
+}
+
+#define AXG_AUD_DIV(_name, _reg, _shift, _width, _dflags, _pname, _iflags) \
+struct clk_regmap axg_##_name = {					\
+	.data = &(struct clk_regmap_div_data){				\
+		.offset = (_reg),					\
+		.shift = (_shift),					\
+		.width = (_width),					\
+		.flags = (_dflags),					\
+	},								\
+	.hw.init = &(struct clk_init_data){				\
+		.name = "axg_"#_name,					\
+		.ops = &clk_regmap_divider_ops,				\
+		.parent_names = (const char *[]) { _pname },		\
+		.num_parents = 1,					\
+		.flags = (_iflags),					\
+	},								\
+}
+
+#define AXG_PCLK_GATE(_name, _bit)				\
+	AXG_AUD_GATE(_name, AUDIO_CLK_GATE_EN, _bit, "axg_audio_pclk", 0)
+
+/* Audio peripheral clocks */
+static AXG_PCLK_GATE(ddr_arb,	   0);
+static AXG_PCLK_GATE(pdm,	   1);
+static AXG_PCLK_GATE(tdmin_a,	   2);
+static AXG_PCLK_GATE(tdmin_b,	   3);
+static AXG_PCLK_GATE(tdmin_c,	   4);
+static AXG_PCLK_GATE(tdmin_lb,	   5);
+static AXG_PCLK_GATE(tdmout_a,	   6);
+static AXG_PCLK_GATE(tdmout_b,	   7);
+static AXG_PCLK_GATE(tdmout_c,	   8);
+static AXG_PCLK_GATE(frddr_a,	   9);
+static AXG_PCLK_GATE(frddr_b,	   10);
+static AXG_PCLK_GATE(frddr_c,	   11);
+static AXG_PCLK_GATE(toddr_a,	   12);
+static AXG_PCLK_GATE(toddr_b,	   13);
+static AXG_PCLK_GATE(toddr_c,	   14);
+static AXG_PCLK_GATE(loopback,	   15);
+static AXG_PCLK_GATE(spdifin,	   16);
+static AXG_PCLK_GATE(spdifout,	   17);
+static AXG_PCLK_GATE(resample,	   18);
+static AXG_PCLK_GATE(power_detect, 19);
+
+/* Audio Master Clocks */
+static const char * const mst_mux_parent_names[] = {
+	"axg_mst_in0", "axg_mst_in1", "axg_mst_in2", "axg_mst_in3",
+	"axg_mst_in4", "axg_mst_in5", "axg_mst_in6", "axg_mst_in7",
+};
+
+#define AXG_MST_MCLK_MUX(_name, _reg)					\
+	AXG_AUD_MUX(_name##_sel, _reg, 0x7, 24, CLK_MUX_ROUND_CLOSEST, \
+		    mst_mux_parent_names, CLK_SET_RATE_PARENT)
+
+static AXG_MST_MCLK_MUX(mst_a_mclk,   AUDIO_MCLK_A_CTRL);
+static AXG_MST_MCLK_MUX(mst_b_mclk,   AUDIO_MCLK_B_CTRL);
+static AXG_MST_MCLK_MUX(mst_c_mclk,   AUDIO_MCLK_C_CTRL);
+static AXG_MST_MCLK_MUX(mst_d_mclk,   AUDIO_MCLK_D_CTRL);
+static AXG_MST_MCLK_MUX(mst_e_mclk,   AUDIO_MCLK_E_CTRL);
+static AXG_MST_MCLK_MUX(mst_f_mclk,   AUDIO_MCLK_F_CTRL);
+static AXG_MST_MCLK_MUX(spdifout_clk, AUDIO_CLK_SPDIFOUT_CTRL);
+static AXG_MST_MCLK_MUX(spdifin_clk,  AUDIO_CLK_SPDIFIN_CTRL);
+static AXG_MST_MCLK_MUX(pdm_dclk,     AUDIO_CLK_PDMIN_CTRL0);
+static AXG_MST_MCLK_MUX(pdm_sysclk,   AUDIO_CLK_PDMIN_CTRL1);
+
+#define AXG_MST_MCLK_DIV(_name, _reg)					\
+	AXG_AUD_DIV(_name##_div, _reg, 0, 16, CLK_DIVIDER_ROUND_CLOSEST, \
+		    "axg_"#_name"_sel", CLK_SET_RATE_PARENT)		\
+
+static AXG_MST_MCLK_DIV(mst_a_mclk,   AUDIO_MCLK_A_CTRL);
+static AXG_MST_MCLK_DIV(mst_b_mclk,   AUDIO_MCLK_B_CTRL);
+static AXG_MST_MCLK_DIV(mst_c_mclk,   AUDIO_MCLK_C_CTRL);
+static AXG_MST_MCLK_DIV(mst_d_mclk,   AUDIO_MCLK_D_CTRL);
+static AXG_MST_MCLK_DIV(mst_e_mclk,   AUDIO_MCLK_E_CTRL);
+static AXG_MST_MCLK_DIV(mst_f_mclk,   AUDIO_MCLK_F_CTRL);
+static AXG_MST_MCLK_DIV(spdifout_clk, AUDIO_CLK_SPDIFOUT_CTRL);
+static AXG_MST_MCLK_DIV(spdifin_clk,  AUDIO_CLK_SPDIFIN_CTRL);
+static AXG_MST_MCLK_DIV(pdm_dclk,     AUDIO_CLK_PDMIN_CTRL0);
+static AXG_MST_MCLK_DIV(pdm_sysclk,   AUDIO_CLK_PDMIN_CTRL1);
+
+#define AXG_MST_MCLK_GATE(_name, _reg)					\
+	AXG_AUD_GATE(_name, _reg, 31,  "axg_"#_name"_div",		\
+		     CLK_SET_RATE_PARENT)
+
+static AXG_MST_MCLK_GATE(mst_a_mclk,   AUDIO_MCLK_A_CTRL);
+static AXG_MST_MCLK_GATE(mst_b_mclk,   AUDIO_MCLK_B_CTRL);
+static AXG_MST_MCLK_GATE(mst_c_mclk,   AUDIO_MCLK_C_CTRL);
+static AXG_MST_MCLK_GATE(mst_d_mclk,   AUDIO_MCLK_D_CTRL);
+static AXG_MST_MCLK_GATE(mst_e_mclk,   AUDIO_MCLK_E_CTRL);
+static AXG_MST_MCLK_GATE(mst_f_mclk,   AUDIO_MCLK_F_CTRL);
+static AXG_MST_MCLK_GATE(spdifout_clk, AUDIO_CLK_SPDIFOUT_CTRL);
+static AXG_MST_MCLK_GATE(spdifin_clk,  AUDIO_CLK_SPDIFIN_CTRL);
+static AXG_MST_MCLK_GATE(pdm_dclk,     AUDIO_CLK_PDMIN_CTRL0);
+static AXG_MST_MCLK_GATE(pdm_sysclk,   AUDIO_CLK_PDMIN_CTRL1);
+
+/* Sample Clocks */
+#define AXG_MST_SCLK_PRE_EN(_name, _reg)			\
+	AXG_AUD_GATE(mst_##_name##_sclk_pre_en, _reg, 31,	\
+		     "axg_mst_"#_name"_mclk", 0)
+
+static AXG_MST_SCLK_PRE_EN(a, AUDIO_MST_A_SCLK_CTRL0);
+static AXG_MST_SCLK_PRE_EN(b, AUDIO_MST_B_SCLK_CTRL0);
+static AXG_MST_SCLK_PRE_EN(c, AUDIO_MST_C_SCLK_CTRL0);
+static AXG_MST_SCLK_PRE_EN(d, AUDIO_MST_D_SCLK_CTRL0);
+static AXG_MST_SCLK_PRE_EN(e, AUDIO_MST_E_SCLK_CTRL0);
+static AXG_MST_SCLK_PRE_EN(f, AUDIO_MST_F_SCLK_CTRL0);
+
+#define AXG_AUD_SCLK_DIV(_name, _reg, _div_shift, _div_width,		\
+			 _hi_shift, _hi_width, _pname, _iflags)		\
+struct clk_regmap axg_##_name = {					\
+	.data = &(struct meson_sclk_div_data) {				\
+		.div = {						\
+			.reg_off = (_reg),				\
+			.shift   = (_div_shift),			\
+			.width   = (_div_width),			\
+		},							\
+		.hi = {							\
+			.reg_off = (_reg),				\
+			.shift   = (_hi_shift),				\
+			.width   = (_hi_width),				\
+		},							\
+	},								\
+	.hw.init = &(struct clk_init_data) {				\
+		.name = "axg_"#_name,					\
+		.ops = &meson_sclk_div_ops,				\
+		.parent_names = (const char *[]) { _pname },		\
+		.num_parents = 1,					\
+		.flags = (_iflags),					\
+	},								\
+}
+
+#define AXG_MST_SCLK_DIV(_name, _reg)					\
+	AXG_AUD_SCLK_DIV(mst_##_name##_sclk_div, _reg, 20, 10, 0, 0,	\
+			 "axg_mst_"#_name"_sclk_pre_en",		\
+			 CLK_SET_RATE_PARENT)
+
+static AXG_MST_SCLK_DIV(a, AUDIO_MST_A_SCLK_CTRL0);
+static AXG_MST_SCLK_DIV(b, AUDIO_MST_B_SCLK_CTRL0);
+static AXG_MST_SCLK_DIV(c, AUDIO_MST_C_SCLK_CTRL0);
+static AXG_MST_SCLK_DIV(d, AUDIO_MST_D_SCLK_CTRL0);
+static AXG_MST_SCLK_DIV(e, AUDIO_MST_E_SCLK_CTRL0);
+static AXG_MST_SCLK_DIV(f, AUDIO_MST_F_SCLK_CTRL0);
+
+#define AXG_MST_SCLK_POST_EN(_name, _reg)				\
+	AXG_AUD_GATE(mst_##_name##_sclk_post_en, _reg, 30,		\
+		     "axg_mst_"#_name"_sclk_div", CLK_SET_RATE_PARENT)
+
+static AXG_MST_SCLK_POST_EN(a, AUDIO_MST_A_SCLK_CTRL0);
+static AXG_MST_SCLK_POST_EN(b, AUDIO_MST_B_SCLK_CTRL0);
+static AXG_MST_SCLK_POST_EN(c, AUDIO_MST_C_SCLK_CTRL0);
+static AXG_MST_SCLK_POST_EN(d, AUDIO_MST_D_SCLK_CTRL0);
+static AXG_MST_SCLK_POST_EN(e, AUDIO_MST_E_SCLK_CTRL0);
+static AXG_MST_SCLK_POST_EN(f, AUDIO_MST_F_SCLK_CTRL0);
+
+#define AXG_AUD_TRIPHASE(_name, _reg, _width, _shift0, _shift1, _shift2, \
+			 _pname, _iflags)				\
+struct clk_regmap axg_##_name = {					\
+	.data = &(struct meson_clk_triphase_data) {			\
+		.ph0 = {						\
+			.reg_off = (_reg),				\
+			.shift   = (_shift0),				\
+			.width   = (_width),				\
+		},							\
+		.ph1 = {						\
+			.reg_off = (_reg),				\
+			.shift   = (_shift1),				\
+			.width   = (_width),				\
+		},							\
+		.ph2 = {						\
+			.reg_off = (_reg),				\
+			.shift   = (_shift2),				\
+			.width   = (_width),				\
+		},							\
+	},								\
+	.hw.init = &(struct clk_init_data) {				\
+		.name = "axg_"#_name,					\
+		.ops = &meson_clk_triphase_ops,				\
+		.parent_names = (const char *[]) { _pname },		\
+		.num_parents = 1,					\
+		.flags = CLK_DUTY_CYCLE_PARENT | (_iflags),		\
+	},								\
+}
+
+#define AXG_MST_SCLK(_name, _reg)					\
+	AXG_AUD_TRIPHASE(mst_##_name##_sclk, _reg, 1, 0, 2, 4,		\
+			 "axg_mst_"#_name"_sclk_post_en", CLK_SET_RATE_PARENT)
+
+static AXG_MST_SCLK(a, AUDIO_MST_A_SCLK_CTRL1);
+static AXG_MST_SCLK(b, AUDIO_MST_B_SCLK_CTRL1);
+static AXG_MST_SCLK(c, AUDIO_MST_C_SCLK_CTRL1);
+static AXG_MST_SCLK(d, AUDIO_MST_D_SCLK_CTRL1);
+static AXG_MST_SCLK(e, AUDIO_MST_E_SCLK_CTRL1);
+static AXG_MST_SCLK(f, AUDIO_MST_F_SCLK_CTRL1);
+
+#define AXG_MST_LRCLK_DIV(_name, _reg)					\
+	AXG_AUD_SCLK_DIV(mst_##_name##_lrclk_div, _reg, 0, 10, 10, 10,	\
+		    "axg_mst_"#_name"_sclk_post_en", 0)			\
+
+static AXG_MST_LRCLK_DIV(a, AUDIO_MST_A_SCLK_CTRL0);
+static AXG_MST_LRCLK_DIV(b, AUDIO_MST_B_SCLK_CTRL0);
+static AXG_MST_LRCLK_DIV(c, AUDIO_MST_C_SCLK_CTRL0);
+static AXG_MST_LRCLK_DIV(d, AUDIO_MST_D_SCLK_CTRL0);
+static AXG_MST_LRCLK_DIV(e, AUDIO_MST_E_SCLK_CTRL0);
+static AXG_MST_LRCLK_DIV(f, AUDIO_MST_F_SCLK_CTRL0);
+
+#define AXG_MST_LRCLK(_name, _reg)					\
+	AXG_AUD_TRIPHASE(mst_##_name##_lrclk, _reg, 1, 1, 3, 5,		\
+			 "axg_mst_"#_name"_lrclk_div", CLK_SET_RATE_PARENT)
+
+static AXG_MST_LRCLK(a, AUDIO_MST_A_SCLK_CTRL1);
+static AXG_MST_LRCLK(b, AUDIO_MST_B_SCLK_CTRL1);
+static AXG_MST_LRCLK(c, AUDIO_MST_C_SCLK_CTRL1);
+static AXG_MST_LRCLK(d, AUDIO_MST_D_SCLK_CTRL1);
+static AXG_MST_LRCLK(e, AUDIO_MST_E_SCLK_CTRL1);
+static AXG_MST_LRCLK(f, AUDIO_MST_F_SCLK_CTRL1);
+
+static const char * const tdm_sclk_parent_names[] = {
+	"axg_mst_a_sclk", "axg_mst_b_sclk", "axg_mst_c_sclk",
+	"axg_mst_d_sclk", "axg_mst_e_sclk", "axg_mst_f_sclk",
+	"axg_slv_sclk0", "axg_slv_sclk1", "axg_slv_sclk2",
+	"axg_slv_sclk3", "axg_slv_sclk4", "axg_slv_sclk5",
+	"axg_slv_sclk6", "axg_slv_sclk7", "axg_slv_sclk8",
+	"axg_slv_sclk9"
+};
+
+#define AXG_TDM_SCLK_MUX(_name, _reg)				\
+	AXG_AUD_MUX(tdm##_name##_sclk_sel, _reg, 0xf, 24,	\
+		    CLK_MUX_ROUND_CLOSEST,			\
+		    tdm_sclk_parent_names, 0)
+
+static AXG_TDM_SCLK_MUX(in_a,  AUDIO_CLK_TDMIN_A_CTRL);
+static AXG_TDM_SCLK_MUX(in_b,  AUDIO_CLK_TDMIN_B_CTRL);
+static AXG_TDM_SCLK_MUX(in_c,  AUDIO_CLK_TDMIN_C_CTRL);
+static AXG_TDM_SCLK_MUX(in_lb, AUDIO_CLK_TDMIN_LB_CTRL);
+static AXG_TDM_SCLK_MUX(out_a, AUDIO_CLK_TDMOUT_A_CTRL);
+static AXG_TDM_SCLK_MUX(out_b, AUDIO_CLK_TDMOUT_B_CTRL);
+static AXG_TDM_SCLK_MUX(out_c, AUDIO_CLK_TDMOUT_C_CTRL);
+
+#define AXG_TDM_SCLK_PRE_EN(_name, _reg)				\
+	AXG_AUD_GATE(tdm##_name##_sclk_pre_en, _reg, 31,		\
+		     "axg_tdm"#_name"_sclk_sel", CLK_SET_RATE_PARENT)
+
+static AXG_TDM_SCLK_PRE_EN(in_a,  AUDIO_CLK_TDMIN_A_CTRL);
+static AXG_TDM_SCLK_PRE_EN(in_b,  AUDIO_CLK_TDMIN_B_CTRL);
+static AXG_TDM_SCLK_PRE_EN(in_c,  AUDIO_CLK_TDMIN_C_CTRL);
+static AXG_TDM_SCLK_PRE_EN(in_lb, AUDIO_CLK_TDMIN_LB_CTRL);
+static AXG_TDM_SCLK_PRE_EN(out_a, AUDIO_CLK_TDMOUT_A_CTRL);
+static AXG_TDM_SCLK_PRE_EN(out_b, AUDIO_CLK_TDMOUT_B_CTRL);
+static AXG_TDM_SCLK_PRE_EN(out_c, AUDIO_CLK_TDMOUT_C_CTRL);
+
+#define AXG_TDM_SCLK_POST_EN(_name, _reg)				\
+	AXG_AUD_GATE(tdm##_name##_sclk_post_en, _reg, 30,		\
+		     "axg_tdm"#_name"_sclk_pre_en", CLK_SET_RATE_PARENT)
+
+static AXG_TDM_SCLK_POST_EN(in_a,  AUDIO_CLK_TDMIN_A_CTRL);
+static AXG_TDM_SCLK_POST_EN(in_b,  AUDIO_CLK_TDMIN_B_CTRL);
+static AXG_TDM_SCLK_POST_EN(in_c,  AUDIO_CLK_TDMIN_C_CTRL);
+static AXG_TDM_SCLK_POST_EN(in_lb, AUDIO_CLK_TDMIN_LB_CTRL);
+static AXG_TDM_SCLK_POST_EN(out_a, AUDIO_CLK_TDMOUT_A_CTRL);
+static AXG_TDM_SCLK_POST_EN(out_b, AUDIO_CLK_TDMOUT_B_CTRL);
+static AXG_TDM_SCLK_POST_EN(out_c, AUDIO_CLK_TDMOUT_C_CTRL);
+
+#define AXG_TDM_SCLK(_name, _reg)					\
+	struct clk_regmap axg_tdm##_name##_sclk = {			\
+	.data = &(struct meson_clk_phase_data) {			\
+		.ph = {							\
+			.reg_off = (_reg),				\
+			.shift   = 29,					\
+			.width   = 1,					\
+		},							\
+	},								\
+	.hw.init = &(struct clk_init_data) {				\
+		.name = "axg_tdm"#_name"_sclk",				\
+		.ops = &meson_clk_phase_ops,				\
+		.parent_names = (const char *[])			\
+		{ "axg_tdm"#_name"_sclk_post_en" },			\
+		.num_parents = 1,					\
+		.flags = CLK_DUTY_CYCLE_PARENT | CLK_SET_RATE_PARENT,	\
+	},								\
+}
+
+static AXG_TDM_SCLK(in_a,  AUDIO_CLK_TDMIN_A_CTRL);
+static AXG_TDM_SCLK(in_b,  AUDIO_CLK_TDMIN_B_CTRL);
+static AXG_TDM_SCLK(in_c,  AUDIO_CLK_TDMIN_C_CTRL);
+static AXG_TDM_SCLK(in_lb, AUDIO_CLK_TDMIN_LB_CTRL);
+static AXG_TDM_SCLK(out_a, AUDIO_CLK_TDMOUT_A_CTRL);
+static AXG_TDM_SCLK(out_b, AUDIO_CLK_TDMOUT_B_CTRL);
+static AXG_TDM_SCLK(out_c, AUDIO_CLK_TDMOUT_C_CTRL);
+
+static const char * const tdm_lrclk_parent_names[] = {
+	"axg_mst_a_lrclk", "axg_mst_b_lrclk", "axg_mst_c_lrclk",
+	"axg_mst_d_lrclk", "axg_mst_e_lrclk", "axg_mst_f_lrclk",
+	"axg_slv_lrclk0", "axg_slv_lrclk1", "axg_slv_lrclk2",
+	"axg_slv_lrclk3", "axg_slv_lrclk4", "axg_slv_lrclk5",
+	"axg_slv_lrclk6", "axg_slv_lrclk7", "axg_slv_lrclk8",
+	"axg_slv_lrclk9"
+};
+
+#define AXG_TDM_LRLCK(_name, _reg)		       \
+	AXG_AUD_MUX(tdm##_name##_lrclk, _reg, 0xf, 20, \
+		    CLK_MUX_ROUND_CLOSEST,	       \
+		    tdm_lrclk_parent_names, 0)
+
+static AXG_TDM_LRLCK(in_a,  AUDIO_CLK_TDMIN_A_CTRL);
+static AXG_TDM_LRLCK(in_b,  AUDIO_CLK_TDMIN_B_CTRL);
+static AXG_TDM_LRLCK(in_c,  AUDIO_CLK_TDMIN_C_CTRL);
+static AXG_TDM_LRLCK(in_lb, AUDIO_CLK_TDMIN_LB_CTRL);
+static AXG_TDM_LRLCK(out_a, AUDIO_CLK_TDMOUT_A_CTRL);
+static AXG_TDM_LRLCK(out_b, AUDIO_CLK_TDMOUT_B_CTRL);
+static AXG_TDM_LRLCK(out_c, AUDIO_CLK_TDMOUT_C_CTRL);
+
+/*
+ * Array of all clocks provided by this provider
+ * The input clocks of the controller will be populated at runtime
+ */
+static struct clk_hw_onecell_data axg_audio_hw_onecell_data = {
+	.hws = {
+		[AUD_CLKID_DDR_ARB]		= &axg_ddr_arb.hw,
+		[AUD_CLKID_PDM]			= &axg_pdm.hw,
+		[AUD_CLKID_TDMIN_A]		= &axg_tdmin_a.hw,
+		[AUD_CLKID_TDMIN_B]		= &axg_tdmin_b.hw,
+		[AUD_CLKID_TDMIN_C]		= &axg_tdmin_c.hw,
+		[AUD_CLKID_TDMIN_LB]		= &axg_tdmin_lb.hw,
+		[AUD_CLKID_TDMOUT_A]		= &axg_tdmout_a.hw,
+		[AUD_CLKID_TDMOUT_B]		= &axg_tdmout_b.hw,
+		[AUD_CLKID_TDMOUT_C]		= &axg_tdmout_c.hw,
+		[AUD_CLKID_FRDDR_A]		= &axg_frddr_a.hw,
+		[AUD_CLKID_FRDDR_B]		= &axg_frddr_b.hw,
+		[AUD_CLKID_FRDDR_C]		= &axg_frddr_c.hw,
+		[AUD_CLKID_TODDR_A]		= &axg_toddr_a.hw,
+		[AUD_CLKID_TODDR_B]		= &axg_toddr_b.hw,
+		[AUD_CLKID_TODDR_C]		= &axg_toddr_c.hw,
+		[AUD_CLKID_LOOPBACK]		= &axg_loopback.hw,
+		[AUD_CLKID_SPDIFIN]		= &axg_spdifin.hw,
+		[AUD_CLKID_SPDIFOUT]		= &axg_spdifout.hw,
+		[AUD_CLKID_RESAMPLE]		= &axg_resample.hw,
+		[AUD_CLKID_POWER_DETECT]	= &axg_power_detect.hw,
+		[AUD_CLKID_MST_A_MCLK_SEL]	= &axg_mst_a_mclk_sel.hw,
+		[AUD_CLKID_MST_B_MCLK_SEL]	= &axg_mst_b_mclk_sel.hw,
+		[AUD_CLKID_MST_C_MCLK_SEL]	= &axg_mst_c_mclk_sel.hw,
+		[AUD_CLKID_MST_D_MCLK_SEL]	= &axg_mst_d_mclk_sel.hw,
+		[AUD_CLKID_MST_E_MCLK_SEL]	= &axg_mst_e_mclk_sel.hw,
+		[AUD_CLKID_MST_F_MCLK_SEL]	= &axg_mst_f_mclk_sel.hw,
+		[AUD_CLKID_MST_A_MCLK_DIV]	= &axg_mst_a_mclk_div.hw,
+		[AUD_CLKID_MST_B_MCLK_DIV]	= &axg_mst_b_mclk_div.hw,
+		[AUD_CLKID_MST_C_MCLK_DIV]	= &axg_mst_c_mclk_div.hw,
+		[AUD_CLKID_MST_D_MCLK_DIV]	= &axg_mst_d_mclk_div.hw,
+		[AUD_CLKID_MST_E_MCLK_DIV]	= &axg_mst_e_mclk_div.hw,
+		[AUD_CLKID_MST_F_MCLK_DIV]	= &axg_mst_f_mclk_div.hw,
+		[AUD_CLKID_MST_A_MCLK]		= &axg_mst_a_mclk.hw,
+		[AUD_CLKID_MST_B_MCLK]		= &axg_mst_b_mclk.hw,
+		[AUD_CLKID_MST_C_MCLK]		= &axg_mst_c_mclk.hw,
+		[AUD_CLKID_MST_D_MCLK]		= &axg_mst_d_mclk.hw,
+		[AUD_CLKID_MST_E_MCLK]		= &axg_mst_e_mclk.hw,
+		[AUD_CLKID_MST_F_MCLK]		= &axg_mst_f_mclk.hw,
+		[AUD_CLKID_SPDIFOUT_CLK_SEL]	= &axg_spdifout_clk_sel.hw,
+		[AUD_CLKID_SPDIFOUT_CLK_DIV]	= &axg_spdifout_clk_div.hw,
+		[AUD_CLKID_SPDIFOUT_CLK]	= &axg_spdifout_clk.hw,
+		[AUD_CLKID_SPDIFIN_CLK_SEL]	= &axg_spdifin_clk_sel.hw,
+		[AUD_CLKID_SPDIFIN_CLK_DIV]	= &axg_spdifin_clk_div.hw,
+		[AUD_CLKID_SPDIFIN_CLK]		= &axg_spdifin_clk.hw,
+		[AUD_CLKID_PDM_DCLK_SEL]	= &axg_pdm_dclk_sel.hw,
+		[AUD_CLKID_PDM_DCLK_DIV]	= &axg_pdm_dclk_div.hw,
+		[AUD_CLKID_PDM_DCLK]		= &axg_pdm_dclk.hw,
+		[AUD_CLKID_PDM_SYSCLK_SEL]	= &axg_pdm_sysclk_sel.hw,
+		[AUD_CLKID_PDM_SYSCLK_DIV]	= &axg_pdm_sysclk_div.hw,
+		[AUD_CLKID_PDM_SYSCLK]		= &axg_pdm_sysclk.hw,
+		[AUD_CLKID_MST_A_SCLK_PRE_EN]	= &axg_mst_a_sclk_pre_en.hw,
+		[AUD_CLKID_MST_B_SCLK_PRE_EN]	= &axg_mst_b_sclk_pre_en.hw,
+		[AUD_CLKID_MST_C_SCLK_PRE_EN]	= &axg_mst_c_sclk_pre_en.hw,
+		[AUD_CLKID_MST_D_SCLK_PRE_EN]	= &axg_mst_d_sclk_pre_en.hw,
+		[AUD_CLKID_MST_E_SCLK_PRE_EN]	= &axg_mst_e_sclk_pre_en.hw,
+		[AUD_CLKID_MST_F_SCLK_PRE_EN]	= &axg_mst_f_sclk_pre_en.hw,
+		[AUD_CLKID_MST_A_SCLK_DIV]	= &axg_mst_a_sclk_div.hw,
+		[AUD_CLKID_MST_B_SCLK_DIV]	= &axg_mst_b_sclk_div.hw,
+		[AUD_CLKID_MST_C_SCLK_DIV]	= &axg_mst_c_sclk_div.hw,
+		[AUD_CLKID_MST_D_SCLK_DIV]	= &axg_mst_d_sclk_div.hw,
+		[AUD_CLKID_MST_E_SCLK_DIV]	= &axg_mst_e_sclk_div.hw,
+		[AUD_CLKID_MST_F_SCLK_DIV]	= &axg_mst_f_sclk_div.hw,
+		[AUD_CLKID_MST_A_SCLK_POST_EN]	= &axg_mst_a_sclk_post_en.hw,
+		[AUD_CLKID_MST_B_SCLK_POST_EN]	= &axg_mst_b_sclk_post_en.hw,
+		[AUD_CLKID_MST_C_SCLK_POST_EN]	= &axg_mst_c_sclk_post_en.hw,
+		[AUD_CLKID_MST_D_SCLK_POST_EN]	= &axg_mst_d_sclk_post_en.hw,
+		[AUD_CLKID_MST_E_SCLK_POST_EN]	= &axg_mst_e_sclk_post_en.hw,
+		[AUD_CLKID_MST_F_SCLK_POST_EN]	= &axg_mst_f_sclk_post_en.hw,
+		[AUD_CLKID_MST_A_SCLK]		= &axg_mst_a_sclk.hw,
+		[AUD_CLKID_MST_B_SCLK]		= &axg_mst_b_sclk.hw,
+		[AUD_CLKID_MST_C_SCLK]		= &axg_mst_c_sclk.hw,
+		[AUD_CLKID_MST_D_SCLK]		= &axg_mst_d_sclk.hw,
+		[AUD_CLKID_MST_E_SCLK]		= &axg_mst_e_sclk.hw,
+		[AUD_CLKID_MST_F_SCLK]		= &axg_mst_f_sclk.hw,
+		[AUD_CLKID_MST_A_LRCLK_DIV]	= &axg_mst_a_lrclk_div.hw,
+		[AUD_CLKID_MST_B_LRCLK_DIV]	= &axg_mst_b_lrclk_div.hw,
+		[AUD_CLKID_MST_C_LRCLK_DIV]	= &axg_mst_c_lrclk_div.hw,
+		[AUD_CLKID_MST_D_LRCLK_DIV]	= &axg_mst_d_lrclk_div.hw,
+		[AUD_CLKID_MST_E_LRCLK_DIV]	= &axg_mst_e_lrclk_div.hw,
+		[AUD_CLKID_MST_F_LRCLK_DIV]	= &axg_mst_f_lrclk_div.hw,
+		[AUD_CLKID_MST_A_LRCLK]		= &axg_mst_a_lrclk.hw,
+		[AUD_CLKID_MST_B_LRCLK]		= &axg_mst_b_lrclk.hw,
+		[AUD_CLKID_MST_C_LRCLK]		= &axg_mst_c_lrclk.hw,
+		[AUD_CLKID_MST_D_LRCLK]		= &axg_mst_d_lrclk.hw,
+		[AUD_CLKID_MST_E_LRCLK]		= &axg_mst_e_lrclk.hw,
+		[AUD_CLKID_MST_F_LRCLK]		= &axg_mst_f_lrclk.hw,
+		[AUD_CLKID_TDMIN_A_SCLK_SEL]	= &axg_tdmin_a_sclk_sel.hw,
+		[AUD_CLKID_TDMIN_B_SCLK_SEL]	= &axg_tdmin_b_sclk_sel.hw,
+		[AUD_CLKID_TDMIN_C_SCLK_SEL]	= &axg_tdmin_c_sclk_sel.hw,
+		[AUD_CLKID_TDMIN_LB_SCLK_SEL]	= &axg_tdmin_lb_sclk_sel.hw,
+		[AUD_CLKID_TDMOUT_A_SCLK_SEL]	= &axg_tdmout_a_sclk_sel.hw,
+		[AUD_CLKID_TDMOUT_B_SCLK_SEL]	= &axg_tdmout_b_sclk_sel.hw,
+		[AUD_CLKID_TDMOUT_C_SCLK_SEL]	= &axg_tdmout_c_sclk_sel.hw,
+		[AUD_CLKID_TDMIN_A_SCLK_PRE_EN]	= &axg_tdmin_a_sclk_pre_en.hw,
+		[AUD_CLKID_TDMIN_B_SCLK_PRE_EN]	= &axg_tdmin_b_sclk_pre_en.hw,
+		[AUD_CLKID_TDMIN_C_SCLK_PRE_EN]	= &axg_tdmin_c_sclk_pre_en.hw,
+		[AUD_CLKID_TDMIN_LB_SCLK_PRE_EN] = &axg_tdmin_lb_sclk_pre_en.hw,
+		[AUD_CLKID_TDMOUT_A_SCLK_PRE_EN] = &axg_tdmout_a_sclk_pre_en.hw,
+		[AUD_CLKID_TDMOUT_B_SCLK_PRE_EN] = &axg_tdmout_b_sclk_pre_en.hw,
+		[AUD_CLKID_TDMOUT_C_SCLK_PRE_EN] = &axg_tdmout_c_sclk_pre_en.hw,
+		[AUD_CLKID_TDMIN_A_SCLK_POST_EN] = &axg_tdmin_a_sclk_post_en.hw,
+		[AUD_CLKID_TDMIN_B_SCLK_POST_EN] = &axg_tdmin_b_sclk_post_en.hw,
+		[AUD_CLKID_TDMIN_C_SCLK_POST_EN] = &axg_tdmin_c_sclk_post_en.hw,
+		[AUD_CLKID_TDMIN_LB_SCLK_POST_EN] = &axg_tdmin_lb_sclk_post_en.hw,
+		[AUD_CLKID_TDMOUT_A_SCLK_POST_EN] = &axg_tdmout_a_sclk_post_en.hw,
+		[AUD_CLKID_TDMOUT_B_SCLK_POST_EN] = &axg_tdmout_b_sclk_post_en.hw,
+		[AUD_CLKID_TDMOUT_C_SCLK_POST_EN] = &axg_tdmout_c_sclk_post_en.hw,
+		[AUD_CLKID_TDMIN_A_SCLK]	= &axg_tdmin_a_sclk.hw,
+		[AUD_CLKID_TDMIN_B_SCLK]	= &axg_tdmin_b_sclk.hw,
+		[AUD_CLKID_TDMIN_C_SCLK]	= &axg_tdmin_c_sclk.hw,
+		[AUD_CLKID_TDMIN_LB_SCLK]	= &axg_tdmin_lb_sclk.hw,
+		[AUD_CLKID_TDMOUT_A_SCLK]	= &axg_tdmout_a_sclk.hw,
+		[AUD_CLKID_TDMOUT_B_SCLK]	= &axg_tdmout_b_sclk.hw,
+		[AUD_CLKID_TDMOUT_C_SCLK]	= &axg_tdmout_c_sclk.hw,
+		[AUD_CLKID_TDMIN_A_LRCLK]	= &axg_tdmin_a_lrclk.hw,
+		[AUD_CLKID_TDMIN_B_LRCLK]	= &axg_tdmin_b_lrclk.hw,
+		[AUD_CLKID_TDMIN_C_LRCLK]	= &axg_tdmin_c_lrclk.hw,
+		[AUD_CLKID_TDMIN_LB_LRCLK]	= &axg_tdmin_lb_lrclk.hw,
+		[AUD_CLKID_TDMOUT_A_LRCLK]	= &axg_tdmout_a_lrclk.hw,
+		[AUD_CLKID_TDMOUT_B_LRCLK]	= &axg_tdmout_b_lrclk.hw,
+		[AUD_CLKID_TDMOUT_C_LRCLK]	= &axg_tdmout_c_lrclk.hw,
+		[NR_CLKS] = NULL,
+	},
+	.num = NR_CLKS,
+};
+
+/* Convenience table to populate regmap in .probe() */
+static struct clk_regmap *const axg_audio_clk_regmaps[] = {
+	&axg_ddr_arb,
+	&axg_pdm,
+	&axg_tdmin_a,
+	&axg_tdmin_b,
+	&axg_tdmin_c,
+	&axg_tdmin_lb,
+	&axg_tdmout_a,
+	&axg_tdmout_b,
+	&axg_tdmout_c,
+	&axg_frddr_a,
+	&axg_frddr_b,
+	&axg_frddr_c,
+	&axg_toddr_a,
+	&axg_toddr_b,
+	&axg_toddr_c,
+	&axg_loopback,
+	&axg_spdifin,
+	&axg_spdifout,
+	&axg_resample,
+	&axg_power_detect,
+	&axg_mst_a_mclk_sel,
+	&axg_mst_b_mclk_sel,
+	&axg_mst_c_mclk_sel,
+	&axg_mst_d_mclk_sel,
+	&axg_mst_e_mclk_sel,
+	&axg_mst_f_mclk_sel,
+	&axg_mst_a_mclk_div,
+	&axg_mst_b_mclk_div,
+	&axg_mst_c_mclk_div,
+	&axg_mst_d_mclk_div,
+	&axg_mst_e_mclk_div,
+	&axg_mst_f_mclk_div,
+	&axg_mst_a_mclk,
+	&axg_mst_b_mclk,
+	&axg_mst_c_mclk,
+	&axg_mst_d_mclk,
+	&axg_mst_e_mclk,
+	&axg_mst_f_mclk,
+	&axg_spdifout_clk_sel,
+	&axg_spdifout_clk_div,
+	&axg_spdifout_clk,
+	&axg_spdifin_clk_sel,
+	&axg_spdifin_clk_div,
+	&axg_spdifin_clk,
+	&axg_pdm_dclk_sel,
+	&axg_pdm_dclk_div,
+	&axg_pdm_dclk,
+	&axg_pdm_sysclk_sel,
+	&axg_pdm_sysclk_div,
+	&axg_pdm_sysclk,
+	&axg_mst_a_sclk_pre_en,
+	&axg_mst_b_sclk_pre_en,
+	&axg_mst_c_sclk_pre_en,
+	&axg_mst_d_sclk_pre_en,
+	&axg_mst_e_sclk_pre_en,
+	&axg_mst_f_sclk_pre_en,
+	&axg_mst_a_sclk_div,
+	&axg_mst_b_sclk_div,
+	&axg_mst_c_sclk_div,
+	&axg_mst_d_sclk_div,
+	&axg_mst_e_sclk_div,
+	&axg_mst_f_sclk_div,
+	&axg_mst_a_sclk_post_en,
+	&axg_mst_b_sclk_post_en,
+	&axg_mst_c_sclk_post_en,
+	&axg_mst_d_sclk_post_en,
+	&axg_mst_e_sclk_post_en,
+	&axg_mst_f_sclk_post_en,
+	&axg_mst_a_sclk,
+	&axg_mst_b_sclk,
+	&axg_mst_c_sclk,
+	&axg_mst_d_sclk,
+	&axg_mst_e_sclk,
+	&axg_mst_f_sclk,
+	&axg_mst_a_lrclk_div,
+	&axg_mst_b_lrclk_div,
+	&axg_mst_c_lrclk_div,
+	&axg_mst_d_lrclk_div,
+	&axg_mst_e_lrclk_div,
+	&axg_mst_f_lrclk_div,
+	&axg_mst_a_lrclk,
+	&axg_mst_b_lrclk,
+	&axg_mst_c_lrclk,
+	&axg_mst_d_lrclk,
+	&axg_mst_e_lrclk,
+	&axg_mst_f_lrclk,
+	&axg_tdmin_a_sclk_sel,
+	&axg_tdmin_b_sclk_sel,
+	&axg_tdmin_c_sclk_sel,
+	&axg_tdmin_lb_sclk_sel,
+	&axg_tdmout_a_sclk_sel,
+	&axg_tdmout_b_sclk_sel,
+	&axg_tdmout_c_sclk_sel,
+	&axg_tdmin_a_sclk_pre_en,
+	&axg_tdmin_b_sclk_pre_en,
+	&axg_tdmin_c_sclk_pre_en,
+	&axg_tdmin_lb_sclk_pre_en,
+	&axg_tdmout_a_sclk_pre_en,
+	&axg_tdmout_b_sclk_pre_en,
+	&axg_tdmout_c_sclk_pre_en,
+	&axg_tdmin_a_sclk_post_en,
+	&axg_tdmin_b_sclk_post_en,
+	&axg_tdmin_c_sclk_post_en,
+	&axg_tdmin_lb_sclk_post_en,
+	&axg_tdmout_a_sclk_post_en,
+	&axg_tdmout_b_sclk_post_en,
+	&axg_tdmout_c_sclk_post_en,
+	&axg_tdmin_a_sclk,
+	&axg_tdmin_b_sclk,
+	&axg_tdmin_c_sclk,
+	&axg_tdmin_lb_sclk,
+	&axg_tdmout_a_sclk,
+	&axg_tdmout_b_sclk,
+	&axg_tdmout_c_sclk,
+	&axg_tdmin_a_lrclk,
+	&axg_tdmin_b_lrclk,
+	&axg_tdmin_c_lrclk,
+	&axg_tdmin_lb_lrclk,
+	&axg_tdmout_a_lrclk,
+	&axg_tdmout_b_lrclk,
+	&axg_tdmout_c_lrclk,
+};
+
+static struct clk *devm_clk_get_enable(struct device *dev, char *id)
+{
+	struct clk *clk;
+	int ret;
+
+	clk = devm_clk_get(dev, id);
+	if (IS_ERR(clk)) {
+		if (PTR_ERR(clk) != -EPROBE_DEFER)
+			dev_err(dev, "failed to get %s", id);
+		return clk;
+	}
+
+	ret = clk_prepare_enable(clk);
+	if (ret) {
+		dev_err(dev, "failed to enable %s", id);
+		return ERR_PTR(ret);
+	}
+
+	ret = devm_add_action_or_reset(dev,
+				       (void(*)(void *))clk_disable_unprepare,
+				       clk);
+	if (ret) {
+		dev_err(dev, "failed to add reset action on %s", id);
+		return ERR_PTR(ret);
+	}
+
+	return clk;
+}
+
+static const struct clk_ops axg_clk_no_ops = {};
+
+static struct clk_hw *axg_clk_hw_register_bypass(struct device *dev,
+						 const char *name,
+						 const char *parent_name)
+{
+	struct clk_hw *hw;
+	struct clk_init_data init;
+	char *clk_name;
+	int ret;
+
+	hw = devm_kzalloc(dev, sizeof(*hw), GFP_KERNEL);
+	if (!hw)
+		return ERR_PTR(-ENOMEM);
+
+	clk_name = kasprintf(GFP_KERNEL, "axg_%s", name);
+	if (!clk_name)
+		return ERR_PTR(-ENOMEM);
+
+	init.name = clk_name;
+	init.ops = &axg_clk_no_ops;
+	init.flags = 0;
+	init.parent_names = parent_name ? &parent_name : NULL;
+	init.num_parents = parent_name ? 1 : 0;
+	hw->init = &init;
+
+	ret = devm_clk_hw_register(dev, hw);
+	kfree(clk_name);
+
+	return ret ? ERR_PTR(ret) : hw;
+}
+
+static int axg_register_clk_hw_input(struct device *dev,
+				     const char *name,
+				     unsigned int clkid)
+{
+	struct clk *parent_clk = devm_clk_get(dev, name);
+	struct clk_hw *hw = NULL;
+
+	if (IS_ERR(parent_clk)) {
+		int err = PTR_ERR(parent_clk);
+
+		/* It is ok if an input clock is missing */
+		if (err == -ENOENT) {
+			dev_dbg(dev, "%s not provided", name);
+		} else {
+			if (err != -EPROBE_DEFER)
+				dev_err(dev, "failed to get %s clock", name);
+			return err;
+		}
+	} else {
+		hw = axg_clk_hw_register_bypass(dev, name,
+						__clk_get_name(parent_clk));
+	}
+
+	if (IS_ERR(hw)) {
+		dev_err(dev, "failed to register %s clock", name);
+		return PTR_ERR(hw);
+	}
+
+	axg_audio_hw_onecell_data.hws[clkid] = hw;
+	return 0;
+}
+
+static int axg_register_clk_hw_inputs(struct device *dev,
+				      const char *basename,
+				      unsigned int count,
+				      unsigned int clkid)
+{
+	char *name;
+	int i, ret;
+
+	for (i = 0; i < count; i++) {
+		name = kasprintf(GFP_KERNEL, "%s%d", basename, i);
+		if (!name)
+			return -ENOMEM;
+
+		ret = axg_register_clk_hw_input(dev, name, clkid + i);
+		kfree(name);
+		if (ret)
+			return ret;
+	}
+
+	return 0;
+}
+
+static const struct regmap_config axg_audio_regmap_cfg = {
+	.reg_bits	= 32,
+	.val_bits	= 32,
+	.reg_stride	= 4,
+	.max_register	= AUDIO_CLK_PDMIN_CTRL1,
+};
+
+static int axg_audio_clkc_probe(struct platform_device *pdev)
+{
+	struct device *dev = &pdev->dev;
+	struct regmap *map;
+	struct resource *res;
+	void __iomem *regs;
+	struct clk *clk;
+	struct clk_hw *hw;
+	int ret, i;
+
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	regs = devm_ioremap_resource(dev, res);
+	if (IS_ERR(regs))
+		return PTR_ERR(regs);
+
+	map = devm_regmap_init_mmio(dev, regs, &axg_audio_regmap_cfg);
+	if (IS_ERR(map)) {
+		dev_err(dev, "failed to init regmap: %ld\n", PTR_ERR(map));
+		return PTR_ERR(map);
+	}
+
+	/* Get the mandatory peripheral clock */
+	clk = devm_clk_get_enable(dev, "pclk");
+	if (IS_ERR(clk))
+		return PTR_ERR(clk);
+
+	ret = device_reset(dev);
+	if (ret) {
+		dev_err(dev, "failed to reset device\n");
+		return ret;
+	}
+
+	/* Register the peripheral input clock */
+	hw = axg_clk_hw_register_bypass(dev, "audio_pclk",
+					__clk_get_name(clk));
+	if (IS_ERR(hw))
+		return PTR_ERR(hw);
+
+	axg_audio_hw_onecell_data.hws[AUD_CLKID_PCLK] = hw;
+
+	/* Register optional input master clocks */
+	ret = axg_register_clk_hw_inputs(dev, "mst_in",
+					 AXG_MST_IN_COUNT,
+					 AUD_CLKID_MST0);
+	if (ret)
+		return ret;
+
+	/* Register optional input slave sclks */
+	ret = axg_register_clk_hw_inputs(dev, "slv_sclk",
+					 AXG_SLV_SCLK_COUNT,
+					 AUD_CLKID_SLV_SCLK0);
+	if (ret)
+		return ret;
+
+	/* Register optional input slave lrclks */
+	ret = axg_register_clk_hw_inputs(dev, "slv_lrclk",
+					 AXG_SLV_LRCLK_COUNT,
+					 AUD_CLKID_SLV_LRCLK0);
+	if (ret)
+		return ret;
+
+	/* Populate regmap for the regmap backed clocks */
+	for (i = 0; i < ARRAY_SIZE(axg_audio_clk_regmaps); i++)
+		axg_audio_clk_regmaps[i]->map = map;
+
+	/* Take care to skip the registered input clocks */
+	for (i = AUD_CLKID_DDR_ARB; i < axg_audio_hw_onecell_data.num; i++) {
+		hw = axg_audio_hw_onecell_data.hws[i];
+		/* array might be sparse */
+		if (!hw)
+			continue;
+
+		ret = devm_clk_hw_register(dev, hw);
+		if (ret) {
+			dev_err(dev, "failed to register clock %s\n",
+				hw->init->name);
+			return ret;
+		}
+	}
+
+	return devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get,
+					   &axg_audio_hw_onecell_data);
+}
+
+static const struct of_device_id clkc_match_table[] = {
+	{ .compatible = "amlogic,axg-audio-clkc" },
+	{}
+};
+MODULE_DEVICE_TABLE(of, clkc_match_table);
+
+static struct platform_driver axg_audio_driver = {
+	.probe		= axg_audio_clkc_probe,
+	.driver		= {
+		.name	= "axg-audio-clkc",
+		.of_match_table = clkc_match_table,
+	},
+};
+module_platform_driver(axg_audio_driver);
+
+MODULE_DESCRIPTION("Amlogic A113x Audio Clock driver");
+MODULE_AUTHOR("Jerome Brunet <jbrunet at baylibre.com>");
+MODULE_LICENSE("GPL v2");
diff --git a/drivers/clk/meson/axg-audio.h b/drivers/clk/meson/axg-audio.h
new file mode 100644
index 000000000000..e7a0efd12429
--- /dev/null
+++ b/drivers/clk/meson/axg-audio.h
@@ -0,0 +1,127 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2018 BayLibre, SAS.
+ * Author: Jerome Brunet <jbrunet at baylibre.com>
+ */
+
+#ifndef __AXG_AUDIO_CLKC_H
+#define __AXG_AUDIO_CLKC_H
+
+/*
+ * Audio Clock  register offsets
+ *
+ * Register offsets from the datasheet must be multiplied by 4 before
+ * to get the right offset
+ */
+#define AUDIO_CLK_GATE_EN	0x000
+#define AUDIO_MCLK_A_CTRL	0x004
+#define AUDIO_MCLK_B_CTRL	0x008
+#define AUDIO_MCLK_C_CTRL	0x00C
+#define AUDIO_MCLK_D_CTRL	0x010
+#define AUDIO_MCLK_E_CTRL	0x014
+#define AUDIO_MCLK_F_CTRL	0x018
+#define AUDIO_MST_A_SCLK_CTRL0	0x040
+#define AUDIO_MST_A_SCLK_CTRL1	0x044
+#define AUDIO_MST_B_SCLK_CTRL0	0x048
+#define AUDIO_MST_B_SCLK_CTRL1	0x04C
+#define AUDIO_MST_C_SCLK_CTRL0	0x050
+#define AUDIO_MST_C_SCLK_CTRL1	0x054
+#define AUDIO_MST_D_SCLK_CTRL0	0x058
+#define AUDIO_MST_D_SCLK_CTRL1	0x05C
+#define AUDIO_MST_E_SCLK_CTRL0	0x060
+#define AUDIO_MST_E_SCLK_CTRL1	0x064
+#define AUDIO_MST_F_SCLK_CTRL0	0x068
+#define AUDIO_MST_F_SCLK_CTRL1	0x06C
+#define AUDIO_CLK_TDMIN_A_CTRL	0x080
+#define AUDIO_CLK_TDMIN_B_CTRL	0x084
+#define AUDIO_CLK_TDMIN_C_CTRL	0x088
+#define AUDIO_CLK_TDMIN_LB_CTRL 0x08C
+#define AUDIO_CLK_TDMOUT_A_CTRL 0x090
+#define AUDIO_CLK_TDMOUT_B_CTRL 0x094
+#define AUDIO_CLK_TDMOUT_C_CTRL 0x098
+#define AUDIO_CLK_SPDIFIN_CTRL	0x09C
+#define AUDIO_CLK_SPDIFOUT_CTRL 0x0A0
+#define AUDIO_CLK_RESAMPLE_CTRL 0x0A4
+#define AUDIO_CLK_LOCKER_CTRL	0x0A8
+#define AUDIO_CLK_PDMIN_CTRL0	0x0AC
+#define AUDIO_CLK_PDMIN_CTRL1	0x0B0
+
+/*
+ * CLKID index values
+ * These indices are entirely contrived and do not map onto the hardware.
+ */
+
+#define AUD_CLKID_PCLK			0
+#define AUD_CLKID_MST0			1
+#define AUD_CLKID_MST1			2
+#define AUD_CLKID_MST2			3
+#define AUD_CLKID_MST3			4
+#define AUD_CLKID_MST4			5
+#define AUD_CLKID_MST5			6
+#define AUD_CLKID_MST6			7
+#define AUD_CLKID_MST7			8
+#define AUD_CLKID_MST_A_MCLK_SEL	59
+#define AUD_CLKID_MST_B_MCLK_SEL	60
+#define AUD_CLKID_MST_C_MCLK_SEL	61
+#define AUD_CLKID_MST_D_MCLK_SEL	62
+#define AUD_CLKID_MST_E_MCLK_SEL	63
+#define AUD_CLKID_MST_F_MCLK_SEL	64
+#define AUD_CLKID_MST_A_MCLK_DIV	65
+#define AUD_CLKID_MST_B_MCLK_DIV	66
+#define AUD_CLKID_MST_C_MCLK_DIV	67
+#define AUD_CLKID_MST_D_MCLK_DIV	68
+#define AUD_CLKID_MST_E_MCLK_DIV	69
+#define AUD_CLKID_MST_F_MCLK_DIV	70
+#define AUD_CLKID_SPDIFOUT_CLK_SEL	71
+#define AUD_CLKID_SPDIFOUT_CLK_DIV	72
+#define AUD_CLKID_SPDIFIN_CLK_SEL	73
+#define AUD_CLKID_SPDIFIN_CLK_DIV	74
+#define AUD_CLKID_PDM_DCLK_SEL		75
+#define AUD_CLKID_PDM_DCLK_DIV		76
+#define AUD_CLKID_PDM_SYSCLK_SEL	77
+#define AUD_CLKID_PDM_SYSCLK_DIV	78
+#define AUD_CLKID_MST_A_SCLK_PRE_EN	92
+#define AUD_CLKID_MST_B_SCLK_PRE_EN	93
+#define AUD_CLKID_MST_C_SCLK_PRE_EN	94
+#define AUD_CLKID_MST_D_SCLK_PRE_EN	95
+#define AUD_CLKID_MST_E_SCLK_PRE_EN	96
+#define AUD_CLKID_MST_F_SCLK_PRE_EN	97
+#define AUD_CLKID_MST_A_SCLK_DIV	98
+#define AUD_CLKID_MST_B_SCLK_DIV	99
+#define AUD_CLKID_MST_C_SCLK_DIV	100
+#define AUD_CLKID_MST_D_SCLK_DIV	101
+#define AUD_CLKID_MST_E_SCLK_DIV	102
+#define AUD_CLKID_MST_F_SCLK_DIV	103
+#define AUD_CLKID_MST_A_SCLK_POST_EN	104
+#define AUD_CLKID_MST_B_SCLK_POST_EN	105
+#define AUD_CLKID_MST_C_SCLK_POST_EN	106
+#define AUD_CLKID_MST_D_SCLK_POST_EN	107
+#define AUD_CLKID_MST_E_SCLK_POST_EN	108
+#define AUD_CLKID_MST_F_SCLK_POST_EN	109
+#define AUD_CLKID_MST_A_LRCLK_DIV	110
+#define AUD_CLKID_MST_B_LRCLK_DIV	111
+#define AUD_CLKID_MST_C_LRCLK_DIV	112
+#define AUD_CLKID_MST_D_LRCLK_DIV	113
+#define AUD_CLKID_MST_E_LRCLK_DIV	114
+#define AUD_CLKID_MST_F_LRCLK_DIV	115
+#define AUD_CLKID_TDMIN_A_SCLK_PRE_EN	137
+#define AUD_CLKID_TDMIN_B_SCLK_PRE_EN	138
+#define AUD_CLKID_TDMIN_C_SCLK_PRE_EN	139
+#define AUD_CLKID_TDMIN_LB_SCLK_PRE_EN	140
+#define AUD_CLKID_TDMOUT_A_SCLK_PRE_EN	141
+#define AUD_CLKID_TDMOUT_B_SCLK_PRE_EN	142
+#define AUD_CLKID_TDMOUT_C_SCLK_PRE_EN	143
+#define AUD_CLKID_TDMIN_A_SCLK_POST_EN	144
+#define AUD_CLKID_TDMIN_B_SCLK_POST_EN	145
+#define AUD_CLKID_TDMIN_C_SCLK_POST_EN	146
+#define AUD_CLKID_TDMIN_LB_SCLK_POST_EN	147
+#define AUD_CLKID_TDMOUT_A_SCLK_POST_EN	148
+#define AUD_CLKID_TDMOUT_B_SCLK_POST_EN	149
+#define AUD_CLKID_TDMOUT_C_SCLK_POST_EN	150
+
+/* include the CLKIDs which are part of the DT bindings */
+#include <dt-bindings/clock/axg-audio-clkc.h>
+
+#define NR_CLKS	151
+
+#endif /*__AXG_AUDIO_CLKC_H */
-- 
2.14.3



From yixun.lan at amlogic.com  Thu Apr 26 09:05:06 2018
From: yixun.lan at amlogic.com (Yixun Lan)
Date: Thu, 26 Apr 2018 16:05:06 +0000
Subject: [PATCH 0/2] net: stmmac: dwmac-meson: 100M phy mode support for AXG
 SoC
Message-ID: <20180426160508.29380-1-yixun.lan@amlogic.com>

Due to the dwmac glue layer register changed, we need to 
introduce a new compatible name for the Meson-AXG SoC
to support for the RMII 100M ethernet PHY.

Yixun Lan (2):
  dt-bindings: net: meson-dwmac: new compatible name for AXG SoC
  net: stmmac: dwmac-meson: extend phy mode setting

 .../devicetree/bindings/net/meson-dwmac.txt   |  1 +
 .../ethernet/stmicro/stmmac/dwmac-meson8b.c   | 96 ++++++++++++++++---
 2 files changed, 86 insertions(+), 11 deletions(-)

-- 
2.17.0



From yixun.lan at amlogic.com  Thu Apr 26 09:05:07 2018
From: yixun.lan at amlogic.com (Yixun Lan)
Date: Thu, 26 Apr 2018 16:05:07 +0000
Subject: [PATCH 1/2] dt-bindings: net: meson-dwmac: new compatible name for
 AXG SoC
In-Reply-To: <20180426160508.29380-1-yixun.lan@amlogic.com>
References: <20180426160508.29380-1-yixun.lan@amlogic.com>
Message-ID: <20180426160508.29380-2-yixun.lan@amlogic.com>

We need to introduce a new compatible name for the Meson-AXG SoC
in order to support the RMII 100M ethernet PHY, since the PRG_ETH0
register of the dwmac glue layer is changed from previous old SoC.

Signed-off-by: Yixun Lan <yixun.lan at amlogic.com>
---
 Documentation/devicetree/bindings/net/meson-dwmac.txt | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/net/meson-dwmac.txt b/Documentation/devicetree/bindings/net/meson-dwmac.txt
index 61cada22ae6c..1321bb194ed9 100644
--- a/Documentation/devicetree/bindings/net/meson-dwmac.txt
+++ b/Documentation/devicetree/bindings/net/meson-dwmac.txt
@@ -11,6 +11,7 @@ Required properties on all platforms:
 			- "amlogic,meson8b-dwmac"
 			- "amlogic,meson8m2-dwmac"
 			- "amlogic,meson-gxbb-dwmac"
+			- "amlogic,meson-axg-dwmac"
 		Additionally "snps,dwmac" and any applicable more
 		detailed version number described in net/stmmac.txt
 		should be used.
-- 
2.17.0



From yixun.lan at amlogic.com  Thu Apr 26 09:05:08 2018
From: yixun.lan at amlogic.com (Yixun Lan)
Date: Thu, 26 Apr 2018 16:05:08 +0000
Subject: [PATCH 2/2] net: stmmac: dwmac-meson: extend phy mode setting
In-Reply-To: <20180426160508.29380-1-yixun.lan@amlogic.com>
References: <20180426160508.29380-1-yixun.lan@amlogic.com>
Message-ID: <20180426160508.29380-3-yixun.lan@amlogic.com>

  In the Meson-AXG SoC, the phy mode setting of PRG_ETH0 in the glue layer
is extended from bit[0] to bit[2:0].
  There is no problem if we configure it to the RGMII 1000M PHY mode,
since the register setting is coincidentally compatible with previous one,
but for the RMII 100M PHY mode, the configuration need to be changed to
value - b100.
  This patch was verified with a RTL8201F 100M ethernet PHY.

Signed-off-by: Yixun Lan <yixun.lan at amlogic.com>
---
 .../ethernet/stmicro/stmmac/dwmac-meson8b.c   | 95 ++++++++++++++++---
 1 file changed, 84 insertions(+), 11 deletions(-)

diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c
index 7cb794094a70..e3688b6dd87c 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c
@@ -18,6 +18,7 @@
 #include <linux/io.h>
 #include <linux/ioport.h>
 #include <linux/module.h>
+#include <linux/of_device.h>
 #include <linux/of_net.h>
 #include <linux/mfd/syscon.h>
 #include <linux/platform_device.h>
@@ -29,6 +30,10 @@
 
 #define PRG_ETH0_RGMII_MODE		BIT(0)
 
+#define PRG_ETH0_EXT_PHY_MODE_MASK	GENMASK(2, 0)
+#define PRG_ETH0_EXT_RGMII_MODE		1
+#define PRG_ETH0_EXT_RMII_MODE		4
+
 /* mux to choose between fclk_div2 (bit unset) and mpll2 (bit set) */
 #define PRG_ETH0_CLK_M250_SEL_SHIFT	4
 #define PRG_ETH0_CLK_M250_SEL_MASK	GENMASK(4, 4)
@@ -46,10 +51,16 @@
 #define PRG_ETH0_TX_AND_PHY_REF_CLK	BIT(12)
 
 #define MUX_CLK_NUM_PARENTS		2
+struct meson8b_dwmac_data {
+	bool ext_phy_mode;
+};
 
 struct meson8b_dwmac {
 	struct device		*dev;
 	void __iomem		*regs;
+
+	const struct meson8b_dwmac_data *data;
+
 	phy_interface_t		phy_mode;
 	struct clk		*rgmii_tx_clk;
 	u32			tx_delay_ns;
@@ -171,6 +182,46 @@ static int meson8b_init_rgmii_tx_clk(struct meson8b_dwmac *dwmac)
 	return 0;
 }
 
+static int meson8b_init_set_mode(struct meson8b_dwmac *dwmac)
+{
+	bool ext_phy_mode = dwmac->data->ext_phy_mode;
+
+	switch (dwmac->phy_mode) {
+	case PHY_INTERFACE_MODE_RGMII:
+	case PHY_INTERFACE_MODE_RGMII_RXID:
+	case PHY_INTERFACE_MODE_RGMII_ID:
+	case PHY_INTERFACE_MODE_RGMII_TXID:
+		/* enable RGMII mode */
+		if (ext_phy_mode)
+			meson8b_dwmac_mask_bits(dwmac, PRG_ETH0,
+						PRG_ETH0_EXT_PHY_MODE_MASK,
+						PRG_ETH0_EXT_RGMII_MODE);
+		else
+			meson8b_dwmac_mask_bits(dwmac, PRG_ETH0,
+						PRG_ETH0_RGMII_MODE,
+						PRG_ETH0_RGMII_MODE);
+
+		break;
+	case PHY_INTERFACE_MODE_RMII:
+		/* disable RGMII mode -> enables RMII mode */
+		if (ext_phy_mode)
+			meson8b_dwmac_mask_bits(dwmac, PRG_ETH0,
+						PRG_ETH0_EXT_PHY_MODE_MASK,
+						PRG_ETH0_EXT_RMII_MODE);
+		else
+			meson8b_dwmac_mask_bits(dwmac, PRG_ETH0,
+						PRG_ETH0_RGMII_MODE, 0);
+
+		break;
+	default:
+		dev_err(dwmac->dev, "fail to set phy-mode %s\n",
+			phy_modes(dwmac->phy_mode));
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
 static int meson8b_init_prg_eth(struct meson8b_dwmac *dwmac)
 {
 	int ret;
@@ -188,10 +239,6 @@ static int meson8b_init_prg_eth(struct meson8b_dwmac *dwmac)
 
 	case PHY_INTERFACE_MODE_RGMII_ID:
 	case PHY_INTERFACE_MODE_RGMII_TXID:
-		/* enable RGMII mode */
-		meson8b_dwmac_mask_bits(dwmac, PRG_ETH0, PRG_ETH0_RGMII_MODE,
-					PRG_ETH0_RGMII_MODE);
-
 		/* only relevant for RMII mode -> disable in RGMII mode */
 		meson8b_dwmac_mask_bits(dwmac, PRG_ETH0,
 					PRG_ETH0_INVERTED_RMII_CLK, 0);
@@ -224,10 +271,6 @@ static int meson8b_init_prg_eth(struct meson8b_dwmac *dwmac)
 		break;
 
 	case PHY_INTERFACE_MODE_RMII:
-		/* disable RGMII mode -> enables RMII mode */
-		meson8b_dwmac_mask_bits(dwmac, PRG_ETH0, PRG_ETH0_RGMII_MODE,
-					0);
-
 		/* invert internal clk_rmii_i to generate 25/2.5 tx_rx_clk */
 		meson8b_dwmac_mask_bits(dwmac, PRG_ETH0,
 					PRG_ETH0_INVERTED_RMII_CLK,
@@ -274,6 +317,11 @@ static int meson8b_dwmac_probe(struct platform_device *pdev)
 		goto err_remove_config_dt;
 	}
 
+	dwmac->data = (const struct meson8b_dwmac_data *)
+		of_device_get_match_data(&pdev->dev);
+	if (!dwmac->data)
+		return -EINVAL;
+
 	res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
 	dwmac->regs = devm_ioremap_resource(&pdev->dev, res);
 	if (IS_ERR(dwmac->regs)) {
@@ -298,6 +346,10 @@ static int meson8b_dwmac_probe(struct platform_device *pdev)
 	if (ret)
 		goto err_remove_config_dt;
 
+	ret = meson8b_init_set_mode(dwmac);
+	if (ret)
+		goto err_remove_config_dt;
+
 	ret = meson8b_init_prg_eth(dwmac);
 	if (ret)
 		goto err_remove_config_dt;
@@ -316,10 +368,31 @@ static int meson8b_dwmac_probe(struct platform_device *pdev)
 	return ret;
 }
 
+static const struct meson8b_dwmac_data meson8b_dwmac_data = {
+	.ext_phy_mode = false,
+};
+
+static const struct meson8b_dwmac_data meson_axg_dwmac_data = {
+	.ext_phy_mode = true,
+};
+
 static const struct of_device_id meson8b_dwmac_match[] = {
-	{ .compatible = "amlogic,meson8b-dwmac" },
-	{ .compatible = "amlogic,meson8m2-dwmac" },
-	{ .compatible = "amlogic,meson-gxbb-dwmac" },
+	{
+		.compatible = "amlogic,meson8b-dwmac",
+		.data = &meson8b_dwmac_data,
+	},
+	{
+		.compatible = "amlogic,meson8m2-dwmac",
+		.data = &meson8b_dwmac_data,
+	},
+	{
+		.compatible = "amlogic,meson-gxbb-dwmac",
+		.data = &meson8b_dwmac_data,
+	},
+	{
+		.compatible = "amlogic,meson-axg-dwmac",
+		.data = &meson_axg_dwmac_data,
+	},
 	{ }
 };
 MODULE_DEVICE_TABLE(of, meson8b_dwmac_match);
-- 
2.17.0



From narmstrong at baylibre.com  Thu Apr 26 01:32:55 2018
From: narmstrong at baylibre.com (Neil Armstrong)
Date: Thu, 26 Apr 2018 10:32:55 +0200
Subject: [PATCH] pinctrl: meson: axg: add tdm pins
In-Reply-To: <20180409145429.16619-1-jbrunet@baylibre.com>
References: <20180409145429.16619-1-jbrunet@baylibre.com>
Message-ID: <fc4e195e-095a-c04c-8ff8-37fadc22ab21@baylibre.com>

On 09/04/2018 16:54, Jerome Brunet wrote:
> Add the information related to the tdm pins of the A113D SoC
> 
> Signed-off-by: Jerome Brunet <jbrunet at baylibre.com>
> ---
>  drivers/pinctrl/meson/pinctrl-meson-axg.c | 107 ++++++++++++++++++++++++++++++
>  1 file changed, 107 insertions(+)
> 
> diff --git a/drivers/pinctrl/meson/pinctrl-meson-axg.c b/drivers/pinctrl/meson/pinctrl-meson-axg.c
> index 4b91ff74779b..11dc23fde6d5 100644
> --- a/drivers/pinctrl/meson/pinctrl-meson-axg.c
> +++ b/drivers/pinctrl/meson/pinctrl-meson-axg.c
> @@ -312,6 +312,47 @@ static const unsigned int pdm_din1_pins[] = {GPIOA_16};
>  static const unsigned int pdm_din2_pins[] = {GPIOA_17};
>  static const unsigned int pdm_din3_pins[] = {GPIOA_18};
>  
> +/* mclk */
> +static const unsigned int mclk_c_pins[] = {GPIOA_0};
> +static const unsigned int mclk_b_pins[] = {GPIOA_1};
> +
> +/* tdm */
> +static const unsigned int tdma_sclk_pins[] = {GPIOX_12};
> +static const unsigned int tdma_sclk_slv_pins[] = {GPIOX_12};
> +static const unsigned int tdma_fs_pins[] = {GPIOX_13};
> +static const unsigned int tdma_fs_slv_pins[] = {GPIOX_13};
> +static const unsigned int tdma_din0_pins[] = {GPIOX_14};
> +static const unsigned int tdma_dout0_x14_pins[] = {GPIOX_14};
> +static const unsigned int tdma_dout0_x15_pins[] = {GPIOX_15};
> +static const unsigned int tdma_dout1_pins[] = {GPIOX_15};
> +static const unsigned int tdma_din1_pins[] = {GPIOX_15};
> +
> +static const unsigned int tdmc_sclk_pins[] = {GPIOA_2};
> +static const unsigned int tdmc_sclk_slv_pins[] = {GPIOA_2};
> +static const unsigned int tdmc_fs_pins[] = {GPIOA_3};
> +static const unsigned int tdmc_fs_slv_pins[] = {GPIOA_3};
> +static const unsigned int tdmc_din0_pins[] = {GPIOA_4};
> +static const unsigned int tdmc_dout0_pins[] = {GPIOA_4};
> +static const unsigned int tdmc_din1_pins[] = {GPIOA_5};
> +static const unsigned int tdmc_dout1_pins[] = {GPIOA_5};
> +static const unsigned int tdmc_din2_pins[] = {GPIOA_6};
> +static const unsigned int tdmc_dout2_pins[] = {GPIOA_6};
> +static const unsigned int tdmc_din3_pins[] = {GPIOA_7};
> +static const unsigned int tdmc_dout3_pins[] = {GPIOA_7};
> +
> +static const unsigned int tdmb_sclk_pins[] = {GPIOA_8};
> +static const unsigned int tdmb_sclk_slv_pins[] = {GPIOA_8};
> +static const unsigned int tdmb_fs_pins[] = {GPIOA_9};
> +static const unsigned int tdmb_fs_slv_pins[] = {GPIOA_9};
> +static const unsigned int tdmb_din0_pins[] = {GPIOA_10};
> +static const unsigned int tdmb_dout0_pins[] = {GPIOA_10};
> +static const unsigned int tdmb_din1_pins[] = {GPIOA_11};
> +static const unsigned int tdmb_dout1_pins[] = {GPIOA_11};
> +static const unsigned int tdmb_din2_pins[] = {GPIOA_12};
> +static const unsigned int tdmb_dout2_pins[] = {GPIOA_12};
> +static const unsigned int tdmb_din3_pins[] = {GPIOA_13};
> +static const unsigned int tdmb_dout3_pins[] = {GPIOA_13};
> +
>  static struct meson_pmx_group meson_axg_periphs_groups[] = {
>  	GPIO_GROUP(GPIOZ_0),
>  	GPIO_GROUP(GPIOZ_1),
> @@ -495,6 +536,15 @@ static struct meson_pmx_group meson_axg_periphs_groups[] = {
>  	GROUP(eth_rx_dv_x, 4),
>  	GROUP(eth_mdio_x, 4),
>  	GROUP(eth_mdc_x, 4),
> +	GROUP(tdma_sclk, 1),
> +	GROUP(tdma_sclk_slv, 2),
> +	GROUP(tdma_fs, 1),
> +	GROUP(tdma_fs_slv, 2),
> +	GROUP(tdma_din0, 1),
> +	GROUP(tdma_dout0_x14, 2),
> +	GROUP(tdma_dout0_x15, 1),
> +	GROUP(tdma_dout1, 2),
> +	GROUP(tdma_din1, 3),
>  
>  	/* bank GPIOY */
>  	GROUP(eth_txd0_y, 1),
> @@ -544,6 +594,32 @@ static struct meson_pmx_group meson_axg_periphs_groups[] = {
>  	GROUP(pdm_din1, 1),
>  	GROUP(pdm_din2, 1),
>  	GROUP(pdm_din3, 1),
> +	GROUP(mclk_c, 1),
> +	GROUP(mclk_b, 1),
> +	GROUP(tdmc_sclk, 1),
> +	GROUP(tdmc_sclk_slv, 2),
> +	GROUP(tdmc_fs, 1),
> +	GROUP(tdmc_fs_slv, 2),
> +	GROUP(tdmc_din0, 2),
> +	GROUP(tdmc_dout0, 1),
> +	GROUP(tdmc_din1, 2),
> +	GROUP(tdmc_dout1, 1),
> +	GROUP(tdmc_din2, 2),
> +	GROUP(tdmc_dout2, 1),
> +	GROUP(tdmc_din3, 2),
> +	GROUP(tdmc_dout3, 1),
> +	GROUP(tdmb_sclk, 1),
> +	GROUP(tdmb_sclk_slv, 2),
> +	GROUP(tdmb_fs, 1),
> +	GROUP(tdmb_fs_slv, 2),
> +	GROUP(tdmb_din0, 2),
> +	GROUP(tdmb_dout0, 1),
> +	GROUP(tdmb_din1, 2),
> +	GROUP(tdmb_dout1, 1),
> +	GROUP(tdmb_din2, 2),
> +	GROUP(tdmb_dout2, 1),
> +	GROUP(tdmb_din3, 2),
> +	GROUP(tdmb_dout3, 1),
>  };
>  
>  /* uart_ao_a */
> @@ -845,6 +921,32 @@ static const char * const jtag_ao_groups[] = {
>  	"jtag_ao_tdi", "jtag_ao_tdo", "jtag_ao_clk", "jtag_ao_tms",
>  };
>  
> +static const char * const mclk_c_groups[] = {
> +	"mclk_c",
> +};
> +
> +static const char * const mclk_b_groups[] = {
> +	"mclk_b",
> +};
> +
> +static const char * const tdma_groups[] = {
> +	"tdma_sclk", "tdma_sclk_slv", "tdma_fs", "tdma_fs_slv",
> +	"tdma_din0", "tdma_dout0_x14", "tdma_dout0_x15", "tdma_dout1",
> +	"tdma_din1",
> +};
> +
> +static const char * const tdmc_groups[] = {
> +	"tdmc_sclk", "tdmc_sclk_slv", "tdmc_fs", "tdmc_fs_slv",
> +	"tdmc_din0", "tdmc_dout0", "tdmc_din1",	"tdmc_dout1",
> +	"tdmc_din2", "tdmc_dout2", "tdmc_din3",	"tdmc_dout3",
> +};
> +
> +static const char * const tdmb_groups[] = {
> +	"tdmb_sclk", "tdmb_sclk_slv", "tdmb_fs", "tdmb_fs_slv",
> +	"tdmb_din0", "tdmb_dout0", "tdmb_din1",	"tdmb_dout1",
> +	"tdmb_din2", "tdmb_dout2", "tdmb_din3",	"tdmb_dout3",
> +};
> +
>  static struct meson_pmx_func meson_axg_periphs_functions[] = {
>  	FUNCTION(gpio_periphs),
>  	FUNCTION(emmc),
> @@ -870,6 +972,11 @@ static struct meson_pmx_func meson_axg_periphs_functions[] = {
>  	FUNCTION(spdif_in),
>  	FUNCTION(jtag_ee),
>  	FUNCTION(pdm),
> +	FUNCTION(mclk_b),
> +	FUNCTION(mclk_c),
> +	FUNCTION(tdma),
> +	FUNCTION(tdmb),
> +	FUNCTION(tdmc),
>  };
>  
>  static struct meson_pmx_func meson_axg_aobus_functions[] = {
> 

Reviewed-by: Neil Armstrong <narmstrong at baylibre.com>


From narmstrong at baylibre.com  Thu Apr 26 01:35:33 2018
From: narmstrong at baylibre.com (Neil Armstrong)
Date: Thu, 26 Apr 2018 10:35:33 +0200
Subject: [PATCH] spi: meson-axg: Fix error handling in meson_spicc_probe()
In-Reply-To: <1523655586-4163-1-git-send-email-khoroshilov@ispras.ru>
References: <1523655586-4163-1-git-send-email-khoroshilov@ispras.ru>
Message-ID: <a2a9cde3-5192-ce05-cc5c-d0191f0e811a@baylibre.com>

Hi Alexey,


On 13/04/2018 23:39, Alexey Khoroshilov wrote:
> If devm_spi_register_master() fails in meson_spicc_probe(),
> spicc->core is left undisabled. The patch fixes that.
> 
> Found by Linux Driver Verification project (linuxtesting.org).
> 
> Signed-off-by: Alexey Khoroshilov <khoroshilov at ispras.ru>
> ---
>  drivers/spi/spi-meson-spicc.c | 11 ++++++++---
>  1 file changed, 8 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/spi/spi-meson-spicc.c b/drivers/spi/spi-meson-spicc.c
> index 5c82910e3480..7fe4488ace57 100644
> --- a/drivers/spi/spi-meson-spicc.c
> +++ b/drivers/spi/spi-meson-spicc.c
> @@ -574,10 +574,15 @@ static int meson_spicc_probe(struct platform_device *pdev)
>  		master->max_speed_hz = rate >> 2;
>  
>  	ret = devm_spi_register_master(&pdev->dev, master);
> -	if (!ret)
> -		return 0;
> +	if (ret) {
> +		dev_err(&pdev->dev, "spi master registration failed\n");
> +		goto out_clk;
> +	}
>  
> -	dev_err(&pdev->dev, "spi master registration failed\n");
> +	return 0;
> +
> +out_clk:
> +	clk_disable_unprepare(spicc->core);
>  
>  out_master:
>  	spi_master_put(master);
> 

The correct subject should be "spi: meson-spicc:"

Apart that :
Reviewed-by: Neil Armstrong <narmstrong at baylibre.com>

Neil


From narmstrong at baylibre.com  Thu Apr 26 01:36:28 2018
From: narmstrong at baylibre.com (Neil Armstrong)
Date: Thu, 26 Apr 2018 10:36:28 +0200
Subject: [PATCH] ARM64: dts: meson-axg: add tdm pins
In-Reply-To: <20180417064035.28776-1-jbrunet@baylibre.com>
References: <20180417064035.28776-1-jbrunet@baylibre.com>
Message-ID: <49f6e142-f958-c86a-e951-a3eb7aa4e720@baylibre.com>

On 17/04/2018 08:40, Jerome Brunet wrote:
> Add tdm pins to amlogic's A113 device tree
> 
> Signed-off-by: Jerome Brunet <jbrunet at baylibre.com>
> ---
>  arch/arm64/boot/dts/amlogic/meson-axg.dtsi | 245 +++++++++++++++++++++++++++++
>  1 file changed, 245 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
> index b58808eb3cc8..74013965e86a 100644
> --- a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
> +++ b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
> @@ -660,6 +660,251 @@
>  						function = "uart_ao_b_z";
>  					};
>  				};
> +
> +				mclk_b_pins: mclk_b {
> +					mux {
> +						groups = "mclk_b";
> +						function = "mclk_b";
> +					};
> +				};
> +
> +				mclk_c_pins: mclk_c {
> +					mux {
> +						groups = "mclk_c";
> +						function = "mclk_c";
> +					};
> +				};
> +
> +				tdma_sclk_pins: tdma_sclk {
> +					mux {
> +						groups = "tdma_sclk";
> +						function = "tdma";
> +					};
> +				};
> +
> +				tdma_sclk_slv_pins: tdma_sclk_slv {
> +					mux {
> +						groups = "tdma_sclk_slv";
> +						function = "tdma";
> +					};
> +				};
> +
> +				tdma_fs_pins: tdma_fs {
> +					mux {
> +						groups = "tdma_fs";
> +						function = "tdma";
> +					};
> +				};
> +
> +				tdma_fs_slv_pins: tdma_fs_slv {
> +					mux {
> +						groups = "tdma_fs_slv";
> +						function = "tdma";
> +					};
> +				};
> +
> +				tdma_din0_pins: tdma_din0 {
> +					mux {
> +						groups = "tdma_din0";
> +						function = "tdma";
> +					};
> +				};
> +
> +				tdma_dout0_x14_pins: tdma_dout0_x14 {
> +					mux {
> +						groups = "tdma_dout0_x14";
> +						function = "tdma";
> +					};
> +				};
> +
> +				tdma_dout0_x15_pins: tdma_dout0_x15 {
> +					mux {
> +						groups = "tdma_dout0_x15";
> +						function = "tdma";
> +					};
> +				};
> +
> +				tdma_dout1_pins: tdma_dout1 {
> +					mux {
> +						groups = "tdma_dout1";
> +						function = "tdma";
> +					};
> +				};
> +
> +				tdma_din1_pins: tdma_din1 {
> +					mux {
> +						groups = "tdma_din1";
> +						function = "tdma";
> +					};
> +				};
> +
> +				tdmb_sclk_pins: tdmb_sclk {
> +					mux {
> +						groups = "tdmb_sclk";
> +						function = "tdmb";
> +					};
> +				};
> +
> +				tdmb_sclk_slv_pins: tdmb_sclk_slv {
> +					mux {
> +						groups = "tdmb_sclk_slv";
> +						function = "tdmb";
> +					};
> +				};
> +
> +				tdmb_fs_pins: tdmb_fs {
> +					mux {
> +						groups = "tdmb_fs";
> +						function = "tdmb";
> +					};
> +				};
> +
> +				tdmb_fs_slv_pins: tdmb_fs_slv {
> +					mux {
> +						groups = "tdmb_fs_slv";
> +						function = "tdmb";
> +					};
> +				};
> +
> +				tdmb_din0_pins: tdmb_din0 {
> +					mux {
> +						groups = "tdmb_din0";
> +						function = "tdmb";
> +					};
> +				};
> +
> +				tdmb_dout0_pins: tdmb_dout0 {
> +					mux {
> +						groups = "tdmb_dout0";
> +						function = "tdmb";
> +					};
> +				};
> +
> +				tdmb_din1_pins: tdmb_din1 {
> +					mux {
> +						groups = "tdmb_din1";
> +						function = "tdmb";
> +					};
> +				};
> +
> +				tdmb_dout1_pins: tdmb_dout1 {
> +					mux {
> +						groups = "tdmb_dout1";
> +						function = "tdmb";
> +					};
> +				};
> +
> +				tdmb_din2_pins: tdmb_din2 {
> +					mux {
> +						groups = "tdmb_din2";
> +						function = "tdmb";
> +					};
> +				};
> +
> +				tdmb_dout2_pins: tdmb_dout2 {
> +					mux {
> +						groups = "tdmb_dout2";
> +						function = "tdmb";
> +					};
> +				};
> +
> +				tdmb_din3_pins: tdmb_din3 {
> +					mux {
> +						groups = "tdmb_din3";
> +						function = "tdmb";
> +					};
> +				};
> +
> +				tdmb_dout3_pins: tdmb_dout3 {
> +					mux {
> +						groups = "tdmb_dout3";
> +						function = "tdmb";
> +					};
> +				};
> +
> +				tdmc_sclk_pins: tdmc_sclk {
> +					mux {
> +						groups = "tdmc_sclk";
> +						function = "tdmc";
> +					};
> +				};
> +
> +				tdmc_sclk_slv_pins: tdmc_sclk_slv {
> +					mux {
> +						groups = "tdmc_sclk_slv";
> +						function = "tdmc";
> +					};
> +				};
> +
> +				tdmc_fs_pins: tdmc_fs {
> +					mux {
> +						groups = "tdmc_fs";
> +						function = "tdmc";
> +					};
> +				};
> +
> +				tdmc_fs_slv_pins: tdmc_fs_slv {
> +					mux {
> +						groups = "tdmc_fs_slv";
> +						function = "tdmc";
> +					};
> +				};
> +
> +				tdmc_din0_pins: tdmc_din0 {
> +					mux {
> +						groups = "tdmc_din0";
> +						function = "tdmc";
> +					};
> +				};
> +
> +				tdmc_dout0_pins: tdmc_dout0 {
> +					mux {
> +						groups = "tdmc_dout0";
> +						function = "tdmc";
> +					};
> +				};
> +
> +				tdmc_din1_pins: tdmc_din1 {
> +					mux {
> +						groups = "tdmc_din1";
> +						function = "tdmc";
> +					};
> +				};
> +
> +				tdmc_dout1_pins: tdmc_dout1 {
> +					mux {
> +						groups = "tdmc_dout1";
> +						function = "tdmc";
> +					};
> +				};
> +
> +				tdmc_din2_pins: tdmc_din2 {
> +					mux {
> +						groups = "tdmc_din2";
> +						function = "tdmc";
> +					};
> +				};
> +
> +				tdmc_dout2_pins: tdmc_dout2 {
> +					mux {
> +						groups = "tdmc_dout2";
> +						function = "tdmc";
> +					};
> +				};
> +
> +				tdmc_din3_pins: tdmc_din3 {
> +					mux {
> +						groups = "tdmc_din3";
> +						function = "tdmc";
> +					};
> +				};
> +
> +				tdmc_dout3_pins: tdmc_dout3 {
> +					mux {
> +						groups = "tdmc_dout3";
> +						function = "tdmc";
> +					};
> +				};
>  			};
>  		};
>  
> 

Reviewed-by: Neil Armstrong <narmstrong at baylibre.com>


From narmstrong at baylibre.com  Thu Apr 26 01:38:08 2018
From: narmstrong at baylibre.com (Neil Armstrong)
Date: Thu, 26 Apr 2018 10:38:08 +0200
Subject: [PATCH] drm: bridge: dw-hdmi: Fix overflow workaround for Amlogic
 Meson GX SoCs
In-Reply-To: <20180419082751.GA23187@kroah.com>
References: <1519386277-25902-1-git-send-email-narmstrong@baylibre.com>
 <3b17d17b-cf3d-be54-2462-191e4f2af653@baylibre.com>
 <20180419082751.GA23187@kroah.com>
Message-ID: <8766c753-bc2c-0e54-0ac0-73acaa0e11d8@baylibre.com>

Hi Greg,

On 19/04/2018 10:27, Greg KH wrote:
> On Thu, Apr 19, 2018 at 10:18:35AM +0200, Neil Armstrong wrote:
>> Hi Greg,
>>
>> On 23/02/2018 12:44, Neil Armstrong wrote:
>>> The Amlogic Meson GX SoCs, embedded the v2.01a controller, has been also
>>> identified needing this workaround.
>>> This patch adds the corresponding version to enable a single iteration for
>>> this specific version.
>>>
>>> Fixes: be41fc55f1aa ("drm: bridge: dw-hdmi: Handle overflow workaround based on device version")
>>> Signed-off-by: Neil Armstrong <narmstrong at baylibre.com>
>>
>> This patch is now present in linux master as commit 9c305eb442f3b371fc722ade827bbf673514123e
>> Could it be selected for 4.14 ?
>> The patch has been reworked to apply for 4.17 as indicated in the commit log, but the original patch will apply over 4.14.
> 
> I don't have any "original" patch here, I just tried applying it to
> 4.16.y and 4.14.y and it did not work.  Can you please provide a working
> backport?

I sent a backported version last week, any news of it ?

Message-Id: <1524128048-11086-1-git-send-email-narmstrong at baylibre.com>

Thanks,
Neil

> 
> thanks,
> 
> greg k-h
> 



From narmstrong at baylibre.com  Thu Apr 26 01:39:56 2018
From: narmstrong at baylibre.com (Neil Armstrong)
Date: Thu, 26 Apr 2018 10:39:56 +0200
Subject: [PATCH 1/2] clk: meson: mpll: add round closest support
In-Reply-To: <20180420095603.29964-2-jbrunet@baylibre.com>
References: <20180420095603.29964-1-jbrunet@baylibre.com>
 <20180420095603.29964-2-jbrunet@baylibre.com>
Message-ID: <f60eb9b0-c9dc-e9bd-1c2d-6df01a583a35@baylibre.com>

On 20/04/2018 11:56, Jerome Brunet wrote:
> Allow the mpll driver to round the requested rate up if
> CLK_MESON_MPLL_ROUND_CLOSEST is set and it provides a rate closer to the
> requested rate.
> 
> Signed-off-by: Jerome Brunet <jbrunet at baylibre.com>
> ---
>  drivers/clk/meson/clk-mpll.c | 25 ++++++++++++++++++++-----
>  drivers/clk/meson/clkc.h     |  3 +++
>  2 files changed, 23 insertions(+), 5 deletions(-)
> 
> diff --git a/drivers/clk/meson/clk-mpll.c b/drivers/clk/meson/clk-mpll.c
> index 0df1227b65b3..4e5283eb892a 100644
> --- a/drivers/clk/meson/clk-mpll.c
> +++ b/drivers/clk/meson/clk-mpll.c
> @@ -89,10 +89,23 @@ static long rate_from_params(unsigned long parent_rate,
>  static void params_from_rate(unsigned long requested_rate,
>  			     unsigned long parent_rate,
>  			     unsigned int *sdm,
> -			     unsigned int *n2)
> +			     unsigned int *n2,
> +			     u8 flags)
>  {
>  	uint64_t div = parent_rate;
> -	unsigned long rem = do_div(div, requested_rate);
> +	uint64_t frac = do_div(div, requested_rate);
> +	unsigned long rem;
> +
> +	frac *= SDM_DEN;
> +	rem = do_div(frac, requested_rate);
> +
> +	/* Should we round up ? */
> +	if (flags & CLK_MESON_MPLL_ROUND_CLOSEST
> +	    && rem > (requested_rate / 2)) {
> +		frac = (frac + 1) % SDM_DEN;
> +		if (frac == 0)
> +			div += 1;
> +	}
>  
>  	if (div < N2_MIN) {
>  		*n2 = N2_MIN;
> @@ -102,7 +115,7 @@ static void params_from_rate(unsigned long requested_rate,
>  		*sdm = SDM_DEN - 1;
>  	} else {
>  		*n2 = div;
> -		*sdm = DIV_ROUND_UP_ULL((u64)rem * SDM_DEN, requested_rate);
> +		*sdm = frac;
>  	}
>  }
>  
> @@ -125,9 +138,11 @@ static long mpll_round_rate(struct clk_hw *hw,
>  			    unsigned long rate,
>  			    unsigned long *parent_rate)
>  {
> +	struct clk_regmap *clk = to_clk_regmap(hw);
> +	struct meson_clk_mpll_data *mpll = meson_clk_mpll_data(clk);
>  	unsigned int sdm, n2;
>  
> -	params_from_rate(rate, *parent_rate, &sdm, &n2);
> +	params_from_rate(rate, *parent_rate, &sdm, &n2, mpll->flags);
>  	return rate_from_params(*parent_rate, sdm, n2);
>  }
>  
> @@ -140,7 +155,7 @@ static int mpll_set_rate(struct clk_hw *hw,
>  	unsigned int sdm, n2;
>  	unsigned long flags = 0;
>  
> -	params_from_rate(rate, parent_rate, &sdm, &n2);
> +	params_from_rate(rate, parent_rate, &sdm, &n2, mpll->flags);
>  
>  	if (mpll->lock)
>  		spin_lock_irqsave(mpll->lock, flags);
> diff --git a/drivers/clk/meson/clkc.h b/drivers/clk/meson/clkc.h
> index 8fe73c4edca8..8cc265cd3d2b 100644
> --- a/drivers/clk/meson/clkc.h
> +++ b/drivers/clk/meson/clkc.h
> @@ -97,8 +97,11 @@ struct meson_clk_mpll_data {
>  	struct parm ssen;
>  	struct parm misc;
>  	spinlock_t *lock;
> +	u8 flags;
>  };
>  
> +#define CLK_MESON_MPLL_ROUND_CLOSEST	BIT(0)
> +
>  struct meson_clk_audio_div_data {
>  	struct parm div;
>  	u8 flags;
> 

Acked-by: Neil Armstrong <narmstrong at baylibre.com>


From narmstrong at baylibre.com  Thu Apr 26 01:40:04 2018
From: narmstrong at baylibre.com (Neil Armstrong)
Date: Thu, 26 Apr 2018 10:40:04 +0200
Subject: [PATCH 2/2] clk: meson: axg: let mpll clocks round closest
In-Reply-To: <20180420095603.29964-3-jbrunet@baylibre.com>
References: <20180420095603.29964-1-jbrunet@baylibre.com>
 <20180420095603.29964-3-jbrunet@baylibre.com>
Message-ID: <7c6068d6-299d-698f-dec7-13cdf6b85f6e@baylibre.com>

On 20/04/2018 11:56, Jerome Brunet wrote:
> Let the mpll dividers achieve the closest rate possible, even if
> it means rounding the requested rate up.
> 
> This is done to improve the accuracy of the rates provided by these
> plls to the audio subsystem
> 
> Signed-off-by: Jerome Brunet <jbrunet at baylibre.com>
> ---
>  drivers/clk/meson/axg.c | 4 ++++
>  1 file changed, 4 insertions(+)
> 
> diff --git a/drivers/clk/meson/axg.c b/drivers/clk/meson/axg.c
> index 5f5d468c1efe..bd4dbc696b88 100644
> --- a/drivers/clk/meson/axg.c
> +++ b/drivers/clk/meson/axg.c
> @@ -461,6 +461,7 @@ static struct clk_regmap axg_mpll0_div = {
>  			.width	 = 1,
>  		},
>  		.lock = &meson_clk_lock,
> +		.flags = CLK_MESON_MPLL_ROUND_CLOSEST,
>  	},
>  	.hw.init = &(struct clk_init_data){
>  		.name = "mpll0_div",
> @@ -507,6 +508,7 @@ static struct clk_regmap axg_mpll1_div = {
>  			.width	 = 1,
>  		},
>  		.lock = &meson_clk_lock,
> +		.flags = CLK_MESON_MPLL_ROUND_CLOSEST,
>  	},
>  	.hw.init = &(struct clk_init_data){
>  		.name = "mpll1_div",
> @@ -553,6 +555,7 @@ static struct clk_regmap axg_mpll2_div = {
>  			.width	 = 1,
>  		},
>  		.lock = &meson_clk_lock,
> +		.flags = CLK_MESON_MPLL_ROUND_CLOSEST,
>  	},
>  	.hw.init = &(struct clk_init_data){
>  		.name = "mpll2_div",
> @@ -599,6 +602,7 @@ static struct clk_regmap axg_mpll3_div = {
>  			.width	 = 1,
>  		},
>  		.lock = &meson_clk_lock,
> +		.flags = CLK_MESON_MPLL_ROUND_CLOSEST,
>  	},
>  	.hw.init = &(struct clk_init_data){
>  		.name = "mpll3_div",
> 

Acked-by: Neil Armstrong <narmstrong at baylibre.com>


From narmstrong at baylibre.com  Thu Apr 26 01:40:56 2018
From: narmstrong at baylibre.com (Neil Armstrong)
Date: Thu, 26 Apr 2018 10:40:56 +0200
Subject: [PATCH] dt-bindings: meson-uart: DT fix
 s/clocks-names/clock-names/
In-Reply-To: <1524468760-22912-1-git-send-email-geert+renesas@glider.be>
References: <1524468760-22912-1-git-send-email-geert+renesas@glider.be>
Message-ID: <8ca5eed0-8dd6-b411-32a6-d63c62ff9e04@baylibre.com>

On 23/04/2018 09:32, Geert Uytterhoeven wrote:
> Signed-off-by: Geert Uytterhoeven <geert+renesas at glider.be>
> ---
>  Documentation/devicetree/bindings/serial/amlogic,meson-uart.txt | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/Documentation/devicetree/bindings/serial/amlogic,meson-uart.txt b/Documentation/devicetree/bindings/serial/amlogic,meson-uart.txt
> index 8ff65fa632fdedd7..c06c045126fc9070 100644
> --- a/Documentation/devicetree/bindings/serial/amlogic,meson-uart.txt
> +++ b/Documentation/devicetree/bindings/serial/amlogic,meson-uart.txt
> @@ -21,7 +21,7 @@ Required properties:
>  - interrupts : identifier to the device interrupt
>  - clocks : a list of phandle + clock-specifier pairs, one for each
>  	   entry in clock names.
> -- clocks-names :
> +- clock-names :
>     * "xtal" for external xtal clock identifier
>     * "pclk" for the bus core clock, either the clk81 clock or the gate clock
>     * "baud" for the source of the baudrate generator, can be either the xtal
> 

Acked-by: Neil Armstrong <narmstrong at baylibre.com>


From yixun.lan at amlogic.com  Thu Apr 26 01:44:30 2018
From: yixun.lan at amlogic.com (Yixun Lan)
Date: Thu, 26 Apr 2018 16:44:30 +0800
Subject: [PATCH v7 0/7] clk: meson-axg: Add AO Cloclk and Reset driver
Message-ID: <20180426084437.192394-1-yixun.lan@amlogic.com>

  This patch try to add AO clock and Reset driver for Amlogic's
Meson-AXG SoC.
  Please note that patch 7 need to wait for the DTS changes[3] merged
into mainline first, otherwise it will break the serial console.

 patch 2: factor the common code into a dedicated file
 patch 3-5: add the aoclk driver for AXG SoC
 patch 6-7: drop unnecessary clock flags

changes since v6 at [7]: 
 - fix over 80 chars chechpatch error
 - add Philip's Ack on patch 5
 - drop extra end of newline

changes since v5 at [6]: 
 - drop unnecessary header files
 - add 'axg_aoclk' prefix to clk driver, make them more consistent
 - add missing end new line..

changes since v4 at [5]: 
 - fix return err
 - introduce CONFIG_COMMON_CLK_MESON_AO
 - format/style minor fix

changes since v3 at [4]: 
 - add 'const' contraint to the read-only data
 - switch to devm_of_clk_add_hw_provider API
 - check return value of devm_reset_controller_register

changes since v2 at [2]: 
 - rework meson_aoclkc_probe() which leverage the of_match_data
 - merge patch 5-6 into this series
 - seperate DTS patch, will send to Kevin Hilman independently
 
changes since v1 at [0]: 
 - rebase to clk-meson's branch 'next/drivers' [1]
 - fix license, update to BSD-3-Clause
 - drop un-used include header file

[0] https://lkml.kernel.org/r/20180209070026.193879-1-yixun.lan at amlogic.com
[1] git://github.com/BayLibre/clk-meson.git branch: next-drivers
[2] https://lkml.kernel.org/r/20180323143816.200573-1-yixun.lan at amlogic.com
[3] https://lkml.kernel.org/r/20180326081809.49493-4-yixun.lan at amlogic.com
[4] https://lkml.kernel.org/r/20180328025050.221585-1-yixun.lan at amlogic.com
[5] https://lkml.kernel.org/r/20180408031938.153474-1-yixun.lan at amlogic.com
[6] https://lkml.kernel.org/r/20180409143749.71197-1-yixun.lan at amlogic.com
[7] https://lkml.kernel.org/r/20180419135426.155794-1-yixun.lan at amlogic.com


Qiufang Dai (1):
  clk: meson-axg: Add AO Clock and Reset controller driver

Yixun Lan (6):
  clk: meson: migrate to devm_of_clk_add_hw_provider API
  clk: meson: aoclk: refactor common code into dedicated file
  dt-bindings: clock: axg-aoclkc: New binding for Meson-AXG SoC
  dt-bindings: clock: reset: Add AXG AO Clock and Reset Bindings
  clk: meson: drop CLK_SET_RATE_PARENT flag
  clk: meson: drop CLK_IGNORE_UNUSED flag

 .../bindings/clock/amlogic,gxbb-aoclkc.txt    |   1 +
 drivers/clk/meson/Kconfig                     |   8 +
 drivers/clk/meson/Makefile                    |   3 +-
 drivers/clk/meson/axg-aoclk.c                 | 163 ++++++++++++++++++
 drivers/clk/meson/axg-aoclk.h                 |  29 ++++
 drivers/clk/meson/gxbb-aoclk.c                |  95 ++++------
 drivers/clk/meson/gxbb-aoclk.h                |   5 +
 drivers/clk/meson/meson-aoclk.c               |  81 +++++++++
 drivers/clk/meson/meson-aoclk.h               |  34 ++++
 include/dt-bindings/clock/axg-aoclkc.h        |  26 +++
 include/dt-bindings/reset/axg-aoclkc.h        |  20 +++
 11 files changed, 401 insertions(+), 64 deletions(-)
 create mode 100644 drivers/clk/meson/axg-aoclk.c
 create mode 100644 drivers/clk/meson/axg-aoclk.h
 create mode 100644 drivers/clk/meson/meson-aoclk.c
 create mode 100644 drivers/clk/meson/meson-aoclk.h
 create mode 100644 include/dt-bindings/clock/axg-aoclkc.h
 create mode 100644 include/dt-bindings/reset/axg-aoclkc.h

-- 
2.17.0



From yixun.lan at amlogic.com  Thu Apr 26 01:44:31 2018
From: yixun.lan at amlogic.com (Yixun Lan)
Date: Thu, 26 Apr 2018 16:44:31 +0800
Subject: [PATCH v7 1/7] clk: meson: migrate to devm_of_clk_add_hw_provider API
In-Reply-To: <20180426084437.192394-1-yixun.lan@amlogic.com>
References: <20180426084437.192394-1-yixun.lan@amlogic.com>
Message-ID: <20180426084437.192394-2-yixun.lan@amlogic.com>

There is a protential memory leak, as of_clk_del_provider is
never called if of_clk_add_hw_provider has been executed.
Fix this by using devm variant API.

Fixes: f8c11f79912d ("clk: meson: Add GXBB AO Clock and Reset controller driver")
Suggested-by: Stephen Boyd <sboyd at kernel.org>
Signed-off-by: Yixun Lan <yixun.lan at amlogic.com>
---
 drivers/clk/meson/gxbb-aoclk.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/clk/meson/gxbb-aoclk.c b/drivers/clk/meson/gxbb-aoclk.c
index 9ec23ae9a219..eebb580b9e0f 100644
--- a/drivers/clk/meson/gxbb-aoclk.c
+++ b/drivers/clk/meson/gxbb-aoclk.c
@@ -191,7 +191,7 @@ static int gxbb_aoclkc_probe(struct platform_device *pdev)
 	if (ret)
 		return ret;
 
-	return of_clk_add_hw_provider(dev->of_node, of_clk_hw_onecell_get,
+	return devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get,
 			&gxbb_aoclk_onecell_data);
 }
 
-- 
2.17.0



From yixun.lan at amlogic.com  Thu Apr 26 01:44:32 2018
From: yixun.lan at amlogic.com (Yixun Lan)
Date: Thu, 26 Apr 2018 16:44:32 +0800
Subject: [PATCH v7 2/7] clk: meson: aoclk: refactor common code into dedicated
 file
In-Reply-To: <20180426084437.192394-1-yixun.lan@amlogic.com>
References: <20180426084437.192394-1-yixun.lan@amlogic.com>
Message-ID: <20180426084437.192394-3-yixun.lan@amlogic.com>

We try to refactor the common code into one dedicated file,
while preparing to add new Meson-AXG aoclk driver, this would
help us to better share the code by all aoclk drivers.

Suggested-by: Jerome Brunet <jbrunet at baylibre.com>
Signed-off-by: Yixun Lan <yixun.lan at amlogic.com>
---
 drivers/clk/meson/Kconfig       |  7 +++
 drivers/clk/meson/Makefile      |  1 +
 drivers/clk/meson/gxbb-aoclk.c  | 94 +++++++++++----------------------
 drivers/clk/meson/gxbb-aoclk.h  |  5 ++
 drivers/clk/meson/meson-aoclk.c | 81 ++++++++++++++++++++++++++++
 drivers/clk/meson/meson-aoclk.h | 34 ++++++++++++
 6 files changed, 160 insertions(+), 62 deletions(-)
 create mode 100644 drivers/clk/meson/meson-aoclk.c
 create mode 100644 drivers/clk/meson/meson-aoclk.h

diff --git a/drivers/clk/meson/Kconfig b/drivers/clk/meson/Kconfig
index d5cbec522aec..fddc7ec7b820 100644
--- a/drivers/clk/meson/Kconfig
+++ b/drivers/clk/meson/Kconfig
@@ -3,6 +3,12 @@ config COMMON_CLK_AMLOGIC
 	depends on OF
 	depends on ARCH_MESON || COMPILE_TEST
 
+config COMMON_CLK_MESON_AO
+	bool
+	depends on OF
+	depends on ARCH_MESON || COMPILE_TEST
+	select COMMON_CLK_REGMAP_MESON
+
 config COMMON_CLK_REGMAP_MESON
 	bool
 	select REGMAP
@@ -21,6 +27,7 @@ config COMMON_CLK_GXBB
 	bool
 	depends on COMMON_CLK_AMLOGIC
 	select RESET_CONTROLLER
+	select COMMON_CLK_MESON_AO
 	select COMMON_CLK_REGMAP_MESON
 	select MFD_SYSCON
 	help
diff --git a/drivers/clk/meson/Makefile b/drivers/clk/meson/Makefile
index ffee82e60b7a..0a8df284f4e7 100644
--- a/drivers/clk/meson/Makefile
+++ b/drivers/clk/meson/Makefile
@@ -3,6 +3,7 @@
 #
 
 obj-$(CONFIG_COMMON_CLK_AMLOGIC) += clk-pll.o clk-mpll.o clk-audio-divider.o
+obj-$(CONFIG_COMMON_CLK_MESON_AO) += meson-aoclk.o
 obj-$(CONFIG_COMMON_CLK_MESON8B) += meson8b.o
 obj-$(CONFIG_COMMON_CLK_GXBB)	 += gxbb.o gxbb-aoclk.o gxbb-aoclk-32k.o
 obj-$(CONFIG_COMMON_CLK_AXG)	 += axg.o
diff --git a/drivers/clk/meson/gxbb-aoclk.c b/drivers/clk/meson/gxbb-aoclk.c
index eebb580b9e0f..20f73e0d82a4 100644
--- a/drivers/clk/meson/gxbb-aoclk.c
+++ b/drivers/clk/meson/gxbb-aoclk.c
@@ -52,39 +52,12 @@
  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */
-#include <linux/clk-provider.h>
-#include <linux/of_address.h>
 #include <linux/platform_device.h>
-#include <linux/reset-controller.h>
 #include <linux/mfd/syscon.h>
-#include <linux/regmap.h>
-#include <linux/init.h>
-#include <linux/delay.h>
-#include <dt-bindings/clock/gxbb-aoclkc.h>
-#include <dt-bindings/reset/gxbb-aoclkc.h>
 #include "clk-regmap.h"
+#include "meson-aoclk.h"
 #include "gxbb-aoclk.h"
 
-struct gxbb_aoclk_reset_controller {
-	struct reset_controller_dev reset;
-	unsigned int *data;
-	struct regmap *regmap;
-};
-
-static int gxbb_aoclk_do_reset(struct reset_controller_dev *rcdev,
-			       unsigned long id)
-{
-	struct gxbb_aoclk_reset_controller *reset =
-		container_of(rcdev, struct gxbb_aoclk_reset_controller, reset);
-
-	return regmap_write(reset->regmap, AO_RTI_GEN_CNTL_REG0,
-			    BIT(reset->data[id]));
-}
-
-static const struct reset_control_ops gxbb_aoclk_reset_ops = {
-	.reset = gxbb_aoclk_do_reset,
-};
-
 #define GXBB_AO_GATE(_name, _bit)					\
 static struct clk_regmap _name##_ao = {					\
 	.data = &(struct clk_regmap_gate_data) {			\
@@ -117,7 +90,7 @@ static struct aoclk_cec_32k cec_32k_ao = {
 	},
 };
 
-static unsigned int gxbb_aoclk_reset[] = {
+static const unsigned int gxbb_aoclk_reset[] = {
 	[RESET_AO_REMOTE] = 16,
 	[RESET_AO_I2C_MASTER] = 18,
 	[RESET_AO_I2C_SLAVE] = 19,
@@ -135,7 +108,7 @@ static struct clk_regmap *gxbb_aoclk_gate[] = {
 	[CLKID_AO_IR_BLASTER] = &ir_blaster_ao,
 };
 
-static struct clk_hw_onecell_data gxbb_aoclk_onecell_data = {
+static const struct clk_hw_onecell_data gxbb_aoclk_onecell_data = {
 	.hws = {
 		[CLKID_AO_REMOTE] = &remote_ao.hw,
 		[CLKID_AO_I2C_MASTER] = &i2c_master_ao.hw,
@@ -145,58 +118,55 @@ static struct clk_hw_onecell_data gxbb_aoclk_onecell_data = {
 		[CLKID_AO_IR_BLASTER] = &ir_blaster_ao.hw,
 		[CLKID_AO_CEC_32K] = &cec_32k_ao.hw,
 	},
-	.num = 7,
+	.num = NR_CLKS,
 };
 
-static int gxbb_aoclkc_probe(struct platform_device *pdev)
+static int gxbb_register_cec_ao_32k(struct platform_device *pdev)
 {
-	struct gxbb_aoclk_reset_controller *rstc;
 	struct device *dev = &pdev->dev;
 	struct regmap *regmap;
-	int ret, clkid;
-
-	rstc = devm_kzalloc(dev, sizeof(*rstc), GFP_KERNEL);
-	if (!rstc)
-		return -ENOMEM;
+	int ret;
 
 	regmap = syscon_node_to_regmap(of_get_parent(dev->of_node));
 	if (IS_ERR(regmap)) {
 		dev_err(dev, "failed to get regmap\n");
-		return -ENODEV;
-	}
-
-	/* Reset Controller */
-	rstc->regmap = regmap;
-	rstc->data = gxbb_aoclk_reset;
-	rstc->reset.ops = &gxbb_aoclk_reset_ops;
-	rstc->reset.nr_resets = ARRAY_SIZE(gxbb_aoclk_reset);
-	rstc->reset.of_node = dev->of_node;
-	ret = devm_reset_controller_register(dev, &rstc->reset);
-
-	/*
-	 * Populate regmap and register all clks
-	 */
-	for (clkid = 0; clkid < ARRAY_SIZE(gxbb_aoclk_gate); clkid++) {
-		gxbb_aoclk_gate[clkid]->map = regmap;
-
-		ret = devm_clk_hw_register(dev,
-					   gxbb_aoclk_onecell_data.hws[clkid]);
-		if (ret)
-			return ret;
+		return PTR_ERR(regmap);
 	}
 
 	/* Specific clocks */
 	cec_32k_ao.regmap = regmap;
 	ret = devm_clk_hw_register(dev, &cec_32k_ao.hw);
+	if (ret) {
+		dev_err(&pdev->dev, "clk cec_32k_ao register failed.\n");
+		return ret;
+	}
+
+	return 0;
+}
+
+static const struct meson_aoclk_data gxbb_aoclkc_data = {
+	.reset_reg	= AO_RTI_GEN_CNTL_REG0,
+	.num_reset	= ARRAY_SIZE(gxbb_aoclk_reset),
+	.reset		= gxbb_aoclk_reset,
+	.num_clks	= ARRAY_SIZE(gxbb_aoclk_gate),
+	.clks		= gxbb_aoclk_gate,
+	.hw_data	= &gxbb_aoclk_onecell_data,
+};
+
+static int gxbb_aoclkc_probe(struct platform_device *pdev)
+{
+	int ret = gxbb_register_cec_ao_32k(pdev);
 	if (ret)
 		return ret;
 
-	return devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get,
-			&gxbb_aoclk_onecell_data);
+	return meson_aoclkc_probe(pdev);
 }
 
 static const struct of_device_id gxbb_aoclkc_match_table[] = {
-	{ .compatible = "amlogic,meson-gx-aoclkc" },
+	{
+		.compatible	= "amlogic,meson-gx-aoclkc",
+		.data		= &gxbb_aoclkc_data,
+	},
 	{ }
 };
 
diff --git a/drivers/clk/meson/gxbb-aoclk.h b/drivers/clk/meson/gxbb-aoclk.h
index badc4c22b4ee..6e7fa4134a00 100644
--- a/drivers/clk/meson/gxbb-aoclk.h
+++ b/drivers/clk/meson/gxbb-aoclk.h
@@ -8,6 +8,8 @@
 #ifndef __GXBB_AOCLKC_H
 #define __GXBB_AOCLKC_H
 
+#define NR_CLKS	7
+
 /* AO Configuration Clock registers offsets */
 #define AO_RTI_PWR_CNTL_REG1	0x0c
 #define AO_RTI_PWR_CNTL_REG0	0x10
@@ -26,4 +28,7 @@ struct aoclk_cec_32k {
 
 extern const struct clk_ops meson_aoclk_cec_32k_ops;
 
+#include <dt-bindings/clock/gxbb-aoclkc.h>
+#include <dt-bindings/reset/gxbb-aoclkc.h>
+
 #endif /* __GXBB_AOCLKC_H */
diff --git a/drivers/clk/meson/meson-aoclk.c b/drivers/clk/meson/meson-aoclk.c
new file mode 100644
index 000000000000..f965845917e3
--- /dev/null
+++ b/drivers/clk/meson/meson-aoclk.c
@@ -0,0 +1,81 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Amlogic Meson-AXG Clock Controller Driver
+ *
+ * Copyright (c) 2016 BayLibre, SAS.
+ * Author: Neil Armstrong <narmstrong at baylibre.com>
+ *
+ * Copyright (c) 2018 Amlogic, inc.
+ * Author: Qiufang Dai <qiufang.dai at amlogic.com>
+ * Author: Yixun Lan <yixun.lan at amlogic.com>
+ */
+
+#include <linux/platform_device.h>
+#include <linux/reset-controller.h>
+#include <linux/mfd/syscon.h>
+#include <linux/of_device.h>
+#include "clk-regmap.h"
+#include "meson-aoclk.h"
+
+static int meson_aoclk_do_reset(struct reset_controller_dev *rcdev,
+			       unsigned long id)
+{
+	struct meson_aoclk_reset_controller *rstc =
+		container_of(rcdev, struct meson_aoclk_reset_controller, reset);
+
+	return regmap_write(rstc->regmap, rstc->data->reset_reg,
+			    BIT(rstc->data->reset[id]));
+}
+
+static const struct reset_control_ops meson_aoclk_reset_ops = {
+	.reset = meson_aoclk_do_reset,
+};
+
+int meson_aoclkc_probe(struct platform_device *pdev)
+{
+	struct meson_aoclk_reset_controller *rstc;
+	struct meson_aoclk_data *data;
+	struct device *dev = &pdev->dev;
+	struct regmap *regmap;
+	int ret, clkid;
+
+	data = (struct meson_aoclk_data *) of_device_get_match_data(dev);
+	if (!data)
+		return -ENODEV;
+
+	rstc = devm_kzalloc(dev, sizeof(*rstc), GFP_KERNEL);
+	if (!rstc)
+		return -ENOMEM;
+
+	regmap = syscon_node_to_regmap(of_get_parent(dev->of_node));
+	if (IS_ERR(regmap)) {
+		dev_err(dev, "failed to get regmap\n");
+		return PTR_ERR(regmap);
+	}
+
+	/* Reset Controller */
+	rstc->data = data;
+	rstc->regmap = regmap;
+	rstc->reset.ops = &meson_aoclk_reset_ops;
+	rstc->reset.nr_resets = data->num_reset,
+	rstc->reset.of_node = dev->of_node;
+	ret = devm_reset_controller_register(dev, &rstc->reset);
+	if (ret) {
+		dev_err(dev, "failed to register reset controller\n");
+		return ret;
+	}
+
+	/*
+	 * Populate regmap and register all clks
+	 */
+	for (clkid = 0; clkid < data->num_clks; clkid++) {
+		data->clks[clkid]->map = regmap;
+
+		ret = devm_clk_hw_register(dev, data->hw_data->hws[clkid]);
+		if (ret)
+			return ret;
+	}
+
+	return devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get,
+		(void *) data->hw_data);
+}
diff --git a/drivers/clk/meson/meson-aoclk.h b/drivers/clk/meson/meson-aoclk.h
new file mode 100644
index 000000000000..ab2819e88922
--- /dev/null
+++ b/drivers/clk/meson/meson-aoclk.h
@@ -0,0 +1,34 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2017 BayLibre, SAS
+ * Author: Neil Armstrong <narmstrong at baylibre.com>
+ *
+ * Copyright (c) 2018 Amlogic, inc.
+ * Author: Qiufang Dai <qiufang.dai at amlogic.com>
+ * Author: Yixun Lan <yixun.lan at amlogic.com>
+ */
+
+#ifndef __MESON_AOCLK_H__
+#define __MESON_AOCLK_H__
+
+#include <linux/platform_device.h>
+#include <linux/reset-controller.h>
+#include "clk-regmap.h"
+
+struct meson_aoclk_data {
+	const unsigned int			reset_reg;
+	const int				num_reset;
+	const unsigned int			*reset;
+	int					num_clks;
+	struct clk_regmap			**clks;
+	const struct clk_hw_onecell_data	*hw_data;
+};
+
+struct meson_aoclk_reset_controller {
+	struct reset_controller_dev		reset;
+	const struct meson_aoclk_data		*data;
+	struct regmap				*regmap;
+};
+
+int meson_aoclkc_probe(struct platform_device *pdev);
+#endif
-- 
2.17.0



From yixun.lan at amlogic.com  Thu Apr 26 01:44:33 2018
From: yixun.lan at amlogic.com (Yixun Lan)
Date: Thu, 26 Apr 2018 16:44:33 +0800
Subject: [PATCH v7 3/7] dt-bindings: clock: axg-aoclkc: New binding for
 Meson-AXG SoC
In-Reply-To: <20180426084437.192394-1-yixun.lan@amlogic.com>
References: <20180426084437.192394-1-yixun.lan@amlogic.com>
Message-ID: <20180426084437.192394-4-yixun.lan@amlogic.com>

Update the dt-binding documentation to support new compatible string
for the Amlogic's Meson-AXG SoC.

Reviewed-by: Rob Herring <robh at kernel.org>
Signed-off-by: Yixun Lan <yixun.lan at amlogic.com>
---
 Documentation/devicetree/bindings/clock/amlogic,gxbb-aoclkc.txt | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/clock/amlogic,gxbb-aoclkc.txt b/Documentation/devicetree/bindings/clock/amlogic,gxbb-aoclkc.txt
index 786dc39ca904..3a880528030e 100644
--- a/Documentation/devicetree/bindings/clock/amlogic,gxbb-aoclkc.txt
+++ b/Documentation/devicetree/bindings/clock/amlogic,gxbb-aoclkc.txt
@@ -9,6 +9,7 @@ Required Properties:
 	- GXBB (S905) : "amlogic,meson-gxbb-aoclkc"
 	- GXL (S905X, S905D) : "amlogic,meson-gxl-aoclkc"
 	- GXM (S912) : "amlogic,meson-gxm-aoclkc"
+	- AXG (A113D, A113X) : "amlogic,meson-axg-aoclkc"
 	followed by the common "amlogic,meson-gx-aoclkc"
 
 - #clock-cells: should be 1.
-- 
2.17.0



From yixun.lan at amlogic.com  Thu Apr 26 01:44:34 2018
From: yixun.lan at amlogic.com (Yixun Lan)
Date: Thu, 26 Apr 2018 16:44:34 +0800
Subject: [PATCH v7 4/7] dt-bindings: clock: reset: Add AXG AO Clock and Reset
 Bindings
In-Reply-To: <20180426084437.192394-1-yixun.lan@amlogic.com>
References: <20180426084437.192394-1-yixun.lan@amlogic.com>
Message-ID: <20180426084437.192394-5-yixun.lan@amlogic.com>

Add dt-bindings headers for the Meson-AXG's AO clock and
reset controller.

Reviewed-by: Rob Herring <robh at kernel.org>
Signed-off-by: Yixun Lan <yixun.lan at amlogic.com>
---
 include/dt-bindings/clock/axg-aoclkc.h | 26 ++++++++++++++++++++++++++
 include/dt-bindings/reset/axg-aoclkc.h | 20 ++++++++++++++++++++
 2 files changed, 46 insertions(+)
 create mode 100644 include/dt-bindings/clock/axg-aoclkc.h
 create mode 100644 include/dt-bindings/reset/axg-aoclkc.h

diff --git a/include/dt-bindings/clock/axg-aoclkc.h b/include/dt-bindings/clock/axg-aoclkc.h
new file mode 100644
index 000000000000..61955016a55b
--- /dev/null
+++ b/include/dt-bindings/clock/axg-aoclkc.h
@@ -0,0 +1,26 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */
+/*
+ * Copyright (c) 2016 BayLibre, SAS
+ * Author: Neil Armstrong <narmstrong at baylibre.com>
+ *
+ * Copyright (c) 2018 Amlogic, inc.
+ * Author: Qiufang Dai <qiufang.dai at amlogic.com>
+ */
+
+#ifndef DT_BINDINGS_CLOCK_AMLOGIC_MESON_AXG_AOCLK
+#define DT_BINDINGS_CLOCK_AMLOGIC_MESON_AXG_AOCLK
+
+#define CLKID_AO_REMOTE		0
+#define CLKID_AO_I2C_MASTER	1
+#define CLKID_AO_I2C_SLAVE	2
+#define CLKID_AO_UART1		3
+#define CLKID_AO_UART2		4
+#define CLKID_AO_IR_BLASTER	5
+#define CLKID_AO_SAR_ADC	6
+#define CLKID_AO_CLK81		7
+#define CLKID_AO_SAR_ADC_SEL	8
+#define CLKID_AO_SAR_ADC_DIV	9
+#define CLKID_AO_SAR_ADC_CLK	10
+#define CLKID_AO_ALT_XTAL	11
+
+#endif
diff --git a/include/dt-bindings/reset/axg-aoclkc.h b/include/dt-bindings/reset/axg-aoclkc.h
new file mode 100644
index 000000000000..d342c0b6b2a7
--- /dev/null
+++ b/include/dt-bindings/reset/axg-aoclkc.h
@@ -0,0 +1,20 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */
+/*
+ * Copyright (c) 2016 BayLibre, SAS
+ * Author: Neil Armstrong <narmstrong at baylibre.com>
+ *
+ * Copyright (c) 2018 Amlogic, inc.
+ * Author: Qiufang Dai <qiufang.dai at amlogic.com>
+ */
+
+#ifndef DT_BINDINGS_RESET_AMLOGIC_MESON_AXG_AOCLK
+#define DT_BINDINGS_RESET_AMLOGIC_MESON_AXG_AOCLK
+
+#define RESET_AO_REMOTE		0
+#define RESET_AO_I2C_MASTER	1
+#define RESET_AO_I2C_SLAVE	2
+#define RESET_AO_UART1		3
+#define RESET_AO_UART2		4
+#define RESET_AO_IR_BLASTER	5
+
+#endif
-- 
2.17.0



From narmstrong at baylibre.com  Thu Apr 26 01:46:01 2018
From: narmstrong at baylibre.com (Neil Armstrong)
Date: Thu, 26 Apr 2018 10:46:01 +0200
Subject: [PATCH 1/7] clk: meson: clean-up meson clock configuration
In-Reply-To: <20180425163304.10852-2-jbrunet@baylibre.com>
References: <20180425163304.10852-1-jbrunet@baylibre.com>
 <20180425163304.10852-2-jbrunet@baylibre.com>
Message-ID: <d643c87a-d364-1587-100d-119f8b417f11@baylibre.com>

On 25/04/2018 18:32, Jerome Brunet wrote:
> Clean the dependencies in meson clock Kconfig.
> CLK_AMLOGIC should actually select CLK_REGMAP_MESON which it uses. Also,
> each platform should select CLK_AMLOGIC, so everything is properly turned
> on when the platform Kconfig enable each configuration flag
> 
> Signed-off-by: Jerome Brunet <jbrunet at baylibre.com>
> ---
>  drivers/clk/meson/Kconfig | 11 ++++-------
>  1 file changed, 4 insertions(+), 7 deletions(-)
> 
> diff --git a/drivers/clk/meson/Kconfig b/drivers/clk/meson/Kconfig
> index d5cbec522aec..87d69573e172 100644
> --- a/drivers/clk/meson/Kconfig
> +++ b/drivers/clk/meson/Kconfig
> @@ -1,7 +1,7 @@
>  config COMMON_CLK_AMLOGIC
>  	bool
> -	depends on OF
>  	depends on ARCH_MESON || COMPILE_TEST
> +	select COMMON_CLK_REGMAP_MESON
>  
>  config COMMON_CLK_REGMAP_MESON
>  	bool
> @@ -9,9 +9,8 @@ config COMMON_CLK_REGMAP_MESON
>  
>  config COMMON_CLK_MESON8B
>  	bool
> -	depends on COMMON_CLK_AMLOGIC
> +	select COMMON_CLK_AMLOGIC
>  	select RESET_CONTROLLER
> -	select COMMON_CLK_REGMAP_MESON
>  	help
>  	  Support for the clock controller on AmLogic S802 (Meson8),
>  	  S805 (Meson8b) and S812 (Meson8m2) devices. Say Y if you
> @@ -19,9 +18,8 @@ config COMMON_CLK_MESON8B
>  
>  config COMMON_CLK_GXBB
>  	bool
> -	depends on COMMON_CLK_AMLOGIC
> +	select COMMON_CLK_AMLOGIC
>  	select RESET_CONTROLLER
> -	select COMMON_CLK_REGMAP_MESON
>  	select MFD_SYSCON
>  	help
>  	  Support for the clock controller on AmLogic S905 devices, aka gxbb.
> @@ -29,9 +27,8 @@ config COMMON_CLK_GXBB
>  
>  config COMMON_CLK_AXG
>  	bool
> -	depends on COMMON_CLK_AMLOGIC
> +	select COMMON_CLK_AMLOGIC
>  	select RESET_CONTROLLER
> -	select COMMON_CLK_REGMAP_MESON
>  	select MFD_SYSCON
>  	help
>  	  Support for the clock controller on AmLogic A113D devices, aka axg.
> 

Acked-by: Neil Armstrong <narmstrong at baylibre.com>


From narmstrong at baylibre.com  Thu Apr 26 01:46:12 2018
From: narmstrong at baylibre.com (Neil Armstrong)
Date: Thu, 26 Apr 2018 10:46:12 +0200
Subject: [PATCH 2/7] clk: meson: add clk-phase clock driver
In-Reply-To: <20180425163304.10852-3-jbrunet@baylibre.com>
References: <20180425163304.10852-1-jbrunet@baylibre.com>
 <20180425163304.10852-3-jbrunet@baylibre.com>
Message-ID: <86b8e8f5-fb69-3249-fc1e-b4f2213284db@baylibre.com>

On 25/04/2018 18:32, Jerome Brunet wrote:
> Add a driver based meson clk-regmap to control clock phase on
> amlogic SoCs
> 
> Signed-off-by: Jerome Brunet <jbrunet at baylibre.com>
> ---
>  drivers/clk/meson/Makefile    |  1 +
>  drivers/clk/meson/clk-phase.c | 63 +++++++++++++++++++++++++++++++++++++++++++
>  drivers/clk/meson/clkc.h      |  8 ++++++
>  3 files changed, 72 insertions(+)
>  create mode 100644 drivers/clk/meson/clk-phase.c
> 
> diff --git a/drivers/clk/meson/Makefile b/drivers/clk/meson/Makefile
> index ffee82e60b7a..352fb848c406 100644
> --- a/drivers/clk/meson/Makefile
> +++ b/drivers/clk/meson/Makefile
> @@ -3,6 +3,7 @@
>  #
>  
>  obj-$(CONFIG_COMMON_CLK_AMLOGIC) += clk-pll.o clk-mpll.o clk-audio-divider.o
> +obj-$(CONFIG_COMMON_CLK_AMLOGIC) += clk-phase.o
>  obj-$(CONFIG_COMMON_CLK_MESON8B) += meson8b.o
>  obj-$(CONFIG_COMMON_CLK_GXBB)	 += gxbb.o gxbb-aoclk.o gxbb-aoclk-32k.o
>  obj-$(CONFIG_COMMON_CLK_AXG)	 += axg.o
> diff --git a/drivers/clk/meson/clk-phase.c b/drivers/clk/meson/clk-phase.c
> new file mode 100644
> index 000000000000..96e70497ef1b
> --- /dev/null
> +++ b/drivers/clk/meson/clk-phase.c
> @@ -0,0 +1,63 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +/*
> + * Copyright (c) 2018 BayLibre, SAS.
> + * Author: Jerome Brunet <jbrunet at baylibre.com>
> + */
> +
> +#include <linux/clk-provider.h>
> +#include "clkc.h"
> +
> +#define phase_step(_width) (360 / (1 << (_width)))
> +
> +static inline struct meson_clk_phase_data *
> +meson_clk_phase_data(struct clk_regmap *clk)
> +{
> +	return (struct meson_clk_phase_data *)clk->data;
> +}
> +
> +int meson_clk_degrees_from_val(unsigned int val, unsigned int width)
> +{
> +	return phase_step(width) * val;
> +}
> +EXPORT_SYMBOL_GPL(meson_clk_degrees_from_val);
> +
> +unsigned int meson_clk_degrees_to_val(int degrees, unsigned int width)
> +{
> +	unsigned int val = DIV_ROUND_CLOSEST(degrees, phase_step(width));
> +
> +	/*
> +	 * This last calculation is here for cases when degrees is rounded
> +	 * to 360, in which case val == (1 << width).
> +	 */
> +	return val % (1 << width);
> +}
> +EXPORT_SYMBOL_GPL(meson_clk_degrees_to_val);
> +
> +static int meson_clk_phase_get_phase(struct clk_hw *hw)
> +{
> +	struct clk_regmap *clk = to_clk_regmap(hw);
> +	struct meson_clk_phase_data *phase = meson_clk_phase_data(clk);
> +	unsigned int val;
> +
> +	val = meson_parm_read(clk->map, &phase->ph);
> +
> +	return meson_clk_degrees_from_val(val, phase->ph.width);
> +}
> +
> +static int meson_clk_phase_set_phase(struct clk_hw *hw, int degrees)
> +{
> +	struct clk_regmap *clk = to_clk_regmap(hw);
> +	struct meson_clk_phase_data *phase = meson_clk_phase_data(clk);
> +	unsigned int val;
> +
> +	val = meson_clk_degrees_to_val(degrees, phase->ph.width);
> +	meson_parm_write(clk->map, &phase->ph, val);
> +
> +	return 0;
> +}
> +
> +const struct clk_ops meson_clk_phase_ops = {
> +	.get_phase	= meson_clk_phase_get_phase,
> +	.set_phase	= meson_clk_phase_set_phase,
> +};
> +EXPORT_SYMBOL_GPL(meson_clk_phase_ops);
> diff --git a/drivers/clk/meson/clkc.h b/drivers/clk/meson/clkc.h
> index 8fe73c4edca8..9a17d6705e0a 100644
> --- a/drivers/clk/meson/clkc.h
> +++ b/drivers/clk/meson/clkc.h
> @@ -104,6 +104,13 @@ struct meson_clk_audio_div_data {
>  	u8 flags;
>  };
>  
> +struct meson_clk_phase_data {
> +	struct parm ph;
> +};
> +
> +int meson_clk_degrees_from_val(unsigned int val, unsigned int width);
> +unsigned int meson_clk_degrees_to_val(int degrees, unsigned int width);
> +
>  #define MESON_GATE(_name, _reg, _bit)					\
>  struct clk_regmap _name = {						\
>  	.data = &(struct clk_regmap_gate_data){				\
> @@ -127,5 +134,6 @@ extern const struct clk_ops meson_clk_mpll_ro_ops;
>  extern const struct clk_ops meson_clk_mpll_ops;
>  extern const struct clk_ops meson_clk_audio_divider_ro_ops;
>  extern const struct clk_ops meson_clk_audio_divider_ops;
> +extern const struct clk_ops meson_clk_phase_ops;
>  
>  #endif /* __CLKC_H */
> 

Acked-by: Neil Armstrong <narmstrong at baylibre.com>


From yixun.lan at amlogic.com  Thu Apr 26 01:44:35 2018
From: yixun.lan at amlogic.com (Yixun Lan)
Date: Thu, 26 Apr 2018 16:44:35 +0800
Subject: [PATCH v7 5/7] clk: meson-axg: Add AO Clock and Reset controller
 driver
In-Reply-To: <20180426084437.192394-1-yixun.lan@amlogic.com>
References: <20180426084437.192394-1-yixun.lan@amlogic.com>
Message-ID: <20180426084437.192394-6-yixun.lan@amlogic.com>

From: Qiufang Dai <qiufang.dai at amlogic.com>

Adds a Clock and Reset controller driver for the Always-On part
of the Amlogic Meson-AXG SoC.

Acked-by: Philipp Zabel <p.zabel at pengutronix.de>
Signed-off-by: Qiufang Dai <qiufang.dai at amlogic.com>
Signed-off-by: Yixun Lan <yixun.lan at amlogic.com>
---
 drivers/clk/meson/Kconfig     |   1 +
 drivers/clk/meson/Makefile    |   2 +-
 drivers/clk/meson/axg-aoclk.c | 164 ++++++++++++++++++++++++++++++++++
 drivers/clk/meson/axg-aoclk.h |  29 ++++++
 4 files changed, 195 insertions(+), 1 deletion(-)
 create mode 100644 drivers/clk/meson/axg-aoclk.c
 create mode 100644 drivers/clk/meson/axg-aoclk.h

diff --git a/drivers/clk/meson/Kconfig b/drivers/clk/meson/Kconfig
index fddc7ec7b820..815659eebea3 100644
--- a/drivers/clk/meson/Kconfig
+++ b/drivers/clk/meson/Kconfig
@@ -38,6 +38,7 @@ config COMMON_CLK_AXG
 	bool
 	depends on COMMON_CLK_AMLOGIC
 	select RESET_CONTROLLER
+	select COMMON_CLK_MESON_AO
 	select COMMON_CLK_REGMAP_MESON
 	select MFD_SYSCON
 	help
diff --git a/drivers/clk/meson/Makefile b/drivers/clk/meson/Makefile
index 0a8df284f4e7..d0d13aeb369a 100644
--- a/drivers/clk/meson/Makefile
+++ b/drivers/clk/meson/Makefile
@@ -6,5 +6,5 @@ obj-$(CONFIG_COMMON_CLK_AMLOGIC) += clk-pll.o clk-mpll.o clk-audio-divider.o
 obj-$(CONFIG_COMMON_CLK_MESON_AO) += meson-aoclk.o
 obj-$(CONFIG_COMMON_CLK_MESON8B) += meson8b.o
 obj-$(CONFIG_COMMON_CLK_GXBB)	 += gxbb.o gxbb-aoclk.o gxbb-aoclk-32k.o
-obj-$(CONFIG_COMMON_CLK_AXG)	 += axg.o
+obj-$(CONFIG_COMMON_CLK_AXG)	 += axg.o axg-aoclk.o
 obj-$(CONFIG_COMMON_CLK_REGMAP_MESON)	+= clk-regmap.o
diff --git a/drivers/clk/meson/axg-aoclk.c b/drivers/clk/meson/axg-aoclk.c
new file mode 100644
index 000000000000..29e088542387
--- /dev/null
+++ b/drivers/clk/meson/axg-aoclk.c
@@ -0,0 +1,164 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Amlogic Meson-AXG Clock Controller Driver
+ *
+ * Copyright (c) 2016 Baylibre SAS.
+ * Author: Michael Turquette <mturquette at baylibre.com>
+ *
+ * Copyright (c) 2018 Amlogic, inc.
+ * Author: Qiufang Dai <qiufang.dai at amlogic.com>
+ */
+#include <linux/clk-provider.h>
+#include <linux/platform_device.h>
+#include <linux/reset-controller.h>
+#include <linux/mfd/syscon.h>
+#include "clk-regmap.h"
+#include "meson-aoclk.h"
+#include "axg-aoclk.h"
+
+#define AXG_AO_GATE(_name, _bit)					\
+static struct clk_regmap axg_aoclk_##_name = {				\
+	.data = &(struct clk_regmap_gate_data) {			\
+		.offset = (AO_RTI_GEN_CNTL_REG0),			\
+		.bit_idx = (_bit),					\
+	},								\
+	.hw.init = &(struct clk_init_data) {				\
+		.name =  "axg_ao_" #_name,				\
+		.ops = &clk_regmap_gate_ops,				\
+		.parent_names = (const char *[]){ "clk81" },		\
+		.num_parents = 1,					\
+		.flags = CLK_IGNORE_UNUSED,				\
+	},								\
+}
+
+AXG_AO_GATE(remote, 0);
+AXG_AO_GATE(i2c_master, 1);
+AXG_AO_GATE(i2c_slave, 2);
+AXG_AO_GATE(uart1, 3);
+AXG_AO_GATE(uart2, 5);
+AXG_AO_GATE(ir_blaster, 6);
+AXG_AO_GATE(saradc, 7);
+
+static struct clk_regmap axg_aoclk_clk81 = {
+	.data = &(struct clk_regmap_mux_data) {
+		.offset = AO_RTI_PWR_CNTL_REG0,
+		.mask = 0x1,
+		.shift = 8,
+	},
+	.hw.init = &(struct clk_init_data){
+		.name = "axg_ao_clk81",
+		.ops = &clk_regmap_mux_ro_ops,
+		.parent_names = (const char *[]){ "clk81", "ao_alt_xtal"},
+		.num_parents = 2,
+	},
+};
+
+static struct clk_regmap axg_aoclk_saradc_mux = {
+	.data = &(struct clk_regmap_mux_data) {
+		.offset = AO_SAR_CLK,
+		.mask = 0x3,
+		.shift = 9,
+	},
+	.hw.init = &(struct clk_init_data){
+		.name = "axg_ao_saradc_mux",
+		.ops = &clk_regmap_mux_ops,
+		.parent_names = (const char *[]){ "xtal", "axg_ao_clk81" },
+		.num_parents = 2,
+	},
+};
+
+static struct clk_regmap axg_aoclk_saradc_div = {
+	.data = &(struct clk_regmap_div_data) {
+		.offset = AO_SAR_CLK,
+		.shift = 0,
+		.width = 8,
+	},
+	.hw.init = &(struct clk_init_data){
+		.name = "axg_ao_saradc_div",
+		.ops = &clk_regmap_divider_ops,
+		.parent_names = (const char *[]){ "axg_ao_saradc_mux" },
+		.num_parents = 1,
+		.flags = CLK_SET_RATE_PARENT,
+	},
+};
+
+static struct clk_regmap axg_aoclk_saradc_gate = {
+	.data = &(struct clk_regmap_gate_data) {
+		.offset = AO_SAR_CLK,
+		.bit_idx = 8,
+	},
+	.hw.init = &(struct clk_init_data){
+		.name = "axg_ao_saradc_gate",
+		.ops = &clk_regmap_gate_ops,
+		.parent_names = (const char *[]){ "axg_ao_saradc_div" },
+		.num_parents = 1,
+		.flags = CLK_SET_RATE_PARENT,
+	},
+};
+
+static const unsigned int axg_aoclk_reset[] = {
+	[RESET_AO_REMOTE]	= 16,
+	[RESET_AO_I2C_MASTER]	= 18,
+	[RESET_AO_I2C_SLAVE]	= 19,
+	[RESET_AO_UART1]	= 17,
+	[RESET_AO_UART2]	= 22,
+	[RESET_AO_IR_BLASTER]	= 23,
+};
+
+static struct clk_regmap *axg_aoclk_regmap[] = {
+	[CLKID_AO_REMOTE]	= &axg_aoclk_remote,
+	[CLKID_AO_I2C_MASTER]	= &axg_aoclk_i2c_master,
+	[CLKID_AO_I2C_SLAVE]	= &axg_aoclk_i2c_slave,
+	[CLKID_AO_UART1]	= &axg_aoclk_uart1,
+	[CLKID_AO_UART2]	= &axg_aoclk_uart2,
+	[CLKID_AO_IR_BLASTER]	= &axg_aoclk_ir_blaster,
+	[CLKID_AO_SAR_ADC]	= &axg_aoclk_saradc,
+	[CLKID_AO_CLK81]	= &axg_aoclk_clk81,
+	[CLKID_AO_SAR_ADC_SEL]	= &axg_aoclk_saradc_mux,
+	[CLKID_AO_SAR_ADC_DIV]	= &axg_aoclk_saradc_div,
+	[CLKID_AO_SAR_ADC_CLK]	= &axg_aoclk_saradc_gate,
+};
+
+static const struct clk_hw_onecell_data axg_aoclk_onecell_data = {
+	.hws = {
+		[CLKID_AO_REMOTE]	= &axg_aoclk_remote.hw,
+		[CLKID_AO_I2C_MASTER]	= &axg_aoclk_i2c_master.hw,
+		[CLKID_AO_I2C_SLAVE]	= &axg_aoclk_i2c_slave.hw,
+		[CLKID_AO_UART1]	= &axg_aoclk_uart1.hw,
+		[CLKID_AO_UART2]	= &axg_aoclk_uart2.hw,
+		[CLKID_AO_IR_BLASTER]	= &axg_aoclk_ir_blaster.hw,
+		[CLKID_AO_SAR_ADC]	= &axg_aoclk_saradc.hw,
+		[CLKID_AO_CLK81]	= &axg_aoclk_clk81.hw,
+		[CLKID_AO_SAR_ADC_SEL]	= &axg_aoclk_saradc_mux.hw,
+		[CLKID_AO_SAR_ADC_DIV]	= &axg_aoclk_saradc_div.hw,
+		[CLKID_AO_SAR_ADC_CLK]	= &axg_aoclk_saradc_gate.hw,
+	},
+	.num = NR_CLKS,
+};
+
+static const struct meson_aoclk_data axg_aoclkc_data = {
+	.reset_reg	= AO_RTI_GEN_CNTL_REG0,
+	.num_reset	= ARRAY_SIZE(axg_aoclk_reset),
+	.reset		= axg_aoclk_reset,
+	.num_clks	= ARRAY_SIZE(axg_aoclk_regmap),
+	.clks		= axg_aoclk_regmap,
+	.hw_data	= &axg_aoclk_onecell_data,
+};
+
+static const struct of_device_id axg_aoclkc_match_table[] = {
+	{
+		.compatible	= "amlogic,meson-axg-aoclkc",
+		.data		= &axg_aoclkc_data,
+	},
+	{ }
+};
+
+static struct platform_driver axg_aoclkc_driver = {
+	.probe		= meson_aoclkc_probe,
+	.driver		= {
+		.name	= "axg-aoclkc",
+		.of_match_table = axg_aoclkc_match_table,
+	},
+};
+
+builtin_platform_driver(axg_aoclkc_driver);
diff --git a/drivers/clk/meson/axg-aoclk.h b/drivers/clk/meson/axg-aoclk.h
new file mode 100644
index 000000000000..91384d8dd844
--- /dev/null
+++ b/drivers/clk/meson/axg-aoclk.h
@@ -0,0 +1,29 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2017 BayLibre, SAS
+ * Author: Neil Armstrong <narmstrong at baylibre.com>
+ *
+ * Copyright (c) 2018 Amlogic, inc.
+ * Author: Qiufang Dai <qiufang.dai at amlogic.com>
+ */
+
+#ifndef __AXG_AOCLKC_H
+#define __AXG_AOCLKC_H
+
+#define NR_CLKS	11
+/* AO Configuration Clock registers offsets
+ * Register offsets from the data sheet must be multiplied by 4.
+ */
+#define AO_RTI_PWR_CNTL_REG1	0x0C
+#define AO_RTI_PWR_CNTL_REG0	0x10
+#define AO_RTI_GEN_CNTL_REG0	0x40
+#define AO_OSCIN_CNTL		0x58
+#define AO_CRT_CLK_CNTL1	0x68
+#define AO_SAR_CLK		0x90
+#define AO_RTC_ALT_CLK_CNTL0	0x94
+#define AO_RTC_ALT_CLK_CNTL1	0x98
+
+#include <dt-bindings/clock/axg-aoclkc.h>
+#include <dt-bindings/reset/axg-aoclkc.h>
+
+#endif /* __AXG_AOCLKC_H */
-- 
2.17.0



From yixun.lan at amlogic.com  Thu Apr 26 01:44:36 2018
From: yixun.lan at amlogic.com (Yixun Lan)
Date: Thu, 26 Apr 2018 16:44:36 +0800
Subject: [PATCH v7 6/7] clk: meson: drop CLK_SET_RATE_PARENT flag
In-Reply-To: <20180426084437.192394-1-yixun.lan@amlogic.com>
References: <20180426084437.192394-1-yixun.lan@amlogic.com>
Message-ID: <20180426084437.192394-7-yixun.lan@amlogic.com>

The clk81 is not expected to be changed, so drop this flag.

Signed-off-by: Yixun Lan <yixun.lan at amlogic.com>
---
 drivers/clk/meson/gxbb-aoclk.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/clk/meson/gxbb-aoclk.c b/drivers/clk/meson/gxbb-aoclk.c
index 20f73e0d82a4..408e3e2fca18 100644
--- a/drivers/clk/meson/gxbb-aoclk.c
+++ b/drivers/clk/meson/gxbb-aoclk.c
@@ -69,7 +69,7 @@ static struct clk_regmap _name##_ao = {					\
 		.ops = &clk_regmap_gate_ops,				\
 		.parent_names = (const char *[]){ "clk81" },		\
 		.num_parents = 1,					\
-		.flags = (CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED),	\
+		.flags = CLK_IGNORE_UNUSED,				\
 	},								\
 }
 
-- 
2.17.0



From jbrunet at baylibre.com  Thu Apr 26 01:47:06 2018
From: jbrunet at baylibre.com (Jerome Brunet)
Date: Thu, 26 Apr 2018 10:47:06 +0200
Subject: [PATCH 2/2] net: stmmac: dwmac-meson: extend phy mode setting
In-Reply-To: <20180426160508.29380-3-yixun.lan@amlogic.com>
References: <20180426160508.29380-1-yixun.lan@amlogic.com>
 <20180426160508.29380-3-yixun.lan@amlogic.com>
Message-ID: <1524732426.4026.84.camel@baylibre.com>

On Thu, 2018-04-26 at 16:05 +0000, Yixun Lan wrote:
>   In the Meson-AXG SoC, the phy mode setting of PRG_ETH0 in the glue layer
> is extended from bit[0] to bit[2:0].
>   There is no problem if we configure it to the RGMII 1000M PHY mode,
> since the register setting is coincidentally compatible with previous one,
> but for the RMII 100M PHY mode, the configuration need to be changed to
> value - b100.
>   This patch was verified with a RTL8201F 100M ethernet PHY.
> 
> Signed-off-by: Yixun Lan <yixun.lan at amlogic.com>
> ---
>  .../ethernet/stmicro/stmmac/dwmac-meson8b.c   | 95 ++++++++++++++++---
>  1 file changed, 84 insertions(+), 11 deletions(-)
> 
> diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c
> index 7cb794094a70..e3688b6dd87c 100644
> --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c
> +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c
> @@ -18,6 +18,7 @@
>  #include <linux/io.h>
>  #include <linux/ioport.h>
>  #include <linux/module.h>
> +#include <linux/of_device.h>
>  #include <linux/of_net.h>
>  #include <linux/mfd/syscon.h>
>  #include <linux/platform_device.h>
> @@ -29,6 +30,10 @@
>  
>  #define PRG_ETH0_RGMII_MODE		BIT(0)
>  
> +#define PRG_ETH0_EXT_PHY_MODE_MASK	GENMASK(2, 0)
> +#define PRG_ETH0_EXT_RGMII_MODE		1
> +#define PRG_ETH0_EXT_RMII_MODE		4
> +
>  /* mux to choose between fclk_div2 (bit unset) and mpll2 (bit set) */
>  #define PRG_ETH0_CLK_M250_SEL_SHIFT	4
>  #define PRG_ETH0_CLK_M250_SEL_MASK	GENMASK(4, 4)
> @@ -46,10 +51,16 @@
>  #define PRG_ETH0_TX_AND_PHY_REF_CLK	BIT(12)
>  
>  #define MUX_CLK_NUM_PARENTS		2
> +struct meson8b_dwmac_data {
> +	bool ext_phy_mode;
> +};
>  
>  struct meson8b_dwmac {
>  	struct device		*dev;
>  	void __iomem		*regs;
> +
> +	const struct meson8b_dwmac_data *data;
> +
>  	phy_interface_t		phy_mode;
>  	struct clk		*rgmii_tx_clk;
>  	u32			tx_delay_ns;
> @@ -171,6 +182,46 @@ static int meson8b_init_rgmii_tx_clk(struct meson8b_dwmac *dwmac)
>  	return 0;
>  }
>  
> +static int meson8b_init_set_mode(struct meson8b_dwmac *dwmac)
> +{
> +	bool ext_phy_mode = dwmac->data->ext_phy_mode;
> +
> +	switch (dwmac->phy_mode) {
> +	case PHY_INTERFACE_MODE_RGMII:
> +	case PHY_INTERFACE_MODE_RGMII_RXID:
> +	case PHY_INTERFACE_MODE_RGMII_ID:
> +	case PHY_INTERFACE_MODE_RGMII_TXID:
> +		/* enable RGMII mode */
> +		if (ext_phy_mode)

Looks weird to have this if target at a specific SoC withing a function named
after another SoC

Couldn't you make one function per soc type, and pass that function pointer in
the match data ?

> +			meson8b_dwmac_mask_bits(dwmac, PRG_ETH0,
> +						PRG_ETH0_EXT_PHY_MODE_MASK,
> +						PRG_ETH0_EXT_RGMII_MODE);
> +		else
> +			meson8b_dwmac_mask_bits(dwmac, PRG_ETH0,
> +						PRG_ETH0_RGMII_MODE,
> +						PRG_ETH0_RGMII_MODE);
> +
> +		break;
> +	case PHY_INTERFACE_MODE_RMII:
> +		/* disable RGMII mode -> enables RMII mode */
> +		if (ext_phy_mode)
> +			meson8b_dwmac_mask_bits(dwmac, PRG_ETH0,
> +						PRG_ETH0_EXT_PHY_MODE_MASK,
> +						PRG_ETH0_EXT_RMII_MODE);
> +		else
> +			meson8b_dwmac_mask_bits(dwmac, PRG_ETH0,
> +						PRG_ETH0_RGMII_MODE, 0);
> +
> +		break;
> +	default:
> +		dev_err(dwmac->dev, "fail to set phy-mode %s\n",
> +			phy_modes(dwmac->phy_mode));
> +		return -EINVAL;
> +	}
> +
> +	return 0;
> +}
> +
>  static int meson8b_init_prg_eth(struct meson8b_dwmac *dwmac)
>  {
>  	int ret;
> @@ -188,10 +239,6 @@ static int meson8b_init_prg_eth(struct meson8b_dwmac *dwmac)
>  
>  	case PHY_INTERFACE_MODE_RGMII_ID:
>  	case PHY_INTERFACE_MODE_RGMII_TXID:
> -		/* enable RGMII mode */
> -		meson8b_dwmac_mask_bits(dwmac, PRG_ETH0, PRG_ETH0_RGMII_MODE,
> -					PRG_ETH0_RGMII_MODE);
> -
>  		/* only relevant for RMII mode -> disable in RGMII mode */
>  		meson8b_dwmac_mask_bits(dwmac, PRG_ETH0,
>  					PRG_ETH0_INVERTED_RMII_CLK, 0);
> @@ -224,10 +271,6 @@ static int meson8b_init_prg_eth(struct meson8b_dwmac *dwmac)
>  		break;
>  
>  	case PHY_INTERFACE_MODE_RMII:
> -		/* disable RGMII mode -> enables RMII mode */
> -		meson8b_dwmac_mask_bits(dwmac, PRG_ETH0, PRG_ETH0_RGMII_MODE,
> -					0);
> -
>  		/* invert internal clk_rmii_i to generate 25/2.5 tx_rx_clk */
>  		meson8b_dwmac_mask_bits(dwmac, PRG_ETH0,
>  					PRG_ETH0_INVERTED_RMII_CLK,
> @@ -274,6 +317,11 @@ static int meson8b_dwmac_probe(struct platform_device *pdev)
>  		goto err_remove_config_dt;
>  	}
>  
> +	dwmac->data = (const struct meson8b_dwmac_data *)
> +		of_device_get_match_data(&pdev->dev);
> +	if (!dwmac->data)
> +		return -EINVAL;
> +
>  	res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
>  	dwmac->regs = devm_ioremap_resource(&pdev->dev, res);
>  	if (IS_ERR(dwmac->regs)) {
> @@ -298,6 +346,10 @@ static int meson8b_dwmac_probe(struct platform_device *pdev)
>  	if (ret)
>  		goto err_remove_config_dt;
>  
> +	ret = meson8b_init_set_mode(dwmac);
> +	if (ret)
> +		goto err_remove_config_dt;
> +
>  	ret = meson8b_init_prg_eth(dwmac);
>  	if (ret)
>  		goto err_remove_config_dt;
> @@ -316,10 +368,31 @@ static int meson8b_dwmac_probe(struct platform_device *pdev)
>  	return ret;
>  }
>  
> +static const struct meson8b_dwmac_data meson8b_dwmac_data = {
> +	.ext_phy_mode = false,
> +};
> +
> +static const struct meson8b_dwmac_data meson_axg_dwmac_data = {
> +	.ext_phy_mode = true,
> +};
> +
>  static const struct of_device_id meson8b_dwmac_match[] = {
> -	{ .compatible = "amlogic,meson8b-dwmac" },
> -	{ .compatible = "amlogic,meson8m2-dwmac" },
> -	{ .compatible = "amlogic,meson-gxbb-dwmac" },
> +	{
> +		.compatible = "amlogic,meson8b-dwmac",
> +		.data = &meson8b_dwmac_data,
> +	},
> +	{
> +		.compatible = "amlogic,meson8m2-dwmac",
> +		.data = &meson8b_dwmac_data,
> +	},
> +	{
> +		.compatible = "amlogic,meson-gxbb-dwmac",
> +		.data = &meson8b_dwmac_data,
> +	},
> +	{
> +		.compatible = "amlogic,meson-axg-dwmac",
> +		.data = &meson_axg_dwmac_data,
> +	},
>  	{ }
>  };
>  MODULE_DEVICE_TABLE(of, meson8b_dwmac_match);



From yixun.lan at amlogic.com  Thu Apr 26 01:44:37 2018
From: yixun.lan at amlogic.com (Yixun Lan)
Date: Thu, 26 Apr 2018 16:44:37 +0800
Subject: [PATCH v7 7/7] clk: meson: drop CLK_IGNORE_UNUSED flag
In-Reply-To: <20180426084437.192394-1-yixun.lan@amlogic.com>
References: <20180426084437.192394-1-yixun.lan@amlogic.com>
Message-ID: <20180426084437.192394-8-yixun.lan@amlogic.com>

Rely on drivers to request the clock explicitly.

Previous the kernel will leave the clock on while
bootloader adready initilized the clock, this wasn't
optimal way, so fix it here.

Signed-off-by: Yixun Lan <yixun.lan at amlogic.com>
---
 drivers/clk/meson/axg-aoclk.c  | 1 -
 drivers/clk/meson/gxbb-aoclk.c | 1 -
 2 files changed, 2 deletions(-)

diff --git a/drivers/clk/meson/axg-aoclk.c b/drivers/clk/meson/axg-aoclk.c
index 29e088542387..ab42596a9801 100644
--- a/drivers/clk/meson/axg-aoclk.c
+++ b/drivers/clk/meson/axg-aoclk.c
@@ -27,7 +27,6 @@ static struct clk_regmap axg_aoclk_##_name = {				\
 		.ops = &clk_regmap_gate_ops,				\
 		.parent_names = (const char *[]){ "clk81" },		\
 		.num_parents = 1,					\
-		.flags = CLK_IGNORE_UNUSED,				\
 	},								\
 }
 
diff --git a/drivers/clk/meson/gxbb-aoclk.c b/drivers/clk/meson/gxbb-aoclk.c
index 408e3e2fca18..f5895730067b 100644
--- a/drivers/clk/meson/gxbb-aoclk.c
+++ b/drivers/clk/meson/gxbb-aoclk.c
@@ -69,7 +69,6 @@ static struct clk_regmap _name##_ao = {					\
 		.ops = &clk_regmap_gate_ops,				\
 		.parent_names = (const char *[]){ "clk81" },		\
 		.num_parents = 1,					\
-		.flags = CLK_IGNORE_UNUSED,				\
 	},								\
 }
 
-- 
2.17.0



From narmstrong at baylibre.com  Thu Apr 26 01:47:38 2018
From: narmstrong at baylibre.com (Neil Armstrong)
Date: Thu, 26 Apr 2018 10:47:38 +0200
Subject: [PATCH 4/7] clk: meson: add axg audio sclk divider driver
In-Reply-To: <20180425163304.10852-5-jbrunet@baylibre.com>
References: <20180425163304.10852-1-jbrunet@baylibre.com>
 <20180425163304.10852-5-jbrunet@baylibre.com>
Message-ID: <d0435ffb-1101-6f1b-b2de-1dc74f6a9543@baylibre.com>

On 25/04/2018 18:33, Jerome Brunet wrote:
> Add a driver to control the clock divider found in the sample clock
> generator of the axg audio clock controller.
> 
> The sclk divider accumulates specific features which make the generic
> divider unsuitable to control it:
> - zero based divider (div = val + 1), but zero value gates the clock,
>   so minimum divider value is 2.
> - lrclk variant may adjust the duty cycle depending the divider value
>   and the 'hi' value.
> 
> Signed-off-by: Jerome Brunet <jbrunet at baylibre.com>
> ---
>  drivers/clk/meson/Makefile     |   2 +-
>  drivers/clk/meson/clkc-audio.h |   8 ++
>  drivers/clk/meson/sclk-div.c   | 243 +++++++++++++++++++++++++++++++++++++++++
>  3 files changed, 252 insertions(+), 1 deletion(-)
>  create mode 100644 drivers/clk/meson/sclk-div.c
> 
> diff --git a/drivers/clk/meson/Makefile b/drivers/clk/meson/Makefile
> index 64bb917fe1f0..f51b4754c31b 100644
> --- a/drivers/clk/meson/Makefile
> +++ b/drivers/clk/meson/Makefile
> @@ -4,7 +4,7 @@
>  
>  obj-$(CONFIG_COMMON_CLK_AMLOGIC) += clk-pll.o clk-mpll.o clk-audio-divider.o
>  obj-$(CONFIG_COMMON_CLK_AMLOGIC) += clk-phase.o
> -obj-$(CONFIG_COMMON_CLK_AMLOGIC_AUDIO)	+= clk-triphase.o
> +obj-$(CONFIG_COMMON_CLK_AMLOGIC_AUDIO)	+= clk-triphase.o sclk-div.o
>  obj-$(CONFIG_COMMON_CLK_MESON8B) += meson8b.o
>  obj-$(CONFIG_COMMON_CLK_GXBB)	 += gxbb.o gxbb-aoclk.o gxbb-aoclk-32k.o
>  obj-$(CONFIG_COMMON_CLK_AXG)	 += axg.o
> diff --git a/drivers/clk/meson/clkc-audio.h b/drivers/clk/meson/clkc-audio.h
> index 286ff1201258..0a7c157ebf81 100644
> --- a/drivers/clk/meson/clkc-audio.h
> +++ b/drivers/clk/meson/clkc-audio.h
> @@ -15,6 +15,14 @@ struct meson_clk_triphase_data {
>  	struct parm ph2;
>  };
>  
> +struct meson_sclk_div_data {
> +	struct parm div;
> +	struct parm hi;
> +	unsigned int cached_div;
> +	struct clk_duty cached_duty;
> +};
> +
>  extern const struct clk_ops meson_clk_triphase_ops;
> +extern const struct clk_ops meson_sclk_div_ops;
>  
>  #endif /* __MESON_CLKC_AUDIO_H */
> diff --git a/drivers/clk/meson/sclk-div.c b/drivers/clk/meson/sclk-div.c
> new file mode 100644
> index 000000000000..8c0bc914a6d7
> --- /dev/null
> +++ b/drivers/clk/meson/sclk-div.c
> @@ -0,0 +1,243 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +/*
> + * Copyright (c) 2018 BayLibre, SAS.
> + * Author: Jerome Brunet <jbrunet at baylibre.com>
> + *
> + * Sample clock generator divider:
> + * This HW divider gates with value 0 but is otherwise a zero based divider:
> + *
> + * val >= 1
> + * divider = val + 1
> + *
> + * The duty cycle may also be set for the LR clock variant. The duty cycle
> + * ratio is:
> + *
> + * hi = [0 - val]
> + * duty_cycle = (1 + hi) / (1 + val)
> + */
> +
> +#include "clkc-audio.h"
> +
> +static inline struct meson_sclk_div_data *
> +meson_sclk_div_data(struct clk_regmap *clk)
> +{
> +	return (struct meson_sclk_div_data *)clk->data;
> +}
> +
> +static int sclk_div_maxval(struct meson_sclk_div_data *sclk)
> +{
> +	return (1 << sclk->div.width) - 1;
> +}
> +
> +static int sclk_div_maxdiv(struct meson_sclk_div_data *sclk)
> +{
> +	return sclk_div_maxval(sclk) + 1;
> +}
> +
> +static int sclk_div_getdiv(struct clk_hw *hw, unsigned long rate,
> +			   unsigned long prate, int maxdiv)
> +{
> +	int div = DIV_ROUND_CLOSEST_ULL((u64)prate, rate);
> +
> +	return clamp(div, 2, maxdiv);
> +}
> +
> +static int sclk_div_bestdiv(struct clk_hw *hw, unsigned long rate,
> +			    unsigned long *prate,
> +			    struct meson_sclk_div_data *sclk)
> +{
> +	struct clk_hw *parent = clk_hw_get_parent(hw);
> +	int bestdiv = 0, i;
> +	unsigned long maxdiv, now, parent_now;
> +	unsigned long best = 0, best_parent = 0;
> +
> +	if (!rate)
> +		rate = 1;
> +
> +	maxdiv = sclk_div_maxdiv(sclk);
> +
> +	if (!(clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT))
> +		return sclk_div_getdiv(hw, rate, *prate, maxdiv);
> +
> +	/*
> +	 * The maximum divider we can use without overflowing
> +	 * unsigned long in rate * i below
> +	 */
> +	maxdiv = min(ULONG_MAX / rate, maxdiv);
> +
> +	for (i = 2; i <= maxdiv; i++) {
> +		/*
> +		 * It's the most ideal case if the requested rate can be
> +		 * divided from parent clock without needing to change
> +		 * parent rate, so return the divider immediately.
> +		 */
> +		if (rate * i == *prate)
> +			return i;
> +
> +		parent_now = clk_hw_round_rate(parent, rate * i);
> +		now = DIV_ROUND_UP_ULL((u64)parent_now, i);
> +
> +		if (abs(rate - now) < abs(rate - best)) {
> +			bestdiv = i;
> +			best = now;
> +			best_parent = parent_now;
> +		}
> +	}
> +
> +	if (!bestdiv)
> +		bestdiv = sclk_div_maxdiv(sclk);
> +	else
> +		*prate = best_parent;
> +
> +	return bestdiv;
> +}
> +
> +static long sclk_div_round_rate(struct clk_hw *hw, unsigned long rate,
> +				unsigned long *prate)
> +{
> +	struct clk_regmap *clk = to_clk_regmap(hw);
> +	struct meson_sclk_div_data *sclk = meson_sclk_div_data(clk);
> +	int div;
> +
> +	div = sclk_div_bestdiv(hw, rate, prate, sclk);
> +
> +	return DIV_ROUND_UP_ULL((u64)*prate, div);
> +}
> +
> +static void sclk_apply_ratio(struct clk_regmap *clk,
> +			     struct meson_sclk_div_data *sclk)
> +{
> +	unsigned int hi = DIV_ROUND_CLOSEST(sclk->cached_div *
> +					    sclk->cached_duty.num,
> +					    sclk->cached_duty.den);
> +
> +	if (hi)
> +		hi -= 1;
> +
> +	meson_parm_write(clk->map, &sclk->hi, hi);
> +}
> +
> +static int sclk_div_set_duty_cycle(struct clk_hw *hw,
> +				   struct clk_duty *duty)
> +{
> +	struct clk_regmap *clk = to_clk_regmap(hw);
> +	struct meson_sclk_div_data *sclk = meson_sclk_div_data(clk);
> +
> +	if (MESON_PARM_APPLICABLE(&sclk->hi)) {
> +		memcpy(&sclk->cached_duty, duty, sizeof(*duty));
> +		sclk_apply_ratio(clk, sclk);
> +	}
> +
> +	return 0;
> +}
> +
> +static int sclk_div_get_duty_cycle(struct clk_hw *hw,
> +				   struct clk_duty *duty)
> +{
> +	struct clk_regmap *clk = to_clk_regmap(hw);
> +	struct meson_sclk_div_data *sclk = meson_sclk_div_data(clk);
> +	int hi;
> +
> +	if (!MESON_PARM_APPLICABLE(&sclk->hi)) {
> +		duty->num = 1;
> +		duty->den = 2;
> +		return 0;
> +	}
> +
> +	hi = meson_parm_read(clk->map, &sclk->hi);
> +	duty->num = hi + 1;
> +	duty->den = sclk->cached_div;
> +	return 0;
> +}
> +
> +static void sclk_apply_divider(struct clk_regmap *clk,
> +			       struct meson_sclk_div_data *sclk)
> +{
> +	if (MESON_PARM_APPLICABLE(&sclk->hi))
> +		sclk_apply_ratio(clk, sclk);
> +
> +	meson_parm_write(clk->map, &sclk->div, sclk->cached_div - 1);
> +}
> +
> +static int sclk_div_set_rate(struct clk_hw *hw, unsigned long rate,
> +			     unsigned long prate)
> +{
> +	struct clk_regmap *clk = to_clk_regmap(hw);
> +	struct meson_sclk_div_data *sclk = meson_sclk_div_data(clk);
> +	unsigned long maxdiv = sclk_div_maxdiv(sclk);
> +
> +	sclk->cached_div = sclk_div_getdiv(hw, rate, prate, maxdiv);
> +
> +	if (clk_hw_is_enabled(hw))
> +		sclk_apply_divider(clk, sclk);
> +
> +	return 0;
> +}
> +
> +static unsigned long sclk_div_recalc_rate(struct clk_hw *hw,
> +					  unsigned long prate)
> +{
> +	struct clk_regmap *clk = to_clk_regmap(hw);
> +	struct meson_sclk_div_data *sclk = meson_sclk_div_data(clk);
> +
> +	return DIV_ROUND_UP_ULL((u64)prate, sclk->cached_div);
> +}
> +
> +static int sclk_div_enable(struct clk_hw *hw)
> +{
> +	struct clk_regmap *clk = to_clk_regmap(hw);
> +	struct meson_sclk_div_data *sclk = meson_sclk_div_data(clk);
> +
> +	sclk_apply_divider(clk, sclk);
> +
> +	return 0;
> +}
> +
> +static void sclk_div_disable(struct clk_hw *hw)
> +{
> +	struct clk_regmap *clk = to_clk_regmap(hw);
> +	struct meson_sclk_div_data *sclk = meson_sclk_div_data(clk);
> +
> +	meson_parm_write(clk->map, &sclk->div, 0);
> +}
> +
> +static int sclk_div_is_enabled(struct clk_hw *hw)
> +{
> +	struct clk_regmap *clk = to_clk_regmap(hw);
> +	struct meson_sclk_div_data *sclk = meson_sclk_div_data(clk);
> +
> +	if (meson_parm_read(clk->map, &sclk->div))
> +		return 1;
> +
> +	return 0;
> +}
> +
> +static void sclk_div_init(struct clk_hw *hw)
> +{
> +	struct clk_regmap *clk = to_clk_regmap(hw);
> +	struct meson_sclk_div_data *sclk = meson_sclk_div_data(clk);
> +	unsigned int val;
> +
> +	val = meson_parm_read(clk->map, &sclk->div);
> +
> +	/* if the divider is initially disabled, assume max */
> +	if (!val)
> +		sclk->cached_div = sclk_div_maxdiv(sclk);
> +	else
> +		sclk->cached_div = val + 1;
> +
> +	sclk_div_get_duty_cycle(hw, &sclk->cached_duty);
> +}
> +
> +const struct clk_ops meson_sclk_div_ops = {
> +	.recalc_rate	= sclk_div_recalc_rate,
> +	.round_rate	= sclk_div_round_rate,
> +	.set_rate	= sclk_div_set_rate,
> +	.enable		= sclk_div_enable,
> +	.disable	= sclk_div_disable,
> +	.is_enabled	= sclk_div_is_enabled,
> +	.get_duty_cycle	= sclk_div_get_duty_cycle,
> +	.set_duty_cycle = sclk_div_set_duty_cycle,
> +	.init		= sclk_div_init,
> +};
> +EXPORT_SYMBOL_GPL(meson_sclk_div_ops);
> 

Acked-by: Neil Armstrong <narmstrong at baylibre.com>


From narmstrong at baylibre.com  Thu Apr 26 01:48:44 2018
From: narmstrong at baylibre.com (Neil Armstrong)
Date: Thu, 26 Apr 2018 10:48:44 +0200
Subject: [PATCH 5/7] clk: meson: axg: export audio clock controller id
 bindings
In-Reply-To: <20180425163304.10852-6-jbrunet@baylibre.com>
References: <20180425163304.10852-1-jbrunet@baylibre.com>
 <20180425163304.10852-6-jbrunet@baylibre.com>
Message-ID: <5a842562-eb68-334c-5c77-d785bd0178d0@baylibre.com>

On 25/04/2018 18:33, Jerome Brunet wrote:
> export the clock ids dt-bindings usable by the consumers of the axg
> audio clock controller
> 
> Signed-off-by: Jerome Brunet <jbrunet at baylibre.com>
> ---
>  include/dt-bindings/clock/axg-audio-clkc.h | 94 ++++++++++++++++++++++++++++++
>  1 file changed, 94 insertions(+)
>  create mode 100644 include/dt-bindings/clock/axg-audio-clkc.h
> 
> diff --git a/include/dt-bindings/clock/axg-audio-clkc.h b/include/dt-bindings/clock/axg-audio-clkc.h
> new file mode 100644
> index 000000000000..4426ae655858
> --- /dev/null
> +++ b/include/dt-bindings/clock/axg-audio-clkc.h
> @@ -0,0 +1,94 @@
> +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
> +/*
> + * Copyright (c) 2018 Baylibre SAS.
> + * Author: Jerome Brunet <jbrunet at baylibre.com>
> + */
> +
> +#ifndef __AXG_AUDIO_CLKC_BINDINGS_H
> +#define __AXG_AUDIO_CLKC_BINDINGS_H
> +
> +#define AUD_CLKID_SLV_SCLK0		9
> +#define AUD_CLKID_SLV_SCLK1		10
> +#define AUD_CLKID_SLV_SCLK2		11
> +#define AUD_CLKID_SLV_SCLK3		12
> +#define AUD_CLKID_SLV_SCLK4		13
> +#define AUD_CLKID_SLV_SCLK5		14
> +#define AUD_CLKID_SLV_SCLK6		15
> +#define AUD_CLKID_SLV_SCLK7		16
> +#define AUD_CLKID_SLV_SCLK8		17
> +#define AUD_CLKID_SLV_SCLK9		18
> +#define AUD_CLKID_SLV_LRCLK0		19
> +#define AUD_CLKID_SLV_LRCLK1		20
> +#define AUD_CLKID_SLV_LRCLK2		21
> +#define AUD_CLKID_SLV_LRCLK3		22
> +#define AUD_CLKID_SLV_LRCLK4		23
> +#define AUD_CLKID_SLV_LRCLK5		24
> +#define AUD_CLKID_SLV_LRCLK6		25
> +#define AUD_CLKID_SLV_LRCLK7		26
> +#define AUD_CLKID_SLV_LRCLK8		27
> +#define AUD_CLKID_SLV_LRCLK9		28
> +#define AUD_CLKID_DDR_ARB		29
> +#define AUD_CLKID_PDM			30
> +#define AUD_CLKID_TDMIN_A		31
> +#define AUD_CLKID_TDMIN_B		32
> +#define AUD_CLKID_TDMIN_C		33
> +#define AUD_CLKID_TDMIN_LB		34
> +#define AUD_CLKID_TDMOUT_A		35
> +#define AUD_CLKID_TDMOUT_B		36
> +#define AUD_CLKID_TDMOUT_C		37
> +#define AUD_CLKID_FRDDR_A		38
> +#define AUD_CLKID_FRDDR_B		39
> +#define AUD_CLKID_FRDDR_C		40
> +#define AUD_CLKID_TODDR_A		41
> +#define AUD_CLKID_TODDR_B		42
> +#define AUD_CLKID_TODDR_C		43
> +#define AUD_CLKID_LOOPBACK		44
> +#define AUD_CLKID_SPDIFIN		45
> +#define AUD_CLKID_SPDIFOUT		46
> +#define AUD_CLKID_RESAMPLE		47
> +#define AUD_CLKID_POWER_DETECT		48
> +#define AUD_CLKID_MST_A_MCLK		49
> +#define AUD_CLKID_MST_B_MCLK		50
> +#define AUD_CLKID_MST_C_MCLK		51
> +#define AUD_CLKID_MST_D_MCLK		52
> +#define AUD_CLKID_MST_E_MCLK		53
> +#define AUD_CLKID_MST_F_MCLK		54
> +#define AUD_CLKID_SPDIFOUT_CLK		55
> +#define AUD_CLKID_SPDIFIN_CLK		56
> +#define AUD_CLKID_PDM_DCLK		57
> +#define AUD_CLKID_PDM_SYSCLK		58
> +#define AUD_CLKID_MST_A_SCLK		79
> +#define AUD_CLKID_MST_B_SCLK		80
> +#define AUD_CLKID_MST_C_SCLK		81
> +#define AUD_CLKID_MST_D_SCLK		82
> +#define AUD_CLKID_MST_E_SCLK		83
> +#define AUD_CLKID_MST_F_SCLK		84
> +#define AUD_CLKID_MST_A_LRCLK		86
> +#define AUD_CLKID_MST_B_LRCLK		87
> +#define AUD_CLKID_MST_C_LRCLK		88
> +#define AUD_CLKID_MST_D_LRCLK		89
> +#define AUD_CLKID_MST_E_LRCLK		90
> +#define AUD_CLKID_MST_F_LRCLK		91
> +#define AUD_CLKID_TDMIN_A_SCLK_SEL	116
> +#define AUD_CLKID_TDMIN_B_SCLK_SEL	117
> +#define AUD_CLKID_TDMIN_C_SCLK_SEL	118
> +#define AUD_CLKID_TDMIN_LB_SCLK_SEL	119
> +#define AUD_CLKID_TDMOUT_A_SCLK_SEL	120
> +#define AUD_CLKID_TDMOUT_B_SCLK_SEL	121
> +#define AUD_CLKID_TDMOUT_C_SCLK_SEL	122
> +#define AUD_CLKID_TDMIN_A_SCLK		123
> +#define AUD_CLKID_TDMIN_B_SCLK		124
> +#define AUD_CLKID_TDMIN_C_SCLK		125
> +#define AUD_CLKID_TDMIN_LB_SCLK		126
> +#define AUD_CLKID_TDMOUT_A_SCLK		127
> +#define AUD_CLKID_TDMOUT_B_SCLK		128
> +#define AUD_CLKID_TDMOUT_C_SCLK		129
> +#define AUD_CLKID_TDMIN_A_LRCLK		130
> +#define AUD_CLKID_TDMIN_B_LRCLK		131
> +#define AUD_CLKID_TDMIN_C_LRCLK		132
> +#define AUD_CLKID_TDMIN_LB_LRCLK	133
> +#define AUD_CLKID_TDMOUT_A_LRCLK	134
> +#define AUD_CLKID_TDMOUT_B_LRCLK	135
> +#define AUD_CLKID_TDMOUT_C_LRCLK	136
> +
> +#endif /* __AXG_AUDIO_CLKC_BINDINGS_H */
> 

Acked-by: Neil Armstrong <narmstrong at baylibre.com>


From narmstrong at baylibre.com  Thu Apr 26 01:49:29 2018
From: narmstrong at baylibre.com (Neil Armstrong)
Date: Thu, 26 Apr 2018 10:49:29 +0200
Subject: [PATCH 7/7] clk: meson: axg: add the audio clock controller driver
In-Reply-To: <20180425163304.10852-8-jbrunet@baylibre.com>
References: <20180425163304.10852-1-jbrunet@baylibre.com>
 <20180425163304.10852-8-jbrunet@baylibre.com>
Message-ID: <82a486c6-4972-cb3d-5851-f020dfffb21e@baylibre.com>

On 25/04/2018 18:33, Jerome Brunet wrote:
> The axg audio clock controller is the clock generation unit for the
> amlogic audio subsystem of A113 based SoCs. It may be clocked by 8
> different plls provided by the primary clock controller and also by
> 10 slave bit clocks and 10 slave sample clocks which may be provided
> by external components, such as audio codecs, through the SoC pads.
> 
> It contains several muxes, dividers and gates which are fed into the
> the different devices of the audio subsystem.
> 
> Signed-off-by: Jerome Brunet <jbrunet at baylibre.com>
> ---
>  drivers/clk/meson/Kconfig     |   9 +
>  drivers/clk/meson/Makefile    |   1 +
>  drivers/clk/meson/axg-audio.c | 845 ++++++++++++++++++++++++++++++++++++++++++
>  drivers/clk/meson/axg-audio.h | 127 +++++++
>  4 files changed, 982 insertions(+)
>  create mode 100644 drivers/clk/meson/axg-audio.c
>  create mode 100644 drivers/clk/meson/axg-audio.h
> 
> diff --git a/drivers/clk/meson/Kconfig b/drivers/clk/meson/Kconfig
> index 7f7fd6fb3809..006fa1204e5b 100644
> --- a/drivers/clk/meson/Kconfig
> +++ b/drivers/clk/meson/Kconfig
> @@ -38,3 +38,12 @@ config COMMON_CLK_AXG
>  	help
>  	  Support for the clock controller on AmLogic A113D devices, aka axg.
>  	  Say Y if you want peripherals and CPU frequency scaling to work.
> +
> +config COMMON_CLK_AXG_AUDIO
> +	tristate "Meson AXG Audio Clock Controller Driver"
> +	depends on COMMON_CLK_AXG
> +	select COMMON_CLK_AMLOGIC_AUDIO
> +	select MFD_SYSCON
> +	help
> +	  Support for the audio clock controller on AmLogic A113D devices,
> +	  aka axg, Say Y if you want audio subsystem to work.
> diff --git a/drivers/clk/meson/Makefile b/drivers/clk/meson/Makefile
> index f51b4754c31b..1ab89b627586 100644
> --- a/drivers/clk/meson/Makefile
> +++ b/drivers/clk/meson/Makefile
> @@ -8,4 +8,5 @@ obj-$(CONFIG_COMMON_CLK_AMLOGIC_AUDIO)	+= clk-triphase.o sclk-div.o
>  obj-$(CONFIG_COMMON_CLK_MESON8B) += meson8b.o
>  obj-$(CONFIG_COMMON_CLK_GXBB)	 += gxbb.o gxbb-aoclk.o gxbb-aoclk-32k.o
>  obj-$(CONFIG_COMMON_CLK_AXG)	 += axg.o
> +obj-$(CONFIG_COMMON_CLK_AXG_AUDIO)	+= axg-audio.o
>  obj-$(CONFIG_COMMON_CLK_REGMAP_MESON)	+= clk-regmap.o
> diff --git a/drivers/clk/meson/axg-audio.c b/drivers/clk/meson/axg-audio.c
> new file mode 100644
> index 000000000000..830c13ccd819
> --- /dev/null
> +++ b/drivers/clk/meson/axg-audio.c
> @@ -0,0 +1,845 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +/*
> + * Copyright (c) 2018 BayLibre, SAS.
> + * Author: Jerome Brunet <jbrunet at baylibre.com>
> + */
> +
> +#include <linux/clk.h>
> +#include <linux/clk-provider.h>
> +#include <linux/init.h>
> +#include <linux/of_device.h>
> +#include <linux/module.h>
> +#include <linux/platform_device.h>
> +#include <linux/regmap.h>
> +#include <linux/reset.h>
> +#include <linux/slab.h>
> +
> +#include "clkc-audio.h"
> +#include "axg-audio.h"
> +
> +#define AXG_MST_IN_COUNT	8
> +#define AXG_SLV_SCLK_COUNT	10
> +#define AXG_SLV_LRCLK_COUNT	10
> +
> +#define AXG_AUD_GATE(_name, _reg, _bit, _pname, _iflags)		\
> +struct clk_regmap axg_##_name = {					\
> +	.data = &(struct clk_regmap_gate_data){				\
> +		.offset = (_reg),					\
> +		.bit_idx = (_bit),					\
> +	},								\
> +	.hw.init = &(struct clk_init_data) {				\
> +		.name = "axg_"#_name,					\
> +		.ops = &clk_regmap_gate_ops,				\
> +		.parent_names = (const char *[]){ _pname },		\
> +		.num_parents = 1,					\
> +		.flags = CLK_DUTY_CYCLE_PARENT | (_iflags),		\
> +	},								\
> +}
> +
> +#define AXG_AUD_MUX(_name, _reg, _mask, _shift, _dflags, _pnames, _iflags) \
> +struct clk_regmap axg_##_name = {					\
> +	.data = &(struct clk_regmap_mux_data){				\
> +		.offset = (_reg),					\
> +		.mask = (_mask),					\
> +		.shift = (_shift),					\
> +		.flags = (_dflags),					\
> +	},								\
> +	.hw.init = &(struct clk_init_data){				\
> +		.name = "axg_"#_name,					\
> +		.ops = &clk_regmap_mux_ops,				\
> +		.parent_names = (_pnames),				\
> +		.num_parents = ARRAY_SIZE(_pnames),			\
> +		.flags = CLK_DUTY_CYCLE_PARENT | (_iflags),		\
> +	},								\
> +}
> +
> +#define AXG_AUD_DIV(_name, _reg, _shift, _width, _dflags, _pname, _iflags) \
> +struct clk_regmap axg_##_name = {					\
> +	.data = &(struct clk_regmap_div_data){				\
> +		.offset = (_reg),					\
> +		.shift = (_shift),					\
> +		.width = (_width),					\
> +		.flags = (_dflags),					\
> +	},								\
> +	.hw.init = &(struct clk_init_data){				\
> +		.name = "axg_"#_name,					\
> +		.ops = &clk_regmap_divider_ops,				\
> +		.parent_names = (const char *[]) { _pname },		\
> +		.num_parents = 1,					\
> +		.flags = (_iflags),					\
> +	},								\
> +}
> +
> +#define AXG_PCLK_GATE(_name, _bit)				\
> +	AXG_AUD_GATE(_name, AUDIO_CLK_GATE_EN, _bit, "axg_audio_pclk", 0)
> +
> +/* Audio peripheral clocks */
> +static AXG_PCLK_GATE(ddr_arb,	   0);
> +static AXG_PCLK_GATE(pdm,	   1);
> +static AXG_PCLK_GATE(tdmin_a,	   2);
> +static AXG_PCLK_GATE(tdmin_b,	   3);
> +static AXG_PCLK_GATE(tdmin_c,	   4);
> +static AXG_PCLK_GATE(tdmin_lb,	   5);
> +static AXG_PCLK_GATE(tdmout_a,	   6);
> +static AXG_PCLK_GATE(tdmout_b,	   7);
> +static AXG_PCLK_GATE(tdmout_c,	   8);
> +static AXG_PCLK_GATE(frddr_a,	   9);
> +static AXG_PCLK_GATE(frddr_b,	   10);
> +static AXG_PCLK_GATE(frddr_c,	   11);
> +static AXG_PCLK_GATE(toddr_a,	   12);
> +static AXG_PCLK_GATE(toddr_b,	   13);
> +static AXG_PCLK_GATE(toddr_c,	   14);
> +static AXG_PCLK_GATE(loopback,	   15);
> +static AXG_PCLK_GATE(spdifin,	   16);
> +static AXG_PCLK_GATE(spdifout,	   17);
> +static AXG_PCLK_GATE(resample,	   18);
> +static AXG_PCLK_GATE(power_detect, 19);
> +
> +/* Audio Master Clocks */
> +static const char * const mst_mux_parent_names[] = {
> +	"axg_mst_in0", "axg_mst_in1", "axg_mst_in2", "axg_mst_in3",
> +	"axg_mst_in4", "axg_mst_in5", "axg_mst_in6", "axg_mst_in7",
> +};
> +
> +#define AXG_MST_MCLK_MUX(_name, _reg)					\
> +	AXG_AUD_MUX(_name##_sel, _reg, 0x7, 24, CLK_MUX_ROUND_CLOSEST, \
> +		    mst_mux_parent_names, CLK_SET_RATE_PARENT)
> +
> +static AXG_MST_MCLK_MUX(mst_a_mclk,   AUDIO_MCLK_A_CTRL);
> +static AXG_MST_MCLK_MUX(mst_b_mclk,   AUDIO_MCLK_B_CTRL);
> +static AXG_MST_MCLK_MUX(mst_c_mclk,   AUDIO_MCLK_C_CTRL);
> +static AXG_MST_MCLK_MUX(mst_d_mclk,   AUDIO_MCLK_D_CTRL);
> +static AXG_MST_MCLK_MUX(mst_e_mclk,   AUDIO_MCLK_E_CTRL);
> +static AXG_MST_MCLK_MUX(mst_f_mclk,   AUDIO_MCLK_F_CTRL);
> +static AXG_MST_MCLK_MUX(spdifout_clk, AUDIO_CLK_SPDIFOUT_CTRL);
> +static AXG_MST_MCLK_MUX(spdifin_clk,  AUDIO_CLK_SPDIFIN_CTRL);
> +static AXG_MST_MCLK_MUX(pdm_dclk,     AUDIO_CLK_PDMIN_CTRL0);
> +static AXG_MST_MCLK_MUX(pdm_sysclk,   AUDIO_CLK_PDMIN_CTRL1);
> +
> +#define AXG_MST_MCLK_DIV(_name, _reg)					\
> +	AXG_AUD_DIV(_name##_div, _reg, 0, 16, CLK_DIVIDER_ROUND_CLOSEST, \
> +		    "axg_"#_name"_sel", CLK_SET_RATE_PARENT)		\
> +
> +static AXG_MST_MCLK_DIV(mst_a_mclk,   AUDIO_MCLK_A_CTRL);
> +static AXG_MST_MCLK_DIV(mst_b_mclk,   AUDIO_MCLK_B_CTRL);
> +static AXG_MST_MCLK_DIV(mst_c_mclk,   AUDIO_MCLK_C_CTRL);
> +static AXG_MST_MCLK_DIV(mst_d_mclk,   AUDIO_MCLK_D_CTRL);
> +static AXG_MST_MCLK_DIV(mst_e_mclk,   AUDIO_MCLK_E_CTRL);
> +static AXG_MST_MCLK_DIV(mst_f_mclk,   AUDIO_MCLK_F_CTRL);
> +static AXG_MST_MCLK_DIV(spdifout_clk, AUDIO_CLK_SPDIFOUT_CTRL);
> +static AXG_MST_MCLK_DIV(spdifin_clk,  AUDIO_CLK_SPDIFIN_CTRL);
> +static AXG_MST_MCLK_DIV(pdm_dclk,     AUDIO_CLK_PDMIN_CTRL0);
> +static AXG_MST_MCLK_DIV(pdm_sysclk,   AUDIO_CLK_PDMIN_CTRL1);
> +
> +#define AXG_MST_MCLK_GATE(_name, _reg)					\
> +	AXG_AUD_GATE(_name, _reg, 31,  "axg_"#_name"_div",		\
> +		     CLK_SET_RATE_PARENT)
> +
> +static AXG_MST_MCLK_GATE(mst_a_mclk,   AUDIO_MCLK_A_CTRL);
> +static AXG_MST_MCLK_GATE(mst_b_mclk,   AUDIO_MCLK_B_CTRL);
> +static AXG_MST_MCLK_GATE(mst_c_mclk,   AUDIO_MCLK_C_CTRL);
> +static AXG_MST_MCLK_GATE(mst_d_mclk,   AUDIO_MCLK_D_CTRL);
> +static AXG_MST_MCLK_GATE(mst_e_mclk,   AUDIO_MCLK_E_CTRL);
> +static AXG_MST_MCLK_GATE(mst_f_mclk,   AUDIO_MCLK_F_CTRL);
> +static AXG_MST_MCLK_GATE(spdifout_clk, AUDIO_CLK_SPDIFOUT_CTRL);
> +static AXG_MST_MCLK_GATE(spdifin_clk,  AUDIO_CLK_SPDIFIN_CTRL);
> +static AXG_MST_MCLK_GATE(pdm_dclk,     AUDIO_CLK_PDMIN_CTRL0);
> +static AXG_MST_MCLK_GATE(pdm_sysclk,   AUDIO_CLK_PDMIN_CTRL1);
> +
> +/* Sample Clocks */
> +#define AXG_MST_SCLK_PRE_EN(_name, _reg)			\
> +	AXG_AUD_GATE(mst_##_name##_sclk_pre_en, _reg, 31,	\
> +		     "axg_mst_"#_name"_mclk", 0)
> +
> +static AXG_MST_SCLK_PRE_EN(a, AUDIO_MST_A_SCLK_CTRL0);
> +static AXG_MST_SCLK_PRE_EN(b, AUDIO_MST_B_SCLK_CTRL0);
> +static AXG_MST_SCLK_PRE_EN(c, AUDIO_MST_C_SCLK_CTRL0);
> +static AXG_MST_SCLK_PRE_EN(d, AUDIO_MST_D_SCLK_CTRL0);
> +static AXG_MST_SCLK_PRE_EN(e, AUDIO_MST_E_SCLK_CTRL0);
> +static AXG_MST_SCLK_PRE_EN(f, AUDIO_MST_F_SCLK_CTRL0);
> +
> +#define AXG_AUD_SCLK_DIV(_name, _reg, _div_shift, _div_width,		\
> +			 _hi_shift, _hi_width, _pname, _iflags)		\
> +struct clk_regmap axg_##_name = {					\
> +	.data = &(struct meson_sclk_div_data) {				\
> +		.div = {						\
> +			.reg_off = (_reg),				\
> +			.shift   = (_div_shift),			\
> +			.width   = (_div_width),			\
> +		},							\
> +		.hi = {							\
> +			.reg_off = (_reg),				\
> +			.shift   = (_hi_shift),				\
> +			.width   = (_hi_width),				\
> +		},							\
> +	},								\
> +	.hw.init = &(struct clk_init_data) {				\
> +		.name = "axg_"#_name,					\
> +		.ops = &meson_sclk_div_ops,				\
> +		.parent_names = (const char *[]) { _pname },		\
> +		.num_parents = 1,					\
> +		.flags = (_iflags),					\
> +	},								\
> +}
> +
> +#define AXG_MST_SCLK_DIV(_name, _reg)					\
> +	AXG_AUD_SCLK_DIV(mst_##_name##_sclk_div, _reg, 20, 10, 0, 0,	\
> +			 "axg_mst_"#_name"_sclk_pre_en",		\
> +			 CLK_SET_RATE_PARENT)
> +
> +static AXG_MST_SCLK_DIV(a, AUDIO_MST_A_SCLK_CTRL0);
> +static AXG_MST_SCLK_DIV(b, AUDIO_MST_B_SCLK_CTRL0);
> +static AXG_MST_SCLK_DIV(c, AUDIO_MST_C_SCLK_CTRL0);
> +static AXG_MST_SCLK_DIV(d, AUDIO_MST_D_SCLK_CTRL0);
> +static AXG_MST_SCLK_DIV(e, AUDIO_MST_E_SCLK_CTRL0);
> +static AXG_MST_SCLK_DIV(f, AUDIO_MST_F_SCLK_CTRL0);
> +
> +#define AXG_MST_SCLK_POST_EN(_name, _reg)				\
> +	AXG_AUD_GATE(mst_##_name##_sclk_post_en, _reg, 30,		\
> +		     "axg_mst_"#_name"_sclk_div", CLK_SET_RATE_PARENT)
> +
> +static AXG_MST_SCLK_POST_EN(a, AUDIO_MST_A_SCLK_CTRL0);
> +static AXG_MST_SCLK_POST_EN(b, AUDIO_MST_B_SCLK_CTRL0);
> +static AXG_MST_SCLK_POST_EN(c, AUDIO_MST_C_SCLK_CTRL0);
> +static AXG_MST_SCLK_POST_EN(d, AUDIO_MST_D_SCLK_CTRL0);
> +static AXG_MST_SCLK_POST_EN(e, AUDIO_MST_E_SCLK_CTRL0);
> +static AXG_MST_SCLK_POST_EN(f, AUDIO_MST_F_SCLK_CTRL0);
> +
> +#define AXG_AUD_TRIPHASE(_name, _reg, _width, _shift0, _shift1, _shift2, \
> +			 _pname, _iflags)				\
> +struct clk_regmap axg_##_name = {					\
> +	.data = &(struct meson_clk_triphase_data) {			\
> +		.ph0 = {						\
> +			.reg_off = (_reg),				\
> +			.shift   = (_shift0),				\
> +			.width   = (_width),				\
> +		},							\
> +		.ph1 = {						\
> +			.reg_off = (_reg),				\
> +			.shift   = (_shift1),				\
> +			.width   = (_width),				\
> +		},							\
> +		.ph2 = {						\
> +			.reg_off = (_reg),				\
> +			.shift   = (_shift2),				\
> +			.width   = (_width),				\
> +		},							\
> +	},								\
> +	.hw.init = &(struct clk_init_data) {				\
> +		.name = "axg_"#_name,					\
> +		.ops = &meson_clk_triphase_ops,				\
> +		.parent_names = (const char *[]) { _pname },		\
> +		.num_parents = 1,					\
> +		.flags = CLK_DUTY_CYCLE_PARENT | (_iflags),		\
> +	},								\
> +}
> +
> +#define AXG_MST_SCLK(_name, _reg)					\
> +	AXG_AUD_TRIPHASE(mst_##_name##_sclk, _reg, 1, 0, 2, 4,		\
> +			 "axg_mst_"#_name"_sclk_post_en", CLK_SET_RATE_PARENT)
> +
> +static AXG_MST_SCLK(a, AUDIO_MST_A_SCLK_CTRL1);
> +static AXG_MST_SCLK(b, AUDIO_MST_B_SCLK_CTRL1);
> +static AXG_MST_SCLK(c, AUDIO_MST_C_SCLK_CTRL1);
> +static AXG_MST_SCLK(d, AUDIO_MST_D_SCLK_CTRL1);
> +static AXG_MST_SCLK(e, AUDIO_MST_E_SCLK_CTRL1);
> +static AXG_MST_SCLK(f, AUDIO_MST_F_SCLK_CTRL1);
> +
> +#define AXG_MST_LRCLK_DIV(_name, _reg)					\
> +	AXG_AUD_SCLK_DIV(mst_##_name##_lrclk_div, _reg, 0, 10, 10, 10,	\
> +		    "axg_mst_"#_name"_sclk_post_en", 0)			\
> +
> +static AXG_MST_LRCLK_DIV(a, AUDIO_MST_A_SCLK_CTRL0);
> +static AXG_MST_LRCLK_DIV(b, AUDIO_MST_B_SCLK_CTRL0);
> +static AXG_MST_LRCLK_DIV(c, AUDIO_MST_C_SCLK_CTRL0);
> +static AXG_MST_LRCLK_DIV(d, AUDIO_MST_D_SCLK_CTRL0);
> +static AXG_MST_LRCLK_DIV(e, AUDIO_MST_E_SCLK_CTRL0);
> +static AXG_MST_LRCLK_DIV(f, AUDIO_MST_F_SCLK_CTRL0);
> +
> +#define AXG_MST_LRCLK(_name, _reg)					\
> +	AXG_AUD_TRIPHASE(mst_##_name##_lrclk, _reg, 1, 1, 3, 5,		\
> +			 "axg_mst_"#_name"_lrclk_div", CLK_SET_RATE_PARENT)
> +
> +static AXG_MST_LRCLK(a, AUDIO_MST_A_SCLK_CTRL1);
> +static AXG_MST_LRCLK(b, AUDIO_MST_B_SCLK_CTRL1);
> +static AXG_MST_LRCLK(c, AUDIO_MST_C_SCLK_CTRL1);
> +static AXG_MST_LRCLK(d, AUDIO_MST_D_SCLK_CTRL1);
> +static AXG_MST_LRCLK(e, AUDIO_MST_E_SCLK_CTRL1);
> +static AXG_MST_LRCLK(f, AUDIO_MST_F_SCLK_CTRL1);
> +
> +static const char * const tdm_sclk_parent_names[] = {
> +	"axg_mst_a_sclk", "axg_mst_b_sclk", "axg_mst_c_sclk",
> +	"axg_mst_d_sclk", "axg_mst_e_sclk", "axg_mst_f_sclk",
> +	"axg_slv_sclk0", "axg_slv_sclk1", "axg_slv_sclk2",
> +	"axg_slv_sclk3", "axg_slv_sclk4", "axg_slv_sclk5",
> +	"axg_slv_sclk6", "axg_slv_sclk7", "axg_slv_sclk8",
> +	"axg_slv_sclk9"
> +};
> +
> +#define AXG_TDM_SCLK_MUX(_name, _reg)				\
> +	AXG_AUD_MUX(tdm##_name##_sclk_sel, _reg, 0xf, 24,	\
> +		    CLK_MUX_ROUND_CLOSEST,			\
> +		    tdm_sclk_parent_names, 0)
> +
> +static AXG_TDM_SCLK_MUX(in_a,  AUDIO_CLK_TDMIN_A_CTRL);
> +static AXG_TDM_SCLK_MUX(in_b,  AUDIO_CLK_TDMIN_B_CTRL);
> +static AXG_TDM_SCLK_MUX(in_c,  AUDIO_CLK_TDMIN_C_CTRL);
> +static AXG_TDM_SCLK_MUX(in_lb, AUDIO_CLK_TDMIN_LB_CTRL);
> +static AXG_TDM_SCLK_MUX(out_a, AUDIO_CLK_TDMOUT_A_CTRL);
> +static AXG_TDM_SCLK_MUX(out_b, AUDIO_CLK_TDMOUT_B_CTRL);
> +static AXG_TDM_SCLK_MUX(out_c, AUDIO_CLK_TDMOUT_C_CTRL);
> +
> +#define AXG_TDM_SCLK_PRE_EN(_name, _reg)				\
> +	AXG_AUD_GATE(tdm##_name##_sclk_pre_en, _reg, 31,		\
> +		     "axg_tdm"#_name"_sclk_sel", CLK_SET_RATE_PARENT)
> +
> +static AXG_TDM_SCLK_PRE_EN(in_a,  AUDIO_CLK_TDMIN_A_CTRL);
> +static AXG_TDM_SCLK_PRE_EN(in_b,  AUDIO_CLK_TDMIN_B_CTRL);
> +static AXG_TDM_SCLK_PRE_EN(in_c,  AUDIO_CLK_TDMIN_C_CTRL);
> +static AXG_TDM_SCLK_PRE_EN(in_lb, AUDIO_CLK_TDMIN_LB_CTRL);
> +static AXG_TDM_SCLK_PRE_EN(out_a, AUDIO_CLK_TDMOUT_A_CTRL);
> +static AXG_TDM_SCLK_PRE_EN(out_b, AUDIO_CLK_TDMOUT_B_CTRL);
> +static AXG_TDM_SCLK_PRE_EN(out_c, AUDIO_CLK_TDMOUT_C_CTRL);
> +
> +#define AXG_TDM_SCLK_POST_EN(_name, _reg)				\
> +	AXG_AUD_GATE(tdm##_name##_sclk_post_en, _reg, 30,		\
> +		     "axg_tdm"#_name"_sclk_pre_en", CLK_SET_RATE_PARENT)
> +
> +static AXG_TDM_SCLK_POST_EN(in_a,  AUDIO_CLK_TDMIN_A_CTRL);
> +static AXG_TDM_SCLK_POST_EN(in_b,  AUDIO_CLK_TDMIN_B_CTRL);
> +static AXG_TDM_SCLK_POST_EN(in_c,  AUDIO_CLK_TDMIN_C_CTRL);
> +static AXG_TDM_SCLK_POST_EN(in_lb, AUDIO_CLK_TDMIN_LB_CTRL);
> +static AXG_TDM_SCLK_POST_EN(out_a, AUDIO_CLK_TDMOUT_A_CTRL);
> +static AXG_TDM_SCLK_POST_EN(out_b, AUDIO_CLK_TDMOUT_B_CTRL);
> +static AXG_TDM_SCLK_POST_EN(out_c, AUDIO_CLK_TDMOUT_C_CTRL);
> +
> +#define AXG_TDM_SCLK(_name, _reg)					\
> +	struct clk_regmap axg_tdm##_name##_sclk = {			\
> +	.data = &(struct meson_clk_phase_data) {			\
> +		.ph = {							\
> +			.reg_off = (_reg),				\
> +			.shift   = 29,					\
> +			.width   = 1,					\
> +		},							\
> +	},								\
> +	.hw.init = &(struct clk_init_data) {				\
> +		.name = "axg_tdm"#_name"_sclk",				\
> +		.ops = &meson_clk_phase_ops,				\
> +		.parent_names = (const char *[])			\
> +		{ "axg_tdm"#_name"_sclk_post_en" },			\
> +		.num_parents = 1,					\
> +		.flags = CLK_DUTY_CYCLE_PARENT | CLK_SET_RATE_PARENT,	\
> +	},								\
> +}
> +
> +static AXG_TDM_SCLK(in_a,  AUDIO_CLK_TDMIN_A_CTRL);
> +static AXG_TDM_SCLK(in_b,  AUDIO_CLK_TDMIN_B_CTRL);
> +static AXG_TDM_SCLK(in_c,  AUDIO_CLK_TDMIN_C_CTRL);
> +static AXG_TDM_SCLK(in_lb, AUDIO_CLK_TDMIN_LB_CTRL);
> +static AXG_TDM_SCLK(out_a, AUDIO_CLK_TDMOUT_A_CTRL);
> +static AXG_TDM_SCLK(out_b, AUDIO_CLK_TDMOUT_B_CTRL);
> +static AXG_TDM_SCLK(out_c, AUDIO_CLK_TDMOUT_C_CTRL);
> +
> +static const char * const tdm_lrclk_parent_names[] = {
> +	"axg_mst_a_lrclk", "axg_mst_b_lrclk", "axg_mst_c_lrclk",
> +	"axg_mst_d_lrclk", "axg_mst_e_lrclk", "axg_mst_f_lrclk",
> +	"axg_slv_lrclk0", "axg_slv_lrclk1", "axg_slv_lrclk2",
> +	"axg_slv_lrclk3", "axg_slv_lrclk4", "axg_slv_lrclk5",
> +	"axg_slv_lrclk6", "axg_slv_lrclk7", "axg_slv_lrclk8",
> +	"axg_slv_lrclk9"
> +};
> +
> +#define AXG_TDM_LRLCK(_name, _reg)		       \
> +	AXG_AUD_MUX(tdm##_name##_lrclk, _reg, 0xf, 20, \
> +		    CLK_MUX_ROUND_CLOSEST,	       \
> +		    tdm_lrclk_parent_names, 0)
> +
> +static AXG_TDM_LRLCK(in_a,  AUDIO_CLK_TDMIN_A_CTRL);
> +static AXG_TDM_LRLCK(in_b,  AUDIO_CLK_TDMIN_B_CTRL);
> +static AXG_TDM_LRLCK(in_c,  AUDIO_CLK_TDMIN_C_CTRL);
> +static AXG_TDM_LRLCK(in_lb, AUDIO_CLK_TDMIN_LB_CTRL);
> +static AXG_TDM_LRLCK(out_a, AUDIO_CLK_TDMOUT_A_CTRL);
> +static AXG_TDM_LRLCK(out_b, AUDIO_CLK_TDMOUT_B_CTRL);
> +static AXG_TDM_LRLCK(out_c, AUDIO_CLK_TDMOUT_C_CTRL);
> +
> +/*
> + * Array of all clocks provided by this provider
> + * The input clocks of the controller will be populated at runtime
> + */
> +static struct clk_hw_onecell_data axg_audio_hw_onecell_data = {
> +	.hws = {
> +		[AUD_CLKID_DDR_ARB]		= &axg_ddr_arb.hw,
> +		[AUD_CLKID_PDM]			= &axg_pdm.hw,
> +		[AUD_CLKID_TDMIN_A]		= &axg_tdmin_a.hw,
> +		[AUD_CLKID_TDMIN_B]		= &axg_tdmin_b.hw,
> +		[AUD_CLKID_TDMIN_C]		= &axg_tdmin_c.hw,
> +		[AUD_CLKID_TDMIN_LB]		= &axg_tdmin_lb.hw,
> +		[AUD_CLKID_TDMOUT_A]		= &axg_tdmout_a.hw,
> +		[AUD_CLKID_TDMOUT_B]		= &axg_tdmout_b.hw,
> +		[AUD_CLKID_TDMOUT_C]		= &axg_tdmout_c.hw,
> +		[AUD_CLKID_FRDDR_A]		= &axg_frddr_a.hw,
> +		[AUD_CLKID_FRDDR_B]		= &axg_frddr_b.hw,
> +		[AUD_CLKID_FRDDR_C]		= &axg_frddr_c.hw,
> +		[AUD_CLKID_TODDR_A]		= &axg_toddr_a.hw,
> +		[AUD_CLKID_TODDR_B]		= &axg_toddr_b.hw,
> +		[AUD_CLKID_TODDR_C]		= &axg_toddr_c.hw,
> +		[AUD_CLKID_LOOPBACK]		= &axg_loopback.hw,
> +		[AUD_CLKID_SPDIFIN]		= &axg_spdifin.hw,
> +		[AUD_CLKID_SPDIFOUT]		= &axg_spdifout.hw,
> +		[AUD_CLKID_RESAMPLE]		= &axg_resample.hw,
> +		[AUD_CLKID_POWER_DETECT]	= &axg_power_detect.hw,
> +		[AUD_CLKID_MST_A_MCLK_SEL]	= &axg_mst_a_mclk_sel.hw,
> +		[AUD_CLKID_MST_B_MCLK_SEL]	= &axg_mst_b_mclk_sel.hw,
> +		[AUD_CLKID_MST_C_MCLK_SEL]	= &axg_mst_c_mclk_sel.hw,
> +		[AUD_CLKID_MST_D_MCLK_SEL]	= &axg_mst_d_mclk_sel.hw,
> +		[AUD_CLKID_MST_E_MCLK_SEL]	= &axg_mst_e_mclk_sel.hw,
> +		[AUD_CLKID_MST_F_MCLK_SEL]	= &axg_mst_f_mclk_sel.hw,
> +		[AUD_CLKID_MST_A_MCLK_DIV]	= &axg_mst_a_mclk_div.hw,
> +		[AUD_CLKID_MST_B_MCLK_DIV]	= &axg_mst_b_mclk_div.hw,
> +		[AUD_CLKID_MST_C_MCLK_DIV]	= &axg_mst_c_mclk_div.hw,
> +		[AUD_CLKID_MST_D_MCLK_DIV]	= &axg_mst_d_mclk_div.hw,
> +		[AUD_CLKID_MST_E_MCLK_DIV]	= &axg_mst_e_mclk_div.hw,
> +		[AUD_CLKID_MST_F_MCLK_DIV]	= &axg_mst_f_mclk_div.hw,
> +		[AUD_CLKID_MST_A_MCLK]		= &axg_mst_a_mclk.hw,
> +		[AUD_CLKID_MST_B_MCLK]		= &axg_mst_b_mclk.hw,
> +		[AUD_CLKID_MST_C_MCLK]		= &axg_mst_c_mclk.hw,
> +		[AUD_CLKID_MST_D_MCLK]		= &axg_mst_d_mclk.hw,
> +		[AUD_CLKID_MST_E_MCLK]		= &axg_mst_e_mclk.hw,
> +		[AUD_CLKID_MST_F_MCLK]		= &axg_mst_f_mclk.hw,
> +		[AUD_CLKID_SPDIFOUT_CLK_SEL]	= &axg_spdifout_clk_sel.hw,
> +		[AUD_CLKID_SPDIFOUT_CLK_DIV]	= &axg_spdifout_clk_div.hw,
> +		[AUD_CLKID_SPDIFOUT_CLK]	= &axg_spdifout_clk.hw,
> +		[AUD_CLKID_SPDIFIN_CLK_SEL]	= &axg_spdifin_clk_sel.hw,
> +		[AUD_CLKID_SPDIFIN_CLK_DIV]	= &axg_spdifin_clk_div.hw,
> +		[AUD_CLKID_SPDIFIN_CLK]		= &axg_spdifin_clk.hw,
> +		[AUD_CLKID_PDM_DCLK_SEL]	= &axg_pdm_dclk_sel.hw,
> +		[AUD_CLKID_PDM_DCLK_DIV]	= &axg_pdm_dclk_div.hw,
> +		[AUD_CLKID_PDM_DCLK]		= &axg_pdm_dclk.hw,
> +		[AUD_CLKID_PDM_SYSCLK_SEL]	= &axg_pdm_sysclk_sel.hw,
> +		[AUD_CLKID_PDM_SYSCLK_DIV]	= &axg_pdm_sysclk_div.hw,
> +		[AUD_CLKID_PDM_SYSCLK]		= &axg_pdm_sysclk.hw,
> +		[AUD_CLKID_MST_A_SCLK_PRE_EN]	= &axg_mst_a_sclk_pre_en.hw,
> +		[AUD_CLKID_MST_B_SCLK_PRE_EN]	= &axg_mst_b_sclk_pre_en.hw,
> +		[AUD_CLKID_MST_C_SCLK_PRE_EN]	= &axg_mst_c_sclk_pre_en.hw,
> +		[AUD_CLKID_MST_D_SCLK_PRE_EN]	= &axg_mst_d_sclk_pre_en.hw,
> +		[AUD_CLKID_MST_E_SCLK_PRE_EN]	= &axg_mst_e_sclk_pre_en.hw,
> +		[AUD_CLKID_MST_F_SCLK_PRE_EN]	= &axg_mst_f_sclk_pre_en.hw,
> +		[AUD_CLKID_MST_A_SCLK_DIV]	= &axg_mst_a_sclk_div.hw,
> +		[AUD_CLKID_MST_B_SCLK_DIV]	= &axg_mst_b_sclk_div.hw,
> +		[AUD_CLKID_MST_C_SCLK_DIV]	= &axg_mst_c_sclk_div.hw,
> +		[AUD_CLKID_MST_D_SCLK_DIV]	= &axg_mst_d_sclk_div.hw,
> +		[AUD_CLKID_MST_E_SCLK_DIV]	= &axg_mst_e_sclk_div.hw,
> +		[AUD_CLKID_MST_F_SCLK_DIV]	= &axg_mst_f_sclk_div.hw,
> +		[AUD_CLKID_MST_A_SCLK_POST_EN]	= &axg_mst_a_sclk_post_en.hw,
> +		[AUD_CLKID_MST_B_SCLK_POST_EN]	= &axg_mst_b_sclk_post_en.hw,
> +		[AUD_CLKID_MST_C_SCLK_POST_EN]	= &axg_mst_c_sclk_post_en.hw,
> +		[AUD_CLKID_MST_D_SCLK_POST_EN]	= &axg_mst_d_sclk_post_en.hw,
> +		[AUD_CLKID_MST_E_SCLK_POST_EN]	= &axg_mst_e_sclk_post_en.hw,
> +		[AUD_CLKID_MST_F_SCLK_POST_EN]	= &axg_mst_f_sclk_post_en.hw,
> +		[AUD_CLKID_MST_A_SCLK]		= &axg_mst_a_sclk.hw,
> +		[AUD_CLKID_MST_B_SCLK]		= &axg_mst_b_sclk.hw,
> +		[AUD_CLKID_MST_C_SCLK]		= &axg_mst_c_sclk.hw,
> +		[AUD_CLKID_MST_D_SCLK]		= &axg_mst_d_sclk.hw,
> +		[AUD_CLKID_MST_E_SCLK]		= &axg_mst_e_sclk.hw,
> +		[AUD_CLKID_MST_F_SCLK]		= &axg_mst_f_sclk.hw,
> +		[AUD_CLKID_MST_A_LRCLK_DIV]	= &axg_mst_a_lrclk_div.hw,
> +		[AUD_CLKID_MST_B_LRCLK_DIV]	= &axg_mst_b_lrclk_div.hw,
> +		[AUD_CLKID_MST_C_LRCLK_DIV]	= &axg_mst_c_lrclk_div.hw,
> +		[AUD_CLKID_MST_D_LRCLK_DIV]	= &axg_mst_d_lrclk_div.hw,
> +		[AUD_CLKID_MST_E_LRCLK_DIV]	= &axg_mst_e_lrclk_div.hw,
> +		[AUD_CLKID_MST_F_LRCLK_DIV]	= &axg_mst_f_lrclk_div.hw,
> +		[AUD_CLKID_MST_A_LRCLK]		= &axg_mst_a_lrclk.hw,
> +		[AUD_CLKID_MST_B_LRCLK]		= &axg_mst_b_lrclk.hw,
> +		[AUD_CLKID_MST_C_LRCLK]		= &axg_mst_c_lrclk.hw,
> +		[AUD_CLKID_MST_D_LRCLK]		= &axg_mst_d_lrclk.hw,
> +		[AUD_CLKID_MST_E_LRCLK]		= &axg_mst_e_lrclk.hw,
> +		[AUD_CLKID_MST_F_LRCLK]		= &axg_mst_f_lrclk.hw,
> +		[AUD_CLKID_TDMIN_A_SCLK_SEL]	= &axg_tdmin_a_sclk_sel.hw,
> +		[AUD_CLKID_TDMIN_B_SCLK_SEL]	= &axg_tdmin_b_sclk_sel.hw,
> +		[AUD_CLKID_TDMIN_C_SCLK_SEL]	= &axg_tdmin_c_sclk_sel.hw,
> +		[AUD_CLKID_TDMIN_LB_SCLK_SEL]	= &axg_tdmin_lb_sclk_sel.hw,
> +		[AUD_CLKID_TDMOUT_A_SCLK_SEL]	= &axg_tdmout_a_sclk_sel.hw,
> +		[AUD_CLKID_TDMOUT_B_SCLK_SEL]	= &axg_tdmout_b_sclk_sel.hw,
> +		[AUD_CLKID_TDMOUT_C_SCLK_SEL]	= &axg_tdmout_c_sclk_sel.hw,
> +		[AUD_CLKID_TDMIN_A_SCLK_PRE_EN]	= &axg_tdmin_a_sclk_pre_en.hw,
> +		[AUD_CLKID_TDMIN_B_SCLK_PRE_EN]	= &axg_tdmin_b_sclk_pre_en.hw,
> +		[AUD_CLKID_TDMIN_C_SCLK_PRE_EN]	= &axg_tdmin_c_sclk_pre_en.hw,
> +		[AUD_CLKID_TDMIN_LB_SCLK_PRE_EN] = &axg_tdmin_lb_sclk_pre_en.hw,
> +		[AUD_CLKID_TDMOUT_A_SCLK_PRE_EN] = &axg_tdmout_a_sclk_pre_en.hw,
> +		[AUD_CLKID_TDMOUT_B_SCLK_PRE_EN] = &axg_tdmout_b_sclk_pre_en.hw,
> +		[AUD_CLKID_TDMOUT_C_SCLK_PRE_EN] = &axg_tdmout_c_sclk_pre_en.hw,
> +		[AUD_CLKID_TDMIN_A_SCLK_POST_EN] = &axg_tdmin_a_sclk_post_en.hw,
> +		[AUD_CLKID_TDMIN_B_SCLK_POST_EN] = &axg_tdmin_b_sclk_post_en.hw,
> +		[AUD_CLKID_TDMIN_C_SCLK_POST_EN] = &axg_tdmin_c_sclk_post_en.hw,
> +		[AUD_CLKID_TDMIN_LB_SCLK_POST_EN] = &axg_tdmin_lb_sclk_post_en.hw,
> +		[AUD_CLKID_TDMOUT_A_SCLK_POST_EN] = &axg_tdmout_a_sclk_post_en.hw,
> +		[AUD_CLKID_TDMOUT_B_SCLK_POST_EN] = &axg_tdmout_b_sclk_post_en.hw,
> +		[AUD_CLKID_TDMOUT_C_SCLK_POST_EN] = &axg_tdmout_c_sclk_post_en.hw,
> +		[AUD_CLKID_TDMIN_A_SCLK]	= &axg_tdmin_a_sclk.hw,
> +		[AUD_CLKID_TDMIN_B_SCLK]	= &axg_tdmin_b_sclk.hw,
> +		[AUD_CLKID_TDMIN_C_SCLK]	= &axg_tdmin_c_sclk.hw,
> +		[AUD_CLKID_TDMIN_LB_SCLK]	= &axg_tdmin_lb_sclk.hw,
> +		[AUD_CLKID_TDMOUT_A_SCLK]	= &axg_tdmout_a_sclk.hw,
> +		[AUD_CLKID_TDMOUT_B_SCLK]	= &axg_tdmout_b_sclk.hw,
> +		[AUD_CLKID_TDMOUT_C_SCLK]	= &axg_tdmout_c_sclk.hw,
> +		[AUD_CLKID_TDMIN_A_LRCLK]	= &axg_tdmin_a_lrclk.hw,
> +		[AUD_CLKID_TDMIN_B_LRCLK]	= &axg_tdmin_b_lrclk.hw,
> +		[AUD_CLKID_TDMIN_C_LRCLK]	= &axg_tdmin_c_lrclk.hw,
> +		[AUD_CLKID_TDMIN_LB_LRCLK]	= &axg_tdmin_lb_lrclk.hw,
> +		[AUD_CLKID_TDMOUT_A_LRCLK]	= &axg_tdmout_a_lrclk.hw,
> +		[AUD_CLKID_TDMOUT_B_LRCLK]	= &axg_tdmout_b_lrclk.hw,
> +		[AUD_CLKID_TDMOUT_C_LRCLK]	= &axg_tdmout_c_lrclk.hw,
> +		[NR_CLKS] = NULL,
> +	},
> +	.num = NR_CLKS,
> +};
> +
> +/* Convenience table to populate regmap in .probe() */
> +static struct clk_regmap *const axg_audio_clk_regmaps[] = {
> +	&axg_ddr_arb,
> +	&axg_pdm,
> +	&axg_tdmin_a,
> +	&axg_tdmin_b,
> +	&axg_tdmin_c,
> +	&axg_tdmin_lb,
> +	&axg_tdmout_a,
> +	&axg_tdmout_b,
> +	&axg_tdmout_c,
> +	&axg_frddr_a,
> +	&axg_frddr_b,
> +	&axg_frddr_c,
> +	&axg_toddr_a,
> +	&axg_toddr_b,
> +	&axg_toddr_c,
> +	&axg_loopback,
> +	&axg_spdifin,
> +	&axg_spdifout,
> +	&axg_resample,
> +	&axg_power_detect,
> +	&axg_mst_a_mclk_sel,
> +	&axg_mst_b_mclk_sel,
> +	&axg_mst_c_mclk_sel,
> +	&axg_mst_d_mclk_sel,
> +	&axg_mst_e_mclk_sel,
> +	&axg_mst_f_mclk_sel,
> +	&axg_mst_a_mclk_div,
> +	&axg_mst_b_mclk_div,
> +	&axg_mst_c_mclk_div,
> +	&axg_mst_d_mclk_div,
> +	&axg_mst_e_mclk_div,
> +	&axg_mst_f_mclk_div,
> +	&axg_mst_a_mclk,
> +	&axg_mst_b_mclk,
> +	&axg_mst_c_mclk,
> +	&axg_mst_d_mclk,
> +	&axg_mst_e_mclk,
> +	&axg_mst_f_mclk,
> +	&axg_spdifout_clk_sel,
> +	&axg_spdifout_clk_div,
> +	&axg_spdifout_clk,
> +	&axg_spdifin_clk_sel,
> +	&axg_spdifin_clk_div,
> +	&axg_spdifin_clk,
> +	&axg_pdm_dclk_sel,
> +	&axg_pdm_dclk_div,
> +	&axg_pdm_dclk,
> +	&axg_pdm_sysclk_sel,
> +	&axg_pdm_sysclk_div,
> +	&axg_pdm_sysclk,
> +	&axg_mst_a_sclk_pre_en,
> +	&axg_mst_b_sclk_pre_en,
> +	&axg_mst_c_sclk_pre_en,
> +	&axg_mst_d_sclk_pre_en,
> +	&axg_mst_e_sclk_pre_en,
> +	&axg_mst_f_sclk_pre_en,
> +	&axg_mst_a_sclk_div,
> +	&axg_mst_b_sclk_div,
> +	&axg_mst_c_sclk_div,
> +	&axg_mst_d_sclk_div,
> +	&axg_mst_e_sclk_div,
> +	&axg_mst_f_sclk_div,
> +	&axg_mst_a_sclk_post_en,
> +	&axg_mst_b_sclk_post_en,
> +	&axg_mst_c_sclk_post_en,
> +	&axg_mst_d_sclk_post_en,
> +	&axg_mst_e_sclk_post_en,
> +	&axg_mst_f_sclk_post_en,
> +	&axg_mst_a_sclk,
> +	&axg_mst_b_sclk,
> +	&axg_mst_c_sclk,
> +	&axg_mst_d_sclk,
> +	&axg_mst_e_sclk,
> +	&axg_mst_f_sclk,
> +	&axg_mst_a_lrclk_div,
> +	&axg_mst_b_lrclk_div,
> +	&axg_mst_c_lrclk_div,
> +	&axg_mst_d_lrclk_div,
> +	&axg_mst_e_lrclk_div,
> +	&axg_mst_f_lrclk_div,
> +	&axg_mst_a_lrclk,
> +	&axg_mst_b_lrclk,
> +	&axg_mst_c_lrclk,
> +	&axg_mst_d_lrclk,
> +	&axg_mst_e_lrclk,
> +	&axg_mst_f_lrclk,
> +	&axg_tdmin_a_sclk_sel,
> +	&axg_tdmin_b_sclk_sel,
> +	&axg_tdmin_c_sclk_sel,
> +	&axg_tdmin_lb_sclk_sel,
> +	&axg_tdmout_a_sclk_sel,
> +	&axg_tdmout_b_sclk_sel,
> +	&axg_tdmout_c_sclk_sel,
> +	&axg_tdmin_a_sclk_pre_en,
> +	&axg_tdmin_b_sclk_pre_en,
> +	&axg_tdmin_c_sclk_pre_en,
> +	&axg_tdmin_lb_sclk_pre_en,
> +	&axg_tdmout_a_sclk_pre_en,
> +	&axg_tdmout_b_sclk_pre_en,
> +	&axg_tdmout_c_sclk_pre_en,
> +	&axg_tdmin_a_sclk_post_en,
> +	&axg_tdmin_b_sclk_post_en,
> +	&axg_tdmin_c_sclk_post_en,
> +	&axg_tdmin_lb_sclk_post_en,
> +	&axg_tdmout_a_sclk_post_en,
> +	&axg_tdmout_b_sclk_post_en,
> +	&axg_tdmout_c_sclk_post_en,
> +	&axg_tdmin_a_sclk,
> +	&axg_tdmin_b_sclk,
> +	&axg_tdmin_c_sclk,
> +	&axg_tdmin_lb_sclk,
> +	&axg_tdmout_a_sclk,
> +	&axg_tdmout_b_sclk,
> +	&axg_tdmout_c_sclk,
> +	&axg_tdmin_a_lrclk,
> +	&axg_tdmin_b_lrclk,
> +	&axg_tdmin_c_lrclk,
> +	&axg_tdmin_lb_lrclk,
> +	&axg_tdmout_a_lrclk,
> +	&axg_tdmout_b_lrclk,
> +	&axg_tdmout_c_lrclk,
> +};
> +
> +static struct clk *devm_clk_get_enable(struct device *dev, char *id)
> +{
> +	struct clk *clk;
> +	int ret;
> +
> +	clk = devm_clk_get(dev, id);
> +	if (IS_ERR(clk)) {
> +		if (PTR_ERR(clk) != -EPROBE_DEFER)
> +			dev_err(dev, "failed to get %s", id);
> +		return clk;
> +	}
> +
> +	ret = clk_prepare_enable(clk);
> +	if (ret) {
> +		dev_err(dev, "failed to enable %s", id);
> +		return ERR_PTR(ret);
> +	}
> +
> +	ret = devm_add_action_or_reset(dev,
> +				       (void(*)(void *))clk_disable_unprepare,
> +				       clk);
> +	if (ret) {
> +		dev_err(dev, "failed to add reset action on %s", id);
> +		return ERR_PTR(ret);
> +	}
> +
> +	return clk;
> +}
> +
> +static const struct clk_ops axg_clk_no_ops = {};
> +
> +static struct clk_hw *axg_clk_hw_register_bypass(struct device *dev,
> +						 const char *name,
> +						 const char *parent_name)
> +{
> +	struct clk_hw *hw;
> +	struct clk_init_data init;
> +	char *clk_name;
> +	int ret;
> +
> +	hw = devm_kzalloc(dev, sizeof(*hw), GFP_KERNEL);
> +	if (!hw)
> +		return ERR_PTR(-ENOMEM);
> +
> +	clk_name = kasprintf(GFP_KERNEL, "axg_%s", name);
> +	if (!clk_name)
> +		return ERR_PTR(-ENOMEM);
> +
> +	init.name = clk_name;
> +	init.ops = &axg_clk_no_ops;
> +	init.flags = 0;
> +	init.parent_names = parent_name ? &parent_name : NULL;
> +	init.num_parents = parent_name ? 1 : 0;
> +	hw->init = &init;
> +
> +	ret = devm_clk_hw_register(dev, hw);
> +	kfree(clk_name);
> +
> +	return ret ? ERR_PTR(ret) : hw;
> +}
> +
> +static int axg_register_clk_hw_input(struct device *dev,
> +				     const char *name,
> +				     unsigned int clkid)
> +{
> +	struct clk *parent_clk = devm_clk_get(dev, name);
> +	struct clk_hw *hw = NULL;
> +
> +	if (IS_ERR(parent_clk)) {
> +		int err = PTR_ERR(parent_clk);
> +
> +		/* It is ok if an input clock is missing */
> +		if (err == -ENOENT) {
> +			dev_dbg(dev, "%s not provided", name);
> +		} else {
> +			if (err != -EPROBE_DEFER)
> +				dev_err(dev, "failed to get %s clock", name);
> +			return err;
> +		}
> +	} else {
> +		hw = axg_clk_hw_register_bypass(dev, name,
> +						__clk_get_name(parent_clk));
> +	}
> +
> +	if (IS_ERR(hw)) {
> +		dev_err(dev, "failed to register %s clock", name);
> +		return PTR_ERR(hw);
> +	}
> +
> +	axg_audio_hw_onecell_data.hws[clkid] = hw;
> +	return 0;
> +}
> +
> +static int axg_register_clk_hw_inputs(struct device *dev,
> +				      const char *basename,
> +				      unsigned int count,
> +				      unsigned int clkid)
> +{
> +	char *name;
> +	int i, ret;
> +
> +	for (i = 0; i < count; i++) {
> +		name = kasprintf(GFP_KERNEL, "%s%d", basename, i);
> +		if (!name)
> +			return -ENOMEM;
> +
> +		ret = axg_register_clk_hw_input(dev, name, clkid + i);
> +		kfree(name);
> +		if (ret)
> +			return ret;
> +	}
> +
> +	return 0;
> +}
> +
> +static const struct regmap_config axg_audio_regmap_cfg = {
> +	.reg_bits	= 32,
> +	.val_bits	= 32,
> +	.reg_stride	= 4,
> +	.max_register	= AUDIO_CLK_PDMIN_CTRL1,
> +};
> +
> +static int axg_audio_clkc_probe(struct platform_device *pdev)
> +{
> +	struct device *dev = &pdev->dev;
> +	struct regmap *map;
> +	struct resource *res;
> +	void __iomem *regs;
> +	struct clk *clk;
> +	struct clk_hw *hw;
> +	int ret, i;
> +
> +	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> +	regs = devm_ioremap_resource(dev, res);
> +	if (IS_ERR(regs))
> +		return PTR_ERR(regs);
> +
> +	map = devm_regmap_init_mmio(dev, regs, &axg_audio_regmap_cfg);
> +	if (IS_ERR(map)) {
> +		dev_err(dev, "failed to init regmap: %ld\n", PTR_ERR(map));
> +		return PTR_ERR(map);
> +	}
> +
> +	/* Get the mandatory peripheral clock */
> +	clk = devm_clk_get_enable(dev, "pclk");
> +	if (IS_ERR(clk))
> +		return PTR_ERR(clk);
> +
> +	ret = device_reset(dev);
> +	if (ret) {
> +		dev_err(dev, "failed to reset device\n");
> +		return ret;
> +	}
> +
> +	/* Register the peripheral input clock */
> +	hw = axg_clk_hw_register_bypass(dev, "audio_pclk",
> +					__clk_get_name(clk));
> +	if (IS_ERR(hw))
> +		return PTR_ERR(hw);
> +
> +	axg_audio_hw_onecell_data.hws[AUD_CLKID_PCLK] = hw;
> +
> +	/* Register optional input master clocks */
> +	ret = axg_register_clk_hw_inputs(dev, "mst_in",
> +					 AXG_MST_IN_COUNT,
> +					 AUD_CLKID_MST0);
> +	if (ret)
> +		return ret;
> +
> +	/* Register optional input slave sclks */
> +	ret = axg_register_clk_hw_inputs(dev, "slv_sclk",
> +					 AXG_SLV_SCLK_COUNT,
> +					 AUD_CLKID_SLV_SCLK0);
> +	if (ret)
> +		return ret;
> +
> +	/* Register optional input slave lrclks */
> +	ret = axg_register_clk_hw_inputs(dev, "slv_lrclk",
> +					 AXG_SLV_LRCLK_COUNT,
> +					 AUD_CLKID_SLV_LRCLK0);
> +	if (ret)
> +		return ret;
> +
> +	/* Populate regmap for the regmap backed clocks */
> +	for (i = 0; i < ARRAY_SIZE(axg_audio_clk_regmaps); i++)
> +		axg_audio_clk_regmaps[i]->map = map;
> +
> +	/* Take care to skip the registered input clocks */
> +	for (i = AUD_CLKID_DDR_ARB; i < axg_audio_hw_onecell_data.num; i++) {
> +		hw = axg_audio_hw_onecell_data.hws[i];
> +		/* array might be sparse */
> +		if (!hw)
> +			continue;
> +
> +		ret = devm_clk_hw_register(dev, hw);
> +		if (ret) {
> +			dev_err(dev, "failed to register clock %s\n",
> +				hw->init->name);
> +			return ret;
> +		}
> +	}
> +
> +	return devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get,
> +					   &axg_audio_hw_onecell_data);
> +}
> +
> +static const struct of_device_id clkc_match_table[] = {
> +	{ .compatible = "amlogic,axg-audio-clkc" },
> +	{}
> +};
> +MODULE_DEVICE_TABLE(of, clkc_match_table);
> +
> +static struct platform_driver axg_audio_driver = {
> +	.probe		= axg_audio_clkc_probe,
> +	.driver		= {
> +		.name	= "axg-audio-clkc",
> +		.of_match_table = clkc_match_table,
> +	},
> +};
> +module_platform_driver(axg_audio_driver);
> +
> +MODULE_DESCRIPTION("Amlogic A113x Audio Clock driver");
> +MODULE_AUTHOR("Jerome Brunet <jbrunet at baylibre.com>");
> +MODULE_LICENSE("GPL v2");
> diff --git a/drivers/clk/meson/axg-audio.h b/drivers/clk/meson/axg-audio.h
> new file mode 100644
> index 000000000000..e7a0efd12429
> --- /dev/null
> +++ b/drivers/clk/meson/axg-audio.h
> @@ -0,0 +1,127 @@
> +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
> +/*
> + * Copyright (c) 2018 BayLibre, SAS.
> + * Author: Jerome Brunet <jbrunet at baylibre.com>
> + */
> +
> +#ifndef __AXG_AUDIO_CLKC_H
> +#define __AXG_AUDIO_CLKC_H
> +
> +/*
> + * Audio Clock  register offsets
> + *
> + * Register offsets from the datasheet must be multiplied by 4 before
> + * to get the right offset
> + */
> +#define AUDIO_CLK_GATE_EN	0x000
> +#define AUDIO_MCLK_A_CTRL	0x004
> +#define AUDIO_MCLK_B_CTRL	0x008
> +#define AUDIO_MCLK_C_CTRL	0x00C
> +#define AUDIO_MCLK_D_CTRL	0x010
> +#define AUDIO_MCLK_E_CTRL	0x014
> +#define AUDIO_MCLK_F_CTRL	0x018
> +#define AUDIO_MST_A_SCLK_CTRL0	0x040
> +#define AUDIO_MST_A_SCLK_CTRL1	0x044
> +#define AUDIO_MST_B_SCLK_CTRL0	0x048
> +#define AUDIO_MST_B_SCLK_CTRL1	0x04C
> +#define AUDIO_MST_C_SCLK_CTRL0	0x050
> +#define AUDIO_MST_C_SCLK_CTRL1	0x054
> +#define AUDIO_MST_D_SCLK_CTRL0	0x058
> +#define AUDIO_MST_D_SCLK_CTRL1	0x05C
> +#define AUDIO_MST_E_SCLK_CTRL0	0x060
> +#define AUDIO_MST_E_SCLK_CTRL1	0x064
> +#define AUDIO_MST_F_SCLK_CTRL0	0x068
> +#define AUDIO_MST_F_SCLK_CTRL1	0x06C
> +#define AUDIO_CLK_TDMIN_A_CTRL	0x080
> +#define AUDIO_CLK_TDMIN_B_CTRL	0x084
> +#define AUDIO_CLK_TDMIN_C_CTRL	0x088
> +#define AUDIO_CLK_TDMIN_LB_CTRL 0x08C
> +#define AUDIO_CLK_TDMOUT_A_CTRL 0x090
> +#define AUDIO_CLK_TDMOUT_B_CTRL 0x094
> +#define AUDIO_CLK_TDMOUT_C_CTRL 0x098
> +#define AUDIO_CLK_SPDIFIN_CTRL	0x09C
> +#define AUDIO_CLK_SPDIFOUT_CTRL 0x0A0
> +#define AUDIO_CLK_RESAMPLE_CTRL 0x0A4
> +#define AUDIO_CLK_LOCKER_CTRL	0x0A8
> +#define AUDIO_CLK_PDMIN_CTRL0	0x0AC
> +#define AUDIO_CLK_PDMIN_CTRL1	0x0B0
> +
> +/*
> + * CLKID index values
> + * These indices are entirely contrived and do not map onto the hardware.
> + */
> +
> +#define AUD_CLKID_PCLK			0
> +#define AUD_CLKID_MST0			1
> +#define AUD_CLKID_MST1			2
> +#define AUD_CLKID_MST2			3
> +#define AUD_CLKID_MST3			4
> +#define AUD_CLKID_MST4			5
> +#define AUD_CLKID_MST5			6
> +#define AUD_CLKID_MST6			7
> +#define AUD_CLKID_MST7			8
> +#define AUD_CLKID_MST_A_MCLK_SEL	59
> +#define AUD_CLKID_MST_B_MCLK_SEL	60
> +#define AUD_CLKID_MST_C_MCLK_SEL	61
> +#define AUD_CLKID_MST_D_MCLK_SEL	62
> +#define AUD_CLKID_MST_E_MCLK_SEL	63
> +#define AUD_CLKID_MST_F_MCLK_SEL	64
> +#define AUD_CLKID_MST_A_MCLK_DIV	65
> +#define AUD_CLKID_MST_B_MCLK_DIV	66
> +#define AUD_CLKID_MST_C_MCLK_DIV	67
> +#define AUD_CLKID_MST_D_MCLK_DIV	68
> +#define AUD_CLKID_MST_E_MCLK_DIV	69
> +#define AUD_CLKID_MST_F_MCLK_DIV	70
> +#define AUD_CLKID_SPDIFOUT_CLK_SEL	71
> +#define AUD_CLKID_SPDIFOUT_CLK_DIV	72
> +#define AUD_CLKID_SPDIFIN_CLK_SEL	73
> +#define AUD_CLKID_SPDIFIN_CLK_DIV	74
> +#define AUD_CLKID_PDM_DCLK_SEL		75
> +#define AUD_CLKID_PDM_DCLK_DIV		76
> +#define AUD_CLKID_PDM_SYSCLK_SEL	77
> +#define AUD_CLKID_PDM_SYSCLK_DIV	78
> +#define AUD_CLKID_MST_A_SCLK_PRE_EN	92
> +#define AUD_CLKID_MST_B_SCLK_PRE_EN	93
> +#define AUD_CLKID_MST_C_SCLK_PRE_EN	94
> +#define AUD_CLKID_MST_D_SCLK_PRE_EN	95
> +#define AUD_CLKID_MST_E_SCLK_PRE_EN	96
> +#define AUD_CLKID_MST_F_SCLK_PRE_EN	97
> +#define AUD_CLKID_MST_A_SCLK_DIV	98
> +#define AUD_CLKID_MST_B_SCLK_DIV	99
> +#define AUD_CLKID_MST_C_SCLK_DIV	100
> +#define AUD_CLKID_MST_D_SCLK_DIV	101
> +#define AUD_CLKID_MST_E_SCLK_DIV	102
> +#define AUD_CLKID_MST_F_SCLK_DIV	103
> +#define AUD_CLKID_MST_A_SCLK_POST_EN	104
> +#define AUD_CLKID_MST_B_SCLK_POST_EN	105
> +#define AUD_CLKID_MST_C_SCLK_POST_EN	106
> +#define AUD_CLKID_MST_D_SCLK_POST_EN	107
> +#define AUD_CLKID_MST_E_SCLK_POST_EN	108
> +#define AUD_CLKID_MST_F_SCLK_POST_EN	109
> +#define AUD_CLKID_MST_A_LRCLK_DIV	110
> +#define AUD_CLKID_MST_B_LRCLK_DIV	111
> +#define AUD_CLKID_MST_C_LRCLK_DIV	112
> +#define AUD_CLKID_MST_D_LRCLK_DIV	113
> +#define AUD_CLKID_MST_E_LRCLK_DIV	114
> +#define AUD_CLKID_MST_F_LRCLK_DIV	115
> +#define AUD_CLKID_TDMIN_A_SCLK_PRE_EN	137
> +#define AUD_CLKID_TDMIN_B_SCLK_PRE_EN	138
> +#define AUD_CLKID_TDMIN_C_SCLK_PRE_EN	139
> +#define AUD_CLKID_TDMIN_LB_SCLK_PRE_EN	140
> +#define AUD_CLKID_TDMOUT_A_SCLK_PRE_EN	141
> +#define AUD_CLKID_TDMOUT_B_SCLK_PRE_EN	142
> +#define AUD_CLKID_TDMOUT_C_SCLK_PRE_EN	143
> +#define AUD_CLKID_TDMIN_A_SCLK_POST_EN	144
> +#define AUD_CLKID_TDMIN_B_SCLK_POST_EN	145
> +#define AUD_CLKID_TDMIN_C_SCLK_POST_EN	146
> +#define AUD_CLKID_TDMIN_LB_SCLK_POST_EN	147
> +#define AUD_CLKID_TDMOUT_A_SCLK_POST_EN	148
> +#define AUD_CLKID_TDMOUT_B_SCLK_POST_EN	149
> +#define AUD_CLKID_TDMOUT_C_SCLK_POST_EN	150
> +
> +/* include the CLKIDs which are part of the DT bindings */
> +#include <dt-bindings/clock/axg-audio-clkc.h>
> +
> +#define NR_CLKS	151
> +
> +#endif /*__AXG_AUDIO_CLKC_H */
> 

Acked-by: Neil Armstrong <narmstrong at baylibre.com>


From narmstrong at baylibre.com  Thu Apr 26 01:50:59 2018
From: narmstrong at baylibre.com (Neil Armstrong)
Date: Thu, 26 Apr 2018 10:50:59 +0200
Subject: [PATCH 3/7] clk: meson: add triple phase clock driver
In-Reply-To: <bc770c22-f0b9-ed1f-bba7-631b9cd42436@baylibre.com>
References: <20180425163304.10852-1-jbrunet@baylibre.com>
 <20180425163304.10852-4-jbrunet@baylibre.com>
 <bc770c22-f0b9-ed1f-bba7-631b9cd42436@baylibre.com>
Message-ID: <1696abba-abc2-ebbb-0d57-9fe252411b4a@baylibre.com>

On 26/04/2018 10:47, Neil Armstrong wrote:
> On 25/04/2018 18:33, Jerome Brunet wrote:
>> Add a driver to control the output of the sample clock generator found
>> in the axg audio clock controller.
>>
>> The goal of this driver is to coherently control the phase provided to
>> the different element using the sample clock generator. This simplify
>> the usage of the sample clock generator a lot, without comprising the
>> ability of the SoC.
>>
>> Signed-off-by: Jerome Brunet <jbrunet at baylibre.com>
>> ---
>>  drivers/clk/meson/Kconfig        |  5 +++
>>  drivers/clk/meson/Makefile       |  1 +
>>  drivers/clk/meson/clk-triphase.c | 68 ++++++++++++++++++++++++++++++++++++++++
>>  drivers/clk/meson/clkc-audio.h   | 20 ++++++++++++
>>  4 files changed, 94 insertions(+)
>>  create mode 100644 drivers/clk/meson/clk-triphase.c
>>  create mode 100644 drivers/clk/meson/clkc-audio.h
>>
>> diff --git a/drivers/clk/meson/Kconfig b/drivers/clk/meson/Kconfig
>> index 87d69573e172..7f7fd6fb3809 100644
>> --- a/drivers/clk/meson/Kconfig
>> +++ b/drivers/clk/meson/Kconfig
>> @@ -3,6 +3,11 @@ config COMMON_CLK_AMLOGIC
>>  	depends on ARCH_MESON || COMPILE_TEST
>>  	select COMMON_CLK_REGMAP_MESON
>>  
>> +config COMMON_CLK_AMLOGIC_AUDIO
>> +	bool
>> +	depends on ARCH_MESON || COMPILE_TEST
>> +	select COMMON_CLK_AMLOGIC
>> +
>>  config COMMON_CLK_REGMAP_MESON
>>  	bool
>>  	select REGMAP
>> diff --git a/drivers/clk/meson/Makefile b/drivers/clk/meson/Makefile
>> index 352fb848c406..64bb917fe1f0 100644
>> --- a/drivers/clk/meson/Makefile
>> +++ b/drivers/clk/meson/Makefile
>> @@ -4,6 +4,7 @@
>>  
>>  obj-$(CONFIG_COMMON_CLK_AMLOGIC) += clk-pll.o clk-mpll.o clk-audio-divider.o
>>  obj-$(CONFIG_COMMON_CLK_AMLOGIC) += clk-phase.o
>> +obj-$(CONFIG_COMMON_CLK_AMLOGIC_AUDIO)	+= clk-triphase.o
>>  obj-$(CONFIG_COMMON_CLK_MESON8B) += meson8b.o
>>  obj-$(CONFIG_COMMON_CLK_GXBB)	 += gxbb.o gxbb-aoclk.o gxbb-aoclk-32k.o
>>  obj-$(CONFIG_COMMON_CLK_AXG)	 += axg.o
>> diff --git a/drivers/clk/meson/clk-triphase.c b/drivers/clk/meson/clk-triphase.c
>> new file mode 100644
>> index 000000000000..9508c03c73c1
>> --- /dev/null
>> +++ b/drivers/clk/meson/clk-triphase.c
>> @@ -0,0 +1,68 @@
>> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
>> +/*
>> + * Copyright (c) 2018 BayLibre, SAS.
>> + * Author: Jerome Brunet <jbrunet at baylibre.com>
>> + */
>> +
>> +#include <linux/clk-provider.h>
>> +#include "clkc-audio.h"
>> +
>> +/*
>> + * This is a special clock for the audio controller.
>> + * The phase of mst_sclk clock output can be controlled independently
>> + * for the outside world (ph0), the tdmout (ph1) and tdmin (ph2).
>> + * Controlling these 3 phases as just one makes things simpler and
>> + * give the same clock view to all the element on the i2s bus.
>> + * If necessary, we can still control the phase in the tdm block
>> + * which makes these independent control redundant.
>> + */
>> +static inline struct meson_clk_triphase_data *
>> +meson_clk_triphase_data(struct clk_regmap *clk)
>> +{
>> +	return (struct meson_clk_triphase_data *)clk->data;
>> +}
>> +
>> +static void meson_clk_triphase_sync(struct clk_hw *hw)
>> +{
>> +	struct clk_regmap *clk = to_clk_regmap(hw);
>> +	struct meson_clk_triphase_data *tph = meson_clk_triphase_data(clk);
>> +	unsigned int val;
>> +
>> +	/* Get phase 0 and sync it to phase 1 and 2 */
>> +	val = meson_parm_read(clk->map, &tph->ph0);
>> +	meson_parm_write(clk->map, &tph->ph1, val);
>> +	meson_parm_write(clk->map, &tph->ph2, val);
>> +}
>> +
>> +static int meson_clk_triphase_get_phase(struct clk_hw *hw)
>> +{
>> +	struct clk_regmap *clk = to_clk_regmap(hw);
>> +	struct meson_clk_triphase_data *tph = meson_clk_triphase_data(clk);
>> +	unsigned int val;
>> +
>> +	/* Phase are in sync, reading phase 0 is enough */
>> +	val = meson_parm_read(clk->map, &tph->ph0);
>> +
>> +	return meson_clk_degrees_from_val(val, tph->ph0.width);
>> +}
>> +
>> +static int meson_clk_triphase_set_phase(struct clk_hw *hw, int degrees)
>> +{
>> +	struct clk_regmap *clk = to_clk_regmap(hw);
>> +	struct meson_clk_triphase_data *tph = meson_clk_triphase_data(clk);
>> +	unsigned int val;
>> +
>> +	val = meson_clk_degrees_to_val(degrees, tph->ph0.width);
>> +	meson_parm_write(clk->map, &tph->ph0, val);
>> +	meson_parm_write(clk->map, &tph->ph1, val);
>> +	meson_parm_write(clk->map, &tph->ph2, val);
>> +
>> +	return 0;
>> +}
>> +
>> +const struct clk_ops meson_clk_triphase_ops = {
>> +	.init		= meson_clk_triphase_sync,
>> +	.get_phase	= meson_clk_triphase_get_phase,
>> +	.set_phase	= meson_clk_triphase_set_phase,
>> +};
>> +EXPORT_SYMBOL_GPL(meson_clk_triphase_ops);
>> diff --git a/drivers/clk/meson/clkc-audio.h b/drivers/clk/meson/clkc-audio.h
>> new file mode 100644
>> index 000000000000..286ff1201258
>> --- /dev/null
>> +++ b/drivers/clk/meson/clkc-audio.h
>> @@ -0,0 +1,20 @@
>> +/* SPDX-License-Identifier: GPL-2.0 */
> 
> // SPDX-License-Identifier: GPL-2.0
> 
> Checkpatch should have warned about this !

My bad, I wasn't totally aware there is an exception in headers...

> 
>> +/*
>> + * Copyright (c) 2018 BayLibre, SAS.
>> + * Author: Jerome Brunet <jbrunet at baylibre.com>
>> + */
>> +
>> +#ifndef __MESON_CLKC_AUDIO_H
>> +#define __MESON_CLKC_AUDIO_H
>> +
>> +#include "clkc.h"
>> +
>> +struct meson_clk_triphase_data {
>> +	struct parm ph0;
>> +	struct parm ph1;
>> +	struct parm ph2;
>> +};
>> +
>> +extern const struct clk_ops meson_clk_triphase_ops;
>> +
>> +#endif /* __MESON_CLKC_AUDIO_H */
>>
> 
> Apart that :
> 
> Acked-by: Neil Armstrong <narmstrong at baylibre.com>
> 



From p.zabel at pengutronix.de  Thu Apr 26 01:59:29 2018
From: p.zabel at pengutronix.de (Philipp Zabel)
Date: Thu, 26 Apr 2018 10:59:29 +0200
Subject: [PATCH v7 5/7] clk: meson-axg: Add AO Clock and Reset
 controller driver
In-Reply-To: <20180426084437.192394-6-yixun.lan@amlogic.com>
References: <20180426084437.192394-1-yixun.lan@amlogic.com>
 <20180426084437.192394-6-yixun.lan@amlogic.com>
Message-ID: <1524733169.3408.3.camel@pengutronix.de>

On Thu, 2018-04-26 at 16:44 +0800, Yixun Lan wrote:
> From: Qiufang Dai <qiufang.dai at amlogic.com>
> 
> Adds a Clock and Reset controller driver for the Always-On part
> of the Amlogic Meson-AXG SoC.
> 
> Acked-by: Philipp Zabel <p.zabel at pengutronix.de>

Wrong patch, I have not formed an opinion on this one.

regards
Philipp


From greg at kroah.com  Thu Apr 26 01:59:44 2018
From: greg at kroah.com (Greg KH)
Date: Thu, 26 Apr 2018 10:59:44 +0200
Subject: [PATCH] drm: bridge: dw-hdmi: Fix overflow workaround for
 Amlogic Meson GX SoCs
In-Reply-To: <8766c753-bc2c-0e54-0ac0-73acaa0e11d8@baylibre.com>
References: <1519386277-25902-1-git-send-email-narmstrong@baylibre.com>
 <3b17d17b-cf3d-be54-2462-191e4f2af653@baylibre.com>
 <20180419082751.GA23187@kroah.com>
 <8766c753-bc2c-0e54-0ac0-73acaa0e11d8@baylibre.com>
Message-ID: <20180426085944.GA17265@kroah.com>

On Thu, Apr 26, 2018 at 10:38:08AM +0200, Neil Armstrong wrote:
> Hi Greg,
> 
> On 19/04/2018 10:27, Greg KH wrote:
> > On Thu, Apr 19, 2018 at 10:18:35AM +0200, Neil Armstrong wrote:
> >> Hi Greg,
> >>
> >> On 23/02/2018 12:44, Neil Armstrong wrote:
> >>> The Amlogic Meson GX SoCs, embedded the v2.01a controller, has been also
> >>> identified needing this workaround.
> >>> This patch adds the corresponding version to enable a single iteration for
> >>> this specific version.
> >>>
> >>> Fixes: be41fc55f1aa ("drm: bridge: dw-hdmi: Handle overflow workaround based on device version")
> >>> Signed-off-by: Neil Armstrong <narmstrong at baylibre.com>
> >>
> >> This patch is now present in linux master as commit 9c305eb442f3b371fc722ade827bbf673514123e
> >> Could it be selected for 4.14 ?
> >> The patch has been reworked to apply for 4.17 as indicated in the commit log, but the original patch will apply over 4.14.
> > 
> > I don't have any "original" patch here, I just tried applying it to
> > 4.16.y and 4.14.y and it did not work.  Can you please provide a working
> > backport?
> 
> I sent a backported version last week, any news of it ?
> 
> Message-Id: <1524128048-11086-1-git-send-email-narmstrong at baylibre.com>

Ick, for some reason I missed that in my inbox, sorry, I'll queue it up
for the next round of releases.  Thanks for reminding me.

greg k-h


From p.zabel at pengutronix.de  Thu Apr 26 01:59:39 2018
From: p.zabel at pengutronix.de (Philipp Zabel)
Date: Thu, 26 Apr 2018 10:59:39 +0200
Subject: [PATCH v7 4/7] dt-bindings: clock: reset: Add AXG AO Clock and
 Reset Bindings
In-Reply-To: <20180426084437.192394-5-yixun.lan@amlogic.com>
References: <20180426084437.192394-1-yixun.lan@amlogic.com>
 <20180426084437.192394-5-yixun.lan@amlogic.com>
Message-ID: <1524733179.3408.5.camel@pengutronix.de>

On Thu, 2018-04-26 at 16:44 +0800, Yixun Lan wrote:
> Add dt-bindings headers for the Meson-AXG's AO clock and
> reset controller.
> 
> Reviewed-by: Rob Herring <robh at kernel.org>
> Signed-off-by: Yixun Lan <yixun.lan at amlogic.com>

This one is
Acked-by: Philipp Zabel <p.zabel at pengutronix.de>

regards
Philipp


From narmstrong at baylibre.com  Thu Apr 26 01:47:04 2018
From: narmstrong at baylibre.com (Neil Armstrong)
Date: Thu, 26 Apr 2018 10:47:04 +0200
Subject: [PATCH 3/7] clk: meson: add triple phase clock driver
In-Reply-To: <20180425163304.10852-4-jbrunet@baylibre.com>
References: <20180425163304.10852-1-jbrunet@baylibre.com>
 <20180425163304.10852-4-jbrunet@baylibre.com>
Message-ID: <bc770c22-f0b9-ed1f-bba7-631b9cd42436@baylibre.com>

On 25/04/2018 18:33, Jerome Brunet wrote:
> Add a driver to control the output of the sample clock generator found
> in the axg audio clock controller.
> 
> The goal of this driver is to coherently control the phase provided to
> the different element using the sample clock generator. This simplify
> the usage of the sample clock generator a lot, without comprising the
> ability of the SoC.
> 
> Signed-off-by: Jerome Brunet <jbrunet at baylibre.com>
> ---
>  drivers/clk/meson/Kconfig        |  5 +++
>  drivers/clk/meson/Makefile       |  1 +
>  drivers/clk/meson/clk-triphase.c | 68 ++++++++++++++++++++++++++++++++++++++++
>  drivers/clk/meson/clkc-audio.h   | 20 ++++++++++++
>  4 files changed, 94 insertions(+)
>  create mode 100644 drivers/clk/meson/clk-triphase.c
>  create mode 100644 drivers/clk/meson/clkc-audio.h
> 
> diff --git a/drivers/clk/meson/Kconfig b/drivers/clk/meson/Kconfig
> index 87d69573e172..7f7fd6fb3809 100644
> --- a/drivers/clk/meson/Kconfig
> +++ b/drivers/clk/meson/Kconfig
> @@ -3,6 +3,11 @@ config COMMON_CLK_AMLOGIC
>  	depends on ARCH_MESON || COMPILE_TEST
>  	select COMMON_CLK_REGMAP_MESON
>  
> +config COMMON_CLK_AMLOGIC_AUDIO
> +	bool
> +	depends on ARCH_MESON || COMPILE_TEST
> +	select COMMON_CLK_AMLOGIC
> +
>  config COMMON_CLK_REGMAP_MESON
>  	bool
>  	select REGMAP
> diff --git a/drivers/clk/meson/Makefile b/drivers/clk/meson/Makefile
> index 352fb848c406..64bb917fe1f0 100644
> --- a/drivers/clk/meson/Makefile
> +++ b/drivers/clk/meson/Makefile
> @@ -4,6 +4,7 @@
>  
>  obj-$(CONFIG_COMMON_CLK_AMLOGIC) += clk-pll.o clk-mpll.o clk-audio-divider.o
>  obj-$(CONFIG_COMMON_CLK_AMLOGIC) += clk-phase.o
> +obj-$(CONFIG_COMMON_CLK_AMLOGIC_AUDIO)	+= clk-triphase.o
>  obj-$(CONFIG_COMMON_CLK_MESON8B) += meson8b.o
>  obj-$(CONFIG_COMMON_CLK_GXBB)	 += gxbb.o gxbb-aoclk.o gxbb-aoclk-32k.o
>  obj-$(CONFIG_COMMON_CLK_AXG)	 += axg.o
> diff --git a/drivers/clk/meson/clk-triphase.c b/drivers/clk/meson/clk-triphase.c
> new file mode 100644
> index 000000000000..9508c03c73c1
> --- /dev/null
> +++ b/drivers/clk/meson/clk-triphase.c
> @@ -0,0 +1,68 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +/*
> + * Copyright (c) 2018 BayLibre, SAS.
> + * Author: Jerome Brunet <jbrunet at baylibre.com>
> + */
> +
> +#include <linux/clk-provider.h>
> +#include "clkc-audio.h"
> +
> +/*
> + * This is a special clock for the audio controller.
> + * The phase of mst_sclk clock output can be controlled independently
> + * for the outside world (ph0), the tdmout (ph1) and tdmin (ph2).
> + * Controlling these 3 phases as just one makes things simpler and
> + * give the same clock view to all the element on the i2s bus.
> + * If necessary, we can still control the phase in the tdm block
> + * which makes these independent control redundant.
> + */
> +static inline struct meson_clk_triphase_data *
> +meson_clk_triphase_data(struct clk_regmap *clk)
> +{
> +	return (struct meson_clk_triphase_data *)clk->data;
> +}
> +
> +static void meson_clk_triphase_sync(struct clk_hw *hw)
> +{
> +	struct clk_regmap *clk = to_clk_regmap(hw);
> +	struct meson_clk_triphase_data *tph = meson_clk_triphase_data(clk);
> +	unsigned int val;
> +
> +	/* Get phase 0 and sync it to phase 1 and 2 */
> +	val = meson_parm_read(clk->map, &tph->ph0);
> +	meson_parm_write(clk->map, &tph->ph1, val);
> +	meson_parm_write(clk->map, &tph->ph2, val);
> +}
> +
> +static int meson_clk_triphase_get_phase(struct clk_hw *hw)
> +{
> +	struct clk_regmap *clk = to_clk_regmap(hw);
> +	struct meson_clk_triphase_data *tph = meson_clk_triphase_data(clk);
> +	unsigned int val;
> +
> +	/* Phase are in sync, reading phase 0 is enough */
> +	val = meson_parm_read(clk->map, &tph->ph0);
> +
> +	return meson_clk_degrees_from_val(val, tph->ph0.width);
> +}
> +
> +static int meson_clk_triphase_set_phase(struct clk_hw *hw, int degrees)
> +{
> +	struct clk_regmap *clk = to_clk_regmap(hw);
> +	struct meson_clk_triphase_data *tph = meson_clk_triphase_data(clk);
> +	unsigned int val;
> +
> +	val = meson_clk_degrees_to_val(degrees, tph->ph0.width);
> +	meson_parm_write(clk->map, &tph->ph0, val);
> +	meson_parm_write(clk->map, &tph->ph1, val);
> +	meson_parm_write(clk->map, &tph->ph2, val);
> +
> +	return 0;
> +}
> +
> +const struct clk_ops meson_clk_triphase_ops = {
> +	.init		= meson_clk_triphase_sync,
> +	.get_phase	= meson_clk_triphase_get_phase,
> +	.set_phase	= meson_clk_triphase_set_phase,
> +};
> +EXPORT_SYMBOL_GPL(meson_clk_triphase_ops);
> diff --git a/drivers/clk/meson/clkc-audio.h b/drivers/clk/meson/clkc-audio.h
> new file mode 100644
> index 000000000000..286ff1201258
> --- /dev/null
> +++ b/drivers/clk/meson/clkc-audio.h
> @@ -0,0 +1,20 @@
> +/* SPDX-License-Identifier: GPL-2.0 */

// SPDX-License-Identifier: GPL-2.0

Checkpatch should have warned about this !

> +/*
> + * Copyright (c) 2018 BayLibre, SAS.
> + * Author: Jerome Brunet <jbrunet at baylibre.com>
> + */
> +
> +#ifndef __MESON_CLKC_AUDIO_H
> +#define __MESON_CLKC_AUDIO_H
> +
> +#include "clkc.h"
> +
> +struct meson_clk_triphase_data {
> +	struct parm ph0;
> +	struct parm ph1;
> +	struct parm ph2;
> +};
> +
> +extern const struct clk_ops meson_clk_triphase_ops;
> +
> +#endif /* __MESON_CLKC_AUDIO_H */
> 

Apart that :

Acked-by: Neil Armstrong <narmstrong at baylibre.com>


From yixun.lan at amlogic.com  Thu Apr 26 02:05:52 2018
From: yixun.lan at amlogic.com (Yixun Lan)
Date: Thu, 26 Apr 2018 17:05:52 +0800
Subject: [PATCH v7 4/7] dt-bindings: clock: reset: Add AXG AO Clock and
 Reset Bindings
In-Reply-To: <1524733179.3408.5.camel@pengutronix.de>
References: <20180426084437.192394-1-yixun.lan@amlogic.com>
 <20180426084437.192394-5-yixun.lan@amlogic.com>
 <1524733179.3408.5.camel@pengutronix.de>
Message-ID: <2c7eb0fb-1ddb-728c-0f2c-e807449a4f59@amlogic.com>



On 04/26/18 16:59, Philipp Zabel wrote:
> On Thu, 2018-04-26 at 16:44 +0800, Yixun Lan wrote:
>> Add dt-bindings headers for the Meson-AXG's AO clock and
>> reset controller.
>>
>> Reviewed-by: Rob Herring <robh at kernel.org>
>> Signed-off-by: Yixun Lan <yixun.lan at amlogic.com>
> 
> This one is
> Acked-by: Philipp Zabel <p.zabel at pengutronix.de>
> 

Hi Philipp
 My bad, Indeed, I made a mistake..

HI Jerome:
 Could you fix this once apply the patch series?
or do you want me send another version?

Yixun



From jbrunet at baylibre.com  Thu Apr 26 03:38:17 2018
From: jbrunet at baylibre.com (Jerome Brunet)
Date: Thu, 26 Apr 2018 12:38:17 +0200
Subject: [PATCH] mmc: meson-gx: add device reset
Message-ID: <20180426103817.12675-1-jbrunet@baylibre.com>

Trigger the reset line of the mmc controller while probing, if available
The reset should be optional for now, at least until all related DT node
have the reset property

Signed-off-by: Jerome Brunet <jbrunet at baylibre.com>
---
 Documentation/devicetree/bindings/mmc/amlogic,meson-gx.txt | 2 ++
 drivers/mmc/host/meson-gx-mmc.c                            | 6 ++++++
 2 files changed, 8 insertions(+)

diff --git a/Documentation/devicetree/bindings/mmc/amlogic,meson-gx.txt b/Documentation/devicetree/bindings/mmc/amlogic,meson-gx.txt
index 5add8d7d855f..ba434375e7f2 100644
--- a/Documentation/devicetree/bindings/mmc/amlogic,meson-gx.txt
+++ b/Documentation/devicetree/bindings/mmc/amlogic,meson-gx.txt
@@ -20,6 +20,7 @@ Required properties:
 	"clkin1" - Other parent clock of internal mux
   The driver has an internal mux clock which switches between clkin0 and clkin1 depending on the
   clock rate requested by the MMC core.
+- reset      : phandle of the internal reset line
 
 Example:
 
@@ -30,4 +31,5 @@ Example:
 		clocks = <&clkc CLKID_SD_EMMC_A>, <&xtal>, <&clkc CLKID_FCLK_DIV2>;
 		clock-names = "core", "clkin0", "clkin1";
 		pinctrl-0 = <&emmc_pins>;
+		resets = <&reset RESET_SD_EMMC_A>;
 	};
diff --git a/drivers/mmc/host/meson-gx-mmc.c b/drivers/mmc/host/meson-gx-mmc.c
index 55bbd67177df..9d214622c8cf 100644
--- a/drivers/mmc/host/meson-gx-mmc.c
+++ b/drivers/mmc/host/meson-gx-mmc.c
@@ -35,6 +35,7 @@
 #include <linux/clk.h>
 #include <linux/clk-provider.h>
 #include <linux/regulator/consumer.h>
+#include <linux/reset.h>
 #include <linux/interrupt.h>
 #include <linux/bitfield.h>
 #include <linux/pinctrl/consumer.h>
@@ -1212,6 +1213,11 @@ static int meson_mmc_probe(struct platform_device *pdev)
 		goto free_host;
 	}
 
+	ret = device_reset_optional(&pdev->dev);
+	if (ret)
+		if (ret != -EPROBE_DEFER)
+			dev_err(&pdev->dev, "device reset failed: %d\n", ret);
+
 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 	host->regs = devm_ioremap_resource(&pdev->dev, res);
 	if (IS_ERR(host->regs)) {
-- 
2.14.3



From jbrunet at baylibre.com  Thu Apr 26 03:41:19 2018
From: jbrunet at baylibre.com (Jerome Brunet)
Date: Thu, 26 Apr 2018 12:41:19 +0200
Subject: [PATCH] ARM64: dts: meson: add MMC resets
Message-ID: <20180426104119.13659-1-jbrunet@baylibre.com>

Add reset lines to the mmc controllers of the meson gx and axg SoCs

Signed-off-by: Jerome Brunet <jbrunet at baylibre.com>
---
 arch/arm64/boot/dts/amlogic/meson-axg.dtsi  | 3 +++
 arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi | 3 +++
 arch/arm64/boot/dts/amlogic/meson-gxl.dtsi  | 5 ++++-
 3 files changed, 10 insertions(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
index 854d5b25effd..56c84afb2802 100644
--- a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
@@ -8,6 +8,7 @@
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 #include <dt-bindings/clock/axg-clkc.h>
 #include <dt-bindings/gpio/meson-axg-gpio.h>
+#include <dt-bindings/reset/amlogic,meson-axg-reset.h>
 
 / {
 	compatible = "amlogic,meson-axg";
@@ -130,6 +131,7 @@
 					<&clkc CLKID_SD_EMMC_B_CLK0>,
 					<&clkc CLKID_FCLK_DIV2>;
 				clock-names = "core", "clkin0", "clkin1";
+				resets = <&reset RESET_SD_EMMC_B>;
 			};
 
 			sd_emmc_c: mmc at 7000 {
@@ -141,6 +143,7 @@
 					<&clkc CLKID_SD_EMMC_C_CLK0>,
 					<&clkc CLKID_FCLK_DIV2>;
 				clock-names = "core", "clkin0", "clkin1";
+				resets = <&reset RESET_SD_EMMC_C>;
 			};
 		};
 
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi
index c3b8e0d3fbc9..1cbb0829b15d 100644
--- a/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi
@@ -715,6 +715,7 @@
 		 <&clkc CLKID_SD_EMMC_A_CLK0>,
 		 <&clkc CLKID_FCLK_DIV2>;
 	clock-names = "core", "clkin0", "clkin1";
+	resets = <&reset RESET_SD_EMMC_A>;
 };
 
 &sd_emmc_b {
@@ -722,6 +723,7 @@
 		 <&clkc CLKID_SD_EMMC_B_CLK0>,
 		 <&clkc CLKID_FCLK_DIV2>;
 	clock-names = "core", "clkin0", "clkin1";
+	resets = <&reset RESET_SD_EMMC_B>;
 };
 
 &sd_emmc_c {
@@ -729,6 +731,7 @@
 		 <&clkc CLKID_SD_EMMC_C_CLK0>,
 		 <&clkc CLKID_FCLK_DIV2>;
 	clock-names = "core", "clkin0", "clkin1";
+	resets = <&reset RESET_SD_EMMC_C>;
 };
 
 &spicc {
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi
index 00b5bbd0b3e1..6e4a07112ed8 100644
--- a/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi
@@ -724,13 +724,15 @@
 		 <&clkc CLKID_SD_EMMC_A_CLK0>,
 		 <&clkc CLKID_FCLK_DIV2>;
 	clock-names = "core", "clkin0", "clkin1";
+	resets = <&reset RESET_SD_EMMC_A>;
 };
 
 &sd_emmc_b {
 	clocks = <&clkc CLKID_SD_EMMC_B>,
 		 <&clkc CLKID_SD_EMMC_B_CLK0>,
 		 <&clkc CLKID_FCLK_DIV2>;
-       clock-names = "core", "clkin0", "clkin1";
+	clock-names = "core", "clkin0", "clkin1";
+	resets = <&reset RESET_SD_EMMC_B>;
 };
 
 &sd_emmc_c {
@@ -738,6 +740,7 @@
 		 <&clkc CLKID_SD_EMMC_C_CLK0>,
 		 <&clkc CLKID_FCLK_DIV2>;
 	clock-names = "core", "clkin0", "clkin1";
+	resets = <&reset RESET_SD_EMMC_C>;
 };
 
 &spicc {
-- 
2.14.3



From jbrunet at baylibre.com  Thu Apr 26 03:50:46 2018
From: jbrunet at baylibre.com (Jerome Brunet)
Date: Thu, 26 Apr 2018 12:50:46 +0200
Subject: [PATCH] ARM64: dts: meson: disable sd-uhs modes on the libretech-cc
Message-ID: <20180426105046.14817-1-jbrunet@baylibre.com>

There is a problem with the sd-uhs mode when doing a soft reboot.
Switching back from 1.8v to 3.3v messes with the card, which no longer
respond (timeout errors). According to the specification, we should
perform a card reset (power cycling the card) but this is something we
cannot control on this design.

Then the only solution to restore the communication with the card is an
"unplug-plug" which is not acceptable

Until we find a solution, if any, disable the sd-uhs modes on this design.
For the people using uhs at the moment, there will a performance drop as
a result.

Fixes: 3cde63ebc85c ("ARM64: dts: meson-gxl: libretech-cc: enable high speed modes")
Signed-off-by: Jerome Brunet <jbrunet at baylibre.com>
---
 arch/arm64/boot/dts/amlogic/meson-gxl-s905x-libretech-cc.dts | 3 ---
 1 file changed, 3 deletions(-)

diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-libretech-cc.dts b/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-libretech-cc.dts
index 3e3eb31748a3..f63bceb88caa 100644
--- a/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-libretech-cc.dts
+++ b/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-libretech-cc.dts
@@ -234,9 +234,6 @@
 
 	bus-width = <4>;
 	cap-sd-highspeed;
-	sd-uhs-sdr12;
-	sd-uhs-sdr25;
-	sd-uhs-sdr50;
 	max-frequency = <100000000>;
 	disable-wp;
 
-- 
2.14.3



From ulf.hansson at linaro.org  Thu Apr 26 06:54:48 2018
From: ulf.hansson at linaro.org (Ulf Hansson)
Date: Thu, 26 Apr 2018 15:54:48 +0200
Subject: [PATCH] mmc: meson-gx: add device reset
In-Reply-To: <20180426103817.12675-1-jbrunet@baylibre.com>
References: <20180426103817.12675-1-jbrunet@baylibre.com>
Message-ID: <CAPDyKFooqSGrgKqKxTTRBYbi6s-199GhRNhQvVD0wzWWK3UG=Q@mail.gmail.com>

On 26 April 2018 at 12:38, Jerome Brunet <jbrunet at baylibre.com> wrote:
> Trigger the reset line of the mmc controller while probing, if available
> The reset should be optional for now, at least until all related DT node
> have the reset property
>
> Signed-off-by: Jerome Brunet <jbrunet at baylibre.com>
> ---
>  Documentation/devicetree/bindings/mmc/amlogic,meson-gx.txt | 2 ++

Please move DT doc changes into separate patches. And make the DT
maintainers are in to field as well.

Otherwise, this looks good to me.

Kind regards
Uffe

>  drivers/mmc/host/meson-gx-mmc.c                            | 6 ++++++
>  2 files changed, 8 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/mmc/amlogic,meson-gx.txt b/Documentation/devicetree/bindings/mmc/amlogic,meson-gx.txt
> index 5add8d7d855f..ba434375e7f2 100644
> --- a/Documentation/devicetree/bindings/mmc/amlogic,meson-gx.txt
> +++ b/Documentation/devicetree/bindings/mmc/amlogic,meson-gx.txt
> @@ -20,6 +20,7 @@ Required properties:
>         "clkin1" - Other parent clock of internal mux
>    The driver has an internal mux clock which switches between clkin0 and clkin1 depending on the
>    clock rate requested by the MMC core.
> +- reset      : phandle of the internal reset line
>
>  Example:
>
> @@ -30,4 +31,5 @@ Example:
>                 clocks = <&clkc CLKID_SD_EMMC_A>, <&xtal>, <&clkc CLKID_FCLK_DIV2>;
>                 clock-names = "core", "clkin0", "clkin1";
>                 pinctrl-0 = <&emmc_pins>;
> +               resets = <&reset RESET_SD_EMMC_A>;
>         };
> diff --git a/drivers/mmc/host/meson-gx-mmc.c b/drivers/mmc/host/meson-gx-mmc.c
> index 55bbd67177df..9d214622c8cf 100644
> --- a/drivers/mmc/host/meson-gx-mmc.c
> +++ b/drivers/mmc/host/meson-gx-mmc.c
> @@ -35,6 +35,7 @@
>  #include <linux/clk.h>
>  #include <linux/clk-provider.h>
>  #include <linux/regulator/consumer.h>
> +#include <linux/reset.h>
>  #include <linux/interrupt.h>
>  #include <linux/bitfield.h>
>  #include <linux/pinctrl/consumer.h>
> @@ -1212,6 +1213,11 @@ static int meson_mmc_probe(struct platform_device *pdev)
>                 goto free_host;
>         }
>
> +       ret = device_reset_optional(&pdev->dev);
> +       if (ret)
> +               if (ret != -EPROBE_DEFER)
> +                       dev_err(&pdev->dev, "device reset failed: %d\n", ret);
> +
>         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
>         host->regs = devm_ioremap_resource(&pdev->dev, res);
>         if (IS_ERR(host->regs)) {
> --
> 2.14.3
>


From arnd at arndb.de  Thu Apr 26 07:52:47 2018
From: arnd at arndb.de (Arnd Bergmann)
Date: Thu, 26 Apr 2018 16:52:47 +0200
Subject: [GIT PULL] Amlogic fixes for v4.17-rc
In-Reply-To: <7hbmeg5e6f.fsf@baylibre.com>
References: <7hbmeg5e6f.fsf@baylibre.com>
Message-ID: <CAK8P3a2OpkRwHQvrDh13gLYA1xdNk635XduPDuico2wNG6rQzw@mail.gmail.com>

On Thu, Apr 19, 2018 at 12:43 AM, Kevin Hilman <khilman at baylibre.com> wrote:
> Arnd, Olof,
>
> Technically, this is more "late" than "fixes", but I have excuses...
>
> 1) I was on vacation, but more importantly,
> 2) There were last minute driver issues that got sorted out after I sent
> the main batch v4.17 DT pull requests.  Those issues (USB
> suspend/resume) have now been sorted out and merged for v4.17-rc, so I'm
> sending this series to enable USB for Amlogic.
>
> This has been tested on Amlogic SoCs on top of v4.17-rc1.

Pulled into fixes. I think this is still fine as an exceptional case.

      Arnd


From greg at kroah.com  Thu Apr 26 10:45:56 2018
From: greg at kroah.com (Greg KH)
Date: Thu, 26 Apr 2018 19:45:56 +0200
Subject: [PATCH stable] drm: bridge: dw-hdmi: Fix overflow workaround for
 Amlogic Meson GX SoCs
In-Reply-To: <1524128048-11086-1-git-send-email-narmstrong@baylibre.com>
References: <1524128048-11086-1-git-send-email-narmstrong@baylibre.com>
Message-ID: <20180426174556.GB28091@kroah.com>

On Thu, Apr 19, 2018 at 10:54:08AM +0200, Neil Armstrong wrote:
> commit 9c305eb442f3b371fc722ade827bbf673514123e upstream
> 
> The Amlogic Meson GX SoCs, embedded the v2.01a controller, has been also
> identified needing this workaround.
> This patch adds the corresponding version to enable a single iteration for
> this specific version.
> 
> Fixes: be41fc55f1aa ("drm: bridge: dw-hdmi: Handle overflow workaround based on device version")
> Acked-by: Archit Taneja <architt at codeaurora.org>
> [narmstrong: s/identifies/identified and rebased against Jernej's change]
> Signed-off-by: Neil Armstrong <narmstrong at baylibre.com>
> Link: https://patchwork.freedesktop.org/patch/msgid/1519386277-25902-1-git-send-email-narmstrong at baylibre.com
> [narmstrong: v4.14 to v4.16 backport]
> Cc: <stable at vger.kernel.org> # 4.14.x

Now applied, thanks.

greg k-h


From khilman at baylibre.com  Thu Apr 26 16:35:34 2018
From: khilman at baylibre.com (Kevin Hilman)
Date: Thu, 26 Apr 2018 16:35:34 -0700
Subject: [PATCH] mmc: meson-gx: add device reset
In-Reply-To: <20180426103817.12675-1-jbrunet@baylibre.com> (Jerome Brunet's
 message of "Thu, 26 Apr 2018 12:38:17 +0200")
References: <20180426103817.12675-1-jbrunet@baylibre.com>
Message-ID: <7ha7tp35ix.fsf@baylibre.com>

Jerome Brunet <jbrunet at baylibre.com> writes:

> Trigger the reset line of the mmc controller while probing, if available
> The reset should be optional for now, at least until all related DT node
> have the reset property
>
> Signed-off-by: Jerome Brunet <jbrunet at baylibre.com>

Reviewed-by: Kevin Hilman <khilman at baylibre.com>


From lkp at intel.com  Thu Apr 26 18:13:23 2018
From: lkp at intel.com (kbuild test robot)
Date: Fri, 27 Apr 2018 09:13:23 +0800
Subject: [PATCH 7/7] clk: meson: axg: add the audio clock controller driver
In-Reply-To: <20180425163304.10852-8-jbrunet@baylibre.com>
References: <20180425163304.10852-8-jbrunet@baylibre.com>
Message-ID: <201804270920.dd1N3TWc%fengguang.wu@intel.com>

Hi Jerome,

I love your patch! Yet something to improve:

[auto build test ERROR on clk/clk-next]
[also build test ERROR on v4.17-rc2 next-20180426]
[if your patch is applied to the wrong git tree, please drop us a note to help improve the system]

url:    https://github.com/0day-ci/linux/commits/Jerome-Brunet/clk-meson-axg-add-audio-clock-controller-support/20180427-035149
base:   https://git.kernel.org/pub/scm/linux/kernel/git/clk/linux.git clk-next
config: arm64-allmodconfig (attached as .config)
compiler: aarch64-linux-gnu-gcc (Debian 7.2.0-11) 7.2.0
reproduce:
        wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
        chmod +x ~/bin/make.cross
        # save the attached .config to linux build tree
        make.cross ARCH=arm64 

All error/warnings (new ones prefixed by >>):

   In file included from drivers/clk/meson/clk-triphase.c:8:0:
>> drivers/clk/meson/clkc-audio.h:22:18: error: field 'cached_duty' has incomplete type
     struct clk_duty cached_duty;
                     ^~~~~~~~~~~
--
   In file included from drivers/clk/meson/sclk-div.c:19:0:
>> drivers/clk/meson/clkc-audio.h:22:18: error: field 'cached_duty' has incomplete type
     struct clk_duty cached_duty;
                     ^~~~~~~~~~~
   drivers/clk/meson/sclk-div.c: In function 'sclk_div_set_duty_cycle':
>> drivers/clk/meson/sclk-div.c:127:43: error: dereferencing pointer to incomplete type 'struct clk_duty'
      memcpy(&sclk->cached_duty, duty, sizeof(*duty));
                                              ^~~~~
   drivers/clk/meson/sclk-div.c: At top level:
>> drivers/clk/meson/sclk-div.c:239:3: error: 'const struct clk_ops' has no member named 'get_duty_cycle'
     .get_duty_cycle = sclk_div_get_duty_cycle,
      ^~~~~~~~~~~~~~
>> drivers/clk/meson/sclk-div.c:239:20: error: initialization from incompatible pointer type [-Werror=incompatible-pointer-types]
     .get_duty_cycle = sclk_div_get_duty_cycle,
                       ^~~~~~~~~~~~~~~~~~~~~~~
   drivers/clk/meson/sclk-div.c:239:20: note: (near initialization for 'meson_sclk_div_ops.disable_unused')
>> drivers/clk/meson/sclk-div.c:240:3: error: 'const struct clk_ops' has no member named 'set_duty_cycle'
     .set_duty_cycle = sclk_div_set_duty_cycle,
      ^~~~~~~~~~~~~~
   drivers/clk/meson/sclk-div.c:240:20: error: initialization from incompatible pointer type [-Werror=incompatible-pointer-types]
     .set_duty_cycle = sclk_div_set_duty_cycle,
                       ^~~~~~~~~~~~~~~~~~~~~~~
   drivers/clk/meson/sclk-div.c:240:20: note: (near initialization for 'meson_sclk_div_ops.recalc_rate')
   cc1: some warnings being treated as errors
--
   In file included from drivers/clk/meson/axg-audio.c:17:0:
>> drivers/clk/meson/clkc-audio.h:22:18: error: field 'cached_duty' has incomplete type
     struct clk_duty cached_duty;
                     ^~~~~~~~~~~
>> drivers/clk/meson/axg-audio.c:35:12: error: 'CLK_DUTY_CYCLE_PARENT' undeclared here (not in a function); did you mean 'CLK_SET_RATE_PARENT'?
      .flags = CLK_DUTY_CYCLE_PARENT | (_iflags),  \
               ^
>> drivers/clk/meson/axg-audio.c:74:2: note: in expansion of macro 'AXG_AUD_GATE'
     AXG_AUD_GATE(_name, AUDIO_CLK_GATE_EN, _bit, "axg_audio_pclk", 0)
     ^~~~~~~~~~~~
>> drivers/clk/meson/axg-audio.c:77:8: note: in expansion of macro 'AXG_PCLK_GATE'
    static AXG_PCLK_GATE(ddr_arb,    0);
           ^~~~~~~~~~~~~

vim +/cached_duty +22 drivers/clk/meson/clkc-audio.h

6f493fa86 Jerome Brunet 2018-04-25  17  
e8e28d3aa Jerome Brunet 2018-04-25  18  struct meson_sclk_div_data {
e8e28d3aa Jerome Brunet 2018-04-25  19  	struct parm div;
e8e28d3aa Jerome Brunet 2018-04-25  20  	struct parm hi;
e8e28d3aa Jerome Brunet 2018-04-25  21  	unsigned int cached_div;
e8e28d3aa Jerome Brunet 2018-04-25 @22  	struct clk_duty cached_duty;
e8e28d3aa Jerome Brunet 2018-04-25  23  };
e8e28d3aa Jerome Brunet 2018-04-25  24  

:::::: The code at line 22 was first introduced by commit
:::::: e8e28d3aaf526ae3af0d0fd0e8b4c8c8ad2041d8 clk: meson: add axg audio sclk divider driver

:::::: TO: Jerome Brunet <jbrunet at baylibre.com>
:::::: CC: 0day robot <fengguang.wu at intel.com>

---
0-DAY kernel test infrastructure                Open Source Technology Center
https://lists.01.org/pipermail/kbuild-all                   Intel Corporation
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From yixun.lan at amlogic.com  Thu Apr 26 20:09:59 2018
From: yixun.lan at amlogic.com (Yixun Lan)
Date: Fri, 27 Apr 2018 11:09:59 +0800
Subject: [PATCH 2/2] net: stmmac: dwmac-meson: extend phy mode setting
In-Reply-To: <1524732426.4026.84.camel@baylibre.com>
References: <20180426160508.29380-1-yixun.lan@amlogic.com>
 <20180426160508.29380-3-yixun.lan@amlogic.com>
 <1524732426.4026.84.camel@baylibre.com>
Message-ID: <daa6e325-ce4d-7b6b-dc43-2a884d485139@amlogic.com>

Hi Jerome
On 04/26/18 16:47, Jerome Brunet wrote:
> On Thu, 2018-04-26 at 16:05 +0000, Yixun Lan wrote:
>>   In the Meson-AXG SoC, the phy mode setting of PRG_ETH0 in the glue layer
>> is extended from bit[0] to bit[2:0].
>>   There is no problem if we configure it to the RGMII 1000M PHY mode,
>> since the register setting is coincidentally compatible with previous one,
>> but for the RMII 100M PHY mode, the configuration need to be changed to
>> value - b100.
>>   This patch was verified with a RTL8201F 100M ethernet PHY.
>>
>> Signed-off-by: Yixun Lan <yixun.lan at amlogic.com>
>> ---
>>  .../ethernet/stmicro/stmmac/dwmac-meson8b.c   | 95 ++++++++++++++++---
>>  1 file changed, 84 insertions(+), 11 deletions(-)
>>
>> diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c
>> index 7cb794094a70..e3688b6dd87c 100644
>> --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c
>> +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c
>> @@ -18,6 +18,7 @@
>>  #include <linux/io.h>
>>  #include <linux/ioport.h>
>>  #include <linux/module.h>
>> +#include <linux/of_device.h>
>>  #include <linux/of_net.h>
>>  #include <linux/mfd/syscon.h>
>>  #include <linux/platform_device.h>
>> @@ -29,6 +30,10 @@
>>  
>>  #define PRG_ETH0_RGMII_MODE		BIT(0)
>>  
>> +#define PRG_ETH0_EXT_PHY_MODE_MASK	GENMASK(2, 0)
>> +#define PRG_ETH0_EXT_RGMII_MODE		1
>> +#define PRG_ETH0_EXT_RMII_MODE		4
>> +
>>  /* mux to choose between fclk_div2 (bit unset) and mpll2 (bit set) */
>>  #define PRG_ETH0_CLK_M250_SEL_SHIFT	4
>>  #define PRG_ETH0_CLK_M250_SEL_MASK	GENMASK(4, 4)
>> @@ -46,10 +51,16 @@
>>  #define PRG_ETH0_TX_AND_PHY_REF_CLK	BIT(12)
>>  
>>  #define MUX_CLK_NUM_PARENTS		2
>> +struct meson8b_dwmac_data {
>> +	bool ext_phy_mode;
>> +};
>>  
>>  struct meson8b_dwmac {
>>  	struct device		*dev;
>>  	void __iomem		*regs;
>> +
>> +	const struct meson8b_dwmac_data *data;
>> +
>>  	phy_interface_t		phy_mode;
>>  	struct clk		*rgmii_tx_clk;
>>  	u32			tx_delay_ns;
>> @@ -171,6 +182,46 @@ static int meson8b_init_rgmii_tx_clk(struct meson8b_dwmac *dwmac)
>>  	return 0;
>>  }
>>  
>> +static int meson8b_init_set_mode(struct meson8b_dwmac *dwmac)
>> +{
>> +	bool ext_phy_mode = dwmac->data->ext_phy_mode;
>> +
>> +	switch (dwmac->phy_mode) {
>> +	case PHY_INTERFACE_MODE_RGMII:
>> +	case PHY_INTERFACE_MODE_RGMII_RXID:
>> +	case PHY_INTERFACE_MODE_RGMII_ID:
>> +	case PHY_INTERFACE_MODE_RGMII_TXID:
>> +		/* enable RGMII mode */
>> +		if (ext_phy_mode)
> 
> Looks weird to have this if target at a specific SoC withing a function named
> after another SoC
> 
> Couldn't you make one function per soc type, and pass that function pointer in
> the match data ?
> 
sounds good, I can do this

>> +			meson8b_dwmac_mask_bits(dwmac, PRG_ETH0,
>> +						PRG_ETH0_EXT_PHY_MODE_MASK,
>> +						PRG_ETH0_EXT_RGMII_MODE);
>> +		else
>> +			meson8b_dwmac_mask_bits(dwmac, PRG_ETH0,
>> +						PRG_ETH0_RGMII_MODE,
>> +						PRG_ETH0_RGMII_MODE);
>> +
>> +		break;
>> +	case PHY_INTERFACE_MODE_RMII:
>> +		/* disable RGMII mode -> enables RMII mode */
>> +		if (ext_phy_mode)
>> +			meson8b_dwmac_mask_bits(dwmac, PRG_ETH0,
>> +						PRG_ETH0_EXT_PHY_MODE_MASK,
>> +						PRG_ETH0_EXT_RMII_MODE);
>> +		else
>> +			meson8b_dwmac_mask_bits(dwmac, PRG_ETH0,
>> +						PRG_ETH0_RGMII_MODE, 0);
>> +
>> +		break;
>> +	default:
>> +		dev_err(dwmac->dev, "fail to set phy-mode %s\n",
>> +			phy_modes(dwmac->phy_mode));
>> +		return -EINVAL;
>> +	}
>> +
>> +	return 0;
>> +}
>> +
>>  static int meson8b_init_prg_eth(struct meson8b_dwmac *dwmac)
>>  {
>>  	int ret;
>> @@ -188,10 +239,6 @@ static int meson8b_init_prg_eth(struct meson8b_dwmac *dwmac)
>>  
>>  	case PHY_INTERFACE_MODE_RGMII_ID:
>>  	case PHY_INTERFACE_MODE_RGMII_TXID:
>> -		/* enable RGMII mode */
>> -		meson8b_dwmac_mask_bits(dwmac, PRG_ETH0, PRG_ETH0_RGMII_MODE,
>> -					PRG_ETH0_RGMII_MODE);
>> -
>>  		/* only relevant for RMII mode -> disable in RGMII mode */
>>  		meson8b_dwmac_mask_bits(dwmac, PRG_ETH0,
>>  					PRG_ETH0_INVERTED_RMII_CLK, 0);
>> @@ -224,10 +271,6 @@ static int meson8b_init_prg_eth(struct meson8b_dwmac *dwmac)
>>  		break;
>>  
>>  	case PHY_INTERFACE_MODE_RMII:
>> -		/* disable RGMII mode -> enables RMII mode */
>> -		meson8b_dwmac_mask_bits(dwmac, PRG_ETH0, PRG_ETH0_RGMII_MODE,
>> -					0);
>> -
>>  		/* invert internal clk_rmii_i to generate 25/2.5 tx_rx_clk */
>>  		meson8b_dwmac_mask_bits(dwmac, PRG_ETH0,
>>  					PRG_ETH0_INVERTED_RMII_CLK,
>> @@ -274,6 +317,11 @@ static int meson8b_dwmac_probe(struct platform_device *pdev)
>>  		goto err_remove_config_dt;
>>  	}
>>  
>> +	dwmac->data = (const struct meson8b_dwmac_data *)
>> +		of_device_get_match_data(&pdev->dev);
>> +	if (!dwmac->data)
>> +		return -EINVAL;
>> +
>>  	res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
>>  	dwmac->regs = devm_ioremap_resource(&pdev->dev, res);
>>  	if (IS_ERR(dwmac->regs)) {
>> @@ -298,6 +346,10 @@ static int meson8b_dwmac_probe(struct platform_device *pdev)
>>  	if (ret)
>>  		goto err_remove_config_dt;
>>  
>> +	ret = meson8b_init_set_mode(dwmac);
>> +	if (ret)
>> +		goto err_remove_config_dt;
>> +
>>  	ret = meson8b_init_prg_eth(dwmac);
>>  	if (ret)
>>  		goto err_remove_config_dt;
>> @@ -316,10 +368,31 @@ static int meson8b_dwmac_probe(struct platform_device *pdev)
>>  	return ret;
>>  }
>>  
>> +static const struct meson8b_dwmac_data meson8b_dwmac_data = {
>> +	.ext_phy_mode = false,
>> +};
>> +
>> +static const struct meson8b_dwmac_data meson_axg_dwmac_data = {
>> +	.ext_phy_mode = true,
>> +};
>> +
>>  static const struct of_device_id meson8b_dwmac_match[] = {
>> -	{ .compatible = "amlogic,meson8b-dwmac" },
>> -	{ .compatible = "amlogic,meson8m2-dwmac" },
>> -	{ .compatible = "amlogic,meson-gxbb-dwmac" },
>> +	{
>> +		.compatible = "amlogic,meson8b-dwmac",
>> +		.data = &meson8b_dwmac_data,
>> +	},
>> +	{
>> +		.compatible = "amlogic,meson8m2-dwmac",
>> +		.data = &meson8b_dwmac_data,
>> +	},
>> +	{
>> +		.compatible = "amlogic,meson-gxbb-dwmac",
>> +		.data = &meson8b_dwmac_data,
>> +	},
>> +	{
>> +		.compatible = "amlogic,meson-axg-dwmac",
>> +		.data = &meson_axg_dwmac_data,
>> +	},
>>  	{ }
>>  };
>>  MODULE_DEVICE_TABLE(of, meson8b_dwmac_match);
> 
> .
> 



From jbrunet at baylibre.com  Fri Apr 27 02:20:41 2018
From: jbrunet at baylibre.com (Jerome Brunet)
Date: Fri, 27 Apr 2018 11:20:41 +0200
Subject: [PATCH v7 0/7] clk: meson-axg: Add AO Cloclk and Reset driver
In-Reply-To: <20180426084437.192394-1-yixun.lan@amlogic.com>
References: <20180426084437.192394-1-yixun.lan@amlogic.com>
Message-ID: <1524820841.4026.112.camel@baylibre.com>

On Thu, 2018-04-26 at 16:44 +0800, Yixun Lan wrote:
>   This patch try to add AO clock and Reset driver for Amlogic's
> Meson-AXG SoC.
>   Please note that patch 7 need to wait for the DTS changes[3] merged
> into mainline first, otherwise it will break the serial console.
> 
>  patch 2: factor the common code into a dedicated file
>  patch 3-5: add the aoclk driver for AXG SoC
>  patch 6-7: drop unnecessary clock flags
> 
> changes since v6 at [7]: 
>  - fix over 80 chars chechpatch error
>  - add Philip's Ack on patch 5
>  - drop extra end of newline
> 
> changes since v5 at [6]: 
>  - drop unnecessary header files
>  - add 'axg_aoclk' prefix to clk driver, make them more consistent
>  - add missing end new line..
> 
> changes since v4 at [5]: 
>  - fix return err
>  - introduce CONFIG_COMMON_CLK_MESON_AO
>  - format/style minor fix
> 
> changes since v3 at [4]: 
>  - add 'const' contraint to the read-only data
>  - switch to devm_of_clk_add_hw_provider API
>  - check return value of devm_reset_controller_register
> 
> changes since v2 at [2]: 
>  - rework meson_aoclkc_probe() which leverage the of_match_data
>  - merge patch 5-6 into this series
>  - seperate DTS patch, will send to Kevin Hilman independently
>  
> changes since v1 at [0]: 
>  - rebase to clk-meson's branch 'next/drivers' [1]
>  - fix license, update to BSD-3-Clause
>  - drop un-used include header file
> 
> [0] https://lkml.kernel.org/r/20180209070026.193879-1-yixun.lan at amlogic.com
> [1] git://github.com/BayLibre/clk-meson.git branch: next-drivers
> [2] https://lkml.kernel.org/r/20180323143816.200573-1-yixun.lan at amlogic.com
> [3] https://lkml.kernel.org/r/20180326081809.49493-4-yixun.lan at amlogic.com
> [4] https://lkml.kernel.org/r/20180328025050.221585-1-yixun.lan at amlogic.com
> [5] https://lkml.kernel.org/r/20180408031938.153474-1-yixun.lan at amlogic.com
> [6] https://lkml.kernel.org/r/20180409143749.71197-1-yixun.lan at amlogic.com
> [7] https://lkml.kernel.org/r/20180419135426.155794-1-yixun.lan at amlogic.com

Yixun,

Your series looks mostly Ok to me, apart from the problem reported by Philipp.

However, once applied, if the clkc ao controller is enabled, both gxl and axg
fail to complete the boot. Could you please explain how this was tested ??

Not merging it until we get to the bottom of this.

> 
> 
> Qiufang Dai (1):
>   clk: meson-axg: Add AO Clock and Reset controller driver
> 
> Yixun Lan (6):
>   clk: meson: migrate to devm_of_clk_add_hw_provider API
>   clk: meson: aoclk: refactor common code into dedicated file
>   dt-bindings: clock: axg-aoclkc: New binding for Meson-AXG SoC
>   dt-bindings: clock: reset: Add AXG AO Clock and Reset Bindings
>   clk: meson: drop CLK_SET_RATE_PARENT flag
>   clk: meson: drop CLK_IGNORE_UNUSED flag
> 
>  .../bindings/clock/amlogic,gxbb-aoclkc.txt    |   1 +
>  drivers/clk/meson/Kconfig                     |   8 +
>  drivers/clk/meson/Makefile                    |   3 +-
>  drivers/clk/meson/axg-aoclk.c                 | 163 ++++++++++++++++++
>  drivers/clk/meson/axg-aoclk.h                 |  29 ++++
>  drivers/clk/meson/gxbb-aoclk.c                |  95 ++++------
>  drivers/clk/meson/gxbb-aoclk.h                |   5 +
>  drivers/clk/meson/meson-aoclk.c               |  81 +++++++++
>  drivers/clk/meson/meson-aoclk.h               |  34 ++++
>  include/dt-bindings/clock/axg-aoclkc.h        |  26 +++
>  include/dt-bindings/reset/axg-aoclkc.h        |  20 +++
>  11 files changed, 401 insertions(+), 64 deletions(-)
>  create mode 100644 drivers/clk/meson/axg-aoclk.c
>  create mode 100644 drivers/clk/meson/axg-aoclk.h
>  create mode 100644 drivers/clk/meson/meson-aoclk.c
>  create mode 100644 drivers/clk/meson/meson-aoclk.h
>  create mode 100644 include/dt-bindings/clock/axg-aoclkc.h
>  create mode 100644 include/dt-bindings/reset/axg-aoclkc.h
> 



From yixun.lan at amlogic.com  Fri Apr 27 02:31:44 2018
From: yixun.lan at amlogic.com (Yixun Lan)
Date: Fri, 27 Apr 2018 17:31:44 +0800
Subject: [PATCH v7 0/7] clk: meson-axg: Add AO Cloclk and Reset driver
In-Reply-To: <1524820841.4026.112.camel@baylibre.com>
References: <20180426084437.192394-1-yixun.lan@amlogic.com>
 <1524820841.4026.112.camel@baylibre.com>
Message-ID: <fbd24a73-6793-76be-3ca5-04cbac5db198@amlogic.com>

hi Jerome:


On 04/27/18 17:20, Jerome Brunet wrote:
> On Thu, 2018-04-26 at 16:44 +0800, Yixun Lan wrote:
>>   This patch try to add AO clock and Reset driver for Amlogic's
>> Meson-AXG SoC.
>>   Please note that patch 7 need to wait for the DTS changes[3] merged
>> into mainline first, otherwise it will break the serial console.
>>
>>  patch 2: factor the common code into a dedicated file
>>  patch 3-5: add the aoclk driver for AXG SoC
>>  patch 6-7: drop unnecessary clock flags
>>
>> changes since v6 at [7]: 
>>  - fix over 80 chars chechpatch error
>>  - add Philip's Ack on patch 5
>>  - drop extra end of newline
>>
>> changes since v5 at [6]: 
>>  - drop unnecessary header files
>>  - add 'axg_aoclk' prefix to clk driver, make them more consistent
>>  - add missing end new line..
>>
>> changes since v4 at [5]: 
>>  - fix return err
>>  - introduce CONFIG_COMMON_CLK_MESON_AO
>>  - format/style minor fix
>>
>> changes since v3 at [4]: 
>>  - add 'const' contraint to the read-only data
>>  - switch to devm_of_clk_add_hw_provider API
>>  - check return value of devm_reset_controller_register
>>
>> changes since v2 at [2]: 
>>  - rework meson_aoclkc_probe() which leverage the of_match_data
>>  - merge patch 5-6 into this series
>>  - seperate DTS patch, will send to Kevin Hilman independently
>>  
>> changes since v1 at [0]: 
>>  - rebase to clk-meson's branch 'next/drivers' [1]
>>  - fix license, update to BSD-3-Clause
>>  - drop un-used include header file
>>
>> [0] https://lkml.kernel.org/r/20180209070026.193879-1-yixun.lan at amlogic.com
>> [1] git://github.com/BayLibre/clk-meson.git branch: next-drivers
>> [2] https://lkml.kernel.org/r/20180323143816.200573-1-yixun.lan at amlogic.com
>> [3] https://lkml.kernel.org/r/20180326081809.49493-4-yixun.lan at amlogic.com
>> [4] https://lkml.kernel.org/r/20180328025050.221585-1-yixun.lan at amlogic.com
>> [5] https://lkml.kernel.org/r/20180408031938.153474-1-yixun.lan at amlogic.com
>> [6] https://lkml.kernel.org/r/20180409143749.71197-1-yixun.lan at amlogic.com
>> [7] https://lkml.kernel.org/r/20180419135426.155794-1-yixun.lan at amlogic.com
> 
> Yixun,
> 
> Your series looks mostly Ok to me, apart from the problem reported by Philipp.
> 
> However, once applied, if the clkc ao controller is enabled, both gxl and axg
> fail to complete the boot. Could you please explain how this was tested ??
> 

isn't this caused by the patch 7?
 [PATCH v7 7/7] clk: meson: drop CLK_IGNORE_UNUSED flag


you need to also apply this DT patch which I've sent[1]:
 [PATCH v3 3/3] ARM64: dts: meson: fix clock source of the pclk for UART_AO

could you exclude the patch 7 for now until Kevin merged the DT part?

[1] https://lkml.kernel.org/r/20180328030130.240336-4-yixun.lan at amlogic.com


> Not merging it until we get to the bottom of this.
> 
>>
>>
>> Qiufang Dai (1):
>>   clk: meson-axg: Add AO Clock and Reset controller driver
>>
>> Yixun Lan (6):
>>   clk: meson: migrate to devm_of_clk_add_hw_provider API
>>   clk: meson: aoclk: refactor common code into dedicated file
>>   dt-bindings: clock: axg-aoclkc: New binding for Meson-AXG SoC
>>   dt-bindings: clock: reset: Add AXG AO Clock and Reset Bindings
>>   clk: meson: drop CLK_SET_RATE_PARENT flag
>>   clk: meson: drop CLK_IGNORE_UNUSED flag
>>
>>  .../bindings/clock/amlogic,gxbb-aoclkc.txt    |   1 +
>>  drivers/clk/meson/Kconfig                     |   8 +
>>  drivers/clk/meson/Makefile                    |   3 +-
>>  drivers/clk/meson/axg-aoclk.c                 | 163 ++++++++++++++++++
>>  drivers/clk/meson/axg-aoclk.h                 |  29 ++++
>>  drivers/clk/meson/gxbb-aoclk.c                |  95 ++++------
>>  drivers/clk/meson/gxbb-aoclk.h                |   5 +
>>  drivers/clk/meson/meson-aoclk.c               |  81 +++++++++
>>  drivers/clk/meson/meson-aoclk.h               |  34 ++++
>>  include/dt-bindings/clock/axg-aoclkc.h        |  26 +++
>>  include/dt-bindings/reset/axg-aoclkc.h        |  20 +++
>>  11 files changed, 401 insertions(+), 64 deletions(-)
>>  create mode 100644 drivers/clk/meson/axg-aoclk.c
>>  create mode 100644 drivers/clk/meson/axg-aoclk.h
>>  create mode 100644 drivers/clk/meson/meson-aoclk.c
>>  create mode 100644 drivers/clk/meson/meson-aoclk.h
>>  create mode 100644 include/dt-bindings/clock/axg-aoclkc.h
>>  create mode 100644 include/dt-bindings/reset/axg-aoclkc.h
>>
> 
> .
> 



From jbrunet at baylibre.com  Fri Apr 27 02:33:40 2018
From: jbrunet at baylibre.com (Jerome Brunet)
Date: Fri, 27 Apr 2018 11:33:40 +0200
Subject: [PATCH 0/2] clk: meson: mpll: add round closest support
In-Reply-To: <20180420095603.29964-1-jbrunet@baylibre.com>
References: <20180420095603.29964-1-jbrunet@baylibre.com>
Message-ID: <1524821620.4026.113.camel@baylibre.com>

On Fri, 2018-04-20 at 11:56 +0200, Jerome Brunet wrote:
> ATM, the mpll driver can only round the requested rate down, even if
> rounding up would have provided a better approximation of the requested
> rate.
> 
> This patchset adds a flag to enable rounding to the closest rate possible,
> even if it means rounding up.
> 
> The flag is then enabled on the axg platform to improve the rates provided
> to the audio subsystem.
> 
> Jerome Brunet (2):
>   clk: meson: mpll: add round closest support
>   clk: meson: axg: let mpll clocks round closest
> 
>  drivers/clk/meson/axg.c      |  4 ++++
>  drivers/clk/meson/clk-mpll.c | 25 ++++++++++++++++++++-----
>  drivers/clk/meson/clkc.h     |  3 +++
>  3 files changed, 27 insertions(+), 5 deletions(-)
> 

Series applied with Neil's ack


From jbrunet at baylibre.com  Fri Apr 27 02:59:14 2018
From: jbrunet at baylibre.com (Jerome Brunet)
Date: Fri, 27 Apr 2018 11:59:14 +0200
Subject: [PATCH v7 0/7] clk: meson-axg: Add AO Cloclk and Reset driver
In-Reply-To: <fbd24a73-6793-76be-3ca5-04cbac5db198@amlogic.com>
References: <20180426084437.192394-1-yixun.lan@amlogic.com>
 <1524820841.4026.112.camel@baylibre.com>
 <fbd24a73-6793-76be-3ca5-04cbac5db198@amlogic.com>
Message-ID: <1524823154.4026.123.camel@baylibre.com>

On Fri, 2018-04-27 at 17:31 +0800, Yixun Lan wrote:
> hi Jerome:
> 
> 
> On 04/27/18 17:20, Jerome Brunet wrote:
> > On Thu, 2018-04-26 at 16:44 +0800, Yixun Lan wrote:
> > >   This patch try to add AO clock and Reset driver for Amlogic's
> > > Meson-AXG SoC.
> > >   Please note that patch 7 need to wait for the DTS changes[3] merged
> > > into mainline first, otherwise it will break the serial console.
> > > 
> > >  patch 2: factor the common code into a dedicated file
> > >  patch 3-5: add the aoclk driver for AXG SoC
> > >  patch 6-7: drop unnecessary clock flags
> > > 
> > > changes since v6 at [7]: 
> > >  - fix over 80 chars chechpatch error
> > >  - add Philip's Ack on patch 5
> > >  - drop extra end of newline
> > > 
> > > changes since v5 at [6]: 
> > >  - drop unnecessary header files
> > >  - add 'axg_aoclk' prefix to clk driver, make them more consistent
> > >  - add missing end new line..
> > > 
> > > changes since v4 at [5]: 
> > >  - fix return err
> > >  - introduce CONFIG_COMMON_CLK_MESON_AO
> > >  - format/style minor fix
> > > 
> > > changes since v3 at [4]: 
> > >  - add 'const' contraint to the read-only data
> > >  - switch to devm_of_clk_add_hw_provider API
> > >  - check return value of devm_reset_controller_register
> > > 
> > > changes since v2 at [2]: 
> > >  - rework meson_aoclkc_probe() which leverage the of_match_data
> > >  - merge patch 5-6 into this series
> > >  - seperate DTS patch, will send to Kevin Hilman independently
> > >  
> > > changes since v1 at [0]: 
> > >  - rebase to clk-meson's branch 'next/drivers' [1]
> > >  - fix license, update to BSD-3-Clause
> > >  - drop un-used include header file
> > > 
> > > [0] https://lkml.kernel.org/r/20180209070026.193879-1-yixun.lan at amlogic.com
> > > [1] git://github.com/BayLibre/clk-meson.git branch: next-drivers
> > > [2] https://lkml.kernel.org/r/20180323143816.200573-1-yixun.lan at amlogic.com
> > > [3] https://lkml.kernel.org/r/20180326081809.49493-4-yixun.lan at amlogic.com
> > > [4] https://lkml.kernel.org/r/20180328025050.221585-1-yixun.lan at amlogic.com
> > > [5] https://lkml.kernel.org/r/20180408031938.153474-1-yixun.lan at amlogic.com
> > > [6] https://lkml.kernel.org/r/20180409143749.71197-1-yixun.lan at amlogic.com
> > > [7] https://lkml.kernel.org/r/20180419135426.155794-1-yixun.lan at amlogic.com
> > 
> > Yixun,
> > 
> > Your series looks mostly Ok to me, apart from the problem reported by Philipp.
> > 
> > However, once applied, if the clkc ao controller is enabled, both gxl and axg
> > fail to complete the boot. Could you please explain how this was tested ??
> > 
> 
> isn't this caused by the patch 7?
>  [PATCH v7 7/7] clk: meson: drop CLK_IGNORE_UNUSED flag
> 
> 
> you need to also apply this DT patch which I've sent[1]:
>  [PATCH v3 3/3] ARM64: dts: meson: fix clock source of the pclk for UART_AO
> 
> could you exclude the patch 7 for now until Kevin merged the DT part?
> 
> [1] https://lkml.kernel.org/r/20180328030130.240336-4-yixun.lan at amlogic.com

Looks to be the problem indeed. But it is still an issue with how your patchset
in organized.

I can't merge this until Kevin merges the patch above, which he can't merge
until there is the clkc_ao support in axg, which is given by this series.

1# You should remove the axg part of the patch above. Kevin will be able to
merge it w/o any dependencies. (BTW, the patch is broken for axg because 1) you
did not include the dt-binding header for the clkc_ao in axg and 2) the clkc_ao
does not exist at this stage)
2# I can then safely merge this series - w/o breaking gxbb and gxl.
3# Finally you'll have to make a DT change for the axg, enabling the clkc_ao and
changes the uart clocks at the same time.

> 
> 
> > Not merging it until we get to the bottom of this.
> > 
> > > 
> > > 
> > > Qiufang Dai (1):
> > >   clk: meson-axg: Add AO Clock and Reset controller driver
> > > 
> > > Yixun Lan (6):
> > >   clk: meson: migrate to devm_of_clk_add_hw_provider API
> > >   clk: meson: aoclk: refactor common code into dedicated file
> > >   dt-bindings: clock: axg-aoclkc: New binding for Meson-AXG SoC
> > >   dt-bindings: clock: reset: Add AXG AO Clock and Reset Bindings
> > >   clk: meson: drop CLK_SET_RATE_PARENT flag
> > >   clk: meson: drop CLK_IGNORE_UNUSED flag
> > > 
> > >  .../bindings/clock/amlogic,gxbb-aoclkc.txt    |   1 +
> > >  drivers/clk/meson/Kconfig                     |   8 +
> > >  drivers/clk/meson/Makefile                    |   3 +-
> > >  drivers/clk/meson/axg-aoclk.c                 | 163 ++++++++++++++++++
> > >  drivers/clk/meson/axg-aoclk.h                 |  29 ++++
> > >  drivers/clk/meson/gxbb-aoclk.c                |  95 ++++------
> > >  drivers/clk/meson/gxbb-aoclk.h                |   5 +
> > >  drivers/clk/meson/meson-aoclk.c               |  81 +++++++++
> > >  drivers/clk/meson/meson-aoclk.h               |  34 ++++
> > >  include/dt-bindings/clock/axg-aoclkc.h        |  26 +++
> > >  include/dt-bindings/reset/axg-aoclkc.h        |  20 +++
> > >  11 files changed, 401 insertions(+), 64 deletions(-)
> > >  create mode 100644 drivers/clk/meson/axg-aoclk.c
> > >  create mode 100644 drivers/clk/meson/axg-aoclk.h
> > >  create mode 100644 drivers/clk/meson/meson-aoclk.c
> > >  create mode 100644 drivers/clk/meson/meson-aoclk.h
> > >  create mode 100644 include/dt-bindings/clock/axg-aoclkc.h
> > >  create mode 100644 include/dt-bindings/reset/axg-aoclkc.h
> > > 
> > 
> > .
> > 
> 
> 



From jbrunet at baylibre.com  Fri Apr 27 03:00:52 2018
From: jbrunet at baylibre.com (Jerome Brunet)
Date: Fri, 27 Apr 2018 12:00:52 +0200
Subject: [PATCH v7 1/7] clk: meson: migrate to
 devm_of_clk_add_hw_provider API
In-Reply-To: <20180426084437.192394-2-yixun.lan@amlogic.com>
References: <20180426084437.192394-1-yixun.lan@amlogic.com>
 <20180426084437.192394-2-yixun.lan@amlogic.com>
Message-ID: <1524823252.4026.124.camel@baylibre.com>

On Thu, 2018-04-26 at 16:44 +0800, Yixun Lan wrote:
> There is a protential memory leak, as of_clk_del_provider is
> never called if of_clk_add_hw_provider has been executed.
> Fix this by using devm variant API.
> 
> Fixes: f8c11f79912d ("clk: meson: Add GXBB AO Clock and Reset controller driver")
> Suggested-by: Stephen Boyd <sboyd at kernel.org>
> Signed-off-by: Yixun Lan <yixun.lan at amlogic.com>
> ---
>  drivers/clk/meson/gxbb-aoclk.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/clk/meson/gxbb-aoclk.c b/drivers/clk/meson/gxbb-aoclk.c
> index 9ec23ae9a219..eebb580b9e0f 100644
> --- a/drivers/clk/meson/gxbb-aoclk.c
> +++ b/drivers/clk/meson/gxbb-aoclk.c
> @@ -191,7 +191,7 @@ static int gxbb_aoclkc_probe(struct platform_device *pdev)
>  	if (ret)
>  		return ret;
>  
> -	return of_clk_add_hw_provider(dev->of_node, of_clk_hw_onecell_get,
> +	return devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get,
>  			&gxbb_aoclk_onecell_data);
>  }
>  

Applied
Thx


From yixun.lan at amlogic.com  Fri Apr 27 05:33:42 2018
From: yixun.lan at amlogic.com (Yixun Lan)
Date: Fri, 27 Apr 2018 20:33:42 +0800
Subject: [PATCH v7 0/7] clk: meson-axg: Add AO Cloclk and Reset driver
In-Reply-To: <1524823154.4026.123.camel@baylibre.com>
References: <20180426084437.192394-1-yixun.lan@amlogic.com>
 <1524820841.4026.112.camel@baylibre.com>
 <fbd24a73-6793-76be-3ca5-04cbac5db198@amlogic.com>
 <1524823154.4026.123.camel@baylibre.com>
Message-ID: <ab754711-f727-133c-7bc3-a9f3243c2278@amlogic.com>

Hi Jerome:


On 04/27/2018 05:59 PM, Jerome Brunet wrote:
> On Fri, 2018-04-27 at 17:31 +0800, Yixun Lan wrote:
>> hi Jerome:
>>
>>
>> On 04/27/18 17:20, Jerome Brunet wrote:
>>> On Thu, 2018-04-26 at 16:44 +0800, Yixun Lan wrote:
>>>>   This patch try to add AO clock and Reset driver for Amlogic's
>>>> Meson-AXG SoC.
>>>>   Please note that patch 7 need to wait for the DTS changes[3] merged
>>>> into mainline first, otherwise it will break the serial console.
>>>>
>>>>  patch 2: factor the common code into a dedicated file
>>>>  patch 3-5: add the aoclk driver for AXG SoC
>>>>  patch 6-7: drop unnecessary clock flags
>>>>
>>>> changes since v6 at [7]: 
>>>>  - fix over 80 chars chechpatch error
>>>>  - add Philip's Ack on patch 5
>>>>  - drop extra end of newline
>>>>
>>>> changes since v5 at [6]: 
>>>>  - drop unnecessary header files
>>>>  - add 'axg_aoclk' prefix to clk driver, make them more consistent
>>>>  - add missing end new line..
>>>>
>>>> changes since v4 at [5]: 
>>>>  - fix return err
>>>>  - introduce CONFIG_COMMON_CLK_MESON_AO
>>>>  - format/style minor fix
>>>>
>>>> changes since v3 at [4]: 
>>>>  - add 'const' contraint to the read-only data
>>>>  - switch to devm_of_clk_add_hw_provider API
>>>>  - check return value of devm_reset_controller_register
>>>>
>>>> changes since v2 at [2]: 
>>>>  - rework meson_aoclkc_probe() which leverage the of_match_data
>>>>  - merge patch 5-6 into this series
>>>>  - seperate DTS patch, will send to Kevin Hilman independently
>>>>  
>>>> changes since v1 at [0]: 
>>>>  - rebase to clk-meson's branch 'next/drivers' [1]
>>>>  - fix license, update to BSD-3-Clause
>>>>  - drop un-used include header file
>>>>
>>>> [0] https://lkml.kernel.org/r/20180209070026.193879-1-yixun.lan at amlogic.com
>>>> [1] git://github.com/BayLibre/clk-meson.git branch: next-drivers
>>>> [2] https://lkml.kernel.org/r/20180323143816.200573-1-yixun.lan at amlogic.com
>>>> [3] https://lkml.kernel.org/r/20180326081809.49493-4-yixun.lan at amlogic.com
>>>> [4] https://lkml.kernel.org/r/20180328025050.221585-1-yixun.lan at amlogic.com
>>>> [5] https://lkml.kernel.org/r/20180408031938.153474-1-yixun.lan at amlogic.com
>>>> [6] https://lkml.kernel.org/r/20180409143749.71197-1-yixun.lan at amlogic.com
>>>> [7] https://lkml.kernel.org/r/20180419135426.155794-1-yixun.lan at amlogic.com
>>>
>>> Yixun,
>>>
>>> Your series looks mostly Ok to me, apart from the problem reported by Philipp.
>>>
>>> However, once applied, if the clkc ao controller is enabled, both gxl and axg
>>> fail to complete the boot. Could you please explain how this was tested ??
>>>
>>
>> isn't this caused by the patch 7?
>>  [PATCH v7 7/7] clk: meson: drop CLK_IGNORE_UNUSED flag
>>
>>
>> you need to also apply this DT patch which I've sent[1]:
>>  [PATCH v3 3/3] ARM64: dts: meson: fix clock source of the pclk for UART_AO
>>
>> could you exclude the patch 7 for now until Kevin merged the DT part?
>>
>> [1] https://lkml.kernel.org/r/20180328030130.240336-4-yixun.lan at amlogic.com
> 
> Looks to be the problem indeed. But it is still an issue with how your patchset
> in organized.
> 
> I can't merge this until Kevin merges the patch above, which he can't merge
> until there is the clkc_ao support in axg, which is given by this series.
> 
> 1# You should remove the axg part of the patch above. Kevin will be able to
> merge it w/o any dependencies. (BTW, the patch is broken for axg because 1) you
> did not include the dt-binding header for the clkc_ao in axg and 2) the clkc_ao
> does not exist at this stage)
> 2# I can then safely merge this series - w/o breaking gxbb and gxl.
> 3# Finally you'll have to make a DT change for the axg, enabling the clkc_ao and
> changes the uart clocks at the same time.
> 

  I didn't make myself clear in previous email

  I mean, could you merge patch 1-6, just exclude the patch 7
then kevin can merge the DT part (there are three patches) [1]
after the DT patches merged, then you can take this patch 7
This way, it won't break gxl or any other SoCs

  I'm sending patch 7 along with this series, it would be better if I
give a warning about it.

[1] https://lkml.kernel.org/r20180328030130.240336-1-yixun.lan at amlogic.com

>>
>>
>>> Not merging it until we get to the bottom of this.
>>>
>>>>
>>>>
>>>> Qiufang Dai (1):
>>>>   clk: meson-axg: Add AO Clock and Reset controller driver
>>>>
>>>> Yixun Lan (6):
>>>>   clk: meson: migrate to devm_of_clk_add_hw_provider API
>>>>   clk: meson: aoclk: refactor common code into dedicated file
>>>>   dt-bindings: clock: axg-aoclkc: New binding for Meson-AXG SoC
>>>>   dt-bindings: clock: reset: Add AXG AO Clock and Reset Bindings
>>>>   clk: meson: drop CLK_SET_RATE_PARENT flag
>>>>   clk: meson: drop CLK_IGNORE_UNUSED flag
>>>>
>>>>  .../bindings/clock/amlogic,gxbb-aoclkc.txt    |   1 +
>>>>  drivers/clk/meson/Kconfig                     |   8 +
>>>>  drivers/clk/meson/Makefile                    |   3 +-
>>>>  drivers/clk/meson/axg-aoclk.c                 | 163 ++++++++++++++++++
>>>>  drivers/clk/meson/axg-aoclk.h                 |  29 ++++
>>>>  drivers/clk/meson/gxbb-aoclk.c                |  95 ++++------
>>>>  drivers/clk/meson/gxbb-aoclk.h                |   5 +
>>>>  drivers/clk/meson/meson-aoclk.c               |  81 +++++++++
>>>>  drivers/clk/meson/meson-aoclk.h               |  34 ++++
>>>>  include/dt-bindings/clock/axg-aoclkc.h        |  26 +++
>>>>  include/dt-bindings/reset/axg-aoclkc.h        |  20 +++
>>>>  11 files changed, 401 insertions(+), 64 deletions(-)
>>>>  create mode 100644 drivers/clk/meson/axg-aoclk.c
>>>>  create mode 100644 drivers/clk/meson/axg-aoclk.h
>>>>  create mode 100644 drivers/clk/meson/meson-aoclk.c
>>>>  create mode 100644 drivers/clk/meson/meson-aoclk.h
>>>>  create mode 100644 include/dt-bindings/clock/axg-aoclkc.h
>>>>  create mode 100644 include/dt-bindings/reset/axg-aoclkc.h
>>>>
>>>
>>> .
>>>
>>
>>
> 
> .
> 



From linus.walleij at linaro.org  Fri Apr 27 06:33:32 2018
From: linus.walleij at linaro.org (Linus Walleij)
Date: Fri, 27 Apr 2018 15:33:32 +0200
Subject: [PATCH] pinctrl: meson-axg: fix the range of aobus bank
In-Reply-To: <20180417170824.18670-1-yixun.lan@amlogic.com>
References: <20180417170824.18670-1-yixun.lan@amlogic.com>
Message-ID: <CACRpkdaRvKs=ekpxxW_NuxP=d5ijUafOHbpSk8igMUckbDWwyw@mail.gmail.com>

On Tue, Apr 17, 2018 at 7:08 PM, Yixun Lan <yixun.lan at amlogic.com> wrote:

> The GPIOAO bank is range from GPIOAO_0 to GPIOAO_13.
>
> Fixes: 83c566806a68 ("pinctrl: meson-axg: Add new pinctrl driver for Meson AXG SoC")
> Reported-by: Xingyu Chen <xingyu.chen at amlogic.com>
> Signed-off-by: Yixun Lan <yixun.lan at amlogic.com>

Patch applied with Kevin's ACK.

Yours,
Linus Walleij


From khilman at baylibre.com  Fri Apr 27 11:49:35 2018
From: khilman at baylibre.com (Kevin Hilman)
Date: Fri, 27 Apr 2018 11:49:35 -0700
Subject: [PATCH v7 0/7] clk: meson-axg: Add AO Cloclk and Reset driver
In-Reply-To: <ab754711-f727-133c-7bc3-a9f3243c2278@amlogic.com> (Yixun Lan's
 message of "Fri, 27 Apr 2018 20:33:42 +0800")
References: <20180426084437.192394-1-yixun.lan@amlogic.com>
 <1524820841.4026.112.camel@baylibre.com>
 <fbd24a73-6793-76be-3ca5-04cbac5db198@amlogic.com>
 <1524823154.4026.123.camel@baylibre.com>
 <ab754711-f727-133c-7bc3-a9f3243c2278@amlogic.com>
Message-ID: <7hsh7g1o3k.fsf@baylibre.com>

Hi Yixun,

Yixun Lan <yixun.lan at amlogic.com> writes:

> On 04/27/2018 05:59 PM, Jerome Brunet wrote:

[...]

>> 
>> Looks to be the problem indeed. But it is still an issue with how your patchset
>> in organized.
>> 
>> I can't merge this until Kevin merges the patch above, which he can't merge
>> until there is the clkc_ao support in axg, which is given by this series.
>> 
>> 1# You should remove the axg part of the patch above. Kevin will be able to
>> merge it w/o any dependencies. (BTW, the patch is broken for axg because 1) you
>> did not include the dt-binding header for the clkc_ao in axg and 2) the clkc_ao
>> does not exist at this stage)
>> 2# I can then safely merge this series - w/o breaking gxbb and gxl.
>> 3# Finally you'll have to make a DT change for the axg, enabling the clkc_ao and
>> changes the uart clocks at the same time.
>> 
>
>   I didn't make myself clear in previous email
>
>   I mean, could you merge patch 1-6, just exclude the patch 7
> then kevin can merge the DT part (there are three patches) [1]
> after the DT patches merged, then you can take this patch 7
> This way, it won't break gxl or any other SoCs
>
>   I'm sending patch 7 along with this series, it would be better if I
> give a warning about it.

Your proposal requires extra work from a couple different maintainers to
track all the dependencies, and is very error prone.  Sometimes
maintainers may do this for you if they have time and are feeling
generous, but you will have much more success if you can ease the
process.

Jerome has provided lots of guidance throughout this series and just
above has provided you with a very good proposal above which minimizes
the dependencies, and provides the changes in the right order.

Please follow Jerome's suggestion,

Thanks,

Kevin


From khilman at baylibre.com  Fri Apr 27 12:03:26 2018
From: khilman at baylibre.com (Kevin Hilman)
Date: Fri, 27 Apr 2018 12:03:26 -0700
Subject: [PATCH v3 2/3] ARM64: dts: meson-axg: add an 32K alt aoclk
In-Reply-To: <20180328030130.240336-3-yixun.lan@amlogic.com> (Yixun Lan's
 message of "Wed, 28 Mar 2018 11:01:29 +0800")
References: <20180328030130.240336-1-yixun.lan@amlogic.com>
 <20180328030130.240336-3-yixun.lan@amlogic.com>
Message-ID: <7hmuxo1ngh.fsf@baylibre.com>

Yixun Lan <yixun.lan at amlogic.com> writes:

> The ao_clk81 in AO domain have two clock source,
> one from a 32K alt crystal we name it as ao_alt_clk,
> another is the clk81 signal from EE domain.
>
> Acked-by: Jerome Brunet <jbrunet at baylibre.com>
> Signed-off-by: Yixun Lan <yixun.lan at amlogic.com>

As this one is a stanadlone, I've applied it to v4.18/dt64,

Thanks,

Kevin

> ---
>  arch/arm64/boot/dts/amlogic/meson-axg.dtsi | 7 +++++++
>  1 file changed, 7 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
> index b0eff7d7f771..40ca49fb94a6 100644
> --- a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
> +++ b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
> @@ -108,6 +108,13 @@
>  		#clock-cells = <0>;
>  	};
>  
> +	ao_alt_xtal: ao_alt_xtal-clk {
> +		compatible = "fixed-clock";
> +		clock-frequency = <32000000>;
> +		clock-output-names = "ao_alt_xtal";
> +		#clock-cells = <0>;
> +	};
> +
>  	soc {
>  		compatible = "simple-bus";
>  		#address-cells = <2>;


From khilman at baylibre.com  Fri Apr 27 12:06:23 2018
From: khilman at baylibre.com (Kevin Hilman)
Date: Fri, 27 Apr 2018 12:06:23 -0700
Subject: [PATCH 0/2] Amlogic 32-bit multi_v7_defconfig updates
In-Reply-To: <20180422103805.1324-1-martin.blumenstingl@googlemail.com>
 (Martin Blumenstingl's message of "Sun, 22 Apr 2018 12:38:03 +0200")
References: <20180422103805.1324-1-martin.blumenstingl@googlemail.com>
Message-ID: <7hh8nw1nbk.fsf@baylibre.com>

Martin Blumenstingl <martin.blumenstingl at googlemail.com> writes:

> Some boards come with a PMU (system power controller, such as the Ricoh
> RN5T618). These need CONFIG_I2C_MESON built-in so the regulators can be
> set up during boot.
>
> Also enable CONFIG_PWM_MESON (as module) because some boards use it to
> dim the LED and/or generate the 32.768 kHz clock for the SDIO wifi chip.
>
> @Kevin: I assume that you'll take this through your tree, so no immediate
> action from the arm-soc maintainers needed, right?

Correct.

Merged into v4.18/defconfig,

Kevin


From khilman at baylibre.com  Fri Apr 27 12:08:10 2018
From: khilman at baylibre.com (Kevin Hilman)
Date: Fri, 27 Apr 2018 12:08:10 -0700
Subject: [PATCH 0/2] add the ARM PMU on Meson8 and Meson8b
In-Reply-To: <20180422104502.2942-1-martin.blumenstingl@googlemail.com>
 (Martin Blumenstingl's message of "Sun, 22 Apr 2018 12:45:00 +0200")
References: <20180422104502.2942-1-martin.blumenstingl@googlemail.com>
Message-ID: <7hd0yk1n8l.fsf@baylibre.com>

Martin Blumenstingl <martin.blumenstingl at googlemail.com> writes:

> Meson8 uses Cortex-A9 cores and Meson8b uses Cortex-A5 cores. As most
> Cortex-A5/A9 implementation these Amlogic SoCs also come with a
> built-in PMU for counting cpu and cache events like cache misses and
> hits.

Applied to v4.18/dt,

Thanks,

Kevin


From khilman at baylibre.com  Fri Apr 27 12:09:35 2018
From: khilman at baylibre.com (Kevin Hilman)
Date: Fri, 27 Apr 2018 12:09:35 -0700
Subject: [PATCH] ARM64: dts: meson-axg: enable AP6255 wifi module
In-Reply-To: <20180423145729.14368-1-yixun.lan@amlogic.com> (Yixun Lan's
 message of "Mon, 23 Apr 2018 14:57:29 +0000")
References: <20180423145729.14368-1-yixun.lan@amlogic.com>
Message-ID: <7h7eos1n68.fsf@baylibre.com>

Yixun Lan <yixun.lan at amlogic.com> writes:

> The Meson-AXG S400 board is shipped with AP6255 wifi module,
> which is actually using the brcmfmac 43455 driver.
>
> Signed-off-by: Yixun Lan <yixun.lan at amlogic.com>
> ---
>  .../arm64/boot/dts/amlogic/meson-axg-s400.dts | 44 ++++++++++++++++++-
>  1 file changed, 43 insertions(+), 1 deletion(-)
>
> diff --git a/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts b/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts
> index f67d4e47e641..b3e1bdca32bb 100644
> --- a/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts
> +++ b/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts
> @@ -51,7 +51,16 @@
>  
>  	sdio_pwrseq: sdio-pwrseq {
>  		compatible = "mmc-pwrseq-simple";
> -		reset-gpios = <&gpio GPIOX_6 GPIO_ACTIVE_LOW>;
> +		reset-gpios = <&gpio GPIOX_7 GPIO_ACTIVE_LOW>;

You didn't mention this GPIO change in the changelog.  Is it
intentional?

Kevin

> +		clocks = <&wifi32k>;
> +		clock-names = "ext_clock";
> +	};
> +
> +	wifi32k: wifi32k {
> +		compatible = "pwm-clock";
> +		#clock-cells = <0>;
> +		clock-frequency = <32768>;
> +		pwms = <&pwm_ab 0 30518 0>; /* PWM_A at 32.768KHz */
>  	};
>  };
>  
> @@ -86,6 +95,12 @@
>  	pinctrl-names = "default";
>  };
>  
> +&pwm_ab {
> +	status = "okay";
> +	pinctrl-0 = <&pwm_a_x20_pins>;
> +	pinctrl-names = "default";
> +};
> +
>  /* emmc storage */
>  &sd_emmc_c {
>  	status = "okay";
> @@ -105,3 +120,30 @@
>  	vmmc-supply = <&vcc_3v3>;
>  	vqmmc-supply = <&vddio_boot>;
>  };
> +
> +/* wifi module */
> +&sd_emmc_b {
> +	status = "okay";
> +	#address-cells = <1>;
> +	#size-cells = <0>;
> +
> +	pinctrl-0 = <&sdio_pins>;
> +	pinctrl-1 = <&sdio_clk_gate_pins>;
> +	pinctrl-names = "default", "clk-gate";
> +
> +	bus-width = <4>;
> +	cap-sd-highspeed;
> +	max-frequency = <100000000>;
> +	non-removable;
> +	disable-wp;
> +
> +	mmc-pwrseq = <&sdio_pwrseq>;
> +
> +	vmmc-supply = <&vddao_3v3>;
> +	vqmmc-supply = <&vddio_boot>;
> +
> +	brcmf: wifi at 1 {
> +		reg = <1>;
> +		compatible = "brcm,bcm4329-fmac";
> +	};
> +};


From khilman at baylibre.com  Fri Apr 27 12:15:39 2018
From: khilman at baylibre.com (Kevin Hilman)
Date: Fri, 27 Apr 2018 12:15:39 -0700
Subject: [PATCH] ARM64: dts: meson: disable sd-uhs modes on the
 libretech-cc
In-Reply-To: <20180426105046.14817-1-jbrunet@baylibre.com> (Jerome Brunet's
 message of "Thu, 26 Apr 2018 12:50:46 +0200")
References: <20180426105046.14817-1-jbrunet@baylibre.com>
Message-ID: <7hvacczcis.fsf@baylibre.com>

Jerome Brunet <jbrunet at baylibre.com> writes:

> There is a problem with the sd-uhs mode when doing a soft reboot.
> Switching back from 1.8v to 3.3v messes with the card, which no longer
> respond (timeout errors). According to the specification, we should
> perform a card reset (power cycling the card) but this is something we
> cannot control on this design.
>
> Then the only solution to restore the communication with the card is an
> "unplug-plug" which is not acceptable
>
> Until we find a solution, if any, disable the sd-uhs modes on this design.
> For the people using uhs at the moment, there will a performance drop as
> a result.
>
> Fixes: 3cde63ebc85c ("ARM64: dts: meson-gxl: libretech-cc: enable high speed modes")
> Signed-off-by: Jerome Brunet <jbrunet at baylibre.com>

Applied to v4.17/fixes, and adding a Cc to stable.

Thanks,

Kevin


From khilman at baylibre.com  Fri Apr 27 12:22:56 2018
From: khilman at baylibre.com (Kevin Hilman)
Date: Fri, 27 Apr 2018 12:22:56 -0700
Subject: [PATCH] ARM64: dts: meson: add MMC resets
In-Reply-To: <20180426104119.13659-1-jbrunet@baylibre.com> (Jerome Brunet's
 message of "Thu, 26 Apr 2018 12:41:19 +0200")
References: <20180426104119.13659-1-jbrunet@baylibre.com>
Message-ID: <7hpo2kzc6n.fsf@baylibre.com>

Jerome Brunet <jbrunet at baylibre.com> writes:

> Add reset lines to the mmc controllers of the meson gx and axg SoCs
>
> Signed-off-by: Jerome Brunet <jbrunet at baylibre.com>

Applied to v4.18/dt64,

Thanks,

Kevin


From khilman at baylibre.com  Fri Apr 27 12:11:32 2018
From: khilman at baylibre.com (Kevin Hilman)
Date: Fri, 27 Apr 2018 12:11:32 -0700
Subject: [PATCH 0/3] pinctrl: meson: add support for the Meson8m2 SoC
In-Reply-To: <20180422105330.4712-1-martin.blumenstingl@googlemail.com>
 (Martin Blumenstingl's message of "Sun, 22 Apr 2018 12:53:27 +0200")
References: <20180422105330.4712-1-martin.blumenstingl@googlemail.com>
Message-ID: <7h36zg1n2z.fsf@baylibre.com>

Martin Blumenstingl <martin.blumenstingl at googlemail.com> writes:

> The Meson8m2 SoC is a variant of Meson8 with some updates from Meson8b
> (such as the Gigabit capable DesignWare MAC).
> It is mostly pin compatible with Meson8, only 10 (existing) CBUS pins
> get an additional function. Four of these are Ethernet RXD2, RXD3, TXD2
> and TXD3 (GPIOZ_0..GPIOZ_3) which are required when the board uses an
> RGMII PHY. GPIODV_24 and GPIODV_25 provide "VGA" support on Meson8,
> which doesn't seem to be supported on Meson8m2 anymore.
> The other 4 are GPIOH_9 (reg 3 bit 19), CARD_4 (reg 8 bit 8),
> CARD_5 (reg 8 bit 7) and GPIOY_3 (reg 3 bit 11). Their function is
> currently unknown.
>
> The AOBUS pins seem to be identical on Meson8 and Meson8m2. However,
> since there's no official documentation I decided to add a new compatible
> string.

Reviewed-by: Kevin Hilman <khilman at baylibre.com>


From robh at kernel.org  Fri Apr 27 14:15:21 2018
From: robh at kernel.org (Rob Herring)
Date: Fri, 27 Apr 2018 16:15:21 -0500
Subject: [PATCH 1/3] dt-bindings: pinctrl: meson: add support for the
 Meson8m2 SoC
In-Reply-To: <20180422105330.4712-2-martin.blumenstingl@googlemail.com>
References: <20180422105330.4712-1-martin.blumenstingl@googlemail.com>
 <20180422105330.4712-2-martin.blumenstingl@googlemail.com>
Message-ID: <20180427211521.rfjtwx4zorf3ipde@rob-hp-laptop>

On Sun, Apr 22, 2018 at 12:53:28PM +0200, Martin Blumenstingl wrote:
> The Meson8m2 SoC is a variant of Meson8 with some updates from Meson8b
> (such as the Gigabit capable DesignWare MAC).
> It is mostly pin compatible with Meson8, only 10 (existing) CBUS pins
> get an additional function (four of these are Ethernet RXD2, RXD3, TXD2
> and TXD3 which are required when the board uses an RGMII PHY).
> The AOBUS pins seem to be identical on Meson8 and Meson8m2.
> 
> Signed-off-by: Martin Blumenstingl <martin.blumenstingl at googlemail.com>
> ---
>  Documentation/devicetree/bindings/pinctrl/meson,pinctrl.txt | 2 ++
>  1 file changed, 2 insertions(+)

Reviewed-by: Rob Herring <robh at kernel.org>


From robh at kernel.org  Fri Apr 27 14:53:17 2018
From: robh at kernel.org (Rob Herring)
Date: Fri, 27 Apr 2018 16:53:17 -0500
Subject: [PATCH] dt-bindings: meson-uart: DT fix
 s/clocks-names/clock-names/
In-Reply-To: <1524468760-22912-1-git-send-email-geert+renesas@glider.be>
References: <1524468760-22912-1-git-send-email-geert+renesas@glider.be>
Message-ID: <20180427215317.u4ueypn5vhm5xmcw@rob-hp-laptop>

On Mon, Apr 23, 2018 at 09:32:40AM +0200, Geert Uytterhoeven wrote:
> Signed-off-by: Geert Uytterhoeven <geert+renesas at glider.be>
> ---
>  Documentation/devicetree/bindings/serial/amlogic,meson-uart.txt | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)

As this is only binding change, I've applied it.

Rob


From yixun.lan at amlogic.com  Fri Apr 27 18:50:06 2018
From: yixun.lan at amlogic.com (Yixun Lan)
Date: Sat, 28 Apr 2018 09:50:06 +0800
Subject: [PATCH v7 0/7] clk: meson-axg: Add AO Cloclk and Reset driver
In-Reply-To: <7hsh7g1o3k.fsf@baylibre.com>
References: <20180426084437.192394-1-yixun.lan@amlogic.com>
 <1524820841.4026.112.camel@baylibre.com>
 <fbd24a73-6793-76be-3ca5-04cbac5db198@amlogic.com>
 <1524823154.4026.123.camel@baylibre.com>
 <ab754711-f727-133c-7bc3-a9f3243c2278@amlogic.com>
 <7hsh7g1o3k.fsf@baylibre.com>
Message-ID: <973672c6-1cc1-7f38-ac30-263fd5f0b69c@amlogic.com>

Hi Kevin

On 04/28/18 02:49, Kevin Hilman wrote:
> Hi Yixun,
> 
> Yixun Lan <yixun.lan at amlogic.com> writes:
> 
>> On 04/27/2018 05:59 PM, Jerome Brunet wrote:
> 
> [...]
> 
>>>
>>> Looks to be the problem indeed. But it is still an issue with how your patchset
>>> in organized.
>>>
>>> I can't merge this until Kevin merges the patch above, which he can't merge
>>> until there is the clkc_ao support in axg, which is given by this series.
>>>
>>> 1# You should remove the axg part of the patch above. Kevin will be able to
>>> merge it w/o any dependencies. (BTW, the patch is broken for axg because 1) you
>>> did not include the dt-binding header for the clkc_ao in axg and 2) the clkc_ao
>>> does not exist at this stage)
>>> 2# I can then safely merge this series - w/o breaking gxbb and gxl.
>>> 3# Finally you'll have to make a DT change for the axg, enabling the clkc_ao and
>>> changes the uart clocks at the same time.
>>>
>>
>>   I didn't make myself clear in previous email
>>
>>   I mean, could you merge patch 1-6, just exclude the patch 7
>> then kevin can merge the DT part (there are three patches) [1]
>> after the DT patches merged, then you can take this patch 7
>> This way, it won't break gxl or any other SoCs
>>

>>   I'm sending patch 7 along with this series, it would be better if I
>> give a warning about it.
> 
> Your proposal requires extra work from a couple different maintainers to
> track all the dependencies, and is very error prone.  Sometimes
> maintainers may do this for you if they have time and are feeling
> generous, but you will have much more success if you can ease the
> process.
> 
Indeed

 I've actually put a note in the cover letter to highlight special
attention needed for patch 7, but turns out rely on maintainers to
handle the dependencies isn't a wise idea
 Lesson has been learned here, and I'll handle dependencies myself next
time.


> Jerome has provided lots of guidance throughout this series and just
> above has provided you with a very good proposal above which minimizes
> the dependencies, and provides the changes in the right order.
> 
> Please follow Jerome's suggestion,
> 
as already replied in my previous email, again here is my approach

a) I'll send patch 2-6, just leave out patch 7 for now, and as patch 1
is already accepted.. this way it won't break gxbb/gxl (the OLD SoC)
b) will pin you to require DT patch merged or re-send if necessary (as
till now the clkao driver is merged)
c) send out the patch 7 for UART AO clock fix

this is exactly what Jerome suggested..

Thank you

Yixun



From yixun.lan at amlogic.com  Fri Apr 27 18:56:07 2018
From: yixun.lan at amlogic.com (Yixun Lan)
Date: Sat, 28 Apr 2018 09:56:07 +0800
Subject: [PATCH] ARM64: dts: meson-axg: enable AP6255 wifi module
In-Reply-To: <7h7eos1n68.fsf@baylibre.com>
References: <20180423145729.14368-1-yixun.lan@amlogic.com>
 <7h7eos1n68.fsf@baylibre.com>
Message-ID: <30de15b8-4cc4-7f97-d134-7af75cb6ace1@amlogic.com>

On 04/28/18 03:09, Kevin Hilman wrote:
> Yixun Lan <yixun.lan at amlogic.com> writes:
> 
>> The Meson-AXG S400 board is shipped with AP6255 wifi module,
>> which is actually using the brcmfmac 43455 driver.
>>
>> Signed-off-by: Yixun Lan <yixun.lan at amlogic.com>
>> ---
>>  .../arm64/boot/dts/amlogic/meson-axg-s400.dts | 44 ++++++++++++++++++-
>>  1 file changed, 43 insertions(+), 1 deletion(-)
>>
>> diff --git a/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts b/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts
>> index f67d4e47e641..b3e1bdca32bb 100644
>> --- a/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts
>> +++ b/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts
>> @@ -51,7 +51,16 @@
>>  
>>  	sdio_pwrseq: sdio-pwrseq {
>>  		compatible = "mmc-pwrseq-simple";
>> -		reset-gpios = <&gpio GPIOX_6 GPIO_ACTIVE_LOW>;
>> +		reset-gpios = <&gpio GPIOX_7 GPIO_ACTIVE_LOW>;
> 
> You didn't mention this GPIO change in the changelog.  Is it
> intentional?

Yes, the 'sdio_pwrseq' is used by wifi driver till now
previous the reset-gpio is wrongly configured (copy & paste error),
according to the schematics, it's GPIOX_7 which need to be fixed here.

to be clean, in s400 board
 GPIOX_6 is WIFI_WAKE_HOST pin
 GPIOX_7 is WIFI_PWREN pin

do you want me to put a note into the commit message? and resend this patch?

Thanks


> 
>> +		clocks = <&wifi32k>;
>> +		clock-names = "ext_clock";
>> +	};
>> +
>> +	wifi32k: wifi32k {
>> +		compatible = "pwm-clock";
>> +		#clock-cells = <0>;
>> +		clock-frequency = <32768>;
>> +		pwms = <&pwm_ab 0 30518 0>; /* PWM_A at 32.768KHz */
>>  	};
>>  };
>>  
>> @@ -86,6 +95,12 @@
>>  	pinctrl-names = "default";
>>  };
>>  
>> +&pwm_ab {
>> +	status = "okay";
>> +	pinctrl-0 = <&pwm_a_x20_pins>;
>> +	pinctrl-names = "default";
>> +};
>> +
>>  /* emmc storage */
>>  &sd_emmc_c {
>>  	status = "okay";
>> @@ -105,3 +120,30 @@
>>  	vmmc-supply = <&vcc_3v3>;
>>  	vqmmc-supply = <&vddio_boot>;
>>  };
>> +
>> +/* wifi module */
>> +&sd_emmc_b {
>> +	status = "okay";
>> +	#address-cells = <1>;
>> +	#size-cells = <0>;
>> +
>> +	pinctrl-0 = <&sdio_pins>;
>> +	pinctrl-1 = <&sdio_clk_gate_pins>;
>> +	pinctrl-names = "default", "clk-gate";
>> +
>> +	bus-width = <4>;
>> +	cap-sd-highspeed;
>> +	max-frequency = <100000000>;
>> +	non-removable;
>> +	disable-wp;
>> +
>> +	mmc-pwrseq = <&sdio_pwrseq>;
>> +
>> +	vmmc-supply = <&vddao_3v3>;
>> +	vqmmc-supply = <&vddio_boot>;
>> +
>> +	brcmf: wifi at 1 {
>> +		reg = <1>;
>> +		compatible = "brcm,bcm4329-fmac";
>> +	};
>> +};
> 
> .
> 



From yixun.lan at amlogic.com  Sat Apr 28 03:21:09 2018
From: yixun.lan at amlogic.com (Yixun Lan)
Date: Sat, 28 Apr 2018 10:21:09 +0000
Subject: [PATCH v2 0/2] net: stmmac: dwmac-meson: 100M phy mode support for
 AXG SoC
Message-ID: <20180428102111.18384-1-yixun.lan@amlogic.com>

Due to the dwmac glue layer register changed, we need to 
introduce a new compatible name for the Meson-AXG SoC
to support for the RMII 100M ethernet PHY.

Change since v1 at [1]:
  - implement set_phy_mode() for each SoC

[1] https://lkml.kernel.org/r/20180426160508.29380-1-yixun.lan at amlogic.com

Yixun Lan (2):
  dt-bindings: net: meson-dwmac: new compatible name for AXG SoC
  net: stmmac: dwmac-meson: extend phy mode setting

 .../devicetree/bindings/net/meson-dwmac.txt   |   1 +
 .../ethernet/stmicro/stmmac/dwmac-meson8b.c   | 120 +++++++++++++++---
 2 files changed, 105 insertions(+), 16 deletions(-)

-- 
2.17.0



From yixun.lan at amlogic.com  Sat Apr 28 03:21:10 2018
From: yixun.lan at amlogic.com (Yixun Lan)
Date: Sat, 28 Apr 2018 10:21:10 +0000
Subject: [PATCH v2 1/2] dt-bindings: net: meson-dwmac: new compatible name for
 AXG SoC
In-Reply-To: <20180428102111.18384-1-yixun.lan@amlogic.com>
References: <20180428102111.18384-1-yixun.lan@amlogic.com>
Message-ID: <20180428102111.18384-2-yixun.lan@amlogic.com>

We need to introduce a new compatible name for the Meson-AXG SoC
in order to support the RMII 100M ethernet PHY, since the PRG_ETH0
register of the dwmac glue layer is changed from previous old SoC.

Signed-off-by: Yixun Lan <yixun.lan at amlogic.com>
---
 Documentation/devicetree/bindings/net/meson-dwmac.txt | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/net/meson-dwmac.txt b/Documentation/devicetree/bindings/net/meson-dwmac.txt
index 61cada22ae6c..1321bb194ed9 100644
--- a/Documentation/devicetree/bindings/net/meson-dwmac.txt
+++ b/Documentation/devicetree/bindings/net/meson-dwmac.txt
@@ -11,6 +11,7 @@ Required properties on all platforms:
 			- "amlogic,meson8b-dwmac"
 			- "amlogic,meson8m2-dwmac"
 			- "amlogic,meson-gxbb-dwmac"
+			- "amlogic,meson-axg-dwmac"
 		Additionally "snps,dwmac" and any applicable more
 		detailed version number described in net/stmmac.txt
 		should be used.
-- 
2.17.0



From yixun.lan at amlogic.com  Sat Apr 28 03:21:11 2018
From: yixun.lan at amlogic.com (Yixun Lan)
Date: Sat, 28 Apr 2018 10:21:11 +0000
Subject: [PATCH v2 2/2] net: stmmac: dwmac-meson: extend phy mode setting
In-Reply-To: <20180428102111.18384-1-yixun.lan@amlogic.com>
References: <20180428102111.18384-1-yixun.lan@amlogic.com>
Message-ID: <20180428102111.18384-3-yixun.lan@amlogic.com>

  In the Meson-AXG SoC, the phy mode setting of PRG_ETH0 in the glue layer
is extended from bit[0] to bit[2:0].
  There is no problem if we configure it to the RGMII 1000M PHY mode,
since the register setting is coincidentally compatible with previous one,
but for the RMII 100M PHY mode, the configuration need to be changed to
value - b100.
  This patch was verified with a RTL8201F 100M ethernet PHY.

Signed-off-by: Yixun Lan <yixun.lan at amlogic.com>
---
 .../ethernet/stmicro/stmmac/dwmac-meson8b.c   | 120 +++++++++++++++---
 1 file changed, 104 insertions(+), 16 deletions(-)

diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c
index 7cb794094a70..4ff231df7322 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c
@@ -18,6 +18,7 @@
 #include <linux/io.h>
 #include <linux/ioport.h>
 #include <linux/module.h>
+#include <linux/of_device.h>
 #include <linux/of_net.h>
 #include <linux/mfd/syscon.h>
 #include <linux/platform_device.h>
@@ -29,6 +30,10 @@
 
 #define PRG_ETH0_RGMII_MODE		BIT(0)
 
+#define PRG_ETH0_EXT_PHY_MODE_MASK	GENMASK(2, 0)
+#define PRG_ETH0_EXT_RGMII_MODE		1
+#define PRG_ETH0_EXT_RMII_MODE		4
+
 /* mux to choose between fclk_div2 (bit unset) and mpll2 (bit set) */
 #define PRG_ETH0_CLK_M250_SEL_SHIFT	4
 #define PRG_ETH0_CLK_M250_SEL_MASK	GENMASK(4, 4)
@@ -47,12 +52,20 @@
 
 #define MUX_CLK_NUM_PARENTS		2
 
+struct meson8b_dwmac;
+
+struct meson8b_dwmac_data {
+	int (*set_phy_mode)(struct meson8b_dwmac *dwmac);
+};
+
 struct meson8b_dwmac {
-	struct device		*dev;
-	void __iomem		*regs;
-	phy_interface_t		phy_mode;
-	struct clk		*rgmii_tx_clk;
-	u32			tx_delay_ns;
+	struct device			*dev;
+	void __iomem			*regs;
+
+	const struct meson8b_dwmac_data	*data;
+	phy_interface_t			phy_mode;
+	struct clk			*rgmii_tx_clk;
+	u32				tx_delay_ns;
 };
 
 struct meson8b_dwmac_clk_configs {
@@ -171,6 +184,59 @@ static int meson8b_init_rgmii_tx_clk(struct meson8b_dwmac *dwmac)
 	return 0;
 }
 
+static int meson8b_set_phy_mode(struct meson8b_dwmac *dwmac)
+{
+	switch (dwmac->phy_mode) {
+	case PHY_INTERFACE_MODE_RGMII:
+	case PHY_INTERFACE_MODE_RGMII_RXID:
+	case PHY_INTERFACE_MODE_RGMII_ID:
+	case PHY_INTERFACE_MODE_RGMII_TXID:
+		/* enable RGMII mode */
+		meson8b_dwmac_mask_bits(dwmac, PRG_ETH0,
+					PRG_ETH0_RGMII_MODE,
+					PRG_ETH0_RGMII_MODE);
+		break;
+	case PHY_INTERFACE_MODE_RMII:
+		/* disable RGMII mode -> enables RMII mode */
+		meson8b_dwmac_mask_bits(dwmac, PRG_ETH0,
+					PRG_ETH0_RGMII_MODE, 0);
+		break;
+	default:
+		dev_err(dwmac->dev, "fail to set phy-mode %s\n",
+			phy_modes(dwmac->phy_mode));
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+static int meson_axg_set_phy_mode(struct meson8b_dwmac *dwmac)
+{
+	switch (dwmac->phy_mode) {
+	case PHY_INTERFACE_MODE_RGMII:
+	case PHY_INTERFACE_MODE_RGMII_RXID:
+	case PHY_INTERFACE_MODE_RGMII_ID:
+	case PHY_INTERFACE_MODE_RGMII_TXID:
+		/* enable RGMII mode */
+		meson8b_dwmac_mask_bits(dwmac, PRG_ETH0,
+					PRG_ETH0_EXT_PHY_MODE_MASK,
+					PRG_ETH0_EXT_RGMII_MODE);
+		break;
+	case PHY_INTERFACE_MODE_RMII:
+		/* disable RGMII mode -> enables RMII mode */
+		meson8b_dwmac_mask_bits(dwmac, PRG_ETH0,
+					PRG_ETH0_EXT_PHY_MODE_MASK,
+					PRG_ETH0_EXT_RMII_MODE);
+		break;
+	default:
+		dev_err(dwmac->dev, "fail to set phy-mode %s\n",
+			phy_modes(dwmac->phy_mode));
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
 static int meson8b_init_prg_eth(struct meson8b_dwmac *dwmac)
 {
 	int ret;
@@ -188,10 +254,6 @@ static int meson8b_init_prg_eth(struct meson8b_dwmac *dwmac)
 
 	case PHY_INTERFACE_MODE_RGMII_ID:
 	case PHY_INTERFACE_MODE_RGMII_TXID:
-		/* enable RGMII mode */
-		meson8b_dwmac_mask_bits(dwmac, PRG_ETH0, PRG_ETH0_RGMII_MODE,
-					PRG_ETH0_RGMII_MODE);
-
 		/* only relevant for RMII mode -> disable in RGMII mode */
 		meson8b_dwmac_mask_bits(dwmac, PRG_ETH0,
 					PRG_ETH0_INVERTED_RMII_CLK, 0);
@@ -224,10 +286,6 @@ static int meson8b_init_prg_eth(struct meson8b_dwmac *dwmac)
 		break;
 
 	case PHY_INTERFACE_MODE_RMII:
-		/* disable RGMII mode -> enables RMII mode */
-		meson8b_dwmac_mask_bits(dwmac, PRG_ETH0, PRG_ETH0_RGMII_MODE,
-					0);
-
 		/* invert internal clk_rmii_i to generate 25/2.5 tx_rx_clk */
 		meson8b_dwmac_mask_bits(dwmac, PRG_ETH0,
 					PRG_ETH0_INVERTED_RMII_CLK,
@@ -274,6 +332,11 @@ static int meson8b_dwmac_probe(struct platform_device *pdev)
 		goto err_remove_config_dt;
 	}
 
+	dwmac->data = (const struct meson8b_dwmac_data *)
+		of_device_get_match_data(&pdev->dev);
+	if (!dwmac->data)
+		return -EINVAL;
+
 	res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
 	dwmac->regs = devm_ioremap_resource(&pdev->dev, res);
 	if (IS_ERR(dwmac->regs)) {
@@ -298,6 +361,10 @@ static int meson8b_dwmac_probe(struct platform_device *pdev)
 	if (ret)
 		goto err_remove_config_dt;
 
+	ret = dwmac->data->set_phy_mode(dwmac);
+	if (ret)
+		goto err_remove_config_dt;
+
 	ret = meson8b_init_prg_eth(dwmac);
 	if (ret)
 		goto err_remove_config_dt;
@@ -316,10 +383,31 @@ static int meson8b_dwmac_probe(struct platform_device *pdev)
 	return ret;
 }
 
+static const struct meson8b_dwmac_data meson8b_dwmac_data = {
+	.set_phy_mode = meson8b_set_phy_mode,
+};
+
+static const struct meson8b_dwmac_data meson_axg_dwmac_data = {
+	.set_phy_mode = meson_axg_set_phy_mode,
+};
+
 static const struct of_device_id meson8b_dwmac_match[] = {
-	{ .compatible = "amlogic,meson8b-dwmac" },
-	{ .compatible = "amlogic,meson8m2-dwmac" },
-	{ .compatible = "amlogic,meson-gxbb-dwmac" },
+	{
+		.compatible = "amlogic,meson8b-dwmac",
+		.data = &meson8b_dwmac_data,
+	},
+	{
+		.compatible = "amlogic,meson8m2-dwmac",
+		.data = &meson8b_dwmac_data,
+	},
+	{
+		.compatible = "amlogic,meson-gxbb-dwmac",
+		.data = &meson8b_dwmac_data,
+	},
+	{
+		.compatible = "amlogic,meson-axg-dwmac",
+		.data = &meson_axg_dwmac_data,
+	},
 	{ }
 };
 MODULE_DEVICE_TABLE(of, meson8b_dwmac_match);
-- 
2.17.0



From martin.blumenstingl at googlemail.com  Sat Apr 28 06:23:16 2018
From: martin.blumenstingl at googlemail.com (Martin Blumenstingl)
Date: Sat, 28 Apr 2018 15:23:16 +0200
Subject: [PATCH meson-clk-next] clk: meson: meson8b: enable
 CLK_MESON_MPLL_ROUND_CLOSEST for all MPLLs
Message-ID: <20180428132316.20108-1-martin.blumenstingl@googlemail.com>

Until recently the clk-mpll implementation always used
DIV_ROUND_UP_ULL(). However, since commit 1b0e500dc606e9 ("clk: meson:
mpll: add round closest support") the default was changed to round down
the SDM divisor.
This broke RGMII Ethernet on Meson8b (which uses MPLL2 as RGMII TX
clock). With the old implementation the MPLL2 output was 249999701Hz,
but with "round closest" disabled the output is 212500000Hz.

Enabling CLK_MESON_MPLL_ROUND_CLOSEST for all MPLL2 clocks on Meson8b
fixes this because we now get the same 249999701Hz from MPLL2 as before.

Fixes: 1b0e500dc606e9 ("clk: meson: mpll: add round closest support")
Signed-off-by: Martin Blumenstingl <martin.blumenstingl at googlemail.com>
---
 drivers/clk/meson/meson8b.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/clk/meson/meson8b.c b/drivers/clk/meson/meson8b.c
index d0524ec71aad..2639a892a5d4 100644
--- a/drivers/clk/meson/meson8b.c
+++ b/drivers/clk/meson/meson8b.c
@@ -382,6 +382,7 @@ static struct clk_regmap meson8b_mpll0_div = {
 			.width   = 1,
 		},
 		.lock = &meson_clk_lock,
+		.flags = CLK_MESON_MPLL_ROUND_CLOSEST,
 	},
 	.hw.init = &(struct clk_init_data){
 		.name = "mpll0_div",
@@ -423,6 +424,7 @@ static struct clk_regmap meson8b_mpll1_div = {
 			.width   = 9,
 		},
 		.lock = &meson_clk_lock,
+		.flags = CLK_MESON_MPLL_ROUND_CLOSEST,
 	},
 	.hw.init = &(struct clk_init_data){
 		.name = "mpll1_div",
@@ -464,6 +466,7 @@ static struct clk_regmap meson8b_mpll2_div = {
 			.width   = 9,
 		},
 		.lock = &meson_clk_lock,
+		.flags = CLK_MESON_MPLL_ROUND_CLOSEST,
 	},
 	.hw.init = &(struct clk_init_data){
 		.name = "mpll2_div",
-- 
2.17.0



From jbrunet at baylibre.com  Sat Apr 28 08:01:34 2018
From: jbrunet at baylibre.com (Jerome Brunet)
Date: Sat, 28 Apr 2018 17:01:34 +0200
Subject: [PATCH meson-clk-next] clk: meson: meson8b: enable
 CLK_MESON_MPLL_ROUND_CLOSEST for all MPLLs
In-Reply-To: <20180428132316.20108-1-martin.blumenstingl@googlemail.com>
References: <20180428132316.20108-1-martin.blumenstingl@googlemail.com>
Message-ID: <1524927694.28715.2.camel@baylibre.com>

On Sat, 2018-04-28 at 15:23 +0200, Martin Blumenstingl wrote:
> Until recently the clk-mpll implementation always used
> DIV_ROUND_UP_ULL(). However, since commit 1b0e500dc606e9 ("clk: meson:
> mpll: add round closest support") the default was changed to round down
> the SDM divisor.
> This broke RGMII Ethernet on Meson8b (which uses MPLL2 as RGMII TX
> clock). With the old implementation the MPLL2 output was 249999701Hz,
> but with "round closest" disabled the output is 212500000Hz.

> 
> Enabling CLK_MESON_MPLL_ROUND_CLOSEST for all MPLL2 clocks on Meson8b
> fixes this because we now get the same 249999701Hz from MPLL2 as before.

It should either be rounding up or down, not down or 'more down'
I guess I need to revisit this series. In the mean time, I'll drop it.
Thanks for reporting the issue

> 
> Fixes: 1b0e500dc606e9 ("clk: meson: mpll: add round closest support")
> Signed-off-by: Martin Blumenstingl <martin.blumenstingl at googlemail.com>
> ---
>  drivers/clk/meson/meson8b.c | 3 +++
>  1 file changed, 3 insertions(+)
> 
> diff --git a/drivers/clk/meson/meson8b.c b/drivers/clk/meson/meson8b.c
> index d0524ec71aad..2639a892a5d4 100644
> --- a/drivers/clk/meson/meson8b.c
> +++ b/drivers/clk/meson/meson8b.c
> @@ -382,6 +382,7 @@ static struct clk_regmap meson8b_mpll0_div = {
>  			.width   = 1,
>  		},
>  		.lock = &meson_clk_lock,
> +		.flags = CLK_MESON_MPLL_ROUND_CLOSEST,
>  	},
>  	.hw.init = &(struct clk_init_data){
>  		.name = "mpll0_div",
> @@ -423,6 +424,7 @@ static struct clk_regmap meson8b_mpll1_div = {
>  			.width   = 9,
>  		},
>  		.lock = &meson_clk_lock,
> +		.flags = CLK_MESON_MPLL_ROUND_CLOSEST,
>  	},
>  	.hw.init = &(struct clk_init_data){
>  		.name = "mpll1_div",
> @@ -464,6 +466,7 @@ static struct clk_regmap meson8b_mpll2_div = {
>  			.width   = 9,
>  		},
>  		.lock = &meson_clk_lock,
> +		.flags = CLK_MESON_MPLL_ROUND_CLOSEST,
>  	},
>  	.hw.init = &(struct clk_init_data){
>  		.name = "mpll2_div",



From martin.blumenstingl at googlemail.com  Sat Apr 28 14:25:21 2018
From: martin.blumenstingl at googlemail.com (Martin Blumenstingl)
Date: Sat, 28 Apr 2018 23:25:21 +0200
Subject: [PATCH] pwm: meson: fix allocation of meson_pwm_channel array
Message-ID: <20180428212521.29328-1-martin.blumenstingl@googlemail.com>

Using the pwm-meson driver on the 32-bit SoCs causes memory corruption.
The result are some hard-to-explain errors, for example
devm_clk_register crashes with a NULL dereference somewhere deep in the
common clock framework code.
In some cases the kernel even refused to boot when any of the PWM
controllers were enables on Meson8b.

The root cause seems to be an incorrect memory size in the devm_kcalloc
call in meson_pwm_probe. The code allocates an array of meson_pwm_channel
structs, but the size given is the size of the meson_pwm struct (which
seems like a small copy-and-paste error, as meson_pwm is allocated a few
lines above).
Even with this typo the code seemed to work fine on the 64-bit GX SoCs
(maybe due to the structs having the same size in the compiled result,
but I haven't checked this further).

Fixes: 211ed630753d2f ("pwm: Add support for Meson PWM Controller")
Signed-off-by: Martin Blumenstingl <martin.blumenstingl at googlemail.com>
---
 drivers/pwm/pwm-meson.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/pwm/pwm-meson.c b/drivers/pwm/pwm-meson.c
index 0767deba8e62..822860b4801a 100644
--- a/drivers/pwm/pwm-meson.c
+++ b/drivers/pwm/pwm-meson.c
@@ -541,8 +541,8 @@ static int meson_pwm_probe(struct platform_device *pdev)
 	meson->data = of_device_get_match_data(&pdev->dev);
 	meson->inverter_mask = BIT(meson->chip.npwm) - 1;
 
-	channels = devm_kcalloc(&pdev->dev, meson->chip.npwm, sizeof(*meson),
-				GFP_KERNEL);
+	channels = devm_kcalloc(&pdev->dev, meson->chip.npwm,
+				sizeof(*channels), GFP_KERNEL);
 	if (!channels)
 		return -ENOMEM;
 
-- 
2.17.0



From khoroshilov at ispras.ru  Sat Apr 28 15:46:23 2018
From: khoroshilov at ispras.ru (Alexey Khoroshilov)
Date: Sun, 29 Apr 2018 01:46:23 +0300
Subject: [PATCH v2] spi: meson-spicc: Fix error handling in meson_spicc_probe()
In-Reply-To: <a2a9cde3-5192-ce05-cc5c-d0191f0e811a@baylibre.com>
Message-ID: <1524955583-22760-1-git-send-email-khoroshilov@ispras.ru>

If devm_spi_register_master() fails in meson_spicc_probe(),
spicc->core is left undisabled. The patch fixes that.

Found by Linux Driver Verification project (linuxtesting.org).

Signed-off-by: Alexey Khoroshilov <khoroshilov at ispras.ru>
Reviewed-by: Neil Armstrong <narmstrong at baylibre.com>
---
v2: Fix subject as Neil Armstrong noted.

 drivers/spi/spi-meson-spicc.c | 11 ++++++++---
 1 file changed, 8 insertions(+), 3 deletions(-)

diff --git a/drivers/spi/spi-meson-spicc.c b/drivers/spi/spi-meson-spicc.c
index 5c82910e3480..7fe4488ace57 100644
--- a/drivers/spi/spi-meson-spicc.c
+++ b/drivers/spi/spi-meson-spicc.c
@@ -574,10 +574,15 @@ static int meson_spicc_probe(struct platform_device *pdev)
 		master->max_speed_hz = rate >> 2;
 
 	ret = devm_spi_register_master(&pdev->dev, master);
-	if (!ret)
-		return 0;
+	if (ret) {
+		dev_err(&pdev->dev, "spi master registration failed\n");
+		goto out_clk;
+	}
 
-	dev_err(&pdev->dev, "spi master registration failed\n");
+	return 0;
+
+out_clk:
+	clk_disable_unprepare(spicc->core);
 
 out_master:
 	spi_master_put(master);
-- 
2.7.4



From thierry.reding at gmail.com  Mon Apr 30 01:34:47 2018
From: thierry.reding at gmail.com (Thierry Reding)
Date: Mon, 30 Apr 2018 10:34:47 +0200
Subject: [PATCH] pwm: meson: fix allocation of meson_pwm_channel array
In-Reply-To: <20180428212521.29328-1-martin.blumenstingl@googlemail.com>
References: <20180428212521.29328-1-martin.blumenstingl@googlemail.com>
Message-ID: <20180430083447.GJ2484@ulmo>

On Sat, Apr 28, 2018 at 11:25:21PM +0200, Martin Blumenstingl wrote:
> Using the pwm-meson driver on the 32-bit SoCs causes memory corruption.
> The result are some hard-to-explain errors, for example
> devm_clk_register crashes with a NULL dereference somewhere deep in the
> common clock framework code.
> In some cases the kernel even refused to boot when any of the PWM
> controllers were enables on Meson8b.
> 
> The root cause seems to be an incorrect memory size in the devm_kcalloc
> call in meson_pwm_probe. The code allocates an array of meson_pwm_channel
> structs, but the size given is the size of the meson_pwm struct (which
> seems like a small copy-and-paste error, as meson_pwm is allocated a few
> lines above).
> Even with this typo the code seemed to work fine on the 64-bit GX SoCs
> (maybe due to the structs having the same size in the compiled result,
> but I haven't checked this further).
> 
> Fixes: 211ed630753d2f ("pwm: Add support for Meson PWM Controller")
> Signed-off-by: Martin Blumenstingl <martin.blumenstingl at googlemail.com>
> ---
>  drivers/pwm/pwm-meson.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)

Applied, thanks.

Thierry
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From linus.walleij at linaro.org  Mon Apr 30 01:52:46 2018
From: linus.walleij at linaro.org (Linus Walleij)
Date: Mon, 30 Apr 2018 10:52:46 +0200
Subject: [PATCH 1/3] dt-bindings: pinctrl: meson: add support for the
 Meson8m2 SoC
In-Reply-To: <20180422105330.4712-2-martin.blumenstingl@googlemail.com>
References: <20180422105330.4712-1-martin.blumenstingl@googlemail.com>
 <20180422105330.4712-2-martin.blumenstingl@googlemail.com>
Message-ID: <CACRpkdZt7kj0FBRfBqgmxYVMt4yiBPyVsvVdgyzgJGiiErdB=A@mail.gmail.com>

On Sun, Apr 22, 2018 at 12:53 PM, Martin Blumenstingl
<martin.blumenstingl at googlemail.com> wrote:

> The Meson8m2 SoC is a variant of Meson8 with some updates from Meson8b
> (such as the Gigabit capable DesignWare MAC).
> It is mostly pin compatible with Meson8, only 10 (existing) CBUS pins
> get an additional function (four of these are Ethernet RXD2, RXD3, TXD2
> and TXD3 which are required when the board uses an RGMII PHY).
> The AOBUS pins seem to be identical on Meson8 and Meson8m2.
>
> Signed-off-by: Martin Blumenstingl <martin.blumenstingl at googlemail.com>

Patch applied with Rob's and Kevin's ACKs.

Yours,
Linus Walleij


From linus.walleij at linaro.org  Mon Apr 30 01:54:20 2018
From: linus.walleij at linaro.org (Linus Walleij)
Date: Mon, 30 Apr 2018 10:54:20 +0200
Subject: [PATCH 2/3] pinctrl: meson: meson8: add support for the Meson8m2
 SoC
In-Reply-To: <20180422105330.4712-3-martin.blumenstingl@googlemail.com>
References: <20180422105330.4712-1-martin.blumenstingl@googlemail.com>
 <20180422105330.4712-3-martin.blumenstingl@googlemail.com>
Message-ID: <CACRpkdb+tS_7B+k+Fir71EPavu-1iZOhYJb3aQ2xr2MMtfUwzQ@mail.gmail.com>

On Sun, Apr 22, 2018 at 12:53 PM, Martin Blumenstingl
<martin.blumenstingl at googlemail.com> wrote:

> Add Meson8m2 support to the existing Meson8 pinctrl driver. Since there
> are only very few changes (Meson8m2 has an extra signal on 10 CBUS pins,
> no other differences were found so far).
> Add the new compatible strings for Meson8m2 to the existing Meson8
> driver so we don't have to duplicate the whole driver.
>
> Signed-off-by: Martin Blumenstingl <martin.blumenstingl at googlemail.com>

Patch applied with Kevin's ACK.

Yours,
Linus Walleij


From linus.walleij at linaro.org  Mon Apr 30 01:55:32 2018
From: linus.walleij at linaro.org (Linus Walleij)
Date: Mon, 30 Apr 2018 10:55:32 +0200
Subject: [PATCH 3/3] pinctrl: meson: meson8: add the RGMII RXD2/RXD3 and
 TXD2/TXD3 signals
In-Reply-To: <20180422105330.4712-4-martin.blumenstingl@googlemail.com>
References: <20180422105330.4712-1-martin.blumenstingl@googlemail.com>
 <20180422105330.4712-4-martin.blumenstingl@googlemail.com>
Message-ID: <CACRpkdbqvq4gp58F39VeHRFdwU+O7tDUBu7L_Vg7+ZKjUy2Vtw@mail.gmail.com>

On Sun, Apr 22, 2018 at 12:53 PM, Martin Blumenstingl
<martin.blumenstingl at googlemail.com> wrote:

> These are only available on the Meson8m2 SoC (which uses the same
> DesignWare Ethernet MAC as Meson8b).
> The "eth_tx_clk_50m" signal either provides a 50MHz clock for the RMII
> PHYs or the RGMII TX clock (as far as we know the frequency is
> controlled by the PRG_ETHERNET registers in the Ethernet MAC "glue" IP
> block).
>
> Signed-off-by: Martin Blumenstingl <martin.blumenstingl at googlemail.com>

Patch applied with Kevin's ACK.

Yours,
Linus Walleij


From khilman at baylibre.com  Mon Apr 30 08:35:47 2018
From: khilman at baylibre.com (Kevin Hilman)
Date: Mon, 30 Apr 2018 08:35:47 -0700
Subject: [PATCH] ARM64: dts: meson-axg: enable AP6255 wifi module
In-Reply-To: <30de15b8-4cc4-7f97-d134-7af75cb6ace1@amlogic.com>
References: <20180423145729.14368-1-yixun.lan@amlogic.com>
 <7h7eos1n68.fsf@baylibre.com>
 <30de15b8-4cc4-7f97-d134-7af75cb6ace1@amlogic.com>
Message-ID: <CAOi56cXKmv_Us1wDcMOYbdjFzZcLVu_t210Yrv891wKi22hV8A@mail.gmail.com>

On Fri, Apr 27, 2018 at 6:56 PM, Yixun Lan <yixun.lan at amlogic.com> wrote:
> On 04/28/18 03:09, Kevin Hilman wrote:
>> Yixun Lan <yixun.lan at amlogic.com> writes:
>>
>>> The Meson-AXG S400 board is shipped with AP6255 wifi module,
>>> which is actually using the brcmfmac 43455 driver.
>>>
>>> Signed-off-by: Yixun Lan <yixun.lan at amlogic.com>
>>> ---
>>>  .../arm64/boot/dts/amlogic/meson-axg-s400.dts | 44 ++++++++++++++++++-
>>>  1 file changed, 43 insertions(+), 1 deletion(-)
>>>
>>> diff --git a/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts b/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts
>>> index f67d4e47e641..b3e1bdca32bb 100644
>>> --- a/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts
>>> +++ b/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts
>>> @@ -51,7 +51,16 @@
>>>
>>>      sdio_pwrseq: sdio-pwrseq {
>>>              compatible = "mmc-pwrseq-simple";
>>> -            reset-gpios = <&gpio GPIOX_6 GPIO_ACTIVE_LOW>;
>>> +            reset-gpios = <&gpio GPIOX_7 GPIO_ACTIVE_LOW>;
>>
>> You didn't mention this GPIO change in the changelog.  Is it
>> intentional?
>
> Yes, the 'sdio_pwrseq' is used by wifi driver till now
> previous the reset-gpio is wrongly configured (copy & paste error),
> according to the schematics, it's GPIOX_7 which need to be fixed here.
>
> to be clean, in s400 board
>  GPIOX_6 is WIFI_WAKE_HOST pin
>  GPIOX_7 is WIFI_PWREN pin
>
> do you want me to put a note into the commit message? and resend this patch?

OK, thanks for the explanation.

I'd prefer the GPIO pin fix as a separate, standalone patch.

Thanks,

Kevin


