[PATCH 0/2] add the reset controller to the Meson8b clkc

Martin Blumenstingl martin.blumenstingl at googlemail.com
Tue Jul 11 15:49:37 PDT 2017

This registers the four CPU (soft) reset lines (one for each CPU core)
provided by the clock controller's HHI_SYS_CPU_CLK_CNTL0 register.

This is the first preparation step for SMP and CPU hotplug support on

The reset controller part of the meson8b clock controller has to be
registered early (which I did through CLK_OF_DECLARE_DRIVER), because
the secondary cores are started *very* early in the boot process (and
meson8b_clkc_probe is invoked long after we need the reset controller
to be available for booting the secondary CPU cores).

The user of the reset-controller (= the patches which enable SMP and
CPU hotplug support) will follow in the next days. I decided to split
this because the SMP series will probably consist of 6 patches alone
(and may need to go through two separate trees).

Martin Blumenstingl (2):
  clk: meson: meson8b: register the built-in reset controller
  ARM: dts: meson: mark the clock controller also as reset controller

 .../bindings/clock/amlogic,meson8b-clkc.txt        |   7 +-
 arch/arm/boot/dts/meson8.dtsi                      |   1 +
 arch/arm/boot/dts/meson8b.dtsi                     |   1 +
 drivers/clk/meson/Kconfig                          |   1 +
 drivers/clk/meson/meson8b.c                        | 109 ++++++++++++++++++---
 drivers/clk/meson/meson8b.h                        |   1 +
 6 files changed, 107 insertions(+), 13 deletions(-)


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