Decompressing Linux... Parsing ELF... done.
Booting the kernel.
[    0.000000][    T0] Linux version 6.1.0-rc5-00020-g6919cda8e0f1 (kbuild@969e24c280e0) (gcc-11 (Debian 11.3.0-8) 11.3.0, GNU ld (GNU Binutils for Debian) 2.39) #1 SMP Sat Dec 10 22:14:19 CST 2022
[    0.000000][    T0] Command line: ip=::::lkp-hsw-4ex1::dhcp root=/dev/ram0 RESULT_ROOT=/result/vm-scalability/performance-4-64-1-swap-w-seq-never-never/lkp-hsw-4ex1/debian-11.1-x86_64-20220510.cgz/x86_64-rhel-8.3/gcc-11/6919cda8e0f127fe773cad2553f0648de1c48445/0 BOOT_IMAGE=/pkg/linux/x86_64-rhel-8.3/gcc-11/6919cda8e0f127fe773cad2553f0648de1c48445/vmlinuz-6.1.0-rc5-00020-g6919cda8e0f1 branch=linux-devel/devel-hourly-20221209-093320 job=/lkp/jobs/scheduled/lkp-hsw-4ex1/vm-scalability-performance-4-64-1-swap-w-seq-never-never-debian-11.1-x86_64-20220510.cgz-6919cda8e0f127fe773cad2553f0648de1c4844-20221210-31307-1s05up6-0.yaml user=lkp ARCH=x86_64 kconfig=x86_64-rhel-8.3 commit=6919cda8e0f127fe773cad2553f0648de1c48445 initcall_debug cma=0 memmap=120G!4G memmap=120G!130G memmap=120G!258G memmap=120G!386G max_uptime=2100 LKP_SERVER=internal-lkp-server nokaslr selinux=0 debug apic=debug sysrq_always_enabled rcupdate.rcu_cpu_stall_timeout=100 net.ifnames=0 printk.devkmsg=on panic=-1 sof
[    0.000000][    T0] x86/fpu: Supporting XSAVE feature 0x001: 'x87 floating point registers'
[    0.000000][    T0] x86/fpu: Supporting XSAVE feature 0x002: 'SSE registers'
[    0.000000][    T0] x86/fpu: Supporting XSAVE feature 0x004: 'AVX registers'
[    0.000000][    T0] x86/fpu: xstate_offset[2]:  576, xstate_sizes[2]:  256
[    0.000000][    T0] x86/fpu: Enabled xstate features 0x7, context size is 832 bytes, using 'standard' format.
[    0.000000][    T0] signal: max sigframe size: 1776
[    0.000000][    T0] BIOS-provided physical RAM map:
[    0.000000][    T0] BIOS-e820: [mem 0x0000000000000100-0x000000000009cfff] usable
[    0.000000][    T0] BIOS-e820: [mem 0x000000000009d000-0x000000000009ffff] reserved
[    0.000000][    T0] BIOS-e820: [mem 0x00000000000e0000-0x00000000000fffff] reserved
[    0.000000][    T0] BIOS-e820: [mem 0x0000000000100000-0x0000000073becfff] usable
[    0.000000][    T0] BIOS-e820: [mem 0x0000000073bed000-0x0000000074621fff] reserved
[    0.000000][    T0] BIOS-e820: [mem 0x0000000074622000-0x000000007689dfff] ACPI NVS
[    0.000000][    T0] BIOS-e820: [mem 0x000000007689e000-0x000000007699dfff] ACPI data
[    0.000000][    T0] BIOS-e820: [mem 0x000000007699e000-0x000000007b7fffff] usable
[    0.000000][    T0] BIOS-e820: [mem 0x000000007b800000-0x000000008fffffff] reserved
[    0.000000][    T0] BIOS-e820: [mem 0x00000000fed1c000-0x00000000fed1ffff] reserved
[    0.000000][    T0] BIOS-e820: [mem 0x00000000ff800000-0x00000000ffffffff] reserved
[    0.000000][    T0] BIOS-e820: [mem 0x0000000100000000-0x000000807fffffff] usable
[    0.000000][    T0] printk: debug: ignoring loglevel setting.
[    0.000000][    T0] printk: bootconsole [earlyser0] enabled
[    0.000000][    T0] NX (Execute Disable) protection: active
[    0.000000][    T0] user-defined physical RAM map:
[    0.000000][    T0] user: [mem 0x0000000000000100-0x000000000009cfff] usable
[    0.000000][    T0] user: [mem 0x000000000009d000-0x000000000009ffff] reserved
[    0.000000][    T0] user: [mem 0x00000000000e0000-0x00000000000fffff] reserved
[    0.000000][    T0] user: [mem 0x0000000000100000-0x0000000073becfff] usable
[    0.000000][    T0] user: [mem 0x0000000073bed000-0x0000000074621fff] reserved
[    0.000000][    T0] user: [mem 0x0000000074622000-0x000000007689dfff] ACPI NVS
[    0.000000][    T0] user: [mem 0x000000007689e000-0x000000007699dfff] ACPI data
[    0.000000][    T0] user: [mem 0x000000007699e000-0x000000007b7fffff] usable
[    0.000000][    T0] user: [mem 0x000000007b800000-0x000000008fffffff] reserved
[    0.000000][    T0] user: [mem 0x00000000fed1c000-0x00000000fed1ffff] reserved
[    0.000000][    T0] user: [mem 0x00000000ff800000-0x00000000ffffffff] reserved
[    0.000000][    T0] user: [mem 0x0000000100000000-0x0000001effffffff] persistent (type 12)
[    0.000000][    T0] user: [mem 0x0000001f00000000-0x000000207fffffff] usable
[    0.000000][    T0] user: [mem 0x0000002080000000-0x0000003e7fffffff] persistent (type 12)
[    0.000000][    T0] user: [mem 0x0000003e80000000-0x000000407fffffff] usable
[    0.000000][    T0] user: [mem 0x0000004080000000-0x0000005e7fffffff] persistent (type 12)
[    0.000000][    T0] user: [mem 0x0000005e80000000-0x000000607fffffff] usable
[    0.000000][    T0] user: [mem 0x0000006080000000-0x0000007e7fffffff] persistent (type 12)
[    0.000000][    T0] user: [mem 0x0000007e80000000-0x000000807fffffff] usable
[    0.000000][    T0] SMBIOS 2.7 present.
[    0.000000][    T0] DMI: Intel Corporation BRICKLAND/BRICKLAND, BIOS BRHSXSD1.86B.0067.R02.1507221722 07/22/2015
[    0.000000][    T0] tsc: Fast TSC calibration using PIT
[    0.000000][    T0] tsc: Detected 2493.898 MHz processor
[    0.000717][    T0] e820: update [mem 0x00000000-0x00000fff] usable ==> reserved
[    0.008773][    T0] e820: remove [mem 0x000a0000-0x000fffff] usable
[    0.015762][    T0] last_pfn = 0x8080000 max_arch_pfn = 0x400000000
[    0.022932][    T0] x86/PAT: Configuration [0-7]: WB  WC  UC- UC  WB  WP  UC- WT  
[    0.033563][    T0] last_pfn = 0x7b800 max_arch_pfn = 0x400000000
[    0.040176][    T0] Scan for SMP in [mem 0x00000000-0x000003ff]
[    0.046795][    T0] Scan for SMP in [mem 0x0009fc00-0x0009ffff]
[    0.053385][    T0] Scan for SMP in [mem 0x000f0000-0x000fffff]
[    0.067579][    T0] Scan for SMP in [mem 0x0009d000-0x0009d3ff]
[    0.074020][    T0] Using GB pages for direct mapping
[    0.080109][    T0] RAMDISK: [mem 0x80311cf000-0x807d1fffff]
[    0.086227][    T0] ACPI: Early table checksum verification disabled
[    0.093310][    T0] ACPI: RSDP 0x00000000000F0410 000024 (v02 INTEL )
[    0.100482][    T0] ACPI: XSDT 0x000000007699C0E8 0000BC (v01 INTEL  TIANO    00000000      01000013)
[    0.110762][    T0] ACPI: FACP 0x0000000076999000 0000F4 (v04 INTEL  TIANO    00000000 MSFT 01000013)
[    0.121042][    T0] ACPI: DSDT 0x000000007696A000 0234A8 (v02 INTEL  TIANO    00000003 MSFT 01000013)
[    0.131315][    T0] ACPI: FACS 0x0000000074FFD000 000040
[    0.137230][    T0] ACPI: TCPA 0x000000007699B000 000064 (v02 INTEL  EDK2     00000002      01000013)
[    0.147507][    T0] ACPI: BDAT 0x000000007699A000 000030 (v01 INTEL  TIANO    00000000 MSFT 01000013)
[    0.157785][    T0] ACPI: HPET 0x0000000076998000 000038 (v01 INTEL  TIANO    00000001 MSFT 01000013)
[    0.168062][    T0] ACPI: APIC 0x0000000076997000 00085C (v03 INTEL  TIANO    00000000 MSFT 01000013)
[    0.178340][    T0] ACPI: MCFG 0x0000000076996000 00003C (v01 INTEL  TIANO    00000001 MSFT 01000013)
[    0.188619][    T0] ACPI: MSCT 0x0000000076995000 000090 (v01 INTEL  TIANO    00000001 MSFT 01000013)
[    0.198895][    T0] ACPI: PCCT 0x0000000076994000 0000AC (v01 INTEL  TIANO    00000002 MSFT 01000013)
[    0.209174][    T0] ACPI: PMCT 0x0000000076993000 000060 (v01 INTEL  TIANO    00000000 MSFT 01000013)
[    0.219452][    T0] ACPI: RASF 0x0000000076992000 000030 (v01 INTEL  TIANO    00000001 MSFT 01000013)
[    0.229730][    T0] ACPI: SLIT 0x0000000076991000 00006C (v01 INTEL  TIANO    00000001 MSFT 01000013)
[    0.240008][    T0] ACPI: SRAT 0x0000000076990000 000E30 (v03 INTEL  TIANO    00000001 MSFT 01000013)
[    0.250285][    T0] ACPI: SVOS 0x000000007698F000 000032 (v01 INTEL  TIANO    00000000 MSFT 01000013)
[    0.260563][    T0] ACPI: WDDT 0x000000007698E000 000040 (v01 INTEL  TIANO    00000000 MSFT 01000013)
[    0.270842][    T0] ACPI: SSDT 0x00000000768B2000 0B723B (v02 INTEL  SSDT  PM 00004000 INTL 20090521)
[    0.281119][    T0] ACPI: SSDT 0x00000000768B0000 001DAF (v02 INTEL  SpsNm    00000002 INTL 20090521)
[    0.291398][    T0] ACPI: SSDT 0x00000000768AF000 000040 (v02 INTEL  SpsNvs   00000002 INTL 20090521)
[    0.301675][    T0] ACPI: PRAD 0x00000000768AE000 000125 (v02 INTEL  SpsPrAgg 00000002 INTL 20090521)
[    0.311953][    T0] ACPI: SPCR 0x00000000768AD000 000050 (v01                 00000000      00000000)
[    0.322231][    T0] ACPI: Reserving FACP table memory at [mem 0x76999000-0x769990f3]
[    0.330859][    T0] ACPI: Reserving DSDT table memory at [mem 0x7696a000-0x7698d4a7]
[    0.339489][    T0] ACPI: Reserving FACS table memory at [mem 0x74ffd000-0x74ffd03f]
[    0.348118][    T0] ACPI: Reserving TCPA table memory at [mem 0x7699b000-0x7699b063]
[    0.356750][    T0] ACPI: Reserving BDAT table memory at [mem 0x7699a000-0x7699a02f]
[    0.365378][    T0] ACPI: Reserving HPET table memory at [mem 0x76998000-0x76998037]
[    0.374008][    T0] ACPI: Reserving APIC table memory at [mem 0x76997000-0x7699785b]
[    0.382638][    T0] ACPI: Reserving MCFG table memory at [mem 0x76996000-0x7699603b]
[    0.391267][    T0] ACPI: Reserving MSCT table memory at [mem 0x76995000-0x7699508f]
[    0.399897][    T0] ACPI: Reserving PCCT table memory at [mem 0x76994000-0x769940ab]
[    0.408526][    T0] ACPI: Reserving PMCT table memory at [mem 0x76993000-0x7699305f]
[    0.417156][    T0] ACPI: Reserving RASF table memory at [mem 0x76992000-0x7699202f]
[    0.425786][    T0] ACPI: Reserving SLIT table memory at [mem 0x76991000-0x7699106b]
[    0.434415][    T0] ACPI: Reserving SRAT table memory at [mem 0x76990000-0x76990e2f]
[    0.443045][    T0] ACPI: Reserving SVOS table memory at [mem 0x7698f000-0x7698f031]
[    0.451675][    T0] ACPI: Reserving WDDT table memory at [mem 0x7698e000-0x7698e03f]
[    0.460304][    T0] ACPI: Reserving SSDT table memory at [mem 0x768b2000-0x7696923a]
[    0.468933][    T0] ACPI: Reserving SSDT table memory at [mem 0x768b0000-0x768b1dae]
[    0.477564][    T0] ACPI: Reserving SSDT table memory at [mem 0x768af000-0x768af03f]
[    0.486194][    T0] ACPI: Reserving PRAD table memory at [mem 0x768ae000-0x768ae124]
[    0.494822][    T0] ACPI: Reserving SPCR table memory at [mem 0x768ad000-0x768ad04f]
[    0.503474][    T0] mapped APIC to ffffffffff5fc000 (        fee00000)
[    0.510733][    T0] SRAT: PXM 0 -> APIC 0x00 -> Node 0
[    0.516446][    T0] SRAT: PXM 0 -> APIC 0x02 -> Node 0
[    0.522167][    T0] SRAT: PXM 0 -> APIC 0x04 -> Node 0
[    0.527886][    T0] SRAT: PXM 0 -> APIC 0x06 -> Node 0
[    0.533607][    T0] SRAT: PXM 0 -> APIC 0x08 -> Node 0
[    0.539327][    T0] SRAT: PXM 0 -> APIC 0x10 -> Node 0
[    0.545048][    T0] SRAT: PXM 0 -> APIC 0x12 -> Node 0
[    0.550769][    T0] SRAT: PXM 0 -> APIC 0x14 -> Node 0
[    0.556490][    T0] SRAT: PXM 0 -> APIC 0x16 -> Node 0
[    0.562211][    T0] SRAT: PXM 0 -> APIC 0x20 -> Node 0
[    0.567932][    T0] SRAT: PXM 0 -> APIC 0x22 -> Node 0
[    0.573652][    T0] SRAT: PXM 0 -> APIC 0x24 -> Node 0
[    0.579374][    T0] SRAT: PXM 0 -> APIC 0x26 -> Node 0
[    0.585094][    T0] SRAT: PXM 0 -> APIC 0x28 -> Node 0
[    0.590815][    T0] SRAT: PXM 0 -> APIC 0x30 -> Node 0
[    0.596536][    T0] SRAT: PXM 0 -> APIC 0x32 -> Node 0
[    0.602257][    T0] SRAT: PXM 0 -> APIC 0x34 -> Node 0
[    0.607978][    T0] SRAT: PXM 0 -> APIC 0x36 -> Node 0
[    0.613697][    T0] SRAT: PXM 1 -> APIC 0x40 -> Node 1
[    0.619419][    T0] SRAT: PXM 1 -> APIC 0x42 -> Node 1
[    0.625140][    T0] SRAT: PXM 1 -> APIC 0x44 -> Node 1
[    0.630860][    T0] SRAT: PXM 1 -> APIC 0x46 -> Node 1
[    0.636582][    T0] SRAT: PXM 1 -> APIC 0x48 -> Node 1
[    0.642302][    T0] SRAT: PXM 1 -> APIC 0x50 -> Node 1
[    0.648022][    T0] SRAT: PXM 1 -> APIC 0x52 -> Node 1
[    0.653745][    T0] SRAT: PXM 1 -> APIC 0x54 -> Node 1
[    0.659463][    T0] SRAT: PXM 1 -> APIC 0x56 -> Node 1
[    0.665185][    T0] SRAT: PXM 1 -> APIC 0x60 -> Node 1
[    0.670906][    T0] SRAT: PXM 1 -> APIC 0x62 -> Node 1
[    0.676626][    T0] SRAT: PXM 1 -> APIC 0x64 -> Node 1
[    0.682347][    T0] SRAT: PXM 1 -> APIC 0x66 -> Node 1
[    0.688067][    T0] SRAT: PXM 1 -> APIC 0x68 -> Node 1
[    0.693789][    T0] SRAT: PXM 1 -> APIC 0x70 -> Node 1
[    0.699511][    T0] SRAT: PXM 1 -> APIC 0x72 -> Node 1
[    0.705230][    T0] SRAT: PXM 1 -> APIC 0x74 -> Node 1
[    0.710950][    T0] SRAT: PXM 1 -> APIC 0x76 -> Node 1
[    0.716671][    T0] SRAT: PXM 2 -> APIC 0x80 -> Node 2
[    0.722393][    T0] SRAT: PXM 2 -> APIC 0x82 -> Node 2
[    0.728113][    T0] SRAT: PXM 2 -> APIC 0x84 -> Node 2
[    0.733833][    T0] SRAT: PXM 2 -> APIC 0x86 -> Node 2
[    0.739554][    T0] SRAT: PXM 2 -> APIC 0x88 -> Node 2
[    0.745277][    T0] SRAT: PXM 2 -> APIC 0x90 -> Node 2
[    0.750996][    T0] SRAT: PXM 2 -> APIC 0x92 -> Node 2
[    0.756718][    T0] SRAT: PXM 2 -> APIC 0x94 -> Node 2
[    0.762438][    T0] SRAT: PXM 2 -> APIC 0x96 -> Node 2
[    0.768158][    T0] SRAT: PXM 2 -> APIC 0xa0 -> Node 2
[    0.773880][    T0] SRAT: PXM 2 -> APIC 0xa2 -> Node 2
[    0.779600][    T0] SRAT: PXM 2 -> APIC 0xa4 -> Node 2
[    0.785320][    T0] SRAT: PXM 2 -> APIC 0xa6 -> Node 2
[    0.791040][    T0] SRAT: PXM 2 -> APIC 0xa8 -> Node 2
[    0.796762][    T0] SRAT: PXM 2 -> APIC 0xb0 -> Node 2
[    0.802483][    T0] SRAT: PXM 2 -> APIC 0xb2 -> Node 2
[    0.808203][    T0] SRAT: PXM 2 -> APIC 0xb4 -> Node 2
[    0.813925][    T0] SRAT: PXM 2 -> APIC 0xb6 -> Node 2
[    0.819645][    T0] SRAT: PXM 3 -> APIC 0xc0 -> Node 3
[    0.825366][    T0] SRAT: PXM 3 -> APIC 0xc2 -> Node 3
[    0.831087][    T0] SRAT: PXM 3 -> APIC 0xc4 -> Node 3
[    0.836807][    T0] SRAT: PXM 3 -> APIC 0xc6 -> Node 3
[    0.842528][    T0] SRAT: PXM 3 -> APIC 0xc8 -> Node 3
[    0.848250][    T0] SRAT: PXM 3 -> APIC 0xd0 -> Node 3
[    0.853970][    T0] SRAT: PXM 3 -> APIC 0xd2 -> Node 3
[    0.859690][    T0] SRAT: PXM 3 -> APIC 0xd4 -> Node 3
[    0.865412][    T0] SRAT: PXM 3 -> APIC 0xd6 -> Node 3
[    0.871132][    T0] SRAT: PXM 3 -> APIC 0xe0 -> Node 3
[    0.876852][    T0] SRAT: PXM 3 -> APIC 0xe2 -> Node 3
[    0.882574][    T0] SRAT: PXM 3 -> APIC 0xe4 -> Node 3
[    0.888294][    T0] SRAT: PXM 3 -> APIC 0xe6 -> Node 3
[    0.894015][    T0] SRAT: PXM 3 -> APIC 0xe8 -> Node 3
[    0.899735][    T0] SRAT: PXM 3 -> APIC 0xf0 -> Node 3
[    0.905456][    T0] SRAT: PXM 3 -> APIC 0xf2 -> Node 3
[    0.911176][    T0] SRAT: PXM 3 -> APIC 0xf4 -> Node 3
[    0.916898][    T0] SRAT: PXM 3 -> APIC 0xf6 -> Node 3
[    0.922619][    T0] SRAT: PXM 0 -> APIC 0x01 -> Node 0
[    0.928339][    T0] SRAT: PXM 0 -> APIC 0x03 -> Node 0
[    0.934059][    T0] SRAT: PXM 0 -> APIC 0x05 -> Node 0
[    0.939781][    T0] SRAT: PXM 0 -> APIC 0x07 -> Node 0
[    0.945501][    T0] SRAT: PXM 0 -> APIC 0x09 -> Node 0
[    0.951222][    T0] SRAT: PXM 0 -> APIC 0x11 -> Node 0
[    0.956944][    T0] SRAT: PXM 0 -> APIC 0x13 -> Node 0
[    0.962664][    T0] SRAT: PXM 0 -> APIC 0x15 -> Node 0
[    0.968384][    T0] SRAT: PXM 0 -> APIC 0x17 -> Node 0
[    0.974106][    T0] SRAT: PXM 0 -> APIC 0x21 -> Node 0
[    0.979826][    T0] SRAT: PXM 0 -> APIC 0x23 -> Node 0
[    0.985546][    T0] SRAT: PXM 0 -> APIC 0x25 -> Node 0
[    0.991267][    T0] SRAT: PXM 0 -> APIC 0x27 -> Node 0
[    0.996989][    T0] SRAT: PXM 0 -> APIC 0x29 -> Node 0
[    1.002709][    T0] SRAT: PXM 0 -> APIC 0x31 -> Node 0
[    1.008429][    T0] SRAT: PXM 0 -> APIC 0x33 -> Node 0
[    1.014150][    T0] SRAT: PXM 0 -> APIC 0x35 -> Node 0
[    1.019871][    T0] SRAT: PXM 0 -> APIC 0x37 -> Node 0
[    1.025593][    T0] SRAT: PXM 1 -> APIC 0x41 -> Node 1
[    1.031313][    T0] SRAT: PXM 1 -> APIC 0x43 -> Node 1
[    1.037033][    T0] SRAT: PXM 1 -> APIC 0x45 -> Node 1
[    1.042755][    T0] SRAT: PXM 1 -> APIC 0x47 -> Node 1
[    1.048475][    T0] SRAT: PXM 1 -> APIC 0x49 -> Node 1
[    1.054197][    T0] SRAT: PXM 1 -> APIC 0x51 -> Node 1
[    1.059917][    T0] SRAT: PXM 1 -> APIC 0x53 -> Node 1
[    1.065637][    T0] SRAT: PXM 1 -> APIC 0x55 -> Node 1
[    1.071359][    T0] SRAT: PXM 1 -> APIC 0x57 -> Node 1
[    1.077080][    T0] SRAT: PXM 1 -> APIC 0x61 -> Node 1
[    1.082799][    T0] SRAT: PXM 1 -> APIC 0x63 -> Node 1
[    1.088520][    T0] SRAT: PXM 1 -> APIC 0x65 -> Node 1
[    1.094242][    T0] SRAT: PXM 1 -> APIC 0x67 -> Node 1
[    1.099962][    T0] SRAT: PXM 1 -> APIC 0x69 -> Node 1
[    1.105683][    T0] SRAT: PXM 1 -> APIC 0x71 -> Node 1
[    1.111403][    T0] SRAT: PXM 1 -> APIC 0x73 -> Node 1
[    1.117124][    T0] SRAT: PXM 1 -> APIC 0x75 -> Node 1
[    1.122845][    T0] SRAT: PXM 1 -> APIC 0x77 -> Node 1
[    1.128566][    T0] SRAT: PXM 2 -> APIC 0x81 -> Node 2
[    1.134286][    T0] SRAT: PXM 2 -> APIC 0x83 -> Node 2
[    1.140008][    T0] SRAT: PXM 2 -> APIC 0x85 -> Node 2
[    1.145728][    T0] SRAT: PXM 2 -> APIC 0x87 -> Node 2
[    1.151449][    T0] SRAT: PXM 2 -> APIC 0x89 -> Node 2
[    1.157169][    T0] SRAT: PXM 2 -> APIC 0x91 -> Node 2
[    1.162891][    T0] SRAT: PXM 2 -> APIC 0x93 -> Node 2
[    1.168612][    T0] SRAT: PXM 2 -> APIC 0x95 -> Node 2
[    1.174332][    T0] SRAT: PXM 2 -> APIC 0x97 -> Node 2
[    1.180052][    T0] SRAT: PXM 2 -> APIC 0xa1 -> Node 2
[    1.185773][    T0] SRAT: PXM 2 -> APIC 0xa3 -> Node 2
[    1.191494][    T0] SRAT: PXM 2 -> APIC 0xa5 -> Node 2
[    1.197214][    T0] SRAT: PXM 2 -> APIC 0xa7 -> Node 2
[    1.202936][    T0] SRAT: PXM 2 -> APIC 0xa9 -> Node 2
[    1.208657][    T0] SRAT: PXM 2 -> APIC 0xb1 -> Node 2
[    1.214377][    T0] SRAT: PXM 2 -> APIC 0xb3 -> Node 2
[    1.220097][    T0] SRAT: PXM 2 -> APIC 0xb5 -> Node 2
[    1.225819][    T0] SRAT: PXM 2 -> APIC 0xb7 -> Node 2
[    1.231539][    T0] SRAT: PXM 3 -> APIC 0xc1 -> Node 3
[    1.237260][    T0] SRAT: PXM 3 -> APIC 0xc3 -> Node 3
[    1.242981][    T0] SRAT: PXM 3 -> APIC 0xc5 -> Node 3
[    1.248701][    T0] SRAT: PXM 3 -> APIC 0xc7 -> Node 3
[    1.254423][    T0] SRAT: PXM 3 -> APIC 0xc9 -> Node 3
[    1.260143][    T0] SRAT: PXM 3 -> APIC 0xd1 -> Node 3
[    1.265864][    T0] SRAT: PXM 3 -> APIC 0xd3 -> Node 3
[    1.271585][    T0] SRAT: PXM 3 -> APIC 0xd5 -> Node 3
[    1.277306][    T0] SRAT: PXM 3 -> APIC 0xd7 -> Node 3
[    1.283026][    T0] SRAT: PXM 3 -> APIC 0xe1 -> Node 3
[    1.288747][    T0] SRAT: PXM 3 -> APIC 0xe3 -> Node 3
[    1.294467][    T0] SRAT: PXM 3 -> APIC 0xe5 -> Node 3
[    1.300189][    T0] SRAT: PXM 3 -> APIC 0xe7 -> Node 3
[    1.305908][    T0] SRAT: PXM 3 -> APIC 0xe9 -> Node 3
[    1.311630][    T0] SRAT: PXM 3 -> APIC 0xf1 -> Node 3
[    1.317350][    T0] SRAT: PXM 3 -> APIC 0xf3 -> Node 3
[    1.323072][    T0] SRAT: PXM 3 -> APIC 0xf5 -> Node 3
[    1.328791][    T0] SRAT: PXM 3 -> APIC 0xf7 -> Node 3
[    1.334517][    T0] ACPI: SRAT: Node 0 PXM 0 [mem 0x00000000-0x7fffffff]
[    1.341979][    T0] ACPI: SRAT: Node 0 PXM 0 [mem 0x100000000-0x207fffffff]
[    1.349736][    T0] ACPI: SRAT: Node 1 PXM 1 [mem 0x2080000000-0x407fffffff]
[    1.357589][    T0] ACPI: SRAT: Node 2 PXM 2 [mem 0x4080000000-0x607fffffff]
[    1.365444][    T0] ACPI: SRAT: Node 3 PXM 3 [mem 0x6080000000-0x807fffffff]
[    1.373301][    T0] NUMA: Initialized distance table, cnt=4
[    1.379506][    T0] NUMA: Node 0 [mem 0x00000000-0x7fffffff] + [mem 0x100000000-0x207fffffff] -> [mem 0x00000000-0x207fffffff]
[    1.392214][    T0] NODE_DATA(0) allocated [mem 0x207ffd5000-0x207fffffff]
[    1.399898][    T0] NODE_DATA(1) allocated [mem 0x407ffd5000-0x407fffffff]
[    1.407583][    T0] NODE_DATA(2) allocated [mem 0x607ffd5000-0x607fffffff]
[    1.415243][    T0] NODE_DATA(3) allocated [mem 0x807ffd4000-0x807fffefff]
[    1.423192][    T0] Zone ranges:
[    1.426593][    T0]   DMA      [mem 0x0000000000001000-0x0000000000ffffff]
[    1.434252][    T0]   DMA32    [mem 0x0000000001000000-0x00000000ffffffff]
[    1.441913][    T0]   Normal   [mem 0x0000000100000000-0x000000807fffffff]
[    1.449573][    T0]   Device   empty
[    1.453549][    T0] Movable zone start for each node
[    1.459077][    T0] Early memory node ranges
[    1.463826][    T0]   node   0: [mem 0x0000000000001000-0x000000000009cfff]
[    1.471584][    T0]   node   0: [mem 0x0000000000100000-0x0000000073becfff]
[    1.479339][    T0]   node   0: [mem 0x000000007699e000-0x000000007b7fffff]
[    1.487098][    T0]   node   0: [mem 0x0000001f00000000-0x000000207fffffff]
[    1.494854][    T0]   node   1: [mem 0x0000003e80000000-0x000000407fffffff]
[    1.502611][    T0]   node   2: [mem 0x0000005e80000000-0x000000607fffffff]
[    1.510369][    T0]   node   3: [mem 0x0000007e80000000-0x000000807fffffff]
[    1.518125][    T0] Initmem setup node 0 [mem 0x0000000000001000-0x000000207fffffff]
[    1.526755][    T0] Initmem setup node 1 [mem 0x0000003e80000000-0x000000407fffffff]
[    1.535385][    T0] Initmem setup node 2 [mem 0x0000005e80000000-0x000000607fffffff]
[    1.544014][    T0] Initmem setup node 3 [mem 0x0000007e80000000-0x000000807fffffff]
[    1.552662][    T0] On node 0, zone DMA: 1 pages in unavailable ranges
[    1.552738][    T0] On node 0, zone DMA: 99 pages in unavailable ranges
[    1.566766][    T0] On node 0, zone DMA32: 11697 pages in unavailable ranges
[    1.575162][    T0] On node 0, zone Normal: 18432 pages in unavailable ranges
[    1.586261][    T0] ACPI: PM-Timer IO Port: 0x408
[    1.599295][    T0] ACPI: LAPIC_NMI (acpi_id[0x00] high level lint[0x1])
[    1.606730][    T0] ACPI: LAPIC_NMI (acpi_id[0x01] high level lint[0x1])
[    1.614196][    T0] ACPI: LAPIC_NMI (acpi_id[0x02] high level lint[0x1])
[    1.621663][    T0] ACPI: LAPIC_NMI (acpi_id[0x03] high level lint[0x1])
[    1.629128][    T0] ACPI: LAPIC_NMI (acpi_id[0x04] high level lint[0x1])
[    1.636594][    T0] ACPI: LAPIC_NMI (acpi_id[0x05] high level lint[0x1])
[    1.644061][    T0] ACPI: LAPIC_NMI (acpi_id[0x06] high level lint[0x1])
[    1.651527][    T0] ACPI: LAPIC_NMI (acpi_id[0x07] high level lint[0x1])
[    1.658992][    T0] ACPI: LAPIC_NMI (acpi_id[0x08] high level lint[0x1])
[    1.666461][    T0] ACPI: LAPIC_NMI (acpi_id[0x09] high level lint[0x1])
[    1.673924][    T0] ACPI: LAPIC_NMI (acpi_id[0x0a] high level lint[0x1])
[    1.681390][    T0] ACPI: LAPIC_NMI (acpi_id[0x0b] high level lint[0x1])
[    1.688857][    T0] ACPI: LAPIC_NMI (acpi_id[0x0c] high level lint[0x1])
[    1.696322][    T0] ACPI: LAPIC_NMI (acpi_id[0x0d] high level lint[0x1])
[    1.703789][    T0] ACPI: LAPIC_NMI (acpi_id[0x0e] high level lint[0x1])
[    1.711255][    T0] ACPI: LAPIC_NMI (acpi_id[0x0f] high level lint[0x1])
[    1.718720][    T0] ACPI: LAPIC_NMI (acpi_id[0x10] high level lint[0x1])
[    1.726187][    T0] ACPI: LAPIC_NMI (acpi_id[0x11] high level lint[0x1])
[    1.733653][    T0] ACPI: LAPIC_NMI (acpi_id[0x12] high level lint[0x1])
[    1.741119][    T0] ACPI: LAPIC_NMI (acpi_id[0x13] high level lint[0x1])
[    1.748586][    T0] ACPI: LAPIC_NMI (acpi_id[0x14] high level lint[0x1])
[    1.756051][    T0] ACPI: LAPIC_NMI (acpi_id[0x15] high level lint[0x1])
[    1.763517][    T0] ACPI: LAPIC_NMI (acpi_id[0x16] high level lint[0x1])
[    1.770984][    T0] ACPI: LAPIC_NMI (acpi_id[0x17] high level lint[0x1])
[    1.778449][    T0] ACPI: LAPIC_NMI (acpi_id[0x18] high level lint[0x1])
[    1.785915][    T0] ACPI: LAPIC_NMI (acpi_id[0x19] high level lint[0x1])
[    1.793382][    T0] ACPI: LAPIC_NMI (acpi_id[0x1a] high level lint[0x1])
[    1.800848][    T0] ACPI: LAPIC_NMI (acpi_id[0x1b] high level lint[0x1])
[    1.808313][    T0] ACPI: LAPIC_NMI (acpi_id[0x1c] high level lint[0x1])
[    1.815780][    T0] ACPI: LAPIC_NMI (acpi_id[0x1d] high level lint[0x1])
[    1.823247][    T0] ACPI: LAPIC_NMI (acpi_id[0x1e] high level lint[0x1])
[    1.830712][    T0] ACPI: LAPIC_NMI (acpi_id[0x1f] high level lint[0x1])
[    1.838177][    T0] ACPI: LAPIC_NMI (acpi_id[0x20] high level lint[0x1])
[    1.845645][    T0] ACPI: LAPIC_NMI (acpi_id[0x21] high level lint[0x1])
[    1.853110][    T0] ACPI: LAPIC_NMI (acpi_id[0x22] high level lint[0x1])
[    1.860576][    T0] ACPI: LAPIC_NMI (acpi_id[0x23] high level lint[0x1])
[    1.868042][    T0] ACPI: LAPIC_NMI (acpi_id[0x24] high level lint[0x1])
[    1.875508][    T0] ACPI: LAPIC_NMI (acpi_id[0x25] high level lint[0x1])
[    1.882975][    T0] ACPI: LAPIC_NMI (acpi_id[0x26] high level lint[0x1])
[    1.890440][    T0] ACPI: LAPIC_NMI (acpi_id[0x27] high level lint[0x1])
[    1.897907][    T0] ACPI: LAPIC_NMI (acpi_id[0x28] high level lint[0x1])
[    1.905372][    T0] ACPI: LAPIC_NMI (acpi_id[0x29] high level lint[0x1])
[    1.912839][    T0] ACPI: LAPIC_NMI (acpi_id[0x2a] high level lint[0x1])
[    1.920305][    T0] ACPI: LAPIC_NMI (acpi_id[0x2b] high level lint[0x1])
[    1.927771][    T0] ACPI: LAPIC_NMI (acpi_id[0x2c] high level lint[0x1])
[    1.935236][    T0] ACPI: LAPIC_NMI (acpi_id[0x2d] high level lint[0x1])
[    1.942703][    T0] ACPI: LAPIC_NMI (acpi_id[0x2e] high level lint[0x1])
[    1.950170][    T0] ACPI: LAPIC_NMI (acpi_id[0x2f] high level lint[0x1])
[    1.957635][    T0] ACPI: LAPIC_NMI (acpi_id[0x30] high level lint[0x1])
[    1.965102][    T0] ACPI: LAPIC_NMI (acpi_id[0x31] high level lint[0x1])
[    1.972567][    T0] ACPI: LAPIC_NMI (acpi_id[0x32] high level lint[0x1])
[    1.980034][    T0] ACPI: LAPIC_NMI (acpi_id[0x33] high level lint[0x1])
[    1.987499][    T0] ACPI: LAPIC_NMI (acpi_id[0x34] high level lint[0x1])
[    1.994966][    T0] ACPI: LAPIC_NMI (acpi_id[0x35] high level lint[0x1])
[    2.002432][    T0] ACPI: LAPIC_NMI (acpi_id[0x36] high level lint[0x1])
[    2.009897][    T0] ACPI: LAPIC_NMI (acpi_id[0x37] high level lint[0x1])
[    2.017363][    T0] ACPI: LAPIC_NMI (acpi_id[0x38] high level lint[0x1])
[    2.024830][    T0] ACPI: LAPIC_NMI (acpi_id[0x39] high level lint[0x1])
[    2.032296][    T0] ACPI: LAPIC_NMI (acpi_id[0x3a] high level lint[0x1])
[    2.039762][    T0] ACPI: LAPIC_NMI (acpi_id[0x3b] high level lint[0x1])
[    2.047228][    T0] ACPI: LAPIC_NMI (acpi_id[0x3c] high level lint[0x1])
[    2.054694][    T0] ACPI: LAPIC_NMI (acpi_id[0x3d] high level lint[0x1])
[    2.062161][    T0] ACPI: LAPIC_NMI (acpi_id[0x3e] high level lint[0x1])
[    2.069627][    T0] ACPI: LAPIC_NMI (acpi_id[0x3f] high level lint[0x1])
[    2.077093][    T0] ACPI: LAPIC_NMI (acpi_id[0x40] high level lint[0x1])
[    2.084558][    T0] ACPI: LAPIC_NMI (acpi_id[0x41] high level lint[0x1])
[    2.092024][    T0] ACPI: LAPIC_NMI (acpi_id[0x42] high level lint[0x1])
[    2.099491][    T0] ACPI: LAPIC_NMI (acpi_id[0x43] high level lint[0x1])
[    2.106956][    T0] ACPI: LAPIC_NMI (acpi_id[0x44] high level lint[0x1])
[    2.114422][    T0] ACPI: LAPIC_NMI (acpi_id[0x45] high level lint[0x1])
[    2.121888][    T0] ACPI: LAPIC_NMI (acpi_id[0x46] high level lint[0x1])
[    2.129355][    T0] ACPI: LAPIC_NMI (acpi_id[0x47] high level lint[0x1])
[    2.136821][    T0] ACPI: LAPIC_NMI (acpi_id[0x48] high level lint[0x1])
[    2.144288][    T0] ACPI: LAPIC_NMI (acpi_id[0x49] high level lint[0x1])
[    2.151754][    T0] ACPI: LAPIC_NMI (acpi_id[0x4a] high level lint[0x1])
[    2.159219][    T0] ACPI: LAPIC_NMI (acpi_id[0x4b] high level lint[0x1])
[    2.166686][    T0] ACPI: LAPIC_NMI (acpi_id[0x4c] high level lint[0x1])
[    2.174151][    T0] ACPI: LAPIC_NMI (acpi_id[0x4d] high level lint[0x1])
[    2.181617][    T0] ACPI: LAPIC_NMI (acpi_id[0x4e] high level lint[0x1])
[    2.189083][    T0] ACPI: LAPIC_NMI (acpi_id[0x4f] high level lint[0x1])
[    2.196550][    T0] ACPI: LAPIC_NMI (acpi_id[0x50] high level lint[0x1])
[    2.204016][    T0] ACPI: LAPIC_NMI (acpi_id[0x51] high level lint[0x1])
[    2.211481][    T0] ACPI: LAPIC_NMI (acpi_id[0x52] high level lint[0x1])
[    2.218948][    T0] ACPI: LAPIC_NMI (acpi_id[0x53] high level lint[0x1])
[    2.226413][    T0] ACPI: LAPIC_NMI (acpi_id[0x54] high level lint[0x1])
[    2.233880][    T0] ACPI: LAPIC_NMI (acpi_id[0x55] high level lint[0x1])
[    2.241346][    T0] ACPI: LAPIC_NMI (acpi_id[0x56] high level lint[0x1])
[    2.248813][    T0] ACPI: LAPIC_NMI (acpi_id[0x57] high level lint[0x1])
[    2.256278][    T0] ACPI: LAPIC_NMI (acpi_id[0x58] high level lint[0x1])
[    2.263744][    T0] ACPI: LAPIC_NMI (acpi_id[0x59] high level lint[0x1])
[    2.271210][    T0] ACPI: LAPIC_NMI (acpi_id[0x5a] high level lint[0x1])
[    2.278677][    T0] ACPI: LAPIC_NMI (acpi_id[0x5b] high level lint[0x1])
[    2.286142][    T0] ACPI: LAPIC_NMI (acpi_id[0x5c] high level lint[0x1])
[    2.293609][    T0] ACPI: LAPIC_NMI (acpi_id[0x5d] high level lint[0x1])
[    2.301074][    T0] ACPI: LAPIC_NMI (acpi_id[0x5e] high level lint[0x1])
[    2.308540][    T0] ACPI: LAPIC_NMI (acpi_id[0x5f] high level lint[0x1])
[    2.316007][    T0] ACPI: LAPIC_NMI (acpi_id[0x60] high level lint[0x1])
[    2.323473][    T0] ACPI: LAPIC_NMI (acpi_id[0x61] high level lint[0x1])
[    2.330938][    T0] ACPI: LAPIC_NMI (acpi_id[0x62] high level lint[0x1])
[    2.338405][    T0] ACPI: LAPIC_NMI (acpi_id[0x63] high level lint[0x1])
[    2.345870][    T0] ACPI: LAPIC_NMI (acpi_id[0x64] high level lint[0x1])
[    2.353337][    T0] ACPI: LAPIC_NMI (acpi_id[0x65] high level lint[0x1])
[    2.360803][    T0] ACPI: LAPIC_NMI (acpi_id[0x66] high level lint[0x1])
[    2.368269][    T0] ACPI: LAPIC_NMI (acpi_id[0x67] high level lint[0x1])
[    2.375734][    T0] ACPI: LAPIC_NMI (acpi_id[0x68] high level lint[0x1])
[    2.383201][    T0] ACPI: LAPIC_NMI (acpi_id[0x69] high level lint[0x1])
[    2.390666][    T0] ACPI: LAPIC_NMI (acpi_id[0x6a] high level lint[0x1])
[    2.398133][    T0] ACPI: LAPIC_NMI (acpi_id[0x6b] high level lint[0x1])
[    2.405600][    T0] ACPI: LAPIC_NMI (acpi_id[0x6c] high level lint[0x1])
[    2.413066][    T0] ACPI: LAPIC_NMI (acpi_id[0x6d] high level lint[0x1])
[    2.420531][    T0] ACPI: LAPIC_NMI (acpi_id[0x6e] high level lint[0x1])
[    2.427998][    T0] ACPI: LAPIC_NMI (acpi_id[0x6f] high level lint[0x1])
[    2.435463][    T0] ACPI: LAPIC_NMI (acpi_id[0x70] high level lint[0x1])
[    2.442931][    T0] ACPI: LAPIC_NMI (acpi_id[0x71] high level lint[0x1])
[    2.450396][    T0] ACPI: LAPIC_NMI (acpi_id[0x72] high level lint[0x1])
[    2.457862][    T0] ACPI: LAPIC_NMI (acpi_id[0x73] high level lint[0x1])
[    2.465328][    T0] ACPI: LAPIC_NMI (acpi_id[0x74] high level lint[0x1])
[    2.472793][    T0] ACPI: LAPIC_NMI (acpi_id[0x75] high level lint[0x1])
[    2.480260][    T0] ACPI: LAPIC_NMI (acpi_id[0x76] high level lint[0x1])
[    2.487726][    T0] ACPI: LAPIC_NMI (acpi_id[0x77] high level lint[0x1])
[    2.495192][    T0] ACPI: LAPIC_NMI (acpi_id[0x78] high level lint[0x1])
[    2.502658][    T0] ACPI: LAPIC_NMI (acpi_id[0x79] high level lint[0x1])
[    2.510124][    T0] ACPI: LAPIC_NMI (acpi_id[0x7a] high level lint[0x1])
[    2.517591][    T0] ACPI: LAPIC_NMI (acpi_id[0x7b] high level lint[0x1])
[    2.525056][    T0] ACPI: LAPIC_NMI (acpi_id[0x7c] high level lint[0x1])
[    2.532522][    T0] ACPI: LAPIC_NMI (acpi_id[0x7c] high level lint[0x1])
[    2.539989][    T0] ACPI: LAPIC_NMI (acpi_id[0x7d] high level lint[0x1])
[    2.547454][    T0] ACPI: LAPIC_NMI (acpi_id[0x7e] high level lint[0x1])
[    2.554920][    T0] ACPI: LAPIC_NMI (acpi_id[0x7f] high level lint[0x1])
[    2.562388][    T0] ACPI: LAPIC_NMI (acpi_id[0x80] high level lint[0x1])
[    2.569853][    T0] ACPI: LAPIC_NMI (acpi_id[0x81] high level lint[0x1])
[    2.577320][    T0] ACPI: LAPIC_NMI (acpi_id[0x82] high level lint[0x1])
[    2.584785][    T0] ACPI: LAPIC_NMI (acpi_id[0x83] high level lint[0x1])
[    2.592252][    T0] ACPI: LAPIC_NMI (acpi_id[0x84] high level lint[0x1])
[    2.599717][    T0] ACPI: LAPIC_NMI (acpi_id[0x85] high level lint[0x1])
[    2.607182][    T0] ACPI: LAPIC_NMI (acpi_id[0x86] high level lint[0x1])
[    2.614649][    T0] ACPI: LAPIC_NMI (acpi_id[0x87] high level lint[0x1])
[    2.622116][    T0] ACPI: LAPIC_NMI (acpi_id[0x88] high level lint[0x1])
[    2.629581][    T0] ACPI: LAPIC_NMI (acpi_id[0x89] high level lint[0x1])
[    2.637048][    T0] ACPI: LAPIC_NMI (acpi_id[0x8a] high level lint[0x1])
[    2.644513][    T0] ACPI: LAPIC_NMI (acpi_id[0x8b] high level lint[0x1])
[    2.651979][    T0] ACPI: LAPIC_NMI (acpi_id[0x8c] high level lint[0x1])
[    2.659446][    T0] ACPI: LAPIC_NMI (acpi_id[0x8d] high level lint[0x1])
[    2.666912][    T0] ACPI: LAPIC_NMI (acpi_id[0x8f] high level lint[0x1])
[    2.674393][    T0] IOAPIC[0]: apic_id 8, version 32, address 0xfec00000, GSI 0-23
[    2.682820][    T0] IOAPIC[1]: apic_id 9, version 32, address 0xfec01000, GSI 24-47
[    2.691350][    T0] IOAPIC[2]: apic_id 10, version 32, address 0xfec40000, GSI 48-71
[    2.699980][    T0] IOAPIC[3]: apic_id 11, version 32, address 0xfec80000, GSI 72-95
[    2.708610][    T0] IOAPIC[4]: apic_id 12, version 32, address 0xfecc0000, GSI 96-119
[    2.717337][    T0] ACPI: INT_SRC_OVR (bus 0 bus_irq 0 global_irq 2 dfl dfl)
[    2.725192][    T0] Int: type 0, pol 0, trig 0, bus 00, IRQ 00, APIC ID 8, APIC INT 02
[    2.734009][    T0] ACPI: INT_SRC_OVR (bus 0 bus_irq 9 global_irq 9 high level)
[    2.742154][    T0] Int: type 0, pol 1, trig 3, bus 00, IRQ 09, APIC ID 8, APIC INT 09
[    2.750980][    T0] Int: type 0, pol 0, trig 0, bus 00, IRQ 01, APIC ID 8, APIC INT 01
[    2.759800][    T0] Int: type 0, pol 0, trig 0, bus 00, IRQ 03, APIC ID 8, APIC INT 03
[    2.768625][    T0] Int: type 0, pol 0, trig 0, bus 00, IRQ 04, APIC ID 8, APIC INT 04
[    2.777448][    T0] Int: type 0, pol 0, trig 0, bus 00, IRQ 05, APIC ID 8, APIC INT 05
[    2.786271][    T0] Int: type 0, pol 0, trig 0, bus 00, IRQ 06, APIC ID 8, APIC INT 06
[    2.795095][    T0] Int: type 0, pol 0, trig 0, bus 00, IRQ 07, APIC ID 8, APIC INT 07
[    2.803920][    T0] Int: type 0, pol 0, trig 0, bus 00, IRQ 08, APIC ID 8, APIC INT 08
[    2.812743][    T0] Int: type 0, pol 0, trig 0, bus 00, IRQ 0a, APIC ID 8, APIC INT 0a
[    2.821566][    T0] Int: type 0, pol 0, trig 0, bus 00, IRQ 0b, APIC ID 8, APIC INT 0b
[    2.830390][    T0] Int: type 0, pol 0, trig 0, bus 00, IRQ 0c, APIC ID 8, APIC INT 0c
[    2.839213][    T0] Int: type 0, pol 0, trig 0, bus 00, IRQ 0d, APIC ID 8, APIC INT 0d
[    2.848037][    T0] Int: type 0, pol 0, trig 0, bus 00, IRQ 0e, APIC ID 8, APIC INT 0e
[    2.856860][    T0] Int: type 0, pol 0, trig 0, bus 00, IRQ 0f, APIC ID 8, APIC INT 0f
[    2.865688][    T0] ACPI: Using ACPI (MADT) for SMP configuration information
[    2.873638][    T0] ACPI: HPET id: 0x8086a301 base: 0xfed00000
[    2.880141][    T0] ACPI: SPCR: SPCR table version 1
[    2.885663][    T0] ACPI: SPCR: console: uart,io,0x3f8,115200
[    2.892059][    T0] TSC deadline timer available
[    2.897200][    T0] smpboot: Allowing 144 CPUs, 0 hotplug CPUs
[    2.903702][    T0] mapped IOAPIC to ffffffffff5fb000 (fec00000)
[    2.910384][    T0] mapped IOAPIC to ffffffffff5fa000 (fec01000)
[    2.917074][    T0] mapped IOAPIC to ffffffffff5f9000 (fec40000)
[    2.923764][    T0] mapped IOAPIC to ffffffffff5f8000 (fec80000)
[    2.930454][    T0] mapped IOAPIC to ffffffffff5f7000 (fecc0000)
[    2.937163][    T0] PM: hibernation: Registered nosave memory: [mem 0x00000000-0x00000fff]
[    2.946357][    T0] PM: hibernation: Registered nosave memory: [mem 0x0009d000-0x0009ffff]
[    2.955567][    T0] PM: hibernation: Registered nosave memory: [mem 0x000a0000-0x000dffff]
[    2.964779][    T0] PM: hibernation: Registered nosave memory: [mem 0x000e0000-0x000fffff]
[    2.973991][    T0] PM: hibernation: Registered nosave memory: [mem 0x73bed000-0x74621fff]
[    2.983202][    T0] PM: hibernation: Registered nosave memory: [mem 0x74622000-0x7689dfff]
[    2.992413][    T0] PM: hibernation: Registered nosave memory: [mem 0x7689e000-0x7699dfff]
[    3.001627][    T0] PM: hibernation: Registered nosave memory: [mem 0x7b800000-0x8fffffff]
[    3.010835][    T0] PM: hibernation: Registered nosave memory: [mem 0x90000000-0xfed1bfff]
[    3.020048][    T0] PM: hibernation: Registered nosave memory: [mem 0xfed1c000-0xfed1ffff]
[    3.029259][    T0] PM: hibernation: Registered nosave memory: [mem 0xfed20000-0xff7fffff]
[    3.038469][    T0] PM: hibernation: Registered nosave memory: [mem 0xff800000-0xffffffff]
[    3.047682][    T0] PM: hibernation: Registered nosave memory: [mem 0x100000000-0x1effffffff]
[    3.057184][    T0] PM: hibernation: Registered nosave memory: [mem 0x2080000000-0x3e7fffffff]
[    3.066785][    T0] PM: hibernation: Registered nosave memory: [mem 0x4080000000-0x5e7fffffff]
[    3.076382][    T0] PM: hibernation: Registered nosave memory: [mem 0x6080000000-0x7e7fffffff]
[    3.085986][    T0] [mem 0x90000000-0xfed1bfff] available for PCI devices
[    3.093544][    T0] Booting paravirtualized kernel on bare hardware
[    3.100533][    T0] clocksource: refined-jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 1910969940391419 ns
[    3.118398][    T0] setup_percpu: NR_CPUS:8192 nr_cpumask_bits:144 nr_cpu_ids:144 nr_node_ids:4
[    3.141210][    T0] percpu: Embedded 54 pages/cpu s183208 r8192 d29784 u262144
[    3.149096][    T0] pcpu-alloc: s183208 r8192 d29784 u262144 alloc=1*2097152
[    3.156934][    T0] pcpu-alloc: [0] 000 001 002 003 004 005 006 007 
[    3.164012][    T0] pcpu-alloc: [0] 008 009 010 011 012 013 014 015 
[    3.171089][    T0] pcpu-alloc: [0] 016 017 072 073 074 075 076 077 
[    3.178168][    T0] pcpu-alloc: [0] 078 079 080 081 082 083 084 085 
[    3.185246][    T0] pcpu-alloc: [0] 086 087 088 089 --- --- --- --- 
[    3.192325][    T0] pcpu-alloc: [1] 018 019 020 021 022 023 024 025 
[    3.199403][    T0] pcpu-alloc: [1] 026 027 028 029 030 031 032 033 
[    3.206480][    T0] pcpu-alloc: [1] 034 035 090 091 092 093 094 095 
[    3.213559][    T0] pcpu-alloc: [1] 096 097 098 099 100 101 102 103 
[    3.220637][    T0] pcpu-alloc: [1] 104 105 106 107 --- --- --- --- 
[    3.227718][    T0] pcpu-alloc: [2] 036 037 038 039 040 041 042 043 
[    3.234793][    T0] pcpu-alloc: [2] 044 045 046 047 048 049 050 051 
[    3.241871][    T0] pcpu-alloc: [2] 052 053 108 109 110 111 112 113 
[    3.248950][    T0] pcpu-alloc: [2] 114 115 116 117 118 119 120 121 
[    3.256028][    T0] pcpu-alloc: [2] 122 123 124 125 --- --- --- --- 
[    3.263107][    T0] pcpu-alloc: [3] 054 055 056 057 058 059 060 061 
[    3.270186][    T0] pcpu-alloc: [3] 062 063 064 065 066 067 068 069 
[    3.277263][    T0] pcpu-alloc: [3] 070 071 126 127 128 129 130 131 
[    3.284343][    T0] pcpu-alloc: [3] 132 133 134 135 136 137 138 139 
[    3.291419][    T0] pcpu-alloc: [3] 140 141 142 143 --- --- --- --- 
[    3.298556][    T0] Fallback order for Node 0: 0 1 2 3 
[    3.304318][    T0] Fallback order for Node 1: 1 2 3 0 
[    3.310137][    T0] Fallback order for Node 2: 2 3 0 1 
[    3.315954][    T0] Fallback order for Node 3: 3 0 1 2 
[    3.321783][    T0] Built 4 zonelists, mobility grouping on.  Total pages: 8227621
[    3.330205][    T0] Policy zone: Normal
[    3.334477][    T0] Kernel command line: ip=::::lkp-hsw-4ex1::dhcp root=/dev/ram0 RESULT_ROOT=/result/vm-scalability/performance-4-64-1-swap-w-seq-never-never/lkp-hsw-4ex1/debian-11.1-x86_64-20220510.cgz/x86_64-rhel-8.3/gcc-11/6919cda8e0f127fe773cad2553f0648de1c48445/0 BOOT_IMAGE=/pkg/linux/x86_64-rhel-8.3/gcc-11/6919cda8e0f127fe773cad2553f0648de1c48445/vmlinuz-6.1.0-rc5-00020-g6919cda8e0f1 branch=linux-devel/devel-hourly-20221209-093320 job=/lkp/jobs/scheduled/lkp-hsw-4ex1/vm-scalability-performance-4-64-1-swap-w-seq-never-never-debian-11.1-x86_64-20220510.cgz-6919cda8e0f127fe773cad2553f0648de1c4844-20221210-31307-1s05up6-0.yaml user=lkp ARCH=x86_64 kconfig=x86_64-rhel-8.3 commit=6919cda8e0f127fe773cad2553f0648de1c48445 initcall_debug cma=0 memmap=120G!4G memmap=120G!130G memmap=120G!258G memmap=120G!386G max_uptime=2100 LKP_SERVER=internal-lkp-server nokaslr selinux=0 debug apic=debug sysrq_always_enabled rcupdate.rcu_cpu_stall_timeout=100 net.ifnames=0 printk.devkmsg=on panic
[    3.334758][    T0] sysrq: sysrq always enabled.
[    3.436552][    T0] ignoring the deprecated load_ramdisk= option
[    3.443272][    T0] Unknown kernel command line parameters "nokaslr RESULT_ROOT=/result/vm-scalability/performance-4-64-1-swap-w-seq-never-never/lkp-hsw-4ex1/debian-11.1-x86_64-20220510.cgz/x86_64-rhel-8.3/gcc-11/6919cda8e0f127fe773cad2553f0648de1c48445/0 BOOT_IMAGE=/pkg/linux/x86_64-rhel-8.3/gcc-11/6919cda8e0f127fe773cad2553f0648de1c48445/vmlinuz-6.1.0-rc5-00020-g6919cda8e0f1 branch=linux-devel/devel-hourly-20221209-093320 job=/lkp/jobs/scheduled/lkp-hsw-4ex1/vm-scalability-performance-4-64-1-swap-w-seq-never-never-debian-11.1-x86_64-20220510.cgz-6919cda8e0f127fe773cad2553f0648de1c4844-20221210-31307-1s05up6-0.yaml user=lkp ARCH=x86_64 kconfig=x86_64-rhel-8.3 commit=6919cda8e0f127fe773cad2553f0648de1c48445 cma=0 max_uptime=2100 LKP_SERVER=internal-lkp-server selinux=0 softlockup_panic=1 prompt_ramdisk=0 vga=normal", will be passed to user space.
[    3.526879][    T0] random: crng init done
[    3.531407][    T0] printk: log_buf_len individual max cpu contribution: 4096 bytes
[    3.539937][    T0] printk: log_buf_len total cpu_extra contributions: 585728 bytes
[    3.548470][    T0] printk: log_buf_len min size: 1048576 bytes
[    3.558695][    T0] printk: log_buf_len: 2097152 bytes
[    3.564233][    T0] printk: early log buf free: 1014056(96%)
[    3.572570][    T0] mem auto-init: stack:off, heap alloc:off, heap free:off
[    3.580149][    T0] software IO TLB: area num 256.
[    3.638752][    T0] Memory: 2434108K/33433516K available (16393K kernel code, 5763K rwdata, 9328K rodata, 2788K init, 2824K bss, 1922912K reserved, 0K cma-reserved)
[    3.656178][    T0] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=144, Nodes=4
[    3.664315][    T0] Kernel/User page tables isolation: enabled
[    3.670843][    T0] ftrace: allocating 47087 entries in 184 pages
[    3.689699][    T0] ftrace: allocated 184 pages with 4 groups
[    3.697302][    T0] rcu: Hierarchical RCU implementation.
[    3.703120][    T0] rcu: 	RCU restricting CPUs from NR_CPUS=8192 to nr_cpu_ids=144.
[    3.711657][    T0] 	RCU CPU stall warnings timeout set to 100 (rcu_cpu_stall_timeout).
[    3.720573][    T0] 	Rude variant of Tasks RCU enabled.
[    3.726390][    T0] 	Tracing variant of Tasks RCU enabled.
[    3.732501][    T0] rcu: RCU calculated value of scheduler-enlistment delay is 100 jiffies.
[    3.741807][    T0] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=144
[    3.755319][    T0] NR_IRQS: 524544, nr_irqs: 3208, preallocated irqs: 16
[    3.763064][    T0] rcu: srcu_init: Setting srcu_struct sizes to big.
[    3.770400][    T0] calling  con_init+0x0/0x22f @ 0
[    3.778017][    T0] Console: colour VGA+ 80x25
[    3.853890][    T0] printk: console [tty0] enabled
[    3.859148][    T0] initcall con_init+0x0/0x22f returned 0 after 0 usecs
[    3.866620][    T0] calling  hvc_console_init+0x0/0x18 @ 0
[    3.872725][    T0] initcall hvc_console_init+0x0/0x18 returned 0 after 0 usecs
[    3.880902][    T0] calling  univ8250_console_init+0x0/0x2b @ 0
[    3.887486][    T0] printk: console [ttyS0] enabled
[    3.887486][    T0] printk: console [ttyS0] enabled
[    3.898332][    T0] printk: bootconsole [earlyser0] disabled
[    3.898332][    T0] printk: bootconsole [earlyser0] disabled
[    3.910944][    T0] initcall univ8250_console_init+0x0/0x2b returned 0 after 0 usecs
[    3.920363][    T0] mempolicy: Enabling automatic NUMA balancing. Configure with numa_balancing= or the kernel.numa_balancing sysctl
[    3.933826][    T0] ACPI: Core revision 20220331
[    3.939824][    T0] clocksource: hpet: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 133484882848 ns
[    3.950976][    T0] APIC: Switch to symmetric I/O mode setup
[    3.957593][    T0] x2apic: IRQ remapping doesn't support X2APIC mode
[    3.965026][    T0] Switched APIC routing to physical flat.
[    3.971366][    T0] masked ExtINT on CPU#0
[    3.976682][    T0] ENABLING IO-APIC IRQs
[    3.981278][    T0] init IO_APIC IRQs
[    3.985467][    T0]  apic 8 pin 0 not connected
[    3.991967][    T0] IOAPIC[0]: Preconfigured routing entry (8-1 -> IRQ 1 Level:0 ActiveLow:0)
[    4.001634][    T0] IOAPIC[0]: Preconfigured routing entry (8-2 -> IRQ 0 Level:0 ActiveLow:0)
[    4.011299][    T0] IOAPIC[0]: Preconfigured routing entry (8-3 -> IRQ 3 Level:0 ActiveLow:0)
[    4.020968][    T0] IOAPIC[0]: Preconfigured routing entry (8-4 -> IRQ 4 Level:0 ActiveLow:0)
[    4.030635][    T0] IOAPIC[0]: Preconfigured routing entry (8-5 -> IRQ 5 Level:0 ActiveLow:0)
[    4.040291][    T0] IOAPIC[0]: Preconfigured routing entry (8-6 -> IRQ 6 Level:0 ActiveLow:0)
[    4.049957][    T0] IOAPIC[0]: Preconfigured routing entry (8-7 -> IRQ 7 Level:0 ActiveLow:0)
[    4.059622][    T0] IOAPIC[0]: Preconfigured routing entry (8-8 -> IRQ 8 Level:0 ActiveLow:0)
[    4.069288][    T0] IOAPIC[0]: Preconfigured routing entry (8-9 -> IRQ 9 Level:1 ActiveLow:0)
[    4.078958][    T0] IOAPIC[0]: Preconfigured routing entry (8-10 -> IRQ 10 Level:0 ActiveLow:0)
[    4.088820][    T0] IOAPIC[0]: Preconfigured routing entry (8-11 -> IRQ 11 Level:0 ActiveLow:0)
[    4.098680][    T0] IOAPIC[0]: Preconfigured routing entry (8-12 -> IRQ 12 Level:0 ActiveLow:0)
[    4.108542][    T0] IOAPIC[0]: Preconfigured routing entry (8-13 -> IRQ 13 Level:0 ActiveLow:0)
[    4.118401][    T0] IOAPIC[0]: Preconfigured routing entry (8-14 -> IRQ 14 Level:0 ActiveLow:0)
[    4.128262][    T0] IOAPIC[0]: Preconfigured routing entry (8-15 -> IRQ 15 Level:0 ActiveLow:0)
[    4.138118][    T0]  apic 8 pin 16 not connected
[    4.143379][    T0]  apic 8 pin 17 not connected
[    4.148639][    T0]  apic 8 pin 18 not connected
[    4.153899][    T0]  apic 8 pin 19 not connected
[    4.159159][    T0]  apic 8 pin 20 not connected
[    4.164419][    T0]  apic 8 pin 21 not connected
[    4.169680][    T0]  apic 8 pin 22 not connected
[    4.174940][    T0]  apic 8 pin 23 not connected
[    4.180201][    T0]  apic 9 pin 0 not connected
[    4.185362][    T0]  apic 9 pin 1 not connected
[    4.190516][    T0]  apic 9 pin 2 not connected
[    4.195669][    T0]  apic 9 pin 3 not connected
[    4.200822][    T0]  apic 9 pin 4 not connected
[    4.205984][    T0]  apic 9 pin 5 not connected
[    4.211137][    T0]  apic 9 pin 6 not connected
[    4.216290][    T0]  apic 9 pin 7 not connected
[    4.221443][    T0]  apic 9 pin 8 not connected
[    4.226605][    T0]  apic 9 pin 9 not connected
[    4.231766][    T0]  apic 9 pin 10 not connected
[    4.237026][    T0]  apic 9 pin 11 not connected
[    4.242286][    T0]  apic 9 pin 12 not connected
[    4.247546][    T0]  apic 9 pin 13 not connected
[    4.252806][    T0]  apic 9 pin 14 not connected
[    4.258066][    T0]  apic 9 pin 15 not connected
[    4.263326][    T0]  apic 9 pin 16 not connected
[    4.268586][    T0]  apic 9 pin 17 not connected
[    4.273847][    T0]  apic 9 pin 18 not connected
[    4.279107][    T0]  apic 9 pin 19 not connected
[    4.284367][    T0]  apic 9 pin 20 not connected
[    4.289627][    T0]  apic 9 pin 21 not connected
[    4.294887][    T0]  apic 9 pin 22 not connected
[    4.300147][    T0]  apic 9 pin 23 not connected
[    4.305407][    T0]  apic 10 pin 0 not connected
[    4.310667][    T0]  apic 10 pin 1 not connected
[    4.315927][    T0]  apic 10 pin 2 not connected
[    4.321188][    T0]  apic 10 pin 3 not connected
[    4.326448][    T0]  apic 10 pin 4 not connected
[    4.331708][    T0]  apic 10 pin 5 not connected
[    4.336968][    T0]  apic 10 pin 6 not connected
[    4.342228][    T0]  apic 10 pin 7 not connected
[    4.347491][    T0]  apic 10 pin 8 not connected
[    4.352752][    T0]  apic 10 pin 9 not connected
[    4.358016][    T0]  apic 10 pin 10 not connected
[    4.363374][    T0]  apic 10 pin 11 not connected
[    4.368732][    T0]  apic 10 pin 12 not connected
[    4.374091][    T0]  apic 10 pin 13 not connected
[    4.379447][    T0]  apic 10 pin 14 not connected
[    4.384795][    T0]  apic 10 pin 15 not connected
[    4.390151][    T0]  apic 10 pin 16 not connected
[    4.395508][    T0]  apic 10 pin 17 not connected
[    4.400864][    T0]  apic 10 pin 18 not connected
[    4.406220][    T0]  apic 10 pin 19 not connected
[    4.411576][    T0]  apic 10 pin 20 not connected
[    4.416933][    T0]  apic 10 pin 21 not connected
[    4.422289][    T0]  apic 10 pin 22 not connected
[    4.427645][    T0]  apic 10 pin 23 not connected
[    4.433001][    T0]  apic 11 pin 0 not connected
[    4.438261][    T0]  apic 11 pin 1 not connected
[    4.443522][    T0]  apic 11 pin 2 not connected
[    4.448782][    T0]  apic 11 pin 3 not connected
[    4.454042][    T0]  apic 11 pin 4 not connected
[    4.459304][    T0]  apic 11 pin 5 not connected
[    4.464564][    T0]  apic 11 pin 6 not connected
[    4.469826][    T0]  apic 11 pin 7 not connected
[    4.475086][    T0]  apic 11 pin 8 not connected
[    4.480347][    T0]  apic 11 pin 9 not connected
[    4.485608][    T0]  apic 11 pin 10 not connected
[    4.490964][    T0]  apic 11 pin 11 not connected
[    4.496320][    T0]  apic 11 pin 12 not connected
[    4.501677][    T0]  apic 11 pin 13 not connected
[    4.507034][    T0]  apic 11 pin 14 not connected
[    4.512394][    T0]  apic 11 pin 15 not connected
[    4.517750][    T0]  apic 11 pin 16 not connected
[    4.523106][    T0]  apic 11 pin 17 not connected
[    4.528466][    T0]  apic 11 pin 18 not connected
[    4.533824][    T0]  apic 11 pin 19 not connected
[    4.539180][    T0]  apic 11 pin 20 not connected
[    4.544537][    T0]  apic 11 pin 21 not connected
[    4.549896][    T0]  apic 11 pin 22 not connected
[    4.555253][    T0]  apic 11 pin 23 not connected
[    4.560609][    T0]  apic 12 pin 0 not connected
[    4.565869][    T0]  apic 12 pin 1 not connected
[    4.571129][    T0]  apic 12 pin 2 not connected
[    4.576390][    T0]  apic 12 pin 3 not connected
[    4.581650][    T0]  apic 12 pin 4 not connected
[    4.586911][    T0]  apic 12 pin 5 not connected
[    4.592173][    T0]  apic 12 pin 6 not connected
[    4.597436][    T0]  apic 12 pin 7 not connected
[    4.602697][    T0]  apic 12 pin 8 not connected
[    4.607959][    T0]  apic 12 pin 9 not connected
[    4.613223][    T0]  apic 12 pin 10 not connected
[    4.618580][    T0]  apic 12 pin 11 not connected
[    4.623938][    T0]  apic 12 pin 12 not connected
[    4.629294][    T0]  apic 12 pin 13 not connected
[    4.634651][    T0]  apic 12 pin 14 not connected
[    4.639999][    T0]  apic 12 pin 15 not connected
[    4.645354][    T0]  apic 12 pin 16 not connected
[    4.650702][    T0]  apic 12 pin 17 not connected
[    4.656058][    T0]  apic 12 pin 18 not connected
[    4.661415][    T0]  apic 12 pin 19 not connected
[    4.666771][    T0]  apic 12 pin 20 not connected
[    4.672127][    T0]  apic 12 pin 21 not connected
[    4.677474][    T0]  apic 12 pin 22 not connected
[    4.682831][    T0]  apic 12 pin 23 not connected
[    4.688320][    T0] ..TIMER: vector=0x30 apic1=0 pin1=2 apic2=-1 pin2=-1
[    4.700012][    T0] clocksource: tsc-early: mask: 0xffffffffffffffff max_cycles: 0x23f2b5acdec, max_idle_ns: 440795289676 ns
[    4.712699][    T0] Calibrating delay loop (skipped), value calculated using timer frequency.. 4987.79 BogoMIPS (lpj=2493898)
[    4.713857][    T0] pid_max: default: 147456 minimum: 1152
[    4.715067][    T0] LSM: Security Framework initializing
[    4.716745][    T0] Yama: becoming mindful.
[    4.717861][    T0] AppArmor: AppArmor initialized
[    4.725520][    T0] Dentry cache hash table entries: 4194304 (order: 13, 33554432 bytes, vmalloc hugepage)
[    4.729641][    T0] Inode-cache hash table entries: 2097152 (order: 12, 16777216 bytes, vmalloc hugepage)
[    4.730040][    T0] Mount-cache hash table entries: 65536 (order: 7, 524288 bytes, vmalloc)
[    4.730957][    T0] Mountpoint-cache hash table entries: 65536 (order: 7, 524288 bytes, vmalloc)
[    4.733230][    T0] CPU0: Thermal monitoring enabled (TM1)
[    4.733873][    T0] process: using mwait in idle threads
[    4.734816][    T0] Last level iTLB entries: 4KB 1024, 2MB 1024, 4MB 1024
[    4.735814][    T0] Last level dTLB entries: 4KB 1024, 2MB 1024, 4MB 1024, 1GB 4
[    4.736854][    T0] Spectre V1 : Mitigation: usercopy/swapgs barriers and __user pointer sanitization
[    4.737857][    T0] Spectre V2 : Mitigation: Retpolines
[    4.738809][    T0] Spectre V2 : Spectre v2 / SpectreRSB mitigation: Filling RSB on context switch
[    4.739846][    T0] Spectre V2 : Spectre v2 / SpectreRSB : Filling RSB on VMEXIT
[    4.740841][    T0] Spectre V2 : Enabling Restricted Speculation for firmware calls
[    4.741848][    T0] Spectre V2 : mitigation: Enabling conditional Indirect Branch Prediction Barrier
[    4.742847][    T0] Spectre V2 : User space: Mitigation: STIBP via prctl
[    4.743816][    T0] Speculative Store Bypass: Mitigation: Speculative Store Bypass disabled via prctl
[    4.745706][    T0] MDS: Mitigation: Clear CPU buffers
[    4.746809][    T0] TAA: Mitigation: Clear CPU buffers
[    4.747809][    T0] MMIO Stale Data: Mitigation: Clear CPU buffers
[    4.770383][    T0] Freeing SMP alternatives memory: 44K
[    4.771070][    T1] smpboot: CPU0: Intel(R) Xeon(R) CPU E7-8890 v3 @ 2.50GHz (family: 0x6, model: 0x3f, stepping: 0x4)
[    4.772206][    T1] cblist_init_generic: Setting adjustable number of callback queues.
[    4.772700][    T1] cblist_init_generic: Setting shift to 8 and lim to 1.
[    4.773889][    T1] cblist_init_generic: Setting shift to 8 and lim to 1.
[    4.775727][    T1] calling  init_hw_perf_events+0x0/0x451 @ 1
[    4.776811][    T1] Performance Events: PEBS fmt2+, Haswell events, 16-deep LBR, full-width counters, Intel PMU driver.
[    4.777856][    T1] ... version:                3
[    4.778807][    T1] ... bit width:              48
[    4.779807][    T1] ... generic registers:      4
[    4.780807][    T1] ... value mask:             0000ffffffffffff
[    4.781811][    T1] ... max period:             00007fffffffffff
[    4.782811][    T1] ... fixed-purpose events:   3
[    4.783807][    T1] ... event mask:             000000070000000f
[    4.785029][    T1] initcall init_hw_perf_events+0x0/0x451 returned 0 after 8000 usecs
[    4.785844][    T1] calling  init_real_mode+0x0/0xc5 @ 1
[    4.786834][    T1] initcall init_real_mode+0x0/0xc5 returned 0 after 0 usecs
[    4.787816][    T1] calling  trace_init_perf_perm_irq_work_exit+0x0/0x17 @ 1
[    4.788816][    T1] initcall trace_init_perf_perm_irq_work_exit+0x0/0x17 returned 0 after 0 usecs
[    4.789846][    T1] calling  bp_init_aperfmperf+0x0/0x2d @ 1
[    4.790828][    T1] Estimated ratio of average max frequency by base frequency (times 1024): 1228
[    4.791848][    T1] initcall bp_init_aperfmperf+0x0/0x2d returned 0 after 1000 usecs
[    4.792843][    T1] calling  register_nmi_cpu_backtrace_handler+0x0/0x1a @ 1
[    4.793816][    T1] initcall register_nmi_cpu_backtrace_handler+0x0/0x1a returned 0 after 0 usecs
[    4.794846][    T1] calling  kvm_setup_vsyscall_timeinfo+0x0/0x5f @ 1
[    4.795814][    T1] initcall kvm_setup_vsyscall_timeinfo+0x0/0x5f returned 0 after 0 usecs
[    4.796844][    T1] calling  spawn_ksoftirqd+0x0/0x3d @ 1
[    4.797838][    T1] initcall spawn_ksoftirqd+0x0/0x3d returned 0 after 0 usecs
[    4.798842][    T1] calling  migration_init+0x0/0x4b @ 1
[    4.799811][    T1] initcall migration_init+0x0/0x4b returned 0 after 0 usecs
[    4.800815][    T1] calling  srcu_bootup_announce+0x0/0x7c @ 1
[    4.801811][    T1] rcu: Hierarchical SRCU implementation.
[    4.802812][    T1] rcu: 	Max phase no-delay instances is 400.
[    4.803812][    T1] initcall srcu_bootup_announce+0x0/0x7c returned 0 after 2000 usecs
[    4.804843][    T1] calling  rcu_spawn_gp_kthread+0x0/0x195 @ 1
[    4.805871][    T1] initcall rcu_spawn_gp_kthread+0x0/0x195 returned 0 after 0 usecs
[    4.806843][    T1] calling  check_cpu_stall_init+0x0/0x1f @ 1
[    4.807815][    T1] initcall check_cpu_stall_init+0x0/0x1f returned 0 after 0 usecs
[    4.808842][    T1] calling  rcu_sysrq_init+0x0/0x26 @ 1
[    4.809809][    T1] initcall rcu_sysrq_init+0x0/0x26 returned 0 after 0 usecs
[    4.810817][    T1] calling  trace_init_flags_sys_enter+0x0/0x13 @ 1
[    4.811812][    T1] initcall trace_init_flags_sys_enter+0x0/0x13 returned 0 after 0 usecs
[    4.812844][    T1] calling  trace_init_flags_sys_exit+0x0/0x13 @ 1
[    4.813812][    T1] initcall trace_init_flags_sys_exit+0x0/0x13 returned 0 after 0 usecs
[    4.814844][    T1] calling  cpu_stop_init+0x0/0x7f @ 1
[    4.815849][    T1] initcall cpu_stop_init+0x0/0x7f returned 0 after 0 usecs
[    4.816817][    T1] calling  init_kprobes+0x0/0x149 @ 1
[    4.817999][    T1] initcall init_kprobes+0x0/0x149 returned 0 after 0 usecs
[    4.818817][    T1] calling  init_events+0x0/0x4d @ 1
[    4.819836][    T1] initcall init_events+0x0/0x4d returned 0 after 0 usecs
[    4.820814][    T1] calling  init_trace_printk+0x0/0xc @ 1
[    4.821811][    T1] initcall init_trace_printk+0x0/0xc returned 0 after 0 usecs
[    4.822841][    T1] calling  event_trace_enable_again+0x0/0x23 @ 1
[    4.823816][    T1] initcall event_trace_enable_again+0x0/0x23 returned 0 after 0 usecs
[    4.824844][    T1] calling  irq_work_init_threads+0x0/0x7 @ 1
[    4.825811][    T1] initcall irq_work_init_threads+0x0/0x7 returned 0 after 0 usecs
[    4.826842][    T1] calling  static_call_init+0x0/0x89 @ 1
[    4.827809][    T1] initcall static_call_init+0x0/0x89 returned 0 after 0 usecs
[    4.828842][    T1] calling  jump_label_init_module+0x0/0x11 @ 1
[    4.829811][    T1] initcall jump_label_init_module+0x0/0x11 returned 0 after 0 usecs
[    4.830843][    T1] calling  init_zero_pfn+0x0/0x3c @ 1
[    4.831811][    T1] initcall init_zero_pfn+0x0/0x3c returned 0 after 0 usecs
[    4.832814][    T1] calling  init_fs_inode_sysctls+0x0/0x26 @ 1
[    4.833815][    T1] initcall init_fs_inode_sysctls+0x0/0x26 returned 0 after 0 usecs
[    4.834842][    T1] calling  init_fs_locks_sysctls+0x0/0x26 @ 1
[    4.835819][    T1] initcall init_fs_locks_sysctls+0x0/0x26 returned 0 after 0 usecs
[    4.836842][    T1] calling  dynamic_debug_init+0x0/0x231 @ 1
[    4.837932][    T1] initcall dynamic_debug_init+0x0/0x231 returned 0 after 0 usecs
[    4.838843][    T1] calling  efi_memreserve_root_init+0x0/0x2a @ 1
[    4.839817][    T1] initcall efi_memreserve_root_init+0x0/0x2a returned 0 after 0 usecs
[    4.840844][    T1] calling  efi_earlycon_remap_fb+0x0/0x56 @ 1
[    4.841813][    T1] initcall efi_earlycon_remap_fb+0x0/0x56 returned 0 after 0 usecs
[    4.842844][    T1] calling  bpf_dispatcher_xdp_init+0x0/0x11 @ 1
[    4.843817][    T1] initcall bpf_dispatcher_xdp_init+0x0/0x11 returned 0 after 0 usecs
[    4.858008][    T7] NMI watchdog: Enabled. Permanently consumes one hw-PMU counter.
[    4.861546][    T1] smp: Bringing up secondary CPUs ...
[    4.861993][    T1] x86: Booting SMP configuration:
[    4.862810][    T1] .... node  #0, CPUs:          #1
[    0.933581][    T0] masked ExtINT on CPU#1
[    4.874946][    T1]    #2
[    0.933581][    T0] masked ExtINT on CPU#2
[    4.884906][    T1]    #3
[    0.933581][    T0] masked ExtINT on CPU#3
[    4.894906][    T1]    #4
[    0.933581][    T0] masked ExtINT on CPU#4
[    4.904721][    T1]    #5
[    0.933581][    T0] masked ExtINT on CPU#5
[    4.914236][    T1]    #6
[    0.933581][    T0] masked ExtINT on CPU#6
[    4.924099][    T1]    #7
[    0.933581][    T0] masked ExtINT on CPU#7
[    4.933922][    T1]    #8
[    0.933581][    T0] masked ExtINT on CPU#8
[    4.943909][    T1]    #9
[    0.933581][    T0] masked ExtINT on CPU#9
[    4.953924][    T1]   #10
[    0.933581][    T0] masked ExtINT on CPU#10
[    4.963878][    T1]   #11
[    0.933581][    T0] masked ExtINT on CPU#11
[    4.973858][    T1]   #12
[    0.933581][    T0] masked ExtINT on CPU#12
[    4.983887][    T1]   #13
[    0.933581][    T0] masked ExtINT on CPU#13
[    4.993904][    T1]   #14
[    0.933581][    T0] masked ExtINT on CPU#14
[    5.003798][    T1]   #15
[    0.933581][    T0] masked ExtINT on CPU#15
[    5.013725][    T1]   #16
[    0.933581][    T0] masked ExtINT on CPU#16
[    5.023280][    T1]   #17
[    0.933581][    T0] masked ExtINT on CPU#17
[    5.033712][    T1] 
[    5.035019][    T1] .... node  #1, CPUs:    #18
[    0.933581][    T0] masked ExtINT on CPU#18
[    0.933581][    T0] smpboot: CPU 18 Converting physical 0 to logical die 1
[    5.114889][    T1]   #19
[    0.933581][    T0] masked ExtINT on CPU#19
[    5.124941][    T1]   #20
[    0.933581][    T0] masked ExtINT on CPU#20
[    5.134892][    T1]   #21
[    0.933581][    T0] masked ExtINT on CPU#21
[    5.144891][    T1]   #22
[    0.933581][    T0] masked ExtINT on CPU#22
[    5.154890][    T1]   #23
[    0.933581][    T0] masked ExtINT on CPU#23
[    5.164894][    T1]   #24
[    0.933581][    T0] masked ExtINT on CPU#24
[    5.174893][    T1]   #25
[    0.933581][    T0] masked ExtINT on CPU#25
[    5.184895][    T1]   #26
[    0.933581][    T0] masked ExtINT on CPU#26
[    5.194903][    T1]   #27
[    0.933581][    T0] masked ExtINT on CPU#27
[    5.204896][    T1]   #28
[    0.933581][    T0] masked ExtINT on CPU#28
[    5.214839][    T1]   #29
[    0.933581][    T0] masked ExtINT on CPU#29
[    5.224853][    T1]   #30
[    0.933581][    T0] masked ExtINT on CPU#30
[    5.234903][    T1]   #31
[    0.933581][    T0] masked ExtINT on CPU#31
[    5.244904][    T1]   #32
[    0.933581][    T0] masked ExtINT on CPU#32
[    5.254902][    T1]   #33
[    0.933581][    T0] masked ExtINT on CPU#33
[    5.264905][    T1]   #34
[    0.933581][    T0] masked ExtINT on CPU#34
[    5.274907][    T1]   #35
[    0.933581][    T0] masked ExtINT on CPU#35
[    5.284912][    T1] 
[    5.286012][    T1] .... node  #2, CPUs:    #36
[    0.933581][    T0] masked ExtINT on CPU#36
[    0.933581][    T0] smpboot: CPU 36 Converting physical 0 to logical die 2
[    5.365881][    T1]   #37
[    0.933581][    T0] masked ExtINT on CPU#37
[    5.375988][    T1]   #38
[    0.933581][    T0] masked ExtINT on CPU#38
[    5.385951][    T1]   #39
[    0.933581][    T0] masked ExtINT on CPU#39
[    5.395937][    T1]   #40
[    0.933581][    T0] masked ExtINT on CPU#40
[    5.405925][    T1]   #41
[    0.933581][    T0] masked ExtINT on CPU#41
[    5.416234][    T1]   #42
[    0.933581][    T0] masked ExtINT on CPU#42
[    5.426281][    T1]   #43
[    0.933581][    T0] masked ExtINT on CPU#43
[    5.436208][    T1]   #44
[    0.933581][    T0] masked ExtINT on CPU#44
[    5.446169][    T1]   #45
[    0.933581][    T0] masked ExtINT on CPU#45
[    5.456043][    T1]   #46
[    0.933581][    T0] masked ExtINT on CPU#46
[    5.466041][    T1]   #47
[    0.933581][    T0] masked ExtINT on CPU#47
[    5.476105][    T1]   #48
[    0.933581][    T0] masked ExtINT on CPU#48
[    5.486180][    T1]   #49
[    0.933581][    T0] masked ExtINT on CPU#49
[    5.496164][    T1]   #50
[    0.933581][    T0] masked ExtINT on CPU#50
[    5.506158][    T1]   #51
[    0.933581][    T0] masked ExtINT on CPU#51
[    5.516179][    T1]   #52
[    0.933581][    T0] masked ExtINT on CPU#52
[    5.526291][    T1]   #53
[    0.933581][    T0] masked ExtINT on CPU#53
[    5.536728][    T1] 
[    5.538012][    T1] .... node  #3, CPUs:    #54
[    0.933581][    T0] masked ExtINT on CPU#54
[    0.933581][    T0] smpboot: CPU 54 Converting physical 0 to logical die 3
[    5.617872][    T1]   #55
[    0.933581][    T0] masked ExtINT on CPU#55
[    5.627955][    T1]   #56
[    0.933581][    T0] masked ExtINT on CPU#56
[    5.637950][    T1]   #57
[    0.933581][    T0] masked ExtINT on CPU#57
[    5.647952][    T1]   #58
[    0.933581][    T0] masked ExtINT on CPU#58
[    5.657953][    T1]   #59
[    0.933581][    T0] masked ExtINT on CPU#59
[    5.667956][    T1]   #60
[    0.933581][    T0] masked ExtINT on CPU#60
[    5.677953][    T1]   #61
[    0.933581][    T0] masked ExtINT on CPU#61
[    5.687952][    T1]   #62
[    0.933581][    T0] masked ExtINT on CPU#62
[    5.697954][    T1]   #63
[    0.933581][    T0] masked ExtINT on CPU#63
[    5.707953][    T1]   #64
[    0.933581][    T0] masked ExtINT on CPU#64
[    5.717840][    T1]   #65
[    0.933581][    T0] masked ExtINT on CPU#65
[    5.727854][    T1]   #66
[    0.933581][    T0] masked ExtINT on CPU#66
[    5.737960][    T1]   #67
[    0.933581][    T0] masked ExtINT on CPU#67
[    5.747962][    T1]   #68
[    0.933581][    T0] masked ExtINT on CPU#68
[    5.757960][    T1]   #69
[    0.933581][    T0] masked ExtINT on CPU#69
[    5.767961][    T1]   #70
[    0.933581][    T0] masked ExtINT on CPU#70
[    5.777965][    T1]   #71
[    0.933581][    T0] masked ExtINT on CPU#71
[    5.787967][    T1] 
[    5.789011][    T1] .... node  #0, CPUs:    #72
[    0.933581][    T0] masked ExtINT on CPU#72
[    5.799772][    T1] MDS CPU bug present and SMT on, data leak possible. See https://www.kernel.org/doc/html/latest/admin-guide/hw-vuln/mds.html for more details.
[    5.801117][    T1] TAA CPU bug present and SMT on, data leak possible. See https://www.kernel.org/doc/html/latest/admin-guide/hw-vuln/tsx_async_abort.html for more details.
[    5.801894][    T1] MMIO Stale Data CPU bug present and SMT on, data leak possible. See https://www.kernel.org/doc/html/latest/admin-guide/hw-vuln/processor_mmio_stale_data.html for more details.
[    5.803163][    T1]   #73
[    0.933581][    T0] masked ExtINT on CPU#73
[    5.812910][    T1]   #74
[    0.933581][    T0] masked ExtINT on CPU#74
[    5.822832][    T1]   #75
[    0.933581][    T0] masked ExtINT on CPU#75
[    5.832756][    T1]   #76
[    0.933581][    T0] masked ExtINT on CPU#76
[    5.842138][    T1]   #77
[    0.933581][    T0] masked ExtINT on CPU#77
[    5.852116][    T1]   #78
[    0.933581][    T0] masked ExtINT on CPU#78
[    5.862070][    T1]   #79
[    0.933581][    T0] masked ExtINT on CPU#79
[    5.871969][    T1]   #80
[    0.933581][    T0] masked ExtINT on CPU#80
[    5.881970][    T1]   #81
[    0.933581][    T0] masked ExtINT on CPU#81
[    5.891916][    T1]   #82
[    0.933581][    T0] masked ExtINT on CPU#82
[    5.901906][    T1]   #83
[    0.933581][    T0] masked ExtINT on CPU#83
[    5.911905][    T1]   #84
[    0.933581][    T0] masked ExtINT on CPU#84
[    5.921938][    T1]   #85
[    0.933581][    T0] masked ExtINT on CPU#85
[    5.931920][    T1]   #86
[    0.933581][    T0] masked ExtINT on CPU#86
[    5.941914][    T1]   #87
[    0.933581][    T0] masked ExtINT on CPU#87
[    5.951906][    T1]   #88
[    0.933581][    T0] masked ExtINT on CPU#88
[    5.961902][    T1]   #89
[    0.933581][    T0] masked ExtINT on CPU#89
[    5.971948][    T1] 
[    5.973019][    T1] .... node  #1, CPUs:    #90
[    0.933581][    T0] masked ExtINT on CPU#90
[    5.984858][    T1]   #91
[    0.933581][    T0] masked ExtINT on CPU#91
[    5.994870][    T1]   #92
[    0.933581][    T0] masked ExtINT on CPU#92
[    6.004847][    T1]   #93
[    0.933581][    T0] masked ExtINT on CPU#93
[    6.014862][    T1]   #94
[    0.933581][    T0] masked ExtINT on CPU#94
[    6.024841][    T1]   #95
[    0.933581][    T0] masked ExtINT on CPU#95
[    6.034860][    T1]   #96
[    0.933581][    T0] masked ExtINT on CPU#96
[    6.045012][    T1]   #97
[    0.933581][    T0] masked ExtINT on CPU#97
[    6.055013][    T1]   #98
[    0.933581][    T0] masked ExtINT on CPU#98
[    6.065012][    T1]   #99
[    0.933581][    T0] masked ExtINT on CPU#99
[    6.074871][    T1]  #100
[    0.933581][    T0] masked ExtINT on CPU#100
[    6.085015][    T1]  #101
[    0.933581][    T0] masked ExtINT on CPU#101
[    6.095017][    T1]  #102
[    0.933581][    T0] masked ExtINT on CPU#102
[    6.105109][    T1]  #103
[    0.933581][    T0] masked ExtINT on CPU#103
[    6.115789][    T1]  #104
[    0.933581][    T0] masked ExtINT on CPU#104
[    6.125834][    T1]  #105
[    0.933581][    T0] masked ExtINT on CPU#105
[    6.135858][    T1]  #106
[    0.933581][    T0] masked ExtINT on CPU#106
[    6.146023][    T1]  #107
[    0.933581][    T0] masked ExtINT on CPU#107
[    6.156026][    T1] 
[    6.157011][    T1] .... node  #2, CPUs:   #108
[    0.933581][    T0] masked ExtINT on CPU#108
[    6.168848][    T1]  #109
[    0.933581][    T0] masked ExtINT on CPU#109
[    6.179046][    T1]  #110
[    0.933581][    T0] masked ExtINT on CPU#110
[    6.189043][    T1]  #111
[    0.933581][    T0] masked ExtINT on CPU#111
[    6.199113][    T1]  #112
[    0.933581][    T0] masked ExtINT on CPU#112
[    6.209174][    T1]  #113
[    0.933581][    T0] masked ExtINT on CPU#113
[    6.219856][    T1]  #114
[    0.933581][    T0] masked ExtINT on CPU#114
[    6.229836][    T1]  #115
[    0.933581][    T0] masked ExtINT on CPU#115
[    6.240053][    T1]  #116
[    0.933581][    T0] masked ExtINT on CPU#116
[    6.250051][    T1]  #117
[    0.933581][    T0] masked ExtINT on CPU#117
[    6.260050][    T1]  #118
[    0.933581][    T0] masked ExtINT on CPU#118
[    6.270053][    T1]  #119
[    0.933581][    T0] masked ExtINT on CPU#119
[    6.280136][    T1]  #120
[    0.933581][    T0] masked ExtINT on CPU#120
[    6.290818][    T1]  #121
[    0.933581][    T0] masked ExtINT on CPU#121
[    6.300857][    T1]  #122
[    0.933581][    T0] masked ExtINT on CPU#122
[    6.310831][    T1]  #123
[    0.933581][    T0] masked ExtINT on CPU#123
[    6.321060][    T1]  #124
[    0.933581][    T0] masked ExtINT on CPU#124
[    6.331837][    T1]  #125
[    0.933581][    T0] masked ExtINT on CPU#125
[    6.341896][    T1] 
[    6.343012][    T1] .... node  #3, CPUs:   #126
[    0.933581][    T0] masked ExtINT on CPU#126
[    6.354847][    T1]  #127
[    0.933581][    T0] masked ExtINT on CPU#127
[    6.365064][    T1]  #128
[    0.933581][    T0] masked ExtINT on CPU#128
[    6.375062][    T1]  #129
[    0.933581][    T0] masked ExtINT on CPU#129
[    6.385098][    T1]  #130
[    0.933581][    T0] masked ExtINT on CPU#130
[    6.395157][    T1]  #131
[    0.933581][    T0] masked ExtINT on CPU#131
[    6.405859][    T1]  #132
[    0.933581][    T0] masked ExtINT on CPU#132
[    6.415846][    T1]  #133
[    0.933581][    T0] masked ExtINT on CPU#133
[    6.426069][    T1]  #134
[    0.933581][    T0] masked ExtINT on CPU#134
[    6.436068][    T1]  #135
[    0.933581][    T0] masked ExtINT on CPU#135
[    6.446071][    T1]  #136
[    0.933581][    T0] masked ExtINT on CPU#136
[    6.456072][    T1]  #137
[    0.933581][    T0] masked ExtINT on CPU#137
[    6.466834][    T1]  #138
[    0.933581][    T0] masked ExtINT on CPU#138
[    6.476844][    T1]  #139
[    0.933581][    T0] masked ExtINT on CPU#139
[    6.487078][    T1]  #140
[    0.933581][    T0] masked ExtINT on CPU#140
[    6.497076][    T1]  #141
[    0.933581][    T0] masked ExtINT on CPU#141
[    6.507084][    T1]  #142
[    0.933581][    T0] masked ExtINT on CPU#142
[    6.517846][    T1]  #143
[    0.933581][    T0] masked ExtINT on CPU#143
[    6.527776][    T1] smp: Brought up 4 nodes, 144 CPUs
[    6.529022][    T1] smpboot: Max logical packages: 4
[    6.529822][    T1] smpboot: Total of 144 processors activated (719907.19 BogoMIPS)
[    6.552625][  T737] node 0 deferred pages initialised in 12ms
[    6.553461][  T742] node 3 deferred pages initialised in 14ms
[    6.555756][  T740] node 2 deferred pages initialised in 17ms
[    6.558753][  T738] node 1 deferred pages initialised in 19ms
[    6.580837][    T1] devtmpfs: initialized
[    6.585900][    T1] x86/mm: Memory block size: 2048MB
[    6.592351][    T1] calling  bpf_jit_charge_init+0x0/0x40 @ 1
[    6.598816][    T1] initcall bpf_jit_charge_init+0x0/0x40 returned 0 after 0 usecs
[    6.606845][    T1] calling  ipc_ns_init+0x0/0x44 @ 1
[    6.612816][    T1] initcall ipc_ns_init+0x0/0x44 returned 0 after 0 usecs
[    6.620819][    T1] calling  init_mmap_min_addr+0x0/0x1a @ 1
[    6.626812][    T1] initcall init_mmap_min_addr+0x0/0x1a returned 0 after 0 usecs
[    6.635844][    T1] calling  pci_realloc_setup_params+0x0/0x49 @ 1
[    6.642816][    T1] initcall pci_realloc_setup_params+0x0/0x49 returned 0 after 0 usecs
[    6.651847][    T1] calling  inet_frag_wq_init+0x0/0x41 @ 1
[    6.657818][    T1] initcall inet_frag_wq_init+0x0/0x41 returned 0 after 0 usecs
[    6.666986][    T1] calling  e820__register_nvs_regions+0x0/0x3c @ 1
[    6.673838][    T1] ACPI: PM: Registering ACPI NVS region [mem 0x74622000-0x7689dfff] (36159488 bytes)
[    6.685837][    T1] initcall e820__register_nvs_regions+0x0/0x3c returned 0 after 12000 usecs
[    6.694849][    T1] calling  cpufreq_register_tsc_scaling+0x0/0x2e @ 1
[    6.702816][    T1] initcall cpufreq_register_tsc_scaling+0x0/0x2e returned 0 after 0 usecs
[    6.711847][    T1] calling  reboot_init+0x0/0x41 @ 1
[    6.717818][    T1] initcall reboot_init+0x0/0x41 returned 0 after 0 usecs
[    6.725818][    T1] calling  init_lapic_sysfs+0x0/0x25 @ 1
[    6.731819][    T1] initcall init_lapic_sysfs+0x0/0x25 returned 0 after 0 usecs
[    6.739846][    T1] calling  alloc_frozen_cpus+0x0/0x25 @ 1
[    6.746828][    T1] initcall alloc_frozen_cpus+0x0/0x25 returned 0 after 0 usecs
[    6.754846][    T1] calling  cpu_hotplug_pm_sync_init+0x0/0x18 @ 1
[    6.761816][    T1] initcall cpu_hotplug_pm_sync_init+0x0/0x18 returned 0 after 0 usecs
[    6.770849][    T1] calling  wq_sysfs_init+0x0/0x2f @ 1
[    6.776817][    T1] initcall wq_sysfs_init+0x0/0x2f returned 0 after 0 usecs
[    6.784820][    T1] calling  ksysfs_init+0x0/0x9d @ 1
[    6.790817][    T1] initcall ksysfs_init+0x0/0x9d returned 0 after 0 usecs
[    6.797818][    T1] calling  schedutil_gov_init+0x0/0x11 @ 1
[    6.804817][    T1] initcall schedutil_gov_init+0x0/0x11 returned 0 after 0 usecs
[    6.812845][    T1] calling  pm_init+0x0/0x7b @ 1
[    6.818925][    T1] initcall pm_init+0x0/0x7b returned 0 after 0 usecs
[    6.825819][    T1] calling  pm_disk_init+0x0/0x18 @ 1
[    6.831817][    T1] initcall pm_disk_init+0x0/0x18 returned 0 after 0 usecs
[    6.839818][    T1] calling  swsusp_header_init+0x0/0x30 @ 1
[    6.845814][    T1] initcall swsusp_header_init+0x0/0x30 returned 0 after 0 usecs
[    6.854846][    T1] calling  rcu_set_runtime_mode+0x0/0x1b @ 1
[    6.860845][    T1] initcall rcu_set_runtime_mode+0x0/0x1b returned 0 after 0 usecs
[    6.869845][    T1] calling  init_jiffies_clocksource+0x0/0x18 @ 1
[    6.876822][    T1] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 1911260446275000 ns
[    6.888858][    T1] initcall init_jiffies_clocksource+0x0/0x18 returned 0 after 12000 usecs
[    6.897848][    T1] calling  futex_init+0x0/0xcf @ 1
[    6.903818][    T1] futex hash table entries: 65536 (order: 10, 4194304 bytes, vmalloc)
[    6.913580][    T1] initcall futex_init+0x0/0xcf returned 0 after 10000 usecs
[    6.921819][    T1] calling  cgroup_wq_init+0x0/0x2d @ 1
[    6.927898][    T1] initcall cgroup_wq_init+0x0/0x2d returned 0 after 0 usecs
[    6.935820][    T1] calling  cgroup1_wq_init+0x0/0x2d @ 1
[    6.941815][    T1] initcall cgroup1_wq_init+0x0/0x2d returned 0 after 1000 usecs
[    6.950848][    T1] calling  ftrace_mod_cmd_init+0x0/0x9 @ 1
[    6.956819][    T1] initcall ftrace_mod_cmd_init+0x0/0x9 returned 0 after 0 usecs
[    6.965845][    T1] calling  init_wakeup_tracer+0x0/0x31 @ 1
[    6.971833][    T1] initcall init_wakeup_tracer+0x0/0x31 returned 0 after 0 usecs
[    6.980845][    T1] calling  init_graph_trace+0x0/0x61 @ 1
[    6.986818][    T1] initcall init_graph_trace+0x0/0x61 returned 0 after 0 usecs
[    6.994844][    T1] calling  trace_events_eprobe_init_early+0x0/0x2b @ 1
[    7.002818][    T1] initcall trace_events_eprobe_init_early+0x0/0x2b returned 0 after 0 usecs
[    7.011848][    T1] calling  trace_events_synth_init_early+0x0/0x2b @ 1
[    7.019820][    T1] initcall trace_events_synth_init_early+0x0/0x2b returned 0 after 0 usecs
[    7.028851][    T1] calling  init_kprobe_trace_early+0x0/0x2a @ 1
[    7.035818][    T1] initcall init_kprobe_trace_early+0x0/0x2a returned 0 after 0 usecs
[    7.044846][    T1] calling  memory_failure_init+0x0/0xa3 @ 1
[    7.051847][    T1] initcall memory_failure_init+0x0/0xa3 returned 0 after 0 usecs
[    7.059845][    T1] calling  fsnotify_init+0x0/0x4d @ 1
[    7.065832][    T1] initcall fsnotify_init+0x0/0x4d returned 0 after 1000 usecs
[    7.074845][    T1] calling  filelock_init+0x0/0xa4 @ 1
[    7.080954][    T1] initcall filelock_init+0x0/0xa4 returned 0 after 0 usecs
[    7.088817][    T1] calling  init_script_binfmt+0x0/0x1a @ 1
[    7.094816][    T1] initcall init_script_binfmt+0x0/0x1a returned 0 after 0 usecs
[    7.103846][    T1] calling  init_elf_binfmt+0x0/0x1a @ 1
[    7.109814][    T1] initcall init_elf_binfmt+0x0/0x1a returned 0 after 0 usecs
[    7.117844][    T1] calling  init_compat_elf_binfmt+0x0/0x1a @ 1
[    7.124814][    T1] initcall init_compat_elf_binfmt+0x0/0x1a returned 0 after 0 usecs
[    7.133846][    T1] calling  configfs_init+0x0/0x9e @ 1
[    7.139813][    T1] initcall configfs_init+0x0/0x9e returned 0 after 0 usecs
[    7.147818][    T1] calling  debugfs_init+0x0/0x67 @ 1
[    7.152814][    T1] initcall debugfs_init+0x0/0x67 returned 0 after 0 usecs
[    7.160817][    T1] calling  tracefs_init+0x0/0x41 @ 1
[    7.166813][    T1] initcall tracefs_init+0x0/0x41 returned 0 after 0 usecs
[    7.174816][    T1] calling  securityfs_init+0x0/0x72 @ 1
[    7.180927][    T1] initcall securityfs_init+0x0/0x72 returned 0 after 0 usecs
[    7.188844][    T1] calling  pinctrl_init+0x0/0xb2 @ 1
[    7.194811][    T1] pinctrl core: initialized pinctrl subsystem
[    7.201883][    T1] initcall pinctrl_init+0x0/0xb2 returned 0 after 7000 usecs
[    7.209846][    T1] calling  gpiolib_dev_init+0x0/0x100 @ 1
[    7.216765][    T1] initcall gpiolib_dev_init+0x0/0x100 returned 0 after 0 usecs
[    7.224846][    T1] calling  virtio_init+0x0/0x40 @ 1
[    7.230819][    T1] initcall virtio_init+0x0/0x40 returned 0 after 0 usecs
[    7.237817][    T1] calling  iommu_init+0x0/0x2f @ 1
[    7.243815][    T1] initcall iommu_init+0x0/0x2f returned 0 after 0 usecs
[    7.251817][    T1] calling  component_debug_init+0x0/0x21 @ 1
[    7.257818][    T1] initcall component_debug_init+0x0/0x21 returned 0 after 0 usecs
[    7.266846][    T1] calling  cpufreq_core_init+0x0/0x9a @ 1
[    7.272822][    T1] initcall cpufreq_core_init+0x0/0x9a returned 0 after 1000 usecs
[    7.281852][    T1] calling  cpufreq_gov_performance_init+0x0/0x11 @ 1
[    7.288817][    T1] initcall cpufreq_gov_performance_init+0x0/0x11 returned 0 after 0 usecs
[    7.307697][    T1] calling  cpufreq_gov_powersave_init+0x0/0x11 @ 1
[    7.314816][    T1] initcall cpufreq_gov_powersave_init+0x0/0x11 returned 0 after 0 usecs
[    7.324848][    T1] calling  cpufreq_gov_userspace_init+0x0/0x11 @ 1
[    7.331816][    T1] initcall cpufreq_gov_userspace_init+0x0/0x11 returned 0 after 0 usecs
[    7.340848][    T1] calling  CPU_FREQ_GOV_ONDEMAND_init+0x0/0x11 @ 1
[    7.347822][    T1] initcall CPU_FREQ_GOV_ONDEMAND_init+0x0/0x11 returned 0 after 0 usecs
[    7.357849][    T1] calling  CPU_FREQ_GOV_CONSERVATIVE_init+0x0/0x11 @ 1
[    7.364818][    T1] initcall CPU_FREQ_GOV_CONSERVATIVE_init+0x0/0x11 returned 0 after 0 usecs
[    7.374848][    T1] calling  cpuidle_init+0x0/0x24 @ 1
[    7.380851][    T1] initcall cpuidle_init+0x0/0x24 returned 0 after 0 usecs
[    7.388816][    T1] calling  sock_init+0x0/0xa3 @ 1
[    7.397993][    T1] initcall sock_init+0x0/0xa3 returned 0 after 4000 usecs
[    7.405825][    T1] calling  net_inuse_init+0x0/0x28 @ 1
[    7.411882][    T1] initcall net_inuse_init+0x0/0x28 returned 0 after 0 usecs
[    7.419820][    T1] calling  net_defaults_init+0x0/0x28 @ 1
[    7.425820][    T1] initcall net_defaults_init+0x0/0x28 returned 0 after 0 usecs
[    7.433846][    T1] calling  init_default_flow_dissectors+0x0/0x54 @ 1
[    7.441822][    T1] initcall init_default_flow_dissectors+0x0/0x54 returned 0 after 0 usecs
[    7.450852][    T1] calling  netpoll_init+0x0/0x2d @ 1
[    7.456813][    T1] initcall netpoll_init+0x0/0x2d returned 0 after 0 usecs
[    7.464820][    T1] calling  netlink_proto_init+0x0/0x181 @ 1
[    7.471819][    T1] NET: Registered PF_NETLINK/PF_ROUTE protocol family
[    7.478884][    T1] initcall netlink_proto_init+0x0/0x181 returned 0 after 7000 usecs
[    7.487846][    T1] calling  genl_init+0x0/0x3c @ 1
[    7.493840][    T1] initcall genl_init+0x0/0x3c returned 0 after 0 usecs
[    7.500815][    T1] calling  bsp_pm_check_init+0x0/0x18 @ 1
[    7.506817][    T1] initcall bsp_pm_check_init+0x0/0x18 returned 0 after 0 usecs
[    7.515987][    T1] calling  irq_sysfs_init+0x0/0x96 @ 1
[    7.521827][    T1] initcall irq_sysfs_init+0x0/0x96 returned 0 after 0 usecs
[    7.529819][    T1] calling  audit_init+0x0/0x173 @ 1
[    7.535827][    T1] audit: initializing netlink subsys (disabled)
[    7.542856][    T1] initcall audit_init+0x0/0x173 returned 0 after 7000 usecs
[    7.542856][  T775] audit: type=2000 audit(1670682606.840:1): state=initialized audit_enabled=0 res=1
[    7.550699][    T1] calling  release_early_probes+0x0/0x37 @ 1
[    7.568086][    T1] initcall release_early_probes+0x0/0x37 returned 0 after 0 usecs
[    7.576844][    T1] calling  bdi_class_init+0x0/0x4d @ 1
[    7.582814][    T1] initcall bdi_class_init+0x0/0x4d returned 0 after 0 usecs
[    7.590819][    T1] calling  mm_sysfs_init+0x0/0x2d @ 1
[    7.596812][    T1] initcall mm_sysfs_init+0x0/0x2d returned 0 after 0 usecs
[    7.604816][    T1] calling  init_per_zone_wmark_min+0x0/0x2a @ 1
[    7.611257][    T1] initcall init_per_zone_wmark_min+0x0/0x2a returned 0 after 0 usecs
[    7.620847][    T1] calling  mpi_init+0x0/0x43 @ 1
[    7.625813][    T1] initcall mpi_init+0x0/0x43 returned 0 after 0 usecs
[    7.633816][    T1] calling  acpi_gpio_setup_params+0x0/0x8f @ 1
[    7.640817][    T1] initcall acpi_gpio_setup_params+0x0/0x8f returned 0 after 0 usecs
[    7.648845][    T1] calling  pcibus_class_init+0x0/0x18 @ 1
[    7.655821][    T1] initcall pcibus_class_init+0x0/0x18 returned 0 after 0 usecs
[    7.663844][    T1] calling  pci_driver_init+0x0/0x26 @ 1
[    7.669813][    T1] initcall pci_driver_init+0x0/0x26 returned 0 after 0 usecs
[    7.677847][    T1] calling  backlight_class_init+0x0/0xaf @ 1
[    7.684816][    T1] initcall backlight_class_init+0x0/0xaf returned 0 after 0 usecs
[    7.693848][    T1] calling  tty_class_init+0x0/0x38 @ 1
[    7.699834][    T1] initcall tty_class_init+0x0/0x38 returned 0 after 0 usecs
[    7.707819][    T1] calling  vtconsole_class_init+0x0/0xbf @ 1
[    7.713878][    T1] initcall vtconsole_class_init+0x0/0xbf returned 0 after 0 usecs
[    7.722846][    T1] calling  iommu_dev_init+0x0/0x18 @ 1
[    7.728818][    T1] initcall iommu_dev_init+0x0/0x18 returned 0 after 0 usecs
[    7.736817][    T1] calling  mipi_dsi_bus_init+0x0/0x11 @ 1
[    7.743821][    T1] initcall mipi_dsi_bus_init+0x0/0x11 returned 0 after 0 usecs
[    7.751846][    T1] calling  devlink_class_init+0x0/0x4a @ 1
[    7.758738][    T1] initcall devlink_class_init+0x0/0x4a returned 0 after 0 usecs
[    7.766845][    T1] calling  software_node_init+0x0/0x2f @ 1
[    7.772832][    T1] initcall software_node_init+0x0/0x2f returned 0 after 0 usecs
[    7.781844][    T1] calling  wakeup_sources_debugfs_init+0x0/0x28 @ 1
[    7.788857][    T1] initcall wakeup_sources_debugfs_init+0x0/0x28 returned 0 after 0 usecs
[    7.798847][    T1] calling  wakeup_sources_sysfs_init+0x0/0x31 @ 1
[    7.805839][    T1] initcall wakeup_sources_sysfs_init+0x0/0x31 returned 0 after 0 usecs
[    7.814846][    T1] calling  regmap_initcall+0x0/0x11 @ 1
[    7.820817][    T1] initcall regmap_initcall+0x0/0x11 returned 0 after 0 usecs
[    7.828847][    T1] calling  spi_init+0x0/0xa5 @ 1
[    7.834811][    T1] initcall spi_init+0x0/0xa5 returned 0 after 0 usecs
[    7.841818][    T1] calling  i2c_init+0x0/0xb8 @ 1
[    7.847840][    T1] initcall i2c_init+0x0/0xb8 returned 0 after 0 usecs
[    7.854815][    T1] calling  thermal_init+0x0/0xfb @ 1
[    7.860816][    T1] thermal_sys: Registered thermal governor 'fair_share'
[    7.860817][    T1] thermal_sys: Registered thermal governor 'bang_bang'
[    7.868816][    T1] thermal_sys: Registered thermal governor 'step_wise'
[    7.875816][    T1] thermal_sys: Registered thermal governor 'user_space'
[    7.883822][    T1] initcall thermal_init+0x0/0xfb returned 0 after 23000 usecs
[    7.899846][    T1] calling  init_menu+0x0/0x11 @ 1
[    7.905724][    T1] cpuidle: using governor menu
[    7.910811][    T1] initcall init_menu+0x0/0x11 returned 0 after 5000 usecs
[    7.918816][    T1] calling  pcc_init+0x0/0x8d @ 1
[    7.923956][    T1] Detected 2 PCC Subspaces
[    7.928819][    T1] Registering PCC driver as Mailbox controller
[    7.935824][    T1] initcall pcc_init+0x0/0x8d returned 0 after 12000 usecs
[    7.943816][    T1] calling  amd_postcore_init+0x0/0x123 @ 1
[    7.949814][    T1] initcall amd_postcore_init+0x0/0x123 returned 0 after 0 usecs
[    7.958844][    T1] calling  kobject_uevent_init+0x0/0xc @ 1
[    7.964856][    T1] initcall kobject_uevent_init+0x0/0xc returned 0 after 0 usecs
[    7.973984][    T1] calling  bts_init+0x0/0xbf @ 1
[    7.978813][    T1] initcall bts_init+0x0/0xbf returned -19 after 0 usecs
[    7.986819][    T1] calling  pt_init+0x0/0x1f3 @ 1
[    7.992715][    T1] initcall pt_init+0x0/0x1f3 returned -19 after 0 usecs
[    7.999818][    T1] calling  boot_params_ksysfs_init+0x0/0x70 @ 1
[    8.006823][    T1] initcall boot_params_ksysfs_init+0x0/0x70 returned 0 after 0 usecs
[    8.015849][    T1] calling  sbf_init+0x0/0xd7 @ 1
[    8.021809][    T1] initcall sbf_init+0x0/0xd7 returned 0 after 0 usecs
[    8.028816][    T1] calling  arch_kdebugfs_init+0x0/0x205 @ 1
[    8.035853][    T1] initcall arch_kdebugfs_init+0x0/0x205 returned 0 after 0 usecs
[    8.043846][    T1] calling  xfd_update_static_branch+0x0/0x22 @ 1
[    8.050815][    T1] initcall xfd_update_static_branch+0x0/0x22 returned 0 after 0 usecs
[    8.059848][    T1] calling  intel_pconfig_init+0x0/0x8a @ 1
[    8.066814][    T1] initcall intel_pconfig_init+0x0/0x8a returned 0 after 0 usecs
[    8.074844][    T1] calling  mtrr_if_init+0x0/0x62 @ 1
[    8.080816][    T1] initcall mtrr_if_init+0x0/0x62 returned 0 after 0 usecs
[    8.088818][    T1] calling  activate_jump_labels+0x0/0x36 @ 1
[    8.094816][    T1] initcall activate_jump_labels+0x0/0x36 returned 0 after 0 usecs
[    8.103844][    T1] calling  init_s4_sigcheck+0x0/0x28 @ 1
[    8.109814][    T1] initcall init_s4_sigcheck+0x0/0x28 returned 0 after 0 usecs
[    8.117852][    T1] calling  ffh_cstate_init+0x0/0x35 @ 1
[    8.124814][    T1] initcall ffh_cstate_init+0x0/0x35 returned 0 after 0 usecs
[    8.132850][    T1] calling  kvm_alloc_cpumask+0x0/0x8c @ 1
[    8.138814][    T1] initcall kvm_alloc_cpumask+0x0/0x8c returned 0 after 0 usecs
[    8.146852][    T1] calling  activate_jump_labels+0x0/0x36 @ 1
[    8.153817][    T1] initcall activate_jump_labels+0x0/0x36 returned 0 after 0 usecs
[    8.162846][    T1] calling  gigantic_pages_init+0x0/0x24 @ 1
[    8.168821][    T1] initcall gigantic_pages_init+0x0/0x24 returned 0 after 0 usecs
[    8.177845][    T1] calling  uv_rtc_setup_clock+0x0/0x14f @ 1
[    8.183815][    T1] initcall uv_rtc_setup_clock+0x0/0x14f returned -19 after 0 usecs
[    8.192846][    T1] calling  kcmp_cookies_init+0x0/0x3c @ 1
[    8.199698][    T1] initcall kcmp_cookies_init+0x0/0x3c returned 0 after 0 usecs
[    8.207845][    T1] calling  cryptomgr_init+0x0/0x11 @ 1
[    8.213817][    T1] initcall cryptomgr_init+0x0/0x11 returned 0 after 0 usecs
[    8.221818][    T1] calling  acpi_pci_init+0x0/0x53 @ 1
[    8.227811][    T1] ACPI FADT declares the system doesn't support PCIe ASPM, so disable it
[    8.236849][    T1] acpiphp: ACPI Hot Plug PCI Controller Driver version: 0.5
[    8.244818][    T1] initcall acpi_pci_init+0x0/0x53 returned 0 after 17000 usecs
[    8.253845][    T1] calling  dma_channel_table_init+0x0/0xb8 @ 1
[    8.260772][    T1] initcall dma_channel_table_init+0x0/0xb8 returned 0 after 0 usecs
[    8.268847][    T1] calling  dma_bus_init+0x0/0x106 @ 1
[    8.275017][    T1] initcall dma_bus_init+0x0/0x106 returned 0 after 1000 usecs
[    8.283845][    T1] calling  iommu_dma_init+0x0/0x40 @ 1
[    8.289821][    T1] initcall iommu_dma_init+0x0/0x40 returned 0 after 0 usecs
[    8.297818][    T1] calling  dmi_id_init+0x0/0xbd @ 1
[    8.303814][    T1] initcall dmi_id_init+0x0/0xbd returned 0 after 0 usecs
[    8.310817][    T1] calling  pci_arch_init+0x0/0x76 @ 1
[    8.316823][    T1] PCI: MMCONFIG for domain 0000 [bus 00-ff] at [mem 0x80000000-0x8fffffff] (base 0x80000000)
[    8.337705][    T1] PCI: MMCONFIG at [mem 0x80000000-0x8fffffff] reserved in E820
[    8.345874][    T1] PCI: Using configuration type 1 for base access
[    8.353818][    T1] initcall pci_arch_init+0x0/0x76 returned 0 after 37000 usecs
[    8.361981][    T1] calling  init_vdso+0x0/0x18 @ 1
[    8.367822][    T1] initcall init_vdso+0x0/0x18 returned 0 after 0 usecs
[    8.374818][    T1] calling  sysenter_setup+0x0/0x18 @ 1
[    8.380823][    T1] initcall sysenter_setup+0x0/0x18 returned 0 after 0 usecs
[    8.388822][    T1] calling  fixup_ht_bug+0x0/0xc6 @ 1
[    8.394815][    T1] core: PMU erratum BJ122, BV98, HSD29 worked around, HT is on
[    8.403849][    T1] initcall fixup_ht_bug+0x0/0xc6 returned 0 after 9000 usecs
[    8.411846][    T1] calling  topology_init+0x0/0x3b @ 1
[    8.420826][    T1] initcall topology_init+0x0/0x3b returned 0 after 3000 usecs
[    8.428845][    T1] calling  intel_epb_init+0x0/0x8e @ 1
[    8.439732][    T1] initcall intel_epb_init+0x0/0x8e returned 0 after 5000 usecs
[    8.447846][    T1] calling  mtrr_init_finialize+0x0/0x43 @ 1
[    8.454821][    T1] initcall mtrr_init_finialize+0x0/0x43 returned 0 after 0 usecs
[    8.462844][    T1] calling  uid_cache_init+0x0/0xb5 @ 1
[    8.469818][    T1] initcall uid_cache_init+0x0/0xb5 returned 0 after 0 usecs
[    8.477820][    T1] calling  param_sysfs_init+0x0/0xab @ 1
[    8.485169][    T1] initcall param_sysfs_init+0x0/0xab returned 0 after 1000 usecs
[    8.493850][    T1] calling  user_namespace_sysctl_init+0x0/0xbe @ 1
[    8.500859][    T1] initcall user_namespace_sysctl_init+0x0/0xbe returned 0 after 0 usecs
[    8.509847][    T1] calling  proc_schedstat_init+0x0/0x29 @ 1
[    8.516825][    T1] initcall proc_schedstat_init+0x0/0x29 returned 0 after 0 usecs
[    8.524846][    T1] calling  pm_sysrq_init+0x0/0x1d @ 1
[    8.531698][    T1] initcall pm_sysrq_init+0x0/0x1d returned 0 after 1000 usecs
[    8.539846][    T1] calling  create_proc_profile+0x0/0x100 @ 1
[    8.545813][    T1] initcall create_proc_profile+0x0/0x100 returned 0 after 0 usecs
[    8.554845][    T1] calling  crash_save_vmcoreinfo_init+0x0/0x714 @ 1
[    8.561856][    T1] initcall crash_save_vmcoreinfo_init+0x0/0x714 returned 0 after 0 usecs
[    8.571846][    T1] calling  crash_notes_memory_init+0x0/0x3d @ 1
[    8.578896][    T1] initcall crash_notes_memory_init+0x0/0x3d returned 0 after 0 usecs
[    8.587849][    T1] calling  cgroup_sysfs_init+0x0/0x18 @ 1
[    8.593825][    T1] initcall cgroup_sysfs_init+0x0/0x18 returned 0 after 0 usecs
[    8.601846][    T1] calling  cgroup_namespaces_init+0x0/0xc @ 1
[    8.608817][    T1] initcall cgroup_namespaces_init+0x0/0xc returned 0 after 0 usecs
[    8.617848][    T1] calling  user_namespaces_init+0x0/0x31 @ 1
[    8.624757][    T1] initcall user_namespaces_init+0x0/0x31 returned 0 after 0 usecs
[    8.632846][    T1] calling  init_optprobes+0x0/0x1d @ 1
[    8.638816][    T1] kprobes: kprobe jump-optimization is enabled. All kprobes are optimized if possible.
[    8.649850][    T1] initcall init_optprobes+0x0/0x1d returned 0 after 11000 usecs
[    8.657845][    T1] calling  hung_task_init+0x0/0x79 @ 1
[    8.664726][    T1] initcall hung_task_init+0x0/0x79 returned 0 after 0 usecs
[    8.672819][    T1] calling  ftrace_check_for_weak_functions+0x0/0x66 @ 1
[    8.679926][    T1] initcall ftrace_check_for_weak_functions+0x0/0x66 returned 0 after 0 usecs
[    8.689848][    T1] calling  trace_eval_init+0x0/0x8d @ 1
[    8.695821][    T1] initcall trace_eval_init+0x0/0x8d returned 0 after 0 usecs
[    8.703844][    T1] calling  send_signal_irq_work_init+0x0/0x5c @ 1
[    8.710848][    T1] initcall send_signal_irq_work_init+0x0/0x5c returned 0 after 0 usecs
[    8.720846][    T1] calling  dev_map_init+0x0/0x52 @ 1
[    8.726814][    T1] initcall dev_map_init+0x0/0x52 returned 0 after 0 usecs
[    8.733819][    T1] calling  cpu_map_init+0x0/0x46 @ 1
[    8.739840][    T1] initcall cpu_map_init+0x0/0x46 returned 0 after 0 usecs
[    8.747817][    T1] calling  netns_bpf_init+0x0/0x11 @ 1
[    8.753815][    T1] initcall netns_bpf_init+0x0/0x11 returned 0 after 0 usecs
[    8.761818][    T1] calling  btf_vmlinux_init+0x0/0x66 @ 1
[    8.768708][    T1] initcall btf_vmlinux_init+0x0/0x66 returned 0 after 0 usecs
[    8.776846][    T1] calling  oom_init+0x0/0x4e @ 1
[    8.781814][    T1] initcall oom_init+0x0/0x4e returned 0 after 0 usecs
[    8.789816][    T1] calling  default_bdi_init+0x0/0x2d @ 1
[    8.795860][    T1] initcall default_bdi_init+0x0/0x2d returned 0 after 0 usecs
[    8.803845][    T1] calling  cgwb_init+0x0/0x2d @ 1
[    8.809905][    T1] initcall cgwb_init+0x0/0x2d returned 0 after 0 usecs
[    8.817817][    T1] calling  percpu_enable_async+0x0/0x13 @ 1
[    8.823817][    T1] initcall percpu_enable_async+0x0/0x13 returned 0 after 0 usecs
[    8.832846][    T1] calling  kcompactd_init+0x0/0x9c @ 1
[    8.838813][    T1] initcall kcompactd_init+0x0/0x9c returned 0 after 0 usecs
[    8.846824][    T1] calling  init_user_reserve+0x0/0x40 @ 1
[    8.852814][    T1] initcall init_user_reserve+0x0/0x40 returned 0 after 0 usecs
[    8.860846][    T1] calling  init_admin_reserve+0x0/0x40 @ 1
[    8.867819][    T1] initcall init_admin_reserve+0x0/0x40 returned 0 after 0 usecs
[    8.875844][    T1] calling  init_reserve_notifier+0x0/0x23 @ 1
[    8.882818][    T1] initcall init_reserve_notifier+0x0/0x23 returned 0 after 0 usecs
[    8.891847][    T1] calling  swap_init_sysfs+0x0/0x6c @ 1
[    8.897818][    T1] initcall swap_init_sysfs+0x0/0x6c returned 0 after 0 usecs
[    8.905847][    T1] calling  swapfile_init+0x0/0xd1 @ 1
[    8.911813][    T1] initcall swapfile_init+0x0/0xd1 returned 0 after 0 usecs
[    8.919816][    T1] calling  hugetlb_init+0x0/0x34e @ 1
[    8.925830][    T1] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
[    8.934844][    T1] HugeTLB: 16380 KiB vmemmap can be freed for a 1.00 GiB page
[    8.942844][    T1] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
[    8.950845][    T1] HugeTLB: 28 KiB vmemmap can be freed for a 2.00 MiB page
[    8.958822][    T1] initcall hugetlb_init+0x0/0x34e returned 0 after 34000 usecs
[    8.967846][    T1] calling  ksm_init+0x0/0x1a3 @ 1
[    8.972820][    T1] initcall ksm_init+0x0/0x1a3 returned 0 after 0 usecs
[    8.980816][    T1] calling  memory_tier_init+0x0/0x10c @ 1
[    8.987700][    T1] initcall memory_tier_init+0x0/0x10c returned 0 after 1000 usecs
[    8.995851][    T1] calling  numa_init_sysfs+0x0/0x6c @ 1
[    9.001820][    T1] initcall numa_init_sysfs+0x0/0x6c returned 0 after 0 usecs
[    9.009844][    T1] calling  hugepage_init+0x0/0x153 @ 1
[    9.016746][    T1] initcall hugepage_init+0x0/0x153 returned 0 after 0 usecs
[    9.024818][    T1] calling  mem_cgroup_init+0x0/0x12f @ 1
[    9.030847][    T1] initcall mem_cgroup_init+0x0/0x12f returned 0 after 0 usecs
[    9.038844][    T1] calling  mem_cgroup_swap_init+0x0/0x60 @ 1
[    9.045819][    T1] initcall mem_cgroup_swap_init+0x0/0x60 returned 0 after 0 usecs
[    9.053846][    T1] calling  page_idle_init+0x0/0x37 @ 1
[    9.060818][    T1] initcall page_idle_init+0x0/0x37 returned 0 after 0 usecs
[    9.068818][    T1] calling  seqiv_module_init+0x0/0x11 @ 1
[    9.074816][    T1] initcall seqiv_module_init+0x0/0x11 returned 0 after 0 usecs
[    9.082845][    T1] calling  rsa_init+0x0/0x43 @ 1
[    9.088812][    T1] initcall rsa_init+0x0/0x43 returned 0 after 0 usecs
[    9.095822][    T1] calling  hmac_module_init+0x0/0x11 @ 1
[    9.101813][    T1] initcall hmac_module_init+0x0/0x11 returned 0 after 0 usecs
[    9.110844][    T1] calling  crypto_null_mod_init+0x0/0x71 @ 1
[    9.116818][    T1] initcall crypto_null_mod_init+0x0/0x71 returned 0 after 0 usecs
[    9.125847][    T1] calling  md5_mod_init+0x0/0x11 @ 1
[    9.131814][    T1] initcall md5_mod_init+0x0/0x11 returned 0 after 0 usecs
[    9.139817][    T1] calling  sha1_generic_mod_init+0x0/0x11 @ 1
[    9.146819][    T1] initcall sha1_generic_mod_init+0x0/0x11 returned 0 after 0 usecs
[    9.154851][    T1] calling  sha256_generic_mod_init+0x0/0x16 @ 1
[    9.161815][    T1] initcall sha256_generic_mod_init+0x0/0x16 returned 0 after 0 usecs
[    9.170847][    T1] calling  sha512_generic_mod_init+0x0/0x16 @ 1
[    9.177815][    T1] initcall sha512_generic_mod_init+0x0/0x16 returned 0 after 0 usecs
[    9.186847][    T1] calling  crypto_ecb_module_init+0x0/0x11 @ 1
[    9.193814][    T1] initcall crypto_ecb_module_init+0x0/0x11 returned 0 after 0 usecs
[    9.202846][    T1] calling  crypto_cbc_module_init+0x0/0x11 @ 1
[    9.209814][    T1] initcall crypto_cbc_module_init+0x0/0x11 returned 0 after 0 usecs
[    9.217845][    T1] calling  crypto_cfb_module_init+0x0/0x11 @ 1
[    9.224816][    T1] initcall crypto_cfb_module_init+0x0/0x11 returned 0 after 0 usecs
[    9.233846][    T1] calling  crypto_ctr_module_init+0x0/0x16 @ 1
[    9.240815][    T1] initcall crypto_ctr_module_init+0x0/0x16 returned 0 after 0 usecs
[    9.249848][    T1] calling  crypto_gcm_module_init+0x0/0x67 @ 1
[    9.256821][    T1] initcall crypto_gcm_module_init+0x0/0x67 returned 0 after 0 usecs
[    9.264846][    T1] calling  cryptd_init+0x0/0xf9 @ 1
[    9.271734][    T1] cryptd: max_cpu_qlen set to 1000
[    9.276813][    T1] initcall cryptd_init+0x0/0xf9 returned 0 after 6000 usecs
[    9.284818][    T1] calling  aes_init+0x0/0x11 @ 1
[    9.290816][    T1] initcall aes_init+0x0/0x11 returned 0 after 0 usecs
[    9.297815][    T1] calling  deflate_mod_init+0x0/0x48 @ 1
[    9.304821][    T1] initcall deflate_mod_init+0x0/0x48 returned 0 after 0 usecs
[    9.312844][    T1] calling  crc32c_mod_init+0x0/0x11 @ 1
[    9.327702][    T1] initcall crc32c_mod_init+0x0/0x11 returned 0 after 0 usecs
[    9.335844][    T1] calling  crct10dif_mod_init+0x0/0x11 @ 1
[    9.342824][    T1] initcall crct10dif_mod_init+0x0/0x11 returned 0 after 0 usecs
[    9.350848][    T1] calling  lzo_mod_init+0x0/0x43 @ 1
[    9.356814][    T1] initcall lzo_mod_init+0x0/0x43 returned 0 after 0 usecs
[    9.364818][    T1] calling  lzorle_mod_init+0x0/0x43 @ 1
[    9.370818][    T1] initcall lzorle_mod_init+0x0/0x43 returned 0 after 0 usecs
[    9.378843][    T1] calling  drbg_init+0x0/0x81 @ 1
[    9.384843][    T1] initcall drbg_init+0x0/0x81 returned 0 after 0 usecs
[    9.392818][    T1] calling  ghash_mod_init+0x0/0x11 @ 1
[    9.398814][    T1] initcall ghash_mod_init+0x0/0x11 returned 0 after 0 usecs
[    9.406817][    T1] calling  init_bio+0x0/0xae @ 1
[    9.412856][    T1] initcall init_bio+0x0/0xae returned 0 after 1000 usecs
[    9.419818][    T1] calling  blk_ioc_init+0x0/0x2e @ 1
[    9.425812][    T1] initcall blk_ioc_init+0x0/0x2e returned 0 after 0 usecs
[    9.433818][    T1] calling  blk_mq_init+0x0/0xc4 @ 1
[    9.439843][    T1] initcall blk_mq_init+0x0/0xc4 returned 0 after 0 usecs
[    9.447816][    T1] calling  genhd_device_init+0x0/0x66 @ 1
[    9.453928][    T1] initcall genhd_device_init+0x0/0x66 returned 0 after 0 usecs
[    9.462846][    T1] calling  blkcg_init+0x0/0x2d @ 1
[    9.467817][    T1] initcall blkcg_init+0x0/0x2d returned 0 after 0 usecs
[    9.475817][    T1] calling  io_wq_init+0x0/0x3d @ 1
[    9.481810][    T1] initcall io_wq_init+0x0/0x3d returned 0 after 0 usecs
[    9.488816][    T1] calling  sg_pool_init+0x0/0xb4 @ 1
[    9.494814][    T1] initcall sg_pool_init+0x0/0xb4 returned 0 after 0 usecs
[    9.502821][    T1] calling  irq_poll_setup+0x0/0x78 @ 1
[    9.508844][    T1] initcall irq_poll_setup+0x0/0x78 returned 0 after 0 usecs
[    9.516818][    T1] calling  gpiolib_debugfs_init+0x0/0x28 @ 1
[    9.523849][    T1] initcall gpiolib_debugfs_init+0x0/0x28 returned 0 after 0 usecs
[    9.532847][    T1] calling  pwm_debugfs_init+0x0/0x28 @ 1
[    9.538815][    T1] initcall pwm_debugfs_init+0x0/0x28 returned 0 after 0 usecs
[    9.546844][    T1] calling  pwm_sysfs_init+0x0/0x18 @ 1
[    9.552842][    T1] initcall pwm_sysfs_init+0x0/0x18 returned 0 after 0 usecs
[    9.560819][    T1] calling  pci_slot_init+0x0/0x40 @ 1
[    9.566815][    T1] initcall pci_slot_init+0x0/0x40 returned 0 after 0 usecs
[    9.574820][    T1] calling  fbmem_init+0x0/0xe5 @ 1
[    9.580891][    T1] initcall fbmem_init+0x0/0xe5 returned 0 after 0 usecs
[    9.588818][    T1] calling  scan_for_dmi_ipmi+0x0/0x26f @ 1
[    9.594866][    T1] initcall scan_for_dmi_ipmi+0x0/0x26f returned 0 after 0 usecs
[    9.603847][    T1] calling  acpi_init+0x0/0x131 @ 1
[    9.608816][    T1] ACPI: Added _OSI(Module Device)
[    9.614814][    T1] ACPI: Added _OSI(Processor Device)
[    9.620811][    T1] ACPI: Added _OSI(3.0 _SCP Extensions)
[    9.626812][    T1] ACPI: Added _OSI(Processor Aggregator Device)
[    9.721454][    T1] ACPI: 4 ACPI AML tables successfully acquired and loaded
[    9.741993][    T1] ACPI: Dynamic OEM Table Load:
[    9.750153][    T1] ACPI BIOS Error (bug): AE_AML_BUFFER_LIMIT, Field [CPB3] at bit offset/length 64/32 exceeds size of target Buffer (64 bits) (20220331/dsopcode-198)
[    9.766898][    T1] ACPI Error: Aborting method \_SB._OSC due to previous error (AE_AML_BUFFER_LIMIT) (20220331/psparse-529)
[    9.805318][    T1] ACPI: Interpreter enabled
[    9.809827][    T1] ACPI: PM: (supports S0 S4 S5)
[    9.814814][    T1] ACPI: Using IOAPIC for interrupt routing
[    9.821850][    T1] PCI: Using host bridge windows from ACPI; if necessary, use "pci=nocrs" and report a bug
[    9.832852][    T1] PCI: Using E820 reservations for host bridge windows
[    9.840497][    T1] ACPI: Enabled 6 GPEs in block 00 to 3F
[   10.007558][    T1] ACPI: PCI Root Bridge [UNC3] (domain 0000 [bus ff])
[   10.015822][    T1] acpi PNP0A03:00: _OSC: OS supports [ExtendedConfig ASPM ClockPM Segments MSI HPX-Type3]
[   10.026898][    T1] PCI host bridge to bus 0000:ff
[   10.031812][    T1] pci_bus 0000:ff: Unknown NUMA node; performance will be reduced
[   10.040849][    T1] pci_bus 0000:ff: root bus resource [bus ff]
[   10.047715][    T1] pci 0000:ff:08.0: [8086:2f80] type 00 class 0x088000
[   10.054861][    T1] pci 0000:ff:08.0: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   10.063850][    T1] pci 0000:ff:08.0: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   10.072890][    T1] pci 0000:ff:08.2: [8086:2f32] type 00 class 0x110100
[   10.080857][    T1] pci 0000:ff:08.2: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   10.089849][    T1] pci 0000:ff:08.2: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   10.098854][    T1] pci 0000:ff:09.0: [8086:2f90] type 00 class 0x088000
[   10.105858][    T1] pci 0000:ff:09.0: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   10.114850][    T1] pci 0000:ff:09.0: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   10.123909][    T1] pci 0000:ff:09.2: [8086:2f33] type 00 class 0x110100
[   10.131858][    T1] pci 0000:ff:09.2: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   10.140848][    T1] pci 0000:ff:09.2: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   10.149892][    T1] pci 0000:ff:0a.0: [8086:2f40] type 00 class 0x088000
[   10.157856][    T1] pci 0000:ff:0a.0: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   10.166848][    T1] pci 0000:ff:0a.0: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   10.175852][    T1] pci 0000:ff:0a.2: [8086:2f3a] type 00 class 0x110100
[   10.182886][    T1] pci 0000:ff:0a.2: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   10.191846][    T1] pci 0000:ff:0a.2: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   10.200884][    T1] pci 0000:ff:0b.0: [8086:2f81] type 00 class 0x088000
[   10.208855][    T1] pci 0000:ff:0b.0: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   10.217848][    T1] pci 0000:ff:0b.0: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   10.226856][    T1] pci 0000:ff:0b.1: [8086:2f36] type 00 class 0x110100
[   10.233880][    T1] pci 0000:ff:0b.1: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   10.242849][    T1] pci 0000:ff:0b.1: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   10.252757][    T1] pci 0000:ff:0b.4: [8086:2f41] type 00 class 0x088000
[   10.259880][    T1] pci 0000:ff:0b.4: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   10.268847][    T1] pci 0000:ff:0b.4: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   10.277894][    T1] pci 0000:ff:0b.5: [8086:2f3e] type 00 class 0x110100
[   10.285857][    T1] pci 0000:ff:0b.5: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   10.294849][    T1] pci 0000:ff:0b.5: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   10.303854][    T1] pci 0000:ff:0b.6: [8086:2f3f] type 00 class 0x110100
[   10.310875][    T1] pci 0000:ff:0b.6: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   10.319847][    T1] pci 0000:ff:0b.6: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   10.328882][    T1] pci 0000:ff:0c.0: [8086:2fe0] type 00 class 0x088000
[   10.336856][    T1] pci 0000:ff:0c.0: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   10.345847][    T1] pci 0000:ff:0c.0: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   10.354876][    T1] pci 0000:ff:0c.1: [8086:2fe1] type 00 class 0x088000
[   10.362859][    T1] pci 0000:ff:0c.1: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   10.371849][    T1] pci 0000:ff:0c.1: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   10.380853][    T1] pci 0000:ff:0c.2: [8086:2fe2] type 00 class 0x088000
[   10.387856][    T1] pci 0000:ff:0c.2: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   10.396847][    T1] pci 0000:ff:0c.2: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   10.405876][    T1] pci 0000:ff:0c.3: [8086:2fe3] type 00 class 0x088000
[   10.413856][    T1] pci 0000:ff:0c.3: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   10.422847][    T1] pci 0000:ff:0c.3: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   10.431852][    T1] pci 0000:ff:0c.4: [8086:2fe4] type 00 class 0x088000
[   10.438884][    T1] pci 0000:ff:0c.4: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   10.447847][    T1] pci 0000:ff:0c.4: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   10.456880][    T1] pci 0000:ff:0c.5: [8086:2fe5] type 00 class 0x088000
[   10.464855][    T1] pci 0000:ff:0c.5: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   10.473847][    T1] pci 0000:ff:0c.5: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   10.482873][    T1] pci 0000:ff:0c.6: [8086:2fe6] type 00 class 0x088000
[   10.490854][    T1] pci 0000:ff:0c.6: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   10.499848][    T1] pci 0000:ff:0c.6: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   10.508852][    T1] pci 0000:ff:0c.7: [8086:2fe7] type 00 class 0x088000
[   10.515879][    T1] pci 0000:ff:0c.7: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   10.524846][    T1] pci 0000:ff:0c.7: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   10.533897][    T1] pci 0000:ff:0d.0: [8086:2fe8] type 00 class 0x088000
[   10.541855][    T1] pci 0000:ff:0d.0: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   10.550846][    T1] pci 0000:ff:0d.0: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   10.559851][    T1] pci 0000:ff:0d.1: [8086:2fe9] type 00 class 0x088000
[   10.566858][    T1] pci 0000:ff:0d.1: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   10.575849][    T1] pci 0000:ff:0d.1: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   10.584875][    T1] pci 0000:ff:0d.2: [8086:2fea] type 00 class 0x088000
[   10.592857][    T1] pci 0000:ff:0d.2: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   10.610698][    T1] pci 0000:ff:0d.2: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   10.619895][    T1] pci 0000:ff:0d.3: [8086:2feb] type 00 class 0x088000
[   10.627856][    T1] pci 0000:ff:0d.3: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   10.636847][    T1] pci 0000:ff:0d.3: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   10.645884][    T1] pci 0000:ff:0d.4: [8086:2fec] type 00 class 0x088000
[   10.652856][    T1] pci 0000:ff:0d.4: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   10.661852][    T1] pci 0000:ff:0d.4: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   10.671751][    T1] pci 0000:ff:0d.5: [8086:2fed] type 00 class 0x088000
[   10.678857][    T1] pci 0000:ff:0d.5: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   10.687848][    T1] pci 0000:ff:0d.5: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   10.696881][    T1] pci 0000:ff:0d.6: [8086:2fee] type 00 class 0x088000
[   10.704855][    T1] pci 0000:ff:0d.6: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   10.713847][    T1] pci 0000:ff:0d.6: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   10.722851][    T1] pci 0000:ff:0d.7: [8086:2fef] type 00 class 0x088000
[   10.729859][    T1] pci 0000:ff:0d.7: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   10.738847][    T1] pci 0000:ff:0d.7: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   10.747874][    T1] pci 0000:ff:0e.0: [8086:2ff0] type 00 class 0x088000
[   10.755855][    T1] pci 0000:ff:0e.0: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   10.764847][    T1] pci 0000:ff:0e.0: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   10.773887][    T1] pci 0000:ff:0e.1: [8086:2ff1] type 00 class 0x088000
[   10.780855][    T1] pci 0000:ff:0e.1: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   10.789850][    T1] pci 0000:ff:0e.1: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   10.798851][    T1] pci 0000:ff:0f.0: [8086:2ff8] type 00 class 0x088000
[   10.806856][    T1] pci 0000:ff:0f.0: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   10.815846][    T1] pci 0000:ff:0f.0: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   10.824878][    T1] pci 0000:ff:0f.1: [8086:2ff9] type 00 class 0x088000
[   10.832856][    T1] pci 0000:ff:0f.1: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   10.841847][    T1] pci 0000:ff:0f.1: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   10.850851][    T1] pci 0000:ff:0f.2: [8086:2ffa] type 00 class 0x088000
[   10.857857][    T1] pci 0000:ff:0f.2: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   10.866852][    T1] pci 0000:ff:0f.2: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   10.875889][    T1] pci 0000:ff:0f.3: [8086:2ffb] type 00 class 0x088000
[   10.883856][    T1] pci 0000:ff:0f.3: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   10.892847][    T1] pci 0000:ff:0f.3: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   10.901885][    T1] pci 0000:ff:0f.4: [8086:2ffc] type 00 class 0x088000
[   10.908854][    T1] pci 0000:ff:0f.4: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   10.917847][    T1] pci 0000:ff:0f.4: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   10.926871][    T1] pci 0000:ff:0f.5: [8086:2ffd] type 00 class 0x088000
[   10.934854][    T1] pci 0000:ff:0f.5: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   10.943852][    T1] pci 0000:ff:0f.5: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   10.952850][    T1] pci 0000:ff:0f.6: [8086:2ffe] type 00 class 0x088000
[   10.960858][    T1] pci 0000:ff:0f.6: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   10.969846][    T1] pci 0000:ff:0f.6: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   10.977890][    T1] pci 0000:ff:10.0: [8086:2f1d] type 00 class 0x088000
[   10.985857][    T1] pci 0000:ff:10.0: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   10.994848][    T1] pci 0000:ff:10.0: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   11.003850][    T1] pci 0000:ff:10.1: [8086:2f34] type 00 class 0x110100
[   11.011859][    T1] pci 0000:ff:10.1: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   11.020846][    T1] pci 0000:ff:10.1: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   11.029851][    T1] pci 0000:ff:10.5: [8086:2f1e] type 00 class 0x088000
[   11.036857][    T1] pci 0000:ff:10.5: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   11.045851][    T1] pci 0000:ff:10.5: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   11.054888][    T1] pci 0000:ff:10.7: [8086:2f1f] type 00 class 0x088000
[   11.062856][    T1] pci 0000:ff:10.7: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   11.071847][    T1] pci 0000:ff:10.7: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   11.080890][    T1] pci 0000:ff:12.0: [8086:2fa0] type 00 class 0x088000
[   11.087856][    T1] pci 0000:ff:12.0: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   11.096851][    T1] pci 0000:ff:12.0: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   11.106739][    T1] pci 0000:ff:12.1: [8086:2f30] type 00 class 0x110100
[   11.113858][    T1] pci 0000:ff:12.1: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   11.122847][    T1] pci 0000:ff:12.1: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   11.131875][    T1] pci 0000:ff:12.2: [8086:2f70] type 00 class 0x088000
[   11.139857][    T1] pci 0000:ff:12.2: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   11.148848][    T1] pci 0000:ff:12.2: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   11.157893][    T1] pci 0000:ff:12.4: [8086:2f60] type 00 class 0x088000
[   11.164857][    T1] pci 0000:ff:12.4: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   11.173847][    T1] pci 0000:ff:12.4: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   11.182870][    T1] pci 0000:ff:12.5: [8086:2f38] type 00 class 0x110100
[   11.190856][    T1] pci 0000:ff:12.5: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   11.199847][    T1] pci 0000:ff:12.5: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   11.208884][    T1] pci 0000:ff:13.0: [8086:2fa8] type 00 class 0x088000
[   11.215864][    T1] pci 0000:ff:13.0: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   11.224848][    T1] pci 0000:ff:13.0: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   11.233919][    T1] pci 0000:ff:13.1: [8086:2f71] type 00 class 0x088000
[   11.241861][    T1] pci 0000:ff:13.1: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   11.250846][    T1] pci 0000:ff:13.1: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   11.259908][    T1] pci 0000:ff:13.2: [8086:2faa] type 00 class 0x088000
[   11.267860][    T1] pci 0000:ff:13.2: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   11.276848][    T1] pci 0000:ff:13.2: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   11.285765][    T1] pci 0000:ff:13.3: [8086:2fab] type 00 class 0x088000
[   11.292892][    T1] pci 0000:ff:13.3: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   11.301848][    T1] pci 0000:ff:13.3: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   11.310897][    T1] pci 0000:ff:13.4: [8086:2fac] type 00 class 0x088000
[   11.318861][    T1] pci 0000:ff:13.4: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   11.327847][    T1] pci 0000:ff:13.4: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   11.336855][    T1] pci 0000:ff:13.5: [8086:2fad] type 00 class 0x088000
[   11.343862][    T1] pci 0000:ff:13.5: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   11.352849][    T1] pci 0000:ff:13.5: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   11.361892][    T1] pci 0000:ff:13.6: [8086:2fae] type 00 class 0x088000
[   11.369857][    T1] pci 0000:ff:13.6: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   11.378846][    T1] pci 0000:ff:13.6: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   11.387893][    T1] pci 0000:ff:13.7: [8086:2faf] type 00 class 0x088000
[   11.395856][    T1] pci 0000:ff:13.7: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   11.404848][    T1] pci 0000:ff:13.7: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   11.413850][    T1] pci 0000:ff:14.0: [8086:2fb0] type 00 class 0x088000
[   11.420862][    T1] pci 0000:ff:14.0: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   11.429847][    T1] pci 0000:ff:14.0: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   11.438902][    T1] pci 0000:ff:14.1: [8086:2fb1] type 00 class 0x088000
[   11.446861][    T1] pci 0000:ff:14.1: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   11.455847][    T1] pci 0000:ff:14.1: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   11.464852][    T1] pci 0000:ff:14.2: [8086:2fb2] type 00 class 0x088000
[   11.471862][    T1] pci 0000:ff:14.2: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   11.480847][    T1] pci 0000:ff:14.2: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   11.490764][    T1] pci 0000:ff:14.3: [8086:2fb3] type 00 class 0x088000
[   11.497880][    T1] pci 0000:ff:14.3: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   11.506850][    T1] pci 0000:ff:14.3: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   11.515896][    T1] pci 0000:ff:14.4: [8086:2fbc] type 00 class 0x088000
[   11.523864][    T1] pci 0000:ff:14.4: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   11.541698][    T1] pci 0000:ff:14.4: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   11.550888][    T1] pci 0000:ff:14.5: [8086:2fbd] type 00 class 0x088000
[   11.558860][    T1] pci 0000:ff:14.5: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   11.567847][    T1] pci 0000:ff:14.5: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   11.576901][    T1] pci 0000:ff:14.6: [8086:2fbe] type 00 class 0x088000
[   11.583859][    T1] pci 0000:ff:14.6: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   11.592848][    T1] pci 0000:ff:14.6: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   11.601852][    T1] pci 0000:ff:14.7: [8086:2fbf] type 00 class 0x088000
[   11.609859][    T1] pci 0000:ff:14.7: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   11.618850][    T1] pci 0000:ff:14.7: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   11.627913][    T1] pci 0000:ff:15.0: [8086:2fb4] type 00 class 0x088000
[   11.634864][    T1] pci 0000:ff:15.0: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   11.643848][    T1] pci 0000:ff:15.0: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   11.652903][    T1] pci 0000:ff:15.1: [8086:2fb5] type 00 class 0x088000
[   11.660864][    T1] pci 0000:ff:15.1: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   11.669848][    T1] pci 0000:ff:15.1: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   11.678856][    T1] pci 0000:ff:15.2: [8086:2fb6] type 00 class 0x088000
[   11.686891][    T1] pci 0000:ff:15.2: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   11.695846][    T1] pci 0000:ff:15.2: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   11.704900][    T1] pci 0000:ff:15.3: [8086:2fb7] type 00 class 0x088000
[   11.711863][    T1] pci 0000:ff:15.3: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   11.720846][    T1] pci 0000:ff:15.3: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   11.729858][    T1] pci 0000:ff:16.0: [8086:2f68] type 00 class 0x088000
[   11.737864][    T1] pci 0000:ff:16.0: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   11.746847][    T1] pci 0000:ff:16.0: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   11.755897][    T1] pci 0000:ff:16.1: [8086:2f79] type 00 class 0x088000
[   11.763863][    T1] pci 0000:ff:16.1: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   11.772846][    T1] pci 0000:ff:16.1: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   11.780906][    T1] pci 0000:ff:16.2: [8086:2f6a] type 00 class 0x088000
[   11.788862][    T1] pci 0000:ff:16.2: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   11.797846][    T1] pci 0000:ff:16.2: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   11.806901][    T1] pci 0000:ff:16.3: [8086:2f6b] type 00 class 0x088000
[   11.814866][    T1] pci 0000:ff:16.3: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   11.823852][    T1] pci 0000:ff:16.3: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   11.832960][    T1] pci 0000:ff:16.4: [8086:2f6c] type 00 class 0x088000
[   11.839869][    T1] pci 0000:ff:16.4: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   11.848846][    T1] pci 0000:ff:16.4: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   11.857915][    T1] pci 0000:ff:16.5: [8086:2f6d] type 00 class 0x088000
[   11.865868][    T1] pci 0000:ff:16.5: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   11.874852][    T1] pci 0000:ff:16.5: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   11.883855][    T1] pci 0000:ff:16.6: [8086:2f6e] type 00 class 0x088000
[   11.891877][    T1] pci 0000:ff:16.6: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   11.900846][    T1] pci 0000:ff:16.6: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   11.909899][    T1] pci 0000:ff:16.7: [8086:2f6f] type 00 class 0x088000
[   11.916862][    T1] pci 0000:ff:16.7: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   11.925847][    T1] pci 0000:ff:16.7: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   11.934852][    T1] pci 0000:ff:17.0: [8086:2fd0] type 00 class 0x088000
[   11.942865][    T1] pci 0000:ff:17.0: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   11.951846][    T1] pci 0000:ff:17.0: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   11.960906][    T1] pci 0000:ff:17.1: [8086:2fd1] type 00 class 0x088000
[   11.968863][    T1] pci 0000:ff:17.1: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   11.977852][    T1] pci 0000:ff:17.1: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   11.986741][    T1] pci 0000:ff:17.2: [8086:2fd2] type 00 class 0x088000
[   11.993866][    T1] pci 0000:ff:17.2: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   12.002847][    T1] pci 0000:ff:17.2: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   12.011908][    T1] pci 0000:ff:17.3: [8086:2fd3] type 00 class 0x088000
[   12.019863][    T1] pci 0000:ff:17.3: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   12.028848][    T1] pci 0000:ff:17.3: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   12.037858][    T1] pci 0000:ff:17.4: [8086:2fb8] type 00 class 0x088000
[   12.044888][    T1] pci 0000:ff:17.4: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   12.053847][    T1] pci 0000:ff:17.4: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   12.062896][    T1] pci 0000:ff:17.5: [8086:2fb9] type 00 class 0x088000
[   12.070859][    T1] pci 0000:ff:17.5: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   12.079846][    T1] pci 0000:ff:17.5: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   12.088878][    T1] pci 0000:ff:17.6: [8086:2fba] type 00 class 0x088000
[   12.096858][    T1] pci 0000:ff:17.6: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   12.105847][    T1] pci 0000:ff:17.6: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   12.114852][    T1] pci 0000:ff:17.7: [8086:2fbb] type 00 class 0x088000
[   12.121890][    T1] pci 0000:ff:17.7: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   12.130846][    T1] pci 0000:ff:17.7: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   12.139891][    T1] pci 0000:ff:18.0: [8086:2fd4] type 00 class 0x088000
[   12.147865][    T1] pci 0000:ff:18.0: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   12.156846][    T1] pci 0000:ff:18.0: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   12.165858][    T1] pci 0000:ff:18.1: [8086:2fd5] type 00 class 0x088000
[   12.172864][    T1] pci 0000:ff:18.1: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   12.181846][    T1] pci 0000:ff:18.1: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   12.190893][    T1] pci 0000:ff:18.2: [8086:2fd6] type 00 class 0x088000
[   12.198864][    T1] pci 0000:ff:18.2: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   12.207852][    T1] pci 0000:ff:18.2: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   12.216914][    T1] pci 0000:ff:18.3: [8086:2fd7] type 00 class 0x088000
[   12.224862][    T1] pci 0000:ff:18.3: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   12.233846][    T1] pci 0000:ff:18.3: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   12.242899][    T1] pci 0000:ff:1e.0: [8086:2f98] type 00 class 0x088000
[   12.249856][    T1] pci 0000:ff:1e.0: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   12.258846][    T1] pci 0000:ff:1e.0: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   12.267889][    T1] pci 0000:ff:1e.1: [8086:2f99] type 00 class 0x088000
[   12.275859][    T1] pci 0000:ff:1e.1: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   12.284850][    T1] pci 0000:ff:1e.1: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   12.293892][    T1] pci 0000:ff:1e.2: [8086:2f9a] type 00 class 0x088000
[   12.300857][    T1] pci 0000:ff:1e.2: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   12.309852][    T1] pci 0000:ff:1e.2: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   12.318871][    T1] pci 0000:ff:1e.3: calling  quirk_intel_brickland_xeon_ras_cap+0x0/0x80 @ 1
[   12.328854][    T1] pci 0000:ff:1e.3: quirk_intel_brickland_xeon_ras_cap+0x0/0x80 took 0 usecs
[   12.338851][    T1] pci 0000:ff:1e.3: calling  pci_invalid_bar+0x0/0x40 @ 1
[   12.346816][    T1] pci 0000:ff:1e.3: pci_invalid_bar+0x0/0x40 took 0 usecs
[   12.354818][    T1] pci 0000:ff:1e.3: [8086:2fc0] type 00 class 0x088000
[   12.361824][    T1] pci 0000:ff:1e.3: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   12.370848][    T1] pci 0000:ff:1e.3: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   12.379896][    T1] pci 0000:ff:1e.4: [8086:2f9c] type 00 class 0x088000
[   12.387857][    T1] pci 0000:ff:1e.4: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   12.396847][    T1] pci 0000:ff:1e.4: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   12.405851][    T1] pci 0000:ff:1f.0: [8086:2f88] type 00 class 0x088000
[   12.412857][    T1] pci 0000:ff:1f.0: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   12.421849][    T1] pci 0000:ff:1f.0: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   12.430852][    T1] pci 0000:ff:1f.2: [8086:2f8a] type 00 class 0x088000
[   12.438897][    T1] pci 0000:ff:1f.2: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   12.447846][    T1] pci 0000:ff:1f.2: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   12.457083][    T1] ACPI: PCI Root Bridge [UNC2] (domain 0000 [bus bf])
[   12.464822][    T1] acpi PNP0A03:01: _OSC: OS supports [ExtendedConfig ASPM ClockPM Segments MSI HPX-Type3]
[   12.484801][    T1] PCI host bridge to bus 0000:bf
[   12.489811][    T1] pci_bus 0000:bf: Unknown NUMA node; performance will be reduced
[   12.498846][    T1] pci_bus 0000:bf: root bus resource [bus bf]
[   12.505822][    T1] pci 0000:bf:08.0: [8086:2f80] type 00 class 0x088000
[   12.512858][    T1] pci 0000:bf:08.0: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   12.521847][    T1] pci 0000:bf:08.0: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   12.530851][    T1] pci 0000:bf:08.2: [8086:2f32] type 00 class 0x110100
[   12.538863][    T1] pci 0000:bf:08.2: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   12.547847][    T1] pci 0000:bf:08.2: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   12.556888][    T1] pci 0000:bf:09.0: [8086:2f90] type 00 class 0x088000
[   12.563858][    T1] pci 0000:bf:09.0: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   12.572846][    T1] pci 0000:bf:09.0: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   12.581879][    T1] pci 0000:bf:09.2: [8086:2f33] type 00 class 0x110100
[   12.589858][    T1] pci 0000:bf:09.2: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   12.598853][    T1] pci 0000:bf:09.2: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   12.607851][    T1] pci 0000:bf:0a.0: [8086:2f40] type 00 class 0x088000
[   12.615860][    T1] pci 0000:bf:0a.0: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   12.624846][    T1] pci 0000:bf:0a.0: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   12.633892][    T1] pci 0000:bf:0a.2: [8086:2f3a] type 00 class 0x110100
[   12.640859][    T1] pci 0000:bf:0a.2: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   12.649847][    T1] pci 0000:bf:0a.2: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   12.658852][    T1] pci 0000:bf:0b.0: [8086:2f81] type 00 class 0x088000
[   12.666858][    T1] pci 0000:bf:0b.0: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   12.675846][    T1] pci 0000:bf:0b.0: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   12.684877][    T1] pci 0000:bf:0b.1: [8086:2f36] type 00 class 0x110100
[   12.691858][    T1] pci 0000:bf:0b.1: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   12.700846][    T1] pci 0000:bf:0b.1: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   12.709894][    T1] pci 0000:bf:0b.4: [8086:2f41] type 00 class 0x088000
[   12.717856][    T1] pci 0000:bf:0b.4: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   12.726847][    T1] pci 0000:bf:0b.4: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   12.735852][    T1] pci 0000:bf:0b.5: [8086:2f3e] type 00 class 0x110100
[   12.742858][    T1] pci 0000:bf:0b.5: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   12.751847][    T1] pci 0000:bf:0b.5: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   12.760881][    T1] pci 0000:bf:0b.6: [8086:2f3f] type 00 class 0x110100
[   12.768857][    T1] pci 0000:bf:0b.6: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   12.777847][    T1] pci 0000:bf:0b.6: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   12.786850][    T1] pci 0000:bf:0c.0: [8086:2fe0] type 00 class 0x088000
[   12.794879][    T1] pci 0000:bf:0c.0: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   12.803846][    T1] pci 0000:bf:0c.0: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   12.812890][    T1] pci 0000:bf:0c.1: [8086:2fe1] type 00 class 0x088000
[   12.819857][    T1] pci 0000:bf:0c.1: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   12.828846][    T1] pci 0000:bf:0c.1: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   12.837882][    T1] pci 0000:bf:0c.2: [8086:2fe2] type 00 class 0x088000
[   12.845856][    T1] pci 0000:bf:0c.2: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   12.854849][    T1] pci 0000:bf:0c.2: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   12.863851][    T1] pci 0000:bf:0c.3: [8086:2fe3] type 00 class 0x088000
[   12.870872][    T1] pci 0000:bf:0c.3: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   12.879846][    T1] pci 0000:bf:0c.3: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   12.888879][    T1] pci 0000:bf:0c.4: [8086:2fe4] type 00 class 0x088000
[   12.896857][    T1] pci 0000:bf:0c.4: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   12.905850][    T1] pci 0000:bf:0c.4: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   12.914854][    T1] pci 0000:bf:0c.5: [8086:2fe5] type 00 class 0x088000
[   12.921858][    T1] pci 0000:bf:0c.5: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   12.930847][    T1] pci 0000:bf:0c.5: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   12.939874][    T1] pci 0000:bf:0c.6: [8086:2fe6] type 00 class 0x088000
[   12.947855][    T1] pci 0000:bf:0c.6: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   12.956847][    T1] pci 0000:bf:0c.6: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   12.965885][    T1] pci 0000:bf:0c.7: [8086:2fe7] type 00 class 0x088000
[   12.973856][    T1] pci 0000:bf:0c.7: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   12.982847][    T1] pci 0000:bf:0c.7: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   12.991850][    T1] pci 0000:bf:0d.0: [8086:2fe8] type 00 class 0x088000
[   12.998863][    T1] pci 0000:bf:0d.0: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   13.007846][    T1] pci 0000:bf:0d.0: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   13.016885][    T1] pci 0000:bf:0d.1: [8086:2fe9] type 00 class 0x088000
[   13.024857][    T1] pci 0000:bf:0d.1: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   13.033847][    T1] pci 0000:bf:0d.1: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   13.042853][    T1] pci 0000:bf:0d.2: [8086:2fea] type 00 class 0x088000
[   13.049858][    T1] pci 0000:bf:0d.2: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   13.058846][    T1] pci 0000:bf:0d.2: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   13.067893][    T1] pci 0000:bf:0d.3: [8086:2feb] type 00 class 0x088000
[   13.075856][    T1] pci 0000:bf:0d.3: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   13.084846][    T1] pci 0000:bf:0d.3: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   13.093872][    T1] pci 0000:bf:0d.4: [8086:2fec] type 00 class 0x088000
[   13.100855][    T1] pci 0000:bf:0d.4: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   13.109847][    T1] pci 0000:bf:0d.4: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   13.118851][    T1] pci 0000:bf:0d.5: [8086:2fed] type 00 class 0x088000
[   13.126864][    T1] pci 0000:bf:0d.5: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   13.135846][    T1] pci 0000:bf:0d.5: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   13.144878][    T1] pci 0000:bf:0d.6: [8086:2fee] type 00 class 0x088000
[   13.152859][    T1] pci 0000:bf:0d.6: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   13.160847][    T1] pci 0000:bf:0d.6: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   13.169884][    T1] pci 0000:bf:0d.7: [8086:2fef] type 00 class 0x088000
[   13.177857][    T1] pci 0000:bf:0d.7: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   13.186846][    T1] pci 0000:bf:0d.7: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   13.195889][    T1] pci 0000:bf:0e.0: [8086:2ff0] type 00 class 0x088000
[   13.203857][    T1] pci 0000:bf:0e.0: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   13.212846][    T1] pci 0000:bf:0e.0: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   13.221882][    T1] pci 0000:bf:0e.1: [8086:2ff1] type 00 class 0x088000
[   13.228860][    T1] pci 0000:bf:0e.1: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   13.237848][    T1] pci 0000:bf:0e.1: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   13.246887][    T1] pci 0000:bf:0f.0: [8086:2ff8] type 00 class 0x088000
[   13.254857][    T1] pci 0000:bf:0f.0: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   13.263848][    T1] pci 0000:bf:0f.0: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   13.272851][    T1] pci 0000:bf:0f.1: [8086:2ff9] type 00 class 0x088000
[   13.279859][    T1] pci 0000:bf:0f.1: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   13.288848][    T1] pci 0000:bf:0f.1: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   13.297890][    T1] pci 0000:bf:0f.2: [8086:2ffa] type 00 class 0x088000
[   13.305856][    T1] pci 0000:bf:0f.2: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   13.314846][    T1] pci 0000:bf:0f.2: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   13.323879][    T1] pci 0000:bf:0f.3: [8086:2ffb] type 00 class 0x088000
[   13.331856][    T1] pci 0000:bf:0f.3: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   13.339847][    T1] pci 0000:bf:0f.3: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   13.349736][    T1] pci 0000:bf:0f.4: [8086:2ffc] type 00 class 0x088000
[   13.356858][    T1] pci 0000:bf:0f.4: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   13.365846][    T1] pci 0000:bf:0f.4: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   13.374872][    T1] pci 0000:bf:0f.5: [8086:2ffd] type 00 class 0x088000
[   13.382858][    T1] pci 0000:bf:0f.5: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   13.391846][    T1] pci 0000:bf:0f.5: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   13.409742][    T1] pci 0000:bf:0f.6: [8086:2ffe] type 00 class 0x088000
[   13.417859][    T1] pci 0000:bf:0f.6: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   13.425851][    T1] pci 0000:bf:0f.6: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   13.434887][    T1] pci 0000:bf:10.0: [8086:2f1d] type 00 class 0x088000
[   13.442859][    T1] pci 0000:bf:10.0: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   13.451847][    T1] pci 0000:bf:10.0: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   13.460891][    T1] pci 0000:bf:10.1: [8086:2f34] type 00 class 0x110100
[   13.468856][    T1] pci 0000:bf:10.1: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   13.477847][    T1] pci 0000:bf:10.1: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   13.486884][    T1] pci 0000:bf:10.5: [8086:2f1e] type 00 class 0x088000
[   13.493857][    T1] pci 0000:bf:10.5: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   13.502848][    T1] pci 0000:bf:10.5: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   13.511889][    T1] pci 0000:bf:10.7: [8086:2f1f] type 00 class 0x088000
[   13.519856][    T1] pci 0000:bf:10.7: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   13.528848][    T1] pci 0000:bf:10.7: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   13.537853][    T1] pci 0000:bf:12.0: [8086:2fa0] type 00 class 0x088000
[   13.544864][    T1] pci 0000:bf:12.0: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   13.553847][    T1] pci 0000:bf:12.0: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   13.562883][    T1] pci 0000:bf:12.1: [8086:2f30] type 00 class 0x110100
[   13.570859][    T1] pci 0000:bf:12.1: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   13.579850][    T1] pci 0000:bf:12.1: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   13.588853][    T1] pci 0000:bf:12.2: [8086:2f70] type 00 class 0x088000
[   13.596859][    T1] pci 0000:bf:12.2: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   13.605850][    T1] pci 0000:bf:12.2: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   13.613913][    T1] pci 0000:bf:12.4: [8086:2f60] type 00 class 0x088000
[   13.621859][    T1] pci 0000:bf:12.4: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   13.630846][    T1] pci 0000:bf:12.4: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   13.639882][    T1] pci 0000:bf:12.5: [8086:2f38] type 00 class 0x110100
[   13.647858][    T1] pci 0000:bf:12.5: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   13.656848][    T1] pci 0000:bf:12.5: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   13.665853][    T1] pci 0000:bf:13.0: [8086:2fa8] type 00 class 0x088000
[   13.672890][    T1] pci 0000:bf:13.0: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   13.681847][    T1] pci 0000:bf:13.0: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   13.690908][    T1] pci 0000:bf:13.1: [8086:2f71] type 00 class 0x088000
[   13.698865][    T1] pci 0000:bf:13.1: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   13.707849][    T1] pci 0000:bf:13.1: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   13.716900][    T1] pci 0000:bf:13.2: [8086:2faa] type 00 class 0x088000
[   13.724865][    T1] pci 0000:bf:13.2: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   13.732847][    T1] pci 0000:bf:13.2: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   13.741910][    T1] pci 0000:bf:13.3: [8086:2fab] type 00 class 0x088000
[   13.749865][    T1] pci 0000:bf:13.3: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   13.758847][    T1] pci 0000:bf:13.3: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   13.767856][    T1] pci 0000:bf:13.4: [8086:2fac] type 00 class 0x088000
[   13.775865][    T1] pci 0000:bf:13.4: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   13.784847][    T1] pci 0000:bf:13.4: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   13.793906][    T1] pci 0000:bf:13.5: [8086:2fad] type 00 class 0x088000
[   13.800865][    T1] pci 0000:bf:13.5: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   13.809849][    T1] pci 0000:bf:13.5: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   13.818856][    T1] pci 0000:bf:13.6: [8086:2fae] type 00 class 0x088000
[   13.826861][    T1] pci 0000:bf:13.6: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   13.835846][    T1] pci 0000:bf:13.6: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   13.844893][    T1] pci 0000:bf:13.7: [8086:2faf] type 00 class 0x088000
[   13.851859][    T1] pci 0000:bf:13.7: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   13.860847][    T1] pci 0000:bf:13.7: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   13.869873][    T1] pci 0000:bf:14.0: [8086:2fb0] type 00 class 0x088000
[   13.877862][    T1] pci 0000:bf:14.0: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   13.886847][    T1] pci 0000:bf:14.0: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   13.895853][    T1] pci 0000:bf:14.1: [8086:2fb1] type 00 class 0x088000
[   13.903864][    T1] pci 0000:bf:14.1: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   13.912846][    T1] pci 0000:bf:14.1: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   13.921909][    T1] pci 0000:bf:14.2: [8086:2fb2] type 00 class 0x088000
[   13.928863][    T1] pci 0000:bf:14.2: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   13.937847][    T1] pci 0000:bf:14.2: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   13.946857][    T1] pci 0000:bf:14.3: [8086:2fb3] type 00 class 0x088000
[   13.954864][    T1] pci 0000:bf:14.3: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   13.963846][    T1] pci 0000:bf:14.3: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   13.972912][    T1] pci 0000:bf:14.4: [8086:2fbc] type 00 class 0x088000
[   13.980701][    T1] pci 0000:bf:14.4: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   13.988848][    T1] pci 0000:bf:14.4: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   13.997903][    T1] pci 0000:bf:14.5: [8086:2fbd] type 00 class 0x088000
[   14.005861][    T1] pci 0000:bf:14.5: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   14.014846][    T1] pci 0000:bf:14.5: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   14.023877][    T1] pci 0000:bf:14.6: [8086:2fbe] type 00 class 0x088000
[   14.031861][    T1] pci 0000:bf:14.6: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   14.039850][    T1] pci 0000:bf:14.6: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   14.049716][    T1] pci 0000:bf:14.7: [8086:2fbf] type 00 class 0x088000
[   14.056861][    T1] pci 0000:bf:14.7: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   14.065846][    T1] pci 0000:bf:14.7: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   14.074892][    T1] pci 0000:bf:15.0: [8086:2fb4] type 00 class 0x088000
[   14.082863][    T1] pci 0000:bf:15.0: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   14.091849][    T1] pci 0000:bf:15.0: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   14.100855][    T1] pci 0000:bf:15.1: [8086:2fb5] type 00 class 0x088000
[   14.107865][    T1] pci 0000:bf:15.1: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   14.116847][    T1] pci 0000:bf:15.1: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   14.125852][    T1] pci 0000:bf:15.2: [8086:2fb6] type 00 class 0x088000
[   14.133863][    T1] pci 0000:bf:15.2: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   14.142846][    T1] pci 0000:bf:15.2: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   14.151911][    T1] pci 0000:bf:15.3: [8086:2fb7] type 00 class 0x088000
[   14.158862][    T1] pci 0000:bf:15.3: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   14.167846][    T1] pci 0000:bf:15.3: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   14.176899][    T1] pci 0000:bf:16.0: [8086:2f68] type 00 class 0x088000
[   14.184862][    T1] pci 0000:bf:16.0: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   14.193847][    T1] pci 0000:bf:16.0: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   14.202854][    T1] pci 0000:bf:16.1: [8086:2f79] type 00 class 0x088000
[   14.210865][    T1] pci 0000:bf:16.1: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   14.219846][    T1] pci 0000:bf:16.1: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   14.228909][    T1] pci 0000:bf:16.2: [8086:2f6a] type 00 class 0x088000
[   14.235865][    T1] pci 0000:bf:16.2: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   14.244849][    T1] pci 0000:bf:16.2: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   14.253855][    T1] pci 0000:bf:16.3: [8086:2f6b] type 00 class 0x088000
[   14.261865][    T1] pci 0000:bf:16.3: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   14.270847][    T1] pci 0000:bf:16.3: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   14.279893][    T1] pci 0000:bf:16.4: [8086:2f6c] type 00 class 0x088000
[   14.286863][    T1] pci 0000:bf:16.4: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   14.295848][    T1] pci 0000:bf:16.4: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   14.304904][    T1] pci 0000:bf:16.5: [8086:2f6d] type 00 class 0x088000
[   14.312862][    T1] pci 0000:bf:16.5: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   14.321848][    T1] pci 0000:bf:16.5: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   14.339758][    T1] pci 0000:bf:16.6: [8086:2f6e] type 00 class 0x088000
[   14.347861][    T1] pci 0000:bf:16.6: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   14.356847][    T1] pci 0000:bf:16.6: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   14.365883][    T1] pci 0000:bf:16.7: [8086:2f6f] type 00 class 0x088000
[   14.372860][    T1] pci 0000:bf:16.7: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   14.381848][    T1] pci 0000:bf:16.7: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   14.390852][    T1] pci 0000:bf:17.0: [8086:2fd0] type 00 class 0x088000
[   14.398865][    T1] pci 0000:bf:17.0: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   14.407846][    T1] pci 0000:bf:17.0: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   14.416908][    T1] pci 0000:bf:17.1: [8086:2fd1] type 00 class 0x088000
[   14.424863][    T1] pci 0000:bf:17.1: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   14.433846][    T1] pci 0000:bf:17.1: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   14.442890][    T1] pci 0000:bf:17.2: [8086:2fd2] type 00 class 0x088000
[   14.449863][    T1] pci 0000:bf:17.2: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   14.458850][    T1] pci 0000:bf:17.2: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   14.467853][    T1] pci 0000:bf:17.3: [8086:2fd3] type 00 class 0x088000
[   14.475864][    T1] pci 0000:bf:17.3: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   14.484847][    T1] pci 0000:bf:17.3: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   14.493905][    T1] pci 0000:bf:17.4: [8086:2fb8] type 00 class 0x088000
[   14.500860][    T1] pci 0000:bf:17.4: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   14.509848][    T1] pci 0000:bf:17.4: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   14.518851][    T1] pci 0000:bf:17.5: [8086:2fb9] type 00 class 0x088000
[   14.526860][    T1] pci 0000:bf:17.5: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   14.535851][    T1] pci 0000:bf:17.5: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   14.544886][    T1] pci 0000:bf:17.6: [8086:2fba] type 00 class 0x088000
[   14.551860][    T1] pci 0000:bf:17.6: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   14.560846][    T1] pci 0000:bf:17.6: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   14.569891][    T1] pci 0000:bf:17.7: [8086:2fbb] type 00 class 0x088000
[   14.577858][    T1] pci 0000:bf:17.7: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   14.586846][    T1] pci 0000:bf:17.7: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   14.595880][    T1] pci 0000:bf:18.0: [8086:2fd4] type 00 class 0x088000
[   14.603866][    T1] pci 0000:bf:18.0: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   14.612854][    T1] pci 0000:bf:18.0: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   14.621908][    T1] pci 0000:bf:18.1: [8086:2fd5] type 00 class 0x088000
[   14.628863][    T1] pci 0000:bf:18.1: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   14.637849][    T1] pci 0000:bf:18.1: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   14.646854][    T1] pci 0000:bf:18.2: [8086:2fd6] type 00 class 0x088000
[   14.654895][    T1] pci 0000:bf:18.2: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   14.663846][    T1] pci 0000:bf:18.2: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   14.672910][    T1] pci 0000:bf:18.3: [8086:2fd7] type 00 class 0x088000
[   14.679863][    T1] pci 0000:bf:18.3: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   14.688846][    T1] pci 0000:bf:18.3: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   14.697910][    T1] pci 0000:bf:1e.0: [8086:2f98] type 00 class 0x088000
[   14.705856][    T1] pci 0000:bf:1e.0: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   14.714850][    T1] pci 0000:bf:1e.0: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   14.723853][    T1] pci 0000:bf:1e.1: [8086:2f99] type 00 class 0x088000
[   14.731896][    T1] pci 0000:bf:1e.1: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   14.740846][    T1] pci 0000:bf:1e.1: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   14.749894][    T1] pci 0000:bf:1e.2: [8086:2f9a] type 00 class 0x088000
[   14.756857][    T1] pci 0000:bf:1e.2: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   14.765846][    T1] pci 0000:bf:1e.2: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   14.774851][    T1] pci 0000:bf:1e.3: calling  quirk_intel_brickland_xeon_ras_cap+0x0/0x80 @ 1
[   14.784850][    T1] pci 0000:bf:1e.3: quirk_intel_brickland_xeon_ras_cap+0x0/0x80 took 0 usecs
[   14.794849][    T1] pci 0000:bf:1e.3: calling  pci_invalid_bar+0x0/0x40 @ 1
[   14.802816][    T1] pci 0000:bf:1e.3: pci_invalid_bar+0x0/0x40 took 0 usecs
[   14.809816][    T1] pci 0000:bf:1e.3: [8086:2fc0] type 00 class 0x088000
[   14.817830][    T1] pci 0000:bf:1e.3: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   14.826846][    T1] pci 0000:bf:1e.3: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   14.835906][    T1] pci 0000:bf:1e.4: [8086:2f9c] type 00 class 0x088000
[   14.843856][    T1] pci 0000:bf:1e.4: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   14.852847][    T1] pci 0000:bf:1e.4: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   14.861921][    T1] pci 0000:bf:1f.0: [8086:2f88] type 00 class 0x088000
[   14.868856][    T1] pci 0000:bf:1f.0: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   14.877847][    T1] pci 0000:bf:1f.0: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   14.886852][    T1] pci 0000:bf:1f.2: [8086:2f8a] type 00 class 0x088000
[   14.894861][    T1] pci 0000:bf:1f.2: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   14.903852][    T1] pci 0000:bf:1f.2: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   14.913023][    T1] ACPI: PCI Root Bridge [UNC1] (domain 0000 [bus 7f])
[   14.919820][    T1] acpi PNP0A03:02: _OSC: OS supports [ExtendedConfig ASPM ClockPM Segments MSI HPX-Type3]
[   14.930887][    T1] PCI host bridge to bus 0000:7f
[   14.936810][    T1] pci_bus 0000:7f: Unknown NUMA node; performance will be reduced
[   14.945845][    T1] pci_bus 0000:7f: root bus resource [bus 7f]
[   14.951823][    T1] pci 0000:7f:08.0: [8086:2f80] type 00 class 0x088000
[   14.959856][    T1] pci 0000:7f:08.0: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   14.968848][    T1] pci 0000:7f:08.0: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   14.977895][    T1] pci 0000:7f:08.2: [8086:2f32] type 00 class 0x110100
[   14.984858][    T1] pci 0000:7f:08.2: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   14.993847][    T1] pci 0000:7f:08.2: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   15.003727][    T1] pci 0000:7f:09.0: [8086:2f90] type 00 class 0x088000
[   15.010857][    T1] pci 0000:7f:09.0: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   15.019852][    T1] pci 0000:7f:09.0: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   15.028895][    T1] pci 0000:7f:09.2: [8086:2f33] type 00 class 0x110100
[   15.036861][    T1] pci 0000:7f:09.2: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   15.045846][    T1] pci 0000:7f:09.2: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   15.053878][    T1] pci 0000:7f:0a.0: [8086:2f40] type 00 class 0x088000
[   15.061855][    T1] pci 0000:7f:0a.0: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   15.070848][    T1] pci 0000:7f:0a.0: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   15.079850][    T1] pci 0000:7f:0a.2: [8086:2f3a] type 00 class 0x110100
[   15.087858][    T1] pci 0000:7f:0a.2: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   15.096846][    T1] pci 0000:7f:0a.2: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   15.105885][    T1] pci 0000:7f:0b.0: [8086:2f81] type 00 class 0x088000
[   15.112855][    T1] pci 0000:7f:0b.0: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   15.121847][    T1] pci 0000:7f:0b.0: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   15.130851][    T1] pci 0000:7f:0b.1: [8086:2f36] type 00 class 0x110100
[   15.138858][    T1] pci 0000:7f:0b.1: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   15.147846][    T1] pci 0000:7f:0b.1: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   15.156891][    T1] pci 0000:7f:0b.4: [8086:2f41] type 00 class 0x088000
[   15.163854][    T1] pci 0000:7f:0b.4: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   15.172848][    T1] pci 0000:7f:0b.4: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   15.181881][    T1] pci 0000:7f:0b.5: [8086:2f3e] type 00 class 0x110100
[   15.189860][    T1] pci 0000:7f:0b.5: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   15.198847][    T1] pci 0000:7f:0b.5: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   15.207852][    T1] pci 0000:7f:0b.6: [8086:2f3f] type 00 class 0x110100
[   15.214856][    T1] pci 0000:7f:0b.6: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   15.223846][    T1] pci 0000:7f:0b.6: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   15.232888][    T1] pci 0000:7f:0c.0: [8086:2fe0] type 00 class 0x088000
[   15.240855][    T1] pci 0000:7f:0c.0: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   15.249847][    T1] pci 0000:7f:0c.0: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   15.258852][    T1] pci 0000:7f:0c.1: [8086:2fe1] type 00 class 0x088000
[   15.266856][    T1] pci 0000:7f:0c.1: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   15.284698][    T1] pci 0000:7f:0c.1: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   15.293897][    T1] pci 0000:7f:0c.2: [8086:2fe2] type 00 class 0x088000
[   15.300854][    T1] pci 0000:7f:0c.2: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   15.309847][    T1] pci 0000:7f:0c.2: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   15.318891][    T1] pci 0000:7f:0c.3: [8086:2fe3] type 00 class 0x088000
[   15.326855][    T1] pci 0000:7f:0c.3: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   15.335846][    T1] pci 0000:7f:0c.3: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   15.344850][    T1] pci 0000:7f:0c.4: [8086:2fe4] type 00 class 0x088000
[   15.352855][    T1] pci 0000:7f:0c.4: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   15.361846][    T1] pci 0000:7f:0c.4: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   15.369894][    T1] pci 0000:7f:0c.5: [8086:2fe5] type 00 class 0x088000
[   15.377855][    T1] pci 0000:7f:0c.5: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   15.386847][    T1] pci 0000:7f:0c.5: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   15.395856][    T1] pci 0000:7f:0c.6: [8086:2fe6] type 00 class 0x088000
[   15.403856][    T1] pci 0000:7f:0c.6: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   15.412846][    T1] pci 0000:7f:0c.6: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   15.421852][    T1] pci 0000:7f:0c.7: [8086:2fe7] type 00 class 0x088000
[   15.428857][    T1] pci 0000:7f:0c.7: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   15.437846][    T1] pci 0000:7f:0c.7: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   15.446876][    T1] pci 0000:7f:0d.0: [8086:2fe8] type 00 class 0x088000
[   15.454853][    T1] pci 0000:7f:0d.0: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   15.463846][    T1] pci 0000:7f:0d.0: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   15.472901][    T1] pci 0000:7f:0d.1: [8086:2fe9] type 00 class 0x088000
[   15.479858][    T1] pci 0000:7f:0d.1: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   15.488850][    T1] pci 0000:7f:0d.1: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   15.497852][    T1] pci 0000:7f:0d.2: [8086:2fea] type 00 class 0x088000
[   15.505856][    T1] pci 0000:7f:0d.2: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   15.514846][    T1] pci 0000:7f:0d.2: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   15.523897][    T1] pci 0000:7f:0d.3: [8086:2feb] type 00 class 0x088000
[   15.530855][    T1] pci 0000:7f:0d.3: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   15.539848][    T1] pci 0000:7f:0d.3: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   15.549747][    T1] pci 0000:7f:0d.4: [8086:2fec] type 00 class 0x088000
[   15.556858][    T1] pci 0000:7f:0d.4: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   15.565846][    T1] pci 0000:7f:0d.4: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   15.574875][    T1] pci 0000:7f:0d.5: [8086:2fed] type 00 class 0x088000
[   15.582854][    T1] pci 0000:7f:0d.5: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   15.591852][    T1] pci 0000:7f:0d.5: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   15.600893][    T1] pci 0000:7f:0d.6: [8086:2fee] type 00 class 0x088000
[   15.607858][    T1] pci 0000:7f:0d.6: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   15.616849][    T1] pci 0000:7f:0d.6: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   15.625852][    T1] pci 0000:7f:0d.7: [8086:2fef] type 00 class 0x088000
[   15.633857][    T1] pci 0000:7f:0d.7: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   15.642848][    T1] pci 0000:7f:0d.7: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   15.651900][    T1] pci 0000:7f:0e.0: [8086:2ff0] type 00 class 0x088000
[   15.658855][    T1] pci 0000:7f:0e.0: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   15.667847][    T1] pci 0000:7f:0e.0: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   15.676850][    T1] pci 0000:7f:0e.1: [8086:2ff1] type 00 class 0x088000
[   15.684857][    T1] pci 0000:7f:0e.1: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   15.693847][    T1] pci 0000:7f:0e.1: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   15.702873][    T1] pci 0000:7f:0f.0: [8086:2ff8] type 00 class 0x088000
[   15.710855][    T1] pci 0000:7f:0f.0: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   15.718846][    T1] pci 0000:7f:0f.0: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   15.727898][    T1] pci 0000:7f:0f.1: [8086:2ff9] type 00 class 0x088000
[   15.735853][    T1] pci 0000:7f:0f.1: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   15.744849][    T1] pci 0000:7f:0f.1: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   15.753850][    T1] pci 0000:7f:0f.2: [8086:2ffa] type 00 class 0x088000
[   15.761858][    T1] pci 0000:7f:0f.2: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   15.770846][    T1] pci 0000:7f:0f.2: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   15.779893][    T1] pci 0000:7f:0f.3: [8086:2ffb] type 00 class 0x088000
[   15.786855][    T1] pci 0000:7f:0f.3: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   15.795846][    T1] pci 0000:7f:0f.3: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   15.804851][    T1] pci 0000:7f:0f.4: [8086:2ffc] type 00 class 0x088000
[   15.812891][    T1] pci 0000:7f:0f.4: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   15.821846][    T1] pci 0000:7f:0f.4: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   15.830898][    T1] pci 0000:7f:0f.5: [8086:2ffd] type 00 class 0x088000
[   15.837854][    T1] pci 0000:7f:0f.5: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   15.846846][    T1] pci 0000:7f:0f.5: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   15.855881][    T1] pci 0000:7f:0f.6: [8086:2ffe] type 00 class 0x088000
[   15.863854][    T1] pci 0000:7f:0f.6: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   15.872847][    T1] pci 0000:7f:0f.6: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   15.881856][    T1] pci 0000:7f:10.0: [8086:2f1d] type 00 class 0x088000
[   15.889895][    T1] pci 0000:7f:10.0: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   15.898850][    T1] pci 0000:7f:10.0: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   15.906897][    T1] pci 0000:7f:10.1: [8086:2f34] type 00 class 0x110100
[   15.914855][    T1] pci 0000:7f:10.1: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   15.923846][    T1] pci 0000:7f:10.1: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   15.932850][    T1] pci 0000:7f:10.5: [8086:2f1e] type 00 class 0x088000
[   15.940856][    T1] pci 0000:7f:10.5: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   15.949846][    T1] pci 0000:7f:10.5: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   15.958890][    T1] pci 0000:7f:10.7: [8086:2f1f] type 00 class 0x088000
[   15.965854][    T1] pci 0000:7f:10.7: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   15.974846][    T1] pci 0000:7f:10.7: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   15.983903][    T1] pci 0000:7f:12.0: [8086:2fa0] type 00 class 0x088000
[   15.991855][    T1] pci 0000:7f:12.0: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   16.000847][    T1] pci 0000:7f:12.0: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   16.009850][    T1] pci 0000:7f:12.1: [8086:2f30] type 00 class 0x110100
[   16.017858][    T1] pci 0000:7f:12.1: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   16.025852][    T1] pci 0000:7f:12.1: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   16.034895][    T1] pci 0000:7f:12.2: [8086:2f70] type 00 class 0x088000
[   16.042857][    T1] pci 0000:7f:12.2: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   16.051854][    T1] pci 0000:7f:12.2: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   16.060921][    T1] pci 0000:7f:12.4: [8086:2f60] type 00 class 0x088000
[   16.068858][    T1] pci 0000:7f:12.4: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   16.077848][    T1] pci 0000:7f:12.4: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   16.086893][    T1] pci 0000:7f:12.5: [8086:2f38] type 00 class 0x110100
[   16.093856][    T1] pci 0000:7f:12.5: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   16.102847][    T1] pci 0000:7f:12.5: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   16.112718][    T1] pci 0000:7f:13.0: [8086:2fa8] type 00 class 0x088000
[   16.119862][    T1] pci 0000:7f:13.0: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   16.128847][    T1] pci 0000:7f:13.0: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   16.137904][    T1] pci 0000:7f:13.1: [8086:2f71] type 00 class 0x088000
[   16.145859][    T1] pci 0000:7f:13.1: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   16.154846][    T1] pci 0000:7f:13.1: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   16.163898][    T1] pci 0000:7f:13.2: [8086:2faa] type 00 class 0x088000
[   16.170859][    T1] pci 0000:7f:13.2: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   16.179847][    T1] pci 0000:7f:13.2: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   16.188854][    T1] pci 0000:7f:13.3: [8086:2fab] type 00 class 0x088000
[   16.196862][    T1] pci 0000:7f:13.3: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   16.214698][    T1] pci 0000:7f:13.3: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   16.223884][    T1] pci 0000:7f:13.4: [8086:2fac] type 00 class 0x088000
[   16.231858][    T1] pci 0000:7f:13.4: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   16.240847][    T1] pci 0000:7f:13.4: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   16.249908][    T1] pci 0000:7f:13.5: [8086:2fad] type 00 class 0x088000
[   16.256860][    T1] pci 0000:7f:13.5: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   16.265846][    T1] pci 0000:7f:13.5: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   16.274882][    T1] pci 0000:7f:13.6: [8086:2fae] type 00 class 0x088000
[   16.282856][    T1] pci 0000:7f:13.6: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   16.291847][    T1] pci 0000:7f:13.6: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   16.300852][    T1] pci 0000:7f:13.7: [8086:2faf] type 00 class 0x088000
[   16.308858][    T1] pci 0000:7f:13.7: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   16.317851][    T1] pci 0000:7f:13.7: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   16.326896][    T1] pci 0000:7f:14.0: [8086:2fb0] type 00 class 0x088000
[   16.333860][    T1] pci 0000:7f:14.0: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   16.342853][    T1] pci 0000:7f:14.0: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   16.351891][    T1] pci 0000:7f:14.1: [8086:2fb1] type 00 class 0x088000
[   16.359861][    T1] pci 0000:7f:14.1: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   16.368847][    T1] pci 0000:7f:14.1: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   16.377852][    T1] pci 0000:7f:14.2: [8086:2fb2] type 00 class 0x088000
[   16.385873][    T1] pci 0000:7f:14.2: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   16.394846][    T1] pci 0000:7f:14.2: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   16.403902][    T1] pci 0000:7f:14.3: [8086:2fb3] type 00 class 0x088000
[   16.410860][    T1] pci 0000:7f:14.3: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   16.419846][    T1] pci 0000:7f:14.3: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   16.428888][    T1] pci 0000:7f:14.4: [8086:2fbc] type 00 class 0x088000
[   16.436856][    T1] pci 0000:7f:14.4: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   16.445847][    T1] pci 0000:7f:14.4: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   16.454850][    T1] pci 0000:7f:14.5: [8086:2fbd] type 00 class 0x088000
[   16.461859][    T1] pci 0000:7f:14.5: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   16.470846][    T1] pci 0000:7f:14.5: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   16.479892][    T1] pci 0000:7f:14.6: [8086:2fbe] type 00 class 0x088000
[   16.487857][    T1] pci 0000:7f:14.6: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   16.496846][    T1] pci 0000:7f:14.6: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   16.505852][    T1] pci 0000:7f:14.7: [8086:2fbf] type 00 class 0x088000
[   16.513858][    T1] pci 0000:7f:14.7: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   16.522846][    T1] pci 0000:7f:14.7: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   16.531851][    T1] pci 0000:7f:15.0: [8086:2fb4] type 00 class 0x088000
[   16.538862][    T1] pci 0000:7f:15.0: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   16.547846][    T1] pci 0000:7f:15.0: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   16.556909][    T1] pci 0000:7f:15.1: [8086:2fb5] type 00 class 0x088000
[   16.564859][    T1] pci 0000:7f:15.1: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   16.573848][    T1] pci 0000:7f:15.1: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   16.582903][    T1] pci 0000:7f:15.2: [8086:2fb6] type 00 class 0x088000
[   16.589859][    T1] pci 0000:7f:15.2: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   16.598849][    T1] pci 0000:7f:15.2: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   16.608761][    T1] pci 0000:7f:15.3: [8086:2fb7] type 00 class 0x088000
[   16.615870][    T1] pci 0000:7f:15.3: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   16.624846][    T1] pci 0000:7f:15.3: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   16.633904][    T1] pci 0000:7f:16.0: [8086:2f68] type 00 class 0x088000
[   16.641862][    T1] pci 0000:7f:16.0: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   16.650846][    T1] pci 0000:7f:16.0: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   16.659908][    T1] pci 0000:7f:16.1: [8086:2f79] type 00 class 0x088000
[   16.666865][    T1] pci 0000:7f:16.1: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   16.675848][    T1] pci 0000:7f:16.1: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   16.684858][    T1] pci 0000:7f:16.2: [8086:2f6a] type 00 class 0x088000
[   16.692864][    T1] pci 0000:7f:16.2: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   16.701846][    T1] pci 0000:7f:16.2: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   16.710902][    T1] pci 0000:7f:16.3: [8086:2f6b] type 00 class 0x088000
[   16.718863][    T1] pci 0000:7f:16.3: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   16.727846][    T1] pci 0000:7f:16.3: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   16.736852][    T1] pci 0000:7f:16.4: [8086:2f6c] type 00 class 0x088000
[   16.743863][    T1] pci 0000:7f:16.4: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   16.752847][    T1] pci 0000:7f:16.4: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   16.761911][    T1] pci 0000:7f:16.5: [8086:2f6d] type 00 class 0x088000
[   16.769862][    T1] pci 0000:7f:16.5: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   16.778846][    T1] pci 0000:7f:16.5: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   16.787905][    T1] pci 0000:7f:16.6: [8086:2f6e] type 00 class 0x088000
[   16.794859][    T1] pci 0000:7f:16.6: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   16.803846][    T1] pci 0000:7f:16.6: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   16.812877][    T1] pci 0000:7f:16.7: [8086:2f6f] type 00 class 0x088000
[   16.820857][    T1] pci 0000:7f:16.7: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   16.829853][    T1] pci 0000:7f:16.7: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   16.838883][    T1] pci 0000:7f:17.0: [8086:2fd0] type 00 class 0x088000
[   16.846864][    T1] pci 0000:7f:17.0: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   16.855847][    T1] pci 0000:7f:17.0: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   16.864854][    T1] pci 0000:7f:17.1: [8086:2fd1] type 00 class 0x088000
[   16.871864][    T1] pci 0000:7f:17.1: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   16.880846][    T1] pci 0000:7f:17.1: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   16.889893][    T1] pci 0000:7f:17.2: [8086:2fd2] type 00 class 0x088000
[   16.897863][    T1] pci 0000:7f:17.2: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   16.906852][    T1] pci 0000:7f:17.2: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   16.915857][    T1] pci 0000:7f:17.3: [8086:2fd3] type 00 class 0x088000
[   16.923863][    T1] pci 0000:7f:17.3: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   16.932850][    T1] pci 0000:7f:17.3: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   16.941920][    T1] pci 0000:7f:17.4: [8086:2fb8] type 00 class 0x088000
[   16.948862][    T1] pci 0000:7f:17.4: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   16.957846][    T1] pci 0000:7f:17.4: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   16.966895][    T1] pci 0000:7f:17.5: [8086:2fb9] type 00 class 0x088000
[   16.974858][    T1] pci 0000:7f:17.5: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   16.983846][    T1] pci 0000:7f:17.5: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   16.992876][    T1] pci 0000:7f:17.6: [8086:2fba] type 00 class 0x088000
[   16.999861][    T1] pci 0000:7f:17.6: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   17.008847][    T1] pci 0000:7f:17.6: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   17.017920][    T1] pci 0000:7f:17.7: [8086:2fbb] type 00 class 0x088000
[   17.025858][    T1] pci 0000:7f:17.7: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   17.034847][    T1] pci 0000:7f:17.7: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   17.043850][    T1] pci 0000:7f:18.0: [8086:2fd4] type 00 class 0x088000
[   17.051866][    T1] pci 0000:7f:18.0: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   17.060849][    T1] pci 0000:7f:18.0: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   17.069924][    T1] pci 0000:7f:18.1: [8086:2fd5] type 00 class 0x088000
[   17.076864][    T1] pci 0000:7f:18.1: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   17.085847][    T1] pci 0000:7f:18.1: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   17.094903][    T1] pci 0000:7f:18.2: [8086:2fd6] type 00 class 0x088000
[   17.102862][    T1] pci 0000:7f:18.2: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   17.111848][    T1] pci 0000:7f:18.2: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   17.120853][    T1] pci 0000:7f:18.3: [8086:2fd7] type 00 class 0x088000
[   17.127870][    T1] pci 0000:7f:18.3: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   17.146700][    T1] pci 0000:7f:18.3: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   17.155917][    T1] pci 0000:7f:1e.0: [8086:2f98] type 00 class 0x088000
[   17.162858][    T1] pci 0000:7f:1e.0: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   17.171848][    T1] pci 0000:7f:1e.0: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   17.180883][    T1] pci 0000:7f:1e.1: [8086:2f99] type 00 class 0x088000
[   17.188855][    T1] pci 0000:7f:1e.1: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   17.197849][    T1] pci 0000:7f:1e.1: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   17.206851][    T1] pci 0000:7f:1e.2: [8086:2f9a] type 00 class 0x088000
[   17.213858][    T1] pci 0000:7f:1e.2: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   17.222846][    T1] pci 0000:7f:1e.2: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   17.231891][    T1] pci 0000:7f:1e.3: calling  quirk_intel_brickland_xeon_ras_cap+0x0/0x80 @ 1
[   17.241850][    T1] pci 0000:7f:1e.3: quirk_intel_brickland_xeon_ras_cap+0x0/0x80 took 0 usecs
[   17.251849][    T1] pci 0000:7f:1e.3: calling  pci_invalid_bar+0x0/0x40 @ 1
[   17.258816][    T1] pci 0000:7f:1e.3: pci_invalid_bar+0x0/0x40 took 0 usecs
[   17.266819][    T1] pci 0000:7f:1e.3: [8086:2fc0] type 00 class 0x088000
[   17.274825][    T1] pci 0000:7f:1e.3: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   17.283847][    T1] pci 0000:7f:1e.3: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   17.292883][    T1] pci 0000:7f:1e.4: [8086:2f9c] type 00 class 0x088000
[   17.299856][    T1] pci 0000:7f:1e.4: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   17.308846][    T1] pci 0000:7f:1e.4: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   17.317899][    T1] pci 0000:7f:1f.0: [8086:2f88] type 00 class 0x088000
[   17.325860][    T1] pci 0000:7f:1f.0: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   17.334847][    T1] pci 0000:7f:1f.0: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   17.343894][    T1] pci 0000:7f:1f.2: [8086:2f8a] type 00 class 0x088000
[   17.351856][    T1] pci 0000:7f:1f.2: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   17.360848][    T1] pci 0000:7f:1f.2: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   17.370008][    T1] ACPI: PCI Root Bridge [UNC0] (domain 0000 [bus 3f])
[   17.376820][    T1] acpi PNP0A03:03: _OSC: OS supports [ExtendedConfig ASPM ClockPM Segments MSI HPX-Type3]
[   17.387890][    T1] PCI host bridge to bus 0000:3f
[   17.393810][    T1] pci_bus 0000:3f: Unknown NUMA node; performance will be reduced
[   17.401846][    T1] pci_bus 0000:3f: root bus resource [bus 3f]
[   17.408820][    T1] pci 0000:3f:08.0: [8086:2f80] type 00 class 0x088000
[   17.416864][    T1] pci 0000:3f:08.0: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   17.425847][    T1] pci 0000:3f:08.0: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   17.434879][    T1] pci 0000:3f:08.2: [8086:2f32] type 00 class 0x110100
[   17.441857][    T1] pci 0000:3f:08.2: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   17.450846][    T1] pci 0000:3f:08.2: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   17.459895][    T1] pci 0000:3f:09.0: [8086:2f90] type 00 class 0x088000
[   17.467857][    T1] pci 0000:3f:09.0: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   17.476847][    T1] pci 0000:3f:09.0: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   17.485851][    T1] pci 0000:3f:09.2: [8086:2f33] type 00 class 0x110100
[   17.492865][    T1] pci 0000:3f:09.2: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   17.501846][    T1] pci 0000:3f:09.2: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   17.510890][    T1] pci 0000:3f:0a.0: [8086:2f40] type 00 class 0x088000
[   17.518858][    T1] pci 0000:3f:0a.0: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   17.527852][    T1] pci 0000:3f:0a.0: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   17.536852][    T1] pci 0000:3f:0a.2: [8086:2f3a] type 00 class 0x110100
[   17.544863][    T1] pci 0000:3f:0a.2: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   17.553846][    T1] pci 0000:3f:0a.2: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   17.561897][    T1] pci 0000:3f:0b.0: [8086:2f81] type 00 class 0x088000
[   17.569856][    T1] pci 0000:3f:0b.0: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   17.578846][    T1] pci 0000:3f:0b.0: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   17.587885][    T1] pci 0000:3f:0b.1: [8086:2f36] type 00 class 0x110100
[   17.595857][    T1] pci 0000:3f:0b.1: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   17.604846][    T1] pci 0000:3f:0b.1: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   17.613857][    T1] pci 0000:3f:0b.4: [8086:2f41] type 00 class 0x088000
[   17.620858][    T1] pci 0000:3f:0b.4: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   17.629852][    T1] pci 0000:3f:0b.4: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   17.638899][    T1] pci 0000:3f:0b.5: [8086:2f3e] type 00 class 0x110100
[   17.646857][    T1] pci 0000:3f:0b.5: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   17.655846][    T1] pci 0000:3f:0b.5: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   17.664854][    T1] pci 0000:3f:0b.6: [8086:2f3f] type 00 class 0x110100
[   17.671858][    T1] pci 0000:3f:0b.6: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   17.680846][    T1] pci 0000:3f:0b.6: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   17.690727][    T1] pci 0000:3f:0c.0: [8086:2fe0] type 00 class 0x088000
[   17.697857][    T1] pci 0000:3f:0c.0: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   17.706846][    T1] pci 0000:3f:0c.0: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   17.715886][    T1] pci 0000:3f:0c.1: [8086:2fe1] type 00 class 0x088000
[   17.723856][    T1] pci 0000:3f:0c.1: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   17.732846][    T1] pci 0000:3f:0c.1: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   17.740868][    T1] pci 0000:3f:0c.2: [8086:2fe2] type 00 class 0x088000
[   17.748855][    T1] pci 0000:3f:0c.2: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   17.757853][    T1] pci 0000:3f:0c.2: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   17.766852][    T1] pci 0000:3f:0c.3: [8086:2fe3] type 00 class 0x088000
[   17.774858][    T1] pci 0000:3f:0c.3: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   17.783848][    T1] pci 0000:3f:0c.3: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   17.792894][    T1] pci 0000:3f:0c.4: [8086:2fe4] type 00 class 0x088000
[   17.799857][    T1] pci 0000:3f:0c.4: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   17.808846][    T1] pci 0000:3f:0c.4: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   17.817852][    T1] pci 0000:3f:0c.5: [8086:2fe5] type 00 class 0x088000
[   17.825858][    T1] pci 0000:3f:0c.5: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   17.834846][    T1] pci 0000:3f:0c.5: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   17.843854][    T1] pci 0000:3f:0c.6: [8086:2fe6] type 00 class 0x088000
[   17.850859][    T1] pci 0000:3f:0c.6: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   17.859847][    T1] pci 0000:3f:0c.6: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   17.868879][    T1] pci 0000:3f:0c.7: [8086:2fe7] type 00 class 0x088000
[   17.876856][    T1] pci 0000:3f:0c.7: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   17.885846][    T1] pci 0000:3f:0c.7: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   17.894886][    T1] pci 0000:3f:0d.0: [8086:2fe8] type 00 class 0x088000
[   17.902857][    T1] pci 0000:3f:0d.0: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   17.910848][    T1] pci 0000:3f:0d.0: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   17.920732][    T1] pci 0000:3f:0d.1: [8086:2fe9] type 00 class 0x088000
[   17.927858][    T1] pci 0000:3f:0d.1: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   17.936848][    T1] pci 0000:3f:0d.1: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   17.945887][    T1] pci 0000:3f:0d.2: [8086:2fea] type 00 class 0x088000
[   17.953857][    T1] pci 0000:3f:0d.2: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   17.962852][    T1] pci 0000:3f:0d.2: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   17.971852][    T1] pci 0000:3f:0d.3: [8086:2feb] type 00 class 0x088000
[   17.978858][    T1] pci 0000:3f:0d.3: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   17.987846][    T1] pci 0000:3f:0d.3: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   17.996892][    T1] pci 0000:3f:0d.4: [8086:2fec] type 00 class 0x088000
[   18.004855][    T1] pci 0000:3f:0d.4: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   18.013848][    T1] pci 0000:3f:0d.4: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   18.022873][    T1] pci 0000:3f:0d.5: [8086:2fed] type 00 class 0x088000
[   18.029855][    T1] pci 0000:3f:0d.5: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   18.038847][    T1] pci 0000:3f:0d.5: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   18.047853][    T1] pci 0000:3f:0d.6: [8086:2fee] type 00 class 0x088000
[   18.055865][    T1] pci 0000:3f:0d.6: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   18.064846][    T1] pci 0000:3f:0d.6: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   18.082731][    T1] pci 0000:3f:0d.7: [8086:2fef] type 00 class 0x088000
[   18.090856][    T1] pci 0000:3f:0d.7: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   18.099846][    T1] pci 0000:3f:0d.7: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   18.108892][    T1] pci 0000:3f:0e.0: [8086:2ff0] type 00 class 0x088000
[   18.116702][    T1] pci 0000:3f:0e.0: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   18.124855][    T1] pci 0000:3f:0e.0: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   18.133895][    T1] pci 0000:3f:0e.1: [8086:2ff1] type 00 class 0x088000
[   18.141857][    T1] pci 0000:3f:0e.1: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   18.150847][    T1] pci 0000:3f:0e.1: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   18.159857][    T1] pci 0000:3f:0f.0: [8086:2ff8] type 00 class 0x088000
[   18.167858][    T1] pci 0000:3f:0f.0: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   18.176846][    T1] pci 0000:3f:0f.0: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   18.185884][    T1] pci 0000:3f:0f.1: [8086:2ff9] type 00 class 0x088000
[   18.192856][    T1] pci 0000:3f:0f.1: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   18.201846][    T1] pci 0000:3f:0f.1: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   18.210874][    T1] pci 0000:3f:0f.2: [8086:2ffa] type 00 class 0x088000
[   18.218855][    T1] pci 0000:3f:0f.2: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   18.227847][    T1] pci 0000:3f:0f.2: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   18.236850][    T1] pci 0000:3f:0f.3: [8086:2ffb] type 00 class 0x088000
[   18.243862][    T1] pci 0000:3f:0f.3: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   18.252846][    T1] pci 0000:3f:0f.3: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   18.261876][    T1] pci 0000:3f:0f.4: [8086:2ffc] type 00 class 0x088000
[   18.269857][    T1] pci 0000:3f:0f.4: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   18.278846][    T1] pci 0000:3f:0f.4: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   18.287851][    T1] pci 0000:3f:0f.5: [8086:2ffd] type 00 class 0x088000
[   18.295860][    T1] pci 0000:3f:0f.5: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   18.303851][    T1] pci 0000:3f:0f.5: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   18.313746][    T1] pci 0000:3f:0f.6: [8086:2ffe] type 00 class 0x088000
[   18.320858][    T1] pci 0000:3f:0f.6: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   18.329846][    T1] pci 0000:3f:0f.6: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   18.338851][    T1] pci 0000:3f:10.0: [8086:2f1d] type 00 class 0x088000
[   18.346861][    T1] pci 0000:3f:10.0: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   18.355851][    T1] pci 0000:3f:10.0: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   18.364892][    T1] pci 0000:3f:10.1: [8086:2f34] type 00 class 0x110100
[   18.371855][    T1] pci 0000:3f:10.1: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   18.380850][    T1] pci 0000:3f:10.1: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   18.389887][    T1] pci 0000:3f:10.5: [8086:2f1e] type 00 class 0x088000
[   18.397855][    T1] pci 0000:3f:10.5: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   18.406847][    T1] pci 0000:3f:10.5: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   18.415852][    T1] pci 0000:3f:10.7: [8086:2f1f] type 00 class 0x088000
[   18.423861][    T1] pci 0000:3f:10.7: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   18.432846][    T1] pci 0000:3f:10.7: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   18.440890][    T1] pci 0000:3f:12.0: [8086:2fa0] type 00 class 0x088000
[   18.448859][    T1] pci 0000:3f:12.0: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   18.457846][    T1] pci 0000:3f:12.0: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   18.466880][    T1] pci 0000:3f:12.1: [8086:2f30] type 00 class 0x110100
[   18.474861][    T1] pci 0000:3f:12.1: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   18.483850][    T1] pci 0000:3f:12.1: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   18.492857][    T1] pci 0000:3f:12.2: [8086:2f70] type 00 class 0x088000
[   18.499860][    T1] pci 0000:3f:12.2: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   18.508846][    T1] pci 0000:3f:12.2: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   18.517892][    T1] pci 0000:3f:12.4: [8086:2f60] type 00 class 0x088000
[   18.525859][    T1] pci 0000:3f:12.4: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   18.534852][    T1] pci 0000:3f:12.4: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   18.543854][    T1] pci 0000:3f:12.5: [8086:2f38] type 00 class 0x110100
[   18.550862][    T1] pci 0000:3f:12.5: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   18.559846][    T1] pci 0000:3f:12.5: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   18.568884][    T1] pci 0000:3f:13.0: [8086:2fa8] type 00 class 0x088000
[   18.576861][    T1] pci 0000:3f:13.0: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   18.585846][    T1] pci 0000:3f:13.0: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   18.594907][    T1] pci 0000:3f:13.1: [8086:2f71] type 00 class 0x088000
[   18.602861][    T1] pci 0000:3f:13.1: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   18.611847][    T1] pci 0000:3f:13.1: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   18.620852][    T1] pci 0000:3f:13.2: [8086:2faa] type 00 class 0x088000
[   18.627863][    T1] pci 0000:3f:13.2: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   18.636852][    T1] pci 0000:3f:13.2: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   18.645914][    T1] pci 0000:3f:13.3: [8086:2fab] type 00 class 0x088000
[   18.653862][    T1] pci 0000:3f:13.3: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   18.662846][    T1] pci 0000:3f:13.3: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   18.671853][    T1] pci 0000:3f:13.4: [8086:2fac] type 00 class 0x088000
[   18.678865][    T1] pci 0000:3f:13.4: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   18.687846][    T1] pci 0000:3f:13.4: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   18.696889][    T1] pci 0000:3f:13.5: [8086:2fad] type 00 class 0x088000
[   18.704861][    T1] pci 0000:3f:13.5: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   18.713846][    T1] pci 0000:3f:13.5: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   18.722910][    T1] pci 0000:3f:13.6: [8086:2fae] type 00 class 0x088000
[   18.730859][    T1] pci 0000:3f:13.6: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   18.739848][    T1] pci 0000:3f:13.6: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   18.748852][    T1] pci 0000:3f:13.7: [8086:2faf] type 00 class 0x088000
[   18.755860][    T1] pci 0000:3f:13.7: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   18.764853][    T1] pci 0000:3f:13.7: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   18.773901][    T1] pci 0000:3f:14.0: [8086:2fb0] type 00 class 0x088000
[   18.781863][    T1] pci 0000:3f:14.0: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   18.790846][    T1] pci 0000:3f:14.0: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   18.799851][    T1] pci 0000:3f:14.1: [8086:2fb1] type 00 class 0x088000
[   18.806863][    T1] pci 0000:3f:14.1: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   18.815846][    T1] pci 0000:3f:14.1: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   18.824911][    T1] pci 0000:3f:14.2: [8086:2fb2] type 00 class 0x088000
[   18.832862][    T1] pci 0000:3f:14.2: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   18.841847][    T1] pci 0000:3f:14.2: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   18.850894][    T1] pci 0000:3f:14.3: [8086:2fb3] type 00 class 0x088000
[   18.858861][    T1] pci 0000:3f:14.3: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   18.867847][    T1] pci 0000:3f:14.3: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   18.876738][    T1] pci 0000:3f:14.4: [8086:2fbc] type 00 class 0x088000
[   18.883860][    T1] pci 0000:3f:14.4: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   18.892846][    T1] pci 0000:3f:14.4: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   18.901892][    T1] pci 0000:3f:14.5: [8086:2fbd] type 00 class 0x088000
[   18.909859][    T1] pci 0000:3f:14.5: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   18.918846][    T1] pci 0000:3f:14.5: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   18.927854][    T1] pci 0000:3f:14.6: [8086:2fbe] type 00 class 0x088000
[   18.934866][    T1] pci 0000:3f:14.6: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   18.943848][    T1] pci 0000:3f:14.6: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   18.952896][    T1] pci 0000:3f:14.7: [8086:2fbf] type 00 class 0x088000
[   18.960859][    T1] pci 0000:3f:14.7: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   18.969846][    T1] pci 0000:3f:14.7: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   18.978880][    T1] pci 0000:3f:15.0: [8086:2fb4] type 00 class 0x088000
[   18.985861][    T1] pci 0000:3f:15.0: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   18.994847][    T1] pci 0000:3f:15.0: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   19.013755][    T1] pci 0000:3f:15.1: [8086:2fb5] type 00 class 0x088000
[   19.020865][    T1] pci 0000:3f:15.1: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   19.029846][    T1] pci 0000:3f:15.1: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   19.038896][    T1] pci 0000:3f:15.2: [8086:2fb6] type 00 class 0x088000
[   19.046864][    T1] pci 0000:3f:15.2: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   19.055849][    T1] pci 0000:3f:15.2: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   19.064853][    T1] pci 0000:3f:15.3: [8086:2fb7] type 00 class 0x088000
[   19.072870][    T1] pci 0000:3f:15.3: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   19.081848][    T1] pci 0000:3f:15.3: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   19.090903][    T1] pci 0000:3f:16.0: [8086:2f68] type 00 class 0x088000
[   19.097862][    T1] pci 0000:3f:16.0: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   19.106847][    T1] pci 0000:3f:16.0: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   19.115908][    T1] pci 0000:3f:16.1: [8086:2f79] type 00 class 0x088000
[   19.123864][    T1] pci 0000:3f:16.1: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   19.132847][    T1] pci 0000:3f:16.1: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   19.141856][    T1] pci 0000:3f:16.2: [8086:2f6a] type 00 class 0x088000
[   19.148864][    T1] pci 0000:3f:16.2: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   19.157846][    T1] pci 0000:3f:16.2: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   19.166915][    T1] pci 0000:3f:16.3: [8086:2f6b] type 00 class 0x088000
[   19.174863][    T1] pci 0000:3f:16.3: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   19.183846][    T1] pci 0000:3f:16.3: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   19.192852][    T1] pci 0000:3f:16.4: [8086:2f6c] type 00 class 0x088000
[   19.200866][    T1] pci 0000:3f:16.4: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   19.209847][    T1] pci 0000:3f:16.4: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   19.218894][    T1] pci 0000:3f:16.5: [8086:2f6d] type 00 class 0x088000
[   19.225862][    T1] pci 0000:3f:16.5: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   19.234846][    T1] pci 0000:3f:16.5: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   19.243904][    T1] pci 0000:3f:16.6: [8086:2f6e] type 00 class 0x088000
[   19.251858][    T1] pci 0000:3f:16.6: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   19.260847][    T1] pci 0000:3f:16.6: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   19.269855][    T1] pci 0000:3f:16.7: [8086:2f6f] type 00 class 0x088000
[   19.276861][    T1] pci 0000:3f:16.7: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   19.285846][    T1] pci 0000:3f:16.7: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   19.294906][    T1] pci 0000:3f:17.0: [8086:2fd0] type 00 class 0x088000
[   19.302864][    T1] pci 0000:3f:17.0: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   19.311846][    T1] pci 0000:3f:17.0: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   19.320852][    T1] pci 0000:3f:17.1: [8086:2fd1] type 00 class 0x088000
[   19.328885][    T1] pci 0000:3f:17.1: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   19.337846][    T1] pci 0000:3f:17.1: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   19.345911][    T1] pci 0000:3f:17.2: [8086:2fd2] type 00 class 0x088000
[   19.353867][    T1] pci 0000:3f:17.2: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   19.362847][    T1] pci 0000:3f:17.2: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   19.371913][    T1] pci 0000:3f:17.3: [8086:2fd3] type 00 class 0x088000
[   19.379863][    T1] pci 0000:3f:17.3: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   19.388846][    T1] pci 0000:3f:17.3: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   19.397887][    T1] pci 0000:3f:17.4: [8086:2fb8] type 00 class 0x088000
[   19.404858][    T1] pci 0000:3f:17.4: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   19.413846][    T1] pci 0000:3f:17.4: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   19.422891][    T1] pci 0000:3f:17.5: [8086:2fb9] type 00 class 0x088000
[   19.430859][    T1] pci 0000:3f:17.5: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   19.439848][    T1] pci 0000:3f:17.5: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   19.448879][    T1] pci 0000:3f:17.6: [8086:2fba] type 00 class 0x088000
[   19.456864][    T1] pci 0000:3f:17.6: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   19.464848][    T1] pci 0000:3f:17.6: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   19.474733][    T1] pci 0000:3f:17.7: [8086:2fbb] type 00 class 0x088000
[   19.481860][    T1] pci 0000:3f:17.7: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   19.490846][    T1] pci 0000:3f:17.7: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   19.499853][    T1] pci 0000:3f:18.0: [8086:2fd4] type 00 class 0x088000
[   19.507869][    T1] pci 0000:3f:18.0: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   19.516847][    T1] pci 0000:3f:18.0: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   19.525903][    T1] pci 0000:3f:18.1: [8086:2fd5] type 00 class 0x088000
[   19.532863][    T1] pci 0000:3f:18.1: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   19.541848][    T1] pci 0000:3f:18.1: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   19.550888][    T1] pci 0000:3f:18.2: [8086:2fd6] type 00 class 0x088000
[   19.558863][    T1] pci 0000:3f:18.2: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   19.567848][    T1] pci 0000:3f:18.2: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   19.576853][    T1] pci 0000:3f:18.3: [8086:2fd7] type 00 class 0x088000
[   19.584866][    T1] pci 0000:3f:18.3: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   19.592847][    T1] pci 0000:3f:18.3: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   19.601921][    T1] pci 0000:3f:1e.0: [8086:2f98] type 00 class 0x088000
[   19.609859][    T1] pci 0000:3f:1e.0: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   19.618848][    T1] pci 0000:3f:1e.0: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   19.627855][    T1] pci 0000:3f:1e.1: [8086:2f99] type 00 class 0x088000
[   19.635884][    T1] pci 0000:3f:1e.1: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   19.644849][    T1] pci 0000:3f:1e.1: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   19.653889][    T1] pci 0000:3f:1e.2: [8086:2f9a] type 00 class 0x088000
[   19.660858][    T1] pci 0000:3f:1e.2: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   19.669849][    T1] pci 0000:3f:1e.2: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   19.678881][    T1] pci 0000:3f:1e.3: calling  quirk_intel_brickland_xeon_ras_cap+0x0/0x80 @ 1
[   19.688854][    T1] pci 0000:3f:1e.3: quirk_intel_brickland_xeon_ras_cap+0x0/0x80 took 0 usecs
[   19.698849][    T1] pci 0000:3f:1e.3: calling  pci_invalid_bar+0x0/0x40 @ 1
[   19.706817][    T1] pci 0000:3f:1e.3: pci_invalid_bar+0x0/0x40 took 0 usecs
[   19.713818][    T1] pci 0000:3f:1e.3: [8086:2fc0] type 00 class 0x088000
[   19.721731][    T1] pci 0000:3f:1e.3: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   19.730848][    T1] pci 0000:3f:1e.3: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   19.739907][    T1] pci 0000:3f:1e.4: [8086:2f9c] type 00 class 0x088000
[   19.747858][    T1] pci 0000:3f:1e.4: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   19.756848][    T1] pci 0000:3f:1e.4: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   19.765852][    T1] pci 0000:3f:1f.0: [8086:2f88] type 00 class 0x088000
[   19.772891][    T1] pci 0000:3f:1f.0: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   19.781847][    T1] pci 0000:3f:1f.0: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   19.790906][    T1] pci 0000:3f:1f.2: [8086:2f8a] type 00 class 0x088000
[   19.798859][    T1] pci 0000:3f:1f.2: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   19.807848][    T1] pci 0000:3f:1f.2: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   19.910797][    T1] ACPI: PCI Root Bridge [IIO0] (domain 0000 [bus 00-3e])
[   19.917820][    T1] acpi PNP0A08:00: _OSC: OS supports [ExtendedConfig ASPM ClockPM Segments MSI HPX-Type3]
[   19.930207][    T1] acpi PNP0A08:00: _OSC: platform does not support [SHPCHotplug LTR]
[   19.940546][    T1] acpi PNP0A08:00: _OSC: OS now controls [PCIeHotplug PME AER PCIeCapability]
[   19.949850][    T1] acpi PNP0A08:00: FADT indicates ASPM is unsupported, using BIOS configuration
[   19.959995][    T1] acpi PNP0A08:00: ignoring host bridge window [mem 0x000c4000-0x000cbfff window] (conflicts with Video ROM [mem 0x000c0000-0x000c7fff])
[   19.976352][    T1] PCI host bridge to bus 0000:00
[   19.981813][    T1] pci_bus 0000:00: Unknown NUMA node; performance will be reduced
[   19.990849][    T1] pci_bus 0000:00: root bus resource [io  0x0000-0x0cf7 window]
[   19.998847][    T1] pci_bus 0000:00: root bus resource [io  0x1000-0x3fff window]
[   20.007845][    T1] pci_bus 0000:00: root bus resource [mem 0x000a0000-0x000bffff window]
[   20.016847][    T1] pci_bus 0000:00: root bus resource [mem 0xfed40000-0xfedfffff window]
[   20.025848][    T1] pci_bus 0000:00: root bus resource [mem 0x90000000-0xabffbfff window]
[   20.044700][    T1] pci_bus 0000:00: root bus resource [mem 0x380000000000-0x381fffffffff window]
[   20.054856][    T1] pci_bus 0000:00: root bus resource [bus 00-3e]
[   20.061905][    T1] pci 0000:00:00.0: calling  quirk_mmio_always_on+0x0/0x40 @ 1
[   20.069845][    T1] pci 0000:00:00.0: quirk_mmio_always_on+0x0/0x40 took 0 usecs
[   20.077845][    T1] pci 0000:00:00.0: [8086:2f00] type 00 class 0x060000
[   20.085873][    T1] pci 0000:00:00.0: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   20.094846][    T1] pci 0000:00:00.0: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   20.103981][    T1] pci 0000:00:02.0: calling  quirk_cmd_compl+0x0/0x80 @ 1
[   20.111821][    T1] pci 0000:00:02.0: quirk_cmd_compl+0x0/0x80 took 0 usecs
[   20.119818][    T1] pci 0000:00:02.0: calling  quirk_no_aersid+0x0/0x40 @ 1
[   20.127818][    T1] pci 0000:00:02.0: quirk_no_aersid+0x0/0x40 took 0 usecs
[   20.135818][    T1] pci 0000:00:02.0: [8086:2f04] type 01 class 0x060400
[   20.142867][    T1] pci 0000:00:02.0: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   20.151848][    T1] pci 0000:00:02.0: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   20.160846][    T1] pci 0000:00:02.0: calling  pci_fixup_transparent_bridge+0x0/0x40 @ 1
[   20.169849][    T1] pci 0000:00:02.0: pci_fixup_transparent_bridge+0x0/0x40 took 0 usecs
[   20.178875][    T1] pci 0000:00:02.0: PME# supported from D0 D3hot D3cold
[   20.186979][    T1] pci 0000:00:03.0: calling  quirk_cmd_compl+0x0/0x80 @ 1
[   20.194818][    T1] pci 0000:00:03.0: quirk_cmd_compl+0x0/0x80 took 0 usecs
[   20.202816][    T1] pci 0000:00:03.0: calling  quirk_no_aersid+0x0/0x40 @ 1
[   20.210818][    T1] pci 0000:00:03.0: quirk_no_aersid+0x0/0x40 took 0 usecs
[   20.218816][    T1] pci 0000:00:03.0: [8086:2f08] type 01 class 0x060400
[   20.225871][    T1] pci 0000:00:03.0: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   20.234847][    T1] pci 0000:00:03.0: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   20.243846][    T1] pci 0000:00:03.0: calling  pci_fixup_transparent_bridge+0x0/0x40 @ 1
[   20.252846][    T1] pci 0000:00:03.0: pci_fixup_transparent_bridge+0x0/0x40 took 0 usecs
[   20.262878][    T1] pci 0000:00:03.0: PME# supported from D0 D3hot D3cold
[   20.269853][    T1] pci 0000:00:03.2: calling  quirk_cmd_compl+0x0/0x80 @ 1
[   20.277819][    T1] pci 0000:00:03.2: quirk_cmd_compl+0x0/0x80 took 0 usecs
[   20.285817][    T1] pci 0000:00:03.2: calling  quirk_no_aersid+0x0/0x40 @ 1
[   20.293816][    T1] pci 0000:00:03.2: quirk_no_aersid+0x0/0x40 took 0 usecs
[   20.301818][    T1] pci 0000:00:03.2: [8086:2f0a] type 01 class 0x060400
[   20.309729][    T1] pci 0000:00:03.2: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   20.317848][    T1] pci 0000:00:03.2: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   20.326846][    T1] pci 0000:00:03.2: calling  pci_fixup_transparent_bridge+0x0/0x40 @ 1
[   20.336847][    T1] pci 0000:00:03.2: pci_fixup_transparent_bridge+0x0/0x40 took 0 usecs
[   20.345876][    T1] pci 0000:00:03.2: PME# supported from D0 D3hot D3cold
[   20.353018][    T1] pci 0000:00:03.3: calling  quirk_cmd_compl+0x0/0x80 @ 1
[   20.361817][    T1] pci 0000:00:03.3: quirk_cmd_compl+0x0/0x80 took 0 usecs
[   20.368821][    T1] pci 0000:00:03.3: calling  quirk_no_aersid+0x0/0x40 @ 1
[   20.376824][    T1] pci 0000:00:03.3: quirk_no_aersid+0x0/0x40 took 0 usecs
[   20.384817][    T1] pci 0000:00:03.3: [8086:2f0b] type 01 class 0x060400
[   20.392866][    T1] pci 0000:00:03.3: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   20.401848][    T1] pci 0000:00:03.3: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   20.410846][    T1] pci 0000:00:03.3: calling  pci_fixup_transparent_bridge+0x0/0x40 @ 1
[   20.419847][    T1] pci 0000:00:03.3: pci_fixup_transparent_bridge+0x0/0x40 took 0 usecs
[   20.428864][    T1] pci 0000:00:03.3: PME# supported from D0 D3hot D3cold
[   20.436991][    T1] pci 0000:00:05.0: [8086:2f28] type 00 class 0x088000
[   20.443869][    T1] pci 0000:00:05.0: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   20.452846][    T1] pci 0000:00:05.0: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   20.462811][    T1] pci 0000:00:05.1: [8086:2f29] type 00 class 0x088000
[   20.469869][    T1] pci 0000:00:05.1: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   20.478847][    T1] pci 0000:00:05.1: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   20.487972][    T1] pci 0000:00:05.2: [8086:2f2a] type 00 class 0x088000
[   20.495868][    T1] pci 0000:00:05.2: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   20.504846][    T1] pci 0000:00:05.2: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   20.513898][    T1] pci 0000:00:05.4: [8086:2f2c] type 00 class 0x080020
[   20.520834][    T1] pci 0000:00:05.4: reg 0x10: [mem 0x93406000-0x93406fff]
[   20.528878][    T1] pci 0000:00:05.4: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   20.537848][    T1] pci 0000:00:05.4: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   20.546856][    T1] pci 0000:00:11.0: calling  quirk_cmd_compl+0x0/0x80 @ 1
[   20.554818][    T1] pci 0000:00:11.0: quirk_cmd_compl+0x0/0x80 took 0 usecs
[   20.562816][    T1] pci 0000:00:11.0: calling  quirk_no_aersid+0x0/0x40 @ 1
[   20.570818][    T1] pci 0000:00:11.0: quirk_no_aersid+0x0/0x40 took 0 usecs
[   20.578817][    T1] pci 0000:00:11.0: [8086:1d3e] type 01 class 0x060400
[   20.586703][    T1] pci 0000:00:11.0: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   20.594848][    T1] pci 0000:00:11.0: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   20.603848][    T1] pci 0000:00:11.0: calling  pci_fixup_transparent_bridge+0x0/0x40 @ 1
[   20.612847][    T1] pci 0000:00:11.0: pci_fixup_transparent_bridge+0x0/0x40 took 0 usecs
[   20.622898][    T1] pci 0000:00:11.0: PME# supported from D0 D3hot D3cold
[   20.630006][    T1] pci 0000:00:1a.0: [8086:1d2d] type 00 class 0x0c0320
[   20.637847][    T1] pci 0000:00:1a.0: reg 0x10: [mem 0x93402000-0x934023ff]
[   20.645901][    T1] pci 0000:00:1a.0: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   20.654853][    T1] pci 0000:00:1a.0: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   20.663885][    T1] pci 0000:00:1a.0: PME# supported from D0 D3hot D3cold
[   20.671824][    T1] pci 0000:00:1c.0: calling  quirk_cmd_compl+0x0/0x80 @ 1
[   20.679820][    T1] pci 0000:00:1c.0: quirk_cmd_compl+0x0/0x80 took 0 usecs
[   20.687817][    T1] pci 0000:00:1c.0: calling  quirk_no_aersid+0x0/0x40 @ 1
[   20.694816][    T1] pci 0000:00:1c.0: quirk_no_aersid+0x0/0x40 took 0 usecs
[   20.702817][    T1] pci 0000:00:1c.0: [8086:1d10] type 01 class 0x060400
[   20.710906][    T1] pci 0000:00:1c.0: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   20.719847][    T1] pci 0000:00:1c.0: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   20.728846][    T1] pci 0000:00:1c.0: calling  pci_fixup_transparent_bridge+0x0/0x40 @ 1
[   20.737847][    T1] pci 0000:00:1c.0: pci_fixup_transparent_bridge+0x0/0x40 took 0 usecs
[   20.746913][    T1] pci 0000:00:1c.0: PME# supported from D0 D3hot D3cold
[   20.754973][    T1] pci 0000:00:1c.7: calling  quirk_cmd_compl+0x0/0x80 @ 1
[   20.762818][    T1] pci 0000:00:1c.7: quirk_cmd_compl+0x0/0x80 took 0 usecs
[   20.770816][    T1] pci 0000:00:1c.7: calling  quirk_no_aersid+0x0/0x40 @ 1
[   20.778818][    T1] pci 0000:00:1c.7: quirk_no_aersid+0x0/0x40 took 0 usecs
[   20.786816][    T1] pci 0000:00:1c.7: [8086:1d1e] type 01 class 0x060400
[   20.793889][    T1] pci 0000:00:1c.7: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   20.802848][    T1] pci 0000:00:1c.7: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   20.811846][    T1] pci 0000:00:1c.7: calling  pci_fixup_transparent_bridge+0x0/0x40 @ 1
[   20.820846][    T1] pci 0000:00:1c.7: pci_fixup_transparent_bridge+0x0/0x40 took 0 usecs
[   20.829885][    T1] pci 0000:00:1c.7: PME# supported from D0 D3hot D3cold
[   20.837822][    T1] pci 0000:00:1d.0: [8086:1d26] type 00 class 0x0c0320
[   20.845843][    T1] pci 0000:00:1d.0: reg 0x10: [mem 0x93401000-0x934013ff]
[   20.853898][    T1] pci 0000:00:1d.0: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   20.862847][    T1] pci 0000:00:1d.0: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   20.871878][    T1] pci 0000:00:1d.0: PME# supported from D0 D3hot D3cold
[   20.878938][    T1] pci 0000:00:1e.0: calling  quirk_cmd_compl+0x0/0x80 @ 1
[   20.886817][    T1] pci 0000:00:1e.0: quirk_cmd_compl+0x0/0x80 took 0 usecs
[   20.894816][    T1] pci 0000:00:1e.0: calling  quirk_no_aersid+0x0/0x40 @ 1
[   20.902816][    T1] pci 0000:00:1e.0: quirk_no_aersid+0x0/0x40 took 0 usecs
[   20.910816][    T1] pci 0000:00:1e.0: [8086:244e] type 01 class 0x060401
[   20.918879][    T1] pci 0000:00:1e.0: calling  quirk_use_pcie_bridge_dma_alias+0x0/0x80 @ 1
[   20.927850][    T1] pci 0000:00:1e.0: quirk_use_pcie_bridge_dma_alias+0x0/0x80 took 0 usecs
[   20.936854][    T1] pci 0000:00:1e.0: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   20.945852][    T1] pci 0000:00:1e.0: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   20.954849][    T1] pci 0000:00:1e.0: calling  pci_fixup_transparent_bridge+0x0/0x40 @ 1
[   20.964849][    T1] pci 0000:00:1e.0: pci_fixup_transparent_bridge+0x0/0x40 took 0 usecs
[   20.973869][    T1] pci 0000:00:1f.0: [8086:1d41] type 00 class 0x060100
[   20.980952][    T1] pci 0000:00:1f.0: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   20.990847][    T1] pci 0000:00:1f.0: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   21.000023][    T1] pci 0000:00:1f.2: [8086:1d02] type 00 class 0x010601
[   21.006840][    T1] pci 0000:00:1f.2: reg 0x10: [io  0x2058-0x205f]
[   21.013826][    T1] pci 0000:00:1f.2: reg 0x14: [io  0x207c-0x207f]
[   21.021828][    T1] pci 0000:00:1f.2: reg 0x18: [io  0x2050-0x2057]
[   21.028828][    T1] pci 0000:00:1f.2: reg 0x1c: [io  0x2078-0x207b]
[   21.035827][    T1] pci 0000:00:1f.2: reg 0x20: [io  0x2020-0x203f]
[   21.042829][    T1] pci 0000:00:1f.2: reg 0x24: [mem 0x93400000-0x934007ff]
[   21.050834][    T1] pci 0000:00:1f.2: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   21.059850][    T1] pci 0000:00:1f.2: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   21.068884][    T1] pci 0000:00:1f.2: PME# supported from D3hot
[   21.084815][    T1] pci 0000:00:1f.3: [8086:1d22] type 00 class 0x0c0500
[   21.091849][    T1] pci 0000:00:1f.3: reg 0x10: [mem 0x381ffff00000-0x381ffff000ff 64bit]
[   21.101883][    T1] pci 0000:00:1f.3: reg 0x20: [io  0x2000-0x201f]
[   21.108845][    T1] pci 0000:00:1f.3: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   21.117851][    T1] pci 0000:00:1f.3: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   21.126990][    T1] acpiphp: Slot [8] registered
[   21.131851][    T1] pci 0000:01:00.0: [1000:0087] type 00 class 0x010700
[   21.139833][    T1] pci 0000:01:00.0: reg 0x10: [io  0x1000-0x10ff]
[   21.146828][    T1] pci 0000:01:00.0: reg 0x14: [mem 0x93340000-0x9334ffff 64bit]
[   21.154858][    T1] pci 0000:01:00.0: reg 0x1c: [mem 0x93300000-0x9333ffff 64bit]
[   21.163864][    T1] pci 0000:01:00.0: reg 0x30: [mem 0xfff00000-0xffffffff pref]
[   21.171857][    T1] pci 0000:01:00.0: supports D1 D2
[   21.177947][    T1] pci 0000:00:02.0: PCI bridge to [bus 01]
[   21.184814][    T1] pci 0000:00:02.0:   bridge window [io  0x1000-0x1fff]
[   21.191817][    T1] pci 0000:00:02.0:   bridge window [mem 0x93300000-0x933fffff]
[   21.201005][    T1] acpiphp: Slot [2] registered
[   21.205837][    T1] pci 0000:00:03.0: PCI bridge to [bus 02]
[   21.212831][    T1] acpiphp: Slot [1] registered
[   21.217864][    T1] pci 0000:03:00.0: calling  quirk_f0_vpd_link+0x0/0x80 @ 1
[   21.225818][    T1] pci 0000:03:00.0: quirk_f0_vpd_link+0x0/0x80 took 0 usecs
[   21.233819][    T1] pci 0000:03:00.0: [8086:1528] type 00 class 0x020000
[   21.241855][    T1] pci 0000:03:00.0: reg 0x10: [mem 0x92c00000-0x92dfffff 64bit pref]
[   21.250895][    T1] pci 0000:03:00.0: reg 0x20: [mem 0x92e04000-0x92e07fff 64bit pref]
[   21.259865][    T1] pci 0000:03:00.0: reg 0x30: [mem 0xfff80000-0xffffffff pref]
[   21.267861][    T1] pci 0000:03:00.0: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   21.276847][    T1] pci 0000:03:00.0: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   21.285872][    T1] pci 0000:03:00.0: PME# supported from D0 D3hot
[   21.292850][    T1] pci 0000:03:00.0: reg 0x184: [mem 0x93100000-0x93103fff 64bit]
[   21.301844][    T1] pci 0000:03:00.0: VF(n) BAR0 space: [mem 0x93100000-0x931fffff 64bit] (contains BAR0 for 64 VFs)
[   21.313879][    T1] pci 0000:03:00.0: reg 0x190: [mem 0x93200000-0x93203fff 64bit]
[   21.321845][    T1] pci 0000:03:00.0: VF(n) BAR3 space: [mem 0x93200000-0x932fffff 64bit] (contains BAR3 for 64 VFs)
[   21.334008][    T1] pci 0000:03:00.0: 16.000 Gb/s available PCIe bandwidth, limited by 5.0 GT/s PCIe x4 link at 0000:00:03.2 (capable of 32.000 Gb/s with 5.0 GT/s PCIe x8 link)
[   21.352051][    T1] pci 0000:03:00.1: calling  quirk_f0_vpd_link+0x0/0x80 @ 1
[   21.359825][    T1] pci 0000:03:00.1: quirk_f0_vpd_link+0x0/0x80 took 0 usecs
[   21.367819][    T1] pci 0000:03:00.1: [8086:1528] type 00 class 0x020000
[   21.375849][    T1] pci 0000:03:00.1: reg 0x10: [mem 0x92a00000-0x92bfffff 64bit pref]
[   21.384890][    T1] pci 0000:03:00.1: reg 0x20: [mem 0x92e00000-0x92e03fff 64bit pref]
[   21.393867][    T1] pci 0000:03:00.1: reg 0x30: [mem 0xfff80000-0xffffffff pref]
[   21.401924][    T1] pci 0000:03:00.1: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   21.410848][    T1] pci 0000:03:00.1: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   21.419877][    T1] pci 0000:03:00.1: PME# supported from D0 D3hot
[   21.426845][    T1] pci 0000:03:00.1: reg 0x184: [mem 0x92f00000-0x92f03fff 64bit]
[   21.435844][    T1] pci 0000:03:00.1: VF(n) BAR0 space: [mem 0x92f00000-0x92ffffff 64bit] (contains BAR0 for 64 VFs)
[   21.447881][    T1] pci 0000:03:00.1: reg 0x190: [mem 0x93000000-0x93003fff 64bit]
[   21.455848][    T1] pci 0000:03:00.1: VF(n) BAR3 space: [mem 0x93000000-0x930fffff 64bit] (contains BAR3 for 64 VFs)
[   21.468838][    T1] pci 0000:00:03.2: PCI bridge to [bus 03-04]
[   21.474817][    T1] pci 0000:00:03.2:   bridge window [mem 0x92f00000-0x932fffff]
[   21.483846][    T1] pci 0000:00:03.2:   bridge window [mem 0x92a00000-0x92efffff 64bit pref]
[   21.493036][    T1] acpiphp: Slot [0] registered
[   21.498843][    T1] pci 0000:00:03.3: PCI bridge to [bus 05]
[   21.504883][    T1] pci 0000:00:11.0: PCI bridge to [bus 06]
[   21.511890][    T1] pci 0000:00:1c.0: PCI bridge to [bus 07]
[   21.517910][    T1] pci 0000:08:00.0: [102b:0522] type 00 class 0x030000
[   21.525856][    T1] pci 0000:08:00.0: reg 0x10: [mem 0x91000000-0x91ffffff pref]
[   21.533869][    T1] pci 0000:08:00.0: reg 0x14: [mem 0x92800000-0x92803fff]
[   21.541838][    T1] pci 0000:08:00.0: reg 0x18: [mem 0x92000000-0x927fffff]
[   21.549900][    T1] pci 0000:08:00.0: reg 0x30: [mem 0xffff0000-0xffffffff pref]
[   21.558706][    T1] pci 0000:08:00.0: calling  efifb_fixup_resources+0x0/0x100 @ 1
[   21.566848][    T1] pci 0000:08:00.0: efifb_fixup_resources+0x0/0x100 took 0 usecs
[   21.575844][    T1] pci 0000:08:00.0: calling  pci_fixup_video+0x0/0x100 @ 1
[   21.583826][    T1] pci 0000:08:00.0: Video device with shadowed ROM at [mem 0x000c0000-0x000dffff]
[   21.593856][    T1] pci 0000:08:00.0: pci_fixup_video+0x0/0x100 took 9765 usecs
[   21.601888][    T1] pci 0000:00:1c.7: PCI bridge to [bus 08]
[   21.608817][    T1] pci 0000:00:1c.7:   bridge window [mem 0x92000000-0x928fffff]
[   21.616850][    T1] pci 0000:00:1c.7:   bridge window [mem 0x91000000-0x91ffffff 64bit pref]
[   21.626872][    T1] pci_bus 0000:09: extended config space not accessible
[   21.634713][    T1] pci 0000:00:1e.0: PCI bridge to [bus 09] (subtractive decode)
[   21.642855][    T1] pci 0000:00:1e.0:   bridge window [io  0x0000-0x0cf7 window] (subtractive decode)
[   21.652851][    T1] pci 0000:00:1e.0:   bridge window [io  0x1000-0x3fff window] (subtractive decode)
[   21.663854][    T1] pci 0000:00:1e.0:   bridge window [mem 0x000a0000-0x000bffff window] (subtractive decode)
[   21.674854][    T1] pci 0000:00:1e.0:   bridge window [mem 0xfed40000-0xfedfffff window] (subtractive decode)
[   21.685858][    T1] pci 0000:00:1e.0:   bridge window [mem 0x90000000-0xabffbfff window] (subtractive decode)
[   21.696855][    T1] pci 0000:00:1e.0:   bridge window [mem 0x380000000000-0x381fffffffff window] (subtractive decode)
[   21.709079][    T1] ACPI: PCI: Interrupt link LNKA configured for IRQ 0
[   21.716818][    T1] ACPI: PCI: Interrupt link LNKA disabled
[   21.723863][    T1] ACPI: PCI: Interrupt link LNKB configured for IRQ 0
[   21.730816][    T1] ACPI: PCI: Interrupt link LNKB disabled
[   21.736867][    T1] ACPI: PCI: Interrupt link LNKC configured for IRQ 0
[   21.744817][    T1] ACPI: PCI: Interrupt link LNKC disabled
[   21.750819][    T1] ACPI: PCI: Interrupt link LNKD configured for IRQ 0
[   21.758817][    T1] ACPI: PCI: Interrupt link LNKD disabled
[   21.764856][    T1] ACPI: PCI: Interrupt link LNKE configured for IRQ 0
[   21.772816][    T1] ACPI: PCI: Interrupt link LNKE disabled
[   21.778855][    T1] ACPI: PCI: Interrupt link LNKF configured for IRQ 0
[   21.785819][    T1] ACPI: PCI: Interrupt link LNKF disabled
[   21.792820][    T1] ACPI: PCI: Interrupt link LNKG configured for IRQ 0
[   21.799818][    T1] ACPI: PCI: Interrupt link LNKG disabled
[   21.806861][    T1] ACPI: PCI: Interrupt link LNKH configured for IRQ 0
[   21.813816][    T1] ACPI: PCI: Interrupt link LNKH disabled
[   21.821168][    T1] ACPI: PCI Root Bridge [IIO1] (domain 0000 [bus 40-7e])
[   21.828820][    T1] acpi PNP0A08:01: _OSC: OS supports [ExtendedConfig ASPM ClockPM Segments MSI HPX-Type3]
[   21.840378][    T1] acpi PNP0A08:01: _OSC: platform does not support [SHPCHotplug LTR]
[   21.849536][    T1] acpi PNP0A08:01: _OSC: OS now controls [PCIeHotplug PME AER PCIeCapability]
[   21.859851][    T1] acpi PNP0A08:01: FADT indicates ASPM is unsupported, using BIOS configuration
[   21.870042][    T1] PCI host bridge to bus 0000:40
[   21.874818][    T1] pci_bus 0000:40: Unknown NUMA node; performance will be reduced
[   21.883845][    T1] pci_bus 0000:40: root bus resource [mem 0x000a0000-0x000bffff window]
[   21.892846][    T1] pci_bus 0000:40: root bus resource [io  0x4000-0x7fff window]
[   21.901847][    T1] pci_bus 0000:40: root bus resource [io  0x03b0-0x03bb window]
[   21.909846][    T1] pci_bus 0000:40: root bus resource [io  0x03c0-0x03df window]
[   21.918846][    T1] pci_bus 0000:40: root bus resource [mem 0xac000000-0xc7ffbfff window]
[   21.927847][    T1] pci_bus 0000:40: root bus resource [mem 0x382000000000-0x383fffffffff window]
[   21.937856][    T1] pci_bus 0000:40: root bus resource [bus 40-7e]
[   21.944881][    T1] pci 0000:40:02.0: calling  quirk_cmd_compl+0x0/0x80 @ 1
[   21.952817][    T1] pci 0000:40:02.0: quirk_cmd_compl+0x0/0x80 took 0 usecs
[   21.960816][    T1] pci 0000:40:02.0: calling  quirk_no_aersid+0x0/0x40 @ 1
[   21.968817][    T1] pci 0000:40:02.0: quirk_no_aersid+0x0/0x40 took 0 usecs
[   21.976821][    T1] pci 0000:40:02.0: [8086:2f04] type 01 class 0x060400
[   21.983863][    T1] pci 0000:40:02.0: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   21.992847][    T1] pci 0000:40:02.0: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   22.001846][    T1] pci 0000:40:02.0: calling  pci_fixup_transparent_bridge+0x0/0x40 @ 1
[   22.010848][    T1] pci 0000:40:02.0: pci_fixup_transparent_bridge+0x0/0x40 took 0 usecs
[   22.019878][    T1] pci 0000:40:02.0: PME# supported from D0 D3hot D3cold
[   22.027844][    T1] pci 0000:40:02.2: calling  quirk_cmd_compl+0x0/0x80 @ 1
[   22.035818][    T1] pci 0000:40:02.2: quirk_cmd_compl+0x0/0x80 took 0 usecs
[   22.043817][    T1] pci 0000:40:02.2: calling  quirk_no_aersid+0x0/0x40 @ 1
[   22.051816][    T1] pci 0000:40:02.2: quirk_no_aersid+0x0/0x40 took 0 usecs
[   22.059818][    T1] pci 0000:40:02.2: [8086:2f06] type 01 class 0x060400
[   22.067702][    T1] pci 0000:40:02.2: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   22.075847][    T1] pci 0000:40:02.2: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   22.094698][    T1] pci 0000:40:02.2: calling  pci_fixup_transparent_bridge+0x0/0x40 @ 1
[   22.103846][    T1] pci 0000:40:02.2: pci_fixup_transparent_bridge+0x0/0x40 took 0 usecs
[   22.112877][    T1] pci 0000:40:02.2: PME# supported from D0 D3hot D3cold
[   22.120954][    T1] pci 0000:40:03.0: calling  quirk_cmd_compl+0x0/0x80 @ 1
[   22.128817][    T1] pci 0000:40:03.0: quirk_cmd_compl+0x0/0x80 took 0 usecs
[   22.136819][    T1] pci 0000:40:03.0: calling  quirk_no_aersid+0x0/0x40 @ 1
[   22.143819][    T1] pci 0000:40:03.0: quirk_no_aersid+0x0/0x40 took 0 usecs
[   22.151816][    T1] pci 0000:40:03.0: [8086:2f08] type 01 class 0x060400
[   22.159863][    T1] pci 0000:40:03.0: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   22.168853][    T1] pci 0000:40:03.0: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   22.177846][    T1] pci 0000:40:03.0: calling  pci_fixup_transparent_bridge+0x0/0x40 @ 1
[   22.186848][    T1] pci 0000:40:03.0: pci_fixup_transparent_bridge+0x0/0x40 took 0 usecs
[   22.195874][    T1] pci 0000:40:03.0: PME# supported from D0 D3hot D3cold
[   22.203841][    T1] pci 0000:40:05.0: [8086:2f28] type 00 class 0x088000
[   22.211866][    T1] pci 0000:40:05.0: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   22.220847][    T1] pci 0000:40:05.0: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   22.229854][    T1] pci 0000:40:05.1: [8086:2f29] type 00 class 0x088000
[   22.236878][    T1] pci 0000:40:05.1: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   22.245847][    T1] pci 0000:40:05.1: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   22.254939][    T1] pci 0000:40:05.2: [8086:2f2a] type 00 class 0x088000
[   22.262872][    T1] pci 0000:40:05.2: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   22.271846][    T1] pci 0000:40:05.2: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   22.280909][    T1] pci 0000:40:05.4: [8086:2f2c] type 00 class 0x080020
[   22.288838][    T1] pci 0000:40:05.4: reg 0x10: [mem 0xac000000-0xac000fff]
[   22.296878][    T1] pci 0000:40:05.4: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   22.305848][    T1] pci 0000:40:05.4: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   22.315022][    T1] pci 0000:40:02.0: PCI bridge to [bus 41]
[   22.320817][    T1] pci 0000:40:02.0:   bridge window [io  0x4000-0x4fff]
[   22.328817][    T1] pci 0000:40:02.0:   bridge window [mem 0xac100000-0xac2fffff]
[   22.336848][    T1] pci 0000:40:02.0:   bridge window [mem 0x382000000000-0x3820001fffff 64bit pref]
[   22.348004][    T1] pci 0000:40:02.2: PCI bridge to [bus 42]
[   22.353816][    T1] pci 0000:40:02.2:   bridge window [io  0x5000-0x5fff]
[   22.361818][    T1] pci 0000:40:02.2:   bridge window [mem 0xac300000-0xac4fffff]
[   22.370850][    T1] pci 0000:40:02.2:   bridge window [mem 0x382000200000-0x3820003fffff 64bit pref]
[   22.380907][    T1] acpiphp: Slot [6] registered
[   22.385836][    T1] pci 0000:40:03.0: PCI bridge to [bus 43]
[   22.393127][    T1] ACPI: PCI Root Bridge [IIO2] (domain 0000 [bus 80-be])
[   22.400823][    T1] acpi PNP0A08:02: _OSC: OS supports [ExtendedConfig ASPM ClockPM Segments MSI HPX-Type3]
[   22.412332][    T1] acpi PNP0A08:02: _OSC: platform does not support [SHPCHotplug LTR]
[   22.421541][    T1] acpi PNP0A08:02: _OSC: OS now controls [PCIeHotplug PME AER PCIeCapability]
[   22.431850][    T1] acpi PNP0A08:02: FADT indicates ASPM is unsupported, using BIOS configuration
[   22.441877][    T1] acpi PNP0A08:02: ignoring host bridge window [io  0x4558-0xffff window] (conflicts with PCI Bus 0000:40 [io  0x4000-0x7fff window])
[   22.457028][    T1] PCI host bridge to bus 0000:80
[   22.462815][    T1] pci_bus 0000:80: Unknown NUMA node; performance will be reduced
[   22.471850][    T1] pci_bus 0000:80: root bus resource [mem 0x000a0000-0x000bffff window]
[   22.480856][    T1] pci_bus 0000:80: root bus resource [io  0x03b0-0x03bb window]
[   22.488847][    T1] pci_bus 0000:80: root bus resource [io  0x03c0-0x03df window]
[   22.497845][    T1] pci_bus 0000:80: root bus resource [mem 0xc8000000-0xe3ffbfff window]
[   22.506847][    T1] pci_bus 0000:80: root bus resource [mem 0x384000000000-0x385fffffffff window]
[   22.516857][    T1] pci_bus 0000:80: root bus resource [bus 80-be]
[   22.523815][    T1] pci 0000:80:02.0: calling  quirk_cmd_compl+0x0/0x80 @ 1
[   22.531818][    T1] pci 0000:80:02.0: quirk_cmd_compl+0x0/0x80 took 0 usecs
[   22.539816][    T1] pci 0000:80:02.0: calling  quirk_no_aersid+0x0/0x40 @ 1
[   22.547818][    T1] pci 0000:80:02.0: quirk_no_aersid+0x0/0x40 took 0 usecs
[   22.555818][    T1] pci 0000:80:02.0: [8086:2f04] type 01 class 0x060400
[   22.562862][    T1] pci 0000:80:02.0: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   22.571849][    T1] pci 0000:80:02.0: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   22.580847][    T1] pci 0000:80:02.0: calling  pci_fixup_transparent_bridge+0x0/0x40 @ 1
[   22.589847][    T1] pci 0000:80:02.0: pci_fixup_transparent_bridge+0x0/0x40 took 0 usecs
[   22.598882][    T1] pci 0000:80:02.0: PME# supported from D0 D3hot D3cold
[   22.607026][    T1] pci 0000:80:02.2: calling  quirk_cmd_compl+0x0/0x80 @ 1
[   22.614822][    T1] pci 0000:80:02.2: quirk_cmd_compl+0x0/0x80 took 0 usecs
[   22.622817][    T1] pci 0000:80:02.2: calling  quirk_no_aersid+0x0/0x40 @ 1
[   22.630819][    T1] pci 0000:80:02.2: quirk_no_aersid+0x0/0x40 took 0 usecs
[   22.638818][    T1] pci 0000:80:02.2: [8086:2f06] type 01 class 0x060400
[   22.646704][    T1] pci 0000:80:02.2: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   22.654854][    T1] pci 0000:80:02.2: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   22.663847][    T1] pci 0000:80:02.2: calling  pci_fixup_transparent_bridge+0x0/0x40 @ 1
[   22.672849][    T1] pci 0000:80:02.2: pci_fixup_transparent_bridge+0x0/0x40 took 0 usecs
[   22.682877][    T1] pci 0000:80:02.2: PME# supported from D0 D3hot D3cold
[   22.689844][    T1] pci 0000:80:03.0: calling  quirk_cmd_compl+0x0/0x80 @ 1
[   22.697820][    T1] pci 0000:80:03.0: quirk_cmd_compl+0x0/0x80 took 0 usecs
[   22.705818][    T1] pci 0000:80:03.0: calling  quirk_no_aersid+0x0/0x40 @ 1
[   22.713817][    T1] pci 0000:80:03.0: quirk_no_aersid+0x0/0x40 took 0 usecs
[   22.721819][    T1] pci 0000:80:03.0: [8086:2f08] type 01 class 0x060400
[   22.729703][    T1] pci 0000:80:03.0: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   22.737848][    T1] pci 0000:80:03.0: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   22.746849][    T1] pci 0000:80:03.0: calling  pci_fixup_transparent_bridge+0x0/0x40 @ 1
[   22.756850][    T1] pci 0000:80:03.0: pci_fixup_transparent_bridge+0x0/0x40 took 0 usecs
[   22.765860][    T1] pci 0000:80:03.0: PME# supported from D0 D3hot D3cold
[   22.772996][    T1] pci 0000:80:05.0: [8086:2f28] type 00 class 0x088000
[   22.780870][    T1] pci 0000:80:05.0: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   22.789846][    T1] pci 0000:80:05.0: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   22.798942][    T1] pci 0000:80:05.1: [8086:2f29] type 00 class 0x088000
[   22.806867][    T1] pci 0000:80:05.1: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   22.815847][    T1] pci 0000:80:05.1: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   22.824946][    T1] pci 0000:80:05.2: [8086:2f2a] type 00 class 0x088000
[   22.832868][    T1] pci 0000:80:05.2: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   22.841847][    T1] pci 0000:80:05.2: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   22.850763][    T1] pci 0000:80:05.4: [8086:2f2c] type 00 class 0x080020
[   22.857838][    T1] pci 0000:80:05.4: reg 0x10: [mem 0xc8000000-0xc8000fff]
[   22.865878][    T1] pci 0000:80:05.4: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   22.874846][    T1] pci 0000:80:05.4: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   22.884159][    T1] acpiphp: Slot [4] registered
[   22.889815][    T1] pci 0000:80:02.0: PCI bridge to [bus 81]
[   22.896038][    T1] acpiphp: Slot [3] registered
[   22.901826][    T1] pci 0000:80:02.2: PCI bridge to [bus 82]
[   22.907959][    T1] acpiphp: Slot [9] registered
[   22.912828][    T1] pci 0000:80:03.0: PCI bridge to [bus 83]
[   22.920118][    T1] ACPI: PCI Root Bridge [IIO3] (domain 0000 [bus c0-fe])
[   22.927820][    T1] acpi PNP0A08:03: _OSC: OS supports [ExtendedConfig ASPM ClockPM Segments MSI HPX-Type3]
[   22.939345][    T1] acpi PNP0A08:03: _OSC: platform does not support [SHPCHotplug LTR]
[   22.948543][    T1] acpi PNP0A08:03: _OSC: OS now controls [PCIeHotplug PME AER PCIeCapability]
[   22.958851][    T1] acpi PNP0A08:03: FADT indicates ASPM is unsupported, using BIOS configuration
[   22.969048][    T1] PCI host bridge to bus 0000:c0
[   22.974812][    T1] pci_bus 0000:c0: Unknown NUMA node; performance will be reduced
[   22.982845][    T1] pci_bus 0000:c0: root bus resource [mem 0x000a0000-0x000bffff window]
[   22.991847][    T1] pci_bus 0000:c0: root bus resource [io  0xc000-0xffff window]
[   23.000846][    T1] pci_bus 0000:c0: root bus resource [io  0x03b0-0x03bb window]
[   23.009705][    T1] pci_bus 0000:c0: root bus resource [io  0x03c0-0x03df window]
[   23.017846][    T1] pci_bus 0000:c0: root bus resource [mem 0xe4000000-0xfbffbfff window]
[   23.026847][    T1] pci_bus 0000:c0: root bus resource [mem 0x386000000000-0x387fffffffff window]
[   23.036851][    T1] pci_bus 0000:c0: root bus resource [bus c0-fe]
[   23.043858][    T1] pci 0000:c0:02.0: calling  quirk_cmd_compl+0x0/0x80 @ 1
[   23.051817][    T1] pci 0000:c0:02.0: quirk_cmd_compl+0x0/0x80 took 0 usecs
[   23.059816][    T1] pci 0000:c0:02.0: calling  quirk_no_aersid+0x0/0x40 @ 1
[   23.067817][    T1] pci 0000:c0:02.0: quirk_no_aersid+0x0/0x40 took 0 usecs
[   23.075818][    T1] pci 0000:c0:02.0: [8086:2f04] type 01 class 0x060400
[   23.082862][    T1] pci 0000:c0:02.0: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   23.101698][    T1] pci 0000:c0:02.0: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   23.109846][    T1] pci 0000:c0:02.0: calling  pci_fixup_transparent_bridge+0x0/0x40 @ 1
[   23.119847][    T1] pci 0000:c0:02.0: pci_fixup_transparent_bridge+0x0/0x40 took 0 usecs
[   23.128856][    T1] pci 0000:c0:02.0: PME# supported from D0 D3hot D3cold
[   23.135960][    T1] pci 0000:c0:02.2: calling  quirk_cmd_compl+0x0/0x80 @ 1
[   23.143818][    T1] pci 0000:c0:02.2: quirk_cmd_compl+0x0/0x80 took 0 usecs
[   23.151816][    T1] pci 0000:c0:02.2: calling  quirk_no_aersid+0x0/0x40 @ 1
[   23.159820][    T1] pci 0000:c0:02.2: quirk_no_aersid+0x0/0x40 took 0 usecs
[   23.167819][    T1] pci 0000:c0:02.2: [8086:2f06] type 01 class 0x060400
[   23.175866][    T1] pci 0000:c0:02.2: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   23.184848][    T1] pci 0000:c0:02.2: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   23.193846][    T1] pci 0000:c0:02.2: calling  pci_fixup_transparent_bridge+0x0/0x40 @ 1
[   23.202847][    T1] pci 0000:c0:02.2: pci_fixup_transparent_bridge+0x0/0x40 took 0 usecs
[   23.211874][    T1] pci 0000:c0:02.2: PME# supported from D0 D3hot D3cold
[   23.219973][    T1] pci 0000:c0:03.0: calling  quirk_cmd_compl+0x0/0x80 @ 1
[   23.227820][    T1] pci 0000:c0:03.0: quirk_cmd_compl+0x0/0x80 took 0 usecs
[   23.234818][    T1] pci 0000:c0:03.0: calling  quirk_no_aersid+0x0/0x40 @ 1
[   23.242820][    T1] pci 0000:c0:03.0: quirk_no_aersid+0x0/0x40 took 0 usecs
[   23.250816][    T1] pci 0000:c0:03.0: [8086:2f08] type 01 class 0x060400
[   23.258864][    T1] pci 0000:c0:03.0: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   23.267848][    T1] pci 0000:c0:03.0: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   23.276846][    T1] pci 0000:c0:03.0: calling  pci_fixup_transparent_bridge+0x0/0x40 @ 1
[   23.285848][    T1] pci 0000:c0:03.0: pci_fixup_transparent_bridge+0x0/0x40 took 0 usecs
[   23.294878][    T1] pci 0000:c0:03.0: PME# supported from D0 D3hot D3cold
[   23.302821][    T1] pci 0000:c0:05.0: [8086:2f28] type 00 class 0x088000
[   23.309867][    T1] pci 0000:c0:05.0: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   23.318848][    T1] pci 0000:c0:05.0: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   23.327927][    T1] pci 0000:c0:05.1: [8086:2f29] type 00 class 0x088000
[   23.335868][    T1] pci 0000:c0:05.1: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   23.344846][    T1] pci 0000:c0:05.1: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   23.353855][    T1] pci 0000:c0:05.2: [8086:2f2a] type 00 class 0x088000
[   23.361869][    T1] pci 0000:c0:05.2: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   23.370851][    T1] pci 0000:c0:05.2: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   23.379927][    T1] pci 0000:c0:05.4: [8086:2f2c] type 00 class 0x080020
[   23.386832][    T1] pci 0000:c0:05.4: reg 0x10: [mem 0xe4000000-0xe4000fff]
[   23.394876][    T1] pci 0000:c0:05.4: calling  quirk_igfx_skip_te_disable+0x0/0x80 @ 1
[   23.403848][    T1] pci 0000:c0:05.4: quirk_igfx_skip_te_disable+0x0/0x80 took 0 usecs
[   23.413114][    T1] pci 0000:c0:02.0: PCI bridge to [bus c1]
[   23.419814][    T1] pci 0000:c0:02.0:   bridge window [io  0xc000-0xcfff]
[   23.427820][    T1] pci 0000:c0:02.0:   bridge window [mem 0xe4100000-0xe42fffff]
[   23.435846][    T1] pci 0000:c0:02.0:   bridge window [mem 0x386000000000-0x3860001fffff 64bit pref]
[   23.446826][    T1] pci 0000:c0:02.2: PCI bridge to [bus c2]
[   23.452814][    T1] pci 0000:c0:02.2:   bridge window [io  0xd000-0xdfff]
[   23.460819][    T1] pci 0000:c0:02.2:   bridge window [mem 0xe4300000-0xe44fffff]
[   23.468846][    T1] pci 0000:c0:02.2:   bridge window [mem 0x386000200000-0x3860003fffff 64bit pref]
[   23.478986][    T1] acpiphp: Slot [11] registered
[   23.484827][    T1] pci 0000:c0:03.0: PCI bridge to [bus c3]
[   23.492224][    T1] initcall acpi_init+0x0/0x131 returned 0 after 13883000 usecs
[   23.499847][    T1] calling  adxl_init+0x0/0x190 @ 1
[   23.505816][    T1] initcall adxl_init+0x0/0x190 returned -19 after 0 usecs
[   23.513817][    T1] calling  pnp_init+0x0/0x11 @ 1
[   23.518829][    T1] initcall pnp_init+0x0/0x11 returned 0 after 0 usecs
[   23.526816][    T1] calling  misc_init+0x0/0xc9 @ 1
[   23.531848][    T1] initcall misc_init+0x0/0xc9 returned 0 after 0 usecs
[   23.539816][    T1] calling  tpm_init+0x0/0xf5 @ 1
[   23.545735][    T1] initcall tpm_init+0x0/0xf5 returned 0 after 0 usecs
[   23.552817][    T1] calling  iommu_subsys_init+0x0/0x11a @ 1
[   23.558812][    T1] iommu: Default domain type: Translated 
[   23.565813][    T1] iommu: DMA domain TLB invalidation policy: lazy mode 
[   23.573698][    T1] initcall iommu_subsys_init+0x0/0x11a returned 0 after 14000 usecs
[   23.581847][    T1] calling  cn_init+0x0/0x100 @ 1
[   23.587864][    T1] initcall cn_init+0x0/0x100 returned 0 after 0 usecs
[   23.594816][    T1] calling  dax_core_init+0x0/0xc8 @ 1
[   23.601056][    T1] initcall dax_core_init+0x0/0xc8 returned 0 after 1000 usecs
[   23.609846][    T1] calling  dma_buf_init+0x0/0xcb @ 1
[   23.615813][    T1] initcall dma_buf_init+0x0/0xcb returned 0 after 0 usecs
[   23.622819][    T1] calling  init_scsi+0x0/0x8c @ 1
[   23.628913][    T1] SCSI subsystem initialized
[   23.633809][    T1] initcall init_scsi+0x0/0x8c returned 0 after 5000 usecs
[   23.641817][    T1] calling  phy_init+0x0/0x69 @ 1
[   23.647839][    T1] initcall phy_init+0x0/0x69 returned 0 after 0 usecs
[   23.654819][    T1] calling  usb_common_init+0x0/0x21 @ 1
[   23.660820][    T1] initcall usb_common_init+0x0/0x21 returned 0 after 0 usecs
[   23.668846][    T1] calling  usb_init+0x0/0x12e @ 1
[   23.674818][    T1] ACPI: bus type USB registered
[   23.679847][    T1] usbcore: registered new interface driver usbfs
[   23.686817][    T1] usbcore: registered new interface driver hub
[   23.693919][    T1] usbcore: registered new device driver usb
[   23.700813][    T1] initcall usb_init+0x0/0x12e returned 0 after 26000 usecs
[   23.708817][    T1] calling  xdbc_init+0x0/0x155 @ 1
[   23.713810][    T1] initcall xdbc_init+0x0/0x155 returned 0 after 0 usecs
[   23.721816][    T1] calling  typec_init+0x0/0xb2 @ 1
[   23.727830][    T1] initcall typec_init+0x0/0xb2 returned 0 after 0 usecs
[   23.734816][    T1] calling  serio_init+0x0/0x32 @ 1
[   23.740813][    T1] initcall serio_init+0x0/0x32 returned 0 after 0 usecs
[   23.748818][    T1] calling  input_init+0x0/0x108 @ 1
[   23.754733][    T1] initcall input_init+0x0/0x108 returned 0 after 0 usecs
[   23.761819][    T1] calling  rtc_init+0x0/0x54 @ 1
[   23.767829][    T1] initcall rtc_init+0x0/0x54 returned 0 after 0 usecs
[   23.774816][    T1] calling  pps_init+0x0/0xb4 @ 1
[   23.780817][    T1] pps_core: LinuxPPS API ver. 1 registered
[   23.786813][    T1] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
[   23.797851][    T1] initcall pps_init+0x0/0xb4 returned 0 after 17000 usecs
[   23.805816][    T1] calling  ptp_init+0x0/0xa3 @ 1
[   23.811811][    T1] PTP clock support registered
[   23.816811][    T1] initcall ptp_init+0x0/0xa3 returned 0 after 5000 usecs
[   23.824817][    T1] calling  power_supply_class_init+0x0/0x44 @ 1
[   23.830829][    T1] initcall power_supply_class_init+0x0/0x44 returned 0 after 0 usecs
[   23.839846][    T1] calling  hwmon_init+0x0/0x103 @ 1
[   23.845850][    T1] initcall hwmon_init+0x0/0x103 returned 0 after 0 usecs
[   23.853817][    T1] calling  md_init+0x0/0x160 @ 1
[   23.859872][    T1] initcall md_init+0x0/0x160 returned 0 after 0 usecs
[   23.866817][    T1] calling  edac_init+0x0/0x7a @ 1
[   23.872810][    T1] EDAC MC: Ver: 3.0.0
[   23.877720][    T1] initcall edac_init+0x0/0x7a returned 0 after 5000 usecs
[   23.885818][    T1] calling  leds_init+0x0/0x40 @ 1
[   23.890811][    T1] initcall leds_init+0x0/0x40 returned 0 after 0 usecs
[   23.898817][    T1] calling  dmi_init+0x0/0x120 @ 1
[   23.903832][    T1] initcall dmi_init+0x0/0x120 returned 0 after 0 usecs
[   23.911816][    T1] calling  efisubsys_init+0x0/0x23b @ 1
[   23.917814][    T1] initcall efisubsys_init+0x0/0x23b returned 0 after 0 usecs
[   23.925847][    T1] calling  ras_init+0x0/0xf @ 1
[   23.931812][    T1] initcall ras_init+0x0/0xf returned 0 after 0 usecs
[   23.938817][    T1] calling  nvmem_init+0x0/0x11 @ 1
[   23.944812][    T1] initcall nvmem_init+0x0/0x11 returned 0 after 0 usecs
[   23.951824][    T1] calling  proto_init+0x0/0x11 @ 1
[   23.957829][    T1] initcall proto_init+0x0/0x11 returned 0 after 0 usecs
[   23.965816][    T1] calling  net_dev_init+0x0/0x259 @ 1
[   23.972008][    T1] initcall net_dev_init+0x0/0x259 returned 0 after 0 usecs
[   23.979819][    T1] calling  neigh_init+0x0/0x89 @ 1
[   23.984812][    T1] initcall neigh_init+0x0/0x89 returned 0 after 0 usecs
[   23.992817][    T1] calling  fib_notifier_init+0x0/0x11 @ 1
[   23.998814][    T1] initcall fib_notifier_init+0x0/0x11 returned 0 after 0 usecs
[   24.007846][    T1] calling  fib_rules_init+0x0/0xb6 @ 1
[   24.013813][    T1] initcall fib_rules_init+0x0/0xb6 returned 0 after 0 usecs
[   24.021818][    T1] calling  init_cgroup_netprio+0x0/0x18 @ 1
[   24.027813][    T1] initcall init_cgroup_netprio+0x0/0x18 returned 0 after 0 usecs
[   24.036852][    T1] calling  bpf_lwt_init+0x0/0x16 @ 1
[   24.042814][    T1] initcall bpf_lwt_init+0x0/0x16 returned 0 after 0 usecs
[   24.050818][    T1] calling  pktsched_init+0x0/0x117 @ 1
[   24.056814][    T1] initcall pktsched_init+0x0/0x117 returned 0 after 0 usecs
[   24.064825][    T1] calling  tc_filter_init+0x0/0x104 @ 1
[   24.070813][    T1] initcall tc_filter_init+0x0/0x104 returned 0 after 0 usecs
[   24.078845][    T1] calling  tc_action_init+0x0/0x59 @ 1
[   24.084811][    T1] initcall tc_action_init+0x0/0x59 returned 0 after 0 usecs
[   24.092818][    T1] calling  ethnl_init+0x0/0x5c @ 1
[   24.098857][    T1] initcall ethnl_init+0x0/0x5c returned 0 after 0 usecs
[   24.106817][    T1] calling  nexthop_init+0x0/0xfa @ 1
[   24.112816][    T1] initcall nexthop_init+0x0/0xfa returned 0 after 0 usecs
[   24.119817][    T1] calling  cipso_v4_init+0x0/0x68 @ 1
[   24.125813][    T1] initcall cipso_v4_init+0x0/0x68 returned 0 after 0 usecs
[   24.133820][    T1] calling  netlbl_init+0x0/0x7d @ 1
[   24.139812][    T1] NetLabel: Initializing
[   24.144807][    T1] NetLabel:  domain hash size = 128
[   24.149810][    T1] NetLabel:  protocols = UNLABELED CIPSOv4 CALIPSO
[   24.157817][    T1] NetLabel:  unlabeled traffic allowed by default
[   24.173698][    T1] initcall netlbl_init+0x0/0x7d returned 0 after 34000 usecs
[   24.181844][    T1] calling  pci_subsys_init+0x0/0x67 @ 1
[   24.187812][    T1] PCI: Using ACPI for IRQ routing
[   24.197135][    T1] PCI: pci_cache_line_size set to 64 bytes
[   24.203211][    T1] e820: reserve RAM buffer [mem 0x0009d000-0x0009ffff]
[   24.210820][    T1] e820: reserve RAM buffer [mem 0x73bed000-0x73ffffff]
[   24.218815][    T1] e820: reserve RAM buffer [mem 0x7b800000-0x7bffffff]
[   24.225822][    T1] initcall pci_subsys_init+0x0/0x67 returned 0 after 39000 usecs
[   24.234845][    T1] calling  vsprintf_init_hashval+0x0/0xe @ 1
[   24.241814][    T1] initcall vsprintf_init_hashval+0x0/0xe returned 0 after 0 usecs
[   24.249844][    T1] calling  vga_arb_device_init+0x0/0x7b @ 1
[   24.256819][    T1] pci 0000:08:00.0: vgaarb: setting as boot VGA device
[   24.257697][    T1] pci 0000:08:00.0: vgaarb: bridge control possible
[   24.257697][    T1] pci 0000:08:00.0: vgaarb: VGA device added: decodes=io+mem,owns=io+mem,locks=none
[   24.281712][    T1] vgaarb: loaded
[   24.285805][    T1] initcall vga_arb_device_init+0x0/0x7b returned 0 after 29000 usecs
[   24.294847][    T1] calling  watchdog_init+0x0/0x9c @ 1
[   24.300816][    T1] initcall watchdog_init+0x0/0x9c returned 0 after 0 usecs
[   24.308953][    T1] calling  nmi_warning_debugfs+0x0/0x2b @ 1
[   24.315860][    T1] initcall nmi_warning_debugfs+0x0/0x2b returned 0 after 0 usecs
[   24.323851][    T1] calling  save_microcode_in_initrd+0x0/0x51 @ 1
[   24.330820][    T1] initcall save_microcode_in_initrd+0x0/0x51 returned 0 after 0 usecs
[   24.340846][    T1] calling  hpet_late_init+0x0/0x113 @ 1
[   24.346819][    T1] hpet0: at MMIO 0xfed00000, IRQs 2, 8, 0, 0, 0, 0, 0, 0
[   24.353817][    T1] hpet0: 8 comparators, 64-bit 14.318180 MHz counter
[   24.363697][    T1] initcall hpet_late_init+0x0/0x113 returned 0 after 17000 usecs
[   24.371846][    T1] calling  init_amd_nbs+0x0/0x129 @ 1
[   24.377875][    T1] initcall init_amd_nbs+0x0/0x129 returned 0 after 1000 usecs
[   24.386849][    T1] calling  iomem_init_inode+0x0/0x8a @ 1
[   24.392935][    T1] initcall iomem_init_inode+0x0/0x8a returned 0 after 0 usecs
[   24.400844][    T1] calling  clocksource_done_booting+0x0/0x46 @ 1
[   24.408902][    T1] clocksource: Switched to clocksource tsc-early
[   24.415801][    T1] initcall clocksource_done_booting+0x0/0x46 returned 0 after 8104 usecs
[   24.425184][    T1] calling  tracer_init_tracefs+0x0/0xb9 @ 1
[   24.431797][    T1] initcall tracer_init_tracefs+0x0/0xb9 returned 0 after 77 usecs
[   24.440500][    T1] calling  init_trace_printk_function_export+0x0/0x2c @ 1
[   24.448409][    T1] initcall init_trace_printk_function_export+0x0/0x2c returned 0 after 9 usecs
[   24.458372][    T1] calling  init_graph_tracefs+0x0/0x2c @ 1
[   24.464815][    T1] initcall init_graph_tracefs+0x0/0x2c returned 0 after 4 usecs
[   24.473319][    T1] calling  trace_events_synth_init+0x0/0x4b @ 1
[   24.480237][    T1] initcall trace_events_synth_init+0x0/0x4b returned 0 after 1 usecs
[   24.489222][    T1] calling  bpf_event_init+0x0/0x13 @ 1
[   24.495265][    T1] initcall bpf_event_init+0x0/0x13 returned 0 after 0 usecs
[   24.503348][    T1] calling  init_kprobe_trace+0x0/0x159 @ 1
[   24.509790][    T1] initcall init_kprobe_trace+0x0/0x159 returned 0 after 9 usecs
[   24.518289][    T1] calling  init_dynamic_event+0x0/0x2c @ 1
[   24.524730][    T1] initcall init_dynamic_event+0x0/0x2c returned 0 after 6 usecs
[   24.533227][    T1] calling  init_uprobe_trace+0x0/0x60 @ 1
[   24.539569][    T1] initcall init_uprobe_trace+0x0/0x60 returned 0 after 7 usecs
[   24.547969][    T1] calling  bpf_init+0x0/0x51 @ 1
[   24.553442][    T1] initcall bpf_init+0x0/0x51 returned 0 after 15 usecs
[   24.561038][    T1] calling  btf_module_init+0x0/0x27 @ 1
[   24.567178][    T1] initcall btf_module_init+0x0/0x27 returned 0 after 2 usecs
[   24.575389][    T1] calling  secretmem_init+0x0/0x41 @ 1
[   24.581441][    T1] initcall secretmem_init+0x0/0x41 returned 0 after 1 usecs
[   24.589526][    T1] calling  init_fs_stat_sysctls+0x0/0x32 @ 1
[   24.596200][    T1] initcall init_fs_stat_sysctls+0x0/0x32 returned 0 after 40 usecs
[   24.604993][    T1] calling  init_fs_exec_sysctls+0x0/0x26 @ 1
[   24.611644][    T1] initcall init_fs_exec_sysctls+0x0/0x26 returned 0 after 25 usecs
[   24.620438][    T1] calling  init_pipe_fs+0x0/0x68 @ 1
[   24.626388][    T1] initcall init_pipe_fs+0x0/0x68 returned 0 after 99 usecs
[   24.634376][    T1] calling  init_fs_namei_sysctls+0x0/0x26 @ 1
[   24.641119][    T1] initcall init_fs_namei_sysctls+0x0/0x26 returned 0 after 20 usecs
[   24.650010][    T1] calling  init_fs_dcache_sysctls+0x0/0x26 @ 1
[   24.656834][    T1] initcall init_fs_dcache_sysctls+0x0/0x26 returned 0 after 2 usecs
[   24.665726][    T1] calling  init_fs_namespace_sysctls+0x0/0x26 @ 1
[   24.672841][    T1] initcall init_fs_namespace_sysctls+0x0/0x26 returned 0 after 4 usecs
[   24.682022][    T1] calling  cgroup_writeback_init+0x0/0x2a @ 1
[   24.688853][    T1] initcall cgroup_writeback_init+0x0/0x2a returned 0 after 100 usecs
[   24.697841][    T1] calling  inotify_user_setup+0x0/0xd4 @ 1
[   24.704296][    T1] initcall inotify_user_setup+0x0/0xd4 returned 0 after 21 usecs
[   24.712898][    T1] calling  eventpoll_init+0x0/0xe3 @ 1
[   24.719015][    T1] initcall eventpoll_init+0x0/0xe3 returned 0 after 75 usecs
[   24.727223][    T1] calling  anon_inode_init+0x0/0x5d @ 1
[   24.733400][    T1] initcall anon_inode_init+0x0/0x5d returned 0 after 40 usecs
[   24.741704][    T1] calling  init_dax_wait_table+0x0/0x38 @ 1
[   24.748313][    T1] initcall init_dax_wait_table+0x0/0x38 returned 0 after 80 usecs
[   24.757008][    T1] calling  proc_locks_init+0x0/0x2c @ 1
[   24.763160][    T1] initcall proc_locks_init+0x0/0x2c returned 0 after 13 usecs
[   24.771464][    T1] calling  init_fs_coredump_sysctls+0x0/0x26 @ 1
[   24.778494][    T1] initcall init_fs_coredump_sysctls+0x0/0x26 returned 0 after 14 usecs
[   24.787671][    T1] calling  iomap_init+0x0/0x20 @ 1
[   24.793402][    T1] initcall iomap_init+0x0/0x20 returned 0 after 77 usecs
[   24.801193][    T1] calling  dquot_init+0x0/0x112 @ 1
[   24.806941][    T1] VFS: Disk quotas dquot_6.6.0
[   24.812300][    T1] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
[   24.820895][    T1] initcall dquot_init+0x0/0x112 returned 0 after 13954 usecs
[   24.829104][    T1] calling  quota_init+0x0/0x28 @ 1
[   24.834798][    T1] initcall quota_init+0x0/0x28 returned 0 after 37 usecs
[   24.842588][    T1] calling  proc_cmdline_init+0x0/0x26 @ 1
[   24.848932][    T1] initcall proc_cmdline_init+0x0/0x26 returned 0 after 8 usecs
[   24.857327][    T1] calling  proc_consoles_init+0x0/0x29 @ 1
[   24.863790][    T1] initcall proc_consoles_init+0x0/0x29 returned 0 after 29 usecs
[   24.872397][    T1] calling  proc_cpuinfo_init+0x0/0x23 @ 1
[   24.878738][    T1] initcall proc_cpuinfo_init+0x0/0x23 returned 0 after 5 usecs
[   24.887142][    T1] calling  proc_devices_init+0x0/0x30 @ 1
[   24.893478][    T1] initcall proc_devices_init+0x0/0x30 returned 0 after 2 usecs
[   24.901880][    T1] calling  proc_interrupts_init+0x0/0x29 @ 1
[   24.908506][    T1] initcall proc_interrupts_init+0x0/0x29 returned 0 after 1 usecs
[   24.917201][    T1] calling  proc_loadavg_init+0x0/0x2d @ 1
[   24.923542][    T1] initcall proc_loadavg_init+0x0/0x2d returned 0 after 2 usecs
[   24.931943][    T1] calling  proc_meminfo_init+0x0/0x2d @ 1
[   24.938280][    T1] initcall proc_meminfo_init+0x0/0x2d returned 0 after 1 usecs
[   24.946679][    T1] calling  proc_stat_init+0x0/0x23 @ 1
[   24.952733][    T1] initcall proc_stat_init+0x0/0x23 returned 0 after 4 usecs
[   24.960815][    T1] calling  proc_uptime_init+0x0/0x2d @ 1
[   24.967056][    T1] initcall proc_uptime_init+0x0/0x2d returned 0 after 0 usecs
[   24.975362][    T1] calling  proc_version_init+0x0/0x2d @ 1
[   24.981696][    T1] initcall proc_version_init+0x0/0x2d returned 0 after 0 usecs
[   24.990097][    T1] calling  proc_softirqs_init+0x0/0x2d @ 1
[   24.996532][    T1] initcall proc_softirqs_init+0x0/0x2d returned 0 after 1 usecs
[   25.005031][    T1] calling  proc_kcore_init+0x0/0xfb @ 1
[   25.011197][    T1] initcall proc_kcore_init+0x0/0xfb returned 0 after 26 usecs
[   25.019501][    T1] calling  vmcore_init+0x0/0x171 @ 1
[   25.025351][    T1] initcall vmcore_init+0x0/0x171 returned 0 after 2 usecs
[   25.033241][    T1] calling  proc_kmsg_init+0x0/0x26 @ 1
[   25.039287][    T1] initcall proc_kmsg_init+0x0/0x26 returned 0 after 2 usecs
[   25.047373][    T1] calling  proc_page_init+0x0/0x5a @ 1
[   25.053418][    T1] initcall proc_page_init+0x0/0x5a returned 0 after 5 usecs
[   25.061499][    T1] calling  init_ramfs_fs+0x0/0x11 @ 1
[   25.067451][    T1] initcall init_ramfs_fs+0x0/0x11 returned 0 after 2 usecs
[   25.075436][    T1] calling  init_hugetlbfs_fs+0x0/0xff @ 1
[   25.081946][    T1] initcall init_hugetlbfs_fs+0x0/0xff returned 0 after 173 usecs
[   25.090544][    T1] calling  aa_create_aafs+0x0/0x3b0 @ 1
[   25.096845][    T1] AppArmor: AppArmor Filesystem Enabled
[   25.102984][    T1] initcall aa_create_aafs+0x0/0x3b0 returned 0 after 6297 usecs
[   25.111485][    T1] calling  dynamic_debug_init_control+0x0/0x80 @ 1
[   25.118714][    T1] initcall dynamic_debug_init_control+0x0/0x80 returned 0 after 8 usecs
[   25.127986][    T1] calling  acpi_event_init+0x0/0x31 @ 1
[   25.134155][    T1] initcall acpi_event_init+0x0/0x31 returned 0 after 32 usecs
[   25.142465][    T1] calling  pnp_system_init+0x0/0x11 @ 1
[   25.148623][    T1] initcall pnp_system_init+0x0/0x11 returned 0 after 17 usecs
[   25.166044][    T1] calling  pnpacpi_init+0x0/0x6e @ 1
[   25.171894][    T1] pnp: PnP ACPI init
[   25.177883][    T1] system 00:01: [io  0x0500-0x053f] has been reserved
[   25.185393][    T1] system 00:01: [io  0x0400-0x047f] has been reserved
[   25.192897][    T1] system 00:01: [io  0x0540-0x057f] has been reserved
[   25.200400][    T1] system 00:01: [io  0x0600-0x061f] has been reserved
[   25.207904][    T1] system 00:01: [io  0x0ca0-0x0ca5] could not be reserved
[   25.215803][    T1] system 00:01: [io  0x0880-0x0883] has been reserved
[   25.223301][    T1] system 00:01: [io  0x0800-0x081f] has been reserved
[   25.230802][    T1] system 00:01: [mem 0xfed1c000-0xfed3ffff] could not be reserved
[   25.239496][    T1] system 00:01: [mem 0xfed45000-0xfed8bfff] has been reserved
[   25.247802][    T1] system 00:01: [mem 0xff000000-0xffffffff] could not be reserved
[   25.256498][    T1] system 00:01: [mem 0xfee00000-0xfeefffff] has been reserved
[   25.264794][    T1] system 00:01: [mem 0xfed12000-0xfed1200f] has been reserved
[   25.273101][    T1] system 00:01: [mem 0xfed12010-0xfed1201f] has been reserved
[   25.281405][    T1] system 00:01: [mem 0xfed1b000-0xfed1bfff] has been reserved
[   25.290494][    T1] pnp: PnP ACPI: found 5 devices
[   25.295954][    T1] initcall pnpacpi_init+0x0/0x6e returned 0 after 124062 usecs
[   25.304359][    T1] calling  chr_dev_init+0x0/0xab @ 1
[   25.311706][    T1] initcall chr_dev_init+0x0/0xab returned 0 after 1494 usecs
[   25.319919][    T1] calling  hwrng_modinit+0x0/0x86 @ 1
[   25.325910][    T1] initcall hwrng_modinit+0x0/0x86 returned 0 after 46 usecs
[   25.334007][    T1] calling  firmware_class_init+0x0/0xfe @ 1
[   25.340552][    T1] initcall firmware_class_init+0x0/0xfe returned 0 after 17 usecs
[   25.349242][    T1] calling  init_acpi_pm_clocksource+0x0/0xe0 @ 1
[   25.360786][    T1] clocksource: acpi_pm: mask: 0xffffff max_cycles: 0xffffff, max_idle_ns: 2085701024 ns
[   25.371621][    T1] initcall init_acpi_pm_clocksource+0x0/0xe0 returned 0 after 15355 usecs
[   25.381092][    T1] calling  powercap_init+0x0/0x26 @ 1
[   25.387058][    T1] initcall powercap_init+0x0/0x26 returned 0 after 30 usecs
[   25.395140][    T1] calling  sysctl_core_init+0x0/0x2b @ 1
[   25.401405][    T1] initcall sysctl_core_init+0x0/0x2b returned 0 after 25 usecs
[   25.409808][    T1] calling  eth_offload_init+0x0/0x18 @ 1
[   25.416042][    T1] initcall eth_offload_init+0x0/0x18 returned 0 after 0 usecs
[   25.424346][    T1] calling  ipv4_offload_init+0x0/0x78 @ 1
[   25.430682][    T1] initcall ipv4_offload_init+0x0/0x78 returned 0 after 1 usecs
[   25.439085][    T1] calling  inet_init+0x0/0x2aa @ 1
[   25.444871][    T1] NET: Registered PF_INET protocol family
[   25.452081][    T1] IP idents hash table entries: 262144 (order: 9, 2097152 bytes, vmalloc)
[   25.465290][    T1] tcp_listen_portaddr_hash hash table entries: 16384 (order: 6, 262144 bytes, vmalloc)
[   25.476085][    T1] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, vmalloc)
[   25.485800][    T1] TCP established hash table entries: 262144 (order: 9, 2097152 bytes, vmalloc)
[   25.496253][    T1] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, vmalloc)
[   25.506052][    T1] TCP: Hash tables configured (established 262144 bind 65536)
[   25.514679][    T1] UDP hash table entries: 16384 (order: 7, 524288 bytes, vmalloc)
[   25.523488][    T1] UDP-Lite hash table entries: 16384 (order: 7, 524288 bytes, vmalloc)
[   25.533061][    T1] initcall inet_init+0x0/0x2aa returned 0 after 88322 usecs
[   25.541149][    T1] calling  af_unix_init+0x0/0xd4 @ 1
[   25.547016][    T1] NET: Registered PF_UNIX/PF_LOCAL protocol family
[   25.554242][    T1] initcall af_unix_init+0x0/0xd4 returned 0 after 7245 usecs
[   25.562451][    T1] calling  ipv6_offload_init+0x0/0x83 @ 1
[   25.568794][    T1] initcall ipv6_offload_init+0x0/0x83 returned 0 after 2 usecs
[   25.577196][    T1] calling  init_sunrpc+0x0/0x8c @ 1
[   25.583218][    T1] RPC: Registered named UNIX socket transport module.
[   25.590731][    T1] RPC: Registered udp transport module.
[   25.596871][    T1] RPC: Registered tcp transport module.
[   25.603010][    T1] RPC: Registered tcp NFSv4.1 backchannel transport module.
[   25.611092][    T1] initcall init_sunrpc+0x0/0x8c returned 0 after 28143 usecs
[   25.619308][    T1] calling  vlan_offload_init+0x0/0x24 @ 1
[   25.625643][    T1] initcall vlan_offload_init+0x0/0x24 returned 0 after 1 usecs
[   25.634050][    T1] calling  xsk_init+0x0/0xcf @ 1
[   25.639516][    T1] NET: Registered PF_XDP protocol family
[   25.645785][    T1] initcall xsk_init+0x0/0xcf returned 0 after 6271 usecs
[   25.653600][    T1] calling  pcibios_assign_resources+0x0/0xd1 @ 1
[   25.660667][    T1] pci 0000:01:00.0: can't claim BAR 6 [mem 0xfff00000-0xffffffff pref]: no compatible bridge window
[   25.672679][    T1] pci 0000:03:00.0: can't claim BAR 6 [mem 0xfff80000-0xffffffff pref]: no compatible bridge window
[   25.684691][    T1] pci 0000:03:00.1: can't claim BAR 6 [mem 0xfff80000-0xffffffff pref]: no compatible bridge window
[   25.696899][    T1] pci 0000:01:00.0: BAR 6: no space for [mem size 0x00100000 pref]
[   25.705700][    T1] pci 0000:01:00.0: BAR 6: failed to assign [mem size 0x00100000 pref]
[   25.714886][    T1] pci 0000:00:02.0: PCI bridge to [bus 01]
[   25.721324][    T1] pci 0000:00:02.0:   bridge window [io  0x1000-0x1fff]
[   25.729035][    T1] pci 0000:00:02.0:   bridge window [mem 0x93300000-0x933fffff]
[   25.737555][    T1] pci 0000:00:03.0: PCI bridge to [bus 02]
[   25.744031][    T1] pci 0000:03:00.0: BAR 6: assigned [mem 0x92e80000-0x92efffff pref]
[   25.753033][    T1] pci 0000:03:00.1: BAR 6: no space for [mem size 0x00080000 pref]
[   25.761829][    T1] pci 0000:03:00.1: BAR 6: failed to assign [mem size 0x00080000 pref]
[   25.771012][    T1] pci 0000:00:03.2: PCI bridge to [bus 03-04]
[   25.777748][    T1] pci 0000:00:03.2:   bridge window [mem 0x92f00000-0x932fffff]
[   25.786260][    T1] pci 0000:00:03.2:   bridge window [mem 0x92a00000-0x92efffff 64bit pref]
[   25.795843][    T1] pci 0000:00:03.3: PCI bridge to [bus 05]
[   25.802297][    T1] pci 0000:00:11.0: PCI bridge to [bus 06]
[   25.808760][    T1] pci 0000:00:1c.0: PCI bridge to [bus 07]
[   25.815222][    T1] pci 0000:00:1c.7: PCI bridge to [bus 08]
[   25.821663][    T1] pci 0000:00:1c.7:   bridge window [mem 0x92000000-0x928fffff]
[   25.830171][    T1] pci 0000:00:1c.7:   bridge window [mem 0x91000000-0x91ffffff 64bit pref]
[   25.839758][    T1] pci 0000:00:1e.0: PCI bridge to [bus 09]
[   25.846213][    T1] pci_bus 0000:00: resource 4 [io  0x0000-0x0cf7 window]
[   25.854009][    T1] pci_bus 0000:00: resource 5 [io  0x1000-0x3fff window]
[   25.861805][    T1] pci_bus 0000:00: resource 6 [mem 0x000a0000-0x000bffff window]
[   25.870405][    T1] pci_bus 0000:00: resource 7 [mem 0xfed40000-0xfedfffff window]
[   25.879004][    T1] pci_bus 0000:00: resource 8 [mem 0x90000000-0xabffbfff window]
[   25.887602][    T1] pci_bus 0000:00: resource 9 [mem 0x380000000000-0x381fffffffff window]
[   25.896977][    T1] pci_bus 0000:01: resource 0 [io  0x1000-0x1fff]
[   25.904091][    T1] pci_bus 0000:01: resource 1 [mem 0x93300000-0x933fffff]
[   25.911983][    T1] pci_bus 0000:03: resource 1 [mem 0x92f00000-0x932fffff]
[   25.919876][    T1] pci_bus 0000:03: resource 2 [mem 0x92a00000-0x92efffff 64bit pref]
[   25.928866][    T1] pci_bus 0000:08: resource 1 [mem 0x92000000-0x928fffff]
[   25.936760][    T1] pci_bus 0000:08: resource 2 [mem 0x91000000-0x91ffffff 64bit pref]
[   25.945742][    T1] pci_bus 0000:09: resource 4 [io  0x0000-0x0cf7 window]
[   25.953536][    T1] pci_bus 0000:09: resource 5 [io  0x1000-0x3fff window]
[   25.961327][    T1] pci_bus 0000:09: resource 6 [mem 0x000a0000-0x000bffff window]
[   25.969928][    T1] pci_bus 0000:09: resource 7 [mem 0xfed40000-0xfedfffff window]
[   25.978532][    T1] pci_bus 0000:09: resource 8 [mem 0x90000000-0xabffbfff window]
[   25.987132][    T1] pci_bus 0000:09: resource 9 [mem 0x380000000000-0x381fffffffff window]
[   25.996624][    T1] pci 0000:40:02.0: PCI bridge to [bus 41]
[   26.003059][    T1] pci 0000:40:02.0:   bridge window [io  0x4000-0x4fff]
[   26.010763][    T1] pci 0000:40:02.0:   bridge window [mem 0xac100000-0xac2fffff]
[   26.019268][    T1] pci 0000:40:02.0:   bridge window [mem 0x382000000000-0x3820001fffff 64bit pref]
[   26.029628][    T1] pci 0000:40:02.2: PCI bridge to [bus 42]
[   26.036061][    T1] pci 0000:40:02.2:   bridge window [io  0x5000-0x5fff]
[   26.043765][    T1] pci 0000:40:02.2:   bridge window [mem 0xac300000-0xac4fffff]
[   26.052272][    T1] pci 0000:40:02.2:   bridge window [mem 0x382000200000-0x3820003fffff 64bit pref]
[   26.062627][    T1] pci 0000:40:03.0: PCI bridge to [bus 43]
[   26.069081][    T1] pci_bus 0000:40: resource 4 [mem 0x000a0000-0x000bffff window]
[   26.077680][    T1] pci_bus 0000:40: resource 5 [io  0x4000-0x7fff window]
[   26.085463][    T1] pci_bus 0000:40: resource 6 [io  0x03b0-0x03bb window]
[   26.093259][    T1] pci_bus 0000:40: resource 7 [io  0x03c0-0x03df window]
[   26.101056][    T1] pci_bus 0000:40: resource 8 [mem 0xac000000-0xc7ffbfff window]
[   26.109656][    T1] pci_bus 0000:40: resource 9 [mem 0x382000000000-0x383fffffffff window]
[   26.119034][    T1] pci_bus 0000:41: resource 0 [io  0x4000-0x4fff]
[   26.126146][    T1] pci_bus 0000:41: resource 1 [mem 0xac100000-0xac2fffff]
[   26.134038][    T1] pci_bus 0000:41: resource 2 [mem 0x382000000000-0x3820001fffff 64bit pref]
[   26.153098][    T1] pci_bus 0000:42: resource 0 [io  0x5000-0x5fff]
[   26.160212][    T1] pci_bus 0000:42: resource 1 [mem 0xac300000-0xac4fffff]
[   26.168101][    T1] pci_bus 0000:42: resource 2 [mem 0x382000200000-0x3820003fffff 64bit pref]
[   26.177949][    T1] ACPI: \_SB_.IIO1.AID1: IOxAPIC at (null), GSI 48
[   26.185209][    T1] pci 0000:80:02.0: PCI bridge to [bus 81]
[   26.191661][    T1] pci 0000:80:02.2: PCI bridge to [bus 82]
[   26.198115][    T1] pci 0000:80:03.0: PCI bridge to [bus 83]
[   26.204565][    T1] pci_bus 0000:80: resource 4 [mem 0x000a0000-0x000bffff window]
[   26.213163][    T1] pci_bus 0000:80: resource 5 [io  0x03b0-0x03bb window]
[   26.220957][    T1] pci_bus 0000:80: resource 6 [io  0x03c0-0x03df window]
[   26.228752][    T1] pci_bus 0000:80: resource 7 [mem 0xc8000000-0xe3ffbfff window]
[   26.237354][    T1] pci_bus 0000:80: resource 8 [mem 0x384000000000-0x385fffffffff window]
[   26.246751][    T1] ACPI: \_SB_.IIO2.AID2: IOxAPIC at (null), GSI 72
[   26.254024][    T1] pci 0000:c0:02.0: PCI bridge to [bus c1]
[   26.260459][    T1] pci 0000:c0:02.0:   bridge window [io  0xc000-0xcfff]
[   26.268166][    T1] pci 0000:c0:02.0:   bridge window [mem 0xe4100000-0xe42fffff]
[   26.276670][    T1] pci 0000:c0:02.0:   bridge window [mem 0x386000000000-0x3860001fffff 64bit pref]
[   26.287027][    T1] pci 0000:c0:02.2: PCI bridge to [bus c2]
[   26.293461][    T1] pci 0000:c0:02.2:   bridge window [io  0xd000-0xdfff]
[   26.301165][    T1] pci 0000:c0:02.2:   bridge window [mem 0xe4300000-0xe44fffff]
[   26.309673][    T1] pci 0000:c0:02.2:   bridge window [mem 0x386000200000-0x3860003fffff 64bit pref]
[   26.320036][    T1] pci 0000:c0:03.0: PCI bridge to [bus c3]
[   26.326484][    T1] pci_bus 0000:c0: resource 4 [mem 0x000a0000-0x000bffff window]
[   26.335080][    T1] pci_bus 0000:c0: resource 5 [io  0xc000-0xffff window]
[   26.342873][    T1] pci_bus 0000:c0: resource 6 [io  0x03b0-0x03bb window]
[   26.350669][    T1] pci_bus 0000:c0: resource 7 [io  0x03c0-0x03df window]
[   26.358463][    T1] pci_bus 0000:c0: resource 8 [mem 0xe4000000-0xfbffbfff window]
[   26.367064][    T1] pci_bus 0000:c0: resource 9 [mem 0x386000000000-0x387fffffffff window]
[   26.376442][    T1] pci_bus 0000:c1: resource 0 [io  0xc000-0xcfff]
[   26.383558][    T1] pci_bus 0000:c1: resource 1 [mem 0xe4100000-0xe42fffff]
[   26.391449][    T1] pci_bus 0000:c1: resource 2 [mem 0x386000000000-0x3860001fffff 64bit pref]
[   26.401218][    T1] pci_bus 0000:c2: resource 0 [io  0xd000-0xdfff]
[   26.408329][    T1] pci_bus 0000:c2: resource 1 [mem 0xe4300000-0xe44fffff]
[   26.416220][    T1] pci_bus 0000:c2: resource 2 [mem 0x386000200000-0x3860003fffff 64bit pref]
[   26.425999][    T1] ACPI: \_SB_.IIO3.AID3: IOxAPIC at (null), GSI 96
[   26.433263][    T1] initcall pcibios_assign_resources+0x0/0xd1 returned 0 after 772637 usecs
[   26.442832][    T1] calling  pci_apply_final_quirks+0x0/0x125 @ 1
[   26.450298][    T1] pci 0000:00:05.0: calling  quirk_disable_intel_boot_interrupt+0x0/0x100 @ 1
[   26.460168][    T1] pci 0000:00:05.0: disabled boot interrupts on device [8086:2f28]
[   26.468960][    T1] pci 0000:00:05.0: quirk_disable_intel_boot_interrupt+0x0/0x100 took 8587 usecs
[   26.479143][    T1] pci 0000:00:1a.0: calling  quirk_usb_early_handoff+0x0/0x140 @ 1
[   26.488173][    T1] IOAPIC[0]: Preconfigured routing entry (8-16 -> IRQ 16 Level:1 ActiveLow:1)
[   26.498148][    T1] pci 0000:00:1a.0: quirk_usb_early_handoff+0x0/0x140 took 9953 usecs
[   26.507253][    T1] pci 0000:00:1d.0: calling  quirk_usb_early_handoff+0x0/0x140 @ 1
[   26.516148][    T1] IOAPIC[0]: Preconfigured routing entry (8-23 -> IRQ 23 Level:1 ActiveLow:1)
[   26.526089][    T1] pci 0000:00:1d.0: quirk_usb_early_handoff+0x0/0x140 took 9796 usecs
[   26.535200][    T1] pci 0000:03:00.0: calling  quirk_e100_interrupt+0x0/0x180 @ 1
[   26.543712][    T1] pci 0000:03:00.0: quirk_e100_interrupt+0x0/0x180 took 0 usecs
[   26.552223][    T1] pci 0000:03:00.1: calling  quirk_e100_interrupt+0x0/0x180 @ 1
[   26.560732][    T1] pci 0000:03:00.1: quirk_e100_interrupt+0x0/0x180 took 0 usecs
[   26.569255][    T1] pci 0000:40:05.0: calling  quirk_disable_intel_boot_interrupt+0x0/0x100 @ 1
[   26.579120][    T1] pci 0000:40:05.0: disabled boot interrupts on device [8086:2f28]
[   26.587916][    T1] pci 0000:40:05.0: quirk_disable_intel_boot_interrupt+0x0/0x100 took 8590 usecs
[   26.598091][    T1] pci 0000:80:05.0: calling  quirk_disable_intel_boot_interrupt+0x0/0x100 @ 1
[   26.607960][    T1] pci 0000:80:05.0: disabled boot interrupts on device [8086:2f28]
[   26.616760][    T1] pci 0000:80:05.0: quirk_disable_intel_boot_interrupt+0x0/0x100 took 8592 usecs
[   26.626929][    T1] pci 0000:c0:05.0: calling  quirk_disable_intel_boot_interrupt+0x0/0x100 @ 1
[   26.636802][    T1] pci 0000:c0:05.0: disabled boot interrupts on device [8086:2f28]
[   26.645598][    T1] pci 0000:c0:05.0: quirk_disable_intel_boot_interrupt+0x0/0x100 took 8590 usecs
[   26.655769][    T1] PCI: CLS 32 bytes, default 64
[   26.661135][    T1] initcall pci_apply_final_quirks+0x0/0x125 returned 0 after 211383 usecs
[   26.670612][    T1] calling  acpi_reserve_resources+0x0/0xef @ 1
[   26.677443][    T1] initcall acpi_reserve_resources+0x0/0xef returned 0 after 2 usecs
[   26.686339][    T1] calling  populate_rootfs+0x0/0x40 @ 1
[   26.692493][    T1] initcall populate_rootfs+0x0/0x40 returned 0 after 3 usecs
[   26.692593][  T743] Trying to unpack rootfs image as initramfs...
[   26.700559][    T1] calling  pci_iommu_init+0x0/0x36 @ 1
[   26.700566][    T1] PCI-DMA: Using software bounce buffering for IO (SWIOTLB)
[   26.700567][    T1] software IO TLB: mapped [mem 0x0000000077800000-0x000000007b800000] (64MB)
[   26.700569][    T1] initcall pci_iommu_init+0x0/0x36 returned 0 after 3 usecs
[   26.739617][    T1] calling  ir_dev_scope_init+0x0/0x3d @ 1
[   26.745955][    T1] initcall ir_dev_scope_init+0x0/0x3d returned 0 after 0 usecs
[   26.754510][    T1] calling  ia32_binfmt_init+0x0/0x18 @ 1
[   26.760762][    T1] initcall ia32_binfmt_init+0x0/0x18 returned 0 after 12 usecs
[   26.769173][    T1] calling  amd_ibs_init+0x0/0x156 @ 1
[   26.775116][    T1] initcall amd_ibs_init+0x0/0x156 returned -19 after 0 usecs
[   26.783323][    T1] calling  msr_init+0x0/0x5a @ 1
[   26.788804][    T1] initcall msr_init+0x0/0x5a returned 0 after 22 usecs
[   26.796400][    T1] calling  register_kernel_offset_dumper+0x0/0x1f @ 1
[   26.803903][    T1] initcall register_kernel_offset_dumper+0x0/0x1f returned 0 after 0 usecs
[   26.813468][    T1] calling  i8259A_init_ops+0x0/0x25 @ 1
[   26.819608][    T1] initcall i8259A_init_ops+0x0/0x25 returned 0 after 0 usecs
[   26.827814][    T1] calling  init_tsc_clocksource+0x0/0x89 @ 1
[   26.834442][    T1] initcall init_tsc_clocksource+0x0/0x89 returned 0 after 1 usecs
[   26.843134][    T1] calling  add_rtc_cmos+0x0/0xb5 @ 1
[   26.848980][    T1] initcall add_rtc_cmos+0x0/0xb5 returned 0 after 0 usecs
[   26.856870][    T1] calling  i8237A_init_ops+0x0/0x3f @ 1
[   26.863014][    T1] initcall i8237A_init_ops+0x0/0x3f returned 0 after 5 usecs
[   26.871224][    T1] calling  umwait_init+0x0/0x96 @ 1
[   26.876974][    T1] initcall umwait_init+0x0/0x96 returned -19 after 0 usecs
[   26.884961][    T1] calling  msr_init+0x0/0xe2 @ 1
[   26.898199][    T1] initcall msr_init+0x0/0xe2 returned 0 after 7779 usecs
[   26.905998][    T1] calling  cpuid_init+0x0/0xe2 @ 1
[   26.915498][    T1] initcall cpuid_init+0x0/0xe2 returned 0 after 3848 usecs
[   26.923490][    T1] calling  ioapic_init_ops+0x0/0x18 @ 1
[   26.929633][    T1] initcall ioapic_init_ops+0x0/0x18 returned 0 after 0 usecs
[   26.937833][    T1] calling  register_e820_pmem+0x0/0x62 @ 1
[   26.944285][    T1] initcall register_e820_pmem+0x0/0x62 returned 0 after 23 usecs
[   26.952881][    T1] calling  add_pcspkr+0x0/0x73 @ 1
[   26.958541][    T1] initcall add_pcspkr+0x0/0x73 returned 0 after 8 usecs
[   26.966234][    T1] calling  start_periodic_check_for_corruption+0x0/0x40 @ 1
[   26.974325][    T1] initcall start_periodic_check_for_corruption+0x0/0x40 returned 0 after 0 usecs
[   26.984478][    T1] calling  audit_classes_init+0x0/0xb3 @ 1
[   26.990917][    T1] initcall audit_classes_init+0x0/0xb3 returned 0 after 9 usecs
[   26.999422][    T1] calling  sha1_ssse3_mod_init+0x0/0x9f @ 1
[   27.005973][    T1] initcall sha1_ssse3_mod_init+0x0/0x9f returned 0 after 23 usecs
[   27.014666][    T1] calling  sha256_ssse3_mod_init+0x0/0xb3 @ 1
[   27.021398][    T1] initcall sha256_ssse3_mod_init+0x0/0xb3 returned 0 after 8 usecs
[   27.030187][    T1] calling  iosf_mbi_init+0x0/0x29 @ 1
[   27.036281][    T1] initcall iosf_mbi_init+0x0/0x29 returned 0 after 148 usecs
[   27.044489][    T1] calling  proc_execdomains_init+0x0/0x26 @ 1
[   27.051216][    T1] initcall proc_execdomains_init+0x0/0x26 returned 0 after 3 usecs
[   27.060004][    T1] calling  register_warn_debugfs+0x0/0x28 @ 1
[   27.066732][    T1] initcall register_warn_debugfs+0x0/0x28 returned 0 after 2 usecs
[   27.075520][    T1] calling  cpuhp_sysfs_init+0x0/0x8f @ 1
[   27.082170][    T1] initcall cpuhp_sysfs_init+0x0/0x8f returned 0 after 413 usecs
[   27.090676][    T1] calling  ioresources_init+0x0/0x4e @ 1
[   27.096909][    T1] initcall ioresources_init+0x0/0x4e returned 0 after 5 usecs
[   27.105213][    T1] calling  snapshot_device_init+0x0/0x11 @ 1
[   27.111868][    T1] initcall snapshot_device_init+0x0/0x11 returned 0 after 29 usecs
[   27.120662][    T1] calling  irq_pm_init_ops+0x0/0x18 @ 1
[   27.135923][    T1] initcall irq_pm_init_ops+0x0/0x18 returned 0 after 0 usecs
[   27.144133][    T1] calling  klp_init+0x0/0x2d @ 1
[   27.149599][    T1] initcall klp_init+0x0/0x2d returned 0 after 7 usecs
[   27.157106][    T1] calling  proc_modules_init+0x0/0x23 @ 1
[   27.163440][    T1] initcall proc_modules_init+0x0/0x23 returned 0 after 2 usecs
[   27.171843][    T1] calling  timer_sysctl_init+0x0/0x1f @ 1
[   27.178193][    T1] initcall timer_sysctl_init+0x0/0x1f returned 0 after 18 usecs
[   27.186696][    T1] calling  timekeeping_init_ops+0x0/0x18 @ 1
[   27.193322][    T1] initcall timekeeping_init_ops+0x0/0x18 returned 0 after 0 usecs
[   27.202014][    T1] calling  init_clocksource_sysfs+0x0/0x28 @ 1
[   27.208874][    T1] initcall init_clocksource_sysfs+0x0/0x28 returned 0 after 40 usecs
[   27.217860][    T1] calling  init_timer_list_procfs+0x0/0x36 @ 1
[   27.224690][    T1] initcall init_timer_list_procfs+0x0/0x36 returned 0 after 9 usecs
[   27.233577][    T1] calling  alarmtimer_init+0x0/0xe3 @ 1
[   27.239733][    T1] initcall alarmtimer_init+0x0/0xe3 returned 0 after 16 usecs
[   27.248036][    T1] calling  init_posix_timers+0x0/0x2e @ 1
[   27.254375][    T1] initcall init_posix_timers+0x0/0x2e returned 0 after 4 usecs
[   27.262776][    T1] calling  clockevents_init_sysfs+0x0/0xcc @ 1
[   27.270752][    T1] initcall clockevents_init_sysfs+0x0/0xcc returned 0 after 1155 usecs
[   27.279935][    T1] calling  proc_dma_init+0x0/0x26 @ 1
[   27.285883][    T1] initcall proc_dma_init+0x0/0x26 returned 0 after 4 usecs
[   27.293867][    T1] calling  kallsyms_init+0x0/0x26 @ 1
[   27.299813][    T1] initcall kallsyms_init+0x0/0x26 returned 0 after 2 usecs
[   27.307791][    T1] calling  pid_namespaces_init+0x0/0x31 @ 1
[   27.314338][    T1] initcall pid_namespaces_init+0x0/0x31 returned 0 after 17 usecs
[   27.323032][    T1] calling  ikconfig_init+0x0/0x46 @ 1
[   27.328978][    T1] initcall ikconfig_init+0x0/0x46 returned 0 after 2 usecs
[   27.336956][    T1] calling  audit_watch_init+0x0/0x40 @ 1
[   27.343196][    T1] initcall audit_watch_init+0x0/0x40 returned 0 after 4 usecs
[   27.351506][    T1] calling  audit_fsnotify_init+0x0/0x43 @ 1
[   27.358033][    T1] initcall audit_fsnotify_init+0x0/0x43 returned 0 after 0 usecs
[   27.366629][    T1] calling  audit_tree_init+0x0/0x74 @ 1
[   27.372771][    T1] initcall audit_tree_init+0x0/0x74 returned 0 after 2 usecs
[   27.380978][    T1] calling  seccomp_sysctl_init+0x0/0x30 @ 1
[   27.387515][    T1] initcall seccomp_sysctl_init+0x0/0x30 returned 0 after 9 usecs
[   27.396103][    T1] calling  utsname_sysctl_init+0x0/0x18 @ 1
[   27.402638][    T1] initcall utsname_sysctl_init+0x0/0x18 returned 0 after 8 usecs
[   27.411235][    T1] calling  init_tracepoints+0x0/0x30 @ 1
[   27.417478][    T1] initcall init_tracepoints+0x0/0x30 returned 0 after 5 usecs
[   27.425793][    T1] calling  init_lstats_procfs+0x0/0x40 @ 1
[   27.432233][    T1] initcall init_lstats_procfs+0x0/0x40 returned 0 after 9 usecs
[   27.440724][    T1] calling  stack_trace_init+0x0/0xa8 @ 1
[   27.447003][    T1] initcall stack_trace_init+0x0/0xa8 returned 0 after 42 usecs
[   27.455408][    T1] calling  perf_event_sysfs_init+0x0/0x8a @ 1
[   27.462252][    T1] initcall perf_event_sysfs_init+0x0/0x8a returned 0 after 119 usecs
[   27.471242][    T1] calling  system_trusted_keyring_init+0x0/0x65 @ 1
[   27.478546][    T1] Initialise system trusted keyrings
[   27.484397][    T1] initcall system_trusted_keyring_init+0x0/0x65 returned 0 after 5851 usecs
[   27.494062][    T1] calling  blacklist_init+0x0/0xcc @ 1
[   27.500102][    T1] Key type blacklist registered
[   27.505464][    T1] initcall blacklist_init+0x0/0xcc returned 0 after 5363 usecs
[   27.513866][    T1] calling  kswapd_init+0x0/0x64 @ 1
[   27.519776][    T1] initcall kswapd_init+0x0/0x64 returned 0 after 162 usecs
[   27.527771][    T1] calling  extfrag_debug_init+0x0/0x5b @ 1
[   27.534208][    T1] initcall extfrag_debug_init+0x0/0x5b returned 0 after 7 usecs
[   27.542708][    T1] calling  mm_compute_batch_init+0x0/0x23 @ 1
[   27.549430][    T1] initcall mm_compute_batch_init+0x0/0x23 returned 0 after 1 usecs
[   27.558222][    T1] calling  slab_proc_init+0x0/0x26 @ 1
[   27.564263][    T1] initcall slab_proc_init+0x0/0x26 returned 0 after 1 usecs
[   27.572344][    T1] calling  workingset_init+0x0/0x9d @ 1
[   27.578482][    T1] workingset: timestamp_bits=36 max_order=23 bucket_order=0
[   27.586565][    T1] initcall workingset_init+0x0/0x9d returned 0 after 8083 usecs
[   27.595064][    T1] calling  proc_vmalloc_init+0x0/0x34 @ 1
[   27.601402][    T1] initcall proc_vmalloc_init+0x0/0x34 returned 0 after 6 usecs
[   27.609809][    T1] calling  procswaps_init+0x0/0x23 @ 1
[   27.615853][    T1] initcall procswaps_init+0x0/0x23 returned 0 after 1 usecs
[   27.623930][    T1] calling  init_frontswap+0x0/0x97 @ 1
[   27.629980][    T1] initcall init_frontswap+0x0/0x97 returned 0 after 9 usecs
[   27.638063][    T1] calling  slab_sysfs_init+0x0/0xf2 @ 1
[   27.645839][    T1] initcall slab_sysfs_init+0x0/0xf2 returned 0 after 1637 usecs
[   27.654332][    T1] calling  slab_debugfs_init+0x0/0x52 @ 1
[   27.660672][    T1] initcall slab_debugfs_init+0x0/0x52 returned 0 after 6 usecs
[   27.669073][    T1] calling  init_zbud+0x0/0x24 @ 1
[   27.674630][    T1] zbud: loaded
[   27.678336][    T1] initcall init_zbud+0x0/0x24 returned 0 after 3705 usecs
[   27.686224][    T1] calling  zs_init+0x0/0x77 @ 1
[   27.691651][    T1] initcall zs_init+0x0/0x77 returned 0 after 68 usecs
[   27.699156][    T1] calling  fcntl_init+0x0/0x2e @ 1
[   27.704817][    T1] initcall fcntl_init+0x0/0x2e returned 0 after 8 usecs
[   27.712512][    T1] calling  proc_filesystems_init+0x0/0x26 @ 1
[   27.719239][    T1] initcall proc_filesystems_init+0x0/0x26 returned 0 after 3 usecs
[   27.728028][    T1] calling  start_dirtytime_writeback+0x0/0x1b @ 1
[   27.735141][    T1] initcall start_dirtytime_writeback+0x0/0x1b returned 0 after 0 usecs
[   27.744320][    T1] calling  dio_init+0x0/0x31 @ 1
[   27.749780][    T1] initcall dio_init+0x0/0x31 returned 0 after 1 usecs
[   27.757279][    T1] calling  dnotify_init+0x0/0x9c @ 1
[   27.763204][    T1] initcall dnotify_init+0x0/0x9c returned 0 after 78 usecs
[   27.771186][    T1] calling  fanotify_user_setup+0x0/0x141 @ 1
[   27.777817][    T1] initcall fanotify_user_setup+0x0/0x141 returned 0 after 7 usecs
[   27.786509][    T1] calling  aio_setup+0x0/0x97 @ 1
[   27.792124][    T1] initcall aio_setup+0x0/0x97 returned 0 after 62 usecs
[   27.799820][    T1] calling  mbcache_init+0x0/0x35 @ 1
[   27.805776][    T1] initcall mbcache_init+0x0/0x35 returned 0 after 110 usecs
[   27.813862][    T1] calling  init_grace+0x0/0x11 @ 1
[   27.819514][    T1] initcall init_grace+0x0/0x11 returned 0 after 2 usecs
[   27.827207][    T1] calling  init_v2_quota_format+0x0/0x26 @ 1
[   27.833833][    T1] initcall init_v2_quota_format+0x0/0x26 returned 0 after 0 usecs
[   27.842525][    T1] calling  init_devpts_fs+0x0/0x30 @ 1
[   27.848590][    T1] initcall init_devpts_fs+0x0/0x30 returned 0 after 22 usecs
[   27.856807][    T1] calling  ext4_init_fs+0x0/0x18e @ 1
[   27.863100][    T1] initcall ext4_init_fs+0x0/0x18e returned 0 after 348 usecs
[   27.871308][    T1] calling  journal_init+0x0/0x132 @ 1
[   27.877337][    T1] initcall journal_init+0x0/0x132 returned 0 after 86 usecs
[   27.885422][    T1] calling  init_nfs_fs+0x0/0x161 @ 1
[   27.891582][    T1] initcall init_nfs_fs+0x0/0x161 returned 0 after 313 usecs
[   27.899669][    T1] calling  init_nfs_v3+0x0/0x18 @ 1
[   27.902707][    T7] tsc: Refined TSC clocksource calibration: 2493.987 MHz
[   27.905309][    T1] initcall init_nfs_v3+0x0/0x18 returned 0 after 1 usecs
[   27.905312][    T1] calling  init_nlm+0x0/0x66 @ 1
[   27.913051][    T7] clocksource: tsc: mask: 0xffffffffffffffff max_cycles: 0x23f30999899, max_idle_ns: 440795236616 ns
[   27.920679][    T1] initcall init_nlm+0x0/0x66 returned 0 after 18 usecs
[   27.946160][    T1] calling  init_nls_cp437+0x0/0x13 @ 1
[   27.952204][    T1] initcall init_nls_cp437+0x0/0x13 returned 0 after 1 usecs
[   27.960290][    T1] calling  init_nls_ascii+0x0/0x13 @ 1
[   27.966334][    T1] initcall init_nls_ascii+0x0/0x13 returned 0 after 0 usecs
[   27.974418][    T1] calling  init_autofs_fs+0x0/0x2e @ 1
[   27.980535][    T7] clocksource: Switched to clocksource tsc
[   27.980589][    T1] initcall init_autofs_fs+0x0/0x2e returned 0 after 127 usecs
[   27.995277][    T1] calling  efivarfs_init+0x0/0x25 @ 1
[   28.001227][    T1] initcall efivarfs_init+0x0/0x25 returned -19 after 0 usecs
[   28.009433][    T1] calling  ipc_init+0x0/0x29 @ 1
[   28.014936][    T1] initcall ipc_init+0x0/0x29 returned 0 after 43 usecs
[   28.022537][    T1] calling  ipc_sysctl_init+0x0/0x31 @ 1
[   28.028709][    T1] initcall ipc_sysctl_init+0x0/0x31 returned 0 after 35 usecs
[   28.037012][    T1] calling  init_mqueue_fs+0x0/0xb4 @ 1
[   28.043199][    T1] initcall init_mqueue_fs+0x0/0xb4 returned 0 after 148 usecs
[   28.051504][    T1] calling  key_proc_init+0x0/0x68 @ 1
[   28.057449][    T1] initcall key_proc_init+0x0/0x68 returned 0 after 1 usecs
[   28.065433][    T1] calling  apparmor_nf_ip_init+0x0/0x33 @ 1
[   28.072099][    T1] initcall apparmor_nf_ip_init+0x0/0x33 returned 0 after 137 usecs
[   28.080881][    T1] calling  jent_mod_init+0x0/0x32 @ 1
[   28.096795][    T1] initcall jent_mod_init+0x0/0x32 returned 0 after 9969 usecs
[   28.105107][    T1] calling  af_alg_init+0x0/0x45 @ 1
[   28.110858][    T1] NET: Registered PF_ALG protocol family
[   28.117091][    T1] initcall af_alg_init+0x0/0x45 returned 0 after 6233 usecs
[   28.125174][    T1] calling  algif_hash_init+0x0/0x11 @ 1
[   28.131314][    T1] initcall algif_hash_init+0x0/0x11 returned 0 after 0 usecs
[   28.139521][    T1] calling  algif_skcipher_init+0x0/0x11 @ 1
[   28.146049][    T1] initcall algif_skcipher_init+0x0/0x11 returned 0 after 0 usecs
[   28.163776][    T1] calling  rng_init+0x0/0x11 @ 1
[   28.169242][    T1] initcall rng_init+0x0/0x11 returned 0 after 7 usecs
[   28.176746][    T1] calling  algif_aead_init+0x0/0x11 @ 1
[   28.182884][    T1] initcall algif_aead_init+0x0/0x11 returned 0 after 0 usecs
[   28.191089][    T1] calling  asymmetric_key_init+0x0/0x11 @ 1
[   28.197617][    T1] Key type asymmetric registered
[   28.203073][    T1] initcall asymmetric_key_init+0x0/0x11 returned 0 after 5457 usecs
[   28.211961][    T1] calling  x509_key_init+0x0/0x1d @ 1
[   28.217906][    T1] Asymmetric key parser 'x509' registered
[   28.224239][    T1] initcall x509_key_init+0x0/0x1d returned 0 after 6333 usecs
[   28.232547][    T1] calling  blkdev_init+0x0/0x20 @ 1
[   28.238333][    T1] initcall blkdev_init+0x0/0x20 returned 0 after 43 usecs
[   28.246220][    T1] calling  proc_genhd_init+0x0/0x46 @ 1
[   28.252363][    T1] initcall proc_genhd_init+0x0/0x46 returned 0 after 3 usecs
[   28.260568][    T1] calling  bsg_init+0x0/0xb3 @ 1
[   28.266033][    T1] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 247)
[   28.275210][    T1] initcall bsg_init+0x0/0xb3 returned 0 after 9183 usecs
[   28.283000][    T1] calling  throtl_init+0x0/0x3c @ 1
[   28.288906][    T1] initcall throtl_init+0x0/0x3c returned 0 after 155 usecs
[   28.296895][    T1] calling  deadline_init+0x0/0x11 @ 1
[   28.302840][    T1] io scheduler mq-deadline registered
[   28.308784][    T1] initcall deadline_init+0x0/0x11 returned 0 after 5945 usecs
[   28.317087][    T1] calling  kyber_init+0x0/0x11 @ 1
[   28.322740][    T1] io scheduler kyber registered
[   28.328097][    T1] initcall kyber_init+0x0/0x11 returned 0 after 5357 usecs
[   28.336082][    T1] calling  bfq_init+0x0/0x8f @ 1
[   28.341643][    T1] io scheduler bfq registered
[   28.346813][    T1] initcall bfq_init+0x0/0x8f returned 0 after 5273 usecs
[   28.354605][    T1] calling  io_uring_init+0x0/0x36 @ 1
[   28.360550][    T1] initcall io_uring_init+0x0/0x36 returned 0 after 3 usecs
[   28.368535][    T1] calling  blake2s_mod_init+0x0/0xc @ 1
[   28.374675][    T1] initcall blake2s_mod_init+0x0/0xc returned 0 after 0 usecs
[   28.382873][    T1] calling  crc_t10dif_mod_init+0x0/0x50 @ 1
[   28.389560][    T1] initcall crc_t10dif_mod_init+0x0/0x50 returned 0 after 160 usecs
[   28.398358][    T1] calling  percpu_counter_startup+0x0/0x55 @ 1
[   28.406388][    T1] initcall percpu_counter_startup+0x0/0x55 returned 0 after 1206 usecs
[   28.415575][    T1] calling  digsig_init+0x0/0x3d @ 1
[   28.421404][    T1] initcall digsig_init+0x0/0x3d returned 0 after 77 usecs
[   28.429299][    T1] calling  pcie_portdrv_init+0x0/0x4d @ 1
[   28.435802][    T1] IOAPIC[1]: Preconfigured routing entry (9-23 -> IRQ 24 Level:1 ActiveLow:1)
[   28.445789][    T1] pcieport 0000:00:02.0: PME: Signaling with IRQ 25
[   28.453190][    T1] pcieport 0000:00:02.0: AER: enabled with IRQ 25
[   28.460509][    T1] pcieport 0000:00:03.0: PME: Signaling with IRQ 26
[   28.467884][    T1] pcieport 0000:00:03.0: AER: enabled with IRQ 26
[   28.475187][    T1] pcieport 0000:00:03.2: PME: Signaling with IRQ 27
[   28.482582][    T1] pcieport 0000:00:03.2: AER: enabled with IRQ 27
[   28.489895][    T1] pcieport 0000:00:03.3: PME: Signaling with IRQ 28
[   28.497287][    T1] pcieport 0000:00:03.3: AER: enabled with IRQ 28
[   28.504569][    T1] IOAPIC[0]: Preconfigured routing entry (8-19 -> IRQ 19 Level:1 ActiveLow:1)
[   28.514562][    T1] pcieport 0000:00:11.0: PME: Signaling with IRQ 29
[   28.521957][    T1] pcieport 0000:00:11.0: AER: enabled with IRQ 29
[   28.529204][    T1] IOAPIC[0]: Preconfigured routing entry (8-16 -> IRQ 16 Level:1 ActiveLow:1)
[   28.539156][    T1] pcieport 0000:00:1c.0: PME: Signaling with IRQ 30
[   28.546684][    T1] pcieport 0000:00:1c.7: PME: Signaling with IRQ 31
[   28.554114][    T1] IOAPIC[2]: Preconfigured routing entry (10-23 -> IRQ 32 Level:1 ActiveLow:1)
[   28.564208][    T1] pcieport 0000:40:02.0: PME: Signaling with IRQ 33
[   28.571606][    T1] pcieport 0000:40:02.0: AER: enabled with IRQ 33
[   28.578746][    T1] pcieport 0000:40:02.0: pciehp: Slot #5 AttnBtn+ PwrCtrl+ MRL- AttnInd+ PwrInd+ HotPlug+ Surprise- Interlock- NoCompl- IbPresDis- LLActRep+ (with Cmd Compl erratum)
[   28.597439][    T1] pcieport 0000:40:02.2: PME: Signaling with IRQ 34
[   28.604831][    T1] pcieport 0000:40:02.2: AER: enabled with IRQ 34
[   28.611973][    T1] pcieport 0000:40:02.2: pciehp: Slot #7 AttnBtn+ PwrCtrl+ MRL- AttnInd+ PwrInd+ HotPlug+ Surprise- Interlock- NoCompl- IbPresDis- LLActRep+ (with Cmd Compl erratum)
[   28.630696][    T1] pcieport 0000:40:03.0: PME: Signaling with IRQ 35
[   28.638086][    T1] pcieport 0000:40:03.0: AER: enabled with IRQ 35
[   28.645420][    T1] IOAPIC[3]: Preconfigured routing entry (11-23 -> IRQ 36 Level:1 ActiveLow:1)
[   28.655532][    T1] pcieport 0000:80:02.0: PME: Signaling with IRQ 37
[   28.662911][    T1] pcieport 0000:80:02.0: AER: enabled with IRQ 37
[   28.670220][    T1] pcieport 0000:80:02.2: PME: Signaling with IRQ 38
[   28.677602][    T1] pcieport 0000:80:02.2: AER: enabled with IRQ 38
[   28.684920][    T1] pcieport 0000:80:03.0: PME: Signaling with IRQ 39
[   28.692291][    T1] pcieport 0000:80:03.0: AER: enabled with IRQ 39
[   28.699531][    T1] IOAPIC[4]: Preconfigured routing entry (12-23 -> IRQ 40 Level:1 ActiveLow:1)
[   28.709594][    T1] pcieport 0000:c0:02.0: PME: Signaling with IRQ 41
[   28.716969][    T1] pcieport 0000:c0:02.0: AER: enabled with IRQ 41
[   28.724121][    T1] pcieport 0000:c0:02.0: pciehp: Slot #12 AttnBtn+ PwrCtrl+ MRL- AttnInd+ PwrInd+ HotPlug+ Surprise- Interlock- NoCompl- IbPresDis- LLActRep+ (with Cmd Compl erratum)
[   28.742976][    T1] pcieport 0000:c0:02.2: PME: Signaling with IRQ 42
[   28.750362][    T1] pcieport 0000:c0:02.2: AER: enabled with IRQ 42
[   28.757502][    T1] pcieport 0000:c0:02.2: pciehp: Slot #10 AttnBtn+ PwrCtrl+ MRL- AttnInd+ PwrInd+ HotPlug+ Surprise- Interlock- NoCompl- IbPresDis- LLActRep+ (with Cmd Compl erratum)
[   28.776369][    T1] pcieport 0000:c0:03.0: PME: Signaling with IRQ 43
[   28.783758][    T1] pcieport 0000:c0:03.0: AER: enabled with IRQ 43
[   28.790949][    T1] initcall pcie_portdrv_init+0x0/0x4d returned 0 after 355318 usecs
[   28.799851][    T1] calling  pci_proc_init+0x0/0x70 @ 1
[   28.806331][    T1] initcall pci_proc_init+0x0/0x70 returned 0 after 528 usecs
[   28.814542][    T1] calling  pci_hotplug_init+0x0/0xc @ 1
[   28.820674][    T1] initcall pci_hotplug_init+0x0/0xc returned 0 after 0 usecs
[   28.828887][    T1] calling  shpcd_init+0x0/0x61 @ 1
[   28.834656][    T1] shpchp: Standard Hot Plug PCI Controller Driver version: 0.4
[   28.843060][    T1] initcall shpcd_init+0x0/0x61 returned 0 after 8520 usecs
[   28.851050][    T1] calling  pci_stub_init+0x0/0x178 @ 1
[   28.857194][    T1] initcall pci_stub_init+0x0/0x178 returned 0 after 99 usecs
[   28.865406][    T1] calling  vmd_drv_init+0x0/0x1a @ 1
[   28.871341][    T1] initcall vmd_drv_init+0x0/0x1a returned 0 after 88 usecs
[   28.879326][    T1] calling  vesafb_driver_init+0x0/0x13 @ 1
[   28.885766][    T1] initcall vesafb_driver_init+0x0/0x13 returned 0 after 7 usecs
[   28.894254][    T1] calling  efifb_driver_init+0x0/0x13 @ 1
[   28.900591][    T1] initcall efifb_driver_init+0x0/0x13 returned 0 after 5 usecs
[   28.908992][    T1] calling  intel_idle_init+0x0/0x2a3 @ 1
[   28.915279][    T7] Monitor-Mwait will be used to enter C-1 state
[   28.922203][    T7] Monitor-Mwait will be used to enter C-2 state
[   28.929125][    T1] ACPI: \_SB_.SCK0.CP00: Found 2 idle states
[   28.943924][    T1] initcall intel_idle_init+0x0/0x2a3 returned 0 after 28697 usecs
[   28.952644][    T1] calling  ged_driver_init+0x0/0x13 @ 1
[   28.958796][    T1] initcall ged_driver_init+0x0/0x13 returned 0 after 14 usecs
[   28.967099][    T1] calling  acpi_ac_init+0x0/0x48 @ 1
[   28.973164][    T1] initcall acpi_ac_init+0x0/0x48 returned 0 after 207 usecs
[   28.981248][    T1] calling  acpi_button_driver_init+0x0/0x57 @ 1
[   28.988262][    T1] input: Sleep Button as /devices/LNXSYSTM:00/LNXSYBUS:00/PNP0C0E:00/input/input0
[   28.998627][    T1] ACPI: button: Sleep Button [SLPB]
[   29.004432][    T1] input: Power Button as /devices/LNXSYSTM:00/LNXPWRBN:00/input/input1
[   29.013766][    T1] ACPI: button: Power Button [PWRF]
[   29.019537][    T1] initcall acpi_button_driver_init+0x0/0x57 returned 0 after 31374 usecs
[   29.028916][    T1] calling  acpi_fan_driver_init+0x0/0x13 @ 1
[   29.035558][    T1] initcall acpi_fan_driver_init+0x0/0x13 returned 0 after 15 usecs
[   29.044351][    T1] calling  acpi_processor_driver_init+0x0/0xbb @ 1
[   29.065501][    T1] initcall acpi_processor_driver_init+0x0/0xbb returned 0 after 13938 usecs
[   29.075174][    T1] calling  acpi_thermal_init+0x0/0x86 @ 1
[   29.081805][    T1] initcall acpi_thermal_init+0x0/0x86 returned 0 after 299 usecs
[   29.090405][    T1] calling  acpi_battery_init+0x0/0x3d @ 1
[   29.096741][    T1] initcall acpi_battery_init+0x0/0x3d returned 0 after 2 usecs
[   29.105141][    T1] calling  acpi_hed_driver_init+0x0/0x11 @ 1
[   29.111814][    T1] initcall acpi_hed_driver_init+0x0/0x11 returned 0 after 42 usecs
[   29.120604][    T1] calling  bgrt_init+0x0/0xc2 @ 1
[   29.126159][    T1] initcall bgrt_init+0x0/0xc2 returned -19 after 0 usecs
[   29.133948][    T1] calling  erst_init+0x0/0x2fa @ 1
[   29.139602][    T1] initcall erst_init+0x0/0x2fa returned 0 after 2 usecs
[   29.147295][    T1] calling  gpio_clk_driver_init+0x0/0x13 @ 1
[   29.153927][    T1] initcall gpio_clk_driver_init+0x0/0x13 returned 0 after 6 usecs
[   29.162619][    T1] calling  plt_clk_driver_init+0x0/0x13 @ 1
[   29.169153][    T1] initcall plt_clk_driver_init+0x0/0x13 returned 0 after 7 usecs
[   29.177749][    T1] calling  dw_pci_driver_init+0x0/0x1a @ 1
[   29.184227][    T1] initcall dw_pci_driver_init+0x0/0x1a returned 0 after 48 usecs
[   29.192825][    T1] calling  virtio_pci_driver_init+0x0/0x1a @ 1
[   29.199701][    T1] initcall virtio_pci_driver_init+0x0/0x1a returned 0 after 53 usecs
[   29.208703][    T1] calling  n_null_init+0x0/0x1e @ 1
[   29.214462][    T1] initcall n_null_init+0x0/0x1e returned 0 after 0 usecs
[   29.222252][    T1] calling  pty_init+0x0/0x11 @ 1
[   29.236946][    T1] initcall pty_init+0x0/0x11 returned 0 after 60 usecs
[   29.244546][    T1] calling  sysrq_init+0x0/0x4e @ 1
[   29.250201][    T1] initcall sysrq_init+0x0/0x4e returned 0 after 3 usecs
[   29.257901][    T1] calling  serial8250_init+0x0/0x18c @ 1
[   29.264126][    T1] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
[   29.272099][    T1] 00:02: ttyS0 at I/O 0x3f8 (irq = 4, base_baud = 115200) is a 16550A
[   29.281326][    T1] 00:03: ttyS1 at I/O 0x2f8 (irq = 3, base_baud = 115200) is a 16550A
[   29.290599][    T1] initcall serial8250_init+0x0/0x18c returned 0 after 26472 usecs
[   29.299297][    T1] calling  serial_pci_driver_init+0x0/0x1a @ 1
[   29.306277][    T1] initcall serial_pci_driver_init+0x0/0x1a returned 0 after 156 usecs
[   29.315359][    T1] calling  exar_pci_driver_init+0x0/0x1a @ 1
[   29.322059][    T1] initcall exar_pci_driver_init+0x0/0x1a returned 0 after 73 usecs
[   29.330858][    T1] calling  dw8250_platform_driver_init+0x0/0x13 @ 1
[   29.338178][    T1] initcall dw8250_platform_driver_init+0x0/0x13 returned 0 after 15 usecs
[   29.347650][    T1] calling  lpss8250_pci_driver_init+0x0/0x1a @ 1
[   29.354707][    T1] initcall lpss8250_pci_driver_init+0x0/0x1a returned 0 after 46 usecs
[   29.363886][    T1] calling  mid8250_pci_driver_init+0x0/0x1a @ 1
[   29.370842][    T1] initcall mid8250_pci_driver_init+0x0/0x1a returned 0 after 39 usecs
[   29.379927][    T1] calling  pericom8250_pci_driver_init+0x0/0x1a @ 1
[   29.387289][    T1] initcall pericom8250_pci_driver_init+0x0/0x1a returned 0 after 53 usecs
[   29.396761][    T1] calling  random_sysctls_init+0x0/0x26 @ 1
[   29.403296][    T1] initcall random_sysctls_init+0x0/0x26 returned 0 after 7 usecs
[   29.411891][    T1] calling  hpet_init+0x0/0x76 @ 1
[   29.417618][    T1] initcall hpet_init+0x0/0x76 returned 0 after 173 usecs
[   29.425419][    T1] calling  nvram_module_init+0x0/0x8d @ 1
[   29.431839][    T1] Non-volatile memory driver v1.3
[   29.437397][    T1] initcall nvram_module_init+0x0/0x8d returned 0 after 5644 usecs
[   29.446094][    T1] calling  virtio_rng_driver_init+0x0/0x11 @ 1
[   29.452977][    T1] initcall virtio_rng_driver_init+0x0/0x11 returned 0 after 65 usecs
[   29.461961][    T1] calling  init_tis+0x0/0xe2 @ 1
[   29.476773][    T1] tpm_tis 00:04: 1.2 TPM (device-id 0x0, rev-id 78)
[   29.496658][    T1] tpm tpm0: [Hardware Error]: Adjusting reported durations.
[   29.524775][    T1] tpm tpm0: TPM is disabled/deactivated (0x6)
[   29.531506][    T1] tpm tpm0: tpm_read_log_acpi: TCPA log area empty
[   29.543953][    T1] initcall init_tis+0x0/0xe2 returned 0 after 76536 usecs
[   29.551863][    T1] calling  crb_acpi_driver_init+0x0/0x11 @ 1
[   29.558691][    T1] initcall crb_acpi_driver_init+0x0/0x11 returned 0 after 202 usecs
[   29.567581][    T1] calling  cn_proc_init+0x0/0x3e @ 1
[   29.573429][    T1] initcall cn_proc_init+0x0/0x3e returned 0 after 2 usecs
[   29.581316][    T1] calling  topology_sysfs_init+0x0/0x2c @ 1
[   29.589142][    T1] initcall topology_sysfs_init+0x0/0x2c returned 0 after 1299 usecs
[   29.598031][    T1] calling  cacheinfo_sysfs_init+0x0/0x2c @ 1
[   29.617629][    T1] initcall cacheinfo_sysfs_init+0x0/0x2c returned 0 after 12973 usecs
[   29.626725][    T1] calling  lpc_ich_driver_init+0x0/0x1a @ 1
[   29.633548][    T1] initcall lpc_ich_driver_init+0x0/0x1a returned 0 after 295 usecs
[   29.642340][    T1] calling  intel_lpss_init+0x0/0x21 @ 1
[   29.648485][    T1] initcall intel_lpss_init+0x0/0x21 returned 0 after 7 usecs
[   29.656692][    T1] calling  intel_lpss_pci_driver_init+0x0/0x1a @ 1
[   29.664057][    T1] initcall intel_lpss_pci_driver_init+0x0/0x1a returned 0 after 155 usecs
[   29.673528][    T1] calling  intel_lpss_acpi_driver_init+0x0/0x13 @ 1
[   29.680852][    T1] initcall intel_lpss_acpi_driver_init+0x0/0x13 returned 0 after 14 usecs
[   29.690323][    T1] calling  mac_hid_init+0x0/0x2d @ 1
[   29.696186][    T1] initcall mac_hid_init+0x0/0x2d returned 0 after 15 usecs
[   29.704172][    T1] calling  rdac_init+0x0/0x79 @ 1
[   29.709729][    T1] rdac: device handler registered
[   29.715449][    T1] initcall rdac_init+0x0/0x79 returned 0 after 5720 usecs
[   29.723353][    T1] calling  hp_sw_init+0x0/0x11 @ 1
[   29.729004][    T1] hp_sw: device handler registered
[   29.734654][    T1] initcall hp_sw_init+0x0/0x11 returned 0 after 5650 usecs
[   29.742640][    T1] calling  clariion_init+0x0/0x37 @ 1
[   29.748586][    T1] emc: device handler registered
[   29.754040][    T1] initcall clariion_init+0x0/0x37 returned 0 after 5454 usecs
[   29.762347][    T1] calling  alua_init+0x0/0x68 @ 1
[   29.768150][    T1] alua: device handler registered
[   29.773720][    T1] initcall alua_init+0x0/0x68 returned 0 after 5819 usecs
[   29.781610][    T1] calling  blackhole_netdev_init+0x0/0x80 @ 1
[   29.788367][    T1] initcall blackhole_netdev_init+0x0/0x80 returned 0 after 33 usecs
[   29.797253][    T1] calling  phylink_init+0x0/0x3b @ 1
[   29.803099][    T1] initcall phylink_init+0x0/0x3b returned 0 after 0 usecs
[   29.810986][    T1] calling  phy_module_init+0x0/0x18 @ 1
[   29.817146][    T1] initcall phy_module_init+0x0/0x18 returned 0 after 22 usecs
[   29.825459][    T1] calling  fixed_mdio_bus_init+0x0/0x10d @ 1
[   29.832190][    T1] initcall fixed_mdio_bus_init+0x0/0x10d returned 0 after 107 usecs
[   29.841077][    T1] calling  phy_module_init+0x0/0x18 @ 1
[   29.847288][    T1] initcall phy_module_init+0x0/0x18 returned 0 after 71 usecs
[   29.855592][    T1] calling  cavium_ptp_driver_init+0x0/0x1a @ 1
[   29.862517][    T1] initcall cavium_ptp_driver_init+0x0/0x1a returned 0 after 107 usecs
[   29.871624][    T1] calling  e1000_init_module+0x0/0x7b @ 1
[   29.877956][    T1] e1000: Intel(R) PRO/1000 Network Driver
[   29.884285][    T1] e1000: Copyright (c) 1999-2006 Intel Corporation.
[   29.891645][    T1] initcall e1000_init_module+0x0/0x7b returned 0 after 13689 usecs
[   29.900436][    T1] calling  e1000_init_module+0x0/0x32 @ 1
[   29.906766][    T1] e1000e: Intel(R) PRO/1000 Network Driver
[   29.913192][    T1] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
[   29.920775][    T1] initcall e1000_init_module+0x0/0x32 returned 0 after 14008 usecs
[   29.929557][    T1] calling  igb_init_module+0x0/0x40 @ 1
[   29.935693][    T1] igb: Intel(R) Gigabit Ethernet Network Driver
[   29.942607][    T1] igb: Copyright (c) 2007-2014 Intel Corporation.
[   29.949770][    T1] initcall igb_init_module+0x0/0x40 returned 0 after 14076 usecs
[   29.958364][    T1] calling  igc_init_module+0x0/0x40 @ 1
[   29.964499][    T1] Intel(R) 2.5G Ethernet Linux Driver
[   29.970440][    T1] Copyright(c) 2018 Intel Corporation.
[   29.976563][    T1] initcall igc_init_module+0x0/0x40 returned 0 after 12063 usecs
[   29.985182][    T1] calling  ixgbe_init_module+0x0/0xad @ 1
[   29.991505][    T1] ixgbe: Intel(R) 10 Gigabit PCI Express Network Driver
[   29.999195][    T1] ixgbe: Copyright (c) 1999-2016 Intel Corporation.
[   30.006768][    T1] IOAPIC[1]: Preconfigured routing entry (9-21 -> IRQ 44 Level:1 ActiveLow:1)
[   30.280946][    T1] ixgbe 0000:03:00.0: Multiqueue Enabled: Rx Queue count = 63, Tx Queue count = 63 XDP Queue count = 0
[   30.378091][    T1] ixgbe 0000:03:00.0: 16.000 Gb/s available PCIe bandwidth, limited by 5.0 GT/s PCIe x4 link at 0000:00:03.2 (capable of 32.000 Gb/s with 5.0 GT/s PCIe x8 link)
[   30.493083][    T1] ixgbe 0000:03:00.0: MAC: 3, PHY: 0, PBA No: G36748-004
[   30.500889][    T1] ixgbe 0000:03:00.0: a0:36:9f:18:d6:a8
[   30.655442][    T1] ixgbe 0000:03:00.0: Intel(R) 10 Gigabit Network Connection
[   30.663817][    T1] IOAPIC[1]: Preconfigured routing entry (9-18 -> IRQ 109 Level:1 ActiveLow:1)
[   30.935001][    T1] ixgbe 0000:03:00.1: Multiqueue Enabled: Rx Queue count = 63, Tx Queue count = 63 XDP Queue count = 0
[   31.031958][    T1] ixgbe 0000:03:00.1: 16.000 Gb/s available PCIe bandwidth, limited by 5.0 GT/s PCIe x4 link at 0000:00:03.2 (capable of 32.000 Gb/s with 5.0 GT/s PCIe x8 link)
[   31.146907][    T1] ixgbe 0000:03:00.1: MAC: 3, PHY: 0, PBA No: G36748-004
[   31.154704][    T1] ixgbe 0000:03:00.1: a0:36:9f:18:d6:aa
[   31.309548][    T1] ixgbe 0000:03:00.1: Intel(R) 10 Gigabit Network Connection
[   31.317870][    T1] initcall ixgbe_init_module+0x0/0xad returned 0 after 1326365 usecs
[   31.326855][    T1] calling  i40e_init_module+0x0/0x96 @ 1
[   31.333088][    T1] i40e: Intel(R) Ethernet Connection XL710 Network Driver
[   31.340974][    T1] i40e: Copyright (c) 2013 - 2019 Intel Corporation.
[   31.348696][    T1] initcall i40e_init_module+0x0/0x96 returned 0 after 15608 usecs
[   31.357402][    T1] calling  rtl8169_pci_driver_init+0x0/0x1a @ 1
[   31.364364][    T1] initcall rtl8169_pci_driver_init+0x0/0x1a returned 0 after 43 usecs
[   31.373444][    T1] calling  rtl8152_driver_init+0x0/0x1a @ 1
[   31.379988][    T1] usbcore: registered new interface driver r8152
[   31.386998][    T1] initcall rtl8152_driver_init+0x0/0x1a returned 0 after 7027 usecs
[   31.395884][    T1] calling  asix_driver_init+0x0/0x1a @ 1
[   31.402139][    T1] usbcore: registered new interface driver asix
[   31.409069][    T1] initcall asix_driver_init+0x0/0x1a returned 0 after 6949 usecs
[   31.417662][    T1] calling  ax88179_178a_driver_init+0x0/0x1a @ 1
[   31.424730][    T1] usbcore: registered new interface driver ax88179_178a
[   31.432426][    T1] initcall ax88179_178a_driver_init+0x0/0x1a returned 0 after 7747 usecs
[   31.441800][    T1] calling  usbnet_init+0x0/0x2f @ 1
[   31.447549][    T1] initcall usbnet_init+0x0/0x2f returned 0 after 0 usecs
[   31.455340][    T1] calling  usbport_trig_init+0x0/0x11 @ 1
[   31.461670][    T1] initcall usbport_trig_init+0x0/0x11 returned 0 after 1 usecs
[   31.470069][    T1] calling  mon_init+0x0/0x133 @ 1
[   31.475737][    T1] initcall mon_init+0x0/0x133 returned 0 after 114 usecs
[   31.483532][    T1] calling  ehci_hcd_init+0x0/0xd7 @ 1
[   31.489550][    T1] initcall ehci_hcd_init+0x0/0xd7 returned 0 after 74 usecs
[   31.497657][    T1] calling  ehci_pci_init+0x0/0x56 @ 1
[   31.503901][    T1] ehci-pci 0000:00:1a.0: EHCI Host Controller
[   31.520005][    T1] ehci-pci 0000:00:1a.0: new USB bus registered, assigned bus number 1
[   31.529239][    T1] ehci-pci 0000:00:1a.0: debug port 2
[   31.539141][    T1] ehci-pci 0000:00:1a.0: irq 16, io mem 0x93402000
[   31.552760][    T1] ehci-pci 0000:00:1a.0: USB 2.0 started, EHCI 1.00
[   31.560121][    T1] usb usb1: New USB device found, idVendor=1d6b, idProduct=0002, bcdDevice= 6.01
[   31.570301][    T1] usb usb1: New USB device strings: Mfr=3, Product=2, SerialNumber=1
[   31.579285][    T1] usb usb1: Product: EHCI Host Controller
[   31.585615][    T1] usb usb1: Manufacturer: Linux 6.1.0-rc5-00020-g6919cda8e0f1 ehci_hcd
[   31.594792][    T1] usb usb1: SerialNumber: 0000:00:1a.0
[   31.600965][    T1] hub 1-0:1.0: USB hub found
[   31.606061][    T1] hub 1-0:1.0: 2 ports detected
[   31.611734][    T1] IOAPIC[0]: Preconfigured routing entry (8-23 -> IRQ 23 Level:1 ActiveLow:1)
[   31.621664][    T1] ehci-pci 0000:00:1d.0: EHCI Host Controller
[   31.628469][    T1] ehci-pci 0000:00:1d.0: new USB bus registered, assigned bus number 2
[   31.637682][    T1] ehci-pci 0000:00:1d.0: debug port 2
[   31.647551][    T1] ehci-pci 0000:00:1d.0: irq 23, io mem 0x93401000
[   31.661733][    T1] ehci-pci 0000:00:1d.0: USB 2.0 started, EHCI 1.00
[   31.669083][    T1] usb usb2: New USB device found, idVendor=1d6b, idProduct=0002, bcdDevice= 6.01
[   31.679239][    T1] usb usb2: New USB device strings: Mfr=3, Product=2, SerialNumber=1
[   31.688223][    T1] usb usb2: Product: EHCI Host Controller
[   31.694551][    T1] usb usb2: Manufacturer: Linux 6.1.0-rc5-00020-g6919cda8e0f1 ehci_hcd
[   31.703729][    T1] usb usb2: SerialNumber: 0000:00:1d.0
[   31.709949][    T1] hub 2-0:1.0: USB hub found
[   31.715040][    T1] hub 2-0:1.0: 2 ports detected
[   31.720532][    T1] initcall ehci_pci_init+0x0/0x56 returned 0 after 216927 usecs
[   31.729045][    T1] calling  ohci_hcd_mod_init+0x0/0x6e @ 1
[   31.735399][    T1] initcall ohci_hcd_mod_init+0x0/0x6e returned 0 after 23 usecs
[   31.743897][    T1] calling  ohci_pci_init+0x0/0x56 @ 1
[   31.749890][    T1] initcall ohci_pci_init+0x0/0x56 returned 0 after 50 usecs
[   31.757976][    T1] calling  uhci_hcd_init+0x0/0xe7 @ 1
[   31.763965][    T1] initcall uhci_hcd_init+0x0/0xe7 returned 0 after 46 usecs
[   31.772049][    T1] calling  xhci_hcd_init+0x0/0x28 @ 1
[   31.777994][    T1] initcall xhci_hcd_init+0x0/0x28 returned 0 after 1 usecs
[   31.785969][    T1] calling  xhci_pci_init+0x0/0x4e @ 1
[   31.791961][    T1] initcall xhci_pci_init+0x0/0x4e returned 0 after 48 usecs
[   31.800052][    T1] calling  ucsi_acpi_platform_driver_init+0x0/0x13 @ 1
[   31.807912][    T1] initcall ucsi_acpi_platform_driver_init+0x0/0x13 returned 0 after 269 usecs
[   31.817775][    T1] calling  i8042_init+0x0/0xea @ 1
[   31.823468][    T1] i8042: PNP: No PS/2 controller found.
[   31.829605][    T1] initcall i8042_init+0x0/0xea returned 0 after 6179 usecs
[   31.837591][    T1] calling  serport_init+0x0/0x30 @ 1
[   31.843436][    T1] initcall serport_init+0x0/0x30 returned 0 after 0 usecs
[   31.851324][    T1] calling  input_leds_init+0x0/0x11 @ 1
[   31.857491][    T1] initcall input_leds_init+0x0/0x11 returned 0 after 29 usecs
[   31.859726][    T7] usb 1-1: new high-speed USB device number 2 using ehci-pci
[   31.865660][    T1] calling  mousedev_init+0x0/0x63 @ 1
[   31.880046][    T1] mousedev: PS/2 mouse device common for all mice
[   31.887160][    T1] initcall mousedev_init+0x0/0x63 returned 0 after 7197 usecs
[   31.895466][    T1] calling  evdev_init+0x0/0x11 @ 1
[   31.901231][    T1] initcall evdev_init+0x0/0x11 returned 0 after 112 usecs
[   31.909126][    T1] calling  atkbd_init+0x0/0x26 @ 1
[   31.914785][    T1] initcall atkbd_init+0x0/0x26 returned 0 after 17 usecs
[   31.922576][    T1] calling  psmouse_init+0x0/0x8a @ 1
[   31.928523][    T1] initcall psmouse_init+0x0/0x8a returned 0 after 102 usecs
[   31.936623][    T1] calling  cmos_init+0x0/0x74 @ 1
[   31.942200][    T1] rtc_cmos 00:00: RTC can wake from S4
[   31.948568][    T1] rtc_cmos 00:00: registered as rtc0
[   31.954490][    T1] rtc_cmos 00:00: setting system clock to 2022-12-10T14:30:33 UTC (1670682633)
[   31.964479][    T1] rtc_cmos 00:00: alarms up to one month, y3k, 114 bytes nvram
[   31.972884][  T781] usb 2-1: new high-speed USB device number 2 using ehci-pci
[   31.981115][    T1] initcall cmos_init+0x0/0x74 returned 0 after 38938 usecs
[   31.989106][    T1] calling  smbalert_driver_init+0x0/0x13 @ 1
[   31.995747][    T1] initcall smbalert_driver_init+0x0/0x13 returned 0 after 14 usecs
[   32.002166][    T7] usb 1-1: New USB device found, idVendor=8087, idProduct=0024, bcdDevice= 0.00
[   32.004408][    T1] calling  i2c_i801_init+0x0/0xcb @ 1
[   32.014316][    T7] usb 1-1: New USB device strings: Mfr=0, Product=0, SerialNumber=0
[   32.014568][    T7] hub 1-1:1.0: USB hub found
[   32.020280][    T1] initcall i2c_i801_init+0x0/0xcb returned 0 after 117 usecs
[   32.020359][    T9] IOAPIC[0]: Preconfigured routing entry (8-18 -> IRQ 18 Level:1 ActiveLow:1)
[   32.020412][    T9] i801_smbus 0000:00:1f.3: SMBus using PCI interrupt
[   32.020926][    T9] i2c i2c-0: 48/96 memory slots populated (from DMI)
[   32.020929][    T9] i2c i2c-0: Systems with more than 4 memory slots not supported yet, not instantiating SPD
[   32.029056][    T7] hub 1-1:1.0: 6 ports detected
[   32.033878][    T1] calling  thermal_throttle_init_device+0x0/0x42 @ 1
[   32.097761][    T1] initcall thermal_throttle_init_device+0x0/0x42 returned 0 after 6362 usecs
[   32.107539][    T1] calling  esb_driver_init+0x0/0x1a @ 1
[   32.113746][    T1] initcall esb_driver_init+0x0/0x1a returned 0 after 62 usecs
[   32.122055][    T1] calling  iTCO_wdt_driver_init+0x0/0x13 @ 1
[   32.124181][  T781] usb 2-1: New USB device found, idVendor=8087, idProduct=0024, bcdDevice= 0.00
[   32.128606][    T1] iTCO_wdt iTCO_wdt.0.auto: unable to reset NO_REBOOT flag, device disabled by hardware/BIOS
[   32.138486][  T781] usb 2-1: New USB device strings: Mfr=0, Product=0, SerialNumber=0
[   32.138692][  T781] hub 2-1:1.0: USB hub found
[   32.149687][    T1] initcall iTCO_wdt_driver_init+0x0/0x13 returned 0 after 21118 usecs
[   32.163709][  T781] hub 2-1:1.0: 8 ports detected
[   32.172453][    T1] calling  iTCO_vendor_init_module+0x0/0x39 @ 1
[   32.185461][    T1] iTCO_vendor_support: vendor-support=0
[   32.191600][    T1] initcall iTCO_vendor_init_module+0x0/0x39 returned 0 after 6139 usecs
[   32.200879][    T1] calling  intel_pstate_init+0x0/0x384 @ 1
[   32.207329][    T1] intel_pstate: Intel P-state driver initializing
[   32.234370][    T1] initcall intel_pstate_init+0x0/0x384 returned 0 after 27058 usecs
[   32.243293][    T1] calling  haltpoll_init+0x0/0xcd @ 1
[   32.249238][    T1] initcall haltpoll_init+0x0/0xcd returned -19 after 0 usecs
[   32.257437][    T1] calling  dmi_sysfs_init+0x0/0xe3 @ 1
[   32.264098][    T1] initcall dmi_sysfs_init+0x0/0xe3 returned 0 after 620 usecs
[   32.272405][    T1] calling  fw_cfg_sysfs_init+0x0/0x64 @ 1
[   32.278770][    T1] initcall fw_cfg_sysfs_init+0x0/0x64 returned 0 after 31 usecs
[   32.287269][    T1] calling  sysfb_init+0x0/0xc7 @ 1
[   32.292964][    T1] initcall sysfb_init+0x0/0xc7 returned 0 after 40 usecs
[   32.300761][    T1] calling  esrt_sysfs_init+0x0/0x2e2 @ 1
[   32.306998][    T1] initcall esrt_sysfs_init+0x0/0x2e2 returned -38 after 0 usecs
[   32.315491][    T1] calling  efivars_pstore_init+0x0/0x87 @ 1
[   32.322033][    T1] initcall efivars_pstore_init+0x0/0x87 returned 0 after 0 usecs
[   32.330630][    T1] calling  hid_init+0x0/0x66 @ 1
[   32.336114][    T1] hid: raw HID events driver (C) Jiri Kosina
[   32.342772][    T1] initcall hid_init+0x0/0x66 returned 0 after 6684 usecs
[   32.350563][    T1] calling  hid_generic_init+0x0/0x1a @ 1
[   32.356819][    T1] initcall hid_generic_init+0x0/0x1a returned 0 after 18 usecs
[   32.365219][    T1] calling  magicmouse_driver_init+0x0/0x1a @ 1
[   32.372046][    T1] initcall magicmouse_driver_init+0x0/0x1a returned 0 after 7 usecs
[   32.380926][    T1] calling  sensor_hub_driver_init+0x0/0x1a @ 1
[   32.387754][    T1] initcall sensor_hub_driver_init+0x0/0x1a returned 0 after 8 usecs
[   32.396643][    T1] calling  hid_init+0x0/0x62 @ 1
[   32.402146][    T1] usbcore: registered new interface driver usbhid
[   32.409259][    T1] usbhid: USB HID core driver
[   32.414425][    T1] initcall hid_init+0x0/0x62 returned 0 after 12313 usecs
[   32.422315][    T1] calling  pmc_atom_init+0x0/0x4e @ 1
[   32.428503][    T1] initcall pmc_atom_init+0x0/0x4e returned -19 after 242 usecs
[   32.436905][    T1] calling  sock_diag_init+0x0/0x2f @ 1
[   32.443118][    T1] initcall sock_diag_init+0x0/0x2f returned 0 after 170 usecs
[   32.451437][    T1] calling  init_net_drop_monitor+0x0/0xf8 @ 1
[   32.453758][  T781] usb 2-1.2: new full-speed USB device number 3 using ehci-pci
[   32.458045][    T1] drop_monitor: Initializing network drop monitor service
[   32.458103][    T1] initcall init_net_drop_monitor+0x0/0xf8 returned 0 after 57 usecs
[   32.483333][    T1] calling  blackhole_init+0x0/0x11 @ 1
[   32.489376][    T1] initcall blackhole_init+0x0/0x11 returned 0 after 2 usecs
[   32.497459][    T1] calling  fq_codel_module_init+0x0/0x11 @ 1
[   32.504084][    T1] initcall fq_codel_module_init+0x0/0x11 returned 0 after 0 usecs
[   32.512781][    T1] calling  init_cgroup_cls+0x0/0x11 @ 1
[   32.518921][    T1] initcall init_cgroup_cls+0x0/0x11 returned 0 after 0 usecs
[   32.527139][    T1] calling  xt_init+0x0/0x11f @ 1
[   32.532660][    T1] initcall xt_init+0x0/0x11f returned 0 after 59 usecs
[   32.540283][    T1] calling  tcpudp_mt_init+0x0/0x16 @ 1
[   32.546327][    T1] initcall tcpudp_mt_init+0x0/0x16 returned 0 after 1 usecs
[   32.552985][  T781] usb 2-1.2: New USB device found, idVendor=14dd, idProduct=1005, bcdDevice= 0.00
[   32.554293][    T1] calling  gre_offload_init+0x0/0x52 @ 1
[   32.554299][    T1] initcall gre_offload_init+0x0/0x52 returned 0 after 0 usecs
[   32.564398][  T781] usb 2-1.2: New USB device strings: Mfr=1, Product=2, SerialNumber=3
[   32.570516][    T1] calling  sysctl_ipv4_init+0x0/0x50 @ 1
[   32.578676][  T781] usb 2-1.2: Product: D2CIM-VUSB
[   32.587683][    T1] initcall sysctl_ipv4_init+0x0/0x50 returned 0 after 73 usecs
[   32.593730][  T781] usb 2-1.2: Manufacturer: Raritan
[   32.593732][  T781] usb 2-1.2: SerialNumber: EFFB212D0A6E2DE
[   32.601200][  T781] input: Raritan D2CIM-VUSB Keyboard as /devices/pci0000:00/0000:00:1d.0/usb2/2-1/2-1.2/2-1.2:1.0/0003:14DD:1005.0001/input/input2
[   32.607452][    T1] calling  cubictcp_register+0x0/0x72 @ 1
[   32.617967][    T1] initcall cubictcp_register+0x0/0x72 returned 0 after 10508 usecs
[   32.659699][    T1] calling  xfrm_user_init+0x0/0x34 @ 1
[   32.665758][    T1] Initializing XFRM netlink socket
[   32.671492][    T1] initcall xfrm_user_init+0x0/0x34 returned 0 after 5733 usecs
[   32.673895][  T781] input: Raritan D2CIM-VUSB Mouse as /devices/pci0000:00/0000:00:1d.0/usb2/2-1/2-1.2/2-1.2:1.0/0003:14DD:1005.0001/input/input3
[   32.679767][    T1] calling  inet6_init+0x0/0x3d1 @ 1
[   32.694429][  T781] hid-generic 0003:14DD:1005.0001: input,hidraw0: USB HID v1.11 Keyboard [Raritan D2CIM-VUSB] on usb-0000:00:1d.0-1.2/input0
[   32.700240][    T1] NET: Registered PF_INET6 protocol family
[   32.723032][    T1] Segment Routing with IPv6
[   32.728017][    T1] In-situ OAM (IOAM) with IPv6
[   32.733328][    T1] initcall inet6_init+0x0/0x3d1 returned 0 after 33360 usecs
[   32.741541][    T1] calling  packet_init+0x0/0x83 @ 1
[   32.747295][    T1] NET: Registered PF_PACKET protocol family
[   32.753823][    T1] initcall packet_init+0x0/0x83 returned 0 after 6531 usecs
[   32.761907][    T1] calling  strp_dev_init+0x0/0x37 @ 1
[   32.767940][    T1] initcall strp_dev_init+0x0/0x37 returned 0 after 87 usecs
[   32.776026][    T1] calling  dccp_init+0x0/0x3be @ 1
[   32.777758][  T781] usb 2-1.4: new full-speed USB device number 4 using ehci-pci
[   32.782929][    T1] DCCP: Activated CCID 2 (TCP-like)
[   32.795847][    T1] DCCP: Activated CCID 3 (TCP-Friendly Rate Control)
[   32.803260][    T1] initcall dccp_init+0x0/0x3be returned 0 after 21691 usecs
[   32.811347][    T1] calling  dccp_v4_init+0x0/0x84 @ 1
[   32.817307][    T1] initcall dccp_v4_init+0x0/0x84 returned 0 after 112 usecs
[   32.825396][    T1] calling  dccp_v6_init+0x0/0x84 @ 1
[   32.831491][    T1] initcall dccp_v6_init+0x0/0x84 returned 0 after 237 usecs
[   32.839589][    T1] calling  init_p9+0x0/0x2e @ 1
[   32.845011][    T1] 9pnet: Installing 9P2000 support
[   32.850662][    T1] initcall init_p9+0x0/0x2e returned 0 after 5710 usecs
[   32.858361][    T1] calling  p9_trans_fd_init+0x0/0x30 @ 1
[   32.864603][    T1] initcall p9_trans_fd_init+0x0/0x30 returned 0 after 0 usecs
[   32.872920][    T1] calling  p9_virtio_init+0x0/0x52 @ 1
[   32.878982][    T1] initcall p9_virtio_init+0x0/0x52 returned 0 after 13 usecs
[   32.884544][  T781] usb 2-1.4: New USB device found, idVendor=046b, idProduct=ff10, bcdDevice= 1.00
[   32.887051][    T1] calling  dcbnl_init+0x0/0x54 @ 1
[   32.897159][  T781] usb 2-1.4: New USB device strings: Mfr=1, Product=2, SerialNumber=3
[   32.902705][    T1] initcall dcbnl_init+0x0/0x54 returned 0 after 2 usecs
[   32.911650][  T781] usb 2-1.4: Product: Virtual Keyboard and Mouse
[   32.911652][  T781] usb 2-1.4: Manufacturer: American Megatrends Inc.
[   32.919239][    T1] calling  mpls_gso_init+0x0/0x30 @ 1
[   32.926151][  T781] usb 2-1.4: SerialNumber: serial
[   32.933353][    T1] mpls_gso: MPLS GSO support
[   32.940771][  T781] input: American Megatrends Inc. Virtual Keyboard and Mouse as /devices/pci0000:00/0000:00:1d.0/usb2/2-1/2-1.4/2-1.4:1.0/0003:046B:FF10.0002/input/input4
[   32.944653][    T1] initcall mpls_gso_init+0x0/0x30 returned 0 after 11300 usecs
[   32.949763][  T781] hid-generic 0003:046B:FF10.0002: input,hidraw1: USB HID v1.10 Keyboard [American Megatrends Inc. Virtual Keyboard and Mouse] on usb-0000:00:1d.0-1.4/input0
[   32.966793][    T1] calling  nsh_init_module+0x0/0x18 @ 1
[   32.976086][  T781] input: American Megatrends Inc. Virtual Keyboard and Mouse as /devices/pci0000:00/0000:00:1d.0/usb2/2-1/2-1.4/2-1.4:1.1/0003:046B:FF10.0003/input/input5
[   32.992532][    T1] initcall nsh_init_module+0x0/0x18 returned 0 after 0 usecs
[   32.998744][  T781] hid-generic 0003:046B:FF10.0003: input,hidraw2: USB HID v1.10 Mouse [American Megatrends Inc. Virtual Keyboard and Mouse] on usb-0000:00:1d.0-1.4/input1
[   33.015756][    T1] calling  pm_check_save_msr+0x0/0x80 @ 1
[   33.049771][    T1] initcall pm_check_save_msr+0x0/0x80 returned 0 after 39 usecs
[   33.058315][    T1] calling  mcheck_init_device+0x0/0x14b @ 1
[   33.078470][    T1] initcall mcheck_init_device+0x0/0x14b returned 0 after 13621 usecs
[   33.087470][    T1] calling  dev_mcelog_init_device+0x0/0xca @ 1
[   33.094431][    T1] initcall dev_mcelog_init_device+0x0/0xca returned 0 after 139 usecs
[   33.103670][    T1] calling  kernel_do_mounts_initrd_sysctls_init+0x0/0x26 @ 1
[   33.111879][    T1] initcall kernel_do_mounts_initrd_sysctls_init+0x0/0x26 returned 0 after 1 usecs
[   33.122126][    T1] calling  tboot_late_init+0x0/0x11b @ 1
[   33.128364][    T1] initcall tboot_late_init+0x0/0x11b returned 0 after 0 usecs
[   33.136669][    T1] calling  mcheck_late_init+0x0/0x41 @ 1
[   33.142913][    T1] initcall mcheck_late_init+0x0/0x41 returned 0 after 9 usecs
[   33.151219][    T1] calling  severities_debugfs_init+0x0/0x2e @ 1
[   33.158139][    T1] initcall severities_debugfs_init+0x0/0x2e returned 0 after 6 usecs
[   33.167126][    T1] calling  microcode_init+0x0/0x1e9 @ 1
[   33.173343][    T0] microcode: sig=0x306f4, pf=0x80, revision=0x1a
[   33.185228][    T1] microcode: Microcode Update Driver: v2.2.
[   33.185232][    T1] initcall microcode_init+0x0/0x1e9 returned 0 after 11965 usecs
[   33.200365][    T1] calling  hpet_insert_resource+0x0/0x27 @ 1
[   33.207005][    T1] initcall hpet_insert_resource+0x0/0x27 returned 0 after 14 usecs
[   33.215796][    T1] calling  start_sync_check_timer+0x0/0x54 @ 1
[   33.222621][    T1] initcall start_sync_check_timer+0x0/0x54 returned 0 after 0 usecs
[   33.231509][    T1] calling  update_mp_table+0x0/0x2be @ 1
[   33.237763][    T1] initcall update_mp_table+0x0/0x2be returned 0 after 0 usecs
[   33.246070][    T1] calling  lapic_insert_resource+0x0/0x47 @ 1
[   33.252800][    T1] initcall lapic_insert_resource+0x0/0x47 returned 0 after 4 usecs
[   33.261592][    T1] calling  print_ipi_mode+0x0/0x31 @ 1
[   33.267639][    T1] IPI shorthand broadcast: enabled
[   33.273282][    T1] initcall print_ipi_mode+0x0/0x31 returned 0 after 5643 usecs
[   33.281677][    T1] calling  print_ICs+0x0/0xa4 @ 1
[   33.287282][    T0] ... APIC ID:      00000000 (0)
[   33.289748][    T0] ... APIC VERSION: 01060015
[   33.289748][    T0] 0000000000000000000000000000000000000000000000000000000000000000
[   33.289748][    T0] 0000000000000000000000000000000000000000000000000000000000000000
[   33.289748][    T0] 0000000000000000000000000000000000000000000000000000000008001000
[   33.321751][    T0] 
[   33.326715][    T1] number of MP IRQ sources: 15.
[   33.332078][    T1] number of IO-APIC #8 registers: 24.
[   33.338034][    T1] number of IO-APIC #9 registers: 24.
[   33.343978][    T1] number of IO-APIC #10 registers: 24.
[   33.350032][    T1] number of IO-APIC #11 registers: 24.
[   33.356075][    T1] number of IO-APIC #12 registers: 24.
[   33.362127][    T1] testing the IO APIC.......................
[   33.368753][    T1] IO APIC #8......
[   33.372848][    T1] .... register #00: 08000000
[   33.378026][    T1] .......    : physical APIC id: 08
[   33.383783][    T1] .......    : Delivery Type: 0
[   33.389146][    T1] .......    : LTS          : 0
[   33.394511][    T1] .... register #01: 00170020
[   33.399682][    T1] .......     : max redirection entries: 17
[   33.406212][    T1] .......     : PRQ implemented: 0
[   33.411866][    T1] .......     : IO APIC version: 20
[   33.417618][    T1] .... IRQ redirection table:
[   33.422789][    T1] IOAPIC 0:
[   33.426214][    T1]  pin00, disabled, edge , high, V(00), IRR(0), S(0), physical, D(0000), M(0)
[   33.436091][    T1]  pin01, disabled, edge , high, V(00), IRR(0), S(0), physical, D(0000), M(0)
[   33.445957][    T1]  pin02, enabled , edge , high, V(30), IRR(0), S(0), physical, D(0000), M(0)
[   33.455831][    T1]  pin03, disabled, edge , high, V(00), IRR(0), S(0), physical, D(0000), M(0)
[   33.465698][    T1]  pin04, disabled, edge , high, V(00), IRR(0), S(0), physical, D(0000), M(0)
[   33.475566][    T1]  pin05, disabled, edge , high, V(00), IRR(0), S(0), physical, D(0000), M(0)
[   33.485432][    T1]  pin06, disabled, edge , high, V(00), IRR(0), S(0), physical, D(0000), M(0)
[   33.495297][    T1]  pin07, disabled, edge , high, V(00), IRR(0), S(0), physical, D(0000), M(0)
[   33.505163][    T1]  pin08, enabled , edge , high, V(21), IRR(0), S(0), physical, D(0001), M(0)
[   33.515030][    T1]  pin09, enabled , level, high, V(21), IRR(0), S(0), physical, D(0002), M(0)
[   33.524895][    T1]  pin0a, disabled, edge , high, V(00), IRR(0), S(0), physical, D(0000), M(0)
[   33.534764][    T1]  pin0b, disabled, edge , high, V(F5), IRR(0), S(0), remapped, I(668D),  Z(2)
[   33.544734][    T1]  pin0c, disabled, edge , high, V(00), IRR(0), S(0), physical, D(0000), M(0)
[   33.563925][    T1]  pin0d, disabled, edge , high, V(00), IRR(0), S(0), physical, D(0000), M(0)
[   33.573804][    T1]  pin0e, disabled, edge , high, V(00), IRR(0), S(0), physical, D(0000), M(0)
[   33.583662][    T1]  pin0f, disabled, edge , high, V(00), IRR(0), S(0), physical, D(0000), M(0)
[   33.593527][    T1]  pin10, enabled , level, low , V(21), IRR(0), S(0), physical, D(0040), M(0)
[   33.603394][    T1]  pin11, disabled, edge , high, V(00), IRR(0), S(0), physical, D(0000), M(0)
[   33.613257][    T1]  pin12, enabled , level, low , V(21), IRR(0), S(0), physical, D(0044), M(0)
[   33.623122][    T1]  pin13, disabled, edge , high, V(00), IRR(0), S(0), physical, D(0000), M(0)
[   33.632986][    T1]  pin14, disabled, edge , high, V(00), IRR(0), S(0), physical, D(0000), M(0)
[   33.642857][    T1]  pin15, disabled, edge , high, V(00), IRR(0), S(0), physical, D(0000), M(0)
[   33.652729][    T1]  pin16, disabled, edge , high, V(00), IRR(0), S(0), physical, D(0000), M(0)
[   33.662598][    T1]  pin17, enabled , level, low , V(21), IRR(0), S(0), physical, D(0042), M(0)
[   33.672466][    T1] IO APIC #9......
[   33.676568][    T1] .... register #00: 09000000
[   33.681749][    T1] .......    : physical APIC id: 09
[   33.687501][    T1] .......    : Delivery Type: 0
[   33.692865][    T1] .......    : LTS          : 0
[   33.698217][    T1] .... register #01: 00170020
[   33.703389][    T1] .......     : max redirection entries: 17
[   33.709920][    T1] .......     : PRQ implemented: 0
[   33.715574][    T1] .......     : IO APIC version: 20
[   33.721329][    T1] .... register #02: 00000000
[   33.726495][    T1] .......     : arbitration: 00
[   33.731855][    T1] .... register #03: 00000001
[   33.737025][    T1] .......     : Boot DT    : 1
[   33.742283][    T1] .... IRQ redirection table:
[   33.747453][    T1] IOAPIC 1:
[   33.750875][    T1]  pin00, disabled, edge , high, V(00), IRR(0), S(0), physical, D(0000), M(0)
[   33.760738][    T1]  pin01, disabled, edge , high, V(00), IRR(0), S(0), physical, D(0000), M(0)
[   33.770600][    T1]  pin02, disabled, edge , high, V(00), IRR(0), S(0), physical, D(0000), M(0)
[   33.780468][    T1]  pin03, disabled, edge , high, V(00), IRR(0), S(0), physical, D(0000), M(0)
[   33.790327][    T1]  pin04, disabled, edge , high, V(00), IRR(0), S(0), physical, D(0000), M(0)
[   33.800182][    T1]  pin05, disabled, edge , high, V(00), IRR(0), S(0), physical, D(0000), M(0)
[   33.810056][    T1]  pin06, disabled, edge , high, V(00), IRR(0), S(0), physical, D(0000), M(0)
[   33.819918][    T1]  pin07, disabled, edge , high, V(00), IRR(0), S(0), physical, D(0000), M(0)
[   33.829791][    T1]  pin08, disabled, edge , high, V(00), IRR(0), S(0), physical, D(0000), M(0)
[   33.839657][    T1]  pin09, disabled, edge , high, V(00), IRR(0), S(0), physical, D(0000), M(0)
[   33.849525][    T1]  pin0a, disabled, edge , high, V(00), IRR(0), S(0), physical, D(0000), M(0)
[   33.859387][    T1]  pin0b, disabled, edge , high, V(00), IRR(0), S(0), physical, D(0000), M(0)
[   33.869249][    T1]  pin0c, disabled, edge , high, V(00), IRR(0), S(0), physical, D(0000), M(0)
[   33.879113][    T1]  pin0d, disabled, edge , high, V(00), IRR(0), S(0), physical, D(0000), M(0)
[   33.888975][    T1]  pin0e, disabled, edge , high, V(00), IRR(0), S(0), physical, D(0000), M(0)
[   33.898841][    T1]  pin0f, disabled, edge , high, V(00), IRR(0), S(0), physical, D(0000), M(0)
[   33.908706][    T1]  pin10, disabled, edge , high, V(00), IRR(0), S(0), physical, D(0000), M(0)
[   33.918571][    T1]  pin11, disabled, edge , high, V(00), IRR(0), S(0), physical, D(0000), M(0)
[   33.928439][    T1]  pin12, disabled, edge , high, V(00), IRR(0), S(0), physical, D(0000), M(0)
[   33.938305][    T1]  pin13, disabled, edge , high, V(00), IRR(0), S(0), physical, D(0000), M(0)
[   33.948169][    T1]  pin14, disabled, edge , high, V(00), IRR(0), S(0), physical, D(0000), M(0)
[   33.958045][    T1]  pin15, disabled, edge , high, V(00), IRR(0), S(0), physical, D(0000), M(0)
[   33.967907][    T1]  pin16, disabled, edge , high, V(00), IRR(0), S(0), physical, D(0000), M(0)
[   33.977791][    T1]  pin17, disabled, edge , high, V(00), IRR(0), S(0), physical, D(0000), M(0)
[   33.987663][    T1] IO APIC #10......
[   33.991857][    T1] .... register #00: 0A000000
[   33.997025][    T1] .......    : physical APIC id: 0A
[   34.002780][    T1] .......    : Delivery Type: 0
[   34.008143][    T1] .......    : LTS          : 0
[   34.013502][    T1] .... register #01: 00170020
[   34.018670][    T1] .......     : max redirection entries: 17
[   34.025202][    T1] .......     : PRQ implemented: 0
[   34.030853][    T1] .......     : IO APIC version: 20
[   34.036605][    T1] .... register #02: 00000000
[   34.041777][    T1] .......     : arbitration: 00
[   34.047139][    T1] .... register #03: 00000001
[   34.052311][    T1] .......     : Boot DT    : 1
[   34.057577][    T1] .... IRQ redirection table:
[   34.062747][    T1] IOAPIC 2:
[   34.066158][    T1]  pin00, disabled, edge , high, V(00), IRR(0), S(0), physical, D(0000), M(0)
[   34.076021][    T1]  pin01, disabled, edge , high, V(00), IRR(0), S(0), physical, D(0000), M(0)
[   34.085889][    T1]  pin02, disabled, edge , high, V(00), IRR(0), S(0), physical, D(0000), M(0)
[   34.095760][    T1]  pin03, disabled, edge , high, V(00), IRR(0), S(0), physical, D(0000), M(0)
[   34.105625][    T1]  pin04, disabled, edge , high, V(00), IRR(0), S(0), physical, D(0000), M(0)
[   34.115496][    T1]  pin05, disabled, edge , high, V(00), IRR(0), S(0), physical, D(0000), M(0)
[   34.125365][    T1]  pin06, disabled, edge , high, V(00), IRR(0), S(0), physical, D(0000), M(0)
[   34.135229][    T1]  pin07, disabled, edge , high, V(00), IRR(0), S(0), physical, D(0000), M(0)
[   34.145091][    T1]  pin08, disabled, edge , high, V(00), IRR(0), S(0), physical, D(0000), M(0)
[   34.154956][    T1]  pin09, disabled, edge , high, V(00), IRR(0), S(0), physical, D(0000), M(0)
[   34.164826][    T1]  pin0a, disabled, edge , high, V(00), IRR(0), S(0), physical, D(0000), M(0)
[   34.174690][    T1]  pin0b, disabled, edge , high, V(00), IRR(0), S(0), physical, D(0000), M(0)
[   34.184559][    T1]  pin0c, disabled, edge , high, V(00), IRR(0), S(0), physical, D(0000), M(0)
[   34.194421][    T1]  pin0d, disabled, edge , high, V(00), IRR(0), S(0), physical, D(0000), M(0)
[   34.204285][    T1]  pin0e, disabled, edge , high, V(00), IRR(0), S(0), physical, D(0000), M(0)
[   34.214159][    T1]  pin0f, disabled, edge , high, V(00), IRR(0), S(0), physical, D(0000), M(0)
[   34.224035][    T1]  pin10, disabled, edge , high, V(00), IRR(0), S(0), physical, D(0000), M(0)
[   34.233900][    T1]  pin11, disabled, edge , high, V(00), IRR(0), S(0), physical, D(0000), M(0)
[   34.243771][    T1]  pin12, disabled, edge , high, V(00), IRR(0), S(0), physical, D(0000), M(0)
[   34.253637][    T1]  pin13, disabled, edge , high, V(00), IRR(0), S(0), physical, D(0000), M(0)
[   34.263504][    T1]  pin14, disabled, edge , high, V(00), IRR(0), S(0), physical, D(0000), M(0)
[   34.273369][    T1]  pin15, disabled, edge , high, V(00), IRR(0), S(0), physical, D(0000), M(0)
[   34.283233][    T1]  pin16, disabled, edge , high, V(00), IRR(0), S(0), physical, D(0000), M(0)
[   34.293099][    T1]  pin17, disabled, edge , high, V(00), IRR(0), S(0), physical, D(0000), M(0)
[   34.302965][    T1] IO APIC #11......
[   34.307161][    T1] .... register #00: 0B000000
[   34.312331][    T1] .......    : physical APIC id: 0B
[   34.318086][    T1] .......    : Delivery Type: 0
[   34.323456][    T1] .......    : LTS          : 0
[   34.328821][    T1] .... register #01: 00170020
[   34.333993][    T1] .......     : max redirection entries: 17
[   34.340530][    T1] .......     : PRQ implemented: 0
[   34.346185][    T1] .......     : IO APIC version: 20
[   34.351937][    T1] .... register #02: 00000000
[   34.357104][    T1] .......     : arbitration: 00
[   34.362468][    T1] .... register #03: 00000001
[   34.367637][    T1] .......     : Boot DT    : 1
[   34.372904][    T1] .... IRQ redirection table:
[   34.378077][    T1] IOAPIC 3:
[   34.381504][    T1]  pin00, disabled, edge , high, V(00), IRR(0), S(0), physical, D(0000), M(0)
[   34.391371][    T1]  pin01, disabled, edge , high, V(00), IRR(0), S(0), physical, D(0000), M(0)
[   34.401236][    T1]  pin02, disabled, edge , high, V(00), IRR(0), S(0), physical, D(0000), M(0)
[   34.411099][    T1]  pin03, disabled, edge , high, V(00), IRR(0), S(0), physical, D(0000), M(0)
[   34.420963][    T1]  pin04, disabled, edge , high, V(00), IRR(0), S(0), physical, D(0000), M(0)
[   34.430833][    T1]  pin05, disabled, edge , high, V(00), IRR(0), S(0), physical, D(0000), M(0)
[   34.440703][    T1]  pin06, disabled, edge , high, V(00), IRR(0), S(0), physical, D(0000), M(0)
[   34.450573][    T1]  pin07, disabled, edge , high, V(00), IRR(0), S(0), physical, D(0000), M(0)
[   34.460438][    T1]  pin08, disabled, edge , high, V(00), IRR(0), S(0), physical, D(0000), M(0)
[   34.479679][    T1]  pin09, disabled, edge , high, V(00), IRR(0), S(0), physical, D(0000), M(0)
[   34.489543][    T1]  pin0a, disabled, edge , high, V(00), IRR(0), S(0), physical, D(0000), M(0)
[   34.499410][    T1]  pin0b, disabled, edge , high, V(00), IRR(0), S(0), physical, D(0000), M(0)
[   34.509283][    T1]  pin0c, disabled, edge , high, V(00), IRR(0), S(0), physical, D(0000), M(0)
[   34.519149][    T1]  pin0d, disabled, edge , high, V(00), IRR(0), S(0), physical, D(0000), M(0)
[   34.529010][    T1]  pin0e, disabled, edge , high, V(00), IRR(0), S(0), physical, D(0000), M(0)
[   34.538877][    T1]  pin0f, disabled, edge , high, V(00), IRR(0), S(0), physical, D(0000), M(0)
[   34.548748][    T1]  pin10, disabled, edge , high, V(00), IRR(0), S(0), physical, D(0000), M(0)
[   34.558613][    T1]  pin11, disabled, edge , high, V(00), IRR(0), S(0), physical, D(0000), M(0)
[   34.568482][    T1]  pin12, disabled, edge , high, V(00), IRR(0), S(0), physical, D(0000), M(0)
[   34.578349][    T1]  pin13, disabled, edge , high, V(00), IRR(0), S(0), physical, D(0000), M(0)
[   34.588206][    T1]  pin14, disabled, edge , high, V(00), IRR(0), S(0), physical, D(0000), M(0)
[   34.598082][    T1]  pin15, disabled, edge , high, V(00), IRR(0), S(0), physical, D(0000), M(0)
[   34.607945][    T1]  pin16, disabled, edge , high, V(00), IRR(0), S(0), physical, D(0000), M(0)
[   34.617816][    T1]  pin17, disabled, edge , high, V(00), IRR(0), S(0), physical, D(0000), M(0)
[   34.627683][    T1] IO APIC #12......
[   34.631874][    T1] .... register #00: 0C000000
[   34.637040][    T1] .......    : physical APIC id: 0C
[   34.642798][    T1] .......    : Delivery Type: 0
[   34.648159][    T1] .......    : LTS          : 0
[   34.653529][    T1] .... register #01: 00170020
[   34.658698][    T1] .......     : max redirection entries: 17
[   34.665228][    T1] .......     : PRQ implemented: 0
[   34.670884][    T1] .......     : IO APIC version: 20
[   34.676637][    T1] .... register #02: 00000000
[   34.681821][    T1] .......     : arbitration: 00
[   34.687183][    T1] .... register #03: 00000001
[   34.692355][    T1] .......     : Boot DT    : 1
[   34.697627][    T1] .... IRQ redirection table:
[   34.702799][    T1] IOAPIC 4:
[   34.706218][    T1]  pin00, disabled, edge , high, V(00), IRR(0), S(0), physical, D(0000), M(0)
[   34.716085][    T1]  pin01, disabled, edge , high, V(00), IRR(0), S(0), physical, D(0000), M(0)
[   34.725949][    T1]  pin02, disabled, edge , high, V(00), IRR(0), S(0), physical, D(0000), M(0)
[   34.735826][    T1]  pin03, disabled, edge , high, V(00), IRR(0), S(0), physical, D(0000), M(0)
[   34.745690][    T1]  pin04, disabled, edge , high, V(00), IRR(0), S(0), physical, D(0000), M(0)
[   34.755554][    T1]  pin05, disabled, edge , high, V(00), IRR(0), S(0), physical, D(0000), M(0)
[   34.765421][    T1]  pin06, disabled, edge , high, V(00), IRR(0), S(0), physical, D(0000), M(0)
[   34.775287][    T1]  pin07, disabled, edge , high, V(00), IRR(0), S(0), physical, D(0000), M(0)
[   34.785151][    T1]  pin08, disabled, edge , high, V(00), IRR(0), S(0), physical, D(0000), M(0)
[   34.795015][    T1]  pin09, disabled, edge , high, V(00), IRR(0), S(0), physical, D(0000), M(0)
[   34.804877][    T1]  pin0a, disabled, edge , high, V(00), IRR(0), S(0), physical, D(0000), M(0)
[   34.814745][    T1]  pin0b, disabled, edge , high, V(00), IRR(0), S(0), physical, D(0000), M(0)
[   34.824616][    T1]  pin0c, disabled, edge , high, V(00), IRR(0), S(0), physical, D(0000), M(0)
[   34.834485][    T1]  pin0d, disabled, edge , high, V(00), IRR(0), S(0), physical, D(0000), M(0)
[   34.844353][    T1]  pin0e, disabled, edge , high, V(00), IRR(0), S(0), physical, D(0000), M(0)
[   34.854223][    T1]  pin0f, disabled, edge , high, V(00), IRR(0), S(0), physical, D(0000), M(0)
[   34.864091][    T1]  pin10, disabled, edge , high, V(00), IRR(0), S(0), physical, D(0000), M(0)
[   34.873947][    T1]  pin11, disabled, edge , high, V(00), IRR(0), S(0), physical, D(0000), M(0)
[   34.883823][    T1]  pin12, disabled, edge , high, V(00), IRR(0), S(0), physical, D(0000), M(0)
[   34.893690][    T1]  pin13, disabled, edge , high, V(00), IRR(0), S(0), physical, D(0000), M(0)
[   34.903557][    T1]  pin14, disabled, edge , high, V(00), IRR(0), S(0), physical, D(0000), M(0)
[   34.913414][    T1]  pin15, disabled, edge , high, V(00), IRR(0), S(0), physical, D(0000), M(0)
[   34.923279][    T1]  pin16, disabled, edge , high, V(00), IRR(0), S(0), physical, D(0000), M(0)
[   34.933143][    T1]  pin17, disabled, edge , high, V(00), IRR(0), S(0), physical, D(0000), M(0)
[   34.943007][    T1] IRQ to pin mappings:
[   34.947498][    T1] IRQ0 -> 0:2
[   34.951111][    T1] IRQ1 -> 0:1
[   34.954731][    T1] IRQ3 -> 0:3
[   34.958348][    T1] IRQ4 -> 0:4
[   34.961963][    T1] IRQ5 -> 0:5
[   34.965581][    T1] IRQ6 -> 0:6
[   34.969193][    T1] IRQ7 -> 0:7
[   34.972810][    T1] IRQ8 -> 0:8
[   34.976427][    T1] IRQ9 -> 0:9
[   34.980042][    T1] IRQ10 -> 0:10
[   34.983852][    T1] IRQ11 -> 0:11
[   34.987664][    T1] IRQ12 -> 0:12
[   34.991474][    T1] IRQ13 -> 0:13
[   34.995281][    T1] IRQ14 -> 0:14
[   34.999088][    T1] IRQ15 -> 0:15
[   35.002894][    T1] IRQ16 -> 0:16
[   35.006705][    T1] IRQ18 -> 0:18
[   35.010514][    T1] IRQ19 -> 0:19
[   35.014324][    T1] IRQ23 -> 0:23
[   35.018134][    T1] IRQ24 -> 1:23
[   35.021943][    T1] IRQ32 -> 2:23
[   35.025765][    T1] IRQ36 -> 3:23
[   35.029574][    T1] IRQ40 -> 4:23
[   35.033384][    T1] IRQ44 -> 1:21
[   35.037198][    T1] IRQ109 -> 1:18
[   35.041113][    T1] .................................... done.
[   35.047754][    T1] initcall print_ICs+0x0/0xa4 returned 0 after 1760521 usecs
[   35.055968][    T1] calling  setup_efi_kvm_sev_migration+0x0/0x16d @ 1
[   35.063377][    T1] initcall setup_efi_kvm_sev_migration+0x0/0x16d returned 0 after 0 usecs
[   35.072854][    T1] calling  create_tlb_single_page_flush_ceiling+0x0/0x2d @ 1
[   35.081141][    T1] initcall create_tlb_single_page_flush_ceiling+0x0/0x2d returned 0 after 76 usecs
[   35.091514][    T1] calling  pat_memtype_list_init+0x0/0x36 @ 1
[   35.098239][    T1] initcall pat_memtype_list_init+0x0/0x36 returned 0 after 2 usecs
[   35.107031][    T1] calling  create_init_pkru_value+0x0/0x32 @ 1
[   35.113851][    T1] initcall create_init_pkru_value+0x0/0x32 returned 0 after 0 usecs
[   35.122753][    T1] calling  aesni_init+0x0/0x187 @ 1
[   35.128503][    T1] AVX2 version of gcm_enc/dec engaged.
[   35.134860][    T1] AES CTR mode by8 optimization enabled
[   35.141683][    T1] initcall aesni_init+0x0/0x187 returned 0 after 13180 usecs
[   35.149897][    T1] calling  kernel_panic_sysctls_init+0x0/0x26 @ 1
[   35.157049][    T1] initcall kernel_panic_sysctls_init+0x0/0x26 returned 0 after 40 usecs
[   35.166338][    T1] calling  reboot_ksysfs_init+0x0/0x6e @ 1
[   35.172777][    T1] initcall reboot_ksysfs_init+0x0/0x6e returned 0 after 7 usecs
[   35.181275][    T1] calling  sched_core_sysctl_init+0x0/0x2b @ 1
[   35.188096][    T1] initcall sched_core_sysctl_init+0x0/0x2b returned 0 after 1 usecs
[   35.196983][    T1] calling  sched_fair_sysctl_init+0x0/0x26 @ 1
[   35.203806][    T1] initcall sched_fair_sysctl_init+0x0/0x26 returned 0 after 2 usecs
[   35.212701][    T1] calling  sched_rt_sysctl_init+0x0/0x26 @ 1
[   35.219379][    T1] initcall sched_rt_sysctl_init+0x0/0x26 returned 0 after 48 usecs
[   35.228199][    T1] calling  sched_dl_sysctl_init+0x0/0x26 @ 1
[   35.234831][    T1] initcall sched_dl_sysctl_init+0x0/0x26 returned 0 after 4 usecs
[   35.243523][    T1] calling  sched_clock_init_late+0x0/0x8d @ 1
[   35.250249][    T1] sched_clock: Marking stable (34317550851, 932581600)->(36253650232, -1003517781)
[   35.261025][    T1] initcall sched_clock_init_late+0x0/0x8d returned 0 after 10776 usecs
[   35.270208][    T1] calling  sched_init_debug+0x0/0x255 @ 1
[   35.280806][    T1] initcall sched_init_debug+0x0/0x255 returned 0 after 4273 usecs
[   35.289531][    T1] calling  cpu_latency_qos_init+0x0/0x3e @ 1
[   35.296257][    T1] initcall cpu_latency_qos_init+0x0/0x3e returned 0 after 100 usecs
[   35.305150][    T1] calling  pm_debugfs_init+0x0/0x28 @ 1
[   35.311305][    T1] initcall pm_debugfs_init+0x0/0x28 returned 0 after 24 usecs
[   35.319609][    T1] calling  printk_late_init+0x0/0x115 @ 1
[   35.325950][    T1] initcall printk_late_init+0x0/0x115 returned 0 after 6 usecs
[   35.334351][    T1] calling  init_srcu_module_notifier+0x0/0x30 @ 1
[   35.341461][    T1] initcall init_srcu_module_notifier+0x0/0x30 returned 0 after 1 usecs
[   35.350630][    T1] calling  swiotlb_create_default_debugfs+0x0/0x6c @ 1
[   35.367350][    T1] initcall swiotlb_create_default_debugfs+0x0/0x6c returned 0 after 5 usecs
[   35.377013][    T1] calling  tk_debug_sleep_time_init+0x0/0x28 @ 1
[   35.384027][    T1] initcall tk_debug_sleep_time_init+0x0/0x28 returned 0 after 1 usecs
[   35.393107][    T1] calling  bpf_ksym_iter_register+0x0/0x1d @ 1
[   35.399928][    T1] initcall bpf_ksym_iter_register+0x0/0x1d returned 0 after 0 usecs
[   35.408814][    T1] calling  kernel_acct_sysctls_init+0x0/0x26 @ 1
[   35.415827][    T1] initcall kernel_acct_sysctls_init+0x0/0x26 returned 0 after 1 usecs
[   35.424913][    T1] calling  kexec_core_sysctl_init+0x0/0x26 @ 1
[   35.431734][    T1] initcall kexec_core_sysctl_init+0x0/0x26 returned 0 after 1 usecs
[   35.440622][    T1] calling  bpf_rstat_kfunc_init+0x0/0x16 @ 1
[   35.447250][    T1] initcall bpf_rstat_kfunc_init+0x0/0x16 returned 0 after 3 usecs
[   35.455944][    T1] calling  debugfs_kprobe_init+0x0/0x78 @ 1
[   35.462477][    T1] initcall debugfs_kprobe_init+0x0/0x78 returned 0 after 5 usecs
[   35.471073][    T1] calling  kernel_delayacct_sysctls_init+0x0/0x26 @ 1
[   35.478574][    T1] initcall kernel_delayacct_sysctls_init+0x0/0x26 returned 0 after 0 usecs
[   35.488143][    T1] calling  taskstats_init+0x0/0x3f @ 1
[   35.494192][    T1] registered taskstats version 1
[   35.499649][    T1] initcall taskstats_init+0x0/0x3f returned 0 after 5465 usecs
[   35.508051][    T1] calling  ftrace_sysctl_init+0x0/0x21 @ 1
[   35.514485][    T1] initcall ftrace_sysctl_init+0x0/0x21 returned 0 after 1 usecs
[   35.522984][    T1] calling  init_hwlat_tracer+0x0/0x116 @ 1
[   35.534500][    T1] initcall init_hwlat_tracer+0x0/0x116 returned 0 after 5085 usecs
[   35.543304][    T1] calling  bpf_key_sig_kfuncs_init+0x0/0x11 @ 1
[   35.550222][    T1] initcall bpf_key_sig_kfuncs_init+0x0/0x11 returned 0 after 1 usecs
[   35.559206][    T1] calling  bpf_syscall_sysctl_init+0x0/0x26 @ 1
[   35.566127][    T1] initcall bpf_syscall_sysctl_init+0x0/0x26 returned 0 after 6 usecs
[   35.575110][    T1] calling  kfunc_init+0x0/0x16 @ 1
[   35.580760][    T1] initcall kfunc_init+0x0/0x16 returned 0 after 0 usecs
[   35.588451][    T1] calling  bpf_map_iter_init+0x0/0x32 @ 1
[   35.594782][    T1] initcall bpf_map_iter_init+0x0/0x32 returned 0 after 0 usecs
[   35.603182][    T1] calling  task_iter_init+0x0/0xc9 @ 1
[   35.609249][    T1] initcall task_iter_init+0x0/0xc9 returned 0 after 27 usecs
[   35.617455][    T1] calling  bpf_prog_iter_init+0x0/0x1d @ 1
[   35.623882][    T1] initcall bpf_prog_iter_init+0x0/0x1d returned 0 after 0 usecs
[   35.632378][    T1] calling  bpf_link_iter_init+0x0/0x1d @ 1
[   35.638807][    T1] initcall bpf_link_iter_init+0x0/0x1d returned 0 after 0 usecs
[   35.647304][    T1] calling  init_trampolines+0x0/0x1d @ 1
[   35.653541][    T1] initcall init_trampolines+0x0/0x1d returned 0 after 2 usecs
[   35.661842][    T1] calling  bpf_cgroup_iter_init+0x0/0x1d @ 1
[   35.668465][    T1] initcall bpf_cgroup_iter_init+0x0/0x1d returned 0 after 0 usecs
[   35.677156][    T1] calling  load_system_certificate_list+0x0/0x2b @ 1
[   35.684562][    T1] Loading compiled-in X.509 certificates
[   35.691839][    T1] Loaded X.509 cert 'Build time autogenerated kernel key: b35ab558ee7f94858b3fd59097c5ad33ce90b29d'
[   35.703841][    T1] initcall load_system_certificate_list+0x0/0x2b returned 0 after 19279 usecs
[   35.713704][    T1] calling  fault_around_debugfs+0x0/0x28 @ 1
[   35.720337][    T1] initcall fault_around_debugfs+0x0/0x28 returned 0 after 3 usecs
[   35.729031][    T1] calling  max_swapfiles_check+0x0/0xc @ 1
[   35.735464][    T1] initcall max_swapfiles_check+0x0/0xc returned 0 after 0 usecs
[   35.743962][    T1] calling  init_zswap+0x0/0x32b @ 1
[   35.751010][    T1] zswap: loaded using pool lzo/zbud
[   35.757188][    T1] initcall init_zswap+0x0/0x32b returned 0 after 7472 usecs
[   35.765270][    T1] calling  hugetlb_vmemmap_init+0x0/0x69 @ 1
[   35.771900][    T1] initcall hugetlb_vmemmap_init+0x0/0x69 returned 0 after 6 usecs
[   35.780597][    T1] calling  split_huge_pages_debugfs+0x0/0x28 @ 1
[   35.787614][    T1] initcall split_huge_pages_debugfs+0x0/0x28 returned 0 after 3 usecs
[   35.796694][    T1] calling  check_early_ioremap_leak+0x0/0x3d @ 1
[   35.803712][    T1] initcall check_early_ioremap_leak+0x0/0x3d returned 0 after 0 usecs
[   35.812795][    T1] calling  set_hardened_usercopy+0x0/0x24 @ 1
[   35.819511][    T1] initcall set_hardened_usercopy+0x0/0x24 returned 1 after 0 usecs
[   35.828300][    T1] calling  fscrypt_init+0x0/0x88 @ 1
[   35.834693][    T1] Key type .fscrypt registered
[   35.839962][    T1] Key type fscrypt-provisioning registered
[   35.846391][    T1] initcall fscrypt_init+0x0/0x88 returned 0 after 12244 usecs
[   35.854687][    T1] calling  pstore_init+0x0/0x61 @ 1
[   35.860441][    T1] initcall pstore_init+0x0/0x61 returned 0 after 2 usecs
[   35.868234][    T1] calling  init_root_keyring+0x0/0xe @ 1
[   35.874486][    T1] initcall init_root_keyring+0x0/0xe returned 0 after 15 usecs
[   35.882887][    T1] calling  init_trusted+0x0/0x16f @ 1
[   40.113033][  T743] Freeing initrd memory: 1245380K
[   40.122877][    T1] Key type trusted registered
[   40.128051][    T1] initcall init_trusted+0x0/0x16f returned 0 after 4239220 usecs
[   40.136651][    T1] calling  init_encrypted+0x0/0xd4 @ 1
[   40.145762][    T1] Key type encrypted registered
[   40.151141][    T1] initcall init_encrypted+0x0/0xd4 returned 0 after 8448 usecs
[   40.159553][    T1] calling  init_profile_hash+0x0/0x83 @ 1
[   40.165892][    T1] AppArmor: AppArmor sha1 policy hashing enabled
[   40.172902][    T1] initcall init_profile_hash+0x0/0x83 returned 0 after 7014 usecs
[   40.181592][    T1] calling  integrity_fs_init+0x0/0x52 @ 1
[   40.187933][    T1] initcall integrity_fs_init+0x0/0x52 returned 0 after 5 usecs
[   40.196333][    T1] calling  crypto_algapi_init+0x0/0x7f @ 1
[   40.205806][    T1] initcall crypto_algapi_init+0x0/0x7f returned 0 after 3039 usecs
[   40.214604][    T1] calling  blk_timeout_init+0x0/0x17 @ 1
[   40.220839][    T1] initcall blk_timeout_init+0x0/0x17 returned 0 after 0 usecs
[   40.229151][    T1] calling  init_error_injection+0x0/0x6e @ 1
[   40.236045][    T1] initcall init_error_injection+0x0/0x6e returned 0 after 262 usecs
[   40.244939][    T1] calling  pci_resource_alignment_sysfs_init+0x0/0x18 @ 1
[   40.252848][    T1] initcall pci_resource_alignment_sysfs_init+0x0/0x18 returned 0 after 4 usecs
[   40.262813][    T1] calling  pci_sysfs_init+0x0/0x72 @ 1
[   40.269117][    T1] initcall pci_sysfs_init+0x0/0x72 returned 0 after 260 usecs
[   40.277422][    T1] calling  bert_init+0x0/0x282 @ 1
[   40.283093][    T1] initcall bert_init+0x0/0x282 returned 0 after 1 usecs
[   40.290801][    T1] calling  clk_debug_init+0x0/0x115 @ 1
[   40.296955][    T1] initcall clk_debug_init+0x0/0x115 returned 0 after 15 usecs
[   40.305258][    T1] calling  dmar_free_unused_resources+0x0/0xbc @ 1
[   40.312473][    T1] initcall dmar_free_unused_resources+0x0/0xbc returned 0 after 4 usecs
[   40.321768][    T1] calling  sync_state_resume_initcall+0x0/0x40 @ 1
[   40.328984][    T1] initcall sync_state_resume_initcall+0x0/0x40 returned 0 after 0 usecs
[   40.338280][    T1] calling  deferred_probe_initcall+0x0/0xc0 @ 1
[   40.345214][    T1] initcall deferred_probe_initcall+0x0/0xc0 returned 0 after 17 usecs
[   40.354296][    T1] calling  firmware_memmap_init+0x0/0x37 @ 1
[   40.360952][    T1] initcall firmware_memmap_init+0x0/0x37 returned 0 after 29 usecs
[   40.369744][    T1] calling  register_update_efi_random_seed+0x0/0x22 @ 1
[   40.377430][    T1] initcall register_update_efi_random_seed+0x0/0x22 returned 0 after 0 usecs
[   40.387191][    T1] calling  efi_shutdown_init+0x0/0x48 @ 1
[   40.393524][    T1] initcall efi_shutdown_init+0x0/0x48 returned -19 after 0 usecs
[   40.402123][    T1] calling  efi_earlycon_unmap_fb+0x0/0x2a @ 1
[   40.408843][    T1] initcall efi_earlycon_unmap_fb+0x0/0x2a returned 0 after 0 usecs
[   40.417632][    T1] calling  itmt_legacy_init+0x0/0x4d @ 1
[   40.423869][    T1] initcall itmt_legacy_init+0x0/0x4d returned -19 after 0 usecs
[   40.432367][    T1] calling  bpf_sockmap_iter_init+0x0/0x1d @ 1
[   40.439088][    T1] initcall bpf_sockmap_iter_init+0x0/0x1d returned 0 after 0 usecs
[   40.447876][    T1] calling  bpf_sk_storage_map_iter_init+0x0/0x1d @ 1
[   40.455280][    T1] initcall bpf_sk_storage_map_iter_init+0x0/0x1d returned 0 after 0 usecs
[   40.464756][    T1] calling  sch_default_qdisc+0x0/0x11 @ 1
[   40.471089][    T1] initcall sch_default_qdisc+0x0/0x11 returned 0 after 2 usecs
[   40.479482][    T1] calling  bpf_prog_test_run_init+0x0/0x9a @ 1
[   40.486320][    T1] initcall bpf_prog_test_run_init+0x0/0x9a returned 0 after 16 usecs
[   40.495310][    T1] calling  tcp_congestion_default+0x0/0x18 @ 1
[   40.502131][    T1] initcall tcp_congestion_default+0x0/0x18 returned 0 after 2 usecs
[   40.511019][    T1] calling  ip_auto_config+0x0/0x4c6 @ 1
[   40.790800][    T1] pps pps0: new PPS source ptp0
[   40.796273][    T1] ixgbe 0000:03:00.0: registered PHC device on eth0
[   41.214657][    T1] pps pps1: new PPS source ptp1
[   41.220143][    T1] ixgbe 0000:03:00.1: registered PHC device on eth1
[   43.549168][   T10] ixgbe 0000:03:00.0 eth0: NIC Link is Up 1 Gbps, Flow Control: None
[   43.558411][  T931] IPv6: ADDRCONF(NETDEV_CHANGE): eth0: link becomes ready
[   43.577768][    T1] Sending DHCP requests ., OK
[   43.602581][    T1] IP-Config: Got DHCP answer from 192.168.2.7, my address is 192.168.2.30
[   43.612077][    T1] IP-Config: Complete:
[   43.616572][    T1]      device=eth0, hwaddr=a0:36:9f:18:d6:a8, ipaddr=192.168.2.30, mask=255.255.255.0, gw=192.168.2.200
[   43.628967][    T1]      host=lkp-hsw-4ex1, domain=lkp.intel.com, nis-domain=(none)
[   43.637659][    T1]      bootserver=192.168.2.200, rootserver=192.168.2.200, rootpath=
[   43.637664][    T1]      nameserver0=192.168.2.200
[   43.653186][    T1] ixgbe 0000:03:00.1: removed PHC on eth1
[   43.980086][    T1] initcall ip_auto_config+0x0/0x4c6 returned 0 after 3462931 usecs
[   43.988888][    T1] calling  tcp_bpf_v4_build_proto+0x0/0x97 @ 1
[   43.995718][    T1] initcall tcp_bpf_v4_build_proto+0x0/0x97 returned 0 after 8 usecs
[   44.004606][    T1] calling  udp_bpf_v4_build_proto+0x0/0x45 @ 1
[   44.011433][    T1] initcall udp_bpf_v4_build_proto+0x0/0x45 returned 0 after 1 usecs
[   44.020324][    T1] calling  bpf_tcp_ca_kfunc_init+0x0/0x16 @ 1
[   44.027056][    T1] initcall bpf_tcp_ca_kfunc_init+0x0/0x16 returned 0 after 6 usecs
[   44.035844][    T1] calling  pci_mmcfg_late_insert_resources+0x0/0x54 @ 1
[   44.043549][    T1] initcall pci_mmcfg_late_insert_resources+0x0/0x54 returned 0 after 4 usecs
[   44.053312][    T1] calling  software_resume+0x0/0x40 @ 1
[   44.059473][    T1] initcall software_resume+0x0/0x40 returned -2 after 4 usecs
[   44.067777][    T1] calling  ftrace_check_sync+0x0/0x18 @ 1
[   44.074132][    T1] initcall ftrace_check_sync+0x0/0x18 returned 0 after 14 usecs
[   44.082630][    T1] calling  latency_fsnotify_init+0x0/0x3c @ 1
[   44.089390][    T1] initcall latency_fsnotify_init+0x0/0x3c returned 0 after 34 usecs
[   44.098283][    T1] calling  trace_eval_sync+0x0/0x18 @ 1
[   44.104436][    T1] initcall trace_eval_sync+0x0/0x18 returned 0 after 7 usecs
[   44.112646][    T1] calling  late_trace_init+0x0/0xa0 @ 1
[   44.118796][    T1] initcall late_trace_init+0x0/0xa0 returned 0 after 2 usecs
[   44.127014][    T1] calling  acpi_gpio_handle_deferred_request_irqs+0x0/0x5d @ 1
[   44.135424][    T1] initcall acpi_gpio_handle_deferred_request_irqs+0x0/0x5d returned 0 after 4 usecs
[   44.145876][    T1] calling  fb_logo_late_init+0x0/0x13 @ 1
[   44.152218][    T1] initcall fb_logo_late_init+0x0/0x13 returned 0 after 0 usecs
[   44.160618][    T1] calling  clk_disable_unused+0x0/0x106 @ 1
[   44.167153][    T1] initcall clk_disable_unused+0x0/0x106 returned 0 after 1 usecs
[   44.178146][    T1] Freeing unused kernel image (initmem) memory: 2788K
[   44.187767][    T1] Write protecting the kernel read-only data: 28672k
[   44.196431][    T1] Freeing unused kernel image (text/rodata gap) memory: 2036K
[   44.205380][    T1] Freeing unused kernel image (rodata/data gap) memory: 912K
[   44.219775][    T1] Run /init as init process
[   44.224760][    T1]   with arguments:
[   44.228952][    T1]     /init
[   44.232365][    T1]     nokaslr
[   44.235976][    T1]   with environment:
[   44.240356][    T1]     HOME=/
[   44.243870][    T1]     TERM=linux
[   44.247766][    T1]     RESULT_ROOT=/result/vm-scalability/performance-4-64-1-swap-w-seq-never-never/lkp-hsw-4ex1/debian-11.1-x86_64-20220510.cgz/x86_64-rhel-8.3/gcc-11/6919cda8e0f127fe773cad2553f0648de1c48445/0
[   44.268940][    T1]     BOOT_IMAGE=/pkg/linux/x86_64-rhel-8.3/gcc-11/6919cda8e0f127fe773cad2553f0648de1c48445/vmlinuz-6.1.0-rc5-00020-g6919cda8e0f1
[   44.283866][    T1]     branch=linux-devel/devel-hourly-20221209-093320
[   44.291369][    T1]     job=/lkp/jobs/scheduled/lkp-hsw-4ex1/vm-scalability-performance-4-64-1-swap-w-seq-never-never-debian-11.1-x86_64-20220510.cgz-6919cda8e0f127fe773cad2553f0648de1c4844-20221210-31307-1s05up6-0.yaml
[   44.313316][    T1]     user=lkp
[   44.317022][    T1]     ARCH=x86_64
[   44.321019][    T1]     kconfig=x86_64-rhel-8.3
[   44.326187][    T1]     commit=6919cda8e0f127fe773cad2553f0648de1c48445
[   44.333688][    T1]     cma=0
[   44.337105][    T1]     max_uptime=2100
[   44.341493][    T1]     LKP_SERVER=internal-lkp-server
[   44.347339][    T1]     selinux=0
[   44.351144][    T1]     softlockup_panic=1
[   44.355820][    T1]     prompt_ramdisk=0
[   44.360304][    T1]     vga=normal
[   44.370211][    T1] systemd[1]: RTC configured in localtime, applying delta of 0 minutes to system time.
[   44.385298][    T1] calling  ip_tables_init+0x0/0x1000 [ip_tables] @ 1
[   44.392721][    T1] initcall ip_tables_init+0x0/0x1000 [ip_tables] returned 0 after 6 usecs


 to Wall Directo[   44.536373][ T1081] fuse: init (API version 7.37)
[   44.536620][ T1081] initcall fuse_init+0x0/0x146 [fuse] returned 0 after 246 usecs
oad Kernel Modul[   44.712638][ T1115] initcall acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] returned -17 after 0 usecs
ount Root and Ke[   44.759041][ T1257] initcall acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] returned -17 after 0 usecs
rnel File System[   44.770974][ T1280] calling  acpi_pad_init+0x0/0x1000 [acpi_pad] @ 1280
      [   44.779772][ T1280] initcall acpi_pad_init+0x0/0x1000 [acpi_pad] returned 0 after 262 usecs
1;39mColdplug Al[   44.798831][ T1278] calling  ipmi_init_msghandler_mod+0x0/0x1000 [ipmi_msghandler] @ 1278
0m...
 Pages File Syst[   44.850376][ T1281] calling  joydev_init+0x0/0x1000 [joydev] @ 1281
[   44.886202][ T1322] calling  libnvdimm_init+0x0/0x48 [libnvdimm] @ 1322
m.
[   44.931305][ T1284] initcall raid_init+0x0/0x1000 [raid_class] returned 0 after 129 usecs
[   44.940862][ T1308] ipmi device interface
m.
Debug File Syste[   44.976535][ T1227] calling  acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] @ 1227
[   44.982662][ T1115] initcall ata_init+0x0/0x5f [libata] returned 0 after 6490 usecs
nel Trace File S[   45.031966][ T1322] initcall e820_pmem_driver_init+0x0/0x1000 [nd_e820] returned 0 after 306 usecs
9mCreate list of[   45.064330][ T1115] ahci 0000:00:1f.2: version 3.0
[   45.072649][ T1290] ipmi_si: IPMI System Interface driver
 the current ker[   45.079884][ T1115] ahci 0000:00:1f.2: AHCI 0001.0300 32 slots 6 ports 6 Gbps 0x10 impl SATA mode
[   45.094988][ T1115] ahci 0000:00:1f.2: flags: 64bit ncq sntf pm led clo pio slum part ems apst 
[   45.106444][ T1290] ipmi_si: Adding SMBIOS-specified kcs state machine
Load Kernel Modu[   45.126631][ T1290] ipmi_si IPI0001:00: ipmi_platform: probing via ACPI

         Mount[   45.139389][ T1290] ipmi_si IPI0001:00: ipmi_platform: [io  0x0ca2-0x0ca3] regsize 1 spacing 1 irq 0
nel Configuratio[   45.177044][ T1306] calling  rapl_pmu_init+0x0/0xf99 [rapl] @ 1306
[   45.177402][ T1115] scsi host4: ahci
[   45.192076][ T1306] RAPL PMU: API unit is 2^-32 Joules, 2 fixed counters, 655360 ms ovfl timer
[   45.196373][ T1115] ata1: DUMMY
[   45.205897][ T1306] RAPL PMU: hw unit of domain package 2^-14 Joules
[   45.205899][ T1306] RAPL PMU: hw unit of domain dram 2^-16 Joules
[   45.209415][ T1115] ata2: DUMMY
[   45.209417][ T1115] ata3: DUMMY
[0m.
 Kernel Variable[   45.295035][ T1284] mpt3sas version 43.100.00.00 loaded
      [   45.302626][ T1284] mpt3sas 0000:01:00.0: can't disable ASPM; OS doesn't have ASPM control
[   45.302928][ T1491] calling  acpi_ipmi_init+0x0/0x1000 [acpi_ipmi] @ 1491
[   45.324190][ T1491] initcall acpi_ipmi_init+0x0/0x1000 [acpi_ipmi] returned 0 after 3555 usecs
1;39mCreate Syst[   45.331899][ T1284] mpt2sas_cm0: 64 BIT PCI BUS DMA ADDRESSING SUPPORTED, total mem (32761772 kB)

;1;39mKernel Con[   45.384949][ T1397] initcall sha512_ssse3_mod_init+0x0/0x1000 [sha512_ssse3] returned 0 after 511 usecs
1;39mApply Kerne[   45.418944][ T1284] mpt2sas_cm0: MSI-X vectors supported: 16

[0;1;39mCreate S[   45.448531][ T1284] mpt2sas0-msix0: PCI-MSI-X enabled: IRQ 176

         Start[   45.464665][ T1284] mpt2sas0-msix2: PCI-MSI-X enabled: IRQ 178
ate Static Devic[   45.480788][ T1284] mpt2sas0-msix4: PCI-MSI-X enabled: IRQ 180
[0m...
ad Kernel Module[   45.488711][ T1284] mpt2sas_cm0: iomem(0x0000000093340000), mapped(0x000000009ace5fbd), size(65536)
[   45.498327][ T1261] initcall acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] returned -17 after 0 usecs
[   45.506377][ T1284] mpt2sas_cm0: ioport(0x0000000000001000), size(256)
[   45.522754][ T1389] calling  ghash_pclmulqdqni_mod_init+0x0/0x1000 [ghash_clmulni_intel] @ 1389
[   45.531480][ T1492] ata5: SATA link up 1.5 Gbps (SStatus 113 SControl 300)
    [   45.533286][ T1492] ata5.00: ATAPI: TEAC    DV-W28S-W, 1.0A, max UDMA/100
0;1;39mFUSE Cont[   45.544354][ T1389] initcall ghash_pclmulqdqni_mod_init+0x0/0x1000 [ghash_clmulni_intel] returned 0 after 191 usecs
[   45.552450][    T9] scsi 4:0:0:0: CD-ROM            TEAC     DV-W28S-W        1.0A PQ: 0 ANSI: 5
[0m...
Device Nodes in [   45.671521][ T1284] mpt2sas_cm0: sense pool(0x00000000c0a63c69)- dma(0x1f13580000): depth(2939),element_size(96), pool_size(0 kB)
0;1;39mLocal Fil[   45.721433][ T1284] mpt2sas_cm0: Current Controller Queue Depth(2936),Max Controller Queue Depth(3072)
[0m.
9mLocal File Sys[   45.754924][ T1250] initcall acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] returned -17 after 0 usecs
     [   45.766646][ T1384] calling  crc32c_intel_mod_init+0x0/0x1000 [crc32c_intel] @ 1384
[   45.785755][ T1284] mpt2sas_cm0: LSISAS2308: FWVersion(17.00.01.00), ChipRevision(0x05), BiosVersion(07.33.00.00)
;1;39mPreprocess[   45.800264][ T1284] mpt2sas_cm0: Intel(R) Controller: Subsystem ID: 0x3050
 NFS configurati[   45.800850][ T1290] ipmi_si dmi-ipmi-si.0: Removing SMBIOS-specified kcs state machine in favor of ACPI
     [   45.809205][ T1284] mpt2sas_cm0: Protocol=(
;1;39mRule-based[   45.821476][ T1290] ipmi_si: Trying ACPI-specified kcs state machine at i/o address 0xca2, slave address 0x20, irq 0
vice Events and [   45.827631][ T1284] scsi host6: Fusion MPT SAS Host
[   45.871662][  T754] mpt2sas_cm0: sending port enable !!
[   45.871714][ T1284] initcall _mpt3sas_init+0x0/0x1000 [mpt3sas] returned 0 after 95153 usecs
9mRule-based Man[   45.953676][ T1454] calling  crct10dif_intel_mod_init+0x0/0x1000 [crct10dif_pclmul] @ 1454
ager for Device [   45.964287][ T1454] initcall crct10dif_intel_mod_init+0x0/0x1000 [crct10dif_pclmul] returned 0 after 181 usecs
Coldplug All ude[   45.997579][ T1204] initcall acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] returned -17 after 0 usecs
[   46.047156][ T1290] ipmi_si IPI0001:00: IPMI kcs interface initialized
[   46.054581][ T1290] initcall init_ipmi_si+0x0/0x15a [ipmi_si] returned 0 after 57002 usecs
[   46.156101][ T1292] calling  kvm_x86_init+0x0/0x11 [kvm] @ 1292
[   46.162881][ T1292] initcall kvm_x86_init+0x0/0x11 [kvm] returned 0 after 0 usecs
0m...
[   46.201535][ T1167] initcall acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] returned -17 after 2 usecs
[   46.212672][ T1278] calling  init_ipmi_ssif+0x0/0x1000 [ipmi_ssif] @ 1278
[   46.220399][ T1278] ipmi_ssif: IPMI SSIF Interface driver
[   46.220473][ T1278] initcall init_ipmi_ssif+0x0/0x1000 [ipmi_ssif] returned 0 after 74 usecs
[   46.292443][ T1391] initcall vmx_init+0x0/0xf4 [kvm_intel] returned 0 after 37121 usecs
[   46.318462][ T1264] calling  acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] @ 1264
[   46.326884][ T1264] initcall acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] returned -17 after 1 usecs
[   46.350990][ T1289] initcall coretemp_init+0x0/0x1000 [coretemp] returned 0 after 4798 usecs
0m] Reached targ[   46.381605][ T1200] initcall acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] returned -17 after 0 usecs
[0m.
.
[   46.454367][ T1297] calling  pkg_temp_thermal_init+0x0/0x1000 [x86_pkg_temp_thermal] @ 1297
1;39mDaily apt u[   46.514674][ T1317] calling  sbridge_init+0x0/0x1000 [sb_edac] @ 1317
pgrade and clean[   46.523062][ T1317] EDAC sbridge: Seeking for: PCI ID 8086:2fa0

[   46.539453][ T1317] EDAC sbridge: Seeking for: PCI ID 8086:2fa0
[   46.546281][ T1317] EDAC sbridge: Seeking for: PCI ID 8086:2fa0
1;39mPeriodic ex[   46.569395][ T1317] EDAC sbridge: Seeking for: PCI ID 8086:2f60
eck for All File[   46.585819][ T1317] EDAC sbridge: Seeking for: PCI ID 8086:2f60
[   46.593992][ T1317] EDAC sbridge: Seeking for: PCI ID 8086:2f60
[   46.601946][ T1317] EDAC sbridge: Seeking for: PCI ID 8086:2fa8
[   46.608679][ T1317] EDAC sbridge: Seeking for: PCI ID 8086:2fa8
1;39mDiscard unu[   46.631858][ T1317] EDAC sbridge: Seeking for: PCI ID 8086:2fa8
sed blocks once [   46.640075][ T1317] EDAC sbridge: Seeking for: PCI ID 8086:2f71
[   46.648244][ T1317] EDAC sbridge: Seeking for: PCI ID 8086:2f71
[   46.656141][ T1317] EDAC sbridge: Seeking for: PCI ID 8086:2f71
[   46.672251][ T1317] EDAC sbridge: Seeking for: PCI ID 8086:2f71
1;39mDaily rotat[   46.695385][ T1317] EDAC sbridge: Seeking for: PCI ID 8086:2faa
ion of log files[   46.703584][ T1317] EDAC sbridge: Seeking for: PCI ID 8086:2faa
[   46.711789][ T1317] EDAC sbridge: Seeking for: PCI ID 8086:2faa
[   46.719091][ T1317] EDAC sbridge: Seeking for: PCI ID 8086:2faa
1;39mDaily Clean[   46.742232][ T1317] EDAC sbridge: Seeking for: PCI ID 8086:2fab
up of Temporary [   46.750441][ T1317] EDAC sbridge: Seeking for: PCI ID 8086:2fab

[   46.766841][ T1317] EDAC sbridge: Seeking for: PCI ID 8086:2fac
[   46.773671][ T1317] EDAC sbridge: Seeking for: PCI ID 8086:2fac
0m] Reached targ[   46.788646][ T1317] EDAC sbridge: Seeking for: PCI ID 8086:2fac
[   46.805075][ T1317] EDAC sbridge: Seeking for: PCI ID 8086:2fad
[   46.812544][ T1317] EDAC sbridge: Seeking for: PCI ID 8086:2fad
[   46.819283][ T1317] EDAC sbridge: Seeking for: PCI ID 8086:2fad
0m] Listening on[   46.834230][ T1317] EDAC sbridge: Seeking for: PCI ID 8086:2fad
System Message B[   46.850618][ T1317] EDAC sbridge: Seeking for: PCI ID 8086:2f68
[   46.858836][ T1317] EDAC sbridge: Seeking for: PCI ID 8086:2f68
[   46.866984][ T1317] EDAC sbridge: Seeking for: PCI ID 8086:2f68
0m] Reached targ[   46.881943][ T1317] EDAC sbridge: Seeking for: PCI ID 8086:2f79
[   46.898274][ T1317] EDAC sbridge: Seeking for: PCI ID 8086:2f79
[   46.905871][ T1317] EDAC sbridge: Seeking for: PCI ID 8086:2f79
0m] Reached targ[   46.920855][ T1317] EDAC sbridge: Seeking for: PCI ID 8086:2f6a
[   46.937230][ T1317] EDAC sbridge: Seeking for: PCI ID 8086:2f6a
[   46.945304][ T1317] EDAC sbridge: Seeking for: PCI ID 8086:2f6a
[   46.952044][ T1317] EDAC sbridge: Seeking for: PCI ID 8086:2f6a
[   46.958782][ T1317] EDAC sbridge: Seeking for: PCI ID 8086:2f6b
[   46.965510][ T1317] EDAC sbridge: Seeking for: PCI ID 8086:2f6b
[   46.972237][ T1317] EDAC sbridge: Seeking for: PCI ID 8086:2f6b
[   46.978967][ T1317] EDAC sbridge: Seeking for: PCI ID 8086:2f6b
[   46.985692][ T1317] EDAC sbridge: Seeking for: PCI ID 8086:2f6b
[   46.992415][ T1317] EDAC sbridge: Seeking for: PCI ID 8086:2f6c
[   46.999149][ T1317] EDAC sbridge: Seeking for: PCI ID 8086:2f6c
[   47.005876][ T1317] EDAC sbridge: Seeking for: PCI ID 8086:2f6c
[   47.012609][ T1317] EDAC sbridge: Seeking for: PCI ID 8086:2f6c
[   47.019334][ T1317] EDAC sbridge: Seeking for: PCI ID 8086:2f6c
[   47.026069][ T1317] EDAC sbridge: Seeking for: PCI ID 8086:2f6d
[   47.032809][ T1317] EDAC sbridge: Seeking for: PCI ID 8086:2f6d
[   47.039540][ T1317] EDAC sbridge: Seeking for: PCI ID 8086:2f6d
[   47.046270][ T1317] EDAC sbridge: Seeking for: PCI ID 8086:2f6d
[   47.052999][ T1317] EDAC sbridge: Seeking for: PCI ID 8086:2f6d
[   47.059746][ T1317] EDAC sbridge: Seeking for: PCI ID 8086:2ffc
[   47.066468][ T1317] EDAC sbridge: Seeking for: PCI ID 8086:2ffc
[   47.073186][ T1317] EDAC sbridge: Seeking for: PCI ID 8086:2ffc
[   47.079919][ T1317] EDAC sbridge: Seeking for: PCI ID 8086:2ffc
[   47.086652][ T1317] EDAC sbridge: Seeking for: PCI ID 8086:2ffc
[   47.093377][ T1317] EDAC sbridge: Seeking for: PCI ID 8086:2ffd
[   47.100113][ T1317] EDAC sbridge: Seeking for: PCI ID 8086:2ffd
[   47.106860][ T1317] EDAC sbridge: Seeking for: PCI ID 8086:2ffd
[   47.113589][ T1317] EDAC sbridge: Seeking for: PCI ID 8086:2ffd
[   47.120319][ T1317] EDAC sbridge: Seeking for: PCI ID 8086:2ffd
[   47.127047][ T1317] EDAC sbridge: Seeking for: PCI ID 8086:2fbd
[   47.133788][ T1317] EDAC sbridge: Seeking for: PCI ID 8086:2fbd
[   47.140517][ T1317] EDAC sbridge: Seeking for: PCI ID 8086:2fbd
[   47.147249][ T1317] EDAC sbridge: Seeking for: PCI ID 8086:2fbd
[   47.153978][ T1317] EDAC sbridge: Seeking for: PCI ID 8086:2fbd
[   47.160703][ T1317] EDAC sbridge: Seeking for: PCI ID 8086:2fbf
[   47.167432][ T1317] EDAC sbridge: Seeking for: PCI ID 8086:2fbf
[   47.174157][ T1317] EDAC sbridge: Seeking for: PCI ID 8086:2fbf
[   47.180884][ T1317] EDAC sbridge: Seeking for: PCI ID 8086:2fbf
[   47.187613][ T1317] EDAC sbridge: Seeking for: PCI ID 8086:2fbf
[   47.194337][ T1317] EDAC sbridge: Seeking for: PCI ID 8086:2fb9
[   47.201077][ T1317] EDAC sbridge: Seeking for: PCI ID 8086:2fb9
[   47.207819][ T1317] EDAC sbridge: Seeking for: PCI ID 8086:2fb9
[   47.214551][ T1317] EDAC sbridge: Seeking for: PCI ID 8086:2fb9
[   47.221279][ T1317] EDAC sbridge: Seeking for: PCI ID 8086:2fb9
[   47.228001][ T1317] EDAC sbridge: Seeking for: PCI ID 8086:2fbb
[   47.234762][ T1317] EDAC sbridge: Seeking for: PCI ID 8086:2fbb
[   47.241490][ T1317] EDAC sbridge: Seeking for: PCI ID 8086:2fbb
[   47.248219][ T1317] EDAC sbridge: Seeking for: PCI ID 8086:2fbb
[   47.254950][ T1317] EDAC sbridge: Seeking for: PCI ID 8086:2fbb
[   47.261859][ T1317] EDAC MC0: Giving out device to module sb_edac controller Haswell SrcID#3_Ha#0: DEV 0000:ff:12.0 (INTERRUPT)
[   47.275015][ T1317] EDAC MC1: Giving out device to module sb_edac controller Haswell SrcID#2_Ha#0: DEV 0000:bf:12.0 (INTERRUPT)
[   47.288144][ T1317] EDAC MC2: Giving out device to module sb_edac controller Haswell SrcID#1_Ha#0: DEV 0000:7f:12.0 (INTERRUPT)
[   47.301265][ T1317] EDAC MC3: Giving out device to module sb_edac controller Haswell SrcID#0_Ha#0: DEV 0000:3f:12.0 (INTERRUPT)
[   47.314340][ T1317] EDAC MC4: Giving out device to module sb_edac controller Haswell SrcID#3_Ha#1: DEV 0000:ff:12.4 (INTERRUPT)
[   47.327430][ T1317] EDAC MC5: Giving out device to module sb_edac controller Haswell SrcID#2_Ha#1: DEV 0000:bf:12.4 (INTERRUPT)
[   47.340504][ T1317] EDAC MC6: Giving out device to module sb_edac controller Haswell SrcID#1_Ha#1: DEV 0000:7f:12.4 (INTERRUPT)
[   47.353577][ T1317] EDAC MC7: Giving out device to module sb_edac controller Haswell SrcID#0_Ha#1: DEV 0000:3f:12.4 (INTERRUPT)
[   47.366548][ T1317] EDAC sbridge:  Ver: 1.1.2 
[   47.371628][ T1317] initcall sbridge_init+0x0/0x1000 [sb_edac] returned 0 after 848566 usecs
[   47.425586][ T1275] calling  acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] @ 1275
[   47.433801][ T1275] initcall acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] returned -17 after 0 usecs
e command to reb[   47.479242][ T1275] calling  rapl_init+0x0/0x1000 [intel_rapl_common] @ 1275
[   47.480255][   T10] mpt2sas_cm0: hba_port entry: 000000006351a43e, port: 255 is added to hba_port list
[   47.488239][ T1275] initcall rapl_init+0x0/0x1000 [intel_rapl_common] returned 0 after 68 usecs
[   47.499955][   T10] mpt2sas_cm0: host_add: handle(0x0001), sas_addr(0x500605b005c3d950), phys(8)
.
[   47.531712][ T1366] calling  acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] @ 1366
[   47.539932][ T1366] initcall acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] returned -17 after 0 usecs
..
[   47.578405][ T1446] initcall acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] returned -17 after 0 usecs
LKP: ttyS0: 1557: current_version: 1a, target_version: 1a
/var/lock/lkp-bo[   47.616693][ T1159] initcall acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] returned -17 after 0 usecs
[   47.647808][ T1348] calling  acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] @ 1348
[   47.656040][ T1348] initcall acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] returned -17 after 0 usecs
LKP: ttyS0: 1557: skip deploy intel ucode as ucode is same
[   47.688796][ T1122] calling  acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] @ 1122
[   47.697020][ T1122] initcall acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] returned -17 after 0 usecs
[   47.725679][ T1348] calling  acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] @ 1348
[   47.731550][   T10] mpt2sas_cm0: handle(0xa) sas_address(0x4433221106000000) port_type(0x1)
[   47.733755][ T1348] initcall acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] returned -17 after 0 usecs
LKP: ttyS0: 1557: Kernel tests: Boot OK!
[   47.813656][ T1188] calling  acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] @ 1188
LKP: ttyS0: 1557[   47.821893][ T1188] initcall acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] returned -17 after 0 usecs
: HOSTNAME lkp-hsw-4ex1, MAC a0:36:9f:18:d6:a8, kernel 6.1.0-rc5-00020-g6919cda8e0f1 1

[   47.858391][ T1139] initcall acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] returned -17 after 0 usecs
1;39mLSB: OpenIP[   47.891687][ T1403] initcall acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] returned -17 after 0 usecs
         Startin[   47.920789][ T1308] calling  acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] @ 1308
ernel image with[   47.964612][ T1250] initcall acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] returned -17 after 0 usecs
[   47.981973][ T1049] mpt2sas_cm0: handle(0xb) sas_address(0x4433221102000000) port_type(0x1)
[   47.997665][ T1400] calling  acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] @ 1400
[   48.005888][ T1400] initcall acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] returned -17 after 0 usecs
[   48.030661][ T1244] calling  acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] @ 1244
[   48.048220][ T1244] initcall acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] returned -17 after 1 usecs
[   48.080604][ T1323] calling  acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] @ 1323
[   48.088824][ T1323] initcall acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] returned -17 after 0 usecs
[   48.117589][ T1329] calling  acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] @ 1329
[   48.125821][ T1329] initcall acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] returned -17 after 0 usecs
[   48.157665][ T1386] calling  acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] @ 1386
[   48.165891][ T1386] initcall acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] returned -17 after 0 usecs
[   48.190641][ T1172] calling  acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] @ 1172
[   48.198872][ T1172] initcall acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] returned -17 after 0 usecs
[   48.223827][ T1182] calling  acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] @ 1182
[   48.232051][ T1182] initcall acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] returned -17 after 0 usecs
[   48.257621][ T1172] calling  acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] @ 1172
[   48.265845][ T1172] initcall acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] returned -17 after 0 usecs
[   48.290648][ T1182] calling  acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] @ 1182
[   48.298879][ T1182] initcall acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] returned -17 after 0 usecs
[   48.324764][ T1174] calling  acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] @ 1174
[   48.332987][ T1174] initcall acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] returned -17 after 0 usecs
[   48.362514][ T1182] calling  acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] @ 1182
[   48.370753][ T1182] initcall acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] returned -17 after 0 usecs
[   48.395812][ T1164] calling  acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] @ 1164
[   48.404038][ T1164] initcall acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] returned -17 after 0 usecs
[   48.428624][ T1433] calling  acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] @ 1433
[   48.436849][ T1433] initcall acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] returned -17 after 0 usecs
[   48.461603][ T1194] calling  acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] @ 1194
[   48.469838][ T1194] initcall acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] returned -17 after 0 usecs
[   48.500616][ T1256] calling  acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] @ 1256
[   48.508844][ T1256] initcall acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] returned -17 after 0 usecs
[   48.534683][ T1272] calling  acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] @ 1272
[   48.542912][ T1272] initcall acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] returned -17 after 0 usecs
[   48.568818][ T1448] calling  acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] @ 1448
[   48.577050][ T1448] initcall acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] returned -17 after 0 usecs
[   48.599752][ T1179] calling  acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] @ 1179
[   48.607979][ T1179] initcall acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] returned -17 after 0 usecs
[   48.633588][ T1201] calling  acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] @ 1201
[   48.641814][ T1201] initcall acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] returned -17 after 0 usecs
[   48.666744][ T1154] calling  acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] @ 1154
[   48.674963][ T1154] initcall acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] returned -17 after 0 usecs
[   48.699717][ T1254] calling  acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] @ 1254
[   48.707936][ T1254] initcall acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] returned -17 after 0 usecs
[   48.732573][ T1377] calling  acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] @ 1377
[   48.740793][ T1377] initcall acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] returned -17 after 0 usecs
[   48.765675][ T1205] calling  acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] @ 1205
[   48.773900][ T1205] initcall acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] returned -17 after 0 usecs
[   48.799689][ T1144] calling  acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] @ 1144
[   48.807917][ T1144] initcall acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] returned -17 after 0 usecs
[   48.832714][ T1279] calling  acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] @ 1279
[   48.840934][ T1279] initcall acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] returned -17 after 0 usecs
[   48.865744][ T1455] calling  acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] @ 1455
[   48.873958][ T1455] initcall acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] returned -17 after 0 usecs
[   48.898739][ T1157] calling  acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] @ 1157
[   48.906958][ T1157] initcall acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] returned -17 after 0 usecs
[   48.929572][ T1116] calling  acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] @ 1116
[   48.937800][ T1116] initcall acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] returned -17 after 0 usecs
[   48.964634][ T1114] calling  acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] @ 1114
[   48.972875][ T1114] initcall acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] returned -17 after 0 usecs
[   48.999693][ T1453] calling  acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] @ 1453
[   49.007920][ T1453] initcall acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] returned -17 after 0 usecs
[   49.032644][ T1424] calling  acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] @ 1424
[   49.040877][ T1424] initcall acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] returned -17 after 0 usecs
[   49.065670][ T1459] calling  acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] @ 1459
[   49.073895][ T1459] initcall acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] returned -17 after 0 usecs
[   49.098637][ T1176] calling  acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] @ 1176
[   49.106857][ T1176] initcall acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] returned -17 after 0 usecs
[   49.131758][ T1180] calling  acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] @ 1180
[   49.139978][ T1180] initcall acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] returned -17 after 0 usecs
[   49.167592][ T1212] calling  acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] @ 1212
[   49.175834][ T1212] initcall acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] returned -17 after 0 usecs
[   49.200524][ T1400] calling  acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] @ 1400
[   49.208755][ T1400] initcall acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] returned -17 after 0 usecs
[   49.233747][ T1161] calling  acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] @ 1161
[   49.241976][ T1161] initcall acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] returned -17 after 1 usecs
[   49.272126][ T1176] calling  dax_pmem_init+0x0/0x1000 [dax_pmem] @ 1176
[   49.279776][ T1176] initcall dax_pmem_init+0x0/0x1000 [dax_pmem] returned 0 after 112 usecs
[   49.289628][ T1143] calling  acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] @ 1143
[   49.289630][ T1179] calling  intel_rapl_msr_driver_init+0x0/0x1000 [intel_rapl_msr] @ 1179
[   49.289743][ T1180] calling  nd_btt_init+0x0/0x1000 [nd_btt] @ 1180
[   49.289757][ T1180] initcall nd_btt_init+0x0/0x1000 [nd_btt] returned 0 after 6 usecs
[   49.297704][ T1143] initcall acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] returned -17 after 0 usecs
[   49.333352][ T1157] calling  init_sg+0x0/0x1000 [sg] @ 1157
[   49.333453][   T18] intel_rapl_common: Found RAPL domain package
[   49.339784][ T1157] scsi 4:0:0:0: Attached scsi generic sg0 type 5
[   49.346385][   T18] intel_rapl_common: Found RAPL domain dram
[   49.353294][ T1157] initcall init_sg+0x0/0x1000 [sg] returned 0 after 13617 usecs
[   49.359702][   T18] intel_rapl_common: DRAM domain energy unit 15300pj
[   49.360344][  T104] intel_rapl_common: Found RAPL domain package
[   49.382912][  T104] intel_rapl_common: Found RAPL domain dram
[   49.389457][  T104] intel_rapl_common: DRAM domain energy unit 15300pj
[   49.397492][  T195] intel_rapl_common: Found RAPL domain package
[   49.404329][  T195] intel_rapl_common: Found RAPL domain dram
[   49.410864][  T195] intel_rapl_common: DRAM domain energy unit 15300pj
[   49.418957][  T286] intel_rapl_common: Found RAPL domain package
[   49.425800][  T286] intel_rapl_common: Found RAPL domain dram
[   49.432338][  T286] intel_rapl_common: DRAM domain energy unit 15300pj
[   49.440666][ T1163] calling  acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] @ 1163
[   49.448892][ T1163] initcall acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] returned -17 after 0 usecs
[   49.459250][ T1453] calling  nd_pmem_driver_init+0x0/0x1000 [nd_pmem] @ 1453
[   49.459299][ T1179] initcall intel_rapl_msr_driver_init+0x0/0x1000 [intel_rapl_msr] returned 0 after 10407 usecs
[   49.467220][ T1453] nd_pmem namespace0.0: unable to guarantee persistence of writes
[   49.501674][ T1123] calling  acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] @ 1123
[   49.519391][ T1123] initcall acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] returned -17 after 1 usecs
[   49.731892][ T1160] calling  acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] @ 1160
[   49.740132][ T1160] initcall acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] returned -17 after 1 usecs
[   49.975288][ T1453] memmap_init_zone_device initialised 31457280 pages in 467ms
[   49.984139][ T1453] nd_pmem namespace2.0: unable to guarantee persistence of writes
[   49.996022][ T1117] calling  acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] @ 1117
[   50.004257][ T1117] initcall acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] returned -17 after 0 usecs
[   50.305800][ T1371] calling  acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] @ 1371
[   50.314019][ T1371] initcall acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] returned -17 after 0 usecs
[   50.515296][ T1453] memmap_init_zone_device initialised 31457280 pages in 504ms
[   50.524101][ T1453] nd_pmem namespace3.0: unable to guarantee persistence of writes
[   50.533782][ T1189] calling  acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] @ 1189
[   50.542000][ T1189] initcall acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] returned -17 after 0 usecs
[   50.768669][ T1258] calling  acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] @ 1258
[   50.776911][ T1258] initcall acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] returned -17 after 0 usecs
[   50.957403][ T1453] memmap_init_zone_device initialised 31457280 pages in 394ms
[   50.966177][ T1453] nd_pmem namespace1.0: unable to guarantee persistence of writes
[   50.981980][ T1360] calling  acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] @ 1360
[   50.990199][ T1360] initcall acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] returned -17 after 0 usecs
[   51.216958][ T1374] calling  acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] @ 1374
[   51.225187][ T1374] initcall acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] returned -17 after 0 usecs
[   51.449288][ T1453] memmap_init_zone_device initialised 31457280 pages in 456ms
[   51.458003][ T1453] initcall nd_pmem_driver_init+0x0/0x1000 [nd_pmem] returned 0 after 232816 usecs
[   51.478135][ T1225] calling  acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] @ 1225
[   51.486363][ T1225] initcall acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] returned -17 after 0 usecs
[   51.518845][ T1274] calling  acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] @ 1274
[   51.527057][ T1274] initcall acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] returned -17 after 0 usecs
[   51.557753][ T1141] calling  acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] @ 1141
[   51.565971][ T1141] initcall acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] returned -17 after 0 usecs
[   51.594869][ T1177] calling  acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] @ 1177
[   51.603096][ T1177] initcall acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] returned -17 after 0 usecs
[   51.625637][ T1465] calling  acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] @ 1465
[   51.633881][ T1465] initcall acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] returned -17 after 0 usecs
[   51.658670][ T1210] calling  acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] @ 1210
[   51.666890][ T1210] initcall acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] returned -17 after 0 usecs
[   51.696815][ T1208] calling  acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] @ 1208
[   51.705054][ T1208] initcall acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] returned -17 after 0 usecs
[   51.733640][ T1350] calling  acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] @ 1350
[   51.741874][ T1350] initcall acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] returned -17 after 0 usecs
[   51.766751][ T1446] calling  acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] @ 1446
[   51.774966][ T1446] initcall acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] returned -17 after 0 usecs
[   51.799801][ T1366] calling  acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] @ 1366
[   51.808039][ T1366] initcall acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] returned -17 after 0 usecs
[   51.832793][ T1286] calling  acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] @ 1286
[   51.841014][ T1286] initcall acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] returned -17 after 0 usecs
[   51.869731][ T1252] calling  acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] @ 1252
[   51.877950][ T1252] initcall acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] returned -17 after 0 usecs
[   51.906594][ T1322] calling  acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] @ 1322
[   51.914819][ T1322] initcall acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] returned -17 after 0 usecs
[   51.939823][ T1412] calling  acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] @ 1412
[   51.948042][ T1412] initcall acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] returned -17 after 0 usecs
[   51.973780][ T1380] calling  acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] @ 1380
[   51.981998][ T1380] initcall acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] returned -17 after 0 usecs
[   52.010719][ T1388] calling  acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] @ 1388
[   52.018935][ T1388] initcall acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] returned -17 after 0 usecs
[   52.043681][ T1134] calling  acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] @ 1134
[   52.051906][ T1134] initcall acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] returned -17 after 0 usecs
[   52.076787][ T1450] calling  acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] @ 1450
[   52.085010][ T1450] initcall acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] returned -17 after 0 usecs
[   52.109787][ T1287] calling  acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] @ 1287
[   52.118010][ T1287] initcall acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] returned -17 after 0 usecs
[   52.143657][ T1262] calling  acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] @ 1262
[   52.151878][ T1262] initcall acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] returned -17 after 0 usecs
[   52.176753][ T1369] calling  acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] @ 1369
[   52.184985][ T1369] initcall acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] returned -17 after 0 usecs
[   52.209733][ T1219] calling  acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] @ 1219
[   52.217955][ T1219] initcall acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] returned -17 after 0 usecs
[   52.242760][ T1417] calling  acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] @ 1417
[   52.250979][ T1417] initcall acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] returned -17 after 0 usecs
[   52.275782][ T1182] calling  acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] @ 1182
[   52.284010][ T1182] initcall acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] returned -17 after 0 usecs
[   52.308874][ T1325] calling  acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] @ 1325
[   52.317105][ T1325] initcall acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] returned -17 after 0 usecs
[   52.341695][ T1282] calling  acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] @ 1282
[   52.349923][ T1282] initcall acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] returned -17 after 0 usecs
[   52.377578][ T1127] calling  acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] @ 1127
[   52.385800][ T1127] initcall acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] returned -17 after 0 usecs
[   52.410707][ T1266] calling  acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] @ 1266
[   52.418926][ T1266] initcall acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] returned -17 after 0 usecs
[   52.444749][ T1321] calling  acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] @ 1321
[   52.452965][ T1321] initcall acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] returned -17 after 0 usecs
[   52.477818][ T1324] calling  acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] @ 1324
[   52.486042][ T1324] initcall acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] returned -17 after 0 usecs
[   52.512907][ T1351] calling  acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] @ 1351
[   52.521135][ T1351] initcall acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] returned -17 after 0 usecs
[   52.545849][ T1227] calling  acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] @ 1227
[   52.554065][ T1227] initcall acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] returned -17 after 0 usecs
[   52.578765][ T1120] calling  acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] @ 1120
[   52.586980][ T1120] initcall acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] returned -17 after 0 usecs
[   52.611668][ T1119] calling  acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] @ 1119
[   52.629173][ T1119] initcall acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] returned -17 after 0 usecs
[   52.653771][ T1231] calling  acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] @ 1231
[   52.661991][ T1231] initcall acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] returned -17 after 0 usecs
[   52.687723][ T1172] calling  acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] @ 1172
[   52.695942][ T1172] initcall acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] returned -17 after 0 usecs
[   52.724792][ T1191] calling  acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] @ 1191
[   52.733009][ T1191] initcall acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] returned -17 after 0 usecs
[   52.761669][ T1178] calling  acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] @ 1178
[   52.769894][ T1178] initcall acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] returned -17 after 0 usecs
[   52.794738][ T1224] calling  acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] @ 1224
[   52.802957][ T1224] initcall acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] returned -17 after 0 usecs
[   52.827742][ T1436] calling  acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] @ 1436
[   52.835964][ T1436] initcall acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] returned -17 after 0 usecs
[   52.860744][ T1196] calling  acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] @ 1196
[   52.868959][ T1196] initcall acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] returned -17 after 0 usecs
[   52.893665][ T1280] calling  acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] @ 1280
[   52.901881][ T1280] initcall acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] returned -17 after 0 usecs
[   52.926820][ T1347] calling  acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] @ 1347
[   52.935037][ T1347] initcall acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] returned -17 after 0 usecs
[   52.959819][ T1194] calling  acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] @ 1194
[   52.968041][ T1194] initcall acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] returned -17 after 0 usecs
[   52.996825][ T1283] calling  acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] @ 1283
[   53.005055][ T1283] initcall acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] returned -17 after 0 usecs
[   53.031776][ T1383] calling  acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] @ 1383
[   53.039997][ T1383] initcall acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] returned -17 after 0 usecs
[   53.064771][ T1246] calling  acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] @ 1246
[   53.073001][ T1246] initcall acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] returned -17 after 0 usecs
[   53.098622][ T1133] calling  acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] @ 1133
[   53.106862][ T1133] initcall acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] returned -17 after 0 usecs
[   53.132644][ T1264] calling  acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] @ 1264
[   53.140873][ T1264] initcall acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] returned -17 after 0 usecs
[   53.169790][ T1167] calling  acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] @ 1167
[   53.178006][ T1167] initcall acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] returned -17 after 0 usecs
[   53.202961][ T1323] calling  acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] @ 1323
[   53.211176][ T1323] initcall acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] returned -17 after 0 usecs
[   53.235720][ T1155] calling  acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] @ 1155
[   53.243948][ T1155] initcall acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] returned -17 after 0 usecs
[   53.269790][ T1356] calling  acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] @ 1356
[   53.278005][ T1356] initcall acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] returned -17 after 0 usecs
[   53.302904][ T1273] calling  acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] @ 1273
[   53.311134][ T1273] initcall acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] returned -17 after 0 usecs
[   53.335779][ T1165] calling  acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] @ 1165
[   53.343990][ T1165] initcall acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] returned -17 after 0 usecs
[   53.358559][ T1598] LKP: stdout: 1557: Kernel tests: Boot OK!
[   53.358564][ T1598] 
[   53.374682][ T1281] calling  acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] @ 1281
[   53.382908][ T1281] initcall acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] returned -17 after 0 usecs
[   53.419923][ T1410] calling  acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] @ 1410
[   53.428143][ T1410] initcall acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] returned -17 after 0 usecs
[   53.452752][ T1200] calling  acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] @ 1200
[   53.460991][ T1200] initcall acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] returned -17 after 0 usecs
[   53.489652][ T1348] calling  acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] @ 1348
[   53.497874][ T1348] initcall acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] returned -17 after 0 usecs
[   53.522692][ T1226] calling  acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] @ 1226
[   53.530918][ T1226] initcall acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] returned -17 after 0 usecs
[   53.556604][ T1216] calling  acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] @ 1216
[   53.564844][ T1216] initcall acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] returned -17 after 0 usecs
[   53.589723][ T1354] calling  acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] @ 1354
[   53.597941][ T1354] initcall acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] returned -17 after 0 usecs
[   53.612731][  T754] mpt2sas_cm0: port enable: SUCCESS
[   53.620205][  T754] scsi 6:0:0:0: Direct-Access     ATA      INTEL SSDSC2BA40 0150 PQ: 0 ANSI: 6
[   53.630176][  T754] scsi 6:0:0:0: SATA: handle(0x000b), sas_addr(0x4433221102000000), phy(2), device_name(0x55cd2e404c2e98e3)
[   53.642951][  T754] scsi 6:0:0:0: enclosure logical id (0x500605b005c3d950), slot(1) 
[   53.651931][  T754] scsi 6:0:0:0: atapi(n), ncq(y), asyn_notify(n), smart(y), fua(y), sw_preserve(y)
[   53.662301][  T754] scsi 6:0:0:0: qdepth(32), tagged(1), scsi_level(7), cmd_que(1)
[   53.671210][ T1346] calling  acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] @ 1346
[   53.676026][  T754]  end_device-6:0: add: handle(0x000b), sas_addr(0x4433221102000000)
[   53.679287][ T1346] initcall acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] returned -17 after 0 usecs
[   53.689277][  T754] scsi 6:0:1:0: Direct-Access     SEAGATE  ST9300653SS      0004 PQ: 0 ANSI: 6
[   53.708535][  T754] scsi 6:0:1:0: SSP: handle(0x0009), sas_addr(0x5000c50067bdf9c1), phy(0), device_name(0x5000c50067bdf9c0)
[   53.721214][  T754] scsi 6:0:1:0: enclosure logical id (0x500605b005c3d950), slot(3) 
[   53.730103][  T754] scsi 6:0:1:0: qdepth(254), tagged(1), scsi_level(7), cmd_que(1)
[   53.740739][  T754]  end_device-6:1: add: handle(0x0009), sas_addr(0x5000c50067bdf9c1)
[   53.750690][  T754] scsi 6:0:2:0: Direct-Access     ATA      INTEL SSDSC2BB80 0370 PQ: 0 ANSI: 6
[   53.760654][  T754] scsi 6:0:2:0: SATA: handle(0x000a), sas_addr(0x4433221106000000), phy(6), device_name(0x55cd2e40003aeb61)
[   53.773422][  T754] scsi 6:0:2:0: enclosure logical id (0x500605b005c3d950), slot(5) 
[   53.782376][  T754] scsi 6:0:2:0: atapi(n), ncq(y), asyn_notify(n), smart(y), fua(y), sw_preserve(y)
[   53.792745][  T754] scsi 6:0:2:0: qdepth(32), tagged(1), scsi_level(7), cmd_que(1)
[   53.802025][ T1195] calling  acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] @ 1195
[   53.803187][  T754]  end_device-6:2: add: handle(0x000a), sas_addr(0x4433221106000000)
[   53.810099][ T1195] initcall acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] returned -17 after 0 usecs
[   53.819149][  T754] scsi 6:0:0:0: Attached scsi generic sg1 type 0
[   53.836546][  T754] scsi 6:0:1:0: Attached scsi generic sg2 type 0
[   53.843696][  T754] scsi 6:0:2:0: Attached scsi generic sg3 type 0
[   53.855325][ T1259] calling  acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] @ 1259
[   53.863565][ T1259] initcall acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] returned -17 after 0 usecs
[   53.874131][ T1157] calling  cdrom_init+0x0/0x1000 [cdrom] @ 1157
[   53.881069][ T1157] initcall cdrom_init+0x0/0x1000 [cdrom] returned 0 after 6 usecs
[   53.890039][ T1196] calling  crc64_rocksoft_mod_init+0x0/0x1000 [crc64_rocksoft] @ 1196
[   53.899474][ T1157] calling  init_sr+0x0/0x1000 [sr_mod] @ 1157
[   53.906382][ T2250] calling  crc64_rocksoft_init+0x0/0x1000 [crc64_rocksoft_generic] @ 2250
[   53.915943][ T2250] initcall crc64_rocksoft_init+0x0/0x1000 [crc64_rocksoft_generic] returned 0 after 67 usecs
[   53.937545][ T1421] calling  acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] @ 1421
[   53.937757][ T1157] sr 4:0:0:0: [sr0] scsi3-mmc drive: 24x/24x writer dvd-ram cd/rw xa/form2 cdda tray
[   53.945621][ T1421] initcall acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] returned -17 after 0 usecs
[   53.956022][ T1157] cdrom: Uniform CD-ROM driver Revision: 3.20
[   53.966035][ T1196] initcall crc64_rocksoft_mod_init+0x0/0x1000 [crc64_rocksoft] returned 0 after 20413 usecs
[   54.001995][ T1246] calling  init_sd+0x0/0x1000 [sd_mod] @ 1246
[   54.012796][ T1157] sr 4:0:0:0: Attached scsi CD-ROM sr0
[   54.018913][ T1246] initcall init_sd+0x0/0x1000 [sd_mod] returned 0 after 10173 usecs
[   54.018929][ T1157] initcall init_sr+0x0/0x1000 [sr_mod] returned 0 after 10180 usecs
[   54.019566][  T747] sd 6:0:2:0: [sdc] 1562824368 512-byte logical blocks: (800 GB/745 GiB)
[   54.019569][  T747] sd 6:0:2:0: [sdc] 4096-byte physical blocks
[   54.019642][  T200] sd 6:0:1:0: [sda] 585937500 512-byte logical blocks: (300 GB/279 GiB)
[   54.019723][  T754] sd 6:0:0:0: [sdb] 781422768 512-byte logical blocks: (400 GB/373 GiB)
[   54.019726][  T754] sd 6:0:0:0: [sdb] 4096-byte physical blocks
[   54.019921][  T200] sd 6:0:1:0: [sda] Write Protect is off
[   54.019923][  T200] sd 6:0:1:0: [sda] Mode Sense: d7 00 10 08
[   54.020073][  T747] sd 6:0:2:0: [sdc] Write Protect is off
[   54.020083][  T747] sd 6:0:2:0: [sdc] Mode Sense: 7f 00 10 08
[   54.020320][  T747] sd 6:0:2:0: [sdc] Write cache: enabled, read cache: enabled, supports DPO and FUA
[   54.020365][  T200] sd 6:0:1:0: [sda] Write cache: enabled, read cache: enabled, supports DPO and FUA
[   54.020444][  T754] sd 6:0:0:0: [sdb] Write Protect is off
[   54.020446][  T754] sd 6:0:0:0: [sdb] Mode Sense: 7f 00 10 08
[   54.021024][  T754] sd 6:0:0:0: [sdb] Write cache: enabled, read cache: enabled, supports DPO and FUA
[   54.022927][  T747]  sdc: sdc1
[   54.023103][  T747] sd 6:0:2:0: [sdc] Attached SCSI disk
[   54.023773][  T200]  sda: sda1
[   54.023926][  T200] sd 6:0:1:0: [sda] Attached SCSI disk
[   54.024404][  T754]  sdb: sdb1
[   54.024514][  T754] sd 6:0:0:0: [sdb] Attached SCSI disk
[   54.090879][ T1203] calling  acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] @ 1203
[   54.090892][ T2271] calling  libcrc32c_mod_init+0x0/0x1000 [libcrc32c] @ 2271
[   54.090904][ T2271] initcall libcrc32c_mod_init+0x0/0x1000 [libcrc32c] returned 0 after 2 usecs
[   54.176569][ T2272] calling  init_module+0x0/0x1000 [raid6_pq] @ 2272
[   54.184488][ T1203] initcall acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] returned -17 after 0 usecs
[   54.208701][ T2272] raid6: avx2x4   gen() 28993 MB/s
[   54.242702][ T2272] raid6: avx2x2   gen() 27987 MB/s
[   54.264702][ T2272] raid6: avx2x1   gen() 26540 MB/s
[   54.270368][ T2272] raid6: using algorithm avx2x4 gen() 28993 MB/s
[   54.293702][ T2272] raid6: .... xor() 7940 MB/s, rmw enabled
[   54.300130][ T2272] raid6: using avx2x2 recovery algorithm
[   54.306381][ T2272] initcall init_module+0x0/0x1000 [raid6_pq] returned 0 after 113926 usecs
[   54.317754][ T2271] calling  calibrate_xor_blocks+0x0/0xf3e [xor] @ 2271
[   54.325360][ T2271] xor: automatically using best checksumming function   avx       
[   54.334180][ T2271] initcall calibrate_xor_blocks+0x0/0xf3e [xor] returned 0 after 8819 usecs
[   54.346443][ T2272] calling  blake2b_mod_init+0x0/0x1000 [blake2b_generic] @ 2272
[   54.355260][ T2272] initcall blake2b_mod_init+0x0/0x1000 [blake2b_generic] returned 0 after 304 usecs
[   54.377471][ T1398] calling  acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] @ 1398
[   54.385692][ T1398] initcall acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] returned -17 after 0 usecs
[   54.629788][ T1403] calling  acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] @ 1403
[   54.630111][ T2272] calling  init_btrfs_fs+0x0/0x148 [btrfs] @ 2272
[   54.637866][ T1403] initcall acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] returned -17 after 0 usecs
[   54.645259][ T2272] Btrfs loaded, crc32c=crc32c-intel, zoned=no, fsverity=no
[   54.663271][ T2272] initcall init_btrfs_fs+0x0/0x148 [btrfs] returned 0 after 18412 usecs
[   54.673538][ T1196] BTRFS: device fsid ac875424-820a-4bf2-8f58-8853947607d6 devid 1 transid 8514 /dev/sdb1 scanned by systemd-udevd (1196)
[   54.687885][ T1323] BTRFS: device fsid 09c2e0e8-416a-487a-92a7-1a1437a77e20 devid 1 transid 13 /dev/sdc1 scanned by systemd-udevd (1323)
[   54.706846][ T1387] calling  acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] @ 1387
[   54.715075][ T1387] initcall acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] returned -17 after 0 usecs
[   54.748756][ T1355] calling  acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] @ 1355
[   54.756976][ T1355] initcall acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] returned -17 after 0 usecs
[   54.789626][ T1113] calling  acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] @ 1113
[   54.797863][ T1113] initcall acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] returned -17 after 0 usecs
[   54.834628][ T1148] calling  acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] @ 1148
[   54.842857][ T1148] initcall acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] returned -17 after 0 usecs
[   54.880675][ T1405] calling  acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] @ 1405
[   54.888903][ T1405] initcall acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] returned -17 after 0 usecs
[   54.925598][ T1445] calling  acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] @ 1445
[   54.933824][ T1445] initcall acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] returned -17 after 0 usecs
[   54.970627][ T1463] calling  acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] @ 1463
[   54.978864][ T1463] initcall acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] returned -17 after 0 usecs
[   55.004748][ T1229] calling  acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] @ 1229
[   55.012969][ T1229] initcall acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] returned -17 after 0 usecs
[   55.045727][ T1187] calling  acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] @ 1187
[   55.053938][ T1187] initcall acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] returned -17 after 0 usecs
[   55.087630][ T1313] calling  acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] @ 1313
[   55.095865][ T1313] initcall acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] returned -17 after 0 usecs
[   55.127640][ T1269] calling  acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] @ 1269
[   55.135869][ T1269] initcall acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] returned -17 after 0 usecs
[   55.160627][ T1327] calling  acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] @ 1327
[   55.168847][ T1327] initcall acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] returned -17 after 0 usecs
[   55.193751][ T1240] calling  acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] @ 1240
[   55.201969][ T1240] initcall acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] returned -17 after 0 usecs
[   55.238667][ T1411] calling  acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] @ 1411
[   55.246888][ T1411] initcall acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] returned -17 after 0 usecs
[   55.283653][ T1118] calling  acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] @ 1118
[   55.291889][ T1118] initcall acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] returned -17 after 0 usecs
[   55.328717][ T1438] calling  acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] @ 1438
[   55.336941][ T1438] initcall acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] returned -17 after 0 usecs
[   55.369717][ T1170] calling  acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] @ 1170
[   55.377942][ T1170] initcall acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] returned -17 after 0 usecs
[   55.405663][ T1232] calling  acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] @ 1232
[   55.413886][ T1232] initcall acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] returned -17 after 0 usecs
[   55.451625][ T1162] calling  acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] @ 1162
[   55.459865][ T1162] initcall acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] returned -17 after 0 usecs
[   55.492830][ T1132] calling  acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] @ 1132
[   55.501067][ T1132] initcall acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] returned -17 after 0 usecs
[   55.533676][ T1292] calling  acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] @ 1292
[   55.541896][ T1292] initcall acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] returned -17 after 0 usecs
[   55.578674][ T1268] calling  acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] @ 1268
[   55.586899][ T1268] initcall acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] returned -17 after 0 usecs
[   55.619688][ T1126] calling  acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] @ 1126
[   55.627909][ T1126] initcall acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] returned -17 after 0 usecs
[   55.656628][ T1256] calling  acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] @ 1256
[   55.664849][ T1256] initcall acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] returned -17 after 0 usecs
[   55.695664][ T1135] calling  acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] @ 1135
[   55.703883][ T1135] initcall acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] returned -17 after 0 usecs
[   55.736833][ T1467] calling  acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] @ 1467
[   55.754432][ T1467] initcall acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] returned -17 after 0 usecs
[   55.782692][ T1222] calling  acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] @ 1222
[   55.790920][ T1222] initcall acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] returned -17 after 0 usecs
[   55.815618][ T1416] calling  acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] @ 1416
[   55.823852][ T1416] initcall acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] returned -17 after 0 usecs
[   55.848686][ T1297] calling  acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] @ 1297
[   55.856913][ T1297] initcall acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] returned -17 after 0 usecs
[   55.881826][ T1289] calling  acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] @ 1289
[   55.890044][ T1289] initcall acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] returned -17 after 0 usecs
[   55.923635][ T1243] calling  acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] @ 1243
[   55.931877][ T1243] initcall acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] returned -17 after 0 usecs
[   55.960624][ T1121] calling  acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] @ 1121
[   55.968849][ T1121] initcall acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] returned -17 after 0 usecs
[   55.993684][ T1173] calling  acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] @ 1173
[   56.001904][ T1173] initcall acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] returned -17 after 0 usecs
[   56.030677][ T1228] calling  acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] @ 1228
[   56.038907][ T1228] initcall acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] returned -17 after 0 usecs
[   56.063787][ T1312] calling  acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] @ 1312
[   56.072017][ T1312] initcall acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] returned -17 after 0 usecs
[   56.103594][ T1185] calling  acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] @ 1185
[   56.111827][ T1185] initcall acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] returned -17 after 0 usecs
[   56.136769][ T1353] calling  acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] @ 1353
[   56.144998][ T1353] initcall acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] returned -17 after 0 usecs
[   56.173613][ T1253] calling  acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] @ 1253
[   56.181844][ T1253] initcall acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] returned -17 after 0 usecs
[   56.206569][ T1430] calling  acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] @ 1430
[   56.214801][ T1430] initcall acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] returned -17 after 0 usecs
[   56.239749][ T1168] calling  acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] @ 1168
[   56.247975][ T1168] initcall acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] returned -17 after 0 usecs
[   56.276638][ T1420] calling  acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] @ 1420
[   56.284855][ T1420] initcall acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] returned -17 after 0 usecs
[   56.309670][ T1368] calling  acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] @ 1368
[   56.317902][ T1368] initcall acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] returned -17 after 0 usecs
[   56.343529][ T1241] calling  acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] @ 1241
[   56.344644][ T1598] LKP: stdout: 1557: HOSTNAME lkp-hsw-4ex1, MAC a0:36:9f:18:d6:a8, kernel 6.1.0-rc5-00020-g6919cda8e0f1 1
[   56.351605][ T1241] initcall acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] returned -17 after 0 usecs
[   56.351754][ T1598] 
[   56.396527][ T1277] calling  acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] @ 1277
[   56.404752][ T1277] initcall acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] returned -17 after 0 usecs
[   56.427606][ T1211] calling  acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] @ 1211
[   56.435837][ T1211] initcall acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] returned -17 after 0 usecs
[   56.458617][ T1308] calling  acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] @ 1308
[   56.466848][ T1308] initcall acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] returned -17 after 0 usecs
[   56.489673][ T1295] calling  acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] @ 1295
[   56.497901][ T1295] initcall acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] returned -17 after 0 usecs
[   56.520628][ T1391] calling  acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] @ 1391
[   56.528855][ T1391] initcall acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] returned -17 after 0 usecs
[   56.551589][ T1209] calling  acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] @ 1209
[   56.559816][ T1209] initcall acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] returned -17 after 0 usecs
[   56.582630][ T1174] calling  acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] @ 1174
[   56.590860][ T1174] initcall acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] returned -17 after 0 usecs
[   56.617650][ T1267] calling  acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] @ 1267
[   56.625878][ T1267] initcall acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] returned -17 after 0 usecs
[   56.648499][ T1217] calling  acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] @ 1217
[   56.656747][ T1217] initcall acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] returned -17 after 0 usecs
[   56.679593][ T1124] calling  acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] @ 1124
[   56.682266][ T1598] install debs round one: dpkg -i --force-confdef --force-depends /opt/deb/ntpdate_1%3a4.2.8p15+dfsg-1_amd64.deb
[   56.687674][ T1124] initcall acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] returned -17 after 0 usecs
[   56.687824][ T1598] 
[   56.688560][ T1598] /opt/deb/sysstat_12.5.2-2_amd64.deb
[   56.713805][ T1598] 
[   56.723235][ T1598] /opt/deb/libssl1.1_1.1.1n-0+deb11u3_amd64.deb
[   56.723237][ T1598] 
[   56.733441][ T1598] /opt/deb/libdeflate0_1.7-1_amd64.deb
[   56.733445][ T1598] 
[   56.743200][ T1598] /opt/deb/gtk-update-icon-cache_3.24.24-4+deb11u2_amd64.deb
[   56.743202][ T1598] 
[   56.755100][ T1598] /opt/deb/libavahi-common-data_0.8-5+deb11u1_amd64.deb
[   56.755102][ T1598] 
[   56.765567][ T1115] calling  acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] @ 1115
[   56.766273][ T1598] /opt/deb/libasound2-data_1.2.4-1.1_all.deb
[   56.773642][ T1115] initcall acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] returned -17 after 0 usecs
[   56.773797][ T1598] 
[   56.794041][ T1598] /opt/deb/ca-certificates-java_20190909_all.deb
[   56.794043][ T1598] 
[   56.804351][ T1598] /opt/deb/libatomic1_10.2.1-6_amd64.deb
[   56.804353][ T1598] 
[   56.813934][ T1598] /opt/deb/libquadmath0_10.2.1-6_amd64.deb
[   56.813935][ T1598] 
[   56.823196][ T1235] calling  acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] @ 1235
[   56.824161][ T1598] /opt/deb/libgcc-10-dev_10.2.1-6_amd64.deb
[   56.831270][ T1235] initcall acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] returned -17 after 0 usecs
[   56.837702][ T1598] 
[   56.851452][ T1598] /opt/deb/lib32gcc-s1_10.2.1-6_amd64.deb
[   56.851456][ T1598] 
[   56.861043][ T1598] /opt/deb/gcc-10_10.2.1-6_amd64.deb
[   56.861045][ T1598] 
[   56.870144][ T1598] /opt/deb/gcc_4%3a10.2.1-1_amd64.deb
[   56.870149][ T1598] 
[   56.879334][ T1598] /opt/deb/g++-10_10.2.1-6_amd64.deb
[   56.879337][ T1598] 
[   56.888096][ T1270] calling  acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] @ 1270
[   56.888528][ T1598] /opt/deb/g++_4%3a10.2.1-1_amd64.deb
[   56.896175][ T1270] initcall acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] returned -17 after 0 usecs
[   56.896326][ T1598] 
[   56.915799][ T1598] /opt/deb/libatk1.0-data_2.36.0-2_all.deb
[   56.915801][ T1598] 
[   56.925592][ T1598] /opt/deb/libatk1.0-0_2.36.0-2_amd64.deb
[   56.925595][ T1598] 
[   56.935335][ T1598] /opt/deb/gir1.2-atk-1.0_2.36.0-2_amd64.deb
[   56.935336][ T1598] 
[   56.945304][ T1598] /opt/deb/libthai-data_0.1.28-3_all.deb
[   56.945305][ T1598] 
[   56.954842][ T1598] /opt/deb/libdatrie1_0.2.13-1_amd64.deb
[   56.954843][ T1598] 
[   56.964375][ T1598] /opt/deb/libdpkg-perl_1.20.12_all.deb
[   56.964378][ T1598] 
[   56.973420][ T1190] calling  acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] @ 1190
[   56.974035][ T1598] /opt/deb/libglib2.0-data_2.66.8-1_all.deb
[   56.981495][ T1190] initcall acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] returned -17 after 0 usecs
[   56.981641][ T1598] 
[   57.001679][ T1598] /opt/deb/python3-lib2to3_3.9.2-1_all.deb
[   57.001681][ T1598] 
[   57.021008][ T1598] /opt/deb/python3-distutils_3.9.2-1_all.deb
[   57.021009][ T1598] 
[   57.031029][ T1598] /opt/deb/libatk1.0-dev_2.36.0-2_amd64.deb
[   57.031031][ T1598] 
[   57.041130][ T1598] /opt/deb/libexpat1-dev_2.2.10-2+deb11u3_amd64.deb
[   57.041132][ T1598] 
[   57.051838][ T1598] /opt/deb/libdatrie-dev_0.2.13-1_amd64.deb
[   57.051842][ T1598] 
[   57.061240][ T1285] calling  acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] @ 1285
[   57.062035][ T1598] /opt/deb/libperl-dev_5.32.1-4+deb11u2_amd64.deb
[   57.069315][ T1285] initcall acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] returned -17 after 0 usecs
[   57.069460][ T1598] 
[   57.090072][ T1598] /opt/deb/libpython3.9_3.9.2-1_amd64.deb
[   57.090074][ T1598] 
[   57.099874][ T1598] /opt/deb/libpython3.9-dev_3.9.2-1_amd64.deb
[   57.099876][ T1598] 
[   57.109998][ T1598] /opt/deb/libpython3-dev_3.9.2-3_amd64.deb
[   57.109999][ T1598] 
[   57.120066][ T1598] /opt/deb/python3-pkg-resources_52.0.0-4_all.deb
[   57.120067][ T1598] 
[   57.130447][ T1454] calling  acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] @ 1454
[   57.130876][ T1598] /opt/deb/python3-pygments_2.7.1+dfsg-2.1_all.deb
[   57.138528][ T1454] initcall acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] returned -17 after 0 usecs
[   57.138672][ T1598] 
[   57.159392][ T1598] /opt/deb/python3-yaml_5.3.1-5_amd64.deb
[   57.159395][ T1598] 
[   57.168962][ T1598] /opt/deb/patch_2.7.6-7_amd64.deb
[   57.168964][ T1598] 
[   57.177972][ T1598] /opt/deb/python3.9-dev_3.9.2-1_amd64.deb
[   57.177973][ T1598] 
[   57.187720][ T1598] /opt/deb/python3-dev_3.9.2-3_amd64.deb
[   57.187721][ T1598] 
[   57.196783][ T1230] calling  acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] @ 1230
[   57.197482][ T1598] /opt/deb/python3-setuptools_52.0.0-4_all.deb
[   57.204855][ T1230] initcall acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] returned -17 after 0 usecs
[   57.205005][ T1598] 
[   57.225488][ T1598] Selecting previously unselected package ntpdate.
[   57.225493][ T1598] 
[   57.236762][ T1598] (Reading database ... 16440 files and directories currently installed.)
[   57.236765][ T1598] 
[   57.250158][ T1598] Preparing to unpack .../ntpdate_1%3a4.2.8p15+dfsg-1_amd64.deb ...
[   57.250161][ T1598] 
[   57.262432][ T1598] Unpacking ntpdate (1:4.2.8p15+dfsg-1) ...
[   57.262433][ T1598] 
[   57.271902][ T1365] calling  acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] @ 1365
[   57.272583][ T1598] Selecting previously unselected package sysstat.
[   57.279970][ T1365] initcall acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] returned -17 after 0 usecs
[   57.280120][ T1598] 
[   57.301175][ T1598] Preparing to unpack .../deb/sysstat_12.5.2-2_amd64.deb ...
[   57.301178][ T1598] 
[   57.312563][ T1598] Unpacking sysstat (12.5.2-2) ...
[   57.312565][ T1598] 
[   57.322106][ T1598] Preparing to unpack .../libssl1.1_1.1.1n-0+deb11u3_amd64.deb ...
[   57.322107][ T1598] 
[   57.334967][ T1598] Unpacking libssl1.1:amd64 (1.1.1n-0+deb11u3) over (1.1.1n-0+deb11u1) ...
[   57.334969][ T1598] 
[   57.348245][ T1598] Selecting previously unselected package libdeflate0:amd64.
[   57.348248][ T1598] 
[   57.359348][ T1192] calling  acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] @ 1192
[   57.360277][ T1598] Preparing to unpack .../libdeflate0_1.7-1_amd64.deb ...
[   57.367416][ T1192] initcall acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] returned -17 after 0 usecs
[   57.367563][ T1598] 
[   57.388972][ T1598] Unpacking libdeflate0:amd64 (1.7-1) ...
[   57.388974][ T1598] 
[   57.399158][ T1598] Selecting previously unselected package gtk-update-icon-cache.
[   57.399162][ T1598] 
[   57.411983][ T1598] Preparing to unpack .../gtk-update-icon-cache_3.24.24-4+deb11u2_amd64.deb ...
[   57.411985][ T1598] 
[   57.425799][ T1598] Unpacking gtk-update-icon-cache (3.24.24-4+deb11u2) ...
[   57.425800][ T1598] 
[   57.436521][ T1248] calling  acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] @ 1248
[   57.437801][ T1598] Selecting previously unselected package libavahi-common-data:amd64.
[   57.444601][ T1248] initcall acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] returned -17 after 0 usecs
[   57.444762][ T1598] 
[   57.446243][ T1598] Preparing to unpack .../libavahi-common-data_0.8-5+deb11u1_amd64.deb ...
[   57.466570][ T1598] 
[   57.479904][ T1598] Unpacking libavahi-common-data:amd64 (0.8-5+deb11u1) ...
[   57.479905][ T1598] 
[   57.491595][ T1598] Selecting previously unselected package libasound2-data.
[   57.491600][ T1598] 
[   57.503381][ T1598] Preparing to unpack .../libasound2-data_1.2.4-1.1_all.deb ...
[   57.503384][ T1598] 
[   57.514733][ T1223] calling  acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] @ 1223
[   57.515336][ T1598] Unpacking libasound2-data (1.2.4-1.1) ...
[   57.522809][ T1223] initcall acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] returned -17 after 0 usecs
[   57.522957][ T1598] 
[   57.543447][ T1598] Selecting previously unselected package ca-certificates-java.
[   57.543450][ T1598] 
[   57.555854][ T1598] Preparing to unpack .../ca-certificates-java_20190909_all.deb ...
[   57.555855][ T1598] 
[   57.568219][ T1598] Unpacking ca-certificates-java (20190909) ...
[   57.568220][ T1598] 
[   57.578909][ T1598] Selecting previously unselected package libatomic1:amd64.
[   57.578911][ T1598] 
[   57.589766][ T1198] calling  acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] @ 1198
[   57.590759][ T1598] Preparing to unpack .../libatomic1_10.2.1-6_amd64.deb ...
[   57.597842][ T1198] initcall acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] returned -17 after 0 usecs
[   57.597991][ T1598] 
1;39mSystem Logg[   57.632223][ T1598] Selecting previously unselected package libquadmath0:amd64.

[   57.645988][ T1598] Preparing to unpack .../libquadmath0_10.2.1-6_amd64.deb ...
[   57.645990][ T1598] 
[   57.657725][ T1598] Unpacking libquadmath0:amd64 (10.2.1-6) ...
[   57.657728][ T1598] 
[   57.667302][ T1218] calling  acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] @ 1218
[   57.668369][ T1598] Selecting previously unselected package libgcc-10-dev:amd64.
[   57.675376][ T1218] initcall acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] returned -17 after 0 usecs
[   57.675523][ T1598] 
[   57.697869][ T1598] Preparing to unpack .../libgcc-10-dev_10.2.1-6_amd64.deb ...
[   57.697872][ T1598] 
[   57.709730][ T1598] Unpacking libgcc-10-dev:amd64 (10.2.1-6) ...
[   57.709732][ T1598] 
[   57.720171][ T1598] Selecting previously unselected package lib32gcc-s1.
[   57.720179][ T1598] 
[   57.731522][ T1598] Preparing to unpack .../lib32gcc-s1_10.2.1-6_amd64.deb ...
[   57.731530][ T1598] 
[   57.742571][ T1164] calling  acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] @ 1164
[   57.743148][ T1598] Unpacking lib32gcc-s1 (10.2.1-6) ...
[   57.750643][ T1164] initcall acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] returned -17 after 0 usecs
[   57.767016][ T1598] 
[   57.770523][ T1598] Selecting previously unselected package gcc-10.
[   57.770528][ T1598] 
[   57.781348][ T1598] Preparing to unpack .../deb/gcc-10_10.2.1-6_amd64.deb ...
[   57.781354][ T1598] 
[   57.792610][ T1598] Unpacking gcc-10 (10.2.1-6) ...
[   57.792616][ T1598] 
[   57.801603][ T1598] Selecting previously unselected package gcc.
[   57.801606][ T1598] 
[   57.812169][ T1598] Preparing to unpack .../deb/gcc_4%3a10.2.1-1_amd64.deb ...
[   57.812174][ T1598] 
[   57.823766][ T1598] Unpacking gcc (4:10.2.1-1) ...
[   57.823769][ T1598] 
[   57.832127][ T1326] calling  acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] @ 1326
[   57.832856][ T1598] Selecting previously unselected package g++-10.
[   57.840202][ T1326] initcall acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] returned -17 after 0 usecs
[   57.840348][ T1598] 
[   57.861337][ T1598] Preparing to unpack .../deb/g++-10_10.2.1-6_amd64.deb ...
[   57.861343][ T1598] 
[   57.882177][ T1598] Unpacking g++-10 (10.2.1-6) ...
[   57.882184][ T1598] 
[   57.891205][ T1598] Selecting previously unselected package g++.
[   57.891210][ T1598] 
[   57.901802][ T1598] Preparing to unpack .../deb/g++_4%3a10.2.1-1_amd64.deb ...
[   57.901805][ T1598] 
[   57.912818][ T1276] calling  acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] @ 1276
[   57.913255][ T1598] Unpacking g++ (4:10.2.1-1) ...
[   57.920889][ T1276] initcall acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] returned -17 after 0 usecs
[   57.921056][ T1598] 
[   57.940374][ T1598] Selecting previously unselected package libatk1.0-data.
[   57.940379][ T1598] 
[   57.952131][ T1598] Preparing to unpack .../libatk1.0-data_2.36.0-2_all.deb ...
[   57.952133][ T1598] 
[   57.963819][ T1598] Unpacking libatk1.0-data (2.36.0-2) ...
[   57.963821][ T1598] 
[   57.973917][ T1598] Selecting previously unselected package libatk1.0-0:amd64.
[   57.973920][ T1598] 
[   57.984960][ T1122] calling  acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] @ 1122
[   57.985933][ T1598] Preparing to unpack .../libatk1.0-0_2.36.0-2_amd64.deb ...
[   57.993038][ T1122] initcall acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] returned -17 after 0 usecs
[   57.993188][ T1598] 
[   58.014955][ T1598] Unpacking libatk1.0-0:amd64 (2.36.0-2) ...
[   58.014957][ T1598] 
[   58.025387][ T1598] Selecting previously unselected package gir1.2-atk-1.0:amd64.
[   58.025394][ T1598] 
[   58.037690][ T1598] Preparing to unpack .../gir1.2-atk-1.0_2.36.0-2_amd64.deb ...
[   58.037697][ T1598] 
[   58.049651][ T1598] Unpacking gir1.2-atk-1.0:amd64 (2.36.0-2) ...
[   58.049657][ T1598] 
[   58.060211][ T1598] Selecting previously unselected package libthai-data.
[   58.060217][ T1598] 
[   58.070690][ T1220] calling  acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] @ 1220
[   58.071675][ T1598] Preparing to unpack .../libthai-data_0.1.28-3_all.deb ...
[   58.078764][ T1220] initcall acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] returned -17 after 0 usecs
[   58.086736][ T1598] 
[   58.100456][ T1598] Unpacking libthai-data (0.1.28-3) ...
[   58.100464][ T1598] 
[   58.110328][ T1598] Selecting previously unselected package libdatrie1:amd64.
[   58.110334][ T1598] 
[   58.122142][ T1598] Preparing to unpack .../libdatrie1_0.2.13-1_amd64.deb ...
[   58.122148][ T1598] 
[   58.133596][ T1598] Unpacking libdatrie1:amd64 (0.2.13-1) ...
[   58.133603][ T1598] 
[   58.143773][ T1598] Selecting previously unselected package libdpkg-perl.
[   58.143775][ T1598] 
[   58.155165][ T1598] Preparing to unpack .../libdpkg-perl_1.20.12_all.deb ...
[   58.155170][ T1598] 
[   58.165982][ T1213] calling  acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] @ 1213
[   58.166508][ T1598] Unpacking libdpkg-perl (1.20.12) ...
[   58.174060][ T1213] initcall acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] returned -17 after 0 usecs
[   58.179999][ T1598] 
[   58.194064][ T1598] Selecting previously unselected package libglib2.0-data.
[   58.194066][ T1598] 
[   58.205801][ T1598] Preparing to unpack .../libglib2.0-data_2.66.8-1_all.deb ...
[   58.205804][ T1598] 
[   58.217522][ T1598] Unpacking libglib2.0-data (2.66.8-1) ...
[   58.217528][ T1598] 
[   58.227611][ T1598] Selecting previously unselected package python3-lib2to3.
[   58.227617][ T1598] 
[   58.239350][ T1598] Preparing to unpack .../python3-lib2to3_3.9.2-1_all.deb ...
[   58.239358][ T1598] 
[   58.250993][ T1598] Unpacking python3-lib2to3 (3.9.2-1) ...
[   58.250996][ T1598] 
[   58.260269][ T1429] calling  acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] @ 1429
[   58.261130][ T1598] Selecting previously unselected package python3-distutils.
[   58.268345][ T1429] initcall acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] returned -17 after 0 usecs
[   58.276410][ T1598] 
[   58.277602][ T1598] Preparing to unpack .../python3-distutils_3.9.2-1_all.deb ...
[   58.289407][ T1598] 
[   58.301276][ T1598] Unpacking python3-distutils (3.9.2-1) ...
[   58.301284][ T1598] 
[   58.311565][ T1598] Selecting previously unselected package libatk1.0-dev:amd64.
[   58.311573][ T1598] 
[   58.323704][ T1598] Preparing to unpack .../libatk1.0-dev_2.36.0-2_amd64.deb ...
[   58.323707][ T1598] 
[   58.335088][ T1389] calling  acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] @ 1389
[   58.335655][ T1598] Unpacking libatk1.0-dev:amd64 (2.36.0-2) ...
[   58.343163][ T1389] initcall acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] returned -17 after 0 usecs
[   58.343314][ T1598] 
[   58.364075][ T1598] Selecting previously unselected package libexpat1-dev:amd64.
[   58.364077][ T1598] 
[   58.376449][ T1598] Preparing to unpack .../libexpat1-dev_2.2.10-2+deb11u3_amd64.deb ...
[   58.376455][ T1598] 
[   58.389243][ T1598] Unpacking libexpat1-dev:amd64 (2.2.10-2+deb11u3) ...
[   58.389247][ T1598] 
[   58.400631][ T1598] Selecting previously unselected package libdatrie-dev:amd64.
[   58.400637][ T1598] 
[   58.412848][ T1598] Preparing to unpack .../libdatrie-dev_0.2.13-1_amd64.deb ...
[   58.412850][ T1598] 
[   58.424126][ T1206] calling  acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] @ 1206
[   58.424796][ T1598] Unpacking libdatrie-dev:amd64 (0.2.13-1) ...
[   58.432201][ T1206] initcall acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] returned -17 after 0 usecs
[   58.432351][ T1598] 
[   58.453081][ T1598] Selecting previously unselected package libperl-dev:amd64.
[   58.453083][ T1598] 
[   58.465213][ T1598] Preparing to unpack .../libperl-dev_5.32.1-4+deb11u2_amd64.deb ...
[   58.465218][ T1598] 
[   58.477800][ T1598] Unpacking libperl-dev:amd64 (5.32.1-4+deb11u2) ...
[   58.477803][ T1598] 
[   58.489008][ T1598] Selecting previously unselected package libpython3.9:amd64.
[   58.489011][ T1598] 
[   58.500120][ T1146] calling  acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] @ 1146
[   58.501145][ T1598] Preparing to unpack .../libpython3.9_3.9.2-1_amd64.deb ...
[   58.508193][ T1146] initcall acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] returned -17 after 0 usecs
[   58.508339][ T1598] 
[   58.530137][ T1598] Unpacking libpython3.9:amd64 (3.9.2-1) ...
[   58.530142][ T1598] 
[   58.540622][ T1598] Selecting previously unselected package libpython3.9-dev:amd64.
[   58.540630][ T1598] 
[   58.553139][ T1598] Preparing to unpack .../libpython3.9-dev_3.9.2-1_amd64.deb ...
[   58.553144][ T1598] 
[   58.564616][ T1139] calling  acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] @ 1139
[   58.565337][ T1598] Unpacking libpython3.9-dev:amd64 (3.9.2-1) ...
[   58.572689][ T1139] initcall acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] returned -17 after 0 usecs
[   58.579600][ T1598] 
[   58.593842][ T1598] Selecting previously unselected package libpython3-dev:amd64.
[   58.593844][ T1598] 
[   58.606135][ T1598] Preparing to unpack .../libpython3-dev_3.9.2-3_amd64.deb ...
[   58.606140][ T1598] 
[   58.617939][ T1598] Unpacking libpython3-dev:amd64 (3.9.2-3) ...
[   58.617942][ T1598] 
[   58.628592][ T1598] Selecting previously unselected package python3-pkg-resources.
[   58.628598][ T1598] 
[   58.640140][ T1215] calling  acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] @ 1215
[   58.641240][ T1598] Preparing to unpack .../python3-pkg-resources_52.0.0-4_all.deb ...
[   58.648215][ T1215] initcall acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] returned -17 after 0 usecs
[   58.648363][ T1598] 
[   58.671020][ T1598] Unpacking python3-pkg-resources (52.0.0-4) ...
[   58.671024][ T1598] 
[   58.681766][ T1598] Selecting previously unselected package python3-pygments.
[   58.681769][ T1598] 
[   58.693806][ T1598] Preparing to unpack .../python3-pygments_2.7.1+dfsg-2.1_all.deb ...
[   58.693810][ T1598] 
[   58.715898][ T1598] Unpacking python3-pygments (2.7.1+dfsg-2.1) ...
[   58.715900][ T1598] 
[   58.725943][ T1370] calling  acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] @ 1370
[   58.726774][ T1598] Selecting previously unselected package python3-yaml.
[   58.734019][ T1370] initcall acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] returned -17 after 0 usecs
[   58.734168][ T1598] 
[   58.755766][ T1598] Preparing to unpack .../python3-yaml_5.3.1-5_amd64.deb ...
[   58.755768][ T1598] 
[   58.767263][ T1598] Unpacking python3-yaml (5.3.1-5) ...
[   58.767267][ T1598] 
[   58.776778][ T1598] Selecting previously unselected package patch.
[   58.776780][ T1598] 
[   58.787424][ T1598] Preparing to unpack .../deb/patch_2.7.6-7_amd64.deb ...
[   58.787430][ T1598] 
[   58.798439][ T1598] Unpacking patch (2.7.6-7) ...
[   58.798443][ T1598] 
[   58.807472][ T1598] Selecting previously unselected package python3.9-dev.
[   58.807478][ T1598] 
[   58.818193][ T1349] calling  acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] @ 1349
[   58.819107][ T1598] Preparing to unpack .../python3.9-dev_3.9.2-1_amd64.deb ...
[   58.826266][ T1349] initcall acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] returned -17 after 0 usecs
[   58.845091][ T1598] 
[   58.848378][ T1598] Unpacking python3.9-dev (3.9.2-1) ...
[   58.848384][ T1598] 
[   58.858130][ T1598] Selecting previously unselected package python3-dev.
[   58.858133][ T1598] 
[   58.869455][ T1598] Preparing to unpack .../python3-dev_3.9.2-3_amd64.deb ...
[   58.869460][ T1598] 
[   58.880807][ T1598] Unpacking python3-dev (3.9.2-3) ...
[   58.880809][ T1598] 
[   58.889594][ T1204] calling  acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] @ 1204
[   58.890631][ T1598] Selecting previously unselected package python3-setuptools.
[   58.897662][ T1204] initcall acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] returned -17 after 0 usecs
[   58.905815][ T1598] 
[   58.907113][ T1598] Preparing to unpack .../python3-setuptools_52.0.0-4_all.deb ...
[   58.918828][ T1598] 
[   58.930949][ T1598] Unpacking python3-setuptools (52.0.0-4) ...
[   58.930952][ T1598] 
[   58.941244][ T1598] Setting up libssl1.1:amd64 (1.1.1n-0+deb11u3) ...
[   58.941249][ T1598] 
[   58.951973][ T1598] Setting up libdeflate0:amd64 (1.7-1) ...
[   58.951977][ T1598] 
[   58.961597][ T1257] calling  acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] @ 1257
[   58.962297][ T1598] Setting up libavahi-common-data:amd64 (0.8-5+deb11u1) ...
[   58.969676][ T1257] initcall acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] returned -17 after 0 usecs
[   58.969826][ T1598] 
[   58.970637][ T1598] Setting up libasound2-data (1.2.4-1.1) ...
[   58.990634][ T1598] 
[   59.000647][ T1598] Setting up libatomic1:amd64 (10.2.1-6) ...
[   59.000653][ T1598] 
[   59.010728][ T1598] Setting up libquadmath0:amd64 (10.2.1-6) ...
[   59.010730][ T1598] 
[   59.020914][ T1598] Setting up libatk1.0-data (2.36.0-2) ...
[   59.020919][ T1598] 
[   59.030661][ T1598] Setting up libthai-data (0.1.28-3) ...
[   59.030668][ T1598] 
[   59.040303][ T1598] Setting up libdatrie1:amd64 (0.2.13-1) ...
[   59.040309][ T1598] 
[   59.050232][ T1598] Setting up libdpkg-perl (1.20.12) ...
[   59.050238][ T1598] 
[   59.059235][ T1461] calling  acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] @ 1461
[   59.059878][ T1598] Setting up libglib2.0-data (2.66.8-1) ...
[   59.067309][ T1461] initcall acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] returned -17 after 0 usecs
[   59.067458][ T1598] 
[   59.087519][ T1598] Setting up python3-lib2to3 (3.9.2-1) ...
[   59.087527][ T1598] 
[   59.097362][ T1598] Setting up python3-distutils (3.9.2-1) ...
[   59.097369][ T1598] 
[   59.107441][ T1598] Setting up libpython3.9:amd64 (3.9.2-1) ...
[   59.107446][ T1598] 
[   59.117725][ T1598] Setting up python3-pkg-resources (52.0.0-4) ...
[   59.117729][ T1598] 
[   59.128371][ T1598] Setting up python3-pygments (2.7.1+dfsg-2.1) ...
[   59.128375][ T1598] 
[   59.138918][ T1598] Setting up patch (2.7.6-7) ...
[   59.138920][ T1598] 
[   59.138971][ T1158] calling  acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] @ 1158
[   59.145169][ T1598] Setting up python3-setuptools (52.0.0-4) ...
[   59.146717][ T1158] initcall acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] returned -17 after 0 usecs
[   59.172128][ T1598] 
[   59.175487][ T1598] Setting up ntpdate (1:4.2.8p15+dfsg-1) ...
[   59.175494][ T1598] 
[   59.185301][ T1598] Setting up gcc-10 (10.2.1-6) ...
[   59.185309][ T1598] 
[   59.194140][ T1598] Setting up gcc (4:10.2.1-1) ...
[   59.194146][ T1598] 
[   59.202907][ T1598] Setting up g++-10 (10.2.1-6) ...
[   59.202909][ T1598] 
[   59.211519][ T1422] calling  acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] @ 1422
[   59.211842][ T1598] Setting up g++ (4:10.2.1-1) ...
[   59.219597][ T1422] initcall acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] returned -17 after 0 usecs
[   59.219757][ T1598] 
[   59.221489][ T1598] update-alternatives: using /usr/bin/g++ to provide /usr/bin/c++ (c++) in auto mode
[   59.238028][ T1598] 
[   59.252019][ T1598] Setting up libatk1.0-0:amd64 (2.36.0-2) ...
[   59.252021][ T1598] 
[   59.262247][ T1598] Setting up gir1.2-atk-1.0:amd64 (2.36.0-2) ...
[   59.262254][ T1598] 
[   59.272763][ T1598] Setting up libatk1.0-dev:amd64 (2.36.0-2) ...
[   59.272765][ T1598] 
[   59.282657][ T1169] calling  acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] @ 1169
[   59.283457][ T1598] Setting up libexpat1-dev:amd64 (2.2.10-2+deb11u3) ...
[   59.290734][ T1169] initcall acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] returned -17 after 0 usecs
[   59.290879][ T1598] 
[   59.312224][ T1598] Setting up libdatrie-dev:amd64 (0.2.13-1) ...
[   59.312230][ T1598] 
[   59.322800][ T1598] Setting up libperl-dev:amd64 (5.32.1-4+deb11u2) ...
[   59.322802][ T1598] 
[   59.333847][ T1598] Setting up libpython3.9-dev:amd64 (3.9.2-1) ...
[   59.333850][ T1598] 
[   59.344430][ T1598] Setting up libpython3-dev:amd64 (3.9.2-3) ...
[   59.344433][ T1598] 
[   59.354203][ T1152] calling  acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] @ 1152
[   59.354765][ T1598] Setting up python3-yaml (5.3.1-5) ...
[   59.362276][ T1152] initcall acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] returned -17 after 0 usecs
[   59.362427][ T1598] 
[   59.382066][ T1598] Setting up python3.9-dev (3.9.2-1) ...
[   59.382068][ T1598] 
[   59.391566][ T1598] Setting up python3-dev (3.9.2-3) ...
[   59.391572][ T1598] 
[   59.400853][ T1598] Setting up sysstat (12.5.2-2) ...
[   59.400855][ T1598] 
[   59.410290][ T1598] Setting up gtk-update-icon-cache (3.24.24-4+deb11u2) ...
[   59.410296][ T1598] 
[   59.421761][ T1598] Setting up ca-certificates-java (20190909) ...
[   59.421765][ T1598] 
[   59.431629][ T1247] calling  acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] @ 1247
[   59.432195][ T1598] Adding debian:emSign_Root_CA_-_G1.pem
[   59.439705][ T1247] initcall acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] returned -17 after 0 usecs
[   59.439854][ T1598] 
[   59.459442][ T1598] Adding debian:emSign_Root_CA_-_C1.pem
[   59.459451][ T1598] 
[   59.468981][ T1598] Adding debian:emSign_ECC_Root_CA_-_G3.pem
[   59.468984][ T1598] 
[   59.478909][ T1598] Adding debian:emSign_ECC_Root_CA_-_C3.pem
[   59.478911][ T1598] 
[   59.489039][ T1598] Adding debian:ePKI_Root_Certification_Authority.pem
[   59.489041][ T1598] 
[   59.499878][ T1598] Adding debian:e-Szigno_Root_CA_2017.pem
[   59.499881][ T1598] 
[   59.509038][ T1166] calling  acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] @ 1166
[   59.509594][ T1598] Adding debian:certSIGN_Root_CA_G2.pem
[   59.517112][ T1166] initcall acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] returned -17 after 0 usecs
[   59.523152][ T1598] 
[   59.536806][ T1598] Adding debian:certSIGN_ROOT_CA.pem
[   59.536808][ T1598] 
[   59.545970][ T1598] Adding debian:XRamp_Global_CA_Root.pem
[   59.545973][ T1598] 
[   59.556120][ T1598] Adding debian:VeriSign_Universal_Root_Certification_Authority.pem
[   59.556123][ T1598] 
[   59.577966][ T1598] Adding debian:USERTrust_RSA_Certification_Authority.pem
[   59.577968][ T1598] 
[   59.589541][ T1598] Adding debian:USERTrust_ECC_Certification_Authority.pem
[   59.589549][ T1598] 
[   59.600472][ T1375] calling  acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] @ 1375
[   59.600837][ T1598] Adding debian:UCA_Global_G2_Root.pem
[   59.608547][ T1375] initcall acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] returned -17 after 0 usecs
[   59.608695][ T1598] 
[   59.628415][ T1598] Adding debian:UCA_Extended_Validation_Root.pem
[   59.628421][ T1598] 
[   59.639380][ T1598] Adding debian:Trustwave_Global_ECC_P384_Certification_Authority.pem
[   59.639386][ T1598] 
[   59.652415][ T1598] Adding debian:Trustwave_Global_ECC_P256_Certification_Authority.pem
[   59.652423][ T1598] 
[   59.665251][ T1598] Adding debian:Trustwave_Global_Certification_Authority.pem
[   59.665258][ T1598] 
[   59.676918][ T1598] Adding debian:Trustis_FPS_Root_CA.pem
[   59.676920][ T1598] 
[   59.676962][ T1362] calling  acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] @ 1362
[   59.683794][ T1598] Adding debian:TrustCor_RootCert_CA-2.pem
[   59.685393][ T1362] initcall acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] returned -17 after 0 usecs
[   59.710428][ T1598] 
[   59.713810][ T1598] Adding debian:TrustCor_RootCert_CA-1.pem
[   59.713812][ T1598] 
[   59.723454][ T1598] Adding debian:TrustCor_ECA-1.pem
[   59.723458][ T1598] 
[   59.732465][ T1598] Adding debian:TeliaSonera_Root_CA_v1.pem
[   59.732473][ T1598] 
[   59.742498][ T1598] Adding debian:TWCA_Root_Certification_Authority.pem
[   59.742505][ T1598] 
[   59.753168][ T1458] calling  acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] @ 1458
[   59.753433][ T1598] Adding debian:TWCA_Global_Root_CA.pem
[   59.761246][ T1458] initcall acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] returned -17 after 0 usecs
[   59.761395][ T1598] 
[   59.781545][ T1598] Adding debian:TUBITAK_Kamu_SM_SSL_Kok_Sertifikasi_-_Surum_1.pem
[   59.781552][ T1598] 
[   59.793732][ T1598] Adding debian:T-TeleSec_GlobalRoot_Class_3.pem
[   59.793735][ T1598] 
[   59.804239][ T1598] Adding debian:T-TeleSec_GlobalRoot_Class_2.pem
[   59.804247][ T1598] 
[   59.814655][ T1598] Adding debian:SwissSign_Silver_CA_-_G2.pem
[   59.814661][ T1598] 
[   59.824641][ T1598] Adding debian:SwissSign_Gold_CA_-_G2.pem
[   59.824647][ T1598] 
[   59.835100][ T1598] Adding debian:Starfield_Services_Root_Certificate_Authority_-_G2.pem
[   59.835103][ T1598] 
[   59.847049][ T1452] calling  acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] @ 1452
[   59.848126][ T1598] Adding debian:Starfield_Root_Certificate_Authority_-_G2.pem
[   59.855122][ T1452] initcall acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] returned -17 after 0 usecs
[   59.863294][ T1598] 
[   59.877053][ T1598] Adding debian:Starfield_Class_2_CA.pem
[   59.877055][ T1598] 
[   59.886904][ T1598] Adding debian:Staat_der_Nederlanden_Root_CA_-_G3.pem
[   59.886906][ T1598] 
[   59.898093][ T1598] Adding debian:Staat_der_Nederlanden_EV_Root_CA.pem
[   59.898095][ T1598] 
[   59.908370][ T1221] calling  acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] @ 1221
[   59.908945][ T1598] Adding debian:Sonera_Class_2_Root_CA.pem
[   59.916454][ T1221] initcall acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] returned -17 after 0 usecs
[   59.916599][ T1598] 
[   59.936713][ T1598] Adding debian:Security_Communication_Root_CA.pem
[   59.936717][ T1598] 
[   59.947451][ T1598] Adding debian:Security_Communication_RootCA2.pem
[   59.947459][ T1598] 
[   59.957910][ T1598] Adding debian:Secure_Global_CA.pem
[   59.957912][ T1598] 
[   59.966946][ T1598] Adding debian:SecureTrust_CA.pem
[   59.966948][ T1598] 
[   59.975445][ T1402] calling  acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] @ 1402
[   59.976006][ T1598] Adding debian:SecureSign_RootCA11.pem
[   59.983523][ T1402] initcall acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] returned -17 after 0 usecs
[   59.983671][ T1598] 
[   60.003164][ T1598] Adding debian:SZAFIR_ROOT_CA2.pem
[   60.003170][ T1598] 
[   60.012658][ T1598] Adding debian:SSL.com_Root_Certification_Authority_RSA.pem
[   60.012665][ T1598] 
[   60.024612][ T1598] Adding debian:SSL.com_Root_Certification_Authority_ECC.pem
[   60.024619][ T1598] 
[   60.036659][ T1598] Adding debian:SSL.com_EV_Root_Certification_Authority_RSA_R2.pem
[   60.036665][ T1598] 
[   60.048712][ T1433] calling  acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] @ 1433
[   60.049397][ T1598] Adding debian:SSL.com_EV_Root_Certification_Authority_ECC.pem
[   60.056778][ T1433] initcall acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] returned -17 after 0 usecs
[   60.056926][ T1598] 
[   60.078886][ T1598] Adding debian:QuoVadis_Root_CA_3_G3.pem
[   60.078888][ T1598] 
[   60.088464][ T1598] Adding debian:QuoVadis_Root_CA_3.pem
[   60.088470][ T1598] 
[   60.097848][ T1598] Adding debian:QuoVadis_Root_CA_2_G3.pem
[   60.097850][ T1598] 
[   60.107457][ T1598] Adding debian:QuoVadis_Root_CA_2.pem
[   60.107462][ T1598] 
[   60.116846][ T1598] Adding debian:QuoVadis_Root_CA_1_G3.pem
[   60.116848][ T1598] 
[   60.126414][ T1598] Adding debian:QuoVadis_Root_CA.pem
[   60.126420][ T1598] 
[   60.135818][ T1598] Adding debian:OISTE_WISeKey_Global_Root_GC_CA.pem
[   60.135820][ T1598] 
[   60.145989][ T1265] calling  acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] @ 1265
[   60.146787][ T1598] Adding debian:OISTE_WISeKey_Global_Root_GB_CA.pem
[   60.154066][ T1265] initcall acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] returned -17 after 0 usecs
[   60.154213][ T1598] 
[   60.175407][ T1598] Adding debian:Network_Solutions_Certificate_Authority.pem
[   60.175413][ T1598] 
[   60.196509][ T1186] calling  acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] @ 1186
[   60.204736][ T1186] initcall acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] returned -17 after 0 usecs
[   60.227598][ T1188] calling  acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] @ 1188
[   60.235826][ T1188] initcall acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] returned -17 after 0 usecs
[   60.258519][ T1288] calling  acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] @ 1288
[   60.266751][ T1288] initcall acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] returned -17 after 0 usecs
[   60.293471][ T1394] calling  acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] @ 1394
[   60.301713][ T1394] initcall acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] returned -17 after 0 usecs
[   60.324440][ T1255] calling  acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] @ 1255
[   60.332658][ T1255] initcall acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] returned -17 after 0 usecs
[   60.357498][ T1372] calling  acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] @ 1372
[   60.365736][ T1372] initcall acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] returned -17 after 0 usecs
[   60.388503][ T1311] calling  acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] @ 1311
[   60.396733][ T1311] initcall acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] returned -17 after 0 usecs
[   60.423436][ T1181] calling  acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] @ 1181
[   60.431666][ T1181] initcall acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] returned -17 after 0 usecs
[   60.460693][ T1184] calling  acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] @ 1184
[   60.468927][ T1184] initcall acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] returned -17 after 0 usecs
[   60.493505][ T1242] calling  acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] @ 1242
[   60.501739][ T1242] initcall acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] returned -17 after 0 usecs
[   60.528588][ T1306] calling  acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] @ 1306
[   60.536816][ T1306] initcall acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] returned -17 after 0 usecs
[   60.559671][ T1150] calling  acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] @ 1150
[   60.567903][ T1150] initcall acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] returned -17 after 0 usecs
[   60.590579][ T1171] calling  acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] @ 1171
[   60.608279][ T1171] initcall acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] returned -17 after 1 usecs
[   60.618462][ T1598] 
[   60.630895][ T1598] Adding debian:NAVER_Global_Root_Certification_Authority.pem
[   60.630898][ T1598] 
[   60.643110][ T1598] Adding debian:Microsoft_RSA_Root_Certificate_Authority_2017.pem
[   60.643114][ T1598] 
[   60.655654][ T1598] Adding debian:Microsoft_ECC_Root_Certificate_Authority_2017.pem
[   60.655660][ T1598] 
[   60.667298][ T1214] calling  acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] @ 1214
[   60.668047][ T1598] Adding debian:Microsec_e-Szigno_Root_CA_2009.pem
[   60.675368][ T1214] initcall acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] returned -17 after 0 usecs
[   60.675526][ T1598] 
[   60.696071][ T1598] Adding debian:Izenpe.com.pem
[   60.696074][ T1598] 
[   60.704979][ T1598] Adding debian:IdenTrust_Public_Sector_Root_CA_1.pem
[   60.704981][ T1598] 
[   60.716038][ T1598] Adding debian:IdenTrust_Commercial_Root_CA_1.pem
[   60.716041][ T1598] 
[   60.726414][ T1598] Adding debian:ISRG_Root_X1.pem
[   60.726419][ T1598] 
[   60.735279][ T1598] Adding debian:Hongkong_Post_Root_CA_3.pem
[   60.735285][ T1598] 
[   60.744642][ T1468] calling  acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] @ 1468
[   60.745321][ T1598] Adding debian:Hongkong_Post_Root_CA_1.pem
[   60.752728][ T1468] initcall acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] returned -17 after 0 usecs
[   60.752875][ T1598] 
[   60.773695][ T1598] Adding debian:Hellenic_Academic_and_Research_Institutions_RootCA_2015.pem
[   60.773721][ T1598] 
[   60.787467][ T1598] Adding debian:Hellenic_Academic_and_Research_Institutions_RootCA_2011.pem
[   60.787474][ T1598] 
[   60.801344][ T1598] Adding debian:Hellenic_Academic_and_Research_Institutions_ECC_RootCA_2015.pem
[   60.801351][ T1598] 
[   60.815155][ T1598] Adding debian:Go_Daddy_Root_Certificate_Authority_-_G2.pem
[   60.815163][ T1598] 
[   60.826198][ T1199] calling  acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] @ 1199
[   60.826808][ T1598] Adding debian:Go_Daddy_Class_2_CA.pem
[   60.834272][ T1199] initcall acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] returned -17 after 0 usecs
[   60.840803][ T1598] 
[   60.854270][ T1598] Adding debian:Global_Chambersign_Root_-_2008.pem
[   60.854277][ T1598] 
[   60.864890][ T1598] Adding debian:GlobalSign_Root_CA_-_R6.pem
[   60.864893][ T1598] 
[   60.874799][ T1598] Adding debian:GlobalSign_Root_CA_-_R3.pem
[   60.874801][ T1598] 
[   60.884692][ T1598] Adding debian:GlobalSign_Root_CA_-_R2.pem
[   60.884709][ T1598] 
[   60.894076][ T1317] calling  acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] @ 1317
[   60.894590][ T1598] Adding debian:GlobalSign_Root_CA.pem
[   60.902153][ T1317] initcall acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] returned -17 after 0 usecs
[   60.918511][ T1598] 
[   60.921964][ T1598] Adding debian:GlobalSign_ECC_Root_CA_-_R5.pem
[   60.921966][ T1598] 
[   60.932354][ T1598] Adding debian:GlobalSign_ECC_Root_CA_-_R4.pem
[   60.932360][ T1598] 
[   60.943134][ T1598] Adding debian:GeoTrust_Primary_Certification_Authority_-_G2.pem
[   60.943138][ T1598] 
[   60.954980][ T1598] Adding debian:GTS_Root_R4.pem
[   60.954983][ T1598] 
[   60.963472][ T1598] Adding debian:GTS_Root_R3.pem
[   60.963479][ T1598] 
[   60.971984][ T1598] Adding debian:GTS_Root_R2.pem
[   60.971987][ T1598] 
[   60.980300][ T1397] calling  acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] @ 1397
[   60.980577][ T1598] Adding debian:GTS_Root_R1.pem
[   60.988376][ T1397] initcall acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] returned -17 after 0 usecs
[   60.988534][ T1598] 
[   61.007439][ T1598] Adding debian:GDCA_TrustAUTH_R5_ROOT.pem
[   61.007445][ T1598] 
[   61.017651][ T1598] Adding debian:Entrust_Root_Certification_Authority_-_G4.pem
[   61.017657][ T1598] 
[   61.029729][ T1598] Adding debian:Entrust_Root_Certification_Authority_-_G2.pem
[   61.029733][ T1598] 
[   61.041849][ T1598] Adding debian:Entrust_Root_Certification_Authority_-_EC1.pem
[   61.041851][ T1598] 
[   61.053920][ T1598] Adding debian:Entrust_Root_Certification_Authority.pem
[   61.053922][ T1598] 
[   61.064597][ T1238] calling  acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] @ 1238
[   61.065589][ T1598] Adding debian:Entrust.net_Premium_2048_Secure_Server_CA.pem
[   61.072672][ T1238] initcall acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] returned -17 after 0 usecs
[   61.072823][ T1598] 
[   61.073342][ T1598] Adding debian:EC-ACC.pem
[   61.093873][ T1598] 
[   61.102339][ T1598] Adding debian:E-Tugra_Certification_Authority.pem
[   61.102346][ T1598] 
[   61.113072][ T1598] Adding debian:DigiCert_Trusted_Root_G4.pem
[   61.113076][ T1598] 
[   61.123327][ T1598] Adding debian:DigiCert_High_Assurance_EV_Root_CA.pem
[   61.123332][ T1598] 
[   61.134326][ T1598] Adding debian:DigiCert_Global_Root_G3.pem
[   61.134331][ T1598] 
[   61.143724][ T1384] calling  acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] @ 1384
[   61.144344][ T1598] Adding debian:DigiCert_Global_Root_G2.pem
[   61.151796][ T1384] initcall acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] returned -17 after 0 usecs
[   61.168639][ T1598] 
[   61.172027][ T1598] Adding debian:DigiCert_Global_Root_CA.pem
[   61.172029][ T1598] 
[   61.182049][ T1598] Adding debian:DigiCert_Assured_ID_Root_G3.pem
[   61.182052][ T1598] 
[   61.192428][ T1598] Adding debian:DigiCert_Assured_ID_Root_G2.pem
[   61.192433][ T1598] 
[   61.202821][ T1598] Adding debian:DigiCert_Assured_ID_Root_CA.pem
[   61.202823][ T1598] 
[   61.212533][ T1197] calling  acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] @ 1197
[   61.213006][ T1598] Adding debian:DST_Root_CA_X3.pem
[   61.220611][ T1197] initcall acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] returned -17 after 0 usecs
[   61.220764][ T1598] 
[   61.221762][ T1598] Adding debian:D-TRUST_Root_Class_3_CA_2_EV_2009.pem
[   61.239123][ T1598] 
[   61.250108][ T1598] Adding debian:D-TRUST_Root_Class_3_CA_2_2009.pem
[   61.250111][ T1598] 
[   61.260633][ T1598] Adding debian:Cybertrust_Global_Root.pem
[   61.260638][ T1598] 
[   61.270468][ T1598] Adding debian:Comodo_AAA_Services_root.pem
[   61.270473][ T1598] 
[   61.280664][ T1598] Adding debian:Chambers_of_Commerce_Root_-_2008.pem
[   61.280669][ T1598] 
[   61.290926][ T1125] calling  acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] @ 1125
[   61.291607][ T1598] Adding debian:Certum_Trusted_Network_CA_2.pem
[   61.299001][ T1125] initcall acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] returned -17 after 0 usecs
[   61.299150][ T1598] 
[   61.319661][ T1598] Adding debian:Certum_Trusted_Network_CA.pem
[   61.319670][ T1598] 
[   61.329634][ T1598] Adding debian:Certigna_Root_CA.pem
[   61.329640][ T1598] 
[   61.338560][ T1598] Adding debian:Certigna.pem
[   61.338566][ T1598] 
[   61.347253][ T1598] Adding debian:COMODO_RSA_Certification_Authority.pem
[   61.347259][ T1598] 
[   61.358476][ T1598] Adding debian:COMODO_ECC_Certification_Authority.pem
[   61.358482][ T1598] 
[   61.369562][ T1598] Adding debian:COMODO_Certification_Authority.pem
[   61.369570][ T1598] 
[   61.379900][ T1598] Adding debian:CFCA_EV_ROOT.pem
[   61.379902][ T1598] 
[   61.388178][ T1244] calling  acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] @ 1244
[   61.388662][ T1598] Adding debian:CA_Disig_Root_R2.pem
[   61.396255][ T1244] initcall acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] returned -17 after 0 usecs
[   61.396405][ T1598] 
[   61.415792][ T1598] Adding debian:Buypass_Class_3_Root_CA.pem
[   61.415795][ T1598] 
[   61.425705][ T1598] Adding debian:Buypass_Class_2_Root_CA.pem
[   61.425718][ T1598] 
[   61.435655][ T1598] Adding debian:Baltimore_CyberTrust_Root.pem
[   61.435660][ T1598] 
[   61.446498][ T1598] Adding debian:Autoridad_de_Certificacion_Firmaprofesional_CIF_A62634068.pem
[   61.446503][ T1598] 
[   61.468962][ T1598] Adding debian:Atos_TrustedRoot_2011.pem
[   61.468964][ T1598] 
[   61.478507][ T1598] Adding debian:Amazon_Root_CA_4.pem
[   61.478513][ T1598] 
[   61.487560][ T1598] Adding debian:Amazon_Root_CA_3.pem
[   61.487567][ T1598] 
[   61.496623][ T1598] Adding debian:Amazon_Root_CA_2.pem
[   61.496630][ T1598] 
[   61.505690][ T1598] Adding debian:Amazon_Root_CA_1.pem
[   61.505697][ T1598] 
[   61.514945][ T1598] Adding debian:AffirmTrust_Premium_ECC.pem
[   61.514947][ T1598] 
[   61.524795][ T1598] Adding debian:AffirmTrust_Premium.pem
[   61.524797][ T1598] 
[   61.533734][ T1202] calling  acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] @ 1202
[   61.534398][ T1598] Adding debian:AffirmTrust_Networking.pem
[   61.541808][ T1202] initcall acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] returned -17 after 0 usecs
[   61.558548][ T1598] 
[   61.561872][ T1598] Adding debian:AffirmTrust_Commercial.pem
[   61.561874][ T1598] 
[   61.571798][ T1598] Adding debian:Actalis_Authentication_Root_CA.pem
[   61.571800][ T1598] 
[   61.582220][ T1598] Adding debian:AC_RAIZ_FNMT-RCM.pem
[   61.582226][ T1598] 
[   61.591157][ T1598] Adding debian:ACCVRAIZ1.pem
[   61.591162][ T1598] 
[   61.599055][ T1598] done.
[   61.599058][ T1598] 
[   61.599170][ T1234] calling  acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] @ 1234
[   61.602910][ T1598] Setting up libgcc-10-dev:amd64 (10.2.1-6) ...
[   61.604430][ T1234] initcall acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] returned -17 after 0 usecs
[   61.612498][ T1598] 
[   61.613246][ T1598] Setting up lib32gcc-s1 (10.2.1-6) ...
[   61.632479][ T1598] 
[   61.642286][ T1598] Processing triggers for libc-bin (2.31-13+deb11u3) ...
[   61.642292][ T1598] 
[   61.653737][ T1598] Processing triggers for ca-certificates (20210119) ...
[   61.653739][ T1598] 
[   61.664939][ T1598] Updating certificates in /etc/ssl/certs...
[   61.664941][ T1598] 
[   61.674350][ T1183] calling  acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] @ 1183
[   61.674720][ T1598] 0 added, 0 removed; done.
[   61.682418][ T1183] initcall acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] returned -17 after 0 usecs
[   61.682567][ T1598] 
[   61.701248][ T1598] Running hooks in /etc/ca-certificates/update.d...
[   61.701254][ T1598] 
[   61.711131][ T1598] 
[   61.711133][ T1598] 
[   61.716332][ T1598] done.
[   61.716334][ T1598] 
[   61.722023][ T1598] done.
[   61.722025][ T1598] 
[   61.737533][ T1425] calling  acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] @ 1425
[   61.745768][ T1425] initcall acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] returned -17 after 0 usecs
[   61.768434][ T1207] calling  acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] @ 1207
[   61.776662][ T1207] initcall acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] returned -17 after 0 usecs
[   61.803509][ T1250] calling  acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] @ 1250
[   61.811739][ T1250] initcall acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] returned -17 after 0 usecs
[   61.838565][ T1261] calling  acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] @ 1261
[   61.846794][ T1261] initcall acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] returned -17 after 0 usecs
[   61.869486][ T1175] calling  acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] @ 1175
[   61.877719][ T1175] initcall acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] returned -17 after 0 usecs
[   61.900472][ T1456] calling  acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] @ 1456
[   61.908697][ T1456] initcall acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] returned -17 after 0 usecs
[   61.931457][ T1404] calling  acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] @ 1404
[   61.939680][ T1404] initcall acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] returned -17 after 0 usecs
[   61.962566][ T1390] calling  acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] @ 1390
[   61.970788][ T1390] initcall acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] returned -17 after 0 usecs
[   61.993455][ T1251] calling  acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] @ 1251
[   62.001679][ T1251] initcall acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] returned -17 after 0 usecs
[   62.026427][ T1393] calling  acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] @ 1393
[   62.034652][ T1393] initcall acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] returned -17 after 0 usecs
[   62.059447][ T1249] calling  acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] @ 1249
[   62.067675][ T1249] initcall acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] returned -17 after 0 usecs
[   62.090611][ T1386] calling  acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] @ 1386
[   62.098845][ T1386] initcall acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] returned -17 after 0 usecs
[   62.125469][ T1260] calling  acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] @ 1260
[   62.133697][ T1260] initcall acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] returned -17 after 0 usecs
[   62.160422][ T1263] calling  acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] @ 1263
[   62.168648][ T1263] initcall acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] returned -17 after 0 usecs
[   62.193379][ T1441] calling  acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] @ 1441
[   62.201598][ T1441] initcall acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] returned -17 after 0 usecs
[   62.226563][ T1413] calling  acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] @ 1413
[   62.234794][ T1413] initcall acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] returned -17 after 0 usecs
[   62.257467][ T1329] calling  acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] @ 1329
[   62.265695][ T1329] initcall acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] returned -17 after 0 usecs
[   62.292444][ T1137] calling  acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] @ 1137
[   62.300676][ T1137] initcall acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] returned -17 after 0 usecs
[   62.327398][ T1159] calling  acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] @ 1159
[   62.335628][ T1159] initcall acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] returned -17 after 0 usecs
[   62.360360][ T1236] calling  acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] @ 1236
[   62.368585][ T1236] initcall acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] returned -17 after 0 usecs
[   62.401417][ T1381] calling  acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] @ 1381
[   62.409642][ T1381] initcall acpi_cpufreq_init+0x0/0xea5 [acpi_cpufreq] returned -17 after 0 usecs
[   62.477884][ T1598] 10 Dec 14:30:08 ntpdate[3701]: step time server 192.168.1.200 offset -56.014211 sec
LKP: ttyS0: 1557[   62.477888][ T1598] 
:  /lkp/lkp/src/bin/run-lkp /lkp/jobs/scheduled/lkp-hsw-4ex1/vm-scalability-performance-4-64-1-swap-w-seq-never-never-debian-11.1-x86_64-20220510.cgz-6919cda8e0f127fe773cad2553f0648de1c4844-20221210-31307-1s05up6-0.yaml
[   65.486670][ T3800] Adding 125829116k swap on /dev/pmem0.  Priority:1 extents:1 across:125829116k SSFS
[   65.535510][ T3804] Adding 125829116k swap on /dev/pmem1.  Priority:1 extents:1 across:125829116k SSFS
[   65.578796][ T3808] Adding 125829116k swap on /dev/pmem2.  Priority:1 extents:1 across:125829116k SSFS
[   65.622620][ T3812] Adding 125829116k swap on /dev/pmem3.  Priority:1 extents:1 across:125829116k SSFS
[   65.996319][   C60] Scheduler tracepoints stat_sleep, stat_iowait, stat_blocked and stat_runtime require the kernel parameter schedstats=enable or kernel.sched_schedstats=1
[   66.849054][ T6306] calling  loop_init+0x0/0x1000 [loop] @ 6306
[   66.855872][ T6306] loop: module loaded
[   66.860283][ T6306] initcall loop_init+0x0/0x1000 [loop] returned 0 after 4478 usecs
[   66.887554][ T6397] loop0: detected capacity change from 0 to 65523544
[   67.086599][ T1598] LKP: stdout: 1557:  /lkp/lkp/src/bin/run-lkp /lkp/jobs/scheduled/lkp-hsw-4ex1/vm-scalability-performance-4-64-1-swap-w-seq-never-never-debian-11.1-x86_64-20220510.cgz-6919cda8e0f127fe773cad2553f0648de1c4844-20221210-31307-1s05up6-0.yaml
[   67.086624][ T1598] 
[   67.119891][ T1598] RESULT_ROOT=/result/vm-scalability/performance-4-64-1-swap-w-seq-never-never/lkp-hsw-4ex1/debian-11.1-x86_64-20220510.cgz/x86_64-rhel-8.3/gcc-11/6919cda8e0f127fe773cad2553f0648de1c48445/0
[   67.119896][ T1598] 
[   67.148215][ T1598] job=/lkp/jobs/scheduled/lkp-hsw-4ex1/vm-scalability-performance-4-64-1-swap-w-seq-never-never-debian-11.1-x86_64-20220510.cgz-6919cda8e0f127fe773cad2553f0648de1c4844-20221210-31307-1s05up6-0.yaml
[   67.148224][ T1598] 
[   67.290991][ T6452] calling  init_xfs_fs+0x0/0x1de [xfs] @ 6452
[   67.297795][ T6452] SGI XFS with ACLs, security attributes, realtime, scrub, quota, fatal assert, debug enabled
[   67.310374][ T6452] initcall init_xfs_fs+0x0/0x1de [xfs] returned 0 after 12578 usecs
[   67.330664][ T6397] XFS (loop0): Mounting V5 Filesystem
[   67.338833][ T6397] XFS (loop0): Ending clean mount
[   67.344609][ T6397] xfs filesystem being mounted at /tmp/vm-scalability-tmp/vm-scalability supports timestamps until 2038 (0x7fffffff)
[   67.400229][ T1600] /lkp/lkp/src/bin/run-lkp: 66: echo_to_tty: not found
[   67.400236][ T1600] 
[   67.410835][ T1600] Events disabled
[   67.410839][ T1600] 
[   67.688429][ T6678] Scheduler tracepoints stat_sleep, stat_iowait, stat_blocked and stat_runtime require the kernel parameter schedstats=enable or kernel.sched_schedstats=1
[   67.808556][  T924] general protection fault, probably for non-canonical address 0xb000000000000048: 0000 [#1] SMP PTI
[   67.820666][  T924] CPU: 72 PID: 924 Comm: kswapd0 Not tainted 6.1.0-rc5-00020-g6919cda8e0f1 #1
[   67.830527][  T924] Hardware name: Intel Corporation BRICKLAND/BRICKLAND, BIOS BRHSXSD1.86B.0067.R02.1507221722 07/22/2015
[   67.843012][  T924] RIP: 0010:filemap_release_folio+0x2e/0x80
[   67.849545][  T924] Code: 00 48 8b 07 48 8b 57 18 83 e0 01 74 59 48 f7 07 00 60 00 00 74 22 48 8b 07 f6 c4 80 75 32 48 85 d2 74 34 48 8b 82 90 00 00 00 <48> 8b 40 48 48 85 c0 74 24 e9 c4 c1 d2 00 48 85 d2 74 1f 48 8b 8a
[   67.871488][  T924] RSP: 0018:ffffc900061efb28 EFLAGS: 00010246
[   67.878209][  T924] RAX: b000000000000000 RBX: ffffc900061efc08 RCX: 00ffff889f0005be
[   67.887094][  T924] RDX: ffff889f03987f71 RSI: 0000000000000cc0 RDI: ffffea007c573840
[   67.891233][ T1600] ------------------------------------------------------------
[   67.895832][  T924] RBP: ffffc900061efb98 R08: ffff88be945000c0 R09: 0000000000000001
[   67.895833][  T924] R10: ffff88a07ffd5000 R11: 0000000000030900 R12: ffffc900061efc1c
[   67.895835][  T924] R13: ffffea007c573840 R14: ffffea007c573848 R15: ffffc900061efe10
[   67.895837][  T924] FS:  0000000000000000(0000) GS:ffff88a077880000(0000) knlGS:0000000000000000
[   67.895838][  T924] CS:  0010 DS: 0000 ES: 0000 CR0: 0000000080050033
[   67.895840][  T924] CR2: 000055d74170e000 CR3: 000000807ee0a002 CR4: 00000000001706e0
[   67.895841][  T924] DR0: 0000000000000000 DR1: 0000000000000000 DR2: 0000000000000000
[   67.895842][  T924] DR3: 0000000000000000 DR6: 00000000fffe0ff0 DR7: 0000000000000400
[   67.895844][  T924] Call Trace:
[   67.904106][ T1600] 
[   67.912835][  T924]  <TASK>
[   67.912837][  T924]  shrink_folio_list+0x59a/0xb80
[   67.912848][  T924]  shrink_inactive_list+0x157/0x440
[   67.921991][ T1600] perf_event_attr:
[   67.930324][  T924]  shrink_lruvec+0x2b5/0x3c0
[   67.930328][  T924]  shrink_node_memcgs+0x175/0x200
[   67.930330][  T924]  shrink_node+0xb6/0x300
[   67.930331][  T924]  balance_pgdat+0x31c/0x700
[   67.930334][  T924]  kswapd+0x101/0x1c0
[   67.940145][ T1600] 
[   67.947323][  T924]  ? balance_pgdat+0x700/0x700
[   67.947325][  T924]  kthread+0xd9/0x100
[   67.947331][  T924]  ? kthread_complete_and_exit+0x40/0x40
[   67.956964][ T1600]   size                             128
[   67.964807][  T924]  ret_from_fork+0x22/0x30
[   67.964815][  T924]  </TASK>
[   67.964816][  T924] Modules linked in: xfs
[   67.973563][ T1600] 
[   67.977057][  T924]  loop btrfs blake2b_generic xor raid6_pq zstd_compress libcrc32c sd_mod t10_pi crc64_rocksoft_generic sr_mod crc64_rocksoft crc64 cdrom
[   67.980468][ T1600]   { sample_period, sample_freq }   1000003
[   67.982616][  T924]  nd_pmem intel_rapl_msr sg nd_btt dax_pmem intel_rapl_common sb_edac x86_pkg_temp_thermal intel_powerclamp coretemp kvm_intel ipmi_ssif kvm irqbypass crct10dif_pclmul
[   67.987979][ T1600] 
[   67.993603][  T924]  crc32_pclmul crc32c_intel ghash_clmulni_intel sha512_ssse3 acpi_ipmi rapl mpt3sas ahci ipmi_si nd_e820 libahci intel_cstate raid_class ipmi_devintf intel_uncore libnvdimm libata joydev scsi_transport_sas wmi ipmi_msghandler acpi_pad drm fuse ip_tables
[   68.135290][ T6720] general protection fault, probably for non-canonical address 0x8d000000000001f6: 0000 [#2] SMP PTI
[   68.135323][  T924] ---[ end trace 0000000000000000 ]---
[   68.147238][ T6720] CPU: 63 PID: 6720 Comm: usemem Tainted: G      D            6.1.0-rc5-00020-g6919cda8e0f1 #1
[   68.147242][ T6720] Hardware name: Intel Corporation BRICKLAND/BRICKLAND, BIOS BRHSXSD1.86B.0067.R02.1507221722 07/22/2015
[   68.147244][ T6720] RIP: 0010:filemap_release_folio+0x2e/0x80
[   68.153186][  T924] RIP: 0010:filemap_release_folio+0x2e/0x80
[   68.164532][ T6720] Code: 00 48 8b 07 48 8b 57 18 83 e0 01 74 59 48 f7 07 00 60 00 00 74 22 48 8b 07 f6 c4 80 75 32 48 85 d2 74 34 48 8b 82 90 00 00 00 <48> 8b 40 48 48 85 c0 74 24 e9 c4 c1 d2 00 48 85 d2 74 1f 48 8b 8a
[   68.164536][ T6720] RSP: 0000:ffffc900094a7838 EFLAGS: 00010246
[   68.164540][ T6720] RAX: 8d000000000001ae RBX: ffffc900094a7918 RCX: 0100000000000dfc
[   68.164541][ T6720] RDX: ffff88be89515f71 RSI: 0000000000140dca RDI: ffffea017d7fabc0
[   68.164543][ T6720] RBP: ffffc900094a78a8 R08: ffff88bf24880840 R09: 0000000000000001
[   68.164544][ T6720] R10: ffff88e07ffd5000 R11: 0000000000030958 R12: ffffc900094a792c
[   68.164545][ T6720] R13: ffffea017d7fabc0 R14: ffffea017d7fabc8 R15: ffffc900094a7b80
[   68.164546][ T6720] FS:  00007fcc55dca740(0000) GS:ffff890028840000(0000) knlGS:0000000000000000
[   68.164548][ T6720] CS:  0010 DS: 0000 ES: 0000 CR0: 0000000080050033
[   68.176881][  T924] Code: 00 48 8b 07 48 8b 57 18 83 e0 01 74 59 48 f7 07 00 60 00 00 74 22 48 8b 07 f6 c4 80 75 32 48 85 d2 74 34 48 8b 82 90 00 00 00 <48> 8b 40 48 48 85 c0 74 24 e9 c4 c1 d2 00 48 85 d2 74 1f 48 8b 8a
[   68.183280][ T6720] CR2: 00007fcaf5a54000 CR3: 0000003e8a2f2003 CR4: 00000000001706e0
[   68.183282][ T6720] DR0: 0000000000000000 DR1: 0000000000000000 DR2: 0000000000000000
[   68.183284][ T6720] DR3: 0000000000000000 DR6: 00000000fffe0ff0 DR7: 0000000000000400
[   68.183285][ T6720] Call Trace:
[   68.183288][ T6720]  <TASK>
[   68.189709][  T924] RSP: 0018:ffffc900061efb28 EFLAGS: 00010246
[   68.199790][ T1600]   sample_type                      IP|TID|TIME|CALLCHAIN|ID|CPU
[   68.199794][ T1600] 
[   68.200766][ T1600]   read_format                      ID|LOST
[   68.200768][ T1600] 
[   68.201607][ T1600]   disabled                         1
[   68.201609][ T1600] 
[   68.202431][ T1600]   inherit                          1
[   68.202433][ T1600] 
[   68.203269][ T1600]   precise_ip                       2
[   68.203271][ T1600] 
[   68.204090][ T1600]   sample_id_all                    1
[   68.204092][ T1600] 
[   68.204931][ T1600]   exclude_guest                    1
[   68.204933][ T1600] 
[   68.206360][ T1600] ------------------------------------------------------------
[   68.206363][ T1600] 
[   68.207834][ T1600] ------------------------------------------------------------
[   68.207836][ T1600] 
[   68.208197][ T1600] perf_event_attr:
[   68.208198][ T1600] 
[   68.209031][ T1600]   type                             1
[   68.209034][ T1600] 
[   68.209908][ T1600]   size                             128
[   68.209910][ T1600] 
[   68.210793][ T1600]   config                           0x9
[   68.210795][ T1600] 
[   68.211432][ T6720]  shrink_folio_list+0x59a/0xb80
[   68.211739][ T1600]   { sample_period, sample_freq }   1000003
[   68.211741][ T1600] 
[   68.213186][ T1600]   sample_type                      IP|TID|TIME|CALLCHAIN|ID|CPU
[   68.213188][ T1600] 
[   68.214156][ T1600]   read_format                      ID|LOST
[   68.214158][ T1600] 
[   68.214996][ T1600]   inherit                          1
[   68.214998][ T1600] 
[   68.215839][ T1600]   mmap                             1
[   68.215841][ T1600] 
[   68.216659][ T1600]   comm                             1
[   68.216661][ T1600] 
[   68.217454][ T1600]   task                             1
[   68.217456][ T1600] 
[   68.218052][  T924] 
[   68.218275][ T1600]   sample_id_all                    1
[   68.218277][ T1600] 
[   68.219108][ T1600]   mmap2                            1
[   68.219111][ T1600] 
[   68.219940][ T1600]   comm_exec                        1
[   68.219942][ T1600] 
[   68.220781][ T1600]   ksymbol                          1
[   68.220783][ T1600] 
[   68.221602][ T1600]   bpf_event                        1
[   68.221604][ T1600] 
[   68.223037][ T1600] ------------------------------------------------------------
[   68.223039][ T1600] 
[   68.224419][ T1600] ------------------------------------------------------------
[   68.224421][ T1600] 
[   68.224807][ T1600] perf_event_attr:
[   68.224809][ T1600] 
[   68.225639][ T1600]   type                             1
[   68.225641][ T1600] 
[   68.226508][ T1600]   size                             128
[   68.226510][ T1600] 
[   68.226787][ T6720]  shrink_inactive_list+0x157/0x440
[   68.226792][ T6720]  shrink_lruvec+0x2b5/0x3c0
[   68.226794][ T6720]  shrink_node_memcgs+0x175/0x200
[   68.226797][ T6720]  shrink_node+0xb6/0x300
[   68.226800][ T6720]  shrink_zones+0x88/0x280
[   68.227420][ T1600]   config                           0x9
[   68.227423][ T1600] 
[   68.228275][ T1600]   watermark                        1
[   68.228277][ T1600] 
[   68.229098][ T1600]   sample_id_all                    1
[   68.229100][ T1600] 
[   68.229919][ T1600]   bpf_event                        1
[   68.229921][ T1600] 
[   68.230830][ T1600]   { wakeup_events, wakeup_watermark } 1
[   68.230832][ T1600] 
[   68.232218][ T1600] ------------------------------------------------------------
[   68.232220][ T1600] 
[   68.235547][  T924] RAX: b000000000000000 RBX: ffffc900061efc08 RCX: 00ffff889f0005be
[   68.244276][ T6720]  do_try_to_free_pages+0x84/0x300
[   68.244280][ T6720]  try_to_free_pages+0xdf/0x200
[   68.244282][ T6720]  __alloc_pages_slowpath+0x349/0xac0
[   68.244288][ T6720]  ? get_page_from_freelist+0xc7/0x580
[   68.253031][  T924] RDX: ffff889f03987f71 RSI: 0000000000000cc0 RDI: ffffea007c573840
[   68.261766][ T6720]  __alloc_pages+0x312/0x340
[   68.261769][ T6720]  __folio_alloc+0x17/0x80
[   68.261771][ T6720]  ? policy_node+0x4f/0x80
[   68.271585][  T924] RBP: ffffc900061efb98 R08: ffff88be945000c0 R09: 0000000000000001
[   68.278765][ T6720]  vma_alloc_folio+0x8f/0x340
[   68.278769][ T6720]  do_anonymous_page+0xc7/0x400
[   68.278774][ T6720]  __handle_mm_fault+0x430/0x600
[   68.300516][  T924] R10: ffff88a07ffd5000 R11: 0000000000030900 R12: ffffc900061efc1c
[   68.309247][ T6720]  handle_mm_fault+0xd3/0x2c0
[   68.309252][ T6720]  do_user_addr_fault+0x1c5/0x6c0
[   68.309258][ T6720]  ? sched_clock_cpu+0x9/0xc0
[   68.318003][  T924] R13: ffffea007c573840 R14: ffffea007c573848 R15: ffffc900061efe10
[   68.326734][ T6720]  exc_page_fault+0x62/0x140
[   68.326741][ T6720]  asm_exc_page_fault+0x22/0x30
[   68.330251][  T924] FS:  0000000000000000(0000) GS:ffff88a077880000(0000) knlGS:0000000000000000
[   68.333361][ T6720] RIP: 0033:0x558ba4124ad6
[   68.333369][ T6720] Code: 01 00 00 00 e8 1b f9 ff ff 89 c7 e8 6c ff ff ff bf 00 00 00 00 e8 0a f9 ff ff 85 d2 74 08 48 8d 04 f7 48 8b 00 c3 48 8d 04 f7 <48> 89 30 b8 00 00 00 00 c3 41 54 55 53 48 85 ff 0f 84 21 01 00 00
[   68.339983][  T924] CS:  0010 DS: 0000 ES: 0000 CR0: 0000000080050033
[   68.348516][ T6720] RSP: 002b:00007ffc26b72d68 EFLAGS: 00010246
[   68.348523][ T6720] RAX: 00007fcaf5a54000 RBX: 00000000029cf800 RCX: 0000000000000018
[   68.348524][ T6720] RDX: 0000000000000000 RSI: 00000000029cf800 RDI: 00007fcae0bd8000
[   68.348525][ T6720] RBP: 00000000029cf800 R08: 00007ffc26bd4080 R09: 00007ffc26b72d50
[   68.348527][ T6720] R10: 00000000639497f5 R11: 0000000000000246 R12: 0000000014e7c000
[   68.348528][ T6720] R13: 00007fcae0bd8000 R14: 00007ffc26b72dfc R15: 00007ffc26b72f00
[   68.350970][  T924] CR2: 000055d74170e000 CR3: 000000807ee0a002 CR4: 00000000001706e0
[   68.357474][ T6720]  </TASK>
[   68.357478][ T6720] Modules linked in: xfs loop btrfs blake2b_generic xor raid6_pq
[   68.359928][  T924] DR0: 0000000000000000 DR1: 0000000000000000 DR2: 0000000000000000
[   68.365850][ T6720]  zstd_compress libcrc32c sd_mod t10_pi crc64_rocksoft_generic sr_mod crc64_rocksoft
[   68.368298][  T924] DR3: 0000000000000000 DR6: 00000000fffe0ff0 DR7: 0000000000000400
[   68.374214][ T6720]  crc64 cdrom nd_pmem intel_rapl_msr
[   68.376662][  T924] Kernel panic - not syncing: Fatal exception
[   68.382583][ T6720]  sg nd_btt dax_pmem intel_rapl_common sb_edac x86_pkg_temp_thermal intel_powerclamp coretemp kvm_intel ipmi_ssif kvm irqbypass crct10dif_pclmul crc32_pclmul crc32c_intel ghash_clmulni_intel sha512_ssse3 acpi_ipmi rapl mpt3sas ahci ipmi_si nd_e820 libahci intel_cstate raid_class ipmi_devintf intel_uncore libnvdimm libata joydev scsi_transport_sas wmi ipmi_msghandler acpi_pad drm fuse ip_tables
[   68.556232][ T6728] general protection fault, probably for non-canonical address 0x8d000000000001f6: 0000 [#3] SMP PTI
[   68.558674][ T6728] CPU: 54 PID: 6728 Comm: usemem Tainted: G      D            6.1.0-rc5-00020-g6919cda8e0f1 #1
[   68.564606][ T6728] Hardware name: Intel Corporation BRICKLAND/BRICKLAND, BIOS BRHSXSD1.86B.0067.R02.1507221722 07/22/2015
[   68.567048][ T6728] RIP: 0010:filemap_release_folio+0x2e/0x80
[   68.575304][ T6728] Code: 00 48 8b 07 48 8b 57 18 83 e0 01 74 59 48 f7 07 00 60 00 00 74 22 48 8b 07 f6 c4 80 75 32 48 85 d2 74 34 48 8b 82 90 00 00 00 <48> 8b 40 48 48 85 c0 74 24 e9 c4 c1 d2 00 48 85 d2 74 1f 48 8b 8a
[   68.577733][ T6728] RSP: 0000:ffffc9000955f838 EFLAGS: 00010246
[   68.588426][ T6728] RAX: 8d000000000001ae RBX: ffffc9000955f918 RCX: 0100000000000dfc
[   68.592416][ T6728] RDX: ffff88be89515f71 RSI: 0000000000140dca RDI: ffffea00fa68a300
[   68.594847][ T6728] RBP: ffffc9000955f8a8 R08: ffff88bf24884c80 R09: 0000000000000001
[   68.600776][ T6728] R10: ffff88c07ffd5000 R11: 000000000003092c R12: ffffc9000955f92c
[   68.603218][ T6728] R13: ffffea00fa68a300 R14: ffffea00fa68a308 R15: ffffc9000955fb80
[   68.609344][ T6728] FS:  00007fcc55dca740(0000) GS:ffff890028600000(0000) knlGS:0000000000000000
[   68.611781][ T6728] CS:  0010 DS: 0000 ES: 0000 CR0: 0000000080050033
[   68.617412][ T6728] CR2: 00007fcaed9d4000 CR3: 0000003f278e0002 CR4: 00000000001706e0
[   68.622370][ T6728] DR0: 0000000000000000 DR1: 0000000000000000 DR2: 0000000000000000
[   68.627812][ T6728] DR3: 0000000000000000 DR6: 00000000fffe0ff0 DR7: 0000000000000400
[   68.632478][ T6728] Call Trace:
[   68.638408][ T6728]  <TASK>
[   68.644530][ T6728]  shrink_folio_list+0x59a/0xb80
[   68.646974][ T6728]  shrink_inactive_list+0x157/0x440
[   68.652904][ T6728]  shrink_lruvec+0x2b5/0x3c0
[   68.655343][ T6728]  shrink_node_memcgs+0x175/0x200
[   68.661273][ T6728]  shrink_node+0xb6/0x300
[   68.663711][ T6728]  shrink_zones+0x88/0x280
[   68.669637][ T6728]  do_try_to_free_pages+0x84/0x300
[   68.672074][ T6728]  try_to_free_pages+0xdf/0x200
[   68.678286][ T6728]  __alloc_pages_slowpath+0x349/0xac0
[   68.680725][ T6728]  ? get_page_from_freelist+0xc7/0x580
[   68.688981][ T6728]  __alloc_pages+0x312/0x340
[   68.691421][ T6728]  __folio_alloc+0x17/0x80
[   68.700160][ T6728]  ? policy_node+0x4f/0x80
[   68.705700][ T6728]  vma_alloc_folio+0x8f/0x340
[   68.710949][ T6728]  do_anonymous_page+0xc7/0x400
[   68.717947][ T6728]  __handle_mm_fault+0x430/0x600
[   68.723876][ T6728]  handle_mm_fault+0xd3/0x2c0
[   68.732619][ T6728]  do_user_addr_fault+0x1c5/0x6c0
[   68.737579][ T6728]  ? sched_clock_cpu+0x9/0xc0
[   68.742347][ T6728]  exc_page_fault+0x62/0x140
[   68.747114][ T6728]  asm_exc_page_fault+0x22/0x30
[   68.755849][ T6728] RIP: 0033:0x558ba4124ad6
[   68.760910][ T6728] Code: 01 00 00 00 e8 1b f9 ff ff 89 c7 e8 6c ff ff ff bf 00 00 00 00 e8 0a f9 ff ff 85 d2 74 08 48 8d 04 f7 48 8b 00 c3 48 8d 04 f7 <48> 89 30 b8 00 00 00 00 c3 41 54 55 53 48 85 ff 0f 84 21 01 00 00
[   68.766160][ T6728] RSP: 002b:00007ffc26b72d68 EFLAGS: 00010246
[   68.780246][ T6728] RAX: 00007fcaed9d4000 RBX: 00000000019bf800 RCX: 0000000000000018
[   68.785301][ T6728] RDX: 0000000000000000 RSI: 00000000019bf800 RDI: 00007fcae0bd8000
[   68.790746][ T6728] RBP: 00000000019bf800 R08: 00007ffc26bd4080 R09: 00007ffc26b72d50
[   68.795796][ T6728] R10: 00000000639497f5 R11: 0000000000000246 R12: 000000000cdfc000
[   68.804538][ T6728] R13: 00007fcae0bd8000 R14: 00007ffc26b72dfc R15: 00007ffc26b72f00
[   68.809497][ T6728]  </TASK>
[   68.814746][ T6728] Modules linked in: xfs loop btrfs blake2b_generic xor raid6_pq zstd_compress libcrc32c sd_mod t10_pi crc64_rocksoft_generic sr_mod crc64_rocksoft crc64 cdrom nd_pmem intel_rapl_msr sg nd_btt dax_pmem intel_rapl_common sb_edac x86_pkg_temp_thermal intel_powerclamp coretemp kvm_intel ipmi_ssif kvm irqbypass crct10dif_pclmul crc32_pclmul crc32c_intel ghash_clmulni_intel sha512_ssse3 acpi_ipmi rapl mpt3sas ahci ipmi_si nd_e820 libahci intel_cstate raid_class ipmi_devintf intel_uncore libnvdimm libata joydev scsi_transport_sas wmi ipmi_msghandler acpi_pad drm fuse ip_tables
[   69.334146][  T924] Kernel Offset: disabled
Loading PEIM at 0x000FFFD5CC0 EntryPoint=0x000FFFD6C90 
Register PPI Notify: F894643D-C449-42D1-8EA8-85BDD8C65BDE
Loading PEIM at 0x000FFFD91A0 EntryPoint=0x000FFFD9AE0 
Install PPI: E6AF1F7B-FC3F-46DA-A828-A3B457A44282
Loading PEIM at 0x000FFFE51E0 EntryPoint=0x000FFFE5B20 
Register PPI Notify: F894643D-C449-42D1-8EA8-85BDD8C65BDE
Loading PEIM at 0x000FFFEB7A0 EntryPoint=0x000FFFEC258 
InstallPchSpi() Start
Install PPI: A38C6898-2B5C-4FF6-9326-2E63212E56C2
SPI PPI Installed
InstallPchSpi() End
Loading PEIM at 0x000FFFEDEE0 EntryPoint=0x000FFFEE658 
Loading PEIM at 0x000FFD55520 EntryPoint=0x000FFD55750 
Loading PEIM at 0x000FFD558A0 EntryPoint=0x000FFD56228 
Install PPI: 7F19E716-419C-4E79-8E37-C2BD84EB6528
Flash Map PEIM Loaded
Loading PEIM at 0x000FFD56E20 EntryPoint=0x000FFD57928 
Force an S5 exit path.
Install PPI: EE0EA811-FBD9-4777-B95A-BA4F71101F74
Install PPI: E5EE2066-FAA1-4DFA-924E-B1E3A8EE30E8
[HECI] MBAR not programmed in PEI phase, using default 0xFEDB0000
Loading PEIM at 0x000FFD5C680 EntryPoint=0x000FFD5D5D0 
[SPS] Waiting for ME firmware initialization
Register PPI Notify: 605EA650-C65C-42E1-BA80-91A52AB618C6
Loading PEIM at 0x000FFD5E6C0 EntryPoint=0x000FFD5EFF8 
InitializePchSmbusPeim() Start
Install PPI: 9CA93627-B65B-4324-A202-C0B461764543
Notify: PPI Guid: 9CA93627-B65B-4324-A202-C0B461764543, Peim notify entry point: FFFC2924
PEI SmbusExecute() Start
PEI SmbusExecute() End
Expected Clock Generator ID is 11, populated 31
PEI SmbusExecute() Start
PEI SmbusExecute() End
Register PPI Notify: F894643D-C449-42D1-8EA8-85BDD8C65BDE
InitializePchSmbusPeim() End
Loading PEIM at 0x000FFD5FFC0 EntryPoint=0x000FFD60AC0 
GUID HOB gEfiPlatformTxtDeviceMemoryGuid not found!
GUID HOB gEfiPlatformTxtPolicyDataGuid not found! Error when do TxtPei Init.
Loading PEIM at 0x000FFD61D20 EntryPoint=0x000FFD8C5F8 
Loading NV Setup variable.
ScrambleEn = 0x1
CMOS_LTSX_OFFSET(2A)= 0x00: for LT/TPM policy
Emulation Value is: 0!
Running on hardware
InitHeap() 
OemInitSerialDebug() 
Boot Mode check: Mode=1 OK

RC Version: 01400003 
QPI Init starting...


******* QPI Setup Structure *******
PPINrOptIn: 0
Bus   Ratio: 1 1 1 1
IO    Ratio: 1 1 1 1
MMIOL Ratio: 1 1 1 1
LegacyVgaSoc: 0
MmioP2pDis: 0
IsocAzaliaVc1En: 0
DebugPrintLevel: 15
AltRtid2S: 0
ClusterOnDieEn: 0
IBPECIEn: 0
E2EParityEn: 0
EarlySnoopEn: 0
DegradePrecedence: 0
QpiLinkSpeedMode: 1 (FAST)
QpiLinkSpeed: 6
QpiLinkL0pEn: 1
QpiLinkL1En: 1
QpiLinkL0rEn: 2
QpiLbEn: 0
IioUniphyDisable (per socket):   0  0  0  0
QpiLinkCreditReduce: 0
QpiConfigTxWci: 11
QpiCrcMode: 0
QpiCpuSktHotPlugEn: 0
QpiCpuSktHotPlugTopology: 0
QpiSkuMismatchCheck: 1
QpiPortDisable (per port):  S0:0 0 0   S1:0 0 0   S2:0 0 0   S3:0 0 0 
QpiLinkCreditReduce (per port):  S0:0 0 0   S1:0 0 0   S2:0 0 0   S3:0 0 0 
QpiLinkSpeed (per port):  S0:6 6 6   S1:6 6 6   S2:6 6 6   S3:6 6 6 
QpiProbeType (per port):  S0:0 0 0   S1:0 0 0   S2:0 0 0   S3:0 0 0 
QpiConfigTxWci (per port):  S0:11 11 11   S1:11 11 11   S2:11 11 11   S3:11 11 11 
Rsvd (per port):  S0:0 0 0   S1:0 0 0   S2:0 0 0   S3:0 0 0 


******* Common Setup Structure *******
mmCfgBase: 0x80000000 
mmCfgSize: 0x10000000
mmiolBase: 0x90000000 
mmiolSize: 0x6C000000 
mmiohBase: 0x00003800-00000000
mmiohSize: 128 GB 
numaEn: 1 
isocEn: 1 
mesegEn: 0 
dcaEn: 1 


******* Common Var Structure *******
resetRequired: 0 
state: 0 
numCpus: 0 
socketPresentBitMap: 0x01 
busIio: 0x00 0x00 0x00 0x00
busUncore: 0x3F 0x00 0x00 0x00 
mmCfgBase: 0x80000000 


;******* Collecting Early System Information - START *******Checkpoint Code: Socket 0, 0xA1, 0x00, 0x1FFF

    SocketId: 0    CAPID4: 0x04000582
;  SBSP Socket: 0   SKU: 0x04   SubSKU: 0x03   Stepping: 0x04   CAPID4[sbsp]: 0x04000582
;  Total Cbos: 18   Cbo List: 0x3FFFF   Total HA: 02   Total R3Qpi: 02   Total QpiAgent: 03

;  TotCpus: 4  CpuList: 0x0F 
;  busIio:    0x00 0x40 0x80 0xC0 
;  busUncore: 0x3F 0x7F 0xBF 0xFF 
;  Reset Type: Warm Reset   Link Speed: Fast Speed
;******* Collecting Early System Information - END   *******


;******* Setting up Minimum Path - START *******Checkpoint Code: Socket 0, 0xA3, 0x01, 0x0000


; Constructing SBSP minimum path Topology Tree 
; -------------------------------------------- 

; Adding SBSP (CPU0) to the treeCheckpoint Code: Socket 0, 0xA3, 0x02, 0x0020

   CPU0 Link Exchange
   UseQpiPcSts = 1 : LEP0(1,CPU1) : LEP1(1,CPU2) : LEP2(2,CPU3)


; Adding CPU1 to the treeCheckpoint Code: Socket 0, 0xA3, 0x01, 0x0040
Checkpoint Code: Socket 0, 0xA3, 0x05, 0x0040

;   Setting path between SBSP and CPU1. 
;   In SBSP setting route to CPU1 using port 0. 
;   In CPU1 using port 1 to set the R2PCIe route. 


; Adding CPU2 to the treeCheckpoint Code: Socket 0, 0xA3, 0x01, 0x0080
Checkpoint Code: Socket 0, 0xA3, 0x05, 0x0080

;   Setting path between SBSP and CPU2. 
;   In SBSP setting route to CPU2 using port 1. 
;   In CPU2 using port 1 to set the R2PCIe route. 


; Adding CPU3 to the treeCheckpoint Code: Socket 0, 0xA3, 0x01, 0x0100
Checkpoint Code: Socket 0, 0xA3, 0x05, 0x0100

;   Setting path between SBSP and CPU3. 
;   In SBSP setting route to CPU3 using port 2. 
;   In CPU3 using port 2 to set the R2PCIe route. 

    SocketId: 1    CAPID4: 0x04000582Checkpoint Code: Socket 0, 0xA3, 0x02, 0x0040

   CPU1 Link Exchange
   UseQpiPcSts = 1 : LEP0(1,CPU3) : LEP1(0,CPU0) : LEP2(0,CPU2)
Checkpoint Code: Socket 0, 0xA3, 0x03, 0x0040

    SocketId: 2    CAPID4: 0x04000582Checkpoint Code: Socket 0, 0xA3, 0x02, 0x0080

   CPU2 Link Exchange
   UseQpiPcSts = 1 : LEP0(2,CPU1) : LEP1(1,CPU0) : LEP2(0,CPU3)
Checkpoint Code: Socket 0, 0xA3, 0x03, 0x0080

    SocketId: 3    CAPID4: 0x04000582Checkpoint Code: Socket 0, 0xA3, 0x02, 0x0100

   CPU3 Link Exchange
   UseQpiPcSts = 1 : LEP0(2,CPU2) : LEP1(0,CPU1) : LEP2(2,CPU0)
Checkpoint Code: Socket 0, 0xA3, 0x03, 0x0100


;SBSP Minimum Path Tree
;----------------------
;Index  Socket  ParentPort  Hop  ParentIndex
; 00     CPU0    --         0     --
; 01     CPU1    01         1     00
; 02     CPU2    01         1     00
; 03     CPU3    02         1     00
;******* Setting up Minimum Path - END   *******


;******* Initialize MCTP - START *******
;******* Initialize MCTP - END   *******


;******* Check for QPI Topology Degradation - START *******Checkpoint Code: Socket 0, 0xA7, 0x01, 0x1FFF



;Link Exchange Parameter
;-----------------------
;CPU0 : LEP0(1:CPU1) : LEP1(1:CPU2) : LEP2(2:CPU3) 
;CPU1 : LEP0(1:CPU3) : LEP1(0:CPU0) : LEP2(0:CPU2) 
;CPU2 : LEP0(2:CPU1) : LEP1(1:CPU0) : LEP2(0:CPU3) 
;CPU3 : LEP0(2:CPU2) : LEP1(0:CPU1) : LEP2(2:CPU0) 
;  Already Reduced to Supported Topology

;  System will be treated 4S Configuration


;******* Check for QPI Topology Degradation - END *******


;******* Checking QPIRC Input Structure - START *******

;    Sys configuration Type = 1
;******* Checking QPIRC Input Structure - END   *******


;******* Allocate RTIDs - START *******
;    RTIDs Distribution :   TotPerCbo - 06
;    First Pool         :   TotPerCbo - 03   TotExtra - 05   TotAsym - 05
;    Second Pool        :   TotPerCbo - 03   TotExtra - 09   TotAsym - 09

; RTID Allocation Table
; ---------------------

;          Local          Neighbor
;          -----          --------
;         Base  Size    Base  Size

;  First Pool
;  ----------
;  WB      00  01         00  01 
;  UBOX    01  04         01  04 
;  MESEG   00  00         00  00 
;  CBO00   05  03         05  03 
;  CBO01   08  03         08  03 
;  CBO02   11  03         11  03 
;  CBO03   14  03         14  03 
;  CBO04   17  04         17  04 
;  CBO05   21  03         21  03 
;  CBO06   24  03         24  03 
;  CBO07   27  03         27  03 
;  CBO08   30  04         30  04 
;  CBO09   34  03         34  03 
;  CBO10   37  04         37  04 
;  CBO11   41  03         41  03 
;  CBO12   44  04         44  04 
;  CBO13   48  03         48  03 
;  CBO14   51  04         51  04 
;  CBO15   55  03         55  03 
;  CBO16   58  03         58  03 
;  CBO17   61  03         61  03 
;  CBO18   00  00         00  00 
;  CBO19   00  00         00  00 
;  CBO20   00  00         00  00 
;  CBO21   00  00         00  00 
;  CBO22   00  00         00  00 
;  CBO23   00  00         00  00 

;  Second Pool
;  ----------
;  CBO00   01  04         01  04 
;  CBO01   05  03         05  03 
;  CBO02   08  04         08  04 
;  CBO03   12  03         12  03 
;  CBO04   15  03         15  03 
;  CBO05   18  03         18  03 
;  CBO06   21  03         21  03 
;  CBO07   24  04         24  04 
;  CBO08   28  03         28  03 
;  CBO09   31  04         31  04 
;  CBO10   35  03         35  03 
;  CBO11   38  04         38  04 
;  CBO12   42  03         42  03 
;  CBO13   45  04         45  04 
;  CBO14   49  03         49  03 
;  CBO15   52  04         52  04 
;  CBO16   56  03         56  03 
;  CBO17   59  03         59  03 
;  CBO18   00  00         00  00 
;  CBO19   00  00         00  00 
;  CBO20   00  00         00  00 
;  CBO21   00  00         00  00 
;  CBO22   00  00         00  00 
;  CBO23   00  00         00  00 




;******* Allocate RTIDs - END *******


;******* Cacluate Resource Allocation - START *******Checkpoint Code: Socket 0, 0xA9, 0x01, 0x1FFF


;CPU Resource Allocation
;-----------------------
;CPU0   Bus: 0x00 - 0x3F  IO: 0x0000 - 0x3FFF  IOAPIC: 0xFEC00000 - 0xFEC3FFFF  MMIOL: 0x90000000 - 0xABFFFFFF  MMIOH: 0x00003800 00000000 - 0x0000381F FFFFFFFF
;CPU1   Bus: 0x40 - 0x7F  IO: 0x4000 - 0x7FFF  IOAPIC: 0xFEC40000 - 0xFEC7FFFF  MMIOL: 0xAC000000 - 0xC7FFFFFF  MMIOH: 0x00003820 00000000 - 0x0000383F FFFFFFFF
;CPU2   Bus: 0x80 - 0xBF  IO: 0x8000 - 0xBFFF  IOAPIC: 0xFEC80000 - 0xFECBFFFF  MMIOL: 0xC8000000 - 0xE3FFFFFF  MMIOH: 0x00003840 00000000 - 0x0000385F FFFFFFFF
;CPU3   Bus: 0xC0 - 0xFF  IO: 0xC000 - 0xFFFF  IOAPIC: 0xFECC0000 - 0xFECFFFFF  MMIOL: 0xE4000000 - 0xFBFFFFFF  MMIOH: 0x00003860 00000000 - 0x0000387F FFFFFFFF

;******* Cacluate Resource Allocation - END   *******


;******* Check for QPI Topology change across reset - START *******


;******* Check for QPI Topology change across reset - END *******


;******* Phy/Link Updates On Warm Reset - START *******
;  Force unused links to disabled/low power state.
;  Socket 0 QPI Link 0 Freq is currently 96.
;  Socket 0 QPI Link 1 Freq is currently 96.
;  Socket 0 QPI Link 2 Freq is currently 96.
;  Socket 1 QPI Link 0 Freq is currently 96.
;  Socket 1 QPI Link 1 Freq is currently 96.
;  Socket 1 QPI Link 2 Freq is currently 96.
;  Socket 2 QPI Link 0 Freq is currently 96.
;  Socket 2 QPI Link 1 Freq is currently 96.
;  Socket 2 QPI Link 2 Freq is currently 96.
;  Socket 3 QPI Link 0 Freq is currently 96.
;  Socket 3 QPI Link 1 Freq is currently 96.
;  Socket 3 QPI Link 2 Freq is currently 96.
;  System wide QPI Freq is currently 96.
;******* Phy/Link Updates On Warm Reset - END *******


;******* Sync Up PBSPs - START *******
;    Verifying if the remote socket(s) checked-in. 
;******* Sync Up PBSPs - END   *******
;  Wait for mailbox ready
;  Send Data portion of command.  Socket = 0 Data sent == 0x0
;  Send Pcode mailbox command. Socket = 0 Command sent == 0x91
;  Wait for mailbox ready
;  Wait for mailbox ready
;  Send Data portion of command.  Socket = 1 Data sent == 0x0
;  Send Pcode mailbox command. Socket = 1 Command sent == 0x91
;  Wait for mailbox ready
;  Wait for mailbox ready
;  Send Data portion of command.  Socket = 2 Data sent == 0x0
;  Send Pcode mailbox command. Socket = 2 Command sent == 0x91
;  Wait for mailbox ready
;  Wait for mailbox ready
;  Send Data portion of command.  Socket = 3 Data sent == 0x0
;  Send Pcode mailbox command. Socket = 3 Command sent == 0x91
;  Wait for mailbox ready


;******* Program Route Back Table - START *******Checkpoint Code: Socket 0, 0xAA, 0x04, 0x1FFF


; RBT Entries: 
; 000 : 0x00 
; 001 : 0x1F 
; 002 : 0x1F 
; 003 : 0x1F 
; 004 : 0x1F 
; 005 : 0x00 
; 006 : 0x00 
; 007 : 0x00 
; 008 : 0x01 
; 009 : 0x01 
; 010 : 0x01 
; 011 : 0x02 
; 012 : 0x02 
; 013 : 0x02 
; 014 : 0x03 
; 015 : 0x03 
; 016 : 0x03 
; 017 : 0x04 
; 018 : 0x04 
; 019 : 0x04 
; 020 : 0x04 
; 021 : 0x05 
; 022 : 0x05 
; 023 : 0x05 
; 024 : 0x06 
; 025 : 0x06 
; 026 : 0x06 
; 027 : 0x07 
; 028 : 0x07 
; 029 : 0x07 
; 030 : 0x08 
; 031 : 0x08 
; 032 : 0x08 
; 033 : 0x08 
; 034 : 0x09 
; 035 : 0x09 
; 036 : 0x09 
; 037 : 0x0A 
; 038 : 0x0A 
; 039 : 0x0A 
; 040 : 0x0A 
; 041 : 0x0B 
; 042 : 0x0B 
; 043 : 0x0B 
; 044 : 0x0C 
; 045 : 0x0C 
; 046 : 0x0C 
; 047 : 0x0C 
; 048 : 0x0D 
; 049 : 0x0D 
; 050 : 0x0D 
; 051 : 0x0E 
; 052 : 0x0E 
; 053 : 0x0E 
; 054 : 0x0E 
; 055 : 0x0F 
; 056 : 0x0F 
; 057 : 0x0F 
; 058 : 0x10 
; 059 : 0x10 
; 060 : 0x10 
; 061 : 0x11 
; 062 : 0x11 
; 063 : 0x11 
; 064 : 0x00 
; 065 : 0x00 
; 066 : 0x00 
; 067 : 0x00 
; 068 : 0x00 
; 069 : 0x01 
; 070 : 0x01 
; 071 : 0x01 
; 072 : 0x02 
; 073 : 0x02 
; 074 : 0x02 
; 075 : 0x02 
; 076 : 0x03 
; 077 : 0x03 
; 078 : 0x03 
; 079 : 0x04 
; 080 : 0x04 
; 081 : 0x04 
; 082 : 0x05 
; 083 : 0x05 
; 084 : 0x05 
; 085 : 0x06 
; 086 : 0x06 
; 087 : 0x06 
; 088 : 0x07 
; 089 : 0x07 
; 090 : 0x07 
; 091 : 0x07 
; 092 : 0x08 
; 093 : 0x08 
; 094 : 0x08 
; 095 : 0x09 
; 096 : 0x09 
; 097 : 0x09 
; 098 : 0x09 
; 099 : 0x0A 
; 100 : 0x0A 
; 101 : 0x0A 
; 102 : 0x0B 
; 103 : 0x0B 
; 104 : 0x0B 
; 105 : 0x0B 
; 106 : 0x0C 
; 107 : 0x0C 
; 108 : 0x0C 
; 109 : 0x0D 
; 110 : 0x0D 
; 111 : 0x0D 
; 112 : 0x0D 
; 113 : 0x0E 
; 114 : 0x0E 
; 115 : 0x0E 
; 116 : 0x0F 
; 117 : 0x0F 
; 118 : 0x0F 
; 119 : 0x0F 
; 120 : 0x10 
; 121 : 0x10 
; 122 : 0x10 
; 123 : 0x11 
; 124 : 0x11 
; 125 : 0x11 
; 126 : 0x00 
; 127 : 0x00 
;******* Program Route Back Table - END   *******


;******* Topology Dicovery and Optimum Route Calculation - START *******Checkpoint Code: Socket 0, 0xA7, 0x02, 0x1FFF


;  Locating the Rings Present in the Topology

;  No Rings Found

;  Constructing Topology TreeCheckpoint Code: Socket 0, 0xA7, 0x03, 0x1FE0


; Adjacency Table
; ----------------
;S0 P0 VN0 TX (00) :   S1 P1 VN0 RX (17)
;S0 P0 VN0 RX (01) :
;S0 P1 VN0 TX (04) :   S2 P1 VN0 RX (29)
;S0 P1 VN0 RX (05) :
;S0 P2 VN0 TX (08) :   S3 P2 VN0 RX (45)
;S0 P2 VN0 RX (09) :
;S1 P0 VN0 TX (12) :   S3 P1 VN0 RX (41)
;S1 P0 VN0 RX (13) :
;S1 P1 VN0 TX (16) :   S0 P0 VN0 RX (01)
;S1 P1 VN0 RX (17) :
;S1 P2 VN0 TX (20) :   S2 P0 VN0 RX (25)
;S1 P2 VN0 RX (21) :
;S2 P0 VN0 TX (24) :   S1 P2 VN0 RX (21)
;S2 P0 VN0 RX (25) :
;S2 P1 VN0 TX (28) :   S0 P1 VN0 RX (05)
;S2 P1 VN0 RX (29) :
;S2 P2 VN0 TX (32) :   S3 P0 VN0 RX (37)
;S2 P2 VN0 RX (33) :
;S3 P0 VN0 TX (36) :   S2 P2 VN0 RX (33)
;S3 P0 VN0 RX (37) :
;S3 P1 VN0 TX (40) :   S1 P0 VN0 RX (13)
;S3 P1 VN0 RX (41) :
;S3 P2 VN0 TX (44) :   S0 P2 VN0 RX (09)
;S3 P2 VN0 RX (45) :

; Checking for Deadlock...

;CPU0 Topology Tree
;-------------------
;Index  Socket  ParentSocket  ParentPort  ParentIndex  Hop
; 00     CPU0       --            --          --        0
; 01     CPU1      CPU0           01          00        1
; 02     CPU2      CPU0           01          00        1
; 03     CPU3      CPU0           02          00        1

;CPU1 Topology Tree
;-------------------
;Index  Socket  ParentSocket  ParentPort  ParentIndex  Hop
; 00     CPU1       --            --          --        0
; 01     CPU3      CPU1           01          00        1
; 02     CPU0      CPU1           00          00        1
; 03     CPU2      CPU1           00          00        1

;CPU2 Topology Tree
;-------------------
;Index  Socket  ParentSocket  ParentPort  ParentIndex  Hop
; 00     CPU2       --            --          --        0
; 01     CPU1      CPU2           02          00        1
; 02     CPU0      CPU2           01          00        1
; 03     CPU3      CPU2           00          00        1

;CPU3 Topology Tree
;-------------------
;Index  Socket  ParentSocket  ParentPort  ParentIndex  Hop
; 00     CPU3       --            --          --        0
; 01     CPU2      CPU3           02          00        1
; 02     CPU1      CPU3           00          00        1
; 03     CPU0      CPU3           02          00        1
;
"S0 P0 VN0 TX" -> "S1 P1 VN0 RX";
"S0 P1 VN0 TX" -> "S2 P1 VN0 RX";
"S0 P2 VN0 TX" -> "S3 P2 VN0 RX";
;
"S1 P0 VN0 TX" -> "S3 P1 VN0 RX";
"S1 P1 VN0 TX" -> "S0 P0 VN0 RX";
"S1 P2 VN0 TX" -> "S2 P0 VN0 RX";
;
"S2 P0 VN0 TX" -> "S1 P2 VN0 RX";
"S2 P1 VN0 TX" -> "S0 P1 VN0 RX";
"S2 P2 VN0 TX" -> "S3 P0 VN0 RX";
;
"S3 P0 VN0 TX" -> "S2 P2 VN0 RX";
"S3 P1 VN0 TX" -> "S1 P0 VN0 RX";
"S3 P2 VN0 TX" -> "S0 P2 VN0 RX";
; Calculating Route for CPU0 Checkpoint Code: Socket 0, 0xA7, 0x04, 0x0020

; Calculating Route for CPU1 Checkpoint Code: Socket 0, 0xA7, 0x04, 0x0040

; Calculating Route for CPU2 Checkpoint Code: Socket 0, 0xA7, 0x04, 0x0080

; Calculating Route for CPU3 Checkpoint Code: Socket 0, 0xA7, 0x04, 0x0100



;CPU 0 Routing Table
;-------------------
;DestSocket  Port
;   CPU1       0
;   CPU2       1
;   CPU3       2


;CPU 1 Routing Table
;-------------------
;DestSocket  Port
;   CPU0       1
;   CPU2       2
;   CPU3       0


;CPU 2 Routing Table
;-------------------
;DestSocket  Port
;   CPU0       1
;   CPU1       0
;   CPU3       2


;CPU 3 Routing Table
;-------------------
;DestSocket  Port
;   CPU0       2
;   CPU1       1
;   CPU2       0


;******* Topology Dicovery and Optimum Route Calculation - END   *******


;******* Program Optimum Route Table Settings - START *******Checkpoint Code: Socket 0, 0xA8, 0xFF, 0x1FFF

;******* Program Optimum Route Table Settings - END   *******


;******* Program Final IO SAD Setting - START *******Checkpoint Code: Socket 0, 0xA9, 0x02, 0x1FFF
Checkpoint Code: Socket 0, 0xA9, 0x02, 0x1FFF
Checkpoint Code: Socket 0, 0xA9, 0x03, 0x0027
Checkpoint Code: Socket 0, 0xA9, 0x03, 0x0047
Checkpoint Code: Socket 0, 0xA9, 0x03, 0x0087
Checkpoint Code: Socket 0, 0xA9, 0x03, 0x0107

;******* Program Final IO SAD Setting - END   *******


;******* Program Misc. QPI Parameters - START *******Checkpoint Code: Socket 0, 0xAA, 0x05, 0x1FFF

    Lock QPI DFX.
;******* Program Misc. QPI Parameters - END   *******


;******* Program Home Agent Credits - START *******Checkpoint Code: Socket 0, 0xAA, 0x03, 0x1FFF

;******* Program Home Agent Credits - END   *******


;******* Program System Coherency Registers - START *******Checkpoint Code: Socket 0, 0xAE, 0x00, 0x1FFF

;******* Program System Coherency Registers - END   *******


;******* Check for S3 Resume - START *******
;******* Check for S3 Resume - END   *******


;******* Collect Previous Boot Error - START *******
;******* Collect Previous Boot Error - END   *******


******* QPI Output Structure *******
OutLegacyVgaSoc: 0
OutIsocEn: 0
OutMesegEn: 0
OutIsocAzaliaVc1En: 0
OutClusterOnDieEn: 0
OutIBPECIEn: 0
OutE2EParityEn: 0
OutEarlySnoopEn: 0
QpiCurrentLinkSpeedMode: 1 (FAST)
OutQpiLinkSpeed: 5
OutQpiLinkL0pEn: 0
OutQpiLinkL1En: 1
OutQpiLinkL0rEn: 2
OutIioUniphyDisable: 0, 0, 0, 0
OutQpiCrcMode: 0
OutClusterOnDieReduction: 0

QpiInternalGlobal->BtModeEn: 1
QpiInternalGlobal->BtMode: 1
QpiInternalGlobal->BtMode2Alt: 0
QpiInternalGlobal->SnoopFanoutEn: 0
QpiInternalGlobal->SysSnoopMode: 3Checkpoint Code: Socket 0, 0xAF, 0x00, 0x1FFF

;******* QPIRC Exit  *******

QPI Init completed! Reset Requested: 0
SetBIOSInitDone: Setting RST_CPL bit1 everywhere...
BIOS_RST_CPL_1 set on socket 1
BIOS_RST_CPL_1 set on socket 2
BIOS_RST_CPL_1 set on socket 3
BIOS_RST_CPL_1 set on socket 0
SetBIOSInitDone: Clear DMICtrlAutoPmCmplt...
DMICTRL.auto_complete_pm cleared on socket 0
Pipe Init starting...Pass PIPE_DISPATCH_SYNCH_PSYSHOST
Pass PeiPipeSlaveInit
Pass pointer to host
Copy host structure

Synch of host structure to Socket 1 starting...
Pass PIPE_DISPATCH_SYNCH_PSYSHOST
N1 Checked into Pipe
Pass PeiPipeSlaveInit
Pass pointer to host
Copy host structure

Synch of host structure to Socket 2 starting...
Pass PIPE_DISPATCH_SYNCH_PSYSHOST
N2 Checked into Pipe
Pass PeiPipeSlaveInit
Pass pointer to host
Copy host structure

Synch of host structure to Socket 3 starting...
Pipe Init completed! Reset Requested: 0
N3 Checked into Pipe
CPU Feature Early Config starting...
Config IOT/OCLA Start: resetRequired = 0 

Config IOT/OCLA end. resetRequired = 0 
CPU miscellaneous configuration...
CPUMISC Current socket:         00
PcodeMailboxStatus = 0,  PCU_MISC_CONFIG  = 9840000
CPUMISC Current socket:         01
PcodeMailboxStatus = 0,  PCU_MISC_CONFIG  = 9840000
CPUMISC Current socket:         02
PcodeMailboxStatus = 0,  PCU_MISC_CONFIG  = 9840000
CPUMISC Current socket:         03
PcodeMailboxStatus = 0,  PCU_MISC_CONFIG  = 9840000
completed!
CPU Feature Early Config completed! Reset Requested: 0
Collect Previous Boot errors - start

CpuType = 0, CpuSubType = 2

MemoryQpiInitHsxlib: CPU_HSX_EX, CPU_BDX_EX
PrevBootErrors - Valid MCA UC entries: 0
Collect Previous Boot errors - end
START_MRC_RUN

sizeof sysHost = 286634

sizeof sysVar = 73483

sizeof memVar = 41569

sizeof cpuVar = 600

sizeof qpi_host_out = 494

sizeof commonVar = 1636

sizeof sysNvram = 208995

sizeof cpuNvram = 20

sizeof memNvram = 1505

sizeof qpiNvram = 56

sizeof commonNvram = 207414

sizeof commonImcNvram = 25925

sizeof nodeIMC = 3856

sizeof ddrChannel = 825

sizeof vmseChannelNvram = 2407

sizeof channelNvram = 5134

sizeof jckddrvar = 32076

sizeof sysHostSetup = 1698

struct sysHost.common {
  options:         00000005
      PROMOTE_WARN_EN         1
      PROMOTE_MRC_WARN_EN     0
      HALT_ON_ERROR_EN        1
  lowGap:          20
  highGap:         01
  serialDebugMsgLvl:0012
  bsdBreakpoint:   00
  maxAddrMem:      40000
  debugPort:       80
  nvramPtr:        00000000
  sysHostBufferPtr:00000000
  mmCfgBase:       80000000
  mmCfgSize:       10000000
  mmiohSize:       00000080
  pchumaEn:        00
  numaEn:          01
  isocEn:          01
  dcaEn:           01
  bdatEn:          00
  consoleComPort:  3F8
  ptrrSupport      01

struct sysHost.setup.mem {
  options:         C990DEA8
      TEMPHIGH_EN              0
      PDWN_IBT_OFF_EN          0
      PDWN_SR_CKE_MODE         0
      OPP_SELF_REF_EN          1
      MDLL_SHUT_DOWN_EN        0
      PAGE_POLICY              1
      ALLOW2XREF_EN            0
      MULTI_THREAD_MRC_EN      1
      ADAPTIVE_PAGE_EN         0
      CMD_CLK_TRAINING_EN      1
      SCRAMBLE_EN              1
      NUMA_AWARE               1
      ECC_CHECK_EN             1
      BALANCED_4WAY_EN         0
      CA_PARITY_EN             1
      SPLIT_BELOW_4GB_EN       0
      MARGIN_RANKS_EN          1
      MEMORY_TEST_FAST_BOOT_EN 1
      ATTEMPT_FAST_BOOT        0
      ZQ_CALIBRATION_EN        1
      PC6_CMD_ADDR_STANDBY_EN  0
      PROC_EIST_EN  1
      LRD_SUBRNK_C2CAS_TIM_EN  1
      DIMM_LRDIMM_3DS_SUPPORT  0
      PROMOTE_MEM_TRAIN_ERRORS 0
      PROMOTE_MEM_RAS_WARNINGS 0
      VMSE_CLOCK_STOP_EN 1
      SAFE_MC_BGF_PSV_EN            1

  options2:         16B003BA
      ADR_SUPPORT_EN                0
      HA_EARLY_WRITE_POST_EN        1
      MC_CHANNEL_HASH_MODE          0
      UNUSED_MEM_CHANNEL_INPUTS_EN  1
      PDA_EN                        0
      READ_VREF_CENTER_EN           1
      WRITE_VREF_CENTER_EN          1
      CMD_2_DATA_TUNING             1
      THERMAL_SENSOR_EN             1
      CATASTROPHIC_TRIP_EN          1
      VUNIT_CLOCK_GATING_EN         0
      TUNIT_CLOCK_GATING_EN         0
      MUNIT_CLOCK_GATING_EN         0
      DUNIT_CLOCK_GATING_EN         0
      CPGC_MEMORY_TEST_EN           0
      CPGC_MEMORY_ECC_EN            1
      OPP_READ_DURING_WMM           0
      PSMI_SUPPORT_EN               0
      JCK_PWR_MGMT_EN               0
      DISPLAY_EYE_EN   0
      ADVANCED_CLK_TRAINING         0
      RXVREF_PERSTROBE_TRAINING     0
      ADVANCED_STROBE_CENTERING     1
      ODT TIMING MODE               1
      EXT_DIMM_VREF_CIRCUIT         0
      BIOS_VMSE_RESET               1
      JCK_SAVE_ERRLOGS              0
      JKT_ERROR_FLOW                0
      VMSE_DISABLE_RCOMP            0
      MXB_RANK_SHARING_MODE         1
      JCK PER DIMM PARITY ERROR EN  0
      DDR4_DIMM_ISOLATION_ENABLE    0

  vmseOptions:         0000E041
      VMSE_MODE_2_1             1
      VMSE_PREAMBLE_2UI         0
      SAFE_TURN_AROUND_TIMINGS  0
      VMSE_RANK_MARGIN_TOOL_EN  0
      VMT Pattern Length (loop count)  00
      VMSE_NB_PERST_EN          0
      VMSE_SB_PERST_EN          1
      RESTORE_VMSE_TRAININGS_ON_FAST_BOOT          0
      VMSE_DATA_SCRAMBLING_EN  1
      VMSE_CMD_SCRAMBLING_EN   1
      VMSE_CMD_SCR_ON_RETRY_EN 1

  RASmodeEx:       06
      DEVTAGGING_EN        0
      Bank SDDC_EN        0
      DMNDSCRB_EN        1
      PTRLSCRB_EN        1
      DDDC_EN            0
      Bank DDDC_EN       0
      A7_MODE            0
      DDDC_WIREKILL      0
      GLOBAL_RAS_POLICY  0

  RASmode:         00
      RK_SPARE             0
      CH_LOCKSTEP          0
      CH_MIRROR            0

struct sysHost.setup.mem {
  VMSE PI Increment:        02
  VMSE VREF Increment:      04
  enforcePOR:      00
  ddrFreqLimit:    00
  nodeInter:       02
  chInter:         04
  rankInter:       08
  dimmTypeSupport: 02
  pdwnCkMode:      00
  MemPwrSave:      01
  ckeThrottling:   01
  olttPeakBWLIMITPercent: 00
  thermalThrottlingOptions:  08
      CLTT_EN             1
      MH_OUTPUT_EN        0
      MH_SENSE_EN         0
  dramraplen:      02
  dramraplbwlimittf: 01
  dramraplRefreshBase: 0A
  dramMaint: 02
  electricalThrottling:  00
  forceRankMult:   00
  lrdimmModuleDelay: 01
  cmdClkEyeWidth:  64
  rmtPatternLength:0F
  patrolScrubDuration:18
  spareErrTh:      0x7FFF
  WirekillRankTh:  0x02
  leakyBktLo:      0x28
  leakyBktHi:      0x29
  scrambleSeedLow: 00000000
  scrambleSeedHigh:00000000
  check_pm_sts:    00
  check_platform_detect: 00
  pushtoCasLatency:        0x16
  phaseShedding:           0x01
  laiMode:                 0x00
  tolm:                    0x01
  mcODTOverride:           0x00
  numSparTrans:            0x0004
  earlyCmdTraining:        0x01
  nbErrTh:             0xFF
  sbErrTh:                 0x1FFF
  vmseLinkFailTh:          0x07
  migrationSpareMask       0x00
  memMirroringMode:        0x00
  memMirorEnableMap:       0x00
      MIRROR_SCRUB     1
  partialMirrorSize[00] = 0001 [64MB] 
  struct ddrIMCSetup[00] {
    enabled:        00000001
    ddrVddLimit:    00
    struct ddrChannelSetup[00] {
      enabled:       01
      batterybacked: 00
      rankMask:      FF
      numDimmSlots:  03
      struct ddrDimmSetup[00] {
        mapOut[00]: 00
        mapOut[01]: 00
        mapOut[02]: 00
        mapOut[03]: 00
    };
      struct ddrDimmSetup[01] {
        mapOut[00]: 00
        mapOut[01]: 00
        mapOut[02]: 00
        mapOut[03]: 00
    };
      struct ddrDimmSetup[02] {
        mapOut[00]: 00
        mapOut[01]: 00
        mapOut[02]: 00
        mapOut[03]: 00
    };
    };
    struct ddrChannelSetup[01] {
      enabled:       01
      batterybacked: 00
      rankMask:      FF
      numDimmSlots:  03
      struct ddrDimmSetup[00] {
        mapOut[00]: 00
        mapOut[01]: 00
        mapOut[02]: 00
        mapOut[03]: 00
    };
      struct ddrDimmSetup[01] {
        mapOut[00]: 00
        mapOut[01]: 00
        mapOut[02]: 00
        mapOut[03]: 00
    };
      struct ddrDimmSetup[02] {
        mapOut[00]: 00
        mapOut[01]: 00
        mapOut[02]: 00
        mapOut[03]: 00
    };
    };
    struct ddrChannelSetup[02] {
      enabled:       01
      batterybacked: 00
      rankMask:      FF
      numDimmSlots:  03
      struct ddrDimmSetup[00] {
        mapOut[00]: 00
        mapOut[01]: 00
        mapOut[02]: 00
        mapOut[03]: 00
    };
      struct ddrDimmSetup[01] {
        mapOut[00]: 00
        mapOut[01]: 00
        mapOut[02]: 00
        mapOut[03]: 00
    };
      struct ddrDimmSetup[02] {
        mapOut[00]: 00
        mapOut[01]: 00
        mapOut[02]: 00
        mapOut[03]: 00
    };
    };
    struct ddrChannelSetup[03] {
      enabled:       01
      batterybacked: 00
      rankMask:      FF
      numDimmSlots:  03
      struct ddrDimmSetup[00] {
        mapOut[00]: 00
        mapOut[01]: 00
        mapOut[02]: 00
        mapOut[03]: 00
    };
      struct ddrDimmSetup[01] {
        mapOut[00]: 00
        mapOut[01]: 00
        mapOut[02]: 00
        mapOut[03]: 00
    };
      struct ddrDimmSetup[02] {
        mapOut[00]: 00
        mapOut[01]: 00
        mapOut[02]: 00
        mapOut[03]: 00
    };
    };
  partialMirrorSize[01] = 0001 [64MB] 
  struct ddrIMCSetup[01] {
    enabled:        00000001
    ddrVddLimit:    00
    struct ddrChannelSetup[00] {
      enabled:       01
      batterybacked: 00
      rankMask:      FF
      numDimmSlots:  03
      struct ddrDimmSetup[00] {
        mapOut[00]: 00
        mapOut[01]: 00
        mapOut[02]: 00
        mapOut[03]: 00
    };
      struct ddrDimmSetup[01] {
        mapOut[00]: 00
        mapOut[01]: 00
        mapOut[02]: 00
        mapOut[03]: 00
    };
      struct ddrDimmSetup[02] {
        mapOut[00]: 00
        mapOut[01]: 00
        mapOut[02]: 00
        mapOut[03]: 00
    };
    };
    struct ddrChannelSetup[01] {
      enabled:       01
      batterybacked: 00
      rankMask:      FF
      numDimmSlots:  03
      struct ddrDimmSetup[00] {
        mapOut[00]: 00
        mapOut[01]: 00
        mapOut[02]: 00
        mapOut[03]: 00
    };
      struct ddrDimmSetup[01] {
        mapOut[00]: 00
        mapOut[01]: 00
        mapOut[02]: 00
        mapOut[03]: 00
    };
      struct ddrDimmSetup[02] {
        mapOut[00]: 00
        mapOut[01]: 00
        mapOut[02]: 00
        mapOut[03]: 00
    };
    };
    struct ddrChannelSetup[02] {
      enabled:       01
      batterybacked: 00
      rankMask:      FF
      numDimmSlots:  03
      struct ddrDimmSetup[00] {
        mapOut[00]: 00
        mapOut[01]: 00
        mapOut[02]: 00
        mapOut[03]: 00
    };
      struct ddrDimmSetup[01] {
        mapOut[00]: 00
        mapOut[01]: 00
        mapOut[02]: 00
        mapOut[03]: 00
    };
      struct ddrDimmSetup[02] {
        mapOut[00]: 00
        mapOut[01]: 00
        mapOut[02]: 00
        mapOut[03]: 00
    };
    };
    struct ddrChannelSetup[03] {
      enabled:       01
      batterybacked: 00
      rankMask:      FF
      numDimmSlots:  03
      struct ddrDimmSetup[00] {
        mapOut[00]: 00
        mapOut[01]: 00
        mapOut[02]: 00
        mapOut[03]: 00
    };
      struct ddrDimmSetup[01] {
        mapOut[00]: 00
        mapOut[01]: 00
        mapOut[02]: 00
        mapOut[03]: 00
    };
      struct ddrDimmSetup[02] {
        mapOut[00]: 00
        mapOut[01]: 00
        mapOut[02]: 00
        mapOut[03]: 00
    };
    };
  };
}; //struct sysHost.setup

CPU Frequency: 0  2500 (MHz)
N0: Clearing the MRC NVRAM structure.
N0: nvram node enabled = 0x1
N1: nvram node enabled = 0x1
bootMode = NormalBoot. Taking the normal boot path through MRC.
subBootMode = ColdBoot. Taking the cold boot sub-path through MRC.
CPU type is CPU_HSX and stepping is D0_REV_HSX: Apply all HSX D0/E0 WAs
Checkpoint Code: Socket 0, 0xB0, 0x02, 0x0000
Checkpoint Code: Socket 0, 0xB0, 0x10, 0x0000
N0: InitMemoryRiser: Stage 0 - Init VPP
N0.C0: InitMemoryRiser: Stage 0 - Init VMSE ERR
N0.C2: InitMemoryRiser: Stage 0 - Init VMSE ERR
N0: InitMemoryRiser: Read Initial SLTCON Data = 0x3C0
N0: InitMemoryRiser: slotCon.Bits.power_controller_control = 0, slotCon.Bits.power_indicator_control = 1
N0: InitMemoryRiser: Write SLTCON Data = 0x1E5
N0: InitMemoryRiser: Initialize hotplug events 
N1.C0: InitMemoryRiser: Stage 0 - Init VMSE ERR
N1.C2: InitMemoryRiser: Stage 0 - Init VMSE ERR
N1: InitMemoryRiser: Read Initial SLTCON Data = 0x3C0
N0: InitMemoryRiser: slotCon.Bits.power_controller_control = 0, slotCon.Bits.power_indicator_control = 1
N1: InitMemoryRiser: Write SLTCON Data = 0x1E5
N1: InitMemoryRiser: Initialize hotplug events 
N0: InitMemoryRiser: vpp enabled set. Skip update. vppMemN1org Data = 0x3
Checkpoint Code: Socket 0, 0xB0, 0x11, 0x0000
N0: InitMemoryRiser: Stage 1 - Init SLTCon
N0: InitMemoryRiser: Read Initial SLTCON Data = 0x1E5
Checkpoint Code: Socket 0, 0xB0, 0x11, 0x0000
N1: InitMemoryRiser: Stage 1 - Init SLTCon
N1: InitMemoryRiser: Read Initial SLTCON Data = 0x1E5
Checkpoint Code: Socket 0, 0xB0, 0x14, 0x0000
N0: InitMemoryRiser: Power Enable Good detection
N0: InitMemoryRiser: Power Enable Good
Checkpoint Code: Socket 0, 0xB0, 0x14, 0x0000
N1: InitMemoryRiser: Power Enable Good detection
N1: InitMemoryRiser: Power Enable Good
Checkpoint Code: Socket 0, 0xB0, 0x04, 0x0001
N0: VmseResetViaVpp: Write SLTCON Data = 0x9E5
N0: VmseResetViaVpp: Write SLTCON Data = 0x1E5
N1: VmseResetViaVpp: Write SLTCON Data = 0x9E5
N1: VmseResetViaVpp: Write SLTCON Data = 0x1E5
Multi-Threaded MRC Init
Dispatch S1 for mem init
Skt1 Entering MRC

sizeof sysHost = 286634

sizeof sysVar = 73483

sizeof memVar = 41569

sizeof cpuVar = 600

sizeof qpi_host_out = 494

sizeof commonVar = 1636

sizeof sysNvram = 208995

sizeof cpuNvram = 20

sizeof memNvram = 1505

sizeof qpiNvram = 56

sizeof commonNvram = 207414

sizeof commonImcNvram = 25925

sizeof nodeIMC = 3856

sizeof ddrChannel = 825

sizeof vmseChannelNvram = 2407

sizeof channelNvram = 5134

sizeof jckddrvar = 32076

sizeof sysHostSetup = 1698

struct sysHost.common {
  options:         00000005
      PROMOTE_WARN_EN         1
      PROMOTE_MRC_WARN_EN     0
      HALT_ON_ERROR_EN        1
  lowGap:          20
  highGap:         01
  serialDebugMsgLvl:0012
  bsdBreakpoint:   00
  maxAddrMem:      40000
  debugPort:       80
  nvramPtr:        00000000
  sysHostBufferPtr:00000000
  mmCfgBase:       80000000
  mmCfgSize:       10000000
  mmiohSize:       00000080
  pchumaEn:        00
  numaEn:          01
  isocEn:          01
  dcaEn:           01
  bdatEn:          00
  consoleComPort:  3F8
  ptrrSupport      01

struct sysHost.setup.mem {
  options:         C990DEA8
      TEMPHIGH_EN              0
      PDWN_IBT_OFF_EN          0
      PDWN_SR_CKE_MODE         0
      OPP_SELF_REF_EN          1
      MDLL_SHUT_DOWN_EN        0
      PAGE_POLICY              1
      ALLOW2XREF_EN            0
      MULTI_THREAD_MRC_EN      1
      ADAPTIVE_PAGE_EN         0
      CMD_CLK_TRAINING_EN      1
      SCRAMBLE_EN              1
      NUMA_AWARE               1
      ECC_CHECK_EN             1
      BALANCED_4WAY_EN         0
      CA_PARITY_EN             1
      SPLIT_BELOW_4GB_EN       0
      MARGIN_RANKS_EN          1
      MEMORY_TEST_FAST_BOOT_EN 1
      ATTEMPT_FAST_BOOT        0
      ZQ_CALIBRATION_EN        1
      PC6_CMD_ADDR_STANDBY_EN  0
      PROC_EIST_EN  1
      LRD_SUBRNK_C2CAS_TIM_EN  1
      DIMM_LRDIMM_3DS_SUPPORT  0
      PROMOTE_MEM_TRAIN_ERRORS 0
      PROMOTE_MEM_RAS_WARNINGS 0
      VMSE_CLOCK_STOP_EN 1
      SAFE_MC_BGF_PSV_EN            1

  options2:         16B003BA
      ADR_SUPPORT_EN                0
      HA_EARLY_WRITE_POST_EN        1
      MC_CHANNEL_HASH_MODE          0
      UNUSED_MEM_CHANNEL_INPUTS_EN  1
      PDA_EN                        0
      READ_VREF_CENTER_EN           1
      WRITE_VREF_CENTER_EN          1
      CMD_2_DATA_TUNING             1
      THERMAL_SENSOR_EN             1
      CATASTROPHIC_TRIP_EN          1
      VUNIT_CLOCK_GATING_EN         0
      TUNIT_CLOCK_GATING_EN         0
      MUNIT_CLOCK_GATING_EN         0
      DUNIT_CLOCK_GATING_EN         0
      CPGC_MEMORY_TEST_EN           0
      CPGC_MEMORY_ECC_EN            1
      OPP_READ_DURING_WMM           0
      PSMI_SUPPORT_EN               0
      JCK_PWR_MGMT_EN               0
      DISPLAY_EYE_EN   0
      ADVANCED_CLK_TRAINING         0
      RXVREF_PERSTROBE_TRAINING     0
      ADVANCED_STROBE_CENTERING     1
      ODT TIMING MODE               1
      EXT_DIMM_VREF_CIRCUIT         0
      BIOS_VMSE_RESET               1
      JCK_SAVE_ERRLOGS              0
      JKT_ERROR_FLOW                0
      VMSE_DISABLE_RCOMP            0
      MXB_RANK_SHARING_MODE         1
      JCK PER DIMM PARITY ERROR EN  0
      DDR4_DIMM_ISOLATION_ENABLE    0

  vmseOptions:         0000E041
      VMSE_MODE_2_1             1
      VMSE_PREAMBLE_2UI         0
      SAFE_TURN_AROUND_TIMINGS  0
      VMSE_RANK_MARGIN_TOOL_EN  0
      VMT Pattern Length (loop count)  00
      VMSE_NB_PERST_EN          0
      VMSE_SB_PERST_EN          1
      RESTORE_VMSE_TRAININGS_ON_FAST_BOOT          0
      VMSE_DATA_SCRAMBLING_EN  1
      VMSE_CMD_SCRAMBLING_EN   1
      VMSE_CMD_SCR_ON_RETRY_EN 1

  RASmodeEx:       06
      DEVTAGGING_EN        0
      Bank SDDC_EN        0
      DMNDSCRB_EN        1
      PTRLSCRB_EN        1
      DDDC_EN            0
      Bank DDDC_EN       0
      A7_MODE            0
      DDDC_WIREKILL      0
      GLOBAL_RAS_POLICY  0

  RASmode:         00
      RK_SPARE             0
      CH_LOCKSTEP          0
      CH_MIRROR            0

struct sysHost.setup.mem {
  VMSE PI Increment:        02
  VMSE VREF Increment:      04
  enforcePOR:      00
  ddrFreqLimit:    00
  nodeInter:       02
  chInter:         04
  rankInter:       08
  dimmTypeSupport: 02
  pdwnCkMode:      00
  MemPwrSave:      01
  ckeThrottling:   01
  olttPeakBWLIMITPercent: 00
  thermalThrottlingOptions:  08
      CLTT_EN             1
      MH_OUTPUT_EN        0
      MH_SENSE_EN         0
  dramraplen:      02
  dramraplbwlimittf: 01
  dramraplRefreshBase: 0A
  dramMaint: 02
  electricalThrottling:  00
  forceRankMult:   00
  lrdimmModuleDelay: 01
  cmdClkEyeWidth:  64
  rmtPatternLength:0F
  patrolScrubDuration:18
  spareErrTh:      0x7FFF
  WirekillRankTh:  0x02
  leakyBktLo:      0x28
  leakyBktHi:      0x29
  scrambleSeedLow: 00000000
  scrambleSeedHigh:00000000
  check_pm_sts:    00
  check_platform_detect: 00
  pushtoCasLatency:        0x16
  phaseShedding:           0x01
  laiMode:                 0x00
  tolm:                    0x01
  mcODTOverride:           0x00
  numSparTrans:            0x0004
  earlyCmdTraining:        0x01
  nbErrTh:             0xFF
  sbErrTh:                 0x1FFF
  vmseLinkFailTh:          0x07
  migrationSpareMask       0x00
  memMirroringMode:        0x00
  memMirorEnableMap:       0x00
      MIRROR_SCRUB     1
  partialMirrorSize[02] = 0001 [64MB] 
  struct ddrIMCSetup[02] {
    enabled:        00000001
    ddrVddLimit:    00
    struct ddrChannelSetup[00] {
      enabled:       01
      batterybacked: 00
      rankMask:      FF
      numDimmSlots:  03
      struct ddrDimmSetup[00] {
        mapOut[00]: 00
        mapOut[01]: 00
        mapOut[02]: 00
        mapOut[03]: 00
    };
      struct ddrDimmSetup[01] {
        mapOut[00]: 00
        mapOut[01]: 00
        mapOut[02]: 00
        mapOut[03]: 00
    };
      struct ddrDimmSetup[02] {
        mapOut[00]: 00
        mapOut[01]: 00
        mapOut[02]: 00
        mapOut[03]: 00
    };
    };
    struct ddrChannelSetup[01] {
      enabled:       01
      batterybacked: 00
      rankMask:      FF
      numDimmSlots:  03
      struct ddrDimmSetup[00] {
        mapOut[00]: 00
        mapOut[01]: 00
        mapOut[02]: 00
        mapOut[03]: 00
    };
      struct ddrDimmSetup[01] {
        mapOut[00]: 00
        mapOut[01]: 00
        mapOut[02]: 00
        mapOut[03]: 00
    };
      struct ddrDimmSetup[02] {
        mapOut[00]: 00
        mapOut[01]: 00
        mapOut[02]: 00
        mapOut[03]: 00
    };
    };
    struct ddrChannelSetup[02] {
      enabled:       01
      batterybacked: 00
      rankMask:      FF
      numDimmSlots:  03
      struct ddrDimmSetup[00] {
        mapOut[00]: 00
        mapOut[01]: 00
        mapOut[02]: 00
        mapOut[03]: 00
    };
      struct ddrDimmSetup[01] {
        mapOut[00]: 00
        mapOut[01]: 00
        mapOut[02]: 00
        mapOut[03]: 00
    };
      struct ddrDimmSetup[02] {
        mapOut[00]: 00
        mapOut[01]: 00
        mapOut[02]: 00
        mapOut[03]: 00
    };
    };
    struct ddrChannelSetup[03] {
      enabled:       01
      batterybacked: 00
      rankMask:      FF
      numDimmSlots:  03
      struct ddrDimmSetup[00] {
        mapOut[00]: 00
        mapOut[01]: 00
        mapOut[02]: 00
        mapOut[03]: 00
    };
      struct ddrDimmSetup[01] {
        mapOut[00]: 00
        mapOut[01]: 00
        mapOut[02]: 00
        mapOut[03]: 00
    };
      struct ddrDimmSetup[02] {
        mapOut[00]: 00
        mapOut[01]: 00
        mapOut[02]: 00
        mapOut[03]: 00
    };
    };
  partialMirrorSize[03] = 0001 [64MB] 
  struct ddrIMCSetup[03] {
    enabled:        00000001
    ddrVddLimit:    00
    struct ddrChannelSetup[00] {
      enabled:       01
      batterybacked: 00
      rankMask:      FF
      numDimmSlots:  03
      struct ddrDimmSetup[00] {
        mapOut[00]: 00
        mapOut[01]: 00
        mapOut[02]: 00
        mapOut[03]: 00
    };
      struct ddrDimmSetup[01] {
        mapOut[00]: 00
        mapOut[01]: 00
        mapOut[02]: 00
        mapOut[03]: 00
    };
      struct ddrDimmSetup[02] {
        mapOut[00]: 00
        mapOut[01]: 00
        mapOut[02]: 00
        mapOut[03]: 00
    };
    };
    struct ddrChannelSetup[01] {
      enabled:       01
      batterybacked: 00
      rankMask:      FF
      numDimmSlots:  03
      struct ddrDimmSetup[00] {
        mapOut[00]: 00
        mapOut[01]: 00
        mapOut[02]: 00
        mapOut[03]: 00
    };
      struct ddrDimmSetup[01] {
        mapOut[00]: 00
        mapOut[01]: 00
        mapOut[02]: 00
        mapOut[03]: 00
    };
      struct ddrDimmSetup[02] {
        mapOut[00]: 00
        mapOut[01]: 00
        mapOut[02]: 00
        mapOut[03]: 00
    };
    };
    struct ddrChannelSetup[02] {
      enabled:       01
      batterybacked: 00
      rankMask:      FF
      numDimmSlots:  03
      struct ddrDimmSetup[00] {
        mapOut[00]: 00
        mapOut[01]: 00
        mapOut[02]: 00
        mapOut[03]: 00
    };
      struct ddrDimmSetup[01] {
        mapOut[00]: 00
        mapOut[01]: 00
        mapOut[02]: 00
        mapOut[03]: 00
    };
      struct ddrDimmSetup[02] {
        mapOut[00]: 00
        mapOut[01]: 00
        mapOut[02]: 00
        mapOut[03]: 00
    };
    };
    struct ddrChannelSetup[03] {
      enabled:       01
      batterybacked: 00
      rankMask:      FF
      numDimmSlots:  03
      struct ddrDimmSetup[00] {
        mapOut[00]: 00
        mapOut[01]: 00
        mapOut[02]: 00
        mapOut[03]: 00
    };
      struct ddrDimmSetup[01] {
        mapOut[00]: 00
        mapOut[01]: 00
        mapOut[02]: 00
        mapOut[03]: 00
    };
      struct ddrDimmSetup[02] {
        mapOut[00]: 00
        mapOut[01]: 00
        mapOut[02]: 00
        mapOut[03]: 00
    };
    };
  };
}; //struct sysHost.setup

CPU Frequency: 0  2500 (MHz)
N2: Clearing the MRC NVRAM structure.
N2: nvram node enabled = 0x1
N3: nvram node enabled = 0x1
bootMode = NormalBoot. Taking the normal boot path through MRC.
subBootMode = ColdBoot. Taking the cold boot sub-path through MRC.
CPU type is CPU_HSX and stepping is D0_REV_HSX: Apply all HSX D0/E0 WAs
N2: InitMemoryRiser: Stage 0 - Init VPP
N2.C0: InitMemoryRiser: Stage 0 - Init VMSE ERR
N2.C2: InitMemoryRiser: Stage 0 - Init VMSE ERR
N2: InitMemoryRiser: Read Initial SLTCON Data = 0x3C0
N2: InitMemoryRiser: slotCon.Bits.power_controller_control = 0, slotCon.Bits.power_indicator_control = 1
N2: InitMemoryRiser: Write SLTCON Data = 0x1E5
N2: InitMemoryRiser: Initialize hotplug events 
N3.C0: InitMemoryRiser: Stage 0 - Init VMSE ERR
N3.C2: InitMemoryRiser: Stage 0 - Init VMSE ERR
N3: InitMemoryRiser: Read Initial SLTCON Data = 0x3C0
N2: InitMemoryRiser: slotCon.Bits.power_controller_control = 0, slotCon.Bits.power_indicator_control = 1
N3: InitMemoryRiser: Write SLTCON Data = 0x1E5
N3: InitMemoryRiser: Initialize hotplug events 
N2: InitMemoryRiser: vpp enabled set. Skip update. vppMemN1org Data = 0x3
N2: InitMemoryRiser: Stage 1 - Init SLTCon
N2: InitMemoryRiser: Read Initial SLTCON Data = 0x1E5
N3: InitMemoryRiser: Stage 1 - Init SLTCon
N3: InitMemoryRiser: Read Initial SLTCON Data = 0x1E5
N2: InitMemoryRiser: Power Enable Good detection
N2: InitMemoryRiser: Power Enable Good
N3: InitMemoryRiser: Power Enable Good detection
N3: InitMemoryRiser: Power Enable Good
N2: VmseResetViaVpp: Write SLTCON Data = 0x9E5
N2: VmseResetViaVpp: Write SLTCON Data = 0x1E5
N3: VmseResetViaVpp: Write SLTCON Data = 0x9E5
N3: VmseResetViaVpp: Write SLTCON Data = 0x1E5
Dispatch S2 for mem init
N2: Init Throttling (Early)
Skt2 Entering MRC
N2: Detect DIMM Config

sizeof sysHost = 286634

sizeof sysVar = 73483

sizeof memVar = 41569

sizeof cpuVar = 600

sizeof qpi_host_out = 494

sizeof commonVar = 1636

sizeof sysNvram = 208995

sizeof cpuNvram = 20

sizeof memNvram = 1505

sizeof qpiNvram = 56

sizeof commonNvram = 207414

sizeof commonImcNvram = 25925

sizeof nodeIMC = 3856

sizeof ddrChannel = 825

sizeof vmseChannelNvram = 2407

sizeof channelNvram = 5134

sizeof jckddrvar = 32076

sizeof sysHostSetup = 1698

struct sysHost.common {
  options:         00000005
      PROMOTE_WARN_EN         1
      PROMOTE_MRC_WARN_EN     0
      HALT_ON_ERROR_EN        1
  lowGap:          20
  highGap:         01
  serialDebugMsgLvl:0012
  bsdBreakpoint:   00
  maxAddrMem:      40000
  debugPort:       80
  nvramPtr:        00000000
  sysHostBufferPtr:00000000
  mmCfgBase:       80000000
  mmCfgSize:       10000000
  mmiohSize:       00000080
  pchumaEn:        00
  numaEn:          01
  isocEn:          01
  dcaEn:           01
  bdatEn:          00
  consoleComPort:  3F8
  ptrrSupport      01

struct sysHost.setup.mem {
  options:         C990DEA8
      TEMPHIGH_EN              0
      PDWN_IBT_OFF_EN          0
      PDWN_SR_CKE_MODE         0
      OPP_SELF_REF_EN          1
      MDLL_SHUT_DOWN_EN        0
      PAGE_POLICY              1
      ALLOW2XREF_EN            0
      MULTI_THREAD_MRC_EN      1
      ADAPTIVE_PAGE_EN         0
      CMD_CLK_TRAINING_EN      1
      SCRAMBLE_EN              1
      NUMA_AWARE               1
      ECC_CHECK_EN             1
      BALANCED_4WAY_EN         0
      CA_PARITY_EN             1
      SPLIT_BELOW_4GB_EN       0
      MARGIN_RANKS_EN          1
      MEMORY_TEST_FAST_BOOT_EN 1
      ATTEMPT_FAST_BOOT        0
      ZQ_CALIBRATION_EN        1
      PC6_CMD_ADDR_STANDBY_EN  0
      PROC_EIST_EN  1
      LRD_SUBRNK_C2CAS_TIM_EN  1
      DIMM_LRDIMM_3DS_SUPPORT  0
      PROMOTE_MEM_TRAIN_ERRORS 0
      PROMOTE_MEM_RAS_WARNINGS 0
      VMSE_CLOCK_STOP_EN 1
      SAFE_MC_BGF_PSV_EN            1

  options2:         16B003BA
      ADR_SUPPORT_EN                0
      HA_EARLY_WRITE_POST_EN        1
      MC_CHANNEL_HASH_MODE          0
      UNUSED_MEM_CHANNEL_INPUTS_EN  1
      PDA_EN                        0
      READ_VREF_CENTER_EN           1
      WRITE_VREF_CENTER_EN          1
      CMD_2_DATA_TUNING             1
      THERMAL_SENSOR_EN             1
      CATASTROPHIC_TRIP_EN          1
      VUNIT_CLOCK_GATING_EN         0
      TUNIT_CLOCK_GATING_EN         0
      MUNIT_CLOCK_GATING_EN         0
      DUNIT_CLOCK_GATING_EN         0
      CPGC_MEMORY_TEST_EN           0
      CPGC_MEMORY_ECC_EN            1
      OPP_READ_DURING_WMM           0
      PSMI_SUPPORT_EN               0
      JCK_PWR_MGMT_EN               0
      DISPLAY_EYE_EN   0
      ADVANCED_CLK_TRAINING         0
      RXVREF_PERSTROBE_TRAINING     0
      ADVANCED_STROBE_CENTERING     1
      ODT TIMING MODE               1
      EXT_DIMM_VREF_CIRCUIT         0
      BIOS_VMSE_RESET               1
      JCK_SAVE_ERRLOGS              0
      JKT_ERROR_FLOW                0
      VMSE_DISABLE_RCOMP            0
      MXB_RANK_SHARING_MODE         1
      JCK PER DIMM PARITY ERROR EN  0
      DDR4_DIMM_ISOLATION_ENABLE    0

  vmseOptions:         0000E041
      VMSE_MODE_2_1             1
      VMSE_PREAMBLE_2UI         0
      SAFE_TURN_AROUND_TIMINGS  0
      VMSE_RANK_MARGIN_TOOL_EN  0
      VMT Pattern Length (loop count)  00
      VMSE_NB_PERST_EN          0
      VMSE_SB_PERST_EN          1
      RESTORE_VMSE_TRAININGS_ON_FAST_BOOT          0
      VMSE_DATA_SCRAMBLING_EN  1
      VMSE_CMD_SCRAMBLING_EN   1
      VMSE_CMD_SCR_ON_RETRY_EN 1

  RASmodeEx:       06
      DEVTAGGING_EN        0
      Bank SDDC_EN        0
      DMNDSCRB_EN        1
      PTRLSCRB_EN        1
      DDDC_EN            0
      Bank DDDC_EN       0
      A7_MODE            0
      DDDC_WIREKILL      0
      GLOBAL_RAS_POLICY  0

  RASmode:         00
      RK_SPARE             0
      CH_LOCKSTEP          0
      CH_MIRROR            0

struct sysHost.setup.mem {
  VMSE PI Increment:        02
  VMSE VREF Increment:      04
  enforcePOR:      00
  ddrFreqLimit:    00
  nodeInter:       02
  chInter:         04
  rankInter:       08
  dimmTypeSupport: 02
  pdwnCkMode:      00
  MemPwrSave:      01
  ckeThrottling:   01
  olttPeakBWLIMITPercent: 00
  thermalThrottlingOptions:  08
      CLTT_EN             1
      MH_OUTPUT_EN        0
      MH_SENSE_EN         0
  dramraplen:      02
  dramraplbwlimittf: 01
  dramraplRefreshBase: 0A
  dramMaint: 02
  electricalThrottling:  00
  forceRankMult:   00
  lrdimmModuleDelay: 01
  cmdClkEyeWidth:  64
  rmtPatternLength:0F
  patrolScrubDuration:18
  spareErrTh:      0x7FFF
  WirekillRankTh:  0x02
  leakyBktLo:      0x28
  leakyBktHi:      0x29
  scrambleSeedLow: 00000000
  scrambleSeedHigh:00000000
  check_pm_sts:    00
  check_platform_detect: 00
  pushtoCasLatency:        0x16
  phaseShedding:           0x01
  laiMode:                 0x00
  tolm:                    0x01
  mcODTOverride:           0x00
  numSparTrans:            0x0004
  earlyCmdTraining:        0x01
  nbErrTh:             0xFF
  sbErrTh:                 0x1FFF
  vmseLinkFailTh:          0x07
  migrationSpareMask       0x00
  memMirroringMode:        0x00
  memMirorEnableMap:       0x00
      MIRROR_SCRUB     1
  partialMirrorSize[04] = 0001 [64MB] 
  struct ddrIMCSetup[04] {
    enabled:        00000001
    ddrVddLimit:    00
    struct ddrChannelSetup[00] {
      enabled:       01
      batterybacked: 00
      rankMask:      FF
      numDimmSlots:  03
      struct ddrDimmSetup[00] {
        mapOut[00]: 00
        mapOut[01]: 00
        mapOut[02]: 00
        mapOut[03]: 00
    };
      struct ddrDimmSetup[01] {
        mapOut[00]: 00
        mapOut[01]: 00
        mapOut[02]: 00
        mapOut[03]: 00
    };
      struct ddrDimmSetup[02] {
        mapOut[00]: 00
        mapOut[01]: 00
        mapOut[02]: 00
        mapOut[03]: 00
    };
    };
    struct ddrChannelSetup[01] {
      enabled:       01
      batterybacked: 00
      rankMask:      FF
      numDimmSlots:  03
      struct ddrDimmSetup[00] {
        mapOut[00]: 00
        mapOut[01]: 00
        mapOut[02]: 00
        mapOut[03]: 00
    };
      struct ddrDimmSetup[01] {
        mapOut[00]: 00
        mapOut[01]: 00
        mapOut[02]: 00
        mapOut[03]: 00
    };
      struct ddrDimmSetup[02] {
        mapOut[00]: 00
        mapOut[01]: 00
        mapOut[02]: 00
        mapOut[03]: 00
    };
    };
    struct ddrChannelSetup[02] {
      enabled:       01
      batterybacked: 00
      rankMask:      FF
      numDimmSlots:  03
      struct ddrDimmSetup[00] {
        mapOut[00]: 00
        mapOut[01]: 00
        mapOut[02]: 00
        mapOut[03]: 00
    };
      struct ddrDimmSetup[01] {
        mapOut[00]: 00
        mapOut[01]: 00
        mapOut[02]: 00
        mapOut[03]: 00
    };
      struct ddrDimmSetup[02] {
        mapOut[00]: 00
        mapOut[01]: 00
        mapOut[02]: 00
        mapOut[03]: 00
    };
    };
    struct ddrChannelSetup[03] {
      enabled:       01
      batterybacked: 00
      rankMask:      FF
      numDimmSlots:  03
      struct ddrDimmSetup[00] {
        mapOut[00]: 00
        mapOut[01]: 00
        mapOut[02]: 00
        mapOut[03]: 00
    };
      struct ddrDimmSetup[01] {
        mapOut[00]: 00
        mapOut[01]: 00
        mapOut[02]: 00
        mapOut[03]: 00
    };
      struct ddrDimmSetup[02] {
        mapOut[00]: 00
        mapOut[01]: 00
        mapOut[02]: 00
        mapOut[03]: 00
    };
    };
  partialMirrorSize[05] = 0001 [64MB] 
  struct ddrIMCSetup[05] {
    enabled:        00000001
    ddrVddLimit:    00
    struct ddrChannelSetup[00] {
      enabled:       01
      batterybacked: 00
      rankMask:      FF
      numDimmSlots:  03
      struct ddrDimmSetup[00] {
        mapOut[00]: 00
        mapOut[01]: 00
        mapOut[02]: 00
        mapOut[03]: 00
    };
      struct ddrDimmSetup[01] {
        mapOut[00]: 00
        mapOut[01]: 00
        mapOut[02]: 00
        mapOut[03]: 00
    };
      struct ddrDimmSetup[02] {
        mapOut[00]: 00
        mapOut[01]: 00
        mapOut[02]: 00
        mapOut[03]: 00
    };
    };
    struct ddrChannelSetup[01] {
      enabled:       01
      batterybacked: 00
      rankMask:      FF
      numDimmSlots:  03
      struct ddrDimmSetup[00] {
        mapOut[00]: 00
        mapOut[01]: 00
        mapOut[02]: 00
        mapOut[03]: 00
    };
      struct ddrDimmSetup[01] {
        mapOut[00]: 00
        mapOut[01]: 00
        mapOut[02]: 00
        mapOut[03]: 00
    };
      struct ddrDimmSetup[02] {
        mapOut[00]: 00
        mapOut[01]: 00
        mapOut[02]: 00
        mapOut[03]: 00
    };
    };
    struct ddrChannelSetup[02] {
      enabled:       01
      batterybacked: 00
      rankMask:      FF
      numDimmSlots:  03
      struct ddrDimmSetup[00] {
        mapOut[00]: 00
        mapOut[01]: 00
        mapOut[02]: 00
        mapOut[03]: 00
    };
      struct ddrDimmSetup[01] {
        mapOut[00]: 00
        mapOut[01]: 00
        mapOut[02]: 00
        mapOut[03]: 00
    };
      struct ddrDimmSetup[02] {
        mapOut[00]: 00
        mapOut[01]: 00
        mapOut[02]: 00
        mapOut[03]: 00
    };
    };
    struct ddrChannelSetup[03] {
      enabled:       01
      batterybacked: 00
      rankMask:      FF
      numDimmSlots:  03
      struct ddrDimmSetup[00] {
        mapOut[00]: 00
        mapOut[01]: 00
        mapOut[02]: 00
        mapOut[03]: 00
    };
      struct ddrDimmSetup[01] {
        mapOut[00]: 00
        mapOut[01]: 00
        mapOut[02]: 00
        mapOut[03]: 00
    };
      struct ddrDimmSetup[02] {
        mapOut[00]: 00
        mapOut[01]: 00
        mapOut[02]: 00
        mapOut[03]: 00
    };
    };
  };
}; //struct sysHost.setup

CPU Frequency: 0  2500 (MHz)
Set SMBUS Clock Frequency to 6650 for DDR Frequency 1330
N4: Clearing the MRC NVRAM structure.
N4: nvram node enabled = 0x1
N5: nvram node enabled = 0x1
bootMode = NormalBoot. Taking the normal boot path through MRC.
subBootMode = ColdBoot. Taking the cold boot sub-path through MRC.
CPU type is CPU_HSX and stepping is D0_REV_HSX: Apply all HSX D0/E0 WAs
N4: InitMemoryRiser: Stage 0 - Init VPP
N4.C0: InitMemoryRiser: Stage 0 - Init VMSE ERR
N4.C2: InitMemoryRiser: Stage 0 - Init VMSE ERR
N4: InitMemoryRiser: Read Initial SLTCON Data = 0x3C0
N4: InitMemoryRiser: slotCon.Bits.power_controller_control = 0, slotCon.Bits.power_indicator_control = 1
N4: InitMemoryRiser: Write SLTCON Data = 0x1E5
N4: InitMemoryRiser: Initialize hotplug events 
N5.C0: InitMemoryRiser: Stage 0 - Init VMSE ERR
N5.C2: InitMemoryRiser: Stage 0 - Init VMSE ERR
N5: InitMemoryRiser: Read Initial SLTCON Data = 0x3C0
N4: InitMemoryRiser: slotCon.Bits.power_controller_control = 0, slotCon.Bits.power_indicator_control = 1
N5: InitMemoryRiser: Write SLTCON Data = 0x1E5
N5: InitMemoryRiser: Initialize hotplug events 
N4: InitMemoryRiser: vpp enabled set. Skip update. vppMemN1org Data = 0x3
N4: InitMemoryRiser: Stage 1 - Init SLTCon
N4: InitMemoryRiser: Read Initial SLTCON Data = 0x1E5
N5: InitMemoryRiser: Stage 1 - Init SLTCon
N5: InitMemoryRiser: Read Initial SLTCON Data = 0x1E5
N4: InitMemoryRiser: Power Enable Good detection
N4: InitMemoryRiser: Power Enable Good
N5: InitMemoryRiser: Power Enable Good detection
N5: InitMemoryRiser: Power Enable Good
N4: VmseResetViaVpp: Write SLTCON Data = 0x9E5
N4: VmseResetViaVpp: Write SLTCON Data = 0x1E5
N5: VmseResetViaVpp: Write SLTCON Data = 0x9E5
N5: VmseResetViaVpp: Write SLTCON Data = 0x1E5
N2.C0: Jordan Creek Rev ID = 33
N2.C0: Setting Rev ID  = C1_REV
N2.C1: Jordan Creek Rev ID = 33
N2.C1: Setting Rev ID  = C1_REV
SMBUS read fail status = 0xE0000005
RETRY
SMBUS read fail status = 0xE000000B
RETRY
SMBUS read fail status = 0xE0000005
RETRY
SMBUS read fail status = 0xE000000B
RETRY
SMBUS read fail status = 0xE0000005
RETRY
SMBUS read fail status = 0xE000000B
RETRY
SMBUS read fail status = 0xE0000005
RETRY
SMBUS read fail status = 0xE000000B
RETRY

DIMM Detect time            3343 ms
N3: Init Throttling (Early)
N3: Detect DIMM Config
Set SMBUS Clock Frequency to 6650 for DDR Frequency 1330
Dispatch S3 for mem init
N4: Init Throttling (Early)
Skt3 Entering MRC
N4: Detect DIMM Config

sizeof sysHost = 286634

sizeof sysVar = 73483

sizeof memVar = 41569

sizeof cpuVar = 600

sizeof qpi_host_out = 494

sizeof commonVar = 1636

sizeof sysNvram = 208995

sizeof cpuNvram = 20

sizeof memNvram = 1505

sizeof qpiNvram = 56

sizeof commonNvram = 207414

sizeof commonImcNvram = 25925

sizeof nodeIMC = 3856

sizeof ddrChannel = 825

sizeof vmseChannelNvram = 2407

sizeof channelNvram = 5134

sizeof jckddrvar = 32076

sizeof sysHostSetup = 1698

struct sysHost.common {
  options:         00000005
      PROMOTE_WARN_EN         1
      PROMOTE_MRC_WARN_EN     0
      HALT_ON_ERROR_EN        1
  lowGap:          20
  highGap:         01
  serialDebugMsgLvl:0012
  bsdBreakpoint:   00
  maxAddrMem:      40000
  debugPort:       80
  nvramPtr:        00000000
  sysHostBufferPtr:00000000
  mmCfgBase:       80000000
  mmCfgSize:       10000000
  mmiohSize:       00000080
  pchumaEn:        00
  numaEn:          01
  isocEn:          01
  dcaEn:           01
  bdatEn:          00
  consoleComPort:  3F8
  ptrrSupport      01

struct sysHost.setup.mem {
  options:         C990DEA8
      TEMPHIGH_EN              0
      PDWN_IBT_OFF_EN          0
      PDWN_SR_CKE_MODE         0
      OPP_SELF_REF_EN          1
      MDLL_SHUT_DOWN_EN        0
      PAGE_POLICY              1
      ALLOW2XREF_EN            0
      MULTI_THREAD_MRC_EN      1
      ADAPTIVE_PAGE_EN         0
      CMD_CLK_TRAINING_EN      1
      SCRAMBLE_EN              1
      NUMA_AWARE               1
      ECC_CHECK_EN             1
      BALANCED_4WAY_EN         0
      CA_PARITY_EN             1
      SPLIT_BELOW_4GB_EN       0
      MARGIN_RANKS_EN          1
      MEMORY_TEST_FAST_BOOT_EN 1
      ATTEMPT_FAST_BOOT        0
      ZQ_CALIBRATION_EN        1
      PC6_CMD_ADDR_STANDBY_EN  0
      PROC_EIST_EN  1
      LRD_SUBRNK_C2CAS_TIM_EN  1
      DIMM_LRDIMM_3DS_SUPPORT  0
      PROMOTE_MEM_TRAIN_ERRORS 0
      PROMOTE_MEM_RAS_WARNINGS 0
      VMSE_CLOCK_STOP_EN 1
      SAFE_MC_BGF_PSV_EN            1

  options2:         16B003BA
      ADR_SUPPORT_EN                0
      HA_EARLY_WRITE_POST_EN        1
      MC_CHANNEL_HASH_MODE          0
      UNUSED_MEM_CHANNEL_INPUTS_EN  1
      PDA_EN                        0
      READ_VREF_CENTER_EN           1
      WRITE_VREF_CENTER_EN          1
      CMD_2_DATA_TUNING             1
      THERMAL_SENSOR_EN             1
      CATASTROPHIC_TRIP_EN          1
      VUNIT_CLOCK_GATING_EN         0
      TUNIT_CLOCK_GATING_EN         0
      MUNIT_CLOCK_GATING_EN         0
      DUNIT_CLOCK_GATING_EN         0
      CPGC_MEMORY_TEST_EN           0
      CPGC_MEMORY_ECC_EN            1
      OPP_READ_DURING_WMM           0
      PSMI_SUPPORT_EN               0
      JCK_PWR_MGMT_EN               0
      DISPLAY_EYE_EN   0
      ADVANCED_CLK_TRAINING         0
      RXVREF_PERSTROBE_TRAINING     0
      ADVANCED_STROBE_CENTERING     1
      ODT TIMING MODE               1
      EXT_DIMM_VREF_CIRCUIT         0
      BIOS_VMSE_RESET               1
      JCK_SAVE_ERRLOGS              0
      JKT_ERROR_FLOW                0
      VMSE_DISABLE_RCOMP            0
      MXB_RANK_SHARING_MODE         1
      JCK PER DIMM PARITY ERROR EN  0
      DDR4_DIMM_ISOLATION_ENABLE    0

  vmseOptions:         0000E041
      VMSE_MODE_2_1             1
      VMSE_PREAMBLE_2UI         0
      SAFE_TURN_AROUND_TIMINGS  0
      VMSE_RANK_MARGIN_TOOL_EN  0
      VMT Pattern Length (loop count)  00
      VMSE_NB_PERST_EN          0
      VMSE_SB_PERST_EN          1
      RESTORE_VMSE_TRAININGS_ON_FAST_BOOT          0
      VMSE_DATA_SCRAMBLING_EN  1
      VMSE_CMD_SCRAMBLING_EN   1
      VMSE_CMD_SCR_ON_RETRY_EN 1

  RASmodeEx:       06
      DEVTAGGING_EN        0
      Bank SDDC_EN        0
      DMNDSCRB_EN        1
      PTRLSCRB_EN        1
      DDDC_EN            0
      Bank DDDC_EN       0
      A7_MODE            0
      DDDC_WIREKILL      0
      GLOBAL_RAS_POLICY  0

  RASmode:         00
      RK_SPARE             0
      CH_LOCKSTEP          0
      CH_MIRROR            0

struct sysHost.setup.mem {
  VMSE PI Increment:        02
  VMSE VREF Increment:      04
  enforcePOR:      00
  ddrFreqLimit:    00
  nodeInter:       02
  chInter:         04
  rankInter:       08
  dimmTypeSupport: 02
  pdwnCkMode:      00
  MemPwrSave:      01
  ckeThrottling:   01
  olttPeakBWLIMITPercent: 00
  thermalThrottlingOptions:  08
      CLTT_EN             1
      MH_OUTPUT_EN        0
      MH_SENSE_EN         0
  dramraplen:      02
  dramraplbwlimittf: 01
  dramraplRefreshBase: 0A
  dramMaint: 02
  electricalThrottling:  00
  forceRankMult:   00
  lrdimmModuleDelay: 01
  cmdClkEyeWidth:  64
  rmtPatternLength:0F
  patrolScrubDuration:18
  spareErrTh:      0x7FFF
  WirekillRankTh:  0x02
  leakyBktLo:      0x28
  leakyBktHi:      0x29
  scrambleSeedLow: 00000000
  scrambleSeedHigh:00000000
  check_pm_sts:    00
  check_platform_detect: 00
  pushtoCasLatency:        0x16
  phaseShedding:           0x01
  laiMode:                 0x00
  tolm:                    0x01
  mcODTOverride:           0x00
  numSparTrans:            0x0004
  earlyCmdTraining:        0x01
  nbErrTh:             0xFF
  sbErrTh:                 0x1FFF
  vmseLinkFailTh:          0x07
  migrationSpareMask       0x00
  memMirroringMode:        0x00
  memMirorEnableMap:       0x00
      MIRROR_SCRUB     1
  partialMirrorSize[06] = 0001 [64MB] 
  struct ddrIMCSetup[06] {
    enabled:        00000001
    ddrVddLimit:    00
    struct ddrChannelSetup[00] {
      enabled:       01
      batterybacked: 00
      rankMask:      FF
      numDimmSlots:  03
      struct ddrDimmSetup[00] {
        mapOut[00]: 00
        mapOut[01]: 00
        mapOut[02]: 00
        mapOut[03]: 00
    };
      struct ddrDimmSetup[01] {
        mapOut[00]: 00
        mapOut[01]: 00
        mapOut[02]: 00
        mapOut[03]: 00
    };
      struct ddrDimmSetup[02] {
        mapOut[00]: 00
        mapOut[01]: 00
        mapOut[02]: 00
        mapOut[03]: 00
    };
    };
    struct ddrChannelSetup[01] {
      enabled:       01
      batterybacked: 00
      rankMask:      FF
      numDimmSlots:  03
      struct ddrDimmSetup[00] {
        mapOut[00]: 00
        mapOut[01]: 00
        mapOut[02]: 00
        mapOut[03]: 00
    };
      struct ddrDimmSetup[01] {
        mapOut[00]: 00
        mapOut[01]: 00
        mapOut[02]: 00
        mapOut[03]: 00
    };
      struct ddrDimmSetup[02] {
        mapOut[00]: 00
        mapOut[01]: 00
        mapOut[02]: 00
        mapOut[03]: 00
    };
    };
    struct ddrChannelSetup[02] {
      enabled:       01
      batterybacked: 00
      rankMask:      FF
      numDimmSlots:  03
      struct ddrDimmSetup[00] {
        mapOut[00]: 00
        mapOut[01]: 00
        mapOut[02]: 00
        mapOut[03]: 00
    };
      struct ddrDimmSetup[01] {
        mapOut[00]: 00
        mapOut[01]: 00
        mapOut[02]: 00
        mapOut[03]: 00
    };
      struct ddrDimmSetup[02] {
        mapOut[00]: 00
        mapOut[01]: 00
        mapOut[02]: 00
        mapOut[03]: 00
    };
    };
    struct ddrChannelSetup[03] {
      enabled:       01
      batterybacked: 00
      rankMask:      FF
      numDimmSlots:  03
      struct ddrDimmSetup[00] {
        mapOut[00]: 00
        mapOut[01]: 00
        mapOut[02]: 00
        mapOut[03]: 00
    };
      struct ddrDimmSetup[01] {
        mapOut[00]: 00
        mapOut[01]: 00
        mapOut[02]: 00
        mapOut[03]: 00
    };
      struct ddrDimmSetup[02] {
        mapOut[00]: 00
        mapOut[01]: 00
        mapOut[02]: 00
        mapOut[03]: 00
    };
    };
  partialMirrorSize[07] = 0001 [64MB] 
  struct ddrIMCSetup[07] {
    enabled:        00000001
    ddrVddLimit:    00
    struct ddrChannelSetup[00] {
      enabled:       01
      batterybacked: 00
      rankMask:      FF
      numDimmSlots:  03
      struct ddrDimmSetup[00] {
        mapOut[00]: 00
        mapOut[01]: 00
        mapOut[02]: 00
        mapOut[03]: 00
    };
      struct ddrDimmSetup[01] {
        mapOut[00]: 00
        mapOut[01]: 00
        mapOut[02]: 00
        mapOut[03]: 00
    };
      struct ddrDimmSetup[02] {
        mapOut[00]: 00
        mapOut[01]: 00
        mapOut[02]: 00
        mapOut[03]: 00
    };
    };
    struct ddrChannelSetup[01] {
      enabled:       01
      batterybacked: 00
      rankMask:      FF
      numDimmSlots:  03
      struct ddrDimmSetup[00] {
        mapOut[00]: 00
        mapOut[01]: 00
        mapOut[02]: 00
        mapOut[03]: 00
    };
      struct ddrDimmSetup[01] {
        mapOut[00]: 00
        mapOut[01]: 00
        mapOut[02]: 00
        mapOut[03]: 00
    };
      struct ddrDimmSetup[02] {
        mapOut[00]: 00
        mapOut[01]: 00
        mapOut[02]: 00
        mapOut[03]: 00
    };
    };
    struct ddrChannelSetup[02] {
      enabled:       01
      batterybacked: 00
      rankMask:      FF
      numDimmSlots:  03
      struct ddrDimmSetup[00] {
        mapOut[00]: 00
        mapOut[01]: 00
        mapOut[02]: 00
        mapOut[03]: 00
    };
      struct ddrDimmSetup[01] {
        mapOut[00]: 00
        mapOut[01]: 00
        mapOut[02]: 00
        mapOut[03]: 00
    };
      struct ddrDimmSetup[02] {
        mapOut[00]: 00
        mapOut[01]: 00
        mapOut[02]: 00
        mapOut[03]: 00
    };
    };
    struct ddrChannelSetup[03] {
      enabled:       01
      batterybacked: 00
      rankMask:      FF
      numDimmSlots:  03
      struct ddrDimmSetup[00] {
        mapOut[00]: 00
        mapOut[01]: 00
        mapOut[02]: 00
        mapOut[03]: 00
    };
      struct ddrDimmSetup[01] {
        mapOut[00]: 00
        mapOut[01]: 00
        mapOut[02]: 00
        mapOut[03]: 00
    };
      struct ddrDimmSetup[02] {
        mapOut[00]: 00
        mapOut[01]: 00
        mapOut[02]: 00
        mapOut[03]: 00
    };
    };
  };
}; //struct sysHost.setup

CPU Frequency: 0  2500 (MHz)
Set SMBUS Clock Frequency to 6650 for DDR Frequency 1330
N6: Clearing the MRC NVRAM structure.
N6: nvram node enabled = 0x1
N7: nvram node enabled = 0x1
bootMode = NormalBoot. Taking the normal boot path through MRC.
subBootMode = ColdBoot. Taking the cold boot sub-path through MRC.
CPU type is CPU_HSX and stepping is D0_REV_HSX: Apply all HSX D0/E0 WAs
N3.C0: Jordan Creek Rev ID = 33
N6: InitMemoryRiser: Stage 0 - Init VPP
N3.C0: Setting Rev ID  = C1_REV
N6.C0: InitMemoryRiser: Stage 0 - Init VMSE ERR
N6.C2: InitMemoryRiser: Stage 0 - Init VMSE ERR
N3.C1: Jordan Creek Rev ID = 33
N6: InitMemoryRiser: Read Initial SLTCON Data = 0x3C0
N3.C1: Setting Rev ID  = C1_REV
N6: InitMemoryRiser: slotCon.Bits.power_controller_control = 0, slotCon.Bits.power_indicator_control = 1
SMBUS read fail status = 0xE0000001
RETRY
N6: InitMemoryRiser: Write SLTCON Data = 0x1E5
N6: InitMemoryRiser: Initialize hotplug events 
N7.C0: InitMemoryRiser: Stage 0 - Init VMSE ERR
N7.C2: InitMemoryRiser: Stage 0 - Init VMSE ERR
N7: InitMemoryRiser: Read Initial SLTCON Data = 0x3C0
N6: InitMemoryRiser: slotCon.Bits.power_controller_control = 0, slotCon.Bits.power_indicator_control = 1
SMBUS read fail status = 0xE0000003
RETRY
N7: InitMemoryRiser: Write SLTCON Data = 0x1E5
SMBUS read fail status = 0xE0000007
RETRY
N7: InitMemoryRiser: Initialize hotplug events 
N6: InitMemoryRiser: vpp enabled set. Skip update. vppMemN1org Data = 0x3
N6: InitMemoryRiser: Stage 1 - Init SLTCon
N6: InitMemoryRiser: Read Initial SLTCON Data = 0x1E5
N7: InitMemoryRiser: Stage 1 - Init SLTCon
N7: InitMemoryRiser: Read Initial SLTCON Data = 0x1E5
SMBUS read fail status = 0xE000000F
RETRY
SMBUS read fail status = 0xE0000001
RETRY
SMBUS read fail status = 0xE0000003
RETRY
SMBUS read fail status = 0xE0000007
RETRY
SMBUS read fail status = 0xE000000F
RETRY
SMBUS read fail status = 0xE0000001
RETRY
SMBUS read fail status = 0xE0000003
RETRY
SMBUS read fail status = 0xE0000007
RETRY
SMBUS read fail status = 0xE000000F
RETRY
SMBUS read fail status = 0xE0000001
RETRY
SMBUS read fail status = 0xE0000003
RETRY
SMBUS read fail status = 0xE0000007
RETRY
SMBUS read fail status = 0xE000000F
RETRY

DIMM Detect time            2443 ms
Send data from S1 to S0
N6: InitMemoryRiser: Power Enable Good detection
N6: InitMemoryRiser: Power Enable Good
N7: InitMemoryRiser: Power Enable Good detection
N7: InitMemoryRiser: Power Enable Good
N6: VmseResetViaVpp: Write SLTCON Data = 0x9E5
N6: VmseResetViaVpp: Write SLTCON Data = 0x1E5
N7: VmseResetViaVpp: Write SLTCON Data = 0x9E5
N7: VmseResetViaVpp: Write SLTCON Data = 0x1E5
N4.C0: Jordan Creek Rev ID = 33
N4.C0: Setting Rev ID  = C1_REV
N4.C1: Jordan Creek Rev ID = 33
N4.C1: Setting Rev ID  = C1_REV
SMBUS read fail status = 0xE0000005
RETRY
SMBUS read fail status = 0xE000000B
RETRY
SMBUS read fail status = 0xE0000005
RETRY
SMBUS read fail status = 0xE000000B
RETRY
SMBUS read fail status = 0xE0000005
RETRY
SMBUS read fail status = 0xE000000B
RETRY
SMBUS read fail status = 0xE0000005
RETRY
SMBUS read fail status = 0xE000000B
RETRY

DIMM Detect time            3343 ms
N5: Init Throttling (Early)
N5: Detect DIMM Config
Set SMBUS Clock Frequency to 6650 for DDR Frequency 1330
N0: Init Throttling (Early)
N6: Init Throttling (Early)
Checkpoint Code: Socket 0, 0xB0, 0x00, 0x0000
N6: Detect DIMM Config
N0: Detect DIMM Config
Set SMBUS Clock Frequency to 6650 for DDR Frequency 1330
Set SMBUS Clock Frequency to 6650 for DDR Frequency 1330
N5.C0: Jordan Creek Rev ID = 33
N5.C0: Setting Rev ID  = C1_REV
N5.C1: Jordan Creek Rev ID = 33
N5.C1: Setting Rev ID  = C1_REV
SMBUS read fail status = 0xE0000001
RETRY
SMBUS read fail status = 0xE0000003
RETRY
SMBUS read fail status = 0xE0000007
RETRY
SMBUS read fail status = 0xE000000F
RETRY
SMBUS read fail status = 0xE0000001
RETRY
SMBUS read fail status = 0xE0000003
RETRY
SMBUS read fail status = 0xE0000007
RETRY
SMBUS read fail status = 0xE000000F
RETRY
SMBUS read fail status = 0xE0000001
RETRY
SMBUS read fail status = 0xE0000003
RETRY
SMBUS read fail status = 0xE0000007
RETRY
SMBUS read fail status = 0xE000000F
RETRY
SMBUS read fail status = 0xE0000001
RETRY
SMBUS read fail status = 0xE0000003
RETRY
SMBUS read fail status = 0xE0000007
RETRY
SMBUS read fail status = 0xE000000F
RETRY

DIMM Detect time            2412 ms
Send data from S2 to S0
N6.C0: Jordan Creek Rev ID = 33
N6.C0: Setting Rev ID  = C1_REV
N0.C0: Jordan Creek Rev ID = 33
N0.C0: Setting Rev ID  = C1_REV
N6.C1: Jordan Creek Rev ID = 33
N6.C1: Setting Rev ID  = C1_REV
N0.C1: Jordan Creek Rev ID = 33
N0.C1: Setting Rev ID  = C1_REV
SMBUS read fail status = 0xE0000005
RETRY
SMBUS read fail status = 0xE0000005
RETRY
SMBUS read fail status = 0xE000000B
RETRY
SMBUS read fail status = 0xE000000B
RETRY
SMBUS read fail status = 0xE0000005
RETRY
SMBUS read fail status = 0xE0000005
RETRY
SMBUS read fail status = 0xE000000B
RETRY
SMBUS read fail status = 0xE000000B
RETRY
SMBUS read fail status = 0xE0000005
RETRY
SMBUS read fail status = 0xE0000005
RETRY
SMBUS read fail status = 0xE000000B
RETRY
SMBUS read fail status = 0xE000000B
RETRY
SMBUS read fail status = 0xE0000005
RETRY
SMBUS read fail status = 0xE0000005
RETRY
SMBUS read fail status = 0xE000000B
RETRY

DIMM Detect time            2260 ms
SMBUS read fail status = 0xE000000B
RETRY
N7: Init Throttling (Early)

DIMM Detect time            2266 ms
N7: Detect DIMM Config
N1: Init Throttling (Early)
Set SMBUS Clock Frequency to 6650 for DDR Frequency 1330
Checkpoint Code: Socket 0, 0xB0, 0x00, 0x0000
N1: Detect DIMM Config
Set SMBUS Clock Frequency to 6650 for DDR Frequency 1330
N7.C0: Jordan Creek Rev ID = 33
N7.C0: Setting Rev ID  = C1_REV
N1.C0: Jordan Creek Rev ID = 33
N7.C1: Jordan Creek Rev ID = 33
N1.C0: Setting Rev ID  = C1_REV
N7.C1: Setting Rev ID  = C1_REV
SMBUS read fail status = 0xE0000001
RETRY
N1.C1: Jordan Creek Rev ID = 33
N1.C1: Setting Rev ID  = C1_REV
SMBUS read fail status = 0xE0000001
RETRY
SMBUS read fail status = 0xE0000003
RETRY
SMBUS read fail status = 0xE0000007
RETRY
SMBUS read fail status = 0xE0000003
RETRY
SMBUS read fail status = 0xE0000007
RETRY
SMBUS read fail status = 0xE000000F
RETRY
SMBUS read fail status = 0xE0000001
RETRY
SMBUS read fail status = 0xE000000F
RETRY
SMBUS read fail status = 0xE0000001
RETRY
SMBUS read fail status = 0xE0000003
RETRY
SMBUS read fail status = 0xE0000007
RETRY
SMBUS read fail status = 0xE0000003
RETRY
SMBUS read fail status = 0xE0000007
RETRY
SMBUS read fail status = 0xE000000F
RETRY
SMBUS read fail status = 0xE0000001
RETRY
SMBUS read fail status = 0xE000000F
RETRY
SMBUS read fail status = 0xE0000001
RETRY
SMBUS read fail status = 0xE0000003
RETRY
SMBUS read fail status = 0xE0000007
RETRY
SMBUS read fail status = 0xE0000003
RETRY
SMBUS read fail status = 0xE0000007
RETRY
SMBUS read fail status = 0xE000000F
RETRY
SMBUS read fail status = 0xE0000001
RETRY
SMBUS read fail status = 0xE000000F
RETRY
SMBUS read fail status = 0xE0000001
RETRY
SMBUS read fail status = 0xE0000003
RETRY
SMBUS read fail status = 0xE0000007
RETRY
SMBUS read fail status = 0xE0000003
RETRY
SMBUS read fail status = 0xE0000007
RETRY
SMBUS read fail status = 0xE000000F
RETRY

DIMM Detect time            2419 ms
Send data from S3 to S0
SMBUS read fail status = 0xE000000F
RETRY

DIMM Detect time            2419 ms
Get Var data from S1 to S0
Get NVRAM data from S1 to S0
Get Var data from S2 to S0
Get NVRAM data from S2 to S0
Get Var data from S3 to S0
Get NVRAM data from S3 to S0
Node   | Channel | DIMM |  Bus Segment | SMBUS Address
-------|---------|------|--------------|--------------
   0   |    0    |   0  |      0       |       0      - Present
   0   |    0    |   1  |      0       |       1      - Present
   0   |    0    |   2  |      0       |       2      - Not Present
   0   |    1    |   0  |      0       |       4      - Present
   0   |    1    |   1  |      0       |       5      - Present
   0   |    1    |   2  |      0       |       6      - Not Present
   0   |    2    |   0  |      1       |       0      - Present
   0   |    2    |   1  |      1       |       1      - Present
   0   |    2    |   2  |      1       |       2      - Not Present
   0   |    3    |   0  |      1       |       4      - Present
   0   |    3    |   1  |      1       |       5      - Present
   0   |    3    |   2  |      1       |       6      - Not Present
Node   | Channel | DIMM |  Bus Segment | SMBUS Address
-------|---------|------|--------------|--------------
   1   |    0    |   0  |      0       |       0      - Present
   1   |    0    |   1  |      0       |       1      - Not Present
   1   |    0    |   2  |      0       |       2      - Not Present
   1   |    1    |   0  |      0       |       4      - Present
   1   |    1    |   1  |      0       |       5      - Not Present
   1   |    1    |   2  |      0       |       6      - Not Present
   1   |    2    |   0  |      1       |       0      - Present
   1   |    2    |   1  |      1       |       1      - Not Present
   1   |    2    |   2  |      1       |       2      - Not Present
   1   |    3    |   0  |      1       |       4      - Present
   1   |    3    |   1  |      1       |       5      - Not Present
   1   |    3    |   2  |      1       |       6      - Not Present
Node   | Channel | DIMM |  Bus Segment | SMBUS Address
-------|---------|------|--------------|--------------
   2   |    0    |   0  |      0       |       0      - Present
   2   |    0    |   1  |      0       |       1      - Present
   2   |    0    |   2  |      0       |       2      - Not Present
   2   |    1    |   0  |      0       |       4      - Present
   2   |    1    |   1  |      0       |       5      - Present
   2   |    1    |   2  |      0       |       6      - Not Present
   2   |    2    |   0  |      1       |       0      - Present
   2   |    2    |   1  |      1       |       1      - Present
   2   |    2    |   2  |      1       |       2      - Not Present
   2   |    3    |   0  |      1       |       4      - Present
   2   |    3    |   1  |      1       |       5      - Present
   2   |    3    |   2  |      1       |       6      - Not Present
Node   | Channel | DIMM |  Bus Segment | SMBUS Address
-------|---------|------|--------------|--------------
   3   |    0    |   0  |      0       |       0      - Present
   3   |    0    |   1  |      0       |       1      - Not Present
   3   |    0    |   2  |      0       |       2      - Not Present
   3   |    1    |   0  |      0       |       4      - Present
   3   |    1    |   1  |      0       |       5      - Not Present
   3   |    1    |   2  |      0       |       6      - Not Present
   3   |    2    |   0  |      1       |       0      - Present
   3   |    2    |   1  |      1       |       1      - Not Present
   3   |    2    |   2  |      1       |       2      - Not Present
   3   |    3    |   0  |      1       |       4      - Present
   3   |    3    |   1  |      1       |       5      - Not Present
   3   |    3    |   2  |      1       |       6      - Not Present
Node   | Channel | DIMM |  Bus Segment | SMBUS Address
-------|---------|------|--------------|--------------
   4   |    0    |   0  |      0       |       0      - Present
   4   |    0    |   1  |      0       |       1      - Present
   4   |    0    |   2  |      0       |       2      - Not Present
   4   |    1    |   0  |      0       |       4      - Present
   4   |    1    |   1  |      0       |       5      - Present
   4   |    1    |   2  |      0       |       6      - Not Present
   4   |    2    |   0  |      1       |       0      - Present
   4   |    2    |   1  |      1       |       1      - Present
   4   |    2    |   2  |      1       |       2      - Not Present
   4   |    3    |   0  |      1       |       4      - Present
   4   |    3    |   1  |      1       |       5      - Present
   4   |    3    |   2  |      1       |       6      - Not Present
Node   | Channel | DIMM |  Bus Segment | SMBUS Address
-------|---------|------|--------------|--------------
   5   |    0    |   0  |      0       |       0      - Present
   5   |    0    |   1  |      0       |       1      - Not Present
   5   |    0    |   2  |      0       |       2      - Not Present
   5   |    1    |   0  |      0       |       4      - Present
   5   |    1    |   1  |      0       |       5      - Not Present
   5   |    1    |   2  |      0       |       6      - Not Present
   5   |    2    |   0  |      1       |       0      - Present
   5   |    2    |   1  |      1       |       1      - Not Present
   5   |    2    |   2  |      1       |       2      - Not Present
   5   |    3    |   0  |      1       |       4      - Present
   5   |    3    |   1  |      1       |       5      - Not Present
   5   |    3    |   2  |      1       |       6      - Not Present
Node   | Channel | DIMM |  Bus Segment | SMBUS Address
-------|---------|------|--------------|--------------
   6   |    0    |   0  |      0       |       0      - Present
   6   |    0    |   1  |      0       |       1      - Present
   6   |    0    |   2  |      0       |       2      - Not Present
   6   |    1    |   0  |      0       |       4      - Present
   6   |    1    |   1  |      0       |       5      - Present
   6   |    1    |   2  |      0       |       6      - Not Present
   6   |    2    |   0  |      1       |       0      - Present
   6   |    2    |   1  |      1       |       1      - Present
   6   |    2    |   2  |      1       |       2      - Not Present
   6   |    3    |   0  |      1       |       4      - Present
   6   |    3    |   1  |      1       |       5      - Present
   6   |    3    |   2  |      1       |       6      - Not Present
Node   | Channel | DIMM |  Bus Segment | SMBUS Address
-------|---------|------|--------------|--------------
   7   |    0    |   0  |      0       |       0      - Present
   7   |    0    |   1  |      0       |       1      - Not Present
   7   |    0    |   2  |      0       |       2      - Not Present
   7   |    1    |   0  |      0       |       4      - Present
   7   |    1    |   1  |      0       |       5      - Not Present
   7   |    1    |   2  |      0       |       6      - Not Present
   7   |    2    |   0  |      1       |       0      - Present
   7   |    2    |   1  |      1       |       1      - Not Present
   7   |    2    |   2  |      1       |       2      - Not Present
   7   |    3    |   0  |      1       |       4      - Present
   7   |    3    |   1  |      1       |       5      - Not Present
   7   |    3    |   2  |      1       |       6      - Not Present
N0.C0.D0: techIndex = 4. Num Ranks = 2
N0.C0.D1: techIndex = 4. Num Ranks = 2
N0.C1.D0: techIndex = 4. Num Ranks = 2
N0.C1.D1: techIndex = 4. Num Ranks = 2
N0.C2.D0: techIndex = 4. Num Ranks = 2
N0.C2.D1: techIndex = 4. Num Ranks = 2
N0.C3.D0: techIndex = 4. Num Ranks = 2
N0.C3.D1: techIndex = 4. Num Ranks = 2
N1.C0.D0: techIndex = 6. Num Ranks = 2
N1.C1.D0: techIndex = 6. Num Ranks = 2
N1.C2.D0: techIndex = 6. Num Ranks = 2
N1.C3.D0: techIndex = 6. Num Ranks = 2
N2.C0.D0: techIndex = 4. Num Ranks = 2
N2.C0.D1: techIndex = 4. Num Ranks = 2
N2.C1.D0: techIndex = 4. Num Ranks = 2
N2.C1.D1: techIndex = 4. Num Ranks = 2
N2.C2.D0: techIndex = 4. Num Ranks = 2
N2.C2.D1: techIndex = 4. Num Ranks = 2
N2.C3.D0: techIndex = 4. Num Ranks = 2
N2.C3.D1: techIndex = 4. Num Ranks = 2
N3.C0.D0: techIndex = 6. Num Ranks = 2
N3.C1.D0: techIndex = 6. Num Ranks = 2
N3.C2.D0: techIndex = 6. Num Ranks = 2
N3.C3.D0: techIndex = 6. Num Ranks = 2
N4.C0.D0: techIndex = 4. Num Ranks = 2
N4.C0.D1: techIndex = 4. Num Ranks = 2
N4.C1.D0: techIndex = 4. Num Ranks = 2
N4.C1.D1: techIndex = 4. Num Ranks = 2
N4.C2.D0: techIndex = 4. Num Ranks = 2
N4.C2.D1: techIndex = 4. Num Ranks = 2
N4.C3.D0: techIndex = 4. Num Ranks = 2
N4.C3.D1: techIndex = 4. Num Ranks = 2
N5.C0.D0: techIndex = 6. Num Ranks = 2
N5.C1.D0: techIndex = 6. Num Ranks = 2
N5.C2.D0: techIndex = 6. Num Ranks = 2
N5.C3.D0: techIndex = 6. Num Ranks = 2
N6.C0.D0: techIndex = 4. Num Ranks = 2
N6.C0.D1: techIndex = 4. Num Ranks = 2
N6.C1.D0: techIndex = 4. Num Ranks = 2
N6.C1.D1: techIndex = 4. Num Ranks = 2
N6.C2.D0: techIndex = 4. Num Ranks = 2
N6.C2.D1: techIndex = 4. Num Ranks = 2
N6.C3.D0: techIndex = 4. Num Ranks = 2
N6.C3.D1: techIndex = 4. Num Ranks = 2
N7.C0.D0: techIndex = 6. Num Ranks = 2
N7.C1.D0: techIndex = 6. Num Ranks = 2
N7.C2.D0: techIndex = 6. Num Ranks = 2
N7.C3.D0: techIndex = 6. Num Ranks = 2
N8: RDIMM DDR3 population
Checkpoint Code: Socket 0, 0xB2, 0x00, 0x0000
Check Dimm Ranks
Check DIMM population
N0.C0.D0: Number of ranks = 2
N0.C0.D1: Number of ranks = 2
N0.C0.D0.R0: ENABLED
N0.C0.D0.R1: ENABLED
N0.C0.D1.R0: ENABLED
N0.C0.D1.R1: ENABLED
N0.C0: TermRnkMsk = 0x2000011
N0.C1.D0: Number of ranks = 2
N0.C1.D1: Number of ranks = 2
N0.C1.D0.R0: ENABLED
N0.C1.D0.R1: ENABLED
N0.C1.D1.R0: ENABLED
N0.C1.D1.R1: ENABLED
N0.C1: TermRnkMsk = 0x2000011
N0.C2.D0: Number of ranks = 2
N0.C2.D1: Number of ranks = 2
N0.C2.D0.R0: ENABLED
N0.C2.D0.R1: ENABLED
N0.C2.D1.R0: ENABLED
N0.C2.D1.R1: ENABLED
N0.C2: TermRnkMsk = 0x2000011
N0.C3.D0: Number of ranks = 2
N0.C3.D1: Number of ranks = 2
N0.C3.D0.R0: ENABLED
N0.C3.D0.R1: ENABLED
N0.C3.D1.R0: ENABLED
N0.C3.D1.R1: ENABLED
N0.C3: TermRnkMsk = 0x2000011
N1.C0.D0: Number of ranks = 2
N1.C0.D0.R0: ENABLED
N1.C0.D0.R1: ENABLED
N1.C0: TermRnkMsk = 0x2000001
N1.C1.D0: Number of ranks = 2
N1.C1.D0.R0: ENABLED
N1.C1.D0.R1: ENABLED
N1.C1: TermRnkMsk = 0x2000001
N1.C2.D0: Number of ranks = 2
N1.C2.D0.R0: ENABLED
N1.C2.D0.R1: ENABLED
N1.C2: TermRnkMsk = 0x2000001
N1.C3.D0: Number of ranks = 2
N1.C3.D0.R0: ENABLED
N1.C3.D0.R1: ENABLED
N1.C3: TermRnkMsk = 0x2000001
N2.C0.D0: Number of ranks = 2
N2.C0.D1: Number of ranks = 2
N2.C0.D0.R0: ENABLED
N2.C0.D0.R1: ENABLED
N2.C0.D1.R0: ENABLED
N2.C0.D1.R1: ENABLED
N2.C0: TermRnkMsk = 0x2000011
N2.C1.D0: Number of ranks = 2
N2.C1.D1: Number of ranks = 2
N2.C1.D0.R0: ENABLED
N2.C1.D0.R1: ENABLED
N2.C1.D1.R0: ENABLED
N2.C1.D1.R1: ENABLED
N2.C1: TermRnkMsk = 0x2000011
N2.C2.D0: Number of ranks = 2
N2.C2.D1: Number of ranks = 2
N2.C2.D0.R0: ENABLED
N2.C2.D0.R1: ENABLED
N2.C2.D1.R0: ENABLED
N2.C2.D1.R1: ENABLED
N2.C2: TermRnkMsk = 0x2000011
N2.C3.D0: Number of ranks = 2
N2.C3.D1: Number of ranks = 2
N2.C3.D0.R0: ENABLED
N2.C3.D0.R1: ENABLED
N2.C3.D1.R0: ENABLED
N2.C3.D1.R1: ENABLED
N2.C3: TermRnkMsk = 0x2000011
N3.C0.D0: Number of ranks = 2
N3.C0.D0.R0: ENABLED
N3.C0.D0.R1: ENABLED
N3.C0: TermRnkMsk = 0x2000001
N3.C1.D0: Number of ranks = 2
N3.C1.D0.R0: ENABLED
N3.C1.D0.R1: ENABLED
N3.C1: TermRnkMsk = 0x2000001
N3.C2.D0: Number of ranks = 2
N3.C2.D0.R0: ENABLED
N3.C2.D0.R1: ENABLED
N3.C2: TermRnkMsk = 0x2000001
N3.C3.D0: Number of ranks = 2
N3.C3.D0.R0: ENABLED
N3.C3.D0.R1: ENABLED
N3.C3: TermRnkMsk = 0x2000001
N4.C0.D0: Number of ranks = 2
N4.C0.D1: Number of ranks = 2
N4.C0.D0.R0: ENABLED
N4.C0.D0.R1: ENABLED
N4.C0.D1.R0: ENABLED
N4.C0.D1.R1: ENABLED
N4.C0: TermRnkMsk = 0x2000011
N4.C1.D0: Number of ranks = 2
N4.C1.D1: Number of ranks = 2
N4.C1.D0.R0: ENABLED
N4.C1.D0.R1: ENABLED
N4.C1.D1.R0: ENABLED
N4.C1.D1.R1: ENABLED
N4.C1: TermRnkMsk = 0x2000011
N4.C2.D0: Number of ranks = 2
N4.C2.D1: Number of ranks = 2
N4.C2.D0.R0: ENABLED
N4.C2.D0.R1: ENABLED
N4.C2.D1.R0: ENABLED
N4.C2.D1.R1: ENABLED
N4.C2: TermRnkMsk = 0x2000011
N4.C3.D0: Number of ranks = 2
N4.C3.D1: Number of ranks = 2
N4.C3.D0.R0: ENABLED
N4.C3.D0.R1: ENABLED
N4.C3.D1.R0: ENABLED
N4.C3.D1.R1: ENABLED
N4.C3: TermRnkMsk = 0x2000011
N5.C0.D0: Number of ranks = 2
N5.C0.D0.R0: ENABLED
N5.C0.D0.R1: ENABLED
N5.C0: TermRnkMsk = 0x2000001
N5.C1.D0: Number of ranks = 2
N5.C1.D0.R0: ENABLED
N5.C1.D0.R1: ENABLED
N5.C1: TermRnkMsk = 0x2000001
N5.C2.D0: Number of ranks = 2
N5.C2.D0.R0: ENABLED
N5.C2.D0.R1: ENABLED
N5.C2: TermRnkMsk = 0x2000001
N5.C3.D0: Number of ranks = 2
N5.C3.D0.R0: ENABLED
N5.C3.D0.R1: ENABLED
N5.C3: TermRnkMsk = 0x2000001
N6.C0.D0: Number of ranks = 2
N6.C0.D1: Number of ranks = 2
N6.C0.D0.R0: ENABLED
N6.C0.D0.R1: ENABLED
N6.C0.D1.R0: ENABLED
N6.C0.D1.R1: ENABLED
N6.C0: TermRnkMsk = 0x2000011
N6.C1.D0: Number of ranks = 2
N6.C1.D1: Number of ranks = 2
N6.C1.D0.R0: ENABLED
N6.C1.D0.R1: ENABLED
N6.C1.D1.R0: ENABLED
N6.C1.D1.R1: ENABLED
N6.C1: TermRnkMsk = 0x2000011
N6.C2.D0: Number of ranks = 2
N6.C2.D1: Number of ranks = 2
N6.C2.D0.R0: ENABLED
N6.C2.D0.R1: ENABLED
N6.C2.D1.R0: ENABLED
N6.C2.D1.R1: ENABLED
N6.C2: TermRnkMsk = 0x2000011
N6.C3.D0: Number of ranks = 2
N6.C3.D1: Number of ranks = 2
N6.C3.D0.R0: ENABLED
N6.C3.D0.R1: ENABLED
N6.C3.D1.R0: ENABLED
N6.C3.D1.R1: ENABLED
N6.C3: TermRnkMsk = 0x2000011
N7.C0.D0: Number of ranks = 2
N7.C0.D0.R0: ENABLED
N7.C0.D0.R1: ENABLED
N7.C0: TermRnkMsk = 0x2000001
N7.C1.D0: Number of ranks = 2
N7.C1.D0.R0: ENABLED
N7.C1.D0.R1: ENABLED
N7.C1: TermRnkMsk = 0x2000001
N7.C2.D0: Number of ranks = 2
N7.C2.D0.R0: ENABLED
N7.C2.D0.R1: ENABLED
N7.C2: TermRnkMsk = 0x2000001
N7.C3.D0: Number of ranks = 2
N7.C3.D0.R0: ENABLED
N7.C3.D0.R1: ENABLED
N7.C3: TermRnkMsk = 0x2000001
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CheckDimmRanks time            973 ms
Checkpoint Code: Socket 0, 0xB3, 0x00, 0x0000
Capid2.Bits.qpi_allowed_cfclk_ratio_dis = 9 
Capid2.Bits.qpi_allowed_cfclk_ratio_dis = 9 
Capid2.Bits.qpi_allowed_cfclk_ratio_dis = 9 
Capid2.Bits.qpi_allowed_cfclk_ratio_dis = 9 
Capid2.Bits.qpi_allowed_cfclk_ratio_dis = 9 
Capid2.Bits.qpi_allowed_cfclk_ratio_dis = 9 
Capid2.Bits.qpi_allowed_cfclk_ratio_dis = 9 
Capid2.Bits.qpi_allowed_cfclk_ratio_dis = 9 
DDR Freq Limit = 3
Init DDR Clocks
N0.C0: POR Vdd LUT Index = 42
N0.C0: POR Vdd LUT Index = 43
N0.C0: Checks if the requested Vdd 0x02 is supported - SUCCESS
N0.C1: POR Vdd LUT Index = 42
N0.C1: POR Vdd LUT Index = 43
N0.C1: Checks if the requested Vdd 0x02 is supported - SUCCESS
N0.C2: POR Vdd LUT Index = 42
N0.C2: POR Vdd LUT Index = 43
N0.C2: Checks if the requested Vdd 0x02 is supported - SUCCESS
N0.C3: POR Vdd LUT Index = 42
N0.C3: POR Vdd LUT Index = 43
N0.C3: Checks if the requested Vdd 0x02 is supported - SUCCESS
N2.C0: POR Vdd LUT Index = 42
N2.C0: POR Vdd LUT Index = 43
N2.C0: Checks if the requested Vdd 0x02 is supported - SUCCESS
N2.C1: POR Vdd LUT Index = 42
N2.C1: POR Vdd LUT Index = 43
N2.C1: Checks if the requested Vdd 0x02 is supported - SUCCESS
N2.C2: POR Vdd LUT Index = 42
N2.C2: POR Vdd LUT Index = 43
N2.C2: Checks if the requested Vdd 0x02 is supported - SUCCESS
N2.C3: POR Vdd LUT Index = 42
N2.C3: POR Vdd LUT Index = 43
N2.C3: Checks if the requested Vdd 0x02 is supported - SUCCESS
N4.C0: POR Vdd LUT Index = 42
N4.C0: POR Vdd LUT Index = 43
N4.C0: Checks if the requested Vdd 0x02 is supported - SUCCESS
N4.C1: POR Vdd LUT Index = 42
N4.C1: POR Vdd LUT Index = 43
N4.C1: Checks if the requested Vdd 0x02 is supported - SUCCESS
N4.C2: POR Vdd LUT Index = 42
N4.C2: POR Vdd LUT Index = 43
N4.C2: Checks if the requested Vdd 0x02 is supported - SUCCESS
N4.C3: POR Vdd LUT Index = 42
N4.C3: POR Vdd LUT Index = 43
N4.C3: Checks if the requested Vdd 0x02 is supported - SUCCESS
N6.C0: POR Vdd LUT Index = 42
N6.C0: POR Vdd LUT Index = 43
N6.C0: Checks if the requested Vdd 0x02 is supported - SUCCESS
N6.C1: POR Vdd LUT Index = 42
N6.C1: POR Vdd LUT Index = 43
N6.C1: Checks if the requested Vdd 0x02 is supported - SUCCESS
N6.C2: POR Vdd LUT Index = 42
N6.C2: POR Vdd LUT Index = 43
N6.C2: Checks if the requested Vdd 0x02 is supported - SUCCESS
N6.C3: POR Vdd LUT Index = 42
N6.C3: POR Vdd LUT Index = 43
N6.C3: Checks if the requested Vdd 0x02 is supported - SUCCESS
N0: commonTck = 10, ddrFreq set to 3
N0.C0: Common Dram Vdd = 0
N0.C0: GetPORDDRFreq found freqTable LUT index 42. ddrFreq = 2
N0.C0: GetPORDDRFreq = 2
N0.C0: SPD Dimm Freq = 3 vs POR Freq = 2
N0.C0: Freq Override = 2
N0.C1: Common Dram Vdd = 0
N0.C1: GetPORDDRFreq found freqTable LUT index 42. ddrFreq = 2
N0.C1: GetPORDDRFreq = 2
N0.C1: SPD Dimm Freq = 2 vs POR Freq = 2
N0.C1: Freq Override = 2
N0.C2: Common Dram Vdd = 0
N0.C2: GetPORDDRFreq found freqTable LUT index 42. ddrFreq = 2
N0.C2: GetPORDDRFreq = 2
N0.C2: SPD Dimm Freq = 2 vs POR Freq = 2
N0.C2: Freq Override = 2
N0.C3: Common Dram Vdd = 0
N0.C3: GetPORDDRFreq found freqTable LUT index 42. ddrFreq = 2
N0.C3: GetPORDDRFreq = 2
N0.C3: SPD Dimm Freq = 2 vs POR Freq = 2
N0.C3: Freq Override = 2
N0: For JCK1 enforce MaxDdrFreq to be 1333MT/s. The 1600MT/s is not supported for vmse_2xfc 0 in 2:1 mode
N1: commonTck = 10, ddrFreq set to 3
N1.C0: Common Dram Vdd = 0
N1.C0: GetPORDDRFreq found freqTable LUT index 38. ddrFreq = 2
N1.C0: GetPORDDRFreq = 2
N1.C0: SPD Dimm Freq = 3 vs POR Freq = 2
N1.C0: Freq Override = 2
N1.C1: Common Dram Vdd = 0
N1.C1: GetPORDDRFreq found freqTable LUT index 38. ddrFreq = 2
N1.C1: GetPORDDRFreq = 2
N1.C1: SPD Dimm Freq = 2 vs POR Freq = 2
N1.C1: Freq Override = 2
N1.C2: Common Dram Vdd = 0
N1.C2: GetPORDDRFreq found freqTable LUT index 38. ddrFreq = 2
N1.C2: GetPORDDRFreq = 2
N1.C2: SPD Dimm Freq = 2 vs POR Freq = 2
N1.C2: Freq Override = 2
N1.C3: Common Dram Vdd = 0
N1.C3: GetPORDDRFreq found freqTable LUT index 38. ddrFreq = 2
N1.C3: GetPORDDRFreq = 2
N1.C3: SPD Dimm Freq = 2 vs POR Freq = 2
N1.C3: Freq Override = 2
N1: For JCK1 enforce MaxDdrFreq to be 1333MT/s. The 1600MT/s is not supported for vmse_2xfc 0 in 2:1 mode
N2: commonTck = 12, ddrFreq set to 2
N2.C0: Common Dram Vdd = 0
N2.C0: GetPORDDRFreq found freqTable LUT index 42. ddrFreq = 2
N2.C0: GetPORDDRFreq = 2
N2.C0: SPD Dimm Freq = 2 vs POR Freq = 2
N2.C0: Freq Override = 2
N2.C1: Common Dram Vdd = 0
N2.C1: GetPORDDRFreq found freqTable LUT index 42. ddrFreq = 2
N2.C1: GetPORDDRFreq = 2
N2.C1: SPD Dimm Freq = 2 vs POR Freq = 2
N2.C1: Freq Override = 2
N2.C2: Common Dram Vdd = 0
N2.C2: GetPORDDRFreq found freqTable LUT index 42. ddrFreq = 2
N2.C2: GetPORDDRFreq = 2
N2.C2: SPD Dimm Freq = 2 vs POR Freq = 2
N2.C2: Freq Override = 2
N2.C3: Common Dram Vdd = 0
N2.C3: GetPORDDRFreq found freqTable LUT index 42. ddrFreq = 2
N2.C3: GetPORDDRFreq = 2
N2.C3: SPD Dimm Freq = 2 vs POR Freq = 2
N2.C3: Freq Override = 2
N2: For JCK1 enforce MaxDdrFreq to be 1333MT/s. The 1600MT/s is not supported for vmse_2xfc 0 in 2:1 mode
N3: commonTck = 10, ddrFreq set to 3
N3.C0: Common Dram Vdd = 0
N3.C0: GetPORDDRFreq found freqTable LUT index 38. ddrFreq = 2
N3.C0: GetPORDDRFreq = 2
N3.C0: SPD Dimm Freq = 3 vs POR Freq = 2
N3.C0: Freq Override = 2
N3.C1: Common Dram Vdd = 0
N3.C1: GetPORDDRFreq found freqTable LUT index 38. ddrFreq = 2
N3.C1: GetPORDDRFreq = 2
N3.C1: SPD Dimm Freq = 2 vs POR Freq = 2
N3.C1: Freq Override = 2
N3.C2: Common Dram Vdd = 0
N3.C2: GetPORDDRFreq found freqTable LUT index 38. ddrFreq = 2
N3.C2: GetPORDDRFreq = 2
N3.C2: SPD Dimm Freq = 2 vs POR Freq = 2
N3.C2: Freq Override = 2
N3.C3: Common Dram Vdd = 0
N3.C3: GetPORDDRFreq found freqTable LUT index 38. ddrFreq = 2
N3.C3: GetPORDDRFreq = 2
N3.C3: SPD Dimm Freq = 2 vs POR Freq = 2
N3.C3: Freq Override = 2
N3: For JCK1 enforce MaxDdrFreq to be 1333MT/s. The 1600MT/s is not supported for vmse_2xfc 0 in 2:1 mode
N4: commonTck = 10, ddrFreq set to 3
N4.C0: Common Dram Vdd = 0
N4.C0: GetPORDDRFreq found freqTable LUT index 42. ddrFreq = 2
N4.C0: GetPORDDRFreq = 2
N4.C0: SPD Dimm Freq = 3 vs POR Freq = 2
N4.C0: Freq Override = 2
N4.C1: Common Dram Vdd = 0
N4.C1: GetPORDDRFreq found freqTable LUT index 42. ddrFreq = 2
N4.C1: GetPORDDRFreq = 2
N4.C1: SPD Dimm Freq = 2 vs POR Freq = 2
N4.C1: Freq Override = 2
N4.C2: Common Dram Vdd = 0
N4.C2: GetPORDDRFreq found freqTable LUT index 42. ddrFreq = 2
N4.C2: GetPORDDRFreq = 2
N4.C2: SPD Dimm Freq = 2 vs POR Freq = 2
N4.C2: Freq Override = 2
N4.C3: Common Dram Vdd = 0
N4.C3: GetPORDDRFreq found freqTable LUT index 42. ddrFreq = 2
N4.C3: GetPORDDRFreq = 2
N4.C3: SPD Dimm Freq = 2 vs POR Freq = 2
N4.C3: Freq Override = 2
N4: For JCK1 enforce MaxDdrFreq to be 1333MT/s. The 1600MT/s is not supported for vmse_2xfc 0 in 2:1 mode
N5: commonTck = 10, ddrFreq set to 3
N5.C0: Common Dram Vdd = 0
N5.C0: GetPORDDRFreq found freqTable LUT index 38. ddrFreq = 2
N5.C0: GetPORDDRFreq = 2
N5.C0: SPD Dimm Freq = 3 vs POR Freq = 2
N5.C0: Freq Override = 2
N5.C1: Common Dram Vdd = 0
N5.C1: GetPORDDRFreq found freqTable LUT index 38. ddrFreq = 2
N5.C1: GetPORDDRFreq = 2
N5.C1: SPD Dimm Freq = 2 vs POR Freq = 2
N5.C1: Freq Override = 2
N5.C2: Common Dram Vdd = 0
N5.C2: GetPORDDRFreq found freqTable LUT index 38. ddrFreq = 2
N5.C2: GetPORDDRFreq = 2
N5.C2: SPD Dimm Freq = 2 vs POR Freq = 2
N5.C2: Freq Override = 2
N5.C3: Common Dram Vdd = 0
N5.C3: GetPORDDRFreq found freqTable LUT index 38. ddrFreq = 2
N5.C3: GetPORDDRFreq = 2
N5.C3: SPD Dimm Freq = 2 vs POR Freq = 2
N5.C3: Freq Override = 2
N5: For JCK1 enforce MaxDdrFreq to be 1333MT/s. The 1600MT/s is not supported for vmse_2xfc 0 in 2:1 mode
N6: commonTck = 12, ddrFreq set to 2
N6.C0: Common Dram Vdd = 0
N6.C0: GetPORDDRFreq found freqTable LUT index 42. ddrFreq = 2
N6.C0: GetPORDDRFreq = 2
N6.C0: SPD Dimm Freq = 2 vs POR Freq = 2
N6.C0: Freq Override = 2
N6.C1: Common Dram Vdd = 0
N6.C1: GetPORDDRFreq found freqTable LUT index 42. ddrFreq = 2
N6.C1: GetPORDDRFreq = 2
N6.C1: SPD Dimm Freq = 2 vs POR Freq = 2
N6.C1: Freq Override = 2
N6.C2: Common Dram Vdd = 0
N6.C2: GetPORDDRFreq found freqTable LUT index 42. ddrFreq = 2
N6.C2: GetPORDDRFreq = 2
N6.C2: SPD Dimm Freq = 2 vs POR Freq = 2
N6.C2: Freq Override = 2
N6.C3: Common Dram Vdd = 0
N6.C3: GetPORDDRFreq found freqTable LUT index 42. ddrFreq = 2
N6.C3: GetPORDDRFreq = 2
N6.C3: SPD Dimm Freq = 2 vs POR Freq = 2
N6.C3: Freq Override = 2
N6: For JCK1 enforce MaxDdrFreq to be 1333MT/s. The 1600MT/s is not supported for vmse_2xfc 0 in 2:1 mode
N7: commonTck = 10, ddrFreq set to 3
N7.C0: Common Dram Vdd = 0
N7.C0: GetPORDDRFreq found freqTable LUT index 38. ddrFreq = 2
N7.C0: GetPORDDRFreq = 2
N7.C0: SPD Dimm Freq = 3 vs POR Freq = 2
N7.C0: Freq Override = 2
N7.C1: Common Dram Vdd = 0
N7.C1: GetPORDDRFreq found freqTable LUT index 38. ddrFreq = 2
N7.C1: GetPORDDRFreq = 2
N7.C1: SPD Dimm Freq = 2 vs POR Freq = 2
N7.C1: Freq Override = 2
N7.C2: Common Dram Vdd = 0
N7.C2: GetPORDDRFreq found freqTable LUT index 38. ddrFreq = 2
N7.C2: GetPORDDRFreq = 2
N7.C2: SPD Dimm Freq = 2 vs POR Freq = 2
N7.C2: Freq Override = 2
N7.C3: Common Dram Vdd = 0
N7.C3: GetPORDDRFreq found freqTable LUT index 38. ddrFreq = 2
N7.C3: GetPORDDRFreq = 2
N7.C3: SPD Dimm Freq = 2 vs POR Freq = 2
N7.C3: Freq Override = 2
N7: For JCK1 enforce MaxDdrFreq to be 1333MT/s. The 1600MT/s is not supported for vmse_2xfc 0 in 2:1 mode
N8: System common freq = 2
System freq at boot = 2
N0: Node freq = 2
N1: Node freq = 2
N2: Node freq = 2
N3: Node freq = 2
N4: Node freq = 2
N5: Node freq = 2
N6: Node freq = 2
N7: Node freq = 2
Memory behind Node 0 running at DDR Freq - 1333Mhz, Running at VMSE Freq - 2667Mhz in 2:1 mode
Memory behind Node 1 running at DDR Freq - 1333Mhz, Running at VMSE Freq - 2667Mhz in 2:1 mode
Memory behind Node 2 running at DDR Freq - 1333Mhz, Running at VMSE Freq - 2667Mhz in 2:1 mode
Memory behind Node 3 running at DDR Freq - 1333Mhz, Running at VMSE Freq - 2667Mhz in 2:1 mode
Memory behind Node 4 running at DDR Freq - 1333Mhz, Running at VMSE Freq - 2667Mhz in 2:1 mode
Memory behind Node 5 running at DDR Freq - 1333Mhz, Running at VMSE Freq - 2667Mhz in 2:1 mode
Memory behind Node 6 running at DDR Freq - 1333Mhz, Running at VMSE Freq - 2667Mhz in 2:1 mode
Memory behind Node 7 running at DDR Freq - 1333Mhz, Running at VMSE Freq - 2667Mhz in 2:1 mode
Get data from S0 to S1
Get data from S0 to S2
Get data from S0 to S3
N0: SetLowVoltage: Checkpoint Code: Socket 0, 0xB4, 0xFB, 0x0000
Setting N0 Vdd to 1.5V
N0: CMD_ACTIVE_VR_MASK = 0x0, ACTIVE_VR_MASK = 0xF 
N0: DDR Voltage: N0: 1.50V
N0: GetSvidEncodingPerProtocol: VrMode = 0x1, SvidEncodingValue = 0xFB 
N1: SetLowVoltage: Checkpoint Code: Socket 0, 0xB4, 0xFB, 0x0000
Setting N1 Vdd to 1.5V
N1: CMD_ACTIVE_VR_MASK = 0x0, ACTIVE_VR_MASK = 0xF 
N1: DDR Voltage: N1: 1.50V
N1: GetSvidEncodingPerProtocol: VrMode = 0x1, SvidEncodingValue = 0xFB 
N2: SetLowVoltage: Checkpoint Code: Socket 0, 0xB4, 0xFB, 0x0000
Setting N2 Vdd to 1.5V
N2: CMD_ACTIVE_VR_MASK = 0x0, ACTIVE_VR_MASK = 0xF 
N2: DDR Voltage: N2: 1.50V
N2: GetSvidEncodingPerProtocol: VrMode = 0x1, SvidEncodingValue = 0xFB 
N3: SetLowVoltage: Checkpoint Code: Socket 0, 0xB4, 0xFB, 0x0000
Setting N3 Vdd to 1.5V
N3: CMD_ACTIVE_VR_MASK = 0x0, ACTIVE_VR_MASK = 0xF 
N3: DDR Voltage: N3: 1.50V
N3: GetSvidEncodingPerProtocol: VrMode = 0x1, SvidEncodingValue = 0xFB 
N4: SetLowVoltage: Checkpoint Code: Socket 0, 0xB4, 0xFB, 0x0000
Setting N4 Vdd to 1.5V
N4: CMD_ACTIVE_VR_MASK = 0x0, ACTIVE_VR_MASK = 0xF 
N4: DDR Voltage: N4: 1.50V
N4: GetSvidEncodingPerProtocol: VrMode = 0x1, SvidEncodingValue = 0xFB 
N5: SetLowVoltage: Checkpoint Code: Socket 0, 0xB4, 0xFB, 0x0000
Setting N5 Vdd to 1.5V
N5: CMD_ACTIVE_VR_MASK = 0x0, ACTIVE_VR_MASK = 0xF 
N5: DDR Voltage: N5: 1.50V
N5: GetSvidEncodingPerProtocol: VrMode = 0x1, SvidEncodingValue = 0xFB 
N6: SetLowVoltage: Checkpoint Code: Socket 0, 0xB4, 0xFB, 0x0000
Setting N6 Vdd to 1.5V
N6: CMD_ACTIVE_VR_MASK = 0x0, ACTIVE_VR_MASK = 0xF 
N6: DDR Voltage: N6: 1.50V
N6: GetSvidEncodingPerProtocol: VrMode = 0x1, SvidEncodingValue = 0xFB 
N7: SetLowVoltage: Checkpoint Code: Socket 0, 0xB4, 0xFB, 0x0000
Setting N7 Vdd to 1.5V
N7: CMD_ACTIVE_VR_MASK = 0x0, ACTIVE_VR_MASK = 0xF 
N7: DDR Voltage: N7: 1.50V
N7: GetSvidEncodingPerProtocol: VrMode = 0x1, SvidEncodingValue = 0xFB 
Send data from S0 to S1
Send data from S0 to S2
N2: GatherSPDData
Gather SPD Data
N2.C0.D0: tWR in MTB units: 0x78
N4: GatherSPDData
Send data from S0 to S3
Gather SPD Data
N4.C0.D0: tWR in MTB units: 0x78
N6: GatherSPDData
Checkpoint Code: Socket 0, 0xB5, 0x00, 0x0000
Gather SPD Data
N0: GatherSPDData
Gather SPD Data
N6.C0.D0: tWR in MTB units: 0x78
N0.C0.D0: tWR in MTB units: 0x78
N2.C1.D0: tWR in MTB units: 0x78
N4.C1.D0: tWR in MTB units: 0x78
N6.C1.D0: tWR in MTB units: 0x78
N0.C1.D0: tWR in MTB units: 0x78
N2.C2.D0: tWR in MTB units: 0x78
N4.C2.D0: tWR in MTB units: 0x78
N6.C2.D0: tWR in MTB units: 0x78
N0.C2.D0: tWR in MTB units: 0x78
N2.C3.D0: tWR in MTB units: 0x78
N4.C3.D0: tWR in MTB units: 0x78
N6.C3.D0: tWR in MTB units: 0x78
N0.C3.D0: tWR in MTB units: 0x78

GatherSPDData time            194 ms
N2: GlobalEarlyConfig
N2: Global Early Configuration
N2.C0: GlobalEarlyConfig: mcmntChknbit.frc_mddl_on = 1

GatherSPDData time            194 ms
N2.C0.D0: Config DIMMMTR_0_MCDDC_DESC_REG: 000C502D
N4: GlobalEarlyConfig
N2.C0.D1: Config DIMMMTR_0_MCDDC_DESC_REG: 000C502D
N4: Global Early Configuration

GatherSPDData time            193 ms

GatherSPDData time            193 ms
N2.C0: RX Vref Default = 32
N4.C0: GlobalEarlyConfig: mcmntChknbit.frc_mddl_on = 1
N6: GlobalEarlyConfig
N0: GlobalEarlyConfig
N2.C1: GlobalEarlyConfig: mcmntChknbit.frc_mddl_on = 1
N4.C0.D0: Config DIMMMTR_0_MCDDC_DESC_REG: 000C502D
N6: Global Early Configuration
N0: Global Early Configuration
N2.C1.D0: Config DIMMMTR_0_MCDDC_DESC_REG: 000C502D
N4.C0.D1: Config DIMMMTR_0_MCDDC_DESC_REG: 000C502D
N6.C0: GlobalEarlyConfig: mcmntChknbit.frc_mddl_on = 1
N0.C0: GlobalEarlyConfig: mcmntChknbit.frc_mddl_on = 1
N2.C1.D1: Config DIMMMTR_0_MCDDC_DESC_REG: 000C502D
N4.C0: RX Vref Default = 32
N6.C0.D0: Config DIMMMTR_0_MCDDC_DESC_REG: 000C502D
N0.C0.D0: Config DIMMMTR_0_MCDDC_DESC_REG: 000C502D
N2.C1: RX Vref Default = 32
N4.C1: GlobalEarlyConfig: mcmntChknbit.frc_mddl_on = 1
N6.C0.D1: Config DIMMMTR_0_MCDDC_DESC_REG: 000C502D
N0.C0.D1: Config DIMMMTR_0_MCDDC_DESC_REG: 000C502D
N2.C2: GlobalEarlyConfig: mcmntChknbit.frc_mddl_on = 1
N4.C1.D0: Config DIMMMTR_0_MCDDC_DESC_REG: 000C502D
N6.C0: RX Vref Default = 32
N0.C0: RX Vref Default = 32
N2.C2.D0: Config DIMMMTR_0_MCDDC_DESC_REG: 000C502D
N4.C1.D1: Config DIMMMTR_0_MCDDC_DESC_REG: 000C502D
N6.C1: GlobalEarlyConfig: mcmntChknbit.frc_mddl_on = 1
N0.C1: GlobalEarlyConfig: mcmntChknbit.frc_mddl_on = 1
N2.C2.D1: Config DIMMMTR_0_MCDDC_DESC_REG: 000C502D
N4.C1: RX Vref Default = 32
N6.C1.D0: Config DIMMMTR_0_MCDDC_DESC_REG: 000C502D
N0.C1.D0: Config DIMMMTR_0_MCDDC_DESC_REG: 000C502D
N2.C2: RX Vref Default = 32
N4.C2: GlobalEarlyConfig: mcmntChknbit.frc_mddl_on = 1
N6.C1.D1: Config DIMMMTR_0_MCDDC_DESC_REG: 000C502D
N0.C1.D1: Config DIMMMTR_0_MCDDC_DESC_REG: 000C502D
N2.C3: GlobalEarlyConfig: mcmntChknbit.frc_mddl_on = 1
N4.C2.D0: Config DIMMMTR_0_MCDDC_DESC_REG: 000C502D
N6.C1: RX Vref Default = 32
N0.C1: RX Vref Default = 32
N2.C3.D0: Config DIMMMTR_0_MCDDC_DESC_REG: 000C502D
N4.C2.D1: Config DIMMMTR_0_MCDDC_DESC_REG: 000C502D
N6.C2: GlobalEarlyConfig: mcmntChknbit.frc_mddl_on = 1
N0.C2: GlobalEarlyConfig: mcmntChknbit.frc_mddl_on = 1
N2.C3.D1: Config DIMMMTR_0_MCDDC_DESC_REG: 000C502D
N4.C2: RX Vref Default = 32
N6.C2.D0: Config DIMMMTR_0_MCDDC_DESC_REG: 000C502D
N0.C2.D0: Config DIMMMTR_0_MCDDC_DESC_REG: 000C502D
N2.C3: RX Vref Default = 32
N4.C3: GlobalEarlyConfig: mcmntChknbit.frc_mddl_on = 1
N6.C2.D1: Config DIMMMTR_0_MCDDC_DESC_REG: 000C502D
N0.C2.D1: Config DIMMMTR_0_MCDDC_DESC_REG: 000C502D
N2: ChannelEarlyConfig
N4.C3.D0: Config DIMMMTR_0_MCDDC_DESC_REG: 000C502D
N6.C2: RX Vref Default = 32
N0.C2: RX Vref Default = 32
N2: Channel Early Configuration
N4.C3.D1: Config DIMMMTR_0_MCDDC_DESC_REG: 000C502D
N6.C3: GlobalEarlyConfig: mcmntChknbit.frc_mddl_on = 1
N0.C3: GlobalEarlyConfig: mcmntChknbit.frc_mddl_on = 1
N2.C0: Enable = 1
N4.C3: RX Vref Default = 32
N6.C3.D0: Config DIMMMTR_0_MCDDC_DESC_REG: 000C502D
N0.C3.D0: Config DIMMMTR_0_MCDDC_DESC_REG: 000C502D
N2.C0.D0: Enable = 1
N4: ChannelEarlyConfig
N6.C3.D1: Config DIMMMTR_0_MCDDC_DESC_REG: 000C502D
N0.C3.D1: Config DIMMMTR_0_MCDDC_DESC_REG: 000C502D
N2.C0.D0.R0: Enable = 1
N4: Channel Early Configuration
N6.C3: RX Vref Default = 32
N0.C3: RX Vref Default = 32
N2.C0.D0.R0: ENABLED: ckeMask = 00000001
N4.C0: Enable = 1
N6: ChannelEarlyConfig
Checkpoint Code: Socket 0, 0xB8, 0x00, 0x0000
N2.C0.D0.R1: Enable = 1
N4.C0.D0: Enable = 1
N6: Channel Early Configuration
N0: ChannelEarlyConfig
N2.C0.D0.R1: ENABLED: ckeMask = 00000003
N4.C0.D0.R0: Enable = 1
N6.C0: Enable = 1
N0: Channel Early Configuration
N2.C0.D0.R2: Enable = 0
N4.C0.D0.R0: ENABLED: ckeMask = 00000001
N6.C0.D0: Enable = 1
N0.C0: Enable = 1
N2.C0.D0.R3: Enable = 0
N4.C0.D0.R1: Enable = 1
N6.C0.D0.R0: Enable = 1
N0.C0.D0: Enable = 1
N2.C0.D1: Enable = 1
N4.C0.D0.R1: ENABLED: ckeMask = 00000003
N6.C0.D0.R0: ENABLED: ckeMask = 00000001
N0.C0.D0.R0: Enable = 1
N2.C0.D1.R0: Enable = 1
N4.C0.D0.R2: Enable = 0
N6.C0.D0.R1: Enable = 1
N0.C0.D0.R0: ENABLED: ckeMask = 00000001
N2.C0.D1.R0: ENABLED: ckeMask = 00000007
N4.C0.D0.R3: Enable = 0
N6.C0.D0.R1: ENABLED: ckeMask = 00000003
N0.C0.D0.R1: Enable = 1
N2.C0.D1.R1: Enable = 1
N4.C0.D1: Enable = 1
N6.C0.D0.R2: Enable = 0
N0.C0.D0.R1: ENABLED: ckeMask = 00000003
N2.C0.D1.R1: ENABLED: ckeMask = 0000000F
N4.C0.D1.R0: Enable = 1
N6.C0.D0.R3: Enable = 0
N0.C0.D0.R2: Enable = 0
N2.C0.D1.R2: Enable = 0
N4.C0.D1.R0: ENABLED: ckeMask = 00000007
N6.C0.D1: Enable = 1
N0.C0.D0.R3: Enable = 0
N2.C0.D1.R3: Enable = 0
N4.C0.D1.R1: Enable = 1
N6.C0.D1.R0: Enable = 1
N0.C0.D1: Enable = 1
N2.C0.D2: Enable = 0
N4.C0.D1.R1: ENABLED: ckeMask = 0000000F
N6.C0.D1.R0: ENABLED: ckeMask = 00000007
N0.C0.D1.R0: Enable = 1
N2.C1: Enable = 1
N4.C0.D1.R2: Enable = 0
N6.C0.D1.R1: Enable = 1
N0.C0.D1.R0: ENABLED: ckeMask = 00000007
N2.C1.D0: Enable = 1
N4.C0.D1.R3: Enable = 0
N6.C0.D1.R1: ENABLED: ckeMask = 0000000F
N0.C0.D1.R1: Enable = 1
N2.C1.D0.R0: Enable = 1
N4.C0.D2: Enable = 0
N6.C0.D1.R2: Enable = 0
N0.C0.D1.R1: ENABLED: ckeMask = 0000000F
N2.C1.D0.R0: ENABLED: ckeMask = 00000001
N4.C1: Enable = 1
N6.C0.D1.R3: Enable = 0
N0.C0.D1.R2: Enable = 0
N2.C1.D0.R1: Enable = 1
N4.C1.D0: Enable = 1
N6.C0.D2: Enable = 0
N0.C0.D1.R3: Enable = 0
N2.C1.D0.R1: ENABLED: ckeMask = 00000003
N4.C1.D0.R0: Enable = 1
N6.C1: Enable = 1
N0.C0.D2: Enable = 0
N2.C1.D0.R2: Enable = 0
N4.C1.D0.R0: ENABLED: ckeMask = 00000001
N6.C1.D0: Enable = 1
N0.C1: Enable = 1
N2.C1.D0.R3: Enable = 0
N4.C1.D0.R1: Enable = 1
N6.C1.D0.R0: Enable = 1
N0.C1.D0: Enable = 1
N2.C1.D1: Enable = 1
N4.C1.D0.R1: ENABLED: ckeMask = 00000003
N6.C1.D0.R0: ENABLED: ckeMask = 00000001
N0.C1.D0.R0: Enable = 1
N2.C1.D1.R0: Enable = 1
N4.C1.D0.R2: Enable = 0
N6.C1.D0.R1: Enable = 1
N0.C1.D0.R0: ENABLED: ckeMask = 00000001
N2.C1.D1.R0: ENABLED: ckeMask = 00000007
N4.C1.D0.R3: Enable = 0
N6.C1.D0.R1: ENABLED: ckeMask = 00000003
N0.C1.D0.R1: Enable = 1
N2.C1.D1.R1: Enable = 1
N4.C1.D1: Enable = 1
N6.C1.D0.R2: Enable = 0
N0.C1.D0.R1: ENABLED: ckeMask = 00000003
N2.C1.D1.R1: ENABLED: ckeMask = 0000000F
N4.C1.D1.R0: Enable = 1
N6.C1.D0.R3: Enable = 0
N0.C1.D0.R2: Enable = 0
N2.C1.D1.R2: Enable = 0
N4.C1.D1.R0: ENABLED: ckeMask = 00000007
N6.C1.D1: Enable = 1
N0.C1.D0.R3: Enable = 0
N2.C1.D1.R3: Enable = 0
N4.C1.D1.R1: Enable = 1
N6.C1.D1.R0: Enable = 1
N0.C1.D1: Enable = 1
N2.C1.D2: Enable = 0
N4.C1.D1.R1: ENABLED: ckeMask = 0000000F
N6.C1.D1.R0: ENABLED: ckeMask = 00000007
N0.C1.D1.R0: Enable = 1
N2.C2: Enable = 1
N4.C1.D1.R2: Enable = 0
N6.C1.D1.R1: Enable = 1
N0.C1.D1.R0: ENABLED: ckeMask = 00000007
N2.C2.D0: Enable = 1
N4.C1.D1.R3: Enable = 0
N6.C1.D1.R1: ENABLED: ckeMask = 0000000F
N0.C1.D1.R1: Enable = 1
N2.C2.D0.R0: Enable = 1
N4.C1.D2: Enable = 0
N6.C1.D1.R2: Enable = 0
N0.C1.D1.R1: ENABLED: ckeMask = 0000000F
N2.C2.D0.R0: ENABLED: ckeMask = 00000001
N4.C2: Enable = 1
N6.C1.D1.R3: Enable = 0
N0.C1.D1.R2: Enable = 0
N2.C2.D0.R1: Enable = 1
N4.C2.D0: Enable = 1
N6.C1.D2: Enable = 0
N0.C1.D1.R3: Enable = 0
N2.C2.D0.R1: ENABLED: ckeMask = 00000003
N4.C2.D0.R0: Enable = 1
N6.C2: Enable = 1
N0.C1.D2: Enable = 0
N2.C2.D0.R2: Enable = 0
N4.C2.D0.R0: ENABLED: ckeMask = 00000001
N6.C2.D0: Enable = 1
N0.C2: Enable = 1
N2.C2.D0.R3: Enable = 0
N4.C2.D0.R1: Enable = 1
N6.C2.D0.R0: Enable = 1
N0.C2.D0: Enable = 1
N2.C2.D1: Enable = 1
N4.C2.D0.R1: ENABLED: ckeMask = 00000003
N6.C2.D0.R0: ENABLED: ckeMask = 00000001
N0.C2.D0.R0: Enable = 1
N2.C2.D1.R0: Enable = 1
N4.C2.D0.R2: Enable = 0
N6.C2.D0.R1: Enable = 1
N0.C2.D0.R0: ENABLED: ckeMask = 00000001
N2.C2.D1.R0: ENABLED: ckeMask = 00000007
N4.C2.D0.R3: Enable = 0
N6.C2.D0.R1: ENABLED: ckeMask = 00000003
N0.C2.D0.R1: Enable = 1
N2.C2.D1.R1: Enable = 1
N4.C2.D1: Enable = 1
N6.C2.D0.R2: Enable = 0
N0.C2.D0.R1: ENABLED: ckeMask = 00000003
N2.C2.D1.R1: ENABLED: ckeMask = 0000000F
N4.C2.D1.R0: Enable = 1
N6.C2.D0.R3: Enable = 0
N0.C2.D0.R2: Enable = 0
N2.C2.D1.R2: Enable = 0
N4.C2.D1.R0: ENABLED: ckeMask = 00000007
N6.C2.D1: Enable = 1
N0.C2.D0.R3: Enable = 0
N2.C2.D1.R3: Enable = 0
N4.C2.D1.R1: Enable = 1
N6.C2.D1.R0: Enable = 1
N0.C2.D1: Enable = 1
N2.C2.D2: Enable = 0
N4.C2.D1.R1: ENABLED: ckeMask = 0000000F
N6.C2.D1.R0: ENABLED: ckeMask = 00000007
N0.C2.D1.R0: Enable = 1
N2.C3: Enable = 1
N4.C2.D1.R2: Enable = 0
N6.C2.D1.R1: Enable = 1
N0.C2.D1.R0: ENABLED: ckeMask = 00000007
N2.C3.D0: Enable = 1
N4.C2.D1.R3: Enable = 0
N6.C2.D1.R1: ENABLED: ckeMask = 0000000F
N0.C2.D1.R1: Enable = 1
N2.C3.D0.R0: Enable = 1
N4.C2.D2: Enable = 0
N6.C2.D1.R2: Enable = 0
N0.C2.D1.R1: ENABLED: ckeMask = 0000000F
N2.C3.D0.R0: ENABLED: ckeMask = 00000001
N4.C3: Enable = 1
N6.C2.D1.R3: Enable = 0
N0.C2.D1.R2: Enable = 0
N2.C3.D0.R1: Enable = 1
N4.C3.D0: Enable = 1
N6.C2.D2: Enable = 0
N0.C2.D1.R3: Enable = 0
N2.C3.D0.R1: ENABLED: ckeMask = 00000003
N4.C3.D0.R0: Enable = 1
N6.C3: Enable = 1
N0.C2.D2: Enable = 0
N2.C3.D0.R2: Enable = 0
N4.C3.D0.R0: ENABLED: ckeMask = 00000001
N6.C3.D0: Enable = 1
N0.C3: Enable = 1
N2.C3.D0.R3: Enable = 0
N4.C3.D0.R1: Enable = 1
N6.C3.D0.R0: Enable = 1
N0.C3.D0: Enable = 1
N2.C3.D1: Enable = 1
N4.C3.D0.R1: ENABLED: ckeMask = 00000003
N6.C3.D0.R0: ENABLED: ckeMask = 00000001
N0.C3.D0.R0: Enable = 1
N2.C3.D1.R0: Enable = 1
N4.C3.D0.R2: Enable = 0
N6.C3.D0.R1: Enable = 1
N0.C3.D0.R0: ENABLED: ckeMask = 00000001
N2.C3.D1.R0: ENABLED: ckeMask = 00000007
N4.C3.D0.R3: Enable = 0
N6.C3.D0.R1: ENABLED: ckeMask = 00000003
N0.C3.D0.R1: Enable = 1
N2.C3.D1.R1: Enable = 1
N4.C3.D1: Enable = 1
N6.C3.D0.R2: Enable = 0
N0.C3.D0.R1: ENABLED: ckeMask = 00000003
N2.C3.D1.R1: ENABLED: ckeMask = 0000000F
N4.C3.D1.R0: Enable = 1
N6.C3.D0.R3: Enable = 0
N0.C3.D0.R2: Enable = 0
N2.C3.D1.R2: Enable = 0
N4.C3.D1.R0: ENABLED: ckeMask = 00000007
N6.C3.D1: Enable = 1
N0.C3.D0.R3: Enable = 0
N2.C3.D1.R3: Enable = 0
N4.C3.D1.R1: Enable = 1
N6.C3.D1.R0: Enable = 1
N0.C3.D1: Enable = 1
N2.C3.D2: Enable = 0
N4.C3.D1.R1: ENABLED: ckeMask = 0000000F
N6.C3.D1.R0: ENABLED: ckeMask = 00000007
N0.C3.D1.R0: Enable = 1
N2: Memory Timings:
N4.C3.D1.R2: Enable = 0
N6.C3.D1.R1: Enable = 1
N0.C3.D1.R0: ENABLED: ckeMask = 00000007
N2.C0: nCL = 9
N4.C3.D1.R3: Enable = 0
N6.C3.D1.R1: ENABLED: ckeMask = 0000000F
N0.C3.D1.R1: Enable = 1
N2.C0: nCWL = 7
N4.C3.D2: Enable = 0
N6.C3.D1.R2: Enable = 0
N0.C3.D1.R1: ENABLED: ckeMask = 0000000F
N2.C0: nRP = 9
N4: Memory Timings:
N6.C3.D1.R3: Enable = 0
N0.C3.D1.R2: Enable = 0
N2.C0: nRCD = 9
N4.C0: nCL = 9
N6.C3.D2: Enable = 0
N0.C3.D1.R3: Enable = 0
N2.C0: nRRD = 4
N4.C0: nCWL = 7
N6: Memory Timings:
N0.C3.D2: Enable = 0
N2.C0: nWTR = 5
N4.C0: nRP = 9
N6.C0: nCL = 9
N0: Memory Timings:
N2.C0: nRAS = 24
N4.C0: nRCD = 9
N6.C0: nCWL = 7
N0.C0: nCL = 9
N2.C0: nRTP = 5
N4.C0: nRRD = 4
N6.C0: nRP = 9
N0.C0: nCWL = 7
N2.C0: nWR = 10
N4.C0: nWTR = 5
N6.C0: nRCD = 9
N0.C0: nRP = 9
N2.C0: nFAW = 20
N4.C0: nRAS = 24
N6.C0: nRRD = 4
N0.C0: nRCD = 9
N2.C0: nRC = 33
N4.C0: nRTP = 5
N6.C0: nWTR = 5
N0.C0: nRRD = 4
N2.C0: nRFC = 107
N4.C0: nWR = 10
N6.C0: nRAS = 24
N0.C0: nWTR = 5
N2.C0: casSup = 0x3C
N4.C0: nFAW = 20
N6.C0: nRTP = 5
N0.C0: nRAS = 24
N2.C0: trrMode = 0
N4.C0: nRC = 33
N6.C0: nWR = 10
N0.C0: nRTP = 5
N2.C0: twoXRefresh = 0
N4.C0: nRFC = 107
N6.C0: nFAW = 20
N0.C0: nWR = 10
N2.C0: t_stagger_ref = 0x4B
N4.C0: casSup = 0xFC
N6.C0: nRC = 33
N0.C0: nFAW = 20
N2.C0: tcsrftp.Bits.t_xsdll = 512
N4.C0: trrMode = 0
N6.C0: nRFC = 107
N0.C0: nRC = 33
N2.C0: Common CL = 9
Common CWL = 7
N4.C0: twoXRefresh = 0
N6.C0: casSup = 0x3C
N0.C0: nRFC = 107
N2: Memory Timings:
N4.C0: t_stagger_ref = 0x4B
N6.C0: trrMode = 0
N0.C0: casSup = 0xFC
N2.C1: nCL = 9
N4.C0: tcsrftp.Bits.t_xsdll = 512
N6.C0: twoXRefresh = 0
N0.C0: trrMode = 0
N2.C1: nCWL = 7
N4.C0: Common CL = 9
Common CWL = 7
N6.C0: t_stagger_ref = 0x4B
N0.C0: twoXRefresh = 0
N2.C1: nRP = 9
N4: Memory Timings:
N6.C0: tcsrftp.Bits.t_xsdll = 512
N0.C0: t_stagger_ref = 0x4B
N2.C1: nRCD = 9
N4.C1: nCL = 9
N6.C0: Common CL = 9
Common CWL = 7
N0.C0: tcsrftp.Bits.t_xsdll = 512
N2.C1: nRRD = 4
N4.C1: nCWL = 7
N6: Memory Timings:
N0.C0: Common CL = 9
Common CWL = 7
N2.C1: nWTR = 5
N4.C1: nRP = 9
N6.C1: nCL = 9
N0: Memory Timings:
N2.C1: nRAS = 24
N4.C1: nRCD = 9
N6.C1: nCWL = 7
N0.C1: nCL = 9
N2.C1: nRTP = 5
N4.C1: nRRD = 4
N6.C1: nRP = 9
N0.C1: nCWL = 7
N2.C1: nWR = 10
N4.C1: nWTR = 5
N6.C1: nRCD = 9
N0.C1: nRP = 9
N2.C1: nFAW = 20
N4.C1: nRAS = 24
N6.C1: nRRD = 4
N0.C1: nRCD = 9
N2.C1: nRC = 33
N4.C1: nRTP = 5
N6.C1: nWTR = 5
N0.C1: nRRD = 4
N2.C1: nRFC = 107
N4.C1: nWR = 10
N6.C1: nRAS = 24
N0.C1: nWTR = 5
N2.C1: casSup = 0x3C
N4.C1: nFAW = 20
N6.C1: nRTP = 5
N0.C1: nRAS = 24
N2.C1: trrMode = 0
N4.C1: nRC = 33
N6.C1: nWR = 10
N0.C1: nRTP = 5
N2.C1: twoXRefresh = 0
N4.C1: nRFC = 107
N6.C1: nFAW = 20
N0.C1: nWR = 10
N2.C1: t_stagger_ref = 0x4B
N4.C1: casSup = 0xFC
N6.C1: nRC = 33
N0.C1: nFAW = 20
N2.C1: tcsrftp.Bits.t_xsdll = 512
N4.C1: trrMode = 0
N6.C1: nRFC = 107
N0.C1: nRC = 33
N2.C1: Common CL = 9
Common CWL = 7
N4.C1: twoXRefresh = 0
N6.C1: casSup = 0x3C
N0.C1: nRFC = 107
N2: Memory Timings:
N4.C1: t_stagger_ref = 0x4B
N6.C1: trrMode = 0
N0.C1: casSup = 0xFC
N2.C2: nCL = 9
N4.C1: tcsrftp.Bits.t_xsdll = 512
N6.C1: twoXRefresh = 0
N0.C1: trrMode = 0
N2.C2: nCWL = 7
N4.C1: Common CL = 9
Common CWL = 7
N6.C1: t_stagger_ref = 0x4B
N0.C1: twoXRefresh = 0
N2.C2: nRP = 9
N4: Memory Timings:
N6.C1: tcsrftp.Bits.t_xsdll = 512
N0.C1: t_stagger_ref = 0x4B
N2.C2: nRCD = 9
N4.C2: nCL = 9
N6.C1: Common CL = 9
Common CWL = 7
N0.C1: tcsrftp.Bits.t_xsdll = 512
N2.C2: nRRD = 4
N4.C2: nCWL = 7
N6: Memory Timings:
N0.C1: Common CL = 9
Common CWL = 7
N2.C2: nWTR = 5
N4.C2: nRP = 9
N6.C2: nCL = 9
N0: Memory Timings:
N2.C2: nRAS = 24
N4.C2: nRCD = 9
N6.C2: nCWL = 7
N0.C2: nCL = 9
N2.C2: nRTP = 5
N4.C2: nRRD = 4
N6.C2: nRP = 9
N0.C2: nCWL = 7
N2.C2: nWR = 10
N4.C2: nWTR = 5
N6.C2: nRCD = 9
N0.C2: nRP = 9
N2.C2: nFAW = 20
N4.C2: nRAS = 24
N6.C2: nRRD = 4
N0.C2: nRCD = 9
N2.C2: nRC = 33
N4.C2: nRTP = 5
N6.C2: nWTR = 5
N0.C2: nRRD = 4
N2.C2: nRFC = 107
N4.C2: nWR = 10
N6.C2: nRAS = 24
N0.C2: nWTR = 5
N2.C2: casSup = 0x3C
N4.C2: nFAW = 20
N6.C2: nRTP = 5
N0.C2: nRAS = 24
N2.C2: trrMode = 0
N4.C2: nRC = 33
N6.C2: nWR = 10
N0.C2: nRTP = 5
N2.C2: twoXRefresh = 0
N4.C2: nRFC = 107
N6.C2: nFAW = 20
N0.C2: nWR = 10
N2.C2: t_stagger_ref = 0x4B
N4.C2: casSup = 0xFC
N6.C2: nRC = 33
N0.C2: nFAW = 20
N2.C2: tcsrftp.Bits.t_xsdll = 512
N4.C2: trrMode = 0
N6.C2: nRFC = 107
N0.C2: nRC = 33
N2.C2: Common CL = 9
Common CWL = 7
N4.C2: twoXRefresh = 0
N6.C2: casSup = 0x3C
N0.C2: nRFC = 107
N2: Memory Timings:
N4.C2: t_stagger_ref = 0x4B
N6.C2: trrMode = 0
N0.C2: casSup = 0xFC
N2.C3: nCL = 9
N4.C2: tcsrftp.Bits.t_xsdll = 512
N6.C2: twoXRefresh = 0
N0.C2: trrMode = 0
N2.C3: nCWL = 7
N4.C2: Common CL = 9
Common CWL = 7
N6.C2: t_stagger_ref = 0x4B
N0.C2: twoXRefresh = 0
N2.C3: nRP = 9
N4: Memory Timings:
N6.C2: tcsrftp.Bits.t_xsdll = 512
N0.C2: t_stagger_ref = 0x4B
N2.C3: nRCD = 9
N4.C3: nCL = 9
N6.C2: Common CL = 9
Common CWL = 7
N0.C2: tcsrftp.Bits.t_xsdll = 512
N2.C3: nRRD = 4
N4.C3: nCWL = 7
N6: Memory Timings:
N0.C2: Common CL = 9
Common CWL = 7
N2.C3: nWTR = 5
N4.C3: nRP = 9
N6.C3: nCL = 9
N0: Memory Timings:
N2.C3: nRAS = 24
N4.C3: nRCD = 9
N6.C3: nCWL = 7
N0.C3: nCL = 9
N2.C3: nRTP = 5
N4.C3: nRRD = 4
N6.C3: nRP = 9
N0.C3: nCWL = 7
N2.C3: nWR = 10
N4.C3: nWTR = 5
N6.C3: nRCD = 9
N0.C3: nRP = 9
N2.C3: nFAW = 20
N4.C3: nRAS = 24
N6.C3: nRRD = 4
N0.C3: nRCD = 9
N2.C3: nRC = 33
N4.C3: nRTP = 5
N6.C3: nWTR = 5
N0.C3: nRRD = 4
N2.C3: nRFC = 107
N4.C3: nWR = 10
N6.C3: nRAS = 24
N0.C3: nWTR = 5
N2.C3: casSup = 0x3C
N4.C3: nFAW = 20
N6.C3: nRTP = 5
N0.C3: nRAS = 24
N2.C3: trrMode = 0
N4.C3: nRC = 33
N6.C3: nWR = 10
N0.C3: nRTP = 5
N2.C3: twoXRefresh = 0
N4.C3: nRFC = 107
N6.C3: nFAW = 20
N0.C3: nWR = 10
N2.C3: t_stagger_ref = 0x4B
N4.C3: casSup = 0xFC
N6.C3: nRC = 33
N0.C3: nFAW = 20
N2.C3: tcsrftp.Bits.t_xsdll = 512
N4.C3: trrMode = 0
N6.C3: nRFC = 107
N0.C3: nRC = 33
N2.C3: Common CL = 9
Common CWL = 7
N4.C3: twoXRefresh = 0
N6.C3: casSup = 0x3C
N0.C3: nRFC = 107
N2: PreVmseTraining
N4.C3: t_stagger_ref = 0x4B
N6.C3: trrMode = 0
N0.C3: casSup = 0xFC
N2.C0: InitHostVmseCfg
N4.C3: tcsrftp.Bits.t_xsdll = 512
N6.C3: twoXRefresh = 0
N0.C3: trrMode = 0
N2.C0: vmse_wr_turnaround = 0x7 
N4.C3: Common CL = 9
Common CWL = 7
N6.C3: t_stagger_ref = 0x4B
N0.C3: twoXRefresh = 0
N2.C2: InitHostVmseCfg
N4: PreVmseTraining
N6.C3: tcsrftp.Bits.t_xsdll = 512
N0.C3: t_stagger_ref = 0x4B
N2.C2: vmse_wr_turnaround = 0x7 
N4.C0: InitHostVmseCfg
N6.C3: Common CL = 9
Common CWL = 7
N0.C3: tcsrftp.Bits.t_xsdll = 512
N2: HsxInitDdrioInterface
N4.C0: vmse_wr_turnaround = 0x7 
N6: PreVmseTraining
N0.C3: Common CL = 9
Common CWL = 7
N2.C0: rxVref = 0x5F
N4.C2: InitHostVmseCfg
N6.C0: InitHostVmseCfg
Checkpoint Code: Socket 0, 0xB6, 0x00, 0x0000
N2.C1: rxVref = 0x5F
N4.C2: vmse_wr_turnaround = 0x7 
N6.C0: vmse_wr_turnaround = 0x7 
N0: PreVmseTraining
N2: HsxVmseCompInit
N4: HsxInitDdrioInterface
N6.C2: InitHostVmseCfg
Checkpoint Code: Socket 0, 0xB6, 0x01, 0x0000
N2: VmseCrossoverCalib
N2: Enable xovercal
N2: vmse_modes =          1,  0
N2.C0: piDelay CMDn  CMDs  CTL  CKE  CLK   0  1  2  3  4  5  6  7  8  9 10 11 12 13 14 15 16 17
          0       0     0    0    0    0   1  1  1  1  0  1  1  1  0  1  1  1  1  0  1  1  1  0 
          1       0     0    0    0    0   1  1  1  1  0  1  1  1  0  1  1  1  1  0  1  1  1  0 
          2       0     0    0    0    0   1  1  1  1  0  1  1  1  1  1  1  1  1  0  1  1  1  1 
          3       0     0    1    0    0   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
          4       0     0    1    0    0   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
          5       0     0    1    1    0   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
          6       0     0    1    1    0   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
          7       0     0    1    1    0   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
          8       0     0    1    1    0   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
          9       0     0    1    1    0   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         10       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         11       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         12       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         13       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         14       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         15       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         16       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         17       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         18       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         19       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         20       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         21       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         22       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         23       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         24       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         25       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         26       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         27       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         28       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         29       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         30       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         31       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         32       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         33       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         34       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         35       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         36       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         37       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         38       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         39       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         40       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         41       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         42       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         43       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         44       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         45       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         46       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         47       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         48       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         49       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         50       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         51       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         52       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         53       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         54       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         55       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         56       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         57       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         58       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         59       0     0    1    1    1   0  1  1  1  1  1  1  1  1  0  1  1  1  1  1  1  1  1 
         60       0     0    1    1    1   X  1  1  1  1  1  1  1  1  X  1  1  1  1  1  1  1  1 
         61       0     0    1    1    1   X  0  1  1  1  1  1  1  1  X  0  1  1  1  1  1  1  1 
         62       0     0    1    1    1   X  X  1  1  1  1  1  0  1  X  X  1  1  1  1  1  0  1 
         63       0     0    1    1    1   X  X  1  1  1  1  1  X  1  X  X  1  1  1  1  1  X  1 
N2.C0: setting ddrcrinvertpiclk
          0       0     0    1    1    1   X  X  0  1  1  1  0  X  1  X  X  0  1  1  1  0  X  1 
          1       0     0    1    1    1   X  X  0  0  1  1  0  X  1  X  X  0  0  1  1  0  X  1 
          2       0     0    1    1    1   X  X  0  X  1  0  0  X  1  X  X  0  X  1  0  0  X  1 
          3       0     0    1    1    1   X  X  0  X  1  X  0  X  0  X  X  0  X  1  X  0  X  0 
          4       0     0    0    1    1   X  X  0  X  0  X  0  X  X  X  X  0  X  0  X  0  X  X 
          5       0     0    X    1    1   X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0  X  X 
          6       0     0    X    1    1   X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0  X  X 
          7       0     0    X    0    1   X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0  X  X 
          8       0     0    X    X    1   X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0  X  X 
          9       0     0    X    X    1   X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0  X  X 
         10       0     0    X    X    1   X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0  X  X 
         11       0     0    X    X    0   X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0  X  X 
         12       0     0    X    X    X   X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0  X  X 
         13       0     0    X    X    X   X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0  X  X 
         14       0     0    X    X    X   X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0  X  X 
         15       0     0    X    X    X   X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0  X  X 
         16       0     0    X    X    X   X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0  X  X 
         17       0     0    X    X    X   X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0  X  X 
         18       0     0    X    X    X   X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0  X  X 
         19       0     0    X    X    X   X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0  X  X 
         20       0     0    X    X    X   X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0  X  X 
         21       0     0    X    X    X   X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0  X  X 
         22       0     0    X    X    X   X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0  X  X 
         23       0     0    X    X    X   X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0  X  X 
         24       0     0    X    X    X   X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0  X  X 
         25       0     0    X    X    X   X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0  X  X 
         26       0     0    X    X    X   X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0  X  X 
         27       0     0    X    X    X   X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0  X  X 
         28       0     0    X    X    X   X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0  X  X 
         29       0     0    X    X    X   X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0  X  X 
         30       0     0    X    X    X   X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0  X  X 
         31       0     0    X    X    X   X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0  X  X 
         32       0     0    X    X    X   X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0  X  X 
         33       0     0    X    X    X   X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0  X  X 
         34       0     0    X    X    X   X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0  X  X 
         35       0     0    X    X    X   X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0  X  X 
         36       0     0    X    X    X   X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0  X  X 
         37       0     0    X    X    X   X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0  X  X 
         38       0     0    X    X    X   X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0  X  X 
         39       0     0    X    X    X   X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0  X  X 
         40       0     0    X    X    X   X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0  X  X 
         41       0     0    X    X    X   X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0  X  X 
         42       0     0    X    X    X   X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0  X  X 
         43       0     0    X    X    X   X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0  X  X 
         44       0     0    X    X    X   X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0  X  X 
         45       0     0    X    X    X   X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0  X  X 
         46       0     0    X    X    X   X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0  X  X 
         47       0     0    X    X    X   X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0  X  X 
         48       0     0    X    X    X   X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0  X  X 
         49       0     0    X    X    X   X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0  X  X 
         50       0     0    X    X    X   X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0  X  X 
         51       0     0    X    X    X   X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0  X  X 
         52       0     0    X    X    X   X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0  X  X 
         53       0     0    X    X    X   X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0  X  X 
         54       0     0    X    X    X   X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0  X  X 
         55       0     0    X    X    X   X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0  X  X 
         56       0     0    X    X    X   X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0  X  X 
         57       0     0    X    X    X   X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0  X  X 
         58       0     0    X    X    X   X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0  X  X 
         59       0     0    X    X    X   X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0  X  X 
         60       0     0    X    X    X   X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0  X  X 
         61       0     0    X    X    X   X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0  X  X 
         62       0     0    X    X    X   X  X  1  X  X  X  0  X  X  X  X  1  X  X  X  0  X  X 
         63       0     0    X    X    X   X  X  1  X  X  X  1  X  X  X  X  1  X  X  X  1  X  X 
N2.C0: CMD-N xovercal offset = 0
N2.C0: CMD-S xovercal offset = 0
N2.C0: CTL xovercal offset   = 4
N2.C0: CKE xovercal offset   = 7
N2.C0: CLK xovercal offset   = 11
N2.C0.S18: STROBE                     0   1   2   3   4   5   6   7   8   9  10  11  12  13  14  15  16  17
N2.C0.S18: Rec En xovercal offset =  59  61   0   1   4   2   0  62   3  59  61   0   1   4   2   0  62   3 
N2.C0.S18: Tx Dqs xovercal offset =  59  63   0  63  63  63   0  63  63  63  63   0  63  63  63   0  63  63 
N2.C0.S18: Tx Dq xovercal offset  =  59  61   0   1   4   2   0  62   3  59  61   0   1   4   2   0  62   3 
N2.C0:         CMDn  CMDs  CTL  CKE  CLK   0  1  2  3  4  5  6  7  8
N2.C0: offsets:  0     0     4N2: getComplexCkeSetupTime defaultOffset = 98
N2: getComplexCkeSetupTime = 98
    7   11
Ctl Offsets Delta / final ctl offset / final cke offset /  98  /  38  /   9
Cke invertpiclk / Ctl invertpiclk / 0x0  /  0x0
N2: getComplexClkSetupTime defaultOffset = 0
N2: getComplexClkSetupTime = 0
ClkSetupTime = 11
N2: getComplexDqSetupTime defaultOffset = 0
N2: getComplexDqSetupTime = 0
N2.C0.S00: txdqoffset delta = 0, dq invertpiclk = 0
N2: getComplexDqsSetupTime defaultOffset = 40
N2: getComplexDqsSetupTime = 40
N2.C0.S00: txdqsoffset delta = 40
N2: getComplexRcvEnSetupTime defaultOffset = 37
N2: getComplexRcvEnSetupTime = 37
N2.C0.S00: rcvenoffset delta = 37
N2.C0.S00: Final txdqoffset / txdqsoffset / rcvenoffset / 27 /  3 /  0
N2: getComplexDqSetupTime defaultOffset = 0
N2: getComplexDqSetupTime = 0
N2.C0.S01: txdqoffset delta = 0, dq invertpiclk = 0
N2: getComplexDqsSetupTime defaultOffset = 40
N2: getComplexDqsSetupTime = 40
N2.C0.S01: txdqsoffset delta = 40
N2: getComplexRcvEnSetupTime defaultOffset = 37
N2: getComplexRcvEnSetupTime = 37
N2.C0.S01: rcvenoffset delta = 37
N2.C0.S01: Final txdqoffset / txdqsoffset / rcvenoffset / 61 / 37 / 34
N2: getComplexDqSetupTime defaultOffset = 0
N2: getComplexDqSetupTime = 0
N2.C0.S02: txdqoffset delta = 0, dq invertpiclk = 3
N2: getComplexDqsSetupTime defaultOffset = 40
N2: getComplexDqsSetupTime = 40
N2.C0.S02: txdqsoffset delta = 40
N2: getComplexRcvEnSetupTime defaultOffset = 37
N2: getComplexRcvEnSetupTime = 37
N2.C0.S02: rcvenoffset delta = 37
N2.C0.S02: Final txdqoffset / txdqsoffset / rcvenoffset / 32 /  8 /  5
N2: getComplexDqSetupTime defaultOffset = 0
N2: getComplexDqSetupTime = 0
N2.C0.S03: txdqoffset delta = 0, dq invertpiclk = 3
N2: getComplexDqsSetupTime defaultOffset = 40
N2: getComplexDqsSetupTime = 40
N2.C0.S03: txdqsoffset delta = 40
N2: getComplexRcvEnSetupTime defaultOffset = 37
N2: getComplexRcvEnSetupTime = 37
N2.C0.S03: rcvenoffset delta = 37
N2.C0.S03: Final txdqoffset / txdqsoffset / rcvenoffset /  1 / 41 / 38
N2: getComplexDqSetupTime defaultOffset = 0
N2: getComplexDqSetupTime = 0
N2.C0.S04: txdqoffset delta = 0, dq invertpiclk = 3
N2: getComplexDqsSetupTime defaultOffset = 40
N2: getComplexDqsSetupTime = 40
N2.C0.S04: txdqsoffset delta = 40
N2: getComplexRcvEnSetupTime defaultOffset = 37
N2: getComplexRcvEnSetupTime = 37
N2.C0.S04: rcvenoffset delta = 37
N2.C0.S04: Final txdqoffset / txdqsoffset / rcvenoffset / 36 / 12 /  9
N2: getComplexDqSetupTime defaultOffset = 0
N2: getComplexDqSetupTime = 0
N2.C0.S05: txdqoffset delta = 0, dq invertpiclk = 3
N2: getComplexDqsSetupTime defaultOffset = 40
N2: getComplexDqsSetupTime = 40
N2.C0.S05: txdqsoffset delta = 40
N2: getComplexRcvEnSetupTime defaultOffset = 37
N2: getComplexRcvEnSetupTime = 37
N2.C0.S05: rcvenoffset delta = 37
N2.C0.S05: Final txdqoffset / txdqsoffset / rcvenoffset /  2 / 42 / 39
N2: getComplexDqSetupTime defaultOffset = 0
N2: getComplexDqSetupTime = 0
N2.C0.S06: txdqoffset delta = 0, dq invertpiclk = 3
N2: getComplexDqsSetupTime defaultOffset = 40
N2: getComplexDqsSetupTime = 40
N2.C0.S06: txdqsoffset delta = 40
N2: getComplexRcvEnSetupTime defaultOffset = 37
N2: getComplexRcvEnSetupTime = 37
N2.C0.S06: rcvenoffset delta = 37
N2.C0.S06: Final txdqoffset / txdqsoffset / rcvenoffset / 32 /  8 /  5
N2: getComplexDqSetupTime defaultOffset = 0
N2: getComplexDqSetupTime = 0
N2.C0.S07: txdqoffset delta = 0, dq invertpiclk = 0
N2: getComplexDqsSetupTime defaultOffset = 40
N2: getComplexDqsSetupTime = 40
N2.C0.S07: txdqsoffset delta = 40
N2: getComplexRcvEnSetupTime defaultOffset = 37
N2: getComplexRcvEnSetupTime = 37
N2.C0.S07: rcvenoffset delta = 37
N2.C0.S07: Final txdqoffset / txdqsoffset / rcvenoffset / 62 / 38 / 35
N2: getComplexDqSetupTime defaultOffset = 0
N2: getComplexDqSetupTime = 0
N2.C0.S08: txdqoffset delta = 0, dq invertpiclk = 3
N2: getComplexDqsSetupTime defaultOffset = 40
N2: getComplexDqsSetupTime = 40
N2.C0.S08: txdqsoffset delta = 40
N2: getComplexRcvEnSetupTime defaultOffset = 37
N2: getComplexRcvEnSetupTime = 37
N2.C0.S08: rcvenoffset delta = 37
N2.C0.S08: Final txdqoffset / txdqsoffset / rcvenoffset / 35 / 11 /  8

N2: vmse_modes =          1,  0
N2.C1: piDelay CMDn  CMDs  CTL  CKE  CLK   0  1  2  3  4  5  6  7  8  9 10 11 12 13 14 15 16 17
          0       0     0    1    0    0   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
          1       0     0    1    1    0   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
          2       0     0    1    1    0   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
          3       0     0    1    1    0   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
          4       0     0    1    1    0   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
          5       0     0    1    1    0   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
          6       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
          7       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
          8       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
          9       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         10       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         11       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         12       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         13       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         14       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         15       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         16       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         17       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         18       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         19       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         20       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         21       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         22       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         23       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         24       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         25       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         26       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         27       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         28       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         29       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         30       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         31       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         32       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         33       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         34       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         35       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         36       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         37       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         38       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         39       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         40       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         41       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         42       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         43       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         44       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         45       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         46       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         47       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         48       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         49       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         50       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         51       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         52       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         53       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         54       0     0    1    1    1   0  1  1  1  1  1  1  1  1  0  1  1  1  1  1  1  1  1 
         55       0     0    1    1    1   X  1  1  1  1  1  1  1  1  X  1  1  1  1  1  1  1  1 
         56       0     0    1    1    1   X  1  1  1  1  1  1  1  1  X  1  1  1  1  1  1  1  1 
         57       0     0    1    1    1   X  0  1  1  1  1  1  1  1  X  0  1  1  1  1  1  1  1 
         58       0     0    1    1    1   X  X  1  1  1  1  1  1  1  X  X  1  1  1  1  1  1  1 
         59       0     0    1    1    1   X  X  0  1  1  1  1  0  1  X  X  0  1  1  1  1  0  1 
         60       0     0    1    1    1   X  X  X  1  1  1  0  X  1  X  X  X  1  1  1  0  X  1 
         61       0     0    1    1    1   X  X  X  1  1  1  X  X  1  X  X  X  1  1  1  X  X  1 
         62       0     0    1    1    1   X  X  X  0  1  0  X  X  1  X  X  X  0  1  0  X  X  1 
         63       0     0    1    1    1   X  X  X  X  1  X  X  X  1  X  X  X  X  1  X  X  X  1 
N2.C1: setting ddrcrinvertpiclk
          0       0     0    0    1    1   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
          1       0     0    0    1    1   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
          2       0     0    0    1    1   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
          3       0     0    0    0    1   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
          4       0     0    0    X    1   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
          5       0     0    0    X    1   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
          6       0     0    0    X    1   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
          7       0     0    0    X    0   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
          8       0     0    0    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
          9       0     0    0    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         10       0     0    0    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         11       0     0    0    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         12       0     0    0    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         13       0     0    0    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         14       0     0    0    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         15       0     0    0    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         16       0     0    0    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         17       0     0    0    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         18       0     0    0    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         19       0     0    0    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         20       0     0    0    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         21       0     0    0    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         22       0     0    0    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         23       0     0    0    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         24       0     0    0    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         25       0     0    0    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         26       0     0    0    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         27       0     0    0    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         28       0     0    0    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         29       0     0    0    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         30       0     0    0    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         31       0     0    0    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         32       0     0    0    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         33       0     0    0    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         34       0     0    0    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         35       0     0    0    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         36       0     0    0    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         37       0     0    0    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         38       0     0    0    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         39       0     0    0    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         40       0     0    0    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         41       0     0    0    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         42       0     0    0    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         43       0     0    0    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         44       0     0    0    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         45       0     0    0    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         46       0     0    0    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         47       0     0    0    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         48       0     0    0    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         49       0     0    0    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         50       0     0    0    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         51       0     0    0    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         52       0     0    0    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         53       0     0    0    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         54       0     0    0    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         55       0     0    0    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         56       0     0    0    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         57       0     0    0    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         58       0     0    0    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         59       0     0    0    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         60       0     0    0    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         61       0     0    0    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         62       0     0    0    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         63       0     0    0    X    X   X  X  X  X  0  X  X  X  1  X  X  X  X  0  X  X  X  1 
N2.C1: CMD-N xovercal offset = 0
N2.C1: CMD-S xovercal offset = 0
N2.C1: CTL xovercal offset   = 0
N2.C1: CKE xovercal offset   = 3
N2.C1: CLK xovercal offset   = 7
N2.C1.S18: STROBE                     0   1   2   3   4   5   6   7   8   9  10  11  12  13  14  15  16  17
N2.C1.S18: Rec En xovercal offset =  54  57  59  62   0  62  60  59   0  54  57  59  62   0  62  60  59   0 
N2.C1.S18: Tx Dqs xovercal offset =  54  63  63  63   0  63  63  63   0  63  63  63  63   0  63  63  63   0 
N2.C1.S18: Tx Dq xovercal offset  =  54  57  59  62   0  62  60  59   0  54  57  59  62   0  62  60  59   0 
N2.C1:         CMDn  CMDs  CTL  CKE  CLK   0  1  2  3  4  5  6  7  8
N2.C1: offsets:  0     0     0N2: getComplexCkeSetupTime defaultOffset = 98
N2: getComplexCkeSetupTime = 98
    3    7
Ctl Offsets Delta / final ctl offset / final cke offset /  98  /   2  /  37
Cke invertpiclk / Ctl invertpiclk / 0x0  /  0x0
N2: getComplexClkSetupTime defaultOffset = 0
N2: getComplexClkSetupTime = 0
ClkSetupTime = 39
N2: getComplexDqSetupTime defaultOffset = 0
N2: getComplexDqSetupTime = 0
N2.C1.S00: txdqoffset delta = 0, dq invertpiclk = 0
N2: getComplexDqsSetupTime defaultOffset = 40
N2: getComplexDqsSetupTime = 40
N2.C1.S00: txdqsoffset delta = 40
N2: getComplexRcvEnSetupTime defaultOffset = 37
N2: getComplexRcvEnSetupTime = 37
N2.C1.S00: rcvenoffset delta = 37
N2.C1.S00: Final txdqoffset / txdqsoffset / rcvenoffset / 54 / 30 / 27
N2: getComplexDqSetupTime defaultOffset = 0
N2: getComplexDqSetupTime = 0
N2.C1.S01: txdqoffset delta = 0, dq invertpiclk = 0
N2: getComplexDqsSetupTime defaultOffset = 40
N2: getComplexDqsSetupTime = 40
N2.C1.S01: txdqsoffset delta = 40
N2: getComplexRcvEnSetupTime defaultOffset = 37
N2: getComplexRcvEnSetupTime = 37
N2.C1.S01: rcvenoffset delta = 37
N2.C1.S01: Final txdqoffset / txdqsoffset / rcvenoffset / 25 /  1 / 62
N2: getComplexDqSetupTime defaultOffset = 0
N2: getComplexDqSetupTime = 0
N2.C1.S02: txdqoffset delta = 0, dq invertpiclk = 0
N2: getComplexDqsSetupTime defaultOffset = 40
N2: getComplexDqsSetupTime = 40
N2.C1.S02: txdqsoffset delta = 40
N2: getComplexRcvEnSetupTime defaultOffset = 37
N2: getComplexRcvEnSetupTime = 37
N2.C1.S02: rcvenoffset delta = 37
N2.C1.S02: Final txdqoffset / txdqsoffset / rcvenoffset / 59 / 35 / 32
N2: getComplexDqSetupTime defaultOffset = 0
N2: getComplexDqSetupTime = 0
N2.C1.S03: txdqoffset delta = 0, dq invertpiclk = 0
N2: getComplexDqsSetupTime defaultOffset = 40
N2: getComplexDqsSetupTime = 40
N2.C1.S03: txdqsoffset delta = 40
N2: getComplexRcvEnSetupTime defaultOffset = 37
N2: getComplexRcvEnSetupTime = 37
N2.C1.S03: rcvenoffset delta = 37
N2.C1.S03: Final txdqoffset / txdqsoffset / rcvenoffset / 30 /  6 /  3
N2: getComplexDqSetupTime defaultOffset = 0
N2: getComplexDqSetupTime = 0
N2.C1.S04: txdqoffset delta = 0, dq invertpiclk = 3
N2: getComplexDqsSetupTime defaultOffset = 40
N2: getComplexDqsSetupTime = 40
N2.C1.S04: txdqsoffset delta = 40
N2: getComplexRcvEnSetupTime defaultOffset = 37
N2: getComplexRcvEnSetupTime = 37
N2.C1.S04: rcvenoffset delta = 37
N2.C1.S04: Final txdqoffset / txdqsoffset / rcvenoffset /  0 / 40 / 37
N2: getComplexDqSetupTime defaultOffset = 0
N2: getComplexDqSetupTime = 0
N2.C1.S05: txdqoffset delta = 0, dq invertpiclk = 0
N2: getComplexDqsSetupTime defaultOffset = 40
N2: getComplexDqsSetupTime = 40
N2.C1.S05: txdqsoffset delta = 40
N2: getComplexRcvEnSetupTime defaultOffset = 37
N2: getComplexRcvEnSetupTime = 37
N2.C1.S05: rcvenoffset delta = 37
N2.C1.S05: Final txdqoffset / txdqsoffset / rcvenoffset / 30 /  6 /  3
N2: getComplexDqSetupTime defaultOffset = 0
N2: getComplexDqSetupTime = 0
N2.C1.S06: txdqoffset delta = 0, dq invertpiclk = 0
N2: getComplexDqsSetupTime defaultOffset = 40
N2: getComplexDqsSetupTime = 40
N2.C1.S06: txdqsoffset delta = 40
N2: getComplexRcvEnSetupTime defaultOffset = 37
N2: getComplexRcvEnSetupTime = 37
N2.C1.S06: rcvenoffset delta = 37
N2.C1.S06: Final txdqoffset / txdqsoffset / rcvenoffset / 60 / 36 / 33
N2: getComplexDqSetupTime defaultOffset = 0
N2: getComplexDqSetupTime = 0
N2.C1.S07: txdqoffset delta = 0, dq invertpiclk = 0
N2: getComplexDqsSetupTime defaultOffset = 40
N2: getComplexDqsSetupTime = 40
N2.C1.S07: txdqsoffset delta = 40
N2: getComplexRcvEnSetupTime defaultOffset = 37
N2: getComplexRcvEnSetupTime = 37
N2.C1.S07: rcvenoffset delta = 37
N2.C1.S07: Final txdqoffset / txdqsoffset / rcvenoffset / 27 /  3 /  0
N2: getComplexDqSetupTime defaultOffset = 0
N2: getComplexDqSetupTime = 0
N2.C1.S08: txdqoffset delta = 0, dq invertpiclk = 3
N2: getComplexDqsSetupTime defaultOffset = 40
N2: getComplexDqsSetupTime = 40
N2.C1.S08: txdqsoffset delta = 40
N2: getComplexRcvEnSetupTime defaultOffset = 37
N2: getComplexRcvEnSetupTime = 37
N2.C1.S08: rcvenoffset delta = 37
N2.C1.S08: Final txdqoffset / txdqsoffset / rcvenoffset /  0 / 40 / 37

N4.C0: rxVref = 0x5F
N6.C2: vmse_wr_turnaround = 0x7 
N0.C0: InitHostVmseCfg
N4.C1: rxVref = 0x5F
N6: HsxInitDdrioInterface
N0.C0: vmse_wr_turnaround = 0x7 
N4: HsxVmseCompInit
N6.C0: rxVref = 0x5F
Checkpoint Code: Socket 0, 0xB6, 0x01, 0x0000
N2: SetupJckSmbCfg: JCK VLINFREQ set to: 0x820F1028
N4: VmseCrossoverCalib
N4: Enable xovercal
N4: vmse_modes =          1,  0
N4.C0: piDelay CMDn  CMDs  CTL  CKE  CLK   0  1  2  3  4  5  6  7  8  9 10 11 12 13 14 15 16 17
          0       0     0    0    0    0   1  1  1  1  0  1  1  1  0  1  1  1  1  0  1  1  1  0 
          1       0     0    0    0    0   1  1  1  1  1  1  1  1  0  1  1  1  1  1  1  1  1  0 
          2       0     0    1    0    0   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
          3       0     0    1    0    0   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
          4       0     0    1    1    0   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
          5       0     0    1    1    0   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
          6       0     0    1    1    0   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
          7       0     0    1    1    0   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
          8       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
          9       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         10       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         11       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         12       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         13       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         14       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         15       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         16       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         17       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         18       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         19       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         20       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         21       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         22       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         23       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         24       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         25       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         26       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         27       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         28       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         29       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         30       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         31       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         32       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         33       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         34       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         35       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         36       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         37       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         38       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         39       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         40       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         41       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         42       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         43       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         44       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         45       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         46       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         47       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         48       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         49       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         50       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         51       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         52       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         53       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         54       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         55       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         56       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         57       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         58       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         59       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         60       0     0    1    1    1   0  1  1  1  1  1  1  1  1  0  1  1  1  1  1  1  1  1 
         61       0     0    1    1    1   X  0  1  1  1  1  1  1  1  X  0  1  1  1  1  1  1  1 
         62       0     0    1    1    1   X  X  1  1  1  1  1  1  1  X  X  1  1  1  1  1  1  1 
         63       0     0    1    1    1   X  X  1  1  1  1  1  0  1  X  X  1  1  1  1  1  0  1 
N4.C0: setting ddrcrinvertpiclk
          0       0     0    1    1    1   X  X  0  0  1  1  0  X  1  X  X  0  0  1  1  0  X  1 
          1       0     0    1    1    1   X  X  0  0  1  0  0  X  1  X  X  0  0  1  0  0  X  1 
          2       0     0    1    1    1   X  X  0  0  0  X  0  X  1  X  X  0  0  0  X  0  X  1 
          3       0     0    0    1    1   X  X  0  0  X  X  0  X  0  X  X  0  0  X  X  0  X  0 
          4       0     0    X    1    1   X  X  0  0  X  X  0  X  X  X  X  0  0  X  X  0  X  X 
          5       0     0    X    0    1   X  X  0  0  X  X  0  X  X  X  X  0  0  X  X  0  X  X 
          6       0     0    X    X    1   X  X  0  0  X  X  0  X  X  X  X  0  0  X  X  0  X  X 
          7       0     0    X    X    1   X  X  0  0  X  X  0  X  X  X  X  0  0  X  X  0  X  X 
          8       0     0    X    X    1   X  X  0  0  X  X  0  X  X  X  X  0  0  X  X  0  X  X 
          9       0     0    X    X    1   X  X  0  0  X  X  0  X  X  X  X  0  0  X  X  0  X  X 
         10       0     0    X    X    0   X  X  0  0  X  X  0  X  X  X  X  0  0  X  X  0  X  X 
         11       0     0    X    X    X   X  X  0  0  X  X  0  X  X  X  X  0  0  X  X  0  X  X 
         12       0     0    X    X    X   X  X  0  0  X  X  0  X  X  X  X  0  0  X  X  0  X  X 
         13       0     0    X    X    X   X  X  0  0  X  X  0  X  X  X  X  0  0  X  X  0  X  X 
         14       0     0    X    X    X   X  X  0  0  X  X  0  X  X  X  X  0  0  X  X  0  X  X 
         15       0     0    X    X    X   X  X  0  0  X  X  0  X  X  X  X  0  0  X  X  0  X  X 
         16       0     0    X    X    X   X  X  0  0  X  X  0  X  X  X  X  0  0  X  X  0  X  X 
         17       0     0    X    X    X   X  X  0  0  X  X  0  X  X  X  X  0  0  X  X  0  X  X 
         18       0     0    X    X    X   X  X  0  0  X  X  0  X  X  X  X  0  0  X  X  0  X  X 
         19       0     0    X    X    X   X  X  0  0  X  X  0  X  X  X  X  0  0  X  X  0  X  X 
         20       0     0    X    X    X   X  X  0  0  X  X  0  X  X  X  X  0  0  X  X  0  X  X 
         21       0     0    X    X    X   X  X  0  0  X  X  0  X  X  X  X  0  0  X  X  0  X  X 
         22       0     0    X    X    X   X  X  0  0  X  X  0  X  X  X  X  0  0  X  X  0  X  X 
         23       0     0    X    X    X   X  X  0  0  X  X  0  X  X  X  X  0  0  X  X  0  X  X 
         24       0     0    X    X    X   X  X  0  0  X  X  0  X  X  X  X  0  0  X  X  0  X  X 
         25       0     0    X    X    X   X  X  0  0  X  X  0  X  X  X  X  0  0  X  X  0  X  X 
         26       0     0    X    X    X   X  X  0  0  X  X  0  X  X  X  X  0  0  X  X  0  X  X 
         27       0     0    X    X    X   X  X  0  0  X  X  0  X  X  X  X  0  0  X  X  0  X  X 
         28       0     0    X    X    X   X  X  0  0  X  X  0  X  X  X  X  0  0  X  X  0  X  X 
         29       0     0    X    X    X   X  X  0  0  X  X  0  X  X  X  X  0  0  X  X  0  X  X 
         30       0     0    X    X    X   X  X  0  0  X  X  0  X  X  X  X  0  0  X  X  0  X  X 
         31       0     0    X    X    X   X  X  0  0  X  X  0  X  X  X  X  0  0  X  X  0  X  X 
         32       0     0    X    X    X   X  X  0  0  X  X  0  X  X  X  X  0  0  X  X  0  X  X 
         33       0     0    X    X    X   X  X  0  0  X  X  0  X  X  X  X  0  0  X  X  0  X  X 
         34       0     0    X    X    X   X  X  0  0  X  X  0  X  X  X  X  0  0  X  X  0  X  X 
         35       0     0    X    X    X   X  X  0  0  X  X  0  X  X  X  X  0  0  X  X  0  X  X 
         36       0     0    X    X    X   X  X  0  0  X  X  0  X  X  X  X  0  0  X  X  0  X  X 
         37       0     0    X    X    X   X  X  0  0  X  X  0  X  X  X  X  0  0  X  X  0  X  X 
         38       0     0    X    X    X   X  X  0  0  X  X  0  X  X  X  X  0  0  X  X  0  X  X 
         39       0     0    X    X    X   X  X  0  0  X  X  0  X  X  X  X  0  0  X  X  0  X  X 
         40       0     0    X    X    X   X  X  0  0  X  X  0  X  X  X  X  0  0  X  X  0  X  X 
         41       0     0    X    X    X   X  X  0  0  X  X  0  X  X  X  X  0  0  X  X  0  X  X 
         42       0     0    X    X    X   X  X  0  0  X  X  0  X  X  X  X  0  0  X  X  0  X  X 
         43       0     0    X    X    X   X  X  0  0  X  X  0  X  X  X  X  0  0  X  X  0  X  X 
         44       0     0    X    X    X   X  X  0  0  X  X  0  X  X  X  X  0  0  X  X  0  X  X 
         45       0     0    X    X    X   X  X  0  0  X  X  0  X  X  X  X  0  0  X  X  0  X  X 
         46       0     0    X    X    X   X  X  0  0  X  X  0  X  X  X  X  0  0  X  X  0  X  X 
         47       0     0    X    X    X   X  X  0  0  X  X  0  X  X  X  X  0  0  X  X  0  X  X 
         48       0     0    X    X    X   X  X  0  0  X  X  0  X  X  X  X  0  0  X  X  0  X  X 
         49       0     0    X    X    X   X  X  0  0  X  X  0  X  X  X  X  0  0  X  X  0  X  X 
         50       0     0    X    X    X   X  X  0  0  X  X  0  X  X  X  X  0  0  X  X  0  X  X 
         51       0     0    X    X    X   X  X  0  0  X  X  0  X  X  X  X  0  0  X  X  0  X  X 
         52       0     0    X    X    X   X  X  0  0  X  X  0  X  X  X  X  0  0  X  X  0  X  X 
         53       0     0    X    X    X   X  X  0  0  X  X  0  X  X  X  X  0  0  X  X  0  X  X 
         54       0     0    X    X    X   X  X  0  0  X  X  0  X  X  X  X  0  0  X  X  0  X  X 
         55       0     0    X    X    X   X  X  0  0  X  X  0  X  X  X  X  0  0  X  X  0  X  X 
         56       0     0    X    X    X   X  X  0  0  X  X  0  X  X  X  X  0  0  X  X  0  X  X 
         57       0     0    X    X    X   X  X  0  0  X  X  0  X  X  X  X  0  0  X  X  0  X  X 
         58       0     0    X    X    X   X  X  0  0  X  X  0  X  X  X  X  0  0  X  X  0  X  X 
         59       0     0    X    X    X   X  X  0  0  X  X  0  X  X  X  X  0  0  X  X  0  X  X 
         60       0     0    X    X    X   X  X  0  0  X  X  0  X  X  X  X  0  0  X  X  0  X  X 
         61       0     0    X    X    X   X  X  0  0  X  X  0  X  X  X  X  0  0  X  X  0  X  X 
         62       0     0    X    X    X   X  X  1  0  X  X  0  X  X  X  X  1  0  X  X  0  X  X 
         63       0     0    X    X    X   X  X  1  0  X  X  1  X  X  X  X  1  0  X  X  1  X  X 
N4.C0: CMD-N xovercal offset = 0
N4.C0: CMD-S xovercal offset = 0
N4.C0: CTL xovercal offset   = 3
N4.C0: CKE xovercal offset   = 5
N4.C0: CLK xovercal offset   = 10
N4.C0.S18: STROBE                     0   1   2   3   4   5   6   7   8   9  10  11  12  13  14  15  16  17
N4.C0.S18: Rec En xovercal offset =  60  61   0   0   2   1   0  63   3  60  61   0   0   2   1   0  63   3 
N4.C0.S18: Tx Dqs xovercal offset =  60  63   0   0  63  63   0  63  63  63  63   0   0  63  63   0  63  63 
N4.C0.S18: Tx Dq xovercal offset  =  60  61   0   0   2   1   0  63   3  60  61   0   0   2   1   0  63   3 
N4.C0:         CMDn  CMDs  CTL  CKE  CLK   0  1  2  3  4  5  6  7  8
N4.C0: offsets:  0     0     3N4: getComplexCkeSetupTime defaultOffset = 98
N4: getComplexCkeSetupTime = 98
    5   10
Ctl Offsets Delta / final ctl offset / final cke offset /  98  /  37  /   7
Cke invertpiclk / Ctl invertpiclk / 0x0  /  0x0
N4: getComplexClkSetupTime defaultOffset = 0
N4: getComplexClkSetupTime = 0
ClkSetupTime = 10
N4: getComplexDqSetupTime defaultOffset = 0
N4: getComplexDqSetupTime = 0
N4.C0.S00: txdqoffset delta = 0, dq invertpiclk = 0
N4: getComplexDqsSetupTime defaultOffset = 40
N4: getComplexDqsSetupTime = 40
N4.C0.S00: txdqsoffset delta = 40
N4: getComplexRcvEnSetupTime defaultOffset = 37
N4: getComplexRcvEnSetupTime = 37
N4.C0.S00: rcvenoffset delta = 37
N4.C0.S00: Final txdqoffset / txdqsoffset / rcvenoffset / 28 /  4 /  1
N4: getComplexDqSetupTime defaultOffset = 0
N4: getComplexDqSetupTime = 0
N4.C0.S01: txdqoffset delta = 0, dq invertpiclk = 0
N4: getComplexDqsSetupTime defaultOffset = 40
N4: getComplexDqsSetupTime = 40
N4.C0.S01: txdqsoffset delta = 40
N4: getComplexRcvEnSetupTime defaultOffset = 37
N4: getComplexRcvEnSetupTime = 37
N4.C0.S01: rcvenoffset delta = 37
N4.C0.S01: Final txdqoffset / txdqsoffset / rcvenoffset / 61 / 37 / 34
N4: getComplexDqSetupTime defaultOffset = 0
N4: getComplexDqSetupTime = 0
N4.C0.S02: txdqoffset delta = 0, dq invertpiclk = 3
N4: getComplexDqsSetupTime defaultOffset = 40
N4: getComplexDqsSetupTime = 40
N4.C0.S02: txdqsoffset delta = 40
N4: getComplexRcvEnSetupTime defaultOffset = 37
N4: getComplexRcvEnSetupTime = 37
N4.C0.S02: rcvenoffset delta = 37
N4.C0.S02: Final txdqoffset / txdqsoffset / rcvenoffset / 32 /  8 /  5
N4: getComplexDqSetupTime defaultOffset = 0
N4: getComplexDqSetupTime = 0
N4.C0.S03: txdqoffset delta = 0, dq invertpiclk = 3
N4: getComplexDqsSetupTime defaultOffset = 40
N4: getComplexDqsSetupTime = 40
N4.C0.S03: txdqsoffset delta = 40
N4: getComplexRcvEnSetupTime defaultOffset = 37
N4: getComplexRcvEnSetupTime = 37
N4.C0.S03: rcvenoffset delta = 37
N4.C0.S03: Final txdqoffset / txdqsoffset / rcvenoffset /  0 / 40 / 37
N4: getComplexDqSetupTime defaultOffset = 0
N4: getComplexDqSetupTime = 0
N4.C0.S04: txdqoffset delta = 0, dq invertpiclk = 3
N4: getComplexDqsSetupTime defaultOffset = 40
N4: getComplexDqsSetupTime = 40
N4.C0.S04: txdqsoffset delta = 40
N4: getComplexRcvEnSetupTime defaultOffset = 37
N4: getComplexRcvEnSetupTime = 37
N4.C0.S04: rcvenoffset delta = 37
N4.C0.S04: Final txdqoffset / txdqsoffset / rcvenoffset / 34 / 10 /  7
N4: getComplexDqSetupTime defaultOffset = 0
N4: getComplexDqSetupTime = 0
N4.C0.S05: txdqoffset delta = 0, dq invertpiclk = 3
N4: getComplexDqsSetupTime defaultOffset = 40
N4: getComplexDqsSetupTime = 40
N4.C0.S05: txdqsoffset delta = 40
N4: getComplexRcvEnSetupTime defaultOffset = 37
N4: getComplexRcvEnSetupTime = 37
N4.C0.S05: rcvenoffset delta = 37
N4.C0.S05: Final txdqoffset / txdqsoffset / rcvenoffset /  1 / 41 / 38
N4: getComplexDqSetupTime defaultOffset = 0
N4: getComplexDqSetupTime = 0
N4.C0.S06: txdqoffset delta = 0, dq invertpiclk = 3
N4: getComplexDqsSetupTime defaultOffset = 40
N4: getComplexDqsSetupTime = 40
N4.C0.S06: txdqsoffset delta = 40
N4: getComplexRcvEnSetupTime defaultOffset = 37
N4: getComplexRcvEnSetupTime = 37
N4.C0.S06: rcvenoffset delta = 37
N4.C0.S06: Final txdqoffset / txdqsoffset / rcvenoffset / 32 /  8 /  5
N4: getComplexDqSetupTime defaultOffset = 0
N4: getComplexDqSetupTime = 0
N4.C0.S07: txdqoffset delta = 0, dq invertpiclk = 0
N4: getComplexDqsSetupTime defaultOffset = 40
N4: getComplexDqsSetupTime = 40
N4.C0.S07: txdqsoffset delta = 40
N4: getComplexRcvEnSetupTime defaultOffset = 37
N4: getComplexRcvEnSetupTime = 37
N4.C0.S07: rcvenoffset delta = 37
N4.C0.S07: Final txdqoffset / txdqsoffset / rcvenoffset / 63 / 39 / 36
N4: getComplexDqSetupTime defaultOffset = 0
N4: getComplexDqSetupTime = 0
N4.C0.S08: txdqoffset delta = 0, dq invertpiclk = 3
N4: getComplexDqsSetupTime defaultOffset = 40
N4: getComplexDqsSetupTime = 40
N4.C0.S08: txdqsoffset delta = 40
N4: getComplexRcvEnSetupTime defaultOffset = 37
N4: getComplexRcvEnSetupTime = 37
N4.C0.S08: rcvenoffset delta = 37
N4.C0.S08: Final txdqoffset / txdqsoffset / rcvenoffset / 35 / 11 /  8

N4: vmse_modes =          1,  0
N4.C1: piDelay CMDn  CMDs  CTL  CKE  CLK   0  1  2  3  4  5  6  7  8  9 10 11 12 13 14 15 16 17
          0       0     0    1    1    0   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
          1       0     0    1    1    0   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
          2       0     0    1    1    0   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
          3       0     0    1    1    0   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
          4       0     0    1    1    0   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
          5       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
          6       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
          7       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
          8       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
          9       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         10       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         11       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         12       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         13       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         14       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         15       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         16       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         17       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         18       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         19       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         20       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         21       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         22       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         23       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         24       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         25       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         26       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         27       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         28       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         29       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         30       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         31       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         32       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         33       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         34       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         35       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         36       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         37       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         38       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         39       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         40       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         41       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         42       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         43       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         44       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         45       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         46       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         47       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         48       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         49       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         50       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         51       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         52       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         53       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         54       0     0    1    1    1   0  1  1  1  1  1  1  1  1  0  1  1  1  1  1  1  1  1 
         55       0     0    1    1    1   X  1  1  1  1  1  1  1  1  X  1  1  1  1  1  1  1  1 
         56       0     0    1    1    1   X  1  1  1  1  1  1  1  1  X  1  1  1  1  1  1  1  1 
         57       0     0    1    1    1   X  0  1  1  1  1  1  1  1  X  0  1  1  1  1  1  1  1 
         58       0     0    1    1    1   X  X  1  1  1  1  1  1  1  X  X  1  1  1  1  1  1  1 
         59       0     0    1    1    1   X  X  0  1  1  1  1  0  1  X  X  0  1  1  1  1  0  1 
         60       0     0    1    1    1   X  X  X  1  1  1  0  X  1  X  X  X  1  1  1  0  X  1 
         61       0     0    1    1    1   X  X  X  1  1  1  X  X  1  X  X  X  1  1  1  X  X  1 
         62       0     0    1    1    1   X  X  X  0  1  0  X  X  1  X  X  X  0  1  0  X  X  1 
         63       0     0    1    1    1   X  X  X  X  1  X  X  X  1  X  X  X  X  1  X  X  X  1 
N4.C1: setting ddrcrinvertpiclk
          0       0     0    0    1    1   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
          1       0     0    0    1    1   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
          2       0     0    0    0    1   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
          3       0     0    0    X    1   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
          4       0     0    0    X    1   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
          5       0     0    0    X    1   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
          6       0     0    0    X    1   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
          7       0     0    0    X    0   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
          8       0     0    0    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
          9       0     0    0    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         10       0     0    0    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         11       0     0    0    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         12       0     0    0    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         13       0     0    0    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         14       0     0    0    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         15       0     0    0    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         16       0     0    0    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         17       0     0    0    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         18       0     0    0    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         19       0     0    0    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         20       0     0    0    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         21       0     0    0    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         22       0     0    0    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         23       0     0    0    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         24       0     0    0    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         25       0     0    0    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         26       0     0    0    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         27       0     0    0    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         28       0     0    0    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         29       0     0    0    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         30       0     0    0    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         31       0     0    0    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         32       0     0    0    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         33       0     0    0    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         34       0     0    0    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         35       0     0    0    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         36       0     0    0    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         37       0     0    0    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         38       0     0    0    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         39       0     0    0    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         40       0     0    0    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         41       0     0    0    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         42       0     0    0    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         43       0     0    0    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         44       0     0    0    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         45       0     0    0    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         46       0     0    0    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         47       0     0    0    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         48       0     0    0    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         49       0     0    0    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         50       0     0    0    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         51       0     0    0    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         52       0     0    0    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         53       0     0    0    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         54       0     0    0    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         55       0     0    0    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         56       0     0    0    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         57       0     0    0    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         58       0     0    0    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         59       0     0    0    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         60       0     0    0    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         61       0     0    0    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         62       0     0    0    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         63       0     0    0    X    X   X  X  X  X  1  X  X  X  1  X  X  X  X  1  X  X  X  1 
N4.C1: CMD-N xovercal offset = 0
N4.C1: CMD-S xovercal offset = 0
N4.C1: CTL xovercal offset   = 0
N4.C1: CKE xovercal offset   = 2
N4.C1: CLK xovercal offset   = 7
N4.C1.S18: STROBE                     0   1   2   3   4   5   6   7   8   9  10  11  12  13  14  15  16  17
N4.C1.S18: Rec En xovercal offset =  54  57  59  62   0  62  60  59   0  54  57  59  62   0  62  60  59   0 
N4.C1.S18: Tx Dqs xovercal offset =  54  63  63  63   0  63  63  63   0  63  63  63  63   0  63  63  63   0 
N4.C1.S18: Tx Dq xovercal offset  =  54  57  59  62   0  62  60  59   0  54  57  59  62   0  62  60  59   0 
N4.C1:         CMDn  CMDs  CTL  CKE  CLK   0  1  2  3  4  5  6  7  8
N4.C1: offsets:  0     0     0N4: getComplexCkeSetupTime defaultOffset = 98
N4: getComplexCkeSetupTime = 98
    2    7
Ctl Offsets Delta / final ctl offset / final cke offset /  98  /   2  /  36
Cke invertpiclk / Ctl invertpiclk / 0x0  /  0x0
N4: getComplexClkSetupTime defaultOffset = 0
N4: getComplexClkSetupTime = 0
ClkSetupTime = 39
N4: getComplexDqSetupTime defaultOffset = 0
N4: getComplexDqSetupTime = 0
N4.C1.S00: txdqoffset delta = 0, dq invertpiclk = 0
N4: getComplexDqsSetupTime defaultOffset = 40
N4: getComplexDqsSetupTime = 40
N4.C1.S00: txdqsoffset delta = 40
N4: getComplexRcvEnSetupTime defaultOffset = 37
N4: getComplexRcvEnSetupTime = 37
N4.C1.S00: rcvenoffset delta = 37
N4.C1.S00: Final txdqoffset / txdqsoffset / rcvenoffset / 54 / 30 / 27
N4: getComplexDqSetupTime defaultOffset = 0
N4: getComplexDqSetupTime = 0
N4.C1.S01: txdqoffset delta = 0, dq invertpiclk = 0
N4: getComplexDqsSetupTime defaultOffset = 40
N4: getComplexDqsSetupTime = 40
N4.C1.S01: txdqsoffset delta = 40
N4: getComplexRcvEnSetupTime defaultOffset = 37
N4: getComplexRcvEnSetupTime = 37
N4.C1.S01: rcvenoffset delta = 37
N4.C1.S01: Final txdqoffset / txdqsoffset / rcvenoffset / 25 /  1 / 62
N4: getComplexDqSetupTime defaultOffset = 0
N4: getComplexDqSetupTime = 0
N4.C1.S02: txdqoffset delta = 0, dq invertpiclk = 0
N4: getComplexDqsSetupTime defaultOffset = 40
N4: getComplexDqsSetupTime = 40
N4.C1.S02: txdqsoffset delta = 40
N4: getComplexRcvEnSetupTime defaultOffset = 37
N4: getComplexRcvEnSetupTime = 37
N4.C1.S02: rcvenoffset delta = 37
N4.C1.S02: Final txdqoffset / txdqsoffset / rcvenoffset / 59 / 35 / 32
N4: getComplexDqSetupTime defaultOffset = 0
N4: getComplexDqSetupTime = 0
N4.C1.S03: txdqoffset delta = 0, dq invertpiclk = 0
N4: getComplexDqsSetupTime defaultOffset = 40
N4: getComplexDqsSetupTime = 40
N4.C1.S03: txdqsoffset delta = 40
N4: getComplexRcvEnSetupTime defaultOffset = 37
N4: getComplexRcvEnSetupTime = 37
N4.C1.S03: rcvenoffset delta = 37
N4.C1.S03: Final txdqoffset / txdqsoffset / rcvenoffset / 30 /  6 /  3
N4: getComplexDqSetupTime defaultOffset = 0
N4: getComplexDqSetupTime = 0
N4.C1.S04: txdqoffset delta = 0, dq invertpiclk = 3
N4: getComplexDqsSetupTime defaultOffset = 40
N4: getComplexDqsSetupTime = 40
N4.C1.S04: txdqsoffset delta = 40
N4: getComplexRcvEnSetupTime defaultOffset = 37
N4: getComplexRcvEnSetupTime = 37
N4.C1.S04: rcvenoffset delta = 37
N4.C1.S04: Final txdqoffset / txdqsoffset / rcvenoffset /  0 / 40 / 37
N4: getComplexDqSetupTime defaultOffset = 0
N4: getComplexDqSetupTime = 0
N4.C1.S05: txdqoffset delta = 0, dq invertpiclk = 0
N4: getComplexDqsSetupTime defaultOffset = 40
N4: getComplexDqsSetupTime = 40
N4.C1.S05: txdqsoffset delta = 40
N4: getComplexRcvEnSetupTime defaultOffset = 37
N4: getComplexRcvEnSetupTime = 37
N4.C1.S05: rcvenoffset delta = 37
N4.C1.S05: Final txdqoffset / txdqsoffset / rcvenoffset / 30 /  6 /  3
N4: getComplexDqSetupTime defaultOffset = 0
N4: getComplexDqSetupTime = 0
N4.C1.S06: txdqoffset delta = 0, dq invertpiclk = 0
N4: getComplexDqsSetupTime defaultOffset = 40
N4: getComplexDqsSetupTime = 40
N4.C1.S06: txdqsoffset delta = 40
N4: getComplexRcvEnSetupTime defaultOffset = 37
N4: getComplexRcvEnSetupTime = 37
N4.C1.S06: rcvenoffset delta = 37
N4.C1.S06: Final txdqoffset / txdqsoffset / rcvenoffset / 60 / 36 / 33
N4: getComplexDqSetupTime defaultOffset = 0
N4: getComplexDqSetupTime = 0
N4.C1.S07: txdqoffset delta = 0, dq invertpiclk = 0
N4: getComplexDqsSetupTime defaultOffset = 40
N4: getComplexDqsSetupTime = 40
N4.C1.S07: txdqsoffset delta = 40
N4: getComplexRcvEnSetupTime defaultOffset = 37
N4: getComplexRcvEnSetupTime = 37
N4.C1.S07: rcvenoffset delta = 37
N4.C1.S07: Final txdqoffset / txdqsoffset / rcvenoffset / 27 /  3 /  0
N4: getComplexDqSetupTime defaultOffset = 0
N4: getComplexDqSetupTime = 0
N4.C1.S08: txdqoffset delta = 0, dq invertpiclk = 3
N4: getComplexDqsSetupTime defaultOffset = 40
N4: getComplexDqsSetupTime = 40
N4.C1.S08: txdqsoffset delta = 40
N4: getComplexRcvEnSetupTime defaultOffset = 37
N4: getComplexRcvEnSetupTime = 37
N4.C1.S08: rcvenoffset delta = 37
N4.C1.S08: Final txdqoffset / txdqsoffset / rcvenoffset /  0 / 40 / 37

N6.C1: rxVref = 0x5F
N0.C2: InitHostVmseCfg
N2: SetupJckSmbCfg: PLL is locked.
N6: HsxVmseCompInit
N0.C2: vmse_wr_turnaround = 0x7 
N2.C0: SetupJckSmbCfg: dlyFrms = 15
N6: VmseCrossoverCalib
N6: Enable xovercal
N6: vmse_modes =          1,  0
N6.C0: piDelay CMDn  CMDs  CTL  CKE  CLK   0  1  2  3  4  5  6  7  8  9 10 11 12 13 14 15 16 17
          0       0     0    1    0    0   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
          1       0     0    1    1    0   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
          2       0     0    1    1    0   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
          3       0     0    1    1    0   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
          4       0     0    1    1    0   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
          5       0     0    1    1    0   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
          6       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
          7       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
          8       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
          9       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         10       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         11       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         12       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         13       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         14       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         15       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         16       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         17       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         18       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         19       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         20       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         21       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         22       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         23       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         24       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         25       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         26       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         27       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         28       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         29       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         30       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         31       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         32       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         33       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         34       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         35       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         36       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         37       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         38       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         39       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         40       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         41       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         42       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         43       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         44       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         45       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         46       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         47       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         48       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         49       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         50       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         51       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         52       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         53       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         54       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         55       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         56       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         57       0     0    1    1    1   0  1  1  1  1  1  1  1  1  0  1  1  1  1  1  1  1  1 
         58       0     0    1    1    1   X  0  1  1  1  1  1  1  1  X  0  1  1  1  1  1  1  1 
         59       0     0    1    1    1   X  X  1  1  1  1  1  1  1  X  X  1  1  1  1  1  1  1 
         60       0     0    1    1    1   X  X  0  1  1  1  1  1  1  X  X  0  1  1  1  1  1  1 
         61       0     0    1    1    1   X  X  X  1  1  1  0  0  1  X  X  X  1  1  1  0  0  1 
         62       0     0    1    1    1   X  X  X  0  1  1  X  X  1  X  X  X  0  1  1  X  X  1 
         63       0     0    1    1    1   X  X  X  X  1  0  X  X  1  X  X  X  X  1  0  X  X  1 
N6.C0: setting ddrcrinvertpiclk
          0       0     0    0    1    1   X  X  X  X  1  X  X  X  1  X  X  X  X  1  X  X  X  1 
          1       0     0    0    1    1   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
          2       0     0    0    1    1   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
          3       0     0    0    0    1   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
          4       0     0    0    X    1   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
          5       0     0    0    X    1   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
          6       0     0    0    X    1   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
          7       0     0    0    X    0   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
          8       0     0    0    X    X   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
          9       0     0    0    X    X   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
         10       0     0    0    X    X   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
         11       0     0    0    X    X   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
         12       0     0    0    X    X   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
         13       0     0    0    X    X   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
         14       0     0    0    X    X   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
         15       0     0    0    X    X   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
         16       0     0    0    X    X   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
         17       0     0    0    X    X   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
         18       0     0    0    X    X   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
         19       0     0    0    X    X   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
         20       0     0    0    X    X   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
         21       0     0    0    X    X   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
         22       0     0    0    X    X   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
         23       0     0    0    X    X   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
         24       0     0    0    X    X   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
         25       0     0    0    X    X   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
         26       0     0    0    X    X   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
         27       0     0    0    X    X   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
         28       0     0    0    X    X   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
         29       0     0    0    X    X   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
         30       0     0    0    X    X   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
         31       0     0    0    X    X   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
         32       0     0    0    X    X   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
         33       0     0    0    X    X   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
         34       0     0    0    X    X   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
         35       0     0    0    X    X   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
         36       0     0    0    X    X   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
         37       0     0    0    X    X   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
         38       0     0    0    X    X   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
         39       0     0    0    X    X   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
         40       0     0    0    X    X   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
         41       0     0    0    X    X   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
         42       0     0    0    X    X   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
         43       0     0    0    X    X   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
         44       0     0    0    X    X   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
         45       0     0    0    X    X   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
         46       0     0    0    X    X   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
         47       0     0    0    X    X   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
         48       0     0    0    X    X   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
         49       0     0    0    X    X   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
         50       0     0    0    X    X   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
         51       0     0    0    X    X   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
         52       0     0    0    X    X   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
         53       0     0    0    X    X   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
         54       0     0    0    X    X   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
         55       0     0    0    X    X   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
         56       0     0    0    X    X   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
         57       0     0    0    X    X   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
         58       0     0    0    X    X   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
         59       0     0    0    X    X   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
         60       0     0    0    X    X   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
         61       0     0    0    X    X   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
         62       0     0    0    X    X   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
         63       0     0    0    X    X   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
N6.C0: CMD-N xovercal offset = 0
N6.C0: CMD-S xovercal offset = 0
N6.C0: CTL xovercal offset   = 0
N6.C0: CKE xovercal offset   = 3
N6.C0: CLK xovercal offset   = 7
N6.C0.S18: STROBE                     0   1   2   3   4   5   6   7   8   9  10  11  12  13  14  15  16  17
N6.C0.S18: Rec En xovercal offset =  57  58  60  62   1  63  61  61   1  57  58  60  62   1  63  61  61   1 
N6.C0.S18: Tx Dqs xovercal offset =  57  63  63  63  63  63  63  63  63  63  63  63  63  63  63  63  63  63 
N6.C0.S18: Tx Dq xovercal offset  =  57  58  60  62   1  63  61  61   1  57  58  60  62   1  63  61  61   1 
N6.C0:         CMDn  CMDs  CTL  CKE  CLK   0  1  2  3  4  5  6  7  8
N6.C0: offsets:  0     0     0N6: getComplexCkeSetupTime defaultOffset = 98
N6: getComplexCkeSetupTime = 98
    3    7
Ctl Offsets Delta / final ctl offset / final cke offset /  98  /  34  /   5
Cke invertpiclk / Ctl invertpiclk / 0x0  /  0x0
N6: getComplexClkSetupTime defaultOffset = 0
N6: getComplexClkSetupTime = 0
ClkSetupTime = 7
N6: getComplexDqSetupTime defaultOffset = 0
N6: getComplexDqSetupTime = 0
N6.C0.S00: txdqoffset delta = 0, dq invertpiclk = 0
N6: getComplexDqsSetupTime defaultOffset = 40
N6: getComplexDqsSetupTime = 40
N6.C0.S00: txdqsoffset delta = 40
N6: getComplexRcvEnSetupTime defaultOffset = 37
N6: getComplexRcvEnSetupTime = 37
N6.C0.S00: rcvenoffset delta = 37
N6.C0.S00: Final txdqoffset / txdqsoffset / rcvenoffset / 25 /  1 / 62
N6: getComplexDqSetupTime defaultOffset = 0
N6: getComplexDqSetupTime = 0
N6.C0.S01: txdqoffset delta = 0, dq invertpiclk = 0
N6: getComplexDqsSetupTime defaultOffset = 40
N6: getComplexDqsSetupTime = 40
N6.C0.S01: txdqsoffset delta = 40
N6: getComplexRcvEnSetupTime defaultOffset = 37
N6: getComplexRcvEnSetupTime = 37
N6.C0.S01: rcvenoffset delta = 37
N6.C0.S01: Final txdqoffset / txdqsoffset / rcvenoffset / 58 / 34 / 31
N6: getComplexDqSetupTime defaultOffset = 0
N6: getComplexDqSetupTime = 0
N6.C0.S02: txdqoffset delta = 0, dq invertpiclk = 0
N6: getComplexDqsSetupTime defaultOffset = 40
N6: getComplexDqsSetupTime = 40
N6.C0.S02: txdqsoffset delta = 40
N6: getComplexRcvEnSetupTime defaultOffset = 37
N6: getComplexRcvEnSetupTime = 37
N6.C0.S02: rcvenoffset delta = 37
N6.C0.S02: Final txdqoffset / txdqsoffset / rcvenoffset / 28 /  4 /  1
N6: getComplexDqSetupTime defaultOffset = 0
N6: getComplexDqSetupTime = 0
N6.C0.S03: txdqoffset delta = 0, dq invertpiclk = 0
N6: getComplexDqsSetupTime defaultOffset = 40
N6: getComplexDqsSetupTime = 40
N6.C0.S03: txdqsoffset delta = 40
N6: getComplexRcvEnSetupTime defaultOffset = 37
N6: getComplexRcvEnSetupTime = 37
N6.C0.S03: rcvenoffset delta = 37
N6.C0.S03: Final txdqoffset / txdqsoffset / rcvenoffset / 62 / 38 / 35
N6: getComplexDqSetupTime defaultOffset = 0
N6: getComplexDqSetupTime = 0
N6.C0.S04: txdqoffset delta = 0, dq invertpiclk = 3
N6: getComplexDqsSetupTime defaultOffset = 40
N6: getComplexDqsSetupTime = 40
N6.C0.S04: txdqsoffset delta = 40
N6: getComplexRcvEnSetupTime defaultOffset = 37
N6: getComplexRcvEnSetupTime = 37
N6.C0.S04: rcvenoffset delta = 37
N6.C0.S04: Final txdqoffset / txdqsoffset / rcvenoffset / 33 /  9 /  6
N6: getComplexDqSetupTime defaultOffset = 0
N6: getComplexDqSetupTime = 0
N6.C0.S05: txdqoffset delta = 0, dq invertpiclk = 0
N6: getComplexDqsSetupTime defaultOffset = 40
N6: getComplexDqsSetupTime = 40
N6.C0.S05: txdqsoffset delta = 40
N6: getComplexRcvEnSetupTime defaultOffset = 37
N6: getComplexRcvEnSetupTime = 37
N6.C0.S05: rcvenoffset delta = 37
N6.C0.S05: Final txdqoffset / txdqsoffset / rcvenoffset / 63 / 39 / 36
N6: getComplexDqSetupTime defaultOffset = 0
N6: getComplexDqSetupTime = 0
N6.C0.S06: txdqoffset delta = 0, dq invertpiclk = 0
N6: getComplexDqsSetupTime defaultOffset = 40
N6: getComplexDqsSetupTime = 40
N6.C0.S06: txdqsoffset delta = 40
N6: getComplexRcvEnSetupTime defaultOffset = 37
N6: getComplexRcvEnSetupTime = 37
N6.C0.S06: rcvenoffset delta = 37
N6.C0.S06: Final txdqoffset / txdqsoffset / rcvenoffset / 29 /  5 /  2
N6: getComplexDqSetupTime defaultOffset = 0
N6: getComplexDqSetupTime = 0
N6.C0.S07: txdqoffset delta = 0, dq invertpiclk = 0
N6: getComplexDqsSetupTime defaultOffset = 40
N6: getComplexDqsSetupTime = 40
N6.C0.S07: txdqsoffset delta = 40
N6: getComplexRcvEnSetupTime defaultOffset = 37
N6: getComplexRcvEnSetupTime = 37
N6.C0.S07: rcvenoffset delta = 37
N6.C0.S07: Final txdqoffset / txdqsoffset / rcvenoffset / 61 / 37 / 34
N6: getComplexDqSetupTime defaultOffset = 0
N6: getComplexDqSetupTime = 0
N6.C0.S08: txdqoffset delta = 0, dq invertpiclk = 3
N6: getComplexDqsSetupTime defaultOffset = 40
N6: getComplexDqsSetupTime = 40
N6.C0.S08: txdqsoffset delta = 40
N6: getComplexRcvEnSetupTime defaultOffset = 37
N6: getComplexRcvEnSetupTime = 37
N6.C0.S08: rcvenoffset delta = 37
N6.C0.S08: Final txdqoffset / txdqsoffset / rcvenoffset / 33 /  9 /  6

N6: vmse_modes =          1,  0
N6.C1: piDelay CMDn  CMDs  CTL  CKE  CLK   0  1  2  3  4  5  6  7  8  9 10 11 12 13 14 15 16 17
          0       0     0    1    1    0   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
          1       0     0    1    1    0   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
          2       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
          3       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
          4       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
          5       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
          6       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
          7       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
          8       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
          9       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         10       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         11       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         12       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         13       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         14       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         15       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         16       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         17       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         18       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         19       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         20       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         21       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         22       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         23       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         24       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         25       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         26       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         27       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         28       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         29       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         30       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         31       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         32       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         33       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         34       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         35       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         36       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         37       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         38       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         39       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         40       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         41       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         42       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         43       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         44       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         45       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         46       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         47       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         48       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         49       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         50       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         51       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         52       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         53       0     0    1    1    1   0  1  1  1  1  1  1  1  1  0  1  1  1  1  1  1  1  1 
         54       0     0    1    1    1   X  0  1  1  1  1  1  1  1  X  0  1  1  1  1  1  1  1 
         55       0     0    1    1    1   X  X  1  1  1  1  1  1  1  X  X  1  1  1  1  1  1  1 
         56       0     0    1    1    1   X  X  0  1  1  1  1  0  1  X  X  0  1  1  1  1  0  1 
         57       0     0    1    1    1   X  X  X  1  1  1  1  X  1  X  X  X  1  1  1  1  X  1 
         58       0     0    1    1    1   X  X  X  1  1  1  0  X  1  X  X  X  1  1  1  0  X  1 
         59       0     0    1    1    1   X  X  X  0  1  1  X  X  1  X  X  X  1  1  1  X  X  1 
         60       0     0    1    1    1   X  X  X  X  1  0  X  X  1  X  X  X  0  1  0  X  X  1 
         61       0     0    0    1    1   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         62       0     0    X    1    1   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
         63       0     0    X    0    1   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
N6.C1: setting ddrcrinvertpiclk
          0       0     0    X    X    1   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
          1       0     0    X    X    1   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
          2       0     0    X    X    1   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
          3       0     0    X    X    0   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
          4       0     0    X    X    X   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
          5       0     0    X    X    X   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
          6       0     0    X    X    X   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
          7       0     0    X    X    X   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
          8       0     0    X    X    X   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
          9       0     0    X    X    X   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
         10       0     0    X    X    X   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
         11       0     0    X    X    X   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
         12       0     0    X    X    X   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
         13       0     0    X    X    X   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
         14       0     0    X    X    X   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
         15       0     0    X    X    X   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
         16       0     0    X    X    X   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
         17       0     0    X    X    X   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
         18       0     0    X    X    X   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
         19       0     0    X    X    X   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
         20       0     0    X    X    X   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
         21       0     0    X    X    X   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
         22       0     0    X    X    X   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
         23       0     0    X    X    X   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
         24       0     0    X    X    X   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
         25       0     0    X    X    X   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
         26       0     0    X    X    X   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
         27       0     0    X    X    X   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
         28       0     0    X    X    X   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
         29       0     0    X    X    X   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
         30       0     0    X    X    X   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
         31       0     0    X    X    X   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
         32       0     0    X    X    X   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
         33       0     0    X    X    X   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
         34       0     0    X    X    X   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
         35       0     0    X    X    X   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
         36       0     0    X    X    X   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
         37       0     0    X    X    X   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
         38       0     0    X    X    X   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
         39       0     0    X    X    X   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
         40       0     0    X    X    X   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
         41       0     0    X    X    X   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
         42       0     0    X    X    X   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
         43       0     0    X    X    X   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
         44       0     0    X    X    X   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
         45       0     0    X    X    X   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
         46       0     0    X    X    X   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
         47       0     0    X    X    X   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
         48       0     0    X    X    X   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
         49       0     0    X    X    X   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
         50       0     0    X    X    X   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
         51       0     0    X    X    X   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
         52       0     0    X    X    X   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
         53       0     0    X    X    X   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
         54       0     0    X    X    X   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
         55       0     0    X    X    X   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
         56       0     0    X    X    X   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
         57       0     0    X    X    X   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
         58       0     0    X    X    X   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
         59       0     0    X    X    X   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
         60       0     0    X    X    X   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
         61       0     0    X    X    X   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
         62       0     0    X    X    X   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
         63       0     0    X    X    X   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
N6.C1: CMD-N xovercal offset = 0
N6.C1: CMD-S xovercal offset = 0
N6.C1: CTL xovercal offset   = 61
N6.C1: CKE xovercal offset   = 63
N6.C1: CLK xovercal offset   = 3
N6.C1.S18: STROBE                     0   1   2   3   4   5   6   7   8   9  10  11  12  13  14  15  16  17
N6.C1.S18: Rec En xovercal offset =  53  54  56  59  61  60  58  56  61  53  54  56  60  61  60  58  56  61 
N6.C1.S18: Tx Dqs xovercal offset =  53  63  63  63  63  63  63  63  63  63  63  63  63  63  63  63  63  63 
N6.C1.S18: Tx Dq xovercal offset  =  53  54  56  59  61  60  58  56  61  53  54  56  60  61  60  58  56  61 
N6.C1:         CMDn  CMDs  CTL  CKE  CLK   0  1  2  3  4  5  6  7  8
N6.C1: offsets:  0     0    61N6: getComplexCkeSetupTime defaultOffset = 98
N6: getComplexCkeSetupTime = 98
   63    3
Ctl Offsets Delta / final ctl offset / final cke offset /  98  /  63  /  33
Cke invertpiclk / Ctl invertpiclk / 0x0  /  0x0
N6: getComplexClkSetupTime defaultOffset = 0
N6: getComplexClkSetupTime = 0
ClkSetupTime = 35
N6: getComplexDqSetupTime defaultOffset = 0
N6: getComplexDqSetupTime = 0
N6.C1.S00: txdqoffset delta = 0, dq invertpiclk = 0
N6: getComplexDqsSetupTime defaultOffset = 40
N6: getComplexDqsSetupTime = 40
N6.C1.S00: txdqsoffset delta = 40
N6: getComplexRcvEnSetupTime defaultOffset = 37
N6: getComplexRcvEnSetupTime = 37
N6.C1.S00: rcvenoffset delta = 37
N6.C1.S00: Final txdqoffset / txdqsoffset / rcvenoffset / 53 / 29 / 26
N6: getComplexDqSetupTime defaultOffset = 0
N6: getComplexDqSetupTime = 0
N6.C1.S01: txdqoffset delta = 0, dq invertpiclk = 0
N6: getComplexDqsSetupTime defaultOffset = 40
N6: getComplexDqsSetupTime = 40
N6.C1.S01: txdqsoffset delta = 40
N6: getComplexRcvEnSetupTime defaultOffset = 37
N6: getComplexRcvEnSetupTime = 37
N6.C1.S01: rcvenoffset delta = 37
N6.C1.S01: Final txdqoffset / txdqsoffset / rcvenoffset / 22 / 62 / 59
N6: getComplexDqSetupTime defaultOffset = 0
N6: getComplexDqSetupTime = 0
N6.C1.S02: txdqoffset delta = 0, dq invertpiclk = 0
N6: getComplexDqsSetupTime defaultOffset = 40
N6: getComplexDqsSetupTime = 40
N6.C1.S02: txdqsoffset delta = 40
N6: getComplexRcvEnSetupTime defaultOffset = 37
N6: getComplexRcvEnSetupTime = 37
N6.C1.S02: rcvenoffset delta = 37
N6.C1.S02: Final txdqoffset / txdqsoffset / rcvenoffset / 56 / 32 / 29
N6: getComplexDqSetupTime defaultOffset = 0
N6: getComplexDqSetupTime = 0
N6.C1.S03: txdqoffset delta = 0, dq invertpiclk = 0
N6: getComplexDqsSetupTime defaultOffset = 40
N6: getComplexDqsSetupTime = 40
N6.C1.S03: txdqsoffset delta = 40
N6: getComplexRcvEnSetupTime defaultOffset = 37
N6: getComplexRcvEnSetupTime = 37
N6.C1.S03: rcvenoffset delta = 37
N6.C1.S03: Final txdqoffset / txdqsoffset / rcvenoffset / 27 /  3 /  0
N6: getComplexDqSetupTime defaultOffset = 0
N6: getComplexDqSetupTime = 0
N6.C1.S04: txdqoffset delta = 0, dq invertpiclk = 0
N6: getComplexDqsSetupTime defaultOffset = 40
N6: getComplexDqsSetupTime = 40
N6.C1.S04: txdqsoffset delta = 40
N6: getComplexRcvEnSetupTime defaultOffset = 37
N6: getComplexRcvEnSetupTime = 37
N6.C1.S04: rcvenoffset delta = 37
N6.C1.S04: Final txdqoffset / txdqsoffset / rcvenoffset / 61 / 37 / 34
N6: getComplexDqSetupTime defaultOffset = 0
N6: getComplexDqSetupTime = 0
N6.C1.S05: txdqoffset delta = 0, dq invertpiclk = 0
N6: getComplexDqsSetupTime defaultOffset = 40
N6: getComplexDqsSetupTime = 40
N6.C1.S05: txdqsoffset delta = 40
N6: getComplexRcvEnSetupTime defaultOffset = 37
N6: getComplexRcvEnSetupTime = 37
N6.C1.S05: rcvenoffset delta = 37
N6.C1.S05: Final txdqoffset / txdqsoffset / rcvenoffset / 28 /  4 /  1
N6: getComplexDqSetupTime defaultOffset = 0
N6: getComplexDqSetupTime = 0
N6.C1.S06: txdqoffset delta = 0, dq invertpiclk = 0
N6: getComplexDqsSetupTime defaultOffset = 40
N6: getComplexDqsSetupTime = 40
N6.C1.S06: txdqsoffset delta = 40
N6: getComplexRcvEnSetupTime defaultOffset = 37
N6: getComplexRcvEnSetupTime = 37
N6.C1.S06: rcvenoffset delta = 37
N6.C1.S06: Final txdqoffset / txdqsoffset / rcvenoffset / 58 / 34 / 31
N6: getComplexDqSetupTime defaultOffset = 0
N6: getComplexDqSetupTime = 0
N6.C1.S07: txdqoffset delta = 0, dq invertpiclk = 0
N6: getComplexDqsSetupTime defaultOffset = 40
N6: getComplexDqsSetupTime = 40
N6.C1.S07: txdqsoffset delta = 40
N6: getComplexRcvEnSetupTime defaultOffset = 37
N6: getComplexRcvEnSetupTime = 37
N6.C1.S07: rcvenoffset delta = 37
N6.C1.S07: Final txdqoffset / txdqsoffset / rcvenoffset / 24 /  0 / 61
N6: getComplexDqSetupTime defaultOffset = 0
N6: getComplexDqSetupTime = 0
N6.C1.S08: txdqoffset delta = 0, dq invertpiclk = 0
N6: getComplexDqsSetupTime defaultOffset = 40
N6: getComplexDqsSetupTime = 40
N6.C1.S08: txdqsoffset delta = 40
N6: getComplexRcvEnSetupTime defaultOffset = 37
N6: getComplexRcvEnSetupTime = 37
N6.C1.S08: rcvenoffset delta = 37
N6.C1.S08: Final txdqoffset / txdqsoffset / rcvenoffset / 61 / 37 / 34

Checkpoint Code: Socket 0, 0xB6, 0x02, 0x0000
N2.C0: cwleffective = 8
N4: SetupJckSmbCfg: JCK VLINFREQ set to: 0x820F1028
N0: HsxInitDdrioInterface
N2.C0: PreVMSE Training raw cleff = 9, raw cwleff = 7
N0.C0: rxVref = 0x5F
N4: SetupJckSmbCfg: PLL is locked.
N6: SetupJckSmbCfg: JCK VLINFREQ set to: 0x820F1028
N0.C1: rxVref = 0x5F
N2.C0: vmseratio = 0, revisionId = 5, vmse_mode = 1, QCRM_ENABLE = 0
N4.C0: SetupJckSmbCfg: dlyFrms = 15
N6: SetupJckSmbCfg: PLL is locked.
N0: HsxVmseCompInit
N2: SetupJckSmbCfg: JCK wpsyncrcven = 5, wpsyncdata = 10
N4.C0: cwleffective = 8
N6.C0: SetupJckSmbCfg: dlyFrms = 15
Checkpoint Code: Socket 0, 0xB6, 0x58, 0x0000
N0: VmseCrossoverCalib
N0: Enable xovercal
N0: vmse_modes =          1,  0
N0.C0: piDelay CMDn  CMDs  CTL  CKE  CLK   0  1  2  3  4  5  6  7  8  9 10 11 12 13 14 15 16 17
          0       0     0    0    0    0   1  1  1  1  0  1  1  1  0  1  1  1  1  0  1  1  1  0 
          1       0     0    0    0    0   1  1  1  1  0  1  1  1  1  1  1  1  1  0  1  1  1  1 
          2       0     0    1    0    0   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
          3       0     0    1    0    0   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
          4       0     0    1    1    0   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
          5       0     0    1    1    0   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
          6       0     0    1    1    0   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
          7       0     0    1    1    0   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
          8       0     0    1    1    0   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
          9       0     0    1    1    0   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         10       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         11       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         12       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         13       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         14       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         15       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         16       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         17       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         18       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         19       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         20       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         21       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         22       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         23       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         24       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         25       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         26       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         27       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         28       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         29       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         30       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         31       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         32       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         33       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         34       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         35       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         36       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         37       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         38       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         39       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         40       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         41       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         42       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         43       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         44       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         45       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         46       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         47       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         48       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         49       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         50       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         51       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         52       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         53       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         54       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         55       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         56       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         57       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         58       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         59       0     0    1    1    1   0  1  1  1  1  1  1  1  1  0  1  1  1  1  1  1  1  1 
         60       0     0    1    1    1   X  0  1  1  1  1  1  1  1  X  0  1  1  1  1  1  1  1 
         61       0     0    1    1    1   X  X  1  1  1  1  1  1  1  X  X  1  1  1  1  1  1  1 
         62       0     0    1    1    1   X  X  1  1  1  1  1  0  1  X  X  1  1  1  1  1  0  1 
         63       0     0    1    1    1   X  X  0  1  1  1  1  X  1  X  X  0  1  1  1  1  X  1 
N0.C0: setting ddrcrinvertpiclk
          0       0     0    1    1    1   X  X  X  1  1  1  0  X  1  X  X  X  1  1  1  0  X  1 
          1       0     0    1    1    1   X  X  X  0  1  1  0  X  1  X  X  X  0  1  1  0  X  1 
          2       0     0    1    1    1   X  X  X  X  1  0  0  X  0  X  X  X  X  1  0  0  X  0 
          3       0     0    1    1    1   X  X  X  X  0  X  0  X  X  X  X  X  X  0  X  0  X  X 
          4       0     0    0    1    1   X  X  X  X  X  X  0  X  X  X  X  X  X  X  X  0  X  X 
          5       0     0    X    1    1   X  X  X  X  X  X  0  X  X  X  X  X  X  X  X  0  X  X 
          6       0     0    X    0    1   X  X  X  X  X  X  0  X  X  X  X  X  X  X  X  0  X  X 
          7       0     0    X    X    1   X  X  X  X  X  X  0  X  X  X  X  X  X  X  X  0  X  X 
          8       0     0    X    X    1   X  X  X  X  X  X  0  X  X  X  X  X  X  X  X  0  X  X 
          9       0     0    X    X    1   X  X  X  X  X  X  0  X  X  X  X  X  X  X  X  0  X  X 
         10       0     0    X    X    1   X  X  X  X  X  X  0  X  X  X  X  X  X  X  X  0  X  X 
         11       0     0    X    X    0   X  X  X  X  X  X  0  X  X  X  X  X  X  X  X  0  X  X 
         12       0     0    X    X    X   X  X  X  X  X  X  0  X  X  X  X  X  X  X  X  0  X  X 
         13       0     0    X    X    X   X  X  X  X  X  X  0  X  X  X  X  X  X  X  X  0  X  X 
         14       0     0    X    X    X   X  X  X  X  X  X  0  X  X  X  X  X  X  X  X  0  X  X 
         15       0     0    X    X    X   X  X  X  X  X  X  0  X  X  X  X  X  X  X  X  0  X  X 
         16       0     0    X    X    X   X  X  X  X  X  X  0  X  X  X  X  X  X  X  X  0  X  X 
         17       0     0    X    X    X   X  X  X  X  X  X  0  X  X  X  X  X  X  X  X  0  X  X 
         18       0     0    X    X    X   X  X  X  X  X  X  0  X  X  X  X  X  X  X  X  0  X  X 
         19       0     0    X    X    X   X  X  X  X  X  X  0  X  X  X  X  X  X  X  X  0  X  X 
         20       0     0    X    X    X   X  X  X  X  X  X  0  X  X  X  X  X  X  X  X  0  X  X 
         21       0     0    X    X    X   X  X  X  X  X  X  0  X  X  X  X  X  X  X  X  0  X  X 
         22       0     0    X    X    X   X  X  X  X  X  X  0  X  X  X  X  X  X  X  X  0  X  X 
         23       0     0    X    X    X   X  X  X  X  X  X  0  X  X  X  X  X  X  X  X  0  X  X 
         24       0     0    X    X    X   X  X  X  X  X  X  0  X  X  X  X  X  X  X  X  0  X  X 
         25       0     0    X    X    X   X  X  X  X  X  X  0  X  X  X  X  X  X  X  X  0  X  X 
         26       0     0    X    X    X   X  X  X  X  X  X  0  X  X  X  X  X  X  X  X  0  X  X 
         27       0     0    X    X    X   X  X  X  X  X  X  0  X  X  X  X  X  X  X  X  0  X  X 
         28       0     0    X    X    X   X  X  X  X  X  X  0  X  X  X  X  X  X  X  X  0  X  X 
         29       0     0    X    X    X   X  X  X  X  X  X  0  X  X  X  X  X  X  X  X  0  X  X 
         30       0     0    X    X    X   X  X  X  X  X  X  0  X  X  X  X  X  X  X  X  0  X  X 
         31       0     0    X    X    X   X  X  X  X  X  X  0  X  X  X  X  X  X  X  X  0  X  X 
         32       0     0    X    X    X   X  X  X  X  X  X  0  X  X  X  X  X  X  X  X  0  X  X 
         33       0     0    X    X    X   X  X  X  X  X  X  0  X  X  X  X  X  X  X  X  0  X  X 
         34       0     0    X    X    X   X  X  X  X  X  X  0  X  X  X  X  X  X  X  X  0  X  X 
         35       0     0    X    X    X   X  X  X  X  X  X  0  X  X  X  X  X  X  X  X  0  X  X 
         36       0     0    X    X    X   X  X  X  X  X  X  0  X  X  X  X  X  X  X  X  0  X  X 
         37       0     0    X    X    X   X  X  X  X  X  X  0  X  X  X  X  X  X  X  X  0  X  X 
         38       0     0    X    X    X   X  X  X  X  X  X  0  X  X  X  X  X  X  X  X  0  X  X 
         39       0     0    X    X    X   X  X  X  X  X  X  0  X  X  X  X  X  X  X  X  0  X  X 
         40       0     0    X    X    X   X  X  X  X  X  X  0  X  X  X  X  X  X  X  X  0  X  X 
         41       0     0    X    X    X   X  X  X  X  X  X  0  X  X  X  X  X  X  X  X  0  X  X 
         42       0     0    X    X    X   X  X  X  X  X  X  0  X  X  X  X  X  X  X  X  0  X  X 
         43       0     0    X    X    X   X  X  X  X  X  X  0  X  X  X  X  X  X  X  X  0  X  X 
         44       0     0    X    X    X   X  X  X  X  X  X  0  X  X  X  X  X  X  X  X  0  X  X 
         45       0     0    X    X    X   X  X  X  X  X  X  0  X  X  X  X  X  X  X  X  0  X  X 
         46       0     0    X    X    X   X  X  X  X  X  X  0  X  X  X  X  X  X  X  X  0  X  X 
         47       0     0    X    X    X   X  X  X  X  X  X  0  X  X  X  X  X  X  X  X  0  X  X 
         48       0     0    X    X    X   X  X  X  X  X  X  0  X  X  X  X  X  X  X  X  0  X  X 
         49       0     0    X    X    X   X  X  X  X  X  X  0  X  X  X  X  X  X  X  X  0  X  X 
         50       0     0    X    X    X   X  X  X  X  X  X  0  X  X  X  X  X  X  X  X  0  X  X 
         51       0     0    X    X    X   X  X  X  X  X  X  0  X  X  X  X  X  X  X  X  0  X  X 
         52       0     0    X    X    X   X  X  X  X  X  X  0  X  X  X  X  X  X  X  X  0  X  X 
         53       0     0    X    X    X   X  X  X  X  X  X  0  X  X  X  X  X  X  X  X  0  X  X 
         54       0     0    X    X    X   X  X  X  X  X  X  0  X  X  X  X  X  X  X  X  0  X  X 
         55       0     0    X    X    X   X  X  X  X  X  X  0  X  X  X  X  X  X  X  X  0  X  X 
         56       0     0    X    X    X   X  X  X  X  X  X  0  X  X  X  X  X  X  X  X  0  X  X 
         57       0     0    X    X    X   X  X  X  X  X  X  0  X  X  X  X  X  X  X  X  0  X  X 
         58       0     0    X    X    X   X  X  X  X  X  X  0  X  X  X  X  X  X  X  X  0  X  X 
         59       0     0    X    X    X   X  X  X  X  X  X  0  X  X  X  X  X  X  X  X  0  X  X 
         60       0     0    X    X    X   X  X  X  X  X  X  0  X  X  X  X  X  X  X  X  0  X  X 
         61       0     0    X    X    X   X  X  X  X  X  X  0  X  X  X  X  X  X  X  X  0  X  X 
         62       0     0    X    X    X   X  X  X  X  X  X  0  X  X  X  X  X  X  X  X  0  X  X 
         63       0     0    X    X    X   X  X  X  X  X  X  1  X  X  X  X  X  X  X  X  1  X  X 
N0.C0: CMD-N xovercal offset = 0
N0.C0: CMD-S xovercal offset = 0
N0.C0: CTL xovercal offset   = 4
N0.C0: CKE xovercal offset   = 6
N0.C0: CLK xovercal offset   = 11
N0.C0.S18: STROBE                     0   1   2   3   4   5   6   7   8   9  10  11  12  13  14  15  16  17
N0.C0.S18: Rec En xovercal offset =  59  60  63   1   3   2   0  62   2  59  60  63   1   3   2   0  62   2 
N0.C0.S18: Tx Dqs xovercal offset =  59  63  63  63  63  63   0  63  63  63  63  63  63  63  63   0  63  63 
N0.C0.S18: Tx Dq xovercal offset  =  59  60  63   1   3   2   0  62   2  59  60  63   1   3   2   0  62   2 
N0.C0:         CMDn  CMDs  CTL  CKE  CLK   0  1  2  3  4  5  6  7  8
N0.C0: offsets:  0     0     4N0: getComplexCkeSetupTime defaultOffset = 98
N0: getComplexCkeSetupTime = 98
    6   11
Ctl Offsets Delta / final ctl offset / final cke offset /  98  /  38  /   8
Cke invertpiclk / Ctl invertpiclk / 0x0  /  0x0
N0: getComplexClkSetupTime defaultOffset = 0
N0: getComplexClkSetupTime = 0
ClkSetupTime = 11
N0: getComplexDqSetupTime defaultOffset = 0
N0: getComplexDqSetupTime = 0
N0.C0.S00: txdqoffset delta = 0, dq invertpiclk = 0
N0: getComplexDqsSetupTime defaultOffset = 40
N0: getComplexDqsSetupTime = 40
N0.C0.S00: txdqsoffset delta = 40
N0: getComplexRcvEnSetupTime defaultOffset = 37
N0: getComplexRcvEnSetupTime = 37
N0.C0.S00: rcvenoffset delta = 37
N0.C0.S00: Final txdqoffset / txdqsoffset / rcvenoffset / 27 /  3 /  0
N0: getComplexDqSetupTime defaultOffset = 0
N0: getComplexDqSetupTime = 0
N0.C0.S01: txdqoffset delta = 0, dq invertpiclk = 0
N0: getComplexDqsSetupTime defaultOffset = 40
N0: getComplexDqsSetupTime = 40
N0.C0.S01: txdqsoffset delta = 40
N0: getComplexRcvEnSetupTime defaultOffset = 37
N0: getComplexRcvEnSetupTime = 37
N0.C0.S01: rcvenoffset delta = 37
N0.C0.S01: Final txdqoffset / txdqsoffset / rcvenoffset / 60 / 36 / 33
N0: getComplexDqSetupTime defaultOffset = 0
N0: getComplexDqSetupTime = 0
N0.C0.S02: txdqoffset delta = 0, dq invertpiclk = 0
N0: getComplexDqsSetupTime defaultOffset = 40
N0: getComplexDqsSetupTime = 40
N0.C0.S02: txdqsoffset delta = 40
N0: getComplexRcvEnSetupTime defaultOffset = 37
N0: getComplexRcvEnSetupTime = 37
N0.C0.S02: rcvenoffset delta = 37
N0.C0.S02: Final txdqoffset / txdqsoffset / rcvenoffset / 31 /  7 /  4
N0: getComplexDqSetupTime defaultOffset = 0
N0: getComplexDqSetupTime = 0
N0.C0.S03: txdqoffset delta = 0, dq invertpiclk = 3
N0: getComplexDqsSetupTime defaultOffset = 40
N0: getComplexDqsSetupTime = 40
N0.C0.S03: txdqsoffset delta = 40
N0: getComplexRcvEnSetupTime defaultOffset = 37
N0: getComplexRcvEnSetupTime = 37
N0.C0.S03: rcvenoffset delta = 37
N0.C0.S03: Final txdqoffset / txdqsoffset / rcvenoffset /  1 / 41 / 38
N0: getComplexDqSetupTime defaultOffset = 0
N0: getComplexDqSetupTime = 0
N0.C0.S04: txdqoffset delta = 0, dq invertpiclk = 3
N0: getComplexDqsSetupTime defaultOffset = 40
N0: getComplexDqsSetupTime = 40
N0.C0.S04: txdqsoffset delta = 40
N0: getComplexRcvEnSetupTime defaultOffset = 37
N0: getComplexRcvEnSetupTime = 37
N0.C0.S04: rcvenoffset delta = 37
N0.C0.S04: Final txdqoffset / txdqsoffset / rcvenoffset / 35 / 11 /  8
N0: getComplexDqSetupTime defaultOffset = 0
N0: getComplexDqSetupTime = 0
N0.C0.S05: txdqoffset delta = 0, dq invertpiclk = 3
N0: getComplexDqsSetupTime defaultOffset = 40
N0: getComplexDqsSetupTime = 40
N0.C0.S05: txdqsoffset delta = 40
N0: getComplexRcvEnSetupTime defaultOffset = 37
N0: getComplexRcvEnSetupTime = 37
N0.C0.S05: rcvenoffset delta = 37
N0.C0.S05: Final txdqoffset / txdqsoffset / rcvenoffset /  2 / 42 / 39
N0: getComplexDqSetupTime defaultOffset = 0
N0: getComplexDqSetupTime = 0
N0.C0.S06: txdqoffset delta = 0, dq invertpiclk = 3
N0: getComplexDqsSetupTime defaultOffset = 40
N0: getComplexDqsSetupTime = 40
N0.C0.S06: txdqsoffset delta = 40
N0: getComplexRcvEnSetupTime defaultOffset = 37
N0: getComplexRcvEnSetupTime = 37
N0.C0.S06: rcvenoffset delta = 37
N0.C0.S06: Final txdqoffset / txdqsoffset / rcvenoffset / 32 /  8 /  5
N0: getComplexDqSetupTime defaultOffset = 0
N0: getComplexDqSetupTime = 0
N0.C0.S07: txdqoffset delta = 0, dq invertpiclk = 0
N0: getComplexDqsSetupTime defaultOffset = 40
N0: getComplexDqsSetupTime = 40
N0.C0.S07: txdqsoffset delta = 40
N0: getComplexRcvEnSetupTime defaultOffset = 37
N0: getComplexRcvEnSetupTime = 37
N0.C0.S07: rcvenoffset delta = 37
N0.C0.S07: Final txdqoffset / txdqsoffset / rcvenoffset / 62 / 38 / 35
N0: getComplexDqSetupTime defaultOffset = 0
N0: getComplexDqSetupTime = 0
N0.C0.S08: txdqoffset delta = 0, dq invertpiclk = 3
N0: getComplexDqsSetupTime defaultOffset = 40
N0: getComplexDqsSetupTime = 40
N0.C0.S08: txdqsoffset delta = 40
N0: getComplexRcvEnSetupTime defaultOffset = 37
N0: getComplexRcvEnSetupTime = 37
N0.C0.S08: rcvenoffset delta = 37
N0.C0.S08: Final txdqoffset / txdqsoffset / rcvenoffset / 34 / 10 /  7

N0: vmse_modes =          1,  0
N0.C1: piDelay CMDn  CMDs  CTL  CKE  CLK   0  1  2  3  4  5  6  7  8  9 10 11 12 13 14 15 16 17
          0       0     0    1    1    0   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
          1       0     0    1    1    0   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
          2       0     0    1    1    0   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
          3       0     0    1    1    0   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
          4       0     0    1    1    0   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
          5       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
          6       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
          7       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
          8       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
          9       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         10       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         11       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         12       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         13       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         14       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         15       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         16       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         17       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         18       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         19       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         20       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         21       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         22       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         23       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         24       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         25       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         26       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         27       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         28       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         29       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         30       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         31       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         32       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         33       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         34       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         35       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         36       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         37       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         38       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         39       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         40       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         41       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         42       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         43       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         44       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         45       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         46       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         47       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         48       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         49       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         50       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         51       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         52       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         53       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         54       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         55       0     0    1    1    1   0  1  1  1  1  1  1  1  1  0  1  1  1  1  1  1  1  1 
         56       0     0    1    1    1   X  1  1  1  1  1  1  1  1  X  1  1  1  1  1  1  1  1 
         57       0     0    1    1    1   X  0  1  1  1  1  1  1  1  X  0  1  1  1  1  1  1  1 
         58       0     0    1    1    1   X  X  1  1  1  1  1  1  1  X  X  1  1  1  1  1  1  1 
         59       0     0    1    1    1   X  X  1  1  1  1  1  0  1  X  X  1  1  1  1  1  0  1 
         60       0     0    1    1    1   X  X  0  1  1  1  1  X  1  X  X  0  1  1  1  1  X  1 
         61       0     0    1    1    1   X  X  X  0  1  1  0  X  1  X  X  X  0  1  1  0  X  1 
         62       0     0    1    1    1   X  X  X  X  1  0  X  X  1  X  X  X  X  1  0  X  X  1 
         63       0     0    1    1    1   X  X  X  X  1  X  X  X  1  X  X  X  X  1  X  X  X  1 
N0.C1: setting ddrcrinvertpiclk
          0       0     0    0    1    1   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
          1       0     0    0    1    1   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
          2       0     0    0    0    1   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
          3       0     0    0    X    1   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
          4       0     0    0    X    1   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
          5       0     0    0    X    1   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
          6       0     0    0    X    0   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
          7       0     0    0    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
          8       0     0    0    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
          9       0     0    0    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         10       0     0    0    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         11       0     0    0    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         12       0     0    0    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         13       0     0    0    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         14       0     0    0    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         15       0     0    0    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         16       0     0    0    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         17       0     0    0    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         18       0     0    0    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         19       0     0    0    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         20       0     0    0    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         21       0     0    0    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         22       0     0    0    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         23       0     0    0    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         24       0     0    0    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         25       0     0    0    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         26       0     0    0    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         27       0     0    0    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         28       0     0    0    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         29       0     0    0    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         30       0     0    0    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         31       0     0    0    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         32       0     0    0    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         33       0     0    0    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         34       0     0    0    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         35       0     0    0    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         36       0     0    0    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         37       0     0    0    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         38       0     0    0    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         39       0     0    0    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         40       0     0    0    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         41       0     0    0    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         42       0     0    0    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         43       0     0    0    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         44       0     0    0    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         45       0     0    0    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         46       0     0    0    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         47       0     0    0    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         48       0     0    0    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         49       0     0    0    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         50       0     0    0    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         51       0     0    0    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         52       0     0    0    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         53       0     0    0    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         54       0     0    0    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         55       0     0    0    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         56       0     0    0    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         57       0     0    0    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         58       0     0    0    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         59       0     0    0    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         60       0     0    0    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         61       0     0    0    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         62       0     0    0    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         63       0     0    0    X    X   X  X  X  X  1  X  X  X  1  X  X  X  X  1  X  X  X  1 
N0.C1: CMD-N xovercal offset = 0
N0.C1: CMD-S xovercal offset = 0
N0.C1: CTL xovercal offset   = 0
N0.C1: CKE xovercal offset   = 2
N0.C1: CLK xovercal offset   = 6
N0.C1.S18: STROBE                     0   1   2   3   4   5   6   7   8   9  10  11  12  13  14  15  16  17
N0.C1.S18: Rec En xovercal offset =  55  57  60  61   0  62  61  59   0  55  57  60  61   0  62  61  59   0 
N0.C1.S18: Tx Dqs xovercal offset =  55  63  63  63   0  63  63  63   0  63  63  63  63   0  63  63  63   0 
N0.C1.S18: Tx Dq xovercal offset  =  55  57  60  61   0  62  61  59   0  55  57  60  61   0  62  61  59   0 
N0.C1:         CMDn  CMDs  CTL  CKE  CLK   0  1  2  3  4  5  6  7  8
N0.C1: offsets:  0     0     0N0: getComplexCkeSetupTime defaultOffset = 98
N0: getComplexCkeSetupTime = 98
    2    6
Ctl Offsets Delta / final ctl offset / final cke offset /  98  /   2  /  36
Cke invertpiclk / Ctl invertpiclk / 0x0  /  0x0
N0: getComplexClkSetupTime defaultOffset = 0
N0: getComplexClkSetupTime = 0
ClkSetupTime = 38
N0: getComplexDqSetupTime defaultOffset = 0
N0: getComplexDqSetupTime = 0
N0.C1.S00: txdqoffset delta = 0, dq invertpiclk = 0
N0: getComplexDqsSetupTime defaultOffset = 40
N0: getComplexDqsSetupTime = 40
N0.C1.S00: txdqsoffset delta = 40
N0: getComplexRcvEnSetupTime defaultOffset = 37
N0: getComplexRcvEnSetupTime = 37
N0.C1.S00: rcvenoffset delta = 37
N0.C1.S00: Final txdqoffset / txdqsoffset / rcvenoffset / 55 / 31 / 28
N0: getComplexDqSetupTime defaultOffset = 0
N0: getComplexDqSetupTime = 0
N0.C1.S01: txdqoffset delta = 0, dq invertpiclk = 0
N0: getComplexDqsSetupTime defaultOffset = 40
N0: getComplexDqsSetupTime = 40
N0.C1.S01: txdqsoffset delta = 40
N0: getComplexRcvEnSetupTime defaultOffset = 37
N0: getComplexRcvEnSetupTime = 37
N0.C1.S01: rcvenoffset delta = 37
N0.C1.S01: Final txdqoffset / txdqsoffset / rcvenoffset / 25 /  1 / 62
N0: getComplexDqSetupTime defaultOffset = 0
N0: getComplexDqSetupTime = 0
N0.C1.S02: txdqoffset delta = 0, dq invertpiclk = 0
N0: getComplexDqsSetupTime defaultOffset = 40
N0: getComplexDqsSetupTime = 40
N0.C1.S02: txdqsoffset delta = 40
N0: getComplexRcvEnSetupTime defaultOffset = 37
N0: getComplexRcvEnSetupTime = 37
N0.C1.S02: rcvenoffset delta = 37
N0.C1.S02: Final txdqoffset / txdqsoffset / rcvenoffset / 60 / 36 / 33
N0: getComplexDqSetupTime defaultOffset = 0
N0: getComplexDqSetupTime = 0
N0.C1.S03: txdqoffset delta = 0, dq invertpiclk = 0
N0: getComplexDqsSetupTime defaultOffset = 40
N0: getComplexDqsSetupTime = 40
N0.C1.S03: txdqsoffset delta = 40
N0: getComplexRcvEnSetupTime defaultOffset = 37
N0: getComplexRcvEnSetupTime = 37
N0.C1.S03: rcvenoffset delta = 37
N0.C1.S03: Final txdqoffset / txdqsoffset / rcvenoffset / 29 /  5 /  2
N0: getComplexDqSetupTime defaultOffset = 0
N0: getComplexDqSetupTime = 0
N0.C1.S04: txdqoffset delta = 0, dq invertpiclk = 3
N0: getComplexDqsSetupTime defaultOffset = 40
N0: getComplexDqsSetupTime = 40
N0.C1.S04: txdqsoffset delta = 40
N0: getComplexRcvEnSetupTime defaultOffset = 37
N0: getComplexRcvEnSetupTime = 37
N0.C1.S04: rcvenoffset delta = 37
N0.C1.S04: Final txdqoffset / txdqsoffset / rcvenoffset /  0 / 40 / 37
N0: getComplexDqSetupTime defaultOffset = 0
N0: getComplexDqSetupTime = 0
N0.C1.S05: txdqoffset delta = 0, dq invertpiclk = 0
N0: getComplexDqsSetupTime defaultOffset = 40
N0: getComplexDqsSetupTime = 40
N0.C1.S05: txdqsoffset delta = 40
N0: getComplexRcvEnSetupTime defaultOffset = 37
N0: getComplexRcvEnSetupTime = 37
N0.C1.S05: rcvenoffset delta = 37
N0.C1.S05: Final txdqoffset / txdqsoffset / rcvenoffset / 30 /  6 /  3
N0: getComplexDqSetupTime defaultOffset = 0
N0: getComplexDqSetupTime = 0
N0.C1.S06: txdqoffset delta = 0, dq invertpiclk = 0
N0: getComplexDqsSetupTime defaultOffset = 40
N0: getComplexDqsSetupTime = 40
N0.C1.S06: txdqsoffset delta = 40
N0: getComplexRcvEnSetupTime defaultOffset = 37
N0: getComplexRcvEnSetupTime = 37
N0.C1.S06: rcvenoffset delta = 37
N0.C1.S06: Final txdqoffset / txdqsoffset / rcvenoffset / 61 / 37 / 34
N0: getComplexDqSetupTime defaultOffset = 0
N0: getComplexDqSetupTime = 0
N0.C1.S07: txdqoffset delta = 0, dq invertpiclk = 0
N0: getComplexDqsSetupTime defaultOffset = 40
N0: getComplexDqsSetupTime = 40
N0.C1.S07: txdqsoffset delta = 40
N0: getComplexRcvEnSetupTime defaultOffset = 37
N0: getComplexRcvEnSetupTime = 37
N0.C1.S07: rcvenoffset delta = 37
N0.C1.S07: Final txdqoffset / txdqsoffset / rcvenoffset / 27 /  3 /  0
N0: getComplexDqSetupTime defaultOffset = 0
N0: getComplexDqSetupTime = 0
N0.C1.S08: txdqoffset delta = 0, dq invertpiclk = 3
N0: getComplexDqsSetupTime defaultOffset = 40
N0: getComplexDqsSetupTime = 40
N0.C1.S08: txdqsoffset delta = 40
N0: getComplexRcvEnSetupTime defaultOffset = 37
N0: getComplexRcvEnSetupTime = 37
N0.C1.S08: rcvenoffset delta = 37
N0.C1.S08: Final txdqoffset / txdqsoffset / rcvenoffset /  0 / 40 / 37

N2.C0: SELF CAL 
N4.C0: PreVMSE Training raw cleff = 9, raw cwleff = 7
N6.C0: cwleffective = 8
N6.C0: PreVMSE Training raw cleff = 9, raw cwleff = 7
N2.C0: JckCompCodeCheck: Phase 1 - Comp Code Results
N4.C0: vmseratio = 0, revisionId = 5, vmse_mode = 1, QCRM_ENABLE = 0
N6.C0: vmseratio = 0, revisionId = 5, vmse_mode = 1, QCRM_ENABLE = 0
N0: SetupJckSmbCfg: JCK VLINFREQ set to: 0x820F1028
N2.C0: Cycle ron_up ron_eq_up ron_dn ron_eq_dn odt scomp_up scom_dn tcomp_l2h tcomp_h2l   bad_training
N4: SetupJckSmbCfg: JCK wpsyncrcven = 5, wpsyncdata = 10
N6: SetupJckSmbCfg: JCK wpsyncrcven = 5, wpsyncdata = 10
N0: SetupJckSmbCfg: PLL is locked.
N0.C0: SetupJckSmbCfg: dlyFrms = 15
N0.C0: cwleffective = 8
N2.C0:  0       42     42       38      30      38     16      16        8       31       0
N0.C0: PreVMSE Training raw cleff = 9, raw cwleff = 7
N0.C0: vmseratio = 0, revisionId = 5, vmse_mode = 1, QCRM_ENABLE = 0
N0: SetupJckSmbCfg: JCK wpsyncrcven = 5, wpsyncdata = 10
N2.C0:  1       43     43       39      30      38     16      16        8       31       0
N2.C0:  2       42     42       38      30      38     15      15        8       31       0
N2.C0:  3       42     42       38      30      38     16      16        8       31       0
N2.C0:  4       42     42       38      30      38     16      16        8       31       0
N2.C0:  5       42     42       38      30      38     15      15        8       31       0
N2.C0:  6       42     42       38      30      38     16      16        8       31       0
N2.C0:  7       42     42       38      30      38     15      15        8       31       0
N2.C0:  8       42     42       38      30      38     16      16        8       31       0
N2.C0:  9       42     42       38      28      38     16      16        8       31       0
N2.C0: JckCompCodeCheck: Phase 2 - Check for bad ron_up vs average: num = 10, ron_up_avg = 42, ron_up_75avg = 31
N2.C0: Cycle ron_up ron_eq_up ron_dn ron_eq_dn odt scomp_up scom_dn tcomp_l2h tcomp_h2l   bad_training
N4.C0: SELF CAL 
N6.C0: SELF CAL 
N2.C0: JckCompCodeCheck: Phase 3 - Comp Code Limits
N2.C0: ron_up_limitdn   ron_dn_limitup   ron_eq_dn_limtdn  odt_limitdn
N4.C0: JckCompCodeCheck: Phase 1 - Comp Code Results
N6.C0: JckCompCodeCheck: Phase 1 - Comp Code Results
N2.C0:     26                45                20             24
N4.C0: Cycle ron_up ron_eq_up ron_dn ron_eq_dn odt scomp_up scom_dn tcomp_l2h tcomp_h2l   bad_training
N6.C0: Cycle ron_up ron_eq_up ron_dn ron_eq_dn odt scomp_up scom_dn tcomp_l2h tcomp_h2l   bad_training
N2.C0: JckCompCodeCheck: Phase 3 - SUCCESS
N2.C0: VmseOverrideJckCompCodes
N0.C0: SELF CAL 
N4.C0:  0       42     42       39      32      39     15      15        8       31       0
N0.C0: JckCompCodeCheck: Phase 1 - Comp Code Results
N6.C0:  0       42     42       38      30      39     17      17        5       31       0
N0.C0: Cycle ron_up ron_eq_up ron_dn ron_eq_dn odt scomp_up scom_dn tcomp_l2h tcomp_h2l   bad_training
N4.C0:  1       42     42       39      31      39     14      14        8       31       0
N6.C0:  1       42     42       38      30      39     18      18        6       31       0
N0.C0:  0       41     41       37      32      38     16      16       31        8       0
N4.C0:  2       42     42       39      31      39     15      15        8       31       0
N6.C0:  2       42     42       38      29      39     17      17        6       31       0
N0.C0:  1       41     41       37      33      38     16      16       31        8       0
N4.C0:  3       42     42       39      31      39     15      15        8       31       0
N6.C0:  3       43     43       39      28      39     17      17        4       31       0
N0.C0:  2       41     41       37      32      38     16      16       31        8       0
N4.C0:  4       42     42       39      31      39     15      15        8       31       0
N6.C0:  4       43     43       39      30      39     16      16        5       31       0
N0.C0:  3       41     41       37      33      38     15      15       31        8       0
N4.C0:  5       42     42       39      31      39     14      14        8       31       0
N6.C0:  5       43     43       39      31      39     17      17        6       31       0
N0.C0:  4       41     41       37      33      38     16      16       31        8       0
N4.C0:  6       42     42       39      31      39     14      14        8       31       0
N6.C0:  6       43     43       39      30      39     17      17        5       31       0
N0.C0:  5       41     41       37      32      38     16      16       31        8       0
N4.C0:  7       42     42       39      32      39     15      15        8       31       0
N6.C0:  7       43     43       39      31      39     16      16        4       31       0
N0.C0:  6       41     41       37      32      38     16      16       31        8       0
N4.C0:  8       42     42       39      27      39     15      15        8       31       0
N6.C0:  8       43     43       39      31      39     16      16        7       31       0
N0.C0:  7       41     41       37      32      38     16      16       31        8       0
N4.C0:  9       42     42       39      32      39     15      15        8       31       0
N4.C0: JckCompCodeCheck: Phase 2 - Check for bad ron_up vs average: num = 10, ron_up_avg = 42, ron_up_75avg = 31
N6.C0:  9       43     43       39      31      39     16      16        7       31       0
N0.C0:  8       41     41       37      33      38     16      16       31        8       0
N4.C0: Cycle ron_up ron_eq_up ron_dn ron_eq_dn odt scomp_up scom_dn tcomp_l2h tcomp_h2l   bad_training
N6.C0: JckCompCodeCheck: Phase 2 - Check for bad ron_up vs average: num = 10, ron_up_avg = 42, ron_up_75avg = 31
N4.C0: JckCompCodeCheck: Phase 3 - Comp Code Limits
N6.C0: Cycle ron_up ron_eq_up ron_dn ron_eq_dn odt scomp_up scom_dn tcomp_l2h tcomp_h2l   bad_training
N0.C0:  9       41     41       37      33      38     16      16       31        8       0
N4.C0: ron_up_limitdn   ron_dn_limitup   ron_eq_dn_limtdn  odt_limitdn
N6.C0: JckCompCodeCheck: Phase 3 - Comp Code Limits
N0.C0: JckCompCodeCheck: Phase 2 - Check for bad ron_up vs average: num = 10, ron_up_avg = 41, ron_up_75avg = 30
N4.C0:     26                46                21             24
N6.C0: ron_up_limitdn   ron_dn_limitup   ron_eq_dn_limtdn  odt_limitdn
N0.C0: Cycle ron_up ron_eq_up ron_dn ron_eq_dn odt scomp_up scom_dn tcomp_l2h tcomp_h2l   bad_training
N4.C0: JckCompCodeCheck: Phase 3 - SUCCESS
N6.C0:     26                45                20             24
N0.C0: JckCompCodeCheck: Phase 3 - Comp Code Limits
N4.C0: VmseOverrideJckCompCodes
N6.C0: JckCompCodeCheck: Phase 3 - SUCCESS
N0.C0: ron_up_limitdn   ron_dn_limitup   ron_eq_dn_limtdn  odt_limitdn
N6.C0: VmseOverrideJckCompCodes
N0.C0:     25                45                21             24
N0.C0: JckCompCodeCheck: Phase 3 - SUCCESS
N0.C0: VmseOverrideJckCompCodes
N2: SetupJckSmbCfg: JCK VLINFREQ set to: 0x820F1028
N2: SetupJckSmbCfg: PLL is locked.
N2.C2: SetupJckSmbCfg: dlyFrms = 15
N2.C2: cwleffective = 8
N2.C2: PreVMSE Training raw cleff = 9, raw cwleff = 7
N2.C2: vmseratio = 0, revisionId = 5, vmse_mode = 1, QCRM_ENABLE = 0
N2: SetupJckSmbCfg: JCK wpsyncrcven = 5, wpsyncdata = 10
N2.C1: SELF CAL 
N2.C1: JckCompCodeCheck: Phase 1 - Comp Code Results
N2.C1: Cycle ron_up ron_eq_up ron_dn ron_eq_dn odt scomp_up scom_dn tcomp_l2h tcomp_h2l   bad_training
N4: SetupJckSmbCfg: JCK VLINFREQ set to: 0x820F1028
Checkpoint Code: Socket 0, 0xB6, 0xA0, 0x0000
N4: SetupJckSmbCfg: PLL is locked.
N6: SetupJckSmbCfg: JCK VLINFREQ set to: 0x820F1028
N2.C1:  0       42     42       39      32      38     15      15        7       31       0
N4.C2: SetupJckSmbCfg: dlyFrms = 15
N6: SetupJckSmbCfg: PLL is locked.
N0: SetupJckSmbCfg: JCK VLINFREQ set to: 0x820F1028
N4.C2: cwleffective = 8
N6.C2: SetupJckSmbCfg: dlyFrms = 15
N4.C2: PreVMSE Training raw cleff = 9, raw cwleff = 7
N0: SetupJckSmbCfg: PLL is locked.
N6.C2: cwleffective = 8
N2.C1:  1       42     42       39      31      38     15      15        8       31       0
N4.C2: vmseratio = 0, revisionId = 5, vmse_mode = 1, QCRM_ENABLE = 0
N6.C2: PreVMSE Training raw cleff = 9, raw cwleff = 7
N0.C2: SetupJckSmbCfg: dlyFrms = 15
N4: SetupJckSmbCfg: JCK wpsyncrcven = 5, wpsyncdata = 10
N6.C2: vmseratio = 0, revisionId = 5, vmse_mode = 1, QCRM_ENABLE = 0
N0.C2: cwleffective = 8
N2.C1:  2       42     42       39      31      38     15      15        6       31       0
N6: SetupJckSmbCfg: JCK wpsyncrcven = 5, wpsyncdata = 10
N0.C2: PreVMSE Training raw cleff = 9, raw cwleff = 7
N0.C2: vmseratio = 0, revisionId = 5, vmse_mode = 1, QCRM_ENABLE = 0
N2.C1:  3       42     42       39      31      38     15      15        8       31       0
N0: SetupJckSmbCfg: JCK wpsyncrcven = 5, wpsyncdata = 10
N2.C1:  4       42     42       39      32      38     15      15        7       31       0
N2.C1:  5       42     42       39      32      38     15      15        7       31       0
N2.C1:  6       42     42       39      32      38     15      15        7       31       0
N2.C1:  7       42     42       39      31      38     15      15        8       31       0
N2.C1:  8       42     42       39      31      38     15      15        8       31       0
N2.C1:  9       42     42       39      32      38     15      15        8       31       0
N2.C1: JckCompCodeCheck: Phase 2 - Check for bad ron_up vs average: num = 10, ron_up_avg = 42, ron_up_75avg = 31
N2.C1: Cycle ron_up ron_eq_up ron_dn ron_eq_dn odt scomp_up scom_dn tcomp_l2h tcomp_h2l   bad_training
N2.C1: JckCompCodeCheck: Phase 3 - Comp Code Limits
N2.C1: ron_up_limitdn   ron_dn_limitup   ron_eq_dn_limtdn  odt_limitdn
N2.C1:     26                46                21             24
N2.C1: JckCompCodeCheck: Phase 3 - SUCCESS
N2.C1: VmseOverrideJckCompCodes
N4.C1: SELF CAL 
N4.C1: JckCompCodeCheck: Phase 1 - Comp Code Results
N4.C1: Cycle ron_up ron_eq_up ron_dn ron_eq_dn odt scomp_up scom_dn tcomp_l2h tcomp_h2l   bad_training
N6.C1: SELF CAL 
N6.C1: JckCompCodeCheck: Phase 1 - Comp Code Results
N6.C1: Cycle ron_up ron_eq_up ron_dn ron_eq_dn odt scomp_up scom_dn tcomp_l2h tcomp_h2l   bad_training
N4.C1:  0       42     42       39      31      38     14      14       13       31       0
N0.C1: SELF CAL 
N0.C1: JckCompCodeCheck: Phase 1 - Comp Code Results
N0.C1: Cycle ron_up ron_eq_up ron_dn ron_eq_dn odt scomp_up scom_dn tcomp_l2h tcomp_h2l   bad_training
N4.C1:  1       42     42       39      31      38     14      14       14       31       0
N6.C1:  0       41     41       38      30      38     15      15        9       31       0
N0.C1:  0       41     41       37      32      38     16      16        8       31       0
N4.C1:  2       42     42       39      31      38     14      14       14       31       0
N6.C1:  1       41     41       38      30      38     15      15        9       31       0
N0.C1:  1       41     41       37      32      38     16      16        8       31       0
N4.C1:  3       42     42       39      29      38     14      14       13       31       0
N6.C1:  2       41     41       38      30      38     15      15       10       31       0
N0.C1:  2       41     41       37      32      38     16      16        8       31       0
N4.C1:  4       42     42       39      29      38     14      14       13       31       0
N6.C1:  3       41     41       38      30      38     15      15        8       31       0
N0.C1:  3       41     41       37      32      38     16      16        8       31       0
N4.C1:  5       42     42       39      30      38     14      14       13       31       0
N6.C1:  4       41     41       38      30      38     15      15        9       31       0
N0.C1:  4       41     41       37      31      38     16      16        8       31       0
N4.C1:  6       42     42       39      29      38     14      14       13       31       0
N6.C1:  5       41     41       38      30      38     15      15        8       31       0
N0.C1:  5       41     41       37      32      38     16      16        8       31       0
N4.C1:  7       20     20       19      13      38     14      14        8       31       0
N6.C1:  6       41     41       38      30      38     15      15        9       31       0
N0.C1:  6       41     41       37      31      38     16      16        8       31       0
N4.C1:  8       42     42       39      29      38     14      14       13       31       0
N6.C1:  7       41     41       38      30      38     15      15       10       31       0
N0.C1:  7       41     41       37      32      38     16      16        8       31       0
N4.C1:  9       42     42       39      30      38     14      14       14       31       0
N4.C1: JckCompCodeCheck: Phase 2 - Check for bad ron_up vs average: num = 10, ron_up_avg = 39, ron_up_75avg = 29
N6.C1:  8       41     41       38      30      38     15      15        8       31       0
N4.C1: Cycle ron_up ron_eq_up ron_dn ron_eq_dn odt scomp_up scom_dn tcomp_l2h tcomp_h2l   bad_training
N0.C1:  8       41     41       37      32      38     16      16        8       31       0
N4.C1:  7       20     20       19      13      38     14      14        8       31       1
N4.C1: JckCompCodeCheck: Phase 3 - Comp Code Limits
N6.C1:  9       41     41       38      30      38     15      15        9       31       0
N4.C1: ron_up_limitdn   ron_dn_limitup   ron_eq_dn_limtdn  odt_limitdn
N6.C1: JckCompCodeCheck: Phase 2 - Check for bad ron_up vs average: num = 10, ron_up_avg = 41, ron_up_75avg = 30
N0.C1:  9       41     41       37      32      38     16      16        8       31       0
N4.C1:     26                46                20             24
N6.C1: Cycle ron_up ron_eq_up ron_dn ron_eq_dn odt scomp_up scom_dn tcomp_l2h tcomp_h2l   bad_training
N0.C1: JckCompCodeCheck: Phase 2 - Check for bad ron_up vs average: num = 10, ron_up_avg = 41, ron_up_75avg = 30
N4.C1: JckCompCodeCheck: Phase 3 - SUCCESS
N6.C1: JckCompCodeCheck: Phase 3 - Comp Code Limits
N0.C1: Cycle ron_up ron_eq_up ron_dn ron_eq_dn odt scomp_up scom_dn tcomp_l2h tcomp_h2l   bad_training
N4.C1: VmseOverrideJckCompCodes
N6.C1: ron_up_limitdn   ron_dn_limitup   ron_eq_dn_limtdn  odt_limitdn
N0.C1: JckCompCodeCheck: Phase 3 - Comp Code Limits
N6.C1:     25                45                20             24
N0.C1: ron_up_limitdn   ron_dn_limitup   ron_eq_dn_limtdn  odt_limitdn
N6.C1: JckCompCodeCheck: Phase 3 - SUCCESS
N0.C1:     25                45                21             24
N6.C1: VmseOverrideJckCompCodes
N0.C1: JckCompCodeCheck: Phase 3 - SUCCESS
N0.C1: VmseOverrideJckCompCodes
N2: Start VMSE training Sequence
N2: ddrCh0.enabled = 1
N2: ddrCh1.enabled = 1
N2: ddrCh2.enabled = 1
N2: ddrCh3.enabled = 1
N2: VMSE0.enabled = 1
N2: VMSE1.enabled = 1
N2: CpgcVmseTraining for VMSE0
N2: Initialize VMSE Channels

START - VMSE Detect DC
N2: HsxVmseCompInit
N2.C0: Skip DC Detect check for CMD results
N2.C0: Skip DC Detect check for CMD results
N2: HsxVmseCompInit
N2.C0: VmseDetectDC: SUCCESS
N2.C0: VmseDetectClock
N2.C0: VmseDetectClock: SUCCESS

END - VMSE Detect DC                   Time         212 ms

START - MXB Clock Train
N2.C0: VmseAdjustVckVoc: retrain Clock DCC.
   dcc1_vck = 0x3F, dcc2_vck = 0x37, preampvoc = 0xE
N2.C0: VmseRefVckResync: ddrFreq = 0x2, VMSE_MODE_2_1 = 1, VMSE_PREAMBLE_2UI = 0
N2.C0: VmseRefVckResync: VLINKFREQNXT set to: 0x20F940A
N2.C0: VmseTrainClockAlign: JCK clkadjcnt =6

END - MXB Clock Train                  Time         222 ms

START - VMSE Train Command
N2.C0.B00: HsxCtlXoverInit: invertPiClk = 0x0, RankUsed = 0xFFF, Training = 0x38FFF09
N2.C0.B01: HsxCtlXoverInit: invertPiClk = 0x0, RankUsed = 0xFFF, Training = 0x38FFF26
N2.C0: VmseTrainCmdFine: vmse link sts = 0x4947
N4: Start VMSE training Sequence
N4: ddrCh0.enabled = 1
N4: ddrCh1.enabled = 1
N4: ddrCh2.enabled = 1
N4: ddrCh3.enabled = 1
N4: VMSE0.enabled = 1
N4: VMSE1.enabled = 1
N4: CpgcVmseTraining for VMSE0
N4: Initialize VMSE Channels

START - VMSE Detect DC
N4: HsxVmseCompInit
N4.C0: Skip DC Detect check for CMD results
N6: Start VMSE training Sequence
Checkpoint Code: Socket 0, 0xB6, 0xA0, 0x0000
N6: ddrCh0.enabled = 1
N6: ddrCh1.enabled = 1
N4.C0: Skip DC Detect check for CMD results
N6: ddrCh2.enabled = 1
Checkpoint Code: Socket 0, 0xB6, 0x10, 0x0000
N4: HsxVmseCompInit
N6: ddrCh3.enabled = 1
N0: Start VMSE training Sequence
N4.C0: VmseDetectDC: SUCCESS
N6: VMSE0.enabled = 1
N0: ddrCh0.enabled = 1
N4.C0: VmseDetectClock
N6: VMSE1.enabled = 1
N0: ddrCh1.enabled = 1
N6: CpgcVmseTraining for VMSE0
N0: ddrCh2.enabled = 1
N6: Initialize VMSE Channels
N0: ddrCh3.enabled = 1

START - VMSE Detect DC
N0: VMSE0.enabled = 1
N6: HsxVmseCompInit
N0: VMSE1.enabled = 1
N0: CpgcVmseTraining for VMSE0
Checkpoint Code: Socket 0, 0xB6, 0x11, 0x0000
N0: Initialize VMSE Channels
N6.C0: Skip DC Detect check for CMD results

START - VMSE Detect DC
Checkpoint Code: Socket 0, 0xB6, 0x46, 0x0000
N0: HsxVmseCompInit
Checkpoint Code: Socket 0, 0xB6, 0x80, 0x0000
N6.C0: Skip DC Detect check for CMD results
N6: HsxVmseCompInit
N6.C0: VmseDetectDC: SUCCESS
N6.C0: VmseDetectClock
N0.C0: Skip DC Detect check for CMD results
N0.C0: Skip DC Detect check for CMD results
N0: HsxVmseCompInit
Checkpoint Code: Socket 0, 0xB6, 0x81, 0x0000
N0.C0: VmseDetectDC: SUCCESS
N0.C0: VmseDetectClock
N4.C0: VmseDetectClock: SUCCESS

END - VMSE Detect DC                   Time         233 ms

START - MXB Clock Train
N6.C0: VmseDetectClock: SUCCESS

END - VMSE Detect DC                   Time         220 ms

START - MXB Clock Train
N4.C0: VmseAdjustVckVoc: retrain Clock DCC.
   dcc1_vck = 0x3F, dcc2_vck = 0x1F, preampvoc = 0xB
N0.C0: VmseDetectClock: SUCCESS

END - VMSE Detect DC                   Time         238 ms

START - MXB Clock Train
Checkpoint Code: Socket 0, 0xB6, 0x48, 0x0000
N4.C0: VmseRefVckResync: ddrFreq = 0x2, VMSE_MODE_2_1 = 1, VMSE_PREAMBLE_2UI = 0
Checkpoint Code: Socket 0, 0xB6, 0x6C, 0x0000
N6.C0: VmseAdjustVckVoc: retrain Clock DCC.
   dcc1_vck = 0x8, dcc2_vck = 0x3F, preampvoc = 0xD
N4.C0: VmseRefVckResync: VLINKFREQNXT set to: 0x20F940A
N0.C0: VmseRefVckResync: ddrFreq = 0x2, VMSE_MODE_2_1 = 1, VMSE_PREAMBLE_2UI = 0
N4.C0: VmseTrainClockAlign: JCK clkadjcnt =6
N6.C0: VmseAdjustVckVoc: retrain Clock DCC.
   dcc1_vck = 0x4, dcc2_vck = 0x3F, preampvoc = 0xE

END - MXB Clock Train                  Time         228 ms
N0.C0: VmseRefVckResync: VLINKFREQNXT set to: 0x20F940A

START - VMSE Train Command
N4.C0.B00: HsxCtlXoverInit: invertPiClk = 0x0, RankUsed = 0xFFF, Training = 0x38FFF07
N0.C0: VmseTrainClockAlign: JCK clkadjcnt =1
N4.C0.B01: HsxCtlXoverInit: invertPiClk = 0x0, RankUsed = 0xFFF, Training = 0x38FFF25
N6.C0: VmseRefVckResync: ddrFreq = 0x2, VMSE_MODE_2_1 = 1, VMSE_PREAMBLE_2UI = 0

END - MXB Clock Train                  Time         175 ms

START - VMSE Train Command
Checkpoint Code: Socket 0, 0xB6, 0x4A, 0x0000
N6.C0: VmseRefVckResync: VLINKFREQNXT set to: 0x20F940A
N0.C0.B00: HsxCtlXoverInit: invertPiClk = 0x0, RankUsed = 0xFFF, Training = 0x38FFF08
N0.C0.B01: HsxCtlXoverInit: invertPiClk = 0x0, RankUsed = 0xFFF, Training = 0x38FFF26
Checkpoint Code: Socket 0, 0xB6, 0x60, 0x0000
N6.C0: VmseTrainClockAlign: JCK clkadjcnt =3

END - MXB Clock Train                  Time         300 ms

START - VMSE Train Command
N4.C0: VmseTrainCmdFine: vmse link sts = 0x4947
N6.C0.B00: HsxCtlXoverInit: invertPiClk = 0x0, RankUsed = 0xFFF, Training = 0x38FFF05
N6.C0.B01: HsxCtlXoverInit: invertPiClk = 0x0, RankUsed = 0xFFF, Training = 0x38FFF22
Checkpoint Code: Socket 0, 0xB6, 0x5A, 0x0000
N0.C0: VmseTrainCmdFine: vmse link sts = 0x4947
N6.C0: VmseTrainCmdFine: vmse link sts = 0x4947
Entry 0 - TrainDcc - DCCStart: 59, VocStart: 14, DCCFinal: 27, VocFinal: 14
Entry 1 - TrainDcc - DCCStart: 38, VocStart: 14, DCCFinal: 30, VocFinal: 14
Entry 0 - TrainDcc - DCCStart: 19, VocStart: 17, DCCFinal: 19, VocFinal: 17
Entry 1 - TrainDcc - DCCStart: 28, VocStart: 17, DCCFinal: 12, VocFinal: 17
N2.C0.S00: VmseCmdFineTraining Final: centerPi = 0x5F, PiEw = 0x2D, centerVref = 0x39, vrefHeight = 0x41
N2.C0.S01: VmseCmdFineTraining Final: centerPi = 0x5F, PiEw = 0x2E, centerVref = 0x3A, vrefHeight = 0x41
N2.C0.S02: VmseCmdFineTraining Final: centerPi = 0x5D, PiEw = 0x33, centerVref = 0x37, vrefHeight = 0x47
N2.C0.S03: VmseCmdFineTraining Final: centerPi = 0x62, PiEw = 0x31, centerVref = 0x3A, vrefHeight = 0x43
N2.C0.S04: VmseCmdFineTraining Final: centerPi = 0x59, PiEw = 0x2F, centerVref = 0x3A, vrefHeight = 0x43
N2.C0.S05: VmseCmdFineTraining Final: centerPi = 0x5D, PiEw = 0x2F, centerVref = 0x36, vrefHeight = 0x47
N2.C0.S06: VmseCmdFineTraining Final: centerPi = 0x5E, PiEw = 0x31, centerVref = 0x39, vrefHeight = 0x47
N2.C0.S07: VmseCmdFineTraining Final: centerPi = 0x5E, PiEw = 0x2F, centerVref = 0x37, vrefHeight = 0x43
N2.C0.S08: VmseCmdFineTraining Final: centerPi = 0x5B, PiEw = 0x2C, centerVref = 0x38, vrefHeight = 0x43
N2.C0.S09: VmseCmdFineTraining Final: centerPi = 0x5D, PiEw = 0x2F, centerVref = 0x3A, vrefHeight = 0x41
N2.C0.S10: VmseCmdFineTraining Final: centerPi = 0x5F, PiEw = 0x2C, centerVref = 0x37, vrefHeight = 0x47
N2.C0.S11: VmseCmdFineTraining Final: centerPi = 0x59, PiEw = 0x2C, centerVref = 0x37, vrefHeight = 0x45
N2.C0.S12: VmseCmdFineTraining Final: centerPi = 0x5F, PiEw = 0x30, centerVref = 0x39, vrefHeight = 0x47
N2.C0.S13: VmseCmdFineTraining Final: centerPi = 0x5A, PiEw = 0x2B, centerVref = 0x3A, vrefHeight = 0x41
N2.C0.S14: VmseCmdFineTraining Final: centerPi = 0x5F, PiEw = 0x30, centerVref = 0x3A, vrefHeight = 0x45
N2.C0.S15: VmseCmdFineTraining Final: centerPi = 0x62, PiEw = 0x2E, centerVref = 0x40, vrefHeight = 0x41
N2.C0.S16: VmseCmdFineTraining Final: centerPi = 0x5B, PiEw = 0x2D, centerVref = 0x39, vrefHeight = 0x41
Entry 0 - TrainDcc - DCCStart: 57, VocStart: 11, DCCFinal: 17, VocFinal: 11
Entry 1 - TrainDcc - DCCStart: 20, VocStart: 11, DCCFinal: 28, VocFinal: 11
Entry 0 - TrainDcc - DCCStart: 1, VocStart: 14, DCCFinal: 9, VocFinal: 14
Entry 1 - TrainDcc - DCCStart: 46, VocStart: 14, DCCFinal: 38, VocFinal: 14

END - VMSE Train Command               Time         7239 ms

START - VMSE Train Read Leveling
N2.C0: VmseReadLevelFineSetup: Initial RT = 101, Initial IO Latency = 0, Initial IO Comp = 15
N2.C0: VmseRLWLFineSearchAll: Entry
N2.C0: FINE READ LEVEL DELAY
N2.C0.S00: RCVEN DELAY = 153
N2.C0.S01: RCVEN DELAY = 153
N2.C0.S02: RCVEN DELAY = 43
N2.C0.S03: RCVEN DELAY = 49
N2.C0.S04: RCVEN DELAY = 59
N2.C0.S05: RCVEN DELAY = 131
N2.C0.S06: RCVEN DELAY = 56
N2.C0.S07: RCVEN DELAY = 128
N2.C0.S08: RCVEN DELAY = 85
N2.C0.S00: READ LEVEL: FINAL RCVEN DELAY (both nibbles) = 249
N2.C0.S01: READ LEVEL: FINAL RCVEN DELAY (both nibbles) = 249
N2.C0.S02: READ LEVEL: FINAL RCVEN DELAY (both nibbles) = 269
N2.C0.S03: READ LEVEL: FINAL RCVEN DELAY (both nibbles) = 275
N2.C0.S04: READ LEVEL: FINAL RCVEN DELAY (both nibbles) = 285
N2.C0.S05: READ LEVEL: FINAL RCVEN DELAY (both nibbles) = 229
N0.C0.S00: VmseCmdFineTraining Final: centerPi = 0x5F, PiEw = 0x31, centerVref = 0x40, vrefHeight = 0x39
N2.C0.S06: READ LEVEL: FINAL RCVEN DELAY (both nibbles) = 282
N0.C0.S01: VmseCmdFineTraining Final: centerPi = 0x5E, PiEw = 0x2E, centerVref = 0x3C, vrefHeight = 0x41
N2.C0.S07: READ LEVEL: FINAL RCVEN DELAY (both nibbles) = 224
N0.C0.S02: VmseCmdFineTraining Final: centerPi = 0x5C, PiEw = 0x32, centerVref = 0x39, vrefHeight = 0x43
N2.C0.S08: READ LEVEL: FINAL RCVEN DELAY (both nibbles) = 311
N0.C0.S03: VmseCmdFineTraining Final: centerPi = 0x5F, PiEw = 0x2F, centerVref = 0x3B, vrefHeight = 0x3D
N2.C0.D0.S09: READ LEVEL: FINAL RT (all ranks) = 85, FINAL IO LATENCY (all ranks) = 4
N0.C0.S04: VmseCmdFineTraining Final: centerPi = 0x56, PiEw = 0x31, centerVref = 0x41, vrefHeight = 0x3B
N2.C0.D1.S09: READ LEVEL: FINAL RT (all ranks) = 85, FINAL IO LATENCY (all ranks) = 4
N0.C0.S05: VmseCmdFineTraining Final: centerPi = 0x5A, PiEw = 0x31, centerVref = 0x3A, vrefHeight = 0x3D

END - VMSE Train Read Leveling         Time         320 ms
N0.C0.S06: VmseCmdFineTraining Final: centerPi = 0x5B, PiEw = 0x2F, centerVref = 0x3D, vrefHeight = 0x3F

START - VMSE Train Read
N0.C0.S07: VmseCmdFineTraining Final: centerPi = 0x5C, PiEw = 0x31, centerVref = 0x3D, vrefHeight = 0x3F
N0.C0.S08: VmseCmdFineTraining Final: centerPi = 0x57, PiEw = 0x31, centerVref = 0x41, vrefHeight = 0x3F
N0.C0.S09: VmseCmdFineTraining Final: centerPi = 0x5C, PiEw = 0x2E, centerVref = 0x3E, vrefHeight = 0x39
N0.C0.S10: VmseCmdFineTraining Final: centerPi = 0x5D, PiEw = 0x2F, centerVref = 0x3E, vrefHeight = 0x3D
N0.C0.S11: VmseCmdFineTraining Final: centerPi = 0x57, PiEw = 0x30, centerVref = 0x3B, vrefHeight = 0x41
N0.C0.S12: VmseCmdFineTraining Final: centerPi = 0x5F, PiEw = 0x31, centerVref = 0x3B, vrefHeight = 0x41
N0.C0.S13: VmseCmdFineTraining Final: centerPi = 0x56, PiEw = 0x30, centerVref = 0x3D, vrefHeight = 0x39
N0.C0.S14: VmseCmdFineTraining Final: centerPi = 0x5D, PiEw = 0x31, centerVref = 0x3F, vrefHeight = 0x41
N0.C0.S15: VmseCmdFineTraining Final: centerPi = 0x5E, PiEw = 0x30, centerVref = 0x40, vrefHeight = 0x35
N0.C0.S16: VmseCmdFineTraining Final: centerPi = 0x5B, PiEw = 0x2E, centerVref = 0x3D, vrefHeight = 0x41

END - VMSE Train Command               Time         7091 ms

START - VMSE Train Read Leveling
Checkpoint Code: Socket 0, 0xB6, 0x4E, 0x0000
N0.C0: VmseReadLevelFineSetup: Initial RT = 101, Initial IO Latency = 0, Initial IO Comp = 15
N0.C0: VmseRLWLFineSearchAll: Entry
N0.C0: FINE READ LEVEL DELAY
N0.C0.S00: RCVEN DELAY = 32
N0.C0.S01: RCVEN DELAY = 154
N0.C0.S02: RCVEN DELAY = 46
N0.C0.S03: RCVEN DELAY = 49
N0.C0.S04: RCVEN DELAY = 123
N0.C0.S05: RCVEN DELAY = 133
N0.C0.S06: RCVEN DELAY = 123
N0.C0.S07: RCVEN DELAY = 132
N0.C0.S08: RCVEN DELAY = 149
N0.C0.S00: READ LEVEL: FINAL RCVEN DELAY (both nibbles) = 131
N0.C0.S01: READ LEVEL: FINAL RCVEN DELAY (both nibbles) = 123
N4.C0.S00: VmseCmdFineTraining Final: centerPi = 0x63, PiEw = 0x31, centerVref = 0x34, vrefHeight = 0x41
N0.C0.S02: READ LEVEL: FINAL RCVEN DELAY (both nibbles) = 146
N4.C0.S01: VmseCmdFineTraining Final: centerPi = 0x5C, PiEw = 0x2D, centerVref = 0x42, vrefHeight = 0x41
N0.C0.S03: READ LEVEL: FINAL RCVEN DELAY (both nibbles) = 147
N4.C0.S02: VmseCmdFineTraining Final: centerPi = 0x5B, PiEw = 0x31, centerVref = 0x3E, vrefHeight = 0x3F
N6.C0.S00: VmseCmdFineTraining Final: centerPi = 0x60, PiEw = 0x2E, centerVref = 0x3C, vrefHeight = 0x41
N0.C0.S04: READ LEVEL: FINAL RCVEN DELAY (both nibbles) = 92
N4.C0.S03: VmseCmdFineTraining Final: centerPi = 0x5F, PiEw = 0x31, centerVref = 0x3D, vrefHeight = 0x43
N6.C0.S01: VmseCmdFineTraining Final: centerPi = 0x5E, PiEw = 0x2E, centerVref = 0x35, vrefHeight = 0x47
N0.C0.S05: READ LEVEL: FINAL RCVEN DELAY (both nibbles) = 101
N4.C0.S04: VmseCmdFineTraining Final: centerPi = 0x56, PiEw = 0x2F, centerVref = 0x3A, vrefHeight = 0x41
N6.C0.S02: VmseCmdFineTraining Final: centerPi = 0x5C, PiEw = 0x32, centerVref = 0x38, vrefHeight = 0x49
N0.C0.S06: READ LEVEL: FINAL RCVEN DELAY (both nibbles) = 92
N4.C0.S05: VmseCmdFineTraining Final: centerPi = 0x58, PiEw = 0x2F, centerVref = 0x3E, vrefHeight = 0x41
N6.C0.S03: VmseCmdFineTraining Final: centerPi = 0x61, PiEw = 0x31, centerVref = 0x39, vrefHeight = 0x43
N0.C0.S07: READ LEVEL: FINAL RCVEN DELAY (both nibbles) = 100
N4.C0.S06: VmseCmdFineTraining Final: centerPi = 0x61, PiEw = 0x32, centerVref = 0x31, vrefHeight = 0x47
N6.C0.S04: VmseCmdFineTraining Final: centerPi = 0x5A, PiEw = 0x29, centerVref = 0x3C, vrefHeight = 0x45
N0.C0.S08: READ LEVEL: FINAL RCVEN DELAY (both nibbles) = 118
N4.C0.S07: VmseCmdFineTraining Final: centerPi = 0x5D, PiEw = 0x30, centerVref = 0x37, vrefHeight = 0x41
N6.C0.S05: VmseCmdFineTraining Final: centerPi = 0x5A, PiEw = 0x2F, centerVref = 0x36, vrefHeight = 0x45
N0.C0.D0.S09: READ LEVEL: FINAL RT (all ranks) = 83, FINAL IO LATENCY (all ranks) = 2
N4.C0.S08: VmseCmdFineTraining Final: centerPi = 0x58, PiEw = 0x31, centerVref = 0x38, vrefHeight = 0x41
N6.C0.S06: VmseCmdFineTraining Final: centerPi = 0x5D, PiEw = 0x31, centerVref = 0x3A, vrefHeight = 0x49
N0.C0.D1.S09: READ LEVEL: FINAL RT (all ranks) = 83, FINAL IO LATENCY (all ranks) = 2
N4.C0.S09: VmseCmdFineTraining Final: centerPi = 0x5D, PiEw = 0x2F, centerVref = 0x3F, vrefHeight = 0x3D
N6.C0.S07: VmseCmdFineTraining Final: centerPi = 0x5D, PiEw = 0x30, centerVref = 0x34, vrefHeight = 0x47

END - VMSE Train Read Leveling         Time         449 ms
N4.C0.S10: VmseCmdFineTraining Final: centerPi = 0x5B, PiEw = 0x2F, centerVref = 0x41, vrefHeight = 0x3F
N6.C0.S08: VmseCmdFineTraining Final: centerPi = 0x5B, PiEw = 0x31, centerVref = 0x37, vrefHeight = 0x45

START - VMSE Train Read
N4.C0.S11: VmseCmdFineTraining Final: centerPi = 0x57, PiEw = 0x30, centerVref = 0x39, vrefHeight = 0x41
N6.C0.S09: VmseCmdFineTraining Final: centerPi = 0x5C, PiEw = 0x2E, centerVref = 0x3E, vrefHeight = 0x39
Checkpoint Code: Socket 0, 0xB6, 0x50, 0x0000
N4.C0.S12: VmseCmdFineTraining Final: centerPi = 0x5F, PiEw = 0x31, centerVref = 0x35, vrefHeight = 0x45
N6.C0.S10: VmseCmdFineTraining Final: centerPi = 0x5F, PiEw = 0x2F, centerVref = 0x3A, vrefHeight = 0x41
N4.C0.S13: VmseCmdFineTraining Final: centerPi = 0x57, PiEw = 0x30, centerVref = 0x3A, vrefHeight = 0x3D
N6.C0.S11: VmseCmdFineTraining Final: centerPi = 0x5A, PiEw = 0x2F, centerVref = 0x3A, vrefHeight = 0x47
N4.C0.S14: VmseCmdFineTraining Final: centerPi = 0x5E, PiEw = 0x32, centerVref = 0x3A, vrefHeight = 0x43
N6.C0.S12: VmseCmdFineTraining Final: centerPi = 0x5F, PiEw = 0x30, centerVref = 0x39, vrefHeight = 0x47
N4.C0.S15: VmseCmdFineTraining Final: centerPi = 0x60, PiEw = 0x2E, centerVref = 0x3C, vrefHeight = 0x41
N6.C0.S13: VmseCmdFineTraining Final: centerPi = 0x5A, PiEw = 0x30, centerVref = 0x34, vrefHeight = 0x45
N4.C0.S16: VmseCmdFineTraining Final: centerPi = 0x5C, PiEw = 0x2D, centerVref = 0x39, vrefHeight = 0x43
N6.C0.S14: VmseCmdFineTraining Final: centerPi = 0x5F, PiEw = 0x30, centerVref = 0x36, vrefHeight = 0x47
N6.C0.S15: VmseCmdFineTraining Final: centerPi = 0x64, PiEw = 0x30, centerVref = 0x32, vrefHeight = 0x45
N6.C0.S16: VmseCmdFineTraining Final: centerPi = 0x5F, PiEw = 0x2D, centerVref = 0x32, vrefHeight = 0x49

END - VMSE Train Command               Time         7942 ms

START - VMSE Train Read Leveling

END - VMSE Train Command               Time         7850 ms

START - VMSE Train Read Leveling
N4.C0: VmseReadLevelFineSetup: Initial RT = 101, Initial IO Latency = 0, Initial IO Comp = 15
N6.C0: VmseReadLevelFineSetup: Initial RT = 101, Initial IO Latency = 0, Initial IO Comp = 15
N4.C0: VmseRLWLFineSearchAll: Entry
N4.C0: FINE READ LEVEL DELAY
N4.C0.S00: RCVEN DELAY = 152
N4.C0.S01: RCVEN DELAY = 146
N4.C0.S02: RCVEN DELAY = 38
N4.C0.S03: RCVEN DELAY = 42
N4.C0.S04: RCVEN DELAY = 121
N4.C0.S05: RCVEN DELAY = 128
N4.C0.S06: RCVEN DELAY = 121
N4.C0.S07: RCVEN DELAY = 125
N4.C0.S08: RCVEN DELAY = 145
N6.C0: VmseRLWLFineSearchAll: Entry
N6.C0: FINE READ LEVEL DELAY
N4.C0.S00: READ LEVEL: FINAL RCVEN DELAY (both nibbles) = 250
N6.C0.S00: RCVEN DELAY = 31
N4.C0.S01: READ LEVEL: FINAL RCVEN DELAY (both nibbles) = 241
N6.C0.S01: RCVEN DELAY = 154
N4.C0.S02: READ LEVEL: FINAL RCVEN DELAY (both nibbles) = 264
N6.C0.S02: RCVEN DELAY = 43
N4.C0.S03: READ LEVEL: FINAL RCVEN DELAY (both nibbles) = 268
N6.C0.S03: RCVEN DELAY = 44
N4.C0.S04: READ LEVEL: FINAL RCVEN DELAY (both nibbles) = 218
N6.C0.S04: RCVEN DELAY = 125
N4.C0.S05: READ LEVEL: FINAL RCVEN DELAY (both nibbles) = 226
N6.C0.S05: RCVEN DELAY = 135
N4.C0.S06: READ LEVEL: FINAL RCVEN DELAY (both nibbles) = 218
N6.C0.S06: RCVEN DELAY = 125
N4.C0.S07: READ LEVEL: FINAL RCVEN DELAY (both nibbles) = 221
N6.C0.S07: RCVEN DELAY = 134
N4.C0.S08: READ LEVEL: FINAL RCVEN DELAY (both nibbles) = 241
N6.C0.S08: RCVEN DELAY = 149
N4.C0.D0.S09: READ LEVEL: FINAL RT (all ranks) = 85, FINAL IO LATENCY (all ranks) = 4
N6.C0.S00: READ LEVEL: FINAL RCVEN DELAY (both nibbles) = 129
N4.C0.D1.S09: READ LEVEL: FINAL RT (all ranks) = 85, FINAL IO LATENCY (all ranks) = 4
N6.C0.S01: READ LEVEL: FINAL RCVEN DELAY (both nibbles) = 123

END - VMSE Train Read Leveling         Time         302 ms
N6.C0.S02: READ LEVEL: FINAL RCVEN DELAY (both nibbles) = 142

START - VMSE Train Read
N6.C0.S03: READ LEVEL: FINAL RCVEN DELAY (both nibbles) = 142
N6.C0.S04: READ LEVEL: FINAL RCVEN DELAY (both nibbles) = 93
N6.C0.S05: READ LEVEL: FINAL RCVEN DELAY (both nibbles) = 104
N6.C0.S06: READ LEVEL: FINAL RCVEN DELAY (both nibbles) = 93
N6.C0.S07: READ LEVEL: FINAL RCVEN DELAY (both nibbles) = 102
N6.C0.S08: READ LEVEL: FINAL RCVEN DELAY (both nibbles) = 118
N6.C0.D0.S09: READ LEVEL: FINAL RT (all ranks) = 83, FINAL IO LATENCY (all ranks) = 2
N6.C0.D1.S09: READ LEVEL: FINAL RT (all ranks) = 83, FINAL IO LATENCY (all ranks) = 2

END - VMSE Train Read Leveling         Time         350 ms

START - VMSE Train Read

END - VMSE Train Read                  Time         3941 ms

START - VMSE Train Level Tx DQS DCC
N2.C0: VmseLevelTxDqsDccExecute: MXB DQS DCC Finished Successfully

END - VMSE Train Level Tx DQS DCC      Time         12 ms

START - VMSE Train Write Leveling
N2.C0: VmseWriteLevelFineSetup: Set push to data delay = 6, Global TX DQS delay = 0
N2.C0: VmseRLWLFineSearchAll: Entry
N2.C0: FINE WRITE LEVEL DELAY
N2.C0.S00: TX DQS DELAY = 118
N2.C0.S01: TX DQS DELAY = 118
N2.C0.S02: TX DQS DELAY = 93
N2.C0.S03: TX DQS DELAY = 96
N2.C0.S04: TX DQS DELAY = 87
N2.C0.S05: TX DQS DELAY = 142
N2.C0.S06: TX DQS DELAY = 84
N2.C0.S07: TX DQS DELAY = 142
N2.C0.S08: TX DQS DELAY = 50
N2.C0: VmseWriteLevelCoarseSetup: Set push to data delay = 6, Global TX DQS delay = 0
N2.C0: VmseWriteLevelCoarseExecute
N2.C0: VmseWLCoarseUpdatePD: New push to data delay = 6, New global TxDQS delay = 1
N2.C0: VmseWLCoarseUpdatePD: New push to data delay = 7, New global TxDQS delay = 0
N2.C0: VmseWLCoarseUpdatePD: New push to data delay = 7, New global TxDQS delay = 1
N2.C0: VmseWLCoarseUpdatePD: New push to data delay = 8, New global TxDQS delay = 0
N2.C0: VmseWLCoarseUpdatePD: New push to data delay = 8, New global TxDQS delay = 1
N2.C0.S00: FINAL TX DQS BEFORE TxFIFO CHECK = 216
N2.C0.S01: FINAL TX DQS BEFORE TxFIFO CHECK = 216
N2.C0.S02: FINAL TX DQS BEFORE TxFIFO CHECK = 192
N2.C0.S03: FINAL TX DQS BEFORE TxFIFO CHECK = 194
N2.C0.S04: FINAL TX DQS BEFORE TxFIFO CHECK = 313
N2.C0.S05: FINAL TX DQS BEFORE TxFIFO CHECK = 241
N2.C0.S06: FINAL TX DQS BEFORE TxFIFO CHECK = 311
N2.C0.S07: FINAL TX DQS BEFORE TxFIFO CHECK = 241
N2.C0.S08: FINAL TX DQS BEFORE TxFIFO CHECK = 275

END - VMSE Train Write Leveling        Time         156 ms

START - VMSE Train Write

END - VMSE Train Read                  Time         3955 ms

START - VMSE Train Level Tx DQS DCC
Checkpoint Code: Socket 0, 0xB6, 0x52, 0x0000
N0.C0: VmseLevelTxDqsDccExecute: MXB DQS DCC Finished Successfully
N0.C0.S08: VmseAdjustDqsVoc: retrain DQS DCC.
N0.C0.S08:    dcc1_dqs = 0x0, preampvoc = 0xB
N0.C0: VmseLevelTxDqsDccExecute: MXB DQS DCC Finished Successfully

END - VMSE Train Level Tx DQS DCC      Time         39 ms

START - VMSE Train Write Leveling
Checkpoint Code: Socket 0, 0xB6, 0x54, 0x0000
N0.C0: VmseWriteLevelFineSetup: Set push to data delay = 6, Global TX DQS delay = 0
N0.C0: VmseRLWLFineSearchAll: Entry
N0.C0: FINE WRITE LEVEL DELAY
N0.C0.S00: TX DQS DELAY = 114
N0.C0.S01: TX DQS DELAY = 113
N0.C0.S02: TX DQS DELAY = 100
N0.C0.S03: TX DQS DELAY = 98
N0.C0.S04: TX DQS DELAY = 144
N0.C0.S05: TX DQS DELAY = 142
N0.C0.S06: TX DQS DELAY = 144
N0.C0.S07: TX DQS DELAY = 142
N0.C0.S08: TX DQS DELAY = 115
N0.C0: VmseWriteLevelCoarseSetup: Set push to data delay = 6, Global TX DQS delay = 0
N0.C0: VmseWriteLevelCoarseExecute
Checkpoint Code: Socket 0, 0xB6, 0xAC, 0x0000
N0.C0: VmseWLCoarseUpdatePD: New push to data delay = 6, New global TxDQS delay = 1
N0.C0: VmseWLCoarseUpdatePD: New push to data delay = 7, New global TxDQS delay = 0
N0.C0: VmseWLCoarseUpdatePD: New push to data delay = 7, New global TxDQS delay = 1
N0.C0: VmseWLCoarseUpdatePD: New push to data delay = 8, New global TxDQS delay = 0
N0.C0.S00: FINAL TX DQS BEFORE TxFIFO CHECK = 84
N0.C0.S01: FINAL TX DQS BEFORE TxFIFO CHECK = 85
N0.C0.S02: FINAL TX DQS BEFORE TxFIFO CHECK = 70
N0.C0.S03: FINAL TX DQS BEFORE TxFIFO CHECK = 68
N0.C0.S04: FINAL TX DQS BEFORE TxFIFO CHECK = 114
N0.C0.S05: FINAL TX DQS BEFORE TxFIFO CHECK = 112
N0.C0.S06: FINAL TX DQS BEFORE TxFIFO CHECK = 114
N0.C0.S07: FINAL TX DQS BEFORE TxFIFO CHECK = 112
N0.C0.S08: FINAL TX DQS BEFORE TxFIFO CHECK = 86
N0.C0: ResolveTxFIFOPtrSeparation: Smallest PI (68) < MIN ALLOWED DELAY (176) 
N0.C0: VmseIncTxFifoPtrSeparation: New push to data delay = 7
N0.C0.S00: VmseIncTxFifoPtrSeparation: pi adjustment = 128, FINAL TX DQS DELAY = 340
N0.C0.S01: VmseIncTxFifoPtrSeparation: pi adjustment = 128, FINAL TX DQS DELAY = 341
N0.C0.S02: VmseIncTxFifoPtrSeparation: pi adjustment = 128, FINAL TX DQS DELAY = 326
N0.C0.S03: VmseIncTxFifoPtrSeparation: pi adjustment = 128, FINAL TX DQS DELAY = 324
N0.C0.S04: VmseIncTxFifoPtrSeparation: pi adjustment = 128, FINAL TX DQS DELAY = 370
N0.C0.S05: VmseIncTxFifoPtrSeparation: pi adjustment = 128, FINAL TX DQS DELAY = 368
N0.C0.S06: VmseIncTxFifoPtrSeparation: pi adjustment = 128, FINAL TX DQS DELAY = 370
N0.C0.S07: VmseIncTxFifoPtrSeparation: pi adjustment = 128, FINAL TX DQS DELAY = 368
N0.C0.S08: VmseIncTxFifoPtrSeparation: pi adjustment = 128, FINAL TX DQS DELAY = 342

END - VMSE Train Write Leveling        Time         253 ms

START - VMSE Train Write
Checkpoint Code: Socket 0, 0xB6, 0x56, 0x0000
N0.C0.S58: ParamSweep: EdgeLeft = 0x3D EdgeRight = 0x43 MinEyeSize not reached 

END - VMSE Train Read                  Time         3794 ms

START - VMSE Train Level Tx DQS DCC

END - VMSE Train Read                  Time         3875 ms
N6.C0: VmseLevelTxDqsDccExecute: MXB DQS DCC Finished Successfully

START - VMSE Train Level Tx DQS DCC

END - VMSE Train Level Tx DQS DCC      Time         14 ms
N4.C0: VmseLevelTxDqsDccExecute: MXB DQS DCC Finished Successfully

START - VMSE Train Write Leveling
Entry 0 - TrainDcc - DCCStart: 29, VocStart: 9, DCCFinal: 29, VocFinal: 9
N4.C0.S07: VmseAdjustDqsVoc: retrain DQS DCC.
N6.C0: VmseWriteLevelFineSetup: Set push to data delay = 6, Global TX DQS delay = 0
Entry 1 - TrainDcc - DCCStart: 52, VocStart: 12, DCCFinal: 52, VocFinal: 12
N4.C0.S07:    dcc1_dqs = 0x0, preampvoc = 0xC
N6.C0: VmseRLWLFineSearchAll: Entry
Entry 2 - TrainDcc - DCCStart: 10, VocStart: 16, DCCFinal: 42, VocFinal: 16
N4.C0: VmseLevelTxDqsDccExecute: MXB DQS DCC Finished Successfully
N6.C0: FINE WRITE LEVEL DELAY
Entry 3 - TrainDcc - DCCStart: 21, VocStart: 13, DCCFinal: 21, VocFinal: 13
N4.C0.S03: VmseAdjustDqsVoc: retrain DQS DCC.
N6.C0.S00: TX DQS DELAY = 116
Entry 4 - TrainDcc - DCCStart: 42, VocStart: 8, DCCFinal: 42, VocFinal: 9
N4.C0.S03:    dcc1_dqs = 0x0, preampvoc = 0x11
N6.C0.S01: TX DQS DELAY = 117
Entry 5 - TrainDcc - DCCStart: 19, VocStart: 16, DCCFinal: 19, VocFinal: 16
N4.C0: VmseLevelTxDqsDccExecute: MXB DQS DCC Finished Successfully
N6.C0.S02: TX DQS DELAY = 101
Entry 6 - TrainDcc - DCCStart: 43, VocStart: 11, DCCFinal: 43, VocFinal: 11

END - VMSE Train Level Tx DQS DCC      Time         122 ms
N6.C0.S03: TX DQS DELAY = 102
Entry 7 - TrainDcc - DCCStart: 4, VocStart: 16, DCCFinal: 4, VocFinal: 16

START - VMSE Train Write Leveling
N6.C0.S04: TX DQS DELAY = 149
Entry 8 - TrainDcc - DCCStart: 14, VocStart: 12, DCCFinal: 14, VocFinal: 12
N4.C0: VmseWriteLevelFineSetup: Set push to data delay = 6, Global TX DQS delay = 0
N6.C0.S05: TX DQS DELAY = 143
N0.C0.S58: ParamSweep: EdgeLeft = 0x40 EdgeRight = 0x45 MinEyeSize not reached 
N4.C0: VmseRLWLFineSearchAll: Entry
N6.C0.S06: TX DQS DELAY = 146
N4.C0: FINE WRITE LEVEL DELAY
N6.C0.S07: TX DQS DELAY = 143
N4.C0.S00: TX DQS DELAY = 104
N6.C0.S08: TX DQS DELAY = 115
N4.C0.S01: TX DQS DELAY = 108
N6.C0: VmseWriteLevelCoarseSetup: Set push to data delay = 6, Global TX DQS delay = 0
N4.C0.S02: TX DQS DELAY = 91
N6.C0: VmseWriteLevelCoarseExecute
N4.C0.S03: TX DQS DELAY = 89
N6.C0: VmseWLCoarseUpdatePD: New push to data delay = 6, New global TxDQS delay = 1
N4.C0.S04: TX DQS DELAY = 142
N6.C0: VmseWLCoarseUpdatePD: New push to data delay = 7, New global TxDQS delay = 0
N4.C0.S05: TX DQS DELAY = 132
N6.C0: VmseWLCoarseUpdatePD: New push to data delay = 7, New global TxDQS delay = 1
N4.C0.S06: TX DQS DELAY = 139
N6.C0: VmseWLCoarseUpdatePD: New push to data delay = 8, New global TxDQS delay = 0
N4.C0.S07: TX DQS DELAY = 132
N6.C0.S00: FINAL TX DQS BEFORE TxFIFO CHECK = 86
N4.C0.S08: TX DQS DELAY = 108
N6.C0.S01: FINAL TX DQS BEFORE TxFIFO CHECK = 86
N4.C0: VmseWriteLevelCoarseSetup: Set push to data delay = 6, Global TX DQS delay = 0
N6.C0.S02: FINAL TX DQS BEFORE TxFIFO CHECK = 71
N4.C0: VmseWriteLevelCoarseExecute
N6.C0.S03: FINAL TX DQS BEFORE TxFIFO CHECK = 72
N4.C0: VmseWLCoarseUpdatePD: New push to data delay = 6, New global TxDQS delay = 1
N6.C0.S04: FINAL TX DQS BEFORE TxFIFO CHECK = 119
N4.C0: VmseWLCoarseUpdatePD: New push to data delay = 7, New global TxDQS delay = 0
N6.C0.S05: FINAL TX DQS BEFORE TxFIFO CHECK = 114
N4.C0: VmseWLCoarseUpdatePD: New push to data delay = 7, New global TxDQS delay = 1
N6.C0.S06: FINAL TX DQS BEFORE TxFIFO CHECK = 117
N4.C0: VmseWLCoarseUpdatePD: New push to data delay = 8, New global TxDQS delay = 0
N6.C0.S07: FINAL TX DQS BEFORE TxFIFO CHECK = 114
N4.C0: VmseWLCoarseUpdatePD: New push to data delay = 8, New global TxDQS delay = 1
N6.C0.S08: FINAL TX DQS BEFORE TxFIFO CHECK = 85
N4.C0.S00: FINAL TX DQS BEFORE TxFIFO CHECK = 202
N6.C0: ResolveTxFIFOPtrSeparation: Smallest PI (71) < MIN ALLOWED DELAY (176) 
N4.C0.S01: FINAL TX DQS BEFORE TxFIFO CHECK = 205
N6.C0: VmseIncTxFifoPtrSeparation: New push to data delay = 7
N4.C0.S02: FINAL TX DQS BEFORE TxFIFO CHECK = 189
N6.C0.S00: VmseIncTxFifoPtrSeparation: pi adjustment = 128, FINAL TX DQS DELAY = 342
N4.C0.S03: FINAL TX DQS BEFORE TxFIFO CHECK = 190
N6.C0.S01: VmseIncTxFifoPtrSeparation: pi adjustment = 128, FINAL TX DQS DELAY = 342
N4.C0.S04: FINAL TX DQS BEFORE TxFIFO CHECK = 240
N6.C0.S02: VmseIncTxFifoPtrSeparation: pi adjustment = 128, FINAL TX DQS DELAY = 327
N4.C0.S05: FINAL TX DQS BEFORE TxFIFO CHECK = 230
N6.C0.S03: VmseIncTxFifoPtrSeparation: pi adjustment = 128, FINAL TX DQS DELAY = 328
N2.C0.S00: VmseWriteTraining Final: centerPi = 0x3C, PiEw = 0x2A, centerVref = 0x40, vrefHeight = 0x30
N4.C0.S06: FINAL TX DQS BEFORE TxFIFO CHECK = 236
N6.C0.S04: VmseIncTxFifoPtrSeparation: pi adjustment = 128, FINAL TX DQS DELAY = 375
N2.C0.S01: VmseWriteTraining Final: centerPi = 0x3C, PiEw = 0x29, centerVref = 0x3E, vrefHeight = 0x2E
N4.C0.S07: FINAL TX DQS BEFORE TxFIFO CHECK = 231
N6.C0.S05: VmseIncTxFifoPtrSeparation: pi adjustment = 128, FINAL TX DQS DELAY = 370
N2.C0.S02: VmseWriteTraining Final: centerPi = 0x3A, PiEw = 0x23, centerVref = 0x3E, vrefHeight = 0x2C
N4.C0.S08: FINAL TX DQS BEFORE TxFIFO CHECK = 206
N6.C0.S06: VmseIncTxFifoPtrSeparation: pi adjustment = 128, FINAL TX DQS DELAY = 373
N2.C0.S03: VmseWriteTraining Final: centerPi = 0x39, PiEw = 0x24, centerVref = 0x3E, vrefHeight = 0x2E

END - VMSE Train Write Leveling        Time         383 ms
N6.C0.S07: VmseIncTxFifoPtrSeparation: pi adjustment = 128, FINAL TX DQS DELAY = 370
N2.C0.S04: VmseWriteTraining Final: centerPi = 0x3E, PiEw = 0x23, centerVref = 0x3E, vrefHeight = 0x2A

START - VMSE Train Write
N6.C0.S08: VmseIncTxFifoPtrSeparation: pi adjustment = 128, FINAL TX DQS DELAY = 341
N2.C0.S05: VmseWriteTraining Final: centerPi = 0x40, PiEw = 0x28, centerVref = 0x3C, vrefHeight = 0x2E

END - VMSE Train Write Leveling        Time         580 ms
N2.C0.S06: VmseWriteTraining Final: centerPi = 0x3F, PiEw = 0x26, centerVref = 0x3B, vrefHeight = 0x2C

START - VMSE Train Write
N2.C0.S07: VmseWriteTraining Final: centerPi = 0x3C, PiEw = 0x25, centerVref = 0x3E, vrefHeight = 0x28
N2.C0.S08: VmseWriteTraining Final: centerPi = 0x39, PiEw = 0x29, centerVref = 0x3F, vrefHeight = 0x2E
N2.C0.S09: VmseWriteTraining Final: centerPi = 0x3A, PiEw = 0x29, centerVref = 0x3D, vrefHeight = 0x2C
N2.C0.S10: VmseWriteTraining Final: centerPi = 0x37, PiEw = 0x26, centerVref = 0x3E, vrefHeight = 0x2E
N2.C0.S11: VmseWriteTraining Final: centerPi = 0x35, PiEw = 0x2C, centerVref = 0x43, vrefHeight = 0x2E
N2.C0.S12: VmseWriteTraining Final: centerPi = 0x3E, PiEw = 0x29, centerVref = 0x3E, vrefHeight = 0x2C
N2.C0.S13: VmseWriteTraining Final: centerPi = 0x3B, PiEw = 0x28, centerVref = 0x3D, vrefHeight = 0x2A
N2.C0.S14: VmseWriteTraining Final: centerPi = 0x3F, PiEw = 0x26, centerVref = 0x3D, vrefHeight = 0x30
N2.C0.S15: VmseWriteTraining Final: centerPi = 0x3D, PiEw = 0x2B, centerVref = 0x42, vrefHeight = 0x2E
N2.C0.S16: VmseWriteTraining Final: centerPi = 0x3B, PiEw = 0x23, centerVref = 0x40, vrefHeight = 0x24
N2.C0.S17: VmseWriteTraining Final: centerPi = 0x3C, PiEw = 0x24, centerVref = 0x3E, vrefHeight = 0x2A
N2.C0.S18: VmseWriteTraining Final: centerPi = 0x38, PiEw = 0x24, centerVref = 0x3F, vrefHeight = 0x2A
N2.C0.S19: VmseWriteTraining Final: centerPi = 0x37, PiEw = 0x2B, centerVref = 0x3E, vrefHeight = 0x2A
N2.C0.S20: VmseWriteTraining Final: centerPi = 0x40, PiEw = 0x27, centerVref = 0x3E, vrefHeight = 0x28
N2.C0.S21: VmseWriteTraining Final: centerPi = 0x3F, PiEw = 0x27, centerVref = 0x3B, vrefHeight = 0x2A
N2.C0.S22: VmseWriteTraining Final: centerPi = 0x3C, PiEw = 0x24, centerVref = 0x41, vrefHeight = 0x2A
N2.C0.S23: VmseWriteTraining Final: centerPi = 0x3F, PiEw = 0x28, centerVref = 0x42, vrefHeight = 0x2A
N2.C0.S24: VmseWriteTraining Final: centerPi = 0x3C, PiEw = 0x29, centerVref = 0x41, vrefHeight = 0x2A
N2.C0.S25: VmseWriteTraining Final: centerPi = 0x3A, PiEw = 0x26, centerVref = 0x42, vrefHeight = 0x2C
N2.C0.S26: VmseWriteTraining Final: centerPi = 0x39, PiEw = 0x25, centerVref = 0x40, vrefHeight = 0x2A
N2.C0.S27: VmseWriteTraining Final: centerPi = 0x37, PiEw = 0x28, centerVref = 0x3F, vrefHeight = 0x2C
N2.C0.S28: VmseWriteTraining Final: centerPi = 0x3F, PiEw = 0x27, centerVref = 0x3A, vrefHeight = 0x2E
Entry 0 - TrainDcc - DCCStart: 14, VocStart: 12, DCCFinal: 30, VocFinal: 12
N2.C0.S29: VmseWriteTraining Final: centerPi = 0x3A, PiEw = 0x1F, centerVref = 0x41, vrefHeight = 0x24
Entry 1 - TrainDcc - DCCStart: 3, VocStart: 9, DCCFinal: 3, VocFinal: 9
N2.C0.S30: VmseWriteTraining Final: centerPi = 0x3D, PiEw = 0x27, centerVref = 0x3D, vrefHeight = 0x2C
Entry 2 - TrainDcc - DCCStart: 15, VocStart: 9, DCCFinal: 15, VocFinal: 9
N2.C0.S31: VmseWriteTraining Final: centerPi = 0x3C, PiEw = 0x29, centerVref = 0x42, vrefHeight = 0x2A
Entry 3 - TrainDcc - DCCStart: 19, VocStart: 14, DCCFinal: 19, VocFinal: 14
N2.C0.S32: VmseWriteTraining Final: centerPi = 0x3A, PiEw = 0x29, centerVref = 0x3F, vrefHeight = 0x30
Entry 4 - TrainDcc - DCCStart: 1, VocStart: 17, DCCFinal: 1, VocFinal: 26
N2.C0.S33: VmseWriteTraining Final: centerPi = 0x3D, PiEw = 0x29, centerVref = 0x39, vrefHeight = 0x34
Entry 5 - TrainDcc - DCCStart: 21, VocStart: 13, DCCFinal: 21, VocFinal: 13
N2.C0.S34: VmseWriteTraining Final: centerPi = 0x37, PiEw = 0x2A, centerVref = 0x42, vrefHeight = 0x32
Entry 6 - TrainDcc - DCCStart: 30, VocStart: 13, DCCFinal: 30, VocFinal: 15
N2.C0.S35: VmseWriteTraining Final: centerPi = 0x36, PiEw = 0x29, centerVref = 0x39, vrefHeight = 0x32
Entry 7 - TrainDcc - DCCStart: 18, VocStart: 9, DCCFinal: 18, VocFinal: 9
N2.C0.S36: VmseWriteTraining Final: centerPi = 0x3C, PiEw = 0x2A, centerVref = 0x3E, vrefHeight = 0x30
Entry 8 - TrainDcc - DCCStart: 6, VocStart: 11, DCCFinal: 6, VocFinal: 11
N2.C0.S37: VmseWriteTraining Final: centerPi = 0x40, PiEw = 0x29, centerVref = 0x34, vrefHeight = 0x30
N2.C0.S38: VmseWriteTraining Final: centerPi = 0x3A, PiEw = 0x27, centerVref = 0x3E, vrefHeight = 0x30
N2.C0.S39: VmseWriteTraining Final: centerPi = 0x3D, PiEw = 0x2B, centerVref = 0x3C, vrefHeight = 0x32
N2.C0.S40: VmseWriteTraining Final: centerPi = 0x3A, PiEw = 0x2C, centerVref = 0x3E, vrefHeight = 0x2E
N2.C0.S41: VmseWriteTraining Final: centerPi = 0x3B, PiEw = 0x26, centerVref = 0x3C, vrefHeight = 0x2E
N2.C0.S42: VmseWriteTraining Final: centerPi = 0x37, PiEw = 0x27, centerVref = 0x3C, vrefHeight = 0x2C
N2.C0.S43: VmseWriteTraining Final: centerPi = 0x3A, PiEw = 0x2B, centerVref = 0x3F, vrefHeight = 0x30
N2.C0.S44: VmseWriteTraining Final: centerPi = 0x3E, PiEw = 0x2B, centerVref = 0x41, vrefHeight = 0x2C
N2.C0.S45: VmseWriteTraining Final: centerPi = 0x40, PiEw = 0x28, centerVref = 0x41, vrefHeight = 0x2C
N2.C0.S46: VmseWriteTraining Final: centerPi = 0x3B, PiEw = 0x27, centerVref = 0x3E, vrefHeight = 0x2C
N2.C0.S47: VmseWriteTraining Final: centerPi = 0x3D, PiEw = 0x2A, centerVref = 0x42, vrefHeight = 0x2C
N2.C0.S48: VmseWriteTraining Final: centerPi = 0x3A, PiEw = 0x28, centerVref = 0x3B, vrefHeight = 0x2C
N2.C0.S49: VmseWriteTraining Final: centerPi = 0x3A, PiEw = 0x29, centerVref = 0x37, vrefHeight = 0x32
N2.C0.S50: VmseWriteTraining Final: centerPi = 0x38, PiEw = 0x25, centerVref = 0x3E, vrefHeight = 0x2E
N2.C0.S51: VmseWriteTraining Final: centerPi = 0x36, PiEw = 0x27, centerVref = 0x39, vrefHeight = 0x30
N2.C0.S52: VmseWriteTraining Final: centerPi = 0x3B, PiEw = 0x26, centerVref = 0x3B, vrefHeight = 0x2E
N2.C0.S53: VmseWriteTraining Final: centerPi = 0x3B, PiEw = 0x26, centerVref = 0x40, vrefHeight = 0x2C
N2.C0.S54: VmseWriteTraining Final: centerPi = 0x3D, PiEw = 0x25, centerVref = 0x3D, vrefHeight = 0x30
N2.C0.S55: VmseWriteTraining Final: centerPi = 0x3B, PiEw = 0x28, centerVref = 0x3E, vrefHeight = 0x2E
N2.C0.S56: VmseWriteTraining Final: centerPi = 0x3F, PiEw = 0x2A, centerVref = 0x3E, vrefHeight = 0x2E
N2.C0.S57: VmseWriteTraining Final: centerPi = 0x3F, PiEw = 0x2A, centerVref = 0x3D, vrefHeight = 0x2E
N2.C0.S58: VmseWriteTraining Final: centerPi = 0x3C, PiEw = 0x28, centerVref = 0x3F, vrefHeight = 0x2E
N2.C0.S59: VmseWriteTraining Final: centerPi = 0x3A, PiEw = 0x2A, centerVref = 0x3E, vrefHeight = 0x2C
N2.C0.S60: VmseWriteTraining Final: centerPi = 0x44, PiEw = 0x29, centerVref = 0x3B, vrefHeight = 0x2E
N2.C0.S61: VmseWriteTraining Final: centerPi = 0x42, PiEw = 0x25, centerVref = 0x42, vrefHeight = 0x2C
N2.C0.S62: VmseWriteTraining Final: centerPi = 0x42, PiEw = 0x25, centerVref = 0x3B, vrefHeight = 0x2C
N0.C0.S00: VmseWriteTraining Final: centerPi = 0x39, PiEw = 0x2C, centerVref = 0x43, vrefHeight = 0x28
N2.C0.S63: VmseWriteTraining Final: centerPi = 0x40, PiEw = 0x2C, centerVref = 0x40, vrefHeight = 0x2C
N0.C0.S01: VmseWriteTraining Final: centerPi = 0x39, PiEw = 0x28, centerVref = 0x3D, vrefHeight = 0x26
N2.C0.S64: VmseWriteTraining Final: centerPi = 0x3C, PiEw = 0x28, centerVref = 0x43, vrefHeight = 0x2C
N0.C0.S02: VmseWriteTraining Final: centerPi = 0x39, PiEw = 0x25, centerVref = 0x40, vrefHeight = 0x26
N2.C0.S65: VmseWriteTraining Final: centerPi = 0x3C, PiEw = 0x23, centerVref = 0x3F, vrefHeight = 0x2E
N0.C0.S03: VmseWriteTraining Final: centerPi = 0x39, PiEw = 0x25, centerVref = 0x41, vrefHeight = 0x28
N2.C0.S66: VmseWriteTraining Final: centerPi = 0x3A, PiEw = 0x1F, centerVref = 0x3B, vrefHeight = 0x2C
N0.C0.S04: VmseWriteTraining Final: centerPi = 0x3D, PiEw = 0x23, centerVref = 0x40, vrefHeight = 0x24
N2.C0.S67: VmseWriteTraining Final: centerPi = 0x3C, PiEw = 0x20, centerVref = 0x3E, vrefHeight = 0x30
N0.C0.S05: VmseWriteTraining Final: centerPi = 0x3D, PiEw = 0x27, centerVref = 0x44, vrefHeight = 0x26
N2.C0.S68: VmseWriteTraining Final: centerPi = 0x3F, PiEw = 0x25, centerVref = 0x3D, vrefHeight = 0x2C
N0.C0.S06: VmseWriteTraining Final: centerPi = 0x3D, PiEw = 0x26, centerVref = 0x42, vrefHeight = 0x26
N2.C0.S69: VmseWriteTraining Final: centerPi = 0x3F, PiEw = 0x28, centerVref = 0x45, vrefHeight = 0x2E
N0.C0.S07: VmseWriteTraining Final: centerPi = 0x3E, PiEw = 0x25, centerVref = 0x3B, vrefHeight = 0x24
N2.C0.S70: VmseWriteTraining Final: centerPi = 0x3E, PiEw = 0x22, centerVref = 0x3C, vrefHeight = 0x2A
N0.C0.S08: VmseWriteTraining Final: centerPi = 0x3D, PiEw = 0x27, centerVref = 0x41, vrefHeight = 0x28
N2.C0.S71: VmseWriteTraining Final: centerPi = 0x3F, PiEw = 0x26, centerVref = 0x3E, vrefHeight = 0x2E
N0.C0.S09: VmseWriteTraining Final: centerPi = 0x3D, PiEw = 0x23, centerVref = 0x3F, vrefHeight = 0x28

END - VMSE Train Write                 Time         2661 ms
N0.C0.S10: VmseWriteTraining Final: centerPi = 0x3A, PiEw = 0x22, centerVref = 0x40, vrefHeight = 0x2A
N2: 
Total VMSE trainings latency = 14874 ms
N0.C0.S11: VmseWriteTraining Final: centerPi = 0x3A, PiEw = 0x23, centerVref = 0x42, vrefHeight = 0x28
N2: CpgcVmseTraining for VMSE1
N0.C0.S12: VmseWriteTraining Final: centerPi = 0x40, PiEw = 0x25, centerVref = 0x3D, vrefHeight = 0x28
N2: Initialize VMSE Channels
N0.C0.S13: VmseWriteTraining Final: centerPi = 0x3F, PiEw = 0x23, centerVref = 0x46, vrefHeight = 0x26

START - VMSE Detect DC
N0.C0.S14: VmseWriteTraining Final: centerPi = 0x40, PiEw = 0x24, centerVref = 0x3E, vrefHeight = 0x2A
N2: HsxVmseCompInit
N0.C0.S15: VmseWriteTraining Final: centerPi = 0x41, PiEw = 0x24, centerVref = 0x3A, vrefHeight = 0x28
N0.C0.S16: VmseWriteTraining Final: centerPi = 0x3C, PiEw = 0x28, centerVref = 0x45, vrefHeight = 0x22
N2.C1: Skip DC Detect check for CMD results
N0.C0.S17: VmseWriteTraining Final: centerPi = 0x3E, PiEw = 0x26, centerVref = 0x3E, vrefHeight = 0x26
N0.C0.S18: VmseWriteTraining Final: centerPi = 0x3A, PiEw = 0x26, centerVref = 0x40, vrefHeight = 0x26
N2.C1: Skip DC Detect check for CMD results
N0.C0.S19: VmseWriteTraining Final: centerPi = 0x3A, PiEw = 0x26, centerVref = 0x43, vrefHeight = 0x28
N2: HsxVmseCompInit
N0.C0.S20: VmseWriteTraining Final: centerPi = 0x41, PiEw = 0x23, centerVref = 0x3E, vrefHeight = 0x26
N2.C1: VmseDetectDC: SUCCESS
Entry 0 - TrainDcc - DCCStart: 12, VocStart: 14, DCCFinal: 28, VocFinal: 14
N0.C0.S21: VmseWriteTraining Final: centerPi = 0x3F, PiEw = 0x23, centerVref = 0x43, vrefHeight = 0x22
N2.C1: VmseDetectClock
Entry 1 - TrainDcc - DCCStart: 9, VocStart: 7, DCCFinal: 9, VocFinal: 7
N0.C0.S22: VmseWriteTraining Final: centerPi = 0x3B, PiEw = 0x21, centerVref = 0x3F, vrefHeight = 0x24
Entry 2 - TrainDcc - DCCStart: 14, VocStart: 14, DCCFinal: 63, VocFinal: 15
N0.C0.S23: VmseWriteTraining Final: centerPi = 0x3F, PiEw = 0x25, centerVref = 0x41, vrefHeight = 0x26
Entry 3 - TrainDcc - DCCStart: 5, VocStart: 17, DCCFinal: 5, VocFinal: 17
Entry 0 - TrainDcc - DCCStart: 24, VocStart: 16, DCCFinal: 24, VocFinal: 16
N0.C0.S24: VmseWriteTraining Final: centerPi = 0x3A, PiEw = 0x29, centerVref = 0x40, vrefHeight = 0x22
Entry 4 - TrainDcc - DCCStart: 14, VocStart: 12, DCCFinal: 14, VocFinal: 21
Entry 1 - TrainDcc - DCCStart: 18, VocStart: 11, DCCFinal: 18, VocFinal: 11
N0.C0.S25: VmseWriteTraining Final: centerPi = 0x3A, PiEw = 0x26, centerVref = 0x3E, vrefHeight = 0x26
Entry 5 - TrainDcc - DCCStart: 5, VocStart: 13, DCCFinal: 5, VocFinal: 13
Entry 2 - TrainDcc - DCCStart: 10, VocStart: 13, DCCFinal: 10, VocFinal: 13
N0.C0.S26: VmseWriteTraining Final: centerPi = 0x38, PiEw = 0x21, centerVref = 0x40, vrefHeight = 0x26
Entry 6 - TrainDcc - DCCStart: 7, VocStart: 9, DCCFinal: 7, VocFinal: 13
Entry 3 - TrainDcc - DCCStart: 10, VocStart: 9, DCCFinal: 10, VocFinal: 9
N0.C0.S27: VmseWriteTraining Final: centerPi = 0x39, PiEw = 0x2A, centerVref = 0x3F, vrefHeight = 0x28
Entry 7 - TrainDcc - DCCStart: 4, VocStart: 12, DCCFinal: 4, VocFinal: 12
Entry 4 - TrainDcc - DCCStart: 26, VocStart: 12, DCCFinal: 26, VocFinal: 13
N0.C0.S28: VmseWriteTraining Final: centerPi = 0x3E, PiEw = 0x27, centerVref = 0x40, vrefHeight = 0x26
N2.C1: VmseDetectClock: SUCCESS
Entry 8 - TrainDcc - DCCStart: 14, VocStart: 16, DCCFinal: 14, VocFinal: 16
Entry 5 - TrainDcc - DCCStart: 10, VocStart: 13, DCCFinal: 10, VocFinal: 13
N0.C0.S29: VmseWriteTraining Final: centerPi = 0x3D, PiEw = 0x28, centerVref = 0x41, vrefHeight = 0x24

END - VMSE Detect DC                   Time         291 ms
Entry 6 - TrainDcc - DCCStart: 10, VocStart: 12, DCCFinal: 10, VocFinal: 17
N0.C0.S30: VmseWriteTraining Final: centerPi = 0x3E, PiEw = 0x26, centerVref = 0x41, vrefHeight = 0x24

START - MXB Clock Train
Entry 7 - TrainDcc - DCCStart: 12, VocStart: 17, DCCFinal: 12, VocFinal: 17
N0.C0.S31: VmseWriteTraining Final: centerPi = 0x3F, PiEw = 0x2A, centerVref = 0x42, vrefHeight = 0x26
Entry 8 - TrainDcc - DCCStart: 10, VocStart: 13, DCCFinal: 10, VocFinal: 13
N0.C0.S32: VmseWriteTraining Final: centerPi = 0x3C, PiEw = 0x2B, centerVref = 0x41, vrefHeight = 0x28
N0.C0.S33: VmseWriteTraining Final: centerPi = 0x3E, PiEw = 0x28, centerVref = 0x3C, vrefHeight = 0x2A
N0.C0.S34: VmseWriteTraining Final: centerPi = 0x3D, PiEw = 0x29, centerVref = 0x43, vrefHeight = 0x2C
N0.C0.S35: VmseWriteTraining Final: centerPi = 0x3A, PiEw = 0x26, centerVref = 0x3A, vrefHeight = 0x28
N0.C0.S36: VmseWriteTraining Final: centerPi = 0x42, PiEw = 0x28, centerVref = 0x3E, vrefHeight = 0x2A
N0.C0.S37: VmseWriteTraining Final: centerPi = 0x40, PiEw = 0x28, centerVref = 0x3F, vrefHeight = 0x28
N2.C2: VmseRefVckResync: ddrFreq = 0x2, VMSE_MODE_2_1 = 1, VMSE_PREAMBLE_2UI = 0
N0.C0.S38: VmseWriteTraining Final: centerPi = 0x3D, PiEw = 0x26, centerVref = 0x3D, vrefHeight = 0x28
N0.C0.S39: VmseWriteTraining Final: centerPi = 0x43, PiEw = 0x28, centerVref = 0x36, vrefHeight = 0x2C
N0.C0.S40: VmseWriteTraining Final: centerPi = 0x37, PiEw = 0x2C, centerVref = 0x42, vrefHeight = 0x26
N2.C2: VmseRefVckResync: VLINKFREQNXT set to: 0x20F940A
N0.C0.S41: VmseWriteTraining Final: centerPi = 0x3B, PiEw = 0x27, centerVref = 0x3D, vrefHeight = 0x28
N0.C0.S42: VmseWriteTraining Final: centerPi = 0x3A, PiEw = 0x27, centerVref = 0x3E, vrefHeight = 0x2A
N0.C0.S43: VmseWriteTraining Final: centerPi = 0x38, PiEw = 0x24, centerVref = 0x3F, vrefHeight = 0x28
N2.C1: VmseTrainClockAlign: JCK clkadjcnt =0
N0.C0.S44: VmseWriteTraining Final: centerPi = 0x3D, PiEw = 0x28, centerVref = 0x3D, vrefHeight = 0x28

END - MXB Clock Train                  Time         183 ms
N0.C0.S45: VmseWriteTraining Final: centerPi = 0x3F, PiEw = 0x27, centerVref = 0x3E, vrefHeight = 0x28

START - VMSE Train Command
N0.C0.S46: VmseWriteTraining Final: centerPi = 0x3C, PiEw = 0x24, centerVref = 0x3E, vrefHeight = 0x26
N0.C0.S47: VmseWriteTraining Final: centerPi = 0x3D, PiEw = 0x27, centerVref = 0x3E, vrefHeight = 0x2A
N2.C1.B00: HsxCtlXoverInit: invertPiClk = 0x0, RankUsed = 0xFFF, Training = 0x38FFF25
N4.C0.S00: VmseWriteTraining Final: centerPi = 0x3A, PiEw = 0x2B, centerVref = 0x47, vrefHeight = 0x28
N0.C0.S48: VmseWriteTraining Final: centerPi = 0x3A, PiEw = 0x23, centerVref = 0x41, vrefHeight = 0x24
N2.C1.B01: HsxCtlXoverInit: invertPiClk = 0x0, RankUsed = 0xFFF, Training = 0x38FFF02
N4.C0.S01: VmseWriteTraining Final: centerPi = 0x39, PiEw = 0x26, centerVref = 0x3F, vrefHeight = 0x24
N0.C0.S49: VmseWriteTraining Final: centerPi = 0x39, PiEw = 0x2B, centerVref = 0x43, vrefHeight = 0x2A
N4.C0.S02: VmseWriteTraining Final: centerPi = 0x3A, PiEw = 0x26, centerVref = 0x41, vrefHeight = 0x28
N0.C0.S50: VmseWriteTraining Final: centerPi = 0x38, PiEw = 0x27, centerVref = 0x3B, vrefHeight = 0x24
N4.C0.S03: VmseWriteTraining Final: centerPi = 0x39, PiEw = 0x25, centerVref = 0x42, vrefHeight = 0x2A
N0.C0.S51: VmseWriteTraining Final: centerPi = 0x36, PiEw = 0x27, centerVref = 0x3F, vrefHeight = 0x28
N2.C1: VmseTrainCmdFine: vmse link sts = 0x4947
N4.C0.S04: VmseWriteTraining Final: centerPi = 0x3C, PiEw = 0x24, centerVref = 0x40, vrefHeight = 0x22
N6.C0.S00: VmseWriteTraining Final: centerPi = 0x3B, PiEw = 0x29, centerVref = 0x40, vrefHeight = 0x2E
N0.C0.S52: VmseWriteTraining Final: centerPi = 0x3C, PiEw = 0x24, centerVref = 0x3C, vrefHeight = 0x26
N4.C0.S05: VmseWriteTraining Final: centerPi = 0x3F, PiEw = 0x27, centerVref = 0x43, vrefHeight = 0x28
N6.C0.S01: VmseWriteTraining Final: centerPi = 0x3A, PiEw = 0x2A, centerVref = 0x41, vrefHeight = 0x2E
N0.C0.S53: VmseWriteTraining Final: centerPi = 0x3E, PiEw = 0x26, centerVref = 0x3B, vrefHeight = 0x28
N4.C0.S06: VmseWriteTraining Final: centerPi = 0x3C, PiEw = 0x25, centerVref = 0x42, vrefHeight = 0x26
N6.C0.S02: VmseWriteTraining Final: centerPi = 0x3A, PiEw = 0x24, centerVref = 0x3E, vrefHeight = 0x2C
N0.C0.S54: VmseWriteTraining Final: centerPi = 0x3B, PiEw = 0x22, centerVref = 0x40, vrefHeight = 0x26
N4.C0.S07: VmseWriteTraining Final: centerPi = 0x3A, PiEw = 0x27, centerVref = 0x40, vrefHeight = 0x22
N6.C0.S03: VmseWriteTraining Final: centerPi = 0x3B, PiEw = 0x26, centerVref = 0x3A, vrefHeight = 0x2E
N0.C0.S55: VmseWriteTraining Final: centerPi = 0x3C, PiEw = 0x25, centerVref = 0x42, vrefHeight = 0x26
N4.C0.S08: VmseWriteTraining Final: centerPi = 0x40, PiEw = 0x21, centerVref = 0x3B, vrefHeight = 0x28
N6.C0.S04: VmseWriteTraining Final: centerPi = 0x40, PiEw = 0x24, centerVref = 0x3D, vrefHeight = 0x2C
N0.C0.S56: VmseWriteTraining Final: centerPi = 0x3E, PiEw = 0x25, centerVref = 0x44, vrefHeight = 0x26
N4.C0.S09: VmseWriteTraining Final: centerPi = 0x38, PiEw = 0x29, centerVref = 0x40, vrefHeight = 0x26
N6.C0.S05: VmseWriteTraining Final: centerPi = 0x3E, PiEw = 0x25, centerVref = 0x3C, vrefHeight = 0x2C
N0.C0.S57: VmseWriteTraining Final: centerPi = 0x3E, PiEw = 0x27, centerVref = 0x3F, vrefHeight = 0x28
N4.C0.S10: VmseWriteTraining Final: centerPi = 0x36, PiEw = 0x26, centerVref = 0x3E, vrefHeight = 0x2A
N6.C0.S06: VmseWriteTraining Final: centerPi = 0x3E, PiEw = 0x25, centerVref = 0x3F, vrefHeight = 0x2A
N0.C0.S58: VmseWriteTraining Final: centerPi = 0x3D, PiEw = 0x22, centerVref = 0x35, vrefHeight = 0x28
N4.C0.S11: VmseWriteTraining Final: centerPi = 0x3B, PiEw = 0x23, centerVref = 0x3E, vrefHeight = 0x2A
N6.C0.S07: VmseWriteTraining Final: centerPi = 0x3E, PiEw = 0x22, centerVref = 0x3D, vrefHeight = 0x28
N0.C0.S59: VmseWriteTraining Final: centerPi = 0x39, PiEw = 0x2A, centerVref = 0x3F, vrefHeight = 0x28
N4.C0.S12: VmseWriteTraining Final: centerPi = 0x3F, PiEw = 0x26, centerVref = 0x3F, vrefHeight = 0x24
N6.C0.S08: VmseWriteTraining Final: centerPi = 0x39, PiEw = 0x2A, centerVref = 0x43, vrefHeight = 0x2E
N0.C0.S60: VmseWriteTraining Final: centerPi = 0x42, PiEw = 0x27, centerVref = 0x42, vrefHeight = 0x2A
N4.C0.S13: VmseWriteTraining Final: centerPi = 0x3E, PiEw = 0x28, centerVref = 0x41, vrefHeight = 0x28
N6.C0.S09: VmseWriteTraining Final: centerPi = 0x39, PiEw = 0x28, centerVref = 0x45, vrefHeight = 0x2E
N0.C0.S61: VmseWriteTraining Final: centerPi = 0x41, PiEw = 0x26, centerVref = 0x3F, vrefHeight = 0x26
N4.C0.S14: VmseWriteTraining Final: centerPi = 0x3E, PiEw = 0x25, centerVref = 0x41, vrefHeight = 0x28
N6.C0.S10: VmseWriteTraining Final: centerPi = 0x38, PiEw = 0x24, centerVref = 0x3C, vrefHeight = 0x30
N0.C0.S62: VmseWriteTraining Final: centerPi = 0x42, PiEw = 0x27, centerVref = 0x3B, vrefHeight = 0x26
N4.C0.S15: VmseWriteTraining Final: centerPi = 0x3D, PiEw = 0x28, centerVref = 0x42, vrefHeight = 0x2A
N6.C0.S11: VmseWriteTraining Final: centerPi = 0x39, PiEw = 0x29, centerVref = 0x3F, vrefHeight = 0x2E
N0.C0.S63: VmseWriteTraining Final: centerPi = 0x41, PiEw = 0x28, centerVref = 0x3D, vrefHeight = 0x28
N4.C0.S16: VmseWriteTraining Final: centerPi = 0x3D, PiEw = 0x27, centerVref = 0x42, vrefHeight = 0x22
N6.C0.S12: VmseWriteTraining Final: centerPi = 0x3F, PiEw = 0x26, centerVref = 0x43, vrefHeight = 0x2E
N0.C0.S64: VmseWriteTraining Final: centerPi = 0x3C, PiEw = 0x23, centerVref = 0x43, vrefHeight = 0x24
N4.C0.S17: VmseWriteTraining Final: centerPi = 0x38, PiEw = 0x22, centerVref = 0x3F, vrefHeight = 0x22
N6.C0.S13: VmseWriteTraining Final: centerPi = 0x3E, PiEw = 0x26, centerVref = 0x3E, vrefHeight = 0x2E
N0.C0.S65: VmseWriteTraining Final: centerPi = 0x3B, PiEw = 0x24, centerVref = 0x42, vrefHeight = 0x26
N4.C0.S18: VmseWriteTraining Final: centerPi = 0x38, PiEw = 0x25, centerVref = 0x41, vrefHeight = 0x24
N6.C0.S14: VmseWriteTraining Final: centerPi = 0x3D, PiEw = 0x23, centerVref = 0x3D, vrefHeight = 0x2E
N0.C0.S66: VmseWriteTraining Final: centerPi = 0x39, PiEw = 0x1E, centerVref = 0x43, vrefHeight = 0x24
N4.C0.S19: VmseWriteTraining Final: centerPi = 0x3A, PiEw = 0x26, centerVref = 0x3A, vrefHeight = 0x26
N6.C0.S15: VmseWriteTraining Final: centerPi = 0x42, PiEw = 0x26, centerVref = 0x37, vrefHeight = 0x32
N0.C0.S67: VmseWriteTraining Final: centerPi = 0x39, PiEw = 0x28, centerVref = 0x42, vrefHeight = 0x26
N4.C0.S20: VmseWriteTraining Final: centerPi = 0x3E, PiEw = 0x26, centerVref = 0x42, vrefHeight = 0x26
N6.C0.S16: VmseWriteTraining Final: centerPi = 0x3D, PiEw = 0x29, centerVref = 0x3E, vrefHeight = 0x26
N0.C0.S68: VmseWriteTraining Final: centerPi = 0x3F, PiEw = 0x24, centerVref = 0x41, vrefHeight = 0x24
N4.C0.S21: VmseWriteTraining Final: centerPi = 0x3D, PiEw = 0x29, centerVref = 0x41, vrefHeight = 0x24
N6.C0.S17: VmseWriteTraining Final: centerPi = 0x3D, PiEw = 0x26, centerVref = 0x41, vrefHeight = 0x28
N0.C0.S69: VmseWriteTraining Final: centerPi = 0x41, PiEw = 0x20, centerVref = 0x43, vrefHeight = 0x28
N4.C0.S22: VmseWriteTraining Final: centerPi = 0x3E, PiEw = 0x22, centerVref = 0x3E, vrefHeight = 0x22
N6.C0.S18: VmseWriteTraining Final: centerPi = 0x39, PiEw = 0x23, centerVref = 0x3C, vrefHeight = 0x26
N0.C0.S70: VmseWriteTraining Final: centerPi = 0x3E, PiEw = 0x21, centerVref = 0x3F, vrefHeight = 0x24
N4.C0.S23: VmseWriteTraining Final: centerPi = 0x3B, PiEw = 0x26, centerVref = 0x40, vrefHeight = 0x24
N6.C0.S19: VmseWriteTraining Final: centerPi = 0x38, PiEw = 0x27, centerVref = 0x41, vrefHeight = 0x2C
N0.C0.S71: VmseWriteTraining Final: centerPi = 0x3E, PiEw = 0x22, centerVref = 0x41, vrefHeight = 0x24
N4.C0.S24: VmseWriteTraining Final: centerPi = 0x3E, PiEw = 0x23, centerVref = 0x40, vrefHeight = 0x22
N6.C0.S20: VmseWriteTraining Final: centerPi = 0x40, PiEw = 0x27, centerVref = 0x3E, vrefHeight = 0x28

END - VMSE Train Write                 Time         3168 ms
N4.C0.S25: VmseWriteTraining Final: centerPi = 0x3C, PiEw = 0x20, centerVref = 0x41, vrefHeight = 0x26
N6.C0.S21: VmseWriteTraining Final: centerPi = 0x40, PiEw = 0x25, centerVref = 0x36, vrefHeight = 0x2A
Checkpoint Code: Socket 0, 0xB6, 0x64, 0x0000
N4.C0.S26: VmseWriteTraining Final: centerPi = 0x3C, PiEw = 0x1C, centerVref = 0x40, vrefHeight = 0x26
N6.C0.S22: VmseWriteTraining Final: centerPi = 0x3D, PiEw = 0x26, centerVref = 0x3E, vrefHeight = 0x26
N0: 
Total VMSE trainings latency = 15554 ms
N4.C0.S27: VmseWriteTraining Final: centerPi = 0x3B, PiEw = 0x25, centerVref = 0x3D, vrefHeight = 0x28
N6.C0.S23: VmseWriteTraining Final: centerPi = 0x43, PiEw = 0x25, centerVref = 0x3B, vrefHeight = 0x2C
N0: CpgcVmseTraining for VMSE1
N4.C0.S28: VmseWriteTraining Final: centerPi = 0x40, PiEw = 0x20, centerVref = 0x38, vrefHeight = 0x26
N6.C0.S24: VmseWriteTraining Final: centerPi = 0x3B, PiEw = 0x2C, centerVref = 0x43, vrefHeight = 0x28
Checkpoint Code: Socket 0, 0xB6, 0x11, 0x0000
N4.C0.S29: VmseWriteTraining Final: centerPi = 0x3F, PiEw = 0x22, centerVref = 0x3F, vrefHeight = 0x24
N6.C0.S25: VmseWriteTraining Final: centerPi = 0x3B, PiEw = 0x28, centerVref = 0x41, vrefHeight = 0x2C
N0: Initialize VMSE Channels
N4.C0.S30: VmseWriteTraining Final: centerPi = 0x3F, PiEw = 0x1F, centerVref = 0x3D, vrefHeight = 0x24
N6.C0.S26: VmseWriteTraining Final: centerPi = 0x3C, PiEw = 0x24, centerVref = 0x3D, vrefHeight = 0x2E

START - VMSE Detect DC
N4.C0.S31: VmseWriteTraining Final: centerPi = 0x41, PiEw = 0x27, centerVref = 0x3E, vrefHeight = 0x26
N6.C0.S27: VmseWriteTraining Final: centerPi = 0x37, PiEw = 0x2C, centerVref = 0x42, vrefHeight = 0x2C
Checkpoint Code: Socket 0, 0xB6, 0x46, 0x0000
N4.C0.S32: VmseWriteTraining Final: centerPi = 0x3F, PiEw = 0x25, centerVref = 0x42, vrefHeight = 0x2A
N6.C0.S28: VmseWriteTraining Final: centerPi = 0x3F, PiEw = 0x24, centerVref = 0x3C, vrefHeight = 0x2E
N0: HsxVmseCompInit
N4.C0.S33: VmseWriteTraining Final: centerPi = 0x3A, PiEw = 0x28, centerVref = 0x40, vrefHeight = 0x26
N6.C0.S29: VmseWriteTraining Final: centerPi = 0x3C, PiEw = 0x25, centerVref = 0x3F, vrefHeight = 0x28
Checkpoint Code: Socket 0, 0xB6, 0x80, 0x0000
N4.C0.S34: VmseWriteTraining Final: centerPi = 0x39, PiEw = 0x29, centerVref = 0x40, vrefHeight = 0x2C
N6.C0.S30: VmseWriteTraining Final: centerPi = 0x3E, PiEw = 0x21, centerVref = 0x3C, vrefHeight = 0x2A
N0.C1: Skip DC Detect check for CMD results
N4.C0.S35: VmseWriteTraining Final: centerPi = 0x39, PiEw = 0x24, centerVref = 0x3D, vrefHeight = 0x2C
N6.C0.S31: VmseWriteTraining Final: centerPi = 0x3E, PiEw = 0x29, centerVref = 0x40, vrefHeight = 0x2C
N0.C1: Skip DC Detect check for CMD results
N4.C0.S36: VmseWriteTraining Final: centerPi = 0x3E, PiEw = 0x26, centerVref = 0x3D, vrefHeight = 0x28
N6.C0.S32: VmseWriteTraining Final: centerPi = 0x3A, PiEw = 0x27, centerVref = 0x3F, vrefHeight = 0x30
N0: HsxVmseCompInit
N4.C0.S37: VmseWriteTraining Final: centerPi = 0x3D, PiEw = 0x21, centerVref = 0x3E, vrefHeight = 0x22
N6.C0.S33: VmseWriteTraining Final: centerPi = 0x37, PiEw = 0x28, centerVref = 0x41, vrefHeight = 0x28
Checkpoint Code: Socket 0, 0xB6, 0x81, 0x0000
N4.C0.S38: VmseWriteTraining Final: centerPi = 0x3D, PiEw = 0x27, centerVref = 0x3D, vrefHeight = 0x28
N6.C0.S34: VmseWriteTraining Final: centerPi = 0x38, PiEw = 0x28, centerVref = 0x40, vrefHeight = 0x30
N0.C1: VmseDetectDC: SUCCESS
N4.C0.S39: VmseWriteTraining Final: centerPi = 0x3C, PiEw = 0x24, centerVref = 0x3F, vrefHeight = 0x28
N6.C0.S35: VmseWriteTraining Final: centerPi = 0x36, PiEw = 0x2A, centerVref = 0x40, vrefHeight = 0x30
N0.C1: VmseDetectClock
N4.C0.S40: VmseWriteTraining Final: centerPi = 0x39, PiEw = 0x27, centerVref = 0x44, vrefHeight = 0x24
N6.C0.S36: VmseWriteTraining Final: centerPi = 0x3F, PiEw = 0x29, centerVref = 0x3A, vrefHeight = 0x32
N4.C0.S41: VmseWriteTraining Final: centerPi = 0x3D, PiEw = 0x22, centerVref = 0x3C, vrefHeight = 0x2A
N6.C0.S37: VmseWriteTraining Final: centerPi = 0x3E, PiEw = 0x26, centerVref = 0x3C, vrefHeight = 0x2C
N4.C0.S42: VmseWriteTraining Final: centerPi = 0x3C, PiEw = 0x26, centerVref = 0x41, vrefHeight = 0x28
N6.C0.S38: VmseWriteTraining Final: centerPi = 0x39, PiEw = 0x25, centerVref = 0x3E, vrefHeight = 0x2C
N4.C0.S43: VmseWriteTraining Final: centerPi = 0x39, PiEw = 0x25, centerVref = 0x3D, vrefHeight = 0x28
N6.C0.S39: VmseWriteTraining Final: centerPi = 0x3D, PiEw = 0x29, centerVref = 0x3B, vrefHeight = 0x2E
N4.C0.S44: VmseWriteTraining Final: centerPi = 0x3B, PiEw = 0x26, centerVref = 0x42, vrefHeight = 0x22
N6.C0.S40: VmseWriteTraining Final: centerPi = 0x3B, PiEw = 0x29, centerVref = 0x3C, vrefHeight = 0x2E
N4.C0.S45: VmseWriteTraining Final: centerPi = 0x41, PiEw = 0x24, centerVref = 0x43, vrefHeight = 0x28
N6.C0.S41: VmseWriteTraining Final: centerPi = 0x3B, PiEw = 0x28, centerVref = 0x40, vrefHeight = 0x2E
N4.C0.S46: VmseWriteTraining Final: centerPi = 0x3C, PiEw = 0x26, centerVref = 0x3C, vrefHeight = 0x26
N6.C0.S42: VmseWriteTraining Final: centerPi = 0x40, PiEw = 0x23, centerVref = 0x38, vrefHeight = 0x32
N4.C0.S47: VmseWriteTraining Final: centerPi = 0x3B, PiEw = 0x26, centerVref = 0x3B, vrefHeight = 0x28
N6.C0.S43: VmseWriteTraining Final: centerPi = 0x3A, PiEw = 0x28, centerVref = 0x38, vrefHeight = 0x30
N0.C1: VmseDetectClock: SUCCESS
N4.C0.S48: VmseWriteTraining Final: centerPi = 0x3D, PiEw = 0x25, centerVref = 0x3E, vrefHeight = 0x26
N6.C0.S44: VmseWriteTraining Final: centerPi = 0x40, PiEw = 0x27, centerVref = 0x40, vrefHeight = 0x2E

END - VMSE Detect DC                   Time         410 ms
N4.C0.S49: VmseWriteTraining Final: centerPi = 0x3F, PiEw = 0x27, centerVref = 0x3C, vrefHeight = 0x2A
N6.C0.S45: VmseWriteTraining Final: centerPi = 0x40, PiEw = 0x23, centerVref = 0x3D, vrefHeight = 0x2C

START - MXB Clock Train
N4.C0.S50: VmseWriteTraining Final: centerPi = 0x38, PiEw = 0x24, centerVref = 0x3C, vrefHeight = 0x26
N6.C0.S46: VmseWriteTraining Final: centerPi = 0x3D, PiEw = 0x27, centerVref = 0x3A, vrefHeight = 0x2C
Checkpoint Code: Socket 0, 0xB6, 0x48, 0x0000
N4.C0.S51: VmseWriteTraining Final: centerPi = 0x3A, PiEw = 0x28, centerVref = 0x3F, vrefHeight = 0x28
N6.C0.S47: VmseWriteTraining Final: centerPi = 0x3D, PiEw = 0x24, centerVref = 0x3B, vrefHeight = 0x2E
N4.C0.S52: VmseWriteTraining Final: centerPi = 0x3E, PiEw = 0x25, centerVref = 0x3E, vrefHeight = 0x26
N6.C0.S48: VmseWriteTraining Final: centerPi = 0x3B, PiEw = 0x24, centerVref = 0x3D, vrefHeight = 0x2A
Checkpoint Code: Socket 0, 0xB6, 0x6C, 0x0000
N4.C0.S53: VmseWriteTraining Final: centerPi = 0x3F, PiEw = 0x27, centerVref = 0x3B, vrefHeight = 0x28
N6.C0.S49: VmseWriteTraining Final: centerPi = 0x3D, PiEw = 0x28, centerVref = 0x39, vrefHeight = 0x2E
N4.C0.S54: VmseWriteTraining Final: centerPi = 0x3C, PiEw = 0x26, centerVref = 0x3E, vrefHeight = 0x22
N6.C0.S50: VmseWriteTraining Final: centerPi = 0x3A, PiEw = 0x23, centerVref = 0x40, vrefHeight = 0x2C
N4.C0.S55: VmseWriteTraining Final: centerPi = 0x3D, PiEw = 0x27, centerVref = 0x3F, vrefHeight = 0x24
N6.C0.S51: VmseWriteTraining Final: centerPi = 0x38, PiEw = 0x23, centerVref = 0x3C, vrefHeight = 0x28
N0.C1: VmseAdjustVckVoc: retrain Clock DCC.
   dcc1_vck = 0xC, dcc2_vck = 0x3F, preampvoc = 0x8
N4.C0.S56: VmseWriteTraining Final: centerPi = 0x3E, PiEw = 0x28, centerVref = 0x42, vrefHeight = 0x28
N6.C0.S52: VmseWriteTraining Final: centerPi = 0x40, PiEw = 0x26, centerVref = 0x39, vrefHeight = 0x2C
Checkpoint Code: Socket 0, 0xB6, 0x6C, 0x0000
N4.C0.S57: VmseWriteTraining Final: centerPi = 0x3E, PiEw = 0x2A, centerVref = 0x43, vrefHeight = 0x2A
N6.C0.S53: VmseWriteTraining Final: centerPi = 0x3F, PiEw = 0x27, centerVref = 0x3A, vrefHeight = 0x2E
N4.C0.S58: VmseWriteTraining Final: centerPi = 0x3B, PiEw = 0x28, centerVref = 0x3C, vrefHeight = 0x26
N6.C0.S54: VmseWriteTraining Final: centerPi = 0x3F, PiEw = 0x25, centerVref = 0x39, vrefHeight = 0x28
N4.C0.S59: VmseWriteTraining Final: centerPi = 0x3A, PiEw = 0x22, centerVref = 0x40, vrefHeight = 0x26
N6.C0.S55: VmseWriteTraining Final: centerPi = 0x3D, PiEw = 0x26, centerVref = 0x3C, vrefHeight = 0x2A
N0.C1: VmseAdjustVckVoc: retrain Clock DCC.
   dcc1_vck = 0x9, dcc2_vck = 0x3F, preampvoc = 0x9
N4.C0.S60: VmseWriteTraining Final: centerPi = 0x45, PiEw = 0x23, centerVref = 0x43, vrefHeight = 0x2C
N6.C0.S56: VmseWriteTraining Final: centerPi = 0x3F, PiEw = 0x29, centerVref = 0x3C, vrefHeight = 0x2E
Checkpoint Code: Socket 0, 0xB6, 0x6C, 0x0000
N4.C0.S61: VmseWriteTraining Final: centerPi = 0x45, PiEw = 0x22, centerVref = 0x42, vrefHeight = 0x26
N6.C0.S57: VmseWriteTraining Final: centerPi = 0x3E, PiEw = 0x29, centerVref = 0x3C, vrefHeight = 0x30
N4.C0.S62: VmseWriteTraining Final: centerPi = 0x41, PiEw = 0x27, centerVref = 0x3B, vrefHeight = 0x28
N6.C0.S58: VmseWriteTraining Final: centerPi = 0x3C, PiEw = 0x24, centerVref = 0x3D, vrefHeight = 0x2E
N4.C0.S63: VmseWriteTraining Final: centerPi = 0x45, PiEw = 0x24, centerVref = 0x3B, vrefHeight = 0x2A
N6.C0.S59: VmseWriteTraining Final: centerPi = 0x39, PiEw = 0x2B, centerVref = 0x39, vrefHeight = 0x30
N0.C1: VmseAdjustVckVoc: retrain Clock DCC.
   dcc1_vck = 0x7, dcc2_vck = 0x3F, preampvoc = 0xA
N4.C0.S64: VmseWriteTraining Final: centerPi = 0x3C, PiEw = 0x25, centerVref = 0x40, vrefHeight = 0x22
N6.C0.S60: VmseWriteTraining Final: centerPi = 0x40, PiEw = 0x26, centerVref = 0x3A, vrefHeight = 0x2E
Checkpoint Code: Socket 0, 0xB6, 0x6C, 0x0000
N4.C0.S65: VmseWriteTraining Final: centerPi = 0x3E, PiEw = 0x23, centerVref = 0x3D, vrefHeight = 0x28
N6.C0.S61: VmseWriteTraining Final: centerPi = 0x41, PiEw = 0x23, centerVref = 0x42, vrefHeight = 0x2C
N4.C0.S66: VmseWriteTraining Final: centerPi = 0x3F, PiEw = 0x1F, centerVref = 0x3F, vrefHeight = 0x26
N6.C0.S62: VmseWriteTraining Final: centerPi = 0x41, PiEw = 0x26, centerVref = 0x3D, vrefHeight = 0x2E
N4.C0.S67: VmseWriteTraining Final: centerPi = 0x38, PiEw = 0x29, centerVref = 0x42, vrefHeight = 0x28
N6.C0.S63: VmseWriteTraining Final: centerPi = 0x41, PiEw = 0x29, centerVref = 0x41, vrefHeight = 0x2E
N0.C2: VmseRefVckResync: ddrFreq = 0x2, VMSE_MODE_2_1 = 1, VMSE_PREAMBLE_2UI = 0
N4.C0.S68: VmseWriteTraining Final: centerPi = 0x42, PiEw = 0x25, centerVref = 0x3F, vrefHeight = 0x28
N6.C0.S64: VmseWriteTraining Final: centerPi = 0x3B, PiEw = 0x29, centerVref = 0x3F, vrefHeight = 0x2C
N4.C0.S69: VmseWriteTraining Final: centerPi = 0x40, PiEw = 0x26, centerVref = 0x3C, vrefHeight = 0x26
N6.C0.S65: VmseWriteTraining Final: centerPi = 0x3B, PiEw = 0x27, centerVref = 0x3E, vrefHeight = 0x2A
N0.C2: VmseRefVckResync: VLINKFREQNXT set to: 0x20F940A
N4.C0.S70: VmseWriteTraining Final: centerPi = 0x3E, PiEw = 0x1C, centerVref = 0x41, vrefHeight = 0x22
N6.C0.S66: VmseWriteTraining Final: centerPi = 0x3C, PiEw = 0x1F, centerVref = 0x3B, vrefHeight = 0x2A
N4.C0.S71: VmseWriteTraining Final: centerPi = 0x3E, PiEw = 0x26, centerVref = 0x46, vrefHeight = 0x22
N6.C0.S67: VmseWriteTraining Final: centerPi = 0x39, PiEw = 0x29, centerVref = 0x3B, vrefHeight = 0x2C
N0.C1: VmseTrainClockAlign: JCK clkadjcnt =3

END - VMSE Train Write                 Time         3536 ms
N6.C0.S68: VmseWriteTraining Final: centerPi = 0x3E, PiEw = 0x24, centerVref = 0x3F, vrefHeight = 0x2A

END - MXB Clock Train                  Time         563 ms
N4: 
Total VMSE trainings latency = 16816 ms
N6.C0.S69: VmseWriteTraining Final: centerPi = 0x43, PiEw = 0x1F, centerVref = 0x3B, vrefHeight = 0x2C

START - VMSE Train Command
N4: CpgcVmseTraining for VMSE1
N6.C0.S70: VmseWriteTraining Final: centerPi = 0x3F, PiEw = 0x22, centerVref = 0x39, vrefHeight = 0x28
Checkpoint Code: Socket 0, 0xB6, 0x4A, 0x0000
N4: Initialize VMSE Channels
N6.C0.S71: VmseWriteTraining Final: centerPi = 0x3E, PiEw = 0x24, centerVref = 0x3A, vrefHeight = 0x2A

START - VMSE Detect DC

END - VMSE Train Write                 Time         3588 ms
N0.C1.B00: HsxCtlXoverInit: invertPiClk = 0x0, RankUsed = 0xFFF, Training = 0x38FFF24
N4: HsxVmseCompInit
N6: 
Total VMSE trainings latency = 16814 ms
N0.C1.B01: HsxCtlXoverInit: invertPiClk = 0x0, RankUsed = 0xFFF, Training = 0x38FFF02
N4.C1: Skip DC Detect check for CMD results
N6: CpgcVmseTraining for VMSE1
Checkpoint Code: Socket 0, 0xB6, 0x60, 0x0000
N6: Initialize VMSE Channels
N4.C1: Skip DC Detect check for CMD results

START - VMSE Detect DC
N4: HsxVmseCompInit
N6: HsxVmseCompInit
N4.C1: VmseDetectDC: SUCCESS
N4.C1: VmseDetectClock
N6.C1: Skip DC Detect check for CMD results
N6.C1: Skip DC Detect check for CMD results
Checkpoint Code: Socket 0, 0xB6, 0x5A, 0x0000
N6: HsxVmseCompInit
N6.C1: VmseDetectDC: SUCCESS
N6.C1: VmseDetectClock
N0.C1: VmseTrainCmdFine: vmse link sts = 0x4947
N4.C1: VmseDetectClock: SUCCESS

END - VMSE Detect DC                   Time         235 ms

START - MXB Clock Train
N6.C1: VmseDetectClock: SUCCESS

END - VMSE Detect DC                   Time         218 ms

START - MXB Clock Train
N4.C1: VmseAdjustVckVoc: retrain Clock DCC.
   dcc1_vck = 0x3F, dcc2_vck = 0x29, preampvoc = 0xB
N6.C2: VmseRefVckResync: ddrFreq = 0x2, VMSE_MODE_2_1 = 1, VMSE_PREAMBLE_2UI = 0
N6.C2: VmseRefVckResync: VLINKFREQNXT set to: 0x20F940A
N4.C1: VmseAdjustVckVoc: retrain Clock DCC.
   dcc1_vck = 0x3F, dcc2_vck = 0x1F, preampvoc = 0xC
N6.C1: VmseTrainClockAlign: JCK clkadjcnt =0

END - MXB Clock Train                  Time         156 ms

START - VMSE Train Command
N4.C2: VmseRefVckResync: ddrFreq = 0x2, VMSE_MODE_2_1 = 1, VMSE_PREAMBLE_2UI = 0
N6.C1.B00: HsxCtlXoverInit: invertPiClk = 0x0, RankUsed = 0xFFF, Training = 0x38FFF21
N6.C1.B01: HsxCtlXoverInit: invertPiClk = 0x0, RankUsed = 0xFFF, Training = 0x38FFF3F
N4.C2: VmseRefVckResync: VLINKFREQNXT set to: 0x20F940A
N4.C1: VmseTrainClockAlign: JCK clkadjcnt =0

END - MXB Clock Train                  Time         291 ms

START - VMSE Train Command
N4.C1.B00: HsxCtlXoverInit: invertPiClk = 0x0, RankUsed = 0xFFF, Training = 0x38FFF24
N4.C1.B01: HsxCtlXoverInit: invertPiClk = 0x0, RankUsed = 0xFFF, Training = 0x38FFF02
N6.C1: VmseTrainCmdFine: vmse link sts = 0x4947
N4.C1: VmseTrainCmdFine: vmse link sts = 0x4947
Entry 0 - TrainDcc - DCCStart: 25, VocStart: 14, DCCFinal: 25, VocFinal: 14
Entry 1 - TrainDcc - DCCStart: 34, VocStart: 14, DCCFinal: 34, VocFinal: 14
N2.C1.S00: VmseCmdFineTraining Final: centerPi = 0x5E, PiEw = 0x31, centerVref = 0x3C, vrefHeight = 0x49
N2.C1.S01: VmseCmdFineTraining Final: centerPi = 0x5D, PiEw = 0x2F, centerVref = 0x3D, vrefHeight = 0x4D
N2.C1.S02: VmseCmdFineTraining Final: centerPi = 0x5A, PiEw = 0x35, centerVref = 0x42, vrefHeight = 0x4D
N2.C1.S03: VmseCmdFineTraining Final: centerPi = 0x60, PiEw = 0x32, centerVref = 0x34, vrefHeight = 0x4F
N2.C1.S04: VmseCmdFineTraining Final: centerPi = 0x55, PiEw = 0x31, centerVref = 0x35, vrefHeight = 0x4D
N2.C1.S05: VmseCmdFineTraining Final: centerPi = 0x58, PiEw = 0x31, centerVref = 0x3C, vrefHeight = 0x4D
N2.C1.S06: VmseCmdFineTraining Final: centerPi = 0x5D, PiEw = 0x31, centerVref = 0x33, vrefHeight = 0x4D
N2.C1.S07: VmseCmdFineTraining Final: centerPi = 0x5D, PiEw = 0x34, centerVref = 0x34, vrefHeight = 0x4B
N2.C1.S08: VmseCmdFineTraining Final: centerPi = 0x57, PiEw = 0x2E, centerVref = 0x39, vrefHeight = 0x49
N2.C1.S09: VmseCmdFineTraining Final: centerPi = 0x5C, PiEw = 0x31, centerVref = 0x36, vrefHeight = 0x47
N2.C1.S10: VmseCmdFineTraining Final: centerPi = 0x5B, PiEw = 0x2F, centerVref = 0x3E, vrefHeight = 0x49
N2.C1.S11: VmseCmdFineTraining Final: centerPi = 0x56, PiEw = 0x2D, centerVref = 0x39, vrefHeight = 0x49
N2.C1.S12: VmseCmdFineTraining Final: centerPi = 0x5D, PiEw = 0x31, centerVref = 0x31, vrefHeight = 0x4D
N2.C1.S13: VmseCmdFineTraining Final: centerPi = 0x58, PiEw = 0x32, centerVref = 0x39, vrefHeight = 0x4B
N2.C1.S14: VmseCmdFineTraining Final: centerPi = 0x5C, PiEw = 0x33, centerVref = 0x3D, vrefHeight = 0x4D
N2.C1.S15: VmseCmdFineTraining Final: centerPi = 0x5F, PiEw = 0x31, centerVref = 0x39, vrefHeight = 0x4B
N2.C1.S16: VmseCmdFineTraining Final: centerPi = 0x5B, PiEw = 0x2F, centerVref = 0x3E, vrefHeight = 0x4D

END - VMSE Train Command               Time         7156 ms

START - VMSE Train Read Leveling
N2.C1: VmseReadLevelFineSetup: Initial RT = 101, Initial IO Latency = 0, Initial IO Comp = 15
N2.C1: VmseRLWLFineSearchAll: Entry
N2.C1: FINE READ LEVEL DELAY
N2.C1.S00: RCVEN DELAY = 72
N2.C1.S01: RCVEN DELAY = 66
N2.C1.S02: RCVEN DELAY = 70
N2.C1.S03: RCVEN DELAY = 45
N2.C1.S04: RCVEN DELAY = 72
N2.C1.S05: RCVEN DELAY = 47
N2.C1.S06: RCVEN DELAY = 76
N2.C1.S07: RCVEN DELAY = 52
N2.C1.S08: RCVEN DELAY = 46
N2.C1.S00: READ LEVEL: FINAL RCVEN DELAY (both nibbles) = 42
N2.C1.S01: READ LEVEL: FINAL RCVEN DELAY (both nibbles) = 34
N2.C1.S02: READ LEVEL: FINAL RCVEN DELAY (both nibbles) = 38
N2.C1.S03: READ LEVEL: FINAL RCVEN DELAY (both nibbles) = 17
N2.C1.S04: READ LEVEL: FINAL RCVEN DELAY (both nibbles) = 42
N2.C1.S05: READ LEVEL: FINAL RCVEN DELAY (both nibbles) = 17
N2.C1.S06: READ LEVEL: FINAL RCVEN DELAY (both nibbles) = 45
N2.C1.S07: READ LEVEL: FINAL RCVEN DELAY (both nibbles) = 22
N2.C1.S08: READ LEVEL: FINAL RCVEN DELAY (both nibbles) = 14
N2.C1.D0.S09: READ LEVEL: FINAL RT (all ranks) = 83, FINAL IO LATENCY (all ranks) = 2
N2.C1.D1.S09: READ LEVEL: FINAL RT (all ranks) = 83, FINAL IO LATENCY (all ranks) = 2

END - VMSE Train Read Leveling         Time         262 ms

START - VMSE Train Read
Entry 0 - TrainDcc - DCCStart: 4, VocStart: 10, DCCFinal: 0, VocFinal: 10
Entry 1 - TrainDcc - DCCStart: 61, VocStart: 10, DCCFinal: 13, VocFinal: 10
Entry 0 - TrainDcc - DCCStart: 57, VocStart: 12, DCCFinal: 25, VocFinal: 12
Entry 1 - TrainDcc - DCCStart: 23, VocStart: 12, DCCFinal: 31, VocFinal: 12
N0.C1.S00: VmseCmdFineTraining Final: centerPi = 0x63, PiEw = 0x31, centerVref = 0x3F, vrefHeight = 0x47
N0.C1.S01: VmseCmdFineTraining Final: centerPi = 0x62, PiEw = 0x2F, centerVref = 0x3C, vrefHeight = 0x4B
Entry 0 - TrainDcc - DCCStart: 57, VocStart: 7, DCCFinal: 17, VocFinal: 7
N0.C1.S02: VmseCmdFineTraining Final: centerPi = 0x60, PiEw = 0x33, centerVref = 0x36, vrefHeight = 0x47
Entry 1 - TrainDcc - DCCStart: 30, VocStart: 7, DCCFinal: 30, VocFinal: 7
N0.C1.S03: VmseCmdFineTraining Final: centerPi = 0x62, PiEw = 0x2F, centerVref = 0x3C, vrefHeight = 0x47
N0.C1.S04: VmseCmdFineTraining Final: centerPi = 0x59, PiEw = 0x31, centerVref = 0x37, vrefHeight = 0x49
N0.C1.S05: VmseCmdFineTraining Final: centerPi = 0x5E, PiEw = 0x32, centerVref = 0x3C, vrefHeight = 0x47
N0.C1.S06: VmseCmdFineTraining Final: centerPi = 0x5D, PiEw = 0x31, centerVref = 0x3E, vrefHeight = 0x4D
N0.C1.S07: VmseCmdFineTraining Final: centerPi = 0x61, PiEw = 0x34, centerVref = 0x3A, vrefHeight = 0x49
N0.C1.S08: VmseCmdFineTraining Final: centerPi = 0x57, PiEw = 0x31, centerVref = 0x3D, vrefHeight = 0x43
N0.C1.S09: VmseCmdFineTraining Final: centerPi = 0x5C, PiEw = 0x2D, centerVref = 0x3A, vrefHeight = 0x49
N0.C1.S10: VmseCmdFineTraining Final: centerPi = 0x5D, PiEw = 0x2F, centerVref = 0x3D, vrefHeight = 0x47
N0.C1.S11: VmseCmdFineTraining Final: centerPi = 0x58, PiEw = 0x31, centerVref = 0x3B, vrefHeight = 0x4B
N0.C1.S12: VmseCmdFineTraining Final: centerPi = 0x5D, PiEw = 0x2F, centerVref = 0x3E, vrefHeight = 0x47
N0.C1.S13: VmseCmdFineTraining Final: centerPi = 0x59, PiEw = 0x32, centerVref = 0x40, vrefHeight = 0x49
N0.C1.S14: VmseCmdFineTraining Final: centerPi = 0x5D, PiEw = 0x31, centerVref = 0x3A, vrefHeight = 0x47
N0.C1.S15: VmseCmdFineTraining Final: centerPi = 0x60, PiEw = 0x31, centerVref = 0x3E, vrefHeight = 0x45
N0.C1.S16: VmseCmdFineTraining Final: centerPi = 0x5A, PiEw = 0x30, centerVref = 0x3D, vrefHeight = 0x47
N4.C1.S00: VmseCmdFineTraining Final: centerPi = 0x60, PiEw = 0x30, centerVref = 0x3B, vrefHeight = 0x4B
N4.C1.S01: VmseCmdFineTraining Final: centerPi = 0x5E, PiEw = 0x2E, centerVref = 0x3D, vrefHeight = 0x47
N4.C1.S02: VmseCmdFineTraining Final: centerPi = 0x5B, PiEw = 0x33, centerVref = 0x3D, vrefHeight = 0x49

END - VMSE Train Command               Time         7072 ms
N4.C1.S03: VmseCmdFineTraining Final: centerPi = 0x5F, PiEw = 0x31, centerVref = 0x3C, vrefHeight = 0x49

START - VMSE Train Read Leveling
N4.C1.S04: VmseCmdFineTraining Final: centerPi = 0x57, PiEw = 0x31, centerVref = 0x3F, vrefHeight = 0x4B
Checkpoint Code: Socket 0, 0xB6, 0x4E, 0x0000
N4.C1.S05: VmseCmdFineTraining Final: centerPi = 0x5E, PiEw = 0x30, centerVref = 0x38, vrefHeight = 0x4B
N4.C1.S06: VmseCmdFineTraining Final: centerPi = 0x5C, PiEw = 0x2F, centerVref = 0x3B, vrefHeight = 0x4D
N4.C1.S07: VmseCmdFineTraining Final: centerPi = 0x5D, PiEw = 0x33, centerVref = 0x3C, vrefHeight = 0x49
N4.C1.S08: VmseCmdFineTraining Final: centerPi = 0x57, PiEw = 0x33, centerVref = 0x3D, vrefHeight = 0x49
N4.C1.S09: VmseCmdFineTraining Final: centerPi = 0x5C, PiEw = 0x2E, centerVref = 0x3B, vrefHeight = 0x47
N4.C1.S10: VmseCmdFineTraining Final: centerPi = 0x5D, PiEw = 0x2F, centerVref = 0x3D, vrefHeight = 0x49
N4.C1.S11: VmseCmdFineTraining Final: centerPi = 0x58, PiEw = 0x30, centerVref = 0x3C, vrefHeight = 0x47
N4.C1.S12: VmseCmdFineTraining Final: centerPi = 0x5B, PiEw = 0x30, centerVref = 0x3C, vrefHeight = 0x47
N4.C1.S13: VmseCmdFineTraining Final: centerPi = 0x57, PiEw = 0x31, centerVref = 0x39, vrefHeight = 0x47
N0.C1: VmseReadLevelFineSetup: Initial RT = 101, Initial IO Latency = 0, Initial IO Comp = 15
N4.C1.S14: VmseCmdFineTraining Final: centerPi = 0x5D, PiEw = 0x32, centerVref = 0x3B, vrefHeight = 0x49
N4.C1.S15: VmseCmdFineTraining Final: centerPi = 0x61, PiEw = 0x32, centerVref = 0x3D, vrefHeight = 0x49
N4.C1.S16: VmseCmdFineTraining Final: centerPi = 0x5A, PiEw = 0x2F, centerVref = 0x3F, vrefHeight = 0x4B
N0.C1: VmseRLWLFineSearchAll: Entry
N0.C1: FINE READ LEVEL DELAY
N0.C1.S00: RCVEN DELAY = 80
N0.C1.S01: RCVEN DELAY = 72
N0.C1.S02: RCVEN DELAY = 74
N0.C1.S03: RCVEN DELAY = 53
N0.C1.S04: RCVEN DELAY = 81
N0.C1.S05: RCVEN DELAY = 58
N0.C1.S06: RCVEN DELAY = 86
N0.C1.S07: RCVEN DELAY = 61
N0.C1.S08: RCVEN DELAY = 53
N0.C1.S00: READ LEVEL: FINAL RCVEN DELAY (both nibbles) = 50
N0.C1.S01: READ LEVEL: FINAL RCVEN DELAY (both nibbles) = 41
N0.C1.S02: READ LEVEL: FINAL RCVEN DELAY (both nibbles) = 44
N0.C1.S03: READ LEVEL: FINAL RCVEN DELAY (both nibbles) = 22
N0.C1.S04: READ LEVEL: FINAL RCVEN DELAY (both nibbles) = 53
N0.C1.S05: READ LEVEL: FINAL RCVEN DELAY (both nibbles) = 29
N0.C1.S06: READ LEVEL: FINAL RCVEN DELAY (both nibbles) = 55
N0.C1.S07: READ LEVEL: FINAL RCVEN DELAY (both nibbles) = 30
N0.C1.S08: READ LEVEL: FINAL RCVEN DELAY (both nibbles) = 22
N0.C1.D0.S09: READ LEVEL: FINAL RT (all ranks) = 83, FINAL IO LATENCY (all ranks) = 2
N0.C1.D1.S09: READ LEVEL: FINAL RT (all ranks) = 83, FINAL IO LATENCY (all ranks) = 2

END - VMSE Train Read Leveling         Time         290 ms

START - VMSE Train Read
Checkpoint Code: Socket 0, 0xB6, 0x50, 0x0000

END - VMSE Train Command               Time         6837 ms

START - VMSE Train Read Leveling
N4.C1: VmseReadLevelFineSetup: Initial RT = 101, Initial IO Latency = 0, Initial IO Comp = 15
N4.C1: VmseRLWLFineSearchAll: Entry
N4.C1: FINE READ LEVEL DELAY
N4.C1.S00: RCVEN DELAY = 77
N4.C1.S01: RCVEN DELAY = 70
N4.C1.S02: RCVEN DELAY = 80
N4.C1.S03: RCVEN DELAY = 50
N4.C1.S04: RCVEN DELAY = 79
N4.C1.S05: RCVEN DELAY = 50
N4.C1.S06: RCVEN DELAY = 85
N4.C1.S07: RCVEN DELAY = 59
N4.C1.S08: RCVEN DELAY = 54
N4.C1.S00: READ LEVEL: FINAL RCVEN DELAY (both nibbles) = 176
N4.C1.S01: READ LEVEL: FINAL RCVEN DELAY (both nibbles) = 167
N4.C1.S02: READ LEVEL: FINAL RCVEN DELAY (both nibbles) = 178
N4.C1.S03: READ LEVEL: FINAL RCVEN DELAY (both nibbles) = 148
N4.C1.S04: READ LEVEL: FINAL RCVEN DELAY (both nibbles) = 176
N4.C1.S05: READ LEVEL: FINAL RCVEN DELAY (both nibbles) = 148
N4.C1.S06: READ LEVEL: FINAL RCVEN DELAY (both nibbles) = 181
N4.C1.S07: READ LEVEL: FINAL RCVEN DELAY (both nibbles) = 158
N4.C1.S08: READ LEVEL: FINAL RCVEN DELAY (both nibbles) = 152
N4.C1.D0.S09: READ LEVEL: FINAL RT (all ranks) = 83, FINAL IO LATENCY (all ranks) = 2
N4.C1.D1.S09: READ LEVEL: FINAL RT (all ranks) = 83, FINAL IO LATENCY (all ranks) = 2

END - VMSE Train Read Leveling         Time         263 ms

START - VMSE Train Read
N6.C1.S00: VmseCmdFineTraining Final: centerPi = 0x66, PiEw = 0x33, centerVref = 0x33, vrefHeight = 0x53
N6.C1.S01: VmseCmdFineTraining Final: centerPi = 0x66, PiEw = 0x30, centerVref = 0x2E, vrefHeight = 0x53
N6.C1.S02: VmseCmdFineTraining Final: centerPi = 0x61, PiEw = 0x35, centerVref = 0x33, vrefHeight = 0x51
N6.C1.S03: VmseCmdFineTraining Final: centerPi = 0x63, PiEw = 0x32, centerVref = 0x3B, vrefHeight = 0x51
N6.C1.S04: VmseCmdFineTraining Final: centerPi = 0x5C, PiEw = 0x32, centerVref = 0x36, vrefHeight = 0x4D
N6.C1.S05: VmseCmdFineTraining Final: centerPi = 0x5E, PiEw = 0x33, centerVref = 0x3A, vrefHeight = 0x4B
N6.C1.S06: VmseCmdFineTraining Final: centerPi = 0x62, PiEw = 0x32, centerVref = 0x30, vrefHeight = 0x53
N6.C1.S07: VmseCmdFineTraining Final: centerPi = 0x63, PiEw = 0x34, centerVref = 0x2F, vrefHeight = 0x51
N6.C1.S08: VmseCmdFineTraining Final: centerPi = 0x59, PiEw = 0x33, centerVref = 0x38, vrefHeight = 0x47
N6.C1.S09: VmseCmdFineTraining Final: centerPi = 0x5C, PiEw = 0x31, centerVref = 0x3F, vrefHeight = 0x49
N6.C1.S10: VmseCmdFineTraining Final: centerPi = 0x5C, PiEw = 0x2F, centerVref = 0x36, vrefHeight = 0x49
N6.C1.S11: VmseCmdFineTraining Final: centerPi = 0x58, PiEw = 0x32, centerVref = 0x39, vrefHeight = 0x4D
N6.C1.S12: VmseCmdFineTraining Final: centerPi = 0x5E, PiEw = 0x32, centerVref = 0x3B, vrefHeight = 0x4D
N6.C1.S13: VmseCmdFineTraining Final: centerPi = 0x59, PiEw = 0x31, centerVref = 0x3B, vrefHeight = 0x47
N6.C1.S14: VmseCmdFineTraining Final: centerPi = 0x5D, PiEw = 0x32, centerVref = 0x3E, vrefHeight = 0x49
N6.C1.S15: VmseCmdFineTraining Final: centerPi = 0x61, PiEw = 0x33, centerVref = 0x3A, vrefHeight = 0x4B
N6.C1.S16: VmseCmdFineTraining Final: centerPi = 0x5D, PiEw = 0x31, centerVref = 0x3B, vrefHeight = 0x51

END - VMSE Train Command               Time         7584 ms

START - VMSE Train Read Leveling
N6.C1: VmseReadLevelFineSetup: Initial RT = 101, Initial IO Latency = 0, Initial IO Comp = 15
N6.C1: VmseRLWLFineSearchAll: Entry
N6.C1: FINE READ LEVEL DELAY
N6.C1.S00: RCVEN DELAY = 70
N6.C1.S01: RCVEN DELAY = 64
N6.C1.S02: RCVEN DELAY = 70
N6.C1.S03: RCVEN DELAY = 45
N6.C1.S04: RCVEN DELAY = 70
N6.C1.S05: RCVEN DELAY = 47
N6.C1.S06: RCVEN DELAY = 75
N6.C1.S07: RCVEN DELAY = 56
N6.C1.S08: RCVEN DELAY = 50
N6.C1.S00: READ LEVEL: FINAL RCVEN DELAY (both nibbles) = 171
N6.C1.S01: READ LEVEL: FINAL RCVEN DELAY (both nibbles) = 162
N6.C1.S02: READ LEVEL: FINAL RCVEN DELAY (both nibbles) = 171
N6.C1.S03: READ LEVEL: FINAL RCVEN DELAY (both nibbles) = 144
N6.C1.S04: READ LEVEL: FINAL RCVEN DELAY (both nibbles) = 171
N6.C1.S05: READ LEVEL: FINAL RCVEN DELAY (both nibbles) = 145
N6.C1.S06: READ LEVEL: FINAL RCVEN DELAY (both nibbles) = 172
N6.C1.S07: READ LEVEL: FINAL RCVEN DELAY (both nibbles) = 153
N6.C1.S08: READ LEVEL: FINAL RCVEN DELAY (both nibbles) = 147
N6.C1.D0.S09: READ LEVEL: FINAL RT (all ranks) = 83, FINAL IO LATENCY (all ranks) = 2
N6.C1.D1.S09: READ LEVEL: FINAL RT (all ranks) = 83, FINAL IO LATENCY (all ranks) = 2

END - VMSE Train Read Leveling         Time         263 ms

START - VMSE Train Read

END - VMSE Train Read                  Time         3895 ms

START - VMSE Train Level Tx DQS DCC
N2.C1: VmseLevelTxDqsDccExecute: MXB DQS DCC Finished Successfully
N2.C1.S01: VmseAdjustDqsVoc: retrain DQS DCC.
N2.C1.S01:    dcc1_dqs = 0x0, preampvoc = 0xA
N2.C1: VmseLevelTxDqsDccExecute: MXB DQS DCC Finished Successfully
N2.C1.S01: VmseAdjustDqsVoc: retrain DQS DCC.
N2.C1.S01:    dcc1_dqs = 0x0, preampvoc = 0x9
N2.C1: VmseLevelTxDqsDccExecute: MXB DQS DCC Finished Successfully

END - VMSE Train Level Tx DQS DCC      Time         56 ms

START - VMSE Train Write Leveling
N2.C1: VmseWriteLevelFineSetup: Set push to data delay = 6, Global TX DQS delay = 0
N2.C1: VmseRLWLFineSearchAll: Entry
N2.C1: FINE WRITE LEVEL DELAY
N2.C1.S00: TX DQS DELAY = 52
N2.C1.S01: TX DQS DELAY = 58
N2.C1.S02: TX DQS DELAY = 52
N2.C1.S03: TX DQS DELAY = 85
N2.C1.S04: TX DQS DELAY = 51
N2.C1.S05: TX DQS DELAY = 78
N2.C1.S06: TX DQS DELAY = 47
N2.C1.S07: TX DQS DELAY = 73
N2.C1.S08: TX DQS DELAY = 73
N2.C1: VmseWriteLevelCoarseSetup: Set push to data delay = 6, Global TX DQS delay = 0
N2.C1: VmseWriteLevelCoarseExecute
N2.C1: VmseWLCoarseUpdatePD: New push to data delay = 6, New global TxDQS delay = 1
N2.C1: VmseWLCoarseUpdatePD: New push to data delay = 7, New global TxDQS delay = 0
N2.C1: VmseWLCoarseUpdatePD: New push to data delay = 7, New global TxDQS delay = 1
N2.C1: VmseWLCoarseUpdatePD: New push to data delay = 8, New global TxDQS delay = 0
N2.C1: VmseWLCoarseUpdatePD: New push to data delay = 8, New global TxDQS delay = 1
N2.C1.S00: FINAL TX DQS BEFORE TxFIFO CHECK = 151
N2.C1.S01: FINAL TX DQS BEFORE TxFIFO CHECK = 157
N2.C1.S02: FINAL TX DQS BEFORE TxFIFO CHECK = 150
N2.C1.S03: FINAL TX DQS BEFORE TxFIFO CHECK = 182
N2.C1.S04: FINAL TX DQS BEFORE TxFIFO CHECK = 149
N2.C1.S05: FINAL TX DQS BEFORE TxFIFO CHECK = 177
N2.C1.S06: FINAL TX DQS BEFORE TxFIFO CHECK = 146
N2.C1.S07: FINAL TX DQS BEFORE TxFIFO CHECK = 171
N2.C1.S08: FINAL TX DQS BEFORE TxFIFO CHECK = 172
N2.C1: ResolveTxFIFOPtrSeparation: Smallest PI (146) < MIN ALLOWED DELAY (176) 
N2.C1: VmseIncTxFifoPtrSeparation: New push to data delay = 7
N2.C1.S00: VmseIncTxFifoPtrSeparation: pi adjustment = 256, FINAL TX DQS DELAY = 407
N2.C1.S01: VmseIncTxFifoPtrSeparation: pi adjustment = 256, FINAL TX DQS DELAY = 413
N2.C1.S02: VmseIncTxFifoPtrSeparation: pi adjustment = 256, FINAL TX DQS DELAY = 406
N2.C1.S03: VmseIncTxFifoPtrSeparation: pi adjustment = 256, FINAL TX DQS DELAY = 438
N2.C1.S04: VmseIncTxFifoPtrSeparation: pi adjustment = 256, FINAL TX DQS DELAY = 405
N2.C1.S05: VmseIncTxFifoPtrSeparation: pi adjustment = 256, FINAL TX DQS DELAY = 433
N2.C1.S06: VmseIncTxFifoPtrSeparation: pi adjustment = 256, FINAL TX DQS DELAY = 402
N2.C1.S07: VmseIncTxFifoPtrSeparation: pi adjustment = 256, FINAL TX DQS DELAY = 427
N2.C1.S08: VmseIncTxFifoPtrSeparation: pi adjustment = 256, FINAL TX DQS DELAY = 428

END - VMSE Train Write Leveling        Time         252 ms

START - VMSE Train Write
Entry 0 - TrainDcc - DCCStart: 2, VocStart: 12, DCCFinal: 34, VocFinal: 12
Entry 1 - TrainDcc - DCCStart: 9, VocStart: 9, DCCFinal: 9, VocFinal: 9
Entry 2 - TrainDcc - DCCStart: 5, VocStart: 13, DCCFinal: 37, VocFinal: 13
Entry 3 - TrainDcc - DCCStart: 21, VocStart: 12, DCCFinal: 21, VocFinal: 12
Entry 4 - TrainDcc - DCCStart: 10, VocStart: 16, DCCFinal: 10, VocFinal: 24
Entry 5 - TrainDcc - DCCStart: 25, VocStart: 11, DCCFinal: 25, VocFinal: 11
Entry 6 - TrainDcc - DCCStart: 12, VocStart: 20, DCCFinal: 12, VocFinal: 29
Entry 7 - TrainDcc - DCCStart: 25, VocStart: 10, DCCFinal: 25, VocFinal: 10
Entry 8 - TrainDcc - DCCStart: 5, VocStart: 10, DCCFinal: 5, VocFinal: 10
N2.C1.S00: VmseWriteTraining Final: centerPi = 0x3B, PiEw = 0x2B, centerVref = 0x3E, vrefHeight = 0x2E
N2.C1.S01: VmseWriteTraining Final: centerPi = 0x3B, PiEw = 0x2E, centerVref = 0x38, vrefHeight = 0x2E
N2.C1.S02: VmseWriteTraining Final: centerPi = 0x37, PiEw = 0x29, centerVref = 0x3D, vrefHeight = 0x2C
N2.C1.S03: VmseWriteTraining Final: centerPi = 0x3A, PiEw = 0x29, centerVref = 0x3C, vrefHeight = 0x2E
N2.C1.S04: VmseWriteTraining Final: centerPi = 0x3E, PiEw = 0x2C, centerVref = 0x3A, vrefHeight = 0x2E
N2.C1.S05: VmseWriteTraining Final: centerPi = 0x3C, PiEw = 0x2C, centerVref = 0x3D, vrefHeight = 0x2C
N2.C1.S06: VmseWriteTraining Final: centerPi = 0x3C, PiEw = 0x2B, centerVref = 0x3F, vrefHeight = 0x30
N2.C1.S07: VmseWriteTraining Final: centerPi = 0x3E, PiEw = 0x2B, centerVref = 0x3A, vrefHeight = 0x2E
N2.C1.S08: VmseWriteTraining Final: centerPi = 0x3D, PiEw = 0x24, centerVref = 0x3F, vrefHeight = 0x30
N2.C1.S09: VmseWriteTraining Final: centerPi = 0x3E, PiEw = 0x29, centerVref = 0x3E, vrefHeight = 0x2E

END - VMSE Train Read                  Time         3882 ms
N2.C1.S10: VmseWriteTraining Final: centerPi = 0x3B, PiEw = 0x28, centerVref = 0x3F, vrefHeight = 0x2E

START - VMSE Train Level Tx DQS DCC
N2.C1.S11: VmseWriteTraining Final: centerPi = 0x39, PiEw = 0x27, centerVref = 0x3D, vrefHeight = 0x2C
Checkpoint Code: Socket 0, 0xB6, 0x52, 0x0000
N2.C1.S12: VmseWriteTraining Final: centerPi = 0x41, PiEw = 0x28, centerVref = 0x40, vrefHeight = 0x2E
N0.C1: VmseLevelTxDqsDccExecute: MXB DQS DCC Finished Successfully
N2.C1.S13: VmseWriteTraining Final: centerPi = 0x40, PiEw = 0x29, centerVref = 0x3A, vrefHeight = 0x2E

END - VMSE Train Level Tx DQS DCC      Time         34 ms
N2.C1.S14: VmseWriteTraining Final: centerPi = 0x3F, PiEw = 0x24, centerVref = 0x3C, vrefHeight = 0x2E

START - VMSE Train Write Leveling
N2.C1.S15: VmseWriteTraining Final: centerPi = 0x40, PiEw = 0x27, centerVref = 0x3F, vrefHeight = 0x2E
Checkpoint Code: Socket 0, 0xB6, 0x54, 0x0000
N2.C1.S16: VmseWriteTraining Final: centerPi = 0x39, PiEw = 0x27, centerVref = 0x3D, vrefHeight = 0x2C
N0.C1: VmseWriteLevelFineSetup: Set push to data delay = 6, Global TX DQS delay = 0
N2.C1.S17: VmseWriteTraining Final: centerPi = 0x37, PiEw = 0x29, centerVref = 0x39, vrefHeight = 0x2C

END - VMSE Train Read                  Time         3714 ms
N0.C1: VmseRLWLFineSearchAll: Entry
N2.C1.S18: VmseWriteTraining Final: centerPi = 0x36, PiEw = 0x29, centerVref = 0x39, vrefHeight = 0x30

START - VMSE Train Level Tx DQS DCC
N0.C1: FINE WRITE LEVEL DELAY
N2.C1.S19: VmseWriteTraining Final: centerPi = 0x35, PiEw = 0x2D, centerVref = 0x3E, vrefHeight = 0x32
N4.C1: VmseLevelTxDqsDccExecute: MXB DQS DCC Finished Successfully
N0.C1.S00: TX DQS DELAY = 61
N2.C1.S20: VmseWriteTraining Final: centerPi = 0x3C, PiEw = 0x28, centerVref = 0x3F, vrefHeight = 0x2C

END - VMSE Train Level Tx DQS DCC      Time         21 ms
N0.C1.S01: TX DQS DELAY = 65
N2.C1.S21: VmseWriteTraining Final: centerPi = 0x39, PiEw = 0x28, centerVref = 0x3E, vrefHeight = 0x2A

START - VMSE Train Write Leveling
N0.C1.S02: TX DQS DELAY = 58
N2.C1.S22: VmseWriteTraining Final: centerPi = 0x3A, PiEw = 0x27, centerVref = 0x39, vrefHeight = 0x2C
N4.C1: VmseWriteLevelFineSetup: Set push to data delay = 6, Global TX DQS delay = 0
N0.C1.S03: TX DQS DELAY = 89
N2.C1.S23: VmseWriteTraining Final: centerPi = 0x39, PiEw = 0x29, centerVref = 0x3E, vrefHeight = 0x2A
N4.C1: VmseRLWLFineSearchAll: Entry
N0.C1.S04: TX DQS DELAY = 61
N2.C1.S24: VmseWriteTraining Final: centerPi = 0x3A, PiEw = 0x28, centerVref = 0x3E, vrefHeight = 0x2E
N4.C1: FINE WRITE LEVEL DELAY
N0.C1.S05: TX DQS DELAY = 81
N2.C1.S25: VmseWriteTraining Final: centerPi = 0x3B, PiEw = 0x2E, centerVref = 0x3F, vrefHeight = 0x2E
N4.C1.S00: TX DQS DELAY = 60
N0.C1.S06: TX DQS DELAY = 51
N2.C1.S26: VmseWriteTraining Final: centerPi = 0x3B, PiEw = 0x29, centerVref = 0x3C, vrefHeight = 0x30
N4.C1.S01: TX DQS DELAY = 62
N0.C1.S07: TX DQS DELAY = 77
N2.C1.S27: VmseWriteTraining Final: centerPi = 0x3A, PiEw = 0x2B, centerVref = 0x37, vrefHeight = 0x30
N4.C1.S02: TX DQS DELAY = 56
N0.C1.S08: TX DQS DELAY = 79
N2.C1.S28: VmseWriteTraining Final: centerPi = 0x3E, PiEw = 0x21, centerVref = 0x3A, vrefHeight = 0x2A
N4.C1.S03: TX DQS DELAY = 86
N0.C1: VmseWriteLevelCoarseSetup: Set push to data delay = 6, Global TX DQS delay = 0
N2.C1.S29: VmseWriteTraining Final: centerPi = 0x3E, PiEw = 0x24, centerVref = 0x39, vrefHeight = 0x2C
N4.C1.S04: TX DQS DELAY = 56
N0.C1: VmseWriteLevelCoarseExecute
N2.C1.S30: VmseWriteTraining Final: centerPi = 0x3F, PiEw = 0x28, centerVref = 0x3C, vrefHeight = 0x32
N4.C1.S05: TX DQS DELAY = 80
Checkpoint Code: Socket 0, 0xB6, 0xAC, 0x0000
N2.C1.S31: VmseWriteTraining Final: centerPi = 0x3D, PiEw = 0x26, centerVref = 0x40, vrefHeight = 0x2A
N4.C1.S06: TX DQS DELAY = 49
N0.C1: VmseWLCoarseUpdatePD: New push to data delay = 6, New global TxDQS delay = 1
N2.C1.S32: VmseWriteTraining Final: centerPi = 0x3A, PiEw = 0x2B, centerVref = 0x41, vrefHeight = 0x2C
N4.C1.S07: TX DQS DELAY = 70
N0.C1: VmseWLCoarseUpdatePD: New push to data delay = 7, New global TxDQS delay = 0
N2.C1.S33: VmseWriteTraining Final: centerPi = 0x42, PiEw = 0x26, centerVref = 0x38, vrefHeight = 0x30
N4.C1.S08: TX DQS DELAY = 73
N0.C1: VmseWLCoarseUpdatePD: New push to data delay = 7, New global TxDQS delay = 1
N2.C1.S34: VmseWriteTraining Final: centerPi = 0x3D, PiEw = 0x27, centerVref = 0x3C, vrefHeight = 0x2E
N4.C1: VmseWriteLevelCoarseSetup: Set push to data delay = 6, Global TX DQS delay = 0
N0.C1: VmseWLCoarseUpdatePD: New push to data delay = 8, New global TxDQS delay = 0
N2.C1.S35: VmseWriteTraining Final: centerPi = 0x3C, PiEw = 0x27, centerVref = 0x3A, vrefHeight = 0x30
N4.C1: VmseWriteLevelCoarseExecute
N0.C1: VmseWLCoarseUpdatePD: New push to data delay = 8, New global TxDQS delay = 1
N2.C1.S36: VmseWriteTraining Final: centerPi = 0x42, PiEw = 0x28, centerVref = 0x40, vrefHeight = 0x2E
N4.C1: VmseWLCoarseUpdatePD: New push to data delay = 6, New global TxDQS delay = 1
N0.C1.S00: FINAL TX DQS BEFORE TxFIFO CHECK = 157
N2.C1.S37: VmseWriteTraining Final: centerPi = 0x3D, PiEw = 0x2B, centerVref = 0x3C, vrefHeight = 0x2A
N4.C1: VmseWLCoarseUpdatePD: New push to data delay = 7, New global TxDQS delay = 0
N0.C1.S01: FINAL TX DQS BEFORE TxFIFO CHECK = 164
N2.C1.S38: VmseWriteTraining Final: centerPi = 0x3F, PiEw = 0x29, centerVref = 0x3D, vrefHeight = 0x2E
N4.C1: VmseWLCoarseUpdatePD: New push to data delay = 7, New global TxDQS delay = 1
N0.C1.S02: FINAL TX DQS BEFORE TxFIFO CHECK = 156
N2.C1.S39: VmseWriteTraining Final: centerPi = 0x3E, PiEw = 0x29, centerVref = 0x3D, vrefHeight = 0x2C
N4.C1: VmseWLCoarseUpdatePD: New push to data delay = 8, New global TxDQS delay = 0
N0.C1.S03: FINAL TX DQS BEFORE TxFIFO CHECK = 187
N2.C1.S40: VmseWriteTraining Final: centerPi = 0x37, PiEw = 0x29, centerVref = 0x46, vrefHeight = 0x2C
N4.C1: VmseWLCoarseUpdatePD: New push to data delay = 8, New global TxDQS delay = 1
N0.C1.S04: FINAL TX DQS BEFORE TxFIFO CHECK = 157
N2.C1.S41: VmseWriteTraining Final: centerPi = 0x39, PiEw = 0x2B, centerVref = 0x3F, vrefHeight = 0x2E
N4.C1: VmseWLCoarseUpdatePD: New push to data delay = 9, New global TxDQS delay = 0
N0.C1.S05: FINAL TX DQS BEFORE TxFIFO CHECK = 179
N2.C1.S42: VmseWriteTraining Final: centerPi = 0x3A, PiEw = 0x28, centerVref = 0x3A, vrefHeight = 0x2E
N4.C1.S00: FINAL TX DQS BEFORE TxFIFO CHECK = 32
N0.C1.S06: FINAL TX DQS BEFORE TxFIFO CHECK = 148
N2.C1.S43: VmseWriteTraining Final: centerPi = 0x39, PiEw = 0x2A, centerVref = 0x3D, vrefHeight = 0x2E
N4.C1.S01: FINAL TX DQS BEFORE TxFIFO CHECK = 33
N0.C1.S07: FINAL TX DQS BEFORE TxFIFO CHECK = 176
N2.C1.S44: VmseWriteTraining Final: centerPi = 0x41, PiEw = 0x26, centerVref = 0x3D, vrefHeight = 0x30
N4.C1.S02: FINAL TX DQS BEFORE TxFIFO CHECK = 24
N0.C1.S08: FINAL TX DQS BEFORE TxFIFO CHECK = 177
N2.C1.S45: VmseWriteTraining Final: centerPi = 0x3E, PiEw = 0x27, centerVref = 0x3C, vrefHeight = 0x2E
N4.C1.S03: FINAL TX DQS BEFORE TxFIFO CHECK = 58
N0.C1: ResolveTxFIFOPtrSeparation: Smallest PI (148) < MIN ALLOWED DELAY (176) 
N2.C1.S46: VmseWriteTraining Final: centerPi = 0x3F, PiEw = 0x23, centerVref = 0x3A, vrefHeight = 0x2E
N4.C1.S04: FINAL TX DQS BEFORE TxFIFO CHECK = 24
N0.C1: VmseIncTxFifoPtrSeparation: New push to data delay = 7
N2.C1.S47: VmseWriteTraining Final: centerPi = 0x3E, PiEw = 0x2C, centerVref = 0x3D, vrefHeight = 0x2C
N4.C1.S05: FINAL TX DQS BEFORE TxFIFO CHECK = 50
N0.C1.S00: VmseIncTxFifoPtrSeparation: pi adjustment = 256, FINAL TX DQS DELAY = 413
N2.C1.S48: VmseWriteTraining Final: centerPi = 0x3A, PiEw = 0x29, centerVref = 0x3F, vrefHeight = 0x2A
N4.C1.S06: FINAL TX DQS BEFORE TxFIFO CHECK = 19
N0.C1.S01: VmseIncTxFifoPtrSeparation: pi adjustment = 256, FINAL TX DQS DELAY = 420
N2.C1.S49: VmseWriteTraining Final: centerPi = 0x3E, PiEw = 0x29, centerVref = 0x3D, vrefHeight = 0x30
N4.C1.S07: FINAL TX DQS BEFORE TxFIFO CHECK = 41
N0.C1.S02: VmseIncTxFifoPtrSeparation: pi adjustment = 256, FINAL TX DQS DELAY = 412
N2.C1.S50: VmseWriteTraining Final: centerPi = 0x3B, PiEw = 0x2B, centerVref = 0x40, vrefHeight = 0x2C
N4.C1.S08: FINAL TX DQS BEFORE TxFIFO CHECK = 42

END - VMSE Train Read                  Time         3796 ms
N0.C1.S03: VmseIncTxFifoPtrSeparation: pi adjustment = 256, FINAL TX DQS DELAY = 443
N2.C1.S51: VmseWriteTraining Final: centerPi = 0x3B, PiEw = 0x2D, centerVref = 0x3B, vrefHeight = 0x30
N4.C1: ResolveTxFIFOPtrSeparation: Smallest PI (19) < MIN ALLOWED DELAY (176) 

START - VMSE Train Level Tx DQS DCC
N0.C1.S04: VmseIncTxFifoPtrSeparation: pi adjustment = 256, FINAL TX DQS DELAY = 413
N2.C1.S52: VmseWriteTraining Final: centerPi = 0x43, PiEw = 0x28, centerVref = 0x3B, vrefHeight = 0x2C
N4.C1: VmseIncTxFifoPtrSeparation: New push to data delay = 8
N6.C1: VmseLevelTxDqsDccExecute: MXB DQS DCC Finished Successfully
N0.C1.S05: VmseIncTxFifoPtrSeparation: pi adjustment = 256, FINAL TX DQS DELAY = 435
N2.C1.S53: VmseWriteTraining Final: centerPi = 0x42, PiEw = 0x2A, centerVref = 0x3D, vrefHeight = 0x2C
N4.C1.S00: VmseIncTxFifoPtrSeparation: pi adjustment = 128, FINAL TX DQS DELAY = 288

END - VMSE Train Level Tx DQS DCC      Time         34 ms
N0.C1.S06: VmseIncTxFifoPtrSeparation: pi adjustment = 256, FINAL TX DQS DELAY = 404
N2.C1.S54: VmseWriteTraining Final: centerPi = 0x3F, PiEw = 0x26, centerVref = 0x41, vrefHeight = 0x2E
N4.C1.S01: VmseIncTxFifoPtrSeparation: pi adjustment = 128, FINAL TX DQS DELAY = 289

START - VMSE Train Write Leveling
N0.C1.S07: VmseIncTxFifoPtrSeparation: pi adjustment = 256, FINAL TX DQS DELAY = 432
N2.C1.S55: VmseWriteTraining Final: centerPi = 0x40, PiEw = 0x2A, centerVref = 0x3B, vrefHeight = 0x30
N4.C1.S02: VmseIncTxFifoPtrSeparation: pi adjustment = 128, FINAL TX DQS DELAY = 280
N6.C1: VmseWriteLevelFineSetup: Set push to data delay = 6, Global TX DQS delay = 0
N0.C1.S08: VmseIncTxFifoPtrSeparation: pi adjustment = 256, FINAL TX DQS DELAY = 433
N2.C1.S56: VmseWriteTraining Final: centerPi = 0x3A, PiEw = 0x29, centerVref = 0x3F, vrefHeight = 0x2C
N4.C1.S03: VmseIncTxFifoPtrSeparation: pi adjustment = 128, FINAL TX DQS DELAY = 314
N6.C1: VmseRLWLFineSearchAll: Entry

END - VMSE Train Write Leveling        Time         973 ms
N2.C1.S57: VmseWriteTraining Final: centerPi = 0x3B, PiEw = 0x2C, centerVref = 0x3E, vrefHeight = 0x2E
N4.C1.S04: VmseIncTxFifoPtrSeparation: pi adjustment = 128, FINAL TX DQS DELAY = 280
N6.C1: FINE WRITE LEVEL DELAY

START - VMSE Train Write
N2.C1.S58: VmseWriteTraining Final: centerPi = 0x3A, PiEw = 0x29, centerVref = 0x3C, vrefHeight = 0x2E
N4.C1.S05: VmseIncTxFifoPtrSeparation: pi adjustment = 128, FINAL TX DQS DELAY = 306
N6.C1.S00: TX DQS DELAY = 59
Checkpoint Code: Socket 0, 0xB6, 0x56, 0x0000
N2.C1.S59: VmseWriteTraining Final: centerPi = 0x3A, PiEw = 0x2D, centerVref = 0x3D, vrefHeight = 0x30
N4.C1.S06: VmseIncTxFifoPtrSeparation: pi adjustment = 128, FINAL TX DQS DELAY = 275
N6.C1.S01: TX DQS DELAY = 64
N2.C1.S60: VmseWriteTraining Final: centerPi = 0x3E, PiEw = 0x2A, centerVref = 0x3B, vrefHeight = 0x2C
N4.C1.S07: VmseIncTxFifoPtrSeparation: pi adjustment = 128, FINAL TX DQS DELAY = 297
N6.C1.S02: TX DQS DELAY = 52
N2.C1.S61: VmseWriteTraining Final: centerPi = 0x3E, PiEw = 0x29, centerVref = 0x40, vrefHeight = 0x2E
N4.C1.S08: VmseIncTxFifoPtrSeparation: pi adjustment = 128, FINAL TX DQS DELAY = 298
N6.C1.S03: TX DQS DELAY = 85
N2.C1.S62: VmseWriteTraining Final: centerPi = 0x3D, PiEw = 0x2C, centerVref = 0x3B, vrefHeight = 0x30

END - VMSE Train Write Leveling        Time         991 ms
N6.C1.S04: TX DQS DELAY = 54
N2.C1.S63: VmseWriteTraining Final: centerPi = 0x3C, PiEw = 0x2C, centerVref = 0x3B, vrefHeight = 0x2E

START - VMSE Train Write
N6.C1.S05: TX DQS DELAY = 79
N2.C1.S64: VmseWriteTraining Final: centerPi = 0x3B, PiEw = 0x28, centerVref = 0x3F, vrefHeight = 0x2C
N6.C1.S06: TX DQS DELAY = 45
N2.C1.S65: VmseWriteTraining Final: centerPi = 0x39, PiEw = 0x25, centerVref = 0x39, vrefHeight = 0x28
N6.C1.S07: TX DQS DELAY = 74
N2.C1.S66: VmseWriteTraining Final: centerPi = 0x39, PiEw = 0x1F, centerVref = 0x3B, vrefHeight = 0x2C
N6.C1.S08: TX DQS DELAY = 71
N2.C1.S67: VmseWriteTraining Final: centerPi = 0x3C, PiEw = 0x25, centerVref = 0x3A, vrefHeight = 0x30
N6.C1: VmseWriteLevelCoarseSetup: Set push to data delay = 6, Global TX DQS delay = 0
N2.C1.S68: VmseWriteTraining Final: centerPi = 0x41, PiEw = 0x26, centerVref = 0x3C, vrefHeight = 0x2E
N6.C1: VmseWriteLevelCoarseExecute
N2.C1.S69: VmseWriteTraining Final: centerPi = 0x3D, PiEw = 0x23, centerVref = 0x3D, vrefHeight = 0x2C
N6.C1: VmseWLCoarseUpdatePD: New push to data delay = 6, New global TxDQS delay = 1
N2.C1.S70: VmseWriteTraining Final: centerPi = 0x40, PiEw = 0x24, centerVref = 0x3B, vrefHeight = 0x2E
N6.C1: VmseWLCoarseUpdatePD: New push to data delay = 7, New global TxDQS delay = 0
N2.C1.S71: VmseWriteTraining Final: centerPi = 0x3E, PiEw = 0x26, centerVref = 0x43, vrefHeight = 0x2A
N6.C1: VmseWLCoarseUpdatePD: New push to data delay = 7, New global TxDQS delay = 1

END - VMSE Train Write                 Time         3039 ms
N6.C1: VmseWLCoarseUpdatePD: New push to data delay = 8, New global TxDQS delay = 0
N2: 
Total VMSE trainings latency = 15297 ms
N6.C1: VmseWLCoarseUpdatePD: New push to data delay = 8, New global TxDQS delay = 1
N3: GatherSPDData
N6.C1: VmseWLCoarseUpdatePD: New push to data delay = 9, New global TxDQS delay = 0
Gather SPD Data
N6.C1.S00: FINAL TX DQS BEFORE TxFIFO CHECK = 29
N3.C0.D0: tWR in MTB units: 0x78
N6.C1.S01: FINAL TX DQS BEFORE TxFIFO CHECK = 33
N6.C1.S02: FINAL TX DQS BEFORE TxFIFO CHECK = 23
N6.C1.S03: FINAL TX DQS BEFORE TxFIFO CHECK = 57
N6.C1.S04: FINAL TX DQS BEFORE TxFIFO CHECK = 24
N6.C1.S05: FINAL TX DQS BEFORE TxFIFO CHECK = 49
N3.C1.D0: tWR in MTB units: 0x78
N6.C1.S06: FINAL TX DQS BEFORE TxFIFO CHECK = 13
N6.C1.S07: FINAL TX DQS BEFORE TxFIFO CHECK = 42
N6.C1.S08: FINAL TX DQS BEFORE TxFIFO CHECK = 41
N6.C1: ResolveTxFIFOPtrSeparation: Smallest PI (13) < MIN ALLOWED DELAY (176) 
N3.C2.D0: tWR in MTB units: 0x78
N6.C1: VmseIncTxFifoPtrSeparation: New push to data delay = 8
N6.C1.S00: VmseIncTxFifoPtrSeparation: pi adjustment = 128, FINAL TX DQS DELAY = 285
N6.C1.S01: VmseIncTxFifoPtrSeparation: pi adjustment = 128, FINAL TX DQS DELAY = 289
N3.C3.D0: tWR in MTB units: 0x78
N6.C1.S02: VmseIncTxFifoPtrSeparation: pi adjustment = 128, FINAL TX DQS DELAY = 279
N6.C1.S03: VmseIncTxFifoPtrSeparation: pi adjustment = 128, FINAL TX DQS DELAY = 313

GatherSPDData time            112 ms
N6.C1.S04: VmseIncTxFifoPtrSeparation: pi adjustment = 128, FINAL TX DQS DELAY = 280
N3: GlobalEarlyConfig
N6.C1.S05: VmseIncTxFifoPtrSeparation: pi adjustment = 128, FINAL TX DQS DELAY = 305
N3: Global Early Configuration
N6.C1.S06: VmseIncTxFifoPtrSeparation: pi adjustment = 128, FINAL TX DQS DELAY = 269
N3.C0: GlobalEarlyConfig: mcmntChknbit.frc_mddl_on = 1
N6.C1.S07: VmseIncTxFifoPtrSeparation: pi adjustment = 128, FINAL TX DQS DELAY = 298
N3.C0.D0: Config DIMMMTR_0_MCDDC_DESC_REG: 000C5051
N6.C1.S08: VmseIncTxFifoPtrSeparation: pi adjustment = 128, FINAL TX DQS DELAY = 297
N3.C0: RX Vref Default = 32

END - VMSE Train Write Leveling        Time         598 ms
N3.C1: GlobalEarlyConfig: mcmntChknbit.frc_mddl_on = 1

START - VMSE Train Write
N3.C1.D0: Config DIMMMTR_0_MCDDC_DESC_REG: 000C5051
N3.C1: RX Vref Default = 32
N3.C2: GlobalEarlyConfig: mcmntChknbit.frc_mddl_on = 1
N3.C2.D0: Config DIMMMTR_0_MCDDC_DESC_REG: 000C5051
N3.C2: RX Vref Default = 32
N3.C3: GlobalEarlyConfig: mcmntChknbit.frc_mddl_on = 1
N3.C3.D0: Config DIMMMTR_0_MCDDC_DESC_REG: 000C5051
N3.C3: RX Vref Default = 32
N3: ChannelEarlyConfig
N3: Channel Early Configuration
N3.C0: Enable = 1
N3.C0.D0: Enable = 1
N3.C0.D0.R0: Enable = 1
N3.C0.D0.R0: ENABLED: ckeMask = 00000001
N3.C0.D0.R1: Enable = 1
N3.C0.D0.R1: ENABLED: ckeMask = 00000003
N3.C0.D0.R2: Enable = 0
N3.C0.D0.R3: Enable = 0
N3.C0.D1: Enable = 0
N3.C0.D2: Enable = 0
N3.C1: Enable = 1
N3.C1.D0: Enable = 1
N3.C1.D0.R0: Enable = 1
N3.C1.D0.R0: ENABLED: ckeMask = 00000001
N3.C1.D0.R1: Enable = 1
N3.C1.D0.R1: ENABLED: ckeMask = 00000003
N3.C1.D0.R2: Enable = 0
N3.C1.D0.R3: Enable = 0
N3.C1.D1: Enable = 0
N3.C1.D2: Enable = 0
N3.C2: Enable = 1
N3.C2.D0: Enable = 1
N3.C2.D0.R0: Enable = 1
N3.C2.D0.R0: ENABLED: ckeMask = 00000001
N3.C2.D0.R1: Enable = 1
N3.C2.D0.R1: ENABLED: ckeMask = 00000003
N3.C2.D0.R2: Enable = 0
N3.C2.D0.R3: Enable = 0
N3.C2.D1: Enable = 0
N3.C2.D2: Enable = 0
N3.C3: Enable = 1
N3.C3.D0: Enable = 1
N3.C3.D0.R0: Enable = 1
N3.C3.D0.R0: ENABLED: ckeMask = 00000001
N3.C3.D0.R1: Enable = 1
N3.C3.D0.R1: ENABLED: ckeMask = 00000003
N3.C3.D0.R2: Enable = 0
N3.C3.D0.R3: Enable = 0
N3.C3.D1: Enable = 0
N3.C3.D2: Enable = 0
N3: Memory Timings:
N3.C0: nCL = 9
N3.C0: nCWL = 7
N3.C0: nRP = 9
N3.C0: nRCD = 9
N3.C0: nRRD = 4
N3.C0: nWTR = 5
N3.C0: nRAS = 24
N3.C0: nRTP = 5
N3.C0: nWR = 10
N3.C0: nFAW = 20
N3.C0: nRC = 33
N3.C0: nRFC = 174
N3.C0: casSup = 0xFC
N3.C0: trrMode = 0
N3.C0: twoXRefresh = 0
N3.C0: t_stagger_ref = 0x86
N3.C0: tcsrftp.Bits.t_xsdll = 512
N3.C0: Common CL = 9
Common CWL = 7
N3: Memory Timings:
N3.C1: nCL = 9
N3.C1: nCWL = 7
N3.C1: nRP = 9
N3.C1: nRCD = 9
N3.C1: nRRD = 4
N3.C1: nWTR = 5
N3.C1: nRAS = 24
N3.C1: nRTP = 5
N3.C1: nWR = 10
N3.C1: nFAW = 20
N3.C1: nRC = 33
N3.C1: nRFC = 174
N3.C1: casSup = 0xFC
N3.C1: trrMode = 0
N3.C1: twoXRefresh = 0
N3.C1: t_stagger_ref = 0x86
N3.C1: tcsrftp.Bits.t_xsdll = 512
N3.C1: Common CL = 9
Common CWL = 7
N3: Memory Timings:
N3.C2: nCL = 9
N3.C2: nCWL = 7
N3.C2: nRP = 9
N3.C2: nRCD = 9
N3.C2: nRRD = 4
N3.C2: nWTR = 5
N3.C2: nRAS = 24
N3.C2: nRTP = 5
N3.C2: nWR = 10
N3.C2: nFAW = 20
N3.C2: nRC = 33
N3.C2: nRFC = 174
N3.C2: casSup = 0xFC
N3.C2: trrMode = 0
N3.C2: twoXRefresh = 0
N3.C2: t_stagger_ref = 0x86
N3.C2: tcsrftp.Bits.t_xsdll = 512
N3.C2: Common CL = 9
Common CWL = 7
N3: Memory Timings:
N3.C3: nCL = 9
N3.C3: nCWL = 7
N3.C3: nRP = 9
N3.C3: nRCD = 9
N3.C3: nRRD = 4
N3.C3: nWTR = 5
N3.C3: nRAS = 24
N3.C3: nRTP = 5
N3.C3: nWR = 10
N3.C3: nFAW = 20
N3.C3: nRC = 33
N3.C3: nRFC = 174
N3.C3: casSup = 0xFC
N3.C3: trrMode = 0
N3.C3: twoXRefresh = 0
N3.C3: t_stagger_ref = 0x86
N3.C3: tcsrftp.Bits.t_xsdll = 512
N3.C3: Common CL = 9
Common CWL = 7
N3: PreVmseTraining
N3.C0: InitHostVmseCfg
N3.C0: vmse_wr_turnaround = 0x7 
N3.C2: InitHostVmseCfg
N3.C2: vmse_wr_turnaround = 0x7 
N3: HsxInitDdrioInterface
N3.C0: rxVref = 0x5F
N3.C1: rxVref = 0x5F
N3: HsxVmseCompInit
N3: VmseCrossoverCalib
N3: Enable xovercal
N3: vmse_modes =          1,  0
N3.C0: piDelay CMDn  CMDs  CTL  CKE  CLK   0  1  2  3  4  5  6  7  8  9 10 11 12 13 14 15 16 17
          0       0     0    0    0    0   1  1  1  0  0  0  1  1  0  1  1  1  0  0  0  1  1  0 
          1       0     0    0    0    0   1  1  1  1  0  0  1  1  0  1  1  1  1  0  0  1  1  0 
          2       0     0    0    0    0   1  1  1  1  0  1  1  1  0  1  1  1  1  0  1  1  1  0 
          3       0     0    0    0    0   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
          4       0     0    1    0    0   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
          5       0     0    1    0    0   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
          6       0     0    1    1    0   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
          7       0     0    1    1    0   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
          8       0     0    1    1    0   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
          9       0     0    1    1    0   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         10       0     0    1    1    0   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         11       0     0    1    1    0   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         12       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         13       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         14       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         15       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         16       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         17       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         18       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         19       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         20       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         21       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         22       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         23       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         24       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         25       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         26       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         27       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         28       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         29       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         30       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         31       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         32       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         33       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         34       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         35       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         36       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         37       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         38       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         39       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         40       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         41       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         42       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         43       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         44       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         45       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         46       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         47       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         48       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         49       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         50       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         51       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         52       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         53       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         54       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         55       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         56       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         57       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         58       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         59       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         60       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         61       0     0    1    1    1   0  0  1  1  1  1  1  1  1  0  1  1  1  1  1  1  1  1 
         62       0     0    1    1    1   X  X  1  1  1  1  1  1  1  X  0  1  1  1  1  1  1  1 
         63       0     0    1    1    1   X  X  1  1  1  1  1  1  1  X  X  1  1  1  1  1  1  1 
N3.C0: setting ddrcrinvertpiclk
          0       0     0    1    1    1   X  X  0  1  1  1  0  0  1  X  X  0  1  1  1  0  0  1 
          1       0     0    1    1    1   X  X  0  1  1  1  0  0  1  X  X  0  1  1  1  0  0  1 
          2       0     0    1    1    1   X  X  0  1  1  1  0  0  1  X  X  0  1  1  1  0  0  1 
          3       0     0    1    1    1   X  X  0  0  1  1  0  0  1  X  X  0  0  1  1  0  0  1 
          4       0     0    1    1    1   X  X  0  X  1  0  0  0  1  X  X  0  X  1  0  0  0  1 
          5       0     0    0    1    1   X  X  0  X  0  X  0  0  0  X  X  0  X  0  X  0  0  0 
          6       0     0    X    1    1   X  X  0  X  X  X  0  0  X  X  X  0  X  X  X  0  0  X 
          7       0     0    X    1    1   X  X  0  X  X  X  0  0  X  X  X  0  X  X  X  0  0  X 
          8       0     0    X    0    1   X  X  0  X  X  X  0  0  X  X  X  0  X  X  X  0  0  X 
          9       0     0    X    X    1   X  X  0  X  X  X  0  0  X  X  X  0  X  X  X  0  0  X 
         10       0     0    X    X    1   X  X  0  X  X  X  0  0  X  X  X  0  X  X  X  0  0  X 
         11       0     0    X    X    1   X  X  0  X  X  X  0  0  X  X  X  0  X  X  X  0  0  X 
         12       0     0    X    X    1   X  X  0  X  X  X  0  0  X  X  X  0  X  X  X  0  0  X 
         13       0     0    X    X    0   X  X  0  X  X  X  0  0  X  X  X  0  X  X  X  0  0  X 
         14       0     0    X    X    X   X  X  0  X  X  X  0  0  X  X  X  0  X  X  X  0  0  X 
         15       0     0    X    X    X   X  X  0  X  X  X  0  0  X  X  X  0  X  X  X  0  0  X 
         16       0     0    X    X    X   X  X  0  X  X  X  0  0  X  X  X  0  X  X  X  0  0  X 
         17       0     0    X    X    X   X  X  0  X  X  X  0  0  X  X  X  0  X  X  X  0  0  X 
         18       0     0    X    X    X   X  X  0  X  X  X  0  0  X  X  X  0  X  X  X  0  0  X 
         19       0     0    X    X    X   X  X  0  X  X  X  0  0  X  X  X  0  X  X  X  0  0  X 
         20       0     0    X    X    X   X  X  0  X  X  X  0  0  X  X  X  0  X  X  X  0  0  X 
         21       0     0    X    X    X   X  X  0  X  X  X  0  0  X  X  X  0  X  X  X  0  0  X 
         22       0     0    X    X    X   X  X  0  X  X  X  0  0  X  X  X  0  X  X  X  0  0  X 
         23       0     0    X    X    X   X  X  0  X  X  X  0  0  X  X  X  0  X  X  X  0  0  X 
         24       0     0    X    X    X   X  X  0  X  X  X  0  0  X  X  X  0  X  X  X  0  0  X 
         25       0     0    X    X    X   X  X  0  X  X  X  0  0  X  X  X  0  X  X  X  0  0  X 
         26       0     0    X    X    X   X  X  0  X  X  X  0  0  X  X  X  0  X  X  X  0  0  X 
         27       0     0    X    X    X   X  X  0  X  X  X  0  0  X  X  X  0  X  X  X  0  0  X 
         28       0     0    X    X    X   X  X  0  X  X  X  0  0  X  X  X  0  X  X  X  0  0  X 
         29       0     0    X    X    X   X  X  0  X  X  X  0  0  X  X  X  0  X  X  X  0  0  X 
         30       0     0    X    X    X   X  X  0  X  X  X  0  0  X  X  X  0  X  X  X  0  0  X 
         31       0     0    X    X    X   X  X  0  X  X  X  0  0  X  X  X  0  X  X  X  0  0  X 
         32       0     0    X    X    X   X  X  0  X  X  X  0  0  X  X  X  0  X  X  X  0  0  X 
         33       0     0    X    X    X   X  X  0  X  X  X  0  0  X  X  X  0  X  X  X  0  0  X 
         34       0     0    X    X    X   X  X  0  X  X  X  0  0  X  X  X  0  X  X  X  0  0  X 
         35       0     0    X    X    X   X  X  0  X  X  X  0  0  X  X  X  0  X  X  X  0  0  X 
         36       0     0    X    X    X   X  X  0  X  X  X  0  0  X  X  X  0  X  X  X  0  0  X 
         37       0     0    X    X    X   X  X  0  X  X  X  0  0  X  X  X  0  X  X  X  0  0  X 
         38       0     0    X    X    X   X  X  0  X  X  X  0  0  X  X  X  0  X  X  X  0  0  X 
         39       0     0    X    X    X   X  X  0  X  X  X  0  0  X  X  X  0  X  X  X  0  0  X 
         40       0     0    X    X    X   X  X  0  X  X  X  0  0  X  X  X  0  X  X  X  0  0  X 
         41       0     0    X    X    X   X  X  0  X  X  X  0  0  X  X  X  0  X  X  X  0  0  X 
         42       0     0    X    X    X   X  X  0  X  X  X  0  0  X  X  X  0  X  X  X  0  0  X 
         43       0     0    X    X    X   X  X  0  X  X  X  0  0  X  X  X  0  X  X  X  0  0  X 
         44       0     0    X    X    X   X  X  0  X  X  X  0  0  X  X  X  0  X  X  X  0  0  X 
         45       0     0    X    X    X   X  X  0  X  X  X  0  0  X  X  X  0  X  X  X  0  0  X 
         46       0     0    X    X    X   X  X  0  X  X  X  0  0  X  X  X  0  X  X  X  0  0  X 
         47       0     0    X    X    X   X  X  0  X  X  X  0  0  X  X  X  0  X  X  X  0  0  X 
         48       0     0    X    X    X   X  X  0  X  X  X  0  0  X  X  X  0  X  X  X  0  0  X 
         49       0     0    X    X    X   X  X  0  X  X  X  0  0  X  X  X  0  X  X  X  0  0  X 
         50       0     0    X    X    X   X  X  0  X  X  X  0  0  X  X  X  0  X  X  X  0  0  X 
         51       0     0    X    X    X   X  X  0  X  X  X  0  0  X  X  X  0  X  X  X  0  0  X 
         52       0     0    X    X    X   X  X  0  X  X  X  0  0  X  X  X  0  X  X  X  0  0  X 
         53       0     0    X    X    X   X  X  0  X  X  X  0  0  X  X  X  0  X  X  X  0  0  X 
         54       0     0    X    X    X   X  X  0  X  X  X  0  0  X  X  X  0  X  X  X  0  0  X 
         55       0     0    X    X    X   X  X  0  X  X  X  0  0  X  X  X  0  X  X  X  0  0  X 
         56       0     0    X    X    X   X  X  0  X  X  X  0  0  X  X  X  0  X  X  X  0  0  X 
         57       0     0    X    X    X   X  X  0  X  X  X  0  0  X  X  X  0  X  X  X  0  0  X 
         58       0     0    X    X    X   X  X  0  X  X  X  0  0  X  X  X  0  X  X  X  0  0  X 
         59       0     0    X    X    X   X  X  0  X  X  X  0  0  X  X  X  0  X  X  X  0  0  X 
         60       0     0    X    X    X   X  X  0  X  X  X  0  0  X  X  X  0  X  X  X  0  0  X 
         61       0     0    X    X    X   X  X  0  X  X  X  0  0  X  X  X  0  X  X  X  0  0  X 
         62       0     0    X    X    X   X  X  0  X  X  X  0  0  X  X  X  0  X  X  X  0  0  X 
         63       0     0    X    X    X   X  X  1  X  X  X  1  1  X  X  X  1  X  X  X  1  1  X 
N3.C0: CMD-N xovercal offset = 0
N3.C0: CMD-S xovercal offset = 0
N3.C0: CTL xovercal offset   = 5
N3.C0: CKE xovercal offset   = 8
N3.C0: CLK xovercal offset   = 13
N3.C0.S18: STROBE                     0   1   2   3   4   5   6   7   8   9  10  11  12  13  14  15  16  17
N3.C0.S18: Rec En xovercal offset =  61  61   0   3   5   4   0   0   5  61  62   0   3   5   4   0   0   5 
N3.C0.S18: Tx Dqs xovercal offset =  61  63   0  63  63  63   0   0  63  63  63   0  63  63  63   0   0  63 
N3.C0.S18: Tx Dq xovercal offset  =  61  61   0   3   5   4   0   0   5  61  62   0   3   5   4   0   0   5 
N3.C0:         CMDn  CMDs  CTL  CKE  CLK   0  1  2  3  4  5  6  7  8
N3.C0: offsets:  0     0     5N3: getComplexCkeSetupTime defaultOffset = 98
N3: getComplexCkeSetupTime = 98
    8   13
Ctl Offsets Delta / final ctl offset / final cke offset /  98  /  39  /  10
Cke invertpiclk / Ctl invertpiclk / 0x0  /  0x0
N3: getComplexClkSetupTime defaultOffset = 0
N3: getComplexClkSetupTime = 0
ClkSetupTime = 13
N3: getComplexDqSetupTime defaultOffset = 0
N3: getComplexDqSetupTime = 0
N3.C0.S00: txdqoffset delta = 0, dq invertpiclk = 0
N3: getComplexDqsSetupTime defaultOffset = 40
N3: getComplexDqsSetupTime = 40
N3.C0.S00: txdqsoffset delta = 40
N3: getComplexRcvEnSetupTime defaultOffset = 37
N3: getComplexRcvEnSetupTime = 37
N3.C0.S00: rcvenoffset delta = 37
N3.C0.S00: Final txdqoffset / txdqsoffset / rcvenoffset / 29 /  5 /  2
N3: getComplexDqSetupTime defaultOffset = 0
N3: getComplexDqSetupTime = 0
N3.C0.S01: txdqoffset delta = 0, dq invertpiclk = 0
N3: getComplexDqsSetupTime defaultOffset = 40
N3: getComplexDqsSetupTime = 40
N3.C0.S01: txdqsoffset delta = 40
N3: getComplexRcvEnSetupTime defaultOffset = 37
N3: getComplexRcvEnSetupTime = 37
N3.C0.S01: rcvenoffset delta = 37
N3.C0.S01: Final txdqoffset / txdqsoffset / rcvenoffset / 61 / 37 / 34
N3: getComplexDqSetupTime defaultOffset = 0
N3: getComplexDqSetupTime = 0
N3.C0.S02: txdqoffset delta = 0, dq invertpiclk = 3
N3: getComplexDqsSetupTime defaultOffset = 40
N3: getComplexDqsSetupTime = 40
N3.C0.S02: txdqsoffset delta = 40
N3: getComplexRcvEnSetupTime defaultOffset = 37
N3: getComplexRcvEnSetupTime = 37
N3.C0.S02: rcvenoffset delta = 37
N3.C0.S02: Final txdqoffset / txdqsoffset / rcvenoffset / 32 /  8 /  5
N3: getComplexDqSetupTime defaultOffset = 0
N3: getComplexDqSetupTime = 0
N3.C0.S03: txdqoffset delta = 0, dq invertpiclk = 3
N3: getComplexDqsSetupTime defaultOffset = 40
N3: getComplexDqsSetupTime = 40
N3.C0.S03: txdqsoffset delta = 40
N3: getComplexRcvEnSetupTime defaultOffset = 37
N3: getComplexRcvEnSetupTime = 37
N3.C0.S03: rcvenoffset delta = 37
N3.C0.S03: Final txdqoffset / txdqsoffset / rcvenoffset /  3 / 43 / 40
N3: getComplexDqSetupTime defaultOffset = 0
N3: getComplexDqSetupTime = 0
N3.C0.S04: txdqoffset delta = 0, dq invertpiclk = 3
N3: getComplexDqsSetupTime defaultOffset = 40
N3: getComplexDqsSetupTime = 40
N3.C0.S04: txdqsoffset delta = 40
N3: getComplexRcvEnSetupTime defaultOffset = 37
N3: getComplexRcvEnSetupTime = 37
N3.C0.S04: rcvenoffset delta = 37
N3.C0.S04: Final txdqoffset / txdqsoffset / rcvenoffset / 37 / 13 / 10
N3: getComplexDqSetupTime defaultOffset = 0
N3: getComplexDqSetupTime = 0
N3.C0.S05: txdqoffset delta = 0, dq invertpiclk = 3
N3: getComplexDqsSetupTime defaultOffset = 40
N3: getComplexDqsSetupTime = 40
N3.C0.S05: txdqsoffset delta = 40
N3: getComplexRcvEnSetupTime defaultOffset = 37
N3: getComplexRcvEnSetupTime = 37
N3.C0.S05: rcvenoffset delta = 37
N3.C0.S05: Final txdqoffset / txdqsoffset / rcvenoffset /  4 / 44 / 41
N3: getComplexDqSetupTime defaultOffset = 0
N3: getComplexDqSetupTime = 0
N3.C0.S06: txdqoffset delta = 0, dq invertpiclk = 3
N3: getComplexDqsSetupTime defaultOffset = 40
N3: getComplexDqsSetupTime = 40
N3.C0.S06: txdqsoffset delta = 40
N3: getComplexRcvEnSetupTime defaultOffset = 37
N3: getComplexRcvEnSetupTime = 37
N3.C0.S06: rcvenoffset delta = 37
N3.C0.S06: Final txdqoffset / txdqsoffset / rcvenoffset / 32 /  8 /  5
N3: getComplexDqSetupTime defaultOffset = 0
N3: getComplexDqSetupTime = 0
N3.C0.S07: txdqoffset delta = 0, dq invertpiclk = 3
N3: getComplexDqsSetupTime defaultOffset = 40
N3: getComplexDqsSetupTime = 40
N3.C0.S07: txdqsoffset delta = 40
N3: getComplexRcvEnSetupTime defaultOffset = 37
N3: getComplexRcvEnSetupTime = 37
N3.C0.S07: rcvenoffset delta = 37
N3.C0.S07: Final txdqoffset / txdqsoffset / rcvenoffset /  0 / 40 / 37
N3: getComplexDqSetupTime defaultOffset = 0
N3: getComplexDqSetupTime = 0
N3.C0.S08: txdqoffset delta = 0, dq invertpiclk = 3
N3: getComplexDqsSetupTime defaultOffset = 40
N3: getComplexDqsSetupTime = 40
N3.C0.S08: txdqsoffset delta = 40
N3: getComplexRcvEnSetupTime defaultOffset = 37
N3: getComplexRcvEnSetupTime = 37
N3.C0.S08: rcvenoffset delta = 37
N3.C0.S08: Final txdqoffset / txdqsoffset / rcvenoffset / 37 / 13 / 10

N3: vmse_modes =          1,  0
N3.C1: piDelay CMDn  CMDs  CTL  CKE  CLK   0  1  2  3  4  5  6  7  8  9 10 11 12 13 14 15 16 17
          0       0     0    1    0    0   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
          1       0     0    1    0    0   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
          2       0     0    1    0    0   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
          3       0     0    1    1    0   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
          4       0     0    1    1    0   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
          5       0     0    1    1    0   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
          6       0     0    1    1    0   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
          7       0     0    1    1    0   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
          8       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
          9       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         10       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         11       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         12       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         13       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         14       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         15       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         16       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         17       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         18       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         19       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         20       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         21       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         22       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         23       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         24       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         25       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         26       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         27       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         28       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         29       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         30       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         31       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         32       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         33       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         34       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         35       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         36       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         37       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         38       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         39       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         40       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         41       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         42       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         43       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         44       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         45       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         46       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         47       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         48       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         49       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         50       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         51       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         52       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         53       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         54       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         55       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         56       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         57       0     0    1    1    1   0  1  1  1  1  1  1  1  1  0  1  1  1  1  1  1  1  1 
         58       0     0    1    1    1   X  0  1  1  1  1  1  1  1  X  0  1  1  1  1  1  1  1 
         59       0     0    1    1    1   X  X  1  1  1  1  1  1  1  X  X  1  1  1  1  1  1  1 
         60       0     0    1    1    1   X  X  1  1  1  1  1  0  1  X  X  1  1  1  1  1  0  1 
         61       0     0    1    1    1   X  X  0  1  1  1  1  X  1  X  X  0  1  1  1  1  X  1 
         62       0     0    1    1    1   X  X  X  1  1  1  1  X  1  X  X  X  1  1  1  1  X  1 
         63       0     0    1    1    1   X  X  X  0  1  1  0  X  1  X  X  X  0  1  1  0  X  1 
N3.C1: setting ddrcrinvertpiclk
          0       0     0    1    1    1   X  X  X  X  1  0  X  X  1  X  X  X  X  1  0  X  X  1 
          1       0     0    0    1    1   X  X  X  X  1  0  X  X  1  X  X  X  X  1  0  X  X  1 
          2       0     0    X    1    1   X  X  X  X  1  0  X  X  0  X  X  X  X  1  0  X  X  0 
          3       0     0    X    1    1   X  X  X  X  0  0  X  X  X  X  X  X  X  0  0  X  X  X 
          4       0     0    X    0    1   X  X  X  X  X  0  X  X  X  X  X  X  X  X  0  X  X  X 
          5       0     0    X    X    1   X  X  X  X  X  0  X  X  X  X  X  X  X  X  0  X  X  X 
          6       0     0    X    X    1   X  X  X  X  X  0  X  X  X  X  X  X  X  X  0  X  X  X 
          7       0     0    X    X    1   X  X  X  X  X  0  X  X  X  X  X  X  X  X  0  X  X  X 
          8       0     0    X    X    1   X  X  X  X  X  0  X  X  X  X  X  X  X  X  0  X  X  X 
          9       0     0    X    X    0   X  X  X  X  X  0  X  X  X  X  X  X  X  X  0  X  X  X 
         10       0     0    X    X    X   X  X  X  X  X  0  X  X  X  X  X  X  X  X  0  X  X  X 
         11       0     0    X    X    X   X  X  X  X  X  0  X  X  X  X  X  X  X  X  0  X  X  X 
         12       0     0    X    X    X   X  X  X  X  X  0  X  X  X  X  X  X  X  X  0  X  X  X 
         13       0     0    X    X    X   X  X  X  X  X  0  X  X  X  X  X  X  X  X  0  X  X  X 
         14       0     0    X    X    X   X  X  X  X  X  0  X  X  X  X  X  X  X  X  0  X  X  X 
         15       0     0    X    X    X   X  X  X  X  X  0  X  X  X  X  X  X  X  X  0  X  X  X 
         16       0     0    X    X    X   X  X  X  X  X  0  X  X  X  X  X  X  X  X  0  X  X  X 
         17       0     0    X    X    X   X  X  X  X  X  0  X  X  X  X  X  X  X  X  0  X  X  X 
         18       0     0    X    X    X   X  X  X  X  X  0  X  X  X  X  X  X  X  X  0  X  X  X 
         19       0     0    X    X    X   X  X  X  X  X  0  X  X  X  X  X  X  X  X  0  X  X  X 
         20       0     0    X    X    X   X  X  X  X  X  0  X  X  X  X  X  X  X  X  0  X  X  X 
         21       0     0    X    X    X   X  X  X  X  X  0  X  X  X  X  X  X  X  X  0  X  X  X 
         22       0     0    X    X    X   X  X  X  X  X  0  X  X  X  X  X  X  X  X  0  X  X  X 
         23       0     0    X    X    X   X  X  X  X  X  0  X  X  X  X  X  X  X  X  0  X  X  X 
         24       0     0    X    X    X   X  X  X  X  X  0  X  X  X  X  X  X  X  X  0  X  X  X 
         25       0     0    X    X    X   X  X  X  X  X  0  X  X  X  X  X  X  X  X  0  X  X  X 
         26       0     0    X    X    X   X  X  X  X  X  0  X  X  X  X  X  X  X  X  0  X  X  X 
         27       0     0    X    X    X   X  X  X  X  X  0  X  X  X  X  X  X  X  X  0  X  X  X 
         28       0     0    X    X    X   X  X  X  X  X  0  X  X  X  X  X  X  X  X  0  X  X  X 
         29       0     0    X    X    X   X  X  X  X  X  0  X  X  X  X  X  X  X  X  0  X  X  X 
         30       0     0    X    X    X   X  X  X  X  X  0  X  X  X  X  X  X  X  X  0  X  X  X 
         31       0     0    X    X    X   X  X  X  X  X  0  X  X  X  X  X  X  X  X  0  X  X  X 
         32       0     0    X    X    X   X  X  X  X  X  0  X  X  X  X  X  X  X  X  0  X  X  X 
         33       0     0    X    X    X   X  X  X  X  X  0  X  X  X  X  X  X  X  X  0  X  X  X 
         34       0     0    X    X    X   X  X  X  X  X  0  X  X  X  X  X  X  X  X  0  X  X  X 
         35       0     0    X    X    X   X  X  X  X  X  0  X  X  X  X  X  X  X  X  0  X  X  X 
         36       0     0    X    X    X   X  X  X  X  X  0  X  X  X  X  X  X  X  X  0  X  X  X 
         37       0     0    X    X    X   X  X  X  X  X  0  X  X  X  X  X  X  X  X  0  X  X  X 
         38       0     0    X    X    X   X  X  X  X  X  0  X  X  X  X  X  X  X  X  0  X  X  X 
         39       0     0    X    X    X   X  X  X  X  X  0  X  X  X  X  X  X  X  X  0  X  X  X 
         40       0     0    X    X    X   X  X  X  X  X  0  X  X  X  X  X  X  X  X  0  X  X  X 
         41       0     0    X    X    X   X  X  X  X  X  0  X  X  X  X  X  X  X  X  0  X  X  X 
         42       0     0    X    X    X   X  X  X  X  X  0  X  X  X  X  X  X  X  X  0  X  X  X 
         43       0     0    X    X    X   X  X  X  X  X  0  X  X  X  X  X  X  X  X  0  X  X  X 
         44       0     0    X    X    X   X  X  X  X  X  0  X  X  X  X  X  X  X  X  0  X  X  X 
         45       0     0    X    X    X   X  X  X  X  X  0  X  X  X  X  X  X  X  X  0  X  X  X 
         46       0     0    X    X    X   X  X  X  X  X  0  X  X  X  X  X  X  X  X  0  X  X  X 
         47       0     0    X    X    X   X  X  X  X  X  0  X  X  X  X  X  X  X  X  0  X  X  X 
         48       0     0    X    X    X   X  X  X  X  X  0  X  X  X  X  X  X  X  X  0  X  X  X 
         49       0     0    X    X    X   X  X  X  X  X  0  X  X  X  X  X  X  X  X  0  X  X  X 
         50       0     0    X    X    X   X  X  X  X  X  0  X  X  X  X  X  X  X  X  0  X  X  X 
         51       0     0    X    X    X   X  X  X  X  X  0  X  X  X  X  X  X  X  X  0  X  X  X 
         52       0     0    X    X    X   X  X  X  X  X  0  X  X  X  X  X  X  X  X  0  X  X  X 
         53       0     0    X    X    X   X  X  X  X  X  0  X  X  X  X  X  X  X  X  0  X  X  X 
         54       0     0    X    X    X   X  X  X  X  X  0  X  X  X  X  X  X  X  X  0  X  X  X 
         55       0     0    X    X    X   X  X  X  X  X  0  X  X  X  X  X  X  X  X  0  X  X  X 
         56       0     0    X    X    X   X  X  X  X  X  0  X  X  X  X  X  X  X  X  0  X  X  X 
         57       0     0    X    X    X   X  X  X  X  X  0  X  X  X  X  X  X  X  X  0  X  X  X 
         58       0     0    X    X    X   X  X  X  X  X  0  X  X  X  X  X  X  X  X  0  X  X  X 
         59       0     0    X    X    X   X  X  X  X  X  0  X  X  X  X  X  X  X  X  0  X  X  X 
         60       0     0    X    X    X   X  X  X  X  X  0  X  X  X  X  X  X  X  X  0  X  X  X 
         61       0     0    X    X    X   X  X  X  X  X  0  X  X  X  X  X  X  X  X  0  X  X  X 
         62       0     0    X    X    X   X  X  X  X  X  1  X  X  X  X  X  X  X  X  1  X  X  X 
         63       0     0    X    X    X   X  X  X  X  X  1  X  X  X  X  X  X  X  X  1  X  X  X 
N3.C1: CMD-N xovercal offset = 0
N3.C1: CMD-S xovercal offset = 0
N3.C1: CTL xovercal offset   = 1
N3.C1: CKE xovercal offset   = 4
N3.C1: CLK xovercal offset   = 9
N3.C1.S18: STROBE                     0   1   2   3   4   5   6   7   8   9  10  11  12  13  14  15  16  17
N3.C1.S18: Rec En xovercal offset =  57  58  61  63   3   0  63  60   2  57  58  61  63   3   0  63  60   2 
N3.C1.S18: Tx Dqs xovercal offset =  57  63  63  63  63   0  63  63  63  63  63  63  63  63   0  63  63  63 
N3.C1.S18: Tx Dq xovercal offset  =  57  58  61  63   3   0  63  60   2  57  58  61  63   3   0  63  60   2 
N3.C1:         CMDn  CMDs  CTL  CKE  CLK   0  1  2  3  4  5  6  7  8
N3.C1: offsets:  0     0     1N3: getComplexCkeSetupTime defaultOffset = 98
N3: getComplexCkeSetupTime = 98
    4    9
Ctl Offsets Delta / final ctl offset / final cke offset /  98  /   3  /  38
Cke invertpiclk / Ctl invertpiclk / 0x0  /  0x0
N3: getComplexClkSetupTime defaultOffset = 0
N3: getComplexClkSetupTime = 0
ClkSetupTime = 41
N3: getComplexDqSetupTime defaultOffset = 0
N3: getComplexDqSetupTime = 0
N3.C1.S00: txdqoffset delta = 0, dq invertpiclk = 0
N3: getComplexDqsSetupTime defaultOffset = 40
N3: getComplexDqsSetupTime = 40
N3.C1.S00: txdqsoffset delta = 40
N3: getComplexRcvEnSetupTime defaultOffset = 37
N3: getComplexRcvEnSetupTime = 37
N3.C1.S00: rcvenoffset delta = 37
N3.C1.S00: Final txdqoffset / txdqsoffset / rcvenoffset / 57 / 33 / 30
N3: getComplexDqSetupTime defaultOffset = 0
N3: getComplexDqSetupTime = 0
N3.C1.S01: txdqoffset delta = 0, dq invertpiclk = 0
N3: getComplexDqsSetupTime defaultOffset = 40
N3: getComplexDqsSetupTime = 40
N3.C1.S01: txdqsoffset delta = 40
N3: getComplexRcvEnSetupTime defaultOffset = 37
N3: getComplexRcvEnSetupTime = 37
N3.C1.S01: rcvenoffset delta = 37
N3.C1.S01: Final txdqoffset / txdqsoffset / rcvenoffset / 26 /  2 / 63
N3: getComplexDqSetupTime defaultOffset = 0
N3: getComplexDqSetupTime = 0
N3.C1.S02: txdqoffset delta = 0, dq invertpiclk = 0
N3: getComplexDqsSetupTime defaultOffset = 40
N3: getComplexDqsSetupTime = 40
N3.C1.S02: txdqsoffset delta = 40
N3: getComplexRcvEnSetupTime defaultOffset = 37
N3: getComplexRcvEnSetupTime = 37
N3.C1.S02: rcvenoffset delta = 37
N3.C1.S02: Final txdqoffset / txdqsoffset / rcvenoffset / 61 / 37 / 34
N3: getComplexDqSetupTime defaultOffset = 0
N3: getComplexDqSetupTime = 0
N3.C1.S03: txdqoffset delta = 0, dq invertpiclk = 0
N3: getComplexDqsSetupTime defaultOffset = 40
N3: getComplexDqsSetupTime = 40
N3.C1.S03: txdqsoffset delta = 40
N3: getComplexRcvEnSetupTime defaultOffset = 37
N3: getComplexRcvEnSetupTime = 37
N3.C1.S03: rcvenoffset delta = 37
N3.C1.S03: Final txdqoffset / txdqsoffset / rcvenoffset / 31 /  7 /  4
N3: getComplexDqSetupTime defaultOffset = 0
N3: getComplexDqSetupTime = 0
N3.C1.S04: txdqoffset delta = 0, dq invertpiclk = 3
N3: getComplexDqsSetupTime defaultOffset = 40
N3: getComplexDqsSetupTime = 40
N3.C1.S04: txdqsoffset delta = 40
N3: getComplexRcvEnSetupTime defaultOffset = 37
N3: getComplexRcvEnSetupTime = 37
N3.C1.S04: rcvenoffset delta = 37
N3.C1.S04: Final txdqoffset / txdqsoffset / rcvenoffset /  3 / 43 / 40
N3: getComplexDqSetupTime defaultOffset = 0
N3: getComplexDqSetupTime = 0
N3.C1.S05: txdqoffset delta = 0, dq invertpiclk = 3
N3: getComplexDqsSetupTime defaultOffset = 40
N3: getComplexDqsSetupTime = 40
N3.C1.S05: txdqsoffset delta = 40
N3: getComplexRcvEnSetupTime defaultOffset = 37
N3: getComplexRcvEnSetupTime = 37
N3.C1.S05: rcvenoffset delta = 37
N3.C1.S05: Final txdqoffset / txdqsoffset / rcvenoffset / 32 /  8 /  5
N3: getComplexDqSetupTime defaultOffset = 0
N3: getComplexDqSetupTime = 0
N3.C1.S06: txdqoffset delta = 0, dq invertpiclk = 0
N3: getComplexDqsSetupTime defaultOffset = 40
N3: getComplexDqsSetupTime = 40
N3.C1.S06: txdqsoffset delta = 40
N3: getComplexRcvEnSetupTime defaultOffset = 37
N3: getComplexRcvEnSetupTime = 37
N3.C1.S06: rcvenoffset delta = 37
N3.C1.S06: Final txdqoffset / txdqsoffset / rcvenoffset / 63 / 39 / 36
N3: getComplexDqSetupTime defaultOffset = 0
N3: getComplexDqSetupTime = 0
N3.C1.S07: txdqoffset delta = 0, dq invertpiclk = 0
N3: getComplexDqsSetupTime defaultOffset = 40
N3: getComplexDqsSetupTime = 40
N3.C1.S07: txdqsoffset delta = 40
N3: getComplexRcvEnSetupTime defaultOffset = 37
N3: getComplexRcvEnSetupTime = 37
N3.C1.S07: rcvenoffset delta = 37
N3.C1.S07: Final txdqoffset / txdqsoffset / rcvenoffset / 28 /  4 /  1
N3: getComplexDqSetupTime defaultOffset = 0
N3: getComplexDqSetupTime = 0
N3.C1.S08: txdqoffset delta = 0, dq invertpiclk = 3
N3: getComplexDqsSetupTime defaultOffset = 40
N3: getComplexDqsSetupTime = 40
N3.C1.S08: txdqsoffset delta = 40
N3: getComplexRcvEnSetupTime defaultOffset = 37
N3: getComplexRcvEnSetupTime = 37
N3.C1.S08: rcvenoffset delta = 37
N3.C1.S08: Final txdqoffset / txdqsoffset / rcvenoffset /  2 / 42 / 39

Entry 0 - TrainDcc - DCCStart: 27, VocStart: 16, DCCFinal: 63, VocFinal: 16
Entry 0 - TrainDcc - DCCStart: 30, VocStart: 22, DCCFinal: 62, VocFinal: 22
Entry 0 - TrainDcc - DCCStart: 6, VocStart: 14, DCCFinal: 14, VocFinal: 14
Entry 1 - TrainDcc - DCCStart: 14, VocStart: 12, DCCFinal: 14, VocFinal: 12
Entry 1 - TrainDcc - DCCStart: 40, VocStart: 10, DCCFinal: 40, VocFinal: 10
Entry 1 - TrainDcc - DCCStart: 17, VocStart: 17, DCCFinal: 17, VocFinal: 17
N3: SetupJckSmbCfg: JCK VLINFREQ set to: 0x820F1028
Entry 2 - TrainDcc - DCCStart: 34, VocStart: 16, DCCFinal: 34, VocFinal: 16
Entry 2 - TrainDcc - DCCStart: 8, VocStart: 11, DCCFinal: 24, VocFinal: 11
Entry 2 - TrainDcc - DCCStart: 6, VocStart: 14, DCCFinal: 38, VocFinal: 14
N3: SetupJckSmbCfg: PLL is locked.
Entry 3 - TrainDcc - DCCStart: 16, VocStart: 17, DCCFinal: 16, VocFinal: 17
Entry 3 - TrainDcc - DCCStart: 33, VocStart: 13, DCCFinal: 33, VocFinal: 13
Entry 3 - TrainDcc - DCCStart: 8, VocStart: 11, DCCFinal: 8, VocFinal: 11
N3.C0: SetupJckSmbCfg: dlyFrms = 15
Entry 4 - TrainDcc - DCCStart: 39, VocStart: 12, DCCFinal: 39, VocFinal: 12
Entry 4 - TrainDcc - DCCStart: 31, VocStart: 10, DCCFinal: 31, VocFinal: 11
Entry 4 - TrainDcc - DCCStart: 30, VocStart: 16, DCCFinal: 30, VocFinal: 16
N3.C0: cwleffective = 8
Entry 5 - TrainDcc - DCCStart: 13, VocStart: 11, DCCFinal: 13, VocFinal: 11
Entry 5 - TrainDcc - DCCStart: 10, VocStart: 13, DCCFinal: 10, VocFinal: 13
Entry 5 - TrainDcc - DCCStart: 10, VocStart: 12, DCCFinal: 10, VocFinal: 12
N3.C0: PreVMSE Training raw cleff = 9, raw cwleff = 7
Entry 6 - TrainDcc - DCCStart: 20, VocStart: 13, DCCFinal: 20, VocFinal: 16
Entry 6 - TrainDcc - DCCStart: 31, VocStart: 11, DCCFinal: 31, VocFinal: 11
Entry 6 - TrainDcc - DCCStart: 8, VocStart: 11, DCCFinal: 8, VocFinal: 11
N3.C0: vmseratio = 0, revisionId = 5, vmse_mode = 1, QCRM_ENABLE = 0
Entry 7 - TrainDcc - DCCStart: 3, VocStart: 12, DCCFinal: 3, VocFinal: 12
Entry 7 - TrainDcc - DCCStart: 35, VocStart: 13, DCCFinal: 35, VocFinal: 13
Entry 7 - TrainDcc - DCCStart: 13, VocStart: 14, DCCFinal: 13, VocFinal: 14
N3: SetupJckSmbCfg: JCK wpsyncrcven = 5, wpsyncdata = 10
Entry 8 - TrainDcc - DCCStart: 25, VocStart: 13, DCCFinal: 25, VocFinal: 13
Entry 8 - TrainDcc - DCCStart: 18, VocStart: 13, DCCFinal: 18, VocFinal: 13
Entry 8 - TrainDcc - DCCStart: 13, VocStart: 10, DCCFinal: 13, VocFinal: 10
N0.C1.S00: VmseWriteTraining Final: centerPi = 0x39, PiEw = 0x28, centerVref = 0x47, vrefHeight = 0x28
N4.C1.S00: VmseWriteTraining Final: centerPi = 0x39, PiEw = 0x2B, centerVref = 0x41, vrefHeight = 0x28
N0.C1.S01: VmseWriteTraining Final: centerPi = 0x3C, PiEw = 0x2B, centerVref = 0x3F, vrefHeight = 0x2A
N4.C1.S01: VmseWriteTraining Final: centerPi = 0x37, PiEw = 0x2B, centerVref = 0x45, vrefHeight = 0x28
N6.C1.S00: VmseWriteTraining Final: centerPi = 0x36, PiEw = 0x2A, centerVref = 0x40, vrefHeight = 0x2E
N0.C1.S02: VmseWriteTraining Final: centerPi = 0x39, PiEw = 0x28, centerVref = 0x41, vrefHeight = 0x28
N4.C1.S02: VmseWriteTraining Final: centerPi = 0x37, PiEw = 0x2C, centerVref = 0x40, vrefHeight = 0x2A
N6.C1.S01: VmseWriteTraining Final: centerPi = 0x3B, PiEw = 0x29, centerVref = 0x3D, vrefHeight = 0x30
N0.C1.S03: VmseWriteTraining Final: centerPi = 0x39, PiEw = 0x2A, centerVref = 0x3C, vrefHeight = 0x2A
N4.C1.S03: VmseWriteTraining Final: centerPi = 0x37, PiEw = 0x29, centerVref = 0x3F, vrefHeight = 0x28
N6.C1.S02: VmseWriteTraining Final: centerPi = 0x33, PiEw = 0x2D, centerVref = 0x3C, vrefHeight = 0x30
N0.C1.S04: VmseWriteTraining Final: centerPi = 0x40, PiEw = 0x29, centerVref = 0x41, vrefHeight = 0x28
N4.C1.S04: VmseWriteTraining Final: centerPi = 0x3F, PiEw = 0x25, centerVref = 0x3B, vrefHeight = 0x28
N6.C1.S03: VmseWriteTraining Final: centerPi = 0x38, PiEw = 0x28, centerVref = 0x39, vrefHeight = 0x30
N0.C1.S05: VmseWriteTraining Final: centerPi = 0x3E, PiEw = 0x29, centerVref = 0x3E, vrefHeight = 0x26
N3.C0: SELF CAL 
N4.C1.S05: VmseWriteTraining Final: centerPi = 0x3C, PiEw = 0x29, centerVref = 0x3F, vrefHeight = 0x28
N6.C1.S04: VmseWriteTraining Final: centerPi = 0x3C, PiEw = 0x2A, centerVref = 0x39, vrefHeight = 0x2E
N0.C1.S06: VmseWriteTraining Final: centerPi = 0x3E, PiEw = 0x28, centerVref = 0x3C, vrefHeight = 0x2A
N3.C0: JckCompCodeCheck: Phase 1 - Comp Code Results
N4.C1.S06: VmseWriteTraining Final: centerPi = 0x3C, PiEw = 0x2A, centerVref = 0x40, vrefHeight = 0x2A
N6.C1.S05: VmseWriteTraining Final: centerPi = 0x37, PiEw = 0x2B, centerVref = 0x40, vrefHeight = 0x2C
N0.C1.S07: VmseWriteTraining Final: centerPi = 0x3E, PiEw = 0x29, centerVref = 0x40, vrefHeight = 0x2A
N3.C0: Cycle ron_up ron_eq_up ron_dn ron_eq_dn odt scomp_up scom_dn tcomp_l2h tcomp_h2l   bad_training
N4.C1.S07: VmseWriteTraining Final: centerPi = 0x3A, PiEw = 0x2A, centerVref = 0x40, vrefHeight = 0x2A
N6.C1.S06: VmseWriteTraining Final: centerPi = 0x37, PiEw = 0x2C, centerVref = 0x3C, vrefHeight = 0x2E
N0.C1.S08: VmseWriteTraining Final: centerPi = 0x3C, PiEw = 0x27, centerVref = 0x44, vrefHeight = 0x2A
N3.C0:  0       42     42       39      33      38     16      16        8       31       0
N4.C1.S08: VmseWriteTraining Final: centerPi = 0x3A, PiEw = 0x2A, centerVref = 0x42, vrefHeight = 0x2A
N6.C1.S07: VmseWriteTraining Final: centerPi = 0x37, PiEw = 0x2A, centerVref = 0x3B, vrefHeight = 0x2C
N0.C1.S09: VmseWriteTraining Final: centerPi = 0x3B, PiEw = 0x2A, centerVref = 0x40, vrefHeight = 0x28
N3.C0:  1       42     42       39      33      38     16      16       31        8       0
N4.C1.S09: VmseWriteTraining Final: centerPi = 0x3E, PiEw = 0x29, centerVref = 0x43, vrefHeight = 0x2A
N6.C1.S08: VmseWriteTraining Final: centerPi = 0x37, PiEw = 0x2C, centerVref = 0x43, vrefHeight = 0x30
N0.C1.S10: VmseWriteTraining Final: centerPi = 0x3B, PiEw = 0x28, centerVref = 0x3F, vrefHeight = 0x28
N3.C0:  2       42     42       39      33      38     16      16        8       31       0
N4.C1.S10: VmseWriteTraining Final: centerPi = 0x3B, PiEw = 0x25, centerVref = 0x42, vrefHeight = 0x2E
N6.C1.S09: VmseWriteTraining Final: centerPi = 0x3B, PiEw = 0x2B, centerVref = 0x3D, vrefHeight = 0x30
N0.C1.S11: VmseWriteTraining Final: centerPi = 0x3A, PiEw = 0x29, centerVref = 0x3E, vrefHeight = 0x2A
N3.C0:  3       42     42       39      33      38     16      16       31        8       0
N4.C1.S11: VmseWriteTraining Final: centerPi = 0x38, PiEw = 0x2C, centerVref = 0x41, vrefHeight = 0x28
N6.C1.S10: VmseWriteTraining Final: centerPi = 0x37, PiEw = 0x2A, centerVref = 0x40, vrefHeight = 0x32
N0.C1.S12: VmseWriteTraining Final: centerPi = 0x42, PiEw = 0x29, centerVref = 0x40, vrefHeight = 0x2A
N3.C0:  4       42     42       39      33      38     16      16        8       31       0
N4.C1.S12: VmseWriteTraining Final: centerPi = 0x42, PiEw = 0x23, centerVref = 0x40, vrefHeight = 0x2A
N6.C1.S11: VmseWriteTraining Final: centerPi = 0x35, PiEw = 0x2D, centerVref = 0x43, vrefHeight = 0x2E
N0.C1.S13: VmseWriteTraining Final: centerPi = 0x42, PiEw = 0x27, centerVref = 0x3F, vrefHeight = 0x28
N3.C0:  5       42     42       39      33      38     16      16       31        8       0
N4.C1.S13: VmseWriteTraining Final: centerPi = 0x3E, PiEw = 0x29, centerVref = 0x3C, vrefHeight = 0x26
N6.C1.S12: VmseWriteTraining Final: centerPi = 0x3B, PiEw = 0x28, centerVref = 0x40, vrefHeight = 0x2C
N0.C1.S14: VmseWriteTraining Final: centerPi = 0x40, PiEw = 0x26, centerVref = 0x3D, vrefHeight = 0x2A
N3.C0:  6       42     42       39      33      38     16      16        8       31       0
N4.C1.S14: VmseWriteTraining Final: centerPi = 0x3F, PiEw = 0x24, centerVref = 0x3E, vrefHeight = 0x2A
N6.C1.S13: VmseWriteTraining Final: centerPi = 0x3B, PiEw = 0x27, centerVref = 0x41, vrefHeight = 0x2E
N0.C1.S15: VmseWriteTraining Final: centerPi = 0x40, PiEw = 0x2B, centerVref = 0x43, vrefHeight = 0x2A
N3.C0:  7       42     42       39      33      38     16      16       31        8       0
N4.C1.S15: VmseWriteTraining Final: centerPi = 0x3F, PiEw = 0x2B, centerVref = 0x45, vrefHeight = 0x2A
N6.C1.S14: VmseWriteTraining Final: centerPi = 0x3F, PiEw = 0x26, centerVref = 0x3B, vrefHeight = 0x30
N0.C1.S16: VmseWriteTraining Final: centerPi = 0x39, PiEw = 0x2B, centerVref = 0x40, vrefHeight = 0x28
N3.C0:  8       42     42       39      34      38     17      17       31        8       0
N4.C1.S16: VmseWriteTraining Final: centerPi = 0x37, PiEw = 0x29, centerVref = 0x40, vrefHeight = 0x26
N6.C1.S15: VmseWriteTraining Final: centerPi = 0x3A, PiEw = 0x2B, centerVref = 0x41, vrefHeight = 0x2E
N0.C1.S17: VmseWriteTraining Final: centerPi = 0x3A, PiEw = 0x2A, centerVref = 0x3F, vrefHeight = 0x28
N3.C0:  9       42     42       40      33      38     16      16        8       31       0
N4.C1.S17: VmseWriteTraining Final: centerPi = 0x37, PiEw = 0x28, centerVref = 0x3D, vrefHeight = 0x26
N6.C1.S16: VmseWriteTraining Final: centerPi = 0x38, PiEw = 0x29, centerVref = 0x41, vrefHeight = 0x2C
N0.C1.S18: VmseWriteTraining Final: centerPi = 0x37, PiEw = 0x28, centerVref = 0x3A, vrefHeight = 0x2A
N3.C0: JckCompCodeCheck: Phase 2 - Check for bad ron_up vs average: num = 10, ron_up_avg = 42, ron_up_75avg = 31
N4.C1.S18: VmseWriteTraining Final: centerPi = 0x35, PiEw = 0x28, centerVref = 0x40, vrefHeight = 0x26
N6.C1.S17: VmseWriteTraining Final: centerPi = 0x35, PiEw = 0x27, centerVref = 0x42, vrefHeight = 0x28
N0.C1.S19: VmseWriteTraining Final: centerPi = 0x37, PiEw = 0x2B, centerVref = 0x3C, vrefHeight = 0x2A
N3.C0: Cycle ron_up ron_eq_up ron_dn ron_eq_dn odt scomp_up scom_dn tcomp_l2h tcomp_h2l   bad_training
N4.C1.S19: VmseWriteTraining Final: centerPi = 0x35, PiEw = 0x2A, centerVref = 0x3B, vrefHeight = 0x2C
N6.C1.S18: VmseWriteTraining Final: centerPi = 0x39, PiEw = 0x27, centerVref = 0x41, vrefHeight = 0x30
N0.C1.S20: VmseWriteTraining Final: centerPi = 0x3C, PiEw = 0x29, centerVref = 0x43, vrefHeight = 0x28
N3.C0: JckCompCodeCheck: Phase 3 - Comp Code Limits
N4.C1.S20: VmseWriteTraining Final: centerPi = 0x3D, PiEw = 0x28, centerVref = 0x3D, vrefHeight = 0x26
N6.C1.S19: VmseWriteTraining Final: centerPi = 0x36, PiEw = 0x2A, centerVref = 0x3D, vrefHeight = 0x30
N0.C1.S21: VmseWriteTraining Final: centerPi = 0x3A, PiEw = 0x27, centerVref = 0x40, vrefHeight = 0x28
N3.C0: ron_up_limitdn   ron_dn_limitup   ron_eq_dn_limtdn  odt_limitdn
N4.C1.S21: VmseWriteTraining Final: centerPi = 0x3E, PiEw = 0x24, centerVref = 0x3C, vrefHeight = 0x2A
N6.C1.S20: VmseWriteTraining Final: centerPi = 0x3B, PiEw = 0x29, centerVref = 0x40, vrefHeight = 0x2A
N0.C1.S22: VmseWriteTraining Final: centerPi = 0x39, PiEw = 0x28, centerVref = 0x3C, vrefHeight = 0x26
N3.C0:     26                46                22             24
N4.C1.S22: VmseWriteTraining Final: centerPi = 0x3B, PiEw = 0x27, centerVref = 0x3C, vrefHeight = 0x2A
N6.C1.S21: VmseWriteTraining Final: centerPi = 0x3B, PiEw = 0x25, centerVref = 0x3D, vrefHeight = 0x2C
N0.C1.S23: VmseWriteTraining Final: centerPi = 0x3A, PiEw = 0x2A, centerVref = 0x44, vrefHeight = 0x26
N3.C0: JckCompCodeCheck: Phase 3 - SUCCESS
N4.C1.S23: VmseWriteTraining Final: centerPi = 0x39, PiEw = 0x27, centerVref = 0x40, vrefHeight = 0x22
N6.C1.S22: VmseWriteTraining Final: centerPi = 0x38, PiEw = 0x26, centerVref = 0x3E, vrefHeight = 0x28
N0.C1.S24: VmseWriteTraining Final: centerPi = 0x3C, PiEw = 0x24, centerVref = 0x3F, vrefHeight = 0x28
N3.C0: VmseOverrideJckCompCodes
N4.C1.S24: VmseWriteTraining Final: centerPi = 0x3A, PiEw = 0x26, centerVref = 0x3D, vrefHeight = 0x28
N6.C1.S23: VmseWriteTraining Final: centerPi = 0x3B, PiEw = 0x26, centerVref = 0x3E, vrefHeight = 0x2C
N0.C1.S25: VmseWriteTraining Final: centerPi = 0x3D, PiEw = 0x26, centerVref = 0x3D, vrefHeight = 0x2C
N4.C1.S25: VmseWriteTraining Final: centerPi = 0x3B, PiEw = 0x27, centerVref = 0x3D, vrefHeight = 0x2C
N6.C1.S24: VmseWriteTraining Final: centerPi = 0x3A, PiEw = 0x27, centerVref = 0x41, vrefHeight = 0x30
N0.C1.S26: VmseWriteTraining Final: centerPi = 0x3D, PiEw = 0x27, centerVref = 0x41, vrefHeight = 0x2C
N4.C1.S26: VmseWriteTraining Final: centerPi = 0x3A, PiEw = 0x26, centerVref = 0x3C, vrefHeight = 0x2C
N6.C1.S25: VmseWriteTraining Final: centerPi = 0x37, PiEw = 0x2D, centerVref = 0x40, vrefHeight = 0x2C
N0.C1.S27: VmseWriteTraining Final: centerPi = 0x39, PiEw = 0x27, centerVref = 0x3E, vrefHeight = 0x2C
N4.C1.S27: VmseWriteTraining Final: centerPi = 0x39, PiEw = 0x27, centerVref = 0x3B, vrefHeight = 0x2C
N6.C1.S26: VmseWriteTraining Final: centerPi = 0x3C, PiEw = 0x27, centerVref = 0x39, vrefHeight = 0x32
N0.C1.S28: VmseWriteTraining Final: centerPi = 0x3E, PiEw = 0x1D, centerVref = 0x40, vrefHeight = 0x22
N4.C1.S28: VmseWriteTraining Final: centerPi = 0x3D, PiEw = 0x21, centerVref = 0x3B, vrefHeight = 0x20
N6.C1.S27: VmseWriteTraining Final: centerPi = 0x34, PiEw = 0x27, centerVref = 0x3E, vrefHeight = 0x2C
N0.C1.S29: VmseWriteTraining Final: centerPi = 0x3E, PiEw = 0x24, centerVref = 0x3B, vrefHeight = 0x26
N4.C1.S29: VmseWriteTraining Final: centerPi = 0x3E, PiEw = 0x23, centerVref = 0x3F, vrefHeight = 0x24
N6.C1.S28: VmseWriteTraining Final: centerPi = 0x3E, PiEw = 0x1D, centerVref = 0x36, vrefHeight = 0x28
N0.C1.S30: VmseWriteTraining Final: centerPi = 0x41, PiEw = 0x25, centerVref = 0x40, vrefHeight = 0x2A
N4.C1.S30: VmseWriteTraining Final: centerPi = 0x3F, PiEw = 0x25, centerVref = 0x3F, vrefHeight = 0x2C
N6.C1.S29: VmseWriteTraining Final: centerPi = 0x39, PiEw = 0x24, centerVref = 0x3C, vrefHeight = 0x28
N0.C1.S31: VmseWriteTraining Final: centerPi = 0x3F, PiEw = 0x27, centerVref = 0x3D, vrefHeight = 0x24
N4.C1.S31: VmseWriteTraining Final: centerPi = 0x3D, PiEw = 0x24, centerVref = 0x3A, vrefHeight = 0x26
N6.C1.S30: VmseWriteTraining Final: centerPi = 0x3D, PiEw = 0x26, centerVref = 0x3F, vrefHeight = 0x30
N0.C1.S32: VmseWriteTraining Final: centerPi = 0x3B, PiEw = 0x2A, centerVref = 0x42, vrefHeight = 0x26
N4.C1.S32: VmseWriteTraining Final: centerPi = 0x39, PiEw = 0x29, centerVref = 0x3E, vrefHeight = 0x26
N6.C1.S31: VmseWriteTraining Final: centerPi = 0x3C, PiEw = 0x29, centerVref = 0x38, vrefHeight = 0x2A
N0.C1.S33: VmseWriteTraining Final: centerPi = 0x3C, PiEw = 0x2B, centerVref = 0x3A, vrefHeight = 0x2A
N4.C1.S33: VmseWriteTraining Final: centerPi = 0x38, PiEw = 0x2B, centerVref = 0x3F, vrefHeight = 0x28
N6.C1.S32: VmseWriteTraining Final: centerPi = 0x3E, PiEw = 0x21, centerVref = 0x3C, vrefHeight = 0x2C
N0.C1.S34: VmseWriteTraining Final: centerPi = 0x3A, PiEw = 0x28, centerVref = 0x3F, vrefHeight = 0x2C
N4.C1.S34: VmseWriteTraining Final: centerPi = 0x38, PiEw = 0x25, centerVref = 0x3F, vrefHeight = 0x2A
N6.C1.S33: VmseWriteTraining Final: centerPi = 0x38, PiEw = 0x2D, centerVref = 0x42, vrefHeight = 0x2C
N0.C1.S35: VmseWriteTraining Final: centerPi = 0x37, PiEw = 0x2C, centerVref = 0x40, vrefHeight = 0x2A
N4.C1.S35: VmseWriteTraining Final: centerPi = 0x37, PiEw = 0x2A, centerVref = 0x40, vrefHeight = 0x2C
N6.C1.S34: VmseWriteTraining Final: centerPi = 0x3E, PiEw = 0x22, centerVref = 0x39, vrefHeight = 0x30
N0.C1.S36: VmseWriteTraining Final: centerPi = 0x3F, PiEw = 0x29, centerVref = 0x3E, vrefHeight = 0x28
N4.C1.S36: VmseWriteTraining Final: centerPi = 0x41, PiEw = 0x27, centerVref = 0x3C, vrefHeight = 0x2A
N6.C1.S35: VmseWriteTraining Final: centerPi = 0x3B, PiEw = 0x29, centerVref = 0x39, vrefHeight = 0x30
N0.C1.S37: VmseWriteTraining Final: centerPi = 0x3C, PiEw = 0x28, centerVref = 0x3E, vrefHeight = 0x28
N4.C1.S37: VmseWriteTraining Final: centerPi = 0x3D, PiEw = 0x27, centerVref = 0x41, vrefHeight = 0x28
N6.C1.S36: VmseWriteTraining Final: centerPi = 0x3D, PiEw = 0x21, centerVref = 0x42, vrefHeight = 0x2C
N0.C1.S38: VmseWriteTraining Final: centerPi = 0x3F, PiEw = 0x29, centerVref = 0x3B, vrefHeight = 0x2A
N4.C1.S38: VmseWriteTraining Final: centerPi = 0x3B, PiEw = 0x26, centerVref = 0x3C, vrefHeight = 0x26
N6.C1.S37: VmseWriteTraining Final: centerPi = 0x3C, PiEw = 0x28, centerVref = 0x3D, vrefHeight = 0x2C
N0.C1.S39: VmseWriteTraining Final: centerPi = 0x3D, PiEw = 0x28, centerVref = 0x40, vrefHeight = 0x26
N4.C1.S39: VmseWriteTraining Final: centerPi = 0x3C, PiEw = 0x27, centerVref = 0x3E, vrefHeight = 0x28
N6.C1.S38: VmseWriteTraining Final: centerPi = 0x3F, PiEw = 0x26, centerVref = 0x3C, vrefHeight = 0x2E
N0.C1.S40: VmseWriteTraining Final: centerPi = 0x3C, PiEw = 0x26, centerVref = 0x3D, vrefHeight = 0x28
N4.C1.S40: VmseWriteTraining Final: centerPi = 0x3D, PiEw = 0x21, centerVref = 0x3C, vrefHeight = 0x2A
N6.C1.S39: VmseWriteTraining Final: centerPi = 0x40, PiEw = 0x24, centerVref = 0x3E, vrefHeight = 0x2E
N0.C1.S41: VmseWriteTraining Final: centerPi = 0x3B, PiEw = 0x29, centerVref = 0x42, vrefHeight = 0x2A
N4.C1.S41: VmseWriteTraining Final: centerPi = 0x3C, PiEw = 0x2A, centerVref = 0x3E, vrefHeight = 0x2A
N6.C1.S40: VmseWriteTraining Final: centerPi = 0x3D, PiEw = 0x27, centerVref = 0x40, vrefHeight = 0x30
N0.C1.S42: VmseWriteTraining Final: centerPi = 0x39, PiEw = 0x23, centerVref = 0x40, vrefHeight = 0x2A
N4.C1.S42: VmseWriteTraining Final: centerPi = 0x39, PiEw = 0x21, centerVref = 0x39, vrefHeight = 0x28
N6.C1.S41: VmseWriteTraining Final: centerPi = 0x3C, PiEw = 0x2A, centerVref = 0x3D, vrefHeight = 0x30
N0.C1.S43: VmseWriteTraining Final: centerPi = 0x39, PiEw = 0x27, centerVref = 0x42, vrefHeight = 0x28
N4.C1.S43: VmseWriteTraining Final: centerPi = 0x37, PiEw = 0x28, centerVref = 0x3E, vrefHeight = 0x2A
N6.C1.S42: VmseWriteTraining Final: centerPi = 0x3C, PiEw = 0x23, centerVref = 0x38, vrefHeight = 0x30
N0.C1.S44: VmseWriteTraining Final: centerPi = 0x40, PiEw = 0x24, centerVref = 0x3A, vrefHeight = 0x2A
N4.C1.S44: VmseWriteTraining Final: centerPi = 0x3D, PiEw = 0x25, centerVref = 0x3C, vrefHeight = 0x28
N6.C1.S43: VmseWriteTraining Final: centerPi = 0x3D, PiEw = 0x26, centerVref = 0x3B, vrefHeight = 0x2E
N0.C1.S45: VmseWriteTraining Final: centerPi = 0x3F, PiEw = 0x28, centerVref = 0x41, vrefHeight = 0x28
N4.C1.S45: VmseWriteTraining Final: centerPi = 0x39, PiEw = 0x29, centerVref = 0x40, vrefHeight = 0x26
N6.C1.S44: VmseWriteTraining Final: centerPi = 0x3E, PiEw = 0x27, centerVref = 0x3E, vrefHeight = 0x2C
N0.C1.S46: VmseWriteTraining Final: centerPi = 0x3E, PiEw = 0x26, centerVref = 0x40, vrefHeight = 0x2A
N4.C1.S46: VmseWriteTraining Final: centerPi = 0x3E, PiEw = 0x21, centerVref = 0x3C, vrefHeight = 0x2A
N6.C1.S45: VmseWriteTraining Final: centerPi = 0x3F, PiEw = 0x24, centerVref = 0x3D, vrefHeight = 0x2C
N0.C1.S47: VmseWriteTraining Final: centerPi = 0x3E, PiEw = 0x2A, centerVref = 0x44, vrefHeight = 0x2A
N3: SetupJckSmbCfg: JCK VLINFREQ set to: 0x820F1028
N4.C1.S47: VmseWriteTraining Final: centerPi = 0x3B, PiEw = 0x2B, centerVref = 0x41, vrefHeight = 0x28
N6.C1.S46: VmseWriteTraining Final: centerPi = 0x3C, PiEw = 0x28, centerVref = 0x3F, vrefHeight = 0x30
N0.C1.S48: VmseWriteTraining Final: centerPi = 0x3E, PiEw = 0x27, centerVref = 0x40, vrefHeight = 0x26
N3: SetupJckSmbCfg: PLL is locked.
N4.C1.S48: VmseWriteTraining Final: centerPi = 0x39, PiEw = 0x2A, centerVref = 0x43, vrefHeight = 0x24
N6.C1.S47: VmseWriteTraining Final: centerPi = 0x3E, PiEw = 0x2B, centerVref = 0x43, vrefHeight = 0x2C
N0.C1.S49: VmseWriteTraining Final: centerPi = 0x3E, PiEw = 0x28, centerVref = 0x39, vrefHeight = 0x28
N3.C2: SetupJckSmbCfg: dlyFrms = 15
N4.C1.S49: VmseWriteTraining Final: centerPi = 0x3F, PiEw = 0x25, centerVref = 0x3C, vrefHeight = 0x2A
N6.C1.S48: VmseWriteTraining Final: centerPi = 0x3A, PiEw = 0x29, centerVref = 0x43, vrefHeight = 0x28
N0.C1.S50: VmseWriteTraining Final: centerPi = 0x3D, PiEw = 0x25, centerVref = 0x3F, vrefHeight = 0x28
N3.C2: cwleffective = 8
N4.C1.S50: VmseWriteTraining Final: centerPi = 0x3A, PiEw = 0x27, centerVref = 0x40, vrefHeight = 0x2A
N6.C1.S49: VmseWriteTraining Final: centerPi = 0x3C, PiEw = 0x2B, centerVref = 0x3B, vrefHeight = 0x30
N0.C1.S51: VmseWriteTraining Final: centerPi = 0x3C, PiEw = 0x2A, centerVref = 0x40, vrefHeight = 0x2A
N3.C2: PreVMSE Training raw cleff = 9, raw cwleff = 7
N4.C1.S51: VmseWriteTraining Final: centerPi = 0x3B, PiEw = 0x29, centerVref = 0x3F, vrefHeight = 0x2C
N6.C1.S50: VmseWriteTraining Final: centerPi = 0x3C, PiEw = 0x26, centerVref = 0x40, vrefHeight = 0x30
N0.C1.S52: VmseWriteTraining Final: centerPi = 0x42, PiEw = 0x26, centerVref = 0x41, vrefHeight = 0x28
N3.C2: vmseratio = 0, revisionId = 5, vmse_mode = 1, QCRM_ENABLE = 0
N4.C1.S52: VmseWriteTraining Final: centerPi = 0x42, PiEw = 0x26, centerVref = 0x3C, vrefHeight = 0x2A
N6.C1.S51: VmseWriteTraining Final: centerPi = 0x37, PiEw = 0x29, centerVref = 0x3D, vrefHeight = 0x2E
N0.C1.S53: VmseWriteTraining Final: centerPi = 0x41, PiEw = 0x29, centerVref = 0x3E, vrefHeight = 0x26
N3: SetupJckSmbCfg: JCK wpsyncrcven = 5, wpsyncdata = 10
N4.C1.S53: VmseWriteTraining Final: centerPi = 0x41, PiEw = 0x28, centerVref = 0x3D, vrefHeight = 0x28
N6.C1.S52: VmseWriteTraining Final: centerPi = 0x3E, PiEw = 0x24, centerVref = 0x3D, vrefHeight = 0x2C
N0.C1.S54: VmseWriteTraining Final: centerPi = 0x40, PiEw = 0x25, centerVref = 0x3F, vrefHeight = 0x28
N4.C1.S54: VmseWriteTraining Final: centerPi = 0x3E, PiEw = 0x27, centerVref = 0x40, vrefHeight = 0x2A
N6.C1.S53: VmseWriteTraining Final: centerPi = 0x3C, PiEw = 0x26, centerVref = 0x3C, vrefHeight = 0x28
N0.C1.S55: VmseWriteTraining Final: centerPi = 0x41, PiEw = 0x27, centerVref = 0x3F, vrefHeight = 0x28
N4.C1.S55: VmseWriteTraining Final: centerPi = 0x3E, PiEw = 0x26, centerVref = 0x3F, vrefHeight = 0x28
N6.C1.S54: VmseWriteTraining Final: centerPi = 0x3E, PiEw = 0x28, centerVref = 0x3D, vrefHeight = 0x2E
N0.C1.S56: VmseWriteTraining Final: centerPi = 0x3D, PiEw = 0x29, centerVref = 0x3E, vrefHeight = 0x26
N4.C1.S56: VmseWriteTraining Final: centerPi = 0x3C, PiEw = 0x27, centerVref = 0x3E, vrefHeight = 0x26
N6.C1.S55: VmseWriteTraining Final: centerPi = 0x3B, PiEw = 0x29, centerVref = 0x42, vrefHeight = 0x2A
N0.C1.S57: VmseWriteTraining Final: centerPi = 0x3E, PiEw = 0x2A, centerVref = 0x42, vrefHeight = 0x28
N4.C1.S57: VmseWriteTraining Final: centerPi = 0x3D, PiEw = 0x2A, centerVref = 0x43, vrefHeight = 0x28
N6.C1.S56: VmseWriteTraining Final: centerPi = 0x38, PiEw = 0x2C, centerVref = 0x44, vrefHeight = 0x2A
N0.C1.S58: VmseWriteTraining Final: centerPi = 0x3C, PiEw = 0x2A, centerVref = 0x42, vrefHeight = 0x2A
N4.C1.S58: VmseWriteTraining Final: centerPi = 0x3F, PiEw = 0x22, centerVref = 0x39, vrefHeight = 0x2C
N6.C1.S57: VmseWriteTraining Final: centerPi = 0x3A, PiEw = 0x2A, centerVref = 0x39, vrefHeight = 0x2E
N0.C1.S59: VmseWriteTraining Final: centerPi = 0x3B, PiEw = 0x2C, centerVref = 0x40, vrefHeight = 0x2A
N4.C1.S59: VmseWriteTraining Final: centerPi = 0x3C, PiEw = 0x25, centerVref = 0x3F, vrefHeight = 0x28
N6.C1.S58: VmseWriteTraining Final: centerPi = 0x39, PiEw = 0x2C, centerVref = 0x3E, vrefHeight = 0x2C
N0.C1.S60: VmseWriteTraining Final: centerPi = 0x42, PiEw = 0x26, centerVref = 0x3C, vrefHeight = 0x28
N4.C1.S60: VmseWriteTraining Final: centerPi = 0x45, PiEw = 0x24, centerVref = 0x39, vrefHeight = 0x2A
N6.C1.S59: VmseWriteTraining Final: centerPi = 0x37, PiEw = 0x2C, centerVref = 0x3E, vrefHeight = 0x2E
N0.C1.S61: VmseWriteTraining Final: centerPi = 0x40, PiEw = 0x28, centerVref = 0x42, vrefHeight = 0x26
N4.C1.S61: VmseWriteTraining Final: centerPi = 0x40, PiEw = 0x27, centerVref = 0x3E, vrefHeight = 0x26
N6.C1.S60: VmseWriteTraining Final: centerPi = 0x3F, PiEw = 0x28, centerVref = 0x39, vrefHeight = 0x2E
N0.C1.S62: VmseWriteTraining Final: centerPi = 0x40, PiEw = 0x2B, centerVref = 0x3E, vrefHeight = 0x2A
N4.C1.S62: VmseWriteTraining Final: centerPi = 0x40, PiEw = 0x29, centerVref = 0x3D, vrefHeight = 0x2A
N6.C1.S61: VmseWriteTraining Final: centerPi = 0x3D, PiEw = 0x26, centerVref = 0x41, vrefHeight = 0x2C
N0.C1.S63: VmseWriteTraining Final: centerPi = 0x40, PiEw = 0x29, centerVref = 0x40, vrefHeight = 0x2A
N4.C1.S63: VmseWriteTraining Final: centerPi = 0x41, PiEw = 0x24, centerVref = 0x42, vrefHeight = 0x28
N6.C1.S62: VmseWriteTraining Final: centerPi = 0x3E, PiEw = 0x2A, centerVref = 0x43, vrefHeight = 0x30
N0.C1.S64: VmseWriteTraining Final: centerPi = 0x39, PiEw = 0x25, centerVref = 0x42, vrefHeight = 0x26
N4.C1.S64: VmseWriteTraining Final: centerPi = 0x37, PiEw = 0x29, centerVref = 0x40, vrefHeight = 0x24
N6.C1.S63: VmseWriteTraining Final: centerPi = 0x3E, PiEw = 0x2A, centerVref = 0x41, vrefHeight = 0x30
N0.C1.S65: VmseWriteTraining Final: centerPi = 0x36, PiEw = 0x25, centerVref = 0x3F, vrefHeight = 0x24
N4.C1.S65: VmseWriteTraining Final: centerPi = 0x36, PiEw = 0x24, centerVref = 0x40, vrefHeight = 0x24
N6.C1.S64: VmseWriteTraining Final: centerPi = 0x38, PiEw = 0x28, centerVref = 0x40, vrefHeight = 0x2C
N0.C1.S66: VmseWriteTraining Final: centerPi = 0x39, PiEw = 0x20, centerVref = 0x3E, vrefHeight = 0x26
N4.C1.S66: VmseWriteTraining Final: centerPi = 0x34, PiEw = 0x25, centerVref = 0x42, vrefHeight = 0x20
N6.C1.S65: VmseWriteTraining Final: centerPi = 0x36, PiEw = 0x24, centerVref = 0x3E, vrefHeight = 0x2A
N0.C1.S67: VmseWriteTraining Final: centerPi = 0x39, PiEw = 0x22, centerVref = 0x3D, vrefHeight = 0x2C
N3.C1: SELF CAL 
N4.C1.S67: VmseWriteTraining Final: centerPi = 0x3A, PiEw = 0x24, centerVref = 0x3D, vrefHeight = 0x28
N6.C1.S66: VmseWriteTraining Final: centerPi = 0x39, PiEw = 0x24, centerVref = 0x3B, vrefHeight = 0x2C
N0.C1.S68: VmseWriteTraining Final: centerPi = 0x3F, PiEw = 0x25, centerVref = 0x3D, vrefHeight = 0x28
N3.C1: JckCompCodeCheck: Phase 1 - Comp Code Results
N4.C1.S68: VmseWriteTraining Final: centerPi = 0x3D, PiEw = 0x26, centerVref = 0x46, vrefHeight = 0x2A
N6.C1.S67: VmseWriteTraining Final: centerPi = 0x39, PiEw = 0x26, centerVref = 0x3E, vrefHeight = 0x2E
N0.C1.S69: VmseWriteTraining Final: centerPi = 0x3E, PiEw = 0x25, centerVref = 0x43, vrefHeight = 0x28
N3.C1: Cycle ron_up ron_eq_up ron_dn ron_eq_dn odt scomp_up scom_dn tcomp_l2h tcomp_h2l   bad_training
N4.C1.S69: VmseWriteTraining Final: centerPi = 0x3C, PiEw = 0x22, centerVref = 0x3E, vrefHeight = 0x26
N6.C1.S68: VmseWriteTraining Final: centerPi = 0x3C, PiEw = 0x26, centerVref = 0x41, vrefHeight = 0x2A
N0.C1.S70: VmseWriteTraining Final: centerPi = 0x3D, PiEw = 0x25, centerVref = 0x40, vrefHeight = 0x2A
N3.C1:  0       42     42       39      33      39     16      16       12       31       0
N4.C1.S70: VmseWriteTraining Final: centerPi = 0x3C, PiEw = 0x24, centerVref = 0x3F, vrefHeight = 0x2C
N6.C1.S69: VmseWriteTraining Final: centerPi = 0x3B, PiEw = 0x24, centerVref = 0x3D, vrefHeight = 0x2C
N0.C1.S71: VmseWriteTraining Final: centerPi = 0x3D, PiEw = 0x27, centerVref = 0x3F, vrefHeight = 0x28
N3.C1:  1       42     42       39      33      38     15      15       12       31       0
N4.C1.S71: VmseWriteTraining Final: centerPi = 0x3B, PiEw = 0x26, centerVref = 0x3C, vrefHeight = 0x26
N6.C1.S70: VmseWriteTraining Final: centerPi = 0x3D, PiEw = 0x27, centerVref = 0x3B, vrefHeight = 0x30

END - VMSE Train Write                 Time         8734 ms

END - VMSE Train Write                 Time         8622 ms
N6.C1.S71: VmseWriteTraining Final: centerPi = 0x3C, PiEw = 0x2A, centerVref = 0x40, vrefHeight = 0x2A
Checkpoint Code: Socket 0, 0xB6, 0x64, 0x0000
N3.C1:  2       42     42       39      33      38     15      15       14       31       0
N4: 
Total VMSE trainings latency = 21164 ms

END - VMSE Train Write                 Time         8277 ms
N0: 
Total VMSE trainings latency = 22291 ms
N5: GatherSPDData
N6: 
Total VMSE trainings latency = 21139 ms
Checkpoint Code: Socket 0, 0xB5, 0x00, 0x0000
Gather SPD Data
N7: GatherSPDData
N1: GatherSPDData
N3.C1:  3       42     42       39      33      38     16      16       13       31       0
N5.C0.D0: tWR in MTB units: 0x78
Gather SPD Data
Gather SPD Data
N7.C0.D0: tWR in MTB units: 0x78
N1.C0.D0: tWR in MTB units: 0x78
N5.C1.D0: tWR in MTB units: 0x78
N3.C1:  4       42     42       39      33      38     15      15       15       31       0
N7.C1.D0: tWR in MTB units: 0x78
N1.C1.D0: tWR in MTB units: 0x78
N5.C2.D0: tWR in MTB units: 0x78
N7.C2.D0: tWR in MTB units: 0x78
N1.C2.D0: tWR in MTB units: 0x78
N3.C1:  5       42     42       39      33      38     15      15       13       31       0
N5.C3.D0: tWR in MTB units: 0x78
N7.C3.D0: tWR in MTB units: 0x78
N1.C3.D0: tWR in MTB units: 0x78

GatherSPDData time            120 ms
N5: GlobalEarlyConfig
N5: Global Early Configuration

GatherSPDData time            109 ms

GatherSPDData time            111 ms
N3.C1:  6       42     42       39      33      38     15      15       12       31       0
N5.C0: GlobalEarlyConfig: mcmntChknbit.frc_mddl_on = 1
N7: GlobalEarlyConfig
N1: GlobalEarlyConfig
N5.C0.D0: Config DIMMMTR_0_MCDDC_DESC_REG: 000C5051
N7: Global Early Configuration
N1: Global Early Configuration
N5.C0: RX Vref Default = 32
N7.C0: GlobalEarlyConfig: mcmntChknbit.frc_mddl_on = 1
N1.C0: GlobalEarlyConfig: mcmntChknbit.frc_mddl_on = 1
N3.C1:  7       42     42       39      32      39     15      15       12       31       0
N5.C1: GlobalEarlyConfig: mcmntChknbit.frc_mddl_on = 1
N7.C0.D0: Config DIMMMTR_0_MCDDC_DESC_REG: 000C5051
N1.C0.D0: Config DIMMMTR_0_MCDDC_DESC_REG: 000C5051
N5.C1.D0: Config DIMMMTR_0_MCDDC_DESC_REG: 000C5051
N7.C0: RX Vref Default = 32
N1.C0: RX Vref Default = 32
N5.C1: RX Vref Default = 32
N7.C1: GlobalEarlyConfig: mcmntChknbit.frc_mddl_on = 1
N1.C1: GlobalEarlyConfig: mcmntChknbit.frc_mddl_on = 1
N3.C1:  8       42     42       39      33      39     16      16       11       31       0
N5.C2: GlobalEarlyConfig: mcmntChknbit.frc_mddl_on = 1
N7.C1.D0: Config DIMMMTR_0_MCDDC_DESC_REG: 000C5051
N1.C1.D0: Config DIMMMTR_0_MCDDC_DESC_REG: 000C5051
N5.C2.D0: Config DIMMMTR_0_MCDDC_DESC_REG: 000C5051
N7.C1: RX Vref Default = 32
N1.C1: RX Vref Default = 32
N5.C2: RX Vref Default = 32
N7.C2: GlobalEarlyConfig: mcmntChknbit.frc_mddl_on = 1
N1.C2: GlobalEarlyConfig: mcmntChknbit.frc_mddl_on = 1
N3.C1:  9       42     42       39      33      39     15      15       12       31       0
N5.C3: GlobalEarlyConfig: mcmntChknbit.frc_mddl_on = 1
N7.C2.D0: Config DIMMMTR_0_MCDDC_DESC_REG: 000C5051
N1.C2.D0: Config DIMMMTR_0_MCDDC_DESC_REG: 000C5051
N3.C1: JckCompCodeCheck: Phase 2 - Check for bad ron_up vs average: num = 10, ron_up_avg = 42, ron_up_75avg = 31
N5.C3.D0: Config DIMMMTR_0_MCDDC_DESC_REG: 000C5051
N7.C2: RX Vref Default = 32
N1.C2: RX Vref Default = 32
N3.C1: Cycle ron_up ron_eq_up ron_dn ron_eq_dn odt scomp_up scom_dn tcomp_l2h tcomp_h2l   bad_training
N5.C3: RX Vref Default = 32
N7.C3: GlobalEarlyConfig: mcmntChknbit.frc_mddl_on = 1
N1.C3: GlobalEarlyConfig: mcmntChknbit.frc_mddl_on = 1
N3.C1: JckCompCodeCheck: Phase 3 - Comp Code Limits
N5: ChannelEarlyConfig
N7.C3.D0: Config DIMMMTR_0_MCDDC_DESC_REG: 000C5051
N1.C3.D0: Config DIMMMTR_0_MCDDC_DESC_REG: 000C5051
N3.C1: ron_up_limitdn   ron_dn_limitup   ron_eq_dn_limtdn  odt_limitdn
N5: Channel Early Configuration
N7.C3: RX Vref Default = 32
N1.C3: RX Vref Default = 32
N3.C1:     26                46                21             24
N5.C0: Enable = 1
N7: ChannelEarlyConfig
Checkpoint Code: Socket 0, 0xB8, 0x00, 0x0000
N3.C1: JckCompCodeCheck: Phase 3 - SUCCESS
N5.C0.D0: Enable = 1
N7: Channel Early Configuration
N1: ChannelEarlyConfig
N3.C1: VmseOverrideJckCompCodes
N5.C0.D0.R0: Enable = 1
N7.C0: Enable = 1
N1: Channel Early Configuration
N5.C0.D0.R0: ENABLED: ckeMask = 00000001
N7.C0.D0: Enable = 1
N1.C0: Enable = 1
N5.C0.D0.R1: Enable = 1
N7.C0.D0.R0: Enable = 1
N1.C0.D0: Enable = 1
N5.C0.D0.R1: ENABLED: ckeMask = 00000003
N7.C0.D0.R0: ENABLED: ckeMask = 00000001
N1.C0.D0.R0: Enable = 1
N5.C0.D0.R2: Enable = 0
N7.C0.D0.R1: Enable = 1
N1.C0.D0.R0: ENABLED: ckeMask = 00000001
N5.C0.D0.R3: Enable = 0
N7.C0.D0.R1: ENABLED: ckeMask = 00000003
N1.C0.D0.R1: Enable = 1
N5.C0.D1: Enable = 0
N7.C0.D0.R2: Enable = 0
N1.C0.D0.R1: ENABLED: ckeMask = 00000003
N5.C0.D2: Enable = 0
N7.C0.D0.R3: Enable = 0
N1.C0.D0.R2: Enable = 0
N5.C1: Enable = 1
N7.C0.D1: Enable = 0
N1.C0.D0.R3: Enable = 0
N5.C1.D0: Enable = 1
N7.C0.D2: Enable = 0
N1.C0.D1: Enable = 0
N5.C1.D0.R0: Enable = 1
N7.C1: Enable = 1
N1.C0.D2: Enable = 0
N5.C1.D0.R0: ENABLED: ckeMask = 00000001
N7.C1.D0: Enable = 1
N1.C1: Enable = 1
N5.C1.D0.R1: Enable = 1
N7.C1.D0.R0: Enable = 1
N1.C1.D0: Enable = 1
N5.C1.D0.R1: ENABLED: ckeMask = 00000003
N7.C1.D0.R0: ENABLED: ckeMask = 00000001
N1.C1.D0.R0: Enable = 1
N5.C1.D0.R2: Enable = 0
N7.C1.D0.R1: Enable = 1
N1.C1.D0.R0: ENABLED: ckeMask = 00000001
N5.C1.D0.R3: Enable = 0
N7.C1.D0.R1: ENABLED: ckeMask = 00000003
N1.C1.D0.R1: Enable = 1
N5.C1.D1: Enable = 0
N7.C1.D0.R2: Enable = 0
N1.C1.D0.R1: ENABLED: ckeMask = 00000003
N5.C1.D2: Enable = 0
N7.C1.D0.R3: Enable = 0
N1.C1.D0.R2: Enable = 0
N5.C2: Enable = 1
N7.C1.D1: Enable = 0
N1.C1.D0.R3: Enable = 0
N5.C2.D0: Enable = 1
N7.C1.D2: Enable = 0
N1.C1.D1: Enable = 0
N5.C2.D0.R0: Enable = 1
N7.C2: Enable = 1
N1.C1.D2: Enable = 0
N5.C2.D0.R0: ENABLED: ckeMask = 00000001
N7.C2.D0: Enable = 1
N1.C2: Enable = 1
N5.C2.D0.R1: Enable = 1
N7.C2.D0.R0: Enable = 1
N1.C2.D0: Enable = 1
N5.C2.D0.R1: ENABLED: ckeMask = 00000003
N7.C2.D0.R0: ENABLED: ckeMask = 00000001
N1.C2.D0.R0: Enable = 1
N5.C2.D0.R2: Enable = 0
N7.C2.D0.R1: Enable = 1
N1.C2.D0.R0: ENABLED: ckeMask = 00000001
N5.C2.D0.R3: Enable = 0
N7.C2.D0.R1: ENABLED: ckeMask = 00000003
N1.C2.D0.R1: Enable = 1
N5.C2.D1: Enable = 0
N7.C2.D0.R2: Enable = 0
N1.C2.D0.R1: ENABLED: ckeMask = 00000003
N5.C2.D2: Enable = 0
N7.C2.D0.R3: Enable = 0
N1.C2.D0.R2: Enable = 0
N5.C3: Enable = 1
N7.C2.D1: Enable = 0
N1.C2.D0.R3: Enable = 0
N5.C3.D0: Enable = 1
N7.C2.D2: Enable = 0
N1.C2.D1: Enable = 0
N5.C3.D0.R0: Enable = 1
N7.C3: Enable = 1
N1.C2.D2: Enable = 0
N5.C3.D0.R0: ENABLED: ckeMask = 00000001
N7.C3.D0: Enable = 1
N1.C3: Enable = 1
N5.C3.D0.R1: Enable = 1
N7.C3.D0.R0: Enable = 1
N1.C3.D0: Enable = 1
N5.C3.D0.R1: ENABLED: ckeMask = 00000003
N7.C3.D0.R0: ENABLED: ckeMask = 00000001
N1.C3.D0.R0: Enable = 1
N5.C3.D0.R2: Enable = 0
N7.C3.D0.R1: Enable = 1
N1.C3.D0.R0: ENABLED: ckeMask = 00000001
N5.C3.D0.R3: Enable = 0
N7.C3.D0.R1: ENABLED: ckeMask = 00000003
N1.C3.D0.R1: Enable = 1
N5.C3.D1: Enable = 0
N7.C3.D0.R2: Enable = 0
N1.C3.D0.R1: ENABLED: ckeMask = 00000003
N5.C3.D2: Enable = 0
N7.C3.D0.R3: Enable = 0
N1.C3.D0.R2: Enable = 0
N5: Memory Timings:
N7.C3.D1: Enable = 0
N1.C3.D0.R3: Enable = 0
N5.C0: nCL = 9
N7.C3.D2: Enable = 0
N1.C3.D1: Enable = 0
N5.C0: nCWL = 7
N7: Memory Timings:
N1.C3.D2: Enable = 0
N5.C0: nRP = 9
N7.C0: nCL = 9
N1: Memory Timings:
N5.C0: nRCD = 9
N7.C0: nCWL = 7
N1.C0: nCL = 9
N5.C0: nRRD = 4
N7.C0: nRP = 9
N1.C0: nCWL = 7
N5.C0: nWTR = 5
N7.C0: nRCD = 9
N1.C0: nRP = 9
N5.C0: nRAS = 24
N7.C0: nRRD = 4
N1.C0: nRCD = 9
N5.C0: nRTP = 5
N7.C0: nWTR = 5
N1.C0: nRRD = 4
N5.C0: nWR = 10
N7.C0: nRAS = 24
N1.C0: nWTR = 5
N5.C0: nFAW = 20
N7.C0: nRTP = 5
N1.C0: nRAS = 24
N5.C0: nRC = 33
N7.C0: nWR = 10
N1.C0: nRTP = 5
N5.C0: nRFC = 174
N7.C0: nFAW = 20
N1.C0: nWR = 10
N5.C0: casSup = 0xFC
N7.C0: nRC = 33
N1.C0: nFAW = 20
N5.C0: trrMode = 0
N7.C0: nRFC = 174
N1.C0: nRC = 33
N5.C0: twoXRefresh = 0
N7.C0: casSup = 0xFC
N1.C0: nRFC = 174
N5.C0: t_stagger_ref = 0x86
N7.C0: trrMode = 0
N1.C0: casSup = 0xFC
N5.C0: tcsrftp.Bits.t_xsdll = 512
N7.C0: twoXRefresh = 0
N1.C0: trrMode = 0
N5.C0: Common CL = 9
Common CWL = 7
N7.C0: t_stagger_ref = 0x86
N1.C0: twoXRefresh = 0
N5: Memory Timings:
N7.C0: tcsrftp.Bits.t_xsdll = 512
N1.C0: t_stagger_ref = 0x86
N5.C1: nCL = 9
N7.C0: Common CL = 9
Common CWL = 7
N1.C0: tcsrftp.Bits.t_xsdll = 512
N5.C1: nCWL = 7
N7: Memory Timings:
N1.C0: Common CL = 9
Common CWL = 7
N5.C1: nRP = 9
N7.C1: nCL = 9
N1: Memory Timings:
N5.C1: nRCD = 9
N7.C1: nCWL = 7
N1.C1: nCL = 9
N5.C1: nRRD = 4
N7.C1: nRP = 9
N1.C1: nCWL = 7
N5.C1: nWTR = 5
N7.C1: nRCD = 9
N1.C1: nRP = 9
N5.C1: nRAS = 24
N7.C1: nRRD = 4
N1.C1: nRCD = 9
N5.C1: nRTP = 5
N7.C1: nWTR = 5
N1.C1: nRRD = 4
N5.C1: nWR = 10
N7.C1: nRAS = 24
N1.C1: nWTR = 5
N5.C1: nFAW = 20
N7.C1: nRTP = 5
N1.C1: nRAS = 24
N5.C1: nRC = 33
N7.C1: nWR = 10
N1.C1: nRTP = 5
N5.C1: nRFC = 174
N7.C1: nFAW = 20
N1.C1: nWR = 10
N5.C1: casSup = 0xFC
N7.C1: nRC = 33
N1.C1: nFAW = 20
N5.C1: trrMode = 0
N7.C1: nRFC = 174
N1.C1: nRC = 33
N5.C1: twoXRefresh = 0
N7.C1: casSup = 0xFC
N1.C1: nRFC = 174
N5.C1: t_stagger_ref = 0x86
N7.C1: trrMode = 0
N1.C1: casSup = 0xFC
N5.C1: tcsrftp.Bits.t_xsdll = 512
N7.C1: twoXRefresh = 0
N1.C1: trrMode = 0
N5.C1: Common CL = 9
Common CWL = 7
N7.C1: t_stagger_ref = 0x86
N1.C1: twoXRefresh = 0
N5: Memory Timings:
N7.C1: tcsrftp.Bits.t_xsdll = 512
N1.C1: t_stagger_ref = 0x86
N5.C2: nCL = 9
N7.C1: Common CL = 9
Common CWL = 7
N1.C1: tcsrftp.Bits.t_xsdll = 512
N5.C2: nCWL = 7
N7: Memory Timings:
N1.C1: Common CL = 9
Common CWL = 7
N5.C2: nRP = 9
N7.C2: nCL = 9
N1: Memory Timings:
N5.C2: nRCD = 9
N7.C2: nCWL = 7
N1.C2: nCL = 9
N5.C2: nRRD = 4
N7.C2: nRP = 9
N1.C2: nCWL = 7
N5.C2: nWTR = 5
N7.C2: nRCD = 9
N1.C2: nRP = 9
N5.C2: nRAS = 24
N7.C2: nRRD = 4
N1.C2: nRCD = 9
N5.C2: nRTP = 5
N7.C2: nWTR = 5
N1.C2: nRRD = 4
N5.C2: nWR = 10
N7.C2: nRAS = 24
N1.C2: nWTR = 5
N5.C2: nFAW = 20
N7.C2: nRTP = 5
N1.C2: nRAS = 24
N5.C2: nRC = 33
N7.C2: nWR = 10
N1.C2: nRTP = 5
N5.C2: nRFC = 174
N7.C2: nFAW = 20
N1.C2: nWR = 10
N5.C2: casSup = 0xFC
N7.C2: nRC = 33
N1.C2: nFAW = 20
N5.C2: trrMode = 0
N7.C2: nRFC = 174
N1.C2: nRC = 33
N5.C2: twoXRefresh = 0
N7.C2: casSup = 0xFC
N1.C2: nRFC = 174
N5.C2: t_stagger_ref = 0x86
N7.C2: trrMode = 0
N1.C2: casSup = 0xFC
N5.C2: tcsrftp.Bits.t_xsdll = 512
N7.C2: twoXRefresh = 0
N1.C2: trrMode = 0
N5.C2: Common CL = 9
Common CWL = 7
N7.C2: t_stagger_ref = 0x86
N1.C2: twoXRefresh = 0
N5: Memory Timings:
N7.C2: tcsrftp.Bits.t_xsdll = 512
N1.C2: t_stagger_ref = 0x86
N5.C3: nCL = 9
N7.C2: Common CL = 9
Common CWL = 7
N1.C2: tcsrftp.Bits.t_xsdll = 512
N5.C3: nCWL = 7
N7: Memory Timings:
N1.C2: Common CL = 9
Common CWL = 7
N5.C3: nRP = 9
N7.C3: nCL = 9
N1: Memory Timings:
N5.C3: nRCD = 9
N7.C3: nCWL = 7
N1.C3: nCL = 9
N3: Start VMSE training Sequence
N5.C3: nRRD = 4
N7.C3: nRP = 9
N1.C3: nCWL = 7
N3: ddrCh0.enabled = 1
N5.C3: nWTR = 5
N7.C3: nRCD = 9
N1.C3: nRP = 9
N3: ddrCh1.enabled = 1
N5.C3: nRAS = 24
N7.C3: nRRD = 4
N1.C3: nRCD = 9
N3: ddrCh2.enabled = 1
N5.C3: nRTP = 5
N7.C3: nWTR = 5
N1.C3: nRRD = 4
N3: ddrCh3.enabled = 1
N5.C3: nWR = 10
N7.C3: nRAS = 24
N1.C3: nWTR = 5
N3: VMSE0.enabled = 1
N5.C3: nFAW = 20
N7.C3: nRTP = 5
N1.C3: nRAS = 24
N3: VMSE1.enabled = 1
N5.C3: nRC = 33
N7.C3: nWR = 10
N1.C3: nRTP = 5
N3: CpgcVmseTraining for VMSE0
N5.C3: nRFC = 174
N7.C3: nFAW = 20
N1.C3: nWR = 10
N3: Initialize VMSE Channels
N5.C3: casSup = 0xFC
N7.C3: nRC = 33
N1.C3: nFAW = 20

START - VMSE Detect DC
N5.C3: trrMode = 0
N7.C3: nRFC = 174
N1.C3: nRC = 33
N3: HsxVmseCompInit
N5.C3: twoXRefresh = 0
N7.C3: casSup = 0xFC
N1.C3: nRFC = 174
N5.C3: t_stagger_ref = 0x86
N7.C3: trrMode = 0
N1.C3: casSup = 0xFC
N3.C0: Skip DC Detect check for CMD results
N5.C3: tcsrftp.Bits.t_xsdll = 512
N7.C3: twoXRefresh = 0
N1.C3: trrMode = 0
N5.C3: Common CL = 9
Common CWL = 7
N7.C3: t_stagger_ref = 0x86
N1.C3: twoXRefresh = 0
N3.C0: Skip DC Detect check for CMD results
N5: PreVmseTraining
N7.C3: tcsrftp.Bits.t_xsdll = 512
N1.C3: t_stagger_ref = 0x86
N3: HsxVmseCompInit
N5.C0: InitHostVmseCfg
N7.C3: Common CL = 9
Common CWL = 7
N1.C3: tcsrftp.Bits.t_xsdll = 512
N3.C0: VmseDetectDC: SUCCESS
N5.C0: vmse_wr_turnaround = 0x7 
N7: PreVmseTraining
N1.C3: Common CL = 9
Common CWL = 7
N3.C0: VmseDetectClock
N5.C2: InitHostVmseCfg
N7.C0: InitHostVmseCfg
Checkpoint Code: Socket 0, 0xB6, 0x00, 0x0000
N5.C2: vmse_wr_turnaround = 0x7 
N7.C0: vmse_wr_turnaround = 0x7 
N1: PreVmseTraining
N5: HsxInitDdrioInterface
N7.C2: InitHostVmseCfg
Checkpoint Code: Socket 0, 0xB6, 0x01, 0x0000
N5.C0: rxVref = 0x5F
N7.C2: vmse_wr_turnaround = 0x7 
N1.C0: InitHostVmseCfg
N5.C1: rxVref = 0x5F
N7: HsxInitDdrioInterface
N1.C0: vmse_wr_turnaround = 0x7 
N5: HsxVmseCompInit
N7.C0: rxVref = 0x5F
Checkpoint Code: Socket 0, 0xB6, 0x01, 0x0000
N5: VmseCrossoverCalib
N5: Enable xovercal
N5: vmse_modes =          1,  0
N5.C0: piDelay CMDn  CMDs  CTL  CKE  CLK   0  1  2  3  4  5  6  7  8  9 10 11 12 13 14 15 16 17
          0       0     0    0    0    0   1  1  1  1  0  0  1  1  0  1  1  1  1  0  0  1  1  0 
          1       0     0    0    0    0   1  1  1  1  0  1  1  1  0  1  1  1  1  0  1  1  1  0 
          2       0     0    0    0    0   1  1  1  1  0  1  1  1  0  1  1  1  1  0  1  1  1  0 
          3       0     0    1    0    0   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
          4       0     0    1    0    0   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
          5       0     0    1    1    0   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
          6       0     0    1    1    0   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
          7       0     0    1    1    0   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
          8       0     0    1    1    0   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
          9       0     0    1    1    0   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         10       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         11       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         12       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         13       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         14       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         15       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         16       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         17       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         18       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         19       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         20       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         21       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         22       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         23       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         24       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         25       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         26       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         27       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         28       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         29       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         30       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         31       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         32       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         33       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         34       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         35       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         36       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         37       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         38       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         39       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         40       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         41       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         42       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         43       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         44       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         45       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         46       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         47       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         48       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         49       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         50       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         51       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         52       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         53       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         54       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         55       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         56       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         57       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         58       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         59       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         60       0     0    1    1    1   0  1  1  1  1  1  1  1  1  0  1  1  1  1  1  1  1  1 
         61       0     0    1    1    1   X  1  1  1  1  1  1  1  1  X  1  1  1  1  1  1  1  1 
         62       0     0    1    1    1   X  0  1  1  1  1  1  1  1  X  0  1  1  1  1  1  1  1 
         63       0     0    1    1    1   X  X  1  1  1  1  1  1  1  X  X  1  1  1  1  1  1  1 
N5.C0: setting ddrcrinvertpiclk
          0       0     0    1    1    1   X  X  0  1  1  1  0  0  1  X  X  0  1  1  1  0  0  1 
          1       0     0    1    1    1   X  X  0  0  1  1  0  0  1  X  X  0  0  1  1  0  0  1 
          2       0     0    1    1    1   X  X  0  X  1  1  0  0  1  X  X  0  X  1  1  0  0  1 
          3       0     0    1    1    1   X  X  0  X  1  0  0  0  1  X  X  0  X  1  0  0  0  1 
          4       0     0    0    1    1   X  X  0  X  0  X  0  0  0  X  X  0  X  0  X  0  0  0 
          5       0     0    X    0    1   X  X  0  X  X  X  0  0  X  X  X  0  X  X  X  0  0  X 
          6       0     0    X    X    1   X  X  0  X  X  X  0  0  X  X  X  0  X  X  X  0  0  X 
          7       0     0    X    X    1   X  X  0  X  X  X  0  0  X  X  X  0  X  X  X  0  0  X 
          8       0     0    X    X    1   X  X  0  X  X  X  0  0  X  X  X  0  X  X  X  0  0  X 
          9       0     0    X    X    1   X  X  0  X  X  X  0  0  X  X  X  0  X  X  X  0  0  X 
         10       0     0    X    X    1   X  X  0  X  X  X  0  0  X  X  X  0  X  X  X  0  0  X 
         11       0     0    X    X    0   X  X  0  X  X  X  0  0  X  X  X  0  X  X  X  0  0  X 
         12       0     0    X    X    X   X  X  0  X  X  X  0  0  X  X  X  0  X  X  X  0  0  X 
         13       0     0    X    X    X   X  X  0  X  X  X  0  0  X  X  X  0  X  X  X  0  0  X 
         14       0     0    X    X    X   X  X  0  X  X  X  0  0  X  X  X  0  X  X  X  0  0  X 
         15       0     0    X    X    X   X  X  0  X  X  X  0  0  X  X  X  0  X  X  X  0  0  X 
         16       0     0    X    X    X   X  X  0  X  X  X  0  0  X  X  X  0  X  X  X  0  0  X 
         17       0     0    X    X    X   X  X  0  X  X  X  0  0  X  X  X  0  X  X  X  0  0  X 
         18       0     0    X    X    X   X  X  0  X  X  X  0  0  X  X  X  0  X  X  X  0  0  X 
         19       0     0    X    X    X   X  X  0  X  X  X  0  0  X  X  X  0  X  X  X  0  0  X 
         20       0     0    X    X    X   X  X  0  X  X  X  0  0  X  X  X  0  X  X  X  0  0  X 
         21       0     0    X    X    X   X  X  0  X  X  X  0  0  X  X  X  0  X  X  X  0  0  X 
         22       0     0    X    X    X   X  X  0  X  X  X  0  0  X  X  X  0  X  X  X  0  0  X 
         23       0     0    X    X    X   X  X  0  X  X  X  0  0  X  X  X  0  X  X  X  0  0  X 
         24       0     0    X    X    X   X  X  0  X  X  X  0  0  X  X  X  0  X  X  X  0  0  X 
         25       0     0    X    X    X   X  X  0  X  X  X  0  0  X  X  X  0  X  X  X  0  0  X 
         26       0     0    X    X    X   X  X  0  X  X  X  0  0  X  X  X  0  X  X  X  0  0  X 
         27       0     0    X    X    X   X  X  0  X  X  X  0  0  X  X  X  0  X  X  X  0  0  X 
         28       0     0    X    X    X   X  X  0  X  X  X  0  0  X  X  X  0  X  X  X  0  0  X 
         29       0     0    X    X    X   X  X  0  X  X  X  0  0  X  X  X  0  X  X  X  0  0  X 
         30       0     0    X    X    X   X  X  0  X  X  X  0  0  X  X  X  0  X  X  X  0  0  X 
         31       0     0    X    X    X   X  X  0  X  X  X  0  0  X  X  X  0  X  X  X  0  0  X 
         32       0     0    X    X    X   X  X  0  X  X  X  0  0  X  X  X  0  X  X  X  0  0  X 
         33       0     0    X    X    X   X  X  0  X  X  X  0  0  X  X  X  0  X  X  X  0  0  X 
         34       0     0    X    X    X   X  X  0  X  X  X  0  0  X  X  X  0  X  X  X  0  0  X 
         35       0     0    X    X    X   X  X  0  X  X  X  0  0  X  X  X  0  X  X  X  0  0  X 
         36       0     0    X    X    X   X  X  0  X  X  X  0  0  X  X  X  0  X  X  X  0  0  X 
         37       0     0    X    X    X   X  X  0  X  X  X  0  0  X  X  X  0  X  X  X  0  0  X 
         38       0     0    X    X    X   X  X  0  X  X  X  0  0  X  X  X  0  X  X  X  0  0  X 
         39       0     0    X    X    X   X  X  0  X  X  X  0  0  X  X  X  0  X  X  X  0  0  X 
         40       0     0    X    X    X   X  X  0  X  X  X  0  0  X  X  X  0  X  X  X  0  0  X 
         41       0     0    X    X    X   X  X  0  X  X  X  0  0  X  X  X  0  X  X  X  0  0  X 
         42       0     0    X    X    X   X  X  0  X  X  X  0  0  X  X  X  0  X  X  X  0  0  X 
         43       0     0    X    X    X   X  X  0  X  X  X  0  0  X  X  X  0  X  X  X  0  0  X 
         44       0     0    X    X    X   X  X  0  X  X  X  0  0  X  X  X  0  X  X  X  0  0  X 
         45       0     0    X    X    X   X  X  0  X  X  X  0  0  X  X  X  0  X  X  X  0  0  X 
         46       0     0    X    X    X   X  X  0  X  X  X  0  0  X  X  X  0  X  X  X  0  0  X 
         47       0     0    X    X    X   X  X  0  X  X  X  0  0  X  X  X  0  X  X  X  0  0  X 
         48       0     0    X    X    X   X  X  0  X  X  X  0  0  X  X  X  0  X  X  X  0  0  X 
         49       0     0    X    X    X   X  X  0  X  X  X  0  0  X  X  X  0  X  X  X  0  0  X 
         50       0     0    X    X    X   X  X  0  X  X  X  0  0  X  X  X  0  X  X  X  0  0  X 
         51       0     0    X    X    X   X  X  0  X  X  X  0  0  X  X  X  0  X  X  X  0  0  X 
         52       0     0    X    X    X   X  X  0  X  X  X  0  0  X  X  X  0  X  X  X  0  0  X 
         53       0     0    X    X    X   X  X  0  X  X  X  0  0  X  X  X  0  X  X  X  0  0  X 
         54       0     0    X    X    X   X  X  0  X  X  X  0  0  X  X  X  0  X  X  X  0  0  X 
         55       0     0    X    X    X   X  X  0  X  X  X  0  0  X  X  X  0  X  X  X  0  0  X 
         56       0     0    X    X    X   X  X  0  X  X  X  0  0  X  X  X  0  X  X  X  0  0  X 
         57       0     0    X    X    X   X  X  0  X  X  X  0  0  X  X  X  0  X  X  X  0  0  X 
         58       0     0    X    X    X   X  X  0  X  X  X  0  0  X  X  X  0  X  X  X  0  0  X 
         59       0     0    X    X    X   X  X  0  X  X  X  0  0  X  X  X  0  X  X  X  0  0  X 
         60       0     0    X    X    X   X  X  0  X  X  X  0  0  X  X  X  0  X  X  X  0  0  X 
         61       0     0    X    X    X   X  X  0  X  X  X  0  0  X  X  X  0  X  X  X  0  0  X 
         62       0     0    X    X    X   X  X  0  X  X  X  0  0  X  X  X  0  X  X  X  0  0  X 
         63       0     0    X    X    X   X  X  0  X  X  X  0  1  X  X  X  0  X  X  X  0  0  X 
N5.C0: CMD-N xovercal offset = 0
N5.C0: CMD-S xovercal offset = 0
N5.C0: CTL xovercal offset   = 4
N5.C0: CKE xovercal offset   = 5
N5.C0: CLK xovercal offset   = 11
N5.C0.S18: STROBE                     0   1   2   3   4   5   6   7   8   9  10  11  12  13  14  15  16  17
N5.C0.S18: Rec En xovercal offset =  60  62   0   1   4   3   0   0   4  60  62   0   1   4   3   0   0   4 
N5.C0.S18: Tx Dqs xovercal offset =  60  63   0  63  63  63   0   0  63  63  63   0  63  63  63   0   0  63 
N5.C0.S18: Tx Dq xovercal offset  =  60  62   0   1   4   3   0   0   4  60  62   0   1   4   3   0   0   4 
N5.C0:         CMDn  CMDs  CTL  CKE  CLK   0  1  2  3  4  5  6  7  8
N5.C0: offsets:  0     0     4N5: getComplexCkeSetupTime defaultOffset = 98
N5: getComplexCkeSetupTime = 98
    5   11
Ctl Offsets Delta / final ctl offset / final cke offset /  98  /  38  /   7
Cke invertpiclk / Ctl invertpiclk / 0x0  /  0x0
N5: getComplexClkSetupTime defaultOffset = 0
N5: getComplexClkSetupTime = 0
ClkSetupTime = 11
N5: getComplexDqSetupTime defaultOffset = 0
N5: getComplexDqSetupTime = 0
N5.C0.S00: txdqoffset delta = 0, dq invertpiclk = 0
N5: getComplexDqsSetupTime defaultOffset = 40
N5: getComplexDqsSetupTime = 40
N5.C0.S00: txdqsoffset delta = 40
N5: getComplexRcvEnSetupTime defaultOffset = 37
N5: getComplexRcvEnSetupTime = 37
N5.C0.S00: rcvenoffset delta = 37
N5.C0.S00: Final txdqoffset / txdqsoffset / rcvenoffset / 28 /  4 /  1
N5: getComplexDqSetupTime defaultOffset = 0
N5: getComplexDqSetupTime = 0
N5.C0.S01: txdqoffset delta = 0, dq invertpiclk = 0
N5: getComplexDqsSetupTime defaultOffset = 40
N5: getComplexDqsSetupTime = 40
N5.C0.S01: txdqsoffset delta = 40
N5: getComplexRcvEnSetupTime defaultOffset = 37
N5: getComplexRcvEnSetupTime = 37
N5.C0.S01: rcvenoffset delta = 37
N5.C0.S01: Final txdqoffset / txdqsoffset / rcvenoffset / 62 / 38 / 35
N5: getComplexDqSetupTime defaultOffset = 0
N5: getComplexDqSetupTime = 0
N5.C0.S02: txdqoffset delta = 0, dq invertpiclk = 3
N5: getComplexDqsSetupTime defaultOffset = 40
N5: getComplexDqsSetupTime = 40
N5.C0.S02: txdqsoffset delta = 40
N5: getComplexRcvEnSetupTime defaultOffset = 37
N5: getComplexRcvEnSetupTime = 37
N5.C0.S02: rcvenoffset delta = 37
N5.C0.S02: Final txdqoffset / txdqsoffset / rcvenoffset / 32 /  8 /  5
N5: getComplexDqSetupTime defaultOffset = 0
N5: getComplexDqSetupTime = 0
N5.C0.S03: txdqoffset delta = 0, dq invertpiclk = 3
N5: getComplexDqsSetupTime defaultOffset = 40
N5: getComplexDqsSetupTime = 40
N5.C0.S03: txdqsoffset delta = 40
N5: getComplexRcvEnSetupTime defaultOffset = 37
N5: getComplexRcvEnSetupTime = 37
N5.C0.S03: rcvenoffset delta = 37
N5.C0.S03: Final txdqoffset / txdqsoffset / rcvenoffset /  1 / 41 / 38
N5: getComplexDqSetupTime defaultOffset = 0
N5: getComplexDqSetupTime = 0
N5.C0.S04: txdqoffset delta = 0, dq invertpiclk = 3
N5: getComplexDqsSetupTime defaultOffset = 40
N5: getComplexDqsSetupTime = 40
N5.C0.S04: txdqsoffset delta = 40
N5: getComplexRcvEnSetupTime defaultOffset = 37
N5: getComplexRcvEnSetupTime = 37
N5.C0.S04: rcvenoffset delta = 37
N5.C0.S04: Final txdqoffset / txdqsoffset / rcvenoffset / 36 / 12 /  9
N5: getComplexDqSetupTime defaultOffset = 0
N5: getComplexDqSetupTime = 0
N5.C0.S05: txdqoffset delta = 0, dq invertpiclk = 3
N5: getComplexDqsSetupTime defaultOffset = 40
N5: getComplexDqsSetupTime = 40
N5.C0.S05: txdqsoffset delta = 40
N5: getComplexRcvEnSetupTime defaultOffset = 37
N5: getComplexRcvEnSetupTime = 37
N5.C0.S05: rcvenoffset delta = 37
N5.C0.S05: Final txdqoffset / txdqsoffset / rcvenoffset /  3 / 43 / 40
N5: getComplexDqSetupTime defaultOffset = 0
N5: getComplexDqSetupTime = 0
N5.C0.S06: txdqoffset delta = 0, dq invertpiclk = 3
N5: getComplexDqsSetupTime defaultOffset = 40
N5: getComplexDqsSetupTime = 40
N5.C0.S06: txdqsoffset delta = 40
N5: getComplexRcvEnSetupTime defaultOffset = 37
N5: getComplexRcvEnSetupTime = 37
N5.C0.S06: rcvenoffset delta = 37
N5.C0.S06: Final txdqoffset / txdqsoffset / rcvenoffset / 32 /  8 /  5
N5: getComplexDqSetupTime defaultOffset = 0
N5: getComplexDqSetupTime = 0
N5.C0.S07: txdqoffset delta = 0, dq invertpiclk = 3
N5: getComplexDqsSetupTime defaultOffset = 40
N5: getComplexDqsSetupTime = 40
N5.C0.S07: txdqsoffset delta = 40
N5: getComplexRcvEnSetupTime defaultOffset = 37
N5: getComplexRcvEnSetupTime = 37
N5.C0.S07: rcvenoffset delta = 37
N5.C0.S07: Final txdqoffset / txdqsoffset / rcvenoffset /  0 / 40 / 37
N5: getComplexDqSetupTime defaultOffset = 0
N5: getComplexDqSetupTime = 0
N5.C0.S08: txdqoffset delta = 0, dq invertpiclk = 3
N5: getComplexDqsSetupTime defaultOffset = 40
N5: getComplexDqsSetupTime = 40
N5.C0.S08: txdqsoffset delta = 40
N5: getComplexRcvEnSetupTime defaultOffset = 37
N5: getComplexRcvEnSetupTime = 37
N5.C0.S08: rcvenoffset delta = 37
N5.C0.S08: Final txdqoffset / txdqsoffset / rcvenoffset / 36 / 12 /  9

N5: vmse_modes =          1,  0
N5.C1: piDelay CMDn  CMDs  CTL  CKE  CLK   0  1  2  3  4  5  6  7  8  9 10 11 12 13 14 15 16 17
          0       0     0    1    0    0   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
          1       0     0    1    1    0   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
          2       0     0    1    1    0   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
          3       0     0    1    1    0   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
          4       0     0    1    1    0   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
          5       0     0    1    1    0   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
          6       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
          7       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
          8       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
          9       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         10       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         11       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         12       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         13       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         14       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         15       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         16       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         17       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         18       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         19       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         20       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         21       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         22       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         23       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         24       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         25       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         26       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         27       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         28       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         29       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         30       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         31       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         32       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         33       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         34       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         35       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         36       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         37       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         38       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         39       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         40       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         41       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         42       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         43       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         44       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         45       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         46       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         47       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         48       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         49       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         50       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         51       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         52       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         53       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         54       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         55       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         56       0     0    1    1    1   0  1  1  1  1  1  1  1  1  0  1  1  1  1  1  1  1  1 
         57       0     0    1    1    1   X  1  1  1  1  1  1  1  1  X  1  1  1  1  1  1  1  1 
         58       0     0    1    1    1   X  0  1  1  1  1  1  1  1  X  0  1  1  1  1  1  1  1 
         59       0     0    1    1    1   X  X  1  1  1  1  1  1  1  X  X  1  1  1  1  1  1  1 
         60       0     0    1    1    1   X  X  0  1  1  1  1  0  1  X  X  0  1  1  1  1  0  1 
         61       0     0    1    1    1   X  X  X  1  1  1  0  X  1  X  X  X  1  1  1  0  X  1 
         62       0     0    1    1    1   X  X  X  0  1  1  X  X  1  X  X  X  0  1  1  X  X  1 
         63       0     0    1    1    1   X  X  X  X  1  0  X  X  1  X  X  X  X  1  0  X  X  1 
N5.C1: setting ddrcrinvertpiclk
          0       0     0    0    1    1   X  X  X  X  1  X  X  X  0  X  X  X  X  1  X  X  X  0 
          1       0     0    0    1    1   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
          2       0     0    0    1    1   X  X  X  X  X  X  X  X  0  X  X  X  X  X  X  X  X  0 
          3       0     0    0    0    1   X  X  X  X  X  X  X  X  0  X  X  X  X  X  X  X  X  0 
          4       0     0    0    X    1   X  X  X  X  X  X  X  X  0  X  X  X  X  X  X  X  X  0 
          5       0     0    0    X    1   X  X  X  X  X  X  X  X  0  X  X  X  X  X  X  X  X  0 
          6       0     0    0    X    1   X  X  X  X  X  X  X  X  0  X  X  X  X  X  X  X  X  0 
          7       0     0    0    X    0   X  X  X  X  X  X  X  X  0  X  X  X  X  X  X  X  X  0 
          8       0     0    0    X    X   X  X  X  X  X  X  X  X  0  X  X  X  X  X  X  X  X  0 
          9       0     0    0    X    X   X  X  X  X  X  X  X  X  0  X  X  X  X  X  X  X  X  0 
         10       0     0    0    X    X   X  X  X  X  X  X  X  X  0  X  X  X  X  X  X  X  X  0 
         11       0     0    0    X    X   X  X  X  X  X  X  X  X  0  X  X  X  X  X  X  X  X  0 
         12       0     0    0    X    X   X  X  X  X  X  X  X  X  0  X  X  X  X  X  X  X  X  0 
         13       0     0    0    X    X   X  X  X  X  X  X  X  X  0  X  X  X  X  X  X  X  X  0 
         14       0     0    0    X    X   X  X  X  X  X  X  X  X  0  X  X  X  X  X  X  X  X  0 
         15       0     0    0    X    X   X  X  X  X  X  X  X  X  0  X  X  X  X  X  X  X  X  0 
         16       0     0    0    X    X   X  X  X  X  X  X  X  X  0  X  X  X  X  X  X  X  X  0 
         17       0     0    0    X    X   X  X  X  X  X  X  X  X  0  X  X  X  X  X  X  X  X  0 
         18       0     0    0    X    X   X  X  X  X  X  X  X  X  0  X  X  X  X  X  X  X  X  0 
         19       0     0    0    X    X   X  X  X  X  X  X  X  X  0  X  X  X  X  X  X  X  X  0 
         20       0     0    0    X    X   X  X  X  X  X  X  X  X  0  X  X  X  X  X  X  X  X  0 
         21       0     0    0    X    X   X  X  X  X  X  X  X  X  0  X  X  X  X  X  X  X  X  0 
         22       0     0    0    X    X   X  X  X  X  X  X  X  X  0  X  X  X  X  X  X  X  X  0 
         23       0     0    0    X    X   X  X  X  X  X  X  X  X  0  X  X  X  X  X  X  X  X  0 
         24       0     0    0    X    X   X  X  X  X  X  X  X  X  0  X  X  X  X  X  X  X  X  0 
         25       0     0    0    X    X   X  X  X  X  X  X  X  X  0  X  X  X  X  X  X  X  X  0 
         26       0     0    0    X    X   X  X  X  X  X  X  X  X  0  X  X  X  X  X  X  X  X  0 
         27       0     0    0    X    X   X  X  X  X  X  X  X  X  0  X  X  X  X  X  X  X  X  0 
         28       0     0    0    X    X   X  X  X  X  X  X  X  X  0  X  X  X  X  X  X  X  X  0 
         29       0     0    0    X    X   X  X  X  X  X  X  X  X  0  X  X  X  X  X  X  X  X  0 
         30       0     0    0    X    X   X  X  X  X  X  X  X  X  0  X  X  X  X  X  X  X  X  0 
         31       0     0    0    X    X   X  X  X  X  X  X  X  X  0  X  X  X  X  X  X  X  X  0 
         32       0     0    0    X    X   X  X  X  X  X  X  X  X  0  X  X  X  X  X  X  X  X  0 
         33       0     0    0    X    X   X  X  X  X  X  X  X  X  0  X  X  X  X  X  X  X  X  0 
         34       0     0    0    X    X   X  X  X  X  X  X  X  X  0  X  X  X  X  X  X  X  X  0 
         35       0     0    0    X    X   X  X  X  X  X  X  X  X  0  X  X  X  X  X  X  X  X  0 
         36       0     0    0    X    X   X  X  X  X  X  X  X  X  0  X  X  X  X  X  X  X  X  0 
         37       0     0    0    X    X   X  X  X  X  X  X  X  X  0  X  X  X  X  X  X  X  X  0 
         38       0     0    0    X    X   X  X  X  X  X  X  X  X  0  X  X  X  X  X  X  X  X  0 
         39       0     0    0    X    X   X  X  X  X  X  X  X  X  0  X  X  X  X  X  X  X  X  0 
         40       0     0    0    X    X   X  X  X  X  X  X  X  X  0  X  X  X  X  X  X  X  X  0 
         41       0     0    0    X    X   X  X  X  X  X  X  X  X  0  X  X  X  X  X  X  X  X  0 
         42       0     0    0    X    X   X  X  X  X  X  X  X  X  0  X  X  X  X  X  X  X  X  0 
         43       0     0    0    X    X   X  X  X  X  X  X  X  X  0  X  X  X  X  X  X  X  X  0 
         44       0     0    0    X    X   X  X  X  X  X  X  X  X  0  X  X  X  X  X  X  X  X  0 
         45       0     0    0    X    X   X  X  X  X  X  X  X  X  0  X  X  X  X  X  X  X  X  0 
         46       0     0    0    X    X   X  X  X  X  X  X  X  X  0  X  X  X  X  X  X  X  X  0 
         47       0     0    0    X    X   X  X  X  X  X  X  X  X  0  X  X  X  X  X  X  X  X  0 
         48       0     0    0    X    X   X  X  X  X  X  X  X  X  0  X  X  X  X  X  X  X  X  0 
         49       0     0    0    X    X   X  X  X  X  X  X  X  X  0  X  X  X  X  X  X  X  X  0 
         50       0     0    0    X    X   X  X  X  X  X  X  X  X  0  X  X  X  X  X  X  X  X  0 
         51       0     0    0    X    X   X  X  X  X  X  X  X  X  0  X  X  X  X  X  X  X  X  0 
         52       0     0    0    X    X   X  X  X  X  X  X  X  X  0  X  X  X  X  X  X  X  X  0 
         53       0     0    0    X    X   X  X  X  X  X  X  X  X  0  X  X  X  X  X  X  X  X  0 
         54       0     0    0    X    X   X  X  X  X  X  X  X  X  0  X  X  X  X  X  X  X  X  0 
         55       0     0    0    X    X   X  X  X  X  X  X  X  X  0  X  X  X  X  X  X  X  X  0 
         56       0     0    0    X    X   X  X  X  X  X  X  X  X  0  X  X  X  X  X  X  X  X  0 
         57       0     0    0    X    X   X  X  X  X  X  X  X  X  0  X  X  X  X  X  X  X  X  0 
         58       0     0    0    X    X   X  X  X  X  X  X  X  X  0  X  X  X  X  X  X  X  X  0 
         59       0     0    0    X    X   X  X  X  X  X  X  X  X  0  X  X  X  X  X  X  X  X  0 
         60       0     0    0    X    X   X  X  X  X  X  X  X  X  0  X  X  X  X  X  X  X  X  0 
         61       0     0    0    X    X   X  X  X  X  X  X  X  X  0  X  X  X  X  X  X  X  X  0 
         62       0     0    0    X    X   X  X  X  X  X  X  X  X  0  X  X  X  X  X  X  X  X  0 
         63       0     0    0    X    X   X  X  X  X  X  X  X  X  0  X  X  X  X  X  X  X  X  0 
N5.C1: CMD-N xovercal offset = 0
N5.C1: CMD-S xovercal offset = 0
N5.C1: CTL xovercal offset   = 0
N5.C1: CKE xovercal offset   = 3
N5.C1: CLK xovercal offset   = 7
N5.C1.S18: STROBE                     0   1   2   3   4   5   6   7   8   9  10  11  12  13  14  15  16  17
N5.C1.S18: Rec En xovercal offset =  56  58  60  62   1  63  61  60   0  56  58  60  62   1  63  61  60   0 
N5.C1.S18: Tx Dqs xovercal offset =  56  63  63  63  63  63  63  63   0  63  63  63  63  63  63  63  63   0 
N5.C1.S18: Tx Dq xovercal offset  =  56  58  60  62   1  63  61  60   0  56  58  60  62   1  63  61  60   0 
N5.C1:         CMDn  CMDs  CTL  CKE  CLK   0  1  2  3  4  5  6  7  8
N5.C1: offsets:  0     0     0N5: getComplexCkeSetupTime defaultOffset = 98
N5: getComplexCkeSetupTime = 98
    3    7
Ctl Offsets Delta / final ctl offset / final cke offset /  98  /   2  /  37
Cke invertpiclk / Ctl invertpiclk / 0x0  /  0x0
N5: getComplexClkSetupTime defaultOffset = 0
N5: getComplexClkSetupTime = 0
ClkSetupTime = 39
N5: getComplexDqSetupTime defaultOffset = 0
N5: getComplexDqSetupTime = 0
N5.C1.S00: txdqoffset delta = 0, dq invertpiclk = 0
N5: getComplexDqsSetupTime defaultOffset = 40
N5: getComplexDqsSetupTime = 40
N5.C1.S00: txdqsoffset delta = 40
N5: getComplexRcvEnSetupTime defaultOffset = 37
N5: getComplexRcvEnSetupTime = 37
N5.C1.S00: rcvenoffset delta = 37
N5.C1.S00: Final txdqoffset / txdqsoffset / rcvenoffset / 56 / 32 / 29
N5: getComplexDqSetupTime defaultOffset = 0
N5: getComplexDqSetupTime = 0
N5.C1.S01: txdqoffset delta = 0, dq invertpiclk = 0
N5: getComplexDqsSetupTime defaultOffset = 40
N5: getComplexDqsSetupTime = 40
N5.C1.S01: txdqsoffset delta = 40
N5: getComplexRcvEnSetupTime defaultOffset = 37
N5: getComplexRcvEnSetupTime = 37
N5.C1.S01: rcvenoffset delta = 37
N5.C1.S01: Final txdqoffset / txdqsoffset / rcvenoffset / 26 /  2 / 63
N5: getComplexDqSetupTime defaultOffset = 0
N5: getComplexDqSetupTime = 0
N5.C1.S02: txdqoffset delta = 0, dq invertpiclk = 0
N5: getComplexDqsSetupTime defaultOffset = 40
N5: getComplexDqsSetupTime = 40
N5.C1.S02: txdqsoffset delta = 40
N5: getComplexRcvEnSetupTime defaultOffset = 37
N5: getComplexRcvEnSetupTime = 37
N5.C1.S02: rcvenoffset delta = 37
N5.C1.S02: Final txdqoffset / txdqsoffset / rcvenoffset / 60 / 36 / 33
N5: getComplexDqSetupTime defaultOffset = 0
N5: getComplexDqSetupTime = 0
N5.C1.S03: txdqoffset delta = 0, dq invertpiclk = 0
N5: getComplexDqsSetupTime defaultOffset = 40
N5: getComplexDqsSetupTime = 40
N5.C1.S03: txdqsoffset delta = 40
N5: getComplexRcvEnSetupTime defaultOffset = 37
N5: getComplexRcvEnSetupTime = 37
N5.C1.S03: rcvenoffset delta = 37
N5.C1.S03: Final txdqoffset / txdqsoffset / rcvenoffset / 30 /  6 /  3
N5: getComplexDqSetupTime defaultOffset = 0
N5: getComplexDqSetupTime = 0
N5.C1.S04: txdqoffset delta = 0, dq invertpiclk = 3
N5: getComplexDqsSetupTime defaultOffset = 40
N5: getComplexDqsSetupTime = 40
N5.C1.S04: txdqsoffset delta = 40
N5: getComplexRcvEnSetupTime defaultOffset = 37
N5: getComplexRcvEnSetupTime = 37
N5.C1.S04: rcvenoffset delta = 37
N5.C1.S04: Final txdqoffset / txdqsoffset / rcvenoffset /  1 / 41 / 38
N5: getComplexDqSetupTime defaultOffset = 0
N5: getComplexDqSetupTime = 0
N5.C1.S05: txdqoffset delta = 0, dq invertpiclk = 0
N5: getComplexDqsSetupTime defaultOffset = 40
N5: getComplexDqsSetupTime = 40
N5.C1.S05: txdqsoffset delta = 40
N5: getComplexRcvEnSetupTime defaultOffset = 37
N5: getComplexRcvEnSetupTime = 37
N5.C1.S05: rcvenoffset delta = 37
N5.C1.S05: Final txdqoffset / txdqsoffset / rcvenoffset / 31 /  7 /  4
N5: getComplexDqSetupTime defaultOffset = 0
N5: getComplexDqSetupTime = 0
N5.C1.S06: txdqoffset delta = 0, dq invertpiclk = 0
N5: getComplexDqsSetupTime defaultOffset = 40
N5: getComplexDqsSetupTime = 40
N5.C1.S06: txdqsoffset delta = 40
N5: getComplexRcvEnSetupTime defaultOffset = 37
N5: getComplexRcvEnSetupTime = 37
N5.C1.S06: rcvenoffset delta = 37
N5.C1.S06: Final txdqoffset / txdqsoffset / rcvenoffset / 61 / 37 / 34
N5: getComplexDqSetupTime defaultOffset = 0
N5: getComplexDqSetupTime = 0
N5.C1.S07: txdqoffset delta = 0, dq invertpiclk = 0
N5: getComplexDqsSetupTime defaultOffset = 40
N5: getComplexDqsSetupTime = 40
N5.C1.S07: txdqsoffset delta = 40
N5: getComplexRcvEnSetupTime defaultOffset = 37
N5: getComplexRcvEnSetupTime = 37
N5.C1.S07: rcvenoffset delta = 37
N5.C1.S07: Final txdqoffset / txdqsoffset / rcvenoffset / 28 /  4 /  1
N5: getComplexDqSetupTime defaultOffset = 0
N5: getComplexDqSetupTime = 0
N5.C1.S08: txdqoffset delta = 0, dq invertpiclk = 3
N5: getComplexDqsSetupTime defaultOffset = 40
N5: getComplexDqsSetupTime = 40
N5.C1.S08: txdqsoffset delta = 40
N5: getComplexRcvEnSetupTime defaultOffset = 37
N5: getComplexRcvEnSetupTime = 37
N5.C1.S08: rcvenoffset delta = 37
N5.C1.S08: Final txdqoffset / txdqsoffset / rcvenoffset /  0 / 40 / 37

N7.C1: rxVref = 0x5F
N1.C2: InitHostVmseCfg
N3.C0: VmseDetectClock: SUCCESS
N7: HsxVmseCompInit
N1.C2: vmse_wr_turnaround = 0x7 

END - VMSE Detect DC                   Time         4944 ms
N7: VmseCrossoverCalib
N7: Enable xovercal
N7: vmse_modes =          1,  0
N7.C0: piDelay CMDn  CMDs  CTL  CKE  CLK   0  1  2  3  4  5  6  7  8  9 10 11 12 13 14 15 16 17
          0       0     0    0    0    0   1  1  1  1  0  1  1  1  1  1  1  1  1  0  1  1  1  1 
          1       0     0    1    0    0   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
          2       0     0    1    0    0   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
          3       0     0    1    1    0   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
          4       0     0    1    1    0   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
          5       0     0    1    1    0   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
          6       0     0    1    1    0   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
          7       0     0    1    1    0   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
          8       0     0    1    1    0   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
          9       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         10       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         11       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         12       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         13       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         14       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         15       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         16       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         17       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         18       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         19       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         20       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         21       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         22       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         23       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         24       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         25       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         26       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         27       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         28       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         29       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         30       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         31       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         32       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         33       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         34       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         35       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         36       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         37       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         38       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         39       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         40       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         41       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         42       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         43       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         44       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         45       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         46       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         47       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         48       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         49       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         50       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         51       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         52       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         53       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         54       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         55       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         56       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         57       0     0    1    1    1   0  1  1  1  1  1  1  1  1  0  1  1  1  1  1  1  1  1 
         58       0     0    1    1    1   X  1  1  1  1  1  1  1  1  X  1  1  1  1  1  1  1  1 
         59       0     0    1    1    1   X  1  1  1  1  1  1  1  1  X  1  1  1  1  1  1  1  1 
         60       0     0    1    1    1   X  0  1  1  1  1  1  1  1  X  0  1  1  1  1  1  1  1 
         61       0     0    1    1    1   X  X  1  1  1  1  1  1  1  X  X  1  1  1  1  1  1  1 
         62       0     0    1    1    1   X  X  0  1  1  1  0  0  1  X  X  0  1  1  1  0  0  1 
         63       0     0    1    1    1   X  X  X  1  1  1  X  X  1  X  X  X  1  1  1  X  X  1 
N7.C0: setting ddrcrinvertpiclk
          0       0     0    1    1    1   X  X  X  0  1  0  X  X  1  X  X  X  0  1  0  X  X  1 
          1       0     0    1    1    1   X  X  X  0  1  0  X  X  0  X  X  X  0  1  0  X  X  0 
          2       0     0    1    1    1   X  X  X  0  0  0  X  X  X  X  X  X  0  0  0  X  X  X 
          3       0     0    0    1    1   X  X  X  0  X  0  X  X  X  X  X  X  0  X  0  X  X  X 
          4       0     0    X    0    1   X  X  X  0  X  0  X  X  X  X  X  X  0  X  0  X  X  X 
          5       0     0    X    X    1   X  X  X  0  X  0  X  X  X  X  X  X  0  X  0  X  X  X 
          6       0     0    X    X    1   X  X  X  0  X  0  X  X  X  X  X  X  0  X  0  X  X  X 
          7       0     0    X    X    1   X  X  X  0  X  0  X  X  X  X  X  X  0  X  0  X  X  X 
          8       0     0    X    X    1   X  X  X  0  X  0  X  X  X  X  X  X  0  X  0  X  X  X 
          9       0     0    X    X    1   X  X  X  0  X  0  X  X  X  X  X  X  0  X  0  X  X  X 
         10       0     0    X    X    0   X  X  X  0  X  0  X  X  X  X  X  X  0  X  0  X  X  X 
         11       0     0    X    X    X   X  X  X  0  X  0  X  X  X  X  X  X  0  X  0  X  X  X 
         12       0     0    X    X    X   X  X  X  0  X  0  X  X  X  X  X  X  0  X  0  X  X  X 
         13       0     0    X    X    X   X  X  X  0  X  0  X  X  X  X  X  X  0  X  0  X  X  X 
         14       0     0    X    X    X   X  X  X  0  X  0  X  X  X  X  X  X  0  X  0  X  X  X 
         15       0     0    X    X    X   X  X  X  0  X  0  X  X  X  X  X  X  0  X  0  X  X  X 
         16       0     0    X    X    X   X  X  X  0  X  0  X  X  X  X  X  X  0  X  0  X  X  X 
         17       0     0    X    X    X   X  X  X  0  X  0  X  X  X  X  X  X  0  X  0  X  X  X 
         18       0     0    X    X    X   X  X  X  0  X  0  X  X  X  X  X  X  0  X  0  X  X  X 
         19       0     0    X    X    X   X  X  X  0  X  0  X  X  X  X  X  X  0  X  0  X  X  X 
         20       0     0    X    X    X   X  X  X  0  X  0  X  X  X  X  X  X  0  X  0  X  X  X 
         21       0     0    X    X    X   X  X  X  0  X  0  X  X  X  X  X  X  0  X  0  X  X  X 
         22       0     0    X    X    X   X  X  X  0  X  0  X  X  X  X  X  X  0  X  0  X  X  X 
         23       0     0    X    X    X   X  X  X  0  X  0  X  X  X  X  X  X  0  X  0  X  X  X 
         24       0     0    X    X    X   X  X  X  0  X  0  X  X  X  X  X  X  0  X  0  X  X  X 
         25       0     0    X    X    X   X  X  X  0  X  0  X  X  X  X  X  X  0  X  0  X  X  X 
         26       0     0    X    X    X   X  X  X  0  X  0  X  X  X  X  X  X  0  X  0  X  X  X 
         27       0     0    X    X    X   X  X  X  0  X  0  X  X  X  X  X  X  0  X  0  X  X  X 
         28       0     0    X    X    X   X  X  X  0  X  0  X  X  X  X  X  X  0  X  0  X  X  X 
         29       0     0    X    X    X   X  X  X  0  X  0  X  X  X  X  X  X  0  X  0  X  X  X 
         30       0     0    X    X    X   X  X  X  0  X  0  X  X  X  X  X  X  0  X  0  X  X  X 
         31       0     0    X    X    X   X  X  X  0  X  0  X  X  X  X  X  X  0  X  0  X  X  X 
         32       0     0    X    X    X   X  X  X  0  X  0  X  X  X  X  X  X  0  X  0  X  X  X 
         33       0     0    X    X    X   X  X  X  0  X  0  X  X  X  X  X  X  0  X  0  X  X  X 
         34       0     0    X    X    X   X  X  X  0  X  0  X  X  X  X  X  X  0  X  0  X  X  X 
         35       0     0    X    X    X   X  X  X  0  X  0  X  X  X  X  X  X  0  X  0  X  X  X 
         36       0     0    X    X    X   X  X  X  0  X  0  X  X  X  X  X  X  0  X  0  X  X  X 
         37       0     0    X    X    X   X  X  X  0  X  0  X  X  X  X  X  X  0  X  0  X  X  X 
         38       0     0    X    X    X   X  X  X  0  X  0  X  X  X  X  X  X  0  X  0  X  X  X 
         39       0     0    X    X    X   X  X  X  0  X  0  X  X  X  X  X  X  0  X  0  X  X  X 
         40       0     0    X    X    X   X  X  X  0  X  0  X  X  X  X  X  X  0  X  0  X  X  X 
         41       0     0    X    X    X   X  X  X  0  X  0  X  X  X  X  X  X  0  X  0  X  X  X 
         42       0     0    X    X    X   X  X  X  0  X  0  X  X  X  X  X  X  0  X  0  X  X  X 
         43       0     0    X    X    X   X  X  X  0  X  0  X  X  X  X  X  X  0  X  0  X  X  X 
         44       0     0    X    X    X   X  X  X  0  X  0  X  X  X  X  X  X  0  X  0  X  X  X 
         45       0     0    X    X    X   X  X  X  0  X  0  X  X  X  X  X  X  0  X  0  X  X  X 
         46       0     0    X    X    X   X  X  X  0  X  0  X  X  X  X  X  X  0  X  0  X  X  X 
         47       0     0    X    X    X   X  X  X  0  X  0  X  X  X  X  X  X  0  X  0  X  X  X 
         48       0     0    X    X    X   X  X  X  0  X  0  X  X  X  X  X  X  0  X  0  X  X  X 
         49       0     0    X    X    X   X  X  X  0  X  0  X  X  X  X  X  X  0  X  0  X  X  X 
         50       0     0    X    X    X   X  X  X  0  X  0  X  X  X  X  X  X  0  X  0  X  X  X 
         51       0     0    X    X    X   X  X  X  0  X  0  X  X  X  X  X  X  0  X  0  X  X  X 
         52       0     0    X    X    X   X  X  X  0  X  0  X  X  X  X  X  X  0  X  0  X  X  X 
         53       0     0    X    X    X   X  X  X  0  X  0  X  X  X  X  X  X  0  X  0  X  X  X 
         54       0     0    X    X    X   X  X  X  0  X  0  X  X  X  X  X  X  0  X  0  X  X  X 
         55       0     0    X    X    X   X  X  X  0  X  0  X  X  X  X  X  X  0  X  0  X  X  X 
         56       0     0    X    X    X   X  X  X  0  X  0  X  X  X  X  X  X  0  X  0  X  X  X 
         57       0     0    X    X    X   X  X  X  0  X  0  X  X  X  X  X  X  0  X  0  X  X  X 
         58       0     0    X    X    X   X  X  X  0  X  0  X  X  X  X  X  X  0  X  0  X  X  X 
         59       0     0    X    X    X   X  X  X  0  X  0  X  X  X  X  X  X  0  X  0  X  X  X 
         60       0     0    X    X    X   X  X  X  0  X  0  X  X  X  X  X  X  0  X  0  X  X  X 
         61       0     0    X    X    X   X  X  X  0  X  0  X  X  X  X  X  X  0  X  0  X  X  X 
         62       0     0    X    X    X   X  X  X  0  X  0  X  X  X  X  X  X  0  X  0  X  X  X 
         63       0     0    X    X    X   X  X  X  0  X  0  X  X  X  X  X  X  0  X  0  X  X  X 
N7.C0: CMD-N xovercal offset = 0
N7.C0: CMD-S xovercal offset = 0
N7.C0: CTL xovercal offset   = 3
N7.C0: CKE xovercal offset   = 4
N7.C0: CLK xovercal offset   = 10
N7.C0.S18: STROBE                     0   1   2   3   4   5   6   7   8   9  10  11  12  13  14  15  16  17
N7.C0.S18: Rec En xovercal offset =  57  60  62   0   2   0  62  62   1  57  60  62   0   2   0  62  62   1 
N7.C0.S18: Tx Dqs xovercal offset =  57  63  63   0  63   0  63  63  63  63  63  63   0  63   0  63  63  63 
N7.C0.S18: Tx Dq xovercal offset  =  57  60  62   0   2   0  62  62   1  57  60  62   0   2   0  62  62   1 
N7.C0:         CMDn  CMDs  CTL  CKE  CLK   0  1  2  3  4  5  6  7  8
N7.C0: offsets:  0     0     3N7: getComplexCkeSetupTime defaultOffset = 98
N7: getComplexCkeSetupTime = 98
    4   10
Ctl Offsets Delta / final ctl offset / final cke offset /  98  /  37  /   6
Cke invertpiclk / Ctl invertpiclk / 0x0  /  0x0
N7: getComplexClkSetupTime defaultOffset = 0
N7: getComplexClkSetupTime = 0
ClkSetupTime = 10
N7: getComplexDqSetupTime defaultOffset = 0
N7: getComplexDqSetupTime = 0
N7.C0.S00: txdqoffset delta = 0, dq invertpiclk = 0
N7: getComplexDqsSetupTime defaultOffset = 40
N7: getComplexDqsSetupTime = 40
N7.C0.S00: txdqsoffset delta = 40
N7: getComplexRcvEnSetupTime defaultOffset = 37
N7: getComplexRcvEnSetupTime = 37
N7.C0.S00: rcvenoffset delta = 37
N7.C0.S00: Final txdqoffset / txdqsoffset / rcvenoffset / 25 /  1 / 62
N7: getComplexDqSetupTime defaultOffset = 0
N7: getComplexDqSetupTime = 0
N7.C0.S01: txdqoffset delta = 0, dq invertpiclk = 0
N7: getComplexDqsSetupTime defaultOffset = 40
N7: getComplexDqsSetupTime = 40
N7.C0.S01: txdqsoffset delta = 40
N7: getComplexRcvEnSetupTime defaultOffset = 37
N7: getComplexRcvEnSetupTime = 37
N7.C0.S01: rcvenoffset delta = 37
N7.C0.S01: Final txdqoffset / txdqsoffset / rcvenoffset / 60 / 36 / 33
N7: getComplexDqSetupTime defaultOffset = 0
N7: getComplexDqSetupTime = 0
N7.C0.S02: txdqoffset delta = 0, dq invertpiclk = 0
N7: getComplexDqsSetupTime defaultOffset = 40
N7: getComplexDqsSetupTime = 40
N7.C0.S02: txdqsoffset delta = 40
N7: getComplexRcvEnSetupTime defaultOffset = 37
N7: getComplexRcvEnSetupTime = 37
N7.C0.S02: rcvenoffset delta = 37
N7.C0.S02: Final txdqoffset / txdqsoffset / rcvenoffset / 30 /  6 /  3
N7: getComplexDqSetupTime defaultOffset = 0
N7: getComplexDqSetupTime = 0
N7.C0.S03: txdqoffset delta = 0, dq invertpiclk = 3
N7: getComplexDqsSetupTime defaultOffset = 40
N7: getComplexDqsSetupTime = 40
N7.C0.S03: txdqsoffset delta = 40
N7: getComplexRcvEnSetupTime defaultOffset = 37
N7: getComplexRcvEnSetupTime = 37
N7.C0.S03: rcvenoffset delta = 37
N7.C0.S03: Final txdqoffset / txdqsoffset / rcvenoffset /  0 / 40 / 37
N7: getComplexDqSetupTime defaultOffset = 0
N7: getComplexDqSetupTime = 0
N7.C0.S04: txdqoffset delta = 0, dq invertpiclk = 3
N7: getComplexDqsSetupTime defaultOffset = 40
N7: getComplexDqsSetupTime = 40
N7.C0.S04: txdqsoffset delta = 40
N7: getComplexRcvEnSetupTime defaultOffset = 37
N7: getComplexRcvEnSetupTime = 37
N7.C0.S04: rcvenoffset delta = 37
N7.C0.S04: Final txdqoffset / txdqsoffset / rcvenoffset / 34 / 10 /  7
N7: getComplexDqSetupTime defaultOffset = 0
N7: getComplexDqSetupTime = 0
N7.C0.S05: txdqoffset delta = 0, dq invertpiclk = 3
N7: getComplexDqsSetupTime defaultOffset = 40
N7: getComplexDqsSetupTime = 40
N7.C0.S05: txdqsoffset delta = 40
N7: getComplexRcvEnSetupTime defaultOffset = 37
N7: getComplexRcvEnSetupTime = 37
N7.C0.S05: rcvenoffset delta = 37
N7.C0.S05: Final txdqoffset / txdqsoffset / rcvenoffset /  0 / 40 / 37
N7: getComplexDqSetupTime defaultOffset = 0
N7: getComplexDqSetupTime = 0
N7.C0.S06: txdqoffset delta = 0, dq invertpiclk = 0
N7: getComplexDqsSetupTime defaultOffset = 40
N7: getComplexDqsSetupTime = 40
N7.C0.S06: txdqsoffset delta = 40
N7: getComplexRcvEnSetupTime defaultOffset = 37
N7: getComplexRcvEnSetupTime = 37
N7.C0.S06: rcvenoffset delta = 37
N7.C0.S06: Final txdqoffset / txdqsoffset / rcvenoffset / 30 /  6 /  3
N7: getComplexDqSetupTime defaultOffset = 0
N7: getComplexDqSetupTime = 0
N7.C0.S07: txdqoffset delta = 0, dq invertpiclk = 0
N7: getComplexDqsSetupTime defaultOffset = 40
N7: getComplexDqsSetupTime = 40
N7.C0.S07: txdqsoffset delta = 40
N7: getComplexRcvEnSetupTime defaultOffset = 37
N7: getComplexRcvEnSetupTime = 37
N7.C0.S07: rcvenoffset delta = 37
N7.C0.S07: Final txdqoffset / txdqsoffset / rcvenoffset / 62 / 38 / 35
N7: getComplexDqSetupTime defaultOffset = 0
N7: getComplexDqSetupTime = 0
N7.C0.S08: txdqoffset delta = 0, dq invertpiclk = 3
N7: getComplexDqsSetupTime defaultOffset = 40
N7: getComplexDqsSetupTime = 40
N7.C0.S08: txdqsoffset delta = 40
N7: getComplexRcvEnSetupTime defaultOffset = 37
N7: getComplexRcvEnSetupTime = 37
N7.C0.S08: rcvenoffset delta = 37
N7.C0.S08: Final txdqoffset / txdqsoffset / rcvenoffset / 33 /  9 /  6

N7: vmse_modes =          1,  0
N7.C1: piDelay CMDn  CMDs  CTL  CKE  CLK   0  1  2  3  4  5  6  7  8  9 10 11 12 13 14 15 16 17
          0       0     0    1    1    0   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
          1       0     0    1    1    0   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
          2       0     0    1    1    0   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
          3       0     0    1    1    0   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
          4       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
          5       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
          6       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
          7       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
          8       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
          9       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         10       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         11       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         12       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         13       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         14       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         15       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         16       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         17       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         18       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         19       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         20       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         21       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         22       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         23       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         24       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         25       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         26       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         27       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         28       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         29       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         30       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         31       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         32       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         33       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         34       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         35       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         36       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         37       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         38       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         39       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         40       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         41       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         42       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         43       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         44       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         45       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         46       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         47       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         48       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         49       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         50       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         51       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         52       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         53       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         54       0     0    1    1    1   0  1  1  1  1  1  1  1  1  0  1  1  1  1  1  1  1  1 
         55       0     0    1    1    1   X  1  1  1  1  1  1  1  1  X  1  1  1  1  1  1  1  1 
         56       0     0    1    1    1   X  0  1  1  1  1  1  1  1  X  0  1  1  1  1  1  1  1 
         57       0     0    1    1    1   X  X  1  1  1  1  1  1  1  X  X  1  1  1  1  1  1  1 
         58       0     0    1    1    1   X  X  0  1  1  1  0  0  1  X  X  0  1  1  1  0  0  1 
         59       0     0    1    1    1   X  X  X  1  1  1  X  X  1  X  X  X  1  1  1  X  X  1 
         60       0     0    1    1    1   X  X  X  0  1  1  X  X  1  X  X  X  0  1  1  X  X  1 
         61       0     0    1    1    1   X  X  X  X  1  0  X  X  1  X  X  X  X  1  0  X  X  1 
         62       0     0    1    1    1   X  X  X  X  1  X  X  X  1  X  X  X  X  1  X  X  X  1 
         63       0     0    0    1    1   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
N7.C1: setting ddrcrinvertpiclk
          0       0     0    X    1    1   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
          1       0     0    X    0    1   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
          2       0     0    X    X    1   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
          3       0     0    X    X    1   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
          4       0     0    X    X    1   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
          5       0     0    X    X    0   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
          6       0     0    X    X    X   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
          7       0     0    X    X    X   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
          8       0     0    X    X    X   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
          9       0     0    X    X    X   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
         10       0     0    X    X    X   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
         11       0     0    X    X    X   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
         12       0     0    X    X    X   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
         13       0     0    X    X    X   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
         14       0     0    X    X    X   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
         15       0     0    X    X    X   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
         16       0     0    X    X    X   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
         17       0     0    X    X    X   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
         18       0     0    X    X    X   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
         19       0     0    X    X    X   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
         20       0     0    X    X    X   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
         21       0     0    X    X    X   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
         22       0     0    X    X    X   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
         23       0     0    X    X    X   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
         24       0     0    X    X    X   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
         25       0     0    X    X    X   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
         26       0     0    X    X    X   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
         27       0     0    X    X    X   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
         28       0     0    X    X    X   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
         29       0     0    X    X    X   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
         30       0     0    X    X    X   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
         31       0     0    X    X    X   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
         32       0     0    X    X    X   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
         33       0     0    X    X    X   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
         34       0     0    X    X    X   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
         35       0     0    X    X    X   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
         36       0     0    X    X    X   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
         37       0     0    X    X    X   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
         38       0     0    X    X    X   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
         39       0     0    X    X    X   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
         40       0     0    X    X    X   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
         41       0     0    X    X    X   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
         42       0     0    X    X    X   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
         43       0     0    X    X    X   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
         44       0     0    X    X    X   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
         45       0     0    X    X    X   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
         46       0     0    X    X    X   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
         47       0     0    X    X    X   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
         48       0     0    X    X    X   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
         49       0     0    X    X    X   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
         50       0     0    X    X    X   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
         51       0     0    X    X    X   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
         52       0     0    X    X    X   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
         53       0     0    X    X    X   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
         54       0     0    X    X    X   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
         55       0     0    X    X    X   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
         56       0     0    X    X    X   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
         57       0     0    X    X    X   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
         58       0     0    X    X    X   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
         59       0     0    X    X    X   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
         60       0     0    X    X    X   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
         61       0     0    X    X    X   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
         62       0     0    X    X    X   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
         63       0     0    X    X    X   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
N7.C1: CMD-N xovercal offset = 0
N7.C1: CMD-S xovercal offset = 0
N7.C1: CTL xovercal offset   = 63
N7.C1: CKE xovercal offset   = 1
N7.C1: CLK xovercal offset   = 5
N7.C1.S18: STROBE                     0   1   2   3   4   5   6   7   8   9  10  11  12  13  14  15  16  17
N7.C1.S18: Rec En xovercal offset =  54  56  58  60  63  61  58  58  63  54  56  58  60  63  61  58  58  63 
N7.C1.S18: Tx Dqs xovercal offset =  54  63  63  63  63  63  63  63  63  63  63  63  63  63  63  63  63  63 
N7.C1.S18: Tx Dq xovercal offset  =  54  56  58  60  63  61  58  58  63  54  56  58  60  63  61  58  58  63 
N7.C1:         CMDn  CMDs  CTL  CKE  CLK   0  1  2  3  4  5  6  7  8
N7.C1: offsets:  0     0    63N7: getComplexCkeSetupTime defaultOffset = 98
N7: getComplexCkeSetupTime = 98
    1    5
Ctl Offsets Delta / final ctl offset / final cke offset /  98  /   1  /  35
Cke invertpiclk / Ctl invertpiclk / 0x0  /  0x0
N7: getComplexClkSetupTime defaultOffset = 0
N7: getComplexClkSetupTime = 0
ClkSetupTime = 37
N7: getComplexDqSetupTime defaultOffset = 0
N7: getComplexDqSetupTime = 0
N7.C1.S00: txdqoffset delta = 0, dq invertpiclk = 0
N7: getComplexDqsSetupTime defaultOffset = 40
N7: getComplexDqsSetupTime = 40
N7.C1.S00: txdqsoffset delta = 40
N7: getComplexRcvEnSetupTime defaultOffset = 37
N7: getComplexRcvEnSetupTime = 37
N7.C1.S00: rcvenoffset delta = 37
N7.C1.S00: Final txdqoffset / txdqsoffset / rcvenoffset / 54 / 30 / 27
N7: getComplexDqSetupTime defaultOffset = 0
N7: getComplexDqSetupTime = 0
N7.C1.S01: txdqoffset delta = 0, dq invertpiclk = 0
N7: getComplexDqsSetupTime defaultOffset = 40
N7: getComplexDqsSetupTime = 40
N7.C1.S01: txdqsoffset delta = 40
N7: getComplexRcvEnSetupTime defaultOffset = 37
N7: getComplexRcvEnSetupTime = 37
N7.C1.S01: rcvenoffset delta = 37
N7.C1.S01: Final txdqoffset / txdqsoffset / rcvenoffset / 24 /  0 / 61
N7: getComplexDqSetupTime defaultOffset = 0
N7: getComplexDqSetupTime = 0
N7.C1.S02: txdqoffset delta = 0, dq invertpiclk = 0
N7: getComplexDqsSetupTime defaultOffset = 40
N7: getComplexDqsSetupTime = 40
N7.C1.S02: txdqsoffset delta = 40
N7: getComplexRcvEnSetupTime defaultOffset = 37
N7: getComplexRcvEnSetupTime = 37
N7.C1.S02: rcvenoffset delta = 37
N7.C1.S02: Final txdqoffset / txdqsoffset / rcvenoffset / 58 / 34 / 31
N7: getComplexDqSetupTime defaultOffset = 0
N7: getComplexDqSetupTime = 0
N7.C1.S03: txdqoffset delta = 0, dq invertpiclk = 0
N7: getComplexDqsSetupTime defaultOffset = 40
N7: getComplexDqsSetupTime = 40
N7.C1.S03: txdqsoffset delta = 40
N7: getComplexRcvEnSetupTime defaultOffset = 37
N7: getComplexRcvEnSetupTime = 37
N7.C1.S03: rcvenoffset delta = 37
N7.C1.S03: Final txdqoffset / txdqsoffset / rcvenoffset / 28 /  4 /  1
N7: getComplexDqSetupTime defaultOffset = 0
N7: getComplexDqSetupTime = 0
N7.C1.S04: txdqoffset delta = 0, dq invertpiclk = 0
N7: getComplexDqsSetupTime defaultOffset = 40
N7: getComplexDqsSetupTime = 40
N7.C1.S04: txdqsoffset delta = 40
N7: getComplexRcvEnSetupTime defaultOffset = 37
N7: getComplexRcvEnSetupTime = 37
N7.C1.S04: rcvenoffset delta = 37
N7.C1.S04: Final txdqoffset / txdqsoffset / rcvenoffset / 63 / 39 / 36
N7: getComplexDqSetupTime defaultOffset = 0
N7: getComplexDqSetupTime = 0
N7.C1.S05: txdqoffset delta = 0, dq invertpiclk = 0
N7: getComplexDqsSetupTime defaultOffset = 40
N7: getComplexDqsSetupTime = 40
N7.C1.S05: txdqsoffset delta = 40
N7: getComplexRcvEnSetupTime defaultOffset = 37
N7: getComplexRcvEnSetupTime = 37
N7.C1.S05: rcvenoffset delta = 37
N7.C1.S05: Final txdqoffset / txdqsoffset / rcvenoffset / 29 /  5 /  2
N7: getComplexDqSetupTime defaultOffset = 0
N7: getComplexDqSetupTime = 0
N7.C1.S06: txdqoffset delta = 0, dq invertpiclk = 0
N7: getComplexDqsSetupTime defaultOffset = 40
N7: getComplexDqsSetupTime = 40
N7.C1.S06: txdqsoffset delta = 40
N7: getComplexRcvEnSetupTime defaultOffset = 37
N7: getComplexRcvEnSetupTime = 37
N7.C1.S06: rcvenoffset delta = 37
N7.C1.S06: Final txdqoffset / txdqsoffset / rcvenoffset / 58 / 34 / 31
N7: getComplexDqSetupTime defaultOffset = 0
N7: getComplexDqSetupTime = 0
N7.C1.S07: txdqoffset delta = 0, dq invertpiclk = 0
N7: getComplexDqsSetupTime defaultOffset = 40
N7: getComplexDqsSetupTime = 40
N7.C1.S07: txdqsoffset delta = 40
N7: getComplexRcvEnSetupTime defaultOffset = 37
N7: getComplexRcvEnSetupTime = 37
N7.C1.S07: rcvenoffset delta = 37
N7.C1.S07: Final txdqoffset / txdqsoffset / rcvenoffset / 26 /  2 / 63
N7: getComplexDqSetupTime defaultOffset = 0
N7: getComplexDqSetupTime = 0
N7.C1.S08: txdqoffset delta = 0, dq invertpiclk = 0
N7: getComplexDqsSetupTime defaultOffset = 40
N7: getComplexDqsSetupTime = 40
N7.C1.S08: txdqsoffset delta = 40
N7: getComplexRcvEnSetupTime defaultOffset = 37
N7: getComplexRcvEnSetupTime = 37
N7.C1.S08: rcvenoffset delta = 37
N7.C1.S08: Final txdqoffset / txdqsoffset / rcvenoffset / 63 / 39 / 36

Checkpoint Code: Socket 0, 0xB6, 0x02, 0x0000

START - MXB Clock Train
N5: SetupJckSmbCfg: JCK VLINFREQ set to: 0x820F1028
N1: HsxInitDdrioInterface
N1.C0: rxVref = 0x5F
N1.C1: rxVref = 0x5F
N1: HsxVmseCompInit
N5: SetupJckSmbCfg: PLL is locked.
N7: SetupJckSmbCfg: JCK VLINFREQ set to: 0x820F1028
Checkpoint Code: Socket 0, 0xB6, 0x58, 0x0000
N1: VmseCrossoverCalib
N1: Enable xovercal
N1: vmse_modes =          1,  0
N1.C0: piDelay CMDn  CMDs  CTL  CKE  CLK   0  1  2  3  4  5  6  7  8  9 10 11 12 13 14 15 16 17
          0       0     0    0    0    0   1  1  1  1  0  1  1  1  0  1  1  1  1  0  1  1  1  0 
          1       0     0    0    0    0   1  1  1  1  0  1  1  1  1  1  1  1  1  0  1  1  1  1 
          2       0     0    0    0    0   1  1  1  1  0  1  1  1  1  1  1  1  1  0  1  1  1  1 
          3       0     0    1    0    0   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
          4       0     0    1    0    0   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
          5       0     0    1    1    0   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
          6       0     0    1    1    0   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
          7       0     0    1    1    0   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
          8       0     0    1    1    0   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
          9       0     0    1    1    0   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         10       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         11       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         12       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         13       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         14       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         15       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         16       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         17       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         18       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         19       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         20       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         21       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         22       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         23       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         24       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         25       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         26       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         27       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         28       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         29       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         30       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         31       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         32       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         33       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         34       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         35       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         36       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         37       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         38       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         39       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         40       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         41       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         42       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         43       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         44       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         45       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         46       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         47       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         48       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         49       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         50       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         51       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         52       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         53       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         54       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         55       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         56       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         57       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         58       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         59       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         60       0     0    1    1    1   0  1  1  1  1  1  1  1  1  0  1  1  1  1  1  1  1  1 
         61       0     0    1    1    1   X  0  1  1  1  1  1  1  1  X  0  1  1  1  1  1  1  1 
         62       0     0    1    1    1   X  X  1  1  1  1  1  1  1  X  X  1  1  1  1  1  1  1 
         63       0     0    1    1    1   X  X  1  1  1  1  1  1  1  X  X  1  1  1  1  1  1  1 
N1.C0: setting ddrcrinvertpiclk
          0       0     0    1    1    1   X  X  0  1  1  1  0  0  1  X  X  0  1  1  1  0  0  1 
          1       0     0    1    1    1   X  X  0  0  1  1  0  0  1  X  X  0  0  1  1  0  0  1 
          2       0     0    1    1    1   X  X  0  X  1  0  0  0  1  X  X  0  X  1  0  0  0  1 
          3       0     0    1    1    1   X  X  0  X  1  X  0  0  0  X  X  0  X  1  X  0  0  0 
          4       0     0    0    1    1   X  X  0  X  0  X  0  0  X  X  X  0  X  0  X  0  0  X 
          5       0     0    X    1    1   X  X  0  X  X  X  0  0  X  X  X  0  X  X  X  0  0  X 
          6       0     0    X    0    1   X  X  0  X  X  X  0  0  X  X  X  0  X  X  X  0  0  X 
          7       0     0    X    X    1   X  X  0  X  X  X  0  0  X  X  X  0  X  X  X  0  0  X 
          8       0     0    X    X    1   X  X  0  X  X  X  0  0  X  X  X  0  X  X  X  0  0  X 
          9       0     0    X    X    1   X  X  0  X  X  X  0  0  X  X  X  0  X  X  X  0  0  X 
         10       0     0    X    X    1   X  X  0  X  X  X  0  0  X  X  X  0  X  X  X  0  0  X 
         11       0     0    X    X    0   X  X  0  X  X  X  0  0  X  X  X  0  X  X  X  0  0  X 
         12       0     0    X    X    X   X  X  0  X  X  X  0  0  X  X  X  0  X  X  X  0  0  X 
         13       0     0    X    X    X   X  X  0  X  X  X  0  0  X  X  X  0  X  X  X  0  0  X 
         14       0     0    X    X    X   X  X  0  X  X  X  0  0  X  X  X  0  X  X  X  0  0  X 
         15       0     0    X    X    X   X  X  0  X  X  X  0  0  X  X  X  0  X  X  X  0  0  X 
         16       0     0    X    X    X   X  X  0  X  X  X  0  0  X  X  X  0  X  X  X  0  0  X 
         17       0     0    X    X    X   X  X  0  X  X  X  0  0  X  X  X  0  X  X  X  0  0  X 
         18       0     0    X    X    X   X  X  0  X  X  X  0  0  X  X  X  0  X  X  X  0  0  X 
         19       0     0    X    X    X   X  X  0  X  X  X  0  0  X  X  X  0  X  X  X  0  0  X 
         20       0     0    X    X    X   X  X  0  X  X  X  0  0  X  X  X  0  X  X  X  0  0  X 
         21       0     0    X    X    X   X  X  0  X  X  X  0  0  X  X  X  0  X  X  X  0  0  X 
         22       0     0    X    X    X   X  X  0  X  X  X  0  0  X  X  X  0  X  X  X  0  0  X 
         23       0     0    X    X    X   X  X  0  X  X  X  0  0  X  X  X  0  X  X  X  0  0  X 
         24       0     0    X    X    X   X  X  0  X  X  X  0  0  X  X  X  0  X  X  X  0  0  X 
         25       0     0    X    X    X   X  X  0  X  X  X  0  0  X  X  X  0  X  X  X  0  0  X 
         26       0     0    X    X    X   X  X  0  X  X  X  0  0  X  X  X  0  X  X  X  0  0  X 
         27       0     0    X    X    X   X  X  0  X  X  X  0  0  X  X  X  0  X  X  X  0  0  X 
         28       0     0    X    X    X   X  X  0  X  X  X  0  0  X  X  X  0  X  X  X  0  0  X 
         29       0     0    X    X    X   X  X  0  X  X  X  0  0  X  X  X  0  X  X  X  0  0  X 
         30       0     0    X    X    X   X  X  0  X  X  X  0  0  X  X  X  0  X  X  X  0  0  X 
         31       0     0    X    X    X   X  X  0  X  X  X  0  0  X  X  X  0  X  X  X  0  0  X 
         32       0     0    X    X    X   X  X  0  X  X  X  0  0  X  X  X  0  X  X  X  0  0  X 
         33       0     0    X    X    X   X  X  0  X  X  X  0  0  X  X  X  0  X  X  X  0  0  X 
         34       0     0    X    X    X   X  X  0  X  X  X  0  0  X  X  X  0  X  X  X  0  0  X 
         35       0     0    X    X    X   X  X  0  X  X  X  0  0  X  X  X  0  X  X  X  0  0  X 
         36       0     0    X    X    X   X  X  0  X  X  X  0  0  X  X  X  0  X  X  X  0  0  X 
         37       0     0    X    X    X   X  X  0  X  X  X  0  0  X  X  X  0  X  X  X  0  0  X 
         38       0     0    X    X    X   X  X  0  X  X  X  0  0  X  X  X  0  X  X  X  0  0  X 
         39       0     0    X    X    X   X  X  0  X  X  X  0  0  X  X  X  0  X  X  X  0  0  X 
         40       0     0    X    X    X   X  X  0  X  X  X  0  0  X  X  X  0  X  X  X  0  0  X 
         41       0     0    X    X    X   X  X  0  X  X  X  0  0  X  X  X  0  X  X  X  0  0  X 
         42       0     0    X    X    X   X  X  0  X  X  X  0  0  X  X  X  0  X  X  X  0  0  X 
         43       0     0    X    X    X   X  X  0  X  X  X  0  0  X  X  X  0  X  X  X  0  0  X 
         44       0     0    X    X    X   X  X  0  X  X  X  0  0  X  X  X  0  X  X  X  0  0  X 
         45       0     0    X    X    X   X  X  0  X  X  X  0  0  X  X  X  0  X  X  X  0  0  X 
         46       0     0    X    X    X   X  X  0  X  X  X  0  0  X  X  X  0  X  X  X  0  0  X 
         47       0     0    X    X    X   X  X  0  X  X  X  0  0  X  X  X  0  X  X  X  0  0  X 
         48       0     0    X    X    X   X  X  0  X  X  X  0  0  X  X  X  0  X  X  X  0  0  X 
         49       0     0    X    X    X   X  X  0  X  X  X  0  0  X  X  X  0  X  X  X  0  0  X 
         50       0     0    X    X    X   X  X  0  X  X  X  0  0  X  X  X  0  X  X  X  0  0  X 
         51       0     0    X    X    X   X  X  0  X  X  X  0  0  X  X  X  0  X  X  X  0  0  X 
         52       0     0    X    X    X   X  X  0  X  X  X  0  0  X  X  X  0  X  X  X  0  0  X 
         53       0     0    X    X    X   X  X  0  X  X  X  0  0  X  X  X  0  X  X  X  0  0  X 
         54       0     0    X    X    X   X  X  0  X  X  X  0  0  X  X  X  0  X  X  X  0  0  X 
         55       0     0    X    X    X   X  X  0  X  X  X  0  0  X  X  X  0  X  X  X  0  0  X 
         56       0     0    X    X    X   X  X  0  X  X  X  0  0  X  X  X  0  X  X  X  0  0  X 
         57       0     0    X    X    X   X  X  0  X  X  X  0  0  X  X  X  0  X  X  X  0  0  X 
         58       0     0    X    X    X   X  X  0  X  X  X  0  0  X  X  X  0  X  X  X  0  0  X 
         59       0     0    X    X    X   X  X  0  X  X  X  0  0  X  X  X  0  X  X  X  0  0  X 
         60       0     0    X    X    X   X  X  0  X  X  X  0  0  X  X  X  0  X  X  X  0  0  X 
         61       0     0    X    X    X   X  X  0  X  X  X  0  0  X  X  X  0  X  X  X  0  0  X 
         62       0     0    X    X    X   X  X  0  X  X  X  0  0  X  X  X  0  X  X  X  0  0  X 
         63       0     0    X    X    X   X  X  1  X  X  X  1  1  X  X  X  1  X  X  X  1  1  X 
N1.C0: CMD-N xovercal offset = 0
N1.C0: CMD-S xovercal offset = 0
N1.C0: CTL xovercal offset   = 4
N1.C0: CKE xovercal offset   = 6
N1.C0: CLK xovercal offset   = 11
N1.C0.S18: STROBE                     0   1   2   3   4   5   6   7   8   9  10  11  12  13  14  15  16  17
N1.C0.S18: Rec En xovercal offset =  60  61   0   1   4   2   0   0   3  60  61   0   1   4   2   0   0   3 
N1.C0.S18: Tx Dqs xovercal offset =  60  63   0  63  63  63   0   0  63  63  63   0  63  63  63   0   0  63 
N1.C0.S18: Tx Dq xovercal offset  =  60  61   0   1   4   2   0   0   3  60  61   0   1   4   2   0   0   3 
N1.C0:         CMDn  CMDs  CTL  CKE  CLK   0  1  2  3  4  5  6  7  8
N1.C0: offsets:  0     0     4N1: getComplexCkeSetupTime defaultOffset = 98
N1: getComplexCkeSetupTime = 98
    6   11
Ctl Offsets Delta / final ctl offset / final cke offset /  98  /  38  /   8
Cke invertpiclk / Ctl invertpiclk / 0x0  /  0x0
N1: getComplexClkSetupTime defaultOffset = 0
N1: getComplexClkSetupTime = 0
ClkSetupTime = 11
N1: getComplexDqSetupTime defaultOffset = 0
N1: getComplexDqSetupTime = 0
N1.C0.S00: txdqoffset delta = 0, dq invertpiclk = 0
N1: getComplexDqsSetupTime defaultOffset = 40
N1: getComplexDqsSetupTime = 40
N1.C0.S00: txdqsoffset delta = 40
N1: getComplexRcvEnSetupTime defaultOffset = 37
N1: getComplexRcvEnSetupTime = 37
N1.C0.S00: rcvenoffset delta = 37
N1.C0.S00: Final txdqoffset / txdqsoffset / rcvenoffset / 28 /  4 /  1
N1: getComplexDqSetupTime defaultOffset = 0
N1: getComplexDqSetupTime = 0
N1.C0.S01: txdqoffset delta = 0, dq invertpiclk = 0
N1: getComplexDqsSetupTime defaultOffset = 40
N1: getComplexDqsSetupTime = 40
N1.C0.S01: txdqsoffset delta = 40
N1: getComplexRcvEnSetupTime defaultOffset = 37
N1: getComplexRcvEnSetupTime = 37
N1.C0.S01: rcvenoffset delta = 37
N1.C0.S01: Final txdqoffset / txdqsoffset / rcvenoffset / 61 / 37 / 34
N1: getComplexDqSetupTime defaultOffset = 0
N1: getComplexDqSetupTime = 0
N1.C0.S02: txdqoffset delta = 0, dq invertpiclk = 3
N1: getComplexDqsSetupTime defaultOffset = 40
N1: getComplexDqsSetupTime = 40
N1.C0.S02: txdqsoffset delta = 40
N1: getComplexRcvEnSetupTime defaultOffset = 37
N1: getComplexRcvEnSetupTime = 37
N1.C0.S02: rcvenoffset delta = 37
N1.C0.S02: Final txdqoffset / txdqsoffset / rcvenoffset / 32 /  8 /  5
N1: getComplexDqSetupTime defaultOffset = 0
N1: getComplexDqSetupTime = 0
N1.C0.S03: txdqoffset delta = 0, dq invertpiclk = 3
N1: getComplexDqsSetupTime defaultOffset = 40
N1: getComplexDqsSetupTime = 40
N1.C0.S03: txdqsoffset delta = 40
N1: getComplexRcvEnSetupTime defaultOffset = 37
N1: getComplexRcvEnSetupTime = 37
N1.C0.S03: rcvenoffset delta = 37
N1.C0.S03: Final txdqoffset / txdqsoffset / rcvenoffset /  1 / 41 / 38
N1: getComplexDqSetupTime defaultOffset = 0
N1: getComplexDqSetupTime = 0
N1.C0.S04: txdqoffset delta = 0, dq invertpiclk = 3
N1: getComplexDqsSetupTime defaultOffset = 40
N1: getComplexDqsSetupTime = 40
N1.C0.S04: txdqsoffset delta = 40
N1: getComplexRcvEnSetupTime defaultOffset = 37
N1: getComplexRcvEnSetupTime = 37
N1.C0.S04: rcvenoffset delta = 37
N1.C0.S04: Final txdqoffset / txdqsoffset / rcvenoffset / 36 / 12 /  9
N1: getComplexDqSetupTime defaultOffset = 0
N1: getComplexDqSetupTime = 0
N1.C0.S05: txdqoffset delta = 0, dq invertpiclk = 3
N1: getComplexDqsSetupTime defaultOffset = 40
N1: getComplexDqsSetupTime = 40
N1.C0.S05: txdqsoffset delta = 40
N1: getComplexRcvEnSetupTime defaultOffset = 37
N1: getComplexRcvEnSetupTime = 37
N1.C0.S05: rcvenoffset delta = 37
N1.C0.S05: Final txdqoffset / txdqsoffset / rcvenoffset /  2 / 42 / 39
N1: getComplexDqSetupTime defaultOffset = 0
N1: getComplexDqSetupTime = 0
N1.C0.S06: txdqoffset delta = 0, dq invertpiclk = 3
N1: getComplexDqsSetupTime defaultOffset = 40
N1: getComplexDqsSetupTime = 40
N1.C0.S06: txdqsoffset delta = 40
N1: getComplexRcvEnSetupTime defaultOffset = 37
N1: getComplexRcvEnSetupTime = 37
N1.C0.S06: rcvenoffset delta = 37
N1.C0.S06: Final txdqoffset / txdqsoffset / rcvenoffset / 32 /  8 /  5
N1: getComplexDqSetupTime defaultOffset = 0
N1: getComplexDqSetupTime = 0
N1.C0.S07: txdqoffset delta = 0, dq invertpiclk = 3
N1: getComplexDqsSetupTime defaultOffset = 40
N1: getComplexDqsSetupTime = 40
N1.C0.S07: txdqsoffset delta = 40
N1: getComplexRcvEnSetupTime defaultOffset = 37
N1: getComplexRcvEnSetupTime = 37
N1.C0.S07: rcvenoffset delta = 37
N1.C0.S07: Final txdqoffset / txdqsoffset / rcvenoffset /  0 / 40 / 37
N1: getComplexDqSetupTime defaultOffset = 0
N1: getComplexDqSetupTime = 0
N1.C0.S08: txdqoffset delta = 0, dq invertpiclk = 3
N1: getComplexDqsSetupTime defaultOffset = 40
N1: getComplexDqsSetupTime = 40
N1.C0.S08: txdqsoffset delta = 40
N1: getComplexRcvEnSetupTime defaultOffset = 37
N1: getComplexRcvEnSetupTime = 37
N1.C0.S08: rcvenoffset delta = 37
N1.C0.S08: Final txdqoffset / txdqsoffset / rcvenoffset / 35 / 11 /  8

N1: vmse_modes =          1,  0
N1.C1: piDelay CMDn  CMDs  CTL  CKE  CLK   0  1  2  3  4  5  6  7  8  9 10 11 12 13 14 15 16 17
          0       0     0    1    0    0   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
          1       0     0    1    1    0   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
          2       0     0    1    1    0   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
          3       0     0    1    1    0   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
          4       0     0    1    1    0   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
          5       0     0    1    1    0   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
          6       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
          7       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
          8       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
          9       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         10       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         11       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         12       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         13       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         14       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         15       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         16       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         17       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         18       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         19       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         20       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         21       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         22       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         23       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         24       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         25       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         26       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         27       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         28       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         29       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         30       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         31       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         32       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         33       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         34       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         35       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         36       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         37       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         38       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         39       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         40       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         41       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         42       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         43       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         44       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         45       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         46       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         47       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         48       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         49       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         50       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         51       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         52       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         53       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         54       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         55       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         56       0     0    1    1    1   0  1  1  1  1  1  1  1  1  0  1  1  1  1  1  1  1  1 
         57       0     0    1    1    1   X  1  1  1  1  1  1  1  1  X  0  1  1  1  1  1  1  1 
         58       0     0    1    1    1   X  0  1  1  1  1  1  1  1  X  X  1  1  1  1  1  1  1 
         59       0     0    1    1    1   X  X  0  1  1  1  1  1  1  X  X  0  1  1  1  1  1  1 
         60       0     0    1    1    1   X  X  X  1  1  1  0  0  1  X  X  X  1  1  1  0  0  1 
         61       0     0    1    1    1   X  X  X  0  1  1  X  X  1  X  X  X  0  1  1  X  X  1 
         62       0     0    1    1    1   X  X  X  X  1  1  X  X  1  X  X  X  X  1  0  X  X  1 
         63       0     0    1    1    1   X  X  X  X  1  0  X  X  1  X  X  X  X  1  X  X  X  1 
N1.C1: setting ddrcrinvertpiclk
          0       0     0    1    1    1   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
          1       0     0    0    1    1   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
          2       0     0    X    1    1   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
          3       0     0    X    0    1   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
          4       0     0    X    X    1   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
          5       0     0    X    X    1   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
          6       0     0    X    X    1   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
          7       0     0    X    X    0   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
          8       0     0    X    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
          9       0     0    X    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         10       0     0    X    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         11       0     0    X    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         12       0     0    X    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         13       0     0    X    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         14       0     0    X    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         15       0     0    X    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         16       0     0    X    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         17       0     0    X    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         18       0     0    X    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         19       0     0    X    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         20       0     0    X    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         21       0     0    X    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         22       0     0    X    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         23       0     0    X    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         24       0     0    X    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         25       0     0    X    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         26       0     0    X    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         27       0     0    X    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         28       0     0    X    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         29       0     0    X    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         30       0     0    X    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         31       0     0    X    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         32       0     0    X    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         33       0     0    X    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         34       0     0    X    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         35       0     0    X    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         36       0     0    X    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         37       0     0    X    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         38       0     0    X    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         39       0     0    X    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         40       0     0    X    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         41       0     0    X    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         42       0     0    X    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         43       0     0    X    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         44       0     0    X    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         45       0     0    X    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         46       0     0    X    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         47       0     0    X    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         48       0     0    X    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         49       0     0    X    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         50       0     0    X    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         51       0     0    X    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         52       0     0    X    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         53       0     0    X    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         54       0     0    X    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         55       0     0    X    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         56       0     0    X    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         57       0     0    X    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         58       0     0    X    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         59       0     0    X    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         60       0     0    X    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         61       0     0    X    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         62       0     0    X    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         63       0     0    X    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
N1.C1: CMD-N xovercal offset = 0
N1.C1: CMD-S xovercal offset = 0
N1.C1: CTL xovercal offset   = 1
N1.C1: CKE xovercal offset   = 3
N1.C1: CLK xovercal offset   = 7
N1.C1.S18: STROBE                     0   1   2   3   4   5   6   7   8   9  10  11  12  13  14  15  16  17
N1.C1.S18: Rec En xovercal offset =  56  58  59  61   0  63  60  60   0  56  57  59  61   0  62  60  60   0 
N1.C1.S18: Tx Dqs xovercal offset =  56  63  63  63   0  63  63  63   0  63  63  63  63   0  63  63  63   0 
N1.C1.S18: Tx Dq xovercal offset  =  56  58  59  61   0  63  60  60   0  56  57  59  61   0  62  60  60   0 
N1.C1:         CMDn  CMDs  CTL  CKE  CLK   0  1  2  3  4  5  6  7  8
N1.C1: offsets:  0     0     1N1: getComplexCkeSetupTime defaultOffset = 98
N1: getComplexCkeSetupTime = 98
    3    7
Ctl Offsets Delta / final ctl offset / final cke offset /  98  /   3  /  37
Cke invertpiclk / Ctl invertpiclk / 0x0  /  0x0
N1: getComplexClkSetupTime defaultOffset = 0
N1: getComplexClkSetupTime = 0
ClkSetupTime = 39
N1: getComplexDqSetupTime defaultOffset = 0
N1: getComplexDqSetupTime = 0
N1.C1.S00: txdqoffset delta = 0, dq invertpiclk = 0
N1: getComplexDqsSetupTime defaultOffset = 40
N1: getComplexDqsSetupTime = 40
N1.C1.S00: txdqsoffset delta = 40
N1: getComplexRcvEnSetupTime defaultOffset = 37
N1: getComplexRcvEnSetupTime = 37
N1.C1.S00: rcvenoffset delta = 37
N1.C1.S00: Final txdqoffset / txdqsoffset / rcvenoffset / 56 / 32 / 29
N1: getComplexDqSetupTime defaultOffset = 0
N1: getComplexDqSetupTime = 0
N1.C1.S01: txdqoffset delta = 0, dq invertpiclk = 0
N1: getComplexDqsSetupTime defaultOffset = 40
N1: getComplexDqsSetupTime = 40
N1.C1.S01: txdqsoffset delta = 40
N1: getComplexRcvEnSetupTime defaultOffset = 37
N1: getComplexRcvEnSetupTime = 37
N1.C1.S01: rcvenoffset delta = 37
N1.C1.S01: Final txdqoffset / txdqsoffset / rcvenoffset / 26 /  2 / 63
N1: getComplexDqSetupTime defaultOffset = 0
N1: getComplexDqSetupTime = 0
N1.C1.S02: txdqoffset delta = 0, dq invertpiclk = 0
N1: getComplexDqsSetupTime defaultOffset = 40
N1: getComplexDqsSetupTime = 40
N1.C1.S02: txdqsoffset delta = 40
N1: getComplexRcvEnSetupTime defaultOffset = 37
N1: getComplexRcvEnSetupTime = 37
N1.C1.S02: rcvenoffset delta = 37
N1.C1.S02: Final txdqoffset / txdqsoffset / rcvenoffset / 59 / 35 / 32
N1: getComplexDqSetupTime defaultOffset = 0
N1: getComplexDqSetupTime = 0
N1.C1.S03: txdqoffset delta = 0, dq invertpiclk = 0
N1: getComplexDqsSetupTime defaultOffset = 40
N1: getComplexDqsSetupTime = 40
N1.C1.S03: txdqsoffset delta = 40
N1: getComplexRcvEnSetupTime defaultOffset = 37
N1: getComplexRcvEnSetupTime = 37
N1.C1.S03: rcvenoffset delta = 37
N1.C1.S03: Final txdqoffset / txdqsoffset / rcvenoffset / 29 /  5 /  2
N1: getComplexDqSetupTime defaultOffset = 0
N1: getComplexDqSetupTime = 0
N1.C1.S04: txdqoffset delta = 0, dq invertpiclk = 3
N1: getComplexDqsSetupTime defaultOffset = 40
N1: getComplexDqsSetupTime = 40
N1.C1.S04: txdqsoffset delta = 40
N1: getComplexRcvEnSetupTime defaultOffset = 37
N1: getComplexRcvEnSetupTime = 37
N1.C1.S04: rcvenoffset delta = 37
N1.C1.S04: Final txdqoffset / txdqsoffset / rcvenoffset /  0 / 40 / 37
N1: getComplexDqSetupTime defaultOffset = 0
N1: getComplexDqSetupTime = 0
N1.C1.S05: txdqoffset delta = 0, dq invertpiclk = 0
N1: getComplexDqsSetupTime defaultOffset = 40
N1: getComplexDqsSetupTime = 40
N1.C1.S05: txdqsoffset delta = 40
N1: getComplexRcvEnSetupTime defaultOffset = 37
N1: getComplexRcvEnSetupTime = 37
N1.C1.S05: rcvenoffset delta = 37
N1.C1.S05: Final txdqoffset / txdqsoffset / rcvenoffset / 31 /  7 /  4
N1: getComplexDqSetupTime defaultOffset = 0
N1: getComplexDqSetupTime = 0
N1.C1.S06: txdqoffset delta = 0, dq invertpiclk = 0
N1: getComplexDqsSetupTime defaultOffset = 40
N1: getComplexDqsSetupTime = 40
N1.C1.S06: txdqsoffset delta = 40
N1: getComplexRcvEnSetupTime defaultOffset = 37
N1: getComplexRcvEnSetupTime = 37
N1.C1.S06: rcvenoffset delta = 37
N1.C1.S06: Final txdqoffset / txdqsoffset / rcvenoffset / 60 / 36 / 33
N1: getComplexDqSetupTime defaultOffset = 0
N1: getComplexDqSetupTime = 0
N1.C1.S07: txdqoffset delta = 0, dq invertpiclk = 0
N1: getComplexDqsSetupTime defaultOffset = 40
N1: getComplexDqsSetupTime = 40
N1.C1.S07: txdqsoffset delta = 40
N1: getComplexRcvEnSetupTime defaultOffset = 37
N1: getComplexRcvEnSetupTime = 37
N1.C1.S07: rcvenoffset delta = 37
N1.C1.S07: Final txdqoffset / txdqsoffset / rcvenoffset / 28 /  4 /  1
N1: getComplexDqSetupTime defaultOffset = 0
N1: getComplexDqSetupTime = 0
N1.C1.S08: txdqoffset delta = 0, dq invertpiclk = 3
N1: getComplexDqsSetupTime defaultOffset = 40
N1: getComplexDqsSetupTime = 40
N1.C1.S08: txdqsoffset delta = 40
N1: getComplexRcvEnSetupTime defaultOffset = 37
N1: getComplexRcvEnSetupTime = 37
N1.C1.S08: rcvenoffset delta = 37
N1.C1.S08: Final txdqoffset / txdqsoffset / rcvenoffset /  0 / 40 / 37

N3.C0: VmseRefVckResync: ddrFreq = 0x2, VMSE_MODE_2_1 = 1, VMSE_PREAMBLE_2UI = 0
N5.C0: SetupJckSmbCfg: dlyFrms = 15
N7: SetupJckSmbCfg: PLL is locked.
N5.C0: cwleffective = 8
N7.C0: SetupJckSmbCfg: dlyFrms = 15
N1: SetupJckSmbCfg: JCK VLINFREQ set to: 0x820F1028
N5.C0: PreVMSE Training raw cleff = 9, raw cwleff = 7
N7.C0: cwleffective = 8
N3.C0: VmseRefVckResync: VLINKFREQNXT set to: 0x20F940A
N5.C0: vmseratio = 0, revisionId = 5, vmse_mode = 1, QCRM_ENABLE = 0
N7.C0: PreVMSE Training raw cleff = 9, raw cwleff = 7
N1: SetupJckSmbCfg: PLL is locked.
N5: SetupJckSmbCfg: JCK wpsyncrcven = 5, wpsyncdata = 10
N7.C0: vmseratio = 0, revisionId = 5, vmse_mode = 1, QCRM_ENABLE = 0
N1.C0: SetupJckSmbCfg: dlyFrms = 15
N3.C0: VmseTrainClockAlign: JCK clkadjcnt =0
N7: SetupJckSmbCfg: JCK wpsyncrcven = 5, wpsyncdata = 10
N1.C0: cwleffective = 8

END - MXB Clock Train                  Time         4912 ms
N1.C0: PreVMSE Training raw cleff = 9, raw cwleff = 7

START - VMSE Train Command
N1.C0: vmseratio = 0, revisionId = 5, vmse_mode = 1, QCRM_ENABLE = 0
N3.C0.B00: HsxCtlXoverInit: invertPiClk = 0x0, RankUsed = 0xFFF, Training = 0x38FFF0A
N1: SetupJckSmbCfg: JCK wpsyncrcven = 5, wpsyncdata = 10
N3.C0.B01: HsxCtlXoverInit: invertPiClk = 0x0, RankUsed = 0xFFF, Training = 0x38FFF27
N3.C0: VmseTrainCmdFine: vmse link sts = 0x4947
N5.C0: SELF CAL 
N5.C0: JckCompCodeCheck: Phase 1 - Comp Code Results
N5.C0: Cycle ron_up ron_eq_up ron_dn ron_eq_dn odt scomp_up scom_dn tcomp_l2h tcomp_h2l   bad_training
N7.C0: SELF CAL 
N7.C0: JckCompCodeCheck: Phase 1 - Comp Code Results
N7.C0: Cycle ron_up ron_eq_up ron_dn ron_eq_dn odt scomp_up scom_dn tcomp_l2h tcomp_h2l   bad_training
N5.C0:  0       42     42       39      33      38     15      15        8       31       0
N1.C0: SELF CAL 
N1.C0: JckCompCodeCheck: Phase 1 - Comp Code Results
N1.C0: Cycle ron_up ron_eq_up ron_dn ron_eq_dn odt scomp_up scom_dn tcomp_l2h tcomp_h2l   bad_training
N5.C0:  1       42     42       39      33      38     15      15        8       31       0
N7.C0:  0       41     41       36      30      38     16      16        9       31       0
N1.C0:  0       41     41       39      28      38     14      14        8       31       0
N5.C0:  2       42     42       39      33      38     15      15        8       31       0
N7.C0:  1       41     41       36      31      38     15      15       10       31       0
N1.C0:  1       42     42       39      30      38     14      14        8       31       0
N5.C0:  3       42     42       39      33      38     15      15        8       31       0
N7.C0:  2       41     41       36      31      38     16      16        8       31       0
N1.C0:  2       41     41       38      30      19     14      14        8       31       0
N5.C0:  4       42     42       39      33      38     15      15        8       31       0
N7.C0:  3       41     41       37      29      38     16      16       10       31       0
N1.C0:  3       42     42       39      30      38     14      14       31        8       0
N5.C0:  5       42     42       39      33      38     15      15        8       31       0
N7.C0:  4       41     41       36      31      38     16      16        2       31       0
N1.C0:  4       42     42       39      30      38     14      14        8       31       0
N5.C0:  6       42     42       39      33      38     15      15        8       31       0
N7.C0:  5       41     41       36      31      38     15      15        6       31       0
N1.C0:  5       41     41       39      29      38     14      14       31        8       0
N5.C0:  7       42     42       39      33      38     15      15        8       31       0
N7.C0:  6       41     41       36      31      38     15      15        4       31       0
N1.C0:  6       41     41       39      28      38     14      14       31        8       0
N5.C0:  8       42     42       39      28      38     15      15        8       31       0
N7.C0:  7       41     41       36      31      38     15      15       10       31       0
N1.C0:  7       41     41       39      29      38     14      14        8       31       0
N5.C0:  9       42     42       39      33      38     15      15        8       31       0
N5.C0: JckCompCodeCheck: Phase 2 - Check for bad ron_up vs average: num = 10, ron_up_avg = 42, ron_up_75avg = 31
N7.C0:  8       41     41       36      31      38     15      15       10       31       0
N5.C0: Cycle ron_up ron_eq_up ron_dn ron_eq_dn odt scomp_up scom_dn tcomp_l2h tcomp_h2l   bad_training
N1.C0:  8       41     41       39      28      38     15      15        8       31       0
N5.C0: JckCompCodeCheck: Phase 3 - Comp Code Limits
N5.C0: ron_up_limitdn   ron_dn_limitup   ron_eq_dn_limtdn  odt_limitdn
N7.C0:  9       41     41       36      31      38     15      15        7       31       0
N5.C0:     26                46                21             24
N7.C0: JckCompCodeCheck: Phase 2 - Check for bad ron_up vs average: num = 10, ron_up_avg = 41, ron_up_75avg = 30
N1.C0:  9       41     41       38      31      38     14      14        8       31       0
N5.C0: JckCompCodeCheck: Phase 3 - SUCCESS
N7.C0: Cycle ron_up ron_eq_up ron_dn ron_eq_dn odt scomp_up scom_dn tcomp_l2h tcomp_h2l   bad_training
N1.C0: JckCompCodeCheck: Phase 2 - Check for bad ron_up vs average: num = 10, ron_up_avg = 41, ron_up_75avg = 30
N5.C0: VmseOverrideJckCompCodes
N7.C0: JckCompCodeCheck: Phase 3 - Comp Code Limits
N1.C0: Cycle ron_up ron_eq_up ron_dn ron_eq_dn odt scomp_up scom_dn tcomp_l2h tcomp_h2l   bad_training
N7.C0: ron_up_limitdn   ron_dn_limitup   ron_eq_dn_limtdn  odt_limitdn
N1.C0: JckCompCodeCheck: Phase 3 - Comp Code Limits
N7.C0:     25                44                20             24
N1.C0: ron_up_limitdn   ron_dn_limitup   ron_eq_dn_limtdn  odt_limitdn
N7.C0: JckCompCodeCheck: Phase 3 - SUCCESS
N1.C0:     26                45                20             24
N7.C0: VmseOverrideJckCompCodes
N1.C0: JckCompCodeCheck: Phase 3 - SUCCESS
N1.C0: VmseOverrideJckCompCodes
N5: SetupJckSmbCfg: JCK VLINFREQ set to: 0x820F1028
N5: SetupJckSmbCfg: PLL is locked.
N5.C2: SetupJckSmbCfg: dlyFrms = 15
N5.C2: cwleffective = 8
Checkpoint Code: Socket 0, 0xB6, 0xA0, 0x0000
N5.C2: PreVMSE Training raw cleff = 9, raw cwleff = 7
N5.C2: vmseratio = 0, revisionId = 5, vmse_mode = 1, QCRM_ENABLE = 0
N7: SetupJckSmbCfg: JCK VLINFREQ set to: 0x820F1028
N5: SetupJckSmbCfg: JCK wpsyncrcven = 5, wpsyncdata = 10
N1: SetupJckSmbCfg: JCK VLINFREQ set to: 0x820F1028
N7: SetupJckSmbCfg: PLL is locked.
N7.C2: SetupJckSmbCfg: dlyFrms = 15
N1: SetupJckSmbCfg: PLL is locked.
N7.C2: cwleffective = 8
N1.C2: SetupJckSmbCfg: dlyFrms = 15
N7.C2: PreVMSE Training raw cleff = 9, raw cwleff = 7
N1.C2: cwleffective = 8
N1.C2: PreVMSE Training raw cleff = 9, raw cwleff = 7
N7.C2: vmseratio = 0, revisionId = 5, vmse_mode = 1, QCRM_ENABLE = 0
N1.C2: vmseratio = 0, revisionId = 5, vmse_mode = 1, QCRM_ENABLE = 0
N7: SetupJckSmbCfg: JCK wpsyncrcven = 5, wpsyncdata = 10
N1: SetupJckSmbCfg: JCK wpsyncrcven = 5, wpsyncdata = 10
N5.C1: SELF CAL 
N5.C1: JckCompCodeCheck: Phase 1 - Comp Code Results
N5.C1: Cycle ron_up ron_eq_up ron_dn ron_eq_dn odt scomp_up scom_dn tcomp_l2h tcomp_h2l   bad_training
N5.C1:  0       41     41       38      29      38     15      15       31        8       0
N7.C1: SELF CAL 
N1.C1: SELF CAL 
N7.C1: JckCompCodeCheck: Phase 1 - Comp Code Results
N1.C1: JckCompCodeCheck: Phase 1 - Comp Code Results
N7.C1: Cycle ron_up ron_eq_up ron_dn ron_eq_dn odt scomp_up scom_dn tcomp_l2h tcomp_h2l   bad_training
N1.C1: Cycle ron_up ron_eq_up ron_dn ron_eq_dn odt scomp_up scom_dn tcomp_l2h tcomp_h2l   bad_training
N5.C1:  1       41     41       38      30      38     15      15       31        8       0
N7.C1:  0       43     43       40      32      39     16      16        8       31       0
N1.C1:  0       42     42       37      31      38     14      14       23       31       0
N5.C1:  2       41     41       38      29      38     15      15       31        8       0
N7.C1:  1       43     43       40      31      39     16      16        8       31       0
N1.C1:  1       42     42       37      31      38     14      14       21       31       0
N5.C1:  3       41     41       37      29      38     15      15       31        8       0
N7.C1:  2       42     42       39      31      39     16      16        8       31       0
N1.C1:  2       42     42       37      31      38     15      15       20       31       0
N5.C1:  4       41     41       38      30      38     15      15       31        8       0
N7.C1:  3       42     42       39      31      39     16      16        8       31       0
N1.C1:  3       42     42       37      31      38     15      15       22       31       0
N5.C1:  5       41     41       38      30      38     15      15       31        8       0
N7.C1:  4       43     43       40      32      39     16      16        8       31       0
N1.C1:  4       42     42       37      31      38     14      14       23       31       0
N5.C1:  6       41     41       38      29      38     15      15       31        8       0
N7.C1:  5       42     42       39      31      39     16      16        8       31       0
N1.C1:  5       42     42       37      31      38     14      14       25       31       0
N5.C1:  7       41     41       38      29      38     15      15       31        8       0
N7.C1:  6       43     43       40      31      39     16      16        8       31       0
N1.C1:  6       42     42       37      31      38     16      16       23       31       0
N5.C1:  8       41     41       38      29      38     15      15       31        8       0
N7.C1:  7       43     43       40      32      39     16      16        8       31       0
N1.C1:  7       42     42       37      31      38     14      14       20       31       0
N5.C1:  9       41     41       38      30      38     15      15       31        8       0
N5.C1: JckCompCodeCheck: Phase 2 - Check for bad ron_up vs average: num = 10, ron_up_avg = 41, ron_up_75avg = 30
N7.C1:  8       42     42       39      31      39     16      16        8       31       0
N5.C1: Cycle ron_up ron_eq_up ron_dn ron_eq_dn odt scomp_up scom_dn tcomp_l2h tcomp_h2l   bad_training
N1.C1:  8       42     42       37      31      38     14      14       21       31       0
N5.C1: JckCompCodeCheck: Phase 3 - Comp Code Limits
N5.C1: ron_up_limitdn   ron_dn_limitup   ron_eq_dn_limtdn  odt_limitdn
N7.C1:  9       43     43       40      32      39     16      16        8       31       0
N5.C1:     25                45                20             24
N7.C1: JckCompCodeCheck: Phase 2 - Check for bad ron_up vs average: num = 10, ron_up_avg = 42, ron_up_75avg = 31
N1.C1:  9       42     42       37      31      38     15      15       22       31       0
N5.C1: JckCompCodeCheck: Phase 3 - SUCCESS
N7.C1: Cycle ron_up ron_eq_up ron_dn ron_eq_dn odt scomp_up scom_dn tcomp_l2h tcomp_h2l   bad_training
N1.C1: JckCompCodeCheck: Phase 2 - Check for bad ron_up vs average: num = 10, ron_up_avg = 42, ron_up_75avg = 31
N5.C1: VmseOverrideJckCompCodes
N7.C1: JckCompCodeCheck: Phase 3 - Comp Code Limits
N1.C1: Cycle ron_up ron_eq_up ron_dn ron_eq_dn odt scomp_up scom_dn tcomp_l2h tcomp_h2l   bad_training
N7.C1: ron_up_limitdn   ron_dn_limitup   ron_eq_dn_limtdn  odt_limitdn
N1.C1: JckCompCodeCheck: Phase 3 - Comp Code Limits
N7.C1:     26                46                21             24
N1.C1: ron_up_limitdn   ron_dn_limitup   ron_eq_dn_limtdn  odt_limitdn
N7.C1: JckCompCodeCheck: Phase 3 - SUCCESS
N1.C1:     26                45                20             24
N7.C1: VmseOverrideJckCompCodes
N1.C1: JckCompCodeCheck: Phase 3 - SUCCESS
N1.C1: VmseOverrideJckCompCodes
N5: Start VMSE training Sequence
N5: ddrCh0.enabled = 1
N5: ddrCh1.enabled = 1
N5: ddrCh2.enabled = 1
N5: ddrCh3.enabled = 1
N5: VMSE0.enabled = 1
N5: VMSE1.enabled = 1
N5: CpgcVmseTraining for VMSE0
N5: Initialize VMSE Channels

START - VMSE Detect DC
N5: HsxVmseCompInit
N5.C0: Skip DC Detect check for CMD results
N5.C0: Skip DC Detect check for CMD results
N7: Start VMSE training Sequence
Checkpoint Code: Socket 0, 0xB6, 0xA0, 0x0000
N5: HsxVmseCompInit
N7: ddrCh0.enabled = 1
N5.C0: VmseDetectDC: SUCCESS
N7: ddrCh1.enabled = 1
Checkpoint Code: Socket 0, 0xB6, 0x10, 0x0000
N5.C0: VmseDetectClock
N7: ddrCh2.enabled = 1
N1: Start VMSE training Sequence
N7: ddrCh3.enabled = 1
N1: ddrCh0.enabled = 1
N7: VMSE0.enabled = 1
N1: ddrCh1.enabled = 1
N7: VMSE1.enabled = 1
N1: ddrCh2.enabled = 1
N7: CpgcVmseTraining for VMSE0
N1: ddrCh3.enabled = 1
N7: Initialize VMSE Channels
N1: VMSE0.enabled = 1

START - VMSE Detect DC
N1: VMSE1.enabled = 1
N7: HsxVmseCompInit
N1: CpgcVmseTraining for VMSE0
Checkpoint Code: Socket 0, 0xB6, 0x11, 0x0000
N1: Initialize VMSE Channels
N7.C0: Skip DC Detect check for CMD results

START - VMSE Detect DC
Checkpoint Code: Socket 0, 0xB6, 0x46, 0x0000
N1: HsxVmseCompInit
Checkpoint Code: Socket 0, 0xB6, 0x80, 0x0000
N7.C0: Skip DC Detect check for CMD results
N7: HsxVmseCompInit
N7.C0: VmseDetectDC: SUCCESS
N7.C0: VmseDetectClock
N1.C0: Skip DC Detect check for CMD results
N1.C0: Skip DC Detect check for CMD results
N1: HsxVmseCompInit
Checkpoint Code: Socket 0, 0xB6, 0x81, 0x0000
N1.C0: VmseDetectDC: SUCCESS
N1.C0: VmseDetectClock
N5.C0: VmseDetectClock: SUCCESS

END - VMSE Detect DC                   Time         230 ms

START - MXB Clock Train
N7.C0: VmseDetectClock: SUCCESS

END - VMSE Detect DC                   Time         218 ms

START - MXB Clock Train
N5.C0: VmseRefVckResync: ddrFreq = 0x2, VMSE_MODE_2_1 = 1, VMSE_PREAMBLE_2UI = 0
N1.C0: VmseDetectClock: SUCCESS

END - VMSE Detect DC                   Time         228 ms

START - MXB Clock Train
N5.C0: VmseRefVckResync: VLINKFREQNXT set to: 0x20F940A
Checkpoint Code: Socket 0, 0xB6, 0x48, 0x0000
N5.C0: VmseTrainClockAlign: JCK clkadjcnt =6

END - MXB Clock Train                  Time         160 ms
N7.C0: VmseRefVckResync: ddrFreq = 0x2, VMSE_MODE_2_1 = 1, VMSE_PREAMBLE_2UI = 0
Checkpoint Code: Socket 0, 0xB6, 0x6C, 0x0000

START - VMSE Train Command
N5.C0.B00: HsxCtlXoverInit: invertPiClk = 0x0, RankUsed = 0xFFF, Training = 0x38FFF07
N7.C0: VmseRefVckResync: VLINKFREQNXT set to: 0x20F940A
N5.C0.B01: HsxCtlXoverInit: invertPiClk = 0x0, RankUsed = 0xFFF, Training = 0x38FFF26
N1.C0: VmseAdjustVckVoc: retrain Clock DCC.
   dcc1_vck = 0x18, dcc2_vck = 0x3F, preampvoc = 0x9
N7.C0: VmseTrainClockAlign: JCK clkadjcnt =5
Checkpoint Code: Socket 0, 0xB6, 0x6C, 0x0000

END - MXB Clock Train                  Time         173 ms

START - VMSE Train Command
N7.C0.B00: HsxCtlXoverInit: invertPiClk = 0x0, RankUsed = 0xFFF, Training = 0x38FFF06
N7.C0.B01: HsxCtlXoverInit: invertPiClk = 0x0, RankUsed = 0xFFF, Training = 0x38FFF25
N1.C0: VmseAdjustVckVoc: retrain Clock DCC.
   dcc1_vck = 0x14, dcc2_vck = 0x3F, preampvoc = 0xA
N5.C0: VmseTrainCmdFine: vmse link sts = 0x4947
Checkpoint Code: Socket 0, 0xB6, 0x6C, 0x0000
N7.C0: VmseTrainCmdFine: vmse link sts = 0x4947
N1.C0: VmseRefVckResync: ddrFreq = 0x2, VMSE_MODE_2_1 = 1, VMSE_PREAMBLE_2UI = 0
N1.C0: VmseRefVckResync: VLINKFREQNXT set to: 0x20F940A
N1.C0: VmseTrainClockAlign: JCK clkadjcnt =4

END - MXB Clock Train                  Time         337 ms

START - VMSE Train Command
Checkpoint Code: Socket 0, 0xB6, 0x4A, 0x0000
N1.C0.B00: HsxCtlXoverInit: invertPiClk = 0x0, RankUsed = 0xFFF, Training = 0x38FFF08
N1.C0.B01: HsxCtlXoverInit: invertPiClk = 0x0, RankUsed = 0xFFF, Training = 0x38FFF26
Checkpoint Code: Socket 0, 0xB6, 0x60, 0x0000
Checkpoint Code: Socket 0, 0xB6, 0x5A, 0x0000
N1.C0: VmseTrainCmdFine: vmse link sts = 0x4947
Entry 0 - TrainDcc - DCCStart: 13, VocStart: 9, DCCFinal: 13, VocFinal: 9
Entry 1 - TrainDcc - DCCStart: 14, VocStart: 9, DCCFinal: 14, VocFinal: 9
N3.C0.S00: VmseCmdFineTraining Final: centerPi = 0x63, PiEw = 0x2E, centerVref = 0x3F, vrefHeight = 0x45
N3.C0.S01: VmseCmdFineTraining Final: centerPi = 0x61, PiEw = 0x2F, centerVref = 0x36, vrefHeight = 0x47
N3.C0.S02: VmseCmdFineTraining Final: centerPi = 0x5D, PiEw = 0x32, centerVref = 0x3A, vrefHeight = 0x45
N3.C0.S03: VmseCmdFineTraining Final: centerPi = 0x62, PiEw = 0x31, centerVref = 0x39, vrefHeight = 0x47
N3.C0.S04: VmseCmdFineTraining Final: centerPi = 0x59, PiEw = 0x30, centerVref = 0x39, vrefHeight = 0x45
N3.C0.S05: VmseCmdFineTraining Final: centerPi = 0x5A, PiEw = 0x30, centerVref = 0x3E, vrefHeight = 0x43
N3.C0.S06: VmseCmdFineTraining Final: centerPi = 0x5B, PiEw = 0x2F, centerVref = 0x40, vrefHeight = 0x41
N3.C0.S07: VmseCmdFineTraining Final: centerPi = 0x5F, PiEw = 0x31, centerVref = 0x3B, vrefHeight = 0x49
N3.C0.S08: VmseCmdFineTraining Final: centerPi = 0x5B, PiEw = 0x31, centerVref = 0x40, vrefHeight = 0x45
N3.C0.S09: VmseCmdFineTraining Final: centerPi = 0x5F, PiEw = 0x31, centerVref = 0x39, vrefHeight = 0x43
N3.C0.S10: VmseCmdFineTraining Final: centerPi = 0x5F, PiEw = 0x2F, centerVref = 0x38, vrefHeight = 0x43
N3.C0.S11: VmseCmdFineTraining Final: centerPi = 0x58, PiEw = 0x30, centerVref = 0x37, vrefHeight = 0x47
N3.C0.S12: VmseCmdFineTraining Final: centerPi = 0x63, PiEw = 0x32, centerVref = 0x37, vrefHeight = 0x49
N3.C0.S13: VmseCmdFineTraining Final: centerPi = 0x5A, PiEw = 0x31, centerVref = 0x36, vrefHeight = 0x43
N3.C0.S14: VmseCmdFineTraining Final: centerPi = 0x60, PiEw = 0x34, centerVref = 0x46, vrefHeight = 0x49
N3.C0.S15: VmseCmdFineTraining Final: centerPi = 0x64, PiEw = 0x31, centerVref = 0x37, vrefHeight = 0x49
N3.C0.S16: VmseCmdFineTraining Final: centerPi = 0x5B, PiEw = 0x31, centerVref = 0x38, vrefHeight = 0x41

END - VMSE Train Command               Time         7426 ms

START - VMSE Train Read Leveling
N3.C0: VmseReadLevelFineSetup: Initial RT = 101, Initial IO Latency = 0, Initial IO Comp = 15
N3.C0: VmseRLWLFineSearchAll: Entry
N3.C0: FINE READ LEVEL DELAY
N3.C0.S00: RCVEN DELAY = 149
N3.C0.S01: RCVEN DELAY = 111
N3.C0.S02: RCVEN DELAY = 28
N3.C0.S03: RCVEN DELAY = 135
N3.C0.S04: RCVEN DELAY = 93
N3.C0.S05: RCVEN DELAY = 107
N3.C0.S06: RCVEN DELAY = 103
N3.C0.S07: RCVEN DELAY = 91
N3.C0.S08: RCVEN DELAY = 40
N3.C0.S00: READ LEVEL: FINAL RCVEN DELAY (both nibbles) = 247
N3.C0.S01: READ LEVEL: FINAL RCVEN DELAY (both nibbles) = 208
N3.C0.S02: READ LEVEL: FINAL RCVEN DELAY (both nibbles) = 256
N3.C0.S03: READ LEVEL: FINAL RCVEN DELAY (both nibbles) = 230
N3.C0.S04: READ LEVEL: FINAL RCVEN DELAY (both nibbles) = 190
N3.C0.S05: READ LEVEL: FINAL RCVEN DELAY (both nibbles) = 205
N3.C0.S06: READ LEVEL: FINAL RCVEN DELAY (both nibbles) = 199
N3.C0.S07: READ LEVEL: FINAL RCVEN DELAY (both nibbles) = 188
N3.C0.S08: READ LEVEL: FINAL RCVEN DELAY (both nibbles) = 266
N3.C0.D0.S09: READ LEVEL: FINAL RT (all ranks) = 85, FINAL IO LATENCY (all ranks) = 4
N3.C0.D1.S09: READ LEVEL: FINAL RT (all ranks) = 85, FINAL IO LATENCY (all ranks) = 4

END - VMSE Train Read Leveling         Time         264 ms

START - VMSE Train Read
Entry 0 - TrainDcc - DCCStart: 20, VocStart: 18, DCCFinal: 28, VocFinal: 18
Entry 1 - TrainDcc - DCCStart: 51, VocStart: 18, DCCFinal: 27, VocFinal: 18
Entry 0 - TrainDcc - DCCStart: 14, VocStart: 11, DCCFinal: 14, VocFinal: 11
Entry 1 - TrainDcc - DCCStart: 45, VocStart: 11, DCCFinal: 45, VocFinal: 11
Entry 0 - TrainDcc - DCCStart: 11, VocStart: 10, DCCFinal: 11, VocFinal: 10
Entry 1 - TrainDcc - DCCStart: 46, VocStart: 10, DCCFinal: 46, VocFinal: 10
N5.C0.S00: VmseCmdFineTraining Final: centerPi = 0x60, PiEw = 0x31, centerVref = 0x3C, vrefHeight = 0x43
N5.C0.S01: VmseCmdFineTraining Final: centerPi = 0x5F, PiEw = 0x31, centerVref = 0x36, vrefHeight = 0x47
N5.C0.S02: VmseCmdFineTraining Final: centerPi = 0x5C, PiEw = 0x32, centerVref = 0x3B, vrefHeight = 0x47
N5.C0.S03: VmseCmdFineTraining Final: centerPi = 0x5F, PiEw = 0x31, centerVref = 0x3A, vrefHeight = 0x45
N5.C0.S04: VmseCmdFineTraining Final: centerPi = 0x56, PiEw = 0x31, centerVref = 0x3E, vrefHeight = 0x41
N5.C0.S05: VmseCmdFineTraining Final: centerPi = 0x58, PiEw = 0x2E, centerVref = 0x39, vrefHeight = 0x43
N5.C0.S06: VmseCmdFineTraining Final: centerPi = 0x5A, PiEw = 0x30, centerVref = 0x3A, vrefHeight = 0x43
N5.C0.S07: VmseCmdFineTraining Final: centerPi = 0x5C, PiEw = 0x31, centerVref = 0x3D, vrefHeight = 0x47
N5.C0.S08: VmseCmdFineTraining Final: centerPi = 0x58, PiEw = 0x32, centerVref = 0x40, vrefHeight = 0x45
N5.C0.S09: VmseCmdFineTraining Final: centerPi = 0x5D, PiEw = 0x31, centerVref = 0x38, vrefHeight = 0x43
N5.C0.S10: VmseCmdFineTraining Final: centerPi = 0x5D, PiEw = 0x2F, centerVref = 0x3B, vrefHeight = 0x43
N5.C0.S11: VmseCmdFineTraining Final: centerPi = 0x58, PiEw = 0x2F, centerVref = 0x38, vrefHeight = 0x47
N5.C0.S12: VmseCmdFineTraining Final: centerPi = 0x5E, PiEw = 0x30, centerVref = 0x3D, vrefHeight = 0x47
N5.C0.S13: VmseCmdFineTraining Final: centerPi = 0x59, PiEw = 0x2F, centerVref = 0x3A, vrefHeight = 0x41
N5.C0.S14: VmseCmdFineTraining Final: centerPi = 0x5E, PiEw = 0x33, centerVref = 0x36, vrefHeight = 0x45
N5.C0.S15: VmseCmdFineTraining Final: centerPi = 0x60, PiEw = 0x2F, centerVref = 0x3B, vrefHeight = 0x45
N5.C0.S16: VmseCmdFineTraining Final: centerPi = 0x5B, PiEw = 0x2F, centerVref = 0x3F, vrefHeight = 0x43

END - VMSE Train Command               Time         6613 ms

START - VMSE Train Read Leveling
N5.C0: VmseReadLevelFineSetup: Initial RT = 101, Initial IO Latency = 0, Initial IO Comp = 15
N5.C0: VmseRLWLFineSearchAll: Entry
N5.C0: FINE READ LEVEL DELAY
N5.C0.S00: RCVEN DELAY = 120
N5.C0.S01: RCVEN DELAY = 87
N5.C0.S02: RCVEN DELAY = 120
N5.C0.S03: RCVEN DELAY = 100
N5.C0.S04: RCVEN DELAY = 71
N5.C0.S05: RCVEN DELAY = 80
N5.C0.S06: RCVEN DELAY = 76
N5.C0.S07: RCVEN DELAY = 65
N5.C0.S08: RCVEN DELAY = 76
N5.C0.S00: READ LEVEL: FINAL RCVEN DELAY (both nibbles) = 217
N5.C0.S01: READ LEVEL: FINAL RCVEN DELAY (both nibbles) = 185
N5.C0.S02: READ LEVEL: FINAL RCVEN DELAY (both nibbles) = 216
N7.C0.S00: VmseCmdFineTraining Final: centerPi = 0x63, PiEw = 0x2F, centerVref = 0x37, vrefHeight = 0x45
N5.C0.S03: READ LEVEL: FINAL RCVEN DELAY (both nibbles) = 196
N7.C0.S01: VmseCmdFineTraining Final: centerPi = 0x62, PiEw = 0x30, centerVref = 0x34, vrefHeight = 0x4B
N5.C0.S04: READ LEVEL: FINAL RCVEN DELAY (both nibbles) = 170
N7.C0.S02: VmseCmdFineTraining Final: centerPi = 0x5D, PiEw = 0x35, centerVref = 0x3B, vrefHeight = 0x45
N5.C0.S05: READ LEVEL: FINAL RCVEN DELAY (both nibbles) = 178
N7.C0.S03: VmseCmdFineTraining Final: centerPi = 0x62, PiEw = 0x32, centerVref = 0x34, vrefHeight = 0x47
N5.C0.S06: READ LEVEL: FINAL RCVEN DELAY (both nibbles) = 174
N7.C0.S04: VmseCmdFineTraining Final: centerPi = 0x5A, PiEw = 0x31, centerVref = 0x35, vrefHeight = 0x47
N5.C0.S07: READ LEVEL: FINAL RCVEN DELAY (both nibbles) = 163
N7.C0.S05: VmseCmdFineTraining Final: centerPi = 0x5B, PiEw = 0x2F, centerVref = 0x3B, vrefHeight = 0x45
N5.C0.S08: READ LEVEL: FINAL RCVEN DELAY (both nibbles) = 174
N7.C0.S06: VmseCmdFineTraining Final: centerPi = 0x5C, PiEw = 0x2F, centerVref = 0x38, vrefHeight = 0x47
N5.C0.D0.S09: READ LEVEL: FINAL RT (all ranks) = 83, FINAL IO LATENCY (all ranks) = 2
N7.C0.S07: VmseCmdFineTraining Final: centerPi = 0x5F, PiEw = 0x32, centerVref = 0x39, vrefHeight = 0x49
N5.C0.D1.S09: READ LEVEL: FINAL RT (all ranks) = 83, FINAL IO LATENCY (all ranks) = 2
N7.C0.S08: VmseCmdFineTraining Final: centerPi = 0x58, PiEw = 0x31, centerVref = 0x38, vrefHeight = 0x41

END - VMSE Train Read Leveling         Time         353 ms
N7.C0.S09: VmseCmdFineTraining Final: centerPi = 0x5E, PiEw = 0x31, centerVref = 0x39, vrefHeight = 0x47

START - VMSE Train Read
N7.C0.S10: VmseCmdFineTraining Final: centerPi = 0x5C, PiEw = 0x2F, centerVref = 0x3C, vrefHeight = 0x45
N7.C0.S11: VmseCmdFineTraining Final: centerPi = 0x58, PiEw = 0x30, centerVref = 0x38, vrefHeight = 0x47
N7.C0.S12: VmseCmdFineTraining Final: centerPi = 0x5E, PiEw = 0x30, centerVref = 0x37, vrefHeight = 0x49
N7.C0.S13: VmseCmdFineTraining Final: centerPi = 0x57, PiEw = 0x30, centerVref = 0x3C, vrefHeight = 0x43
N7.C0.S14: VmseCmdFineTraining Final: centerPi = 0x5C, PiEw = 0x33, centerVref = 0x3C, vrefHeight = 0x47
N7.C0.S15: VmseCmdFineTraining Final: centerPi = 0x5F, PiEw = 0x2F, centerVref = 0x39, vrefHeight = 0x47
N7.C0.S16: VmseCmdFineTraining Final: centerPi = 0x5A, PiEw = 0x2E, centerVref = 0x34, vrefHeight = 0x49
N1.C0.S00: VmseCmdFineTraining Final: centerPi = 0x66, PiEw = 0x31, centerVref = 0x39, vrefHeight = 0x45
N1.C0.S01: VmseCmdFineTraining Final: centerPi = 0x62, PiEw = 0x30, centerVref = 0x3B, vrefHeight = 0x47
N1.C0.S02: VmseCmdFineTraining Final: centerPi = 0x5F, PiEw = 0x35, centerVref = 0x38, vrefHeight = 0x49
N1.C0.S03: VmseCmdFineTraining Final: centerPi = 0x62, PiEw = 0x32, centerVref = 0x37, vrefHeight = 0x45
N1.C0.S04: VmseCmdFineTraining Final: centerPi = 0x58, PiEw = 0x2F, centerVref = 0x40, vrefHeight = 0x45
N1.C0.S05: VmseCmdFineTraining Final: centerPi = 0x5C, PiEw = 0x2F, centerVref = 0x39, vrefHeight = 0x45
N1.C0.S06: VmseCmdFineTraining Final: centerPi = 0x5B, PiEw = 0x30, centerVref = 0x3D, vrefHeight = 0x47
N1.C0.S07: VmseCmdFineTraining Final: centerPi = 0x62, PiEw = 0x32, centerVref = 0x39, vrefHeight = 0x47
N1.C0.S08: VmseCmdFineTraining Final: centerPi = 0x57, PiEw = 0x31, centerVref = 0x3B, vrefHeight = 0x41
N1.C0.S09: VmseCmdFineTraining Final: centerPi = 0x5C, PiEw = 0x30, centerVref = 0x3B, vrefHeight = 0x43
N1.C0.S10: VmseCmdFineTraining Final: centerPi = 0x5B, PiEw = 0x2D, centerVref = 0x34, vrefHeight = 0x3F
N1.C0.S11: VmseCmdFineTraining Final: centerPi = 0x56, PiEw = 0x31, centerVref = 0x37, vrefHeight = 0x45

END - VMSE Train Command               Time         7157 ms
N1.C0.S12: VmseCmdFineTraining Final: centerPi = 0x5D, PiEw = 0x2E, centerVref = 0x3C, vrefHeight = 0x47

START - VMSE Train Read Leveling
N1.C0.S13: VmseCmdFineTraining Final: centerPi = 0x56, PiEw = 0x30, centerVref = 0x3C, vrefHeight = 0x3F
N1.C0.S14: VmseCmdFineTraining Final: centerPi = 0x5F, PiEw = 0x34, centerVref = 0x3A, vrefHeight = 0x49
N1.C0.S15: VmseCmdFineTraining Final: centerPi = 0x5E, PiEw = 0x30, centerVref = 0x39, vrefHeight = 0x45
N1.C0.S16: VmseCmdFineTraining Final: centerPi = 0x5A, PiEw = 0x2E, centerVref = 0x38, vrefHeight = 0x47
N7.C0: VmseReadLevelFineSetup: Initial RT = 101, Initial IO Latency = 0, Initial IO Comp = 15
N7.C0: VmseRLWLFineSearchAll: Entry
N7.C0: FINE READ LEVEL DELAY
N7.C0.S00: RCVEN DELAY = 128
N7.C0.S01: RCVEN DELAY = 92
N7.C0.S02: RCVEN DELAY = 137
N7.C0.S03: RCVEN DELAY = 113
N7.C0.S04: RCVEN DELAY = 77
N7.C0.S05: RCVEN DELAY = 89
N7.C0.S06: RCVEN DELAY = 89
N7.C0.S07: RCVEN DELAY = 71
N7.C0.S08: RCVEN DELAY = 82
N7.C0.S00: READ LEVEL: FINAL RCVEN DELAY (both nibbles) = 98
N7.C0.S01: READ LEVEL: FINAL RCVEN DELAY (both nibbles) = 60
N7.C0.S02: READ LEVEL: FINAL RCVEN DELAY (both nibbles) = 105

END - VMSE Train Command               Time         7189 ms
N7.C0.S03: READ LEVEL: FINAL RCVEN DELAY (both nibbles) = 83

START - VMSE Train Read Leveling
N7.C0.S04: READ LEVEL: FINAL RCVEN DELAY (both nibbles) = 48
Checkpoint Code: Socket 0, 0xB6, 0x4E, 0x0000
N7.C0.S05: READ LEVEL: FINAL RCVEN DELAY (both nibbles) = 59
N7.C0.S06: READ LEVEL: FINAL RCVEN DELAY (both nibbles) = 59
N7.C0.S07: READ LEVEL: FINAL RCVEN DELAY (both nibbles) = 41
N7.C0.S08: READ LEVEL: FINAL RCVEN DELAY (both nibbles) = 52
N7.C0.D0.S09: READ LEVEL: FINAL RT (all ranks) = 83, FINAL IO LATENCY (all ranks) = 2
N7.C0.D1.S09: READ LEVEL: FINAL RT (all ranks) = 83, FINAL IO LATENCY (all ranks) = 2

END - VMSE Train Read Leveling         Time         279 ms

START - VMSE Train Read
N1.C0: VmseReadLevelFineSetup: Initial RT = 101, Initial IO Latency = 0, Initial IO Comp = 15
N1.C0: VmseRLWLFineSearchAll: Entry
N1.C0: FINE READ LEVEL DELAY
N1.C0.S00: RCVEN DELAY = 131
N1.C0.S01: RCVEN DELAY = 95

END - VMSE Train Read                  Time         3956 ms
N1.C0.S02: RCVEN DELAY = 139

START - VMSE Train Level Tx DQS DCC
N1.C0.S03: RCVEN DELAY = 120
N1.C0.S04: RCVEN DELAY = 80
N3.C0: VmseLevelTxDqsDccExecute: MXB DQS DCC Finished Successfully
N1.C0.S05: RCVEN DELAY = 92

END - VMSE Train Level Tx DQS DCC      Time         13 ms
N1.C0.S06: RCVEN DELAY = 87

START - VMSE Train Write Leveling
N1.C0.S07: RCVEN DELAY = 75
N3.C0: VmseWriteLevelFineSetup: Set push to data delay = 6, Global TX DQS delay = 0
N1.C0.S08: RCVEN DELAY = 86
N3.C0: VmseRLWLFineSearchAll: Entry
N1.C0.S00: READ LEVEL: FINAL RCVEN DELAY (both nibbles) = 100
N3.C0: FINE WRITE LEVEL DELAY
N1.C0.S01: READ LEVEL: FINAL RCVEN DELAY (both nibbles) = 66
N3.C0.S00: TX DQS DELAY = 50
N1.C0.S02: READ LEVEL: FINAL RCVEN DELAY (both nibbles) = 105
N3.C0.S01: TX DQS DELAY = 91
N1.C0.S03: READ LEVEL: FINAL RCVEN DELAY (both nibbles) = 89
N3.C0.S02: TX DQS DELAY = 49
N1.C0.S04: READ LEVEL: FINAL RCVEN DELAY (both nibbles) = 50
N3.C0.S03: TX DQS DELAY = 67
N1.C0.S05: READ LEVEL: FINAL RCVEN DELAY (both nibbles) = 60
N3.C0.S04: TX DQS DELAY = 104
N1.C0.S06: READ LEVEL: FINAL RCVEN DELAY (both nibbles) = 57
N3.C0.S05: TX DQS DELAY = 94
N1.C0.S07: READ LEVEL: FINAL RCVEN DELAY (both nibbles) = 45
N3.C0.S06: TX DQS DELAY = 96
N1.C0.S08: READ LEVEL: FINAL RCVEN DELAY (both nibbles) = 57
N3.C0.S07: TX DQS DELAY = 112
N1.C0.D0.S09: READ LEVEL: FINAL RT (all ranks) = 83, FINAL IO LATENCY (all ranks) = 2
N3.C0.S08: TX DQS DELAY = 157
N1.C0.D1.S09: READ LEVEL: FINAL RT (all ranks) = 83, FINAL IO LATENCY (all ranks) = 2
N3.C0: VmseWriteLevelCoarseSetup: Set push to data delay = 6, Global TX DQS delay = 0

END - VMSE Train Read Leveling         Time         345 ms
N3.C0: VmseWriteLevelCoarseExecute

START - VMSE Train Read
N3.C0: VmseWLCoarseUpdatePD: New push to data delay = 6, New global TxDQS delay = 1
Checkpoint Code: Socket 0, 0xB6, 0x50, 0x0000
N3.C0: VmseWLCoarseUpdatePD: New push to data delay = 7, New global TxDQS delay = 0
N3.C0: VmseWLCoarseUpdatePD: New push to data delay = 7, New global TxDQS delay = 1
N3.C0: VmseWLCoarseUpdatePD: New push to data delay = 8, New global TxDQS delay = 0
N3.C0: VmseWLCoarseUpdatePD: New push to data delay = 8, New global TxDQS delay = 1
N3.C0.S00: FINAL TX DQS BEFORE TxFIFO CHECK = 148
N3.C0.S01: FINAL TX DQS BEFORE TxFIFO CHECK = 187
N3.C0.S02: FINAL TX DQS BEFORE TxFIFO CHECK = 146
N3.C0.S03: FINAL TX DQS BEFORE TxFIFO CHECK = 165
N3.C0.S04: FINAL TX DQS BEFORE TxFIFO CHECK = 203
N3.C0.S05: FINAL TX DQS BEFORE TxFIFO CHECK = 193
N3.C0.S06: FINAL TX DQS BEFORE TxFIFO CHECK = 195
N3.C0.S07: FINAL TX DQS BEFORE TxFIFO CHECK = 209
N3.C0.S08: FINAL TX DQS BEFORE TxFIFO CHECK = 255
N3.C0: ResolveTxFIFOPtrSeparation: Smallest PI (146) < MIN ALLOWED DELAY (176) 
N3.C0: VmseIncTxFifoPtrSeparation: New push to data delay = 7
N3.C0.S00: VmseIncTxFifoPtrSeparation: pi adjustment = 256, FINAL TX DQS DELAY = 404
N3.C0.S01: VmseIncTxFifoPtrSeparation: pi adjustment = 256, FINAL TX DQS DELAY = 443
N3.C0.S02: VmseIncTxFifoPtrSeparation: pi adjustment = 256, FINAL TX DQS DELAY = 402
N3.C0.S03: VmseIncTxFifoPtrSeparation: pi adjustment = 256, FINAL TX DQS DELAY = 421
N3.C0.S04: VmseIncTxFifoPtrSeparation: pi adjustment = 256, FINAL TX DQS DELAY = 459
N3.C0.S05: VmseIncTxFifoPtrSeparation: pi adjustment = 256, FINAL TX DQS DELAY = 449
N3.C0.S06: VmseIncTxFifoPtrSeparation: pi adjustment = 256, FINAL TX DQS DELAY = 451
N3.C0.S07: VmseIncTxFifoPtrSeparation: pi adjustment = 256, FINAL TX DQS DELAY = 465
N3.C0.S08: VmseIncTxFifoPtrSeparation: pi adjustment = 256, FINAL TX DQS DELAY = 511

END - VMSE Train Write Leveling        Time         347 ms

START - VMSE Train Write
Entry 0 - TrainDcc - DCCStart: 2, VocStart: 11, DCCFinal: 10, VocFinal: 11
Entry 1 - TrainDcc - DCCStart: 14, VocStart: 16, DCCFinal: 14, VocFinal: 16
Entry 2 - TrainDcc - DCCStart: 21, VocStart: 9, DCCFinal: 21, VocFinal: 9
Entry 3 - TrainDcc - DCCStart: 13, VocStart: 12, DCCFinal: 13, VocFinal: 12
Entry 4 - TrainDcc - DCCStart: 8, VocStart: 7, DCCFinal: 8, VocFinal: 16
Entry 5 - TrainDcc - DCCStart: 9, VocStart: 16, DCCFinal: 9, VocFinal: 16
Entry 6 - TrainDcc - DCCStart: 2, VocStart: 10, DCCFinal: 2, VocFinal: 19
Entry 7 - TrainDcc - DCCStart: 8, VocStart: 8, DCCFinal: 8, VocFinal: 8
Entry 8 - TrainDcc - DCCStart: 14, VocStart: 12, DCCFinal: 14, VocFinal: 12
N3.C0.S00: VmseWriteTraining Final: centerPi = 0x3E, PiEw = 0x29, centerVref = 0x45, vrefHeight = 0x28
N3.C0.S01: VmseWriteTraining Final: centerPi = 0x3F, PiEw = 0x25, centerVref = 0x3C, vrefHeight = 0x2A
N3.C0.S02: VmseWriteTraining Final: centerPi = 0x3D, PiEw = 0x26, centerVref = 0x3F, vrefHeight = 0x2A
N3.C0.S03: VmseWriteTraining Final: centerPi = 0x39, PiEw = 0x29, centerVref = 0x41, vrefHeight = 0x2A
N3.C0.S04: VmseWriteTraining Final: centerPi = 0x42, PiEw = 0x28, centerVref = 0x3D, vrefHeight = 0x28
N3.C0.S05: VmseWriteTraining Final: centerPi = 0x3F, PiEw = 0x2A, centerVref = 0x41, vrefHeight = 0x28
N3.C0.S06: VmseWriteTraining Final: centerPi = 0x3F, PiEw = 0x29, centerVref = 0x3E, vrefHeight = 0x28
N3.C0.S07: VmseWriteTraining Final: centerPi = 0x43, PiEw = 0x27, centerVref = 0x41, vrefHeight = 0x2C
N3.C0.S08: VmseWriteTraining Final: centerPi = 0x3D, PiEw = 0x29, centerVref = 0x42, vrefHeight = 0x2E
N3.C0.S09: VmseWriteTraining Final: centerPi = 0x3B, PiEw = 0x29, centerVref = 0x3D, vrefHeight = 0x2C
N3.C0.S10: VmseWriteTraining Final: centerPi = 0x39, PiEw = 0x27, centerVref = 0x3E, vrefHeight = 0x2E
N3.C0.S11: VmseWriteTraining Final: centerPi = 0x38, PiEw = 0x28, centerVref = 0x3E, vrefHeight = 0x2E
N3.C0.S12: VmseWriteTraining Final: centerPi = 0x42, PiEw = 0x24, centerVref = 0x3B, vrefHeight = 0x2C
N3.C0.S13: VmseWriteTraining Final: centerPi = 0x3E, PiEw = 0x27, centerVref = 0x40, vrefHeight = 0x2A
N3.C0.S14: VmseWriteTraining Final: centerPi = 0x3D, PiEw = 0x22, centerVref = 0x3F, vrefHeight = 0x2C
N3.C0.S15: VmseWriteTraining Final: centerPi = 0x3E, PiEw = 0x27, centerVref = 0x3F, vrefHeight = 0x2A
N3.C0.S16: VmseWriteTraining Final: centerPi = 0x3E, PiEw = 0x29, centerVref = 0x3F, vrefHeight = 0x28
N3.C0.S17: VmseWriteTraining Final: centerPi = 0x3C, PiEw = 0x25, centerVref = 0x3F, vrefHeight = 0x28
N3.C0.S18: VmseWriteTraining Final: centerPi = 0x3A, PiEw = 0x24, centerVref = 0x3D, vrefHeight = 0x26
N3.C0.S19: VmseWriteTraining Final: centerPi = 0x38, PiEw = 0x27, centerVref = 0x3C, vrefHeight = 0x28
N3.C0.S20: VmseWriteTraining Final: centerPi = 0x40, PiEw = 0x25, centerVref = 0x3E, vrefHeight = 0x28
N3.C0.S21: VmseWriteTraining Final: centerPi = 0x3F, PiEw = 0x27, centerVref = 0x43, vrefHeight = 0x26
N3.C0.S22: VmseWriteTraining Final: centerPi = 0x3F, PiEw = 0x27, centerVref = 0x3E, vrefHeight = 0x28
N3.C0.S23: VmseWriteTraining Final: centerPi = 0x3F, PiEw = 0x27, centerVref = 0x40, vrefHeight = 0x26
N3.C0.S24: VmseWriteTraining Final: centerPi = 0x3C, PiEw = 0x29, centerVref = 0x3E, vrefHeight = 0x26
N3.C0.S25: VmseWriteTraining Final: centerPi = 0x3B, PiEw = 0x26, centerVref = 0x3A, vrefHeight = 0x28
N3.C0.S26: VmseWriteTraining Final: centerPi = 0x3D, PiEw = 0x26, centerVref = 0x3D, vrefHeight = 0x2C
N3.C0.S27: VmseWriteTraining Final: centerPi = 0x3B, PiEw = 0x2C, centerVref = 0x3A, vrefHeight = 0x2A
N3.C0.S28: VmseWriteTraining Final: centerPi = 0x42, PiEw = 0x23, centerVref = 0x3D, vrefHeight = 0x2A
N3.C0.S29: VmseWriteTraining Final: centerPi = 0x3F, PiEw = 0x28, centerVref = 0x3F, vrefHeight = 0x28
N3.C0.S30: VmseWriteTraining Final: centerPi = 0x41, PiEw = 0x26, centerVref = 0x3F, vrefHeight = 0x2C
N3.C0.S31: VmseWriteTraining Final: centerPi = 0x40, PiEw = 0x26, centerVref = 0x41, vrefHeight = 0x2A
N3.C0.S32: VmseWriteTraining Final: centerPi = 0x3E, PiEw = 0x29, centerVref = 0x3E, vrefHeight = 0x2A
N3.C0.S33: VmseWriteTraining Final: centerPi = 0x3D, PiEw = 0x28, centerVref = 0x3E, vrefHeight = 0x2C
N3.C0.S34: VmseWriteTraining Final: centerPi = 0x3C, PiEw = 0x27, centerVref = 0x38, vrefHeight = 0x2E
N3.C0.S35: VmseWriteTraining Final: centerPi = 0x39, PiEw = 0x2B, centerVref = 0x3E, vrefHeight = 0x2E
N3.C0.S36: VmseWriteTraining Final: centerPi = 0x42, PiEw = 0x29, centerVref = 0x3B, vrefHeight = 0x2C
N3.C0.S37: VmseWriteTraining Final: centerPi = 0x41, PiEw = 0x24, centerVref = 0x41, vrefHeight = 0x28
N3.C0.S38: VmseWriteTraining Final: centerPi = 0x3D, PiEw = 0x27, centerVref = 0x40, vrefHeight = 0x2C
N3.C0.S39: VmseWriteTraining Final: centerPi = 0x41, PiEw = 0x28, centerVref = 0x41, vrefHeight = 0x2C
N3.C0.S40: VmseWriteTraining Final: centerPi = 0x3D, PiEw = 0x2A, centerVref = 0x42, vrefHeight = 0x2A
N3.C0.S41: VmseWriteTraining Final: centerPi = 0x3D, PiEw = 0x28, centerVref = 0x3E, vrefHeight = 0x2A
N3.C0.S42: VmseWriteTraining Final: centerPi = 0x3D, PiEw = 0x25, centerVref = 0x3C, vrefHeight = 0x2A
N3.C0.S43: VmseWriteTraining Final: centerPi = 0x3D, PiEw = 0x22, centerVref = 0x39, vrefHeight = 0x2A
N3.C0.S44: VmseWriteTraining Final: centerPi = 0x40, PiEw = 0x26, centerVref = 0x45, vrefHeight = 0x28
N3.C0.S45: VmseWriteTraining Final: centerPi = 0x40, PiEw = 0x25, centerVref = 0x3E, vrefHeight = 0x26
N3.C0.S46: VmseWriteTraining Final: centerPi = 0x3F, PiEw = 0x20, centerVref = 0x43, vrefHeight = 0x28
N3.C0.S47: VmseWriteTraining Final: centerPi = 0x3F, PiEw = 0x24, centerVref = 0x3C, vrefHeight = 0x2A
N3.C0.S48: VmseWriteTraining Final: centerPi = 0x3B, PiEw = 0x25, centerVref = 0x42, vrefHeight = 0x24
N3.C0.S49: VmseWriteTraining Final: centerPi = 0x42, PiEw = 0x25, centerVref = 0x3C, vrefHeight = 0x2E
N3.C0.S50: VmseWriteTraining Final: centerPi = 0x3B, PiEw = 0x29, centerVref = 0x40, vrefHeight = 0x28
N3.C0.S51: VmseWriteTraining Final: centerPi = 0x38, PiEw = 0x28, centerVref = 0x3C, vrefHeight = 0x28
N3.C0.S52: VmseWriteTraining Final: centerPi = 0x42, PiEw = 0x23, centerVref = 0x40, vrefHeight = 0x28
N3.C0.S53: VmseWriteTraining Final: centerPi = 0x44, PiEw = 0x2A, centerVref = 0x3E, vrefHeight = 0x2C
N3.C0.S54: VmseWriteTraining Final: centerPi = 0x41, PiEw = 0x23, centerVref = 0x3C, vrefHeight = 0x2A
N3.C0.S55: VmseWriteTraining Final: centerPi = 0x42, PiEw = 0x25, centerVref = 0x3F, vrefHeight = 0x2A
N3.C0.S56: VmseWriteTraining Final: centerPi = 0x3C, PiEw = 0x27, centerVref = 0x3E, vrefHeight = 0x26
N3.C0.S57: VmseWriteTraining Final: centerPi = 0x3D, PiEw = 0x26, centerVref = 0x3D, vrefHeight = 0x2C
N3.C0.S58: VmseWriteTraining Final: centerPi = 0x3E, PiEw = 0x26, centerVref = 0x3B, vrefHeight = 0x2E
N3.C0.S59: VmseWriteTraining Final: centerPi = 0x39, PiEw = 0x22, centerVref = 0x3E, vrefHeight = 0x2C
N3.C0.S60: VmseWriteTraining Final: centerPi = 0x43, PiEw = 0x23, centerVref = 0x3A, vrefHeight = 0x2A
N3.C0.S61: VmseWriteTraining Final: centerPi = 0x41, PiEw = 0x23, centerVref = 0x44, vrefHeight = 0x28
N3.C0.S62: VmseWriteTraining Final: centerPi = 0x41, PiEw = 0x26, centerVref = 0x3D, vrefHeight = 0x2C
N3.C0.S63: VmseWriteTraining Final: centerPi = 0x40, PiEw = 0x2B, centerVref = 0x3F, vrefHeight = 0x2C
N3.C0.S64: VmseWriteTraining Final: centerPi = 0x3D, PiEw = 0x2A, centerVref = 0x42, vrefHeight = 0x2A
N3.C0.S65: VmseWriteTraining Final: centerPi = 0x40, PiEw = 0x20, centerVref = 0x40, vrefHeight = 0x2A
N3.C0.S66: VmseWriteTraining Final: centerPi = 0x3E, PiEw = 0x24, centerVref = 0x3B, vrefHeight = 0x2C
N3.C0.S67: VmseWriteTraining Final: centerPi = 0x3B, PiEw = 0x2C, centerVref = 0x41, vrefHeight = 0x2C
N3.C0.S68: VmseWriteTraining Final: centerPi = 0x43, PiEw = 0x28, centerVref = 0x3C, vrefHeight = 0x2A
N3.C0.S69: VmseWriteTraining Final: centerPi = 0x3F, PiEw = 0x25, centerVref = 0x46, vrefHeight = 0x28
N3.C0.S70: VmseWriteTraining Final: centerPi = 0x41, PiEw = 0x24, centerVref = 0x3D, vrefHeight = 0x28
N3.C0.S71: VmseWriteTraining Final: centerPi = 0x42, PiEw = 0x28, centerVref = 0x3F, vrefHeight = 0x2C

END - VMSE Train Write                 Time         2227 ms
N3: 
Total VMSE trainings latency = 29000 ms
N3: CpgcVmseTraining for VMSE1
N3: Initialize VMSE Channels

START - VMSE Detect DC
N3: HsxVmseCompInit
N3.C1: Skip DC Detect check for CMD results
N3.C1: Skip DC Detect check for CMD results
N3: HsxVmseCompInit
N3.C1: VmseDetectDC: SUCCESS
N3.C1: VmseDetectClock
N3.C1: VmseDetectClock: SUCCESS

END - VMSE Detect DC                   Time         212 ms

START - MXB Clock Train
N3.C2: VmseRefVckResync: ddrFreq = 0x2, VMSE_MODE_2_1 = 1, VMSE_PREAMBLE_2UI = 0
N3.C2: VmseRefVckResync: VLINKFREQNXT set to: 0x20F940A
N3.C1: VmseTrainClockAlign: JCK clkadjcnt =7

END - MXB Clock Train                  Time         156 ms

START - VMSE Train Command
N3.C1.B00: HsxCtlXoverInit: invertPiClk = 0x0, RankUsed = 0xFFF, Training = 0x38FFF26
N3.C1.B01: HsxCtlXoverInit: invertPiClk = 0x0, RankUsed = 0xFFF, Training = 0x38FFF03
N3.C1: VmseTrainCmdFine: vmse link sts = 0x4947

END - VMSE Train Read                  Time         3942 ms

START - VMSE Train Level Tx DQS DCC
N5.C0: VmseLevelTxDqsDccExecute: MXB DQS DCC Finished Successfully

END - VMSE Train Level Tx DQS DCC      Time         12 ms

START - VMSE Train Write Leveling
N5.C0: VmseWriteLevelFineSetup: Set push to data delay = 6, Global TX DQS delay = 0
N5.C0: VmseRLWLFineSearchAll: Entry
N5.C0: FINE WRITE LEVEL DELAY
N5.C0.S00: TX DQS DELAY = 43
N5.C0.S01: TX DQS DELAY = 75
N5.C0.S02: TX DQS DELAY = 46
N5.C0.S03: TX DQS DELAY = 59
N5.C0.S04: TX DQS DELAY = 95
N5.C0.S05: TX DQS DELAY = 86
N5.C0.S06: TX DQS DELAY = 86
N5.C0.S07: TX DQS DELAY = 102
N5.C0.S08: TX DQS DELAY = 79
N5.C0: VmseWriteLevelCoarseSetup: Set push to data delay = 6, Global TX DQS delay = 0
N5.C0: VmseWriteLevelCoarseExecute
N5.C0: VmseWLCoarseUpdatePD: New push to data delay = 6, New global TxDQS delay = 1
N5.C0: VmseWLCoarseUpdatePD: New push to data delay = 7, New global TxDQS delay = 0
N5.C0: VmseWLCoarseUpdatePD: New push to data delay = 7, New global TxDQS delay = 1
N5.C0: VmseWLCoarseUpdatePD: New push to data delay = 8, New global TxDQS delay = 0
N5.C0: VmseWLCoarseUpdatePD: New push to data delay = 8, New global TxDQS delay = 1
N5.C0.S00: FINAL TX DQS BEFORE TxFIFO CHECK = 141
N5.C0.S01: FINAL TX DQS BEFORE TxFIFO CHECK = 172
N5.C0.S02: FINAL TX DQS BEFORE TxFIFO CHECK = 144
N5.C0.S03: FINAL TX DQS BEFORE TxFIFO CHECK = 158
N5.C0.S04: FINAL TX DQS BEFORE TxFIFO CHECK = 194
N5.C0.S05: FINAL TX DQS BEFORE TxFIFO CHECK = 183
N5.C0.S06: FINAL TX DQS BEFORE TxFIFO CHECK = 183
N5.C0.S07: FINAL TX DQS BEFORE TxFIFO CHECK = 200
N5.C0.S08: FINAL TX DQS BEFORE TxFIFO CHECK = 177
N5.C0: ResolveTxFIFOPtrSeparation: Smallest PI (141) < MIN ALLOWED DELAY (176) 
N5.C0: VmseIncTxFifoPtrSeparation: New push to data delay = 7
N5.C0.S00: VmseIncTxFifoPtrSeparation: pi adjustment = 256, FINAL TX DQS DELAY = 397
N5.C0.S01: VmseIncTxFifoPtrSeparation: pi adjustment = 256, FINAL TX DQS DELAY = 428
N5.C0.S02: VmseIncTxFifoPtrSeparation: pi adjustment = 256, FINAL TX DQS DELAY = 400
N5.C0.S03: VmseIncTxFifoPtrSeparation: pi adjustment = 256, FINAL TX DQS DELAY = 414
N5.C0.S04: VmseIncTxFifoPtrSeparation: pi adjustment = 256, FINAL TX DQS DELAY = 450
N5.C0.S05: VmseIncTxFifoPtrSeparation: pi adjustment = 256, FINAL TX DQS DELAY = 439
N5.C0.S06: VmseIncTxFifoPtrSeparation: pi adjustment = 256, FINAL TX DQS DELAY = 439
N5.C0.S07: VmseIncTxFifoPtrSeparation: pi adjustment = 256, FINAL TX DQS DELAY = 456
N5.C0.S08: VmseIncTxFifoPtrSeparation: pi adjustment = 256, FINAL TX DQS DELAY = 433

END - VMSE Train Write Leveling        Time         252 ms

START - VMSE Train Write

END - VMSE Train Read                  Time         4053 ms

START - VMSE Train Level Tx DQS DCC
N7.C0: VmseLevelTxDqsDccExecute: MXB DQS DCC Finished Successfully

END - VMSE Train Level Tx DQS DCC      Time         12 ms

START - VMSE Train Write Leveling
N7.C0: VmseWriteLevelFineSetup: Set push to data delay = 6, Global TX DQS delay = 0
N7.C0: VmseRLWLFineSearchAll: Entry
N7.C0: FINE WRITE LEVEL DELAY
N7.C0.S00: TX DQS DELAY = 45
N7.C0.S01: TX DQS DELAY = 79
N7.C0.S02: TX DQS DELAY = 40
N7.C0.S03: TX DQS DELAY = 64
N7.C0.S04: TX DQS DELAY = 98
N7.C0.S05: TX DQS DELAY = 88
N7.C0.S06: TX DQS DELAY = 88
N7.C0.S07: TX DQS DELAY = 104
N7.C0.S08: TX DQS DELAY = 79
N7.C0: VmseWriteLevelCoarseSetup: Set push to data delay = 6, Global TX DQS delay = 0
N7.C0: VmseWriteLevelCoarseExecute
N7.C0: VmseWLCoarseUpdatePD: New push to data delay = 6, New global TxDQS delay = 1
N7.C0: VmseWLCoarseUpdatePD: New push to data delay = 7, New global TxDQS delay = 0
N7.C0: VmseWLCoarseUpdatePD: New push to data delay = 7, New global TxDQS delay = 1
N7.C0: VmseWLCoarseUpdatePD: New push to data delay = 8, New global TxDQS delay = 0

END - VMSE Train Read                  Time         3883 ms
N7.C0.S00: FINAL TX DQS BEFORE TxFIFO CHECK = 16

START - VMSE Train Level Tx DQS DCC
N7.C0.S01: FINAL TX DQS BEFORE TxFIFO CHECK = 50
Checkpoint Code: Socket 0, 0xB6, 0x52, 0x0000
N7.C0.S02: FINAL TX DQS BEFORE TxFIFO CHECK = 10
N7.C0.S03: FINAL TX DQS BEFORE TxFIFO CHECK = 33
N1.C0: VmseLevelTxDqsDccExecute: MXB DQS DCC Finished Successfully
N7.C0.S04: FINAL TX DQS BEFORE TxFIFO CHECK = 69

END - VMSE Train Level Tx DQS DCC      Time         28 ms
N7.C0.S05: FINAL TX DQS BEFORE TxFIFO CHECK = 59

START - VMSE Train Write Leveling
N7.C0.S06: FINAL TX DQS BEFORE TxFIFO CHECK = 60
Checkpoint Code: Socket 0, 0xB6, 0x54, 0x0000
N7.C0.S07: FINAL TX DQS BEFORE TxFIFO CHECK = 74
N1.C0: VmseWriteLevelFineSetup: Set push to data delay = 6, Global TX DQS delay = 0
N7.C0.S08: FINAL TX DQS BEFORE TxFIFO CHECK = 50
N7.C0: ResolveTxFIFOPtrSeparation: Smallest PI (10) < MIN ALLOWED DELAY (176) 
N1.C0: VmseRLWLFineSearchAll: Entry
N7.C0: VmseIncTxFifoPtrSeparation: New push to data delay = 7
N1.C0: FINE WRITE LEVEL DELAY
N7.C0.S00: VmseIncTxFifoPtrSeparation: pi adjustment = 128, FINAL TX DQS DELAY = 272
N1.C0.S00: TX DQS DELAY = 48
N7.C0.S01: VmseIncTxFifoPtrSeparation: pi adjustment = 128, FINAL TX DQS DELAY = 306
N1.C0.S01: TX DQS DELAY = 78
N7.C0.S02: VmseIncTxFifoPtrSeparation: pi adjustment = 128, FINAL TX DQS DELAY = 266
N1.C0.S02: TX DQS DELAY = 41
N7.C0.S03: VmseIncTxFifoPtrSeparation: pi adjustment = 128, FINAL TX DQS DELAY = 289
N1.C0.S03: TX DQS DELAY = 64
N7.C0.S04: VmseIncTxFifoPtrSeparation: pi adjustment = 128, FINAL TX DQS DELAY = 325
N1.C0.S04: TX DQS DELAY = 100
N7.C0.S05: VmseIncTxFifoPtrSeparation: pi adjustment = 128, FINAL TX DQS DELAY = 315
N1.C0.S05: TX DQS DELAY = 82
N7.C0.S06: VmseIncTxFifoPtrSeparation: pi adjustment = 128, FINAL TX DQS DELAY = 316
N1.C0.S06: TX DQS DELAY = 88
N7.C0.S07: VmseIncTxFifoPtrSeparation: pi adjustment = 128, FINAL TX DQS DELAY = 330
N1.C0.S07: TX DQS DELAY = 100
N7.C0.S08: VmseIncTxFifoPtrSeparation: pi adjustment = 128, FINAL TX DQS DELAY = 306
N1.C0.S08: TX DQS DELAY = 82

END - VMSE Train Write Leveling        Time         322 ms
N1.C0: VmseWriteLevelCoarseSetup: Set push to data delay = 6, Global TX DQS delay = 0

START - VMSE Train Write
N1.C0: VmseWriteLevelCoarseExecute
Checkpoint Code: Socket 0, 0xB6, 0xAC, 0x0000
N1.C0: VmseWLCoarseUpdatePD: New push to data delay = 6, New global TxDQS delay = 1
N1.C0: VmseWLCoarseUpdatePD: New push to data delay = 7, New global TxDQS delay = 0
N1.C0: VmseWLCoarseUpdatePD: New push to data delay = 7, New global TxDQS delay = 1
N1.C0: VmseWLCoarseUpdatePD: New push to data delay = 8, New global TxDQS delay = 0
N1.C0.S00: FINAL TX DQS BEFORE TxFIFO CHECK = 18
N1.C0.S01: FINAL TX DQS BEFORE TxFIFO CHECK = 48
N1.C0.S02: FINAL TX DQS BEFORE TxFIFO CHECK = 12
N1.C0.S03: FINAL TX DQS BEFORE TxFIFO CHECK = 34
N1.C0.S04: FINAL TX DQS BEFORE TxFIFO CHECK = 70
N1.C0.S05: FINAL TX DQS BEFORE TxFIFO CHECK = 54
N1.C0.S06: FINAL TX DQS BEFORE TxFIFO CHECK = 59
N1.C0.S07: FINAL TX DQS BEFORE TxFIFO CHECK = 70
N1.C0.S08: FINAL TX DQS BEFORE TxFIFO CHECK = 54
N1.C0: ResolveTxFIFOPtrSeparation: Smallest PI (12) < MIN ALLOWED DELAY (176) 
N1.C0: VmseIncTxFifoPtrSeparation: New push to data delay = 7
N1.C0.S00: VmseIncTxFifoPtrSeparation: pi adjustment = 128, FINAL TX DQS DELAY = 274
N1.C0.S01: VmseIncTxFifoPtrSeparation: pi adjustment = 128, FINAL TX DQS DELAY = 304
N1.C0.S02: VmseIncTxFifoPtrSeparation: pi adjustment = 128, FINAL TX DQS DELAY = 268
N1.C0.S03: VmseIncTxFifoPtrSeparation: pi adjustment = 128, FINAL TX DQS DELAY = 290
N1.C0.S04: VmseIncTxFifoPtrSeparation: pi adjustment = 128, FINAL TX DQS DELAY = 326
N1.C0.S05: VmseIncTxFifoPtrSeparation: pi adjustment = 128, FINAL TX DQS DELAY = 310
N1.C0.S06: VmseIncTxFifoPtrSeparation: pi adjustment = 128, FINAL TX DQS DELAY = 315
N1.C0.S07: VmseIncTxFifoPtrSeparation: pi adjustment = 128, FINAL TX DQS DELAY = 326
N1.C0.S08: VmseIncTxFifoPtrSeparation: pi adjustment = 128, FINAL TX DQS DELAY = 310

END - VMSE Train Write Leveling        Time         369 ms

START - VMSE Train Write
Checkpoint Code: Socket 0, 0xB6, 0x56, 0x0000
Entry 0 - TrainDcc - DCCStart: 9, VocStart: 14, DCCFinal: 25, VocFinal: 14
Entry 1 - TrainDcc - DCCStart: 11, VocStart: 11, DCCFinal: 11, VocFinal: 11
Entry 2 - TrainDcc - DCCStart: 16, VocStart: 12, DCCFinal: 24, VocFinal: 12
Entry 3 - TrainDcc - DCCStart: 5, VocStart: 12, DCCFinal: 5, VocFinal: 12
Entry 4 - TrainDcc - DCCStart: 5, VocStart: 12, DCCFinal: 5, VocFinal: 20
Entry 5 - TrainDcc - DCCStart: 16, VocStart: 13, DCCFinal: 16, VocFinal: 13
Entry 6 - TrainDcc - DCCStart: 8, VocStart: 17, DCCFinal: 8, VocFinal: 26
Entry 7 - TrainDcc - DCCStart: 9, VocStart: 13, DCCFinal: 9, VocFinal: 13
Entry 8 - TrainDcc - DCCStart: 5, VocStart: 9, DCCFinal: 5, VocFinal: 9
N5.C0.S00: VmseWriteTraining Final: centerPi = 0x3B, PiEw = 0x29, centerVref = 0x44, vrefHeight = 0x26
N5.C0.S01: VmseWriteTraining Final: centerPi = 0x3C, PiEw = 0x28, centerVref = 0x41, vrefHeight = 0x28
N5.C0.S02: VmseWriteTraining Final: centerPi = 0x3A, PiEw = 0x23, centerVref = 0x3D, vrefHeight = 0x28
N5.C0.S03: VmseWriteTraining Final: centerPi = 0x38, PiEw = 0x2A, centerVref = 0x40, vrefHeight = 0x28
N5.C0.S04: VmseWriteTraining Final: centerPi = 0x3F, PiEw = 0x27, centerVref = 0x40, vrefHeight = 0x26
N5.C0.S05: VmseWriteTraining Final: centerPi = 0x3D, PiEw = 0x29, centerVref = 0x43, vrefHeight = 0x24
N5.C0.S06: VmseWriteTraining Final: centerPi = 0x3D, PiEw = 0x24, centerVref = 0x3F, vrefHeight = 0x24
N5.C0.S07: VmseWriteTraining Final: centerPi = 0x3F, PiEw = 0x29, centerVref = 0x40, vrefHeight = 0x26
N5.C0.S08: VmseWriteTraining Final: centerPi = 0x3B, PiEw = 0x25, centerVref = 0x44, vrefHeight = 0x2A
N5.C0.S09: VmseWriteTraining Final: centerPi = 0x3C, PiEw = 0x25, centerVref = 0x3C, vrefHeight = 0x2A
N5.C0.S10: VmseWriteTraining Final: centerPi = 0x3A, PiEw = 0x21, centerVref = 0x3E, vrefHeight = 0x2A
N5.C0.S11: VmseWriteTraining Final: centerPi = 0x3B, PiEw = 0x26, centerVref = 0x41, vrefHeight = 0x2A
N5.C0.S12: VmseWriteTraining Final: centerPi = 0x41, PiEw = 0x24, centerVref = 0x3F, vrefHeight = 0x2A
N5.C0.S13: VmseWriteTraining Final: centerPi = 0x3E, PiEw = 0x28, centerVref = 0x3E, vrefHeight = 0x26
N5.C0.S14: VmseWriteTraining Final: centerPi = 0x3E, PiEw = 0x24, centerVref = 0x3E, vrefHeight = 0x28
N5.C0.S15: VmseWriteTraining Final: centerPi = 0x3F, PiEw = 0x26, centerVref = 0x41, vrefHeight = 0x28
N5.C0.S16: VmseWriteTraining Final: centerPi = 0x3C, PiEw = 0x25, centerVref = 0x44, vrefHeight = 0x22
N5.C0.S17: VmseWriteTraining Final: centerPi = 0x3C, PiEw = 0x25, centerVref = 0x3E, vrefHeight = 0x26
N5.C0.S18: VmseWriteTraining Final: centerPi = 0x39, PiEw = 0x27, centerVref = 0x40, vrefHeight = 0x26
N5.C0.S19: VmseWriteTraining Final: centerPi = 0x37, PiEw = 0x29, centerVref = 0x40, vrefHeight = 0x26
N5.C0.S20: VmseWriteTraining Final: centerPi = 0x3F, PiEw = 0x26, centerVref = 0x3C, vrefHeight = 0x26
N5.C0.S21: VmseWriteTraining Final: centerPi = 0x3D, PiEw = 0x22, centerVref = 0x3F, vrefHeight = 0x22
N5.C0.S22: VmseWriteTraining Final: centerPi = 0x3D, PiEw = 0x23, centerVref = 0x3B, vrefHeight = 0x28
N5.C0.S23: VmseWriteTraining Final: centerPi = 0x3F, PiEw = 0x27, centerVref = 0x3E, vrefHeight = 0x26
N5.C0.S24: VmseWriteTraining Final: centerPi = 0x3C, PiEw = 0x23, centerVref = 0x3B, vrefHeight = 0x22
N5.C0.S25: VmseWriteTraining Final: centerPi = 0x3D, PiEw = 0x29, centerVref = 0x41, vrefHeight = 0x28
N5.C0.S26: VmseWriteTraining Final: centerPi = 0x3B, PiEw = 0x26, centerVref = 0x3F, vrefHeight = 0x28
N5.C0.S27: VmseWriteTraining Final: centerPi = 0x39, PiEw = 0x27, centerVref = 0x3E, vrefHeight = 0x26
N5.C0.S28: VmseWriteTraining Final: centerPi = 0x3F, PiEw = 0x21, centerVref = 0x3F, vrefHeight = 0x24
N5.C0.S29: VmseWriteTraining Final: centerPi = 0x41, PiEw = 0x25, centerVref = 0x3E, vrefHeight = 0x24
N5.C0.S30: VmseWriteTraining Final: centerPi = 0x3F, PiEw = 0x25, centerVref = 0x40, vrefHeight = 0x26
N5.C0.S31: VmseWriteTraining Final: centerPi = 0x40, PiEw = 0x26, centerVref = 0x3C, vrefHeight = 0x26
N5.C0.S32: VmseWriteTraining Final: centerPi = 0x3C, PiEw = 0x28, centerVref = 0x3E, vrefHeight = 0x26
N5.C0.S33: VmseWriteTraining Final: centerPi = 0x3B, PiEw = 0x2A, centerVref = 0x45, vrefHeight = 0x2A
N5.C0.S34: VmseWriteTraining Final: centerPi = 0x3B, PiEw = 0x28, centerVref = 0x3C, vrefHeight = 0x2C
N5.C0.S35: VmseWriteTraining Final: centerPi = 0x3A, PiEw = 0x2B, centerVref = 0x42, vrefHeight = 0x2C
N5.C0.S36: VmseWriteTraining Final: centerPi = 0x41, PiEw = 0x29, centerVref = 0x3B, vrefHeight = 0x28
N5.C0.S37: VmseWriteTraining Final: centerPi = 0x42, PiEw = 0x27, centerVref = 0x42, vrefHeight = 0x2A
N5.C0.S38: VmseWriteTraining Final: centerPi = 0x3D, PiEw = 0x28, centerVref = 0x41, vrefHeight = 0x2C
N5.C0.S39: VmseWriteTraining Final: centerPi = 0x41, PiEw = 0x29, centerVref = 0x39, vrefHeight = 0x2A
N5.C0.S40: VmseWriteTraining Final: centerPi = 0x3B, PiEw = 0x24, centerVref = 0x40, vrefHeight = 0x28
N5.C0.S41: VmseWriteTraining Final: centerPi = 0x3A, PiEw = 0x2C, centerVref = 0x41, vrefHeight = 0x28
N5.C0.S42: VmseWriteTraining Final: centerPi = 0x37, PiEw = 0x25, centerVref = 0x3D, vrefHeight = 0x28
N5.C0.S43: VmseWriteTraining Final: centerPi = 0x39, PiEw = 0x24, centerVref = 0x39, vrefHeight = 0x28
Entry 0 - TrainDcc - DCCStart: 9, VocStart: 12, DCCFinal: 33, VocFinal: 12
N5.C0.S44: VmseWriteTraining Final: centerPi = 0x3E, PiEw = 0x27, centerVref = 0x3B, vrefHeight = 0x26
Entry 1 - TrainDcc - DCCStart: 19, VocStart: 13, DCCFinal: 19, VocFinal: 13
N5.C0.S45: VmseWriteTraining Final: centerPi = 0x3D, PiEw = 0x26, centerVref = 0x41, vrefHeight = 0x28
Entry 2 - TrainDcc - DCCStart: 14, VocStart: 17, DCCFinal: 30, VocFinal: 17
N5.C0.S46: VmseWriteTraining Final: centerPi = 0x3E, PiEw = 0x21, centerVref = 0x3D, vrefHeight = 0x26
Entry 3 - TrainDcc - DCCStart: 12, VocStart: 20, DCCFinal: 12, VocFinal: 20
N5.C0.S47: VmseWriteTraining Final: centerPi = 0x3D, PiEw = 0x25, centerVref = 0x41, vrefHeight = 0x28
Entry 4 - TrainDcc - DCCStart: 9, VocStart: 11, DCCFinal: 9, VocFinal: 12
N5.C0.S48: VmseWriteTraining Final: centerPi = 0x3B, PiEw = 0x27, centerVref = 0x3E, vrefHeight = 0x22
Entry 5 - TrainDcc - DCCStart: 12, VocStart: 8, DCCFinal: 12, VocFinal: 8
N5.C0.S49: VmseWriteTraining Final: centerPi = 0x3A, PiEw = 0x29, centerVref = 0x3E, vrefHeight = 0x2A
Entry 6 - TrainDcc - DCCStart: 2, VocStart: 16, DCCFinal: 2, VocFinal: 22
N5.C0.S50: VmseWriteTraining Final: centerPi = 0x38, PiEw = 0x2A, centerVref = 0x42, vrefHeight = 0x28
Entry 7 - TrainDcc - DCCStart: 17, VocStart: 12, DCCFinal: 17, VocFinal: 12
N5.C0.S51: VmseWriteTraining Final: centerPi = 0x36, PiEw = 0x27, centerVref = 0x3D, vrefHeight = 0x26
Entry 8 - TrainDcc - DCCStart: 4, VocStart: 17, DCCFinal: 4, VocFinal: 17
N5.C0.S52: VmseWriteTraining Final: centerPi = 0x3F, PiEw = 0x25, centerVref = 0x3F, vrefHeight = 0x28
N5.C0.S53: VmseWriteTraining Final: centerPi = 0x3F, PiEw = 0x27, centerVref = 0x3C, vrefHeight = 0x26
N5.C0.S54: VmseWriteTraining Final: centerPi = 0x3D, PiEw = 0x24, centerVref = 0x3F, vrefHeight = 0x28
Entry 0 - TrainDcc - DCCStart: 3, VocStart: 12, DCCFinal: 63, VocFinal: 13
N5.C0.S55: VmseWriteTraining Final: centerPi = 0x3D, PiEw = 0x27, centerVref = 0x3D, vrefHeight = 0x28
Entry 1 - TrainDcc - DCCStart: 11, VocStart: 14, DCCFinal: 11, VocFinal: 14
N5.C0.S56: VmseWriteTraining Final: centerPi = 0x3D, PiEw = 0x23, centerVref = 0x3E, vrefHeight = 0x26
Entry 2 - TrainDcc - DCCStart: 18, VocStart: 16, DCCFinal: 63, VocFinal: 18
N5.C0.S57: VmseWriteTraining Final: centerPi = 0x3D, PiEw = 0x22, centerVref = 0x3F, vrefHeight = 0x28
Entry 3 - TrainDcc - DCCStart: 31, VocStart: 13, DCCFinal: 31, VocFinal: 13
N5.C0.S58: VmseWriteTraining Final: centerPi = 0x3C, PiEw = 0x24, centerVref = 0x3D, vrefHeight = 0x2C
Entry 4 - TrainDcc - DCCStart: 11, VocStart: 12, DCCFinal: 11, VocFinal: 19
N5.C0.S59: VmseWriteTraining Final: centerPi = 0x37, PiEw = 0x27, centerVref = 0x42, vrefHeight = 0x28
Entry 5 - TrainDcc - DCCStart: 1, VocStart: 11, DCCFinal: 1, VocFinal: 11
N5.C0.S60: VmseWriteTraining Final: centerPi = 0x42, PiEw = 0x25, centerVref = 0x3B, vrefHeight = 0x28
Entry 6 - TrainDcc - DCCStart: 3, VocStart: 14, DCCFinal: 3, VocFinal: 22
N5.C0.S61: VmseWriteTraining Final: centerPi = 0x40, PiEw = 0x1F, centerVref = 0x3D, vrefHeight = 0x28
Entry 7 - TrainDcc - DCCStart: 6, VocStart: 13, DCCFinal: 6, VocFinal: 13
N5.C0.S62: VmseWriteTraining Final: centerPi = 0x3E, PiEw = 0x22, centerVref = 0x3B, vrefHeight = 0x28
Entry 8 - TrainDcc - DCCStart: 3, VocStart: 11, DCCFinal: 3, VocFinal: 11
N5.C0.S63: VmseWriteTraining Final: centerPi = 0x40, PiEw = 0x23, centerVref = 0x3D, vrefHeight = 0x26
N5.C0.S64: VmseWriteTraining Final: centerPi = 0x3F, PiEw = 0x21, centerVref = 0x3F, vrefHeight = 0x24
N5.C0.S65: VmseWriteTraining Final: centerPi = 0x3D, PiEw = 0x20, centerVref = 0x3E, vrefHeight = 0x22
N5.C0.S66: VmseWriteTraining Final: centerPi = 0x3D, PiEw = 0x20, centerVref = 0x3C, vrefHeight = 0x26
N5.C0.S67: VmseWriteTraining Final: centerPi = 0x3B, PiEw = 0x26, centerVref = 0x3D, vrefHeight = 0x28
N5.C0.S68: VmseWriteTraining Final: centerPi = 0x42, PiEw = 0x21, centerVref = 0x3E, vrefHeight = 0x26
N5.C0.S69: VmseWriteTraining Final: centerPi = 0x40, PiEw = 0x20, centerVref = 0x41, vrefHeight = 0x24
N5.C0.S70: VmseWriteTraining Final: centerPi = 0x40, PiEw = 0x20, centerVref = 0x3F, vrefHeight = 0x24
N7.C0.S00: VmseWriteTraining Final: centerPi = 0x3A, PiEw = 0x28, centerVref = 0x47, vrefHeight = 0x2A
N5.C0.S71: VmseWriteTraining Final: centerPi = 0x41, PiEw = 0x26, centerVref = 0x37, vrefHeight = 0x28
N7.C0.S01: VmseWriteTraining Final: centerPi = 0x38, PiEw = 0x2B, centerVref = 0x40, vrefHeight = 0x26

END - VMSE Train Write                 Time         2266 ms
N7.C0.S02: VmseWriteTraining Final: centerPi = 0x3C, PiEw = 0x27, centerVref = 0x3F, vrefHeight = 0x2C
N5: 
Total VMSE trainings latency = 13951 ms
N7.C0.S03: VmseWriteTraining Final: centerPi = 0x3D, PiEw = 0x26, centerVref = 0x43, vrefHeight = 0x2A
N5: CpgcVmseTraining for VMSE1
N7.C0.S04: VmseWriteTraining Final: centerPi = 0x41, PiEw = 0x27, centerVref = 0x3B, vrefHeight = 0x2C
N5: Initialize VMSE Channels
N7.C0.S05: VmseWriteTraining Final: centerPi = 0x3E, PiEw = 0x29, centerVref = 0x45, vrefHeight = 0x28

START - VMSE Detect DC
N7.C0.S06: VmseWriteTraining Final: centerPi = 0x3F, PiEw = 0x29, centerVref = 0x3D, vrefHeight = 0x2C
N5: HsxVmseCompInit
N7.C0.S07: VmseWriteTraining Final: centerPi = 0x3D, PiEw = 0x28, centerVref = 0x3F, vrefHeight = 0x2A
N7.C0.S08: VmseWriteTraining Final: centerPi = 0x3D, PiEw = 0x27, centerVref = 0x42, vrefHeight = 0x2E
N5.C1: Skip DC Detect check for CMD results
N7.C0.S09: VmseWriteTraining Final: centerPi = 0x3B, PiEw = 0x26, centerVref = 0x3D, vrefHeight = 0x2C
N7.C0.S10: VmseWriteTraining Final: centerPi = 0x3A, PiEw = 0x28, centerVref = 0x41, vrefHeight = 0x2C
N5.C1: Skip DC Detect check for CMD results
N7.C0.S11: VmseWriteTraining Final: centerPi = 0x3A, PiEw = 0x29, centerVref = 0x42, vrefHeight = 0x2E
N5: HsxVmseCompInit
N7.C0.S12: VmseWriteTraining Final: centerPi = 0x40, PiEw = 0x24, centerVref = 0x40, vrefHeight = 0x2A
N5.C1: VmseDetectDC: SUCCESS
N7.C0.S13: VmseWriteTraining Final: centerPi = 0x40, PiEw = 0x24, centerVref = 0x3E, vrefHeight = 0x2A
N1.C0.S00: VmseWriteTraining Final: centerPi = 0x3B, PiEw = 0x2B, centerVref = 0x44, vrefHeight = 0x2C
N5.C1: VmseDetectClock
N7.C0.S14: VmseWriteTraining Final: centerPi = 0x3D, PiEw = 0x24, centerVref = 0x44, vrefHeight = 0x2E
N1.C0.S01: VmseWriteTraining Final: centerPi = 0x38, PiEw = 0x27, centerVref = 0x44, vrefHeight = 0x28
N7.C0.S15: VmseWriteTraining Final: centerPi = 0x3F, PiEw = 0x28, centerVref = 0x3F, vrefHeight = 0x2C
N1.C0.S02: VmseWriteTraining Final: centerPi = 0x3D, PiEw = 0x24, centerVref = 0x38, vrefHeight = 0x2C
N7.C0.S16: VmseWriteTraining Final: centerPi = 0x3B, PiEw = 0x2A, centerVref = 0x45, vrefHeight = 0x26
N1.C0.S03: VmseWriteTraining Final: centerPi = 0x39, PiEw = 0x28, centerVref = 0x3B, vrefHeight = 0x2C
N7.C0.S17: VmseWriteTraining Final: centerPi = 0x3A, PiEw = 0x29, centerVref = 0x3F, vrefHeight = 0x28
N1.C0.S04: VmseWriteTraining Final: centerPi = 0x3C, PiEw = 0x26, centerVref = 0x3F, vrefHeight = 0x26
N7.C0.S18: VmseWriteTraining Final: centerPi = 0x3A, PiEw = 0x23, centerVref = 0x3D, vrefHeight = 0x28
N1.C0.S05: VmseWriteTraining Final: centerPi = 0x3B, PiEw = 0x2B, centerVref = 0x40, vrefHeight = 0x26
N7.C0.S19: VmseWriteTraining Final: centerPi = 0x36, PiEw = 0x2A, centerVref = 0x41, vrefHeight = 0x28
N1.C0.S06: VmseWriteTraining Final: centerPi = 0x3A, PiEw = 0x28, centerVref = 0x3F, vrefHeight = 0x28
N7.C0.S20: VmseWriteTraining Final: centerPi = 0x41, PiEw = 0x27, centerVref = 0x40, vrefHeight = 0x28
N1.C0.S07: VmseWriteTraining Final: centerPi = 0x3D, PiEw = 0x2B, centerVref = 0x3C, vrefHeight = 0x2A
N7.C0.S21: VmseWriteTraining Final: centerPi = 0x40, PiEw = 0x26, centerVref = 0x3F, vrefHeight = 0x28
N1.C0.S08: VmseWriteTraining Final: centerPi = 0x3C, PiEw = 0x27, centerVref = 0x43, vrefHeight = 0x28
N5.C1: VmseDetectClock: SUCCESS
N7.C0.S22: VmseWriteTraining Final: centerPi = 0x3E, PiEw = 0x22, centerVref = 0x3C, vrefHeight = 0x28
N1.C0.S09: VmseWriteTraining Final: centerPi = 0x3E, PiEw = 0x21, centerVref = 0x3A, vrefHeight = 0x2A

END - VMSE Detect DC                   Time         297 ms
N7.C0.S23: VmseWriteTraining Final: centerPi = 0x3D, PiEw = 0x27, centerVref = 0x41, vrefHeight = 0x28
N1.C0.S10: VmseWriteTraining Final: centerPi = 0x3A, PiEw = 0x25, centerVref = 0x40, vrefHeight = 0x2A

START - MXB Clock Train
N7.C0.S24: VmseWriteTraining Final: centerPi = 0x3A, PiEw = 0x25, centerVref = 0x42, vrefHeight = 0x26
N1.C0.S11: VmseWriteTraining Final: centerPi = 0x3C, PiEw = 0x25, centerVref = 0x40, vrefHeight = 0x2C
N7.C0.S25: VmseWriteTraining Final: centerPi = 0x3A, PiEw = 0x25, centerVref = 0x40, vrefHeight = 0x28
N1.C0.S12: VmseWriteTraining Final: centerPi = 0x40, PiEw = 0x23, centerVref = 0x3E, vrefHeight = 0x2A
N7.C0.S26: VmseWriteTraining Final: centerPi = 0x3B, PiEw = 0x26, centerVref = 0x42, vrefHeight = 0x2A
N1.C0.S13: VmseWriteTraining Final: centerPi = 0x42, PiEw = 0x21, centerVref = 0x3E, vrefHeight = 0x2A
N7.C0.S27: VmseWriteTraining Final: centerPi = 0x3B, PiEw = 0x21, centerVref = 0x3C, vrefHeight = 0x2A
N1.C0.S14: VmseWriteTraining Final: centerPi = 0x3F, PiEw = 0x24, centerVref = 0x42, vrefHeight = 0x2A
N5.C2: VmseRefVckResync: ddrFreq = 0x2, VMSE_MODE_2_1 = 1, VMSE_PREAMBLE_2UI = 0
N7.C0.S28: VmseWriteTraining Final: centerPi = 0x3D, PiEw = 0x24, centerVref = 0x3A, vrefHeight = 0x26
N1.C0.S15: VmseWriteTraining Final: centerPi = 0x3D, PiEw = 0x2B, centerVref = 0x41, vrefHeight = 0x28
N7.C0.S29: VmseWriteTraining Final: centerPi = 0x3D, PiEw = 0x27, centerVref = 0x43, vrefHeight = 0x28
N1.C0.S16: VmseWriteTraining Final: centerPi = 0x3B, PiEw = 0x27, centerVref = 0x3F, vrefHeight = 0x24
N5.C2: VmseRefVckResync: VLINKFREQNXT set to: 0x20F940A
N7.C0.S30: VmseWriteTraining Final: centerPi = 0x3D, PiEw = 0x22, centerVref = 0x3D, vrefHeight = 0x28
N1.C0.S17: VmseWriteTraining Final: centerPi = 0x37, PiEw = 0x26, centerVref = 0x48, vrefHeight = 0x24
N7.C0.S31: VmseWriteTraining Final: centerPi = 0x3E, PiEw = 0x27, centerVref = 0x3C, vrefHeight = 0x2A
N1.C0.S18: VmseWriteTraining Final: centerPi = 0x37, PiEw = 0x26, centerVref = 0x43, vrefHeight = 0x28
N5.C1: VmseTrainClockAlign: JCK clkadjcnt =5
N7.C0.S32: VmseWriteTraining Final: centerPi = 0x3D, PiEw = 0x24, centerVref = 0x3F, vrefHeight = 0x2A
N1.C0.S19: VmseWriteTraining Final: centerPi = 0x34, PiEw = 0x2A, centerVref = 0x3F, vrefHeight = 0x28

END - MXB Clock Train                  Time         200 ms
N7.C0.S33: VmseWriteTraining Final: centerPi = 0x3A, PiEw = 0x29, centerVref = 0x41, vrefHeight = 0x2A
N1.C0.S20: VmseWriteTraining Final: centerPi = 0x41, PiEw = 0x22, centerVref = 0x3D, vrefHeight = 0x28

START - VMSE Train Command
N7.C0.S34: VmseWriteTraining Final: centerPi = 0x3A, PiEw = 0x26, centerVref = 0x45, vrefHeight = 0x2A
N1.C0.S21: VmseWriteTraining Final: centerPi = 0x3D, PiEw = 0x28, centerVref = 0x43, vrefHeight = 0x28
N5.C1.B00: HsxCtlXoverInit: invertPiClk = 0x0, RankUsed = 0xFFF, Training = 0x38FFF25
N7.C0.S35: VmseWriteTraining Final: centerPi = 0x38, PiEw = 0x29, centerVref = 0x3F, vrefHeight = 0x2E
N1.C0.S22: VmseWriteTraining Final: centerPi = 0x39, PiEw = 0x27, centerVref = 0x3B, vrefHeight = 0x28
N5.C1.B01: HsxCtlXoverInit: invertPiClk = 0x0, RankUsed = 0xFFF, Training = 0x38FFF02
N7.C0.S36: VmseWriteTraining Final: centerPi = 0x42, PiEw = 0x26, centerVref = 0x3D, vrefHeight = 0x2C
N1.C0.S23: VmseWriteTraining Final: centerPi = 0x3C, PiEw = 0x29, centerVref = 0x3D, vrefHeight = 0x28
N7.C0.S37: VmseWriteTraining Final: centerPi = 0x40, PiEw = 0x28, centerVref = 0x45, vrefHeight = 0x2A
N1.C0.S24: VmseWriteTraining Final: centerPi = 0x3A, PiEw = 0x25, centerVref = 0x41, vrefHeight = 0x24
N7.C0.S38: VmseWriteTraining Final: centerPi = 0x40, PiEw = 0x26, centerVref = 0x40, vrefHeight = 0x2E
N1.C0.S25: VmseWriteTraining Final: centerPi = 0x3B, PiEw = 0x25, centerVref = 0x3B, vrefHeight = 0x2A
N7.C0.S39: VmseWriteTraining Final: centerPi = 0x40, PiEw = 0x26, centerVref = 0x40, vrefHeight = 0x2A
N1.C0.S26: VmseWriteTraining Final: centerPi = 0x39, PiEw = 0x24, centerVref = 0x42, vrefHeight = 0x2A
N7.C0.S40: VmseWriteTraining Final: centerPi = 0x38, PiEw = 0x28, centerVref = 0x49, vrefHeight = 0x28
N1.C0.S27: VmseWriteTraining Final: centerPi = 0x37, PiEw = 0x24, centerVref = 0x42, vrefHeight = 0x28
N5.C1: VmseTrainCmdFine: vmse link sts = 0x4947
N7.C0.S41: VmseWriteTraining Final: centerPi = 0x3C, PiEw = 0x28, centerVref = 0x40, vrefHeight = 0x2A
N1.C0.S28: VmseWriteTraining Final: centerPi = 0x3C, PiEw = 0x1F, centerVref = 0x3D, vrefHeight = 0x26
N7.C0.S42: VmseWriteTraining Final: centerPi = 0x3A, PiEw = 0x25, centerVref = 0x3C, vrefHeight = 0x28
N1.C0.S29: VmseWriteTraining Final: centerPi = 0x3D, PiEw = 0x29, centerVref = 0x43, vrefHeight = 0x28
N7.C0.S43: VmseWriteTraining Final: centerPi = 0x37, PiEw = 0x29, centerVref = 0x40, vrefHeight = 0x2A
N1.C0.S30: VmseWriteTraining Final: centerPi = 0x3E, PiEw = 0x27, centerVref = 0x3C, vrefHeight = 0x26
N7.C0.S44: VmseWriteTraining Final: centerPi = 0x3F, PiEw = 0x29, centerVref = 0x40, vrefHeight = 0x2A
N1.C0.S31: VmseWriteTraining Final: centerPi = 0x3E, PiEw = 0x26, centerVref = 0x40, vrefHeight = 0x26
N7.C0.S45: VmseWriteTraining Final: centerPi = 0x3E, PiEw = 0x25, centerVref = 0x40, vrefHeight = 0x2A
N1.C0.S32: VmseWriteTraining Final: centerPi = 0x3A, PiEw = 0x29, centerVref = 0x42, vrefHeight = 0x28
N7.C0.S46: VmseWriteTraining Final: centerPi = 0x3D, PiEw = 0x24, centerVref = 0x3D, vrefHeight = 0x28
N1.C0.S33: VmseWriteTraining Final: centerPi = 0x3B, PiEw = 0x26, centerVref = 0x3F, vrefHeight = 0x2A
N7.C0.S47: VmseWriteTraining Final: centerPi = 0x41, PiEw = 0x25, centerVref = 0x3B, vrefHeight = 0x2C
N1.C0.S34: VmseWriteTraining Final: centerPi = 0x37, PiEw = 0x28, centerVref = 0x3A, vrefHeight = 0x2C
N7.C0.S48: VmseWriteTraining Final: centerPi = 0x3D, PiEw = 0x24, centerVref = 0x3F, vrefHeight = 0x24
N1.C0.S35: VmseWriteTraining Final: centerPi = 0x3D, PiEw = 0x27, centerVref = 0x3F, vrefHeight = 0x2E
N7.C0.S49: VmseWriteTraining Final: centerPi = 0x3D, PiEw = 0x28, centerVref = 0x3D, vrefHeight = 0x2C
N1.C0.S36: VmseWriteTraining Final: centerPi = 0x41, PiEw = 0x24, centerVref = 0x39, vrefHeight = 0x2C
N7.C0.S50: VmseWriteTraining Final: centerPi = 0x3C, PiEw = 0x24, centerVref = 0x40, vrefHeight = 0x28
N1.C0.S37: VmseWriteTraining Final: centerPi = 0x3E, PiEw = 0x29, centerVref = 0x40, vrefHeight = 0x28
N7.C0.S51: VmseWriteTraining Final: centerPi = 0x38, PiEw = 0x29, centerVref = 0x3F, vrefHeight = 0x2C
N1.C0.S38: VmseWriteTraining Final: centerPi = 0x3A, PiEw = 0x2A, centerVref = 0x43, vrefHeight = 0x2A
N7.C0.S52: VmseWriteTraining Final: centerPi = 0x41, PiEw = 0x23, centerVref = 0x3F, vrefHeight = 0x26
N1.C0.S39: VmseWriteTraining Final: centerPi = 0x41, PiEw = 0x27, centerVref = 0x3B, vrefHeight = 0x2C
N7.C0.S53: VmseWriteTraining Final: centerPi = 0x41, PiEw = 0x24, centerVref = 0x3F, vrefHeight = 0x2A
N1.C0.S40: VmseWriteTraining Final: centerPi = 0x3E, PiEw = 0x24, centerVref = 0x3E, vrefHeight = 0x2A
N7.C0.S54: VmseWriteTraining Final: centerPi = 0x40, PiEw = 0x25, centerVref = 0x3F, vrefHeight = 0x28
N1.C0.S41: VmseWriteTraining Final: centerPi = 0x3E, PiEw = 0x25, centerVref = 0x41, vrefHeight = 0x28
N7.C0.S55: VmseWriteTraining Final: centerPi = 0x42, PiEw = 0x29, centerVref = 0x39, vrefHeight = 0x2C
N1.C0.S42: VmseWriteTraining Final: centerPi = 0x3C, PiEw = 0x24, centerVref = 0x3C, vrefHeight = 0x2A
N7.C0.S56: VmseWriteTraining Final: centerPi = 0x3B, PiEw = 0x25, centerVref = 0x45, vrefHeight = 0x26
N1.C0.S43: VmseWriteTraining Final: centerPi = 0x3E, PiEw = 0x20, centerVref = 0x40, vrefHeight = 0x2A
N7.C0.S57: VmseWriteTraining Final: centerPi = 0x3C, PiEw = 0x27, centerVref = 0x3E, vrefHeight = 0x2A
N1.C0.S44: VmseWriteTraining Final: centerPi = 0x41, PiEw = 0x22, centerVref = 0x3E, vrefHeight = 0x28
N7.C0.S58: VmseWriteTraining Final: centerPi = 0x39, PiEw = 0x27, centerVref = 0x3B, vrefHeight = 0x2A
N1.C0.S45: VmseWriteTraining Final: centerPi = 0x42, PiEw = 0x24, centerVref = 0x3C, vrefHeight = 0x26
N7.C0.S59: VmseWriteTraining Final: centerPi = 0x36, PiEw = 0x24, centerVref = 0x3D, vrefHeight = 0x2C
N1.C0.S46: VmseWriteTraining Final: centerPi = 0x41, PiEw = 0x22, centerVref = 0x45, vrefHeight = 0x28
N7.C0.S60: VmseWriteTraining Final: centerPi = 0x41, PiEw = 0x27, centerVref = 0x3B, vrefHeight = 0x2C
N1.C0.S47: VmseWriteTraining Final: centerPi = 0x3F, PiEw = 0x25, centerVref = 0x40, vrefHeight = 0x28
N7.C0.S61: VmseWriteTraining Final: centerPi = 0x41, PiEw = 0x23, centerVref = 0x3F, vrefHeight = 0x2C
N1.C0.S48: VmseWriteTraining Final: centerPi = 0x3D, PiEw = 0x25, centerVref = 0x3E, vrefHeight = 0x26
N7.C0.S62: VmseWriteTraining Final: centerPi = 0x3E, PiEw = 0x26, centerVref = 0x3A, vrefHeight = 0x2E
N1.C0.S49: VmseWriteTraining Final: centerPi = 0x3E, PiEw = 0x2A, centerVref = 0x3E, vrefHeight = 0x2A
N7.C0.S63: VmseWriteTraining Final: centerPi = 0x3E, PiEw = 0x28, centerVref = 0x42, vrefHeight = 0x2C
N1.C0.S50: VmseWriteTraining Final: centerPi = 0x3C, PiEw = 0x29, centerVref = 0x40, vrefHeight = 0x2A
N7.C0.S64: VmseWriteTraining Final: centerPi = 0x3F, PiEw = 0x21, centerVref = 0x3F, vrefHeight = 0x28
N1.C0.S51: VmseWriteTraining Final: centerPi = 0x3A, PiEw = 0x27, centerVref = 0x3D, vrefHeight = 0x2A
N7.C0.S65: VmseWriteTraining Final: centerPi = 0x3B, PiEw = 0x1E, centerVref = 0x44, vrefHeight = 0x22
N1.C0.S52: VmseWriteTraining Final: centerPi = 0x42, PiEw = 0x27, centerVref = 0x41, vrefHeight = 0x28
N7.C0.S66: VmseWriteTraining Final: centerPi = 0x3E, PiEw = 0x22, centerVref = 0x40, vrefHeight = 0x26
N1.C0.S53: VmseWriteTraining Final: centerPi = 0x43, PiEw = 0x26, centerVref = 0x3D, vrefHeight = 0x2A
N7.C0.S67: VmseWriteTraining Final: centerPi = 0x3D, PiEw = 0x28, centerVref = 0x37, vrefHeight = 0x2A
N1.C0.S54: VmseWriteTraining Final: centerPi = 0x3F, PiEw = 0x27, centerVref = 0x41, vrefHeight = 0x26
N7.C0.S68: VmseWriteTraining Final: centerPi = 0x42, PiEw = 0x24, centerVref = 0x3E, vrefHeight = 0x28
N1.C0.S55: VmseWriteTraining Final: centerPi = 0x41, PiEw = 0x29, centerVref = 0x3F, vrefHeight = 0x2A
N7.C0.S69: VmseWriteTraining Final: centerPi = 0x40, PiEw = 0x21, centerVref = 0x3F, vrefHeight = 0x28
N1.C0.S56: VmseWriteTraining Final: centerPi = 0x3F, PiEw = 0x21, centerVref = 0x44, vrefHeight = 0x28
N7.C0.S70: VmseWriteTraining Final: centerPi = 0x40, PiEw = 0x23, centerVref = 0x41, vrefHeight = 0x26
N1.C0.S57: VmseWriteTraining Final: centerPi = 0x3E, PiEw = 0x23, centerVref = 0x3C, vrefHeight = 0x2A
N7.C0.S71: VmseWriteTraining Final: centerPi = 0x40, PiEw = 0x23, centerVref = 0x3F, vrefHeight = 0x28
N1.C0.S58: VmseWriteTraining Final: centerPi = 0x3F, PiEw = 0x25, centerVref = 0x3E, vrefHeight = 0x2C

END - VMSE Train Write                 Time         3040 ms
N1.C0.S59: VmseWriteTraining Final: centerPi = 0x38, PiEw = 0x27, centerVref = 0x43, vrefHeight = 0x28
N7: 
Total VMSE trainings latency = 15377 ms
N1.C0.S60: VmseWriteTraining Final: centerPi = 0x40, PiEw = 0x21, centerVref = 0x3F, vrefHeight = 0x28
N7: CpgcVmseTraining for VMSE1
N1.C0.S61: VmseWriteTraining Final: centerPi = 0x41, PiEw = 0x22, centerVref = 0x40, vrefHeight = 0x26
N7: Initialize VMSE Channels
N1.C0.S62: VmseWriteTraining Final: centerPi = 0x3F, PiEw = 0x1F, centerVref = 0x40, vrefHeight = 0x2A

START - VMSE Detect DC
N1.C0.S63: VmseWriteTraining Final: centerPi = 0x40, PiEw = 0x27, centerVref = 0x43, vrefHeight = 0x28
N7: HsxVmseCompInit
N1.C0.S64: VmseWriteTraining Final: centerPi = 0x3D, PiEw = 0x21, centerVref = 0x45, vrefHeight = 0x28
N1.C0.S65: VmseWriteTraining Final: centerPi = 0x3B, PiEw = 0x22, centerVref = 0x3F, vrefHeight = 0x28
N7.C1: Skip DC Detect check for CMD results
N1.C0.S66: VmseWriteTraining Final: centerPi = 0x3B, PiEw = 0x21, centerVref = 0x3F, vrefHeight = 0x26
N1.C0.S67: VmseWriteTraining Final: centerPi = 0x3A, PiEw = 0x22, centerVref = 0x3E, vrefHeight = 0x2A
N7.C1: Skip DC Detect check for CMD results
N1.C0.S68: VmseWriteTraining Final: centerPi = 0x43, PiEw = 0x22, centerVref = 0x41, vrefHeight = 0x28
N7: HsxVmseCompInit
N1.C0.S69: VmseWriteTraining Final: centerPi = 0x40, PiEw = 0x20, centerVref = 0x3E, vrefHeight = 0x26
N7.C1: VmseDetectDC: SUCCESS
N1.C0.S70: VmseWriteTraining Final: centerPi = 0x40, PiEw = 0x23, centerVref = 0x3E, vrefHeight = 0x26
N7.C1: VmseDetectClock
N1.C0.S71: VmseWriteTraining Final: centerPi = 0x41, PiEw = 0x24, centerVref = 0x3A, vrefHeight = 0x28

END - VMSE Train Write                 Time         3035 ms
Checkpoint Code: Socket 0, 0xB6, 0x64, 0x0000
N1: 
Total VMSE trainings latency = 15544 ms
N1: CpgcVmseTraining for VMSE1
Checkpoint Code: Socket 0, 0xB6, 0x11, 0x0000
N1: Initialize VMSE Channels

START - VMSE Detect DC
Checkpoint Code: Socket 0, 0xB6, 0x46, 0x0000
N1: HsxVmseCompInit
Checkpoint Code: Socket 0, 0xB6, 0x80, 0x0000
N1.C1: Skip DC Detect check for CMD results
N1.C1: Skip DC Detect check for CMD results
N1: HsxVmseCompInit
Checkpoint Code: Socket 0, 0xB6, 0x81, 0x0000
N1.C1: VmseDetectDC: SUCCESS
N1.C1: VmseDetectClock
N7.C1: VmseDetectClock: SUCCESS

END - VMSE Detect DC                   Time         277 ms

START - MXB Clock Train
N7.C2: VmseRefVckResync: ddrFreq = 0x2, VMSE_MODE_2_1 = 1, VMSE_PREAMBLE_2UI = 0
N1.C1: VmseDetectClock: SUCCESS

END - VMSE Detect DC                   Time         230 ms

START - MXB Clock Train
Checkpoint Code: Socket 0, 0xB6, 0x48, 0x0000
N7.C2: VmseRefVckResync: VLINKFREQNXT set to: 0x20F940A
Checkpoint Code: Socket 0, 0xB6, 0x6C, 0x0000
N7.C1: VmseTrainClockAlign: JCK clkadjcnt =5

END - MXB Clock Train                  Time         158 ms

START - VMSE Train Command
N7.C1.B00: HsxCtlXoverInit: invertPiClk = 0x0, RankUsed = 0xFFF, Training = 0x38FFF23
N7.C1.B01: HsxCtlXoverInit: invertPiClk = 0x0, RankUsed = 0xFFF, Training = 0x38FFF01
N1.C1: VmseAdjustVckVoc: retrain Clock DCC.
   dcc1_vck = 0x34, dcc2_vck = 0x3F, preampvoc = 0xB
Checkpoint Code: Socket 0, 0xB6, 0x6C, 0x0000
N1.C1: VmseAdjustVckVoc: retrain Clock DCC.
   dcc1_vck = 0x24, dcc2_vck = 0x3F, preampvoc = 0xC
Checkpoint Code: Socket 0, 0xB6, 0x6C, 0x0000
N7.C1: VmseTrainCmdFine: vmse link sts = 0x4947
N1.C2: VmseRefVckResync: ddrFreq = 0x2, VMSE_MODE_2_1 = 1, VMSE_PREAMBLE_2UI = 0
N1.C2: VmseRefVckResync: VLINKFREQNXT set to: 0x20F940A
N1.C1: VmseTrainClockAlign: JCK clkadjcnt =1

END - MXB Clock Train                  Time         308 ms

START - VMSE Train Command
Checkpoint Code: Socket 0, 0xB6, 0x4A, 0x0000
N1.C1.B00: HsxCtlXoverInit: invertPiClk = 0x0, RankUsed = 0xFFF, Training = 0x38FFF25
N1.C1.B01: HsxCtlXoverInit: invertPiClk = 0x0, RankUsed = 0xFFF, Training = 0x38FFF03
Checkpoint Code: Socket 0, 0xB6, 0x60, 0x0000
Checkpoint Code: Socket 0, 0xB6, 0x5A, 0x0000
N1.C1: VmseTrainCmdFine: vmse link sts = 0x4947
Entry 0 - TrainDcc - DCCStart: 8, VocStart: 11, DCCFinal: 24, VocFinal: 11
Entry 1 - TrainDcc - DCCStart: 58, VocStart: 11, DCCFinal: 34, VocFinal: 11
N3.C1.S00: VmseCmdFineTraining Final: centerPi = 0x60, PiEw = 0x30, centerVref = 0x3F, vrefHeight = 0x43
N3.C1.S01: VmseCmdFineTraining Final: centerPi = 0x5E, PiEw = 0x2E, centerVref = 0x3A, vrefHeight = 0x45
N3.C1.S02: VmseCmdFineTraining Final: centerPi = 0x5B, PiEw = 0x33, centerVref = 0x3D, vrefHeight = 0x43
N3.C1.S03: VmseCmdFineTraining Final: centerPi = 0x5E, PiEw = 0x2E, centerVref = 0x41, vrefHeight = 0x41
N3.C1.S04: VmseCmdFineTraining Final: centerPi = 0x56, PiEw = 0x2F, centerVref = 0x3D, vrefHeight = 0x41
N3.C1.S05: VmseCmdFineTraining Final: centerPi = 0x5A, PiEw = 0x31, centerVref = 0x40, vrefHeight = 0x45
N3.C1.S06: VmseCmdFineTraining Final: centerPi = 0x5A, PiEw = 0x2E, centerVref = 0x3C, vrefHeight = 0x45
N3.C1.S07: VmseCmdFineTraining Final: centerPi = 0x5D, PiEw = 0x33, centerVref = 0x3D, vrefHeight = 0x47
N3.C1.S08: VmseCmdFineTraining Final: centerPi = 0x55, PiEw = 0x2F, centerVref = 0x40, vrefHeight = 0x3B
N3.C1.S09: VmseCmdFineTraining Final: centerPi = 0x59, PiEw = 0x2F, centerVref = 0x40, vrefHeight = 0x3F
N3.C1.S10: VmseCmdFineTraining Final: centerPi = 0x5A, PiEw = 0x2E, centerVref = 0x3D, vrefHeight = 0x3F
N3.C1.S11: VmseCmdFineTraining Final: centerPi = 0x55, PiEw = 0x2F, centerVref = 0x45, vrefHeight = 0x3D
N3.C1.S12: VmseCmdFineTraining Final: centerPi = 0x5B, PiEw = 0x2D, centerVref = 0x3C, vrefHeight = 0x43
N3.C1.S13: VmseCmdFineTraining Final: centerPi = 0x57, PiEw = 0x2F, centerVref = 0x3F, vrefHeight = 0x43
N3.C1.S14: VmseCmdFineTraining Final: centerPi = 0x5A, PiEw = 0x31, centerVref = 0x3C, vrefHeight = 0x43
N3.C1.S15: VmseCmdFineTraining Final: centerPi = 0x5E, PiEw = 0x2F, centerVref = 0x3F, vrefHeight = 0x3F
N3.C1.S16: VmseCmdFineTraining Final: centerPi = 0x5A, PiEw = 0x2E, centerVref = 0x3A, vrefHeight = 0x47

END - VMSE Train Command               Time         7108 ms

START - VMSE Train Read Leveling
N3.C1: VmseReadLevelFineSetup: Initial RT = 101, Initial IO Latency = 0, Initial IO Comp = 15
N3.C1: VmseRLWLFineSearchAll: Entry
N3.C1: FINE READ LEVEL DELAY
N3.C1.S00: RCVEN DELAY = 47
N3.C1.S01: RCVEN DELAY = 43
N3.C1.S02: RCVEN DELAY = 155
N3.C1.S03: RCVEN DELAY = 37
N3.C1.S04: RCVEN DELAY = 135
N3.C1.S05: RCVEN DELAY = 128
N3.C1.S06: RCVEN DELAY = 124
N3.C1.S07: RCVEN DELAY = 124
N3.C1.S08: RCVEN DELAY = 124
N3.C1.S00: READ LEVEL: FINAL RCVEN DELAY (both nibbles) = 145
N3.C1.S01: READ LEVEL: FINAL RCVEN DELAY (both nibbles) = 141
N3.C1.S02: READ LEVEL: FINAL RCVEN DELAY (both nibbles) = 124
N3.C1.S03: READ LEVEL: FINAL RCVEN DELAY (both nibbles) = 137
N3.C1.S04: READ LEVEL: FINAL RCVEN DELAY (both nibbles) = 103
N3.C1.S05: READ LEVEL: FINAL RCVEN DELAY (both nibbles) = 98
N3.C1.S06: READ LEVEL: FINAL RCVEN DELAY (both nibbles) = 94
N3.C1.S07: READ LEVEL: FINAL RCVEN DELAY (both nibbles) = 94
N3.C1.S08: READ LEVEL: FINAL RCVEN DELAY (both nibbles) = 94
N3.C1.D0.S09: READ LEVEL: FINAL RT (all ranks) = 83, FINAL IO LATENCY (all ranks) = 2
N3.C1.D1.S09: READ LEVEL: FINAL RT (all ranks) = 83, FINAL IO LATENCY (all ranks) = 2

END - VMSE Train Read Leveling         Time         263 ms

START - VMSE Train Read
Entry 0 - TrainDcc - DCCStart: 12, VocStart: 12, DCCFinal: 12, VocFinal: 12
Entry 1 - TrainDcc - DCCStart: 35, VocStart: 12, DCCFinal: 35, VocFinal: 12
N5.C1.S00: VmseCmdFineTraining Final: centerPi = 0x60, PiEw = 0x32, centerVref = 0x3C, vrefHeight = 0x43
N5.C1.S01: VmseCmdFineTraining Final: centerPi = 0x5C, PiEw = 0x2F, centerVref = 0x3E, vrefHeight = 0x43
N5.C1.S02: VmseCmdFineTraining Final: centerPi = 0x5A, PiEw = 0x33, centerVref = 0x3D, vrefHeight = 0x43
N5.C1.S03: VmseCmdFineTraining Final: centerPi = 0x5E, PiEw = 0x2F, centerVref = 0x3D, vrefHeight = 0x43
N5.C1.S04: VmseCmdFineTraining Final: centerPi = 0x56, PiEw = 0x30, centerVref = 0x3D, vrefHeight = 0x47
N5.C1.S05: VmseCmdFineTraining Final: centerPi = 0x59, PiEw = 0x2F, centerVref = 0x3B, vrefHeight = 0x43
N5.C1.S06: VmseCmdFineTraining Final: centerPi = 0x5A, PiEw = 0x30, centerVref = 0x40, vrefHeight = 0x45
N5.C1.S07: VmseCmdFineTraining Final: centerPi = 0x5D, PiEw = 0x34, centerVref = 0x39, vrefHeight = 0x45
N5.C1.S08: VmseCmdFineTraining Final: centerPi = 0x58, PiEw = 0x2F, centerVref = 0x3C, vrefHeight = 0x41
N5.C1.S09: VmseCmdFineTraining Final: centerPi = 0x5A, PiEw = 0x30, centerVref = 0x3F, vrefHeight = 0x3F
N5.C1.S10: VmseCmdFineTraining Final: centerPi = 0x5D, PiEw = 0x2D, centerVref = 0x3A, vrefHeight = 0x47
N5.C1.S11: VmseCmdFineTraining Final: centerPi = 0x56, PiEw = 0x2D, centerVref = 0x3D, vrefHeight = 0x41
N5.C1.S12: VmseCmdFineTraining Final: centerPi = 0x5C, PiEw = 0x2E, centerVref = 0x38, vrefHeight = 0x43
N5.C1.S13: VmseCmdFineTraining Final: centerPi = 0x59, PiEw = 0x2F, centerVref = 0x3C, vrefHeight = 0x43
N5.C1.S14: VmseCmdFineTraining Final: centerPi = 0x5A, PiEw = 0x32, centerVref = 0x3C, vrefHeight = 0x3F
N5.C1.S15: VmseCmdFineTraining Final: centerPi = 0x60, PiEw = 0x2F, centerVref = 0x39, vrefHeight = 0x45
N5.C1.S16: VmseCmdFineTraining Final: centerPi = 0x5B, PiEw = 0x2E, centerVref = 0x3D, vrefHeight = 0x47

END - VMSE Train Command               Time         6412 ms

START - VMSE Train Read Leveling
N5.C1: VmseReadLevelFineSetup: Initial RT = 101, Initial IO Latency = 0, Initial IO Comp = 15
N5.C1: VmseRLWLFineSearchAll: Entry
N5.C1: FINE READ LEVEL DELAY
N5.C1.S00: RCVEN DELAY = 41
N5.C1.S01: RCVEN DELAY = 40
N5.C1.S02: RCVEN DELAY = 150
N5.C1.S03: RCVEN DELAY = 35
N5.C1.S04: RCVEN DELAY = 130
N5.C1.S05: RCVEN DELAY = 122
N5.C1.S06: RCVEN DELAY = 120
N5.C1.S07: RCVEN DELAY = 116
N5.C1.S08: RCVEN DELAY = 120
N5.C1.S00: READ LEVEL: FINAL RCVEN DELAY (both nibbles) = 268
N5.C1.S01: READ LEVEL: FINAL RCVEN DELAY (both nibbles) = 265
N5.C1.S02: READ LEVEL: FINAL RCVEN DELAY (both nibbles) = 248
N5.C1.S03: READ LEVEL: FINAL RCVEN DELAY (both nibbles) = 260
N5.C1.S04: READ LEVEL: FINAL RCVEN DELAY (both nibbles) = 228
N5.C1.S05: READ LEVEL: FINAL RCVEN DELAY (both nibbles) = 218
N5.C1.S06: READ LEVEL: FINAL RCVEN DELAY (both nibbles) = 216
N5.C1.S07: READ LEVEL: FINAL RCVEN DELAY (both nibbles) = 211
N5.C1.S08: READ LEVEL: FINAL RCVEN DELAY (both nibbles) = 216
N5.C1.D0.S09: READ LEVEL: FINAL RT (all ranks) = 85, FINAL IO LATENCY (all ranks) = 4
N5.C1.D1.S09: READ LEVEL: FINAL RT (all ranks) = 85, FINAL IO LATENCY (all ranks) = 4

END - VMSE Train Read Leveling         Time         264 ms

START - VMSE Train Read
Entry 0 - TrainDcc - DCCStart: 41, VocStart: 8, DCCFinal: 25, VocFinal: 8
Entry 1 - TrainDcc - DCCStart: 12, VocStart: 8, DCCFinal: 28, VocFinal: 8
Entry 0 - TrainDcc - DCCStart: 27, VocStart: 12, DCCFinal: 19, VocFinal: 12
Entry 1 - TrainDcc - DCCStart: 52, VocStart: 12, DCCFinal: 4, VocFinal: 12

END - VMSE Train Read                  Time         4045 ms

START - VMSE Train Level Tx DQS DCC
N3.C1: VmseLevelTxDqsDccExecute: MXB DQS DCC Finished Successfully
N3.C1.S05: VmseAdjustDqsVoc: retrain DQS DCC.
N3.C1.S05:    dcc1_dqs = 0x3F, preampvoc = 0xC
N3.C1: VmseLevelTxDqsDccExecute: MXB DQS DCC Finished Successfully

END - VMSE Train Level Tx DQS DCC      Time         34 ms

START - VMSE Train Write Leveling
N3.C1: VmseWriteLevelFineSetup: Set push to data delay = 6, Global TX DQS delay = 0
N3.C1: VmseRLWLFineSearchAll: Entry
N3.C1: FINE WRITE LEVEL DELAY
N3.C1.S00: TX DQS DELAY = 64
N3.C1.S01: TX DQS DELAY = 64
N3.C1.S02: TX DQS DELAY = 80
N3.C1.S03: TX DQS DELAY = 70
N3.C1.S04: TX DQS DELAY = 96
N3.C1.S05: TX DQS DELAY = 107
N3.C1.S06: TX DQS DELAY = 106
N3.C1.S07: TX DQS DELAY = 110
N3.C1.S08: TX DQS DELAY = 104
N3.C1: VmseWriteLevelCoarseSetup: Set push to data delay = 6, Global TX DQS delay = 0
N3.C1: VmseWriteLevelCoarseExecute
N3.C1: VmseWLCoarseUpdatePD: New push to data delay = 6, New global TxDQS delay = 1
N3.C1: VmseWLCoarseUpdatePD: New push to data delay = 7, New global TxDQS delay = 0
N3.C1: VmseWLCoarseUpdatePD: New push to data delay = 7, New global TxDQS delay = 1
N3.C1: VmseWLCoarseUpdatePD: New push to data delay = 8, New global TxDQS delay = 0
N3.C1: VmseWLCoarseUpdatePD: New push to data delay = 8, New global TxDQS delay = 1
N3.C1.S00: FINAL TX DQS BEFORE TxFIFO CHECK = 161
N3.C1.S01: FINAL TX DQS BEFORE TxFIFO CHECK = 161
N3.C1.S02: FINAL TX DQS BEFORE TxFIFO CHECK = 175
N3.C1.S03: FINAL TX DQS BEFORE TxFIFO CHECK = 166
N3.C1.S04: FINAL TX DQS BEFORE TxFIFO CHECK = 193
N3.C1.S05: FINAL TX DQS BEFORE TxFIFO CHECK = 204
N3.C1.S06: FINAL TX DQS BEFORE TxFIFO CHECK = 202
N3.C1.S07: FINAL TX DQS BEFORE TxFIFO CHECK = 207
N3.C1.S08: FINAL TX DQS BEFORE TxFIFO CHECK = 202
N3.C1: ResolveTxFIFOPtrSeparation: Smallest PI (161) < MIN ALLOWED DELAY (176) 
N3.C1: VmseIncTxFifoPtrSeparation: New push to data delay = 7
N3.C1.S00: VmseIncTxFifoPtrSeparation: pi adjustment = 256, FINAL TX DQS DELAY = 417
N3.C1.S01: VmseIncTxFifoPtrSeparation: pi adjustment = 256, FINAL TX DQS DELAY = 417
N3.C1.S02: VmseIncTxFifoPtrSeparation: pi adjustment = 256, FINAL TX DQS DELAY = 431
N3.C1.S03: VmseIncTxFifoPtrSeparation: pi adjustment = 256, FINAL TX DQS DELAY = 422
N3.C1.S04: VmseIncTxFifoPtrSeparation: pi adjustment = 256, FINAL TX DQS DELAY = 449
N3.C1.S05: VmseIncTxFifoPtrSeparation: pi adjustment = 256, FINAL TX DQS DELAY = 460
N3.C1.S06: VmseIncTxFifoPtrSeparation: pi adjustment = 256, FINAL TX DQS DELAY = 458
N3.C1.S07: VmseIncTxFifoPtrSeparation: pi adjustment = 256, FINAL TX DQS DELAY = 463
N3.C1.S08: VmseIncTxFifoPtrSeparation: pi adjustment = 256, FINAL TX DQS DELAY = 458

END - VMSE Train Write Leveling        Time         252 ms

START - VMSE Train Write
N7.C1.S00: VmseCmdFineTraining Final: centerPi = 0x62, PiEw = 0x31, centerVref = 0x39, vrefHeight = 0x45
N7.C1.S01: VmseCmdFineTraining Final: centerPi = 0x60, PiEw = 0x2E, centerVref = 0x38, vrefHeight = 0x49
N7.C1.S02: VmseCmdFineTraining Final: centerPi = 0x5E, PiEw = 0x33, centerVref = 0x39, vrefHeight = 0x41
N7.C1.S03: VmseCmdFineTraining Final: centerPi = 0x61, PiEw = 0x2F, centerVref = 0x41, vrefHeight = 0x41
N7.C1.S04: VmseCmdFineTraining Final: centerPi = 0x5C, PiEw = 0x2E, centerVref = 0x38, vrefHeight = 0x45
N7.C1.S05: VmseCmdFineTraining Final: centerPi = 0x5E, PiEw = 0x30, centerVref = 0x3D, vrefHeight = 0x43
N7.C1.S06: VmseCmdFineTraining Final: centerPi = 0x60, PiEw = 0x31, centerVref = 0x38, vrefHeight = 0x4B
N7.C1.S07: VmseCmdFineTraining Final: centerPi = 0x60, PiEw = 0x33, centerVref = 0x3B, vrefHeight = 0x47
N7.C1.S08: VmseCmdFineTraining Final: centerPi = 0x59, PiEw = 0x30, centerVref = 0x3E, vrefHeight = 0x3D
N7.C1.S09: VmseCmdFineTraining Final: centerPi = 0x5F, PiEw = 0x2C, centerVref = 0x38, vrefHeight = 0x43
N7.C1.S10: VmseCmdFineTraining Final: centerPi = 0x5C, PiEw = 0x2D, centerVref = 0x3E, vrefHeight = 0x41
N7.C1.S11: VmseCmdFineTraining Final: centerPi = 0x59, PiEw = 0x29, centerVref = 0x36, vrefHeight = 0x45
N7.C1.S12: VmseCmdFineTraining Final: centerPi = 0x5D, PiEw = 0x2D, centerVref = 0x41, vrefHeight = 0x39
N7.C1.S13: VmseCmdFineTraining Final: centerPi = 0x5B, PiEw = 0x2C, centerVref = 0x3B, vrefHeight = 0x3F
N7.C1.S14: VmseCmdFineTraining Final: centerPi = 0x5D, PiEw = 0x30, centerVref = 0x39, vrefHeight = 0x43
N7.C1.S15: VmseCmdFineTraining Final: centerPi = 0x60, PiEw = 0x2D, centerVref = 0x40, vrefHeight = 0x3D
N7.C1.S16: VmseCmdFineTraining Final: centerPi = 0x5C, PiEw = 0x2E, centerVref = 0x3C, vrefHeight = 0x45
N1.C1.S00: VmseCmdFineTraining Final: centerPi = 0x62, PiEw = 0x33, centerVref = 0x39, vrefHeight = 0x45
N1.C1.S01: VmseCmdFineTraining Final: centerPi = 0x61, PiEw = 0x30, centerVref = 0x39, vrefHeight = 0x47
N1.C1.S02: VmseCmdFineTraining Final: centerPi = 0x60, PiEw = 0x35, centerVref = 0x3C, vrefHeight = 0x47
N1.C1.S03: VmseCmdFineTraining Final: centerPi = 0x5E, PiEw = 0x2F, centerVref = 0x3D, vrefHeight = 0x3D

END - VMSE Train Command               Time         7274 ms
N1.C1.S04: VmseCmdFineTraining Final: centerPi = 0x58, PiEw = 0x2F, centerVref = 0x37, vrefHeight = 0x41

START - VMSE Train Read Leveling
N1.C1.S05: VmseCmdFineTraining Final: centerPi = 0x5C, PiEw = 0x31, centerVref = 0x3A, vrefHeight = 0x47
N1.C1.S06: VmseCmdFineTraining Final: centerPi = 0x5B, PiEw = 0x2F, centerVref = 0x3C, vrefHeight = 0x47
N1.C1.S07: VmseCmdFineTraining Final: centerPi = 0x61, PiEw = 0x36, centerVref = 0x3C, vrefHeight = 0x47
N1.C1.S08: VmseCmdFineTraining Final: centerPi = 0x59, PiEw = 0x2D, centerVref = 0x36, vrefHeight = 0x3F
N1.C1.S09: VmseCmdFineTraining Final: centerPi = 0x5C, PiEw = 0x2C, centerVref = 0x3D, vrefHeight = 0x3F
N1.C1.S10: VmseCmdFineTraining Final: centerPi = 0x5D, PiEw = 0x2D, centerVref = 0x3A, vrefHeight = 0x45
N1.C1.S11: VmseCmdFineTraining Final: centerPi = 0x57, PiEw = 0x2E, centerVref = 0x3B, vrefHeight = 0x45
N1.C1.S12: VmseCmdFineTraining Final: centerPi = 0x5E, PiEw = 0x2F, centerVref = 0x38, vrefHeight = 0x43
N1.C1.S13: VmseCmdFineTraining Final: centerPi = 0x59, PiEw = 0x2F, centerVref = 0x3D, vrefHeight = 0x41
N7.C1: VmseReadLevelFineSetup: Initial RT = 101, Initial IO Latency = 0, Initial IO Comp = 15
N1.C1.S14: VmseCmdFineTraining Final: centerPi = 0x5D, PiEw = 0x30, centerVref = 0x3B, vrefHeight = 0x43
N1.C1.S15: VmseCmdFineTraining Final: centerPi = 0x65, PiEw = 0x2F, centerVref = 0x36, vrefHeight = 0x47
N1.C1.S16: VmseCmdFineTraining Final: centerPi = 0x5D, PiEw = 0x2E, centerVref = 0x37, vrefHeight = 0x47
N7.C1: VmseRLWLFineSearchAll: Entry
N7.C1: FINE READ LEVEL DELAY
N7.C1.S00: RCVEN DELAY = 51
N7.C1.S01: RCVEN DELAY = 48
N7.C1.S02: RCVEN DELAY = 35
N7.C1.S03: RCVEN DELAY = 43
N7.C1.S04: RCVEN DELAY = 142
N7.C1.S05: RCVEN DELAY = 134
N7.C1.S06: RCVEN DELAY = 131
N7.C1.S07: RCVEN DELAY = 125
N7.C1.S08: RCVEN DELAY = 125
N7.C1.S00: READ LEVEL: FINAL RCVEN DELAY (both nibbles) = 278
N7.C1.S01: READ LEVEL: FINAL RCVEN DELAY (both nibbles) = 272
N7.C1.S02: READ LEVEL: FINAL RCVEN DELAY (both nibbles) = 261
N7.C1.S03: READ LEVEL: FINAL RCVEN DELAY (both nibbles) = 268
N7.C1.S04: READ LEVEL: FINAL RCVEN DELAY (both nibbles) = 237
N7.C1.S05: READ LEVEL: FINAL RCVEN DELAY (both nibbles) = 232
N7.C1.S06: READ LEVEL: FINAL RCVEN DELAY (both nibbles) = 229
N7.C1.S07: READ LEVEL: FINAL RCVEN DELAY (both nibbles) = 220
N7.C1.S08: READ LEVEL: FINAL RCVEN DELAY (both nibbles) = 220
N7.C1.D0.S09: READ LEVEL: FINAL RT (all ranks) = 85, FINAL IO LATENCY (all ranks) = 4
N7.C1.D1.S09: READ LEVEL: FINAL RT (all ranks) = 85, FINAL IO LATENCY (all ranks) = 4

END - VMSE Train Read Leveling         Time         275 ms

START - VMSE Train Read

END - VMSE Train Command               Time         7346 ms

START - VMSE Train Read Leveling
Checkpoint Code: Socket 0, 0xB6, 0x4E, 0x0000
N1.C1: VmseReadLevelFineSetup: Initial RT = 101, Initial IO Latency = 0, Initial IO Comp = 15
N1.C1: VmseRLWLFineSearchAll: Entry
N1.C1: FINE READ LEVEL DELAY
N1.C1.S00: RCVEN DELAY = 39
N1.C1.S01: RCVEN DELAY = 38
N1.C1.S02: RCVEN DELAY = 150
N1.C1.S03: RCVEN DELAY = 35
N1.C1.S04: RCVEN DELAY = 132
N1.C1.S05: RCVEN DELAY = 121
N1.C1.S06: RCVEN DELAY = 117
N1.C1.S07: RCVEN DELAY = 117
N1.C1.S08: RCVEN DELAY = 115
N1.C1.S00: READ LEVEL: FINAL RCVEN DELAY (both nibbles) = 135
N1.C1.S01: READ LEVEL: FINAL RCVEN DELAY (both nibbles) = 135
N1.C1.S02: READ LEVEL: FINAL RCVEN DELAY (both nibbles) = 119
N1.C1.S03: READ LEVEL: FINAL RCVEN DELAY (both nibbles) = 131
N1.C1.S04: READ LEVEL: FINAL RCVEN DELAY (both nibbles) = 100
N1.C1.S05: READ LEVEL: FINAL RCVEN DELAY (both nibbles) = 89
N1.C1.S06: READ LEVEL: FINAL RCVEN DELAY (both nibbles) = 86
N1.C1.S07: READ LEVEL: FINAL RCVEN DELAY (both nibbles) = 85
N1.C1.S08: READ LEVEL: FINAL RCVEN DELAY (both nibbles) = 82
N1.C1.D0.S09: READ LEVEL: FINAL RT (all ranks) = 83, FINAL IO LATENCY (all ranks) = 2
N1.C1.D1.S09: READ LEVEL: FINAL RT (all ranks) = 83, FINAL IO LATENCY (all ranks) = 2

END - VMSE Train Read Leveling         Time         268 ms
Entry 0 - TrainDcc - DCCStart: 33, VocStart: 11, DCCFinal: 41, VocFinal: 11

START - VMSE Train Read
Entry 1 - TrainDcc - DCCStart: 31, VocStart: 11, DCCFinal: 31, VocFinal: 11
Checkpoint Code: Socket 0, 0xB6, 0x50, 0x0000
Entry 2 - TrainDcc - DCCStart: 48, VocStart: 16, DCCFinal: 48, VocFinal: 16
Entry 3 - TrainDcc - DCCStart: 33, VocStart: 17, DCCFinal: 33, VocFinal: 17
Entry 4 - TrainDcc - DCCStart: 24, VocStart: 14, DCCFinal: 24, VocFinal: 17
Entry 5 - TrainDcc - DCCStart: 18, VocStart: 12, DCCFinal: 18, VocFinal: 12
Entry 6 - TrainDcc - DCCStart: 34, VocStart: 7, DCCFinal: 34, VocFinal: 7
Entry 7 - TrainDcc - DCCStart: 11, VocStart: 11, DCCFinal: 11, VocFinal: 11
Entry 8 - TrainDcc - DCCStart: 18, VocStart: 14, DCCFinal: 18, VocFinal: 14
N3.C1.S00: VmseWriteTraining Final: centerPi = 0x39, PiEw = 0x27, centerVref = 0x43, vrefHeight = 0x28
N3.C1.S01: VmseWriteTraining Final: centerPi = 0x3A, PiEw = 0x27, centerVref = 0x41, vrefHeight = 0x28
N3.C1.S02: VmseWriteTraining Final: centerPi = 0x39, PiEw = 0x24, centerVref = 0x3C, vrefHeight = 0x2A
N3.C1.S03: VmseWriteTraining Final: centerPi = 0x37, PiEw = 0x2A, centerVref = 0x40, vrefHeight = 0x2A
N3.C1.S04: VmseWriteTraining Final: centerPi = 0x3E, PiEw = 0x28, centerVref = 0x3C, vrefHeight = 0x2A
N3.C1.S05: VmseWriteTraining Final: centerPi = 0x3D, PiEw = 0x28, centerVref = 0x42, vrefHeight = 0x26
N3.C1.S06: VmseWriteTraining Final: centerPi = 0x3B, PiEw = 0x25, centerVref = 0x3E, vrefHeight = 0x26
N3.C1.S07: VmseWriteTraining Final: centerPi = 0x3D, PiEw = 0x25, centerVref = 0x42, vrefHeight = 0x28
N3.C1.S08: VmseWriteTraining Final: centerPi = 0x3A, PiEw = 0x27, centerVref = 0x44, vrefHeight = 0x26
N3.C1.S09: VmseWriteTraining Final: centerPi = 0x3C, PiEw = 0x28, centerVref = 0x3E, vrefHeight = 0x28
N3.C1.S10: VmseWriteTraining Final: centerPi = 0x39, PiEw = 0x24, centerVref = 0x40, vrefHeight = 0x28
N3.C1.S11: VmseWriteTraining Final: centerPi = 0x3B, PiEw = 0x29, centerVref = 0x40, vrefHeight = 0x2A
N3.C1.S12: VmseWriteTraining Final: centerPi = 0x40, PiEw = 0x23, centerVref = 0x42, vrefHeight = 0x26
N3.C1.S13: VmseWriteTraining Final: centerPi = 0x3F, PiEw = 0x28, centerVref = 0x40, vrefHeight = 0x26
N3.C1.S14: VmseWriteTraining Final: centerPi = 0x3E, PiEw = 0x25, centerVref = 0x3F, vrefHeight = 0x2A
N3.C1.S15: VmseWriteTraining Final: centerPi = 0x3E, PiEw = 0x27, centerVref = 0x46, vrefHeight = 0x26
N3.C1.S16: VmseWriteTraining Final: centerPi = 0x38, PiEw = 0x29, centerVref = 0x45, vrefHeight = 0x28
N3.C1.S17: VmseWriteTraining Final: centerPi = 0x39, PiEw = 0x28, centerVref = 0x3F, vrefHeight = 0x28
N3.C1.S18: VmseWriteTraining Final: centerPi = 0x37, PiEw = 0x25, centerVref = 0x40, vrefHeight = 0x28
N3.C1.S19: VmseWriteTraining Final: centerPi = 0x37, PiEw = 0x2B, centerVref = 0x43, vrefHeight = 0x2C
N3.C1.S20: VmseWriteTraining Final: centerPi = 0x3E, PiEw = 0x28, centerVref = 0x3B, vrefHeight = 0x28
N3.C1.S21: VmseWriteTraining Final: centerPi = 0x3E, PiEw = 0x22, centerVref = 0x3F, vrefHeight = 0x28
N3.C1.S22: VmseWriteTraining Final: centerPi = 0x3C, PiEw = 0x27, centerVref = 0x43, vrefHeight = 0x28
N3.C1.S23: VmseWriteTraining Final: centerPi = 0x3C, PiEw = 0x28, centerVref = 0x3F, vrefHeight = 0x28
N3.C1.S24: VmseWriteTraining Final: centerPi = 0x38, PiEw = 0x27, centerVref = 0x43, vrefHeight = 0x28
N3.C1.S25: VmseWriteTraining Final: centerPi = 0x3A, PiEw = 0x29, centerVref = 0x3F, vrefHeight = 0x2A
N3.C1.S26: VmseWriteTraining Final: centerPi = 0x39, PiEw = 0x27, centerVref = 0x41, vrefHeight = 0x2A
N3.C1.S27: VmseWriteTraining Final: centerPi = 0x39, PiEw = 0x2F, centerVref = 0x40, vrefHeight = 0x2E
N3.C1.S28: VmseWriteTraining Final: centerPi = 0x3B, PiEw = 0x27, centerVref = 0x43, vrefHeight = 0x26
N3.C1.S29: VmseWriteTraining Final: centerPi = 0x3B, PiEw = 0x28, centerVref = 0x43, vrefHeight = 0x28
N3.C1.S30: VmseWriteTraining Final: centerPi = 0x3D, PiEw = 0x27, centerVref = 0x41, vrefHeight = 0x28
N3.C1.S31: VmseWriteTraining Final: centerPi = 0x3D, PiEw = 0x2D, centerVref = 0x42, vrefHeight = 0x2A
N3.C1.S32: VmseWriteTraining Final: centerPi = 0x3C, PiEw = 0x28, centerVref = 0x43, vrefHeight = 0x28
N3.C1.S33: VmseWriteTraining Final: centerPi = 0x3C, PiEw = 0x28, centerVref = 0x3D, vrefHeight = 0x28
N3.C1.S34: VmseWriteTraining Final: centerPi = 0x3C, PiEw = 0x29, centerVref = 0x3F, vrefHeight = 0x2A
N3.C1.S35: VmseWriteTraining Final: centerPi = 0x3A, PiEw = 0x2A, centerVref = 0x42, vrefHeight = 0x2C
N3.C1.S36: VmseWriteTraining Final: centerPi = 0x3F, PiEw = 0x26, centerVref = 0x3F, vrefHeight = 0x2A
N3.C1.S37: VmseWriteTraining Final: centerPi = 0x3E, PiEw = 0x27, centerVref = 0x3F, vrefHeight = 0x2A
N3.C1.S38: VmseWriteTraining Final: centerPi = 0x3E, PiEw = 0x26, centerVref = 0x3C, vrefHeight = 0x2A
N3.C1.S39: VmseWriteTraining Final: centerPi = 0x3F, PiEw = 0x25, centerVref = 0x40, vrefHeight = 0x2A
N3.C1.S40: VmseWriteTraining Final: centerPi = 0x3A, PiEw = 0x27, centerVref = 0x40, vrefHeight = 0x26
N3.C1.S41: VmseWriteTraining Final: centerPi = 0x3B, PiEw = 0x27, centerVref = 0x3F, vrefHeight = 0x26
N3.C1.S42: VmseWriteTraining Final: centerPi = 0x39, PiEw = 0x1D, centerVref = 0x3F, vrefHeight = 0x24
N3.C1.S43: VmseWriteTraining Final: centerPi = 0x37, PiEw = 0x23, centerVref = 0x45, vrefHeight = 0x24
N3.C1.S44: VmseWriteTraining Final: centerPi = 0x3F, PiEw = 0x23, centerVref = 0x3F, vrefHeight = 0x28
N3.C1.S45: VmseWriteTraining Final: centerPi = 0x3C, PiEw = 0x1F, centerVref = 0x41, vrefHeight = 0x22
N3.C1.S46: VmseWriteTraining Final: centerPi = 0x3E, PiEw = 0x21, centerVref = 0x3F, vrefHeight = 0x24
N3.C1.S47: VmseWriteTraining Final: centerPi = 0x3D, PiEw = 0x2A, centerVref = 0x40, vrefHeight = 0x26
N3.C1.S48: VmseWriteTraining Final: centerPi = 0x3B, PiEw = 0x28, centerVref = 0x3F, vrefHeight = 0x24
N3.C1.S49: VmseWriteTraining Final: centerPi = 0x3D, PiEw = 0x26, centerVref = 0x3F, vrefHeight = 0x2A
N3.C1.S50: VmseWriteTraining Final: centerPi = 0x3D, PiEw = 0x27, centerVref = 0x40, vrefHeight = 0x2C
N3.C1.S51: VmseWriteTraining Final: centerPi = 0x38, PiEw = 0x2A, centerVref = 0x40, vrefHeight = 0x2C
N3.C1.S52: VmseWriteTraining Final: centerPi = 0x41, PiEw = 0x27, centerVref = 0x41, vrefHeight = 0x2C
N3.C1.S53: VmseWriteTraining Final: centerPi = 0x3D, PiEw = 0x20, centerVref = 0x3F, vrefHeight = 0x24
N3.C1.S54: VmseWriteTraining Final: centerPi = 0x3E, PiEw = 0x28, centerVref = 0x3D, vrefHeight = 0x2A
N3.C1.S55: VmseWriteTraining Final: centerPi = 0x3D, PiEw = 0x24, centerVref = 0x41, vrefHeight = 0x26
N3.C1.S56: VmseWriteTraining Final: centerPi = 0x3C, PiEw = 0x26, centerVref = 0x44, vrefHeight = 0x26
N3.C1.S57: VmseWriteTraining Final: centerPi = 0x40, PiEw = 0x26, centerVref = 0x3E, vrefHeight = 0x28
N3.C1.S58: VmseWriteTraining Final: centerPi = 0x3E, PiEw = 0x29, centerVref = 0x40, vrefHeight = 0x2A
N3.C1.S59: VmseWriteTraining Final: centerPi = 0x3E, PiEw = 0x2C, centerVref = 0x41, vrefHeight = 0x2C
N3.C1.S60: VmseWriteTraining Final: centerPi = 0x43, PiEw = 0x25, centerVref = 0x3B, vrefHeight = 0x26
N3.C1.S61: VmseWriteTraining Final: centerPi = 0x43, PiEw = 0x26, centerVref = 0x3F, vrefHeight = 0x24
N3.C1.S62: VmseWriteTraining Final: centerPi = 0x42, PiEw = 0x24, centerVref = 0x3E, vrefHeight = 0x2A
N3.C1.S63: VmseWriteTraining Final: centerPi = 0x41, PiEw = 0x22, centerVref = 0x41, vrefHeight = 0x28
N3.C1.S64: VmseWriteTraining Final: centerPi = 0x3A, PiEw = 0x28, centerVref = 0x43, vrefHeight = 0x28
N3.C1.S65: VmseWriteTraining Final: centerPi = 0x39, PiEw = 0x26, centerVref = 0x40, vrefHeight = 0x2A
N3.C1.S66: VmseWriteTraining Final: centerPi = 0x38, PiEw = 0x24, centerVref = 0x44, vrefHeight = 0x28
N3.C1.S67: VmseWriteTraining Final: centerPi = 0x3A, PiEw = 0x27, centerVref = 0x3E, vrefHeight = 0x2C
N3.C1.S68: VmseWriteTraining Final: centerPi = 0x3E, PiEw = 0x26, centerVref = 0x42, vrefHeight = 0x28
N3.C1.S69: VmseWriteTraining Final: centerPi = 0x3C, PiEw = 0x23, centerVref = 0x41, vrefHeight = 0x28
N3.C1.S70: VmseWriteTraining Final: centerPi = 0x3B, PiEw = 0x22, centerVref = 0x3E, vrefHeight = 0x28
N3.C1.S71: VmseWriteTraining Final: centerPi = 0x3D, PiEw = 0x25, centerVref = 0x40, vrefHeight = 0x2A

END - VMSE Train Write                 Time         2120 ms
N3: 
Total VMSE trainings latency = 14272 ms
N2: PostVmseTraining
N2.C0: PostVmseTraining
N2.C0: PostVMSE Training VMSE Health Check Passed
N2.C1: PostVmseTraining
N2.C2: PostVMSE Training VMSE Health Check Passed
N2: PreDdrTraining
N2: PreDdrTraining[QCRM=OFF]
N2.C0.D0: CheckRankPopLocal: dimmPresent: 1, numRanks = 2
N2.C0.D0.R0: CheckRankPopLocal: mapOut: 0, enabled = 1
N2.C0.D0.R1: CheckRankPopLocal: mapOut: 0, enabled = 1
N2.C0.D1: CheckRankPopLocal: dimmPresent: 1, numRanks = 2
N2.C0.D1.R0: CheckRankPopLocal: mapOut: 0, enabled = 1
N2.C0.D1.R1: CheckRankPopLocal: mapOut: 0, enabled = 1
N2.C0.D2: CheckRankPopLocal: dimmPresent: 0, numRanks = 0
N2.C0.D0: CheckRankPopLocal: amap: 0x00000000
N2.C0.D1: CheckRankPopLocal: amap: 0x00000000
N2.C0.D2: CheckRankPopLocal: amap: 0x00000000
N2.C1.D0: CheckRankPopLocal: dimmPresent: 1, numRanks = 2
N2.C1.D0.R0: CheckRankPopLocal: mapOut: 0, enabled = 1
N2.C1.D0.R1: CheckRankPopLocal: mapOut: 0, enabled = 1
N2.C1.D1: CheckRankPopLocal: dimmPresent: 1, numRanks = 2
N2.C1.D1.R0: CheckRankPopLocal: mapOut: 0, enabled = 1
N2.C1.D1.R1: CheckRankPopLocal: mapOut: 0, enabled = 1
N2.C1.D2: CheckRankPopLocal: dimmPresent: 0, numRanks = 0
N2.C1.D0: CheckRankPopLocal: amap: 0x00000000
N2.C1.D1: CheckRankPopLocal: amap: 0x00000000
N2.C1.D2: CheckRankPopLocal: amap: 0x00000000
N2.C2.D0: CheckRankPopLocal: dimmPresent: 1, numRanks = 2
N2.C2.D0.R0: CheckRankPopLocal: mapOut: 0, enabled = 1
N2.C2.D0.R1: CheckRankPopLocal: mapOut: 0, enabled = 1
N2.C2.D1: CheckRankPopLocal: dimmPresent: 1, numRanks = 2
N2.C2.D1.R0: CheckRankPopLocal: mapOut: 0, enabled = 1
N2.C2.D1.R1: CheckRankPopLocal: mapOut: 0, enabled = 1
N2.C2.D2: CheckRankPopLocal: dimmPresent: 0, numRanks = 0
N2.C2.D0: CheckRankPopLocal: amap: 0x00000000
N2.C2.D1: CheckRankPopLocal: amap: 0x00000000
N2.C2.D2: CheckRankPopLocal: amap: 0x00000000
N2.C3.D0: CheckRankPopLocal: dimmPresent: 1, numRanks = 2
N2.C3.D0.R0: CheckRankPopLocal: mapOut: 0, enabled = 1
N2.C3.D0.R1: CheckRankPopLocal: mapOut: 0, enabled = 1
N2.C3.D1: CheckRankPopLocal: dimmPresent: 1, numRanks = 2
N2.C3.D1.R0: CheckRankPopLocal: mapOut: 0, enabled = 1
N2.C3.D1.R1: CheckRankPopLocal: mapOut: 0, enabled = 1
N2.C3.D2: CheckRankPopLocal: dimmPresent: 0, numRanks = 0
N2.C3.D0: CheckRankPopLocal: amap: 0x00000000
N2.C3.D1: CheckRankPopLocal: amap: 0x00000000
N2.C3.D2: CheckRankPopLocal: amap: 0x00000000
N2.C0: JCK cmd timing = 3N
N2.C0: RdCmd2DataValidLatency = 20, (dlyFrmS = 15, clEff = 10, earlyCas = 0, selNTiming = 2)
N2.C0: CLK0_CFG: 0x000FFF30
N2.C0: DDR_RANKCTL: 0x000FEA40
N2.C0: MCODT = 0 ( 50 ohms)
N2.C0.D0.R0: Rtt_wr = 120, Rtt_nom = 20

END - VMSE Train Read                  Time         3982 ms
N2.C0.D0.R1: Rtt_wr = 120, Rtt_nom = 0

START - VMSE Train Level Tx DQS DCC
N2.C0.D1.R0: Rtt_wr = 120, Rtt_nom = 20
N2.C0.D1.R1: Rtt_wr = 120, Rtt_nom = 0
N5.C1: VmseLevelTxDqsDccExecute: MXB DQS DCC Finished Successfully
N2.C0: ODTRDCTL00 = 0x01000104

END - VMSE Train Level Tx DQS DCC      Time         15 ms
N2.C0: ODTRDCTL01 = 0x00000001

START - VMSE Train Write Leveling
N2.C0: ODTWRCTL00 = 0x05000185
N5.C1: VmseWriteLevelFineSetup: Set push to data delay = 6, Global TX DQS delay = 0
N2.C0: ODTWRCTL01 = 0x00000009
N2.C1: RdCmd2DataValidLatency = 20, (dlyFrmS = 15, clEff = 10, earlyCas = 0, selNTiming = 2)
N5.C1: VmseRLWLFineSearchAll: Entry
N2.C1: CLK0_CFG: 0x000FF330
N5.C1: FINE WRITE LEVEL DELAY
N2.C1: DDR_RANKCTL: 0x000FEA40
N5.C1.S00: TX DQS DELAY = 65
N2.C1: MCODT = 0 ( 50 ohms)
N5.C1.S01: TX DQS DELAY = 65
N2.C1.D0.R0: Rtt_wr = 120, Rtt_nom = 20
N5.C1.S02: TX DQS DELAY = 79
N2.C1.D0.R1: Rtt_wr = 120, Rtt_nom = 0
N5.C1.S03: TX DQS DELAY = 70
N2.C1.D1.R0: Rtt_wr = 120, Rtt_nom = 20
N5.C1.S04: TX DQS DELAY = 99
N2.C1.D1.R1: Rtt_wr = 120, Rtt_nom = 0
N5.C1.S05: TX DQS DELAY = 103
N2.C1: ODTRDCTL00 = 0x01000104
N5.C1.S06: TX DQS DELAY = 109
N2.C1: ODTRDCTL01 = 0x00000001
N5.C1.S07: TX DQS DELAY = 111
N2.C1: ODTWRCTL00 = 0x05000185
N5.C1.S08: TX DQS DELAY = 107
N2.C1: ODTWRCTL01 = 0x00000009
N5.C1: VmseWriteLevelCoarseSetup: Set push to data delay = 6, Global TX DQS delay = 0
N2.C2: JCK cmd timing = 3N
N5.C1: VmseWriteLevelCoarseExecute
N2.C2: RdCmd2DataValidLatency = 20, (dlyFrmS = 15, clEff = 10, earlyCas = 0, selNTiming = 2)
N5.C1: VmseWLCoarseUpdatePD: New push to data delay = 6, New global TxDQS delay = 1
N2.C2: CLK0_CFG: 0x000FFF30
N5.C1: VmseWLCoarseUpdatePD: New push to data delay = 7, New global TxDQS delay = 0
N2.C2: DDR_RANKCTL: 0x000FEA40
N5.C1: VmseWLCoarseUpdatePD: New push to data delay = 7, New global TxDQS delay = 1
N2.C2: MCODT = 0 ( 50 ohms)
N5.C1: VmseWLCoarseUpdatePD: New push to data delay = 8, New global TxDQS delay = 0
N2.C2.D0.R0: Rtt_wr = 120, Rtt_nom = 20
N5.C1: VmseWLCoarseUpdatePD: New push to data delay = 8, New global TxDQS delay = 1
N2.C2.D0.R1: Rtt_wr = 120, Rtt_nom = 0
N5.C1: VmseWLCoarseUpdatePD: New push to data delay = 9, New global TxDQS delay = 0
N2.C2.D1.R0: Rtt_wr = 120, Rtt_nom = 20
N5.C1.S00: FINAL TX DQS BEFORE TxFIFO CHECK = 35
N2.C2.D1.R1: Rtt_wr = 120, Rtt_nom = 0
N5.C1.S01: FINAL TX DQS BEFORE TxFIFO CHECK = 35
N2.C2: ODTRDCTL00 = 0x01000104
N5.C1.S02: FINAL TX DQS BEFORE TxFIFO CHECK = 47
N2.C2: ODTRDCTL01 = 0x00000001
N5.C1.S03: FINAL TX DQS BEFORE TxFIFO CHECK = 40
N2.C2: ODTWRCTL00 = 0x05000185
N5.C1.S04: FINAL TX DQS BEFORE TxFIFO CHECK = 68
N2.C2: ODTWRCTL01 = 0x00000009
N5.C1.S05: FINAL TX DQS BEFORE TxFIFO CHECK = 72
N2.C3: RdCmd2DataValidLatency = 20, (dlyFrmS = 15, clEff = 10, earlyCas = 0, selNTiming = 2)
N5.C1.S06: FINAL TX DQS BEFORE TxFIFO CHECK = 80
N2.C3: CLK0_CFG: 0x000FF330
N5.C1.S07: FINAL TX DQS BEFORE TxFIFO CHECK = 80
N2.C3: DDR_RANKCTL: 0x000FEA40
N5.C1.S08: FINAL TX DQS BEFORE TxFIFO CHECK = 76
N2.C3: MCODT = 0 ( 50 ohms)
N5.C1: ResolveTxFIFOPtrSeparation: Smallest PI (35) < MIN ALLOWED DELAY (176) 
N2.C3.D0.R0: Rtt_wr = 120, Rtt_nom = 20
N5.C1: VmseIncTxFifoPtrSeparation: New push to data delay = 8
N2.C3.D0.R1: Rtt_wr = 120, Rtt_nom = 0
N5.C1.S00: VmseIncTxFifoPtrSeparation: pi adjustment = 128, FINAL TX DQS DELAY = 291
N2.C3.D1.R0: Rtt_wr = 120, Rtt_nom = 20
N5.C1.S01: VmseIncTxFifoPtrSeparation: pi adjustment = 128, FINAL TX DQS DELAY = 291
N2.C3.D1.R1: Rtt_wr = 120, Rtt_nom = 0
N5.C1.S02: VmseIncTxFifoPtrSeparation: pi adjustment = 128, FINAL TX DQS DELAY = 303
N2.C3: ODTRDCTL00 = 0x01000104
N5.C1.S03: VmseIncTxFifoPtrSeparation: pi adjustment = 128, FINAL TX DQS DELAY = 296
N2.C3: ODTRDCTL01 = 0x00000001
N5.C1.S04: VmseIncTxFifoPtrSeparation: pi adjustment = 128, FINAL TX DQS DELAY = 324
N2.C3: ODTWRCTL00 = 0x05000185
N5.C1.S05: VmseIncTxFifoPtrSeparation: pi adjustment = 128, FINAL TX DQS DELAY = 328
N2.C3: ODTWRCTL01 = 0x00000009
N5.C1.S06: VmseIncTxFifoPtrSeparation: pi adjustment = 128, FINAL TX DQS DELAY = 336
N2.C0.D0: PreDdrTraining: Program dimmmtr 0xC502D
N5.C1.S07: VmseIncTxFifoPtrSeparation: pi adjustment = 128, FINAL TX DQS DELAY = 336
N2.C0.D1: PreDdrTraining: Program dimmmtr 0xC502D
N5.C1.S08: VmseIncTxFifoPtrSeparation: pi adjustment = 128, FINAL TX DQS DELAY = 332
N2.C1.D0: PreDdrTraining: Program dimmmtr 0xC502D

END - VMSE Train Write Leveling        Time         427 ms
N2.C1.D1: PreDdrTraining: Program dimmmtr 0xC502D

START - VMSE Train Write
N2.C2.D0: PreDdrTraining: Program dimmmtr 0xC502D
N2.C2.D1: PreDdrTraining: Program dimmmtr 0xC502D
N2.C3.D0: PreDdrTraining: Program dimmmtr 0xC502D
N2.C3.D1: PreDdrTraining: Program dimmmtr 0xC502D
N2: InitializeDdrioForUse
N2: SetupJckForBL: setting BL to 8
N2.C0: ODTTIMCTL (INIT RELAX) rdwidth = 10 rddly = 0 wrwidth = 8 wrdly = 0
N2.C1: ODTTIMCTL (INIT RELAX) rdwidth = 10 rddly = 0 wrwidth = 8 wrdly = 0
N2.C2: ODTTIMCTL (INIT RELAX) rdwidth = 10 rddly = 0 wrwidth = 8 wrdly = 0
N2.C3: ODTTIMCTL (INIT RELAX) rdwidth = 10 rddly = 0 wrwidth = 8 wrdly = 0
N2: JckDdrTraining
N2: InitializeDdrioForTraining: QCRM Disabled
N2.C0: InitializeDdrioForTraining: cleff = 10
N2.C0: InitializeDdrioForTraining: cwleff = 8
N2.C0: InitializeDdrioForTraining: initial ddrInitIndexRx = 4 ddrInitIndexTx = 2
N2.C0: InitializeDdrioForTraining: initial RdCmd2RcvEnLatency = 5
N2.C0: InitializeDdrioForTraining: initial RdPtrOffsetRcvEn = 4
N2.C0: InitializeDdrioForTraining: initial rkrdptroffsetrcvenb = 6
N2.C0: InitializeDdrioForTraining: initial rkrdptroffsetdrvenrcvenb = 5
N2.C0: InitializeDdrioForTraining: initial WrCmd2DqsStartLatency = 4
N2.C0: InitializeDdrioForTraining: initial RdPtrOffsetDqs = 10
N2.C0: InitializeDdrioForTraining: initial RdCmd2RcvEnLatency = 5
N2.C0: InitializeDdrioForTraining: initial WrCmd2DqsStartLatency = 4
N2.C0: InitializeDdrioForTraining: initial RdPtrOffsetRcvEn = 4
N2.C0: InitializeDdrioForTraining: initial RdPtrOffsetDqs = 6
N2.C0: InitializeDdrioForTraining: initial RdPtrOffsetDq = 5
N2.C1: InitializeDdrioForTraining: cleff = 10
N2.C1: InitializeDdrioForTraining: cwleff = 8
N2.C1: InitializeDdrioForTraining: initial ddrInitIndexRx = 4 ddrInitIndexTx = 2
N2.C1: InitializeDdrioForTraining: initial RdCmd2RcvEnLatency = 5
N2.C1: InitializeDdrioForTraining: initial RdPtrOffsetRcvEn = 4
N2.C1: InitializeDdrioForTraining: initial rkrdptroffsetrcvenb = 6
N2.C1: InitializeDdrioForTraining: initial rkrdptroffsetdrvenrcvenb = 5
N2.C1: InitializeDdrioForTraining: initial WrCmd2DqsStartLatency = 4
N2.C1: InitializeDdrioForTraining: initial RdPtrOffsetDqs = 10
N2.C1: InitializeDdrioForTraining: initial RdCmd2RcvEnLatency = 5
N2.C1: InitializeDdrioForTraining: initial WrCmd2DqsStartLatency = 4
N2.C1: InitializeDdrioForTraining: initial RdPtrOffsetRcvEn = 4
N2.C1: InitializeDdrioForTraining: initial RdPtrOffsetDqs = 6
N2.C1: InitializeDdrioForTraining: initial RdPtrOffsetDq = 5
N2.C2: InitializeDdrioForTraining: cleff = 10
N2.C2: InitializeDdrioForTraining: cwleff = 8
N2.C2: InitializeDdrioForTraining: initial ddrInitIndexRx = 4 ddrInitIndexTx = 2
N2.C2: InitializeDdrioForTraining: initial RdCmd2RcvEnLatency = 5
N2.C2: InitializeDdrioForTraining: initial RdPtrOffsetRcvEn = 4
N2.C2: InitializeDdrioForTraining: initial rkrdptroffsetrcvenb = 6
N2.C2: InitializeDdrioForTraining: initial rkrdptroffsetdrvenrcvenb = 5
N2.C2: InitializeDdrioForTraining: initial WrCmd2DqsStartLatency = 4
N2.C2: InitializeDdrioForTraining: initial RdPtrOffsetDqs = 10
N2.C2: InitializeDdrioForTraining: initial RdCmd2RcvEnLatency = 5
N2.C2: InitializeDdrioForTraining: initial WrCmd2DqsStartLatency = 4
N2.C2: InitializeDdrioForTraining: initial RdPtrOffsetRcvEn = 4
N2.C2: InitializeDdrioForTraining: initial RdPtrOffsetDqs = 6
N2.C2: InitializeDdrioForTraining: initial RdPtrOffsetDq = 5
N2.C3: InitializeDdrioForTraining: cleff = 10
N2.C3: InitializeDdrioForTraining: cwleff = 8
N2.C3: InitializeDdrioForTraining: initial ddrInitIndexRx = 4 ddrInitIndexTx = 2
N2.C3: InitializeDdrioForTraining: initial RdCmd2RcvEnLatency = 5
N2.C3: InitializeDdrioForTraining: initial RdPtrOffsetRcvEn = 4
N2.C3: InitializeDdrioForTraining: initial rkrdptroffsetrcvenb = 6
N2.C3: InitializeDdrioForTraining: initial rkrdptroffsetdrvenrcvenb = 5
N2.C3: InitializeDdrioForTraining: initial WrCmd2DqsStartLatency = 4
N2.C3: InitializeDdrioForTraining: initial RdPtrOffsetDqs = 10
N2.C3: InitializeDdrioForTraining: initial RdCmd2RcvEnLatency = 5
N2.C3: InitializeDdrioForTraining: initial WrCmd2DqsStartLatency = 4
N2.C3: InitializeDdrioForTraining: initial RdPtrOffsetRcvEn = 4
N2.C3: InitializeDdrioForTraining: initial RdPtrOffsetDqs = 6
N2.C3: InitializeDdrioForTraining: initial RdPtrOffsetDq = 5
N2: DdrClockStopWa
N2: JckSetOdtRelaxTiming:
N2.C0: ODTTIMCTL (INIT RELAX) rdwidth = 10 rddly = 0 wrwidth = 8 wrdly = 0
N2.C0.S00: DDRIOHSIODATA0_LATCTL1 = 08040804
N2.C0.S01: DDRIOHSIODATA0_LATCTL1 = 08040804
N2.C0.S02: DDRIOHSIODATA0_LATCTL1 = 08040804
N2.C0.S03: DDRIOHSIODATA0_LATCTL1 = 08040804
N2.C0.S04: DDRIOHSIODATA0_LATCTL1 = 08040804
N2.C0.S05: DDRIOHSIODATA0_LATCTL1 = 08040804
N2.C0.S06: DDRIOHSIODATA0_LATCTL1 = 08040804
N2.C0.S07: DDRIOHSIODATA0_LATCTL1 = 08040804
N2.C0.S08: DDRIOHSIODATA0_LATCTL1 = 08040804
N2.C1: ODTTIMCTL (INIT RELAX) rdwidth = 10 rddly = 0 wrwidth = 8 wrdly = 0
N2.C1.S00: DDRIOHSIODATA0_LATCTL1 = 08040804
N2.C1.S01: DDRIOHSIODATA0_LATCTL1 = 08040804
N2.C1.S02: DDRIOHSIODATA0_LATCTL1 = 08040804
N2.C1.S03: DDRIOHSIODATA0_LATCTL1 = 08040804
N2.C1.S04: DDRIOHSIODATA0_LATCTL1 = 08040804
N2.C1.S05: DDRIOHSIODATA0_LATCTL1 = 08040804
N2.C1.S06: DDRIOHSIODATA0_LATCTL1 = 08040804
N2.C1.S07: DDRIOHSIODATA0_LATCTL1 = 08040804
N2.C1.S08: DDRIOHSIODATA0_LATCTL1 = 08040804
N2.C2: ODTTIMCTL (INIT RELAX) rdwidth = 10 rddly = 0 wrwidth = 8 wrdly = 0
N2.C2.S00: DDRIOHSIODATA0_LATCTL1 = 08040804
N2.C2.S01: DDRIOHSIODATA0_LATCTL1 = 08040804
N2.C2.S02: DDRIOHSIODATA0_LATCTL1 = 08040804
N2.C2.S03: DDRIOHSIODATA0_LATCTL1 = 08040804
N2.C2.S04: DDRIOHSIODATA0_LATCTL1 = 08040804
N2.C2.S05: DDRIOHSIODATA0_LATCTL1 = 08040804
N2.C2.S06: DDRIOHSIODATA0_LATCTL1 = 08040804
N2.C2.S07: DDRIOHSIODATA0_LATCTL1 = 08040804
N2.C2.S08: DDRIOHSIODATA0_LATCTL1 = 08040804
N2.C3: ODTTIMCTL (INIT RELAX) rdwidth = 10 rddly = 0 wrwidth = 8 wrdly = 0
N2.C3.S00: DDRIOHSIODATA0_LATCTL1 = 08040804
N2.C3.S01: DDRIOHSIODATA0_LATCTL1 = 08040804
N2.C3.S02: DDRIOHSIODATA0_LATCTL1 = 08040804
N2.C3.S03: DDRIOHSIODATA0_LATCTL1 = 08040804
N2.C3.S04: DDRIOHSIODATA0_LATCTL1 = 08040804
N2.C3.S05: DDRIOHSIODATA0_LATCTL1 = 08040804
N2.C3.S06: DDRIOHSIODATA0_LATCTL1 = 08040804
N2.C3.S07: DDRIOHSIODATA0_LATCTL1 = 08040804
N2.C3.S08: DDRIOHSIODATA0_LATCTL1 = 08040804

START - Early Command Training
N2.C0: DDRIOHSIODATA0_LATCTL1 = 08040804
N2.C0: RdCmd2DataValidLatency = 20, (dlyFrmS = 15, clEff = 10, earlyCas = 0, selNTiming = 2)
N2.C0: SettingForTrainingStep: RdCmd2RcvEnLatency = 5
N2.C0: SettingForTrainingStep: Programming 7 tick initial value to CTL signals
N2.C1: DDRIOHSIODATA0_LATCTL1 = 08040804
N2.C1: RdCmd2DataValidLatency = 20, (dlyFrmS = 15, clEff = 10, earlyCas = 0, selNTiming = 2)
N2.C1: SettingForTrainingStep: RdCmd2RcvEnLatency = 5
N2.C1: SettingForTrainingStep: Programming 10 tick initial value to CTL signals
N2.C2: DDRIOHSIODATA0_LATCTL1 = 08040804
N2.C2: RdCmd2DataValidLatency = 20, (dlyFrmS = 15, clEff = 10, earlyCas = 0, selNTiming = 2)
N2.C2: SettingForTrainingStep: RdCmd2RcvEnLatency = 5
N2.C2: SettingForTrainingStep: Programming 7 tick initial value to CTL signals
N2.C3: DDRIOHSIODATA0_LATCTL1 = 08040804
N2.C3: RdCmd2DataValidLatency = 20, (dlyFrmS = 15, clEff = 10, earlyCas = 0, selNTiming = 2)
N2.C3: SettingForTrainingStep: RdCmd2RcvEnLatency = 5
N2.C3: SettingForTrainingStep: Programming 10 tick initial value to CTL signals
N2: FSM Basic Clock Training
N2.C0: JCK cmd timing = 1N
N2.C0: RdCmd2DataValidLatency = 21, (dlyFrmS = 15, clEff = 10, earlyCas = 0, selNTiming = 0)
N2.C1: RdCmd2DataValidLatency = 21, (dlyFrmS = 15, clEff = 10, earlyCas = 0, selNTiming = 0)
N2.C2: JCK cmd timing = 1N
N2.C2: RdCmd2DataValidLatency = 21, (dlyFrmS = 15, clEff = 10, earlyCas = 0, selNTiming = 0)
N2.C3: RdCmd2DataValidLatency = 21, (dlyFrmS = 15, clEff = 10, earlyCas = 0, selNTiming = 0)
Entry 0 - TrainDcc - DCCStart: 25, VocStart: 14, DCCFinal: 25, VocFinal: 14
Entry 1 - TrainDcc - DCCStart: 10, VocStart: 13, DCCFinal: 10, VocFinal: 13
Entry 2 - TrainDcc - DCCStart: 27, VocStart: 10, DCCFinal: 63, VocFinal: 12
Entry 3 - TrainDcc - DCCStart: 14, VocStart: 12, DCCFinal: 14, VocFinal: 12
Entry 4 - TrainDcc - DCCStart: 40, VocStart: 11, DCCFinal: 40, VocFinal: 15
Entry 5 - TrainDcc - DCCStart: 34, VocStart: 10, DCCFinal: 34, VocFinal: 10
Entry 6 - TrainDcc - DCCStart: 32, VocStart: 13, DCCFinal: 32, VocFinal: 13
Entry 7 - TrainDcc - DCCStart: 28, VocStart: 13, DCCFinal: 28, VocFinal: 13
Entry 8 - TrainDcc - DCCStart: 33, VocStart: 17, DCCFinal: 33, VocFinal: 17
N5.C1.S00: VmseWriteTraining Final: centerPi = 0x38, PiEw = 0x28, centerVref = 0x48, vrefHeight = 0x26
N5.C1.S01: VmseWriteTraining Final: centerPi = 0x3A, PiEw = 0x25, centerVref = 0x3C, vrefHeight = 0x26
N5.C1.S02: VmseWriteTraining Final: centerPi = 0x36, PiEw = 0x22, centerVref = 0x3E, vrefHeight = 0x26
N5.C1.S03: VmseWriteTraining Final: centerPi = 0x39, PiEw = 0x2A, centerVref = 0x3F, vrefHeight = 0x28
N5.C1.S04: VmseWriteTraining Final: centerPi = 0x3E, PiEw = 0x27, centerVref = 0x3E, vrefHeight = 0x24
N5.C1.S05: VmseWriteTraining Final: centerPi = 0x3D, PiEw = 0x27, centerVref = 0x42, vrefHeight = 0x26
N5.C1.S06: VmseWriteTraining Final: centerPi = 0x3B, PiEw = 0x24, centerVref = 0x40, vrefHeight = 0x26
N5.C1.S07: VmseWriteTraining Final: centerPi = 0x3D, PiEw = 0x28, centerVref = 0x3C, vrefHeight = 0x26
N5.C1.S08: VmseWriteTraining Final: centerPi = 0x3B, PiEw = 0x26, centerVref = 0x45, vrefHeight = 0x26
N5.C1.S09: VmseWriteTraining Final: centerPi = 0x3C, PiEw = 0x28, centerVref = 0x3E, vrefHeight = 0x26
N5.C1.S10: VmseWriteTraining Final: centerPi = 0x3B, PiEw = 0x24, centerVref = 0x3E, vrefHeight = 0x26
N5.C1.S11: VmseWriteTraining Final: centerPi = 0x39, PiEw = 0x28, centerVref = 0x3E, vrefHeight = 0x2A
N5.C1.S12: VmseWriteTraining Final: centerPi = 0x40, PiEw = 0x24, centerVref = 0x3E, vrefHeight = 0x24
N5.C1.S13: VmseWriteTraining Final: centerPi = 0x41, PiEw = 0x24, centerVref = 0x3D, vrefHeight = 0x28
N5.C1.S14: VmseWriteTraining Final: centerPi = 0x40, PiEw = 0x23, centerVref = 0x3C, vrefHeight = 0x26
N5.C1.S15: VmseWriteTraining Final: centerPi = 0x40, PiEw = 0x25, centerVref = 0x3D, vrefHeight = 0x28
N5.C1.S16: VmseWriteTraining Final: centerPi = 0x39, PiEw = 0x23, centerVref = 0x43, vrefHeight = 0x24
N5.C1.S17: VmseWriteTraining Final: centerPi = 0x38, PiEw = 0x27, centerVref = 0x3D, vrefHeight = 0x24
N5.C1.S18: VmseWriteTraining Final: centerPi = 0x37, PiEw = 0x28, centerVref = 0x41, vrefHeight = 0x24
N5.C1.S19: VmseWriteTraining Final: centerPi = 0x37, PiEw = 0x29, centerVref = 0x3D, vrefHeight = 0x28
N5.C1.S20: VmseWriteTraining Final: centerPi = 0x3C, PiEw = 0x28, centerVref = 0x3E, vrefHeight = 0x26
N5.C1.S21: VmseWriteTraining Final: centerPi = 0x3B, PiEw = 0x23, centerVref = 0x3D, vrefHeight = 0x24
N5.C1.S22: VmseWriteTraining Final: centerPi = 0x3B, PiEw = 0x23, centerVref = 0x3C, vrefHeight = 0x26
N5.C1.S23: VmseWriteTraining Final: centerPi = 0x3A, PiEw = 0x27, centerVref = 0x41, vrefHeight = 0x24
N5.C1.S24: VmseWriteTraining Final: centerPi = 0x3B, PiEw = 0x25, centerVref = 0x40, vrefHeight = 0x24
N5.C1.S25: VmseWriteTraining Final: centerPi = 0x3A, PiEw = 0x2B, centerVref = 0x40, vrefHeight = 0x26
N5.C1.S26: VmseWriteTraining Final: centerPi = 0x39, PiEw = 0x26, centerVref = 0x40, vrefHeight = 0x28
N5.C1.S27: VmseWriteTraining Final: centerPi = 0x3A, PiEw = 0x2A, centerVref = 0x40, vrefHeight = 0x2A
N5.C1.S28: VmseWriteTraining Final: centerPi = 0x3D, PiEw = 0x25, centerVref = 0x3B, vrefHeight = 0x24
N5.C1.S29: VmseWriteTraining Final: centerPi = 0x3F, PiEw = 0x24, centerVref = 0x3E, vrefHeight = 0x26
N5.C1.S30: VmseWriteTraining Final: centerPi = 0x3F, PiEw = 0x26, centerVref = 0x3E, vrefHeight = 0x2A
N5.C1.S31: VmseWriteTraining Final: centerPi = 0x3F, PiEw = 0x2A, centerVref = 0x3C, vrefHeight = 0x28
N5.C1.S32: VmseWriteTraining Final: centerPi = 0x3B, PiEw = 0x27, centerVref = 0x43, vrefHeight = 0x24
N5.C1.S33: VmseWriteTraining Final: centerPi = 0x3A, PiEw = 0x27, centerVref = 0x3E, vrefHeight = 0x26
N5.C1.S34: VmseWriteTraining Final: centerPi = 0x39, PiEw = 0x25, centerVref = 0x3E, vrefHeight = 0x2A
N5.C1.S35: VmseWriteTraining Final: centerPi = 0x37, PiEw = 0x27, centerVref = 0x3B, vrefHeight = 0x2C
N5.C1.S36: VmseWriteTraining Final: centerPi = 0x3E, PiEw = 0x27, centerVref = 0x3B, vrefHeight = 0x28
N5.C1.S37: VmseWriteTraining Final: centerPi = 0x3C, PiEw = 0x26, centerVref = 0x40, vrefHeight = 0x26
N5.C1.S38: VmseWriteTraining Final: centerPi = 0x3D, PiEw = 0x25, centerVref = 0x42, vrefHeight = 0x28
N5.C1.S39: VmseWriteTraining Final: centerPi = 0x3B, PiEw = 0x26, centerVref = 0x3E, vrefHeight = 0x26
N5.C1.S40: VmseWriteTraining Final: centerPi = 0x38, PiEw = 0x28, centerVref = 0x41, vrefHeight = 0x24

END - VMSE Train Read                  Time         3968 ms
N5.C1.S41: VmseWriteTraining Final: centerPi = 0x38, PiEw = 0x22, centerVref = 0x3D, vrefHeight = 0x22

START - VMSE Train Level Tx DQS DCC
N5.C1.S42: VmseWriteTraining Final: centerPi = 0x35, PiEw = 0x22, centerVref = 0x3E, vrefHeight = 0x20
N7.C1: VmseLevelTxDqsDccExecute: MXB DQS DCC Finished Successfully
N5.C1.S43: VmseWriteTraining Final: centerPi = 0x36, PiEw = 0x22, centerVref = 0x3C, vrefHeight = 0x24
N7.C1.S04: VmseAdjustDqsVoc: retrain DQS DCC.
N5.C1.S44: VmseWriteTraining Final: centerPi = 0x3E, PiEw = 0x25, centerVref = 0x3E, vrefHeight = 0x26
N7.C1.S04:    dcc1_dqs = 0x3F, preampvoc = 0xE
N5.C1.S45: VmseWriteTraining Final: centerPi = 0x3B, PiEw = 0x1F, centerVref = 0x3A, vrefHeight = 0x22
N7.C1.S08: VmseAdjustDqsVoc: retrain DQS DCC.
N5.C1.S46: VmseWriteTraining Final: centerPi = 0x3D, PiEw = 0x23, centerVref = 0x3C, vrefHeight = 0x26
N7.C1.S08:    dcc1_dqs = 0x0, preampvoc = 0xC
N5.C1.S47: VmseWriteTraining Final: centerPi = 0x3B, PiEw = 0x26, centerVref = 0x39, vrefHeight = 0x26
N7.C1: VmseLevelTxDqsDccExecute: MXB DQS DCC Finished Successfully
N5.C1.S48: VmseWriteTraining Final: centerPi = 0x3A, PiEw = 0x29, centerVref = 0x41, vrefHeight = 0x24
N7.C1.S08: VmseAdjustDqsVoc: retrain DQS DCC.
N5.C1.S49: VmseWriteTraining Final: centerPi = 0x3B, PiEw = 0x2A, centerVref = 0x40, vrefHeight = 0x2A
N7.C1.S08:    dcc1_dqs = 0x0, preampvoc = 0xB
N5.C1.S50: VmseWriteTraining Final: centerPi = 0x3B, PiEw = 0x25, centerVref = 0x3E, vrefHeight = 0x2A
N7.C1: VmseLevelTxDqsDccExecute: MXB DQS DCC Finished Successfully
N5.C1.S51: VmseWriteTraining Final: centerPi = 0x3B, PiEw = 0x2B, centerVref = 0x3B, vrefHeight = 0x2C

END - VMSE Train Level Tx DQS DCC      Time         150 ms
N5.C1.S52: VmseWriteTraining Final: centerPi = 0x42, PiEw = 0x26, centerVref = 0x3C, vrefHeight = 0x2A

START - VMSE Train Write Leveling
N5.C1.S53: VmseWriteTraining Final: centerPi = 0x3E, PiEw = 0x23, centerVref = 0x3C, vrefHeight = 0x24
N7.C1: VmseWriteLevelFineSetup: Set push to data delay = 6, Global TX DQS delay = 0
N5.C1.S54: VmseWriteTraining Final: centerPi = 0x3E, PiEw = 0x25, centerVref = 0x3C, vrefHeight = 0x2A
N7.C1: VmseRLWLFineSearchAll: Entry
N5.C1.S55: VmseWriteTraining Final: centerPi = 0x3D, PiEw = 0x26, centerVref = 0x40, vrefHeight = 0x26
N7.C1: FINE WRITE LEVEL DELAY
N5.C1.S56: VmseWriteTraining Final: centerPi = 0x3B, PiEw = 0x24, centerVref = 0x41, vrefHeight = 0x24
N7.C1.S00: TX DQS DELAY = 74
N5.C1.S57: VmseWriteTraining Final: centerPi = 0x3C, PiEw = 0x24, centerVref = 0x3F, vrefHeight = 0x28
N7.C1.S01: TX DQS DELAY = 74
N5.C1.S58: VmseWriteTraining Final: centerPi = 0x3A, PiEw = 0x28, centerVref = 0x3B, vrefHeight = 0x2A
N7.C1.S02: TX DQS DELAY = 90
N5.C1.S59: VmseWriteTraining Final: centerPi = 0x39, PiEw = 0x2A, centerVref = 0x3E, vrefHeight = 0x2A
N7.C1.S03: TX DQS DELAY = 79
N5.C1.S60: VmseWriteTraining Final: centerPi = 0x3F, PiEw = 0x26, centerVref = 0x38, vrefHeight = 0x26
N7.C1.S04: TX DQS DELAY = 109
N5.C1.S61: VmseWriteTraining Final: centerPi = 0x3D, PiEw = 0x25, centerVref = 0x40, vrefHeight = 0x22
N7.C1.S05: TX DQS DELAY = 114
N5.C1.S62: VmseWriteTraining Final: centerPi = 0x3F, PiEw = 0x25, centerVref = 0x41, vrefHeight = 0x28
N7.C1.S06: TX DQS DELAY = 119
N5.C1.S63: VmseWriteTraining Final: centerPi = 0x3C, PiEw = 0x28, centerVref = 0x3E, vrefHeight = 0x26
N7.C1.S07: TX DQS DELAY = 119

END - VMSE Train Read                  Time         4011 ms
N5.C1.S64: VmseWriteTraining Final: centerPi = 0x39, PiEw = 0x28, centerVref = 0x46, vrefHeight = 0x26
N7.C1.S08: TX DQS DELAY = 112

START - VMSE Train Level Tx DQS DCC
N5.C1.S65: VmseWriteTraining Final: centerPi = 0x37, PiEw = 0x2A, centerVref = 0x3E, vrefHeight = 0x26
N7.C1: VmseWriteLevelCoarseSetup: Set push to data delay = 6, Global TX DQS delay = 0
Checkpoint Code: Socket 0, 0xB6, 0x52, 0x0000
N5.C1.S66: VmseWriteTraining Final: centerPi = 0x38, PiEw = 0x25, centerVref = 0x3B, vrefHeight = 0x28
N7.C1: VmseWriteLevelCoarseExecute
N1.C1: VmseLevelTxDqsDccExecute: MXB DQS DCC Finished Successfully
N5.C1.S67: VmseWriteTraining Final: centerPi = 0x39, PiEw = 0x29, centerVref = 0x3C, vrefHeight = 0x2A
N7.C1: VmseWLCoarseUpdatePD: New push to data delay = 6, New global TxDQS delay = 1

END - VMSE Train Level Tx DQS DCC      Time         47 ms
N5.C1.S68: VmseWriteTraining Final: centerPi = 0x3E, PiEw = 0x27, centerVref = 0x40, vrefHeight = 0x2A
N7.C1: VmseWLCoarseUpdatePD: New push to data delay = 7, New global TxDQS delay = 0

START - VMSE Train Write Leveling
N5.C1.S69: VmseWriteTraining Final: centerPi = 0x3E, PiEw = 0x25, centerVref = 0x3F, vrefHeight = 0x28
N7.C1: VmseWLCoarseUpdatePD: New push to data delay = 7, New global TxDQS delay = 1
Checkpoint Code: Socket 0, 0xB6, 0x54, 0x0000
N5.C1.S70: VmseWriteTraining Final: centerPi = 0x3B, PiEw = 0x26, centerVref = 0x3E, vrefHeight = 0x28
N7.C1: VmseWLCoarseUpdatePD: New push to data delay = 8, New global TxDQS delay = 0
N1.C1: VmseWriteLevelFineSetup: Set push to data delay = 6, Global TX DQS delay = 0
N5.C1.S71: VmseWriteTraining Final: centerPi = 0x3B, PiEw = 0x27, centerVref = 0x40, vrefHeight = 0x2A
N7.C1: VmseWLCoarseUpdatePD: New push to data delay = 8, New global TxDQS delay = 1
N1.C1: VmseRLWLFineSearchAll: Entry

END - VMSE Train Write                 Time         2307 ms
N7.C1: VmseWLCoarseUpdatePD: New push to data delay = 9, New global TxDQS delay = 0
N1.C1: FINE WRITE LEVEL DELAY
N5: 
Total VMSE trainings latency = 14114 ms
N7.C1.S00: FINAL TX DQS BEFORE TxFIFO CHECK = 45
N1.C1.S00: TX DQS DELAY = 62
N4: PostVmseTraining
N7.C1.S01: FINAL TX DQS BEFORE TxFIFO CHECK = 46
N1.C1.S01: TX DQS DELAY = 62
N4.C0: PostVmseTraining
N7.C1.S02: FINAL TX DQS BEFORE TxFIFO CHECK = 60
N1.C1.S02: TX DQS DELAY = 75
N4.C0: PostVMSE Training VMSE Health Check Passed
N7.C1.S03: FINAL TX DQS BEFORE TxFIFO CHECK = 49
N1.C1.S03: TX DQS DELAY = 69
N4.C1: PostVmseTraining
N7.C1.S04: FINAL TX DQS BEFORE TxFIFO CHECK = 78
N1.C1.S04: TX DQS DELAY = 96
N4.C2: PostVMSE Training VMSE Health Check Passed
N7.C1.S05: FINAL TX DQS BEFORE TxFIFO CHECK = 83
N1.C1.S05: TX DQS DELAY = 102
N4: PreDdrTraining
N7.C1.S06: FINAL TX DQS BEFORE TxFIFO CHECK = 89
N1.C1.S06: TX DQS DELAY = 105
N4: PreDdrTraining[QCRM=OFF]
N7.C1.S07: FINAL TX DQS BEFORE TxFIFO CHECK = 90
N1.C1.S07: TX DQS DELAY = 106
N4.C0.D0: CheckRankPopLocal: dimmPresent: 1, numRanks = 2
N7.C1.S08: FINAL TX DQS BEFORE TxFIFO CHECK = 82
N1.C1.S08: TX DQS DELAY = 101
N4.C0.D0.R0: CheckRankPopLocal: mapOut: 0, enabled = 1
N7.C1: ResolveTxFIFOPtrSeparation: Smallest PI (45) < MIN ALLOWED DELAY (176) 
N1.C1: VmseWriteLevelCoarseSetup: Set push to data delay = 6, Global TX DQS delay = 0
N4.C0.D0.R1: CheckRankPopLocal: mapOut: 0, enabled = 1
N7.C1: VmseIncTxFifoPtrSeparation: New push to data delay = 8
N1.C1: VmseWriteLevelCoarseExecute
N4.C0.D1: CheckRankPopLocal: dimmPresent: 1, numRanks = 2
N7.C1.S00: VmseIncTxFifoPtrSeparation: pi adjustment = 128, FINAL TX DQS DELAY = 301
Checkpoint Code: Socket 0, 0xB6, 0xAC, 0x0000
N4.C0.D1.R0: CheckRankPopLocal: mapOut: 0, enabled = 1
N7.C1.S01: VmseIncTxFifoPtrSeparation: pi adjustment = 128, FINAL TX DQS DELAY = 302
N1.C1: VmseWLCoarseUpdatePD: New push to data delay = 6, New global TxDQS delay = 1
N4.C0.D1.R1: CheckRankPopLocal: mapOut: 0, enabled = 1
N7.C1.S02: VmseIncTxFifoPtrSeparation: pi adjustment = 128, FINAL TX DQS DELAY = 316
N1.C1: VmseWLCoarseUpdatePD: New push to data delay = 7, New global TxDQS delay = 0
N4.C0.D2: CheckRankPopLocal: dimmPresent: 0, numRanks = 0
N7.C1.S03: VmseIncTxFifoPtrSeparation: pi adjustment = 128, FINAL TX DQS DELAY = 305
N1.C1: VmseWLCoarseUpdatePD: New push to data delay = 7, New global TxDQS delay = 1
N4.C0.D0: CheckRankPopLocal: amap: 0x00000000
N7.C1.S04: VmseIncTxFifoPtrSeparation: pi adjustment = 128, FINAL TX DQS DELAY = 334
N1.C1: VmseWLCoarseUpdatePD: New push to data delay = 8, New global TxDQS delay = 0
N4.C0.D1: CheckRankPopLocal: amap: 0x00000000
N7.C1.S05: VmseIncTxFifoPtrSeparation: pi adjustment = 128, FINAL TX DQS DELAY = 339
N1.C1: VmseWLCoarseUpdatePD: New push to data delay = 8, New global TxDQS delay = 1
N4.C0.D2: CheckRankPopLocal: amap: 0x00000000
N7.C1.S06: VmseIncTxFifoPtrSeparation: pi adjustment = 128, FINAL TX DQS DELAY = 345
N1.C1.S00: FINAL TX DQS BEFORE TxFIFO CHECK = 159
N4.C1.D0: CheckRankPopLocal: dimmPresent: 1, numRanks = 2
N7.C1.S07: VmseIncTxFifoPtrSeparation: pi adjustment = 128, FINAL TX DQS DELAY = 346
N1.C1.S01: FINAL TX DQS BEFORE TxFIFO CHECK = 160
N4.C1.D0.R0: CheckRankPopLocal: mapOut: 0, enabled = 1
N7.C1.S08: VmseIncTxFifoPtrSeparation: pi adjustment = 128, FINAL TX DQS DELAY = 338
N1.C1.S02: FINAL TX DQS BEFORE TxFIFO CHECK = 172
N4.C1.D0.R1: CheckRankPopLocal: mapOut: 0, enabled = 1

END - VMSE Train Write Leveling        Time         725 ms
N1.C1.S03: FINAL TX DQS BEFORE TxFIFO CHECK = 167
N4.C1.D1: CheckRankPopLocal: dimmPresent: 1, numRanks = 2

START - VMSE Train Write
N1.C1.S04: FINAL TX DQS BEFORE TxFIFO CHECK = 192
N4.C1.D1.R0: CheckRankPopLocal: mapOut: 0, enabled = 1
N1.C1.S05: FINAL TX DQS BEFORE TxFIFO CHECK = 200
N4.C1.D1.R1: CheckRankPopLocal: mapOut: 0, enabled = 1
N1.C1.S06: FINAL TX DQS BEFORE TxFIFO CHECK = 204
N4.C1.D2: CheckRankPopLocal: dimmPresent: 0, numRanks = 0
N1.C1.S07: FINAL TX DQS BEFORE TxFIFO CHECK = 205
N4.C1.D0: CheckRankPopLocal: amap: 0x00000000
N1.C1.S08: FINAL TX DQS BEFORE TxFIFO CHECK = 200
N4.C1.D1: CheckRankPopLocal: amap: 0x00000000
N1.C1: ResolveTxFIFOPtrSeparation: Smallest PI (159) < MIN ALLOWED DELAY (176) 
N4.C1.D2: CheckRankPopLocal: amap: 0x00000000
N1.C1: VmseIncTxFifoPtrSeparation: New push to data delay = 7
N4.C2.D0: CheckRankPopLocal: dimmPresent: 1, numRanks = 2
N1.C1.S00: VmseIncTxFifoPtrSeparation: pi adjustment = 256, FINAL TX DQS DELAY = 415
N4.C2.D0.R0: CheckRankPopLocal: mapOut: 0, enabled = 1
N1.C1.S01: VmseIncTxFifoPtrSeparation: pi adjustment = 256, FINAL TX DQS DELAY = 416
N4.C2.D0.R1: CheckRankPopLocal: mapOut: 0, enabled = 1
N1.C1.S02: VmseIncTxFifoPtrSeparation: pi adjustment = 256, FINAL TX DQS DELAY = 428
N4.C2.D1: CheckRankPopLocal: dimmPresent: 1, numRanks = 2
N1.C1.S03: VmseIncTxFifoPtrSeparation: pi adjustment = 256, FINAL TX DQS DELAY = 423
N4.C2.D1.R0: CheckRankPopLocal: mapOut: 0, enabled = 1
N1.C1.S04: VmseIncTxFifoPtrSeparation: pi adjustment = 256, FINAL TX DQS DELAY = 448
N4.C2.D1.R1: CheckRankPopLocal: mapOut: 0, enabled = 1
N1.C1.S05: VmseIncTxFifoPtrSeparation: pi adjustment = 256, FINAL TX DQS DELAY = 456
N4.C2.D2: CheckRankPopLocal: dimmPresent: 0, numRanks = 0
N1.C1.S06: VmseIncTxFifoPtrSeparation: pi adjustment = 256, FINAL TX DQS DELAY = 460
N4.C2.D0: CheckRankPopLocal: amap: 0x00000000
N1.C1.S07: VmseIncTxFifoPtrSeparation: pi adjustment = 256, FINAL TX DQS DELAY = 461
N4.C2.D1: CheckRankPopLocal: amap: 0x00000000
N1.C1.S08: VmseIncTxFifoPtrSeparation: pi adjustment = 256, FINAL TX DQS DELAY = 456
N4.C2.D2: CheckRankPopLocal: amap: 0x00000000

END - VMSE Train Write Leveling        Time         681 ms
N4.C3.D0: CheckRankPopLocal: dimmPresent: 1, numRanks = 2

START - VMSE Train Write
N4.C3.D0.R0: CheckRankPopLocal: mapOut: 0, enabled = 1
Checkpoint Code: Socket 0, 0xB6, 0x56, 0x0000
N4.C3.D0.R1: CheckRankPopLocal: mapOut: 0, enabled = 1
N4.C3.D1: CheckRankPopLocal: dimmPresent: 1, numRanks = 2
N4.C3.D1.R0: CheckRankPopLocal: mapOut: 0, enabled = 1
N4.C3.D1.R1: CheckRankPopLocal: mapOut: 0, enabled = 1
N4.C3.D2: CheckRankPopLocal: dimmPresent: 0, numRanks = 0
N4.C3.D0: CheckRankPopLocal: amap: 0x00000000
N4.C3.D1: CheckRankPopLocal: amap: 0x00000000
N4.C3.D2: CheckRankPopLocal: amap: 0x00000000
N4.C0: JCK cmd timing = 3N
N4.C0: RdCmd2DataValidLatency = 20, (dlyFrmS = 15, clEff = 10, earlyCas = 0, selNTiming = 2)
N4.C0: CLK0_CFG: 0x000FFF30
N4.C0: DDR_RANKCTL: 0x000FEA40
N4.C0: MCODT = 0 ( 50 ohms)
N4.C0.D0.R0: Rtt_wr = 120, Rtt_nom = 20
N4.C0.D0.R1: Rtt_wr = 120, Rtt_nom = 0
N4.C0.D1.R0: Rtt_wr = 120, Rtt_nom = 20
N4.C0.D1.R1: Rtt_wr = 120, Rtt_nom = 0
N4.C0: ODTRDCTL00 = 0x01000104
N4.C0: ODTRDCTL01 = 0x00000001
N4.C0: ODTWRCTL00 = 0x05000185
N4.C0: ODTWRCTL01 = 0x00000009
N4.C1: RdCmd2DataValidLatency = 20, (dlyFrmS = 15, clEff = 10, earlyCas = 0, selNTiming = 2)
N4.C1: CLK0_CFG: 0x000FF330
N4.C1: DDR_RANKCTL: 0x000FEA40
N4.C1: MCODT = 0 ( 50 ohms)
N4.C1.D0.R0: Rtt_wr = 120, Rtt_nom = 20
N4.C1.D0.R1: Rtt_wr = 120, Rtt_nom = 0
N4.C1.D1.R0: Rtt_wr = 120, Rtt_nom = 20
N4.C1.D1.R1: Rtt_wr = 120, Rtt_nom = 0
N4.C1: ODTRDCTL00 = 0x01000104
N4.C1: ODTRDCTL01 = 0x00000001
N4.C1: ODTWRCTL00 = 0x05000185
N4.C1: ODTWRCTL01 = 0x00000009
N4.C2: JCK cmd timing = 3N
N4.C2: RdCmd2DataValidLatency = 20, (dlyFrmS = 15, clEff = 10, earlyCas = 0, selNTiming = 2)
N4.C2: CLK0_CFG: 0x000FFF30
N4.C2: DDR_RANKCTL: 0x000FEA40
N4.C2: MCODT = 0 ( 50 ohms)
N4.C2.D0.R0: Rtt_wr = 120, Rtt_nom = 20
N4.C2.D0.R1: Rtt_wr = 120, Rtt_nom = 0
N4.C2.D1.R0: Rtt_wr = 120, Rtt_nom = 20
N4.C2.D1.R1: Rtt_wr = 120, Rtt_nom = 0
N4.C2: ODTRDCTL00 = 0x01000104
N4.C2: ODTRDCTL01 = 0x00000001
N4.C2: ODTWRCTL00 = 0x05000185
N4.C2: ODTWRCTL01 = 0x00000009
N4.C3: RdCmd2DataValidLatency = 20, (dlyFrmS = 15, clEff = 10, earlyCas = 0, selNTiming = 2)
N4.C3: CLK0_CFG: 0x000FF330
N4.C3: DDR_RANKCTL: 0x000FEA40
N4.C3: MCODT = 0 ( 50 ohms)
N4.C3.D0.R0: Rtt_wr = 120, Rtt_nom = 20
N4.C3.D0.R1: Rtt_wr = 120, Rtt_nom = 0
N4.C3.D1.R0: Rtt_wr = 120, Rtt_nom = 20
N4.C3.D1.R1: Rtt_wr = 120, Rtt_nom = 0
N4.C3: ODTRDCTL00 = 0x01000104
N4.C3: ODTRDCTL01 = 0x00000001
N4.C3: ODTWRCTL00 = 0x05000185
N4.C3: ODTWRCTL01 = 0x00000009
N4.C0.D0: PreDdrTraining: Program dimmmtr 0xC502D
N4.C0.D1: PreDdrTraining: Program dimmmtr 0xC502D
N4.C1.D0: PreDdrTraining: Program dimmmtr 0xC502D
N4.C1.D1: PreDdrTraining: Program dimmmtr 0xC502D
N4.C2.D0: PreDdrTraining: Program dimmmtr 0xC502D
N4.C2.D1: PreDdrTraining: Program dimmmtr 0xC502D
N4.C3.D0: PreDdrTraining: Program dimmmtr 0xC502D
N4.C3.D1: PreDdrTraining: Program dimmmtr 0xC502D
N4: InitializeDdrioForUse
N4: SetupJckForBL: setting BL to 8
N4.C0: ODTTIMCTL (INIT RELAX) rdwidth = 10 rddly = 0 wrwidth = 8 wrdly = 0
N4.C1: ODTTIMCTL (INIT RELAX) rdwidth = 10 rddly = 0 wrwidth = 8 wrdly = 0
N4.C2: ODTTIMCTL (INIT RELAX) rdwidth = 10 rddly = 0 wrwidth = 8 wrdly = 0
N4.C3: ODTTIMCTL (INIT RELAX) rdwidth = 10 rddly = 0 wrwidth = 8 wrdly = 0
N4: JckDdrTraining
N4: InitializeDdrioForTraining: QCRM Disabled
N4.C0: InitializeDdrioForTraining: cleff = 10
N4.C0: InitializeDdrioForTraining: cwleff = 8
N4.C0: InitializeDdrioForTraining: initial ddrInitIndexRx = 4 ddrInitIndexTx = 2
N4.C0: InitializeDdrioForTraining: initial RdCmd2RcvEnLatency = 5
N4.C0: InitializeDdrioForTraining: initial RdPtrOffsetRcvEn = 4
N4.C0: InitializeDdrioForTraining: initial rkrdptroffsetrcvenb = 6
N4.C0: InitializeDdrioForTraining: initial rkrdptroffsetdrvenrcvenb = 5
N4.C0: InitializeDdrioForTraining: initial WrCmd2DqsStartLatency = 4
N4.C0: InitializeDdrioForTraining: initial RdPtrOffsetDqs = 10
N4.C0: InitializeDdrioForTraining: initial RdCmd2RcvEnLatency = 5
N4.C0: InitializeDdrioForTraining: initial WrCmd2DqsStartLatency = 4
N4.C0: InitializeDdrioForTraining: initial RdPtrOffsetRcvEn = 4
N4.C0: InitializeDdrioForTraining: initial RdPtrOffsetDqs = 6
N4.C0: InitializeDdrioForTraining: initial RdPtrOffsetDq = 5
N4.C1: InitializeDdrioForTraining: cleff = 10
N4.C1: InitializeDdrioForTraining: cwleff = 8
N4.C1: InitializeDdrioForTraining: initial ddrInitIndexRx = 4 ddrInitIndexTx = 2
N4.C1: InitializeDdrioForTraining: initial RdCmd2RcvEnLatency = 5
N4.C1: InitializeDdrioForTraining: initial RdPtrOffsetRcvEn = 4
N4.C1: InitializeDdrioForTraining: initial rkrdptroffsetrcvenb = 6
N4.C1: InitializeDdrioForTraining: initial rkrdptroffsetdrvenrcvenb = 5
N4.C1: InitializeDdrioForTraining: initial WrCmd2DqsStartLatency = 4
N4.C1: InitializeDdrioForTraining: initial RdPtrOffsetDqs = 10
N4.C1: InitializeDdrioForTraining: initial RdCmd2RcvEnLatency = 5
N4.C1: InitializeDdrioForTraining: initial WrCmd2DqsStartLatency = 4
N4.C1: InitializeDdrioForTraining: initial RdPtrOffsetRcvEn = 4
N4.C1: InitializeDdrioForTraining: initial RdPtrOffsetDqs = 6
N4.C1: InitializeDdrioForTraining: initial RdPtrOffsetDq = 5
N4.C2: InitializeDdrioForTraining: cleff = 10
N4.C2: InitializeDdrioForTraining: cwleff = 8
N4.C2: InitializeDdrioForTraining: initial ddrInitIndexRx = 4 ddrInitIndexTx = 2
N4.C2: InitializeDdrioForTraining: initial RdCmd2RcvEnLatency = 5
N4.C2: InitializeDdrioForTraining: initial RdPtrOffsetRcvEn = 4
N4.C2: InitializeDdrioForTraining: initial rkrdptroffsetrcvenb = 6
N4.C2: InitializeDdrioForTraining: initial rkrdptroffsetdrvenrcvenb = 5
N4.C2: InitializeDdrioForTraining: initial WrCmd2DqsStartLatency = 4
N4.C2: InitializeDdrioForTraining: initial RdPtrOffsetDqs = 10
N4.C2: InitializeDdrioForTraining: initial RdCmd2RcvEnLatency = 5
N4.C2: InitializeDdrioForTraining: initial WrCmd2DqsStartLatency = 4
N4.C2: InitializeDdrioForTraining: initial RdPtrOffsetRcvEn = 4
N4.C2: InitializeDdrioForTraining: initial RdPtrOffsetDqs = 6
N4.C2: InitializeDdrioForTraining: initial RdPtrOffsetDq = 5
N4.C3: InitializeDdrioForTraining: cleff = 10
N4.C3: InitializeDdrioForTraining: cwleff = 8
N4.C3: InitializeDdrioForTraining: initial ddrInitIndexRx = 4 ddrInitIndexTx = 2
N4.C3: InitializeDdrioForTraining: initial RdCmd2RcvEnLatency = 5
N4.C3: InitializeDdrioForTraining: initial RdPtrOffsetRcvEn = 4
N4.C3: InitializeDdrioForTraining: initial rkrdptroffsetrcvenb = 6
N4.C3: InitializeDdrioForTraining: initial rkrdptroffsetdrvenrcvenb = 5
N4.C3: InitializeDdrioForTraining: initial WrCmd2DqsStartLatency = 4
N4.C3: InitializeDdrioForTraining: initial RdPtrOffsetDqs = 10
N4.C3: InitializeDdrioForTraining: initial RdCmd2RcvEnLatency = 5
N4.C3: InitializeDdrioForTraining: initial WrCmd2DqsStartLatency = 4
N4.C3: InitializeDdrioForTraining: initial RdPtrOffsetRcvEn = 4
N4.C3: InitializeDdrioForTraining: initial RdPtrOffsetDqs = 6
N4.C3: InitializeDdrioForTraining: initial RdPtrOffsetDq = 5
N4: DdrClockStopWa
N4: JckSetOdtRelaxTiming:
N4.C0: ODTTIMCTL (INIT RELAX) rdwidth = 10 rddly = 0 wrwidth = 8 wrdly = 0
N4.C0.S00: DDRIOHSIODATA0_LATCTL1 = 08040804
N4.C0.S01: DDRIOHSIODATA0_LATCTL1 = 08040804
N4.C0.S02: DDRIOHSIODATA0_LATCTL1 = 08040804
N4.C0.S03: DDRIOHSIODATA0_LATCTL1 = 08040804
N4.C0.S04: DDRIOHSIODATA0_LATCTL1 = 08040804
N4.C0.S05: DDRIOHSIODATA0_LATCTL1 = 08040804
N4.C0.S06: DDRIOHSIODATA0_LATCTL1 = 08040804
N4.C0.S07: DDRIOHSIODATA0_LATCTL1 = 08040804
N4.C0.S08: DDRIOHSIODATA0_LATCTL1 = 08040804
N4.C1: ODTTIMCTL (INIT RELAX) rdwidth = 10 rddly = 0 wrwidth = 8 wrdly = 0
N4.C1.S00: DDRIOHSIODATA0_LATCTL1 = 08040804
N4.C1.S01: DDRIOHSIODATA0_LATCTL1 = 08040804
N4.C1.S02: DDRIOHSIODATA0_LATCTL1 = 08040804
N4.C1.S03: DDRIOHSIODATA0_LATCTL1 = 08040804
N4.C1.S04: DDRIOHSIODATA0_LATCTL1 = 08040804
N4.C1.S05: DDRIOHSIODATA0_LATCTL1 = 08040804
N4.C1.S06: DDRIOHSIODATA0_LATCTL1 = 08040804
N4.C1.S07: DDRIOHSIODATA0_LATCTL1 = 08040804
N4.C1.S08: DDRIOHSIODATA0_LATCTL1 = 08040804
N4.C2: ODTTIMCTL (INIT RELAX) rdwidth = 10 rddly = 0 wrwidth = 8 wrdly = 0
N4.C2.S00: DDRIOHSIODATA0_LATCTL1 = 08040804
N4.C2.S01: DDRIOHSIODATA0_LATCTL1 = 08040804
N4.C2.S02: DDRIOHSIODATA0_LATCTL1 = 08040804
Entry 0 - TrainDcc - DCCStart: 21, VocStart: 13, DCCFinal: 61, VocFinal: 13
N4.C2.S03: DDRIOHSIODATA0_LATCTL1 = 08040804
Entry 1 - TrainDcc - DCCStart: 7, VocStart: 14, DCCFinal: 7, VocFinal: 14
N4.C2.S04: DDRIOHSIODATA0_LATCTL1 = 08040804
Entry 2 - TrainDcc - DCCStart: 49, VocStart: 13, DCCFinal: 41, VocFinal: 13
N4.C2.S05: DDRIOHSIODATA0_LATCTL1 = 08040804
Entry 3 - TrainDcc - DCCStart: 39, VocStart: 13, DCCFinal: 39, VocFinal: 13
N4.C2.S06: DDRIOHSIODATA0_LATCTL1 = 08040804
Entry 4 - TrainDcc - DCCStart: 34, VocStart: 14, DCCFinal: 34, VocFinal: 14
N4.C2.S07: DDRIOHSIODATA0_LATCTL1 = 08040804
Entry 5 - TrainDcc - DCCStart: 28, VocStart: 12, DCCFinal: 28, VocFinal: 12
N4.C2.S08: DDRIOHSIODATA0_LATCTL1 = 08040804
Entry 6 - TrainDcc - DCCStart: 61, VocStart: 13, DCCFinal: 61, VocFinal: 13
N4.C3: ODTTIMCTL (INIT RELAX) rdwidth = 10 rddly = 0 wrwidth = 8 wrdly = 0
Entry 7 - TrainDcc - DCCStart: 18, VocStart: 9, DCCFinal: 18, VocFinal: 9
N4.C3.S00: DDRIOHSIODATA0_LATCTL1 = 08040804
Entry 8 - TrainDcc - DCCStart: 11, VocStart: 11, DCCFinal: 11, VocFinal: 11
N4.C3.S01: DDRIOHSIODATA0_LATCTL1 = 08040804
N4.C3.S02: DDRIOHSIODATA0_LATCTL1 = 08040804
N4.C3.S03: DDRIOHSIODATA0_LATCTL1 = 08040804
N4.C3.S04: DDRIOHSIODATA0_LATCTL1 = 08040804
N4.C3.S05: DDRIOHSIODATA0_LATCTL1 = 08040804
N4.C3.S06: DDRIOHSIODATA0_LATCTL1 = 08040804
N4.C3.S07: DDRIOHSIODATA0_LATCTL1 = 08040804
N4.C3.S08: DDRIOHSIODATA0_LATCTL1 = 08040804

START - Early Command Training
N4.C0: DDRIOHSIODATA0_LATCTL1 = 08040804
N4.C0: RdCmd2DataValidLatency = 20, (dlyFrmS = 15, clEff = 10, earlyCas = 0, selNTiming = 2)
N4.C0: SettingForTrainingStep: RdCmd2RcvEnLatency = 5
N4.C0: SettingForTrainingStep: Programming 7 tick initial value to CTL signals
N4.C1: DDRIOHSIODATA0_LATCTL1 = 08040804
N4.C1: RdCmd2DataValidLatency = 20, (dlyFrmS = 15, clEff = 10, earlyCas = 0, selNTiming = 2)
N4.C1: SettingForTrainingStep: RdCmd2RcvEnLatency = 5
N4.C1: SettingForTrainingStep: Programming 10 tick initial value to CTL signals
N4.C2: DDRIOHSIODATA0_LATCTL1 = 08040804
N4.C2: RdCmd2DataValidLatency = 20, (dlyFrmS = 15, clEff = 10, earlyCas = 0, selNTiming = 2)
N4.C2: SettingForTrainingStep: RdCmd2RcvEnLatency = 5
N4.C2: SettingForTrainingStep: Programming 7 tick initial value to CTL signals
N4.C3: DDRIOHSIODATA0_LATCTL1 = 08040804
N4.C3: RdCmd2DataValidLatency = 20, (dlyFrmS = 15, clEff = 10, earlyCas = 0, selNTiming = 2)
N4.C3: SettingForTrainingStep: RdCmd2RcvEnLatency = 5
N4.C3: SettingForTrainingStep: Programming 10 tick initial value to CTL signals
Entry 0 - TrainDcc - DCCStart: 16, VocStart: 13, DCCFinal: 48, VocFinal: 13
N2.C0.D0: CalcFinalClock(90,120) = 22
N4: FSM Basic Clock Training
Entry 1 - TrainDcc - DCCStart: 4, VocStart: 11, DCCFinal: 4, VocFinal: 11
N2.C0.D1: CalcFinalClock(99,113) = 27
N4.C0: JCK cmd timing = 1N
Entry 2 - TrainDcc - DCCStart: 14, VocStart: 12, DCCFinal: 46, VocFinal: 12
N2.C1.D0: CalcFinalClock(95,113) = 23
N4.C0: RdCmd2DataValidLatency = 21, (dlyFrmS = 15, clEff = 10, earlyCas = 0, selNTiming = 0)
Entry 3 - TrainDcc - DCCStart: 5, VocStart: 13, DCCFinal: 5, VocFinal: 13
N2.C1.D1: CalcFinalClock(101,118) = 32
N4.C1: RdCmd2DataValidLatency = 21, (dlyFrmS = 15, clEff = 10, earlyCas = 0, selNTiming = 0)
Entry 4 - TrainDcc - DCCStart: 11, VocStart: 11, DCCFinal: 11, VocFinal: 17
N2.C2.D0: CalcFinalClock(88,122) = 21
N4.C2: JCK cmd timing = 1N
Entry 5 - TrainDcc - DCCStart: 12, VocStart: 16, DCCFinal: 12, VocFinal: 16
N2.C2.D1: CalcFinalClock(97,113) = 25
N4.C2: RdCmd2DataValidLatency = 21, (dlyFrmS = 15, clEff = 10, earlyCas = 0, selNTiming = 0)
Entry 6 - TrainDcc - DCCStart: 9, VocStart: 12, DCCFinal: 9, VocFinal: 21
N2.C3.D0: CalcFinalClock(94,107) = 19
N4.C3: RdCmd2DataValidLatency = 21, (dlyFrmS = 15, clEff = 10, earlyCas = 0, selNTiming = 0)
Entry 7 - TrainDcc - DCCStart: 5, VocStart: 11, DCCFinal: 5, VocFinal: 11
N2.C3.D1: CalcFinalClock(95,118) = 26
N7.C1.S00: VmseWriteTraining Final: centerPi = 0x39, PiEw = 0x2A, centerVref = 0x3D, vrefHeight = 0x2C
Entry 8 - TrainDcc - DCCStart: 1, VocStart: 12, DCCFinal: 1, VocFinal: 12
N2.C0: JCK cmd timing = 3N
N7.C1.S01: VmseWriteTraining Final: centerPi = 0x37, PiEw = 0x2C, centerVref = 0x40, vrefHeight = 0x2C
N2.C0: RdCmd2DataValidLatency = 20, (dlyFrmS = 15, clEff = 10, earlyCas = 0, selNTiming = 2)
N7.C1.S02: VmseWriteTraining Final: centerPi = 0x35, PiEw = 0x28, centerVref = 0x41, vrefHeight = 0x2A
N2.C1: RdCmd2DataValidLatency = 20, (dlyFrmS = 15, clEff = 10, earlyCas = 0, selNTiming = 2)
N7.C1.S03: VmseWriteTraining Final: centerPi = 0x39, PiEw = 0x2A, centerVref = 0x3B, vrefHeight = 0x30
N2.C2: JCK cmd timing = 3N
N7.C1.S04: VmseWriteTraining Final: centerPi = 0x3D, PiEw = 0x29, centerVref = 0x3E, vrefHeight = 0x2E
N2.C2: RdCmd2DataValidLatency = 20, (dlyFrmS = 15, clEff = 10, earlyCas = 0, selNTiming = 2)
N7.C1.S05: VmseWriteTraining Final: centerPi = 0x3F, PiEw = 0x24, centerVref = 0x38, vrefHeight = 0x2E
N2.C3: RdCmd2DataValidLatency = 20, (dlyFrmS = 15, clEff = 10, earlyCas = 0, selNTiming = 2)
N7.C1.S06: VmseWriteTraining Final: centerPi = 0x3A, PiEw = 0x24, centerVref = 0x40, vrefHeight = 0x2E
N2: RunTrainStep: Final status = 0
N7.C1.S07: VmseWriteTraining Final: centerPi = 0x3B, PiEw = 0x27, centerVref = 0x41, vrefHeight = 0x2A

END - Early Command Training           Time         3701 ms
N7.C1.S08: VmseWriteTraining Final: centerPi = 0x3D, PiEw = 0x29, centerVref = 0x40, vrefHeight = 0x2A

START - Basic Read DQ/DQS Training
N7.C1.S09: VmseWriteTraining Final: centerPi = 0x3C, PiEw = 0x28, centerVref = 0x41, vrefHeight = 0x2A
N2.C0: RdCmd2DataValidLatency = 20, (dlyFrmS = 15, clEff = 10, earlyCas = 0, selNTiming = 2)
N7.C1.S10: VmseWriteTraining Final: centerPi = 0x3C, PiEw = 0x27, centerVref = 0x40, vrefHeight = 0x2C
N2.C0: SettingForTrainingStep: RdCmd2RcvEnLatency = 5
N7.C1.S11: VmseWriteTraining Final: centerPi = 0x3C, PiEw = 0x29, centerVref = 0x3B, vrefHeight = 0x2C
N2.C1: RdCmd2DataValidLatency = 20, (dlyFrmS = 15, clEff = 10, earlyCas = 0, selNTiming = 2)
N7.C1.S12: VmseWriteTraining Final: centerPi = 0x43, PiEw = 0x27, centerVref = 0x3C, vrefHeight = 0x2C
N2.C1: SettingForTrainingStep: RdCmd2RcvEnLatency = 5
N7.C1.S13: VmseWriteTraining Final: centerPi = 0x42, PiEw = 0x25, centerVref = 0x44, vrefHeight = 0x2C
N2.C2: RdCmd2DataValidLatency = 20, (dlyFrmS = 15, clEff = 10, earlyCas = 0, selNTiming = 2)
N7.C1.S14: VmseWriteTraining Final: centerPi = 0x41, PiEw = 0x1E, centerVref = 0x41, vrefHeight = 0x2E
N2.C2: SettingForTrainingStep: RdCmd2RcvEnLatency = 5
N7.C1.S15: VmseWriteTraining Final: centerPi = 0x41, PiEw = 0x29, centerVref = 0x3E, vrefHeight = 0x2C
N2.C3: RdCmd2DataValidLatency = 20, (dlyFrmS = 15, clEff = 10, earlyCas = 0, selNTiming = 2)
N7.C1.S16: VmseWriteTraining Final: centerPi = 0x3B, PiEw = 0x29, centerVref = 0x42, vrefHeight = 0x2C
N2.C3: SettingForTrainingStep: RdCmd2RcvEnLatency = 5
N7.C1.S17: VmseWriteTraining Final: centerPi = 0x3A, PiEw = 0x28, centerVref = 0x42, vrefHeight = 0x2C
N1.C1.S00: VmseWriteTraining Final: centerPi = 0x37, PiEw = 0x2B, centerVref = 0x40, vrefHeight = 0x28
N2.C0.D0.R0.S00: RdDqDqs FSM results: Left = 04, Right = 60, center = 32
N7.C1.S18: VmseWriteTraining Final: centerPi = 0x3C, PiEw = 0x24, centerVref = 0x3B, vrefHeight = 0x2C
N1.C1.S01: VmseWriteTraining Final: centerPi = 0x36, PiEw = 0x26, centerVref = 0x3D, vrefHeight = 0x28
N2.C0.D0.R0.S00: RxDqsDelay = 032
N7.C1.S19: VmseWriteTraining Final: centerPi = 0x38, PiEw = 0x2C, centerVref = 0x3E, vrefHeight = 0x30
N1.C1.S02: VmseWriteTraining Final: centerPi = 0x35, PiEw = 0x26, centerVref = 0x41, vrefHeight = 0x26
N2.C0.D0.R0.S01: RdDqDqs FSM results: Left = 07, Right = 58, center = 32
N7.C1.S20: VmseWriteTraining Final: centerPi = 0x3E, PiEw = 0x24, centerVref = 0x41, vrefHeight = 0x2C
N1.C1.S03: VmseWriteTraining Final: centerPi = 0x35, PiEw = 0x29, centerVref = 0x3B, vrefHeight = 0x2A
N2.C0.D0.R0.S01: RxDqsDelay = 032
N7.C1.S21: VmseWriteTraining Final: centerPi = 0x3D, PiEw = 0x27, centerVref = 0x3E, vrefHeight = 0x2E
N1.C1.S04: VmseWriteTraining Final: centerPi = 0x3F, PiEw = 0x26, centerVref = 0x42, vrefHeight = 0x2A
N2.C0.D0.R0.S02: RdDqDqs FSM results: Left = 03, Right = 63, center = 33
N7.C1.S22: VmseWriteTraining Final: centerPi = 0x3C, PiEw = 0x26, centerVref = 0x40, vrefHeight = 0x2E
N1.C1.S05: VmseWriteTraining Final: centerPi = 0x3B, PiEw = 0x27, centerVref = 0x40, vrefHeight = 0x26
N2.C0.D0.R0.S02: RxDqsDelay = 033
N7.C1.S23: VmseWriteTraining Final: centerPi = 0x3A, PiEw = 0x28, centerVref = 0x3D, vrefHeight = 0x2A
N1.C1.S06: VmseWriteTraining Final: centerPi = 0x3D, PiEw = 0x27, centerVref = 0x40, vrefHeight = 0x2C
N2.C0.D0.R0.S03: RdDqDqs FSM results: Left = 06, Right = 60, center = 33
N7.C1.S24: VmseWriteTraining Final: centerPi = 0x3A, PiEw = 0x29, centerVref = 0x3A, vrefHeight = 0x2A
N1.C1.S07: VmseWriteTraining Final: centerPi = 0x3F, PiEw = 0x25, centerVref = 0x3B, vrefHeight = 0x2C
N2.C0.D0.R0.S03: RxDqsDelay = 033
N7.C1.S25: VmseWriteTraining Final: centerPi = 0x3A, PiEw = 0x29, centerVref = 0x3E, vrefHeight = 0x2C
N1.C1.S08: VmseWriteTraining Final: centerPi = 0x3F, PiEw = 0x1E, centerVref = 0x3B, vrefHeight = 0x28
N2.C0.D0.R0.S04: RdDqDqs FSM results: Left = 07, Right = 63, center = 35
N7.C1.S26: VmseWriteTraining Final: centerPi = 0x37, PiEw = 0x29, centerVref = 0x43, vrefHeight = 0x2C
N1.C1.S09: VmseWriteTraining Final: centerPi = 0x3D, PiEw = 0x26, centerVref = 0x3E, vrefHeight = 0x2A
N2.C0.D0.R0.S04: RxDqsDelay = 035
N7.C1.S27: VmseWriteTraining Final: centerPi = 0x39, PiEw = 0x2D, centerVref = 0x39, vrefHeight = 0x30
N1.C1.S10: VmseWriteTraining Final: centerPi = 0x3E, PiEw = 0x22, centerVref = 0x3B, vrefHeight = 0x2C
N2.C0.D0.R0.S05: RdDqDqs FSM results: Left = 06, Right = 63, center = 34
N7.C1.S28: VmseWriteTraining Final: centerPi = 0x3F, PiEw = 0x27, centerVref = 0x3E, vrefHeight = 0x2E
N1.C1.S11: VmseWriteTraining Final: centerPi = 0x3E, PiEw = 0x24, centerVref = 0x3F, vrefHeight = 0x2C
N2.C0.D0.R0.S05: RxDqsDelay = 034
N7.C1.S29: VmseWriteTraining Final: centerPi = 0x3D, PiEw = 0x27, centerVref = 0x3D, vrefHeight = 0x2A
N1.C1.S12: VmseWriteTraining Final: centerPi = 0x40, PiEw = 0x23, centerVref = 0x3F, vrefHeight = 0x28
N2.C0.D0.R0.S06: RdDqDqs FSM results: Left = 07, Right = 63, center = 35
N7.C1.S30: VmseWriteTraining Final: centerPi = 0x3E, PiEw = 0x26, centerVref = 0x3C, vrefHeight = 0x2C
N1.C1.S13: VmseWriteTraining Final: centerPi = 0x40, PiEw = 0x25, centerVref = 0x42, vrefHeight = 0x26
N2.C0.D0.R0.S06: RxDqsDelay = 035
N7.C1.S31: VmseWriteTraining Final: centerPi = 0x3E, PiEw = 0x2A, centerVref = 0x3B, vrefHeight = 0x2E
N1.C1.S14: VmseWriteTraining Final: centerPi = 0x41, PiEw = 0x22, centerVref = 0x3D, vrefHeight = 0x2A
N2.C0.D0.R0.S07: RdDqDqs FSM results: Left = 05, Right = 63, center = 34
N7.C1.S32: VmseWriteTraining Final: centerPi = 0x3C, PiEw = 0x2A, centerVref = 0x3C, vrefHeight = 0x2A
N1.C1.S15: VmseWriteTraining Final: centerPi = 0x3D, PiEw = 0x27, centerVref = 0x46, vrefHeight = 0x28
N2.C0.D0.R0.S07: RxDqsDelay = 034
N7.C1.S33: VmseWriteTraining Final: centerPi = 0x3B, PiEw = 0x2A, centerVref = 0x3B, vrefHeight = 0x2E
N1.C1.S16: VmseWriteTraining Final: centerPi = 0x38, PiEw = 0x2B, centerVref = 0x41, vrefHeight = 0x28
N2.C0.D0.R0.S08: RdDqDqs FSM results: Left = 09, Right = 63, center = 36
N7.C1.S34: VmseWriteTraining Final: centerPi = 0x38, PiEw = 0x2A, centerVref = 0x41, vrefHeight = 0x2C
N1.C1.S17: VmseWriteTraining Final: centerPi = 0x37, PiEw = 0x28, centerVref = 0x3F, vrefHeight = 0x28
N2.C0.D0.R0.S08: RxDqsDelay = 036
N7.C1.S35: VmseWriteTraining Final: centerPi = 0x3B, PiEw = 0x27, centerVref = 0x3B, vrefHeight = 0x32
N1.C1.S18: VmseWriteTraining Final: centerPi = 0x3C, PiEw = 0x24, centerVref = 0x3D, vrefHeight = 0x28
N2.C0.D0.R0.S09: RdDqDqs FSM results: Left = 05, Right = 60, center = 32
N7.C1.S36: VmseWriteTraining Final: centerPi = 0x40, PiEw = 0x26, centerVref = 0x43, vrefHeight = 0x2E
N1.C1.S19: VmseWriteTraining Final: centerPi = 0x37, PiEw = 0x29, centerVref = 0x3E, vrefHeight = 0x2A
N2.C0.D0.R0.S09: RxDqsDelay = 032
N7.C1.S37: VmseWriteTraining Final: centerPi = 0x3F, PiEw = 0x25, centerVref = 0x40, vrefHeight = 0x2C
N1.C1.S20: VmseWriteTraining Final: centerPi = 0x3B, PiEw = 0x25, centerVref = 0x3B, vrefHeight = 0x28
N2.C0.D0.R0.S10: RdDqDqs FSM results: Left = 06, Right = 61, center = 33
N7.C1.S38: VmseWriteTraining Final: centerPi = 0x40, PiEw = 0x26, centerVref = 0x3B, vrefHeight = 0x30
N1.C1.S21: VmseWriteTraining Final: centerPi = 0x3E, PiEw = 0x25, centerVref = 0x3A, vrefHeight = 0x2A
N2.C0.D0.R0.S10: RxDqsDelay = 033
N7.C1.S39: VmseWriteTraining Final: centerPi = 0x40, PiEw = 0x27, centerVref = 0x3C, vrefHeight = 0x2E
N1.C1.S22: VmseWriteTraining Final: centerPi = 0x3C, PiEw = 0x23, centerVref = 0x3E, vrefHeight = 0x2A
N2.C0.D0.R0.S11: RdDqDqs FSM results: Left = 05, Right = 63, center = 34
N7.C1.S40: VmseWriteTraining Final: centerPi = 0x3A, PiEw = 0x23, centerVref = 0x44, vrefHeight = 0x2A
N1.C1.S23: VmseWriteTraining Final: centerPi = 0x3A, PiEw = 0x28, centerVref = 0x47, vrefHeight = 0x26
N2.C0.D0.R0.S11: RxDqsDelay = 034
N7.C1.S41: VmseWriteTraining Final: centerPi = 0x36, PiEw = 0x25, centerVref = 0x3D, vrefHeight = 0x26
N1.C1.S24: VmseWriteTraining Final: centerPi = 0x3B, PiEw = 0x24, centerVref = 0x40, vrefHeight = 0x28
N2.C0.D0.R0.S12: RdDqDqs FSM results: Left = 05, Right = 63, center = 34
N7.C1.S42: VmseWriteTraining Final: centerPi = 0x3A, PiEw = 0x21, centerVref = 0x3C, vrefHeight = 0x2A
N1.C1.S25: VmseWriteTraining Final: centerPi = 0x39, PiEw = 0x28, centerVref = 0x40, vrefHeight = 0x24
N2.C0.D0.R0.S12: RxDqsDelay = 034
N7.C1.S43: VmseWriteTraining Final: centerPi = 0x39, PiEw = 0x26, centerVref = 0x3D, vrefHeight = 0x2C
N1.C1.S26: VmseWriteTraining Final: centerPi = 0x3B, PiEw = 0x22, centerVref = 0x41, vrefHeight = 0x28
N2.C0.D0.R0.S13: RdDqDqs FSM results: Left = 04, Right = 63, center = 33
N7.C1.S44: VmseWriteTraining Final: centerPi = 0x3E, PiEw = 0x25, centerVref = 0x3B, vrefHeight = 0x2C
N1.C1.S27: VmseWriteTraining Final: centerPi = 0x3C, PiEw = 0x27, centerVref = 0x3C, vrefHeight = 0x2C
N2.C0.D0.R0.S13: RxDqsDelay = 033
N7.C1.S45: VmseWriteTraining Final: centerPi = 0x3D, PiEw = 0x23, centerVref = 0x3C, vrefHeight = 0x2A
N1.C1.S28: VmseWriteTraining Final: centerPi = 0x41, PiEw = 0x21, centerVref = 0x3E, vrefHeight = 0x2C
N2.C0.D0.R0.S14: RdDqDqs FSM results: Left = 03, Right = 61, center = 32
N7.C1.S46: VmseWriteTraining Final: centerPi = 0x3C, PiEw = 0x22, centerVref = 0x3E, vrefHeight = 0x28
N1.C1.S29: VmseWriteTraining Final: centerPi = 0x3E, PiEw = 0x23, centerVref = 0x41, vrefHeight = 0x28
N2.C0.D0.R0.S14: RxDqsDelay = 032
N7.C1.S47: VmseWriteTraining Final: centerPi = 0x3D, PiEw = 0x26, centerVref = 0x3C, vrefHeight = 0x2A
N1.C1.S30: VmseWriteTraining Final: centerPi = 0x3B, PiEw = 0x29, centerVref = 0x42, vrefHeight = 0x28
N2.C0.D0.R0.S15: RdDqDqs FSM results: Left = 04, Right = 63, center = 33
N7.C1.S48: VmseWriteTraining Final: centerPi = 0x3B, PiEw = 0x27, centerVref = 0x3F, vrefHeight = 0x2A
N1.C1.S31: VmseWriteTraining Final: centerPi = 0x43, PiEw = 0x22, centerVref = 0x3C, vrefHeight = 0x2A
N2.C0.D0.R0.S15: RxDqsDelay = 033
N7.C1.S49: VmseWriteTraining Final: centerPi = 0x3D, PiEw = 0x28, centerVref = 0x3A, vrefHeight = 0x32
N1.C1.S32: VmseWriteTraining Final: centerPi = 0x3C, PiEw = 0x24, centerVref = 0x3D, vrefHeight = 0x28
N2.C0.D0.R0.S16: RdDqDqs FSM results: Left = 06, Right = 63, center = 34
N7.C1.S50: VmseWriteTraining Final: centerPi = 0x3B, PiEw = 0x25, centerVref = 0x3B, vrefHeight = 0x2E
N1.C1.S33: VmseWriteTraining Final: centerPi = 0x3B, PiEw = 0x24, centerVref = 0x3C, vrefHeight = 0x2A
N2.C0.D0.R0.S16: RxDqsDelay = 034
N7.C1.S51: VmseWriteTraining Final: centerPi = 0x3C, PiEw = 0x2A, centerVref = 0x3E, vrefHeight = 0x30
N1.C1.S34: VmseWriteTraining Final: centerPi = 0x3D, PiEw = 0x26, centerVref = 0x3F, vrefHeight = 0x2E
N2.C0.D0.R0.S17: RdDqDqs FSM results: Left = 08, Right = 60, center = 34
N7.C1.S52: VmseWriteTraining Final: centerPi = 0x3F, PiEw = 0x25, centerVref = 0x3C, vrefHeight = 0x2E
N1.C1.S35: VmseWriteTraining Final: centerPi = 0x3E, PiEw = 0x25, centerVref = 0x3A, vrefHeight = 0x2E
N2.C0.D0.R0.S17: RxDqsDelay = 034
N7.C1.S53: VmseWriteTraining Final: centerPi = 0x40, PiEw = 0x25, centerVref = 0x3C, vrefHeight = 0x2C
N1.C1.S36: VmseWriteTraining Final: centerPi = 0x40, PiEw = 0x27, centerVref = 0x3B, vrefHeight = 0x2C
N2.C0.D0.R1.S00: RdDqDqs FSM results: Left = 05, Right = 63, center = 34
N7.C1.S54: VmseWriteTraining Final: centerPi = 0x3F, PiEw = 0x29, centerVref = 0x3B, vrefHeight = 0x30
N1.C1.S37: VmseWriteTraining Final: centerPi = 0x44, PiEw = 0x22, centerVref = 0x36, vrefHeight = 0x2A
N2.C0.D0.R1.S00: RxDqsDelay = 034
N7.C1.S55: VmseWriteTraining Final: centerPi = 0x3C, PiEw = 0x25, centerVref = 0x3D, vrefHeight = 0x2A
N1.C1.S38: VmseWriteTraining Final: centerPi = 0x3F, PiEw = 0x26, centerVref = 0x3B, vrefHeight = 0x2C
N2.C0.D0.R1.S01: RdDqDqs FSM results: Left = 06, Right = 63, center = 34
N7.C1.S56: VmseWriteTraining Final: centerPi = 0x3B, PiEw = 0x28, centerVref = 0x40, vrefHeight = 0x28
N1.C1.S39: VmseWriteTraining Final: centerPi = 0x3D, PiEw = 0x27, centerVref = 0x3F, vrefHeight = 0x28
N2.C0.D0.R1.S01: RxDqsDelay = 034
N7.C1.S57: VmseWriteTraining Final: centerPi = 0x3D, PiEw = 0x2B, centerVref = 0x40, vrefHeight = 0x30
N1.C1.S40: VmseWriteTraining Final: centerPi = 0x3D, PiEw = 0x20, centerVref = 0x3B, vrefHeight = 0x26
N2.C0.D0.R1.S02: RdDqDqs FSM results: Left = 04, Right = 63, center = 33
N7.C1.S58: VmseWriteTraining Final: centerPi = 0x3C, PiEw = 0x2A, centerVref = 0x3A, vrefHeight = 0x30
N1.C1.S41: VmseWriteTraining Final: centerPi = 0x39, PiEw = 0x26, centerVref = 0x41, vrefHeight = 0x24
N2.C0.D0.R1.S02: RxDqsDelay = 033
N7.C1.S59: VmseWriteTraining Final: centerPi = 0x3B, PiEw = 0x2B, centerVref = 0x3D, vrefHeight = 0x30
N1.C1.S42: VmseWriteTraining Final: centerPi = 0x38, PiEw = 0x1B, centerVref = 0x41, vrefHeight = 0x22
N2.C0.D0.R1.S03: RdDqDqs FSM results: Left = 07, Right = 63, center = 35
N7.C1.S60: VmseWriteTraining Final: centerPi = 0x3F, PiEw = 0x23, centerVref = 0x3D, vrefHeight = 0x2C
N1.C1.S43: VmseWriteTraining Final: centerPi = 0x39, PiEw = 0x1F, centerVref = 0x3B, vrefHeight = 0x28
N2.C0.D0.R1.S03: RxDqsDelay = 035
N7.C1.S61: VmseWriteTraining Final: centerPi = 0x3E, PiEw = 0x23, centerVref = 0x3C, vrefHeight = 0x28
N1.C1.S44: VmseWriteTraining Final: centerPi = 0x3F, PiEw = 0x24, centerVref = 0x41, vrefHeight = 0x28
N2.C0.D0.R1.S04: RdDqDqs FSM results: Left = 07, Right = 63, center = 35
N7.C1.S62: VmseWriteTraining Final: centerPi = 0x42, PiEw = 0x27, centerVref = 0x3D, vrefHeight = 0x2C
N1.C1.S45: VmseWriteTraining Final: centerPi = 0x3D, PiEw = 0x1D, centerVref = 0x3F, vrefHeight = 0x24
N2.C0.D0.R1.S04: RxDqsDelay = 035
N7.C1.S63: VmseWriteTraining Final: centerPi = 0x3D, PiEw = 0x28, centerVref = 0x41, vrefHeight = 0x2A
N1.C1.S46: VmseWriteTraining Final: centerPi = 0x42, PiEw = 0x1E, centerVref = 0x36, vrefHeight = 0x2A
N2.C0.D0.R1.S05: RdDqDqs FSM results: Left = 04, Right = 63, center = 33
N7.C1.S64: VmseWriteTraining Final: centerPi = 0x3B, PiEw = 0x25, centerVref = 0x3F, vrefHeight = 0x2C
N1.C1.S47: VmseWriteTraining Final: centerPi = 0x3E, PiEw = 0x24, centerVref = 0x42, vrefHeight = 0x26
N2.C0.D0.R1.S05: RxDqsDelay = 033
N7.C1.S65: VmseWriteTraining Final: centerPi = 0x38, PiEw = 0x29, centerVref = 0x43, vrefHeight = 0x2C
N1.C1.S48: VmseWriteTraining Final: centerPi = 0x41, PiEw = 0x20, centerVref = 0x3A, vrefHeight = 0x28
N2.C0.D0.R1.S06: RdDqDqs FSM results: Left = 06, Right = 63, center = 34
N7.C1.S66: VmseWriteTraining Final: centerPi = 0x39, PiEw = 0x22, centerVref = 0x40, vrefHeight = 0x2C
N1.C1.S49: VmseWriteTraining Final: centerPi = 0x43, PiEw = 0x23, centerVref = 0x3D, vrefHeight = 0x2C
N2.C0.D0.R1.S06: RxDqsDelay = 034
N7.C1.S67: VmseWriteTraining Final: centerPi = 0x39, PiEw = 0x25, centerVref = 0x3E, vrefHeight = 0x2E
N1.C1.S50: VmseWriteTraining Final: centerPi = 0x3C, PiEw = 0x2A, centerVref = 0x41, vrefHeight = 0x2C
N2.C0.D0.R1.S07: RdDqDqs FSM results: Left = 06, Right = 63, center = 34
N7.C1.S68: VmseWriteTraining Final: centerPi = 0x41, PiEw = 0x23, centerVref = 0x3A, vrefHeight = 0x2C
N1.C1.S51: VmseWriteTraining Final: centerPi = 0x3F, PiEw = 0x2B, centerVref = 0x39, vrefHeight = 0x30
N2.C0.D0.R1.S07: RxDqsDelay = 034
N7.C1.S69: VmseWriteTraining Final: centerPi = 0x3E, PiEw = 0x25, centerVref = 0x38, vrefHeight = 0x2C
N1.C1.S52: VmseWriteTraining Final: centerPi = 0x43, PiEw = 0x27, centerVref = 0x3A, vrefHeight = 0x2A
N2.C0.D0.R1.S08: RdDqDqs FSM results: Left = 09, Right = 63, center = 36
N7.C1.S70: VmseWriteTraining Final: centerPi = 0x3D, PiEw = 0x22, centerVref = 0x3D, vrefHeight = 0x30
N1.C1.S53: VmseWriteTraining Final: centerPi = 0x40, PiEw = 0x25, centerVref = 0x3D, vrefHeight = 0x28
N2.C0.D0.R1.S08: RxDqsDelay = 036
N7.C1.S71: VmseWriteTraining Final: centerPi = 0x3F, PiEw = 0x21, centerVref = 0x3A, vrefHeight = 0x2E
N1.C1.S54: VmseWriteTraining Final: centerPi = 0x3F, PiEw = 0x28, centerVref = 0x3E, vrefHeight = 0x2C
N2.C0.D0.R1.S09: RdDqDqs FSM results: Left = 04, Right = 63, center = 33

END - VMSE Train Write                 Time         3358 ms
N1.C1.S55: VmseWriteTraining Final: centerPi = 0x3E, PiEw = 0x27, centerVref = 0x3F, vrefHeight = 0x28
N2.C0.D0.R1.S09: RxDqsDelay = 033
N7: 
Total VMSE trainings latency = 16366 ms
N1.C1.S56: VmseWriteTraining Final: centerPi = 0x3E, PiEw = 0x1F, centerVref = 0x44, vrefHeight = 0x26
N2.C0.D0.R1.S10: RdDqDqs FSM results: Left = 07, Right = 59, center = 33
N6: PostVmseTraining
N1.C1.S57: VmseWriteTraining Final: centerPi = 0x3E, PiEw = 0x28, centerVref = 0x40, vrefHeight = 0x2A
N2.C0.D0.R1.S10: RxDqsDelay = 033
N6.C0: PostVmseTraining
N1.C1.S58: VmseWriteTraining Final: centerPi = 0x3C, PiEw = 0x25, centerVref = 0x3D, vrefHeight = 0x2C
N2.C0.D0.R1.S11: RdDqDqs FSM results: Left = 04, Right = 63, center = 33
N6.C0: PostVMSE Training VMSE Health Check Passed
N1.C1.S59: VmseWriteTraining Final: centerPi = 0x3B, PiEw = 0x28, centerVref = 0x3D, vrefHeight = 0x2C
N2.C0.D0.R1.S11: RxDqsDelay = 033
N6.C1: PostVmseTraining
N1.C1.S60: VmseWriteTraining Final: centerPi = 0x41, PiEw = 0x24, centerVref = 0x3C, vrefHeight = 0x26
N2.C0.D0.R1.S12: RdDqDqs FSM results: Left = 05, Right = 63, center = 34
N6.C2: PostVMSE Training VMSE Health Check Passed
N1.C1.S61: VmseWriteTraining Final: centerPi = 0x3F, PiEw = 0x27, centerVref = 0x42, vrefHeight = 0x26
N2.C0.D0.R1.S12: RxDqsDelay = 034
N6: PreDdrTraining
N1.C1.S62: VmseWriteTraining Final: centerPi = 0x42, PiEw = 0x1F, centerVref = 0x3A, vrefHeight = 0x2A
N2.C0.D0.R1.S13: RdDqDqs FSM results: Left = 05, Right = 63, center = 34
N6: PreDdrTraining[QCRM=OFF]
N1.C1.S63: VmseWriteTraining Final: centerPi = 0x3E, PiEw = 0x27, centerVref = 0x42, vrefHeight = 0x28
N2.C0.D0.R1.S13: RxDqsDelay = 034
N6.C0.D0: CheckRankPopLocal: dimmPresent: 1, numRanks = 2
N1.C1.S64: VmseWriteTraining Final: centerPi = 0x41, PiEw = 0x1F, centerVref = 0x3E, vrefHeight = 0x2C
N2.C0.D0.R1.S14: RdDqDqs FSM results: Left = 04, Right = 60, center = 32
N6.C0.D0.R0: CheckRankPopLocal: mapOut: 0, enabled = 1
N1.C1.S65: VmseWriteTraining Final: centerPi = 0x3A, PiEw = 0x22, centerVref = 0x3E, vrefHeight = 0x28
N2.C0.D0.R1.S14: RxDqsDelay = 032
N6.C0.D0.R1: CheckRankPopLocal: mapOut: 0, enabled = 1
N1.C1.S66: VmseWriteTraining Final: centerPi = 0x3D, PiEw = 0x1E, centerVref = 0x3C, vrefHeight = 0x2A
N2.C0.D0.R1.S15: RdDqDqs FSM results: Left = 05, Right = 63, center = 34
N6.C0.D1: CheckRankPopLocal: dimmPresent: 1, numRanks = 2
N1.C1.S67: VmseWriteTraining Final: centerPi = 0x3A, PiEw = 0x25, centerVref = 0x45, vrefHeight = 0x2C
N2.C0.D0.R1.S15: RxDqsDelay = 034
N6.C0.D1.R0: CheckRankPopLocal: mapOut: 0, enabled = 1
N1.C1.S68: VmseWriteTraining Final: centerPi = 0x40, PiEw = 0x20, centerVref = 0x43, vrefHeight = 0x28
N2.C0.D0.R1.S16: RdDqDqs FSM results: Left = 05, Right = 63, center = 34
N6.C0.D1.R1: CheckRankPopLocal: mapOut: 0, enabled = 1
N1.C1.S69: VmseWriteTraining Final: centerPi = 0x40, PiEw = 0x22, centerVref = 0x3E, vrefHeight = 0x2A
N2.C0.D0.R1.S16: RxDqsDelay = 034
N6.C0.D2: CheckRankPopLocal: dimmPresent: 0, numRanks = 0
N1.C1.S70: VmseWriteTraining Final: centerPi = 0x3F, PiEw = 0x1C, centerVref = 0x40, vrefHeight = 0x2C
N2.C0.D0.R1.S17: RdDqDqs FSM results: Left = 07, Right = 63, center = 35
N6.C0.D0: CheckRankPopLocal: amap: 0x00000000
N1.C1.S71: VmseWriteTraining Final: centerPi = 0x3E, PiEw = 0x21, centerVref = 0x3C, vrefHeight = 0x2A
N2.C0.D0.R1.S17: RxDqsDelay = 035
N6.C0.D1: CheckRankPopLocal: amap: 0x00000000

END - VMSE Train Write                 Time         3508 ms
N2.C0.D1.R0.S00: RdDqDqs FSM results: Left = 08, Right = 63, center = 35
N6.C0.D2: CheckRankPopLocal: amap: 0x00000000
Checkpoint Code: Socket 0, 0xB6, 0x64, 0x0000
N2.C0.D1.R0.S00: RxDqsDelay = 035
N6.C1.D0: CheckRankPopLocal: dimmPresent: 1, numRanks = 2
N1: 
Total VMSE trainings latency = 16592 ms
N2.C0.D1.R0.S01: RdDqDqs FSM results: Left = 09, Right = 63, center = 36
N6.C1.D0.R0: CheckRankPopLocal: mapOut: 0, enabled = 1
N0: PostVmseTraining
N2.C0.D1.R0.S01: RxDqsDelay = 036
N6.C1.D0.R1: CheckRankPopLocal: mapOut: 0, enabled = 1
Checkpoint Code: Socket 0, 0xB6, 0x5C, 0x0000
N2.C0.D1.R0.S02: RdDqDqs FSM results: Left = 07, Right = 63, center = 35
N6.C1.D1: CheckRankPopLocal: dimmPresent: 1, numRanks = 2
N0.C0: PostVmseTraining
N2.C0.D1.R0.S02: RxDqsDelay = 035
N6.C1.D1.R0: CheckRankPopLocal: mapOut: 0, enabled = 1
N0.C0: PostVMSE Training VMSE Health Check Passed
N2.C0.D1.R0.S03: RdDqDqs FSM results: Left = 09, Right = 63, center = 36
N6.C1.D1.R1: CheckRankPopLocal: mapOut: 0, enabled = 1
N0.C1: PostVmseTraining
N2.C0.D1.R0.S03: RxDqsDelay = 036
N6.C1.D2: CheckRankPopLocal: dimmPresent: 0, numRanks = 0
N0.C2: PostVMSE Training VMSE Health Check Passed
N2.C0.D1.R0.S04: RdDqDqs FSM results: Left = 11, Right = 63, center = 37
N6.C1.D0: CheckRankPopLocal: amap: 0x00000000
N0: PreDdrTraining
N2.C0.D1.R0.S04: RxDqsDelay = 037
N6.C1.D1: CheckRankPopLocal: amap: 0x00000000
N0: PreDdrTraining[QCRM=OFF]
N2.C0.D1.R0.S05: RdDqDqs FSM results: Left = 08, Right = 63, center = 35
N6.C1.D2: CheckRankPopLocal: amap: 0x00000000
N0.C0.D0: CheckRankPopLocal: dimmPresent: 1, numRanks = 2
N2.C0.D1.R0.S05: RxDqsDelay = 035
N6.C2.D0: CheckRankPopLocal: dimmPresent: 1, numRanks = 2
N0.C0.D0.R0: CheckRankPopLocal: mapOut: 0, enabled = 1
N2.C0.D1.R0.S06: RdDqDqs FSM results: Left = 10, Right = 63, center = 36
N6.C2.D0.R0: CheckRankPopLocal: mapOut: 0, enabled = 1
N0.C0.D0.R1: CheckRankPopLocal: mapOut: 0, enabled = 1
N2.C0.D1.R0.S06: RxDqsDelay = 036
N6.C2.D0.R1: CheckRankPopLocal: mapOut: 0, enabled = 1
N0.C0.D1: CheckRankPopLocal: dimmPresent: 1, numRanks = 2
N2.C0.D1.R0.S07: RdDqDqs FSM results: Left = 09, Right = 63, center = 36
N6.C2.D1: CheckRankPopLocal: dimmPresent: 1, numRanks = 2
N0.C0.D1.R0: CheckRankPopLocal: mapOut: 0, enabled = 1
N2.C0.D1.R0.S07: RxDqsDelay = 036
N6.C2.D1.R0: CheckRankPopLocal: mapOut: 0, enabled = 1
N0.C0.D1.R1: CheckRankPopLocal: mapOut: 0, enabled = 1
N2.C0.D1.R0.S08: RdDqDqs FSM results: Left = 11, Right = 63, center = 37
N6.C2.D1.R1: CheckRankPopLocal: mapOut: 0, enabled = 1
N0.C0.D2: CheckRankPopLocal: dimmPresent: 0, numRanks = 0
N2.C0.D1.R0.S08: RxDqsDelay = 037
N6.C2.D2: CheckRankPopLocal: dimmPresent: 0, numRanks = 0
N0.C0.D0: CheckRankPopLocal: amap: 0x00000000
N2.C0.D1.R0.S09: RdDqDqs FSM results: Left = 08, Right = 63, center = 35
N6.C2.D0: CheckRankPopLocal: amap: 0x00000000
N0.C0.D1: CheckRankPopLocal: amap: 0x00000000
N2.C0.D1.R0.S09: RxDqsDelay = 035
N6.C2.D1: CheckRankPopLocal: amap: 0x00000000
N0.C0.D2: CheckRankPopLocal: amap: 0x00000000
N2.C0.D1.R0.S10: RdDqDqs FSM results: Left = 09, Right = 61, center = 35
N6.C2.D2: CheckRankPopLocal: amap: 0x00000000
N0.C1.D0: CheckRankPopLocal: dimmPresent: 1, numRanks = 2
N2.C0.D1.R0.S10: RxDqsDelay = 035
N6.C3.D0: CheckRankPopLocal: dimmPresent: 1, numRanks = 2
N0.C1.D0.R0: CheckRankPopLocal: mapOut: 0, enabled = 1
N2.C0.D1.R0.S11: RdDqDqs FSM results: Left = 07, Right = 63, center = 35
N6.C3.D0.R0: CheckRankPopLocal: mapOut: 0, enabled = 1
N0.C1.D0.R1: CheckRankPopLocal: mapOut: 0, enabled = 1
N2.C0.D1.R0.S11: RxDqsDelay = 035
N6.C3.D0.R1: CheckRankPopLocal: mapOut: 0, enabled = 1
N0.C1.D1: CheckRankPopLocal: dimmPresent: 1, numRanks = 2
N2.C0.D1.R0.S12: RdDqDqs FSM results: Left = 08, Right = 63, center = 35
N6.C3.D1: CheckRankPopLocal: dimmPresent: 1, numRanks = 2
N0.C1.D1.R0: CheckRankPopLocal: mapOut: 0, enabled = 1
N2.C0.D1.R0.S12: RxDqsDelay = 035
N6.C3.D1.R0: CheckRankPopLocal: mapOut: 0, enabled = 1
N0.C1.D1.R1: CheckRankPopLocal: mapOut: 0, enabled = 1
N2.C0.D1.R0.S13: RdDqDqs FSM results: Left = 08, Right = 63, center = 35
N6.C3.D1.R1: CheckRankPopLocal: mapOut: 0, enabled = 1
N0.C1.D2: CheckRankPopLocal: dimmPresent: 0, numRanks = 0
N2.C0.D1.R0.S13: RxDqsDelay = 035
N6.C3.D2: CheckRankPopLocal: dimmPresent: 0, numRanks = 0
N0.C1.D0: CheckRankPopLocal: amap: 0x00000000
N2.C0.D1.R0.S14: RdDqDqs FSM results: Left = 06, Right = 63, center = 34
N6.C3.D0: CheckRankPopLocal: amap: 0x00000000
N0.C1.D1: CheckRankPopLocal: amap: 0x00000000
N2.C0.D1.R0.S14: RxDqsDelay = 034
N6.C3.D1: CheckRankPopLocal: amap: 0x00000000
N0.C1.D2: CheckRankPopLocal: amap: 0x00000000
N2.C0.D1.R0.S15: RdDqDqs FSM results: Left = 08, Right = 63, center = 35
N6.C3.D2: CheckRankPopLocal: amap: 0x00000000
N0.C2.D0: CheckRankPopLocal: dimmPresent: 1, numRanks = 2
N2.C0.D1.R0.S15: RxDqsDelay = 035
N6.C0: JCK cmd timing = 3N
N0.C2.D0.R0: CheckRankPopLocal: mapOut: 0, enabled = 1
N2.C0.D1.R0.S16: RdDqDqs FSM results: Left = 08, Right = 63, center = 35
N6.C0: RdCmd2DataValidLatency = 20, (dlyFrmS = 15, clEff = 10, earlyCas = 0, selNTiming = 2)
N0.C2.D0.R1: CheckRankPopLocal: mapOut: 0, enabled = 1
N2.C0.D1.R0.S16: RxDqsDelay = 035
N6.C0: CLK0_CFG: 0x000FFF30
N0.C2.D1: CheckRankPopLocal: dimmPresent: 1, numRanks = 2
N2.C0.D1.R0.S17: RdDqDqs FSM results: Left = 10, Right = 63, center = 36
N6.C0: DDR_RANKCTL: 0x000FEA40
N0.C2.D1.R0: CheckRankPopLocal: mapOut: 0, enabled = 1
N2.C0.D1.R0.S17: RxDqsDelay = 036
N6.C0: MCODT = 0 ( 50 ohms)
N0.C2.D1.R1: CheckRankPopLocal: mapOut: 0, enabled = 1
N2.C0.D1.R1.S00: RdDqDqs FSM results: Left = 08, Right = 63, center = 35
N6.C0.D0.R0: Rtt_wr = 120, Rtt_nom = 20
N0.C2.D2: CheckRankPopLocal: dimmPresent: 0, numRanks = 0
N2.C0.D1.R1.S00: RxDqsDelay = 035
N6.C0.D0.R1: Rtt_wr = 120, Rtt_nom = 0
N0.C2.D0: CheckRankPopLocal: amap: 0x00000000
N2.C0.D1.R1.S01: RdDqDqs FSM results: Left = 09, Right = 63, center = 36
N6.C0.D1.R0: Rtt_wr = 120, Rtt_nom = 20
N0.C2.D1: CheckRankPopLocal: amap: 0x00000000
N2.C0.D1.R1.S01: RxDqsDelay = 036
N6.C0.D1.R1: Rtt_wr = 120, Rtt_nom = 0
N0.C2.D2: CheckRankPopLocal: amap: 0x00000000
N2.C0.D1.R1.S02: RdDqDqs FSM results: Left = 07, Right = 63, center = 35
N6.C0: ODTRDCTL00 = 0x01000104
N0.C3.D0: CheckRankPopLocal: dimmPresent: 1, numRanks = 2
N2.C0.D1.R1.S02: RxDqsDelay = 035
N6.C0: ODTRDCTL01 = 0x00000001
N0.C3.D0.R0: CheckRankPopLocal: mapOut: 0, enabled = 1
N2.C0.D1.R1.S03: RdDqDqs FSM results: Left = 09, Right = 63, center = 36
N6.C0: ODTWRCTL00 = 0x05000185
N0.C3.D0.R1: CheckRankPopLocal: mapOut: 0, enabled = 1
N2.C0.D1.R1.S03: RxDqsDelay = 036
N6.C0: ODTWRCTL01 = 0x00000009
N0.C3.D1: CheckRankPopLocal: dimmPresent: 1, numRanks = 2
N2.C0.D1.R1.S04: RdDqDqs FSM results: Left = 10, Right = 63, center = 36
N6.C1: RdCmd2DataValidLatency = 20, (dlyFrmS = 15, clEff = 10, earlyCas = 0, selNTiming = 2)
N0.C3.D1.R0: CheckRankPopLocal: mapOut: 0, enabled = 1
N2.C0.D1.R1.S04: RxDqsDelay = 036
N6.C1: CLK0_CFG: 0x000FF330
N0.C3.D1.R1: CheckRankPopLocal: mapOut: 0, enabled = 1
N2.C0.D1.R1.S05: RdDqDqs FSM results: Left = 07, Right = 63, center = 35
N6.C1: DDR_RANKCTL: 0x000FEA40
N0.C3.D2: CheckRankPopLocal: dimmPresent: 0, numRanks = 0
N2.C0.D1.R1.S05: RxDqsDelay = 035
N6.C1: MCODT = 0 ( 50 ohms)
N0.C3.D0: CheckRankPopLocal: amap: 0x00000000
N2.C0.D1.R1.S06: RdDqDqs FSM results: Left = 11, Right = 63, center = 37
N6.C1.D0.R0: Rtt_wr = 120, Rtt_nom = 20
N0.C3.D1: CheckRankPopLocal: amap: 0x00000000
N2.C0.D1.R1.S06: RxDqsDelay = 037
N6.C1.D0.R1: Rtt_wr = 120, Rtt_nom = 0
N0.C3.D2: CheckRankPopLocal: amap: 0x00000000
N2.C0.D1.R1.S07: RdDqDqs FSM results: Left = 10, Right = 63, center = 36
N6.C1.D1.R0: Rtt_wr = 120, Rtt_nom = 20
N0.C0: JCK cmd timing = 3N
N2.C0.D1.R1.S07: RxDqsDelay = 036
N6.C1.D1.R1: Rtt_wr = 120, Rtt_nom = 0
N0.C0: RdCmd2DataValidLatency = 20, (dlyFrmS = 15, clEff = 10, earlyCas = 0, selNTiming = 2)
N2.C0.D1.R1.S08: RdDqDqs FSM results: Left = 12, Right = 63, center = 37
N6.C1: ODTRDCTL00 = 0x01000104
N0.C0: CLK0_CFG: 0x000FFF30
N2.C0.D1.R1.S08: RxDqsDelay = 037
N6.C1: ODTRDCTL01 = 0x00000001
N0.C0: DDR_RANKCTL: 0x000FEA40
N2.C0.D1.R1.S09: RdDqDqs FSM results: Left = 08, Right = 63, center = 35
N6.C1: ODTWRCTL00 = 0x05000185
N0.C0: MCODT = 0 ( 50 ohms)
N2.C0.D1.R1.S09: RxDqsDelay = 035
N6.C1: ODTWRCTL01 = 0x00000009
N0.C0.D0.R0: Rtt_wr = 120, Rtt_nom = 20
N2.C0.D1.R1.S10: RdDqDqs FSM results: Left = 09, Right = 63, center = 36
N6.C2: JCK cmd timing = 3N
N0.C0.D0.R1: Rtt_wr = 120, Rtt_nom = 0
N2.C0.D1.R1.S10: RxDqsDelay = 036
N6.C2: RdCmd2DataValidLatency = 20, (dlyFrmS = 15, clEff = 10, earlyCas = 0, selNTiming = 2)
N0.C0.D1.R0: Rtt_wr = 120, Rtt_nom = 20
N2.C0.D1.R1.S11: RdDqDqs FSM results: Left = 07, Right = 63, center = 35
N6.C2: CLK0_CFG: 0x000FFF30
N0.C0.D1.R1: Rtt_wr = 120, Rtt_nom = 0
N2.C0.D1.R1.S11: RxDqsDelay = 035
N6.C2: DDR_RANKCTL: 0x000FEA40
N0.C0: ODTRDCTL00 = 0x01000104
N2.C0.D1.R1.S12: RdDqDqs FSM results: Left = 08, Right = 63, center = 35
N6.C2: MCODT = 0 ( 50 ohms)
N0.C0: ODTRDCTL01 = 0x00000001
N2.C0.D1.R1.S12: RxDqsDelay = 035
N6.C2.D0.R0: Rtt_wr = 120, Rtt_nom = 20
N0.C0: ODTWRCTL00 = 0x05000185
N2.C0.D1.R1.S13: RdDqDqs FSM results: Left = 08, Right = 63, center = 35
N6.C2.D0.R1: Rtt_wr = 120, Rtt_nom = 0
N0.C0: ODTWRCTL01 = 0x00000009
N2.C0.D1.R1.S13: RxDqsDelay = 035
N6.C2.D1.R0: Rtt_wr = 120, Rtt_nom = 20
N0.C1: RdCmd2DataValidLatency = 20, (dlyFrmS = 15, clEff = 10, earlyCas = 0, selNTiming = 2)
N2.C0.D1.R1.S14: RdDqDqs FSM results: Left = 06, Right = 63, center = 34
N4.C0.D0: CalcFinalClock(91,119) = 22
N6.C2.D1.R1: Rtt_wr = 120, Rtt_nom = 0
N0.C1: CLK0_CFG: 0x000FF330
N2.C0.D1.R1.S14: RxDqsDelay = 034
N4.C0.D1: CalcFinalClock(96,114) = 25
N6.C2: ODTRDCTL00 = 0x01000104
N0.C1: DDR_RANKCTL: 0x000FEA40
N2.C0.D1.R1.S15: RdDqDqs FSM results: Left = 08, Right = 63, center = 35
N4.C1.D0: CalcFinalClock(96,113) = 24
N6.C2: ODTRDCTL01 = 0x00000001
N0.C1: MCODT = 0 ( 50 ohms)
N2.C0.D1.R1.S15: RxDqsDelay = 035
N4.C1.D1: CalcFinalClock(99,120) = 31
N6.C2: ODTWRCTL00 = 0x05000185
N0.C1.D0.R0: Rtt_wr = 120, Rtt_nom = 20
N2.C0.D1.R1.S16: RdDqDqs FSM results: Left = 08, Right = 63, center = 35
N4.C2.D0: CalcFinalClock(87,124) = 21
N6.C2: ODTWRCTL01 = 0x00000009
N0.C1.D0.R1: Rtt_wr = 120, Rtt_nom = 0
N2.C0.D1.R1.S16: RxDqsDelay = 035
N4.C2.D1: CalcFinalClock(98,115) = 27
N6.C3: RdCmd2DataValidLatency = 20, (dlyFrmS = 15, clEff = 10, earlyCas = 0, selNTiming = 2)
N0.C1.D1.R0: Rtt_wr = 120, Rtt_nom = 20
N2.C0.D1.R1.S17: RdDqDqs FSM results: Left = 10, Right = 63, center = 36
N4.C3.D0: CalcFinalClock(95,108) = 21
N6.C3: CLK0_CFG: 0x000FF330
N0.C1.D1.R1: Rtt_wr = 120, Rtt_nom = 0
N2.C0.D1.R1.S17: RxDqsDelay = 036
N4.C3.D1: CalcFinalClock(100,117) = 30
N6.C3: DDR_RANKCTL: 0x000FEA40
N0.C1: ODTRDCTL00 = 0x01000104
START_DATA_RX_DQS
N4.C0: JCK cmd timing = 3N
N6.C3: MCODT = 0 ( 50 ohms)
N0.C1: ODTRDCTL01 = 0x00000001
N2.C0.R0.S00: PI = 33
N4.C0: RdCmd2DataValidLatency = 20, (dlyFrmS = 15, clEff = 10, earlyCas = 0, selNTiming = 2)
N6.C3.D0.R0: Rtt_wr = 120, Rtt_nom = 20
N0.C1: ODTWRCTL00 = 0x05000185
N2.C0.R0.S01: PI = 33
N4.C1: RdCmd2DataValidLatency = 20, (dlyFrmS = 15, clEff = 10, earlyCas = 0, selNTiming = 2)
N6.C3.D0.R1: Rtt_wr = 120, Rtt_nom = 0
N0.C1: ODTWRCTL01 = 0x00000009
N2.C0.R0.S02: PI = 33
N4.C2: JCK cmd timing = 3N
N6.C3.D1.R0: Rtt_wr = 120, Rtt_nom = 20
N0.C2: JCK cmd timing = 3N
N2.C0.R0.S03: PI = 34
N4.C2: RdCmd2DataValidLatency = 20, (dlyFrmS = 15, clEff = 10, earlyCas = 0, selNTiming = 2)
N6.C3.D1.R1: Rtt_wr = 120, Rtt_nom = 0
N0.C2: RdCmd2DataValidLatency = 20, (dlyFrmS = 15, clEff = 10, earlyCas = 0, selNTiming = 2)
N2.C0.R0.S04: PI = 35
N4.C3: RdCmd2DataValidLatency = 20, (dlyFrmS = 15, clEff = 10, earlyCas = 0, selNTiming = 2)
N6.C3: ODTRDCTL00 = 0x01000104
N0.C2: CLK0_CFG: 0x000FFF30
N2.C0.R0.S05: PI = 33
N4: RunTrainStep: Final status = 0
N6.C3: ODTRDCTL01 = 0x00000001
N0.C2: DDR_RANKCTL: 0x000FEA40
N2.C0.R0.S06: PI = 34

END - Early Command Training           Time         3747 ms
N6.C3: ODTWRCTL00 = 0x05000185
N0.C2: MCODT = 0 ( 50 ohms)
N2.C0.R0.S07: PI = 34

START - Basic Read DQ/DQS Training
N6.C3: ODTWRCTL01 = 0x00000009
N0.C2.D0.R0: Rtt_wr = 120, Rtt_nom = 20
N2.C0.R0.S08: PI = 36
N4.C0: RdCmd2DataValidLatency = 20, (dlyFrmS = 15, clEff = 10, earlyCas = 0, selNTiming = 2)
N6.C0.D0: PreDdrTraining: Program dimmmtr 0xC502D
N0.C2.D0.R1: Rtt_wr = 120, Rtt_nom = 0
N2.C0.R0.S09: PI = 32
N4.C0: SettingForTrainingStep: RdCmd2RcvEnLatency = 5
N6.C0.D1: PreDdrTraining: Program dimmmtr 0xC502D
N0.C2.D1.R0: Rtt_wr = 120, Rtt_nom = 20
N2.C0.R0.S10: PI = 33
N4.C1: RdCmd2DataValidLatency = 20, (dlyFrmS = 15, clEff = 10, earlyCas = 0, selNTiming = 2)
N6.C1.D0: PreDdrTraining: Program dimmmtr 0xC502D
N0.C2.D1.R1: Rtt_wr = 120, Rtt_nom = 0
N2.C0.R0.S11: PI = 33
N4.C1: SettingForTrainingStep: RdCmd2RcvEnLatency = 5
N6.C1.D1: PreDdrTraining: Program dimmmtr 0xC502D
N0.C2: ODTRDCTL00 = 0x01000104
N2.C0.R0.S12: PI = 34
N4.C2: RdCmd2DataValidLatency = 20, (dlyFrmS = 15, clEff = 10, earlyCas = 0, selNTiming = 2)
N6.C2.D0: PreDdrTraining: Program dimmmtr 0xC502D
N0.C2: ODTRDCTL01 = 0x00000001
N2.C0.R0.S13: PI = 33
N4.C2: SettingForTrainingStep: RdCmd2RcvEnLatency = 5
N6.C2.D1: PreDdrTraining: Program dimmmtr 0xC502D
N0.C2: ODTWRCTL00 = 0x05000185
N2.C0.R0.S14: PI = 32
N4.C3: RdCmd2DataValidLatency = 20, (dlyFrmS = 15, clEff = 10, earlyCas = 0, selNTiming = 2)
N6.C3.D0: PreDdrTraining: Program dimmmtr 0xC502D
N0.C2: ODTWRCTL01 = 0x00000009
N2.C0.R0.S15: PI = 33
N4.C3: SettingForTrainingStep: RdCmd2RcvEnLatency = 5
N6.C3.D1: PreDdrTraining: Program dimmmtr 0xC502D
N0.C3: RdCmd2DataValidLatency = 20, (dlyFrmS = 15, clEff = 10, earlyCas = 0, selNTiming = 2)
N2.C0.R0.S16: PI = 34
N4.C0.D0.R0.S00: RdDqDqs FSM results: Left = 11, Right = 63, center = 37
N6: InitializeDdrioForUse
N0.C3: CLK0_CFG: 0x000FF330
N2.C0.R0.S17: PI = 34
N4.C0.D0.R0.S00: RxDqsDelay = 037
N6: SetupJckForBL: setting BL to 8
N0.C3: DDR_RANKCTL: 0x000FEA40
N2.C0.R0.S00: PI = 33
N4.C0.D0.R0.S01: RdDqDqs FSM results: Left = 11, Right = 63, center = 37
N6.C0: ODTTIMCTL (INIT RELAX) rdwidth = 10 rddly = 0 wrwidth = 8 wrdly = 0
N0.C3: MCODT = 0 ( 50 ohms)
N2.C0.R0.S01: PI = 33
N4.C0.D0.R0.S01: RxDqsDelay = 037
N6.C1: ODTTIMCTL (INIT RELAX) rdwidth = 10 rddly = 0 wrwidth = 8 wrdly = 0
N0.C3.D0.R0: Rtt_wr = 120, Rtt_nom = 20
N2.C0.R0.S02: PI = 33
N4.C0.D0.R0.S02: RdDqDqs FSM results: Left = 14, Right = 63, center = 38
N6.C2: ODTTIMCTL (INIT RELAX) rdwidth = 10 rddly = 0 wrwidth = 8 wrdly = 0
N0.C3.D0.R1: Rtt_wr = 120, Rtt_nom = 0
N2.C0.R0.S03: PI = 34
N4.C0.D0.R0.S02: RxDqsDelay = 038
N6.C3: ODTTIMCTL (INIT RELAX) rdwidth = 10 rddly = 0 wrwidth = 8 wrdly = 0
N0.C3.D1.R0: Rtt_wr = 120, Rtt_nom = 20
N2.C0.R0.S04: PI = 35
N4.C0.D0.R0.S03: RdDqDqs FSM results: Left = 12, Right = 63, center = 37
N6: JckDdrTraining
N0.C3.D1.R1: Rtt_wr = 120, Rtt_nom = 0
N2.C0.R0.S05: PI = 33
N4.C0.D0.R0.S03: RxDqsDelay = 037
N6: InitializeDdrioForTraining: QCRM Disabled
N0.C3: ODTRDCTL00 = 0x01000104
N2.C0.R0.S06: PI = 34
N4.C0.D0.R0.S04: RdDqDqs FSM results: Left = 12, Right = 63, center = 37
N6.C0: InitializeDdrioForTraining: cleff = 10
N0.C3: ODTRDCTL01 = 0x00000001
N2.C0.R0.S07: PI = 34
N4.C0.D0.R0.S04: RxDqsDelay = 037
N6.C0: InitializeDdrioForTraining: cwleff = 8
N0.C3: ODTWRCTL00 = 0x05000185
N2.C0.R0.S08: PI = 36
N4.C0.D0.R0.S05: RdDqDqs FSM results: Left = 11, Right = 63, center = 37
N6.C0: InitializeDdrioForTraining: initial ddrInitIndexRx = 4 ddrInitIndexTx = 2
N0.C3: ODTWRCTL01 = 0x00000009
N2.C0.R0.S09: PI = 32
N4.C0.D0.R0.S05: RxDqsDelay = 037
N6.C0: InitializeDdrioForTraining: initial RdCmd2RcvEnLatency = 5
N0.C0.D0: PreDdrTraining: Program dimmmtr 0xC502D
N2.C0.R0.S10: PI = 33
N4.C0.D0.R0.S06: RdDqDqs FSM results: Left = 14, Right = 63, center = 38
N6.C0: InitializeDdrioForTraining: initial RdPtrOffsetRcvEn = 4
N0.C0.D1: PreDdrTraining: Program dimmmtr 0xC502D
N2.C0.R0.S11: PI = 33
N4.C0.D0.R0.S06: RxDqsDelay = 038
N6.C0: InitializeDdrioForTraining: initial rkrdptroffsetrcvenb = 6
N0.C1.D0: PreDdrTraining: Program dimmmtr 0xC502D
N2.C0.R0.S12: PI = 34
N4.C0.D0.R0.S07: RdDqDqs FSM results: Left = 13, Right = 63, center = 38
N6.C0: InitializeDdrioForTraining: initial rkrdptroffsetdrvenrcvenb = 5
N0.C1.D1: PreDdrTraining: Program dimmmtr 0xC502D
N2.C0.R0.S13: PI = 33
N4.C0.D0.R0.S07: RxDqsDelay = 038
N6.C0: InitializeDdrioForTraining: initial WrCmd2DqsStartLatency = 4
N0.C2.D0: PreDdrTraining: Program dimmmtr 0xC502D
N2.C0.R0.S14: PI = 32
N4.C0.D0.R0.S08: RdDqDqs FSM results: Left = 12, Right = 63, center = 37
N6.C0: InitializeDdrioForTraining: initial RdPtrOffsetDqs = 10
N0.C2.D1: PreDdrTraining: Program dimmmtr 0xC502D
N2.C0.R0.S15: PI = 33
N4.C0.D0.R0.S08: RxDqsDelay = 037
N6.C0: InitializeDdrioForTraining: initial RdCmd2RcvEnLatency = 5
N0.C3.D0: PreDdrTraining: Program dimmmtr 0xC502D
N2.C0.R0.S16: PI = 34
N4.C0.D0.R0.S09: RdDqDqs FSM results: Left = 14, Right = 63, center = 38
N6.C0: InitializeDdrioForTraining: initial WrCmd2DqsStartLatency = 4
N0.C3.D1: PreDdrTraining: Program dimmmtr 0xC502D
N2.C0.R0.S17: PI = 34
N4.C0.D0.R0.S09: RxDqsDelay = 038
N6.C0: InitializeDdrioForTraining: initial RdPtrOffsetRcvEn = 4
N0: InitializeDdrioForUse
N2.C0.R2.S00: PI = 35
N4.C0.D0.R0.S10: RdDqDqs FSM results: Left = 11, Right = 63, center = 37
N6.C0: InitializeDdrioForTraining: initial RdPtrOffsetDqs = 6
N0: SetupJckForBL: setting BL to 8
N2.C0.R2.S01: PI = 36
N4.C0.D0.R0.S10: RxDqsDelay = 037
N6.C0: InitializeDdrioForTraining: initial RdPtrOffsetDq = 5
N0.C0: ODTTIMCTL (INIT RELAX) rdwidth = 10 rddly = 0 wrwidth = 8 wrdly = 0
N2.C0.R2.S02: PI = 35
N4.C0.D0.R0.S11: RdDqDqs FSM results: Left = 11, Right = 63, center = 37
N6.C1: InitializeDdrioForTraining: cleff = 10
N0.C1: ODTTIMCTL (INIT RELAX) rdwidth = 10 rddly = 0 wrwidth = 8 wrdly = 0
N2.C0.R2.S03: PI = 36
N4.C0.D0.R0.S11: RxDqsDelay = 037
N6.C1: InitializeDdrioForTraining: cwleff = 8
N0.C2: ODTTIMCTL (INIT RELAX) rdwidth = 10 rddly = 0 wrwidth = 8 wrdly = 0
N2.C0.R2.S04: PI = 36
N4.C0.D0.R0.S12: RdDqDqs FSM results: Left = 12, Right = 63, center = 37
N6.C1: InitializeDdrioForTraining: initial ddrInitIndexRx = 4 ddrInitIndexTx = 2
N0.C3: ODTTIMCTL (INIT RELAX) rdwidth = 10 rddly = 0 wrwidth = 8 wrdly = 0
N2.C0.R2.S05: PI = 35
N4.C0.D0.R0.S12: RxDqsDelay = 037
N6.C1: InitializeDdrioForTraining: initial RdCmd2RcvEnLatency = 5
N0: JckDdrTraining
N2.C0.R2.S06: PI = 36
N4.C0.D0.R0.S13: RdDqDqs FSM results: Left = 10, Right = 63, center = 36
N6.C1: InitializeDdrioForTraining: initial RdPtrOffsetRcvEn = 4
N0: InitializeDdrioForTraining: QCRM Disabled
N2.C0.R2.S07: PI = 36
N4.C0.D0.R0.S13: RxDqsDelay = 036
N6.C1: InitializeDdrioForTraining: initial rkrdptroffsetrcvenb = 6
N0.C0: InitializeDdrioForTraining: cleff = 10
N2.C0.R2.S08: PI = 37
N4.C0.D0.R0.S14: RdDqDqs FSM results: Left = 11, Right = 63, center = 37
N6.C1: InitializeDdrioForTraining: initial rkrdptroffsetdrvenrcvenb = 5
N0.C0: InitializeDdrioForTraining: cwleff = 8
N2.C0.R2.S09: PI = 35
N4.C0.D0.R0.S14: RxDqsDelay = 037
N6.C1: InitializeDdrioForTraining: initial WrCmd2DqsStartLatency = 4
N0.C0: InitializeDdrioForTraining: initial ddrInitIndexRx = 4 ddrInitIndexTx = 2
N2.C0.R2.S10: PI = 35
N4.C0.D0.R0.S15: RdDqDqs FSM results: Left = 09, Right = 63, center = 36
N6.C1: InitializeDdrioForTraining: initial RdPtrOffsetDqs = 10
N0.C0: InitializeDdrioForTraining: initial RdCmd2RcvEnLatency = 5
N2.C0.R2.S11: PI = 35
N4.C0.D0.R0.S15: RxDqsDelay = 036
N6.C1: InitializeDdrioForTraining: initial RdCmd2RcvEnLatency = 5
N0.C0: InitializeDdrioForTraining: initial RdPtrOffsetRcvEn = 4
N2.C0.R2.S12: PI = 35
N4.C0.D0.R0.S16: RdDqDqs FSM results: Left = 11, Right = 63, center = 37
N6.C1: InitializeDdrioForTraining: initial WrCmd2DqsStartLatency = 4
N0.C0: InitializeDdrioForTraining: initial rkrdptroffsetrcvenb = 6
N2.C0.R2.S13: PI = 35
N4.C0.D0.R0.S16: RxDqsDelay = 037
N6.C1: InitializeDdrioForTraining: initial RdPtrOffsetRcvEn = 4
N0.C0: InitializeDdrioForTraining: initial rkrdptroffsetdrvenrcvenb = 5
N2.C0.R2.S14: PI = 34
N4.C0.D0.R0.S17: RdDqDqs FSM results: Left = 10, Right = 63, center = 36
N6.C1: InitializeDdrioForTraining: initial RdPtrOffsetDqs = 6
N0.C0: InitializeDdrioForTraining: initial WrCmd2DqsStartLatency = 4
N2.C0.R2.S15: PI = 35
N4.C0.D0.R0.S17: RxDqsDelay = 036
N6.C1: InitializeDdrioForTraining: initial RdPtrOffsetDq = 5
N0.C0: InitializeDdrioForTraining: initial RdPtrOffsetDqs = 10
N2.C0.R2.S16: PI = 35
N4.C0.D0.R1.S00: RdDqDqs FSM results: Left = 10, Right = 63, center = 36
N6.C2: InitializeDdrioForTraining: cleff = 10
N0.C0: InitializeDdrioForTraining: initial RdCmd2RcvEnLatency = 5
N2.C0.R2.S17: PI = 36
N4.C0.D0.R1.S00: RxDqsDelay = 036
N6.C2: InitializeDdrioForTraining: cwleff = 8
N0.C0: InitializeDdrioForTraining: initial WrCmd2DqsStartLatency = 4
N2.C0.R2.S00: PI = 35
N4.C0.D0.R1.S01: RdDqDqs FSM results: Left = 10, Right = 63, center = 36
N6.C2: InitializeDdrioForTraining: initial ddrInitIndexRx = 4 ddrInitIndexTx = 2
N0.C0: InitializeDdrioForTraining: initial RdPtrOffsetRcvEn = 4
N2.C0.R2.S01: PI = 36
N4.C0.D0.R1.S01: RxDqsDelay = 036
N6.C2: InitializeDdrioForTraining: initial RdCmd2RcvEnLatency = 5
N0.C0: InitializeDdrioForTraining: initial RdPtrOffsetDqs = 6
N2.C0.R2.S02: PI = 35
N4.C0.D0.R1.S02: RdDqDqs FSM results: Left = 13, Right = 63, center = 38
N6.C2: InitializeDdrioForTraining: initial RdPtrOffsetRcvEn = 4
N0.C0: InitializeDdrioForTraining: initial RdPtrOffsetDq = 5
N2.C0.R2.S03: PI = 36
N4.C0.D0.R1.S02: RxDqsDelay = 038
N6.C2: InitializeDdrioForTraining: initial rkrdptroffsetrcvenb = 6
N0.C1: InitializeDdrioForTraining: cleff = 10
N2.C0.R2.S04: PI = 36
N4.C0.D0.R1.S03: RdDqDqs FSM results: Left = 12, Right = 63, center = 37
N6.C2: InitializeDdrioForTraining: initial rkrdptroffsetdrvenrcvenb = 5
N0.C1: InitializeDdrioForTraining: cwleff = 8
N2.C0.R2.S05: PI = 35
N4.C0.D0.R1.S03: RxDqsDelay = 037
N6.C2: InitializeDdrioForTraining: initial WrCmd2DqsStartLatency = 4
N0.C1: InitializeDdrioForTraining: initial ddrInitIndexRx = 4 ddrInitIndexTx = 2
N2.C0.R2.S06: PI = 36
N4.C0.D0.R1.S04: RdDqDqs FSM results: Left = 12, Right = 63, center = 37
N6.C2: InitializeDdrioForTraining: initial RdPtrOffsetDqs = 10
N0.C1: InitializeDdrioForTraining: initial RdCmd2RcvEnLatency = 5
N2.C0.R2.S07: PI = 36
N4.C0.D0.R1.S04: RxDqsDelay = 037
N6.C2: InitializeDdrioForTraining: initial RdCmd2RcvEnLatency = 5
N0.C1: InitializeDdrioForTraining: initial RdPtrOffsetRcvEn = 4
N2.C0.R2.S08: PI = 37
N4.C0.D0.R1.S05: RdDqDqs FSM results: Left = 11, Right = 63, center = 37
N6.C2: InitializeDdrioForTraining: initial WrCmd2DqsStartLatency = 4
N0.C1: InitializeDdrioForTraining: initial rkrdptroffsetrcvenb = 6
N2.C0.R2.S09: PI = 35
N4.C0.D0.R1.S05: RxDqsDelay = 037
N6.C2: InitializeDdrioForTraining: initial RdPtrOffsetRcvEn = 4
N0.C1: InitializeDdrioForTraining: initial rkrdptroffsetdrvenrcvenb = 5
N2.C0.R2.S10: PI = 35
N4.C0.D0.R1.S06: RdDqDqs FSM results: Left = 14, Right = 63, center = 38
N6.C2: InitializeDdrioForTraining: initial RdPtrOffsetDqs = 6
N0.C1: InitializeDdrioForTraining: initial WrCmd2DqsStartLatency = 4
N2.C0.R2.S11: PI = 35
N4.C0.D0.R1.S06: RxDqsDelay = 038
N6.C2: InitializeDdrioForTraining: initial RdPtrOffsetDq = 5
N0.C1: InitializeDdrioForTraining: initial RdPtrOffsetDqs = 10
N2.C0.R2.S12: PI = 35
N4.C0.D0.R1.S07: RdDqDqs FSM results: Left = 13, Right = 63, center = 38
N6.C3: InitializeDdrioForTraining: cleff = 10
N0.C1: InitializeDdrioForTraining: initial RdCmd2RcvEnLatency = 5
N2.C0.R2.S13: PI = 35
N4.C0.D0.R1.S07: RxDqsDelay = 038
N6.C3: InitializeDdrioForTraining: cwleff = 8
N0.C1: InitializeDdrioForTraining: initial WrCmd2DqsStartLatency = 4
N2.C0.R2.S14: PI = 34
N4.C0.D0.R1.S08: RdDqDqs FSM results: Left = 12, Right = 63, center = 37
N6.C3: InitializeDdrioForTraining: initial ddrInitIndexRx = 4 ddrInitIndexTx = 2
N0.C1: InitializeDdrioForTraining: initial RdPtrOffsetRcvEn = 4
N2.C0.R2.S15: PI = 35
N4.C0.D0.R1.S08: RxDqsDelay = 037
N6.C3: InitializeDdrioForTraining: initial RdCmd2RcvEnLatency = 5
N0.C1: InitializeDdrioForTraining: initial RdPtrOffsetDqs = 6
N2.C0.R2.S16: PI = 35
N4.C0.D0.R1.S09: RdDqDqs FSM results: Left = 13, Right = 63, center = 38
N6.C3: InitializeDdrioForTraining: initial RdPtrOffsetRcvEn = 4
N0.C1: InitializeDdrioForTraining: initial RdPtrOffsetDq = 5
N2.C0.R2.S17: PI = 36
N4.C0.D0.R1.S09: RxDqsDelay = 038
N6.C3: InitializeDdrioForTraining: initial rkrdptroffsetrcvenb = 6
N0.C2: InitializeDdrioForTraining: cleff = 10
STOP_DATA_RX_DQS
N4.C0.D0.R1.S10: RdDqDqs FSM results: Left = 10, Right = 63, center = 36
N6.C3: InitializeDdrioForTraining: initial rkrdptroffsetdrvenrcvenb = 5
N0.C2: InitializeDdrioForTraining: cwleff = 8
N2.C1.D0.R0.S00: RdDqDqs FSM results: Left = 03, Right = 63, center = 33
N4.C0.D0.R1.S10: RxDqsDelay = 036
N6.C3: InitializeDdrioForTraining: initial WrCmd2DqsStartLatency = 4
N0.C2: InitializeDdrioForTraining: initial ddrInitIndexRx = 4 ddrInitIndexTx = 2
N2.C1.D0.R0.S00: RxDqsDelay = 033
N4.C0.D0.R1.S11: RdDqDqs FSM results: Left = 11, Right = 63, center = 37
N6.C3: InitializeDdrioForTraining: initial RdPtrOffsetDqs = 10
N0.C2: InitializeDdrioForTraining: initial RdCmd2RcvEnLatency = 5
N2.C1.D0.R0.S01: RdDqDqs FSM results: Left = 05, Right = 63, center = 34
N4.C0.D0.R1.S11: RxDqsDelay = 037
N6.C3: InitializeDdrioForTraining: initial RdCmd2RcvEnLatency = 5
N0.C2: InitializeDdrioForTraining: initial RdPtrOffsetRcvEn = 4
N2.C1.D0.R0.S01: RxDqsDelay = 034
N4.C0.D0.R1.S12: RdDqDqs FSM results: Left = 13, Right = 63, center = 38
N6.C3: InitializeDdrioForTraining: initial WrCmd2DqsStartLatency = 4
N0.C2: InitializeDdrioForTraining: initial rkrdptroffsetrcvenb = 6
N2.C1.D0.R0.S02: RdDqDqs FSM results: Left = 03, Right = 61, center = 32
N4.C0.D0.R1.S12: RxDqsDelay = 038
N6.C3: InitializeDdrioForTraining: initial RdPtrOffsetRcvEn = 4
N0.C2: InitializeDdrioForTraining: initial rkrdptroffsetdrvenrcvenb = 5
N2.C1.D0.R0.S02: RxDqsDelay = 032
N4.C0.D0.R1.S13: RdDqDqs FSM results: Left = 10, Right = 63, center = 36
N6.C3: InitializeDdrioForTraining: initial RdPtrOffsetDqs = 6
N0.C2: InitializeDdrioForTraining: initial WrCmd2DqsStartLatency = 4
N2.C1.D0.R0.S03: RdDqDqs FSM results: Left = 06, Right = 63, center = 34
N4.C0.D0.R1.S13: RxDqsDelay = 036
N6.C3: InitializeDdrioForTraining: initial RdPtrOffsetDq = 5
N0.C2: InitializeDdrioForTraining: initial RdPtrOffsetDqs = 10
N2.C1.D0.R0.S03: RxDqsDelay = 034
N4.C0.D0.R1.S14: RdDqDqs FSM results: Left = 12, Right = 63, center = 37
N6: DdrClockStopWa
N0.C2: InitializeDdrioForTraining: initial RdCmd2RcvEnLatency = 5
N2.C1.D0.R0.S04: RdDqDqs FSM results: Left = 06, Right = 63, center = 34
N4.C0.D0.R1.S14: RxDqsDelay = 037
N6: JckSetOdtRelaxTiming:
N0.C2: InitializeDdrioForTraining: initial WrCmd2DqsStartLatency = 4
N2.C1.D0.R0.S04: RxDqsDelay = 034
N4.C0.D0.R1.S15: RdDqDqs FSM results: Left = 10, Right = 63, center = 36
N6.C0: ODTTIMCTL (INIT RELAX) rdwidth = 10 rddly = 0 wrwidth = 8 wrdly = 0
N0.C2: InitializeDdrioForTraining: initial RdPtrOffsetRcvEn = 4
N2.C1.D0.R0.S05: RdDqDqs FSM results: Left = 05, Right = 63, center = 34
N4.C0.D0.R1.S15: RxDqsDelay = 036
N6.C0.S00: DDRIOHSIODATA0_LATCTL1 = 08040804
N0.C2: InitializeDdrioForTraining: initial RdPtrOffsetDqs = 6
N2.C1.D0.R0.S05: RxDqsDelay = 034
N4.C0.D0.R1.S16: RdDqDqs FSM results: Left = 10, Right = 63, center = 36
N6.C0.S01: DDRIOHSIODATA0_LATCTL1 = 08040804
N0.C2: InitializeDdrioForTraining: initial RdPtrOffsetDq = 5
N2.C1.D0.R0.S06: RdDqDqs FSM results: Left = 04, Right = 63, center = 33
N4.C0.D0.R1.S16: RxDqsDelay = 036
N6.C0.S02: DDRIOHSIODATA0_LATCTL1 = 08040804
N0.C3: InitializeDdrioForTraining: cleff = 10
N2.C1.D0.R0.S06: RxDqsDelay = 033
N4.C0.D0.R1.S17: RdDqDqs FSM results: Left = 11, Right = 63, center = 37
N6.C0.S03: DDRIOHSIODATA0_LATCTL1 = 08040804
N0.C3: InitializeDdrioForTraining: cwleff = 8
N2.C1.D0.R0.S07: RdDqDqs FSM results: Left = 06, Right = 63, center = 34
N4.C0.D0.R1.S17: RxDqsDelay = 037
N6.C0.S04: DDRIOHSIODATA0_LATCTL1 = 08040804
N0.C3: InitializeDdrioForTraining: initial ddrInitIndexRx = 4 ddrInitIndexTx = 2
N2.C1.D0.R0.S07: RxDqsDelay = 034
N4.C0.D1.R0.S00: RdDqDqs FSM results: Left = 13, Right = 63, center = 38
N6.C0.S05: DDRIOHSIODATA0_LATCTL1 = 08040804
N0.C3: InitializeDdrioForTraining: initial RdCmd2RcvEnLatency = 5
N2.C1.D0.R0.S08: RdDqDqs FSM results: Left = 03, Right = 58, center = 30
N4.C0.D1.R0.S00: RxDqsDelay = 038
N6.C0.S06: DDRIOHSIODATA0_LATCTL1 = 08040804
N0.C3: InitializeDdrioForTraining: initial RdPtrOffsetRcvEn = 4
N2.C1.D0.R0.S08: RxDqsDelay = 030
N4.C0.D1.R0.S01: RdDqDqs FSM results: Left = 14, Right = 63, center = 38
N6.C0.S07: DDRIOHSIODATA0_LATCTL1 = 08040804
N0.C3: InitializeDdrioForTraining: initial rkrdptroffsetrcvenb = 6
N2.C1.D0.R0.S09: RdDqDqs FSM results: Left = 03, Right = 63, center = 33
N4.C0.D1.R0.S01: RxDqsDelay = 038
N6.C0.S08: DDRIOHSIODATA0_LATCTL1 = 08040804
N0.C3: InitializeDdrioForTraining: initial rkrdptroffsetdrvenrcvenb = 5
N2.C1.D0.R0.S09: RxDqsDelay = 033
N4.C0.D1.R0.S02: RdDqDqs FSM results: Left = 16, Right = 63, center = 39
N6.C1: ODTTIMCTL (INIT RELAX) rdwidth = 10 rddly = 0 wrwidth = 8 wrdly = 0
N0.C3: InitializeDdrioForTraining: initial WrCmd2DqsStartLatency = 4
N2.C1.D0.R0.S10: RdDqDqs FSM results: Left = 04, Right = 60, center = 32
N4.C0.D1.R0.S02: RxDqsDelay = 039
N6.C1.S00: DDRIOHSIODATA0_LATCTL1 = 08040804
N0.C3: InitializeDdrioForTraining: initial RdPtrOffsetDqs = 10
N2.C1.D0.R0.S10: RxDqsDelay = 032
N4.C0.D1.R0.S03: RdDqDqs FSM results: Left = 13, Right = 63, center = 38
N6.C1.S01: DDRIOHSIODATA0_LATCTL1 = 08040804
N0.C3: InitializeDdrioForTraining: initial RdCmd2RcvEnLatency = 5
N2.C1.D0.R0.S11: RdDqDqs FSM results: Left = 02, Right = 63, center = 32
N4.C0.D1.R0.S03: RxDqsDelay = 038
N6.C1.S02: DDRIOHSIODATA0_LATCTL1 = 08040804
N0.C3: InitializeDdrioForTraining: initial WrCmd2DqsStartLatency = 4
N2.C1.D0.R0.S11: RxDqsDelay = 032
N4.C0.D1.R0.S04: RdDqDqs FSM results: Left = 15, Right = 63, center = 39
N6.C1.S03: DDRIOHSIODATA0_LATCTL1 = 08040804
N0.C3: InitializeDdrioForTraining: initial RdPtrOffsetRcvEn = 4
N2.C1.D0.R0.S12: RdDqDqs FSM results: Left = 05, Right = 58, center = 31
N4.C0.D1.R0.S04: RxDqsDelay = 039
N6.C1.S04: DDRIOHSIODATA0_LATCTL1 = 08040804
N0.C3: InitializeDdrioForTraining: initial RdPtrOffsetDqs = 6
N2.C1.D0.R0.S12: RxDqsDelay = 031
N4.C0.D1.R0.S05: RdDqDqs FSM results: Left = 14, Right = 63, center = 38
N6.C1.S05: DDRIOHSIODATA0_LATCTL1 = 08040804
N0.C3: InitializeDdrioForTraining: initial RdPtrOffsetDq = 5
N2.C1.D0.R0.S13: RdDqDqs FSM results: Left = 03, Right = 57, center = 30
N4.C0.D1.R0.S05: RxDqsDelay = 038
N6.C1.S06: DDRIOHSIODATA0_LATCTL1 = 08040804
N0: DdrClockStopWa
N2.C1.D0.R0.S13: RxDqsDelay = 030
N4.C0.D1.R0.S06: RdDqDqs FSM results: Left = 16, Right = 63, center = 39
N6.C1.S07: DDRIOHSIODATA0_LATCTL1 = 08040804
N0: JckSetOdtRelaxTiming:
N2.C1.D0.R0.S14: RdDqDqs FSM results: Left = 08, Right = 63, center = 35
N4.C0.D1.R0.S06: RxDqsDelay = 039
N6.C1.S08: DDRIOHSIODATA0_LATCTL1 = 08040804
N0.C0: ODTTIMCTL (INIT RELAX) rdwidth = 10 rddly = 0 wrwidth = 8 wrdly = 0
N2.C1.D0.R0.S14: RxDqsDelay = 035
N4.C0.D1.R0.S07: RdDqDqs FSM results: Left = 17, Right = 63, center = 40
N6.C2: ODTTIMCTL (INIT RELAX) rdwidth = 10 rddly = 0 wrwidth = 8 wrdly = 0
N0.C0.S00: DDRIOHSIODATA0_LATCTL1 = 08040804
N2.C1.D0.R0.S15: RdDqDqs FSM results: Left = 06, Right = 63, center = 34
N4.C0.D1.R0.S07: RxDqsDelay = 040
N6.C2.S00: DDRIOHSIODATA0_LATCTL1 = 08040804
N0.C0.S01: DDRIOHSIODATA0_LATCTL1 = 08040804
N2.C1.D0.R0.S15: RxDqsDelay = 034
N4.C0.D1.R0.S08: RdDqDqs FSM results: Left = 17, Right = 63, center = 40
N6.C2.S01: DDRIOHSIODATA0_LATCTL1 = 08040804
N0.C0.S02: DDRIOHSIODATA0_LATCTL1 = 08040804
N2.C1.D0.R0.S16: RdDqDqs FSM results: Left = 05, Right = 63, center = 34
N4.C0.D1.R0.S08: RxDqsDelay = 040
N6.C2.S02: DDRIOHSIODATA0_LATCTL1 = 08040804
N0.C0.S03: DDRIOHSIODATA0_LATCTL1 = 08040804
N2.C1.D0.R0.S16: RxDqsDelay = 034
N4.C0.D1.R0.S09: RdDqDqs FSM results: Left = 17, Right = 63, center = 40
N6.C2.S03: DDRIOHSIODATA0_LATCTL1 = 08040804
N0.C0.S04: DDRIOHSIODATA0_LATCTL1 = 08040804
N2.C1.D0.R0.S17: RdDqDqs FSM results: Left = 01, Right = 56, center = 28
N4.C0.D1.R0.S09: RxDqsDelay = 040
N6.C2.S04: DDRIOHSIODATA0_LATCTL1 = 08040804
N0.C0.S05: DDRIOHSIODATA0_LATCTL1 = 08040804
N2.C1.D0.R0.S17: RxDqsDelay = 028
N4.C0.D1.R0.S10: RdDqDqs FSM results: Left = 14, Right = 63, center = 38
N6.C2.S05: DDRIOHSIODATA0_LATCTL1 = 08040804
N0.C0.S06: DDRIOHSIODATA0_LATCTL1 = 08040804
N2.C1.D0.R1.S00: RdDqDqs FSM results: Left = 04, Right = 60, center = 32
N4.C0.D1.R0.S10: RxDqsDelay = 038
N6.C2.S06: DDRIOHSIODATA0_LATCTL1 = 08040804
N0.C0.S07: DDRIOHSIODATA0_LATCTL1 = 08040804
N2.C1.D0.R1.S00: RxDqsDelay = 032
N4.C0.D1.R0.S11: RdDqDqs FSM results: Left = 13, Right = 63, center = 38
N6.C2.S07: DDRIOHSIODATA0_LATCTL1 = 08040804
N0.C0.S08: DDRIOHSIODATA0_LATCTL1 = 08040804
N2.C1.D0.R1.S01: RdDqDqs FSM results: Left = 05, Right = 63, center = 34
N4.C0.D1.R0.S11: RxDqsDelay = 038
N6.C2.S08: DDRIOHSIODATA0_LATCTL1 = 08040804
N0.C1: ODTTIMCTL (INIT RELAX) rdwidth = 10 rddly = 0 wrwidth = 8 wrdly = 0
N2.C1.D0.R1.S01: RxDqsDelay = 034
N4.C0.D1.R0.S12: RdDqDqs FSM results: Left = 15, Right = 63, center = 39
N6.C3: ODTTIMCTL (INIT RELAX) rdwidth = 10 rddly = 0 wrwidth = 8 wrdly = 0
N0.C1.S00: DDRIOHSIODATA0_LATCTL1 = 08040804
N2.C1.D0.R1.S02: RdDqDqs FSM results: Left = 04, Right = 63, center = 33
N4.C0.D1.R0.S12: RxDqsDelay = 039
N6.C3.S00: DDRIOHSIODATA0_LATCTL1 = 08040804
N0.C1.S01: DDRIOHSIODATA0_LATCTL1 = 08040804
N2.C1.D0.R1.S02: RxDqsDelay = 033
N4.C0.D1.R0.S13: RdDqDqs FSM results: Left = 13, Right = 63, center = 38
N6.C3.S01: DDRIOHSIODATA0_LATCTL1 = 08040804
N0.C1.S02: DDRIOHSIODATA0_LATCTL1 = 08040804
N2.C1.D0.R1.S03: RdDqDqs FSM results: Left = 06, Right = 63, center = 34
N4.C0.D1.R0.S13: RxDqsDelay = 038
N6.C3.S02: DDRIOHSIODATA0_LATCTL1 = 08040804
N0.C1.S03: DDRIOHSIODATA0_LATCTL1 = 08040804
N2.C1.D0.R1.S03: RxDqsDelay = 034
N4.C0.D1.R0.S14: RdDqDqs FSM results: Left = 14, Right = 63, center = 38
N6.C3.S03: DDRIOHSIODATA0_LATCTL1 = 08040804
N0.C1.S04: DDRIOHSIODATA0_LATCTL1 = 08040804
N2.C1.D0.R1.S04: RdDqDqs FSM results: Left = 06, Right = 63, center = 34
N4.C0.D1.R0.S14: RxDqsDelay = 038
N6.C3.S04: DDRIOHSIODATA0_LATCTL1 = 08040804
N0.C1.S05: DDRIOHSIODATA0_LATCTL1 = 08040804
N2.C1.D0.R1.S04: RxDqsDelay = 034
N4.C0.D1.R0.S15: RdDqDqs FSM results: Left = 12, Right = 63, center = 37
N6.C3.S05: DDRIOHSIODATA0_LATCTL1 = 08040804
N0.C1.S06: DDRIOHSIODATA0_LATCTL1 = 08040804
N2.C1.D0.R1.S05: RdDqDqs FSM results: Left = 04, Right = 63, center = 33
N4.C0.D1.R0.S15: RxDqsDelay = 037
N6.C3.S06: DDRIOHSIODATA0_LATCTL1 = 08040804
N0.C1.S07: DDRIOHSIODATA0_LATCTL1 = 08040804
N2.C1.D0.R1.S05: RxDqsDelay = 033
N4.C0.D1.R0.S16: RdDqDqs FSM results: Left = 15, Right = 63, center = 39
N6.C3.S07: DDRIOHSIODATA0_LATCTL1 = 08040804
N0.C1.S08: DDRIOHSIODATA0_LATCTL1 = 08040804
N2.C1.D0.R1.S06: RdDqDqs FSM results: Left = 04, Right = 63, center = 33
N4.C0.D1.R0.S16: RxDqsDelay = 039
N6.C3.S08: DDRIOHSIODATA0_LATCTL1 = 08040804
N0.C2: ODTTIMCTL (INIT RELAX) rdwidth = 10 rddly = 0 wrwidth = 8 wrdly = 0
N2.C1.D0.R1.S06: RxDqsDelay = 033
N4.C0.D1.R0.S17: RdDqDqs FSM results: Left = 15, Right = 63, center = 39

START - Early Command Training
N0.C2.S00: DDRIOHSIODATA0_LATCTL1 = 08040804
N2.C1.D0.R1.S07: RdDqDqs FSM results: Left = 05, Right = 63, center = 34
N4.C0.D1.R0.S17: RxDqsDelay = 039
N6.C0: DDRIOHSIODATA0_LATCTL1 = 08040804
N0.C2.S01: DDRIOHSIODATA0_LATCTL1 = 08040804
N2.C1.D0.R1.S07: RxDqsDelay = 034
N4.C0.D1.R1.S00: RdDqDqs FSM results: Left = 12, Right = 63, center = 37
N6.C0: RdCmd2DataValidLatency = 20, (dlyFrmS = 15, clEff = 10, earlyCas = 0, selNTiming = 2)
N0.C2.S02: DDRIOHSIODATA0_LATCTL1 = 08040804
N2.C1.D0.R1.S08: RdDqDqs FSM results: Left = 03, Right = 59, center = 31
N4.C0.D1.R1.S00: RxDqsDelay = 037
N6.C0: SettingForTrainingStep: RdCmd2RcvEnLatency = 5
N0.C2.S03: DDRIOHSIODATA0_LATCTL1 = 08040804
N2.C1.D0.R1.S08: RxDqsDelay = 031
N4.C0.D1.R1.S01: RdDqDqs FSM results: Left = 14, Right = 63, center = 38
N6.C0: SettingForTrainingStep: Programming 7 tick initial value to CTL signals
N0.C2.S04: DDRIOHSIODATA0_LATCTL1 = 08040804
N2.C1.D0.R1.S09: RdDqDqs FSM results: Left = 04, Right = 61, center = 32
N4.C0.D1.R1.S01: RxDqsDelay = 038
N6.C1: DDRIOHSIODATA0_LATCTL1 = 08040804
N0.C2.S05: DDRIOHSIODATA0_LATCTL1 = 08040804
N2.C1.D0.R1.S09: RxDqsDelay = 032
N4.C0.D1.R1.S02: RdDqDqs FSM results: Left = 16, Right = 63, center = 39
N6.C1: RdCmd2DataValidLatency = 20, (dlyFrmS = 15, clEff = 10, earlyCas = 0, selNTiming = 2)
N0.C2.S06: DDRIOHSIODATA0_LATCTL1 = 08040804
N2.C1.D0.R1.S10: RdDqDqs FSM results: Left = 04, Right = 58, center = 31
N4.C0.D1.R1.S02: RxDqsDelay = 039
N6.C1: SettingForTrainingStep: RdCmd2RcvEnLatency = 5
N0.C2.S07: DDRIOHSIODATA0_LATCTL1 = 08040804
N2.C1.D0.R1.S10: RxDqsDelay = 031
N4.C0.D1.R1.S03: RdDqDqs FSM results: Left = 12, Right = 63, center = 37
N6.C1: SettingForTrainingStep: Programming 10 tick initial value to CTL signals
N0.C2.S08: DDRIOHSIODATA0_LATCTL1 = 08040804
N2.C1.D0.R1.S11: RdDqDqs FSM results: Left = 02, Right = 63, center = 32
N4.C0.D1.R1.S03: RxDqsDelay = 037
N6.C2: DDRIOHSIODATA0_LATCTL1 = 08040804
N0.C3: ODTTIMCTL (INIT RELAX) rdwidth = 10 rddly = 0 wrwidth = 8 wrdly = 0
N2.C1.D0.R1.S11: RxDqsDelay = 032
N4.C0.D1.R1.S04: RdDqDqs FSM results: Left = 14, Right = 63, center = 38
N6.C2: RdCmd2DataValidLatency = 20, (dlyFrmS = 15, clEff = 10, earlyCas = 0, selNTiming = 2)
N0.C3.S00: DDRIOHSIODATA0_LATCTL1 = 08040804
N2.C1.D0.R1.S12: RdDqDqs FSM results: Left = 06, Right = 59, center = 32
N4.C0.D1.R1.S04: RxDqsDelay = 038
N6.C2: SettingForTrainingStep: RdCmd2RcvEnLatency = 5
N0.C3.S01: DDRIOHSIODATA0_LATCTL1 = 08040804
N2.C1.D0.R1.S12: RxDqsDelay = 032
N4.C0.D1.R1.S05: RdDqDqs FSM results: Left = 14, Right = 63, center = 38
N6.C2: SettingForTrainingStep: Programming 7 tick initial value to CTL signals
N0.C3.S02: DDRIOHSIODATA0_LATCTL1 = 08040804
N2.C1.D0.R1.S13: RdDqDqs FSM results: Left = 04, Right = 61, center = 32
N4.C0.D1.R1.S05: RxDqsDelay = 038
N6.C3: DDRIOHSIODATA0_LATCTL1 = 08040804
N0.C3.S03: DDRIOHSIODATA0_LATCTL1 = 08040804
N2.C1.D0.R1.S13: RxDqsDelay = 032
N4.C0.D1.R1.S06: RdDqDqs FSM results: Left = 17, Right = 63, center = 40
N6.C3: RdCmd2DataValidLatency = 20, (dlyFrmS = 15, clEff = 10, earlyCas = 0, selNTiming = 2)
N0.C3.S04: DDRIOHSIODATA0_LATCTL1 = 08040804
N2.C1.D0.R1.S14: RdDqDqs FSM results: Left = 07, Right = 60, center = 33
N4.C0.D1.R1.S06: RxDqsDelay = 040
N6.C3: SettingForTrainingStep: RdCmd2RcvEnLatency = 5
N0.C3.S05: DDRIOHSIODATA0_LATCTL1 = 08040804
N2.C1.D0.R1.S14: RxDqsDelay = 033
N4.C0.D1.R1.S07: RdDqDqs FSM results: Left = 18, Right = 63, center = 40
N6.C3: SettingForTrainingStep: Programming 10 tick initial value to CTL signals
N0.C3.S06: DDRIOHSIODATA0_LATCTL1 = 08040804
N2.C1.D0.R1.S15: RdDqDqs FSM results: Left = 06, Right = 63, center = 34
N4.C0.D1.R1.S07: RxDqsDelay = 040
N6: FSM Basic Clock Training
N0.C3.S07: DDRIOHSIODATA0_LATCTL1 = 08040804
N2.C1.D0.R1.S15: RxDqsDelay = 034
N4.C0.D1.R1.S08: RdDqDqs FSM results: Left = 17, Right = 63, center = 40
N6.C0: JCK cmd timing = 1N
N0.C3.S08: DDRIOHSIODATA0_LATCTL1 = 08040804
N2.C1.D0.R1.S16: RdDqDqs FSM results: Left = 05, Right = 61, center = 33
N4.C0.D1.R1.S08: RxDqsDelay = 040
N6.C0: RdCmd2DataValidLatency = 21, (dlyFrmS = 15, clEff = 10, earlyCas = 0, selNTiming = 0)

START - Early Command Training
N2.C1.D0.R1.S16: RxDqsDelay = 033
N4.C0.D1.R1.S09: RdDqDqs FSM results: Left = 18, Right = 63, center = 40
N6.C1: RdCmd2DataValidLatency = 21, (dlyFrmS = 15, clEff = 10, earlyCas = 0, selNTiming = 0)
Checkpoint Code: Socket 0, 0xB7, 0x00, 0x0000
N2.C1.D0.R1.S17: RdDqDqs FSM results: Left = 02, Right = 54, center = 28
N4.C0.D1.R1.S09: RxDqsDelay = 040
N6.C2: JCK cmd timing = 1N
N0.C0: DDRIOHSIODATA0_LATCTL1 = 08040804
N2.C1.D0.R1.S17: RxDqsDelay = 028
N4.C0.D1.R1.S10: RdDqDqs FSM results: Left = 12, Right = 63, center = 37
N6.C2: RdCmd2DataValidLatency = 21, (dlyFrmS = 15, clEff = 10, earlyCas = 0, selNTiming = 0)
N0.C0: RdCmd2DataValidLatency = 20, (dlyFrmS = 15, clEff = 10, earlyCas = 0, selNTiming = 2)
N2.C1.D1.R0.S00: RdDqDqs FSM results: Left = 08, Right = 63, center = 35
N4.C0.D1.R1.S10: RxDqsDelay = 037
N6.C3: RdCmd2DataValidLatency = 21, (dlyFrmS = 15, clEff = 10, earlyCas = 0, selNTiming = 0)
N0.C0: SettingForTrainingStep: RdCmd2RcvEnLatency = 5
N2.C1.D1.R0.S00: RxDqsDelay = 035
N4.C0.D1.R1.S11: RdDqDqs FSM results: Left = 13, Right = 63, center = 38
N0.C0: SettingForTrainingStep: Programming 7 tick initial value to CTL signals
N2.C1.D1.R0.S01: RdDqDqs FSM results: Left = 09, Right = 63, center = 36
N4.C0.D1.R1.S11: RxDqsDelay = 038
N0.C1: DDRIOHSIODATA0_LATCTL1 = 08040804
N2.C1.D1.R0.S01: RxDqsDelay = 036
N4.C0.D1.R1.S12: RdDqDqs FSM results: Left = 15, Right = 63, center = 39
N0.C1: RdCmd2DataValidLatency = 20, (dlyFrmS = 15, clEff = 10, earlyCas = 0, selNTiming = 2)
N2.C1.D1.R0.S02: RdDqDqs FSM results: Left = 07, Right = 63, center = 35
N4.C0.D1.R1.S12: RxDqsDelay = 039
N0.C1: SettingForTrainingStep: RdCmd2RcvEnLatency = 5
N2.C1.D1.R0.S02: RxDqsDelay = 035
N4.C0.D1.R1.S13: RdDqDqs FSM results: Left = 12, Right = 63, center = 37
N0.C1: SettingForTrainingStep: Programming 10 tick initial value to CTL signals
N2.C1.D1.R0.S03: RdDqDqs FSM results: Left = 08, Right = 63, center = 35
N4.C0.D1.R1.S13: RxDqsDelay = 037
N0.C2: DDRIOHSIODATA0_LATCTL1 = 08040804
N2.C1.D1.R0.S03: RxDqsDelay = 035
N4.C0.D1.R1.S14: RdDqDqs FSM results: Left = 15, Right = 63, center = 39
N0.C2: RdCmd2DataValidLatency = 20, (dlyFrmS = 15, clEff = 10, earlyCas = 0, selNTiming = 2)
N2.C1.D1.R0.S04: RdDqDqs FSM results: Left = 10, Right = 63, center = 36
N4.C0.D1.R1.S14: RxDqsDelay = 039
N0.C2: SettingForTrainingStep: RdCmd2RcvEnLatency = 5
N2.C1.D1.R0.S04: RxDqsDelay = 036
N4.C0.D1.R1.S15: RdDqDqs FSM results: Left = 12, Right = 63, center = 37
N0.C2: SettingForTrainingStep: Programming 7 tick initial value to CTL signals
N2.C1.D1.R0.S05: RdDqDqs FSM results: Left = 07, Right = 63, center = 35
N4.C0.D1.R1.S15: RxDqsDelay = 037
N0.C3: DDRIOHSIODATA0_LATCTL1 = 08040804
N2.C1.D1.R0.S05: RxDqsDelay = 035
N4.C0.D1.R1.S16: RdDqDqs FSM results: Left = 15, Right = 63, center = 39
N0.C3: RdCmd2DataValidLatency = 20, (dlyFrmS = 15, clEff = 10, earlyCas = 0, selNTiming = 2)
N2.C1.D1.R0.S06: RdDqDqs FSM results: Left = 06, Right = 63, center = 34
N4.C0.D1.R1.S16: RxDqsDelay = 039
N0.C3: SettingForTrainingStep: RdCmd2RcvEnLatency = 5
N2.C1.D1.R0.S06: RxDqsDelay = 034
N4.C0.D1.R1.S17: RdDqDqs FSM results: Left = 14, Right = 63, center = 38
N0.C3: SettingForTrainingStep: Programming 10 tick initial value to CTL signals
N2.C1.D1.R0.S07: RdDqDqs FSM results: Left = 09, Right = 63, center = 36
N4.C0.D1.R1.S17: RxDqsDelay = 038
N0: FSM Basic Clock Training
N2.C1.D1.R0.S07: RxDqsDelay = 036
START_DATA_RX_DQS
N0.C0: JCK cmd timing = 1N
N2.C1.D1.R0.S08: RdDqDqs FSM results: Left = 06, Right = 63, center = 34
N4.C0.R0.S00: PI = 36
N0.C0: RdCmd2DataValidLatency = 21, (dlyFrmS = 15, clEff = 10, earlyCas = 0, selNTiming = 0)
N2.C1.D1.R0.S08: RxDqsDelay = 034
N4.C0.R0.S01: PI = 36
N0.C1: RdCmd2DataValidLatency = 21, (dlyFrmS = 15, clEff = 10, earlyCas = 0, selNTiming = 0)
N2.C1.D1.R0.S09: RdDqDqs FSM results: Left = 06, Right = 63, center = 34
N4.C0.R0.S02: PI = 38
N0.C2: JCK cmd timing = 1N
N2.C1.D1.R0.S09: RxDqsDelay = 034
N4.C0.R0.S03: PI = 37
N0.C2: RdCmd2DataValidLatency = 21, (dlyFrmS = 15, clEff = 10, earlyCas = 0, selNTiming = 0)
N2.C1.D1.R0.S10: RdDqDqs FSM results: Left = 07, Right = 63, center = 35
N4.C0.R0.S04: PI = 37
N0.C3: RdCmd2DataValidLatency = 21, (dlyFrmS = 15, clEff = 10, earlyCas = 0, selNTiming = 0)
N2.C1.D1.R0.S10: RxDqsDelay = 035
N4.C0.R0.S05: PI = 37
N2.C1.D1.R0.S11: RdDqDqs FSM results: Left = 04, Right = 63, center = 33
N4.C0.R0.S06: PI = 38
N2.C1.D1.R0.S11: RxDqsDelay = 033
N4.C0.R0.S07: PI = 38
N2.C1.D1.R0.S12: RdDqDqs FSM results: Left = 08, Right = 63, center = 35
N4.C0.R0.S08: PI = 37
N2.C1.D1.R0.S12: RxDqsDelay = 035
N4.C0.R0.S09: PI = 38
N2.C1.D1.R0.S13: RdDqDqs FSM results: Left = 06, Right = 63, center = 34
N4.C0.R0.S10: PI = 36
N2.C1.D1.R0.S13: RxDqsDelay = 034
N4.C0.R0.S11: PI = 37
N2.C1.D1.R0.S14: RdDqDqs FSM results: Left = 10, Right = 63, center = 36
N4.C0.R0.S12: PI = 37
N2.C1.D1.R0.S14: RxDqsDelay = 036
N4.C0.R0.S13: PI = 36
N2.C1.D1.R0.S15: RdDqDqs FSM results: Left = 09, Right = 63, center = 36
N4.C0.R0.S14: PI = 37
N2.C1.D1.R0.S15: RxDqsDelay = 036
N4.C0.R0.S15: PI = 36
N2.C1.D1.R0.S16: RdDqDqs FSM results: Left = 07, Right = 63, center = 35
N4.C0.R0.S16: PI = 36
N2.C1.D1.R0.S16: RxDqsDelay = 035
N4.C0.R0.S17: PI = 36
N2.C1.D1.R0.S17: RdDqDqs FSM results: Left = 04, Right = 58, center = 31
N4.C0.R0.S00: PI = 36
N2.C1.D1.R0.S17: RxDqsDelay = 031
N4.C0.R0.S01: PI = 36
N4.C0.R0.S02: PI = 38
N2.C1.D1.R1.S00: RdDqDqs FSM results: Left = 08, Right = 63, center = 35
N4.C0.R0.S03: PI = 37
N2.C1.D1.R1.S00: RxDqsDelay = 035
N4.C0.R0.S04: PI = 37
N2.C1.D1.R1.S01: RdDqDqs FSM results: Left = 10, Right = 63, center = 36
N4.C0.R0.S05: PI = 37
N2.C1.D1.R1.S01: RxDqsDelay = 036
N4.C0.R0.S06: PI = 38
N2.C1.D1.R1.S02: RdDqDqs FSM results: Left = 07, Right = 63, center = 35
N4.C0.R0.S07: PI = 38
N2.C1.D1.R1.S02: RxDqsDelay = 035
N4.C0.R0.S08: PI = 37
N2.C1.D1.R1.S03: RdDqDqs FSM results: Left = 08, Right = 63, center = 35
N4.C0.R0.S09: PI = 38
N2.C1.D1.R1.S03: RxDqsDelay = 035
N4.C0.R0.S10: PI = 36
N2.C1.D1.R1.S04: RdDqDqs FSM results: Left = 09, Right = 63, center = 36
N4.C0.R0.S11: PI = 37
N2.C1.D1.R1.S04: RxDqsDelay = 036
N4.C0.R0.S12: PI = 37
N2.C1.D1.R1.S05: RdDqDqs FSM results: Left = 07, Right = 63, center = 35
N4.C0.R0.S13: PI = 36
N2.C1.D1.R1.S05: RxDqsDelay = 035
N4.C0.R0.S14: PI = 37
N2.C1.D1.R1.S06: RdDqDqs FSM results: Left = 07, Right = 63, center = 35
N4.C0.R0.S15: PI = 36
N2.C1.D1.R1.S06: RxDqsDelay = 035
N4.C0.R0.S16: PI = 36
N2.C1.D1.R1.S07: RdDqDqs FSM results: Left = 09, Right = 63, center = 36
N4.C0.R0.S17: PI = 36
N2.C1.D1.R1.S07: RxDqsDelay = 036
N4.C0.R2.S00: PI = 37
N2.C1.D1.R1.S08: RdDqDqs FSM results: Left = 07, Right = 63, center = 35
N4.C0.R2.S01: PI = 38
N2.C1.D1.R1.S08: RxDqsDelay = 035
N4.C0.R2.S02: PI = 39
N2.C1.D1.R1.S09: RdDqDqs FSM results: Left = 07, Right = 63, center = 35
N4.C0.R2.S03: PI = 37
N2.C1.D1.R1.S09: RxDqsDelay = 035
N4.C0.R2.S04: PI = 38
N2.C1.D1.R1.S10: RdDqDqs FSM results: Left = 07, Right = 63, center = 35
N4.C0.R2.S05: PI = 38
N2.C1.D1.R1.S10: RxDqsDelay = 035
N4.C0.R2.S06: PI = 39
N2.C1.D1.R1.S11: RdDqDqs FSM results: Left = 05, Right = 63, center = 34
N4.C0.R2.S07: PI = 40
N2.C1.D1.R1.S11: RxDqsDelay = 034
N4.C0.R2.S08: PI = 40
N2.C1.D1.R1.S12: RdDqDqs FSM results: Left = 08, Right = 63, center = 35
N4.C0.R2.S09: PI = 40
N2.C1.D1.R1.S12: RxDqsDelay = 035
N4.C0.R2.S10: PI = 37
N2.C1.D1.R1.S13: RdDqDqs FSM results: Left = 08, Right = 63, center = 35
N4.C0.R2.S11: PI = 38
N2.C1.D1.R1.S13: RxDqsDelay = 035
N4.C0.R2.S12: PI = 39
N2.C1.D1.R1.S14: RdDqDqs FSM results: Left = 10, Right = 63, center = 36
N4.C0.R2.S13: PI = 37
N2.C1.D1.R1.S14: RxDqsDelay = 036
N4.C0.R2.S14: PI = 38
N2.C1.D1.R1.S15: RdDqDqs FSM results: Left = 09, Right = 63, center = 36
N4.C0.R2.S15: PI = 37
N2.C1.D1.R1.S15: RxDqsDelay = 036
N4.C0.R2.S16: PI = 39
N2.C1.D1.R1.S16: RdDqDqs FSM results: Left = 07, Right = 63, center = 35
N4.C0.R2.S17: PI = 38
N2.C1.D1.R1.S16: RxDqsDelay = 035
N4.C0.R2.S00: PI = 37
N2.C1.D1.R1.S17: RdDqDqs FSM results: Left = 04, Right = 58, center = 31
N4.C0.R2.S01: PI = 38
N2.C1.D1.R1.S17: RxDqsDelay = 031
N4.C0.R2.S02: PI = 39
N4.C0.R2.S03: PI = 37
START_DATA_RX_DQS
N4.C0.R2.S04: PI = 38
N2.C1.R0.S00: PI = 32
N4.C0.R2.S05: PI = 38
N2.C1.R0.S01: PI = 34
N4.C0.R2.S06: PI = 39
N2.C1.R0.S02: PI = 32
N4.C0.R2.S07: PI = 40
N2.C1.R0.S03: PI = 34
N4.C0.R2.S08: PI = 40
N2.C1.R0.S04: PI = 34
N4.C0.R2.S09: PI = 40
N2.C1.R0.S05: PI = 33
N4.C0.R2.S10: PI = 37
N2.C1.R0.S06: PI = 33
N4.C0.R2.S11: PI = 38
N2.C1.R0.S07: PI = 34
N4.C0.R2.S12: PI = 39
N2.C1.R0.S08: PI = 30
N4.C0.R2.S13: PI = 37
N2.C1.R0.S09: PI = 32
N4.C0.R2.S14: PI = 38
N2.C1.R0.S10: PI = 31
N4.C0.R2.S15: PI = 37
N2.C1.R0.S11: PI = 32
N4.C0.R2.S16: PI = 39
N2.C1.R0.S12: PI = 31
N4.C0.R2.S17: PI = 38
N2.C1.R0.S13: PI = 31
STOP_DATA_RX_DQS
N2.C1.R0.S14: PI = 34
N2.C1.R0.S15: PI = 34
N4.C1.D0.R0.S00: RdDqDqs FSM results: Left = 12, Right = 63, center = 37
N2.C1.R0.S16: PI = 33
N4.C1.D0.R0.S00: RxDqsDelay = 037
N2.C1.R0.S17: PI = 28
N4.C1.D0.R0.S01: RdDqDqs FSM results: Left = 12, Right = 63, center = 37
N2.C1.R0.S00: PI = 32
N4.C1.D0.R0.S01: RxDqsDelay = 037
N2.C1.R0.S01: PI = 34
N4.C1.D0.R0.S02: RdDqDqs FSM results: Left = 11, Right = 63, center = 37
N2.C1.R0.S02: PI = 32
N4.C1.D0.R0.S02: RxDqsDelay = 037
N2.C1.R0.S03: PI = 34
N4.C1.D0.R0.S03: RdDqDqs FSM results: Left = 12, Right = 63, center = 37
N2.C1.R0.S04: PI = 34
N4.C1.D0.R0.S03: RxDqsDelay = 037
N2.C1.R0.S05: PI = 33
N4.C1.D0.R0.S04: RdDqDqs FSM results: Left = 14, Right = 63, center = 38
N2.C1.R0.S06: PI = 33
N4.C1.D0.R0.S04: RxDqsDelay = 038
N2.C1.R0.S07: PI = 34
N4.C1.D0.R0.S05: RdDqDqs FSM results: Left = 11, Right = 61, center = 36
N2.C1.R0.S08: PI = 30
N4.C1.D0.R0.S05: RxDqsDelay = 036
N2.C1.R0.S09: PI = 32
N4.C1.D0.R0.S06: RdDqDqs FSM results: Left = 16, Right = 63, center = 39
N2.C1.R0.S10: PI = 31
N4.C1.D0.R0.S06: RxDqsDelay = 039
N2.C1.R0.S11: PI = 32
N4.C1.D0.R0.S07: RdDqDqs FSM results: Left = 17, Right = 63, center = 40
N2.C1.R0.S12: PI = 31
N4.C1.D0.R0.S07: RxDqsDelay = 040
N2.C1.R0.S13: PI = 31
N4.C1.D0.R0.S08: RdDqDqs FSM results: Left = 13, Right = 63, center = 38
N2.C1.R0.S14: PI = 34
N4.C1.D0.R0.S08: RxDqsDelay = 038
N2.C1.R0.S15: PI = 34
N4.C1.D0.R0.S09: RdDqDqs FSM results: Left = 10, Right = 63, center = 36
N2.C1.R0.S16: PI = 33
N4.C1.D0.R0.S09: RxDqsDelay = 036
N2.C1.R0.S17: PI = 28
N4.C1.D0.R0.S10: RdDqDqs FSM results: Left = 09, Right = 63, center = 36
N2.C1.R2.S00: PI = 35
N4.C1.D0.R0.S10: RxDqsDelay = 036
N2.C1.R2.S01: PI = 36
N4.C1.D0.R0.S11: RdDqDqs FSM results: Left = 06, Right = 63, center = 34
N2.C1.R2.S02: PI = 35
N4.C1.D0.R0.S11: RxDqsDelay = 034
N2.C1.R2.S03: PI = 35
N4.C1.D0.R0.S12: RdDqDqs FSM results: Left = 10, Right = 63, center = 36
N2.C1.R2.S04: PI = 36
N4.C1.D0.R0.S12: RxDqsDelay = 036
N2.C1.R2.S05: PI = 35
N4.C1.D0.R0.S13: RdDqDqs FSM results: Left = 12, Right = 63, center = 37
N2.C1.R2.S06: PI = 34
N4.C1.D0.R0.S13: RxDqsDelay = 037
N2.C1.R2.S07: PI = 36
N4.C1.D0.R0.S14: RdDqDqs FSM results: Left = 09, Right = 61, center = 35
N2.C1.R2.S08: PI = 34
N4.C1.D0.R0.S14: RxDqsDelay = 035
N2.C1.R2.S09: PI = 34
N4.C1.D0.R0.S15: RdDqDqs FSM results: Left = 16, Right = 63, center = 39
N2.C1.R2.S10: PI = 35
N4.C1.D0.R0.S15: RxDqsDelay = 039
N2.C1.R2.S11: PI = 33
N4.C1.D0.R0.S16: RdDqDqs FSM results: Left = 11, Right = 63, center = 37
N2.C1.R2.S12: PI = 35
N4.C1.D0.R0.S16: RxDqsDelay = 037
N2.C1.R2.S13: PI = 34
N4.C1.D0.R0.S17: RdDqDqs FSM results: Left = 13, Right = 63, center = 38
N2.C1.R2.S14: PI = 36
N4.C1.D0.R0.S17: RxDqsDelay = 038
N2.C1.R2.S15: PI = 36
N2.C1.R2.S16: PI = 35
N4.C1.D0.R1.S00: RdDqDqs FSM results: Left = 11, Right = 63, center = 37
N2.C1.R2.S17: PI = 31
N4.C1.D0.R1.S00: RxDqsDelay = 037
N2.C1.R2.S00: PI = 35
N4.C1.D0.R1.S01: RdDqDqs FSM results: Left = 11, Right = 63, center = 37
N2.C1.R2.S01: PI = 36
N4.C1.D0.R1.S01: RxDqsDelay = 037
N2.C1.R2.S02: PI = 35
N4.C1.D0.R1.S02: RdDqDqs FSM results: Left = 12, Right = 63, center = 37
N2.C1.R2.S03: PI = 35
N4.C1.D0.R1.S02: RxDqsDelay = 037
N2.C1.R2.S04: PI = 36
N4.C1.D0.R1.S03: RdDqDqs FSM results: Left = 12, Right = 63, center = 37
N2.C1.R2.S05: PI = 35
N4.C1.D0.R1.S03: RxDqsDelay = 037
N2.C1.R2.S06: PI = 34
N4.C1.D0.R1.S04: RdDqDqs FSM results: Left = 12, Right = 63, center = 37
N2.C1.R2.S07: PI = 36
N4.C1.D0.R1.S04: RxDqsDelay = 037
N2.C1.R2.S08: PI = 34
N4.C1.D0.R1.S05: RdDqDqs FSM results: Left = 12, Right = 60, center = 36
N2.C1.R2.S09: PI = 34
N4.C1.D0.R1.S05: RxDqsDelay = 036
N2.C1.R2.S10: PI = 35
N4.C1.D0.R1.S06: RdDqDqs FSM results: Left = 16, Right = 63, center = 39
N2.C1.R2.S11: PI = 33
N4.C1.D0.R1.S06: RxDqsDelay = 039
N2.C1.R2.S12: PI = 35
N4.C1.D0.R1.S07: RdDqDqs FSM results: Left = 15, Right = 63, center = 39
N2.C1.R2.S13: PI = 34
N4.C1.D0.R1.S07: RxDqsDelay = 039
N2.C1.R2.S14: PI = 36
N4.C1.D0.R1.S08: RdDqDqs FSM results: Left = 13, Right = 63, center = 38
N2.C1.R2.S15: PI = 36
N4.C1.D0.R1.S08: RxDqsDelay = 038
N2.C1.R2.S16: PI = 35
N4.C1.D0.R1.S09: RdDqDqs FSM results: Left = 11, Right = 63, center = 37
N2.C1.R2.S17: PI = 31
N4.C1.D0.R1.S09: RxDqsDelay = 037
STOP_DATA_RX_DQS
N4.C1.D0.R1.S10: RdDqDqs FSM results: Left = 08, Right = 63, center = 35
N2.C2.D0.R0.S00: RdDqDqs FSM results: Left = 04, Right = 63, center = 33
N4.C1.D0.R1.S10: RxDqsDelay = 035
N2.C2.D0.R0.S00: RxDqsDelay = 033
N4.C1.D0.R1.S11: RdDqDqs FSM results: Left = 08, Right = 63, center = 35
N2.C2.D0.R0.S01: RdDqDqs FSM results: Left = 05, Right = 63, center = 34
N4.C1.D0.R1.S11: RxDqsDelay = 035
N2.C2.D0.R0.S01: RxDqsDelay = 034
N4.C1.D0.R1.S12: RdDqDqs FSM results: Left = 10, Right = 63, center = 36
N2.C2.D0.R0.S02: RdDqDqs FSM results: Left = 07, Right = 63, center = 35
N4.C1.D0.R1.S12: RxDqsDelay = 036
N2.C2.D0.R0.S02: RxDqsDelay = 035
N4.C1.D0.R1.S13: RdDqDqs FSM results: Left = 12, Right = 63, center = 37
N2.C2.D0.R0.S03: RdDqDqs FSM results: Left = 06, Right = 63, center = 34
N4.C1.D0.R1.S13: RxDqsDelay = 037
N2.C2.D0.R0.S03: RxDqsDelay = 034
N4.C1.D0.R1.S14: RdDqDqs FSM results: Left = 08, Right = 58, center = 33
N2.C2.D0.R0.S04: RdDqDqs FSM results: Left = 04, Right = 63, center = 33
N4.C1.D0.R1.S14: RxDqsDelay = 033
N2.C2.D0.R0.S04: RxDqsDelay = 033
N4.C1.D0.R1.S15: RdDqDqs FSM results: Left = 14, Right = 63, center = 38
N2.C2.D0.R0.S05: RdDqDqs FSM results: Left = 09, Right = 63, center = 36
N4.C1.D0.R1.S15: RxDqsDelay = 038
N2.C2.D0.R0.S05: RxDqsDelay = 036
N4.C1.D0.R1.S16: RdDqDqs FSM results: Left = 10, Right = 63, center = 36
N2.C2.D0.R0.S06: RdDqDqs FSM results: Left = 05, Right = 63, center = 34
N4.C1.D0.R1.S16: RxDqsDelay = 036
N2.C2.D0.R0.S06: RxDqsDelay = 034
N4.C1.D0.R1.S17: RdDqDqs FSM results: Left = 13, Right = 63, center = 38
N2.C2.D0.R0.S07: RdDqDqs FSM results: Left = 12, Right = 63, center = 37
N4.C1.D0.R1.S17: RxDqsDelay = 038
N2.C2.D0.R0.S07: RxDqsDelay = 037
N4.C1.D1.R0.S00: RdDqDqs FSM results: Left = 15, Right = 63, center = 39
N2.C2.D0.R0.S08: RdDqDqs FSM results: Left = 07, Right = 63, center = 35
N4.C1.D1.R0.S00: RxDqsDelay = 039
N2.C2.D0.R0.S08: RxDqsDelay = 035
N4.C1.D1.R0.S01: RdDqDqs FSM results: Left = 16, Right = 63, center = 39
N2.C2.D0.R0.S09: RdDqDqs FSM results: Left = 07, Right = 63, center = 35
N4.C1.D1.R0.S01: RxDqsDelay = 039
N2.C2.D0.R0.S09: RxDqsDelay = 035
N4.C1.D1.R0.S02: RdDqDqs FSM results: Left = 17, Right = 63, center = 40
N2.C2.D0.R0.S10: RdDqDqs FSM results: Left = 07, Right = 60, center = 33
N4.C1.D1.R0.S02: RxDqsDelay = 040
N2.C2.D0.R0.S10: RxDqsDelay = 033
N4.C1.D1.R0.S03: RdDqDqs FSM results: Left = 17, Right = 63, center = 40
N2.C2.D0.R0.S11: RdDqDqs FSM results: Left = 09, Right = 63, center = 36
N4.C1.D1.R0.S03: RxDqsDelay = 040
N2.C2.D0.R0.S11: RxDqsDelay = 036
N4.C1.D1.R0.S04: RdDqDqs FSM results: Left = 18, Right = 63, center = 40
N2.C2.D0.R0.S12: RdDqDqs FSM results: Left = 07, Right = 63, center = 35
N4.C1.D1.R0.S04: RxDqsDelay = 040
N2.C2.D0.R0.S12: RxDqsDelay = 035
N4.C1.D1.R0.S05: RdDqDqs FSM results: Left = 16, Right = 63, center = 39
N2.C2.D0.R0.S13: RdDqDqs FSM results: Left = 03, Right = 63, center = 33
N4.C1.D1.R0.S05: RxDqsDelay = 039
N2.C2.D0.R0.S13: RxDqsDelay = 033
N4.C1.D1.R0.S06: RdDqDqs FSM results: Left = 19, Right = 63, center = 41
N2.C2.D0.R0.S14: RdDqDqs FSM results: Left = 09, Right = 63, center = 36
N4.C1.D1.R0.S06: RxDqsDelay = 041
N2.C2.D0.R0.S14: RxDqsDelay = 036
N4.C1.D1.R0.S07: RdDqDqs FSM results: Left = 19, Right = 63, center = 41
N2.C2.D0.R0.S15: RdDqDqs FSM results: Left = 10, Right = 63, center = 36
N4.C1.D1.R0.S07: RxDqsDelay = 041
N2.C2.D0.R0.S15: RxDqsDelay = 036
N4.C1.D1.R0.S08: RdDqDqs FSM results: Left = 17, Right = 63, center = 40
N2.C2.D0.R0.S16: RdDqDqs FSM results: Left = 09, Right = 63, center = 36
N4.C1.D1.R0.S08: RxDqsDelay = 040
N2.C2.D0.R0.S16: RxDqsDelay = 036
N4.C1.D1.R0.S09: RdDqDqs FSM results: Left = 13, Right = 63, center = 38
N2.C2.D0.R0.S17: RdDqDqs FSM results: Left = 09, Right = 63, center = 36
N4.C1.D1.R0.S09: RxDqsDelay = 038
N2.C2.D0.R0.S17: RxDqsDelay = 036
N4.C1.D1.R0.S10: RdDqDqs FSM results: Left = 13, Right = 63, center = 38
N2.C2.D0.R1.S00: RdDqDqs FSM results: Left = 04, Right = 63, center = 33
N4.C1.D1.R0.S10: RxDqsDelay = 038
N2.C2.D0.R1.S00: RxDqsDelay = 033
N4.C1.D1.R0.S11: RdDqDqs FSM results: Left = 09, Right = 63, center = 36
N2.C2.D0.R1.S01: RdDqDqs FSM results: Left = 05, Right = 63, center = 34
N4.C1.D1.R0.S11: RxDqsDelay = 036
N2.C2.D0.R1.S01: RxDqsDelay = 034
N4.C1.D1.R0.S12: RdDqDqs FSM results: Left = 15, Right = 63, center = 39
N2.C2.D0.R1.S02: RdDqDqs FSM results: Left = 08, Right = 63, center = 35
N4.C1.D1.R0.S12: RxDqsDelay = 039
N2.C2.D0.R1.S02: RxDqsDelay = 035
N4.C1.D1.R0.S13: RdDqDqs FSM results: Left = 18, Right = 63, center = 40
N2.C2.D0.R1.S03: RdDqDqs FSM results: Left = 06, Right = 63, center = 34
N4.C1.D1.R0.S13: RxDqsDelay = 040
N2.C2.D0.R1.S03: RxDqsDelay = 034
N4.C1.D1.R0.S14: RdDqDqs FSM results: Left = 12, Right = 61, center = 36
N2.C2.D0.R1.S04: RdDqDqs FSM results: Left = 03, Right = 63, center = 33
N4.C1.D1.R0.S14: RxDqsDelay = 036
N2.C2.D0.R1.S04: RxDqsDelay = 033
N4.C1.D1.R0.S15: RdDqDqs FSM results: Left = 18, Right = 63, center = 40
N2.C2.D0.R1.S05: RdDqDqs FSM results: Left = 09, Right = 63, center = 36
N4.C1.D1.R0.S15: RxDqsDelay = 040
N2.C2.D0.R1.S05: RxDqsDelay = 036
N4.C1.D1.R0.S16: RdDqDqs FSM results: Left = 15, Right = 63, center = 39
N2.C2.D0.R1.S06: RdDqDqs FSM results: Left = 04, Right = 63, center = 33
N4.C1.D1.R0.S16: RxDqsDelay = 039
N2.C2.D0.R1.S06: RxDqsDelay = 033
N4.C1.D1.R0.S17: RdDqDqs FSM results: Left = 17, Right = 63, center = 40
N2.C2.D0.R1.S07: RdDqDqs FSM results: Left = 11, Right = 63, center = 37
N4.C1.D1.R0.S17: RxDqsDelay = 040
N2.C2.D0.R1.S07: RxDqsDelay = 037
N4.C1.D1.R1.S00: RdDqDqs FSM results: Left = 15, Right = 63, center = 39
N2.C2.D0.R1.S08: RdDqDqs FSM results: Left = 07, Right = 63, center = 35
N4.C1.D1.R1.S00: RxDqsDelay = 039
N2.C2.D0.R1.S08: RxDqsDelay = 035
N4.C1.D1.R1.S01: RdDqDqs FSM results: Left = 15, Right = 63, center = 39
N2.C2.D0.R1.S09: RdDqDqs FSM results: Left = 07, Right = 63, center = 35
N4.C1.D1.R1.S01: RxDqsDelay = 039
N2.C2.D0.R1.S09: RxDqsDelay = 035
N4.C1.D1.R1.S02: RdDqDqs FSM results: Left = 16, Right = 63, center = 39
N2.C2.D0.R1.S10: RdDqDqs FSM results: Left = 07, Right = 63, center = 35
N4.C1.D1.R1.S02: RxDqsDelay = 039
N2.C2.D0.R1.S10: RxDqsDelay = 035
N4.C1.D1.R1.S03: RdDqDqs FSM results: Left = 16, Right = 63, center = 39
N2.C2.D0.R1.S11: RdDqDqs FSM results: Left = 09, Right = 63, center = 36
N4.C1.D1.R1.S03: RxDqsDelay = 039
N2.C2.D0.R1.S11: RxDqsDelay = 036
N4.C1.D1.R1.S04: RdDqDqs FSM results: Left = 19, Right = 63, center = 41
N2.C2.D0.R1.S12: RdDqDqs FSM results: Left = 08, Right = 63, center = 35
N4.C1.D1.R1.S04: RxDqsDelay = 041
N2.C2.D0.R1.S12: RxDqsDelay = 035
N4.C1.D1.R1.S05: RdDqDqs FSM results: Left = 16, Right = 63, center = 39
N2.C2.D0.R1.S13: RdDqDqs FSM results: Left = 03, Right = 63, center = 33
N4.C1.D1.R1.S05: RxDqsDelay = 039
N2.C2.D0.R1.S13: RxDqsDelay = 033
N4.C1.D1.R1.S06: RdDqDqs FSM results: Left = 19, Right = 63, center = 41
N2.C2.D0.R1.S14: RdDqDqs FSM results: Left = 09, Right = 63, center = 36
N4.C1.D1.R1.S06: RxDqsDelay = 041
N2.C2.D0.R1.S14: RxDqsDelay = 036
N4.C1.D1.R1.S07: RdDqDqs FSM results: Left = 19, Right = 63, center = 41
N2.C2.D0.R1.S15: RdDqDqs FSM results: Left = 09, Right = 63, center = 36
N4.C1.D1.R1.S07: RxDqsDelay = 041
N2.C2.D0.R1.S15: RxDqsDelay = 036
N4.C1.D1.R1.S08: RdDqDqs FSM results: Left = 17, Right = 63, center = 40
N2.C2.D0.R1.S16: RdDqDqs FSM results: Left = 09, Right = 63, center = 36
N4.C1.D1.R1.S08: RxDqsDelay = 040
N2.C2.D0.R1.S16: RxDqsDelay = 036
N4.C1.D1.R1.S09: RdDqDqs FSM results: Left = 13, Right = 63, center = 38
N2.C2.D0.R1.S17: RdDqDqs FSM results: Left = 08, Right = 63, center = 35
N4.C1.D1.R1.S09: RxDqsDelay = 038
N2.C2.D0.R1.S17: RxDqsDelay = 035
N4.C1.D1.R1.S10: RdDqDqs FSM results: Left = 13, Right = 63, center = 38
N2.C2.D1.R0.S00: RdDqDqs FSM results: Left = 08, Right = 63, center = 35
N4.C1.D1.R1.S10: RxDqsDelay = 038
N2.C2.D1.R0.S00: RxDqsDelay = 035
N4.C1.D1.R1.S11: RdDqDqs FSM results: Left = 09, Right = 63, center = 36
N2.C2.D1.R0.S01: RdDqDqs FSM results: Left = 09, Right = 63, center = 36
N4.C1.D1.R1.S11: RxDqsDelay = 036
N2.C2.D1.R0.S01: RxDqsDelay = 036
N4.C1.D1.R1.S12: RdDqDqs FSM results: Left = 16, Right = 63, center = 39
N2.C2.D1.R0.S02: RdDqDqs FSM results: Left = 12, Right = 63, center = 37
N4.C1.D1.R1.S12: RxDqsDelay = 039
N2.C2.D1.R0.S02: RxDqsDelay = 037
N4.C1.D1.R1.S13: RdDqDqs FSM results: Left = 17, Right = 63, center = 40
N2.C2.D1.R0.S03: RdDqDqs FSM results: Left = 09, Right = 63, center = 36
N4.C1.D1.R1.S13: RxDqsDelay = 040
N2.C2.D1.R0.S03: RxDqsDelay = 036
N4.C1.D1.R1.S14: RdDqDqs FSM results: Left = 12, Right = 63, center = 37
N2.C2.D1.R0.S04: RdDqDqs FSM results: Left = 10, Right = 63, center = 36
N4.C1.D1.R1.S14: RxDqsDelay = 037
N2.C2.D1.R0.S04: RxDqsDelay = 036
N4.C1.D1.R1.S15: RdDqDqs FSM results: Left = 18, Right = 63, center = 40
N2.C2.D1.R0.S05: RdDqDqs FSM results: Left = 10, Right = 63, center = 36
N4.C1.D1.R1.S15: RxDqsDelay = 040
N2.C2.D1.R0.S05: RxDqsDelay = 036
N4.C1.D1.R1.S16: RdDqDqs FSM results: Left = 14, Right = 63, center = 38
N2.C2.D1.R0.S06: RdDqDqs FSM results: Left = 08, Right = 63, center = 35
N4.C1.D1.R1.S16: RxDqsDelay = 038
N2.C2.D1.R0.S06: RxDqsDelay = 035
N4.C1.D1.R1.S17: RdDqDqs FSM results: Left = 18, Right = 63, center = 40
N2.C2.D1.R0.S07: RdDqDqs FSM results: Left = 15, Right = 63, center = 39
N4.C1.D1.R1.S17: RxDqsDelay = 040
N2.C2.D1.R0.S07: RxDqsDelay = 039
START_DATA_RX_DQS
N2.C2.D1.R0.S08: RdDqDqs FSM results: Left = 10, Right = 63, center = 36
N4.C1.R0.S00: PI = 37
N2.C2.D1.R0.S08: RxDqsDelay = 036
N4.C1.R0.S01: PI = 37
N2.C2.D1.R0.S09: RdDqDqs FSM results: Left = 11, Right = 63, center = 37
N4.C1.R0.S02: PI = 37
N2.C2.D1.R0.S09: RxDqsDelay = 037
N4.C1.R0.S03: PI = 37
N2.C2.D1.R0.S10: RdDqDqs FSM results: Left = 10, Right = 63, center = 36
N4.C1.R0.S04: PI = 37
N2.C2.D1.R0.S10: RxDqsDelay = 036
N4.C1.R0.S05: PI = 36
N2.C2.D1.R0.S11: RdDqDqs FSM results: Left = 11, Right = 63, center = 37
N4.C1.R0.S06: PI = 39
N2.C2.D1.R0.S11: RxDqsDelay = 037
N4.C1.R0.S07: PI = 39
N2.C2.D1.R0.S12: RdDqDqs FSM results: Left = 10, Right = 63, center = 36
N4.C1.R0.S08: PI = 38
N2.C2.D1.R0.S12: RxDqsDelay = 036
N4.C1.R0.S09: PI = 36
N2.C2.D1.R0.S13: RdDqDqs FSM results: Left = 06, Right = 63, center = 34
N4.C1.R0.S10: PI = 35
N2.C2.D1.R0.S13: RxDqsDelay = 034
N4.C1.R0.S11: PI = 34
N2.C2.D1.R0.S14: RdDqDqs FSM results: Left = 11, Right = 63, center = 37
N4.C1.R0.S12: PI = 36
N2.C2.D1.R0.S14: RxDqsDelay = 037
N4.C1.R0.S13: PI = 37
N2.C2.D1.R0.S15: RdDqDqs FSM results: Left = 14, Right = 63, center = 38
N4.C1.R0.S14: PI = 34
N2.C2.D1.R0.S15: RxDqsDelay = 038
N4.C1.R0.S15: PI = 38
N2.C2.D1.R0.S16: RdDqDqs FSM results: Left = 12, Right = 63, center = 37
N4.C1.R0.S16: PI = 36
N2.C2.D1.R0.S16: RxDqsDelay = 037
N4.C1.R0.S17: PI = 38
N2.C2.D1.R0.S17: RdDqDqs FSM results: Left = 12, Right = 63, center = 37
N4.C1.R0.S00: PI = 37
N2.C2.D1.R0.S17: RxDqsDelay = 037
N4.C1.R0.S01: PI = 37
N4.C1.R0.S02: PI = 37
N2.C2.D1.R1.S00: RdDqDqs FSM results: Left = 08, Right = 63, center = 35
N4.C1.R0.S03: PI = 37
N2.C2.D1.R1.S00: RxDqsDelay = 035
N4.C1.R0.S04: PI = 37
N2.C2.D1.R1.S01: RdDqDqs FSM results: Left = 08, Right = 63, center = 35
N4.C1.R0.S05: PI = 36
N2.C2.D1.R1.S01: RxDqsDelay = 035
N4.C1.R0.S06: PI = 39
N2.C2.D1.R1.S02: RdDqDqs FSM results: Left = 11, Right = 63, center = 37
N4.C1.R0.S07: PI = 39
N2.C2.D1.R1.S02: RxDqsDelay = 037
N4.C1.R0.S08: PI = 38
N2.C2.D1.R1.S03: RdDqDqs FSM results: Left = 09, Right = 63, center = 36
N4.C1.R0.S09: PI = 36
N2.C2.D1.R1.S03: RxDqsDelay = 036
N4.C1.R0.S10: PI = 35
N2.C2.D1.R1.S04: RdDqDqs FSM results: Left = 09, Right = 63, center = 36
N4.C1.R0.S11: PI = 34
N2.C2.D1.R1.S04: RxDqsDelay = 036
N4.C1.R0.S12: PI = 36
N2.C2.D1.R1.S05: RdDqDqs FSM results: Left = 10, Right = 63, center = 36
N4.C1.R0.S13: PI = 37
N2.C2.D1.R1.S05: RxDqsDelay = 036
N4.C1.R0.S14: PI = 34
N2.C2.D1.R1.S06: RdDqDqs FSM results: Left = 08, Right = 63, center = 35
N4.C1.R0.S15: PI = 38
N2.C2.D1.R1.S06: RxDqsDelay = 035
N4.C1.R0.S16: PI = 36
N2.C2.D1.R1.S07: RdDqDqs FSM results: Left = 15, Right = 63, center = 39
N4.C1.R0.S17: PI = 38
N2.C2.D1.R1.S07: RxDqsDelay = 039
N4.C1.R2.S00: PI = 39
N2.C2.D1.R1.S08: RdDqDqs FSM results: Left = 10, Right = 63, center = 36
N4.C1.R2.S01: PI = 39
N2.C2.D1.R1.S08: RxDqsDelay = 036
N4.C1.R2.S02: PI = 39
N2.C2.D1.R1.S09: RdDqDqs FSM results: Left = 11, Right = 63, center = 37
N4.C1.R2.S03: PI = 39
N2.C2.D1.R1.S09: RxDqsDelay = 037
N4.C1.R2.S04: PI = 40
N2.C2.D1.R1.S10: RdDqDqs FSM results: Left = 10, Right = 63, center = 36
N4.C1.R2.S05: PI = 39
N2.C2.D1.R1.S10: RxDqsDelay = 036
N4.C1.R2.S06: PI = 41
N2.C2.D1.R1.S11: RdDqDqs FSM results: Left = 11, Right = 63, center = 37
N4.C1.R2.S07: PI = 41
N2.C2.D1.R1.S11: RxDqsDelay = 037
N4.C1.R2.S08: PI = 40
N2.C2.D1.R1.S12: RdDqDqs FSM results: Left = 10, Right = 63, center = 36
N4.C1.R2.S09: PI = 38
N2.C2.D1.R1.S12: RxDqsDelay = 036
N4.C1.R2.S10: PI = 38
N2.C2.D1.R1.S13: RdDqDqs FSM results: Left = 07, Right = 63, center = 35
N4.C1.R2.S11: PI = 36
N2.C2.D1.R1.S13: RxDqsDelay = 035
N4.C1.R2.S12: PI = 39
N2.C2.D1.R1.S14: RdDqDqs FSM results: Left = 11, Right = 63, center = 37
N4.C1.R2.S13: PI = 40
N2.C2.D1.R1.S14: RxDqsDelay = 037
N4.C1.R2.S14: PI = 36
N2.C2.D1.R1.S15: RdDqDqs FSM results: Left = 13, Right = 63, center = 38
N4.C1.R2.S15: PI = 40
N2.C2.D1.R1.S15: RxDqsDelay = 038
N4.C1.R2.S16: PI = 38
N2.C2.D1.R1.S16: RdDqDqs FSM results: Left = 12, Right = 63, center = 37
N4.C1.R2.S17: PI = 40
N2.C2.D1.R1.S16: RxDqsDelay = 037
N4.C1.R2.S00: PI = 39
N2.C2.D1.R1.S17: RdDqDqs FSM results: Left = 11, Right = 63, center = 37
N4.C1.R2.S01: PI = 39
N2.C2.D1.R1.S17: RxDqsDelay = 037
N4.C1.R2.S02: PI = 39
N4.C1.R2.S03: PI = 39
START_DATA_RX_DQS
N4.C1.R2.S04: PI = 40
N2.C2.R0.S00: PI = 33
N4.C1.R2.S05: PI = 39
N2.C2.R0.S01: PI = 34
N4.C1.R2.S06: PI = 41
N2.C2.R0.S02: PI = 35
N4.C1.R2.S07: PI = 41
N2.C2.R0.S03: PI = 34
N4.C1.R2.S08: PI = 40
N2.C2.R0.S04: PI = 33
N4.C1.R2.S09: PI = 38
N2.C2.R0.S05: PI = 36
N4.C1.R2.S10: PI = 38
N2.C2.R0.S06: PI = 33
N4.C1.R2.S11: PI = 36
N2.C2.R0.S07: PI = 37
N4.C1.R2.S12: PI = 39
N2.C2.R0.S08: PI = 35
N4.C1.R2.S13: PI = 40
N2.C2.R0.S09: PI = 35
N4.C1.R2.S14: PI = 36
N2.C2.R0.S10: PI = 34
N4.C1.R2.S15: PI = 40
N2.C2.R0.S11: PI = 36
N4.C1.R2.S16: PI = 38
N2.C2.R0.S12: PI = 35
N4.C1.R2.S17: PI = 40
N2.C2.R0.S13: PI = 33
STOP_DATA_RX_DQS
N2.C2.R0.S14: PI = 36
N2.C2.R0.S15: PI = 36
N4.C2.D0.R0.S00: RdDqDqs FSM results: Left = 09, Right = 63, center = 36
N2.C2.R0.S16: PI = 36
N4.C2.D0.R0.S00: RxDqsDelay = 036
N2.C2.R0.S17: PI = 35
N4.C2.D0.R0.S01: RdDqDqs FSM results: Left = 12, Right = 63, center = 37
N2.C2.R0.S00: PI = 33
N4.C2.D0.R0.S01: RxDqsDelay = 037
N2.C2.R0.S01: PI = 34
N4.C2.D0.R0.S02: RdDqDqs FSM results: Left = 10, Right = 63, center = 36
N2.C2.R0.S02: PI = 35
N4.C2.D0.R0.S02: RxDqsDelay = 036
N2.C2.R0.S03: PI = 34
N4.C2.D0.R0.S03: RdDqDqs FSM results: Left = 08, Right = 63, center = 35
N2.C2.R0.S04: PI = 33
N4.C2.D0.R0.S03: RxDqsDelay = 035
N2.C2.R0.S05: PI = 36
N4.C2.D0.R0.S04: RdDqDqs FSM results: Left = 10, Right = 63, center = 36
N2.C2.R0.S06: PI = 33
N4.C2.D0.R0.S04: RxDqsDelay = 036
N2.C2.R0.S07: PI = 37
N4.C2.D0.R0.S05: RdDqDqs FSM results: Left = 12, Right = 63, center = 37
N2.C2.R0.S08: PI = 35
N4.C2.D0.R0.S05: RxDqsDelay = 037
N2.C2.R0.S09: PI = 35
N4.C2.D0.R0.S06: RdDqDqs FSM results: Left = 13, Right = 63, center = 38
N2.C2.R0.S10: PI = 34
N4.C2.D0.R0.S06: RxDqsDelay = 038
N2.C2.R0.S11: PI = 36
N4.C2.D0.R0.S07: RdDqDqs FSM results: Left = 12, Right = 63, center = 37
N2.C2.R0.S12: PI = 35
N4.C2.D0.R0.S07: RxDqsDelay = 037
N2.C2.R0.S13: PI = 33
N4.C2.D0.R0.S08: RdDqDqs FSM results: Left = 13, Right = 63, center = 38
N2.C2.R0.S14: PI = 36
N4.C2.D0.R0.S08: RxDqsDelay = 038
N2.C2.R0.S15: PI = 36
N4.C2.D0.R0.S09: RdDqDqs FSM results: Left = 09, Right = 63, center = 36
N2.C2.R0.S16: PI = 36
N4.C2.D0.R0.S09: RxDqsDelay = 036
N2.C2.R0.S17: PI = 35
N4.C2.D0.R0.S10: RdDqDqs FSM results: Left = 15, Right = 63, center = 39
N2.C2.R2.S00: PI = 35
N4.C2.D0.R0.S10: RxDqsDelay = 039
N2.C2.R2.S01: PI = 35
N4.C2.D0.R0.S11: RdDqDqs FSM results: Left = 05, Right = 63, center = 34
N2.C2.R2.S02: PI = 37
N4.C2.D0.R0.S11: RxDqsDelay = 034
N2.C2.R2.S03: PI = 36
N4.C2.D0.R0.S12: RdDqDqs FSM results: Left = 10, Right = 63, center = 36
N2.C2.R2.S04: PI = 36
N4.C2.D0.R0.S12: RxDqsDelay = 036
N2.C2.R2.S05: PI = 36
N4.C2.D0.R0.S13: RdDqDqs FSM results: Left = 06, Right = 61, center = 33
N2.C2.R2.S06: PI = 35
N4.C2.D0.R0.S13: RxDqsDelay = 033
N2.C2.R2.S07: PI = 39
N4.C2.D0.R0.S14: RdDqDqs FSM results: Left = 15, Right = 63, center = 39
N2.C2.R2.S08: PI = 36
N4.C2.D0.R0.S14: RxDqsDelay = 039
N2.C2.R2.S09: PI = 37
N4.C2.D0.R0.S15: RdDqDqs FSM results: Left = 11, Right = 63, center = 37
N2.C2.R2.S10: PI = 36
N4.C2.D0.R0.S15: RxDqsDelay = 037
N2.C2.R2.S11: PI = 37
N4.C2.D0.R0.S16: RdDqDqs FSM results: Left = 08, Right = 63, center = 35
N2.C2.R2.S12: PI = 36
N4.C2.D0.R0.S16: RxDqsDelay = 035
N2.C2.R2.S13: PI = 34
N4.C2.D0.R0.S17: RdDqDqs FSM results: Left = 09, Right = 63, center = 36
N2.C2.R2.S14: PI = 37
N4.C2.D0.R0.S17: RxDqsDelay = 036
N2.C2.R2.S15: PI = 38
N2.C2.R2.S16: PI = 37
N4.C2.D0.R1.S00: RdDqDqs FSM results: Left = 09, Right = 63, center = 36
N2.C2.R2.S17: PI = 37
N4.C2.D0.R1.S00: RxDqsDelay = 036
N2.C2.R2.S00: PI = 35
N4.C2.D0.R1.S01: RdDqDqs FSM results: Left = 12, Right = 63, center = 37
N2.C2.R2.S01: PI = 35
N4.C2.D0.R1.S01: RxDqsDelay = 037
N2.C2.R2.S02: PI = 37
N4.C2.D0.R1.S02: RdDqDqs FSM results: Left = 09, Right = 63, center = 36
N2.C2.R2.S03: PI = 36
N4.C2.D0.R1.S02: RxDqsDelay = 036
N2.C2.R2.S04: PI = 36
N4.C2.D0.R1.S03: RdDqDqs FSM results: Left = 09, Right = 63, center = 36
N2.C2.R2.S05: PI = 36
N4.C2.D0.R1.S03: RxDqsDelay = 036
N2.C2.R2.S06: PI = 35
N4.C2.D0.R1.S04: RdDqDqs FSM results: Left = 10, Right = 63, center = 36
N2.C2.R2.S07: PI = 39
N4.C2.D0.R1.S04: RxDqsDelay = 036
N2.C2.R2.S08: PI = 36
N4.C2.D0.R1.S05: RdDqDqs FSM results: Left = 11, Right = 63, center = 37
N2.C2.R2.S09: PI = 37
N4.C2.D0.R1.S05: RxDqsDelay = 037
N2.C2.R2.S10: PI = 36
N4.C2.D0.R1.S06: RdDqDqs FSM results: Left = 13, Right = 63, center = 38
N2.C2.R2.S11: PI = 37
N4.C2.D0.R1.S06: RxDqsDelay = 038
N2.C2.R2.S12: PI = 36
N4.C2.D0.R1.S07: RdDqDqs FSM results: Left = 11, Right = 63, center = 37
N2.C2.R2.S13: PI = 34
N4.C2.D0.R1.S07: RxDqsDelay = 037
N2.C2.R2.S14: PI = 37
N4.C2.D0.R1.S08: RdDqDqs FSM results: Left = 13, Right = 63, center = 38
N2.C2.R2.S15: PI = 38
N4.C2.D0.R1.S08: RxDqsDelay = 038
N2.C2.R2.S16: PI = 37
N4.C2.D0.R1.S09: RdDqDqs FSM results: Left = 09, Right = 63, center = 36
N2.C2.R2.S17: PI = 37
N4.C2.D0.R1.S09: RxDqsDelay = 036
STOP_DATA_RX_DQS
N4.C2.D0.R1.S10: RdDqDqs FSM results: Left = 14, Right = 63, center = 38
N2.C3.D0.R0.S00: RdDqDqs FSM results: Left = 10, Right = 63, center = 36
N4.C2.D0.R1.S10: RxDqsDelay = 038
N2.C3.D0.R0.S00: RxDqsDelay = 036
N4.C2.D0.R1.S11: RdDqDqs FSM results: Left = 06, Right = 63, center = 34
N2.C3.D0.R0.S01: RdDqDqs FSM results: Left = 03, Right = 63, center = 33
N4.C2.D0.R1.S11: RxDqsDelay = 034
N2.C3.D0.R0.S01: RxDqsDelay = 033
N4.C2.D0.R1.S12: RdDqDqs FSM results: Left = 10, Right = 63, center = 36
N2.C3.D0.R0.S02: RdDqDqs FSM results: Left = 09, Right = 63, center = 36
N4.C2.D0.R1.S12: RxDqsDelay = 036
N2.C3.D0.R0.S02: RxDqsDelay = 036
N4.C2.D0.R1.S13: RdDqDqs FSM results: Left = 06, Right = 59, center = 32
N2.C3.D0.R0.S03: RdDqDqs FSM results: Left = 05, Right = 63, center = 34
N4.C2.D0.R1.S13: RxDqsDelay = 032
N2.C3.D0.R0.S03: RxDqsDelay = 034
N4.C2.D0.R1.S14: RdDqDqs FSM results: Left = 14, Right = 63, center = 38
N2.C3.D0.R0.S04: RdDqDqs FSM results: Left = 06, Right = 63, center = 34
N4.C2.D0.R1.S14: RxDqsDelay = 038
N2.C3.D0.R0.S04: RxDqsDelay = 034
N4.C2.D0.R1.S15: RdDqDqs FSM results: Left = 11, Right = 63, center = 37
N2.C3.D0.R0.S05: RdDqDqs FSM results: Left = 07, Right = 63, center = 35
N4.C2.D0.R1.S15: RxDqsDelay = 037
N2.C3.D0.R0.S05: RxDqsDelay = 035
N4.C2.D0.R1.S16: RdDqDqs FSM results: Left = 09, Right = 63, center = 36
N2.C3.D0.R0.S06: RdDqDqs FSM results: Left = 10, Right = 63, center = 36
N4.C2.D0.R1.S16: RxDqsDelay = 036
N2.C3.D0.R0.S06: RxDqsDelay = 036
N4.C2.D0.R1.S17: RdDqDqs FSM results: Left = 09, Right = 63, center = 36
N2.C3.D0.R0.S07: RdDqDqs FSM results: Left = 08, Right = 63, center = 35
N4.C2.D0.R1.S17: RxDqsDelay = 036
N2.C3.D0.R0.S07: RxDqsDelay = 035
N2.C3.D0.R0.S08: RdDqDqs FSM results: Left = 04, Right = 63, center = 33
N4.C2.D1.R0.S00: RdDqDqs FSM results: Left = 13, Right = 63, center = 38
N6.C0.D0: CalcFinalClock(92,119) = 23
N2.C3.D0.R0.S08: RxDqsDelay = 033
N4.C2.D1.R0.S00: RxDqsDelay = 038
N2.C3.D0.R0.S09: RdDqDqs FSM results: Left = 09, Right = 63, center = 36
N4.C2.D1.R0.S01: RdDqDqs FSM results: Left = 16, Right = 63, center = 39
N6.C0.D1: CalcFinalClock(100,112) = 28
N2.C3.D0.R0.S09: RxDqsDelay = 036
N4.C2.D1.R0.S01: RxDqsDelay = 039
N2.C3.D0.R0.S10: RdDqDqs FSM results: Left = 04, Right = 63, center = 33
N4.C2.D1.R0.S02: RdDqDqs FSM results: Left = 11, Right = 63, center = 37
N6.C1.D0: CalcFinalClock(100,109) = 26
N2.C3.D0.R0.S10: RxDqsDelay = 033
N4.C2.D1.R0.S02: RxDqsDelay = 037
N2.C3.D0.R0.S11: RdDqDqs FSM results: Left = 09, Right = 63, center = 36
N4.C2.D1.R0.S03: RdDqDqs FSM results: Left = 11, Right = 63, center = 37
N6.C1.D1: CalcFinalClock(103,121) = 35
N2.C3.D0.R0.S11: RxDqsDelay = 036
N4.C2.D1.R0.S03: RxDqsDelay = 037
N2.C3.D0.R0.S12: RdDqDqs FSM results: Left = 05, Right = 63, center = 34
N4.C2.D1.R0.S04: RdDqDqs FSM results: Left = 12, Right = 63, center = 37
N6.C2.D0: CalcFinalClock(90,121) = 22
N2.C3.D0.R0.S12: RxDqsDelay = 034
N4.C2.D1.R0.S04: RxDqsDelay = 037
N2.C3.D0.R0.S13: RdDqDqs FSM results: Left = 04, Right = 63, center = 33
N4.C2.D1.R0.S05: RdDqDqs FSM results: Left = 13, Right = 63, center = 38
N6.C2.D1: CalcFinalClock(99,113) = 27
N2.C3.D0.R0.S13: RxDqsDelay = 033
N4.C2.D1.R0.S05: RxDqsDelay = 038
N2.C3.D0.R0.S14: RdDqDqs FSM results: Left = 07, Right = 63, center = 35
N4.C2.D1.R0.S06: RdDqDqs FSM results: Left = 17, Right = 63, center = 40
N6.C3.D0: CalcFinalClock(99,107) = 24
N2.C3.D0.R0.S14: RxDqsDelay = 035
N4.C2.D1.R0.S06: RxDqsDelay = 040
N2.C3.D0.R0.S15: RdDqDqs FSM results: Left = 07, Right = 63, center = 35
N4.C2.D1.R0.S07: RdDqDqs FSM results: Left = 16, Right = 63, center = 39
N6.C3.D1: CalcFinalClock(97,119) = 28
N2.C3.D0.R0.S15: RxDqsDelay = 035
N4.C2.D1.R0.S07: RxDqsDelay = 039
N2.C3.D0.R0.S16: RdDqDqs FSM results: Left = 10, Right = 63, center = 36
N4.C2.D1.R0.S08: RdDqDqs FSM results: Left = 16, Right = 63, center = 39
N6.C0: JCK cmd timing = 3N
N2.C3.D0.R0.S16: RxDqsDelay = 036
N4.C2.D1.R0.S08: RxDqsDelay = 039
N6.C0: RdCmd2DataValidLatency = 20, (dlyFrmS = 15, clEff = 10, earlyCas = 0, selNTiming = 2)
N0.C0.D0: CalcFinalClock(94,120) = 26
N2.C3.D0.R0.S17: RdDqDqs FSM results: Left = 04, Right = 59, center = 31
N4.C2.D1.R0.S09: RdDqDqs FSM results: Left = 11, Right = 63, center = 37
N6.C1: RdCmd2DataValidLatency = 20, (dlyFrmS = 15, clEff = 10, earlyCas = 0, selNTiming = 2)
N0.C0.D1: CalcFinalClock(100,113) = 28
N2.C3.D0.R0.S17: RxDqsDelay = 031
N4.C2.D1.R0.S09: RxDqsDelay = 037
N6.C2: JCK cmd timing = 3N
N0.C1.D0: CalcFinalClock(96,112) = 24
N2.C3.D0.R1.S00: RdDqDqs FSM results: Left = 10, Right = 63, center = 36
N4.C2.D1.R0.S10: RdDqDqs FSM results: Left = 20, Right = 63, center = 41
N6.C2: RdCmd2DataValidLatency = 20, (dlyFrmS = 15, clEff = 10, earlyCas = 0, selNTiming = 2)
N0.C1.D1: CalcFinalClock(103,121) = 35
N2.C3.D0.R1.S00: RxDqsDelay = 036
N4.C2.D1.R0.S10: RxDqsDelay = 041
N6.C3: RdCmd2DataValidLatency = 20, (dlyFrmS = 15, clEff = 10, earlyCas = 0, selNTiming = 2)
N0.C2.D0: CalcFinalClock(92,121) = 24
N2.C3.D0.R1.S01: RdDqDqs FSM results: Left = 04, Right = 63, center = 33
N4.C2.D1.R0.S11: RdDqDqs FSM results: Left = 10, Right = 63, center = 36
N6: RunTrainStep: Final status = 0
N0.C2.D1: CalcFinalClock(102,111) = 29
N2.C3.D0.R1.S01: RxDqsDelay = 033
N4.C2.D1.R0.S11: RxDqsDelay = 036

END - Early Command Training           Time         4425 ms
N0.C3.D0: CalcFinalClock(98,110) = 25
N2.C3.D0.R1.S02: RdDqDqs FSM results: Left = 10, Right = 63, center = 36
N4.C2.D1.R0.S12: RdDqDqs FSM results: Left = 13, Right = 63, center = 38

START - Basic Read DQ/DQS Training
N0.C3.D1: CalcFinalClock(96,120) = 28
N2.C3.D0.R1.S02: RxDqsDelay = 036
N4.C2.D1.R0.S12: RxDqsDelay = 038
N6.C0: RdCmd2DataValidLatency = 20, (dlyFrmS = 15, clEff = 10, earlyCas = 0, selNTiming = 2)
N0.C0: JCK cmd timing = 3N
N2.C3.D0.R1.S03: RdDqDqs FSM results: Left = 05, Right = 63, center = 34
N4.C2.D1.R0.S13: RdDqDqs FSM results: Left = 09, Right = 63, center = 36
N6.C0: SettingForTrainingStep: RdCmd2RcvEnLatency = 5
N0.C0: RdCmd2DataValidLatency = 20, (dlyFrmS = 15, clEff = 10, earlyCas = 0, selNTiming = 2)
N2.C3.D0.R1.S03: RxDqsDelay = 034
N4.C2.D1.R0.S13: RxDqsDelay = 036
N6.C1: RdCmd2DataValidLatency = 20, (dlyFrmS = 15, clEff = 10, earlyCas = 0, selNTiming = 2)
N0.C1: RdCmd2DataValidLatency = 20, (dlyFrmS = 15, clEff = 10, earlyCas = 0, selNTiming = 2)
N2.C3.D0.R1.S04: RdDqDqs FSM results: Left = 06, Right = 63, center = 34
N4.C2.D1.R0.S14: RdDqDqs FSM results: Left = 18, Right = 63, center = 40
N6.C1: SettingForTrainingStep: RdCmd2RcvEnLatency = 5
N0.C2: JCK cmd timing = 3N
N2.C3.D0.R1.S04: RxDqsDelay = 034
N4.C2.D1.R0.S14: RxDqsDelay = 040
N6.C2: RdCmd2DataValidLatency = 20, (dlyFrmS = 15, clEff = 10, earlyCas = 0, selNTiming = 2)
N0.C2: RdCmd2DataValidLatency = 20, (dlyFrmS = 15, clEff = 10, earlyCas = 0, selNTiming = 2)
N2.C3.D0.R1.S05: RdDqDqs FSM results: Left = 07, Right = 63, center = 35
N4.C2.D1.R0.S15: RdDqDqs FSM results: Left = 16, Right = 63, center = 39
N6.C2: SettingForTrainingStep: RdCmd2RcvEnLatency = 5
N0.C3: RdCmd2DataValidLatency = 20, (dlyFrmS = 15, clEff = 10, earlyCas = 0, selNTiming = 2)
N2.C3.D0.R1.S05: RxDqsDelay = 035
N4.C2.D1.R0.S15: RxDqsDelay = 039
N6.C3: RdCmd2DataValidLatency = 20, (dlyFrmS = 15, clEff = 10, earlyCas = 0, selNTiming = 2)
N0: RunTrainStep: Final status = 0
N2.C3.D0.R1.S06: RdDqDqs FSM results: Left = 09, Right = 63, center = 36
N4.C2.D1.R0.S16: RdDqDqs FSM results: Left = 12, Right = 63, center = 37
N6.C3: SettingForTrainingStep: RdCmd2RcvEnLatency = 5

END - Early Command Training           Time         4206 ms
N2.C3.D0.R1.S06: RxDqsDelay = 036
N4.C2.D1.R0.S16: RxDqsDelay = 037
N6.C0.D0.R0.S00: RdDqDqs FSM results: Left = 04, Right = 59, center = 31

START - Basic Read DQ/DQS Training
N2.C3.D0.R1.S07: RdDqDqs FSM results: Left = 07, Right = 63, center = 35
N4.C2.D1.R0.S17: RdDqDqs FSM results: Left = 13, Right = 63, center = 38
N6.C0.D0.R0.S00: RxDqsDelay = 031
Checkpoint Code: Socket 0, 0xB7, 0x01, 0x0000
N2.C3.D0.R1.S07: RxDqsDelay = 035
N4.C2.D1.R0.S17: RxDqsDelay = 038
N6.C0.D0.R0.S01: RdDqDqs FSM results: Left = 03, Right = 63, center = 33
N0.C0: RdCmd2DataValidLatency = 20, (dlyFrmS = 15, clEff = 10, earlyCas = 0, selNTiming = 2)
N2.C3.D0.R1.S08: RdDqDqs FSM results: Left = 04, Right = 63, center = 33
N4.C2.D1.R1.S00: RdDqDqs FSM results: Left = 12, Right = 63, center = 37
N6.C0.D0.R0.S01: RxDqsDelay = 033
N0.C0: SettingForTrainingStep: RdCmd2RcvEnLatency = 5
N2.C3.D0.R1.S08: RxDqsDelay = 033
N4.C2.D1.R1.S00: RxDqsDelay = 037
N6.C0.D0.R0.S02: RdDqDqs FSM results: Left = 04, Right = 63, center = 33
N0.C1: RdCmd2DataValidLatency = 20, (dlyFrmS = 15, clEff = 10, earlyCas = 0, selNTiming = 2)
N2.C3.D0.R1.S09: RdDqDqs FSM results: Left = 08, Right = 63, center = 35
N4.C2.D1.R1.S01: RdDqDqs FSM results: Left = 16, Right = 63, center = 39
N6.C0.D0.R0.S02: RxDqsDelay = 033
N0.C1: SettingForTrainingStep: RdCmd2RcvEnLatency = 5
N2.C3.D0.R1.S09: RxDqsDelay = 035
N4.C2.D1.R1.S01: RxDqsDelay = 039
N6.C0.D0.R0.S03: RdDqDqs FSM results: Left = 04, Right = 63, center = 33
N0.C2: RdCmd2DataValidLatency = 20, (dlyFrmS = 15, clEff = 10, earlyCas = 0, selNTiming = 2)
N2.C3.D0.R1.S10: RdDqDqs FSM results: Left = 04, Right = 63, center = 33
N4.C2.D1.R1.S02: RdDqDqs FSM results: Left = 11, Right = 63, center = 37
N6.C0.D0.R0.S03: RxDqsDelay = 033
N0.C2: SettingForTrainingStep: RdCmd2RcvEnLatency = 5
N2.C3.D0.R1.S10: RxDqsDelay = 033
N4.C2.D1.R1.S02: RxDqsDelay = 037
N6.C0.D0.R0.S04: RdDqDqs FSM results: Left = 03, Right = 63, center = 33
N0.C3: RdCmd2DataValidLatency = 20, (dlyFrmS = 15, clEff = 10, earlyCas = 0, selNTiming = 2)
N2.C3.D0.R1.S11: RdDqDqs FSM results: Left = 08, Right = 63, center = 35
N4.C2.D1.R1.S03: RdDqDqs FSM results: Left = 10, Right = 63, center = 36
N6.C0.D0.R0.S04: RxDqsDelay = 033
N0.C3: SettingForTrainingStep: RdCmd2RcvEnLatency = 5
N2.C3.D0.R1.S11: RxDqsDelay = 035
N4.C2.D1.R1.S03: RxDqsDelay = 036
N6.C0.D0.R0.S05: RdDqDqs FSM results: Left = 06, Right = 63, center = 34
N0.C0.D0.R0.S00: RdDqDqs FSM results: Left = 04, Right = 63, center = 33
N2.C3.D0.R1.S12: RdDqDqs FSM results: Left = 04, Right = 63, center = 33
N4.C2.D1.R1.S04: RdDqDqs FSM results: Left = 12, Right = 63, center = 37
N6.C0.D0.R0.S05: RxDqsDelay = 034
N0.C0.D0.R0.S00: RxDqsDelay = 033
N2.C3.D0.R1.S12: RxDqsDelay = 033
N4.C2.D1.R1.S04: RxDqsDelay = 037
N6.C0.D0.R0.S06: RdDqDqs FSM results: Left = 04, Right = 63, center = 33
N0.C0.D0.R0.S01: RdDqDqs FSM results: Left = 04, Right = 63, center = 33
N2.C3.D0.R1.S13: RdDqDqs FSM results: Left = 04, Right = 63, center = 33
N4.C2.D1.R1.S05: RdDqDqs FSM results: Left = 14, Right = 63, center = 38
N6.C0.D0.R0.S06: RxDqsDelay = 033
N0.C0.D0.R0.S01: RxDqsDelay = 033
N2.C3.D0.R1.S13: RxDqsDelay = 033
N4.C2.D1.R1.S05: RxDqsDelay = 038
N6.C0.D0.R0.S07: RdDqDqs FSM results: Left = 05, Right = 63, center = 34
N0.C0.D0.R0.S02: RdDqDqs FSM results: Left = 04, Right = 63, center = 33
N2.C3.D0.R1.S14: RdDqDqs FSM results: Left = 08, Right = 63, center = 35
N4.C2.D1.R1.S06: RdDqDqs FSM results: Left = 18, Right = 63, center = 40
N6.C0.D0.R0.S07: RxDqsDelay = 034
N0.C0.D0.R0.S02: RxDqsDelay = 033
N2.C3.D0.R1.S14: RxDqsDelay = 035
N4.C2.D1.R1.S06: RxDqsDelay = 040
N6.C0.D0.R0.S08: RdDqDqs FSM results: Left = 06, Right = 63, center = 34
N0.C0.D0.R0.S03: RdDqDqs FSM results: Left = 03, Right = 63, center = 33
N2.C3.D0.R1.S15: RdDqDqs FSM results: Left = 07, Right = 63, center = 35
N4.C2.D1.R1.S07: RdDqDqs FSM results: Left = 15, Right = 63, center = 39
N6.C0.D0.R0.S08: RxDqsDelay = 034
N0.C0.D0.R0.S03: RxDqsDelay = 033
N2.C3.D0.R1.S15: RxDqsDelay = 035
N4.C2.D1.R1.S07: RxDqsDelay = 039
N6.C0.D0.R0.S09: RdDqDqs FSM results: Left = 04, Right = 63, center = 33
N0.C0.D0.R0.S04: RdDqDqs FSM results: Left = 05, Right = 63, center = 34
N2.C3.D0.R1.S16: RdDqDqs FSM results: Left = 11, Right = 63, center = 37
N4.C2.D1.R1.S08: RdDqDqs FSM results: Left = 17, Right = 63, center = 40
N6.C0.D0.R0.S09: RxDqsDelay = 033
N0.C0.D0.R0.S04: RxDqsDelay = 034
N2.C3.D0.R1.S16: RxDqsDelay = 037
N4.C2.D1.R1.S08: RxDqsDelay = 040
N6.C0.D0.R0.S10: RdDqDqs FSM results: Left = 03, Right = 58, center = 30
N0.C0.D0.R0.S05: RdDqDqs FSM results: Left = 06, Right = 63, center = 34
N2.C3.D0.R1.S17: RdDqDqs FSM results: Left = 04, Right = 61, center = 32
N4.C2.D1.R1.S09: RdDqDqs FSM results: Left = 12, Right = 63, center = 37
N6.C0.D0.R0.S10: RxDqsDelay = 030
N0.C0.D0.R0.S05: RxDqsDelay = 034
N2.C3.D0.R1.S17: RxDqsDelay = 032
N4.C2.D1.R1.S09: RxDqsDelay = 037
N6.C0.D0.R0.S11: RdDqDqs FSM results: Left = 05, Right = 63, center = 34
N0.C0.D0.R0.S06: RdDqDqs FSM results: Left = 04, Right = 63, center = 33
N2.C3.D1.R0.S00: RdDqDqs FSM results: Left = 14, Right = 63, center = 38
N4.C2.D1.R1.S10: RdDqDqs FSM results: Left = 19, Right = 63, center = 41
N6.C0.D0.R0.S11: RxDqsDelay = 034
N0.C0.D0.R0.S06: RxDqsDelay = 033
N2.C3.D1.R0.S00: RxDqsDelay = 038
N4.C2.D1.R1.S10: RxDqsDelay = 041
N6.C0.D0.R0.S12: RdDqDqs FSM results: Left = 04, Right = 63, center = 33
N0.C0.D0.R0.S07: RdDqDqs FSM results: Left = 06, Right = 63, center = 34
N2.C3.D1.R0.S01: RdDqDqs FSM results: Left = 06, Right = 63, center = 34
N4.C2.D1.R1.S11: RdDqDqs FSM results: Left = 10, Right = 63, center = 36
N6.C0.D0.R0.S12: RxDqsDelay = 033
N0.C0.D0.R0.S07: RxDqsDelay = 034
N2.C3.D1.R0.S01: RxDqsDelay = 034
N4.C2.D1.R1.S11: RxDqsDelay = 036
N6.C0.D0.R0.S13: RdDqDqs FSM results: Left = 03, Right = 63, center = 33
N0.C0.D0.R0.S08: RdDqDqs FSM results: Left = 03, Right = 63, center = 33
N2.C3.D1.R0.S02: RdDqDqs FSM results: Left = 12, Right = 63, center = 37
N4.C2.D1.R1.S12: RdDqDqs FSM results: Left = 12, Right = 63, center = 37
N6.C0.D0.R0.S13: RxDqsDelay = 033
N0.C0.D0.R0.S08: RxDqsDelay = 033
N2.C3.D1.R0.S02: RxDqsDelay = 037
N4.C2.D1.R1.S12: RxDqsDelay = 037
N6.C0.D0.R0.S14: RdDqDqs FSM results: Left = 06, Right = 63, center = 34
N0.C0.D0.R0.S09: RdDqDqs FSM results: Left = 05, Right = 63, center = 34
N2.C3.D1.R0.S03: RdDqDqs FSM results: Left = 07, Right = 63, center = 35
N4.C2.D1.R1.S13: RdDqDqs FSM results: Left = 09, Right = 63, center = 36
N6.C0.D0.R0.S14: RxDqsDelay = 034
N0.C0.D0.R0.S09: RxDqsDelay = 034
N2.C3.D1.R0.S03: RxDqsDelay = 035
N4.C2.D1.R1.S13: RxDqsDelay = 036
N6.C0.D0.R0.S15: RdDqDqs FSM results: Left = 07, Right = 63, center = 35
N0.C0.D0.R0.S10: RdDqDqs FSM results: Left = 03, Right = 63, center = 33
N2.C3.D1.R0.S04: RdDqDqs FSM results: Left = 11, Right = 63, center = 37
N4.C2.D1.R1.S14: RdDqDqs FSM results: Left = 17, Right = 63, center = 40
N6.C0.D0.R0.S15: RxDqsDelay = 035
N0.C0.D0.R0.S10: RxDqsDelay = 033
N2.C3.D1.R0.S04: RxDqsDelay = 037
N4.C2.D1.R1.S14: RxDqsDelay = 040
N6.C0.D0.R0.S16: RdDqDqs FSM results: Left = 08, Right = 63, center = 35
N0.C0.D0.R0.S11: RdDqDqs FSM results: Left = 03, Right = 63, center = 33
N2.C3.D1.R0.S05: RdDqDqs FSM results: Left = 10, Right = 63, center = 36
N4.C2.D1.R1.S15: RdDqDqs FSM results: Left = 16, Right = 63, center = 39
N6.C0.D0.R0.S16: RxDqsDelay = 035
N0.C0.D0.R0.S11: RxDqsDelay = 033
N2.C3.D1.R0.S05: RxDqsDelay = 036
N4.C2.D1.R1.S15: RxDqsDelay = 039
N6.C0.D0.R0.S17: RdDqDqs FSM results: Left = 08, Right = 63, center = 35
N0.C0.D0.R0.S12: RdDqDqs FSM results: Left = 05, Right = 63, center = 34
N2.C3.D1.R0.S06: RdDqDqs FSM results: Left = 11, Right = 63, center = 37
N4.C2.D1.R1.S16: RdDqDqs FSM results: Left = 11, Right = 63, center = 37
N6.C0.D0.R0.S17: RxDqsDelay = 035
N0.C0.D0.R0.S12: RxDqsDelay = 034
N2.C3.D1.R0.S06: RxDqsDelay = 037
N4.C2.D1.R1.S16: RxDqsDelay = 037
N6.C0.D0.R1.S00: RdDqDqs FSM results: Left = 05, Right = 59, center = 32
N0.C0.D0.R0.S13: RdDqDqs FSM results: Left = 05, Right = 63, center = 34
N2.C3.D1.R0.S07: RdDqDqs FSM results: Left = 11, Right = 63, center = 37
N4.C2.D1.R1.S17: RdDqDqs FSM results: Left = 12, Right = 63, center = 37
N6.C0.D0.R1.S00: RxDqsDelay = 032
N0.C0.D0.R0.S13: RxDqsDelay = 034
N2.C3.D1.R0.S07: RxDqsDelay = 037
N4.C2.D1.R1.S17: RxDqsDelay = 037
N6.C0.D0.R1.S01: RdDqDqs FSM results: Left = 04, Right = 63, center = 33
N0.C0.D0.R0.S14: RdDqDqs FSM results: Left = 03, Right = 63, center = 33
N2.C3.D1.R0.S08: RdDqDqs FSM results: Left = 09, Right = 63, center = 36
START_DATA_RX_DQS
N6.C0.D0.R1.S01: RxDqsDelay = 033
N0.C0.D0.R0.S14: RxDqsDelay = 033
N2.C3.D1.R0.S08: RxDqsDelay = 036
N4.C2.R0.S00: PI = 36
N6.C0.D0.R1.S02: RdDqDqs FSM results: Left = 05, Right = 63, center = 34
N0.C0.D0.R0.S15: RdDqDqs FSM results: Left = 02, Right = 61, center = 31
N2.C3.D1.R0.S09: RdDqDqs FSM results: Left = 12, Right = 63, center = 37
N4.C2.R0.S01: PI = 37
N6.C0.D0.R1.S02: RxDqsDelay = 034
N0.C0.D0.R0.S15: RxDqsDelay = 031
N2.C3.D1.R0.S09: RxDqsDelay = 037
N4.C2.R0.S02: PI = 36
N6.C0.D0.R1.S03: RdDqDqs FSM results: Left = 04, Right = 63, center = 33
N0.C0.D0.R0.S16: RdDqDqs FSM results: Left = 03, Right = 63, center = 33
N2.C3.D1.R0.S10: RdDqDqs FSM results: Left = 08, Right = 63, center = 35
N4.C2.R0.S03: PI = 35
N6.C0.D0.R1.S03: RxDqsDelay = 033
N0.C0.D0.R0.S16: RxDqsDelay = 033
N2.C3.D1.R0.S10: RxDqsDelay = 035
N4.C2.R0.S04: PI = 36
N6.C0.D0.R1.S04: RdDqDqs FSM results: Left = 05, Right = 63, center = 34
N0.C0.D0.R0.S17: RdDqDqs FSM results: Left = 05, Right = 63, center = 34
N2.C3.D1.R0.S11: RdDqDqs FSM results: Left = 10, Right = 63, center = 36
N4.C2.R0.S05: PI = 37
N6.C0.D0.R1.S04: RxDqsDelay = 034
N0.C0.D0.R0.S17: RxDqsDelay = 034
N2.C3.D1.R0.S11: RxDqsDelay = 036
N4.C2.R0.S06: PI = 38
N6.C0.D0.R1.S05: RdDqDqs FSM results: Left = 05, Right = 63, center = 34
N0.C0.D0.R1.S00: RdDqDqs FSM results: Left = 03, Right = 63, center = 33
N2.C3.D1.R0.S12: RdDqDqs FSM results: Left = 08, Right = 63, center = 35
N4.C2.R0.S07: PI = 37
N6.C0.D0.R1.S05: RxDqsDelay = 034
N0.C0.D0.R1.S00: RxDqsDelay = 033
N2.C3.D1.R0.S12: RxDqsDelay = 035
N4.C2.R0.S08: PI = 38
N6.C0.D0.R1.S06: RdDqDqs FSM results: Left = 04, Right = 63, center = 33
N0.C0.D0.R1.S01: RdDqDqs FSM results: Left = 03, Right = 63, center = 33
N2.C3.D1.R0.S13: RdDqDqs FSM results: Left = 08, Right = 63, center = 35
N4.C2.R0.S09: PI = 36
N6.C0.D0.R1.S06: RxDqsDelay = 033
N0.C0.D0.R1.S01: RxDqsDelay = 033
N2.C3.D1.R0.S13: RxDqsDelay = 035
N4.C2.R0.S10: PI = 38
N6.C0.D0.R1.S07: RdDqDqs FSM results: Left = 04, Right = 63, center = 33
N0.C0.D0.R1.S02: RdDqDqs FSM results: Left = 04, Right = 63, center = 33
N2.C3.D1.R0.S14: RdDqDqs FSM results: Left = 10, Right = 63, center = 36
N4.C2.R0.S11: PI = 34
N6.C0.D0.R1.S07: RxDqsDelay = 033
N0.C0.D0.R1.S02: RxDqsDelay = 033
N2.C3.D1.R0.S14: RxDqsDelay = 036
N4.C2.R0.S12: PI = 36
N6.C0.D0.R1.S08: RdDqDqs FSM results: Left = 05, Right = 63, center = 34
N0.C0.D0.R1.S03: RdDqDqs FSM results: Left = 04, Right = 63, center = 33
N2.C3.D1.R0.S15: RdDqDqs FSM results: Left = 10, Right = 63, center = 36
N4.C2.R0.S13: PI = 32
N6.C0.D0.R1.S08: RxDqsDelay = 034
N0.C0.D0.R1.S03: RxDqsDelay = 033
N2.C3.D1.R0.S15: RxDqsDelay = 036
N4.C2.R0.S14: PI = 38
N6.C0.D0.R1.S09: RdDqDqs FSM results: Left = 05, Right = 63, center = 34
N0.C0.D0.R1.S04: RdDqDqs FSM results: Left = 05, Right = 63, center = 34
N2.C3.D1.R0.S16: RdDqDqs FSM results: Left = 12, Right = 63, center = 37
N4.C2.R0.S15: PI = 37
N6.C0.D0.R1.S09: RxDqsDelay = 034
N0.C0.D0.R1.S04: RxDqsDelay = 034
N2.C3.D1.R0.S16: RxDqsDelay = 037
N4.C2.R0.S16: PI = 35
N6.C0.D0.R1.S10: RdDqDqs FSM results: Left = 04, Right = 59, center = 31
N0.C0.D0.R1.S05: RdDqDqs FSM results: Left = 07, Right = 63, center = 35
N2.C3.D1.R0.S17: RdDqDqs FSM results: Left = 07, Right = 63, center = 35
N4.C2.R0.S17: PI = 36
N6.C0.D0.R1.S10: RxDqsDelay = 031
N0.C0.D0.R1.S05: RxDqsDelay = 035
N2.C3.D1.R0.S17: RxDqsDelay = 035
N4.C2.R0.S00: PI = 36
N6.C0.D0.R1.S11: RdDqDqs FSM results: Left = 04, Right = 61, center = 32
N0.C0.D0.R1.S06: RdDqDqs FSM results: Left = 05, Right = 63, center = 34
N2.C3.D1.R1.S00: RdDqDqs FSM results: Left = 14, Right = 63, center = 38
N4.C2.R0.S01: PI = 37
N6.C0.D0.R1.S11: RxDqsDelay = 032
N0.C0.D0.R1.S06: RxDqsDelay = 034
N2.C3.D1.R1.S00: RxDqsDelay = 038
N4.C2.R0.S02: PI = 36
N6.C0.D0.R1.S12: RdDqDqs FSM results: Left = 05, Right = 63, center = 34
N0.C0.D0.R1.S07: RdDqDqs FSM results: Left = 05, Right = 63, center = 34
N2.C3.D1.R1.S01: RdDqDqs FSM results: Left = 07, Right = 63, center = 35
N4.C2.R0.S03: PI = 35
N6.C0.D0.R1.S12: RxDqsDelay = 034
N0.C0.D0.R1.S07: RxDqsDelay = 034
N2.C3.D1.R1.S01: RxDqsDelay = 035
N4.C2.R0.S04: PI = 36
N6.C0.D0.R1.S13: RdDqDqs FSM results: Left = 03, Right = 63, center = 33
N0.C0.D0.R1.S08: RdDqDqs FSM results: Left = 03, Right = 63, center = 33
N2.C3.D1.R1.S02: RdDqDqs FSM results: Left = 12, Right = 63, center = 37
N4.C2.R0.S05: PI = 37
N6.C0.D0.R1.S13: RxDqsDelay = 033
N0.C0.D0.R1.S08: RxDqsDelay = 033
N2.C3.D1.R1.S02: RxDqsDelay = 037
N4.C2.R0.S06: PI = 38
N6.C0.D0.R1.S14: RdDqDqs FSM results: Left = 06, Right = 63, center = 34
N0.C0.D0.R1.S09: RdDqDqs FSM results: Left = 04, Right = 63, center = 33
N2.C3.D1.R1.S03: RdDqDqs FSM results: Left = 07, Right = 63, center = 35
N4.C2.R0.S07: PI = 37
N6.C0.D0.R1.S14: RxDqsDelay = 034
N0.C0.D0.R1.S09: RxDqsDelay = 033
N2.C3.D1.R1.S03: RxDqsDelay = 035
N4.C2.R0.S08: PI = 38
N6.C0.D0.R1.S15: RdDqDqs FSM results: Left = 06, Right = 63, center = 34
N0.C0.D0.R1.S10: RdDqDqs FSM results: Left = 05, Right = 63, center = 34
N2.C3.D1.R1.S04: RdDqDqs FSM results: Left = 10, Right = 63, center = 36
N4.C2.R0.S09: PI = 36
N6.C0.D0.R1.S15: RxDqsDelay = 034
N0.C0.D0.R1.S10: RxDqsDelay = 034
N2.C3.D1.R1.S04: RxDqsDelay = 036
N4.C2.R0.S10: PI = 38
N6.C0.D0.R1.S16: RdDqDqs FSM results: Left = 08, Right = 63, center = 35
N0.C0.D0.R1.S11: RdDqDqs FSM results: Left = 03, Right = 63, center = 33
N2.C3.D1.R1.S05: RdDqDqs FSM results: Left = 10, Right = 63, center = 36
N4.C2.R0.S11: PI = 34
N6.C0.D0.R1.S16: RxDqsDelay = 035
N0.C0.D0.R1.S11: RxDqsDelay = 033
N2.C3.D1.R1.S05: RxDqsDelay = 036
N4.C2.R0.S12: PI = 36
N6.C0.D0.R1.S17: RdDqDqs FSM results: Left = 07, Right = 63, center = 35
N0.C0.D0.R1.S12: RdDqDqs FSM results: Left = 04, Right = 63, center = 33
N2.C3.D1.R1.S06: RdDqDqs FSM results: Left = 11, Right = 63, center = 37
N4.C2.R0.S13: PI = 32
N6.C0.D0.R1.S17: RxDqsDelay = 035
N0.C0.D0.R1.S12: RxDqsDelay = 033
N2.C3.D1.R1.S06: RxDqsDelay = 037
N4.C2.R0.S14: PI = 38
N6.C0.D1.R0.S00: RdDqDqs FSM results: Left = 07, Right = 63, center = 35
N0.C0.D0.R1.S13: RdDqDqs FSM results: Left = 05, Right = 63, center = 34
N2.C3.D1.R1.S07: RdDqDqs FSM results: Left = 11, Right = 63, center = 37
N4.C2.R0.S15: PI = 37
N6.C0.D1.R0.S00: RxDqsDelay = 035
N0.C0.D0.R1.S13: RxDqsDelay = 034
N2.C3.D1.R1.S07: RxDqsDelay = 037
N4.C2.R0.S16: PI = 35
N6.C0.D1.R0.S01: RdDqDqs FSM results: Left = 07, Right = 63, center = 35
N0.C0.D0.R1.S14: RdDqDqs FSM results: Left = 04, Right = 63, center = 33
N2.C3.D1.R1.S08: RdDqDqs FSM results: Left = 09, Right = 63, center = 36
N4.C2.R0.S17: PI = 36
N6.C0.D1.R0.S01: RxDqsDelay = 035
N0.C0.D0.R1.S14: RxDqsDelay = 033
N2.C3.D1.R1.S08: RxDqsDelay = 036
N4.C2.R2.S00: PI = 37
N6.C0.D1.R0.S02: RdDqDqs FSM results: Left = 09, Right = 63, center = 36
N0.C0.D0.R1.S15: RdDqDqs FSM results: Left = 03, Right = 63, center = 33
N2.C3.D1.R1.S09: RdDqDqs FSM results: Left = 12, Right = 63, center = 37
N4.C2.R2.S01: PI = 39
N6.C0.D1.R0.S02: RxDqsDelay = 036
N0.C0.D0.R1.S15: RxDqsDelay = 033
N2.C3.D1.R1.S09: RxDqsDelay = 037
N4.C2.R2.S02: PI = 37
N6.C0.D1.R0.S03: RdDqDqs FSM results: Left = 06, Right = 63, center = 34
N0.C0.D0.R1.S16: RdDqDqs FSM results: Left = 02, Right = 63, center = 32
N2.C3.D1.R1.S10: RdDqDqs FSM results: Left = 08, Right = 63, center = 35
N4.C2.R2.S03: PI = 36
N6.C0.D1.R0.S03: RxDqsDelay = 034
N0.C0.D0.R1.S16: RxDqsDelay = 032
N2.C3.D1.R1.S10: RxDqsDelay = 035
N4.C2.R2.S04: PI = 37
N6.C0.D1.R0.S04: RdDqDqs FSM results: Left = 07, Right = 63, center = 35
N0.C0.D0.R1.S17: RdDqDqs FSM results: Left = 05, Right = 63, center = 34
N2.C3.D1.R1.S11: RdDqDqs FSM results: Left = 10, Right = 63, center = 36
N4.C2.R2.S05: PI = 38
N6.C0.D1.R0.S04: RxDqsDelay = 035
N0.C0.D0.R1.S17: RxDqsDelay = 034
N2.C3.D1.R1.S11: RxDqsDelay = 036
N4.C2.R2.S06: PI = 40
N6.C0.D1.R0.S05: RdDqDqs FSM results: Left = 09, Right = 63, center = 36
N0.C0.D1.R0.S00: RdDqDqs FSM results: Left = 07, Right = 63, center = 35
N2.C3.D1.R1.S12: RdDqDqs FSM results: Left = 09, Right = 63, center = 36
N4.C2.R2.S07: PI = 39
N6.C0.D1.R0.S05: RxDqsDelay = 036
N0.C0.D1.R0.S00: RxDqsDelay = 035
N2.C3.D1.R1.S12: RxDqsDelay = 036
N4.C2.R2.S08: PI = 39
N6.C0.D1.R0.S06: RdDqDqs FSM results: Left = 08, Right = 63, center = 35
N0.C0.D1.R0.S01: RdDqDqs FSM results: Left = 08, Right = 63, center = 35
N2.C3.D1.R1.S13: RdDqDqs FSM results: Left = 09, Right = 63, center = 36
N4.C2.R2.S09: PI = 37
N6.C0.D1.R0.S06: RxDqsDelay = 035
N0.C0.D1.R0.S01: RxDqsDelay = 035
N2.C3.D1.R1.S13: RxDqsDelay = 036
N4.C2.R2.S10: PI = 41
N6.C0.D1.R0.S07: RdDqDqs FSM results: Left = 10, Right = 63, center = 36
N0.C0.D1.R0.S02: RdDqDqs FSM results: Left = 09, Right = 63, center = 36
N2.C3.D1.R1.S14: RdDqDqs FSM results: Left = 11, Right = 63, center = 37
N4.C2.R2.S11: PI = 36
N6.C0.D1.R0.S07: RxDqsDelay = 036
N0.C0.D1.R0.S02: RxDqsDelay = 036
N2.C3.D1.R1.S14: RxDqsDelay = 037
N4.C2.R2.S12: PI = 37
N6.C0.D1.R0.S08: RdDqDqs FSM results: Left = 10, Right = 63, center = 36
N0.C0.D1.R0.S03: RdDqDqs FSM results: Left = 07, Right = 63, center = 35
N2.C3.D1.R1.S15: RdDqDqs FSM results: Left = 10, Right = 63, center = 36
N4.C2.R2.S13: PI = 36
N6.C0.D1.R0.S08: RxDqsDelay = 036
N0.C0.D1.R0.S03: RxDqsDelay = 035
N2.C3.D1.R1.S15: RxDqsDelay = 036
N4.C2.R2.S14: PI = 40
N6.C0.D1.R0.S09: RdDqDqs FSM results: Left = 07, Right = 63, center = 35
N0.C0.D1.R0.S04: RdDqDqs FSM results: Left = 08, Right = 63, center = 35
N2.C3.D1.R1.S16: RdDqDqs FSM results: Left = 12, Right = 63, center = 37
N4.C2.R2.S15: PI = 39
N6.C0.D1.R0.S09: RxDqsDelay = 035
N0.C0.D1.R0.S04: RxDqsDelay = 035
N2.C3.D1.R1.S16: RxDqsDelay = 037
N4.C2.R2.S16: PI = 37
N6.C0.D1.R0.S10: RdDqDqs FSM results: Left = 06, Right = 63, center = 34
N0.C0.D1.R0.S05: RdDqDqs FSM results: Left = 09, Right = 63, center = 36
N2.C3.D1.R1.S17: RdDqDqs FSM results: Left = 07, Right = 63, center = 35
N4.C2.R2.S17: PI = 37
N6.C0.D1.R0.S10: RxDqsDelay = 034
N0.C0.D1.R0.S05: RxDqsDelay = 036
N2.C3.D1.R1.S17: RxDqsDelay = 035
N4.C2.R2.S00: PI = 37
N6.C0.D1.R0.S11: RdDqDqs FSM results: Left = 07, Right = 63, center = 35
N0.C0.D1.R0.S06: RdDqDqs FSM results: Left = 09, Right = 63, center = 36
START_DATA_RX_DQS
N4.C2.R2.S01: PI = 39
N6.C0.D1.R0.S11: RxDqsDelay = 035
N0.C0.D1.R0.S06: RxDqsDelay = 036
N2.C3.R0.S00: PI = 36
N4.C2.R2.S02: PI = 37
N6.C0.D1.R0.S12: RdDqDqs FSM results: Left = 07, Right = 63, center = 35
N0.C0.D1.R0.S07: RdDqDqs FSM results: Left = 08, Right = 63, center = 35
N2.C3.R0.S01: PI = 33
N4.C2.R2.S03: PI = 36
N6.C0.D1.R0.S12: RxDqsDelay = 035
N0.C0.D1.R0.S07: RxDqsDelay = 035
N2.C3.R0.S02: PI = 36
N4.C2.R2.S04: PI = 37
N6.C0.D1.R0.S13: RdDqDqs FSM results: Left = 07, Right = 63, center = 35
N0.C0.D1.R0.S08: RdDqDqs FSM results: Left = 06, Right = 63, center = 34
N2.C3.R0.S03: PI = 34
N4.C2.R2.S05: PI = 38
N6.C0.D1.R0.S13: RxDqsDelay = 035
N0.C0.D1.R0.S08: RxDqsDelay = 034
N2.C3.R0.S04: PI = 34
N4.C2.R2.S06: PI = 40
N6.C0.D1.R0.S14: RdDqDqs FSM results: Left = 09, Right = 63, center = 36
N0.C0.D1.R0.S09: RdDqDqs FSM results: Left = 10, Right = 63, center = 36
N2.C3.R0.S05: PI = 35
N4.C2.R2.S07: PI = 39
N6.C0.D1.R0.S14: RxDqsDelay = 036
N0.C0.D1.R0.S09: RxDqsDelay = 036
N2.C3.R0.S06: PI = 36
N4.C2.R2.S08: PI = 39
N6.C0.D1.R0.S15: RdDqDqs FSM results: Left = 10, Right = 63, center = 36
N0.C0.D1.R0.S10: RdDqDqs FSM results: Left = 08, Right = 63, center = 35
N2.C3.R0.S07: PI = 35
N4.C2.R2.S09: PI = 37
N6.C0.D1.R0.S15: RxDqsDelay = 036
N0.C0.D1.R0.S10: RxDqsDelay = 035
N2.C3.R0.S08: PI = 33
N4.C2.R2.S10: PI = 41
N6.C0.D1.R0.S16: RdDqDqs FSM results: Left = 11, Right = 63, center = 37
N0.C0.D1.R0.S11: RdDqDqs FSM results: Left = 05, Right = 63, center = 34
N2.C3.R0.S09: PI = 35
N4.C2.R2.S11: PI = 36
N6.C0.D1.R0.S16: RxDqsDelay = 037
N0.C0.D1.R0.S11: RxDqsDelay = 034
N2.C3.R0.S10: PI = 33
N4.C2.R2.S12: PI = 37
N6.C0.D1.R0.S17: RdDqDqs FSM results: Left = 10, Right = 63, center = 36
N0.C0.D1.R0.S12: RdDqDqs FSM results: Left = 08, Right = 63, center = 35
N2.C3.R0.S11: PI = 35
N4.C2.R2.S13: PI = 36
N6.C0.D1.R0.S17: RxDqsDelay = 036
N0.C0.D1.R0.S12: RxDqsDelay = 035
N2.C3.R0.S12: PI = 33
N4.C2.R2.S14: PI = 40
N6.C0.D1.R1.S00: RdDqDqs FSM results: Left = 08, Right = 63, center = 35
N0.C0.D1.R0.S13: RdDqDqs FSM results: Left = 09, Right = 63, center = 36
N2.C3.R0.S13: PI = 33
N4.C2.R2.S15: PI = 39
N6.C0.D1.R1.S00: RxDqsDelay = 035
N0.C0.D1.R0.S13: RxDqsDelay = 036
N2.C3.R0.S14: PI = 35
N4.C2.R2.S16: PI = 37
N6.C0.D1.R1.S01: RdDqDqs FSM results: Left = 07, Right = 63, center = 35
N0.C0.D1.R0.S14: RdDqDqs FSM results: Left = 07, Right = 63, center = 35
N2.C3.R0.S15: PI = 35
N4.C2.R2.S17: PI = 37
N6.C0.D1.R1.S01: RxDqsDelay = 035
N0.C0.D1.R0.S14: RxDqsDelay = 035
N2.C3.R0.S16: PI = 36
STOP_DATA_RX_DQS
N6.C0.D1.R1.S02: RdDqDqs FSM results: Left = 09, Right = 63, center = 36
N0.C0.D1.R0.S15: RdDqDqs FSM results: Left = 04, Right = 63, center = 33
N2.C3.R0.S17: PI = 31
N4.C3.D0.R0.S00: RdDqDqs FSM results: Left = 13, Right = 63, center = 38
N6.C0.D1.R1.S02: RxDqsDelay = 036
N0.C0.D1.R0.S15: RxDqsDelay = 033
N2.C3.R0.S00: PI = 36
N4.C3.D0.R0.S00: RxDqsDelay = 038
N6.C0.D1.R1.S03: RdDqDqs FSM results: Left = 07, Right = 63, center = 35
N0.C0.D1.R0.S16: RdDqDqs FSM results: Left = 05, Right = 63, center = 34
N2.C3.R0.S01: PI = 33
N4.C3.D0.R0.S01: RdDqDqs FSM results: Left = 17, Right = 63, center = 40
N6.C0.D1.R1.S03: RxDqsDelay = 035
N0.C0.D1.R0.S16: RxDqsDelay = 034
N2.C3.R0.S02: PI = 36
N4.C3.D0.R0.S01: RxDqsDelay = 040
N6.C0.D1.R1.S04: RdDqDqs FSM results: Left = 07, Right = 63, center = 35
N0.C0.D1.R0.S17: RdDqDqs FSM results: Left = 07, Right = 63, center = 35
N2.C3.R0.S03: PI = 34
N4.C3.D0.R0.S02: RdDqDqs FSM results: Left = 10, Right = 63, center = 36
N6.C0.D1.R1.S04: RxDqsDelay = 035
N0.C0.D1.R0.S17: RxDqsDelay = 035
N2.C3.R0.S04: PI = 34
N4.C3.D0.R0.S02: RxDqsDelay = 036
N6.C0.D1.R1.S05: RdDqDqs FSM results: Left = 08, Right = 63, center = 35
N0.C0.D1.R1.S00: RdDqDqs FSM results: Left = 08, Right = 63, center = 35
N2.C3.R0.S05: PI = 35
N4.C3.D0.R0.S03: RdDqDqs FSM results: Left = 11, Right = 63, center = 37
N6.C0.D1.R1.S05: RxDqsDelay = 035
N0.C0.D1.R1.S00: RxDqsDelay = 035
N2.C3.R0.S06: PI = 36
N4.C3.D0.R0.S03: RxDqsDelay = 037
N6.C0.D1.R1.S06: RdDqDqs FSM results: Left = 07, Right = 63, center = 35
N0.C0.D1.R1.S01: RdDqDqs FSM results: Left = 07, Right = 63, center = 35
N2.C3.R0.S07: PI = 35
N4.C3.D0.R0.S04: RdDqDqs FSM results: Left = 16, Right = 63, center = 39
N6.C0.D1.R1.S06: RxDqsDelay = 035
N0.C0.D1.R1.S01: RxDqsDelay = 035
N2.C3.R0.S08: PI = 33
N4.C3.D0.R0.S04: RxDqsDelay = 039
N6.C0.D1.R1.S07: RdDqDqs FSM results: Left = 10, Right = 63, center = 36
N0.C0.D1.R1.S02: RdDqDqs FSM results: Left = 08, Right = 63, center = 35
N2.C3.R0.S09: PI = 35
N4.C3.D0.R0.S05: RdDqDqs FSM results: Left = 14, Right = 63, center = 38
N6.C0.D1.R1.S07: RxDqsDelay = 036
N0.C0.D1.R1.S02: RxDqsDelay = 035
N2.C3.R0.S10: PI = 33
N4.C3.D0.R0.S05: RxDqsDelay = 038
N6.C0.D1.R1.S08: RdDqDqs FSM results: Left = 10, Right = 63, center = 36
N0.C0.D1.R1.S03: RdDqDqs FSM results: Left = 07, Right = 63, center = 35
N2.C3.R0.S11: PI = 35
N4.C3.D0.R0.S06: RdDqDqs FSM results: Left = 16, Right = 63, center = 39
N6.C0.D1.R1.S08: RxDqsDelay = 036
N0.C0.D1.R1.S03: RxDqsDelay = 035
N2.C3.R0.S12: PI = 33
N4.C3.D0.R0.S06: RxDqsDelay = 039
N6.C0.D1.R1.S09: RdDqDqs FSM results: Left = 08, Right = 63, center = 35
N0.C0.D1.R1.S04: RdDqDqs FSM results: Left = 08, Right = 63, center = 35
N2.C3.R0.S13: PI = 33
N4.C3.D0.R0.S07: RdDqDqs FSM results: Left = 11, Right = 63, center = 37
N6.C0.D1.R1.S09: RxDqsDelay = 035
N0.C0.D1.R1.S04: RxDqsDelay = 035
N2.C3.R0.S14: PI = 35
N4.C3.D0.R0.S07: RxDqsDelay = 037
N6.C0.D1.R1.S10: RdDqDqs FSM results: Left = 06, Right = 63, center = 34
N0.C0.D1.R1.S05: RdDqDqs FSM results: Left = 10, Right = 63, center = 36
N2.C3.R0.S15: PI = 35
N4.C3.D0.R0.S08: RdDqDqs FSM results: Left = 07, Right = 63, center = 35
N6.C0.D1.R1.S10: RxDqsDelay = 034
N0.C0.D1.R1.S05: RxDqsDelay = 036
N2.C3.R0.S16: PI = 36
N4.C3.D0.R0.S08: RxDqsDelay = 035
N6.C0.D1.R1.S11: RdDqDqs FSM results: Left = 08, Right = 63, center = 35
N0.C0.D1.R1.S06: RdDqDqs FSM results: Left = 10, Right = 63, center = 36
N2.C3.R0.S17: PI = 31
N4.C3.D0.R0.S09: RdDqDqs FSM results: Left = 13, Right = 63, center = 38
N6.C0.D1.R1.S11: RxDqsDelay = 035
N0.C0.D1.R1.S06: RxDqsDelay = 036
N2.C3.R2.S00: PI = 38
N4.C3.D0.R0.S09: RxDqsDelay = 038
N6.C0.D1.R1.S12: RdDqDqs FSM results: Left = 07, Right = 63, center = 35
N0.C0.D1.R1.S07: RdDqDqs FSM results: Left = 09, Right = 63, center = 36
N2.C3.R2.S01: PI = 34
N4.C3.D0.R0.S10: RdDqDqs FSM results: Left = 10, Right = 63, center = 36
N6.C0.D1.R1.S12: RxDqsDelay = 035
N0.C0.D1.R1.S07: RxDqsDelay = 036
N2.C3.R2.S02: PI = 37
N4.C3.D0.R0.S10: RxDqsDelay = 036
N6.C0.D1.R1.S13: RdDqDqs FSM results: Left = 09, Right = 63, center = 36
N0.C0.D1.R1.S08: RdDqDqs FSM results: Left = 06, Right = 63, center = 34
N2.C3.R2.S03: PI = 35
N4.C3.D0.R0.S11: RdDqDqs FSM results: Left = 10, Right = 63, center = 36
N6.C0.D1.R1.S13: RxDqsDelay = 036
N0.C0.D1.R1.S08: RxDqsDelay = 034
N2.C3.R2.S04: PI = 36
N4.C3.D0.R0.S11: RxDqsDelay = 036
N6.C0.D1.R1.S14: RdDqDqs FSM results: Left = 10, Right = 63, center = 36
N0.C0.D1.R1.S09: RdDqDqs FSM results: Left = 11, Right = 63, center = 37
N2.C3.R2.S05: PI = 36
N4.C3.D0.R0.S12: RdDqDqs FSM results: Left = 12, Right = 63, center = 37
N6.C0.D1.R1.S14: RxDqsDelay = 036
N0.C0.D1.R1.S09: RxDqsDelay = 037
N2.C3.R2.S06: PI = 37
N4.C3.D0.R0.S12: RxDqsDelay = 037
N6.C0.D1.R1.S15: RdDqDqs FSM results: Left = 11, Right = 63, center = 37
N0.C0.D1.R1.S10: RdDqDqs FSM results: Left = 09, Right = 63, center = 36
N2.C3.R2.S07: PI = 37
N4.C3.D0.R0.S13: RdDqDqs FSM results: Left = 09, Right = 63, center = 36
N6.C0.D1.R1.S15: RxDqsDelay = 037
N0.C0.D1.R1.S10: RxDqsDelay = 036
N2.C3.R2.S08: PI = 36
N4.C3.D0.R0.S13: RxDqsDelay = 036
N6.C0.D1.R1.S16: RdDqDqs FSM results: Left = 11, Right = 63, center = 37
N0.C0.D1.R1.S11: RdDqDqs FSM results: Left = 06, Right = 63, center = 34
N2.C3.R2.S09: PI = 37
N4.C3.D0.R0.S14: RdDqDqs FSM results: Left = 13, Right = 63, center = 38
N6.C0.D1.R1.S16: RxDqsDelay = 037
N0.C0.D1.R1.S11: RxDqsDelay = 034
N2.C3.R2.S10: PI = 35
N4.C3.D0.R0.S14: RxDqsDelay = 038
N6.C0.D1.R1.S17: RdDqDqs FSM results: Left = 10, Right = 63, center = 36
N0.C0.D1.R1.S12: RdDqDqs FSM results: Left = 08, Right = 63, center = 35
N2.C3.R2.S11: PI = 36
N4.C3.D0.R0.S15: RdDqDqs FSM results: Left = 13, Right = 63, center = 38
N6.C0.D1.R1.S17: RxDqsDelay = 036
N0.C0.D1.R1.S12: RxDqsDelay = 035
N2.C3.R2.S12: PI = 35
N4.C3.D0.R0.S15: RxDqsDelay = 038
START_DATA_RX_DQS
N0.C0.D1.R1.S13: RdDqDqs FSM results: Left = 09, Right = 63, center = 36
N2.C3.R2.S13: PI = 35
N4.C3.D0.R0.S16: RdDqDqs FSM results: Left = 09, Right = 63, center = 36
N6.C0.R0.S00: PI = 31
N0.C0.D1.R1.S13: RxDqsDelay = 036
N2.C3.R2.S14: PI = 36
N4.C3.D0.R0.S16: RxDqsDelay = 036
N6.C0.R0.S01: PI = 33
N0.C0.D1.R1.S14: RdDqDqs FSM results: Left = 06, Right = 63, center = 34
N2.C3.R2.S15: PI = 36
N4.C3.D0.R0.S17: RdDqDqs FSM results: Left = 11, Right = 63, center = 37
N6.C0.R0.S02: PI = 33
N0.C0.D1.R1.S14: RxDqsDelay = 034
N2.C3.R2.S16: PI = 37
N4.C3.D0.R0.S17: RxDqsDelay = 037
N6.C0.R0.S03: PI = 33
N0.C0.D1.R1.S15: RdDqDqs FSM results: Left = 04, Right = 63, center = 33
N2.C3.R2.S17: PI = 35
N4.C3.D0.R1.S00: RdDqDqs FSM results: Left = 12, Right = 63, center = 37
N6.C0.R0.S04: PI = 33
N0.C0.D1.R1.S15: RxDqsDelay = 033
N2.C3.R2.S00: PI = 38
N4.C3.D0.R1.S00: RxDqsDelay = 037
N6.C0.R0.S05: PI = 34
N0.C0.D1.R1.S16: RdDqDqs FSM results: Left = 05, Right = 63, center = 34
N2.C3.R2.S01: PI = 34
N4.C3.D0.R1.S01: RdDqDqs FSM results: Left = 16, Right = 63, center = 39
N6.C0.R0.S06: PI = 33
N0.C0.D1.R1.S16: RxDqsDelay = 034
N2.C3.R2.S02: PI = 37
N4.C3.D0.R1.S01: RxDqsDelay = 039
N6.C0.R0.S07: PI = 33
N0.C0.D1.R1.S17: RdDqDqs FSM results: Left = 07, Right = 63, center = 35
N2.C3.R2.S03: PI = 35
N4.C3.D0.R1.S02: RdDqDqs FSM results: Left = 10, Right = 63, center = 36
N6.C0.R0.S08: PI = 34
N0.C0.D1.R1.S17: RxDqsDelay = 035
N2.C3.R2.S04: PI = 36
N4.C3.D0.R1.S02: RxDqsDelay = 036
N6.C0.R0.S09: PI = 33
START_DATA_RX_DQS
N2.C3.R2.S05: PI = 36
N4.C3.D0.R1.S03: RdDqDqs FSM results: Left = 10, Right = 63, center = 36
N6.C0.R0.S10: PI = 30
N0.C0.R0.S00: PI = 33
N2.C3.R2.S06: PI = 37
N4.C3.D0.R1.S03: RxDqsDelay = 036
N6.C0.R0.S11: PI = 33
N0.C0.R0.S01: PI = 33
N2.C3.R2.S07: PI = 37
N4.C3.D0.R1.S04: RdDqDqs FSM results: Left = 15, Right = 63, center = 39
N6.C0.R0.S12: PI = 33
N0.C0.R0.S02: PI = 33
N2.C3.R2.S08: PI = 36
N4.C3.D0.R1.S04: RxDqsDelay = 039
N6.C0.R0.S13: PI = 33
N0.C0.R0.S03: PI = 33
N2.C3.R2.S09: PI = 37
N4.C3.D0.R1.S05: RdDqDqs FSM results: Left = 12, Right = 63, center = 37
N6.C0.R0.S14: PI = 34
N0.C0.R0.S04: PI = 34
N2.C3.R2.S10: PI = 35
N4.C3.D0.R1.S05: RxDqsDelay = 037
N6.C0.R0.S15: PI = 34
N0.C0.R0.S05: PI = 34
N2.C3.R2.S11: PI = 36
N4.C3.D0.R1.S06: RdDqDqs FSM results: Left = 16, Right = 63, center = 39
N6.C0.R0.S16: PI = 35
N0.C0.R0.S06: PI = 33
N2.C3.R2.S12: PI = 35
N4.C3.D0.R1.S06: RxDqsDelay = 039
N6.C0.R0.S17: PI = 35
N0.C0.R0.S07: PI = 34
N2.C3.R2.S13: PI = 35
N4.C3.D0.R1.S07: RdDqDqs FSM results: Left = 11, Right = 63, center = 37
N6.C0.R0.S00: PI = 31
N0.C0.R0.S08: PI = 33
N2.C3.R2.S14: PI = 36
N4.C3.D0.R1.S07: RxDqsDelay = 037
N6.C0.R0.S01: PI = 33
N0.C0.R0.S09: PI = 33
N2.C3.R2.S15: PI = 36
N4.C3.D0.R1.S08: RdDqDqs FSM results: Left = 07, Right = 63, center = 35
N6.C0.R0.S02: PI = 33
N0.C0.R0.S10: PI = 33
N2.C3.R2.S16: PI = 37
N4.C3.D0.R1.S08: RxDqsDelay = 035
N6.C0.R0.S03: PI = 33
N0.C0.R0.S11: PI = 33
N2.C3.R2.S17: PI = 35
N4.C3.D0.R1.S09: RdDqDqs FSM results: Left = 12, Right = 63, center = 37
N6.C0.R0.S04: PI = 33
N0.C0.R0.S12: PI = 33
STOP_DATA_RX_DQS
N4.C3.D0.R1.S09: RxDqsDelay = 037
N6.C0.R0.S05: PI = 34
N0.C0.R0.S13: PI = 34
N2: RunTrainStep: Final status = 0
N4.C3.D0.R1.S10: RdDqDqs FSM results: Left = 09, Right = 63, center = 36
N6.C0.R0.S06: PI = 33
N0.C0.R0.S14: PI = 33

END - Basic Read DQ/DQS Training       Time         13784 ms
N4.C3.D0.R1.S10: RxDqsDelay = 036
N6.C0.R0.S07: PI = 33
N0.C0.R0.S15: PI = 32

START - Basic Receive Enable Training
N4.C3.D0.R1.S11: RdDqDqs FSM results: Left = 10, Right = 63, center = 36
N6.C0.R0.S08: PI = 34
N0.C0.R0.S16: PI = 32
N2.C0: QCRM debug: extraRcvEnLatency = 0
N4.C3.D0.R1.S11: RxDqsDelay = 036
N6.C0.R0.S09: PI = 33
N0.C0.R0.S17: PI = 34
N2.C0: SettingForTrainingStep: RdCmd2RcvEnLatency = 10, RdPtrOffsetRcvEn = 4
N4.C3.D0.R1.S12: RdDqDqs FSM results: Left = 11, Right = 63, center = 37
N6.C0.R0.S10: PI = 30
N0.C0.R0.S00: PI = 33
N2.C1: QCRM debug: extraRcvEnLatency = 0
N4.C3.D0.R1.S12: RxDqsDelay = 037
N6.C0.R0.S11: PI = 33
N0.C0.R0.S01: PI = 33
N2.C1: SettingForTrainingStep: RdCmd2RcvEnLatency = 10, RdPtrOffsetRcvEn = 4
N4.C3.D0.R1.S13: RdDqDqs FSM results: Left = 09, Right = 63, center = 36
N6.C0.R0.S12: PI = 33
N0.C0.R0.S02: PI = 33
N2.C2: QCRM debug: extraRcvEnLatency = 0
N4.C3.D0.R1.S13: RxDqsDelay = 036
N6.C0.R0.S13: PI = 33
N0.C0.R0.S03: PI = 33
N2.C2: SettingForTrainingStep: RdCmd2RcvEnLatency = 10, RdPtrOffsetRcvEn = 4
N4.C3.D0.R1.S14: RdDqDqs FSM results: Left = 11, Right = 63, center = 37
N6.C0.R0.S14: PI = 34
N0.C0.R0.S04: PI = 34
N2.C3: QCRM debug: extraRcvEnLatency = 0
N4.C3.D0.R1.S14: RxDqsDelay = 037
N6.C0.R0.S15: PI = 34
N0.C0.R0.S05: PI = 34
N2.C3: SettingForTrainingStep: RdCmd2RcvEnLatency = 10, RdPtrOffsetRcvEn = 4
N4.C3.D0.R1.S15: RdDqDqs FSM results: Left = 12, Right = 63, center = 37
N6.C0.R0.S16: PI = 35
N0.C0.R0.S06: PI = 33
N2.C0.D0.R0: RcvEnFine: Initial RdCmd2RcvEnLatency = 10, Initial RdPtrOffsetRcvEn = 4
N4.C3.D0.R1.S15: RxDqsDelay = 037
N6.C0.R0.S17: PI = 35
N0.C0.R0.S07: PI = 34
N4.C3.D0.R1.S16: RdDqDqs FSM results: Left = 09, Right = 63, center = 36
N6.C0.R2.S00: PI = 35
N0.C0.R0.S08: PI = 33
N2.C0.D0.R0.S00: Rcv En Fine Value = 270
N4.C3.D0.R1.S16: RxDqsDelay = 036
N6.C0.R2.S01: PI = 35
N0.C0.R0.S09: PI = 33
N2.C0.D0.R0.S01: Rcv En Fine Value = 380
N4.C3.D0.R1.S17: RdDqDqs FSM results: Left = 11, Right = 63, center = 37
N6.C0.R2.S02: PI = 36
N0.C0.R0.S10: PI = 33
N2.C0.D0.R0.S02: Rcv En Fine Value = 354
N4.C3.D0.R1.S17: RxDqsDelay = 037
N6.C0.R2.S03: PI = 34
N0.C0.R0.S11: PI = 33
N2.C0.D0.R0.S03: Rcv En Fine Value = 328
N4.C3.D1.R0.S00: RdDqDqs FSM results: Left = 18, Right = 63, center = 40
N6.C0.R2.S04: PI = 35
N0.C0.R0.S12: PI = 33
N2.C0.D0.R0.S04: Rcv En Fine Value = 321
N4.C3.D1.R0.S00: RxDqsDelay = 040
N6.C0.R2.S05: PI = 35
N0.C0.R0.S13: PI = 34
N2.C0.D0.R0.S05: Rcv En Fine Value = 348
N4.C3.D1.R0.S01: RdDqDqs FSM results: Left = 20, Right = 63, center = 41
N6.C0.R2.S06: PI = 35
N0.C0.R0.S14: PI = 33
N2.C0.D0.R0.S06: Rcv En Fine Value = 377
N4.C3.D1.R0.S01: RxDqsDelay = 041
N6.C0.R2.S07: PI = 36
N0.C0.R0.S15: PI = 32
N2.C0.D0.R0.S07: Rcv En Fine Value = 272
N4.C3.D1.R0.S02: RdDqDqs FSM results: Left = 13, Right = 63, center = 38
N6.C0.R2.S08: PI = 36
N0.C0.R0.S16: PI = 32
N2.C0.D0.R0.S08: Rcv En Fine Value = 319
N4.C3.D1.R0.S02: RxDqsDelay = 038
N6.C0.R2.S09: PI = 35
N0.C0.R0.S17: PI = 34
N2.C0.D0.R0.S09: Rcv En Fine Value = 270
N4.C3.D1.R0.S03: RdDqDqs FSM results: Left = 15, Right = 63, center = 39
N6.C0.R2.S10: PI = 34
N0.C0.R2.S00: PI = 35
N2.C0.D0.R0.S10: Rcv En Fine Value = 381
N4.C3.D1.R0.S03: RxDqsDelay = 039
N6.C0.R2.S11: PI = 35
N0.C0.R2.S01: PI = 35
N2.C0.D0.R0.S11: Rcv En Fine Value = 353
N4.C3.D1.R0.S04: RdDqDqs FSM results: Left = 20, Right = 63, center = 41
N6.C0.R2.S12: PI = 35
N0.C0.R2.S02: PI = 35
N2.C0.D0.R0.S12: Rcv En Fine Value = 331
N4.C3.D1.R0.S04: RxDqsDelay = 041
N6.C0.R2.S13: PI = 35
N0.C0.R2.S03: PI = 35
N2.C0.D0.R0.S13: Rcv En Fine Value = 319
N4.C3.D1.R0.S05: RdDqDqs FSM results: Left = 18, Right = 63, center = 40
N6.C0.R2.S14: PI = 36
N0.C0.R2.S04: PI = 35
N2.C0.D0.R0.S14: Rcv En Fine Value = 345
N4.C3.D1.R0.S05: RxDqsDelay = 040
N6.C0.R2.S15: PI = 36
N0.C0.R2.S05: PI = 36
N2.C0.D0.R0.S15: Rcv En Fine Value = 377
N4.C3.D1.R0.S06: RdDqDqs FSM results: Left = 18, Right = 63, center = 40
N6.C0.R2.S16: PI = 37
N0.C0.R2.S06: PI = 36
N2.C0.D0.R0.S16: Rcv En Fine Value = 272
N4.C3.D1.R0.S06: RxDqsDelay = 040
N6.C0.R2.S17: PI = 36
N0.C0.R2.S07: PI = 35
N2.C0.D0.R0.S17: Rcv En Fine Value = 317
N4.C3.D1.R0.S07: RdDqDqs FSM results: Left = 14, Right = 63, center = 38
N6.C0.R2.S00: PI = 35
N0.C0.R2.S08: PI = 34
N2.C0.D0.R0: Starting preamble search lower nibbles
N4.C3.D1.R0.S07: RxDqsDelay = 038
N6.C0.R2.S01: PI = 35
N0.C0.R2.S09: PI = 36
N2.C0.D0.R0.S00: PI = 014, PtrOffset = 004
N4.C3.D1.R0.S08: RdDqDqs FSM results: Left = 10, Right = 63, center = 36
N6.C0.R2.S02: PI = 36
N0.C0.R2.S10: PI = 35
N2.C0.D0.R0.S01: PI = 060, PtrOffset = 005
N4.C3.D1.R0.S08: RxDqsDelay = 036
N6.C0.R2.S03: PI = 34
N0.C0.R2.S11: PI = 34
N2.C0.D0.R0.S02: PI = 034, PtrOffset = 005
N4.C3.D1.R0.S09: RdDqDqs FSM results: Left = 16, Right = 63, center = 39
N6.C0.R2.S04: PI = 35
N0.C0.R2.S12: PI = 35
N2.C0.D0.R0.S03: PI = 008, PtrOffset = 005
N4.C3.D1.R0.S09: RxDqsDelay = 039
N6.C0.R2.S05: PI = 35
N0.C0.R2.S13: PI = 36
N2.C0.D0.R0.S04: PI = 001, PtrOffset = 005
N4.C3.D1.R0.S10: RdDqDqs FSM results: Left = 15, Right = 63, center = 39
N6.C0.R2.S06: PI = 35
N0.C0.R2.S14: PI = 34
N2.C0.D0.R0.S05: PI = 028, PtrOffset = 005
N4.C3.D1.R0.S10: RxDqsDelay = 039
N6.C0.R2.S07: PI = 36
N0.C0.R2.S15: PI = 33
N2.C0.D0.R0.S06: PI = 057, PtrOffset = 005
N4.C3.D1.R0.S11: RdDqDqs FSM results: Left = 12, Right = 63, center = 37
N6.C0.R2.S08: PI = 36
N0.C0.R2.S16: PI = 34
N2.C0.D0.R0.S07: PI = 016, PtrOffset = 004
N4.C3.D1.R0.S11: RxDqsDelay = 037
N6.C0.R2.S09: PI = 35
N0.C0.R2.S17: PI = 35
N2.C0.D0.R0.S08: PI = 063, PtrOffset = 004
N4.C3.D1.R0.S12: RdDqDqs FSM results: Left = 15, Right = 63, center = 39
N6.C0.R2.S10: PI = 34
N0.C0.R2.S00: PI = 35
N2.C0.D0.R0.S00: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N4.C3.D1.R0.S12: RxDqsDelay = 039
N6.C0.R2.S11: PI = 35
N0.C0.R2.S01: PI = 35
N2.C0.D0.R0.S01: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N4.C3.D1.R0.S13: RdDqDqs FSM results: Left = 12, Right = 63, center = 37
N6.C0.R2.S12: PI = 35
N0.C0.R2.S02: PI = 35
N2.C0.D0.R0.S02: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N4.C3.D1.R0.S13: RxDqsDelay = 037
N6.C0.R2.S13: PI = 35
N0.C0.R2.S03: PI = 35
N2.C0.D0.R0.S03: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N4.C3.D1.R0.S14: RdDqDqs FSM results: Left = 16, Right = 63, center = 39
N6.C0.R2.S14: PI = 36
N0.C0.R2.S04: PI = 35
N2.C0.D0.R0.S04: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N4.C3.D1.R0.S14: RxDqsDelay = 039
N6.C0.R2.S15: PI = 36
N0.C0.R2.S05: PI = 36
N2.C0.D0.R0.S05: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N4.C3.D1.R0.S15: RdDqDqs FSM results: Left = 17, Right = 63, center = 40
N6.C0.R2.S16: PI = 37
N0.C0.R2.S06: PI = 36
N2.C0.D0.R0.S06: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N4.C3.D1.R0.S15: RxDqsDelay = 040
N6.C0.R2.S17: PI = 36
N0.C0.R2.S07: PI = 35
N2.C0.D0.R0.S07: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N4.C3.D1.R0.S16: RdDqDqs FSM results: Left = 12, Right = 63, center = 37
STOP_DATA_RX_DQS
N0.C0.R2.S08: PI = 34
N2.C0.D0.R0.S08: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N4.C3.D1.R0.S16: RxDqsDelay = 037
N6.C1.D0.R0.S00: RdDqDqs FSM results: Left = 04, Right = 60, center = 32
N0.C0.R2.S09: PI = 36
N2.C0.D0.R0.S00: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N4.C3.D1.R0.S17: RdDqDqs FSM results: Left = 16, Right = 63, center = 39
N6.C1.D0.R0.S00: RxDqsDelay = 032
N0.C0.R2.S10: PI = 35
N2.C0.D0.R0.S01: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N4.C3.D1.R0.S17: RxDqsDelay = 039
N6.C1.D0.R0.S01: RdDqDqs FSM results: Left = 04, Right = 63, center = 33
N0.C0.R2.S11: PI = 34
N2.C0.D0.R0.S02: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N4.C3.D1.R1.S00: RdDqDqs FSM results: Left = 17, Right = 63, center = 40
N6.C1.D0.R0.S01: RxDqsDelay = 033
N0.C0.R2.S12: PI = 35
N2.C0.D0.R0.S03: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N4.C3.D1.R1.S00: RxDqsDelay = 040
N6.C1.D0.R0.S02: RdDqDqs FSM results: Left = 03, Right = 61, center = 32
N0.C0.R2.S13: PI = 36
N2.C0.D0.R0.S04: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N4.C3.D1.R1.S01: RdDqDqs FSM results: Left = 20, Right = 63, center = 41
N6.C1.D0.R0.S02: RxDqsDelay = 032
N0.C0.R2.S14: PI = 34
N2.C0.D0.R0.S05: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N4.C3.D1.R1.S01: RxDqsDelay = 041
N6.C1.D0.R0.S03: RdDqDqs FSM results: Left = 03, Right = 63, center = 33
N0.C0.R2.S15: PI = 33
N2.C0.D0.R0.S06: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N4.C3.D1.R1.S02: RdDqDqs FSM results: Left = 13, Right = 63, center = 38
N6.C1.D0.R0.S03: RxDqsDelay = 033
N0.C0.R2.S16: PI = 34
N2.C0.D0.R0.S07: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N4.C3.D1.R1.S02: RxDqsDelay = 038
N6.C1.D0.R0.S04: RdDqDqs FSM results: Left = 05, Right = 63, center = 34
N0.C0.R2.S17: PI = 35
N2.C0.D0.R0.S08: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N4.C3.D1.R1.S03: RdDqDqs FSM results: Left = 16, Right = 63, center = 39
N6.C1.D0.R0.S04: RxDqsDelay = 034
STOP_DATA_RX_DQS
N2.C0.D0.R0.S00: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N4.C3.D1.R1.S03: RxDqsDelay = 039
N6.C1.D0.R0.S05: RdDqDqs FSM results: Left = 05, Right = 63, center = 34
N0.C1.D0.R0.S00: RdDqDqs FSM results: Left = 02, Right = 63, center = 32
N2.C0.D0.R0.S01: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N4.C3.D1.R1.S04: RdDqDqs FSM results: Left = 19, Right = 63, center = 41
N6.C1.D0.R0.S05: RxDqsDelay = 034
N0.C1.D0.R0.S00: RxDqsDelay = 032
N2.C0.D0.R0.S02: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N4.C3.D1.R1.S04: RxDqsDelay = 041
N6.C1.D0.R0.S06: RdDqDqs FSM results: Left = 04, Right = 63, center = 33
N0.C1.D0.R0.S01: RdDqDqs FSM results: Left = 06, Right = 63, center = 34
N2.C0.D0.R0.S03: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N4.C3.D1.R1.S05: RdDqDqs FSM results: Left = 17, Right = 63, center = 40
N6.C1.D0.R0.S06: RxDqsDelay = 033
N0.C1.D0.R0.S01: RxDqsDelay = 034
N2.C0.D0.R0.S04: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N4.C3.D1.R1.S05: RxDqsDelay = 040
N6.C1.D0.R0.S07: RdDqDqs FSM results: Left = 05, Right = 63, center = 34
N0.C1.D0.R0.S02: RdDqDqs FSM results: Left = 06, Right = 63, center = 34
N2.C0.D0.R0.S05: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N4.C3.D1.R1.S06: RdDqDqs FSM results: Left = 20, Right = 63, center = 41
N6.C1.D0.R0.S07: RxDqsDelay = 034
N0.C1.D0.R0.S02: RxDqsDelay = 034
N2.C0.D0.R0.S06: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N4.C3.D1.R1.S06: RxDqsDelay = 041
N6.C1.D0.R0.S08: RdDqDqs FSM results: Left = 03, Right = 63, center = 33
N0.C1.D0.R0.S03: RdDqDqs FSM results: Left = 04, Right = 63, center = 33
N2.C0.D0.R0.S07: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N4.C3.D1.R1.S07: RdDqDqs FSM results: Left = 15, Right = 63, center = 39
N6.C1.D0.R0.S08: RxDqsDelay = 033
N0.C1.D0.R0.S03: RxDqsDelay = 033
N2.C0.D0.R0.S08: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N4.C3.D1.R1.S07: RxDqsDelay = 039
N6.C1.D0.R0.S09: RdDqDqs FSM results: Left = 07, Right = 63, center = 35
N0.C1.D0.R0.S04: RdDqDqs FSM results: Left = 02, Right = 63, center = 32
N2.C0.D0.R0.S00: Preamble found at Latency = 008
N4.C3.D1.R1.S08: RdDqDqs FSM results: Left = 11, Right = 63, center = 37
N6.C1.D0.R0.S09: RxDqsDelay = 035
N0.C1.D0.R0.S04: RxDqsDelay = 032
N2.C0.D0.R0.S07: Preamble found at Latency = 008
N4.C3.D1.R1.S08: RxDqsDelay = 037
N6.C1.D0.R0.S10: RdDqDqs FSM results: Left = 04, Right = 63, center = 33
N0.C1.D0.R0.S05: RdDqDqs FSM results: Left = 05, Right = 63, center = 34
N2.C0.D0.R0.S00: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N4.C3.D1.R1.S09: RdDqDqs FSM results: Left = 16, Right = 63, center = 39
N6.C1.D0.R0.S10: RxDqsDelay = 033
N0.C1.D0.R0.S05: RxDqsDelay = 034
N2.C0.D0.R0.S01: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N4.C3.D1.R1.S09: RxDqsDelay = 039
N6.C1.D0.R0.S11: RdDqDqs FSM results: Left = 03, Right = 63, center = 33
N0.C1.D0.R0.S06: RdDqDqs FSM results: Left = 05, Right = 63, center = 34
N2.C0.D0.R0.S02: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N4.C3.D1.R1.S10: RdDqDqs FSM results: Left = 14, Right = 63, center = 38
N6.C1.D0.R0.S11: RxDqsDelay = 033
N0.C1.D0.R0.S06: RxDqsDelay = 034
N2.C0.D0.R0.S03: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N4.C3.D1.R1.S10: RxDqsDelay = 038
N6.C1.D0.R0.S12: RdDqDqs FSM results: Left = 04, Right = 63, center = 33
N0.C1.D0.R0.S07: RdDqDqs FSM results: Left = 05, Right = 63, center = 34
N2.C0.D0.R0.S04: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N4.C3.D1.R1.S11: RdDqDqs FSM results: Left = 12, Right = 63, center = 37
N6.C1.D0.R0.S12: RxDqsDelay = 033
N0.C1.D0.R0.S07: RxDqsDelay = 034
N2.C0.D0.R0.S05: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N4.C3.D1.R1.S11: RxDqsDelay = 037
N6.C1.D0.R0.S13: RdDqDqs FSM results: Left = 05, Right = 63, center = 34
N0.C1.D0.R0.S08: RdDqDqs FSM results: Left = 02, Right = 61, center = 31
N2.C0.D0.R0.S06: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N4.C3.D1.R1.S12: RdDqDqs FSM results: Left = 15, Right = 63, center = 39
N6.C1.D0.R0.S13: RxDqsDelay = 034
N0.C1.D0.R0.S08: RxDqsDelay = 031
N2.C0.D0.R0.S07: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N4.C3.D1.R1.S12: RxDqsDelay = 039
N6.C1.D0.R0.S14: RdDqDqs FSM results: Left = 05, Right = 63, center = 34
N0.C1.D0.R0.S09: RdDqDqs FSM results: Left = 04, Right = 63, center = 33
N2.C0.D0.R0.S08: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N4.C3.D1.R1.S13: RdDqDqs FSM results: Left = 12, Right = 63, center = 37
N6.C1.D0.R0.S14: RxDqsDelay = 034
N0.C1.D0.R0.S09: RxDqsDelay = 033
N2.C0.D0.R0.S01: Preamble found at Latency = 007
N4.C3.D1.R1.S13: RxDqsDelay = 037
N6.C1.D0.R0.S15: RdDqDqs FSM results: Left = 07, Right = 59, center = 33
N0.C1.D0.R0.S10: RdDqDqs FSM results: Left = 05, Right = 63, center = 34
N2.C0.D0.R0.S02: Preamble found at Latency = 007
N4.C3.D1.R1.S14: RdDqDqs FSM results: Left = 16, Right = 63, center = 39
N6.C1.D0.R0.S15: RxDqsDelay = 033
N0.C1.D0.R0.S10: RxDqsDelay = 034
N2.C0.D0.R0.S03: Preamble found at Latency = 007
N4.C3.D1.R1.S14: RxDqsDelay = 039
N6.C1.D0.R0.S16: RdDqDqs FSM results: Left = 07, Right = 63, center = 35
N0.C1.D0.R0.S11: RdDqDqs FSM results: Left = 02, Right = 63, center = 32
N2.C0.D0.R0.S04: Preamble found at Latency = 007
N4.C3.D1.R1.S15: RdDqDqs FSM results: Left = 18, Right = 63, center = 40
N6.C1.D0.R0.S16: RxDqsDelay = 035
N0.C1.D0.R0.S11: RxDqsDelay = 032
N2.C0.D0.R0.S05: Preamble found at Latency = 007
N4.C3.D1.R1.S15: RxDqsDelay = 040
N6.C1.D0.R0.S17: RdDqDqs FSM results: Left = 03, Right = 63, center = 33
N0.C1.D0.R0.S12: RdDqDqs FSM results: Left = 04, Right = 63, center = 33
N2.C0.D0.R0.S06: Preamble found at Latency = 007
N4.C3.D1.R1.S16: RdDqDqs FSM results: Left = 11, Right = 63, center = 37
N6.C1.D0.R0.S17: RxDqsDelay = 033
N0.C1.D0.R0.S12: RxDqsDelay = 033
N2.C0.D0.R0.S08: Preamble found at Latency = 007
N4.C3.D1.R1.S16: RxDqsDelay = 037
N6.C1.D0.R1.S00: RdDqDqs FSM results: Left = 03, Right = 63, center = 33
N0.C1.D0.R0.S13: RdDqDqs FSM results: Left = 03, Right = 63, center = 33
N2.C0.D0.R0.S00: Total Receive Enable Delay = 1326
N4.C3.D1.R1.S17: RdDqDqs FSM results: Left = 15, Right = 63, center = 39
N6.C1.D0.R1.S00: RxDqsDelay = 033
N0.C1.D0.R0.S13: RxDqsDelay = 033
N2.C0.D0.R0.S01: Total Receive Enable Delay = 1308
N4.C3.D1.R1.S17: RxDqsDelay = 039
N6.C1.D0.R1.S01: RdDqDqs FSM results: Left = 07, Right = 63, center = 35
N0.C1.D0.R0.S14: RdDqDqs FSM results: Left = 06, Right = 63, center = 34
N2.C0.D0.R0.S02: Total Receive Enable Delay = 1282
START_DATA_RX_DQS
N6.C1.D0.R1.S01: RxDqsDelay = 035
N0.C1.D0.R0.S14: RxDqsDelay = 034
N2.C0.D0.R0.S03: Total Receive Enable Delay = 1256
N4.C3.R0.S00: PI = 37
N6.C1.D0.R1.S02: RdDqDqs FSM results: Left = 02, Right = 63, center = 32
N0.C1.D0.R0.S15: RdDqDqs FSM results: Left = 02, Right = 63, center = 32
N2.C0.D0.R0.S04: Total Receive Enable Delay = 1249
N4.C3.R0.S01: PI = 39
N6.C1.D0.R1.S02: RxDqsDelay = 032
N0.C1.D0.R0.S15: RxDqsDelay = 032
N2.C0.D0.R0.S05: Total Receive Enable Delay = 1276
N4.C3.R0.S02: PI = 36
N6.C1.D0.R1.S03: RdDqDqs FSM results: Left = 04, Right = 63, center = 33
N0.C1.D0.R0.S16: RdDqDqs FSM results: Left = 03, Right = 63, center = 33
N2.C0.D0.R0.S06: Total Receive Enable Delay = 1305
N4.C3.R0.S03: PI = 36
N6.C1.D0.R1.S03: RxDqsDelay = 033
N0.C1.D0.R0.S16: RxDqsDelay = 033
N2.C0.D0.R0.S07: Total Receive Enable Delay = 1328
N4.C3.R0.S04: PI = 39
N6.C1.D0.R1.S04: RdDqDqs FSM results: Left = 05, Right = 63, center = 34
N0.C1.D0.R0.S17: RdDqDqs FSM results: Left = 01, Right = 63, center = 32
N2.C0.D0.R0.S08: Total Receive Enable Delay = 1247
N4.C3.R0.S05: PI = 37
N6.C1.D0.R1.S04: RxDqsDelay = 034
N0.C1.D0.R0.S17: RxDqsDelay = 032
N2.C0.D0.R0: Starting preamble search upper nibbles
N4.C3.R0.S06: PI = 39
N6.C1.D0.R1.S05: RdDqDqs FSM results: Left = 06, Right = 63, center = 34
N0.C1.D0.R1.S00: RdDqDqs FSM results: Left = 03, Right = 63, center = 33
N2.C0.D0.R0.S09: PI = 014, PtrOffset = 004
N4.C3.R0.S07: PI = 37
N6.C1.D0.R1.S05: RxDqsDelay = 034
N0.C1.D0.R1.S00: RxDqsDelay = 033
N2.C0.D0.R0.S10: PI = 061, PtrOffset = 005
N4.C3.R0.S08: PI = 35
N6.C1.D0.R1.S06: RdDqDqs FSM results: Left = 04, Right = 63, center = 33
N0.C1.D0.R1.S01: RdDqDqs FSM results: Left = 05, Right = 63, center = 34
N2.C0.D0.R0.S11: PI = 033, PtrOffset = 005
N4.C3.R0.S09: PI = 37
N6.C1.D0.R1.S06: RxDqsDelay = 033
N0.C1.D0.R1.S01: RxDqsDelay = 034
N2.C0.D0.R0.S12: PI = 011, PtrOffset = 005
N4.C3.R0.S10: PI = 36
N6.C1.D0.R1.S07: RdDqDqs FSM results: Left = 05, Right = 63, center = 34
N0.C1.D0.R1.S02: RdDqDqs FSM results: Left = 05, Right = 63, center = 34
N2.C0.D0.R0.S13: PI = 063, PtrOffset = 004
N4.C3.R0.S11: PI = 36
N6.C1.D0.R1.S07: RxDqsDelay = 034
N0.C1.D0.R1.S02: RxDqsDelay = 034
N2.C0.D0.R0.S14: PI = 025, PtrOffset = 005
N4.C3.R0.S12: PI = 37
N6.C1.D0.R1.S08: RdDqDqs FSM results: Left = 03, Right = 63, center = 33
N0.C1.D0.R1.S03: RdDqDqs FSM results: Left = 03, Right = 63, center = 33
N2.C0.D0.R0.S15: PI = 057, PtrOffset = 005
N4.C3.R0.S13: PI = 36
N6.C1.D0.R1.S08: RxDqsDelay = 033
N0.C1.D0.R1.S03: RxDqsDelay = 033
N2.C0.D0.R0.S16: PI = 016, PtrOffset = 004
N4.C3.R0.S14: PI = 37
N6.C1.D0.R1.S09: RdDqDqs FSM results: Left = 07, Right = 63, center = 35
N0.C1.D0.R1.S04: RdDqDqs FSM results: Left = 02, Right = 63, center = 32
N2.C0.D0.R0.S17: PI = 061, PtrOffset = 004
N4.C3.R0.S15: PI = 37
N6.C1.D0.R1.S09: RxDqsDelay = 035
N0.C1.D0.R1.S04: RxDqsDelay = 032
N2.C0.D0.R0.S09: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N4.C3.R0.S16: PI = 36
N6.C1.D0.R1.S10: RdDqDqs FSM results: Left = 04, Right = 63, center = 33
N0.C1.D0.R1.S05: RdDqDqs FSM results: Left = 04, Right = 63, center = 33
N2.C0.D0.R0.S10: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N4.C3.R0.S17: PI = 37
N6.C1.D0.R1.S10: RxDqsDelay = 033
N0.C1.D0.R1.S05: RxDqsDelay = 033
N2.C0.D0.R0.S11: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N4.C3.R0.S00: PI = 37
N6.C1.D0.R1.S11: RdDqDqs FSM results: Left = 03, Right = 59, center = 31
N0.C1.D0.R1.S06: RdDqDqs FSM results: Left = 05, Right = 63, center = 34
N2.C0.D0.R0.S12: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N4.C3.R0.S01: PI = 39
N6.C1.D0.R1.S11: RxDqsDelay = 031
N0.C1.D0.R1.S06: RxDqsDelay = 034
N2.C0.D0.R0.S13: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N4.C3.R0.S02: PI = 36
N6.C1.D0.R1.S12: RdDqDqs FSM results: Left = 04, Right = 63, center = 33
N0.C1.D0.R1.S07: RdDqDqs FSM results: Left = 03, Right = 63, center = 33
N2.C0.D0.R0.S14: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N4.C3.R0.S03: PI = 36
N6.C1.D0.R1.S12: RxDqsDelay = 033
N0.C1.D0.R1.S07: RxDqsDelay = 033
N2.C0.D0.R0.S15: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N4.C3.R0.S04: PI = 39
N6.C1.D0.R1.S13: RdDqDqs FSM results: Left = 05, Right = 63, center = 34
N0.C1.D0.R1.S08: RdDqDqs FSM results: Left = 02, Right = 63, center = 32
N2.C0.D0.R0.S16: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N4.C3.R0.S05: PI = 37
N6.C1.D0.R1.S13: RxDqsDelay = 034
N0.C1.D0.R1.S08: RxDqsDelay = 032
N2.C0.D0.R0.S17: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N4.C3.R0.S06: PI = 39
N6.C1.D0.R1.S14: RdDqDqs FSM results: Left = 05, Right = 63, center = 34
N0.C1.D0.R1.S09: RdDqDqs FSM results: Left = 04, Right = 63, center = 33
N2.C0.D0.R0.S09: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N4.C3.R0.S07: PI = 37
N6.C1.D0.R1.S14: RxDqsDelay = 034
N0.C1.D0.R1.S09: RxDqsDelay = 033
N2.C0.D0.R0.S10: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N4.C3.R0.S08: PI = 35
N6.C1.D0.R1.S15: RdDqDqs FSM results: Left = 06, Right = 60, center = 33
N0.C1.D0.R1.S10: RdDqDqs FSM results: Left = 05, Right = 63, center = 34
N2.C0.D0.R0.S11: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N4.C3.R0.S09: PI = 37
N6.C1.D0.R1.S15: RxDqsDelay = 033
N0.C1.D0.R1.S10: RxDqsDelay = 034
N2.C0.D0.R0.S12: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N4.C3.R0.S10: PI = 36
N6.C1.D0.R1.S16: RdDqDqs FSM results: Left = 07, Right = 63, center = 35
N0.C1.D0.R1.S11: RdDqDqs FSM results: Left = 02, Right = 63, center = 32
N2.C0.D0.R0.S13: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N4.C3.R0.S11: PI = 36
N6.C1.D0.R1.S16: RxDqsDelay = 035
N0.C1.D0.R1.S11: RxDqsDelay = 032
N2.C0.D0.R0.S14: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N4.C3.R0.S12: PI = 37
N6.C1.D0.R1.S17: RdDqDqs FSM results: Left = 03, Right = 63, center = 33
N0.C1.D0.R1.S12: RdDqDqs FSM results: Left = 04, Right = 63, center = 33
N2.C0.D0.R0.S15: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N4.C3.R0.S13: PI = 36
N6.C1.D0.R1.S17: RxDqsDelay = 033
N0.C1.D0.R1.S12: RxDqsDelay = 033
N2.C0.D0.R0.S16: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N4.C3.R0.S14: PI = 37
N6.C1.D1.R0.S00: RdDqDqs FSM results: Left = 07, Right = 63, center = 35
N0.C1.D0.R1.S13: RdDqDqs FSM results: Left = 02, Right = 63, center = 32
N2.C0.D0.R0.S17: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N4.C3.R0.S15: PI = 37
N6.C1.D1.R0.S00: RxDqsDelay = 035
N0.C1.D0.R1.S13: RxDqsDelay = 032
N2.C0.D0.R0.S09: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N4.C3.R0.S16: PI = 36
N6.C1.D1.R0.S01: RdDqDqs FSM results: Left = 09, Right = 63, center = 36
N0.C1.D0.R1.S14: RdDqDqs FSM results: Left = 05, Right = 63, center = 34
N2.C0.D0.R0.S10: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N4.C3.R0.S17: PI = 37
N6.C1.D1.R0.S01: RxDqsDelay = 036
N0.C1.D0.R1.S14: RxDqsDelay = 034
N2.C0.D0.R0.S11: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N4.C3.R2.S00: PI = 40
N6.C1.D1.R0.S02: RdDqDqs FSM results: Left = 06, Right = 63, center = 34
N0.C1.D0.R1.S15: RdDqDqs FSM results: Left = 03, Right = 63, center = 33
N2.C0.D0.R0.S12: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N4.C3.R2.S01: PI = 41
N6.C1.D1.R0.S02: RxDqsDelay = 034
N0.C1.D0.R1.S15: RxDqsDelay = 033
N2.C0.D0.R0.S13: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N4.C3.R2.S02: PI = 38
N6.C1.D1.R0.S03: RdDqDqs FSM results: Left = 07, Right = 63, center = 35
N0.C1.D0.R1.S16: RdDqDqs FSM results: Left = 02, Right = 60, center = 31
N2.C0.D0.R0.S14: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N4.C3.R2.S03: PI = 39
N6.C1.D1.R0.S03: RxDqsDelay = 035
N0.C1.D0.R1.S16: RxDqsDelay = 031
N2.C0.D0.R0.S15: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N4.C3.R2.S04: PI = 41
N6.C1.D1.R0.S04: RdDqDqs FSM results: Left = 09, Right = 63, center = 36
N0.C1.D0.R1.S17: RdDqDqs FSM results: Left = 01, Right = 60, center = 30
N2.C0.D0.R0.S16: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N4.C3.R2.S05: PI = 40
N6.C1.D1.R0.S04: RxDqsDelay = 036
N0.C1.D0.R1.S17: RxDqsDelay = 030
N2.C0.D0.R0.S17: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N4.C3.R2.S06: PI = 40
N6.C1.D1.R0.S05: RdDqDqs FSM results: Left = 09, Right = 63, center = 36
N0.C1.D1.R0.S00: RdDqDqs FSM results: Left = 05, Right = 63, center = 34
N2.C0.D0.R0.S09: Preamble found at Latency = 008
N4.C3.R2.S07: PI = 38
N6.C1.D1.R0.S05: RxDqsDelay = 036
N0.C1.D1.R0.S00: RxDqsDelay = 034
N2.C0.D0.R0.S16: Preamble found at Latency = 008
N4.C3.R2.S08: PI = 36
N6.C1.D1.R0.S06: RdDqDqs FSM results: Left = 09, Right = 63, center = 36
N0.C1.D1.R0.S01: RdDqDqs FSM results: Left = 08, Right = 63, center = 35
N2.C0.D0.R0.S09: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N4.C3.R2.S09: PI = 39
N6.C1.D1.R0.S06: RxDqsDelay = 036
N0.C1.D1.R0.S01: RxDqsDelay = 035
N2.C0.D0.R0.S10: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N4.C3.R2.S10: PI = 38
N6.C1.D1.R0.S07: RdDqDqs FSM results: Left = 09, Right = 63, center = 36
N0.C1.D1.R0.S02: RdDqDqs FSM results: Left = 10, Right = 63, center = 36
N2.C0.D0.R0.S11: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N4.C3.R2.S11: PI = 37
N6.C1.D1.R0.S07: RxDqsDelay = 036
N0.C1.D1.R0.S02: RxDqsDelay = 036
N2.C0.D0.R0.S12: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N4.C3.R2.S12: PI = 39
N6.C1.D1.R0.S08: RdDqDqs FSM results: Left = 07, Right = 63, center = 35
N0.C1.D1.R0.S03: RdDqDqs FSM results: Left = 06, Right = 63, center = 34
N2.C0.D0.R0.S13: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N4.C3.R2.S13: PI = 37
N6.C1.D1.R0.S08: RxDqsDelay = 035
N0.C1.D1.R0.S03: RxDqsDelay = 034
N2.C0.D0.R0.S14: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N4.C3.R2.S14: PI = 39
N6.C1.D1.R0.S09: RdDqDqs FSM results: Left = 12, Right = 63, center = 37
N0.C1.D1.R0.S04: RdDqDqs FSM results: Left = 05, Right = 63, center = 34
N2.C0.D0.R0.S15: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N4.C3.R2.S15: PI = 40
N6.C1.D1.R0.S09: RxDqsDelay = 037
N0.C1.D1.R0.S04: RxDqsDelay = 034
N2.C0.D0.R0.S16: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N4.C3.R2.S16: PI = 37
N6.C1.D1.R0.S10: RdDqDqs FSM results: Left = 08, Right = 63, center = 35
N0.C1.D1.R0.S05: RdDqDqs FSM results: Left = 08, Right = 63, center = 35
N2.C0.D0.R0.S17: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N4.C3.R2.S17: PI = 39
N6.C1.D1.R0.S10: RxDqsDelay = 035
N0.C1.D1.R0.S05: RxDqsDelay = 035
N2.C0.D0.R0.S10: Preamble found at Latency = 007
N4.C3.R2.S00: PI = 40
N6.C1.D1.R0.S11: RdDqDqs FSM results: Left = 04, Right = 63, center = 33
N0.C1.D1.R0.S06: RdDqDqs FSM results: Left = 08, Right = 63, center = 35
N2.C0.D0.R0.S11: Preamble found at Latency = 007
N4.C3.R2.S01: PI = 41
N6.C1.D1.R0.S11: RxDqsDelay = 033
N0.C1.D1.R0.S06: RxDqsDelay = 035
N2.C0.D0.R0.S12: Preamble found at Latency = 007
N4.C3.R2.S02: PI = 38
N6.C1.D1.R0.S12: RdDqDqs FSM results: Left = 06, Right = 63, center = 34
N0.C1.D1.R0.S07: RdDqDqs FSM results: Left = 08, Right = 63, center = 35
N2.C0.D0.R0.S13: Preamble found at Latency = 007
N4.C3.R2.S03: PI = 39
N6.C1.D1.R0.S12: RxDqsDelay = 034
N0.C1.D1.R0.S07: RxDqsDelay = 035
N2.C0.D0.R0.S14: Preamble found at Latency = 007
N4.C3.R2.S04: PI = 41
N6.C1.D1.R0.S13: RdDqDqs FSM results: Left = 09, Right = 63, center = 36
N0.C1.D1.R0.S08: RdDqDqs FSM results: Left = 05, Right = 63, center = 34
N2.C0.D0.R0.S15: Preamble found at Latency = 007
N4.C3.R2.S05: PI = 40
N6.C1.D1.R0.S13: RxDqsDelay = 036
N0.C1.D1.R0.S08: RxDqsDelay = 034
N2.C0.D0.R0.S17: Preamble found at Latency = 007
N4.C3.R2.S06: PI = 40
N6.C1.D1.R0.S14: RdDqDqs FSM results: Left = 09, Right = 63, center = 36
N0.C1.D1.R0.S09: RdDqDqs FSM results: Left = 08, Right = 63, center = 35
N2.C0.D0.R0: Preamble found for all upper nibbles, adjusting Pi, Offset to center into preamble
N4.C3.R2.S07: PI = 38
N6.C1.D1.R0.S14: RxDqsDelay = 036
N0.C1.D1.R0.S09: RxDqsDelay = 035
N2.C0.D0.R0.S09: Total Receive Enable Delay = 1326
N4.C3.R2.S08: PI = 36
N6.C1.D1.R0.S15: RdDqDqs FSM results: Left = 10, Right = 63, center = 36
N0.C1.D1.R0.S10: RdDqDqs FSM results: Left = 10, Right = 63, center = 36
N2.C0.D0.R0.S10: Total Receive Enable Delay = 1309
N4.C3.R2.S09: PI = 39
N6.C1.D1.R0.S15: RxDqsDelay = 036
N0.C1.D1.R0.S10: RxDqsDelay = 036
N2.C0.D0.R0.S11: Total Receive Enable Delay = 1281
N4.C3.R2.S10: PI = 38
N6.C1.D1.R0.S16: RdDqDqs FSM results: Left = 09, Right = 63, center = 36
N0.C1.D1.R0.S11: RdDqDqs FSM results: Left = 05, Right = 63, center = 34
N2.C0.D0.R0.S12: Total Receive Enable Delay = 1259
N4.C3.R2.S11: PI = 37
N6.C1.D1.R0.S16: RxDqsDelay = 036
N0.C1.D1.R0.S11: RxDqsDelay = 034
N2.C0.D0.R0.S13: Total Receive Enable Delay = 1247
N4.C3.R2.S12: PI = 39
N6.C1.D1.R0.S17: RdDqDqs FSM results: Left = 06, Right = 63, center = 34
N0.C1.D1.R0.S12: RdDqDqs FSM results: Left = 06, Right = 63, center = 34
N2.C0.D0.R0.S14: Total Receive Enable Delay = 1273
N4.C3.R2.S13: PI = 37
N6.C1.D1.R0.S17: RxDqsDelay = 034
N0.C1.D1.R0.S12: RxDqsDelay = 034
N2.C0.D0.R0.S15: Total Receive Enable Delay = 1305
N4.C3.R2.S14: PI = 39
N6.C1.D1.R1.S00: RdDqDqs FSM results: Left = 07, Right = 63, center = 35
N0.C1.D1.R0.S13: RdDqDqs FSM results: Left = 07, Right = 63, center = 35
N2.C0.D0.R0.S16: Total Receive Enable Delay = 1328
N4.C3.R2.S15: PI = 40
N6.C1.D1.R1.S00: RxDqsDelay = 035
N0.C1.D1.R0.S13: RxDqsDelay = 035
N2.C0.D0.R0.S17: Total Receive Enable Delay = 1245
N4.C3.R2.S16: PI = 37
N6.C1.D1.R1.S01: RdDqDqs FSM results: Left = 10, Right = 63, center = 36
N0.C1.D1.R0.S14: RdDqDqs FSM results: Left = 07, Right = 63, center = 35
N2.C0.D0.R1: RcvEnFine: Initial RdCmd2RcvEnLatency = 10, Initial RdPtrOffsetRcvEn = 4
N4.C3.R2.S17: PI = 39
N6.C1.D1.R1.S01: RxDqsDelay = 036
N0.C1.D1.R0.S14: RxDqsDelay = 035
N2.C0.D0.R1.S00: Rcv En Fine Value = 270
STOP_DATA_RX_DQS
N6.C1.D1.R1.S02: RdDqDqs FSM results: Left = 05, Right = 63, center = 34
N0.C1.D1.R0.S15: RdDqDqs FSM results: Left = 05, Right = 63, center = 34
N2.C0.D0.R1.S01: Rcv En Fine Value = 380
N4: RunTrainStep: Final status = 0
N6.C1.D1.R1.S02: RxDqsDelay = 034
N0.C1.D1.R0.S15: RxDqsDelay = 034
N2.C0.D0.R1.S02: Rcv En Fine Value = 351

END - Basic Read DQ/DQS Training       Time         13573 ms
N6.C1.D1.R1.S03: RdDqDqs FSM results: Left = 08, Right = 63, center = 35
N0.C1.D1.R0.S16: RdDqDqs FSM results: Left = 05, Right = 63, center = 34
N2.C0.D0.R1.S03: Rcv En Fine Value = 330

START - Basic Receive Enable Training
N6.C1.D1.R1.S03: RxDqsDelay = 035
N0.C1.D1.R0.S16: RxDqsDelay = 034
N2.C0.D0.R1.S04: Rcv En Fine Value = 322
N4.C0: QCRM debug: extraRcvEnLatency = 0
N6.C1.D1.R1.S04: RdDqDqs FSM results: Left = 09, Right = 63, center = 36
N0.C1.D1.R0.S17: RdDqDqs FSM results: Left = 04, Right = 63, center = 33
N2.C0.D0.R1.S05: Rcv En Fine Value = 347
N4.C0: SettingForTrainingStep: RdCmd2RcvEnLatency = 10, RdPtrOffsetRcvEn = 4
N6.C1.D1.R1.S04: RxDqsDelay = 036
N0.C1.D1.R0.S17: RxDqsDelay = 033
N2.C0.D0.R1.S06: Rcv En Fine Value = 378
N4.C1: QCRM debug: extraRcvEnLatency = 0
N6.C1.D1.R1.S05: RdDqDqs FSM results: Left = 09, Right = 63, center = 36
N0.C1.D1.R1.S00: RdDqDqs FSM results: Left = 07, Right = 63, center = 35
N2.C0.D0.R1.S07: Rcv En Fine Value = 273
N4.C1: SettingForTrainingStep: RdCmd2RcvEnLatency = 10, RdPtrOffsetRcvEn = 4
N6.C1.D1.R1.S05: RxDqsDelay = 036
N0.C1.D1.R1.S00: RxDqsDelay = 035
N2.C0.D0.R1.S08: Rcv En Fine Value = 318
N4.C2: QCRM debug: extraRcvEnLatency = 0
N6.C1.D1.R1.S06: RdDqDqs FSM results: Left = 10, Right = 63, center = 36
N0.C1.D1.R1.S01: RdDqDqs FSM results: Left = 08, Right = 63, center = 35
N2.C0.D0.R1.S09: Rcv En Fine Value = 269
N4.C2: SettingForTrainingStep: RdCmd2RcvEnLatency = 10, RdPtrOffsetRcvEn = 4
N6.C1.D1.R1.S06: RxDqsDelay = 036
N0.C1.D1.R1.S01: RxDqsDelay = 035
N2.C0.D0.R1.S10: Rcv En Fine Value = 380
N4.C3: QCRM debug: extraRcvEnLatency = 0
N6.C1.D1.R1.S07: RdDqDqs FSM results: Left = 09, Right = 63, center = 36
N0.C1.D1.R1.S02: RdDqDqs FSM results: Left = 08, Right = 63, center = 35
N2.C0.D0.R1.S11: Rcv En Fine Value = 351
N4.C3: SettingForTrainingStep: RdCmd2RcvEnLatency = 10, RdPtrOffsetRcvEn = 4
N6.C1.D1.R1.S07: RxDqsDelay = 036
N0.C1.D1.R1.S02: RxDqsDelay = 035
N2.C0.D0.R1.S12: Rcv En Fine Value = 332
N4.C0.D0.R0: RcvEnFine: Initial RdCmd2RcvEnLatency = 10, Initial RdPtrOffsetRcvEn = 4
N6.C1.D1.R1.S08: RdDqDqs FSM results: Left = 09, Right = 63, center = 36
N0.C1.D1.R1.S03: RdDqDqs FSM results: Left = 06, Right = 63, center = 34
N2.C0.D0.R1.S13: Rcv En Fine Value = 320
N4.C0.D0.R0.S00: Rcv En Fine Value = 268
N6.C1.D1.R1.S08: RxDqsDelay = 036
N0.C1.D1.R1.S03: RxDqsDelay = 034
N2.C0.D0.R1.S14: Rcv En Fine Value = 345
N4.C0.D0.R0.S01: Rcv En Fine Value = 374
N6.C1.D1.R1.S09: RdDqDqs FSM results: Left = 12, Right = 63, center = 37
N0.C1.D1.R1.S04: RdDqDqs FSM results: Left = 07, Right = 63, center = 35
N2.C0.D0.R1.S15: Rcv En Fine Value = 378
N4.C0.D0.R0.S02: Rcv En Fine Value = 348
N6.C1.D1.R1.S09: RxDqsDelay = 037
N0.C1.D1.R1.S04: RxDqsDelay = 035
N2.C0.D0.R1.S16: Rcv En Fine Value = 271
N4.C0.D0.R0.S03: Rcv En Fine Value = 326
N6.C1.D1.R1.S10: RdDqDqs FSM results: Left = 08, Right = 63, center = 35
N0.C1.D1.R1.S05: RdDqDqs FSM results: Left = 08, Right = 63, center = 35
N2.C0.D0.R1.S17: Rcv En Fine Value = 316
N4.C0.D0.R0.S04: Rcv En Fine Value = 318
N6.C1.D1.R1.S10: RxDqsDelay = 035
N0.C1.D1.R1.S05: RxDqsDelay = 035
N2.C0.D0.R1: Starting preamble search lower nibbles
N4.C0.D0.R0.S05: Rcv En Fine Value = 342
N6.C1.D1.R1.S11: RdDqDqs FSM results: Left = 04, Right = 63, center = 33
N0.C1.D1.R1.S06: RdDqDqs FSM results: Left = 09, Right = 63, center = 36
N2.C0.D0.R1.S00: PI = 014, PtrOffset = 004
N4.C0.D0.R0.S06: Rcv En Fine Value = 375
N6.C1.D1.R1.S11: RxDqsDelay = 033
N0.C1.D1.R1.S06: RxDqsDelay = 036
N2.C0.D0.R1.S01: PI = 060, PtrOffset = 005
N4.C0.D0.R0.S07: Rcv En Fine Value = 269
N6.C1.D1.R1.S12: RdDqDqs FSM results: Left = 08, Right = 63, center = 35
N0.C1.D1.R1.S07: RdDqDqs FSM results: Left = 07, Right = 63, center = 35
N2.C0.D0.R1.S02: PI = 031, PtrOffset = 005
N4.C0.D0.R0.S08: Rcv En Fine Value = 313
N6.C1.D1.R1.S12: RxDqsDelay = 035
N0.C1.D1.R1.S07: RxDqsDelay = 035
N2.C0.D0.R1.S03: PI = 010, PtrOffset = 005
N4.C0.D0.R0.S09: Rcv En Fine Value = 265
N6.C1.D1.R1.S13: RdDqDqs FSM results: Left = 10, Right = 63, center = 36
N0.C1.D1.R1.S08: RdDqDqs FSM results: Left = 05, Right = 63, center = 34
N2.C0.D0.R1.S04: PI = 002, PtrOffset = 005
N4.C0.D0.R0.S10: Rcv En Fine Value = 374
N6.C1.D1.R1.S13: RxDqsDelay = 036
N0.C1.D1.R1.S08: RxDqsDelay = 034
N2.C0.D0.R1.S05: PI = 027, PtrOffset = 005
N4.C0.D0.R0.S11: Rcv En Fine Value = 347
N6.C1.D1.R1.S14: RdDqDqs FSM results: Left = 09, Right = 63, center = 36
N0.C1.D1.R1.S09: RdDqDqs FSM results: Left = 07, Right = 63, center = 35
N2.C0.D0.R1.S06: PI = 058, PtrOffset = 005
N4.C0.D0.R0.S12: Rcv En Fine Value = 325
N6.C1.D1.R1.S14: RxDqsDelay = 036
N0.C1.D1.R1.S09: RxDqsDelay = 035
N2.C0.D0.R1.S07: PI = 017, PtrOffset = 004
N4.C0.D0.R0.S13: Rcv En Fine Value = 319
N6.C1.D1.R1.S15: RdDqDqs FSM results: Left = 10, Right = 63, center = 36
N0.C1.D1.R1.S10: RdDqDqs FSM results: Left = 09, Right = 63, center = 36
N2.C0.D0.R1.S08: PI = 062, PtrOffset = 004
N4.C0.D0.R0.S14: Rcv En Fine Value = 340
N6.C1.D1.R1.S15: RxDqsDelay = 036
N0.C1.D1.R1.S10: RxDqsDelay = 036
N2.C0.D0.R1.S00: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N4.C0.D0.R0.S15: Rcv En Fine Value = 372
N6.C1.D1.R1.S16: RdDqDqs FSM results: Left = 09, Right = 63, center = 36
N0.C1.D1.R1.S11: RdDqDqs FSM results: Left = 03, Right = 63, center = 33
N2.C0.D0.R1.S01: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N4.C0.D0.R0.S16: Rcv En Fine Value = 267
N6.C1.D1.R1.S16: RxDqsDelay = 036
N0.C1.D1.R1.S11: RxDqsDelay = 033
N2.C0.D0.R1.S02: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N4.C0.D0.R0.S17: Rcv En Fine Value = 311
N6.C1.D1.R1.S17: RdDqDqs FSM results: Left = 06, Right = 63, center = 34
N0.C1.D1.R1.S12: RdDqDqs FSM results: Left = 06, Right = 63, center = 34
N2.C0.D0.R1.S03: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N4.C0.D0.R0: Starting preamble search lower nibbles
N6.C1.D1.R1.S17: RxDqsDelay = 034
N0.C1.D1.R1.S12: RxDqsDelay = 034
N2.C0.D0.R1.S04: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N4.C0.D0.R0.S00: PI = 012, PtrOffset = 004
START_DATA_RX_DQS
N0.C1.D1.R1.S13: RdDqDqs FSM results: Left = 07, Right = 63, center = 35
N2.C0.D0.R1.S05: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N4.C0.D0.R0.S01: PI = 054, PtrOffset = 005
N6.C1.R0.S00: PI = 32
N0.C1.D1.R1.S13: RxDqsDelay = 035
N2.C0.D0.R1.S06: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N4.C0.D0.R0.S02: PI = 028, PtrOffset = 005
N6.C1.R0.S01: PI = 34
N0.C1.D1.R1.S14: RdDqDqs FSM results: Left = 05, Right = 63, center = 34
N2.C0.D0.R1.S07: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N4.C0.D0.R0.S03: PI = 006, PtrOffset = 005
N6.C1.R0.S02: PI = 32
N0.C1.D1.R1.S14: RxDqsDelay = 034
N2.C0.D0.R1.S08: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N4.C0.D0.R0.S04: PI = 062, PtrOffset = 004
N6.C1.R0.S03: PI = 33
N0.C1.D1.R1.S15: RdDqDqs FSM results: Left = 05, Right = 63, center = 34
N2.C0.D0.R1.S00: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N4.C0.D0.R0.S05: PI = 022, PtrOffset = 005
N6.C1.R0.S04: PI = 34
N0.C1.D1.R1.S15: RxDqsDelay = 034
N2.C0.D0.R1.S01: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N4.C0.D0.R0.S06: PI = 055, PtrOffset = 005
N6.C1.R0.S05: PI = 34
N0.C1.D1.R1.S16: RdDqDqs FSM results: Left = 05, Right = 63, center = 34
N2.C0.D0.R1.S02: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N4.C0.D0.R0.S07: PI = 013, PtrOffset = 004
N6.C1.R0.S06: PI = 33
N0.C1.D1.R1.S16: RxDqsDelay = 034
N2.C0.D0.R1.S03: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N4.C0.D0.R0.S08: PI = 057, PtrOffset = 004
N6.C1.R0.S07: PI = 34
N0.C1.D1.R1.S17: RdDqDqs FSM results: Left = 04, Right = 63, center = 33
N2.C0.D0.R1.S04: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N4.C0.D0.R0.S00: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N6.C1.R0.S08: PI = 33
N0.C1.D1.R1.S17: RxDqsDelay = 033
N2.C0.D0.R1.S05: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N4.C0.D0.R0.S01: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N6.C1.R0.S09: PI = 35
START_DATA_RX_DQS
N2.C0.D0.R1.S06: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N4.C0.D0.R0.S02: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N6.C1.R0.S10: PI = 33
N0.C1.R0.S00: PI = 32
N2.C0.D0.R1.S07: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N4.C0.D0.R0.S03: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N6.C1.R0.S11: PI = 32
N0.C1.R0.S01: PI = 34
N2.C0.D0.R1.S08: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N4.C0.D0.R0.S04: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N6.C1.R0.S12: PI = 33
N0.C1.R0.S02: PI = 34
N2.C0.D0.R1.S00: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N4.C0.D0.R0.S05: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N6.C1.R0.S13: PI = 34
N0.C1.R0.S03: PI = 33
N2.C0.D0.R1.S01: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N4.C0.D0.R0.S06: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N6.C1.R0.S14: PI = 34
N0.C1.R0.S04: PI = 32
N2.C0.D0.R1.S02: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N4.C0.D0.R0.S07: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N6.C1.R0.S15: PI = 33
N0.C1.R0.S05: PI = 33
N2.C0.D0.R1.S03: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N4.C0.D0.R0.S08: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N6.C1.R0.S16: PI = 35
N0.C1.R0.S06: PI = 34
N2.C0.D0.R1.S04: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N4.C0.D0.R0.S00: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N6.C1.R0.S17: PI = 33
N0.C1.R0.S07: PI = 33
N2.C0.D0.R1.S05: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N4.C0.D0.R0.S01: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N6.C1.R0.S00: PI = 32
N0.C1.R0.S08: PI = 31
N2.C0.D0.R1.S06: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N4.C0.D0.R0.S02: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N6.C1.R0.S01: PI = 34
N0.C1.R0.S09: PI = 33
N2.C0.D0.R1.S07: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N4.C0.D0.R0.S03: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N6.C1.R0.S02: PI = 32
N0.C1.R0.S10: PI = 34
N2.C0.D0.R1.S08: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N4.C0.D0.R0.S04: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N6.C1.R0.S03: PI = 33
N0.C1.R0.S11: PI = 32
N2.C0.D0.R1.S00: Preamble found at Latency = 008
N4.C0.D0.R0.S05: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N6.C1.R0.S04: PI = 34
N0.C1.R0.S12: PI = 33
N2.C0.D0.R1.S07: Preamble found at Latency = 008
N4.C0.D0.R0.S06: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N6.C1.R0.S05: PI = 34
N0.C1.R0.S13: PI = 32
N2.C0.D0.R1.S00: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N4.C0.D0.R0.S07: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N6.C1.R0.S06: PI = 33
N0.C1.R0.S14: PI = 34
N2.C0.D0.R1.S01: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N4.C0.D0.R0.S08: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N6.C1.R0.S07: PI = 34
N0.C1.R0.S15: PI = 32
N2.C0.D0.R1.S02: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N4.C0.D0.R0.S00: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N6.C1.R0.S08: PI = 33
N0.C1.R0.S16: PI = 32
N2.C0.D0.R1.S03: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N4.C0.D0.R0.S01: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N6.C1.R0.S09: PI = 35
N0.C1.R0.S17: PI = 31
N2.C0.D0.R1.S04: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N4.C0.D0.R0.S02: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N6.C1.R0.S10: PI = 33
N0.C1.R0.S00: PI = 32
N2.C0.D0.R1.S05: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N4.C0.D0.R0.S03: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N6.C1.R0.S11: PI = 32
N0.C1.R0.S01: PI = 34
N2.C0.D0.R1.S06: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N4.C0.D0.R0.S04: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N6.C1.R0.S12: PI = 33
N0.C1.R0.S02: PI = 34
N2.C0.D0.R1.S07: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N4.C0.D0.R0.S05: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N6.C1.R0.S13: PI = 34
N0.C1.R0.S03: PI = 33
N2.C0.D0.R1.S08: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N4.C0.D0.R0.S06: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N6.C1.R0.S14: PI = 34
N0.C1.R0.S04: PI = 32
N2.C0.D0.R1.S01: Preamble found at Latency = 007
N4.C0.D0.R0.S07: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N6.C1.R0.S15: PI = 33
N0.C1.R0.S05: PI = 33
N2.C0.D0.R1.S02: Preamble found at Latency = 007
N4.C0.D0.R0.S08: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N6.C1.R0.S16: PI = 35
N0.C1.R0.S06: PI = 34
N2.C0.D0.R1.S03: Preamble found at Latency = 007
N4.C0.D0.R0.S00: Preamble found at Latency = 008
N6.C1.R0.S17: PI = 33
N0.C1.R0.S07: PI = 33
N2.C0.D0.R1.S04: Preamble found at Latency = 007
N4.C0.D0.R0.S07: Preamble found at Latency = 008
N6.C1.R2.S00: PI = 35
N0.C1.R0.S08: PI = 31
N2.C0.D0.R1.S05: Preamble found at Latency = 007
N4.C0.D0.R0.S00: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N6.C1.R2.S01: PI = 36
N0.C1.R0.S09: PI = 33
N2.C0.D0.R1.S06: Preamble found at Latency = 007
N4.C0.D0.R0.S01: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N6.C1.R2.S02: PI = 34
N0.C1.R0.S10: PI = 34
N2.C0.D0.R1.S08: Preamble found at Latency = 007
N4.C0.D0.R0.S02: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N6.C1.R2.S03: PI = 35
N0.C1.R0.S11: PI = 32
N2.C0.D0.R1.S00: Total Receive Enable Delay = 1326
N4.C0.D0.R0.S03: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N6.C1.R2.S04: PI = 36
N0.C1.R0.S12: PI = 33
N2.C0.D0.R1.S01: Total Receive Enable Delay = 1308
N4.C0.D0.R0.S04: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N6.C1.R2.S05: PI = 36
N0.C1.R0.S13: PI = 32
N2.C0.D0.R1.S02: Total Receive Enable Delay = 1279
N4.C0.D0.R0.S05: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N6.C1.R2.S06: PI = 36
N0.C1.R0.S14: PI = 34
N2.C0.D0.R1.S03: Total Receive Enable Delay = 1258
N4.C0.D0.R0.S06: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N6.C1.R2.S07: PI = 36
N0.C1.R0.S15: PI = 32
N2.C0.D0.R1.S04: Total Receive Enable Delay = 1250
N4.C0.D0.R0.S07: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N6.C1.R2.S08: PI = 35
N0.C1.R0.S16: PI = 32
N2.C0.D0.R1.S05: Total Receive Enable Delay = 1275
N4.C0.D0.R0.S08: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N6.C1.R2.S09: PI = 37
N0.C1.R0.S17: PI = 31
N2.C0.D0.R1.S06: Total Receive Enable Delay = 1306
N4.C0.D0.R0.S01: Preamble found at Latency = 007
N6.C1.R2.S10: PI = 35
N0.C1.R2.S00: PI = 34
N2.C0.D0.R1.S07: Total Receive Enable Delay = 1329
N4.C0.D0.R0.S02: Preamble found at Latency = 007
N6.C1.R2.S11: PI = 33
N0.C1.R2.S01: PI = 35
N2.C0.D0.R1.S08: Total Receive Enable Delay = 1246
N4.C0.D0.R0.S03: Preamble found at Latency = 007
N6.C1.R2.S12: PI = 34
N0.C1.R2.S02: PI = 35
N2.C0.D0.R1: Starting preamble search upper nibbles
N4.C0.D0.R0.S04: Preamble found at Latency = 007
N6.C1.R2.S13: PI = 36
N0.C1.R2.S03: PI = 34
N2.C0.D0.R1.S09: PI = 013, PtrOffset = 004
N4.C0.D0.R0.S05: Preamble found at Latency = 007
N6.C1.R2.S14: PI = 36
N0.C1.R2.S04: PI = 34
N2.C0.D0.R1.S10: PI = 060, PtrOffset = 005
N4.C0.D0.R0.S06: Preamble found at Latency = 007
N6.C1.R2.S15: PI = 36
N0.C1.R2.S05: PI = 35
N2.C0.D0.R1.S11: PI = 031, PtrOffset = 005
N4.C0.D0.R0.S08: Preamble found at Latency = 007
N6.C1.R2.S16: PI = 36
N0.C1.R2.S06: PI = 35
N2.C0.D0.R1.S12: PI = 012, PtrOffset = 005
N4.C0.D0.R0.S00: Total Receive Enable Delay = 1324
N6.C1.R2.S17: PI = 34
N0.C1.R2.S07: PI = 35
N2.C0.D0.R1.S13: PI = 000, PtrOffset = 005
N4.C0.D0.R0.S01: Total Receive Enable Delay = 1302
N6.C1.R2.S00: PI = 35
N0.C1.R2.S08: PI = 34
N2.C0.D0.R1.S14: PI = 025, PtrOffset = 005
N4.C0.D0.R0.S02: Total Receive Enable Delay = 1276
N6.C1.R2.S01: PI = 36
N0.C1.R2.S09: PI = 35
N2.C0.D0.R1.S15: PI = 058, PtrOffset = 005
N4.C0.D0.R0.S03: Total Receive Enable Delay = 1254
N6.C1.R2.S02: PI = 34
N0.C1.R2.S10: PI = 36
N2.C0.D0.R1.S16: PI = 015, PtrOffset = 004
N4.C0.D0.R0.S04: Total Receive Enable Delay = 1246
N6.C1.R2.S03: PI = 35
N0.C1.R2.S11: PI = 33
N2.C0.D0.R1.S17: PI = 060, PtrOffset = 004
N4.C0.D0.R0.S05: Total Receive Enable Delay = 1270
N6.C1.R2.S04: PI = 36
N0.C1.R2.S12: PI = 34
N2.C0.D0.R1.S09: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N4.C0.D0.R0.S06: Total Receive Enable Delay = 1303
N6.C1.R2.S05: PI = 36
N0.C1.R2.S13: PI = 35
N2.C0.D0.R1.S10: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N4.C0.D0.R0.S07: Total Receive Enable Delay = 1325
N6.C1.R2.S06: PI = 36
N0.C1.R2.S14: PI = 34
N2.C0.D0.R1.S11: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N4.C0.D0.R0.S08: Total Receive Enable Delay = 1241
N6.C1.R2.S07: PI = 36
N0.C1.R2.S15: PI = 34
N2.C0.D0.R1.S12: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N4.C0.D0.R0: Starting preamble search upper nibbles
N6.C1.R2.S08: PI = 35
N0.C1.R2.S16: PI = 34
N2.C0.D0.R1.S13: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N4.C0.D0.R0.S09: PI = 009, PtrOffset = 004
N6.C1.R2.S09: PI = 37
N0.C1.R2.S17: PI = 33
N2.C0.D0.R1.S14: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N4.C0.D0.R0.S10: PI = 054, PtrOffset = 005
N6.C1.R2.S10: PI = 35
N0.C1.R2.S00: PI = 34
N2.C0.D0.R1.S15: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N4.C0.D0.R0.S11: PI = 027, PtrOffset = 005
N6.C1.R2.S11: PI = 33
N0.C1.R2.S01: PI = 35
N2.C0.D0.R1.S16: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N4.C0.D0.R0.S12: PI = 005, PtrOffset = 005
N6.C1.R2.S12: PI = 34
N0.C1.R2.S02: PI = 35
N2.C0.D0.R1.S17: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N4.C0.D0.R0.S13: PI = 063, PtrOffset = 004
N6.C1.R2.S13: PI = 36
N0.C1.R2.S03: PI = 34
N2.C0.D0.R1.S09: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N4.C0.D0.R0.S14: PI = 020, PtrOffset = 005
N6.C1.R2.S14: PI = 36
N0.C1.R2.S04: PI = 34
N2.C0.D0.R1.S10: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N4.C0.D0.R0.S15: PI = 052, PtrOffset = 005
N6.C1.R2.S15: PI = 36
N0.C1.R2.S05: PI = 35
N2.C0.D0.R1.S11: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N4.C0.D0.R0.S16: PI = 011, PtrOffset = 004
N6.C1.R2.S16: PI = 36
N0.C1.R2.S06: PI = 35
N2.C0.D0.R1.S12: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N4.C0.D0.R0.S17: PI = 055, PtrOffset = 004
N6.C1.R2.S17: PI = 34
N0.C1.R2.S07: PI = 35
N2.C0.D0.R1.S13: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N4.C0.D0.R0.S09: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
STOP_DATA_RX_DQS
N0.C1.R2.S08: PI = 34
N2.C0.D0.R1.S14: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N4.C0.D0.R0.S10: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N6.C2.D0.R0.S00: RdDqDqs FSM results: Left = 01, Right = 63, center = 32
N0.C1.R2.S09: PI = 35
N2.C0.D0.R1.S15: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N4.C0.D0.R0.S11: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N6.C2.D0.R0.S00: RxDqsDelay = 032
N0.C1.R2.S10: PI = 36
N2.C0.D0.R1.S16: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N4.C0.D0.R0.S12: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N6.C2.D0.R0.S01: RdDqDqs FSM results: Left = 05, Right = 63, center = 34
N0.C1.R2.S11: PI = 33
N2.C0.D0.R1.S17: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N4.C0.D0.R0.S13: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N6.C2.D0.R0.S01: RxDqsDelay = 034
N0.C1.R2.S12: PI = 34
N2.C0.D0.R1.S09: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N4.C0.D0.R0.S14: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N6.C2.D0.R0.S02: RdDqDqs FSM results: Left = 03, Right = 63, center = 33
N0.C1.R2.S13: PI = 35
N2.C0.D0.R1.S10: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N4.C0.D0.R0.S15: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N6.C2.D0.R0.S02: RxDqsDelay = 033
N0.C1.R2.S14: PI = 34
N2.C0.D0.R1.S11: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N4.C0.D0.R0.S16: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N6.C2.D0.R0.S03: RdDqDqs FSM results: Left = 04, Right = 63, center = 33
N0.C1.R2.S15: PI = 34
N2.C0.D0.R1.S12: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N4.C0.D0.R0.S17: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N6.C2.D0.R0.S03: RxDqsDelay = 033
N0.C1.R2.S16: PI = 34
N2.C0.D0.R1.S13: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N4.C0.D0.R0.S09: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N6.C2.D0.R0.S04: RdDqDqs FSM results: Left = 03, Right = 57, center = 30
N0.C1.R2.S17: PI = 33
N2.C0.D0.R1.S14: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N4.C0.D0.R0.S10: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N6.C2.D0.R0.S04: RxDqsDelay = 030
STOP_DATA_RX_DQS
N2.C0.D0.R1.S15: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N4.C0.D0.R0.S11: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N6.C2.D0.R0.S05: RdDqDqs FSM results: Left = 07, Right = 63, center = 35
N0.C2.D0.R0.S00: RdDqDqs FSM results: Left = 03, Right = 63, center = 33
N2.C0.D0.R1.S16: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N4.C0.D0.R0.S12: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N6.C2.D0.R0.S05: RxDqsDelay = 035
N0.C2.D0.R0.S00: RxDqsDelay = 033
N2.C0.D0.R1.S17: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N4.C0.D0.R0.S13: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N6.C2.D0.R0.S06: RdDqDqs FSM results: Left = 06, Right = 63, center = 34
N0.C2.D0.R0.S01: RdDqDqs FSM results: Left = 07, Right = 63, center = 35
N2.C0.D0.R1.S09: Preamble found at Latency = 008
N4.C0.D0.R0.S14: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N6.C2.D0.R0.S06: RxDqsDelay = 034
N0.C2.D0.R0.S01: RxDqsDelay = 035
N2.C0.D0.R1.S16: Preamble found at Latency = 008
N4.C0.D0.R0.S15: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N6.C2.D0.R0.S07: RdDqDqs FSM results: Left = 09, Right = 63, center = 36
N0.C2.D0.R0.S02: RdDqDqs FSM results: Left = 05, Right = 63, center = 34
N2.C0.D0.R1.S09: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N4.C0.D0.R0.S16: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N6.C2.D0.R0.S07: RxDqsDelay = 036
N0.C2.D0.R0.S02: RxDqsDelay = 034
N2.C0.D0.R1.S10: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N4.C0.D0.R0.S17: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N6.C2.D0.R0.S08: RdDqDqs FSM results: Left = 09, Right = 63, center = 36
N0.C2.D0.R0.S03: RdDqDqs FSM results: Left = 06, Right = 63, center = 34
N2.C0.D0.R1.S11: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N4.C0.D0.R0.S09: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N6.C2.D0.R0.S08: RxDqsDelay = 036
N0.C2.D0.R0.S03: RxDqsDelay = 034
N2.C0.D0.R1.S12: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N4.C0.D0.R0.S10: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N6.C2.D0.R0.S09: RdDqDqs FSM results: Left = 04, Right = 63, center = 33
N0.C2.D0.R0.S04: RdDqDqs FSM results: Left = 03, Right = 63, center = 33
N2.C0.D0.R1.S13: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N4.C0.D0.R0.S11: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N6.C2.D0.R0.S09: RxDqsDelay = 033
N0.C2.D0.R0.S04: RxDqsDelay = 033
N2.C0.D0.R1.S14: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N4.C0.D0.R0.S12: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N6.C2.D0.R0.S10: RdDqDqs FSM results: Left = 02, Right = 61, center = 31
N0.C2.D0.R0.S05: RdDqDqs FSM results: Left = 07, Right = 63, center = 35
N2.C0.D0.R1.S15: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N4.C0.D0.R0.S13: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N6.C2.D0.R0.S10: RxDqsDelay = 031
N0.C2.D0.R0.S05: RxDqsDelay = 035
N2.C0.D0.R1.S16: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N4.C0.D0.R0.S14: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N6.C2.D0.R0.S11: RdDqDqs FSM results: Left = 02, Right = 63, center = 32
N0.C2.D0.R0.S06: RdDqDqs FSM results: Left = 06, Right = 63, center = 34
N2.C0.D0.R1.S17: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N4.C0.D0.R0.S15: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N6.C2.D0.R0.S11: RxDqsDelay = 032
N0.C2.D0.R0.S06: RxDqsDelay = 034
N2.C0.D0.R1.S10: Preamble found at Latency = 007
N4.C0.D0.R0.S16: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N6.C2.D0.R0.S12: RdDqDqs FSM results: Left = 03, Right = 63, center = 33
N0.C2.D0.R0.S07: RdDqDqs FSM results: Left = 05, Right = 63, center = 34
N2.C0.D0.R1.S11: Preamble found at Latency = 007
N4.C0.D0.R0.S17: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N6.C2.D0.R0.S12: RxDqsDelay = 033
N0.C2.D0.R0.S07: RxDqsDelay = 034
N2.C0.D0.R1.S12: Preamble found at Latency = 007
N4.C0.D0.R0.S09: Preamble found at Latency = 008
N6.C2.D0.R0.S13: RdDqDqs FSM results: Left = 03, Right = 63, center = 33
N0.C2.D0.R0.S08: RdDqDqs FSM results: Left = 05, Right = 63, center = 34
N2.C0.D0.R1.S13: Preamble found at Latency = 007
N4.C0.D0.R0.S16: Preamble found at Latency = 008
N6.C2.D0.R0.S13: RxDqsDelay = 033
N0.C2.D0.R0.S08: RxDqsDelay = 034
N2.C0.D0.R1.S14: Preamble found at Latency = 007
N4.C0.D0.R0.S09: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N6.C2.D0.R0.S14: RdDqDqs FSM results: Left = 05, Right = 63, center = 34
N0.C2.D0.R0.S09: RdDqDqs FSM results: Left = 02, Right = 63, center = 32
N2.C0.D0.R1.S15: Preamble found at Latency = 007
N4.C0.D0.R0.S10: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N6.C2.D0.R0.S14: RxDqsDelay = 034
N0.C2.D0.R0.S09: RxDqsDelay = 032
N2.C0.D0.R1.S17: Preamble found at Latency = 007
N4.C0.D0.R0.S11: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N6.C2.D0.R0.S15: RdDqDqs FSM results: Left = 03, Right = 63, center = 33
N0.C2.D0.R0.S10: RdDqDqs FSM results: Left = 04, Right = 63, center = 33
N2.C0.D0.R1: Preamble found for all upper nibbles, adjusting Pi, Offset to center into preamble
N4.C0.D0.R0.S12: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N6.C2.D0.R0.S15: RxDqsDelay = 033
N0.C2.D0.R0.S10: RxDqsDelay = 033
N2.C0.D0.R1.S09: Total Receive Enable Delay = 1325
N4.C0.D0.R0.S13: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N6.C2.D0.R0.S16: RdDqDqs FSM results: Left = 06, Right = 63, center = 34
N0.C2.D0.R0.S11: RdDqDqs FSM results: Left = 03, Right = 63, center = 33
N2.C0.D0.R1.S10: Total Receive Enable Delay = 1308
N4.C0.D0.R0.S14: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N6.C2.D0.R0.S16: RxDqsDelay = 034
N0.C2.D0.R0.S11: RxDqsDelay = 033
N2.C0.D0.R1.S11: Total Receive Enable Delay = 1279
N4.C0.D0.R0.S15: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N6.C2.D0.R0.S17: RdDqDqs FSM results: Left = 02, Right = 60, center = 31
N0.C2.D0.R0.S12: RdDqDqs FSM results: Left = 04, Right = 63, center = 33
N2.C0.D0.R1.S12: Total Receive Enable Delay = 1260
N4.C0.D0.R0.S16: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N6.C2.D0.R0.S17: RxDqsDelay = 031
N0.C2.D0.R0.S12: RxDqsDelay = 033
N2.C0.D0.R1.S13: Total Receive Enable Delay = 1248
N4.C0.D0.R0.S17: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N6.C2.D0.R1.S00: RdDqDqs FSM results: Left = 01, Right = 59, center = 30
N0.C2.D0.R0.S13: RdDqDqs FSM results: Left = 04, Right = 63, center = 33
N2.C0.D0.R1.S14: Total Receive Enable Delay = 1273
N4.C0.D0.R0.S10: Preamble found at Latency = 007
N6.C2.D0.R1.S00: RxDqsDelay = 030
N0.C2.D0.R0.S13: RxDqsDelay = 033
N2.C0.D0.R1.S15: Total Receive Enable Delay = 1306
N4.C0.D0.R0.S11: Preamble found at Latency = 007
N6.C2.D0.R1.S01: RdDqDqs FSM results: Left = 06, Right = 63, center = 34
N0.C2.D0.R0.S14: RdDqDqs FSM results: Left = 05, Right = 63, center = 34
N2.C0.D0.R1.S16: Total Receive Enable Delay = 1327
N4.C0.D0.R0.S12: Preamble found at Latency = 007
N6.C2.D0.R1.S01: RxDqsDelay = 034
N0.C2.D0.R0.S14: RxDqsDelay = 034
N2.C0.D0.R1.S17: Total Receive Enable Delay = 1244
N4.C0.D0.R0.S13: Preamble found at Latency = 007
N6.C2.D0.R1.S02: RdDqDqs FSM results: Left = 03, Right = 63, center = 33
N0.C2.D0.R0.S15: RdDqDqs FSM results: Left = 05, Right = 63, center = 34
N2.C0.D1.R0: RcvEnFine: Initial RdCmd2RcvEnLatency = 10, Initial RdPtrOffsetRcvEn = 4
N4.C0.D0.R0.S14: Preamble found at Latency = 007
N6.C2.D0.R1.S02: RxDqsDelay = 033
N0.C2.D0.R0.S15: RxDqsDelay = 034
N2.C0.D1.R0.S00: Rcv En Fine Value = 258
N4.C0.D0.R0.S15: Preamble found at Latency = 007
N6.C2.D0.R1.S03: RdDqDqs FSM results: Left = 05, Right = 63, center = 34
N0.C2.D0.R0.S16: RdDqDqs FSM results: Left = 04, Right = 63, center = 33
N2.C0.D1.R0.S01: Rcv En Fine Value = 370
N4.C0.D0.R0.S17: Preamble found at Latency = 007
N6.C2.D0.R1.S03: RxDqsDelay = 034
N0.C2.D0.R0.S16: RxDqsDelay = 033
N2.C0.D1.R0.S02: Rcv En Fine Value = 339
N4.C0.D0.R0: Preamble found for all upper nibbles, adjusting Pi, Offset to center into preamble
N6.C2.D0.R1.S04: RdDqDqs FSM results: Left = 03, Right = 63, center = 33
N0.C2.D0.R0.S17: RdDqDqs FSM results: Left = 07, Right = 63, center = 35
N2.C0.D1.R0.S03: Rcv En Fine Value = 317
N4.C0.D0.R0.S09: Total Receive Enable Delay = 1321
N6.C2.D0.R1.S04: RxDqsDelay = 033
N0.C2.D0.R0.S17: RxDqsDelay = 035
N2.C0.D1.R0.S04: Rcv En Fine Value = 311
N4.C0.D0.R0.S10: Total Receive Enable Delay = 1302
N6.C2.D0.R1.S05: RdDqDqs FSM results: Left = 07, Right = 63, center = 35
N0.C2.D0.R1.S00: RdDqDqs FSM results: Left = 03, Right = 63, center = 33
N2.C0.D1.R0.S05: Rcv En Fine Value = 336
N4.C0.D0.R0.S11: Total Receive Enable Delay = 1275
N6.C2.D0.R1.S05: RxDqsDelay = 035
N0.C2.D0.R1.S00: RxDqsDelay = 033
N2.C0.D1.R0.S06: Rcv En Fine Value = 364
N4.C0.D0.R0.S12: Total Receive Enable Delay = 1253
N6.C2.D0.R1.S06: RdDqDqs FSM results: Left = 05, Right = 63, center = 34
N0.C2.D0.R1.S01: RdDqDqs FSM results: Left = 08, Right = 63, center = 35
N2.C0.D1.R0.S07: Rcv En Fine Value = 261
N4.C0.D0.R0.S13: Total Receive Enable Delay = 1247
N6.C2.D0.R1.S06: RxDqsDelay = 034
N0.C2.D0.R1.S01: RxDqsDelay = 035
N2.C0.D1.R0.S08: Rcv En Fine Value = 309
N4.C0.D0.R0.S14: Total Receive Enable Delay = 1268
N6.C2.D0.R1.S07: RdDqDqs FSM results: Left = 08, Right = 63, center = 35
N0.C2.D0.R1.S02: RdDqDqs FSM results: Left = 04, Right = 63, center = 33
N2.C0.D1.R0.S09: Rcv En Fine Value = 259
N4.C0.D0.R0.S15: Total Receive Enable Delay = 1300
N6.C2.D0.R1.S07: RxDqsDelay = 035
N0.C2.D0.R1.S02: RxDqsDelay = 033
N2.C0.D1.R0.S10: Rcv En Fine Value = 369
N4.C0.D0.R0.S16: Total Receive Enable Delay = 1323
N6.C2.D0.R1.S08: RdDqDqs FSM results: Left = 09, Right = 63, center = 36
N0.C2.D0.R1.S03: RdDqDqs FSM results: Left = 06, Right = 63, center = 34
N2.C0.D1.R0.S11: Rcv En Fine Value = 339
N4.C0.D0.R0.S17: Total Receive Enable Delay = 1239
N6.C2.D0.R1.S08: RxDqsDelay = 036
N0.C2.D0.R1.S03: RxDqsDelay = 034
N2.C0.D1.R0.S12: Rcv En Fine Value = 318
N4.C0.D0.R1: RcvEnFine: Initial RdCmd2RcvEnLatency = 10, Initial RdPtrOffsetRcvEn = 4
N6.C2.D0.R1.S09: RdDqDqs FSM results: Left = 05, Right = 63, center = 34
N0.C2.D0.R1.S04: RdDqDqs FSM results: Left = 03, Right = 63, center = 33
N2.C0.D1.R0.S13: Rcv En Fine Value = 309
N4.C0.D0.R1.S00: Rcv En Fine Value = 266
N6.C2.D0.R1.S09: RxDqsDelay = 034
N0.C2.D0.R1.S04: RxDqsDelay = 033
N2.C0.D1.R0.S14: Rcv En Fine Value = 336
N4.C0.D0.R1.S01: Rcv En Fine Value = 375
N6.C2.D0.R1.S10: RdDqDqs FSM results: Left = 02, Right = 61, center = 31
N0.C2.D0.R1.S05: RdDqDqs FSM results: Left = 07, Right = 63, center = 35
N2.C0.D1.R0.S15: Rcv En Fine Value = 362
N4.C0.D0.R1.S02: Rcv En Fine Value = 348
N6.C2.D0.R1.S10: RxDqsDelay = 031
N0.C2.D0.R1.S05: RxDqsDelay = 035
N2.C0.D1.R0.S16: Rcv En Fine Value = 258
N4.C0.D0.R1.S03: Rcv En Fine Value = 323
N6.C2.D0.R1.S11: RdDqDqs FSM results: Left = 01, Right = 63, center = 32
N0.C2.D0.R1.S06: RdDqDqs FSM results: Left = 07, Right = 63, center = 35
N2.C0.D1.R0.S17: Rcv En Fine Value = 304
N4.C0.D0.R1.S04: Rcv En Fine Value = 316
N6.C2.D0.R1.S11: RxDqsDelay = 032
N0.C2.D0.R1.S06: RxDqsDelay = 035
N2.C0.D1.R0: Starting preamble search lower nibbles
N4.C0.D0.R1.S05: Rcv En Fine Value = 340
N6.C2.D0.R1.S12: RdDqDqs FSM results: Left = 04, Right = 63, center = 33
N0.C2.D0.R1.S07: RdDqDqs FSM results: Left = 05, Right = 63, center = 34
N2.C0.D1.R0.S00: PI = 002, PtrOffset = 004
N4.C0.D0.R1.S06: Rcv En Fine Value = 374
N6.C2.D0.R1.S12: RxDqsDelay = 033
N0.C2.D0.R1.S07: RxDqsDelay = 034
N2.C0.D1.R0.S01: PI = 050, PtrOffset = 005
N4.C0.D0.R1.S07: Rcv En Fine Value = 270
N6.C2.D0.R1.S13: RdDqDqs FSM results: Left = 02, Right = 63, center = 32
N0.C2.D0.R1.S08: RdDqDqs FSM results: Left = 05, Right = 63, center = 34
N2.C0.D1.R0.S02: PI = 019, PtrOffset = 005
N4.C0.D0.R1.S08: Rcv En Fine Value = 315
N6.C2.D0.R1.S13: RxDqsDelay = 032
N0.C2.D0.R1.S08: RxDqsDelay = 034
N2.C0.D1.R0.S03: PI = 061, PtrOffset = 004
N4.C0.D0.R1.S09: Rcv En Fine Value = 267
N6.C2.D0.R1.S14: RdDqDqs FSM results: Left = 04, Right = 63, center = 33
N0.C2.D0.R1.S09: RdDqDqs FSM results: Left = 03, Right = 63, center = 33
N2.C0.D1.R0.S04: PI = 055, PtrOffset = 004
N4.C0.D0.R1.S10: Rcv En Fine Value = 375
N6.C2.D0.R1.S14: RxDqsDelay = 033
N0.C2.D0.R1.S09: RxDqsDelay = 033
N2.C0.D1.R0.S05: PI = 016, PtrOffset = 005
N4.C0.D0.R1.S11: Rcv En Fine Value = 346
N6.C2.D0.R1.S15: RdDqDqs FSM results: Left = 03, Right = 63, center = 33
N0.C2.D0.R1.S10: RdDqDqs FSM results: Left = 03, Right = 63, center = 33
N2.C0.D1.R0.S06: PI = 044, PtrOffset = 005
N4.C0.D0.R1.S12: Rcv En Fine Value = 325
N6.C2.D0.R1.S15: RxDqsDelay = 033
N0.C2.D0.R1.S10: RxDqsDelay = 033
N2.C0.D1.R0.S07: PI = 005, PtrOffset = 004
N4.C0.D0.R1.S13: Rcv En Fine Value = 316
N6.C2.D0.R1.S16: RdDqDqs FSM results: Left = 06, Right = 63, center = 34
N0.C2.D0.R1.S11: RdDqDqs FSM results: Left = 03, Right = 63, center = 33
N2.C0.D1.R0.S08: PI = 053, PtrOffset = 004
N4.C0.D0.R1.S14: Rcv En Fine Value = 336
N6.C2.D0.R1.S16: RxDqsDelay = 034
N0.C2.D0.R1.S11: RxDqsDelay = 033
N2.C0.D1.R0.S00: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N4.C0.D0.R1.S15: Rcv En Fine Value = 372
N6.C2.D0.R1.S17: RdDqDqs FSM results: Left = 02, Right = 59, center = 30
N0.C2.D0.R1.S12: RdDqDqs FSM results: Left = 04, Right = 63, center = 33
N2.C0.D1.R0.S01: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N4.C0.D0.R1.S16: Rcv En Fine Value = 267
N6.C2.D0.R1.S17: RxDqsDelay = 030
N0.C2.D0.R1.S12: RxDqsDelay = 033
N2.C0.D1.R0.S02: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N4.C0.D0.R1.S17: Rcv En Fine Value = 312
N6.C2.D1.R0.S00: RdDqDqs FSM results: Left = 03, Right = 63, center = 33
N0.C2.D0.R1.S13: RdDqDqs FSM results: Left = 04, Right = 63, center = 33
N2.C0.D1.R0.S03: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N4.C0.D0.R1: Starting preamble search lower nibbles
N6.C2.D1.R0.S00: RxDqsDelay = 033
N0.C2.D0.R1.S13: RxDqsDelay = 033
N2.C0.D1.R0.S04: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N4.C0.D0.R1.S00: PI = 010, PtrOffset = 004
N6.C2.D1.R0.S01: RdDqDqs FSM results: Left = 09, Right = 63, center = 36
N0.C2.D0.R1.S14: RdDqDqs FSM results: Left = 03, Right = 63, center = 33
N2.C0.D1.R0.S05: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N4.C0.D0.R1.S01: PI = 055, PtrOffset = 005
N6.C2.D1.R0.S01: RxDqsDelay = 036
N0.C2.D0.R1.S14: RxDqsDelay = 033
N2.C0.D1.R0.S06: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N4.C0.D0.R1.S02: PI = 028, PtrOffset = 005
N6.C2.D1.R0.S02: RdDqDqs FSM results: Left = 08, Right = 63, center = 35
N0.C2.D0.R1.S15: RdDqDqs FSM results: Left = 06, Right = 63, center = 34
N2.C0.D1.R0.S07: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N4.C0.D0.R1.S03: PI = 003, PtrOffset = 005
N6.C2.D1.R0.S02: RxDqsDelay = 035
N0.C2.D0.R1.S15: RxDqsDelay = 034
N2.C0.D1.R0.S08: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N4.C0.D0.R1.S04: PI = 060, PtrOffset = 004
N6.C2.D1.R0.S03: RdDqDqs FSM results: Left = 08, Right = 63, center = 35
N0.C2.D0.R1.S16: RdDqDqs FSM results: Left = 05, Right = 63, center = 34
N2.C0.D1.R0.S00: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N4.C0.D0.R1.S05: PI = 020, PtrOffset = 005
N6.C2.D1.R0.S03: RxDqsDelay = 035
N0.C2.D0.R1.S16: RxDqsDelay = 034
N2.C0.D1.R0.S01: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N4.C0.D0.R1.S06: PI = 054, PtrOffset = 005
N6.C2.D1.R0.S04: RdDqDqs FSM results: Left = 06, Right = 63, center = 34
N0.C2.D0.R1.S17: RdDqDqs FSM results: Left = 05, Right = 63, center = 34
N2.C0.D1.R0.S02: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N4.C0.D0.R1.S07: PI = 014, PtrOffset = 004
N6.C2.D1.R0.S04: RxDqsDelay = 034
N0.C2.D0.R1.S17: RxDqsDelay = 034
N2.C0.D1.R0.S03: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N4.C0.D0.R1.S08: PI = 059, PtrOffset = 004
N6.C2.D1.R0.S05: RdDqDqs FSM results: Left = 09, Right = 63, center = 36
N0.C2.D1.R0.S00: RdDqDqs FSM results: Left = 07, Right = 63, center = 35
N2.C0.D1.R0.S04: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N4.C0.D0.R1.S00: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N6.C2.D1.R0.S05: RxDqsDelay = 036
N0.C2.D1.R0.S00: RxDqsDelay = 035
N2.C0.D1.R0.S05: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N4.C0.D0.R1.S01: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N6.C2.D1.R0.S06: RdDqDqs FSM results: Left = 10, Right = 63, center = 36
N0.C2.D1.R0.S01: RdDqDqs FSM results: Left = 11, Right = 63, center = 37
N2.C0.D1.R0.S06: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N4.C0.D0.R1.S02: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N6.C2.D1.R0.S06: RxDqsDelay = 036
N0.C2.D1.R0.S01: RxDqsDelay = 037
N2.C0.D1.R0.S07: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N4.C0.D0.R1.S03: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N6.C2.D1.R0.S07: RdDqDqs FSM results: Left = 11, Right = 63, center = 37
N0.C2.D1.R0.S02: RdDqDqs FSM results: Left = 09, Right = 63, center = 36
N2.C0.D1.R0.S08: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N4.C0.D0.R1.S04: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N6.C2.D1.R0.S07: RxDqsDelay = 037
N0.C2.D1.R0.S02: RxDqsDelay = 036
N2.C0.D1.R0.S00: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N4.C0.D0.R1.S05: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N6.C2.D1.R0.S08: RdDqDqs FSM results: Left = 11, Right = 63, center = 37
N0.C2.D1.R0.S03: RdDqDqs FSM results: Left = 09, Right = 63, center = 36
N2.C0.D1.R0.S01: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N4.C0.D0.R1.S06: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N6.C2.D1.R0.S08: RxDqsDelay = 037
N0.C2.D1.R0.S03: RxDqsDelay = 036
N2.C0.D1.R0.S02: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N4.C0.D0.R1.S07: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N6.C2.D1.R0.S09: RdDqDqs FSM results: Left = 08, Right = 63, center = 35
N0.C2.D1.R0.S04: RdDqDqs FSM results: Left = 08, Right = 63, center = 35
N2.C0.D1.R0.S03: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N4.C0.D0.R1.S08: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N6.C2.D1.R0.S09: RxDqsDelay = 035
N0.C2.D1.R0.S04: RxDqsDelay = 035
N2.C0.D1.R0.S04: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N4.C0.D0.R1.S00: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N6.C2.D1.R0.S10: RdDqDqs FSM results: Left = 05, Right = 63, center = 34
N0.C2.D1.R0.S05: RdDqDqs FSM results: Left = 09, Right = 63, center = 36
N2.C0.D1.R0.S05: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N4.C0.D0.R1.S01: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N6.C2.D1.R0.S10: RxDqsDelay = 034
N0.C2.D1.R0.S05: RxDqsDelay = 036
N2.C0.D1.R0.S06: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N4.C0.D0.R1.S02: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N6.C2.D1.R0.S11: RdDqDqs FSM results: Left = 04, Right = 63, center = 33
N0.C2.D1.R0.S06: RdDqDqs FSM results: Left = 11, Right = 63, center = 37
N2.C0.D1.R0.S07: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N4.C0.D0.R1.S03: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N6.C2.D1.R0.S11: RxDqsDelay = 033
N0.C2.D1.R0.S06: RxDqsDelay = 037
N2.C0.D1.R0.S08: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N4.C0.D0.R1.S04: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N6.C2.D1.R0.S12: RdDqDqs FSM results: Left = 07, Right = 63, center = 35
N0.C2.D1.R0.S07: RdDqDqs FSM results: Left = 08, Right = 63, center = 35
N2.C0.D1.R0.S00: Preamble found at Latency = 008
N4.C0.D0.R1.S05: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N6.C2.D1.R0.S12: RxDqsDelay = 035
N0.C2.D1.R0.S07: RxDqsDelay = 035
N2.C0.D1.R0.S07: Preamble found at Latency = 008
N4.C0.D0.R1.S06: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N6.C2.D1.R0.S13: RdDqDqs FSM results: Left = 05, Right = 63, center = 34
N0.C2.D1.R0.S08: RdDqDqs FSM results: Left = 09, Right = 63, center = 36
N2.C0.D1.R0.S00: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N4.C0.D0.R1.S07: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N6.C2.D1.R0.S13: RxDqsDelay = 034
N0.C2.D1.R0.S08: RxDqsDelay = 036
N2.C0.D1.R0.S01: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N4.C0.D0.R1.S08: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N6.C2.D1.R0.S14: RdDqDqs FSM results: Left = 08, Right = 63, center = 35
N0.C2.D1.R0.S09: RdDqDqs FSM results: Left = 06, Right = 63, center = 34
N2.C0.D1.R0.S02: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N4.C0.D0.R1.S00: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N6.C2.D1.R0.S14: RxDqsDelay = 035
N0.C2.D1.R0.S09: RxDqsDelay = 034
N2.C0.D1.R0.S03: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N4.C0.D0.R1.S01: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N6.C2.D1.R0.S15: RdDqDqs FSM results: Left = 06, Right = 63, center = 34
N0.C2.D1.R0.S10: RdDqDqs FSM results: Left = 08, Right = 63, center = 35
N2.C0.D1.R0.S04: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N4.C0.D0.R1.S02: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N6.C2.D1.R0.S15: RxDqsDelay = 034
N0.C2.D1.R0.S10: RxDqsDelay = 035
N2.C0.D1.R0.S05: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N4.C0.D0.R1.S03: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N6.C2.D1.R0.S16: RdDqDqs FSM results: Left = 09, Right = 63, center = 36
N0.C2.D1.R0.S11: RdDqDqs FSM results: Left = 05, Right = 63, center = 34
N2.C0.D1.R0.S06: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N4.C0.D0.R1.S04: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N6.C2.D1.R0.S16: RxDqsDelay = 036
N0.C2.D1.R0.S11: RxDqsDelay = 034
N2.C0.D1.R0.S07: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N4.C0.D0.R1.S05: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N6.C2.D1.R0.S17: RdDqDqs FSM results: Left = 04, Right = 63, center = 33
N0.C2.D1.R0.S12: RdDqDqs FSM results: Left = 09, Right = 63, center = 36
N2.C0.D1.R0.S08: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N4.C0.D0.R1.S06: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N6.C2.D1.R0.S17: RxDqsDelay = 033
N0.C2.D1.R0.S12: RxDqsDelay = 036
N2.C0.D1.R0.S01: Preamble found at Latency = 007
N4.C0.D0.R1.S07: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N6.C2.D1.R1.S00: RdDqDqs FSM results: Left = 04, Right = 63, center = 33
N0.C2.D1.R0.S13: RdDqDqs FSM results: Left = 07, Right = 63, center = 35
N2.C0.D1.R0.S02: Preamble found at Latency = 007
N4.C0.D0.R1.S08: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N6.C2.D1.R1.S00: RxDqsDelay = 033
N0.C2.D1.R0.S13: RxDqsDelay = 035
N2.C0.D1.R0.S03: Preamble found at Latency = 007
N4.C0.D0.R1.S00: Preamble found at Latency = 008
N6.C2.D1.R1.S01: RdDqDqs FSM results: Left = 09, Right = 63, center = 36
N0.C2.D1.R0.S14: RdDqDqs FSM results: Left = 08, Right = 63, center = 35
N2.C0.D1.R0.S04: Preamble found at Latency = 007
N4.C0.D0.R1.S07: Preamble found at Latency = 008
N6.C2.D1.R1.S01: RxDqsDelay = 036
N0.C2.D1.R0.S14: RxDqsDelay = 035
N2.C0.D1.R0.S05: Preamble found at Latency = 007
N4.C0.D0.R1.S00: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N6.C2.D1.R1.S02: RdDqDqs FSM results: Left = 07, Right = 63, center = 35
N0.C2.D1.R0.S15: RdDqDqs FSM results: Left = 09, Right = 63, center = 36
N2.C0.D1.R0.S06: Preamble found at Latency = 007
N4.C0.D0.R1.S01: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N6.C2.D1.R1.S02: RxDqsDelay = 035
N0.C2.D1.R0.S15: RxDqsDelay = 036
N2.C0.D1.R0.S08: Preamble found at Latency = 007
N4.C0.D0.R1.S02: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N6.C2.D1.R1.S03: RdDqDqs FSM results: Left = 09, Right = 63, center = 36
N0.C2.D1.R0.S16: RdDqDqs FSM results: Left = 08, Right = 63, center = 35
N2.C0.D1.R0.S00: Total Receive Enable Delay = 1314
N4.C0.D0.R1.S03: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N6.C2.D1.R1.S03: RxDqsDelay = 036
N0.C2.D1.R0.S16: RxDqsDelay = 035
N2.C0.D1.R0.S01: Total Receive Enable Delay = 1298
N4.C0.D0.R1.S04: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N6.C2.D1.R1.S04: RdDqDqs FSM results: Left = 04, Right = 63, center = 33
N0.C2.D1.R0.S17: RdDqDqs FSM results: Left = 10, Right = 63, center = 36
N2.C0.D1.R0.S02: Total Receive Enable Delay = 1267
N4.C0.D0.R1.S05: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N6.C2.D1.R1.S04: RxDqsDelay = 033
N0.C2.D1.R0.S17: RxDqsDelay = 036
N2.C0.D1.R0.S03: Total Receive Enable Delay = 1245
N4.C0.D0.R1.S06: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N6.C2.D1.R1.S05: RdDqDqs FSM results: Left = 09, Right = 63, center = 36
N0.C2.D1.R1.S00: RdDqDqs FSM results: Left = 07, Right = 63, center = 35
N2.C0.D1.R0.S04: Total Receive Enable Delay = 1239
N4.C0.D0.R1.S07: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N6.C2.D1.R1.S05: RxDqsDelay = 036
N0.C2.D1.R1.S00: RxDqsDelay = 035
N2.C0.D1.R0.S05: Total Receive Enable Delay = 1264
N4.C0.D0.R1.S08: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N6.C2.D1.R1.S06: RdDqDqs FSM results: Left = 10, Right = 63, center = 36
N0.C2.D1.R1.S01: RdDqDqs FSM results: Left = 11, Right = 63, center = 37
N2.C0.D1.R0.S06: Total Receive Enable Delay = 1292
N4.C0.D0.R1.S01: Preamble found at Latency = 007
N6.C2.D1.R1.S06: RxDqsDelay = 036
N0.C2.D1.R1.S01: RxDqsDelay = 037
N2.C0.D1.R0.S07: Total Receive Enable Delay = 1317
N4.C0.D0.R1.S02: Preamble found at Latency = 007
N6.C2.D1.R1.S07: RdDqDqs FSM results: Left = 11, Right = 63, center = 37
N0.C2.D1.R1.S02: RdDqDqs FSM results: Left = 09, Right = 63, center = 36
N2.C0.D1.R0.S08: Total Receive Enable Delay = 1237
N4.C0.D0.R1.S03: Preamble found at Latency = 007
N6.C2.D1.R1.S07: RxDqsDelay = 037
N0.C2.D1.R1.S02: RxDqsDelay = 036
N2.C0.D1.R0: Starting preamble search upper nibbles
N4.C0.D0.R1.S04: Preamble found at Latency = 007
N6.C2.D1.R1.S08: RdDqDqs FSM results: Left = 11, Right = 63, center = 37
N0.C2.D1.R1.S03: RdDqDqs FSM results: Left = 09, Right = 63, center = 36
N2.C0.D1.R0.S09: PI = 003, PtrOffset = 004
N4.C0.D0.R1.S05: Preamble found at Latency = 007
N6.C2.D1.R1.S08: RxDqsDelay = 037
N0.C2.D1.R1.S03: RxDqsDelay = 036
N2.C0.D1.R0.S10: PI = 049, PtrOffset = 005
N4.C0.D0.R1.S06: Preamble found at Latency = 007
N6.C2.D1.R1.S09: RdDqDqs FSM results: Left = 08, Right = 63, center = 35
N0.C2.D1.R1.S04: RdDqDqs FSM results: Left = 08, Right = 63, center = 35
N2.C0.D1.R0.S11: PI = 019, PtrOffset = 005
N4.C0.D0.R1.S08: Preamble found at Latency = 007
N6.C2.D1.R1.S09: RxDqsDelay = 035
N0.C2.D1.R1.S04: RxDqsDelay = 035
N2.C0.D1.R0.S12: PI = 062, PtrOffset = 004
N4.C0.D0.R1.S00: Total Receive Enable Delay = 1322
N6.C2.D1.R1.S10: RdDqDqs FSM results: Left = 05, Right = 63, center = 34
N0.C2.D1.R1.S05: RdDqDqs FSM results: Left = 08, Right = 63, center = 35
N2.C0.D1.R0.S13: PI = 053, PtrOffset = 004
N4.C0.D0.R1.S01: Total Receive Enable Delay = 1303
N6.C2.D1.R1.S10: RxDqsDelay = 034
N0.C2.D1.R1.S05: RxDqsDelay = 035
N2.C0.D1.R0.S14: PI = 016, PtrOffset = 005
N4.C0.D0.R1.S02: Total Receive Enable Delay = 1276
N6.C2.D1.R1.S11: RdDqDqs FSM results: Left = 05, Right = 63, center = 34
N0.C2.D1.R1.S06: RdDqDqs FSM results: Left = 10, Right = 63, center = 36
N2.C0.D1.R0.S15: PI = 042, PtrOffset = 005
N4.C0.D0.R1.S03: Total Receive Enable Delay = 1251
N6.C2.D1.R1.S11: RxDqsDelay = 034
N0.C2.D1.R1.S06: RxDqsDelay = 036
N2.C0.D1.R0.S16: PI = 002, PtrOffset = 004
N4.C0.D0.R1.S04: Total Receive Enable Delay = 1244
N6.C2.D1.R1.S12: RdDqDqs FSM results: Left = 08, Right = 63, center = 35
N0.C2.D1.R1.S07: RdDqDqs FSM results: Left = 09, Right = 63, center = 36
N2.C0.D1.R0.S17: PI = 048, PtrOffset = 004
N4.C0.D0.R1.S05: Total Receive Enable Delay = 1268
N6.C2.D1.R1.S12: RxDqsDelay = 035
N0.C2.D1.R1.S07: RxDqsDelay = 036
N2.C0.D1.R0.S09: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N4.C0.D0.R1.S06: Total Receive Enable Delay = 1302
N6.C2.D1.R1.S13: RdDqDqs FSM results: Left = 06, Right = 63, center = 34
N0.C2.D1.R1.S08: RdDqDqs FSM results: Left = 09, Right = 63, center = 36
N2.C0.D1.R0.S10: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N4.C0.D0.R1.S07: Total Receive Enable Delay = 1326
N6.C2.D1.R1.S13: RxDqsDelay = 034
N0.C2.D1.R1.S08: RxDqsDelay = 036
N2.C0.D1.R0.S11: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N4.C0.D0.R1.S08: Total Receive Enable Delay = 1243
N6.C2.D1.R1.S14: RdDqDqs FSM results: Left = 07, Right = 63, center = 35
N0.C2.D1.R1.S09: RdDqDqs FSM results: Left = 06, Right = 63, center = 34
N2.C0.D1.R0.S12: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N4.C0.D0.R1: Starting preamble search upper nibbles
N6.C2.D1.R1.S14: RxDqsDelay = 035
N0.C2.D1.R1.S09: RxDqsDelay = 034
N2.C0.D1.R0.S13: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N4.C0.D0.R1.S09: PI = 011, PtrOffset = 004
N6.C2.D1.R1.S15: RdDqDqs FSM results: Left = 06, Right = 63, center = 34
N0.C2.D1.R1.S10: RdDqDqs FSM results: Left = 09, Right = 63, center = 36
N2.C0.D1.R0.S14: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N4.C0.D0.R1.S10: PI = 055, PtrOffset = 005
N6.C2.D1.R1.S15: RxDqsDelay = 034
N0.C2.D1.R1.S10: RxDqsDelay = 036
N2.C0.D1.R0.S15: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N4.C0.D0.R1.S11: PI = 026, PtrOffset = 005
N6.C2.D1.R1.S16: RdDqDqs FSM results: Left = 09, Right = 63, center = 36
N0.C2.D1.R1.S11: RdDqDqs FSM results: Left = 06, Right = 63, center = 34
N2.C0.D1.R0.S16: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N4.C0.D0.R1.S12: PI = 005, PtrOffset = 005
N6.C2.D1.R1.S16: RxDqsDelay = 036
N0.C2.D1.R1.S11: RxDqsDelay = 034
N2.C0.D1.R0.S17: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N4.C0.D0.R1.S13: PI = 060, PtrOffset = 004
N6.C2.D1.R1.S17: RdDqDqs FSM results: Left = 04, Right = 63, center = 33
N0.C2.D1.R1.S12: RdDqDqs FSM results: Left = 09, Right = 63, center = 36
N2.C0.D1.R0.S09: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N4.C0.D0.R1.S14: PI = 016, PtrOffset = 005
N6.C2.D1.R1.S17: RxDqsDelay = 033
N0.C2.D1.R1.S12: RxDqsDelay = 036
N2.C0.D1.R0.S10: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N4.C0.D0.R1.S15: PI = 052, PtrOffset = 005
START_DATA_RX_DQS
N0.C2.D1.R1.S13: RdDqDqs FSM results: Left = 08, Right = 63, center = 35
N2.C0.D1.R0.S11: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N4.C0.D0.R1.S16: PI = 011, PtrOffset = 004
N6.C2.R0.S00: PI = 31
N0.C2.D1.R1.S13: RxDqsDelay = 035
N2.C0.D1.R0.S12: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N4.C0.D0.R1.S17: PI = 056, PtrOffset = 004
N6.C2.R0.S01: PI = 34
N0.C2.D1.R1.S14: RdDqDqs FSM results: Left = 07, Right = 63, center = 35
N2.C0.D1.R0.S13: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N4.C0.D0.R1.S09: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N6.C2.R0.S02: PI = 33
N0.C2.D1.R1.S14: RxDqsDelay = 035
N2.C0.D1.R0.S14: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N4.C0.D0.R1.S10: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N6.C2.R0.S03: PI = 33
N0.C2.D1.R1.S15: RdDqDqs FSM results: Left = 08, Right = 63, center = 35
N2.C0.D1.R0.S15: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N4.C0.D0.R1.S11: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N6.C2.R0.S04: PI = 31
N0.C2.D1.R1.S15: RxDqsDelay = 035
N2.C0.D1.R0.S16: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N4.C0.D0.R1.S12: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N6.C2.R0.S05: PI = 35
N0.C2.D1.R1.S16: RdDqDqs FSM results: Left = 09, Right = 63, center = 36
N2.C0.D1.R0.S17: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N4.C0.D0.R1.S13: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N6.C2.R0.S06: PI = 34
N0.C2.D1.R1.S16: RxDqsDelay = 036
N2.C0.D1.R0.S09: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N4.C0.D0.R1.S14: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N6.C2.R0.S07: PI = 35
N0.C2.D1.R1.S17: RdDqDqs FSM results: Left = 09, Right = 63, center = 36
N2.C0.D1.R0.S10: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N4.C0.D0.R1.S15: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N6.C2.R0.S08: PI = 36
N0.C2.D1.R1.S17: RxDqsDelay = 036
N2.C0.D1.R0.S11: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N4.C0.D0.R1.S16: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N6.C2.R0.S09: PI = 33
START_DATA_RX_DQS
N2.C0.D1.R0.S12: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N4.C0.D0.R1.S17: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N6.C2.R0.S10: PI = 31
N0.C2.R0.S00: PI = 33
N2.C0.D1.R0.S13: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N4.C0.D0.R1.S09: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N6.C2.R0.S11: PI = 32
N0.C2.R0.S01: PI = 35
N2.C0.D1.R0.S14: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N4.C0.D0.R1.S10: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N6.C2.R0.S12: PI = 33
N0.C2.R0.S02: PI = 33
N2.C0.D1.R0.S15: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N4.C0.D0.R1.S11: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N6.C2.R0.S13: PI = 32
N0.C2.R0.S03: PI = 34
N2.C0.D1.R0.S16: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N4.C0.D0.R1.S12: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N6.C2.R0.S14: PI = 33
N0.C2.R0.S04: PI = 33
N2.C0.D1.R0.S17: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N4.C0.D0.R1.S13: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N6.C2.R0.S15: PI = 33
N0.C2.R0.S05: PI = 35
N2.C0.D1.R0.S09: Preamble found at Latency = 008
N4.C0.D0.R1.S14: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N6.C2.R0.S16: PI = 34
N0.C2.R0.S06: PI = 34
N2.C0.D1.R0.S16: Preamble found at Latency = 008
N4.C0.D0.R1.S15: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N6.C2.R0.S17: PI = 30
N0.C2.R0.S07: PI = 34
N2.C0.D1.R0.S09: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N4.C0.D0.R1.S16: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N6.C2.R0.S00: PI = 31
N0.C2.R0.S08: PI = 34
N2.C0.D1.R0.S10: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N4.C0.D0.R1.S17: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N6.C2.R0.S01: PI = 34
N0.C2.R0.S09: PI = 32
N2.C0.D1.R0.S11: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N4.C0.D0.R1.S09: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N6.C2.R0.S02: PI = 33
N0.C2.R0.S10: PI = 33
N2.C0.D1.R0.S12: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N4.C0.D0.R1.S10: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N6.C2.R0.S03: PI = 33
N0.C2.R0.S11: PI = 33
N2.C0.D1.R0.S13: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N4.C0.D0.R1.S11: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N6.C2.R0.S04: PI = 31
N0.C2.R0.S12: PI = 33
N2.C0.D1.R0.S14: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N4.C0.D0.R1.S12: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N6.C2.R0.S05: PI = 35
N0.C2.R0.S13: PI = 33
N2.C0.D1.R0.S15: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N4.C0.D0.R1.S13: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N6.C2.R0.S06: PI = 34
N0.C2.R0.S14: PI = 33
N2.C0.D1.R0.S16: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N4.C0.D0.R1.S14: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N6.C2.R0.S07: PI = 35
N0.C2.R0.S15: PI = 34
N2.C0.D1.R0.S17: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N4.C0.D0.R1.S15: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N6.C2.R0.S08: PI = 36
N0.C2.R0.S16: PI = 33
N2.C0.D1.R0.S10: Preamble found at Latency = 007
N4.C0.D0.R1.S16: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N6.C2.R0.S09: PI = 33
N0.C2.R0.S17: PI = 34
N2.C0.D1.R0.S11: Preamble found at Latency = 007
N4.C0.D0.R1.S17: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N6.C2.R0.S10: PI = 31
N0.C2.R0.S00: PI = 33
N2.C0.D1.R0.S12: Preamble found at Latency = 007
N4.C0.D0.R1.S09: Preamble found at Latency = 008
N6.C2.R0.S11: PI = 32
N0.C2.R0.S01: PI = 35
N2.C0.D1.R0.S13: Preamble found at Latency = 007
N4.C0.D0.R1.S16: Preamble found at Latency = 008
N6.C2.R0.S12: PI = 33
N0.C2.R0.S02: PI = 33
N2.C0.D1.R0.S14: Preamble found at Latency = 007
N4.C0.D0.R1.S09: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N6.C2.R0.S13: PI = 32
N0.C2.R0.S03: PI = 34
N2.C0.D1.R0.S15: Preamble found at Latency = 007
N4.C0.D0.R1.S10: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N6.C2.R0.S14: PI = 33
N0.C2.R0.S04: PI = 33
N2.C0.D1.R0.S17: Preamble found at Latency = 007
N4.C0.D0.R1.S11: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N6.C2.R0.S15: PI = 33
N0.C2.R0.S05: PI = 35
N2.C0.D1.R0: Preamble found for all upper nibbles, adjusting Pi, Offset to center into preamble
N4.C0.D0.R1.S12: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N6.C2.R0.S16: PI = 34
N0.C2.R0.S06: PI = 34
N2.C0.D1.R0.S09: Total Receive Enable Delay = 1315
N4.C0.D0.R1.S13: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N6.C2.R0.S17: PI = 30
N0.C2.R0.S07: PI = 34
N2.C0.D1.R0.S10: Total Receive Enable Delay = 1297
N4.C0.D0.R1.S14: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N6.C2.R2.S00: PI = 33
N0.C2.R0.S08: PI = 34
N2.C0.D1.R0.S11: Total Receive Enable Delay = 1267
N4.C0.D0.R1.S15: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N6.C2.R2.S01: PI = 36
N0.C2.R0.S09: PI = 32
N2.C0.D1.R0.S12: Total Receive Enable Delay = 1246
N4.C0.D0.R1.S16: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N6.C2.R2.S02: PI = 35
N0.C2.R0.S10: PI = 33
N2.C0.D1.R0.S13: Total Receive Enable Delay = 1237
N4.C0.D0.R1.S17: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N6.C2.R2.S03: PI = 35
N0.C2.R0.S11: PI = 33
N2.C0.D1.R0.S14: Total Receive Enable Delay = 1264
N4.C0.D0.R1.S10: Preamble found at Latency = 007
N6.C2.R2.S04: PI = 33
N0.C2.R0.S12: PI = 33
N2.C0.D1.R0.S15: Total Receive Enable Delay = 1290
N4.C0.D0.R1.S11: Preamble found at Latency = 007
N6.C2.R2.S05: PI = 36
N0.C2.R0.S13: PI = 33
N2.C0.D1.R0.S16: Total Receive Enable Delay = 1314
N4.C0.D0.R1.S12: Preamble found at Latency = 007
N6.C2.R2.S06: PI = 36
N0.C2.R0.S14: PI = 33
N2.C0.D1.R0.S17: Total Receive Enable Delay = 1232
N4.C0.D0.R1.S13: Preamble found at Latency = 007
N6.C2.R2.S07: PI = 37
N0.C2.R0.S15: PI = 34
N2.C0.D1.R1: RcvEnFine: Initial RdCmd2RcvEnLatency = 10, Initial RdPtrOffsetRcvEn = 4
N4.C0.D0.R1.S14: Preamble found at Latency = 007
N6.C2.R2.S08: PI = 37
N0.C2.R0.S16: PI = 33
N2.C0.D1.R1.S00: Rcv En Fine Value = 257
N4.C0.D0.R1.S15: Preamble found at Latency = 007
N6.C2.R2.S09: PI = 35
N0.C2.R0.S17: PI = 34
N2.C0.D1.R1.S01: Rcv En Fine Value = 369
N4.C0.D0.R1.S17: Preamble found at Latency = 007
N6.C2.R2.S10: PI = 34
N0.C2.R2.S00: PI = 35
N2.C0.D1.R1.S02: Rcv En Fine Value = 339
N4.C0.D0.R1: Preamble found for all upper nibbles, adjusting Pi, Offset to center into preamble
N6.C2.R2.S11: PI = 33
N0.C2.R2.S01: PI = 37
N2.C0.D1.R1.S03: Rcv En Fine Value = 317
N4.C0.D0.R1.S09: Total Receive Enable Delay = 1323
N6.C2.R2.S12: PI = 35
N0.C2.R2.S02: PI = 36
N2.C0.D1.R1.S04: Rcv En Fine Value = 310
N4.C0.D0.R1.S10: Total Receive Enable Delay = 1303
N6.C2.R2.S13: PI = 34
N0.C2.R2.S03: PI = 36
N2.C0.D1.R1.S05: Rcv En Fine Value = 335
N4.C0.D0.R1.S11: Total Receive Enable Delay = 1274
N6.C2.R2.S14: PI = 35
N0.C2.R2.S04: PI = 35
N2.C0.D1.R1.S06: Rcv En Fine Value = 366
N4.C0.D0.R1.S12: Total Receive Enable Delay = 1253
N6.C2.R2.S15: PI = 34
N0.C2.R2.S05: PI = 35
N2.C0.D1.R1.S07: Rcv En Fine Value = 259
N4.C0.D0.R1.S13: Total Receive Enable Delay = 1244
N6.C2.R2.S16: PI = 36
N0.C2.R2.S06: PI = 36
N2.C0.D1.R1.S08: Rcv En Fine Value = 307
N4.C0.D0.R1.S14: Total Receive Enable Delay = 1264
N6.C2.R2.S17: PI = 33
N0.C2.R2.S07: PI = 35
N2.C0.D1.R1.S09: Rcv En Fine Value = 258
N4.C0.D0.R1.S15: Total Receive Enable Delay = 1300
N6.C2.R2.S00: PI = 33
N0.C2.R2.S08: PI = 36
N2.C0.D1.R1.S10: Rcv En Fine Value = 365
N4.C0.D0.R1.S16: Total Receive Enable Delay = 1323
N6.C2.R2.S01: PI = 36
N0.C2.R2.S09: PI = 34
N2.C0.D1.R1.S11: Rcv En Fine Value = 338
N4.C0.D0.R1.S17: Total Receive Enable Delay = 1240
N6.C2.R2.S02: PI = 35
N0.C2.R2.S10: PI = 35
N2.C0.D1.R1.S12: Rcv En Fine Value = 317
N4.C0.D1.R0: RcvEnFine: Initial RdCmd2RcvEnLatency = 10, Initial RdPtrOffsetRcvEn = 4
N6.C2.R2.S03: PI = 35
N0.C2.R2.S11: PI = 34
N2.C0.D1.R1.S13: Rcv En Fine Value = 308
N4.C0.D1.R0.S00: Rcv En Fine Value = 380
N6.C2.R2.S04: PI = 33
N0.C2.R2.S12: PI = 36
N2.C0.D1.R1.S14: Rcv En Fine Value = 332
N4.C0.D1.R0.S01: Rcv En Fine Value = 359
N6.C2.R2.S05: PI = 36
N0.C2.R2.S13: PI = 35
N2.C0.D1.R1.S15: Rcv En Fine Value = 365
N4.C0.D1.R0.S02: Rcv En Fine Value = 329
N6.C2.R2.S06: PI = 36
N0.C2.R2.S14: PI = 35
N2.C0.D1.R1.S16: Rcv En Fine Value = 259
N4.C0.D1.R0.S03: Rcv En Fine Value = 308
N6.C2.R2.S07: PI = 37
N0.C2.R2.S15: PI = 35
N2.C0.D1.R1.S17: Rcv En Fine Value = 305
N4.C0.D1.R0.S04: Rcv En Fine Value = 302
N6.C2.R2.S08: PI = 37
N0.C2.R2.S16: PI = 35
N2.C0.D1.R1: Starting preamble search lower nibbles
N4.C0.D1.R0.S05: Rcv En Fine Value = 327
N6.C2.R2.S09: PI = 35
N0.C2.R2.S17: PI = 36
N2.C0.D1.R1.S00: PI = 001, PtrOffset = 004
N4.C0.D1.R0.S06: Rcv En Fine Value = 361
N6.C2.R2.S10: PI = 34
N0.C2.R2.S00: PI = 35
N2.C0.D1.R1.S01: PI = 049, PtrOffset = 005
N4.C0.D1.R0.S07: Rcv En Fine Value = 381
N6.C2.R2.S11: PI = 33
N0.C2.R2.S01: PI = 37
N2.C0.D1.R1.S02: PI = 019, PtrOffset = 005
N4.C0.D1.R0.S08: Rcv En Fine Value = 298
N6.C2.R2.S12: PI = 35
N0.C2.R2.S02: PI = 36
N2.C0.D1.R1.S03: PI = 061, PtrOffset = 004
N4.C0.D1.R0.S09: Rcv En Fine Value = 378
N6.C2.R2.S13: PI = 34
N0.C2.R2.S03: PI = 36
N2.C0.D1.R1.S04: PI = 054, PtrOffset = 004
N4.C0.D1.R0.S10: Rcv En Fine Value = 360
N6.C2.R2.S14: PI = 35
N0.C2.R2.S04: PI = 35
N2.C0.D1.R1.S05: PI = 015, PtrOffset = 005
N4.C0.D1.R0.S11: Rcv En Fine Value = 331
N6.C2.R2.S15: PI = 34
N0.C2.R2.S05: PI = 35
N2.C0.D1.R1.S06: PI = 046, PtrOffset = 005
N4.C0.D1.R0.S12: Rcv En Fine Value = 307
N6.C2.R2.S16: PI = 36
N0.C2.R2.S06: PI = 36
N2.C0.D1.R1.S07: PI = 003, PtrOffset = 004
N4.C0.D1.R0.S13: Rcv En Fine Value = 304
N6.C2.R2.S17: PI = 33
N0.C2.R2.S07: PI = 35
N2.C0.D1.R1.S08: PI = 051, PtrOffset = 004
N4.C0.D1.R0.S14: Rcv En Fine Value = 323
STOP_DATA_RX_DQS
N0.C2.R2.S08: PI = 36
N2.C0.D1.R1.S00: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N4.C0.D1.R0.S15: Rcv En Fine Value = 357
N6.C3.D0.R0.S00: RdDqDqs FSM results: Left = 03, Right = 59, center = 31
N0.C2.R2.S09: PI = 34
N2.C0.D1.R1.S01: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N4.C0.D1.R0.S16: Rcv En Fine Value = 378
N6.C3.D0.R0.S00: RxDqsDelay = 031
N0.C2.R2.S10: PI = 35
N2.C0.D1.R1.S02: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N4.C0.D1.R0.S17: Rcv En Fine Value = 296
N6.C3.D0.R0.S01: RdDqDqs FSM results: Left = 03, Right = 63, center = 33
N0.C2.R2.S11: PI = 34
N2.C0.D1.R1.S03: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N4.C0.D1.R0: Starting preamble search lower nibbles
N6.C3.D0.R0.S01: RxDqsDelay = 033
N0.C2.R2.S12: PI = 36
N2.C0.D1.R1.S04: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N4.C0.D1.R0.S00: PI = 060, PtrOffset = 005
N6.C3.D0.R0.S02: RdDqDqs FSM results: Left = 03, Right = 63, center = 33
N0.C2.R2.S13: PI = 35
N2.C0.D1.R1.S05: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N4.C0.D1.R0.S01: PI = 039, PtrOffset = 005
N6.C3.D0.R0.S02: RxDqsDelay = 033
N0.C2.R2.S14: PI = 35
N2.C0.D1.R1.S06: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N4.C0.D1.R0.S02: PI = 009, PtrOffset = 005
N6.C3.D0.R0.S03: RdDqDqs FSM results: Left = 04, Right = 63, center = 33
N0.C2.R2.S15: PI = 35
N2.C0.D1.R1.S07: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N4.C0.D1.R0.S03: PI = 052, PtrOffset = 004
N6.C3.D0.R0.S03: RxDqsDelay = 033
N0.C2.R2.S16: PI = 35
N2.C0.D1.R1.S08: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N4.C0.D1.R0.S04: PI = 046, PtrOffset = 004
N6.C3.D0.R0.S04: RdDqDqs FSM results: Left = 10, Right = 63, center = 36
N0.C2.R2.S17: PI = 36
N2.C0.D1.R1.S00: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N4.C0.D1.R0.S05: PI = 007, PtrOffset = 005
N6.C3.D0.R0.S04: RxDqsDelay = 036
STOP_DATA_RX_DQS
N2.C0.D1.R1.S01: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N4.C0.D1.R0.S06: PI = 041, PtrOffset = 005
N6.C3.D0.R0.S05: RdDqDqs FSM results: Left = 06, Right = 63, center = 34
N0.C3.D0.R0.S00: RdDqDqs FSM results: Left = 06, Right = 63, center = 34
N2.C0.D1.R1.S02: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N4.C0.D1.R0.S07: PI = 061, PtrOffset = 005
N6.C3.D0.R0.S05: RxDqsDelay = 034
N0.C3.D0.R0.S00: RxDqsDelay = 034
N2.C0.D1.R1.S03: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N4.C0.D1.R0.S08: PI = 042, PtrOffset = 004
N6.C3.D0.R0.S06: RdDqDqs FSM results: Left = 05, Right = 63, center = 34
N0.C3.D0.R0.S01: RdDqDqs FSM results: Left = 05, Right = 63, center = 34
N2.C0.D1.R1.S04: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N4.C0.D1.R0.S00: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N6.C3.D0.R0.S06: RxDqsDelay = 034
N0.C3.D0.R0.S01: RxDqsDelay = 034
N2.C0.D1.R1.S05: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N4.C0.D1.R0.S01: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N6.C3.D0.R0.S07: RdDqDqs FSM results: Left = 07, Right = 63, center = 35
N0.C3.D0.R0.S02: RdDqDqs FSM results: Left = 05, Right = 63, center = 34
N2.C0.D1.R1.S06: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N4.C0.D1.R0.S02: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N6.C3.D0.R0.S07: RxDqsDelay = 035
N0.C3.D0.R0.S02: RxDqsDelay = 034
N2.C0.D1.R1.S07: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N4.C0.D1.R0.S03: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N6.C3.D0.R0.S08: RdDqDqs FSM results: Left = 03, Right = 63, center = 33
N0.C3.D0.R0.S03: RdDqDqs FSM results: Left = 05, Right = 63, center = 34
N2.C0.D1.R1.S08: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N4.C0.D1.R0.S04: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N6.C3.D0.R0.S08: RxDqsDelay = 033
N0.C3.D0.R0.S03: RxDqsDelay = 034
N2.C0.D1.R1.S00: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N4.C0.D1.R0.S05: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N6.C3.D0.R0.S09: RdDqDqs FSM results: Left = 06, Right = 63, center = 34
N0.C3.D0.R0.S04: RdDqDqs FSM results: Left = 07, Right = 63, center = 35
N2.C0.D1.R1.S01: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N4.C0.D1.R0.S06: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N6.C3.D0.R0.S09: RxDqsDelay = 034
N0.C3.D0.R0.S04: RxDqsDelay = 035
N2.C0.D1.R1.S02: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N4.C0.D1.R0.S07: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N6.C3.D0.R0.S10: RdDqDqs FSM results: Left = 03, Right = 59, center = 31
N0.C3.D0.R0.S05: RdDqDqs FSM results: Left = 05, Right = 63, center = 34
N2.C0.D1.R1.S03: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N4.C0.D1.R0.S08: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N6.C3.D0.R0.S10: RxDqsDelay = 031
N0.C3.D0.R0.S05: RxDqsDelay = 034
N2.C0.D1.R1.S04: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N4.C0.D1.R0.S00: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N6.C3.D0.R0.S11: RdDqDqs FSM results: Left = 03, Right = 63, center = 33
N0.C3.D0.R0.S06: RdDqDqs FSM results: Left = 07, Right = 63, center = 35
N2.C0.D1.R1.S05: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N4.C0.D1.R0.S01: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N6.C3.D0.R0.S11: RxDqsDelay = 033
N0.C3.D0.R0.S06: RxDqsDelay = 035
N2.C0.D1.R1.S06: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N4.C0.D1.R0.S02: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N6.C3.D0.R0.S12: RdDqDqs FSM results: Left = 06, Right = 63, center = 34
N0.C3.D0.R0.S07: RdDqDqs FSM results: Left = 03, Right = 63, center = 33
N2.C0.D1.R1.S07: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N4.C0.D1.R0.S03: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N6.C3.D0.R0.S12: RxDqsDelay = 034
N0.C3.D0.R0.S07: RxDqsDelay = 033
N2.C0.D1.R1.S08: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N4.C0.D1.R0.S04: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N6.C3.D0.R0.S13: RdDqDqs FSM results: Left = 06, Right = 63, center = 34
N0.C3.D0.R0.S08: RdDqDqs FSM results: Left = 03, Right = 63, center = 33
N2.C0.D1.R1.S00: Preamble found at Latency = 008
N4.C0.D1.R0.S05: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N6.C3.D0.R0.S13: RxDqsDelay = 034
N0.C3.D0.R0.S08: RxDqsDelay = 033
N2.C0.D1.R1.S07: Preamble found at Latency = 008
N4.C0.D1.R0.S06: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N6.C3.D0.R0.S14: RdDqDqs FSM results: Left = 03, Right = 58, center = 30
N0.C3.D0.R0.S09: RdDqDqs FSM results: Left = 10, Right = 63, center = 36
N2.C0.D1.R1.S00: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N4.C0.D1.R0.S07: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N6.C3.D0.R0.S14: RxDqsDelay = 030
N0.C3.D0.R0.S09: RxDqsDelay = 036
N2.C0.D1.R1.S01: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N4.C0.D1.R0.S08: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N6.C3.D0.R0.S15: RdDqDqs FSM results: Left = 03, Right = 60, center = 31
N0.C3.D0.R0.S10: RdDqDqs FSM results: Left = 04, Right = 63, center = 33
N2.C0.D1.R1.S02: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N4.C0.D1.R0.S00: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N6.C3.D0.R0.S15: RxDqsDelay = 031
N0.C3.D0.R0.S10: RxDqsDelay = 033
N2.C0.D1.R1.S03: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N4.C0.D1.R0.S01: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N6.C3.D0.R0.S16: RdDqDqs FSM results: Left = 04, Right = 63, center = 33
N0.C3.D0.R0.S11: RdDqDqs FSM results: Left = 02, Right = 63, center = 32
N2.C0.D1.R1.S04: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N4.C0.D1.R0.S02: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N6.C3.D0.R0.S16: RxDqsDelay = 033
N0.C3.D0.R0.S11: RxDqsDelay = 032
N2.C0.D1.R1.S05: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N4.C0.D1.R0.S03: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N6.C3.D0.R0.S17: RdDqDqs FSM results: Left = 04, Right = 63, center = 33
N0.C3.D0.R0.S12: RdDqDqs FSM results: Left = 05, Right = 63, center = 34
N2.C0.D1.R1.S06: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N4.C0.D1.R0.S04: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N6.C3.D0.R0.S17: RxDqsDelay = 033
N0.C3.D0.R0.S12: RxDqsDelay = 034
N2.C0.D1.R1.S07: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N4.C0.D1.R0.S05: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N6.C3.D0.R1.S00: RdDqDqs FSM results: Left = 03, Right = 60, center = 31
N0.C3.D0.R0.S13: RdDqDqs FSM results: Left = 08, Right = 63, center = 35
N2.C0.D1.R1.S08: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N4.C0.D1.R0.S06: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N6.C3.D0.R1.S00: RxDqsDelay = 031
N0.C3.D0.R0.S13: RxDqsDelay = 035
N2.C0.D1.R1.S01: Preamble found at Latency = 007
N4.C0.D1.R0.S07: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N6.C3.D0.R1.S01: RdDqDqs FSM results: Left = 04, Right = 63, center = 33
N0.C3.D0.R0.S14: RdDqDqs FSM results: Left = 03, Right = 63, center = 33
N2.C0.D1.R1.S02: Preamble found at Latency = 007
N4.C0.D1.R0.S08: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N6.C3.D0.R1.S01: RxDqsDelay = 033
N0.C3.D0.R0.S14: RxDqsDelay = 033
N2.C0.D1.R1.S03: Preamble found at Latency = 007
N4.C0.D1.R0.S00: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N6.C3.D0.R1.S02: RdDqDqs FSM results: Left = 03, Right = 63, center = 33
N0.C3.D0.R0.S15: RdDqDqs FSM results: Left = 05, Right = 63, center = 34
N2.C0.D1.R1.S04: Preamble found at Latency = 007
N4.C0.D1.R0.S01: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N6.C3.D0.R1.S02: RxDqsDelay = 033
N0.C3.D0.R0.S15: RxDqsDelay = 034
N2.C0.D1.R1.S05: Preamble found at Latency = 007
N4.C0.D1.R0.S02: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N6.C3.D0.R1.S03: RdDqDqs FSM results: Left = 04, Right = 63, center = 33
N0.C3.D0.R0.S16: RdDqDqs FSM results: Left = 04, Right = 63, center = 33
N2.C0.D1.R1.S06: Preamble found at Latency = 007
N4.C0.D1.R0.S03: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N6.C3.D0.R1.S03: RxDqsDelay = 033
N0.C3.D0.R0.S16: RxDqsDelay = 033
N2.C0.D1.R1.S08: Preamble found at Latency = 007
N4.C0.D1.R0.S04: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N6.C3.D0.R1.S04: RdDqDqs FSM results: Left = 10, Right = 63, center = 36
N0.C3.D0.R0.S17: RdDqDqs FSM results: Left = 03, Right = 63, center = 33
N2.C0.D1.R1.S00: Total Receive Enable Delay = 1313
N4.C0.D1.R0.S05: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N6.C3.D0.R1.S04: RxDqsDelay = 036
N0.C3.D0.R0.S17: RxDqsDelay = 033
N2.C0.D1.R1.S01: Total Receive Enable Delay = 1297
N4.C0.D1.R0.S06: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N6.C3.D0.R1.S05: RdDqDqs FSM results: Left = 05, Right = 63, center = 34
N0.C3.D0.R1.S00: RdDqDqs FSM results: Left = 06, Right = 63, center = 34
N2.C0.D1.R1.S02: Total Receive Enable Delay = 1267
N4.C0.D1.R0.S07: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N6.C3.D0.R1.S05: RxDqsDelay = 034
N0.C3.D0.R1.S00: RxDqsDelay = 034
N2.C0.D1.R1.S03: Total Receive Enable Delay = 1245
N4.C0.D1.R0.S08: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N6.C3.D0.R1.S06: RdDqDqs FSM results: Left = 04, Right = 63, center = 33
N0.C3.D0.R1.S01: RdDqDqs FSM results: Left = 05, Right = 63, center = 34
N2.C0.D1.R1.S04: Total Receive Enable Delay = 1238
N4.C0.D1.R0.S00: Preamble found at Latency = 007
N6.C3.D0.R1.S06: RxDqsDelay = 033
N0.C3.D0.R1.S01: RxDqsDelay = 034
N2.C0.D1.R1.S05: Total Receive Enable Delay = 1263
N4.C0.D1.R0.S01: Preamble found at Latency = 007
N6.C3.D0.R1.S07: RdDqDqs FSM results: Left = 05, Right = 63, center = 34
N0.C3.D0.R1.S02: RdDqDqs FSM results: Left = 04, Right = 63, center = 33
N2.C0.D1.R1.S06: Total Receive Enable Delay = 1294
N4.C0.D1.R0.S02: Preamble found at Latency = 007
N6.C3.D0.R1.S07: RxDqsDelay = 034
N0.C3.D0.R1.S02: RxDqsDelay = 033
N2.C0.D1.R1.S07: Total Receive Enable Delay = 1315
N4.C0.D1.R0.S03: Preamble found at Latency = 007
N6.C3.D0.R1.S08: RdDqDqs FSM results: Left = 03, Right = 63, center = 33
N0.C3.D0.R1.S03: RdDqDqs FSM results: Left = 06, Right = 63, center = 34
N2.C0.D1.R1.S08: Total Receive Enable Delay = 1235
N4.C0.D1.R0.S04: Preamble found at Latency = 007
N6.C3.D0.R1.S08: RxDqsDelay = 033
N0.C3.D0.R1.S03: RxDqsDelay = 034
N2.C0.D1.R1: Starting preamble search upper nibbles
N4.C0.D1.R0.S05: Preamble found at Latency = 007
N6.C3.D0.R1.S09: RdDqDqs FSM results: Left = 06, Right = 63, center = 34
N0.C3.D0.R1.S04: RdDqDqs FSM results: Left = 07, Right = 63, center = 35
N2.C0.D1.R1.S09: PI = 002, PtrOffset = 004
N4.C0.D1.R0.S06: Preamble found at Latency = 007
N6.C3.D0.R1.S09: RxDqsDelay = 034
N0.C3.D0.R1.S04: RxDqsDelay = 035
N2.C0.D1.R1.S10: PI = 045, PtrOffset = 005
N4.C0.D1.R0.S07: Preamble found at Latency = 007
N6.C3.D0.R1.S10: RdDqDqs FSM results: Left = 04, Right = 63, center = 33
N0.C3.D0.R1.S05: RdDqDqs FSM results: Left = 05, Right = 63, center = 34
N2.C0.D1.R1.S11: PI = 018, PtrOffset = 005
N4.C0.D1.R0.S08: Preamble found at Latency = 007
N6.C3.D0.R1.S10: RxDqsDelay = 033
N0.C3.D0.R1.S05: RxDqsDelay = 034
N2.C0.D1.R1.S12: PI = 061, PtrOffset = 004
N4.C0.D1.R0.S00: Total Receive Enable Delay = 1308
N6.C3.D0.R1.S11: RdDqDqs FSM results: Left = 03, Right = 63, center = 33
N0.C3.D0.R1.S06: RdDqDqs FSM results: Left = 07, Right = 63, center = 35
N2.C0.D1.R1.S13: PI = 052, PtrOffset = 004
N4.C0.D1.R0.S01: Total Receive Enable Delay = 1287
N6.C3.D0.R1.S11: RxDqsDelay = 033
N0.C3.D0.R1.S06: RxDqsDelay = 035
N2.C0.D1.R1.S14: PI = 012, PtrOffset = 005
N4.C0.D1.R0.S02: Total Receive Enable Delay = 1257
N6.C3.D0.R1.S12: RdDqDqs FSM results: Left = 07, Right = 63, center = 35
N0.C3.D0.R1.S07: RdDqDqs FSM results: Left = 04, Right = 63, center = 33
N2.C0.D1.R1.S15: PI = 045, PtrOffset = 005
N4.C0.D1.R0.S03: Total Receive Enable Delay = 1236
N6.C3.D0.R1.S12: RxDqsDelay = 035
N0.C3.D0.R1.S07: RxDqsDelay = 033
N2.C0.D1.R1.S16: PI = 003, PtrOffset = 004
N4.C0.D1.R0.S04: Total Receive Enable Delay = 1230
N6.C3.D0.R1.S13: RdDqDqs FSM results: Left = 06, Right = 63, center = 34
N0.C3.D0.R1.S08: RdDqDqs FSM results: Left = 02, Right = 63, center = 32
N2.C0.D1.R1.S17: PI = 049, PtrOffset = 004
N4.C0.D1.R0.S05: Total Receive Enable Delay = 1255
N6.C3.D0.R1.S13: RxDqsDelay = 034
N0.C3.D0.R1.S08: RxDqsDelay = 032
N2.C0.D1.R1.S09: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N4.C0.D1.R0.S06: Total Receive Enable Delay = 1289
N6.C3.D0.R1.S14: RdDqDqs FSM results: Left = 02, Right = 57, center = 29
N0.C3.D0.R1.S09: RdDqDqs FSM results: Left = 09, Right = 63, center = 36
N2.C0.D1.R1.S10: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N4.C0.D1.R0.S07: Total Receive Enable Delay = 1309
N6.C3.D0.R1.S14: RxDqsDelay = 029
N0.C3.D0.R1.S09: RxDqsDelay = 036
N2.C0.D1.R1.S11: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N4.C0.D1.R0.S08: Total Receive Enable Delay = 1226
N6.C3.D0.R1.S15: RdDqDqs FSM results: Left = 03, Right = 58, center = 30
N0.C3.D0.R1.S10: RdDqDqs FSM results: Left = 04, Right = 63, center = 33
N2.C0.D1.R1.S12: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N4.C0.D1.R0: Starting preamble search upper nibbles
N6.C3.D0.R1.S15: RxDqsDelay = 030
N0.C3.D0.R1.S10: RxDqsDelay = 033
N2.C0.D1.R1.S13: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N4.C0.D1.R0.S09: PI = 058, PtrOffset = 005
N6.C3.D0.R1.S16: RdDqDqs FSM results: Left = 02, Right = 57, center = 29
N0.C3.D0.R1.S11: RdDqDqs FSM results: Left = 03, Right = 63, center = 33
N2.C0.D1.R1.S14: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N4.C0.D1.R0.S10: PI = 040, PtrOffset = 005
N6.C3.D0.R1.S16: RxDqsDelay = 029
N0.C3.D0.R1.S11: RxDqsDelay = 033
N2.C0.D1.R1.S15: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N4.C0.D1.R0.S11: PI = 011, PtrOffset = 005
N6.C3.D0.R1.S17: RdDqDqs FSM results: Left = 05, Right = 61, center = 33
N0.C3.D0.R1.S12: RdDqDqs FSM results: Left = 05, Right = 63, center = 34
N2.C0.D1.R1.S16: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N4.C0.D1.R0.S12: PI = 051, PtrOffset = 004
N6.C3.D0.R1.S17: RxDqsDelay = 033
N0.C3.D0.R1.S12: RxDqsDelay = 034
N2.C0.D1.R1.S17: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N4.C0.D1.R0.S13: PI = 048, PtrOffset = 004
N6.C3.D1.R0.S00: RdDqDqs FSM results: Left = 05, Right = 63, center = 34
N0.C3.D0.R1.S13: RdDqDqs FSM results: Left = 07, Right = 63, center = 35
N2.C0.D1.R1.S09: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N4.C0.D1.R0.S14: PI = 003, PtrOffset = 005
N6.C3.D1.R0.S00: RxDqsDelay = 034
N0.C3.D0.R1.S13: RxDqsDelay = 035
N2.C0.D1.R1.S10: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N4.C0.D1.R0.S15: PI = 037, PtrOffset = 005
N6.C3.D1.R0.S01: RdDqDqs FSM results: Left = 06, Right = 63, center = 34
N0.C3.D0.R1.S14: RdDqDqs FSM results: Left = 03, Right = 63, center = 33
N2.C0.D1.R1.S11: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N4.C0.D1.R0.S16: PI = 058, PtrOffset = 005
N6.C3.D1.R0.S01: RxDqsDelay = 034
N0.C3.D0.R1.S14: RxDqsDelay = 033
N2.C0.D1.R1.S12: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N4.C0.D1.R0.S17: PI = 040, PtrOffset = 004
N6.C3.D1.R0.S02: RdDqDqs FSM results: Left = 07, Right = 63, center = 35
N0.C3.D0.R1.S15: RdDqDqs FSM results: Left = 06, Right = 63, center = 34
N2.C0.D1.R1.S13: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N4.C0.D1.R0.S09: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N6.C3.D1.R0.S02: RxDqsDelay = 035
N0.C3.D0.R1.S15: RxDqsDelay = 034
N2.C0.D1.R1.S14: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N4.C0.D1.R0.S10: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N6.C3.D1.R0.S03: RdDqDqs FSM results: Left = 06, Right = 63, center = 34
N0.C3.D0.R1.S16: RdDqDqs FSM results: Left = 03, Right = 63, center = 33
N2.C0.D1.R1.S15: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N4.C0.D1.R0.S11: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N6.C3.D1.R0.S03: RxDqsDelay = 034
N0.C3.D0.R1.S16: RxDqsDelay = 033
N2.C0.D1.R1.S16: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N4.C0.D1.R0.S12: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N6.C3.D1.R0.S04: RdDqDqs FSM results: Left = 14, Right = 63, center = 38
N0.C3.D0.R1.S17: RdDqDqs FSM results: Left = 03, Right = 63, center = 33
N2.C0.D1.R1.S17: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N4.C0.D1.R0.S13: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N6.C3.D1.R0.S04: RxDqsDelay = 038
N0.C3.D0.R1.S17: RxDqsDelay = 033
N2.C0.D1.R1.S09: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N4.C0.D1.R0.S14: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N6.C3.D1.R0.S05: RdDqDqs FSM results: Left = 09, Right = 63, center = 36
N0.C3.D1.R0.S00: RdDqDqs FSM results: Left = 10, Right = 63, center = 36
N2.C0.D1.R1.S10: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N4.C0.D1.R0.S15: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N6.C3.D1.R0.S05: RxDqsDelay = 036
N0.C3.D1.R0.S00: RxDqsDelay = 036
N2.C0.D1.R1.S11: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N4.C0.D1.R0.S16: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N6.C3.D1.R0.S06: RdDqDqs FSM results: Left = 09, Right = 63, center = 36
N0.C3.D1.R0.S01: RdDqDqs FSM results: Left = 09, Right = 63, center = 36
N2.C0.D1.R1.S12: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N4.C0.D1.R0.S17: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N6.C3.D1.R0.S06: RxDqsDelay = 036
N0.C3.D1.R0.S01: RxDqsDelay = 036
N2.C0.D1.R1.S13: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N4.C0.D1.R0.S09: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N6.C3.D1.R0.S07: RdDqDqs FSM results: Left = 09, Right = 63, center = 36
N0.C3.D1.R0.S02: RdDqDqs FSM results: Left = 09, Right = 63, center = 36
N2.C0.D1.R1.S14: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N4.C0.D1.R0.S10: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N6.C3.D1.R0.S07: RxDqsDelay = 036
N0.C3.D1.R0.S02: RxDqsDelay = 036
N2.C0.D1.R1.S15: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N4.C0.D1.R0.S11: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N6.C3.D1.R0.S08: RdDqDqs FSM results: Left = 07, Right = 63, center = 35
N0.C3.D1.R0.S03: RdDqDqs FSM results: Left = 09, Right = 63, center = 36
N2.C0.D1.R1.S16: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N4.C0.D1.R0.S12: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N6.C3.D1.R0.S08: RxDqsDelay = 035
N0.C3.D1.R0.S03: RxDqsDelay = 036
N2.C0.D1.R1.S17: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N4.C0.D1.R0.S13: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N6.C3.D1.R0.S09: RdDqDqs FSM results: Left = 10, Right = 63, center = 36
N0.C3.D1.R0.S04: RdDqDqs FSM results: Left = 10, Right = 63, center = 36
N2.C0.D1.R1.S09: Preamble found at Latency = 008
N4.C0.D1.R0.S14: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N6.C3.D1.R0.S09: RxDqsDelay = 036
N0.C3.D1.R0.S04: RxDqsDelay = 036
N2.C0.D1.R1.S16: Preamble found at Latency = 008
N4.C0.D1.R0.S15: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N6.C3.D1.R0.S10: RdDqDqs FSM results: Left = 07, Right = 63, center = 35
N0.C3.D1.R0.S05: RdDqDqs FSM results: Left = 09, Right = 63, center = 36
N2.C0.D1.R1.S09: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N4.C0.D1.R0.S16: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N6.C3.D1.R0.S10: RxDqsDelay = 035
N0.C3.D1.R0.S05: RxDqsDelay = 036
N2.C0.D1.R1.S10: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N4.C0.D1.R0.S17: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N6.C3.D1.R0.S11: RdDqDqs FSM results: Left = 06, Right = 63, center = 34
N0.C3.D1.R0.S06: RdDqDqs FSM results: Left = 10, Right = 63, center = 36
N2.C0.D1.R1.S11: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N4.C0.D1.R0.S09: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N6.C3.D1.R0.S11: RxDqsDelay = 034
N0.C3.D1.R0.S06: RxDqsDelay = 036
N2.C0.D1.R1.S12: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N4.C0.D1.R0.S10: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N6.C3.D1.R0.S12: RdDqDqs FSM results: Left = 09, Right = 63, center = 36
N0.C3.D1.R0.S07: RdDqDqs FSM results: Left = 07, Right = 63, center = 35
N2.C0.D1.R1.S13: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N4.C0.D1.R0.S11: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N6.C3.D1.R0.S12: RxDqsDelay = 036
N0.C3.D1.R0.S07: RxDqsDelay = 035
N2.C0.D1.R1.S14: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N4.C0.D1.R0.S12: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N6.C3.D1.R0.S13: RdDqDqs FSM results: Left = 09, Right = 63, center = 36
N0.C3.D1.R0.S08: RdDqDqs FSM results: Left = 05, Right = 63, center = 34
N2.C0.D1.R1.S15: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N4.C0.D1.R0.S13: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N6.C3.D1.R0.S13: RxDqsDelay = 036
N0.C3.D1.R0.S08: RxDqsDelay = 034
N2.C0.D1.R1.S16: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N4.C0.D1.R0.S14: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N6.C3.D1.R0.S14: RdDqDqs FSM results: Left = 03, Right = 60, center = 31
N0.C3.D1.R0.S09: RdDqDqs FSM results: Left = 14, Right = 63, center = 38
N2.C0.D1.R1.S17: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N4.C0.D1.R0.S15: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N6.C3.D1.R0.S14: RxDqsDelay = 031
N0.C3.D1.R0.S09: RxDqsDelay = 038
N2.C0.D1.R1.S10: Preamble found at Latency = 007
N4.C0.D1.R0.S16: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N6.C3.D1.R0.S15: RdDqDqs FSM results: Left = 05, Right = 63, center = 34
N0.C3.D1.R0.S10: RdDqDqs FSM results: Left = 09, Right = 63, center = 36
N2.C0.D1.R1.S11: Preamble found at Latency = 007
N4.C0.D1.R0.S17: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N6.C3.D1.R0.S15: RxDqsDelay = 034
N0.C3.D1.R0.S10: RxDqsDelay = 036
N2.C0.D1.R1.S12: Preamble found at Latency = 007
N4.C0.D1.R0.S09: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N6.C3.D1.R0.S16: RdDqDqs FSM results: Left = 05, Right = 63, center = 34
N0.C3.D1.R0.S11: RdDqDqs FSM results: Left = 04, Right = 63, center = 33
N2.C0.D1.R1.S13: Preamble found at Latency = 007
N4.C0.D1.R0.S10: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N6.C3.D1.R0.S16: RxDqsDelay = 034
N0.C3.D1.R0.S11: RxDqsDelay = 033
N2.C0.D1.R1.S14: Preamble found at Latency = 007
N4.C0.D1.R0.S11: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N6.C3.D1.R0.S17: RdDqDqs FSM results: Left = 09, Right = 63, center = 36
N0.C3.D1.R0.S12: RdDqDqs FSM results: Left = 07, Right = 63, center = 35
N2.C0.D1.R1.S15: Preamble found at Latency = 007
N4.C0.D1.R0.S12: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N6.C3.D1.R0.S17: RxDqsDelay = 036
N0.C3.D1.R0.S12: RxDqsDelay = 035
N2.C0.D1.R1.S17: Preamble found at Latency = 007
N4.C0.D1.R0.S13: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N6.C3.D1.R1.S00: RdDqDqs FSM results: Left = 05, Right = 60, center = 32
N0.C3.D1.R0.S13: RdDqDqs FSM results: Left = 10, Right = 63, center = 36
N2.C0.D1.R1: Preamble found for all upper nibbles, adjusting Pi, Offset to center into preamble
N4.C0.D1.R0.S14: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N6.C3.D1.R1.S00: RxDqsDelay = 032
N0.C3.D1.R0.S13: RxDqsDelay = 036
N2.C0.D1.R1.S09: Total Receive Enable Delay = 1314
N4.C0.D1.R0.S15: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N6.C3.D1.R1.S01: RdDqDqs FSM results: Left = 07, Right = 63, center = 35
N0.C3.D1.R0.S14: RdDqDqs FSM results: Left = 05, Right = 63, center = 34
N2.C0.D1.R1.S10: Total Receive Enable Delay = 1293
N4.C0.D1.R0.S16: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N6.C3.D1.R1.S01: RxDqsDelay = 035
N0.C3.D1.R0.S14: RxDqsDelay = 034
N2.C0.D1.R1.S11: Total Receive Enable Delay = 1266
N4.C0.D1.R0.S17: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N6.C3.D1.R1.S02: RdDqDqs FSM results: Left = 06, Right = 63, center = 34
N0.C3.D1.R0.S15: RdDqDqs FSM results: Left = 07, Right = 63, center = 35
N2.C0.D1.R1.S12: Total Receive Enable Delay = 1245
N4.C0.D1.R0.S09: Preamble found at Latency = 007
N6.C3.D1.R1.S02: RxDqsDelay = 034
N0.C3.D1.R0.S15: RxDqsDelay = 035
N2.C0.D1.R1.S13: Total Receive Enable Delay = 1236
N4.C0.D1.R0.S10: Preamble found at Latency = 007
N6.C3.D1.R1.S03: RdDqDqs FSM results: Left = 06, Right = 63, center = 34
N0.C3.D1.R0.S16: RdDqDqs FSM results: Left = 08, Right = 63, center = 35
N2.C0.D1.R1.S14: Total Receive Enable Delay = 1260
N4.C0.D1.R0.S11: Preamble found at Latency = 007
N6.C3.D1.R1.S03: RxDqsDelay = 034
N0.C3.D1.R0.S16: RxDqsDelay = 035
N2.C0.D1.R1.S15: Total Receive Enable Delay = 1293
N4.C0.D1.R0.S12: Preamble found at Latency = 007
N6.C3.D1.R1.S04: RdDqDqs FSM results: Left = 13, Right = 63, center = 38
N0.C3.D1.R0.S17: RdDqDqs FSM results: Left = 07, Right = 63, center = 35
N2.C0.D1.R1.S16: Total Receive Enable Delay = 1315
N4.C0.D1.R0.S13: Preamble found at Latency = 007
N6.C3.D1.R1.S04: RxDqsDelay = 038
N0.C3.D1.R0.S17: RxDqsDelay = 035
N2.C0.D1.R1.S17: Total Receive Enable Delay = 1233
N4.C0.D1.R0.S14: Preamble found at Latency = 007
N6.C3.D1.R1.S05: RdDqDqs FSM results: Left = 08, Right = 63, center = 35
N0.C3.D1.R1.S00: RdDqDqs FSM results: Left = 10, Right = 63, center = 36
START_DATA_REC_EN
N4.C0.D1.R0.S15: Preamble found at Latency = 007
N6.C3.D1.R1.S05: RxDqsDelay = 035
N0.C3.D1.R1.S00: RxDqsDelay = 036
N2.C0.S00: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N4.C0.D1.R0.S16: Preamble found at Latency = 007
N6.C3.D1.R1.S06: RdDqDqs FSM results: Left = 10, Right = 63, center = 36
N0.C3.D1.R1.S01: RdDqDqs FSM results: Left = 09, Right = 63, center = 36
N2.C0.S01: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N4.C0.D1.R0.S17: Preamble found at Latency = 007
N6.C3.D1.R1.S06: RxDqsDelay = 036
N0.C3.D1.R1.S01: RxDqsDelay = 036
N2.C0.S02: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 5
N4.C0.D1.R0: Preamble found for all upper nibbles, adjusting Pi, Offset to center into preamble
N6.C3.D1.R1.S07: RdDqDqs FSM results: Left = 09, Right = 63, center = 36
N0.C3.D1.R1.S02: RdDqDqs FSM results: Left = 08, Right = 63, center = 35
N2.C0.S03: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 5
N4.C0.D1.R0.S09: Total Receive Enable Delay = 1306
N6.C3.D1.R1.S07: RxDqsDelay = 036
N0.C3.D1.R1.S02: RxDqsDelay = 035
N2.C0.S04: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 5
N4.C0.D1.R0.S10: Total Receive Enable Delay = 1288
N6.C3.D1.R1.S08: RdDqDqs FSM results: Left = 07, Right = 63, center = 35
N0.C3.D1.R1.S03: RdDqDqs FSM results: Left = 09, Right = 63, center = 36
N2.C0.S05: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 5
N4.C0.D1.R0.S11: Total Receive Enable Delay = 1259
N6.C3.D1.R1.S08: RxDqsDelay = 035
N0.C3.D1.R1.S03: RxDqsDelay = 036
N2.C0.S06: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N4.C0.D1.R0.S12: Total Receive Enable Delay = 1235
N6.C3.D1.R1.S09: RdDqDqs FSM results: Left = 10, Right = 63, center = 36
N0.C3.D1.R1.S04: RdDqDqs FSM results: Left = 10, Right = 63, center = 36
N2.C0.S07: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N4.C0.D1.R0.S13: Total Receive Enable Delay = 1232
N6.C3.D1.R1.S09: RxDqsDelay = 036
N0.C3.D1.R1.S04: RxDqsDelay = 036
N2.C0.S08: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 5
N4.C0.D1.R0.S14: Total Receive Enable Delay = 1251
N6.C3.D1.R1.S10: RdDqDqs FSM results: Left = 07, Right = 63, center = 35
N0.C3.D1.R1.S05: RdDqDqs FSM results: Left = 10, Right = 63, center = 36
N2.C0.S09: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N4.C0.D1.R0.S15: Total Receive Enable Delay = 1285
N6.C3.D1.R1.S10: RxDqsDelay = 035
N0.C3.D1.R1.S05: RxDqsDelay = 036
N2.C0.S10: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N4.C0.D1.R0.S16: Total Receive Enable Delay = 1306
N6.C3.D1.R1.S11: RdDqDqs FSM results: Left = 07, Right = 63, center = 35
N0.C3.D1.R1.S06: RdDqDqs FSM results: Left = 10, Right = 63, center = 36
N2.C0.S11: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 5
N4.C0.D1.R0.S17: Total Receive Enable Delay = 1224
N6.C3.D1.R1.S11: RxDqsDelay = 035
N0.C3.D1.R1.S06: RxDqsDelay = 036
N2.C0.S12: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 5
N4.C0.D1.R1: RcvEnFine: Initial RdCmd2RcvEnLatency = 10, Initial RdPtrOffsetRcvEn = 4
N6.C3.D1.R1.S12: RdDqDqs FSM results: Left = 09, Right = 63, center = 36
N0.C3.D1.R1.S07: RdDqDqs FSM results: Left = 07, Right = 63, center = 35
N2.C0.S13: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 5
N4.C0.D1.R1.S00: Rcv En Fine Value = 380
N6.C3.D1.R1.S12: RxDqsDelay = 036
N0.C3.D1.R1.S07: RxDqsDelay = 035
N2.C0.S14: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 5
N4.C0.D1.R1.S01: Rcv En Fine Value = 360
N6.C3.D1.R1.S13: RdDqDqs FSM results: Left = 10, Right = 63, center = 36
N0.C3.D1.R1.S08: RdDqDqs FSM results: Left = 04, Right = 63, center = 33
N2.C0.S15: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N4.C0.D1.R1.S02: Rcv En Fine Value = 329
N6.C3.D1.R1.S13: RxDqsDelay = 036
N0.C3.D1.R1.S08: RxDqsDelay = 033
N2.C0.S16: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N4.C0.D1.R1.S03: Rcv En Fine Value = 308
N6.C3.D1.R1.S14: RdDqDqs FSM results: Left = 03, Right = 58, center = 30
N0.C3.D1.R1.S09: RdDqDqs FSM results: Left = 13, Right = 63, center = 38
N2.C0.S17: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 5
N4.C0.D1.R1.S04: Rcv En Fine Value = 303
N6.C3.D1.R1.S14: RxDqsDelay = 030
N0.C3.D1.R1.S09: RxDqsDelay = 038
N2.C0.D0.R0.S00: RcvEn: plus1 = 1, minus1 = 0, PI = 46, DB = 0
N4.C0.D1.R1.S05: Rcv En Fine Value = 327
N6.C3.D1.R1.S15: RdDqDqs FSM results: Left = 06, Right = 63, center = 34
N0.C3.D1.R1.S10: RdDqDqs FSM results: Left = 09, Right = 63, center = 36
N2.C0.D0.R0.S01: RcvEn: plus1 = 1, minus1 = 0, PI = 28, DB = 0
N4.C0.D1.R1.S06: Rcv En Fine Value = 358
N6.C3.D1.R1.S15: RxDqsDelay = 034
N0.C3.D1.R1.S10: RxDqsDelay = 036
N2.C0.D0.R0.S02: RcvEn: plus1 = 0, minus1 = 1, PI = 00, DB = 1
N4.C0.D1.R1.S07: Rcv En Fine Value = 380
N6.C3.D1.R1.S16: RdDqDqs FSM results: Left = 05, Right = 60, center = 32
N0.C3.D1.R1.S11: RdDqDqs FSM results: Left = 05, Right = 63, center = 34
N2.C0.D0.R0.S03: RcvEn: plus1 = 1, minus1 = 0, PI = 41, DB = 0
N4.C0.D1.R1.S08: Rcv En Fine Value = 297
N6.C3.D1.R1.S16: RxDqsDelay = 032
N0.C3.D1.R1.S11: RxDqsDelay = 034
N2.C0.D0.R0.S04: RcvEn: plus1 = 1, minus1 = 0, PI = 33, DB = 0
N4.C0.D1.R1.S09: Rcv En Fine Value = 377
N6.C3.D1.R1.S17: RdDqDqs FSM results: Left = 09, Right = 63, center = 36
N0.C3.D1.R1.S12: RdDqDqs FSM results: Left = 07, Right = 63, center = 35
N2.C0.D0.R0.S05: RcvEn: plus1 = 1, minus1 = 0, PI = 59, DB = 1
N4.C0.D1.R1.S10: Rcv En Fine Value = 359
N6.C3.D1.R1.S17: RxDqsDelay = 036
N0.C3.D1.R1.S12: RxDqsDelay = 035
N2.C0.D0.R0.S06: RcvEn: plus1 = 1, minus1 = 0, PI = 25, DB = 0
N4.C0.D1.R1.S11: Rcv En Fine Value = 329
START_DATA_RX_DQS
N0.C3.D1.R1.S13: RdDqDqs FSM results: Left = 10, Right = 63, center = 36
N2.C0.D0.R0.S07: RcvEn: plus1 = 1, minus1 = 0, PI = 48, DB = 0
N4.C0.D1.R1.S12: Rcv En Fine Value = 308
N6.C3.R0.S00: PI = 31
N0.C3.D1.R1.S13: RxDqsDelay = 036
N2.C0.D0.R0.S08: RcvEn: plus1 = 1, minus1 = 0, PI = 30, DB = 0
N4.C0.D1.R1.S13: Rcv En Fine Value = 301
N6.C3.R0.S01: PI = 33
N0.C3.D1.R1.S14: RdDqDqs FSM results: Left = 06, Right = 63, center = 34
N2.C0.D0.R0.S09: RcvEn: plus1 = 1, minus1 = 0, PI = 45, DB = 0
N4.C0.D1.R1.S14: Rcv En Fine Value = 325
N6.C3.R0.S02: PI = 33
N0.C3.D1.R1.S14: RxDqsDelay = 034
N2.C0.D0.R0.S10: RcvEn: plus1 = 1, minus1 = 0, PI = 28, DB = 0
N4.C0.D1.R1.S15: Rcv En Fine Value = 357
N6.C3.R0.S03: PI = 33
N0.C3.D1.R1.S15: RdDqDqs FSM results: Left = 07, Right = 63, center = 35
N2.C0.D0.R0.S11: RcvEn: plus1 = 0, minus1 = 1, PI = 00, DB = 1
N4.C0.D1.R1.S16: Rcv En Fine Value = 376
N6.C3.R0.S04: PI = 36
N0.C3.D1.R1.S15: RxDqsDelay = 035
N2.C0.D0.R0.S12: RcvEn: plus1 = 1, minus1 = 0, PI = 43, DB = 0
N4.C0.D1.R1.S17: Rcv En Fine Value = 295
N6.C3.R0.S05: PI = 34
N0.C3.D1.R1.S16: RdDqDqs FSM results: Left = 06, Right = 63, center = 34
N2.C0.D0.R0.S13: RcvEn: plus1 = 1, minus1 = 0, PI = 31, DB = 0
N4.C0.D1.R1: Starting preamble search lower nibbles
N6.C3.R0.S06: PI = 33
N0.C3.D1.R1.S16: RxDqsDelay = 034
N2.C0.D0.R0.S14: RcvEn: plus1 = 1, minus1 = 0, PI = 57, DB = 1
N4.C0.D1.R1.S00: PI = 060, PtrOffset = 005
N6.C3.R0.S07: PI = 34
N0.C3.D1.R1.S17: RdDqDqs FSM results: Left = 07, Right = 63, center = 35
N2.C0.D0.R0.S15: RcvEn: plus1 = 1, minus1 = 0, PI = 25, DB = 0
N4.C0.D1.R1.S01: PI = 040, PtrOffset = 005
N6.C3.R0.S08: PI = 33
N0.C3.D1.R1.S17: RxDqsDelay = 035
N2.C0.D0.R0.S16: RcvEn: plus1 = 1, minus1 = 0, PI = 47, DB = 0
N4.C0.D1.R1.S02: PI = 009, PtrOffset = 005
N6.C3.R0.S09: PI = 34
START_DATA_RX_DQS
N2.C0.D0.R0.S17: RcvEn: plus1 = 1, minus1 = 0, PI = 28, DB = 0
N4.C0.D1.R1.S03: PI = 052, PtrOffset = 004
N6.C3.R0.S10: PI = 32
N0.C3.R0.S00: PI = 34
N2.C0.D0.R1.S00: RcvEn: plus1 = 1, minus1 = 0, PI = 46, DB = 0
N4.C0.D1.R1.S04: PI = 047, PtrOffset = 004
N6.C3.R0.S11: PI = 33
N0.C3.R0.S01: PI = 34
N2.C0.D0.R1.S01: RcvEn: plus1 = 1, minus1 = 0, PI = 28, DB = 0
N4.C0.D1.R1.S05: PI = 007, PtrOffset = 005
N6.C3.R0.S12: PI = 34
N0.C3.R0.S02: PI = 33
N2.C0.D0.R1.S02: RcvEn: plus1 = 0, minus1 = 1, PI = 00, DB = 1
N4.C0.D1.R1.S06: PI = 038, PtrOffset = 005
N6.C3.R0.S13: PI = 34
N0.C3.R0.S03: PI = 34
N2.C0.D0.R1.S03: RcvEn: plus1 = 1, minus1 = 0, PI = 41, DB = 0
N4.C0.D1.R1.S07: PI = 060, PtrOffset = 005
N6.C3.R0.S14: PI = 29
N0.C3.R0.S04: PI = 35
N2.C0.D0.R1.S04: RcvEn: plus1 = 1, minus1 = 0, PI = 33, DB = 0
N4.C0.D1.R1.S08: PI = 041, PtrOffset = 004
N6.C3.R0.S15: PI = 30
N0.C3.R0.S05: PI = 34
N2.C0.D0.R1.S05: RcvEn: plus1 = 1, minus1 = 0, PI = 59, DB = 1
N4.C0.D1.R1.S00: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N6.C3.R0.S16: PI = 31
N0.C3.R0.S06: PI = 35
N2.C0.D0.R1.S06: RcvEn: plus1 = 1, minus1 = 0, PI = 25, DB = 0
N4.C0.D1.R1.S01: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N6.C3.R0.S17: PI = 33
N0.C3.R0.S07: PI = 33
N2.C0.D0.R1.S07: RcvEn: plus1 = 1, minus1 = 0, PI = 48, DB = 0
N4.C0.D1.R1.S02: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N6.C3.R0.S00: PI = 31
N0.C3.R0.S08: PI = 32
N2.C0.D0.R1.S08: RcvEn: plus1 = 1, minus1 = 0, PI = 30, DB = 0
N4.C0.D1.R1.S03: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N6.C3.R0.S01: PI = 33
N0.C3.R0.S09: PI = 36
N2.C0.D0.R1.S09: RcvEn: plus1 = 1, minus1 = 0, PI = 45, DB = 0
N4.C0.D1.R1.S04: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N6.C3.R0.S02: PI = 33
N0.C3.R0.S10: PI = 33
N2.C0.D0.R1.S10: RcvEn: plus1 = 1, minus1 = 0, PI = 28, DB = 0
N4.C0.D1.R1.S05: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N6.C3.R0.S03: PI = 33
N0.C3.R0.S11: PI = 32
N2.C0.D0.R1.S11: RcvEn: plus1 = 0, minus1 = 1, PI = 00, DB = 1
N4.C0.D1.R1.S06: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N6.C3.R0.S04: PI = 36
N0.C3.R0.S12: PI = 34
N2.C0.D0.R1.S12: RcvEn: plus1 = 1, minus1 = 0, PI = 43, DB = 0
N4.C0.D1.R1.S07: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N6.C3.R0.S05: PI = 34
N0.C3.R0.S13: PI = 35
N2.C0.D0.R1.S13: RcvEn: plus1 = 1, minus1 = 0, PI = 31, DB = 0
N4.C0.D1.R1.S08: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N6.C3.R0.S06: PI = 33
N0.C3.R0.S14: PI = 33
N2.C0.D0.R1.S14: RcvEn: plus1 = 1, minus1 = 0, PI = 57, DB = 1
N4.C0.D1.R1.S00: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N6.C3.R0.S07: PI = 34
N0.C3.R0.S15: PI = 34
N2.C0.D0.R1.S15: RcvEn: plus1 = 1, minus1 = 0, PI = 25, DB = 0
N4.C0.D1.R1.S01: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N6.C3.R0.S08: PI = 33
N0.C3.R0.S16: PI = 33
N2.C0.D0.R1.S16: RcvEn: plus1 = 1, minus1 = 0, PI = 47, DB = 0
N4.C0.D1.R1.S02: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N6.C3.R0.S09: PI = 34
N0.C3.R0.S17: PI = 33
N2.C0.D0.R1.S17: RcvEn: plus1 = 1, minus1 = 0, PI = 28, DB = 0
N4.C0.D1.R1.S03: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N6.C3.R0.S10: PI = 32
N0.C3.R0.S00: PI = 34
N2.C0.D1.R0.S00: RcvEn: plus1 = 1, minus1 = 0, PI = 33, DB = 0
N4.C0.D1.R1.S04: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N6.C3.R0.S11: PI = 33
N0.C3.R0.S01: PI = 34
N2.C0.D1.R0.S01: RcvEn: plus1 = 1, minus1 = 0, PI = 17, DB = 0
N4.C0.D1.R1.S05: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N6.C3.R0.S12: PI = 34
N0.C3.R0.S02: PI = 33
N2.C0.D1.R0.S02: RcvEn: plus1 = 1, minus1 = 0, PI = 51, DB = 1
N4.C0.D1.R1.S06: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N6.C3.R0.S13: PI = 34
N0.C3.R0.S03: PI = 34
N2.C0.D1.R0.S03: RcvEn: plus1 = 1, minus1 = 0, PI = 29, DB = 0
N4.C0.D1.R1.S07: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N6.C3.R0.S14: PI = 29
N0.C3.R0.S04: PI = 35
N2.C0.D1.R0.S04: RcvEn: plus1 = 1, minus1 = 0, PI = 22, DB = 0
N4.C0.D1.R1.S08: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N6.C3.R0.S15: PI = 30
N0.C3.R0.S05: PI = 34
N2.C0.D1.R0.S05: RcvEn: plus1 = 1, minus1 = 0, PI = 47, DB = 0
N4.C0.D1.R1.S00: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N6.C3.R0.S16: PI = 31
N0.C3.R0.S06: PI = 35
N2.C0.D1.R0.S06: RcvEn: plus1 = 1, minus1 = 0, PI = 13, DB = 1
N4.C0.D1.R1.S01: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N6.C3.R0.S17: PI = 33
N0.C3.R0.S07: PI = 33
N2.C0.D1.R0.S07: RcvEn: plus1 = 1, minus1 = 0, PI = 36, DB = 0
N4.C0.D1.R1.S02: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N6.C3.R2.S00: PI = 33
N0.C3.R0.S08: PI = 32
N2.C0.D1.R0.S08: RcvEn: plus1 = 1, minus1 = 0, PI = 20, DB = 0
N4.C0.D1.R1.S03: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N6.C3.R2.S01: PI = 34
N0.C3.R0.S09: PI = 36
N2.C0.D1.R0.S09: RcvEn: plus1 = 1, minus1 = 0, PI = 34, DB = 0
N4.C0.D1.R1.S04: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N6.C3.R2.S02: PI = 34
N0.C3.R0.S10: PI = 33
N2.C0.D1.R0.S10: RcvEn: plus1 = 1, minus1 = 0, PI = 15, DB = 1
N4.C0.D1.R1.S05: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N6.C3.R2.S03: PI = 34
N0.C3.R0.S11: PI = 32
N2.C0.D1.R0.S11: RcvEn: plus1 = 1, minus1 = 0, PI = 50, DB = 1
N4.C0.D1.R1.S06: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N6.C3.R2.S04: PI = 38
N0.C3.R0.S12: PI = 34
N2.C0.D1.R0.S12: RcvEn: plus1 = 1, minus1 = 0, PI = 29, DB = 0
N4.C0.D1.R1.S07: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N6.C3.R2.S05: PI = 35
N0.C3.R0.S13: PI = 35
N2.C0.D1.R0.S13: RcvEn: plus1 = 1, minus1 = 0, PI = 20, DB = 0
N4.C0.D1.R1.S08: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N6.C3.R2.S06: PI = 36
N0.C3.R0.S14: PI = 33
N2.C0.D1.R0.S14: RcvEn: plus1 = 1, minus1 = 0, PI = 46, DB = 0
N4.C0.D1.R1.S00: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N6.C3.R2.S07: PI = 36
N0.C3.R0.S15: PI = 34
N2.C0.D1.R0.S15: RcvEn: plus1 = 1, minus1 = 0, PI = 11, DB = 1
N4.C0.D1.R1.S01: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N6.C3.R2.S08: PI = 35
N0.C3.R0.S16: PI = 33
N2.C0.D1.R0.S16: RcvEn: plus1 = 1, minus1 = 0, PI = 34, DB = 0
N4.C0.D1.R1.S02: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N6.C3.R2.S09: PI = 36
N0.C3.R0.S17: PI = 33
N2.C0.D1.R0.S17: RcvEn: plus1 = 1, minus1 = 0, PI = 16, DB = 0
N4.C0.D1.R1.S03: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N6.C3.R2.S10: PI = 35
N0.C3.R2.S00: PI = 36
N2.C0.D1.R1.S00: RcvEn: plus1 = 1, minus1 = 0, PI = 33, DB = 0
N4.C0.D1.R1.S04: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N6.C3.R2.S11: PI = 34
N0.C3.R2.S01: PI = 36
N2.C0.D1.R1.S01: RcvEn: plus1 = 1, minus1 = 0, PI = 17, DB = 0
N4.C0.D1.R1.S05: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N6.C3.R2.S12: PI = 36
N0.C3.R2.S02: PI = 35
N2.C0.D1.R1.S02: RcvEn: plus1 = 1, minus1 = 0, PI = 51, DB = 1
N4.C0.D1.R1.S06: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N6.C3.R2.S13: PI = 36
N0.C3.R2.S03: PI = 36
N2.C0.D1.R1.S03: RcvEn: plus1 = 1, minus1 = 0, PI = 29, DB = 0
N4.C0.D1.R1.S07: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N6.C3.R2.S14: PI = 30
N0.C3.R2.S04: PI = 36
N2.C0.D1.R1.S04: RcvEn: plus1 = 1, minus1 = 0, PI = 22, DB = 0
N4.C0.D1.R1.S08: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N6.C3.R2.S15: PI = 34
N0.C3.R2.S05: PI = 36
N2.C0.D1.R1.S05: RcvEn: plus1 = 1, minus1 = 0, PI = 47, DB = 0
N4.C0.D1.R1.S00: Preamble found at Latency = 007
N6.C3.R2.S16: PI = 33
N0.C3.R2.S06: PI = 36
N2.C0.D1.R1.S06: RcvEn: plus1 = 1, minus1 = 0, PI = 13, DB = 1
N4.C0.D1.R1.S01: Preamble found at Latency = 007
N6.C3.R2.S17: PI = 36
N0.C3.R2.S07: PI = 35
N2.C0.D1.R1.S07: RcvEn: plus1 = 1, minus1 = 0, PI = 36, DB = 0
N4.C0.D1.R1.S02: Preamble found at Latency = 007
N6.C3.R2.S00: PI = 33
N0.C3.R2.S08: PI = 33
N2.C0.D1.R1.S08: RcvEn: plus1 = 1, minus1 = 0, PI = 20, DB = 0
N4.C0.D1.R1.S03: Preamble found at Latency = 007
N6.C3.R2.S01: PI = 34
N0.C3.R2.S09: PI = 38
N2.C0.D1.R1.S09: RcvEn: plus1 = 1, minus1 = 0, PI = 34, DB = 0
N4.C0.D1.R1.S04: Preamble found at Latency = 007
N6.C3.R2.S02: PI = 34
N0.C3.R2.S10: PI = 36
N2.C0.D1.R1.S10: RcvEn: plus1 = 1, minus1 = 0, PI = 15, DB = 1
N4.C0.D1.R1.S05: Preamble found at Latency = 007
N6.C3.R2.S03: PI = 34
N0.C3.R2.S11: PI = 33
N2.C0.D1.R1.S11: RcvEn: plus1 = 1, minus1 = 0, PI = 50, DB = 1
N4.C0.D1.R1.S06: Preamble found at Latency = 007
N6.C3.R2.S04: PI = 38
N0.C3.R2.S12: PI = 35
N2.C0.D1.R1.S12: RcvEn: plus1 = 1, minus1 = 0, PI = 29, DB = 0
N4.C0.D1.R1.S07: Preamble found at Latency = 007
N6.C3.R2.S05: PI = 35
N0.C3.R2.S13: PI = 36
N2.C0.D1.R1.S13: RcvEn: plus1 = 1, minus1 = 0, PI = 20, DB = 0
N4.C0.D1.R1.S08: Preamble found at Latency = 007
N6.C3.R2.S06: PI = 36
N0.C3.R2.S14: PI = 34
N2.C0.D1.R1.S14: RcvEn: plus1 = 1, minus1 = 0, PI = 46, DB = 0
N4.C0.D1.R1.S00: Total Receive Enable Delay = 1308
N6.C3.R2.S07: PI = 36
N0.C3.R2.S15: PI = 35
N2.C0.D1.R1.S15: RcvEn: plus1 = 1, minus1 = 0, PI = 11, DB = 1
N4.C0.D1.R1.S01: Total Receive Enable Delay = 1288
N6.C3.R2.S08: PI = 35
N0.C3.R2.S16: PI = 34
N2.C0.D1.R1.S16: RcvEn: plus1 = 1, minus1 = 0, PI = 34, DB = 0
N4.C0.D1.R1.S02: Total Receive Enable Delay = 1257
N6.C3.R2.S09: PI = 36
N0.C3.R2.S17: PI = 35
N2.C0.D1.R1.S17: RcvEn: plus1 = 1, minus1 = 0, PI = 16, DB = 0
N4.C0.D1.R1.S03: Total Receive Enable Delay = 1236
N6.C3.R2.S10: PI = 35
N0.C3.R2.S00: PI = 36
STOP_DATA_REC_EN
N4.C0.D1.R1.S04: Total Receive Enable Delay = 1231
N6.C3.R2.S11: PI = 34
N0.C3.R2.S01: PI = 36
N2.C1.D0.R0: RcvEnFine: Initial RdCmd2RcvEnLatency = 10, Initial RdPtrOffsetRcvEn = 4
N4.C0.D1.R1.S05: Total Receive Enable Delay = 1255
N6.C3.R2.S12: PI = 36
N0.C3.R2.S02: PI = 35
N2.C1.D0.R0.S00: Rcv En Fine Value = 320
N4.C0.D1.R1.S06: Total Receive Enable Delay = 1286
N6.C3.R2.S13: PI = 36
N0.C3.R2.S03: PI = 36
N2.C1.D0.R0.S01: Rcv En Fine Value = 302
N4.C0.D1.R1.S07: Total Receive Enable Delay = 1308
N6.C3.R2.S14: PI = 30
N0.C3.R2.S04: PI = 36
N2.C1.D0.R0.S02: Rcv En Fine Value = 272
N4.C0.D1.R1.S08: Total Receive Enable Delay = 1225
N6.C3.R2.S15: PI = 34
N0.C3.R2.S05: PI = 36
N2.C1.D0.R0.S03: Rcv En Fine Value = 380
N4.C0.D1.R1: Starting preamble search upper nibbles
N6.C3.R2.S16: PI = 33
N0.C3.R2.S06: PI = 36
N2.C1.D0.R0.S04: Rcv En Fine Value = 372
N4.C0.D1.R1.S09: PI = 057, PtrOffset = 005
N6.C3.R2.S17: PI = 36
N0.C3.R2.S07: PI = 35
N2.C1.D0.R0.S05: Rcv En Fine Value = 269
N4.C0.D1.R1.S10: PI = 039, PtrOffset = 005
STOP_DATA_RX_DQS
N0.C3.R2.S08: PI = 33
N2.C1.D0.R0.S06: Rcv En Fine Value = 294
N4.C0.D1.R1.S11: PI = 009, PtrOffset = 005
N6: RunTrainStep: Final status = 0
N0.C3.R2.S09: PI = 38
N2.C1.D0.R0.S07: Rcv En Fine Value = 315
N4.C0.D1.R1.S12: PI = 052, PtrOffset = 004

END - Basic Read DQ/DQS Training       Time         17753 ms
N0.C3.R2.S10: PI = 36
N2.C1.D0.R0.S08: Rcv En Fine Value = 359
N4.C0.D1.R1.S13: PI = 045, PtrOffset = 004

START - Basic Receive Enable Training
N0.C3.R2.S11: PI = 33
N2.C1.D0.R0.S09: Rcv En Fine Value = 321
N4.C0.D1.R1.S14: PI = 005, PtrOffset = 005
N6.C0: QCRM debug: extraRcvEnLatency = 0
N0.C3.R2.S12: PI = 35
N2.C1.D0.R0.S10: Rcv En Fine Value = 301
N4.C0.D1.R1.S15: PI = 037, PtrOffset = 005
N6.C0: SettingForTrainingStep: RdCmd2RcvEnLatency = 10, RdPtrOffsetRcvEn = 4
N0.C3.R2.S13: PI = 36
N2.C1.D0.R0.S11: Rcv En Fine Value = 272
N4.C0.D1.R1.S16: PI = 056, PtrOffset = 005
N6.C1: QCRM debug: extraRcvEnLatency = 0
N0.C3.R2.S14: PI = 34
N2.C1.D0.R0.S12: Rcv En Fine Value = 379
N4.C0.D1.R1.S17: PI = 039, PtrOffset = 004
N6.C1: SettingForTrainingStep: RdCmd2RcvEnLatency = 10, RdPtrOffsetRcvEn = 4
N0.C3.R2.S15: PI = 35
N2.C1.D0.R0.S13: Rcv En Fine Value = 371
N4.C0.D1.R1.S09: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N6.C2: QCRM debug: extraRcvEnLatency = 0
N0.C3.R2.S16: PI = 34
N2.C1.D0.R0.S14: Rcv En Fine Value = 269
N4.C0.D1.R1.S10: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N6.C2: SettingForTrainingStep: RdCmd2RcvEnLatency = 10, RdPtrOffsetRcvEn = 4
N0.C3.R2.S17: PI = 35
N2.C1.D0.R0.S15: Rcv En Fine Value = 296
N4.C0.D1.R1.S11: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N6.C3: QCRM debug: extraRcvEnLatency = 0
STOP_DATA_RX_DQS
N2.C1.D0.R0.S16: Rcv En Fine Value = 314
N4.C0.D1.R1.S12: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N6.C3: SettingForTrainingStep: RdCmd2RcvEnLatency = 10, RdPtrOffsetRcvEn = 4
N0: RunTrainStep: Final status = 0
N2.C1.D0.R0.S17: Rcv En Fine Value = 362
N4.C0.D1.R1.S13: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N6.C0.D0.R0: RcvEnFine: Initial RdCmd2RcvEnLatency = 10, Initial RdPtrOffsetRcvEn = 4

END - Basic Read DQ/DQS Training       Time         17707 ms
N2.C1.D0.R0: Starting preamble search lower nibbles
N4.C0.D1.R1.S14: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N6.C0.D0.R0.S00: Rcv En Fine Value = 277

START - Basic Receive Enable Training
N2.C1.D0.R0.S00: PI = 000, PtrOffset = 005
N4.C0.D1.R1.S15: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N6.C0.D0.R0.S01: Rcv En Fine Value = 383
Checkpoint Code: Socket 0, 0xB7, 0x02, 0x0000
N2.C1.D0.R0.S01: PI = 046, PtrOffset = 004
N4.C0.D1.R1.S16: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N6.C0.D0.R0.S02: Rcv En Fine Value = 354
N0.C0: QCRM debug: extraRcvEnLatency = 0
N2.C1.D0.R0.S02: PI = 016, PtrOffset = 004
N4.C0.D1.R1.S17: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N6.C0.D0.R0.S03: Rcv En Fine Value = 335
N0.C0: SettingForTrainingStep: RdCmd2RcvEnLatency = 10, RdPtrOffsetRcvEn = 4
N2.C1.D0.R0.S03: PI = 060, PtrOffset = 005
N4.C0.D1.R1.S09: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N6.C0.D0.R0.S04: Rcv En Fine Value = 328
N0.C1: QCRM debug: extraRcvEnLatency = 0
N2.C1.D0.R0.S04: PI = 052, PtrOffset = 005
N4.C0.D1.R1.S10: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N6.C0.D0.R0.S05: Rcv En Fine Value = 350
N0.C1: SettingForTrainingStep: RdCmd2RcvEnLatency = 10, RdPtrOffsetRcvEn = 4
N2.C1.D0.R0.S05: PI = 013, PtrOffset = 004
N4.C0.D1.R1.S11: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N6.C0.D0.R0.S06: Rcv En Fine Value = 381
N0.C2: QCRM debug: extraRcvEnLatency = 0
N2.C1.D0.R0.S06: PI = 038, PtrOffset = 004
N4.C0.D1.R1.S12: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N6.C0.D0.R0.S07: Rcv En Fine Value = 276
N0.C2: SettingForTrainingStep: RdCmd2RcvEnLatency = 10, RdPtrOffsetRcvEn = 4
N2.C1.D0.R0.S07: PI = 059, PtrOffset = 004
N4.C0.D1.R1.S13: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N6.C0.D0.R0.S08: Rcv En Fine Value = 324
N0.C3: QCRM debug: extraRcvEnLatency = 0
N2.C1.D0.R0.S08: PI = 039, PtrOffset = 005
N4.C0.D1.R1.S14: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N6.C0.D0.R0.S09: Rcv En Fine Value = 275
N0.C3: SettingForTrainingStep: RdCmd2RcvEnLatency = 10, RdPtrOffsetRcvEn = 4
N2.C1.D0.R0.S00: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N4.C0.D1.R1.S15: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N6.C0.D0.R0.S10: Rcv En Fine Value = 383
N0.C0.D0.R0: RcvEnFine: Initial RdCmd2RcvEnLatency = 10, Initial RdPtrOffsetRcvEn = 4
N2.C1.D0.R0.S01: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N4.C0.D1.R1.S16: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N6.C0.D0.R0.S11: Rcv En Fine Value = 354
N0.C0.D0.R0.S00: Rcv En Fine Value = 266
N2.C1.D0.R0.S02: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N4.C0.D1.R1.S17: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N6.C0.D0.R0.S12: Rcv En Fine Value = 335
N0.C0.D0.R0.S01: Rcv En Fine Value = 376
N2.C1.D0.R0.S03: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N4.C0.D1.R1.S09: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N6.C0.D0.R0.S13: Rcv En Fine Value = 327
N0.C0.D0.R0.S02: Rcv En Fine Value = 348
N2.C1.D0.R0.S04: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N4.C0.D1.R1.S10: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N6.C0.D0.R0.S14: Rcv En Fine Value = 351
N0.C0.D0.R0.S03: Rcv En Fine Value = 328
N2.C1.D0.R0.S05: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N4.C0.D1.R1.S11: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N6.C0.D0.R0.S15: Rcv En Fine Value = 378
N0.C0.D0.R0.S04: Rcv En Fine Value = 319
N2.C1.D0.R0.S06: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N4.C0.D1.R1.S12: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N6.C0.D0.R0.S16: Rcv En Fine Value = 273
N0.C0.D0.R0.S05: Rcv En Fine Value = 341
N2.C1.D0.R0.S07: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N4.C0.D1.R1.S13: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N6.C0.D0.R0.S17: Rcv En Fine Value = 321
N0.C0.D0.R0.S06: Rcv En Fine Value = 378
N2.C1.D0.R0.S08: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N4.C0.D1.R1.S14: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N6.C0.D0.R0: Starting preamble search lower nibbles
N0.C0.D0.R0.S07: Rcv En Fine Value = 268
N2.C1.D0.R0.S00: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N4.C0.D1.R1.S15: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N6.C0.D0.R0.S00: PI = 021, PtrOffset = 004
N0.C0.D0.R0.S08: Rcv En Fine Value = 316
N2.C1.D0.R0.S01: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N4.C0.D1.R1.S16: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N6.C0.D0.R0.S01: PI = 063, PtrOffset = 005
N0.C0.D0.R0.S09: Rcv En Fine Value = 268
N2.C1.D0.R0.S02: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N4.C0.D1.R1.S17: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N6.C0.D0.R0.S02: PI = 034, PtrOffset = 005
N0.C0.D0.R0.S10: Rcv En Fine Value = 374
N2.C1.D0.R0.S03: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N4.C0.D1.R1.S09: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N6.C0.D0.R0.S03: PI = 015, PtrOffset = 005
N0.C0.D0.R0.S11: Rcv En Fine Value = 345
N2.C1.D0.R0.S04: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N4.C0.D1.R1.S10: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N6.C0.D0.R0.S04: PI = 008, PtrOffset = 005
N0.C0.D0.R0.S12: Rcv En Fine Value = 326
N2.C1.D0.R0.S05: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N4.C0.D1.R1.S11: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N6.C0.D0.R0.S05: PI = 030, PtrOffset = 005
N0.C0.D0.R0.S13: Rcv En Fine Value = 321
N2.C1.D0.R0.S06: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N4.C0.D1.R1.S12: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N6.C0.D0.R0.S06: PI = 061, PtrOffset = 005
N0.C0.D0.R0.S14: Rcv En Fine Value = 342
N2.C1.D0.R0.S07: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N4.C0.D1.R1.S13: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N6.C0.D0.R0.S07: PI = 020, PtrOffset = 004
N0.C0.D0.R0.S15: Rcv En Fine Value = 375
N2.C1.D0.R0.S08: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N4.C0.D1.R1.S14: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N6.C0.D0.R0.S08: PI = 004, PtrOffset = 005
N0.C0.D0.R0.S16: Rcv En Fine Value = 270
N2.C1.D0.R0.S00: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N4.C0.D1.R1.S15: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N6.C0.D0.R0.S00: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N0.C0.D0.R0.S17: Rcv En Fine Value = 313
N2.C1.D0.R0.S01: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N4.C0.D1.R1.S16: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N6.C0.D0.R0.S01: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N0.C0.D0.R0: Starting preamble search lower nibbles
N2.C1.D0.R0.S02: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N4.C0.D1.R1.S17: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N6.C0.D0.R0.S02: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N0.C0.D0.R0.S00: PI = 010, PtrOffset = 004
N2.C1.D0.R0.S03: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N4.C0.D1.R1.S09: Preamble found at Latency = 007
N6.C0.D0.R0.S03: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N0.C0.D0.R0.S01: PI = 056, PtrOffset = 005
N2.C1.D0.R0.S04: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N4.C0.D1.R1.S10: Preamble found at Latency = 007
N6.C0.D0.R0.S04: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N0.C0.D0.R0.S02: PI = 028, PtrOffset = 005
N2.C1.D0.R0.S05: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N4.C0.D1.R1.S11: Preamble found at Latency = 007
N6.C0.D0.R0.S05: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N0.C0.D0.R0.S03: PI = 008, PtrOffset = 005
N2.C1.D0.R0.S06: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N4.C0.D1.R1.S12: Preamble found at Latency = 007
N6.C0.D0.R0.S06: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N0.C0.D0.R0.S04: PI = 063, PtrOffset = 004
N2.C1.D0.R0.S07: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N4.C0.D1.R1.S13: Preamble found at Latency = 007
N6.C0.D0.R0.S07: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N0.C0.D0.R0.S05: PI = 021, PtrOffset = 005
N2.C1.D0.R0.S08: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N4.C0.D1.R1.S14: Preamble found at Latency = 007
N6.C0.D0.R0.S08: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N0.C0.D0.R0.S06: PI = 058, PtrOffset = 005
N2.C1.D0.R0.S00: Preamble found at Latency = 008
N4.C0.D1.R1.S15: Preamble found at Latency = 007
N6.C0.D0.R0.S00: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N0.C0.D0.R0.S07: PI = 012, PtrOffset = 004
N2.C1.D0.R0.S01: Preamble found at Latency = 008
N4.C0.D1.R1.S16: Preamble found at Latency = 007
N6.C0.D0.R0.S01: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N0.C0.D0.R0.S08: PI = 060, PtrOffset = 004
N2.C1.D0.R0.S02: Preamble found at Latency = 008
N4.C0.D1.R1.S17: Preamble found at Latency = 007
N6.C0.D0.R0.S02: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N0.C0.D0.R0.S00: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N2.C1.D0.R0.S05: Preamble found at Latency = 008
N4.C0.D1.R1: Preamble found for all upper nibbles, adjusting Pi, Offset to center into preamble
N6.C0.D0.R0.S03: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N0.C0.D0.R0.S01: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N2.C1.D0.R0.S06: Preamble found at Latency = 008
N4.C0.D1.R1.S09: Total Receive Enable Delay = 1305
N6.C0.D0.R0.S04: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N0.C0.D0.R0.S02: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N2.C1.D0.R0.S07: Preamble found at Latency = 008
N4.C0.D1.R1.S10: Total Receive Enable Delay = 1287
N6.C0.D0.R0.S05: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N0.C0.D0.R0.S03: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N2.C1.D0.R0.S00: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N4.C0.D1.R1.S11: Total Receive Enable Delay = 1257
N6.C0.D0.R0.S06: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N0.C0.D0.R0.S04: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N2.C1.D0.R0.S01: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N4.C0.D1.R1.S12: Total Receive Enable Delay = 1236
N6.C0.D0.R0.S07: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N0.C0.D0.R0.S05: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N2.C1.D0.R0.S02: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N4.C0.D1.R1.S13: Total Receive Enable Delay = 1229
N6.C0.D0.R0.S08: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N0.C0.D0.R0.S06: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N2.C1.D0.R0.S03: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N4.C0.D1.R1.S14: Total Receive Enable Delay = 1253
N6.C0.D0.R0.S00: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N0.C0.D0.R0.S07: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N2.C1.D0.R0.S04: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N4.C0.D1.R1.S15: Total Receive Enable Delay = 1285
N6.C0.D0.R0.S01: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N0.C0.D0.R0.S08: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N2.C1.D0.R0.S05: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N4.C0.D1.R1.S16: Total Receive Enable Delay = 1304
N6.C0.D0.R0.S02: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N0.C0.D0.R0.S00: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N2.C1.D0.R0.S06: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N4.C0.D1.R1.S17: Total Receive Enable Delay = 1223
N6.C0.D0.R0.S03: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N0.C0.D0.R0.S01: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N2.C1.D0.R0.S07: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
START_DATA_REC_EN
N6.C0.D0.R0.S04: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N0.C0.D0.R0.S02: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N2.C1.D0.R0.S08: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N4.C0.S00: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N6.C0.D0.R0.S05: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N0.C0.D0.R0.S03: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N2.C1.D0.R0.S03: Preamble found at Latency = 007
N4.C0.S01: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N6.C0.D0.R0.S06: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N0.C0.D0.R0.S04: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N2.C1.D0.R0.S04: Preamble found at Latency = 007
N4.C0.S02: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 5
N6.C0.D0.R0.S07: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N0.C0.D0.R0.S05: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N2.C1.D0.R0.S08: Preamble found at Latency = 007
N4.C0.S03: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 5
N6.C0.D0.R0.S08: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N0.C0.D0.R0.S06: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N2.C1.D0.R0.S00: Total Receive Enable Delay = 1376
N4.C0.S04: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 5
N6.C0.D0.R0.S00: Preamble found at Latency = 008
N0.C0.D0.R0.S07: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N2.C1.D0.R0.S01: Total Receive Enable Delay = 1358
N4.C0.S05: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 5
N6.C0.D0.R0.S07: Preamble found at Latency = 008
N0.C0.D0.R0.S08: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N2.C1.D0.R0.S02: Total Receive Enable Delay = 1328
N4.C0.S06: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N6.C0.D0.R0.S00: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N0.C0.D0.R0.S00: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N2.C1.D0.R0.S03: Total Receive Enable Delay = 1308
N4.C0.S07: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N6.C0.D0.R0.S01: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N0.C0.D0.R0.S01: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N2.C1.D0.R0.S04: Total Receive Enable Delay = 1300
N4.C0.S08: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 5
N6.C0.D0.R0.S02: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N0.C0.D0.R0.S02: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N2.C1.D0.R0.S05: Total Receive Enable Delay = 1325
N4.C0.S09: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N6.C0.D0.R0.S03: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N0.C0.D0.R0.S03: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N2.C1.D0.R0.S06: Total Receive Enable Delay = 1350
N4.C0.S10: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N6.C0.D0.R0.S04: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N0.C0.D0.R0.S04: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N2.C1.D0.R0.S07: Total Receive Enable Delay = 1371
N4.C0.S11: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 5
N6.C0.D0.R0.S05: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N0.C0.D0.R0.S05: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N2.C1.D0.R0.S08: Total Receive Enable Delay = 1287
N4.C0.S12: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 5
N6.C0.D0.R0.S06: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N0.C0.D0.R0.S06: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N2.C1.D0.R0: Starting preamble search upper nibbles
N4.C0.S13: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 5
N6.C0.D0.R0.S07: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N0.C0.D0.R0.S07: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N2.C1.D0.R0.S09: PI = 001, PtrOffset = 005
N4.C0.S14: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 5
N6.C0.D0.R0.S08: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N0.C0.D0.R0.S08: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N2.C1.D0.R0.S10: PI = 045, PtrOffset = 004
N4.C0.S15: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N6.C0.D0.R0.S01: Preamble found at Latency = 007
N0.C0.D0.R0.S00: Preamble found at Latency = 008
N2.C1.D0.R0.S11: PI = 016, PtrOffset = 004
N4.C0.S16: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N6.C0.D0.R0.S02: Preamble found at Latency = 007
N0.C0.D0.R0.S07: Preamble found at Latency = 008
N2.C1.D0.R0.S12: PI = 059, PtrOffset = 005
N4.C0.S17: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 5
N6.C0.D0.R0.S03: Preamble found at Latency = 007
N0.C0.D0.R0.S00: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N2.C1.D0.R0.S13: PI = 051, PtrOffset = 005
N4.C0.D0.R0.S00: RcvEn: plus1 = 1, minus1 = 0, PI = 43, DB = 0
N6.C0.D0.R0.S04: Preamble found at Latency = 007
N0.C0.D0.R0.S01: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N2.C1.D0.R0.S14: PI = 013, PtrOffset = 004
N4.C0.D0.R0.S01: RcvEn: plus1 = 1, minus1 = 0, PI = 22, DB = 0
N6.C0.D0.R0.S05: Preamble found at Latency = 007
N0.C0.D0.R0.S02: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N2.C1.D0.R0.S15: PI = 040, PtrOffset = 004
N4.C0.D0.R0.S02: RcvEn: plus1 = 1, minus1 = 0, PI = 60, DB = 1
N6.C0.D0.R0.S06: Preamble found at Latency = 007
N0.C0.D0.R0.S03: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N2.C1.D0.R0.S16: PI = 058, PtrOffset = 004
N4.C0.D0.R0.S03: RcvEn: plus1 = 1, minus1 = 0, PI = 36, DB = 0
N6.C0.D0.R0.S08: Preamble found at Latency = 007
N0.C0.D0.R0.S04: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N2.C1.D0.R0.S17: PI = 042, PtrOffset = 005
N4.C0.D0.R0.S04: RcvEn: plus1 = 1, minus1 = 0, PI = 29, DB = 0
N6.C0.D0.R0.S00: Total Receive Enable Delay = 1333
N0.C0.D0.R0.S05: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N2.C1.D0.R0.S09: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N4.C0.D0.R0.S05: RcvEn: plus1 = 1, minus1 = 0, PI = 53, DB = 1
N6.C0.D0.R0.S01: Total Receive Enable Delay = 1311
N0.C0.D0.R0.S06: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N2.C1.D0.R0.S10: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N4.C0.D0.R0.S06: RcvEn: plus1 = 1, minus1 = 0, PI = 22, DB = 0
N6.C0.D0.R0.S02: Total Receive Enable Delay = 1282
N0.C0.D0.R0.S07: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N2.C1.D0.R0.S11: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N4.C0.D0.R0.S07: RcvEn: plus1 = 1, minus1 = 0, PI = 45, DB = 0
N6.C0.D0.R0.S03: Total Receive Enable Delay = 1263
N0.C0.D0.R0.S08: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N2.C1.D0.R0.S12: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N4.C0.D0.R0.S08: RcvEn: plus1 = 1, minus1 = 0, PI = 26, DB = 0
N6.C0.D0.R0.S04: Total Receive Enable Delay = 1256
N0.C0.D0.R0.S01: Preamble found at Latency = 007
N2.C1.D0.R0.S13: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N4.C0.D0.R0.S09: RcvEn: plus1 = 1, minus1 = 0, PI = 42, DB = 0
N6.C0.D0.R0.S05: Total Receive Enable Delay = 1278
N0.C0.D0.R0.S02: Preamble found at Latency = 007
N2.C1.D0.R0.S14: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N4.C0.D0.R0.S10: RcvEn: plus1 = 1, minus1 = 0, PI = 22, DB = 0
N6.C0.D0.R0.S06: Total Receive Enable Delay = 1309
N0.C0.D0.R0.S03: Preamble found at Latency = 007
N2.C1.D0.R0.S15: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N4.C0.D0.R0.S11: RcvEn: plus1 = 1, minus1 = 0, PI = 58, DB = 1
N6.C0.D0.R0.S07: Total Receive Enable Delay = 1332
N0.C0.D0.R0.S04: Preamble found at Latency = 007
N2.C1.D0.R0.S16: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N4.C0.D0.R0.S12: RcvEn: plus1 = 1, minus1 = 0, PI = 37, DB = 0
N6.C0.D0.R0.S08: Total Receive Enable Delay = 1252
N0.C0.D0.R0.S05: Preamble found at Latency = 007
N2.C1.D0.R0.S17: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N4.C0.D0.R0.S13: RcvEn: plus1 = 1, minus1 = 0, PI = 29, DB = 0
N6.C0.D0.R0: Starting preamble search upper nibbles
N0.C0.D0.R0.S06: Preamble found at Latency = 007
N2.C1.D0.R0.S09: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N4.C0.D0.R0.S14: RcvEn: plus1 = 1, minus1 = 0, PI = 50, DB = 1
N6.C0.D0.R0.S09: PI = 019, PtrOffset = 004
N0.C0.D0.R0.S08: Preamble found at Latency = 007
N2.C1.D0.R0.S10: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N4.C0.D0.R0.S15: RcvEn: plus1 = 1, minus1 = 0, PI = 20, DB = 0
N6.C0.D0.R0.S10: PI = 063, PtrOffset = 005
N0.C0.D0.R0.S00: Total Receive Enable Delay = 1322
N2.C1.D0.R0.S11: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N4.C0.D0.R0.S16: RcvEn: plus1 = 1, minus1 = 0, PI = 43, DB = 0
N6.C0.D0.R0.S11: PI = 034, PtrOffset = 005
N0.C0.D0.R0.S01: Total Receive Enable Delay = 1304
N2.C1.D0.R0.S12: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N4.C0.D0.R0.S17: RcvEn: plus1 = 1, minus1 = 0, PI = 23, DB = 0
N6.C0.D0.R0.S12: PI = 015, PtrOffset = 005
N0.C0.D0.R0.S02: Total Receive Enable Delay = 1276
N2.C1.D0.R0.S13: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N4.C0.D0.R1.S00: RcvEn: plus1 = 1, minus1 = 0, PI = 43, DB = 0
N6.C0.D0.R0.S13: PI = 007, PtrOffset = 005
N0.C0.D0.R0.S03: Total Receive Enable Delay = 1256
N2.C1.D0.R0.S14: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N4.C0.D0.R1.S01: RcvEn: plus1 = 1, minus1 = 0, PI = 22, DB = 0
N6.C0.D0.R0.S14: PI = 031, PtrOffset = 005
N0.C0.D0.R0.S04: Total Receive Enable Delay = 1247
N2.C1.D0.R0.S15: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N4.C0.D0.R1.S02: RcvEn: plus1 = 1, minus1 = 0, PI = 60, DB = 1
N6.C0.D0.R0.S15: PI = 058, PtrOffset = 005
N0.C0.D0.R0.S05: Total Receive Enable Delay = 1269
N2.C1.D0.R0.S16: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N4.C0.D0.R1.S03: RcvEn: plus1 = 1, minus1 = 0, PI = 36, DB = 0
N6.C0.D0.R0.S16: PI = 017, PtrOffset = 004
N0.C0.D0.R0.S06: Total Receive Enable Delay = 1306
N2.C1.D0.R0.S17: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N4.C0.D0.R1.S04: RcvEn: plus1 = 1, minus1 = 0, PI = 29, DB = 0
N6.C0.D0.R0.S17: PI = 001, PtrOffset = 005
N0.C0.D0.R0.S07: Total Receive Enable Delay = 1324
N2.C1.D0.R0.S09: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N4.C0.D0.R1.S05: RcvEn: plus1 = 1, minus1 = 0, PI = 53, DB = 1
N6.C0.D0.R0.S09: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N0.C0.D0.R0.S08: Total Receive Enable Delay = 1244
N2.C1.D0.R0.S10: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N4.C0.D0.R1.S06: RcvEn: plus1 = 1, minus1 = 0, PI = 22, DB = 0
N6.C0.D0.R0.S10: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N0.C0.D0.R0: Starting preamble search upper nibbles
N2.C1.D0.R0.S11: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N4.C0.D0.R1.S07: RcvEn: plus1 = 1, minus1 = 0, PI = 45, DB = 0
N6.C0.D0.R0.S11: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N0.C0.D0.R0.S09: PI = 012, PtrOffset = 004
N2.C1.D0.R0.S12: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N4.C0.D0.R1.S08: RcvEn: plus1 = 1, minus1 = 0, PI = 26, DB = 0
N6.C0.D0.R0.S12: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N0.C0.D0.R0.S10: PI = 054, PtrOffset = 005
N2.C1.D0.R0.S13: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N4.C0.D0.R1.S09: RcvEn: plus1 = 1, minus1 = 0, PI = 42, DB = 0
N6.C0.D0.R0.S13: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N0.C0.D0.R0.S11: PI = 025, PtrOffset = 005
N2.C1.D0.R0.S14: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N4.C0.D0.R1.S10: RcvEn: plus1 = 1, minus1 = 0, PI = 22, DB = 0
N6.C0.D0.R0.S14: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N0.C0.D0.R0.S12: PI = 006, PtrOffset = 005
N2.C1.D0.R0.S15: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N4.C0.D0.R1.S11: RcvEn: plus1 = 1, minus1 = 0, PI = 58, DB = 1
N6.C0.D0.R0.S15: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N0.C0.D0.R0.S13: PI = 001, PtrOffset = 005
N2.C1.D0.R0.S16: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N4.C0.D0.R1.S12: RcvEn: plus1 = 1, minus1 = 0, PI = 37, DB = 0
N6.C0.D0.R0.S16: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N0.C0.D0.R0.S14: PI = 022, PtrOffset = 005
N2.C1.D0.R0.S17: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N4.C0.D0.R1.S13: RcvEn: plus1 = 1, minus1 = 0, PI = 29, DB = 0
N6.C0.D0.R0.S17: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N0.C0.D0.R0.S15: PI = 055, PtrOffset = 005
N2.C1.D0.R0.S09: Preamble found at Latency = 008
N4.C0.D0.R1.S14: RcvEn: plus1 = 1, minus1 = 0, PI = 50, DB = 1
N6.C0.D0.R0.S09: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N0.C0.D0.R0.S16: PI = 014, PtrOffset = 004
N2.C1.D0.R0.S10: Preamble found at Latency = 008
N4.C0.D0.R1.S15: RcvEn: plus1 = 1, minus1 = 0, PI = 20, DB = 0
N6.C0.D0.R0.S10: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N0.C0.D0.R0.S17: PI = 057, PtrOffset = 004
N2.C1.D0.R0.S11: Preamble found at Latency = 008
N4.C0.D0.R1.S16: RcvEn: plus1 = 1, minus1 = 0, PI = 43, DB = 0
N6.C0.D0.R0.S11: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N0.C0.D0.R0.S09: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N2.C1.D0.R0.S14: Preamble found at Latency = 008
N4.C0.D0.R1.S17: RcvEn: plus1 = 1, minus1 = 0, PI = 23, DB = 0
N6.C0.D0.R0.S12: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N0.C0.D0.R0.S10: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N2.C1.D0.R0.S15: Preamble found at Latency = 008
N4.C0.D1.R0.S00: RcvEn: plus1 = 1, minus1 = 0, PI = 28, DB = 0
N6.C0.D0.R0.S13: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N0.C0.D0.R0.S11: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N2.C1.D0.R0.S16: Preamble found at Latency = 008
N4.C0.D1.R0.S01: RcvEn: plus1 = 1, minus1 = 0, PI = 07, DB = 1
N6.C0.D0.R0.S14: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N0.C0.D0.R0.S12: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N2.C1.D0.R0.S09: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N4.C0.D1.R0.S02: RcvEn: plus1 = 1, minus1 = 0, PI = 41, DB = 0
N6.C0.D0.R0.S15: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N0.C0.D0.R0.S13: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N2.C1.D0.R0.S10: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N4.C0.D1.R0.S03: RcvEn: plus1 = 1, minus1 = 0, PI = 20, DB = 0
N6.C0.D0.R0.S16: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N0.C0.D0.R0.S14: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N2.C1.D0.R0.S11: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N4.C0.D1.R0.S04: RcvEn: plus1 = 1, minus1 = 0, PI = 14, DB = 1
N6.C0.D0.R0.S17: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N0.C0.D0.R0.S15: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N2.C1.D0.R0.S12: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N4.C0.D1.R0.S05: RcvEn: plus1 = 1, minus1 = 0, PI = 39, DB = 0
N6.C0.D0.R0.S09: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N0.C0.D0.R0.S16: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N2.C1.D0.R0.S13: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N4.C0.D1.R0.S06: RcvEn: plus1 = 1, minus1 = 0, PI = 07, DB = 1
N6.C0.D0.R0.S10: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N0.C0.D0.R0.S17: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N2.C1.D0.R0.S14: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N4.C0.D1.R0.S07: RcvEn: plus1 = 1, minus1 = 0, PI = 28, DB = 0
N6.C0.D0.R0.S11: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N0.C0.D0.R0.S09: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N2.C1.D0.R0.S15: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N4.C0.D1.R0.S08: RcvEn: plus1 = 1, minus1 = 0, PI = 09, DB = 1
N6.C0.D0.R0.S12: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N0.C0.D0.R0.S10: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N2.C1.D0.R0.S16: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N4.C0.D1.R0.S09: RcvEn: plus1 = 1, minus1 = 0, PI = 25, DB = 0
N6.C0.D0.R0.S13: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N0.C0.D0.R0.S11: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N2.C1.D0.R0.S17: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N4.C0.D1.R0.S10: RcvEn: plus1 = 1, minus1 = 0, PI = 07, DB = 1
N6.C0.D0.R0.S14: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N0.C0.D0.R0.S12: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N2.C1.D0.R0.S12: Preamble found at Latency = 007
N4.C0.D1.R0.S11: RcvEn: plus1 = 1, minus1 = 0, PI = 42, DB = 0
N6.C0.D0.R0.S15: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N0.C0.D0.R0.S13: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N2.C1.D0.R0.S13: Preamble found at Latency = 007
N4.C0.D1.R0.S12: RcvEn: plus1 = 1, minus1 = 0, PI = 19, DB = 0
N6.C0.D0.R0.S16: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N0.C0.D0.R0.S14: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N2.C1.D0.R0.S17: Preamble found at Latency = 007
N4.C0.D1.R0.S13: RcvEn: plus1 = 1, minus1 = 0, PI = 14, DB = 1
N6.C0.D0.R0.S17: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N0.C0.D0.R0.S15: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N2.C1.D0.R0: Preamble found for all upper nibbles, adjusting Pi, Offset to center into preamble
N4.C0.D1.R0.S14: RcvEn: plus1 = 1, minus1 = 0, PI = 36, DB = 0
N6.C0.D0.R0.S09: Preamble found at Latency = 008
N0.C0.D0.R0.S16: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N2.C1.D0.R0.S09: Total Receive Enable Delay = 1377
N4.C0.D1.R0.S15: RcvEn: plus1 = 1, minus1 = 0, PI = 05, DB = 1
N6.C0.D0.R0.S16: Preamble found at Latency = 008
N0.C0.D0.R0.S17: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N2.C1.D0.R0.S10: Total Receive Enable Delay = 1357
N4.C0.D1.R0.S16: RcvEn: plus1 = 1, minus1 = 0, PI = 25, DB = 0
N6.C0.D0.R0.S09: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N0.C0.D0.R0.S09: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N2.C1.D0.R0.S11: Total Receive Enable Delay = 1328
N4.C0.D1.R0.S17: RcvEn: plus1 = 1, minus1 = 0, PI = 07, DB = 1
N6.C0.D0.R0.S10: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N0.C0.D0.R0.S10: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N2.C1.D0.R0.S12: Total Receive Enable Delay = 1307
N4.C0.D1.R1.S00: RcvEn: plus1 = 1, minus1 = 0, PI = 28, DB = 0
N6.C0.D0.R0.S11: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N0.C0.D0.R0.S11: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N2.C1.D0.R0.S13: Total Receive Enable Delay = 1299
N4.C0.D1.R1.S01: RcvEn: plus1 = 1, minus1 = 0, PI = 07, DB = 1
N6.C0.D0.R0.S12: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N0.C0.D0.R0.S12: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N2.C1.D0.R0.S14: Total Receive Enable Delay = 1325
N4.C0.D1.R1.S02: RcvEn: plus1 = 1, minus1 = 0, PI = 41, DB = 0
N6.C0.D0.R0.S13: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N0.C0.D0.R0.S13: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N2.C1.D0.R0.S15: Total Receive Enable Delay = 1352
N4.C0.D1.R1.S03: RcvEn: plus1 = 1, minus1 = 0, PI = 20, DB = 0
N6.C0.D0.R0.S14: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N0.C0.D0.R0.S14: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N2.C1.D0.R0.S16: Total Receive Enable Delay = 1370
N4.C0.D1.R1.S04: RcvEn: plus1 = 1, minus1 = 0, PI = 14, DB = 1
N6.C0.D0.R0.S15: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N0.C0.D0.R0.S15: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N2.C1.D0.R0.S17: Total Receive Enable Delay = 1290
N4.C0.D1.R1.S05: RcvEn: plus1 = 1, minus1 = 0, PI = 39, DB = 0
N6.C0.D0.R0.S16: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N0.C0.D0.R0.S16: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N2.C1.D0.R1: RcvEnFine: Initial RdCmd2RcvEnLatency = 10, Initial RdPtrOffsetRcvEn = 4
N4.C0.D1.R1.S06: RcvEn: plus1 = 1, minus1 = 0, PI = 07, DB = 1
N6.C0.D0.R0.S17: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N0.C0.D0.R0.S17: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N2.C1.D0.R1.S00: Rcv En Fine Value = 321
N4.C0.D1.R1.S07: RcvEn: plus1 = 1, minus1 = 0, PI = 28, DB = 0
N6.C0.D0.R0.S10: Preamble found at Latency = 007
N0.C0.D0.R0.S09: Preamble found at Latency = 008
N2.C1.D0.R1.S01: Rcv En Fine Value = 302
N4.C0.D1.R1.S08: RcvEn: plus1 = 1, minus1 = 0, PI = 09, DB = 1
N6.C0.D0.R0.S11: Preamble found at Latency = 007
N0.C0.D0.R0.S16: Preamble found at Latency = 008
N2.C1.D0.R1.S02: Rcv En Fine Value = 271
N4.C0.D1.R1.S09: RcvEn: plus1 = 1, minus1 = 0, PI = 25, DB = 0
N6.C0.D0.R0.S12: Preamble found at Latency = 007
N0.C0.D0.R0.S09: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N2.C1.D0.R1.S03: Rcv En Fine Value = 378
N4.C0.D1.R1.S10: RcvEn: plus1 = 1, minus1 = 0, PI = 07, DB = 1
N6.C0.D0.R0.S13: Preamble found at Latency = 007
N0.C0.D0.R0.S10: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N2.C1.D0.R1.S04: Rcv En Fine Value = 373
N4.C0.D1.R1.S11: RcvEn: plus1 = 1, minus1 = 0, PI = 42, DB = 0
N6.C0.D0.R0.S14: Preamble found at Latency = 007
N0.C0.D0.R0.S11: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N2.C1.D0.R1.S05: Rcv En Fine Value = 268
N4.C0.D1.R1.S12: RcvEn: plus1 = 1, minus1 = 0, PI = 19, DB = 0
N6.C0.D0.R0.S15: Preamble found at Latency = 007
N0.C0.D0.R0.S12: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N2.C1.D0.R1.S06: Rcv En Fine Value = 293
N4.C0.D1.R1.S13: RcvEn: plus1 = 1, minus1 = 0, PI = 14, DB = 1
N6.C0.D0.R0.S17: Preamble found at Latency = 007
N0.C0.D0.R0.S13: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N2.C1.D0.R1.S07: Rcv En Fine Value = 314
N4.C0.D1.R1.S14: RcvEn: plus1 = 1, minus1 = 0, PI = 36, DB = 0
N6.C0.D0.R0: Preamble found for all upper nibbles, adjusting Pi, Offset to center into preamble
N0.C0.D0.R0.S14: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N2.C1.D0.R1.S08: Rcv En Fine Value = 360
N4.C0.D1.R1.S15: RcvEn: plus1 = 1, minus1 = 0, PI = 05, DB = 1
N6.C0.D0.R0.S09: Total Receive Enable Delay = 1331
N0.C0.D0.R0.S15: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N2.C1.D0.R1.S09: Rcv En Fine Value = 321
N4.C0.D1.R1.S16: RcvEn: plus1 = 1, minus1 = 0, PI = 25, DB = 0
N6.C0.D0.R0.S10: Total Receive Enable Delay = 1311
N0.C0.D0.R0.S16: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N2.C1.D0.R1.S10: Rcv En Fine Value = 302
N4.C0.D1.R1.S17: RcvEn: plus1 = 1, minus1 = 0, PI = 07, DB = 1
N6.C0.D0.R0.S11: Total Receive Enable Delay = 1282
N0.C0.D0.R0.S17: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N2.C1.D0.R1.S11: Rcv En Fine Value = 271
STOP_DATA_REC_EN
N6.C0.D0.R0.S12: Total Receive Enable Delay = 1263
N0.C0.D0.R0.S10: Preamble found at Latency = 007
N2.C1.D0.R1.S12: Rcv En Fine Value = 381
N4.C1.D0.R0: RcvEnFine: Initial RdCmd2RcvEnLatency = 10, Initial RdPtrOffsetRcvEn = 4
N6.C0.D0.R0.S13: Total Receive Enable Delay = 1255
N0.C0.D0.R0.S11: Preamble found at Latency = 007
N2.C1.D0.R1.S13: Rcv En Fine Value = 371
N4.C1.D0.R0.S00: Rcv En Fine Value = 317
N6.C0.D0.R0.S14: Total Receive Enable Delay = 1279
N0.C0.D0.R0.S12: Preamble found at Latency = 007
N2.C1.D0.R1.S14: Rcv En Fine Value = 268
N4.C1.D0.R0.S01: Rcv En Fine Value = 296
N6.C0.D0.R0.S15: Total Receive Enable Delay = 1306
N0.C0.D0.R0.S13: Preamble found at Latency = 007
N2.C1.D0.R1.S15: Rcv En Fine Value = 296
N4.C1.D0.R0.S02: Rcv En Fine Value = 266
N6.C0.D0.R0.S16: Total Receive Enable Delay = 1329
N0.C0.D0.R0.S14: Preamble found at Latency = 007
N2.C1.D0.R1.S16: Rcv En Fine Value = 316
N4.C1.D0.R0.S03: Rcv En Fine Value = 376
N6.C0.D0.R0.S17: Total Receive Enable Delay = 1249
N0.C0.D0.R0.S15: Preamble found at Latency = 007
N2.C1.D0.R1.S17: Rcv En Fine Value = 360
N4.C1.D0.R0.S04: Rcv En Fine Value = 369
N6.C0.D0.R1: RcvEnFine: Initial RdCmd2RcvEnLatency = 10, Initial RdPtrOffsetRcvEn = 4
N0.C0.D0.R0.S17: Preamble found at Latency = 007
N2.C1.D0.R1: Starting preamble search lower nibbles
N4.C1.D0.R0.S05: Rcv En Fine Value = 265
N6.C0.D0.R1.S00: Rcv En Fine Value = 276
N0.C0.D0.R0: Preamble found for all upper nibbles, adjusting Pi, Offset to center into preamble
N2.C1.D0.R1.S00: PI = 001, PtrOffset = 005
N4.C1.D0.R0.S06: Rcv En Fine Value = 287
N6.C0.D0.R1.S01: Rcv En Fine Value = 383
N0.C0.D0.R0.S09: Total Receive Enable Delay = 1324
N2.C1.D0.R1.S01: PI = 046, PtrOffset = 004
N4.C1.D0.R0.S07: Rcv En Fine Value = 307
N6.C0.D0.R1.S02: Rcv En Fine Value = 353
N0.C0.D0.R0.S10: Total Receive Enable Delay = 1302
N2.C1.D0.R1.S02: PI = 015, PtrOffset = 004
N4.C1.D0.R0.S08: Rcv En Fine Value = 355
N6.C0.D0.R1.S03: Rcv En Fine Value = 334
N0.C0.D0.R0.S11: Total Receive Enable Delay = 1273
N2.C1.D0.R1.S03: PI = 058, PtrOffset = 005
N4.C1.D0.R0.S09: Rcv En Fine Value = 317
N6.C0.D0.R1.S04: Rcv En Fine Value = 328
N0.C0.D0.R0.S12: Total Receive Enable Delay = 1254
N2.C1.D0.R1.S04: PI = 053, PtrOffset = 005
N4.C1.D0.R0.S10: Rcv En Fine Value = 298
N6.C0.D0.R1.S05: Rcv En Fine Value = 347
N0.C0.D0.R0.S13: Total Receive Enable Delay = 1249
N2.C1.D0.R1.S05: PI = 012, PtrOffset = 004
N4.C1.D0.R0.S11: Rcv En Fine Value = 267
N6.C0.D0.R1.S06: Rcv En Fine Value = 382
N0.C0.D0.R0.S14: Total Receive Enable Delay = 1270
N2.C1.D0.R1.S06: PI = 037, PtrOffset = 004
N4.C1.D0.R0.S12: Rcv En Fine Value = 377
N6.C0.D0.R1.S07: Rcv En Fine Value = 276
N0.C0.D0.R0.S15: Total Receive Enable Delay = 1303
N2.C1.D0.R1.S07: PI = 058, PtrOffset = 004
N4.C1.D0.R0.S13: Rcv En Fine Value = 369
N6.C0.D0.R1.S08: Rcv En Fine Value = 323
N0.C0.D0.R0.S16: Total Receive Enable Delay = 1326
N2.C1.D0.R1.S08: PI = 040, PtrOffset = 005
N4.C1.D0.R0.S14: Rcv En Fine Value = 264
N6.C0.D0.R1.S09: Rcv En Fine Value = 273
N0.C0.D0.R0.S17: Total Receive Enable Delay = 1241
N2.C1.D0.R1.S00: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N4.C1.D0.R0.S15: Rcv En Fine Value = 289
N6.C0.D0.R1.S10: Rcv En Fine Value = 257
N0.C0.D0.R1: RcvEnFine: Initial RdCmd2RcvEnLatency = 10, Initial RdPtrOffsetRcvEn = 4
N2.C1.D0.R1.S01: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N4.C1.D0.R0.S16: Rcv En Fine Value = 309
N6.C0.D0.R1.S11: Rcv En Fine Value = 353
N0.C0.D0.R1.S00: Rcv En Fine Value = 269
N2.C1.D0.R1.S02: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N4.C1.D0.R0.S17: Rcv En Fine Value = 355
N6.C0.D0.R1.S12: Rcv En Fine Value = 332
N0.C0.D0.R1.S01: Rcv En Fine Value = 377
N2.C1.D0.R1.S03: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N4.C1.D0.R0: Starting preamble search lower nibbles
N6.C0.D0.R1.S13: Rcv En Fine Value = 326
N0.C0.D0.R1.S02: Rcv En Fine Value = 347
N2.C1.D0.R1.S04: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N4.C1.D0.R0.S00: PI = 061, PtrOffset = 004
N6.C0.D0.R1.S14: Rcv En Fine Value = 348
N0.C0.D0.R1.S03: Rcv En Fine Value = 328
N2.C1.D0.R1.S05: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N4.C1.D0.R0.S01: PI = 040, PtrOffset = 004
N6.C0.D0.R1.S15: Rcv En Fine Value = 382
N0.C0.D0.R1.S04: Rcv En Fine Value = 319
N2.C1.D0.R1.S06: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N4.C1.D0.R0.S02: PI = 010, PtrOffset = 004
N6.C0.D0.R1.S16: Rcv En Fine Value = 274
N0.C0.D0.R1.S05: Rcv En Fine Value = 340
N2.C1.D0.R1.S07: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N4.C1.D0.R0.S03: PI = 056, PtrOffset = 005
N6.C0.D0.R1.S17: Rcv En Fine Value = 320
N0.C0.D0.R1.S06: Rcv En Fine Value = 379
N2.C1.D0.R1.S08: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N4.C1.D0.R0.S04: PI = 049, PtrOffset = 005
N6.C0.D0.R1: Starting preamble search lower nibbles
N0.C0.D0.R1.S07: Rcv En Fine Value = 268
N2.C1.D0.R1.S00: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N4.C1.D0.R0.S05: PI = 009, PtrOffset = 004
N6.C0.D0.R1.S00: PI = 020, PtrOffset = 004
N0.C0.D0.R1.S08: Rcv En Fine Value = 315
N2.C1.D0.R1.S01: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N4.C1.D0.R0.S06: PI = 031, PtrOffset = 004
N6.C0.D0.R1.S01: PI = 063, PtrOffset = 005
N0.C0.D0.R1.S09: Rcv En Fine Value = 265
N2.C1.D0.R1.S02: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N4.C1.D0.R0.S07: PI = 051, PtrOffset = 004
N6.C0.D0.R1.S02: PI = 033, PtrOffset = 005
N0.C0.D0.R1.S10: Rcv En Fine Value = 376
N2.C1.D0.R1.S03: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N4.C1.D0.R0.S08: PI = 035, PtrOffset = 005
N6.C0.D0.R1.S03: PI = 014, PtrOffset = 005
N0.C0.D0.R1.S11: Rcv En Fine Value = 348
N2.C1.D0.R1.S04: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N4.C1.D0.R0.S00: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N6.C0.D0.R1.S04: PI = 008, PtrOffset = 005
N0.C0.D0.R1.S12: Rcv En Fine Value = 327
N2.C1.D0.R1.S05: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N4.C1.D0.R0.S01: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N6.C0.D0.R1.S05: PI = 027, PtrOffset = 005
N0.C0.D0.R1.S13: Rcv En Fine Value = 315
N2.C1.D0.R1.S06: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N4.C1.D0.R0.S02: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N6.C0.D0.R1.S06: PI = 062, PtrOffset = 005
N0.C0.D0.R1.S14: Rcv En Fine Value = 339
N2.C1.D0.R1.S07: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N4.C1.D0.R0.S03: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N6.C0.D0.R1.S07: PI = 020, PtrOffset = 004
N0.C0.D0.R1.S15: Rcv En Fine Value = 375
N2.C1.D0.R1.S08: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N4.C1.D0.R0.S04: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N6.C0.D0.R1.S08: PI = 003, PtrOffset = 005
N0.C0.D0.R1.S16: Rcv En Fine Value = 269
N2.C1.D0.R1.S00: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N4.C1.D0.R0.S05: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N6.C0.D0.R1.S00: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N0.C0.D0.R1.S17: Rcv En Fine Value = 313
N2.C1.D0.R1.S01: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N4.C1.D0.R0.S06: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N6.C0.D0.R1.S01: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N0.C0.D0.R1: Starting preamble search lower nibbles
N2.C1.D0.R1.S02: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N4.C1.D0.R0.S07: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N6.C0.D0.R1.S02: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N0.C0.D0.R1.S00: PI = 013, PtrOffset = 004
N2.C1.D0.R1.S03: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N4.C1.D0.R0.S08: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N6.C0.D0.R1.S03: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N0.C0.D0.R1.S01: PI = 057, PtrOffset = 005
N2.C1.D0.R1.S04: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N4.C1.D0.R0.S00: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N6.C0.D0.R1.S04: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N0.C0.D0.R1.S02: PI = 027, PtrOffset = 005
N2.C1.D0.R1.S05: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N4.C1.D0.R0.S01: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N6.C0.D0.R1.S05: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N0.C0.D0.R1.S03: PI = 008, PtrOffset = 005
N2.C1.D0.R1.S06: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N4.C1.D0.R0.S02: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N6.C0.D0.R1.S06: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N0.C0.D0.R1.S04: PI = 063, PtrOffset = 004
N2.C1.D0.R1.S07: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N4.C1.D0.R0.S03: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N6.C0.D0.R1.S07: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N0.C0.D0.R1.S05: PI = 020, PtrOffset = 005
N2.C1.D0.R1.S08: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N4.C1.D0.R0.S04: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N6.C0.D0.R1.S08: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N0.C0.D0.R1.S06: PI = 059, PtrOffset = 005
N2.C1.D0.R1.S00: Preamble found at Latency = 008
N4.C1.D0.R0.S05: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N6.C0.D0.R1.S00: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N0.C0.D0.R1.S07: PI = 012, PtrOffset = 004
N2.C1.D0.R1.S01: Preamble found at Latency = 008
N4.C1.D0.R0.S06: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N6.C0.D0.R1.S01: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N0.C0.D0.R1.S08: PI = 059, PtrOffset = 004
N2.C1.D0.R1.S02: Preamble found at Latency = 008
N4.C1.D0.R0.S07: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N6.C0.D0.R1.S02: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N0.C0.D0.R1.S00: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N2.C1.D0.R1.S05: Preamble found at Latency = 008
N4.C1.D0.R0.S08: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N6.C0.D0.R1.S03: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N0.C0.D0.R1.S01: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N2.C1.D0.R1.S06: Preamble found at Latency = 008
N4.C1.D0.R0.S00: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N6.C0.D0.R1.S04: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N0.C0.D0.R1.S02: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N2.C1.D0.R1.S07: Preamble found at Latency = 008
N4.C1.D0.R0.S01: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N6.C0.D0.R1.S05: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N0.C0.D0.R1.S03: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N2.C1.D0.R1.S00: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N4.C1.D0.R0.S02: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N6.C0.D0.R1.S06: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N0.C0.D0.R1.S04: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N2.C1.D0.R1.S01: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N4.C1.D0.R0.S03: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N6.C0.D0.R1.S07: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N0.C0.D0.R1.S05: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N2.C1.D0.R1.S02: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N4.C1.D0.R0.S04: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N6.C0.D0.R1.S08: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N0.C0.D0.R1.S06: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N2.C1.D0.R1.S03: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N4.C1.D0.R0.S05: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N6.C0.D0.R1.S00: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N0.C0.D0.R1.S07: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N2.C1.D0.R1.S04: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N4.C1.D0.R0.S06: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N6.C0.D0.R1.S01: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N0.C0.D0.R1.S08: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N2.C1.D0.R1.S05: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N4.C1.D0.R0.S07: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N6.C0.D0.R1.S02: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N0.C0.D0.R1.S00: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N2.C1.D0.R1.S06: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N4.C1.D0.R0.S08: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N6.C0.D0.R1.S03: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N0.C0.D0.R1.S01: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N2.C1.D0.R1.S07: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N4.C1.D0.R0.S00: Preamble found at Latency = 008
N6.C0.D0.R1.S04: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N0.C0.D0.R1.S02: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N2.C1.D0.R1.S08: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N4.C1.D0.R0.S01: Preamble found at Latency = 008
N6.C0.D0.R1.S05: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N0.C0.D0.R1.S03: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N2.C1.D0.R1.S03: Preamble found at Latency = 007
N4.C1.D0.R0.S02: Preamble found at Latency = 008
N6.C0.D0.R1.S06: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N0.C0.D0.R1.S04: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N2.C1.D0.R1.S04: Preamble found at Latency = 007
N4.C1.D0.R0.S05: Preamble found at Latency = 008
N6.C0.D0.R1.S07: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N0.C0.D0.R1.S05: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N2.C1.D0.R1.S08: Preamble found at Latency = 007
N4.C1.D0.R0.S06: Preamble found at Latency = 008
N6.C0.D0.R1.S08: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N0.C0.D0.R1.S06: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N2.C1.D0.R1.S00: Total Receive Enable Delay = 1377
N4.C1.D0.R0.S07: Preamble found at Latency = 008
N6.C0.D0.R1.S00: Preamble found at Latency = 008
N0.C0.D0.R1.S07: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N2.C1.D0.R1.S01: Total Receive Enable Delay = 1358
N4.C1.D0.R0.S00: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N6.C0.D0.R1.S07: Preamble found at Latency = 008
N0.C0.D0.R1.S08: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N2.C1.D0.R1.S02: Total Receive Enable Delay = 1327
N4.C1.D0.R0.S01: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N6.C0.D0.R1.S00: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N0.C0.D0.R1.S00: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N2.C1.D0.R1.S03: Total Receive Enable Delay = 1306
N4.C1.D0.R0.S02: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N6.C0.D0.R1.S01: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N0.C0.D0.R1.S01: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N2.C1.D0.R1.S04: Total Receive Enable Delay = 1301
N4.C1.D0.R0.S03: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N6.C0.D0.R1.S02: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N0.C0.D0.R1.S02: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N2.C1.D0.R1.S05: Total Receive Enable Delay = 1324
N4.C1.D0.R0.S04: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N6.C0.D0.R1.S03: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N0.C0.D0.R1.S03: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N2.C1.D0.R1.S06: Total Receive Enable Delay = 1349
N4.C1.D0.R0.S05: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N6.C0.D0.R1.S04: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N0.C0.D0.R1.S04: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N2.C1.D0.R1.S07: Total Receive Enable Delay = 1370
N4.C1.D0.R0.S06: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N6.C0.D0.R1.S05: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N0.C0.D0.R1.S05: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N2.C1.D0.R1.S08: Total Receive Enable Delay = 1288
N4.C1.D0.R0.S07: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N6.C0.D0.R1.S06: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N0.C0.D0.R1.S06: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N2.C1.D0.R1: Starting preamble search upper nibbles
N4.C1.D0.R0.S08: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N6.C0.D0.R1.S07: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N0.C0.D0.R1.S07: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N2.C1.D0.R1.S09: PI = 001, PtrOffset = 005
N4.C1.D0.R0.S03: Preamble found at Latency = 007
N6.C0.D0.R1.S08: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N0.C0.D0.R1.S08: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N2.C1.D0.R1.S10: PI = 046, PtrOffset = 004
N4.C1.D0.R0.S04: Preamble found at Latency = 007
N6.C0.D0.R1.S01: Preamble found at Latency = 007
N0.C0.D0.R1.S00: Preamble found at Latency = 008
N2.C1.D0.R1.S11: PI = 015, PtrOffset = 004
N4.C1.D0.R0.S08: Preamble found at Latency = 007
N6.C0.D0.R1.S02: Preamble found at Latency = 007
N0.C0.D0.R1.S07: Preamble found at Latency = 008
N2.C1.D0.R1.S12: PI = 061, PtrOffset = 005
N4.C1.D0.R0.S00: Total Receive Enable Delay = 1373
N6.C0.D0.R1.S03: Preamble found at Latency = 007
N0.C0.D0.R1.S00: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N2.C1.D0.R1.S13: PI = 051, PtrOffset = 005
N4.C1.D0.R0.S01: Total Receive Enable Delay = 1352
N6.C0.D0.R1.S04: Preamble found at Latency = 007
N0.C0.D0.R1.S01: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N2.C1.D0.R1.S14: PI = 012, PtrOffset = 004
N4.C1.D0.R0.S02: Total Receive Enable Delay = 1322
N6.C0.D0.R1.S05: Preamble found at Latency = 007
N0.C0.D0.R1.S02: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N2.C1.D0.R1.S15: PI = 040, PtrOffset = 004
N4.C1.D0.R0.S03: Total Receive Enable Delay = 1304
N6.C0.D0.R1.S06: Preamble found at Latency = 007
N0.C0.D0.R1.S03: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N2.C1.D0.R1.S16: PI = 060, PtrOffset = 004
N4.C1.D0.R0.S04: Total Receive Enable Delay = 1297
N6.C0.D0.R1.S08: Preamble found at Latency = 007
N0.C0.D0.R1.S04: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N2.C1.D0.R1.S17: PI = 040, PtrOffset = 005
N4.C1.D0.R0.S05: Total Receive Enable Delay = 1321
N6.C0.D0.R1.S00: Total Receive Enable Delay = 1332
N0.C0.D0.R1.S05: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N2.C1.D0.R1.S09: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N4.C1.D0.R0.S06: Total Receive Enable Delay = 1343
N6.C0.D0.R1.S01: Total Receive Enable Delay = 1311
N0.C0.D0.R1.S06: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N2.C1.D0.R1.S10: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N4.C1.D0.R0.S07: Total Receive Enable Delay = 1363
N6.C0.D0.R1.S02: Total Receive Enable Delay = 1281
N0.C0.D0.R1.S07: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N2.C1.D0.R1.S11: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N4.C1.D0.R0.S08: Total Receive Enable Delay = 1283
N6.C0.D0.R1.S03: Total Receive Enable Delay = 1262
N0.C0.D0.R1.S08: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N2.C1.D0.R1.S12: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N4.C1.D0.R0: Starting preamble search upper nibbles
N6.C0.D0.R1.S04: Total Receive Enable Delay = 1256
N0.C0.D0.R1.S01: Preamble found at Latency = 007
N2.C1.D0.R1.S13: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N4.C1.D0.R0.S09: PI = 061, PtrOffset = 004
N6.C0.D0.R1.S05: Total Receive Enable Delay = 1275
N0.C0.D0.R1.S02: Preamble found at Latency = 007
N2.C1.D0.R1.S14: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N4.C1.D0.R0.S10: PI = 042, PtrOffset = 004
N6.C0.D0.R1.S06: Total Receive Enable Delay = 1310
N0.C0.D0.R1.S03: Preamble found at Latency = 007
N2.C1.D0.R1.S15: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N4.C1.D0.R0.S11: PI = 011, PtrOffset = 004
N6.C0.D0.R1.S07: Total Receive Enable Delay = 1332
N0.C0.D0.R1.S04: Preamble found at Latency = 007
N2.C1.D0.R1.S16: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N4.C1.D0.R0.S12: PI = 057, PtrOffset = 005
N6.C0.D0.R1.S08: Total Receive Enable Delay = 1251
N0.C0.D0.R1.S05: Preamble found at Latency = 007
N2.C1.D0.R1.S17: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N4.C1.D0.R0.S13: PI = 049, PtrOffset = 005
N6.C0.D0.R1: Starting preamble search upper nibbles
N0.C0.D0.R1.S06: Preamble found at Latency = 007
N2.C1.D0.R1.S09: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N4.C1.D0.R0.S14: PI = 008, PtrOffset = 004
N6.C0.D0.R1.S09: PI = 017, PtrOffset = 004
N0.C0.D0.R1.S08: Preamble found at Latency = 007
N2.C1.D0.R1.S10: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N4.C1.D0.R0.S15: PI = 033, PtrOffset = 004
N6.C0.D0.R1.S10: PI = 001, PtrOffset = 004
N0.C0.D0.R1.S00: Total Receive Enable Delay = 1325
N2.C1.D0.R1.S11: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N4.C1.D0.R0.S16: PI = 053, PtrOffset = 004
N6.C0.D0.R1.S11: PI = 033, PtrOffset = 005
N0.C0.D0.R1.S01: Total Receive Enable Delay = 1305
N2.C1.D0.R1.S12: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N4.C1.D0.R0.S17: PI = 035, PtrOffset = 005
N6.C0.D0.R1.S12: PI = 012, PtrOffset = 005
N0.C0.D0.R1.S02: Total Receive Enable Delay = 1275
N2.C1.D0.R1.S13: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N4.C1.D0.R0.S09: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N6.C0.D0.R1.S13: PI = 006, PtrOffset = 005
N0.C0.D0.R1.S03: Total Receive Enable Delay = 1256
N2.C1.D0.R1.S14: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N4.C1.D0.R0.S10: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N6.C0.D0.R1.S14: PI = 028, PtrOffset = 005
N0.C0.D0.R1.S04: Total Receive Enable Delay = 1247
N2.C1.D0.R1.S15: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N4.C1.D0.R0.S11: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N6.C0.D0.R1.S15: PI = 062, PtrOffset = 005
N0.C0.D0.R1.S05: Total Receive Enable Delay = 1268
N2.C1.D0.R1.S16: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N4.C1.D0.R0.S12: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N6.C0.D0.R1.S16: PI = 018, PtrOffset = 004
N0.C0.D0.R1.S06: Total Receive Enable Delay = 1307
N2.C1.D0.R1.S17: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N4.C1.D0.R0.S13: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N6.C0.D0.R1.S17: PI = 000, PtrOffset = 005
N0.C0.D0.R1.S07: Total Receive Enable Delay = 1324
N2.C1.D0.R1.S09: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N4.C1.D0.R0.S14: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N6.C0.D0.R1.S09: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N0.C0.D0.R1.S08: Total Receive Enable Delay = 1243
N2.C1.D0.R1.S10: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N4.C1.D0.R0.S15: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N6.C0.D0.R1.S10: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N0.C0.D0.R1: Starting preamble search upper nibbles
N2.C1.D0.R1.S11: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N4.C1.D0.R0.S16: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N6.C0.D0.R1.S11: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N0.C0.D0.R1.S09: PI = 009, PtrOffset = 004
N2.C1.D0.R1.S12: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N4.C1.D0.R0.S17: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N6.C0.D0.R1.S12: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N0.C0.D0.R1.S10: PI = 056, PtrOffset = 005
N2.C1.D0.R1.S13: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N4.C1.D0.R0.S09: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N6.C0.D0.R1.S13: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N0.C0.D0.R1.S11: PI = 028, PtrOffset = 005
N2.C1.D0.R1.S14: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N4.C1.D0.R0.S10: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N6.C0.D0.R1.S14: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N0.C0.D0.R1.S12: PI = 007, PtrOffset = 005
N2.C1.D0.R1.S15: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N4.C1.D0.R0.S11: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N6.C0.D0.R1.S15: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N0.C0.D0.R1.S13: PI = 059, PtrOffset = 004
N2.C1.D0.R1.S16: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N4.C1.D0.R0.S12: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N6.C0.D0.R1.S16: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N0.C0.D0.R1.S14: PI = 019, PtrOffset = 005
N2.C1.D0.R1.S17: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N4.C1.D0.R0.S13: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N6.C0.D0.R1.S17: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N0.C0.D0.R1.S15: PI = 055, PtrOffset = 005
N2.C1.D0.R1.S09: Preamble found at Latency = 008
N4.C1.D0.R0.S14: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N6.C0.D0.R1.S09: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N0.C0.D0.R1.S16: PI = 013, PtrOffset = 004
N2.C1.D0.R1.S10: Preamble found at Latency = 008
N4.C1.D0.R0.S15: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N6.C0.D0.R1.S10: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N0.C0.D0.R1.S17: PI = 057, PtrOffset = 004
N2.C1.D0.R1.S11: Preamble found at Latency = 008
N4.C1.D0.R0.S16: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N6.C0.D0.R1.S11: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N0.C0.D0.R1.S09: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N2.C1.D0.R1.S14: Preamble found at Latency = 008
N4.C1.D0.R0.S17: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N6.C0.D0.R1.S12: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N0.C0.D0.R1.S10: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N2.C1.D0.R1.S15: Preamble found at Latency = 008
N4.C1.D0.R0.S09: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N6.C0.D0.R1.S13: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N0.C0.D0.R1.S11: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N2.C1.D0.R1.S16: Preamble found at Latency = 008
N4.C1.D0.R0.S10: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N6.C0.D0.R1.S14: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N0.C0.D0.R1.S12: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N2.C1.D0.R1.S09: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N4.C1.D0.R0.S11: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N6.C0.D0.R1.S15: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N0.C0.D0.R1.S13: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N2.C1.D0.R1.S10: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N4.C1.D0.R0.S12: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N6.C0.D0.R1.S16: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N0.C0.D0.R1.S14: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N2.C1.D0.R1.S11: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N4.C1.D0.R0.S13: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N6.C0.D0.R1.S17: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N0.C0.D0.R1.S15: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N2.C1.D0.R1.S12: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N4.C1.D0.R0.S14: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N6.C0.D0.R1.S09: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N0.C0.D0.R1.S16: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N2.C1.D0.R1.S13: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N4.C1.D0.R0.S15: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N6.C0.D0.R1.S10: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N0.C0.D0.R1.S17: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N2.C1.D0.R1.S14: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N4.C1.D0.R0.S16: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N6.C0.D0.R1.S11: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N0.C0.D0.R1.S09: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N2.C1.D0.R1.S15: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N4.C1.D0.R0.S17: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N6.C0.D0.R1.S12: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N0.C0.D0.R1.S10: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N2.C1.D0.R1.S16: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N4.C1.D0.R0.S09: Preamble found at Latency = 008
N6.C0.D0.R1.S13: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N0.C0.D0.R1.S11: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N2.C1.D0.R1.S17: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N4.C1.D0.R0.S10: Preamble found at Latency = 008
N6.C0.D0.R1.S14: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N0.C0.D0.R1.S12: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N2.C1.D0.R1.S12: Preamble found at Latency = 007
N4.C1.D0.R0.S11: Preamble found at Latency = 008
N6.C0.D0.R1.S15: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N0.C0.D0.R1.S13: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N2.C1.D0.R1.S13: Preamble found at Latency = 007
N4.C1.D0.R0.S14: Preamble found at Latency = 008
N6.C0.D0.R1.S16: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N0.C0.D0.R1.S14: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N2.C1.D0.R1.S17: Preamble found at Latency = 007
N4.C1.D0.R0.S15: Preamble found at Latency = 008
N6.C0.D0.R1.S17: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N0.C0.D0.R1.S15: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N2.C1.D0.R1: Preamble found for all upper nibbles, adjusting Pi, Offset to center into preamble
N4.C1.D0.R0.S16: Preamble found at Latency = 008
N6.C0.D0.R1.S09: Preamble found at Latency = 008
N0.C0.D0.R1.S16: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N2.C1.D0.R1.S09: Total Receive Enable Delay = 1377
N4.C1.D0.R0.S09: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N6.C0.D0.R1.S10: Preamble found at Latency = 008
N0.C0.D0.R1.S17: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N2.C1.D0.R1.S10: Total Receive Enable Delay = 1358
N4.C1.D0.R0.S10: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N6.C0.D0.R1.S16: Preamble found at Latency = 008
N0.C0.D0.R1.S09: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N2.C1.D0.R1.S11: Total Receive Enable Delay = 1327
N4.C1.D0.R0.S11: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N6.C0.D0.R1.S09: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N0.C0.D0.R1.S10: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N2.C1.D0.R1.S12: Total Receive Enable Delay = 1309
N4.C1.D0.R0.S12: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N6.C0.D0.R1.S10: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N0.C0.D0.R1.S11: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N2.C1.D0.R1.S13: Total Receive Enable Delay = 1299
N4.C1.D0.R0.S13: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N6.C0.D0.R1.S11: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N0.C0.D0.R1.S12: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N2.C1.D0.R1.S14: Total Receive Enable Delay = 1324
N4.C1.D0.R0.S14: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N6.C0.D0.R1.S12: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N0.C0.D0.R1.S13: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N2.C1.D0.R1.S15: Total Receive Enable Delay = 1352
N4.C1.D0.R0.S15: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N6.C0.D0.R1.S13: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N0.C0.D0.R1.S14: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N2.C1.D0.R1.S16: Total Receive Enable Delay = 1372
N4.C1.D0.R0.S16: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N6.C0.D0.R1.S14: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N0.C0.D0.R1.S15: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N2.C1.D0.R1.S17: Total Receive Enable Delay = 1288
N4.C1.D0.R0.S17: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N6.C0.D0.R1.S15: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N0.C0.D0.R1.S16: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N2.C1.D1.R0: RcvEnFine: Initial RdCmd2RcvEnLatency = 10, Initial RdPtrOffsetRcvEn = 4
N4.C1.D0.R0.S12: Preamble found at Latency = 007
N6.C0.D0.R1.S16: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N0.C0.D0.R1.S17: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N2.C1.D1.R0.S00: Rcv En Fine Value = 304
N4.C1.D0.R0.S13: Preamble found at Latency = 007
N6.C0.D0.R1.S17: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N0.C0.D0.R1.S09: Preamble found at Latency = 008
N2.C1.D1.R0.S01: Rcv En Fine Value = 286
N4.C1.D0.R0.S17: Preamble found at Latency = 007
N6.C0.D0.R1.S11: Preamble found at Latency = 007
N0.C0.D0.R1.S16: Preamble found at Latency = 008
N2.C1.D1.R0.S02: Rcv En Fine Value = 257
N4.C1.D0.R0: Preamble found for all upper nibbles, adjusting Pi, Offset to center into preamble
N6.C0.D0.R1.S12: Preamble found at Latency = 007
N0.C0.D0.R1.S09: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N2.C1.D1.R0.S03: Rcv En Fine Value = 363
N4.C1.D0.R0.S09: Total Receive Enable Delay = 1373
N6.C0.D0.R1.S13: Preamble found at Latency = 007
N0.C0.D0.R1.S10: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N2.C1.D1.R0.S04: Rcv En Fine Value = 355
N4.C1.D0.R0.S10: Total Receive Enable Delay = 1354
N6.C0.D0.R1.S14: Preamble found at Latency = 007
N0.C0.D0.R1.S11: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N2.C1.D1.R0.S05: Rcv En Fine Value = 256
N4.C1.D0.R0.S11: Total Receive Enable Delay = 1323
N6.C0.D0.R1.S15: Preamble found at Latency = 007
N0.C0.D0.R1.S12: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N2.C1.D1.R0.S06: Rcv En Fine Value = 278
N4.C1.D0.R0.S12: Total Receive Enable Delay = 1305
N6.C0.D0.R1.S17: Preamble found at Latency = 007
N0.C0.D0.R1.S13: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N2.C1.D1.R0.S07: Rcv En Fine Value = 299
N4.C1.D0.R0.S13: Total Receive Enable Delay = 1297
N6.C0.D0.R1: Preamble found for all upper nibbles, adjusting Pi, Offset to center into preamble
N0.C0.D0.R1.S14: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N2.C1.D1.R0.S08: Rcv En Fine Value = 345
N4.C1.D0.R0.S14: Total Receive Enable Delay = 1320
N6.C0.D0.R1.S09: Total Receive Enable Delay = 1329
N0.C0.D0.R1.S15: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N2.C1.D1.R0.S09: Rcv En Fine Value = 308
N4.C1.D0.R0.S15: Total Receive Enable Delay = 1345
N6.C0.D0.R1.S10: Total Receive Enable Delay = 1313
N0.C0.D0.R1.S16: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N2.C1.D1.R0.S10: Rcv En Fine Value = 286
N4.C1.D0.R0.S16: Total Receive Enable Delay = 1365
N6.C0.D0.R1.S11: Total Receive Enable Delay = 1281
N0.C0.D0.R1.S17: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N2.C1.D1.R0.S11: Rcv En Fine Value = 256
N4.C1.D0.R0.S17: Total Receive Enable Delay = 1283
N6.C0.D0.R1.S12: Total Receive Enable Delay = 1260
N0.C0.D0.R1.S10: Preamble found at Latency = 007
N2.C1.D1.R0.S12: Rcv En Fine Value = 366
N4.C1.D0.R1: RcvEnFine: Initial RdCmd2RcvEnLatency = 10, Initial RdPtrOffsetRcvEn = 4
N6.C0.D0.R1.S13: Total Receive Enable Delay = 1254
N0.C0.D0.R1.S11: Preamble found at Latency = 007
N2.C1.D1.R0.S13: Rcv En Fine Value = 357
N4.C1.D0.R1.S00: Rcv En Fine Value = 318
N6.C0.D0.R1.S14: Total Receive Enable Delay = 1276
N0.C0.D0.R1.S12: Preamble found at Latency = 007
N2.C1.D1.R0.S14: Rcv En Fine Value = 382
N4.C1.D0.R1.S01: Rcv En Fine Value = 294
N6.C0.D0.R1.S15: Total Receive Enable Delay = 1310
N0.C0.D0.R1.S13: Preamble found at Latency = 007
N2.C1.D1.R0.S15: Rcv En Fine Value = 280
N4.C1.D0.R1.S02: Rcv En Fine Value = 266
N6.C0.D0.R1.S16: Total Receive Enable Delay = 1330
N0.C0.D0.R1.S14: Preamble found at Latency = 007
N2.C1.D1.R0.S16: Rcv En Fine Value = 301
N4.C1.D0.R1.S03: Rcv En Fine Value = 372
N6.C0.D0.R1.S17: Total Receive Enable Delay = 1248
N0.C0.D0.R1.S15: Preamble found at Latency = 007
N2.C1.D1.R0.S17: Rcv En Fine Value = 345
N4.C1.D0.R1.S04: Rcv En Fine Value = 369
N6.C0.D1.R0: RcvEnFine: Initial RdCmd2RcvEnLatency = 10, Initial RdPtrOffsetRcvEn = 4
N0.C0.D0.R1.S17: Preamble found at Latency = 007
N2.C1.D1.R0: Starting preamble search lower nibbles
N4.C1.D0.R1.S05: Rcv En Fine Value = 264
N6.C0.D1.R0.S00: Rcv En Fine Value = 257
N0.C0.D0.R1: Preamble found for all upper nibbles, adjusting Pi, Offset to center into preamble
N2.C1.D1.R0.S00: PI = 048, PtrOffset = 004
N4.C1.D0.R1.S06: Rcv En Fine Value = 289
N6.C0.D1.R0.S01: Rcv En Fine Value = 366
N0.C0.D0.R1.S09: Total Receive Enable Delay = 1321
N2.C1.D1.R0.S01: PI = 030, PtrOffset = 004
N4.C1.D0.R1.S07: Rcv En Fine Value = 308
N6.C0.D1.R0.S02: Rcv En Fine Value = 337
N0.C0.D0.R1.S10: Total Receive Enable Delay = 1304
N2.C1.D1.R0.S02: PI = 001, PtrOffset = 004
N4.C1.D0.R1.S08: Rcv En Fine Value = 356
N6.C0.D1.R0.S03: Rcv En Fine Value = 316
N0.C0.D0.R1.S11: Total Receive Enable Delay = 1276
N2.C1.D1.R0.S03: PI = 043, PtrOffset = 005
N4.C1.D0.R1.S09: Rcv En Fine Value = 318
N6.C0.D1.R0.S04: Rcv En Fine Value = 311
N0.C0.D0.R1.S12: Total Receive Enable Delay = 1255
N2.C1.D1.R0.S04: PI = 035, PtrOffset = 005
N4.C1.D0.R1.S10: Rcv En Fine Value = 297
N6.C0.D1.R0.S05: Rcv En Fine Value = 332
N0.C0.D0.R1.S13: Total Receive Enable Delay = 1243
N2.C1.D1.R0.S05: PI = 000, PtrOffset = 004
N4.C1.D0.R1.S11: Rcv En Fine Value = 268
N6.C0.D1.R0.S06: Rcv En Fine Value = 365
N0.C0.D0.R1.S14: Total Receive Enable Delay = 1267
N2.C1.D1.R0.S06: PI = 022, PtrOffset = 004
N4.C1.D0.R1.S12: Rcv En Fine Value = 376
N6.C0.D1.R0.S07: Rcv En Fine Value = 260
N0.C0.D0.R1.S15: Total Receive Enable Delay = 1303
N2.C1.D1.R0.S07: PI = 043, PtrOffset = 004
N4.C1.D0.R1.S13: Rcv En Fine Value = 368
N6.C0.D1.R0.S08: Rcv En Fine Value = 306
N0.C0.D0.R1.S16: Total Receive Enable Delay = 1325
N2.C1.D1.R0.S08: PI = 025, PtrOffset = 005
N4.C1.D0.R1.S14: Rcv En Fine Value = 265
N6.C0.D1.R0.S09: Rcv En Fine Value = 258
N0.C0.D0.R1.S17: Total Receive Enable Delay = 1241
N2.C1.D1.R0.S00: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N4.C1.D0.R1.S15: Rcv En Fine Value = 291
N6.C0.D1.R0.S10: Rcv En Fine Value = 364
N0.C0.D1.R0: RcvEnFine: Initial RdCmd2RcvEnLatency = 10, Initial RdPtrOffsetRcvEn = 4
N2.C1.D1.R0.S01: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N4.C1.D0.R1.S16: Rcv En Fine Value = 308
N6.C0.D1.R0.S11: Rcv En Fine Value = 337
N0.C0.D1.R0.S00: Rcv En Fine Value = 380
N2.C1.D1.R0.S02: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N4.C1.D0.R1.S17: Rcv En Fine Value = 356
N6.C0.D1.R0.S12: Rcv En Fine Value = 317
N0.C0.D1.R0.S01: Rcv En Fine Value = 357
N2.C1.D1.R0.S03: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N4.C1.D0.R1: Starting preamble search lower nibbles
N6.C0.D1.R0.S13: Rcv En Fine Value = 310
N0.C0.D1.R0.S02: Rcv En Fine Value = 331
N2.C1.D1.R0.S04: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N4.C1.D0.R1.S00: PI = 062, PtrOffset = 004
N6.C0.D1.R0.S14: Rcv En Fine Value = 331
N0.C0.D1.R0.S03: Rcv En Fine Value = 308
N2.C1.D1.R0.S05: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N4.C1.D0.R1.S01: PI = 038, PtrOffset = 004
N6.C0.D1.R0.S15: Rcv En Fine Value = 361
N0.C0.D1.R0.S04: Rcv En Fine Value = 304
N2.C1.D1.R0.S06: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N4.C1.D0.R1.S02: PI = 010, PtrOffset = 004
N6.C0.D1.R0.S16: Rcv En Fine Value = 257
N0.C0.D1.R0.S05: Rcv En Fine Value = 324
N2.C1.D1.R0.S07: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N4.C1.D0.R1.S03: PI = 052, PtrOffset = 005
N6.C0.D1.R0.S17: Rcv En Fine Value = 303
N0.C0.D1.R0.S06: Rcv En Fine Value = 361
N2.C1.D1.R0.S08: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N4.C1.D0.R1.S04: PI = 049, PtrOffset = 005
N6.C0.D1.R0: Starting preamble search lower nibbles
N0.C0.D1.R0.S07: Rcv En Fine Value = 383
N2.C1.D1.R0.S00: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N4.C1.D0.R1.S05: PI = 008, PtrOffset = 004
N6.C0.D1.R0.S00: PI = 001, PtrOffset = 004
N0.C0.D1.R0.S08: Rcv En Fine Value = 297
N2.C1.D1.R0.S01: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N4.C1.D0.R1.S06: PI = 033, PtrOffset = 004
N6.C0.D1.R0.S01: PI = 046, PtrOffset = 005
N0.C0.D1.R0.S09: Rcv En Fine Value = 378
N2.C1.D1.R0.S02: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N4.C1.D0.R1.S07: PI = 052, PtrOffset = 004
N6.C0.D1.R0.S02: PI = 017, PtrOffset = 005
N0.C0.D1.R0.S10: Rcv En Fine Value = 355
N2.C1.D1.R0.S03: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N4.C1.D0.R1.S08: PI = 036, PtrOffset = 005
N6.C0.D1.R0.S03: PI = 060, PtrOffset = 004
N0.C0.D1.R0.S11: Rcv En Fine Value = 328
N2.C1.D1.R0.S04: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N4.C1.D0.R1.S00: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N6.C0.D1.R0.S04: PI = 055, PtrOffset = 004
N0.C0.D1.R0.S12: Rcv En Fine Value = 311
N2.C1.D1.R0.S05: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N4.C1.D0.R1.S01: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N6.C0.D1.R0.S05: PI = 012, PtrOffset = 005
N0.C0.D1.R0.S13: Rcv En Fine Value = 303
N2.C1.D1.R0.S06: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N4.C1.D0.R1.S02: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N6.C0.D1.R0.S06: PI = 045, PtrOffset = 005
N0.C0.D1.R0.S14: Rcv En Fine Value = 325
N2.C1.D1.R0.S07: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N4.C1.D0.R1.S03: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N6.C0.D1.R0.S07: PI = 004, PtrOffset = 004
N0.C0.D1.R0.S15: Rcv En Fine Value = 359
N2.C1.D1.R0.S08: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N4.C1.D0.R1.S04: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N6.C0.D1.R0.S08: PI = 050, PtrOffset = 004
N0.C0.D1.R0.S16: Rcv En Fine Value = 380
N2.C1.D1.R0.S00: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N4.C1.D0.R1.S05: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N6.C0.D1.R0.S00: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N0.C0.D1.R0.S17: Rcv En Fine Value = 293
N2.C1.D1.R0.S01: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N4.C1.D0.R1.S06: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N6.C0.D1.R0.S01: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N0.C0.D1.R0: Starting preamble search lower nibbles
N2.C1.D1.R0.S02: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N4.C1.D0.R1.S07: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N6.C0.D1.R0.S02: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N0.C0.D1.R0.S00: PI = 060, PtrOffset = 005
N2.C1.D1.R0.S03: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N4.C1.D0.R1.S08: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N6.C0.D1.R0.S03: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N0.C0.D1.R0.S01: PI = 037, PtrOffset = 005
N2.C1.D1.R0.S04: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N4.C1.D0.R1.S00: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N6.C0.D1.R0.S04: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N0.C0.D1.R0.S02: PI = 011, PtrOffset = 005
N2.C1.D1.R0.S05: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N4.C1.D0.R1.S01: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N6.C0.D1.R0.S05: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N0.C0.D1.R0.S03: PI = 052, PtrOffset = 004
N2.C1.D1.R0.S06: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N4.C1.D0.R1.S02: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N6.C0.D1.R0.S06: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N0.C0.D1.R0.S04: PI = 048, PtrOffset = 004
N2.C1.D1.R0.S07: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N4.C1.D0.R1.S03: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N6.C0.D1.R0.S07: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N0.C0.D1.R0.S05: PI = 004, PtrOffset = 005
N2.C1.D1.R0.S08: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N4.C1.D0.R1.S04: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N6.C0.D1.R0.S08: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N0.C0.D1.R0.S06: PI = 041, PtrOffset = 005
N2.C1.D1.R0.S00: Preamble found at Latency = 008
N4.C1.D0.R1.S05: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N6.C0.D1.R0.S00: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N0.C0.D1.R0.S07: PI = 063, PtrOffset = 005
N2.C1.D1.R0.S01: Preamble found at Latency = 008
N4.C1.D0.R1.S06: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N6.C0.D1.R0.S01: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N0.C0.D1.R0.S08: PI = 041, PtrOffset = 004
N2.C1.D1.R0.S02: Preamble found at Latency = 008
N4.C1.D0.R1.S07: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N6.C0.D1.R0.S02: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N0.C0.D1.R0.S00: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N2.C1.D1.R0.S05: Preamble found at Latency = 008
N4.C1.D0.R1.S08: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N6.C0.D1.R0.S03: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N0.C0.D1.R0.S01: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N2.C1.D1.R0.S06: Preamble found at Latency = 008
N4.C1.D0.R1.S00: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N6.C0.D1.R0.S04: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N0.C0.D1.R0.S02: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N2.C1.D1.R0.S07: Preamble found at Latency = 008
N4.C1.D0.R1.S01: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N6.C0.D1.R0.S05: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N0.C0.D1.R0.S03: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N2.C1.D1.R0.S00: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N4.C1.D0.R1.S02: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N6.C0.D1.R0.S06: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N0.C0.D1.R0.S04: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N2.C1.D1.R0.S01: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N4.C1.D0.R1.S03: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N6.C0.D1.R0.S07: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N0.C0.D1.R0.S05: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N2.C1.D1.R0.S02: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N4.C1.D0.R1.S04: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N6.C0.D1.R0.S08: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N0.C0.D1.R0.S06: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N2.C1.D1.R0.S03: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N4.C1.D0.R1.S05: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N6.C0.D1.R0.S00: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N0.C0.D1.R0.S07: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N2.C1.D1.R0.S04: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N4.C1.D0.R1.S06: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N6.C0.D1.R0.S01: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N0.C0.D1.R0.S08: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N2.C1.D1.R0.S05: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N4.C1.D0.R1.S07: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N6.C0.D1.R0.S02: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N0.C0.D1.R0.S00: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N2.C1.D1.R0.S06: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N4.C1.D0.R1.S08: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N6.C0.D1.R0.S03: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N0.C0.D1.R0.S01: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N2.C1.D1.R0.S07: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N4.C1.D0.R1.S00: Preamble found at Latency = 008
N6.C0.D1.R0.S04: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N0.C0.D1.R0.S02: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N2.C1.D1.R0.S08: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N4.C1.D0.R1.S01: Preamble found at Latency = 008
N6.C0.D1.R0.S05: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N0.C0.D1.R0.S03: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N2.C1.D1.R0.S03: Preamble found at Latency = 007
N4.C1.D0.R1.S02: Preamble found at Latency = 008
N6.C0.D1.R0.S06: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N0.C0.D1.R0.S04: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N2.C1.D1.R0.S04: Preamble found at Latency = 007
N4.C1.D0.R1.S05: Preamble found at Latency = 008
N6.C0.D1.R0.S07: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N0.C0.D1.R0.S05: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N2.C1.D1.R0.S08: Preamble found at Latency = 007
N4.C1.D0.R1.S06: Preamble found at Latency = 008
N6.C0.D1.R0.S08: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N0.C0.D1.R0.S06: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N2.C1.D1.R0.S00: Total Receive Enable Delay = 1360
N4.C1.D0.R1.S07: Preamble found at Latency = 008
N6.C0.D1.R0.S00: Preamble found at Latency = 008
N0.C0.D1.R0.S07: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N2.C1.D1.R0.S01: Total Receive Enable Delay = 1342
N4.C1.D0.R1.S00: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N6.C0.D1.R0.S07: Preamble found at Latency = 008
N0.C0.D1.R0.S08: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N2.C1.D1.R0.S02: Total Receive Enable Delay = 1313
N4.C1.D0.R1.S01: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N6.C0.D1.R0.S00: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N0.C0.D1.R0.S00: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N2.C1.D1.R0.S03: Total Receive Enable Delay = 1291
N4.C1.D0.R1.S02: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N6.C0.D1.R0.S01: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N0.C0.D1.R0.S01: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N2.C1.D1.R0.S04: Total Receive Enable Delay = 1283
N4.C1.D0.R1.S03: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N6.C0.D1.R0.S02: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N0.C0.D1.R0.S02: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N2.C1.D1.R0.S05: Total Receive Enable Delay = 1312
N4.C1.D0.R1.S04: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N6.C0.D1.R0.S03: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N0.C0.D1.R0.S03: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N2.C1.D1.R0.S06: Total Receive Enable Delay = 1334
N4.C1.D0.R1.S05: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N6.C0.D1.R0.S04: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N0.C0.D1.R0.S04: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N2.C1.D1.R0.S07: Total Receive Enable Delay = 1355
N4.C1.D0.R1.S06: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N6.C0.D1.R0.S05: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N0.C0.D1.R0.S05: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N2.C1.D1.R0.S08: Total Receive Enable Delay = 1273
N4.C1.D0.R1.S07: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N6.C0.D1.R0.S06: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N0.C0.D1.R0.S06: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N2.C1.D1.R0: Starting preamble search upper nibbles
N4.C1.D0.R1.S08: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N6.C0.D1.R0.S07: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N0.C0.D1.R0.S07: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N2.C1.D1.R0.S09: PI = 052, PtrOffset = 004
N4.C1.D0.R1.S03: Preamble found at Latency = 007
N6.C0.D1.R0.S08: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N0.C0.D1.R0.S08: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N2.C1.D1.R0.S10: PI = 030, PtrOffset = 004
N4.C1.D0.R1.S04: Preamble found at Latency = 007
N6.C0.D1.R0.S01: Preamble found at Latency = 007
N0.C0.D1.R0.S00: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N2.C1.D1.R0.S11: PI = 000, PtrOffset = 004
N4.C1.D0.R1.S08: Preamble found at Latency = 007
N6.C0.D1.R0.S02: Preamble found at Latency = 007
N0.C0.D1.R0.S01: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N2.C1.D1.R0.S12: PI = 046, PtrOffset = 005
N4.C1.D0.R1.S00: Total Receive Enable Delay = 1374
N6.C0.D1.R0.S03: Preamble found at Latency = 007
N0.C0.D1.R0.S02: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N2.C1.D1.R0.S13: PI = 037, PtrOffset = 005
N4.C1.D0.R1.S01: Total Receive Enable Delay = 1350
N6.C0.D1.R0.S04: Preamble found at Latency = 007
N0.C0.D1.R0.S03: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N2.C1.D1.R0.S14: PI = 062, PtrOffset = 005
N4.C1.D0.R1.S02: Total Receive Enable Delay = 1322
N6.C0.D1.R0.S05: Preamble found at Latency = 007
N0.C0.D1.R0.S04: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N2.C1.D1.R0.S15: PI = 024, PtrOffset = 004
N4.C1.D0.R1.S03: Total Receive Enable Delay = 1300
N6.C0.D1.R0.S06: Preamble found at Latency = 007
N0.C0.D1.R0.S05: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N2.C1.D1.R0.S16: PI = 045, PtrOffset = 004
N4.C1.D0.R1.S04: Total Receive Enable Delay = 1297
N6.C0.D1.R0.S08: Preamble found at Latency = 007
N0.C0.D1.R0.S06: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N2.C1.D1.R0.S17: PI = 025, PtrOffset = 005
N4.C1.D0.R1.S05: Total Receive Enable Delay = 1320
N6.C0.D1.R0.S00: Total Receive Enable Delay = 1313
N0.C0.D1.R0.S07: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N2.C1.D1.R0.S09: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N4.C1.D0.R1.S06: Total Receive Enable Delay = 1345
N6.C0.D1.R0.S01: Total Receive Enable Delay = 1294
N0.C0.D1.R0.S08: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N2.C1.D1.R0.S10: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N4.C1.D0.R1.S07: Total Receive Enable Delay = 1364
N6.C0.D1.R0.S02: Total Receive Enable Delay = 1265
N0.C0.D1.R0.S00: Preamble found at Latency = 007
N2.C1.D1.R0.S11: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N4.C1.D0.R1.S08: Total Receive Enable Delay = 1284
N6.C0.D1.R0.S03: Total Receive Enable Delay = 1244
N0.C0.D1.R0.S01: Preamble found at Latency = 007
N2.C1.D1.R0.S12: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N4.C1.D0.R1: Starting preamble search upper nibbles
N6.C0.D1.R0.S04: Total Receive Enable Delay = 1239
N0.C0.D1.R0.S02: Preamble found at Latency = 007
N2.C1.D1.R0.S13: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N4.C1.D0.R1.S09: PI = 062, PtrOffset = 004
N6.C0.D1.R0.S05: Total Receive Enable Delay = 1260
N0.C0.D1.R0.S03: Preamble found at Latency = 007
N2.C1.D1.R0.S14: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N4.C1.D0.R1.S10: PI = 041, PtrOffset = 004
N6.C0.D1.R0.S06: Total Receive Enable Delay = 1293
N0.C0.D1.R0.S04: Preamble found at Latency = 007
N2.C1.D1.R0.S15: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N4.C1.D0.R1.S11: PI = 012, PtrOffset = 004
N6.C0.D1.R0.S07: Total Receive Enable Delay = 1316
N0.C0.D1.R0.S05: Preamble found at Latency = 007
N2.C1.D1.R0.S16: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N4.C1.D0.R1.S12: PI = 056, PtrOffset = 005
N6.C0.D1.R0.S08: Total Receive Enable Delay = 1234
N0.C0.D1.R0.S06: Preamble found at Latency = 007
N2.C1.D1.R0.S17: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N4.C1.D0.R1.S13: PI = 048, PtrOffset = 005
N6.C0.D1.R0: Starting preamble search upper nibbles
N0.C0.D1.R0.S07: Preamble found at Latency = 007
N2.C1.D1.R0.S09: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N4.C1.D0.R1.S14: PI = 009, PtrOffset = 004
N6.C0.D1.R0.S09: PI = 002, PtrOffset = 004
N0.C0.D1.R0.S08: Preamble found at Latency = 007
N2.C1.D1.R0.S10: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N4.C1.D0.R1.S15: PI = 035, PtrOffset = 004
N6.C0.D1.R0.S10: PI = 044, PtrOffset = 005
N0.C0.D1.R0.S00: Total Receive Enable Delay = 1308
N2.C1.D1.R0.S11: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N4.C1.D0.R1.S16: PI = 052, PtrOffset = 004
N6.C0.D1.R0.S11: PI = 017, PtrOffset = 005
N0.C0.D1.R0.S01: Total Receive Enable Delay = 1285
N2.C1.D1.R0.S12: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N4.C1.D0.R1.S17: PI = 036, PtrOffset = 005
N6.C0.D1.R0.S12: PI = 061, PtrOffset = 004
N0.C0.D1.R0.S02: Total Receive Enable Delay = 1259
N2.C1.D1.R0.S13: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N4.C1.D0.R1.S09: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N6.C0.D1.R0.S13: PI = 054, PtrOffset = 004
N0.C0.D1.R0.S03: Total Receive Enable Delay = 1236
N2.C1.D1.R0.S14: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N4.C1.D0.R1.S10: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N6.C0.D1.R0.S14: PI = 011, PtrOffset = 005
N0.C0.D1.R0.S04: Total Receive Enable Delay = 1232
N2.C1.D1.R0.S15: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N4.C1.D0.R1.S11: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N6.C0.D1.R0.S15: PI = 041, PtrOffset = 005
N0.C0.D1.R0.S05: Total Receive Enable Delay = 1252
N2.C1.D1.R0.S16: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N4.C1.D0.R1.S12: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N6.C0.D1.R0.S16: PI = 001, PtrOffset = 004
N0.C0.D1.R0.S06: Total Receive Enable Delay = 1289
N2.C1.D1.R0.S17: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N4.C1.D0.R1.S13: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N6.C0.D1.R0.S17: PI = 047, PtrOffset = 004
N0.C0.D1.R0.S07: Total Receive Enable Delay = 1311
N2.C1.D1.R0.S09: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N4.C1.D0.R1.S14: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N6.C0.D1.R0.S09: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N0.C0.D1.R0.S08: Total Receive Enable Delay = 1225
N2.C1.D1.R0.S10: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N4.C1.D0.R1.S15: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N6.C0.D1.R0.S10: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N0.C0.D1.R0: Starting preamble search upper nibbles
N2.C1.D1.R0.S11: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N4.C1.D0.R1.S16: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N6.C0.D1.R0.S11: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N0.C0.D1.R0.S09: PI = 058, PtrOffset = 005
N2.C1.D1.R0.S12: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N4.C1.D0.R1.S17: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N6.C0.D1.R0.S12: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N0.C0.D1.R0.S10: PI = 035, PtrOffset = 005
N2.C1.D1.R0.S13: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N4.C1.D0.R1.S09: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N6.C0.D1.R0.S13: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N0.C0.D1.R0.S11: PI = 008, PtrOffset = 005
N2.C1.D1.R0.S14: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N4.C1.D0.R1.S10: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N6.C0.D1.R0.S14: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N0.C0.D1.R0.S12: PI = 055, PtrOffset = 004
N2.C1.D1.R0.S15: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N4.C1.D0.R1.S11: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N6.C0.D1.R0.S15: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N0.C0.D1.R0.S13: PI = 047, PtrOffset = 004
N2.C1.D1.R0.S16: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N4.C1.D0.R1.S12: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N6.C0.D1.R0.S16: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N0.C0.D1.R0.S14: PI = 005, PtrOffset = 005
N2.C1.D1.R0.S17: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N4.C1.D0.R1.S13: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N6.C0.D1.R0.S17: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N0.C0.D1.R0.S15: PI = 039, PtrOffset = 005
N2.C1.D1.R0.S09: Preamble found at Latency = 008
N4.C1.D0.R1.S14: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N6.C0.D1.R0.S09: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N0.C0.D1.R0.S16: PI = 060, PtrOffset = 005
N2.C1.D1.R0.S10: Preamble found at Latency = 008
N4.C1.D0.R1.S15: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N6.C0.D1.R0.S10: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N0.C0.D1.R0.S17: PI = 037, PtrOffset = 004
N2.C1.D1.R0.S11: Preamble found at Latency = 008
N4.C1.D0.R1.S16: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N6.C0.D1.R0.S11: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N0.C0.D1.R0.S09: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N2.C1.D1.R0.S15: Preamble found at Latency = 008
N4.C1.D0.R1.S17: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N6.C0.D1.R0.S12: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N0.C0.D1.R0.S10: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N2.C1.D1.R0.S16: Preamble found at Latency = 008
N4.C1.D0.R1.S09: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N6.C0.D1.R0.S13: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N0.C0.D1.R0.S11: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N2.C1.D1.R0.S09: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N4.C1.D0.R1.S10: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N6.C0.D1.R0.S14: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N0.C0.D1.R0.S12: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N2.C1.D1.R0.S10: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N4.C1.D0.R1.S11: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N6.C0.D1.R0.S15: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N0.C0.D1.R0.S13: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N2.C1.D1.R0.S11: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N4.C1.D0.R1.S12: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N6.C0.D1.R0.S16: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N0.C0.D1.R0.S14: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N2.C1.D1.R0.S12: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N4.C1.D0.R1.S13: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N6.C0.D1.R0.S17: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N0.C0.D1.R0.S15: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N2.C1.D1.R0.S13: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N4.C1.D0.R1.S14: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N6.C0.D1.R0.S09: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N0.C0.D1.R0.S16: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N2.C1.D1.R0.S14: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N4.C1.D0.R1.S15: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N6.C0.D1.R0.S10: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N0.C0.D1.R0.S17: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N2.C1.D1.R0.S15: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N4.C1.D0.R1.S16: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N6.C0.D1.R0.S11: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N0.C0.D1.R0.S09: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N2.C1.D1.R0.S16: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N4.C1.D0.R1.S17: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N6.C0.D1.R0.S12: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N0.C0.D1.R0.S10: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N2.C1.D1.R0.S17: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N4.C1.D0.R1.S09: Preamble found at Latency = 008
N6.C0.D1.R0.S13: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N0.C0.D1.R0.S11: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N2.C1.D1.R0.S12: Preamble found at Latency = 007
N4.C1.D0.R1.S10: Preamble found at Latency = 008
N6.C0.D1.R0.S14: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N0.C0.D1.R0.S12: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N2.C1.D1.R0.S13: Preamble found at Latency = 007
N4.C1.D0.R1.S11: Preamble found at Latency = 008
N6.C0.D1.R0.S15: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N0.C0.D1.R0.S13: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N2.C1.D1.R0.S14: Preamble found at Latency = 007
N4.C1.D0.R1.S14: Preamble found at Latency = 008
N6.C0.D1.R0.S16: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N0.C0.D1.R0.S14: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N2.C1.D1.R0.S17: Preamble found at Latency = 007
N4.C1.D0.R1.S15: Preamble found at Latency = 008
N6.C0.D1.R0.S17: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N0.C0.D1.R0.S15: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N2.C1.D1.R0: Preamble found for all upper nibbles, adjusting Pi, Offset to center into preamble
N4.C1.D0.R1.S16: Preamble found at Latency = 008
N6.C0.D1.R0.S09: Preamble found at Latency = 008
N0.C0.D1.R0.S16: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N2.C1.D1.R0.S09: Total Receive Enable Delay = 1364
N4.C1.D0.R1.S09: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N6.C0.D1.R0.S16: Preamble found at Latency = 008
N0.C0.D1.R0.S17: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N2.C1.D1.R0.S10: Total Receive Enable Delay = 1342
N4.C1.D0.R1.S10: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N6.C0.D1.R0.S09: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N0.C0.D1.R0.S09: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N2.C1.D1.R0.S11: Total Receive Enable Delay = 1312
N4.C1.D0.R1.S11: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N6.C0.D1.R0.S10: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N0.C0.D1.R0.S10: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N2.C1.D1.R0.S12: Total Receive Enable Delay = 1294
N4.C1.D0.R1.S12: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N6.C0.D1.R0.S11: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N0.C0.D1.R0.S11: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N2.C1.D1.R0.S13: Total Receive Enable Delay = 1285
N4.C1.D0.R1.S13: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N6.C0.D1.R0.S12: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N0.C0.D1.R0.S12: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N2.C1.D1.R0.S14: Total Receive Enable Delay = 1310
N4.C1.D0.R1.S14: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N6.C0.D1.R0.S13: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N0.C0.D1.R0.S13: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N2.C1.D1.R0.S15: Total Receive Enable Delay = 1336
N4.C1.D0.R1.S15: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N6.C0.D1.R0.S14: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N0.C0.D1.R0.S14: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N2.C1.D1.R0.S16: Total Receive Enable Delay = 1357
N4.C1.D0.R1.S16: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N6.C0.D1.R0.S15: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N0.C0.D1.R0.S15: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N2.C1.D1.R0.S17: Total Receive Enable Delay = 1273
N4.C1.D0.R1.S17: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N6.C0.D1.R0.S16: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N0.C0.D1.R0.S16: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N2.C1.D1.R1: RcvEnFine: Initial RdCmd2RcvEnLatency = 10, Initial RdPtrOffsetRcvEn = 4
N4.C1.D0.R1.S12: Preamble found at Latency = 007
N6.C0.D1.R0.S17: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N0.C0.D1.R0.S17: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N2.C1.D1.R1.S00: Rcv En Fine Value = 306
N4.C1.D0.R1.S13: Preamble found at Latency = 007
N6.C0.D1.R0.S10: Preamble found at Latency = 007
N0.C0.D1.R0.S09: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N2.C1.D1.R1.S01: Rcv En Fine Value = 285
N4.C1.D0.R1.S17: Preamble found at Latency = 007
N6.C0.D1.R0.S11: Preamble found at Latency = 007
N0.C0.D1.R0.S10: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N2.C1.D1.R1.S02: Rcv En Fine Value = 256
N4.C1.D0.R1: Preamble found for all upper nibbles, adjusting Pi, Offset to center into preamble
N6.C0.D1.R0.S12: Preamble found at Latency = 007
N0.C0.D1.R0.S11: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N2.C1.D1.R1.S03: Rcv En Fine Value = 363
N4.C1.D0.R1.S09: Total Receive Enable Delay = 1374
N6.C0.D1.R0.S13: Preamble found at Latency = 007
N0.C0.D1.R0.S12: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N2.C1.D1.R1.S04: Rcv En Fine Value = 358
N4.C1.D0.R1.S10: Total Receive Enable Delay = 1353
N6.C0.D1.R0.S14: Preamble found at Latency = 007
N0.C0.D1.R0.S13: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N2.C1.D1.R1.S05: Rcv En Fine Value = 383
N4.C1.D0.R1.S11: Total Receive Enable Delay = 1324
N6.C0.D1.R0.S15: Preamble found at Latency = 007
N0.C0.D1.R0.S14: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N2.C1.D1.R1.S06: Rcv En Fine Value = 278
N4.C1.D0.R1.S12: Total Receive Enable Delay = 1304
N6.C0.D1.R0.S17: Preamble found at Latency = 007
N0.C0.D1.R0.S15: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N2.C1.D1.R1.S07: Rcv En Fine Value = 297
N4.C1.D0.R1.S13: Total Receive Enable Delay = 1296
N6.C0.D1.R0: Preamble found for all upper nibbles, adjusting Pi, Offset to center into preamble
N0.C0.D1.R0.S16: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N2.C1.D1.R1.S08: Rcv En Fine Value = 344
N4.C1.D0.R1.S14: Total Receive Enable Delay = 1321
N6.C0.D1.R0.S09: Total Receive Enable Delay = 1314
N0.C0.D1.R0.S17: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N2.C1.D1.R1.S09: Rcv En Fine Value = 306
N4.C1.D0.R1.S15: Total Receive Enable Delay = 1347
N6.C0.D1.R0.S10: Total Receive Enable Delay = 1292
N0.C0.D1.R0.S09: Preamble found at Latency = 007
N2.C1.D1.R1.S10: Rcv En Fine Value = 289
N4.C1.D0.R1.S16: Total Receive Enable Delay = 1364
N6.C0.D1.R0.S11: Total Receive Enable Delay = 1265
N0.C0.D1.R0.S10: Preamble found at Latency = 007
N2.C1.D1.R1.S11: Rcv En Fine Value = 256
N4.C1.D0.R1.S17: Total Receive Enable Delay = 1284
N6.C0.D1.R0.S12: Total Receive Enable Delay = 1245
N0.C0.D1.R0.S11: Preamble found at Latency = 007
N2.C1.D1.R1.S12: Rcv En Fine Value = 365
N4.C1.D1.R0: RcvEnFine: Initial RdCmd2RcvEnLatency = 10, Initial RdPtrOffsetRcvEn = 4
N6.C0.D1.R0.S13: Total Receive Enable Delay = 1238
N0.C0.D1.R0.S12: Preamble found at Latency = 007
N2.C1.D1.R1.S13: Rcv En Fine Value = 355
N4.C1.D1.R0.S00: Rcv En Fine Value = 300
N6.C0.D1.R0.S14: Total Receive Enable Delay = 1259
N0.C0.D1.R0.S13: Preamble found at Latency = 007
N2.C1.D1.R1.S14: Rcv En Fine Value = 381
N4.C1.D1.R0.S01: Rcv En Fine Value = 279
N6.C0.D1.R0.S15: Total Receive Enable Delay = 1289
N0.C0.D1.R0.S14: Preamble found at Latency = 007
N2.C1.D1.R1.S15: Rcv En Fine Value = 278
N4.C1.D1.R0.S02: Rcv En Fine Value = 379
N6.C0.D1.R0.S16: Total Receive Enable Delay = 1313
N0.C0.D1.R0.S15: Preamble found at Latency = 007
N2.C1.D1.R1.S16: Rcv En Fine Value = 298
N4.C1.D1.R0.S03: Rcv En Fine Value = 356
N6.C0.D1.R0.S17: Total Receive Enable Delay = 1231
N0.C0.D1.R0.S16: Preamble found at Latency = 007
N2.C1.D1.R1.S17: Rcv En Fine Value = 345
N4.C1.D1.R0.S04: Rcv En Fine Value = 350
N6.C0.D1.R1: RcvEnFine: Initial RdCmd2RcvEnLatency = 10, Initial RdPtrOffsetRcvEn = 4
N0.C0.D1.R0.S17: Preamble found at Latency = 007
N2.C1.D1.R1: Starting preamble search lower nibbles
N4.C1.D1.R0.S05: Rcv En Fine Value = 377
N6.C0.D1.R1.S00: Rcv En Fine Value = 262
N0.C0.D1.R0: Preamble found for all upper nibbles, adjusting Pi, Offset to center into preamble
N2.C1.D1.R1.S00: PI = 050, PtrOffset = 004
N4.C1.D1.R0.S06: Rcv En Fine Value = 272
N6.C0.D1.R1.S01: Rcv En Fine Value = 366
N0.C0.D1.R0.S09: Total Receive Enable Delay = 1306
N2.C1.D1.R1.S01: PI = 029, PtrOffset = 004
N4.C1.D1.R0.S07: Rcv En Fine Value = 290
N6.C0.D1.R1.S02: Rcv En Fine Value = 335
N0.C0.D1.R0.S10: Total Receive Enable Delay = 1283
N2.C1.D1.R1.S02: PI = 000, PtrOffset = 004
N4.C1.D1.R0.S08: Rcv En Fine Value = 337
N6.C0.D1.R1.S03: Rcv En Fine Value = 317
N0.C0.D1.R0.S11: Total Receive Enable Delay = 1256
N2.C1.D1.R1.S03: PI = 043, PtrOffset = 005
N4.C1.D1.R0.S09: Rcv En Fine Value = 302
N6.C0.D1.R1.S04: Rcv En Fine Value = 310
N0.C0.D1.R0.S12: Total Receive Enable Delay = 1239
N2.C1.D1.R1.S04: PI = 038, PtrOffset = 005
N4.C1.D1.R0.S10: Rcv En Fine Value = 280
N6.C0.D1.R1.S05: Rcv En Fine Value = 331
N0.C0.D1.R0.S13: Total Receive Enable Delay = 1231
N2.C1.D1.R1.S05: PI = 063, PtrOffset = 005
N4.C1.D1.R0.S11: Rcv En Fine Value = 383
N6.C0.D1.R1.S06: Rcv En Fine Value = 366
N0.C0.D1.R0.S14: Total Receive Enable Delay = 1253
N2.C1.D1.R1.S06: PI = 022, PtrOffset = 004
N4.C1.D1.R0.S12: Rcv En Fine Value = 359
N6.C0.D1.R1.S07: Rcv En Fine Value = 260
N0.C0.D1.R0.S15: Total Receive Enable Delay = 1287
N2.C1.D1.R1.S07: PI = 041, PtrOffset = 004
N4.C1.D1.R0.S13: Rcv En Fine Value = 350
N6.C0.D1.R1.S08: Rcv En Fine Value = 306
N0.C0.D1.R0.S16: Total Receive Enable Delay = 1308
N2.C1.D1.R1.S08: PI = 024, PtrOffset = 005
N4.C1.D1.R0.S14: Rcv En Fine Value = 376
N6.C0.D1.R1.S09: Rcv En Fine Value = 258
N0.C0.D1.R0.S17: Total Receive Enable Delay = 1221
N2.C1.D1.R1.S00: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N4.C1.D1.R0.S15: Rcv En Fine Value = 274
N6.C0.D1.R1.S10: Rcv En Fine Value = 364
N0.C0.D1.R1: RcvEnFine: Initial RdCmd2RcvEnLatency = 10, Initial RdPtrOffsetRcvEn = 4
N2.C1.D1.R1.S01: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N4.C1.D1.R0.S16: Rcv En Fine Value = 294
N6.C0.D1.R1.S11: Rcv En Fine Value = 333
N0.C0.D1.R1.S00: Rcv En Fine Value = 380
N2.C1.D1.R1.S02: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N4.C1.D1.R0.S17: Rcv En Fine Value = 338
N6.C0.D1.R1.S12: Rcv En Fine Value = 317
N0.C0.D1.R1.S01: Rcv En Fine Value = 361
N2.C1.D1.R1.S03: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N4.C1.D1.R0: Starting preamble search lower nibbles
N6.C0.D1.R1.S13: Rcv En Fine Value = 309
N0.C0.D1.R1.S02: Rcv En Fine Value = 330
N2.C1.D1.R1.S04: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N4.C1.D1.R0.S00: PI = 044, PtrOffset = 004
N6.C0.D1.R1.S14: Rcv En Fine Value = 332
N0.C0.D1.R1.S03: Rcv En Fine Value = 311
N2.C1.D1.R1.S05: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N4.C1.D1.R0.S01: PI = 023, PtrOffset = 004
N6.C0.D1.R1.S15: Rcv En Fine Value = 363
N0.C0.D1.R1.S04: Rcv En Fine Value = 303
N2.C1.D1.R1.S06: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N4.C1.D1.R0.S02: PI = 059, PtrOffset = 005
N6.C0.D1.R1.S16: Rcv En Fine Value = 258
N0.C0.D1.R1.S05: Rcv En Fine Value = 322
N2.C1.D1.R1.S07: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N4.C1.D1.R0.S03: PI = 036, PtrOffset = 005
N6.C0.D1.R1.S17: Rcv En Fine Value = 303
N0.C0.D1.R1.S06: Rcv En Fine Value = 359
N2.C1.D1.R1.S08: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N4.C1.D1.R0.S04: PI = 030, PtrOffset = 005
N6.C0.D1.R1: Starting preamble search lower nibbles
N0.C0.D1.R1.S07: Rcv En Fine Value = 381
N2.C1.D1.R1.S00: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N4.C1.D1.R0.S05: PI = 057, PtrOffset = 005
N6.C0.D1.R1.S00: PI = 006, PtrOffset = 004
N0.C0.D1.R1.S08: Rcv En Fine Value = 300
N2.C1.D1.R1.S01: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N4.C1.D1.R0.S06: PI = 016, PtrOffset = 004
N6.C0.D1.R1.S01: PI = 046, PtrOffset = 005
N0.C0.D1.R1.S09: Rcv En Fine Value = 377
N2.C1.D1.R1.S02: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N4.C1.D1.R0.S07: PI = 034, PtrOffset = 004
N6.C0.D1.R1.S02: PI = 015, PtrOffset = 005
N0.C0.D1.R1.S10: Rcv En Fine Value = 359
N2.C1.D1.R1.S03: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N4.C1.D1.R0.S08: PI = 017, PtrOffset = 005
N6.C0.D1.R1.S03: PI = 061, PtrOffset = 004
N0.C0.D1.R1.S11: Rcv En Fine Value = 331
N2.C1.D1.R1.S04: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N4.C1.D1.R0.S00: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N6.C0.D1.R1.S04: PI = 054, PtrOffset = 004
N0.C0.D1.R1.S12: Rcv En Fine Value = 310
N2.C1.D1.R1.S05: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N4.C1.D1.R0.S01: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N6.C0.D1.R1.S05: PI = 011, PtrOffset = 005
N0.C0.D1.R1.S13: Rcv En Fine Value = 300
N2.C1.D1.R1.S06: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N4.C1.D1.R0.S02: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N6.C0.D1.R1.S06: PI = 046, PtrOffset = 005
N0.C0.D1.R1.S14: Rcv En Fine Value = 325
N2.C1.D1.R1.S07: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N4.C1.D1.R0.S03: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N6.C0.D1.R1.S07: PI = 004, PtrOffset = 004
N0.C0.D1.R1.S15: Rcv En Fine Value = 360
N2.C1.D1.R1.S08: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N4.C1.D1.R0.S04: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N6.C0.D1.R1.S08: PI = 050, PtrOffset = 004
N0.C0.D1.R1.S16: Rcv En Fine Value = 383
N2.C1.D1.R1.S00: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N4.C1.D1.R0.S05: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N6.C0.D1.R1.S00: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N0.C0.D1.R1.S17: Rcv En Fine Value = 297
N2.C1.D1.R1.S01: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N4.C1.D1.R0.S06: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N6.C0.D1.R1.S01: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N0.C0.D1.R1: Starting preamble search lower nibbles
N2.C1.D1.R1.S02: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N4.C1.D1.R0.S07: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N6.C0.D1.R1.S02: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N0.C0.D1.R1.S00: PI = 060, PtrOffset = 005
N2.C1.D1.R1.S03: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N4.C1.D1.R0.S08: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N6.C0.D1.R1.S03: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N0.C0.D1.R1.S01: PI = 041, PtrOffset = 005
N2.C1.D1.R1.S04: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N4.C1.D1.R0.S00: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N6.C0.D1.R1.S04: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N0.C0.D1.R1.S02: PI = 010, PtrOffset = 005
N2.C1.D1.R1.S05: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N4.C1.D1.R0.S01: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N6.C0.D1.R1.S05: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N0.C0.D1.R1.S03: PI = 055, PtrOffset = 004
N2.C1.D1.R1.S06: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N4.C1.D1.R0.S02: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N6.C0.D1.R1.S06: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N0.C0.D1.R1.S04: PI = 047, PtrOffset = 004
N2.C1.D1.R1.S07: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N4.C1.D1.R0.S03: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N6.C0.D1.R1.S07: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N0.C0.D1.R1.S05: PI = 002, PtrOffset = 005
N2.C1.D1.R1.S08: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N4.C1.D1.R0.S04: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N6.C0.D1.R1.S08: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N0.C0.D1.R1.S06: PI = 039, PtrOffset = 005
N2.C1.D1.R1.S00: Preamble found at Latency = 008
N4.C1.D1.R0.S05: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N6.C0.D1.R1.S00: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N0.C0.D1.R1.S07: PI = 061, PtrOffset = 005
N2.C1.D1.R1.S01: Preamble found at Latency = 008
N4.C1.D1.R0.S06: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N6.C0.D1.R1.S01: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N0.C0.D1.R1.S08: PI = 044, PtrOffset = 004
N2.C1.D1.R1.S02: Preamble found at Latency = 008
N4.C1.D1.R0.S07: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N6.C0.D1.R1.S02: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N0.C0.D1.R1.S00: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N2.C1.D1.R1.S06: Preamble found at Latency = 008
N4.C1.D1.R0.S08: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N6.C0.D1.R1.S03: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N0.C0.D1.R1.S01: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N2.C1.D1.R1.S07: Preamble found at Latency = 008
N4.C1.D1.R0.S00: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N6.C0.D1.R1.S04: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N0.C0.D1.R1.S02: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N2.C1.D1.R1.S00: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N4.C1.D1.R0.S01: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N6.C0.D1.R1.S05: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N0.C0.D1.R1.S03: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N2.C1.D1.R1.S01: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N4.C1.D1.R0.S02: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N6.C0.D1.R1.S06: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N0.C0.D1.R1.S04: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N2.C1.D1.R1.S02: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N4.C1.D1.R0.S03: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N6.C0.D1.R1.S07: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N0.C0.D1.R1.S05: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N2.C1.D1.R1.S03: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N4.C1.D1.R0.S04: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N6.C0.D1.R1.S08: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N0.C0.D1.R1.S06: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N2.C1.D1.R1.S04: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N4.C1.D1.R0.S05: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N6.C0.D1.R1.S00: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N0.C0.D1.R1.S07: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N2.C1.D1.R1.S05: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N4.C1.D1.R0.S06: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N6.C0.D1.R1.S01: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N0.C0.D1.R1.S08: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N2.C1.D1.R1.S06: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N4.C1.D1.R0.S07: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N6.C0.D1.R1.S02: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N0.C0.D1.R1.S00: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N2.C1.D1.R1.S07: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N4.C1.D1.R0.S08: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N6.C0.D1.R1.S03: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N0.C0.D1.R1.S01: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N2.C1.D1.R1.S08: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N4.C1.D1.R0.S00: Preamble found at Latency = 008
N6.C0.D1.R1.S04: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N0.C0.D1.R1.S02: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N2.C1.D1.R1.S03: Preamble found at Latency = 007
N4.C1.D1.R0.S01: Preamble found at Latency = 008
N6.C0.D1.R1.S05: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N0.C0.D1.R1.S03: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N2.C1.D1.R1.S04: Preamble found at Latency = 007
N4.C1.D1.R0.S06: Preamble found at Latency = 008
N6.C0.D1.R1.S06: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N0.C0.D1.R1.S04: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N2.C1.D1.R1.S05: Preamble found at Latency = 007
N4.C1.D1.R0.S07: Preamble found at Latency = 008
N6.C0.D1.R1.S07: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N0.C0.D1.R1.S05: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N2.C1.D1.R1.S08: Preamble found at Latency = 007
N4.C1.D1.R0.S00: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N6.C0.D1.R1.S08: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N0.C0.D1.R1.S06: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N2.C1.D1.R1.S00: Total Receive Enable Delay = 1362
N4.C1.D1.R0.S01: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N6.C0.D1.R1.S00: Preamble found at Latency = 008
N0.C0.D1.R1.S07: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N2.C1.D1.R1.S01: Total Receive Enable Delay = 1341
N4.C1.D1.R0.S02: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N6.C0.D1.R1.S07: Preamble found at Latency = 008
N0.C0.D1.R1.S08: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N2.C1.D1.R1.S02: Total Receive Enable Delay = 1312
N4.C1.D1.R0.S03: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N6.C0.D1.R1.S00: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N0.C0.D1.R1.S00: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N2.C1.D1.R1.S03: Total Receive Enable Delay = 1291
N4.C1.D1.R0.S04: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N6.C0.D1.R1.S01: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N0.C0.D1.R1.S01: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N2.C1.D1.R1.S04: Total Receive Enable Delay = 1286
N4.C1.D1.R0.S05: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N6.C0.D1.R1.S02: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N0.C0.D1.R1.S02: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N2.C1.D1.R1.S05: Total Receive Enable Delay = 1311
N4.C1.D1.R0.S06: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N6.C0.D1.R1.S03: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N0.C0.D1.R1.S03: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N2.C1.D1.R1.S06: Total Receive Enable Delay = 1334
N4.C1.D1.R0.S07: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N6.C0.D1.R1.S04: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N0.C0.D1.R1.S04: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N2.C1.D1.R1.S07: Total Receive Enable Delay = 1353
N4.C1.D1.R0.S08: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N6.C0.D1.R1.S05: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N0.C0.D1.R1.S05: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N2.C1.D1.R1.S08: Total Receive Enable Delay = 1272
N4.C1.D1.R0.S02: Preamble found at Latency = 007
N6.C0.D1.R1.S06: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N0.C0.D1.R1.S06: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N2.C1.D1.R1: Starting preamble search upper nibbles
N4.C1.D1.R0.S03: Preamble found at Latency = 007
N6.C0.D1.R1.S07: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N0.C0.D1.R1.S07: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N2.C1.D1.R1.S09: PI = 050, PtrOffset = 004
N4.C1.D1.R0.S04: Preamble found at Latency = 007
N6.C0.D1.R1.S08: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N0.C0.D1.R1.S08: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N2.C1.D1.R1.S10: PI = 033, PtrOffset = 004
N4.C1.D1.R0.S05: Preamble found at Latency = 007
N6.C0.D1.R1.S01: Preamble found at Latency = 007
N0.C0.D1.R1.S00: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N2.C1.D1.R1.S11: PI = 000, PtrOffset = 004
N4.C1.D1.R0.S08: Preamble found at Latency = 007
N6.C0.D1.R1.S02: Preamble found at Latency = 007
N0.C0.D1.R1.S01: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N2.C1.D1.R1.S12: PI = 045, PtrOffset = 005
N4.C1.D1.R0.S00: Total Receive Enable Delay = 1356
N6.C0.D1.R1.S03: Preamble found at Latency = 007
N0.C0.D1.R1.S02: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N2.C1.D1.R1.S13: PI = 035, PtrOffset = 005
N4.C1.D1.R0.S01: Total Receive Enable Delay = 1335
N6.C0.D1.R1.S04: Preamble found at Latency = 007
N0.C0.D1.R1.S03: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N2.C1.D1.R1.S14: PI = 061, PtrOffset = 005
N4.C1.D1.R0.S02: Total Receive Enable Delay = 1307
N6.C0.D1.R1.S05: Preamble found at Latency = 007
N0.C0.D1.R1.S04: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N2.C1.D1.R1.S15: PI = 022, PtrOffset = 004
N4.C1.D1.R0.S03: Total Receive Enable Delay = 1284
N6.C0.D1.R1.S06: Preamble found at Latency = 007
N0.C0.D1.R1.S05: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N2.C1.D1.R1.S16: PI = 042, PtrOffset = 004
N4.C1.D1.R0.S04: Total Receive Enable Delay = 1278
N6.C0.D1.R1.S08: Preamble found at Latency = 007
N0.C0.D1.R1.S06: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N2.C1.D1.R1.S17: PI = 025, PtrOffset = 005
N4.C1.D1.R0.S05: Total Receive Enable Delay = 1305
N6.C0.D1.R1.S00: Total Receive Enable Delay = 1318
N0.C0.D1.R1.S07: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N2.C1.D1.R1.S09: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N4.C1.D1.R0.S06: Total Receive Enable Delay = 1328
N6.C0.D1.R1.S01: Total Receive Enable Delay = 1294
N0.C0.D1.R1.S08: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N2.C1.D1.R1.S10: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N4.C1.D1.R0.S07: Total Receive Enable Delay = 1346
N6.C0.D1.R1.S02: Total Receive Enable Delay = 1263
N0.C0.D1.R1.S00: Preamble found at Latency = 007
N2.C1.D1.R1.S11: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N4.C1.D1.R0.S08: Total Receive Enable Delay = 1265
N6.C0.D1.R1.S03: Total Receive Enable Delay = 1245
N0.C0.D1.R1.S01: Preamble found at Latency = 007
N2.C1.D1.R1.S12: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N4.C1.D1.R0: Starting preamble search upper nibbles
N6.C0.D1.R1.S04: Total Receive Enable Delay = 1238
N0.C0.D1.R1.S02: Preamble found at Latency = 007
N2.C1.D1.R1.S13: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N4.C1.D1.R0.S09: PI = 046, PtrOffset = 004
N6.C0.D1.R1.S05: Total Receive Enable Delay = 1259
N0.C0.D1.R1.S03: Preamble found at Latency = 007
N2.C1.D1.R1.S14: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N4.C1.D1.R0.S10: PI = 024, PtrOffset = 004
N6.C0.D1.R1.S06: Total Receive Enable Delay = 1294
N0.C0.D1.R1.S04: Preamble found at Latency = 007
N2.C1.D1.R1.S15: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N4.C1.D1.R0.S11: PI = 063, PtrOffset = 005
N6.C0.D1.R1.S07: Total Receive Enable Delay = 1316
N0.C0.D1.R1.S05: Preamble found at Latency = 007
N2.C1.D1.R1.S16: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N4.C1.D1.R0.S12: PI = 039, PtrOffset = 005
N6.C0.D1.R1.S08: Total Receive Enable Delay = 1234
N0.C0.D1.R1.S06: Preamble found at Latency = 007
N2.C1.D1.R1.S17: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N4.C1.D1.R0.S13: PI = 030, PtrOffset = 005
N6.C0.D1.R1: Starting preamble search upper nibbles
N0.C0.D1.R1.S07: Preamble found at Latency = 007
N2.C1.D1.R1.S09: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N4.C1.D1.R0.S14: PI = 056, PtrOffset = 005
N6.C0.D1.R1.S09: PI = 002, PtrOffset = 004
N0.C0.D1.R1.S08: Preamble found at Latency = 007
N2.C1.D1.R1.S10: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N4.C1.D1.R0.S15: PI = 018, PtrOffset = 004
N6.C0.D1.R1.S10: PI = 044, PtrOffset = 005
N0.C0.D1.R1.S00: Total Receive Enable Delay = 1308
N2.C1.D1.R1.S11: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N4.C1.D1.R0.S16: PI = 038, PtrOffset = 004
N6.C0.D1.R1.S11: PI = 013, PtrOffset = 005
N0.C0.D1.R1.S01: Total Receive Enable Delay = 1289
N2.C1.D1.R1.S12: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N4.C1.D1.R0.S17: PI = 018, PtrOffset = 005
N6.C0.D1.R1.S12: PI = 061, PtrOffset = 004
N0.C0.D1.R1.S02: Total Receive Enable Delay = 1258
N2.C1.D1.R1.S13: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N4.C1.D1.R0.S09: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N6.C0.D1.R1.S13: PI = 053, PtrOffset = 004
N0.C0.D1.R1.S03: Total Receive Enable Delay = 1239
N2.C1.D1.R1.S14: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N4.C1.D1.R0.S10: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N6.C0.D1.R1.S14: PI = 012, PtrOffset = 005
N0.C0.D1.R1.S04: Total Receive Enable Delay = 1231
N2.C1.D1.R1.S15: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N4.C1.D1.R0.S11: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N6.C0.D1.R1.S15: PI = 043, PtrOffset = 005
N0.C0.D1.R1.S05: Total Receive Enable Delay = 1250
N2.C1.D1.R1.S16: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N4.C1.D1.R0.S12: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N6.C0.D1.R1.S16: PI = 002, PtrOffset = 004
N0.C0.D1.R1.S06: Total Receive Enable Delay = 1287
N2.C1.D1.R1.S17: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N4.C1.D1.R0.S13: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N6.C0.D1.R1.S17: PI = 047, PtrOffset = 004
N0.C0.D1.R1.S07: Total Receive Enable Delay = 1309
N2.C1.D1.R1.S09: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N4.C1.D1.R0.S14: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N6.C0.D1.R1.S09: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N0.C0.D1.R1.S08: Total Receive Enable Delay = 1228
N2.C1.D1.R1.S10: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N4.C1.D1.R0.S15: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N6.C0.D1.R1.S10: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N0.C0.D1.R1: Starting preamble search upper nibbles
N2.C1.D1.R1.S11: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N4.C1.D1.R0.S16: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N6.C0.D1.R1.S11: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N0.C0.D1.R1.S09: PI = 057, PtrOffset = 005
N2.C1.D1.R1.S12: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N4.C1.D1.R0.S17: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N6.C0.D1.R1.S12: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N0.C0.D1.R1.S10: PI = 039, PtrOffset = 005
N2.C1.D1.R1.S13: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N4.C1.D1.R0.S09: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N6.C0.D1.R1.S13: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N0.C0.D1.R1.S11: PI = 011, PtrOffset = 005
N2.C1.D1.R1.S14: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N4.C1.D1.R0.S10: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N6.C0.D1.R1.S14: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N0.C0.D1.R1.S12: PI = 054, PtrOffset = 004
N2.C1.D1.R1.S15: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N4.C1.D1.R0.S11: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N6.C0.D1.R1.S15: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N0.C0.D1.R1.S13: PI = 044, PtrOffset = 004
N2.C1.D1.R1.S16: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N4.C1.D1.R0.S12: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N6.C0.D1.R1.S16: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N0.C0.D1.R1.S14: PI = 005, PtrOffset = 005
N2.C1.D1.R1.S17: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N4.C1.D1.R0.S13: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N6.C0.D1.R1.S17: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N0.C0.D1.R1.S15: PI = 040, PtrOffset = 005
N2.C1.D1.R1.S09: Preamble found at Latency = 008
N4.C1.D1.R0.S14: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N6.C0.D1.R1.S09: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N0.C0.D1.R1.S16: PI = 063, PtrOffset = 005
N2.C1.D1.R1.S10: Preamble found at Latency = 008
N4.C1.D1.R0.S15: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N6.C0.D1.R1.S10: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N0.C0.D1.R1.S17: PI = 041, PtrOffset = 004
N2.C1.D1.R1.S11: Preamble found at Latency = 008
N4.C1.D1.R0.S16: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N6.C0.D1.R1.S11: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N0.C0.D1.R1.S09: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N2.C1.D1.R1.S15: Preamble found at Latency = 008
N4.C1.D1.R0.S17: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N6.C0.D1.R1.S12: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N0.C0.D1.R1.S10: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N2.C1.D1.R1.S16: Preamble found at Latency = 008
N4.C1.D1.R0.S09: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N6.C0.D1.R1.S13: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N0.C0.D1.R1.S11: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N2.C1.D1.R1.S09: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N4.C1.D1.R0.S10: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N6.C0.D1.R1.S14: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N0.C0.D1.R1.S12: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N2.C1.D1.R1.S10: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N4.C1.D1.R0.S11: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N6.C0.D1.R1.S15: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N0.C0.D1.R1.S13: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N2.C1.D1.R1.S11: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N4.C1.D1.R0.S12: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N6.C0.D1.R1.S16: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N0.C0.D1.R1.S14: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N2.C1.D1.R1.S12: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N4.C1.D1.R0.S13: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N6.C0.D1.R1.S17: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N0.C0.D1.R1.S15: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N2.C1.D1.R1.S13: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N4.C1.D1.R0.S14: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N6.C0.D1.R1.S09: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N0.C0.D1.R1.S16: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N2.C1.D1.R1.S14: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N4.C1.D1.R0.S15: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N6.C0.D1.R1.S10: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N0.C0.D1.R1.S17: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N2.C1.D1.R1.S15: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N4.C1.D1.R0.S16: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N6.C0.D1.R1.S11: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N0.C0.D1.R1.S09: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N2.C1.D1.R1.S16: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N4.C1.D1.R0.S17: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N6.C0.D1.R1.S12: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N0.C0.D1.R1.S10: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N2.C1.D1.R1.S17: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N4.C1.D1.R0.S09: Preamble found at Latency = 008
N6.C0.D1.R1.S13: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N0.C0.D1.R1.S11: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N2.C1.D1.R1.S12: Preamble found at Latency = 007
N4.C1.D1.R0.S10: Preamble found at Latency = 008
N6.C0.D1.R1.S14: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N0.C0.D1.R1.S12: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N2.C1.D1.R1.S13: Preamble found at Latency = 007
N4.C1.D1.R0.S15: Preamble found at Latency = 008
N6.C0.D1.R1.S15: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N0.C0.D1.R1.S13: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N2.C1.D1.R1.S14: Preamble found at Latency = 007
N4.C1.D1.R0.S16: Preamble found at Latency = 008
N6.C0.D1.R1.S16: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N0.C0.D1.R1.S14: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N2.C1.D1.R1.S17: Preamble found at Latency = 007
N4.C1.D1.R0.S09: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N6.C0.D1.R1.S17: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N0.C0.D1.R1.S15: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N2.C1.D1.R1: Preamble found for all upper nibbles, adjusting Pi, Offset to center into preamble
N4.C1.D1.R0.S10: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N6.C0.D1.R1.S09: Preamble found at Latency = 008
N0.C0.D1.R1.S16: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N2.C1.D1.R1.S09: Total Receive Enable Delay = 1362
N4.C1.D1.R0.S11: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N6.C0.D1.R1.S16: Preamble found at Latency = 008
N0.C0.D1.R1.S17: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N2.C1.D1.R1.S10: Total Receive Enable Delay = 1345
N4.C1.D1.R0.S12: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N6.C0.D1.R1.S09: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N0.C0.D1.R1.S09: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N2.C1.D1.R1.S11: Total Receive Enable Delay = 1312
N4.C1.D1.R0.S13: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N6.C0.D1.R1.S10: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N0.C0.D1.R1.S10: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N2.C1.D1.R1.S12: Total Receive Enable Delay = 1293
N4.C1.D1.R0.S14: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N6.C0.D1.R1.S11: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N0.C0.D1.R1.S11: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N2.C1.D1.R1.S13: Total Receive Enable Delay = 1283
N4.C1.D1.R0.S15: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N6.C0.D1.R1.S12: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N0.C0.D1.R1.S12: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N2.C1.D1.R1.S14: Total Receive Enable Delay = 1309
N4.C1.D1.R0.S16: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N6.C0.D1.R1.S13: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N0.C0.D1.R1.S13: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N2.C1.D1.R1.S15: Total Receive Enable Delay = 1334
N4.C1.D1.R0.S17: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N6.C0.D1.R1.S14: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N0.C0.D1.R1.S14: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N2.C1.D1.R1.S16: Total Receive Enable Delay = 1354
N4.C1.D1.R0.S11: Preamble found at Latency = 007
N6.C0.D1.R1.S15: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N0.C0.D1.R1.S15: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N2.C1.D1.R1.S17: Total Receive Enable Delay = 1273
N4.C1.D1.R0.S12: Preamble found at Latency = 007
N6.C0.D1.R1.S16: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N0.C0.D1.R1.S16: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
START_DATA_REC_EN
N4.C1.D1.R0.S13: Preamble found at Latency = 007
N6.C0.D1.R1.S17: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N0.C0.D1.R1.S17: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N2.C1.S00: RdCmd2RcvEnLatency = 9, RdPtrOffsetRcvEn = 5
N4.C1.D1.R0.S14: Preamble found at Latency = 007
N6.C0.D1.R1.S10: Preamble found at Latency = 007
N0.C0.D1.R1.S09: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N2.C1.S01: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N4.C1.D1.R0.S17: Preamble found at Latency = 007
N6.C0.D1.R1.S11: Preamble found at Latency = 007
N0.C0.D1.R1.S10: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N2.C1.S02: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N4.C1.D1.R0: Preamble found for all upper nibbles, adjusting Pi, Offset to center into preamble
N6.C0.D1.R1.S12: Preamble found at Latency = 007
N0.C0.D1.R1.S11: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N2.C1.S03: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N4.C1.D1.R0.S09: Total Receive Enable Delay = 1358
N6.C0.D1.R1.S13: Preamble found at Latency = 007
N0.C0.D1.R1.S12: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N2.C1.S04: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N4.C1.D1.R0.S10: Total Receive Enable Delay = 1336
N6.C0.D1.R1.S14: Preamble found at Latency = 007
N0.C0.D1.R1.S13: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N2.C1.S05: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N4.C1.D1.R0.S11: Total Receive Enable Delay = 1311
N6.C0.D1.R1.S15: Preamble found at Latency = 007
N0.C0.D1.R1.S14: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N2.C1.S06: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N4.C1.D1.R0.S12: Total Receive Enable Delay = 1287
N6.C0.D1.R1.S17: Preamble found at Latency = 007
N0.C0.D1.R1.S15: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N2.C1.S07: RdCmd2RcvEnLatency = 9, RdPtrOffsetRcvEn = 5
N4.C1.D1.R0.S13: Total Receive Enable Delay = 1278
N6.C0.D1.R1: Preamble found for all upper nibbles, adjusting Pi, Offset to center into preamble
N0.C0.D1.R1.S16: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N2.C1.S08: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 5
N4.C1.D1.R0.S14: Total Receive Enable Delay = 1304
N6.C0.D1.R1.S09: Total Receive Enable Delay = 1314
N0.C0.D1.R1.S17: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N2.C1.S09: RdCmd2RcvEnLatency = 9, RdPtrOffsetRcvEn = 5
N4.C1.D1.R0.S15: Total Receive Enable Delay = 1330
N6.C0.D1.R1.S10: Total Receive Enable Delay = 1292
N0.C0.D1.R1.S09: Preamble found at Latency = 007
N2.C1.S10: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N4.C1.D1.R0.S16: Total Receive Enable Delay = 1350
N6.C0.D1.R1.S11: Total Receive Enable Delay = 1261
N0.C0.D1.R1.S10: Preamble found at Latency = 007
N2.C1.S11: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N4.C1.D1.R0.S17: Total Receive Enable Delay = 1266
N6.C0.D1.R1.S12: Total Receive Enable Delay = 1245
N0.C0.D1.R1.S11: Preamble found at Latency = 007
N2.C1.S12: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N4.C1.D1.R1: RcvEnFine: Initial RdCmd2RcvEnLatency = 10, Initial RdPtrOffsetRcvEn = 4
N6.C0.D1.R1.S13: Total Receive Enable Delay = 1237
N0.C0.D1.R1.S12: Preamble found at Latency = 007
N2.C1.S13: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N4.C1.D1.R1.S00: Rcv En Fine Value = 300
N6.C0.D1.R1.S14: Total Receive Enable Delay = 1260
N0.C0.D1.R1.S13: Preamble found at Latency = 007
N2.C1.S14: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N4.C1.D1.R1.S01: Rcv En Fine Value = 280
N6.C0.D1.R1.S15: Total Receive Enable Delay = 1291
N0.C0.D1.R1.S14: Preamble found at Latency = 007
N2.C1.S15: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N4.C1.D1.R1.S02: Rcv En Fine Value = 378
N6.C0.D1.R1.S16: Total Receive Enable Delay = 1314
N0.C0.D1.R1.S15: Preamble found at Latency = 007
N2.C1.S16: RdCmd2RcvEnLatency = 9, RdPtrOffsetRcvEn = 5
N4.C1.D1.R1.S03: Rcv En Fine Value = 355
N6.C0.D1.R1.S17: Total Receive Enable Delay = 1231
N0.C0.D1.R1.S16: Preamble found at Latency = 007
N2.C1.S17: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 5
N4.C1.D1.R1.S04: Rcv En Fine Value = 350
START_DATA_REC_EN
N0.C0.D1.R1.S17: Preamble found at Latency = 007
N2.C1.D0.R0.S00: RcvEn: plus1 = 1, minus1 = 0, PI = 32, DB = 0
N4.C1.D1.R1.S05: Rcv En Fine Value = 375
N6.C0.S00: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N0.C0.D1.R1: Preamble found for all upper nibbles, adjusting Pi, Offset to center into preamble
N2.C1.D0.R0.S01: RcvEn: plus1 = 0, minus1 = 1, PI = 14, DB = 1
N4.C1.D1.R1.S06: Rcv En Fine Value = 271
N6.C0.S01: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N0.C0.D1.R1.S09: Total Receive Enable Delay = 1305
N2.C1.D0.R0.S02: RcvEn: plus1 = 1, minus1 = 0, PI = 47, DB = 0
N4.C1.D1.R1.S07: Rcv En Fine Value = 291
N6.C0.S02: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 5
N0.C0.D1.R1.S10: Total Receive Enable Delay = 1287
N2.C1.D0.R0.S03: RcvEn: plus1 = 1, minus1 = 0, PI = 27, DB = 0
N4.C1.D1.R1.S08: Rcv En Fine Value = 338
N6.C0.S03: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 5
N0.C0.D1.R1.S11: Total Receive Enable Delay = 1259
N2.C1.D0.R0.S04: RcvEn: plus1 = 1, minus1 = 0, PI = 20, DB = 0
N4.C1.D1.R1.S09: Rcv En Fine Value = 301
N6.C0.S04: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 5
N0.C0.D1.R1.S12: Total Receive Enable Delay = 1238
N2.C1.D0.R0.S05: RcvEn: plus1 = 1, minus1 = 0, PI = 44, DB = 0
N4.C1.D1.R1.S10: Rcv En Fine Value = 281
N6.C0.S05: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 5
N0.C0.D1.R1.S13: Total Receive Enable Delay = 1228
N2.C1.D0.R0.S06: RcvEn: plus1 = 0, minus1 = 1, PI = 05, DB = 1
N4.C1.D1.R1.S11: Rcv En Fine Value = 380
N6.C0.S06: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N0.C0.D1.R1.S14: Total Receive Enable Delay = 1253
N2.C1.D0.R0.S07: RcvEn: plus1 = 1, minus1 = 0, PI = 26, DB = 0
N4.C1.D1.R1.S12: Rcv En Fine Value = 360
N6.C0.S07: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N0.C0.D1.R1.S15: Total Receive Enable Delay = 1288
N2.C1.D0.R0.S08: RcvEn: plus1 = 0, minus1 = 1, PI = 07, DB = 1
N4.C1.D1.R1.S13: Rcv En Fine Value = 350
N6.C0.S08: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 5
N0.C0.D1.R1.S16: Total Receive Enable Delay = 1311
N2.C1.D0.R0.S09: RcvEn: plus1 = 1, minus1 = 0, PI = 33, DB = 0
N4.C1.D1.R1.S14: Rcv En Fine Value = 375
N6.C0.S09: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N0.C0.D1.R1.S17: Total Receive Enable Delay = 1225
N2.C1.D0.R0.S10: RcvEn: plus1 = 0, minus1 = 1, PI = 13, DB = 1
N4.C1.D1.R1.S15: Rcv En Fine Value = 273
N6.C0.S10: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
START_DATA_REC_EN
N2.C1.D0.R0.S11: RcvEn: plus1 = 1, minus1 = 0, PI = 47, DB = 0
N4.C1.D1.R1.S16: Rcv En Fine Value = 294
N6.C0.S11: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 5
N0.C0.S00: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N2.C1.D0.R0.S12: RcvEn: plus1 = 1, minus1 = 0, PI = 28, DB = 0
N4.C1.D1.R1.S17: Rcv En Fine Value = 338
N6.C0.S12: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 5
N0.C0.S01: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N2.C1.D0.R0.S13: RcvEn: plus1 = 1, minus1 = 0, PI = 19, DB = 0
N4.C1.D1.R1: Starting preamble search lower nibbles
N6.C0.S13: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 5
N0.C0.S02: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 5
N2.C1.D0.R0.S14: RcvEn: plus1 = 1, minus1 = 0, PI = 44, DB = 0
N4.C1.D1.R1.S00: PI = 044, PtrOffset = 004
N6.C0.S14: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 5
N0.C0.S03: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 5
N2.C1.D0.R0.S15: RcvEn: plus1 = 0, minus1 = 1, PI = 08, DB = 1
N4.C1.D1.R1.S01: PI = 024, PtrOffset = 004
N6.C0.S15: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N0.C0.S04: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 5
N2.C1.D0.R0.S16: RcvEn: plus1 = 1, minus1 = 0, PI = 27, DB = 0
N4.C1.D1.R1.S02: PI = 058, PtrOffset = 005
N6.C0.S16: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N0.C0.S05: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 5
N2.C1.D0.R0.S17: RcvEn: plus1 = 0, minus1 = 1, PI = 09, DB = 1
N4.C1.D1.R1.S03: PI = 035, PtrOffset = 005
N6.C0.S17: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 5
N0.C0.S06: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N2.C1.D0.R1.S00: RcvEn: plus1 = 1, minus1 = 0, PI = 32, DB = 0
N4.C1.D1.R1.S04: PI = 030, PtrOffset = 005
N6.C0.D0.R0.S00: RcvEn: plus1 = 1, minus1 = 0, PI = 52, DB = 1
N0.C0.S07: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N2.C1.D0.R1.S01: RcvEn: plus1 = 0, minus1 = 1, PI = 14, DB = 1
N4.C1.D1.R1.S05: PI = 055, PtrOffset = 005
N6.C0.D0.R0.S01: RcvEn: plus1 = 1, minus1 = 0, PI = 31, DB = 0
N0.C0.S08: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 5
N2.C1.D0.R1.S02: RcvEn: plus1 = 1, minus1 = 0, PI = 47, DB = 0
N4.C1.D1.R1.S06: PI = 015, PtrOffset = 004
N6.C0.D0.R0.S02: RcvEn: plus1 = 0, minus1 = 1, PI = 01, DB = 1
N0.C0.S09: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N2.C1.D0.R1.S03: RcvEn: plus1 = 1, minus1 = 0, PI = 27, DB = 0
N4.C1.D1.R1.S07: PI = 035, PtrOffset = 004
N6.C0.D0.R0.S03: RcvEn: plus1 = 1, minus1 = 0, PI = 46, DB = 0
N0.C0.S10: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N2.C1.D0.R1.S04: RcvEn: plus1 = 1, minus1 = 0, PI = 20, DB = 0
N4.C1.D1.R1.S08: PI = 018, PtrOffset = 005
N6.C0.D0.R0.S04: RcvEn: plus1 = 1, minus1 = 0, PI = 40, DB = 0
N0.C0.S11: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 5
N2.C1.D0.R1.S05: RcvEn: plus1 = 1, minus1 = 0, PI = 44, DB = 0
N4.C1.D1.R1.S00: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N6.C0.D0.R0.S05: RcvEn: plus1 = 1, minus1 = 0, PI = 60, DB = 1
N0.C0.S12: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 5
N2.C1.D0.R1.S06: RcvEn: plus1 = 0, minus1 = 1, PI = 05, DB = 1
N4.C1.D1.R1.S01: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N6.C0.D0.R0.S06: RcvEn: plus1 = 1, minus1 = 0, PI = 29, DB = 0
N0.C0.S13: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 5
N2.C1.D0.R1.S07: RcvEn: plus1 = 1, minus1 = 0, PI = 26, DB = 0
N4.C1.D1.R1.S02: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N6.C0.D0.R0.S07: RcvEn: plus1 = 1, minus1 = 0, PI = 52, DB = 1
N0.C0.S14: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 5
N2.C1.D0.R1.S08: RcvEn: plus1 = 0, minus1 = 1, PI = 07, DB = 1
N4.C1.D1.R1.S03: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N6.C0.D0.R0.S08: RcvEn: plus1 = 1, minus1 = 0, PI = 35, DB = 0
N0.C0.S15: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N2.C1.D0.R1.S09: RcvEn: plus1 = 1, minus1 = 0, PI = 33, DB = 0
N4.C1.D1.R1.S04: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N6.C0.D0.R0.S09: RcvEn: plus1 = 1, minus1 = 0, PI = 50, DB = 1
N0.C0.S16: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N2.C1.D0.R1.S10: RcvEn: plus1 = 0, minus1 = 1, PI = 13, DB = 1
N4.C1.D1.R1.S05: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N6.C0.D0.R0.S10: RcvEn: plus1 = 1, minus1 = 0, PI = 32, DB = 0
N0.C0.S17: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 5
N2.C1.D0.R1.S11: RcvEn: plus1 = 1, minus1 = 0, PI = 47, DB = 0
N4.C1.D1.R1.S06: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N6.C0.D0.R0.S11: RcvEn: plus1 = 0, minus1 = 1, PI = 01, DB = 1
N0.C0.D0.R0.S00: RcvEn: plus1 = 1, minus1 = 0, PI = 43, DB = 0
N2.C1.D0.R1.S12: RcvEn: plus1 = 1, minus1 = 0, PI = 28, DB = 0
N4.C1.D1.R1.S07: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N6.C0.D0.R0.S12: RcvEn: plus1 = 1, minus1 = 0, PI = 45, DB = 0
N0.C0.D0.R0.S01: RcvEn: plus1 = 1, minus1 = 0, PI = 24, DB = 0
N2.C1.D0.R1.S13: RcvEn: plus1 = 1, minus1 = 0, PI = 19, DB = 0
N4.C1.D1.R1.S08: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N6.C0.D0.R0.S13: RcvEn: plus1 = 1, minus1 = 0, PI = 38, DB = 0
N0.C0.D0.R0.S02: RcvEn: plus1 = 1, minus1 = 0, PI = 59, DB = 1
N2.C1.D0.R1.S14: RcvEn: plus1 = 1, minus1 = 0, PI = 44, DB = 0
N4.C1.D1.R1.S00: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N6.C0.D0.R0.S14: RcvEn: plus1 = 1, minus1 = 0, PI = 61, DB = 1
N0.C0.D0.R0.S03: RcvEn: plus1 = 1, minus1 = 0, PI = 40, DB = 0
N2.C1.D0.R1.S15: RcvEn: plus1 = 0, minus1 = 1, PI = 08, DB = 1
N4.C1.D1.R1.S01: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N6.C0.D0.R0.S15: RcvEn: plus1 = 1, minus1 = 0, PI = 28, DB = 0
N0.C0.D0.R0.S04: RcvEn: plus1 = 1, minus1 = 0, PI = 31, DB = 0
N2.C1.D0.R1.S16: RcvEn: plus1 = 1, minus1 = 0, PI = 27, DB = 0
N4.C1.D1.R1.S02: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N6.C0.D0.R0.S16: RcvEn: plus1 = 1, minus1 = 0, PI = 49, DB = 1
N0.C0.D0.R0.S05: RcvEn: plus1 = 1, minus1 = 0, PI = 52, DB = 1
N2.C1.D0.R1.S17: RcvEn: plus1 = 0, minus1 = 1, PI = 09, DB = 1
N4.C1.D1.R1.S03: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N6.C0.D0.R0.S17: RcvEn: plus1 = 1, minus1 = 0, PI = 32, DB = 0
N0.C0.D0.R0.S06: RcvEn: plus1 = 1, minus1 = 0, PI = 26, DB = 0
N2.C1.D1.R0.S00: RcvEn: plus1 = 1, minus1 = 0, PI = 17, DB = 0
N4.C1.D1.R1.S04: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N6.C0.D0.R1.S00: RcvEn: plus1 = 1, minus1 = 0, PI = 52, DB = 1
N0.C0.D0.R0.S07: RcvEn: plus1 = 1, minus1 = 0, PI = 44, DB = 0
N2.C1.D1.R0.S01: RcvEn: plus1 = 1, minus1 = 0, PI = 61, DB = 1
N4.C1.D1.R1.S05: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N6.C0.D0.R1.S01: RcvEn: plus1 = 1, minus1 = 0, PI = 31, DB = 0
N0.C0.D0.R0.S08: RcvEn: plus1 = 1, minus1 = 0, PI = 27, DB = 0
N2.C1.D1.R0.S02: RcvEn: plus1 = 1, minus1 = 0, PI = 32, DB = 0
N4.C1.D1.R1.S06: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N6.C0.D0.R1.S02: RcvEn: plus1 = 0, minus1 = 1, PI = 01, DB = 1
N0.C0.D0.R0.S09: RcvEn: plus1 = 1, minus1 = 0, PI = 42, DB = 0
N2.C1.D1.R0.S03: RcvEn: plus1 = 1, minus1 = 0, PI = 11, DB = 1
N4.C1.D1.R1.S07: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N6.C0.D0.R1.S03: RcvEn: plus1 = 1, minus1 = 0, PI = 46, DB = 0
N0.C0.D0.R0.S10: RcvEn: plus1 = 1, minus1 = 0, PI = 23, DB = 0
N2.C1.D1.R0.S04: RcvEn: plus1 = 1, minus1 = 0, PI = 04, DB = 1
N4.C1.D1.R1.S08: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N6.C0.D0.R1.S04: RcvEn: plus1 = 1, minus1 = 0, PI = 40, DB = 0
N0.C0.D0.R0.S11: RcvEn: plus1 = 1, minus1 = 0, PI = 58, DB = 1
N2.C1.D1.R0.S05: RcvEn: plus1 = 1, minus1 = 0, PI = 31, DB = 0
N4.C1.D1.R1.S00: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N6.C0.D0.R1.S05: RcvEn: plus1 = 1, minus1 = 0, PI = 60, DB = 1
N0.C0.D0.R0.S12: RcvEn: plus1 = 1, minus1 = 0, PI = 38, DB = 0
N2.C1.D1.R0.S06: RcvEn: plus1 = 1, minus1 = 0, PI = 54, DB = 1
N4.C1.D1.R1.S01: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N6.C0.D0.R1.S06: RcvEn: plus1 = 1, minus1 = 0, PI = 29, DB = 0
N0.C0.D0.R0.S13: RcvEn: plus1 = 1, minus1 = 0, PI = 30, DB = 0
N2.C1.D1.R0.S07: RcvEn: plus1 = 1, minus1 = 0, PI = 10, DB = 1
N4.C1.D1.R1.S02: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N6.C0.D0.R1.S07: RcvEn: plus1 = 1, minus1 = 0, PI = 52, DB = 1
N0.C0.D0.R0.S14: RcvEn: plus1 = 1, minus1 = 0, PI = 52, DB = 1
N2.C1.D1.R0.S08: RcvEn: plus1 = 1, minus1 = 0, PI = 56, DB = 1
N4.C1.D1.R1.S03: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N6.C0.D0.R1.S08: RcvEn: plus1 = 1, minus1 = 0, PI = 35, DB = 0
N0.C0.D0.R0.S15: RcvEn: plus1 = 1, minus1 = 0, PI = 23, DB = 0
N2.C1.D1.R0.S09: RcvEn: plus1 = 1, minus1 = 0, PI = 19, DB = 0
N4.C1.D1.R1.S04: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N6.C0.D0.R1.S09: RcvEn: plus1 = 1, minus1 = 0, PI = 50, DB = 1
N0.C0.D0.R0.S16: RcvEn: plus1 = 1, minus1 = 0, PI = 45, DB = 0
N2.C1.D1.R0.S10: RcvEn: plus1 = 1, minus1 = 0, PI = 63, DB = 1
N4.C1.D1.R1.S05: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N6.C0.D0.R1.S10: RcvEn: plus1 = 1, minus1 = 0, PI = 32, DB = 0
N0.C0.D0.R0.S17: RcvEn: plus1 = 1, minus1 = 0, PI = 25, DB = 0
N2.C1.D1.R0.S11: RcvEn: plus1 = 1, minus1 = 0, PI = 32, DB = 0
N4.C1.D1.R1.S06: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N6.C0.D0.R1.S11: RcvEn: plus1 = 0, minus1 = 1, PI = 01, DB = 1
N0.C0.D0.R1.S00: RcvEn: plus1 = 1, minus1 = 0, PI = 43, DB = 0
N2.C1.D1.R0.S12: RcvEn: plus1 = 1, minus1 = 0, PI = 13, DB = 1
N4.C1.D1.R1.S07: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N6.C0.D0.R1.S12: RcvEn: plus1 = 1, minus1 = 0, PI = 45, DB = 0
N0.C0.D0.R1.S01: RcvEn: plus1 = 1, minus1 = 0, PI = 24, DB = 0
N2.C1.D1.R0.S13: RcvEn: plus1 = 1, minus1 = 0, PI = 04, DB = 1
N4.C1.D1.R1.S08: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N6.C0.D0.R1.S13: RcvEn: plus1 = 1, minus1 = 0, PI = 38, DB = 0
N0.C0.D0.R1.S02: RcvEn: plus1 = 1, minus1 = 0, PI = 59, DB = 1
N2.C1.D1.R0.S14: RcvEn: plus1 = 1, minus1 = 0, PI = 29, DB = 0
N4.C1.D1.R1.S00: Preamble found at Latency = 008
N6.C0.D0.R1.S14: RcvEn: plus1 = 1, minus1 = 0, PI = 61, DB = 1
N0.C0.D0.R1.S03: RcvEn: plus1 = 1, minus1 = 0, PI = 40, DB = 0
N2.C1.D1.R0.S15: RcvEn: plus1 = 1, minus1 = 0, PI = 55, DB = 1
N4.C1.D1.R1.S01: Preamble found at Latency = 008
N6.C0.D0.R1.S15: RcvEn: plus1 = 1, minus1 = 0, PI = 28, DB = 0
N0.C0.D0.R1.S04: RcvEn: plus1 = 1, minus1 = 0, PI = 31, DB = 0
N2.C1.D1.R0.S16: RcvEn: plus1 = 1, minus1 = 0, PI = 11, DB = 1
N4.C1.D1.R1.S06: Preamble found at Latency = 008
N6.C0.D0.R1.S16: RcvEn: plus1 = 1, minus1 = 0, PI = 49, DB = 1
N0.C0.D0.R1.S05: RcvEn: plus1 = 1, minus1 = 0, PI = 52, DB = 1
N2.C1.D1.R0.S17: RcvEn: plus1 = 1, minus1 = 0, PI = 57, DB = 1
N4.C1.D1.R1.S07: Preamble found at Latency = 008
N6.C0.D0.R1.S17: RcvEn: plus1 = 1, minus1 = 0, PI = 32, DB = 0
N0.C0.D0.R1.S06: RcvEn: plus1 = 1, minus1 = 0, PI = 26, DB = 0
N2.C1.D1.R1.S00: RcvEn: plus1 = 1, minus1 = 0, PI = 17, DB = 0
N4.C1.D1.R1.S00: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N6.C0.D1.R0.S00: RcvEn: plus1 = 1, minus1 = 0, PI = 35, DB = 0
N0.C0.D0.R1.S07: RcvEn: plus1 = 1, minus1 = 0, PI = 44, DB = 0
N2.C1.D1.R1.S01: RcvEn: plus1 = 1, minus1 = 0, PI = 61, DB = 1
N4.C1.D1.R1.S01: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N6.C0.D1.R0.S01: RcvEn: plus1 = 1, minus1 = 0, PI = 14, DB = 1
N0.C0.D0.R1.S08: RcvEn: plus1 = 1, minus1 = 0, PI = 27, DB = 0
N2.C1.D1.R1.S02: RcvEn: plus1 = 1, minus1 = 0, PI = 32, DB = 0
N4.C1.D1.R1.S02: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N6.C0.D1.R0.S02: RcvEn: plus1 = 1, minus1 = 0, PI = 48, DB = 0
N0.C0.D0.R1.S09: RcvEn: plus1 = 1, minus1 = 0, PI = 42, DB = 0
N2.C1.D1.R1.S03: RcvEn: plus1 = 1, minus1 = 0, PI = 11, DB = 1
N4.C1.D1.R1.S03: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N6.C0.D1.R0.S03: RcvEn: plus1 = 1, minus1 = 0, PI = 28, DB = 0
N0.C0.D0.R1.S10: RcvEn: plus1 = 1, minus1 = 0, PI = 23, DB = 0
N2.C1.D1.R1.S04: RcvEn: plus1 = 1, minus1 = 0, PI = 04, DB = 1
N4.C1.D1.R1.S04: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N6.C0.D1.R0.S04: RcvEn: plus1 = 1, minus1 = 0, PI = 22, DB = 0
N0.C0.D0.R1.S11: RcvEn: plus1 = 1, minus1 = 0, PI = 58, DB = 1
N2.C1.D1.R1.S05: RcvEn: plus1 = 1, minus1 = 0, PI = 31, DB = 0
N4.C1.D1.R1.S05: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N6.C0.D1.R0.S05: RcvEn: plus1 = 1, minus1 = 0, PI = 43, DB = 0
N0.C0.D0.R1.S12: RcvEn: plus1 = 1, minus1 = 0, PI = 38, DB = 0
N2.C1.D1.R1.S06: RcvEn: plus1 = 1, minus1 = 0, PI = 54, DB = 1
N4.C1.D1.R1.S06: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N6.C0.D1.R0.S06: RcvEn: plus1 = 1, minus1 = 0, PI = 13, DB = 1
N0.C0.D0.R1.S13: RcvEn: plus1 = 1, minus1 = 0, PI = 30, DB = 0
N2.C1.D1.R1.S07: RcvEn: plus1 = 1, minus1 = 0, PI = 10, DB = 1
N4.C1.D1.R1.S07: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N6.C0.D1.R0.S07: RcvEn: plus1 = 1, minus1 = 0, PI = 36, DB = 0
N0.C0.D0.R1.S14: RcvEn: plus1 = 1, minus1 = 0, PI = 52, DB = 1
N2.C1.D1.R1.S08: RcvEn: plus1 = 1, minus1 = 0, PI = 56, DB = 1
N4.C1.D1.R1.S08: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N6.C0.D1.R0.S08: RcvEn: plus1 = 1, minus1 = 0, PI = 18, DB = 0
N0.C0.D0.R1.S15: RcvEn: plus1 = 1, minus1 = 0, PI = 23, DB = 0
N2.C1.D1.R1.S09: RcvEn: plus1 = 1, minus1 = 0, PI = 19, DB = 0
N4.C1.D1.R1.S02: Preamble found at Latency = 007
N6.C0.D1.R0.S09: RcvEn: plus1 = 1, minus1 = 0, PI = 34, DB = 0
N0.C0.D0.R1.S16: RcvEn: plus1 = 1, minus1 = 0, PI = 45, DB = 0
N2.C1.D1.R1.S10: RcvEn: plus1 = 1, minus1 = 0, PI = 63, DB = 1
N4.C1.D1.R1.S03: Preamble found at Latency = 007
N6.C0.D1.R0.S10: RcvEn: plus1 = 1, minus1 = 0, PI = 12, DB = 1
N0.C0.D0.R1.S17: RcvEn: plus1 = 1, minus1 = 0, PI = 25, DB = 0
N2.C1.D1.R1.S11: RcvEn: plus1 = 1, minus1 = 0, PI = 32, DB = 0
N4.C1.D1.R1.S04: Preamble found at Latency = 007
N6.C0.D1.R0.S11: RcvEn: plus1 = 1, minus1 = 0, PI = 47, DB = 0
N0.C0.D1.R0.S00: RcvEn: plus1 = 1, minus1 = 0, PI = 28, DB = 0
N2.C1.D1.R1.S12: RcvEn: plus1 = 1, minus1 = 0, PI = 13, DB = 1
N4.C1.D1.R1.S05: Preamble found at Latency = 007
N6.C0.D1.R0.S12: RcvEn: plus1 = 1, minus1 = 0, PI = 29, DB = 0
N0.C0.D1.R0.S01: RcvEn: plus1 = 1, minus1 = 0, PI = 07, DB = 1
N2.C1.D1.R1.S13: RcvEn: plus1 = 1, minus1 = 0, PI = 04, DB = 1
N4.C1.D1.R1.S08: Preamble found at Latency = 007
N6.C0.D1.R0.S13: RcvEn: plus1 = 1, minus1 = 0, PI = 21, DB = 0
N0.C0.D1.R0.S02: RcvEn: plus1 = 1, minus1 = 0, PI = 42, DB = 0
N2.C1.D1.R1.S14: RcvEn: plus1 = 1, minus1 = 0, PI = 29, DB = 0
N4.C1.D1.R1.S00: Total Receive Enable Delay = 1356
N6.C0.D1.R0.S14: RcvEn: plus1 = 1, minus1 = 0, PI = 43, DB = 0
N0.C0.D1.R0.S03: RcvEn: plus1 = 1, minus1 = 0, PI = 21, DB = 0
N2.C1.D1.R1.S15: RcvEn: plus1 = 1, minus1 = 0, PI = 55, DB = 1
N4.C1.D1.R1.S01: Total Receive Enable Delay = 1336
N6.C0.D1.R0.S15: RcvEn: plus1 = 1, minus1 = 0, PI = 10, DB = 1
N0.C0.D1.R0.S04: RcvEn: plus1 = 1, minus1 = 0, PI = 15, DB = 1
N2.C1.D1.R1.S16: RcvEn: plus1 = 1, minus1 = 0, PI = 11, DB = 1
N4.C1.D1.R1.S02: Total Receive Enable Delay = 1306
N6.C0.D1.R0.S16: RcvEn: plus1 = 1, minus1 = 0, PI = 33, DB = 0
N0.C0.D1.R0.S05: RcvEn: plus1 = 1, minus1 = 0, PI = 35, DB = 0
N2.C1.D1.R1.S17: RcvEn: plus1 = 1, minus1 = 0, PI = 57, DB = 1
N4.C1.D1.R1.S03: Total Receive Enable Delay = 1283
N6.C0.D1.R0.S17: RcvEn: plus1 = 1, minus1 = 0, PI = 15, DB = 1
N0.C0.D1.R0.S06: RcvEn: plus1 = 1, minus1 = 0, PI = 08, DB = 1
STOP_DATA_REC_EN
N4.C1.D1.R1.S04: Total Receive Enable Delay = 1278
N6.C0.D1.R1.S00: RcvEn: plus1 = 1, minus1 = 0, PI = 35, DB = 0
N0.C0.D1.R0.S07: RcvEn: plus1 = 1, minus1 = 0, PI = 30, DB = 0
N2.C2.D0.R0: RcvEnFine: Initial RdCmd2RcvEnLatency = 10, Initial RdPtrOffsetRcvEn = 4
N4.C1.D1.R1.S05: Total Receive Enable Delay = 1303
N6.C0.D1.R1.S01: RcvEn: plus1 = 1, minus1 = 0, PI = 14, DB = 1
N0.C0.D1.R0.S08: RcvEn: plus1 = 1, minus1 = 0, PI = 10, DB = 1
N2.C2.D0.R0.S00: Rcv En Fine Value = 273
N4.C1.D1.R1.S06: Total Receive Enable Delay = 1327
N6.C0.D1.R1.S02: RcvEn: plus1 = 1, minus1 = 0, PI = 48, DB = 0
N0.C0.D1.R0.S09: RcvEn: plus1 = 1, minus1 = 0, PI = 25, DB = 0
N2.C2.D0.R0.S01: Rcv En Fine Value = 382
N4.C1.D1.R1.S07: Total Receive Enable Delay = 1347
N6.C0.D1.R1.S03: RcvEn: plus1 = 1, minus1 = 0, PI = 28, DB = 0
N0.C0.D1.R0.S10: RcvEn: plus1 = 1, minus1 = 0, PI = 05, DB = 1
N2.C2.D0.R0.S02: Rcv En Fine Value = 349
N4.C1.D1.R1.S08: Total Receive Enable Delay = 1266
N6.C0.D1.R1.S04: RcvEn: plus1 = 1, minus1 = 0, PI = 22, DB = 0
N0.C0.D1.R0.S11: RcvEn: plus1 = 1, minus1 = 0, PI = 41, DB = 0
N2.C2.D0.R0.S03: Rcv En Fine Value = 330
N4.C1.D1.R1: Starting preamble search upper nibbles
N6.C0.D1.R1.S05: RcvEn: plus1 = 1, minus1 = 0, PI = 43, DB = 0
N0.C0.D1.R0.S12: RcvEn: plus1 = 1, minus1 = 0, PI = 22, DB = 0
N2.C2.D0.R0.S04: Rcv En Fine Value = 330
N4.C1.D1.R1.S09: PI = 045, PtrOffset = 004
N6.C0.D1.R1.S06: RcvEn: plus1 = 1, minus1 = 0, PI = 13, DB = 1
N0.C0.D1.R0.S13: RcvEn: plus1 = 1, minus1 = 0, PI = 13, DB = 1
N2.C2.D0.R0.S05: Rcv En Fine Value = 344
N4.C1.D1.R1.S10: PI = 025, PtrOffset = 004
N6.C0.D1.R1.S07: RcvEn: plus1 = 1, minus1 = 0, PI = 36, DB = 0
N0.C0.D1.R0.S14: RcvEn: plus1 = 1, minus1 = 0, PI = 37, DB = 0
N2.C2.D0.R0.S06: Rcv En Fine Value = 378
N4.C1.D1.R1.S11: PI = 060, PtrOffset = 005
N6.C0.D1.R1.S08: RcvEn: plus1 = 1, minus1 = 0, PI = 18, DB = 0
N0.C0.D1.R0.S15: RcvEn: plus1 = 1, minus1 = 0, PI = 07, DB = 1
N2.C2.D0.R0.S07: Rcv En Fine Value = 271
N4.C1.D1.R1.S12: PI = 040, PtrOffset = 005
N6.C0.D1.R1.S09: RcvEn: plus1 = 1, minus1 = 0, PI = 34, DB = 0
N0.C0.D1.R0.S16: RcvEn: plus1 = 1, minus1 = 0, PI = 29, DB = 0
N2.C2.D0.R0.S08: Rcv En Fine Value = 317
N4.C1.D1.R1.S13: PI = 030, PtrOffset = 005
N6.C0.D1.R1.S10: RcvEn: plus1 = 1, minus1 = 0, PI = 12, DB = 1
N0.C0.D1.R0.S17: RcvEn: plus1 = 1, minus1 = 0, PI = 07, DB = 1
N2.C2.D0.R0.S09: Rcv En Fine Value = 275
N4.C1.D1.R1.S14: PI = 055, PtrOffset = 005
N6.C0.D1.R1.S11: RcvEn: plus1 = 1, minus1 = 0, PI = 47, DB = 0
N0.C0.D1.R1.S00: RcvEn: plus1 = 1, minus1 = 0, PI = 28, DB = 0
N2.C2.D0.R0.S10: Rcv En Fine Value = 379
N4.C1.D1.R1.S15: PI = 017, PtrOffset = 004
N6.C0.D1.R1.S12: RcvEn: plus1 = 1, minus1 = 0, PI = 29, DB = 0
N0.C0.D1.R1.S01: RcvEn: plus1 = 1, minus1 = 0, PI = 07, DB = 1
N2.C2.D0.R0.S11: Rcv En Fine Value = 349
N4.C1.D1.R1.S16: PI = 038, PtrOffset = 004
N6.C0.D1.R1.S13: RcvEn: plus1 = 1, minus1 = 0, PI = 21, DB = 0
N0.C0.D1.R1.S02: RcvEn: plus1 = 1, minus1 = 0, PI = 42, DB = 0
N2.C2.D0.R0.S12: Rcv En Fine Value = 332
N4.C1.D1.R1.S17: PI = 018, PtrOffset = 005
N6.C0.D1.R1.S14: RcvEn: plus1 = 1, minus1 = 0, PI = 43, DB = 0
N0.C0.D1.R1.S03: RcvEn: plus1 = 1, minus1 = 0, PI = 21, DB = 0
N2.C2.D0.R0.S13: Rcv En Fine Value = 329
N4.C1.D1.R1.S09: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N6.C0.D1.R1.S15: RcvEn: plus1 = 1, minus1 = 0, PI = 10, DB = 1
N0.C0.D1.R1.S04: RcvEn: plus1 = 1, minus1 = 0, PI = 15, DB = 1
N2.C2.D0.R0.S14: Rcv En Fine Value = 341
N4.C1.D1.R1.S10: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N6.C0.D1.R1.S16: RcvEn: plus1 = 1, minus1 = 0, PI = 33, DB = 0
N0.C0.D1.R1.S05: RcvEn: plus1 = 1, minus1 = 0, PI = 35, DB = 0
N2.C2.D0.R0.S15: Rcv En Fine Value = 378
N4.C1.D1.R1.S11: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N6.C0.D1.R1.S17: RcvEn: plus1 = 1, minus1 = 0, PI = 15, DB = 1
N0.C0.D1.R1.S06: RcvEn: plus1 = 1, minus1 = 0, PI = 08, DB = 1
N2.C2.D0.R0.S16: Rcv En Fine Value = 270
N4.C1.D1.R1.S12: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
STOP_DATA_REC_EN
N0.C0.D1.R1.S07: RcvEn: plus1 = 1, minus1 = 0, PI = 30, DB = 0
N2.C2.D0.R0.S17: Rcv En Fine Value = 313
N4.C1.D1.R1.S13: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N6.C1.D0.R0: RcvEnFine: Initial RdCmd2RcvEnLatency = 10, Initial RdPtrOffsetRcvEn = 4
N0.C0.D1.R1.S08: RcvEn: plus1 = 1, minus1 = 0, PI = 10, DB = 1
N2.C2.D0.R0: Starting preamble search lower nibbles
N4.C1.D1.R1.S14: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N6.C1.D0.R0.S00: Rcv En Fine Value = 324
N0.C0.D1.R1.S09: RcvEn: plus1 = 1, minus1 = 0, PI = 25, DB = 0
N2.C2.D0.R0.S00: PI = 017, PtrOffset = 004
N4.C1.D1.R1.S15: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N6.C1.D0.R0.S01: Rcv En Fine Value = 303
N0.C0.D1.R1.S10: RcvEn: plus1 = 1, minus1 = 0, PI = 05, DB = 1
N2.C2.D0.R0.S01: PI = 062, PtrOffset = 005
N4.C1.D1.R1.S16: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N6.C1.D0.R0.S02: Rcv En Fine Value = 275
N0.C0.D1.R1.S11: RcvEn: plus1 = 1, minus1 = 0, PI = 41, DB = 0
N2.C2.D0.R0.S02: PI = 029, PtrOffset = 005
N4.C1.D1.R1.S17: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N6.C1.D0.R0.S03: Rcv En Fine Value = 382
N0.C0.D1.R1.S12: RcvEn: plus1 = 1, minus1 = 0, PI = 22, DB = 0
N2.C2.D0.R0.S03: PI = 010, PtrOffset = 005
N4.C1.D1.R1.S09: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N6.C1.D0.R0.S04: Rcv En Fine Value = 373
N0.C0.D1.R1.S13: RcvEn: plus1 = 1, minus1 = 0, PI = 13, DB = 1
N2.C2.D0.R0.S04: PI = 010, PtrOffset = 005
N4.C1.D1.R1.S10: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N6.C1.D0.R0.S05: Rcv En Fine Value = 270
N0.C0.D1.R1.S14: RcvEn: plus1 = 1, minus1 = 0, PI = 37, DB = 0
N2.C2.D0.R0.S05: PI = 024, PtrOffset = 005
N4.C1.D1.R1.S11: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N6.C1.D0.R0.S06: Rcv En Fine Value = 294
N0.C0.D1.R1.S15: RcvEn: plus1 = 1, minus1 = 0, PI = 07, DB = 1
N2.C2.D0.R0.S06: PI = 058, PtrOffset = 005
N4.C1.D1.R1.S12: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N6.C1.D0.R0.S07: Rcv En Fine Value = 316
N0.C0.D1.R1.S16: RcvEn: plus1 = 1, minus1 = 0, PI = 29, DB = 0
N2.C2.D0.R0.S07: PI = 015, PtrOffset = 004
N4.C1.D1.R1.S13: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N6.C1.D0.R0.S08: Rcv En Fine Value = 362
N0.C0.D1.R1.S17: RcvEn: plus1 = 1, minus1 = 0, PI = 07, DB = 1
N2.C2.D0.R0.S08: PI = 061, PtrOffset = 004
N4.C1.D1.R1.S14: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N6.C1.D0.R0.S09: Rcv En Fine Value = 324
STOP_DATA_REC_EN
N2.C2.D0.R0.S00: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N4.C1.D1.R1.S15: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N6.C1.D0.R0.S10: Rcv En Fine Value = 304
N0.C1.D0.R0: RcvEnFine: Initial RdCmd2RcvEnLatency = 10, Initial RdPtrOffsetRcvEn = 4
N2.C2.D0.R0.S01: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N4.C1.D1.R1.S16: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N6.C1.D0.R0.S11: Rcv En Fine Value = 273
N0.C1.D0.R0.S00: Rcv En Fine Value = 320
N2.C2.D0.R0.S02: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N4.C1.D1.R1.S17: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N6.C1.D0.R0.S12: Rcv En Fine Value = 383
N0.C1.D0.R0.S01: Rcv En Fine Value = 296
N2.C2.D0.R0.S03: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N4.C1.D1.R1.S09: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N6.C1.D0.R0.S13: Rcv En Fine Value = 377
N0.C1.D0.R0.S02: Rcv En Fine Value = 267
N2.C2.D0.R0.S04: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N4.C1.D1.R1.S10: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N6.C1.D0.R0.S14: Rcv En Fine Value = 270
N0.C1.D0.R0.S03: Rcv En Fine Value = 378
N2.C2.D0.R0.S05: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N4.C1.D1.R1.S11: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N6.C1.D0.R0.S15: Rcv En Fine Value = 294
N0.C1.D0.R0.S04: Rcv En Fine Value = 367
N2.C2.D0.R0.S06: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N4.C1.D1.R1.S12: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N6.C1.D0.R0.S16: Rcv En Fine Value = 316
N0.C1.D0.R0.S05: Rcv En Fine Value = 267
N2.C2.D0.R0.S07: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N4.C1.D1.R1.S13: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N6.C1.D0.R0.S17: Rcv En Fine Value = 363
N0.C1.D0.R0.S06: Rcv En Fine Value = 287
N2.C2.D0.R0.S08: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N4.C1.D1.R1.S14: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N6.C1.D0.R0: Starting preamble search lower nibbles
N0.C1.D0.R0.S07: Rcv En Fine Value = 312
N2.C2.D0.R0.S00: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N4.C1.D1.R1.S15: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N6.C1.D0.R0.S00: PI = 004, PtrOffset = 005
N0.C1.D0.R0.S08: Rcv En Fine Value = 354
N2.C2.D0.R0.S01: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N4.C1.D1.R1.S16: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N6.C1.D0.R0.S01: PI = 047, PtrOffset = 004
N0.C1.D0.R0.S09: Rcv En Fine Value = 319
N2.C2.D0.R0.S02: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N4.C1.D1.R1.S17: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N6.C1.D0.R0.S02: PI = 019, PtrOffset = 004
N0.C1.D0.R0.S10: Rcv En Fine Value = 297
N2.C2.D0.R0.S03: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N4.C1.D1.R1.S09: Preamble found at Latency = 008
N6.C1.D0.R0.S03: PI = 062, PtrOffset = 005
N0.C1.D0.R0.S11: Rcv En Fine Value = 268
N2.C2.D0.R0.S04: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N4.C1.D1.R1.S10: Preamble found at Latency = 008
N6.C1.D0.R0.S04: PI = 053, PtrOffset = 005
N0.C1.D0.R0.S12: Rcv En Fine Value = 377
N2.C2.D0.R0.S05: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N4.C1.D1.R1.S15: Preamble found at Latency = 008
N6.C1.D0.R0.S05: PI = 014, PtrOffset = 004
N0.C1.D0.R0.S13: Rcv En Fine Value = 367
N2.C2.D0.R0.S06: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N4.C1.D1.R1.S16: Preamble found at Latency = 008
N6.C1.D0.R0.S06: PI = 038, PtrOffset = 004
N0.C1.D0.R0.S14: Rcv En Fine Value = 265
N2.C2.D0.R0.S07: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N4.C1.D1.R1.S09: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N6.C1.D0.R0.S07: PI = 060, PtrOffset = 004
N0.C1.D0.R0.S15: Rcv En Fine Value = 287
N2.C2.D0.R0.S08: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N4.C1.D1.R1.S10: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N6.C1.D0.R0.S08: PI = 042, PtrOffset = 005
N0.C1.D0.R0.S16: Rcv En Fine Value = 311
N2.C2.D0.R0.S00: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N4.C1.D1.R1.S11: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N6.C1.D0.R0.S00: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N0.C1.D0.R0.S17: Rcv En Fine Value = 357
N2.C2.D0.R0.S01: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N4.C1.D1.R1.S12: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N6.C1.D0.R0.S01: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N0.C1.D0.R0: Starting preamble search lower nibbles
N2.C2.D0.R0.S02: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N4.C1.D1.R1.S13: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N6.C1.D0.R0.S02: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N0.C1.D0.R0.S00: PI = 000, PtrOffset = 005
N2.C2.D0.R0.S03: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N4.C1.D1.R1.S14: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N6.C1.D0.R0.S03: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N0.C1.D0.R0.S01: PI = 040, PtrOffset = 004
N2.C2.D0.R0.S04: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N4.C1.D1.R1.S15: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N6.C1.D0.R0.S04: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N0.C1.D0.R0.S02: PI = 011, PtrOffset = 004
N2.C2.D0.R0.S05: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N4.C1.D1.R1.S16: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N6.C1.D0.R0.S05: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N0.C1.D0.R0.S03: PI = 058, PtrOffset = 005
N2.C2.D0.R0.S06: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N4.C1.D1.R1.S17: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N6.C1.D0.R0.S06: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N0.C1.D0.R0.S04: PI = 047, PtrOffset = 005
N2.C2.D0.R0.S07: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N4.C1.D1.R1.S11: Preamble found at Latency = 007
N6.C1.D0.R0.S07: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N0.C1.D0.R0.S05: PI = 011, PtrOffset = 004
N2.C2.D0.R0.S08: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N4.C1.D1.R1.S12: Preamble found at Latency = 007
N6.C1.D0.R0.S08: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N0.C1.D0.R0.S06: PI = 031, PtrOffset = 004
N2.C2.D0.R0.S00: Preamble found at Latency = 008
N4.C1.D1.R1.S13: Preamble found at Latency = 007
N6.C1.D0.R0.S00: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N0.C1.D0.R0.S07: PI = 056, PtrOffset = 004
N2.C2.D0.R0.S07: Preamble found at Latency = 008
N4.C1.D1.R1.S14: Preamble found at Latency = 007
N6.C1.D0.R0.S01: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N0.C1.D0.R0.S08: PI = 034, PtrOffset = 005
N2.C2.D0.R0.S00: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N4.C1.D1.R1.S17: Preamble found at Latency = 007
N6.C1.D0.R0.S02: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N0.C1.D0.R0.S00: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N2.C2.D0.R0.S01: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N4.C1.D1.R1: Preamble found for all upper nibbles, adjusting Pi, Offset to center into preamble
N6.C1.D0.R0.S03: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N0.C1.D0.R0.S01: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N2.C2.D0.R0.S02: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N4.C1.D1.R1.S09: Total Receive Enable Delay = 1357
N6.C1.D0.R0.S04: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N0.C1.D0.R0.S02: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N2.C2.D0.R0.S03: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N4.C1.D1.R1.S10: Total Receive Enable Delay = 1337
N6.C1.D0.R0.S05: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N0.C1.D0.R0.S03: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N2.C2.D0.R0.S04: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N4.C1.D1.R1.S11: Total Receive Enable Delay = 1308
N6.C1.D0.R0.S06: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N0.C1.D0.R0.S04: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N2.C2.D0.R0.S05: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N4.C1.D1.R1.S12: Total Receive Enable Delay = 1288
N6.C1.D0.R0.S07: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N0.C1.D0.R0.S05: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N2.C2.D0.R0.S06: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N4.C1.D1.R1.S13: Total Receive Enable Delay = 1278
N6.C1.D0.R0.S08: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N0.C1.D0.R0.S06: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N2.C2.D0.R0.S07: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N4.C1.D1.R1.S14: Total Receive Enable Delay = 1303
N6.C1.D0.R0.S00: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N0.C1.D0.R0.S07: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N2.C2.D0.R0.S08: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N4.C1.D1.R1.S15: Total Receive Enable Delay = 1329
N6.C1.D0.R0.S01: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N0.C1.D0.R0.S08: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N2.C2.D0.R0.S01: Preamble found at Latency = 007
N4.C1.D1.R1.S16: Total Receive Enable Delay = 1350
N6.C1.D0.R0.S02: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N0.C1.D0.R0.S00: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N2.C2.D0.R0.S02: Preamble found at Latency = 007
N4.C1.D1.R1.S17: Total Receive Enable Delay = 1266
N6.C1.D0.R0.S03: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N0.C1.D0.R0.S01: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N2.C2.D0.R0.S03: Preamble found at Latency = 007
START_DATA_REC_EN
N6.C1.D0.R0.S04: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N0.C1.D0.R0.S02: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N2.C2.D0.R0.S04: Preamble found at Latency = 007
N4.C1.S00: RdCmd2RcvEnLatency = 9, RdPtrOffsetRcvEn = 5
N6.C1.D0.R0.S05: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N0.C1.D0.R0.S03: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N2.C2.D0.R0.S05: Preamble found at Latency = 007
N4.C1.S01: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N6.C1.D0.R0.S06: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N0.C1.D0.R0.S04: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N2.C2.D0.R0.S06: Preamble found at Latency = 007
N4.C1.S02: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N6.C1.D0.R0.S07: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N0.C1.D0.R0.S05: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N2.C2.D0.R0.S08: Preamble found at Latency = 007
N4.C1.S03: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N6.C1.D0.R0.S08: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N0.C1.D0.R0.S06: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N2.C2.D0.R0.S00: Total Receive Enable Delay = 1329
N4.C1.S04: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 5
N6.C1.D0.R0.S00: Preamble found at Latency = 008
N0.C1.D0.R0.S07: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N2.C2.D0.R0.S01: Total Receive Enable Delay = 1310
N4.C1.S05: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N6.C1.D0.R0.S01: Preamble found at Latency = 008
N0.C1.D0.R0.S08: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N2.C2.D0.R0.S02: Total Receive Enable Delay = 1277
N4.C1.S06: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N6.C1.D0.R0.S02: Preamble found at Latency = 008
N0.C1.D0.R0.S00: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N2.C2.D0.R0.S03: Total Receive Enable Delay = 1258
N4.C1.S07: RdCmd2RcvEnLatency = 9, RdPtrOffsetRcvEn = 5
N6.C1.D0.R0.S05: Preamble found at Latency = 008
N0.C1.D0.R0.S01: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N2.C2.D0.R0.S04: Total Receive Enable Delay = 1258
N4.C1.S08: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 5
N6.C1.D0.R0.S06: Preamble found at Latency = 008
N0.C1.D0.R0.S02: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N2.C2.D0.R0.S05: Total Receive Enable Delay = 1272
N4.C1.S09: RdCmd2RcvEnLatency = 9, RdPtrOffsetRcvEn = 5
N6.C1.D0.R0.S07: Preamble found at Latency = 008
N0.C1.D0.R0.S03: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N2.C2.D0.R0.S06: Total Receive Enable Delay = 1306
N4.C1.S10: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N6.C1.D0.R0.S00: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N0.C1.D0.R0.S04: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N2.C2.D0.R0.S07: Total Receive Enable Delay = 1327
N4.C1.S11: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N6.C1.D0.R0.S01: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N0.C1.D0.R0.S05: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N2.C2.D0.R0.S08: Total Receive Enable Delay = 1245
N4.C1.S12: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N6.C1.D0.R0.S02: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N0.C1.D0.R0.S06: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N2.C2.D0.R0: Starting preamble search upper nibbles
N4.C1.S13: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 5
N6.C1.D0.R0.S03: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N0.C1.D0.R0.S07: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N2.C2.D0.R0.S09: PI = 019, PtrOffset = 004
N4.C1.S14: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N6.C1.D0.R0.S04: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N0.C1.D0.R0.S08: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N2.C2.D0.R0.S10: PI = 059, PtrOffset = 005
N4.C1.S15: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N6.C1.D0.R0.S05: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N0.C1.D0.R0.S00: Preamble found at Latency = 008
N2.C2.D0.R0.S11: PI = 029, PtrOffset = 005
N4.C1.S16: RdCmd2RcvEnLatency = 9, RdPtrOffsetRcvEn = 5
N6.C1.D0.R0.S06: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N0.C1.D0.R0.S01: Preamble found at Latency = 008
N2.C2.D0.R0.S12: PI = 012, PtrOffset = 005
N4.C1.S17: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 5
N6.C1.D0.R0.S07: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N0.C1.D0.R0.S02: Preamble found at Latency = 008
N2.C2.D0.R0.S13: PI = 009, PtrOffset = 005
N4.C1.D0.R0.S00: RcvEn: plus1 = 1, minus1 = 0, PI = 29, DB = 0
N6.C1.D0.R0.S08: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N0.C1.D0.R0.S05: Preamble found at Latency = 008
N2.C2.D0.R0.S14: PI = 021, PtrOffset = 005
N4.C1.D0.R0.S01: RcvEn: plus1 = 0, minus1 = 1, PI = 07, DB = 1
N6.C1.D0.R0.S03: Preamble found at Latency = 007
N0.C1.D0.R0.S06: Preamble found at Latency = 008
N2.C2.D0.R0.S15: PI = 058, PtrOffset = 005
N4.C1.D0.R0.S02: RcvEn: plus1 = 1, minus1 = 0, PI = 42, DB = 0
N6.C1.D0.R0.S04: Preamble found at Latency = 007
N0.C1.D0.R0.S07: Preamble found at Latency = 008
N2.C2.D0.R0.S16: PI = 014, PtrOffset = 004
N4.C1.D0.R0.S03: RcvEn: plus1 = 1, minus1 = 0, PI = 22, DB = 0
N6.C1.D0.R0.S08: Preamble found at Latency = 007
N0.C1.D0.R0.S00: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N2.C2.D0.R0.S17: PI = 057, PtrOffset = 004
N4.C1.D0.R0.S04: RcvEn: plus1 = 0, minus1 = 1, PI = 17, DB = 0
N6.C1.D0.R0.S00: Total Receive Enable Delay = 1380
N0.C1.D0.R0.S01: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N2.C2.D0.R0.S09: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N4.C1.D0.R0.S05: RcvEn: plus1 = 1, minus1 = 0, PI = 40, DB = 0
N6.C1.D0.R0.S01: Total Receive Enable Delay = 1359
N0.C1.D0.R0.S02: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N2.C2.D0.R0.S10: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N4.C1.D0.R0.S06: RcvEn: plus1 = 0, minus1 = 1, PI = 00, DB = 1
N6.C1.D0.R0.S02: Total Receive Enable Delay = 1331
N0.C1.D0.R0.S03: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N2.C2.D0.R0.S11: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N4.C1.D0.R0.S07: RcvEn: plus1 = 1, minus1 = 0, PI = 19, DB = 0
N6.C1.D0.R0.S03: Total Receive Enable Delay = 1310
N0.C1.D0.R0.S04: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N2.C2.D0.R0.S12: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N4.C1.D0.R0.S08: RcvEn: plus1 = 0, minus1 = 1, PI = 03, DB = 1
N6.C1.D0.R0.S04: Total Receive Enable Delay = 1301
N0.C1.D0.R0.S05: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N2.C2.D0.R0.S13: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N4.C1.D0.R0.S09: RcvEn: plus1 = 1, minus1 = 0, PI = 29, DB = 0
N6.C1.D0.R0.S05: Total Receive Enable Delay = 1326
N0.C1.D0.R0.S06: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N2.C2.D0.R0.S14: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N4.C1.D0.R0.S10: RcvEn: plus1 = 0, minus1 = 1, PI = 09, DB = 1
N6.C1.D0.R0.S06: Total Receive Enable Delay = 1350
N0.C1.D0.R0.S07: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N2.C2.D0.R0.S15: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N4.C1.D0.R0.S11: RcvEn: plus1 = 1, minus1 = 0, PI = 43, DB = 0
N6.C1.D0.R0.S07: Total Receive Enable Delay = 1372
N0.C1.D0.R0.S08: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N2.C2.D0.R0.S16: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N4.C1.D0.R0.S12: RcvEn: plus1 = 1, minus1 = 0, PI = 24, DB = 0
N6.C1.D0.R0.S08: Total Receive Enable Delay = 1290
N0.C1.D0.R0.S03: Preamble found at Latency = 007
N2.C2.D0.R0.S17: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N4.C1.D0.R0.S13: RcvEn: plus1 = 0, minus1 = 1, PI = 16, DB = 0
N6.C1.D0.R0: Starting preamble search upper nibbles
N0.C1.D0.R0.S04: Preamble found at Latency = 007
N2.C2.D0.R0.S09: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N4.C1.D0.R0.S14: RcvEn: plus1 = 1, minus1 = 0, PI = 40, DB = 0
N6.C1.D0.R0.S09: PI = 004, PtrOffset = 005
N0.C1.D0.R0.S08: Preamble found at Latency = 007
N2.C2.D0.R0.S10: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N4.C1.D0.R0.S15: RcvEn: plus1 = 0, minus1 = 1, PI = 02, DB = 1
N6.C1.D0.R0.S10: PI = 048, PtrOffset = 004
N0.C1.D0.R0.S00: Total Receive Enable Delay = 1376
N2.C2.D0.R0.S11: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N4.C1.D0.R0.S16: RcvEn: plus1 = 1, minus1 = 0, PI = 20, DB = 0
N6.C1.D0.R0.S11: PI = 017, PtrOffset = 004
N0.C1.D0.R0.S01: Total Receive Enable Delay = 1352
N2.C2.D0.R0.S12: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N4.C1.D0.R0.S17: RcvEn: plus1 = 0, minus1 = 1, PI = 03, DB = 1
N6.C1.D0.R0.S12: PI = 063, PtrOffset = 005
N0.C1.D0.R0.S02: Total Receive Enable Delay = 1323
N2.C2.D0.R0.S13: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N4.C1.D0.R1.S00: RcvEn: plus1 = 1, minus1 = 0, PI = 29, DB = 0
N6.C1.D0.R0.S13: PI = 057, PtrOffset = 005
N0.C1.D0.R0.S03: Total Receive Enable Delay = 1306
N2.C2.D0.R0.S14: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N4.C1.D0.R1.S01: RcvEn: plus1 = 0, minus1 = 1, PI = 07, DB = 1
N6.C1.D0.R0.S14: PI = 014, PtrOffset = 004
N0.C1.D0.R0.S04: Total Receive Enable Delay = 1295
N2.C2.D0.R0.S15: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N4.C1.D0.R1.S02: RcvEn: plus1 = 1, minus1 = 0, PI = 42, DB = 0
N6.C1.D0.R0.S15: PI = 038, PtrOffset = 004
N0.C1.D0.R0.S05: Total Receive Enable Delay = 1323
N2.C2.D0.R0.S16: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N4.C1.D0.R1.S03: RcvEn: plus1 = 1, minus1 = 0, PI = 22, DB = 0
N6.C1.D0.R0.S16: PI = 060, PtrOffset = 004
N0.C1.D0.R0.S06: Total Receive Enable Delay = 1343
N2.C2.D0.R0.S17: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N4.C1.D0.R1.S04: RcvEn: plus1 = 0, minus1 = 1, PI = 17, DB = 0
N6.C1.D0.R0.S17: PI = 043, PtrOffset = 005
N0.C1.D0.R0.S07: Total Receive Enable Delay = 1368
N2.C2.D0.R0.S09: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N4.C1.D0.R1.S05: RcvEn: plus1 = 1, minus1 = 0, PI = 40, DB = 0
N6.C1.D0.R0.S09: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N0.C1.D0.R0.S08: Total Receive Enable Delay = 1282
N2.C2.D0.R0.S10: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N4.C1.D0.R1.S06: RcvEn: plus1 = 0, minus1 = 1, PI = 00, DB = 1
N6.C1.D0.R0.S10: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N0.C1.D0.R0: Starting preamble search upper nibbles
N2.C2.D0.R0.S11: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N4.C1.D0.R1.S07: RcvEn: plus1 = 1, minus1 = 0, PI = 19, DB = 0
N6.C1.D0.R0.S11: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N0.C1.D0.R0.S09: PI = 063, PtrOffset = 004
N2.C2.D0.R0.S12: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N4.C1.D0.R1.S08: RcvEn: plus1 = 0, minus1 = 1, PI = 03, DB = 1
N6.C1.D0.R0.S12: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N0.C1.D0.R0.S10: PI = 041, PtrOffset = 004
N2.C2.D0.R0.S13: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N4.C1.D0.R1.S09: RcvEn: plus1 = 1, minus1 = 0, PI = 29, DB = 0
N6.C1.D0.R0.S13: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N0.C1.D0.R0.S11: PI = 012, PtrOffset = 004
N2.C2.D0.R0.S14: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N4.C1.D0.R1.S10: RcvEn: plus1 = 0, minus1 = 1, PI = 09, DB = 1
N6.C1.D0.R0.S14: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N0.C1.D0.R0.S12: PI = 057, PtrOffset = 005
N2.C2.D0.R0.S15: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N4.C1.D0.R1.S11: RcvEn: plus1 = 1, minus1 = 0, PI = 43, DB = 0
N6.C1.D0.R0.S15: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N0.C1.D0.R0.S13: PI = 047, PtrOffset = 005
N2.C2.D0.R0.S16: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N4.C1.D0.R1.S12: RcvEn: plus1 = 1, minus1 = 0, PI = 24, DB = 0
N6.C1.D0.R0.S16: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N0.C1.D0.R0.S14: PI = 009, PtrOffset = 004
N2.C2.D0.R0.S17: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N4.C1.D0.R1.S13: RcvEn: plus1 = 0, minus1 = 1, PI = 16, DB = 0
N6.C1.D0.R0.S17: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N0.C1.D0.R0.S15: PI = 031, PtrOffset = 004
N2.C2.D0.R0.S09: Preamble found at Latency = 008
N4.C1.D0.R1.S14: RcvEn: plus1 = 1, minus1 = 0, PI = 40, DB = 0
N6.C1.D0.R0.S09: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N0.C1.D0.R0.S16: PI = 055, PtrOffset = 004
N2.C2.D0.R0.S16: Preamble found at Latency = 008
N4.C1.D0.R1.S15: RcvEn: plus1 = 0, minus1 = 1, PI = 02, DB = 1
N6.C1.D0.R0.S10: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N0.C1.D0.R0.S17: PI = 037, PtrOffset = 005
N2.C2.D0.R0.S09: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N4.C1.D0.R1.S16: RcvEn: plus1 = 1, minus1 = 0, PI = 20, DB = 0
N6.C1.D0.R0.S11: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N0.C1.D0.R0.S09: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N2.C2.D0.R0.S10: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N4.C1.D0.R1.S17: RcvEn: plus1 = 0, minus1 = 1, PI = 03, DB = 1
N6.C1.D0.R0.S12: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N0.C1.D0.R0.S10: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N2.C2.D0.R0.S11: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N4.C1.D1.R0.S00: RcvEn: plus1 = 1, minus1 = 0, PI = 12, DB = 1
N6.C1.D0.R0.S13: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N0.C1.D0.R0.S11: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N2.C2.D0.R0.S12: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N4.C1.D1.R0.S01: RcvEn: plus1 = 1, minus1 = 0, PI = 55, DB = 1
N6.C1.D0.R0.S14: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N0.C1.D0.R0.S12: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N2.C2.D0.R0.S13: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N4.C1.D1.R0.S02: RcvEn: plus1 = 1, minus1 = 0, PI = 26, DB = 0
N6.C1.D0.R0.S15: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N0.C1.D0.R0.S13: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N2.C2.D0.R0.S14: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N4.C1.D1.R0.S03: RcvEn: plus1 = 1, minus1 = 0, PI = 03, DB = 1
N6.C1.D0.R0.S16: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N0.C1.D0.R0.S14: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N2.C2.D0.R0.S15: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N4.C1.D1.R0.S04: RcvEn: plus1 = 1, minus1 = 0, PI = 62, DB = 1
N6.C1.D0.R0.S17: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N0.C1.D0.R0.S15: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N2.C2.D0.R0.S16: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N4.C1.D1.R0.S05: RcvEn: plus1 = 1, minus1 = 0, PI = 24, DB = 0
N6.C1.D0.R0.S09: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N0.C1.D0.R0.S16: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N2.C2.D0.R0.S17: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N4.C1.D1.R0.S06: RcvEn: plus1 = 1, minus1 = 0, PI = 47, DB = 0
N6.C1.D0.R0.S10: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N0.C1.D0.R0.S17: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N2.C2.D0.R0.S10: Preamble found at Latency = 007
N4.C1.D1.R0.S07: RcvEn: plus1 = 1, minus1 = 0, PI = 02, DB = 1
N6.C1.D0.R0.S11: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N0.C1.D0.R0.S09: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N2.C2.D0.R0.S11: Preamble found at Latency = 007
N4.C1.D1.R0.S08: RcvEn: plus1 = 1, minus1 = 0, PI = 49, DB = 1
N6.C1.D0.R0.S12: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N0.C1.D0.R0.S10: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N2.C2.D0.R0.S12: Preamble found at Latency = 007
N4.C1.D1.R0.S09: RcvEn: plus1 = 1, minus1 = 0, PI = 13, DB = 1
N6.C1.D0.R0.S13: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N0.C1.D0.R0.S11: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N2.C2.D0.R0.S13: Preamble found at Latency = 007
N4.C1.D1.R0.S10: RcvEn: plus1 = 1, minus1 = 0, PI = 56, DB = 1
N6.C1.D0.R0.S14: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N0.C1.D0.R0.S12: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N2.C2.D0.R0.S14: Preamble found at Latency = 007
N4.C1.D1.R0.S11: RcvEn: plus1 = 1, minus1 = 0, PI = 29, DB = 0
N6.C1.D0.R0.S15: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N0.C1.D0.R0.S13: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N2.C2.D0.R0.S15: Preamble found at Latency = 007
N4.C1.D1.R0.S12: RcvEn: plus1 = 1, minus1 = 0, PI = 07, DB = 1
N6.C1.D0.R0.S16: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N0.C1.D0.R0.S14: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N2.C2.D0.R0.S17: Preamble found at Latency = 007
N4.C1.D1.R0.S13: RcvEn: plus1 = 1, minus1 = 0, PI = 62, DB = 1
N6.C1.D0.R0.S17: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N0.C1.D0.R0.S15: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N2.C2.D0.R0: Preamble found for all upper nibbles, adjusting Pi, Offset to center into preamble
N4.C1.D1.R0.S14: RcvEn: plus1 = 1, minus1 = 0, PI = 23, DB = 0
N6.C1.D0.R0.S09: Preamble found at Latency = 008
N0.C1.D0.R0.S16: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N2.C2.D0.R0.S09: Total Receive Enable Delay = 1331
N4.C1.D1.R0.S15: RcvEn: plus1 = 1, minus1 = 0, PI = 49, DB = 1
N6.C1.D0.R0.S10: Preamble found at Latency = 008
N0.C1.D0.R0.S17: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N2.C2.D0.R0.S10: Total Receive Enable Delay = 1307
N4.C1.D1.R0.S16: RcvEn: plus1 = 1, minus1 = 0, PI = 06, DB = 1
N6.C1.D0.R0.S11: Preamble found at Latency = 008
N0.C1.D0.R0.S09: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N2.C2.D0.R0.S11: Total Receive Enable Delay = 1277
N4.C1.D1.R0.S17: RcvEn: plus1 = 1, minus1 = 0, PI = 50, DB = 1
N6.C1.D0.R0.S14: Preamble found at Latency = 008
N0.C1.D0.R0.S10: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N2.C2.D0.R0.S12: Total Receive Enable Delay = 1260
N4.C1.D1.R1.S00: RcvEn: plus1 = 1, minus1 = 0, PI = 12, DB = 1
N6.C1.D0.R0.S15: Preamble found at Latency = 008
N0.C1.D0.R0.S11: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N2.C2.D0.R0.S13: Total Receive Enable Delay = 1257
N4.C1.D1.R1.S01: RcvEn: plus1 = 1, minus1 = 0, PI = 55, DB = 1
N6.C1.D0.R0.S16: Preamble found at Latency = 008
N0.C1.D0.R0.S12: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N2.C2.D0.R0.S14: Total Receive Enable Delay = 1269
N4.C1.D1.R1.S02: RcvEn: plus1 = 1, minus1 = 0, PI = 26, DB = 0
N6.C1.D0.R0.S09: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N0.C1.D0.R0.S13: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N2.C2.D0.R0.S15: Total Receive Enable Delay = 1306
N4.C1.D1.R1.S03: RcvEn: plus1 = 1, minus1 = 0, PI = 03, DB = 1
N6.C1.D0.R0.S10: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N0.C1.D0.R0.S14: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N2.C2.D0.R0.S16: Total Receive Enable Delay = 1326
N4.C1.D1.R1.S04: RcvEn: plus1 = 1, minus1 = 0, PI = 62, DB = 1
N6.C1.D0.R0.S11: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N0.C1.D0.R0.S15: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N2.C2.D0.R0.S17: Total Receive Enable Delay = 1241
N4.C1.D1.R1.S05: RcvEn: plus1 = 1, minus1 = 0, PI = 24, DB = 0
N6.C1.D0.R0.S12: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N0.C1.D0.R0.S16: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N2.C2.D0.R1: RcvEnFine: Initial RdCmd2RcvEnLatency = 10, Initial RdPtrOffsetRcvEn = 4
N4.C1.D1.R1.S06: RcvEn: plus1 = 1, minus1 = 0, PI = 47, DB = 0
N6.C1.D0.R0.S13: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N0.C1.D0.R0.S17: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N2.C2.D0.R1.S00: Rcv En Fine Value = 275
N4.C1.D1.R1.S07: RcvEn: plus1 = 1, minus1 = 0, PI = 02, DB = 1
N6.C1.D0.R0.S14: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N0.C1.D0.R0.S09: Preamble found at Latency = 008
N2.C2.D0.R1.S01: Rcv En Fine Value = 380
N4.C1.D1.R1.S08: RcvEn: plus1 = 1, minus1 = 0, PI = 49, DB = 1
N6.C1.D0.R0.S15: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N0.C1.D0.R0.S10: Preamble found at Latency = 008
N2.C2.D0.R1.S02: Rcv En Fine Value = 349
N4.C1.D1.R1.S09: RcvEn: plus1 = 1, minus1 = 0, PI = 13, DB = 1
N6.C1.D0.R0.S16: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N0.C1.D0.R0.S11: Preamble found at Latency = 008
N2.C2.D0.R1.S03: Rcv En Fine Value = 331
N4.C1.D1.R1.S10: RcvEn: plus1 = 1, minus1 = 0, PI = 56, DB = 1
N6.C1.D0.R0.S17: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N0.C1.D0.R0.S14: Preamble found at Latency = 008
N2.C2.D0.R1.S04: Rcv En Fine Value = 330
N4.C1.D1.R1.S11: RcvEn: plus1 = 1, minus1 = 0, PI = 29, DB = 0
N6.C1.D0.R0.S12: Preamble found at Latency = 007
N0.C1.D0.R0.S15: Preamble found at Latency = 008
N2.C2.D0.R1.S05: Rcv En Fine Value = 343
N4.C1.D1.R1.S12: RcvEn: plus1 = 1, minus1 = 0, PI = 07, DB = 1
N6.C1.D0.R0.S13: Preamble found at Latency = 007
N0.C1.D0.R0.S16: Preamble found at Latency = 008
N2.C2.D0.R1.S06: Rcv En Fine Value = 381
N4.C1.D1.R1.S13: RcvEn: plus1 = 1, minus1 = 0, PI = 62, DB = 1
N6.C1.D0.R0.S17: Preamble found at Latency = 007
N0.C1.D0.R0.S09: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N2.C2.D0.R1.S07: Rcv En Fine Value = 269
N4.C1.D1.R1.S14: RcvEn: plus1 = 1, minus1 = 0, PI = 23, DB = 0
N6.C1.D0.R0: Preamble found for all upper nibbles, adjusting Pi, Offset to center into preamble
N0.C1.D0.R0.S10: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N2.C2.D0.R1.S08: Rcv En Fine Value = 318
N4.C1.D1.R1.S15: RcvEn: plus1 = 1, minus1 = 0, PI = 49, DB = 1
N6.C1.D0.R0.S09: Total Receive Enable Delay = 1380
N0.C1.D0.R0.S11: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N2.C2.D0.R1.S09: Rcv En Fine Value = 273
N4.C1.D1.R1.S16: RcvEn: plus1 = 1, minus1 = 0, PI = 06, DB = 1
N6.C1.D0.R0.S10: Total Receive Enable Delay = 1360
N0.C1.D0.R0.S12: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N2.C2.D0.R1.S10: Rcv En Fine Value = 381
N4.C1.D1.R1.S17: RcvEn: plus1 = 1, minus1 = 0, PI = 50, DB = 1
N6.C1.D0.R0.S11: Total Receive Enable Delay = 1329
N0.C1.D0.R0.S13: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N2.C2.D0.R1.S11: Rcv En Fine Value = 349
STOP_DATA_REC_EN
N6.C1.D0.R0.S12: Total Receive Enable Delay = 1311
N0.C1.D0.R0.S14: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N2.C2.D0.R1.S12: Rcv En Fine Value = 331
N4.C2.D0.R0: RcvEnFine: Initial RdCmd2RcvEnLatency = 10, Initial RdPtrOffsetRcvEn = 4
N6.C1.D0.R0.S13: Total Receive Enable Delay = 1305
N0.C1.D0.R0.S15: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N2.C2.D0.R1.S13: Rcv En Fine Value = 331
N4.C2.D0.R0.S00: Rcv En Fine Value = 270
N6.C1.D0.R0.S14: Total Receive Enable Delay = 1326
N0.C1.D0.R0.S16: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N2.C2.D0.R1.S14: Rcv En Fine Value = 339
N4.C2.D0.R0.S01: Rcv En Fine Value = 375
N6.C1.D0.R0.S15: Total Receive Enable Delay = 1350
N0.C1.D0.R0.S17: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N2.C2.D0.R1.S15: Rcv En Fine Value = 376
N4.C2.D0.R0.S02: Rcv En Fine Value = 348
N6.C1.D0.R0.S16: Total Receive Enable Delay = 1372
N0.C1.D0.R0.S12: Preamble found at Latency = 007
N2.C2.D0.R1.S16: Rcv En Fine Value = 269
N4.C2.D0.R0.S03: Rcv En Fine Value = 325
N6.C1.D0.R0.S17: Total Receive Enable Delay = 1291
N0.C1.D0.R0.S13: Preamble found at Latency = 007
N2.C2.D0.R1.S17: Rcv En Fine Value = 312
N4.C2.D0.R0.S04: Rcv En Fine Value = 326
N6.C1.D0.R1: RcvEnFine: Initial RdCmd2RcvEnLatency = 10, Initial RdPtrOffsetRcvEn = 4
N0.C1.D0.R0.S17: Preamble found at Latency = 007
N2.C2.D0.R1: Starting preamble search lower nibbles
N4.C2.D0.R0.S05: Rcv En Fine Value = 336
N6.C1.D0.R1.S00: Rcv En Fine Value = 325
N0.C1.D0.R0: Preamble found for all upper nibbles, adjusting Pi, Offset to center into preamble
N2.C2.D0.R1.S00: PI = 019, PtrOffset = 004
N4.C2.D0.R0.S06: Rcv En Fine Value = 375
N6.C1.D0.R1.S01: Rcv En Fine Value = 306
N0.C1.D0.R0.S09: Total Receive Enable Delay = 1375
N2.C2.D0.R1.S01: PI = 060, PtrOffset = 005
N4.C2.D0.R0.S07: Rcv En Fine Value = 262
N6.C1.D0.R1.S02: Rcv En Fine Value = 272
N0.C1.D0.R0.S10: Total Receive Enable Delay = 1353
N2.C2.D0.R1.S02: PI = 029, PtrOffset = 005
N4.C2.D0.R0.S08: Rcv En Fine Value = 312
N6.C1.D0.R1.S03: Rcv En Fine Value = 380
N0.C1.D0.R0.S11: Total Receive Enable Delay = 1324
N2.C2.D0.R1.S03: PI = 011, PtrOffset = 005
N4.C2.D0.R0.S09: Rcv En Fine Value = 270
N6.C1.D0.R1.S04: Rcv En Fine Value = 374
N0.C1.D0.R0.S12: Total Receive Enable Delay = 1305
N2.C2.D0.R1.S04: PI = 010, PtrOffset = 005
N4.C2.D0.R0.S10: Rcv En Fine Value = 375
N6.C1.D0.R1.S05: Rcv En Fine Value = 271
N0.C1.D0.R0.S13: Total Receive Enable Delay = 1295
N2.C2.D0.R1.S05: PI = 023, PtrOffset = 005
N4.C2.D0.R0.S11: Rcv En Fine Value = 342
N6.C1.D0.R1.S06: Rcv En Fine Value = 293
N0.C1.D0.R0.S14: Total Receive Enable Delay = 1321
N2.C2.D0.R1.S06: PI = 061, PtrOffset = 005
N4.C2.D0.R0.S12: Rcv En Fine Value = 324
N6.C1.D0.R1.S07: Rcv En Fine Value = 317
N0.C1.D0.R0.S15: Total Receive Enable Delay = 1343
N2.C2.D0.R1.S07: PI = 013, PtrOffset = 004
N4.C2.D0.R0.S13: Rcv En Fine Value = 324
N6.C1.D0.R1.S08: Rcv En Fine Value = 362
N0.C1.D0.R0.S16: Total Receive Enable Delay = 1367
N2.C2.D0.R1.S08: PI = 062, PtrOffset = 004
N4.C2.D0.R0.S14: Rcv En Fine Value = 340
N6.C1.D0.R1.S09: Rcv En Fine Value = 323
N0.C1.D0.R0.S17: Total Receive Enable Delay = 1285
N2.C2.D0.R1.S00: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N4.C2.D0.R0.S15: Rcv En Fine Value = 375
N6.C1.D0.R1.S10: Rcv En Fine Value = 305
N0.C1.D0.R1: RcvEnFine: Initial RdCmd2RcvEnLatency = 10, Initial RdPtrOffsetRcvEn = 4
N2.C2.D0.R1.S01: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N4.C2.D0.R0.S16: Rcv En Fine Value = 261
N6.C1.D0.R1.S11: Rcv En Fine Value = 271
N0.C1.D0.R1.S00: Rcv En Fine Value = 320
N2.C2.D0.R1.S02: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N4.C2.D0.R0.S17: Rcv En Fine Value = 308
N6.C1.D0.R1.S12: Rcv En Fine Value = 382
N0.C1.D0.R1.S01: Rcv En Fine Value = 297
N2.C2.D0.R1.S03: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N4.C2.D0.R0: Starting preamble search lower nibbles
N6.C1.D0.R1.S13: Rcv En Fine Value = 376
N0.C1.D0.R1.S02: Rcv En Fine Value = 263
N2.C2.D0.R1.S04: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N4.C2.D0.R0.S00: PI = 014, PtrOffset = 004
N6.C1.D0.R1.S14: Rcv En Fine Value = 271
N0.C1.D0.R1.S03: Rcv En Fine Value = 375
N2.C2.D0.R1.S05: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N4.C2.D0.R0.S01: PI = 055, PtrOffset = 005
N6.C1.D0.R1.S15: Rcv En Fine Value = 296
N0.C1.D0.R1.S04: Rcv En Fine Value = 366
N2.C2.D0.R1.S06: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N4.C2.D0.R0.S02: PI = 028, PtrOffset = 005
N6.C1.D0.R1.S16: Rcv En Fine Value = 316
N0.C1.D0.R1.S05: Rcv En Fine Value = 263
N2.C2.D0.R1.S07: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N4.C2.D0.R0.S03: PI = 005, PtrOffset = 005
N6.C1.D0.R1.S17: Rcv En Fine Value = 362
N0.C1.D0.R1.S06: Rcv En Fine Value = 289
N2.C2.D0.R1.S08: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N4.C2.D0.R0.S04: PI = 006, PtrOffset = 005
N6.C1.D0.R1: Starting preamble search lower nibbles
N0.C1.D0.R1.S07: Rcv En Fine Value = 312
N2.C2.D0.R1.S00: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N4.C2.D0.R0.S05: PI = 016, PtrOffset = 005
N6.C1.D0.R1.S00: PI = 005, PtrOffset = 005
N0.C1.D0.R1.S08: Rcv En Fine Value = 356
N2.C2.D0.R1.S01: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N4.C2.D0.R0.S06: PI = 055, PtrOffset = 005
N6.C1.D0.R1.S01: PI = 050, PtrOffset = 004
N0.C1.D0.R1.S09: Rcv En Fine Value = 319
N2.C2.D0.R1.S02: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N4.C2.D0.R0.S07: PI = 006, PtrOffset = 004
N6.C1.D0.R1.S02: PI = 016, PtrOffset = 004
N0.C1.D0.R1.S10: Rcv En Fine Value = 297
N2.C2.D0.R1.S03: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N4.C2.D0.R0.S08: PI = 056, PtrOffset = 004
N6.C1.D0.R1.S03: PI = 060, PtrOffset = 005
N0.C1.D0.R1.S11: Rcv En Fine Value = 267
N2.C2.D0.R1.S04: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N4.C2.D0.R0.S00: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N6.C1.D0.R1.S04: PI = 054, PtrOffset = 005
N0.C1.D0.R1.S12: Rcv En Fine Value = 376
N2.C2.D0.R1.S05: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N4.C2.D0.R0.S01: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N6.C1.D0.R1.S05: PI = 015, PtrOffset = 004
N0.C1.D0.R1.S13: Rcv En Fine Value = 368
N2.C2.D0.R1.S06: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N4.C2.D0.R0.S02: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N6.C1.D0.R1.S06: PI = 037, PtrOffset = 004
N0.C1.D0.R1.S14: Rcv En Fine Value = 265
N2.C2.D0.R1.S07: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N4.C2.D0.R0.S03: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N6.C1.D0.R1.S07: PI = 061, PtrOffset = 004
N0.C1.D0.R1.S15: Rcv En Fine Value = 290
N2.C2.D0.R1.S08: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N4.C2.D0.R0.S04: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N6.C1.D0.R1.S08: PI = 042, PtrOffset = 005
N0.C1.D0.R1.S16: Rcv En Fine Value = 311
N2.C2.D0.R1.S00: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N4.C2.D0.R0.S05: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N6.C1.D0.R1.S00: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N0.C1.D0.R1.S17: Rcv En Fine Value = 358
N2.C2.D0.R1.S01: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N4.C2.D0.R0.S06: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N6.C1.D0.R1.S01: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N0.C1.D0.R1: Starting preamble search lower nibbles
N2.C2.D0.R1.S02: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N4.C2.D0.R0.S07: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N6.C1.D0.R1.S02: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N0.C1.D0.R1.S00: PI = 000, PtrOffset = 005
N2.C2.D0.R1.S03: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N4.C2.D0.R0.S08: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N6.C1.D0.R1.S03: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N0.C1.D0.R1.S01: PI = 041, PtrOffset = 004
N2.C2.D0.R1.S04: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N4.C2.D0.R0.S00: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N6.C1.D0.R1.S04: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N0.C1.D0.R1.S02: PI = 007, PtrOffset = 004
N2.C2.D0.R1.S05: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N4.C2.D0.R0.S01: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N6.C1.D0.R1.S05: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N0.C1.D0.R1.S03: PI = 055, PtrOffset = 005
N2.C2.D0.R1.S06: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N4.C2.D0.R0.S02: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N6.C1.D0.R1.S06: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N0.C1.D0.R1.S04: PI = 046, PtrOffset = 005
N2.C2.D0.R1.S07: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N4.C2.D0.R0.S03: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N6.C1.D0.R1.S07: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N0.C1.D0.R1.S05: PI = 007, PtrOffset = 004
N2.C2.D0.R1.S08: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N4.C2.D0.R0.S04: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N6.C1.D0.R1.S08: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N0.C1.D0.R1.S06: PI = 033, PtrOffset = 004
N2.C2.D0.R1.S00: Preamble found at Latency = 008
N4.C2.D0.R0.S05: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N6.C1.D0.R1.S00: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N0.C1.D0.R1.S07: PI = 056, PtrOffset = 004
N2.C2.D0.R1.S07: Preamble found at Latency = 008
N4.C2.D0.R0.S06: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N6.C1.D0.R1.S01: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N0.C1.D0.R1.S08: PI = 036, PtrOffset = 005
N2.C2.D0.R1.S00: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N4.C2.D0.R0.S07: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N6.C1.D0.R1.S02: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N0.C1.D0.R1.S00: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N2.C2.D0.R1.S01: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N4.C2.D0.R0.S08: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N6.C1.D0.R1.S03: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N0.C1.D0.R1.S01: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N2.C2.D0.R1.S02: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N4.C2.D0.R0.S00: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N6.C1.D0.R1.S04: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N0.C1.D0.R1.S02: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N2.C2.D0.R1.S03: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N4.C2.D0.R0.S01: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N6.C1.D0.R1.S05: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N0.C1.D0.R1.S03: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N2.C2.D0.R1.S04: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N4.C2.D0.R0.S02: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N6.C1.D0.R1.S06: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N0.C1.D0.R1.S04: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N2.C2.D0.R1.S05: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N4.C2.D0.R0.S03: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N6.C1.D0.R1.S07: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N0.C1.D0.R1.S05: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N2.C2.D0.R1.S06: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N4.C2.D0.R0.S04: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N6.C1.D0.R1.S08: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N0.C1.D0.R1.S06: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N2.C2.D0.R1.S07: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N4.C2.D0.R0.S05: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N6.C1.D0.R1.S00: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N0.C1.D0.R1.S07: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N2.C2.D0.R1.S08: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N4.C2.D0.R0.S06: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N6.C1.D0.R1.S01: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N0.C1.D0.R1.S08: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N2.C2.D0.R1.S01: Preamble found at Latency = 007
N4.C2.D0.R0.S07: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N6.C1.D0.R1.S02: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N0.C1.D0.R1.S00: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N2.C2.D0.R1.S02: Preamble found at Latency = 007
N4.C2.D0.R0.S08: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N6.C1.D0.R1.S03: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N0.C1.D0.R1.S01: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N2.C2.D0.R1.S03: Preamble found at Latency = 007
N4.C2.D0.R0.S00: Preamble found at Latency = 008
N6.C1.D0.R1.S04: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N0.C1.D0.R1.S02: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N2.C2.D0.R1.S04: Preamble found at Latency = 007
N4.C2.D0.R0.S07: Preamble found at Latency = 008
N6.C1.D0.R1.S05: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N0.C1.D0.R1.S03: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N2.C2.D0.R1.S05: Preamble found at Latency = 007
N4.C2.D0.R0.S00: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N6.C1.D0.R1.S06: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N0.C1.D0.R1.S04: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N2.C2.D0.R1.S06: Preamble found at Latency = 007
N4.C2.D0.R0.S01: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N6.C1.D0.R1.S07: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N0.C1.D0.R1.S05: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N2.C2.D0.R1.S08: Preamble found at Latency = 007
N4.C2.D0.R0.S02: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N6.C1.D0.R1.S08: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N0.C1.D0.R1.S06: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N2.C2.D0.R1.S00: Total Receive Enable Delay = 1331
N4.C2.D0.R0.S03: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N6.C1.D0.R1.S00: Preamble found at Latency = 008
N0.C1.D0.R1.S07: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N2.C2.D0.R1.S01: Total Receive Enable Delay = 1308
N4.C2.D0.R0.S04: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N6.C1.D0.R1.S01: Preamble found at Latency = 008
N0.C1.D0.R1.S08: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N2.C2.D0.R1.S02: Total Receive Enable Delay = 1277
N4.C2.D0.R0.S05: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N6.C1.D0.R1.S02: Preamble found at Latency = 008
N0.C1.D0.R1.S00: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N2.C2.D0.R1.S03: Total Receive Enable Delay = 1259
N4.C2.D0.R0.S06: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N6.C1.D0.R1.S05: Preamble found at Latency = 008
N0.C1.D0.R1.S01: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N2.C2.D0.R1.S04: Total Receive Enable Delay = 1258
N4.C2.D0.R0.S07: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N6.C1.D0.R1.S06: Preamble found at Latency = 008
N0.C1.D0.R1.S02: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N2.C2.D0.R1.S05: Total Receive Enable Delay = 1271
N4.C2.D0.R0.S08: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N6.C1.D0.R1.S07: Preamble found at Latency = 008
N0.C1.D0.R1.S03: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N2.C2.D0.R1.S06: Total Receive Enable Delay = 1309
N4.C2.D0.R0.S01: Preamble found at Latency = 007
N6.C1.D0.R1.S00: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N0.C1.D0.R1.S04: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N2.C2.D0.R1.S07: Total Receive Enable Delay = 1325
N4.C2.D0.R0.S02: Preamble found at Latency = 007
N6.C1.D0.R1.S01: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N0.C1.D0.R1.S05: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N2.C2.D0.R1.S08: Total Receive Enable Delay = 1246
N4.C2.D0.R0.S03: Preamble found at Latency = 007
N6.C1.D0.R1.S02: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N0.C1.D0.R1.S06: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N2.C2.D0.R1: Starting preamble search upper nibbles
N4.C2.D0.R0.S04: Preamble found at Latency = 007
N6.C1.D0.R1.S03: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N0.C1.D0.R1.S07: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N2.C2.D0.R1.S09: PI = 017, PtrOffset = 004
N4.C2.D0.R0.S05: Preamble found at Latency = 007
N6.C1.D0.R1.S04: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N0.C1.D0.R1.S08: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N2.C2.D0.R1.S10: PI = 061, PtrOffset = 005
N4.C2.D0.R0.S06: Preamble found at Latency = 007
N6.C1.D0.R1.S05: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N0.C1.D0.R1.S00: Preamble found at Latency = 008
N2.C2.D0.R1.S11: PI = 029, PtrOffset = 005
N4.C2.D0.R0.S08: Preamble found at Latency = 007
N6.C1.D0.R1.S06: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N0.C1.D0.R1.S01: Preamble found at Latency = 008
N2.C2.D0.R1.S12: PI = 011, PtrOffset = 005
N4.C2.D0.R0.S00: Total Receive Enable Delay = 1326
N6.C1.D0.R1.S07: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N0.C1.D0.R1.S02: Preamble found at Latency = 008
N2.C2.D0.R1.S13: PI = 011, PtrOffset = 005
N4.C2.D0.R0.S01: Total Receive Enable Delay = 1303
N6.C1.D0.R1.S08: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N0.C1.D0.R1.S05: Preamble found at Latency = 008
N2.C2.D0.R1.S14: PI = 019, PtrOffset = 005
N4.C2.D0.R0.S02: Total Receive Enable Delay = 1276
N6.C1.D0.R1.S03: Preamble found at Latency = 007
N0.C1.D0.R1.S06: Preamble found at Latency = 008
N2.C2.D0.R1.S15: PI = 056, PtrOffset = 005
N4.C2.D0.R0.S03: Total Receive Enable Delay = 1253
N6.C1.D0.R1.S04: Preamble found at Latency = 007
N0.C1.D0.R1.S07: Preamble found at Latency = 008
N2.C2.D0.R1.S16: PI = 013, PtrOffset = 004
N4.C2.D0.R0.S04: Total Receive Enable Delay = 1254
N6.C1.D0.R1.S08: Preamble found at Latency = 007
N0.C1.D0.R1.S00: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N2.C2.D0.R1.S17: PI = 056, PtrOffset = 004
N4.C2.D0.R0.S05: Total Receive Enable Delay = 1264
N6.C1.D0.R1.S00: Total Receive Enable Delay = 1381
N0.C1.D0.R1.S01: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N2.C2.D0.R1.S09: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N4.C2.D0.R0.S06: Total Receive Enable Delay = 1303
N6.C1.D0.R1.S01: Total Receive Enable Delay = 1362
N0.C1.D0.R1.S02: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N2.C2.D0.R1.S10: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N4.C2.D0.R0.S07: Total Receive Enable Delay = 1318
N6.C1.D0.R1.S02: Total Receive Enable Delay = 1328
N0.C1.D0.R1.S03: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N2.C2.D0.R1.S11: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N4.C2.D0.R0.S08: Total Receive Enable Delay = 1240
N6.C1.D0.R1.S03: Total Receive Enable Delay = 1308
N0.C1.D0.R1.S04: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N2.C2.D0.R1.S12: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N4.C2.D0.R0: Starting preamble search upper nibbles
N6.C1.D0.R1.S04: Total Receive Enable Delay = 1302
N0.C1.D0.R1.S05: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N2.C2.D0.R1.S13: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N4.C2.D0.R0.S09: PI = 014, PtrOffset = 004
N6.C1.D0.R1.S05: Total Receive Enable Delay = 1327
N0.C1.D0.R1.S06: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N2.C2.D0.R1.S14: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N4.C2.D0.R0.S10: PI = 055, PtrOffset = 005
N6.C1.D0.R1.S06: Total Receive Enable Delay = 1349
N0.C1.D0.R1.S07: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N2.C2.D0.R1.S15: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N4.C2.D0.R0.S11: PI = 022, PtrOffset = 005
N6.C1.D0.R1.S07: Total Receive Enable Delay = 1373
N0.C1.D0.R1.S08: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N2.C2.D0.R1.S16: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N4.C2.D0.R0.S12: PI = 004, PtrOffset = 005
N6.C1.D0.R1.S08: Total Receive Enable Delay = 1290
N0.C1.D0.R1.S03: Preamble found at Latency = 007
N2.C2.D0.R1.S17: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N4.C2.D0.R0.S13: PI = 004, PtrOffset = 005
N6.C1.D0.R1: Starting preamble search upper nibbles
N0.C1.D0.R1.S04: Preamble found at Latency = 007
N2.C2.D0.R1.S09: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N4.C2.D0.R0.S14: PI = 020, PtrOffset = 005
N6.C1.D0.R1.S09: PI = 003, PtrOffset = 005
N0.C1.D0.R1.S08: Preamble found at Latency = 007
N2.C2.D0.R1.S10: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N4.C2.D0.R0.S15: PI = 055, PtrOffset = 005
N6.C1.D0.R1.S10: PI = 049, PtrOffset = 004
N0.C1.D0.R1.S00: Total Receive Enable Delay = 1376
N2.C2.D0.R1.S11: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N4.C2.D0.R0.S16: PI = 005, PtrOffset = 004
N6.C1.D0.R1.S11: PI = 015, PtrOffset = 004
N0.C1.D0.R1.S01: Total Receive Enable Delay = 1353
N2.C2.D0.R1.S12: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N4.C2.D0.R0.S17: PI = 052, PtrOffset = 004
N6.C1.D0.R1.S12: PI = 062, PtrOffset = 005
N0.C1.D0.R1.S02: Total Receive Enable Delay = 1319
N2.C2.D0.R1.S13: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N4.C2.D0.R0.S09: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N6.C1.D0.R1.S13: PI = 056, PtrOffset = 005
N0.C1.D0.R1.S03: Total Receive Enable Delay = 1303
N2.C2.D0.R1.S14: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N4.C2.D0.R0.S10: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N6.C1.D0.R1.S14: PI = 015, PtrOffset = 004
N0.C1.D0.R1.S04: Total Receive Enable Delay = 1294
N2.C2.D0.R1.S15: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N4.C2.D0.R0.S11: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N6.C1.D0.R1.S15: PI = 040, PtrOffset = 004
N0.C1.D0.R1.S05: Total Receive Enable Delay = 1319
N2.C2.D0.R1.S16: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N4.C2.D0.R0.S12: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N6.C1.D0.R1.S16: PI = 060, PtrOffset = 004
N0.C1.D0.R1.S06: Total Receive Enable Delay = 1345
N2.C2.D0.R1.S17: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N4.C2.D0.R0.S13: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N6.C1.D0.R1.S17: PI = 042, PtrOffset = 005
N0.C1.D0.R1.S07: Total Receive Enable Delay = 1368
N2.C2.D0.R1.S09: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N4.C2.D0.R0.S14: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N6.C1.D0.R1.S09: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N0.C1.D0.R1.S08: Total Receive Enable Delay = 1284
N2.C2.D0.R1.S10: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N4.C2.D0.R0.S15: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N6.C1.D0.R1.S10: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N0.C1.D0.R1: Starting preamble search upper nibbles
N2.C2.D0.R1.S11: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N4.C2.D0.R0.S16: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N6.C1.D0.R1.S11: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N0.C1.D0.R1.S09: PI = 063, PtrOffset = 004
N2.C2.D0.R1.S12: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N4.C2.D0.R0.S17: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N6.C1.D0.R1.S12: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N0.C1.D0.R1.S10: PI = 041, PtrOffset = 004
N2.C2.D0.R1.S13: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N4.C2.D0.R0.S09: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N6.C1.D0.R1.S13: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N0.C1.D0.R1.S11: PI = 011, PtrOffset = 004
N2.C2.D0.R1.S14: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N4.C2.D0.R0.S10: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N6.C1.D0.R1.S14: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N0.C1.D0.R1.S12: PI = 056, PtrOffset = 005
N2.C2.D0.R1.S15: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N4.C2.D0.R0.S11: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N6.C1.D0.R1.S15: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N0.C1.D0.R1.S13: PI = 048, PtrOffset = 005
N2.C2.D0.R1.S16: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N4.C2.D0.R0.S12: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N6.C1.D0.R1.S16: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N0.C1.D0.R1.S14: PI = 009, PtrOffset = 004
N2.C2.D0.R1.S17: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N4.C2.D0.R0.S13: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N6.C1.D0.R1.S17: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N0.C1.D0.R1.S15: PI = 034, PtrOffset = 004
N2.C2.D0.R1.S09: Preamble found at Latency = 008
N4.C2.D0.R0.S14: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N6.C1.D0.R1.S09: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N0.C1.D0.R1.S16: PI = 055, PtrOffset = 004
N2.C2.D0.R1.S16: Preamble found at Latency = 008
N4.C2.D0.R0.S15: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N6.C1.D0.R1.S10: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N0.C1.D0.R1.S17: PI = 038, PtrOffset = 005
N2.C2.D0.R1.S09: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N4.C2.D0.R0.S16: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N6.C1.D0.R1.S11: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N0.C1.D0.R1.S09: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N2.C2.D0.R1.S10: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N4.C2.D0.R0.S17: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N6.C1.D0.R1.S12: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N0.C1.D0.R1.S10: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N2.C2.D0.R1.S11: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N4.C2.D0.R0.S09: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N6.C1.D0.R1.S13: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N0.C1.D0.R1.S11: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N2.C2.D0.R1.S12: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N4.C2.D0.R0.S10: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N6.C1.D0.R1.S14: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N0.C1.D0.R1.S12: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N2.C2.D0.R1.S13: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N4.C2.D0.R0.S11: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N6.C1.D0.R1.S15: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N0.C1.D0.R1.S13: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N2.C2.D0.R1.S14: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N4.C2.D0.R0.S12: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N6.C1.D0.R1.S16: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N0.C1.D0.R1.S14: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N2.C2.D0.R1.S15: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N4.C2.D0.R0.S13: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N6.C1.D0.R1.S17: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N0.C1.D0.R1.S15: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N2.C2.D0.R1.S16: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N4.C2.D0.R0.S14: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N6.C1.D0.R1.S09: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N0.C1.D0.R1.S16: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N2.C2.D0.R1.S17: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N4.C2.D0.R0.S15: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N6.C1.D0.R1.S10: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N0.C1.D0.R1.S17: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N2.C2.D0.R1.S10: Preamble found at Latency = 007
N4.C2.D0.R0.S16: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N6.C1.D0.R1.S11: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N0.C1.D0.R1.S09: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N2.C2.D0.R1.S11: Preamble found at Latency = 007
N4.C2.D0.R0.S17: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N6.C1.D0.R1.S12: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N0.C1.D0.R1.S10: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N2.C2.D0.R1.S12: Preamble found at Latency = 007
N4.C2.D0.R0.S09: Preamble found at Latency = 008
N6.C1.D0.R1.S13: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N0.C1.D0.R1.S11: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N2.C2.D0.R1.S13: Preamble found at Latency = 007
N4.C2.D0.R0.S16: Preamble found at Latency = 008
N6.C1.D0.R1.S14: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N0.C1.D0.R1.S12: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N2.C2.D0.R1.S14: Preamble found at Latency = 007
N4.C2.D0.R0.S09: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N6.C1.D0.R1.S15: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N0.C1.D0.R1.S13: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N2.C2.D0.R1.S15: Preamble found at Latency = 007
N4.C2.D0.R0.S10: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N6.C1.D0.R1.S16: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N0.C1.D0.R1.S14: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N2.C2.D0.R1.S17: Preamble found at Latency = 007
N4.C2.D0.R0.S11: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N6.C1.D0.R1.S17: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N0.C1.D0.R1.S15: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N2.C2.D0.R1: Preamble found for all upper nibbles, adjusting Pi, Offset to center into preamble
N4.C2.D0.R0.S12: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N6.C1.D0.R1.S09: Preamble found at Latency = 008
N0.C1.D0.R1.S16: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N2.C2.D0.R1.S09: Total Receive Enable Delay = 1329
N4.C2.D0.R0.S13: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N6.C1.D0.R1.S10: Preamble found at Latency = 008
N0.C1.D0.R1.S17: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N2.C2.D0.R1.S10: Total Receive Enable Delay = 1309
N4.C2.D0.R0.S14: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N6.C1.D0.R1.S11: Preamble found at Latency = 008
N0.C1.D0.R1.S09: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N2.C2.D0.R1.S11: Total Receive Enable Delay = 1277
N4.C2.D0.R0.S15: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N6.C1.D0.R1.S14: Preamble found at Latency = 008
N0.C1.D0.R1.S10: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N2.C2.D0.R1.S12: Total Receive Enable Delay = 1259
N4.C2.D0.R0.S16: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N6.C1.D0.R1.S15: Preamble found at Latency = 008
N0.C1.D0.R1.S11: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N2.C2.D0.R1.S13: Total Receive Enable Delay = 1259
N4.C2.D0.R0.S17: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N6.C1.D0.R1.S16: Preamble found at Latency = 008
N0.C1.D0.R1.S12: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N2.C2.D0.R1.S14: Total Receive Enable Delay = 1267
N4.C2.D0.R0.S10: Preamble found at Latency = 007
N6.C1.D0.R1.S09: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N0.C1.D0.R1.S13: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N2.C2.D0.R1.S15: Total Receive Enable Delay = 1304
N4.C2.D0.R0.S11: Preamble found at Latency = 007
N6.C1.D0.R1.S10: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N0.C1.D0.R1.S14: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N2.C2.D0.R1.S16: Total Receive Enable Delay = 1325
N4.C2.D0.R0.S12: Preamble found at Latency = 007
N6.C1.D0.R1.S11: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N0.C1.D0.R1.S15: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N2.C2.D0.R1.S17: Total Receive Enable Delay = 1240
N4.C2.D0.R0.S13: Preamble found at Latency = 007
N6.C1.D0.R1.S12: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N0.C1.D0.R1.S16: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N2.C2.D1.R0: RcvEnFine: Initial RdCmd2RcvEnLatency = 10, Initial RdPtrOffsetRcvEn = 4
N4.C2.D0.R0.S14: Preamble found at Latency = 007
N6.C1.D0.R1.S13: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N0.C1.D0.R1.S17: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N2.C2.D1.R0.S00: Rcv En Fine Value = 256
N4.C2.D0.R0.S15: Preamble found at Latency = 007
N6.C1.D0.R1.S14: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N0.C1.D0.R1.S09: Preamble found at Latency = 008
N2.C2.D1.R0.S01: Rcv En Fine Value = 363
N4.C2.D0.R0.S17: Preamble found at Latency = 007
N6.C1.D0.R1.S15: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N0.C1.D0.R1.S10: Preamble found at Latency = 008
N2.C2.D1.R0.S02: Rcv En Fine Value = 331
N4.C2.D0.R0: Preamble found for all upper nibbles, adjusting Pi, Offset to center into preamble
N6.C1.D0.R1.S16: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N0.C1.D0.R1.S11: Preamble found at Latency = 008
N2.C2.D1.R0.S03: Rcv En Fine Value = 318
N4.C2.D0.R0.S09: Total Receive Enable Delay = 1326
N6.C1.D0.R1.S17: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N0.C1.D0.R1.S14: Preamble found at Latency = 008
N2.C2.D1.R0.S04: Rcv En Fine Value = 315
N4.C2.D0.R0.S10: Total Receive Enable Delay = 1303
N6.C1.D0.R1.S12: Preamble found at Latency = 007
N0.C1.D0.R1.S15: Preamble found at Latency = 008
N2.C2.D1.R0.S05: Rcv En Fine Value = 329
N4.C2.D0.R0.S11: Total Receive Enable Delay = 1270
N6.C1.D0.R1.S13: Preamble found at Latency = 007
N0.C1.D0.R1.S16: Preamble found at Latency = 008
N2.C2.D1.R0.S06: Rcv En Fine Value = 364
N4.C2.D0.R0.S12: Total Receive Enable Delay = 1252
N6.C1.D0.R1.S17: Preamble found at Latency = 007
N0.C1.D0.R1.S09: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N2.C2.D1.R0.S07: Rcv En Fine Value = 382
N4.C2.D0.R0.S13: Total Receive Enable Delay = 1252
N6.C1.D0.R1: Preamble found for all upper nibbles, adjusting Pi, Offset to center into preamble
N0.C1.D0.R1.S10: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N2.C2.D1.R0.S08: Rcv En Fine Value = 303
N4.C2.D0.R0.S14: Total Receive Enable Delay = 1268
N6.C1.D0.R1.S09: Total Receive Enable Delay = 1379
N0.C1.D0.R1.S11: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N2.C2.D1.R0.S09: Rcv En Fine Value = 260
N4.C2.D0.R0.S15: Total Receive Enable Delay = 1303
N6.C1.D0.R1.S10: Total Receive Enable Delay = 1361
N0.C1.D0.R1.S12: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N2.C2.D1.R0.S10: Rcv En Fine Value = 363
N4.C2.D0.R0.S16: Total Receive Enable Delay = 1317
N6.C1.D0.R1.S11: Total Receive Enable Delay = 1327
N0.C1.D0.R1.S13: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N2.C2.D1.R0.S11: Rcv En Fine Value = 331
N4.C2.D0.R0.S17: Total Receive Enable Delay = 1236
N6.C1.D0.R1.S12: Total Receive Enable Delay = 1310
N0.C1.D0.R1.S14: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N2.C2.D1.R0.S12: Rcv En Fine Value = 314
N4.C2.D0.R1: RcvEnFine: Initial RdCmd2RcvEnLatency = 10, Initial RdPtrOffsetRcvEn = 4
N6.C1.D0.R1.S13: Total Receive Enable Delay = 1304
N0.C1.D0.R1.S15: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N2.C2.D1.R0.S13: Rcv En Fine Value = 314
N4.C2.D0.R1.S00: Rcv En Fine Value = 270
N6.C1.D0.R1.S14: Total Receive Enable Delay = 1327
N0.C1.D0.R1.S16: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N2.C2.D1.R0.S14: Rcv En Fine Value = 326
N4.C2.D0.R1.S01: Rcv En Fine Value = 375
N6.C1.D0.R1.S15: Total Receive Enable Delay = 1352
N0.C1.D0.R1.S17: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N2.C2.D1.R0.S15: Rcv En Fine Value = 362
N4.C2.D0.R1.S02: Rcv En Fine Value = 347
N6.C1.D0.R1.S16: Total Receive Enable Delay = 1372
N0.C1.D0.R1.S12: Preamble found at Latency = 007
N2.C2.D1.R0.S16: Rcv En Fine Value = 380
N4.C2.D0.R1.S03: Rcv En Fine Value = 325
N6.C1.D0.R1.S17: Total Receive Enable Delay = 1290
N0.C1.D0.R1.S13: Preamble found at Latency = 007
N2.C2.D1.R0.S17: Rcv En Fine Value = 299
N4.C2.D0.R1.S04: Rcv En Fine Value = 324
N6.C1.D1.R0: RcvEnFine: Initial RdCmd2RcvEnLatency = 10, Initial RdPtrOffsetRcvEn = 4
N0.C1.D0.R1.S17: Preamble found at Latency = 007
N2.C2.D1.R0: Starting preamble search lower nibbles
N4.C2.D0.R1.S05: Rcv En Fine Value = 335
N6.C1.D1.R0.S00: Rcv En Fine Value = 311
N0.C1.D0.R1: Preamble found for all upper nibbles, adjusting Pi, Offset to center into preamble
N2.C2.D1.R0.S00: PI = 000, PtrOffset = 004
N4.C2.D0.R1.S06: Rcv En Fine Value = 375
N6.C1.D1.R0.S01: Rcv En Fine Value = 288
N0.C1.D0.R1.S09: Total Receive Enable Delay = 1375
N2.C2.D1.R0.S01: PI = 043, PtrOffset = 005
N4.C2.D0.R1.S07: Rcv En Fine Value = 262
N6.C1.D1.R0.S02: Rcv En Fine Value = 258
N0.C1.D0.R1.S10: Total Receive Enable Delay = 1353
N2.C2.D1.R0.S02: PI = 011, PtrOffset = 005
N4.C2.D0.R1.S08: Rcv En Fine Value = 312
N6.C1.D1.R0.S03: Rcv En Fine Value = 362
N0.C1.D0.R1.S11: Total Receive Enable Delay = 1323
N2.C2.D1.R0.S03: PI = 062, PtrOffset = 004
N4.C2.D0.R1.S09: Rcv En Fine Value = 268
N6.C1.D1.R0.S04: Rcv En Fine Value = 359
N0.C1.D0.R1.S12: Total Receive Enable Delay = 1304
N2.C2.D1.R0.S04: PI = 059, PtrOffset = 004
N4.C2.D0.R1.S10: Rcv En Fine Value = 377
N6.C1.D1.R0.S05: Rcv En Fine Value = 256
N0.C1.D0.R1.S13: Total Receive Enable Delay = 1296
N2.C2.D1.R0.S05: PI = 009, PtrOffset = 005
N4.C2.D0.R1.S11: Rcv En Fine Value = 344
N6.C1.D1.R0.S06: Rcv En Fine Value = 280
N0.C1.D0.R1.S14: Total Receive Enable Delay = 1321
N2.C2.D1.R0.S06: PI = 044, PtrOffset = 005
N4.C2.D0.R1.S12: Rcv En Fine Value = 323
N6.C1.D1.R0.S07: Rcv En Fine Value = 300
N0.C1.D0.R1.S15: Total Receive Enable Delay = 1346
N2.C2.D1.R0.S07: PI = 062, PtrOffset = 005
N4.C2.D0.R1.S13: Rcv En Fine Value = 324
N6.C1.D1.R0.S08: Rcv En Fine Value = 347
N0.C1.D0.R1.S16: Total Receive Enable Delay = 1367
N2.C2.D1.R0.S08: PI = 047, PtrOffset = 004
N4.C2.D0.R1.S14: Rcv En Fine Value = 338
N6.C1.D1.R0.S09: Rcv En Fine Value = 308
N0.C1.D0.R1.S17: Total Receive Enable Delay = 1286
N2.C2.D1.R0.S00: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N4.C2.D0.R1.S15: Rcv En Fine Value = 375
N6.C1.D1.R0.S10: Rcv En Fine Value = 288
N0.C1.D1.R0: RcvEnFine: Initial RdCmd2RcvEnLatency = 10, Initial RdPtrOffsetRcvEn = 4
N2.C2.D1.R0.S01: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N4.C2.D0.R1.S16: Rcv En Fine Value = 263
N6.C1.D1.R0.S11: Rcv En Fine Value = 258
N0.C1.D1.R0.S00: Rcv En Fine Value = 302
N2.C2.D1.R0.S02: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N4.C2.D0.R1.S17: Rcv En Fine Value = 309
N6.C1.D1.R0.S12: Rcv En Fine Value = 367
N0.C1.D1.R0.S01: Rcv En Fine Value = 281
N2.C2.D1.R0.S03: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N4.C2.D0.R1: Starting preamble search lower nibbles
N6.C1.D1.R0.S13: Rcv En Fine Value = 358
N0.C1.D1.R0.S02: Rcv En Fine Value = 377
N2.C2.D1.R0.S04: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N4.C2.D0.R1.S00: PI = 014, PtrOffset = 004
N6.C1.D1.R0.S14: Rcv En Fine Value = 256
N0.C1.D1.R0.S03: Rcv En Fine Value = 361
N2.C2.D1.R0.S05: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N4.C2.D0.R1.S01: PI = 055, PtrOffset = 005
N6.C1.D1.R0.S15: Rcv En Fine Value = 280
N0.C1.D1.R0.S04: Rcv En Fine Value = 352
N2.C2.D1.R0.S06: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N4.C2.D0.R1.S02: PI = 027, PtrOffset = 005
N6.C1.D1.R0.S16: Rcv En Fine Value = 300
N0.C1.D1.R0.S05: Rcv En Fine Value = 378
N2.C2.D1.R0.S07: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N4.C2.D0.R1.S03: PI = 005, PtrOffset = 005
N6.C1.D1.R0.S17: Rcv En Fine Value = 345
N0.C1.D1.R0.S06: Rcv En Fine Value = 272
N2.C2.D1.R0.S08: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N4.C2.D0.R1.S04: PI = 004, PtrOffset = 005
N6.C1.D1.R0: Starting preamble search lower nibbles
N0.C1.D1.R0.S07: Rcv En Fine Value = 294
N2.C2.D1.R0.S00: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N4.C2.D0.R1.S05: PI = 015, PtrOffset = 005
N6.C1.D1.R0.S00: PI = 055, PtrOffset = 004
N0.C1.D1.R0.S08: Rcv En Fine Value = 339
N2.C2.D1.R0.S01: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N4.C2.D0.R1.S06: PI = 055, PtrOffset = 005
N6.C1.D1.R0.S01: PI = 032, PtrOffset = 004
N0.C1.D1.R0.S09: Rcv En Fine Value = 301
N2.C2.D1.R0.S02: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N4.C2.D0.R1.S07: PI = 006, PtrOffset = 004
N6.C1.D1.R0.S02: PI = 002, PtrOffset = 004
N0.C1.D1.R0.S10: Rcv En Fine Value = 277
N2.C2.D1.R0.S03: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N4.C2.D0.R1.S08: PI = 056, PtrOffset = 004
N6.C1.D1.R0.S03: PI = 042, PtrOffset = 005
N0.C1.D1.R0.S11: Rcv En Fine Value = 379
N2.C2.D1.R0.S04: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N4.C2.D0.R1.S00: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N6.C1.D1.R0.S04: PI = 039, PtrOffset = 005
N0.C1.D1.R0.S12: Rcv En Fine Value = 358
N2.C2.D1.R0.S05: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N4.C2.D0.R1.S01: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N6.C1.D1.R0.S05: PI = 000, PtrOffset = 004
N0.C1.D1.R0.S13: Rcv En Fine Value = 352
N2.C2.D1.R0.S06: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N4.C2.D0.R1.S02: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N6.C1.D1.R0.S06: PI = 024, PtrOffset = 004
N0.C1.D1.R0.S14: Rcv En Fine Value = 378
N2.C2.D1.R0.S07: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N4.C2.D0.R1.S03: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N6.C1.D1.R0.S07: PI = 044, PtrOffset = 004
N0.C1.D1.R0.S15: Rcv En Fine Value = 272
N2.C2.D1.R0.S08: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N4.C2.D0.R1.S04: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N6.C1.D1.R0.S08: PI = 027, PtrOffset = 005
N0.C1.D1.R0.S16: Rcv En Fine Value = 295
N2.C2.D1.R0.S00: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N4.C2.D0.R1.S05: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N6.C1.D1.R0.S00: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N0.C1.D1.R0.S17: Rcv En Fine Value = 342
N2.C2.D1.R0.S01: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N4.C2.D0.R1.S06: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N6.C1.D1.R0.S01: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N0.C1.D1.R0: Starting preamble search lower nibbles
N2.C2.D1.R0.S02: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N4.C2.D0.R1.S07: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N6.C1.D1.R0.S02: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N0.C1.D1.R0.S00: PI = 046, PtrOffset = 004
N2.C2.D1.R0.S03: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N4.C2.D0.R1.S08: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N6.C1.D1.R0.S03: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N0.C1.D1.R0.S01: PI = 025, PtrOffset = 004
N2.C2.D1.R0.S04: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N4.C2.D0.R1.S00: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N6.C1.D1.R0.S04: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N0.C1.D1.R0.S02: PI = 057, PtrOffset = 005
N2.C2.D1.R0.S05: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N4.C2.D0.R1.S01: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N6.C1.D1.R0.S05: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N0.C1.D1.R0.S03: PI = 041, PtrOffset = 005
N2.C2.D1.R0.S06: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N4.C2.D0.R1.S02: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N6.C1.D1.R0.S06: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N0.C1.D1.R0.S04: PI = 032, PtrOffset = 005
N2.C2.D1.R0.S07: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N4.C2.D0.R1.S03: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N6.C1.D1.R0.S07: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N0.C1.D1.R0.S05: PI = 058, PtrOffset = 005
N2.C2.D1.R0.S08: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N4.C2.D0.R1.S04: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N6.C1.D1.R0.S08: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N0.C1.D1.R0.S06: PI = 016, PtrOffset = 004
N2.C2.D1.R0.S00: Preamble found at Latency = 008
N4.C2.D0.R1.S05: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N6.C1.D1.R0.S00: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N0.C1.D1.R0.S07: PI = 038, PtrOffset = 004
N2.C2.D1.R0.S00: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N4.C2.D0.R1.S06: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N6.C1.D1.R0.S01: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N0.C1.D1.R0.S08: PI = 019, PtrOffset = 005
N2.C2.D1.R0.S01: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N4.C2.D0.R1.S07: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N6.C1.D1.R0.S02: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N0.C1.D1.R0.S00: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N2.C2.D1.R0.S02: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N4.C2.D0.R1.S08: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N6.C1.D1.R0.S03: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N0.C1.D1.R0.S01: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N2.C2.D1.R0.S03: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N4.C2.D0.R1.S00: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N6.C1.D1.R0.S04: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N0.C1.D1.R0.S02: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N2.C2.D1.R0.S04: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N4.C2.D0.R1.S01: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N6.C1.D1.R0.S05: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N0.C1.D1.R0.S03: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N2.C2.D1.R0.S05: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N4.C2.D0.R1.S02: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N6.C1.D1.R0.S06: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N0.C1.D1.R0.S04: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N2.C2.D1.R0.S06: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N4.C2.D0.R1.S03: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N6.C1.D1.R0.S07: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N0.C1.D1.R0.S05: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N2.C2.D1.R0.S07: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N4.C2.D0.R1.S04: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N6.C1.D1.R0.S08: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N0.C1.D1.R0.S06: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N2.C2.D1.R0.S08: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N4.C2.D0.R1.S05: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N6.C1.D1.R0.S00: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N0.C1.D1.R0.S07: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N2.C2.D1.R0.S01: Preamble found at Latency = 007
N4.C2.D0.R1.S06: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N6.C1.D1.R0.S01: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N0.C1.D1.R0.S08: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N2.C2.D1.R0.S02: Preamble found at Latency = 007
N4.C2.D0.R1.S07: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N6.C1.D1.R0.S02: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N0.C1.D1.R0.S00: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N2.C2.D1.R0.S03: Preamble found at Latency = 007
N4.C2.D0.R1.S08: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N6.C1.D1.R0.S03: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N0.C1.D1.R0.S01: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N2.C2.D1.R0.S04: Preamble found at Latency = 007
N4.C2.D0.R1.S00: Preamble found at Latency = 008
N6.C1.D1.R0.S04: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N0.C1.D1.R0.S02: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N2.C2.D1.R0.S05: Preamble found at Latency = 007
N4.C2.D0.R1.S07: Preamble found at Latency = 008
N6.C1.D1.R0.S05: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N0.C1.D1.R0.S03: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N2.C2.D1.R0.S06: Preamble found at Latency = 007
N4.C2.D0.R1.S00: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N6.C1.D1.R0.S06: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N0.C1.D1.R0.S04: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N2.C2.D1.R0.S07: Preamble found at Latency = 007
N4.C2.D0.R1.S01: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N6.C1.D1.R0.S07: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N0.C1.D1.R0.S05: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N2.C2.D1.R0.S08: Preamble found at Latency = 007
N4.C2.D0.R1.S02: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N6.C1.D1.R0.S08: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N0.C1.D1.R0.S06: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N2.C2.D1.R0.S00: Total Receive Enable Delay = 1312
N4.C2.D0.R1.S03: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N6.C1.D1.R0.S00: Preamble found at Latency = 008
N0.C1.D1.R0.S07: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N2.C2.D1.R0.S01: Total Receive Enable Delay = 1291
N4.C2.D0.R1.S04: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N6.C1.D1.R0.S01: Preamble found at Latency = 008
N0.C1.D1.R0.S08: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N2.C2.D1.R0.S02: Total Receive Enable Delay = 1259
N4.C2.D0.R1.S05: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N6.C1.D1.R0.S02: Preamble found at Latency = 008
N0.C1.D1.R0.S00: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N2.C2.D1.R0.S03: Total Receive Enable Delay = 1246
N4.C2.D0.R1.S06: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N6.C1.D1.R0.S05: Preamble found at Latency = 008
N0.C1.D1.R0.S01: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N2.C2.D1.R0.S04: Total Receive Enable Delay = 1243
N4.C2.D0.R1.S07: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N6.C1.D1.R0.S06: Preamble found at Latency = 008
N0.C1.D1.R0.S02: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N2.C2.D1.R0.S05: Total Receive Enable Delay = 1257
N4.C2.D0.R1.S08: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N6.C1.D1.R0.S07: Preamble found at Latency = 008
N0.C1.D1.R0.S03: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N2.C2.D1.R0.S06: Total Receive Enable Delay = 1292
N4.C2.D0.R1.S01: Preamble found at Latency = 007
N6.C1.D1.R0.S00: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N0.C1.D1.R0.S04: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N2.C2.D1.R0.S07: Total Receive Enable Delay = 1310
N4.C2.D0.R1.S02: Preamble found at Latency = 007
N6.C1.D1.R0.S01: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N0.C1.D1.R0.S05: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N2.C2.D1.R0.S08: Total Receive Enable Delay = 1231
N4.C2.D0.R1.S03: Preamble found at Latency = 007
N6.C1.D1.R0.S02: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N0.C1.D1.R0.S06: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N2.C2.D1.R0: Starting preamble search upper nibbles
N4.C2.D0.R1.S04: Preamble found at Latency = 007
N6.C1.D1.R0.S03: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N0.C1.D1.R0.S07: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N2.C2.D1.R0.S09: PI = 004, PtrOffset = 004
N4.C2.D0.R1.S05: Preamble found at Latency = 007
N6.C1.D1.R0.S04: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N0.C1.D1.R0.S08: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N2.C2.D1.R0.S10: PI = 043, PtrOffset = 005
N4.C2.D0.R1.S06: Preamble found at Latency = 007
N6.C1.D1.R0.S05: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N0.C1.D1.R0.S00: Preamble found at Latency = 008
N2.C2.D1.R0.S11: PI = 011, PtrOffset = 005
N4.C2.D0.R1.S08: Preamble found at Latency = 007
N6.C1.D1.R0.S06: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N0.C1.D1.R0.S01: Preamble found at Latency = 008
N2.C2.D1.R0.S12: PI = 058, PtrOffset = 004
N4.C2.D0.R1.S00: Total Receive Enable Delay = 1326
N6.C1.D1.R0.S07: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N0.C1.D1.R0.S06: Preamble found at Latency = 008
N2.C2.D1.R0.S13: PI = 058, PtrOffset = 004
N4.C2.D0.R1.S01: Total Receive Enable Delay = 1303
N6.C1.D1.R0.S08: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N0.C1.D1.R0.S07: Preamble found at Latency = 008
N2.C2.D1.R0.S14: PI = 006, PtrOffset = 005
N4.C2.D0.R1.S02: Total Receive Enable Delay = 1275
N6.C1.D1.R0.S03: Preamble found at Latency = 007
N0.C1.D1.R0.S00: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N2.C2.D1.R0.S15: PI = 042, PtrOffset = 005
N4.C2.D0.R1.S03: Total Receive Enable Delay = 1253
N6.C1.D1.R0.S04: Preamble found at Latency = 007
N0.C1.D1.R0.S01: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N2.C2.D1.R0.S16: PI = 060, PtrOffset = 005
N4.C2.D0.R1.S04: Total Receive Enable Delay = 1252
N6.C1.D1.R0.S08: Preamble found at Latency = 007
N0.C1.D1.R0.S02: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N2.C2.D1.R0.S17: PI = 043, PtrOffset = 004
N4.C2.D0.R1.S05: Total Receive Enable Delay = 1263
N6.C1.D1.R0.S00: Total Receive Enable Delay = 1367
N0.C1.D1.R0.S03: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N2.C2.D1.R0.S09: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N4.C2.D0.R1.S06: Total Receive Enable Delay = 1303
N6.C1.D1.R0.S01: Total Receive Enable Delay = 1344
N0.C1.D1.R0.S04: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N2.C2.D1.R0.S10: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N4.C2.D0.R1.S07: Total Receive Enable Delay = 1318
N6.C1.D1.R0.S02: Total Receive Enable Delay = 1314
N0.C1.D1.R0.S05: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N2.C2.D1.R0.S11: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N4.C2.D0.R1.S08: Total Receive Enable Delay = 1240
N6.C1.D1.R0.S03: Total Receive Enable Delay = 1290
N0.C1.D1.R0.S06: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N2.C2.D1.R0.S12: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N4.C2.D0.R1: Starting preamble search upper nibbles
N6.C1.D1.R0.S04: Total Receive Enable Delay = 1287
N0.C1.D1.R0.S07: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N2.C2.D1.R0.S13: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N4.C2.D0.R1.S09: PI = 012, PtrOffset = 004
N6.C1.D1.R0.S05: Total Receive Enable Delay = 1312
N0.C1.D1.R0.S08: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N2.C2.D1.R0.S14: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N4.C2.D0.R1.S10: PI = 057, PtrOffset = 005
N6.C1.D1.R0.S06: Total Receive Enable Delay = 1336
N0.C1.D1.R0.S02: Preamble found at Latency = 007
N2.C2.D1.R0.S15: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N4.C2.D0.R1.S11: PI = 024, PtrOffset = 005
N6.C1.D1.R0.S07: Total Receive Enable Delay = 1356
N0.C1.D1.R0.S03: Preamble found at Latency = 007
N2.C2.D1.R0.S16: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N4.C2.D0.R1.S12: PI = 003, PtrOffset = 005
N6.C1.D1.R0.S08: Total Receive Enable Delay = 1275
N0.C1.D1.R0.S04: Preamble found at Latency = 007
N2.C2.D1.R0.S17: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N4.C2.D0.R1.S13: PI = 004, PtrOffset = 005
N6.C1.D1.R0: Starting preamble search upper nibbles
N0.C1.D1.R0.S05: Preamble found at Latency = 007
N2.C2.D1.R0.S09: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N4.C2.D0.R1.S14: PI = 018, PtrOffset = 005
N6.C1.D1.R0.S09: PI = 052, PtrOffset = 004
N0.C1.D1.R0.S08: Preamble found at Latency = 007
N2.C2.D1.R0.S10: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N4.C2.D0.R1.S15: PI = 055, PtrOffset = 005
N6.C1.D1.R0.S10: PI = 032, PtrOffset = 004
N0.C1.D1.R0.S00: Total Receive Enable Delay = 1358
N2.C2.D1.R0.S11: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N4.C2.D0.R1.S16: PI = 007, PtrOffset = 004
N6.C1.D1.R0.S11: PI = 002, PtrOffset = 004
N0.C1.D1.R0.S01: Total Receive Enable Delay = 1337
N2.C2.D1.R0.S12: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N4.C2.D0.R1.S17: PI = 053, PtrOffset = 004
N6.C1.D1.R0.S12: PI = 047, PtrOffset = 005
N0.C1.D1.R0.S02: Total Receive Enable Delay = 1305
N2.C2.D1.R0.S13: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N4.C2.D0.R1.S09: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N6.C1.D1.R0.S13: PI = 038, PtrOffset = 005
N0.C1.D1.R0.S03: Total Receive Enable Delay = 1289
N2.C2.D1.R0.S14: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N4.C2.D0.R1.S10: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N6.C1.D1.R0.S14: PI = 000, PtrOffset = 004
N0.C1.D1.R0.S04: Total Receive Enable Delay = 1280
N2.C2.D1.R0.S15: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N4.C2.D0.R1.S11: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N6.C1.D1.R0.S15: PI = 024, PtrOffset = 004
N0.C1.D1.R0.S05: Total Receive Enable Delay = 1306
N2.C2.D1.R0.S16: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N4.C2.D0.R1.S12: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N6.C1.D1.R0.S16: PI = 044, PtrOffset = 004
N0.C1.D1.R0.S06: Total Receive Enable Delay = 1328
N2.C2.D1.R0.S17: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N4.C2.D0.R1.S13: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N6.C1.D1.R0.S17: PI = 025, PtrOffset = 005
N0.C1.D1.R0.S07: Total Receive Enable Delay = 1350
N2.C2.D1.R0.S09: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N4.C2.D0.R1.S14: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N6.C1.D1.R0.S09: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N0.C1.D1.R0.S08: Total Receive Enable Delay = 1267
N2.C2.D1.R0.S10: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N4.C2.D0.R1.S15: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N6.C1.D1.R0.S10: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N0.C1.D1.R0: Starting preamble search upper nibbles
N2.C2.D1.R0.S11: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N4.C2.D0.R1.S16: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N6.C1.D1.R0.S11: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N0.C1.D1.R0.S09: PI = 045, PtrOffset = 004
N2.C2.D1.R0.S12: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N4.C2.D0.R1.S17: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N6.C1.D1.R0.S12: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N0.C1.D1.R0.S10: PI = 021, PtrOffset = 004
N2.C2.D1.R0.S13: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N4.C2.D0.R1.S09: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N6.C1.D1.R0.S13: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N0.C1.D1.R0.S11: PI = 059, PtrOffset = 005
N2.C2.D1.R0.S14: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N4.C2.D0.R1.S10: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N6.C1.D1.R0.S14: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N0.C1.D1.R0.S12: PI = 038, PtrOffset = 005
N2.C2.D1.R0.S15: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N4.C2.D0.R1.S11: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N6.C1.D1.R0.S15: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N0.C1.D1.R0.S13: PI = 032, PtrOffset = 005
N2.C2.D1.R0.S16: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N4.C2.D0.R1.S12: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N6.C1.D1.R0.S16: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N0.C1.D1.R0.S14: PI = 058, PtrOffset = 005
N2.C2.D1.R0.S17: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N4.C2.D0.R1.S13: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N6.C1.D1.R0.S17: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N0.C1.D1.R0.S15: PI = 016, PtrOffset = 004
N2.C2.D1.R0.S09: Preamble found at Latency = 008
N4.C2.D0.R1.S14: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N6.C1.D1.R0.S09: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N0.C1.D1.R0.S16: PI = 039, PtrOffset = 004
N2.C2.D1.R0.S09: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N4.C2.D0.R1.S15: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N6.C1.D1.R0.S10: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N0.C1.D1.R0.S17: PI = 022, PtrOffset = 005
N2.C2.D1.R0.S10: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N4.C2.D0.R1.S16: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N6.C1.D1.R0.S11: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N0.C1.D1.R0.S09: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N2.C2.D1.R0.S11: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N4.C2.D0.R1.S17: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N6.C1.D1.R0.S12: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N0.C1.D1.R0.S10: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N2.C2.D1.R0.S12: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N4.C2.D0.R1.S09: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N6.C1.D1.R0.S13: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N0.C1.D1.R0.S11: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N2.C2.D1.R0.S13: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N4.C2.D0.R1.S10: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N6.C1.D1.R0.S14: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N0.C1.D1.R0.S12: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N2.C2.D1.R0.S14: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N4.C2.D0.R1.S11: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N6.C1.D1.R0.S15: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N0.C1.D1.R0.S13: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N2.C2.D1.R0.S15: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N4.C2.D0.R1.S12: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N6.C1.D1.R0.S16: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N0.C1.D1.R0.S14: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N2.C2.D1.R0.S16: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N4.C2.D0.R1.S13: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N6.C1.D1.R0.S17: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N0.C1.D1.R0.S15: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N2.C2.D1.R0.S17: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N4.C2.D0.R1.S14: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N6.C1.D1.R0.S09: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N0.C1.D1.R0.S16: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N2.C2.D1.R0.S10: Preamble found at Latency = 007
N4.C2.D0.R1.S15: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N6.C1.D1.R0.S10: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N0.C1.D1.R0.S17: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N2.C2.D1.R0.S11: Preamble found at Latency = 007
N4.C2.D0.R1.S16: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N6.C1.D1.R0.S11: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N0.C1.D1.R0.S09: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N2.C2.D1.R0.S12: Preamble found at Latency = 007
N4.C2.D0.R1.S17: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N6.C1.D1.R0.S12: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N0.C1.D1.R0.S10: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N2.C2.D1.R0.S13: Preamble found at Latency = 007
N4.C2.D0.R1.S09: Preamble found at Latency = 008
N6.C1.D1.R0.S13: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N0.C1.D1.R0.S11: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N2.C2.D1.R0.S14: Preamble found at Latency = 007
N4.C2.D0.R1.S16: Preamble found at Latency = 008
N6.C1.D1.R0.S14: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N0.C1.D1.R0.S12: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N2.C2.D1.R0.S15: Preamble found at Latency = 007
N4.C2.D0.R1.S09: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N6.C1.D1.R0.S15: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N0.C1.D1.R0.S13: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N2.C2.D1.R0.S16: Preamble found at Latency = 007
N4.C2.D0.R1.S10: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N6.C1.D1.R0.S16: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N0.C1.D1.R0.S14: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N2.C2.D1.R0.S17: Preamble found at Latency = 007
N4.C2.D0.R1.S11: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N6.C1.D1.R0.S17: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N0.C1.D1.R0.S15: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N2.C2.D1.R0: Preamble found for all upper nibbles, adjusting Pi, Offset to center into preamble
N4.C2.D0.R1.S12: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N6.C1.D1.R0.S09: Preamble found at Latency = 008
N0.C1.D1.R0.S16: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N2.C2.D1.R0.S09: Total Receive Enable Delay = 1316
N4.C2.D0.R1.S13: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N6.C1.D1.R0.S10: Preamble found at Latency = 008
N0.C1.D1.R0.S17: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N2.C2.D1.R0.S10: Total Receive Enable Delay = 1291
N4.C2.D0.R1.S14: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N6.C1.D1.R0.S11: Preamble found at Latency = 008
N0.C1.D1.R0.S09: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N2.C2.D1.R0.S11: Total Receive Enable Delay = 1259
N4.C2.D0.R1.S15: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N6.C1.D1.R0.S14: Preamble found at Latency = 008
N0.C1.D1.R0.S10: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N2.C2.D1.R0.S12: Total Receive Enable Delay = 1242
N4.C2.D0.R1.S16: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N6.C1.D1.R0.S15: Preamble found at Latency = 008
N0.C1.D1.R0.S11: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N2.C2.D1.R0.S13: Total Receive Enable Delay = 1242
N4.C2.D0.R1.S17: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N6.C1.D1.R0.S16: Preamble found at Latency = 008
N0.C1.D1.R0.S12: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N2.C2.D1.R0.S14: Total Receive Enable Delay = 1254
N4.C2.D0.R1.S10: Preamble found at Latency = 007
N6.C1.D1.R0.S09: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N0.C1.D1.R0.S13: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N2.C2.D1.R0.S15: Total Receive Enable Delay = 1290
N4.C2.D0.R1.S11: Preamble found at Latency = 007
N6.C1.D1.R0.S10: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N0.C1.D1.R0.S14: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N2.C2.D1.R0.S16: Total Receive Enable Delay = 1308
N4.C2.D0.R1.S12: Preamble found at Latency = 007
N6.C1.D1.R0.S11: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N0.C1.D1.R0.S15: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N2.C2.D1.R0.S17: Total Receive Enable Delay = 1227
N4.C2.D0.R1.S13: Preamble found at Latency = 007
N6.C1.D1.R0.S12: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N0.C1.D1.R0.S16: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N2.C2.D1.R1: RcvEnFine: Initial RdCmd2RcvEnLatency = 10, Initial RdPtrOffsetRcvEn = 4
N4.C2.D0.R1.S14: Preamble found at Latency = 007
N6.C1.D1.R0.S13: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N0.C1.D1.R0.S17: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N2.C2.D1.R1.S00: Rcv En Fine Value = 259
N4.C2.D0.R1.S15: Preamble found at Latency = 007
N6.C1.D1.R0.S14: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N0.C1.D1.R0.S09: Preamble found at Latency = 008
N2.C2.D1.R1.S01: Rcv En Fine Value = 364
N4.C2.D0.R1.S17: Preamble found at Latency = 007
N6.C1.D1.R0.S15: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N0.C1.D1.R0.S10: Preamble found at Latency = 008
N2.C2.D1.R1.S02: Rcv En Fine Value = 331
N4.C2.D0.R1: Preamble found for all upper nibbles, adjusting Pi, Offset to center into preamble
N6.C1.D1.R0.S16: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N0.C1.D1.R0.S15: Preamble found at Latency = 008
N2.C2.D1.R1.S03: Rcv En Fine Value = 314
N4.C2.D0.R1.S09: Total Receive Enable Delay = 1324
N6.C1.D1.R0.S17: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N0.C1.D1.R0.S16: Preamble found at Latency = 008
N2.C2.D1.R1.S04: Rcv En Fine Value = 316
N4.C2.D0.R1.S10: Total Receive Enable Delay = 1305
N6.C1.D1.R0.S12: Preamble found at Latency = 007
N0.C1.D1.R0.S09: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N2.C2.D1.R1.S05: Rcv En Fine Value = 328
N4.C2.D0.R1.S11: Total Receive Enable Delay = 1272
N6.C1.D1.R0.S13: Preamble found at Latency = 007
N0.C1.D1.R0.S10: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N2.C2.D1.R1.S06: Rcv En Fine Value = 363
N4.C2.D0.R1.S12: Total Receive Enable Delay = 1251
N6.C1.D1.R0.S17: Preamble found at Latency = 007
N0.C1.D1.R0.S11: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N2.C2.D1.R1.S07: Rcv En Fine Value = 380
N4.C2.D0.R1.S13: Total Receive Enable Delay = 1252
N6.C1.D1.R0: Preamble found for all upper nibbles, adjusting Pi, Offset to center into preamble
N0.C1.D1.R0.S12: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N2.C2.D1.R1.S08: Rcv En Fine Value = 302
N4.C2.D0.R1.S14: Total Receive Enable Delay = 1266
N6.C1.D1.R0.S09: Total Receive Enable Delay = 1364
N0.C1.D1.R0.S13: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N2.C2.D1.R1.S09: Rcv En Fine Value = 257
N4.C2.D0.R1.S15: Total Receive Enable Delay = 1303
N6.C1.D1.R0.S10: Total Receive Enable Delay = 1344
N0.C1.D1.R0.S14: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N2.C2.D1.R1.S10: Rcv En Fine Value = 363
N4.C2.D0.R1.S16: Total Receive Enable Delay = 1319
N6.C1.D1.R0.S11: Total Receive Enable Delay = 1314
N0.C1.D1.R0.S15: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N2.C2.D1.R1.S11: Rcv En Fine Value = 332
N4.C2.D0.R1.S17: Total Receive Enable Delay = 1237
N6.C1.D1.R0.S12: Total Receive Enable Delay = 1295
N0.C1.D1.R0.S16: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N2.C2.D1.R1.S12: Rcv En Fine Value = 315
N4.C2.D1.R0: RcvEnFine: Initial RdCmd2RcvEnLatency = 10, Initial RdPtrOffsetRcvEn = 4
N6.C1.D1.R0.S13: Total Receive Enable Delay = 1286
N0.C1.D1.R0.S17: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N2.C2.D1.R1.S13: Rcv En Fine Value = 314
N4.C2.D1.R0.S00: Rcv En Fine Value = 382
N6.C1.D1.R0.S14: Total Receive Enable Delay = 1312
N0.C1.D1.R0.S11: Preamble found at Latency = 007
N2.C2.D1.R1.S14: Rcv En Fine Value = 325
N4.C2.D1.R0.S01: Rcv En Fine Value = 360
N6.C1.D1.R0.S15: Total Receive Enable Delay = 1336
N0.C1.D1.R0.S12: Preamble found at Latency = 007
N2.C2.D1.R1.S15: Rcv En Fine Value = 361
N4.C2.D1.R0.S02: Rcv En Fine Value = 331
N6.C1.D1.R0.S16: Total Receive Enable Delay = 1356
N0.C1.D1.R0.S13: Preamble found at Latency = 007
N2.C2.D1.R1.S16: Rcv En Fine Value = 256
N4.C2.D1.R0.S03: Rcv En Fine Value = 309
N6.C1.D1.R0.S17: Total Receive Enable Delay = 1273
N0.C1.D1.R0.S14: Preamble found at Latency = 007
N2.C2.D1.R1.S17: Rcv En Fine Value = 299
N4.C2.D1.R0.S04: Rcv En Fine Value = 309
N6.C1.D1.R1: RcvEnFine: Initial RdCmd2RcvEnLatency = 10, Initial RdPtrOffsetRcvEn = 4
N0.C1.D1.R0.S17: Preamble found at Latency = 007
N2.C2.D1.R1: Starting preamble search lower nibbles
N4.C2.D1.R0.S05: Rcv En Fine Value = 323
N6.C1.D1.R1.S00: Rcv En Fine Value = 311
N0.C1.D1.R0: Preamble found for all upper nibbles, adjusting Pi, Offset to center into preamble
N2.C2.D1.R1.S00: PI = 003, PtrOffset = 004
N4.C2.D1.R0.S06: Rcv En Fine Value = 360
N6.C1.D1.R1.S01: Rcv En Fine Value = 287
N0.C1.D1.R0.S09: Total Receive Enable Delay = 1357
N2.C2.D1.R1.S01: PI = 044, PtrOffset = 005
N4.C2.D1.R0.S07: Rcv En Fine Value = 374
N6.C1.D1.R1.S02: Rcv En Fine Value = 383
N0.C1.D1.R0.S10: Total Receive Enable Delay = 1333
N2.C2.D1.R1.S02: PI = 011, PtrOffset = 005
N4.C2.D1.R0.S08: Rcv En Fine Value = 298
N6.C1.D1.R1.S03: Rcv En Fine Value = 363
N0.C1.D1.R0.S11: Total Receive Enable Delay = 1307
N2.C2.D1.R1.S03: PI = 058, PtrOffset = 004
N4.C2.D1.R0.S09: Rcv En Fine Value = 383
N6.C1.D1.R1.S04: Rcv En Fine Value = 359
N0.C1.D1.R0.S12: Total Receive Enable Delay = 1286
N2.C2.D1.R1.S04: PI = 060, PtrOffset = 004
N4.C2.D1.R0.S10: Rcv En Fine Value = 357
N6.C1.D1.R1.S05: Rcv En Fine Value = 381
N0.C1.D1.R0.S13: Total Receive Enable Delay = 1280
N2.C2.D1.R1.S05: PI = 008, PtrOffset = 005
N4.C2.D1.R0.S11: Rcv En Fine Value = 328
N6.C1.D1.R1.S06: Rcv En Fine Value = 280
N0.C1.D1.R0.S14: Total Receive Enable Delay = 1306
N2.C2.D1.R1.S06: PI = 043, PtrOffset = 005
N4.C2.D1.R0.S12: Rcv En Fine Value = 308
N6.C1.D1.R1.S07: Rcv En Fine Value = 297
N0.C1.D1.R0.S15: Total Receive Enable Delay = 1328
N2.C2.D1.R1.S07: PI = 060, PtrOffset = 005
N4.C2.D1.R0.S13: Rcv En Fine Value = 308
N6.C1.D1.R1.S08: Rcv En Fine Value = 348
N0.C1.D1.R0.S16: Total Receive Enable Delay = 1351
N2.C2.D1.R1.S08: PI = 046, PtrOffset = 004
N4.C2.D1.R0.S14: Rcv En Fine Value = 324
N6.C1.D1.R1.S09: Rcv En Fine Value = 309
N0.C1.D1.R0.S17: Total Receive Enable Delay = 1270
N2.C2.D1.R1.S00: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N4.C2.D1.R0.S15: Rcv En Fine Value = 357
N6.C1.D1.R1.S10: Rcv En Fine Value = 290
N0.C1.D1.R1: RcvEnFine: Initial RdCmd2RcvEnLatency = 10, Initial RdPtrOffsetRcvEn = 4
N2.C2.D1.R1.S01: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N4.C2.D1.R0.S16: Rcv En Fine Value = 374
N6.C1.D1.R1.S11: Rcv En Fine Value = 383
N0.C1.D1.R1.S00: Rcv En Fine Value = 303
N2.C2.D1.R1.S02: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N4.C2.D1.R0.S17: Rcv En Fine Value = 293
N6.C1.D1.R1.S12: Rcv En Fine Value = 368
N0.C1.D1.R1.S01: Rcv En Fine Value = 280
N2.C2.D1.R1.S03: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N4.C2.D1.R0: Starting preamble search lower nibbles
N6.C1.D1.R1.S13: Rcv En Fine Value = 359
N0.C1.D1.R1.S02: Rcv En Fine Value = 378
N2.C2.D1.R1.S04: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N4.C2.D1.R0.S00: PI = 062, PtrOffset = 005
N6.C1.D1.R1.S14: Rcv En Fine Value = 382
N0.C1.D1.R1.S03: Rcv En Fine Value = 360
N2.C2.D1.R1.S05: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N4.C2.D1.R0.S01: PI = 040, PtrOffset = 005
N6.C1.D1.R1.S15: Rcv En Fine Value = 281
N0.C1.D1.R1.S04: Rcv En Fine Value = 350
N2.C2.D1.R1.S06: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N4.C2.D1.R0.S02: PI = 011, PtrOffset = 005
N6.C1.D1.R1.S16: Rcv En Fine Value = 302
N0.C1.D1.R1.S05: Rcv En Fine Value = 375
N2.C2.D1.R1.S07: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N4.C2.D1.R0.S03: PI = 053, PtrOffset = 004
N6.C1.D1.R1.S17: Rcv En Fine Value = 346
N0.C1.D1.R1.S06: Rcv En Fine Value = 272
N2.C2.D1.R1.S08: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N4.C2.D1.R0.S04: PI = 053, PtrOffset = 004
N6.C1.D1.R1: Starting preamble search lower nibbles
N0.C1.D1.R1.S07: Rcv En Fine Value = 293
N2.C2.D1.R1.S00: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N4.C2.D1.R0.S05: PI = 003, PtrOffset = 005
N6.C1.D1.R1.S00: PI = 055, PtrOffset = 004
N0.C1.D1.R1.S08: Rcv En Fine Value = 340
N2.C2.D1.R1.S01: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N4.C2.D1.R0.S06: PI = 040, PtrOffset = 005
N6.C1.D1.R1.S01: PI = 031, PtrOffset = 004
N0.C1.D1.R1.S09: Rcv En Fine Value = 301
N2.C2.D1.R1.S02: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N4.C2.D1.R0.S07: PI = 054, PtrOffset = 005
N6.C1.D1.R1.S02: PI = 063, PtrOffset = 005
N0.C1.D1.R1.S10: Rcv En Fine Value = 281
N2.C2.D1.R1.S03: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N4.C2.D1.R0.S08: PI = 042, PtrOffset = 004
N6.C1.D1.R1.S03: PI = 043, PtrOffset = 005
N0.C1.D1.R1.S11: Rcv En Fine Value = 378
N2.C2.D1.R1.S04: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N4.C2.D1.R0.S00: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N6.C1.D1.R1.S04: PI = 039, PtrOffset = 005
N0.C1.D1.R1.S12: Rcv En Fine Value = 359
N2.C2.D1.R1.S05: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N4.C2.D1.R0.S01: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N6.C1.D1.R1.S05: PI = 061, PtrOffset = 005
N0.C1.D1.R1.S13: Rcv En Fine Value = 353
N2.C2.D1.R1.S06: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N4.C2.D1.R0.S02: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N6.C1.D1.R1.S06: PI = 024, PtrOffset = 004
N0.C1.D1.R1.S14: Rcv En Fine Value = 378
N2.C2.D1.R1.S07: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N4.C2.D1.R0.S03: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N6.C1.D1.R1.S07: PI = 041, PtrOffset = 004
N0.C1.D1.R1.S15: Rcv En Fine Value = 273
N2.C2.D1.R1.S08: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N4.C2.D1.R0.S04: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N6.C1.D1.R1.S08: PI = 028, PtrOffset = 005
N0.C1.D1.R1.S16: Rcv En Fine Value = 294
N2.C2.D1.R1.S00: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N4.C2.D1.R0.S05: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N6.C1.D1.R1.S00: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N0.C1.D1.R1.S17: Rcv En Fine Value = 341
N2.C2.D1.R1.S01: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N4.C2.D1.R0.S06: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N6.C1.D1.R1.S01: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N0.C1.D1.R1: Starting preamble search lower nibbles
N2.C2.D1.R1.S02: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N4.C2.D1.R0.S07: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N6.C1.D1.R1.S02: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N0.C1.D1.R1.S00: PI = 047, PtrOffset = 004
N2.C2.D1.R1.S03: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N4.C2.D1.R0.S08: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N6.C1.D1.R1.S03: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N0.C1.D1.R1.S01: PI = 024, PtrOffset = 004
N2.C2.D1.R1.S04: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N4.C2.D1.R0.S00: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N6.C1.D1.R1.S04: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N0.C1.D1.R1.S02: PI = 058, PtrOffset = 005
N2.C2.D1.R1.S05: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N4.C2.D1.R0.S01: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N6.C1.D1.R1.S05: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N0.C1.D1.R1.S03: PI = 040, PtrOffset = 005
N2.C2.D1.R1.S06: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N4.C2.D1.R0.S02: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N6.C1.D1.R1.S06: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N0.C1.D1.R1.S04: PI = 030, PtrOffset = 005
N2.C2.D1.R1.S07: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N4.C2.D1.R0.S03: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N6.C1.D1.R1.S07: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N0.C1.D1.R1.S05: PI = 055, PtrOffset = 005
N2.C2.D1.R1.S08: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N4.C2.D1.R0.S04: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N6.C1.D1.R1.S08: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N0.C1.D1.R1.S06: PI = 016, PtrOffset = 004
N2.C2.D1.R1.S00: Preamble found at Latency = 008
N4.C2.D1.R0.S05: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N6.C1.D1.R1.S00: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N0.C1.D1.R1.S07: PI = 037, PtrOffset = 004
N2.C2.D1.R1.S00: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N4.C2.D1.R0.S06: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N6.C1.D1.R1.S01: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N0.C1.D1.R1.S08: PI = 020, PtrOffset = 005
N2.C2.D1.R1.S01: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N4.C2.D1.R0.S07: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N6.C1.D1.R1.S02: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N0.C1.D1.R1.S00: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N2.C2.D1.R1.S02: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N4.C2.D1.R0.S08: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N6.C1.D1.R1.S03: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N0.C1.D1.R1.S01: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N2.C2.D1.R1.S03: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N4.C2.D1.R0.S00: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N6.C1.D1.R1.S04: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N0.C1.D1.R1.S02: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N2.C2.D1.R1.S04: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N4.C2.D1.R0.S01: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N6.C1.D1.R1.S05: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N0.C1.D1.R1.S03: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N2.C2.D1.R1.S05: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N4.C2.D1.R0.S02: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N6.C1.D1.R1.S06: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N0.C1.D1.R1.S04: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N2.C2.D1.R1.S06: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N4.C2.D1.R0.S03: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N6.C1.D1.R1.S07: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N0.C1.D1.R1.S05: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N2.C2.D1.R1.S07: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N4.C2.D1.R0.S04: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N6.C1.D1.R1.S08: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N0.C1.D1.R1.S06: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N2.C2.D1.R1.S08: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N4.C2.D1.R0.S05: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N6.C1.D1.R1.S00: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N0.C1.D1.R1.S07: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N2.C2.D1.R1.S01: Preamble found at Latency = 007
N4.C2.D1.R0.S06: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N6.C1.D1.R1.S01: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N0.C1.D1.R1.S08: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N2.C2.D1.R1.S02: Preamble found at Latency = 007
N4.C2.D1.R0.S07: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N6.C1.D1.R1.S02: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N0.C1.D1.R1.S00: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N2.C2.D1.R1.S03: Preamble found at Latency = 007
N4.C2.D1.R0.S08: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N6.C1.D1.R1.S03: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N0.C1.D1.R1.S01: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N2.C2.D1.R1.S04: Preamble found at Latency = 007
N4.C2.D1.R0.S00: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N6.C1.D1.R1.S04: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N0.C1.D1.R1.S02: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N2.C2.D1.R1.S05: Preamble found at Latency = 007
N4.C2.D1.R0.S01: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N6.C1.D1.R1.S05: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N0.C1.D1.R1.S03: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N2.C2.D1.R1.S06: Preamble found at Latency = 007
N4.C2.D1.R0.S02: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N6.C1.D1.R1.S06: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N0.C1.D1.R1.S04: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N2.C2.D1.R1.S07: Preamble found at Latency = 007
N4.C2.D1.R0.S03: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N6.C1.D1.R1.S07: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N0.C1.D1.R1.S05: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N2.C2.D1.R1.S08: Preamble found at Latency = 007
N4.C2.D1.R0.S04: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N6.C1.D1.R1.S08: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N0.C1.D1.R1.S06: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N2.C2.D1.R1.S00: Total Receive Enable Delay = 1315
N4.C2.D1.R0.S05: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N6.C1.D1.R1.S00: Preamble found at Latency = 008
N0.C1.D1.R1.S07: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N2.C2.D1.R1.S01: Total Receive Enable Delay = 1292
N4.C2.D1.R0.S06: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N6.C1.D1.R1.S01: Preamble found at Latency = 008
N0.C1.D1.R1.S08: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N2.C2.D1.R1.S02: Total Receive Enable Delay = 1259
N4.C2.D1.R0.S07: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N6.C1.D1.R1.S06: Preamble found at Latency = 008
N0.C1.D1.R1.S00: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N2.C2.D1.R1.S03: Total Receive Enable Delay = 1242
N4.C2.D1.R0.S08: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N6.C1.D1.R1.S07: Preamble found at Latency = 008
N0.C1.D1.R1.S01: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N2.C2.D1.R1.S04: Total Receive Enable Delay = 1244
N4.C2.D1.R0.S00: Preamble found at Latency = 007
N6.C1.D1.R1.S00: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N0.C1.D1.R1.S02: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N2.C2.D1.R1.S05: Total Receive Enable Delay = 1256
N4.C2.D1.R0.S01: Preamble found at Latency = 007
N6.C1.D1.R1.S01: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N0.C1.D1.R1.S03: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N2.C2.D1.R1.S06: Total Receive Enable Delay = 1291
N4.C2.D1.R0.S02: Preamble found at Latency = 007
N6.C1.D1.R1.S02: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N0.C1.D1.R1.S04: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N2.C2.D1.R1.S07: Total Receive Enable Delay = 1308
N4.C2.D1.R0.S03: Preamble found at Latency = 007
N6.C1.D1.R1.S03: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N0.C1.D1.R1.S05: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N2.C2.D1.R1.S08: Total Receive Enable Delay = 1230
N4.C2.D1.R0.S04: Preamble found at Latency = 007
N6.C1.D1.R1.S04: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N0.C1.D1.R1.S06: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N2.C2.D1.R1: Starting preamble search upper nibbles
N4.C2.D1.R0.S05: Preamble found at Latency = 007
N6.C1.D1.R1.S05: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N0.C1.D1.R1.S07: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N2.C2.D1.R1.S09: PI = 001, PtrOffset = 004
N4.C2.D1.R0.S06: Preamble found at Latency = 007
N6.C1.D1.R1.S06: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N0.C1.D1.R1.S08: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N2.C2.D1.R1.S10: PI = 043, PtrOffset = 005
N4.C2.D1.R0.S07: Preamble found at Latency = 007
N6.C1.D1.R1.S07: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N0.C1.D1.R1.S00: Preamble found at Latency = 008
N2.C2.D1.R1.S11: PI = 012, PtrOffset = 005
N4.C2.D1.R0.S08: Preamble found at Latency = 007
N6.C1.D1.R1.S08: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N0.C1.D1.R1.S01: Preamble found at Latency = 008
N2.C2.D1.R1.S12: PI = 059, PtrOffset = 004
N4.C2.D1.R0.S00: Total Receive Enable Delay = 1310
N6.C1.D1.R1.S02: Preamble found at Latency = 007
N0.C1.D1.R1.S06: Preamble found at Latency = 008
N2.C2.D1.R1.S13: PI = 058, PtrOffset = 004
N4.C2.D1.R0.S01: Total Receive Enable Delay = 1288
N6.C1.D1.R1.S03: Preamble found at Latency = 007
N0.C1.D1.R1.S07: Preamble found at Latency = 008
N2.C2.D1.R1.S14: PI = 005, PtrOffset = 005
N4.C2.D1.R0.S02: Total Receive Enable Delay = 1259
N6.C1.D1.R1.S04: Preamble found at Latency = 007
N0.C1.D1.R1.S00: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N2.C2.D1.R1.S15: PI = 041, PtrOffset = 005
N4.C2.D1.R0.S03: Total Receive Enable Delay = 1237
N6.C1.D1.R1.S05: Preamble found at Latency = 007
N0.C1.D1.R1.S01: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N2.C2.D1.R1.S16: PI = 000, PtrOffset = 004
N4.C2.D1.R0.S04: Total Receive Enable Delay = 1237
N6.C1.D1.R1.S08: Preamble found at Latency = 007
N0.C1.D1.R1.S02: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N2.C2.D1.R1.S17: PI = 043, PtrOffset = 004
N4.C2.D1.R0.S05: Total Receive Enable Delay = 1251
N6.C1.D1.R1.S00: Total Receive Enable Delay = 1367
N0.C1.D1.R1.S03: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N2.C2.D1.R1.S09: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N4.C2.D1.R0.S06: Total Receive Enable Delay = 1288
N6.C1.D1.R1.S01: Total Receive Enable Delay = 1343
N0.C1.D1.R1.S04: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N2.C2.D1.R1.S10: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N4.C2.D1.R0.S07: Total Receive Enable Delay = 1302
N6.C1.D1.R1.S02: Total Receive Enable Delay = 1311
N0.C1.D1.R1.S05: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N2.C2.D1.R1.S11: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N4.C2.D1.R0.S08: Total Receive Enable Delay = 1226
N6.C1.D1.R1.S03: Total Receive Enable Delay = 1291
N0.C1.D1.R1.S06: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N2.C2.D1.R1.S12: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N4.C2.D1.R0: Starting preamble search upper nibbles
N6.C1.D1.R1.S04: Total Receive Enable Delay = 1287
N0.C1.D1.R1.S07: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N2.C2.D1.R1.S13: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N4.C2.D1.R0.S09: PI = 063, PtrOffset = 005
N6.C1.D1.R1.S05: Total Receive Enable Delay = 1309
N0.C1.D1.R1.S08: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N2.C2.D1.R1.S14: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N4.C2.D1.R0.S10: PI = 037, PtrOffset = 005
N6.C1.D1.R1.S06: Total Receive Enable Delay = 1336
N0.C1.D1.R1.S02: Preamble found at Latency = 007
N2.C2.D1.R1.S15: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N4.C2.D1.R0.S11: PI = 008, PtrOffset = 005
N6.C1.D1.R1.S07: Total Receive Enable Delay = 1353
N0.C1.D1.R1.S03: Preamble found at Latency = 007
N2.C2.D1.R1.S16: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N4.C2.D1.R0.S12: PI = 052, PtrOffset = 004
N6.C1.D1.R1.S08: Total Receive Enable Delay = 1276
N0.C1.D1.R1.S04: Preamble found at Latency = 007
N2.C2.D1.R1.S17: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N4.C2.D1.R0.S13: PI = 052, PtrOffset = 004
N6.C1.D1.R1: Starting preamble search upper nibbles
N0.C1.D1.R1.S05: Preamble found at Latency = 007
N2.C2.D1.R1.S09: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N4.C2.D1.R0.S14: PI = 004, PtrOffset = 005
N6.C1.D1.R1.S09: PI = 053, PtrOffset = 004
N0.C1.D1.R1.S08: Preamble found at Latency = 007
N2.C2.D1.R1.S10: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N4.C2.D1.R0.S15: PI = 037, PtrOffset = 005
N6.C1.D1.R1.S10: PI = 034, PtrOffset = 004
N0.C1.D1.R1.S00: Total Receive Enable Delay = 1359
N2.C2.D1.R1.S11: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N4.C2.D1.R0.S16: PI = 054, PtrOffset = 005
N6.C1.D1.R1.S11: PI = 063, PtrOffset = 005
N0.C1.D1.R1.S01: Total Receive Enable Delay = 1336
N2.C2.D1.R1.S12: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N4.C2.D1.R0.S17: PI = 037, PtrOffset = 004
N6.C1.D1.R1.S12: PI = 048, PtrOffset = 005
N0.C1.D1.R1.S02: Total Receive Enable Delay = 1306
N2.C2.D1.R1.S13: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N4.C2.D1.R0.S09: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N6.C1.D1.R1.S13: PI = 039, PtrOffset = 005
N0.C1.D1.R1.S03: Total Receive Enable Delay = 1288
N2.C2.D1.R1.S14: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N4.C2.D1.R0.S10: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N6.C1.D1.R1.S14: PI = 062, PtrOffset = 005
N0.C1.D1.R1.S04: Total Receive Enable Delay = 1278
N2.C2.D1.R1.S15: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N4.C2.D1.R0.S11: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N6.C1.D1.R1.S15: PI = 025, PtrOffset = 004
N0.C1.D1.R1.S05: Total Receive Enable Delay = 1303
N2.C2.D1.R1.S16: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N4.C2.D1.R0.S12: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N6.C1.D1.R1.S16: PI = 046, PtrOffset = 004
N0.C1.D1.R1.S06: Total Receive Enable Delay = 1328
N2.C2.D1.R1.S17: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N4.C2.D1.R0.S13: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N6.C1.D1.R1.S17: PI = 026, PtrOffset = 005
N0.C1.D1.R1.S07: Total Receive Enable Delay = 1349
N2.C2.D1.R1.S09: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N4.C2.D1.R0.S14: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N6.C1.D1.R1.S09: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N0.C1.D1.R1.S08: Total Receive Enable Delay = 1268
N2.C2.D1.R1.S10: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N4.C2.D1.R0.S15: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N6.C1.D1.R1.S10: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N0.C1.D1.R1: Starting preamble search upper nibbles
N2.C2.D1.R1.S11: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N4.C2.D1.R0.S16: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N6.C1.D1.R1.S11: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N0.C1.D1.R1.S09: PI = 045, PtrOffset = 004
N2.C2.D1.R1.S12: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N4.C2.D1.R0.S17: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N6.C1.D1.R1.S12: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N0.C1.D1.R1.S10: PI = 025, PtrOffset = 004
N2.C2.D1.R1.S13: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N4.C2.D1.R0.S09: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N6.C1.D1.R1.S13: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N0.C1.D1.R1.S11: PI = 058, PtrOffset = 005
N2.C2.D1.R1.S14: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N4.C2.D1.R0.S10: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N6.C1.D1.R1.S14: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N0.C1.D1.R1.S12: PI = 039, PtrOffset = 005
N2.C2.D1.R1.S15: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N4.C2.D1.R0.S11: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N6.C1.D1.R1.S15: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N0.C1.D1.R1.S13: PI = 033, PtrOffset = 005
N2.C2.D1.R1.S16: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N4.C2.D1.R0.S12: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N6.C1.D1.R1.S16: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N0.C1.D1.R1.S14: PI = 058, PtrOffset = 005
N2.C2.D1.R1.S17: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N4.C2.D1.R0.S13: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N6.C1.D1.R1.S17: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N0.C1.D1.R1.S15: PI = 017, PtrOffset = 004
N2.C2.D1.R1.S09: Preamble found at Latency = 008
N4.C2.D1.R0.S14: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N6.C1.D1.R1.S09: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N0.C1.D1.R1.S16: PI = 038, PtrOffset = 004
N2.C2.D1.R1.S16: Preamble found at Latency = 008
N4.C2.D1.R0.S15: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N6.C1.D1.R1.S10: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N0.C1.D1.R1.S17: PI = 021, PtrOffset = 005
N2.C2.D1.R1.S09: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N4.C2.D1.R0.S16: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N6.C1.D1.R1.S11: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N0.C1.D1.R1.S09: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N2.C2.D1.R1.S10: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N4.C2.D1.R0.S17: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N6.C1.D1.R1.S12: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N0.C1.D1.R1.S10: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N2.C2.D1.R1.S11: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N4.C2.D1.R0.S09: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N6.C1.D1.R1.S13: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N0.C1.D1.R1.S11: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N2.C2.D1.R1.S12: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N4.C2.D1.R0.S10: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N6.C1.D1.R1.S14: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N0.C1.D1.R1.S12: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N2.C2.D1.R1.S13: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N4.C2.D1.R0.S11: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N6.C1.D1.R1.S15: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N0.C1.D1.R1.S13: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N2.C2.D1.R1.S14: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N4.C2.D1.R0.S12: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N6.C1.D1.R1.S16: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N0.C1.D1.R1.S14: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N2.C2.D1.R1.S15: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N4.C2.D1.R0.S13: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N6.C1.D1.R1.S17: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N0.C1.D1.R1.S15: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N2.C2.D1.R1.S16: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N4.C2.D1.R0.S14: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N6.C1.D1.R1.S09: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N0.C1.D1.R1.S16: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N2.C2.D1.R1.S17: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N4.C2.D1.R0.S15: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N6.C1.D1.R1.S10: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N0.C1.D1.R1.S17: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N2.C2.D1.R1.S10: Preamble found at Latency = 007
N4.C2.D1.R0.S16: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N6.C1.D1.R1.S11: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N0.C1.D1.R1.S09: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N2.C2.D1.R1.S11: Preamble found at Latency = 007
N4.C2.D1.R0.S17: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N6.C1.D1.R1.S12: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N0.C1.D1.R1.S10: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N2.C2.D1.R1.S12: Preamble found at Latency = 007
N4.C2.D1.R0.S09: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N6.C1.D1.R1.S13: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N0.C1.D1.R1.S11: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N2.C2.D1.R1.S13: Preamble found at Latency = 007
N4.C2.D1.R0.S10: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N6.C1.D1.R1.S14: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N0.C1.D1.R1.S12: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N2.C2.D1.R1.S14: Preamble found at Latency = 007
N4.C2.D1.R0.S11: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N6.C1.D1.R1.S15: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N0.C1.D1.R1.S13: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N2.C2.D1.R1.S15: Preamble found at Latency = 007
N4.C2.D1.R0.S12: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N6.C1.D1.R1.S16: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N0.C1.D1.R1.S14: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N2.C2.D1.R1.S17: Preamble found at Latency = 007
N4.C2.D1.R0.S13: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N6.C1.D1.R1.S17: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N0.C1.D1.R1.S15: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N2.C2.D1.R1: Preamble found for all upper nibbles, adjusting Pi, Offset to center into preamble
N4.C2.D1.R0.S14: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N6.C1.D1.R1.S09: Preamble found at Latency = 008
N0.C1.D1.R1.S16: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N2.C2.D1.R1.S09: Total Receive Enable Delay = 1313
N4.C2.D1.R0.S15: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N6.C1.D1.R1.S10: Preamble found at Latency = 008
N0.C1.D1.R1.S17: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N2.C2.D1.R1.S10: Total Receive Enable Delay = 1291
N4.C2.D1.R0.S16: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N6.C1.D1.R1.S15: Preamble found at Latency = 008
N0.C1.D1.R1.S09: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N2.C2.D1.R1.S11: Total Receive Enable Delay = 1260
N4.C2.D1.R0.S17: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N6.C1.D1.R1.S16: Preamble found at Latency = 008
N0.C1.D1.R1.S10: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N2.C2.D1.R1.S12: Total Receive Enable Delay = 1243
N4.C2.D1.R0.S09: Preamble found at Latency = 007
N6.C1.D1.R1.S09: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N0.C1.D1.R1.S11: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N2.C2.D1.R1.S13: Total Receive Enable Delay = 1242
N4.C2.D1.R0.S10: Preamble found at Latency = 007
N6.C1.D1.R1.S10: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N0.C1.D1.R1.S12: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N2.C2.D1.R1.S14: Total Receive Enable Delay = 1253
N4.C2.D1.R0.S11: Preamble found at Latency = 007
N6.C1.D1.R1.S11: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N0.C1.D1.R1.S13: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N2.C2.D1.R1.S15: Total Receive Enable Delay = 1289
N4.C2.D1.R0.S12: Preamble found at Latency = 007
N6.C1.D1.R1.S12: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N0.C1.D1.R1.S14: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N2.C2.D1.R1.S16: Total Receive Enable Delay = 1312
N4.C2.D1.R0.S13: Preamble found at Latency = 007
N6.C1.D1.R1.S13: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N0.C1.D1.R1.S15: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N2.C2.D1.R1.S17: Total Receive Enable Delay = 1227
N4.C2.D1.R0.S14: Preamble found at Latency = 007
N6.C1.D1.R1.S14: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N0.C1.D1.R1.S16: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
START_DATA_REC_EN
N4.C2.D1.R0.S15: Preamble found at Latency = 007
N6.C1.D1.R1.S15: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N0.C1.D1.R1.S17: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N2.C2.S00: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N4.C2.D1.R0.S16: Preamble found at Latency = 007
N6.C1.D1.R1.S16: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N0.C1.D1.R1.S09: Preamble found at Latency = 008
N2.C2.S01: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N4.C2.D1.R0.S17: Preamble found at Latency = 007
N6.C1.D1.R1.S17: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N0.C1.D1.R1.S10: Preamble found at Latency = 008
N2.C2.S02: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 5
N4.C2.D1.R0: Preamble found for all upper nibbles, adjusting Pi, Offset to center into preamble
N6.C1.D1.R1.S11: Preamble found at Latency = 007
N0.C1.D1.R1.S15: Preamble found at Latency = 008
N2.C2.S03: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 5
N4.C2.D1.R0.S09: Total Receive Enable Delay = 1311
N6.C1.D1.R1.S12: Preamble found at Latency = 007
N0.C1.D1.R1.S16: Preamble found at Latency = 008
N2.C2.S04: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 5
N4.C2.D1.R0.S10: Total Receive Enable Delay = 1285
N6.C1.D1.R1.S13: Preamble found at Latency = 007
N0.C1.D1.R1.S09: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N2.C2.S05: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 5
N4.C2.D1.R0.S11: Total Receive Enable Delay = 1256
N6.C1.D1.R1.S14: Preamble found at Latency = 007
N0.C1.D1.R1.S10: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N2.C2.S06: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N4.C2.D1.R0.S12: Total Receive Enable Delay = 1236
N6.C1.D1.R1.S17: Preamble found at Latency = 007
N0.C1.D1.R1.S11: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N2.C2.S07: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N4.C2.D1.R0.S13: Total Receive Enable Delay = 1236
N6.C1.D1.R1: Preamble found for all upper nibbles, adjusting Pi, Offset to center into preamble
N0.C1.D1.R1.S12: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N2.C2.S08: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 5
N4.C2.D1.R0.S14: Total Receive Enable Delay = 1252
N6.C1.D1.R1.S09: Total Receive Enable Delay = 1365
N0.C1.D1.R1.S13: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N2.C2.S09: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N4.C2.D1.R0.S15: Total Receive Enable Delay = 1285
N6.C1.D1.R1.S10: Total Receive Enable Delay = 1346
N0.C1.D1.R1.S14: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N2.C2.S10: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N4.C2.D1.R0.S16: Total Receive Enable Delay = 1302
N6.C1.D1.R1.S11: Total Receive Enable Delay = 1311
N0.C1.D1.R1.S15: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N2.C2.S11: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 5
N4.C2.D1.R0.S17: Total Receive Enable Delay = 1221
N6.C1.D1.R1.S12: Total Receive Enable Delay = 1296
N0.C1.D1.R1.S16: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N2.C2.S12: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 5
N4.C2.D1.R1: RcvEnFine: Initial RdCmd2RcvEnLatency = 10, Initial RdPtrOffsetRcvEn = 4
N6.C1.D1.R1.S13: Total Receive Enable Delay = 1287
N0.C1.D1.R1.S17: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N2.C2.S13: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 5
N4.C2.D1.R1.S00: Rcv En Fine Value = 383
N6.C1.D1.R1.S14: Total Receive Enable Delay = 1310
N0.C1.D1.R1.S11: Preamble found at Latency = 007
N2.C2.S14: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 5
N4.C2.D1.R1.S01: Rcv En Fine Value = 359
N6.C1.D1.R1.S15: Total Receive Enable Delay = 1337
N0.C1.D1.R1.S12: Preamble found at Latency = 007
N2.C2.S15: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N4.C2.D1.R1.S02: Rcv En Fine Value = 330
N6.C1.D1.R1.S16: Total Receive Enable Delay = 1358
N0.C1.D1.R1.S13: Preamble found at Latency = 007
N2.C2.S16: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N4.C2.D1.R1.S03: Rcv En Fine Value = 303
N6.C1.D1.R1.S17: Total Receive Enable Delay = 1274
N0.C1.D1.R1.S14: Preamble found at Latency = 007
N2.C2.S17: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 5
N4.C2.D1.R1.S04: Rcv En Fine Value = 311
START_DATA_REC_EN
N0.C1.D1.R1.S17: Preamble found at Latency = 007
N2.C2.D0.R0.S00: RcvEn: plus1 = 1, minus1 = 0, PI = 50, DB = 1
N4.C2.D1.R1.S05: Rcv En Fine Value = 320
N6.C1.S00: RdCmd2RcvEnLatency = 9, RdPtrOffsetRcvEn = 5
N0.C1.D1.R1: Preamble found for all upper nibbles, adjusting Pi, Offset to center into preamble
N2.C2.D0.R0.S01: RcvEn: plus1 = 1, minus1 = 0, PI = 29, DB = 0
N4.C2.D1.R1.S06: Rcv En Fine Value = 359
N6.C1.S01: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N0.C1.D1.R1.S09: Total Receive Enable Delay = 1357
N2.C2.D0.R0.S02: RcvEn: plus1 = 1, minus1 = 0, PI = 61, DB = 1
N4.C2.D1.R1.S07: Rcv En Fine Value = 374
N6.C1.S02: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N0.C1.D1.R1.S10: Total Receive Enable Delay = 1337
N2.C2.D0.R0.S03: RcvEn: plus1 = 1, minus1 = 0, PI = 42, DB = 0
N4.C2.D1.R1.S08: Rcv En Fine Value = 296
N6.C1.S03: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N0.C1.D1.R1.S11: Total Receive Enable Delay = 1306
N2.C2.D0.R0.S04: RcvEn: plus1 = 1, minus1 = 0, PI = 42, DB = 0
N4.C2.D1.R1.S09: Rcv En Fine Value = 380
N6.C1.S04: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N0.C1.D1.R1.S12: Total Receive Enable Delay = 1287
N2.C2.D0.R0.S05: RcvEn: plus1 = 1, minus1 = 0, PI = 55, DB = 1
N4.C2.D1.R1.S10: Rcv En Fine Value = 357
N6.C1.S05: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N0.C1.D1.R1.S13: Total Receive Enable Delay = 1281
N2.C2.D0.R0.S06: RcvEn: plus1 = 1, minus1 = 0, PI = 27, DB = 0
N4.C2.D1.R1.S11: Rcv En Fine Value = 327
N6.C1.S06: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N0.C1.D1.R1.S14: Total Receive Enable Delay = 1306
N2.C2.D0.R0.S07: RcvEn: plus1 = 1, minus1 = 0, PI = 46, DB = 0
N4.C2.D1.R1.S12: Rcv En Fine Value = 305
N6.C1.S07: RdCmd2RcvEnLatency = 9, RdPtrOffsetRcvEn = 5
N0.C1.D1.R1.S15: Total Receive Enable Delay = 1329
N2.C2.D0.R0.S08: RcvEn: plus1 = 1, minus1 = 0, PI = 29, DB = 0
N4.C2.D1.R1.S13: Rcv En Fine Value = 309
N6.C1.S08: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 5
N0.C1.D1.R1.S16: Total Receive Enable Delay = 1350
N2.C2.D0.R0.S09: RcvEn: plus1 = 1, minus1 = 0, PI = 50, DB = 1
N4.C2.D1.R1.S14: Rcv En Fine Value = 323
N6.C1.S09: RdCmd2RcvEnLatency = 9, RdPtrOffsetRcvEn = 5
N0.C1.D1.R1.S17: Total Receive Enable Delay = 1269
N2.C2.D0.R0.S10: RcvEn: plus1 = 1, minus1 = 0, PI = 28, DB = 0
N4.C2.D1.R1.S15: Rcv En Fine Value = 357
N6.C1.S10: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
START_DATA_REC_EN
N2.C2.D0.R0.S11: RcvEn: plus1 = 1, minus1 = 0, PI = 61, DB = 1
N4.C2.D1.R1.S16: Rcv En Fine Value = 371
N6.C1.S11: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N0.C1.S00: RdCmd2RcvEnLatency = 9, RdPtrOffsetRcvEn = 5
N2.C2.D0.R0.S12: RcvEn: plus1 = 1, minus1 = 0, PI = 43, DB = 0
N4.C2.D1.R1.S17: Rcv En Fine Value = 293
N6.C1.S12: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N0.C1.S01: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N2.C2.D0.R0.S13: RcvEn: plus1 = 1, minus1 = 0, PI = 42, DB = 0
N4.C2.D1.R1: Starting preamble search lower nibbles
N6.C1.S13: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N0.C1.S02: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N2.C2.D0.R0.S14: RcvEn: plus1 = 1, minus1 = 0, PI = 52, DB = 1
N4.C2.D1.R1.S00: PI = 063, PtrOffset = 005
N6.C1.S14: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N0.C1.S03: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N2.C2.D0.R0.S15: RcvEn: plus1 = 1, minus1 = 0, PI = 25, DB = 0
N4.C2.D1.R1.S01: PI = 039, PtrOffset = 005
N6.C1.S15: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N0.C1.S04: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 5
N2.C2.D0.R0.S16: RcvEn: plus1 = 1, minus1 = 0, PI = 45, DB = 0
N4.C2.D1.R1.S02: PI = 010, PtrOffset = 005
N6.C1.S16: RdCmd2RcvEnLatency = 9, RdPtrOffsetRcvEn = 5
N0.C1.S05: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N2.C2.D0.R0.S17: RcvEn: plus1 = 1, minus1 = 0, PI = 24, DB = 0
N4.C2.D1.R1.S03: PI = 047, PtrOffset = 004
N6.C1.S17: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 5
N0.C1.S06: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N2.C2.D0.R1.S00: RcvEn: plus1 = 1, minus1 = 0, PI = 50, DB = 1
N4.C2.D1.R1.S04: PI = 055, PtrOffset = 004
N6.C1.D0.R0.S00: RcvEn: plus1 = 1, minus1 = 0, PI = 36, DB = 0
N0.C1.S07: RdCmd2RcvEnLatency = 9, RdPtrOffsetRcvEn = 5
N2.C2.D0.R1.S01: RcvEn: plus1 = 1, minus1 = 0, PI = 29, DB = 0
N4.C2.D1.R1.S05: PI = 000, PtrOffset = 005
N6.C1.D0.R0.S01: RcvEn: plus1 = 0, minus1 = 1, PI = 16, DB = 0
N0.C1.S08: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 5
N2.C2.D0.R1.S02: RcvEn: plus1 = 1, minus1 = 0, PI = 61, DB = 1
N4.C2.D1.R1.S06: PI = 039, PtrOffset = 005
N6.C1.D0.R0.S02: RcvEn: plus1 = 1, minus1 = 0, PI = 49, DB = 1
N0.C1.S09: RdCmd2RcvEnLatency = 9, RdPtrOffsetRcvEn = 5
N2.C2.D0.R1.S03: RcvEn: plus1 = 1, minus1 = 0, PI = 42, DB = 0
N4.C2.D1.R1.S07: PI = 054, PtrOffset = 005
N6.C1.D0.R0.S03: RcvEn: plus1 = 1, minus1 = 0, PI = 29, DB = 0
N0.C1.S10: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N2.C2.D0.R1.S04: RcvEn: plus1 = 1, minus1 = 0, PI = 42, DB = 0
N4.C2.D1.R1.S08: PI = 040, PtrOffset = 004
N6.C1.D0.R0.S04: RcvEn: plus1 = 1, minus1 = 0, PI = 21, DB = 0
N0.C1.S11: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N2.C2.D0.R1.S05: RcvEn: plus1 = 1, minus1 = 0, PI = 55, DB = 1
N4.C2.D1.R1.S00: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N6.C1.D0.R0.S05: RcvEn: plus1 = 1, minus1 = 0, PI = 46, DB = 0
N0.C1.S12: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N2.C2.D0.R1.S06: RcvEn: plus1 = 1, minus1 = 0, PI = 27, DB = 0
N4.C2.D1.R1.S01: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N6.C1.D0.R0.S06: RcvEn: plus1 = 0, minus1 = 1, PI = 05, DB = 1
N0.C1.S13: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 5
N2.C2.D0.R1.S07: RcvEn: plus1 = 1, minus1 = 0, PI = 46, DB = 0
N4.C2.D1.R1.S02: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N6.C1.D0.R0.S07: RcvEn: plus1 = 1, minus1 = 0, PI = 28, DB = 0
N0.C1.S14: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N2.C2.D0.R1.S08: RcvEn: plus1 = 1, minus1 = 0, PI = 29, DB = 0
N4.C2.D1.R1.S03: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N6.C1.D0.R0.S08: RcvEn: plus1 = 0, minus1 = 1, PI = 10, DB = 1
N0.C1.S15: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N2.C2.D0.R1.S09: RcvEn: plus1 = 1, minus1 = 0, PI = 50, DB = 1
N4.C2.D1.R1.S04: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N6.C1.D0.R0.S09: RcvEn: plus1 = 1, minus1 = 0, PI = 35, DB = 0
N0.C1.S16: RdCmd2RcvEnLatency = 9, RdPtrOffsetRcvEn = 5
N2.C2.D0.R1.S10: RcvEn: plus1 = 1, minus1 = 0, PI = 28, DB = 0
N4.C2.D1.R1.S05: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N6.C1.D0.R0.S10: RcvEn: plus1 = 0, minus1 = 1, PI = 16, DB = 0
N0.C1.S17: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 5
N2.C2.D0.R1.S11: RcvEn: plus1 = 1, minus1 = 0, PI = 61, DB = 1
N4.C2.D1.R1.S06: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N6.C1.D0.R0.S11: RcvEn: plus1 = 1, minus1 = 0, PI = 48, DB = 0
N0.C1.D0.R0.S00: RcvEn: plus1 = 1, minus1 = 0, PI = 32, DB = 0
N2.C2.D0.R1.S12: RcvEn: plus1 = 1, minus1 = 0, PI = 43, DB = 0
N4.C2.D1.R1.S07: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N6.C1.D0.R0.S12: RcvEn: plus1 = 1, minus1 = 0, PI = 30, DB = 0
N0.C1.D0.R0.S01: RcvEn: plus1 = 0, minus1 = 1, PI = 08, DB = 1
N2.C2.D0.R1.S13: RcvEn: plus1 = 1, minus1 = 0, PI = 42, DB = 0
N4.C2.D1.R1.S08: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N6.C1.D0.R0.S13: RcvEn: plus1 = 1, minus1 = 0, PI = 24, DB = 0
N0.C1.D0.R0.S02: RcvEn: plus1 = 1, minus1 = 0, PI = 41, DB = 0
N2.C2.D0.R1.S14: RcvEn: plus1 = 1, minus1 = 0, PI = 52, DB = 1
N4.C2.D1.R1.S00: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N6.C1.D0.R0.S14: RcvEn: plus1 = 1, minus1 = 0, PI = 46, DB = 0
N0.C1.D0.R0.S03: RcvEn: plus1 = 1, minus1 = 0, PI = 24, DB = 0
N2.C2.D0.R1.S15: RcvEn: plus1 = 1, minus1 = 0, PI = 25, DB = 0
N4.C2.D1.R1.S01: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N6.C1.D0.R0.S15: RcvEn: plus1 = 0, minus1 = 1, PI = 07, DB = 1
N0.C1.D0.R0.S04: RcvEn: plus1 = 0, minus1 = 1, PI = 14, DB = 1
N2.C2.D0.R1.S16: RcvEn: plus1 = 1, minus1 = 0, PI = 45, DB = 0
N4.C2.D1.R1.S02: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N6.C1.D0.R0.S16: RcvEn: plus1 = 1, minus1 = 0, PI = 28, DB = 0
N0.C1.D0.R0.S05: RcvEn: plus1 = 1, minus1 = 0, PI = 41, DB = 0
N2.C2.D0.R1.S17: RcvEn: plus1 = 1, minus1 = 0, PI = 24, DB = 0
N4.C2.D1.R1.S03: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N6.C1.D0.R0.S17: RcvEn: plus1 = 0, minus1 = 1, PI = 10, DB = 1
N0.C1.D0.R0.S06: RcvEn: plus1 = 0, minus1 = 1, PI = 00, DB = 1
N2.C2.D1.R0.S00: RcvEn: plus1 = 1, minus1 = 0, PI = 33, DB = 0
N4.C2.D1.R1.S04: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N6.C1.D0.R1.S00: RcvEn: plus1 = 1, minus1 = 0, PI = 36, DB = 0
N0.C1.D0.R0.S07: RcvEn: plus1 = 1, minus1 = 0, PI = 24, DB = 0
N2.C2.D1.R0.S01: RcvEn: plus1 = 1, minus1 = 0, PI = 11, DB = 1
N4.C2.D1.R1.S05: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N6.C1.D0.R1.S01: RcvEn: plus1 = 0, minus1 = 1, PI = 16, DB = 0
N0.C1.D0.R0.S08: RcvEn: plus1 = 0, minus1 = 1, PI = 03, DB = 1
N2.C2.D1.R0.S02: RcvEn: plus1 = 1, minus1 = 0, PI = 43, DB = 0
N4.C2.D1.R1.S06: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N6.C1.D0.R1.S02: RcvEn: plus1 = 1, minus1 = 0, PI = 49, DB = 1
N0.C1.D0.R0.S09: RcvEn: plus1 = 1, minus1 = 0, PI = 31, DB = 0
N2.C2.D1.R0.S03: RcvEn: plus1 = 1, minus1 = 0, PI = 28, DB = 0
N4.C2.D1.R1.S07: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N6.C1.D0.R1.S03: RcvEn: plus1 = 1, minus1 = 0, PI = 29, DB = 0
N0.C1.D0.R0.S10: RcvEn: plus1 = 0, minus1 = 1, PI = 09, DB = 1
N2.C2.D1.R0.S04: RcvEn: plus1 = 1, minus1 = 0, PI = 27, DB = 0
N4.C2.D1.R1.S08: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N6.C1.D0.R1.S04: RcvEn: plus1 = 1, minus1 = 0, PI = 21, DB = 0
N0.C1.D0.R0.S11: RcvEn: plus1 = 1, minus1 = 0, PI = 43, DB = 0
N2.C2.D1.R0.S05: RcvEn: plus1 = 1, minus1 = 0, PI = 40, DB = 0
N4.C2.D1.R1.S00: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N6.C1.D0.R1.S05: RcvEn: plus1 = 1, minus1 = 0, PI = 46, DB = 0
N0.C1.D0.R0.S12: RcvEn: plus1 = 1, minus1 = 0, PI = 24, DB = 0
N2.C2.D1.R0.S06: RcvEn: plus1 = 1, minus1 = 0, PI = 11, DB = 1
N4.C2.D1.R1.S01: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N6.C1.D0.R1.S06: RcvEn: plus1 = 0, minus1 = 1, PI = 05, DB = 1
N0.C1.D0.R0.S13: RcvEn: plus1 = 0, minus1 = 1, PI = 15, DB = 1
N2.C2.D1.R0.S07: RcvEn: plus1 = 1, minus1 = 0, PI = 29, DB = 0
N4.C2.D1.R1.S02: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N6.C1.D0.R1.S07: RcvEn: plus1 = 1, minus1 = 0, PI = 28, DB = 0
N0.C1.D0.R0.S14: RcvEn: plus1 = 1, minus1 = 0, PI = 41, DB = 0
N2.C2.D1.R0.S08: RcvEn: plus1 = 1, minus1 = 0, PI = 14, DB = 1
N4.C2.D1.R1.S03: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N6.C1.D0.R1.S08: RcvEn: plus1 = 0, minus1 = 1, PI = 10, DB = 1
N0.C1.D0.R0.S15: RcvEn: plus1 = 0, minus1 = 1, PI = 00, DB = 1
N2.C2.D1.R0.S09: RcvEn: plus1 = 1, minus1 = 0, PI = 34, DB = 0
N4.C2.D1.R1.S04: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N6.C1.D0.R1.S09: RcvEn: plus1 = 1, minus1 = 0, PI = 35, DB = 0
N0.C1.D0.R0.S16: RcvEn: plus1 = 1, minus1 = 0, PI = 23, DB = 0
N2.C2.D1.R0.S10: RcvEn: plus1 = 1, minus1 = 0, PI = 11, DB = 1
N4.C2.D1.R1.S05: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N6.C1.D0.R1.S10: RcvEn: plus1 = 0, minus1 = 1, PI = 16, DB = 0
N0.C1.D0.R0.S17: RcvEn: plus1 = 0, minus1 = 1, PI = 05, DB = 1
N2.C2.D1.R0.S11: RcvEn: plus1 = 1, minus1 = 0, PI = 43, DB = 0
N4.C2.D1.R1.S06: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N6.C1.D0.R1.S11: RcvEn: plus1 = 1, minus1 = 0, PI = 48, DB = 0
N0.C1.D0.R1.S00: RcvEn: plus1 = 1, minus1 = 0, PI = 32, DB = 0
N2.C2.D1.R0.S12: RcvEn: plus1 = 1, minus1 = 0, PI = 26, DB = 0
N4.C2.D1.R1.S07: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N6.C1.D0.R1.S12: RcvEn: plus1 = 1, minus1 = 0, PI = 30, DB = 0
N0.C1.D0.R1.S01: RcvEn: plus1 = 0, minus1 = 1, PI = 08, DB = 1
N2.C2.D1.R0.S13: RcvEn: plus1 = 1, minus1 = 0, PI = 26, DB = 0
N4.C2.D1.R1.S08: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N6.C1.D0.R1.S13: RcvEn: plus1 = 1, minus1 = 0, PI = 24, DB = 0
N0.C1.D0.R1.S02: RcvEn: plus1 = 1, minus1 = 0, PI = 41, DB = 0
N2.C2.D1.R0.S14: RcvEn: plus1 = 1, minus1 = 0, PI = 37, DB = 0
N4.C2.D1.R1.S00: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N6.C1.D0.R1.S14: RcvEn: plus1 = 1, minus1 = 0, PI = 46, DB = 0
N0.C1.D0.R1.S03: RcvEn: plus1 = 1, minus1 = 0, PI = 24, DB = 0
N2.C2.D1.R0.S15: RcvEn: plus1 = 1, minus1 = 0, PI = 09, DB = 1
N4.C2.D1.R1.S01: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N6.C1.D0.R1.S15: RcvEn: plus1 = 0, minus1 = 1, PI = 07, DB = 1
N0.C1.D0.R1.S04: RcvEn: plus1 = 0, minus1 = 1, PI = 14, DB = 1
N2.C2.D1.R0.S16: RcvEn: plus1 = 1, minus1 = 0, PI = 30, DB = 0
N4.C2.D1.R1.S02: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N6.C1.D0.R1.S16: RcvEn: plus1 = 1, minus1 = 0, PI = 28, DB = 0
N0.C1.D0.R1.S05: RcvEn: plus1 = 1, minus1 = 0, PI = 41, DB = 0
N2.C2.D1.R0.S17: RcvEn: plus1 = 1, minus1 = 0, PI = 11, DB = 1
N4.C2.D1.R1.S03: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N6.C1.D0.R1.S17: RcvEn: plus1 = 0, minus1 = 1, PI = 10, DB = 1
N0.C1.D0.R1.S06: RcvEn: plus1 = 0, minus1 = 1, PI = 00, DB = 1
N2.C2.D1.R1.S00: RcvEn: plus1 = 1, minus1 = 0, PI = 33, DB = 0
N4.C2.D1.R1.S04: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N6.C1.D1.R0.S00: RcvEn: plus1 = 1, minus1 = 0, PI = 23, DB = 0
N0.C1.D0.R1.S07: RcvEn: plus1 = 1, minus1 = 0, PI = 24, DB = 0
N2.C2.D1.R1.S01: RcvEn: plus1 = 1, minus1 = 0, PI = 11, DB = 1
N4.C2.D1.R1.S05: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N6.C1.D1.R0.S01: RcvEn: plus1 = 1, minus1 = 0, PI = 63, DB = 1
N0.C1.D0.R1.S08: RcvEn: plus1 = 0, minus1 = 1, PI = 03, DB = 1
N2.C2.D1.R1.S02: RcvEn: plus1 = 1, minus1 = 0, PI = 43, DB = 0
N4.C2.D1.R1.S06: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N6.C1.D1.R0.S02: RcvEn: plus1 = 1, minus1 = 0, PI = 32, DB = 0
N0.C1.D0.R1.S09: RcvEn: plus1 = 1, minus1 = 0, PI = 31, DB = 0
N2.C2.D1.R1.S03: RcvEn: plus1 = 1, minus1 = 0, PI = 28, DB = 0
N4.C2.D1.R1.S07: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N6.C1.D1.R0.S03: RcvEn: plus1 = 1, minus1 = 0, PI = 10, DB = 1
N0.C1.D0.R1.S10: RcvEn: plus1 = 0, minus1 = 1, PI = 09, DB = 1
N2.C2.D1.R1.S04: RcvEn: plus1 = 1, minus1 = 0, PI = 27, DB = 0
N4.C2.D1.R1.S08: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N6.C1.D1.R0.S04: RcvEn: plus1 = 1, minus1 = 0, PI = 07, DB = 1
N0.C1.D0.R1.S11: RcvEn: plus1 = 1, minus1 = 0, PI = 43, DB = 0
N2.C2.D1.R1.S05: RcvEn: plus1 = 1, minus1 = 0, PI = 40, DB = 0
N4.C2.D1.R1.S00: Preamble found at Latency = 007
N6.C1.D1.R0.S05: RcvEn: plus1 = 1, minus1 = 0, PI = 30, DB = 0
N0.C1.D0.R1.S12: RcvEn: plus1 = 1, minus1 = 0, PI = 24, DB = 0
N2.C2.D1.R1.S06: RcvEn: plus1 = 1, minus1 = 0, PI = 11, DB = 1
N4.C2.D1.R1.S01: Preamble found at Latency = 007
N6.C1.D1.R0.S06: RcvEn: plus1 = 1, minus1 = 0, PI = 56, DB = 1
N0.C1.D0.R1.S13: RcvEn: plus1 = 0, minus1 = 1, PI = 15, DB = 1
N2.C2.D1.R1.S07: RcvEn: plus1 = 1, minus1 = 0, PI = 29, DB = 0
N4.C2.D1.R1.S02: Preamble found at Latency = 007
N6.C1.D1.R0.S07: RcvEn: plus1 = 1, minus1 = 0, PI = 10, DB = 1
N0.C1.D0.R1.S14: RcvEn: plus1 = 1, minus1 = 0, PI = 41, DB = 0
N2.C2.D1.R1.S08: RcvEn: plus1 = 1, minus1 = 0, PI = 14, DB = 1
N4.C2.D1.R1.S03: Preamble found at Latency = 007
N6.C1.D1.R0.S08: RcvEn: plus1 = 1, minus1 = 0, PI = 59, DB = 1
N0.C1.D0.R1.S15: RcvEn: plus1 = 0, minus1 = 1, PI = 00, DB = 1
N2.C2.D1.R1.S09: RcvEn: plus1 = 1, minus1 = 0, PI = 34, DB = 0
N4.C2.D1.R1.S04: Preamble found at Latency = 007
N6.C1.D1.R0.S09: RcvEn: plus1 = 1, minus1 = 0, PI = 20, DB = 0
N0.C1.D0.R1.S16: RcvEn: plus1 = 1, minus1 = 0, PI = 23, DB = 0
N2.C2.D1.R1.S10: RcvEn: plus1 = 1, minus1 = 0, PI = 11, DB = 1
N4.C2.D1.R1.S05: Preamble found at Latency = 007
N6.C1.D1.R0.S10: RcvEn: plus1 = 0, minus1 = 1, PI = 01, DB = 1
N0.C1.D0.R1.S17: RcvEn: plus1 = 0, minus1 = 1, PI = 05, DB = 1
N2.C2.D1.R1.S11: RcvEn: plus1 = 1, minus1 = 0, PI = 43, DB = 0
N4.C2.D1.R1.S06: Preamble found at Latency = 007
N6.C1.D1.R0.S11: RcvEn: plus1 = 1, minus1 = 0, PI = 32, DB = 0
N0.C1.D1.R0.S00: RcvEn: plus1 = 1, minus1 = 0, PI = 14, DB = 1
N2.C2.D1.R1.S12: RcvEn: plus1 = 1, minus1 = 0, PI = 26, DB = 0
N4.C2.D1.R1.S07: Preamble found at Latency = 007
N6.C1.D1.R0.S12: RcvEn: plus1 = 1, minus1 = 0, PI = 15, DB = 1
N0.C1.D1.R0.S01: RcvEn: plus1 = 1, minus1 = 0, PI = 56, DB = 1
N2.C2.D1.R1.S13: RcvEn: plus1 = 1, minus1 = 0, PI = 26, DB = 0
N4.C2.D1.R1.S08: Preamble found at Latency = 007
N6.C1.D1.R0.S13: RcvEn: plus1 = 1, minus1 = 0, PI = 06, DB = 1
N0.C1.D1.R0.S02: RcvEn: plus1 = 1, minus1 = 0, PI = 25, DB = 0
N2.C2.D1.R1.S14: RcvEn: plus1 = 1, minus1 = 0, PI = 37, DB = 0
N4.C2.D1.R1.S00: Total Receive Enable Delay = 1311
N6.C1.D1.R0.S14: RcvEn: plus1 = 1, minus1 = 0, PI = 31, DB = 0
N0.C1.D1.R0.S03: RcvEn: plus1 = 1, minus1 = 0, PI = 08, DB = 1
N2.C2.D1.R1.S15: RcvEn: plus1 = 1, minus1 = 0, PI = 09, DB = 1
N4.C2.D1.R1.S01: Total Receive Enable Delay = 1287
N6.C1.D1.R0.S15: RcvEn: plus1 = 1, minus1 = 0, PI = 56, DB = 1
N0.C1.D1.R0.S04: RcvEn: plus1 = 1, minus1 = 0, PI = 63, DB = 1
N2.C2.D1.R1.S16: RcvEn: plus1 = 1, minus1 = 0, PI = 30, DB = 0
N4.C2.D1.R1.S02: Total Receive Enable Delay = 1258
N6.C1.D1.R0.S16: RcvEn: plus1 = 1, minus1 = 0, PI = 13, DB = 1
N0.C1.D1.R0.S05: RcvEn: plus1 = 1, minus1 = 0, PI = 24, DB = 0
N2.C2.D1.R1.S17: RcvEn: plus1 = 1, minus1 = 0, PI = 11, DB = 1
N4.C2.D1.R1.S03: Total Receive Enable Delay = 1231
N6.C1.D1.R0.S17: RcvEn: plus1 = 1, minus1 = 0, PI = 57, DB = 1
N0.C1.D1.R0.S06: RcvEn: plus1 = 1, minus1 = 0, PI = 48, DB = 0
STOP_DATA_REC_EN
N4.C2.D1.R1.S04: Total Receive Enable Delay = 1239
N6.C1.D1.R1.S00: RcvEn: plus1 = 1, minus1 = 0, PI = 23, DB = 0
N0.C1.D1.R0.S07: RcvEn: plus1 = 1, minus1 = 0, PI = 05, DB = 1
N2.C3.D0.R0: RcvEnFine: Initial RdCmd2RcvEnLatency = 10, Initial RdPtrOffsetRcvEn = 4
N4.C2.D1.R1.S05: Total Receive Enable Delay = 1248
N6.C1.D1.R1.S01: RcvEn: plus1 = 1, minus1 = 0, PI = 63, DB = 1
N0.C1.D1.R0.S08: RcvEn: plus1 = 1, minus1 = 0, PI = 51, DB = 1
N2.C3.D0.R0.S00: Rcv En Fine Value = 316
N4.C2.D1.R1.S06: Total Receive Enable Delay = 1287
N6.C1.D1.R1.S02: RcvEn: plus1 = 1, minus1 = 0, PI = 32, DB = 0
N0.C1.D1.R0.S09: RcvEn: plus1 = 1, minus1 = 0, PI = 13, DB = 1
N2.C3.D0.R0.S01: Rcv En Fine Value = 296
N4.C2.D1.R1.S07: Total Receive Enable Delay = 1302
N6.C1.D1.R1.S03: RcvEn: plus1 = 1, minus1 = 0, PI = 10, DB = 1
N0.C1.D1.R0.S10: RcvEn: plus1 = 1, minus1 = 0, PI = 55, DB = 1
N2.C3.D0.R0.S02: Rcv En Fine Value = 266
N4.C2.D1.R1.S08: Total Receive Enable Delay = 1224
N6.C1.D1.R1.S04: RcvEn: plus1 = 1, minus1 = 0, PI = 07, DB = 1
N0.C1.D1.R0.S11: RcvEn: plus1 = 1, minus1 = 0, PI = 26, DB = 0
N2.C3.D0.R0.S03: Rcv En Fine Value = 373
N4.C2.D1.R1: Starting preamble search upper nibbles
N6.C1.D1.R1.S05: RcvEn: plus1 = 1, minus1 = 0, PI = 30, DB = 0
N0.C1.D1.R0.S12: RcvEn: plus1 = 1, minus1 = 0, PI = 06, DB = 1
N2.C3.D0.R0.S04: Rcv En Fine Value = 371
N4.C2.D1.R1.S09: PI = 060, PtrOffset = 005
N6.C1.D1.R1.S06: RcvEn: plus1 = 1, minus1 = 0, PI = 56, DB = 1
N0.C1.D1.R0.S13: RcvEn: plus1 = 0, minus1 = 1, PI = 00, DB = 1
N2.C3.D0.R0.S05: Rcv En Fine Value = 266
N4.C2.D1.R1.S10: PI = 037, PtrOffset = 005
N6.C1.D1.R1.S07: RcvEn: plus1 = 1, minus1 = 0, PI = 10, DB = 1
N0.C1.D1.R0.S14: RcvEn: plus1 = 1, minus1 = 0, PI = 26, DB = 0
N2.C3.D0.R0.S06: Rcv En Fine Value = 289
N4.C2.D1.R1.S11: PI = 007, PtrOffset = 005
N6.C1.D1.R1.S08: RcvEn: plus1 = 1, minus1 = 0, PI = 59, DB = 1
N0.C1.D1.R0.S15: RcvEn: plus1 = 1, minus1 = 0, PI = 48, DB = 0
N2.C3.D0.R0.S07: Rcv En Fine Value = 312
N4.C2.D1.R1.S12: PI = 049, PtrOffset = 004
N6.C1.D1.R1.S09: RcvEn: plus1 = 1, minus1 = 0, PI = 20, DB = 0
N0.C1.D1.R0.S16: RcvEn: plus1 = 1, minus1 = 0, PI = 06, DB = 1
N2.C3.D0.R0.S08: Rcv En Fine Value = 354
N4.C2.D1.R1.S13: PI = 053, PtrOffset = 004
N6.C1.D1.R1.S10: RcvEn: plus1 = 0, minus1 = 1, PI = 01, DB = 1
N0.C1.D1.R0.S17: RcvEn: plus1 = 1, minus1 = 0, PI = 53, DB = 1
N2.C3.D0.R0.S09: Rcv En Fine Value = 318
N4.C2.D1.R1.S14: PI = 003, PtrOffset = 005
N6.C1.D1.R1.S11: RcvEn: plus1 = 1, minus1 = 0, PI = 32, DB = 0
N0.C1.D1.R1.S00: RcvEn: plus1 = 1, minus1 = 0, PI = 14, DB = 1
N2.C3.D0.R0.S10: Rcv En Fine Value = 296
N4.C2.D1.R1.S15: PI = 037, PtrOffset = 005
N6.C1.D1.R1.S12: RcvEn: plus1 = 1, minus1 = 0, PI = 15, DB = 1
N0.C1.D1.R1.S01: RcvEn: plus1 = 1, minus1 = 0, PI = 56, DB = 1
N2.C3.D0.R0.S11: Rcv En Fine Value = 266
N4.C2.D1.R1.S16: PI = 051, PtrOffset = 005
N6.C1.D1.R1.S13: RcvEn: plus1 = 1, minus1 = 0, PI = 06, DB = 1
N0.C1.D1.R1.S02: RcvEn: plus1 = 1, minus1 = 0, PI = 25, DB = 0
N2.C3.D0.R0.S12: Rcv En Fine Value = 376
N4.C2.D1.R1.S17: PI = 037, PtrOffset = 004
N6.C1.D1.R1.S14: RcvEn: plus1 = 1, minus1 = 0, PI = 31, DB = 0
N0.C1.D1.R1.S03: RcvEn: plus1 = 1, minus1 = 0, PI = 08, DB = 1
N2.C3.D0.R0.S13: Rcv En Fine Value = 372
N4.C2.D1.R1.S09: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N6.C1.D1.R1.S15: RcvEn: plus1 = 1, minus1 = 0, PI = 56, DB = 1
N0.C1.D1.R1.S04: RcvEn: plus1 = 1, minus1 = 0, PI = 63, DB = 1
N2.C3.D0.R0.S14: Rcv En Fine Value = 267
N4.C2.D1.R1.S10: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N6.C1.D1.R1.S16: RcvEn: plus1 = 1, minus1 = 0, PI = 13, DB = 1
N0.C1.D1.R1.S05: RcvEn: plus1 = 1, minus1 = 0, PI = 24, DB = 0
N2.C3.D0.R0.S15: Rcv En Fine Value = 290
N4.C2.D1.R1.S11: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N6.C1.D1.R1.S17: RcvEn: plus1 = 1, minus1 = 0, PI = 57, DB = 1
N0.C1.D1.R1.S06: RcvEn: plus1 = 1, minus1 = 0, PI = 48, DB = 0
N2.C3.D0.R0.S16: Rcv En Fine Value = 313
N4.C2.D1.R1.S12: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
STOP_DATA_REC_EN
N0.C1.D1.R1.S07: RcvEn: plus1 = 1, minus1 = 0, PI = 05, DB = 1
N2.C3.D0.R0.S17: Rcv En Fine Value = 357
N4.C2.D1.R1.S13: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N6.C2.D0.R0: RcvEnFine: Initial RdCmd2RcvEnLatency = 10, Initial RdPtrOffsetRcvEn = 4
N0.C1.D1.R1.S08: RcvEn: plus1 = 1, minus1 = 0, PI = 51, DB = 1
N2.C3.D0.R0: Starting preamble search lower nibbles
N4.C2.D1.R1.S14: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N6.C2.D0.R0.S00: Rcv En Fine Value = 277
N0.C1.D1.R1.S09: RcvEn: plus1 = 1, minus1 = 0, PI = 13, DB = 1
N2.C3.D0.R0.S00: PI = 060, PtrOffset = 004
N4.C2.D1.R1.S15: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N6.C2.D0.R0.S01: Rcv En Fine Value = 256
N0.C1.D1.R1.S10: RcvEn: plus1 = 1, minus1 = 0, PI = 55, DB = 1
N2.C3.D0.R0.S01: PI = 040, PtrOffset = 004
N4.C2.D1.R1.S16: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N6.C2.D0.R0.S02: Rcv En Fine Value = 353
N0.C1.D1.R1.S11: RcvEn: plus1 = 1, minus1 = 0, PI = 26, DB = 0
N2.C3.D0.R0.S02: PI = 010, PtrOffset = 004
N4.C2.D1.R1.S17: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N6.C2.D0.R0.S03: Rcv En Fine Value = 333
N0.C1.D1.R1.S12: RcvEn: plus1 = 1, minus1 = 0, PI = 06, DB = 1
N2.C3.D0.R0.S03: PI = 053, PtrOffset = 005
N4.C2.D1.R1.S09: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N6.C2.D0.R0.S04: Rcv En Fine Value = 332
N0.C1.D1.R1.S13: RcvEn: plus1 = 0, minus1 = 1, PI = 00, DB = 1
N2.C3.D0.R0.S04: PI = 051, PtrOffset = 005
N4.C2.D1.R1.S10: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N6.C2.D0.R0.S05: Rcv En Fine Value = 346
N0.C1.D1.R1.S14: RcvEn: plus1 = 1, minus1 = 0, PI = 26, DB = 0
N2.C3.D0.R0.S05: PI = 010, PtrOffset = 004
N4.C2.D1.R1.S11: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N6.C2.D0.R0.S06: Rcv En Fine Value = 382
N0.C1.D1.R1.S15: RcvEn: plus1 = 1, minus1 = 0, PI = 48, DB = 0
N2.C3.D0.R0.S06: PI = 033, PtrOffset = 004
N4.C2.D1.R1.S12: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N6.C2.D0.R0.S07: Rcv En Fine Value = 272
N0.C1.D1.R1.S16: RcvEn: plus1 = 1, minus1 = 0, PI = 06, DB = 1
N2.C3.D0.R0.S07: PI = 056, PtrOffset = 004
N4.C2.D1.R1.S13: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N6.C2.D0.R0.S08: Rcv En Fine Value = 319
N0.C1.D1.R1.S17: RcvEn: plus1 = 1, minus1 = 0, PI = 53, DB = 1
N2.C3.D0.R0.S08: PI = 034, PtrOffset = 005
N4.C2.D1.R1.S14: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N6.C2.D0.R0.S09: Rcv En Fine Value = 275
STOP_DATA_REC_EN
N2.C3.D0.R0.S00: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N4.C2.D1.R1.S15: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N6.C2.D0.R0.S10: Rcv En Fine Value = 383
N0.C2.D0.R0: RcvEnFine: Initial RdCmd2RcvEnLatency = 10, Initial RdPtrOffsetRcvEn = 4
N2.C3.D0.R0.S01: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N4.C2.D1.R1.S16: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N6.C2.D0.R0.S11: Rcv En Fine Value = 350
N0.C2.D0.R0.S00: Rcv En Fine Value = 276
N2.C3.D0.R0.S02: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N4.C2.D1.R1.S17: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N6.C2.D0.R0.S12: Rcv En Fine Value = 333
N0.C2.D0.R0.S01: Rcv En Fine Value = 383
N2.C3.D0.R0.S03: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N4.C2.D1.R1.S09: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N6.C2.D0.R0.S13: Rcv En Fine Value = 331
N0.C2.D0.R0.S02: Rcv En Fine Value = 349
N2.C3.D0.R0.S04: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N4.C2.D1.R1.S10: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N6.C2.D0.R0.S14: Rcv En Fine Value = 344
N0.C2.D0.R0.S03: Rcv En Fine Value = 327
N2.C3.D0.R0.S05: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N4.C2.D1.R1.S11: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N6.C2.D0.R0.S15: Rcv En Fine Value = 383
N0.C2.D0.R0.S04: Rcv En Fine Value = 329
N2.C3.D0.R0.S06: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N4.C2.D1.R1.S12: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N6.C2.D0.R0.S16: Rcv En Fine Value = 270
N0.C2.D0.R0.S05: Rcv En Fine Value = 341
N2.C3.D0.R0.S07: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N4.C2.D1.R1.S13: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N6.C2.D0.R0.S17: Rcv En Fine Value = 321
N0.C2.D0.R0.S06: Rcv En Fine Value = 380
N2.C3.D0.R0.S08: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N4.C2.D1.R1.S14: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N6.C2.D0.R0: Starting preamble search lower nibbles
N0.C2.D0.R0.S07: Rcv En Fine Value = 269
N2.C3.D0.R0.S00: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N4.C2.D1.R1.S15: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N6.C2.D0.R0.S00: PI = 021, PtrOffset = 004
N0.C2.D0.R0.S08: Rcv En Fine Value = 318
N2.C3.D0.R0.S01: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N4.C2.D1.R1.S16: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N6.C2.D0.R0.S01: PI = 000, PtrOffset = 004
N0.C2.D0.R0.S09: Rcv En Fine Value = 274
N2.C3.D0.R0.S02: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N4.C2.D1.R1.S17: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N6.C2.D0.R0.S02: PI = 033, PtrOffset = 005
N0.C2.D0.R0.S10: Rcv En Fine Value = 378
N2.C3.D0.R0.S03: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N4.C2.D1.R1.S09: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N6.C2.D0.R0.S03: PI = 013, PtrOffset = 005
N0.C2.D0.R0.S11: Rcv En Fine Value = 348
N2.C3.D0.R0.S04: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N4.C2.D1.R1.S10: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N6.C2.D0.R0.S04: PI = 012, PtrOffset = 005
N0.C2.D0.R0.S12: Rcv En Fine Value = 327
N2.C3.D0.R0.S05: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N4.C2.D1.R1.S11: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N6.C2.D0.R0.S05: PI = 026, PtrOffset = 005
N0.C2.D0.R0.S13: Rcv En Fine Value = 331
N2.C3.D0.R0.S06: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N4.C2.D1.R1.S12: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N6.C2.D0.R0.S06: PI = 062, PtrOffset = 005
N0.C2.D0.R0.S14: Rcv En Fine Value = 342
N2.C3.D0.R0.S07: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N4.C2.D1.R1.S13: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N6.C2.D0.R0.S07: PI = 016, PtrOffset = 004
N0.C2.D0.R0.S15: Rcv En Fine Value = 379
N2.C3.D0.R0.S08: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N4.C2.D1.R1.S14: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N6.C2.D0.R0.S08: PI = 063, PtrOffset = 004
N0.C2.D0.R0.S16: Rcv En Fine Value = 267
N2.C3.D0.R0.S00: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N4.C2.D1.R1.S15: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N6.C2.D0.R0.S00: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N0.C2.D0.R0.S17: Rcv En Fine Value = 312
N2.C3.D0.R0.S01: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N4.C2.D1.R1.S16: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N6.C2.D0.R0.S01: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N0.C2.D0.R0: Starting preamble search lower nibbles
N2.C3.D0.R0.S02: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N4.C2.D1.R1.S17: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N6.C2.D0.R0.S02: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N0.C2.D0.R0.S00: PI = 020, PtrOffset = 004
N2.C3.D0.R0.S03: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N4.C2.D1.R1.S09: Preamble found at Latency = 007
N6.C2.D0.R0.S03: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N0.C2.D0.R0.S01: PI = 063, PtrOffset = 005
N2.C3.D0.R0.S04: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N4.C2.D1.R1.S10: Preamble found at Latency = 007
N6.C2.D0.R0.S04: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N0.C2.D0.R0.S02: PI = 029, PtrOffset = 005
N2.C3.D0.R0.S05: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N4.C2.D1.R1.S11: Preamble found at Latency = 007
N6.C2.D0.R0.S05: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N0.C2.D0.R0.S03: PI = 007, PtrOffset = 005
N2.C3.D0.R0.S06: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N4.C2.D1.R1.S12: Preamble found at Latency = 007
N6.C2.D0.R0.S06: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N0.C2.D0.R0.S04: PI = 009, PtrOffset = 005
N2.C3.D0.R0.S07: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N4.C2.D1.R1.S13: Preamble found at Latency = 007
N6.C2.D0.R0.S07: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N0.C2.D0.R0.S05: PI = 021, PtrOffset = 005
N2.C3.D0.R0.S08: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N4.C2.D1.R1.S14: Preamble found at Latency = 007
N6.C2.D0.R0.S08: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N0.C2.D0.R0.S06: PI = 060, PtrOffset = 005
N2.C3.D0.R0.S00: Preamble found at Latency = 008
N4.C2.D1.R1.S15: Preamble found at Latency = 007
N6.C2.D0.R0.S00: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N0.C2.D0.R0.S07: PI = 013, PtrOffset = 004
N2.C3.D0.R0.S01: Preamble found at Latency = 008
N4.C2.D1.R1.S16: Preamble found at Latency = 007
N6.C2.D0.R0.S01: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N0.C2.D0.R0.S08: PI = 062, PtrOffset = 004
N2.C3.D0.R0.S02: Preamble found at Latency = 008
N4.C2.D1.R1.S17: Preamble found at Latency = 007
N6.C2.D0.R0.S02: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N0.C2.D0.R0.S00: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N2.C3.D0.R0.S05: Preamble found at Latency = 008
N4.C2.D1.R1: Preamble found for all upper nibbles, adjusting Pi, Offset to center into preamble
N6.C2.D0.R0.S03: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N0.C2.D0.R0.S01: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N2.C3.D0.R0.S06: Preamble found at Latency = 008
N4.C2.D1.R1.S09: Total Receive Enable Delay = 1308
N6.C2.D0.R0.S04: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N0.C2.D0.R0.S02: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N2.C3.D0.R0.S07: Preamble found at Latency = 008
N4.C2.D1.R1.S10: Total Receive Enable Delay = 1285
N6.C2.D0.R0.S05: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N0.C2.D0.R0.S03: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N2.C3.D0.R0.S00: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N4.C2.D1.R1.S11: Total Receive Enable Delay = 1255
N6.C2.D0.R0.S06: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N0.C2.D0.R0.S04: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N2.C3.D0.R0.S01: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N4.C2.D1.R1.S12: Total Receive Enable Delay = 1233
N6.C2.D0.R0.S07: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N0.C2.D0.R0.S05: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N2.C3.D0.R0.S02: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N4.C2.D1.R1.S13: Total Receive Enable Delay = 1237
N6.C2.D0.R0.S08: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N0.C2.D0.R0.S06: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N2.C3.D0.R0.S03: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N4.C2.D1.R1.S14: Total Receive Enable Delay = 1251
N6.C2.D0.R0.S00: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N0.C2.D0.R0.S07: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N2.C3.D0.R0.S04: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N4.C2.D1.R1.S15: Total Receive Enable Delay = 1285
N6.C2.D0.R0.S01: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N0.C2.D0.R0.S08: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N2.C3.D0.R0.S05: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N4.C2.D1.R1.S16: Total Receive Enable Delay = 1299
N6.C2.D0.R0.S02: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N0.C2.D0.R0.S00: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N2.C3.D0.R0.S06: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N4.C2.D1.R1.S17: Total Receive Enable Delay = 1221
N6.C2.D0.R0.S03: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N0.C2.D0.R0.S01: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N2.C3.D0.R0.S07: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
START_DATA_REC_EN
N6.C2.D0.R0.S04: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N0.C2.D0.R0.S02: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N2.C3.D0.R0.S08: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N4.C2.S00: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N6.C2.D0.R0.S05: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N0.C2.D0.R0.S03: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N2.C3.D0.R0.S03: Preamble found at Latency = 007
N4.C2.S01: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N6.C2.D0.R0.S06: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N0.C2.D0.R0.S04: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N2.C3.D0.R0.S04: Preamble found at Latency = 007
N4.C2.S02: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 5
N6.C2.D0.R0.S07: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N0.C2.D0.R0.S05: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N2.C3.D0.R0.S08: Preamble found at Latency = 007
N4.C2.S03: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 5
N6.C2.D0.R0.S08: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N0.C2.D0.R0.S06: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N2.C3.D0.R0.S00: Total Receive Enable Delay = 1372
N4.C2.S04: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 5
N6.C2.D0.R0.S00: Preamble found at Latency = 008
N0.C2.D0.R0.S07: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N2.C3.D0.R0.S01: Total Receive Enable Delay = 1352
N4.C2.S05: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 5
N6.C2.D0.R0.S01: Preamble found at Latency = 008
N0.C2.D0.R0.S08: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N2.C3.D0.R0.S02: Total Receive Enable Delay = 1322
N4.C2.S06: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N6.C2.D0.R0.S07: Preamble found at Latency = 008
N0.C2.D0.R0.S00: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N2.C3.D0.R0.S03: Total Receive Enable Delay = 1301
N4.C2.S07: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N6.C2.D0.R0.S00: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N0.C2.D0.R0.S01: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N2.C3.D0.R0.S04: Total Receive Enable Delay = 1299
N4.C2.S08: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 5
N6.C2.D0.R0.S01: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N0.C2.D0.R0.S02: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N2.C3.D0.R0.S05: Total Receive Enable Delay = 1322
N4.C2.S09: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N6.C2.D0.R0.S02: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N0.C2.D0.R0.S03: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N2.C3.D0.R0.S06: Total Receive Enable Delay = 1345
N4.C2.S10: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N6.C2.D0.R0.S03: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N0.C2.D0.R0.S04: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N2.C3.D0.R0.S07: Total Receive Enable Delay = 1368
N4.C2.S11: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 5
N6.C2.D0.R0.S04: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N0.C2.D0.R0.S05: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N2.C3.D0.R0.S08: Total Receive Enable Delay = 1282
N4.C2.S12: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 5
N6.C2.D0.R0.S05: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N0.C2.D0.R0.S06: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N2.C3.D0.R0: Starting preamble search upper nibbles
N4.C2.S13: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 5
N6.C2.D0.R0.S06: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N0.C2.D0.R0.S07: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N2.C3.D0.R0.S09: PI = 062, PtrOffset = 004
N4.C2.S14: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 5
N6.C2.D0.R0.S07: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N0.C2.D0.R0.S08: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N2.C3.D0.R0.S10: PI = 040, PtrOffset = 004
N4.C2.S15: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N6.C2.D0.R0.S08: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N0.C2.D0.R0.S00: Preamble found at Latency = 008
N2.C3.D0.R0.S11: PI = 010, PtrOffset = 004
N4.C2.S16: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N6.C2.D0.R0.S02: Preamble found at Latency = 007
N0.C2.D0.R0.S07: Preamble found at Latency = 008
N2.C3.D0.R0.S12: PI = 056, PtrOffset = 005
N4.C2.S17: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 5
N6.C2.D0.R0.S03: Preamble found at Latency = 007
N0.C2.D0.R0.S00: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N2.C3.D0.R0.S13: PI = 052, PtrOffset = 005
N4.C2.D0.R0.S00: RcvEn: plus1 = 1, minus1 = 0, PI = 46, DB = 0
N6.C2.D0.R0.S04: Preamble found at Latency = 007
N0.C2.D0.R0.S01: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N2.C3.D0.R0.S14: PI = 011, PtrOffset = 004
N4.C2.D0.R0.S01: RcvEn: plus1 = 1, minus1 = 0, PI = 23, DB = 0
N6.C2.D0.R0.S05: Preamble found at Latency = 007
N0.C2.D0.R0.S02: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N2.C3.D0.R0.S15: PI = 034, PtrOffset = 004
N4.C2.D0.R0.S02: RcvEn: plus1 = 1, minus1 = 0, PI = 59, DB = 1
N6.C2.D0.R0.S06: Preamble found at Latency = 007
N0.C2.D0.R0.S03: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N2.C3.D0.R0.S16: PI = 057, PtrOffset = 004
N4.C2.D0.R0.S03: RcvEn: plus1 = 1, minus1 = 0, PI = 37, DB = 0
N6.C2.D0.R0.S08: Preamble found at Latency = 007
N0.C2.D0.R0.S04: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N2.C3.D0.R0.S17: PI = 037, PtrOffset = 005
N4.C2.D0.R0.S04: RcvEn: plus1 = 1, minus1 = 0, PI = 37, DB = 0
N6.C2.D0.R0.S00: Total Receive Enable Delay = 1333
N0.C2.D0.R0.S05: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N2.C3.D0.R0.S09: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N4.C2.D0.R0.S05: RcvEn: plus1 = 1, minus1 = 0, PI = 47, DB = 0
N6.C2.D0.R0.S01: Total Receive Enable Delay = 1312
N0.C2.D0.R0.S06: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N2.C3.D0.R0.S10: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N4.C2.D0.R0.S06: RcvEn: plus1 = 1, minus1 = 0, PI = 23, DB = 0
N6.C2.D0.R0.S02: Total Receive Enable Delay = 1281
N0.C2.D0.R0.S07: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N2.C3.D0.R0.S11: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N4.C2.D0.R0.S07: RcvEn: plus1 = 1, minus1 = 0, PI = 38, DB = 0
N6.C2.D0.R0.S03: Total Receive Enable Delay = 1261
N0.C2.D0.R0.S08: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N2.C3.D0.R0.S12: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N4.C2.D0.R0.S08: RcvEn: plus1 = 1, minus1 = 0, PI = 24, DB = 0
N6.C2.D0.R0.S04: Total Receive Enable Delay = 1260
N0.C2.D0.R0.S01: Preamble found at Latency = 007
N2.C3.D0.R0.S13: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N4.C2.D0.R0.S09: RcvEn: plus1 = 1, minus1 = 0, PI = 45, DB = 0
N6.C2.D0.R0.S05: Total Receive Enable Delay = 1274
N0.C2.D0.R0.S02: Preamble found at Latency = 007
N2.C3.D0.R0.S14: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N4.C2.D0.R0.S10: RcvEn: plus1 = 1, minus1 = 0, PI = 24, DB = 0
N6.C2.D0.R0.S06: Total Receive Enable Delay = 1310
N0.C2.D0.R0.S03: Preamble found at Latency = 007
N2.C3.D0.R0.S15: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N4.C2.D0.R0.S11: RcvEn: plus1 = 1, minus1 = 0, PI = 55, DB = 1
N6.C2.D0.R0.S07: Total Receive Enable Delay = 1328
N0.C2.D0.R0.S04: Preamble found at Latency = 007
N2.C3.D0.R0.S16: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N4.C2.D0.R0.S12: RcvEn: plus1 = 1, minus1 = 0, PI = 35, DB = 0
N6.C2.D0.R0.S08: Total Receive Enable Delay = 1247
N0.C2.D0.R0.S05: Preamble found at Latency = 007
N2.C3.D0.R0.S17: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N4.C2.D0.R0.S13: RcvEn: plus1 = 1, minus1 = 0, PI = 36, DB = 0
N6.C2.D0.R0: Starting preamble search upper nibbles
N0.C2.D0.R0.S06: Preamble found at Latency = 007
N2.C3.D0.R0.S09: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N4.C2.D0.R0.S14: RcvEn: plus1 = 1, minus1 = 0, PI = 51, DB = 1
N6.C2.D0.R0.S09: PI = 019, PtrOffset = 004
N0.C2.D0.R0.S08: Preamble found at Latency = 007
N2.C3.D0.R0.S10: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N4.C2.D0.R0.S15: RcvEn: plus1 = 1, minus1 = 0, PI = 23, DB = 0
N6.C2.D0.R0.S10: PI = 063, PtrOffset = 005
N0.C2.D0.R0.S00: Total Receive Enable Delay = 1332
N2.C3.D0.R0.S11: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N4.C2.D0.R0.S16: RcvEn: plus1 = 1, minus1 = 0, PI = 38, DB = 0
N6.C2.D0.R0.S11: PI = 030, PtrOffset = 005
N0.C2.D0.R0.S01: Total Receive Enable Delay = 1311
N2.C3.D0.R0.S12: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N4.C2.D0.R0.S17: RcvEn: plus1 = 1, minus1 = 0, PI = 20, DB = 0
N6.C2.D0.R0.S12: PI = 013, PtrOffset = 005
N0.C2.D0.R0.S02: Total Receive Enable Delay = 1277
N2.C3.D0.R0.S13: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N4.C2.D0.R1.S00: RcvEn: plus1 = 1, minus1 = 0, PI = 46, DB = 0
N6.C2.D0.R0.S13: PI = 011, PtrOffset = 005
N0.C2.D0.R0.S03: Total Receive Enable Delay = 1255
N2.C3.D0.R0.S14: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N4.C2.D0.R1.S01: RcvEn: plus1 = 1, minus1 = 0, PI = 23, DB = 0
N6.C2.D0.R0.S14: PI = 024, PtrOffset = 005
N0.C2.D0.R0.S04: Total Receive Enable Delay = 1257
N2.C3.D0.R0.S15: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N4.C2.D0.R1.S02: RcvEn: plus1 = 1, minus1 = 0, PI = 59, DB = 1
N6.C2.D0.R0.S15: PI = 063, PtrOffset = 005
N0.C2.D0.R0.S05: Total Receive Enable Delay = 1269
N2.C3.D0.R0.S16: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N4.C2.D0.R1.S03: RcvEn: plus1 = 1, minus1 = 0, PI = 37, DB = 0
N6.C2.D0.R0.S16: PI = 014, PtrOffset = 004
N0.C2.D0.R0.S06: Total Receive Enable Delay = 1308
N2.C3.D0.R0.S17: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N4.C2.D0.R1.S04: RcvEn: plus1 = 1, minus1 = 0, PI = 37, DB = 0
N6.C2.D0.R0.S17: PI = 001, PtrOffset = 005
N0.C2.D0.R0.S07: Total Receive Enable Delay = 1325
N2.C3.D0.R0.S09: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N4.C2.D0.R1.S05: RcvEn: plus1 = 1, minus1 = 0, PI = 47, DB = 0
N6.C2.D0.R0.S09: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N0.C2.D0.R0.S08: Total Receive Enable Delay = 1246
N2.C3.D0.R0.S10: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N4.C2.D0.R1.S06: RcvEn: plus1 = 1, minus1 = 0, PI = 23, DB = 0
N6.C2.D0.R0.S10: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N0.C2.D0.R0: Starting preamble search upper nibbles
N2.C3.D0.R0.S11: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N4.C2.D0.R1.S07: RcvEn: plus1 = 1, minus1 = 0, PI = 38, DB = 0
N6.C2.D0.R0.S11: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N0.C2.D0.R0.S09: PI = 018, PtrOffset = 004
N2.C3.D0.R0.S12: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N4.C2.D0.R1.S08: RcvEn: plus1 = 1, minus1 = 0, PI = 24, DB = 0
N6.C2.D0.R0.S12: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N0.C2.D0.R0.S10: PI = 058, PtrOffset = 005
N2.C3.D0.R0.S13: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N4.C2.D0.R1.S09: RcvEn: plus1 = 1, minus1 = 0, PI = 45, DB = 0
N6.C2.D0.R0.S13: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N0.C2.D0.R0.S11: PI = 028, PtrOffset = 005
N2.C3.D0.R0.S14: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N4.C2.D0.R1.S10: RcvEn: plus1 = 1, minus1 = 0, PI = 24, DB = 0
N6.C2.D0.R0.S14: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N0.C2.D0.R0.S12: PI = 007, PtrOffset = 005
N2.C3.D0.R0.S15: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N4.C2.D0.R1.S11: RcvEn: plus1 = 1, minus1 = 0, PI = 55, DB = 1
N6.C2.D0.R0.S15: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N0.C2.D0.R0.S13: PI = 011, PtrOffset = 005
N2.C3.D0.R0.S16: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N4.C2.D0.R1.S12: RcvEn: plus1 = 1, minus1 = 0, PI = 35, DB = 0
N6.C2.D0.R0.S16: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N0.C2.D0.R0.S14: PI = 022, PtrOffset = 005
N2.C3.D0.R0.S17: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N4.C2.D0.R1.S13: RcvEn: plus1 = 1, minus1 = 0, PI = 36, DB = 0
N6.C2.D0.R0.S17: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N0.C2.D0.R0.S15: PI = 059, PtrOffset = 005
N2.C3.D0.R0.S09: Preamble found at Latency = 008
N4.C2.D0.R1.S14: RcvEn: plus1 = 1, minus1 = 0, PI = 51, DB = 1
N6.C2.D0.R0.S09: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N0.C2.D0.R0.S16: PI = 011, PtrOffset = 004
N2.C3.D0.R0.S10: Preamble found at Latency = 008
N4.C2.D0.R1.S15: RcvEn: plus1 = 1, minus1 = 0, PI = 23, DB = 0
N6.C2.D0.R0.S10: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N0.C2.D0.R0.S17: PI = 056, PtrOffset = 004
N2.C3.D0.R0.S11: Preamble found at Latency = 008
N4.C2.D0.R1.S16: RcvEn: plus1 = 1, minus1 = 0, PI = 38, DB = 0
N6.C2.D0.R0.S11: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N0.C2.D0.R0.S09: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N2.C3.D0.R0.S14: Preamble found at Latency = 008
N4.C2.D0.R1.S17: RcvEn: plus1 = 1, minus1 = 0, PI = 20, DB = 0
N6.C2.D0.R0.S12: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N0.C2.D0.R0.S10: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N2.C3.D0.R0.S15: Preamble found at Latency = 008
N4.C2.D1.R0.S00: RcvEn: plus1 = 1, minus1 = 0, PI = 30, DB = 0
N6.C2.D0.R0.S13: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N0.C2.D0.R0.S11: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N2.C3.D0.R0.S16: Preamble found at Latency = 008
N4.C2.D1.R0.S01: RcvEn: plus1 = 1, minus1 = 0, PI = 07, DB = 1
N6.C2.D0.R0.S14: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N0.C2.D0.R0.S12: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N2.C3.D0.R0.S09: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N4.C2.D1.R0.S02: RcvEn: plus1 = 1, minus1 = 0, PI = 42, DB = 0
N6.C2.D0.R0.S15: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N0.C2.D0.R0.S13: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N2.C3.D0.R0.S10: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N4.C2.D1.R0.S03: RcvEn: plus1 = 1, minus1 = 0, PI = 18, DB = 0
N6.C2.D0.R0.S16: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N0.C2.D0.R0.S14: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N2.C3.D0.R0.S11: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N4.C2.D1.R0.S04: RcvEn: plus1 = 1, minus1 = 0, PI = 22, DB = 0
N6.C2.D0.R0.S17: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N0.C2.D0.R0.S15: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N2.C3.D0.R0.S12: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N4.C2.D1.R0.S05: RcvEn: plus1 = 1, minus1 = 0, PI = 33, DB = 0
N6.C2.D0.R0.S09: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N0.C2.D0.R0.S16: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N2.C3.D0.R0.S13: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N4.C2.D1.R0.S06: RcvEn: plus1 = 1, minus1 = 0, PI = 07, DB = 1
N6.C2.D0.R0.S10: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N0.C2.D0.R0.S17: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N2.C3.D0.R0.S14: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N4.C2.D1.R0.S07: RcvEn: plus1 = 1, minus1 = 0, PI = 22, DB = 0
N6.C2.D0.R0.S11: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N0.C2.D0.R0.S09: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N2.C3.D0.R0.S15: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N4.C2.D1.R0.S08: RcvEn: plus1 = 1, minus1 = 0, PI = 09, DB = 1
N6.C2.D0.R0.S12: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N0.C2.D0.R0.S10: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N2.C3.D0.R0.S16: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N4.C2.D1.R0.S09: RcvEn: plus1 = 1, minus1 = 0, PI = 29, DB = 0
N6.C2.D0.R0.S13: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N0.C2.D0.R0.S11: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N2.C3.D0.R0.S17: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N4.C2.D1.R0.S10: RcvEn: plus1 = 1, minus1 = 0, PI = 05, DB = 1
N6.C2.D0.R0.S14: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N0.C2.D0.R0.S12: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N2.C3.D0.R0.S12: Preamble found at Latency = 007
N4.C2.D1.R0.S11: RcvEn: plus1 = 1, minus1 = 0, PI = 39, DB = 0
N6.C2.D0.R0.S15: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N0.C2.D0.R0.S13: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N2.C3.D0.R0.S13: Preamble found at Latency = 007
N4.C2.D1.R0.S12: RcvEn: plus1 = 1, minus1 = 0, PI = 18, DB = 0
N6.C2.D0.R0.S16: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N0.C2.D0.R0.S14: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N2.C3.D0.R0.S17: Preamble found at Latency = 007
N4.C2.D1.R0.S13: RcvEn: plus1 = 1, minus1 = 0, PI = 20, DB = 0
N6.C2.D0.R0.S17: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N0.C2.D0.R0.S15: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N2.C3.D0.R0: Preamble found for all upper nibbles, adjusting Pi, Offset to center into preamble
N4.C2.D1.R0.S14: RcvEn: plus1 = 1, minus1 = 0, PI = 35, DB = 0
N6.C2.D0.R0.S09: Preamble found at Latency = 008
N0.C2.D0.R0.S16: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N2.C3.D0.R0.S09: Total Receive Enable Delay = 1374
N4.C2.D1.R0.S15: RcvEn: plus1 = 1, minus1 = 0, PI = 05, DB = 1
N6.C2.D0.R0.S16: Preamble found at Latency = 008
N0.C2.D0.R0.S17: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N2.C3.D0.R0.S10: Total Receive Enable Delay = 1352
N4.C2.D1.R0.S16: RcvEn: plus1 = 1, minus1 = 0, PI = 20, DB = 0
N6.C2.D0.R0.S09: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N0.C2.D0.R0.S09: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N2.C3.D0.R0.S11: Total Receive Enable Delay = 1322
N4.C2.D1.R0.S17: RcvEn: plus1 = 1, minus1 = 0, PI = 05, DB = 1
N6.C2.D0.R0.S10: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N0.C2.D0.R0.S10: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N2.C3.D0.R0.S12: Total Receive Enable Delay = 1304
N4.C2.D1.R1.S00: RcvEn: plus1 = 1, minus1 = 0, PI = 30, DB = 0
N6.C2.D0.R0.S11: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N0.C2.D0.R0.S11: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N2.C3.D0.R0.S13: Total Receive Enable Delay = 1300
N4.C2.D1.R1.S01: RcvEn: plus1 = 1, minus1 = 0, PI = 07, DB = 1
N6.C2.D0.R0.S12: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N0.C2.D0.R0.S12: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N2.C3.D0.R0.S14: Total Receive Enable Delay = 1323
N4.C2.D1.R1.S02: RcvEn: plus1 = 1, minus1 = 0, PI = 42, DB = 0
N6.C2.D0.R0.S13: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N0.C2.D0.R0.S13: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N2.C3.D0.R0.S15: Total Receive Enable Delay = 1346
N4.C2.D1.R1.S03: RcvEn: plus1 = 1, minus1 = 0, PI = 18, DB = 0
N6.C2.D0.R0.S14: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N0.C2.D0.R0.S14: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N2.C3.D0.R0.S16: Total Receive Enable Delay = 1369
N4.C2.D1.R1.S04: RcvEn: plus1 = 1, minus1 = 0, PI = 22, DB = 0
N6.C2.D0.R0.S15: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N0.C2.D0.R0.S15: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N2.C3.D0.R0.S17: Total Receive Enable Delay = 1285
N4.C2.D1.R1.S05: RcvEn: plus1 = 1, minus1 = 0, PI = 33, DB = 0
N6.C2.D0.R0.S16: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N0.C2.D0.R0.S16: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N2.C3.D0.R1: RcvEnFine: Initial RdCmd2RcvEnLatency = 10, Initial RdPtrOffsetRcvEn = 4
N4.C2.D1.R1.S06: RcvEn: plus1 = 1, minus1 = 0, PI = 07, DB = 1
N6.C2.D0.R0.S17: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N0.C2.D0.R0.S17: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N2.C3.D0.R1.S00: Rcv En Fine Value = 314
N4.C2.D1.R1.S07: RcvEn: plus1 = 1, minus1 = 0, PI = 22, DB = 0
N6.C2.D0.R0.S10: Preamble found at Latency = 007
N0.C2.D0.R0.S09: Preamble found at Latency = 008
N2.C3.D0.R1.S01: Rcv En Fine Value = 295
N4.C2.D1.R1.S08: RcvEn: plus1 = 1, minus1 = 0, PI = 09, DB = 1
N6.C2.D0.R0.S11: Preamble found at Latency = 007
N0.C2.D0.R0.S16: Preamble found at Latency = 008
N2.C3.D0.R1.S02: Rcv En Fine Value = 264
N4.C2.D1.R1.S09: RcvEn: plus1 = 1, minus1 = 0, PI = 29, DB = 0
N6.C2.D0.R0.S12: Preamble found at Latency = 007
N0.C2.D0.R0.S09: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N2.C3.D0.R1.S03: Rcv En Fine Value = 375
N4.C2.D1.R1.S10: RcvEn: plus1 = 1, minus1 = 0, PI = 05, DB = 1
N6.C2.D0.R0.S13: Preamble found at Latency = 007
N0.C2.D0.R0.S10: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N2.C3.D0.R1.S04: Rcv En Fine Value = 368
N4.C2.D1.R1.S11: RcvEn: plus1 = 1, minus1 = 0, PI = 39, DB = 0
N6.C2.D0.R0.S14: Preamble found at Latency = 007
N0.C2.D0.R0.S11: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N2.C3.D0.R1.S05: Rcv En Fine Value = 265
N4.C2.D1.R1.S12: RcvEn: plus1 = 1, minus1 = 0, PI = 18, DB = 0
N6.C2.D0.R0.S15: Preamble found at Latency = 007
N0.C2.D0.R0.S12: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N2.C3.D0.R1.S06: Rcv En Fine Value = 288
N4.C2.D1.R1.S13: RcvEn: plus1 = 1, minus1 = 0, PI = 20, DB = 0
N6.C2.D0.R0.S17: Preamble found at Latency = 007
N0.C2.D0.R0.S13: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N2.C3.D0.R1.S07: Rcv En Fine Value = 311
N4.C2.D1.R1.S14: RcvEn: plus1 = 1, minus1 = 0, PI = 35, DB = 0
N6.C2.D0.R0: Preamble found for all upper nibbles, adjusting Pi, Offset to center into preamble
N0.C2.D0.R0.S14: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N2.C3.D0.R1.S08: Rcv En Fine Value = 355
N4.C2.D1.R1.S15: RcvEn: plus1 = 1, minus1 = 0, PI = 05, DB = 1
N6.C2.D0.R0.S09: Total Receive Enable Delay = 1331
N0.C2.D0.R0.S15: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N2.C3.D0.R1.S09: Rcv En Fine Value = 316
N4.C2.D1.R1.S16: RcvEn: plus1 = 1, minus1 = 0, PI = 20, DB = 0
N6.C2.D0.R0.S10: Total Receive Enable Delay = 1311
N0.C2.D0.R0.S16: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N2.C3.D0.R1.S10: Rcv En Fine Value = 297
N4.C2.D1.R1.S17: RcvEn: plus1 = 1, minus1 = 0, PI = 05, DB = 1
N6.C2.D0.R0.S11: Total Receive Enable Delay = 1278
N0.C2.D0.R0.S17: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N2.C3.D0.R1.S11: Rcv En Fine Value = 265
STOP_DATA_REC_EN
N6.C2.D0.R0.S12: Total Receive Enable Delay = 1261
N0.C2.D0.R0.S10: Preamble found at Latency = 007
N2.C3.D0.R1.S12: Rcv En Fine Value = 376
N4.C3.D0.R0: RcvEnFine: Initial RdCmd2RcvEnLatency = 10, Initial RdPtrOffsetRcvEn = 4
N6.C2.D0.R0.S13: Total Receive Enable Delay = 1259
N0.C2.D0.R0.S11: Preamble found at Latency = 007
N2.C3.D0.R1.S13: Rcv En Fine Value = 370
N4.C3.D0.R0.S00: Rcv En Fine Value = 318
N6.C2.D0.R0.S14: Total Receive Enable Delay = 1272
N0.C2.D0.R0.S12: Preamble found at Latency = 007
N2.C3.D0.R1.S14: Rcv En Fine Value = 265
N4.C3.D0.R0.S01: Rcv En Fine Value = 298
N6.C2.D0.R0.S15: Total Receive Enable Delay = 1311
N0.C2.D0.R0.S13: Preamble found at Latency = 007
N2.C3.D0.R1.S15: Rcv En Fine Value = 291
N4.C3.D0.R0.S02: Rcv En Fine Value = 270
N6.C2.D0.R0.S16: Total Receive Enable Delay = 1326
N0.C2.D0.R0.S14: Preamble found at Latency = 007
N2.C3.D0.R1.S16: Rcv En Fine Value = 314
N4.C3.D0.R0.S03: Rcv En Fine Value = 377
N6.C2.D0.R0.S17: Total Receive Enable Delay = 1249
N0.C2.D0.R0.S15: Preamble found at Latency = 007
N2.C3.D0.R1.S17: Rcv En Fine Value = 355
N4.C3.D0.R0.S04: Rcv En Fine Value = 371
N6.C2.D0.R1: RcvEnFine: Initial RdCmd2RcvEnLatency = 10, Initial RdPtrOffsetRcvEn = 4
N0.C2.D0.R0.S17: Preamble found at Latency = 007
N2.C3.D0.R1: Starting preamble search lower nibbles
N4.C3.D0.R0.S05: Rcv En Fine Value = 266
N6.C2.D0.R1.S00: Rcv En Fine Value = 275
N0.C2.D0.R0: Preamble found for all upper nibbles, adjusting Pi, Offset to center into preamble
N2.C3.D0.R1.S00: PI = 058, PtrOffset = 004
N4.C3.D0.R0.S06: Rcv En Fine Value = 292
N6.C2.D0.R1.S01: Rcv En Fine Value = 379
N0.C2.D0.R0.S09: Total Receive Enable Delay = 1330
N2.C3.D0.R1.S01: PI = 039, PtrOffset = 004
N4.C3.D0.R0.S07: Rcv En Fine Value = 310
N6.C2.D0.R1.S02: Rcv En Fine Value = 351
N0.C2.D0.R0.S10: Total Receive Enable Delay = 1306
N2.C3.D0.R1.S02: PI = 008, PtrOffset = 004
N4.C3.D0.R0.S08: Rcv En Fine Value = 353
N6.C2.D0.R1.S03: Rcv En Fine Value = 331
N0.C2.D0.R0.S11: Total Receive Enable Delay = 1276
N2.C3.D0.R1.S03: PI = 055, PtrOffset = 005
N4.C3.D0.R0.S09: Rcv En Fine Value = 319
N6.C2.D0.R1.S04: Rcv En Fine Value = 331
N0.C2.D0.R0.S12: Total Receive Enable Delay = 1255
N2.C3.D0.R1.S04: PI = 048, PtrOffset = 005
N4.C3.D0.R0.S10: Rcv En Fine Value = 298
N6.C2.D0.R1.S05: Rcv En Fine Value = 344
N0.C2.D0.R0.S13: Total Receive Enable Delay = 1259
N2.C3.D0.R1.S05: PI = 009, PtrOffset = 004
N4.C3.D0.R0.S11: Rcv En Fine Value = 270
N6.C2.D0.R1.S06: Rcv En Fine Value = 257
N0.C2.D0.R0.S14: Total Receive Enable Delay = 1270
N2.C3.D0.R1.S06: PI = 032, PtrOffset = 004
N4.C3.D0.R0.S12: Rcv En Fine Value = 377
N6.C2.D0.R1.S07: Rcv En Fine Value = 272
N0.C2.D0.R0.S15: Total Receive Enable Delay = 1307
N2.C3.D0.R1.S07: PI = 055, PtrOffset = 004
N4.C3.D0.R0.S13: Rcv En Fine Value = 370
N6.C2.D0.R1.S08: Rcv En Fine Value = 315
N0.C2.D0.R0.S16: Total Receive Enable Delay = 1323
N2.C3.D0.R1.S08: PI = 035, PtrOffset = 005
N4.C3.D0.R0.S14: Rcv En Fine Value = 267
N6.C2.D0.R1.S09: Rcv En Fine Value = 274
N0.C2.D0.R0.S17: Total Receive Enable Delay = 1240
N2.C3.D0.R1.S00: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N4.C3.D0.R0.S15: Rcv En Fine Value = 291
N6.C2.D0.R1.S10: Rcv En Fine Value = 256
N0.C2.D0.R1: RcvEnFine: Initial RdCmd2RcvEnLatency = 10, Initial RdPtrOffsetRcvEn = 4
N2.C3.D0.R1.S01: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N4.C3.D0.R0.S16: Rcv En Fine Value = 314
N6.C2.D0.R1.S11: Rcv En Fine Value = 349
N0.C2.D0.R1.S00: Rcv En Fine Value = 274
N2.C3.D0.R1.S02: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N4.C3.D0.R0.S17: Rcv En Fine Value = 354
N6.C2.D0.R1.S12: Rcv En Fine Value = 333
N0.C2.D0.R1.S01: Rcv En Fine Value = 381
N2.C3.D0.R1.S03: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N4.C3.D0.R0: Starting preamble search lower nibbles
N6.C2.D0.R1.S13: Rcv En Fine Value = 334
N0.C2.D0.R1.S02: Rcv En Fine Value = 348
N2.C3.D0.R1.S04: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N4.C3.D0.R0.S00: PI = 062, PtrOffset = 004
N6.C2.D0.R1.S14: Rcv En Fine Value = 342
N0.C2.D0.R1.S03: Rcv En Fine Value = 326
N2.C3.D0.R1.S05: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N4.C3.D0.R0.S01: PI = 042, PtrOffset = 004
N6.C2.D0.R1.S15: Rcv En Fine Value = 256
N0.C2.D0.R1.S04: Rcv En Fine Value = 332
N2.C3.D0.R1.S06: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N4.C3.D0.R0.S02: PI = 014, PtrOffset = 004
N6.C2.D0.R1.S16: Rcv En Fine Value = 271
N0.C2.D0.R1.S05: Rcv En Fine Value = 340
N2.C3.D0.R1.S07: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N4.C3.D0.R0.S03: PI = 057, PtrOffset = 005
N6.C2.D0.R1.S17: Rcv En Fine Value = 321
N0.C2.D0.R1.S06: Rcv En Fine Value = 381
N2.C3.D0.R1.S08: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N4.C3.D0.R0.S04: PI = 051, PtrOffset = 005
N6.C2.D0.R1: Starting preamble search lower nibbles
N0.C2.D0.R1.S07: Rcv En Fine Value = 267
N2.C3.D0.R1.S00: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N4.C3.D0.R0.S05: PI = 010, PtrOffset = 004
N6.C2.D0.R1.S00: PI = 019, PtrOffset = 004
N0.C2.D0.R1.S08: Rcv En Fine Value = 318
N2.C3.D0.R1.S01: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N4.C3.D0.R0.S06: PI = 036, PtrOffset = 004
N6.C2.D0.R1.S01: PI = 059, PtrOffset = 005
N0.C2.D0.R1.S09: Rcv En Fine Value = 274
N2.C3.D0.R1.S02: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N4.C3.D0.R0.S07: PI = 054, PtrOffset = 004
N6.C2.D0.R1.S02: PI = 031, PtrOffset = 005
N0.C2.D0.R1.S10: Rcv En Fine Value = 382
N2.C3.D0.R1.S03: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N4.C3.D0.R0.S08: PI = 033, PtrOffset = 005
N6.C2.D0.R1.S03: PI = 011, PtrOffset = 005
N0.C2.D0.R1.S11: Rcv En Fine Value = 347
N2.C3.D0.R1.S04: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N4.C3.D0.R0.S00: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N6.C2.D0.R1.S04: PI = 011, PtrOffset = 005
N0.C2.D0.R1.S12: Rcv En Fine Value = 327
N2.C3.D0.R1.S05: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N4.C3.D0.R0.S01: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N6.C2.D0.R1.S05: PI = 024, PtrOffset = 005
N0.C2.D0.R1.S13: Rcv En Fine Value = 329
N2.C3.D0.R1.S06: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N4.C3.D0.R0.S02: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N6.C2.D0.R1.S06: PI = 001, PtrOffset = 004
N0.C2.D0.R1.S14: Rcv En Fine Value = 339
N2.C3.D0.R1.S07: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N4.C3.D0.R0.S03: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N6.C2.D0.R1.S07: PI = 016, PtrOffset = 004
N0.C2.D0.R1.S15: Rcv En Fine Value = 380
N2.C3.D0.R1.S08: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N4.C3.D0.R0.S04: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N6.C2.D0.R1.S08: PI = 059, PtrOffset = 004
N0.C2.D0.R1.S16: Rcv En Fine Value = 268
N2.C3.D0.R1.S00: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N4.C3.D0.R0.S05: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N6.C2.D0.R1.S00: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N0.C2.D0.R1.S17: Rcv En Fine Value = 312
N2.C3.D0.R1.S01: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N4.C3.D0.R0.S06: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N6.C2.D0.R1.S01: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N0.C2.D0.R1: Starting preamble search lower nibbles
N2.C3.D0.R1.S02: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N4.C3.D0.R0.S07: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N6.C2.D0.R1.S02: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N0.C2.D0.R1.S00: PI = 018, PtrOffset = 004
N2.C3.D0.R1.S03: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N4.C3.D0.R0.S08: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N6.C2.D0.R1.S03: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N0.C2.D0.R1.S01: PI = 061, PtrOffset = 005
N2.C3.D0.R1.S04: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N4.C3.D0.R0.S00: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N6.C2.D0.R1.S04: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N0.C2.D0.R1.S02: PI = 028, PtrOffset = 005
N2.C3.D0.R1.S05: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N4.C3.D0.R0.S01: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N6.C2.D0.R1.S05: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N0.C2.D0.R1.S03: PI = 006, PtrOffset = 005
N2.C3.D0.R1.S06: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N4.C3.D0.R0.S02: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N6.C2.D0.R1.S06: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N0.C2.D0.R1.S04: PI = 012, PtrOffset = 005
N2.C3.D0.R1.S07: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N4.C3.D0.R0.S03: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N6.C2.D0.R1.S07: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N0.C2.D0.R1.S05: PI = 020, PtrOffset = 005
N2.C3.D0.R1.S08: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N4.C3.D0.R0.S04: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N6.C2.D0.R1.S08: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N0.C2.D0.R1.S06: PI = 061, PtrOffset = 005
N2.C3.D0.R1.S00: Preamble found at Latency = 008
N4.C3.D0.R0.S05: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N6.C2.D0.R1.S00: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N0.C2.D0.R1.S07: PI = 011, PtrOffset = 004
N2.C3.D0.R1.S01: Preamble found at Latency = 008
N4.C3.D0.R0.S06: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N6.C2.D0.R1.S01: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N0.C2.D0.R1.S08: PI = 062, PtrOffset = 004
N2.C3.D0.R1.S02: Preamble found at Latency = 008
N4.C3.D0.R0.S07: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N6.C2.D0.R1.S02: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N0.C2.D0.R1.S00: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N2.C3.D0.R1.S05: Preamble found at Latency = 008
N4.C3.D0.R0.S08: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N6.C2.D0.R1.S03: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N0.C2.D0.R1.S01: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N2.C3.D0.R1.S06: Preamble found at Latency = 008
N4.C3.D0.R0.S00: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N6.C2.D0.R1.S04: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N0.C2.D0.R1.S02: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N2.C3.D0.R1.S07: Preamble found at Latency = 008
N4.C3.D0.R0.S01: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N6.C2.D0.R1.S05: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N0.C2.D0.R1.S03: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N2.C3.D0.R1.S00: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N4.C3.D0.R0.S02: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N6.C2.D0.R1.S06: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N0.C2.D0.R1.S04: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N2.C3.D0.R1.S01: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N4.C3.D0.R0.S03: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N6.C2.D0.R1.S07: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N0.C2.D0.R1.S05: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N2.C3.D0.R1.S02: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N4.C3.D0.R0.S04: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N6.C2.D0.R1.S08: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N0.C2.D0.R1.S06: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N2.C3.D0.R1.S03: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N4.C3.D0.R0.S05: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N6.C2.D0.R1.S00: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N0.C2.D0.R1.S07: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N2.C3.D0.R1.S04: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N4.C3.D0.R0.S06: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N6.C2.D0.R1.S01: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N0.C2.D0.R1.S08: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N2.C3.D0.R1.S05: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N4.C3.D0.R0.S07: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N6.C2.D0.R1.S02: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N0.C2.D0.R1.S00: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N2.C3.D0.R1.S06: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N4.C3.D0.R0.S08: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N6.C2.D0.R1.S03: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N0.C2.D0.R1.S01: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N2.C3.D0.R1.S07: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N4.C3.D0.R0.S00: Preamble found at Latency = 008
N6.C2.D0.R1.S04: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N0.C2.D0.R1.S02: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N2.C3.D0.R1.S08: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N4.C3.D0.R0.S01: Preamble found at Latency = 008
N6.C2.D0.R1.S05: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N0.C2.D0.R1.S03: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N2.C3.D0.R1.S03: Preamble found at Latency = 007
N4.C3.D0.R0.S02: Preamble found at Latency = 008
N6.C2.D0.R1.S06: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N0.C2.D0.R1.S04: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N2.C3.D0.R1.S04: Preamble found at Latency = 007
N4.C3.D0.R0.S05: Preamble found at Latency = 008
N6.C2.D0.R1.S07: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N0.C2.D0.R1.S05: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N2.C3.D0.R1.S08: Preamble found at Latency = 007
N4.C3.D0.R0.S06: Preamble found at Latency = 008
N6.C2.D0.R1.S08: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N0.C2.D0.R1.S06: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N2.C3.D0.R1.S00: Total Receive Enable Delay = 1370
N4.C3.D0.R0.S07: Preamble found at Latency = 008
N6.C2.D0.R1.S00: Preamble found at Latency = 008
N0.C2.D0.R1.S07: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N2.C3.D0.R1.S01: Total Receive Enable Delay = 1351
N4.C3.D0.R0.S00: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N6.C2.D0.R1.S06: Preamble found at Latency = 008
N0.C2.D0.R1.S08: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N2.C3.D0.R1.S02: Total Receive Enable Delay = 1320
N4.C3.D0.R0.S01: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N6.C2.D0.R1.S07: Preamble found at Latency = 008
N0.C2.D0.R1.S00: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N2.C3.D0.R1.S03: Total Receive Enable Delay = 1303
N4.C3.D0.R0.S02: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N6.C2.D0.R1.S00: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N0.C2.D0.R1.S01: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N2.C3.D0.R1.S04: Total Receive Enable Delay = 1296
N4.C3.D0.R0.S03: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N6.C2.D0.R1.S01: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N0.C2.D0.R1.S02: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N2.C3.D0.R1.S05: Total Receive Enable Delay = 1321
N4.C3.D0.R0.S04: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N6.C2.D0.R1.S02: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N0.C2.D0.R1.S03: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N2.C3.D0.R1.S06: Total Receive Enable Delay = 1344
N4.C3.D0.R0.S05: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N6.C2.D0.R1.S03: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N0.C2.D0.R1.S04: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N2.C3.D0.R1.S07: Total Receive Enable Delay = 1367
N4.C3.D0.R0.S06: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N6.C2.D0.R1.S04: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N0.C2.D0.R1.S05: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N2.C3.D0.R1.S08: Total Receive Enable Delay = 1283
N4.C3.D0.R0.S07: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N6.C2.D0.R1.S05: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N0.C2.D0.R1.S06: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N2.C3.D0.R1: Starting preamble search upper nibbles
N4.C3.D0.R0.S08: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N6.C2.D0.R1.S06: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N0.C2.D0.R1.S07: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N2.C3.D0.R1.S09: PI = 060, PtrOffset = 004
N4.C3.D0.R0.S03: Preamble found at Latency = 007
N6.C2.D0.R1.S07: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N0.C2.D0.R1.S08: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N2.C3.D0.R1.S10: PI = 041, PtrOffset = 004
N4.C3.D0.R0.S04: Preamble found at Latency = 007
N6.C2.D0.R1.S08: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N0.C2.D0.R1.S00: Preamble found at Latency = 008
N2.C3.D0.R1.S11: PI = 009, PtrOffset = 004
N4.C3.D0.R0.S08: Preamble found at Latency = 007
N6.C2.D0.R1.S01: Preamble found at Latency = 007
N0.C2.D0.R1.S07: Preamble found at Latency = 008
N2.C3.D0.R1.S12: PI = 056, PtrOffset = 005
N4.C3.D0.R0.S00: Total Receive Enable Delay = 1374
N6.C2.D0.R1.S02: Preamble found at Latency = 007
N0.C2.D0.R1.S00: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N2.C3.D0.R1.S13: PI = 050, PtrOffset = 005
N4.C3.D0.R0.S01: Total Receive Enable Delay = 1354
N6.C2.D0.R1.S03: Preamble found at Latency = 007
N0.C2.D0.R1.S01: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N2.C3.D0.R1.S14: PI = 009, PtrOffset = 004
N4.C3.D0.R0.S02: Total Receive Enable Delay = 1326
N6.C2.D0.R1.S04: Preamble found at Latency = 007
N0.C2.D0.R1.S02: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N2.C3.D0.R1.S15: PI = 035, PtrOffset = 004
N4.C3.D0.R0.S03: Total Receive Enable Delay = 1305
N6.C2.D0.R1.S05: Preamble found at Latency = 007
N0.C2.D0.R1.S03: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N2.C3.D0.R1.S16: PI = 058, PtrOffset = 004
N4.C3.D0.R0.S04: Total Receive Enable Delay = 1299
N6.C2.D0.R1.S08: Preamble found at Latency = 007
N0.C2.D0.R1.S04: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N2.C3.D0.R1.S17: PI = 035, PtrOffset = 005
N4.C3.D0.R0.S05: Total Receive Enable Delay = 1322
N6.C2.D0.R1.S00: Total Receive Enable Delay = 1331
N0.C2.D0.R1.S05: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N2.C3.D0.R1.S09: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N4.C3.D0.R0.S06: Total Receive Enable Delay = 1348
N6.C2.D0.R1.S01: Total Receive Enable Delay = 1307
N0.C2.D0.R1.S06: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N2.C3.D0.R1.S10: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N4.C3.D0.R0.S07: Total Receive Enable Delay = 1366
N6.C2.D0.R1.S02: Total Receive Enable Delay = 1279
N0.C2.D0.R1.S07: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N2.C3.D0.R1.S11: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N4.C3.D0.R0.S08: Total Receive Enable Delay = 1281
N6.C2.D0.R1.S03: Total Receive Enable Delay = 1259
N0.C2.D0.R1.S08: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N2.C3.D0.R1.S12: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N4.C3.D0.R0: Starting preamble search upper nibbles
N6.C2.D0.R1.S04: Total Receive Enable Delay = 1259
N0.C2.D0.R1.S01: Preamble found at Latency = 007
N2.C3.D0.R1.S13: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N4.C3.D0.R0.S09: PI = 063, PtrOffset = 004
N6.C2.D0.R1.S05: Total Receive Enable Delay = 1272
N0.C2.D0.R1.S02: Preamble found at Latency = 007
N2.C3.D0.R1.S14: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N4.C3.D0.R0.S10: PI = 042, PtrOffset = 004
N6.C2.D0.R1.S06: Total Receive Enable Delay = 1313
N0.C2.D0.R1.S03: Preamble found at Latency = 007
N2.C3.D0.R1.S15: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N4.C3.D0.R0.S11: PI = 014, PtrOffset = 004
N6.C2.D0.R1.S07: Total Receive Enable Delay = 1328
N0.C2.D0.R1.S04: Preamble found at Latency = 007
N2.C3.D0.R1.S16: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N4.C3.D0.R0.S12: PI = 057, PtrOffset = 005
N6.C2.D0.R1.S08: Total Receive Enable Delay = 1243
N0.C2.D0.R1.S05: Preamble found at Latency = 007
N2.C3.D0.R1.S17: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N4.C3.D0.R0.S13: PI = 050, PtrOffset = 005
N6.C2.D0.R1: Starting preamble search upper nibbles
N0.C2.D0.R1.S06: Preamble found at Latency = 007
N2.C3.D0.R1.S09: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N4.C3.D0.R0.S14: PI = 011, PtrOffset = 004
N6.C2.D0.R1.S09: PI = 018, PtrOffset = 004
N0.C2.D0.R1.S08: Preamble found at Latency = 007
N2.C3.D0.R1.S10: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N4.C3.D0.R0.S15: PI = 035, PtrOffset = 004
N6.C2.D0.R1.S10: PI = 000, PtrOffset = 004
N0.C2.D0.R1.S00: Total Receive Enable Delay = 1330
N2.C3.D0.R1.S11: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N4.C3.D0.R0.S16: PI = 058, PtrOffset = 004
N6.C2.D0.R1.S11: PI = 029, PtrOffset = 005
N0.C2.D0.R1.S01: Total Receive Enable Delay = 1309
N2.C3.D0.R1.S12: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N4.C3.D0.R0.S17: PI = 034, PtrOffset = 005
N6.C2.D0.R1.S12: PI = 013, PtrOffset = 005
N0.C2.D0.R1.S02: Total Receive Enable Delay = 1276
N2.C3.D0.R1.S13: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N4.C3.D0.R0.S09: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N6.C2.D0.R1.S13: PI = 014, PtrOffset = 005
N0.C2.D0.R1.S03: Total Receive Enable Delay = 1254
N2.C3.D0.R1.S14: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N4.C3.D0.R0.S10: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N6.C2.D0.R1.S14: PI = 022, PtrOffset = 005
N0.C2.D0.R1.S04: Total Receive Enable Delay = 1260
N2.C3.D0.R1.S15: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N4.C3.D0.R0.S11: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N6.C2.D0.R1.S15: PI = 000, PtrOffset = 004
N0.C2.D0.R1.S05: Total Receive Enable Delay = 1268
N2.C3.D0.R1.S16: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N4.C3.D0.R0.S12: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N6.C2.D0.R1.S16: PI = 015, PtrOffset = 004
N0.C2.D0.R1.S06: Total Receive Enable Delay = 1309
N2.C3.D0.R1.S17: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N4.C3.D0.R0.S13: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N6.C2.D0.R1.S17: PI = 001, PtrOffset = 005
N0.C2.D0.R1.S07: Total Receive Enable Delay = 1323
N2.C3.D0.R1.S09: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N4.C3.D0.R0.S14: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N6.C2.D0.R1.S09: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N0.C2.D0.R1.S08: Total Receive Enable Delay = 1246
N2.C3.D0.R1.S10: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N4.C3.D0.R0.S15: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N6.C2.D0.R1.S10: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N0.C2.D0.R1: Starting preamble search upper nibbles
N2.C3.D0.R1.S11: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N4.C3.D0.R0.S16: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N6.C2.D0.R1.S11: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N0.C2.D0.R1.S09: PI = 018, PtrOffset = 004
N2.C3.D0.R1.S12: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N4.C3.D0.R0.S17: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N6.C2.D0.R1.S12: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N0.C2.D0.R1.S10: PI = 062, PtrOffset = 005
N2.C3.D0.R1.S13: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N4.C3.D0.R0.S09: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N6.C2.D0.R1.S13: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N0.C2.D0.R1.S11: PI = 027, PtrOffset = 005
N2.C3.D0.R1.S14: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N4.C3.D0.R0.S10: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N6.C2.D0.R1.S14: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N0.C2.D0.R1.S12: PI = 007, PtrOffset = 005
N2.C3.D0.R1.S15: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N4.C3.D0.R0.S11: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N6.C2.D0.R1.S15: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N0.C2.D0.R1.S13: PI = 009, PtrOffset = 005
N2.C3.D0.R1.S16: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N4.C3.D0.R0.S12: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N6.C2.D0.R1.S16: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N0.C2.D0.R1.S14: PI = 019, PtrOffset = 005
N2.C3.D0.R1.S17: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N4.C3.D0.R0.S13: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N6.C2.D0.R1.S17: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N0.C2.D0.R1.S15: PI = 060, PtrOffset = 005
N2.C3.D0.R1.S09: Preamble found at Latency = 008
N4.C3.D0.R0.S14: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N6.C2.D0.R1.S09: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N0.C2.D0.R1.S16: PI = 012, PtrOffset = 004
N2.C3.D0.R1.S10: Preamble found at Latency = 008
N4.C3.D0.R0.S15: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N6.C2.D0.R1.S10: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N0.C2.D0.R1.S17: PI = 056, PtrOffset = 004
N2.C3.D0.R1.S11: Preamble found at Latency = 008
N4.C3.D0.R0.S16: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N6.C2.D0.R1.S11: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N0.C2.D0.R1.S09: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N2.C3.D0.R1.S14: Preamble found at Latency = 008
N4.C3.D0.R0.S17: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N6.C2.D0.R1.S12: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N0.C2.D0.R1.S10: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N2.C3.D0.R1.S15: Preamble found at Latency = 008
N4.C3.D0.R0.S09: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N6.C2.D0.R1.S13: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N0.C2.D0.R1.S11: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N2.C3.D0.R1.S16: Preamble found at Latency = 008
N4.C3.D0.R0.S10: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N6.C2.D0.R1.S14: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N0.C2.D0.R1.S12: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N2.C3.D0.R1.S09: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N4.C3.D0.R0.S11: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N6.C2.D0.R1.S15: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N0.C2.D0.R1.S13: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N2.C3.D0.R1.S10: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N4.C3.D0.R0.S12: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N6.C2.D0.R1.S16: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N0.C2.D0.R1.S14: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N2.C3.D0.R1.S11: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N4.C3.D0.R0.S13: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N6.C2.D0.R1.S17: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N0.C2.D0.R1.S15: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N2.C3.D0.R1.S12: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N4.C3.D0.R0.S14: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N6.C2.D0.R1.S09: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N0.C2.D0.R1.S16: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N2.C3.D0.R1.S13: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N4.C3.D0.R0.S15: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N6.C2.D0.R1.S10: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N0.C2.D0.R1.S17: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N2.C3.D0.R1.S14: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N4.C3.D0.R0.S16: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N6.C2.D0.R1.S11: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N0.C2.D0.R1.S09: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N2.C3.D0.R1.S15: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N4.C3.D0.R0.S17: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N6.C2.D0.R1.S12: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N0.C2.D0.R1.S10: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N2.C3.D0.R1.S16: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N4.C3.D0.R0.S09: Preamble found at Latency = 008
N6.C2.D0.R1.S13: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N0.C2.D0.R1.S11: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N2.C3.D0.R1.S17: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N4.C3.D0.R0.S10: Preamble found at Latency = 008
N6.C2.D0.R1.S14: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N0.C2.D0.R1.S12: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N2.C3.D0.R1.S12: Preamble found at Latency = 007
N4.C3.D0.R0.S11: Preamble found at Latency = 008
N6.C2.D0.R1.S15: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N0.C2.D0.R1.S13: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N2.C3.D0.R1.S13: Preamble found at Latency = 007
N4.C3.D0.R0.S14: Preamble found at Latency = 008
N6.C2.D0.R1.S16: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N0.C2.D0.R1.S14: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N2.C3.D0.R1.S17: Preamble found at Latency = 007
N4.C3.D0.R0.S15: Preamble found at Latency = 008
N6.C2.D0.R1.S17: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N0.C2.D0.R1.S15: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N2.C3.D0.R1: Preamble found for all upper nibbles, adjusting Pi, Offset to center into preamble
N4.C3.D0.R0.S16: Preamble found at Latency = 008
N6.C2.D0.R1.S09: Preamble found at Latency = 008
N0.C2.D0.R1.S16: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N2.C3.D0.R1.S09: Total Receive Enable Delay = 1372
N4.C3.D0.R0.S09: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N6.C2.D0.R1.S10: Preamble found at Latency = 008
N0.C2.D0.R1.S17: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N2.C3.D0.R1.S10: Total Receive Enable Delay = 1353
N4.C3.D0.R0.S10: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N6.C2.D0.R1.S15: Preamble found at Latency = 008
N0.C2.D0.R1.S09: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N2.C3.D0.R1.S11: Total Receive Enable Delay = 1321
N4.C3.D0.R0.S11: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N6.C2.D0.R1.S16: Preamble found at Latency = 008
N0.C2.D0.R1.S10: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N2.C3.D0.R1.S12: Total Receive Enable Delay = 1304
N4.C3.D0.R0.S12: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N6.C2.D0.R1.S09: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N0.C2.D0.R1.S11: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N2.C3.D0.R1.S13: Total Receive Enable Delay = 1298
N4.C3.D0.R0.S13: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N6.C2.D0.R1.S10: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N0.C2.D0.R1.S12: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N2.C3.D0.R1.S14: Total Receive Enable Delay = 1321
N4.C3.D0.R0.S14: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N6.C2.D0.R1.S11: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N0.C2.D0.R1.S13: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N2.C3.D0.R1.S15: Total Receive Enable Delay = 1347
N4.C3.D0.R0.S15: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N6.C2.D0.R1.S12: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N0.C2.D0.R1.S14: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N2.C3.D0.R1.S16: Total Receive Enable Delay = 1370
N4.C3.D0.R0.S16: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N6.C2.D0.R1.S13: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N0.C2.D0.R1.S15: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N2.C3.D0.R1.S17: Total Receive Enable Delay = 1283
N4.C3.D0.R0.S17: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N6.C2.D0.R1.S14: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N0.C2.D0.R1.S16: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N2.C3.D1.R0: RcvEnFine: Initial RdCmd2RcvEnLatency = 10, Initial RdPtrOffsetRcvEn = 4
N4.C3.D0.R0.S12: Preamble found at Latency = 007
N6.C2.D0.R1.S15: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N0.C2.D0.R1.S17: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N2.C3.D1.R0.S00: Rcv En Fine Value = 302
N4.C3.D0.R0.S13: Preamble found at Latency = 007
N6.C2.D0.R1.S16: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N0.C2.D0.R1.S09: Preamble found at Latency = 008
N2.C3.D1.R0.S01: Rcv En Fine Value = 282
N4.C3.D0.R0.S17: Preamble found at Latency = 007
N6.C2.D0.R1.S17: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N0.C2.D0.R1.S16: Preamble found at Latency = 008
N2.C3.D1.R0.S02: Rcv En Fine Value = 378
N4.C3.D0.R0: Preamble found for all upper nibbles, adjusting Pi, Offset to center into preamble
N6.C2.D0.R1.S11: Preamble found at Latency = 007
N0.C2.D0.R1.S09: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N2.C3.D1.R0.S03: Rcv En Fine Value = 361
N4.C3.D0.R0.S09: Total Receive Enable Delay = 1375
N6.C2.D0.R1.S12: Preamble found at Latency = 007
N0.C2.D0.R1.S10: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N2.C3.D1.R0.S04: Rcv En Fine Value = 354
N4.C3.D0.R0.S10: Total Receive Enable Delay = 1354
N6.C2.D0.R1.S13: Preamble found at Latency = 007
N0.C2.D0.R1.S11: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N2.C3.D1.R0.S05: Rcv En Fine Value = 381
N4.C3.D0.R0.S11: Total Receive Enable Delay = 1326
N6.C2.D0.R1.S14: Preamble found at Latency = 007
N0.C2.D0.R1.S12: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N2.C3.D1.R0.S06: Rcv En Fine Value = 276
N4.C3.D0.R0.S12: Total Receive Enable Delay = 1305
N6.C2.D0.R1.S17: Preamble found at Latency = 007
N0.C2.D0.R1.S13: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N2.C3.D1.R0.S07: Rcv En Fine Value = 298
N4.C3.D0.R0.S13: Total Receive Enable Delay = 1298
N6.C2.D0.R1: Preamble found for all upper nibbles, adjusting Pi, Offset to center into preamble
N0.C2.D0.R1.S14: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N2.C3.D1.R0.S08: Rcv En Fine Value = 341
N4.C3.D0.R0.S14: Total Receive Enable Delay = 1323
N6.C2.D0.R1.S09: Total Receive Enable Delay = 1330
N0.C2.D0.R1.S15: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N2.C3.D1.R0.S09: Rcv En Fine Value = 303
N4.C3.D0.R0.S15: Total Receive Enable Delay = 1347
N6.C2.D0.R1.S10: Total Receive Enable Delay = 1312
N0.C2.D0.R1.S16: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N2.C3.D1.R0.S10: Rcv En Fine Value = 283
N4.C3.D0.R0.S16: Total Receive Enable Delay = 1370
N6.C2.D0.R1.S11: Total Receive Enable Delay = 1277
N0.C2.D0.R1.S17: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N2.C3.D1.R0.S11: Rcv En Fine Value = 381
N4.C3.D0.R0.S17: Total Receive Enable Delay = 1282
N6.C2.D0.R1.S12: Total Receive Enable Delay = 1261
N0.C2.D0.R1.S10: Preamble found at Latency = 007
N2.C3.D1.R0.S12: Rcv En Fine Value = 362
N4.C3.D0.R1: RcvEnFine: Initial RdCmd2RcvEnLatency = 10, Initial RdPtrOffsetRcvEn = 4
N6.C2.D0.R1.S13: Total Receive Enable Delay = 1262
N0.C2.D0.R1.S11: Preamble found at Latency = 007
N2.C3.D1.R0.S13: Rcv En Fine Value = 356
N4.C3.D0.R1.S00: Rcv En Fine Value = 318
N6.C2.D0.R1.S14: Total Receive Enable Delay = 1270
N0.C2.D0.R1.S12: Preamble found at Latency = 007
N2.C3.D1.R0.S14: Rcv En Fine Value = 382
N4.C3.D0.R1.S01: Rcv En Fine Value = 298
N6.C2.D0.R1.S15: Total Receive Enable Delay = 1312
N0.C2.D0.R1.S13: Preamble found at Latency = 007
N2.C3.D1.R0.S15: Rcv En Fine Value = 277
N4.C3.D0.R1.S02: Rcv En Fine Value = 267
N6.C2.D0.R1.S16: Total Receive Enable Delay = 1327
N0.C2.D0.R1.S14: Preamble found at Latency = 007
N2.C3.D1.R0.S16: Rcv En Fine Value = 301
N4.C3.D0.R1.S03: Rcv En Fine Value = 376
N6.C2.D0.R1.S17: Total Receive Enable Delay = 1249
N0.C2.D0.R1.S15: Preamble found at Latency = 007
N2.C3.D1.R0.S17: Rcv En Fine Value = 341
N4.C3.D0.R1.S04: Rcv En Fine Value = 369
N6.C2.D1.R0: RcvEnFine: Initial RdCmd2RcvEnLatency = 10, Initial RdPtrOffsetRcvEn = 4
N0.C2.D0.R1.S17: Preamble found at Latency = 007
N2.C3.D1.R0: Starting preamble search lower nibbles
N4.C3.D0.R1.S05: Rcv En Fine Value = 265
N6.C2.D1.R0.S00: Rcv En Fine Value = 266
N0.C2.D0.R1: Preamble found for all upper nibbles, adjusting Pi, Offset to center into preamble
N2.C3.D1.R0.S00: PI = 046, PtrOffset = 004
N4.C3.D0.R1.S06: Rcv En Fine Value = 292
N6.C2.D1.R0.S01: Rcv En Fine Value = 370
N0.C2.D0.R1.S09: Total Receive Enable Delay = 1330
N2.C3.D1.R0.S01: PI = 026, PtrOffset = 004
N4.C3.D0.R1.S07: Rcv En Fine Value = 313
N6.C2.D1.R0.S02: Rcv En Fine Value = 340
N0.C2.D0.R1.S10: Total Receive Enable Delay = 1310
N2.C3.D1.R0.S02: PI = 058, PtrOffset = 005
N4.C3.D0.R1.S08: Rcv En Fine Value = 355
N6.C2.D1.R0.S03: Rcv En Fine Value = 322
N0.C2.D0.R1.S11: Total Receive Enable Delay = 1275
N2.C3.D1.R0.S03: PI = 041, PtrOffset = 005
N4.C3.D0.R1.S09: Rcv En Fine Value = 318
N6.C2.D1.R0.S04: Rcv En Fine Value = 321
N0.C2.D0.R1.S12: Total Receive Enable Delay = 1255
N2.C3.D1.R0.S04: PI = 034, PtrOffset = 005
N4.C3.D0.R1.S10: Rcv En Fine Value = 299
N6.C2.D1.R0.S05: Rcv En Fine Value = 334
N0.C2.D0.R1.S13: Total Receive Enable Delay = 1257
N2.C3.D1.R0.S05: PI = 061, PtrOffset = 005
N4.C3.D0.R1.S11: Rcv En Fine Value = 270
N6.C2.D1.R0.S06: Rcv En Fine Value = 371
N0.C2.D0.R1.S14: Total Receive Enable Delay = 1267
N2.C3.D1.R0.S06: PI = 020, PtrOffset = 004
N4.C3.D0.R1.S12: Rcv En Fine Value = 377
N6.C2.D1.R0.S07: Rcv En Fine Value = 261
N0.C2.D0.R1.S15: Total Receive Enable Delay = 1308
N2.C3.D1.R0.S07: PI = 042, PtrOffset = 004
N4.C3.D0.R1.S13: Rcv En Fine Value = 370
N6.C2.D1.R0.S08: Rcv En Fine Value = 308
N0.C2.D0.R1.S16: Total Receive Enable Delay = 1324
N2.C3.D1.R0.S08: PI = 021, PtrOffset = 005
N4.C3.D0.R1.S14: Rcv En Fine Value = 266
N6.C2.D1.R0.S09: Rcv En Fine Value = 263
N0.C2.D0.R1.S17: Total Receive Enable Delay = 1240
N2.C3.D1.R0.S00: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N4.C3.D0.R1.S15: Rcv En Fine Value = 292
N6.C2.D1.R0.S10: Rcv En Fine Value = 372
N0.C2.D1.R0: RcvEnFine: Initial RdCmd2RcvEnLatency = 10, Initial RdPtrOffsetRcvEn = 4
N2.C3.D1.R0.S01: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N4.C3.D0.R1.S16: Rcv En Fine Value = 314
N6.C2.D1.R0.S11: Rcv En Fine Value = 339
N0.C2.D1.R0.S00: Rcv En Fine Value = 256
N2.C3.D1.R0.S02: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N4.C3.D0.R1.S17: Rcv En Fine Value = 357
N6.C2.D1.R0.S12: Rcv En Fine Value = 319
N0.C2.D1.R0.S01: Rcv En Fine Value = 359
N2.C3.D1.R0.S03: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N4.C3.D0.R1: Starting preamble search lower nibbles
N6.C2.D1.R0.S13: Rcv En Fine Value = 321
N0.C2.D1.R0.S02: Rcv En Fine Value = 329
N2.C3.D1.R0.S04: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N4.C3.D0.R1.S00: PI = 062, PtrOffset = 004
N6.C2.D1.R0.S14: Rcv En Fine Value = 332
N0.C2.D1.R0.S03: Rcv En Fine Value = 307
N2.C3.D1.R0.S05: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N4.C3.D0.R1.S01: PI = 042, PtrOffset = 004
N6.C2.D1.R0.S15: Rcv En Fine Value = 372
N0.C2.D1.R0.S04: Rcv En Fine Value = 313
N2.C3.D1.R0.S06: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N4.C3.D0.R1.S02: PI = 011, PtrOffset = 004
N6.C2.D1.R0.S16: Rcv En Fine Value = 261
N0.C2.D1.R0.S05: Rcv En Fine Value = 323
N2.C3.D1.R0.S07: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N4.C3.D0.R1.S03: PI = 056, PtrOffset = 005
N6.C2.D1.R0.S17: Rcv En Fine Value = 308
N0.C2.D1.R0.S06: Rcv En Fine Value = 359
N2.C3.D1.R0.S08: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N4.C3.D0.R1.S04: PI = 049, PtrOffset = 005
N6.C2.D1.R0: Starting preamble search lower nibbles
N0.C2.D1.R0.S07: Rcv En Fine Value = 377
N2.C3.D1.R0.S00: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N4.C3.D0.R1.S05: PI = 009, PtrOffset = 004
N6.C2.D1.R0.S00: PI = 010, PtrOffset = 004
N0.C2.D1.R0.S08: Rcv En Fine Value = 300
N2.C3.D1.R0.S01: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N4.C3.D0.R1.S06: PI = 036, PtrOffset = 004
N6.C2.D1.R0.S01: PI = 050, PtrOffset = 005
N0.C2.D1.R0.S09: Rcv En Fine Value = 381
N2.C3.D1.R0.S02: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N4.C3.D0.R1.S07: PI = 057, PtrOffset = 004
N6.C2.D1.R0.S02: PI = 020, PtrOffset = 005
N0.C2.D1.R0.S10: Rcv En Fine Value = 357
N2.C3.D1.R0.S03: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N4.C3.D0.R1.S08: PI = 035, PtrOffset = 005
N6.C2.D1.R0.S03: PI = 002, PtrOffset = 005
N0.C2.D1.R0.S11: Rcv En Fine Value = 330
N2.C3.D1.R0.S04: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N4.C3.D0.R1.S00: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N6.C2.D1.R0.S04: PI = 001, PtrOffset = 005
N0.C2.D1.R0.S12: Rcv En Fine Value = 307
N2.C3.D1.R0.S05: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N4.C3.D0.R1.S01: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N6.C2.D1.R0.S05: PI = 014, PtrOffset = 005
N0.C2.D1.R0.S13: Rcv En Fine Value = 312
N2.C3.D1.R0.S06: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N4.C3.D0.R1.S02: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N6.C2.D1.R0.S06: PI = 051, PtrOffset = 005
N0.C2.D1.R0.S14: Rcv En Fine Value = 323
N2.C3.D1.R0.S07: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N4.C3.D0.R1.S03: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N6.C2.D1.R0.S07: PI = 005, PtrOffset = 004
N0.C2.D1.R0.S15: Rcv En Fine Value = 359
N2.C3.D1.R0.S08: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N4.C3.D0.R1.S04: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N6.C2.D1.R0.S08: PI = 052, PtrOffset = 004
N0.C2.D1.R0.S16: Rcv En Fine Value = 375
N2.C3.D1.R0.S00: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N4.C3.D0.R1.S05: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N6.C2.D1.R0.S00: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N0.C2.D1.R0.S17: Rcv En Fine Value = 296
N2.C3.D1.R0.S01: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N4.C3.D0.R1.S06: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N6.C2.D1.R0.S01: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N0.C2.D1.R0: Starting preamble search lower nibbles
N2.C3.D1.R0.S02: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N4.C3.D0.R1.S07: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N6.C2.D1.R0.S02: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N0.C2.D1.R0.S00: PI = 000, PtrOffset = 004
N2.C3.D1.R0.S03: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N4.C3.D0.R1.S08: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N6.C2.D1.R0.S03: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N0.C2.D1.R0.S01: PI = 039, PtrOffset = 005
N2.C3.D1.R0.S04: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N4.C3.D0.R1.S00: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N6.C2.D1.R0.S04: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N0.C2.D1.R0.S02: PI = 009, PtrOffset = 005
N2.C3.D1.R0.S05: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N4.C3.D0.R1.S01: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N6.C2.D1.R0.S05: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N0.C2.D1.R0.S03: PI = 051, PtrOffset = 004
N2.C3.D1.R0.S06: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N4.C3.D0.R1.S02: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N6.C2.D1.R0.S06: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N0.C2.D1.R0.S04: PI = 057, PtrOffset = 004
N2.C3.D1.R0.S07: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N4.C3.D0.R1.S03: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N6.C2.D1.R0.S07: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N0.C2.D1.R0.S05: PI = 003, PtrOffset = 005
N2.C3.D1.R0.S08: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N4.C3.D0.R1.S04: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N6.C2.D1.R0.S08: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N0.C2.D1.R0.S06: PI = 039, PtrOffset = 005
N2.C3.D1.R0.S00: Preamble found at Latency = 008
N4.C3.D0.R1.S05: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N6.C2.D1.R0.S00: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N0.C2.D1.R0.S07: PI = 057, PtrOffset = 005
N2.C3.D1.R0.S01: Preamble found at Latency = 008
N4.C3.D0.R1.S06: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N6.C2.D1.R0.S01: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N0.C2.D1.R0.S08: PI = 044, PtrOffset = 004
N2.C3.D1.R0.S06: Preamble found at Latency = 008
N4.C3.D0.R1.S07: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N6.C2.D1.R0.S02: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N0.C2.D1.R0.S00: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N2.C3.D1.R0.S07: Preamble found at Latency = 008
N4.C3.D0.R1.S08: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N6.C2.D1.R0.S03: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N0.C2.D1.R0.S01: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N2.C3.D1.R0.S00: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N4.C3.D0.R1.S00: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N6.C2.D1.R0.S04: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N0.C2.D1.R0.S02: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N2.C3.D1.R0.S01: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N4.C3.D0.R1.S01: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N6.C2.D1.R0.S05: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N0.C2.D1.R0.S03: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N2.C3.D1.R0.S02: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N4.C3.D0.R1.S02: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N6.C2.D1.R0.S06: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N0.C2.D1.R0.S04: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N2.C3.D1.R0.S03: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N4.C3.D0.R1.S03: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N6.C2.D1.R0.S07: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N0.C2.D1.R0.S05: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N2.C3.D1.R0.S04: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N4.C3.D0.R1.S04: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N6.C2.D1.R0.S08: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N0.C2.D1.R0.S06: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N2.C3.D1.R0.S05: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N4.C3.D0.R1.S05: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N6.C2.D1.R0.S00: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N0.C2.D1.R0.S07: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N2.C3.D1.R0.S06: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N4.C3.D0.R1.S06: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N6.C2.D1.R0.S01: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N0.C2.D1.R0.S08: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N2.C3.D1.R0.S07: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N4.C3.D0.R1.S07: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N6.C2.D1.R0.S02: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N0.C2.D1.R0.S00: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N2.C3.D1.R0.S08: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N4.C3.D0.R1.S08: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N6.C2.D1.R0.S03: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N0.C2.D1.R0.S01: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N2.C3.D1.R0.S02: Preamble found at Latency = 007
N4.C3.D0.R1.S00: Preamble found at Latency = 008
N6.C2.D1.R0.S04: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N0.C2.D1.R0.S02: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N2.C3.D1.R0.S03: Preamble found at Latency = 007
N4.C3.D0.R1.S01: Preamble found at Latency = 008
N6.C2.D1.R0.S05: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N0.C2.D1.R0.S03: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N2.C3.D1.R0.S04: Preamble found at Latency = 007
N4.C3.D0.R1.S02: Preamble found at Latency = 008
N6.C2.D1.R0.S06: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N0.C2.D1.R0.S04: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N2.C3.D1.R0.S05: Preamble found at Latency = 007
N4.C3.D0.R1.S05: Preamble found at Latency = 008
N6.C2.D1.R0.S07: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N0.C2.D1.R0.S05: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N2.C3.D1.R0.S08: Preamble found at Latency = 007
N4.C3.D0.R1.S06: Preamble found at Latency = 008
N6.C2.D1.R0.S08: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N0.C2.D1.R0.S06: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N2.C3.D1.R0.S00: Total Receive Enable Delay = 1358
N4.C3.D0.R1.S07: Preamble found at Latency = 008
N6.C2.D1.R0.S00: Preamble found at Latency = 008
N0.C2.D1.R0.S07: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N2.C3.D1.R0.S01: Total Receive Enable Delay = 1338
N4.C3.D0.R1.S00: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N6.C2.D1.R0.S07: Preamble found at Latency = 008
N0.C2.D1.R0.S08: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N2.C3.D1.R0.S02: Total Receive Enable Delay = 1306
N4.C3.D0.R1.S01: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N6.C2.D1.R0.S00: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N0.C2.D1.R0.S00: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N2.C3.D1.R0.S03: Total Receive Enable Delay = 1289
N4.C3.D0.R1.S02: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N6.C2.D1.R0.S01: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N0.C2.D1.R0.S01: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N2.C3.D1.R0.S04: Total Receive Enable Delay = 1282
N4.C3.D0.R1.S03: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N6.C2.D1.R0.S02: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N0.C2.D1.R0.S02: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N2.C3.D1.R0.S05: Total Receive Enable Delay = 1309
N4.C3.D0.R1.S04: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N6.C2.D1.R0.S03: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N0.C2.D1.R0.S03: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N2.C3.D1.R0.S06: Total Receive Enable Delay = 1332
N4.C3.D0.R1.S05: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N6.C2.D1.R0.S04: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N0.C2.D1.R0.S04: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N2.C3.D1.R0.S07: Total Receive Enable Delay = 1354
N4.C3.D0.R1.S06: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N6.C2.D1.R0.S05: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N0.C2.D1.R0.S05: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N2.C3.D1.R0.S08: Total Receive Enable Delay = 1269
N4.C3.D0.R1.S07: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N6.C2.D1.R0.S06: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N0.C2.D1.R0.S06: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N2.C3.D1.R0: Starting preamble search upper nibbles
N4.C3.D0.R1.S08: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N6.C2.D1.R0.S07: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N0.C2.D1.R0.S07: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N2.C3.D1.R0.S09: PI = 047, PtrOffset = 004
N4.C3.D0.R1.S03: Preamble found at Latency = 007
N6.C2.D1.R0.S08: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N0.C2.D1.R0.S08: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N2.C3.D1.R0.S10: PI = 027, PtrOffset = 004
N4.C3.D0.R1.S04: Preamble found at Latency = 007
N6.C2.D1.R0.S01: Preamble found at Latency = 007
N0.C2.D1.R0.S00: Preamble found at Latency = 008
N2.C3.D1.R0.S11: PI = 061, PtrOffset = 005
N4.C3.D0.R1.S08: Preamble found at Latency = 007
N6.C2.D1.R0.S02: Preamble found at Latency = 007
N0.C2.D1.R0.S00: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N2.C3.D1.R0.S12: PI = 042, PtrOffset = 005
N4.C3.D0.R1.S00: Total Receive Enable Delay = 1374
N6.C2.D1.R0.S03: Preamble found at Latency = 007
N0.C2.D1.R0.S01: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N2.C3.D1.R0.S13: PI = 036, PtrOffset = 005
N4.C3.D0.R1.S01: Total Receive Enable Delay = 1354
N6.C2.D1.R0.S04: Preamble found at Latency = 007
N0.C2.D1.R0.S02: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N2.C3.D1.R0.S14: PI = 062, PtrOffset = 005
N4.C3.D0.R1.S02: Total Receive Enable Delay = 1323
N6.C2.D1.R0.S05: Preamble found at Latency = 007
N0.C2.D1.R0.S03: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N2.C3.D1.R0.S15: PI = 021, PtrOffset = 004
N4.C3.D0.R1.S03: Total Receive Enable Delay = 1304
N6.C2.D1.R0.S06: Preamble found at Latency = 007
N0.C2.D1.R0.S04: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N2.C3.D1.R0.S16: PI = 045, PtrOffset = 004
N4.C3.D0.R1.S04: Total Receive Enable Delay = 1297
N6.C2.D1.R0.S08: Preamble found at Latency = 007
N0.C2.D1.R0.S05: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N2.C3.D1.R0.S17: PI = 021, PtrOffset = 005
N4.C3.D0.R1.S05: Total Receive Enable Delay = 1321
N6.C2.D1.R0.S00: Total Receive Enable Delay = 1322
N0.C2.D1.R0.S06: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N2.C3.D1.R0.S09: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N4.C3.D0.R1.S06: Total Receive Enable Delay = 1348
N6.C2.D1.R0.S01: Total Receive Enable Delay = 1298
N0.C2.D1.R0.S07: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N2.C3.D1.R0.S10: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N4.C3.D0.R1.S07: Total Receive Enable Delay = 1369
N6.C2.D1.R0.S02: Total Receive Enable Delay = 1268
N0.C2.D1.R0.S08: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N2.C3.D1.R0.S11: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N4.C3.D0.R1.S08: Total Receive Enable Delay = 1283
N6.C2.D1.R0.S03: Total Receive Enable Delay = 1250
N0.C2.D1.R0.S01: Preamble found at Latency = 007
N2.C3.D1.R0.S12: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N4.C3.D0.R1: Starting preamble search upper nibbles
N6.C2.D1.R0.S04: Total Receive Enable Delay = 1249
N0.C2.D1.R0.S02: Preamble found at Latency = 007
N2.C3.D1.R0.S13: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N4.C3.D0.R1.S09: PI = 062, PtrOffset = 004
N6.C2.D1.R0.S05: Total Receive Enable Delay = 1262
N0.C2.D1.R0.S03: Preamble found at Latency = 007
N2.C3.D1.R0.S14: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N4.C3.D0.R1.S10: PI = 043, PtrOffset = 004
N6.C2.D1.R0.S06: Total Receive Enable Delay = 1299
N0.C2.D1.R0.S04: Preamble found at Latency = 007
N2.C3.D1.R0.S15: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N4.C3.D0.R1.S11: PI = 014, PtrOffset = 004
N6.C2.D1.R0.S07: Total Receive Enable Delay = 1317
N0.C2.D1.R0.S05: Preamble found at Latency = 007
N2.C3.D1.R0.S16: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N4.C3.D0.R1.S12: PI = 057, PtrOffset = 005
N6.C2.D1.R0.S08: Total Receive Enable Delay = 1236
N0.C2.D1.R0.S06: Preamble found at Latency = 007
N2.C3.D1.R0.S17: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N4.C3.D0.R1.S13: PI = 050, PtrOffset = 005
N6.C2.D1.R0: Starting preamble search upper nibbles
N0.C2.D1.R0.S07: Preamble found at Latency = 007
N2.C3.D1.R0.S09: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N4.C3.D0.R1.S14: PI = 010, PtrOffset = 004
N6.C2.D1.R0.S09: PI = 007, PtrOffset = 004
N0.C2.D1.R0.S08: Preamble found at Latency = 007
N2.C3.D1.R0.S10: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N4.C3.D0.R1.S15: PI = 036, PtrOffset = 004
N6.C2.D1.R0.S10: PI = 052, PtrOffset = 005
N0.C2.D1.R0.S00: Total Receive Enable Delay = 1312
N2.C3.D1.R0.S11: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N4.C3.D0.R1.S16: PI = 058, PtrOffset = 004
N6.C2.D1.R0.S11: PI = 019, PtrOffset = 005
N0.C2.D1.R0.S01: Total Receive Enable Delay = 1287
N2.C3.D1.R0.S12: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N4.C3.D0.R1.S17: PI = 037, PtrOffset = 005
N6.C2.D1.R0.S12: PI = 063, PtrOffset = 004
N0.C2.D1.R0.S02: Total Receive Enable Delay = 1257
N2.C3.D1.R0.S13: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N4.C3.D0.R1.S09: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N6.C2.D1.R0.S13: PI = 001, PtrOffset = 005
N0.C2.D1.R0.S03: Total Receive Enable Delay = 1235
N2.C3.D1.R0.S14: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N4.C3.D0.R1.S10: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N6.C2.D1.R0.S14: PI = 012, PtrOffset = 005
N0.C2.D1.R0.S04: Total Receive Enable Delay = 1241
N2.C3.D1.R0.S15: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N4.C3.D0.R1.S11: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N6.C2.D1.R0.S15: PI = 052, PtrOffset = 005
N0.C2.D1.R0.S05: Total Receive Enable Delay = 1251
N2.C3.D1.R0.S16: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N4.C3.D0.R1.S12: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N6.C2.D1.R0.S16: PI = 005, PtrOffset = 004
N0.C2.D1.R0.S06: Total Receive Enable Delay = 1287
N2.C3.D1.R0.S17: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N4.C3.D0.R1.S13: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N6.C2.D1.R0.S17: PI = 052, PtrOffset = 004
N0.C2.D1.R0.S07: Total Receive Enable Delay = 1305
N2.C3.D1.R0.S09: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N4.C3.D0.R1.S14: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N6.C2.D1.R0.S09: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N0.C2.D1.R0.S08: Total Receive Enable Delay = 1228
N2.C3.D1.R0.S10: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N4.C3.D0.R1.S15: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N6.C2.D1.R0.S10: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N0.C2.D1.R0: Starting preamble search upper nibbles
N2.C3.D1.R0.S11: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N4.C3.D0.R1.S16: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N6.C2.D1.R0.S11: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N0.C2.D1.R0.S09: PI = 061, PtrOffset = 005
N2.C3.D1.R0.S12: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N4.C3.D0.R1.S17: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N6.C2.D1.R0.S12: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N0.C2.D1.R0.S10: PI = 037, PtrOffset = 005
N2.C3.D1.R0.S13: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N4.C3.D0.R1.S09: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N6.C2.D1.R0.S13: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N0.C2.D1.R0.S11: PI = 010, PtrOffset = 005
N2.C3.D1.R0.S14: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N4.C3.D0.R1.S10: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N6.C2.D1.R0.S14: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N0.C2.D1.R0.S12: PI = 051, PtrOffset = 004
N2.C3.D1.R0.S15: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N4.C3.D0.R1.S11: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N6.C2.D1.R0.S15: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N0.C2.D1.R0.S13: PI = 056, PtrOffset = 004
N2.C3.D1.R0.S16: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N4.C3.D0.R1.S12: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N6.C2.D1.R0.S16: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N0.C2.D1.R0.S14: PI = 003, PtrOffset = 005
N2.C3.D1.R0.S17: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N4.C3.D0.R1.S13: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N6.C2.D1.R0.S17: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N0.C2.D1.R0.S15: PI = 039, PtrOffset = 005
N2.C3.D1.R0.S09: Preamble found at Latency = 008
N4.C3.D0.R1.S14: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N6.C2.D1.R0.S09: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N0.C2.D1.R0.S16: PI = 055, PtrOffset = 005
N2.C3.D1.R0.S10: Preamble found at Latency = 008
N4.C3.D0.R1.S15: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N6.C2.D1.R0.S10: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N0.C2.D1.R0.S17: PI = 040, PtrOffset = 004
N2.C3.D1.R0.S15: Preamble found at Latency = 008
N4.C3.D0.R1.S16: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N6.C2.D1.R0.S11: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N0.C2.D1.R0.S09: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N2.C3.D1.R0.S16: Preamble found at Latency = 008
N4.C3.D0.R1.S17: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N6.C2.D1.R0.S12: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N0.C2.D1.R0.S10: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N2.C3.D1.R0.S09: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N4.C3.D0.R1.S09: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N6.C2.D1.R0.S13: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N0.C2.D1.R0.S11: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N2.C3.D1.R0.S10: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N4.C3.D0.R1.S10: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N6.C2.D1.R0.S14: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N0.C2.D1.R0.S12: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N2.C3.D1.R0.S11: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N4.C3.D0.R1.S11: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N6.C2.D1.R0.S15: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N0.C2.D1.R0.S13: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N2.C3.D1.R0.S12: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N4.C3.D0.R1.S12: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N6.C2.D1.R0.S16: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N0.C2.D1.R0.S14: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N2.C3.D1.R0.S13: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N4.C3.D0.R1.S13: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N6.C2.D1.R0.S17: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N0.C2.D1.R0.S15: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N2.C3.D1.R0.S14: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N4.C3.D0.R1.S14: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N6.C2.D1.R0.S09: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N0.C2.D1.R0.S16: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N2.C3.D1.R0.S15: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N4.C3.D0.R1.S15: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N6.C2.D1.R0.S10: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N0.C2.D1.R0.S17: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N2.C3.D1.R0.S16: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N4.C3.D0.R1.S16: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N6.C2.D1.R0.S11: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N0.C2.D1.R0.S09: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N2.C3.D1.R0.S17: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N4.C3.D0.R1.S17: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N6.C2.D1.R0.S12: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N0.C2.D1.R0.S10: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N2.C3.D1.R0.S11: Preamble found at Latency = 007
N4.C3.D0.R1.S09: Preamble found at Latency = 008
N6.C2.D1.R0.S13: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N0.C2.D1.R0.S11: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N2.C3.D1.R0.S12: Preamble found at Latency = 007
N4.C3.D0.R1.S10: Preamble found at Latency = 008
N6.C2.D1.R0.S14: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N0.C2.D1.R0.S12: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N2.C3.D1.R0.S13: Preamble found at Latency = 007
N4.C3.D0.R1.S11: Preamble found at Latency = 008
N6.C2.D1.R0.S15: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N0.C2.D1.R0.S13: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N2.C3.D1.R0.S14: Preamble found at Latency = 007
N4.C3.D0.R1.S14: Preamble found at Latency = 008
N6.C2.D1.R0.S16: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N0.C2.D1.R0.S14: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N2.C3.D1.R0.S17: Preamble found at Latency = 007
N4.C3.D0.R1.S15: Preamble found at Latency = 008
N6.C2.D1.R0.S17: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N0.C2.D1.R0.S15: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N2.C3.D1.R0: Preamble found for all upper nibbles, adjusting Pi, Offset to center into preamble
N4.C3.D0.R1.S16: Preamble found at Latency = 008
N6.C2.D1.R0.S09: Preamble found at Latency = 008
N0.C2.D1.R0.S16: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N2.C3.D1.R0.S09: Total Receive Enable Delay = 1359
N4.C3.D0.R1.S09: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N6.C2.D1.R0.S16: Preamble found at Latency = 008
N0.C2.D1.R0.S17: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N2.C3.D1.R0.S10: Total Receive Enable Delay = 1339
N4.C3.D0.R1.S10: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N6.C2.D1.R0.S09: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N0.C2.D1.R0.S09: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N2.C3.D1.R0.S11: Total Receive Enable Delay = 1309
N4.C3.D0.R1.S11: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N6.C2.D1.R0.S10: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N0.C2.D1.R0.S10: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N2.C3.D1.R0.S12: Total Receive Enable Delay = 1290
N4.C3.D0.R1.S12: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N6.C2.D1.R0.S11: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N0.C2.D1.R0.S11: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N2.C3.D1.R0.S13: Total Receive Enable Delay = 1284
N4.C3.D0.R1.S13: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N6.C2.D1.R0.S12: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N0.C2.D1.R0.S12: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N2.C3.D1.R0.S14: Total Receive Enable Delay = 1310
N4.C3.D0.R1.S14: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N6.C2.D1.R0.S13: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N0.C2.D1.R0.S13: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N2.C3.D1.R0.S15: Total Receive Enable Delay = 1333
N4.C3.D0.R1.S15: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N6.C2.D1.R0.S14: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N0.C2.D1.R0.S14: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N2.C3.D1.R0.S16: Total Receive Enable Delay = 1357
N4.C3.D0.R1.S16: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N6.C2.D1.R0.S15: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N0.C2.D1.R0.S15: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N2.C3.D1.R0.S17: Total Receive Enable Delay = 1269
N4.C3.D0.R1.S17: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N6.C2.D1.R0.S16: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N0.C2.D1.R0.S16: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N2.C3.D1.R1: RcvEnFine: Initial RdCmd2RcvEnLatency = 10, Initial RdPtrOffsetRcvEn = 4
N4.C3.D0.R1.S12: Preamble found at Latency = 007
N6.C2.D1.R0.S17: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N0.C2.D1.R0.S17: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N2.C3.D1.R1.S00: Rcv En Fine Value = 300
N4.C3.D0.R1.S13: Preamble found at Latency = 007
N6.C2.D1.R0.S10: Preamble found at Latency = 007
N0.C2.D1.R0.S09: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N2.C3.D1.R1.S01: Rcv En Fine Value = 282
N4.C3.D0.R1.S17: Preamble found at Latency = 007
N6.C2.D1.R0.S11: Preamble found at Latency = 007
N0.C2.D1.R0.S10: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N2.C3.D1.R1.S02: Rcv En Fine Value = 378
N4.C3.D0.R1: Preamble found for all upper nibbles, adjusting Pi, Offset to center into preamble
N6.C2.D1.R0.S12: Preamble found at Latency = 007
N0.C2.D1.R0.S11: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N2.C3.D1.R1.S03: Rcv En Fine Value = 359
N4.C3.D0.R1.S09: Total Receive Enable Delay = 1374
N6.C2.D1.R0.S13: Preamble found at Latency = 007
N0.C2.D1.R0.S12: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N2.C3.D1.R1.S04: Rcv En Fine Value = 356
N4.C3.D0.R1.S10: Total Receive Enable Delay = 1355
N6.C2.D1.R0.S14: Preamble found at Latency = 007
N0.C2.D1.R0.S13: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N2.C3.D1.R1.S05: Rcv En Fine Value = 380
N4.C3.D0.R1.S11: Total Receive Enable Delay = 1326
N6.C2.D1.R0.S15: Preamble found at Latency = 007
N0.C2.D1.R0.S14: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N2.C3.D1.R1.S06: Rcv En Fine Value = 275
N4.C3.D0.R1.S12: Total Receive Enable Delay = 1305
N6.C2.D1.R0.S17: Preamble found at Latency = 007
N0.C2.D1.R0.S15: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N2.C3.D1.R1.S07: Rcv En Fine Value = 298
N4.C3.D0.R1.S13: Total Receive Enable Delay = 1298
N6.C2.D1.R0: Preamble found for all upper nibbles, adjusting Pi, Offset to center into preamble
N0.C2.D1.R0.S16: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N2.C3.D1.R1.S08: Rcv En Fine Value = 340
N4.C3.D0.R1.S14: Total Receive Enable Delay = 1322
N6.C2.D1.R0.S09: Total Receive Enable Delay = 1319
N0.C2.D1.R0.S17: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N2.C3.D1.R1.S09: Rcv En Fine Value = 302
N4.C3.D0.R1.S15: Total Receive Enable Delay = 1348
N6.C2.D1.R0.S10: Total Receive Enable Delay = 1300
N0.C2.D1.R0.S09: Preamble found at Latency = 007
N2.C3.D1.R1.S10: Rcv En Fine Value = 283
N4.C3.D0.R1.S16: Total Receive Enable Delay = 1370
N6.C2.D1.R0.S11: Total Receive Enable Delay = 1267
N0.C2.D1.R0.S10: Preamble found at Latency = 007
N2.C3.D1.R1.S11: Rcv En Fine Value = 379
N4.C3.D0.R1.S17: Total Receive Enable Delay = 1285
N6.C2.D1.R0.S12: Total Receive Enable Delay = 1247
N0.C2.D1.R0.S11: Preamble found at Latency = 007
N2.C3.D1.R1.S12: Rcv En Fine Value = 362
N4.C3.D1.R0: RcvEnFine: Initial RdCmd2RcvEnLatency = 10, Initial RdPtrOffsetRcvEn = 4
N6.C2.D1.R0.S13: Total Receive Enable Delay = 1249
N0.C2.D1.R0.S12: Preamble found at Latency = 007
N2.C3.D1.R1.S13: Rcv En Fine Value = 356
N4.C3.D1.R0.S00: Rcv En Fine Value = 303
N6.C2.D1.R0.S14: Total Receive Enable Delay = 1260
N0.C2.D1.R0.S13: Preamble found at Latency = 007
N2.C3.D1.R1.S14: Rcv En Fine Value = 379
N4.C3.D1.R0.S01: Rcv En Fine Value = 285
N6.C2.D1.R0.S15: Total Receive Enable Delay = 1300
N0.C2.D1.R0.S14: Preamble found at Latency = 007
N2.C3.D1.R1.S15: Rcv En Fine Value = 277
N4.C3.D1.R0.S02: Rcv En Fine Value = 256
N6.C2.D1.R0.S16: Total Receive Enable Delay = 1317
N0.C2.D1.R0.S15: Preamble found at Latency = 007
N2.C3.D1.R1.S16: Rcv En Fine Value = 297
N4.C3.D1.R0.S03: Rcv En Fine Value = 362
N6.C2.D1.R0.S17: Total Receive Enable Delay = 1236
N0.C2.D1.R0.S16: Preamble found at Latency = 007
N2.C3.D1.R1.S17: Rcv En Fine Value = 340
N4.C3.D1.R0.S04: Rcv En Fine Value = 356
N6.C2.D1.R1: RcvEnFine: Initial RdCmd2RcvEnLatency = 10, Initial RdPtrOffsetRcvEn = 4
N0.C2.D1.R0.S17: Preamble found at Latency = 007
N2.C3.D1.R1: Starting preamble search lower nibbles
N4.C3.D1.R0.S05: Rcv En Fine Value = 381
N6.C2.D1.R1.S00: Rcv En Fine Value = 266
N0.C2.D1.R0: Preamble found for all upper nibbles, adjusting Pi, Offset to center into preamble
N2.C3.D1.R1.S00: PI = 044, PtrOffset = 004
N4.C3.D1.R0.S06: Rcv En Fine Value = 277
N6.C2.D1.R1.S01: Rcv En Fine Value = 369
N0.C2.D1.R0.S09: Total Receive Enable Delay = 1309
N2.C3.D1.R1.S01: PI = 026, PtrOffset = 004
N4.C3.D1.R0.S07: Rcv En Fine Value = 299
N6.C2.D1.R1.S02: Rcv En Fine Value = 339
N0.C2.D1.R0.S10: Total Receive Enable Delay = 1285
N2.C3.D1.R1.S02: PI = 058, PtrOffset = 005
N4.C3.D1.R0.S08: Rcv En Fine Value = 344
N6.C2.D1.R1.S03: Rcv En Fine Value = 321
N0.C2.D1.R0.S11: Total Receive Enable Delay = 1258
N2.C3.D1.R1.S03: PI = 039, PtrOffset = 005
N4.C3.D1.R0.S09: Rcv En Fine Value = 305
N6.C2.D1.R1.S04: Rcv En Fine Value = 319
N0.C2.D1.R0.S12: Total Receive Enable Delay = 1235
N2.C3.D1.R1.S04: PI = 036, PtrOffset = 005
N4.C3.D1.R0.S10: Rcv En Fine Value = 283
N6.C2.D1.R1.S05: Rcv En Fine Value = 334
N0.C2.D1.R0.S13: Total Receive Enable Delay = 1240
N2.C3.D1.R1.S05: PI = 060, PtrOffset = 005
N4.C3.D1.R0.S11: Rcv En Fine Value = 383
N6.C2.D1.R1.S06: Rcv En Fine Value = 373
N0.C2.D1.R0.S14: Total Receive Enable Delay = 1251
N2.C3.D1.R1.S06: PI = 019, PtrOffset = 004
N4.C3.D1.R0.S12: Rcv En Fine Value = 364
N6.C2.D1.R1.S07: Rcv En Fine Value = 260
N0.C2.D1.R0.S15: Total Receive Enable Delay = 1287
N2.C3.D1.R1.S07: PI = 042, PtrOffset = 004
N4.C3.D1.R0.S13: Rcv En Fine Value = 357
N6.C2.D1.R1.S08: Rcv En Fine Value = 306
N0.C2.D1.R0.S16: Total Receive Enable Delay = 1303
N2.C3.D1.R1.S08: PI = 020, PtrOffset = 005
N4.C3.D1.R0.S14: Rcv En Fine Value = 382
N6.C2.D1.R1.S09: Rcv En Fine Value = 264
N0.C2.D1.R0.S17: Total Receive Enable Delay = 1224
N2.C3.D1.R1.S00: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N4.C3.D1.R0.S15: Rcv En Fine Value = 276
N6.C2.D1.R1.S10: Rcv En Fine Value = 373
N0.C2.D1.R1: RcvEnFine: Initial RdCmd2RcvEnLatency = 10, Initial RdPtrOffsetRcvEn = 4
N2.C3.D1.R1.S01: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N4.C3.D1.R0.S16: Rcv En Fine Value = 298
N6.C2.D1.R1.S11: Rcv En Fine Value = 339
N0.C2.D1.R1.S00: Rcv En Fine Value = 383
N2.C3.D1.R1.S02: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N4.C3.D1.R0.S17: Rcv En Fine Value = 342
N6.C2.D1.R1.S12: Rcv En Fine Value = 321
N0.C2.D1.R1.S01: Rcv En Fine Value = 360
N2.C3.D1.R1.S03: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N4.C3.D1.R0: Starting preamble search lower nibbles
N6.C2.D1.R1.S13: Rcv En Fine Value = 318
N0.C2.D1.R1.S02: Rcv En Fine Value = 327
N2.C3.D1.R1.S04: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N4.C3.D1.R0.S00: PI = 047, PtrOffset = 004
N6.C2.D1.R1.S14: Rcv En Fine Value = 332
N0.C2.D1.R1.S03: Rcv En Fine Value = 306
N2.C3.D1.R1.S05: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N4.C3.D1.R0.S01: PI = 029, PtrOffset = 004
N6.C2.D1.R1.S15: Rcv En Fine Value = 370
N0.C2.D1.R1.S04: Rcv En Fine Value = 308
N2.C3.D1.R1.S06: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N4.C3.D1.R0.S02: PI = 000, PtrOffset = 004
N6.C2.D1.R1.S16: Rcv En Fine Value = 259
N0.C2.D1.R1.S05: Rcv En Fine Value = 322
N2.C3.D1.R1.S07: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N4.C3.D1.R0.S03: PI = 042, PtrOffset = 005
N6.C2.D1.R1.S17: Rcv En Fine Value = 309
N0.C2.D1.R1.S06: Rcv En Fine Value = 359
N2.C3.D1.R1.S08: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N4.C3.D1.R0.S04: PI = 036, PtrOffset = 005
N6.C2.D1.R1: Starting preamble search lower nibbles
N0.C2.D1.R1.S07: Rcv En Fine Value = 377
N2.C3.D1.R1.S00: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N4.C3.D1.R0.S05: PI = 061, PtrOffset = 005
N6.C2.D1.R1.S00: PI = 010, PtrOffset = 004
N0.C2.D1.R1.S08: Rcv En Fine Value = 298
N2.C3.D1.R1.S01: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N4.C3.D1.R0.S06: PI = 021, PtrOffset = 004
N6.C2.D1.R1.S01: PI = 049, PtrOffset = 005
N0.C2.D1.R1.S09: Rcv En Fine Value = 257
N2.C3.D1.R1.S02: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N4.C3.D1.R0.S07: PI = 043, PtrOffset = 004
N6.C2.D1.R1.S02: PI = 019, PtrOffset = 005
N0.C2.D1.R1.S10: Rcv En Fine Value = 359
N2.C3.D1.R1.S03: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N4.C3.D1.R0.S08: PI = 024, PtrOffset = 005
N6.C2.D1.R1.S03: PI = 001, PtrOffset = 005
N0.C2.D1.R1.S11: Rcv En Fine Value = 327
N2.C3.D1.R1.S04: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N4.C3.D1.R0.S00: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N6.C2.D1.R1.S04: PI = 063, PtrOffset = 004
N0.C2.D1.R1.S12: Rcv En Fine Value = 306
N2.C3.D1.R1.S05: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N4.C3.D1.R0.S01: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N6.C2.D1.R1.S05: PI = 014, PtrOffset = 005
N0.C2.D1.R1.S13: Rcv En Fine Value = 310
N2.C3.D1.R1.S06: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N4.C3.D1.R0.S02: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N6.C2.D1.R1.S06: PI = 053, PtrOffset = 005
N0.C2.D1.R1.S14: Rcv En Fine Value = 321
N2.C3.D1.R1.S07: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N4.C3.D1.R0.S03: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N6.C2.D1.R1.S07: PI = 004, PtrOffset = 004
N0.C2.D1.R1.S15: Rcv En Fine Value = 359
N2.C3.D1.R1.S08: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N4.C3.D1.R0.S04: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N6.C2.D1.R1.S08: PI = 050, PtrOffset = 004
N0.C2.D1.R1.S16: Rcv En Fine Value = 376
N2.C3.D1.R1.S00: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N4.C3.D1.R0.S05: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N6.C2.D1.R1.S00: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N0.C2.D1.R1.S17: Rcv En Fine Value = 295
N2.C3.D1.R1.S01: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N4.C3.D1.R0.S06: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N6.C2.D1.R1.S01: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N0.C2.D1.R1: Starting preamble search lower nibbles
N2.C3.D1.R1.S02: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N4.C3.D1.R0.S07: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N6.C2.D1.R1.S02: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N0.C2.D1.R1.S00: PI = 063, PtrOffset = 005
N2.C3.D1.R1.S03: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N4.C3.D1.R0.S08: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N6.C2.D1.R1.S03: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N0.C2.D1.R1.S01: PI = 040, PtrOffset = 005
N2.C3.D1.R1.S04: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N4.C3.D1.R0.S00: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N6.C2.D1.R1.S04: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N0.C2.D1.R1.S02: PI = 007, PtrOffset = 005
N2.C3.D1.R1.S05: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N4.C3.D1.R0.S01: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N6.C2.D1.R1.S05: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N0.C2.D1.R1.S03: PI = 050, PtrOffset = 004
N2.C3.D1.R1.S06: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N4.C3.D1.R0.S02: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N6.C2.D1.R1.S06: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N0.C2.D1.R1.S04: PI = 052, PtrOffset = 004
N2.C3.D1.R1.S07: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N4.C3.D1.R0.S03: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N6.C2.D1.R1.S07: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N0.C2.D1.R1.S05: PI = 002, PtrOffset = 005
N2.C3.D1.R1.S08: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N4.C3.D1.R0.S04: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N6.C2.D1.R1.S08: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N0.C2.D1.R1.S06: PI = 039, PtrOffset = 005
N2.C3.D1.R1.S00: Preamble found at Latency = 008
N4.C3.D1.R0.S05: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N6.C2.D1.R1.S00: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N0.C2.D1.R1.S07: PI = 057, PtrOffset = 005
N2.C3.D1.R1.S01: Preamble found at Latency = 008
N4.C3.D1.R0.S06: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N6.C2.D1.R1.S01: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N0.C2.D1.R1.S08: PI = 042, PtrOffset = 004
N2.C3.D1.R1.S06: Preamble found at Latency = 008
N4.C3.D1.R0.S07: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N6.C2.D1.R1.S02: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N0.C2.D1.R1.S00: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N2.C3.D1.R1.S07: Preamble found at Latency = 008
N4.C3.D1.R0.S08: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N6.C2.D1.R1.S03: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N0.C2.D1.R1.S01: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N2.C3.D1.R1.S00: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N4.C3.D1.R0.S00: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N6.C2.D1.R1.S04: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N0.C2.D1.R1.S02: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N2.C3.D1.R1.S01: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N4.C3.D1.R0.S01: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N6.C2.D1.R1.S05: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N0.C2.D1.R1.S03: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N2.C3.D1.R1.S02: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N4.C3.D1.R0.S02: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N6.C2.D1.R1.S06: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N0.C2.D1.R1.S04: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N2.C3.D1.R1.S03: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N4.C3.D1.R0.S03: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N6.C2.D1.R1.S07: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N0.C2.D1.R1.S05: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N2.C3.D1.R1.S04: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N4.C3.D1.R0.S04: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N6.C2.D1.R1.S08: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N0.C2.D1.R1.S06: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N2.C3.D1.R1.S05: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N4.C3.D1.R0.S05: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N6.C2.D1.R1.S00: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N0.C2.D1.R1.S07: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N2.C3.D1.R1.S06: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N4.C3.D1.R0.S06: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N6.C2.D1.R1.S01: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N0.C2.D1.R1.S08: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N2.C3.D1.R1.S07: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N4.C3.D1.R0.S07: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N6.C2.D1.R1.S02: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N0.C2.D1.R1.S00: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N2.C3.D1.R1.S08: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N4.C3.D1.R0.S08: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N6.C2.D1.R1.S03: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N0.C2.D1.R1.S01: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N2.C3.D1.R1.S02: Preamble found at Latency = 007
N4.C3.D1.R0.S00: Preamble found at Latency = 008
N6.C2.D1.R1.S04: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N0.C2.D1.R1.S02: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N2.C3.D1.R1.S03: Preamble found at Latency = 007
N4.C3.D1.R0.S01: Preamble found at Latency = 008
N6.C2.D1.R1.S05: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N0.C2.D1.R1.S03: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N2.C3.D1.R1.S04: Preamble found at Latency = 007
N4.C3.D1.R0.S02: Preamble found at Latency = 008
N6.C2.D1.R1.S06: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N0.C2.D1.R1.S04: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N2.C3.D1.R1.S05: Preamble found at Latency = 007
N4.C3.D1.R0.S06: Preamble found at Latency = 008
N6.C2.D1.R1.S07: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N0.C2.D1.R1.S05: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N2.C3.D1.R1.S08: Preamble found at Latency = 007
N4.C3.D1.R0.S07: Preamble found at Latency = 008
N6.C2.D1.R1.S08: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N0.C2.D1.R1.S06: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N2.C3.D1.R1.S00: Total Receive Enable Delay = 1356
N4.C3.D1.R0.S00: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N6.C2.D1.R1.S00: Preamble found at Latency = 008
N0.C2.D1.R1.S07: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N2.C3.D1.R1.S01: Total Receive Enable Delay = 1338
N4.C3.D1.R0.S01: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N6.C2.D1.R1.S07: Preamble found at Latency = 008
N0.C2.D1.R1.S08: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N2.C3.D1.R1.S02: Total Receive Enable Delay = 1306
N4.C3.D1.R0.S02: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N6.C2.D1.R1.S00: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N0.C2.D1.R1.S00: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N2.C3.D1.R1.S03: Total Receive Enable Delay = 1287
N4.C3.D1.R0.S03: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N6.C2.D1.R1.S01: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N0.C2.D1.R1.S01: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N2.C3.D1.R1.S04: Total Receive Enable Delay = 1284
N4.C3.D1.R0.S04: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N6.C2.D1.R1.S02: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N0.C2.D1.R1.S02: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N2.C3.D1.R1.S05: Total Receive Enable Delay = 1308
N4.C3.D1.R0.S05: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N6.C2.D1.R1.S03: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N0.C2.D1.R1.S03: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N2.C3.D1.R1.S06: Total Receive Enable Delay = 1331
N4.C3.D1.R0.S06: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N6.C2.D1.R1.S04: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N0.C2.D1.R1.S04: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N2.C3.D1.R1.S07: Total Receive Enable Delay = 1354
N4.C3.D1.R0.S07: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N6.C2.D1.R1.S05: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N0.C2.D1.R1.S05: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N2.C3.D1.R1.S08: Total Receive Enable Delay = 1268
N4.C3.D1.R0.S08: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N6.C2.D1.R1.S06: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N0.C2.D1.R1.S06: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N2.C3.D1.R1: Starting preamble search upper nibbles
N4.C3.D1.R0.S03: Preamble found at Latency = 007
N6.C2.D1.R1.S07: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N0.C2.D1.R1.S07: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N2.C3.D1.R1.S09: PI = 046, PtrOffset = 004
N4.C3.D1.R0.S04: Preamble found at Latency = 007
N6.C2.D1.R1.S08: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N0.C2.D1.R1.S08: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N2.C3.D1.R1.S10: PI = 027, PtrOffset = 004
N4.C3.D1.R0.S05: Preamble found at Latency = 007
N6.C2.D1.R1.S01: Preamble found at Latency = 007
N0.C2.D1.R1.S00: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N2.C3.D1.R1.S11: PI = 059, PtrOffset = 005
N4.C3.D1.R0.S08: Preamble found at Latency = 007
N6.C2.D1.R1.S02: Preamble found at Latency = 007
N0.C2.D1.R1.S01: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N2.C3.D1.R1.S12: PI = 042, PtrOffset = 005
N4.C3.D1.R0.S00: Total Receive Enable Delay = 1359
N6.C2.D1.R1.S03: Preamble found at Latency = 007
N0.C2.D1.R1.S02: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N2.C3.D1.R1.S13: PI = 036, PtrOffset = 005
N4.C3.D1.R0.S01: Total Receive Enable Delay = 1341
N6.C2.D1.R1.S04: Preamble found at Latency = 007
N0.C2.D1.R1.S03: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N2.C3.D1.R1.S14: PI = 059, PtrOffset = 005
N4.C3.D1.R0.S02: Total Receive Enable Delay = 1312
N6.C2.D1.R1.S05: Preamble found at Latency = 007
N0.C2.D1.R1.S04: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N2.C3.D1.R1.S15: PI = 021, PtrOffset = 004
N4.C3.D1.R0.S03: Total Receive Enable Delay = 1290
N6.C2.D1.R1.S06: Preamble found at Latency = 007
N0.C2.D1.R1.S05: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N2.C3.D1.R1.S16: PI = 041, PtrOffset = 004
N4.C3.D1.R0.S04: Total Receive Enable Delay = 1284
N6.C2.D1.R1.S08: Preamble found at Latency = 007
N0.C2.D1.R1.S06: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N2.C3.D1.R1.S17: PI = 020, PtrOffset = 005
N4.C3.D1.R0.S05: Total Receive Enable Delay = 1309
N6.C2.D1.R1.S00: Total Receive Enable Delay = 1322
N0.C2.D1.R1.S07: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N2.C3.D1.R1.S09: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N4.C3.D1.R0.S06: Total Receive Enable Delay = 1333
N6.C2.D1.R1.S01: Total Receive Enable Delay = 1297
N0.C2.D1.R1.S08: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N2.C3.D1.R1.S10: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N4.C3.D1.R0.S07: Total Receive Enable Delay = 1355
N6.C2.D1.R1.S02: Total Receive Enable Delay = 1267
N0.C2.D1.R1.S00: Preamble found at Latency = 007
N2.C3.D1.R1.S11: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N4.C3.D1.R0.S08: Total Receive Enable Delay = 1272
N6.C2.D1.R1.S03: Total Receive Enable Delay = 1249
N0.C2.D1.R1.S01: Preamble found at Latency = 007
N2.C3.D1.R1.S12: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N4.C3.D1.R0: Starting preamble search upper nibbles
N6.C2.D1.R1.S04: Total Receive Enable Delay = 1247
N0.C2.D1.R1.S02: Preamble found at Latency = 007
N2.C3.D1.R1.S13: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N4.C3.D1.R0.S09: PI = 049, PtrOffset = 004
N6.C2.D1.R1.S05: Total Receive Enable Delay = 1262
N0.C2.D1.R1.S03: Preamble found at Latency = 007
N2.C3.D1.R1.S14: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N4.C3.D1.R0.S10: PI = 027, PtrOffset = 004
N6.C2.D1.R1.S06: Total Receive Enable Delay = 1301
N0.C2.D1.R1.S04: Preamble found at Latency = 007
N2.C3.D1.R1.S15: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N4.C3.D1.R0.S11: PI = 063, PtrOffset = 005
N6.C2.D1.R1.S07: Total Receive Enable Delay = 1316
N0.C2.D1.R1.S05: Preamble found at Latency = 007
N2.C3.D1.R1.S16: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N4.C3.D1.R0.S12: PI = 044, PtrOffset = 005
N6.C2.D1.R1.S08: Total Receive Enable Delay = 1234
N0.C2.D1.R1.S06: Preamble found at Latency = 007
N2.C3.D1.R1.S17: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N4.C3.D1.R0.S13: PI = 037, PtrOffset = 005
N6.C2.D1.R1: Starting preamble search upper nibbles
N0.C2.D1.R1.S07: Preamble found at Latency = 007
N2.C3.D1.R1.S09: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N4.C3.D1.R0.S14: PI = 062, PtrOffset = 005
N6.C2.D1.R1.S09: PI = 008, PtrOffset = 004
N0.C2.D1.R1.S08: Preamble found at Latency = 007
N2.C3.D1.R1.S10: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N4.C3.D1.R0.S15: PI = 020, PtrOffset = 004
N6.C2.D1.R1.S10: PI = 053, PtrOffset = 005
N0.C2.D1.R1.S00: Total Receive Enable Delay = 1311
N2.C3.D1.R1.S11: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N4.C3.D1.R0.S16: PI = 042, PtrOffset = 004
N6.C2.D1.R1.S11: PI = 019, PtrOffset = 005
N0.C2.D1.R1.S01: Total Receive Enable Delay = 1288
N2.C3.D1.R1.S12: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N4.C3.D1.R0.S17: PI = 022, PtrOffset = 005
N6.C2.D1.R1.S12: PI = 001, PtrOffset = 005
N0.C2.D1.R1.S02: Total Receive Enable Delay = 1255
N2.C3.D1.R1.S13: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N4.C3.D1.R0.S09: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N6.C2.D1.R1.S13: PI = 062, PtrOffset = 004
N0.C2.D1.R1.S03: Total Receive Enable Delay = 1234
N2.C3.D1.R1.S14: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N4.C3.D1.R0.S10: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N6.C2.D1.R1.S14: PI = 012, PtrOffset = 005
N0.C2.D1.R1.S04: Total Receive Enable Delay = 1236
N2.C3.D1.R1.S15: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N4.C3.D1.R0.S11: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N6.C2.D1.R1.S15: PI = 050, PtrOffset = 005
N0.C2.D1.R1.S05: Total Receive Enable Delay = 1250
N2.C3.D1.R1.S16: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N4.C3.D1.R0.S12: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N6.C2.D1.R1.S16: PI = 003, PtrOffset = 004
N0.C2.D1.R1.S06: Total Receive Enable Delay = 1287
N2.C3.D1.R1.S17: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N4.C3.D1.R0.S13: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N6.C2.D1.R1.S17: PI = 053, PtrOffset = 004
N0.C2.D1.R1.S07: Total Receive Enable Delay = 1305
N2.C3.D1.R1.S09: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N4.C3.D1.R0.S14: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N6.C2.D1.R1.S09: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N0.C2.D1.R1.S08: Total Receive Enable Delay = 1226
N2.C3.D1.R1.S10: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N4.C3.D1.R0.S15: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N6.C2.D1.R1.S10: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N0.C2.D1.R1: Starting preamble search upper nibbles
N2.C3.D1.R1.S11: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N4.C3.D1.R0.S16: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N6.C2.D1.R1.S11: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N0.C2.D1.R1.S09: PI = 001, PtrOffset = 004
N2.C3.D1.R1.S12: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N4.C3.D1.R0.S17: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N6.C2.D1.R1.S12: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N0.C2.D1.R1.S10: PI = 039, PtrOffset = 005
N2.C3.D1.R1.S13: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N4.C3.D1.R0.S09: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N6.C2.D1.R1.S13: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N0.C2.D1.R1.S11: PI = 007, PtrOffset = 005
N2.C3.D1.R1.S14: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N4.C3.D1.R0.S10: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N6.C2.D1.R1.S14: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N0.C2.D1.R1.S12: PI = 050, PtrOffset = 004
N2.C3.D1.R1.S15: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N4.C3.D1.R0.S11: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N6.C2.D1.R1.S15: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N0.C2.D1.R1.S13: PI = 054, PtrOffset = 004
N2.C3.D1.R1.S16: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N4.C3.D1.R0.S12: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N6.C2.D1.R1.S16: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N0.C2.D1.R1.S14: PI = 001, PtrOffset = 005
N2.C3.D1.R1.S17: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N4.C3.D1.R0.S13: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N6.C2.D1.R1.S17: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N0.C2.D1.R1.S15: PI = 039, PtrOffset = 005
N2.C3.D1.R1.S09: Preamble found at Latency = 008
N4.C3.D1.R0.S14: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N6.C2.D1.R1.S09: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N0.C2.D1.R1.S16: PI = 056, PtrOffset = 005
N2.C3.D1.R1.S10: Preamble found at Latency = 008
N4.C3.D1.R0.S15: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N6.C2.D1.R1.S10: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N0.C2.D1.R1.S17: PI = 039, PtrOffset = 004
N2.C3.D1.R1.S15: Preamble found at Latency = 008
N4.C3.D1.R0.S16: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N6.C2.D1.R1.S11: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N0.C2.D1.R1.S09: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N2.C3.D1.R1.S16: Preamble found at Latency = 008
N4.C3.D1.R0.S17: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N6.C2.D1.R1.S12: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N0.C2.D1.R1.S10: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N2.C3.D1.R1.S09: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N4.C3.D1.R0.S09: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N6.C2.D1.R1.S13: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N0.C2.D1.R1.S11: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N2.C3.D1.R1.S10: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N4.C3.D1.R0.S10: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N6.C2.D1.R1.S14: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N0.C2.D1.R1.S12: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N2.C3.D1.R1.S11: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N4.C3.D1.R0.S11: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N6.C2.D1.R1.S15: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N0.C2.D1.R1.S13: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N2.C3.D1.R1.S12: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N4.C3.D1.R0.S12: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N6.C2.D1.R1.S16: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N0.C2.D1.R1.S14: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N2.C3.D1.R1.S13: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N4.C3.D1.R0.S13: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N6.C2.D1.R1.S17: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N0.C2.D1.R1.S15: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N2.C3.D1.R1.S14: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N4.C3.D1.R0.S14: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N6.C2.D1.R1.S09: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N0.C2.D1.R1.S16: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N2.C3.D1.R1.S15: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N4.C3.D1.R0.S15: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N6.C2.D1.R1.S10: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N0.C2.D1.R1.S17: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N2.C3.D1.R1.S16: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N4.C3.D1.R0.S16: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N6.C2.D1.R1.S11: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N0.C2.D1.R1.S09: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N2.C3.D1.R1.S17: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N4.C3.D1.R0.S17: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N6.C2.D1.R1.S12: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N0.C2.D1.R1.S10: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N2.C3.D1.R1.S11: Preamble found at Latency = 007
N4.C3.D1.R0.S09: Preamble found at Latency = 008
N6.C2.D1.R1.S13: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N0.C2.D1.R1.S11: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N2.C3.D1.R1.S12: Preamble found at Latency = 007
N4.C3.D1.R0.S10: Preamble found at Latency = 008
N6.C2.D1.R1.S14: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N0.C2.D1.R1.S12: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N2.C3.D1.R1.S13: Preamble found at Latency = 007
N4.C3.D1.R0.S15: Preamble found at Latency = 008
N6.C2.D1.R1.S15: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N0.C2.D1.R1.S13: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N2.C3.D1.R1.S14: Preamble found at Latency = 007
N4.C3.D1.R0.S16: Preamble found at Latency = 008
N6.C2.D1.R1.S16: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N0.C2.D1.R1.S14: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N2.C3.D1.R1.S17: Preamble found at Latency = 007
N4.C3.D1.R0.S09: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N6.C2.D1.R1.S17: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N0.C2.D1.R1.S15: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N2.C3.D1.R1: Preamble found for all upper nibbles, adjusting Pi, Offset to center into preamble
N4.C3.D1.R0.S10: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N6.C2.D1.R1.S09: Preamble found at Latency = 008
N0.C2.D1.R1.S16: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N2.C3.D1.R1.S09: Total Receive Enable Delay = 1358
N4.C3.D1.R0.S11: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N6.C2.D1.R1.S16: Preamble found at Latency = 008
N0.C2.D1.R1.S17: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N2.C3.D1.R1.S10: Total Receive Enable Delay = 1339
N4.C3.D1.R0.S12: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N6.C2.D1.R1.S09: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N0.C2.D1.R1.S09: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N2.C3.D1.R1.S11: Total Receive Enable Delay = 1307
N4.C3.D1.R0.S13: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N6.C2.D1.R1.S10: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N0.C2.D1.R1.S10: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N2.C3.D1.R1.S12: Total Receive Enable Delay = 1290
N4.C3.D1.R0.S14: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N6.C2.D1.R1.S11: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N0.C2.D1.R1.S11: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N2.C3.D1.R1.S13: Total Receive Enable Delay = 1284
N4.C3.D1.R0.S15: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N6.C2.D1.R1.S12: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N0.C2.D1.R1.S12: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N2.C3.D1.R1.S14: Total Receive Enable Delay = 1307
N4.C3.D1.R0.S16: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N6.C2.D1.R1.S13: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N0.C2.D1.R1.S13: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N2.C3.D1.R1.S15: Total Receive Enable Delay = 1333
N4.C3.D1.R0.S17: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N6.C2.D1.R1.S14: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N0.C2.D1.R1.S14: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N2.C3.D1.R1.S16: Total Receive Enable Delay = 1353
N4.C3.D1.R0.S11: Preamble found at Latency = 007
N6.C2.D1.R1.S15: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N0.C2.D1.R1.S15: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N2.C3.D1.R1.S17: Total Receive Enable Delay = 1268
N4.C3.D1.R0.S12: Preamble found at Latency = 007
N6.C2.D1.R1.S16: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N0.C2.D1.R1.S16: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
START_DATA_REC_EN
N4.C3.D1.R0.S13: Preamble found at Latency = 007
N6.C2.D1.R1.S17: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N0.C2.D1.R1.S17: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N2.C3.S00: RdCmd2RcvEnLatency = 9, RdPtrOffsetRcvEn = 5
N4.C3.D1.R0.S14: Preamble found at Latency = 007
N6.C2.D1.R1.S10: Preamble found at Latency = 007
N0.C2.D1.R1.S09: Preamble found at Latency = 008
N2.C3.S01: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N4.C3.D1.R0.S17: Preamble found at Latency = 007
N6.C2.D1.R1.S11: Preamble found at Latency = 007
N0.C2.D1.R1.S09: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N2.C3.S02: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N4.C3.D1.R0: Preamble found for all upper nibbles, adjusting Pi, Offset to center into preamble
N6.C2.D1.R1.S12: Preamble found at Latency = 007
N0.C2.D1.R1.S10: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N2.C3.S03: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N4.C3.D1.R0.S09: Total Receive Enable Delay = 1361
N6.C2.D1.R1.S13: Preamble found at Latency = 007
N0.C2.D1.R1.S11: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N2.C3.S04: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N4.C3.D1.R0.S10: Total Receive Enable Delay = 1339
N6.C2.D1.R1.S14: Preamble found at Latency = 007
N0.C2.D1.R1.S12: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N2.C3.S05: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N4.C3.D1.R0.S11: Total Receive Enable Delay = 1311
N6.C2.D1.R1.S15: Preamble found at Latency = 007
N0.C2.D1.R1.S13: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N2.C3.S06: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N4.C3.D1.R0.S12: Total Receive Enable Delay = 1292
N6.C2.D1.R1.S17: Preamble found at Latency = 007
N0.C2.D1.R1.S14: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N2.C3.S07: RdCmd2RcvEnLatency = 9, RdPtrOffsetRcvEn = 5
N4.C3.D1.R0.S13: Total Receive Enable Delay = 1285
N6.C2.D1.R1: Preamble found for all upper nibbles, adjusting Pi, Offset to center into preamble
N0.C2.D1.R1.S15: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N2.C3.S08: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 5
N4.C3.D1.R0.S14: Total Receive Enable Delay = 1310
N6.C2.D1.R1.S09: Total Receive Enable Delay = 1320
N0.C2.D1.R1.S16: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N2.C3.S09: RdCmd2RcvEnLatency = 9, RdPtrOffsetRcvEn = 5
N4.C3.D1.R0.S15: Total Receive Enable Delay = 1332
N6.C2.D1.R1.S10: Total Receive Enable Delay = 1301
N0.C2.D1.R1.S17: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N2.C3.S10: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N4.C3.D1.R0.S16: Total Receive Enable Delay = 1354
N6.C2.D1.R1.S11: Total Receive Enable Delay = 1267
N0.C2.D1.R1.S10: Preamble found at Latency = 007
N2.C3.S11: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N4.C3.D1.R0.S17: Total Receive Enable Delay = 1270
N6.C2.D1.R1.S12: Total Receive Enable Delay = 1249
N0.C2.D1.R1.S11: Preamble found at Latency = 007
N2.C3.S12: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N4.C3.D1.R1: RcvEnFine: Initial RdCmd2RcvEnLatency = 10, Initial RdPtrOffsetRcvEn = 4
N6.C2.D1.R1.S13: Total Receive Enable Delay = 1246
N0.C2.D1.R1.S12: Preamble found at Latency = 007
N2.C3.S13: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N4.C3.D1.R1.S00: Rcv En Fine Value = 304
N6.C2.D1.R1.S14: Total Receive Enable Delay = 1260
N0.C2.D1.R1.S13: Preamble found at Latency = 007
N2.C3.S14: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N4.C3.D1.R1.S01: Rcv En Fine Value = 283
N6.C2.D1.R1.S15: Total Receive Enable Delay = 1298
N0.C2.D1.R1.S14: Preamble found at Latency = 007
N2.C3.S15: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N4.C3.D1.R1.S02: Rcv En Fine Value = 379
N6.C2.D1.R1.S16: Total Receive Enable Delay = 1315
N0.C2.D1.R1.S15: Preamble found at Latency = 007
N2.C3.S16: RdCmd2RcvEnLatency = 9, RdPtrOffsetRcvEn = 5
N4.C3.D1.R1.S03: Rcv En Fine Value = 363
N6.C2.D1.R1.S17: Total Receive Enable Delay = 1237
N0.C2.D1.R1.S16: Preamble found at Latency = 007
N2.C3.S17: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 5
N4.C3.D1.R1.S04: Rcv En Fine Value = 357
START_DATA_REC_EN
N0.C2.D1.R1.S17: Preamble found at Latency = 007
N2.C3.D0.R0.S00: RcvEn: plus1 = 1, minus1 = 0, PI = 27, DB = 0
N4.C3.D1.R1.S05: Rcv En Fine Value = 378
N6.C2.S00: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N0.C2.D1.R1: Preamble found for all upper nibbles, adjusting Pi, Offset to center into preamble
N2.C3.D0.R0.S01: RcvEn: plus1 = 0, minus1 = 1, PI = 07, DB = 1
N4.C3.D1.R1.S06: Rcv En Fine Value = 277
N6.C2.S01: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N0.C2.D1.R1.S09: Total Receive Enable Delay = 1313
N2.C3.D0.R0.S02: RcvEn: plus1 = 1, minus1 = 0, PI = 41, DB = 0
N4.C3.D1.R1.S07: Rcv En Fine Value = 297
N6.C2.S02: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 5
N0.C2.D1.R1.S10: Total Receive Enable Delay = 1287
N2.C3.D0.R0.S03: RcvEn: plus1 = 1, minus1 = 0, PI = 22, DB = 0
N4.C3.D1.R1.S08: Rcv En Fine Value = 341
N6.C2.S03: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 5
N0.C2.D1.R1.S11: Total Receive Enable Delay = 1255
N2.C3.D0.R0.S04: RcvEn: plus1 = 1, minus1 = 0, PI = 17, DB = 0
N4.C3.D1.R1.S09: Rcv En Fine Value = 305
N6.C2.S04: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 5
N0.C2.D1.R1.S12: Total Receive Enable Delay = 1234
N2.C3.D0.R0.S05: RcvEn: plus1 = 1, minus1 = 0, PI = 41, DB = 0
N4.C3.D1.R1.S10: Rcv En Fine Value = 283
N6.C2.S05: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 5
N0.C2.D1.R1.S13: Total Receive Enable Delay = 1238
N2.C3.D0.R0.S06: RcvEn: plus1 = 0, minus1 = 1, PI = 00, DB = 1
N4.C3.D1.R1.S11: Rcv En Fine Value = 258
N6.C2.S06: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N0.C2.D1.R1.S14: Total Receive Enable Delay = 1249
N2.C3.D0.R0.S07: RcvEn: plus1 = 1, minus1 = 0, PI = 23, DB = 0
N4.C3.D1.R1.S12: Rcv En Fine Value = 366
N6.C2.S07: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N0.C2.D1.R1.S15: Total Receive Enable Delay = 1287
N2.C3.D0.R0.S08: RcvEn: plus1 = 0, minus1 = 1, PI = 02, DB = 1
N4.C3.D1.R1.S13: Rcv En Fine Value = 356
N6.C2.S08: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 5
N0.C2.D1.R1.S16: Total Receive Enable Delay = 1304
N2.C3.D0.R0.S09: RcvEn: plus1 = 1, minus1 = 0, PI = 29, DB = 0
N4.C3.D1.R1.S14: Rcv En Fine Value = 380
N6.C2.S09: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N0.C2.D1.R1.S17: Total Receive Enable Delay = 1223
N2.C3.D0.R0.S10: RcvEn: plus1 = 0, minus1 = 1, PI = 08, DB = 1
N4.C3.D1.R1.S15: Rcv En Fine Value = 277
N6.C2.S10: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
START_DATA_REC_EN
N2.C3.D0.R0.S11: RcvEn: plus1 = 1, minus1 = 0, PI = 41, DB = 0
N4.C3.D1.R1.S16: Rcv En Fine Value = 299
N6.C2.S11: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 5
N0.C2.S00: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N2.C3.D0.R0.S12: RcvEn: plus1 = 1, minus1 = 0, PI = 24, DB = 0
N4.C3.D1.R1.S17: Rcv En Fine Value = 342
N6.C2.S12: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 5
N0.C2.S01: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N2.C3.D0.R0.S13: RcvEn: plus1 = 1, minus1 = 0, PI = 19, DB = 0
N4.C3.D1.R1: Starting preamble search lower nibbles
N6.C2.S13: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 5
N0.C2.S02: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 5
N2.C3.D0.R0.S14: RcvEn: plus1 = 1, minus1 = 0, PI = 42, DB = 0
N4.C3.D1.R1.S00: PI = 048, PtrOffset = 004
N6.C2.S14: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 5
N0.C2.S03: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 5
N2.C3.D0.R0.S15: RcvEn: plus1 = 0, minus1 = 1, PI = 02, DB = 1
N4.C3.D1.R1.S01: PI = 027, PtrOffset = 004
N6.C2.S15: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N0.C2.S04: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 5
N2.C3.D0.R0.S16: RcvEn: plus1 = 1, minus1 = 0, PI = 25, DB = 0
N4.C3.D1.R1.S02: PI = 059, PtrOffset = 005
N6.C2.S16: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N0.C2.S05: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 5
N2.C3.D0.R0.S17: RcvEn: plus1 = 0, minus1 = 1, PI = 04, DB = 1
N4.C3.D1.R1.S03: PI = 043, PtrOffset = 005
N6.C2.S17: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 5
N0.C2.S06: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N2.C3.D0.R1.S00: RcvEn: plus1 = 1, minus1 = 0, PI = 27, DB = 0
N4.C3.D1.R1.S04: PI = 037, PtrOffset = 005
N6.C2.D0.R0.S00: RcvEn: plus1 = 1, minus1 = 0, PI = 52, DB = 1
N0.C2.S07: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N2.C3.D0.R1.S01: RcvEn: plus1 = 0, minus1 = 1, PI = 07, DB = 1
N4.C3.D1.R1.S05: PI = 058, PtrOffset = 005
N6.C2.D0.R0.S01: RcvEn: plus1 = 1, minus1 = 0, PI = 29, DB = 0
N0.C2.S08: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 5
N2.C3.D0.R1.S02: RcvEn: plus1 = 1, minus1 = 0, PI = 41, DB = 0
N4.C3.D1.R1.S06: PI = 021, PtrOffset = 004
N6.C2.D0.R0.S02: RcvEn: plus1 = 0, minus1 = 1, PI = 00, DB = 1
N0.C2.S09: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N2.C3.D0.R1.S03: RcvEn: plus1 = 1, minus1 = 0, PI = 22, DB = 0
N4.C3.D1.R1.S07: PI = 041, PtrOffset = 004
N6.C2.D0.R0.S03: RcvEn: plus1 = 1, minus1 = 0, PI = 44, DB = 0
N0.C2.S10: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N2.C3.D0.R1.S04: RcvEn: plus1 = 1, minus1 = 0, PI = 17, DB = 0
N4.C3.D1.R1.S08: PI = 021, PtrOffset = 005
N6.C2.D0.R0.S04: RcvEn: plus1 = 1, minus1 = 0, PI = 43, DB = 0
N0.C2.S11: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 5
N2.C3.D0.R1.S05: RcvEn: plus1 = 1, minus1 = 0, PI = 41, DB = 0
N4.C3.D1.R1.S00: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N6.C2.D0.R0.S05: RcvEn: plus1 = 1, minus1 = 0, PI = 57, DB = 1
N0.C2.S12: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 5
N2.C3.D0.R1.S06: RcvEn: plus1 = 0, minus1 = 1, PI = 00, DB = 1
N4.C3.D1.R1.S01: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N6.C2.D0.R0.S06: RcvEn: plus1 = 1, minus1 = 0, PI = 31, DB = 0
N0.C2.S13: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 5
N2.C3.D0.R1.S07: RcvEn: plus1 = 1, minus1 = 0, PI = 23, DB = 0
N4.C3.D1.R1.S02: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N6.C2.D0.R0.S07: RcvEn: plus1 = 1, minus1 = 0, PI = 48, DB = 0
N0.C2.S14: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 5
N2.C3.D0.R1.S08: RcvEn: plus1 = 0, minus1 = 1, PI = 02, DB = 1
N4.C3.D1.R1.S03: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N6.C2.D0.R0.S08: RcvEn: plus1 = 1, minus1 = 0, PI = 29, DB = 0
N0.C2.S15: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N2.C3.D0.R1.S09: RcvEn: plus1 = 1, minus1 = 0, PI = 29, DB = 0
N4.C3.D1.R1.S04: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N6.C2.D0.R0.S09: RcvEn: plus1 = 1, minus1 = 0, PI = 50, DB = 1
N0.C2.S16: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N2.C3.D0.R1.S10: RcvEn: plus1 = 0, minus1 = 1, PI = 08, DB = 1
N4.C3.D1.R1.S05: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N6.C2.D0.R0.S10: RcvEn: plus1 = 1, minus1 = 0, PI = 31, DB = 0
N0.C2.S17: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 5
N2.C3.D0.R1.S11: RcvEn: plus1 = 1, minus1 = 0, PI = 41, DB = 0
N4.C3.D1.R1.S06: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N6.C2.D0.R0.S11: RcvEn: plus1 = 1, minus1 = 0, PI = 61, DB = 1
N0.C2.D0.R0.S00: RcvEn: plus1 = 1, minus1 = 0, PI = 51, DB = 1
N2.C3.D0.R1.S12: RcvEn: plus1 = 1, minus1 = 0, PI = 24, DB = 0
N4.C3.D1.R1.S07: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N6.C2.D0.R0.S12: RcvEn: plus1 = 1, minus1 = 0, PI = 45, DB = 0
N0.C2.D0.R0.S01: RcvEn: plus1 = 1, minus1 = 0, PI = 30, DB = 0
N2.C3.D0.R1.S13: RcvEn: plus1 = 1, minus1 = 0, PI = 19, DB = 0
N4.C3.D1.R1.S08: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N6.C2.D0.R0.S13: RcvEn: plus1 = 1, minus1 = 0, PI = 44, DB = 0
N0.C2.D0.R0.S02: RcvEn: plus1 = 1, minus1 = 0, PI = 60, DB = 1
N2.C3.D0.R1.S14: RcvEn: plus1 = 1, minus1 = 0, PI = 42, DB = 0
N4.C3.D1.R1.S00: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N6.C2.D0.R0.S14: RcvEn: plus1 = 1, minus1 = 0, PI = 55, DB = 1
N0.C2.D0.R0.S03: RcvEn: plus1 = 1, minus1 = 0, PI = 38, DB = 0
N2.C3.D0.R1.S15: RcvEn: plus1 = 0, minus1 = 1, PI = 02, DB = 1
N4.C3.D1.R1.S01: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N6.C2.D0.R0.S15: RcvEn: plus1 = 1, minus1 = 0, PI = 31, DB = 0
N0.C2.D0.R0.S04: RcvEn: plus1 = 1, minus1 = 0, PI = 42, DB = 0
N2.C3.D0.R1.S16: RcvEn: plus1 = 1, minus1 = 0, PI = 25, DB = 0
N4.C3.D1.R1.S02: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N6.C2.D0.R0.S16: RcvEn: plus1 = 1, minus1 = 0, PI = 46, DB = 0
N0.C2.D0.R0.S05: RcvEn: plus1 = 1, minus1 = 0, PI = 52, DB = 1
N2.C3.D0.R1.S17: RcvEn: plus1 = 0, minus1 = 1, PI = 04, DB = 1
N4.C3.D1.R1.S03: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N6.C2.D0.R0.S17: RcvEn: plus1 = 1, minus1 = 0, PI = 33, DB = 0
N0.C2.D0.R0.S06: RcvEn: plus1 = 1, minus1 = 0, PI = 28, DB = 0
N2.C3.D1.R0.S00: RcvEn: plus1 = 1, minus1 = 0, PI = 13, DB = 1
N4.C3.D1.R1.S04: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N6.C2.D0.R1.S00: RcvEn: plus1 = 1, minus1 = 0, PI = 52, DB = 1
N0.C2.D0.R0.S07: RcvEn: plus1 = 1, minus1 = 0, PI = 44, DB = 0
N2.C3.D1.R0.S01: RcvEn: plus1 = 1, minus1 = 0, PI = 58, DB = 1
N4.C3.D1.R1.S05: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N6.C2.D0.R1.S01: RcvEn: plus1 = 1, minus1 = 0, PI = 29, DB = 0
N0.C2.D0.R0.S08: RcvEn: plus1 = 1, minus1 = 0, PI = 30, DB = 0
N2.C3.D1.R0.S02: RcvEn: plus1 = 1, minus1 = 0, PI = 26, DB = 0
N4.C3.D1.R1.S06: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N6.C2.D0.R1.S02: RcvEn: plus1 = 0, minus1 = 1, PI = 00, DB = 1
N0.C2.D0.R0.S09: RcvEn: plus1 = 1, minus1 = 0, PI = 50, DB = 1
N2.C3.D1.R0.S03: RcvEn: plus1 = 1, minus1 = 0, PI = 08, DB = 1
N4.C3.D1.R1.S07: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N6.C2.D0.R1.S03: RcvEn: plus1 = 1, minus1 = 0, PI = 44, DB = 0
N0.C2.D0.R0.S10: RcvEn: plus1 = 1, minus1 = 0, PI = 28, DB = 0
N2.C3.D1.R0.S04: RcvEn: plus1 = 1, minus1 = 0, PI = 03, DB = 1
N4.C3.D1.R1.S08: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N6.C2.D0.R1.S04: RcvEn: plus1 = 1, minus1 = 0, PI = 43, DB = 0
N0.C2.D0.R0.S11: RcvEn: plus1 = 1, minus1 = 0, PI = 59, DB = 1
N2.C3.D1.R0.S05: RcvEn: plus1 = 1, minus1 = 0, PI = 28, DB = 0
N4.C3.D1.R1.S00: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N6.C2.D0.R1.S05: RcvEn: plus1 = 1, minus1 = 0, PI = 57, DB = 1
N0.C2.D0.R0.S12: RcvEn: plus1 = 1, minus1 = 0, PI = 39, DB = 0
N2.C3.D1.R0.S06: RcvEn: plus1 = 1, minus1 = 0, PI = 51, DB = 1
N4.C3.D1.R1.S01: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N6.C2.D0.R1.S06: RcvEn: plus1 = 1, minus1 = 0, PI = 31, DB = 0
N0.C2.D0.R0.S13: RcvEn: plus1 = 1, minus1 = 0, PI = 42, DB = 0
N2.C3.D1.R0.S07: RcvEn: plus1 = 1, minus1 = 0, PI = 10, DB = 1
N4.C3.D1.R1.S02: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N6.C2.D0.R1.S07: RcvEn: plus1 = 1, minus1 = 0, PI = 48, DB = 0
N0.C2.D0.R0.S14: RcvEn: plus1 = 1, minus1 = 0, PI = 52, DB = 1
N2.C3.D1.R0.S08: RcvEn: plus1 = 1, minus1 = 0, PI = 52, DB = 1
N4.C3.D1.R1.S03: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N6.C2.D0.R1.S08: RcvEn: plus1 = 1, minus1 = 0, PI = 29, DB = 0
N0.C2.D0.R0.S15: RcvEn: plus1 = 1, minus1 = 0, PI = 27, DB = 0
N2.C3.D1.R0.S09: RcvEn: plus1 = 1, minus1 = 0, PI = 14, DB = 1
N4.C3.D1.R1.S04: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N6.C2.D0.R1.S09: RcvEn: plus1 = 1, minus1 = 0, PI = 50, DB = 1
N0.C2.D0.R0.S16: RcvEn: plus1 = 1, minus1 = 0, PI = 43, DB = 0
N2.C3.D1.R0.S10: RcvEn: plus1 = 1, minus1 = 0, PI = 59, DB = 1
N4.C3.D1.R1.S05: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N6.C2.D0.R1.S10: RcvEn: plus1 = 1, minus1 = 0, PI = 31, DB = 0
N0.C2.D0.R0.S17: RcvEn: plus1 = 1, minus1 = 0, PI = 24, DB = 0
N2.C3.D1.R0.S11: RcvEn: plus1 = 1, minus1 = 0, PI = 28, DB = 0
N4.C3.D1.R1.S06: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N6.C2.D0.R1.S11: RcvEn: plus1 = 1, minus1 = 0, PI = 61, DB = 1
N0.C2.D0.R1.S00: RcvEn: plus1 = 1, minus1 = 0, PI = 51, DB = 1
N2.C3.D1.R0.S12: RcvEn: plus1 = 1, minus1 = 0, PI = 10, DB = 1
N4.C3.D1.R1.S07: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N6.C2.D0.R1.S12: RcvEn: plus1 = 1, minus1 = 0, PI = 45, DB = 0
N0.C2.D0.R1.S01: RcvEn: plus1 = 1, minus1 = 0, PI = 30, DB = 0
N2.C3.D1.R0.S13: RcvEn: plus1 = 1, minus1 = 0, PI = 04, DB = 1
N4.C3.D1.R1.S08: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N6.C2.D0.R1.S13: RcvEn: plus1 = 1, minus1 = 0, PI = 44, DB = 0
N0.C2.D0.R1.S02: RcvEn: plus1 = 1, minus1 = 0, PI = 60, DB = 1
N2.C3.D1.R0.S14: RcvEn: plus1 = 1, minus1 = 0, PI = 28, DB = 0
N4.C3.D1.R1.S00: Preamble found at Latency = 008
N6.C2.D0.R1.S14: RcvEn: plus1 = 1, minus1 = 0, PI = 55, DB = 1
N0.C2.D0.R1.S03: RcvEn: plus1 = 1, minus1 = 0, PI = 38, DB = 0
N2.C3.D1.R0.S15: RcvEn: plus1 = 1, minus1 = 0, PI = 53, DB = 1
N4.C3.D1.R1.S01: Preamble found at Latency = 008
N6.C2.D0.R1.S15: RcvEn: plus1 = 1, minus1 = 0, PI = 31, DB = 0
N0.C2.D0.R1.S04: RcvEn: plus1 = 1, minus1 = 0, PI = 42, DB = 0
N2.C3.D1.R0.S16: RcvEn: plus1 = 1, minus1 = 0, PI = 11, DB = 1
N4.C3.D1.R1.S06: Preamble found at Latency = 008
N6.C2.D0.R1.S16: RcvEn: plus1 = 1, minus1 = 0, PI = 46, DB = 0
N0.C2.D0.R1.S05: RcvEn: plus1 = 1, minus1 = 0, PI = 52, DB = 1
N2.C3.D1.R0.S17: RcvEn: plus1 = 1, minus1 = 0, PI = 52, DB = 1
N4.C3.D1.R1.S07: Preamble found at Latency = 008
N6.C2.D0.R1.S17: RcvEn: plus1 = 1, minus1 = 0, PI = 33, DB = 0
N0.C2.D0.R1.S06: RcvEn: plus1 = 1, minus1 = 0, PI = 28, DB = 0
N2.C3.D1.R1.S00: RcvEn: plus1 = 1, minus1 = 0, PI = 13, DB = 1
N4.C3.D1.R1.S00: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N6.C2.D1.R0.S00: RcvEn: plus1 = 1, minus1 = 0, PI = 42, DB = 0
N0.C2.D0.R1.S07: RcvEn: plus1 = 1, minus1 = 0, PI = 44, DB = 0
N2.C3.D1.R1.S01: RcvEn: plus1 = 1, minus1 = 0, PI = 58, DB = 1
N4.C3.D1.R1.S01: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N6.C2.D1.R0.S01: RcvEn: plus1 = 1, minus1 = 0, PI = 17, DB = 0
N0.C2.D0.R1.S08: RcvEn: plus1 = 1, minus1 = 0, PI = 30, DB = 0
N2.C3.D1.R1.S02: RcvEn: plus1 = 1, minus1 = 0, PI = 26, DB = 0
N4.C3.D1.R1.S02: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N6.C2.D1.R0.S02: RcvEn: plus1 = 1, minus1 = 0, PI = 51, DB = 1
N0.C2.D0.R1.S09: RcvEn: plus1 = 1, minus1 = 0, PI = 50, DB = 1
N2.C3.D1.R1.S03: RcvEn: plus1 = 1, minus1 = 0, PI = 08, DB = 1
N4.C3.D1.R1.S03: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N6.C2.D1.R0.S03: RcvEn: plus1 = 1, minus1 = 0, PI = 33, DB = 0
N0.C2.D0.R1.S10: RcvEn: plus1 = 1, minus1 = 0, PI = 28, DB = 0
N2.C3.D1.R1.S04: RcvEn: plus1 = 1, minus1 = 0, PI = 03, DB = 1
N4.C3.D1.R1.S04: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N6.C2.D1.R0.S04: RcvEn: plus1 = 1, minus1 = 0, PI = 32, DB = 0
N0.C2.D0.R1.S11: RcvEn: plus1 = 1, minus1 = 0, PI = 59, DB = 1
N2.C3.D1.R1.S05: RcvEn: plus1 = 1, minus1 = 0, PI = 28, DB = 0
N4.C3.D1.R1.S05: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N6.C2.D1.R0.S05: RcvEn: plus1 = 1, minus1 = 0, PI = 46, DB = 0
N0.C2.D0.R1.S12: RcvEn: plus1 = 1, minus1 = 0, PI = 39, DB = 0
N2.C3.D1.R1.S06: RcvEn: plus1 = 1, minus1 = 0, PI = 51, DB = 1
N4.C3.D1.R1.S06: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N6.C2.D1.R0.S06: RcvEn: plus1 = 1, minus1 = 0, PI = 20, DB = 0
N0.C2.D0.R1.S13: RcvEn: plus1 = 1, minus1 = 0, PI = 42, DB = 0
N2.C3.D1.R1.S07: RcvEn: plus1 = 1, minus1 = 0, PI = 10, DB = 1
N4.C3.D1.R1.S07: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N6.C2.D1.R0.S07: RcvEn: plus1 = 1, minus1 = 0, PI = 36, DB = 0
N0.C2.D0.R1.S14: RcvEn: plus1 = 1, minus1 = 0, PI = 52, DB = 1
N2.C3.D1.R1.S08: RcvEn: plus1 = 1, minus1 = 0, PI = 52, DB = 1
N4.C3.D1.R1.S08: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N6.C2.D1.R0.S08: RcvEn: plus1 = 1, minus1 = 0, PI = 19, DB = 0
N0.C2.D0.R1.S15: RcvEn: plus1 = 1, minus1 = 0, PI = 27, DB = 0
N2.C3.D1.R1.S09: RcvEn: plus1 = 1, minus1 = 0, PI = 14, DB = 1
N4.C3.D1.R1.S02: Preamble found at Latency = 007
N6.C2.D1.R0.S09: RcvEn: plus1 = 1, minus1 = 0, PI = 39, DB = 0
N0.C2.D0.R1.S16: RcvEn: plus1 = 1, minus1 = 0, PI = 43, DB = 0
N2.C3.D1.R1.S10: RcvEn: plus1 = 1, minus1 = 0, PI = 59, DB = 1
N4.C3.D1.R1.S03: Preamble found at Latency = 007
N6.C2.D1.R0.S10: RcvEn: plus1 = 1, minus1 = 0, PI = 20, DB = 0
N0.C2.D0.R1.S17: RcvEn: plus1 = 1, minus1 = 0, PI = 24, DB = 0
N2.C3.D1.R1.S11: RcvEn: plus1 = 1, minus1 = 0, PI = 28, DB = 0
N4.C3.D1.R1.S04: Preamble found at Latency = 007
N6.C2.D1.R0.S11: RcvEn: plus1 = 1, minus1 = 0, PI = 51, DB = 1
N0.C2.D1.R0.S00: RcvEn: plus1 = 1, minus1 = 0, PI = 31, DB = 0
N2.C3.D1.R1.S12: RcvEn: plus1 = 1, minus1 = 0, PI = 10, DB = 1
N4.C3.D1.R1.S05: Preamble found at Latency = 007
N6.C2.D1.R0.S12: RcvEn: plus1 = 1, minus1 = 0, PI = 32, DB = 0
N0.C2.D1.R0.S01: RcvEn: plus1 = 1, minus1 = 0, PI = 07, DB = 1
N2.C3.D1.R1.S13: RcvEn: plus1 = 1, minus1 = 0, PI = 04, DB = 1
N4.C3.D1.R1.S08: Preamble found at Latency = 007
N6.C2.D1.R0.S13: RcvEn: plus1 = 1, minus1 = 0, PI = 31, DB = 0
N0.C2.D1.R0.S02: RcvEn: plus1 = 1, minus1 = 0, PI = 40, DB = 0
N2.C3.D1.R1.S14: RcvEn: plus1 = 1, minus1 = 0, PI = 28, DB = 0
N4.C3.D1.R1.S00: Total Receive Enable Delay = 1360
N6.C2.D1.R0.S14: RcvEn: plus1 = 1, minus1 = 0, PI = 44, DB = 0
N0.C2.D1.R0.S03: RcvEn: plus1 = 1, minus1 = 0, PI = 18, DB = 0
N2.C3.D1.R1.S15: RcvEn: plus1 = 1, minus1 = 0, PI = 53, DB = 1
N4.C3.D1.R1.S01: Total Receive Enable Delay = 1339
N6.C2.D1.R0.S15: RcvEn: plus1 = 1, minus1 = 0, PI = 19, DB = 0
N0.C2.D1.R0.S04: RcvEn: plus1 = 1, minus1 = 0, PI = 22, DB = 0
N2.C3.D1.R1.S16: RcvEn: plus1 = 1, minus1 = 0, PI = 11, DB = 1
N4.C3.D1.R1.S02: Total Receive Enable Delay = 1307
N6.C2.D1.R0.S16: RcvEn: plus1 = 1, minus1 = 0, PI = 36, DB = 0
N0.C2.D1.R0.S05: RcvEn: plus1 = 1, minus1 = 0, PI = 34, DB = 0
N2.C3.D1.R1.S17: RcvEn: plus1 = 1, minus1 = 0, PI = 52, DB = 1
N4.C3.D1.R1.S03: Total Receive Enable Delay = 1291
N6.C2.D1.R0.S17: RcvEn: plus1 = 1, minus1 = 0, PI = 20, DB = 0
N0.C2.D1.R0.S06: RcvEn: plus1 = 1, minus1 = 0, PI = 07, DB = 1
STOP_DATA_REC_EN
N4.C3.D1.R1.S04: Total Receive Enable Delay = 1285
N6.C2.D1.R1.S00: RcvEn: plus1 = 1, minus1 = 0, PI = 42, DB = 0
N0.C2.D1.R0.S07: RcvEn: plus1 = 1, minus1 = 0, PI = 25, DB = 0
N2.C0.D0.R0.S00: StoreJckWorstRank: worst rank = 0, greatestDelay = 1326
N4.C3.D1.R1.S05: Total Receive Enable Delay = 1306
N6.C2.D1.R1.S01: RcvEn: plus1 = 1, minus1 = 0, PI = 17, DB = 0
N0.C2.D1.R0.S08: RcvEn: plus1 = 1, minus1 = 0, PI = 11, DB = 1
N2.C0.D0.R0.S07: StoreJckWorstRank: worst rank = 0, greatestDelay = 1328
N4.C3.D1.R1.S06: Total Receive Enable Delay = 1333
N6.C2.D1.R1.S02: RcvEn: plus1 = 1, minus1 = 0, PI = 51, DB = 1
N0.C2.D1.R0.S09: RcvEn: plus1 = 1, minus1 = 0, PI = 31, DB = 0
N2.C0.D0.R1.S07: StoreJckWorstRank: worst rank = 1, greatestDelay = 1329
N4.C3.D1.R1.S07: Total Receive Enable Delay = 1353
N6.C2.D1.R1.S03: RcvEn: plus1 = 1, minus1 = 0, PI = 33, DB = 0
N0.C2.D1.R0.S10: RcvEn: plus1 = 1, minus1 = 0, PI = 06, DB = 1
N2.C1.D0.R0.S00: StoreJckWorstRank: worst rank = 0, greatestDelay = 1376
N4.C3.D1.R1.S08: Total Receive Enable Delay = 1269
N6.C2.D1.R1.S04: RcvEn: plus1 = 1, minus1 = 0, PI = 32, DB = 0
N0.C2.D1.R0.S11: RcvEn: plus1 = 1, minus1 = 0, PI = 40, DB = 0
N2.C1.D0.R0.S09: StoreJckWorstRank: worst rank = 0, greatestDelay = 1377
N4.C3.D1.R1: Starting preamble search upper nibbles
N6.C2.D1.R1.S05: RcvEn: plus1 = 1, minus1 = 0, PI = 46, DB = 0
N0.C2.D1.R0.S12: RcvEn: plus1 = 1, minus1 = 0, PI = 18, DB = 0
N2.C0: StoreJckWorstRank: final value: worst rank = 0
N4.C3.D1.R1.S09: PI = 049, PtrOffset = 004
N6.C2.D1.R1.S06: RcvEn: plus1 = 1, minus1 = 0, PI = 20, DB = 0
N0.C2.D1.R0.S13: RcvEn: plus1 = 1, minus1 = 0, PI = 23, DB = 0
N2.C2.D0.R0.S00: StoreJckWorstRank: worst rank = 0, greatestDelay = 1329
N4.C3.D1.R1.S10: PI = 027, PtrOffset = 004
N6.C2.D1.R1.S07: RcvEn: plus1 = 1, minus1 = 0, PI = 36, DB = 0
N0.C2.D1.R0.S14: RcvEn: plus1 = 1, minus1 = 0, PI = 34, DB = 0
N2.C2.D0.R0.S09: StoreJckWorstRank: worst rank = 0, greatestDelay = 1331
N4.C3.D1.R1.S11: PI = 002, PtrOffset = 004
N6.C2.D1.R1.S08: RcvEn: plus1 = 1, minus1 = 0, PI = 19, DB = 0
N0.C2.D1.R0.S15: RcvEn: plus1 = 1, minus1 = 0, PI = 07, DB = 1
N2.C3.D0.R0.S00: StoreJckWorstRank: worst rank = 0, greatestDelay = 1372
N4.C3.D1.R1.S12: PI = 046, PtrOffset = 005
N6.C2.D1.R1.S09: RcvEn: plus1 = 1, minus1 = 0, PI = 39, DB = 0
N0.C2.D1.R0.S16: RcvEn: plus1 = 1, minus1 = 0, PI = 23, DB = 0
N2.C3.D0.R0.S09: StoreJckWorstRank: worst rank = 0, greatestDelay = 1374
N4.C3.D1.R1.S13: PI = 036, PtrOffset = 005
N6.C2.D1.R1.S10: RcvEn: plus1 = 1, minus1 = 0, PI = 20, DB = 0
N0.C2.D1.R0.S17: RcvEn: plus1 = 1, minus1 = 0, PI = 07, DB = 1
N2.C1: StoreJckWorstRank: final value: worst rank = 0
N4.C3.D1.R1.S14: PI = 060, PtrOffset = 005
N6.C2.D1.R1.S11: RcvEn: plus1 = 1, minus1 = 0, PI = 51, DB = 1
N0.C2.D1.R1.S00: RcvEn: plus1 = 1, minus1 = 0, PI = 31, DB = 0
N2: RunTrainStep: Final status = 0
N4.C3.D1.R1.S15: PI = 021, PtrOffset = 004
N6.C2.D1.R1.S12: RcvEn: plus1 = 1, minus1 = 0, PI = 32, DB = 0
N0.C2.D1.R1.S01: RcvEn: plus1 = 1, minus1 = 0, PI = 07, DB = 1

END - Basic Receive Enable Training    Time         62988 ms
N4.C3.D1.R1.S16: PI = 043, PtrOffset = 004
N6.C2.D1.R1.S13: RcvEn: plus1 = 1, minus1 = 0, PI = 31, DB = 0
N0.C2.D1.R1.S02: RcvEn: plus1 = 1, minus1 = 0, PI = 40, DB = 0
N2.C0.S00: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  6
N4.C3.D1.R1.S17: PI = 022, PtrOffset = 005
N6.C2.D1.R1.S14: RcvEn: plus1 = 1, minus1 = 0, PI = 44, DB = 0
N0.C2.D1.R1.S03: RcvEn: plus1 = 1, minus1 = 0, PI = 18, DB = 0
N2.C0.S01: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  6
N4.C3.D1.R1.S09: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N6.C2.D1.R1.S15: RcvEn: plus1 = 1, minus1 = 0, PI = 19, DB = 0
N0.C2.D1.R1.S04: RcvEn: plus1 = 1, minus1 = 0, PI = 22, DB = 0
N2.C0.S02: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  5
N4.C3.D1.R1.S10: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N6.C2.D1.R1.S16: RcvEn: plus1 = 1, minus1 = 0, PI = 36, DB = 0
N0.C2.D1.R1.S05: RcvEn: plus1 = 1, minus1 = 0, PI = 34, DB = 0
N2.C0.S03: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  5
N4.C3.D1.R1.S11: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N6.C2.D1.R1.S17: RcvEn: plus1 = 1, minus1 = 0, PI = 20, DB = 0
N0.C2.D1.R1.S06: RcvEn: plus1 = 1, minus1 = 0, PI = 07, DB = 1
N2.C0.S04: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  5
N4.C3.D1.R1.S12: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
STOP_DATA_REC_EN
N0.C2.D1.R1.S07: RcvEn: plus1 = 1, minus1 = 0, PI = 25, DB = 0
N2.C0.S05: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  5
N4.C3.D1.R1.S13: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N6.C3.D0.R0: RcvEnFine: Initial RdCmd2RcvEnLatency = 10, Initial RdPtrOffsetRcvEn = 4
N0.C2.D1.R1.S08: RcvEn: plus1 = 1, minus1 = 0, PI = 11, DB = 1
N2.C0.S06: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  6
N4.C3.D1.R1.S14: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N6.C3.D0.R0.S00: Rcv En Fine Value = 324
N0.C2.D1.R1.S09: RcvEn: plus1 = 1, minus1 = 0, PI = 31, DB = 0
N2.C0.S07: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  6
N4.C3.D1.R1.S15: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N6.C3.D0.R0.S01: Rcv En Fine Value = 305
N0.C2.D1.R1.S10: RcvEn: plus1 = 1, minus1 = 0, PI = 06, DB = 1
N2.C0.S08: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  5
N4.C3.D1.R1.S16: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N6.C3.D0.R0.S02: Rcv En Fine Value = 278
N0.C2.D1.R1.S11: RcvEn: plus1 = 1, minus1 = 0, PI = 40, DB = 0
N2.C1.S00: SuppressionWindowAdjustmentRd: latency =  9, rdptroffset =  5
N4.C3.D1.R1.S17: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N6.C3.D0.R0.S03: Rcv En Fine Value = 382
N0.C2.D1.R1.S12: RcvEn: plus1 = 1, minus1 = 0, PI = 18, DB = 0
N2.C1.S01: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  6
N4.C3.D1.R1.S09: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N6.C3.D0.R0.S04: Rcv En Fine Value = 373
N0.C2.D1.R1.S13: RcvEn: plus1 = 1, minus1 = 0, PI = 23, DB = 0
N2.C1.S02: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  6
N4.C3.D1.R1.S10: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N6.C3.D0.R0.S05: Rcv En Fine Value = 272
N0.C2.D1.R1.S14: RcvEn: plus1 = 1, minus1 = 0, PI = 34, DB = 0
N2.C1.S03: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  6
N4.C3.D1.R1.S11: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N6.C3.D0.R0.S06: Rcv En Fine Value = 296
N0.C2.D1.R1.S15: RcvEn: plus1 = 1, minus1 = 0, PI = 07, DB = 1
N2.C1.S04: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  6
N4.C3.D1.R1.S12: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N6.C3.D0.R0.S07: Rcv En Fine Value = 319
N0.C2.D1.R1.S16: RcvEn: plus1 = 1, minus1 = 0, PI = 23, DB = 0
N2.C1.S05: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  6
N4.C3.D1.R1.S13: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N6.C3.D0.R0.S08: Rcv En Fine Value = 365
N0.C2.D1.R1.S17: RcvEn: plus1 = 1, minus1 = 0, PI = 07, DB = 1
N2.C1.S06: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  6
N4.C3.D1.R1.S14: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N6.C3.D0.R0.S09: Rcv En Fine Value = 322
STOP_DATA_REC_EN
N2.C1.S07: SuppressionWindowAdjustmentRd: latency =  9, rdptroffset =  5
N4.C3.D1.R1.S15: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N6.C3.D0.R0.S10: Rcv En Fine Value = 302
N0.C3.D0.R0: RcvEnFine: Initial RdCmd2RcvEnLatency = 10, Initial RdPtrOffsetRcvEn = 4
N2.C1.S08: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  5
N4.C3.D1.R1.S16: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N6.C3.D0.R0.S11: Rcv En Fine Value = 275
N0.C3.D0.R0.S00: Rcv En Fine Value = 321
N2.C2.S00: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  6
N4.C3.D1.R1.S17: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N6.C3.D0.R0.S12: Rcv En Fine Value = 379
N0.C3.D0.R0.S01: Rcv En Fine Value = 299
N2.C2.S01: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  6
N4.C3.D1.R1.S09: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N6.C3.D0.R0.S13: Rcv En Fine Value = 373
N0.C3.D0.R0.S02: Rcv En Fine Value = 271
N2.C2.S02: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  5
N4.C3.D1.R1.S10: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N6.C3.D0.R0.S14: Rcv En Fine Value = 277
N0.C3.D0.R0.S03: Rcv En Fine Value = 376
N2.C2.S03: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  5
N4.C3.D1.R1.S11: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N6.C3.D0.R0.S15: Rcv En Fine Value = 298
N0.C3.D0.R0.S04: Rcv En Fine Value = 374
N2.C2.S04: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  5
N4.C3.D1.R1.S12: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N6.C3.D0.R0.S16: Rcv En Fine Value = 319
N0.C3.D0.R0.S05: Rcv En Fine Value = 270
N2.C2.S05: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  5
N4.C3.D1.R1.S13: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N6.C3.D0.R0.S17: Rcv En Fine Value = 362
N0.C3.D0.R0.S06: Rcv En Fine Value = 293
N2.C2.S06: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  6
N4.C3.D1.R1.S14: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N6.C3.D0.R0: Starting preamble search lower nibbles
N0.C3.D0.R0.S07: Rcv En Fine Value = 315
N2.C2.S07: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  6
N4.C3.D1.R1.S15: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N6.C3.D0.R0.S00: PI = 004, PtrOffset = 005
N0.C3.D0.R0.S08: Rcv En Fine Value = 358
N2.C2.S08: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  5
N4.C3.D1.R1.S16: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N6.C3.D0.R0.S01: PI = 049, PtrOffset = 004
N0.C3.D0.R0.S09: Rcv En Fine Value = 322
N2.C3.S00: SuppressionWindowAdjustmentRd: latency =  9, rdptroffset =  5
N4.C3.D1.R1.S17: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N6.C3.D0.R0.S02: PI = 022, PtrOffset = 004
N0.C3.D0.R0.S10: Rcv En Fine Value = 300
N2.C3.S01: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  6
N4.C3.D1.R1.S09: Preamble found at Latency = 008
N6.C3.D0.R0.S03: PI = 062, PtrOffset = 005
N0.C3.D0.R0.S11: Rcv En Fine Value = 272
N2.C3.S02: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  6
N4.C3.D1.R1.S10: Preamble found at Latency = 008
N6.C3.D0.R0.S04: PI = 053, PtrOffset = 005
N0.C3.D0.R0.S12: Rcv En Fine Value = 377
N2.C3.S03: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  6
N4.C3.D1.R1.S11: Preamble found at Latency = 008
N6.C3.D0.R0.S05: PI = 016, PtrOffset = 004
N0.C3.D0.R0.S13: Rcv En Fine Value = 372
N2.C3.S04: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  6
N4.C3.D1.R1.S15: Preamble found at Latency = 008
N6.C3.D0.R0.S06: PI = 040, PtrOffset = 004
N0.C3.D0.R0.S14: Rcv En Fine Value = 270
N2.C3.S05: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  6
N4.C3.D1.R1.S16: Preamble found at Latency = 008
N6.C3.D0.R0.S07: PI = 063, PtrOffset = 004
N0.C3.D0.R0.S15: Rcv En Fine Value = 293
N2.C3.S06: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  6
N4.C3.D1.R1.S09: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N6.C3.D0.R0.S08: PI = 045, PtrOffset = 005
N0.C3.D0.R0.S16: Rcv En Fine Value = 317
N2.C3.S07: SuppressionWindowAdjustmentRd: latency =  9, rdptroffset =  5
N4.C3.D1.R1.S10: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N6.C3.D0.R0.S00: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N0.C3.D0.R0.S17: Rcv En Fine Value = 356
N2.C3.S08: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  5
N4.C3.D1.R1.S11: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N6.C3.D0.R0.S01: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N0.C3.D0.R0: Starting preamble search lower nibbles

START - Basic Write Level Training
N4.C3.D1.R1.S12: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N6.C3.D0.R0.S02: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N0.C3.D0.R0.S00: PI = 001, PtrOffset = 005
N2: START WRITE LEVEL:
N4.C3.D1.R1.S13: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N6.C3.D0.R0.S03: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N0.C3.D0.R0.S01: PI = 043, PtrOffset = 004
N2.C0.D0.R0: ODT Override: 0x5
N4.C3.D1.R1.S14: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N6.C3.D0.R0.S04: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N0.C3.D0.R0.S02: PI = 015, PtrOffset = 004
N2.C0.D0.R0.S00: Write Level Fine Value = 499
N4.C3.D1.R1.S15: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N6.C3.D0.R0.S05: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N0.C3.D0.R0.S03: PI = 056, PtrOffset = 005
N2.C0.D0.R0.S01: Write Level Fine Value = 480
N4.C3.D1.R1.S16: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N6.C3.D0.R0.S06: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N0.C3.D0.R0.S04: PI = 054, PtrOffset = 005
N2.C0.D0.R0.S02: Write Level Fine Value = 470
N4.C3.D1.R1.S17: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N6.C3.D0.R0.S07: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N0.C3.D0.R0.S05: PI = 014, PtrOffset = 004
N2.C0.D0.R0.S03: Write Level Fine Value = 450
N4.C3.D1.R1.S12: Preamble found at Latency = 007
N6.C3.D0.R0.S08: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N0.C3.D0.R0.S06: PI = 037, PtrOffset = 004
N2.C0.D0.R0.S04: Write Level Fine Value = 418
N4.C3.D1.R1.S13: Preamble found at Latency = 007
N6.C3.D0.R0.S00: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N0.C3.D0.R0.S07: PI = 059, PtrOffset = 004
N2.C0.D0.R0.S05: Write Level Fine Value = 436
N4.C3.D1.R1.S14: Preamble found at Latency = 007
N6.C3.D0.R0.S01: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N0.C3.D0.R0.S08: PI = 038, PtrOffset = 005
N2.C0.D0.R0.S06: Write Level Fine Value = 441
N4.C3.D1.R1.S17: Preamble found at Latency = 007
N6.C3.D0.R0.S02: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N0.C3.D0.R0.S00: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N2.C0.D0.R0.S07: Write Level Fine Value = 454
N4.C3.D1.R1: Preamble found for all upper nibbles, adjusting Pi, Offset to center into preamble
N6.C3.D0.R0.S03: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N0.C3.D0.R0.S01: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N2.C0.D0.R0.S08: Write Level Fine Value = 432
N4.C3.D1.R1.S09: Total Receive Enable Delay = 1361
N6.C3.D0.R0.S04: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N0.C3.D0.R0.S02: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N2.C0.D0.R0.S09: Write Level Fine Value = 502
N4.C3.D1.R1.S10: Total Receive Enable Delay = 1339
N6.C3.D0.R0.S05: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N0.C3.D0.R0.S03: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N2.C0.D0.R0.S10: Write Level Fine Value = 481
N4.C3.D1.R1.S11: Total Receive Enable Delay = 1314
N6.C3.D0.R0.S06: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N0.C3.D0.R0.S04: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N2.C0.D0.R0.S11: Write Level Fine Value = 469
N4.C3.D1.R1.S12: Total Receive Enable Delay = 1294
N6.C3.D0.R0.S07: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N0.C3.D0.R0.S05: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N2.C0.D0.R0.S12: Write Level Fine Value = 452
N4.C3.D1.R1.S13: Total Receive Enable Delay = 1284
N6.C3.D0.R0.S08: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N0.C3.D0.R0.S06: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N2.C0.D0.R0.S13: Write Level Fine Value = 420
N4.C3.D1.R1.S14: Total Receive Enable Delay = 1308
N6.C3.D0.R0.S00: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N0.C3.D0.R0.S07: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N2.C0.D0.R0.S14: Write Level Fine Value = 436
N4.C3.D1.R1.S15: Total Receive Enable Delay = 1333
N6.C3.D0.R0.S01: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N0.C3.D0.R0.S08: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N2.C0.D0.R0.S15: Write Level Fine Value = 439
N4.C3.D1.R1.S16: Total Receive Enable Delay = 1355
N6.C3.D0.R0.S02: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N0.C3.D0.R0.S00: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N2.C0.D0.R0.S16: Write Level Fine Value = 454
N4.C3.D1.R1.S17: Total Receive Enable Delay = 1270
N6.C3.D0.R0.S03: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N0.C3.D0.R0.S01: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N2.C0.D0.R0.S17: Write Level Fine Value = 432
START_DATA_REC_EN
N6.C3.D0.R0.S04: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N0.C3.D0.R0.S02: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N2.C0.D0.R1: ODT Override: 0x6
N4.C3.S00: RdCmd2RcvEnLatency = 9, RdPtrOffsetRcvEn = 5
N6.C3.D0.R0.S05: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N0.C3.D0.R0.S03: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N2.C0.D0.R1.S00: Write Level Fine Value = 494
N4.C3.S01: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N6.C3.D0.R0.S06: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N0.C3.D0.R0.S04: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N2.C0.D0.R1.S01: Write Level Fine Value = 476
N4.C3.S02: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N6.C3.D0.R0.S07: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N0.C3.D0.R0.S05: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N2.C0.D0.R1.S02: Write Level Fine Value = 462
N4.C3.S03: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N6.C3.D0.R0.S08: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N0.C3.D0.R0.S06: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N2.C0.D0.R1.S03: Write Level Fine Value = 444
N4.C3.S04: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N6.C3.D0.R0.S00: Preamble found at Latency = 008
N0.C3.D0.R0.S07: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N2.C0.D0.R1.S04: Write Level Fine Value = 411
N4.C3.S05: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N6.C3.D0.R0.S01: Preamble found at Latency = 008
N0.C3.D0.R0.S08: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N2.C0.D0.R1.S05: Write Level Fine Value = 429
N4.C3.S06: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N6.C3.D0.R0.S02: Preamble found at Latency = 008
N0.C3.D0.R0.S00: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N2.C0.D0.R1.S06: Write Level Fine Value = 434
N4.C3.S07: RdCmd2RcvEnLatency = 9, RdPtrOffsetRcvEn = 5
N6.C3.D0.R0.S05: Preamble found at Latency = 008
N0.C3.D0.R0.S01: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N2.C0.D0.R1.S07: Write Level Fine Value = 448
N4.C3.S08: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 5
N6.C3.D0.R0.S06: Preamble found at Latency = 008
N0.C3.D0.R0.S02: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N2.C0.D0.R1.S08: Write Level Fine Value = 424
N4.C3.S09: RdCmd2RcvEnLatency = 9, RdPtrOffsetRcvEn = 5
N6.C3.D0.R0.S07: Preamble found at Latency = 008
N0.C3.D0.R0.S03: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N2.C0.D0.R1.S09: Write Level Fine Value = 490
N4.C3.S10: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N6.C3.D0.R0.S00: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N0.C3.D0.R0.S04: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N2.C0.D0.R1.S10: Write Level Fine Value = 474
N4.C3.S11: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N6.C3.D0.R0.S01: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N0.C3.D0.R0.S05: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N2.C0.D0.R1.S11: Write Level Fine Value = 464
N4.C3.S12: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N6.C3.D0.R0.S02: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N0.C3.D0.R0.S06: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N2.C0.D0.R1.S12: Write Level Fine Value = 448
N4.C3.S13: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N6.C3.D0.R0.S03: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N0.C3.D0.R0.S07: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N2.C0.D0.R1.S13: Write Level Fine Value = 412
N4.C3.S14: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N6.C3.D0.R0.S04: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N0.C3.D0.R0.S08: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N2.C0.D0.R1.S14: Write Level Fine Value = 430
N4.C3.S15: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N6.C3.D0.R0.S05: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N0.C3.D0.R0.S00: Preamble found at Latency = 008
N2.C0.D0.R1.S15: Write Level Fine Value = 435
N4.C3.S16: RdCmd2RcvEnLatency = 9, RdPtrOffsetRcvEn = 5
N6.C3.D0.R0.S06: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N0.C3.D0.R0.S01: Preamble found at Latency = 008
N2.C0.D0.R1.S16: Write Level Fine Value = 449
N4.C3.S17: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 5
N6.C3.D0.R0.S07: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N0.C3.D0.R0.S02: Preamble found at Latency = 008
N2.C0.D0.R1.S17: Write Level Fine Value = 424
N4.C3.D0.R0.S00: RcvEn: plus1 = 1, minus1 = 0, PI = 30, DB = 0
N6.C3.D0.R0.S08: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N0.C3.D0.R0.S05: Preamble found at Latency = 008
N2.C0.D1.R0: ODT Override: 0x5
N4.C3.D0.R0.S01: RcvEn: plus1 = 0, minus1 = 1, PI = 10, DB = 1
N6.C3.D0.R0.S03: Preamble found at Latency = 007
N0.C3.D0.R0.S06: Preamble found at Latency = 008
N2.C0.D1.R0.S00: Write Level Fine Value = 503
N4.C3.D0.R0.S02: RcvEn: plus1 = 1, minus1 = 0, PI = 44, DB = 0
N6.C3.D0.R0.S04: Preamble found at Latency = 007
N0.C3.D0.R0.S07: Preamble found at Latency = 008
N2.C0.D1.R0.S01: Write Level Fine Value = 489
N4.C3.D0.R0.S03: RcvEn: plus1 = 1, minus1 = 0, PI = 24, DB = 0
N6.C3.D0.R0.S08: Preamble found at Latency = 007
N0.C3.D0.R0.S00: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N2.C0.D1.R0.S02: Write Level Fine Value = 475
N4.C3.D0.R0.S04: RcvEn: plus1 = 1, minus1 = 0, PI = 18, DB = 0
N6.C3.D0.R0.S00: Total Receive Enable Delay = 1380
N0.C3.D0.R0.S01: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N2.C0.D1.R0.S03: Write Level Fine Value = 457
N4.C3.D0.R0.S05: RcvEn: plus1 = 1, minus1 = 0, PI = 41, DB = 0
N6.C3.D0.R0.S01: Total Receive Enable Delay = 1361
N0.C3.D0.R0.S02: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N2.C0.D1.R0.S04: Write Level Fine Value = 425
N4.C3.D0.R0.S06: RcvEn: plus1 = 0, minus1 = 1, PI = 04, DB = 1
N6.C3.D0.R0.S02: Total Receive Enable Delay = 1334
N0.C3.D0.R0.S03: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N2.C0.D1.R0.S05: Write Level Fine Value = 443
N4.C3.D0.R0.S07: RcvEn: plus1 = 1, minus1 = 0, PI = 23, DB = 0
N6.C3.D0.R0.S03: Total Receive Enable Delay = 1310
N0.C3.D0.R0.S04: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N2.C0.D1.R0.S06: Write Level Fine Value = 446
N4.C3.D0.R0.S08: RcvEn: plus1 = 0, minus1 = 1, PI = 02, DB = 1
N6.C3.D0.R0.S04: Total Receive Enable Delay = 1301
N0.C3.D0.R0.S05: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N2.C0.D1.R0.S07: Write Level Fine Value = 462
N4.C3.D0.R0.S09: RcvEn: plus1 = 1, minus1 = 0, PI = 30, DB = 0
N6.C3.D0.R0.S05: Total Receive Enable Delay = 1328
N0.C3.D0.R0.S06: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N2.C0.D1.R0.S08: Write Level Fine Value = 433
N4.C3.D0.R0.S10: RcvEn: plus1 = 0, minus1 = 1, PI = 10, DB = 1
N6.C3.D0.R0.S06: Total Receive Enable Delay = 1352
N0.C3.D0.R0.S07: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N2.C0.D1.R0.S09: Write Level Fine Value = 505
N4.C3.D0.R0.S11: RcvEn: plus1 = 1, minus1 = 0, PI = 46, DB = 0
N6.C3.D0.R0.S07: Total Receive Enable Delay = 1375
N0.C3.D0.R0.S08: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N2.C0.D1.R0.S10: Write Level Fine Value = 487
N4.C3.D0.R0.S12: RcvEn: plus1 = 1, minus1 = 0, PI = 25, DB = 0
N6.C3.D0.R0.S08: Total Receive Enable Delay = 1293
N0.C3.D0.R0.S03: Preamble found at Latency = 007
N2.C0.D1.R0.S11: Write Level Fine Value = 477
N4.C3.D0.R0.S13: RcvEn: plus1 = 1, minus1 = 0, PI = 18, DB = 0
N6.C3.D0.R0: Starting preamble search upper nibbles
N0.C3.D0.R0.S04: Preamble found at Latency = 007
N2.C0.D1.R0.S12: Write Level Fine Value = 461
N4.C3.D0.R0.S14: RcvEn: plus1 = 1, minus1 = 0, PI = 42, DB = 0
N6.C3.D0.R0.S09: PI = 002, PtrOffset = 005
N0.C3.D0.R0.S08: Preamble found at Latency = 007
N2.C0.D1.R0.S13: Write Level Fine Value = 426
N4.C3.D0.R0.S15: RcvEn: plus1 = 0, minus1 = 1, PI = 03, DB = 1
N6.C3.D0.R0.S10: PI = 046, PtrOffset = 004
N0.C3.D0.R0.S00: Total Receive Enable Delay = 1377
N2.C0.D1.R0.S14: Write Level Fine Value = 445
N4.C3.D0.R0.S16: RcvEn: plus1 = 1, minus1 = 0, PI = 26, DB = 0
N6.C3.D0.R0.S11: PI = 019, PtrOffset = 004
N0.C3.D0.R0.S01: Total Receive Enable Delay = 1355
N2.C0.D1.R0.S15: Write Level Fine Value = 446
N4.C3.D0.R0.S17: RcvEn: plus1 = 0, minus1 = 1, PI = 03, DB = 1
N6.C3.D0.R0.S12: PI = 059, PtrOffset = 005
N0.C3.D0.R0.S02: Total Receive Enable Delay = 1327
N2.C0.D1.R0.S16: Write Level Fine Value = 462
N4.C3.D0.R1.S00: RcvEn: plus1 = 1, minus1 = 0, PI = 30, DB = 0
N6.C3.D0.R0.S13: PI = 053, PtrOffset = 005
N0.C3.D0.R0.S03: Total Receive Enable Delay = 1304
N2.C0.D1.R0.S17: Write Level Fine Value = 434
N4.C3.D0.R1.S01: RcvEn: plus1 = 0, minus1 = 1, PI = 10, DB = 1
N6.C3.D0.R0.S14: PI = 021, PtrOffset = 004
N0.C3.D0.R0.S04: Total Receive Enable Delay = 1302
N2.C0.D1.R1: ODT Override: 0x9
N4.C3.D0.R1.S02: RcvEn: plus1 = 1, minus1 = 0, PI = 44, DB = 0
N6.C3.D0.R0.S15: PI = 042, PtrOffset = 004
N0.C3.D0.R0.S05: Total Receive Enable Delay = 1326
N2.C0.D1.R1.S00: Write Level Fine Value = 498
N4.C3.D0.R1.S03: RcvEn: plus1 = 1, minus1 = 0, PI = 24, DB = 0
N6.C3.D0.R0.S16: PI = 063, PtrOffset = 004
N0.C3.D0.R0.S06: Total Receive Enable Delay = 1349
N2.C0.D1.R1.S01: Write Level Fine Value = 486
N4.C3.D0.R1.S04: RcvEn: plus1 = 1, minus1 = 0, PI = 18, DB = 0
N6.C3.D0.R0.S17: PI = 042, PtrOffset = 005
N0.C3.D0.R0.S07: Total Receive Enable Delay = 1371
N2.C0.D1.R1.S02: Write Level Fine Value = 471
N4.C3.D0.R1.S05: RcvEn: plus1 = 1, minus1 = 0, PI = 41, DB = 0
N6.C3.D0.R0.S09: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N0.C3.D0.R0.S08: Total Receive Enable Delay = 1286
N2.C0.D1.R1.S03: Write Level Fine Value = 455
N4.C3.D0.R1.S06: RcvEn: plus1 = 0, minus1 = 1, PI = 04, DB = 1
N6.C3.D0.R0.S10: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N0.C3.D0.R0: Starting preamble search upper nibbles
N2.C0.D1.R1.S04: Write Level Fine Value = 420
N4.C3.D0.R1.S07: RcvEn: plus1 = 1, minus1 = 0, PI = 23, DB = 0
N6.C3.D0.R0.S11: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N0.C3.D0.R0.S09: PI = 002, PtrOffset = 005
N2.C0.D1.R1.S05: Write Level Fine Value = 440
N4.C3.D0.R1.S08: RcvEn: plus1 = 0, minus1 = 1, PI = 02, DB = 1
N6.C3.D0.R0.S12: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N0.C3.D0.R0.S10: PI = 044, PtrOffset = 004
N2.C0.D1.R1.S06: Write Level Fine Value = 443
N4.C3.D0.R1.S09: RcvEn: plus1 = 1, minus1 = 0, PI = 30, DB = 0
N6.C3.D0.R0.S13: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N0.C3.D0.R0.S11: PI = 016, PtrOffset = 004
N2.C0.D1.R1.S07: Write Level Fine Value = 460
N4.C3.D0.R1.S10: RcvEn: plus1 = 0, minus1 = 1, PI = 10, DB = 1
N6.C3.D0.R0.S14: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N0.C3.D0.R0.S12: PI = 057, PtrOffset = 005
N2.C0.D1.R1.S08: Write Level Fine Value = 431
N4.C3.D0.R1.S11: RcvEn: plus1 = 1, minus1 = 0, PI = 46, DB = 0
N6.C3.D0.R0.S15: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N0.C3.D0.R0.S13: PI = 052, PtrOffset = 005
N2.C0.D1.R1.S09: Write Level Fine Value = 498
N4.C3.D0.R1.S12: RcvEn: plus1 = 1, minus1 = 0, PI = 25, DB = 0
N6.C3.D0.R0.S16: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N0.C3.D0.R0.S14: PI = 014, PtrOffset = 004
N2.C0.D1.R1.S10: Write Level Fine Value = 487
N4.C3.D0.R1.S13: RcvEn: plus1 = 1, minus1 = 0, PI = 18, DB = 0
N6.C3.D0.R0.S17: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N0.C3.D0.R0.S15: PI = 037, PtrOffset = 004
N2.C0.D1.R1.S11: Write Level Fine Value = 473
N4.C3.D0.R1.S14: RcvEn: plus1 = 1, minus1 = 0, PI = 42, DB = 0
N6.C3.D0.R0.S09: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N0.C3.D0.R0.S16: PI = 061, PtrOffset = 004
N2.C0.D1.R1.S12: Write Level Fine Value = 459
N4.C3.D0.R1.S15: RcvEn: plus1 = 0, minus1 = 1, PI = 03, DB = 1
N6.C3.D0.R0.S10: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N0.C3.D0.R0.S17: PI = 036, PtrOffset = 005
N2.C0.D1.R1.S13: Write Level Fine Value = 421
N4.C3.D0.R1.S16: RcvEn: plus1 = 1, minus1 = 0, PI = 26, DB = 0
N6.C3.D0.R0.S11: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N0.C3.D0.R0.S09: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N2.C0.D1.R1.S14: Write Level Fine Value = 439
N4.C3.D0.R1.S17: RcvEn: plus1 = 0, minus1 = 1, PI = 03, DB = 1
N6.C3.D0.R0.S12: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N0.C3.D0.R0.S10: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N2.C0.D1.R1.S15: Write Level Fine Value = 443
N4.C3.D1.R0.S00: RcvEn: plus1 = 1, minus1 = 0, PI = 15, DB = 1
N6.C3.D0.R0.S13: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N0.C3.D0.R0.S11: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N2.C0.D1.R1.S16: Write Level Fine Value = 459
N4.C3.D1.R0.S01: RcvEn: plus1 = 1, minus1 = 0, PI = 60, DB = 1
N6.C3.D0.R0.S14: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N0.C3.D0.R0.S12: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N2.C0.D1.R1.S17: Write Level Fine Value = 431
N4.C3.D1.R0.S02: RcvEn: plus1 = 1, minus1 = 0, PI = 29, DB = 0
N6.C3.D0.R0.S15: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N0.C3.D0.R0.S13: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N2.C1.D0.R0: ODT Override: 0x5
N4.C3.D1.R0.S03: RcvEn: plus1 = 1, minus1 = 0, PI = 10, DB = 1
N6.C3.D0.R0.S16: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N0.C3.D0.R0.S14: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N2.C1.D0.R0.S00: Write Level Fine Value = 499
N4.C3.D1.R0.S04: RcvEn: plus1 = 1, minus1 = 0, PI = 04, DB = 1
N6.C3.D0.R0.S17: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N0.C3.D0.R0.S15: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N2.C1.D0.R0.S01: Write Level Fine Value = 482
N4.C3.D1.R0.S05: RcvEn: plus1 = 1, minus1 = 0, PI = 27, DB = 0
N6.C3.D0.R0.S09: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N0.C3.D0.R0.S16: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N2.C1.D0.R0.S02: Write Level Fine Value = 475
N4.C3.D1.R0.S06: RcvEn: plus1 = 1, minus1 = 0, PI = 53, DB = 1
N6.C3.D0.R0.S10: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N0.C3.D0.R0.S17: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N2.C1.D0.R0.S03: Write Level Fine Value = 457
N4.C3.D1.R0.S07: RcvEn: plus1 = 1, minus1 = 0, PI = 10, DB = 1
N6.C3.D0.R0.S11: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N0.C3.D0.R0.S09: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N2.C1.D0.R0.S04: Write Level Fine Value = 425
N4.C3.D1.R0.S08: RcvEn: plus1 = 1, minus1 = 0, PI = 54, DB = 1
N6.C3.D0.R0.S12: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N0.C3.D0.R0.S10: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N2.C1.D0.R0.S05: Write Level Fine Value = 440
N4.C3.D1.R0.S09: RcvEn: plus1 = 1, minus1 = 0, PI = 17, DB = 0
N6.C3.D0.R0.S13: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N0.C3.D0.R0.S11: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N2.C1.D0.R0.S06: Write Level Fine Value = 454
N4.C3.D1.R0.S10: RcvEn: plus1 = 1, minus1 = 0, PI = 59, DB = 1
N6.C3.D0.R0.S14: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N0.C3.D0.R0.S12: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N2.C1.D0.R0.S07: Write Level Fine Value = 470
N4.C3.D1.R0.S11: RcvEn: plus1 = 1, minus1 = 0, PI = 32, DB = 0
N6.C3.D0.R0.S15: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N0.C3.D0.R0.S13: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N2.C1.D0.R0.S08: Write Level Fine Value = 440
N4.C3.D1.R0.S12: RcvEn: plus1 = 1, minus1 = 0, PI = 13, DB = 1
N6.C3.D0.R0.S16: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N0.C3.D0.R0.S14: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N2.C1.D0.R0.S09: Write Level Fine Value = 500
N4.C3.D1.R0.S13: RcvEn: plus1 = 1, minus1 = 0, PI = 04, DB = 1
N6.C3.D0.R0.S17: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N0.C3.D0.R0.S15: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N2.C1.D0.R0.S10: Write Level Fine Value = 482
N4.C3.D1.R0.S14: RcvEn: plus1 = 1, minus1 = 0, PI = 29, DB = 0
N6.C3.D0.R0.S09: Preamble found at Latency = 008
N0.C3.D0.R0.S16: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N2.C1.D0.R0.S11: Write Level Fine Value = 475
N4.C3.D1.R0.S15: RcvEn: plus1 = 1, minus1 = 0, PI = 52, DB = 1
N6.C3.D0.R0.S10: Preamble found at Latency = 008
N0.C3.D0.R0.S17: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N2.C1.D0.R0.S12: Write Level Fine Value = 457
N4.C3.D1.R0.S16: RcvEn: plus1 = 1, minus1 = 0, PI = 10, DB = 1
N6.C3.D0.R0.S11: Preamble found at Latency = 008
N0.C3.D0.R0.S09: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N2.C1.D0.R0.S13: Write Level Fine Value = 425
N4.C3.D1.R0.S17: RcvEn: plus1 = 1, minus1 = 0, PI = 54, DB = 1
N6.C3.D0.R0.S14: Preamble found at Latency = 008
N0.C3.D0.R0.S10: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N2.C1.D0.R0.S14: Write Level Fine Value = 440
N4.C3.D1.R1.S00: RcvEn: plus1 = 1, minus1 = 0, PI = 15, DB = 1
N6.C3.D0.R0.S15: Preamble found at Latency = 008
N0.C3.D0.R0.S11: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N2.C1.D0.R0.S15: Write Level Fine Value = 453
N4.C3.D1.R1.S01: RcvEn: plus1 = 1, minus1 = 0, PI = 60, DB = 1
N6.C3.D0.R0.S16: Preamble found at Latency = 008
N0.C3.D0.R0.S12: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N2.C1.D0.R0.S16: Write Level Fine Value = 471
N4.C3.D1.R1.S02: RcvEn: plus1 = 1, minus1 = 0, PI = 29, DB = 0
N6.C3.D0.R0.S09: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N0.C3.D0.R0.S13: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N2.C1.D0.R0.S17: Write Level Fine Value = 438
N4.C3.D1.R1.S03: RcvEn: plus1 = 1, minus1 = 0, PI = 10, DB = 1
N6.C3.D0.R0.S10: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N0.C3.D0.R0.S14: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N2.C1.D0.R1: ODT Override: 0x6
N4.C3.D1.R1.S04: RcvEn: plus1 = 1, minus1 = 0, PI = 04, DB = 1
N6.C3.D0.R0.S11: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N0.C3.D0.R0.S15: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N2.C1.D0.R1.S00: Write Level Fine Value = 492
N4.C3.D1.R1.S05: RcvEn: plus1 = 1, minus1 = 0, PI = 27, DB = 0
N6.C3.D0.R0.S12: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N0.C3.D0.R0.S16: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N2.C1.D0.R1.S01: Write Level Fine Value = 476
N4.C3.D1.R1.S06: RcvEn: plus1 = 1, minus1 = 0, PI = 53, DB = 1
N6.C3.D0.R0.S13: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N0.C3.D0.R0.S17: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N2.C1.D0.R1.S02: Write Level Fine Value = 468
N4.C3.D1.R1.S07: RcvEn: plus1 = 1, minus1 = 0, PI = 10, DB = 1
N6.C3.D0.R0.S14: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N0.C3.D0.R0.S09: Preamble found at Latency = 008
N2.C1.D0.R1.S03: Write Level Fine Value = 451
N4.C3.D1.R1.S08: RcvEn: plus1 = 1, minus1 = 0, PI = 54, DB = 1
N6.C3.D0.R0.S15: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N0.C3.D0.R0.S10: Preamble found at Latency = 008
N2.C1.D0.R1.S04: Write Level Fine Value = 420
N4.C3.D1.R1.S09: RcvEn: plus1 = 1, minus1 = 0, PI = 17, DB = 0
N6.C3.D0.R0.S16: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N0.C3.D0.R0.S11: Preamble found at Latency = 008
N2.C1.D0.R1.S05: Write Level Fine Value = 433
N4.C3.D1.R1.S10: RcvEn: plus1 = 1, minus1 = 0, PI = 59, DB = 1
N6.C3.D0.R0.S17: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N0.C3.D0.R0.S14: Preamble found at Latency = 008
N2.C1.D0.R1.S06: Write Level Fine Value = 445
N4.C3.D1.R1.S11: RcvEn: plus1 = 1, minus1 = 0, PI = 32, DB = 0
N6.C3.D0.R0.S12: Preamble found at Latency = 007
N0.C3.D0.R0.S15: Preamble found at Latency = 008
N2.C1.D0.R1.S07: Write Level Fine Value = 463
N4.C3.D1.R1.S12: RcvEn: plus1 = 1, minus1 = 0, PI = 13, DB = 1
N6.C3.D0.R0.S13: Preamble found at Latency = 007
N0.C3.D0.R0.S16: Preamble found at Latency = 008
N2.C1.D0.R1.S08: Write Level Fine Value = 433
N4.C3.D1.R1.S13: RcvEn: plus1 = 1, minus1 = 0, PI = 04, DB = 1
N6.C3.D0.R0.S17: Preamble found at Latency = 007
N0.C3.D0.R0.S09: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N2.C1.D0.R1.S09: Write Level Fine Value = 491
N4.C3.D1.R1.S14: RcvEn: plus1 = 1, minus1 = 0, PI = 29, DB = 0
N6.C3.D0.R0: Preamble found for all upper nibbles, adjusting Pi, Offset to center into preamble
N0.C3.D0.R0.S10: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N2.C1.D0.R1.S10: Write Level Fine Value = 476
N4.C3.D1.R1.S15: RcvEn: plus1 = 1, minus1 = 0, PI = 52, DB = 1
N6.C3.D0.R0.S09: Total Receive Enable Delay = 1378
N0.C3.D0.R0.S11: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N2.C1.D0.R1.S11: Write Level Fine Value = 467
N4.C3.D1.R1.S16: RcvEn: plus1 = 1, minus1 = 0, PI = 10, DB = 1
N6.C3.D0.R0.S10: Total Receive Enable Delay = 1358
N0.C3.D0.R0.S12: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N2.C1.D0.R1.S12: Write Level Fine Value = 452
N4.C3.D1.R1.S17: RcvEn: plus1 = 1, minus1 = 0, PI = 54, DB = 1
N6.C3.D0.R0.S11: Total Receive Enable Delay = 1331
N0.C3.D0.R0.S13: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N2.C1.D0.R1.S13: Write Level Fine Value = 418
STOP_DATA_REC_EN
N6.C3.D0.R0.S12: Total Receive Enable Delay = 1307
N0.C3.D0.R0.S14: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N2.C1.D0.R1.S14: Write Level Fine Value = 433
N4.C0.D0.R0.S00: StoreJckWorstRank: worst rank = 0, greatestDelay = 1324
N6.C3.D0.R0.S13: Total Receive Enable Delay = 1301
N0.C3.D0.R0.S15: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N2.C1.D0.R1.S15: Write Level Fine Value = 447
N4.C0.D0.R0.S07: StoreJckWorstRank: worst rank = 0, greatestDelay = 1325
N6.C3.D0.R0.S14: Total Receive Enable Delay = 1333
N0.C3.D0.R0.S16: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N2.C1.D0.R1.S16: Write Level Fine Value = 463
N4.C0.D0.R1.S07: StoreJckWorstRank: worst rank = 1, greatestDelay = 1326
N6.C3.D0.R0.S15: Total Receive Enable Delay = 1354
N0.C3.D0.R0.S17: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N2.C1.D0.R1.S17: Write Level Fine Value = 434
N4.C1.D0.R0.S00: StoreJckWorstRank: worst rank = 0, greatestDelay = 1373
N6.C3.D0.R0.S16: Total Receive Enable Delay = 1375
N0.C3.D0.R0.S12: Preamble found at Latency = 007
N2.C1.D1.R0: ODT Override: 0x5
N4.C1.D0.R1.S00: StoreJckWorstRank: worst rank = 1, greatestDelay = 1374
N6.C3.D0.R0.S17: Total Receive Enable Delay = 1290
N0.C3.D0.R0.S13: Preamble found at Latency = 007
N2.C1.D1.R0.S00: Write Level Fine Value = 504
N4.C0: StoreJckWorstRank: final value: worst rank = 1
N6.C3.D0.R1: RcvEnFine: Initial RdCmd2RcvEnLatency = 10, Initial RdPtrOffsetRcvEn = 4
N0.C3.D0.R0.S17: Preamble found at Latency = 007
N2.C1.D1.R0.S01: Write Level Fine Value = 489
N4.C2.D0.R0.S00: StoreJckWorstRank: worst rank = 0, greatestDelay = 1326
N6.C3.D0.R1.S00: Rcv En Fine Value = 325
N0.C3.D0.R0: Preamble found for all upper nibbles, adjusting Pi, Offset to center into preamble
N2.C1.D1.R0.S02: Write Level Fine Value = 481
N4.C3.D0.R0.S00: StoreJckWorstRank: worst rank = 0, greatestDelay = 1374
N6.C3.D0.R1.S01: Rcv En Fine Value = 303
N0.C3.D0.R0.S09: Total Receive Enable Delay = 1378
N2.C1.D1.R0.S03: Write Level Fine Value = 463
N4.C3.D0.R0.S09: StoreJckWorstRank: worst rank = 0, greatestDelay = 1375
N6.C3.D0.R1.S02: Rcv En Fine Value = 274
N0.C3.D0.R0.S10: Total Receive Enable Delay = 1356
N2.C1.D1.R0.S04: Write Level Fine Value = 432
N4.C1: StoreJckWorstRank: final value: worst rank = 0
N6.C3.D0.R1.S03: Rcv En Fine Value = 378
N0.C3.D0.R0.S11: Total Receive Enable Delay = 1328
N2.C1.D1.R0.S05: Write Level Fine Value = 447
N4: RunTrainStep: Final status = 0
N6.C3.D0.R1.S04: Rcv En Fine Value = 373
N0.C3.D0.R0.S12: Total Receive Enable Delay = 1305
N2.C1.D1.R0.S06: Write Level Fine Value = 458

END - Basic Receive Enable Training    Time         63640 ms
N6.C3.D0.R1.S05: Rcv En Fine Value = 274
N0.C3.D0.R0.S13: Total Receive Enable Delay = 1300
N2.C1.D1.R0.S07: Write Level Fine Value = 477
N4.C0.S00: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  6
N6.C3.D0.R1.S06: Rcv En Fine Value = 296
N0.C3.D0.R0.S14: Total Receive Enable Delay = 1326
N2.C1.D1.R0.S08: Write Level Fine Value = 442
N4.C0.S01: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  6
N6.C3.D0.R1.S07: Rcv En Fine Value = 317
N0.C3.D0.R0.S15: Total Receive Enable Delay = 1349
N2.C1.D1.R0.S09: Write Level Fine Value = 505
N4.C0.S02: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  5
N6.C3.D0.R1.S08: Rcv En Fine Value = 363
N0.C3.D0.R0.S16: Total Receive Enable Delay = 1373
N2.C1.D1.R0.S10: Write Level Fine Value = 488
N4.C0.S03: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  5
N6.C3.D0.R1.S09: Rcv En Fine Value = 322
N0.C3.D0.R0.S17: Total Receive Enable Delay = 1284
N2.C1.D1.R0.S11: Write Level Fine Value = 481
N4.C0.S04: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  5
N6.C3.D0.R1.S10: Rcv En Fine Value = 305
N0.C3.D0.R1: RcvEnFine: Initial RdCmd2RcvEnLatency = 10, Initial RdPtrOffsetRcvEn = 4
N2.C1.D1.R0.S12: Write Level Fine Value = 465
N4.C0.S05: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  5
N6.C3.D0.R1.S11: Rcv En Fine Value = 275
N0.C3.D0.R1.S00: Rcv En Fine Value = 323
N2.C1.D1.R0.S13: Write Level Fine Value = 431
N4.C0.S06: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  6
N6.C3.D0.R1.S12: Rcv En Fine Value = 380
N0.C3.D0.R1.S01: Rcv En Fine Value = 300
N2.C1.D1.R0.S14: Write Level Fine Value = 447
N4.C0.S07: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  6
N6.C3.D0.R1.S13: Rcv En Fine Value = 374
N0.C3.D0.R1.S02: Rcv En Fine Value = 272
N2.C1.D1.R0.S15: Write Level Fine Value = 457
N4.C0.S08: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  5
N6.C3.D0.R1.S14: Rcv En Fine Value = 276
N0.C3.D0.R1.S03: Rcv En Fine Value = 374
N2.C1.D1.R0.S16: Write Level Fine Value = 476
N4.C1.S00: SuppressionWindowAdjustmentRd: latency =  9, rdptroffset =  5
N6.C3.D0.R1.S15: Rcv En Fine Value = 299
N0.C3.D0.R1.S04: Rcv En Fine Value = 371
N2.C1.D1.R0.S17: Write Level Fine Value = 443
N4.C1.S01: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  6
N6.C3.D0.R1.S16: Rcv En Fine Value = 318
N0.C3.D0.R1.S05: Rcv En Fine Value = 269
N2.C1.D1.R1: ODT Override: 0x9
N4.C1.S02: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  6
N6.C3.D0.R1.S17: Rcv En Fine Value = 362
N0.C3.D0.R1.S06: Rcv En Fine Value = 291
N2.C1.D1.R1.S00: Write Level Fine Value = 500
N4.C1.S03: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  6
N6.C3.D0.R1: Starting preamble search lower nibbles
N0.C3.D0.R1.S07: Rcv En Fine Value = 313
N2.C1.D1.R1.S01: Write Level Fine Value = 484
N4.C1.S04: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  5
N6.C3.D0.R1.S00: PI = 005, PtrOffset = 005
N0.C3.D0.R1.S08: Rcv En Fine Value = 360
N2.C1.D1.R1.S02: Write Level Fine Value = 476
N4.C1.S05: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  6
N6.C3.D0.R1.S01: PI = 047, PtrOffset = 004
N0.C3.D0.R1.S09: Rcv En Fine Value = 320
N2.C1.D1.R1.S03: Write Level Fine Value = 459
N4.C1.S06: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  6
N6.C3.D0.R1.S02: PI = 018, PtrOffset = 004
N0.C3.D0.R1.S10: Rcv En Fine Value = 302
N2.C1.D1.R1.S04: Write Level Fine Value = 427
N4.C1.S07: SuppressionWindowAdjustmentRd: latency =  9, rdptroffset =  5
N6.C3.D0.R1.S03: PI = 058, PtrOffset = 005
N0.C3.D0.R1.S11: Rcv En Fine Value = 272
N2.C1.D1.R1.S05: Write Level Fine Value = 442
N4.C1.S08: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  5
N6.C3.D0.R1.S04: PI = 053, PtrOffset = 005
N0.C3.D0.R1.S12: Rcv En Fine Value = 378
N2.C1.D1.R1.S06: Write Level Fine Value = 455
N4.C2.S00: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  6
N6.C3.D0.R1.S05: PI = 018, PtrOffset = 004
N0.C3.D0.R1.S13: Rcv En Fine Value = 370
N2.C1.D1.R1.S07: Write Level Fine Value = 473
N4.C2.S01: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  6
N6.C3.D0.R1.S06: PI = 040, PtrOffset = 004
N0.C3.D0.R1.S14: Rcv En Fine Value = 270
N2.C1.D1.R1.S08: Write Level Fine Value = 437
N4.C2.S02: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  5
N6.C3.D0.R1.S07: PI = 061, PtrOffset = 004
N0.C3.D0.R1.S15: Rcv En Fine Value = 292
N2.C1.D1.R1.S09: Write Level Fine Value = 499
N4.C2.S03: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  5
N6.C3.D0.R1.S08: PI = 043, PtrOffset = 005
N0.C3.D0.R1.S16: Rcv En Fine Value = 317
N2.C1.D1.R1.S10: Write Level Fine Value = 483
N4.C2.S04: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  5
N6.C3.D0.R1.S00: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N0.C3.D0.R1.S17: Rcv En Fine Value = 356
N2.C1.D1.R1.S11: Write Level Fine Value = 476
N4.C2.S05: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  5
N6.C3.D0.R1.S01: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N0.C3.D0.R1: Starting preamble search lower nibbles
N2.C1.D1.R1.S12: Write Level Fine Value = 462
N4.C2.S06: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  6
N6.C3.D0.R1.S02: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N0.C3.D0.R1.S00: PI = 003, PtrOffset = 005
N2.C1.D1.R1.S13: Write Level Fine Value = 427
N4.C2.S07: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  6
N6.C3.D0.R1.S03: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N0.C3.D0.R1.S01: PI = 044, PtrOffset = 004
N2.C1.D1.R1.S14: Write Level Fine Value = 441
N4.C2.S08: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  5
N6.C3.D0.R1.S04: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N0.C3.D0.R1.S02: PI = 016, PtrOffset = 004
N2.C1.D1.R1.S15: Write Level Fine Value = 452
N4.C3.S00: SuppressionWindowAdjustmentRd: latency =  9, rdptroffset =  5
N6.C3.D0.R1.S05: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N0.C3.D0.R1.S03: PI = 054, PtrOffset = 005
N2.C1.D1.R1.S16: Write Level Fine Value = 473
N4.C3.S01: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  6
N6.C3.D0.R1.S06: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N0.C3.D0.R1.S04: PI = 051, PtrOffset = 005
N2.C1.D1.R1.S17: Write Level Fine Value = 437
N4.C3.S02: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  6
N6.C3.D0.R1.S07: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N0.C3.D0.R1.S05: PI = 013, PtrOffset = 004
N2.C2.D0.R0: ODT Override: 0x5
N4.C3.S03: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  6
N6.C3.D0.R1.S08: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N0.C3.D0.R1.S06: PI = 035, PtrOffset = 004
N2.C2.D0.R0.S00: Write Level Fine Value = 498
N4.C3.S04: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  6
N6.C3.D0.R1.S00: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N0.C3.D0.R1.S07: PI = 057, PtrOffset = 004
N2.C2.D0.R0.S01: Write Level Fine Value = 483
N4.C3.S05: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  6
N6.C3.D0.R1.S01: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N0.C3.D0.R1.S08: PI = 040, PtrOffset = 005
N2.C2.D0.R0.S02: Write Level Fine Value = 472
N4.C3.S06: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  6
N6.C3.D0.R1.S02: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N0.C3.D0.R1.S00: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N2.C2.D0.R0.S03: Write Level Fine Value = 454
N4.C3.S07: SuppressionWindowAdjustmentRd: latency =  9, rdptroffset =  5
N6.C3.D0.R1.S03: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N0.C3.D0.R1.S01: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N2.C2.D0.R0.S04: Write Level Fine Value = 413
N4.C3.S08: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  5
N6.C3.D0.R1.S04: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N0.C3.D0.R1.S02: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N2.C2.D0.R0.S05: Write Level Fine Value = 444

START - Basic Write Level Training
N6.C3.D0.R1.S05: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N0.C3.D0.R1.S03: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N2.C2.D0.R0.S06: Write Level Fine Value = 440
N4: START WRITE LEVEL:
N6.C3.D0.R1.S06: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N0.C3.D0.R1.S04: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N2.C2.D0.R0.S07: Write Level Fine Value = 462
N4.C0.D0.R0: ODT Override: 0x5
N6.C3.D0.R1.S07: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N0.C3.D0.R1.S05: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N2.C2.D0.R0.S08: Write Level Fine Value = 436
N4.C0.D0.R0.S00: Write Level Fine Value = 507
N6.C3.D0.R1.S08: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N0.C3.D0.R1.S06: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N2.C2.D0.R0.S09: Write Level Fine Value = 500
N4.C0.D0.R0.S01: Write Level Fine Value = 486
N6.C3.D0.R1.S00: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N0.C3.D0.R1.S07: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N2.C2.D0.R0.S10: Write Level Fine Value = 482
N4.C0.D0.R0.S02: Write Level Fine Value = 479
N6.C3.D0.R1.S01: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N0.C3.D0.R1.S08: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N2.C2.D0.R0.S11: Write Level Fine Value = 472
N4.C0.D0.R0.S03: Write Level Fine Value = 458
N6.C3.D0.R1.S02: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N0.C3.D0.R1.S00: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N2.C2.D0.R0.S12: Write Level Fine Value = 456
N4.C0.D0.R0.S04: Write Level Fine Value = 428
N6.C3.D0.R1.S03: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N0.C3.D0.R1.S01: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N2.C2.D0.R0.S13: Write Level Fine Value = 415
N4.C0.D0.R0.S05: Write Level Fine Value = 446
N6.C3.D0.R1.S04: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N0.C3.D0.R1.S02: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N2.C2.D0.R0.S14: Write Level Fine Value = 442
N4.C0.D0.R0.S06: Write Level Fine Value = 448
N6.C3.D0.R1.S05: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N0.C3.D0.R1.S03: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N2.C2.D0.R0.S15: Write Level Fine Value = 440
N4.C0.D0.R0.S07: Write Level Fine Value = 462
N6.C3.D0.R1.S06: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N0.C3.D0.R1.S04: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N2.C2.D0.R0.S16: Write Level Fine Value = 464
N4.C0.D0.R0.S08: Write Level Fine Value = 440
N6.C3.D0.R1.S07: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N0.C3.D0.R1.S05: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N2.C2.D0.R0.S17: Write Level Fine Value = 435
N4.C0.D0.R0.S09: Write Level Fine Value = 505
N6.C3.D0.R1.S08: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N0.C3.D0.R1.S06: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N2.C2.D0.R1: ODT Override: 0x6
N4.C0.D0.R0.S10: Write Level Fine Value = 486
N6.C3.D0.R1.S00: Preamble found at Latency = 008
N0.C3.D0.R1.S07: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N2.C2.D0.R1.S00: Write Level Fine Value = 491
N4.C0.D0.R0.S11: Write Level Fine Value = 474
N6.C3.D0.R1.S01: Preamble found at Latency = 008
N0.C3.D0.R1.S08: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N2.C2.D0.R1.S01: Write Level Fine Value = 476
N4.C0.D0.R0.S12: Write Level Fine Value = 458
N6.C3.D0.R1.S02: Preamble found at Latency = 008
N0.C3.D0.R1.S00: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N2.C2.D0.R1.S02: Write Level Fine Value = 465
N4.C0.D0.R0.S13: Write Level Fine Value = 428
N6.C3.D0.R1.S05: Preamble found at Latency = 008
N0.C3.D0.R1.S01: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N2.C2.D0.R1.S03: Write Level Fine Value = 449
N4.C0.D0.R0.S14: Write Level Fine Value = 440
N6.C3.D0.R1.S06: Preamble found at Latency = 008
N0.C3.D0.R1.S02: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N2.C2.D0.R1.S04: Write Level Fine Value = 409
N4.C0.D0.R0.S15: Write Level Fine Value = 446
N6.C3.D0.R1.S07: Preamble found at Latency = 008
N0.C3.D0.R1.S03: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N2.C2.D0.R1.S05: Write Level Fine Value = 438
N4.C0.D0.R0.S16: Write Level Fine Value = 462
N6.C3.D0.R1.S00: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N0.C3.D0.R1.S04: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N2.C2.D0.R1.S06: Write Level Fine Value = 434
N4.C0.D0.R0.S17: Write Level Fine Value = 439
N6.C3.D0.R1.S01: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N0.C3.D0.R1.S05: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N2.C2.D0.R1.S07: Write Level Fine Value = 457
N4.C0.D0.R1: ODT Override: 0x6
N6.C3.D0.R1.S02: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N0.C3.D0.R1.S06: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N2.C2.D0.R1.S08: Write Level Fine Value = 426
N4.C0.D0.R1.S00: Write Level Fine Value = 499
N6.C3.D0.R1.S03: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N0.C3.D0.R1.S07: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N2.C2.D0.R1.S09: Write Level Fine Value = 490
N4.C0.D0.R1.S01: Write Level Fine Value = 481
N6.C3.D0.R1.S04: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N0.C3.D0.R1.S08: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N2.C2.D0.R1.S10: Write Level Fine Value = 476
N4.C0.D0.R1.S02: Write Level Fine Value = 471
N6.C3.D0.R1.S05: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N0.C3.D0.R1.S00: Preamble found at Latency = 008
N2.C2.D0.R1.S11: Write Level Fine Value = 467
N4.C0.D0.R1.S03: Write Level Fine Value = 455
N6.C3.D0.R1.S06: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N0.C3.D0.R1.S01: Preamble found at Latency = 008
N2.C2.D0.R1.S12: Write Level Fine Value = 451
N4.C0.D0.R1.S04: Write Level Fine Value = 419
N6.C3.D0.R1.S07: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N0.C3.D0.R1.S02: Preamble found at Latency = 008
N2.C2.D0.R1.S13: Write Level Fine Value = 409
N4.C0.D0.R1.S05: Write Level Fine Value = 438
N6.C3.D0.R1.S08: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N0.C3.D0.R1.S05: Preamble found at Latency = 008
N2.C2.D0.R1.S14: Write Level Fine Value = 438
N4.C0.D0.R1.S06: Write Level Fine Value = 439
N6.C3.D0.R1.S03: Preamble found at Latency = 007
N0.C3.D0.R1.S06: Preamble found at Latency = 008
N2.C2.D0.R1.S15: Write Level Fine Value = 435
N4.C0.D0.R1.S07: Write Level Fine Value = 454
N6.C3.D0.R1.S04: Preamble found at Latency = 007
N0.C3.D0.R1.S07: Preamble found at Latency = 008
N2.C2.D0.R1.S16: Write Level Fine Value = 458
N4.C0.D0.R1.S08: Write Level Fine Value = 432
N6.C3.D0.R1.S08: Preamble found at Latency = 007
N0.C3.D0.R1.S00: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N2.C2.D0.R1.S17: Write Level Fine Value = 426
N4.C0.D0.R1.S09: Write Level Fine Value = 498
N6.C3.D0.R1.S00: Total Receive Enable Delay = 1381
N0.C3.D0.R1.S01: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N2.C2.D1.R0: ODT Override: 0x5
N4.C0.D0.R1.S10: Write Level Fine Value = 481
N6.C3.D0.R1.S01: Total Receive Enable Delay = 1359
N0.C3.D0.R1.S02: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N2.C2.D1.R0.S00: Write Level Fine Value = 498
N4.C0.D0.R1.S11: Write Level Fine Value = 471
N6.C3.D0.R1.S02: Total Receive Enable Delay = 1330
N0.C3.D0.R1.S03: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N2.C2.D1.R0.S01: Write Level Fine Value = 487
N4.C0.D0.R1.S12: Write Level Fine Value = 455
N6.C3.D0.R1.S03: Total Receive Enable Delay = 1306
N0.C3.D0.R1.S04: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N2.C2.D1.R0.S02: Write Level Fine Value = 473
N4.C0.D0.R1.S13: Write Level Fine Value = 421
N6.C3.D0.R1.S04: Total Receive Enable Delay = 1301
N0.C3.D0.R1.S05: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N2.C2.D1.R0.S03: Write Level Fine Value = 463
N4.C0.D0.R1.S14: Write Level Fine Value = 435
N6.C3.D0.R1.S05: Total Receive Enable Delay = 1330
N0.C3.D0.R1.S06: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N2.C2.D1.R0.S04: Write Level Fine Value = 418
N4.C0.D0.R1.S15: Write Level Fine Value = 440
N6.C3.D0.R1.S06: Total Receive Enable Delay = 1352
N0.C3.D0.R1.S07: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N2.C2.D1.R0.S05: Write Level Fine Value = 448
N4.C0.D0.R1.S16: Write Level Fine Value = 455
N6.C3.D0.R1.S07: Total Receive Enable Delay = 1373
N0.C3.D0.R1.S08: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N2.C2.D1.R0.S06: Write Level Fine Value = 444
N4.C0.D0.R1.S17: Write Level Fine Value = 430
N6.C3.D0.R1.S08: Total Receive Enable Delay = 1291
N0.C3.D0.R1.S03: Preamble found at Latency = 007
N2.C2.D1.R0.S07: Write Level Fine Value = 467
N4.C0.D1.R0: ODT Override: 0x5
N6.C3.D0.R1: Starting preamble search upper nibbles
N0.C3.D0.R1.S04: Preamble found at Latency = 007
N2.C2.D1.R0.S08: Write Level Fine Value = 433
N4.C0.D1.R0.S00: Write Level Fine Value = 507
N6.C3.D0.R1.S09: PI = 002, PtrOffset = 005
N0.C3.D0.R1.S08: Preamble found at Latency = 007
N2.C2.D1.R0.S09: Write Level Fine Value = 498
N4.C0.D1.R0.S01: Write Level Fine Value = 494
N6.C3.D0.R1.S10: PI = 049, PtrOffset = 004
N0.C3.D0.R1.S00: Total Receive Enable Delay = 1379
N2.C2.D1.R0.S10: Write Level Fine Value = 487
N4.C0.D1.R0.S02: Write Level Fine Value = 481
N6.C3.D0.R1.S11: PI = 019, PtrOffset = 004
N0.C3.D0.R1.S01: Total Receive Enable Delay = 1356
N2.C2.D1.R0.S11: Write Level Fine Value = 474
N4.C0.D1.R0.S03: Write Level Fine Value = 463
N6.C3.D0.R1.S12: PI = 060, PtrOffset = 005
N0.C3.D0.R1.S02: Total Receive Enable Delay = 1328
N2.C2.D1.R0.S12: Write Level Fine Value = 463
N4.C0.D1.R0.S04: Write Level Fine Value = 430
N6.C3.D0.R1.S13: PI = 054, PtrOffset = 005
N0.C3.D0.R1.S03: Total Receive Enable Delay = 1302
N2.C2.D1.R0.S13: Write Level Fine Value = 419
N4.C0.D1.R0.S05: Write Level Fine Value = 447
N6.C3.D0.R1.S14: PI = 020, PtrOffset = 004
N0.C3.D0.R1.S04: Total Receive Enable Delay = 1299
N2.C2.D1.R0.S14: Write Level Fine Value = 447
N4.C0.D1.R0.S06: Write Level Fine Value = 451
N6.C3.D0.R1.S15: PI = 043, PtrOffset = 004
N0.C3.D0.R1.S05: Total Receive Enable Delay = 1325
N2.C2.D1.R0.S15: Write Level Fine Value = 444
N4.C0.D1.R0.S07: Write Level Fine Value = 465
N6.C3.D0.R1.S16: PI = 062, PtrOffset = 004
N0.C3.D0.R1.S06: Total Receive Enable Delay = 1347
N2.C2.D1.R0.S16: Write Level Fine Value = 467
N4.C0.D1.R0.S08: Write Level Fine Value = 439
N6.C3.D0.R1.S17: PI = 042, PtrOffset = 005
N0.C3.D0.R1.S07: Total Receive Enable Delay = 1369
N2.C2.D1.R0.S17: Write Level Fine Value = 433
N4.C0.D1.R0.S09: Write Level Fine Value = 506
N6.C3.D0.R1.S09: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N0.C3.D0.R1.S08: Total Receive Enable Delay = 1288
N2.C2.D1.R1: ODT Override: 0x9
N4.C0.D1.R0.S10: Write Level Fine Value = 494
N6.C3.D0.R1.S10: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N0.C3.D0.R1: Starting preamble search upper nibbles
N2.C2.D1.R1.S00: Write Level Fine Value = 497
N4.C0.D1.R0.S11: Write Level Fine Value = 480
N6.C3.D0.R1.S11: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N0.C3.D0.R1.S09: PI = 000, PtrOffset = 005
N2.C2.D1.R1.S01: Write Level Fine Value = 481
N4.C0.D1.R0.S12: Write Level Fine Value = 464
N6.C3.D0.R1.S12: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N0.C3.D0.R1.S10: PI = 046, PtrOffset = 004
N2.C2.D1.R1.S02: Write Level Fine Value = 469
N4.C0.D1.R0.S13: Write Level Fine Value = 430
N6.C3.D0.R1.S13: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N0.C3.D0.R1.S11: PI = 016, PtrOffset = 004
N2.C2.D1.R1.S03: Write Level Fine Value = 458
N4.C0.D1.R0.S14: Write Level Fine Value = 447
N6.C3.D0.R1.S14: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N0.C3.D0.R1.S12: PI = 058, PtrOffset = 005
N2.C2.D1.R1.S04: Write Level Fine Value = 413
N4.C0.D1.R0.S15: Write Level Fine Value = 450
N6.C3.D0.R1.S15: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N0.C3.D0.R1.S13: PI = 050, PtrOffset = 005
N2.C2.D1.R1.S05: Write Level Fine Value = 446
N4.C0.D1.R0.S16: Write Level Fine Value = 465
N6.C3.D0.R1.S16: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N0.C3.D0.R1.S14: PI = 014, PtrOffset = 004
N2.C2.D1.R1.S06: Write Level Fine Value = 438
N4.C0.D1.R0.S17: Write Level Fine Value = 439
N6.C3.D0.R1.S17: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N0.C3.D0.R1.S15: PI = 036, PtrOffset = 004
N2.C2.D1.R1.S07: Write Level Fine Value = 465
N4.C0.D1.R1: ODT Override: 0x9
N6.C3.D0.R1.S09: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N0.C3.D0.R1.S16: PI = 061, PtrOffset = 004
N2.C2.D1.R1.S08: Write Level Fine Value = 429
N4.C0.D1.R1.S00: Write Level Fine Value = 504
N6.C3.D0.R1.S10: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N0.C3.D0.R1.S17: PI = 036, PtrOffset = 005
N2.C2.D1.R1.S09: Write Level Fine Value = 495
N4.C0.D1.R1.S01: Write Level Fine Value = 489
N6.C3.D0.R1.S11: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N0.C3.D0.R1.S09: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N2.C2.D1.R1.S10: Write Level Fine Value = 482
N4.C0.D1.R1.S02: Write Level Fine Value = 478
N6.C3.D0.R1.S12: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N0.C3.D0.R1.S10: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N2.C2.D1.R1.S11: Write Level Fine Value = 472
N4.C0.D1.R1.S03: Write Level Fine Value = 461
N6.C3.D0.R1.S13: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N0.C3.D0.R1.S11: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N2.C2.D1.R1.S12: Write Level Fine Value = 457
N4.C0.D1.R1.S04: Write Level Fine Value = 424
N6.C3.D0.R1.S14: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N0.C3.D0.R1.S12: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N2.C2.D1.R1.S13: Write Level Fine Value = 415
N4.C0.D1.R1.S05: Write Level Fine Value = 446
N6.C3.D0.R1.S15: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N0.C3.D0.R1.S13: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N2.C2.D1.R1.S14: Write Level Fine Value = 445
N4.C0.D1.R1.S06: Write Level Fine Value = 447
N6.C3.D0.R1.S16: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N0.C3.D0.R1.S14: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N2.C2.D1.R1.S15: Write Level Fine Value = 439
N4.C0.D1.R1.S07: Write Level Fine Value = 464
N6.C3.D0.R1.S17: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N0.C3.D0.R1.S15: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N2.C2.D1.R1.S16: Write Level Fine Value = 464
N4.C0.D1.R1.S08: Write Level Fine Value = 433
N6.C3.D0.R1.S09: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N0.C3.D0.R1.S16: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N2.C2.D1.R1.S17: Write Level Fine Value = 428
N4.C0.D1.R1.S09: Write Level Fine Value = 505
N6.C3.D0.R1.S10: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N0.C3.D0.R1.S17: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N2.C3.D0.R0: ODT Override: 0x5
N4.C0.D1.R1.S10: Write Level Fine Value = 491
N6.C3.D0.R1.S11: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N0.C3.D0.R1.S09: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N2.C3.D0.R0.S00: Write Level Fine Value = 501
N4.C0.D1.R1.S11: Write Level Fine Value = 479
N6.C3.D0.R1.S12: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N0.C3.D0.R1.S10: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N2.C3.D0.R0.S01: Write Level Fine Value = 488
N4.C0.D1.R1.S12: Write Level Fine Value = 464
N6.C3.D0.R1.S13: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N0.C3.D0.R1.S11: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N2.C3.D0.R0.S02: Write Level Fine Value = 476
N4.C0.D1.R1.S13: Write Level Fine Value = 428
N6.C3.D0.R1.S14: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N0.C3.D0.R1.S12: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N2.C3.D0.R0.S03: Write Level Fine Value = 460
N4.C0.D1.R1.S14: Write Level Fine Value = 443
N6.C3.D0.R1.S15: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N0.C3.D0.R1.S13: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N2.C3.D0.R0.S04: Write Level Fine Value = 427
N4.C0.D1.R1.S15: Write Level Fine Value = 447
N6.C3.D0.R1.S16: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N0.C3.D0.R1.S14: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N2.C3.D0.R0.S05: Write Level Fine Value = 440
N4.C0.D1.R1.S16: Write Level Fine Value = 463
N6.C3.D0.R1.S17: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N0.C3.D0.R1.S15: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N2.C3.D0.R0.S06: Write Level Fine Value = 456
N4.C0.D1.R1.S17: Write Level Fine Value = 433
N6.C3.D0.R1.S09: Preamble found at Latency = 008
N0.C3.D0.R1.S16: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N2.C3.D0.R0.S07: Write Level Fine Value = 471
N4.C1.D0.R0: ODT Override: 0x5
N6.C3.D0.R1.S10: Preamble found at Latency = 008
N0.C3.D0.R1.S17: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N2.C3.D0.R0.S08: Write Level Fine Value = 445
N4.C1.D0.R0.S00: Write Level Fine Value = 506
N6.C3.D0.R1.S11: Preamble found at Latency = 008
N0.C3.D0.R1.S09: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N2.C3.D0.R0.S09: Write Level Fine Value = 504
N4.C1.D0.R0.S01: Write Level Fine Value = 489
N6.C3.D0.R1.S14: Preamble found at Latency = 008
N0.C3.D0.R1.S10: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N2.C3.D0.R0.S10: Write Level Fine Value = 490
N4.C1.D0.R0.S02: Write Level Fine Value = 482
N6.C3.D0.R1.S15: Preamble found at Latency = 008
N0.C3.D0.R1.S11: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N2.C3.D0.R0.S11: Write Level Fine Value = 476
N4.C1.D0.R0.S03: Write Level Fine Value = 469
N6.C3.D0.R1.S16: Preamble found at Latency = 008
N0.C3.D0.R1.S12: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N2.C3.D0.R0.S12: Write Level Fine Value = 462
N4.C1.D0.R0.S04: Write Level Fine Value = 434
N6.C3.D0.R1.S09: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N0.C3.D0.R1.S13: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N2.C3.D0.R0.S13: Write Level Fine Value = 426
N4.C1.D0.R0.S05: Write Level Fine Value = 443
N6.C3.D0.R1.S10: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N0.C3.D0.R1.S14: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N2.C3.D0.R0.S14: Write Level Fine Value = 441
N4.C1.D0.R0.S06: Write Level Fine Value = 462
N6.C3.D0.R1.S11: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N0.C3.D0.R1.S15: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N2.C3.D0.R0.S15: Write Level Fine Value = 455
N4.C1.D0.R0.S07: Write Level Fine Value = 474
N6.C3.D0.R1.S12: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N0.C3.D0.R1.S16: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N2.C3.D0.R0.S16: Write Level Fine Value = 470
N4.C1.D0.R0.S08: Write Level Fine Value = 447
N6.C3.D0.R1.S13: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N0.C3.D0.R1.S17: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N2.C3.D0.R0.S17: Write Level Fine Value = 444
N4.C1.D0.R0.S09: Write Level Fine Value = 508
N6.C3.D0.R1.S14: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N0.C3.D0.R1.S09: Preamble found at Latency = 008
N2.C3.D0.R1: ODT Override: 0x6
N4.C1.D0.R0.S10: Write Level Fine Value = 491
N6.C3.D0.R1.S15: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N0.C3.D0.R1.S10: Preamble found at Latency = 008
N2.C3.D0.R1.S00: Write Level Fine Value = 497
N4.C1.D0.R0.S11: Write Level Fine Value = 484
N6.C3.D0.R1.S16: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N0.C3.D0.R1.S11: Preamble found at Latency = 008
N2.C3.D0.R1.S01: Write Level Fine Value = 479
N4.C1.D0.R0.S12: Write Level Fine Value = 466
N6.C3.D0.R1.S17: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N0.C3.D0.R1.S14: Preamble found at Latency = 008
N2.C3.D0.R1.S02: Write Level Fine Value = 469
N4.C1.D0.R0.S13: Write Level Fine Value = 434
N6.C3.D0.R1.S12: Preamble found at Latency = 007
N0.C3.D0.R1.S15: Preamble found at Latency = 008
N2.C3.D0.R1.S03: Write Level Fine Value = 454
N4.C1.D0.R0.S14: Write Level Fine Value = 445
N6.C3.D0.R1.S13: Preamble found at Latency = 007
N0.C3.D0.R1.S16: Preamble found at Latency = 008
N2.C3.D0.R1.S04: Write Level Fine Value = 420
N4.C1.D0.R0.S15: Write Level Fine Value = 459
N6.C3.D0.R1.S17: Preamble found at Latency = 007
N0.C3.D0.R1.S09: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N2.C3.D0.R1.S05: Write Level Fine Value = 433
N4.C1.D0.R0.S16: Write Level Fine Value = 474
N6.C3.D0.R1: Preamble found for all upper nibbles, adjusting Pi, Offset to center into preamble
N0.C3.D0.R1.S10: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N2.C3.D0.R1.S06: Write Level Fine Value = 448
N4.C1.D0.R0.S17: Write Level Fine Value = 449
N6.C3.D0.R1.S09: Total Receive Enable Delay = 1378
N0.C3.D0.R1.S11: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N2.C3.D0.R1.S07: Write Level Fine Value = 464
N4.C1.D0.R1: ODT Override: 0x6
N6.C3.D0.R1.S10: Total Receive Enable Delay = 1361
N0.C3.D0.R1.S12: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N2.C3.D0.R1.S08: Write Level Fine Value = 437
N4.C1.D0.R1.S00: Write Level Fine Value = 498
N6.C3.D0.R1.S11: Total Receive Enable Delay = 1331
N0.C3.D0.R1.S13: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N2.C3.D0.R1.S09: Write Level Fine Value = 495
N4.C1.D0.R1.S01: Write Level Fine Value = 484
N6.C3.D0.R1.S12: Total Receive Enable Delay = 1308
N0.C3.D0.R1.S14: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N2.C3.D0.R1.S10: Write Level Fine Value = 480
N4.C1.D0.R1.S02: Write Level Fine Value = 474
N6.C3.D0.R1.S13: Total Receive Enable Delay = 1302
N0.C3.D0.R1.S15: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N2.C3.D0.R1.S11: Write Level Fine Value = 470
N4.C1.D0.R1.S03: Write Level Fine Value = 460
N6.C3.D0.R1.S14: Total Receive Enable Delay = 1332
N0.C3.D0.R1.S16: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N2.C3.D0.R1.S12: Write Level Fine Value = 456
N4.C1.D0.R1.S04: Write Level Fine Value = 426
N6.C3.D0.R1.S15: Total Receive Enable Delay = 1355
N0.C3.D0.R1.S17: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N2.C3.D0.R1.S13: Write Level Fine Value = 420
N4.C1.D0.R1.S05: Write Level Fine Value = 438
N6.C3.D0.R1.S16: Total Receive Enable Delay = 1374
N0.C3.D0.R1.S12: Preamble found at Latency = 007
N2.C3.D0.R1.S14: Write Level Fine Value = 434
N4.C1.D0.R1.S06: Write Level Fine Value = 450
N6.C3.D0.R1.S17: Total Receive Enable Delay = 1290
N0.C3.D0.R1.S13: Preamble found at Latency = 007
N2.C3.D0.R1.S15: Write Level Fine Value = 448
N4.C1.D0.R1.S07: Write Level Fine Value = 471
N6.C3.D1.R0: RcvEnFine: Initial RdCmd2RcvEnLatency = 10, Initial RdPtrOffsetRcvEn = 4
N0.C3.D0.R1.S17: Preamble found at Latency = 007
N2.C3.D0.R1.S16: Write Level Fine Value = 466
N4.C1.D0.R1.S08: Write Level Fine Value = 441
N6.C3.D1.R0.S00: Rcv En Fine Value = 309
N0.C3.D0.R1: Preamble found for all upper nibbles, adjusting Pi, Offset to center into preamble
N2.C3.D0.R1.S17: Write Level Fine Value = 437
N4.C1.D0.R1.S09: Write Level Fine Value = 498
N6.C3.D1.R0.S01: Rcv En Fine Value = 288
N0.C3.D0.R1.S09: Total Receive Enable Delay = 1376
N2.C3.D1.R0: ODT Override: 0x5
N4.C1.D0.R1.S10: Write Level Fine Value = 485
N6.C3.D1.R0.S02: Rcv En Fine Value = 262
N0.C3.D0.R1.S10: Total Receive Enable Delay = 1358
N2.C3.D1.R0.S00: Write Level Fine Value = 508
N4.C1.D0.R1.S11: Write Level Fine Value = 475
N6.C3.D1.R0.S03: Rcv En Fine Value = 365
N0.C3.D0.R1.S11: Total Receive Enable Delay = 1328
N2.C3.D1.R0.S01: Write Level Fine Value = 493
N4.C1.D0.R1.S12: Write Level Fine Value = 462
N6.C3.D1.R0.S04: Rcv En Fine Value = 358
N0.C3.D0.R1.S12: Total Receive Enable Delay = 1306
N2.C3.D1.R0.S02: Write Level Fine Value = 481
N4.C1.D0.R1.S13: Write Level Fine Value = 427
N6.C3.D1.R0.S05: Rcv En Fine Value = 261
N0.C3.D0.R1.S13: Total Receive Enable Delay = 1298
N2.C3.D1.R0.S03: Write Level Fine Value = 467
N4.C1.D0.R1.S14: Write Level Fine Value = 440
N6.C3.D1.R0.S06: Rcv En Fine Value = 282
N0.C3.D0.R1.S14: Total Receive Enable Delay = 1326
N2.C3.D1.R0.S04: Write Level Fine Value = 432
N4.C1.D0.R1.S15: Write Level Fine Value = 455
N6.C3.D1.R0.S07: Rcv En Fine Value = 303
N0.C3.D0.R1.S15: Total Receive Enable Delay = 1348
N2.C3.D1.R0.S05: Write Level Fine Value = 446
N4.C1.D0.R1.S16: Write Level Fine Value = 471
N6.C3.D1.R0.S08: Rcv En Fine Value = 346
N0.C3.D0.R1.S16: Total Receive Enable Delay = 1373
N2.C3.D1.R0.S06: Write Level Fine Value = 459
N4.C1.D0.R1.S17: Write Level Fine Value = 440
N6.C3.D1.R0.S09: Rcv En Fine Value = 307
N0.C3.D0.R1.S17: Total Receive Enable Delay = 1284
N2.C3.D1.R0.S07: Write Level Fine Value = 477
N4.C1.D1.R0: ODT Override: 0x5
N6.C3.D1.R0.S10: Rcv En Fine Value = 287
N0.C3.D1.R0: RcvEnFine: Initial RdCmd2RcvEnLatency = 10, Initial RdPtrOffsetRcvEn = 4
N2.C3.D1.R0.S08: Write Level Fine Value = 448
N4.C1.D1.R0.S00: Write Level Fine Value = 511
N6.C3.D1.R0.S11: Rcv En Fine Value = 260
N0.C3.D1.R0.S00: Rcv En Fine Value = 307
N2.C3.D1.R0.S09: Write Level Fine Value = 507
N4.C1.D1.R0.S01: Write Level Fine Value = 495
N6.C3.D1.R0.S12: Rcv En Fine Value = 365
N0.C3.D1.R0.S01: Rcv En Fine Value = 284
N2.C3.D1.R0.S10: Write Level Fine Value = 493
N4.C1.D1.R0.S02: Write Level Fine Value = 484
N6.C3.D1.R0.S13: Rcv En Fine Value = 358
N0.C3.D1.R0.S02: Rcv En Fine Value = 383
N2.C3.D1.R0.S11: Write Level Fine Value = 480
N4.C1.D1.R0.S03: Write Level Fine Value = 468
N6.C3.D1.R0.S14: Rcv En Fine Value = 260
N0.C3.D1.R0.S03: Rcv En Fine Value = 358
N2.C3.D1.R0.S12: Write Level Fine Value = 467
N4.C1.D1.R0.S04: Write Level Fine Value = 434
N6.C3.D1.R0.S15: Rcv En Fine Value = 282
N0.C3.D1.R0.S04: Rcv En Fine Value = 356
N2.C3.D1.R0.S13: Write Level Fine Value = 433
N4.C1.D1.R0.S05: Write Level Fine Value = 447
N6.C3.D1.R0.S16: Rcv En Fine Value = 304
N0.C3.D1.R0.S05: Rcv En Fine Value = 380
N2.C3.D1.R0.S14: Write Level Fine Value = 444
N4.C1.D1.R0.S06: Write Level Fine Value = 462
N6.C3.D1.R0.S17: Rcv En Fine Value = 344
N0.C3.D1.R0.S06: Rcv En Fine Value = 274
N2.C3.D1.R0.S15: Write Level Fine Value = 458
N4.C1.D1.R0.S07: Write Level Fine Value = 478
N6.C3.D1.R0: Starting preamble search lower nibbles
N0.C3.D1.R0.S07: Rcv En Fine Value = 298
N2.C3.D1.R0.S16: Write Level Fine Value = 477
N4.C1.D1.R0.S08: Write Level Fine Value = 447
N6.C3.D1.R0.S00: PI = 053, PtrOffset = 004
N0.C3.D1.R0.S08: Rcv En Fine Value = 341
N2.C3.D1.R0.S17: Write Level Fine Value = 448
N4.C1.D1.R0.S09: Write Level Fine Value = 508
N6.C3.D1.R0.S01: PI = 032, PtrOffset = 004
N0.C3.D1.R0.S09: Rcv En Fine Value = 304
N2.C3.D1.R1: ODT Override: 0x9
N4.C1.D1.R0.S10: Write Level Fine Value = 492
N6.C3.D1.R0.S02: PI = 006, PtrOffset = 004
N0.C3.D1.R0.S10: Rcv En Fine Value = 282
N2.C3.D1.R1.S00: Write Level Fine Value = 505
N4.C1.D1.R0.S11: Write Level Fine Value = 483
N6.C3.D1.R0.S03: PI = 045, PtrOffset = 005
N0.C3.D1.R0.S11: Rcv En Fine Value = 257
N2.C3.D1.R1.S01: Write Level Fine Value = 489
N4.C1.D1.R0.S12: Write Level Fine Value = 468
N6.C3.D1.R0.S04: PI = 038, PtrOffset = 005
N0.C3.D1.R0.S12: Rcv En Fine Value = 362
N2.C3.D1.R1.S02: Write Level Fine Value = 476
N4.C1.D1.R0.S13: Write Level Fine Value = 434
N6.C3.D1.R0.S05: PI = 005, PtrOffset = 004
N0.C3.D1.R0.S13: Rcv En Fine Value = 354
N2.C3.D1.R1.S03: Write Level Fine Value = 464
N4.C1.D1.R0.S14: Write Level Fine Value = 447
N6.C3.D1.R0.S06: PI = 026, PtrOffset = 004
N0.C3.D1.R0.S14: Rcv En Fine Value = 381
N2.C3.D1.R1.S04: Write Level Fine Value = 428
N4.C1.D1.R0.S15: Write Level Fine Value = 462
N6.C3.D1.R0.S07: PI = 047, PtrOffset = 004
N0.C3.D1.R0.S15: Rcv En Fine Value = 276
N2.C3.D1.R1.S05: Write Level Fine Value = 442
N4.C1.D1.R0.S16: Write Level Fine Value = 481
N6.C3.D1.R0.S08: PI = 026, PtrOffset = 005
N0.C3.D1.R0.S16: Rcv En Fine Value = 299
N2.C3.D1.R1.S06: Write Level Fine Value = 455
N4.C1.D1.R0.S17: Write Level Fine Value = 446
N6.C3.D1.R0.S00: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N0.C3.D1.R0.S17: Rcv En Fine Value = 341
N2.C3.D1.R1.S07: Write Level Fine Value = 474
N4.C1.D1.R1: ODT Override: 0x9
N6.C3.D1.R0.S01: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N0.C3.D1.R0: Starting preamble search lower nibbles
N2.C3.D1.R1.S08: Write Level Fine Value = 443
N4.C1.D1.R1.S00: Write Level Fine Value = 506
N6.C3.D1.R0.S02: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N0.C3.D1.R0.S00: PI = 051, PtrOffset = 004
N2.C3.D1.R1.S09: Write Level Fine Value = 504
N4.C1.D1.R1.S01: Write Level Fine Value = 491
N6.C3.D1.R0.S03: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N0.C3.D1.R0.S01: PI = 028, PtrOffset = 004
N2.C3.D1.R1.S10: Write Level Fine Value = 489
N4.C1.D1.R1.S02: Write Level Fine Value = 481
N6.C3.D1.R0.S04: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N0.C3.D1.R0.S02: PI = 063, PtrOffset = 005
N2.C3.D1.R1.S11: Write Level Fine Value = 477
N4.C1.D1.R1.S03: Write Level Fine Value = 467
N6.C3.D1.R0.S05: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N0.C3.D1.R0.S03: PI = 038, PtrOffset = 005
N2.C3.D1.R1.S12: Write Level Fine Value = 464
N4.C1.D1.R1.S04: Write Level Fine Value = 434
N6.C3.D1.R0.S06: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N0.C3.D1.R0.S04: PI = 036, PtrOffset = 005
N2.C3.D1.R1.S13: Write Level Fine Value = 428
N4.C1.D1.R1.S05: Write Level Fine Value = 447
N6.C3.D1.R0.S07: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N0.C3.D1.R0.S05: PI = 060, PtrOffset = 005
N2.C3.D1.R1.S14: Write Level Fine Value = 441
N4.C1.D1.R1.S06: Write Level Fine Value = 457
N6.C3.D1.R0.S08: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N0.C3.D1.R0.S06: PI = 018, PtrOffset = 004
N2.C3.D1.R1.S15: Write Level Fine Value = 455
N4.C1.D1.R1.S07: Write Level Fine Value = 477
N6.C3.D1.R0.S00: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N0.C3.D1.R0.S07: PI = 042, PtrOffset = 004
N2.C3.D1.R1.S16: Write Level Fine Value = 473
N4.C1.D1.R1.S08: Write Level Fine Value = 443
N6.C3.D1.R0.S01: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N0.C3.D1.R0.S08: PI = 021, PtrOffset = 005
N2.C3.D1.R1.S17: Write Level Fine Value = 442
N4.C1.D1.R1.S09: Write Level Fine Value = 505
N6.C3.D1.R0.S02: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N0.C3.D1.R0.S00: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N2: END WRITE LEVEL:
N4.C1.D1.R1.S10: Write Level Fine Value = 490
N6.C3.D1.R0.S03: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N0.C3.D1.R0.S01: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N2: START WRITE LEVEL COARSE:
N4.C1.D1.R1.S11: Write Level Fine Value = 481
N6.C3.D1.R0.S04: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N0.C3.D1.R0.S02: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N4.C1.D1.R1.S12: Write Level Fine Value = 467
N6.C3.D1.R0.S05: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N0.C3.D1.R0.S03: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N4.C1.D1.R1.S13: Write Level Fine Value = 434
N6.C3.D1.R0.S06: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N0.C3.D1.R0.S04: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N4.C1.D1.R1.S14: Write Level Fine Value = 446
N6.C3.D1.R0.S07: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N0.C3.D1.R0.S05: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N4.C1.D1.R1.S15: Write Level Fine Value = 458
N6.C3.D1.R0.S08: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N0.C3.D1.R0.S06: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N2.C0.D0.R0: Write Training Coarse, lower nibbles / bytes
N4.C1.D1.R1.S16: Write Level Fine Value = 475
N6.C3.D1.R0.S00: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N0.C3.D1.R0.S07: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N2.C0.D0.R0.S00: Dq Delay estimate: 467
N4.C1.D1.R1.S17: Write Level Fine Value = 442
N6.C3.D1.R0.S01: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N0.C3.D1.R0.S08: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N2.C0.D0.R0.S01: Dq Delay estimate: 448
N4.C2.D0.R0: ODT Override: 0x5
N6.C3.D1.R0.S02: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N0.C3.D1.R0.S00: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N2.C0.D0.R0.S02: Dq Delay estimate: 437
N4.C2.D0.R0.S00: Write Level Fine Value = 500
N6.C3.D1.R0.S03: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N0.C3.D1.R0.S01: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N2.C0.D0.R0.S03: Dq Delay estimate: 417
N4.C2.D0.R0.S01: Write Level Fine Value = 486
N6.C3.D1.R0.S04: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N0.C3.D1.R0.S02: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N2.C0.D0.R0.S04: Dq Delay estimate: 383
N4.C2.D0.R0.S02: Write Level Fine Value = 477
N6.C3.D1.R0.S05: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N0.C3.D1.R0.S03: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N2.C0.D0.R0.S05: Dq Delay estimate: 402
N4.C2.D0.R0.S03: Write Level Fine Value = 457
N6.C3.D1.R0.S06: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N0.C3.D1.R0.S04: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N2.C0.D0.R0.S06: Dq Delay estimate: 406
N4.C2.D0.R0.S04: Write Level Fine Value = 415
N6.C3.D1.R0.S07: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N0.C3.D1.R0.S05: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N2.C0.D0.R0.S07: Dq Delay estimate: 420
N4.C2.D0.R0.S05: Write Level Fine Value = 446
N6.C3.D1.R0.S08: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N0.C3.D1.R0.S06: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N2.C0.D0.R0.S08: Dq Delay estimate: 396
N4.C2.D0.R0.S06: Write Level Fine Value = 447
N6.C3.D1.R0.S00: Preamble found at Latency = 008
N0.C3.D1.R0.S07: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
ACCM: 0F 0F9F9F9F DF0F0F0F
N4.C2.D0.R0.S07: Write Level Fine Value = 463
N6.C3.D1.R0.S01: Preamble found at Latency = 008
N0.C3.D1.R0.S08: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
ACCM: 0F 0F9F9F9F DF0F0F0F
N4.C2.D0.R0.S08: Write Level Fine Value = 439
N6.C3.D1.R0.S02: Preamble found at Latency = 008
N0.C3.D1.R0.S00: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
ACCM: 0F FF9F9F9F FFFFFFFF
N4.C2.D0.R0.S09: Write Level Fine Value = 503
N6.C3.D1.R0.S05: Preamble found at Latency = 008
N0.C3.D1.R0.S01: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
ACCM: 0F FF9F9F9F FFFFFFFF
N4.C2.D0.R0.S10: Write Level Fine Value = 489
N6.C3.D1.R0.S06: Preamble found at Latency = 008
N0.C3.D1.R0.S02: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N2.C0.D0.R0: CheckMCTest: result = 0x1FFFF
N4.C2.D0.R0.S11: Write Level Fine Value = 477
N6.C3.D1.R0.S07: Preamble found at Latency = 008
N0.C3.D1.R0.S03: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
ACCM: 0F 0FDFDF9F DF0F0F0F
N4.C2.D0.R0.S12: Write Level Fine Value = 458
N6.C3.D1.R0.S00: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N0.C3.D1.R0.S04: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
ACCM: 0F 0FDFDF9F DF0F0F0F
N4.C2.D0.R0.S13: Write Level Fine Value = 418
N6.C3.D1.R0.S01: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N0.C3.D1.R0.S05: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
ACCM: 0F FFDFDF9F FFFFFFFF
N4.C2.D0.R0.S14: Write Level Fine Value = 446
N6.C3.D1.R0.S02: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N0.C3.D1.R0.S06: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
ACCM: 0F FFDFDF9F FFFFFFFF
N4.C2.D0.R0.S15: Write Level Fine Value = 446
N6.C3.D1.R0.S03: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N0.C3.D1.R0.S07: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N2.C0.D0.R0: CheckMCTest: result = 0x1FFFF
N4.C2.D0.R0.S16: Write Level Fine Value = 464
N6.C3.D1.R0.S04: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N0.C3.D1.R0.S08: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
ACCM: 0F 0FDFDFDF DF0F0F0F
N4.C2.D0.R0.S17: Write Level Fine Value = 435
N6.C3.D1.R0.S05: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N0.C3.D1.R0.S00: Preamble found at Latency = 008
ACCM: 0F 0FDFDFDF DF0F0F0F
N4.C2.D0.R1: ODT Override: 0x6
N6.C3.D1.R0.S06: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N0.C3.D1.R0.S01: Preamble found at Latency = 008
ACCM: 0B FBDBD0D0 FBF0F0F0
N4.C2.D0.R1.S00: Write Level Fine Value = 495
N6.C3.D1.R0.S07: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N0.C3.D1.R0.S06: Preamble found at Latency = 008
ACCM: 0B FBDBD0D0 FBF0F0F0
N4.C2.D0.R1.S01: Write Level Fine Value = 478
N6.C3.D1.R0.S08: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N0.C3.D1.R0.S07: Preamble found at Latency = 008
N2.C0.D0.R0: CheckMCTest: result = 0x1FFFF
N4.C2.D0.R1.S02: Write Level Fine Value = 469
N6.C3.D1.R0.S03: Preamble found at Latency = 007
N0.C3.D1.R0.S00: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
ACCM: 0F 0FDFDFDF DF0F0F0F
N4.C2.D0.R1.S03: Write Level Fine Value = 454
N6.C3.D1.R0.S04: Preamble found at Latency = 007
N0.C3.D1.R0.S01: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
ACCM: 0F 0FDFDFDF DF0F0F0F
N4.C2.D0.R1.S04: Write Level Fine Value = 411
N6.C3.D1.R0.S08: Preamble found at Latency = 007
N0.C3.D1.R0.S02: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
ACCM: 0B FFDFD0DD FBF0F0FD
N4.C2.D0.R1.S05: Write Level Fine Value = 439
N6.C3.D1.R0.S00: Total Receive Enable Delay = 1365
N0.C3.D1.R0.S03: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
ACCM: 0B FFDFD0DD FBF0F0FD
N4.C2.D0.R1.S06: Write Level Fine Value = 436
N6.C3.D1.R0.S01: Total Receive Enable Delay = 1344
N0.C3.D1.R0.S04: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N2.C0.D0.R0: CheckMCTest: result = 0x1FFFF
N4.C2.D0.R1.S07: Write Level Fine Value = 459
N6.C3.D1.R0.S02: Total Receive Enable Delay = 1318
N0.C3.D1.R0.S05: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
ACCM: 00 00D0D0D0 D0000000
N4.C2.D0.R1.S08: Write Level Fine Value = 430
N6.C3.D1.R0.S03: Total Receive Enable Delay = 1293
N0.C3.D1.R0.S06: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
ACCM: 00 00D0D0D0 D0000000
N4.C2.D0.R1.S09: Write Level Fine Value = 495
N6.C3.D1.R0.S04: Total Receive Enable Delay = 1286
N0.C3.D1.R0.S07: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
ACCM: 00 F0D0D0D0 F0F0F0F0
N4.C2.D0.R1.S10: Write Level Fine Value = 481
N6.C3.D1.R0.S05: Total Receive Enable Delay = 1317
N0.C3.D1.R0.S08: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
ACCM: 00 F0D0D0D0 F0F0F0F0
N4.C2.D0.R1.S11: Write Level Fine Value = 469
N6.C3.D1.R0.S06: Total Receive Enable Delay = 1338
N0.C3.D1.R0.S02: Preamble found at Latency = 007
N2.C0.D0.R0: CheckMCTest: result = 0x1FE00
N4.C2.D0.R1.S12: Write Level Fine Value = 455
N6.C3.D1.R0.S07: Total Receive Enable Delay = 1359
N0.C3.D1.R0.S03: Preamble found at Latency = 007
ACCM: 00 00D0D0D0 D0000000
N4.C2.D0.R1.S13: Write Level Fine Value = 412
N6.C3.D1.R0.S08: Total Receive Enable Delay = 1274
N0.C3.D1.R0.S04: Preamble found at Latency = 007
ACCM: 00 00D0D0D0 D0000000
N4.C2.D0.R1.S14: Write Level Fine Value = 440
N6.C3.D1.R0: Starting preamble search upper nibbles
N0.C3.D1.R0.S05: Preamble found at Latency = 007
ACCM: 00 F0D0D0D0 F0F0F0F0
N4.C2.D0.R1.S15: Write Level Fine Value = 437
N6.C3.D1.R0.S09: PI = 051, PtrOffset = 004
N0.C3.D1.R0.S08: Preamble found at Latency = 007
ACCM: 00 F0D0D0D0 F0F0F0F0
N4.C2.D0.R1.S16: Write Level Fine Value = 457
N6.C3.D1.R0.S10: PI = 031, PtrOffset = 004
N0.C3.D1.R0.S00: Total Receive Enable Delay = 1363
N2.C0.D0.R0: CheckMCTest: result = 0x1FE00
N4.C2.D0.R1.S17: Write Level Fine Value = 429
N6.C3.D1.R0.S11: PI = 004, PtrOffset = 004
N0.C3.D1.R0.S01: Total Receive Enable Delay = 1340
N2.C0.D0.R0.S00: Offset Found: RdPtrOffsetDqs = 007
N4.C2.D1.R0: ODT Override: 0x5
N6.C3.D1.R0.S12: PI = 045, PtrOffset = 005
N0.C3.D1.R0.S02: Total Receive Enable Delay = 1311
N2.C0.D0.R0.S01: Offset Found: RdPtrOffsetDqs = 007
N4.C2.D1.R0.S00: Write Level Fine Value = 504
N6.C3.D1.R0.S13: PI = 038, PtrOffset = 005
N0.C3.D1.R0.S03: Total Receive Enable Delay = 1286
N2.C0.D0.R0.S02: Offset Found: RdPtrOffsetDqs = 007
N4.C2.D1.R0.S01: Write Level Fine Value = 489
N6.C3.D1.R0.S14: PI = 004, PtrOffset = 004
N0.C3.D1.R0.S04: Total Receive Enable Delay = 1284
N2.C0.D0.R0.S03: Offset Found: RdPtrOffsetDqs = 007
N4.C2.D1.R0.S02: Write Level Fine Value = 480
N6.C3.D1.R0.S15: PI = 026, PtrOffset = 004
N0.C3.D1.R0.S05: Total Receive Enable Delay = 1308
N2.C0.D0.R0.S04: Offset Found: RdPtrOffsetDqs = 006
N4.C2.D1.R0.S03: Write Level Fine Value = 464
N6.C3.D1.R0.S16: PI = 048, PtrOffset = 004
N0.C3.D1.R0.S06: Total Receive Enable Delay = 1330
N2.C0.D0.R0.S05: Offset Found: RdPtrOffsetDqs = 006
N4.C2.D1.R0.S04: Write Level Fine Value = 421
N6.C3.D1.R0.S17: PI = 024, PtrOffset = 005
N0.C3.D1.R0.S07: Total Receive Enable Delay = 1354
N2.C0.D0.R0.S06: Offset Found: RdPtrOffsetDqs = 006
N4.C2.D1.R0.S05: Write Level Fine Value = 450
N6.C3.D1.R0.S09: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N0.C3.D1.R0.S08: Total Receive Enable Delay = 1269
N2.C0.D0.R0.S07: Offset Found: RdPtrOffsetDqs = 007
N4.C2.D1.R0.S06: Write Level Fine Value = 449
N6.C3.D1.R0.S10: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N0.C3.D1.R0: Starting preamble search upper nibbles
N2.C0.D0.R0.S08: Offset Found: RdPtrOffsetDqs = 006
N4.C2.D1.R0.S07: Write Level Fine Value = 467
N6.C3.D1.R0.S11: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N0.C3.D1.R0.S09: PI = 048, PtrOffset = 004
N2.C0.D0.R0: Write Training Coarse, upper nibbles
N4.C2.D1.R0.S08: Write Level Fine Value = 439
N6.C3.D1.R0.S12: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N0.C3.D1.R0.S10: PI = 026, PtrOffset = 004
N2.C0.D0.R0.S09: Dq Delay estimate: 470
N4.C2.D1.R0.S09: Write Level Fine Value = 505
N6.C3.D1.R0.S13: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N0.C3.D1.R0.S11: PI = 001, PtrOffset = 004
N2.C0.D0.R0.S10: Dq Delay estimate: 448
N4.C2.D1.R0.S10: Write Level Fine Value = 491
N6.C3.D1.R0.S14: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N0.C3.D1.R0.S12: PI = 042, PtrOffset = 005
N2.C0.D0.R0.S11: Dq Delay estimate: 435
N4.C2.D1.R0.S11: Write Level Fine Value = 480
N6.C3.D1.R0.S15: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N0.C3.D1.R0.S13: PI = 034, PtrOffset = 005
N2.C0.D0.R0.S12: Dq Delay estimate: 418
N4.C2.D1.R0.S12: Write Level Fine Value = 464
N6.C3.D1.R0.S16: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N0.C3.D1.R0.S14: PI = 061, PtrOffset = 005
N2.C0.D0.R0.S13: Dq Delay estimate: 387
N4.C2.D1.R0.S13: Write Level Fine Value = 422
N6.C3.D1.R0.S17: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N0.C3.D1.R0.S15: PI = 020, PtrOffset = 004
N2.C0.D0.R0.S14: Dq Delay estimate: 404
N4.C2.D1.R0.S14: Write Level Fine Value = 449
N6.C3.D1.R0.S09: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N0.C3.D1.R0.S16: PI = 043, PtrOffset = 004
N2.C0.D0.R0.S15: Dq Delay estimate: 406
N4.C2.D1.R0.S15: Write Level Fine Value = 449
N6.C3.D1.R0.S10: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N0.C3.D1.R0.S17: PI = 021, PtrOffset = 005
N2.C0.D0.R0.S16: Dq Delay estimate: 420
N4.C2.D1.R0.S16: Write Level Fine Value = 469
N6.C3.D1.R0.S11: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N0.C3.D1.R0.S09: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N2.C0.D0.R0.S17: Dq Delay estimate: 398
N4.C2.D1.R0.S17: Write Level Fine Value = 438
N6.C3.D1.R0.S12: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N0.C3.D1.R0.S10: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
ACCM: F0 F0F0F0F0 F0F0F0F0
N4.C2.D1.R1: ODT Override: 0x9
N6.C3.D1.R0.S13: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N0.C3.D1.R0.S11: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
ACCM: F0 F0F0F0F0 F0F0F0F0
N4.C2.D1.R1.S00: Write Level Fine Value = 499
N6.C3.D1.R0.S14: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N0.C3.D1.R0.S12: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
ACCM: F0 F0F0F0F0 F0F0F0F0
N4.C2.D1.R1.S01: Write Level Fine Value = 486
N6.C3.D1.R0.S15: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N0.C3.D1.R0.S13: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
ACCM: F0 F0F0F0F0 F0F0F0F0
N4.C2.D1.R1.S02: Write Level Fine Value = 476
N6.C3.D1.R0.S16: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N0.C3.D1.R0.S14: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N2.C0.D0.R0: CheckMCTest: result = 0x3FE00
N4.C2.D1.R1.S03: Write Level Fine Value = 462
N6.C3.D1.R0.S17: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N0.C3.D1.R0.S15: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
ACCM: F0 F0F0F0F0 F0F0F0F0
N4.C2.D1.R1.S04: Write Level Fine Value = 419
N6.C3.D1.R0.S09: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N0.C3.D1.R0.S16: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
ACCM: F0 F0F0F0F0 F0F0F0F0
N4.C2.D1.R1.S05: Write Level Fine Value = 448
N6.C3.D1.R0.S10: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N0.C3.D1.R0.S17: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
ACCM: F0 F0F0F0F0 F0F0F0F0
N4.C2.D1.R1.S06: Write Level Fine Value = 443
N6.C3.D1.R0.S11: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N0.C3.D1.R0.S09: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
ACCM: F0 F0F0F0F0 F0F0F0F0
N4.C2.D1.R1.S07: Write Level Fine Value = 465
N6.C3.D1.R0.S12: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N0.C3.D1.R0.S10: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N2.C0.D0.R0: CheckMCTest: result = 0x3FE00
N4.C2.D1.R1.S08: Write Level Fine Value = 434
N6.C3.D1.R0.S13: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N0.C3.D1.R0.S11: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
ACCM: F0 F0F0F0F0 F0F0F0F0
N4.C2.D1.R1.S09: Write Level Fine Value = 499
N6.C3.D1.R0.S14: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N0.C3.D1.R0.S12: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
ACCM: F0 F0F0F0F0 F0F0F0F0
N4.C2.D1.R1.S10: Write Level Fine Value = 489
N6.C3.D1.R0.S15: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N0.C3.D1.R0.S13: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
ACCM: 00 00B00000 B0000000
N4.C2.D1.R1.S11: Write Level Fine Value = 476
N6.C3.D1.R0.S16: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N0.C3.D1.R0.S14: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
ACCM: 00 00B00000 B0000000
N4.C2.D1.R1.S12: Write Level Fine Value = 462
N6.C3.D1.R0.S17: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N0.C3.D1.R0.S15: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N2.C0.D0.R0: CheckMCTest: result = 0x3FE00
N4.C2.D1.R1.S13: Write Level Fine Value = 419
N6.C3.D1.R0.S09: Preamble found at Latency = 008
N0.C3.D1.R0.S16: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
ACCM: F0 F0F0F0F0 F0F0F0F0
N4.C2.D1.R1.S14: Write Level Fine Value = 448
N6.C3.D1.R0.S10: Preamble found at Latency = 008
N0.C3.D1.R0.S17: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
ACCM: F0 F0F0F0F0 F0F0F0F0
N4.C2.D1.R1.S15: Write Level Fine Value = 447
N6.C3.D1.R0.S11: Preamble found at Latency = 008
N0.C3.D1.R0.S09: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
ACCM: 00 00F00000 F0000000
N4.C2.D1.R1.S16: Write Level Fine Value = 465
N6.C3.D1.R0.S14: Preamble found at Latency = 008
N0.C3.D1.R0.S10: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
ACCM: 00 00F00000 F0000000
N4.C2.D1.R1.S17: Write Level Fine Value = 432
N6.C3.D1.R0.S15: Preamble found at Latency = 008
N0.C3.D1.R0.S11: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N2.C0.D0.R0: CheckMCTest: result = 0x3FE00
N4.C3.D0.R0: ODT Override: 0x5
N6.C3.D1.R0.S16: Preamble found at Latency = 008
N0.C3.D1.R0.S12: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N2.C0.D0.R0: CheckMCTest: passed
N4.C3.D0.R0.S00: Write Level Fine Value = 385
N6.C3.D1.R0.S09: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N0.C3.D1.R0.S13: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N2.C0.D0.R0: CheckMCTest: passed
N4.C3.D0.R0.S01: Write Level Fine Value = 496
N6.C3.D1.R0.S10: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N0.C3.D1.R0.S14: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N2.C0.D0.R0.S09: Offset Found: RdPtrOffsetDqs = 007
N4.C3.D0.R0.S02: Write Level Fine Value = 486
N6.C3.D1.R0.S11: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N0.C3.D1.R0.S15: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N2.C0.D0.R0.S10: Offset Found: RdPtrOffsetDqs = 007
N4.C3.D0.R0.S03: Write Level Fine Value = 470
N6.C3.D1.R0.S12: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N0.C3.D1.R0.S16: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N2.C0.D0.R0.S11: Offset Found: RdPtrOffsetDqs = 007
N4.C3.D0.R0.S04: Write Level Fine Value = 434
N6.C3.D1.R0.S13: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N0.C3.D1.R0.S17: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N2.C0.D0.R0.S12: Offset Found: RdPtrOffsetDqs = 007
N4.C3.D0.R0.S05: Write Level Fine Value = 449
N6.C3.D1.R0.S14: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N0.C3.D1.R0.S09: Preamble found at Latency = 008
N2.C0.D0.R0.S13: Offset Found: RdPtrOffsetDqs = 006
N4.C3.D0.R0.S06: Write Level Fine Value = 464
N6.C3.D1.R0.S15: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N0.C3.D1.R0.S10: Preamble found at Latency = 008
N2.C0.D0.R0.S14: Offset Found: RdPtrOffsetDqs = 006
N4.C3.D0.R0.S07: Write Level Fine Value = 478
N6.C3.D1.R0.S16: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N0.C3.D1.R0.S11: Preamble found at Latency = 008
N2.C0.D0.R0.S15: Offset Found: RdPtrOffsetDqs = 006
N4.C3.D0.R0.S08: Write Level Fine Value = 454
N6.C3.D1.R0.S17: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N0.C3.D1.R0.S15: Preamble found at Latency = 008
N2.C0.D0.R0.S16: Offset Found: RdPtrOffsetDqs = 007
N4.C3.D0.R0.S09: Write Level Fine Value = 385
N6.C3.D1.R0.S12: Preamble found at Latency = 007
N0.C3.D1.R0.S16: Preamble found at Latency = 008
N2.C0.D0.R0.S17: Offset Found: RdPtrOffsetDqs = 006
N4.C3.D0.R0.S10: Write Level Fine Value = 495
N6.C3.D1.R0.S13: Preamble found at Latency = 007
N0.C3.D1.R0.S09: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N2.C0.D0.R1: Write Training Coarse, lower nibbles / bytes
N4.C3.D0.R0.S11: Write Level Fine Value = 484
N6.C3.D1.R0.S17: Preamble found at Latency = 007
N0.C3.D1.R0.S10: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N2.C0.D0.R1.S00: Dq Delay estimate: 460
N4.C3.D0.R0.S12: Write Level Fine Value = 472
N6.C3.D1.R0: Preamble found for all upper nibbles, adjusting Pi, Offset to center into preamble
N0.C3.D1.R0.S11: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N2.C0.D0.R1.S01: Dq Delay estimate: 442
N4.C3.D0.R0.S13: Write Level Fine Value = 435
N6.C3.D1.R0.S09: Total Receive Enable Delay = 1363
N0.C3.D1.R0.S12: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N2.C0.D0.R1.S02: Dq Delay estimate: 429
N4.C3.D0.R0.S14: Write Level Fine Value = 448
N6.C3.D1.R0.S10: Total Receive Enable Delay = 1343
N0.C3.D1.R0.S13: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N2.C0.D0.R1.S03: Dq Delay estimate: 409
N4.C3.D0.R0.S15: Write Level Fine Value = 465
N6.C3.D1.R0.S11: Total Receive Enable Delay = 1316
N0.C3.D1.R0.S14: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N2.C0.D0.R1.S04: Dq Delay estimate: 376
N4.C3.D0.R0.S16: Write Level Fine Value = 478
N6.C3.D1.R0.S12: Total Receive Enable Delay = 1293
N0.C3.D1.R0.S15: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N2.C0.D0.R1.S05: Dq Delay estimate: 396
N4.C3.D0.R0.S17: Write Level Fine Value = 450
N6.C3.D1.R0.S13: Total Receive Enable Delay = 1286
N0.C3.D1.R0.S16: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N2.C0.D0.R1.S06: Dq Delay estimate: 400
N4.C3.D0.R1: ODT Override: 0x6
N6.C3.D1.R0.S14: Total Receive Enable Delay = 1316
N0.C3.D1.R0.S17: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N2.C0.D0.R1.S07: Dq Delay estimate: 414
N4.C3.D0.R1.S00: Write Level Fine Value = 506
N6.C3.D1.R0.S15: Total Receive Enable Delay = 1338
N0.C3.D1.R0.S12: Preamble found at Latency = 007
N2.C0.D0.R1.S08: Dq Delay estimate: 388
N4.C3.D0.R1.S01: Write Level Fine Value = 490
N6.C3.D1.R0.S16: Total Receive Enable Delay = 1360
N0.C3.D1.R0.S13: Preamble found at Latency = 007
ACCM: 0F 0F0F0F0F 0F0F0F0F
N4.C3.D0.R1.S02: Write Level Fine Value = 476
N6.C3.D1.R0.S17: Total Receive Enable Delay = 1272
N0.C3.D1.R0.S14: Preamble found at Latency = 007
ACCM: 0F 0F0F0F0F 0F0F0F0F
N4.C3.D0.R1.S03: Write Level Fine Value = 465
N6.C3.D1.R1: RcvEnFine: Initial RdCmd2RcvEnLatency = 10, Initial RdPtrOffsetRcvEn = 4
N0.C3.D1.R0.S17: Preamble found at Latency = 007
ACCM: 0F 0F0F0F0F 0F0F0F0F
N4.C3.D0.R1.S04: Write Level Fine Value = 427
N6.C3.D1.R1.S00: Rcv En Fine Value = 310
N0.C3.D1.R0: Preamble found for all upper nibbles, adjusting Pi, Offset to center into preamble
ACCM: 0F 0F0F0F0F 0F0F0F0F
N4.C3.D0.R1.S05: Write Level Fine Value = 440
N6.C3.D1.R1.S01: Rcv En Fine Value = 287
N0.C3.D1.R0.S09: Total Receive Enable Delay = 1360
N2.C0.D0.R1: CheckMCTest: result = 0x1FF
N4.C3.D0.R1.S06: Write Level Fine Value = 456
N6.C3.D1.R1.S02: Rcv En Fine Value = 260
N0.C3.D1.R0.S10: Total Receive Enable Delay = 1338
ACCM: 0F 0F0F0F0F 0F0F0F0F
N4.C3.D0.R1.S07: Write Level Fine Value = 472
N6.C3.D1.R1.S03: Rcv En Fine Value = 365
N0.C3.D1.R0.S11: Total Receive Enable Delay = 1313
ACCM: 0F 0F0F0F0F 0F0F0F0F
N4.C3.D0.R1.S08: Write Level Fine Value = 443
N6.C3.D1.R1.S04: Rcv En Fine Value = 358
N0.C3.D1.R0.S12: Total Receive Enable Delay = 1290
ACCM: 0F 0F0F0F0F 0F0F0F0F
N4.C3.D0.R1.S09: Write Level Fine Value = 505
N6.C3.D1.R1.S05: Rcv En Fine Value = 257
N0.C3.D1.R0.S13: Total Receive Enable Delay = 1282
ACCM: 0F 0F0F0F0F 0F0F0F0F
N4.C3.D0.R1.S10: Write Level Fine Value = 490
N6.C3.D1.R1.S06: Rcv En Fine Value = 282
N0.C3.D1.R0.S14: Total Receive Enable Delay = 1309
N2.C0.D0.R1: CheckMCTest: result = 0x1FF
N4.C3.D0.R1.S11: Write Level Fine Value = 477
N6.C3.D1.R1.S07: Rcv En Fine Value = 302
N0.C3.D1.R0.S15: Total Receive Enable Delay = 1332
ACCM: 0F 0F0F0F0F 0F0F0F0F
N4.C3.D0.R1.S12: Write Level Fine Value = 467
N6.C3.D1.R1.S08: Rcv En Fine Value = 346
N0.C3.D1.R0.S16: Total Receive Enable Delay = 1355
ACCM: 0F 0F0F0F0F 0F0F0F0F
N4.C3.D0.R1.S13: Write Level Fine Value = 427
N6.C3.D1.R1.S09: Rcv En Fine Value = 307
N0.C3.D1.R0.S17: Total Receive Enable Delay = 1269
ACCM: 00 0000000B 00000B00
N4.C3.D0.R1.S14: Write Level Fine Value = 442
N6.C3.D1.R1.S10: Rcv En Fine Value = 288
N0.C3.D1.R1: RcvEnFine: Initial RdCmd2RcvEnLatency = 10, Initial RdPtrOffsetRcvEn = 4
ACCM: 00 0000000B 00000B00
N4.C3.D0.R1.S15: Write Level Fine Value = 457
N6.C3.D1.R1.S11: Rcv En Fine Value = 261
N0.C3.D1.R1.S00: Rcv En Fine Value = 304
N2.C0.D0.R1: CheckMCTest: result = 0x1FF
N4.C3.D0.R1.S16: Write Level Fine Value = 473
N6.C3.D1.R1.S12: Rcv En Fine Value = 366
N0.C3.D1.R1.S01: Rcv En Fine Value = 284
ACCM: 0F 0F0F0F0F 0F0F0F0F
N4.C3.D0.R1.S17: Write Level Fine Value = 443
N6.C3.D1.R1.S13: Rcv En Fine Value = 358
N0.C3.D1.R1.S02: Rcv En Fine Value = 381
ACCM: 0F 0F0F0F0F 0F0F0F0F
N4.C3.D1.R0: ODT Override: 0x5
N6.C3.D1.R1.S14: Rcv En Fine Value = 262
N0.C3.D1.R1.S03: Rcv En Fine Value = 358
ACCM: 00 0000000B 00000F00
N4.C3.D1.R0.S00: Write Level Fine Value = 388
N6.C3.D1.R1.S15: Rcv En Fine Value = 285
N0.C3.D1.R1.S04: Rcv En Fine Value = 353
ACCM: 00 0000000B 00000F00
N4.C3.D1.R0.S01: Write Level Fine Value = 503
N6.C3.D1.R1.S16: Rcv En Fine Value = 304
N0.C3.D1.R1.S05: Rcv En Fine Value = 381
N2.C0.D0.R1: CheckMCTest: result = 0x1FF
N4.C3.D1.R0.S02: Write Level Fine Value = 490
N6.C3.D1.R1.S17: Rcv En Fine Value = 346
N0.C3.D1.R1.S06: Rcv En Fine Value = 274
N2.C0.D0.R1: CheckMCTest: passed
N4.C3.D1.R0.S03: Write Level Fine Value = 475
N6.C3.D1.R1: Starting preamble search lower nibbles
N0.C3.D1.R1.S07: Rcv En Fine Value = 297
N2.C0.D0.R1: CheckMCTest: passed
N4.C3.D1.R0.S04: Write Level Fine Value = 441
N6.C3.D1.R1.S00: PI = 054, PtrOffset = 004
N0.C3.D1.R1.S08: Rcv En Fine Value = 342
N2.C0.D0.R1.S00: Offset Found: RdPtrOffsetDqs = 007
N4.C3.D1.R0.S05: Write Level Fine Value = 451
N6.C3.D1.R1.S01: PI = 031, PtrOffset = 004
N0.C3.D1.R1.S09: Rcv En Fine Value = 305
N2.C0.D0.R1.S01: Offset Found: RdPtrOffsetDqs = 007
N4.C3.D1.R0.S06: Write Level Fine Value = 469
N6.C3.D1.R1.S02: PI = 004, PtrOffset = 004
N0.C3.D1.R1.S10: Rcv En Fine Value = 283
N2.C0.D0.R1.S02: Offset Found: RdPtrOffsetDqs = 007
N4.C3.D1.R0.S07: Write Level Fine Value = 484
N6.C3.D1.R1.S03: PI = 045, PtrOffset = 005
N0.C3.D1.R1.S11: Rcv En Fine Value = 383
N2.C0.D0.R1.S03: Offset Found: RdPtrOffsetDqs = 006
N4.C3.D1.R0.S08: Write Level Fine Value = 455
N6.C3.D1.R1.S04: PI = 038, PtrOffset = 005
N0.C3.D1.R1.S12: Rcv En Fine Value = 362
N2.C0.D0.R1.S04: Offset Found: RdPtrOffsetDqs = 006
N4.C3.D1.R0.S09: Write Level Fine Value = 388
N6.C3.D1.R1.S05: PI = 001, PtrOffset = 004
N0.C3.D1.R1.S13: Rcv En Fine Value = 355
N2.C0.D0.R1.S05: Offset Found: RdPtrOffsetDqs = 006
N4.C3.D1.R0.S10: Write Level Fine Value = 504
N6.C3.D1.R1.S06: PI = 026, PtrOffset = 004
N0.C3.D1.R1.S14: Rcv En Fine Value = 381
N2.C0.D0.R1.S06: Offset Found: RdPtrOffsetDqs = 006
N4.C3.D1.R0.S11: Write Level Fine Value = 490
N6.C3.D1.R1.S07: PI = 046, PtrOffset = 004
N0.C3.D1.R1.S15: Rcv En Fine Value = 275
N2.C0.D0.R1.S07: Offset Found: RdPtrOffsetDqs = 007
N4.C3.D1.R0.S12: Write Level Fine Value = 479
N6.C3.D1.R1.S08: PI = 026, PtrOffset = 005
N0.C3.D1.R1.S16: Rcv En Fine Value = 300
N2.C0.D0.R1.S08: Offset Found: RdPtrOffsetDqs = 006
N4.C3.D1.R0.S13: Write Level Fine Value = 439
N6.C3.D1.R1.S00: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N0.C3.D1.R1.S17: Rcv En Fine Value = 340
N2.C0.D0.R1: Write Training Coarse, upper nibbles
N4.C3.D1.R0.S14: Write Level Fine Value = 455
N6.C3.D1.R1.S01: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N0.C3.D1.R1: Starting preamble search lower nibbles
N2.C0.D0.R1.S09: Dq Delay estimate: 457
N4.C3.D1.R0.S15: Write Level Fine Value = 468
N6.C3.D1.R1.S02: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N0.C3.D1.R1.S00: PI = 048, PtrOffset = 004
N2.C0.D0.R1.S10: Dq Delay estimate: 441
N4.C3.D1.R0.S16: Write Level Fine Value = 484
N6.C3.D1.R1.S03: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N0.C3.D1.R1.S01: PI = 028, PtrOffset = 004
N2.C0.D0.R1.S11: Dq Delay estimate: 431
N4.C3.D1.R0.S17: Write Level Fine Value = 456
N6.C3.D1.R1.S04: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N0.C3.D1.R1.S02: PI = 061, PtrOffset = 005
N2.C0.D0.R1.S12: Dq Delay estimate: 414
N4.C3.D1.R1: ODT Override: 0x9
N6.C3.D1.R1.S05: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N0.C3.D1.R1.S03: PI = 038, PtrOffset = 005
N2.C0.D0.R1.S13: Dq Delay estimate: 378
N4.C3.D1.R1.S00: Write Level Fine Value = 387
N6.C3.D1.R1.S06: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N0.C3.D1.R1.S04: PI = 033, PtrOffset = 005
N2.C0.D0.R1.S14: Dq Delay estimate: 398
N4.C3.D1.R1.S01: Write Level Fine Value = 499
N6.C3.D1.R1.S07: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N0.C3.D1.R1.S05: PI = 061, PtrOffset = 005
N2.C0.D0.R1.S15: Dq Delay estimate: 401
N4.C3.D1.R1.S02: Write Level Fine Value = 486
N6.C3.D1.R1.S08: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N0.C3.D1.R1.S06: PI = 018, PtrOffset = 004
N2.C0.D0.R1.S16: Dq Delay estimate: 415
N4.C3.D1.R1.S03: Write Level Fine Value = 475
N6.C3.D1.R1.S00: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N0.C3.D1.R1.S07: PI = 041, PtrOffset = 004
N2.C0.D0.R1.S17: Dq Delay estimate: 389
N4.C3.D1.R1.S04: Write Level Fine Value = 437
N6.C3.D1.R1.S01: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N0.C3.D1.R1.S08: PI = 022, PtrOffset = 005
ACCM: F0 F0F0F0F0 F0F0F0F0
N4.C3.D1.R1.S05: Write Level Fine Value = 450
N6.C3.D1.R1.S02: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N0.C3.D1.R1.S00: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
ACCM: F0 F0F0F0F0 F0F0F0F0
N4.C3.D1.R1.S06: Write Level Fine Value = 464
N6.C3.D1.R1.S03: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N0.C3.D1.R1.S01: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
ACCM: F0 F0F0F0F0 F0F0F0F0
N4.C3.D1.R1.S07: Write Level Fine Value = 481
N6.C3.D1.R1.S04: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N0.C3.D1.R1.S02: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
ACCM: F0 F0F0F0F0 F0F0F0F0
N4.C3.D1.R1.S08: Write Level Fine Value = 451
N6.C3.D1.R1.S05: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N0.C3.D1.R1.S03: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N2.C0.D0.R1: CheckMCTest: result = 0x3FE00
N4.C3.D1.R1.S09: Write Level Fine Value = 385
N6.C3.D1.R1.S06: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N0.C3.D1.R1.S04: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
ACCM: F0 F0F0F0F0 F0F0F0F0
N4.C3.D1.R1.S10: Write Level Fine Value = 499
N6.C3.D1.R1.S07: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N0.C3.D1.R1.S05: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
ACCM: F0 F0F0F0F0 F0F0F0F0
N4.C3.D1.R1.S11: Write Level Fine Value = 488
N6.C3.D1.R1.S08: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N0.C3.D1.R1.S06: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
ACCM: F0 F0F0F0F0 F0F0F0F0
N4.C3.D1.R1.S12: Write Level Fine Value = 476
N6.C3.D1.R1.S00: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N0.C3.D1.R1.S07: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
ACCM: F0 F0F0F0F0 F0F0F0F0
N4.C3.D1.R1.S13: Write Level Fine Value = 438
N6.C3.D1.R1.S01: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N0.C3.D1.R1.S08: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N2.C0.D0.R1: CheckMCTest: result = 0x3FE00
N4.C3.D1.R1.S14: Write Level Fine Value = 451
N6.C3.D1.R1.S02: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N0.C3.D1.R1.S00: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
ACCM: F0 F0F0F0F0 F0F0F0F0
N4.C3.D1.R1.S15: Write Level Fine Value = 465
N6.C3.D1.R1.S03: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N0.C3.D1.R1.S01: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
ACCM: F0 F0F0F0F0 F0F0F0F0
N4.C3.D1.R1.S16: Write Level Fine Value = 483
N6.C3.D1.R1.S04: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N0.C3.D1.R1.S02: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
ACCM: 00 000000B0 00000000
N4.C3.D1.R1.S17: Write Level Fine Value = 451
N6.C3.D1.R1.S05: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N0.C3.D1.R1.S03: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
ACCM: 00 000000B0 00000000
N4: END WRITE LEVEL:
N6.C3.D1.R1.S06: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N0.C3.D1.R1.S04: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N2.C0.D0.R1: CheckMCTest: result = 0x3FE00
N4: START WRITE LEVEL COARSE:
N6.C3.D1.R1.S07: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N0.C3.D1.R1.S05: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
ACCM: F0 F0F0F0F0 F0F0F0F0
N6.C3.D1.R1.S08: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N0.C3.D1.R1.S06: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
ACCM: F0 F0F0F0F0 F0F0F0F0
N6.C3.D1.R1.S00: Preamble found at Latency = 008
N0.C3.D1.R1.S07: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
ACCM: 00 000000B0 00000000
N6.C3.D1.R1.S01: Preamble found at Latency = 008
N0.C3.D1.R1.S08: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
ACCM: 00 000000B0 00000000
N6.C3.D1.R1.S02: Preamble found at Latency = 008
N0.C3.D1.R1.S00: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N2.C0.D0.R1: CheckMCTest: result = 0x3FE00
N6.C3.D1.R1.S05: Preamble found at Latency = 008
N0.C3.D1.R1.S01: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N2.C0.D0.R1: CheckMCTest: passed
N4.C0.D0.R0: Write Training Coarse, lower nibbles / bytes
N6.C3.D1.R1.S06: Preamble found at Latency = 008
N0.C3.D1.R1.S02: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N2.C0.D0.R1: CheckMCTest: passed
N4.C0.D0.R0.S00: Dq Delay estimate: 470
N6.C3.D1.R1.S07: Preamble found at Latency = 008
N0.C3.D1.R1.S03: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N2.C0.D0.R1.S09: Offset Found: RdPtrOffsetDqs = 007
N4.C0.D0.R0.S01: Dq Delay estimate: 449
N6.C3.D1.R1.S00: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N0.C3.D1.R1.S04: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N2.C0.D0.R1.S10: Offset Found: RdPtrOffsetDqs = 007
N4.C0.D0.R0.S02: Dq Delay estimate: 441
N6.C3.D1.R1.S01: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N0.C3.D1.R1.S05: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N2.C0.D0.R1.S11: Offset Found: RdPtrOffsetDqs = 007
N4.C0.D0.R0.S03: Dq Delay estimate: 421
N6.C3.D1.R1.S02: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N0.C3.D1.R1.S06: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N2.C0.D0.R1.S12: Offset Found: RdPtrOffsetDqs = 007
N4.C0.D0.R0.S04: Dq Delay estimate: 391
N6.C3.D1.R1.S03: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N0.C3.D1.R1.S07: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N2.C0.D0.R1.S13: Offset Found: RdPtrOffsetDqs = 006
N4.C0.D0.R0.S05: Dq Delay estimate: 409
N6.C3.D1.R1.S04: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N0.C3.D1.R1.S08: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N2.C0.D0.R1.S14: Offset Found: RdPtrOffsetDqs = 006
N4.C0.D0.R0.S06: Dq Delay estimate: 410
N6.C3.D1.R1.S05: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N0.C3.D1.R1.S00: Preamble found at Latency = 008
N2.C0.D0.R1.S15: Offset Found: RdPtrOffsetDqs = 006
N4.C0.D0.R0.S07: Dq Delay estimate: 424
N6.C3.D1.R1.S06: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N0.C3.D1.R1.S01: Preamble found at Latency = 008
N2.C0.D0.R1.S16: Offset Found: RdPtrOffsetDqs = 007
N4.C0.D0.R0.S08: Dq Delay estimate: 403
N6.C3.D1.R1.S07: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N0.C3.D1.R1.S06: Preamble found at Latency = 008
N2.C0.D0.R1.S17: Offset Found: RdPtrOffsetDqs = 006
ACCM: 9F 0F0FFF9F 0F0F0F0F
N6.C3.D1.R1.S08: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N0.C3.D1.R1.S07: Preamble found at Latency = 008
N2.C0.D1.R0: Write Training Coarse, lower nibbles / bytes
ACCM: 9F 0F0FFF9F 0F0F0F0F
N6.C3.D1.R1.S03: Preamble found at Latency = 007
N0.C3.D1.R1.S00: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N2.C0.D1.R0.S00: Dq Delay estimate: 468
ACCM: 9F FFFFFF9F FFFFFFFF
N6.C3.D1.R1.S04: Preamble found at Latency = 007
N0.C3.D1.R1.S01: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N2.C0.D1.R0.S01: Dq Delay estimate: 453
ACCM: 9F FFFFFF9F FFFFFFFF
N6.C3.D1.R1.S08: Preamble found at Latency = 007
N0.C3.D1.R1.S02: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N2.C0.D1.R0.S02: Dq Delay estimate: 440
N4.C0.D0.R0: CheckMCTest: result = 0x3FFFF
N6.C3.D1.R1.S00: Total Receive Enable Delay = 1366
N0.C3.D1.R1.S03: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N2.C0.D1.R0.S03: Dq Delay estimate: 421
ACCM: DF 0F0FFFDF 0F0F0F0F
N6.C3.D1.R1.S01: Total Receive Enable Delay = 1343
N0.C3.D1.R1.S04: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N2.C0.D1.R0.S04: Dq Delay estimate: 388
ACCM: DF 0F0FFFDF 0F0F0F0F
N6.C3.D1.R1.S02: Total Receive Enable Delay = 1316
N0.C3.D1.R1.S05: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N2.C0.D1.R0.S05: Dq Delay estimate: 408
ACCM: DF FFFFFFDF FFFFFFFF
N6.C3.D1.R1.S03: Total Receive Enable Delay = 1293
N0.C3.D1.R1.S06: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N2.C0.D1.R0.S06: Dq Delay estimate: 410
ACCM: DF FFFFFFDF FFFFFFFF
N6.C3.D1.R1.S04: Total Receive Enable Delay = 1286
N0.C3.D1.R1.S07: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N2.C0.D1.R0.S07: Dq Delay estimate: 426
N4.C0.D0.R0: CheckMCTest: result = 0x3FFFF
N6.C3.D1.R1.S05: Total Receive Enable Delay = 1313
N0.C3.D1.R1.S08: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N2.C0.D1.R0.S08: Dq Delay estimate: 396
ACCM: DF 0F0FFFDF 0F0F0F0F
N6.C3.D1.R1.S06: Total Receive Enable Delay = 1338
N0.C3.D1.R1.S02: Preamble found at Latency = 007
ACCM: 0F 0F0F0F0F 0F0F0F0F
ACCM: DF 0F0FFFDF 0F0F0F0F
N6.C3.D1.R1.S07: Total Receive Enable Delay = 1358
N0.C3.D1.R1.S03: Preamble found at Latency = 007
ACCM: 0F 0F0F0F0F 0F0F0F0F
ACCM: DB F0FBFBDB F0F0F0FB
N6.C3.D1.R1.S08: Total Receive Enable Delay = 1274
N0.C3.D1.R1.S04: Preamble found at Latency = 007
ACCM: 0F 0F0F0F0F 0F0F0F0F
ACCM: DB F0FBFBDB F0F0F0FB
N6.C3.D1.R1: Starting preamble search upper nibbles
N0.C3.D1.R1.S05: Preamble found at Latency = 007
ACCM: 0F FF0F0FFF FFFFFF0F
N4.C0.D0.R0: CheckMCTest: result = 0x3FFFF
N6.C3.D1.R1.S09: PI = 051, PtrOffset = 004
N0.C3.D1.R1.S08: Preamble found at Latency = 007
N2.C0.D1.R0: CheckMCTest: result = 0x13DFF
ACCM: DF 0F0FFFDF 0F0F0F0F
N6.C3.D1.R1.S10: PI = 032, PtrOffset = 004
N0.C3.D1.R1.S00: Total Receive Enable Delay = 1360
ACCM: 0F 0F0F0F0F 0F0F0F0F
ACCM: DF 0F0FFFDF 0F0F0F0F
N6.C3.D1.R1.S11: PI = 005, PtrOffset = 004
N0.C3.D1.R1.S01: Total Receive Enable Delay = 1340
ACCM: 0F 0F0F0F0F 0F0F0F0F
ACCM: DB F0FFFFDF F0F0F0FF
N6.C3.D1.R1.S12: PI = 046, PtrOffset = 005
N0.C3.D1.R1.S02: Total Receive Enable Delay = 1309
ACCM: 0F 0F0F0F0F 0F0F0F0F
ACCM: DB F0FFFFDF F0F0F0FF
N6.C3.D1.R1.S13: PI = 038, PtrOffset = 005
N0.C3.D1.R1.S03: Total Receive Enable Delay = 1286
ACCM: 0F FF0F0FFF FFFFFF0F
N4.C0.D0.R0: CheckMCTest: result = 0x3FFFF
N6.C3.D1.R1.S14: PI = 006, PtrOffset = 004
N0.C3.D1.R1.S04: Total Receive Enable Delay = 1281
N2.C0.D1.R0: CheckMCTest: result = 0x13DFF
ACCM: D0 0000F0D0 00000000
N6.C3.D1.R1.S15: PI = 029, PtrOffset = 004
N0.C3.D1.R1.S05: Total Receive Enable Delay = 1309
ACCM: 0F 0F0F0F0F 0F0F0F0F
ACCM: D0 0000F0D0 00000000
N6.C3.D1.R1.S16: PI = 048, PtrOffset = 004
N0.C3.D1.R1.S06: Total Receive Enable Delay = 1330
ACCM: 0F 0F0F0F0F 0F0F0F0F
ACCM: D0 F0F0F0D0 F0F0F0F0
N6.C3.D1.R1.S17: PI = 026, PtrOffset = 005
N0.C3.D1.R1.S07: Total Receive Enable Delay = 1353
ACCM: 00 0B0B0000 0000000B
ACCM: D0 F0F0F0D0 F0F0F0F0
N6.C3.D1.R1.S09: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N0.C3.D1.R1.S08: Total Receive Enable Delay = 1270
ACCM: 00 FB0B00F0 F0F0F00B
N4.C0.D0.R0: CheckMCTest: result = 0x3FE00
N6.C3.D1.R1.S10: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N0.C3.D1.R1: Starting preamble search upper nibbles
N2.C0.D1.R0: CheckMCTest: result = 0x13DFF
ACCM: D0 0000F0D0 00000000
N6.C3.D1.R1.S11: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N0.C3.D1.R1.S09: PI = 049, PtrOffset = 004
ACCM: 0F 0F0F0F0F 0F0F0F0F
ACCM: D0 0000F0D0 00000000
N6.C3.D1.R1.S12: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N0.C3.D1.R1.S10: PI = 027, PtrOffset = 004
ACCM: 0F 0F0F0F0F 0F0F0F0F
ACCM: D0 F0F0F0D0 F0F0F0F0
N6.C3.D1.R1.S13: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N0.C3.D1.R1.S11: PI = 063, PtrOffset = 005
ACCM: 00 0F0F000D 0000000F
ACCM: D0 F0F0F0D0 F0F0F0F0
N6.C3.D1.R1.S14: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N0.C3.D1.R1.S12: PI = 042, PtrOffset = 005
ACCM: 00 FF0F00FD F0F0F00F
N4.C0.D0.R0: CheckMCTest: result = 0x3FE00
N6.C3.D1.R1.S15: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N0.C3.D1.R1.S13: PI = 035, PtrOffset = 005
N2.C0.D1.R0: CheckMCTest: result = 0x13DFF
N4.C0.D0.R0.S00: Offset Found: RdPtrOffsetDqs = 007
N6.C3.D1.R1.S16: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N0.C3.D1.R1.S14: PI = 061, PtrOffset = 005
ACCM: 00 00000000 00000000
N4.C0.D0.R0.S01: Offset Found: RdPtrOffsetDqs = 007
N6.C3.D1.R1.S17: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N0.C3.D1.R1.S15: PI = 019, PtrOffset = 004
ACCM: 00 00000000 00000000
N4.C0.D0.R0.S02: Offset Found: RdPtrOffsetDqs = 007
N6.C3.D1.R1.S09: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N0.C3.D1.R1.S16: PI = 044, PtrOffset = 004
ACCM: 00 00000000 00000000
N4.C0.D0.R0.S03: Offset Found: RdPtrOffsetDqs = 007
N6.C3.D1.R1.S10: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N0.C3.D1.R1.S17: PI = 020, PtrOffset = 005
ACCM: 00 F00000F0 F0F0F000
N4.C0.D0.R0.S04: Offset Found: RdPtrOffsetDqs = 006
N6.C3.D1.R1.S11: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N0.C3.D1.R1.S09: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N2.C0.D1.R0: CheckMCTest: result = 0x13C00
N4.C0.D0.R0.S05: Offset Found: RdPtrOffsetDqs = 006
N6.C3.D1.R1.S12: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N0.C3.D1.R1.S10: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
ACCM: 00 00000000 00000000
N4.C0.D0.R0.S06: Offset Found: RdPtrOffsetDqs = 007
N6.C3.D1.R1.S13: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N0.C3.D1.R1.S11: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
ACCM: 00 00000000 00000000
N4.C0.D0.R0.S07: Offset Found: RdPtrOffsetDqs = 007
N6.C3.D1.R1.S14: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N0.C3.D1.R1.S12: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
ACCM: 00 00000000 00000000
N4.C0.D0.R0.S08: Offset Found: RdPtrOffsetDqs = 006
N6.C3.D1.R1.S15: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N0.C3.D1.R1.S13: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
ACCM: 00 F00000F0 F0F0F000
N4.C0.D0.R0: Write Training Coarse, upper nibbles
N6.C3.D1.R1.S16: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N0.C3.D1.R1.S14: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N2.C0.D1.R0: CheckMCTest: result = 0x13C00
N4.C0.D0.R0.S09: Dq Delay estimate: 467
N6.C3.D1.R1.S17: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N0.C3.D1.R1.S15: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N2.C0.D1.R0.S00: Offset Found: RdPtrOffsetDqs = 007
N4.C0.D0.R0.S10: Dq Delay estimate: 449
N6.C3.D1.R1.S09: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N0.C3.D1.R1.S16: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N2.C0.D1.R0.S01: Offset Found: RdPtrOffsetDqs = 007
N4.C0.D0.R0.S11: Dq Delay estimate: 437
N6.C3.D1.R1.S10: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N0.C3.D1.R1.S17: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N2.C0.D1.R0.S02: Offset Found: RdPtrOffsetDqs = 007
N4.C0.D0.R0.S12: Dq Delay estimate: 421
N6.C3.D1.R1.S11: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N0.C3.D1.R1.S09: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N2.C0.D1.R0.S03: Offset Found: RdPtrOffsetDqs = 007
N4.C0.D0.R0.S13: Dq Delay estimate: 392
N6.C3.D1.R1.S12: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N0.C3.D1.R1.S10: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N2.C0.D1.R0.S04: Offset Found: RdPtrOffsetDqs = 006
N4.C0.D0.R0.S14: Dq Delay estimate: 403
N6.C3.D1.R1.S13: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N0.C3.D1.R1.S11: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N2.C0.D1.R0.S05: Offset Found: RdPtrOffsetDqs = 006
N4.C0.D0.R0.S15: Dq Delay estimate: 410
N6.C3.D1.R1.S14: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N0.C3.D1.R1.S12: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N2.C0.D1.R0.S06: Offset Found: RdPtrOffsetDqs = 006
N4.C0.D0.R0.S16: Dq Delay estimate: 425
N6.C3.D1.R1.S15: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N0.C3.D1.R1.S13: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N2.C0.D1.R0.S07: Offset Found: RdPtrOffsetDqs = 007
N4.C0.D0.R0.S17: Dq Delay estimate: 403
N6.C3.D1.R1.S16: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N0.C3.D1.R1.S14: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N2.C0.D1.R0.S08: Offset Found: RdPtrOffsetDqs = 006
ACCM: F0 F0F0F0F0 F0F0F0F0
N6.C3.D1.R1.S17: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N0.C3.D1.R1.S15: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N2.C0.D1.R0: Write Training Coarse, upper nibbles
ACCM: F0 F0F0F0F0 F0F0F0F0
N6.C3.D1.R1.S09: Preamble found at Latency = 008
N0.C3.D1.R1.S16: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N2.C0.D1.R0.S09: Dq Delay estimate: 470
ACCM: F0 F0F0F0F0 F0F0F0F0
N6.C3.D1.R1.S10: Preamble found at Latency = 008
N0.C3.D1.R1.S17: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N2.C0.D1.R0.S10: Dq Delay estimate: 452
ACCM: F0 F0F0F0F0 F0F0F0F0
N6.C3.D1.R1.S11: Preamble found at Latency = 008
N0.C3.D1.R1.S09: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N2.C0.D1.R0.S11: Dq Delay estimate: 442
N4.C0.D0.R0: CheckMCTest: result = 0x3FE00
N6.C3.D1.R1.S14: Preamble found at Latency = 008
N0.C3.D1.R1.S10: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N2.C0.D1.R0.S12: Dq Delay estimate: 426
ACCM: F0 F0F0F0F0 F0F0F0F0
N6.C3.D1.R1.S15: Preamble found at Latency = 008
N0.C3.D1.R1.S11: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N2.C0.D1.R0.S13: Dq Delay estimate: 391
ACCM: F0 F0F0F0F0 F0F0F0F0
N6.C3.D1.R1.S16: Preamble found at Latency = 008
N0.C3.D1.R1.S12: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N2.C0.D1.R0.S14: Dq Delay estimate: 411
ACCM: F0 F0F0F0F0 F0F0F0F0
N6.C3.D1.R1.S09: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N0.C3.D1.R1.S13: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N2.C0.D1.R0.S15: Dq Delay estimate: 411
ACCM: F0 F0F0F0F0 F0F0F0F0
N6.C3.D1.R1.S10: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N0.C3.D1.R1.S14: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N2.C0.D1.R0.S16: Dq Delay estimate: 427
N4.C0.D0.R0: CheckMCTest: result = 0x3FE00
N6.C3.D1.R1.S11: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N0.C3.D1.R1.S15: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N2.C0.D1.R0.S17: Dq Delay estimate: 398
ACCM: F0 F0F0F0F0 F0F0F0F0
N6.C3.D1.R1.S12: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N0.C3.D1.R1.S16: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: F0 F0F0F0F0 F0F0F0F0
N6.C3.D1.R1.S13: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N0.C3.D1.R1.S17: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: B0 000000B0 B00000B0
N6.C3.D1.R1.S14: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N0.C3.D1.R1.S09: Preamble found at Latency = 008
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: B0 000000B0 B00000B0
N6.C3.D1.R1.S15: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N0.C3.D1.R1.S10: Preamble found at Latency = 008
ACCM: F0 F0F0F0F0 F0F0F0F0
N4.C0.D0.R0: CheckMCTest: result = 0x3FE00
N6.C3.D1.R1.S16: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N0.C3.D1.R1.S15: Preamble found at Latency = 008
N2.C0.D1.R0: CheckMCTest: result = 0x3FE00
ACCM: F0 F0F0F0F0 F0F0F0F0
N6.C3.D1.R1.S17: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N0.C3.D1.R1.S16: Preamble found at Latency = 008
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: F0 F0F0F0F0 F0F0F0F0
N6.C3.D1.R1.S12: Preamble found at Latency = 007
N0.C3.D1.R1.S09: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: F0 000000B0 B00000F0
N6.C3.D1.R1.S13: Preamble found at Latency = 007
N0.C3.D1.R1.S10: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: F0 000000B0 B00000F0
N6.C3.D1.R1.S17: Preamble found at Latency = 007
N0.C3.D1.R1.S11: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
ACCM: F0 F0F0F0F0 F0F0F0F0
N4.C0.D0.R0: CheckMCTest: result = 0x3FE00
N6.C3.D1.R1: Preamble found for all upper nibbles, adjusting Pi, Offset to center into preamble
N0.C3.D1.R1.S12: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N2.C0.D1.R0: CheckMCTest: result = 0x3FE00
N4.C0.D0.R0: CheckMCTest: passed
N6.C3.D1.R1.S09: Total Receive Enable Delay = 1363
N0.C3.D1.R1.S13: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
ACCM: F0 F0F0F0F0 F0F0F0F0
N4.C0.D0.R0: CheckMCTest: passed
N6.C3.D1.R1.S10: Total Receive Enable Delay = 1344
N0.C3.D1.R1.S14: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
ACCM: F0 F0F0F0F0 F0F0F0F0
N4.C0.D0.R0.S09: Offset Found: RdPtrOffsetDqs = 007
N6.C3.D1.R1.S11: Total Receive Enable Delay = 1317
N0.C3.D1.R1.S15: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
ACCM: 00 00B00000 00000000
N4.C0.D0.R0.S10: Offset Found: RdPtrOffsetDqs = 007
N6.C3.D1.R1.S12: Total Receive Enable Delay = 1294
N0.C3.D1.R1.S16: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
ACCM: 00 00B00000 00000000
N4.C0.D0.R0.S11: Offset Found: RdPtrOffsetDqs = 007
N6.C3.D1.R1.S13: Total Receive Enable Delay = 1286
N0.C3.D1.R1.S17: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N2.C0.D1.R0: CheckMCTest: result = 0x3FE00
N4.C0.D0.R0.S12: Offset Found: RdPtrOffsetDqs = 007
N6.C3.D1.R1.S14: Total Receive Enable Delay = 1318
N0.C3.D1.R1.S11: Preamble found at Latency = 007
ACCM: F0 F0F0F0F0 F0F0F0F0
N4.C0.D0.R0.S13: Offset Found: RdPtrOffsetDqs = 006
N6.C3.D1.R1.S15: Total Receive Enable Delay = 1341
N0.C3.D1.R1.S12: Preamble found at Latency = 007
ACCM: F0 F0F0F0F0 F0F0F0F0
N4.C0.D0.R0.S14: Offset Found: RdPtrOffsetDqs = 006
N6.C3.D1.R1.S16: Total Receive Enable Delay = 1360
N0.C3.D1.R1.S13: Preamble found at Latency = 007
ACCM: 00 00F00000 00000000
N4.C0.D0.R0.S15: Offset Found: RdPtrOffsetDqs = 006
N6.C3.D1.R1.S17: Total Receive Enable Delay = 1274
N0.C3.D1.R1.S14: Preamble found at Latency = 007
ACCM: 00 00F00000 00000000
N4.C0.D0.R0.S16: Offset Found: RdPtrOffsetDqs = 007
START_DATA_REC_EN
N0.C3.D1.R1.S17: Preamble found at Latency = 007
N2.C0.D1.R0: CheckMCTest: result = 0x3FE00
N4.C0.D0.R0.S17: Offset Found: RdPtrOffsetDqs = 006
N6.C3.S00: RdCmd2RcvEnLatency = 9, RdPtrOffsetRcvEn = 5
N0.C3.D1.R1: Preamble found for all upper nibbles, adjusting Pi, Offset to center into preamble
N2.C0.D1.R0: CheckMCTest: passed
N4.C0.D0.R1: Write Training Coarse, lower nibbles / bytes
N6.C3.S01: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N0.C3.D1.R1.S09: Total Receive Enable Delay = 1361
N2.C0.D1.R0: CheckMCTest: passed
N4.C0.D0.R1.S00: Dq Delay estimate: 463
N6.C3.S02: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N0.C3.D1.R1.S10: Total Receive Enable Delay = 1339
N2.C0.D1.R0.S09: Offset Found: RdPtrOffsetDqs = 007
N4.C0.D0.R1.S01: Dq Delay estimate: 445
N6.C3.S03: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N0.C3.D1.R1.S11: Total Receive Enable Delay = 1311
N2.C0.D1.R0.S10: Offset Found: RdPtrOffsetDqs = 007
N4.C0.D0.R1.S02: Dq Delay estimate: 433
N6.C3.S04: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N0.C3.D1.R1.S12: Total Receive Enable Delay = 1290
N2.C0.D1.R0.S11: Offset Found: RdPtrOffsetDqs = 007
N4.C0.D0.R1.S03: Dq Delay estimate: 418
N6.C3.S05: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N0.C3.D1.R1.S13: Total Receive Enable Delay = 1283
N2.C0.D1.R0.S12: Offset Found: RdPtrOffsetDqs = 007
N4.C0.D0.R1.S04: Dq Delay estimate: 382
N6.C3.S06: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N0.C3.D1.R1.S14: Total Receive Enable Delay = 1309
N2.C0.D1.R0.S13: Offset Found: RdPtrOffsetDqs = 006
N4.C0.D0.R1.S05: Dq Delay estimate: 401
N6.C3.S07: RdCmd2RcvEnLatency = 9, RdPtrOffsetRcvEn = 5
N0.C3.D1.R1.S15: Total Receive Enable Delay = 1331
N2.C0.D1.R0.S14: Offset Found: RdPtrOffsetDqs = 006
N4.C0.D0.R1.S06: Dq Delay estimate: 401
N6.C3.S08: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 5
N0.C3.D1.R1.S16: Total Receive Enable Delay = 1356
N2.C0.D1.R0.S15: Offset Found: RdPtrOffsetDqs = 006
N4.C0.D0.R1.S07: Dq Delay estimate: 416
N6.C3.S09: RdCmd2RcvEnLatency = 9, RdPtrOffsetRcvEn = 5
N0.C3.D1.R1.S17: Total Receive Enable Delay = 1268
N2.C0.D1.R0.S16: Offset Found: RdPtrOffsetDqs = 007
N4.C0.D0.R1.S08: Dq Delay estimate: 395
N6.C3.S10: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
START_DATA_REC_EN
N2.C0.D1.R0.S17: Offset Found: RdPtrOffsetDqs = 006
ACCM: 0F 0F0F0F0F 0F0F0F0F
N6.C3.S11: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N0.C3.S00: RdCmd2RcvEnLatency = 9, RdPtrOffsetRcvEn = 5
N2.C0.D1.R1: Write Training Coarse, lower nibbles / bytes
ACCM: 0F 0F0F0F0F 0F0F0F0F
N6.C3.S12: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N0.C3.S01: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N2.C0.D1.R1.S00: Dq Delay estimate: 463
ACCM: 0F 0F0F0F0F 0F0F0F0F
N6.C3.S13: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N0.C3.S02: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N2.C0.D1.R1.S01: Dq Delay estimate: 450
ACCM: 0F 0F0F0F0F 0F0F0F0F
N6.C3.S14: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N0.C3.S03: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N2.C0.D1.R1.S02: Dq Delay estimate: 436
N4.C0.D0.R1: CheckMCTest: result = 0x1FF
N6.C3.S15: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N0.C3.S04: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N2.C0.D1.R1.S03: Dq Delay estimate: 419
ACCM: 0F 0F0F0F0F 0F0F0F0F
N6.C3.S16: RdCmd2RcvEnLatency = 9, RdPtrOffsetRcvEn = 5
N0.C3.S05: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N2.C0.D1.R1.S04: Dq Delay estimate: 384
ACCM: 0F 0F0F0F0F 0F0F0F0F
N6.C3.S17: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 5
N0.C3.S06: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N2.C0.D1.R1.S05: Dq Delay estimate: 405
ACCM: 0F 0F0F0F0F 0F0F0F0F
N6.C3.D0.R0.S00: RcvEn: plus1 = 1, minus1 = 0, PI = 36, DB = 0
N0.C3.S07: RdCmd2RcvEnLatency = 9, RdPtrOffsetRcvEn = 5
N2.C0.D1.R1.S06: Dq Delay estimate: 406
ACCM: 0F 0F0F0F0F 0F0F0F0F
N6.C3.D0.R0.S01: RcvEn: plus1 = 0, minus1 = 1, PI = 16, DB = 0
N0.C3.S08: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 5
N2.C0.D1.R1.S07: Dq Delay estimate: 424
N4.C0.D0.R1: CheckMCTest: result = 0x1FF
N6.C3.D0.R0.S02: RcvEn: plus1 = 1, minus1 = 0, PI = 52, DB = 1
N0.C3.S09: RdCmd2RcvEnLatency = 9, RdPtrOffsetRcvEn = 5
N2.C0.D1.R1.S08: Dq Delay estimate: 394
ACCM: 0F 0F0F0F0F 0F0F0F0F
N6.C3.D0.R0.S03: RcvEn: plus1 = 1, minus1 = 0, PI = 28, DB = 0
N0.C3.S10: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
ACCM: 0F 0F0F0F0F 0F0F0F0F
ACCM: 0F 0F0F0F0F 0F0F0F0F
N6.C3.D0.R0.S04: RcvEn: plus1 = 1, minus1 = 0, PI = 21, DB = 0
N0.C3.S11: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
ACCM: 0F 0F0F0F0F 0F0F0F0F
ACCM: 00 0000000B 0000000B
N6.C3.D0.R0.S05: RcvEn: plus1 = 1, minus1 = 0, PI = 49, DB = 1
N0.C3.S12: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
ACCM: 0F 0F0F0F0F 0F0F0F0F
ACCM: 00 0000000B 0000000B
N6.C3.D0.R0.S06: RcvEn: plus1 = 0, minus1 = 1, PI = 08, DB = 1
N0.C3.S13: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
ACCM: 0F 0F0F0F0F 0F0F0F0F
N4.C0.D0.R1: CheckMCTest: result = 0x1FF
N6.C3.D0.R0.S07: RcvEn: plus1 = 1, minus1 = 0, PI = 30, DB = 0
N0.C3.S14: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N2.C0.D1.R1: CheckMCTest: result = 0x1FF
ACCM: 0F 0F0F0F0F 0F0F0F0F
N6.C3.D0.R0.S08: RcvEn: plus1 = 0, minus1 = 1, PI = 12, DB = 1
N0.C3.S15: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
ACCM: 0F 0F0F0F0F 0F0F0F0F
ACCM: 0F 0F0F0F0F 0F0F0F0F
N6.C3.D0.R0.S09: RcvEn: plus1 = 1, minus1 = 0, PI = 34, DB = 0
N0.C3.S16: RdCmd2RcvEnLatency = 9, RdPtrOffsetRcvEn = 5
ACCM: 0F 0F0F0F0F 0F0F0F0F
ACCM: 00 0000000B 0000000F
N6.C3.D0.R0.S10: RcvEn: plus1 = 0, minus1 = 1, PI = 15, DB = 1
N0.C3.S17: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 5
ACCM: 0F 0F0F0F0F 0F0F0F0F
ACCM: 00 0000000B 0000000F
N6.C3.D0.R0.S11: RcvEn: plus1 = 1, minus1 = 0, PI = 51, DB = 1
N0.C3.D0.R0.S00: RcvEn: plus1 = 1, minus1 = 0, PI = 34, DB = 0
ACCM: 0F 0F0F0F0F 0F0F0F0F
N4.C0.D0.R1: CheckMCTest: result = 0x1FF
N6.C3.D0.R0.S12: RcvEn: plus1 = 1, minus1 = 0, PI = 27, DB = 0
N0.C3.D0.R0.S01: RcvEn: plus1 = 0, minus1 = 1, PI = 11, DB = 1
N2.C0.D1.R1: CheckMCTest: result = 0x1FF
N4.C0.D0.R1: CheckMCTest: passed
N6.C3.D0.R0.S13: RcvEn: plus1 = 1, minus1 = 0, PI = 21, DB = 0
N0.C3.D0.R0.S02: RcvEn: plus1 = 1, minus1 = 0, PI = 47, DB = 0
ACCM: 0F 0F0F0F0F 0F0F0F0F
N4.C0.D0.R1: CheckMCTest: passed
N6.C3.D0.R0.S14: RcvEn: plus1 = 1, minus1 = 0, PI = 52, DB = 1
N0.C3.D0.R0.S03: RcvEn: plus1 = 1, minus1 = 0, PI = 23, DB = 0
ACCM: 0F 0F0F0F0F 0F0F0F0F
N4.C0.D0.R1.S00: Offset Found: RdPtrOffsetDqs = 007
N6.C3.D0.R0.S15: RcvEn: plus1 = 0, minus1 = 1, PI = 10, DB = 1
N0.C3.D0.R0.S04: RcvEn: plus1 = 1, minus1 = 0, PI = 20, DB = 0
ACCM: 00 0000000B 0000000B
N4.C0.D0.R1.S01: Offset Found: RdPtrOffsetDqs = 007
N6.C3.D0.R0.S16: RcvEn: plus1 = 1, minus1 = 0, PI = 30, DB = 0
N0.C3.D0.R0.S05: RcvEn: plus1 = 1, minus1 = 0, PI = 45, DB = 0
ACCM: 00 0000000B 0000000B
N4.C0.D0.R1.S02: Offset Found: RdPtrOffsetDqs = 007
N6.C3.D0.R0.S17: RcvEn: plus1 = 0, minus1 = 1, PI = 10, DB = 1
N0.C3.D0.R0.S06: RcvEn: plus1 = 0, minus1 = 1, PI = 04, DB = 1
N2.C0.D1.R1: CheckMCTest: result = 0x1FF
N4.C0.D0.R1.S03: Offset Found: RdPtrOffsetDqs = 007
N6.C3.D0.R1.S00: RcvEn: plus1 = 1, minus1 = 0, PI = 36, DB = 0
N0.C3.D0.R0.S07: RcvEn: plus1 = 1, minus1 = 0, PI = 26, DB = 0
ACCM: 0F 0F0F0F0F 0F0F0F0F
N4.C0.D0.R1.S04: Offset Found: RdPtrOffsetDqs = 006
N6.C3.D0.R1.S01: RcvEn: plus1 = 0, minus1 = 1, PI = 16, DB = 0
N0.C3.D0.R0.S08: RcvEn: plus1 = 0, minus1 = 1, PI = 07, DB = 1
ACCM: 0F 0F0F0F0F 0F0F0F0F
N4.C0.D0.R1.S05: Offset Found: RdPtrOffsetDqs = 006
N6.C3.D0.R1.S02: RcvEn: plus1 = 1, minus1 = 0, PI = 52, DB = 1
N0.C3.D0.R0.S09: RcvEn: plus1 = 1, minus1 = 0, PI = 33, DB = 0
ACCM: 00 0000000F 0000000B
N4.C0.D0.R1.S06: Offset Found: RdPtrOffsetDqs = 006
N6.C3.D0.R1.S03: RcvEn: plus1 = 1, minus1 = 0, PI = 28, DB = 0
N0.C3.D0.R0.S10: RcvEn: plus1 = 0, minus1 = 1, PI = 13, DB = 1
ACCM: 00 0000000F 0000000B
N4.C0.D0.R1.S07: Offset Found: RdPtrOffsetDqs = 007
N6.C3.D0.R1.S04: RcvEn: plus1 = 1, minus1 = 0, PI = 21, DB = 0
N0.C3.D0.R0.S11: RcvEn: plus1 = 1, minus1 = 0, PI = 48, DB = 0
N2.C0.D1.R1: CheckMCTest: result = 0x1FF
N4.C0.D0.R1.S08: Offset Found: RdPtrOffsetDqs = 006
N6.C3.D0.R1.S05: RcvEn: plus1 = 1, minus1 = 0, PI = 49, DB = 1
N0.C3.D0.R0.S12: RcvEn: plus1 = 1, minus1 = 0, PI = 25, DB = 0
N2.C0.D1.R1: CheckMCTest: passed
N4.C0.D0.R1: Write Training Coarse, upper nibbles
N6.C3.D0.R1.S06: RcvEn: plus1 = 0, minus1 = 1, PI = 08, DB = 1
N0.C3.D0.R0.S13: RcvEn: plus1 = 1, minus1 = 0, PI = 19, DB = 0
N2.C0.D1.R1: CheckMCTest: passed
N4.C0.D0.R1.S09: Dq Delay estimate: 460
N6.C3.D0.R1.S07: RcvEn: plus1 = 1, minus1 = 0, PI = 30, DB = 0
N0.C3.D0.R0.S14: RcvEn: plus1 = 1, minus1 = 0, PI = 46, DB = 0
N2.C0.D1.R1.S00: Offset Found: RdPtrOffsetDqs = 007
N4.C0.D0.R1.S10: Dq Delay estimate: 445
N6.C3.D0.R1.S08: RcvEn: plus1 = 0, minus1 = 1, PI = 12, DB = 1
N0.C3.D0.R0.S15: RcvEn: plus1 = 0, minus1 = 1, PI = 04, DB = 1
N2.C0.D1.R1.S01: Offset Found: RdPtrOffsetDqs = 007
N4.C0.D0.R1.S11: Dq Delay estimate: 434
N6.C3.D0.R1.S09: RcvEn: plus1 = 1, minus1 = 0, PI = 34, DB = 0
N0.C3.D0.R0.S16: RcvEn: plus1 = 1, minus1 = 0, PI = 29, DB = 0
N2.C0.D1.R1.S02: Offset Found: RdPtrOffsetDqs = 007
N4.C0.D0.R1.S12: Dq Delay estimate: 417
N6.C3.D0.R1.S10: RcvEn: plus1 = 0, minus1 = 1, PI = 15, DB = 1
N0.C3.D0.R0.S17: RcvEn: plus1 = 0, minus1 = 1, PI = 04, DB = 1
N2.C0.D1.R1.S03: Offset Found: RdPtrOffsetDqs = 007
N4.C0.D0.R1.S13: Dq Delay estimate: 385
N6.C3.D0.R1.S11: RcvEn: plus1 = 1, minus1 = 0, PI = 51, DB = 1
N0.C3.D0.R1.S00: RcvEn: plus1 = 1, minus1 = 0, PI = 34, DB = 0
N2.C0.D1.R1.S04: Offset Found: RdPtrOffsetDqs = 006
N4.C0.D0.R1.S14: Dq Delay estimate: 398
N6.C3.D0.R1.S12: RcvEn: plus1 = 1, minus1 = 0, PI = 27, DB = 0
N0.C3.D0.R1.S01: RcvEn: plus1 = 0, minus1 = 1, PI = 11, DB = 1
N2.C0.D1.R1.S05: Offset Found: RdPtrOffsetDqs = 006
N4.C0.D0.R1.S15: Dq Delay estimate: 404
N6.C3.D0.R1.S13: RcvEn: plus1 = 1, minus1 = 0, PI = 21, DB = 0
N0.C3.D0.R1.S02: RcvEn: plus1 = 1, minus1 = 0, PI = 47, DB = 0
N2.C0.D1.R1.S06: Offset Found: RdPtrOffsetDqs = 006
N4.C0.D0.R1.S16: Dq Delay estimate: 419
N6.C3.D0.R1.S14: RcvEn: plus1 = 1, minus1 = 0, PI = 52, DB = 1
N0.C3.D0.R1.S03: RcvEn: plus1 = 1, minus1 = 0, PI = 23, DB = 0
N2.C0.D1.R1.S07: Offset Found: RdPtrOffsetDqs = 007
N4.C0.D0.R1.S17: Dq Delay estimate: 393
N6.C3.D0.R1.S15: RcvEn: plus1 = 0, minus1 = 1, PI = 10, DB = 1
N0.C3.D0.R1.S04: RcvEn: plus1 = 1, minus1 = 0, PI = 20, DB = 0
N2.C0.D1.R1.S08: Offset Found: RdPtrOffsetDqs = 006
ACCM: F0 F0F0F0F0 F0F0F0F0
N6.C3.D0.R1.S16: RcvEn: plus1 = 1, minus1 = 0, PI = 30, DB = 0
N0.C3.D0.R1.S05: RcvEn: plus1 = 1, minus1 = 0, PI = 45, DB = 0
N2.C0.D1.R1: Write Training Coarse, upper nibbles
ACCM: F0 F0F0F0F0 F0F0F0F0
N6.C3.D0.R1.S17: RcvEn: plus1 = 0, minus1 = 1, PI = 10, DB = 1
N0.C3.D0.R1.S06: RcvEn: plus1 = 0, minus1 = 1, PI = 04, DB = 1
N2.C0.D1.R1.S09: Dq Delay estimate: 463
ACCM: F0 F0F0F0F0 F0F0F0F0
N6.C3.D1.R0.S00: RcvEn: plus1 = 1, minus1 = 0, PI = 21, DB = 0
N0.C3.D0.R1.S07: RcvEn: plus1 = 1, minus1 = 0, PI = 26, DB = 0
N2.C0.D1.R1.S10: Dq Delay estimate: 451
ACCM: F0 F0F0F0F0 F0F0F0F0
N6.C3.D1.R0.S01: RcvEn: plus1 = 1, minus1 = 0, PI = 63, DB = 1
N0.C3.D0.R1.S08: RcvEn: plus1 = 0, minus1 = 1, PI = 07, DB = 1
N2.C0.D1.R1.S11: Dq Delay estimate: 438
N4.C0.D0.R1: CheckMCTest: result = 0x3FE00
N6.C3.D1.R0.S02: RcvEn: plus1 = 1, minus1 = 0, PI = 37, DB = 0
N0.C3.D0.R1.S09: RcvEn: plus1 = 1, minus1 = 0, PI = 33, DB = 0
N2.C0.D1.R1.S12: Dq Delay estimate: 424
ACCM: F0 F0F0F0F0 F0F0F0F0
N6.C3.D1.R0.S03: RcvEn: plus1 = 1, minus1 = 0, PI = 13, DB = 1
N0.C3.D0.R1.S10: RcvEn: plus1 = 0, minus1 = 1, PI = 13, DB = 1
N2.C0.D1.R1.S13: Dq Delay estimate: 386
ACCM: F0 F0F0F0F0 F0F0F0F0
N6.C3.D1.R0.S04: RcvEn: plus1 = 1, minus1 = 0, PI = 06, DB = 1
N0.C3.D0.R1.S11: RcvEn: plus1 = 1, minus1 = 0, PI = 48, DB = 0
N2.C0.D1.R1.S14: Dq Delay estimate: 405
ACCM: F0 F0F0F0F0 F0F0F0F0
N6.C3.D1.R0.S05: RcvEn: plus1 = 1, minus1 = 0, PI = 35, DB = 0
N0.C3.D0.R1.S12: RcvEn: plus1 = 1, minus1 = 0, PI = 25, DB = 0
N2.C0.D1.R1.S15: Dq Delay estimate: 408
ACCM: F0 F0F0F0F0 F0F0F0F0
N6.C3.D1.R0.S06: RcvEn: plus1 = 1, minus1 = 0, PI = 58, DB = 1
N0.C3.D0.R1.S13: RcvEn: plus1 = 1, minus1 = 0, PI = 19, DB = 0
N2.C0.D1.R1.S16: Dq Delay estimate: 424
N4.C0.D0.R1: CheckMCTest: result = 0x3FE00
N6.C3.D1.R0.S07: RcvEn: plus1 = 1, minus1 = 0, PI = 14, DB = 1
N0.C3.D0.R1.S14: RcvEn: plus1 = 1, minus1 = 0, PI = 46, DB = 0
N2.C0.D1.R1.S17: Dq Delay estimate: 395
ACCM: F0 F0F0F0F0 F0F0F0F0
N6.C3.D1.R0.S08: RcvEn: plus1 = 1, minus1 = 0, PI = 58, DB = 1
N0.C3.D0.R1.S15: RcvEn: plus1 = 0, minus1 = 1, PI = 04, DB = 1
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: F0 F0F0F0F0 F0F0F0F0
N6.C3.D1.R0.S09: RcvEn: plus1 = 1, minus1 = 0, PI = 19, DB = 0
N0.C3.D0.R1.S16: RcvEn: plus1 = 1, minus1 = 0, PI = 29, DB = 0
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: 00 00000000 00B0B000
N6.C3.D1.R0.S10: RcvEn: plus1 = 1, minus1 = 0, PI = 63, DB = 1
N0.C3.D0.R1.S17: RcvEn: plus1 = 0, minus1 = 1, PI = 04, DB = 1
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: 00 00000000 00B0B000
N6.C3.D1.R0.S11: RcvEn: plus1 = 1, minus1 = 0, PI = 36, DB = 0
N0.C3.D1.R0.S00: RcvEn: plus1 = 1, minus1 = 0, PI = 17, DB = 0
ACCM: F0 F0F0F0F0 F0F0F0F0
N4.C0.D0.R1: CheckMCTest: result = 0x3FE00
N6.C3.D1.R0.S12: RcvEn: plus1 = 1, minus1 = 0, PI = 13, DB = 1
N0.C3.D1.R0.S01: RcvEn: plus1 = 1, minus1 = 0, PI = 60, DB = 1
N2.C0.D1.R1: CheckMCTest: result = 0x3FE00
ACCM: F0 F0F0F0F0 F0F0F0F0
N6.C3.D1.R0.S13: RcvEn: plus1 = 1, minus1 = 0, PI = 06, DB = 1
N0.C3.D1.R0.S02: RcvEn: plus1 = 1, minus1 = 0, PI = 30, DB = 0
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: F0 F0F0F0F0 F0F0F0F0
N6.C3.D1.R0.S14: RcvEn: plus1 = 1, minus1 = 0, PI = 37, DB = 0
N0.C3.D1.R0.S03: RcvEn: plus1 = 1, minus1 = 0, PI = 06, DB = 1
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: 00 00000000 00F0F000
N6.C3.D1.R0.S15: RcvEn: plus1 = 1, minus1 = 0, PI = 59, DB = 1
N0.C3.D1.R0.S04: RcvEn: plus1 = 1, minus1 = 0, PI = 02, DB = 1
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: 00 00000000 00F0F000
N6.C3.D1.R0.S16: RcvEn: plus1 = 1, minus1 = 0, PI = 16, DB = 0
N0.C3.D1.R0.S05: RcvEn: plus1 = 1, minus1 = 0, PI = 28, DB = 0
ACCM: F0 F0F0F0F0 F0F0F0F0
N4.C0.D0.R1: CheckMCTest: result = 0x3FE00
N6.C3.D1.R0.S17: RcvEn: plus1 = 1, minus1 = 0, PI = 57, DB = 1
N0.C3.D1.R0.S06: RcvEn: plus1 = 1, minus1 = 0, PI = 50, DB = 1
N2.C0.D1.R1: CheckMCTest: result = 0x3FE00
N4.C0.D0.R1: CheckMCTest: passed
N6.C3.D1.R1.S00: RcvEn: plus1 = 1, minus1 = 0, PI = 21, DB = 0
N0.C3.D1.R0.S07: RcvEn: plus1 = 1, minus1 = 0, PI = 09, DB = 1
ACCM: F0 F0F0F0F0 F0F0F0F0
N4.C0.D0.R1: CheckMCTest: passed
N6.C3.D1.R1.S01: RcvEn: plus1 = 1, minus1 = 0, PI = 63, DB = 1
N0.C3.D1.R0.S08: RcvEn: plus1 = 1, minus1 = 0, PI = 53, DB = 1
ACCM: F0 F0F0F0F0 F0F0F0F0
N4.C0.D0.R1.S09: Offset Found: RdPtrOffsetDqs = 007
N6.C3.D1.R1.S02: RcvEn: plus1 = 1, minus1 = 0, PI = 37, DB = 0
N0.C3.D1.R0.S09: RcvEn: plus1 = 1, minus1 = 0, PI = 16, DB = 0
ACCM: 00 00B00000 00000000
N4.C0.D0.R1.S10: Offset Found: RdPtrOffsetDqs = 007
N6.C3.D1.R1.S03: RcvEn: plus1 = 1, minus1 = 0, PI = 13, DB = 1
N0.C3.D1.R0.S10: RcvEn: plus1 = 1, minus1 = 0, PI = 58, DB = 1
ACCM: 00 00B00000 00000000
N4.C0.D0.R1.S11: Offset Found: RdPtrOffsetDqs = 007
N6.C3.D1.R1.S04: RcvEn: plus1 = 1, minus1 = 0, PI = 06, DB = 1
N0.C3.D1.R0.S11: RcvEn: plus1 = 1, minus1 = 0, PI = 32, DB = 0
N2.C0.D1.R1: CheckMCTest: result = 0x3FE00
N4.C0.D0.R1.S12: Offset Found: RdPtrOffsetDqs = 007
N6.C3.D1.R1.S05: RcvEn: plus1 = 1, minus1 = 0, PI = 35, DB = 0
N0.C3.D1.R0.S12: RcvEn: plus1 = 1, minus1 = 0, PI = 10, DB = 1
ACCM: F0 F0F0F0F0 F0F0F0F0
N4.C0.D0.R1.S13: Offset Found: RdPtrOffsetDqs = 006
N6.C3.D1.R1.S06: RcvEn: plus1 = 1, minus1 = 0, PI = 58, DB = 1
N0.C3.D1.R0.S13: RcvEn: plus1 = 1, minus1 = 0, PI = 02, DB = 1
ACCM: F0 F0F0F0F0 F0F0F0F0
N4.C0.D0.R1.S14: Offset Found: RdPtrOffsetDqs = 006
N6.C3.D1.R1.S07: RcvEn: plus1 = 1, minus1 = 0, PI = 14, DB = 1
N0.C3.D1.R0.S14: RcvEn: plus1 = 1, minus1 = 0, PI = 29, DB = 0
ACCM: 00 00F00000 00000000
N4.C0.D0.R1.S15: Offset Found: RdPtrOffsetDqs = 006
N6.C3.D1.R1.S08: RcvEn: plus1 = 1, minus1 = 0, PI = 58, DB = 1
N0.C3.D1.R0.S15: RcvEn: plus1 = 1, minus1 = 0, PI = 51, DB = 1
ACCM: 00 00F00000 00000000
N4.C0.D0.R1.S16: Offset Found: RdPtrOffsetDqs = 007
N6.C3.D1.R1.S09: RcvEn: plus1 = 1, minus1 = 0, PI = 19, DB = 0
N0.C3.D1.R0.S16: RcvEn: plus1 = 1, minus1 = 0, PI = 11, DB = 1
N2.C0.D1.R1: CheckMCTest: result = 0x3FE00
N4.C0.D0.R1.S17: Offset Found: RdPtrOffsetDqs = 006
N6.C3.D1.R1.S10: RcvEn: plus1 = 1, minus1 = 0, PI = 63, DB = 1
N0.C3.D1.R0.S17: RcvEn: plus1 = 1, minus1 = 0, PI = 52, DB = 1
N2.C0.D1.R1: CheckMCTest: passed
N4.C0.D1.R0: Write Training Coarse, lower nibbles / bytes
N6.C3.D1.R1.S11: RcvEn: plus1 = 1, minus1 = 0, PI = 36, DB = 0
N0.C3.D1.R1.S00: RcvEn: plus1 = 1, minus1 = 0, PI = 17, DB = 0
N2.C0.D1.R1: CheckMCTest: passed
N4.C0.D1.R0.S00: Dq Delay estimate: 469
N6.C3.D1.R1.S12: RcvEn: plus1 = 1, minus1 = 0, PI = 13, DB = 1
N0.C3.D1.R1.S01: RcvEn: plus1 = 1, minus1 = 0, PI = 60, DB = 1
N2.C0.D1.R1.S09: Offset Found: RdPtrOffsetDqs = 007
N4.C0.D1.R0.S01: Dq Delay estimate: 456
N6.C3.D1.R1.S13: RcvEn: plus1 = 1, minus1 = 0, PI = 06, DB = 1
N0.C3.D1.R1.S02: RcvEn: plus1 = 1, minus1 = 0, PI = 30, DB = 0
N2.C0.D1.R1.S10: Offset Found: RdPtrOffsetDqs = 007
N4.C0.D1.R0.S02: Dq Delay estimate: 442
N6.C3.D1.R1.S14: RcvEn: plus1 = 1, minus1 = 0, PI = 37, DB = 0
N0.C3.D1.R1.S03: RcvEn: plus1 = 1, minus1 = 0, PI = 06, DB = 1
N2.C0.D1.R1.S11: Offset Found: RdPtrOffsetDqs = 007
N4.C0.D1.R0.S03: Dq Delay estimate: 425
N6.C3.D1.R1.S15: RcvEn: plus1 = 1, minus1 = 0, PI = 59, DB = 1
N0.C3.D1.R1.S04: RcvEn: plus1 = 1, minus1 = 0, PI = 02, DB = 1
N2.C0.D1.R1.S12: Offset Found: RdPtrOffsetDqs = 007
N4.C0.D1.R0.S04: Dq Delay estimate: 391
N6.C3.D1.R1.S16: RcvEn: plus1 = 1, minus1 = 0, PI = 16, DB = 0
N0.C3.D1.R1.S05: RcvEn: plus1 = 1, minus1 = 0, PI = 28, DB = 0
N2.C0.D1.R1.S13: Offset Found: RdPtrOffsetDqs = 006
N4.C0.D1.R0.S05: Dq Delay estimate: 409
N6.C3.D1.R1.S17: RcvEn: plus1 = 1, minus1 = 0, PI = 57, DB = 1
N0.C3.D1.R1.S06: RcvEn: plus1 = 1, minus1 = 0, PI = 50, DB = 1
N2.C0.D1.R1.S14: Offset Found: RdPtrOffsetDqs = 006
N4.C0.D1.R0.S06: Dq Delay estimate: 412
STOP_DATA_REC_EN
N0.C3.D1.R1.S07: RcvEn: plus1 = 1, minus1 = 0, PI = 09, DB = 1
N2.C0.D1.R1.S15: Offset Found: RdPtrOffsetDqs = 006
N4.C0.D1.R0.S07: Dq Delay estimate: 425
N6.C0.D0.R0.S00: StoreJckWorstRank: worst rank = 0, greatestDelay = 1333
N0.C3.D1.R1.S08: RcvEn: plus1 = 1, minus1 = 0, PI = 53, DB = 1
N2.C0.D1.R1.S16: Offset Found: RdPtrOffsetDqs = 007
N4.C0.D1.R0.S08: Dq Delay estimate: 399
N6.C1.D0.R0.S00: StoreJckWorstRank: worst rank = 0, greatestDelay = 1380
N0.C3.D1.R1.S09: RcvEn: plus1 = 1, minus1 = 0, PI = 16, DB = 0
N2.C0.D1.R1.S17: Offset Found: RdPtrOffsetDqs = 006
ACCM: 0F 0F0F0F0F 0F0F0F0F
N6.C1.D0.R1.S00: StoreJckWorstRank: worst rank = 1, greatestDelay = 1381
N0.C3.D1.R1.S10: RcvEn: plus1 = 1, minus1 = 0, PI = 58, DB = 1
N2.C0: Calculating Optimimum DQS Values
ACCM: 0F 0F0F0F0F 0F0F0F0F
N6.C0: StoreJckWorstRank: final value: worst rank = 1
N0.C3.D1.R1.S11: RcvEn: plus1 = 1, minus1 = 0, PI = 32, DB = 0
N2.C0.D0.R0.S00: Total Delay in PI ticks: TxDQS = 1011, TxDQ = 979
ACCM: 0F 0F0F0F0F 0F0F0F0F
N6.C2.D0.R0.S00: StoreJckWorstRank: worst rank = 0, greatestDelay = 1333
N0.C3.D1.R1.S12: RcvEn: plus1 = 1, minus1 = 0, PI = 10, DB = 1
N2.C0.D0.R0.S01: Total Delay in PI ticks: TxDQS = 992, TxDQ = 960
ACCM: 0F FF0F0F0F FFFFFF0F
N6.C3.D0.R0.S00: StoreJckWorstRank: worst rank = 0, greatestDelay = 1380
N0.C3.D1.R1.S13: RcvEn: plus1 = 1, minus1 = 0, PI = 02, DB = 1
N2.C0.D0.R0.S02: Total Delay in PI ticks: TxDQS = 982, TxDQ = 949
N4.C0.D1.R0: CheckMCTest: result = 0x11DFF
N6.C3.D0.R1.S00: StoreJckWorstRank: worst rank = 1, greatestDelay = 1381
N0.C3.D1.R1.S14: RcvEn: plus1 = 1, minus1 = 0, PI = 29, DB = 0
N2.C0.D0.R0.S03: Total Delay in PI ticks: TxDQS = 962, TxDQ = 929
ACCM: 0F 0F0F0F0F 0F0F0F0F
N6.C1: StoreJckWorstRank: final value: worst rank = 1
N0.C3.D1.R1.S15: RcvEn: plus1 = 1, minus1 = 0, PI = 51, DB = 1
N2.C0.D0.R0.S04: Total Delay in PI ticks: TxDQS = 930, TxDQ = 895
ACCM: 0F 0F0F0F0F 0F0F0F0F
N6: RunTrainStep: Final status = 0
N0.C3.D1.R1.S16: RcvEn: plus1 = 1, minus1 = 0, PI = 11, DB = 1
N2.C0.D0.R0.S05: Total Delay in PI ticks: TxDQS = 948, TxDQ = 914
ACCM: 0F 0F0F0F0F 0F0F0F0F

END - Basic Receive Enable Training    Time         63830 ms
N0.C3.D1.R1.S17: RcvEn: plus1 = 1, minus1 = 0, PI = 52, DB = 1
N2.C0.D0.R0.S06: Total Delay in PI ticks: TxDQS = 953, TxDQ = 918
ACCM: 0F FF0F0F0F FFFFFF0F
N6.C0.S00: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  6
STOP_DATA_REC_EN
N2.C0.D0.R0.S07: Total Delay in PI ticks: TxDQS = 966, TxDQ = 932
N4.C0.D1.R0: CheckMCTest: result = 0x11DFF
N6.C0.S01: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  6
N0.C0.D0.R0.S00: StoreJckWorstRank: worst rank = 0, greatestDelay = 1322
N2.C0.D0.R0.S08: Total Delay in PI ticks: TxDQS = 944, TxDQ = 908
ACCM: 0F 0F0F0F0F 0F0F0F0F
N6.C0.S02: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  5
N0.C0.D0.R0.S07: StoreJckWorstRank: worst rank = 0, greatestDelay = 1324
N2.C0.D0.R0.S09: Total Delay in PI ticks: TxDQS = 1014, TxDQ = 982
ACCM: 0F 0F0F0F0F 0F0F0F0F
N6.C0.S03: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  5
N0.C0.D0.R0.S16: StoreJckWorstRank: worst rank = 0, greatestDelay = 1326
N2.C0.D0.R0.S10: Total Delay in PI ticks: TxDQS = 993, TxDQ = 960
ACCM: 00 000B0000 000B0B0B
N6.C0.S04: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  5
N0.C1.D0.R0.S00: StoreJckWorstRank: worst rank = 0, greatestDelay = 1376
N2.C0.D0.R0.S11: Total Delay in PI ticks: TxDQS = 981, TxDQ = 947
ACCM: 00 F00B0000 F0FBFB0B
N6.C0.S05: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  5
N0.C0: StoreJckWorstRank: final value: worst rank = 0
N2.C0.D0.R0.S12: Total Delay in PI ticks: TxDQS = 964, TxDQ = 930
N4.C0.D1.R0: CheckMCTest: result = 0x11DFF
N6.C0.S06: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  6
N0.C2.D0.R0.S00: StoreJckWorstRank: worst rank = 0, greatestDelay = 1332
N2.C0.D0.R0.S13: Total Delay in PI ticks: TxDQS = 932, TxDQ = 899
ACCM: 0F 0F0F0F0F 0F0F0F0F
N6.C0.S07: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  6
N0.C3.D0.R0.S00: StoreJckWorstRank: worst rank = 0, greatestDelay = 1377
N2.C0.D0.R0.S14: Total Delay in PI ticks: TxDQS = 948, TxDQ = 916
ACCM: 0F 0F0F0F0F 0F0F0F0F
N6.C0.S08: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  5
N0.C3.D0.R0.S09: StoreJckWorstRank: worst rank = 0, greatestDelay = 1378
N2.C0.D0.R0.S15: Total Delay in PI ticks: TxDQS = 951, TxDQ = 918
ACCM: 00 000F0000 000F0F0B
N6.C1.S00: SuppressionWindowAdjustmentRd: latency =  9, rdptroffset =  5
N0.C3.D0.R1.S00: StoreJckWorstRank: worst rank = 1, greatestDelay = 1379
N2.C0.D0.R0.S16: Total Delay in PI ticks: TxDQS = 966, TxDQ = 932
ACCM: 00 F00F0000 F0FFFF0B
N6.C1.S01: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  6
N0.C1: StoreJckWorstRank: final value: worst rank = 1
N2.C0.D0.R0.S17: Total Delay in PI ticks: TxDQS = 944, TxDQ = 910
N4.C0.D1.R0: CheckMCTest: result = 0x11DFF
N6.C1.S02: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  6
N0: RunTrainStep: Final status = 0
N2.C0.D0.R1.S00: Total Delay in PI ticks: TxDQS = 1006, TxDQ = 972
ACCM: 00 00000000 00000000
N6.C1.S03: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  6

END - Basic Receive Enable Training    Time         63957 ms
N2.C0.D0.R1.S01: Total Delay in PI ticks: TxDQS = 988, TxDQ = 954
ACCM: 00 00000000 00000000
N6.C1.S04: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  6
N0.C0.S00: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  6
N2.C0.D0.R1.S02: Total Delay in PI ticks: TxDQS = 974, TxDQ = 941
ACCM: 00 00000000 00000000
N6.C1.S05: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  6
N0.C0.S01: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  6
N2.C0.D0.R1.S03: Total Delay in PI ticks: TxDQS = 956, TxDQ = 921
ACCM: 00 F0000000 F0F0F000
N6.C1.S06: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  6
N0.C0.S02: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  5
N2.C0.D0.R1.S04: Total Delay in PI ticks: TxDQS = 923, TxDQ = 888
N4.C0.D1.R0: CheckMCTest: result = 0x11C00
N6.C1.S07: SuppressionWindowAdjustmentRd: latency =  9, rdptroffset =  5
N0.C0.S03: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  5
N2.C0.D0.R1.S05: Total Delay in PI ticks: TxDQS = 941, TxDQ = 908
ACCM: 00 00000000 00000000
N6.C1.S08: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  5
N0.C0.S04: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  5
N2.C0.D0.R1.S06: Total Delay in PI ticks: TxDQS = 946, TxDQ = 912
ACCM: 00 00000000 00000000
N6.C2.S00: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  6
N0.C0.S05: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  5
N2.C0.D0.R1.S07: Total Delay in PI ticks: TxDQS = 960, TxDQ = 926
ACCM: 00 00000000 00000000
N6.C2.S01: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  6
N0.C0.S06: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  6
N2.C0.D0.R1.S08: Total Delay in PI ticks: TxDQS = 936, TxDQ = 900
ACCM: 00 F0000000 F0F0F000
N6.C2.S02: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  5
N0.C0.S07: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  6
N2.C0.D0.R1.S09: Total Delay in PI ticks: TxDQS = 1002, TxDQ = 969
N4.C0.D1.R0: CheckMCTest: result = 0x11C00
N6.C2.S03: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  5
N0.C0.S08: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  5
N2.C0.D0.R1.S10: Total Delay in PI ticks: TxDQS = 986, TxDQ = 953
N4.C0.D1.R0.S00: Offset Found: RdPtrOffsetDqs = 007
N6.C2.S04: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  5
N0.C1.S00: SuppressionWindowAdjustmentRd: latency =  9, rdptroffset =  5
N2.C0.D0.R1.S11: Total Delay in PI ticks: TxDQS = 976, TxDQ = 943
N4.C0.D1.R0.S01: Offset Found: RdPtrOffsetDqs = 007
N6.C2.S05: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  5
N0.C1.S01: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  6
N2.C0.D0.R1.S12: Total Delay in PI ticks: TxDQS = 960, TxDQ = 926
N4.C0.D1.R0.S02: Offset Found: RdPtrOffsetDqs = 007
N6.C2.S06: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  6
N0.C1.S02: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  6
N2.C0.D0.R1.S13: Total Delay in PI ticks: TxDQS = 924, TxDQ = 890
N4.C0.D1.R0.S03: Offset Found: RdPtrOffsetDqs = 007
N6.C2.S07: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  6
N0.C1.S03: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  6
N2.C0.D0.R1.S14: Total Delay in PI ticks: TxDQS = 942, TxDQ = 910
N4.C0.D1.R0.S04: Offset Found: RdPtrOffsetDqs = 006
N6.C2.S08: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  5
N0.C1.S04: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  5
N2.C0.D0.R1.S15: Total Delay in PI ticks: TxDQS = 947, TxDQ = 913
N4.C0.D1.R0.S05: Offset Found: RdPtrOffsetDqs = 006
N6.C3.S00: SuppressionWindowAdjustmentRd: latency =  9, rdptroffset =  5
N0.C1.S05: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  6
N2.C0.D0.R1.S16: Total Delay in PI ticks: TxDQS = 961, TxDQ = 927
N4.C0.D1.R0.S06: Offset Found: RdPtrOffsetDqs = 007
N6.C3.S01: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  6
N0.C1.S06: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  6
N2.C0.D0.R1.S17: Total Delay in PI ticks: TxDQS = 936, TxDQ = 901
N4.C0.D1.R0.S07: Offset Found: RdPtrOffsetDqs = 007
N6.C3.S02: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  6
N0.C1.S07: SuppressionWindowAdjustmentRd: latency =  9, rdptroffset =  5
N2.C0.D1.R0.S00: Total Delay in PI ticks: TxDQS = 1015, TxDQ = 980
N4.C0.D1.R0.S08: Offset Found: RdPtrOffsetDqs = 006
N6.C3.S03: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  6
N0.C1.S08: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  5
N2.C0.D1.R0.S01: Total Delay in PI ticks: TxDQS = 1001, TxDQ = 965
N4.C0.D1.R0: Write Training Coarse, upper nibbles
N6.C3.S04: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  6
N0.C2.S00: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  6
N2.C0.D1.R0.S02: Total Delay in PI ticks: TxDQS = 987, TxDQ = 952
N4.C0.D1.R0.S09: Dq Delay estimate: 466
N6.C3.S05: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  6
N0.C2.S01: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  6
N2.C0.D1.R0.S03: Total Delay in PI ticks: TxDQS = 969, TxDQ = 933
N4.C0.D1.R0.S10: Dq Delay estimate: 456
N6.C3.S06: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  6
N0.C2.S02: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  5
N2.C0.D1.R0.S04: Total Delay in PI ticks: TxDQS = 937, TxDQ = 900
N4.C0.D1.R0.S11: Dq Delay estimate: 442
N6.C3.S07: SuppressionWindowAdjustmentRd: latency =  9, rdptroffset =  5
N0.C2.S03: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  5
N2.C0.D1.R0.S05: Total Delay in PI ticks: TxDQS = 955, TxDQ = 920
N4.C0.D1.R0.S12: Dq Delay estimate: 425
N6.C3.S08: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  5
N0.C2.S04: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  5
N2.C0.D1.R0.S06: Total Delay in PI ticks: TxDQS = 958, TxDQ = 922
N4.C0.D1.R0.S13: Dq Delay estimate: 392

START - Basic Write Level Training
N0.C2.S05: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  5
N2.C0.D1.R0.S07: Total Delay in PI ticks: TxDQS = 974, TxDQ = 938
N4.C0.D1.R0.S14: Dq Delay estimate: 409
N6: START WRITE LEVEL:
N0.C2.S06: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  6
N2.C0.D1.R0.S08: Total Delay in PI ticks: TxDQS = 945, TxDQ = 908
N4.C0.D1.R0.S15: Dq Delay estimate: 413
N6.C0.D0.R0: ODT Override: 0x5
N0.C2.S07: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  6
N2.C0.D1.R0.S09: Total Delay in PI ticks: TxDQS = 1017, TxDQ = 982
N4.C0.D1.R0.S16: Dq Delay estimate: 426
N6.C0.D0.R0.S00: Write Level Fine Value = 503
N0.C2.S08: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  5
N2.C0.D1.R0.S10: Total Delay in PI ticks: TxDQS = 999, TxDQ = 964
N4.C0.D1.R0.S17: Dq Delay estimate: 400
N6.C0.D0.R0.S01: Write Level Fine Value = 481
N0.C3.S00: SuppressionWindowAdjustmentRd: latency =  9, rdptroffset =  5
N2.C0.D1.R0.S11: Total Delay in PI ticks: TxDQS = 989, TxDQ = 954
ACCM: F0 F0F0F0F0 F0F0F0F0
N6.C0.D0.R0.S02: Write Level Fine Value = 471
N0.C3.S01: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  6
N2.C0.D1.R0.S12: Total Delay in PI ticks: TxDQS = 973, TxDQ = 938
ACCM: F0 F0F0F0F0 F0F0F0F0
N6.C0.D0.R0.S03: Write Level Fine Value = 453
N0.C3.S02: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  6
N2.C0.D1.R0.S13: Total Delay in PI ticks: TxDQS = 938, TxDQ = 903
ACCM: F0 F0F0F0F0 F0F0F0F0
N6.C0.D0.R0.S04: Write Level Fine Value = 421
N0.C3.S03: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  6
N2.C0.D1.R0.S14: Total Delay in PI ticks: TxDQS = 957, TxDQ = 923
ACCM: F0 F0F0F0F0 F0F0F0F0
N6.C0.D0.R0.S05: Write Level Fine Value = 439
N0.C3.S04: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  6
N2.C0.D1.R0.S15: Total Delay in PI ticks: TxDQS = 958, TxDQ = 923
N4.C0.D1.R0: CheckMCTest: result = 0x3FE00
N6.C0.D0.R0.S06: Write Level Fine Value = 443
N0.C3.S05: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  6
N2.C0.D1.R0.S16: Total Delay in PI ticks: TxDQS = 974, TxDQ = 939
ACCM: F0 F0F0F0F0 F0F0F0F0
N6.C0.D0.R0.S07: Write Level Fine Value = 458
N0.C3.S06: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  6
N2.C0.D1.R0.S17: Total Delay in PI ticks: TxDQS = 946, TxDQ = 910
ACCM: F0 F0F0F0F0 F0F0F0F0
N6.C0.D0.R0.S08: Write Level Fine Value = 434
N0.C3.S07: SuppressionWindowAdjustmentRd: latency =  9, rdptroffset =  5
N2.C0.D1.R1.S00: Total Delay in PI ticks: TxDQS = 1010, TxDQ = 975
ACCM: F0 F0F0F0F0 F0F0F0F0
N6.C0.D0.R0.S09: Write Level Fine Value = 503
N0.C3.S08: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  5
N2.C0.D1.R1.S01: Total Delay in PI ticks: TxDQS = 998, TxDQ = 962
ACCM: F0 F0F0F0F0 F0F0F0F0
N6.C0.D0.R0.S10: Write Level Fine Value = 480

START - Basic Write Level Training
N2.C0.D1.R1.S02: Total Delay in PI ticks: TxDQS = 983, TxDQ = 948
N4.C0.D1.R0: CheckMCTest: result = 0x3FE00
N6.C0.D0.R0.S11: Write Level Fine Value = 470
Checkpoint Code: Socket 0, 0xB7, 0x03, 0x0000
N2.C0.D1.R1.S03: Total Delay in PI ticks: TxDQS = 967, TxDQ = 931
ACCM: F0 F0F0F0F0 F0F0F0F0
N6.C0.D0.R0.S12: Write Level Fine Value = 455
N0: START WRITE LEVEL:
N2.C0.D1.R1.S04: Total Delay in PI ticks: TxDQS = 932, TxDQ = 896
ACCM: F0 F0F0F0F0 F0F0F0F0
N6.C0.D0.R0.S13: Write Level Fine Value = 421
N0.C0.D0.R0: ODT Override: 0x5
N2.C0.D1.R1.S05: Total Delay in PI ticks: TxDQS = 952, TxDQ = 917
ACCM: 00 0000B0B0 0000B000
N6.C0.D0.R0.S14: Write Level Fine Value = 440
N0.C0.D0.R0.S00: Write Level Fine Value = 503
N2.C0.D1.R1.S06: Total Delay in PI ticks: TxDQS = 955, TxDQ = 918
ACCM: 00 0000B0B0 0000B000
N6.C0.D0.R0.S15: Write Level Fine Value = 441
N0.C0.D0.R0.S01: Write Level Fine Value = 486
N2.C0.D1.R1.S07: Total Delay in PI ticks: TxDQS = 972, TxDQ = 936
N4.C0.D1.R0: CheckMCTest: result = 0x3FE00
N6.C0.D0.R0.S16: Write Level Fine Value = 458
N0.C0.D0.R0.S02: Write Level Fine Value = 476
N2.C0.D1.R1.S08: Total Delay in PI ticks: TxDQS = 943, TxDQ = 906
ACCM: F0 F0F0F0F0 F0F0F0F0
N6.C0.D0.R0.S17: Write Level Fine Value = 436
N0.C0.D0.R0.S03: Write Level Fine Value = 456
N2.C0.D1.R1.S09: Total Delay in PI ticks: TxDQS = 1010, TxDQ = 975
ACCM: F0 F0F0F0F0 F0F0F0F0
N6.C0.D0.R1: ODT Override: 0x6
N0.C0.D0.R0.S04: Write Level Fine Value = 426
N2.C0.D1.R1.S10: Total Delay in PI ticks: TxDQS = 999, TxDQ = 963
ACCM: 00 0000F0F0 0000F000
N6.C0.D0.R1.S00: Write Level Fine Value = 496
N0.C0.D0.R0.S05: Write Level Fine Value = 442
N2.C0.D1.R1.S11: Total Delay in PI ticks: TxDQS = 985, TxDQ = 950
ACCM: 00 0000F0F0 0000F000
N6.C0.D0.R1.S01: Write Level Fine Value = 474
N0.C0.D0.R0.S06: Write Level Fine Value = 445
N2.C0.D1.R1.S12: Total Delay in PI ticks: TxDQS = 971, TxDQ = 936
N4.C0.D1.R0: CheckMCTest: result = 0x3FE00
N6.C0.D0.R1.S02: Write Level Fine Value = 464
N0.C0.D0.R0.S07: Write Level Fine Value = 462
N2.C0.D1.R1.S13: Total Delay in PI ticks: TxDQS = 933, TxDQ = 898
N4.C0.D1.R0: CheckMCTest: passed
N6.C0.D0.R1.S03: Write Level Fine Value = 447
N0.C0.D0.R0.S08: Write Level Fine Value = 436
N2.C0.D1.R1.S14: Total Delay in PI ticks: TxDQS = 951, TxDQ = 917
N4.C0.D1.R0: CheckMCTest: passed
N6.C0.D0.R1.S04: Write Level Fine Value = 414
N0.C0.D0.R0.S09: Write Level Fine Value = 505
N2.C0.D1.R1.S15: Total Delay in PI ticks: TxDQS = 955, TxDQ = 920
N4.C0.D1.R0.S09: Offset Found: RdPtrOffsetDqs = 007
N6.C0.D0.R1.S05: Write Level Fine Value = 433
N0.C0.D0.R0.S10: Write Level Fine Value = 485
N2.C0.D1.R1.S16: Total Delay in PI ticks: TxDQS = 971, TxDQ = 936
N4.C0.D1.R0.S10: Offset Found: RdPtrOffsetDqs = 007
N6.C0.D0.R1.S06: Write Level Fine Value = 435
N0.C0.D0.R0.S11: Write Level Fine Value = 476
N2.C0.D1.R1.S17: Total Delay in PI ticks: TxDQS = 943, TxDQ = 907
N4.C0.D1.R0.S11: Offset Found: RdPtrOffsetDqs = 007
N6.C0.D0.R1.S07: Write Level Fine Value = 452
N0.C0.D0.R0.S12: Write Level Fine Value = 459
N2.C1.D0.R0: Write Training Coarse, lower nibbles / bytes
N4.C0.D1.R0.S12: Offset Found: RdPtrOffsetDqs = 007
N6.C0.D0.R1.S08: Write Level Fine Value = 425
N0.C0.D0.R0.S13: Write Level Fine Value = 426
N2.C1.D0.R0.S00: Dq Delay estimate: 466
N4.C0.D1.R0.S13: Offset Found: RdPtrOffsetDqs = 006
N6.C0.D0.R1.S09: Write Level Fine Value = 493
N0.C0.D0.R0.S14: Write Level Fine Value = 440
N2.C1.D0.R0.S01: Dq Delay estimate: 448
N4.C0.D1.R0.S14: Offset Found: RdPtrOffsetDqs = 006
N6.C0.D0.R1.S10: Write Level Fine Value = 476
N0.C0.D0.R0.S15: Write Level Fine Value = 445
N2.C1.D0.R0.S02: Dq Delay estimate: 443
N4.C0.D1.R0.S15: Offset Found: RdPtrOffsetDqs = 007
N6.C0.D0.R1.S11: Write Level Fine Value = 463
N0.C0.D0.R0.S16: Write Level Fine Value = 463
N2.C1.D0.R0.S03: Dq Delay estimate: 423
N4.C0.D1.R0.S16: Offset Found: RdPtrOffsetDqs = 007
N6.C0.D0.R1.S12: Write Level Fine Value = 451
N0.C0.D0.R0.S17: Write Level Fine Value = 434
N2.C1.D0.R0.S04: Dq Delay estimate: 391
N4.C0.D1.R0.S17: Offset Found: RdPtrOffsetDqs = 006
N6.C0.D0.R1.S13: Write Level Fine Value = 415
N0.C0.D0.R1: ODT Override: 0x6
N2.C1.D0.R0.S05: Dq Delay estimate: 406
N4.C0.D1.R1: Write Training Coarse, lower nibbles / bytes
N6.C0.D0.R1.S14: Write Level Fine Value = 432
N0.C0.D0.R1.S00: Write Level Fine Value = 498
N2.C1.D0.R0.S06: Dq Delay estimate: 421
N4.C0.D1.R1.S00: Dq Delay estimate: 467
N6.C0.D0.R1.S15: Write Level Fine Value = 435
N0.C0.D0.R1.S01: Write Level Fine Value = 480
N2.C1.D0.R0.S07: Dq Delay estimate: 436
N4.C0.D1.R1.S01: Dq Delay estimate: 451
N6.C0.D0.R1.S16: Write Level Fine Value = 453
N0.C0.D0.R1.S02: Write Level Fine Value = 468
N2.C1.D0.R0.S08: Dq Delay estimate: 410
N4.C0.D1.R1.S02: Dq Delay estimate: 439
N6.C0.D0.R1.S17: Write Level Fine Value = 425
N0.C0.D0.R1.S03: Write Level Fine Value = 450
ACCM: 9F 0FFF9F9F 0F0F0F0F
N4.C0.D1.R1.S03: Dq Delay estimate: 424
N6.C0.D1.R0: ODT Override: 0x5
N0.C0.D0.R1.S04: Write Level Fine Value = 419
ACCM: 9F 0FFF9F9F 0F0F0F0F
N4.C0.D1.R1.S04: Dq Delay estimate: 386
N6.C0.D1.R0.S00: Write Level Fine Value = 502
N0.C0.D0.R1.S05: Write Level Fine Value = 435
ACCM: 9F FFFF9F9F FFFFFFFF
N4.C0.D1.R1.S05: Dq Delay estimate: 408
N6.C0.D1.R0.S01: Write Level Fine Value = 485
N0.C0.D0.R1.S06: Write Level Fine Value = 437
ACCM: 9F FFFF9F9F FFFFFFFF
N4.C0.D1.R1.S06: Dq Delay estimate: 407
N6.C0.D1.R0.S02: Write Level Fine Value = 473
N0.C0.D0.R1.S07: Write Level Fine Value = 456
N2.C1.D0.R0: CheckMCTest: result = 0x3FFFF
N4.C0.D1.R1.S07: Dq Delay estimate: 424
N6.C0.D1.R0.S03: Write Level Fine Value = 460
N0.C0.D0.R1.S08: Write Level Fine Value = 427
ACCM: DF 0FFFDFDF 0F0F0F0F
N4.C0.D1.R1.S08: Dq Delay estimate: 393
N6.C0.D1.R0.S04: Write Level Fine Value = 423
N0.C0.D0.R1.S09: Write Level Fine Value = 496
ACCM: DF 0FFFDFDF 0F0F0F0F
ACCM: 0F 0F0F0F0F 0F0F0F0F
N6.C0.D1.R0.S05: Write Level Fine Value = 441
N0.C0.D0.R1.S10: Write Level Fine Value = 481
ACCM: DF FFFFDFDF FFFFFFFF
ACCM: 0F 0F0F0F0F 0F0F0F0F
N6.C0.D1.R0.S06: Write Level Fine Value = 444
N0.C0.D0.R1.S11: Write Level Fine Value = 468
ACCM: DF FFFFDFDF FFFFFFFF
ACCM: 0F 0F0F0F0F 0F0F0F0F
N6.C0.D1.R0.S07: Write Level Fine Value = 462
N0.C0.D0.R1.S12: Write Level Fine Value = 454
N2.C1.D0.R0: CheckMCTest: result = 0x3FFFF
ACCM: 0F 0F0F0F0F 0F0F0F0F
N6.C0.D1.R0.S08: Write Level Fine Value = 432
N0.C0.D0.R1.S13: Write Level Fine Value = 421
ACCM: DF 0FFFDFDF 0F0F0F0F
N4.C0.D1.R1: CheckMCTest: result = 0x1FF
N6.C0.D1.R0.S09: Write Level Fine Value = 504
N0.C0.D0.R1.S14: Write Level Fine Value = 437
ACCM: DF 0FFFDFDF 0F0F0F0F
ACCM: 0F 0F0F0F0F 0F0F0F0F
N6.C0.D1.R0.S10: Write Level Fine Value = 486
N0.C0.D0.R1.S15: Write Level Fine Value = 440
ACCM: D0 FBFBDBDB FBF0FBFB
ACCM: 0F 0F0F0F0F 0F0F0F0F
N6.C0.D1.R0.S11: Write Level Fine Value = 471
N0.C0.D0.R1.S16: Write Level Fine Value = 456
ACCM: D0 FBFBDBDB FBF0FBFB
ACCM: 0F 0F0F0F0F 0F0F0F0F
N6.C0.D1.R0.S12: Write Level Fine Value = 459
N0.C0.D0.R1.S17: Write Level Fine Value = 427
N2.C1.D0.R0: CheckMCTest: result = 0x3FFFF
ACCM: 0F 0F0F0F0F 0F0F0F0F
N6.C0.D1.R0.S13: Write Level Fine Value = 424
N0.C0.D1.R0: ODT Override: 0x5
ACCM: DF 0FFFDFDF 0F0F0F0F
N4.C0.D1.R1: CheckMCTest: result = 0x1FF
N6.C0.D1.R0.S14: Write Level Fine Value = 443
N0.C0.D1.R0.S00: Write Level Fine Value = 509
ACCM: DF 0FFFDFDF 0F0F0F0F
ACCM: 0F 0F0F0F0F 0F0F0F0F
N6.C0.D1.R0.S15: Write Level Fine Value = 445
N0.C0.D1.R0.S01: Write Level Fine Value = 493
ACCM: D0 FFFFDFDF FFFDFFFF
ACCM: 0F 0F0F0F0F 0F0F0F0F
N6.C0.D1.R0.S16: Write Level Fine Value = 463
N0.C0.D1.R0.S02: Write Level Fine Value = 480
ACCM: D0 FFFFDFDF FFFDFFFF
ACCM: 0B 0B00000B 00000000
N6.C0.D1.R0.S17: Write Level Fine Value = 433
N0.C0.D1.R0.S03: Write Level Fine Value = 463
N2.C1.D0.R0: CheckMCTest: result = 0x3FFFF
ACCM: 0B 0B00000B 00000000
N6.C0.D1.R1: ODT Override: 0x9
N0.C0.D1.R0.S04: Write Level Fine Value = 429
ACCM: D0 00F0D0D0 00000000
N4.C0.D1.R1: CheckMCTest: result = 0x1FF
N6.C0.D1.R1.S00: Write Level Fine Value = 497
N0.C0.D1.R0.S05: Write Level Fine Value = 448
ACCM: D0 00F0D0D0 00000000
ACCM: 0F 0F0F0F0F 0F0F0F0F
N6.C0.D1.R1.S01: Write Level Fine Value = 481
N0.C0.D1.R0.S06: Write Level Fine Value = 448
ACCM: D0 F0F0D0D0 F0F0F0F0
ACCM: 0F 0F0F0F0F 0F0F0F0F
N6.C0.D1.R1.S02: Write Level Fine Value = 468
N0.C0.D1.R0.S07: Write Level Fine Value = 466
ACCM: D0 F0F0D0D0 F0F0F0F0
ACCM: 0F 0F00000F 00000000
N6.C0.D1.R1.S03: Write Level Fine Value = 455
N0.C0.D1.R0.S08: Write Level Fine Value = 438
N2.C1.D0.R0: CheckMCTest: result = 0x3FE00
ACCM: 0F 0F00000F 00000000
N6.C0.D1.R1.S04: Write Level Fine Value = 420
N0.C0.D1.R0.S09: Write Level Fine Value = 505
ACCM: D0 00F0D0D0 00000000
N4.C0.D1.R1: CheckMCTest: result = 0x1FF
N6.C0.D1.R1.S05: Write Level Fine Value = 440
N0.C0.D1.R0.S10: Write Level Fine Value = 493
ACCM: D0 00F0D0D0 00000000
N4.C0.D1.R1: CheckMCTest: passed
N6.C0.D1.R1.S06: Write Level Fine Value = 442
N0.C0.D1.R0.S11: Write Level Fine Value = 479
ACCM: D0 F0F0D0D0 F0F0F0F0
N4.C0.D1.R1: CheckMCTest: passed
N6.C0.D1.R1.S07: Write Level Fine Value = 459
N0.C0.D1.R0.S12: Write Level Fine Value = 465
ACCM: D0 F0F0D0D0 F0F0F0F0
N4.C0.D1.R1.S00: Offset Found: RdPtrOffsetDqs = 007
N6.C0.D1.R1.S08: Write Level Fine Value = 428
N0.C0.D1.R0.S13: Write Level Fine Value = 430
N2.C1.D0.R0: CheckMCTest: result = 0x3FE00
N4.C0.D1.R1.S01: Offset Found: RdPtrOffsetDqs = 007
N6.C0.D1.R1.S09: Write Level Fine Value = 497
N0.C0.D1.R0.S14: Write Level Fine Value = 446
N2.C1.D0.R0.S00: Offset Found: RdPtrOffsetDqs = 007
N4.C0.D1.R1.S02: Offset Found: RdPtrOffsetDqs = 007
N6.C0.D1.R1.S10: Write Level Fine Value = 483
N0.C0.D1.R0.S15: Write Level Fine Value = 450
N2.C1.D0.R0.S01: Offset Found: RdPtrOffsetDqs = 007
N4.C0.D1.R1.S03: Offset Found: RdPtrOffsetDqs = 007
N6.C0.D1.R1.S11: Write Level Fine Value = 470
N0.C0.D1.R0.S16: Write Level Fine Value = 467
N2.C1.D0.R0.S02: Offset Found: RdPtrOffsetDqs = 007
N4.C0.D1.R1.S04: Offset Found: RdPtrOffsetDqs = 006
N6.C0.D1.R1.S12: Write Level Fine Value = 455
N0.C0.D1.R0.S17: Write Level Fine Value = 439
N2.C1.D0.R0.S03: Offset Found: RdPtrOffsetDqs = 007
N4.C0.D1.R1.S05: Offset Found: RdPtrOffsetDqs = 006
N6.C0.D1.R1.S13: Write Level Fine Value = 420
N0.C0.D1.R1: ODT Override: 0x9
N2.C1.D0.R0.S04: Offset Found: RdPtrOffsetDqs = 006
N4.C0.D1.R1.S06: Offset Found: RdPtrOffsetDqs = 006
N6.C0.D1.R1.S14: Write Level Fine Value = 439
N0.C0.D1.R1.S00: Write Level Fine Value = 504
N2.C1.D0.R0.S05: Offset Found: RdPtrOffsetDqs = 006
N4.C0.D1.R1.S07: Offset Found: RdPtrOffsetDqs = 007
N6.C0.D1.R1.S15: Write Level Fine Value = 442
N0.C0.D1.R1.S01: Write Level Fine Value = 488
N2.C1.D0.R0.S06: Offset Found: RdPtrOffsetDqs = 007
N4.C0.D1.R1.S08: Offset Found: RdPtrOffsetDqs = 006
N6.C0.D1.R1.S16: Write Level Fine Value = 456
N0.C0.D1.R1.S02: Write Level Fine Value = 478
N2.C1.D0.R0.S07: Offset Found: RdPtrOffsetDqs = 007
N4.C0.D1.R1: Write Training Coarse, upper nibbles
N6.C0.D1.R1.S17: Write Level Fine Value = 428
N0.C0.D1.R1.S03: Write Level Fine Value = 461
N2.C1.D0.R0.S08: Offset Found: RdPtrOffsetDqs = 006
N4.C0.D1.R1.S09: Dq Delay estimate: 465
N6.C1.D0.R0: ODT Override: 0x5
N0.C0.D1.R1.S04: Write Level Fine Value = 426
N2.C1.D0.R0: Write Training Coarse, upper nibbles
N4.C0.D1.R1.S10: Dq Delay estimate: 454
N6.C1.D0.R0.S00: Write Level Fine Value = 502
N0.C0.D1.R1.S05: Write Level Fine Value = 447
N2.C1.D0.R0.S09: Dq Delay estimate: 467
N4.C0.D1.R1.S11: Dq Delay estimate: 441
N6.C1.D0.R0.S01: Write Level Fine Value = 486
N0.C0.D1.R1.S06: Write Level Fine Value = 447
N2.C1.D0.R0.S10: Dq Delay estimate: 450
N4.C0.D1.R1.S12: Dq Delay estimate: 425
N6.C1.D0.R0.S02: Write Level Fine Value = 476
N0.C0.D1.R1.S07: Write Level Fine Value = 465
N2.C1.D0.R0.S11: Dq Delay estimate: 443
N4.C0.D1.R1.S13: Dq Delay estimate: 391
N6.C1.D0.R0.S03: Write Level Fine Value = 460
N0.C0.D1.R1.S08: Write Level Fine Value = 431
N2.C1.D0.R0.S12: Dq Delay estimate: 426
N4.C0.D1.R1.S14: Dq Delay estimate: 404
N6.C1.D0.R0.S04: Write Level Fine Value = 427
N0.C0.D1.R1.S09: Write Level Fine Value = 504
N2.C1.D0.R0.S13: Dq Delay estimate: 395
N4.C0.D1.R1.S15: Dq Delay estimate: 410
N6.C1.D0.R0.S05: Write Level Fine Value = 441
N0.C0.D1.R1.S10: Write Level Fine Value = 490
N2.C1.D0.R0.S14: Dq Delay estimate: 405
N4.C0.D1.R1.S16: Dq Delay estimate: 424
N6.C1.D0.R0.S06: Write Level Fine Value = 458
N0.C0.D1.R1.S11: Write Level Fine Value = 478
N2.C1.D0.R0.S15: Dq Delay estimate: 419
N4.C0.D1.R1.S17: Dq Delay estimate: 395
N6.C1.D0.R0.S07: Write Level Fine Value = 473
N0.C0.D1.R1.S12: Write Level Fine Value = 462
N2.C1.D0.R0.S16: Dq Delay estimate: 437
ACCM: F0 F0F0F0F0 F0F0F0F0
N6.C1.D0.R0.S08: Write Level Fine Value = 443
N0.C0.D1.R1.S13: Write Level Fine Value = 429
N2.C1.D0.R0.S17: Dq Delay estimate: 410
ACCM: F0 F0F0F0F0 F0F0F0F0
N6.C1.D0.R0.S09: Write Level Fine Value = 503
N0.C0.D1.R1.S14: Write Level Fine Value = 446
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: F0 F0F0F0F0 F0F0F0F0
N6.C1.D0.R0.S10: Write Level Fine Value = 485
N0.C0.D1.R1.S15: Write Level Fine Value = 448
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: F0 F0F0F0F0 F0F0F0F0
N6.C1.D0.R0.S11: Write Level Fine Value = 478
N0.C0.D1.R1.S16: Write Level Fine Value = 464
ACCM: F0 F0F0F0F0 F0F0F0F0
N4.C0.D1.R1: CheckMCTest: result = 0x3FE00
N6.C1.D0.R0.S12: Write Level Fine Value = 461
N0.C0.D1.R1.S17: Write Level Fine Value = 433
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: F0 F0F0F0F0 F0F0F0F0
N6.C1.D0.R0.S13: Write Level Fine Value = 426
N0.C1.D0.R0: ODT Override: 0x5
N2.C1.D0.R0: CheckMCTest: result = 0x3FE00
ACCM: F0 F0F0F0F0 F0F0F0F0
N6.C1.D0.R0.S14: Write Level Fine Value = 440
N0.C1.D0.R0.S00: Write Level Fine Value = 507
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: F0 F0F0F0F0 F0F0F0F0
N6.C1.D0.R0.S15: Write Level Fine Value = 456
N0.C1.D0.R0.S01: Write Level Fine Value = 487
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: F0 F0F0F0F0 F0F0F0F0
N6.C1.D0.R0.S16: Write Level Fine Value = 472
N0.C1.D0.R0.S02: Write Level Fine Value = 481
ACCM: F0 F0F0F0F0 F0F0F0F0
N4.C0.D1.R1: CheckMCTest: result = 0x3FE00
N6.C1.D0.R0.S17: Write Level Fine Value = 443
N0.C1.D0.R0.S03: Write Level Fine Value = 461
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: F0 F0F0F0F0 F0F0F0F0
N6.C1.D0.R1: ODT Override: 0x6
N0.C1.D0.R0.S04: Write Level Fine Value = 426
N2.C1.D0.R0: CheckMCTest: result = 0x3FE00
ACCM: F0 F0F0F0F0 F0F0F0F0
N6.C1.D0.R1.S00: Write Level Fine Value = 497
N0.C1.D0.R0.S05: Write Level Fine Value = 444
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: 00 000000B0 00B0B000
N6.C1.D0.R1.S01: Write Level Fine Value = 479
N0.C1.D0.R0.S06: Write Level Fine Value = 459
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: 00 000000B0 00B0B000
N6.C1.D0.R1.S02: Write Level Fine Value = 471
N0.C1.D0.R0.S07: Write Level Fine Value = 475
ACCM: 00 B0B000B0 B00000B0
N4.C0.D1.R1: CheckMCTest: result = 0x3FE00
N6.C1.D0.R1.S03: Write Level Fine Value = 453
N0.C1.D0.R0.S08: Write Level Fine Value = 442
ACCM: 00 B0B000B0 B00000B0
ACCM: F0 F0F0F0F0 F0F0F0F0
N6.C1.D0.R1.S04: Write Level Fine Value = 423
N0.C1.D0.R0.S09: Write Level Fine Value = 506
N2.C1.D0.R0: CheckMCTest: result = 0x3FE00
ACCM: F0 F0F0F0F0 F0F0F0F0
N6.C1.D0.R1.S05: Write Level Fine Value = 435
N0.C1.D0.R0.S10: Write Level Fine Value = 488
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: 00 000000F0 00F0F000
N6.C1.D0.R1.S06: Write Level Fine Value = 449
N0.C1.D0.R0.S11: Write Level Fine Value = 482
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: 00 000000F0 00F0F000
N6.C1.D0.R1.S07: Write Level Fine Value = 465
N0.C1.D0.R0.S12: Write Level Fine Value = 463
ACCM: 00 F0F0D0F0 F000D0F0
N4.C0.D1.R1: CheckMCTest: result = 0x3FE00
N6.C1.D0.R1.S08: Write Level Fine Value = 436
N0.C1.D0.R0.S13: Write Level Fine Value = 427
ACCM: 00 F0F0D0F0 F000D0F0
N4.C0.D1.R1: CheckMCTest: passed
N6.C1.D0.R1.S09: Write Level Fine Value = 495
N0.C1.D0.R0.S14: Write Level Fine Value = 442
N2.C1.D0.R0: CheckMCTest: result = 0x3FE00
N4.C0.D1.R1: CheckMCTest: passed
N6.C1.D0.R1.S10: Write Level Fine Value = 479
N0.C1.D0.R0.S15: Write Level Fine Value = 458
N2.C1.D0.R0: CheckMCTest: passed
N4.C0.D1.R1.S09: Offset Found: RdPtrOffsetDqs = 007
N6.C1.D0.R1.S11: Write Level Fine Value = 471
N0.C1.D0.R0.S16: Write Level Fine Value = 475
N2.C1.D0.R0: CheckMCTest: passed
N4.C0.D1.R1.S10: Offset Found: RdPtrOffsetDqs = 007
N6.C1.D0.R1.S12: Write Level Fine Value = 454
N0.C1.D0.R0.S17: Write Level Fine Value = 445
N2.C1.D0.R0.S09: Offset Found: RdPtrOffsetDqs = 007
N4.C0.D1.R1.S11: Offset Found: RdPtrOffsetDqs = 007
N6.C1.D0.R1.S13: Write Level Fine Value = 421
N0.C1.D0.R1: ODT Override: 0x6
N2.C1.D0.R0.S10: Offset Found: RdPtrOffsetDqs = 007
N4.C0.D1.R1.S12: Offset Found: RdPtrOffsetDqs = 007
N6.C1.D0.R1.S14: Write Level Fine Value = 433
N0.C1.D0.R1.S00: Write Level Fine Value = 498
N2.C1.D0.R0.S11: Offset Found: RdPtrOffsetDqs = 007
N4.C0.D1.R1.S13: Offset Found: RdPtrOffsetDqs = 006
N6.C1.D0.R1.S15: Write Level Fine Value = 449
N0.C1.D0.R1.S01: Write Level Fine Value = 480
N2.C1.D0.R0.S12: Offset Found: RdPtrOffsetDqs = 007
N4.C0.D1.R1.S14: Offset Found: RdPtrOffsetDqs = 006
N6.C1.D0.R1.S16: Write Level Fine Value = 466
N0.C1.D0.R1.S02: Write Level Fine Value = 473
N2.C1.D0.R0.S13: Offset Found: RdPtrOffsetDqs = 006
N4.C0.D1.R1.S15: Offset Found: RdPtrOffsetDqs = 006
N6.C1.D0.R1.S17: Write Level Fine Value = 434
N0.C1.D0.R1.S03: Write Level Fine Value = 456
N2.C1.D0.R0.S14: Offset Found: RdPtrOffsetDqs = 006
N4.C0.D1.R1.S16: Offset Found: RdPtrOffsetDqs = 007
N6.C1.D1.R0: ODT Override: 0x5
N0.C1.D0.R1.S04: Write Level Fine Value = 420
N2.C1.D0.R0.S15: Offset Found: RdPtrOffsetDqs = 007
N4.C0.D1.R1.S17: Offset Found: RdPtrOffsetDqs = 006
N6.C1.D1.R0.S00: Write Level Fine Value = 506
N0.C1.D0.R1.S05: Write Level Fine Value = 437
N2.C1.D0.R0.S16: Offset Found: RdPtrOffsetDqs = 007
N4.C0: Calculating Optimimum DQS Values
N6.C1.D1.R0.S01: Write Level Fine Value = 490
N0.C1.D0.R1.S06: Write Level Fine Value = 450
N2.C1.D0.R0.S17: Offset Found: RdPtrOffsetDqs = 006
N4.C0.D0.R0.S00: Total Delay in PI ticks: TxDQS = 1019, TxDQ = 982
N6.C1.D1.R0.S02: Write Level Fine Value = 480
N0.C1.D0.R1.S07: Write Level Fine Value = 468
N2.C1.D0.R1: Write Training Coarse, lower nibbles / bytes
N4.C0.D0.R0.S01: Total Delay in PI ticks: TxDQS = 998, TxDQ = 961
N6.C1.D1.R0.S03: Write Level Fine Value = 465
N0.C1.D0.R1.S08: Write Level Fine Value = 437
N2.C1.D0.R1.S00: Dq Delay estimate: 460
N4.C0.D0.R0.S02: Total Delay in PI ticks: TxDQS = 991, TxDQ = 953
N6.C1.D1.R0.S04: Write Level Fine Value = 432
N0.C1.D0.R1.S09: Write Level Fine Value = 497
N2.C1.D0.R1.S01: Dq Delay estimate: 442
N4.C0.D0.R0.S03: Total Delay in PI ticks: TxDQS = 970, TxDQ = 933
N6.C1.D1.R0.S05: Write Level Fine Value = 447
N0.C1.D0.R1.S10: Write Level Fine Value = 481
N2.C1.D0.R1.S02: Dq Delay estimate: 435
N4.C0.D0.R0.S04: Total Delay in PI ticks: TxDQS = 940, TxDQ = 903
N6.C1.D1.R0.S06: Write Level Fine Value = 459
N0.C1.D0.R1.S11: Write Level Fine Value = 471
N2.C1.D0.R1.S03: Dq Delay estimate: 417
N4.C0.D0.R0.S05: Total Delay in PI ticks: TxDQS = 958, TxDQ = 921
N6.C1.D1.R0.S07: Write Level Fine Value = 476
N0.C1.D0.R1.S12: Write Level Fine Value = 457
N2.C1.D0.R1.S04: Dq Delay estimate: 386
N4.C0.D0.R0.S06: Total Delay in PI ticks: TxDQS = 960, TxDQ = 922
N6.C1.D1.R0.S08: Write Level Fine Value = 446
N0.C1.D0.R1.S13: Write Level Fine Value = 423
N2.C1.D0.R1.S05: Dq Delay estimate: 400
N4.C0.D0.R0.S07: Total Delay in PI ticks: TxDQS = 974, TxDQ = 936
N6.C1.D1.R0.S09: Write Level Fine Value = 506
N0.C1.D0.R1.S14: Write Level Fine Value = 440
N2.C1.D0.R1.S06: Dq Delay estimate: 412
N4.C0.D0.R0.S08: Total Delay in PI ticks: TxDQS = 952, TxDQ = 915
N6.C1.D1.R0.S10: Write Level Fine Value = 490
N0.C1.D0.R1.S15: Write Level Fine Value = 450
N2.C1.D0.R1.S07: Dq Delay estimate: 429
N4.C0.D0.R0.S09: Total Delay in PI ticks: TxDQS = 1017, TxDQ = 979
N6.C1.D1.R0.S11: Write Level Fine Value = 481
N0.C1.D0.R1.S16: Write Level Fine Value = 471
N2.C1.D0.R1.S08: Dq Delay estimate: 402
N4.C0.D0.R0.S10: Total Delay in PI ticks: TxDQS = 998, TxDQ = 961
N6.C1.D1.R0.S12: Write Level Fine Value = 466
N0.C1.D0.R1.S17: Write Level Fine Value = 435
ACCM: 0F 0F0F0F0F 0F0F0F0F
N4.C0.D0.R0.S11: Total Delay in PI ticks: TxDQS = 986, TxDQ = 949
N6.C1.D1.R0.S13: Write Level Fine Value = 433
N0.C1.D1.R0: ODT Override: 0x5
ACCM: 0F 0F0F0F0F 0F0F0F0F
N4.C0.D0.R0.S12: Total Delay in PI ticks: TxDQS = 970, TxDQ = 933
N6.C1.D1.R0.S14: Write Level Fine Value = 445
N0.C1.D1.R0.S00: Write Level Fine Value = 509
ACCM: 0F 0F0F0F0F 0F0F0F0F
N4.C0.D0.R0.S13: Total Delay in PI ticks: TxDQS = 940, TxDQ = 904
N6.C1.D1.R0.S15: Write Level Fine Value = 458
N0.C1.D1.R0.S01: Write Level Fine Value = 491
ACCM: 0F 0F0F0F0F 0F0F0F0F
N4.C0.D0.R0.S14: Total Delay in PI ticks: TxDQS = 952, TxDQ = 915
N6.C1.D1.R0.S16: Write Level Fine Value = 480
N0.C1.D1.R0.S02: Write Level Fine Value = 483
N2.C1.D0.R1: CheckMCTest: result = 0x1FF
N4.C0.D0.R0.S15: Total Delay in PI ticks: TxDQS = 958, TxDQ = 922
N6.C1.D1.R0.S17: Write Level Fine Value = 445
N0.C1.D1.R0.S03: Write Level Fine Value = 471
ACCM: 0F 0F0F0F0F 0F0F0F0F
N4.C0.D0.R0.S16: Total Delay in PI ticks: TxDQS = 974, TxDQ = 937
N6.C1.D1.R1: ODT Override: 0x9
N0.C1.D1.R0.S04: Write Level Fine Value = 435
ACCM: 0F 0F0F0F0F 0F0F0F0F
N4.C0.D0.R0.S17: Total Delay in PI ticks: TxDQS = 951, TxDQ = 915
N6.C1.D1.R1.S00: Write Level Fine Value = 502
N0.C1.D1.R0.S05: Write Level Fine Value = 449
ACCM: 0F 0F0F0F0F 0F0F0F0F
N4.C0.D0.R1.S00: Total Delay in PI ticks: TxDQS = 1011, TxDQ = 975
N6.C1.D1.R1.S01: Write Level Fine Value = 485
N0.C1.D1.R0.S06: Write Level Fine Value = 466
ACCM: 0F 0F0F0F0F 0F0F0F0F
N4.C0.D0.R1.S01: Total Delay in PI ticks: TxDQS = 993, TxDQ = 957
N6.C1.D1.R1.S02: Write Level Fine Value = 475
N0.C1.D1.R0.S07: Write Level Fine Value = 482
N2.C1.D0.R1: CheckMCTest: result = 0x1FF
N4.C0.D0.R1.S02: Total Delay in PI ticks: TxDQS = 983, TxDQ = 945
N6.C1.D1.R1.S03: Write Level Fine Value = 461
N0.C1.D1.R0.S08: Write Level Fine Value = 450
ACCM: 0F 0F0F0F0F 0F0F0F0F
N4.C0.D0.R1.S03: Total Delay in PI ticks: TxDQS = 967, TxDQ = 930
N6.C1.D1.R1.S04: Write Level Fine Value = 427
N0.C1.D1.R0.S09: Write Level Fine Value = 510
ACCM: 0F 0F0F0F0F 0F0F0F0F
N4.C0.D0.R1.S04: Total Delay in PI ticks: TxDQS = 931, TxDQ = 894
N6.C1.D1.R1.S05: Write Level Fine Value = 443
N0.C1.D1.R0.S10: Write Level Fine Value = 492
ACCM: 00 0000000B 0B00000B
N4.C0.D0.R1.S05: Total Delay in PI ticks: TxDQS = 950, TxDQ = 913
N6.C1.D1.R1.S06: Write Level Fine Value = 453
N0.C1.D1.R0.S11: Write Level Fine Value = 484
ACCM: 00 0000000B 0B00000B
N4.C0.D0.R1.S06: Total Delay in PI ticks: TxDQS = 951, TxDQ = 913
N6.C1.D1.R1.S07: Write Level Fine Value = 473
N0.C1.D1.R0.S12: Write Level Fine Value = 471
N2.C1.D0.R1: CheckMCTest: result = 0x1FF
N4.C0.D0.R1.S07: Total Delay in PI ticks: TxDQS = 966, TxDQ = 928
N6.C1.D1.R1.S08: Write Level Fine Value = 441
N0.C1.D1.R0.S13: Write Level Fine Value = 435
ACCM: 0F 0F0F0F0F 0F0F0F0F
N4.C0.D0.R1.S08: Total Delay in PI ticks: TxDQS = 944, TxDQ = 907
N6.C1.D1.R1.S09: Write Level Fine Value = 501
N0.C1.D1.R0.S14: Write Level Fine Value = 450
ACCM: 0F 0F0F0F0F 0F0F0F0F
N4.C0.D0.R1.S09: Total Delay in PI ticks: TxDQS = 1010, TxDQ = 972
N6.C1.D1.R1.S10: Write Level Fine Value = 487
N0.C1.D1.R0.S15: Write Level Fine Value = 464
ACCM: 00 0000000F 0F00000F
N4.C0.D0.R1.S10: Total Delay in PI ticks: TxDQS = 993, TxDQ = 957
N6.C1.D1.R1.S11: Write Level Fine Value = 478
N0.C1.D1.R0.S16: Write Level Fine Value = 481
ACCM: 00 0000000F 0F00000F
N4.C0.D0.R1.S11: Total Delay in PI ticks: TxDQS = 983, TxDQ = 946
N6.C1.D1.R1.S12: Write Level Fine Value = 464
N0.C1.D1.R0.S17: Write Level Fine Value = 448
N2.C1.D0.R1: CheckMCTest: result = 0x1FF
N4.C0.D0.R1.S12: Total Delay in PI ticks: TxDQS = 967, TxDQ = 929
N6.C1.D1.R1.S13: Write Level Fine Value = 428
N0.C1.D1.R1: ODT Override: 0x9
N2.C1.D0.R1: CheckMCTest: passed
N4.C0.D0.R1.S13: Total Delay in PI ticks: TxDQS = 933, TxDQ = 897
N6.C1.D1.R1.S14: Write Level Fine Value = 443
N0.C1.D1.R1.S00: Write Level Fine Value = 506
N2.C1.D0.R1: CheckMCTest: passed
N4.C0.D0.R1.S14: Total Delay in PI ticks: TxDQS = 947, TxDQ = 910
N6.C1.D1.R1.S15: Write Level Fine Value = 453
N0.C1.D1.R1.S01: Write Level Fine Value = 489
N2.C1.D0.R1.S00: Offset Found: RdPtrOffsetDqs = 007
N4.C0.D0.R1.S15: Total Delay in PI ticks: TxDQS = 952, TxDQ = 916
N6.C1.D1.R1.S16: Write Level Fine Value = 474
N0.C1.D1.R1.S02: Write Level Fine Value = 481
N2.C1.D0.R1.S01: Offset Found: RdPtrOffsetDqs = 007
N4.C0.D0.R1.S16: Total Delay in PI ticks: TxDQS = 967, TxDQ = 931
N6.C1.D1.R1.S17: Write Level Fine Value = 441
N0.C1.D1.R1.S03: Write Level Fine Value = 467
N2.C1.D0.R1.S02: Offset Found: RdPtrOffsetDqs = 007
N4.C0.D0.R1.S17: Total Delay in PI ticks: TxDQS = 942, TxDQ = 905
N6.C2.D0.R0: ODT Override: 0x5
N0.C1.D1.R1.S04: Write Level Fine Value = 433
N2.C1.D0.R1.S03: Offset Found: RdPtrOffsetDqs = 007
N4.C0.D1.R0.S00: Total Delay in PI ticks: TxDQS = 1019, TxDQ = 981
N6.C2.D0.R0.S00: Write Level Fine Value = 496
N0.C1.D1.R1.S05: Write Level Fine Value = 446
N2.C1.D0.R1.S04: Offset Found: RdPtrOffsetDqs = 006
N4.C0.D1.R0.S01: Total Delay in PI ticks: TxDQS = 1006, TxDQ = 968
N6.C2.D0.R0.S01: Write Level Fine Value = 483
N0.C1.D1.R1.S06: Write Level Fine Value = 458
N2.C1.D0.R1.S05: Offset Found: RdPtrOffsetDqs = 006
N4.C0.D1.R0.S02: Total Delay in PI ticks: TxDQS = 993, TxDQ = 954
N6.C2.D0.R0.S02: Write Level Fine Value = 472
N0.C1.D1.R1.S07: Write Level Fine Value = 481
N2.C1.D0.R1.S06: Offset Found: RdPtrOffsetDqs = 006
N4.C0.D1.R0.S03: Total Delay in PI ticks: TxDQS = 975, TxDQ = 937
N6.C2.D0.R0.S03: Write Level Fine Value = 452
N0.C1.D1.R1.S08: Write Level Fine Value = 444
N2.C1.D0.R1.S07: Offset Found: RdPtrOffsetDqs = 007
N4.C0.D1.R0.S04: Total Delay in PI ticks: TxDQS = 942, TxDQ = 903
N6.C2.D0.R0.S04: Write Level Fine Value = 414
N0.C1.D1.R1.S09: Write Level Fine Value = 506
N2.C1.D0.R1.S08: Offset Found: RdPtrOffsetDqs = 006
N4.C0.D1.R0.S05: Total Delay in PI ticks: TxDQS = 959, TxDQ = 921
N6.C2.D0.R0.S05: Write Level Fine Value = 443
N0.C1.D1.R1.S10: Write Level Fine Value = 491
N2.C1.D0.R1: Write Training Coarse, upper nibbles
N4.C0.D1.R0.S06: Total Delay in PI ticks: TxDQS = 963, TxDQ = 924
N6.C2.D0.R0.S06: Write Level Fine Value = 445
N0.C1.D1.R1.S11: Write Level Fine Value = 483
N2.C1.D0.R1.S09: Dq Delay estimate: 459
N4.C0.D1.R0.S07: Total Delay in PI ticks: TxDQS = 977, TxDQ = 937
N6.C2.D0.R0.S07: Write Level Fine Value = 463
N0.C1.D1.R1.S12: Write Level Fine Value = 468
N2.C1.D0.R1.S10: Dq Delay estimate: 445
N4.C0.D1.R0.S08: Total Delay in PI ticks: TxDQS = 951, TxDQ = 911
N6.C2.D0.R0.S08: Write Level Fine Value = 433
N0.C1.D1.R1.S13: Write Level Fine Value = 433
N2.C1.D0.R1.S11: Dq Delay estimate: 435
N4.C0.D1.R0.S09: Total Delay in PI ticks: TxDQS = 1018, TxDQ = 978
N6.C2.D0.R0.S09: Write Level Fine Value = 497
N0.C1.D1.R1.S14: Write Level Fine Value = 449
N2.C1.D0.R1.S12: Dq Delay estimate: 420
N4.C0.D1.R0.S10: Total Delay in PI ticks: TxDQS = 1006, TxDQ = 968
N6.C2.D0.R0.S10: Write Level Fine Value = 484
N0.C1.D1.R1.S15: Write Level Fine Value = 460
N2.C1.D0.R1.S13: Dq Delay estimate: 386
N4.C0.D1.R0.S11: Total Delay in PI ticks: TxDQS = 992, TxDQ = 954
N6.C2.D0.R0.S11: Write Level Fine Value = 473
N0.C1.D1.R1.S16: Write Level Fine Value = 478
N2.C1.D0.R1.S14: Dq Delay estimate: 400
N4.C0.D1.R0.S12: Total Delay in PI ticks: TxDQS = 976, TxDQ = 937
N6.C2.D0.R0.S12: Write Level Fine Value = 453
N0.C1.D1.R1.S17: Write Level Fine Value = 445
N2.C1.D0.R1.S15: Dq Delay estimate: 413
N4.C0.D1.R0.S13: Total Delay in PI ticks: TxDQS = 942, TxDQ = 904
N6.C2.D0.R0.S13: Write Level Fine Value = 414
N0.C2.D0.R0: ODT Override: 0x5
N2.C1.D0.R1.S16: Dq Delay estimate: 430
N4.C0.D1.R0.S14: Total Delay in PI ticks: TxDQS = 959, TxDQ = 921
N6.C2.D0.R0.S14: Write Level Fine Value = 441
N0.C2.D0.R0.S00: Write Level Fine Value = 503
N2.C1.D0.R1.S17: Dq Delay estimate: 406
N4.C0.D1.R0.S15: Total Delay in PI ticks: TxDQS = 962, TxDQ = 925
N6.C2.D0.R0.S15: Write Level Fine Value = 443
N0.C2.D0.R0.S01: Write Level Fine Value = 487
ACCM: F0 F0F0F0F0 F0F0F0F0
N4.C0.D1.R0.S16: Total Delay in PI ticks: TxDQS = 977, TxDQ = 938
N6.C2.D0.R0.S16: Write Level Fine Value = 463
N0.C2.D0.R0.S02: Write Level Fine Value = 477
ACCM: F0 F0F0F0F0 F0F0F0F0
N4.C0.D1.R0.S17: Total Delay in PI ticks: TxDQS = 951, TxDQ = 912
N6.C2.D0.R0.S17: Write Level Fine Value = 433
N0.C2.D0.R0.S03: Write Level Fine Value = 458
ACCM: F0 F0F0F0F0 F0F0F0F0
N4.C0.D1.R1.S00: Total Delay in PI ticks: TxDQS = 1016, TxDQ = 979
N6.C2.D0.R1: ODT Override: 0x6
N0.C2.D0.R0.S04: Write Level Fine Value = 421
ACCM: F0 F0F0F0F0 F0F0F0F0
N4.C0.D1.R1.S01: Total Delay in PI ticks: TxDQS = 1001, TxDQ = 963
N6.C2.D0.R1.S00: Write Level Fine Value = 490
N0.C2.D0.R0.S05: Write Level Fine Value = 447
N2.C1.D0.R1: CheckMCTest: result = 0x3FE00
N4.C0.D1.R1.S02: Total Delay in PI ticks: TxDQS = 990, TxDQ = 951
N6.C2.D0.R1.S01: Write Level Fine Value = 475
N0.C2.D0.R0.S06: Write Level Fine Value = 447
ACCM: F0 F0F0F0F0 F0F0F0F0
N4.C0.D1.R1.S03: Total Delay in PI ticks: TxDQS = 973, TxDQ = 936
N6.C2.D0.R1.S02: Write Level Fine Value = 464
N0.C2.D0.R0.S07: Write Level Fine Value = 466
ACCM: F0 F0F0F0F0 F0F0F0F0
N4.C0.D1.R1.S04: Total Delay in PI ticks: TxDQS = 936, TxDQ = 898
N6.C2.D0.R1.S03: Write Level Fine Value = 447
N0.C2.D0.R0.S08: Write Level Fine Value = 441
ACCM: F0 F0F0F0F0 F0F0F0F0
N4.C0.D1.R1.S05: Total Delay in PI ticks: TxDQS = 958, TxDQ = 920
N6.C2.D0.R1.S04: Write Level Fine Value = 407
N0.C2.D0.R0.S09: Write Level Fine Value = 504
ACCM: F0 F0F0F0F0 F0F0F0F0
N4.C0.D1.R1.S06: Total Delay in PI ticks: TxDQS = 959, TxDQ = 919
N6.C2.D0.R1.S05: Write Level Fine Value = 437
N0.C2.D0.R0.S10: Write Level Fine Value = 490
N2.C1.D0.R1: CheckMCTest: result = 0x3FE00
N4.C0.D1.R1.S07: Total Delay in PI ticks: TxDQS = 976, TxDQ = 936
N6.C2.D0.R1.S06: Write Level Fine Value = 435
N0.C2.D0.R0.S11: Write Level Fine Value = 478
ACCM: F0 F0F0F0F0 F0F0F0F0
N4.C0.D1.R1.S08: Total Delay in PI ticks: TxDQS = 945, TxDQ = 905
N6.C2.D0.R1.S07: Write Level Fine Value = 457
N0.C2.D0.R0.S12: Write Level Fine Value = 457
ACCM: F0 F0F0F0F0 F0F0F0F0
N4.C0.D1.R1.S09: Total Delay in PI ticks: TxDQS = 1017, TxDQ = 977
N6.C2.D0.R1.S08: Write Level Fine Value = 425
N0.C2.D0.R0.S13: Write Level Fine Value = 418
ACCM: 00 000000B0 B0000000
N4.C0.D1.R1.S10: Total Delay in PI ticks: TxDQS = 1003, TxDQ = 966
N6.C2.D0.R1.S09: Write Level Fine Value = 487
N0.C2.D0.R0.S14: Write Level Fine Value = 446
ACCM: 00 000000B0 B0000000
N4.C0.D1.R1.S11: Total Delay in PI ticks: TxDQS = 991, TxDQ = 953
N6.C2.D0.R1.S10: Write Level Fine Value = 475
N0.C2.D0.R0.S15: Write Level Fine Value = 448
N2.C1.D0.R1: CheckMCTest: result = 0x3FE00
N4.C0.D1.R1.S12: Total Delay in PI ticks: TxDQS = 976, TxDQ = 937
N6.C2.D0.R1.S11: Write Level Fine Value = 465
N0.C2.D0.R0.S16: Write Level Fine Value = 466
ACCM: F0 F0F0F0F0 F0F0F0F0
N4.C0.D1.R1.S13: Total Delay in PI ticks: TxDQS = 940, TxDQ = 903
N6.C2.D0.R1.S12: Write Level Fine Value = 450
N0.C2.D0.R0.S17: Write Level Fine Value = 440
ACCM: F0 F0F0F0F0 F0F0F0F0
N4.C0.D1.R1.S14: Total Delay in PI ticks: TxDQS = 955, TxDQ = 916
N6.C2.D0.R1.S13: Write Level Fine Value = 407
N0.C2.D0.R1: ODT Override: 0x6
ACCM: 00 000000F0 B0000000
N4.C0.D1.R1.S15: Total Delay in PI ticks: TxDQS = 959, TxDQ = 922
N6.C2.D0.R1.S14: Write Level Fine Value = 437
N0.C2.D0.R1.S00: Write Level Fine Value = 495
ACCM: 00 000000F0 B0000000
N4.C0.D1.R1.S16: Total Delay in PI ticks: TxDQS = 975, TxDQ = 936
N6.C2.D0.R1.S15: Write Level Fine Value = 437
N0.C2.D0.R1.S01: Write Level Fine Value = 482
N2.C1.D0.R1: CheckMCTest: result = 0x3FE00
N4.C0.D1.R1.S17: Total Delay in PI ticks: TxDQS = 945, TxDQ = 907
N6.C2.D0.R1.S16: Write Level Fine Value = 457
N0.C2.D0.R1.S02: Write Level Fine Value = 472
N2.C1.D0.R1: CheckMCTest: passed
N4.C1.D0.R0: Write Training Coarse, lower nibbles / bytes
N6.C2.D0.R1.S17: Write Level Fine Value = 425
N0.C2.D0.R1.S03: Write Level Fine Value = 454
N2.C1.D0.R1: CheckMCTest: passed
N4.C1.D0.R0.S00: Dq Delay estimate: 469
N6.C2.D1.R0: ODT Override: 0x5
N0.C2.D0.R1.S04: Write Level Fine Value = 415
N2.C1.D0.R1.S09: Offset Found: RdPtrOffsetDqs = 007
N4.C1.D0.R0.S01: Dq Delay estimate: 452
N6.C2.D1.R0.S00: Write Level Fine Value = 503
N0.C2.D0.R1.S05: Write Level Fine Value = 444
N2.C1.D0.R1.S10: Offset Found: RdPtrOffsetDqs = 007
N4.C1.D0.R0.S02: Dq Delay estimate: 445
N6.C2.D1.R0.S01: Write Level Fine Value = 489
N0.C2.D0.R1.S06: Write Level Fine Value = 439
N2.C1.D0.R1.S11: Offset Found: RdPtrOffsetDqs = 007
N4.C1.D0.R0.S03: Dq Delay estimate: 432
N6.C2.D1.R0.S02: Write Level Fine Value = 480
N0.C2.D0.R1.S07: Write Level Fine Value = 462
N2.C1.D0.R1.S12: Offset Found: RdPtrOffsetDqs = 007
N4.C1.D0.R0.S04: Dq Delay estimate: 396
N6.C2.D1.R0.S03: Write Level Fine Value = 464
N0.C2.D0.R1.S08: Write Level Fine Value = 432
N2.C1.D0.R1.S13: Offset Found: RdPtrOffsetDqs = 006
N4.C1.D0.R0.S05: Dq Delay estimate: 407
N6.C2.D1.R0.S04: Write Level Fine Value = 422
N0.C2.D0.R1.S09: Write Level Fine Value = 497
N2.C1.D0.R1.S14: Offset Found: RdPtrOffsetDqs = 006
N4.C1.D0.R0.S06: Dq Delay estimate: 423
N6.C2.D1.R0.S05: Write Level Fine Value = 452
N0.C2.D0.R1.S10: Write Level Fine Value = 483
N2.C1.D0.R1.S15: Offset Found: RdPtrOffsetDqs = 006
N4.C1.D0.R0.S07: Dq Delay estimate: 434
N6.C2.D1.R0.S06: Write Level Fine Value = 449
N0.C2.D0.R1.S11: Write Level Fine Value = 471
N2.C1.D0.R1.S16: Offset Found: RdPtrOffsetDqs = 007
N4.C1.D0.R0.S08: Dq Delay estimate: 409
N6.C2.D1.R0.S07: Write Level Fine Value = 473
N0.C2.D0.R1.S12: Write Level Fine Value = 454
N2.C1.D0.R1.S17: Offset Found: RdPtrOffsetDqs = 006
ACCM: FF 0F0F0F9F 0F0F0F0F
N6.C2.D1.R0.S08: Write Level Fine Value = 437
N0.C2.D0.R1.S13: Write Level Fine Value = 414
N2.C1.D1.R0: Write Training Coarse, lower nibbles / bytes
ACCM: FF 0F0F0F9F 0F0F0F0F
N6.C2.D1.R0.S09: Write Level Fine Value = 504
N0.C2.D0.R1.S14: Write Level Fine Value = 440
N2.C1.D1.R0.S00: Dq Delay estimate: 469
ACCM: FF FFFFFF9F FFFFFFFF
N6.C2.D1.R0.S10: Write Level Fine Value = 489
N0.C2.D0.R1.S15: Write Level Fine Value = 440
N2.C1.D1.R0.S01: Dq Delay estimate: 453
ACCM: FF FFFFFF9F FFFFFFFF
N6.C2.D1.R0.S11: Write Level Fine Value = 480
N0.C2.D0.R1.S16: Write Level Fine Value = 464
N2.C1.D1.R0.S02: Dq Delay estimate: 446
N4.C1.D0.R0: CheckMCTest: result = 0x3FFFF
N6.C2.D1.R0.S12: Write Level Fine Value = 464
N0.C2.D0.R1.S17: Write Level Fine Value = 430
N2.C1.D1.R0.S03: Dq Delay estimate: 428
ACCM: FF 0F0F0FDF 0F0F0F0F
N6.C2.D1.R0.S13: Write Level Fine Value = 422
N0.C2.D1.R0: ODT Override: 0x5
N2.C1.D1.R0.S04: Dq Delay estimate: 396
ACCM: FF 0F0F0FDF 0F0F0F0F
N6.C2.D1.R0.S14: Write Level Fine Value = 452
N0.C2.D1.R0.S00: Write Level Fine Value = 505
N2.C1.D1.R0.S05: Dq Delay estimate: 412
ACCM: FF FFFFFFDF FFFFFFFF
N6.C2.D1.R0.S15: Write Level Fine Value = 448
N0.C2.D1.R0.S01: Write Level Fine Value = 490
N2.C1.D1.R0.S06: Dq Delay estimate: 424
ACCM: FF FFFFFFDF FFFFFFFF
N6.C2.D1.R0.S16: Write Level Fine Value = 471
N0.C2.D1.R0.S02: Write Level Fine Value = 482
N2.C1.D1.R0.S07: Dq Delay estimate: 441
N4.C1.D0.R0: CheckMCTest: result = 0x3FFFF
N6.C2.D1.R0.S17: Write Level Fine Value = 439
N0.C2.D1.R0.S03: Write Level Fine Value = 464
N2.C1.D1.R0.S08: Dq Delay estimate: 408
ACCM: FF 0F0F0FDF 0F0F0F0F
N6.C2.D1.R1: ODT Override: 0x9
N0.C2.D1.R0.S04: Write Level Fine Value = 422
ACCM: 0F 0F0F0F0F 0F0F0F0F
ACCM: FF 0F0F0FDF 0F0F0F0F
N6.C2.D1.R1.S00: Write Level Fine Value = 498
N0.C2.D1.R0.S05: Write Level Fine Value = 452
ACCM: 0F 0F0F0F0F 0F0F0F0F
ACCM: F0 FBF0F0DB FBF0F0F0
N6.C2.D1.R1.S01: Write Level Fine Value = 484
N0.C2.D1.R0.S06: Write Level Fine Value = 449
ACCM: 0F 0F0F0F0F 0F0F0F0F
ACCM: F0 FBF0F0DB FBF0F0F0
N6.C2.D1.R1.S02: Write Level Fine Value = 474
N0.C2.D1.R0.S07: Write Level Fine Value = 470
ACCM: 0F FF0F0F0F FFFFFF0F
N4.C1.D0.R0: CheckMCTest: result = 0x3FFFF
N6.C2.D1.R1.S03: Write Level Fine Value = 459
N0.C2.D1.R0.S08: Write Level Fine Value = 440
N2.C1.D1.R0: CheckMCTest: result = 0x11DFF
ACCM: FF 0F0F0FDF 0F0F0F0F
N6.C2.D1.R1.S04: Write Level Fine Value = 417
N0.C2.D1.R0.S09: Write Level Fine Value = 503
ACCM: 0F 0F0F0F0F 0F0F0F0F
ACCM: FF 0F0F0FDF 0F0F0F0F
N6.C2.D1.R1.S05: Write Level Fine Value = 448
N0.C2.D1.R0.S10: Write Level Fine Value = 492
ACCM: 0F 0F0F0F0F 0F0F0F0F
ACCM: F0 FFFDF0DF FFF0F0F0
N6.C2.D1.R1.S06: Write Level Fine Value = 444
N0.C2.D1.R0.S11: Write Level Fine Value = 480
ACCM: 0F 0F0F0F0F 0F0F0F0F
ACCM: F0 FFFDF0DF FFF0F0F0
N6.C2.D1.R1.S07: Write Level Fine Value = 468
N0.C2.D1.R0.S12: Write Level Fine Value = 462
ACCM: 0F FF0F0F0F FFFFFF0F
N4.C1.D0.R0: CheckMCTest: result = 0x3FFFF
N6.C2.D1.R1.S08: Write Level Fine Value = 431
N0.C2.D1.R0.S13: Write Level Fine Value = 423
N2.C1.D1.R0: CheckMCTest: result = 0x11DFF
ACCM: D0 000000D0 00000000
N6.C2.D1.R1.S09: Write Level Fine Value = 496
N0.C2.D1.R0.S14: Write Level Fine Value = 448
ACCM: 0F 0F0F0F0F 0F0F0F0F
ACCM: D0 000000D0 00000000
N6.C2.D1.R1.S10: Write Level Fine Value = 484
N0.C2.D1.R0.S15: Write Level Fine Value = 452
ACCM: 0F 0F0F0F0F 0F0F0F0F
ACCM: F0 F0F0F0D0 F0F0F0F0
N6.C2.D1.R1.S11: Write Level Fine Value = 476
N0.C2.D1.R0.S16: Write Level Fine Value = 470
ACCM: 00 0B0B0B0B 00000B0B
ACCM: F0 F0F0F0D0 F0F0F0F0
N6.C2.D1.R1.S12: Write Level Fine Value = 463
N0.C2.D1.R0.S17: Write Level Fine Value = 440
ACCM: 00 FB0B0B0B F0F0FB0B
N4.C1.D0.R0: CheckMCTest: result = 0x3FE00
N6.C2.D1.R1.S13: Write Level Fine Value = 418
N0.C2.D1.R1: ODT Override: 0x9
N2.C1.D1.R0: CheckMCTest: result = 0x11DFF
ACCM: F0 000000D0 00000000
N6.C2.D1.R1.S14: Write Level Fine Value = 446
N0.C2.D1.R1.S00: Write Level Fine Value = 500
ACCM: 0F 0F0F0F0F 0F0F0F0F
ACCM: F0 000000D0 00000000
N6.C2.D1.R1.S15: Write Level Fine Value = 446
N0.C2.D1.R1.S01: Write Level Fine Value = 488
ACCM: 0F 0F0F0F0F 0F0F0F0F
ACCM: F0 F0F0F0D0 F0F0F0F0
N6.C2.D1.R1.S16: Write Level Fine Value = 468
N0.C2.D1.R1.S02: Write Level Fine Value = 477
ACCM: 00 0F0F0F0F 000D0F0F
ACCM: F0 F0F0F0D0 F0F0F0F0
N6.C2.D1.R1.S17: Write Level Fine Value = 432
N0.C2.D1.R1.S03: Write Level Fine Value = 460
ACCM: 00 FF0F0F0F F0FDFF0F
N4.C1.D0.R0: CheckMCTest: result = 0x3FE00
N6.C3.D0.R0: ODT Override: 0x5
N0.C2.D1.R1.S04: Write Level Fine Value = 421
N2.C1.D1.R0: CheckMCTest: result = 0x11DFF
N4.C1.D0.R0.S00: Offset Found: RdPtrOffsetDqs = 007
N6.C3.D0.R0.S00: Write Level Fine Value = 506
N0.C2.D1.R1.S05: Write Level Fine Value = 449
ACCM: 00 00000000 00000000
N4.C1.D0.R0.S01: Offset Found: RdPtrOffsetDqs = 007
N6.C3.D0.R0.S01: Write Level Fine Value = 491
N0.C2.D1.R1.S06: Write Level Fine Value = 444
ACCM: 00 00000000 00000000
N4.C1.D0.R0.S02: Offset Found: RdPtrOffsetDqs = 007
N6.C3.D0.R0.S02: Write Level Fine Value = 484
N0.C2.D1.R1.S07: Write Level Fine Value = 466
ACCM: 00 00000000 00000000
N4.C1.D0.R0.S03: Offset Found: RdPtrOffsetDqs = 007
N6.C3.D0.R0.S03: Write Level Fine Value = 467
N0.C2.D1.R1.S08: Write Level Fine Value = 433
ACCM: 00 F0000000 F0F0F000
N4.C1.D0.R0.S04: Offset Found: RdPtrOffsetDqs = 006
N6.C3.D0.R0.S04: Write Level Fine Value = 430
N0.C2.D1.R1.S09: Write Level Fine Value = 502
N2.C1.D1.R0: CheckMCTest: result = 0x11C00
N4.C1.D0.R0.S05: Offset Found: RdPtrOffsetDqs = 006
N6.C3.D0.R0.S05: Write Level Fine Value = 443
N0.C2.D1.R1.S10: Write Level Fine Value = 489
ACCM: 00 00000000 00000000
N4.C1.D0.R0.S06: Offset Found: RdPtrOffsetDqs = 007
N6.C3.D0.R0.S06: Write Level Fine Value = 460
N0.C2.D1.R1.S11: Write Level Fine Value = 479
ACCM: 00 00000000 00000000
N4.C1.D0.R0.S07: Offset Found: RdPtrOffsetDqs = 007
N6.C3.D0.R0.S07: Write Level Fine Value = 475
N0.C2.D1.R1.S12: Write Level Fine Value = 461
ACCM: 00 00000000 00000000
N4.C1.D0.R0.S08: Offset Found: RdPtrOffsetDqs = 006
N6.C3.D0.R0.S08: Write Level Fine Value = 449
N0.C2.D1.R1.S13: Write Level Fine Value = 423
ACCM: 00 F0000000 F0F0F000
N4.C1.D0.R0: Write Training Coarse, upper nibbles
N6.C3.D0.R0.S09: Write Level Fine Value = 507
N0.C2.D1.R1.S14: Write Level Fine Value = 448
N2.C1.D1.R0: CheckMCTest: result = 0x11C00
N4.C1.D0.R0.S09: Dq Delay estimate: 472
N6.C3.D0.R0.S10: Write Level Fine Value = 491
N0.C2.D1.R1.S15: Write Level Fine Value = 446
N2.C1.D1.R0.S00: Offset Found: RdPtrOffsetDqs = 007
N4.C1.D0.R0.S10: Dq Delay estimate: 455
N6.C3.D0.R0.S11: Write Level Fine Value = 482
N0.C2.D1.R1.S16: Write Level Fine Value = 471
N2.C1.D1.R0.S01: Offset Found: RdPtrOffsetDqs = 007
N4.C1.D0.R0.S11: Dq Delay estimate: 450
N6.C3.D0.R0.S12: Write Level Fine Value = 465
N0.C2.D1.R1.S17: Write Level Fine Value = 434
N2.C1.D1.R0.S02: Offset Found: RdPtrOffsetDqs = 007
N4.C1.D0.R0.S12: Dq Delay estimate: 430
N6.C3.D0.R0.S13: Write Level Fine Value = 430
N0.C3.D0.R0: ODT Override: 0x5
N2.C1.D1.R0.S03: Offset Found: RdPtrOffsetDqs = 007
N4.C1.D0.R0.S13: Dq Delay estimate: 397
N6.C3.D0.R0.S14: Write Level Fine Value = 444
N0.C3.D0.R0.S00: Write Level Fine Value = 388
N2.C1.D1.R0.S04: Offset Found: RdPtrOffsetDqs = 006
N4.C1.D0.R0.S14: Dq Delay estimate: 410
N6.C3.D0.R0.S15: Write Level Fine Value = 458
N0.C3.D0.R0.S01: Write Level Fine Value = 498
N2.C1.D1.R0.S05: Offset Found: RdPtrOffsetDqs = 006
N4.C1.D0.R0.S15: Dq Delay estimate: 420
N6.C3.D0.R0.S16: Write Level Fine Value = 476
N0.C3.D0.R0.S02: Write Level Fine Value = 487
N2.C1.D1.R0.S06: Offset Found: RdPtrOffsetDqs = 007
N4.C1.D0.R0.S16: Dq Delay estimate: 437
N6.C3.D0.R0.S17: Write Level Fine Value = 447
N0.C3.D0.R0.S03: Write Level Fine Value = 468
N2.C1.D1.R0.S07: Offset Found: RdPtrOffsetDqs = 007
N4.C1.D0.R0.S17: Dq Delay estimate: 411
N6.C3.D0.R1: ODT Override: 0x6
N0.C3.D0.R0.S04: Write Level Fine Value = 436
N2.C1.D1.R0.S08: Offset Found: RdPtrOffsetDqs = 006
ACCM: F0 F0F0F0F0 F0F0F0F0
N6.C3.D0.R1.S00: Write Level Fine Value = 499
N0.C3.D0.R0.S05: Write Level Fine Value = 450
N2.C1.D1.R0: Write Training Coarse, upper nibbles
ACCM: F0 F0F0F0F0 F0F0F0F0
N6.C3.D0.R1.S01: Write Level Fine Value = 485
N0.C3.D0.R0.S06: Write Level Fine Value = 465
N2.C1.D1.R0.S09: Dq Delay estimate: 471
ACCM: F0 F0F0F0F0 F0F0F0F0
N6.C3.D0.R1.S02: Write Level Fine Value = 475
N0.C3.D0.R0.S07: Write Level Fine Value = 481
N2.C1.D1.R0.S10: Dq Delay estimate: 453
ACCM: F0 F0F0F0F0 F0F0F0F0
N6.C3.D0.R1.S03: Write Level Fine Value = 459
N0.C3.D0.R0.S08: Write Level Fine Value = 453
N2.C1.D1.R0.S11: Dq Delay estimate: 448
N4.C1.D0.R0: CheckMCTest: result = 0x3FE00
N6.C3.D0.R1.S04: Write Level Fine Value = 423
N0.C3.D0.R0.S09: Write Level Fine Value = 388
N2.C1.D1.R0.S12: Dq Delay estimate: 430
ACCM: F0 F0F0F0F0 F0F0F0F0
N6.C3.D0.R1.S05: Write Level Fine Value = 438
N0.C3.D0.R0.S10: Write Level Fine Value = 498
N2.C1.D1.R0.S13: Dq Delay estimate: 397
ACCM: F0 F0F0F0F0 F0F0F0F0
N6.C3.D0.R1.S06: Write Level Fine Value = 450
N0.C3.D0.R0.S11: Write Level Fine Value = 488
N2.C1.D1.R0.S14: Dq Delay estimate: 411
ACCM: F0 F0F0F0F0 F0F0F0F0
N6.C3.D0.R1.S07: Write Level Fine Value = 469
N0.C3.D0.R0.S12: Write Level Fine Value = 472
N2.C1.D1.R0.S15: Dq Delay estimate: 421
ACCM: F0 F0F0F0F0 F0F0F0F0
N6.C3.D0.R1.S08: Write Level Fine Value = 440
N0.C3.D0.R0.S13: Write Level Fine Value = 434
N2.C1.D1.R0.S16: Dq Delay estimate: 441
N4.C1.D0.R0: CheckMCTest: result = 0x3FE00
N6.C3.D0.R1.S09: Write Level Fine Value = 499
N0.C3.D0.R0.S14: Write Level Fine Value = 449
N2.C1.D1.R0.S17: Dq Delay estimate: 412
ACCM: F0 F0F0F0F0 F0F0F0F0
N6.C3.D0.R1.S10: Write Level Fine Value = 484
N0.C3.D0.R0.S15: Write Level Fine Value = 468
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: F0 F0F0F0F0 F0F0F0F0
N6.C3.D0.R1.S11: Write Level Fine Value = 473
N0.C3.D0.R0.S16: Write Level Fine Value = 477
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: 00 0000B0B0 00000000
N6.C3.D0.R1.S12: Write Level Fine Value = 460
N0.C3.D0.R0.S17: Write Level Fine Value = 454
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: 00 0000B0B0 00000000
N6.C3.D0.R1.S13: Write Level Fine Value = 423
N0.C3.D0.R1: ODT Override: 0x6
ACCM: F0 F0F0F0F0 F0F0F0F0
N4.C1.D0.R0: CheckMCTest: result = 0x3FE00
N6.C3.D0.R1.S14: Write Level Fine Value = 436
N0.C3.D0.R1.S00: Write Level Fine Value = 509
N2.C1.D1.R0: CheckMCTest: result = 0x3FE00
ACCM: F0 F0F0F0F0 F0F0F0F0
N6.C3.D0.R1.S15: Write Level Fine Value = 450
N0.C3.D0.R1.S01: Write Level Fine Value = 490
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: F0 F0F0F0F0 F0F0F0F0
N6.C3.D0.R1.S16: Write Level Fine Value = 470
N0.C3.D0.R1.S02: Write Level Fine Value = 480
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: 00 0000F0F0 00000000
N6.C3.D0.R1.S17: Write Level Fine Value = 439
N0.C3.D0.R1.S03: Write Level Fine Value = 465
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: 00 0000F0F0 00000000
N6.C3.D1.R0: ODT Override: 0x5
N0.C3.D0.R1.S04: Write Level Fine Value = 431
ACCM: F0 F0F0F0F0 F0F0F0F0
N4.C1.D0.R0: CheckMCTest: result = 0x3FE00
N6.C3.D1.R0.S00: Write Level Fine Value = 385
N0.C3.D0.R1.S05: Write Level Fine Value = 443
N2.C1.D1.R0: CheckMCTest: result = 0x3FE00
N4.C1.D0.R0: CheckMCTest: passed
N6.C3.D1.R0.S01: Write Level Fine Value = 496
N0.C3.D0.R1.S06: Write Level Fine Value = 458
ACCM: F0 F0F0F0F0 F0F0F0F0
N4.C1.D0.R0: CheckMCTest: passed
N6.C3.D1.R0.S02: Write Level Fine Value = 485
N0.C3.D0.R1.S07: Write Level Fine Value = 475
ACCM: F0 F0F0F0F0 F0F0F0F0
N4.C1.D0.R0.S09: Offset Found: RdPtrOffsetDqs = 007
N6.C3.D1.R0.S03: Write Level Fine Value = 472
N0.C3.D0.R1.S08: Write Level Fine Value = 446
ACCM: 00 B0B0B0B0 000000B0
N4.C1.D0.R0.S10: Offset Found: RdPtrOffsetDqs = 007
N6.C3.D1.R0.S04: Write Level Fine Value = 436
N0.C3.D0.R1.S09: Write Level Fine Value = 509
ACCM: 00 B0B0B0B0 000000B0
N4.C1.D0.R0.S11: Offset Found: RdPtrOffsetDqs = 007
N6.C3.D1.R0.S05: Write Level Fine Value = 448
N0.C3.D0.R1.S10: Write Level Fine Value = 490
N2.C1.D1.R0: CheckMCTest: result = 0x3FE00
N4.C1.D0.R0.S12: Offset Found: RdPtrOffsetDqs = 007
N6.C3.D1.R0.S06: Write Level Fine Value = 464
N0.C3.D0.R1.S11: Write Level Fine Value = 481
ACCM: F0 F0F0F0F0 F0F0F0F0
N4.C1.D0.R0.S13: Offset Found: RdPtrOffsetDqs = 006
N6.C3.D1.R0.S07: Write Level Fine Value = 482
N0.C3.D0.R1.S12: Write Level Fine Value = 469
ACCM: F0 F0F0F0F0 F0F0F0F0
N4.C1.D0.R0.S14: Offset Found: RdPtrOffsetDqs = 006
N6.C3.D1.R0.S08: Write Level Fine Value = 451
N0.C3.D0.R1.S13: Write Level Fine Value = 432
ACCM: 00 F0F0F0F0 000000F0
N4.C1.D0.R0.S15: Offset Found: RdPtrOffsetDqs = 007
N6.C3.D1.R0.S09: Write Level Fine Value = 384
N0.C3.D0.R1.S14: Write Level Fine Value = 445
ACCM: 00 F0F0F0F0 000000F0
N4.C1.D0.R0.S16: Offset Found: RdPtrOffsetDqs = 007
N6.C3.D1.R0.S10: Write Level Fine Value = 496
N0.C3.D0.R1.S15: Write Level Fine Value = 457
N2.C1.D1.R0: CheckMCTest: result = 0x3FE00
N4.C1.D0.R0.S17: Offset Found: RdPtrOffsetDqs = 007
N6.C3.D1.R0.S11: Write Level Fine Value = 485
N0.C3.D0.R1.S16: Write Level Fine Value = 475
N2.C1.D1.R0: CheckMCTest: passed
N4.C1.D0.R1: Write Training Coarse, lower nibbles / bytes
N6.C3.D1.R0.S12: Write Level Fine Value = 472
N0.C3.D0.R1.S17: Write Level Fine Value = 446
N2.C1.D1.R0: CheckMCTest: passed
N4.C1.D0.R1.S00: Dq Delay estimate: 461
N6.C3.D1.R0.S13: Write Level Fine Value = 435
N0.C3.D1.R0: ODT Override: 0x5
N2.C1.D1.R0.S09: Offset Found: RdPtrOffsetDqs = 007
N4.C1.D0.R1.S01: Dq Delay estimate: 447
N6.C3.D1.R0.S14: Write Level Fine Value = 449
N0.C3.D1.R0.S00: Write Level Fine Value = 390
N2.C1.D1.R0.S10: Offset Found: RdPtrOffsetDqs = 007
N4.C1.D0.R1.S02: Dq Delay estimate: 437
N6.C3.D1.R0.S15: Write Level Fine Value = 463
N0.C3.D1.R0.S01: Write Level Fine Value = 499
N2.C1.D1.R0.S11: Offset Found: RdPtrOffsetDqs = 007
N4.C1.D0.R1.S03: Dq Delay estimate: 423
N6.C3.D1.R0.S16: Write Level Fine Value = 482
N0.C3.D1.R0.S02: Write Level Fine Value = 491
N2.C1.D1.R0.S12: Offset Found: RdPtrOffsetDqs = 007
N4.C1.D0.R1.S04: Dq Delay estimate: 389
N6.C3.D1.R0.S17: Write Level Fine Value = 451
N0.C3.D1.R0.S03: Write Level Fine Value = 472
N2.C1.D1.R0.S13: Offset Found: RdPtrOffsetDqs = 006
N4.C1.D0.R1.S05: Dq Delay estimate: 402
N6.C3.D1.R1: ODT Override: 0x9
N0.C3.D1.R0.S04: Write Level Fine Value = 438
N2.C1.D1.R0.S14: Offset Found: RdPtrOffsetDqs = 006
N4.C1.D0.R1.S06: Dq Delay estimate: 411
N6.C3.D1.R1.S00: Write Level Fine Value = 508
N0.C3.D1.R0.S05: Write Level Fine Value = 452
N2.C1.D1.R0.S15: Offset Found: RdPtrOffsetDqs = 007
N4.C1.D0.R1.S07: Dq Delay estimate: 432
N6.C3.D1.R1.S01: Write Level Fine Value = 491
N0.C3.D1.R0.S06: Write Level Fine Value = 466
N2.C1.D1.R0.S16: Offset Found: RdPtrOffsetDqs = 007
N4.C1.D0.R1.S08: Dq Delay estimate: 403
N6.C3.D1.R1.S02: Write Level Fine Value = 480
N0.C3.D1.R0.S07: Write Level Fine Value = 483
N2.C1.D1.R0.S17: Offset Found: RdPtrOffsetDqs = 006
ACCM: 0F 0F0F0F0F 0F0F0F0F
N6.C3.D1.R1.S03: Write Level Fine Value = 468
N0.C3.D1.R0.S08: Write Level Fine Value = 452
N2.C1.D1.R1: Write Training Coarse, lower nibbles / bytes
ACCM: 0F 0F0F0F0F 0F0F0F0F
N6.C3.D1.R1.S04: Write Level Fine Value = 432
N0.C3.D1.R0.S09: Write Level Fine Value = 390
N2.C1.D1.R1.S00: Dq Delay estimate: 465
ACCM: 0F 0F0F0F0F 0F0F0F0F
N6.C3.D1.R1.S05: Write Level Fine Value = 444
N0.C3.D1.R0.S10: Write Level Fine Value = 501
N2.C1.D1.R1.S01: Dq Delay estimate: 448
ACCM: 0F 0F0F0F0F 0F0F0F0F
N6.C3.D1.R1.S06: Write Level Fine Value = 458
N0.C3.D1.R0.S11: Write Level Fine Value = 491
N2.C1.D1.R1.S02: Dq Delay estimate: 441
N4.C1.D0.R1: CheckMCTest: result = 0x1FF
N6.C3.D1.R1.S07: Write Level Fine Value = 477
N0.C3.D1.R0.S12: Write Level Fine Value = 473
N2.C1.D1.R1.S03: Dq Delay estimate: 424
ACCM: 0F 0F0F0F0F 0F0F0F0F
N6.C3.D1.R1.S08: Write Level Fine Value = 444
N0.C3.D1.R0.S13: Write Level Fine Value = 440
N2.C1.D1.R1.S04: Dq Delay estimate: 391
ACCM: 0F 0F0F0F0F 0F0F0F0F
N6.C3.D1.R1.S09: Write Level Fine Value = 507
N0.C3.D1.R0.S14: Write Level Fine Value = 453
N2.C1.D1.R1.S05: Dq Delay estimate: 407
ACCM: 0F 0F0F0F0F 0F0F0F0F
N6.C3.D1.R1.S10: Write Level Fine Value = 491
N0.C3.D1.R0.S15: Write Level Fine Value = 469
N2.C1.D1.R1.S06: Dq Delay estimate: 420
ACCM: 0F 0F0F0F0F 0F0F0F0F
N6.C3.D1.R1.S11: Write Level Fine Value = 483
N0.C3.D1.R0.S16: Write Level Fine Value = 481
N2.C1.D1.R1.S07: Dq Delay estimate: 437
N4.C1.D0.R1: CheckMCTest: result = 0x1FF
N6.C3.D1.R1.S12: Write Level Fine Value = 468
N0.C3.D1.R0.S17: Write Level Fine Value = 451
N2.C1.D1.R1.S08: Dq Delay estimate: 402
ACCM: 0F 0F0F0F0F 0F0F0F0F
N6.C3.D1.R1.S13: Write Level Fine Value = 431
N0.C3.D1.R1: ODT Override: 0x9
ACCM: 0F 0F0F0F0F 0F0F0F0F
ACCM: 0F 0F0F0F0F 0F0F0F0F
N6.C3.D1.R1.S14: Write Level Fine Value = 444
N0.C3.D1.R1.S00: Write Level Fine Value = 388
ACCM: 0F 0F0F0F0F 0F0F0F0F
ACCM: 0B 00000000 0B0B0B00
N6.C3.D1.R1.S15: Write Level Fine Value = 457
N0.C3.D1.R1.S01: Write Level Fine Value = 497
ACCM: 0F 0F0F0F0F 0F0F0F0F
ACCM: 0B 00000000 0B0B0B00
N6.C3.D1.R1.S16: Write Level Fine Value = 476
N0.C3.D1.R1.S02: Write Level Fine Value = 487
ACCM: 0F 0F0F0F0F 0F0F0F0F
N4.C1.D0.R1: CheckMCTest: result = 0x1FF
N6.C3.D1.R1.S17: Write Level Fine Value = 444
N0.C3.D1.R1.S03: Write Level Fine Value = 472
N2.C1.D1.R1: CheckMCTest: result = 0x1FF
ACCM: 0F 0F0F0F0F 0F0F0F0F
N6: END WRITE LEVEL:
N0.C3.D1.R1.S04: Write Level Fine Value = 436
ACCM: 0F 0F0F0F0F 0F0F0F0F
ACCM: 0F 0F0F0F0F 0F0F0F0F
N6: START WRITE LEVEL COARSE:
N0.C3.D1.R1.S05: Write Level Fine Value = 449
ACCM: 0F 0F0F0F0F 0F0F0F0F
ACCM: 0F 00000000 0F0F0F00
N0.C3.D1.R1.S06: Write Level Fine Value = 464
ACCM: 0F 0F0F0F0F 0F0F0F0F
ACCM: 0F 00000000 0F0F0F00
N0.C3.D1.R1.S07: Write Level Fine Value = 482
ACCM: 0F 0F0F0F0F 0F0F0F0F
N4.C1.D0.R1: CheckMCTest: result = 0x1FF
N0.C3.D1.R1.S08: Write Level Fine Value = 449
N2.C1.D1.R1: CheckMCTest: result = 0x1FF
N4.C1.D0.R1: CheckMCTest: passed
N0.C3.D1.R1.S09: Write Level Fine Value = 387
ACCM: 0F 0F0F0F0F 0F0F0F0F
N4.C1.D0.R1: CheckMCTest: passed
N0.C3.D1.R1.S10: Write Level Fine Value = 498
ACCM: 0F 0F0F0F0F 0F0F0F0F
N4.C1.D0.R1.S00: Offset Found: RdPtrOffsetDqs = 007
N0.C3.D1.R1.S11: Write Level Fine Value = 487
ACCM: 00 0000000B 0B000000
N4.C1.D0.R1.S01: Offset Found: RdPtrOffsetDqs = 007
N6.C0.D0.R0: Write Training Coarse, lower nibbles / bytes
N0.C3.D1.R1.S12: Write Level Fine Value = 474
ACCM: 00 0000000B 0B000000
N4.C1.D0.R1.S02: Offset Found: RdPtrOffsetDqs = 007
N6.C0.D0.R0.S00: Dq Delay estimate: 472
N0.C3.D1.R1.S13: Write Level Fine Value = 439
N2.C1.D1.R1: CheckMCTest: result = 0x1FF
N4.C1.D0.R1.S03: Offset Found: RdPtrOffsetDqs = 007
N6.C0.D0.R0.S01: Dq Delay estimate: 448
N0.C3.D1.R1.S14: Write Level Fine Value = 451
ACCM: 0F 0F0F0F0F 0F0F0F0F
N4.C1.D0.R1.S04: Offset Found: RdPtrOffsetDqs = 006
N6.C0.D0.R0.S02: Dq Delay estimate: 438
N0.C3.D1.R1.S15: Write Level Fine Value = 464
ACCM: 0F 0F0F0F0F 0F0F0F0F
N4.C1.D0.R1.S05: Offset Found: RdPtrOffsetDqs = 006
N6.C0.D0.R0.S03: Dq Delay estimate: 420
N0.C3.D1.R1.S16: Write Level Fine Value = 479
ACCM: 00 0000000F 0F00000D
N4.C1.D0.R1.S06: Offset Found: RdPtrOffsetDqs = 007
N6.C0.D0.R0.S04: Dq Delay estimate: 388
N0.C3.D1.R1.S17: Write Level Fine Value = 449
ACCM: 00 0000000F 0F00000D
N4.C1.D0.R1.S07: Offset Found: RdPtrOffsetDqs = 007
N6.C0.D0.R0.S05: Dq Delay estimate: 405
N0: END WRITE LEVEL:
N2.C1.D1.R1: CheckMCTest: result = 0x1FF
N4.C1.D0.R1.S08: Offset Found: RdPtrOffsetDqs = 006
N6.C0.D0.R0.S06: Dq Delay estimate: 410
Checkpoint Code: Socket 0, 0xB7, 0x04, 0x0000
N2.C1.D1.R1: CheckMCTest: passed
N4.C1.D0.R1: Write Training Coarse, upper nibbles
N6.C0.D0.R0.S07: Dq Delay estimate: 424
N0: START WRITE LEVEL COARSE:
N2.C1.D1.R1: CheckMCTest: passed
N4.C1.D0.R1.S09: Dq Delay estimate: 461
N6.C0.D0.R0.S08: Dq Delay estimate: 400
N2.C1.D1.R1.S00: Offset Found: RdPtrOffsetDqs = 007
N4.C1.D0.R1.S10: Dq Delay estimate: 450
ACCM: 0F 0F9F9F9F 0F0F0F0F
N2.C1.D1.R1.S01: Offset Found: RdPtrOffsetDqs = 007
N4.C1.D0.R1.S11: Dq Delay estimate: 440
ACCM: 0F 0F9F9F9F 0F0F0F0F
N2.C1.D1.R1.S02: Offset Found: RdPtrOffsetDqs = 007
N4.C1.D0.R1.S12: Dq Delay estimate: 426
ACCM: 0F FF9F9F9F FFFFFFFF
N2.C1.D1.R1.S03: Offset Found: RdPtrOffsetDqs = 007
N4.C1.D0.R1.S13: Dq Delay estimate: 390
ACCM: 0F FF9F9F9F FFFFFFFF
N2.C1.D1.R1.S04: Offset Found: RdPtrOffsetDqs = 006
N4.C1.D0.R1.S14: Dq Delay estimate: 407
N6.C0.D0.R0: CheckMCTest: result = 0x1FFFF
N0.C0.D0.R0: Write Training Coarse, lower nibbles / bytes
N2.C1.D1.R1.S05: Offset Found: RdPtrOffsetDqs = 006
N4.C1.D0.R1.S15: Dq Delay estimate: 417
ACCM: 0F 0FDFDFDF 0F0F0F0F
N0.C0.D0.R0.S00: Dq Delay estimate: 470
N2.C1.D1.R1.S06: Offset Found: RdPtrOffsetDqs = 007
N4.C1.D0.R1.S16: Dq Delay estimate: 435
ACCM: 0F 0FDFDFDF 0F0F0F0F
N0.C0.D0.R0.S01: Dq Delay estimate: 453
N2.C1.D1.R1.S07: Offset Found: RdPtrOffsetDqs = 007
N4.C1.D0.R1.S17: Dq Delay estimate: 402
ACCM: 0F FFDFDFDF FFFFFFFF
N0.C0.D0.R0.S02: Dq Delay estimate: 443
N2.C1.D1.R1.S08: Offset Found: RdPtrOffsetDqs = 006
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: 0F FFDFDFDF FFFFFFFF
N0.C0.D0.R0.S03: Dq Delay estimate: 423
N2.C1.D1.R1: Write Training Coarse, upper nibbles
ACCM: F0 F0F0F0F0 F0F0F0F0
N6.C0.D0.R0: CheckMCTest: result = 0x1FFFF
N0.C0.D0.R0.S04: Dq Delay estimate: 392
N2.C1.D1.R1.S09: Dq Delay estimate: 464
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: DF 0FDFDFDF 0F0F0F0F
N0.C0.D0.R0.S05: Dq Delay estimate: 408
N2.C1.D1.R1.S10: Dq Delay estimate: 448
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: DF 0FDFDFDF 0F0F0F0F
N0.C0.D0.R0.S06: Dq Delay estimate: 412
N2.C1.D1.R1.S11: Dq Delay estimate: 442
N4.C1.D0.R1: CheckMCTest: result = 0x3FE00
ACCM: D0 FBDBDBD0 F0F0F0F0
N0.C0.D0.R0.S07: Dq Delay estimate: 428
N2.C1.D1.R1.S12: Dq Delay estimate: 427
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: D0 FBDBDBD0 F0F0F0F0
N0.C0.D0.R0.S08: Dq Delay estimate: 403
N2.C1.D1.R1.S13: Dq Delay estimate: 392
ACCM: F0 F0F0F0F0 F0F0F0F0
N6.C0.D0.R0: CheckMCTest: result = 0x3FFFF
ACCM: 9F 0FFFFF9F 0F0F0F0F
N2.C1.D1.R1.S14: Dq Delay estimate: 405
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: DF 0FDFDFDF 0F0F0F0F
ACCM: 9F 0FFFFF9F 0F0F0F0F
N2.C1.D1.R1.S15: Dq Delay estimate: 416
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: DF 0FDFDFDF 0F0F0F0F
ACCM: 9F FFFFFF9F FFFFFFFF
N2.C1.D1.R1.S16: Dq Delay estimate: 438
N4.C1.D0.R1: CheckMCTest: result = 0x3FE00
ACCM: D0 FFDFDFD0 F0F0FDFD
ACCM: 9F FFFFFF9F FFFFFFFF
N2.C1.D1.R1.S17: Dq Delay estimate: 406
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: D0 FFDFDFD0 F0F0FDFD
N0.C0.D0.R0: CheckMCTest: result = 0x3FFFF
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: F0 F0F0F0F0 F0F0F0F0
N6.C0.D0.R0: CheckMCTest: result = 0x3FFFF
ACCM: 9F 0FFFFFDF 0F0F0F0F
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: B0 00B0B0B0 00000000
ACCM: 00 00D0D0D0 00000000
ACCM: 9F 0FFFFFDF 0F0F0F0F
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: B0 00B0B0B0 00000000
ACCM: 00 00D0D0D0 00000000
ACCM: 9F FFFFFFDF FFFFFFFF
ACCM: F0 F0F0F0F0 F0F0F0F0
N4.C1.D0.R1: CheckMCTest: result = 0x3FE00
ACCM: 00 F0D0D0D0 F0F0F0F0
ACCM: 9F FFFFFFDF FFFFFFFF
N2.C1.D1.R1: CheckMCTest: result = 0x3FE00
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: 00 F0D0D0D0 F0F0F0F0
N0.C0.D0.R0: CheckMCTest: result = 0x3FFFF
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: F0 F0F0F0F0 F0F0F0F0
N6.C0.D0.R0: CheckMCTest: result = 0x1FE00
ACCM: DF 0FFFFFDF 0F0F0F0F
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: F0 00F0F0F0 00000000
ACCM: 00 00D0D0D0 00000000
ACCM: DF 0FFFFFDF 0F0F0F0F
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: F0 00F0F0F0 00000000
ACCM: 00 00D0D0D0 00000000
ACCM: D0 FBFBF0DB F0FBF0F0
ACCM: F0 F0F0F0F0 F0F0F0F0
N4.C1.D0.R1: CheckMCTest: result = 0x3FE00
ACCM: 00 F0D0D0D0 F0F0F0F0
ACCM: D0 FBFBF0DB F0FBF0F0
N2.C1.D1.R1: CheckMCTest: result = 0x3FE00
N4.C1.D0.R1: CheckMCTest: passed
ACCM: 00 F0D0D0D0 F0F0F0F0
N0.C0.D0.R0: CheckMCTest: result = 0x3FFFF
ACCM: F0 F0F0F0F0 F0F0F0F0
N4.C1.D0.R1: CheckMCTest: passed
N6.C0.D0.R0: CheckMCTest: result = 0x1FE00
ACCM: DF 0FFFFFDF 0F0F0F0F
ACCM: F0 F0F0F0F0 F0F0F0F0
N4.C1.D0.R1.S09: Offset Found: RdPtrOffsetDqs = 007
N6.C0.D0.R0.S00: Offset Found: RdPtrOffsetDqs = 007
ACCM: DF 0FFFFFDF 0F0F0F0F
ACCM: 00 000000B0 B0000000
N4.C1.D0.R1.S10: Offset Found: RdPtrOffsetDqs = 007
N6.C0.D0.R0.S01: Offset Found: RdPtrOffsetDqs = 007
ACCM: D0 FFFFF0DF F0FFF0F0
ACCM: 00 000000B0 B0000000
N4.C1.D0.R1.S11: Offset Found: RdPtrOffsetDqs = 007
N6.C0.D0.R0.S02: Offset Found: RdPtrOffsetDqs = 007
ACCM: D0 FFFFF0DF F0FFF0F0
N2.C1.D1.R1: CheckMCTest: result = 0x3FE00
N4.C1.D0.R1.S12: Offset Found: RdPtrOffsetDqs = 007
N6.C0.D0.R0.S03: Offset Found: RdPtrOffsetDqs = 007
N0.C0.D0.R0: CheckMCTest: result = 0x3FFFF
ACCM: F0 F0F0F0F0 F0F0F0F0
N4.C1.D0.R1.S13: Offset Found: RdPtrOffsetDqs = 006
N6.C0.D0.R0.S04: Offset Found: RdPtrOffsetDqs = 006
ACCM: D0 00F0F0D0 00000000
ACCM: F0 F0F0F0F0 F0F0F0F0
N4.C1.D0.R1.S14: Offset Found: RdPtrOffsetDqs = 006
N6.C0.D0.R0.S05: Offset Found: RdPtrOffsetDqs = 006
ACCM: D0 00F0F0D0 00000000
ACCM: 00 000000F0 F0000000
N4.C1.D0.R1.S15: Offset Found: RdPtrOffsetDqs = 007
N6.C0.D0.R0.S06: Offset Found: RdPtrOffsetDqs = 006
ACCM: D0 F0F0F0D0 F0F0F0F0
ACCM: 00 000000F0 F0000000
N4.C1.D0.R1.S16: Offset Found: RdPtrOffsetDqs = 007
N6.C0.D0.R0.S07: Offset Found: RdPtrOffsetDqs = 007
ACCM: D0 F0F0F0D0 F0F0F0F0
N2.C1.D1.R1: CheckMCTest: result = 0x3FE00
N4.C1.D0.R1.S17: Offset Found: RdPtrOffsetDqs = 006
N6.C0.D0.R0.S08: Offset Found: RdPtrOffsetDqs = 006
N0.C0.D0.R0: CheckMCTest: result = 0x3FE00
N2.C1.D1.R1: CheckMCTest: passed
N4.C1.D1.R0: Write Training Coarse, lower nibbles / bytes
N6.C0.D0.R0: Write Training Coarse, upper nibbles
ACCM: D0 00F0F0D0 00000000
N2.C1.D1.R1: CheckMCTest: passed
N4.C1.D1.R0.S00: Dq Delay estimate: 472
N6.C0.D0.R0.S09: Dq Delay estimate: 470
ACCM: D0 00F0F0D0 00000000
N2.C1.D1.R1.S09: Offset Found: RdPtrOffsetDqs = 007
N4.C1.D1.R0.S01: Dq Delay estimate: 456
N6.C0.D0.R0.S10: Dq Delay estimate: 450
ACCM: D0 F0F0F0D0 F0F0F0F0
N2.C1.D1.R1.S10: Offset Found: RdPtrOffsetDqs = 007
N4.C1.D1.R0.S02: Dq Delay estimate: 444
N6.C0.D0.R0.S11: Dq Delay estimate: 436
ACCM: D0 F0F0F0D0 F0F0F0F0
N2.C1.D1.R1.S11: Offset Found: RdPtrOffsetDqs = 007
N4.C1.D1.R0.S03: Dq Delay estimate: 428
N6.C0.D0.R0.S12: Dq Delay estimate: 422
N0.C0.D0.R0: CheckMCTest: result = 0x3FE00
N2.C1.D1.R1.S12: Offset Found: RdPtrOffsetDqs = 007
N4.C1.D1.R0.S04: Dq Delay estimate: 394
N6.C0.D0.R0.S13: Dq Delay estimate: 388
N0.C0.D0.R0.S00: Offset Found: RdPtrOffsetDqs = 007
N2.C1.D1.R1.S13: Offset Found: RdPtrOffsetDqs = 006
N4.C1.D1.R0.S05: Dq Delay estimate: 408
N6.C0.D0.R0.S14: Dq Delay estimate: 406
N0.C0.D0.R0.S01: Offset Found: RdPtrOffsetDqs = 007
N2.C1.D1.R1.S14: Offset Found: RdPtrOffsetDqs = 006
N4.C1.D1.R0.S06: Dq Delay estimate: 421
N6.C0.D0.R0.S15: Dq Delay estimate: 406
N0.C0.D0.R0.S02: Offset Found: RdPtrOffsetDqs = 007
N2.C1.D1.R1.S15: Offset Found: RdPtrOffsetDqs = 007
N4.C1.D1.R0.S07: Dq Delay estimate: 437
N6.C0.D0.R0.S16: Dq Delay estimate: 423
N0.C0.D0.R0.S03: Offset Found: RdPtrOffsetDqs = 007
N2.C1.D1.R1.S16: Offset Found: RdPtrOffsetDqs = 007
N4.C1.D1.R0.S08: Dq Delay estimate: 407
N6.C0.D0.R0.S17: Dq Delay estimate: 401
N0.C0.D0.R0.S04: Offset Found: RdPtrOffsetDqs = 006
N2.C1.D1.R1.S17: Offset Found: RdPtrOffsetDqs = 006
ACCM: 0F 0F0F0F0F 0F0F0F0F
ACCM: F0 F0F0F0F0 F0F0F0F0
N0.C0.D0.R0.S05: Offset Found: RdPtrOffsetDqs = 006
N2.C1: Calculating Optimimum DQS Values
ACCM: 0F 0F0F0F0F 0F0F0F0F
ACCM: F0 F0F0F0F0 F0F0F0F0
N0.C0.D0.R0.S06: Offset Found: RdPtrOffsetDqs = 006
N2.C1.D0.R0.S00: Total Delay in PI ticks: TxDQS = 1011, TxDQ = 978
ACCM: 0F 0F0F0F0F 0F0F0F0F
ACCM: F0 F0F0F0F0 F0F0F0F0
N0.C0.D0.R0.S07: Offset Found: RdPtrOffsetDqs = 007
N2.C1.D0.R0.S01: Total Delay in PI ticks: TxDQS = 994, TxDQ = 960
ACCM: 0F FFFF0F0F FFFF0F0F
ACCM: F0 F0F0F0F0 F0F0F0F0
N0.C0.D0.R0.S08: Offset Found: RdPtrOffsetDqs = 006
N2.C1.D0.R0.S02: Total Delay in PI ticks: TxDQS = 987, TxDQ = 955
N4.C1.D1.R0: CheckMCTest: result = 0x199FF
N6.C0.D0.R0: CheckMCTest: result = 0x3FE00
N0.C0.D0.R0: Write Training Coarse, upper nibbles
N2.C1.D0.R0.S03: Total Delay in PI ticks: TxDQS = 969, TxDQ = 935
ACCM: 0F 0F0F0F0F 0F0F0F0F
ACCM: F0 F0F0F0F0 F0F0F0F0
N0.C0.D0.R0.S09: Dq Delay estimate: 471
N2.C1.D0.R0.S04: Total Delay in PI ticks: TxDQS = 937, TxDQ = 903
ACCM: 0F 0F0F0F0F 0F0F0F0F
ACCM: F0 F0F0F0F0 F0F0F0F0
N0.C0.D0.R0.S10: Dq Delay estimate: 452
N2.C1.D0.R0.S05: Total Delay in PI ticks: TxDQS = 952, TxDQ = 918
ACCM: 0F 0F0F0F0F 0F0F0F0F
ACCM: F0 F0F0F0F0 F0F0F0F0
N0.C0.D0.R0.S11: Dq Delay estimate: 443
N2.C1.D0.R0.S06: Total Delay in PI ticks: TxDQS = 966, TxDQ = 933
ACCM: 0F FFFF0F0F FFFF0F0F
ACCM: F0 F0F0F0F0 F0F0F0F0
N0.C0.D0.R0.S12: Dq Delay estimate: 425
N2.C1.D0.R0.S07: Total Delay in PI ticks: TxDQS = 982, TxDQ = 948
N4.C1.D1.R0: CheckMCTest: result = 0x199FF
N6.C0.D0.R0: CheckMCTest: result = 0x3FE00
N0.C0.D0.R0.S13: Dq Delay estimate: 392
N2.C1.D0.R0.S08: Total Delay in PI ticks: TxDQS = 952, TxDQ = 922
ACCM: 0F 0F0F0F0F 0F0F0F0F
ACCM: F0 F0F0F0F0 F0F0F0F0
N0.C0.D0.R0.S14: Dq Delay estimate: 407
N2.C1.D0.R0.S09: Total Delay in PI ticks: TxDQS = 1012, TxDQ = 979
ACCM: 0F 0F0F0F0F 0F0F0F0F
ACCM: F0 F0F0F0F0 F0F0F0F0
N0.C0.D0.R0.S15: Dq Delay estimate: 414
N2.C1.D0.R0.S10: Total Delay in PI ticks: TxDQS = 994, TxDQ = 962
ACCM: 0B 000B0B0B 00000B0B
ACCM: 00 00B00000 0000B000
N0.C0.D0.R0.S16: Dq Delay estimate: 430
N2.C1.D0.R0.S11: Total Delay in PI ticks: TxDQS = 987, TxDQ = 955
ACCM: 0B F0FB0B0B F0F00B0B
ACCM: 00 00B00000 0000B000
N0.C0.D0.R0.S17: Dq Delay estimate: 400
N2.C1.D0.R0.S12: Total Delay in PI ticks: TxDQS = 969, TxDQ = 938
N4.C1.D1.R0: CheckMCTest: result = 0x199FF
N6.C0.D0.R0: CheckMCTest: result = 0x3FE00
ACCM: F0 F0F0F0F0 F0F0F0F0
N2.C1.D0.R0.S13: Total Delay in PI ticks: TxDQS = 937, TxDQ = 907
ACCM: 0F 0F0F0F0F 0F0F0F0F
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: F0 F0F0F0F0 F0F0F0F0
N2.C1.D0.R0.S14: Total Delay in PI ticks: TxDQS = 952, TxDQ = 917
ACCM: 0F 0F0F0F0F 0F0F0F0F
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: F0 F0F0F0F0 F0F0F0F0
N2.C1.D0.R0.S15: Total Delay in PI ticks: TxDQS = 965, TxDQ = 931
ACCM: 0F 000F0F0F 000C0F0F
ACCM: 00 00F00000 0000F000
ACCM: F0 F0F0F0F0 F0F0F0F0
N2.C1.D0.R0.S16: Total Delay in PI ticks: TxDQS = 983, TxDQ = 949
ACCM: 0F F0FF0F0F F0FC0F0F
ACCM: 00 00F00000 0000F000
N0.C0.D0.R0: CheckMCTest: result = 0x3FE00
N2.C1.D0.R0.S17: Total Delay in PI ticks: TxDQS = 950, TxDQ = 922
N4.C1.D1.R0: CheckMCTest: result = 0x199FF
N6.C0.D0.R0: CheckMCTest: result = 0x3FE00
ACCM: F0 F0F0F0F0 F0F0F0F0
N2.C1.D0.R1.S00: Total Delay in PI ticks: TxDQS = 1004, TxDQ = 972
ACCM: 00 00000000 00000000
N6.C0.D0.R0: CheckMCTest: passed
ACCM: F0 F0F0F0F0 F0F0F0F0
N2.C1.D0.R1.S01: Total Delay in PI ticks: TxDQS = 988, TxDQ = 954
ACCM: 00 00000000 00000000
N6.C0.D0.R0: CheckMCTest: passed
ACCM: F0 F0F0F0F0 F0F0F0F0
N2.C1.D0.R1.S02: Total Delay in PI ticks: TxDQS = 980, TxDQ = 947
ACCM: 00 00000000 00000000
N6.C0.D0.R0.S09: Offset Found: RdPtrOffsetDqs = 007
ACCM: F0 F0F0F0F0 F0F0F0F0
N2.C1.D0.R1.S03: Total Delay in PI ticks: TxDQS = 963, TxDQ = 929
ACCM: 00 F0F00000 F0F00000
N6.C0.D0.R0.S10: Offset Found: RdPtrOffsetDqs = 007
N0.C0.D0.R0: CheckMCTest: result = 0x3FE00
N2.C1.D0.R1.S04: Total Delay in PI ticks: TxDQS = 932, TxDQ = 898
N4.C1.D1.R0: CheckMCTest: result = 0x19800
N6.C0.D0.R0.S11: Offset Found: RdPtrOffsetDqs = 007
ACCM: F0 F0F0F0F0 F0F0F0F0
N2.C1.D0.R1.S05: Total Delay in PI ticks: TxDQS = 945, TxDQ = 912
ACCM: 00 00000000 00000000
N6.C0.D0.R0.S12: Offset Found: RdPtrOffsetDqs = 007
ACCM: F0 F0F0F0F0 F0F0F0F0
N2.C1.D0.R1.S06: Total Delay in PI ticks: TxDQS = 957, TxDQ = 924
ACCM: 00 00000000 00000000
N6.C0.D0.R0.S13: Offset Found: RdPtrOffsetDqs = 006
ACCM: 00 B000B0B0 B0B000B0
N2.C1.D0.R1.S07: Total Delay in PI ticks: TxDQS = 975, TxDQ = 941
ACCM: 00 00000000 00000000
N6.C0.D0.R0.S14: Offset Found: RdPtrOffsetDqs = 006
ACCM: 00 B000B0B0 B0B000B0
N2.C1.D0.R1.S08: Total Delay in PI ticks: TxDQS = 945, TxDQ = 914
ACCM: 00 F0F00000 F0F00000
N6.C0.D0.R0.S15: Offset Found: RdPtrOffsetDqs = 006
N0.C0.D0.R0: CheckMCTest: result = 0x3FE00
N2.C1.D0.R1.S09: Total Delay in PI ticks: TxDQS = 1003, TxDQ = 971
N4.C1.D1.R0: CheckMCTest: result = 0x19800
N6.C0.D0.R0.S16: Offset Found: RdPtrOffsetDqs = 007
ACCM: F0 F0F0F0F0 F0F0F0F0
N2.C1.D0.R1.S10: Total Delay in PI ticks: TxDQS = 988, TxDQ = 957
N4.C1.D1.R0.S00: Offset Found: RdPtrOffsetDqs = 007
N6.C0.D0.R0.S17: Offset Found: RdPtrOffsetDqs = 006
ACCM: F0 F0F0F0F0 F0F0F0F0
N2.C1.D0.R1.S11: Total Delay in PI ticks: TxDQS = 979, TxDQ = 947
N4.C1.D1.R0.S01: Offset Found: RdPtrOffsetDqs = 007
N6.C0.D0.R1: Write Training Coarse, lower nibbles / bytes
ACCM: 00 F000F0B0 F0F000F0
N2.C1.D0.R1.S12: Total Delay in PI ticks: TxDQS = 964, TxDQ = 932
N4.C1.D1.R0.S02: Offset Found: RdPtrOffsetDqs = 007
N6.C0.D0.R1.S00: Dq Delay estimate: 464
ACCM: 00 F000F0B0 F0F000F0
N2.C1.D0.R1.S13: Total Delay in PI ticks: TxDQS = 930, TxDQ = 898
N4.C1.D1.R0.S03: Offset Found: RdPtrOffsetDqs = 007
N6.C0.D0.R1.S01: Dq Delay estimate: 441
N0.C0.D0.R0: CheckMCTest: result = 0x3FE00
N2.C1.D0.R1.S14: Total Delay in PI ticks: TxDQS = 945, TxDQ = 912
N4.C1.D1.R0.S04: Offset Found: RdPtrOffsetDqs = 006
N6.C0.D0.R1.S02: Dq Delay estimate: 430
N0.C0.D0.R0: CheckMCTest: passed
N2.C1.D0.R1.S15: Total Delay in PI ticks: TxDQS = 959, TxDQ = 925
N4.C1.D1.R0.S05: Offset Found: RdPtrOffsetDqs = 006
N6.C0.D0.R1.S03: Dq Delay estimate: 414
N0.C0.D0.R0: CheckMCTest: passed
N2.C1.D0.R1.S16: Total Delay in PI ticks: TxDQS = 975, TxDQ = 942
N4.C1.D1.R0.S06: Offset Found: RdPtrOffsetDqs = 007
N6.C0.D0.R1.S04: Dq Delay estimate: 380
N0.C0.D0.R0.S09: Offset Found: RdPtrOffsetDqs = 007
N2.C1.D0.R1.S17: Total Delay in PI ticks: TxDQS = 946, TxDQ = 918
N4.C1.D1.R0.S07: Offset Found: RdPtrOffsetDqs = 007
N6.C0.D0.R1.S05: Dq Delay estimate: 399
N0.C0.D0.R0.S10: Offset Found: RdPtrOffsetDqs = 007
N2.C1.D1.R0.S00: Total Delay in PI ticks: TxDQS = 1016, TxDQ = 981
N4.C1.D1.R0.S08: Offset Found: RdPtrOffsetDqs = 006
N6.C0.D0.R1.S06: Dq Delay estimate: 402
N0.C0.D0.R0.S11: Offset Found: RdPtrOffsetDqs = 007
N2.C1.D1.R0.S01: Total Delay in PI ticks: TxDQS = 1001, TxDQ = 965
N4.C1.D1.R0: Write Training Coarse, upper nibbles
N6.C0.D0.R1.S07: Dq Delay estimate: 419
N0.C0.D0.R0.S12: Offset Found: RdPtrOffsetDqs = 007
N2.C1.D1.R0.S02: Total Delay in PI ticks: TxDQS = 993, TxDQ = 958
N4.C1.D1.R0.S09: Dq Delay estimate: 470
N6.C0.D0.R1.S08: Dq Delay estimate: 391
N0.C0.D0.R0.S13: Offset Found: RdPtrOffsetDqs = 006
N2.C1.D1.R0.S03: Total Delay in PI ticks: TxDQS = 975, TxDQ = 940
N4.C1.D1.R0.S10: Dq Delay estimate: 454
ACCM: 0F 0F0F0F0F 0F0F0F0F
N0.C0.D0.R0.S14: Offset Found: RdPtrOffsetDqs = 006
N2.C1.D1.R0.S04: Total Delay in PI ticks: TxDQS = 944, TxDQ = 908
N4.C1.D1.R0.S11: Dq Delay estimate: 447
ACCM: 0F 0F0F0F0F 0F0F0F0F
N0.C0.D0.R0.S15: Offset Found: RdPtrOffsetDqs = 006
N2.C1.D1.R0.S05: Total Delay in PI ticks: TxDQS = 959, TxDQ = 924
N4.C1.D1.R0.S12: Dq Delay estimate: 429
ACCM: 0F 0F0F0F0F 0F0F0F0F
N0.C0.D0.R0.S16: Offset Found: RdPtrOffsetDqs = 007
N2.C1.D1.R0.S06: Total Delay in PI ticks: TxDQS = 970, TxDQ = 936
N4.C1.D1.R0.S13: Dq Delay estimate: 394
ACCM: 0F 0F0F0F0F 0F0F0F0F
N0.C0.D0.R0.S17: Offset Found: RdPtrOffsetDqs = 006
N2.C1.D1.R0.S07: Total Delay in PI ticks: TxDQS = 989, TxDQ = 953
N4.C1.D1.R0.S14: Dq Delay estimate: 411
N6.C0.D0.R1: CheckMCTest: result = 0x1FF
N0.C0.D0.R1: Write Training Coarse, lower nibbles / bytes
N2.C1.D1.R0.S08: Total Delay in PI ticks: TxDQS = 954, TxDQ = 920
N4.C1.D1.R0.S15: Dq Delay estimate: 422
ACCM: 0F 0F0F0F0F 0F0F0F0F
N0.C0.D0.R1.S00: Dq Delay estimate: 465
N2.C1.D1.R0.S09: Total Delay in PI ticks: TxDQS = 1017, TxDQ = 983
N4.C1.D1.R0.S16: Dq Delay estimate: 442
ACCM: 0F 0F0F0F0F 0F0F0F0F
N0.C0.D0.R1.S01: Dq Delay estimate: 447
N2.C1.D1.R0.S10: Total Delay in PI ticks: TxDQS = 1000, TxDQ = 965
N4.C1.D1.R0.S17: Dq Delay estimate: 406
ACCM: 0F 0F0F0F0F 0F0F0F0F
N0.C0.D0.R1.S02: Dq Delay estimate: 435
N2.C1.D1.R0.S11: Total Delay in PI ticks: TxDQS = 993, TxDQ = 960
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: 0F 0F0F0F0F 0F0F0F0F
N0.C0.D0.R1.S03: Dq Delay estimate: 417
N2.C1.D1.R0.S12: Total Delay in PI ticks: TxDQS = 977, TxDQ = 942
ACCM: F0 F0F0F0F0 F0F0F0F0
N6.C0.D0.R1: CheckMCTest: result = 0x1FF
N0.C0.D0.R1.S04: Dq Delay estimate: 385
N2.C1.D1.R0.S13: Total Delay in PI ticks: TxDQS = 943, TxDQ = 909
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: 0F 0F0F0F0F 0F0F0F0F
N0.C0.D0.R1.S05: Dq Delay estimate: 400
N2.C1.D1.R0.S14: Total Delay in PI ticks: TxDQS = 959, TxDQ = 923
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: 0F 0F0F0F0F 0F0F0F0F
N0.C0.D0.R1.S06: Dq Delay estimate: 403
N2.C1.D1.R0.S15: Total Delay in PI ticks: TxDQS = 969, TxDQ = 933
N4.C1.D1.R0: CheckMCTest: result = 0x3FE00
ACCM: 00 0000000B 0B000B0B
N0.C0.D0.R1.S07: Dq Delay estimate: 422
N2.C1.D1.R0.S16: Total Delay in PI ticks: TxDQS = 988, TxDQ = 953
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: 00 0000000B 0B000B0B
N0.C0.D0.R1.S08: Dq Delay estimate: 394
N2.C1.D1.R0.S17: Total Delay in PI ticks: TxDQS = 955, TxDQ = 924
ACCM: F0 F0F0F0F0 F0F0F0F0
N6.C0.D0.R1: CheckMCTest: result = 0x1FF
ACCM: 0F 0F0F0F0F 0F0F0F0F
N2.C1.D1.R1.S00: Total Delay in PI ticks: TxDQS = 1012, TxDQ = 977
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: 0F 0F0F0F0F 0F0F0F0F
ACCM: 0F 0F0F0F0F 0F0F0F0F
N2.C1.D1.R1.S01: Total Delay in PI ticks: TxDQS = 996, TxDQ = 960
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: 0F 0F0F0F0F 0F0F0F0F
ACCM: 0F 0F0F0F0F 0F0F0F0F
N2.C1.D1.R1.S02: Total Delay in PI ticks: TxDQS = 988, TxDQ = 953
N4.C1.D1.R0: CheckMCTest: result = 0x3FE00
ACCM: 00 0000000B 0B000F0F
ACCM: 0F 0F0F0F0F 0F0F0F0F
N2.C1.D1.R1.S03: Total Delay in PI ticks: TxDQS = 971, TxDQ = 936
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: 00 0000000B 0B000F0F
N0.C0.D0.R1: CheckMCTest: result = 0x1FF
N2.C1.D1.R1.S04: Total Delay in PI ticks: TxDQS = 939, TxDQ = 903
ACCM: F0 F0F0F0F0 F0F0F0F0
N6.C0.D0.R1: CheckMCTest: result = 0x1FF
ACCM: 0F 0F0F0F0F 0F0F0F0F
N2.C1.D1.R1.S05: Total Delay in PI ticks: TxDQS = 954, TxDQ = 919
ACCM: 00 B0000000 0000B000
N6.C0.D0.R1: CheckMCTest: passed
ACCM: 0F 0F0F0F0F 0F0F0F0F
N2.C1.D1.R1.S06: Total Delay in PI ticks: TxDQS = 967, TxDQ = 932
ACCM: 00 B0000000 0000B000
N6.C0.D0.R1: CheckMCTest: passed
ACCM: 0F 0F0F0F0F 0F0F0F0F
N2.C1.D1.R1.S07: Total Delay in PI ticks: TxDQS = 985, TxDQ = 949
N4.C1.D1.R0: CheckMCTest: result = 0x3FE00
N6.C0.D0.R1.S00: Offset Found: RdPtrOffsetDqs = 007
ACCM: 0F 0F0F0F0F 0F0F0F0F
N2.C1.D1.R1.S08: Total Delay in PI ticks: TxDQS = 949, TxDQ = 914
ACCM: F0 F0F0F0F0 F0F0F0F0
N6.C0.D0.R1.S01: Offset Found: RdPtrOffsetDqs = 007
N0.C0.D0.R1: CheckMCTest: result = 0x1FF
N2.C1.D1.R1.S09: Total Delay in PI ticks: TxDQS = 1011, TxDQ = 976
ACCM: F0 F0F0F0F0 F0F0F0F0
N6.C0.D0.R1.S02: Offset Found: RdPtrOffsetDqs = 007
ACCM: 0F 0F0F0F0F 0F0F0F0F
N2.C1.D1.R1.S10: Total Delay in PI ticks: TxDQS = 995, TxDQ = 960
ACCM: 00 F0000000 0000F000
N6.C0.D0.R1.S03: Offset Found: RdPtrOffsetDqs = 006
ACCM: 0F 0F0F0F0F 0F0F0F0F
N2.C1.D1.R1.S11: Total Delay in PI ticks: TxDQS = 988, TxDQ = 954
ACCM: 00 F0000000 0000F000
N6.C0.D0.R1.S04: Offset Found: RdPtrOffsetDqs = 006
ACCM: 0B 0B000000 000B0000
N2.C1.D1.R1.S12: Total Delay in PI ticks: TxDQS = 974, TxDQ = 939
N4.C1.D1.R0: CheckMCTest: result = 0x3FE00
N6.C0.D0.R1.S05: Offset Found: RdPtrOffsetDqs = 006
ACCM: 0B 0B000000 000B0000
N2.C1.D1.R1.S13: Total Delay in PI ticks: TxDQS = 939, TxDQ = 904
N4.C1.D1.R0: CheckMCTest: passed
N6.C0.D0.R1.S06: Offset Found: RdPtrOffsetDqs = 006
N0.C0.D0.R1: CheckMCTest: result = 0x1FF
N2.C1.D1.R1.S14: Total Delay in PI ticks: TxDQS = 953, TxDQ = 917
N4.C1.D1.R0: CheckMCTest: passed
N6.C0.D0.R1.S07: Offset Found: RdPtrOffsetDqs = 007
ACCM: 0F 0F0F0F0F 0F0F0F0F
N2.C1.D1.R1.S15: Total Delay in PI ticks: TxDQS = 964, TxDQ = 928
N4.C1.D1.R0.S09: Offset Found: RdPtrOffsetDqs = 007
N6.C0.D0.R1.S08: Offset Found: RdPtrOffsetDqs = 006
ACCM: 0F 0F0F0F0F 0F0F0F0F
N2.C1.D1.R1.S16: Total Delay in PI ticks: TxDQS = 985, TxDQ = 950
N4.C1.D1.R0.S10: Offset Found: RdPtrOffsetDqs = 007
N6.C0.D0.R1: Write Training Coarse, upper nibbles
ACCM: 0F 0F000000 000B0000
N2.C1.D1.R1.S17: Total Delay in PI ticks: TxDQS = 949, TxDQ = 918
N4.C1.D1.R0.S11: Offset Found: RdPtrOffsetDqs = 007
N6.C0.D0.R1.S09: Dq Delay estimate: 459
ACCM: 0F 0F000000 000B0000
N2.C2.D0.R0: Write Training Coarse, lower nibbles / bytes
N4.C1.D1.R0.S12: Offset Found: RdPtrOffsetDqs = 007
N6.C0.D0.R1.S10: Dq Delay estimate: 445
N0.C0.D0.R1: CheckMCTest: result = 0x1FF
N2.C2.D0.R0.S00: Dq Delay estimate: 465
N4.C1.D1.R0.S13: Offset Found: RdPtrOffsetDqs = 006
N6.C0.D0.R1.S11: Dq Delay estimate: 431
N0.C0.D0.R1: CheckMCTest: passed
N2.C2.D0.R0.S01: Dq Delay estimate: 449
N4.C1.D1.R0.S14: Offset Found: RdPtrOffsetDqs = 006
N6.C0.D0.R1.S12: Dq Delay estimate: 417
N0.C0.D0.R1: CheckMCTest: passed
N2.C2.D0.R0.S02: Dq Delay estimate: 437
N4.C1.D1.R0.S15: Offset Found: RdPtrOffsetDqs = 007
N6.C0.D0.R1.S13: Dq Delay estimate: 382
N0.C0.D0.R1.S00: Offset Found: RdPtrOffsetDqs = 007
N2.C2.D0.R0.S03: Dq Delay estimate: 420
N4.C1.D1.R0.S16: Offset Found: RdPtrOffsetDqs = 007
N6.C0.D0.R1.S14: Dq Delay estimate: 398
N0.C0.D0.R1.S01: Offset Found: RdPtrOffsetDqs = 007
N2.C2.D0.R0.S04: Dq Delay estimate: 380
N4.C1.D1.R0.S17: Offset Found: RdPtrOffsetDqs = 006
N6.C0.D0.R1.S15: Dq Delay estimate: 401
N0.C0.D0.R1.S02: Offset Found: RdPtrOffsetDqs = 007
N2.C2.D0.R0.S05: Dq Delay estimate: 408
N4.C1.D1.R1: Write Training Coarse, lower nibbles / bytes
N6.C0.D0.R1.S16: Dq Delay estimate: 418
N0.C0.D0.R1.S03: Offset Found: RdPtrOffsetDqs = 007
N2.C2.D0.R0.S06: Dq Delay estimate: 406
N4.C1.D1.R1.S00: Dq Delay estimate: 467
N6.C0.D0.R1.S17: Dq Delay estimate: 390
N0.C0.D0.R1.S04: Offset Found: RdPtrOffsetDqs = 006
N2.C2.D0.R0.S07: Dq Delay estimate: 425
N4.C1.D1.R1.S01: Dq Delay estimate: 452
ACCM: F0 F0F0F0F0 F0F0F0F0
N0.C0.D0.R1.S05: Offset Found: RdPtrOffsetDqs = 006
N2.C2.D0.R0.S08: Dq Delay estimate: 401
N4.C1.D1.R1.S02: Dq Delay estimate: 442
ACCM: F0 F0F0F0F0 F0F0F0F0
N0.C0.D0.R1.S06: Offset Found: RdPtrOffsetDqs = 006
ACCM: 9F 0F9F9F9F 0F0F0F0F
N4.C1.D1.R1.S03: Dq Delay estimate: 428
ACCM: F0 F0F0F0F0 F0F0F0F0
N0.C0.D0.R1.S07: Offset Found: RdPtrOffsetDqs = 007
ACCM: 9F 0F9F9F9F 0F0F0F0F
N4.C1.D1.R1.S04: Dq Delay estimate: 393
ACCM: F0 F0F0F0F0 F0F0F0F0
N0.C0.D0.R1.S08: Offset Found: RdPtrOffsetDqs = 006
ACCM: 9F FF9F9F9F FFFFFFFF
N4.C1.D1.R1.S05: Dq Delay estimate: 408
N6.C0.D0.R1: CheckMCTest: result = 0x3FE00
N0.C0.D0.R1: Write Training Coarse, upper nibbles
ACCM: 9F FF9F9F9F FFFFFFFF
N4.C1.D1.R1.S06: Dq Delay estimate: 416
ACCM: F0 F0F0F0F0 F0F0F0F0
N0.C0.D0.R1.S09: Dq Delay estimate: 463
N2.C2.D0.R0: CheckMCTest: result = 0x3FFFF
N4.C1.D1.R1.S07: Dq Delay estimate: 436
ACCM: F0 F0F0F0F0 F0F0F0F0
N0.C0.D0.R1.S10: Dq Delay estimate: 447
ACCM: 9F 0FDFDFDF 0F0F0F0F
N4.C1.D1.R1.S08: Dq Delay estimate: 403
ACCM: F0 F0F0F0F0 F0F0F0F0
N0.C0.D0.R1.S11: Dq Delay estimate: 435
ACCM: 9F 0FDFDFDF 0F0F0F0F
ACCM: 0F 0F0F0F0F 0F0F0F0F
ACCM: F0 F0F0F0F0 F0F0F0F0
N0.C0.D0.R1.S12: Dq Delay estimate: 421
ACCM: 9F FFDFDFDF FFFFFFFF
ACCM: 0F 0F0F0F0F 0F0F0F0F
N6.C0.D0.R1: CheckMCTest: result = 0x3FE00
N0.C0.D0.R1.S13: Dq Delay estimate: 387
ACCM: 9F FFDFDFDF FFFFFFFF
ACCM: 0F 0F0F0F0F 0F0F0F0F
ACCM: F0 F0F0F0F0 F0F0F0F0
N0.C0.D0.R1.S14: Dq Delay estimate: 404
N2.C2.D0.R0: CheckMCTest: result = 0x3FFFF
ACCM: 0F 0F0F0F0F 0F0F0F0F
ACCM: F0 F0F0F0F0 F0F0F0F0
N0.C0.D0.R1.S15: Dq Delay estimate: 407
ACCM: 0F 0FDFDFDF 0F0F0F0F
N4.C1.D1.R1: CheckMCTest: result = 0x1FF
ACCM: 00 000000B0 0000B000
N0.C0.D0.R1.S16: Dq Delay estimate: 424
ACCM: 0F 0FDFDFDF 0F0F0F0F
ACCM: 0F 0F0F0F0F 0F0F0F0F
ACCM: 00 000000B0 0000B000
N0.C0.D0.R1.S17: Dq Delay estimate: 393
ACCM: 00 FBD0DBDB F0F0F0F0
ACCM: 0F 0F0F0F0F 0F0F0F0F
N6.C0.D0.R1: CheckMCTest: result = 0x3FE00
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: 00 FBD0DBDB F0F0F0F0
ACCM: 0F 0F0F0F0F 0F0F0F0F
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: F0 F0F0F0F0 F0F0F0F0
N2.C2.D0.R0: CheckMCTest: result = 0x1FFFF
ACCM: 0F 0F0F0F0F 0F0F0F0F
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: 0F 0FDFDFDF 0F0F0F0F
N4.C1.D1.R1: CheckMCTest: result = 0x1FF
ACCM: 00 000000B0 0000F000
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: 0F 0FDFDFDF 0F0F0F0F
ACCM: 0F 0F0F0F0F 0F0F0F0F
ACCM: 00 000000B0 0000F000
N0.C0.D0.R1: CheckMCTest: result = 0x3FE00
ACCM: 00 FFDDDFDF F0F0F0FD
ACCM: 0F 0F0F0F0F 0F0F0F0F
N6.C0.D0.R1: CheckMCTest: result = 0x3FE00
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: 00 FFDDDFDF F0F0F0FD
ACCM: 00 00000B0B 0B00000B
N6.C0.D0.R1: CheckMCTest: passed
ACCM: F0 F0F0F0F0 F0F0F0F0
N2.C2.D0.R0: CheckMCTest: result = 0x1FFFF
ACCM: 00 00000B0B 0B00000B
N6.C0.D0.R1: CheckMCTest: passed
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: 00 00D0D0D0 00000000
N4.C1.D1.R1: CheckMCTest: result = 0x1FF
N6.C0.D0.R1.S09: Offset Found: RdPtrOffsetDqs = 007
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: 00 00D0D0D0 00000000
ACCM: 0F 0F0F0F0F 0F0F0F0F
N6.C0.D0.R1.S10: Offset Found: RdPtrOffsetDqs = 007
N0.C0.D0.R1: CheckMCTest: result = 0x3FE00
ACCM: 00 F0D0D0D0 F0F0F0F0
ACCM: 0F 0F0F0F0F 0F0F0F0F
N6.C0.D0.R1.S11: Offset Found: RdPtrOffsetDqs = 007
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: 00 F0D0D0D0 F0F0F0F0
ACCM: 00 00000F0F 0F000D0F
N6.C0.D0.R1.S12: Offset Found: RdPtrOffsetDqs = 007
ACCM: F0 F0F0F0F0 F0F0F0F0
N2.C2.D0.R0: CheckMCTest: result = 0x1FE00
ACCM: 00 00000F0F 0F000D0F
N6.C0.D0.R1.S13: Offset Found: RdPtrOffsetDqs = 006
ACCM: 00 B0B0B0B0 00B0B000
ACCM: 00 00D0D0D0 00000000
N4.C1.D1.R1: CheckMCTest: result = 0x1FF
N6.C0.D0.R1.S14: Offset Found: RdPtrOffsetDqs = 006
ACCM: 00 B0B0B0B0 00B0B000
ACCM: 00 00D0D0D0 00000000
N4.C1.D1.R1: CheckMCTest: passed
N6.C0.D0.R1.S15: Offset Found: RdPtrOffsetDqs = 006
N0.C0.D0.R1: CheckMCTest: result = 0x3FE00
ACCM: 00 F0D0D0D0 F0F0F0F0
N4.C1.D1.R1: CheckMCTest: passed
N6.C0.D0.R1.S16: Offset Found: RdPtrOffsetDqs = 007
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: 00 F0D0D0D0 F0F0F0F0
N4.C1.D1.R1.S00: Offset Found: RdPtrOffsetDqs = 007
N6.C0.D0.R1.S17: Offset Found: RdPtrOffsetDqs = 006
ACCM: F0 F0F0F0F0 F0F0F0F0
N2.C2.D0.R0: CheckMCTest: result = 0x1FE00
N4.C1.D1.R1.S01: Offset Found: RdPtrOffsetDqs = 007
N6.C0.D1.R0: Write Training Coarse, lower nibbles / bytes
ACCM: 00 F0B0F0F0 00F0F000
N2.C2.D0.R0.S00: Offset Found: RdPtrOffsetDqs = 007
N4.C1.D1.R1.S02: Offset Found: RdPtrOffsetDqs = 007
N6.C0.D1.R0.S00: Dq Delay estimate: 467
ACCM: 00 F0B0F0F0 00F0F000
N2.C2.D0.R0.S01: Offset Found: RdPtrOffsetDqs = 007
N4.C1.D1.R1.S03: Offset Found: RdPtrOffsetDqs = 007
N6.C0.D1.R0.S01: Dq Delay estimate: 450
N0.C0.D0.R1: CheckMCTest: result = 0x3FE00
N2.C2.D0.R0.S02: Offset Found: RdPtrOffsetDqs = 007
N4.C1.D1.R1.S04: Offset Found: RdPtrOffsetDqs = 006
N6.C0.D1.R0.S02: Dq Delay estimate: 437
N0.C0.D0.R1: CheckMCTest: passed
N2.C2.D0.R0.S03: Offset Found: RdPtrOffsetDqs = 007
N4.C1.D1.R1.S05: Offset Found: RdPtrOffsetDqs = 006
N6.C0.D1.R0.S03: Dq Delay estimate: 426
N0.C0.D0.R1: CheckMCTest: passed
N2.C2.D0.R0.S04: Offset Found: RdPtrOffsetDqs = 006
N4.C1.D1.R1.S06: Offset Found: RdPtrOffsetDqs = 007
N6.C0.D1.R0.S04: Dq Delay estimate: 388
N0.C0.D0.R1.S09: Offset Found: RdPtrOffsetDqs = 007
N2.C2.D0.R0.S05: Offset Found: RdPtrOffsetDqs = 006
N4.C1.D1.R1.S07: Offset Found: RdPtrOffsetDqs = 007
N6.C0.D1.R0.S05: Dq Delay estimate: 405
N0.C0.D0.R1.S10: Offset Found: RdPtrOffsetDqs = 007
N2.C2.D0.R0.S06: Offset Found: RdPtrOffsetDqs = 006
N4.C1.D1.R1.S08: Offset Found: RdPtrOffsetDqs = 006
N6.C0.D1.R0.S06: Dq Delay estimate: 409
N0.C0.D0.R1.S11: Offset Found: RdPtrOffsetDqs = 007
N2.C2.D0.R0.S07: Offset Found: RdPtrOffsetDqs = 007
N4.C1.D1.R1: Write Training Coarse, upper nibbles
N6.C0.D1.R0.S07: Dq Delay estimate: 426
N0.C0.D0.R1.S12: Offset Found: RdPtrOffsetDqs = 007
N2.C2.D0.R0.S08: Offset Found: RdPtrOffsetDqs = 006
N4.C1.D1.R1.S09: Dq Delay estimate: 467
N6.C0.D1.R0.S08: Dq Delay estimate: 396
N0.C0.D0.R1.S13: Offset Found: RdPtrOffsetDqs = 006
N2.C2.D0.R0: Write Training Coarse, upper nibbles
N4.C1.D1.R1.S10: Dq Delay estimate: 452
ACCM: 0F 0F0F0F0F 0F0F0F0F
N0.C0.D0.R1.S14: Offset Found: RdPtrOffsetDqs = 006
N2.C2.D0.R0.S09: Dq Delay estimate: 465
N4.C1.D1.R1.S11: Dq Delay estimate: 445
ACCM: 0F 0F0F0F0F 0F0F0F0F
N0.C0.D0.R1.S15: Offset Found: RdPtrOffsetDqs = 006
N2.C2.D0.R0.S10: Dq Delay estimate: 449
N4.C1.D1.R1.S12: Dq Delay estimate: 428
ACCM: 0F 0F0F0F0F 0F0F0F0F
N0.C0.D0.R1.S16: Offset Found: RdPtrOffsetDqs = 007
N2.C2.D0.R0.S11: Dq Delay estimate: 436
N4.C1.D1.R1.S13: Dq Delay estimate: 394
ACCM: 0F FF0F0FFF FFFFFF0F
N0.C0.D0.R1.S17: Offset Found: RdPtrOffsetDqs = 006
N2.C2.D0.R0.S12: Dq Delay estimate: 421
N4.C1.D1.R1.S14: Dq Delay estimate: 409
N6.C0.D1.R0: CheckMCTest: result = 0x13DFF
N0.C0.D1.R0: Write Training Coarse, lower nibbles / bytes
N2.C2.D0.R0.S13: Dq Delay estimate: 382
N4.C1.D1.R1.S15: Dq Delay estimate: 418
ACCM: 0F 0F0F0F0F 0F0F0F0F
N0.C0.D1.R0.S00: Dq Delay estimate: 474
N2.C2.D0.R0.S14: Dq Delay estimate: 406
N4.C1.D1.R1.S16: Dq Delay estimate: 437
ACCM: 0F 0F0F0F0F 0F0F0F0F
N0.C0.D1.R0.S01: Dq Delay estimate: 458
N2.C2.D0.R0.S15: Dq Delay estimate: 404
N4.C1.D1.R1.S17: Dq Delay estimate: 402
ACCM: 0F 0F0F0F0F 0F0F0F0F
N0.C0.D1.R0.S02: Dq Delay estimate: 444
N2.C2.D0.R0.S16: Dq Delay estimate: 428
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: 0F FF0F0FFF FFFFFF0F
N0.C0.D1.R0.S03: Dq Delay estimate: 428
N2.C2.D0.R0.S17: Dq Delay estimate: 399
ACCM: F0 F0F0F0F0 F0F0F0F0
N6.C0.D1.R0: CheckMCTest: result = 0x13DFF
N0.C0.D1.R0.S04: Dq Delay estimate: 394
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: 0F 0F0F0F0F 0F0F0F0F
N0.C0.D1.R0.S05: Dq Delay estimate: 412
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: 0F 0F0F0F0F 0F0F0F0F
N0.C0.D1.R0.S06: Dq Delay estimate: 412
ACCM: F0 F0F0F0F0 F0F0F0F0
N4.C1.D1.R1: CheckMCTest: result = 0x3FE00
ACCM: 00 0B000000 0B00000B
N0.C0.D1.R0.S07: Dq Delay estimate: 431
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: 00 FB0000F0 FBF0F00B
N0.C0.D1.R0.S08: Dq Delay estimate: 404
N2.C2.D0.R0: CheckMCTest: result = 0x3FE00
ACCM: F0 F0F0F0F0 F0F0F0F0
N6.C0.D1.R0: CheckMCTest: result = 0x13DFF
ACCM: 0F 0F0F0F0F 0F0F0F0F
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: 0F 0F0F0F0F 0F0F0F0F
ACCM: 0F 0F0F0F0F 0F0F0F0F
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: 0F 0F0F0F0F 0F0F0F0F
ACCM: 0F 0F0F0F0F 0F0F0F0F
ACCM: F0 F0F0F0F0 F0F0F0F0
N4.C1.D1.R1: CheckMCTest: result = 0x3FE00
ACCM: 00 0B000000 0F00000F
ACCM: 0F FF0F0F0F FFFFFF0F
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: 00 FB0000F0 FFF0F00F
N0.C0.D1.R0: CheckMCTest: result = 0x11DFF
N2.C2.D0.R0: CheckMCTest: result = 0x3FE00
ACCM: F0 F0F0F0F0 F0F0F0F0
N6.C0.D1.R0: CheckMCTest: result = 0x13DFF
ACCM: 0F 0F0F0F0F 0F0F0F0F
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: 00 00000000 00B00000
ACCM: 00 00000000 00000000
ACCM: 0F 0F0F0F0F 0F0F0F0F
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: 00 00000000 00B00000
ACCM: 00 00000000 00000000
ACCM: 0F 0F0F0F0F 0F0F0F0F
ACCM: 00 B0B00000 B0000000
N4.C1.D1.R1: CheckMCTest: result = 0x3FE00
ACCM: 00 00000000 00000000
ACCM: 0F FF0F0F0F FFFFFF0F
ACCM: 00 B0B00000 B0000000
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: 00 F00000F0 F0F0F000
N0.C0.D1.R0: CheckMCTest: result = 0x11DFF
N2.C2.D0.R0: CheckMCTest: result = 0x3FE00
ACCM: F0 F0F0F0F0 F0F0F0F0
N6.C0.D1.R0: CheckMCTest: result = 0x13C00
ACCM: 0F 0F0F0F0F 0F0F0F0F
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: 00 00000000 C0F00000
ACCM: 00 00000000 00000000
ACCM: 0F 0F0F0F0F 0F0F0F0F
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: 00 00000000 C0F00000
ACCM: 00 00000000 00000000
ACCM: 0B 0B000B00 0B000B0B
ACCM: 00 F0F00000 F0D00000
N4.C1.D1.R1: CheckMCTest: result = 0x3FE00
ACCM: 00 00000000 00000000
ACCM: 0B FB000B00 FBF0FB0B
ACCM: 00 F0F00000 F0D00000
N4.C1.D1.R1: CheckMCTest: passed
ACCM: 00 F00000F0 F0F0F000
N0.C0.D1.R0: CheckMCTest: result = 0x11DFF
N2.C2.D0.R0: CheckMCTest: result = 0x3FE00
N4.C1.D1.R1: CheckMCTest: passed
N6.C0.D1.R0: CheckMCTest: result = 0x13C00
ACCM: 0F 0F0F0F0F 0F0F0F0F
N2.C2.D0.R0: CheckMCTest: passed
N4.C1.D1.R1.S09: Offset Found: RdPtrOffsetDqs = 007
N6.C0.D1.R0.S00: Offset Found: RdPtrOffsetDqs = 007
ACCM: 0F 0F0F0F0F 0F0F0F0F
N2.C2.D0.R0: CheckMCTest: passed
N4.C1.D1.R1.S10: Offset Found: RdPtrOffsetDqs = 007
N6.C0.D1.R0.S01: Offset Found: RdPtrOffsetDqs = 007
ACCM: 0F 0F000F00 0B000F0F
N2.C2.D0.R0.S09: Offset Found: RdPtrOffsetDqs = 007
N4.C1.D1.R1.S11: Offset Found: RdPtrOffsetDqs = 007
N6.C0.D1.R0.S02: Offset Found: RdPtrOffsetDqs = 007
ACCM: 0F FF000F00 FBF0FF0F
N2.C2.D0.R0.S10: Offset Found: RdPtrOffsetDqs = 007
N4.C1.D1.R1.S12: Offset Found: RdPtrOffsetDqs = 007
N6.C0.D1.R0.S03: Offset Found: RdPtrOffsetDqs = 007
N0.C0.D1.R0: CheckMCTest: result = 0x11DFF
N2.C2.D0.R0.S11: Offset Found: RdPtrOffsetDqs = 007
N4.C1.D1.R1.S13: Offset Found: RdPtrOffsetDqs = 006
N6.C0.D1.R0.S04: Offset Found: RdPtrOffsetDqs = 006
ACCM: 00 00000000 00000000
N2.C2.D0.R0.S12: Offset Found: RdPtrOffsetDqs = 007
N4.C1.D1.R1.S14: Offset Found: RdPtrOffsetDqs = 006
N6.C0.D1.R0.S05: Offset Found: RdPtrOffsetDqs = 006
ACCM: 00 00000000 00000000
N2.C2.D0.R0.S13: Offset Found: RdPtrOffsetDqs = 006
N4.C1.D1.R1.S15: Offset Found: RdPtrOffsetDqs = 007
N6.C0.D1.R0.S06: Offset Found: RdPtrOffsetDqs = 006
ACCM: 00 00000000 00000000
N2.C2.D0.R0.S14: Offset Found: RdPtrOffsetDqs = 006
N4.C1.D1.R1.S16: Offset Found: RdPtrOffsetDqs = 007
N6.C0.D1.R0.S07: Offset Found: RdPtrOffsetDqs = 007
ACCM: 00 F0000000 F0F0F000
N2.C2.D0.R0.S15: Offset Found: RdPtrOffsetDqs = 006
N4.C1.D1.R1.S17: Offset Found: RdPtrOffsetDqs = 006
N6.C0.D1.R0.S08: Offset Found: RdPtrOffsetDqs = 006
N0.C0.D1.R0: CheckMCTest: result = 0x11C00
N2.C2.D0.R0.S16: Offset Found: RdPtrOffsetDqs = 007
N4.C1: Calculating Optimimum DQS Values
N6.C0.D1.R0: Write Training Coarse, upper nibbles
ACCM: 00 00000000 00000000
N2.C2.D0.R0.S17: Offset Found: RdPtrOffsetDqs = 006
N4.C1.D0.R0.S00: Total Delay in PI ticks: TxDQS = 1018, TxDQ = 981
N6.C0.D1.R0.S09: Dq Delay estimate: 469
ACCM: 00 00000000 00000000
N2.C2.D0.R1: Write Training Coarse, lower nibbles / bytes
N4.C1.D0.R0.S01: Total Delay in PI ticks: TxDQS = 1001, TxDQ = 964
N6.C0.D1.R0.S10: Dq Delay estimate: 452
ACCM: 00 00000000 00000000
N2.C2.D0.R1.S00: Dq Delay estimate: 458
N4.C1.D0.R0.S02: Total Delay in PI ticks: TxDQS = 994, TxDQ = 957
N6.C0.D1.R0.S11: Dq Delay estimate: 436
ACCM: 00 F0000000 F0F0F000
N2.C2.D0.R1.S01: Dq Delay estimate: 442
N4.C1.D0.R0.S03: Total Delay in PI ticks: TxDQS = 981, TxDQ = 944
N6.C0.D1.R0.S12: Dq Delay estimate: 424
N0.C0.D1.R0: CheckMCTest: result = 0x11C00
N2.C2.D0.R1.S02: Dq Delay estimate: 430
N4.C1.D0.R0.S04: Total Delay in PI ticks: TxDQS = 946, TxDQ = 908
N6.C0.D1.R0.S13: Dq Delay estimate: 389
N0.C0.D1.R0.S00: Offset Found: RdPtrOffsetDqs = 007
N2.C2.D0.R1.S03: Dq Delay estimate: 415
N4.C1.D0.R0.S05: Total Delay in PI ticks: TxDQS = 955, TxDQ = 919
N6.C0.D1.R0.S14: Dq Delay estimate: 407
N0.C0.D1.R0.S01: Offset Found: RdPtrOffsetDqs = 007
N2.C2.D0.R1.S04: Dq Delay estimate: 376
N4.C1.D0.R0.S06: Total Delay in PI ticks: TxDQS = 974, TxDQ = 935
N6.C0.D1.R0.S15: Dq Delay estimate: 409
N0.C0.D1.R0.S02: Offset Found: RdPtrOffsetDqs = 007
N2.C2.D0.R1.S05: Dq Delay estimate: 402
N4.C1.D0.R0.S07: Total Delay in PI ticks: TxDQS = 986, TxDQ = 946
N6.C0.D1.R0.S16: Dq Delay estimate: 426
N0.C0.D1.R0.S03: Offset Found: RdPtrOffsetDqs = 007
N2.C2.D0.R1.S06: Dq Delay estimate: 401
N4.C1.D0.R0.S08: Total Delay in PI ticks: TxDQS = 959, TxDQ = 921
N6.C0.D1.R0.S17: Dq Delay estimate: 397
N0.C0.D1.R0.S04: Offset Found: RdPtrOffsetDqs = 006
N2.C2.D0.R1.S07: Dq Delay estimate: 420
N4.C1.D0.R0.S09: Total Delay in PI ticks: TxDQS = 1020, TxDQ = 984
ACCM: F0 F0F0F0F0 F0F0F0F0
N0.C0.D1.R0.S05: Offset Found: RdPtrOffsetDqs = 007
N2.C2.D0.R1.S08: Dq Delay estimate: 391
N4.C1.D0.R0.S10: Total Delay in PI ticks: TxDQS = 1003, TxDQ = 967
ACCM: F0 F0F0F0F0 F0F0F0F0
N0.C0.D1.R0.S06: Offset Found: RdPtrOffsetDqs = 007
ACCM: 0F 0F0F0F0F 0F0F0F0F
N4.C1.D0.R0.S11: Total Delay in PI ticks: TxDQS = 996, TxDQ = 962
ACCM: F0 F0F0F0F0 F0F0F0F0
N0.C0.D1.R0.S07: Offset Found: RdPtrOffsetDqs = 007
ACCM: 0F 0F0F0F0F 0F0F0F0F
N4.C1.D0.R0.S12: Total Delay in PI ticks: TxDQS = 978, TxDQ = 942
ACCM: F0 F0F0F0F0 F0F0F0F0
N0.C0.D1.R0.S08: Offset Found: RdPtrOffsetDqs = 006
ACCM: 0F 0F0F0F0F 0F0F0F0F
N4.C1.D0.R0.S13: Total Delay in PI ticks: TxDQS = 946, TxDQ = 909
N6.C0.D1.R0: CheckMCTest: result = 0x3FE00
N0.C0.D1.R0: Write Training Coarse, upper nibbles
ACCM: 0F 0F0F0F0F 0F0F0F0F
N4.C1.D0.R0.S14: Total Delay in PI ticks: TxDQS = 957, TxDQ = 922
ACCM: F0 F0F0F0F0 F0F0F0F0
N0.C0.D1.R0.S09: Dq Delay estimate: 469
N2.C2.D0.R1: CheckMCTest: result = 0x1FF
N4.C1.D0.R0.S15: Total Delay in PI ticks: TxDQS = 971, TxDQ = 932
ACCM: F0 F0F0F0F0 F0F0F0F0
N0.C0.D1.R0.S10: Dq Delay estimate: 458
ACCM: 0F 0F0F0F0F 0F0F0F0F
N4.C1.D0.R0.S16: Total Delay in PI ticks: TxDQS = 986, TxDQ = 949
ACCM: F0 F0F0F0F0 F0F0F0F0
N0.C0.D1.R0.S11: Dq Delay estimate: 445
ACCM: 0F 0F0F0F0F 0F0F0F0F
N4.C1.D0.R0.S17: Total Delay in PI ticks: TxDQS = 961, TxDQ = 923
ACCM: F0 F0F0F0F0 F0F0F0F0
N0.C0.D1.R0.S12: Dq Delay estimate: 430
ACCM: 0F 0F0F0F0F 0F0F0F0F
N4.C1.D0.R1.S00: Total Delay in PI ticks: TxDQS = 1010, TxDQ = 973
N6.C0.D1.R0: CheckMCTest: result = 0x3FE00
N0.C0.D1.R0.S13: Dq Delay estimate: 394
ACCM: 0F 0F0F0F0F 0F0F0F0F
N4.C1.D0.R1.S01: Total Delay in PI ticks: TxDQS = 996, TxDQ = 959
ACCM: F0 F0F0F0F0 F0F0F0F0
N0.C0.D1.R0.S14: Dq Delay estimate: 411
N2.C2.D0.R1: CheckMCTest: result = 0x1FF
N4.C1.D0.R1.S02: Total Delay in PI ticks: TxDQS = 986, TxDQ = 949
ACCM: F0 F0F0F0F0 F0F0F0F0
N0.C0.D1.R0.S15: Dq Delay estimate: 417
ACCM: 0F 0F0F0F0F 0F0F0F0F
N4.C1.D0.R1.S03: Total Delay in PI ticks: TxDQS = 972, TxDQ = 935
ACCM: 00 B0B00000 0000B0B0
N0.C0.D1.R0.S16: Dq Delay estimate: 433
ACCM: 0F 0F0F0F0F 0F0F0F0F
N4.C1.D0.R1.S04: Total Delay in PI ticks: TxDQS = 938, TxDQ = 901
ACCM: 00 B0B00000 0000B0B0
N0.C0.D1.R0.S17: Dq Delay estimate: 404
ACCM: 00 0B000000 0B000000
N4.C1.D0.R1.S05: Total Delay in PI ticks: TxDQS = 950, TxDQ = 914
N6.C0.D1.R0: CheckMCTest: result = 0x3FE00
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: 00 0B000000 0B000000
N4.C1.D0.R1.S06: Total Delay in PI ticks: TxDQS = 962, TxDQ = 923
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: F0 F0F0F0F0 F0F0F0F0
N2.C2.D0.R1: CheckMCTest: result = 0x1FF
N4.C1.D0.R1.S07: Total Delay in PI ticks: TxDQS = 983, TxDQ = 944
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: 0F 0F0F0F0F 0F0F0F0F
N4.C1.D0.R1.S08: Total Delay in PI ticks: TxDQS = 953, TxDQ = 915
ACCM: 00 B0F00000 D000F0F0
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: 0F 0F0F0F0F 0F0F0F0F
N4.C1.D0.R1.S09: Total Delay in PI ticks: TxDQS = 1010, TxDQ = 973
ACCM: 00 B0F00000 D000F0F0
N0.C0.D1.R0: CheckMCTest: result = 0x3FE00
ACCM: 00 0F00000D 0F000000
N4.C1.D0.R1.S10: Total Delay in PI ticks: TxDQS = 997, TxDQ = 962
N6.C0.D1.R0: CheckMCTest: result = 0x3FE00
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: 00 0F00000D 0F000000
N4.C1.D0.R1.S11: Total Delay in PI ticks: TxDQS = 987, TxDQ = 952
N6.C0.D1.R0: CheckMCTest: passed
ACCM: F0 F0F0F0F0 F0F0F0F0
N2.C2.D0.R1: CheckMCTest: result = 0x1FF
N4.C1.D0.R1.S12: Total Delay in PI ticks: TxDQS = 974, TxDQ = 938
N6.C0.D1.R0: CheckMCTest: passed
ACCM: F0 F0F0F0F0 F0F0F0F0
N2.C2.D0.R1: CheckMCTest: passed
N4.C1.D0.R1.S13: Total Delay in PI ticks: TxDQS = 939, TxDQ = 902
N6.C0.D1.R0.S09: Offset Found: RdPtrOffsetDqs = 007
ACCM: F0 F0F0F0F0 F0F0F0F0
N2.C2.D0.R1: CheckMCTest: passed
N4.C1.D0.R1.S14: Total Delay in PI ticks: TxDQS = 952, TxDQ = 919
N6.C0.D1.R0.S10: Offset Found: RdPtrOffsetDqs = 007
N0.C0.D1.R0: CheckMCTest: result = 0x3FE00
N2.C2.D0.R1.S00: Offset Found: RdPtrOffsetDqs = 007
N4.C1.D0.R1.S15: Total Delay in PI ticks: TxDQS = 967, TxDQ = 929
N6.C0.D1.R0.S11: Offset Found: RdPtrOffsetDqs = 007
ACCM: F0 F0F0F0F0 F0F0F0F0
N2.C2.D0.R1.S01: Offset Found: RdPtrOffsetDqs = 007
N4.C1.D0.R1.S16: Total Delay in PI ticks: TxDQS = 983, TxDQ = 947
N6.C0.D1.R0.S12: Offset Found: RdPtrOffsetDqs = 007
ACCM: F0 F0F0F0F0 F0F0F0F0
N2.C2.D0.R1.S02: Offset Found: RdPtrOffsetDqs = 007
N4.C1.D0.R1.S17: Total Delay in PI ticks: TxDQS = 952, TxDQ = 914
N6.C0.D1.R0.S13: Offset Found: RdPtrOffsetDqs = 006
ACCM: B0 B0000000 B0B0B000
N2.C2.D0.R1.S03: Offset Found: RdPtrOffsetDqs = 007
N4.C1.D1.R0.S00: Total Delay in PI ticks: TxDQS = 1023, TxDQ = 984
N6.C0.D1.R0.S14: Offset Found: RdPtrOffsetDqs = 006
ACCM: B0 B0000000 B0B0B000
N2.C2.D0.R1.S04: Offset Found: RdPtrOffsetDqs = 006
N4.C1.D1.R0.S01: Total Delay in PI ticks: TxDQS = 1007, TxDQ = 968
N6.C0.D1.R0.S15: Offset Found: RdPtrOffsetDqs = 006
N0.C0.D1.R0: CheckMCTest: result = 0x3FE00
N2.C2.D0.R1.S05: Offset Found: RdPtrOffsetDqs = 006
N4.C1.D1.R0.S02: Total Delay in PI ticks: TxDQS = 996, TxDQ = 956
N6.C0.D1.R0.S16: Offset Found: RdPtrOffsetDqs = 007
ACCM: F0 F0F0F0F0 F0F0F0F0
N2.C2.D0.R1.S06: Offset Found: RdPtrOffsetDqs = 006
N4.C1.D1.R0.S03: Total Delay in PI ticks: TxDQS = 980, TxDQ = 940
N6.C0.D1.R0.S17: Offset Found: RdPtrOffsetDqs = 006
ACCM: F0 F0F0F0F0 F0F0F0F0
N2.C2.D0.R1.S07: Offset Found: RdPtrOffsetDqs = 007
N4.C1.D1.R0.S04: Total Delay in PI ticks: TxDQS = 946, TxDQ = 906
N6.C0.D1.R1: Write Training Coarse, lower nibbles / bytes
ACCM: F0 F0000000 F0F0F000
N2.C2.D0.R1.S08: Offset Found: RdPtrOffsetDqs = 006
N4.C1.D1.R0.S05: Total Delay in PI ticks: TxDQS = 959, TxDQ = 920
N6.C0.D1.R1.S00: Dq Delay estimate: 462
ACCM: F0 F0000000 F0F0F000
N2.C2.D0.R1: Write Training Coarse, upper nibbles
N4.C1.D1.R0.S06: Total Delay in PI ticks: TxDQS = 974, TxDQ = 933
N6.C0.D1.R1.S01: Dq Delay estimate: 446
N0.C0.D1.R0: CheckMCTest: result = 0x3FE00
N2.C2.D0.R1.S09: Dq Delay estimate: 455
N4.C1.D1.R0.S07: Total Delay in PI ticks: TxDQS = 990, TxDQ = 949
N6.C0.D1.R1.S02: Dq Delay estimate: 432
N0.C0.D1.R0: CheckMCTest: passed
N2.C2.D0.R1.S10: Dq Delay estimate: 441
N4.C1.D1.R0.S08: Total Delay in PI ticks: TxDQS = 959, TxDQ = 919
N6.C0.D1.R1.S03: Dq Delay estimate: 420
N0.C0.D1.R0: CheckMCTest: passed
N2.C2.D0.R1.S11: Dq Delay estimate: 431
N4.C1.D1.R0.S09: Total Delay in PI ticks: TxDQS = 1020, TxDQ = 982
N6.C0.D1.R1.S04: Dq Delay estimate: 385
N0.C0.D1.R0.S09: Offset Found: RdPtrOffsetDqs = 007
N2.C2.D0.R1.S12: Dq Delay estimate: 416
N4.C1.D1.R0.S10: Total Delay in PI ticks: TxDQS = 1004, TxDQ = 966
N6.C0.D1.R1.S05: Dq Delay estimate: 405
N0.C0.D1.R0.S10: Offset Found: RdPtrOffsetDqs = 007
N2.C2.D0.R1.S13: Dq Delay estimate: 376
N4.C1.D1.R0.S11: Total Delay in PI ticks: TxDQS = 995, TxDQ = 959
N6.C0.D1.R1.S06: Dq Delay estimate: 407
N0.C0.D1.R0.S11: Offset Found: RdPtrOffsetDqs = 007
N2.C2.D0.R1.S14: Dq Delay estimate: 402
N4.C1.D1.R0.S12: Total Delay in PI ticks: TxDQS = 980, TxDQ = 941
N6.C0.D1.R1.S07: Dq Delay estimate: 423
N0.C0.D1.R0.S12: Offset Found: RdPtrOffsetDqs = 007
N2.C2.D0.R1.S15: Dq Delay estimate: 399
N4.C1.D1.R0.S13: Total Delay in PI ticks: TxDQS = 946, TxDQ = 906
N6.C0.D1.R1.S08: Dq Delay estimate: 392
N0.C0.D1.R0.S13: Offset Found: RdPtrOffsetDqs = 006
N2.C2.D0.R1.S16: Dq Delay estimate: 422
N4.C1.D1.R0.S14: Total Delay in PI ticks: TxDQS = 959, TxDQ = 923
ACCM: 0F 0F0F0F0F 0F0F0F0F
N0.C0.D1.R0.S14: Offset Found: RdPtrOffsetDqs = 006
N2.C2.D0.R1.S17: Dq Delay estimate: 391
N4.C1.D1.R0.S15: Total Delay in PI ticks: TxDQS = 974, TxDQ = 934
ACCM: 0F 0F0F0F0F 0F0F0F0F
N0.C0.D1.R0.S15: Offset Found: RdPtrOffsetDqs = 007
ACCM: F0 F0F0F0F0 F0F0F0F0
N4.C1.D1.R0.S16: Total Delay in PI ticks: TxDQS = 993, TxDQ = 954
ACCM: 0F 0F0F0F0F 0F0F0F0F
N0.C0.D1.R0.S16: Offset Found: RdPtrOffsetDqs = 007
ACCM: F0 F0F0F0F0 F0F0F0F0
N4.C1.D1.R0.S17: Total Delay in PI ticks: TxDQS = 958, TxDQ = 918
ACCM: 0F 0F0F0F0F 0F0F0F0F
N0.C0.D1.R0.S17: Offset Found: RdPtrOffsetDqs = 006
ACCM: F0 F0F0F0F0 F0F0F0F0
N4.C1.D1.R1.S00: Total Delay in PI ticks: TxDQS = 1018, TxDQ = 979
N6.C0.D1.R1: CheckMCTest: result = 0x1FF
N0.C0.D1.R1: Write Training Coarse, lower nibbles / bytes
ACCM: F0 F0F0F0F0 F0F0F0F0
N4.C1.D1.R1.S01: Total Delay in PI ticks: TxDQS = 1003, TxDQ = 964
ACCM: 0F 0F0F0F0F 0F0F0F0F
N0.C0.D1.R1.S00: Dq Delay estimate: 469
N2.C2.D0.R1: CheckMCTest: result = 0x3FE00
N4.C1.D1.R1.S02: Total Delay in PI ticks: TxDQS = 993, TxDQ = 954
ACCM: 0F 0F0F0F0F 0F0F0F0F
N0.C0.D1.R1.S01: Dq Delay estimate: 453
ACCM: F0 F0F0F0F0 F0F0F0F0
N4.C1.D1.R1.S03: Total Delay in PI ticks: TxDQS = 979, TxDQ = 940
ACCM: 0F 0F0F0F0F 0F0F0F0F
N0.C0.D1.R1.S02: Dq Delay estimate: 443
ACCM: F0 F0F0F0F0 F0F0F0F0
N4.C1.D1.R1.S04: Total Delay in PI ticks: TxDQS = 946, TxDQ = 905
ACCM: 0F 0F0F0F0F 0F0F0F0F
N0.C0.D1.R1.S03: Dq Delay estimate: 426
ACCM: F0 F0F0F0F0 F0F0F0F0
N4.C1.D1.R1.S05: Total Delay in PI ticks: TxDQS = 959, TxDQ = 920
N6.C0.D1.R1: CheckMCTest: result = 0x1FF
N0.C0.D1.R1.S04: Dq Delay estimate: 391
ACCM: F0 F0F0F0F0 F0F0F0F0
N4.C1.D1.R1.S06: Total Delay in PI ticks: TxDQS = 969, TxDQ = 928
ACCM: 0F 0F0F0F0F 0F0F0F0F
N0.C0.D1.R1.S05: Dq Delay estimate: 411
N2.C2.D0.R1: CheckMCTest: result = 0x3FE00
N4.C1.D1.R1.S07: Total Delay in PI ticks: TxDQS = 989, TxDQ = 948
ACCM: 0F 0F0F0F0F 0F0F0F0F
N0.C0.D1.R1.S06: Dq Delay estimate: 411
ACCM: F0 F0F0F0F0 F0F0F0F0
N4.C1.D1.R1.S08: Total Delay in PI ticks: TxDQS = 955, TxDQ = 915
ACCM: 00 00000000 00000B0B
N0.C0.D1.R1.S07: Dq Delay estimate: 429
ACCM: F0 F0F0F0F0 F0F0F0F0
N4.C1.D1.R1.S09: Total Delay in PI ticks: TxDQS = 1017, TxDQ = 979
ACCM: 00 00000000 00000B0B
N0.C0.D1.R1.S08: Dq Delay estimate: 397
ACCM: 00 B0000000 00B00000
N4.C1.D1.R1.S10: Total Delay in PI ticks: TxDQS = 1002, TxDQ = 964
N6.C0.D1.R1: CheckMCTest: result = 0x1FF
ACCM: 0F 0F0F0F0F 0F0F0F0F
ACCM: 00 B0000000 00B00000
N4.C1.D1.R1.S11: Total Delay in PI ticks: TxDQS = 993, TxDQ = 957
ACCM: 0F 0F0F0F0F 0F0F0F0F
ACCM: 0F 0F0F0F0F 0F0F0F0F
N2.C2.D0.R1: CheckMCTest: result = 0x3FE00
N4.C1.D1.R1.S12: Total Delay in PI ticks: TxDQS = 979, TxDQ = 940
ACCM: 0F 0F0F0F0F 0F0F0F0F
ACCM: 0F 0F0F0F0F 0F0F0F0F
ACCM: F0 F0F0F0F0 F0F0F0F0
N4.C1.D1.R1.S13: Total Delay in PI ticks: TxDQS = 946, TxDQ = 906
ACCM: 00 00000000 00000B0F
ACCM: 0F 0F0F0F0F 0F0F0F0F
ACCM: F0 F0F0F0F0 F0F0F0F0
N4.C1.D1.R1.S14: Total Delay in PI ticks: TxDQS = 958, TxDQ = 921
ACCM: 00 00000000 00000B0F
N0.C0.D1.R1: CheckMCTest: result = 0x1FF
ACCM: 00 F0000000 00F00000
N4.C1.D1.R1.S15: Total Delay in PI ticks: TxDQS = 970, TxDQ = 930
N6.C0.D1.R1: CheckMCTest: result = 0x1FF
ACCM: 0F 0F0F0F0F 0F0F0F0F
ACCM: 00 F0000000 00F00000
N4.C1.D1.R1.S16: Total Delay in PI ticks: TxDQS = 987, TxDQ = 949
N6.C0.D1.R1: CheckMCTest: passed
ACCM: 0F 0F0F0F0F 0F0F0F0F
N2.C2.D0.R1: CheckMCTest: result = 0x3FE00
N4.C1.D1.R1.S17: Total Delay in PI ticks: TxDQS = 954, TxDQ = 914
N6.C0.D1.R1: CheckMCTest: passed
ACCM: 0F 0F0F0F0F 0F0F0F0F
N2.C2.D0.R1: CheckMCTest: passed
N4.C2.D0.R0: Write Training Coarse, lower nibbles / bytes
N6.C0.D1.R1.S00: Offset Found: RdPtrOffsetDqs = 007
ACCM: 0F 0F0F0F0F 0F0F0F0F
N2.C2.D0.R1: CheckMCTest: passed
N4.C2.D0.R0.S00: Dq Delay estimate: 464
N6.C0.D1.R1.S01: Offset Found: RdPtrOffsetDqs = 007
N0.C0.D1.R1: CheckMCTest: result = 0x1FF
N2.C2.D0.R1.S09: Offset Found: RdPtrOffsetDqs = 007
N4.C2.D0.R0.S01: Dq Delay estimate: 449
N6.C0.D1.R1.S02: Offset Found: RdPtrOffsetDqs = 007
ACCM: 0F 0F0F0F0F 0F0F0F0F
N2.C2.D0.R1.S10: Offset Found: RdPtrOffsetDqs = 007
N4.C2.D0.R0.S02: Dq Delay estimate: 441
N6.C0.D1.R1.S03: Offset Found: RdPtrOffsetDqs = 007
ACCM: 0F 0F0F0F0F 0F0F0F0F
N2.C2.D0.R1.S11: Offset Found: RdPtrOffsetDqs = 007
N4.C2.D0.R0.S03: Dq Delay estimate: 422
N6.C0.D1.R1.S04: Offset Found: RdPtrOffsetDqs = 006
ACCM: 00 0B0B0B00 0B000B0B
N2.C2.D0.R1.S12: Offset Found: RdPtrOffsetDqs = 007
N4.C2.D0.R0.S04: Dq Delay estimate: 379
N6.C0.D1.R1.S05: Offset Found: RdPtrOffsetDqs = 006
ACCM: 00 0B0B0B00 0B000B0B
N2.C2.D0.R1.S13: Offset Found: RdPtrOffsetDqs = 006
N4.C2.D0.R0.S05: Dq Delay estimate: 409
N6.C0.D1.R1.S06: Offset Found: RdPtrOffsetDqs = 006
N0.C0.D1.R1: CheckMCTest: result = 0x1FF
N2.C2.D0.R1.S14: Offset Found: RdPtrOffsetDqs = 006
N4.C2.D0.R0.S06: Dq Delay estimate: 409
N6.C0.D1.R1.S07: Offset Found: RdPtrOffsetDqs = 007
ACCM: 0F 0F0F0F0F 0F0F0F0F
N2.C2.D0.R1.S15: Offset Found: RdPtrOffsetDqs = 006
N4.C2.D0.R0.S07: Dq Delay estimate: 426
N6.C0.D1.R1.S08: Offset Found: RdPtrOffsetDqs = 006
ACCM: 0F 0F0F0F0F 0F0F0F0F
N2.C2.D0.R1.S16: Offset Found: RdPtrOffsetDqs = 007
N4.C2.D0.R0.S08: Dq Delay estimate: 401
N6.C0.D1.R1: Write Training Coarse, upper nibbles
ACCM: 00 0F0B0F00 0F000F0F
N2.C2.D0.R1.S17: Offset Found: RdPtrOffsetDqs = 006
ACCM: 9F 0FDF0F9F 0F0F0F0F
N6.C0.D1.R1.S09: Dq Delay estimate: 462
ACCM: 00 0F0B0F00 0F000F0F
N2.C2.D1.R0: Write Training Coarse, lower nibbles / bytes
ACCM: 9F 0FDF0F9F 0F0F0F0F
N6.C0.D1.R1.S10: Dq Delay estimate: 449
N0.C0.D1.R1: CheckMCTest: result = 0x1FF
N2.C2.D1.R0.S00: Dq Delay estimate: 463
ACCM: 9F FFFFFF9F FFFFFFFF
N6.C0.D1.R1.S11: Dq Delay estimate: 435
N0.C0.D1.R1: CheckMCTest: passed
N2.C2.D1.R0.S01: Dq Delay estimate: 451
ACCM: 9F FFFFFF9F FFFFFFFF
N6.C0.D1.R1.S12: Dq Delay estimate: 420
N0.C0.D1.R1: CheckMCTest: passed
N2.C2.D1.R0.S02: Dq Delay estimate: 436
N4.C2.D0.R0: CheckMCTest: result = 0x3FFFF
N6.C0.D1.R1.S13: Dq Delay estimate: 384
N0.C0.D1.R1.S00: Offset Found: RdPtrOffsetDqs = 007
N2.C2.D1.R0.S03: Dq Delay estimate: 427
ACCM: DF 0FFFDFDF 0F0F0F0F
N6.C0.D1.R1.S14: Dq Delay estimate: 403
N0.C0.D1.R1.S01: Offset Found: RdPtrOffsetDqs = 007
N2.C2.D1.R0.S04: Dq Delay estimate: 382
ACCM: DF 0FFFDFDF 0F0F0F0F
N6.C0.D1.R1.S15: Dq Delay estimate: 405
N0.C0.D1.R1.S02: Offset Found: RdPtrOffsetDqs = 007
N2.C2.D1.R0.S05: Dq Delay estimate: 412
ACCM: DF FFFFFFDF FFFFFFFF
N6.C0.D1.R1.S16: Dq Delay estimate: 419
N0.C0.D1.R1.S03: Offset Found: RdPtrOffsetDqs = 007
N2.C2.D1.R0.S06: Dq Delay estimate: 409
ACCM: DF FFFFFFDF FFFFFFFF
N6.C0.D1.R1.S17: Dq Delay estimate: 392
N0.C0.D1.R1.S04: Offset Found: RdPtrOffsetDqs = 006
N2.C2.D1.R0.S07: Dq Delay estimate: 428
N4.C2.D0.R0: CheckMCTest: result = 0x3FFFF
ACCM: F0 F0F0F0F0 F0F0F0F0
N0.C0.D1.R1.S05: Offset Found: RdPtrOffsetDqs = 006
N2.C2.D1.R0.S08: Dq Delay estimate: 397
ACCM: DF 0FDF0FDF 0F0F0F0F
ACCM: F0 F0F0F0F0 F0F0F0F0
N0.C0.D1.R1.S06: Offset Found: RdPtrOffsetDqs = 006
ACCM: 0F 0F0F0F0F 0F0F0F0F
ACCM: DF 0FDF0FDF 0F0F0F0F
ACCM: F0 F0F0F0F0 F0F0F0F0
N0.C0.D1.R1.S07: Offset Found: RdPtrOffsetDqs = 007
ACCM: 0F 0F0F0F0F 0F0F0F0F
ACCM: D0 FBFBFAD0 FBF0FBFB
ACCM: F0 F0F0F0F0 F0F0F0F0
N0.C0.D1.R1.S08: Offset Found: RdPtrOffsetDqs = 006
ACCM: 0F 0F0F0F0F 0F0F0F0F
ACCM: D0 FBFBFAD0 FBF0FBFB
N6.C0.D1.R1: CheckMCTest: result = 0x3FE00
N0.C0.D1.R1: Write Training Coarse, upper nibbles
ACCM: 0F FF0F0FFF FFFFFF0F
N4.C2.D0.R0: CheckMCTest: result = 0x3FFFF
ACCM: F0 F0F0F0F0 F0F0F0F0
N0.C0.D1.R1.S09: Dq Delay estimate: 467
N2.C2.D1.R0: CheckMCTest: result = 0x13DFF
ACCM: DF 0FDF0FDF 0F0F0F0F
ACCM: F0 F0F0F0F0 F0F0F0F0
N0.C0.D1.R1.S10: Dq Delay estimate: 454
ACCM: 0F 0F0F0F0F 0F0F0F0F
ACCM: DF 0FDF0FDF 0F0F0F0F
ACCM: F0 F0F0F0F0 F0F0F0F0
N0.C0.D1.R1.S11: Dq Delay estimate: 444
ACCM: 0F 0F0F0F0F 0F0F0F0F
ACCM: D0 FFFFFED0 FFF0FFFF
ACCM: F0 F0F0F0F0 F0F0F0F0
N0.C0.D1.R1.S12: Dq Delay estimate: 427
ACCM: 0F 0F0F0F0F 0F0F0F0F
ACCM: D0 FFFFFED0 FFF0FFFF
N6.C0.D1.R1: CheckMCTest: result = 0x3FE00
N0.C0.D1.R1.S13: Dq Delay estimate: 393
ACCM: 0F FF0F0FFF FFFFFF0F
N4.C2.D0.R0: CheckMCTest: result = 0x3FFFF
ACCM: F0 F0F0F0F0 F0F0F0F0
N0.C0.D1.R1.S14: Dq Delay estimate: 412
N2.C2.D1.R0: CheckMCTest: result = 0x13DFF
ACCM: D0 00D0D0D0 00000000
ACCM: F0 F0F0F0F0 F0F0F0F0
N0.C0.D1.R1.S15: Dq Delay estimate: 415
ACCM: 0F 0F0F0F0F 0F0F0F0F
ACCM: D0 00D0D0D0 00000000
ACCM: 00 B0000000 0000B0B0
N0.C0.D1.R1.S16: Dq Delay estimate: 430
ACCM: 0F 0F0F0F0F 0F0F0F0F
ACCM: D0 F0F0F0D0 F0F0F0F0
ACCM: 00 B0000000 0000B0B0
N0.C0.D1.R1.S17: Dq Delay estimate: 398
ACCM: 00 0B0B0B0B 0000000B
ACCM: D0 F0F0F0D0 F0F0F0F0
N6.C0.D1.R1: CheckMCTest: result = 0x3FE00
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: 00 FB0B0BFB F0F0F00B
N4.C2.D0.R0: CheckMCTest: result = 0x3FE00
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: F0 F0F0F0F0 F0F0F0F0
N2.C2.D1.R0: CheckMCTest: result = 0x13DFF
ACCM: D0 00D0D0D0 00000000
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: 0F 0F0F0F0F 0F0F0F0F
ACCM: D0 00D0D0D0 00000000
ACCM: 00 F0000000 0000F0B0
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: 0F 0F0F0F0F 0F0F0F0F
ACCM: D0 F0F0F0D0 F0F0F0F0
ACCM: 00 F0000000 0000F0B0
N0.C0.D1.R1: CheckMCTest: result = 0x3FE00
ACCM: 00 0B0F0F0F 0C00000F
ACCM: D0 F0F0F0D0 F0F0F0F0
N6.C0.D1.R1: CheckMCTest: result = 0x3FE00
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: 00 FB0F0FFF FCF0F00F
N4.C2.D0.R0: CheckMCTest: result = 0x3FE00
N6.C0.D1.R1: CheckMCTest: passed
ACCM: F0 F0F0F0F0 F0F0F0F0
N2.C2.D1.R0: CheckMCTest: result = 0x13DFF
N4.C2.D0.R0.S00: Offset Found: RdPtrOffsetDqs = 007
N6.C0.D1.R1: CheckMCTest: passed
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: 00 00000000 00000000
N4.C2.D0.R0.S01: Offset Found: RdPtrOffsetDqs = 007
N6.C0.D1.R1.S09: Offset Found: RdPtrOffsetDqs = 007
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: 00 00000000 00000000
N4.C2.D0.R0.S02: Offset Found: RdPtrOffsetDqs = 007
N6.C0.D1.R1.S10: Offset Found: RdPtrOffsetDqs = 007
N0.C0.D1.R1: CheckMCTest: result = 0x3FE00
ACCM: 00 00000000 00000000
N4.C2.D0.R0.S03: Offset Found: RdPtrOffsetDqs = 007
N6.C0.D1.R1.S11: Offset Found: RdPtrOffsetDqs = 007
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: 00 F00000F0 F0F0F000
N4.C2.D0.R0.S04: Offset Found: RdPtrOffsetDqs = 006
N6.C0.D1.R1.S12: Offset Found: RdPtrOffsetDqs = 007
ACCM: F0 F0F0F0F0 F0F0F0F0
N2.C2.D1.R0: CheckMCTest: result = 0x13C00
N4.C2.D0.R0.S05: Offset Found: RdPtrOffsetDqs = 006
N6.C0.D1.R1.S13: Offset Found: RdPtrOffsetDqs = 006
ACCM: 00 0000B0B0 00B000B0
ACCM: 00 00000000 00000000
N4.C2.D0.R0.S06: Offset Found: RdPtrOffsetDqs = 006
N6.C0.D1.R1.S14: Offset Found: RdPtrOffsetDqs = 006
ACCM: 00 0000B0B0 00B000B0
ACCM: 00 00000000 00000000
N4.C2.D0.R0.S07: Offset Found: RdPtrOffsetDqs = 007
N6.C0.D1.R1.S15: Offset Found: RdPtrOffsetDqs = 006
N0.C0.D1.R1: CheckMCTest: result = 0x3FE00
ACCM: 00 00000000 00000000
N4.C2.D0.R0.S08: Offset Found: RdPtrOffsetDqs = 006
N6.C0.D1.R1.S16: Offset Found: RdPtrOffsetDqs = 007
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: 00 F00000F0 F0F0F000
N4.C2.D0.R0: Write Training Coarse, upper nibbles
N6.C0.D1.R1.S17: Offset Found: RdPtrOffsetDqs = 006
ACCM: F0 F0F0F0F0 F0F0F0F0
N2.C2.D1.R0: CheckMCTest: result = 0x13C00
N4.C2.D0.R0.S09: Dq Delay estimate: 467
N6.C0: Calculating Optimimum DQS Values
ACCM: 00 0000F0B0 00F000F0
N2.C2.D1.R0.S00: Offset Found: RdPtrOffsetDqs = 007
N4.C2.D0.R0.S10: Dq Delay estimate: 450
N6.C0.D0.R0.S00: Total Delay in PI ticks: TxDQS = 1015, TxDQ = 984
ACCM: 00 0000F0B0 00F000F0
N2.C2.D1.R0.S01: Offset Found: RdPtrOffsetDqs = 007
N4.C2.D0.R0.S11: Dq Delay estimate: 443
N6.C0.D0.R0.S01: Total Delay in PI ticks: TxDQS = 993, TxDQ = 960
N0.C0.D1.R1: CheckMCTest: result = 0x3FE00
N2.C2.D1.R0.S02: Offset Found: RdPtrOffsetDqs = 007
N4.C2.D0.R0.S12: Dq Delay estimate: 422
N6.C0.D0.R0.S02: Total Delay in PI ticks: TxDQS = 983, TxDQ = 950
N0.C0.D1.R1: CheckMCTest: passed
N2.C2.D1.R0.S03: Offset Found: RdPtrOffsetDqs = 007
N4.C2.D0.R0.S13: Dq Delay estimate: 385
N6.C0.D0.R0.S03: Total Delay in PI ticks: TxDQS = 965, TxDQ = 932
N0.C0.D1.R1: CheckMCTest: passed
N2.C2.D1.R0.S04: Offset Found: RdPtrOffsetDqs = 006
N4.C2.D0.R0.S14: Dq Delay estimate: 407
N6.C0.D0.R0.S04: Total Delay in PI ticks: TxDQS = 933, TxDQ = 900
N0.C0.D1.R1.S09: Offset Found: RdPtrOffsetDqs = 007
N2.C2.D1.R0.S05: Offset Found: RdPtrOffsetDqs = 007
N4.C2.D0.R0.S15: Dq Delay estimate: 409
N6.C0.D0.R0.S05: Total Delay in PI ticks: TxDQS = 951, TxDQ = 917
N0.C0.D1.R1.S10: Offset Found: RdPtrOffsetDqs = 007
N2.C2.D1.R0.S06: Offset Found: RdPtrOffsetDqs = 006
N4.C2.D0.R0.S16: Dq Delay estimate: 429
N6.C0.D0.R0.S06: Total Delay in PI ticks: TxDQS = 955, TxDQ = 922
N0.C0.D1.R1.S11: Offset Found: RdPtrOffsetDqs = 007
N2.C2.D1.R0.S07: Offset Found: RdPtrOffsetDqs = 007
N4.C2.D0.R0.S17: Dq Delay estimate: 399
N6.C0.D0.R0.S07: Total Delay in PI ticks: TxDQS = 970, TxDQ = 936
N0.C0.D1.R1.S12: Offset Found: RdPtrOffsetDqs = 007
N2.C2.D1.R0.S08: Offset Found: RdPtrOffsetDqs = 006
ACCM: F0 F0F0F0F0 F0F0F0F0
N6.C0.D0.R0.S08: Total Delay in PI ticks: TxDQS = 946, TxDQ = 912
N0.C0.D1.R1.S13: Offset Found: RdPtrOffsetDqs = 006
N2.C2.D1.R0: Write Training Coarse, upper nibbles
ACCM: F0 F0F0F0F0 F0F0F0F0
N6.C0.D0.R0.S09: Total Delay in PI ticks: TxDQS = 1015, TxDQ = 982
N0.C0.D1.R1.S14: Offset Found: RdPtrOffsetDqs = 006
N2.C2.D1.R0.S09: Dq Delay estimate: 461
ACCM: F0 F0F0F0F0 F0F0F0F0
N6.C0.D0.R0.S10: Total Delay in PI ticks: TxDQS = 992, TxDQ = 962
N0.C0.D1.R1.S15: Offset Found: RdPtrOffsetDqs = 007
N2.C2.D1.R0.S10: Dq Delay estimate: 451
ACCM: F0 F0F0F0F0 F0F0F0F0
N6.C0.D0.R0.S11: Total Delay in PI ticks: TxDQS = 982, TxDQ = 948
N0.C0.D1.R1.S16: Offset Found: RdPtrOffsetDqs = 007
N2.C2.D1.R0.S11: Dq Delay estimate: 437
N4.C2.D0.R0: CheckMCTest: result = 0x3FE00
N6.C0.D0.R0.S12: Total Delay in PI ticks: TxDQS = 967, TxDQ = 934
N0.C0.D1.R1.S17: Offset Found: RdPtrOffsetDqs = 006
N2.C2.D1.R0.S12: Dq Delay estimate: 427
ACCM: F0 F0F0F0F0 F0F0F0F0
N6.C0.D0.R0.S13: Total Delay in PI ticks: TxDQS = 933, TxDQ = 900
N0.C0: Calculating Optimimum DQS Values
N2.C2.D1.R0.S13: Dq Delay estimate: 385
ACCM: F0 F0F0F0F0 F0F0F0F0
N6.C0.D0.R0.S14: Total Delay in PI ticks: TxDQS = 952, TxDQ = 918
N0.C0.D0.R0.S00: Total Delay in PI ticks: TxDQS = 1015, TxDQ = 982
N2.C2.D1.R0.S14: Dq Delay estimate: 410
ACCM: F0 F0F0F0F0 F0F0F0F0
N6.C0.D0.R0.S15: Total Delay in PI ticks: TxDQS = 953, TxDQ = 918
N0.C0.D0.R0.S01: Total Delay in PI ticks: TxDQS = 998, TxDQ = 965
N2.C2.D1.R0.S15: Dq Delay estimate: 406
ACCM: F0 F0F0F0F0 F0F0F0F0
N6.C0.D0.R0.S16: Total Delay in PI ticks: TxDQS = 970, TxDQ = 935
N0.C0.D0.R0.S02: Total Delay in PI ticks: TxDQS = 988, TxDQ = 955
N2.C2.D1.R0.S16: Dq Delay estimate: 430
N4.C2.D0.R0: CheckMCTest: result = 0x3FE00
N6.C0.D0.R0.S17: Total Delay in PI ticks: TxDQS = 948, TxDQ = 913
N0.C0.D0.R0.S03: Total Delay in PI ticks: TxDQS = 968, TxDQ = 935
N2.C2.D1.R0.S17: Dq Delay estimate: 396
ACCM: F0 F0F0F0F0 F0F0F0F0
N6.C0.D0.R1.S00: Total Delay in PI ticks: TxDQS = 1008, TxDQ = 976
N0.C0.D0.R0.S04: Total Delay in PI ticks: TxDQS = 938, TxDQ = 904
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: F0 F0F0F0F0 F0F0F0F0
N6.C0.D0.R1.S01: Total Delay in PI ticks: TxDQS = 986, TxDQ = 953
N0.C0.D0.R0.S05: Total Delay in PI ticks: TxDQS = 954, TxDQ = 920
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: 00 B00000B0 B0B0B0B0
N6.C0.D0.R1.S02: Total Delay in PI ticks: TxDQS = 976, TxDQ = 942
N0.C0.D0.R0.S06: Total Delay in PI ticks: TxDQS = 957, TxDQ = 924
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: 00 B00000B0 B0B0B0B0
N6.C0.D0.R1.S03: Total Delay in PI ticks: TxDQS = 959, TxDQ = 926
N0.C0.D0.R0.S07: Total Delay in PI ticks: TxDQS = 974, TxDQ = 940
ACCM: F0 F0F0F0F0 F0F0F0F0
N4.C2.D0.R0: CheckMCTest: result = 0x3FE00
N6.C0.D0.R1.S04: Total Delay in PI ticks: TxDQS = 926, TxDQ = 892
N0.C0.D0.R0.S08: Total Delay in PI ticks: TxDQS = 948, TxDQ = 915
N2.C2.D1.R0: CheckMCTest: result = 0x3FE00
ACCM: F0 F0F0F0F0 F0F0F0F0
N6.C0.D0.R1.S05: Total Delay in PI ticks: TxDQS = 945, TxDQ = 911
N0.C0.D0.R0.S09: Total Delay in PI ticks: TxDQS = 1017, TxDQ = 983
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: F0 F0F0F0F0 F0F0F0F0
N6.C0.D0.R1.S06: Total Delay in PI ticks: TxDQS = 947, TxDQ = 914
N0.C0.D0.R0.S10: Total Delay in PI ticks: TxDQS = 997, TxDQ = 964
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: 00 F0D000F0 F0F0F0F0
N6.C0.D0.R1.S07: Total Delay in PI ticks: TxDQS = 964, TxDQ = 931
N0.C0.D0.R0.S11: Total Delay in PI ticks: TxDQS = 988, TxDQ = 955
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: 00 F0D000F0 F0F0F0F0
N6.C0.D0.R1.S08: Total Delay in PI ticks: TxDQS = 937, TxDQ = 903
N0.C0.D0.R0.S12: Total Delay in PI ticks: TxDQS = 971, TxDQ = 937
ACCM: F0 F0F0F0F0 F0F0F0F0
N4.C2.D0.R0: CheckMCTest: result = 0x3FE00
N6.C0.D0.R1.S09: Total Delay in PI ticks: TxDQS = 1005, TxDQ = 971
N0.C0.D0.R0.S13: Total Delay in PI ticks: TxDQS = 938, TxDQ = 904
N2.C2.D1.R0: CheckMCTest: result = 0x3FE00
N4.C2.D0.R0: CheckMCTest: passed
N6.C0.D0.R1.S10: Total Delay in PI ticks: TxDQS = 988, TxDQ = 957
N0.C0.D0.R0.S14: Total Delay in PI ticks: TxDQS = 952, TxDQ = 919
ACCM: F0 F0F0F0F0 F0F0F0F0
N4.C2.D0.R0: CheckMCTest: passed
N6.C0.D0.R1.S11: Total Delay in PI ticks: TxDQS = 975, TxDQ = 943
N0.C0.D0.R0.S15: Total Delay in PI ticks: TxDQS = 957, TxDQ = 926
ACCM: F0 F0F0F0F0 F0F0F0F0
N4.C2.D0.R0.S09: Offset Found: RdPtrOffsetDqs = 007
N6.C0.D0.R1.S12: Total Delay in PI ticks: TxDQS = 963, TxDQ = 929
N0.C0.D0.R0.S16: Total Delay in PI ticks: TxDQS = 975, TxDQ = 942
ACCM: 00 00B00000 00000000
N4.C2.D0.R0.S10: Offset Found: RdPtrOffsetDqs = 007
N6.C0.D0.R1.S13: Total Delay in PI ticks: TxDQS = 927, TxDQ = 894
N0.C0.D0.R0.S17: Total Delay in PI ticks: TxDQS = 946, TxDQ = 912
ACCM: 00 00B00000 00000000
N4.C2.D0.R0.S11: Offset Found: RdPtrOffsetDqs = 007
N6.C0.D0.R1.S14: Total Delay in PI ticks: TxDQS = 944, TxDQ = 910
N0.C0.D0.R1.S00: Total Delay in PI ticks: TxDQS = 1010, TxDQ = 977
N2.C2.D1.R0: CheckMCTest: result = 0x3FE00
N4.C2.D0.R0.S12: Offset Found: RdPtrOffsetDqs = 007
N6.C0.D0.R1.S15: Total Delay in PI ticks: TxDQS = 947, TxDQ = 913
N0.C0.D0.R1.S01: Total Delay in PI ticks: TxDQS = 992, TxDQ = 959
ACCM: F0 F0F0F0F0 F0F0F0F0
N4.C2.D0.R0.S13: Offset Found: RdPtrOffsetDqs = 006
N6.C0.D0.R1.S16: Total Delay in PI ticks: TxDQS = 965, TxDQ = 930
N0.C0.D0.R1.S02: Total Delay in PI ticks: TxDQS = 980, TxDQ = 947
ACCM: F0 F0F0F0F0 F0F0F0F0
N4.C2.D0.R0.S14: Offset Found: RdPtrOffsetDqs = 006
N6.C0.D0.R1.S17: Total Delay in PI ticks: TxDQS = 937, TxDQ = 902
N0.C0.D0.R1.S03: Total Delay in PI ticks: TxDQS = 962, TxDQ = 929
ACCM: 00 00F00000 00000000
N4.C2.D0.R0.S15: Offset Found: RdPtrOffsetDqs = 006
N6.C0.D1.R0.S00: Total Delay in PI ticks: TxDQS = 1014, TxDQ = 979
N0.C0.D0.R1.S04: Total Delay in PI ticks: TxDQS = 931, TxDQ = 897
ACCM: 00 00F00000 00000000
N4.C2.D0.R0.S16: Offset Found: RdPtrOffsetDqs = 007
N6.C0.D1.R0.S01: Total Delay in PI ticks: TxDQS = 997, TxDQ = 962
N0.C0.D0.R1.S05: Total Delay in PI ticks: TxDQS = 947, TxDQ = 912
N2.C2.D1.R0: CheckMCTest: result = 0x3FE00
N4.C2.D0.R0.S17: Offset Found: RdPtrOffsetDqs = 006
N6.C0.D1.R0.S02: Total Delay in PI ticks: TxDQS = 985, TxDQ = 949
N0.C0.D0.R1.S06: Total Delay in PI ticks: TxDQS = 949, TxDQ = 915
N2.C2.D1.R0: CheckMCTest: passed
N4.C2.D0.R1: Write Training Coarse, lower nibbles / bytes
N6.C0.D1.R0.S03: Total Delay in PI ticks: TxDQS = 972, TxDQ = 938
N0.C0.D0.R1.S07: Total Delay in PI ticks: TxDQS = 968, TxDQ = 934
N2.C2.D1.R0: CheckMCTest: passed
N4.C2.D0.R1.S00: Dq Delay estimate: 459
N6.C0.D1.R0.S04: Total Delay in PI ticks: TxDQS = 935, TxDQ = 900
N0.C0.D0.R1.S08: Total Delay in PI ticks: TxDQS = 939, TxDQ = 906
N2.C2.D1.R0.S09: Offset Found: RdPtrOffsetDqs = 007
N4.C2.D0.R1.S01: Dq Delay estimate: 441
N6.C0.D1.R0.S05: Total Delay in PI ticks: TxDQS = 953, TxDQ = 917
N0.C0.D0.R1.S09: Total Delay in PI ticks: TxDQS = 1008, TxDQ = 975
N2.C2.D1.R0.S10: Offset Found: RdPtrOffsetDqs = 007
N4.C2.D0.R1.S02: Dq Delay estimate: 433
N6.C0.D1.R0.S06: Total Delay in PI ticks: TxDQS = 956, TxDQ = 921
N0.C0.D0.R1.S10: Total Delay in PI ticks: TxDQS = 993, TxDQ = 959
N2.C2.D1.R0.S11: Offset Found: RdPtrOffsetDqs = 007
N4.C2.D0.R1.S03: Dq Delay estimate: 418
N6.C0.D1.R0.S07: Total Delay in PI ticks: TxDQS = 974, TxDQ = 938
N0.C0.D0.R1.S11: Total Delay in PI ticks: TxDQS = 980, TxDQ = 947
N2.C2.D1.R0.S12: Offset Found: RdPtrOffsetDqs = 007
N4.C2.D0.R1.S04: Dq Delay estimate: 375
N6.C0.D1.R0.S08: Total Delay in PI ticks: TxDQS = 944, TxDQ = 908
N0.C0.D0.R1.S12: Total Delay in PI ticks: TxDQS = 966, TxDQ = 933
N2.C2.D1.R0.S13: Offset Found: RdPtrOffsetDqs = 006
N4.C2.D0.R1.S05: Dq Delay estimate: 402
N6.C0.D1.R0.S09: Total Delay in PI ticks: TxDQS = 1016, TxDQ = 981
N0.C0.D0.R1.S13: Total Delay in PI ticks: TxDQS = 933, TxDQ = 899
N2.C2.D1.R0.S14: Offset Found: RdPtrOffsetDqs = 006
N4.C2.D0.R1.S06: Dq Delay estimate: 398
N6.C0.D1.R0.S10: Total Delay in PI ticks: TxDQS = 998, TxDQ = 964
N0.C0.D0.R1.S14: Total Delay in PI ticks: TxDQS = 949, TxDQ = 916
N2.C2.D1.R0.S15: Offset Found: RdPtrOffsetDqs = 006
N4.C2.D0.R1.S07: Dq Delay estimate: 422
N6.C0.D1.R0.S11: Total Delay in PI ticks: TxDQS = 983, TxDQ = 948
N0.C0.D0.R1.S15: Total Delay in PI ticks: TxDQS = 952, TxDQ = 919
N2.C2.D1.R0.S16: Offset Found: RdPtrOffsetDqs = 007
N4.C2.D0.R1.S08: Dq Delay estimate: 392
N6.C0.D1.R0.S12: Total Delay in PI ticks: TxDQS = 971, TxDQ = 936
N0.C0.D0.R1.S16: Total Delay in PI ticks: TxDQS = 968, TxDQ = 936
N2.C2.D1.R0.S17: Offset Found: RdPtrOffsetDqs = 006
ACCM: 0F 0F0F0F0F 0F0F0F0F
N6.C0.D1.R0.S13: Total Delay in PI ticks: TxDQS = 936, TxDQ = 901
N0.C0.D0.R1.S17: Total Delay in PI ticks: TxDQS = 939, TxDQ = 905
N2.C2.D1.R1: Write Training Coarse, lower nibbles / bytes
ACCM: 0F 0F0F0F0F 0F0F0F0F
N6.C0.D1.R0.S14: Total Delay in PI ticks: TxDQS = 955, TxDQ = 919
N0.C0.D1.R0.S00: Total Delay in PI ticks: TxDQS = 1021, TxDQ = 986
N2.C2.D1.R1.S00: Dq Delay estimate: 462
ACCM: 0F 0F0F0F0F 0F0F0F0F
N6.C0.D1.R0.S15: Total Delay in PI ticks: TxDQS = 957, TxDQ = 921
N0.C0.D1.R0.S01: Total Delay in PI ticks: TxDQS = 1005, TxDQ = 970
N2.C2.D1.R1.S01: Dq Delay estimate: 446
ACCM: 0F 0F0F0F0F 0F0F0F0F
N6.C0.D1.R0.S16: Total Delay in PI ticks: TxDQS = 975, TxDQ = 938
N0.C0.D1.R0.S02: Total Delay in PI ticks: TxDQS = 992, TxDQ = 956
N2.C2.D1.R1.S02: Dq Delay estimate: 432
N4.C2.D0.R1: CheckMCTest: result = 0x1FF
N6.C0.D1.R0.S17: Total Delay in PI ticks: TxDQS = 945, TxDQ = 909
N0.C0.D1.R0.S03: Total Delay in PI ticks: TxDQS = 975, TxDQ = 940
N2.C2.D1.R1.S03: Dq Delay estimate: 422
ACCM: 0F 0F0F0F0F 0F0F0F0F
N6.C0.D1.R1.S00: Total Delay in PI ticks: TxDQS = 1009, TxDQ = 974
N0.C0.D1.R0.S04: Total Delay in PI ticks: TxDQS = 941, TxDQ = 906
N2.C2.D1.R1.S04: Dq Delay estimate: 377
ACCM: 0F 0F0F0F0F 0F0F0F0F
N6.C0.D1.R1.S01: Total Delay in PI ticks: TxDQS = 993, TxDQ = 958
N0.C0.D1.R0.S05: Total Delay in PI ticks: TxDQS = 960, TxDQ = 924
N2.C2.D1.R1.S05: Dq Delay estimate: 410
ACCM: 0F 0F0F0F0F 0F0F0F0F
N6.C0.D1.R1.S02: Total Delay in PI ticks: TxDQS = 980, TxDQ = 944
N0.C0.D1.R0.S06: Total Delay in PI ticks: TxDQS = 960, TxDQ = 924
N2.C2.D1.R1.S06: Dq Delay estimate: 403
ACCM: 0F 0F0F0F0F 0F0F0F0F
N6.C0.D1.R1.S03: Total Delay in PI ticks: TxDQS = 967, TxDQ = 932
N0.C0.D1.R0.S07: Total Delay in PI ticks: TxDQS = 978, TxDQ = 943
N2.C2.D1.R1.S07: Dq Delay estimate: 426
N4.C2.D0.R1: CheckMCTest: result = 0x1FF
N6.C0.D1.R1.S04: Total Delay in PI ticks: TxDQS = 932, TxDQ = 897
N0.C0.D1.R0.S08: Total Delay in PI ticks: TxDQS = 950, TxDQ = 916
N2.C2.D1.R1.S08: Dq Delay estimate: 393
ACCM: 0F 0F0F0F0F 0F0F0F0F
N6.C0.D1.R1.S05: Total Delay in PI ticks: TxDQS = 952, TxDQ = 917
N0.C0.D1.R0.S09: Total Delay in PI ticks: TxDQS = 1017, TxDQ = 981
ACCM: 0F 0F0F0F0F 0F0F0F0F
ACCM: 0F 0F0F0F0F 0F0F0F0F
N6.C0.D1.R1.S06: Total Delay in PI ticks: TxDQS = 954, TxDQ = 919
N0.C0.D1.R0.S10: Total Delay in PI ticks: TxDQS = 1005, TxDQ = 970
ACCM: 0F 0F0F0F0F 0F0F0F0F
ACCM: 00 0B0B0B00 00000000
N6.C0.D1.R1.S07: Total Delay in PI ticks: TxDQS = 971, TxDQ = 935
N0.C0.D1.R0.S11: Total Delay in PI ticks: TxDQS = 991, TxDQ = 957
ACCM: 0F 0F0F0F0F 0F0F0F0F
ACCM: 00 0B0B0B00 00000000
N6.C0.D1.R1.S08: Total Delay in PI ticks: TxDQS = 940, TxDQ = 904
N0.C0.D1.R0.S12: Total Delay in PI ticks: TxDQS = 977, TxDQ = 942
ACCM: 0F 0F0F0F0F 0F0F0F0F
N4.C2.D0.R1: CheckMCTest: result = 0x1FF
N6.C0.D1.R1.S09: Total Delay in PI ticks: TxDQS = 1009, TxDQ = 974
N0.C0.D1.R0.S13: Total Delay in PI ticks: TxDQS = 942, TxDQ = 906
N2.C2.D1.R1: CheckMCTest: result = 0x1FF
ACCM: 0F 0F0F0F0F 0F0F0F0F
N6.C0.D1.R1.S10: Total Delay in PI ticks: TxDQS = 995, TxDQ = 961
N0.C0.D1.R0.S14: Total Delay in PI ticks: TxDQS = 958, TxDQ = 923
ACCM: 0F 0F0F0F0F 0F0F0F0F
ACCM: 0F 0F0F0F0F 0F0F0F0F
N6.C0.D1.R1.S11: Total Delay in PI ticks: TxDQS = 982, TxDQ = 947
N0.C0.D1.R0.S15: Total Delay in PI ticks: TxDQS = 962, TxDQ = 929
ACCM: 0F 0F0F0F0F 0F0F0F0F
ACCM: 00 0F0F0F00 00000000
N6.C0.D1.R1.S12: Total Delay in PI ticks: TxDQS = 967, TxDQ = 932
N0.C0.D1.R0.S16: Total Delay in PI ticks: TxDQS = 979, TxDQ = 945
ACCM: 0F 0F0F0F0F 0F0F0F0F
ACCM: 00 0F0F0F00 00000000
N6.C0.D1.R1.S13: Total Delay in PI ticks: TxDQS = 932, TxDQ = 896
N0.C0.D1.R0.S17: Total Delay in PI ticks: TxDQS = 951, TxDQ = 916
ACCM: 0F 0F0F0F0F 0F0F0F0F
N4.C2.D0.R1: CheckMCTest: result = 0x1FF
N6.C0.D1.R1.S14: Total Delay in PI ticks: TxDQS = 951, TxDQ = 915
N0.C0.D1.R1.S00: Total Delay in PI ticks: TxDQS = 1016, TxDQ = 981
N2.C2.D1.R1: CheckMCTest: result = 0x1FF
N4.C2.D0.R1: CheckMCTest: passed
N6.C0.D1.R1.S15: Total Delay in PI ticks: TxDQS = 954, TxDQ = 917
N0.C0.D1.R1.S01: Total Delay in PI ticks: TxDQS = 1000, TxDQ = 965
ACCM: 0F 0F0F0F0F 0F0F0F0F
N4.C2.D0.R1: CheckMCTest: passed
N6.C0.D1.R1.S16: Total Delay in PI ticks: TxDQS = 968, TxDQ = 931
N0.C0.D1.R1.S02: Total Delay in PI ticks: TxDQS = 990, TxDQ = 955
ACCM: 0F 0F0F0F0F 0F0F0F0F
N4.C2.D0.R1.S00: Offset Found: RdPtrOffsetDqs = 007
N6.C0.D1.R1.S17: Total Delay in PI ticks: TxDQS = 940, TxDQ = 904
N0.C0.D1.R1.S03: Total Delay in PI ticks: TxDQS = 973, TxDQ = 938
ACCM: 00 00000B0A 000B0000
N4.C2.D0.R1.S01: Offset Found: RdPtrOffsetDqs = 007
N6.C1.D0.R0: Write Training Coarse, lower nibbles / bytes
N0.C0.D1.R1.S04: Total Delay in PI ticks: TxDQS = 938, TxDQ = 903
ACCM: 00 00000B0A 000B0000
N4.C2.D0.R1.S02: Offset Found: RdPtrOffsetDqs = 007
N6.C1.D0.R0.S00: Dq Delay estimate: 470
N0.C0.D1.R1.S05: Total Delay in PI ticks: TxDQS = 959, TxDQ = 923
N2.C2.D1.R1: CheckMCTest: result = 0x1FF
N4.C2.D0.R1.S03: Offset Found: RdPtrOffsetDqs = 007
N6.C1.D0.R0.S01: Dq Delay estimate: 453
N0.C0.D1.R1.S06: Total Delay in PI ticks: TxDQS = 959, TxDQ = 923
ACCM: 0F 0F0F0F0F 0F0F0F0F
N4.C2.D0.R1.S04: Offset Found: RdPtrOffsetDqs = 006
N6.C1.D0.R0.S02: Dq Delay estimate: 444
N0.C0.D1.R1.S07: Total Delay in PI ticks: TxDQS = 977, TxDQ = 941
ACCM: 0F 0F0F0F0F 0F0F0F0F
N4.C2.D0.R1.S05: Offset Found: RdPtrOffsetDqs = 006
N6.C1.D0.R0.S03: Dq Delay estimate: 427
N0.C0.D1.R1.S08: Total Delay in PI ticks: TxDQS = 943, TxDQ = 909
ACCM: 00 00000F0E 000F0000
N4.C2.D0.R1.S06: Offset Found: RdPtrOffsetDqs = 006
N6.C1.D0.R0.S04: Dq Delay estimate: 393
N0.C0.D1.R1.S09: Total Delay in PI ticks: TxDQS = 1016, TxDQ = 979
ACCM: 00 00000F0E 000F0000
N4.C2.D0.R1.S07: Offset Found: RdPtrOffsetDqs = 007
N6.C1.D0.R0.S05: Dq Delay estimate: 407
N0.C0.D1.R1.S10: Total Delay in PI ticks: TxDQS = 1002, TxDQ = 966
N2.C2.D1.R1: CheckMCTest: result = 0x1FF
N4.C2.D0.R1.S08: Offset Found: RdPtrOffsetDqs = 006
N6.C1.D0.R0.S06: Dq Delay estimate: 425
N0.C0.D1.R1.S11: Total Delay in PI ticks: TxDQS = 990, TxDQ = 956
N2.C2.D1.R1: CheckMCTest: passed
N4.C2.D0.R1: Write Training Coarse, upper nibbles
N6.C1.D0.R0.S07: Dq Delay estimate: 439
N0.C0.D1.R1.S12: Total Delay in PI ticks: TxDQS = 974, TxDQ = 939
N2.C2.D1.R1: CheckMCTest: passed
N4.C2.D0.R1.S09: Dq Delay estimate: 459
N6.C1.D0.R0.S08: Dq Delay estimate: 410
N0.C0.D1.R1.S13: Total Delay in PI ticks: TxDQS = 941, TxDQ = 905
N2.C2.D1.R1.S00: Offset Found: RdPtrOffsetDqs = 007
N4.C2.D0.R1.S10: Dq Delay estimate: 443
ACCM: 9F 0FDF9F9F 0F0F0F0F
N0.C0.D1.R1.S14: Total Delay in PI ticks: TxDQS = 958, TxDQ = 924
N2.C2.D1.R1.S01: Offset Found: RdPtrOffsetDqs = 007
N4.C2.D0.R1.S11: Dq Delay estimate: 435
ACCM: 9F 0FDF9F9F 0F0F0F0F
N0.C0.D1.R1.S15: Total Delay in PI ticks: TxDQS = 960, TxDQ = 927
N2.C2.D1.R1.S02: Offset Found: RdPtrOffsetDqs = 007
N4.C2.D0.R1.S12: Dq Delay estimate: 419
ACCM: 9F FFFF9F9F FFFFFFFF
N0.C0.D1.R1.S16: Total Delay in PI ticks: TxDQS = 976, TxDQ = 942
N2.C2.D1.R1.S03: Offset Found: RdPtrOffsetDqs = 007
N4.C2.D0.R1.S13: Dq Delay estimate: 380
ACCM: 9F FFFF9F9F FFFFFFFF
N0.C0.D1.R1.S17: Total Delay in PI ticks: TxDQS = 945, TxDQ = 910
N2.C2.D1.R1.S04: Offset Found: RdPtrOffsetDqs = 006
N4.C2.D0.R1.S14: Dq Delay estimate: 402
N6.C1.D0.R0: CheckMCTest: result = 0x3FFFF
N0.C1.D0.R0: Write Training Coarse, lower nibbles / bytes
N2.C2.D1.R1.S05: Offset Found: RdPtrOffsetDqs = 006
N4.C2.D0.R1.S15: Dq Delay estimate: 400
ACCM: DF 0FDFDFDF 0F0F0F0F
N0.C1.D0.R0.S00: Dq Delay estimate: 475
N2.C2.D1.R1.S06: Offset Found: RdPtrOffsetDqs = 006
N4.C2.D0.R1.S16: Dq Delay estimate: 421
ACCM: DF 0FDFDFDF 0F0F0F0F
N0.C1.D0.R0.S01: Dq Delay estimate: 453
N2.C2.D1.R1.S07: Offset Found: RdPtrOffsetDqs = 007
N4.C2.D0.R1.S17: Dq Delay estimate: 393
ACCM: DF FFFFDFDF FFFFFFFF
N0.C1.D0.R0.S02: Dq Delay estimate: 447
N2.C2.D1.R1.S08: Offset Found: RdPtrOffsetDqs = 006
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: DF FFFFDFDF FFFFFFFF
N0.C1.D0.R0.S03: Dq Delay estimate: 428
N2.C2.D1.R1: Write Training Coarse, upper nibbles
ACCM: F0 F0F0F0F0 F0F0F0F0
N6.C1.D0.R0: CheckMCTest: result = 0x3FFFF
N0.C1.D0.R0.S04: Dq Delay estimate: 394
N2.C2.D1.R1.S09: Dq Delay estimate: 458
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: DF 0FDFDFDF 0F0F0F0F
N0.C1.D0.R0.S05: Dq Delay estimate: 410
N2.C2.D1.R1.S10: Dq Delay estimate: 446
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: DF 0FDFDFDF 0F0F0F0F
N0.C1.D0.R0.S06: Dq Delay estimate: 425
N2.C2.D1.R1.S11: Dq Delay estimate: 435
N4.C2.D0.R1: CheckMCTest: result = 0x3FE00
ACCM: D0 FBFBDBDB FBF0FBFB
N0.C1.D0.R0.S07: Dq Delay estimate: 441
N2.C2.D1.R1.S12: Dq Delay estimate: 421
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: D0 FBFBDBDB FBF0FBFB
N0.C1.D0.R0.S08: Dq Delay estimate: 411
N2.C2.D1.R1.S13: Dq Delay estimate: 380
ACCM: F0 F0F0F0F0 F0F0F0F0
N6.C1.D0.R0: CheckMCTest: result = 0x3FFFF
ACCM: FF 0F0FFF9F 0F0F0F0F
N2.C2.D1.R1.S14: Dq Delay estimate: 408
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: DF 0FDFDFDF 0F0F0F0F
ACCM: FF 0F0FFF9F 0F0F0F0F
N2.C2.D1.R1.S15: Dq Delay estimate: 401
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: DF 0FDFDFDF 0F0F0F0F
ACCM: FF FFFFFF9F FFFFFFFF
N2.C2.D1.R1.S16: Dq Delay estimate: 427
N4.C2.D0.R1: CheckMCTest: result = 0x3FE00
ACCM: DD FFFFDFDF FFF0FFFF
ACCM: FF FFFFFF9F FFFFFFFF
N2.C2.D1.R1.S17: Dq Delay estimate: 391
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: DD FFFFDFDF FFF0FFFF
N0.C1.D0.R0: CheckMCTest: result = 0x3FFFF
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: F0 F0F0F0F0 F0F0F0F0
N6.C1.D0.R0: CheckMCTest: result = 0x3FFFF
ACCM: FF 0F0FFFDF 0F0F0F0F
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: 00 000000B0 000000B0
ACCM: D0 00D0D0D0 00000000
ACCM: FF 0F0FFFDF 0F0F0F0F
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: 00 000000B0 000000B0
ACCM: D0 00D0D0D0 00000000
ACCM: FF FFFFFFDF FFFFFFFF
ACCM: F0 F0F0F0F0 F0F0F0F0
N4.C2.D0.R1: CheckMCTest: result = 0x3FE00
ACCM: D0 F0F0D0D0 F0F0F0F0
ACCM: FF FFFFFFDF FFFFFFFF
N2.C2.D1.R1: CheckMCTest: result = 0x3FE00
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: D0 F0F0D0D0 F0F0F0F0
N0.C1.D0.R0: CheckMCTest: result = 0x3FFFF
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: F0 F0F0F0F0 F0F0F0F0
N6.C1.D0.R0: CheckMCTest: result = 0x3FE00
ACCM: FF 0F0FFFDF 0F0F0F0F
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: 00 000000F0 000000F0
ACCM: D0 00D0D0D0 00000000
ACCM: FF 0F0FFFDF 0F0F0F0F
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: 00 000000F0 000000F0
ACCM: D0 00D0D0D0 00000000
ACCM: F0 FBFBFBDB FBFBFBFB
ACCM: F0 F0F0F0F0 F0F0F0F0
N4.C2.D0.R1: CheckMCTest: result = 0x3FE00
ACCM: D0 F0F0D0D0 F0F0F0F0
ACCM: F0 FBFBFBDB FBFBFBFB
N2.C2.D1.R1: CheckMCTest: result = 0x3FE00
N4.C2.D0.R1: CheckMCTest: passed
ACCM: D0 F0F0D0D0 F0F0F0F0
N0.C1.D0.R0: CheckMCTest: result = 0x3FFFF
ACCM: F0 F0F0F0F0 F0F0F0F0
N4.C2.D0.R1: CheckMCTest: passed
N6.C1.D0.R0: CheckMCTest: result = 0x3FE00
ACCM: FF 0F0FFFDF 0F0F0F0F
ACCM: F0 F0F0F0F0 F0F0F0F0
N4.C2.D0.R1.S09: Offset Found: RdPtrOffsetDqs = 007
N6.C1.D0.R0.S00: Offset Found: RdPtrOffsetDqs = 007
ACCM: FF 0F0FFFDF 0F0F0F0F
ACCM: 00 0000B0B0 00000000
N4.C2.D0.R1.S10: Offset Found: RdPtrOffsetDqs = 007
N6.C1.D0.R0.S01: Offset Found: RdPtrOffsetDqs = 007
ACCM: FD FFFFFFDF FFFFFFFF
ACCM: 00 0000B0B0 00000000
N4.C2.D0.R1.S11: Offset Found: RdPtrOffsetDqs = 007
N6.C1.D0.R0.S02: Offset Found: RdPtrOffsetDqs = 007
ACCM: FD FFFFFFDF FFFFFFFF
N2.C2.D1.R1: CheckMCTest: result = 0x3FE00
N4.C2.D0.R1.S12: Offset Found: RdPtrOffsetDqs = 007
N6.C1.D0.R0.S03: Offset Found: RdPtrOffsetDqs = 007
N0.C1.D0.R0: CheckMCTest: result = 0x3FFFF
ACCM: F0 F0F0F0F0 F0F0F0F0
N4.C2.D0.R1.S13: Offset Found: RdPtrOffsetDqs = 006
N6.C1.D0.R0.S04: Offset Found: RdPtrOffsetDqs = 006
ACCM: F0 0000F0D0 00000000
ACCM: F0 F0F0F0F0 F0F0F0F0
N4.C2.D0.R1.S14: Offset Found: RdPtrOffsetDqs = 006
N6.C1.D0.R0.S05: Offset Found: RdPtrOffsetDqs = 006
ACCM: F0 0000F0D0 00000000
ACCM: 00 0000F0F0 00000000
N4.C2.D0.R1.S15: Offset Found: RdPtrOffsetDqs = 006
N6.C1.D0.R0.S06: Offset Found: RdPtrOffsetDqs = 007
ACCM: F0 F0F0F0D0 F0F0F0F0
ACCM: 00 0000F0F0 00000000
N4.C2.D0.R1.S16: Offset Found: RdPtrOffsetDqs = 007
N6.C1.D0.R0.S07: Offset Found: RdPtrOffsetDqs = 007
ACCM: F0 F0F0F0D0 F0F0F0F0
N2.C2.D1.R1: CheckMCTest: result = 0x3FE00
N4.C2.D0.R1.S17: Offset Found: RdPtrOffsetDqs = 006
N6.C1.D0.R0.S08: Offset Found: RdPtrOffsetDqs = 006
N0.C1.D0.R0: CheckMCTest: result = 0x3FE00
N2.C2.D1.R1: CheckMCTest: passed
N4.C2.D1.R0: Write Training Coarse, lower nibbles / bytes
N6.C1.D0.R0: Write Training Coarse, upper nibbles
ACCM: F0 0000F0D0 00000000
N2.C2.D1.R1: CheckMCTest: passed
N4.C2.D1.R0.S00: Dq Delay estimate: 466
N6.C1.D0.R0.S09: Dq Delay estimate: 468
ACCM: F0 0000F0D0 00000000
N2.C2.D1.R1.S09: Offset Found: RdPtrOffsetDqs = 007
N4.C2.D1.R0.S01: Dq Delay estimate: 450
N6.C1.D0.R0.S10: Dq Delay estimate: 452
ACCM: F0 F0F0F0D0 F0F0F0F0
N2.C2.D1.R1.S10: Offset Found: RdPtrOffsetDqs = 007
N4.C2.D1.R0.S02: Dq Delay estimate: 443
N6.C1.D0.R0.S11: Dq Delay estimate: 445
ACCM: F0 F0F0F0D0 F0F0F0F0
N2.C2.D1.R1.S11: Offset Found: RdPtrOffsetDqs = 007
N4.C2.D1.R0.S03: Dq Delay estimate: 427
N6.C1.D0.R0.S12: Dq Delay estimate: 428
N0.C1.D0.R0: CheckMCTest: result = 0x3FE00
N2.C2.D1.R1.S12: Offset Found: RdPtrOffsetDqs = 007
N4.C2.D1.R0.S04: Dq Delay estimate: 384
N6.C1.D0.R0.S13: Dq Delay estimate: 392
N0.C1.D0.R0.S00: Offset Found: RdPtrOffsetDqs = 007
N2.C2.D1.R1.S13: Offset Found: RdPtrOffsetDqs = 006
N4.C2.D1.R0.S05: Dq Delay estimate: 412
N6.C1.D0.R0.S14: Dq Delay estimate: 406
N0.C1.D0.R0.S01: Offset Found: RdPtrOffsetDqs = 007
N2.C2.D1.R1.S14: Offset Found: RdPtrOffsetDqs = 006
N4.C2.D1.R0.S06: Dq Delay estimate: 409
N6.C1.D0.R0.S15: Dq Delay estimate: 423
N0.C1.D0.R0.S02: Offset Found: RdPtrOffsetDqs = 007
N2.C2.D1.R1.S15: Offset Found: RdPtrOffsetDqs = 006
N4.C2.D1.R0.S07: Dq Delay estimate: 428
N6.C1.D0.R0.S16: Dq Delay estimate: 437
N0.C1.D0.R0.S03: Offset Found: RdPtrOffsetDqs = 007
N2.C2.D1.R1.S16: Offset Found: RdPtrOffsetDqs = 007
N4.C2.D1.R0.S08: Dq Delay estimate: 400
N6.C1.D0.R0.S17: Dq Delay estimate: 410
N0.C1.D0.R0.S04: Offset Found: RdPtrOffsetDqs = 006
N2.C2.D1.R1.S17: Offset Found: RdPtrOffsetDqs = 006
ACCM: 0F 0F0F0F0F 0F0F0F0F
ACCM: F0 F0F0F0F0 F0F0F0F0
N0.C1.D0.R0.S05: Offset Found: RdPtrOffsetDqs = 006
N2.C2: Calculating Optimimum DQS Values
ACCM: 0F 0F0F0F0F 0F0F0F0F
ACCM: F0 F0F0F0F0 F0F0F0F0
N0.C1.D0.R0.S06: Offset Found: RdPtrOffsetDqs = 007
N2.C2.D0.R0.S00: Total Delay in PI ticks: TxDQS = 1010, TxDQ = 977
ACCM: 0F 0F0F0F0F 0F0F0F0F
ACCM: F0 F0F0F0F0 F0F0F0F0
N0.C1.D0.R0.S07: Offset Found: RdPtrOffsetDqs = 007
N2.C2.D0.R0.S01: Total Delay in PI ticks: TxDQS = 995, TxDQ = 961
ACCM: 0F FF0F0FFF FFFFFF0F
ACCM: F0 F0F0F0F0 F0F0F0F0
N0.C1.D0.R0.S08: Offset Found: RdPtrOffsetDqs = 006
N2.C2.D0.R0.S02: Total Delay in PI ticks: TxDQS = 984, TxDQ = 949
N4.C2.D1.R0: CheckMCTest: result = 0x13DFF
N6.C1.D0.R0: CheckMCTest: result = 0x3FE00
N0.C1.D0.R0: Write Training Coarse, upper nibbles
N2.C2.D0.R0.S03: Total Delay in PI ticks: TxDQS = 966, TxDQ = 932
ACCM: 0F 0F0F0F0F 0F0F0F0F
ACCM: F0 F0F0F0F0 F0F0F0F0
N0.C1.D0.R0.S09: Dq Delay estimate: 473
N2.C2.D0.R0.S04: Total Delay in PI ticks: TxDQS = 925, TxDQ = 892
ACCM: 0F 0F0F0F0F 0F0F0F0F
ACCM: F0 F0F0F0F0 F0F0F0F0
N0.C1.D0.R0.S10: Dq Delay estimate: 454
N2.C2.D0.R0.S05: Total Delay in PI ticks: TxDQS = 956, TxDQ = 920
ACCM: 0F 0F0F0F0F 0F0F0F0F
ACCM: F0 F0F0F0F0 F0F0F0F0
N0.C1.D0.R0.S11: Dq Delay estimate: 450
N2.C2.D0.R0.S06: Total Delay in PI ticks: TxDQS = 952, TxDQ = 918
ACCM: 0F FF0F0FFF FFFFFF0F
ACCM: F0 F0F0F0F0 F0F0F0F0
N0.C1.D0.R0.S12: Dq Delay estimate: 430
N2.C2.D0.R0.S07: Total Delay in PI ticks: TxDQS = 974, TxDQ = 937
N4.C2.D1.R0: CheckMCTest: result = 0x13DFF
N6.C1.D0.R0: CheckMCTest: result = 0x3FE00
N0.C1.D0.R0.S13: Dq Delay estimate: 394
N2.C2.D0.R0.S08: Total Delay in PI ticks: TxDQS = 948, TxDQ = 913
ACCM: 0F 0F0F0F0F 0F0F0F0F
ACCM: F0 F0F0F0F0 F0F0F0F0
N0.C1.D0.R0.S14: Dq Delay estimate: 408
N2.C2.D0.R0.S09: Total Delay in PI ticks: TxDQS = 1012, TxDQ = 977
ACCM: 0F 0F0F0F0F 0F0F0F0F
ACCM: F0 F0F0F0F0 F0F0F0F0
N0.C1.D0.R0.S15: Dq Delay estimate: 426
N2.C2.D0.R0.S10: Total Delay in PI ticks: TxDQS = 994, TxDQ = 961
ACCM: 00 0B0B000B 000B0000
ACCM: 00 B0B0B0B0 B000B0B0
N0.C1.D0.R0.S16: Dq Delay estimate: 442
N2.C2.D0.R0.S11: Total Delay in PI ticks: TxDQS = 984, TxDQ = 948
ACCM: 00 FB0B00FB F0FBF000
ACCM: 00 B0B0B0B0 B000B0B0
N0.C1.D0.R0.S17: Dq Delay estimate: 413
N2.C2.D0.R0.S12: Total Delay in PI ticks: TxDQS = 968, TxDQ = 933
N4.C2.D1.R0: CheckMCTest: result = 0x13DFF
N6.C1.D0.R0: CheckMCTest: result = 0x3FE00
ACCM: F0 F0F0F0F0 F0F0F0F0
N2.C2.D0.R0.S13: Total Delay in PI ticks: TxDQS = 927, TxDQ = 894
ACCM: 0F 0F0F0F0F 0F0F0F0F
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: F0 F0F0F0F0 F0F0F0F0
N2.C2.D0.R0.S14: Total Delay in PI ticks: TxDQS = 954, TxDQ = 918
ACCM: 0F 0F0F0F0F 0F0F0F0F
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: F0 F0F0F0F0 F0F0F0F0
N2.C2.D0.R0.S15: Total Delay in PI ticks: TxDQS = 952, TxDQ = 916
ACCM: 00 0F0F000F 000B0000
ACCM: 00 F0F0F0F0 F000F0F0
ACCM: F0 F0F0F0F0 F0F0F0F0
N2.C2.D0.R0.S16: Total Delay in PI ticks: TxDQS = 976, TxDQ = 940
ACCM: 00 FF0F00FF F0FBF000
ACCM: 00 F0F0F0F0 F000F0F0
N0.C1.D0.R0: CheckMCTest: result = 0x3FE00
N2.C2.D0.R0.S17: Total Delay in PI ticks: TxDQS = 947, TxDQ = 911
N4.C2.D1.R0: CheckMCTest: result = 0x13DFF
N6.C1.D0.R0: CheckMCTest: result = 0x3FE00
ACCM: F0 F0F0F0F0 F0F0F0F0
N2.C2.D0.R1.S00: Total Delay in PI ticks: TxDQS = 1003, TxDQ = 970
ACCM: 00 00000000 00000000
N6.C1.D0.R0: CheckMCTest: passed
ACCM: F0 F0F0F0F0 F0F0F0F0
N2.C2.D0.R1.S01: Total Delay in PI ticks: TxDQS = 988, TxDQ = 954
ACCM: 00 00000000 00000000
N6.C1.D0.R0: CheckMCTest: passed
ACCM: F0 F0F0F0F0 F0F0F0F0
N2.C2.D0.R1.S02: Total Delay in PI ticks: TxDQS = 977, TxDQ = 942
ACCM: 00 00000000 00000000
N6.C1.D0.R0.S09: Offset Found: RdPtrOffsetDqs = 007
ACCM: F0 F0F0F0F0 F0F0F0F0
N2.C2.D0.R1.S03: Total Delay in PI ticks: TxDQS = 961, TxDQ = 927
ACCM: 00 F00000F0 F0F0F000
N6.C1.D0.R0.S10: Offset Found: RdPtrOffsetDqs = 007
N0.C1.D0.R0: CheckMCTest: result = 0x3FE00
N2.C2.D0.R1.S04: Total Delay in PI ticks: TxDQS = 921, TxDQ = 888
N4.C2.D1.R0: CheckMCTest: result = 0x13C00
N6.C1.D0.R0.S11: Offset Found: RdPtrOffsetDqs = 007
ACCM: F0 F0F0F0F0 F0F0F0F0
N2.C2.D0.R1.S05: Total Delay in PI ticks: TxDQS = 950, TxDQ = 914
ACCM: 00 00000000 00000000
N6.C1.D0.R0.S12: Offset Found: RdPtrOffsetDqs = 007
ACCM: F0 F0F0F0F0 F0F0F0F0
N2.C2.D0.R1.S06: Total Delay in PI ticks: TxDQS = 946, TxDQ = 913
ACCM: 00 00000000 00000000
N6.C1.D0.R0.S13: Offset Found: RdPtrOffsetDqs = 006
ACCM: B0 00B000B0 0000B0B0
N2.C2.D0.R1.S07: Total Delay in PI ticks: TxDQS = 969, TxDQ = 932
ACCM: 00 00000000 00000000
N6.C1.D0.R0.S14: Offset Found: RdPtrOffsetDqs = 006
ACCM: B0 00B000B0 0000B0B0
N2.C2.D0.R1.S08: Total Delay in PI ticks: TxDQS = 938, TxDQ = 903
ACCM: 00 F00000F0 F0F0F000
N6.C1.D0.R0.S15: Offset Found: RdPtrOffsetDqs = 007
N0.C1.D0.R0: CheckMCTest: result = 0x3FE00
N2.C2.D0.R1.S09: Total Delay in PI ticks: TxDQS = 1002, TxDQ = 967
N4.C2.D1.R0: CheckMCTest: result = 0x13C00
N6.C1.D0.R0.S16: Offset Found: RdPtrOffsetDqs = 007
ACCM: F0 F0F0F0F0 F0F0F0F0
N2.C2.D0.R1.S10: Total Delay in PI ticks: TxDQS = 988, TxDQ = 953
N4.C2.D1.R0.S00: Offset Found: RdPtrOffsetDqs = 007
N6.C1.D0.R0.S17: Offset Found: RdPtrOffsetDqs = 006
ACCM: F0 F0F0F0F0 F0F0F0F0
N2.C2.D0.R1.S11: Total Delay in PI ticks: TxDQS = 979, TxDQ = 943
N4.C2.D1.R0.S01: Offset Found: RdPtrOffsetDqs = 007
N6.C1.D0.R1: Write Training Coarse, lower nibbles / bytes
ACCM: F0 00F000F0 00D0F0F0
N2.C2.D0.R1.S12: Total Delay in PI ticks: TxDQS = 963, TxDQ = 928
N4.C2.D1.R0.S02: Offset Found: RdPtrOffsetDqs = 007
N6.C1.D0.R1.S00: Dq Delay estimate: 464
ACCM: F0 00F000F0 00D0F0F0
N2.C2.D0.R1.S13: Total Delay in PI ticks: TxDQS = 921, TxDQ = 888
N4.C2.D1.R0.S03: Offset Found: RdPtrOffsetDqs = 007
N6.C1.D0.R1.S01: Dq Delay estimate: 444
N0.C1.D0.R0: CheckMCTest: result = 0x3FE00
N2.C2.D0.R1.S14: Total Delay in PI ticks: TxDQS = 950, TxDQ = 914
N4.C2.D1.R0.S04: Offset Found: RdPtrOffsetDqs = 006
N6.C1.D0.R1.S02: Dq Delay estimate: 439
N0.C1.D0.R0: CheckMCTest: passed
N2.C2.D0.R1.S15: Total Delay in PI ticks: TxDQS = 947, TxDQ = 911
N4.C2.D1.R0.S05: Offset Found: RdPtrOffsetDqs = 007
N6.C1.D0.R1.S03: Dq Delay estimate: 420
N0.C1.D0.R0: CheckMCTest: passed
N2.C2.D0.R1.S16: Total Delay in PI ticks: TxDQS = 970, TxDQ = 934
N4.C2.D1.R0.S06: Offset Found: RdPtrOffsetDqs = 007
N6.C1.D0.R1.S04: Dq Delay estimate: 389
N0.C1.D0.R0.S09: Offset Found: RdPtrOffsetDqs = 007
N2.C2.D0.R1.S17: Total Delay in PI ticks: TxDQS = 938, TxDQ = 903
N4.C2.D1.R0.S07: Offset Found: RdPtrOffsetDqs = 007
N6.C1.D0.R1.S05: Dq Delay estimate: 401
N0.C1.D0.R0.S10: Offset Found: RdPtrOffsetDqs = 007
N2.C2.D1.R0.S00: Total Delay in PI ticks: TxDQS = 1010, TxDQ = 975
N4.C2.D1.R0.S08: Offset Found: RdPtrOffsetDqs = 006
N6.C1.D0.R1.S06: Dq Delay estimate: 416
N0.C1.D0.R0.S11: Offset Found: RdPtrOffsetDqs = 007
N2.C2.D1.R0.S01: Total Delay in PI ticks: TxDQS = 999, TxDQ = 963
N4.C2.D1.R0: Write Training Coarse, upper nibbles
N6.C1.D0.R1.S07: Dq Delay estimate: 431
N0.C1.D0.R0.S12: Offset Found: RdPtrOffsetDqs = 007
N2.C2.D1.R0.S02: Total Delay in PI ticks: TxDQS = 985, TxDQ = 948
N4.C2.D1.R0.S09: Dq Delay estimate: 468
N6.C1.D0.R1.S08: Dq Delay estimate: 403
N0.C1.D0.R0.S13: Offset Found: RdPtrOffsetDqs = 006
N2.C2.D1.R0.S03: Total Delay in PI ticks: TxDQS = 975, TxDQ = 939
N4.C2.D1.R0.S10: Dq Delay estimate: 450
ACCM: 0F 0F0F0F0F 0F0F0F0F
N0.C1.D0.R0.S14: Offset Found: RdPtrOffsetDqs = 006
N2.C2.D1.R0.S04: Total Delay in PI ticks: TxDQS = 930, TxDQ = 894
N4.C2.D1.R0.S11: Dq Delay estimate: 444
ACCM: 0F 0F0F0F0F 0F0F0F0F
N0.C1.D0.R0.S15: Offset Found: RdPtrOffsetDqs = 007
N2.C2.D1.R0.S05: Total Delay in PI ticks: TxDQS = 960, TxDQ = 924
N4.C2.D1.R0.S12: Dq Delay estimate: 426
ACCM: 0F 0F0F0F0F 0F0F0F0F
N0.C1.D0.R0.S16: Offset Found: RdPtrOffsetDqs = 007
N2.C2.D1.R0.S06: Total Delay in PI ticks: TxDQS = 956, TxDQ = 921
N4.C2.D1.R0.S13: Dq Delay estimate: 386
ACCM: 0F 0F0F0F0F 0F0F0F0F
N0.C1.D0.R0.S17: Offset Found: RdPtrOffsetDqs = 006
N2.C2.D1.R0.S07: Total Delay in PI ticks: TxDQS = 979, TxDQ = 940
N4.C2.D1.R0.S14: Dq Delay estimate: 409
N6.C1.D0.R1: CheckMCTest: result = 0x1FF
N0.C1.D0.R1: Write Training Coarse, lower nibbles / bytes
N2.C2.D1.R0.S08: Total Delay in PI ticks: TxDQS = 945, TxDQ = 909
N4.C2.D1.R0.S15: Dq Delay estimate: 410
ACCM: 0F 0F0F0F0F 0F0F0F0F
N0.C1.D0.R1.S00: Dq Delay estimate: 465
N2.C2.D1.R0.S09: Total Delay in PI ticks: TxDQS = 1010, TxDQ = 973
N4.C2.D1.R0.S16: Dq Delay estimate: 432
ACCM: 0F 0F0F0F0F 0F0F0F0F
N0.C1.D0.R1.S01: Dq Delay estimate: 446
N2.C2.D1.R0.S10: Total Delay in PI ticks: TxDQS = 999, TxDQ = 963
N4.C2.D1.R0.S17: Dq Delay estimate: 400
ACCM: 0F 0F0F0F0F 0F0F0F0F
N0.C1.D0.R1.S02: Dq Delay estimate: 439
N2.C2.D1.R0.S11: Total Delay in PI ticks: TxDQS = 986, TxDQ = 949
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: 0F 0F0F0F0F 0F0F0F0F
N0.C1.D0.R1.S03: Dq Delay estimate: 423
N2.C2.D1.R0.S12: Total Delay in PI ticks: TxDQS = 975, TxDQ = 939
ACCM: F0 F0F0F0F0 F0F0F0F0
N6.C1.D0.R1: CheckMCTest: result = 0x1FF
N0.C1.D0.R1.S04: Dq Delay estimate: 388
N2.C2.D1.R0.S13: Total Delay in PI ticks: TxDQS = 931, TxDQ = 897
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: 0F 0F0F0F0F 0F0F0F0F
N0.C1.D0.R1.S05: Dq Delay estimate: 404
N2.C2.D1.R0.S14: Total Delay in PI ticks: TxDQS = 959, TxDQ = 922
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: 0F 0F0F0F0F 0F0F0F0F
N0.C1.D0.R1.S06: Dq Delay estimate: 416
N2.C2.D1.R0.S15: Total Delay in PI ticks: TxDQS = 956, TxDQ = 918
N4.C2.D1.R0: CheckMCTest: result = 0x3FE00
ACCM: 00 0000000B 0B000000
N0.C1.D0.R1.S07: Dq Delay estimate: 435
N2.C2.D1.R0.S16: Total Delay in PI ticks: TxDQS = 979, TxDQ = 942
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: 00 0000000B 0B000000
N0.C1.D0.R1.S08: Dq Delay estimate: 405
N2.C2.D1.R0.S17: Total Delay in PI ticks: TxDQS = 945, TxDQ = 908
ACCM: F0 F0F0F0F0 F0F0F0F0
N6.C1.D0.R1: CheckMCTest: result = 0x1FF
ACCM: 0F 0F0F0F0F 0F0F0F0F
N2.C2.D1.R1.S00: Total Delay in PI ticks: TxDQS = 1009, TxDQ = 974
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: 0F 0F0F0F0F 0F0F0F0F
ACCM: 0F 0F0F0F0F 0F0F0F0F
N2.C2.D1.R1.S01: Total Delay in PI ticks: TxDQS = 993, TxDQ = 958
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: 0F 0F0F0F0F 0F0F0F0F
ACCM: 0F 0F0F0F0F 0F0F0F0F
N2.C2.D1.R1.S02: Total Delay in PI ticks: TxDQS = 981, TxDQ = 944
N4.C2.D1.R0: CheckMCTest: result = 0x3FE00
ACCM: 00 0000000F 0F000000
ACCM: 0F 0F0F0F0F 0F0F0F0F
N2.C2.D1.R1.S03: Total Delay in PI ticks: TxDQS = 970, TxDQ = 934
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: 00 0000000F 0F000000
N0.C1.D0.R1: CheckMCTest: result = 0x1FF
N2.C2.D1.R1.S04: Total Delay in PI ticks: TxDQS = 925, TxDQ = 889
ACCM: F0 F0F0F0F0 F0F0F0F0
N6.C1.D0.R1: CheckMCTest: result = 0x1FF
ACCM: 0F 0F0F0F0F 0F0F0F0F
N2.C2.D1.R1.S05: Total Delay in PI ticks: TxDQS = 958, TxDQ = 922
ACCM: B0 B00000B0 B0B000B0
N6.C1.D0.R1: CheckMCTest: passed
ACCM: 0F 0F0F0F0F 0F0F0F0F
N2.C2.D1.R1.S06: Total Delay in PI ticks: TxDQS = 950, TxDQ = 915
ACCM: B0 B00000B0 B0B000B0
N6.C1.D0.R1: CheckMCTest: passed
ACCM: 0F 0F0F0F0F 0F0F0F0F
N2.C2.D1.R1.S07: Total Delay in PI ticks: TxDQS = 977, TxDQ = 938
N4.C2.D1.R0: CheckMCTest: result = 0x3FE00
N6.C1.D0.R1.S00: Offset Found: RdPtrOffsetDqs = 007
ACCM: 0F 0F0F0F0F 0F0F0F0F
N2.C2.D1.R1.S08: Total Delay in PI ticks: TxDQS = 941, TxDQ = 905
ACCM: F0 F0F0F0F0 F0F0F0F0
N6.C1.D0.R1.S01: Offset Found: RdPtrOffsetDqs = 007
N0.C1.D0.R1: CheckMCTest: result = 0x1FF
N2.C2.D1.R1.S09: Total Delay in PI ticks: TxDQS = 1007, TxDQ = 970
ACCM: F0 F0F0F0F0 F0F0F0F0
N6.C1.D0.R1.S02: Offset Found: RdPtrOffsetDqs = 007
ACCM: 0F 0F0F0F0F 0F0F0F0F
N2.C2.D1.R1.S10: Total Delay in PI ticks: TxDQS = 994, TxDQ = 958
ACCM: F0 F00000F0 F0F000F0
N6.C1.D0.R1.S03: Offset Found: RdPtrOffsetDqs = 007
ACCM: 0F 0F0F0F0F 0F0F0F0F
N2.C2.D1.R1.S11: Total Delay in PI ticks: TxDQS = 984, TxDQ = 947
ACCM: F0 F00000F0 F0F000F0
N6.C1.D0.R1.S04: Offset Found: RdPtrOffsetDqs = 006
ACCM: 0B 0B0B000B 0B000B00
N2.C2.D1.R1.S12: Total Delay in PI ticks: TxDQS = 969, TxDQ = 933
N4.C2.D1.R0: CheckMCTest: result = 0x3FE00
N6.C1.D0.R1.S05: Offset Found: RdPtrOffsetDqs = 006
ACCM: 0B 0B0B000B 0B000B00
N2.C2.D1.R1.S13: Total Delay in PI ticks: TxDQS = 927, TxDQ = 892
N4.C2.D1.R0: CheckMCTest: passed
N6.C1.D0.R1.S06: Offset Found: RdPtrOffsetDqs = 007
N0.C1.D0.R1: CheckMCTest: result = 0x1FF
N2.C2.D1.R1.S14: Total Delay in PI ticks: TxDQS = 957, TxDQ = 920
N4.C2.D1.R0: CheckMCTest: passed
N6.C1.D0.R1.S07: Offset Found: RdPtrOffsetDqs = 007
ACCM: 0F 0F0F0F0F 0F0F0F0F
N2.C2.D1.R1.S15: Total Delay in PI ticks: TxDQS = 951, TxDQ = 913
N4.C2.D1.R0.S09: Offset Found: RdPtrOffsetDqs = 007
N6.C1.D0.R1.S08: Offset Found: RdPtrOffsetDqs = 006
ACCM: 0F 0F0F0F0F 0F0F0F0F
N2.C2.D1.R1.S16: Total Delay in PI ticks: TxDQS = 976, TxDQ = 939
N4.C2.D1.R0.S10: Offset Found: RdPtrOffsetDqs = 007
N6.C1.D0.R1: Write Training Coarse, upper nibbles
ACCM: 0F 0B0F000F 0F000F00
N2.C2.D1.R1.S17: Total Delay in PI ticks: TxDQS = 940, TxDQ = 903
N4.C2.D1.R0.S11: Offset Found: RdPtrOffsetDqs = 007
N6.C1.D0.R1.S09: Dq Delay estimate: 460
ACCM: 0F 0B0F000F 0F000F00
N2.C3.D0.R0: Write Training Coarse, lower nibbles / bytes
N4.C2.D1.R0.S12: Offset Found: RdPtrOffsetDqs = 007
N6.C1.D0.R1.S10: Dq Delay estimate: 446
N0.C1.D0.R1: CheckMCTest: result = 0x1FF
N2.C3.D0.R0.S00: Dq Delay estimate: 465
N4.C2.D1.R0.S13: Offset Found: RdPtrOffsetDqs = 006
N6.C1.D0.R1.S11: Dq Delay estimate: 440
N0.C1.D0.R1: CheckMCTest: passed
N2.C3.D0.R0.S01: Dq Delay estimate: 455
N4.C2.D1.R0.S14: Offset Found: RdPtrOffsetDqs = 007
N6.C1.D0.R1.S12: Dq Delay estimate: 421
N0.C1.D0.R1: CheckMCTest: passed
N2.C3.D0.R0.S02: Dq Delay estimate: 440
N4.C2.D1.R0.S15: Offset Found: RdPtrOffsetDqs = 007
N6.C1.D0.R1.S13: Dq Delay estimate: 387
N0.C1.D0.R1.S00: Offset Found: RdPtrOffsetDqs = 007
N2.C3.D0.R0.S03: Dq Delay estimate: 426
N4.C2.D1.R0.S16: Offset Found: RdPtrOffsetDqs = 007
N6.C1.D0.R1.S14: Dq Delay estimate: 399
N0.C1.D0.R1.S01: Offset Found: RdPtrOffsetDqs = 007
N2.C3.D0.R0.S04: Dq Delay estimate: 393
N4.C2.D1.R0.S17: Offset Found: RdPtrOffsetDqs = 006
N6.C1.D0.R1.S15: Dq Delay estimate: 416
N0.C1.D0.R1.S02: Offset Found: RdPtrOffsetDqs = 007
N2.C3.D0.R0.S05: Dq Delay estimate: 405
N4.C2.D1.R1: Write Training Coarse, lower nibbles / bytes
N6.C1.D0.R1.S16: Dq Delay estimate: 431
N0.C1.D0.R1.S03: Offset Found: RdPtrOffsetDqs = 007
N2.C3.D0.R0.S06: Dq Delay estimate: 420
N4.C2.D1.R1.S00: Dq Delay estimate: 462
N6.C1.D0.R1.S17: Dq Delay estimate: 401
N0.C1.D0.R1.S04: Offset Found: RdPtrOffsetDqs = 006
N2.C3.D0.R0.S07: Dq Delay estimate: 436
N4.C2.D1.R1.S01: Dq Delay estimate: 447
ACCM: F0 F0F0F0F0 F0F0F0F0
N0.C1.D0.R1.S05: Offset Found: RdPtrOffsetDqs = 006
N2.C3.D0.R0.S08: Dq Delay estimate: 412
N4.C2.D1.R1.S02: Dq Delay estimate: 439
ACCM: F0 F0F0F0F0 F0F0F0F0
N0.C1.D0.R1.S06: Offset Found: RdPtrOffsetDqs = 007
ACCM: 9F 0FDF9F9F 0F0F0F0F
N4.C2.D1.R1.S03: Dq Delay estimate: 426
ACCM: F0 F0F0F0F0 F0F0F0F0
N0.C1.D0.R1.S07: Offset Found: RdPtrOffsetDqs = 007
ACCM: 9F 0FDF9F9F 0F0F0F0F
N4.C2.D1.R1.S04: Dq Delay estimate: 382
ACCM: F0 F0F0F0F0 F0F0F0F0
N0.C1.D0.R1.S08: Offset Found: RdPtrOffsetDqs = 006
ACCM: 9F FFFF9F9F FFFFFFFF
N4.C2.D1.R1.S05: Dq Delay estimate: 410
N6.C1.D0.R1: CheckMCTest: result = 0x3FE00
N0.C1.D0.R1: Write Training Coarse, upper nibbles
ACCM: 9F FFFF9F9F FFFFFFFF
N4.C2.D1.R1.S06: Dq Delay estimate: 403
ACCM: F0 F0F0F0F0 F0F0F0F0
N0.C1.D0.R1.S09: Dq Delay estimate: 464
N2.C3.D0.R0: CheckMCTest: result = 0x3FFFF
N4.C2.D1.R1.S07: Dq Delay estimate: 426
ACCM: F0 F0F0F0F0 F0F0F0F0
N0.C1.D0.R1.S10: Dq Delay estimate: 447
ACCM: DF 0FDFDFDF 0F0F0F0F
N4.C2.D1.R1.S08: Dq Delay estimate: 394
ACCM: F0 F0F0F0F0 F0F0F0F0
N0.C1.D0.R1.S11: Dq Delay estimate: 439
ACCM: DF 0FDFDFDF 0F0F0F0F
ACCM: 0F 0F0F0F0F 0F0F0F0F
ACCM: F0 F0F0F0F0 F0F0F0F0
N0.C1.D0.R1.S12: Dq Delay estimate: 424
ACCM: DF FFFFDFDF FFFFFFFF
ACCM: 0F 0F0F0F0F 0F0F0F0F
N6.C1.D0.R1: CheckMCTest: result = 0x3FE00
N0.C1.D0.R1.S13: Dq Delay estimate: 391
ACCM: DF FFFFDFDF FFFFFFFF
ACCM: 0F 0F0F0F0F 0F0F0F0F
ACCM: F0 F0F0F0F0 F0F0F0F0
N0.C1.D0.R1.S14: Dq Delay estimate: 406
N2.C3.D0.R0: CheckMCTest: result = 0x3FFFF
ACCM: 0F 0F0F0F0F 0F0F0F0F
ACCM: F0 F0F0F0F0 F0F0F0F0
N0.C1.D0.R1.S15: Dq Delay estimate: 417
ACCM: DF 0FDFDFDF 0F0F0F0F
N4.C2.D1.R1: CheckMCTest: result = 0x1FF
ACCM: 00 00000000 B0000000
N0.C1.D0.R1.S16: Dq Delay estimate: 440
ACCM: DF 0FDFDFDF 0F0F0F0F
ACCM: 0F 0F0F0F0F 0F0F0F0F
ACCM: 00 00000000 B0000000
N0.C1.D0.R1.S17: Dq Delay estimate: 405
ACCM: D0 FBFBDBDB FBF0FBF0
ACCM: 0F 0F0F0F0F 0F0F0F0F
N6.C1.D0.R1: CheckMCTest: result = 0x3FE00
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: D0 FBFBDBDB FBF0FBF0
ACCM: 0F 0F0F0F0F 0F0F0F0F
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: F0 F0F0F0F0 F0F0F0F0
N2.C3.D0.R0: CheckMCTest: result = 0x3FFFF
ACCM: 0F 0F0F0F0F 0F0F0F0F
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: DF 0FDFDFDF 0F0F0F0F
N4.C2.D1.R1: CheckMCTest: result = 0x1FF
ACCM: 00 00000000 F0000000
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: DF 0FDFDFDF 0F0F0F0F
ACCM: 0F 0F0F0F0F 0F0F0F0F
ACCM: 00 00000000 F0000000
N0.C1.D0.R1: CheckMCTest: result = 0x3FE00
ACCM: DD FFFFDFDF FFF0FFF0
ACCM: 0F 0F0F0F0F 0F0F0F0F
N6.C1.D0.R1: CheckMCTest: result = 0x3FE00
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: DD FFFFDFDF FFF0FFF0
ACCM: 00 0000000B 0B000000
N6.C1.D0.R1: CheckMCTest: passed
ACCM: F0 F0F0F0F0 F0F0F0F0
N2.C3.D0.R0: CheckMCTest: result = 0x3FFFF
ACCM: 00 0000000B 0B000000
N6.C1.D0.R1: CheckMCTest: passed
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: D0 00D0D0D0 00000000
N4.C2.D1.R1: CheckMCTest: result = 0x1FF
N6.C1.D0.R1.S09: Offset Found: RdPtrOffsetDqs = 007
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: D0 00D0D0D0 00000000
ACCM: 0F 0F0F0F0F 0F0F0F0F
N6.C1.D0.R1.S10: Offset Found: RdPtrOffsetDqs = 007
N0.C1.D0.R1: CheckMCTest: result = 0x3FE00
ACCM: D0 F0F0D0D0 F0F0F0F0
ACCM: 0F 0F0F0F0F 0F0F0F0F
N6.C1.D0.R1.S11: Offset Found: RdPtrOffsetDqs = 007
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: D0 F0F0D0D0 F0F0F0F0
ACCM: 00 0000000F 0F000000
N6.C1.D0.R1.S12: Offset Found: RdPtrOffsetDqs = 007
ACCM: F0 F0F0F0F0 F0F0F0F0
N2.C3.D0.R0: CheckMCTest: result = 0x3FE00
ACCM: 00 0000000F 0F000000
N6.C1.D0.R1.S13: Offset Found: RdPtrOffsetDqs = 006
ACCM: B0 0000B0B0 B0000000
ACCM: D0 00D0D0D0 00000000
N4.C2.D1.R1: CheckMCTest: result = 0x1FF
N6.C1.D0.R1.S14: Offset Found: RdPtrOffsetDqs = 006
ACCM: B0 0000B0B0 B0000000
ACCM: D0 00D0D0D0 00000000
N4.C2.D1.R1: CheckMCTest: passed
N6.C1.D0.R1.S15: Offset Found: RdPtrOffsetDqs = 007
N0.C1.D0.R1: CheckMCTest: result = 0x3FE00
ACCM: D0 F0F0D0D0 F0F0F0F0
N4.C2.D1.R1: CheckMCTest: passed
N6.C1.D0.R1.S16: Offset Found: RdPtrOffsetDqs = 007
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: D0 F0F0D0D0 F0F0F0F0
N4.C2.D1.R1.S00: Offset Found: RdPtrOffsetDqs = 007
N6.C1.D0.R1.S17: Offset Found: RdPtrOffsetDqs = 006
ACCM: F0 F0F0F0F0 F0F0F0F0
N2.C3.D0.R0: CheckMCTest: result = 0x3FE00
N4.C2.D1.R1.S01: Offset Found: RdPtrOffsetDqs = 007
N6.C1.D1.R0: Write Training Coarse, lower nibbles / bytes
ACCM: F0 0000F0F0 F0000000
N2.C3.D0.R0.S00: Offset Found: RdPtrOffsetDqs = 007
N4.C2.D1.R1.S02: Offset Found: RdPtrOffsetDqs = 007
N6.C1.D1.R0.S00: Dq Delay estimate: 471
ACCM: F0 0000F0F0 F0000000
N2.C3.D0.R0.S01: Offset Found: RdPtrOffsetDqs = 007
N4.C2.D1.R1.S03: Offset Found: RdPtrOffsetDqs = 007
N6.C1.D1.R0.S01: Dq Delay estimate: 454
N0.C1.D0.R1: CheckMCTest: result = 0x3FE00
N2.C3.D0.R0.S02: Offset Found: RdPtrOffsetDqs = 007
N4.C2.D1.R1.S04: Offset Found: RdPtrOffsetDqs = 006
N6.C1.D1.R0.S02: Dq Delay estimate: 446
N0.C1.D0.R1: CheckMCTest: passed
N2.C3.D0.R0.S03: Offset Found: RdPtrOffsetDqs = 007
N4.C2.D1.R1.S05: Offset Found: RdPtrOffsetDqs = 007
N6.C1.D1.R0.S03: Dq Delay estimate: 430
N0.C1.D0.R1: CheckMCTest: passed
N2.C3.D0.R0.S04: Offset Found: RdPtrOffsetDqs = 006
N4.C2.D1.R1.S06: Offset Found: RdPtrOffsetDqs = 006
N6.C1.D1.R0.S04: Dq Delay estimate: 396
N0.C1.D0.R1.S09: Offset Found: RdPtrOffsetDqs = 007
N2.C3.D0.R0.S05: Offset Found: RdPtrOffsetDqs = 006
N4.C2.D1.R1.S07: Offset Found: RdPtrOffsetDqs = 007
N6.C1.D1.R0.S05: Dq Delay estimate: 411
N0.C1.D0.R1.S10: Offset Found: RdPtrOffsetDqs = 007
N2.C3.D0.R0.S06: Offset Found: RdPtrOffsetDqs = 007
N4.C2.D1.R1.S08: Offset Found: RdPtrOffsetDqs = 006
N6.C1.D1.R0.S06: Dq Delay estimate: 423
N0.C1.D0.R1.S11: Offset Found: RdPtrOffsetDqs = 007
N2.C3.D0.R0.S07: Offset Found: RdPtrOffsetDqs = 007
N4.C2.D1.R1: Write Training Coarse, upper nibbles
N6.C1.D1.R0.S07: Dq Delay estimate: 440
N0.C1.D0.R1.S12: Offset Found: RdPtrOffsetDqs = 007
N2.C3.D0.R0.S08: Offset Found: RdPtrOffsetDqs = 006
N4.C2.D1.R1.S09: Dq Delay estimate: 462
N6.C1.D1.R0.S08: Dq Delay estimate: 411
N0.C1.D0.R1.S13: Offset Found: RdPtrOffsetDqs = 006
N2.C3.D0.R0: Write Training Coarse, upper nibbles
N4.C2.D1.R1.S10: Dq Delay estimate: 448
ACCM: 0F 0FDF0F0F 0F0F0F0F
N0.C1.D0.R1.S14: Offset Found: RdPtrOffsetDqs = 006
N2.C3.D0.R0.S09: Dq Delay estimate: 468
N4.C2.D1.R1.S11: Dq Delay estimate: 440
ACCM: 0F 0FDF0F0F 0F0F0F0F
N0.C1.D0.R1.S15: Offset Found: RdPtrOffsetDqs = 007
N2.C3.D0.R0.S10: Dq Delay estimate: 457
N4.C2.D1.R1.S12: Dq Delay estimate: 425
ACCM: 0F 0FDF0F0F 0F0F0F0F
N0.C1.D0.R1.S16: Offset Found: RdPtrOffsetDqs = 007
N2.C3.D0.R0.S11: Dq Delay estimate: 440
N4.C2.D1.R1.S13: Dq Delay estimate: 383
ACCM: 0F FFFF0F0F FFFFFF0F
N0.C1.D0.R1.S17: Offset Found: RdPtrOffsetDqs = 006
N2.C3.D0.R0.S12: Dq Delay estimate: 428
N4.C2.D1.R1.S14: Dq Delay estimate: 408
N6.C1.D1.R0: CheckMCTest: result = 0x19DFF
N0.C1.D1.R0: Write Training Coarse, lower nibbles / bytes
N2.C3.D0.R0.S13: Dq Delay estimate: 393
N4.C2.D1.R1.S15: Dq Delay estimate: 408
ACCM: 0F 0FFF0F0F 0F0F0F0F
N0.C1.D1.R0.S00: Dq Delay estimate: 475
N2.C3.D0.R0.S14: Dq Delay estimate: 406
N4.C2.D1.R1.S16: Dq Delay estimate: 428
ACCM: 0F 0FFF0F0F 0F0F0F0F
N0.C1.D1.R0.S01: Dq Delay estimate: 456
N2.C3.D0.R0.S15: Dq Delay estimate: 420
N4.C2.D1.R1.S17: Dq Delay estimate: 395
ACCM: 0F 0FFF0F0F 0F0F0F0F
N0.C1.D1.R0.S02: Dq Delay estimate: 447
N2.C3.D0.R0.S16: Dq Delay estimate: 434
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: 0F FFFF0F0F FFFFFF0F
N0.C1.D1.R0.S03: Dq Delay estimate: 437
N2.C3.D0.R0.S17: Dq Delay estimate: 413
ACCM: F0 F0F0F0F0 F0F0F0F0
N6.C1.D1.R0: CheckMCTest: result = 0x19DFF
N0.C1.D1.R0.S04: Dq Delay estimate: 401
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: 0F 0FDF0F0F 0F0F0F0F
N0.C1.D1.R0.S05: Dq Delay estimate: 414
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: 0F 0FDF0F0F 0F0F0F0F
N0.C1.D1.R0.S06: Dq Delay estimate: 431
ACCM: F0 F0F0F0F0 F0F0F0F0
N4.C2.D1.R1: CheckMCTest: result = 0x3FE00
ACCM: 00 0BDB0B0B 0B0B0B0B
N0.C1.D1.R0.S07: Dq Delay estimate: 447
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: 00 FBFB0B0B FBFBFB0B
N0.C1.D1.R0.S08: Dq Delay estimate: 416
N2.C3.D0.R0: CheckMCTest: result = 0x3FE00
ACCM: F0 F0F0F0F0 F0F0F0F0
N6.C1.D1.R0: CheckMCTest: result = 0x19DFF
ACCM: 0F 0F0F0F0F 0F0F0F0F
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: 0F 0FFF0F0F 0F0F0F0F
ACCM: 0F 0F0F0F0F 0F0F0F0F
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: 0F 0FFF0F0F 0F0F0F0F
ACCM: 0F 0F0F0F0F 0F0F0F0F
ACCM: F0 F0F0F0F0 F0F0F0F0
N4.C2.D1.R1: CheckMCTest: result = 0x3FE00
ACCM: 00 0FFF0F0F 0F0F0F0F
ACCM: 0F FFFF0F0F FFFFFF0F
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: 00 FFFF0F0F FFFFFF0F
N0.C1.D1.R0: CheckMCTest: result = 0x19DFF
N2.C3.D0.R0: CheckMCTest: result = 0x3FE00
ACCM: F0 F0F0F0F0 F0F0F0F0
N6.C1.D1.R0: CheckMCTest: result = 0x19DFF
ACCM: 0F 0F0F0F0F 0F0F0F0F
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: 00 B0B0B000 00000000
ACCM: 00 00D00000 00000000
ACCM: 0F 0F0F0F0F 0F0F0F0F
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: 00 B0B0B000 00000000
ACCM: 00 00D00000 00000000
ACCM: 0F 0F0F0F0F 0F0F0F0F
ACCM: 00 B0B0B0B0 0000B0B0
N4.C2.D1.R1: CheckMCTest: result = 0x3FE00
ACCM: 00 00D00000 00000000
ACCM: 0F FFFF0F0F FFFFFF0F
ACCM: 00 B0B0B0B0 0000B0B0
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: 00 F0F00000 F0F0F000
N0.C1.D1.R0: CheckMCTest: result = 0x19DFF
N2.C3.D0.R0: CheckMCTest: result = 0x3FE00
ACCM: F0 F0F0F0F0 F0F0F0F0
N6.C1.D1.R0: CheckMCTest: result = 0x19C00
ACCM: 0F 0F0F0F0F 0F0F0F0F
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: 00 F0F0F000 00000000
ACCM: 00 00F00000 00000000
ACCM: 0F 0F0F0F0F 0F0F0F0F
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: 00 F0F0F000 00000000
ACCM: 00 00F00000 00000000
ACCM: 00 0B0B000B 0B000B00
ACCM: 00 F0F0F0F0 0000F0F0
N4.C2.D1.R1: CheckMCTest: result = 0x3FE00
ACCM: 00 00F00000 00000000
ACCM: 00 FBFB000B FBF0FB00
ACCM: 00 F0F0F0F0 0000F0F0
N4.C2.D1.R1: CheckMCTest: passed
ACCM: 00 F0F00000 F0F0F000
N0.C1.D1.R0: CheckMCTest: result = 0x19DFF
N2.C3.D0.R0: CheckMCTest: result = 0x3FE00
N4.C2.D1.R1: CheckMCTest: passed
N6.C1.D1.R0: CheckMCTest: result = 0x19C00
ACCM: 0F 0F0F0F0F 0F0F0F0F
N2.C3.D0.R0: CheckMCTest: passed
N4.C2.D1.R1.S09: Offset Found: RdPtrOffsetDqs = 007
N6.C1.D1.R0.S00: Offset Found: RdPtrOffsetDqs = 007
ACCM: 0F 0F0F0F0F 0F0F0F0F
N2.C3.D0.R0: CheckMCTest: passed
N4.C2.D1.R1.S10: Offset Found: RdPtrOffsetDqs = 007
N6.C1.D1.R0.S01: Offset Found: RdPtrOffsetDqs = 007
ACCM: 00 0F0F000F 0F0D0F00
N2.C3.D0.R0.S09: Offset Found: RdPtrOffsetDqs = 007
N4.C2.D1.R1.S11: Offset Found: RdPtrOffsetDqs = 007
N6.C1.D1.R0.S02: Offset Found: RdPtrOffsetDqs = 007
ACCM: 00 FFFF000F FFFDFF00
N2.C3.D0.R0.S10: Offset Found: RdPtrOffsetDqs = 007
N4.C2.D1.R1.S12: Offset Found: RdPtrOffsetDqs = 007
N6.C1.D1.R0.S03: Offset Found: RdPtrOffsetDqs = 007
N0.C1.D1.R0: CheckMCTest: result = 0x19DFF
N2.C3.D0.R0.S11: Offset Found: RdPtrOffsetDqs = 007
N4.C2.D1.R1.S13: Offset Found: RdPtrOffsetDqs = 006
N6.C1.D1.R0.S04: Offset Found: RdPtrOffsetDqs = 006
ACCM: 00 00000000 00000000
N2.C3.D0.R0.S12: Offset Found: RdPtrOffsetDqs = 007
N4.C2.D1.R1.S14: Offset Found: RdPtrOffsetDqs = 007
N6.C1.D1.R0.S05: Offset Found: RdPtrOffsetDqs = 006
ACCM: 00 00000000 00000000
N2.C3.D0.R0.S13: Offset Found: RdPtrOffsetDqs = 006
N4.C2.D1.R1.S15: Offset Found: RdPtrOffsetDqs = 006
N6.C1.D1.R0.S06: Offset Found: RdPtrOffsetDqs = 007
ACCM: 00 00000000 00000000
N2.C3.D0.R0.S14: Offset Found: RdPtrOffsetDqs = 006
N4.C2.D1.R1.S16: Offset Found: RdPtrOffsetDqs = 007
N6.C1.D1.R0.S07: Offset Found: RdPtrOffsetDqs = 007
ACCM: 00 F0F00000 F0F0F000
N2.C3.D0.R0.S15: Offset Found: RdPtrOffsetDqs = 007
N4.C2.D1.R1.S17: Offset Found: RdPtrOffsetDqs = 006
N6.C1.D1.R0.S08: Offset Found: RdPtrOffsetDqs = 006
N0.C1.D1.R0: CheckMCTest: result = 0x19C00
N2.C3.D0.R0.S16: Offset Found: RdPtrOffsetDqs = 007
N4.C2: Calculating Optimimum DQS Values
N6.C1.D1.R0: Write Training Coarse, upper nibbles
ACCM: 00 00000000 00000000
N2.C3.D0.R0.S17: Offset Found: RdPtrOffsetDqs = 006
N4.C2.D0.R0.S00: Total Delay in PI ticks: TxDQS = 1012, TxDQ = 976
N6.C1.D1.R0.S09: Dq Delay estimate: 469
ACCM: 00 00000000 00000000
N2.C3.D0.R1: Write Training Coarse, lower nibbles / bytes
N4.C2.D0.R0.S01: Total Delay in PI ticks: TxDQS = 998, TxDQ = 961
N6.C1.D1.R0.S10: Dq Delay estimate: 455
ACCM: 00 00000000 00000000
N2.C3.D0.R1.S00: Dq Delay estimate: 461
N4.C2.D0.R0.S02: Total Delay in PI ticks: TxDQS = 989, TxDQ = 953
N6.C1.D1.R0.S11: Dq Delay estimate: 448
ACCM: 00 F0F00000 F0F0F000
N2.C3.D0.R1.S01: Dq Delay estimate: 446
N4.C2.D0.R0.S03: Total Delay in PI ticks: TxDQS = 969, TxDQ = 934
N6.C1.D1.R0.S12: Dq Delay estimate: 432
N0.C1.D1.R0: CheckMCTest: result = 0x19C00
N2.C3.D0.R1.S02: Dq Delay estimate: 433
N4.C2.D0.R0.S04: Total Delay in PI ticks: TxDQS = 927, TxDQ = 891
N6.C1.D1.R0.S13: Dq Delay estimate: 397
N0.C1.D1.R0.S00: Offset Found: RdPtrOffsetDqs = 007
N2.C3.D0.R1.S03: Dq Delay estimate: 420
N4.C2.D0.R0.S05: Total Delay in PI ticks: TxDQS = 958, TxDQ = 921
N6.C1.D1.R0.S14: Dq Delay estimate: 409
N0.C1.D1.R0.S01: Offset Found: RdPtrOffsetDqs = 007
N2.C3.D0.R1.S04: Dq Delay estimate: 386
N4.C2.D0.R0.S06: Total Delay in PI ticks: TxDQS = 959, TxDQ = 921
N6.C1.D1.R0.S15: Dq Delay estimate: 422
N0.C1.D1.R0.S02: Offset Found: RdPtrOffsetDqs = 007
N2.C3.D0.R1.S05: Dq Delay estimate: 398
N4.C2.D0.R0.S07: Total Delay in PI ticks: TxDQS = 975, TxDQ = 938
N6.C1.D1.R0.S16: Dq Delay estimate: 444
N0.C1.D1.R0.S03: Offset Found: RdPtrOffsetDqs = 007
N2.C3.D0.R1.S06: Dq Delay estimate: 412
N4.C2.D0.R0.S08: Total Delay in PI ticks: TxDQS = 951, TxDQ = 913
N6.C1.D1.R0.S17: Dq Delay estimate: 411
N0.C1.D1.R0.S04: Offset Found: RdPtrOffsetDqs = 006
N2.C3.D0.R1.S07: Dq Delay estimate: 429
N4.C2.D0.R0.S09: Total Delay in PI ticks: TxDQS = 1015, TxDQ = 979
ACCM: F0 F0F0F0F0 F0F0F0F0
N0.C1.D1.R0.S05: Offset Found: RdPtrOffsetDqs = 007
N2.C3.D0.R1.S08: Dq Delay estimate: 404
N4.C2.D0.R0.S10: Total Delay in PI ticks: TxDQS = 1001, TxDQ = 962
ACCM: F0 F0F0F0F0 F0F0F0F0
N0.C1.D1.R0.S06: Offset Found: RdPtrOffsetDqs = 007
ACCM: 0F 0F0F0F0F 0F0F0F0F
N4.C2.D0.R0.S11: Total Delay in PI ticks: TxDQS = 989, TxDQ = 955
ACCM: F0 F0F0F0F0 F0F0F0F0
N0.C1.D1.R0.S07: Offset Found: RdPtrOffsetDqs = 007
ACCM: 0F 0F0F0F0F 0F0F0F0F
N4.C2.D0.R0.S12: Total Delay in PI ticks: TxDQS = 970, TxDQ = 934
ACCM: F0 F0F0F0F0 F0F0F0F0
N0.C1.D1.R0.S08: Offset Found: RdPtrOffsetDqs = 007
ACCM: 0F 0F0F0F0F 0F0F0F0F
N4.C2.D0.R0.S13: Total Delay in PI ticks: TxDQS = 930, TxDQ = 897
N6.C1.D1.R0: CheckMCTest: result = 0x3FE00
N0.C1.D1.R0: Write Training Coarse, upper nibbles
ACCM: 0F 0F0F0F0F 0F0F0F0F
N4.C2.D0.R0.S14: Total Delay in PI ticks: TxDQS = 958, TxDQ = 919
ACCM: F0 F0F0F0F0 F0F0F0F0
N0.C1.D1.R0.S09: Dq Delay estimate: 475
N2.C3.D0.R1: CheckMCTest: result = 0x1FF
N4.C2.D0.R0.S15: Total Delay in PI ticks: TxDQS = 958, TxDQ = 921
ACCM: F0 F0F0F0F0 F0F0F0F0
N0.C1.D1.R0.S10: Dq Delay estimate: 456
ACCM: 0F 0F0F0F0F 0F0F0F0F
N4.C2.D0.R0.S16: Total Delay in PI ticks: TxDQS = 976, TxDQ = 941
ACCM: F0 F0F0F0F0 F0F0F0F0
N0.C1.D1.R0.S11: Dq Delay estimate: 450
ACCM: 0F 0F0F0F0F 0F0F0F0F
N4.C2.D0.R0.S17: Total Delay in PI ticks: TxDQS = 947, TxDQ = 911
ACCM: F0 F0F0F0F0 F0F0F0F0
N0.C1.D1.R0.S12: Dq Delay estimate: 437
ACCM: 0F 0F0F0F0F 0F0F0F0F
N4.C2.D0.R1.S00: Total Delay in PI ticks: TxDQS = 1007, TxDQ = 971
N6.C1.D1.R0: CheckMCTest: result = 0x3FE00
N0.C1.D1.R0.S13: Dq Delay estimate: 400
ACCM: 0F 0F0F0F0F 0F0F0F0F
N4.C2.D0.R1.S01: Total Delay in PI ticks: TxDQS = 990, TxDQ = 953
ACCM: F0 F0F0F0F0 F0F0F0F0
N0.C1.D1.R0.S14: Dq Delay estimate: 415
N2.C3.D0.R1: CheckMCTest: result = 0x1FF
N4.C2.D0.R1.S02: Total Delay in PI ticks: TxDQS = 981, TxDQ = 945
ACCM: F0 F0F0F0F0 F0F0F0F0
N0.C1.D1.R0.S15: Dq Delay estimate: 430
ACCM: 0F 0F0F0F0F 0F0F0F0F
N4.C2.D0.R1.S03: Total Delay in PI ticks: TxDQS = 966, TxDQ = 930
ACCM: 00 B0B000B0 B00000B0
N0.C1.D1.R0.S16: Dq Delay estimate: 447
ACCM: 0F 0F0F0F0F 0F0F0F0F
N4.C2.D0.R1.S04: Total Delay in PI ticks: TxDQS = 923, TxDQ = 887
ACCM: 00 B0B000B0 B00000B0
N0.C1.D1.R0.S17: Dq Delay estimate: 415
ACCM: 00 00000000 0000000B
N4.C2.D0.R1.S05: Total Delay in PI ticks: TxDQS = 951, TxDQ = 914
N6.C1.D1.R0: CheckMCTest: result = 0x3FE00
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: 00 00000000 0000000B
N4.C2.D0.R1.S06: Total Delay in PI ticks: TxDQS = 948, TxDQ = 910
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: F0 F0F0F0F0 F0F0F0F0
N2.C3.D0.R1: CheckMCTest: result = 0x1FF
N4.C2.D0.R1.S07: Total Delay in PI ticks: TxDQS = 971, TxDQ = 934
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: 0F 0F0F0F0F 0F0F0F0F
N4.C2.D0.R1.S08: Total Delay in PI ticks: TxDQS = 942, TxDQ = 904
ACCM: 00 F0F000F0 F00000F0
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: 0F 0F0F0F0F 0F0F0F0F
N4.C2.D0.R1.S09: Total Delay in PI ticks: TxDQS = 1007, TxDQ = 971
ACCM: 00 F0F000F0 F00000F0
N0.C1.D1.R0: CheckMCTest: result = 0x3FE00
ACCM: 00 00000000 0000000F
N4.C2.D0.R1.S10: Total Delay in PI ticks: TxDQS = 993, TxDQ = 955
N6.C1.D1.R0: CheckMCTest: result = 0x3FE00
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: 00 00000000 0000000F
N4.C2.D0.R1.S11: Total Delay in PI ticks: TxDQS = 981, TxDQ = 947
N6.C1.D1.R0: CheckMCTest: passed
ACCM: F0 F0F0F0F0 F0F0F0F0
N2.C3.D0.R1: CheckMCTest: result = 0x1FF
N4.C2.D0.R1.S12: Total Delay in PI ticks: TxDQS = 967, TxDQ = 931
N6.C1.D1.R0: CheckMCTest: passed
ACCM: F0 F0F0F0F0 F0F0F0F0
N2.C3.D0.R1: CheckMCTest: passed
N4.C2.D0.R1.S13: Total Delay in PI ticks: TxDQS = 924, TxDQ = 892
N6.C1.D1.R0.S09: Offset Found: RdPtrOffsetDqs = 007
ACCM: F0 F0F0F0F0 F0F0F0F0
N2.C3.D0.R1: CheckMCTest: passed
N4.C2.D0.R1.S14: Total Delay in PI ticks: TxDQS = 952, TxDQ = 914
N6.C1.D1.R0.S10: Offset Found: RdPtrOffsetDqs = 007
N0.C1.D1.R0: CheckMCTest: result = 0x3FE00
N2.C3.D0.R1.S00: Offset Found: RdPtrOffsetDqs = 007
N4.C2.D0.R1.S15: Total Delay in PI ticks: TxDQS = 949, TxDQ = 912
N6.C1.D1.R0.S11: Offset Found: RdPtrOffsetDqs = 007
ACCM: F0 F0F0F0F0 F0F0F0F0
N2.C3.D0.R1.S01: Offset Found: RdPtrOffsetDqs = 007
N4.C2.D0.R1.S16: Total Delay in PI ticks: TxDQS = 969, TxDQ = 933
N6.C1.D1.R0.S12: Offset Found: RdPtrOffsetDqs = 007
ACCM: F0 F0F0F0F0 F0F0F0F0
N2.C3.D0.R1.S02: Offset Found: RdPtrOffsetDqs = 007
N4.C2.D0.R1.S17: Total Delay in PI ticks: TxDQS = 941, TxDQ = 905
N6.C1.D1.R0.S13: Offset Found: RdPtrOffsetDqs = 006
ACCM: B0 00B0B0B0 B0000000
N2.C3.D0.R1.S03: Offset Found: RdPtrOffsetDqs = 007
N4.C2.D1.R0.S00: Total Delay in PI ticks: TxDQS = 1016, TxDQ = 978
N6.C1.D1.R0.S14: Offset Found: RdPtrOffsetDqs = 006
ACCM: B0 00B0B0B0 B0000000
N2.C3.D0.R1.S04: Offset Found: RdPtrOffsetDqs = 006
N4.C2.D1.R0.S01: Total Delay in PI ticks: TxDQS = 1001, TxDQ = 962
N6.C1.D1.R0.S15: Offset Found: RdPtrOffsetDqs = 007
N0.C1.D1.R0: CheckMCTest: result = 0x3FE00
N2.C3.D0.R1.S05: Offset Found: RdPtrOffsetDqs = 006
N4.C2.D1.R0.S02: Total Delay in PI ticks: TxDQS = 992, TxDQ = 955
N6.C1.D1.R0.S16: Offset Found: RdPtrOffsetDqs = 007
ACCM: F0 F0F0F0F0 F0F0F0F0
N2.C3.D0.R1.S06: Offset Found: RdPtrOffsetDqs = 007
N4.C2.D1.R0.S03: Total Delay in PI ticks: TxDQS = 976, TxDQ = 939
N6.C1.D1.R0.S17: Offset Found: RdPtrOffsetDqs = 006
ACCM: F0 F0F0F0F0 F0F0F0F0
N2.C3.D0.R1.S07: Offset Found: RdPtrOffsetDqs = 007
N4.C2.D1.R0.S04: Total Delay in PI ticks: TxDQS = 933, TxDQ = 896
N6.C1.D1.R1: Write Training Coarse, lower nibbles / bytes
ACCM: F0 00F0F0F0 F0000000
N2.C3.D0.R1.S08: Offset Found: RdPtrOffsetDqs = 006
N4.C2.D1.R0.S05: Total Delay in PI ticks: TxDQS = 962, TxDQ = 924
N6.C1.D1.R1.S00: Dq Delay estimate: 467
ACCM: F0 00F0F0F0 F0000000
N2.C3.D0.R1: Write Training Coarse, upper nibbles
N4.C2.D1.R0.S06: Total Delay in PI ticks: TxDQS = 961, TxDQ = 921
N6.C1.D1.R1.S01: Dq Delay estimate: 449
N0.C1.D1.R0: CheckMCTest: result = 0x3FE00
N2.C3.D0.R1.S09: Dq Delay estimate: 460
N4.C2.D1.R0.S07: Total Delay in PI ticks: TxDQS = 979, TxDQ = 940
N6.C1.D1.R1.S02: Dq Delay estimate: 441
N0.C1.D1.R0: CheckMCTest: passed
N2.C3.D0.R1.S10: Dq Delay estimate: 447
N4.C2.D1.R0.S08: Total Delay in PI ticks: TxDQS = 951, TxDQ = 912
N6.C1.D1.R1.S03: Dq Delay estimate: 426
N0.C1.D1.R0: CheckMCTest: passed
N2.C3.D0.R1.S11: Dq Delay estimate: 435
N4.C2.D1.R0.S09: Total Delay in PI ticks: TxDQS = 1017, TxDQ = 980
N6.C1.D1.R1.S04: Dq Delay estimate: 391
N0.C1.D1.R0.S09: Offset Found: RdPtrOffsetDqs = 007
N2.C3.D0.R1.S12: Dq Delay estimate: 423
N4.C2.D1.R0.S10: Total Delay in PI ticks: TxDQS = 1003, TxDQ = 962
N6.C1.D1.R1.S05: Dq Delay estimate: 407
N0.C1.D1.R0.S10: Offset Found: RdPtrOffsetDqs = 007
N2.C3.D0.R1.S13: Dq Delay estimate: 387
N4.C2.D1.R0.S11: Total Delay in PI ticks: TxDQS = 992, TxDQ = 956
N6.C1.D1.R1.S06: Dq Delay estimate: 417
N0.C1.D1.R0.S11: Offset Found: RdPtrOffsetDqs = 007
N2.C3.D0.R1.S14: Dq Delay estimate: 399
N4.C2.D1.R0.S12: Total Delay in PI ticks: TxDQS = 976, TxDQ = 938
N6.C1.D1.R1.S07: Dq Delay estimate: 437
N0.C1.D1.R0.S12: Offset Found: RdPtrOffsetDqs = 007
N2.C3.D0.R1.S15: Dq Delay estimate: 413
N4.C2.D1.R0.S13: Total Delay in PI ticks: TxDQS = 934, TxDQ = 898
N6.C1.D1.R1.S08: Dq Delay estimate: 405
N0.C1.D1.R0.S13: Offset Found: RdPtrOffsetDqs = 006
N2.C3.D0.R1.S16: Dq Delay estimate: 429
N4.C2.D1.R0.S14: Total Delay in PI ticks: TxDQS = 961, TxDQ = 921
ACCM: 0F 0F0F0F0F 0F0F0F0F
N0.C1.D1.R0.S14: Offset Found: RdPtrOffsetDqs = 007
N2.C3.D0.R1.S17: Dq Delay estimate: 405
N4.C2.D1.R0.S15: Total Delay in PI ticks: TxDQS = 961, TxDQ = 922
ACCM: 0F 0F0F0F0F 0F0F0F0F
N0.C1.D1.R0.S15: Offset Found: RdPtrOffsetDqs = 007
ACCM: F0 F0F0F0F0 F0F0F0F0
N4.C2.D1.R0.S16: Total Delay in PI ticks: TxDQS = 981, TxDQ = 944
ACCM: 0F 0F0F0F0F 0F0F0F0F
N0.C1.D1.R0.S16: Offset Found: RdPtrOffsetDqs = 007
ACCM: F0 F0F0F0F0 F0F0F0F0
N4.C2.D1.R0.S17: Total Delay in PI ticks: TxDQS = 950, TxDQ = 912
ACCM: 0F 0F0F0F0F 0F0F0F0F
N0.C1.D1.R0.S17: Offset Found: RdPtrOffsetDqs = 007
ACCM: F0 F0F0F0F0 F0F0F0F0
N4.C2.D1.R1.S00: Total Delay in PI ticks: TxDQS = 1011, TxDQ = 974
N6.C1.D1.R1: CheckMCTest: result = 0x1FF
N0.C1.D1.R1: Write Training Coarse, lower nibbles / bytes
ACCM: F0 F0F0F0F0 F0F0F0F0
N4.C2.D1.R1.S01: Total Delay in PI ticks: TxDQS = 998, TxDQ = 959
ACCM: 0F 0F0F0F0F 0F0F0F0F
N0.C1.D1.R1.S00: Dq Delay estimate: 471
N2.C3.D0.R1: CheckMCTest: result = 0x3FE00
N4.C2.D1.R1.S02: Total Delay in PI ticks: TxDQS = 988, TxDQ = 951
ACCM: 0F 0F0F0F0F 0F0F0F0F
N0.C1.D1.R1.S01: Dq Delay estimate: 454
ACCM: F0 F0F0F0F0 F0F0F0F0
N4.C2.D1.R1.S03: Total Delay in PI ticks: TxDQS = 974, TxDQ = 938
ACCM: 0F 0F0F0F0F 0F0F0F0F
N0.C1.D1.R1.S02: Dq Delay estimate: 446
ACCM: F0 F0F0F0F0 F0F0F0F0
N4.C2.D1.R1.S04: Total Delay in PI ticks: TxDQS = 931, TxDQ = 894
ACCM: 0F 0F0F0F0F 0F0F0F0F
N0.C1.D1.R1.S03: Dq Delay estimate: 433
ACCM: F0 F0F0F0F0 F0F0F0F0
N4.C2.D1.R1.S05: Total Delay in PI ticks: TxDQS = 960, TxDQ = 922
N6.C1.D1.R1: CheckMCTest: result = 0x1FF
N0.C1.D1.R1.S04: Dq Delay estimate: 398
ACCM: F0 F0F0F0F0 F0F0F0F0
N4.C2.D1.R1.S06: Total Delay in PI ticks: TxDQS = 955, TxDQ = 915
ACCM: 0F 0F0F0F0F 0F0F0F0F
N0.C1.D1.R1.S05: Dq Delay estimate: 411
N2.C3.D0.R1: CheckMCTest: result = 0x3FE00
N4.C2.D1.R1.S07: Total Delay in PI ticks: TxDQS = 977, TxDQ = 938
ACCM: 0F 0F0F0F0F 0F0F0F0F
N0.C1.D1.R1.S06: Dq Delay estimate: 422
ACCM: F0 F0F0F0F0 F0F0F0F0
N4.C2.D1.R1.S08: Total Delay in PI ticks: TxDQS = 946, TxDQ = 906
ACCM: 00 00000000 0A0B0000
N0.C1.D1.R1.S07: Dq Delay estimate: 446
ACCM: F0 F0F0F0F0 F0F0F0F0
N4.C2.D1.R1.S09: Total Delay in PI ticks: TxDQS = 1011, TxDQ = 974
ACCM: 00 00000000 0A0B0000
N0.C1.D1.R1.S08: Dq Delay estimate: 410
ACCM: B0 000000B0 0000B000
N4.C2.D1.R1.S10: Total Delay in PI ticks: TxDQS = 1001, TxDQ = 960
N6.C1.D1.R1: CheckMCTest: result = 0x1FF
ACCM: 0F 0F0F0F0F 0F0F0F0F
ACCM: B0 000000B0 0000B000
N4.C2.D1.R1.S11: Total Delay in PI ticks: TxDQS = 988, TxDQ = 952
ACCM: 0F 0F0F0F0F 0F0F0F0F
ACCM: 0F 0F0F0F0F 0F0F0F0F
N2.C3.D0.R1: CheckMCTest: result = 0x3FE00
N4.C2.D1.R1.S12: Total Delay in PI ticks: TxDQS = 974, TxDQ = 937
ACCM: 0F 0F0F0F0F 0F0F0F0F
ACCM: 0F 0F0F0F0F 0F0F0F0F
ACCM: F0 F0F0F0F0 F0F0F0F0
N4.C2.D1.R1.S13: Total Delay in PI ticks: TxDQS = 931, TxDQ = 895
ACCM: 00 00000000 0E0F0000
ACCM: 0F 0F0F0F0F 0F0F0F0F
ACCM: F0 F0F0F0F0 F0F0F0F0
N4.C2.D1.R1.S14: Total Delay in PI ticks: TxDQS = 960, TxDQ = 920
ACCM: 00 00000000 0E0F0000
N0.C1.D1.R1: CheckMCTest: result = 0x1FF
ACCM: F0 000000F0 0000F000
N4.C2.D1.R1.S15: Total Delay in PI ticks: TxDQS = 959, TxDQ = 920
N6.C1.D1.R1: CheckMCTest: result = 0x1FF
ACCM: 0F 0F0F0F0F 0F0F0F0F
ACCM: F0 000000F0 0000F000
N4.C2.D1.R1.S16: Total Delay in PI ticks: TxDQS = 977, TxDQ = 940
N6.C1.D1.R1: CheckMCTest: passed
ACCM: 0F 0F0F0F0F 0F0F0F0F
N2.C3.D0.R1: CheckMCTest: result = 0x3FE00
N4.C2.D1.R1.S17: Total Delay in PI ticks: TxDQS = 944, TxDQ = 907
N6.C1.D1.R1: CheckMCTest: passed
ACCM: 0F 0F0F0F0F 0F0F0F0F
N2.C3.D0.R1: CheckMCTest: passed
N4.C3.D0.R0: Write Training Coarse, lower nibbles / bytes
N6.C1.D1.R1.S00: Offset Found: RdPtrOffsetDqs = 007
ACCM: 0F 0F0F0F0F 0F0F0F0F
N2.C3.D0.R1: CheckMCTest: passed
N4.C3.D0.R0.S00: Dq Delay estimate: 347
N6.C1.D1.R1.S01: Offset Found: RdPtrOffsetDqs = 007
N0.C1.D1.R1: CheckMCTest: result = 0x1FF
N2.C3.D0.R1.S09: Offset Found: RdPtrOffsetDqs = 007
N4.C3.D0.R0.S01: Dq Delay estimate: 456
N6.C1.D1.R1.S02: Offset Found: RdPtrOffsetDqs = 007
ACCM: 0F 0F0F0F0F 0F0F0F0F
N2.C3.D0.R1.S10: Offset Found: RdPtrOffsetDqs = 007
N4.C3.D0.R0.S02: Dq Delay estimate: 450
N6.C1.D1.R1.S03: Offset Found: RdPtrOffsetDqs = 007
ACCM: 0F 0F0F0F0F 0F0F0F0F
N2.C3.D0.R1.S11: Offset Found: RdPtrOffsetDqs = 007
N4.C3.D0.R0.S03: Dq Delay estimate: 433
N6.C1.D1.R1.S04: Offset Found: RdPtrOffsetDqs = 006
ACCM: 0B 0B0B000B 00000000
N2.C3.D0.R1.S12: Offset Found: RdPtrOffsetDqs = 007
N4.C3.D0.R0.S04: Dq Delay estimate: 395
N6.C1.D1.R1.S05: Offset Found: RdPtrOffsetDqs = 006
ACCM: 0B 0B0B000B 00000000
N2.C3.D0.R1.S13: Offset Found: RdPtrOffsetDqs = 006
N4.C3.D0.R0.S05: Dq Delay estimate: 411
N6.C1.D1.R1.S06: Offset Found: RdPtrOffsetDqs = 007
N0.C1.D1.R1: CheckMCTest: result = 0x1FF
N2.C3.D0.R1.S14: Offset Found: RdPtrOffsetDqs = 006
N4.C3.D0.R0.S06: Dq Delay estimate: 425
N6.C1.D1.R1.S07: Offset Found: RdPtrOffsetDqs = 007
ACCM: 0F 0F0F0F0F 0F0F0F0F
N2.C3.D0.R1.S15: Offset Found: RdPtrOffsetDqs = 007
N4.C3.D0.R0.S07: Dq Delay estimate: 441
N6.C1.D1.R1.S08: Offset Found: RdPtrOffsetDqs = 006
ACCM: 0F 0F0F0F0F 0F0F0F0F
N2.C3.D0.R1.S16: Offset Found: RdPtrOffsetDqs = 007
N4.C3.D0.R0.S08: Dq Delay estimate: 419
N6.C1.D1.R1: Write Training Coarse, upper nibbles
ACCM: 0F 0F0F000F 00000000
N2.C3.D0.R1.S17: Offset Found: RdPtrOffsetDqs = 006
ACCM: 0F 0F0F0F9F 0F0F0F0F
N6.C1.D1.R1.S09: Dq Delay estimate: 464
ACCM: 0F 0F0F000F 00000000
N2.C3.D1.R0: Write Training Coarse, lower nibbles / bytes
ACCM: 0F 0F0F0F9F 0F0F0F0F
N6.C1.D1.R1.S10: Dq Delay estimate: 452
N0.C1.D1.R1: CheckMCTest: result = 0x1FF
N2.C3.D1.R0.S00: Dq Delay estimate: 470
ACCM: FF FFFFFF9F FFFFFFF9
N6.C1.D1.R1.S11: Dq Delay estimate: 445
N0.C1.D1.R1: CheckMCTest: passed
N2.C3.D1.R0.S01: Dq Delay estimate: 459
ACCM: FF FFFFFF9F FFFFFFF9
N6.C1.D1.R1.S12: Dq Delay estimate: 429
N0.C1.D1.R1: CheckMCTest: passed
N2.C3.D1.R0.S02: Dq Delay estimate: 444
N4.C3.D0.R0: CheckMCTest: result = 0x3FFFF
N6.C1.D1.R1.S13: Dq Delay estimate: 392
N0.C1.D1.R1.S00: Offset Found: RdPtrOffsetDqs = 007
N2.C3.D1.R0.S03: Dq Delay estimate: 432
ACCM: 0F 0F0F0FDF 0F0F0F0F
N6.C1.D1.R1.S14: Dq Delay estimate: 407
N0.C1.D1.R1.S01: Offset Found: RdPtrOffsetDqs = 007
N2.C3.D1.R0.S04: Dq Delay estimate: 395
ACCM: 0F 0F0F0FDF 0F0F0F0F
N6.C1.D1.R1.S15: Dq Delay estimate: 417
N0.C1.D1.R1.S02: Offset Found: RdPtrOffsetDqs = 007
N2.C3.D1.R0.S05: Dq Delay estimate: 410
ACCM: FF FFFFFFDF FFFFFFFD
N6.C1.D1.R1.S16: Dq Delay estimate: 438
N0.C1.D1.R1.S03: Offset Found: RdPtrOffsetDqs = 007
N2.C3.D1.R0.S06: Dq Delay estimate: 422
ACCM: FF FFFFFFDF FFFFFFFD
N6.C1.D1.R1.S17: Dq Delay estimate: 407
N0.C1.D1.R1.S04: Offset Found: RdPtrOffsetDqs = 006
N2.C3.D1.R0.S07: Dq Delay estimate: 440
N4.C3.D0.R0: CheckMCTest: result = 0x3FFFF
ACCM: F0 F0F0F0F0 F0F0F0F0
N0.C1.D1.R1.S05: Offset Found: RdPtrOffsetDqs = 006
N2.C3.D1.R0.S08: Dq Delay estimate: 412
ACCM: 0F 0F0F0FDF 0F0F0F00
ACCM: F0 F0F0F0F0 F0F0F0F0
N0.C1.D1.R1.S06: Offset Found: RdPtrOffsetDqs = 007
ACCM: 0F 0FDF0F0F 0F0F0F0F
ACCM: 0F 0F0F0FDF 0F0F0F00
ACCM: F0 F0F0F0F0 F0F0F0F0
N0.C1.D1.R1.S07: Offset Found: RdPtrOffsetDqs = 007
ACCM: 0F 0FDF0F0F 0F0F0F0F
ACCM: FB FBF0FBD0 FBFBFBF0
ACCM: F0 F0F0F0F0 F0F0F0F0
N0.C1.D1.R1.S08: Offset Found: RdPtrOffsetDqs = 006
ACCM: 0F 0FDF0F0F 0F0F0F0F
ACCM: FB FBF0FBD0 FBFBFBF0
N6.C1.D1.R1: CheckMCTest: result = 0x3FE00
N0.C1.D1.R1: Write Training Coarse, upper nibbles
ACCM: 0F FFFF0F0F FFFFFF0F
N4.C3.D0.R0: CheckMCTest: result = 0x3FFFE
ACCM: F0 F0F0F0F0 F0F0F0F0
N0.C1.D1.R1.S09: Dq Delay estimate: 471
N2.C3.D1.R0: CheckMCTest: result = 0x19DFF
ACCM: 0F 0F0F0FDF 0F0F0F00
ACCM: F0 F0F0F0F0 F0F0F0F0
N0.C1.D1.R1.S10: Dq Delay estimate: 455
ACCM: 0F 0FDF0F0F 0F0F0F0F
ACCM: 0F 0F0F0FDF 0F0F0F00
ACCM: F0 F0F0F0F0 F0F0F0F0
N0.C1.D1.R1.S11: Dq Delay estimate: 450
ACCM: 0F 0FDF0F0F 0F0F0F0F
ACCM: FF FFF0FFD0 FFFFFFF0
ACCM: F0 F0F0F0F0 F0F0F0F0
N0.C1.D1.R1.S12: Dq Delay estimate: 434
ACCM: 0F 0FDF0F0F 0F0F0F0F
ACCM: FF FFF0FFD0 FFFFFFF0
N6.C1.D1.R1: CheckMCTest: result = 0x3FE00
N0.C1.D1.R1.S13: Dq Delay estimate: 398
ACCM: 0F FFFF0F0F FFFFFF0F
N4.C3.D0.R0: CheckMCTest: result = 0x3FFFE
ACCM: F0 F0F0F0F0 F0F0F0F0
N0.C1.D1.R1.S14: Dq Delay estimate: 415
N2.C3.D1.R0: CheckMCTest: result = 0x19DFF
N4.C3.D0.R0.S00: Offset Found: RdPtrOffsetDqs = 008
ACCM: F0 F0F0F0F0 F0F0F0F0
N0.C1.D1.R1.S15: Dq Delay estimate: 426
ACCM: 0F 0FDF0F0F 0F0F0F0F
ACCM: 00 000000D0 00000000
ACCM: 00 000000B0 B0000000
N0.C1.D1.R1.S16: Dq Delay estimate: 444
ACCM: 0F 0FDF0F0F 0F0F0F0F
ACCM: 00 000000D0 00000000
ACCM: 00 000000B0 B0000000
N0.C1.D1.R1.S17: Dq Delay estimate: 412
ACCM: 00 0BDB000B 00000B0B
ACCM: F0 F0F0F0D0 F0F0F0F0
N6.C1.D1.R1: CheckMCTest: result = 0x3FE00
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: 00 FBFB000B F0F0FB0B
ACCM: F0 F0F0F0D0 F0F0F0F0
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: F0 F0F0F0F0 F0F0F0F0
N2.C3.D1.R0: CheckMCTest: result = 0x19DFF
N4.C3.D0.R0: CheckMCTest: result = 0x3FE00
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: 0F 0FDF0F0F 0F0F0F0F
ACCM: 00 000000D0 00000000
ACCM: 00 000000F0 F000D000
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: 0F 0FDF0F0F 0F0F0F0F
ACCM: 00 000000D0 00000000
ACCM: 00 000000F0 F000D000
N0.C1.D1.R1: CheckMCTest: result = 0x3FE00
ACCM: 00 0FDF000F 000D0F0F
ACCM: F0 F0F0F0D0 F0F0F0F0
N6.C1.D1.R1: CheckMCTest: result = 0x3FE00
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: 00 FFFF000F F0FDFF0F
ACCM: F0 F0F0F0D0 F0F0F0F0
N6.C1.D1.R1: CheckMCTest: passed
ACCM: F0 F0F0F0F0 F0F0F0F0
N2.C3.D1.R0: CheckMCTest: result = 0x19DFF
N4.C3.D0.R0: CheckMCTest: result = 0x3FE00
N6.C1.D1.R1: CheckMCTest: passed
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: 00 00F00000 00000000
N4.C3.D0.R0.S00: Offset Found: RdPtrOffsetDqs = 008
N6.C1.D1.R1.S09: Offset Found: RdPtrOffsetDqs = 007
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: 00 00F00000 00000000
N4.C3.D0.R0.S01: Offset Found: RdPtrOffsetDqs = 007
N6.C1.D1.R1.S10: Offset Found: RdPtrOffsetDqs = 007
N0.C1.D1.R1: CheckMCTest: result = 0x3FE00
ACCM: 00 00F00000 00000000
N4.C3.D0.R0.S02: Offset Found: RdPtrOffsetDqs = 007
N6.C1.D1.R1.S11: Offset Found: RdPtrOffsetDqs = 007
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: 00 F0F00000 F0F0F000
N4.C3.D0.R0.S03: Offset Found: RdPtrOffsetDqs = 007
N6.C1.D1.R1.S12: Offset Found: RdPtrOffsetDqs = 007
ACCM: F0 F0F0F0F0 F0F0F0F0
N2.C3.D1.R0: CheckMCTest: result = 0x19C00
N4.C3.D0.R0.S04: Offset Found: RdPtrOffsetDqs = 006
N6.C1.D1.R1.S13: Offset Found: RdPtrOffsetDqs = 006
ACCM: 00 00B0B0B0 00000000
ACCM: 00 00F00000 00000000
N4.C3.D0.R0.S05: Offset Found: RdPtrOffsetDqs = 007
N6.C1.D1.R1.S14: Offset Found: RdPtrOffsetDqs = 006
ACCM: 00 00B0B0B0 00000000
ACCM: 00 00F00000 00000000
N4.C3.D0.R0.S06: Offset Found: RdPtrOffsetDqs = 007
N6.C1.D1.R1.S15: Offset Found: RdPtrOffsetDqs = 007
N0.C1.D1.R1: CheckMCTest: result = 0x3FE00
ACCM: 00 00F00000 00000000
N4.C3.D0.R0.S07: Offset Found: RdPtrOffsetDqs = 007
N6.C1.D1.R1.S16: Offset Found: RdPtrOffsetDqs = 007
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: 00 F0F00000 F0F0F000
N4.C3.D0.R0.S08: Offset Found: RdPtrOffsetDqs = 007
N6.C1.D1.R1.S17: Offset Found: RdPtrOffsetDqs = 006
ACCM: F0 F0F0F0F0 F0F0F0F0
N2.C3.D1.R0: CheckMCTest: result = 0x19C00
N4.C3.D0.R0: Write Training Coarse, upper nibbles
N6.C1: Calculating Optimimum DQS Values
ACCM: 00 00F0F0F0 00000000
N2.C3.D1.R0.S00: Offset Found: RdPtrOffsetDqs = 007
N4.C3.D0.R0.S09: Dq Delay estimate: 347
N6.C1.D0.R0.S00: Total Delay in PI ticks: TxDQS = 1014, TxDQ = 982
ACCM: 00 00F0F0F0 00000000
N2.C3.D1.R0.S01: Offset Found: RdPtrOffsetDqs = 007
N4.C3.D0.R0.S10: Dq Delay estimate: 459
N6.C1.D0.R0.S01: Total Delay in PI ticks: TxDQS = 998, TxDQ = 965
N0.C1.D1.R1: CheckMCTest: result = 0x3FE00
N2.C3.D1.R0.S02: Offset Found: RdPtrOffsetDqs = 007
N4.C3.D0.R0.S11: Dq Delay estimate: 448
N6.C1.D0.R0.S02: Total Delay in PI ticks: TxDQS = 988, TxDQ = 956
N0.C1.D1.R1: CheckMCTest: passed
N2.C3.D1.R0.S03: Offset Found: RdPtrOffsetDqs = 007
N4.C3.D0.R0.S12: Dq Delay estimate: 435
N6.C1.D0.R0.S03: Total Delay in PI ticks: TxDQS = 972, TxDQ = 939
N0.C1.D1.R1: CheckMCTest: passed
N2.C3.D1.R0.S04: Offset Found: RdPtrOffsetDqs = 006
N4.C3.D0.R0.S13: Dq Delay estimate: 399
N6.C1.D0.R0.S04: Total Delay in PI ticks: TxDQS = 939, TxDQ = 905
N0.C1.D1.R1.S09: Offset Found: RdPtrOffsetDqs = 007
N2.C3.D1.R0.S05: Offset Found: RdPtrOffsetDqs = 006
N4.C3.D0.R0.S14: Dq Delay estimate: 410
N6.C1.D0.R0.S05: Total Delay in PI ticks: TxDQS = 953, TxDQ = 919
N0.C1.D1.R1.S10: Offset Found: RdPtrOffsetDqs = 007
N2.C3.D1.R0.S06: Offset Found: RdPtrOffsetDqs = 007
N4.C3.D0.R0.S15: Dq Delay estimate: 427
N6.C1.D0.R0.S06: Total Delay in PI ticks: TxDQS = 970, TxDQ = 937
N0.C1.D1.R1.S11: Offset Found: RdPtrOffsetDqs = 007
N2.C3.D1.R0.S07: Offset Found: RdPtrOffsetDqs = 007
N4.C3.D0.R0.S16: Dq Delay estimate: 442
N6.C1.D0.R0.S07: Total Delay in PI ticks: TxDQS = 985, TxDQ = 951
N0.C1.D1.R1.S12: Offset Found: RdPtrOffsetDqs = 007
N2.C3.D1.R0.S08: Offset Found: RdPtrOffsetDqs = 007
N4.C3.D0.R0.S17: Dq Delay estimate: 413
N6.C1.D0.R0.S08: Total Delay in PI ticks: TxDQS = 955, TxDQ = 922
N0.C1.D1.R1.S13: Offset Found: RdPtrOffsetDqs = 006
N2.C3.D1.R0: Write Training Coarse, upper nibbles
ACCM: F0 F0F0F0F0 F0F0F0F0
N6.C1.D0.R0.S09: Total Delay in PI ticks: TxDQS = 1015, TxDQ = 980
N0.C1.D1.R1.S14: Offset Found: RdPtrOffsetDqs = 007
N2.C3.D1.R0.S09: Dq Delay estimate: 470
ACCM: F0 F0F0F0F0 F0F0F0F0
N6.C1.D0.R0.S10: Total Delay in PI ticks: TxDQS = 997, TxDQ = 964
N0.C1.D1.R1.S15: Offset Found: RdPtrOffsetDqs = 007
N2.C3.D1.R0.S10: Dq Delay estimate: 458
ACCM: F0 F0F0F0F0 F0F0F0B0
N6.C1.D0.R0.S11: Total Delay in PI ticks: TxDQS = 990, TxDQ = 957
N0.C1.D1.R1.S16: Offset Found: RdPtrOffsetDqs = 007
N2.C3.D1.R0.S11: Dq Delay estimate: 444
ACCM: F0 F0F0F0F0 F0F0F0B0
N6.C1.D0.R0.S12: Total Delay in PI ticks: TxDQS = 973, TxDQ = 940
N0.C1.D1.R1.S17: Offset Found: RdPtrOffsetDqs = 006
N2.C3.D1.R0.S12: Dq Delay estimate: 432
N4.C3.D0.R0: CheckMCTest: result = 0x3FE00
N6.C1.D0.R0.S13: Total Delay in PI ticks: TxDQS = 938, TxDQ = 904
N0.C1: Calculating Optimimum DQS Values
N2.C3.D1.R0.S13: Dq Delay estimate: 398
ACCM: F0 F0F0F0F0 F0F0F0F0
N6.C1.D0.R0.S14: Total Delay in PI ticks: TxDQS = 952, TxDQ = 918
N0.C1.D0.R0.S00: Total Delay in PI ticks: TxDQS = 1019, TxDQ = 987
N2.C3.D1.R0.S14: Dq Delay estimate: 408
ACCM: F0 F0F0F0F0 F0F0F0F0
N6.C1.D0.R0.S15: Total Delay in PI ticks: TxDQS = 968, TxDQ = 935
N0.C1.D0.R0.S01: Total Delay in PI ticks: TxDQS = 999, TxDQ = 965
N2.C3.D1.R0.S15: Dq Delay estimate: 422
ACCM: F0 F0F0F0F0 F0F0F0F0
N6.C1.D0.R0.S16: Total Delay in PI ticks: TxDQS = 984, TxDQ = 949
N0.C1.D0.R0.S02: Total Delay in PI ticks: TxDQS = 993, TxDQ = 959
N2.C3.D1.R0.S16: Dq Delay estimate: 440
ACCM: F0 F0F0F0F0 F0F0F0F0
N6.C1.D0.R0.S17: Total Delay in PI ticks: TxDQS = 955, TxDQ = 922
N0.C1.D0.R0.S03: Total Delay in PI ticks: TxDQS = 973, TxDQ = 940
N2.C3.D1.R0.S17: Dq Delay estimate: 413
N4.C3.D0.R0: CheckMCTest: result = 0x3FE00
N6.C1.D0.R1.S00: Total Delay in PI ticks: TxDQS = 1009, TxDQ = 976
N0.C1.D0.R0.S04: Total Delay in PI ticks: TxDQS = 938, TxDQ = 906
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: F0 F0F0F0F0 F0F0F000
N6.C1.D0.R1.S01: Total Delay in PI ticks: TxDQS = 991, TxDQ = 956
N0.C1.D0.R0.S05: Total Delay in PI ticks: TxDQS = 956, TxDQ = 922
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: F0 F0F0F0F0 F0F0F000
N6.C1.D0.R1.S02: Total Delay in PI ticks: TxDQS = 983, TxDQ = 951
N0.C1.D0.R0.S06: Total Delay in PI ticks: TxDQS = 971, TxDQ = 937
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: B0 0000B0B0 B000B000
N6.C1.D0.R1.S03: Total Delay in PI ticks: TxDQS = 965, TxDQ = 932
N0.C1.D0.R0.S07: Total Delay in PI ticks: TxDQS = 987, TxDQ = 953
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: B0 0000B0B0 B000B000
N6.C1.D0.R1.S04: Total Delay in PI ticks: TxDQS = 935, TxDQ = 901
N0.C1.D0.R0.S08: Total Delay in PI ticks: TxDQS = 954, TxDQ = 923
N2.C3.D1.R0: CheckMCTest: result = 0x3FE00
N4.C3.D0.R0: CheckMCTest: result = 0x3FC00
N6.C1.D0.R1.S05: Total Delay in PI ticks: TxDQS = 947, TxDQ = 913
N0.C1.D0.R0.S09: Total Delay in PI ticks: TxDQS = 1018, TxDQ = 985
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: F0 F0F0F0F0 F0F0F000
N6.C1.D0.R1.S06: Total Delay in PI ticks: TxDQS = 961, TxDQ = 928
N0.C1.D0.R0.S10: Total Delay in PI ticks: TxDQS = 1000, TxDQ = 966
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: F0 F0F0F0F0 F0F0F000
N6.C1.D0.R1.S07: Total Delay in PI ticks: TxDQS = 977, TxDQ = 943
N0.C1.D0.R0.S11: Total Delay in PI ticks: TxDQS = 994, TxDQ = 962
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: F0 0000F0F0 B000F000
N6.C1.D0.R1.S08: Total Delay in PI ticks: TxDQS = 948, TxDQ = 915
N0.C1.D0.R0.S12: Total Delay in PI ticks: TxDQS = 975, TxDQ = 942
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: F0 0000F0F0 B000F000
N6.C1.D0.R1.S09: Total Delay in PI ticks: TxDQS = 1007, TxDQ = 972
N0.C1.D0.R0.S13: Total Delay in PI ticks: TxDQS = 939, TxDQ = 906
N2.C3.D1.R0: CheckMCTest: result = 0x3FE00
N4.C3.D0.R0: CheckMCTest: result = 0x3FC00
N6.C1.D0.R1.S10: Total Delay in PI ticks: TxDQS = 991, TxDQ = 958
N0.C1.D0.R0.S14: Total Delay in PI ticks: TxDQS = 954, TxDQ = 920
ACCM: F0 F0F0F0F0 F0F0F0F0
N4.C3.D0.R0.S09: Offset Found: RdPtrOffsetDqs = 008
N6.C1.D0.R1.S11: Total Delay in PI ticks: TxDQS = 983, TxDQ = 952
N0.C1.D0.R0.S15: Total Delay in PI ticks: TxDQS = 970, TxDQ = 938
ACCM: F0 F0F0F0F0 F0F0F0F0
N4.C3.D0.R0: CheckMCTest: passed
N6.C1.D0.R1.S12: Total Delay in PI ticks: TxDQS = 966, TxDQ = 933
N0.C1.D0.R0.S16: Total Delay in PI ticks: TxDQS = 987, TxDQ = 954
ACCM: 00 B0B0B0B0 0000B0B0
N4.C3.D0.R0: CheckMCTest: passed
N6.C1.D0.R1.S13: Total Delay in PI ticks: TxDQS = 933, TxDQ = 899
N0.C1.D0.R0.S17: Total Delay in PI ticks: TxDQS = 957, TxDQ = 925
ACCM: 00 B0B0B0B0 0000B0B0
N4.C3.D0.R0.S09: Offset Found: RdPtrOffsetDqs = 008
N6.C1.D0.R1.S14: Total Delay in PI ticks: TxDQS = 945, TxDQ = 911
N0.C1.D0.R1.S00: Total Delay in PI ticks: TxDQS = 1010, TxDQ = 977
N2.C3.D1.R0: CheckMCTest: result = 0x3FE00
N4.C3.D0.R0.S10: Offset Found: RdPtrOffsetDqs = 007
N6.C1.D0.R1.S15: Total Delay in PI ticks: TxDQS = 961, TxDQ = 928
N0.C1.D0.R1.S01: Total Delay in PI ticks: TxDQS = 992, TxDQ = 958
ACCM: F0 F0F0F0F0 F0F0F0F0
N4.C3.D0.R0.S11: Offset Found: RdPtrOffsetDqs = 007
N6.C1.D0.R1.S16: Total Delay in PI ticks: TxDQS = 978, TxDQ = 943
N0.C1.D0.R1.S02: Total Delay in PI ticks: TxDQS = 985, TxDQ = 951
ACCM: F0 F0F0F0F0 F0F0F0F0
N4.C3.D0.R0.S12: Offset Found: RdPtrOffsetDqs = 007
N6.C1.D0.R1.S17: Total Delay in PI ticks: TxDQS = 946, TxDQ = 913
N0.C1.D0.R1.S03: Total Delay in PI ticks: TxDQS = 968, TxDQ = 935
ACCM: 00 F0F0F0F0 0000F0F0
N4.C3.D0.R0.S13: Offset Found: RdPtrOffsetDqs = 006
N6.C1.D1.R0.S00: Total Delay in PI ticks: TxDQS = 1018, TxDQ = 983
N0.C1.D0.R1.S04: Total Delay in PI ticks: TxDQS = 932, TxDQ = 900
ACCM: 00 F0F0F0F0 0000F0F0
N4.C3.D0.R0.S14: Offset Found: RdPtrOffsetDqs = 007
N6.C1.D1.R0.S01: Total Delay in PI ticks: TxDQS = 1002, TxDQ = 966
N0.C1.D0.R1.S05: Total Delay in PI ticks: TxDQS = 949, TxDQ = 916
N2.C3.D1.R0: CheckMCTest: result = 0x3FE00
N4.C3.D0.R0.S15: Offset Found: RdPtrOffsetDqs = 007
N6.C1.D1.R0.S02: Total Delay in PI ticks: TxDQS = 992, TxDQ = 958
N0.C1.D0.R1.S06: Total Delay in PI ticks: TxDQS = 962, TxDQ = 928
N2.C3.D1.R0: CheckMCTest: passed
N4.C3.D0.R0.S16: Offset Found: RdPtrOffsetDqs = 007
N6.C1.D1.R0.S03: Total Delay in PI ticks: TxDQS = 977, TxDQ = 942
N0.C1.D0.R1.S07: Total Delay in PI ticks: TxDQS = 980, TxDQ = 947
N2.C3.D1.R0: CheckMCTest: passed
N4.C3.D0.R0.S17: Offset Found: RdPtrOffsetDqs = 007
N6.C1.D1.R0.S04: Total Delay in PI ticks: TxDQS = 944, TxDQ = 908
N0.C1.D0.R1.S08: Total Delay in PI ticks: TxDQS = 949, TxDQ = 917
N2.C3.D1.R0.S09: Offset Found: RdPtrOffsetDqs = 007
N4.C3.D0.R1: Write Training Coarse, lower nibbles / bytes
N6.C1.D1.R0.S05: Total Delay in PI ticks: TxDQS = 959, TxDQ = 923
N0.C1.D0.R1.S09: Total Delay in PI ticks: TxDQS = 1009, TxDQ = 976
N2.C3.D1.R0.S10: Offset Found: RdPtrOffsetDqs = 007
N4.C3.D0.R1.S00: Dq Delay estimate: 469
N6.C1.D1.R0.S06: Total Delay in PI ticks: TxDQS = 971, TxDQ = 935
N0.C1.D0.R1.S10: Total Delay in PI ticks: TxDQS = 993, TxDQ = 959
N2.C3.D1.R0.S11: Offset Found: RdPtrOffsetDqs = 007
N4.C3.D0.R1.S01: Dq Delay estimate: 451
N6.C1.D1.R0.S07: Total Delay in PI ticks: TxDQS = 988, TxDQ = 952
N0.C1.D0.R1.S11: Total Delay in PI ticks: TxDQS = 983, TxDQ = 951
N2.C3.D1.R0.S12: Offset Found: RdPtrOffsetDqs = 007
N4.C3.D0.R1.S02: Dq Delay estimate: 440
N6.C1.D1.R0.S08: Total Delay in PI ticks: TxDQS = 958, TxDQ = 923
N0.C1.D0.R1.S12: Total Delay in PI ticks: TxDQS = 969, TxDQ = 936
N2.C3.D1.R0.S13: Offset Found: RdPtrOffsetDqs = 006
N4.C3.D0.R1.S03: Dq Delay estimate: 429
N6.C1.D1.R0.S09: Total Delay in PI ticks: TxDQS = 1018, TxDQ = 981
N0.C1.D0.R1.S13: Total Delay in PI ticks: TxDQS = 935, TxDQ = 903
N2.C3.D1.R0.S14: Offset Found: RdPtrOffsetDqs = 006
N4.C3.D0.R1.S04: Dq Delay estimate: 388
N6.C1.D1.R0.S10: Total Delay in PI ticks: TxDQS = 1002, TxDQ = 967
N0.C1.D0.R1.S14: Total Delay in PI ticks: TxDQS = 952, TxDQ = 918
N2.C3.D1.R0.S15: Offset Found: RdPtrOffsetDqs = 007
N4.C3.D0.R1.S05: Dq Delay estimate: 403
N6.C1.D1.R0.S11: Total Delay in PI ticks: TxDQS = 993, TxDQ = 960
N0.C1.D0.R1.S15: Total Delay in PI ticks: TxDQS = 962, TxDQ = 929
N2.C3.D1.R0.S16: Offset Found: RdPtrOffsetDqs = 007
N4.C3.D0.R1.S06: Dq Delay estimate: 417
N6.C1.D1.R0.S12: Total Delay in PI ticks: TxDQS = 978, TxDQ = 944
N0.C1.D0.R1.S16: Total Delay in PI ticks: TxDQS = 983, TxDQ = 952
N2.C3.D1.R0.S17: Offset Found: RdPtrOffsetDqs = 007
N4.C3.D0.R1.S07: Dq Delay estimate: 435
N6.C1.D1.R0.S13: Total Delay in PI ticks: TxDQS = 945, TxDQ = 909
N0.C1.D0.R1.S17: Total Delay in PI ticks: TxDQS = 947, TxDQ = 917
N2.C3.D1.R1: Write Training Coarse, lower nibbles / bytes
N4.C3.D0.R1.S08: Dq Delay estimate: 408
N6.C1.D1.R0.S14: Total Delay in PI ticks: TxDQS = 957, TxDQ = 921
N0.C1.D1.R0.S00: Total Delay in PI ticks: TxDQS = 1021, TxDQ = 987
N2.C3.D1.R1.S00: Dq Delay estimate: 467
ACCM: 0F 0F0F0F0F 0F0F0F0F
N6.C1.D1.R0.S15: Total Delay in PI ticks: TxDQS = 970, TxDQ = 934
N0.C1.D1.R0.S01: Total Delay in PI ticks: TxDQS = 1003, TxDQ = 968
N2.C3.D1.R1.S01: Dq Delay estimate: 454
ACCM: 0F 0F0F0F0F 0F0F0F0F
N6.C1.D1.R0.S16: Total Delay in PI ticks: TxDQS = 992, TxDQ = 956
N0.C1.D1.R0.S02: Total Delay in PI ticks: TxDQS = 995, TxDQ = 959
N2.C3.D1.R1.S02: Dq Delay estimate: 439
ACCM: 0F 0F0F0F0F 0F0F0F0F
N6.C1.D1.R0.S17: Total Delay in PI ticks: TxDQS = 957, TxDQ = 923
N0.C1.D1.R0.S03: Total Delay in PI ticks: TxDQS = 983, TxDQ = 949
N2.C3.D1.R1.S03: Dq Delay estimate: 429
ACCM: 0F 0F0F0F0F 0F0F0F0F
N6.C1.D1.R1.S00: Total Delay in PI ticks: TxDQS = 1014, TxDQ = 979
N0.C1.D1.R0.S04: Total Delay in PI ticks: TxDQS = 947, TxDQ = 913
N2.C3.D1.R1.S04: Dq Delay estimate: 392
N4.C3.D0.R1: CheckMCTest: result = 0x1FF
N6.C1.D1.R1.S01: Total Delay in PI ticks: TxDQS = 997, TxDQ = 961
N0.C1.D1.R0.S05: Total Delay in PI ticks: TxDQS = 961, TxDQ = 926
N2.C3.D1.R1.S05: Dq Delay estimate: 406
ACCM: 0F 0F0F0F0F 0F0F0F0F
N6.C1.D1.R1.S02: Total Delay in PI ticks: TxDQS = 987, TxDQ = 953
N0.C1.D1.R0.S06: Total Delay in PI ticks: TxDQS = 978, TxDQ = 943
N2.C3.D1.R1.S06: Dq Delay estimate: 418
ACCM: 0F 0F0F0F0F 0F0F0F0F
N6.C1.D1.R1.S03: Total Delay in PI ticks: TxDQS = 973, TxDQ = 938
N0.C1.D1.R0.S07: Total Delay in PI ticks: TxDQS = 994, TxDQ = 959
N2.C3.D1.R1.S07: Dq Delay estimate: 437
ACCM: 0F 0F0F0F0F 0F0F0F0F
N6.C1.D1.R1.S04: Total Delay in PI ticks: TxDQS = 939, TxDQ = 903
N0.C1.D1.R0.S08: Total Delay in PI ticks: TxDQS = 962, TxDQ = 928
N2.C3.D1.R1.S08: Dq Delay estimate: 407
ACCM: 0F 0F0F0F0F 0F0F0F0F
N6.C1.D1.R1.S05: Total Delay in PI ticks: TxDQS = 955, TxDQ = 919
N0.C1.D1.R0.S09: Total Delay in PI ticks: TxDQS = 1022, TxDQ = 987
ACCM: 0F 0F0F0F0F 0F0F0F0F
N4.C3.D0.R1: CheckMCTest: result = 0x1FF
N6.C1.D1.R1.S06: Total Delay in PI ticks: TxDQS = 965, TxDQ = 929
N0.C1.D1.R0.S10: Total Delay in PI ticks: TxDQS = 1004, TxDQ = 968
ACCM: 0F 0F0F0F0F 0F0F0F0F
ACCM: 0F 0F0F0F0F 0F0F0F0F
N6.C1.D1.R1.S07: Total Delay in PI ticks: TxDQS = 985, TxDQ = 949
N0.C1.D1.R0.S11: Total Delay in PI ticks: TxDQS = 996, TxDQ = 962
ACCM: 0F 0F0F0F0F 0F0F0F0F
ACCM: 0F 0F0F0F0F 0F0F0F0F
N6.C1.D1.R1.S08: Total Delay in PI ticks: TxDQS = 953, TxDQ = 917
N0.C1.D1.R0.S12: Total Delay in PI ticks: TxDQS = 983, TxDQ = 949
ACCM: 0F 0F0F0F0F 0F0F0F0F
ACCM: 0B 0000000B 000B0B00
N6.C1.D1.R1.S09: Total Delay in PI ticks: TxDQS = 1013, TxDQ = 976
N0.C1.D1.R0.S13: Total Delay in PI ticks: TxDQS = 947, TxDQ = 912
N2.C3.D1.R1: CheckMCTest: result = 0x1FF
ACCM: 0B 0000000B 000B0B00
N6.C1.D1.R1.S10: Total Delay in PI ticks: TxDQS = 999, TxDQ = 964
N0.C1.D1.R0.S14: Total Delay in PI ticks: TxDQS = 962, TxDQ = 927
ACCM: 0F 0F0F0F0F 0F0F0F0F
N4.C3.D0.R1: CheckMCTest: result = 0x1FF
N6.C1.D1.R1.S11: Total Delay in PI ticks: TxDQS = 990, TxDQ = 957
N0.C1.D1.R0.S15: Total Delay in PI ticks: TxDQS = 976, TxDQ = 942
ACCM: 0F 0F0F0F0F 0F0F0F0F
ACCM: 0F 0F0F0F0F 0F0F0F0F
N6.C1.D1.R1.S12: Total Delay in PI ticks: TxDQS = 976, TxDQ = 941
N0.C1.D1.R0.S16: Total Delay in PI ticks: TxDQS = 993, TxDQ = 959
ACCM: 0F 0F0F0F0F 0F0F0F0F
ACCM: 0F 0F0F0F0F 0F0F0F0F
N6.C1.D1.R1.S13: Total Delay in PI ticks: TxDQS = 940, TxDQ = 904
N0.C1.D1.R0.S17: Total Delay in PI ticks: TxDQS = 960, TxDQ = 927
ACCM: 0F 0F0F0F0F 0F0F0F0F
ACCM: 0F 0000000F 000F0F00
N6.C1.D1.R1.S14: Total Delay in PI ticks: TxDQS = 955, TxDQ = 919
N0.C1.D1.R1.S00: Total Delay in PI ticks: TxDQS = 1018, TxDQ = 983
N2.C3.D1.R1: CheckMCTest: result = 0x1FF
ACCM: 0F 0000000F 000F0F00
N6.C1.D1.R1.S15: Total Delay in PI ticks: TxDQS = 965, TxDQ = 929
N0.C1.D1.R1.S01: Total Delay in PI ticks: TxDQS = 1001, TxDQ = 966
ACCM: 0F 0F0F0F0F 0F0F0F0F
N4.C3.D0.R1: CheckMCTest: result = 0x1FF
N6.C1.D1.R1.S16: Total Delay in PI ticks: TxDQS = 986, TxDQ = 950
N0.C1.D1.R1.S02: Total Delay in PI ticks: TxDQS = 993, TxDQ = 958
ACCM: 0F 0F0F0F0F 0F0F0F0F
N4.C3.D0.R1: CheckMCTest: passed
N6.C1.D1.R1.S17: Total Delay in PI ticks: TxDQS = 953, TxDQ = 919
N0.C1.D1.R1.S03: Total Delay in PI ticks: TxDQS = 979, TxDQ = 945
ACCM: 00 000B000B 00000000
N4.C3.D0.R1: CheckMCTest: passed
N6.C2.D0.R0: Write Training Coarse, lower nibbles / bytes
N0.C1.D1.R1.S04: Total Delay in PI ticks: TxDQS = 945, TxDQ = 910
ACCM: 00 000B000B 00000000
N4.C3.D0.R1.S00: Offset Found: RdPtrOffsetDqs = 007
N6.C2.D0.R0.S00: Dq Delay estimate: 464
N0.C1.D1.R1.S05: Total Delay in PI ticks: TxDQS = 958, TxDQ = 923
N2.C3.D1.R1: CheckMCTest: result = 0x1FF
N4.C3.D0.R1.S01: Offset Found: RdPtrOffsetDqs = 007
N6.C2.D0.R0.S01: Dq Delay estimate: 449
N0.C1.D1.R1.S06: Total Delay in PI ticks: TxDQS = 970, TxDQ = 934
ACCM: 0F 0F0F0F0F 0F0F0F0F
N4.C3.D0.R1.S02: Offset Found: RdPtrOffsetDqs = 007
N6.C2.D0.R0.S02: Dq Delay estimate: 439
N0.C1.D1.R1.S07: Total Delay in PI ticks: TxDQS = 993, TxDQ = 958
ACCM: 0F 0F0F0F0F 0F0F0F0F
N4.C3.D0.R1.S03: Offset Found: RdPtrOffsetDqs = 007
N6.C2.D0.R0.S03: Dq Delay estimate: 419
N0.C1.D1.R1.S08: Total Delay in PI ticks: TxDQS = 956, TxDQ = 922
ACCM: 00 000F000F 00000000
N4.C3.D0.R1.S04: Offset Found: RdPtrOffsetDqs = 006
N6.C2.D0.R0.S04: Dq Delay estimate: 384
N0.C1.D1.R1.S09: Total Delay in PI ticks: TxDQS = 1018, TxDQ = 983
ACCM: 00 000F000F 00000000
N4.C3.D0.R1.S05: Offset Found: RdPtrOffsetDqs = 006
N6.C2.D0.R0.S05: Dq Delay estimate: 408
N0.C1.D1.R1.S10: Total Delay in PI ticks: TxDQS = 1003, TxDQ = 967
N2.C3.D1.R1: CheckMCTest: result = 0x1FF
N4.C3.D0.R1.S06: Offset Found: RdPtrOffsetDqs = 007
N6.C2.D0.R0.S06: Dq Delay estimate: 411
N0.C1.D1.R1.S11: Total Delay in PI ticks: TxDQS = 995, TxDQ = 962
N2.C3.D1.R1: CheckMCTest: passed
N4.C3.D0.R1.S07: Offset Found: RdPtrOffsetDqs = 007
N6.C2.D0.R0.S07: Dq Delay estimate: 427
N0.C1.D1.R1.S12: Total Delay in PI ticks: TxDQS = 980, TxDQ = 946
N2.C3.D1.R1: CheckMCTest: passed
N4.C3.D0.R1.S08: Offset Found: RdPtrOffsetDqs = 006
N6.C2.D0.R0.S08: Dq Delay estimate: 397
N0.C1.D1.R1.S13: Total Delay in PI ticks: TxDQS = 945, TxDQ = 910
N2.C3.D1.R1.S00: Offset Found: RdPtrOffsetDqs = 007
N4.C3.D0.R1: Write Training Coarse, upper nibbles
ACCM: 0F 0F9F9F0F 0F0F0F0F
N0.C1.D1.R1.S14: Total Delay in PI ticks: TxDQS = 961, TxDQ = 927
N2.C3.D1.R1.S01: Offset Found: RdPtrOffsetDqs = 007
N4.C3.D0.R1.S09: Dq Delay estimate: 468
ACCM: 0F 0F9F9F0F 0F0F0F0F
N0.C1.D1.R1.S15: Total Delay in PI ticks: TxDQS = 972, TxDQ = 938
N2.C3.D1.R1.S02: Offset Found: RdPtrOffsetDqs = 007
N4.C3.D0.R1.S10: Dq Delay estimate: 454
ACCM: 0F FF9F9F0F FFFFFFFF
N0.C1.D1.R1.S16: Total Delay in PI ticks: TxDQS = 990, TxDQ = 956
N2.C3.D1.R1.S03: Offset Found: RdPtrOffsetDqs = 007
N4.C3.D0.R1.S11: Dq Delay estimate: 441
ACCM: 0F FF9F9F0F FFFFFFFF
N0.C1.D1.R1.S17: Total Delay in PI ticks: TxDQS = 957, TxDQ = 924
N2.C3.D1.R1.S04: Offset Found: RdPtrOffsetDqs = 006
N4.C3.D0.R1.S12: Dq Delay estimate: 430
N6.C2.D0.R0: CheckMCTest: result = 0x1DFFF
N0.C2.D0.R0: Write Training Coarse, lower nibbles / bytes
N2.C3.D1.R1.S05: Offset Found: RdPtrOffsetDqs = 006
N4.C3.D0.R1.S13: Dq Delay estimate: 391
ACCM: 0F 0FDFDF0F 0F0F0F0F
N0.C2.D0.R0.S00: Dq Delay estimate: 470
N2.C3.D1.R1.S06: Offset Found: RdPtrOffsetDqs = 007
N4.C3.D0.R1.S14: Dq Delay estimate: 405
ACCM: 0F 0FDFDF0F 0F0F0F0F
N0.C2.D0.R0.S01: Dq Delay estimate: 452
N2.C3.D1.R1.S07: Offset Found: RdPtrOffsetDqs = 007
N4.C3.D0.R1.S15: Dq Delay estimate: 420
ACCM: 0F FFDFDF0F FFFFFFFF
N0.C2.D0.R0.S02: Dq Delay estimate: 443
N2.C3.D1.R1.S08: Offset Found: RdPtrOffsetDqs = 006
N4.C3.D0.R1.S16: Dq Delay estimate: 437
ACCM: 0F FFDFDF0F FFFFFFFF
N0.C2.D0.R0.S03: Dq Delay estimate: 424
N2.C3.D1.R1: Write Training Coarse, upper nibbles
N4.C3.D0.R1.S17: Dq Delay estimate: 406
N6.C2.D0.R0: CheckMCTest: result = 0x1DFFF
N0.C2.D0.R0.S04: Dq Delay estimate: 388
N2.C3.D1.R1.S09: Dq Delay estimate: 467
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: 0F 0FDFDF0F 0F0F0F0F
N0.C2.D0.R0.S05: Dq Delay estimate: 412
N2.C3.D1.R1.S10: Dq Delay estimate: 454
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: 0F 0FDFDF0F 0F0F0F0F
N0.C2.D0.R0.S06: Dq Delay estimate: 413
N2.C3.D1.R1.S11: Dq Delay estimate: 441
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: 0B FBDBDB0B F0F0F0F0
N0.C2.D0.R0.S07: Dq Delay estimate: 432
N2.C3.D1.R1.S12: Dq Delay estimate: 428
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: 0B FBDBDB0B F0F0F0F0
N0.C2.D0.R0.S08: Dq Delay estimate: 407
N2.C3.D1.R1.S13: Dq Delay estimate: 392
N4.C3.D0.R1: CheckMCTest: result = 0x3FE00
N6.C2.D0.R0: CheckMCTest: result = 0x1DFFF
ACCM: 9F 0F0FDF9F 0F0F0F0F
N2.C3.D1.R1.S14: Dq Delay estimate: 404
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: 0F 0FDFDF0F 0F0F0F0F
ACCM: 9F 0F0FDF9F 0F0F0F0F
N2.C3.D1.R1.S15: Dq Delay estimate: 419
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: 0F 0FDFDF0F 0F0F0F0F
ACCM: 9F FFFFFF9F FFFFFFFF
N2.C3.D1.R1.S16: Dq Delay estimate: 436
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: 0B FFDFDF0F F0FDF0F0
ACCM: 9F FFFFFF9F FFFFFFFF
N2.C3.D1.R1.S17: Dq Delay estimate: 407
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: 0B FFDFDF0F F0FDF0F0
N0.C2.D0.R0: CheckMCTest: result = 0x3FFFF
ACCM: F0 F0F0F0F0 F0F0F0F0
N4.C3.D0.R1: CheckMCTest: result = 0x3FE00
N6.C2.D0.R0: CheckMCTest: result = 0x1DFFF
ACCM: DF 0F0FFFDF 0F0F0F0F
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: 00 00D0D000 00000000
ACCM: DF 0F0FFFDF 0F0F0F0F
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: 00 00D0D000 00000000
ACCM: DF FFFFFFDF FFFFFFFF
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: 00 00B0B000 B00000B0
ACCM: 00 F0D0D000 F0F0F0F0
ACCM: DF FFFFFFDF FFFFFFFF
N2.C3.D1.R1: CheckMCTest: result = 0x3FE00
ACCM: 00 00B0B000 B00000B0
ACCM: 00 F0D0D000 F0F0F0F0
N0.C2.D0.R0: CheckMCTest: result = 0x3FFFF
ACCM: F0 F0F0F0F0 F0F0F0F0
N4.C3.D0.R1: CheckMCTest: result = 0x3FE00
N6.C2.D0.R0: CheckMCTest: result = 0x1DE00
ACCM: DF 0F0F0FDF 0F0F0F0F
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: 00 00D0D000 00000000
ACCM: DF 0F0F0FDF 0F0F0F0F
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: 00 00D0D000 00000000
ACCM: DB FBFBFBDB FBF0FBFB
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: 00 00F0F000 F00000F0
ACCM: 00 F0D0D000 F0F0F0F0
ACCM: DB FBFBFBDB FBF0FBFB
N2.C3.D1.R1: CheckMCTest: result = 0x3FE00
ACCM: 00 00F0F000 F00000F0
ACCM: 00 F0D0D000 F0F0F0F0
N0.C2.D0.R0: CheckMCTest: result = 0x3FFFF
ACCM: F0 F0F0F0F0 F0F0F0F0
N4.C3.D0.R1: CheckMCTest: result = 0x3FE00
N6.C2.D0.R0: CheckMCTest: result = 0x1DE00
ACCM: DF 0F0FDFDF 0F0F0F0F
ACCM: F0 F0F0F0F0 F0F0F0F0
N4.C3.D0.R1: CheckMCTest: passed
N6.C2.D0.R0.S00: Offset Found: RdPtrOffsetDqs = 007
ACCM: DF 0F0FDFDF 0F0F0F0F
ACCM: 00 000000B0 0000B000
N4.C3.D0.R1: CheckMCTest: passed
N6.C2.D0.R0.S01: Offset Found: RdPtrOffsetDqs = 007
ACCM: DB FFFFFFDF FFF0FFFF
ACCM: 00 000000B0 0000B000
N4.C3.D0.R1.S09: Offset Found: RdPtrOffsetDqs = 007
N6.C2.D0.R0.S02: Offset Found: RdPtrOffsetDqs = 007
ACCM: DB FFFFFFDF FFF0FFFF
N2.C3.D1.R1: CheckMCTest: result = 0x3FE00
N4.C3.D0.R1.S10: Offset Found: RdPtrOffsetDqs = 007
N6.C2.D0.R0.S03: Offset Found: RdPtrOffsetDqs = 007
N0.C2.D0.R0: CheckMCTest: result = 0x3FFFF
ACCM: F0 F0F0F0F0 F0F0F0F0
N4.C3.D0.R1.S11: Offset Found: RdPtrOffsetDqs = 007
N6.C2.D0.R0.S04: Offset Found: RdPtrOffsetDqs = 006
ACCM: D0 0000F0D0 00000000
ACCM: F0 F0F0F0F0 F0F0F0F0
N4.C3.D0.R1.S12: Offset Found: RdPtrOffsetDqs = 007
N6.C2.D0.R0.S05: Offset Found: RdPtrOffsetDqs = 006
ACCM: D0 0000F0D0 00000000
ACCM: 00 0000D0F0 00D0F000
N4.C3.D0.R1.S13: Offset Found: RdPtrOffsetDqs = 006
N6.C2.D0.R0.S06: Offset Found: RdPtrOffsetDqs = 006
ACCM: D0 F0F0F0D0 F0F0F0F0
ACCM: 00 0000D0F0 00D0F000
N4.C3.D0.R1.S14: Offset Found: RdPtrOffsetDqs = 006
N6.C2.D0.R0.S07: Offset Found: RdPtrOffsetDqs = 007
ACCM: D0 F0F0F0D0 F0F0F0F0
N2.C3.D1.R1: CheckMCTest: result = 0x3FE00
N4.C3.D0.R1.S15: Offset Found: RdPtrOffsetDqs = 007
N6.C2.D0.R0.S08: Offset Found: RdPtrOffsetDqs = 006
N0.C2.D0.R0: CheckMCTest: result = 0x3FE00
N2.C3.D1.R1: CheckMCTest: passed
N4.C3.D0.R1.S16: Offset Found: RdPtrOffsetDqs = 007
N6.C2.D0.R0: Write Training Coarse, upper nibbles
ACCM: D0 0000F0D0 00000000
N2.C3.D1.R1: CheckMCTest: passed
N4.C3.D0.R1.S17: Offset Found: RdPtrOffsetDqs = 006
N6.C2.D0.R0.S09: Dq Delay estimate: 464
ACCM: D0 0000F0D0 00000000
N2.C3.D1.R1.S09: Offset Found: RdPtrOffsetDqs = 007
N4.C3.D1.R0: Write Training Coarse, lower nibbles / bytes
N6.C2.D0.R0.S10: Dq Delay estimate: 453
ACCM: D0 F0F0F0D0 F0F0F0F0
N2.C3.D1.R1.S10: Offset Found: RdPtrOffsetDqs = 007
N4.C3.D1.R0.S00: Dq Delay estimate: 348
N6.C2.D0.R0.S11: Dq Delay estimate: 441
ACCM: D0 F0F0F0D0 F0F0F0F0
N2.C3.D1.R1.S11: Offset Found: RdPtrOffsetDqs = 007
N4.C3.D1.R0.S01: Dq Delay estimate: 462
N6.C2.D0.R0.S12: Dq Delay estimate: 420
N0.C2.D0.R0: CheckMCTest: result = 0x3FE00
N2.C3.D1.R1.S12: Offset Found: RdPtrOffsetDqs = 007
N4.C3.D1.R0.S02: Dq Delay estimate: 452
N6.C2.D0.R0.S13: Dq Delay estimate: 381
N0.C2.D0.R0.S00: Offset Found: RdPtrOffsetDqs = 007
N2.C3.D1.R1.S13: Offset Found: RdPtrOffsetDqs = 006
N4.C3.D1.R0.S03: Dq Delay estimate: 436
N6.C2.D0.R0.S14: Dq Delay estimate: 407
N0.C2.D0.R0.S01: Offset Found: RdPtrOffsetDqs = 007
N2.C3.D1.R1.S14: Offset Found: RdPtrOffsetDqs = 006
N4.C3.D1.R0.S04: Dq Delay estimate: 400
N6.C2.D0.R0.S15: Dq Delay estimate: 410
N0.C2.D0.R0.S02: Offset Found: RdPtrOffsetDqs = 007
N2.C3.D1.R1.S15: Offset Found: RdPtrOffsetDqs = 007
N4.C3.D1.R0.S05: Dq Delay estimate: 411
N6.C2.D0.R0.S16: Dq Delay estimate: 429
N0.C2.D0.R0.S03: Offset Found: RdPtrOffsetDqs = 007
N2.C3.D1.R1.S16: Offset Found: RdPtrOffsetDqs = 007
N4.C3.D1.R0.S06: Dq Delay estimate: 429
N6.C2.D0.R0.S17: Dq Delay estimate: 402
N0.C2.D0.R0.S04: Offset Found: RdPtrOffsetDqs = 006
N2.C3.D1.R1.S17: Offset Found: RdPtrOffsetDqs = 006
N4.C3.D1.R0.S07: Dq Delay estimate: 446
ACCM: F0 F0F0F0F0 F0F0F0F0
N0.C2.D0.R0.S05: Offset Found: RdPtrOffsetDqs = 006
N2.C3: Calculating Optimimum DQS Values
N4.C3.D1.R0.S08: Dq Delay estimate: 419
ACCM: F0 F0F0F0F0 F0F0F0F0
N0.C2.D0.R0.S06: Offset Found: RdPtrOffsetDqs = 006
N2.C3.D0.R0.S00: Total Delay in PI ticks: TxDQS = 1013, TxDQ = 977
ACCM: 0F 0F0F0F0F 0F0F0F0F
ACCM: F0 F0F0F0F0 F0F0F0F0
N0.C2.D0.R0.S07: Offset Found: RdPtrOffsetDqs = 007
N2.C3.D0.R0.S01: Total Delay in PI ticks: TxDQS = 1000, TxDQ = 967
ACCM: 0F 0F0F0F0F 0F0F0F0F
ACCM: F0 F0F0F0F0 F0F0F0F0
N0.C2.D0.R0.S08: Offset Found: RdPtrOffsetDqs = 006
N2.C3.D0.R0.S02: Total Delay in PI ticks: TxDQS = 988, TxDQ = 952
ACCM: 0F 0F0F0F0F 0F0F0F00
N6.C2.D0.R0: CheckMCTest: result = 0x3FE00
N0.C2.D0.R0: Write Training Coarse, upper nibbles
N2.C3.D0.R0.S03: Total Delay in PI ticks: TxDQS = 972, TxDQ = 938
ACCM: 0F FFFF0F0F FFFF0F00
ACCM: F0 F0F0F0F0 F0F0F0F0
N0.C2.D0.R0.S09: Dq Delay estimate: 472
N2.C3.D0.R0.S04: Total Delay in PI ticks: TxDQS = 939, TxDQ = 905
N4.C3.D1.R0: CheckMCTest: result = 0x199FF
ACCM: F0 F0F0F0F0 F0F0F0F0
N0.C2.D0.R0.S10: Dq Delay estimate: 457
N2.C3.D0.R0.S05: Total Delay in PI ticks: TxDQS = 952, TxDQ = 917
ACCM: 0F 0F0F0F0F 0F0F0F0F
ACCM: F0 F0F0F0F0 F0F0F0F0
N0.C2.D0.R0.S11: Dq Delay estimate: 445
N2.C3.D0.R0.S06: Total Delay in PI ticks: TxDQS = 968, TxDQ = 932
ACCM: 0F 0F0F0F0F 0F0F0F0F
ACCM: F0 F0F0F0F0 F0F0F0F0
N0.C2.D0.R0.S12: Dq Delay estimate: 424
N2.C3.D0.R0.S07: Total Delay in PI ticks: TxDQS = 983, TxDQ = 948
ACCM: 0F 0F0F0F0F 0F0F0F00
N6.C2.D0.R0: CheckMCTest: result = 0x3FE00
N0.C2.D0.R0.S13: Dq Delay estimate: 385
N2.C3.D0.R0.S08: Total Delay in PI ticks: TxDQS = 957, TxDQ = 924
ACCM: 0F FFFF0F0F FFFF0F00
ACCM: F0 F0F0F0F0 F0F0F0F0
N0.C2.D0.R0.S14: Dq Delay estimate: 412
N2.C3.D0.R0.S09: Total Delay in PI ticks: TxDQS = 1016, TxDQ = 980
N4.C3.D1.R0: CheckMCTest: result = 0x199FF
ACCM: F0 F0F0F0F0 F0F0F0F0
N0.C2.D0.R0.S15: Dq Delay estimate: 414
N2.C3.D0.R0.S10: Total Delay in PI ticks: TxDQS = 1002, TxDQ = 969
ACCM: 0F 0F0F0F0F 0F0F0F00
ACCM: 00 B0B00000 00B00000
N0.C2.D0.R0.S16: Dq Delay estimate: 433
N2.C3.D0.R0.S11: Total Delay in PI ticks: TxDQS = 988, TxDQ = 952
ACCM: 0F 0F0F0F0F 0F0F0F00
ACCM: 00 B0B00000 00B00000
N0.C2.D0.R0.S17: Dq Delay estimate: 405
N2.C3.D0.R0.S12: Total Delay in PI ticks: TxDQS = 974, TxDQ = 940
ACCM: 0B 0B0B000B 00000000
N6.C2.D0.R0: CheckMCTest: result = 0x3FE00
ACCM: F0 F0F0F0F0 F0F0F0F0
N2.C3.D0.R0.S13: Total Delay in PI ticks: TxDQS = 938, TxDQ = 905
ACCM: 0B FBFB000B F0F00000
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: F0 F0F0F0F0 F0F0F0F0
N2.C3.D0.R0.S14: Total Delay in PI ticks: TxDQS = 953, TxDQ = 918
N4.C3.D1.R0: CheckMCTest: result = 0x199FE
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: F0 F0F0F0F0 F0F0F0F0
N2.C3.D0.R0.S15: Total Delay in PI ticks: TxDQS = 967, TxDQ = 932
ACCM: 0F 0F0F0F0F 0F0F0F00
ACCM: 00 F0F00000 00F00000
ACCM: F0 F0F0F0F0 F0F0F0F0
N2.C3.D0.R0.S16: Total Delay in PI ticks: TxDQS = 982, TxDQ = 946
ACCM: 0F 0F0F0F0F 0F0F0F00
ACCM: 00 F0F00000 00F00000
N0.C2.D0.R0: CheckMCTest: result = 0x3FE00
N2.C3.D0.R0.S17: Total Delay in PI ticks: TxDQS = 956, TxDQ = 925
ACCM: 0F 0F0F000F 00000000
N6.C2.D0.R0: CheckMCTest: result = 0x3FE00
ACCM: F0 F0F0F0F0 F0F0F0F0
N2.C3.D0.R1.S00: Total Delay in PI ticks: TxDQS = 1009, TxDQ = 973
ACCM: 0F FFFF000F F0F00000
N6.C2.D0.R0: CheckMCTest: passed
ACCM: F0 F0F0F0F0 F0F0F0F0
N2.C3.D0.R1.S01: Total Delay in PI ticks: TxDQS = 991, TxDQ = 958
N4.C3.D1.R0: CheckMCTest: result = 0x199FE
N6.C2.D0.R0: CheckMCTest: passed
ACCM: F0 F0F0F0F0 F0F0F0F0
N2.C3.D0.R1.S02: Total Delay in PI ticks: TxDQS = 981, TxDQ = 945
N4.C3.D1.R0.S00: Offset Found: RdPtrOffsetDqs = 008
N6.C2.D0.R0.S09: Offset Found: RdPtrOffsetDqs = 007
ACCM: F0 F0F0F0F0 F0F0F0F0
N2.C3.D0.R1.S03: Total Delay in PI ticks: TxDQS = 966, TxDQ = 932
ACCM: 00 00000000 00000000
N6.C2.D0.R0.S10: Offset Found: RdPtrOffsetDqs = 007
N0.C2.D0.R0: CheckMCTest: result = 0x3FE00
N2.C3.D0.R1.S04: Total Delay in PI ticks: TxDQS = 932, TxDQ = 898
ACCM: 00 00000000 00000000
N6.C2.D0.R0.S11: Offset Found: RdPtrOffsetDqs = 007
ACCM: F0 F0F0F0F0 F0F0F0F0
N2.C3.D0.R1.S05: Total Delay in PI ticks: TxDQS = 945, TxDQ = 910
ACCM: 00 00000000 00000000
N6.C2.D0.R0.S12: Offset Found: RdPtrOffsetDqs = 007
ACCM: F0 F0F0F0F0 F0F0F0F0
N2.C3.D0.R1.S06: Total Delay in PI ticks: TxDQS = 960, TxDQ = 924
ACCM: 00 F0F00000 F0F00000
N6.C2.D0.R0.S13: Offset Found: RdPtrOffsetDqs = 006
ACCM: B0 B00000B0 B00000B0
N2.C3.D0.R1.S07: Total Delay in PI ticks: TxDQS = 976, TxDQ = 941
N4.C3.D1.R0: CheckMCTest: result = 0x19800
N6.C2.D0.R0.S14: Offset Found: RdPtrOffsetDqs = 006
ACCM: B0 B00000B0 B00000B0
N2.C3.D0.R1.S08: Total Delay in PI ticks: TxDQS = 949, TxDQ = 916
ACCM: 00 00000000 00000000
N6.C2.D0.R0.S15: Offset Found: RdPtrOffsetDqs = 006
N0.C2.D0.R0: CheckMCTest: result = 0x3FE00
N2.C3.D0.R1.S09: Total Delay in PI ticks: TxDQS = 1007, TxDQ = 972
ACCM: 00 00000000 00000000
N6.C2.D0.R0.S16: Offset Found: RdPtrOffsetDqs = 007
ACCM: F0 F0F0F0F0 F0F0F0F0
N2.C3.D0.R1.S10: Total Delay in PI ticks: TxDQS = 992, TxDQ = 959
ACCM: 00 00000000 00000000
N6.C2.D0.R0.S17: Offset Found: RdPtrOffsetDqs = 006
ACCM: F0 F0F0F0F0 F0F0F0F0
N2.C3.D0.R1.S11: Total Delay in PI ticks: TxDQS = 982, TxDQ = 947
ACCM: 00 F0F00000 F0F00000
N6.C2.D0.R1: Write Training Coarse, lower nibbles / bytes
ACCM: B0 F00000F0 F00000F0
N2.C3.D0.R1.S12: Total Delay in PI ticks: TxDQS = 968, TxDQ = 935
N4.C3.D1.R0: CheckMCTest: result = 0x19800
N6.C2.D0.R1.S00: Dq Delay estimate: 460
ACCM: B0 F00000F0 F00000F0
N2.C3.D0.R1.S13: Total Delay in PI ticks: TxDQS = 932, TxDQ = 899
N4.C3.D1.R0.S00: Offset Found: RdPtrOffsetDqs = 008
N6.C2.D0.R1.S01: Dq Delay estimate: 441
N0.C2.D0.R0: CheckMCTest: result = 0x3FE00
N2.C3.D0.R1.S14: Total Delay in PI ticks: TxDQS = 946, TxDQ = 911
N4.C3.D1.R0.S01: Offset Found: RdPtrOffsetDqs = 007
N6.C2.D0.R1.S02: Dq Delay estimate: 431
N0.C2.D0.R0: CheckMCTest: passed
N2.C3.D0.R1.S15: Total Delay in PI ticks: TxDQS = 960, TxDQ = 925
N4.C3.D1.R0.S02: Offset Found: RdPtrOffsetDqs = 007
N6.C2.D0.R1.S03: Dq Delay estimate: 413
N0.C2.D0.R0: CheckMCTest: passed
N2.C3.D0.R1.S16: Total Delay in PI ticks: TxDQS = 978, TxDQ = 941
N4.C3.D1.R0.S03: Offset Found: RdPtrOffsetDqs = 007
N6.C2.D0.R1.S04: Dq Delay estimate: 374
N0.C2.D0.R0.S09: Offset Found: RdPtrOffsetDqs = 007
N2.C3.D0.R1.S17: Total Delay in PI ticks: TxDQS = 949, TxDQ = 917
N4.C3.D1.R0.S04: Offset Found: RdPtrOffsetDqs = 006
N6.C2.D0.R1.S05: Dq Delay estimate: 402
N0.C2.D0.R0.S10: Offset Found: RdPtrOffsetDqs = 007
N2.C3.D1.R0.S00: Total Delay in PI ticks: TxDQS = 1020, TxDQ = 982
N4.C3.D1.R0.S05: Offset Found: RdPtrOffsetDqs = 007
N6.C2.D0.R1.S06: Dq Delay estimate: 401
N0.C2.D0.R0.S11: Offset Found: RdPtrOffsetDqs = 007
N2.C3.D1.R0.S01: Total Delay in PI ticks: TxDQS = 1005, TxDQ = 971
N4.C3.D1.R0.S06: Offset Found: RdPtrOffsetDqs = 007
N6.C2.D0.R1.S07: Dq Delay estimate: 422
N0.C2.D0.R0.S12: Offset Found: RdPtrOffsetDqs = 007
N2.C3.D1.R0.S02: Total Delay in PI ticks: TxDQS = 993, TxDQ = 956
N4.C3.D1.R0.S07: Offset Found: RdPtrOffsetDqs = 007
N6.C2.D0.R1.S08: Dq Delay estimate: 389
N0.C2.D0.R0.S13: Offset Found: RdPtrOffsetDqs = 006
N2.C3.D1.R0.S03: Total Delay in PI ticks: TxDQS = 979, TxDQ = 944
N4.C3.D1.R0.S08: Offset Found: RdPtrOffsetDqs = 007
ACCM: 0F 0F0F0F0F 0F0F0F0F
N0.C2.D0.R0.S14: Offset Found: RdPtrOffsetDqs = 006
N2.C3.D1.R0.S04: Total Delay in PI ticks: TxDQS = 944, TxDQ = 907
N4.C3.D1.R0: Write Training Coarse, upper nibbles
ACCM: 0F 0F0F0F0F 0F0F0F0F
N0.C2.D0.R0.S15: Offset Found: RdPtrOffsetDqs = 007
N2.C3.D1.R0.S05: Total Delay in PI ticks: TxDQS = 958, TxDQ = 922
N4.C3.D1.R0.S09: Dq Delay estimate: 349
ACCM: 0F 0F0F0F0F 0F0F0F0F
N0.C2.D0.R0.S16: Offset Found: RdPtrOffsetDqs = 007
N2.C3.D1.R0.S06: Total Delay in PI ticks: TxDQS = 971, TxDQ = 934
N4.C3.D1.R0.S10: Dq Delay estimate: 465
ACCM: 0F 0F0F0F0F 0F0F0F0F
N0.C2.D0.R0.S17: Offset Found: RdPtrOffsetDqs = 006
N2.C3.D1.R0.S07: Total Delay in PI ticks: TxDQS = 989, TxDQ = 952
N4.C3.D1.R0.S11: Dq Delay estimate: 453
N6.C2.D0.R1: CheckMCTest: result = 0x1FF
N0.C2.D0.R1: Write Training Coarse, lower nibbles / bytes
N2.C3.D1.R0.S08: Total Delay in PI ticks: TxDQS = 960, TxDQ = 924
N4.C3.D1.R0.S12: Dq Delay estimate: 440
ACCM: 0F 0F0F0F0F 0F0F0F0F
N0.C2.D0.R1.S00: Dq Delay estimate: 462
N2.C3.D1.R0.S09: Total Delay in PI ticks: TxDQS = 1019, TxDQ = 982
N4.C3.D1.R0.S13: Dq Delay estimate: 402
ACCM: 0F 0F0F0F0F 0F0F0F0F
N0.C2.D0.R1.S01: Dq Delay estimate: 447
N2.C3.D1.R0.S10: Total Delay in PI ticks: TxDQS = 1005, TxDQ = 970
N4.C3.D1.R0.S14: Dq Delay estimate: 416
ACCM: 0F 0F0F0F0F 0F0F0F0F
N0.C2.D0.R1.S02: Dq Delay estimate: 439
N2.C3.D1.R0.S11: Total Delay in PI ticks: TxDQS = 992, TxDQ = 956
N4.C3.D1.R0.S15: Dq Delay estimate: 428
ACCM: 0F 0F0F0F0F 0F0F0F0F
N0.C2.D0.R1.S03: Dq Delay estimate: 420
N2.C3.D1.R0.S12: Total Delay in PI ticks: TxDQS = 979, TxDQ = 944
N4.C3.D1.R0.S16: Dq Delay estimate: 447
N6.C2.D0.R1: CheckMCTest: result = 0x1FF
N0.C2.D0.R1.S04: Dq Delay estimate: 382
N2.C3.D1.R0.S13: Total Delay in PI ticks: TxDQS = 945, TxDQ = 910
N4.C3.D1.R0.S17: Dq Delay estimate: 417
ACCM: 0F 0F0F0F0F 0F0F0F0F
N0.C2.D0.R1.S05: Dq Delay estimate: 409
N2.C3.D1.R0.S14: Total Delay in PI ticks: TxDQS = 956, TxDQ = 920
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: 0F 0F0F0F0F 0F0F0F0F
N0.C2.D0.R1.S06: Dq Delay estimate: 404
N2.C3.D1.R0.S15: Total Delay in PI ticks: TxDQS = 970, TxDQ = 934
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: 00 0000000B 0000000B
N0.C2.D0.R1.S07: Dq Delay estimate: 428
N2.C3.D1.R0.S16: Total Delay in PI ticks: TxDQS = 989, TxDQ = 952
ACCM: F0 F0F0F0F0 F0F0F000
ACCM: 00 0000000B 0000000B
N0.C2.D0.R1.S08: Dq Delay estimate: 398
N2.C3.D1.R0.S17: Total Delay in PI ticks: TxDQS = 960, TxDQ = 925
ACCM: F0 F0F0F0F0 F0F0F000
N6.C2.D0.R1: CheckMCTest: result = 0x1FF
ACCM: 0F 0F0F0F0F 0F0F0F0F
N2.C3.D1.R1.S00: Total Delay in PI ticks: TxDQS = 1017, TxDQ = 979
N4.C3.D1.R0: CheckMCTest: result = 0x3FE00
ACCM: 0F 0F0F0F0F 0F0F0F0F
ACCM: 0F 0F0F0F0F 0F0F0F0F
N2.C3.D1.R1.S01: Total Delay in PI ticks: TxDQS = 1001, TxDQ = 966
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: 0F 0F0F0F0F 0F0F0F0F
ACCM: 0F 0F0F0F0F 0F0F0F0F
N2.C3.D1.R1.S02: Total Delay in PI ticks: TxDQS = 988, TxDQ = 951
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: 00 0000000F 0000000F
ACCM: 0F 0F0F0F0F 0F0F0F0F
N2.C3.D1.R1.S03: Total Delay in PI ticks: TxDQS = 976, TxDQ = 941
ACCM: F0 F0F0F0F0 F0F0F000
ACCM: 00 0000000F 0000000F
N0.C2.D0.R1: CheckMCTest: result = 0x1FF
N2.C3.D1.R1.S04: Total Delay in PI ticks: TxDQS = 940, TxDQ = 904
ACCM: F0 F0F0F0F0 F0F0F000
N6.C2.D0.R1: CheckMCTest: result = 0x1FF
ACCM: 0F 0F0F0F0F 0F0F0F0F
N2.C3.D1.R1.S05: Total Delay in PI ticks: TxDQS = 954, TxDQ = 918
N4.C3.D1.R0: CheckMCTest: result = 0x3FE00
N6.C2.D0.R1: CheckMCTest: passed
ACCM: 0F 0F0F0F0F 0F0F0F0F
N2.C3.D1.R1.S06: Total Delay in PI ticks: TxDQS = 967, TxDQ = 930
ACCM: F0 F0F0F0F0 F0F0F000
N6.C2.D0.R1: CheckMCTest: passed
ACCM: 0F 0F0F0F0F 0F0F0F0F
N2.C3.D1.R1.S07: Total Delay in PI ticks: TxDQS = 986, TxDQ = 949
ACCM: F0 F0F0F0F0 F0F0F000
N6.C2.D0.R1.S00: Offset Found: RdPtrOffsetDqs = 007
ACCM: 0F 0F0F0F0F 0F0F0F0F
N2.C3.D1.R1.S08: Total Delay in PI ticks: TxDQS = 955, TxDQ = 919
ACCM: 00 0000B000 B000B000
N6.C2.D0.R1.S01: Offset Found: RdPtrOffsetDqs = 007
N0.C2.D0.R1: CheckMCTest: result = 0x1FF
N2.C3.D1.R1.S09: Total Delay in PI ticks: TxDQS = 1016, TxDQ = 979
ACCM: 00 0000B000 B000B000
N6.C2.D0.R1.S02: Offset Found: RdPtrOffsetDqs = 007
ACCM: 0F 0F0F0F0F 0F0F0F0F
N2.C3.D1.R1.S10: Total Delay in PI ticks: TxDQS = 1001, TxDQ = 966
N4.C3.D1.R0: CheckMCTest: result = 0x3FC00
N6.C2.D0.R1.S03: Offset Found: RdPtrOffsetDqs = 006
ACCM: 0F 0F0F0F0F 0F0F0F0F
N2.C3.D1.R1.S11: Total Delay in PI ticks: TxDQS = 989, TxDQ = 953
ACCM: F0 F0F0F0F0 F0F0F000
N6.C2.D0.R1.S04: Offset Found: RdPtrOffsetDqs = 006
ACCM: 0B 0B0B0B0B 0B000000
N2.C3.D1.R1.S12: Total Delay in PI ticks: TxDQS = 976, TxDQ = 940
ACCM: F0 F0F0F0F0 F0F0F000
N6.C2.D0.R1.S05: Offset Found: RdPtrOffsetDqs = 006
ACCM: 0B 0B0B0B0B 0B000000
N2.C3.D1.R1.S13: Total Delay in PI ticks: TxDQS = 940, TxDQ = 904
ACCM: 00 0000F000 F000F000
N6.C2.D0.R1.S06: Offset Found: RdPtrOffsetDqs = 006
N0.C2.D0.R1: CheckMCTest: result = 0x1FF
N2.C3.D1.R1.S14: Total Delay in PI ticks: TxDQS = 953, TxDQ = 916
ACCM: 00 0000F000 F000F000
N6.C2.D0.R1.S07: Offset Found: RdPtrOffsetDqs = 007
ACCM: 0F 0F0F0F0F 0F0F0F0F
N2.C3.D1.R1.S15: Total Delay in PI ticks: TxDQS = 967, TxDQ = 931
N4.C3.D1.R0: CheckMCTest: result = 0x3FC00
N6.C2.D0.R1.S08: Offset Found: RdPtrOffsetDqs = 006
ACCM: 0F 0F0F0F0F 0F0F0F0F
N2.C3.D1.R1.S16: Total Delay in PI ticks: TxDQS = 985, TxDQ = 948
N4.C3.D1.R0.S09: Offset Found: RdPtrOffsetDqs = 008
N6.C2.D0.R1: Write Training Coarse, upper nibbles
ACCM: 0F 0F0F0F0F 0B000000
N2.C3.D1.R1.S17: Total Delay in PI ticks: TxDQS = 954, TxDQ = 919
N4.C3.D1.R0: CheckMCTest: passed
N6.C2.D0.R1.S09: Dq Delay estimate: 453
ACCM: 0F 0F0F0F0F 0B000000
N2: END WRITE LEVEL COARSE:
N4.C3.D1.R0: CheckMCTest: passed
N6.C2.D0.R1.S10: Dq Delay estimate: 444
N0.C2.D0.R1: CheckMCTest: result = 0x1FF
N2: RunTrainStep: Final status = 0
N4.C3.D1.R0.S09: Offset Found: RdPtrOffsetDqs = 008
N6.C2.D0.R1.S11: Dq Delay estimate: 433
N0.C2.D0.R1: CheckMCTest: passed

END - Basic Write Level Training       Time         38666 ms
N4.C3.D1.R0.S10: Offset Found: RdPtrOffsetDqs = 007
N6.C2.D0.R1.S12: Dq Delay estimate: 417
N0.C2.D0.R1: CheckMCTest: passed

START - Basic Write DQ/DQS Training
N4.C3.D1.R0.S11: Offset Found: RdPtrOffsetDqs = 007
N6.C2.D0.R1.S13: Dq Delay estimate: 375
N0.C2.D0.R1.S00: Offset Found: RdPtrOffsetDqs = 007
N2.C0.D0.R0.S00: wrcmd2dqsstartlatency: 04
N4.C3.D1.R0.S12: Offset Found: RdPtrOffsetDqs = 007
N6.C2.D0.R1.S14: Dq Delay estimate: 404
N0.C2.D0.R1.S01: Offset Found: RdPtrOffsetDqs = 007
N2.C0.D0.R0.S00: RdPtrOffsetTxDq: 06
N4.C3.D1.R0.S13: Offset Found: RdPtrOffsetDqs = 006
N6.C2.D0.R1.S15: Dq Delay estimate: 404
N0.C2.D0.R1.S02: Offset Found: RdPtrOffsetDqs = 007
N2.C0.D0.R0.S00: RdPtrOffsetTxDqs: 07
N4.C3.D1.R0.S14: Offset Found: RdPtrOffsetDqs = 007
N6.C2.D0.R1.S16: Dq Delay estimate: 423
N0.C2.D0.R1.S03: Offset Found: RdPtrOffsetDqs = 007
N2.C0.D0.R0.S00: PiTxDqs: 51
N4.C3.D1.R0.S15: Offset Found: RdPtrOffsetDqs = 007
N6.C2.D0.R1.S17: Dq Delay estimate: 395
N0.C2.D0.R1.S04: Offset Found: RdPtrOffsetDqs = 006
N2.C0.D0.R0.S01: wrcmd2dqsstartlatency: 04
N4.C3.D1.R0.S16: Offset Found: RdPtrOffsetDqs = 007
ACCM: F0 F0F0F0F0 F0F0F0F0
N0.C2.D0.R1.S05: Offset Found: RdPtrOffsetDqs = 006
N2.C0.D0.R0.S01: RdPtrOffsetTxDq: 06
N4.C3.D1.R0.S17: Offset Found: RdPtrOffsetDqs = 007
ACCM: F0 F0F0F0F0 F0F0F0F0
N0.C2.D0.R1.S06: Offset Found: RdPtrOffsetDqs = 006
N2.C0.D0.R0.S01: RdPtrOffsetTxDqs: 07
N4.C3.D1.R1: Write Training Coarse, lower nibbles / bytes
ACCM: F0 F0F0F0F0 F0F0F0F0
N0.C2.D0.R1.S07: Offset Found: RdPtrOffsetDqs = 007
N2.C0.D0.R0.S01: PiTxDqs: 32
N4.C3.D1.R1.S00: Dq Delay estimate: 347
ACCM: F0 F0F0F0F0 F0F0F0F0
N0.C2.D0.R1.S08: Offset Found: RdPtrOffsetDqs = 006
N2.C0.D0.R0.S02: wrcmd2dqsstartlatency: 04
N4.C3.D1.R1.S01: Dq Delay estimate: 458
N6.C2.D0.R1: CheckMCTest: result = 0x3FE00
N0.C2.D0.R1: Write Training Coarse, upper nibbles
N2.C0.D0.R0.S02: RdPtrOffsetTxDq: 05
N4.C3.D1.R1.S02: Dq Delay estimate: 448
ACCM: F0 F0F0F0F0 F0F0F0F0
N0.C2.D0.R1.S09: Dq Delay estimate: 464
N2.C0.D0.R0.S02: RdPtrOffsetTxDqs: 07
N4.C3.D1.R1.S03: Dq Delay estimate: 436
ACCM: F0 F0F0F0F0 F0F0F0F0
N0.C2.D0.R1.S10: Dq Delay estimate: 450
N2.C0.D0.R0.S02: PiTxDqs: 22
N4.C3.D1.R1.S04: Dq Delay estimate: 396
ACCM: F0 F0F0F0F0 F0F0F0F0
N0.C2.D0.R1.S11: Dq Delay estimate: 438
N2.C0.D0.R0.S03: wrcmd2dqsstartlatency: 04
N4.C3.D1.R1.S05: Dq Delay estimate: 410
ACCM: F0 F0F0F0F0 F0F0F0F0
N0.C2.D0.R1.S12: Dq Delay estimate: 421
N2.C0.D0.R0.S03: RdPtrOffsetTxDq: 05
N4.C3.D1.R1.S06: Dq Delay estimate: 423
N6.C2.D0.R1: CheckMCTest: result = 0x3FE00
N0.C2.D0.R1.S13: Dq Delay estimate: 381
N2.C0.D0.R0.S03: RdPtrOffsetTxDqs: 07
N4.C3.D1.R1.S07: Dq Delay estimate: 442
ACCM: F0 F0F0F0F0 F0F0F0F0
N0.C2.D0.R1.S14: Dq Delay estimate: 407
N2.C0.D0.R0.S03: PiTxDqs: 02
N4.C3.D1.R1.S08: Dq Delay estimate: 414
ACCM: F0 F0F0F0F0 F0F0F0F0
N0.C2.D0.R1.S15: Dq Delay estimate: 406
N2.C0.D0.R0.S04: wrcmd2dqsstartlatency: 04
ACCM: 0F 0F0F0F0F 0F0F0F0F
ACCM: 00 0000B000 00000000
N0.C2.D0.R1.S16: Dq Delay estimate: 430
N2.C0.D0.R0.S04: RdPtrOffsetTxDq: 04
ACCM: 0F 0F0F0F0F 0F0F0F0F
ACCM: 00 0000B000 00000000
N0.C2.D0.R1.S17: Dq Delay estimate: 396
N2.C0.D0.R0.S04: RdPtrOffsetTxDqs: 06
ACCM: 0F 0F0F0F0F 0F0F0F00
N6.C2.D0.R1: CheckMCTest: result = 0x3FE00
ACCM: F0 F0F0F0F0 F0F0F0F0
N2.C0.D0.R0.S04: PiTxDqs: 34
ACCM: 0F 0F0F0F0F 0F0F0F00
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: F0 F0F0F0F0 F0F0F0F0
N2.C0.D0.R0.S05: wrcmd2dqsstartlatency: 04
N4.C3.D1.R1: CheckMCTest: result = 0x1FF
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: F0 F0F0F0F0 F0F0F0F0
N2.C0.D0.R0.S05: RdPtrOffsetTxDq: 05
ACCM: 0F 0F0F0F0F 0F0F0F0F
ACCM: 00 0000F000 00000000
ACCM: F0 F0F0F0F0 F0F0F0F0
N2.C0.D0.R0.S05: RdPtrOffsetTxDqs: 06
ACCM: 0F 0F0F0F0F 0F0F0F0F
ACCM: 00 0000F000 00000000
N0.C2.D0.R1: CheckMCTest: result = 0x3FE00
N2.C0.D0.R0.S05: PiTxDqs: 52
ACCM: 0F 0F0F0F0F 0F0F0F00
N6.C2.D0.R1: CheckMCTest: result = 0x3FE00
ACCM: F0 F0F0F0F0 F0F0F0F0
N2.C0.D0.R0.S06: wrcmd2dqsstartlatency: 04
ACCM: 0F 0F0F0F0F 0F0F0F00
N6.C2.D0.R1: CheckMCTest: passed
ACCM: F0 F0F0F0F0 F0F0F0F0
N2.C0.D0.R0.S06: RdPtrOffsetTxDq: 05
N4.C3.D1.R1: CheckMCTest: result = 0x1FF
N6.C2.D0.R1: CheckMCTest: passed
ACCM: F0 F0F0F0F0 F0F0F0F0
N2.C0.D0.R0.S06: RdPtrOffsetTxDqs: 06
ACCM: 0F 0F0F0F0F 0F0F0F00
N6.C2.D0.R1.S09: Offset Found: RdPtrOffsetDqs = 007
ACCM: F0 F0F0F0F0 F0F0F0F0
N2.C0.D0.R0.S06: PiTxDqs: 57
ACCM: 0F 0F0F0F0F 0F0F0F00
N6.C2.D0.R1.S10: Offset Found: RdPtrOffsetDqs = 007
N0.C2.D0.R1: CheckMCTest: result = 0x3FE00
N2.C0.D0.R0.S07: wrcmd2dqsstartlatency: 04
ACCM: 00 000B0B00 0B000000
N6.C2.D0.R1.S11: Offset Found: RdPtrOffsetDqs = 007
ACCM: F0 F0F0F0F0 F0F0F0F0
N2.C0.D0.R0.S07: RdPtrOffsetTxDq: 05
ACCM: 00 000B0B00 0B000000
N6.C2.D0.R1.S12: Offset Found: RdPtrOffsetDqs = 007
ACCM: F0 F0F0F0F0 F0F0F0F0
N2.C0.D0.R0.S07: RdPtrOffsetTxDqs: 07
N4.C3.D1.R1: CheckMCTest: result = 0x1FE
N6.C2.D0.R1.S13: Offset Found: RdPtrOffsetDqs = 006
ACCM: 00 B000B000 000000B0
N2.C0.D0.R0.S07: PiTxDqs: 06
ACCM: 0F 0F0F0F0F 0F0F0F00
N6.C2.D0.R1.S14: Offset Found: RdPtrOffsetDqs = 006
ACCM: 00 B000B000 000000B0
N2.C0.D0.R0.S08: wrcmd2dqsstartlatency: 04
ACCM: 0F 0F0F0F0F 0F0F0F00
N6.C2.D0.R1.S15: Offset Found: RdPtrOffsetDqs = 006
N0.C2.D0.R1: CheckMCTest: result = 0x3FE00
N2.C0.D0.R0.S08: RdPtrOffsetTxDq: 05
ACCM: 00 000B0F00 0F000000
N6.C2.D0.R1.S16: Offset Found: RdPtrOffsetDqs = 007
ACCM: F0 F0F0F0F0 F0F0F0F0
N2.C0.D0.R0.S08: RdPtrOffsetTxDqs: 06
ACCM: 00 000B0F00 0F000000
N6.C2.D0.R1.S17: Offset Found: RdPtrOffsetDqs = 006
ACCM: F0 F0F0F0F0 F0F0F0F0
N2.C0.D0.R0.S08: PiTxDqs: 48
N4.C3.D1.R1: CheckMCTest: result = 0x1FE
N6.C2.D1.R0: Write Training Coarse, lower nibbles / bytes
ACCM: 00 F000F000 000000B0
N2.C0.D0.R0.S09: wrcmd2dqsstartlatency: 04
N4.C3.D1.R1.S00: Offset Found: RdPtrOffsetDqs = 008
N6.C2.D1.R0.S00: Dq Delay estimate: 470
ACCM: 00 F000F000 000000B0
N2.C0.D0.R0.S09: RdPtrOffsetTxDq: 06
N4.C3.D1.R1: CheckMCTest: passed
N6.C2.D1.R0.S01: Dq Delay estimate: 453
N0.C2.D0.R1: CheckMCTest: result = 0x3FE00
N2.C0.D0.R0.S09: RdPtrOffsetTxDqs: 07
N4.C3.D1.R1: CheckMCTest: passed
N6.C2.D1.R0.S02: Dq Delay estimate: 445
N0.C2.D0.R1: CheckMCTest: passed
N2.C0.D0.R0.S09: PiTxDqs: 54
N4.C3.D1.R1.S00: Offset Found: RdPtrOffsetDqs = 008
N6.C2.D1.R0.S03: Dq Delay estimate: 429
N0.C2.D0.R1: CheckMCTest: passed
N2.C0.D0.R0.S10: wrcmd2dqsstartlatency: 04
N4.C3.D1.R1.S01: Offset Found: RdPtrOffsetDqs = 007
N6.C2.D1.R0.S04: Dq Delay estimate: 388
N0.C2.D0.R1.S09: Offset Found: RdPtrOffsetDqs = 007
N2.C0.D0.R0.S10: RdPtrOffsetTxDq: 06
N4.C3.D1.R1.S02: Offset Found: RdPtrOffsetDqs = 007
N6.C2.D1.R0.S05: Dq Delay estimate: 416
N0.C2.D0.R1.S10: Offset Found: RdPtrOffsetDqs = 007
N2.C0.D0.R0.S10: RdPtrOffsetTxDqs: 07
N4.C3.D1.R1.S03: Offset Found: RdPtrOffsetDqs = 007
N6.C2.D1.R0.S06: Dq Delay estimate: 413
N0.C2.D0.R1.S11: Offset Found: RdPtrOffsetDqs = 007
N2.C0.D0.R0.S10: PiTxDqs: 33
N4.C3.D1.R1.S04: Offset Found: RdPtrOffsetDqs = 006
N6.C2.D1.R0.S07: Dq Delay estimate: 436
N0.C2.D0.R1.S12: Offset Found: RdPtrOffsetDqs = 007
N2.C0.D0.R0.S11: wrcmd2dqsstartlatency: 04
N4.C3.D1.R1.S05: Offset Found: RdPtrOffsetDqs = 007
N6.C2.D1.R0.S08: Dq Delay estimate: 400
N0.C2.D0.R1.S13: Offset Found: RdPtrOffsetDqs = 006
N2.C0.D0.R0.S11: RdPtrOffsetTxDq: 05
N4.C3.D1.R1.S06: Offset Found: RdPtrOffsetDqs = 007
ACCM: 0F 0F0F0F0F 0F0F0F0F
N0.C2.D0.R1.S14: Offset Found: RdPtrOffsetDqs = 006
N2.C0.D0.R0.S11: RdPtrOffsetTxDqs: 07
N4.C3.D1.R1.S07: Offset Found: RdPtrOffsetDqs = 007
ACCM: 0F 0F0F0F0F 0F0F0F0F
N0.C2.D0.R1.S15: Offset Found: RdPtrOffsetDqs = 006
N2.C0.D0.R0.S11: PiTxDqs: 21
N4.C3.D1.R1.S08: Offset Found: RdPtrOffsetDqs = 007
ACCM: 0F 0F0F0F0F 0F0F0F0F
N0.C2.D0.R1.S16: Offset Found: RdPtrOffsetDqs = 007
N2.C0.D0.R0.S12: wrcmd2dqsstartlatency: 04
N4.C3.D1.R1: Write Training Coarse, upper nibbles
ACCM: 0F FF0F0FFF FFFFFF0F
N0.C2.D0.R1.S17: Offset Found: RdPtrOffsetDqs = 006
N2.C0.D0.R0.S12: RdPtrOffsetTxDq: 05
N4.C3.D1.R1.S09: Dq Delay estimate: 346
N6.C2.D1.R0: CheckMCTest: result = 0x13DFF
N0.C2.D1.R0: Write Training Coarse, lower nibbles / bytes
N2.C0.D0.R0.S12: RdPtrOffsetTxDqs: 07
N4.C3.D1.R1.S10: Dq Delay estimate: 461
ACCM: 0F 0F0F0F0F 0F0F0F0F
N0.C2.D1.R0.S00: Dq Delay estimate: 470
N2.C0.D0.R0.S12: PiTxDqs: 04
N4.C3.D1.R1.S11: Dq Delay estimate: 451
ACCM: 0F 0F0F0F0F 0F0F0F0F
N0.C2.D1.R0.S01: Dq Delay estimate: 453
N2.C0.D0.R0.S13: wrcmd2dqsstartlatency: 04
N4.C3.D1.R1.S12: Dq Delay estimate: 437
ACCM: 0F 0F0F0F0F 0F0F0F0F
N0.C2.D1.R0.S02: Dq Delay estimate: 446
N2.C0.D0.R0.S13: RdPtrOffsetTxDq: 05
N4.C3.D1.R1.S13: Dq Delay estimate: 401
ACCM: 0F FF0F0FFF FFFFFF0F
N0.C2.D1.R0.S03: Dq Delay estimate: 428
N2.C0.D0.R0.S13: RdPtrOffsetTxDqs: 06
N4.C3.D1.R1.S14: Dq Delay estimate: 412
N6.C2.D1.R0: CheckMCTest: result = 0x13DFF
N0.C2.D1.R0.S04: Dq Delay estimate: 387
N2.C0.D0.R0.S13: PiTxDqs: 36
N4.C3.D1.R1.S15: Dq Delay estimate: 425
ACCM: 0F 0F0F0F0F 0F0F0F0F
N0.C2.D1.R0.S05: Dq Delay estimate: 416
N2.C0.D0.R0.S14: wrcmd2dqsstartlatency: 04
N4.C3.D1.R1.S16: Dq Delay estimate: 446
ACCM: 0F 0F0F0F0F 0F0F0F0F
N0.C2.D1.R0.S06: Dq Delay estimate: 412
N2.C0.D0.R0.S14: RdPtrOffsetTxDq: 05
N4.C3.D1.R1.S17: Dq Delay estimate: 412
ACCM: 00 0B0B000B 0B000000
N0.C2.D1.R0.S07: Dq Delay estimate: 435
N2.C0.D0.R0.S14: RdPtrOffsetTxDqs: 06
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: 00 FB0B00FB FBF0F000
N0.C2.D1.R0.S08: Dq Delay estimate: 404
N2.C0.D0.R0.S14: PiTxDqs: 52
ACCM: F0 F0F0F0F0 F0F0F0F0
N6.C2.D1.R0: CheckMCTest: result = 0x13DFF
ACCM: 0F 0F0F0F0F 0F0F0F0F
N2.C0.D0.R0.S15: wrcmd2dqsstartlatency: 04
ACCM: F0 F0F0F0F0 F0F0F0D0
ACCM: 0F 0F0F0F0F 0F0F0F0F
ACCM: 0F 0F0F0F0F 0F0F0F0F
N2.C0.D0.R0.S15: RdPtrOffsetTxDq: 05
ACCM: F0 F0F0F0F0 F0F0F0D0
ACCM: 0F 0F0F0F0F 0F0F0F0F
ACCM: 0F 0F0F0F0F 0F0F0F0F
N2.C0.D0.R0.S15: RdPtrOffsetTxDqs: 06
N4.C3.D1.R1: CheckMCTest: result = 0x3FE00
ACCM: 00 0F0F0D0F 0F000000
ACCM: 0F FF0F0FFF FFFF0F0F
N2.C0.D0.R0.S15: PiTxDqs: 55
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: 00 FF0F0DFF FFF0F000
N0.C2.D1.R0: CheckMCTest: result = 0x139FF
N2.C0.D0.R0.S16: wrcmd2dqsstartlatency: 04
ACCM: F0 F0F0F0F0 F0F0F0F0
N6.C2.D1.R0: CheckMCTest: result = 0x13DFF
ACCM: 0F 0F0F0F0F 0F0F0F0F
N2.C0.D0.R0.S16: RdPtrOffsetTxDq: 05
ACCM: F0 F0F0F0F0 F0F0F0D0
ACCM: 00 00000000 00000000
ACCM: 0F 0F0F0F0F 0F0F0F0F
N2.C0.D0.R0.S16: RdPtrOffsetTxDqs: 07
ACCM: F0 F0F0F0F0 F0F0F0D0
ACCM: 00 00000000 00000000
ACCM: 0F 0F0F0F0F 0F0F0F0F
N2.C0.D0.R0.S16: PiTxDqs: 06
N4.C3.D1.R1: CheckMCTest: result = 0x3FE00
ACCM: 00 00000000 00000000
ACCM: 0F FF0F0FFF FFFF0F0F
N2.C0.D0.R0.S17: wrcmd2dqsstartlatency: 04
ACCM: F0 F0F0F0F0 F0F0F000
ACCM: 00 F00000F0 F0F0F000
N0.C2.D1.R0: CheckMCTest: result = 0x139FF
N2.C0.D0.R0.S17: RdPtrOffsetTxDq: 05
ACCM: F0 F0F0F0F0 F0F0F000
N6.C2.D1.R0: CheckMCTest: result = 0x13C00
ACCM: 0F 0F0F0F0F 0F0F0F0F
N2.C0.D0.R0.S17: RdPtrOffsetTxDqs: 06
ACCM: 00 B00000B0 00000000
ACCM: 00 00000000 00000000
ACCM: 0F 0F0F0F0F 0F0F0F0F
N2.C0.D0.R0.S17: PiTxDqs: 48
ACCM: 00 B00000B0 00000000
ACCM: 00 00000000 00000000
ACCM: 0B 000B000B 0B0B0B0B
N2.C0.D0.R0.S00: RdPtrOffsetTxDq: 07
N4.C3.D1.R1: CheckMCTest: result = 0x3FC00
ACCM: 00 00000000 00000000
ACCM: 0B F00B00FB FBFB0B0B
N2.C0.D0.R0.S01: RdPtrOffsetTxDq: 07
ACCM: F0 F0F0F0F0 F0F0F000
ACCM: 00 F00000F0 F0F0F000
N0.C2.D1.R0: CheckMCTest: result = 0x139FF
N2.C0.D0.R0.S02: RdPtrOffsetTxDq: 06
ACCM: F0 F0F0F0F0 F0F0F000
N6.C2.D1.R0: CheckMCTest: result = 0x13C00
ACCM: 0F 0F0F0F0F 0F0F0F0F
N2.C0.D0.R0.S03: RdPtrOffsetTxDq: 06
ACCM: 00 F00000F0 0000D000
N6.C2.D1.R0.S00: Offset Found: RdPtrOffsetDqs = 007
ACCM: 0F 0F0F0F0F 0F0F0F0F
N2.C0.D0.R0.S04: RdPtrOffsetTxDq: 05
ACCM: 00 F00000F0 0000D000
N6.C2.D1.R0.S01: Offset Found: RdPtrOffsetDqs = 007
ACCM: 0F 000F000F 0F0F0F0F
N2.C0.D0.R0.S05: RdPtrOffsetTxDq: 06
N4.C3.D1.R1: CheckMCTest: result = 0x3FC00
N6.C2.D1.R0.S02: Offset Found: RdPtrOffsetDqs = 007
ACCM: 0F F00F00FF FFFF0F0F
N2.C0.D0.R0.S06: RdPtrOffsetTxDq: 06
N4.C3.D1.R1.S09: Offset Found: RdPtrOffsetDqs = 008
N6.C2.D1.R0.S03: Offset Found: RdPtrOffsetDqs = 007
N0.C2.D1.R0: CheckMCTest: result = 0x139FF
N2.C0.D0.R0.S07: RdPtrOffsetTxDq: 06
N4.C3.D1.R1: CheckMCTest: passed
N6.C2.D1.R0.S04: Offset Found: RdPtrOffsetDqs = 006
ACCM: 00 00000000 00000000
N2.C0.D0.R0.S08: RdPtrOffsetTxDq: 06
N4.C3.D1.R1: CheckMCTest: passed
N6.C2.D1.R0.S05: Offset Found: RdPtrOffsetDqs = 007
ACCM: 00 00000000 00000000
N2.C0.D0.R0.S09: RdPtrOffsetTxDq: 07
N4.C3.D1.R1.S09: Offset Found: RdPtrOffsetDqs = 008
N6.C2.D1.R0.S06: Offset Found: RdPtrOffsetDqs = 007
ACCM: 00 00000000 00000000
N2.C0.D0.R0.S10: RdPtrOffsetTxDq: 07
N4.C3.D1.R1.S10: Offset Found: RdPtrOffsetDqs = 007
N6.C2.D1.R0.S07: Offset Found: RdPtrOffsetDqs = 007
ACCM: 00 F00000F0 F0F00000
N2.C0.D0.R0.S11: RdPtrOffsetTxDq: 06
N4.C3.D1.R1.S11: Offset Found: RdPtrOffsetDqs = 007
N6.C2.D1.R0.S08: Offset Found: RdPtrOffsetDqs = 006
N0.C2.D1.R0: CheckMCTest: result = 0x13800
N2.C0.D0.R0.S12: RdPtrOffsetTxDq: 06
N4.C3.D1.R1.S12: Offset Found: RdPtrOffsetDqs = 007
N6.C2.D1.R0: Write Training Coarse, upper nibbles
ACCM: 00 00000000 00000000
N2.C0.D0.R0.S13: RdPtrOffsetTxDq: 06
N4.C3.D1.R1.S13: Offset Found: RdPtrOffsetDqs = 006
N6.C2.D1.R0.S09: Dq Delay estimate: 469
ACCM: 00 00000000 00000000
N2.C0.D0.R0.S14: RdPtrOffsetTxDq: 06
N4.C3.D1.R1.S14: Offset Found: RdPtrOffsetDqs = 007
N6.C2.D1.R0.S10: Dq Delay estimate: 455
ACCM: 00 00000000 00000000
N2.C0.D0.R0.S15: RdPtrOffsetTxDq: 06
N4.C3.D1.R1.S15: Offset Found: RdPtrOffsetDqs = 007
N6.C2.D1.R0.S11: Dq Delay estimate: 447
ACCM: 00 F00000F0 F0F00000
N2.C0.D0.R0.S16: RdPtrOffsetTxDq: 06
N4.C3.D1.R1.S16: Offset Found: RdPtrOffsetDqs = 007
N6.C2.D1.R0.S12: Dq Delay estimate: 429
N0.C2.D1.R0: CheckMCTest: result = 0x13800
N2.C0.D0.R0.S17: RdPtrOffsetTxDq: 06
N4.C3.D1.R1.S17: Offset Found: RdPtrOffsetDqs = 007
N6.C2.D1.R0.S13: Dq Delay estimate: 388
N0.C2.D1.R0.S00: Offset Found: RdPtrOffsetDqs = 007
N2.C0.D0.R0.S00: RdPtrOffsetTxDq: 08
N4.C3: Calculating Optimimum DQS Values
N6.C2.D1.R0.S14: Dq Delay estimate: 417
N0.C2.D1.R0.S01: Offset Found: RdPtrOffsetDqs = 007
N2.C0.D0.R0.S01: RdPtrOffsetTxDq: 08
N4.C3.D0.R0.S00: Total Delay in PI ticks: TxDQS = 1025, TxDQ = 987
N6.C2.D1.R0.S15: Dq Delay estimate: 414
N0.C2.D1.R0.S02: Offset Found: RdPtrOffsetDqs = 007
N2.C0.D0.R0.S02: RdPtrOffsetTxDq: 07
N4.C3.D0.R0.S01: Total Delay in PI ticks: TxDQS = 1008, TxDQ = 968
N6.C2.D1.R0.S16: Dq Delay estimate: 435
N0.C2.D1.R0.S03: Offset Found: RdPtrOffsetDqs = 007
N2.C0.D0.R0.S03: RdPtrOffsetTxDq: 07
N4.C3.D0.R0.S02: Total Delay in PI ticks: TxDQS = 998, TxDQ = 962
N6.C2.D1.R0.S17: Dq Delay estimate: 406
N0.C2.D1.R0.S04: Offset Found: RdPtrOffsetDqs = 006
N2.C0.D0.R0.S04: RdPtrOffsetTxDq: 06
N4.C3.D0.R0.S03: Total Delay in PI ticks: TxDQS = 982, TxDQ = 945
ACCM: F0 F0F0F0F0 F0F0F0F0
N0.C2.D1.R0.S05: Offset Found: RdPtrOffsetDqs = 007
N2.C0.D0.R0.S05: RdPtrOffsetTxDq: 07
N4.C3.D0.R0.S04: Total Delay in PI ticks: TxDQS = 946, TxDQ = 907
ACCM: F0 F0F0F0F0 F0F0F0F0
N0.C2.D1.R0.S06: Offset Found: RdPtrOffsetDqs = 007
N2.C0.D0.R0.S06: RdPtrOffsetTxDq: 07
N4.C3.D0.R0.S05: Total Delay in PI ticks: TxDQS = 961, TxDQ = 923
ACCM: F0 F0F0F0F0 F0F0F0F0
N0.C2.D1.R0.S07: Offset Found: RdPtrOffsetDqs = 007
N2.C0.D0.R0.S07: RdPtrOffsetTxDq: 07
N4.C3.D0.R0.S06: Total Delay in PI ticks: TxDQS = 976, TxDQ = 937
ACCM: F0 F0F0F0F0 F0F0F0F0
N0.C2.D1.R0.S08: Offset Found: RdPtrOffsetDqs = 006
N2.C0.D0.R0.S08: RdPtrOffsetTxDq: 07
N4.C3.D0.R0.S07: Total Delay in PI ticks: TxDQS = 990, TxDQ = 953
N6.C2.D1.R0: CheckMCTest: result = 0x3FE00
N0.C2.D1.R0: Write Training Coarse, upper nibbles
N2.C0.D0.R0.S09: RdPtrOffsetTxDq: 08
N4.C3.D0.R0.S08: Total Delay in PI ticks: TxDQS = 966, TxDQ = 931
ACCM: F0 F0F0F0F0 F0F0F0F0
N0.C2.D1.R0.S09: Dq Delay estimate: 469
N2.C0.D0.R0.S10: RdPtrOffsetTxDq: 08
N4.C3.D0.R0.S09: Total Delay in PI ticks: TxDQS = 1025, TxDQ = 987
ACCM: F0 F0F0F0F0 F0F0F0F0
N0.C2.D1.R0.S10: Dq Delay estimate: 457
N2.C0.D0.R0.S11: RdPtrOffsetTxDq: 07
N4.C3.D0.R0.S10: Total Delay in PI ticks: TxDQS = 1007, TxDQ = 971
ACCM: F0 F0F0F0F0 F0F0F0F0
N0.C2.D1.R0.S11: Dq Delay estimate: 446
N2.C0.D0.R0.S12: RdPtrOffsetTxDq: 07
N4.C3.D0.R0.S11: Total Delay in PI ticks: TxDQS = 996, TxDQ = 960
ACCM: F0 F0F0F0F0 F0F0F0F0
N0.C2.D1.R0.S12: Dq Delay estimate: 426
N2.C0.D0.R0.S13: RdPtrOffsetTxDq: 07
N4.C3.D0.R0.S12: Total Delay in PI ticks: TxDQS = 984, TxDQ = 947
N6.C2.D1.R0: CheckMCTest: result = 0x3FE00
N0.C2.D1.R0.S13: Dq Delay estimate: 388
N2.C0.D0.R0.S14: RdPtrOffsetTxDq: 07
N4.C3.D0.R0.S13: Total Delay in PI ticks: TxDQS = 947, TxDQ = 911
ACCM: F0 F0F0F0F0 F0F0F0F0
N0.C2.D1.R0.S14: Dq Delay estimate: 413
N2.C0.D0.R0.S15: RdPtrOffsetTxDq: 07
N4.C3.D0.R0.S14: Total Delay in PI ticks: TxDQS = 960, TxDQ = 922
ACCM: F0 F0F0F0F0 F0F0F0F0
N0.C2.D1.R0.S15: Dq Delay estimate: 416
N2.C0.D0.R0.S16: RdPtrOffsetTxDq: 07
N4.C3.D0.R0.S15: Total Delay in PI ticks: TxDQS = 977, TxDQ = 939
ACCM: 00 B0B00000 000000B0
N0.C2.D1.R0.S16: Dq Delay estimate: 435
N2.C0.D0.R0.S17: RdPtrOffsetTxDq: 07
N4.C3.D0.R0.S16: Total Delay in PI ticks: TxDQS = 990, TxDQ = 954
ACCM: 00 B0B00000 000000B0
N0.C2.D1.R0.S17: Dq Delay estimate: 404
N2.C0.D0.R0.S00: Total Delay in PI ticks: TxDQ = 981
N4.C3.D0.R0.S17: Total Delay in PI ticks: TxDQS = 962, TxDQ = 925
N6.C2.D1.R0: CheckMCTest: result = 0x3FE00
ACCM: F0 F0F0F0F0 F0F0F0F0
N2.C0.D0.R0.S01: Total Delay in PI ticks: TxDQ = 960
N4.C3.D0.R1.S00: Total Delay in PI ticks: TxDQS = 1018, TxDQ = 981
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: F0 F0F0F0F0 F0F0F0F0
N2.C0.D0.R0.S02: Total Delay in PI ticks: TxDQ = 948
N4.C3.D0.R1.S01: Total Delay in PI ticks: TxDQS = 1002, TxDQ = 963
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: F0 F0F0F0F0 F0F0F0F0
N2.C0.D0.R0.S03: Total Delay in PI ticks: TxDQ = 930
N4.C3.D0.R1.S02: Total Delay in PI ticks: TxDQS = 988, TxDQ = 952
ACCM: 00 B0F00000 000000F0
ACCM: F0 F0F0F0F0 F0F0F0F0
N2.C0.D0.R0.S04: Total Delay in PI ticks: TxDQ = 898
N4.C3.D0.R1.S03: Total Delay in PI ticks: TxDQS = 977, TxDQ = 941
ACCM: 00 B0F00000 000000F0
N0.C2.D1.R0: CheckMCTest: result = 0x3FE00
N2.C0.D0.R0.S05: Total Delay in PI ticks: TxDQ = 916
N4.C3.D0.R1.S04: Total Delay in PI ticks: TxDQS = 939, TxDQ = 900
N6.C2.D1.R0: CheckMCTest: result = 0x3FE00
ACCM: F0 F0F0F0F0 F0F0F0F0
N2.C0.D0.R0.S06: Total Delay in PI ticks: TxDQ = 921
N4.C3.D0.R1.S05: Total Delay in PI ticks: TxDQS = 952, TxDQ = 915
N6.C2.D1.R0: CheckMCTest: passed
ACCM: F0 F0F0F0F0 F0F0F0F0
N2.C0.D0.R0.S07: Total Delay in PI ticks: TxDQ = 934
N4.C3.D0.R1.S06: Total Delay in PI ticks: TxDQS = 968, TxDQ = 929
N6.C2.D1.R0: CheckMCTest: passed
ACCM: F0 F0F0F0F0 F0F0F0F0
N2.C0.D0.R0.S08: Total Delay in PI ticks: TxDQ = 914
N4.C3.D0.R1.S07: Total Delay in PI ticks: TxDQS = 984, TxDQ = 947
N6.C2.D1.R0.S09: Offset Found: RdPtrOffsetDqs = 007
ACCM: F0 F0F0F0F0 F0F0F0F0
N2.C0.D0.R0.S09: Total Delay in PI ticks: TxDQ = 980
N4.C3.D0.R1.S08: Total Delay in PI ticks: TxDQS = 955, TxDQ = 920
N6.C2.D1.R0.S10: Offset Found: RdPtrOffsetDqs = 007
N0.C2.D1.R0: CheckMCTest: result = 0x3FE00
N2.C0.D0.R0.S10: Total Delay in PI ticks: TxDQ = 961
N4.C3.D0.R1.S09: Total Delay in PI ticks: TxDQS = 1017, TxDQ = 980
N6.C2.D1.R0.S11: Offset Found: RdPtrOffsetDqs = 007
ACCM: F0 F0F0F0F0 F0F0F0F0
N2.C0.D0.R0.S11: Total Delay in PI ticks: TxDQ = 948
N4.C3.D0.R1.S10: Total Delay in PI ticks: TxDQS = 1002, TxDQ = 966
N6.C2.D1.R0.S12: Offset Found: RdPtrOffsetDqs = 007
ACCM: F0 F0F0F0F0 F0F0F0F0
N2.C0.D0.R0.S12: Total Delay in PI ticks: TxDQ = 930
N4.C3.D0.R1.S11: Total Delay in PI ticks: TxDQS = 989, TxDQ = 953
N6.C2.D1.R0.S13: Offset Found: RdPtrOffsetDqs = 006
ACCM: 00 00B000B0 B000B0B0
N2.C0.D0.R0.S13: Total Delay in PI ticks: TxDQ = 901
N4.C3.D0.R1.S12: Total Delay in PI ticks: TxDQS = 979, TxDQ = 942
N6.C2.D1.R0.S14: Offset Found: RdPtrOffsetDqs = 007
ACCM: 00 00B000B0 B000B0B0
N2.C0.D0.R0.S14: Total Delay in PI ticks: TxDQ = 916
N4.C3.D0.R1.S13: Total Delay in PI ticks: TxDQS = 939, TxDQ = 903
N6.C2.D1.R0.S15: Offset Found: RdPtrOffsetDqs = 007
N0.C2.D1.R0: CheckMCTest: result = 0x3FE00
N2.C0.D0.R0.S15: Total Delay in PI ticks: TxDQ = 918
N4.C3.D0.R1.S14: Total Delay in PI ticks: TxDQS = 954, TxDQ = 917
N6.C2.D1.R0.S16: Offset Found: RdPtrOffsetDqs = 007
ACCM: F0 F0F0F0F0 F0F0F0F0
N2.C0.D0.R0.S16: Total Delay in PI ticks: TxDQ = 934
N4.C3.D0.R1.S15: Total Delay in PI ticks: TxDQS = 969, TxDQ = 932
N6.C2.D1.R0.S17: Offset Found: RdPtrOffsetDqs = 006
ACCM: F0 F0F0F0F0 F0F0F0F0
N2.C0.D0.R0.S17: Total Delay in PI ticks: TxDQ = 911
N4.C3.D0.R1.S16: Total Delay in PI ticks: TxDQS = 985, TxDQ = 949
N6.C2.D1.R1: Write Training Coarse, lower nibbles / bytes
ACCM: 00 00F000F0 F000F0F0
N2.C0.D0.R1.S00: wrcmd2dqsstartlatency: 04
N4.C3.D0.R1.S17: Total Delay in PI ticks: TxDQS = 955, TxDQ = 918
N6.C2.D1.R1.S00: Dq Delay estimate: 465
ACCM: 00 00F000F0 F000F0F0
N2.C0.D0.R1.S00: RdPtrOffsetTxDq: 06
N4.C3.D1.R0.S00: Total Delay in PI ticks: TxDQS = 1028, TxDQ = 988
N6.C2.D1.R1.S01: Dq Delay estimate: 448
N0.C2.D1.R0: CheckMCTest: result = 0x3FE00
N2.C0.D0.R1.S00: RdPtrOffsetTxDqs: 07
N4.C3.D1.R0.S01: Total Delay in PI ticks: TxDQS = 1015, TxDQ = 974
N6.C2.D1.R1.S02: Dq Delay estimate: 439
N0.C2.D1.R0: CheckMCTest: passed
N2.C0.D0.R1.S00: PiTxDqs: 46
N4.C3.D1.R0.S02: Total Delay in PI ticks: TxDQS = 1002, TxDQ = 964
N6.C2.D1.R1.S03: Dq Delay estimate: 423
N0.C2.D1.R0: CheckMCTest: passed
N2.C0.D0.R1.S01: wrcmd2dqsstartlatency: 04
N4.C3.D1.R0.S03: Total Delay in PI ticks: TxDQS = 987, TxDQ = 948
N6.C2.D1.R1.S04: Dq Delay estimate: 384
N0.C2.D1.R0.S09: Offset Found: RdPtrOffsetDqs = 007
N2.C0.D0.R1.S01: RdPtrOffsetTxDq: 05
N4.C3.D1.R0.S04: Total Delay in PI ticks: TxDQS = 953, TxDQ = 912
N6.C2.D1.R1.S05: Dq Delay estimate: 412
N0.C2.D1.R0.S10: Offset Found: RdPtrOffsetDqs = 007
N2.C0.D0.R1.S01: RdPtrOffsetTxDqs: 07
N4.C3.D1.R0.S05: Total Delay in PI ticks: TxDQS = 963, TxDQ = 923
N6.C2.D1.R1.S06: Dq Delay estimate: 408
N0.C2.D1.R0.S11: Offset Found: RdPtrOffsetDqs = 007
N2.C0.D0.R1.S01: PiTxDqs: 28
N4.C3.D1.R0.S06: Total Delay in PI ticks: TxDQS = 981, TxDQ = 941
N6.C2.D1.R1.S07: Dq Delay estimate: 431
N0.C2.D1.R0.S12: Offset Found: RdPtrOffsetDqs = 007
N2.C0.D0.R1.S02: wrcmd2dqsstartlatency: 04
N4.C3.D1.R0.S07: Total Delay in PI ticks: TxDQS = 996, TxDQ = 958
N6.C2.D1.R1.S08: Dq Delay estimate: 394
N0.C2.D1.R0.S13: Offset Found: RdPtrOffsetDqs = 006
N2.C0.D0.R1.S02: RdPtrOffsetTxDq: 05
N4.C3.D1.R0.S08: Total Delay in PI ticks: TxDQS = 967, TxDQ = 931
ACCM: 0F 0F0F0F0F 0F0F0F0F
N0.C2.D1.R0.S14: Offset Found: RdPtrOffsetDqs = 007
N2.C0.D0.R1.S02: RdPtrOffsetTxDqs: 07
N4.C3.D1.R0.S09: Total Delay in PI ticks: TxDQS = 1028, TxDQ = 989
ACCM: 0F 0F0F0F0F 0F0F0F0F
N0.C2.D1.R0.S15: Offset Found: RdPtrOffsetDqs = 007
N2.C0.D0.R1.S02: PiTxDqs: 14
N4.C3.D1.R0.S10: Total Delay in PI ticks: TxDQS = 1016, TxDQ = 977
ACCM: 0F 0F0F0F0F 0F0F0F0F
N0.C2.D1.R0.S16: Offset Found: RdPtrOffsetDqs = 007
N2.C0.D0.R1.S03: wrcmd2dqsstartlatency: 04
N4.C3.D1.R0.S11: Total Delay in PI ticks: TxDQS = 1002, TxDQ = 965
ACCM: 0F 0F0F0F0F 0F0F0F0F
N0.C2.D1.R0.S17: Offset Found: RdPtrOffsetDqs = 006
N2.C0.D0.R1.S03: RdPtrOffsetTxDq: 05
N4.C3.D1.R0.S12: Total Delay in PI ticks: TxDQS = 991, TxDQ = 952
N6.C2.D1.R1: CheckMCTest: result = 0x1FF
N0.C2.D1.R1: Write Training Coarse, lower nibbles / bytes
N2.C0.D0.R1.S03: RdPtrOffsetTxDqs: 06
N4.C3.D1.R0.S13: Total Delay in PI ticks: TxDQS = 951, TxDQ = 914
ACCM: 0F 0F0F0F0F 0F0F0F0F
N0.C2.D1.R1.S00: Dq Delay estimate: 465
N2.C0.D0.R1.S03: PiTxDqs: 60
N4.C3.D1.R0.S14: Total Delay in PI ticks: TxDQS = 967, TxDQ = 928
ACCM: 0F 0F0F0F0F 0F0F0F0F
N0.C2.D1.R1.S01: Dq Delay estimate: 451
N2.C0.D0.R1.S04: wrcmd2dqsstartlatency: 04
N4.C3.D1.R0.S15: Total Delay in PI ticks: TxDQS = 980, TxDQ = 940
ACCM: 0F 0F0F0F0F 0F0F0F0F
N0.C2.D1.R1.S02: Dq Delay estimate: 441
N2.C0.D0.R1.S04: RdPtrOffsetTxDq: 04
N4.C3.D1.R0.S16: Total Delay in PI ticks: TxDQS = 996, TxDQ = 959
ACCM: 0F 0F0F0F0F 0F0F0F0F
N0.C2.D1.R1.S03: Dq Delay estimate: 424
N2.C0.D0.R1.S04: RdPtrOffsetTxDqs: 06
N4.C3.D1.R0.S17: Total Delay in PI ticks: TxDQS = 968, TxDQ = 929
N6.C2.D1.R1: CheckMCTest: result = 0x1FF
N0.C2.D1.R1.S04: Dq Delay estimate: 386
N2.C0.D0.R1.S04: PiTxDqs: 27
N4.C3.D1.R1.S00: Total Delay in PI ticks: TxDQS = 1027, TxDQ = 987
ACCM: 0F 0F0F0F0F 0F0F0F0F
N0.C2.D1.R1.S05: Dq Delay estimate: 414
N2.C0.D0.R1.S05: wrcmd2dqsstartlatency: 04
N4.C3.D1.R1.S01: Total Delay in PI ticks: TxDQS = 1011, TxDQ = 970
ACCM: 0F 0F0F0F0F 0F0F0F0F
N0.C2.D1.R1.S06: Dq Delay estimate: 408
N2.C0.D0.R1.S05: RdPtrOffsetTxDq: 05
N4.C3.D1.R1.S02: Total Delay in PI ticks: TxDQS = 998, TxDQ = 960
ACCM: 00 0B000B0B 0B0B000B
N0.C2.D1.R1.S07: Dq Delay estimate: 430
N2.C0.D0.R1.S05: RdPtrOffsetTxDqs: 06
N4.C3.D1.R1.S03: Total Delay in PI ticks: TxDQS = 987, TxDQ = 948
ACCM: 00 0B000B0B 0B0B000B
N0.C2.D1.R1.S08: Dq Delay estimate: 397
N2.C0.D0.R1.S05: PiTxDqs: 45
N4.C3.D1.R1.S04: Total Delay in PI ticks: TxDQS = 949, TxDQ = 908
N6.C2.D1.R1: CheckMCTest: result = 0x1FF
ACCM: 0F 0F0F0F0F 0F0F0F0F
N2.C0.D0.R1.S06: wrcmd2dqsstartlatency: 04
N4.C3.D1.R1.S05: Total Delay in PI ticks: TxDQS = 962, TxDQ = 922
ACCM: 0F 0F0F0F0F 0F0F0F0F
ACCM: 0F 0F0F0F0F 0F0F0F0F
N2.C0.D0.R1.S06: RdPtrOffsetTxDq: 05
N4.C3.D1.R1.S06: Total Delay in PI ticks: TxDQS = 976, TxDQ = 935
ACCM: 0F 0F0F0F0F 0F0F0F0F
ACCM: 0F 0F0F0F0F 0F0F0F0F
N2.C0.D0.R1.S06: RdPtrOffsetTxDqs: 06
N4.C3.D1.R1.S07: Total Delay in PI ticks: TxDQS = 993, TxDQ = 954
ACCM: 00 0F000F0F 0F0F000B
ACCM: 0F 0F0F0F0F 0F0F0F0F
N2.C0.D0.R1.S06: PiTxDqs: 50
N4.C3.D1.R1.S08: Total Delay in PI ticks: TxDQS = 963, TxDQ = 926
ACCM: 00 0F000F0F 0F0F000B
N0.C2.D1.R1: CheckMCTest: result = 0x1FF
N2.C0.D0.R1.S07: wrcmd2dqsstartlatency: 04
N4.C3.D1.R1.S09: Total Delay in PI ticks: TxDQS = 1025, TxDQ = 986
N6.C2.D1.R1: CheckMCTest: result = 0x1FF
ACCM: 0F 0F0F0F0F 0F0F0F0F
N2.C0.D0.R1.S07: RdPtrOffsetTxDq: 05
N4.C3.D1.R1.S10: Total Delay in PI ticks: TxDQS = 1011, TxDQ = 973
N6.C2.D1.R1: CheckMCTest: passed
ACCM: 0F 0F0F0F0F 0F0F0F0F
N2.C0.D0.R1.S07: RdPtrOffsetTxDqs: 07
N4.C3.D1.R1.S11: Total Delay in PI ticks: TxDQS = 1000, TxDQ = 963
N6.C2.D1.R1: CheckMCTest: passed
ACCM: 0F 0F0F0F0F 0F0F0F0F
N2.C0.D0.R1.S07: PiTxDqs: 00
N4.C3.D1.R1.S12: Total Delay in PI ticks: TxDQS = 988, TxDQ = 949
N6.C2.D1.R1.S00: Offset Found: RdPtrOffsetDqs = 007
ACCM: 0F 0F0F0F0F 0F0F0F0F
N2.C0.D0.R1.S08: wrcmd2dqsstartlatency: 04
N4.C3.D1.R1.S13: Total Delay in PI ticks: TxDQS = 950, TxDQ = 913
N6.C2.D1.R1.S01: Offset Found: RdPtrOffsetDqs = 007
N0.C2.D1.R1: CheckMCTest: result = 0x1FF
N2.C0.D0.R1.S08: RdPtrOffsetTxDq: 05
N4.C3.D1.R1.S14: Total Delay in PI ticks: TxDQS = 963, TxDQ = 924
N6.C2.D1.R1.S02: Offset Found: RdPtrOffsetDqs = 007
ACCM: 0F 0F0F0F0F 0F0F0F0F
N2.C0.D0.R1.S08: RdPtrOffsetTxDqs: 06
N4.C3.D1.R1.S15: Total Delay in PI ticks: TxDQS = 977, TxDQ = 937
N6.C2.D1.R1.S03: Offset Found: RdPtrOffsetDqs = 007
ACCM: 0F 0F0F0F0F 0F0F0F0F
N2.C0.D0.R1.S08: PiTxDqs: 40
N4.C3.D1.R1.S16: Total Delay in PI ticks: TxDQS = 995, TxDQ = 958
N6.C2.D1.R1.S04: Offset Found: RdPtrOffsetDqs = 006
ACCM: 00 0B0B0B00 00000000
N2.C0.D0.R1.S09: wrcmd2dqsstartlatency: 04
N4.C3.D1.R1.S17: Total Delay in PI ticks: TxDQS = 963, TxDQ = 924
N6.C2.D1.R1.S05: Offset Found: RdPtrOffsetDqs = 007
ACCM: 00 0B0B0B00 00000000
N2.C0.D0.R1.S09: RdPtrOffsetTxDq: 06
N4: END WRITE LEVEL COARSE:
N6.C2.D1.R1.S06: Offset Found: RdPtrOffsetDqs = 006
N0.C2.D1.R1: CheckMCTest: result = 0x1FF
N2.C0.D0.R1.S09: RdPtrOffsetTxDqs: 07
N4: RunTrainStep: Final status = 0
N6.C2.D1.R1.S07: Offset Found: RdPtrOffsetDqs = 007
ACCM: 0F 0F0F0F0F 0F0F0F0F
N2.C0.D0.R1.S09: PiTxDqs: 42

END - Basic Write Level Training       Time         37901 ms
N6.C2.D1.R1.S08: Offset Found: RdPtrOffsetDqs = 006
ACCM: 0F 0F0F0F0F 0F0F0F0F
N2.C0.D0.R1.S10: wrcmd2dqsstartlatency: 04

START - Basic Write DQ/DQS Training
N6.C2.D1.R1: Write Training Coarse, upper nibbles
ACCM: 00 0F0F0F00 00000000
N2.C0.D0.R1.S10: RdPtrOffsetTxDq: 05
N4.C0.D0.R0.S00: wrcmd2dqsstartlatency: 04
N6.C2.D1.R1.S09: Dq Delay estimate: 461
ACCM: 00 0F0F0F00 00000000
N2.C0.D0.R1.S10: RdPtrOffsetTxDqs: 07
N4.C0.D0.R0.S00: RdPtrOffsetTxDq: 06
N6.C2.D1.R1.S10: Dq Delay estimate: 450
N0.C2.D1.R1: CheckMCTest: result = 0x1FF
N2.C0.D0.R1.S10: PiTxDqs: 26
N4.C0.D0.R0.S00: RdPtrOffsetTxDqs: 07
N6.C2.D1.R1.S11: Dq Delay estimate: 442
N0.C2.D1.R1: CheckMCTest: passed
N2.C0.D0.R1.S11: wrcmd2dqsstartlatency: 04
N4.C0.D0.R0.S00: PiTxDqs: 59
N6.C2.D1.R1.S12: Dq Delay estimate: 428
N0.C2.D1.R1: CheckMCTest: passed
N2.C0.D0.R1.S11: RdPtrOffsetTxDq: 05
N4.C0.D0.R0.S01: wrcmd2dqsstartlatency: 04
N6.C2.D1.R1.S13: Dq Delay estimate: 384
N0.C2.D1.R1.S00: Offset Found: RdPtrOffsetDqs = 007
N2.C0.D0.R1.S11: RdPtrOffsetTxDqs: 07
N4.C0.D0.R0.S01: RdPtrOffsetTxDq: 06
N6.C2.D1.R1.S14: Dq Delay estimate: 411
N0.C2.D1.R1.S01: Offset Found: RdPtrOffsetDqs = 007
N2.C0.D0.R1.S11: PiTxDqs: 16
N4.C0.D0.R0.S01: RdPtrOffsetTxDqs: 07
N6.C2.D1.R1.S15: Dq Delay estimate: 412
N0.C2.D1.R1.S02: Offset Found: RdPtrOffsetDqs = 007
N2.C0.D0.R1.S12: wrcmd2dqsstartlatency: 04
N4.C0.D0.R0.S01: PiTxDqs: 38
N6.C2.D1.R1.S16: Dq Delay estimate: 432
N0.C2.D1.R1.S03: Offset Found: RdPtrOffsetDqs = 007
N2.C0.D0.R1.S12: RdPtrOffsetTxDq: 05
N4.C0.D0.R0.S02: wrcmd2dqsstartlatency: 04
N6.C2.D1.R1.S17: Dq Delay estimate: 399
N0.C2.D1.R1.S04: Offset Found: RdPtrOffsetDqs = 006
N2.C0.D0.R1.S12: RdPtrOffsetTxDqs: 07
N4.C0.D0.R0.S02: RdPtrOffsetTxDq: 05
ACCM: F0 F0F0F0F0 F0F0F0F0
N0.C2.D1.R1.S05: Offset Found: RdPtrOffsetDqs = 007
N2.C0.D0.R1.S12: PiTxDqs: 00
N4.C0.D0.R0.S02: RdPtrOffsetTxDqs: 07
ACCM: F0 F0F0F0F0 F0F0F0F0
N0.C2.D1.R1.S06: Offset Found: RdPtrOffsetDqs = 006
N2.C0.D0.R1.S13: wrcmd2dqsstartlatency: 04
N4.C0.D0.R0.S02: PiTxDqs: 31
ACCM: F0 F0F0F0F0 F0F0F0F0
N0.C2.D1.R1.S07: Offset Found: RdPtrOffsetDqs = 007
N2.C0.D0.R1.S13: RdPtrOffsetTxDq: 04
N4.C0.D0.R0.S03: wrcmd2dqsstartlatency: 04
ACCM: F0 F0F0F0F0 F0F0F0F0
N0.C2.D1.R1.S08: Offset Found: RdPtrOffsetDqs = 006
N2.C0.D0.R1.S13: RdPtrOffsetTxDqs: 06
N4.C0.D0.R0.S03: RdPtrOffsetTxDq: 05
N6.C2.D1.R1: CheckMCTest: result = 0x3FE00
N0.C2.D1.R1: Write Training Coarse, upper nibbles
N2.C0.D0.R1.S13: PiTxDqs: 28
N4.C0.D0.R0.S03: RdPtrOffsetTxDqs: 07
ACCM: F0 F0F0F0F0 F0F0F0F0
N0.C2.D1.R1.S09: Dq Delay estimate: 468
N2.C0.D0.R1.S14: wrcmd2dqsstartlatency: 04
N4.C0.D0.R0.S03: PiTxDqs: 10
ACCM: F0 F0F0F0F0 F0F0F0F0
N0.C2.D1.R1.S10: Dq Delay estimate: 453
N2.C0.D0.R1.S14: RdPtrOffsetTxDq: 05
N4.C0.D0.R0.S04: wrcmd2dqsstartlatency: 04
ACCM: F0 F0F0F0F0 F0F0F0F0
N0.C2.D1.R1.S11: Dq Delay estimate: 445
N2.C0.D0.R1.S14: RdPtrOffsetTxDqs: 06
N4.C0.D0.R0.S04: RdPtrOffsetTxDq: 05
ACCM: F0 F0F0F0F0 F0F0F0F0
N0.C2.D1.R1.S12: Dq Delay estimate: 425
N2.C0.D0.R1.S14: PiTxDqs: 46
N4.C0.D0.R0.S04: RdPtrOffsetTxDqs: 06
N6.C2.D1.R1: CheckMCTest: result = 0x3FE00
N0.C2.D1.R1.S13: Dq Delay estimate: 388
N2.C0.D0.R1.S15: wrcmd2dqsstartlatency: 04
N4.C0.D0.R0.S04: PiTxDqs: 44
ACCM: F0 F0F0F0F0 F0F0F0F0
N0.C2.D1.R1.S14: Dq Delay estimate: 413
N2.C0.D0.R1.S15: RdPtrOffsetTxDq: 05
N4.C0.D0.R0.S05: wrcmd2dqsstartlatency: 04
ACCM: F0 F0F0F0F0 F0F0F0F0
N0.C2.D1.R1.S15: Dq Delay estimate: 411
N2.C0.D0.R1.S15: RdPtrOffsetTxDqs: 06
N4.C0.D0.R0.S05: RdPtrOffsetTxDq: 05
ACCM: 00 B0000000 B0B000B0
N0.C2.D1.R1.S16: Dq Delay estimate: 435
N2.C0.D0.R1.S15: PiTxDqs: 51
N4.C0.D0.R0.S05: RdPtrOffsetTxDqs: 06
ACCM: 00 B0000000 B0B000B0
N0.C2.D1.R1.S17: Dq Delay estimate: 398
N2.C0.D0.R1.S16: wrcmd2dqsstartlatency: 04
N4.C0.D0.R0.S05: PiTxDqs: 62
N6.C2.D1.R1: CheckMCTest: result = 0x3FE00
ACCM: F0 F0F0F0F0 F0F0F0F0
N2.C0.D0.R1.S16: RdPtrOffsetTxDq: 05
N4.C0.D0.R0.S06: wrcmd2dqsstartlatency: 04
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: F0 F0F0F0F0 F0F0F0F0
N2.C0.D0.R1.S16: RdPtrOffsetTxDqs: 07
N4.C0.D0.R0.S06: RdPtrOffsetTxDq: 05
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: F0 F0F0F0F0 F0F0F0F0
N2.C0.D0.R1.S16: PiTxDqs: 01
N4.C0.D0.R0.S06: RdPtrOffsetTxDqs: 07
ACCM: 00 B0000000 F0F000F0
ACCM: F0 F0F0F0F0 F0F0F0F0
N2.C0.D0.R1.S17: wrcmd2dqsstartlatency: 04
N4.C0.D0.R0.S06: PiTxDqs: 00
ACCM: 00 B0000000 F0F000F0
N0.C2.D1.R1: CheckMCTest: result = 0x3FE00
N2.C0.D0.R1.S17: RdPtrOffsetTxDq: 05
N4.C0.D0.R0.S07: wrcmd2dqsstartlatency: 04
N6.C2.D1.R1: CheckMCTest: result = 0x3FE00
ACCM: F0 F0F0F0F0 F0F0F0F0
N2.C0.D0.R1.S17: RdPtrOffsetTxDqs: 06
N4.C0.D0.R0.S07: RdPtrOffsetTxDq: 05
N6.C2.D1.R1: CheckMCTest: passed
ACCM: F0 F0F0F0F0 F0F0F0F0
N2.C0.D0.R1.S17: PiTxDqs: 40
N4.C0.D0.R0.S07: RdPtrOffsetTxDqs: 07
N6.C2.D1.R1: CheckMCTest: passed
ACCM: F0 F0F0F0F0 F0F0F0F0
N2.C0.D0.R1.S00: RdPtrOffsetTxDq: 07
N4.C0.D0.R0.S07: PiTxDqs: 14
N6.C2.D1.R1.S09: Offset Found: RdPtrOffsetDqs = 007
ACCM: F0 F0F0F0F0 F0F0F0F0
N2.C0.D0.R1.S01: RdPtrOffsetTxDq: 06
N4.C0.D0.R0.S08: wrcmd2dqsstartlatency: 04
N6.C2.D1.R1.S10: Offset Found: RdPtrOffsetDqs = 007
N0.C2.D1.R1: CheckMCTest: result = 0x3FE00
N2.C0.D0.R1.S02: RdPtrOffsetTxDq: 06
N4.C0.D0.R0.S08: RdPtrOffsetTxDq: 05
N6.C2.D1.R1.S11: Offset Found: RdPtrOffsetDqs = 007
ACCM: F0 F0F0F0F0 F0F0F0F0
N2.C0.D0.R1.S03: RdPtrOffsetTxDq: 06
N4.C0.D0.R0.S08: RdPtrOffsetTxDqs: 06
N6.C2.D1.R1.S12: Offset Found: RdPtrOffsetDqs = 007
ACCM: F0 F0F0F0F0 F0F0F0F0
N2.C0.D0.R1.S04: RdPtrOffsetTxDq: 05
N4.C0.D0.R0.S08: PiTxDqs: 56
N6.C2.D1.R1.S13: Offset Found: RdPtrOffsetDqs = 006
ACCM: 00 B0B0B0B0 B0B000B0
N2.C0.D0.R1.S05: RdPtrOffsetTxDq: 06
N4.C0.D0.R0.S09: wrcmd2dqsstartlatency: 04
N6.C2.D1.R1.S14: Offset Found: RdPtrOffsetDqs = 006
ACCM: 00 B0B0B0B0 B0B000B0
N2.C0.D0.R1.S06: RdPtrOffsetTxDq: 06
N4.C0.D0.R0.S09: RdPtrOffsetTxDq: 06
N6.C2.D1.R1.S15: Offset Found: RdPtrOffsetDqs = 006
N0.C2.D1.R1: CheckMCTest: result = 0x3FE00
N2.C0.D0.R1.S07: RdPtrOffsetTxDq: 06
N4.C0.D0.R0.S09: RdPtrOffsetTxDqs: 07
N6.C2.D1.R1.S16: Offset Found: RdPtrOffsetDqs = 007
ACCM: F0 F0F0F0F0 F0F0F0F0
N2.C0.D0.R1.S08: RdPtrOffsetTxDq: 06
N4.C0.D0.R0.S09: PiTxDqs: 57
N6.C2.D1.R1.S17: Offset Found: RdPtrOffsetDqs = 006
ACCM: F0 F0F0F0F0 F0F0F0F0
N2.C0.D0.R1.S09: RdPtrOffsetTxDq: 07
N4.C0.D0.R0.S10: wrcmd2dqsstartlatency: 04
N6.C2: Calculating Optimimum DQS Values
ACCM: 00 F0F0F0F0 F0F000F0
N2.C0.D0.R1.S10: RdPtrOffsetTxDq: 06
N4.C0.D0.R0.S10: RdPtrOffsetTxDq: 06
N6.C2.D0.R0.S00: Total Delay in PI ticks: TxDQS = 1008, TxDQ = 976
ACCM: 00 F0F0F0F0 F0F000F0
N2.C0.D0.R1.S11: RdPtrOffsetTxDq: 06
N4.C0.D0.R0.S10: RdPtrOffsetTxDqs: 07
N6.C2.D0.R0.S01: Total Delay in PI ticks: TxDQS = 995, TxDQ = 961
N0.C2.D1.R1: CheckMCTest: result = 0x3FE00
N2.C0.D0.R1.S12: RdPtrOffsetTxDq: 06
N4.C0.D0.R0.S10: PiTxDqs: 38
N6.C2.D0.R0.S02: Total Delay in PI ticks: TxDQS = 984, TxDQ = 951
N0.C2.D1.R1: CheckMCTest: passed
N2.C0.D0.R1.S13: RdPtrOffsetTxDq: 05
N4.C0.D0.R0.S11: wrcmd2dqsstartlatency: 04
N6.C2.D0.R0.S03: Total Delay in PI ticks: TxDQS = 964, TxDQ = 931
N0.C2.D1.R1: CheckMCTest: passed
N2.C0.D0.R1.S14: RdPtrOffsetTxDq: 06
N4.C0.D0.R0.S11: RdPtrOffsetTxDq: 05
N6.C2.D0.R0.S04: Total Delay in PI ticks: TxDQS = 926, TxDQ = 896
N0.C2.D1.R1.S09: Offset Found: RdPtrOffsetDqs = 007
N2.C0.D0.R1.S15: RdPtrOffsetTxDq: 06
N4.C0.D0.R0.S11: RdPtrOffsetTxDqs: 07
N6.C2.D0.R0.S05: Total Delay in PI ticks: TxDQS = 955, TxDQ = 920
N0.C2.D1.R1.S10: Offset Found: RdPtrOffsetDqs = 007
N2.C0.D0.R1.S16: RdPtrOffsetTxDq: 06
N4.C0.D0.R0.S11: PiTxDqs: 26
N6.C2.D0.R0.S06: Total Delay in PI ticks: TxDQS = 957, TxDQ = 923
N0.C2.D1.R1.S11: Offset Found: RdPtrOffsetDqs = 007
N2.C0.D0.R1.S17: RdPtrOffsetTxDq: 06
N4.C0.D0.R0.S12: wrcmd2dqsstartlatency: 04
N6.C2.D0.R0.S07: Total Delay in PI ticks: TxDQS = 975, TxDQ = 939
N0.C2.D1.R1.S12: Offset Found: RdPtrOffsetDqs = 007
N2.C0.D0.R1.S00: RdPtrOffsetTxDq: 08
N4.C0.D0.R0.S12: RdPtrOffsetTxDq: 05
N6.C2.D0.R0.S08: Total Delay in PI ticks: TxDQS = 945, TxDQ = 909
N0.C2.D1.R1.S13: Offset Found: RdPtrOffsetDqs = 006
N2.C0.D0.R1.S01: RdPtrOffsetTxDq: 07
N4.C0.D0.R0.S12: RdPtrOffsetTxDqs: 07
N6.C2.D0.R0.S09: Total Delay in PI ticks: TxDQS = 1009, TxDQ = 976
N0.C2.D1.R1.S14: Offset Found: RdPtrOffsetDqs = 007
N2.C0.D0.R1.S02: RdPtrOffsetTxDq: 07
N4.C0.D0.R0.S12: PiTxDqs: 10
N6.C2.D0.R0.S10: Total Delay in PI ticks: TxDQS = 996, TxDQ = 965
N0.C2.D1.R1.S15: Offset Found: RdPtrOffsetDqs = 006
N2.C0.D0.R1.S03: RdPtrOffsetTxDq: 07
N4.C0.D0.R0.S13: wrcmd2dqsstartlatency: 04
N6.C2.D0.R0.S11: Total Delay in PI ticks: TxDQS = 985, TxDQ = 953
N0.C2.D1.R1.S16: Offset Found: RdPtrOffsetDqs = 007
N2.C0.D0.R1.S04: RdPtrOffsetTxDq: 06
N4.C0.D0.R0.S13: RdPtrOffsetTxDq: 05
N6.C2.D0.R0.S12: Total Delay in PI ticks: TxDQS = 965, TxDQ = 932
N0.C2.D1.R1.S17: Offset Found: RdPtrOffsetDqs = 006
N2.C0.D0.R1.S05: RdPtrOffsetTxDq: 07
N4.C0.D0.R0.S13: RdPtrOffsetTxDqs: 06
N6.C2.D0.R0.S13: Total Delay in PI ticks: TxDQS = 926, TxDQ = 893
N0.C2: Calculating Optimimum DQS Values
N2.C0.D0.R1.S06: RdPtrOffsetTxDq: 07
N4.C0.D0.R0.S13: PiTxDqs: 44
N6.C2.D0.R0.S14: Total Delay in PI ticks: TxDQS = 953, TxDQ = 919
N0.C2.D0.R0.S00: Total Delay in PI ticks: TxDQS = 1015, TxDQ = 982
N2.C0.D0.R1.S07: RdPtrOffsetTxDq: 07
N4.C0.D0.R0.S14: wrcmd2dqsstartlatency: 04
N6.C2.D0.R0.S15: Total Delay in PI ticks: TxDQS = 955, TxDQ = 922
N0.C2.D0.R0.S01: Total Delay in PI ticks: TxDQS = 999, TxDQ = 964
N2.C0.D0.R1.S08: RdPtrOffsetTxDq: 07
N4.C0.D0.R0.S14: RdPtrOffsetTxDq: 05
N6.C2.D0.R0.S16: Total Delay in PI ticks: TxDQS = 975, TxDQ = 941
N0.C2.D0.R0.S02: Total Delay in PI ticks: TxDQS = 989, TxDQ = 955
N2.C0.D0.R1.S09: RdPtrOffsetTxDq: 08
N4.C0.D0.R0.S14: RdPtrOffsetTxDqs: 06
N6.C2.D0.R0.S17: Total Delay in PI ticks: TxDQS = 945, TxDQ = 914
N0.C2.D0.R0.S03: Total Delay in PI ticks: TxDQS = 970, TxDQ = 936
N2.C0.D0.R1.S10: RdPtrOffsetTxDq: 07
N4.C0.D0.R0.S14: PiTxDqs: 56
N6.C2.D0.R1.S00: Total Delay in PI ticks: TxDQS = 1002, TxDQ = 972
N0.C2.D0.R0.S04: Total Delay in PI ticks: TxDQS = 933, TxDQ = 900
N2.C0.D0.R1.S11: RdPtrOffsetTxDq: 07
N4.C0.D0.R0.S15: wrcmd2dqsstartlatency: 04
N6.C2.D0.R1.S01: Total Delay in PI ticks: TxDQS = 987, TxDQ = 953
N0.C2.D0.R0.S05: Total Delay in PI ticks: TxDQS = 959, TxDQ = 924
N2.C0.D0.R1.S12: RdPtrOffsetTxDq: 07
N4.C0.D0.R0.S15: RdPtrOffsetTxDq: 05
N6.C2.D0.R1.S02: Total Delay in PI ticks: TxDQS = 976, TxDQ = 943
N0.C2.D0.R0.S06: Total Delay in PI ticks: TxDQS = 959, TxDQ = 925
N2.C0.D0.R1.S13: RdPtrOffsetTxDq: 06
N4.C0.D0.R0.S15: RdPtrOffsetTxDqs: 06
N6.C2.D0.R1.S03: Total Delay in PI ticks: TxDQS = 959, TxDQ = 925
N0.C2.D0.R0.S07: Total Delay in PI ticks: TxDQS = 978, TxDQ = 944
N2.C0.D0.R1.S14: RdPtrOffsetTxDq: 07
N4.C0.D0.R0.S15: PiTxDqs: 62
N6.C2.D0.R1.S04: Total Delay in PI ticks: TxDQS = 919, TxDQ = 886
N0.C2.D0.R0.S08: Total Delay in PI ticks: TxDQS = 953, TxDQ = 919
N2.C0.D0.R1.S15: RdPtrOffsetTxDq: 07
N4.C0.D0.R0.S16: wrcmd2dqsstartlatency: 04
N6.C2.D0.R1.S05: Total Delay in PI ticks: TxDQS = 949, TxDQ = 914
N0.C2.D0.R0.S09: Total Delay in PI ticks: TxDQS = 1016, TxDQ = 984
N2.C0.D0.R1.S16: RdPtrOffsetTxDq: 07
N4.C0.D0.R0.S16: RdPtrOffsetTxDq: 05
N6.C2.D0.R1.S06: Total Delay in PI ticks: TxDQS = 947, TxDQ = 913
N0.C2.D0.R0.S10: Total Delay in PI ticks: TxDQS = 1002, TxDQ = 969
N2.C0.D0.R1.S17: RdPtrOffsetTxDq: 07
N4.C0.D0.R0.S16: RdPtrOffsetTxDqs: 07
N6.C2.D0.R1.S07: Total Delay in PI ticks: TxDQS = 969, TxDQ = 934
N0.C2.D0.R0.S11: Total Delay in PI ticks: TxDQS = 990, TxDQ = 957
N2.C0.D0.R1.S00: Total Delay in PI ticks: TxDQ = 975
N4.C0.D0.R0.S16: PiTxDqs: 14
N6.C2.D0.R1.S08: Total Delay in PI ticks: TxDQS = 937, TxDQ = 901
N0.C2.D0.R0.S12: Total Delay in PI ticks: TxDQS = 969, TxDQ = 936
N2.C0.D0.R1.S01: Total Delay in PI ticks: TxDQ = 955
N4.C0.D0.R0.S17: wrcmd2dqsstartlatency: 04
N6.C2.D0.R1.S09: Total Delay in PI ticks: TxDQS = 999, TxDQ = 965
N0.C2.D0.R0.S13: Total Delay in PI ticks: TxDQS = 930, TxDQ = 897
N2.C0.D0.R1.S02: Total Delay in PI ticks: TxDQ = 941
N4.C0.D0.R0.S17: RdPtrOffsetTxDq: 05
N6.C2.D0.R1.S10: Total Delay in PI ticks: TxDQS = 987, TxDQ = 956
N0.C2.D0.R0.S14: Total Delay in PI ticks: TxDQS = 958, TxDQ = 924
N2.C0.D0.R1.S03: Total Delay in PI ticks: TxDQ = 924
N4.C0.D0.R0.S17: RdPtrOffsetTxDqs: 06
N6.C2.D0.R1.S11: Total Delay in PI ticks: TxDQS = 977, TxDQ = 945
N0.C2.D0.R0.S15: Total Delay in PI ticks: TxDQS = 960, TxDQ = 926
N2.C0.D0.R1.S04: Total Delay in PI ticks: TxDQ = 891
N4.C0.D0.R0.S17: PiTxDqs: 55
N6.C2.D0.R1.S12: Total Delay in PI ticks: TxDQS = 962, TxDQ = 929
N0.C2.D0.R0.S16: Total Delay in PI ticks: TxDQS = 978, TxDQ = 945
N2.C0.D0.R1.S05: Total Delay in PI ticks: TxDQ = 909
N4.C0.D0.R0.S00: RdPtrOffsetTxDq: 07
N6.C2.D0.R1.S13: Total Delay in PI ticks: TxDQS = 919, TxDQ = 887
N0.C2.D0.R0.S17: Total Delay in PI ticks: TxDQS = 952, TxDQ = 917
N2.C0.D0.R1.S06: Total Delay in PI ticks: TxDQ = 915
N4.C0.D0.R0.S01: RdPtrOffsetTxDq: 07
N6.C2.D0.R1.S14: Total Delay in PI ticks: TxDQS = 949, TxDQ = 916
N0.C2.D0.R1.S00: Total Delay in PI ticks: TxDQS = 1007, TxDQ = 974
N2.C0.D0.R1.S07: Total Delay in PI ticks: TxDQ = 928
N4.C0.D0.R0.S02: RdPtrOffsetTxDq: 06
N6.C2.D0.R1.S15: Total Delay in PI ticks: TxDQS = 949, TxDQ = 916
N0.C2.D0.R1.S01: Total Delay in PI ticks: TxDQS = 994, TxDQ = 959
N2.C0.D0.R1.S08: Total Delay in PI ticks: TxDQ = 907
N4.C0.D0.R0.S03: RdPtrOffsetTxDq: 06
N6.C2.D0.R1.S16: Total Delay in PI ticks: TxDQS = 969, TxDQ = 935
N0.C2.D0.R1.S02: Total Delay in PI ticks: TxDQS = 984, TxDQ = 951
N2.C0.D0.R1.S09: Total Delay in PI ticks: TxDQ = 970
N4.C0.D0.R0.S04: RdPtrOffsetTxDq: 06
N6.C2.D0.R1.S17: Total Delay in PI ticks: TxDQS = 937, TxDQ = 907
N0.C2.D0.R1.S03: Total Delay in PI ticks: TxDQS = 966, TxDQ = 932
N2.C0.D0.R1.S10: Total Delay in PI ticks: TxDQ = 954
N4.C0.D0.R0.S05: RdPtrOffsetTxDq: 06
N6.C2.D1.R0.S00: Total Delay in PI ticks: TxDQS = 1015, TxDQ = 982
N0.C2.D0.R1.S04: Total Delay in PI ticks: TxDQS = 927, TxDQ = 894
N2.C0.D0.R1.S11: Total Delay in PI ticks: TxDQ = 944
N4.C0.D0.R0.S06: RdPtrOffsetTxDq: 06
N6.C2.D1.R0.S01: Total Delay in PI ticks: TxDQS = 1001, TxDQ = 965
N0.C2.D0.R1.S05: Total Delay in PI ticks: TxDQS = 956, TxDQ = 921
N2.C0.D0.R1.S12: Total Delay in PI ticks: TxDQ = 928
N4.C0.D0.R0.S07: RdPtrOffsetTxDq: 06
N6.C2.D1.R0.S02: Total Delay in PI ticks: TxDQS = 992, TxDQ = 957
N0.C2.D0.R1.S06: Total Delay in PI ticks: TxDQS = 951, TxDQ = 916
N2.C0.D0.R1.S13: Total Delay in PI ticks: TxDQ = 894
N4.C0.D0.R0.S08: RdPtrOffsetTxDq: 06
N6.C2.D1.R0.S03: Total Delay in PI ticks: TxDQS = 976, TxDQ = 941
N0.C2.D0.R1.S07: Total Delay in PI ticks: TxDQS = 974, TxDQ = 940
N2.C0.D0.R1.S14: Total Delay in PI ticks: TxDQ = 911
N4.C0.D0.R0.S09: RdPtrOffsetTxDq: 07
N6.C2.D1.R0.S04: Total Delay in PI ticks: TxDQS = 934, TxDQ = 900
N0.C2.D0.R1.S08: Total Delay in PI ticks: TxDQS = 944, TxDQ = 910
N2.C0.D0.R1.S15: Total Delay in PI ticks: TxDQ = 915
N4.C0.D0.R0.S10: RdPtrOffsetTxDq: 07
N6.C2.D1.R0.S05: Total Delay in PI ticks: TxDQS = 964, TxDQ = 928
N0.C2.D0.R1.S09: Total Delay in PI ticks: TxDQS = 1009, TxDQ = 976
N2.C0.D0.R1.S16: Total Delay in PI ticks: TxDQ = 928
N4.C0.D0.R0.S11: RdPtrOffsetTxDq: 06
N6.C2.D1.R0.S06: Total Delay in PI ticks: TxDQS = 961, TxDQ = 925
N0.C2.D0.R1.S10: Total Delay in PI ticks: TxDQS = 995, TxDQ = 962
N2.C0.D0.R1.S17: Total Delay in PI ticks: TxDQ = 904
N4.C0.D0.R0.S12: RdPtrOffsetTxDq: 06
N6.C2.D1.R0.S07: Total Delay in PI ticks: TxDQS = 985, TxDQ = 948
N0.C2.D0.R1.S11: Total Delay in PI ticks: TxDQS = 983, TxDQ = 950
N2.C0.D1.R0.S00: wrcmd2dqsstartlatency: 04
N4.C0.D0.R0.S13: RdPtrOffsetTxDq: 06
N6.C2.D1.R0.S08: Total Delay in PI ticks: TxDQS = 949, TxDQ = 912
N0.C2.D0.R1.S12: Total Delay in PI ticks: TxDQS = 966, TxDQ = 933
N2.C0.D1.R0.S00: RdPtrOffsetTxDq: 06
N4.C0.D0.R0.S14: RdPtrOffsetTxDq: 06
N6.C2.D1.R0.S09: Total Delay in PI ticks: TxDQS = 1016, TxDQ = 981
N0.C2.D0.R1.S13: Total Delay in PI ticks: TxDQS = 926, TxDQ = 893
N2.C0.D1.R0.S00: RdPtrOffsetTxDqs: 07
N4.C0.D0.R0.S15: RdPtrOffsetTxDq: 06
N6.C2.D1.R0.S10: Total Delay in PI ticks: TxDQS = 1001, TxDQ = 967
N0.C2.D0.R1.S14: Total Delay in PI ticks: TxDQS = 952, TxDQ = 919
N2.C0.D1.R0.S00: PiTxDqs: 55
N4.C0.D0.R0.S16: RdPtrOffsetTxDq: 06
N6.C2.D1.R0.S11: Total Delay in PI ticks: TxDQS = 992, TxDQ = 959
N0.C2.D0.R1.S15: Total Delay in PI ticks: TxDQS = 952, TxDQ = 918
N2.C0.D1.R0.S01: wrcmd2dqsstartlatency: 04
N4.C0.D0.R0.S17: RdPtrOffsetTxDq: 06
N6.C2.D1.R0.S12: Total Delay in PI ticks: TxDQS = 976, TxDQ = 941
N0.C2.D0.R1.S16: Total Delay in PI ticks: TxDQS = 976, TxDQ = 942
N2.C0.D1.R0.S01: RdPtrOffsetTxDq: 06
N4.C0.D0.R0.S00: RdPtrOffsetTxDq: 08
N6.C2.D1.R0.S13: Total Delay in PI ticks: TxDQS = 934, TxDQ = 900
N0.C2.D0.R1.S17: Total Delay in PI ticks: TxDQS = 942, TxDQ = 908
N2.C0.D1.R0.S01: RdPtrOffsetTxDqs: 07
N4.C0.D0.R0.S01: RdPtrOffsetTxDq: 08
N6.C2.D1.R0.S14: Total Delay in PI ticks: TxDQS = 964, TxDQ = 929
N0.C2.D1.R0.S00: Total Delay in PI ticks: TxDQS = 1017, TxDQ = 982
N2.C0.D1.R0.S01: PiTxDqs: 41
N4.C0.D0.R0.S02: RdPtrOffsetTxDq: 07
N6.C2.D1.R0.S15: Total Delay in PI ticks: TxDQS = 960, TxDQ = 926
N0.C2.D1.R0.S01: Total Delay in PI ticks: TxDQS = 1002, TxDQ = 965
N2.C0.D1.R0.S02: wrcmd2dqsstartlatency: 04
N4.C0.D0.R0.S03: RdPtrOffsetTxDq: 07
N6.C2.D1.R0.S16: Total Delay in PI ticks: TxDQS = 983, TxDQ = 947
N0.C2.D1.R0.S02: Total Delay in PI ticks: TxDQS = 994, TxDQ = 958
N2.C0.D1.R0.S02: RdPtrOffsetTxDq: 05
N4.C0.D0.R0.S04: RdPtrOffsetTxDq: 07
N6.C2.D1.R0.S17: Total Delay in PI ticks: TxDQS = 951, TxDQ = 918
N0.C2.D1.R0.S03: Total Delay in PI ticks: TxDQS = 976, TxDQ = 940
N2.C0.D1.R0.S02: RdPtrOffsetTxDqs: 07
N4.C0.D0.R0.S05: RdPtrOffsetTxDq: 07
N6.C2.D1.R1.S00: Total Delay in PI ticks: TxDQS = 1010, TxDQ = 977
N0.C2.D1.R0.S04: Total Delay in PI ticks: TxDQS = 934, TxDQ = 899
N2.C0.D1.R0.S02: PiTxDqs: 27
N4.C0.D0.R0.S06: RdPtrOffsetTxDq: 07
N6.C2.D1.R1.S01: Total Delay in PI ticks: TxDQS = 996, TxDQ = 960
N0.C2.D1.R0.S05: Total Delay in PI ticks: TxDQS = 964, TxDQ = 928
N2.C0.D1.R0.S03: wrcmd2dqsstartlatency: 04
N4.C0.D0.R0.S07: RdPtrOffsetTxDq: 07
N6.C2.D1.R1.S02: Total Delay in PI ticks: TxDQS = 986, TxDQ = 951
N0.C2.D1.R0.S06: Total Delay in PI ticks: TxDQS = 961, TxDQ = 924
N2.C0.D1.R0.S03: RdPtrOffsetTxDq: 05
N4.C0.D0.R0.S08: RdPtrOffsetTxDq: 07
N6.C2.D1.R1.S03: Total Delay in PI ticks: TxDQS = 971, TxDQ = 935
N0.C2.D1.R0.S07: Total Delay in PI ticks: TxDQS = 982, TxDQ = 947
N2.C0.D1.R0.S03: RdPtrOffsetTxDqs: 07
N4.C0.D0.R0.S09: RdPtrOffsetTxDq: 08
N6.C2.D1.R1.S04: Total Delay in PI ticks: TxDQS = 929, TxDQ = 896
N0.C2.D1.R0.S08: Total Delay in PI ticks: TxDQS = 952, TxDQ = 916
N2.C0.D1.R0.S03: PiTxDqs: 09
N4.C0.D0.R0.S10: RdPtrOffsetTxDq: 08
N6.C2.D1.R1.S05: Total Delay in PI ticks: TxDQS = 960, TxDQ = 924
N0.C2.D1.R0.S09: Total Delay in PI ticks: TxDQS = 1015, TxDQ = 981
N2.C0.D1.R0.S04: wrcmd2dqsstartlatency: 04
N4.C0.D0.R0.S11: RdPtrOffsetTxDq: 07
N6.C2.D1.R1.S06: Total Delay in PI ticks: TxDQS = 956, TxDQ = 920
N0.C2.D1.R0.S10: Total Delay in PI ticks: TxDQS = 1004, TxDQ = 969
N2.C0.D1.R0.S04: RdPtrOffsetTxDq: 05
N4.C0.D0.R0.S12: RdPtrOffsetTxDq: 07
N6.C2.D1.R1.S07: Total Delay in PI ticks: TxDQS = 980, TxDQ = 943
N0.C2.D1.R0.S11: Total Delay in PI ticks: TxDQS = 992, TxDQ = 958
N2.C0.D1.R0.S04: RdPtrOffsetTxDqs: 06
N4.C0.D0.R0.S13: RdPtrOffsetTxDq: 07
N6.C2.D1.R1.S08: Total Delay in PI ticks: TxDQS = 943, TxDQ = 906
N0.C2.D1.R0.S12: Total Delay in PI ticks: TxDQS = 974, TxDQ = 938
N2.C0.D1.R0.S04: PiTxDqs: 41
N4.C0.D0.R0.S14: RdPtrOffsetTxDq: 07
N6.C2.D1.R1.S09: Total Delay in PI ticks: TxDQS = 1008, TxDQ = 973
N0.C2.D1.R0.S13: Total Delay in PI ticks: TxDQS = 935, TxDQ = 900
N2.C0.D1.R0.S05: wrcmd2dqsstartlatency: 04
N4.C0.D0.R0.S15: RdPtrOffsetTxDq: 07
N6.C2.D1.R1.S10: Total Delay in PI ticks: TxDQS = 996, TxDQ = 962
N0.C2.D1.R0.S14: Total Delay in PI ticks: TxDQS = 960, TxDQ = 925
N2.C0.D1.R0.S05: RdPtrOffsetTxDq: 05
N4.C0.D0.R0.S16: RdPtrOffsetTxDq: 07
N6.C2.D1.R1.S11: Total Delay in PI ticks: TxDQS = 988, TxDQ = 954
N0.C2.D1.R0.S15: Total Delay in PI ticks: TxDQS = 964, TxDQ = 928
N2.C0.D1.R0.S05: RdPtrOffsetTxDqs: 06
N4.C0.D0.R0.S17: RdPtrOffsetTxDq: 07
N6.C2.D1.R1.S12: Total Delay in PI ticks: TxDQS = 975, TxDQ = 940
N0.C2.D1.R0.S16: Total Delay in PI ticks: TxDQS = 982, TxDQ = 947
N2.C0.D1.R0.S05: PiTxDqs: 59
N4.C0.D0.R0.S00: Total Delay in PI ticks: TxDQ = 986
N6.C2.D1.R1.S13: Total Delay in PI ticks: TxDQS = 930, TxDQ = 896
N0.C2.D1.R0.S17: Total Delay in PI ticks: TxDQS = 952, TxDQ = 916
N2.C0.D1.R0.S06: wrcmd2dqsstartlatency: 04
N4.C0.D0.R0.S01: Total Delay in PI ticks: TxDQ = 964
N6.C2.D1.R1.S14: Total Delay in PI ticks: TxDQS = 958, TxDQ = 923
N0.C2.D1.R1.S00: Total Delay in PI ticks: TxDQS = 1012, TxDQ = 977
N2.C0.D1.R0.S06: RdPtrOffsetTxDq: 05
N4.C0.D0.R0.S02: Total Delay in PI ticks: TxDQ = 956
N6.C2.D1.R1.S15: Total Delay in PI ticks: TxDQS = 958, TxDQ = 924
N0.C2.D1.R1.S01: Total Delay in PI ticks: TxDQS = 1000, TxDQ = 963
N2.C0.D1.R0.S06: RdPtrOffsetTxDqs: 06
N4.C0.D0.R0.S03: Total Delay in PI ticks: TxDQ = 936
N6.C2.D1.R1.S16: Total Delay in PI ticks: TxDQS = 980, TxDQ = 944
N0.C2.D1.R1.S02: Total Delay in PI ticks: TxDQS = 989, TxDQ = 953
N2.C0.D1.R0.S06: PiTxDqs: 62
N4.C0.D0.R0.S04: Total Delay in PI ticks: TxDQ = 906
N6.C2.D1.R1.S17: Total Delay in PI ticks: TxDQS = 944, TxDQ = 911
N0.C2.D1.R1.S03: Total Delay in PI ticks: TxDQS = 972, TxDQ = 936
N2.C0.D1.R0.S07: wrcmd2dqsstartlatency: 04
N4.C0.D0.R0.S05: Total Delay in PI ticks: TxDQ = 923
N6.C3.D0.R0: Write Training Coarse, lower nibbles / bytes
N0.C2.D1.R1.S04: Total Delay in PI ticks: TxDQS = 933, TxDQ = 898
N2.C0.D1.R0.S07: RdPtrOffsetTxDq: 05
N4.C0.D0.R0.S06: Total Delay in PI ticks: TxDQ = 926
N6.C3.D0.R0.S00: Dq Delay estimate: 475
N0.C2.D1.R1.S05: Total Delay in PI ticks: TxDQS = 961, TxDQ = 926
N2.C0.D1.R0.S07: RdPtrOffsetTxDqs: 07
N4.C0.D0.R0.S07: Total Delay in PI ticks: TxDQ = 941
N6.C3.D0.R0.S01: Dq Delay estimate: 458
N0.C2.D1.R1.S06: Total Delay in PI ticks: TxDQS = 956, TxDQ = 920
N2.C0.D1.R0.S07: PiTxDqs: 14
N4.C0.D0.R0.S08: Total Delay in PI ticks: TxDQ = 918
N6.C3.D0.R0.S02: Dq Delay estimate: 451
N0.C2.D1.R1.S07: Total Delay in PI ticks: TxDQS = 978, TxDQ = 942
N2.C0.D1.R0.S08: wrcmd2dqsstartlatency: 04
N4.C0.D0.R0.S09: Total Delay in PI ticks: TxDQ = 985
N6.C3.D0.R0.S03: Dq Delay estimate: 434
N0.C2.D1.R1.S08: Total Delay in PI ticks: TxDQS = 945, TxDQ = 909
N2.C0.D1.R0.S08: RdPtrOffsetTxDq: 05
N4.C0.D0.R0.S10: Total Delay in PI ticks: TxDQ = 963
N6.C3.D0.R0.S04: Dq Delay estimate: 394
N0.C2.D1.R1.S09: Total Delay in PI ticks: TxDQS = 1014, TxDQ = 980
N2.C0.D1.R0.S08: RdPtrOffsetTxDqs: 06
N4.C0.D0.R0.S11: Total Delay in PI ticks: TxDQ = 952
N6.C3.D0.R0.S05: Dq Delay estimate: 409
N0.C2.D1.R1.S10: Total Delay in PI ticks: TxDQS = 1001, TxDQ = 965
N2.C0.D1.R0.S08: PiTxDqs: 49
N4.C0.D0.R0.S12: Total Delay in PI ticks: TxDQ = 936
N6.C3.D0.R0.S06: Dq Delay estimate: 426
N0.C2.D1.R1.S11: Total Delay in PI ticks: TxDQS = 991, TxDQ = 957
N2.C0.D1.R0.S09: wrcmd2dqsstartlatency: 04
N4.C0.D0.R0.S13: Total Delay in PI ticks: TxDQ = 906
N6.C3.D0.R0.S07: Dq Delay estimate: 440
N0.C2.D1.R1.S12: Total Delay in PI ticks: TxDQS = 973, TxDQ = 937
N2.C0.D1.R0.S09: RdPtrOffsetTxDq: 06
N4.C0.D0.R0.S14: Total Delay in PI ticks: TxDQ = 920
N6.C3.D0.R0.S08: Dq Delay estimate: 416
N0.C2.D1.R1.S13: Total Delay in PI ticks: TxDQS = 935, TxDQ = 900
N2.C0.D1.R0.S09: RdPtrOffsetTxDqs: 07
N4.C0.D0.R0.S15: Total Delay in PI ticks: TxDQ = 925
ACCM: 9F 0F0F9F9F 0F0F0F0F
N0.C2.D1.R1.S14: Total Delay in PI ticks: TxDQS = 960, TxDQ = 925
N2.C0.D1.R0.S09: PiTxDqs: 57
N4.C0.D0.R0.S16: Total Delay in PI ticks: TxDQ = 941
ACCM: 9F 0F0F9F9F 0F0F0F0F
N0.C2.D1.R1.S15: Total Delay in PI ticks: TxDQS = 958, TxDQ = 923
N2.C0.D1.R0.S10: wrcmd2dqsstartlatency: 04
N4.C0.D0.R0.S17: Total Delay in PI ticks: TxDQ = 917
ACCM: 9F FFFF9F9F FFFFFFFF
N0.C2.D1.R1.S16: Total Delay in PI ticks: TxDQS = 983, TxDQ = 947
N2.C0.D1.R0.S10: RdPtrOffsetTxDq: 06
N4.C0.D0.R1.S00: wrcmd2dqsstartlatency: 04
ACCM: 9F FFFF9F9F FFFFFFFF
N0.C2.D1.R1.S17: Total Delay in PI ticks: TxDQS = 946, TxDQ = 910
N2.C0.D1.R0.S10: RdPtrOffsetTxDqs: 07
N4.C0.D0.R1.S00: RdPtrOffsetTxDq: 06
N6.C3.D0.R0: CheckMCTest: result = 0x3FFFF
N0.C3.D0.R0: Write Training Coarse, lower nibbles / bytes
N2.C0.D1.R0.S10: PiTxDqs: 39
N4.C0.D0.R1.S00: RdPtrOffsetTxDqs: 07
ACCM: DF 0F0FDFDF 0F0F0F0F
N0.C3.D0.R0.S00: Dq Delay estimate: 354
N2.C0.D1.R0.S11: wrcmd2dqsstartlatency: 04
N4.C0.D0.R1.S00: PiTxDqs: 51
ACCM: DF 0F0FDFDF 0F0F0F0F
N0.C3.D0.R0.S01: Dq Delay estimate: 464
N2.C0.D1.R0.S11: RdPtrOffsetTxDq: 05
N4.C0.D0.R1.S01: wrcmd2dqsstartlatency: 04
ACCM: DF FFFFDFDF FFFFFFFF
N0.C3.D0.R0.S02: Dq Delay estimate: 453
N2.C0.D1.R0.S11: RdPtrOffsetTxDqs: 07
N4.C0.D0.R1.S01: RdPtrOffsetTxDq: 05
ACCM: DF FFFFDFDF FFFFFFFF
N0.C3.D0.R0.S03: Dq Delay estimate: 434
N2.C0.D1.R0.S11: PiTxDqs: 29
N4.C0.D0.R1.S01: RdPtrOffsetTxDqs: 07
N6.C3.D0.R0: CheckMCTest: result = 0x3FFFF
N0.C3.D0.R0.S04: Dq Delay estimate: 401
N2.C0.D1.R0.S12: wrcmd2dqsstartlatency: 04
N4.C0.D0.R1.S01: PiTxDqs: 33
ACCM: DF 0F0FDFDF 0F0F0F0F
N0.C3.D0.R0.S05: Dq Delay estimate: 416
N2.C0.D1.R0.S12: RdPtrOffsetTxDq: 05
N4.C0.D0.R1.S02: wrcmd2dqsstartlatency: 04
ACCM: DF 0F0FDFDF 0F0F0F0F
N0.C3.D0.R0.S06: Dq Delay estimate: 430
N2.C0.D1.R0.S12: RdPtrOffsetTxDqs: 07
N4.C0.D0.R1.S02: RdPtrOffsetTxDq: 05
ACCM: D0 FBFBDBDB FBFBFBFB
N0.C3.D0.R0.S07: Dq Delay estimate: 448
N2.C0.D1.R0.S12: PiTxDqs: 13
N4.C0.D0.R1.S02: RdPtrOffsetTxDqs: 07
ACCM: D0 FBFBDBDB FBFBFBFB
N0.C3.D0.R0.S08: Dq Delay estimate: 420
N2.C0.D1.R0.S13: wrcmd2dqsstartlatency: 04
N4.C0.D0.R1.S02: PiTxDqs: 23
N6.C3.D0.R0: CheckMCTest: result = 0x3FFFF
ACCM: 0F 0F0F0F9F 0F0F0F0F
N2.C0.D1.R0.S13: RdPtrOffsetTxDq: 05
N4.C0.D0.R1.S03: wrcmd2dqsstartlatency: 04
ACCM: DF 0F0FDFDF 0F0F0F0F
ACCM: 0F 0F0F0F9F 0F0F0F0F
N2.C0.D1.R0.S13: RdPtrOffsetTxDqs: 06
N4.C0.D0.R1.S03: RdPtrOffsetTxDq: 05
ACCM: DF 0F0FDFDF 0F0F0F0F
ACCM: FF FFFFFF9F FFFFFFF9
N2.C0.D1.R0.S13: PiTxDqs: 42
N4.C0.D0.R1.S03: RdPtrOffsetTxDqs: 07
ACCM: D0 FFFFDFDF FFFFFBFF
ACCM: FF FFFFFF9F FFFFFFF9
N2.C0.D1.R0.S14: wrcmd2dqsstartlatency: 04
N4.C0.D0.R1.S03: PiTxDqs: 07
ACCM: D0 FFFFDFDF FFFFFBFF
N0.C3.D0.R0: CheckMCTest: result = 0x3FFFF
N2.C0.D1.R0.S14: RdPtrOffsetTxDq: 05
N4.C0.D0.R1.S04: wrcmd2dqsstartlatency: 04
N6.C3.D0.R0: CheckMCTest: result = 0x3FFFF
ACCM: 0F 0F0F0FDF 0F0F0F0F
N2.C0.D1.R0.S14: RdPtrOffsetTxDqs: 06
N4.C0.D0.R1.S04: RdPtrOffsetTxDq: 04
ACCM: D0 0000D0D0 00000000
ACCM: 0F 0F0F0FDF 0F0F0F0F
N2.C0.D1.R0.S14: PiTxDqs: 61
N4.C0.D0.R1.S04: RdPtrOffsetTxDqs: 06
ACCM: D0 0000D0D0 00000000
ACCM: FF FFFFFFDF FFFFFFFD
N2.C0.D1.R0.S15: wrcmd2dqsstartlatency: 04
N4.C0.D0.R1.S04: PiTxDqs: 35
ACCM: D0 F0F0D0D0 F0F0F0F0
ACCM: FF FFFFFFDF FFFFFFFD
N2.C0.D1.R0.S15: RdPtrOffsetTxDq: 05
N4.C0.D0.R1.S05: wrcmd2dqsstartlatency: 04
ACCM: D0 F0F0D0D0 F0F0F0F0
N0.C3.D0.R0: CheckMCTest: result = 0x3FFFF
N2.C0.D1.R0.S15: RdPtrOffsetTxDqs: 06
N4.C0.D0.R1.S05: RdPtrOffsetTxDq: 05
N6.C3.D0.R0: CheckMCTest: result = 0x3FE00
ACCM: 0F 0F0F0FDF 0F0F0F00
N2.C0.D1.R0.S15: PiTxDqs: 62
N4.C0.D0.R1.S05: RdPtrOffsetTxDqs: 06
ACCM: D0 0000D0D0 00000000
ACCM: 0F 0F0F0FDF 0F0F0F00
N2.C0.D1.R0.S16: wrcmd2dqsstartlatency: 04
N4.C0.D0.R1.S05: PiTxDqs: 54
ACCM: D0 0000D0D0 00000000
ACCM: F0 FBF0FBDB F0F0FBF0
N2.C0.D1.R0.S16: RdPtrOffsetTxDq: 05
N4.C0.D0.R1.S06: wrcmd2dqsstartlatency: 04
ACCM: D0 F0F0D0D0 F0F0F0F0
ACCM: F0 FBF0FBDB F0F0FBF0
N2.C0.D1.R0.S16: RdPtrOffsetTxDqs: 07
N4.C0.D0.R1.S06: RdPtrOffsetTxDq: 05
ACCM: D0 F0F0D0D0 F0F0F0F0
N0.C3.D0.R0: CheckMCTest: result = 0x3FFFE
N2.C0.D1.R0.S16: PiTxDqs: 14
N4.C0.D0.R1.S06: RdPtrOffsetTxDqs: 06
N6.C3.D0.R0: CheckMCTest: result = 0x3FE00
ACCM: 0F 0F0F0FDF 0F0F0F00
N2.C0.D1.R0.S17: wrcmd2dqsstartlatency: 04
N4.C0.D0.R1.S06: PiTxDqs: 55
N6.C3.D0.R0.S00: Offset Found: RdPtrOffsetDqs = 007
ACCM: 0F 0F0F0FDF 0F0F0F00
N2.C0.D1.R0.S17: RdPtrOffsetTxDq: 05
N4.C0.D0.R1.S07: wrcmd2dqsstartlatency: 04
N6.C3.D0.R0.S01: Offset Found: RdPtrOffsetDqs = 007
ACCM: F0 FFF0FFDF F0F0FFF0
N2.C0.D1.R0.S17: RdPtrOffsetTxDqs: 06
N4.C0.D0.R1.S07: RdPtrOffsetTxDq: 05
N6.C3.D0.R0.S02: Offset Found: RdPtrOffsetDqs = 007
ACCM: F0 FFF0FFDF F0F0FFF0
N2.C0.D1.R0.S17: PiTxDqs: 50
N4.C0.D0.R1.S07: RdPtrOffsetTxDqs: 07
N6.C3.D0.R0.S03: Offset Found: RdPtrOffsetDqs = 007
N0.C3.D0.R0: CheckMCTest: result = 0x3FFFE
N2.C0.D1.R0.S00: RdPtrOffsetTxDq: 07
N4.C0.D0.R1.S07: PiTxDqs: 06
N6.C3.D0.R0.S04: Offset Found: RdPtrOffsetDqs = 006
N0.C3.D0.R0.S00: Offset Found: RdPtrOffsetDqs = 008
N2.C0.D1.R0.S01: RdPtrOffsetTxDq: 07
N4.C0.D0.R1.S08: wrcmd2dqsstartlatency: 04
N6.C3.D0.R0.S05: Offset Found: RdPtrOffsetDqs = 006
ACCM: 00 000000D0 00000000
N2.C0.D1.R0.S02: RdPtrOffsetTxDq: 06
N4.C0.D0.R1.S08: RdPtrOffsetTxDq: 05
N6.C3.D0.R0.S06: Offset Found: RdPtrOffsetDqs = 007
ACCM: 00 000000D0 00000000
N2.C0.D1.R0.S03: RdPtrOffsetTxDq: 06
N4.C0.D0.R1.S08: RdPtrOffsetTxDqs: 06
N6.C3.D0.R0.S07: Offset Found: RdPtrOffsetDqs = 007
ACCM: F0 F0F0F0D0 F0F0F0F0
N2.C0.D1.R0.S04: RdPtrOffsetTxDq: 06
N4.C0.D0.R1.S08: PiTxDqs: 48
N6.C3.D0.R0.S08: Offset Found: RdPtrOffsetDqs = 007
ACCM: F0 F0F0F0D0 F0F0F0F0
N2.C0.D1.R0.S05: RdPtrOffsetTxDq: 06
N4.C0.D0.R1.S09: wrcmd2dqsstartlatency: 04
N6.C3.D0.R0: Write Training Coarse, upper nibbles
N0.C3.D0.R0: CheckMCTest: result = 0x3FE00
N2.C0.D1.R0.S06: RdPtrOffsetTxDq: 06
N4.C0.D0.R1.S09: RdPtrOffsetTxDq: 06
N6.C3.D0.R0.S09: Dq Delay estimate: 473
ACCM: 00 000000D0 00000000
N2.C0.D1.R0.S07: RdPtrOffsetTxDq: 06
N4.C0.D0.R1.S09: RdPtrOffsetTxDqs: 07
N6.C3.D0.R0.S10: Dq Delay estimate: 460
ACCM: 00 000000D0 00000000
N2.C0.D1.R0.S08: RdPtrOffsetTxDq: 06
N4.C0.D0.R1.S09: PiTxDqs: 50
N6.C3.D0.R0.S11: Dq Delay estimate: 449
ACCM: F0 F0F0F0D0 F0F0F0F0
N2.C0.D1.R0.S09: RdPtrOffsetTxDq: 07
N4.C0.D0.R1.S10: wrcmd2dqsstartlatency: 04
N6.C3.D0.R0.S12: Dq Delay estimate: 431
ACCM: F0 F0F0F0D0 F0F0F0F0
N2.C0.D1.R0.S10: RdPtrOffsetTxDq: 07
N4.C0.D0.R1.S10: RdPtrOffsetTxDq: 05
N6.C3.D0.R0.S13: Dq Delay estimate: 396
N0.C3.D0.R0: CheckMCTest: result = 0x3FE00
N2.C0.D1.R0.S11: RdPtrOffsetTxDq: 06
N4.C0.D0.R1.S10: RdPtrOffsetTxDqs: 07
N6.C3.D0.R0.S14: Dq Delay estimate: 414
N0.C3.D0.R0.S00: Offset Found: RdPtrOffsetDqs = 008
N2.C0.D1.R0.S12: RdPtrOffsetTxDq: 06
N4.C0.D0.R1.S10: PiTxDqs: 33
N6.C3.D0.R0.S15: Dq Delay estimate: 427
N0.C3.D0.R0.S01: Offset Found: RdPtrOffsetDqs = 007
N2.C0.D1.R0.S13: RdPtrOffsetTxDq: 06
N4.C0.D0.R1.S11: wrcmd2dqsstartlatency: 04
N6.C3.D0.R0.S16: Dq Delay estimate: 443
N0.C3.D0.R0.S02: Offset Found: RdPtrOffsetDqs = 007
N2.C0.D1.R0.S14: RdPtrOffsetTxDq: 06
N4.C0.D0.R1.S11: RdPtrOffsetTxDq: 05
N6.C3.D0.R0.S17: Dq Delay estimate: 414
N0.C3.D0.R0.S03: Offset Found: RdPtrOffsetDqs = 007
N2.C0.D1.R0.S15: RdPtrOffsetTxDq: 06
N4.C0.D0.R1.S11: RdPtrOffsetTxDqs: 07
ACCM: F0 F0F0F0F0 F0F0F0F0
N0.C3.D0.R0.S04: Offset Found: RdPtrOffsetDqs = 006
N2.C0.D1.R0.S16: RdPtrOffsetTxDq: 06
N4.C0.D0.R1.S11: PiTxDqs: 23
ACCM: F0 F0F0F0F0 F0F0F0F0
N0.C3.D0.R0.S05: Offset Found: RdPtrOffsetDqs = 007
N2.C0.D1.R0.S17: RdPtrOffsetTxDq: 06
N4.C0.D0.R1.S12: wrcmd2dqsstartlatency: 04
ACCM: F0 F0F0F0F0 F0F0F0F0
N0.C3.D0.R0.S06: Offset Found: RdPtrOffsetDqs = 007
N2.C0.D1.R0.S00: RdPtrOffsetTxDq: 08
N4.C0.D0.R1.S12: RdPtrOffsetTxDq: 05
ACCM: F0 F0F0F0F0 F0F0F0F0
N0.C3.D0.R0.S07: Offset Found: RdPtrOffsetDqs = 007
N2.C0.D1.R0.S01: RdPtrOffsetTxDq: 08
N4.C0.D0.R1.S12: RdPtrOffsetTxDqs: 07
N6.C3.D0.R0: CheckMCTest: result = 0x3FE00
N0.C3.D0.R0.S08: Offset Found: RdPtrOffsetDqs = 007
N2.C0.D1.R0.S02: RdPtrOffsetTxDq: 07
N4.C0.D0.R1.S12: PiTxDqs: 07
ACCM: F0 F0F0F0F0 F0F0F0F0
N0.C3.D0.R0: Write Training Coarse, upper nibbles
N2.C0.D1.R0.S03: RdPtrOffsetTxDq: 07
N4.C0.D0.R1.S13: wrcmd2dqsstartlatency: 04
ACCM: F0 F0F0F0F0 F0F0F0F0
N0.C3.D0.R0.S09: Dq Delay estimate: 352
N2.C0.D1.R0.S04: RdPtrOffsetTxDq: 07
N4.C0.D0.R1.S13: RdPtrOffsetTxDq: 05
ACCM: F0 F0F0F0F0 F0F0F0F0
N0.C3.D0.R0.S10: Dq Delay estimate: 465
N2.C0.D1.R0.S05: RdPtrOffsetTxDq: 07
N4.C0.D0.R1.S13: RdPtrOffsetTxDqs: 06
ACCM: F0 F0F0F0F0 F0F0F0F0
N0.C3.D0.R0.S11: Dq Delay estimate: 456
N2.C0.D1.R0.S06: RdPtrOffsetTxDq: 07
N4.C0.D0.R1.S13: PiTxDqs: 37
N6.C3.D0.R0: CheckMCTest: result = 0x3FE00
N0.C3.D0.R0.S12: Dq Delay estimate: 438
N2.C0.D1.R0.S07: RdPtrOffsetTxDq: 07
N4.C0.D0.R1.S14: wrcmd2dqsstartlatency: 04
ACCM: F0 F0F0F0F0 F0F0F0F0
N0.C3.D0.R0.S13: Dq Delay estimate: 399
N2.C0.D1.R0.S08: RdPtrOffsetTxDq: 07
N4.C0.D0.R1.S14: RdPtrOffsetTxDq: 05
ACCM: F0 F0F0F0F0 F0F0F0F0
N0.C3.D0.R0.S14: Dq Delay estimate: 416
N2.C0.D1.R0.S09: RdPtrOffsetTxDq: 08
N4.C0.D0.R1.S14: RdPtrOffsetTxDqs: 06
ACCM: 00 B0B0B0B0 B000B0B0
N0.C3.D0.R0.S15: Dq Delay estimate: 434
N2.C0.D1.R0.S10: RdPtrOffsetTxDq: 08
N4.C0.D0.R1.S14: PiTxDqs: 51
ACCM: 00 B0B0B0B0 B000B0B0
N0.C3.D0.R0.S16: Dq Delay estimate: 444
N2.C0.D1.R0.S11: RdPtrOffsetTxDq: 07
N4.C0.D0.R1.S15: wrcmd2dqsstartlatency: 04
N6.C3.D0.R0: CheckMCTest: result = 0x3FE00
N0.C3.D0.R0.S17: Dq Delay estimate: 421
N2.C0.D1.R0.S12: RdPtrOffsetTxDq: 07
N4.C0.D0.R1.S15: RdPtrOffsetTxDq: 05
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: F0 F0F0F0F0 F0F0F0F0
N2.C0.D1.R0.S13: RdPtrOffsetTxDq: 07
N4.C0.D0.R1.S15: RdPtrOffsetTxDqs: 06
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: F0 F0F0F0F0 F0F0F0F0
N2.C0.D1.R0.S14: RdPtrOffsetTxDq: 07
N4.C0.D0.R1.S15: PiTxDqs: 56
ACCM: 00 F0F0F0F0 F000F0F0
ACCM: F0 F0F0F0F0 F0F0F0B0
N2.C0.D1.R0.S15: RdPtrOffsetTxDq: 07
N4.C0.D0.R1.S16: wrcmd2dqsstartlatency: 04
ACCM: 00 F0F0F0F0 F000F0F0
ACCM: F0 F0F0F0F0 F0F0F0B0
N2.C0.D1.R0.S16: RdPtrOffsetTxDq: 07
N4.C0.D0.R1.S16: RdPtrOffsetTxDq: 05
N6.C3.D0.R0: CheckMCTest: result = 0x3FE00
N0.C3.D0.R0: CheckMCTest: result = 0x3FE00
N2.C0.D1.R0.S17: RdPtrOffsetTxDq: 07
N4.C0.D0.R1.S16: RdPtrOffsetTxDqs: 07
N6.C3.D0.R0: CheckMCTest: passed
ACCM: F0 F0F0F0F0 F0F0F0F0
N2.C0.D1.R0.S00: Total Delay in PI ticks: TxDQ = 984
N4.C0.D0.R1.S16: PiTxDqs: 07
N6.C3.D0.R0: CheckMCTest: passed
ACCM: F0 F0F0F0F0 F0F0F0F0
N2.C0.D1.R0.S01: Total Delay in PI ticks: TxDQ = 969
N4.C0.D0.R1.S17: wrcmd2dqsstartlatency: 04
N6.C3.D0.R0.S09: Offset Found: RdPtrOffsetDqs = 007
ACCM: F0 F0F0F0F0 F0F0F0F0
N2.C0.D1.R0.S02: Total Delay in PI ticks: TxDQ = 954
N4.C0.D0.R1.S17: RdPtrOffsetTxDq: 05
N6.C3.D0.R0.S10: Offset Found: RdPtrOffsetDqs = 007
ACCM: F0 F0F0F0F0 F0F0F0F0
N2.C0.D1.R0.S03: Total Delay in PI ticks: TxDQ = 937
N4.C0.D0.R1.S17: RdPtrOffsetTxDqs: 06
N6.C3.D0.R0.S11: Offset Found: RdPtrOffsetDqs = 007
N0.C3.D0.R0: CheckMCTest: result = 0x3FE00
N2.C0.D1.R0.S04: Total Delay in PI ticks: TxDQ = 904
N4.C0.D0.R1.S17: PiTxDqs: 46
N6.C3.D0.R0.S12: Offset Found: RdPtrOffsetDqs = 007
ACCM: F0 F0F0F0F0 F0F0F000
N2.C0.D1.R0.S05: Total Delay in PI ticks: TxDQ = 922
N4.C0.D0.R1.S00: RdPtrOffsetTxDq: 07
N6.C3.D0.R0.S13: Offset Found: RdPtrOffsetDqs = 006
ACCM: F0 F0F0F0F0 F0F0F000
N2.C0.D1.R0.S06: Total Delay in PI ticks: TxDQ = 927
N4.C0.D0.R1.S01: RdPtrOffsetTxDq: 06
N6.C3.D0.R0.S14: Offset Found: RdPtrOffsetDqs = 006
ACCM: B0 00B00000 0000B000
N2.C0.D1.R0.S07: Total Delay in PI ticks: TxDQ = 942
N4.C0.D0.R1.S02: RdPtrOffsetTxDq: 06
N6.C3.D0.R0.S15: Offset Found: RdPtrOffsetDqs = 007
ACCM: B0 00B00000 0000B000
N2.C0.D1.R0.S08: Total Delay in PI ticks: TxDQ = 915
N4.C0.D0.R1.S03: RdPtrOffsetTxDq: 06
N6.C3.D0.R0.S16: Offset Found: RdPtrOffsetDqs = 007
N0.C3.D0.R0: CheckMCTest: result = 0x3FC00
N2.C0.D1.R0.S09: Total Delay in PI ticks: TxDQ = 984
N4.C0.D0.R1.S04: RdPtrOffsetTxDq: 05
N6.C3.D0.R0.S17: Offset Found: RdPtrOffsetDqs = 006
ACCM: F0 F0F0F0F0 F0F0F000
N2.C0.D1.R0.S10: Total Delay in PI ticks: TxDQ = 968
N4.C0.D0.R1.S05: RdPtrOffsetTxDq: 06
N6.C3.D0.R1: Write Training Coarse, lower nibbles / bytes
ACCM: F0 F0F0F0F0 F0F0F000
N2.C0.D1.R0.S11: Total Delay in PI ticks: TxDQ = 955
N4.C0.D0.R1.S06: RdPtrOffsetTxDq: 06
N6.C3.D0.R1.S00: Dq Delay estimate: 468
ACCM: F0 00F00000 0000F000
N2.C0.D1.R0.S12: Total Delay in PI ticks: TxDQ = 938
N4.C0.D0.R1.S07: RdPtrOffsetTxDq: 06
N6.C3.D0.R1.S01: Dq Delay estimate: 452
ACCM: F0 00F00000 0000F000
N2.C0.D1.R0.S13: Total Delay in PI ticks: TxDQ = 905
N4.C0.D0.R1.S08: RdPtrOffsetTxDq: 06
N6.C3.D0.R1.S02: Dq Delay estimate: 442
N0.C3.D0.R0: CheckMCTest: result = 0x3FC00
N2.C0.D1.R0.S14: Total Delay in PI ticks: TxDQ = 925
N4.C0.D0.R1.S09: RdPtrOffsetTxDq: 07
N6.C3.D0.R1.S03: Dq Delay estimate: 426
N0.C3.D0.R0.S09: Offset Found: RdPtrOffsetDqs = 008
N2.C0.D1.R0.S15: Total Delay in PI ticks: TxDQ = 924
N4.C0.D0.R1.S10: RdPtrOffsetTxDq: 06
N6.C3.D0.R1.S04: Dq Delay estimate: 387
N0.C3.D0.R0: CheckMCTest: passed
N2.C0.D1.R0.S16: Total Delay in PI ticks: TxDQ = 941
N4.C0.D0.R1.S11: RdPtrOffsetTxDq: 06
N6.C3.D0.R1.S05: Dq Delay estimate: 404
N0.C3.D0.R0: CheckMCTest: passed
N2.C0.D1.R0.S17: Total Delay in PI ticks: TxDQ = 912
N4.C0.D0.R1.S12: RdPtrOffsetTxDq: 06
N6.C3.D0.R1.S06: Dq Delay estimate: 417
N0.C3.D0.R0.S09: Offset Found: RdPtrOffsetDqs = 008
N2.C0.D1.R1.S00: wrcmd2dqsstartlatency: 04
N4.C0.D0.R1.S13: RdPtrOffsetTxDq: 06
N6.C3.D0.R1.S07: Dq Delay estimate: 435
N0.C3.D0.R0.S10: Offset Found: RdPtrOffsetDqs = 007
N2.C0.D1.R1.S00: RdPtrOffsetTxDq: 06
N4.C0.D0.R1.S14: RdPtrOffsetTxDq: 06
N6.C3.D0.R1.S08: Dq Delay estimate: 407
N0.C3.D0.R0.S11: Offset Found: RdPtrOffsetDqs = 007
N2.C0.D1.R1.S00: RdPtrOffsetTxDqs: 07
N4.C0.D0.R1.S15: RdPtrOffsetTxDq: 06
ACCM: 0F 0F0F0F0F 0F0F0F0F
N0.C3.D0.R0.S12: Offset Found: RdPtrOffsetDqs = 007
N2.C0.D1.R1.S00: PiTxDqs: 50
N4.C0.D0.R1.S16: RdPtrOffsetTxDq: 06
ACCM: 0F 0F0F0F0F 0F0F0F0F
N0.C3.D0.R0.S13: Offset Found: RdPtrOffsetDqs = 006
N2.C0.D1.R1.S01: wrcmd2dqsstartlatency: 04
N4.C0.D0.R1.S17: RdPtrOffsetTxDq: 06
ACCM: 0F 0F0F0F0F 0F0F0F0F
N0.C3.D0.R0.S14: Offset Found: RdPtrOffsetDqs = 007
N2.C0.D1.R1.S01: RdPtrOffsetTxDq: 06
N4.C0.D0.R1.S00: RdPtrOffsetTxDq: 08
ACCM: 0F 0F0F0F0F 0F0F0F0F
N0.C3.D0.R0.S15: Offset Found: RdPtrOffsetDqs = 007
N2.C0.D1.R1.S01: RdPtrOffsetTxDqs: 07
N4.C0.D0.R1.S01: RdPtrOffsetTxDq: 07
N6.C3.D0.R1: CheckMCTest: result = 0x1FF
N0.C3.D0.R0.S16: Offset Found: RdPtrOffsetDqs = 007
N2.C0.D1.R1.S01: PiTxDqs: 38
N4.C0.D0.R1.S02: RdPtrOffsetTxDq: 07
ACCM: 0F 0F0F0F0F 0F0F0F0F
N0.C3.D0.R0.S17: Offset Found: RdPtrOffsetDqs = 007
N2.C0.D1.R1.S02: wrcmd2dqsstartlatency: 04
N4.C0.D0.R1.S03: RdPtrOffsetTxDq: 07
ACCM: 0F 0F0F0F0F 0F0F0F0F
N0.C3.D0.R1: Write Training Coarse, lower nibbles / bytes
N2.C0.D1.R1.S02: RdPtrOffsetTxDq: 05
N4.C0.D0.R1.S04: RdPtrOffsetTxDq: 06
ACCM: 0F 0F0F0F0F 0F0F0F0F
N0.C3.D0.R1.S00: Dq Delay estimate: 475
N2.C0.D1.R1.S02: RdPtrOffsetTxDqs: 07
N4.C0.D0.R1.S05: RdPtrOffsetTxDq: 07
ACCM: 0F 0F0F0F0F 0F0F0F0F
N0.C3.D0.R1.S01: Dq Delay estimate: 456
N2.C0.D1.R1.S02: PiTxDqs: 23
N4.C0.D0.R1.S06: RdPtrOffsetTxDq: 07
N6.C3.D0.R1: CheckMCTest: result = 0x1FF
N0.C3.D0.R1.S02: Dq Delay estimate: 447
N2.C0.D1.R1.S03: wrcmd2dqsstartlatency: 04
N4.C0.D0.R1.S07: RdPtrOffsetTxDq: 07
ACCM: 0F 0F0F0F0F 0F0F0F0F
N0.C3.D0.R1.S03: Dq Delay estimate: 431
N2.C0.D1.R1.S03: RdPtrOffsetTxDq: 05
N4.C0.D0.R1.S08: RdPtrOffsetTxDq: 07
ACCM: 0F 0F0F0F0F 0F0F0F0F
N0.C3.D0.R1.S04: Dq Delay estimate: 396
N2.C0.D1.R1.S03: RdPtrOffsetTxDqs: 07
N4.C0.D0.R1.S09: RdPtrOffsetTxDq: 08
ACCM: 00 0000000B 0B0B000B
N0.C3.D0.R1.S05: Dq Delay estimate: 409
N2.C0.D1.R1.S03: PiTxDqs: 07
N4.C0.D0.R1.S10: RdPtrOffsetTxDq: 07
ACCM: 00 0000000B 0B0B000B
N0.C3.D0.R1.S06: Dq Delay estimate: 423
N2.C0.D1.R1.S04: wrcmd2dqsstartlatency: 04
N4.C0.D0.R1.S11: RdPtrOffsetTxDq: 07
N6.C3.D0.R1: CheckMCTest: result = 0x1FF
N0.C3.D0.R1.S07: Dq Delay estimate: 442
N2.C0.D1.R1.S04: RdPtrOffsetTxDq: 05
N4.C0.D0.R1.S12: RdPtrOffsetTxDq: 07
ACCM: 0F 0F0F0F0F 0F0F0F0F
N0.C3.D0.R1.S08: Dq Delay estimate: 414
N2.C0.D1.R1.S04: RdPtrOffsetTxDqs: 06
N4.C0.D0.R1.S13: RdPtrOffsetTxDq: 07
ACCM: 0F 0F0F0F0F 0F0F0F0F
ACCM: 0F 0F0F0F0F 0F0F0F0F
N2.C0.D1.R1.S04: PiTxDqs: 36
N4.C0.D0.R1.S14: RdPtrOffsetTxDq: 07
ACCM: 00 0000000F 0F0F000F
ACCM: 0F 0F0F0F0F 0F0F0F0F
N2.C0.D1.R1.S05: wrcmd2dqsstartlatency: 04
N4.C0.D0.R1.S15: RdPtrOffsetTxDq: 07
ACCM: 00 0000000F 0F0F000F
ACCM: 0F 0F0F0F0F 0F0F0F0F
N2.C0.D1.R1.S05: RdPtrOffsetTxDq: 05
N4.C0.D0.R1.S16: RdPtrOffsetTxDq: 07
N6.C3.D0.R1: CheckMCTest: result = 0x1FF
ACCM: 0F 0F0F0F0F 0F0F0F0F
N2.C0.D1.R1.S05: RdPtrOffsetTxDqs: 06
N4.C0.D0.R1.S17: RdPtrOffsetTxDq: 07
N6.C3.D0.R1: CheckMCTest: passed
N0.C3.D0.R1: CheckMCTest: result = 0x1FF
N2.C0.D1.R1.S05: PiTxDqs: 56
N4.C0.D0.R1.S00: Total Delay in PI ticks: TxDQ = 978
N6.C3.D0.R1: CheckMCTest: passed
ACCM: 0F 0F0F0F0F 0F0F0F0F
N2.C0.D1.R1.S06: wrcmd2dqsstartlatency: 04
N4.C0.D0.R1.S01: Total Delay in PI ticks: TxDQ = 959
N6.C3.D0.R1.S00: Offset Found: RdPtrOffsetDqs = 007
ACCM: 0F 0F0F0F0F 0F0F0F0F
N2.C0.D1.R1.S06: RdPtrOffsetTxDq: 05
N4.C0.D0.R1.S02: Total Delay in PI ticks: TxDQ = 949
N6.C3.D0.R1.S01: Offset Found: RdPtrOffsetDqs = 007
ACCM: 0F 0F0F0F0F 0F0F0F0F
N2.C0.D1.R1.S06: RdPtrOffsetTxDqs: 06
N4.C0.D0.R1.S03: Total Delay in PI ticks: TxDQ = 933
N6.C3.D0.R1.S02: Offset Found: RdPtrOffsetDqs = 007
ACCM: 0F 0F0F0F0F 0F0F0F0F
N2.C0.D1.R1.S06: PiTxDqs: 59
N4.C0.D0.R1.S04: Total Delay in PI ticks: TxDQ = 898
N6.C3.D0.R1.S03: Offset Found: RdPtrOffsetDqs = 007
N0.C3.D0.R1: CheckMCTest: result = 0x1FF
N2.C0.D1.R1.S07: wrcmd2dqsstartlatency: 04
N4.C0.D0.R1.S05: Total Delay in PI ticks: TxDQ = 915
N6.C3.D0.R1.S04: Offset Found: RdPtrOffsetDqs = 006
ACCM: 0F 0F0F0F0F 0F0F0F0F
N2.C0.D1.R1.S07: RdPtrOffsetTxDq: 05
N4.C0.D0.R1.S06: Total Delay in PI ticks: TxDQ = 917
N6.C3.D0.R1.S05: Offset Found: RdPtrOffsetDqs = 006
ACCM: 0F 0F0F0F0F 0F0F0F0F
N2.C0.D1.R1.S07: RdPtrOffsetTxDqs: 07
N4.C0.D0.R1.S07: Total Delay in PI ticks: TxDQ = 933
N6.C3.D0.R1.S06: Offset Found: RdPtrOffsetDqs = 007
ACCM: 0B 0B0B0B0B 0B00000B
N2.C0.D1.R1.S07: PiTxDqs: 12
N4.C0.D0.R1.S08: Total Delay in PI ticks: TxDQ = 911
N6.C3.D0.R1.S07: Offset Found: RdPtrOffsetDqs = 007
ACCM: 0B 0B0B0B0B 0B00000B
N2.C0.D1.R1.S08: wrcmd2dqsstartlatency: 04
N4.C0.D0.R1.S09: Total Delay in PI ticks: TxDQ = 977
N6.C3.D0.R1.S08: Offset Found: RdPtrOffsetDqs = 006
N0.C3.D0.R1: CheckMCTest: result = 0x1FF
N2.C0.D1.R1.S08: RdPtrOffsetTxDq: 05
N4.C0.D0.R1.S10: Total Delay in PI ticks: TxDQ = 959
N6.C3.D0.R1: Write Training Coarse, upper nibbles
ACCM: 0F 0F0F0F0F 0F0F0F0F
N2.C0.D1.R1.S08: RdPtrOffsetTxDqs: 06
N4.C0.D0.R1.S11: Total Delay in PI ticks: TxDQ = 949
N6.C3.D0.R1.S09: Dq Delay estimate: 465
ACCM: 0F 0F0F0F0F 0F0F0F0F
N2.C0.D1.R1.S08: PiTxDqs: 47
N4.C0.D0.R1.S12: Total Delay in PI ticks: TxDQ = 933
N6.C3.D0.R1.S10: Dq Delay estimate: 451
ACCM: 0F 0F0F0F0F 0F00000F
N2.C0.D1.R1.S09: wrcmd2dqsstartlatency: 04
N4.C0.D0.R1.S13: Total Delay in PI ticks: TxDQ = 899
N6.C3.D0.R1.S11: Dq Delay estimate: 440
ACCM: 0F 0F0F0F0F 0F00000F
N2.C0.D1.R1.S09: RdPtrOffsetTxDq: 06
N4.C0.D0.R1.S14: Total Delay in PI ticks: TxDQ = 914
N6.C3.D0.R1.S12: Dq Delay estimate: 425
N0.C3.D0.R1: CheckMCTest: result = 0x1FF
N2.C0.D1.R1.S09: RdPtrOffsetTxDqs: 07
N4.C0.D0.R1.S15: Total Delay in PI ticks: TxDQ = 919
N6.C3.D0.R1.S13: Dq Delay estimate: 389
N0.C3.D0.R1: CheckMCTest: passed
N2.C0.D1.R1.S09: PiTxDqs: 50
N4.C0.D0.R1.S16: Total Delay in PI ticks: TxDQ = 935
N6.C3.D0.R1.S14: Dq Delay estimate: 407
N0.C3.D0.R1: CheckMCTest: passed
N2.C0.D1.R1.S10: wrcmd2dqsstartlatency: 04
N4.C0.D0.R1.S17: Total Delay in PI ticks: TxDQ = 907
N6.C3.D0.R1.S15: Dq Delay estimate: 420
N0.C3.D0.R1.S00: Offset Found: RdPtrOffsetDqs = 007
N2.C0.D1.R1.S10: RdPtrOffsetTxDq: 06
N4.C0.D1.R0.S00: wrcmd2dqsstartlatency: 04
N6.C3.D0.R1.S16: Dq Delay estimate: 441
N0.C3.D0.R1.S01: Offset Found: RdPtrOffsetDqs = 007
N2.C0.D1.R1.S10: RdPtrOffsetTxDqs: 07
N4.C0.D1.R0.S00: RdPtrOffsetTxDq: 06
N6.C3.D0.R1.S17: Dq Delay estimate: 406
N0.C3.D0.R1.S02: Offset Found: RdPtrOffsetDqs = 007
N2.C0.D1.R1.S10: PiTxDqs: 39
N4.C0.D1.R0.S00: RdPtrOffsetTxDqs: 07
ACCM: F0 F0F0F0F0 F0F0F0F0
N0.C3.D0.R1.S03: Offset Found: RdPtrOffsetDqs = 007
N2.C0.D1.R1.S11: wrcmd2dqsstartlatency: 04
N4.C0.D1.R0.S00: PiTxDqs: 59
ACCM: F0 F0F0F0F0 F0F0F0F0
N0.C3.D0.R1.S04: Offset Found: RdPtrOffsetDqs = 006
N2.C0.D1.R1.S11: RdPtrOffsetTxDq: 05
N4.C0.D1.R0.S01: wrcmd2dqsstartlatency: 04
ACCM: F0 F0F0F0F0 F0F0F0F0
N0.C3.D0.R1.S05: Offset Found: RdPtrOffsetDqs = 006
N2.C0.D1.R1.S11: RdPtrOffsetTxDqs: 07
N4.C0.D1.R0.S01: RdPtrOffsetTxDq: 06
ACCM: F0 F0F0F0F0 F0F0F0F0
N0.C3.D0.R1.S06: Offset Found: RdPtrOffsetDqs = 007
N2.C0.D1.R1.S11: PiTxDqs: 25
N4.C0.D1.R0.S01: RdPtrOffsetTxDqs: 07
N6.C3.D0.R1: CheckMCTest: result = 0x3FE00
N0.C3.D0.R1.S07: Offset Found: RdPtrOffsetDqs = 007
N2.C0.D1.R1.S12: wrcmd2dqsstartlatency: 04
N4.C0.D1.R0.S01: PiTxDqs: 46
ACCM: F0 F0F0F0F0 F0F0F0F0
N0.C3.D0.R1.S08: Offset Found: RdPtrOffsetDqs = 006
N2.C0.D1.R1.S12: RdPtrOffsetTxDq: 05
N4.C0.D1.R0.S02: wrcmd2dqsstartlatency: 04
ACCM: F0 F0F0F0F0 F0F0F0F0
N0.C3.D0.R1: Write Training Coarse, upper nibbles
N2.C0.D1.R1.S12: RdPtrOffsetTxDqs: 07
N4.C0.D1.R0.S02: RdPtrOffsetTxDq: 05
ACCM: F0 F0F0F0F0 F0F0F0F0
N0.C3.D0.R1.S09: Dq Delay estimate: 473
N2.C0.D1.R1.S12: PiTxDqs: 11
N4.C0.D1.R0.S02: RdPtrOffsetTxDqs: 07
ACCM: F0 F0F0F0F0 F0F0F0F0
N0.C3.D0.R1.S10: Dq Delay estimate: 457
N2.C0.D1.R1.S13: wrcmd2dqsstartlatency: 04
N4.C0.D1.R0.S02: PiTxDqs: 33
N6.C3.D0.R1: CheckMCTest: result = 0x3FE00
N0.C3.D0.R1.S11: Dq Delay estimate: 448
N2.C0.D1.R1.S13: RdPtrOffsetTxDq: 05
N4.C0.D1.R0.S03: wrcmd2dqsstartlatency: 04
ACCM: F0 F0F0F0F0 F0F0F0F0
N0.C3.D0.R1.S12: Dq Delay estimate: 435
N2.C0.D1.R1.S13: RdPtrOffsetTxDqs: 06
N4.C0.D1.R0.S03: RdPtrOffsetTxDq: 05
ACCM: F0 F0F0F0F0 F0F0F0F0
N0.C3.D0.R1.S13: Dq Delay estimate: 397
N2.C0.D1.R1.S13: PiTxDqs: 37
N4.C0.D1.R0.S03: RdPtrOffsetTxDqs: 07
ACCM: 00 B00000B0 B000B000
N0.C3.D0.R1.S14: Dq Delay estimate: 412
N2.C0.D1.R1.S14: wrcmd2dqsstartlatency: 04
N4.C0.D1.R0.S03: PiTxDqs: 15
ACCM: 00 B00000B0 B000B000
N0.C3.D0.R1.S15: Dq Delay estimate: 423
N2.C0.D1.R1.S14: RdPtrOffsetTxDq: 05
N4.C0.D1.R0.S04: wrcmd2dqsstartlatency: 04
N6.C3.D0.R1: CheckMCTest: result = 0x3FE00
N0.C3.D0.R1.S16: Dq Delay estimate: 442
N2.C0.D1.R1.S14: RdPtrOffsetTxDqs: 06
N4.C0.D1.R0.S04: RdPtrOffsetTxDq: 05
ACCM: F0 F0F0F0F0 F0F0F0F0
N0.C3.D0.R1.S17: Dq Delay estimate: 413
N2.C0.D1.R1.S14: PiTxDqs: 55
N4.C0.D1.R0.S04: RdPtrOffsetTxDqs: 06
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: F0 F0F0F0F0 F0F0F0F0
N2.C0.D1.R1.S15: wrcmd2dqsstartlatency: 04
N4.C0.D1.R0.S04: PiTxDqs: 46
ACCM: 00 F00000F0 F000F000
ACCM: F0 F0F0F0F0 F0F0F0F0
N2.C0.D1.R1.S15: RdPtrOffsetTxDq: 05
N4.C0.D1.R0.S05: wrcmd2dqsstartlatency: 04
ACCM: 00 F00000F0 F000F000
ACCM: F0 F0F0F0F0 F0F0F0F0
N2.C0.D1.R1.S15: RdPtrOffsetTxDqs: 06
N4.C0.D1.R0.S05: RdPtrOffsetTxDq: 05
N6.C3.D0.R1: CheckMCTest: result = 0x3FE00
ACCM: F0 F0F0F0F0 F0F0F0F0
N2.C0.D1.R1.S15: PiTxDqs: 59
N4.C0.D1.R0.S05: RdPtrOffsetTxDqs: 06
N6.C3.D0.R1: CheckMCTest: passed
N0.C3.D0.R1: CheckMCTest: result = 0x3FE00
N2.C0.D1.R1.S16: wrcmd2dqsstartlatency: 04
N4.C0.D1.R0.S05: PiTxDqs: 63
N6.C3.D0.R1: CheckMCTest: passed
ACCM: F0 F0F0F0F0 F0F0F0F0
N2.C0.D1.R1.S16: RdPtrOffsetTxDq: 05
N4.C0.D1.R0.S06: wrcmd2dqsstartlatency: 04
N6.C3.D0.R1.S09: Offset Found: RdPtrOffsetDqs = 007
ACCM: F0 F0F0F0F0 F0F0F0F0
N2.C0.D1.R1.S16: RdPtrOffsetTxDqs: 07
N4.C0.D1.R0.S06: RdPtrOffsetTxDq: 05
N6.C3.D0.R1.S10: Offset Found: RdPtrOffsetDqs = 007
ACCM: F0 F0F0F0F0 F0F0F0F0
N2.C0.D1.R1.S16: PiTxDqs: 11
N4.C0.D1.R0.S06: RdPtrOffsetTxDqs: 07
N6.C3.D0.R1.S11: Offset Found: RdPtrOffsetDqs = 007
ACCM: F0 F0F0F0F0 F0F0F0F0
N2.C0.D1.R1.S17: wrcmd2dqsstartlatency: 04
N4.C0.D1.R0.S06: PiTxDqs: 03
N6.C3.D0.R1.S12: Offset Found: RdPtrOffsetDqs = 007
N0.C3.D0.R1: CheckMCTest: result = 0x3FE00
N2.C0.D1.R1.S17: RdPtrOffsetTxDq: 05
N4.C0.D1.R0.S07: wrcmd2dqsstartlatency: 04
N6.C3.D0.R1.S13: Offset Found: RdPtrOffsetDqs = 006
ACCM: F0 F0F0F0F0 F0F0F0F0
N2.C0.D1.R1.S17: RdPtrOffsetTxDqs: 06
N4.C0.D1.R0.S07: RdPtrOffsetTxDq: 05
N6.C3.D0.R1.S14: Offset Found: RdPtrOffsetDqs = 006
ACCM: F0 F0F0F0F0 F0F0F0F0
N2.C0.D1.R1.S17: PiTxDqs: 47
N4.C0.D1.R0.S07: RdPtrOffsetTxDqs: 07
N6.C3.D0.R1.S15: Offset Found: RdPtrOffsetDqs = 007
ACCM: 00 000000B0 00000000
N2.C0.D1.R1.S00: RdPtrOffsetTxDq: 07
N4.C0.D1.R0.S07: PiTxDqs: 17
N6.C3.D0.R1.S16: Offset Found: RdPtrOffsetDqs = 007
ACCM: 00 000000B0 00000000
N2.C0.D1.R1.S01: RdPtrOffsetTxDq: 07
N4.C0.D1.R0.S08: wrcmd2dqsstartlatency: 04
N6.C3.D0.R1.S17: Offset Found: RdPtrOffsetDqs = 006
N0.C3.D0.R1: CheckMCTest: result = 0x3FE00
N2.C0.D1.R1.S02: RdPtrOffsetTxDq: 06
N4.C0.D1.R0.S08: RdPtrOffsetTxDq: 05
N6.C3.D1.R0: Write Training Coarse, lower nibbles / bytes
ACCM: F0 F0F0F0F0 F0F0F0F0
N2.C0.D1.R1.S03: RdPtrOffsetTxDq: 06
N4.C0.D1.R0.S08: RdPtrOffsetTxDqs: 06
N6.C3.D1.R0.S00: Dq Delay estimate: 351
ACCM: F0 F0F0F0F0 F0F0F0F0
N2.C0.D1.R1.S04: RdPtrOffsetTxDq: 06
N4.C0.D1.R0.S08: PiTxDqs: 55
N6.C3.D1.R0.S01: Dq Delay estimate: 462
ACCM: 00 0000D0F0 00000000
N2.C0.D1.R1.S05: RdPtrOffsetTxDq: 06
N4.C0.D1.R0.S09: wrcmd2dqsstartlatency: 04
N6.C3.D1.R0.S02: Dq Delay estimate: 450
ACCM: 00 0000D0F0 00000000
N2.C0.D1.R1.S06: RdPtrOffsetTxDq: 06
N4.C0.D1.R0.S09: RdPtrOffsetTxDq: 06
N6.C3.D1.R0.S03: Dq Delay estimate: 438
N0.C3.D0.R1: CheckMCTest: result = 0x3FE00
N2.C0.D1.R1.S07: RdPtrOffsetTxDq: 06
N4.C0.D1.R0.S09: RdPtrOffsetTxDqs: 07
N6.C3.D1.R0.S04: Dq Delay estimate: 398
N0.C3.D0.R1: CheckMCTest: passed
N2.C0.D1.R1.S08: RdPtrOffsetTxDq: 06
N4.C0.D1.R0.S09: PiTxDqs: 58
N6.C3.D1.R0.S05: Dq Delay estimate: 412
N0.C3.D0.R1: CheckMCTest: passed
N2.C0.D1.R1.S09: RdPtrOffsetTxDq: 07
N4.C0.D1.R0.S10: wrcmd2dqsstartlatency: 04
N6.C3.D1.R0.S06: Dq Delay estimate: 428
N0.C3.D0.R1.S09: Offset Found: RdPtrOffsetDqs = 007
N2.C0.D1.R1.S10: RdPtrOffsetTxDq: 07
N4.C0.D1.R0.S10: RdPtrOffsetTxDq: 06
N6.C3.D1.R0.S07: Dq Delay estimate: 446
N0.C3.D0.R1.S10: Offset Found: RdPtrOffsetDqs = 007
N2.C0.D1.R1.S11: RdPtrOffsetTxDq: 06
N4.C0.D1.R0.S10: RdPtrOffsetTxDqs: 07
N6.C3.D1.R0.S08: Dq Delay estimate: 416
N0.C3.D0.R1.S11: Offset Found: RdPtrOffsetDqs = 007
N2.C0.D1.R1.S12: RdPtrOffsetTxDq: 06
N4.C0.D1.R0.S10: PiTxDqs: 46
ACCM: 0F 0F0F0F0F 0F0F0F0F
N0.C3.D0.R1.S12: Offset Found: RdPtrOffsetDqs = 007
N2.C0.D1.R1.S13: RdPtrOffsetTxDq: 06
N4.C0.D1.R0.S11: wrcmd2dqsstartlatency: 04
ACCM: 0F 0F0F0F0F 0F0F0F0F
N0.C3.D0.R1.S13: Offset Found: RdPtrOffsetDqs = 006
N2.C0.D1.R1.S14: RdPtrOffsetTxDq: 06
N4.C0.D1.R0.S11: RdPtrOffsetTxDq: 05
ACCM: 0F 0F0F0F0F 0F0F0F09
N0.C3.D0.R1.S14: Offset Found: RdPtrOffsetDqs = 006
N2.C0.D1.R1.S15: RdPtrOffsetTxDq: 06
N4.C0.D1.R0.S11: RdPtrOffsetTxDqs: 07
ACCM: 0F FFFF0F0F FFFF0F09
N0.C3.D0.R1.S15: Offset Found: RdPtrOffsetDqs = 007
N2.C0.D1.R1.S16: RdPtrOffsetTxDq: 06
N4.C0.D1.R0.S11: PiTxDqs: 32
N6.C3.D1.R0: CheckMCTest: result = 0x199FF
N0.C3.D0.R1.S16: Offset Found: RdPtrOffsetDqs = 007
N2.C0.D1.R1.S17: RdPtrOffsetTxDq: 06
N4.C0.D1.R0.S12: wrcmd2dqsstartlatency: 04
ACCM: 0F 0F0F0F0F 0F0F0F0F
N0.C3.D0.R1.S17: Offset Found: RdPtrOffsetDqs = 006
N2.C0.D1.R1.S00: RdPtrOffsetTxDq: 08
N4.C0.D1.R0.S12: RdPtrOffsetTxDq: 05
ACCM: 0F 0F0F0F0F 0F0F0F0F
N0.C3.D1.R0: Write Training Coarse, lower nibbles / bytes
N2.C0.D1.R1.S01: RdPtrOffsetTxDq: 08
N4.C0.D1.R0.S12: RdPtrOffsetTxDqs: 07
ACCM: 0F 0F0F0F0F 0F0F0F0D
N0.C3.D1.R0.S00: Dq Delay estimate: 354
N2.C0.D1.R1.S02: RdPtrOffsetTxDq: 07
N4.C0.D1.R0.S12: PiTxDqs: 16
ACCM: 0F FFFF0F0F FFFF0F0D
N0.C3.D1.R0.S01: Dq Delay estimate: 463
N2.C0.D1.R1.S03: RdPtrOffsetTxDq: 07
N4.C0.D1.R0.S13: wrcmd2dqsstartlatency: 04
N6.C3.D1.R0: CheckMCTest: result = 0x199FF
N0.C3.D1.R0.S02: Dq Delay estimate: 455
N2.C0.D1.R1.S04: RdPtrOffsetTxDq: 07
N4.C0.D1.R0.S13: RdPtrOffsetTxDq: 05
ACCM: 0F 0F0F0F0F 0F0F0F00
N0.C3.D1.R0.S03: Dq Delay estimate: 436
N2.C0.D1.R1.S05: RdPtrOffsetTxDq: 07
N4.C0.D1.R0.S13: RdPtrOffsetTxDqs: 06
ACCM: 0F 0F0F0F0F 0F0F0F00
N0.C3.D1.R0.S04: Dq Delay estimate: 402
N2.C0.D1.R1.S06: RdPtrOffsetTxDq: 07
N4.C0.D1.R0.S13: PiTxDqs: 46
ACCM: 00 0B0B000B 0B000B00
N0.C3.D1.R0.S05: Dq Delay estimate: 416
N2.C0.D1.R1.S07: RdPtrOffsetTxDq: 07
N4.C0.D1.R0.S14: wrcmd2dqsstartlatency: 04
ACCM: 00 FBFB000B FBF00B00
N0.C3.D1.R0.S06: Dq Delay estimate: 430
N2.C0.D1.R1.S08: RdPtrOffsetTxDq: 07
N4.C0.D1.R0.S14: RdPtrOffsetTxDq: 05
N6.C3.D1.R0: CheckMCTest: result = 0x199FE
N0.C3.D1.R0.S07: Dq Delay estimate: 448
N2.C0.D1.R1.S09: RdPtrOffsetTxDq: 08
N4.C0.D1.R0.S14: RdPtrOffsetTxDqs: 06
ACCM: 0F 0F0F0F0F 0F0F0F00
N0.C3.D1.R0.S08: Dq Delay estimate: 418
N2.C0.D1.R1.S10: RdPtrOffsetTxDq: 08
N4.C0.D1.R0.S14: PiTxDqs: 63
ACCM: 0F 0F0F0F0F 0F0F0F00
ACCM: 0F 0F0F0F0F 0F0F0F0F
N2.C0.D1.R1.S11: RdPtrOffsetTxDq: 07
N4.C0.D1.R0.S15: wrcmd2dqsstartlatency: 04
ACCM: 00 0F0F000F 0F0D0F00
ACCM: 0F 0F0F0F0F 0F0F0F0F
N2.C0.D1.R1.S12: RdPtrOffsetTxDq: 07
N4.C0.D1.R0.S15: RdPtrOffsetTxDq: 05
ACCM: 00 FFFF000F FFFD0F00
ACCM: 0F 0F0F0F0F 0F0F0F09
N2.C0.D1.R1.S13: RdPtrOffsetTxDq: 07
N4.C0.D1.R0.S15: RdPtrOffsetTxDqs: 07
N6.C3.D1.R0: CheckMCTest: result = 0x199FE
ACCM: 0F FFFF0F0F FF0F0F09
N2.C0.D1.R1.S14: RdPtrOffsetTxDq: 07
N4.C0.D1.R0.S15: PiTxDqs: 02
N6.C3.D1.R0.S00: Offset Found: RdPtrOffsetDqs = 008
N0.C3.D1.R0: CheckMCTest: result = 0x191FF
N2.C0.D1.R1.S15: RdPtrOffsetTxDq: 07
N4.C0.D1.R0.S16: wrcmd2dqsstartlatency: 04
ACCM: 00 00000000 00000000
ACCM: 0F 0F0F0F0F 0F0F0F0F
N2.C0.D1.R1.S16: RdPtrOffsetTxDq: 07
N4.C0.D1.R0.S16: RdPtrOffsetTxDq: 05
ACCM: 00 00000000 00000000
ACCM: 0F 0F0F0F0F 0F0F0F0F
N2.C0.D1.R1.S17: RdPtrOffsetTxDq: 07
N4.C0.D1.R0.S16: RdPtrOffsetTxDqs: 07
ACCM: 00 00000000 00000000
ACCM: 0F 0F0F0F0F 0F0F0F0D
N2.C0.D1.R1.S00: Total Delay in PI ticks: TxDQ = 980
N4.C0.D1.R0.S16: PiTxDqs: 17
ACCM: 00 F0F00000 F0F00000
ACCM: 0F FFFF0F0F FF0F0F0D
N2.C0.D1.R1.S01: Total Delay in PI ticks: TxDQ = 965
N4.C0.D1.R0.S17: wrcmd2dqsstartlatency: 04
N6.C3.D1.R0: CheckMCTest: result = 0x19800
N0.C3.D1.R0: CheckMCTest: result = 0x191FF
N2.C0.D1.R1.S02: Total Delay in PI ticks: TxDQ = 949
N4.C0.D1.R0.S17: RdPtrOffsetTxDq: 05
ACCM: 00 00000000 00000000
ACCM: 0F 0F0F0F0F 0F0F0F00
N2.C0.D1.R1.S03: Total Delay in PI ticks: TxDQ = 936
N4.C0.D1.R0.S17: RdPtrOffsetTxDqs: 06
ACCM: 00 00000000 00000000
ACCM: 0F 0F0F0F0F 0F0F0F00
N2.C0.D1.R1.S04: Total Delay in PI ticks: TxDQ = 900
N4.C0.D1.R0.S17: PiTxDqs: 55
ACCM: 00 00000000 00000000
ACCM: 0B 0B0B0000 000B0B00
N2.C0.D1.R1.S05: Total Delay in PI ticks: TxDQ = 920
N4.C0.D1.R0.S00: RdPtrOffsetTxDq: 07
ACCM: 00 F0F00000 F0F00000
ACCM: 0B FBFB0000 F00B0B00
N2.C0.D1.R1.S06: Total Delay in PI ticks: TxDQ = 923
N4.C0.D1.R0.S01: RdPtrOffsetTxDq: 07
N6.C3.D1.R0: CheckMCTest: result = 0x19800
N0.C3.D1.R0: CheckMCTest: result = 0x191FE
N2.C0.D1.R1.S07: Total Delay in PI ticks: TxDQ = 938
N4.C0.D1.R0.S02: RdPtrOffsetTxDq: 06
N6.C3.D1.R0.S00: Offset Found: RdPtrOffsetDqs = 008
ACCM: 0F 0F0F0F0F 0F0F0F00
N2.C0.D1.R1.S08: Total Delay in PI ticks: TxDQ = 910
N4.C0.D1.R0.S03: RdPtrOffsetTxDq: 06
N6.C3.D1.R0.S01: Offset Found: RdPtrOffsetDqs = 007
ACCM: 0F 0F0F0F0F 0F0F0F00
N2.C0.D1.R1.S09: Total Delay in PI ticks: TxDQ = 976
N4.C0.D1.R0.S04: RdPtrOffsetTxDq: 06
N6.C3.D1.R0.S02: Offset Found: RdPtrOffsetDqs = 007
ACCM: 0F 0F0B0000 000F0F00
N2.C0.D1.R1.S10: Total Delay in PI ticks: TxDQ = 967
N4.C0.D1.R0.S05: RdPtrOffsetTxDq: 06
N6.C3.D1.R0.S03: Offset Found: RdPtrOffsetDqs = 007
ACCM: 0F FFFB0000 F00F0F00
N2.C0.D1.R1.S11: Total Delay in PI ticks: TxDQ = 951
N4.C0.D1.R0.S06: RdPtrOffsetTxDq: 06
N6.C3.D1.R0.S04: Offset Found: RdPtrOffsetDqs = 006
N0.C3.D1.R0: CheckMCTest: result = 0x191FE
N2.C0.D1.R1.S12: Total Delay in PI ticks: TxDQ = 937
N4.C0.D1.R0.S07: RdPtrOffsetTxDq: 06
N6.C3.D1.R0.S05: Offset Found: RdPtrOffsetDqs = 007
N0.C3.D1.R0.S00: Offset Found: RdPtrOffsetDqs = 008
N2.C0.D1.R1.S13: Total Delay in PI ticks: TxDQ = 901
N4.C0.D1.R0.S08: RdPtrOffsetTxDq: 06
N6.C3.D1.R0.S06: Offset Found: RdPtrOffsetDqs = 007
ACCM: 00 00000000 00000000
N2.C0.D1.R1.S14: Total Delay in PI ticks: TxDQ = 920
N4.C0.D1.R0.S09: RdPtrOffsetTxDq: 07
N6.C3.D1.R0.S07: Offset Found: RdPtrOffsetDqs = 007
ACCM: 00 00000000 00000000
N2.C0.D1.R1.S15: Total Delay in PI ticks: TxDQ = 922
N4.C0.D1.R0.S10: RdPtrOffsetTxDq: 07
N6.C3.D1.R0.S08: Offset Found: RdPtrOffsetDqs = 007
ACCM: 00 00000000 00000000
N2.C0.D1.R1.S16: Total Delay in PI ticks: TxDQ = 937
N4.C0.D1.R0.S11: RdPtrOffsetTxDq: 06
N6.C3.D1.R0: Write Training Coarse, upper nibbles
ACCM: 00 F0F00000 F0000000
N2.C0.D1.R1.S17: Total Delay in PI ticks: TxDQ = 908
N4.C0.D1.R0.S12: RdPtrOffsetTxDq: 06
N6.C3.D1.R0.S09: Dq Delay estimate: 348
N0.C3.D1.R0: CheckMCTest: result = 0x19000
N2.C0: Calculating Optimimum DQ/DQS Values
N4.C0.D1.R0.S13: RdPtrOffsetTxDq: 06
N6.C3.D1.R0.S10: Dq Delay estimate: 461
ACCM: 00 00000000 00000000
N4.C0.D1.R0.S14: RdPtrOffsetTxDq: 06
N6.C3.D1.R0.S11: Dq Delay estimate: 451
ACCM: 00 00000000 00000000
START_DATA_TX_DQ
N4.C0.D1.R0.S15: RdPtrOffsetTxDq: 06
N6.C3.D1.R0.S12: Dq Delay estimate: 436
ACCM: 00 00000000 00000000
N2.C0.S00: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 009, RdPtrOffsetTxDqs = 009
N4.C0.D1.R0.S16: RdPtrOffsetTxDq: 06
N6.C3.D1.R0.S13: Dq Delay estimate: 399
ACCM: 00 F0F00000 F0000000
N2.C0.S00: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 009, RdPtrOffsetTxDqs = 009
N4.C0.D1.R0.S17: RdPtrOffsetTxDq: 06
N6.C3.D1.R0.S14: Dq Delay estimate: 418
N0.C3.D1.R0: CheckMCTest: result = 0x19000
N2.C0.S01: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 009
N4.C0.D1.R0.S00: RdPtrOffsetTxDq: 08
N6.C3.D1.R0.S15: Dq Delay estimate: 429
N0.C3.D1.R0.S00: Offset Found: RdPtrOffsetDqs = 008
N2.C0.S01: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 009
N4.C0.D1.R0.S01: RdPtrOffsetTxDq: 08
N6.C3.D1.R0.S16: Dq Delay estimate: 448
N0.C3.D1.R0.S01: Offset Found: RdPtrOffsetDqs = 007
N2.C0.S02: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 009
N4.C0.D1.R0.S02: RdPtrOffsetTxDq: 07
N6.C3.D1.R0.S17: Dq Delay estimate: 415
N0.C3.D1.R0.S02: Offset Found: RdPtrOffsetDqs = 007
N2.C0.S02: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 009
N4.C0.D1.R0.S03: RdPtrOffsetTxDq: 07
ACCM: F0 F0F0F0F0 F0F0F0F0
N0.C3.D1.R0.S03: Offset Found: RdPtrOffsetDqs = 007
N2.C0.S03: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 008
N4.C0.D1.R0.S04: RdPtrOffsetTxDq: 07
ACCM: F0 F0F0F0F0 F0F0F0F0
N0.C3.D1.R0.S04: Offset Found: RdPtrOffsetDqs = 006
N2.C0.S03: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 008
N4.C0.D1.R0.S05: RdPtrOffsetTxDq: 07
ACCM: F0 F0F0F0F0 F0F0F0D0
N0.C3.D1.R0.S05: Offset Found: RdPtrOffsetDqs = 007
N2.C0.S04: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 007, RdPtrOffsetTxDqs = 008
N4.C0.D1.R0.S06: RdPtrOffsetTxDq: 07
ACCM: F0 F0F0F0F0 F0F0F0D0
N0.C3.D1.R0.S06: Offset Found: RdPtrOffsetDqs = 007
N2.C0.S04: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 007, RdPtrOffsetTxDqs = 008
N4.C0.D1.R0.S07: RdPtrOffsetTxDq: 07
N6.C3.D1.R0: CheckMCTest: result = 0x3FE00
N0.C3.D1.R0.S07: Offset Found: RdPtrOffsetDqs = 007
N2.C0.S05: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 008
N4.C0.D1.R0.S08: RdPtrOffsetTxDq: 07
ACCM: F0 F0F0F0F0 F0F0F0F0
N0.C3.D1.R0.S08: Offset Found: RdPtrOffsetDqs = 007
N2.C0.S05: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 008
N4.C0.D1.R0.S09: RdPtrOffsetTxDq: 08
ACCM: F0 F0F0F0F0 F0F0F0F0
N0.C3.D1.R0: Write Training Coarse, upper nibbles
N2.C0.S06: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 008
N4.C0.D1.R0.S10: RdPtrOffsetTxDq: 08
ACCM: F0 F0F0F0F0 F0F0F0D0
N0.C3.D1.R0.S09: Dq Delay estimate: 352
N2.C0.S06: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 008
N4.C0.D1.R0.S11: RdPtrOffsetTxDq: 07
ACCM: F0 F0F0F0F0 F0F0F0D0
N0.C3.D1.R0.S10: Dq Delay estimate: 465
N2.C0.S07: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 009
N4.C0.D1.R0.S12: RdPtrOffsetTxDq: 07
N6.C3.D1.R0: CheckMCTest: result = 0x3FE00
N0.C3.D1.R0.S11: Dq Delay estimate: 458
N2.C0.S07: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 009
N4.C0.D1.R0.S13: RdPtrOffsetTxDq: 07
ACCM: F0 F0F0F0F0 F0F0F000
N0.C3.D1.R0.S12: Dq Delay estimate: 438
N2.C0.S08: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 008
N4.C0.D1.R0.S14: RdPtrOffsetTxDq: 07
ACCM: F0 F0F0F0F0 F0F0F000
N0.C3.D1.R0.S13: Dq Delay estimate: 404
N2.C0.S08: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 008
N4.C0.D1.R0.S15: RdPtrOffsetTxDq: 07
ACCM: 00 00B000B0 0000B000
N0.C3.D1.R0.S14: Dq Delay estimate: 419
N2.C0.D0.R0.S00: TxDqs: plus1 = 1, minus1 = 0, PI = 48, DB = 0
N4.C0.D1.R0.S16: RdPtrOffsetTxDq: 07
ACCM: 00 00B000B0 0000B000
N0.C3.D1.R0.S15: Dq Delay estimate: 434
N2.C0.D0.R0.S00: TxDq : plus1 = 1, minus1 = 0, PI = 18, DB = 0
N4.C0.D1.R0.S17: RdPtrOffsetTxDq: 07
N6.C3.D1.R0: CheckMCTest: result = 0x3FC00
N0.C3.D1.R0.S16: Dq Delay estimate: 446
N2.C0.D0.R0.S01: TxDqs: plus1 = 1, minus1 = 0, PI = 30, DB = 0
N4.C0.D1.R0.S00: Total Delay in PI ticks: TxDQ = 986
ACCM: F0 F0F0F0F0 F0F0F000
N0.C3.D1.R0.S17: Dq Delay estimate: 416
N2.C0.D0.R0.S01: TxDq : plus1 = 1, minus1 = 0, PI = 61, DB = 1
N4.C0.D1.R0.S01: Total Delay in PI ticks: TxDQ = 969
ACCM: F0 F0F0F0F0 F0F0F000
ACCM: F0 F0F0F0F0 F0F0F0F0
N2.C0.D0.R0.S02: TxDqs: plus1 = 1, minus1 = 0, PI = 18, DB = 0
N4.C0.D1.R0.S02: Total Delay in PI ticks: TxDQ = 958
ACCM: 00 00F000F0 0000F000
ACCM: F0 F0F0F0F0 F0F0F0F0
N2.C0.D0.R0.S02: TxDq : plus1 = 1, minus1 = 0, PI = 48, DB = 0
N4.C0.D1.R0.S03: Total Delay in PI ticks: TxDQ = 939
ACCM: 00 00F000F0 0000F000
ACCM: F0 F0F0F0F0 F0F0F0D0
N2.C0.D0.R0.S03: TxDqs: plus1 = 1, minus1 = 0, PI = 63, DB = 1
N4.C0.D1.R0.S04: Total Delay in PI ticks: TxDQ = 906
N6.C3.D1.R0: CheckMCTest: result = 0x3FC00
ACCM: F0 F0F0F0F0 F0F0F0D0
N2.C0.D0.R0.S03: TxDq : plus1 = 1, minus1 = 0, PI = 31, DB = 0
N4.C0.D1.R0.S05: Total Delay in PI ticks: TxDQ = 923
N6.C3.D1.R0.S09: Offset Found: RdPtrOffsetDqs = 008
N0.C3.D1.R0: CheckMCTest: result = 0x3FE00
N2.C0.D0.R0.S04: TxDqs: plus1 = 1, minus1 = 0, PI = 30, DB = 0
N4.C0.D1.R0.S06: Total Delay in PI ticks: TxDQ = 927
N6.C3.D1.R0: CheckMCTest: passed
ACCM: F0 F0F0F0F0 F0F0F0F0
N2.C0.D0.R0.S04: TxDq : plus1 = 1, minus1 = 0, PI = 62, DB = 1
N4.C0.D1.R0.S07: Total Delay in PI ticks: TxDQ = 943
N6.C3.D1.R0: CheckMCTest: passed
ACCM: F0 F0F0F0F0 F0F0F0F0
N2.C0.D0.R0.S05: TxDqs: plus1 = 1, minus1 = 0, PI = 48, DB = 0
N4.C0.D1.R0.S08: Total Delay in PI ticks: TxDQ = 915
N6.C3.D1.R0.S09: Offset Found: RdPtrOffsetDqs = 008
ACCM: F0 F0F0F0F0 F0F0F0D0
N2.C0.D0.R0.S05: TxDq : plus1 = 1, minus1 = 0, PI = 16, DB = 0
N4.C0.D1.R0.S09: Total Delay in PI ticks: TxDQ = 984
N6.C3.D1.R0.S10: Offset Found: RdPtrOffsetDqs = 007
ACCM: F0 F0F0F0F0 F0F0F0D0
N2.C0.D0.R0.S06: TxDqs: plus1 = 1, minus1 = 0, PI = 53, DB = 1
N4.C0.D1.R0.S10: Total Delay in PI ticks: TxDQ = 971
N6.C3.D1.R0.S11: Offset Found: RdPtrOffsetDqs = 007
N0.C3.D1.R0: CheckMCTest: result = 0x3FE00
N2.C0.D0.R0.S06: TxDq : plus1 = 1, minus1 = 0, PI = 22, DB = 0
N4.C0.D1.R0.S11: Total Delay in PI ticks: TxDQ = 955
N6.C3.D1.R0.S12: Offset Found: RdPtrOffsetDqs = 007
ACCM: F0 F0F0F0F0 F0F0F000
N2.C0.D0.R0.S07: TxDqs: plus1 = 1, minus1 = 0, PI = 03, DB = 1
N4.C0.D1.R0.S12: Total Delay in PI ticks: TxDQ = 942
N6.C3.D1.R0.S13: Offset Found: RdPtrOffsetDqs = 006
ACCM: F0 F0F0F0F0 F0F0F000
N2.C0.D0.R0.S07: TxDq : plus1 = 1, minus1 = 0, PI = 35, DB = 0
N4.C0.D1.R0.S13: Total Delay in PI ticks: TxDQ = 906
N6.C3.D1.R0.S14: Offset Found: RdPtrOffsetDqs = 007
ACCM: 00 B0B000B0 0000B000
N2.C0.D0.R0.S08: TxDqs: plus1 = 1, minus1 = 0, PI = 44, DB = 0
N4.C0.D1.R0.S14: Total Delay in PI ticks: TxDQ = 926
N6.C3.D1.R0.S15: Offset Found: RdPtrOffsetDqs = 007
ACCM: 00 B0B000B0 0000B000
N2.C0.D0.R0.S08: TxDq : plus1 = 1, minus1 = 0, PI = 14, DB = 1
N4.C0.D1.R0.S15: Total Delay in PI ticks: TxDQ = 929
N6.C3.D1.R0.S16: Offset Found: RdPtrOffsetDqs = 007
N0.C3.D1.R0: CheckMCTest: result = 0x3FC00
N2.C0.D0.R0.S09: TxDqs: plus1 = 1, minus1 = 0, PI = 48, DB = 0
N4.C0.D1.R0.S16: Total Delay in PI ticks: TxDQ = 943
N6.C3.D1.R0.S17: Offset Found: RdPtrOffsetDqs = 007
ACCM: F0 F0F0F0F0 F0F0F000
N2.C0.D0.R0.S09: TxDq : plus1 = 1, minus1 = 0, PI = 15, DB = 1
N4.C0.D1.R0.S17: Total Delay in PI ticks: TxDQ = 916
N6.C3.D1.R1: Write Training Coarse, lower nibbles / bytes
ACCM: F0 F0F0F0F0 F0F0F000
N2.C0.D0.R0.S10: TxDqs: plus1 = 1, minus1 = 0, PI = 29, DB = 0
N4.C0.D1.R1.S00: wrcmd2dqsstartlatency: 04
N6.C3.D1.R1.S00: Dq Delay estimate: 476
ACCM: 00 F0F000F0 0000F000
N2.C0.D0.R0.S10: TxDq : plus1 = 1, minus1 = 0, PI = 61, DB = 1
N4.C0.D1.R1.S00: RdPtrOffsetTxDq: 06
N6.C3.D1.R1.S01: Dq Delay estimate: 456
ACCM: 00 F0F000F0 0000F000
N2.C0.D0.R0.S11: TxDqs: plus1 = 1, minus1 = 0, PI = 18, DB = 0
N4.C0.D1.R1.S00: RdPtrOffsetTxDqs: 07
N6.C3.D1.R1.S02: Dq Delay estimate: 446
N0.C3.D1.R0: CheckMCTest: result = 0x3FC00
N2.C0.D0.R0.S11: TxDq : plus1 = 1, minus1 = 0, PI = 50, DB = 1
N4.C0.D1.R1.S00: PiTxDqs: 56
N6.C3.D1.R1.S03: Dq Delay estimate: 434
N0.C3.D1.R0.S09: Offset Found: RdPtrOffsetDqs = 008
N2.C0.D0.R0.S12: TxDqs: plus1 = 0, minus1 = 1, PI = 02, DB = 1
N4.C0.D1.R1.S01: wrcmd2dqsstartlatency: 04
N6.C3.D1.R1.S04: Dq Delay estimate: 394
N0.C3.D1.R0: CheckMCTest: passed
N2.C0.D0.R0.S12: TxDq : plus1 = 1, minus1 = 0, PI = 33, DB = 0
N4.C0.D1.R1.S01: RdPtrOffsetTxDq: 06
N6.C3.D1.R1.S05: Dq Delay estimate: 409
N0.C3.D1.R0: CheckMCTest: passed
N2.C0.D0.R0.S13: TxDqs: plus1 = 1, minus1 = 0, PI = 32, DB = 0
N4.C0.D1.R1.S01: RdPtrOffsetTxDqs: 07
N6.C3.D1.R1.S06: Dq Delay estimate: 422
N0.C3.D1.R0.S09: Offset Found: RdPtrOffsetDqs = 008
N2.C0.D0.R0.S13: TxDq : plus1 = 0, minus1 = 1, PI = 01, DB = 1
N4.C0.D1.R1.S01: PiTxDqs: 41
N6.C3.D1.R1.S07: Dq Delay estimate: 441
N0.C3.D1.R0.S10: Offset Found: RdPtrOffsetDqs = 007
N2.C0.D0.R0.S14: TxDqs: plus1 = 1, minus1 = 0, PI = 49, DB = 1
N4.C0.D1.R1.S02: wrcmd2dqsstartlatency: 04
N6.C3.D1.R1.S08: Dq Delay estimate: 409
N0.C3.D1.R0.S11: Offset Found: RdPtrOffsetDqs = 007
N2.C0.D0.R0.S14: TxDq : plus1 = 1, minus1 = 0, PI = 17, DB = 0
N4.C0.D1.R1.S02: RdPtrOffsetTxDq: 05
ACCM: 0F 0F0F0F0F 0F0F0F0F
N0.C3.D1.R0.S12: Offset Found: RdPtrOffsetDqs = 007
N2.C0.D0.R0.S15: TxDqs: plus1 = 1, minus1 = 0, PI = 53, DB = 1
N4.C0.D1.R1.S02: RdPtrOffsetTxDqs: 07
ACCM: 0F 0F0F0F0F 0F0F0F0F
N0.C3.D1.R0.S13: Offset Found: RdPtrOffsetDqs = 006
N2.C0.D0.R0.S15: TxDq : plus1 = 1, minus1 = 0, PI = 20, DB = 0
N4.C0.D1.R1.S02: PiTxDqs: 30
ACCM: 0F 0F0F0F0F 0F0F0F0F
N0.C3.D1.R0.S14: Offset Found: RdPtrOffsetDqs = 007
N2.C0.D0.R0.S16: TxDqs: plus1 = 1, minus1 = 0, PI = 03, DB = 1
N4.C0.D1.R1.S03: wrcmd2dqsstartlatency: 04
ACCM: 0F 0F0F0F0F 0F0F0F0F
N0.C3.D1.R0.S15: Offset Found: RdPtrOffsetDqs = 007
N2.C0.D0.R0.S16: TxDq : plus1 = 1, minus1 = 0, PI = 35, DB = 0
N4.C0.D1.R1.S03: RdPtrOffsetTxDq: 05
N6.C3.D1.R1: CheckMCTest: result = 0x1FF
N0.C3.D1.R0.S16: Offset Found: RdPtrOffsetDqs = 007
N2.C0.D0.R0.S17: TxDqs: plus1 = 1, minus1 = 0, PI = 44, DB = 0
N4.C0.D1.R1.S03: RdPtrOffsetTxDqs: 07
ACCM: 0F 0F0F0F0F 0F0F0F0F
N0.C3.D1.R0.S17: Offset Found: RdPtrOffsetDqs = 007
N2.C0.D0.R0.S17: TxDq : plus1 = 1, minus1 = 0, PI = 11, DB = 1
N4.C0.D1.R1.S03: PiTxDqs: 13
ACCM: 0F 0F0F0F0F 0F0F0F0F
N0.C3.D1.R1: Write Training Coarse, lower nibbles / bytes
N2.C0.D0.R1.S00: TxDqs: plus1 = 1, minus1 = 0, PI = 48, DB = 0
N4.C0.D1.R1.S04: wrcmd2dqsstartlatency: 04
ACCM: 0F 0F0F0F0F 0F0F0F0F
N0.C3.D1.R1.S00: Dq Delay estimate: 352
N2.C0.D0.R1.S00: TxDq : plus1 = 1, minus1 = 0, PI = 18, DB = 0
N4.C0.D1.R1.S04: RdPtrOffsetTxDq: 05
ACCM: 0F 0F0F0F0F 0F0F0F0F
N0.C3.D1.R1.S01: Dq Delay estimate: 461
N2.C0.D0.R1.S01: TxDqs: plus1 = 1, minus1 = 0, PI = 30, DB = 0
N4.C0.D1.R1.S04: RdPtrOffsetTxDqs: 06
N6.C3.D1.R1: CheckMCTest: result = 0x1FF
N0.C3.D1.R1.S02: Dq Delay estimate: 452
N2.C0.D0.R1.S01: TxDq : plus1 = 1, minus1 = 0, PI = 61, DB = 1
N4.C0.D1.R1.S04: PiTxDqs: 40
ACCM: 0F 0F0F0F0F 0F0F0F0F
N0.C3.D1.R1.S03: Dq Delay estimate: 436
N2.C0.D0.R1.S02: TxDqs: plus1 = 1, minus1 = 0, PI = 18, DB = 0
N4.C0.D1.R1.S05: wrcmd2dqsstartlatency: 04
ACCM: 0F 0F0F0F0F 0F0F0F0F
N0.C3.D1.R1.S04: Dq Delay estimate: 400
N2.C0.D0.R1.S02: TxDq : plus1 = 1, minus1 = 0, PI = 48, DB = 0
N4.C0.D1.R1.S05: RdPtrOffsetTxDq: 05
ACCM: 00 00000000 0B000000
N0.C3.D1.R1.S05: Dq Delay estimate: 413
N2.C0.D0.R1.S03: TxDqs: plus1 = 1, minus1 = 0, PI = 63, DB = 1
N4.C0.D1.R1.S05: RdPtrOffsetTxDqs: 06
ACCM: 00 00000000 0B000000
N0.C3.D1.R1.S06: Dq Delay estimate: 428
N2.C0.D0.R1.S03: TxDq : plus1 = 1, minus1 = 0, PI = 31, DB = 0
N4.C0.D1.R1.S05: PiTxDqs: 62
N6.C3.D1.R1: CheckMCTest: result = 0x1FF
N0.C3.D1.R1.S07: Dq Delay estimate: 447
N2.C0.D0.R1.S04: TxDqs: plus1 = 1, minus1 = 0, PI = 30, DB = 0
N4.C0.D1.R1.S06: wrcmd2dqsstartlatency: 04
ACCM: 0F 0F0F0F0F 0F0F0F0F
N0.C3.D1.R1.S08: Dq Delay estimate: 416
N2.C0.D0.R1.S04: TxDq : plus1 = 1, minus1 = 0, PI = 62, DB = 1
N4.C0.D1.R1.S06: RdPtrOffsetTxDq: 05
ACCM: 0F 0F0F0F0F 0F0F0F0F
ACCM: 0F 0F0F0F0F 0F0F0F0F
N2.C0.D0.R1.S05: TxDqs: plus1 = 1, minus1 = 0, PI = 48, DB = 0
N4.C0.D1.R1.S06: RdPtrOffsetTxDqs: 06
ACCM: 00 00000000 0F000000
ACCM: 0F 0F0F0F0F 0F0F0F0F
N2.C0.D0.R1.S05: TxDq : plus1 = 1, minus1 = 0, PI = 16, DB = 0
N4.C0.D1.R1.S06: PiTxDqs: 63
ACCM: 00 00000000 0F000000
ACCM: 0F 0F0F0F0F 0F0F0F09
N2.C0.D0.R1.S06: TxDqs: plus1 = 1, minus1 = 0, PI = 53, DB = 1
N4.C0.D1.R1.S07: wrcmd2dqsstartlatency: 04
N6.C3.D1.R1: CheckMCTest: result = 0x1FF
ACCM: 0F 0F0F0F0F 0F0F0F09
N2.C0.D0.R1.S06: TxDq : plus1 = 1, minus1 = 0, PI = 22, DB = 0
N4.C0.D1.R1.S07: RdPtrOffsetTxDq: 05
N6.C3.D1.R1: CheckMCTest: passed
N0.C3.D1.R1: CheckMCTest: result = 0x1FF
N2.C0.D0.R1.S07: TxDqs: plus1 = 1, minus1 = 0, PI = 03, DB = 1
N4.C0.D1.R1.S07: RdPtrOffsetTxDqs: 07
N6.C3.D1.R1: CheckMCTest: passed
ACCM: 0F 0F0F0F0F 0F0F0F0F
N2.C0.D0.R1.S07: TxDq : plus1 = 1, minus1 = 0, PI = 35, DB = 0
N4.C0.D1.R1.S07: PiTxDqs: 16
N6.C3.D1.R1.S00: Offset Found: RdPtrOffsetDqs = 007
ACCM: 0F 0F0F0F0F 0F0F0F0F
N2.C0.D0.R1.S08: TxDqs: plus1 = 1, minus1 = 0, PI = 44, DB = 0
N4.C0.D1.R1.S08: wrcmd2dqsstartlatency: 04
N6.C3.D1.R1.S01: Offset Found: RdPtrOffsetDqs = 007
ACCM: 0F 0F0F0F0F 0F0F0F0D
N2.C0.D0.R1.S08: TxDq : plus1 = 1, minus1 = 0, PI = 14, DB = 1
N4.C0.D1.R1.S08: RdPtrOffsetTxDq: 05
N6.C3.D1.R1.S02: Offset Found: RdPtrOffsetDqs = 007
ACCM: 0F 0F0F0F0F 0F0F0F0D
N2.C0.D0.R1.S09: TxDqs: plus1 = 1, minus1 = 0, PI = 48, DB = 0
N4.C0.D1.R1.S08: RdPtrOffsetTxDqs: 06
N6.C3.D1.R1.S03: Offset Found: RdPtrOffsetDqs = 007
N0.C3.D1.R1: CheckMCTest: result = 0x1FF
N2.C0.D0.R1.S09: TxDq : plus1 = 1, minus1 = 0, PI = 15, DB = 1
N4.C0.D1.R1.S08: PiTxDqs: 49
N6.C3.D1.R1.S04: Offset Found: RdPtrOffsetDqs = 006
ACCM: 0F 0F0F0F0F 0F0F0F00
N2.C0.D0.R1.S10: TxDqs: plus1 = 1, minus1 = 0, PI = 29, DB = 0
N4.C0.D1.R1.S09: wrcmd2dqsstartlatency: 04
N6.C3.D1.R1.S05: Offset Found: RdPtrOffsetDqs = 006
ACCM: 0F 0F0F0F0F 0F0F0F00
N2.C0.D0.R1.S10: TxDq : plus1 = 1, minus1 = 0, PI = 61, DB = 1
N4.C0.D1.R1.S09: RdPtrOffsetTxDq: 06
N6.C3.D1.R1.S06: Offset Found: RdPtrOffsetDqs = 007
ACCM: 00 0B000B0B 0B000B00
N2.C0.D0.R1.S11: TxDqs: plus1 = 1, minus1 = 0, PI = 18, DB = 0
N4.C0.D1.R1.S09: RdPtrOffsetTxDqs: 07
N6.C3.D1.R1.S07: Offset Found: RdPtrOffsetDqs = 007
ACCM: 00 0B000B0B 0B000B00
N2.C0.D0.R1.S11: TxDq : plus1 = 1, minus1 = 0, PI = 50, DB = 1
N4.C0.D1.R1.S09: PiTxDqs: 57
N6.C3.D1.R1.S08: Offset Found: RdPtrOffsetDqs = 006
N0.C3.D1.R1: CheckMCTest: result = 0x1FE
N2.C0.D0.R1.S12: TxDqs: plus1 = 0, minus1 = 1, PI = 02, DB = 1
N4.C0.D1.R1.S10: wrcmd2dqsstartlatency: 04
N6.C3.D1.R1: Write Training Coarse, upper nibbles
ACCM: 0F 0F0F0F0F 0F0F0F00
N2.C0.D0.R1.S12: TxDq : plus1 = 1, minus1 = 0, PI = 33, DB = 0
N4.C0.D1.R1.S10: RdPtrOffsetTxDq: 06
N6.C3.D1.R1.S09: Dq Delay estimate: 471
ACCM: 0F 0F0F0F0F 0F0F0F00
N2.C0.D0.R1.S13: TxDqs: plus1 = 1, minus1 = 0, PI = 32, DB = 0
N4.C0.D1.R1.S10: RdPtrOffsetTxDqs: 07
N6.C3.D1.R1.S10: Dq Delay estimate: 456
ACCM: 00 0F000F0F 0F000F00
N2.C0.D0.R1.S13: TxDq : plus1 = 0, minus1 = 1, PI = 01, DB = 1
N4.C0.D1.R1.S10: PiTxDqs: 43
N6.C3.D1.R1.S11: Dq Delay estimate: 448
ACCM: 00 0F000F0F 0F000F00
N2.C0.D0.R1.S14: TxDqs: plus1 = 1, minus1 = 0, PI = 49, DB = 1
N4.C0.D1.R1.S11: wrcmd2dqsstartlatency: 04
N6.C3.D1.R1.S12: Dq Delay estimate: 432
N0.C3.D1.R1: CheckMCTest: result = 0x1FE
N2.C0.D0.R1.S14: TxDq : plus1 = 1, minus1 = 0, PI = 17, DB = 0
N4.C0.D1.R1.S11: RdPtrOffsetTxDq: 05
N6.C3.D1.R1.S13: Dq Delay estimate: 395
N0.C3.D1.R1.S00: Offset Found: RdPtrOffsetDqs = 008
N2.C0.D0.R1.S15: TxDqs: plus1 = 1, minus1 = 0, PI = 53, DB = 1
N4.C0.D1.R1.S11: RdPtrOffsetTxDqs: 07
N6.C3.D1.R1.S14: Dq Delay estimate: 414
N0.C3.D1.R1: CheckMCTest: passed
N2.C0.D0.R1.S15: TxDq : plus1 = 1, minus1 = 0, PI = 20, DB = 0
N4.C0.D1.R1.S11: PiTxDqs: 31
N6.C3.D1.R1.S15: Dq Delay estimate: 423
N0.C3.D1.R1: CheckMCTest: passed
N2.C0.D0.R1.S16: TxDqs: plus1 = 1, minus1 = 0, PI = 03, DB = 1
N4.C0.D1.R1.S12: wrcmd2dqsstartlatency: 04
N6.C3.D1.R1.S16: Dq Delay estimate: 444
N0.C3.D1.R1.S00: Offset Found: RdPtrOffsetDqs = 008
N2.C0.D0.R1.S16: TxDq : plus1 = 1, minus1 = 0, PI = 35, DB = 0
N4.C0.D1.R1.S12: RdPtrOffsetTxDq: 05
N6.C3.D1.R1.S17: Dq Delay estimate: 408
N0.C3.D1.R1.S01: Offset Found: RdPtrOffsetDqs = 007
N2.C0.D0.R1.S17: TxDqs: plus1 = 1, minus1 = 0, PI = 44, DB = 0
N4.C0.D1.R1.S12: RdPtrOffsetTxDqs: 07
ACCM: F0 F0F0F0F0 F0F0F0F0
N0.C3.D1.R1.S02: Offset Found: RdPtrOffsetDqs = 007
N2.C0.D0.R1.S17: TxDq : plus1 = 1, minus1 = 0, PI = 11, DB = 1
N4.C0.D1.R1.S12: PiTxDqs: 16
ACCM: F0 F0F0F0F0 F0F0F0F0
N0.C3.D1.R1.S03: Offset Found: RdPtrOffsetDqs = 007
N2.C0.D1.R0.S00: TxDqs: plus1 = 1, minus1 = 0, PI = 52, DB = 1
N4.C0.D1.R1.S13: wrcmd2dqsstartlatency: 04
ACCM: F0 F0F0F0F0 F0F0F0F0
N0.C3.D1.R1.S04: Offset Found: RdPtrOffsetDqs = 006
N2.C0.D1.R0.S00: TxDq : plus1 = 1, minus1 = 0, PI = 22, DB = 0
N4.C0.D1.R1.S13: RdPtrOffsetTxDq: 05
ACCM: F0 F0F0F0F0 F0F0F0F0
N0.C3.D1.R1.S05: Offset Found: RdPtrOffsetDqs = 007
N2.C0.D1.R0.S01: TxDqs: plus1 = 1, minus1 = 0, PI = 39, DB = 0
N4.C0.D1.R1.S13: RdPtrOffsetTxDqs: 06
N6.C3.D1.R1: CheckMCTest: result = 0x3FE00
N0.C3.D1.R1.S06: Offset Found: RdPtrOffsetDqs = 007
N2.C0.D1.R0.S01: TxDq : plus1 = 0, minus1 = 1, PI = 07, DB = 1
N4.C0.D1.R1.S13: PiTxDqs: 44
ACCM: F0 F0F0F0F0 F0F0F0F0
N0.C3.D1.R1.S07: Offset Found: RdPtrOffsetDqs = 007
N2.C0.D1.R0.S02: TxDqs: plus1 = 1, minus1 = 0, PI = 25, DB = 0
N4.C0.D1.R1.S14: wrcmd2dqsstartlatency: 04
ACCM: F0 F0F0F0F0 F0F0F0F0
N0.C3.D1.R1.S08: Offset Found: RdPtrOffsetDqs = 007
N2.C0.D1.R0.S02: TxDq : plus1 = 1, minus1 = 0, PI = 55, DB = 1
N4.C0.D1.R1.S14: RdPtrOffsetTxDq: 05
ACCM: F0 F0F0F0F0 F0F0F0F0
N0.C3.D1.R1: Write Training Coarse, upper nibbles
N2.C0.D1.R0.S03: TxDqs: plus1 = 0, minus1 = 1, PI = 08, DB = 1
N4.C0.D1.R1.S14: RdPtrOffsetTxDqs: 06
ACCM: F0 F0F0F0F0 F0F0F0F0
N0.C3.D1.R1.S09: Dq Delay estimate: 349
N2.C0.D1.R0.S03: TxDq : plus1 = 1, minus1 = 0, PI = 40, DB = 0
N4.C0.D1.R1.S14: PiTxDqs: 59
N6.C3.D1.R1: CheckMCTest: result = 0x3FE00
N0.C3.D1.R1.S10: Dq Delay estimate: 462
N2.C0.D1.R0.S04: TxDqs: plus1 = 1, minus1 = 0, PI = 38, DB = 0
N4.C0.D1.R1.S15: wrcmd2dqsstartlatency: 04
ACCM: F0 F0F0F0F0 F0F0F0F0
N0.C3.D1.R1.S11: Dq Delay estimate: 453
N2.C0.D1.R0.S04: TxDq : plus1 = 0, minus1 = 1, PI = 06, DB = 1
N4.C0.D1.R1.S15: RdPtrOffsetTxDq: 05
ACCM: F0 F0F0F0F0 F0F0F0F0
N0.C3.D1.R1.S12: Dq Delay estimate: 439
N2.C0.D1.R0.S05: TxDqs: plus1 = 1, minus1 = 0, PI = 57, DB = 1
N4.C0.D1.R1.S15: RdPtrOffsetTxDqs: 06
ACCM: 00 B00000B0 B00000B0
N0.C3.D1.R1.S13: Dq Delay estimate: 403
N2.C0.D1.R0.S05: TxDq : plus1 = 1, minus1 = 0, PI = 25, DB = 0
N4.C0.D1.R1.S15: PiTxDqs: 63
ACCM: 00 B00000B0 B00000B0
N0.C3.D1.R1.S14: Dq Delay estimate: 417
N2.C0.D1.R0.S06: TxDqs: plus1 = 1, minus1 = 0, PI = 60, DB = 1
N4.C0.D1.R1.S16: wrcmd2dqsstartlatency: 04
N6.C3.D1.R1: CheckMCTest: result = 0x3FE00
N0.C3.D1.R1.S15: Dq Delay estimate: 429
N2.C0.D1.R0.S06: TxDq : plus1 = 1, minus1 = 0, PI = 29, DB = 0
N4.C0.D1.R1.S16: RdPtrOffsetTxDq: 05
ACCM: F0 F0F0F0F0 F0F0F0F0
N0.C3.D1.R1.S16: Dq Delay estimate: 445
N2.C0.D1.R0.S07: TxDqs: plus1 = 1, minus1 = 0, PI = 13, DB = 1
N4.C0.D1.R1.S16: RdPtrOffsetTxDqs: 07
ACCM: F0 F0F0F0F0 F0F0F0F0
N0.C3.D1.R1.S17: Dq Delay estimate: 414
N2.C0.D1.R0.S07: TxDq : plus1 = 1, minus1 = 0, PI = 44, DB = 0
N4.C0.D1.R1.S16: PiTxDqs: 15
ACCM: 00 F000D0F0 B00000F0
ACCM: F0 F0F0F0F0 F0F0F0F0
N2.C0.D1.R0.S08: TxDqs: plus1 = 1, minus1 = 0, PI = 48, DB = 0
N4.C0.D1.R1.S17: wrcmd2dqsstartlatency: 04
ACCM: 00 F000D0F0 B00000F0
ACCM: F0 F0F0F0F0 F0F0F0F0
N2.C0.D1.R0.S08: TxDq : plus1 = 1, minus1 = 0, PI = 16, DB = 0
N4.C0.D1.R1.S17: RdPtrOffsetTxDq: 05
N6.C3.D1.R1: CheckMCTest: result = 0x3FE00
ACCM: F0 F0F0F0F0 F0F0F000
N2.C0.D1.R0.S09: TxDqs: plus1 = 1, minus1 = 0, PI = 53, DB = 1
N4.C0.D1.R1.S17: RdPtrOffsetTxDqs: 06
N6.C3.D1.R1: CheckMCTest: passed
ACCM: F0 F0F0F0F0 F0F0F000
N2.C0.D1.R0.S09: TxDq : plus1 = 1, minus1 = 0, PI = 20, DB = 0
N4.C0.D1.R1.S17: PiTxDqs: 49
N6.C3.D1.R1: CheckMCTest: passed
N0.C3.D1.R1: CheckMCTest: result = 0x3FE00
N2.C0.D1.R0.S10: TxDqs: plus1 = 1, minus1 = 0, PI = 39, DB = 0
N4.C0.D1.R1.S00: RdPtrOffsetTxDq: 07
N6.C3.D1.R1.S09: Offset Found: RdPtrOffsetDqs = 007
ACCM: F0 F0F0F0F0 F0F0F0F0
N2.C0.D1.R0.S10: TxDq : plus1 = 0, minus1 = 1, PI = 07, DB = 1
N4.C0.D1.R1.S01: RdPtrOffsetTxDq: 07
N6.C3.D1.R1.S10: Offset Found: RdPtrOffsetDqs = 007
ACCM: F0 F0F0F0F0 F0F0F0F0
N2.C0.D1.R0.S11: TxDqs: plus1 = 1, minus1 = 0, PI = 27, DB = 0
N4.C0.D1.R1.S02: RdPtrOffsetTxDq: 06
N6.C3.D1.R1.S11: Offset Found: RdPtrOffsetDqs = 007
ACCM: F0 F0F0F0F0 F0F0F000
N2.C0.D1.R0.S11: TxDq : plus1 = 1, minus1 = 0, PI = 57, DB = 1
N4.C0.D1.R1.S03: RdPtrOffsetTxDq: 06
N6.C3.D1.R1.S12: Offset Found: RdPtrOffsetDqs = 007
ACCM: F0 F0F0F0F0 F0F0F000
N2.C0.D1.R0.S12: TxDqs: plus1 = 0, minus1 = 1, PI = 12, DB = 1
N4.C0.D1.R1.S04: RdPtrOffsetTxDq: 06
N6.C3.D1.R1.S13: Offset Found: RdPtrOffsetDqs = 006
N0.C3.D1.R1: CheckMCTest: result = 0x3FE00
N2.C0.D1.R0.S12: TxDq : plus1 = 1, minus1 = 0, PI = 41, DB = 0
N4.C0.D1.R1.S05: RdPtrOffsetTxDq: 06
N6.C3.D1.R1.S14: Offset Found: RdPtrOffsetDqs = 006
ACCM: F0 F0F0F0F0 F0F0F000
N2.C0.D1.R0.S13: TxDqs: plus1 = 1, minus1 = 0, PI = 39, DB = 0
N4.C0.D1.R1.S06: RdPtrOffsetTxDq: 06
N6.C3.D1.R1.S15: Offset Found: RdPtrOffsetDqs = 007
ACCM: F0 F0F0F0F0 F0F0F000
N2.C0.D1.R0.S13: TxDq : plus1 = 0, minus1 = 1, PI = 07, DB = 1
N4.C0.D1.R1.S07: RdPtrOffsetTxDq: 06
N6.C3.D1.R1.S16: Offset Found: RdPtrOffsetDqs = 007
ACCM: 00 000000B0 B000B000
N2.C0.D1.R0.S14: TxDqs: plus1 = 1, minus1 = 0, PI = 58, DB = 1
N4.C0.D1.R1.S08: RdPtrOffsetTxDq: 06
N6.C3.D1.R1.S17: Offset Found: RdPtrOffsetDqs = 006
ACCM: 00 000000B0 B000B000
N2.C0.D1.R0.S14: TxDq : plus1 = 1, minus1 = 0, PI = 26, DB = 0
N4.C0.D1.R1.S09: RdPtrOffsetTxDq: 07
N6.C3: Calculating Optimimum DQS Values
N0.C3.D1.R1: CheckMCTest: result = 0x3FC00
N2.C0.D1.R0.S15: TxDqs: plus1 = 1, minus1 = 0, PI = 60, DB = 1
N4.C0.D1.R1.S10: RdPtrOffsetTxDq: 07
N6.C3.D0.R0.S00: Total Delay in PI ticks: TxDQS = 1018, TxDQ = 987
ACCM: F0 F0F0F0F0 F0F0F000
N2.C0.D1.R0.S15: TxDq : plus1 = 1, minus1 = 0, PI = 27, DB = 0
N4.C0.D1.R1.S11: RdPtrOffsetTxDq: 06
N6.C3.D0.R0.S01: Total Delay in PI ticks: TxDQS = 1003, TxDQ = 970
ACCM: F0 F0F0F0F0 F0F0F000
N2.C0.D1.R0.S16: TxDqs: plus1 = 1, minus1 = 0, PI = 12, DB = 1
N4.C0.D1.R1.S12: RdPtrOffsetTxDq: 06
N6.C3.D0.R0.S02: Total Delay in PI ticks: TxDQS = 996, TxDQ = 963
ACCM: 00 0000D0F0 F000F000
N2.C0.D1.R0.S16: TxDq : plus1 = 1, minus1 = 0, PI = 43, DB = 0
N4.C0.D1.R1.S13: RdPtrOffsetTxDq: 06
N6.C3.D0.R0.S03: Total Delay in PI ticks: TxDQS = 979, TxDQ = 946
ACCM: 00 0000D0F0 F000F000
N2.C0.D1.R0.S17: TxDqs: plus1 = 1, minus1 = 0, PI = 48, DB = 0
N4.C0.D1.R1.S14: RdPtrOffsetTxDq: 06
N6.C3.D0.R0.S04: Total Delay in PI ticks: TxDQS = 942, TxDQ = 906
N0.C3.D1.R1: CheckMCTest: result = 0x3FC00
N2.C0.D1.R0.S17: TxDq : plus1 = 1, minus1 = 0, PI = 14, DB = 1
N4.C0.D1.R1.S15: RdPtrOffsetTxDq: 06
N6.C3.D0.R0.S05: Total Delay in PI ticks: TxDQS = 955, TxDQ = 921
N0.C3.D1.R1.S09: Offset Found: RdPtrOffsetDqs = 008
N2.C0.D1.R1.S00: TxDqs: plus1 = 1, minus1 = 0, PI = 52, DB = 1
N4.C0.D1.R1.S16: RdPtrOffsetTxDq: 06
N6.C3.D0.R0.S06: Total Delay in PI ticks: TxDQS = 972, TxDQ = 938
N0.C3.D1.R1: CheckMCTest: passed
N2.C0.D1.R1.S00: TxDq : plus1 = 1, minus1 = 0, PI = 22, DB = 0
N4.C0.D1.R1.S17: RdPtrOffsetTxDq: 06
N6.C3.D0.R0.S07: Total Delay in PI ticks: TxDQS = 987, TxDQ = 952
N0.C3.D1.R1: CheckMCTest: passed
N2.C0.D1.R1.S01: TxDqs: plus1 = 1, minus1 = 0, PI = 39, DB = 0
N4.C0.D1.R1.S00: RdPtrOffsetTxDq: 08
N6.C3.D0.R0.S08: Total Delay in PI ticks: TxDQS = 961, TxDQ = 928
N0.C3.D1.R1.S09: Offset Found: RdPtrOffsetDqs = 008
N2.C0.D1.R1.S01: TxDq : plus1 = 0, minus1 = 1, PI = 07, DB = 1
N4.C0.D1.R1.S01: RdPtrOffsetTxDq: 08
N6.C3.D0.R0.S09: Total Delay in PI ticks: TxDQS = 1019, TxDQ = 985
N0.C3.D1.R1.S10: Offset Found: RdPtrOffsetDqs = 007
N2.C0.D1.R1.S02: TxDqs: plus1 = 1, minus1 = 0, PI = 25, DB = 0
N4.C0.D1.R1.S02: RdPtrOffsetTxDq: 07
N6.C3.D0.R0.S10: Total Delay in PI ticks: TxDQS = 1003, TxDQ = 972
N0.C3.D1.R1.S11: Offset Found: RdPtrOffsetDqs = 007
N2.C0.D1.R1.S02: TxDq : plus1 = 1, minus1 = 0, PI = 55, DB = 1
N4.C0.D1.R1.S03: RdPtrOffsetTxDq: 07
N6.C3.D0.R0.S11: Total Delay in PI ticks: TxDQS = 994, TxDQ = 961
N0.C3.D1.R1.S12: Offset Found: RdPtrOffsetDqs = 007
N2.C0.D1.R1.S03: TxDqs: plus1 = 0, minus1 = 1, PI = 08, DB = 1
N4.C0.D1.R1.S04: RdPtrOffsetTxDq: 07
N6.C3.D0.R0.S12: Total Delay in PI ticks: TxDQS = 977, TxDQ = 943
N0.C3.D1.R1.S13: Offset Found: RdPtrOffsetDqs = 006
N2.C0.D1.R1.S03: TxDq : plus1 = 1, minus1 = 0, PI = 40, DB = 0
N4.C0.D1.R1.S05: RdPtrOffsetTxDq: 07
N6.C3.D0.R0.S13: Total Delay in PI ticks: TxDQS = 942, TxDQ = 908
N0.C3.D1.R1.S14: Offset Found: RdPtrOffsetDqs = 007
N2.C0.D1.R1.S04: TxDqs: plus1 = 1, minus1 = 0, PI = 38, DB = 0
N4.C0.D1.R1.S06: RdPtrOffsetTxDq: 07
N6.C3.D0.R0.S14: Total Delay in PI ticks: TxDQS = 956, TxDQ = 926
N0.C3.D1.R1.S15: Offset Found: RdPtrOffsetDqs = 007
N2.C0.D1.R1.S04: TxDq : plus1 = 0, minus1 = 1, PI = 06, DB = 1
N4.C0.D1.R1.S07: RdPtrOffsetTxDq: 07
N6.C3.D0.R0.S15: Total Delay in PI ticks: TxDQS = 970, TxDQ = 939
N0.C3.D1.R1.S16: Offset Found: RdPtrOffsetDqs = 007
N2.C0.D1.R1.S05: TxDqs: plus1 = 1, minus1 = 0, PI = 57, DB = 1
N4.C0.D1.R1.S08: RdPtrOffsetTxDq: 07
N6.C3.D0.R0.S16: Total Delay in PI ticks: TxDQS = 988, TxDQ = 955
N0.C3.D1.R1.S17: Offset Found: RdPtrOffsetDqs = 007
N2.C0.D1.R1.S05: TxDq : plus1 = 1, minus1 = 0, PI = 25, DB = 0
N4.C0.D1.R1.S09: RdPtrOffsetTxDq: 08
N6.C3.D0.R0.S17: Total Delay in PI ticks: TxDQS = 959, TxDQ = 926
N0.C3: Calculating Optimimum DQS Values
N2.C0.D1.R1.S06: TxDqs: plus1 = 1, minus1 = 0, PI = 60, DB = 1
N4.C0.D1.R1.S10: RdPtrOffsetTxDq: 08
N6.C3.D0.R1.S00: Total Delay in PI ticks: TxDQS = 1011, TxDQ = 980
N0.C3.D0.R0.S00: Total Delay in PI ticks: TxDQS = 1028, TxDQ = 994
N2.C0.D1.R1.S06: TxDq : plus1 = 1, minus1 = 0, PI = 29, DB = 0
N4.C0.D1.R1.S11: RdPtrOffsetTxDq: 07
N6.C3.D0.R1.S01: Total Delay in PI ticks: TxDQS = 997, TxDQ = 964
N0.C3.D0.R0.S01: Total Delay in PI ticks: TxDQS = 1010, TxDQ = 976
N2.C0.D1.R1.S07: TxDqs: plus1 = 1, minus1 = 0, PI = 13, DB = 1
N4.C0.D1.R1.S12: RdPtrOffsetTxDq: 07
N6.C3.D0.R1.S02: Total Delay in PI ticks: TxDQS = 987, TxDQ = 954
N0.C3.D0.R0.S02: Total Delay in PI ticks: TxDQS = 999, TxDQ = 965
N2.C0.D1.R1.S07: TxDq : plus1 = 1, minus1 = 0, PI = 44, DB = 0
N4.C0.D1.R1.S13: RdPtrOffsetTxDq: 07
N6.C3.D0.R1.S03: Total Delay in PI ticks: TxDQS = 971, TxDQ = 938
N0.C3.D0.R0.S03: Total Delay in PI ticks: TxDQS = 980, TxDQ = 946
N2.C0.D1.R1.S08: TxDqs: plus1 = 1, minus1 = 0, PI = 48, DB = 0
N4.C0.D1.R1.S14: RdPtrOffsetTxDq: 07
N6.C3.D0.R1.S04: Total Delay in PI ticks: TxDQS = 935, TxDQ = 899
N0.C3.D0.R0.S04: Total Delay in PI ticks: TxDQS = 948, TxDQ = 913
N2.C0.D1.R1.S08: TxDq : plus1 = 1, minus1 = 0, PI = 16, DB = 0
N4.C0.D1.R1.S15: RdPtrOffsetTxDq: 07
N6.C3.D0.R1.S05: Total Delay in PI ticks: TxDQS = 950, TxDQ = 916
N0.C3.D0.R0.S05: Total Delay in PI ticks: TxDQS = 962, TxDQ = 928
N2.C0.D1.R1.S09: TxDqs: plus1 = 1, minus1 = 0, PI = 53, DB = 1
N4.C0.D1.R1.S16: RdPtrOffsetTxDq: 07
N6.C3.D0.R1.S06: Total Delay in PI ticks: TxDQS = 962, TxDQ = 929
N0.C3.D0.R0.S06: Total Delay in PI ticks: TxDQS = 977, TxDQ = 942
N2.C0.D1.R1.S09: TxDq : plus1 = 1, minus1 = 0, PI = 20, DB = 0
N4.C0.D1.R1.S17: RdPtrOffsetTxDq: 07
N6.C3.D0.R1.S07: Total Delay in PI ticks: TxDQS = 981, TxDQ = 947
N0.C3.D0.R0.S07: Total Delay in PI ticks: TxDQS = 993, TxDQ = 960
N2.C0.D1.R1.S10: TxDqs: plus1 = 1, minus1 = 0, PI = 39, DB = 0
N4.C0.D1.R1.S00: Total Delay in PI ticks: TxDQ = 983
N6.C3.D0.R1.S08: Total Delay in PI ticks: TxDQS = 952, TxDQ = 919
N0.C3.D0.R0.S08: Total Delay in PI ticks: TxDQS = 965, TxDQ = 932
N2.C0.D1.R1.S10: TxDq : plus1 = 0, minus1 = 1, PI = 07, DB = 1
N4.C0.D1.R1.S01: Total Delay in PI ticks: TxDQ = 967
N6.C3.D0.R1.S09: Total Delay in PI ticks: TxDQS = 1011, TxDQ = 977
N0.C3.D0.R0.S09: Total Delay in PI ticks: TxDQS = 1028, TxDQ = 992
N2.C0.D1.R1.S11: TxDqs: plus1 = 1, minus1 = 0, PI = 27, DB = 0
N4.C0.D1.R1.S02: Total Delay in PI ticks: TxDQ = 953
N6.C3.D0.R1.S10: Total Delay in PI ticks: TxDQS = 996, TxDQ = 963
N0.C3.D0.R0.S10: Total Delay in PI ticks: TxDQS = 1010, TxDQ = 977
N2.C0.D1.R1.S11: TxDq : plus1 = 1, minus1 = 0, PI = 57, DB = 1
N4.C0.D1.R1.S03: Total Delay in PI ticks: TxDQ = 935
N6.C3.D0.R1.S11: Total Delay in PI ticks: TxDQS = 985, TxDQ = 952
N0.C3.D0.R0.S11: Total Delay in PI ticks: TxDQS = 1000, TxDQ = 968
N2.C0.D1.R1.S12: TxDqs: plus1 = 0, minus1 = 1, PI = 12, DB = 1
N4.C0.D1.R1.S04: Total Delay in PI ticks: TxDQ = 902
N6.C3.D0.R1.S12: Total Delay in PI ticks: TxDQS = 972, TxDQ = 937
N0.C3.D0.R0.S12: Total Delay in PI ticks: TxDQS = 984, TxDQ = 950
N2.C0.D1.R1.S12: TxDq : plus1 = 1, minus1 = 0, PI = 41, DB = 0
N4.C0.D1.R1.S05: Total Delay in PI ticks: TxDQ = 922
N6.C3.D0.R1.S13: Total Delay in PI ticks: TxDQS = 935, TxDQ = 901
N0.C3.D0.R0.S13: Total Delay in PI ticks: TxDQS = 946, TxDQ = 911
N2.C0.D1.R1.S13: TxDqs: plus1 = 1, minus1 = 0, PI = 39, DB = 0
N4.C0.D1.R1.S06: Total Delay in PI ticks: TxDQ = 924
N6.C3.D0.R1.S14: Total Delay in PI ticks: TxDQS = 948, TxDQ = 919
N0.C3.D0.R0.S14: Total Delay in PI ticks: TxDQS = 961, TxDQ = 928
N2.C0.D1.R1.S13: TxDq : plus1 = 0, minus1 = 1, PI = 07, DB = 1
N4.C0.D1.R1.S07: Total Delay in PI ticks: TxDQ = 941
N6.C3.D0.R1.S15: Total Delay in PI ticks: TxDQS = 962, TxDQ = 932
N0.C3.D0.R0.S15: Total Delay in PI ticks: TxDQS = 980, TxDQ = 946
N2.C0.D1.R1.S14: TxDqs: plus1 = 1, minus1 = 0, PI = 58, DB = 1
N4.C0.D1.R1.S08: Total Delay in PI ticks: TxDQ = 912
N6.C3.D0.R1.S16: Total Delay in PI ticks: TxDQS = 982, TxDQ = 953
N0.C3.D0.R0.S16: Total Delay in PI ticks: TxDQS = 989, TxDQ = 956
N2.C0.D1.R1.S14: TxDq : plus1 = 1, minus1 = 0, PI = 26, DB = 0
N4.C0.D1.R1.S09: Total Delay in PI ticks: TxDQ = 984
N6.C3.D0.R1.S17: Total Delay in PI ticks: TxDQS = 951, TxDQ = 918
N0.C3.D0.R0.S17: Total Delay in PI ticks: TxDQS = 966, TxDQ = 933
N2.C0.D1.R1.S15: TxDqs: plus1 = 1, minus1 = 0, PI = 60, DB = 1
N4.C0.D1.R1.S10: Total Delay in PI ticks: TxDQ = 967
N6.C3.D1.R0.S00: Total Delay in PI ticks: TxDQS = 1025, TxDQ = 991
N0.C3.D0.R1.S00: Total Delay in PI ticks: TxDQS = 1021, TxDQ = 987
N2.C0.D1.R1.S15: TxDq : plus1 = 1, minus1 = 0, PI = 27, DB = 0
N4.C0.D1.R1.S11: Total Delay in PI ticks: TxDQ = 953
N6.C3.D1.R0.S01: Total Delay in PI ticks: TxDQS = 1008, TxDQ = 974
N0.C3.D0.R1.S01: Total Delay in PI ticks: TxDQS = 1002, TxDQ = 968
N2.C0.D1.R1.S16: TxDqs: plus1 = 1, minus1 = 0, PI = 12, DB = 1
N4.C0.D1.R1.S12: Total Delay in PI ticks: TxDQ = 941
N6.C3.D1.R0.S02: Total Delay in PI ticks: TxDQS = 997, TxDQ = 962
N0.C3.D0.R1.S02: Total Delay in PI ticks: TxDQS = 992, TxDQ = 959
N2.C0.D1.R1.S16: TxDq : plus1 = 1, minus1 = 0, PI = 43, DB = 0
N4.C0.D1.R1.S13: Total Delay in PI ticks: TxDQ = 904
N6.C3.D1.R0.S03: Total Delay in PI ticks: TxDQS = 984, TxDQ = 950
N0.C3.D0.R1.S03: Total Delay in PI ticks: TxDQS = 977, TxDQ = 943
N2.C0.D1.R1.S17: TxDqs: plus1 = 1, minus1 = 0, PI = 48, DB = 0
N4.C0.D1.R1.S14: Total Delay in PI ticks: TxDQ = 921
N6.C3.D1.R0.S04: Total Delay in PI ticks: TxDQS = 948, TxDQ = 910
N0.C3.D0.R1.S04: Total Delay in PI ticks: TxDQS = 943, TxDQ = 908
N2.C0.D1.R1.S17: TxDq : plus1 = 1, minus1 = 0, PI = 14, DB = 1
N4.C0.D1.R1.S15: Total Delay in PI ticks: TxDQ = 925
N6.C3.D1.R0.S05: Total Delay in PI ticks: TxDQS = 960, TxDQ = 924
N0.C3.D0.R1.S05: Total Delay in PI ticks: TxDQS = 955, TxDQ = 921
END_DATA_TX_DQ
N4.C0.D1.R1.S16: Total Delay in PI ticks: TxDQ = 941
N6.C3.D1.R0.S06: Total Delay in PI ticks: TxDQS = 976, TxDQ = 940
N0.C3.D0.R1.S06: Total Delay in PI ticks: TxDQS = 970, TxDQ = 935
N2.C1.D0.R0.S00: wrcmd2dqsstartlatency: 04
N4.C0.D1.R1.S17: Total Delay in PI ticks: TxDQ = 910
N6.C3.D1.R0.S07: Total Delay in PI ticks: TxDQS = 994, TxDQ = 958
N0.C3.D0.R1.S07: Total Delay in PI ticks: TxDQS = 987, TxDQ = 954
N2.C1.D0.R0.S00: RdPtrOffsetTxDq: 06
N4.C0: Calculating Optimimum DQ/DQS Values
N6.C3.D1.R0.S08: Total Delay in PI ticks: TxDQS = 963, TxDQ = 928
N0.C3.D0.R1.S08: Total Delay in PI ticks: TxDQS = 958, TxDQ = 926
N2.C1.D0.R0.S00: RdPtrOffsetTxDqs: 07
N6.C3.D1.R0.S09: Total Delay in PI ticks: TxDQS = 1024, TxDQ = 988
N0.C3.D0.R1.S09: Total Delay in PI ticks: TxDQS = 1021, TxDQ = 985
N2.C1.D0.R0.S00: PiTxDqs: 51
START_DATA_TX_DQ
N6.C3.D1.R0.S10: Total Delay in PI ticks: TxDQS = 1008, TxDQ = 973
N0.C3.D0.R1.S10: Total Delay in PI ticks: TxDQS = 1002, TxDQ = 969
N2.C1.D0.R0.S01: wrcmd2dqsstartlatency: 04
N4.C0.S00: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 009, RdPtrOffsetTxDqs = 009
N6.C3.D1.R0.S11: Total Delay in PI ticks: TxDQS = 997, TxDQ = 963
N0.C3.D0.R1.S11: Total Delay in PI ticks: TxDQS = 993, TxDQ = 960
N2.C1.D0.R0.S01: RdPtrOffsetTxDq: 06
N4.C0.S00: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 009, RdPtrOffsetTxDqs = 009
N6.C3.D1.R0.S12: Total Delay in PI ticks: TxDQS = 984, TxDQ = 948
N0.C3.D0.R1.S12: Total Delay in PI ticks: TxDQS = 981, TxDQ = 947
N2.C1.D0.R0.S01: RdPtrOffsetTxDqs: 07
N4.C0.S01: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 009, RdPtrOffsetTxDqs = 009
N6.C3.D1.R0.S13: Total Delay in PI ticks: TxDQS = 947, TxDQ = 911
N0.C3.D0.R1.S13: Total Delay in PI ticks: TxDQS = 944, TxDQ = 909
N2.C1.D0.R0.S01: PiTxDqs: 34
N4.C0.S01: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 009, RdPtrOffsetTxDqs = 009
N6.C3.D1.R0.S14: Total Delay in PI ticks: TxDQS = 961, TxDQ = 930
N0.C3.D0.R1.S14: Total Delay in PI ticks: TxDQS = 957, TxDQ = 924
N2.C1.D0.R0.S02: wrcmd2dqsstartlatency: 04
N4.C0.S02: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 009
N6.C3.D1.R0.S15: Total Delay in PI ticks: TxDQS = 975, TxDQ = 941
N0.C3.D0.R1.S15: Total Delay in PI ticks: TxDQS = 969, TxDQ = 935
N2.C1.D0.R0.S02: RdPtrOffsetTxDq: 05
N4.C0.S02: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 009
N6.C3.D1.R0.S16: Total Delay in PI ticks: TxDQS = 994, TxDQ = 960
N0.C3.D0.R1.S16: Total Delay in PI ticks: TxDQS = 987, TxDQ = 954
N2.C1.D0.R0.S02: RdPtrOffsetTxDqs: 07
N4.C0.S03: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 009
N6.C3.D1.R0.S17: Total Delay in PI ticks: TxDQS = 963, TxDQ = 927
N0.C3.D0.R1.S17: Total Delay in PI ticks: TxDQS = 958, TxDQ = 925
N2.C1.D0.R0.S02: PiTxDqs: 27
N4.C0.S03: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 009
N6.C3.D1.R1.S00: Total Delay in PI ticks: TxDQS = 1020, TxDQ = 988
N0.C3.D1.R0.S00: Total Delay in PI ticks: TxDQS = 1030, TxDQ = 994
N2.C1.D0.R0.S03: wrcmd2dqsstartlatency: 04
N4.C0.S04: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 008
N6.C3.D1.R1.S01: Total Delay in PI ticks: TxDQS = 1003, TxDQ = 968
N0.C3.D1.R0.S01: Total Delay in PI ticks: TxDQS = 1011, TxDQ = 975
N2.C1.D0.R0.S03: RdPtrOffsetTxDq: 05
N4.C0.S04: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 008
N6.C3.D1.R1.S02: Total Delay in PI ticks: TxDQS = 992, TxDQ = 958
N0.C3.D1.R0.S02: Total Delay in PI ticks: TxDQS = 1003, TxDQ = 967
N2.C1.D0.R0.S03: RdPtrOffsetTxDqs: 07
N4.C0.S05: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 008
N6.C3.D1.R1.S03: Total Delay in PI ticks: TxDQS = 980, TxDQ = 946
N0.C3.D1.R0.S03: Total Delay in PI ticks: TxDQS = 984, TxDQ = 948
N2.C1.D0.R0.S03: PiTxDqs: 09
N4.C0.S05: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 008
N6.C3.D1.R1.S04: Total Delay in PI ticks: TxDQS = 944, TxDQ = 906
N0.C3.D1.R0.S04: Total Delay in PI ticks: TxDQS = 950, TxDQ = 914
N2.C1.D0.R0.S04: wrcmd2dqsstartlatency: 04
N4.C0.S06: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 008
N6.C3.D1.R1.S05: Total Delay in PI ticks: TxDQS = 956, TxDQ = 921
N0.C3.D1.R0.S05: Total Delay in PI ticks: TxDQS = 964, TxDQ = 928
N2.C1.D0.R0.S04: RdPtrOffsetTxDq: 05
N4.C0.S06: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 008
N6.C3.D1.R1.S06: Total Delay in PI ticks: TxDQS = 970, TxDQ = 934
N0.C3.D1.R0.S06: Total Delay in PI ticks: TxDQS = 978, TxDQ = 942
N2.C1.D0.R0.S04: RdPtrOffsetTxDqs: 06
N4.C0.S07: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 009
N6.C3.D1.R1.S07: Total Delay in PI ticks: TxDQS = 989, TxDQ = 953
N0.C3.D1.R0.S07: Total Delay in PI ticks: TxDQS = 995, TxDQ = 960
N2.C1.D0.R0.S04: PiTxDqs: 41
N4.C0.S07: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 009
N6.C3.D1.R1.S08: Total Delay in PI ticks: TxDQS = 956, TxDQ = 921
N0.C3.D1.R0.S08: Total Delay in PI ticks: TxDQS = 964, TxDQ = 930
N2.C1.D0.R0.S05: wrcmd2dqsstartlatency: 04
N4.C0.S08: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 008
N6.C3.D1.R1.S09: Total Delay in PI ticks: TxDQS = 1019, TxDQ = 983
N0.C3.D1.R0.S09: Total Delay in PI ticks: TxDQS = 1030, TxDQ = 992
N2.C1.D0.R0.S05: RdPtrOffsetTxDq: 05
N4.C0.S08: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 008
N6.C3.D1.R1.S10: Total Delay in PI ticks: TxDQS = 1003, TxDQ = 968
N0.C3.D1.R0.S10: Total Delay in PI ticks: TxDQS = 1013, TxDQ = 977
N2.C1.D0.R0.S05: RdPtrOffsetTxDqs: 06
N4.C0.D0.R0.S00: TxDqs: plus1 = 1, minus1 = 0, PI = 55, DB = 1
N6.C3.D1.R1.S11: Total Delay in PI ticks: TxDQS = 995, TxDQ = 960
N0.C3.D1.R0.S11: Total Delay in PI ticks: TxDQS = 1003, TxDQ = 970
N2.C1.D0.R0.S05: PiTxDqs: 56
N4.C0.D0.R0.S00: TxDq : plus1 = 1, minus1 = 0, PI = 22, DB = 0
N6.C3.D1.R1.S12: Total Delay in PI ticks: TxDQS = 980, TxDQ = 944
N0.C3.D1.R0.S12: Total Delay in PI ticks: TxDQS = 985, TxDQ = 950
N2.C1.D0.R0.S06: wrcmd2dqsstartlatency: 04
N4.C0.D0.R0.S01: TxDqs: plus1 = 1, minus1 = 0, PI = 35, DB = 0
N6.C3.D1.R1.S13: Total Delay in PI ticks: TxDQS = 943, TxDQ = 907
N0.C3.D1.R0.S13: Total Delay in PI ticks: TxDQS = 952, TxDQ = 916
N2.C1.D0.R0.S06: RdPtrOffsetTxDq: 05
N4.C0.D0.R0.S01: TxDq : plus1 = 1, minus1 = 0, PI = 01, DB = 1
N6.C3.D1.R1.S14: Total Delay in PI ticks: TxDQS = 956, TxDQ = 926
N0.C3.D1.R0.S14: Total Delay in PI ticks: TxDQS = 965, TxDQ = 931
N2.C1.D0.R0.S06: RdPtrOffsetTxDqs: 07
N4.C0.D0.R0.S02: TxDqs: plus1 = 1, minus1 = 0, PI = 27, DB = 0
N6.C3.D1.R1.S15: Total Delay in PI ticks: TxDQS = 969, TxDQ = 935
N0.C3.D1.R0.S15: Total Delay in PI ticks: TxDQS = 981, TxDQ = 946
N2.C1.D0.R0.S06: PiTxDqs: 06
N4.C0.D0.R0.S02: TxDq : plus1 = 1, minus1 = 0, PI = 56, DB = 1
N6.C3.D1.R1.S16: Total Delay in PI ticks: TxDQS = 988, TxDQ = 956
N0.C3.D1.R0.S16: Total Delay in PI ticks: TxDQS = 993, TxDQ = 958
N2.C1.D0.R0.S07: wrcmd2dqsstartlatency: 04
N4.C0.D0.R0.S03: TxDqs: plus1 = 1, minus1 = 0, PI = 08, DB = 1
N6.C3.D1.R1.S17: Total Delay in PI ticks: TxDQS = 956, TxDQ = 920
N0.C3.D1.R0.S17: Total Delay in PI ticks: TxDQS = 963, TxDQ = 928
N2.C1.D0.R0.S07: RdPtrOffsetTxDq: 05
N4.C0.D0.R0.S03: TxDq : plus1 = 1, minus1 = 0, PI = 38, DB = 0
N6: END WRITE LEVEL COARSE:
N0.C3.D1.R1.S00: Total Delay in PI ticks: TxDQS = 1028, TxDQ = 992
N2.C1.D0.R0.S07: RdPtrOffsetTxDqs: 07
N4.C0.D0.R0.S04: TxDqs: plus1 = 1, minus1 = 0, PI = 39, DB = 0
N6: RunTrainStep: Final status = 0
N0.C3.D1.R1.S01: Total Delay in PI ticks: TxDQS = 1009, TxDQ = 973
N2.C1.D0.R0.S07: PiTxDqs: 22
N4.C0.D0.R0.S04: TxDq : plus1 = 1, minus1 = 0, PI = 06, DB = 1

END - Basic Write Level Training       Time         36742 ms
N0.C3.D1.R1.S02: Total Delay in PI ticks: TxDQS = 999, TxDQ = 964
N2.C1.D0.R0.S08: wrcmd2dqsstartlatency: 04
N4.C0.D0.R0.S05: TxDqs: plus1 = 1, minus1 = 0, PI = 58, DB = 1

START - Basic Write DQ/DQS Training
N0.C3.D1.R1.S03: Total Delay in PI ticks: TxDQS = 984, TxDQ = 948
N2.C1.D0.R0.S08: RdPtrOffsetTxDq: 05
N4.C0.D0.R0.S05: TxDq : plus1 = 1, minus1 = 0, PI = 23, DB = 0
N6.C0.D0.R0.S00: wrcmd2dqsstartlatency: 04
N0.C3.D1.R1.S04: Total Delay in PI ticks: TxDQS = 948, TxDQ = 912
N2.C1.D0.R0.S08: RdPtrOffsetTxDqs: 06
N4.C0.D0.R0.S06: TxDqs: plus1 = 1, minus1 = 0, PI = 59, DB = 1
N6.C0.D0.R0.S00: RdPtrOffsetTxDq: 06
N0.C3.D1.R1.S05: Total Delay in PI ticks: TxDQS = 961, TxDQ = 925
N2.C1.D0.R0.S08: PiTxDqs: 56
N4.C0.D0.R0.S06: TxDq : plus1 = 1, minus1 = 0, PI = 25, DB = 0
N6.C0.D0.R0.S00: RdPtrOffsetTxDqs: 07
N0.C3.D1.R1.S06: Total Delay in PI ticks: TxDQS = 976, TxDQ = 940
N2.C1.D0.R0.S09: wrcmd2dqsstartlatency: 04
N4.C0.D0.R0.S07: TxDqs: plus1 = 1, minus1 = 0, PI = 10, DB = 1
N6.C0.D0.R0.S00: PiTxDqs: 55
N0.C3.D1.R1.S07: Total Delay in PI ticks: TxDQS = 994, TxDQ = 959
N2.C1.D0.R0.S09: RdPtrOffsetTxDq: 06
N4.C0.D0.R0.S07: TxDq : plus1 = 1, minus1 = 0, PI = 41, DB = 0
N6.C0.D0.R0.S01: wrcmd2dqsstartlatency: 04
N0.C3.D1.R1.S08: Total Delay in PI ticks: TxDQS = 961, TxDQ = 928
N2.C1.D0.R0.S09: RdPtrOffsetTxDqs: 07
N4.C0.D0.R0.S08: TxDqs: plus1 = 1, minus1 = 0, PI = 52, DB = 1
N6.C0.D0.R0.S01: RdPtrOffsetTxDq: 06
N0.C3.D1.R1.S09: Total Delay in PI ticks: TxDQS = 1027, TxDQ = 989
N2.C1.D0.R0.S09: PiTxDqs: 52
N4.C0.D0.R0.S08: TxDq : plus1 = 1, minus1 = 0, PI = 18, DB = 0
N6.C0.D0.R0.S01: RdPtrOffsetTxDqs: 07
N0.C3.D1.R1.S10: Total Delay in PI ticks: TxDQS = 1010, TxDQ = 974
N2.C1.D0.R0.S10: wrcmd2dqsstartlatency: 04
N4.C0.D0.R0.S09: TxDqs: plus1 = 1, minus1 = 0, PI = 53, DB = 1
N6.C0.D0.R0.S01: PiTxDqs: 33
N0.C3.D1.R1.S11: Total Delay in PI ticks: TxDQS = 999, TxDQ = 965
N2.C1.D0.R0.S10: RdPtrOffsetTxDq: 06
N4.C0.D0.R0.S09: TxDq : plus1 = 1, minus1 = 0, PI = 21, DB = 0
N6.C0.D0.R0.S02: wrcmd2dqsstartlatency: 04
N0.C3.D1.R1.S12: Total Delay in PI ticks: TxDQS = 986, TxDQ = 951
N2.C1.D0.R0.S10: RdPtrOffsetTxDqs: 07
N4.C0.D0.R0.S10: TxDqs: plus1 = 1, minus1 = 0, PI = 35, DB = 0
N6.C0.D0.R0.S02: RdPtrOffsetTxDq: 05
N0.C3.D1.R1.S13: Total Delay in PI ticks: TxDQS = 951, TxDQ = 915
N2.C1.D0.R0.S10: PiTxDqs: 34
N4.C0.D0.R0.S10: TxDq : plus1 = 1, minus1 = 0, PI = 01, DB = 1
N6.C0.D0.R0.S02: RdPtrOffsetTxDqs: 07
N0.C3.D1.R1.S14: Total Delay in PI ticks: TxDQS = 963, TxDQ = 929
N2.C1.D0.R0.S11: wrcmd2dqsstartlatency: 04
N4.C0.D0.R0.S11: TxDqs: plus1 = 1, minus1 = 0, PI = 24, DB = 0
N6.C0.D0.R0.S02: PiTxDqs: 23
N0.C3.D1.R1.S15: Total Delay in PI ticks: TxDQS = 976, TxDQ = 941
N2.C1.D0.R0.S11: RdPtrOffsetTxDq: 05
N4.C0.D0.R0.S11: TxDq : plus1 = 1, minus1 = 0, PI = 54, DB = 1
N6.C0.D0.R0.S03: wrcmd2dqsstartlatency: 04
N0.C3.D1.R1.S16: Total Delay in PI ticks: TxDQS = 991, TxDQ = 957
N2.C1.D0.R0.S11: RdPtrOffsetTxDqs: 07
N4.C0.D0.R0.S12: TxDqs: plus1 = 1, minus1 = 0, PI = 08, DB = 1
N6.C0.D0.R0.S03: RdPtrOffsetTxDq: 05
N0.C3.D1.R1.S17: Total Delay in PI ticks: TxDQS = 961, TxDQ = 926
N2.C1.D0.R0.S11: PiTxDqs: 27
N4.C0.D0.R0.S12: TxDq : plus1 = 1, minus1 = 0, PI = 38, DB = 0
N6.C0.D0.R0.S03: RdPtrOffsetTxDqs: 07
N0: END WRITE LEVEL COARSE:
N2.C1.D0.R0.S12: wrcmd2dqsstartlatency: 04
N4.C0.D0.R0.S13: TxDqs: plus1 = 1, minus1 = 0, PI = 40, DB = 0
N6.C0.D0.R0.S03: PiTxDqs: 05
N0: RunTrainStep: Final status = 0
N2.C1.D0.R0.S12: RdPtrOffsetTxDq: 05
N4.C0.D0.R0.S13: TxDq : plus1 = 1, minus1 = 0, PI = 06, DB = 1
N6.C0.D0.R0.S04: wrcmd2dqsstartlatency: 04

END - Basic Write Level Training       Time         36833 ms
N2.C1.D0.R0.S12: RdPtrOffsetTxDqs: 07
N4.C0.D0.R0.S14: TxDqs: plus1 = 1, minus1 = 0, PI = 53, DB = 1
N6.C0.D0.R0.S04: RdPtrOffsetTxDq: 05

START - Basic Write DQ/DQS Training
N2.C1.D0.R0.S12: PiTxDqs: 09
N4.C0.D0.R0.S14: TxDq : plus1 = 1, minus1 = 0, PI = 21, DB = 0
N6.C0.D0.R0.S04: RdPtrOffsetTxDqs: 06
Checkpoint Code: Socket 0, 0xB7, 0x05, 0x0000
N2.C1.D0.R0.S13: wrcmd2dqsstartlatency: 04
N4.C0.D0.R0.S15: TxDqs: plus1 = 1, minus1 = 0, PI = 59, DB = 1
N6.C0.D0.R0.S04: PiTxDqs: 37
N0.C0.D0.R0.S00: wrcmd2dqsstartlatency: 04
N2.C1.D0.R0.S13: RdPtrOffsetTxDq: 05
N4.C0.D0.R0.S15: TxDq : plus1 = 1, minus1 = 0, PI = 26, DB = 0
N6.C0.D0.R0.S05: wrcmd2dqsstartlatency: 04
N0.C0.D0.R0.S00: RdPtrOffsetTxDq: 06
N2.C1.D0.R0.S13: RdPtrOffsetTxDqs: 06
N4.C0.D0.R0.S16: TxDqs: plus1 = 1, minus1 = 0, PI = 10, DB = 1
N6.C0.D0.R0.S05: RdPtrOffsetTxDq: 05
N0.C0.D0.R0.S00: RdPtrOffsetTxDqs: 07
N2.C1.D0.R0.S13: PiTxDqs: 41
N4.C0.D0.R0.S16: TxDq : plus1 = 1, minus1 = 0, PI = 42, DB = 0
N6.C0.D0.R0.S05: RdPtrOffsetTxDqs: 06
N0.C0.D0.R0.S00: PiTxDqs: 55
N2.C1.D0.R0.S14: wrcmd2dqsstartlatency: 04
N4.C0.D0.R0.S17: TxDqs: plus1 = 1, minus1 = 0, PI = 50, DB = 1
N6.C0.D0.R0.S05: PiTxDqs: 55
N0.C0.D0.R0.S01: wrcmd2dqsstartlatency: 04
N2.C1.D0.R0.S14: RdPtrOffsetTxDq: 05
N4.C0.D0.R0.S17: TxDq : plus1 = 1, minus1 = 0, PI = 16, DB = 0
N6.C0.D0.R0.S06: wrcmd2dqsstartlatency: 04
N0.C0.D0.R0.S01: RdPtrOffsetTxDq: 06
N2.C1.D0.R0.S14: RdPtrOffsetTxDqs: 06
N4.C0.D0.R1.S00: TxDqs: plus1 = 1, minus1 = 0, PI = 55, DB = 1
N6.C0.D0.R0.S06: RdPtrOffsetTxDq: 05
N0.C0.D0.R0.S01: RdPtrOffsetTxDqs: 07
N2.C1.D0.R0.S14: PiTxDqs: 56
N4.C0.D0.R1.S00: TxDq : plus1 = 1, minus1 = 0, PI = 22, DB = 0
N6.C0.D0.R0.S06: RdPtrOffsetTxDqs: 06
N0.C0.D0.R0.S01: PiTxDqs: 38
N2.C1.D0.R0.S15: wrcmd2dqsstartlatency: 04
N4.C0.D0.R1.S01: TxDqs: plus1 = 1, minus1 = 0, PI = 35, DB = 0
N6.C0.D0.R0.S06: PiTxDqs: 59
N0.C0.D0.R0.S02: wrcmd2dqsstartlatency: 04
N2.C1.D0.R0.S15: RdPtrOffsetTxDq: 05
N4.C0.D0.R1.S01: TxDq : plus1 = 1, minus1 = 0, PI = 01, DB = 1
N6.C0.D0.R0.S07: wrcmd2dqsstartlatency: 04
N0.C0.D0.R0.S02: RdPtrOffsetTxDq: 05
N2.C1.D0.R0.S15: RdPtrOffsetTxDqs: 07
N4.C0.D0.R1.S02: TxDqs: plus1 = 1, minus1 = 0, PI = 27, DB = 0
N6.C0.D0.R0.S07: RdPtrOffsetTxDq: 05
N0.C0.D0.R0.S02: RdPtrOffsetTxDqs: 07
N2.C1.D0.R0.S15: PiTxDqs: 05
N4.C0.D0.R1.S02: TxDq : plus1 = 1, minus1 = 0, PI = 56, DB = 1
N6.C0.D0.R0.S07: RdPtrOffsetTxDqs: 07
N0.C0.D0.R0.S02: PiTxDqs: 28
N2.C1.D0.R0.S16: wrcmd2dqsstartlatency: 04
N4.C0.D0.R1.S03: TxDqs: plus1 = 1, minus1 = 0, PI = 08, DB = 1
N6.C0.D0.R0.S07: PiTxDqs: 10
N0.C0.D0.R0.S03: wrcmd2dqsstartlatency: 04
N2.C1.D0.R0.S16: RdPtrOffsetTxDq: 05
N4.C0.D0.R1.S03: TxDq : plus1 = 1, minus1 = 0, PI = 38, DB = 0
N6.C0.D0.R0.S08: wrcmd2dqsstartlatency: 04
N0.C0.D0.R0.S03: RdPtrOffsetTxDq: 05
N2.C1.D0.R0.S16: RdPtrOffsetTxDqs: 07
N4.C0.D0.R1.S04: TxDqs: plus1 = 1, minus1 = 0, PI = 39, DB = 0
N6.C0.D0.R0.S08: RdPtrOffsetTxDq: 05
N0.C0.D0.R0.S03: RdPtrOffsetTxDqs: 07
N2.C1.D0.R0.S16: PiTxDqs: 23
N4.C0.D0.R1.S04: TxDq : plus1 = 1, minus1 = 0, PI = 06, DB = 1
N6.C0.D0.R0.S08: RdPtrOffsetTxDqs: 06
N0.C0.D0.R0.S03: PiTxDqs: 08
N2.C1.D0.R0.S17: wrcmd2dqsstartlatency: 04
N4.C0.D0.R1.S05: TxDqs: plus1 = 1, minus1 = 0, PI = 58, DB = 1
N6.C0.D0.R0.S08: PiTxDqs: 50
N0.C0.D0.R0.S04: wrcmd2dqsstartlatency: 04
N2.C1.D0.R0.S17: RdPtrOffsetTxDq: 05
N4.C0.D0.R1.S05: TxDq : plus1 = 1, minus1 = 0, PI = 23, DB = 0
N6.C0.D0.R0.S09: wrcmd2dqsstartlatency: 04
N0.C0.D0.R0.S04: RdPtrOffsetTxDq: 05
N2.C1.D0.R0.S17: RdPtrOffsetTxDqs: 06
N4.C0.D0.R1.S06: TxDqs: plus1 = 1, minus1 = 0, PI = 59, DB = 1
N6.C0.D0.R0.S09: RdPtrOffsetTxDq: 06
N0.C0.D0.R0.S04: RdPtrOffsetTxDqs: 06
N2.C1.D0.R0.S17: PiTxDqs: 54
N4.C0.D0.R1.S06: TxDq : plus1 = 1, minus1 = 0, PI = 25, DB = 0
N6.C0.D0.R0.S09: RdPtrOffsetTxDqs: 07
N0.C0.D0.R0.S04: PiTxDqs: 42
N2.C1.D0.R0.S00: RdPtrOffsetTxDq: 07
N4.C0.D0.R1.S07: TxDqs: plus1 = 1, minus1 = 0, PI = 10, DB = 1
N6.C0.D0.R0.S09: PiTxDqs: 55
N0.C0.D0.R0.S05: wrcmd2dqsstartlatency: 04
N2.C1.D0.R0.S01: RdPtrOffsetTxDq: 07
N4.C0.D0.R1.S07: TxDq : plus1 = 1, minus1 = 0, PI = 41, DB = 0
N6.C0.D0.R0.S10: wrcmd2dqsstartlatency: 04
N0.C0.D0.R0.S05: RdPtrOffsetTxDq: 05
N2.C1.D0.R0.S02: RdPtrOffsetTxDq: 06
N4.C0.D0.R1.S08: TxDqs: plus1 = 1, minus1 = 0, PI = 52, DB = 1
N6.C0.D0.R0.S10: RdPtrOffsetTxDq: 06
N0.C0.D0.R0.S05: RdPtrOffsetTxDqs: 06
N2.C1.D0.R0.S03: RdPtrOffsetTxDq: 06
N4.C0.D0.R1.S08: TxDq : plus1 = 1, minus1 = 0, PI = 18, DB = 0
N6.C0.D0.R0.S10: RdPtrOffsetTxDqs: 07
N0.C0.D0.R0.S05: PiTxDqs: 58
N2.C1.D0.R0.S04: RdPtrOffsetTxDq: 06
N4.C0.D0.R1.S09: TxDqs: plus1 = 1, minus1 = 0, PI = 53, DB = 1
N6.C0.D0.R0.S10: PiTxDqs: 32
N0.C0.D0.R0.S06: wrcmd2dqsstartlatency: 04
N2.C1.D0.R0.S05: RdPtrOffsetTxDq: 06
N4.C0.D0.R1.S09: TxDq : plus1 = 1, minus1 = 0, PI = 21, DB = 0
N6.C0.D0.R0.S11: wrcmd2dqsstartlatency: 04
N0.C0.D0.R0.S06: RdPtrOffsetTxDq: 05
N2.C1.D0.R0.S06: RdPtrOffsetTxDq: 06
N4.C0.D0.R1.S10: TxDqs: plus1 = 1, minus1 = 0, PI = 35, DB = 0
N6.C0.D0.R0.S11: RdPtrOffsetTxDq: 05
N0.C0.D0.R0.S06: RdPtrOffsetTxDqs: 06
N2.C1.D0.R0.S07: RdPtrOffsetTxDq: 06
N4.C0.D0.R1.S10: TxDq : plus1 = 1, minus1 = 0, PI = 01, DB = 1
N6.C0.D0.R0.S11: RdPtrOffsetTxDqs: 07
N0.C0.D0.R0.S06: PiTxDqs: 61
N2.C1.D0.R0.S08: RdPtrOffsetTxDq: 06
N4.C0.D0.R1.S11: TxDqs: plus1 = 1, minus1 = 0, PI = 24, DB = 0
N6.C0.D0.R0.S11: PiTxDqs: 22
N0.C0.D0.R0.S07: wrcmd2dqsstartlatency: 04
N2.C1.D0.R0.S09: RdPtrOffsetTxDq: 07
N4.C0.D0.R1.S11: TxDq : plus1 = 1, minus1 = 0, PI = 54, DB = 1
N6.C0.D0.R0.S12: wrcmd2dqsstartlatency: 04
N0.C0.D0.R0.S07: RdPtrOffsetTxDq: 05
N2.C1.D0.R0.S10: RdPtrOffsetTxDq: 07
N4.C0.D0.R1.S12: TxDqs: plus1 = 1, minus1 = 0, PI = 08, DB = 1
N6.C0.D0.R0.S12: RdPtrOffsetTxDq: 05
N0.C0.D0.R0.S07: RdPtrOffsetTxDqs: 07
N2.C1.D0.R0.S11: RdPtrOffsetTxDq: 06
N4.C0.D0.R1.S12: TxDq : plus1 = 1, minus1 = 0, PI = 38, DB = 0
N6.C0.D0.R0.S12: RdPtrOffsetTxDqs: 07
N0.C0.D0.R0.S07: PiTxDqs: 14
N2.C1.D0.R0.S12: RdPtrOffsetTxDq: 06
N4.C0.D0.R1.S13: TxDqs: plus1 = 1, minus1 = 0, PI = 40, DB = 0
N6.C0.D0.R0.S12: PiTxDqs: 07
N0.C0.D0.R0.S08: wrcmd2dqsstartlatency: 04
N2.C1.D0.R0.S13: RdPtrOffsetTxDq: 06
N4.C0.D0.R1.S13: TxDq : plus1 = 1, minus1 = 0, PI = 06, DB = 1
N6.C0.D0.R0.S13: wrcmd2dqsstartlatency: 04
N0.C0.D0.R0.S08: RdPtrOffsetTxDq: 05
N2.C1.D0.R0.S14: RdPtrOffsetTxDq: 06
N4.C0.D0.R1.S14: TxDqs: plus1 = 1, minus1 = 0, PI = 53, DB = 1
N6.C0.D0.R0.S13: RdPtrOffsetTxDq: 05
N0.C0.D0.R0.S08: RdPtrOffsetTxDqs: 06
N2.C1.D0.R0.S15: RdPtrOffsetTxDq: 06
N4.C0.D0.R1.S14: TxDq : plus1 = 1, minus1 = 0, PI = 21, DB = 0
N6.C0.D0.R0.S13: RdPtrOffsetTxDqs: 06
N0.C0.D0.R0.S08: PiTxDqs: 52
N2.C1.D0.R0.S16: RdPtrOffsetTxDq: 06
N4.C0.D0.R1.S15: TxDqs: plus1 = 1, minus1 = 0, PI = 59, DB = 1
N6.C0.D0.R0.S13: PiTxDqs: 37
N0.C0.D0.R0.S09: wrcmd2dqsstartlatency: 04
N2.C1.D0.R0.S17: RdPtrOffsetTxDq: 06
N4.C0.D0.R1.S15: TxDq : plus1 = 1, minus1 = 0, PI = 26, DB = 0
N6.C0.D0.R0.S14: wrcmd2dqsstartlatency: 04
N0.C0.D0.R0.S09: RdPtrOffsetTxDq: 06
N2.C1.D0.R0.S00: RdPtrOffsetTxDq: 08
N4.C0.D0.R1.S16: TxDqs: plus1 = 1, minus1 = 0, PI = 10, DB = 1
N6.C0.D0.R0.S14: RdPtrOffsetTxDq: 05
N0.C0.D0.R0.S09: RdPtrOffsetTxDqs: 07
N2.C1.D0.R0.S01: RdPtrOffsetTxDq: 08
N4.C0.D0.R1.S16: TxDq : plus1 = 1, minus1 = 0, PI = 42, DB = 0
N6.C0.D0.R0.S14: RdPtrOffsetTxDqs: 06
N0.C0.D0.R0.S09: PiTxDqs: 57
N2.C1.D0.R0.S02: RdPtrOffsetTxDq: 07
N4.C0.D0.R1.S17: TxDqs: plus1 = 1, minus1 = 0, PI = 50, DB = 1
N6.C0.D0.R0.S14: PiTxDqs: 56
N0.C0.D0.R0.S10: wrcmd2dqsstartlatency: 04
N2.C1.D0.R0.S03: RdPtrOffsetTxDq: 07
N4.C0.D0.R1.S17: TxDq : plus1 = 1, minus1 = 0, PI = 16, DB = 0
N6.C0.D0.R0.S15: wrcmd2dqsstartlatency: 04
N0.C0.D0.R0.S10: RdPtrOffsetTxDq: 06
N2.C1.D0.R0.S04: RdPtrOffsetTxDq: 07
N4.C0.D1.R0.S00: TxDqs: plus1 = 1, minus1 = 0, PI = 57, DB = 1
N6.C0.D0.R0.S15: RdPtrOffsetTxDq: 05
N0.C0.D0.R0.S10: RdPtrOffsetTxDqs: 07
N2.C1.D0.R0.S05: RdPtrOffsetTxDq: 07
N4.C0.D1.R0.S00: TxDq : plus1 = 1, minus1 = 0, PI = 24, DB = 0
N6.C0.D0.R0.S15: RdPtrOffsetTxDqs: 06
N0.C0.D0.R0.S10: PiTxDqs: 37
N2.C1.D0.R0.S06: RdPtrOffsetTxDq: 07
N4.C0.D1.R0.S01: TxDqs: plus1 = 1, minus1 = 0, PI = 43, DB = 0
N6.C0.D0.R0.S15: PiTxDqs: 57
N0.C0.D0.R0.S11: wrcmd2dqsstartlatency: 04
N2.C1.D0.R0.S07: RdPtrOffsetTxDq: 07
N4.C0.D1.R0.S01: TxDq : plus1 = 1, minus1 = 0, PI = 08, DB = 1
N6.C0.D0.R0.S16: wrcmd2dqsstartlatency: 04
N0.C0.D0.R0.S11: RdPtrOffsetTxDq: 05
N2.C1.D0.R0.S08: RdPtrOffsetTxDq: 07
N4.C0.D1.R0.S02: TxDqs: plus1 = 1, minus1 = 0, PI = 31, DB = 0
N6.C0.D0.R0.S16: RdPtrOffsetTxDq: 05
N0.C0.D0.R0.S11: RdPtrOffsetTxDqs: 07
N2.C1.D0.R0.S09: RdPtrOffsetTxDq: 08
N4.C0.D1.R0.S02: TxDq : plus1 = 1, minus1 = 0, PI = 59, DB = 1
N6.C0.D0.R0.S16: RdPtrOffsetTxDqs: 07
N0.C0.D0.R0.S11: PiTxDqs: 28
N2.C1.D0.R0.S10: RdPtrOffsetTxDq: 08
N4.C0.D1.R0.S03: TxDqs: plus1 = 1, minus1 = 0, PI = 14, DB = 1
N6.C0.D0.R0.S16: PiTxDqs: 10
N0.C0.D0.R0.S12: wrcmd2dqsstartlatency: 04
N2.C1.D0.R0.S11: RdPtrOffsetTxDq: 07
N4.C0.D1.R0.S03: TxDq : plus1 = 1, minus1 = 0, PI = 41, DB = 0
N6.C0.D0.R0.S17: wrcmd2dqsstartlatency: 04
N0.C0.D0.R0.S12: RdPtrOffsetTxDq: 05
N2.C1.D0.R0.S12: RdPtrOffsetTxDq: 07
N4.C0.D1.R0.S04: TxDqs: plus1 = 1, minus1 = 0, PI = 43, DB = 0
N6.C0.D0.R0.S17: RdPtrOffsetTxDq: 05
N0.C0.D0.R0.S12: RdPtrOffsetTxDqs: 07
N2.C1.D0.R0.S13: RdPtrOffsetTxDq: 07
N4.C0.D1.R0.S04: TxDq : plus1 = 1, minus1 = 0, PI = 08, DB = 1
N6.C0.D0.R0.S17: RdPtrOffsetTxDqs: 06
N0.C0.D0.R0.S12: PiTxDqs: 11
N2.C1.D0.R0.S14: RdPtrOffsetTxDq: 07
N4.C0.D1.R0.S05: TxDqs: plus1 = 1, minus1 = 0, PI = 62, DB = 1
N6.C0.D0.R0.S17: PiTxDqs: 52
N0.C0.D0.R0.S13: wrcmd2dqsstartlatency: 04
N2.C1.D0.R0.S15: RdPtrOffsetTxDq: 07
N4.C0.D1.R0.S05: TxDq : plus1 = 1, minus1 = 0, PI = 26, DB = 0
N6.C0.D0.R0.S00: RdPtrOffsetTxDq: 07
N0.C0.D0.R0.S13: RdPtrOffsetTxDq: 05
N2.C1.D0.R0.S16: RdPtrOffsetTxDq: 07
N4.C0.D1.R0.S06: TxDqs: plus1 = 0, minus1 = 1, PI = 01, DB = 1
N6.C0.D0.R0.S01: RdPtrOffsetTxDq: 07
N0.C0.D0.R0.S13: RdPtrOffsetTxDqs: 06
N2.C1.D0.R0.S17: RdPtrOffsetTxDq: 07
N4.C0.D1.R0.S06: TxDq : plus1 = 1, minus1 = 0, PI = 29, DB = 0
N6.C0.D0.R0.S02: RdPtrOffsetTxDq: 06
N0.C0.D0.R0.S13: PiTxDqs: 42
N2.C1.D0.R0.S00: Total Delay in PI ticks: TxDQ = 981
N4.C0.D1.R0.S07: TxDqs: plus1 = 1, minus1 = 0, PI = 16, DB = 0
N6.C0.D0.R0.S03: RdPtrOffsetTxDq: 06
N0.C0.D0.R0.S14: wrcmd2dqsstartlatency: 04
N2.C1.D0.R0.S01: Total Delay in PI ticks: TxDQ = 962
N4.C0.D1.R0.S07: TxDq : plus1 = 1, minus1 = 0, PI = 46, DB = 0
N6.C0.D0.R0.S04: RdPtrOffsetTxDq: 06
N0.C0.D0.R0.S14: RdPtrOffsetTxDq: 05
N2.C1.D0.R0.S02: Total Delay in PI ticks: TxDQ = 956
N4.C0.D1.R0.S08: TxDqs: plus1 = 1, minus1 = 0, PI = 52, DB = 1
N6.C0.D0.R0.S05: RdPtrOffsetTxDq: 06
N0.C0.D0.R0.S14: RdPtrOffsetTxDqs: 06
N2.C1.D0.R0.S03: Total Delay in PI ticks: TxDQ = 939
N4.C0.D1.R0.S08: TxDq : plus1 = 1, minus1 = 0, PI = 17, DB = 0
N6.C0.D0.R0.S06: RdPtrOffsetTxDq: 06
N0.C0.D0.R0.S14: PiTxDqs: 56
N2.C1.D0.R0.S04: Total Delay in PI ticks: TxDQ = 906
N4.C0.D1.R0.S09: TxDqs: plus1 = 1, minus1 = 0, PI = 57, DB = 1
N6.C0.D0.R0.S07: RdPtrOffsetTxDq: 06
N0.C0.D0.R0.S15: wrcmd2dqsstartlatency: 04
N2.C1.D0.R0.S05: Total Delay in PI ticks: TxDQ = 919
N4.C0.D1.R0.S09: TxDq : plus1 = 1, minus1 = 0, PI = 24, DB = 0
N6.C0.D0.R0.S08: RdPtrOffsetTxDq: 06
N0.C0.D0.R0.S15: RdPtrOffsetTxDq: 05
N2.C1.D0.R0.S06: Total Delay in PI ticks: TxDQ = 934
N4.C0.D1.R0.S10: TxDqs: plus1 = 1, minus1 = 0, PI = 44, DB = 0
N6.C0.D0.R0.S09: RdPtrOffsetTxDq: 07
N0.C0.D0.R0.S15: RdPtrOffsetTxDqs: 06
N2.C1.D0.R0.S07: Total Delay in PI ticks: TxDQ = 948
N4.C0.D1.R0.S10: TxDq : plus1 = 1, minus1 = 0, PI = 09, DB = 1
N6.C0.D0.R0.S10: RdPtrOffsetTxDq: 07
N0.C0.D0.R0.S15: PiTxDqs: 61
N2.C1.D0.R0.S08: Total Delay in PI ticks: TxDQ = 920
N4.C0.D1.R0.S11: TxDqs: plus1 = 1, minus1 = 0, PI = 31, DB = 0
N6.C0.D0.R0.S11: RdPtrOffsetTxDq: 06
N0.C0.D0.R0.S16: wrcmd2dqsstartlatency: 04
N2.C1.D0.R0.S09: Total Delay in PI ticks: TxDQ = 982
N4.C0.D1.R0.S11: TxDq : plus1 = 1, minus1 = 0, PI = 58, DB = 1
N6.C0.D0.R0.S12: RdPtrOffsetTxDq: 06
N0.C0.D0.R0.S16: RdPtrOffsetTxDq: 05
N2.C1.D0.R0.S10: Total Delay in PI ticks: TxDQ = 962
N4.C0.D1.R0.S12: TxDqs: plus1 = 1, minus1 = 0, PI = 16, DB = 0
N6.C0.D0.R0.S13: RdPtrOffsetTxDq: 06
N0.C0.D0.R0.S16: RdPtrOffsetTxDqs: 07
N2.C1.D0.R0.S11: Total Delay in PI ticks: TxDQ = 958
N4.C0.D1.R0.S12: TxDq : plus1 = 1, minus1 = 0, PI = 45, DB = 0
N6.C0.D0.R0.S14: RdPtrOffsetTxDq: 06
N0.C0.D0.R0.S16: PiTxDqs: 15
N2.C1.D0.R0.S12: Total Delay in PI ticks: TxDQ = 938
N4.C0.D1.R0.S13: TxDqs: plus1 = 1, minus1 = 0, PI = 45, DB = 0
N6.C0.D0.R0.S15: RdPtrOffsetTxDq: 06
N0.C0.D0.R0.S17: wrcmd2dqsstartlatency: 04
N2.C1.D0.R0.S13: Total Delay in PI ticks: TxDQ = 907
N4.C0.D1.R0.S13: TxDq : plus1 = 1, minus1 = 0, PI = 09, DB = 1
N6.C0.D0.R0.S16: RdPtrOffsetTxDq: 06
N0.C0.D0.R0.S17: RdPtrOffsetTxDq: 05
N2.C1.D0.R0.S14: Total Delay in PI ticks: TxDQ = 920
N4.C0.D1.R0.S14: TxDqs: plus1 = 1, minus1 = 0, PI = 61, DB = 1
N6.C0.D0.R0.S17: RdPtrOffsetTxDq: 06
N0.C0.D0.R0.S17: RdPtrOffsetTxDqs: 06
N2.C1.D0.R0.S15: Total Delay in PI ticks: TxDQ = 934
N4.C0.D1.R0.S14: TxDq : plus1 = 1, minus1 = 0, PI = 27, DB = 0
N6.C0.D0.R0.S00: RdPtrOffsetTxDq: 08
N0.C0.D0.R0.S17: PiTxDqs: 50
N2.C1.D0.R0.S16: Total Delay in PI ticks: TxDQ = 950
N4.C0.D1.R0.S15: TxDqs: plus1 = 0, minus1 = 1, PI = 00, DB = 1
N6.C0.D0.R0.S01: RdPtrOffsetTxDq: 08
N0.C0.D0.R0.S00: RdPtrOffsetTxDq: 07
N2.C1.D0.R0.S17: Total Delay in PI ticks: TxDQ = 919
N4.C0.D1.R0.S15: TxDq : plus1 = 1, minus1 = 0, PI = 31, DB = 0
N6.C0.D0.R0.S02: RdPtrOffsetTxDq: 07
N0.C0.D0.R0.S01: RdPtrOffsetTxDq: 07
N2.C1.D0.R1.S00: wrcmd2dqsstartlatency: 04
N4.C0.D1.R0.S16: TxDqs: plus1 = 1, minus1 = 0, PI = 16, DB = 0
N6.C0.D0.R0.S03: RdPtrOffsetTxDq: 07
N0.C0.D0.R0.S02: RdPtrOffsetTxDq: 06
N2.C1.D0.R1.S00: RdPtrOffsetTxDq: 06
N4.C0.D1.R0.S16: TxDq : plus1 = 1, minus1 = 0, PI = 46, DB = 0
N6.C0.D0.R0.S04: RdPtrOffsetTxDq: 07
N0.C0.D0.R0.S03: RdPtrOffsetTxDq: 06
N2.C1.D0.R1.S00: RdPtrOffsetTxDqs: 07
N4.C0.D1.R0.S17: TxDqs: plus1 = 1, minus1 = 0, PI = 52, DB = 1
N6.C0.D0.R0.S05: RdPtrOffsetTxDq: 07
N0.C0.D0.R0.S04: RdPtrOffsetTxDq: 06
N2.C1.D0.R1.S00: PiTxDqs: 44
N4.C0.D1.R0.S17: TxDq : plus1 = 1, minus1 = 0, PI = 17, DB = 0
N6.C0.D0.R0.S06: RdPtrOffsetTxDq: 07
N0.C0.D0.R0.S05: RdPtrOffsetTxDq: 06
N2.C1.D0.R1.S01: wrcmd2dqsstartlatency: 04
N4.C0.D1.R1.S00: TxDqs: plus1 = 1, minus1 = 0, PI = 57, DB = 1
N6.C0.D0.R0.S07: RdPtrOffsetTxDq: 07
N0.C0.D0.R0.S06: RdPtrOffsetTxDq: 06
N2.C1.D0.R1.S01: RdPtrOffsetTxDq: 05
N4.C0.D1.R1.S00: TxDq : plus1 = 1, minus1 = 0, PI = 24, DB = 0
N6.C0.D0.R0.S08: RdPtrOffsetTxDq: 07
N0.C0.D0.R0.S07: RdPtrOffsetTxDq: 06
N2.C1.D0.R1.S01: RdPtrOffsetTxDqs: 07
N4.C0.D1.R1.S01: TxDqs: plus1 = 1, minus1 = 0, PI = 43, DB = 0
N6.C0.D0.R0.S09: RdPtrOffsetTxDq: 08
N0.C0.D0.R0.S08: RdPtrOffsetTxDq: 06
N2.C1.D0.R1.S01: PiTxDqs: 28
N4.C0.D1.R1.S01: TxDq : plus1 = 1, minus1 = 0, PI = 08, DB = 1
N6.C0.D0.R0.S10: RdPtrOffsetTxDq: 08
N0.C0.D0.R0.S09: RdPtrOffsetTxDq: 07
N2.C1.D0.R1.S02: wrcmd2dqsstartlatency: 04
N4.C0.D1.R1.S02: TxDqs: plus1 = 1, minus1 = 0, PI = 31, DB = 0
N6.C0.D0.R0.S11: RdPtrOffsetTxDq: 07
N0.C0.D0.R0.S10: RdPtrOffsetTxDq: 07
N2.C1.D0.R1.S02: RdPtrOffsetTxDq: 05
N4.C0.D1.R1.S02: TxDq : plus1 = 1, minus1 = 0, PI = 59, DB = 1
N6.C0.D0.R0.S12: RdPtrOffsetTxDq: 07
N0.C0.D0.R0.S11: RdPtrOffsetTxDq: 06
N2.C1.D0.R1.S02: RdPtrOffsetTxDqs: 07
N4.C0.D1.R1.S03: TxDqs: plus1 = 1, minus1 = 0, PI = 14, DB = 1
N6.C0.D0.R0.S13: RdPtrOffsetTxDq: 07
N0.C0.D0.R0.S12: RdPtrOffsetTxDq: 06
N2.C1.D0.R1.S02: PiTxDqs: 20
N4.C0.D1.R1.S03: TxDq : plus1 = 1, minus1 = 0, PI = 41, DB = 0
N6.C0.D0.R0.S14: RdPtrOffsetTxDq: 07
N0.C0.D0.R0.S13: RdPtrOffsetTxDq: 06
N2.C1.D0.R1.S03: wrcmd2dqsstartlatency: 04
N4.C0.D1.R1.S04: TxDqs: plus1 = 1, minus1 = 0, PI = 43, DB = 0
N6.C0.D0.R0.S15: RdPtrOffsetTxDq: 07
N0.C0.D0.R0.S14: RdPtrOffsetTxDq: 06
N2.C1.D0.R1.S03: RdPtrOffsetTxDq: 05
N4.C0.D1.R1.S04: TxDq : plus1 = 1, minus1 = 0, PI = 08, DB = 1
N6.C0.D0.R0.S16: RdPtrOffsetTxDq: 07
N0.C0.D0.R0.S15: RdPtrOffsetTxDq: 06
N2.C1.D0.R1.S03: RdPtrOffsetTxDqs: 07
N4.C0.D1.R1.S05: TxDqs: plus1 = 1, minus1 = 0, PI = 62, DB = 1
N6.C0.D0.R0.S17: RdPtrOffsetTxDq: 07
N0.C0.D0.R0.S16: RdPtrOffsetTxDq: 06
N2.C1.D0.R1.S03: PiTxDqs: 03
N4.C0.D1.R1.S05: TxDq : plus1 = 1, minus1 = 0, PI = 26, DB = 0
N6.C0.D0.R0.S00: Total Delay in PI ticks: TxDQ = 986
N0.C0.D0.R0.S17: RdPtrOffsetTxDq: 06
N2.C1.D0.R1.S04: wrcmd2dqsstartlatency: 04
N4.C0.D1.R1.S06: TxDqs: plus1 = 0, minus1 = 1, PI = 01, DB = 1
N6.C0.D0.R0.S01: Total Delay in PI ticks: TxDQ = 962
N0.C0.D0.R0.S00: RdPtrOffsetTxDq: 08
N2.C1.D0.R1.S04: RdPtrOffsetTxDq: 05
N4.C0.D1.R1.S06: TxDq : plus1 = 1, minus1 = 0, PI = 29, DB = 0
N6.C0.D0.R0.S02: Total Delay in PI ticks: TxDQ = 950
N0.C0.D0.R0.S01: RdPtrOffsetTxDq: 08
N2.C1.D0.R1.S04: RdPtrOffsetTxDqs: 06
N4.C0.D1.R1.S07: TxDqs: plus1 = 1, minus1 = 0, PI = 16, DB = 0
N6.C0.D0.R0.S03: Total Delay in PI ticks: TxDQ = 932
N0.C0.D0.R0.S02: RdPtrOffsetTxDq: 07
N2.C1.D0.R1.S04: PiTxDqs: 36
N4.C0.D1.R1.S07: TxDq : plus1 = 1, minus1 = 0, PI = 46, DB = 0
N6.C0.D0.R0.S04: Total Delay in PI ticks: TxDQ = 902
N0.C0.D0.R0.S03: RdPtrOffsetTxDq: 07
N2.C1.D0.R1.S05: wrcmd2dqsstartlatency: 04
N4.C0.D1.R1.S08: TxDqs: plus1 = 1, minus1 = 0, PI = 52, DB = 1
N6.C0.D0.R0.S05: Total Delay in PI ticks: TxDQ = 918
N0.C0.D0.R0.S04: RdPtrOffsetTxDq: 07
N2.C1.D0.R1.S05: RdPtrOffsetTxDq: 05
N4.C0.D1.R1.S08: TxDq : plus1 = 1, minus1 = 0, PI = 17, DB = 0
N6.C0.D0.R0.S06: Total Delay in PI ticks: TxDQ = 924
N0.C0.D0.R0.S05: RdPtrOffsetTxDq: 07
N2.C1.D0.R1.S05: RdPtrOffsetTxDqs: 06
N4.C0.D1.R1.S09: TxDqs: plus1 = 1, minus1 = 0, PI = 57, DB = 1
N6.C0.D0.R0.S07: Total Delay in PI ticks: TxDQ = 937
N0.C0.D0.R0.S06: RdPtrOffsetTxDq: 07
N2.C1.D0.R1.S05: PiTxDqs: 49
N4.C0.D1.R1.S09: TxDq : plus1 = 1, minus1 = 0, PI = 24, DB = 0
N6.C0.D0.R0.S08: Total Delay in PI ticks: TxDQ = 916
N0.C0.D0.R0.S07: RdPtrOffsetTxDq: 07
N2.C1.D0.R1.S06: wrcmd2dqsstartlatency: 04
N4.C0.D1.R1.S10: TxDqs: plus1 = 1, minus1 = 0, PI = 44, DB = 0
N6.C0.D0.R0.S09: Total Delay in PI ticks: TxDQ = 982
N0.C0.D0.R0.S08: RdPtrOffsetTxDq: 07
N2.C1.D0.R1.S06: RdPtrOffsetTxDq: 05
N4.C0.D1.R1.S10: TxDq : plus1 = 1, minus1 = 0, PI = 09, DB = 1
N6.C0.D0.R0.S10: Total Delay in PI ticks: TxDQ = 960
N0.C0.D0.R0.S09: RdPtrOffsetTxDq: 08
N2.C1.D0.R1.S06: RdPtrOffsetTxDqs: 06
N4.C0.D1.R1.S11: TxDqs: plus1 = 1, minus1 = 0, PI = 31, DB = 0
N6.C0.D0.R0.S11: Total Delay in PI ticks: TxDQ = 950
N0.C0.D0.R0.S10: RdPtrOffsetTxDq: 08
N2.C1.D0.R1.S06: PiTxDqs: 61
N4.C0.D1.R1.S11: TxDq : plus1 = 1, minus1 = 0, PI = 58, DB = 1
N6.C0.D0.R0.S12: Total Delay in PI ticks: TxDQ = 933
N0.C0.D0.R0.S11: RdPtrOffsetTxDq: 07
N2.C1.D0.R1.S07: wrcmd2dqsstartlatency: 04
N4.C0.D1.R1.S12: TxDqs: plus1 = 1, minus1 = 0, PI = 16, DB = 0
N6.C0.D0.R0.S13: Total Delay in PI ticks: TxDQ = 901
N0.C0.D0.R0.S12: RdPtrOffsetTxDq: 07
N2.C1.D0.R1.S07: RdPtrOffsetTxDq: 05
N4.C0.D1.R1.S12: TxDq : plus1 = 1, minus1 = 0, PI = 45, DB = 0
N6.C0.D0.R0.S14: Total Delay in PI ticks: TxDQ = 921
N0.C0.D0.R0.S13: RdPtrOffsetTxDq: 07
N2.C1.D0.R1.S07: RdPtrOffsetTxDqs: 07
N4.C0.D1.R1.S13: TxDqs: plus1 = 1, minus1 = 0, PI = 45, DB = 0
N6.C0.D0.R0.S15: Total Delay in PI ticks: TxDQ = 920
N0.C0.D0.R0.S14: RdPtrOffsetTxDq: 07
N2.C1.D0.R1.S07: PiTxDqs: 15
N4.C0.D1.R1.S13: TxDq : plus1 = 1, minus1 = 0, PI = 09, DB = 1
N6.C0.D0.R0.S16: Total Delay in PI ticks: TxDQ = 938
N0.C0.D0.R0.S15: RdPtrOffsetTxDq: 07
N2.C1.D0.R1.S08: wrcmd2dqsstartlatency: 04
N4.C0.D1.R1.S14: TxDqs: plus1 = 1, minus1 = 0, PI = 61, DB = 1
N6.C0.D0.R0.S17: Total Delay in PI ticks: TxDQ = 916
N0.C0.D0.R0.S16: RdPtrOffsetTxDq: 07
N2.C1.D0.R1.S08: RdPtrOffsetTxDq: 05
N4.C0.D1.R1.S14: TxDq : plus1 = 1, minus1 = 0, PI = 27, DB = 0
N6.C0.D0.R1.S00: wrcmd2dqsstartlatency: 04
N0.C0.D0.R0.S17: RdPtrOffsetTxDq: 07
N2.C1.D0.R1.S08: RdPtrOffsetTxDqs: 06
N4.C0.D1.R1.S15: TxDqs: plus1 = 0, minus1 = 1, PI = 00, DB = 1
N6.C0.D0.R1.S00: RdPtrOffsetTxDq: 06
N0.C0.D0.R0.S00: Total Delay in PI ticks: TxDQ = 983
N2.C1.D0.R1.S08: PiTxDqs: 49
N4.C0.D1.R1.S15: TxDq : plus1 = 1, minus1 = 0, PI = 31, DB = 0
N6.C0.D0.R1.S00: RdPtrOffsetTxDqs: 07
N0.C0.D0.R0.S01: Total Delay in PI ticks: TxDQ = 965
N2.C1.D0.R1.S09: wrcmd2dqsstartlatency: 04
N4.C0.D1.R1.S16: TxDqs: plus1 = 1, minus1 = 0, PI = 16, DB = 0
N6.C0.D0.R1.S00: PiTxDqs: 48
N0.C0.D0.R0.S02: Total Delay in PI ticks: TxDQ = 954
N2.C1.D0.R1.S09: RdPtrOffsetTxDq: 06
N4.C0.D1.R1.S16: TxDq : plus1 = 1, minus1 = 0, PI = 46, DB = 0
N6.C0.D0.R1.S01: wrcmd2dqsstartlatency: 04
N0.C0.D0.R0.S03: Total Delay in PI ticks: TxDQ = 935
N2.C1.D0.R1.S09: RdPtrOffsetTxDqs: 07
N4.C0.D1.R1.S17: TxDqs: plus1 = 1, minus1 = 0, PI = 52, DB = 1
N6.C0.D0.R1.S01: RdPtrOffsetTxDq: 05
N0.C0.D0.R0.S04: Total Delay in PI ticks: TxDQ = 906
N2.C1.D0.R1.S09: PiTxDqs: 43
N4.C0.D1.R1.S17: TxDq : plus1 = 1, minus1 = 0, PI = 17, DB = 0
N6.C0.D0.R1.S01: RdPtrOffsetTxDqs: 07
N0.C0.D0.R0.S05: Total Delay in PI ticks: TxDQ = 921
N2.C1.D0.R1.S10: wrcmd2dqsstartlatency: 04
END_DATA_TX_DQ
N6.C0.D0.R1.S01: PiTxDqs: 26
N0.C0.D0.R0.S06: Total Delay in PI ticks: TxDQ = 923
N2.C1.D0.R1.S10: RdPtrOffsetTxDq: 05
N4.C1.D0.R0.S00: wrcmd2dqsstartlatency: 04
N6.C0.D0.R1.S02: wrcmd2dqsstartlatency: 04
N0.C0.D0.R0.S07: Total Delay in PI ticks: TxDQ = 940
N2.C1.D0.R1.S10: RdPtrOffsetTxDqs: 07
N4.C1.D0.R0.S00: RdPtrOffsetTxDq: 06
N6.C0.D0.R1.S02: RdPtrOffsetTxDq: 05
N0.C0.D0.R0.S08: Total Delay in PI ticks: TxDQ = 915
N2.C1.D0.R1.S10: PiTxDqs: 28
N4.C1.D0.R0.S00: RdPtrOffsetTxDqs: 07
N6.C0.D0.R1.S02: RdPtrOffsetTxDqs: 07
N0.C0.D0.R0.S09: Total Delay in PI ticks: TxDQ = 986
N2.C1.D0.R1.S11: wrcmd2dqsstartlatency: 04
N4.C1.D0.R0.S00: PiTxDqs: 58
N6.C0.D0.R1.S02: PiTxDqs: 16
N0.C0.D0.R0.S10: Total Delay in PI ticks: TxDQ = 964
N2.C1.D0.R1.S11: RdPtrOffsetTxDq: 05
N4.C1.D0.R0.S01: wrcmd2dqsstartlatency: 04
N6.C0.D0.R1.S03: wrcmd2dqsstartlatency: 04
N0.C0.D0.R0.S11: Total Delay in PI ticks: TxDQ = 954
N2.C1.D0.R1.S11: RdPtrOffsetTxDqs: 07
N4.C1.D0.R0.S01: RdPtrOffsetTxDq: 06
N6.C0.D0.R1.S03: RdPtrOffsetTxDq: 05
N0.C0.D0.R0.S12: Total Delay in PI ticks: TxDQ = 937
N2.C1.D0.R1.S11: PiTxDqs: 19
N4.C1.D0.R0.S01: RdPtrOffsetTxDqs: 07
N6.C0.D0.R1.S03: RdPtrOffsetTxDqs: 06
N0.C0.D0.R0.S13: Total Delay in PI ticks: TxDQ = 906
N2.C1.D0.R1.S12: wrcmd2dqsstartlatency: 04
N4.C1.D0.R0.S01: PiTxDqs: 41
N6.C0.D0.R1.S03: PiTxDqs: 63
N0.C0.D0.R0.S14: Total Delay in PI ticks: TxDQ = 920
N2.C1.D0.R1.S12: RdPtrOffsetTxDq: 05
N4.C1.D0.R0.S02: wrcmd2dqsstartlatency: 04
N6.C0.D0.R1.S04: wrcmd2dqsstartlatency: 04
N0.C0.D0.R0.S15: Total Delay in PI ticks: TxDQ = 923
N2.C1.D0.R1.S12: RdPtrOffsetTxDqs: 07
N4.C1.D0.R0.S02: RdPtrOffsetTxDq: 05
N6.C0.D0.R1.S04: RdPtrOffsetTxDq: 04
N0.C0.D0.R0.S16: Total Delay in PI ticks: TxDQ = 942
N2.C1.D0.R1.S12: PiTxDqs: 04
N4.C1.D0.R0.S02: RdPtrOffsetTxDqs: 07
N6.C0.D0.R1.S04: RdPtrOffsetTxDqs: 06
N0.C0.D0.R0.S17: Total Delay in PI ticks: TxDQ = 912
N2.C1.D0.R1.S13: wrcmd2dqsstartlatency: 04
N4.C1.D0.R0.S02: PiTxDqs: 34
N6.C0.D0.R1.S04: PiTxDqs: 30
N0.C0.D0.R1.S00: wrcmd2dqsstartlatency: 04
N2.C1.D0.R1.S13: RdPtrOffsetTxDq: 05
N4.C1.D0.R0.S03: wrcmd2dqsstartlatency: 04
N6.C0.D0.R1.S05: wrcmd2dqsstartlatency: 04
N0.C0.D0.R1.S00: RdPtrOffsetTxDq: 06
N2.C1.D0.R1.S13: RdPtrOffsetTxDqs: 06
N4.C1.D0.R0.S03: RdPtrOffsetTxDq: 05
N6.C0.D0.R1.S05: RdPtrOffsetTxDq: 05
N0.C0.D0.R1.S00: RdPtrOffsetTxDqs: 07
N2.C1.D0.R1.S13: PiTxDqs: 34
N4.C1.D0.R0.S03: RdPtrOffsetTxDqs: 07
N6.C0.D0.R1.S05: RdPtrOffsetTxDqs: 06
N0.C0.D0.R1.S00: PiTxDqs: 50
N2.C1.D0.R1.S14: wrcmd2dqsstartlatency: 04
N4.C1.D0.R0.S03: PiTxDqs: 21
N6.C0.D0.R1.S05: PiTxDqs: 49
N0.C0.D0.R1.S01: wrcmd2dqsstartlatency: 04
N2.C1.D0.R1.S14: RdPtrOffsetTxDq: 05
N4.C1.D0.R0.S04: wrcmd2dqsstartlatency: 04
N6.C0.D0.R1.S06: wrcmd2dqsstartlatency: 04
N0.C0.D0.R1.S01: RdPtrOffsetTxDq: 05
N2.C1.D0.R1.S14: RdPtrOffsetTxDqs: 06
N4.C1.D0.R0.S04: RdPtrOffsetTxDq: 05
N6.C0.D0.R1.S06: RdPtrOffsetTxDq: 05
N0.C0.D0.R1.S01: RdPtrOffsetTxDqs: 07
N2.C1.D0.R1.S14: PiTxDqs: 49
N4.C1.D0.R0.S04: RdPtrOffsetTxDqs: 06
N6.C0.D0.R1.S06: RdPtrOffsetTxDqs: 06
N0.C0.D0.R1.S01: PiTxDqs: 32
N2.C1.D0.R1.S15: wrcmd2dqsstartlatency: 04
N4.C1.D0.R0.S04: PiTxDqs: 50
N6.C0.D0.R1.S06: PiTxDqs: 51
N0.C0.D0.R1.S02: wrcmd2dqsstartlatency: 04
N2.C1.D0.R1.S15: RdPtrOffsetTxDq: 05
N4.C1.D0.R0.S05: wrcmd2dqsstartlatency: 04
N6.C0.D0.R1.S07: wrcmd2dqsstartlatency: 04
N0.C0.D0.R1.S02: RdPtrOffsetTxDq: 05
N2.C1.D0.R1.S15: RdPtrOffsetTxDqs: 06
N4.C1.D0.R0.S05: RdPtrOffsetTxDq: 05
N6.C0.D0.R1.S07: RdPtrOffsetTxDq: 05
N0.C0.D0.R1.S02: RdPtrOffsetTxDqs: 07
N2.C1.D0.R1.S15: PiTxDqs: 63
N4.C1.D0.R0.S05: RdPtrOffsetTxDqs: 06
N6.C0.D0.R1.S07: RdPtrOffsetTxDqs: 07
N0.C0.D0.R1.S02: PiTxDqs: 20
N2.C1.D0.R1.S16: wrcmd2dqsstartlatency: 04
N4.C1.D0.R0.S05: PiTxDqs: 59
N6.C0.D0.R1.S07: PiTxDqs: 04
N0.C0.D0.R1.S03: wrcmd2dqsstartlatency: 04
N2.C1.D0.R1.S16: RdPtrOffsetTxDq: 05
N4.C1.D0.R0.S06: wrcmd2dqsstartlatency: 04
N6.C0.D0.R1.S08: wrcmd2dqsstartlatency: 04
N0.C0.D0.R1.S03: RdPtrOffsetTxDq: 05
N2.C1.D0.R1.S16: RdPtrOffsetTxDqs: 07
N4.C1.D0.R0.S06: RdPtrOffsetTxDq: 05
N6.C0.D0.R1.S08: RdPtrOffsetTxDq: 05
N0.C0.D0.R1.S03: RdPtrOffsetTxDqs: 07
N2.C1.D0.R1.S16: PiTxDqs: 15
N4.C1.D0.R0.S06: RdPtrOffsetTxDqs: 07
N6.C0.D0.R1.S08: RdPtrOffsetTxDqs: 06
N0.C0.D0.R1.S03: PiTxDqs: 02
N2.C1.D0.R1.S17: wrcmd2dqsstartlatency: 04
N4.C1.D0.R0.S06: PiTxDqs: 14
N6.C0.D0.R1.S08: PiTxDqs: 41
N0.C0.D0.R1.S04: wrcmd2dqsstartlatency: 04
N2.C1.D0.R1.S17: RdPtrOffsetTxDq: 05
N4.C1.D0.R0.S07: wrcmd2dqsstartlatency: 04
N6.C0.D0.R1.S09: wrcmd2dqsstartlatency: 04
N0.C0.D0.R1.S04: RdPtrOffsetTxDq: 05
N2.C1.D0.R1.S17: RdPtrOffsetTxDqs: 06
N4.C1.D0.R0.S07: RdPtrOffsetTxDq: 05
N6.C0.D0.R1.S09: RdPtrOffsetTxDq: 06
N0.C0.D0.R1.S04: RdPtrOffsetTxDqs: 06
N2.C1.D0.R1.S17: PiTxDqs: 50
N4.C1.D0.R0.S07: RdPtrOffsetTxDqs: 07
N6.C0.D0.R1.S09: RdPtrOffsetTxDqs: 07
N0.C0.D0.R1.S04: PiTxDqs: 35
N2.C1.D0.R1.S00: RdPtrOffsetTxDq: 07
N4.C1.D0.R0.S07: PiTxDqs: 26
N6.C0.D0.R1.S09: PiTxDqs: 45
N0.C0.D0.R1.S05: wrcmd2dqsstartlatency: 04
N2.C1.D0.R1.S01: RdPtrOffsetTxDq: 06
N4.C1.D0.R0.S08: wrcmd2dqsstartlatency: 04
N6.C0.D0.R1.S10: wrcmd2dqsstartlatency: 04
N0.C0.D0.R1.S05: RdPtrOffsetTxDq: 05
N2.C1.D0.R1.S02: RdPtrOffsetTxDq: 06
N4.C1.D0.R0.S08: RdPtrOffsetTxDq: 05
N6.C0.D0.R1.S10: RdPtrOffsetTxDq: 05
N0.C0.D0.R1.S05: RdPtrOffsetTxDqs: 06
N2.C1.D0.R1.S03: RdPtrOffsetTxDq: 06
N4.C1.D0.R0.S08: RdPtrOffsetTxDqs: 06
N6.C0.D0.R1.S10: RdPtrOffsetTxDqs: 07
N0.C0.D0.R1.S05: PiTxDqs: 51
N2.C1.D0.R1.S04: RdPtrOffsetTxDq: 06
N4.C1.D0.R0.S08: PiTxDqs: 63
N6.C0.D0.R1.S10: PiTxDqs: 28
N0.C0.D0.R1.S06: wrcmd2dqsstartlatency: 04
N2.C1.D0.R1.S05: RdPtrOffsetTxDq: 06
N4.C1.D0.R0.S09: wrcmd2dqsstartlatency: 04
N6.C0.D0.R1.S11: wrcmd2dqsstartlatency: 04
N0.C0.D0.R1.S06: RdPtrOffsetTxDq: 05
N2.C1.D0.R1.S06: RdPtrOffsetTxDq: 06
N4.C1.D0.R0.S09: RdPtrOffsetTxDq: 06
N6.C0.D0.R1.S11: RdPtrOffsetTxDq: 05
N0.C0.D0.R1.S06: RdPtrOffsetTxDqs: 06
N2.C1.D0.R1.S07: RdPtrOffsetTxDq: 06
N4.C1.D0.R0.S09: RdPtrOffsetTxDqs: 07
N6.C0.D0.R1.S11: RdPtrOffsetTxDqs: 07
N0.C0.D0.R1.S06: PiTxDqs: 53
N2.C1.D0.R1.S08: RdPtrOffsetTxDq: 06
N4.C1.D0.R0.S09: PiTxDqs: 60
N6.C0.D0.R1.S11: PiTxDqs: 15
N0.C0.D0.R1.S07: wrcmd2dqsstartlatency: 04
N2.C1.D0.R1.S09: RdPtrOffsetTxDq: 07
N4.C1.D0.R0.S10: wrcmd2dqsstartlatency: 04
N6.C0.D0.R1.S12: wrcmd2dqsstartlatency: 04
N0.C0.D0.R1.S07: RdPtrOffsetTxDq: 05
N2.C1.D0.R1.S10: RdPtrOffsetTxDq: 06
N4.C1.D0.R0.S10: RdPtrOffsetTxDq: 06
N6.C0.D0.R1.S12: RdPtrOffsetTxDq: 05
N0.C0.D0.R1.S07: RdPtrOffsetTxDqs: 07
N2.C1.D0.R1.S11: RdPtrOffsetTxDq: 06
N4.C1.D0.R0.S10: RdPtrOffsetTxDqs: 07
N6.C0.D0.R1.S12: RdPtrOffsetTxDqs: 07
N0.C0.D0.R1.S07: PiTxDqs: 08
N2.C1.D0.R1.S12: RdPtrOffsetTxDq: 06
N4.C1.D0.R0.S10: PiTxDqs: 43
N6.C0.D0.R1.S12: PiTxDqs: 03
N0.C0.D0.R1.S08: wrcmd2dqsstartlatency: 04
N2.C1.D0.R1.S13: RdPtrOffsetTxDq: 06
N4.C1.D0.R0.S11: wrcmd2dqsstartlatency: 04
N6.C0.D0.R1.S13: wrcmd2dqsstartlatency: 04
N0.C0.D0.R1.S08: RdPtrOffsetTxDq: 05
N2.C1.D0.R1.S14: RdPtrOffsetTxDq: 06
N4.C1.D0.R0.S11: RdPtrOffsetTxDq: 06
N6.C0.D0.R1.S13: RdPtrOffsetTxDq: 04
N0.C0.D0.R1.S08: RdPtrOffsetTxDqs: 06
N2.C1.D0.R1.S15: RdPtrOffsetTxDq: 06
N4.C1.D0.R0.S11: RdPtrOffsetTxDqs: 07
N6.C0.D0.R1.S13: RdPtrOffsetTxDqs: 06
N0.C0.D0.R1.S08: PiTxDqs: 43
N2.C1.D0.R1.S16: RdPtrOffsetTxDq: 06
N4.C1.D0.R0.S11: PiTxDqs: 36
N6.C0.D0.R1.S13: PiTxDqs: 31
N0.C0.D0.R1.S09: wrcmd2dqsstartlatency: 04
N2.C1.D0.R1.S17: RdPtrOffsetTxDq: 06
N4.C1.D0.R0.S12: wrcmd2dqsstartlatency: 04
N6.C0.D0.R1.S14: wrcmd2dqsstartlatency: 04
N0.C0.D0.R1.S09: RdPtrOffsetTxDq: 06
N2.C1.D0.R1.S00: RdPtrOffsetTxDq: 08
N4.C1.D0.R0.S12: RdPtrOffsetTxDq: 05
N6.C0.D0.R1.S14: RdPtrOffsetTxDq: 05
N0.C0.D0.R1.S09: RdPtrOffsetTxDqs: 07
N2.C1.D0.R1.S01: RdPtrOffsetTxDq: 07
N4.C1.D0.R0.S12: RdPtrOffsetTxDqs: 07
N6.C0.D0.R1.S14: RdPtrOffsetTxDqs: 06
N0.C0.D0.R1.S09: PiTxDqs: 48
N2.C1.D0.R1.S02: RdPtrOffsetTxDq: 07
N4.C1.D0.R0.S12: PiTxDqs: 18
N6.C0.D0.R1.S14: PiTxDqs: 48
N0.C0.D0.R1.S10: wrcmd2dqsstartlatency: 04
N2.C1.D0.R1.S03: RdPtrOffsetTxDq: 07
N4.C1.D0.R0.S13: wrcmd2dqsstartlatency: 04
N6.C0.D0.R1.S15: wrcmd2dqsstartlatency: 04
N0.C0.D0.R1.S10: RdPtrOffsetTxDq: 05
N2.C1.D0.R1.S04: RdPtrOffsetTxDq: 07
N4.C1.D0.R0.S13: RdPtrOffsetTxDq: 05
N6.C0.D0.R1.S15: RdPtrOffsetTxDq: 05
N0.C0.D0.R1.S10: RdPtrOffsetTxDqs: 07
N2.C1.D0.R1.S05: RdPtrOffsetTxDq: 07
N4.C1.D0.R0.S13: RdPtrOffsetTxDqs: 06
N6.C0.D0.R1.S15: RdPtrOffsetTxDqs: 06
N0.C0.D0.R1.S10: PiTxDqs: 33
N2.C1.D0.R1.S06: RdPtrOffsetTxDq: 07
N4.C1.D0.R0.S13: PiTxDqs: 50
N6.C0.D0.R1.S15: PiTxDqs: 51
N0.C0.D0.R1.S11: wrcmd2dqsstartlatency: 04
N2.C1.D0.R1.S07: RdPtrOffsetTxDq: 07
N4.C1.D0.R0.S14: wrcmd2dqsstartlatency: 04
N6.C0.D0.R1.S16: wrcmd2dqsstartlatency: 04
N0.C0.D0.R1.S11: RdPtrOffsetTxDq: 05
N2.C1.D0.R1.S08: RdPtrOffsetTxDq: 07
N4.C1.D0.R0.S14: RdPtrOffsetTxDq: 05
N6.C0.D0.R1.S16: RdPtrOffsetTxDq: 05
N0.C0.D0.R1.S11: RdPtrOffsetTxDqs: 07
N2.C1.D0.R1.S09: RdPtrOffsetTxDq: 08
N4.C1.D0.R0.S14: RdPtrOffsetTxDqs: 06
N6.C0.D0.R1.S16: RdPtrOffsetTxDqs: 07
N0.C0.D0.R1.S11: PiTxDqs: 20
N2.C1.D0.R1.S10: RdPtrOffsetTxDq: 07
N4.C1.D0.R0.S14: PiTxDqs: 61
N6.C0.D0.R1.S16: PiTxDqs: 05
N0.C0.D0.R1.S12: wrcmd2dqsstartlatency: 04
N2.C1.D0.R1.S11: RdPtrOffsetTxDq: 07
N4.C1.D0.R0.S15: wrcmd2dqsstartlatency: 04
N6.C0.D0.R1.S17: wrcmd2dqsstartlatency: 04
N0.C0.D0.R1.S12: RdPtrOffsetTxDq: 05
N2.C1.D0.R1.S12: RdPtrOffsetTxDq: 07
N4.C1.D0.R0.S15: RdPtrOffsetTxDq: 05
N6.C0.D0.R1.S17: RdPtrOffsetTxDq: 05
N0.C0.D0.R1.S12: RdPtrOffsetTxDqs: 07
N2.C1.D0.R1.S13: RdPtrOffsetTxDq: 07
N4.C1.D0.R0.S15: RdPtrOffsetTxDqs: 07
N6.C0.D0.R1.S17: RdPtrOffsetTxDqs: 06
N0.C0.D0.R1.S12: PiTxDqs: 06
N2.C1.D0.R1.S14: RdPtrOffsetTxDq: 07
N4.C1.D0.R0.S15: PiTxDqs: 11
N6.C0.D0.R1.S17: PiTxDqs: 41
N0.C0.D0.R1.S13: wrcmd2dqsstartlatency: 04
N2.C1.D0.R1.S15: RdPtrOffsetTxDq: 07
N4.C1.D0.R0.S16: wrcmd2dqsstartlatency: 04
N6.C0.D0.R1.S00: RdPtrOffsetTxDq: 07
N0.C0.D0.R1.S13: RdPtrOffsetTxDq: 05
N2.C1.D0.R1.S16: RdPtrOffsetTxDq: 07
N4.C1.D0.R0.S16: RdPtrOffsetTxDq: 05
N6.C0.D0.R1.S01: RdPtrOffsetTxDq: 06
N0.C0.D0.R1.S13: RdPtrOffsetTxDqs: 06
N2.C1.D0.R1.S17: RdPtrOffsetTxDq: 07
N4.C1.D0.R0.S16: RdPtrOffsetTxDqs: 07
N6.C0.D0.R1.S02: RdPtrOffsetTxDq: 06
N0.C0.D0.R1.S13: PiTxDqs: 37
N2.C1.D0.R1.S00: Total Delay in PI ticks: TxDQ = 975
N4.C1.D0.R0.S16: PiTxDqs: 26
N6.C0.D0.R1.S03: RdPtrOffsetTxDq: 06
N0.C0.D0.R1.S14: wrcmd2dqsstartlatency: 04
N2.C1.D0.R1.S01: Total Delay in PI ticks: TxDQ = 955
N4.C1.D0.R0.S17: wrcmd2dqsstartlatency: 04
N6.C0.D0.R1.S04: RdPtrOffsetTxDq: 05
N0.C0.D0.R1.S14: RdPtrOffsetTxDq: 05
N2.C1.D0.R1.S02: Total Delay in PI ticks: TxDQ = 948
N4.C1.D0.R0.S17: RdPtrOffsetTxDq: 05
N6.C0.D0.R1.S05: RdPtrOffsetTxDq: 06
N0.C0.D0.R1.S14: RdPtrOffsetTxDqs: 06
N2.C1.D0.R1.S03: Total Delay in PI ticks: TxDQ = 932
N4.C1.D0.R0.S17: RdPtrOffsetTxDqs: 07
N6.C0.D0.R1.S06: RdPtrOffsetTxDq: 06
N0.C0.D0.R1.S14: PiTxDqs: 53
N2.C1.D0.R1.S04: Total Delay in PI ticks: TxDQ = 900
N4.C1.D0.R0.S17: PiTxDqs: 01
N6.C0.D0.R1.S07: RdPtrOffsetTxDq: 06
N0.C0.D0.R1.S15: wrcmd2dqsstartlatency: 04
N2.C1.D0.R1.S05: Total Delay in PI ticks: TxDQ = 912
N4.C1.D0.R0.S00: RdPtrOffsetTxDq: 07
N6.C0.D0.R1.S08: RdPtrOffsetTxDq: 06
N0.C0.D0.R1.S15: RdPtrOffsetTxDq: 05
N2.C1.D0.R1.S06: Total Delay in PI ticks: TxDQ = 925
N4.C1.D0.R0.S01: RdPtrOffsetTxDq: 07
N6.C0.D0.R1.S09: RdPtrOffsetTxDq: 07
N0.C0.D0.R1.S15: RdPtrOffsetTxDqs: 06
N2.C1.D0.R1.S07: Total Delay in PI ticks: TxDQ = 941
N4.C1.D0.R0.S02: RdPtrOffsetTxDq: 06
N6.C0.D0.R1.S10: RdPtrOffsetTxDq: 06
N0.C0.D0.R1.S15: PiTxDqs: 56
N2.C1.D0.R1.S08: Total Delay in PI ticks: TxDQ = 912
N4.C1.D0.R0.S03: RdPtrOffsetTxDq: 06
N6.C0.D0.R1.S11: RdPtrOffsetTxDq: 06
N0.C0.D0.R1.S16: wrcmd2dqsstartlatency: 04
N2.C1.D0.R1.S09: Total Delay in PI ticks: TxDQ = 972
N4.C1.D0.R0.S04: RdPtrOffsetTxDq: 06
N6.C0.D0.R1.S12: RdPtrOffsetTxDq: 06
N0.C0.D0.R1.S16: RdPtrOffsetTxDq: 05
N2.C1.D0.R1.S10: Total Delay in PI ticks: TxDQ = 956
N4.C1.D0.R0.S05: RdPtrOffsetTxDq: 06
N6.C0.D0.R1.S13: RdPtrOffsetTxDq: 05
N0.C0.D0.R1.S16: RdPtrOffsetTxDqs: 07
N2.C1.D0.R1.S11: Total Delay in PI ticks: TxDQ = 950
N4.C1.D0.R0.S06: RdPtrOffsetTxDq: 06
N6.C0.D0.R1.S14: RdPtrOffsetTxDq: 06
N0.C0.D0.R1.S16: PiTxDqs: 08
N2.C1.D0.R1.S12: Total Delay in PI ticks: TxDQ = 933
N4.C1.D0.R0.S07: RdPtrOffsetTxDq: 06
N6.C0.D0.R1.S15: RdPtrOffsetTxDq: 06
N0.C0.D0.R1.S17: wrcmd2dqsstartlatency: 04
N2.C1.D0.R1.S13: Total Delay in PI ticks: TxDQ = 900
N4.C1.D0.R0.S08: RdPtrOffsetTxDq: 06
N6.C0.D0.R1.S16: RdPtrOffsetTxDq: 06
N0.C0.D0.R1.S17: RdPtrOffsetTxDq: 05
N2.C1.D0.R1.S14: Total Delay in PI ticks: TxDQ = 914
N4.C1.D0.R0.S09: RdPtrOffsetTxDq: 07
N6.C0.D0.R1.S17: RdPtrOffsetTxDq: 06
N0.C0.D0.R1.S17: RdPtrOffsetTxDqs: 06
N2.C1.D0.R1.S15: Total Delay in PI ticks: TxDQ = 928
N4.C1.D0.R0.S10: RdPtrOffsetTxDq: 07
N6.C0.D0.R1.S00: RdPtrOffsetTxDq: 08
N0.C0.D0.R1.S17: PiTxDqs: 43
N2.C1.D0.R1.S16: Total Delay in PI ticks: TxDQ = 942
N4.C1.D0.R0.S11: RdPtrOffsetTxDq: 07
N6.C0.D0.R1.S01: RdPtrOffsetTxDq: 07
N0.C0.D0.R1.S00: RdPtrOffsetTxDq: 07
N2.C1.D0.R1.S17: Total Delay in PI ticks: TxDQ = 915
N4.C1.D0.R0.S12: RdPtrOffsetTxDq: 06
N6.C0.D0.R1.S02: RdPtrOffsetTxDq: 07
N0.C0.D0.R1.S01: RdPtrOffsetTxDq: 06
N2.C1.D1.R0.S00: wrcmd2dqsstartlatency: 04
N4.C1.D0.R0.S13: RdPtrOffsetTxDq: 06
N6.C0.D0.R1.S03: RdPtrOffsetTxDq: 07
N0.C0.D0.R1.S02: RdPtrOffsetTxDq: 06
N2.C1.D1.R0.S00: RdPtrOffsetTxDq: 06
N4.C1.D0.R0.S14: RdPtrOffsetTxDq: 06
N6.C0.D0.R1.S04: RdPtrOffsetTxDq: 06
N0.C0.D0.R1.S03: RdPtrOffsetTxDq: 06
N2.C1.D1.R0.S00: RdPtrOffsetTxDqs: 07
N4.C1.D0.R0.S15: RdPtrOffsetTxDq: 06
N6.C0.D0.R1.S05: RdPtrOffsetTxDq: 07
N0.C0.D0.R1.S04: RdPtrOffsetTxDq: 06
N2.C1.D1.R0.S00: PiTxDqs: 56
N4.C1.D0.R0.S16: RdPtrOffsetTxDq: 06
N6.C0.D0.R1.S06: RdPtrOffsetTxDq: 07
N0.C0.D0.R1.S05: RdPtrOffsetTxDq: 06
N2.C1.D1.R0.S01: wrcmd2dqsstartlatency: 04
N4.C1.D0.R0.S17: RdPtrOffsetTxDq: 06
N6.C0.D0.R1.S07: RdPtrOffsetTxDq: 07
N0.C0.D0.R1.S06: RdPtrOffsetTxDq: 06
N2.C1.D1.R0.S01: RdPtrOffsetTxDq: 06
N4.C1.D0.R0.S00: RdPtrOffsetTxDq: 08
N6.C0.D0.R1.S08: RdPtrOffsetTxDq: 07
N0.C0.D0.R1.S07: RdPtrOffsetTxDq: 06
N2.C1.D1.R0.S01: RdPtrOffsetTxDqs: 07
N4.C1.D0.R0.S01: RdPtrOffsetTxDq: 08
N6.C0.D0.R1.S09: RdPtrOffsetTxDq: 08
N0.C0.D0.R1.S08: RdPtrOffsetTxDq: 06
N2.C1.D1.R0.S01: PiTxDqs: 41
N4.C1.D0.R0.S02: RdPtrOffsetTxDq: 07
N6.C0.D0.R1.S10: RdPtrOffsetTxDq: 07
N0.C0.D0.R1.S09: RdPtrOffsetTxDq: 07
N2.C1.D1.R0.S02: wrcmd2dqsstartlatency: 04
N4.C1.D0.R0.S03: RdPtrOffsetTxDq: 07
N6.C0.D0.R1.S11: RdPtrOffsetTxDq: 07
N0.C0.D0.R1.S10: RdPtrOffsetTxDq: 06
N2.C1.D1.R0.S02: RdPtrOffsetTxDq: 05
N4.C1.D0.R0.S04: RdPtrOffsetTxDq: 07
N6.C0.D0.R1.S12: RdPtrOffsetTxDq: 07
N0.C0.D0.R1.S11: RdPtrOffsetTxDq: 06
N2.C1.D1.R0.S02: RdPtrOffsetTxDqs: 07
N4.C1.D0.R0.S05: RdPtrOffsetTxDq: 07
N6.C0.D0.R1.S13: RdPtrOffsetTxDq: 06
N0.C0.D0.R1.S12: RdPtrOffsetTxDq: 06
N2.C1.D1.R0.S02: PiTxDqs: 33
N4.C1.D0.R0.S06: RdPtrOffsetTxDq: 07
N6.C0.D0.R1.S14: RdPtrOffsetTxDq: 07
N0.C0.D0.R1.S13: RdPtrOffsetTxDq: 06
N2.C1.D1.R0.S03: wrcmd2dqsstartlatency: 04
N4.C1.D0.R0.S07: RdPtrOffsetTxDq: 07
N6.C0.D0.R1.S15: RdPtrOffsetTxDq: 07
N0.C0.D0.R1.S14: RdPtrOffsetTxDq: 06
N2.C1.D1.R0.S03: RdPtrOffsetTxDq: 05
N4.C1.D0.R0.S08: RdPtrOffsetTxDq: 07
N6.C0.D0.R1.S16: RdPtrOffsetTxDq: 07
N0.C0.D0.R1.S15: RdPtrOffsetTxDq: 06
N2.C1.D1.R0.S03: RdPtrOffsetTxDqs: 07
N4.C1.D0.R0.S09: RdPtrOffsetTxDq: 08
N6.C0.D0.R1.S17: RdPtrOffsetTxDq: 07
N0.C0.D0.R1.S16: RdPtrOffsetTxDq: 06
N2.C1.D1.R0.S03: PiTxDqs: 15
N4.C1.D0.R0.S10: RdPtrOffsetTxDq: 08
N6.C0.D0.R1.S00: Total Delay in PI ticks: TxDQ = 979
N0.C0.D0.R1.S17: RdPtrOffsetTxDq: 06
N2.C1.D1.R0.S04: wrcmd2dqsstartlatency: 04
N4.C1.D0.R0.S11: RdPtrOffsetTxDq: 08
N6.C0.D0.R1.S01: Total Delay in PI ticks: TxDQ = 954
N0.C0.D0.R1.S00: RdPtrOffsetTxDq: 08
N2.C1.D1.R0.S04: RdPtrOffsetTxDq: 05
N4.C1.D0.R0.S12: RdPtrOffsetTxDq: 07
N6.C0.D0.R1.S02: Total Delay in PI ticks: TxDQ = 944
N0.C0.D0.R1.S01: RdPtrOffsetTxDq: 07
N2.C1.D1.R0.S04: RdPtrOffsetTxDqs: 06
N4.C1.D0.R0.S13: RdPtrOffsetTxDq: 07
N6.C0.D0.R1.S03: Total Delay in PI ticks: TxDQ = 927
N0.C0.D0.R1.S02: RdPtrOffsetTxDq: 07
N2.C1.D1.R0.S04: PiTxDqs: 48
N4.C1.D0.R0.S14: RdPtrOffsetTxDq: 07
N6.C0.D0.R1.S04: Total Delay in PI ticks: TxDQ = 895
N0.C0.D0.R1.S03: RdPtrOffsetTxDq: 07
N2.C1.D1.R0.S05: wrcmd2dqsstartlatency: 04
N4.C1.D0.R0.S15: RdPtrOffsetTxDq: 07
N6.C0.D0.R1.S05: Total Delay in PI ticks: TxDQ = 912
N0.C0.D0.R1.S04: RdPtrOffsetTxDq: 07
N2.C1.D1.R0.S05: RdPtrOffsetTxDq: 05
N4.C1.D0.R0.S16: RdPtrOffsetTxDq: 07
N6.C0.D0.R1.S06: Total Delay in PI ticks: TxDQ = 916
N0.C0.D0.R1.S05: RdPtrOffsetTxDq: 07
N2.C1.D1.R0.S05: RdPtrOffsetTxDqs: 06
N4.C1.D0.R0.S17: RdPtrOffsetTxDq: 07
N6.C0.D0.R1.S07: Total Delay in PI ticks: TxDQ = 930
N0.C0.D0.R1.S06: RdPtrOffsetTxDq: 07
N2.C1.D1.R0.S05: PiTxDqs: 63
N4.C1.D0.R0.S00: Total Delay in PI ticks: TxDQ = 986
N6.C0.D0.R1.S08: Total Delay in PI ticks: TxDQ = 906
N0.C0.D0.R1.S07: RdPtrOffsetTxDq: 07
N2.C1.D1.R0.S06: wrcmd2dqsstartlatency: 04
N4.C1.D0.R0.S01: Total Delay in PI ticks: TxDQ = 968
N6.C0.D0.R1.S09: Total Delay in PI ticks: TxDQ = 973
N0.C0.D0.R1.S08: RdPtrOffsetTxDq: 07
N2.C1.D1.R0.S06: RdPtrOffsetTxDq: 05
N4.C1.D0.R0.S02: Total Delay in PI ticks: TxDQ = 960
N6.C0.D0.R1.S10: Total Delay in PI ticks: TxDQ = 955
N0.C0.D0.R1.S09: RdPtrOffsetTxDq: 08
N2.C1.D1.R0.S06: RdPtrOffsetTxDqs: 07
N4.C1.D0.R0.S03: Total Delay in PI ticks: TxDQ = 947
N6.C0.D0.R1.S11: Total Delay in PI ticks: TxDQ = 943
N0.C0.D0.R1.S10: RdPtrOffsetTxDq: 07
N2.C1.D1.R0.S06: PiTxDqs: 10
N4.C1.D0.R0.S04: Total Delay in PI ticks: TxDQ = 912
N6.C0.D0.R1.S12: Total Delay in PI ticks: TxDQ = 931
N0.C0.D0.R1.S11: RdPtrOffsetTxDq: 07
N2.C1.D1.R0.S07: wrcmd2dqsstartlatency: 04
N4.C1.D0.R0.S05: Total Delay in PI ticks: TxDQ = 922
N6.C0.D0.R1.S13: Total Delay in PI ticks: TxDQ = 896
N0.C0.D0.R1.S12: RdPtrOffsetTxDq: 07
N2.C1.D1.R0.S07: RdPtrOffsetTxDq: 05
N4.C1.D0.R0.S06: Total Delay in PI ticks: TxDQ = 941
N6.C0.D0.R1.S14: Total Delay in PI ticks: TxDQ = 912
N0.C0.D0.R1.S13: RdPtrOffsetTxDq: 07
N2.C1.D1.R0.S07: RdPtrOffsetTxDqs: 07
N4.C1.D0.R0.S07: Total Delay in PI ticks: TxDQ = 952
N6.C0.D0.R1.S15: Total Delay in PI ticks: TxDQ = 914
N0.C0.D0.R1.S14: RdPtrOffsetTxDq: 07
N2.C1.D1.R0.S07: PiTxDqs: 29
N4.C1.D0.R0.S08: Total Delay in PI ticks: TxDQ = 926
N6.C0.D0.R1.S16: Total Delay in PI ticks: TxDQ = 931
N0.C0.D0.R1.S15: RdPtrOffsetTxDq: 07
N2.C1.D1.R0.S08: wrcmd2dqsstartlatency: 04
N4.C1.D0.R0.S09: Total Delay in PI ticks: TxDQ = 987
N6.C0.D0.R1.S17: Total Delay in PI ticks: TxDQ = 905
N0.C0.D0.R1.S16: RdPtrOffsetTxDq: 07
N2.C1.D1.R0.S08: RdPtrOffsetTxDq: 05
N4.C1.D0.R0.S10: Total Delay in PI ticks: TxDQ = 970
N6.C0.D1.R0.S00: wrcmd2dqsstartlatency: 04
N0.C0.D0.R1.S17: RdPtrOffsetTxDq: 07
N2.C1.D1.R0.S08: RdPtrOffsetTxDqs: 06
N4.C1.D0.R0.S11: Total Delay in PI ticks: TxDQ = 963
N6.C0.D1.R0.S00: RdPtrOffsetTxDq: 06
N0.C0.D0.R1.S00: Total Delay in PI ticks: TxDQ = 978
N2.C1.D1.R0.S08: PiTxDqs: 58
N4.C1.D0.R0.S12: Total Delay in PI ticks: TxDQ = 946
N6.C0.D1.R0.S00: RdPtrOffsetTxDqs: 07
N0.C0.D0.R1.S01: Total Delay in PI ticks: TxDQ = 960
N2.C1.D1.R0.S09: wrcmd2dqsstartlatency: 04
N4.C1.D0.R0.S13: Total Delay in PI ticks: TxDQ = 912
N6.C0.D1.R0.S00: PiTxDqs: 54
N0.C0.D0.R1.S02: Total Delay in PI ticks: TxDQ = 946
N2.C1.D1.R0.S09: RdPtrOffsetTxDq: 06
N4.C1.D0.R0.S14: Total Delay in PI ticks: TxDQ = 924
N6.C0.D1.R0.S01: wrcmd2dqsstartlatency: 04
N0.C0.D0.R1.S03: Total Delay in PI ticks: TxDQ = 929
N2.C1.D1.R0.S09: RdPtrOffsetTxDqs: 07
N4.C1.D0.R0.S15: Total Delay in PI ticks: TxDQ = 940
N6.C0.D1.R0.S01: RdPtrOffsetTxDq: 06
N0.C0.D0.R1.S04: Total Delay in PI ticks: TxDQ = 899
N2.C1.D1.R0.S09: PiTxDqs: 57
N4.C1.D0.R0.S16: Total Delay in PI ticks: TxDQ = 952
N6.C0.D1.R0.S01: RdPtrOffsetTxDqs: 07
N0.C0.D0.R1.S05: Total Delay in PI ticks: TxDQ = 913
N2.C1.D1.R0.S10: wrcmd2dqsstartlatency: 04
N4.C1.D0.R0.S17: Total Delay in PI ticks: TxDQ = 929
N6.C0.D1.R0.S01: PiTxDqs: 37
N0.C0.D0.R1.S06: Total Delay in PI ticks: TxDQ = 916
N2.C1.D1.R0.S10: RdPtrOffsetTxDq: 06
N4.C1.D0.R1.S00: wrcmd2dqsstartlatency: 04
N6.C0.D1.R0.S02: wrcmd2dqsstartlatency: 04
N0.C0.D0.R1.S07: Total Delay in PI ticks: TxDQ = 935
N2.C1.D1.R0.S10: RdPtrOffsetTxDqs: 07
N4.C1.D0.R1.S00: RdPtrOffsetTxDq: 06
N6.C0.D1.R0.S02: RdPtrOffsetTxDq: 05
N0.C0.D0.R1.S08: Total Delay in PI ticks: TxDQ = 906
N2.C1.D1.R0.S10: PiTxDqs: 40
N4.C1.D0.R1.S00: RdPtrOffsetTxDqs: 07
N6.C0.D1.R0.S02: RdPtrOffsetTxDqs: 07
N0.C0.D0.R1.S09: Total Delay in PI ticks: TxDQ = 976
N2.C1.D1.R0.S11: wrcmd2dqsstartlatency: 04
N4.C1.D0.R1.S00: PiTxDqs: 50
N6.C0.D1.R0.S02: PiTxDqs: 25
N0.C0.D0.R1.S10: Total Delay in PI ticks: TxDQ = 960
N2.C1.D1.R0.S11: RdPtrOffsetTxDq: 06
N4.C1.D0.R1.S01: wrcmd2dqsstartlatency: 04
N6.C0.D1.R0.S03: wrcmd2dqsstartlatency: 04
N0.C0.D0.R1.S11: Total Delay in PI ticks: TxDQ = 946
N2.C1.D1.R0.S11: RdPtrOffsetTxDqs: 07
N4.C1.D0.R1.S01: RdPtrOffsetTxDq: 05
N6.C0.D1.R0.S03: RdPtrOffsetTxDq: 05
N0.C0.D0.R1.S12: Total Delay in PI ticks: TxDQ = 932
N2.C1.D1.R0.S11: PiTxDqs: 33
N4.C1.D0.R1.S01: RdPtrOffsetTxDqs: 07
N6.C0.D1.R0.S03: RdPtrOffsetTxDqs: 07
N0.C0.D0.R1.S13: Total Delay in PI ticks: TxDQ = 900
N2.C1.D1.R0.S12: wrcmd2dqsstartlatency: 04
N4.C1.D0.R1.S01: PiTxDqs: 36
N6.C0.D1.R0.S03: PiTxDqs: 12
N0.C0.D0.R1.S14: Total Delay in PI ticks: TxDQ = 916
N2.C1.D1.R0.S12: RdPtrOffsetTxDq: 05
N4.C1.D0.R1.S02: wrcmd2dqsstartlatency: 04
N6.C0.D1.R0.S04: wrcmd2dqsstartlatency: 04
N0.C0.D0.R1.S15: Total Delay in PI ticks: TxDQ = 919
N2.C1.D1.R0.S12: RdPtrOffsetTxDqs: 07
N4.C1.D0.R1.S02: RdPtrOffsetTxDq: 05
N6.C0.D1.R0.S04: RdPtrOffsetTxDq: 05
N0.C0.D0.R1.S16: Total Delay in PI ticks: TxDQ = 935
N2.C1.D1.R0.S12: PiTxDqs: 17
N4.C1.D0.R1.S02: RdPtrOffsetTxDqs: 07
N6.C0.D1.R0.S04: RdPtrOffsetTxDqs: 06
N0.C0.D0.R1.S17: Total Delay in PI ticks: TxDQ = 905
N2.C1.D1.R0.S13: wrcmd2dqsstartlatency: 04
N4.C1.D0.R1.S02: PiTxDqs: 26
N6.C0.D1.R0.S04: PiTxDqs: 39
N0.C0.D1.R0.S00: wrcmd2dqsstartlatency: 04
N2.C1.D1.R0.S13: RdPtrOffsetTxDq: 05
N4.C1.D0.R1.S03: wrcmd2dqsstartlatency: 04
N6.C0.D1.R0.S05: wrcmd2dqsstartlatency: 04
N0.C0.D1.R0.S00: RdPtrOffsetTxDq: 06
N2.C1.D1.R0.S13: RdPtrOffsetTxDqs: 06
N4.C1.D0.R1.S03: RdPtrOffsetTxDq: 05
N6.C0.D1.R0.S05: RdPtrOffsetTxDq: 05
N0.C0.D1.R0.S00: RdPtrOffsetTxDqs: 07
N2.C1.D1.R0.S13: PiTxDqs: 47
N4.C1.D0.R1.S03: RdPtrOffsetTxDqs: 07
N6.C0.D1.R0.S05: RdPtrOffsetTxDqs: 06
N0.C0.D1.R0.S00: PiTxDqs: 61
N2.C1.D1.R0.S14: wrcmd2dqsstartlatency: 04
N4.C1.D0.R1.S03: PiTxDqs: 12
N6.C0.D1.R0.S05: PiTxDqs: 57
N0.C0.D1.R0.S01: wrcmd2dqsstartlatency: 04
N2.C1.D1.R0.S14: RdPtrOffsetTxDq: 05
N4.C1.D0.R1.S04: wrcmd2dqsstartlatency: 04
N6.C0.D1.R0.S06: wrcmd2dqsstartlatency: 04
N0.C0.D1.R0.S01: RdPtrOffsetTxDq: 06
N2.C1.D1.R0.S14: RdPtrOffsetTxDqs: 06
N4.C1.D0.R1.S04: RdPtrOffsetTxDq: 05
N6.C0.D1.R0.S06: RdPtrOffsetTxDq: 05
N0.C0.D1.R0.S01: RdPtrOffsetTxDqs: 07
N2.C1.D1.R0.S14: PiTxDqs: 63
N4.C1.D0.R1.S04: RdPtrOffsetTxDqs: 06
N6.C0.D1.R0.S06: RdPtrOffsetTxDqs: 06
N0.C0.D1.R0.S01: PiTxDqs: 45
N2.C1.D1.R0.S15: wrcmd2dqsstartlatency: 04
N4.C1.D0.R1.S04: PiTxDqs: 42
N6.C0.D1.R0.S06: PiTxDqs: 60
N0.C0.D1.R0.S02: wrcmd2dqsstartlatency: 04
N2.C1.D1.R0.S15: RdPtrOffsetTxDq: 05
N4.C1.D0.R1.S05: wrcmd2dqsstartlatency: 04
N6.C0.D1.R0.S07: wrcmd2dqsstartlatency: 04
N0.C0.D1.R0.S02: RdPtrOffsetTxDq: 05
N2.C1.D1.R0.S15: RdPtrOffsetTxDqs: 07
N4.C1.D0.R1.S05: RdPtrOffsetTxDq: 05
N6.C0.D1.R0.S07: RdPtrOffsetTxDq: 05
N0.C0.D1.R0.S02: RdPtrOffsetTxDqs: 07
N2.C1.D1.R0.S15: PiTxDqs: 09
N4.C1.D0.R1.S05: RdPtrOffsetTxDqs: 06
N6.C0.D1.R0.S07: RdPtrOffsetTxDqs: 07
N0.C0.D1.R0.S02: PiTxDqs: 32
N2.C1.D1.R0.S16: wrcmd2dqsstartlatency: 04
N4.C1.D0.R1.S05: PiTxDqs: 54
N6.C0.D1.R0.S07: PiTxDqs: 14
N0.C0.D1.R0.S03: wrcmd2dqsstartlatency: 04
N2.C1.D1.R0.S16: RdPtrOffsetTxDq: 05
N4.C1.D0.R1.S06: wrcmd2dqsstartlatency: 04
N6.C0.D1.R0.S08: wrcmd2dqsstartlatency: 04
N0.C0.D1.R0.S03: RdPtrOffsetTxDq: 05
N2.C1.D1.R0.S16: RdPtrOffsetTxDqs: 07
N4.C1.D0.R1.S06: RdPtrOffsetTxDq: 05
N6.C0.D1.R0.S08: RdPtrOffsetTxDq: 05
N0.C0.D1.R0.S03: RdPtrOffsetTxDqs: 07
N2.C1.D1.R0.S16: PiTxDqs: 28
N4.C1.D0.R1.S06: RdPtrOffsetTxDqs: 07
N6.C0.D1.R0.S08: RdPtrOffsetTxDqs: 06
N0.C0.D1.R0.S03: PiTxDqs: 15
N2.C1.D1.R0.S17: wrcmd2dqsstartlatency: 04
N4.C1.D0.R1.S06: PiTxDqs: 02
N6.C0.D1.R0.S08: PiTxDqs: 48
N0.C0.D1.R0.S04: wrcmd2dqsstartlatency: 04
N2.C1.D1.R0.S17: RdPtrOffsetTxDq: 05
N4.C1.D0.R1.S07: wrcmd2dqsstartlatency: 04
N6.C0.D1.R0.S09: wrcmd2dqsstartlatency: 04
N0.C0.D1.R0.S04: RdPtrOffsetTxDq: 05
N2.C1.D1.R0.S17: RdPtrOffsetTxDqs: 06
N4.C1.D0.R1.S07: RdPtrOffsetTxDq: 05
N6.C0.D1.R0.S09: RdPtrOffsetTxDq: 06
N0.C0.D1.R0.S04: RdPtrOffsetTxDqs: 06
N2.C1.D1.R0.S17: PiTxDqs: 59
N4.C1.D0.R1.S07: RdPtrOffsetTxDqs: 07
N6.C0.D1.R0.S09: RdPtrOffsetTxDqs: 07
N0.C0.D1.R0.S04: PiTxDqs: 45
N2.C1.D1.R0.S00: RdPtrOffsetTxDq: 07
N4.C1.D0.R1.S07: PiTxDqs: 23
N6.C0.D1.R0.S09: PiTxDqs: 56
N0.C0.D1.R0.S05: wrcmd2dqsstartlatency: 04
N2.C1.D1.R0.S01: RdPtrOffsetTxDq: 07
N4.C1.D0.R1.S08: wrcmd2dqsstartlatency: 04
N6.C0.D1.R0.S10: wrcmd2dqsstartlatency: 04
N0.C0.D1.R0.S05: RdPtrOffsetTxDq: 05
N2.C1.D1.R0.S02: RdPtrOffsetTxDq: 06
N4.C1.D0.R1.S08: RdPtrOffsetTxDq: 05
N6.C0.D1.R0.S10: RdPtrOffsetTxDq: 06
N0.C0.D1.R0.S05: RdPtrOffsetTxDqs: 07
N2.C1.D1.R0.S03: RdPtrOffsetTxDq: 06
N4.C1.D0.R1.S08: RdPtrOffsetTxDqs: 06
N6.C0.D1.R0.S10: RdPtrOffsetTxDqs: 07
N0.C0.D1.R0.S05: PiTxDqs: 00
N2.C1.D1.R0.S04: RdPtrOffsetTxDq: 06
N4.C1.D0.R1.S08: PiTxDqs: 57
N6.C0.D1.R0.S10: PiTxDqs: 38
N0.C0.D1.R0.S06: wrcmd2dqsstartlatency: 04
N2.C1.D1.R0.S05: RdPtrOffsetTxDq: 06
N4.C1.D0.R1.S09: wrcmd2dqsstartlatency: 04
N6.C0.D1.R0.S11: wrcmd2dqsstartlatency: 04
N0.C0.D1.R0.S06: RdPtrOffsetTxDq: 05
N2.C1.D1.R0.S06: RdPtrOffsetTxDq: 06
N4.C1.D0.R1.S09: RdPtrOffsetTxDq: 06
N6.C0.D1.R0.S11: RdPtrOffsetTxDq: 05
N0.C0.D1.R0.S06: RdPtrOffsetTxDqs: 07
N2.C1.D1.R0.S07: RdPtrOffsetTxDq: 06
N4.C1.D0.R1.S09: RdPtrOffsetTxDqs: 07
N6.C0.D1.R0.S11: RdPtrOffsetTxDqs: 07
N0.C0.D1.R0.S06: PiTxDqs: 00
N2.C1.D1.R0.S08: RdPtrOffsetTxDq: 06
N4.C1.D0.R1.S09: PiTxDqs: 50
N6.C0.D1.R0.S11: PiTxDqs: 23
N0.C0.D1.R0.S07: wrcmd2dqsstartlatency: 04
N2.C1.D1.R0.S09: RdPtrOffsetTxDq: 07
N4.C1.D0.R1.S10: wrcmd2dqsstartlatency: 04
N6.C0.D1.R0.S12: wrcmd2dqsstartlatency: 04
N0.C0.D1.R0.S07: RdPtrOffsetTxDq: 05
N2.C1.D1.R0.S10: RdPtrOffsetTxDq: 07
N4.C1.D0.R1.S10: RdPtrOffsetTxDq: 06
N6.C0.D1.R0.S12: RdPtrOffsetTxDq: 05
N0.C0.D1.R0.S07: RdPtrOffsetTxDqs: 07
N2.C1.D1.R0.S11: RdPtrOffsetTxDq: 07
N4.C1.D0.R1.S10: RdPtrOffsetTxDqs: 07
N6.C0.D1.R0.S12: RdPtrOffsetTxDqs: 07
N0.C0.D1.R0.S07: PiTxDqs: 18
N2.C1.D1.R0.S12: RdPtrOffsetTxDq: 06
N4.C1.D0.R1.S10: PiTxDqs: 37
N6.C0.D1.R0.S12: PiTxDqs: 11
N0.C0.D1.R0.S08: wrcmd2dqsstartlatency: 04
N2.C1.D1.R0.S13: RdPtrOffsetTxDq: 06
N4.C1.D0.R1.S11: wrcmd2dqsstartlatency: 04
N6.C0.D1.R0.S13: wrcmd2dqsstartlatency: 04
N0.C0.D1.R0.S08: RdPtrOffsetTxDq: 05
N2.C1.D1.R0.S14: RdPtrOffsetTxDq: 06
N4.C1.D0.R1.S11: RdPtrOffsetTxDq: 05
N6.C0.D1.R0.S13: RdPtrOffsetTxDq: 05
N0.C0.D1.R0.S08: RdPtrOffsetTxDqs: 06
N2.C1.D1.R0.S15: RdPtrOffsetTxDq: 06
N4.C1.D0.R1.S11: RdPtrOffsetTxDqs: 07
N6.C0.D1.R0.S13: RdPtrOffsetTxDqs: 06
N0.C0.D1.R0.S08: PiTxDqs: 54
N2.C1.D1.R0.S16: RdPtrOffsetTxDq: 06
N4.C1.D0.R1.S11: PiTxDqs: 27
N6.C0.D1.R0.S13: PiTxDqs: 40
N0.C0.D1.R0.S09: wrcmd2dqsstartlatency: 04
N2.C1.D1.R0.S17: RdPtrOffsetTxDq: 06
N4.C1.D0.R1.S12: wrcmd2dqsstartlatency: 04
N6.C0.D1.R0.S14: wrcmd2dqsstartlatency: 04
N0.C0.D1.R0.S09: RdPtrOffsetTxDq: 06
N2.C1.D1.R0.S00: RdPtrOffsetTxDq: 08
N4.C1.D0.R1.S12: RdPtrOffsetTxDq: 05
N6.C0.D1.R0.S14: RdPtrOffsetTxDq: 05
N0.C0.D1.R0.S09: RdPtrOffsetTxDqs: 07
N2.C1.D1.R0.S01: RdPtrOffsetTxDq: 08
N4.C1.D0.R1.S12: RdPtrOffsetTxDqs: 07
N6.C0.D1.R0.S14: RdPtrOffsetTxDqs: 06
N0.C0.D1.R0.S09: PiTxDqs: 57
N2.C1.D1.R0.S02: RdPtrOffsetTxDq: 07
N4.C1.D0.R1.S12: PiTxDqs: 14
N6.C0.D1.R0.S14: PiTxDqs: 59
N0.C0.D1.R0.S10: wrcmd2dqsstartlatency: 04
N2.C1.D1.R0.S03: RdPtrOffsetTxDq: 07
N4.C1.D0.R1.S13: wrcmd2dqsstartlatency: 04
N6.C0.D1.R0.S15: wrcmd2dqsstartlatency: 04
N0.C0.D1.R0.S10: RdPtrOffsetTxDq: 06
N2.C1.D1.R0.S04: RdPtrOffsetTxDq: 07
N4.C1.D0.R1.S13: RdPtrOffsetTxDq: 05
N6.C0.D1.R0.S15: RdPtrOffsetTxDq: 05
N0.C0.D1.R0.S10: RdPtrOffsetTxDqs: 07
N2.C1.D1.R0.S05: RdPtrOffsetTxDq: 07
N4.C1.D0.R1.S13: RdPtrOffsetTxDqs: 06
N6.C0.D1.R0.S15: RdPtrOffsetTxDqs: 06
N0.C0.D1.R0.S10: PiTxDqs: 45
N2.C1.D1.R0.S06: RdPtrOffsetTxDq: 07
N4.C1.D0.R1.S13: PiTxDqs: 43
N6.C0.D1.R0.S15: PiTxDqs: 61
N0.C0.D1.R0.S11: wrcmd2dqsstartlatency: 04
N2.C1.D1.R0.S07: RdPtrOffsetTxDq: 07
N4.C1.D0.R1.S14: wrcmd2dqsstartlatency: 04
N6.C0.D1.R0.S16: wrcmd2dqsstartlatency: 04
N0.C0.D1.R0.S11: RdPtrOffsetTxDq: 05
N2.C1.D1.R0.S08: RdPtrOffsetTxDq: 07
N4.C1.D0.R1.S14: RdPtrOffsetTxDq: 05
N6.C0.D1.R0.S16: RdPtrOffsetTxDq: 05
N0.C0.D1.R0.S11: RdPtrOffsetTxDqs: 07
N2.C1.D1.R0.S09: RdPtrOffsetTxDq: 08
N4.C1.D0.R1.S14: RdPtrOffsetTxDqs: 06
N6.C0.D1.R0.S16: RdPtrOffsetTxDqs: 07
N0.C0.D1.R0.S11: PiTxDqs: 31
N2.C1.D1.R0.S10: RdPtrOffsetTxDq: 08
N4.C1.D0.R1.S14: PiTxDqs: 56
N6.C0.D1.R0.S16: PiTxDqs: 15
N0.C0.D1.R0.S12: wrcmd2dqsstartlatency: 04
N2.C1.D1.R0.S11: RdPtrOffsetTxDq: 08
N4.C1.D0.R1.S15: wrcmd2dqsstartlatency: 04
N6.C0.D1.R0.S17: wrcmd2dqsstartlatency: 04
N0.C0.D1.R0.S12: RdPtrOffsetTxDq: 05
N2.C1.D1.R0.S12: RdPtrOffsetTxDq: 07
N4.C1.D0.R1.S15: RdPtrOffsetTxDq: 05
N6.C0.D1.R0.S17: RdPtrOffsetTxDq: 05
N0.C0.D1.R0.S12: RdPtrOffsetTxDqs: 07
N2.C1.D1.R0.S13: RdPtrOffsetTxDq: 07
N4.C1.D0.R1.S15: RdPtrOffsetTxDqs: 07
N6.C0.D1.R0.S17: RdPtrOffsetTxDqs: 06
N0.C0.D1.R0.S12: PiTxDqs: 17
N2.C1.D1.R0.S14: RdPtrOffsetTxDq: 07
N4.C1.D0.R1.S15: PiTxDqs: 07
N6.C0.D1.R0.S17: PiTxDqs: 49
N0.C0.D1.R0.S13: wrcmd2dqsstartlatency: 04
N2.C1.D1.R0.S15: RdPtrOffsetTxDq: 07
N4.C1.D0.R1.S16: wrcmd2dqsstartlatency: 04
N6.C0.D1.R0.S00: RdPtrOffsetTxDq: 07
N0.C0.D1.R0.S13: RdPtrOffsetTxDq: 05
N2.C1.D1.R0.S16: RdPtrOffsetTxDq: 07
N4.C1.D0.R1.S16: RdPtrOffsetTxDq: 05
N6.C0.D1.R0.S01: RdPtrOffsetTxDq: 07
N0.C0.D1.R0.S13: RdPtrOffsetTxDqs: 06
N2.C1.D1.R0.S17: RdPtrOffsetTxDq: 07
N4.C1.D0.R1.S16: RdPtrOffsetTxDqs: 07
N6.C0.D1.R0.S02: RdPtrOffsetTxDq: 06
N0.C0.D1.R0.S13: PiTxDqs: 46
N2.C1.D1.R0.S00: Total Delay in PI ticks: TxDQ = 984
N4.C1.D0.R1.S16: PiTxDqs: 23
N6.C0.D1.R0.S03: RdPtrOffsetTxDq: 06
N0.C0.D1.R0.S14: wrcmd2dqsstartlatency: 04
N2.C1.D1.R0.S01: Total Delay in PI ticks: TxDQ = 966
N4.C1.D0.R1.S17: wrcmd2dqsstartlatency: 04
N6.C0.D1.R0.S04: RdPtrOffsetTxDq: 06
N0.C0.D1.R0.S14: RdPtrOffsetTxDq: 05
N2.C1.D1.R0.S02: Total Delay in PI ticks: TxDQ = 959
N4.C1.D0.R1.S17: RdPtrOffsetTxDq: 05
N6.C0.D1.R0.S05: RdPtrOffsetTxDq: 06
N0.C0.D1.R0.S14: RdPtrOffsetTxDqs: 06
N2.C1.D1.R0.S03: Total Delay in PI ticks: TxDQ = 942
N4.C1.D0.R1.S17: RdPtrOffsetTxDqs: 06
N6.C0.D1.R0.S06: RdPtrOffsetTxDq: 06
N0.C0.D1.R0.S14: PiTxDqs: 62
N2.C1.D1.R0.S04: Total Delay in PI ticks: TxDQ = 911
N4.C1.D0.R1.S17: PiTxDqs: 56
N6.C0.D1.R0.S07: RdPtrOffsetTxDq: 06
N0.C0.D1.R0.S15: wrcmd2dqsstartlatency: 04
N2.C1.D1.R0.S05: Total Delay in PI ticks: TxDQ = 925
N4.C1.D0.R1.S00: RdPtrOffsetTxDq: 07
N6.C0.D1.R0.S08: RdPtrOffsetTxDq: 06
N0.C0.D1.R0.S15: RdPtrOffsetTxDq: 05
N2.C1.D1.R0.S06: Total Delay in PI ticks: TxDQ = 938
N4.C1.D0.R1.S01: RdPtrOffsetTxDq: 06
N6.C0.D1.R0.S09: RdPtrOffsetTxDq: 07
N0.C0.D1.R0.S15: RdPtrOffsetTxDqs: 07
N2.C1.D1.R0.S07: Total Delay in PI ticks: TxDQ = 955
N4.C1.D0.R1.S02: RdPtrOffsetTxDq: 06
N6.C0.D1.R0.S10: RdPtrOffsetTxDq: 07
N0.C0.D1.R0.S15: PiTxDqs: 02
N2.C1.D1.R0.S08: Total Delay in PI ticks: TxDQ = 921
N4.C1.D0.R1.S03: RdPtrOffsetTxDq: 06
N6.C0.D1.R0.S11: RdPtrOffsetTxDq: 06
N0.C0.D1.R0.S16: wrcmd2dqsstartlatency: 04
N2.C1.D1.R0.S09: Total Delay in PI ticks: TxDQ = 984
N4.C1.D0.R1.S04: RdPtrOffsetTxDq: 06
N6.C0.D1.R0.S12: RdPtrOffsetTxDq: 06
N0.C0.D1.R0.S16: RdPtrOffsetTxDq: 05
N2.C1.D1.R0.S10: Total Delay in PI ticks: TxDQ = 966
N4.C1.D0.R1.S05: RdPtrOffsetTxDq: 06
N6.C0.D1.R0.S13: RdPtrOffsetTxDq: 06
N0.C0.D1.R0.S16: RdPtrOffsetTxDqs: 07
N2.C1.D1.R0.S11: Total Delay in PI ticks: TxDQ = 961
N4.C1.D0.R1.S06: RdPtrOffsetTxDq: 06
N6.C0.D1.R0.S14: RdPtrOffsetTxDq: 06
N0.C0.D1.R0.S16: PiTxDqs: 19
N2.C1.D1.R0.S12: Total Delay in PI ticks: TxDQ = 945
N4.C1.D0.R1.S07: RdPtrOffsetTxDq: 06
N6.C0.D1.R0.S15: RdPtrOffsetTxDq: 06
N0.C0.D1.R0.S17: wrcmd2dqsstartlatency: 04
N2.C1.D1.R0.S13: Total Delay in PI ticks: TxDQ = 910
N4.C1.D0.R1.S08: RdPtrOffsetTxDq: 06
N6.C0.D1.R0.S16: RdPtrOffsetTxDq: 06
N0.C0.D1.R0.S17: RdPtrOffsetTxDq: 05
N2.C1.D1.R0.S14: Total Delay in PI ticks: TxDQ = 926
N4.C1.D0.R1.S09: RdPtrOffsetTxDq: 07
N6.C0.D1.R0.S17: RdPtrOffsetTxDq: 06
N0.C0.D1.R0.S17: RdPtrOffsetTxDqs: 06
N2.C1.D1.R0.S15: Total Delay in PI ticks: TxDQ = 938
N4.C1.D0.R1.S10: RdPtrOffsetTxDq: 07
N6.C0.D1.R0.S00: RdPtrOffsetTxDq: 08
N0.C0.D1.R0.S17: PiTxDqs: 55
N2.C1.D1.R0.S16: Total Delay in PI ticks: TxDQ = 955
N4.C1.D0.R1.S11: RdPtrOffsetTxDq: 06
N6.C0.D1.R0.S01: RdPtrOffsetTxDq: 08
N0.C0.D1.R0.S00: RdPtrOffsetTxDq: 07
N2.C1.D1.R0.S17: Total Delay in PI ticks: TxDQ = 923
N4.C1.D0.R1.S12: RdPtrOffsetTxDq: 06
N6.C0.D1.R0.S02: RdPtrOffsetTxDq: 07
N0.C0.D1.R0.S01: RdPtrOffsetTxDq: 07
N2.C1.D1.R1.S00: wrcmd2dqsstartlatency: 04
N4.C1.D0.R1.S13: RdPtrOffsetTxDq: 06
N6.C0.D1.R0.S03: RdPtrOffsetTxDq: 07
N0.C0.D1.R0.S02: RdPtrOffsetTxDq: 06
N2.C1.D1.R1.S00: RdPtrOffsetTxDq: 06
N4.C1.D0.R1.S14: RdPtrOffsetTxDq: 06
N6.C0.D1.R0.S04: RdPtrOffsetTxDq: 07
N0.C0.D1.R0.S03: RdPtrOffsetTxDq: 06
N2.C1.D1.R1.S00: RdPtrOffsetTxDqs: 07
N4.C1.D0.R1.S15: RdPtrOffsetTxDq: 06
N6.C0.D1.R0.S05: RdPtrOffsetTxDq: 07
N0.C0.D1.R0.S04: RdPtrOffsetTxDq: 06
N2.C1.D1.R1.S00: PiTxDqs: 52
N4.C1.D0.R1.S16: RdPtrOffsetTxDq: 06
N6.C0.D1.R0.S06: RdPtrOffsetTxDq: 07
N0.C0.D1.R0.S05: RdPtrOffsetTxDq: 06
N2.C1.D1.R1.S01: wrcmd2dqsstartlatency: 04
N4.C1.D0.R1.S17: RdPtrOffsetTxDq: 06
N6.C0.D1.R0.S07: RdPtrOffsetTxDq: 07
N0.C0.D1.R0.S06: RdPtrOffsetTxDq: 06
N2.C1.D1.R1.S01: RdPtrOffsetTxDq: 06
N4.C1.D0.R1.S00: RdPtrOffsetTxDq: 08
N6.C0.D1.R0.S08: RdPtrOffsetTxDq: 07
N0.C0.D1.R0.S07: RdPtrOffsetTxDq: 06
N2.C1.D1.R1.S01: RdPtrOffsetTxDqs: 07
N4.C1.D0.R1.S01: RdPtrOffsetTxDq: 07
N6.C0.D1.R0.S09: RdPtrOffsetTxDq: 08
N0.C0.D1.R0.S08: RdPtrOffsetTxDq: 06
N2.C1.D1.R1.S01: PiTxDqs: 36
N4.C1.D0.R1.S02: RdPtrOffsetTxDq: 07
N6.C0.D1.R0.S10: RdPtrOffsetTxDq: 08
N0.C0.D1.R0.S09: RdPtrOffsetTxDq: 07
N2.C1.D1.R1.S02: wrcmd2dqsstartlatency: 04
N4.C1.D0.R1.S03: RdPtrOffsetTxDq: 07
N6.C0.D1.R0.S11: RdPtrOffsetTxDq: 07
N0.C0.D1.R0.S10: RdPtrOffsetTxDq: 07
N2.C1.D1.R1.S02: RdPtrOffsetTxDq: 05
N4.C1.D0.R1.S04: RdPtrOffsetTxDq: 07
N6.C0.D1.R0.S12: RdPtrOffsetTxDq: 07
N0.C0.D1.R0.S11: RdPtrOffsetTxDq: 06
N2.C1.D1.R1.S02: RdPtrOffsetTxDqs: 07
N4.C1.D0.R1.S05: RdPtrOffsetTxDq: 07
N6.C0.D1.R0.S13: RdPtrOffsetTxDq: 07
N0.C0.D1.R0.S12: RdPtrOffsetTxDq: 06
N2.C1.D1.R1.S02: PiTxDqs: 28
N4.C1.D0.R1.S06: RdPtrOffsetTxDq: 07
N6.C0.D1.R0.S14: RdPtrOffsetTxDq: 07
N0.C0.D1.R0.S13: RdPtrOffsetTxDq: 06
N2.C1.D1.R1.S03: wrcmd2dqsstartlatency: 04
N4.C1.D0.R1.S07: RdPtrOffsetTxDq: 07
N6.C0.D1.R0.S15: RdPtrOffsetTxDq: 07
N0.C0.D1.R0.S14: RdPtrOffsetTxDq: 06
N2.C1.D1.R1.S03: RdPtrOffsetTxDq: 05
N4.C1.D0.R1.S08: RdPtrOffsetTxDq: 07
N6.C0.D1.R0.S16: RdPtrOffsetTxDq: 07
N0.C0.D1.R0.S15: RdPtrOffsetTxDq: 06
N2.C1.D1.R1.S03: RdPtrOffsetTxDqs: 07
N4.C1.D0.R1.S09: RdPtrOffsetTxDq: 08
N6.C0.D1.R0.S17: RdPtrOffsetTxDq: 07
N0.C0.D1.R0.S16: RdPtrOffsetTxDq: 06
N2.C1.D1.R1.S03: PiTxDqs: 11
N4.C1.D0.R1.S10: RdPtrOffsetTxDq: 08
N6.C0.D1.R0.S00: Total Delay in PI ticks: TxDQ = 984
N0.C0.D1.R0.S17: RdPtrOffsetTxDq: 06
N2.C1.D1.R1.S04: wrcmd2dqsstartlatency: 04
N4.C1.D0.R1.S11: RdPtrOffsetTxDq: 07
N6.C0.D1.R0.S01: Total Delay in PI ticks: TxDQ = 964
N0.C0.D1.R0.S00: RdPtrOffsetTxDq: 08
N2.C1.D1.R1.S04: RdPtrOffsetTxDq: 05
N4.C1.D0.R1.S12: RdPtrOffsetTxDq: 07
N6.C0.D1.R0.S02: Total Delay in PI ticks: TxDQ = 953
N0.C0.D1.R0.S01: RdPtrOffsetTxDq: 08
N2.C1.D1.R1.S04: RdPtrOffsetTxDqs: 06
N4.C1.D0.R1.S13: RdPtrOffsetTxDq: 07
N6.C0.D1.R0.S03: Total Delay in PI ticks: TxDQ = 939
N0.C0.D1.R0.S02: RdPtrOffsetTxDq: 07
N2.C1.D1.R1.S04: PiTxDqs: 43
N4.C1.D0.R1.S14: RdPtrOffsetTxDq: 07
N6.C0.D1.R0.S04: Total Delay in PI ticks: TxDQ = 904
N0.C0.D1.R0.S03: RdPtrOffsetTxDq: 07
N2.C1.D1.R1.S05: wrcmd2dqsstartlatency: 04
N4.C1.D0.R1.S15: RdPtrOffsetTxDq: 07
N6.C0.D1.R0.S05: Total Delay in PI ticks: TxDQ = 921
N0.C0.D1.R0.S04: RdPtrOffsetTxDq: 07
N2.C1.D1.R1.S05: RdPtrOffsetTxDq: 05
N4.C1.D0.R1.S16: RdPtrOffsetTxDq: 07
N6.C0.D1.R0.S06: Total Delay in PI ticks: TxDQ = 924
N0.C0.D1.R0.S05: RdPtrOffsetTxDq: 07
N2.C1.D1.R1.S05: RdPtrOffsetTxDqs: 06
N4.C1.D0.R1.S17: RdPtrOffsetTxDq: 07
N6.C0.D1.R0.S07: Total Delay in PI ticks: TxDQ = 941
N0.C0.D1.R0.S06: RdPtrOffsetTxDq: 07
N2.C1.D1.R1.S05: PiTxDqs: 58
N4.C1.D0.R1.S00: Total Delay in PI ticks: TxDQ = 978
N6.C0.D1.R0.S08: Total Delay in PI ticks: TxDQ = 912
N0.C0.D1.R0.S07: RdPtrOffsetTxDq: 07
N2.C1.D1.R1.S06: wrcmd2dqsstartlatency: 04
N4.C1.D0.R1.S01: Total Delay in PI ticks: TxDQ = 963
N6.C0.D1.R0.S09: Total Delay in PI ticks: TxDQ = 982
N0.C0.D1.R0.S08: RdPtrOffsetTxDq: 07
N2.C1.D1.R1.S06: RdPtrOffsetTxDq: 05
N4.C1.D0.R1.S02: Total Delay in PI ticks: TxDQ = 953
N6.C0.D1.R0.S10: Total Delay in PI ticks: TxDQ = 964
N0.C0.D1.R0.S09: RdPtrOffsetTxDq: 08
N2.C1.D1.R1.S06: RdPtrOffsetTxDqs: 07
N4.C1.D0.R1.S03: Total Delay in PI ticks: TxDQ = 938
N6.C0.D1.R0.S11: Total Delay in PI ticks: TxDQ = 950
N0.C0.D1.R0.S10: RdPtrOffsetTxDq: 08
N2.C1.D1.R1.S06: PiTxDqs: 07
N4.C1.D0.R1.S04: Total Delay in PI ticks: TxDQ = 906
N6.C0.D1.R0.S12: Total Delay in PI ticks: TxDQ = 938
N0.C0.D1.R0.S11: RdPtrOffsetTxDq: 07
N2.C1.D1.R1.S07: wrcmd2dqsstartlatency: 04
N4.C1.D0.R1.S05: Total Delay in PI ticks: TxDQ = 916
N6.C0.D1.R0.S13: Total Delay in PI ticks: TxDQ = 904
N0.C0.D1.R0.S12: RdPtrOffsetTxDq: 07
N2.C1.D1.R1.S07: RdPtrOffsetTxDq: 05
N4.C1.D0.R1.S06: Total Delay in PI ticks: TxDQ = 930
N6.C0.D1.R0.S14: Total Delay in PI ticks: TxDQ = 922
N0.C0.D1.R0.S13: RdPtrOffsetTxDq: 07
N2.C1.D1.R1.S07: RdPtrOffsetTxDqs: 07
N4.C1.D0.R1.S07: Total Delay in PI ticks: TxDQ = 946
N6.C0.D1.R0.S15: Total Delay in PI ticks: TxDQ = 923
N0.C0.D1.R0.S14: RdPtrOffsetTxDq: 07
N2.C1.D1.R1.S07: PiTxDqs: 25
N4.C1.D0.R1.S08: Total Delay in PI ticks: TxDQ = 920
N6.C0.D1.R0.S16: Total Delay in PI ticks: TxDQ = 942
N0.C0.D1.R0.S15: RdPtrOffsetTxDq: 07
N2.C1.D1.R1.S08: wrcmd2dqsstartlatency: 04
N4.C1.D0.R1.S09: Total Delay in PI ticks: TxDQ = 976
N6.C0.D1.R0.S17: Total Delay in PI ticks: TxDQ = 911
N0.C0.D1.R0.S16: RdPtrOffsetTxDq: 07
N2.C1.D1.R1.S08: RdPtrOffsetTxDq: 05
N4.C1.D0.R1.S10: Total Delay in PI ticks: TxDQ = 965
N6.C0.D1.R1.S00: wrcmd2dqsstartlatency: 04
N0.C0.D1.R0.S17: RdPtrOffsetTxDq: 07
N2.C1.D1.R1.S08: RdPtrOffsetTxDqs: 06
N4.C1.D0.R1.S11: Total Delay in PI ticks: TxDQ = 954
N6.C0.D1.R1.S00: RdPtrOffsetTxDq: 06
N0.C0.D1.R0.S00: Total Delay in PI ticks: TxDQ = 987
N2.C1.D1.R1.S08: PiTxDqs: 53
N4.C1.D0.R1.S12: Total Delay in PI ticks: TxDQ = 942
N6.C0.D1.R1.S00: RdPtrOffsetTxDqs: 07
N0.C0.D1.R0.S01: Total Delay in PI ticks: TxDQ = 971
N2.C1.D1.R1.S09: wrcmd2dqsstartlatency: 04
N4.C1.D0.R1.S13: Total Delay in PI ticks: TxDQ = 905
N6.C0.D1.R1.S00: PiTxDqs: 49
N0.C0.D1.R0.S02: Total Delay in PI ticks: TxDQ = 956
N2.C1.D1.R1.S09: RdPtrOffsetTxDq: 06
N4.C1.D0.R1.S14: Total Delay in PI ticks: TxDQ = 918
N6.C0.D1.R1.S01: wrcmd2dqsstartlatency: 04
N0.C0.D1.R0.S03: Total Delay in PI ticks: TxDQ = 941
N2.C1.D1.R1.S09: RdPtrOffsetTxDqs: 07
N4.C1.D0.R1.S15: Total Delay in PI ticks: TxDQ = 935
N6.C0.D1.R1.S01: RdPtrOffsetTxDq: 05
N0.C0.D1.R0.S04: Total Delay in PI ticks: TxDQ = 906
N2.C1.D1.R1.S09: PiTxDqs: 51
N4.C1.D0.R1.S16: Total Delay in PI ticks: TxDQ = 950
N6.C0.D1.R1.S01: RdPtrOffsetTxDqs: 07
N0.C0.D1.R0.S05: Total Delay in PI ticks: TxDQ = 925
N2.C1.D1.R1.S10: wrcmd2dqsstartlatency: 04
N4.C1.D0.R1.S17: Total Delay in PI ticks: TxDQ = 919
N6.C0.D1.R1.S01: PiTxDqs: 33
N0.C0.D1.R0.S06: Total Delay in PI ticks: TxDQ = 926
N2.C1.D1.R1.S10: RdPtrOffsetTxDq: 06
N4.C1.D1.R0.S00: wrcmd2dqsstartlatency: 04
N6.C0.D1.R1.S02: wrcmd2dqsstartlatency: 04
N0.C0.D1.R0.S07: Total Delay in PI ticks: TxDQ = 944
N2.C1.D1.R1.S10: RdPtrOffsetTxDqs: 07
N4.C1.D1.R0.S00: RdPtrOffsetTxDq: 06
N6.C0.D1.R1.S02: RdPtrOffsetTxDq: 05
N0.C0.D1.R0.S08: Total Delay in PI ticks: TxDQ = 915
N2.C1.D1.R1.S10: PiTxDqs: 35
N4.C1.D1.R0.S00: RdPtrOffsetTxDqs: 07
N6.C0.D1.R1.S02: RdPtrOffsetTxDqs: 07
N0.C0.D1.R0.S09: Total Delay in PI ticks: TxDQ = 984
N2.C1.D1.R1.S11: wrcmd2dqsstartlatency: 04
N4.C1.D1.R0.S00: PiTxDqs: 63
N6.C0.D1.R1.S02: PiTxDqs: 20
N0.C0.D1.R0.S10: Total Delay in PI ticks: TxDQ = 971
N2.C1.D1.R1.S11: RdPtrOffsetTxDq: 05
N4.C1.D1.R0.S01: wrcmd2dqsstartlatency: 04
N6.C0.D1.R1.S03: wrcmd2dqsstartlatency: 04
N0.C0.D1.R0.S11: Total Delay in PI ticks: TxDQ = 956
N2.C1.D1.R1.S11: RdPtrOffsetTxDqs: 07
N4.C1.D1.R0.S01: RdPtrOffsetTxDq: 06
N6.C0.D1.R1.S03: RdPtrOffsetTxDq: 05
N0.C0.D1.R0.S12: Total Delay in PI ticks: TxDQ = 943
N2.C1.D1.R1.S11: PiTxDqs: 28
N4.C1.D1.R0.S01: RdPtrOffsetTxDqs: 07
N6.C0.D1.R1.S03: RdPtrOffsetTxDqs: 07
N0.C0.D1.R0.S13: Total Delay in PI ticks: TxDQ = 908
N2.C1.D1.R1.S12: wrcmd2dqsstartlatency: 04
N4.C1.D1.R0.S01: PiTxDqs: 47
N6.C0.D1.R1.S03: PiTxDqs: 07
N0.C0.D1.R0.S14: Total Delay in PI ticks: TxDQ = 925
N2.C1.D1.R1.S12: RdPtrOffsetTxDq: 05
N4.C1.D1.R0.S02: wrcmd2dqsstartlatency: 04
N6.C0.D1.R1.S04: wrcmd2dqsstartlatency: 04
N0.C0.D1.R0.S15: Total Delay in PI ticks: TxDQ = 927
N2.C1.D1.R1.S12: RdPtrOffsetTxDqs: 07
N4.C1.D1.R0.S02: RdPtrOffsetTxDq: 05
N6.C0.D1.R1.S04: RdPtrOffsetTxDq: 05
N0.C0.D1.R0.S16: Total Delay in PI ticks: TxDQ = 946
N2.C1.D1.R1.S12: PiTxDqs: 14
N4.C1.D1.R0.S02: RdPtrOffsetTxDqs: 07
N6.C0.D1.R1.S04: RdPtrOffsetTxDqs: 06
N0.C0.D1.R0.S17: Total Delay in PI ticks: TxDQ = 916
N2.C1.D1.R1.S13: wrcmd2dqsstartlatency: 04
N4.C1.D1.R0.S02: PiTxDqs: 36
N6.C0.D1.R1.S04: PiTxDqs: 36
N0.C0.D1.R1.S00: wrcmd2dqsstartlatency: 04
N2.C1.D1.R1.S13: RdPtrOffsetTxDq: 05
N4.C1.D1.R0.S03: wrcmd2dqsstartlatency: 04
N6.C0.D1.R1.S05: wrcmd2dqsstartlatency: 04
N0.C0.D1.R1.S00: RdPtrOffsetTxDq: 06
N2.C1.D1.R1.S13: RdPtrOffsetTxDqs: 06
N4.C1.D1.R0.S03: RdPtrOffsetTxDq: 05
N6.C0.D1.R1.S05: RdPtrOffsetTxDq: 05
N0.C0.D1.R1.S00: RdPtrOffsetTxDqs: 07
N2.C1.D1.R1.S13: PiTxDqs: 43
N4.C1.D1.R0.S03: RdPtrOffsetTxDqs: 07
N6.C0.D1.R1.S05: RdPtrOffsetTxDqs: 06
N0.C0.D1.R1.S00: PiTxDqs: 56
N2.C1.D1.R1.S14: wrcmd2dqsstartlatency: 04
N4.C1.D1.R0.S03: PiTxDqs: 20
N6.C0.D1.R1.S05: PiTxDqs: 56
N0.C0.D1.R1.S01: wrcmd2dqsstartlatency: 04
N2.C1.D1.R1.S14: RdPtrOffsetTxDq: 05
N4.C1.D1.R0.S04: wrcmd2dqsstartlatency: 04
N6.C0.D1.R1.S06: wrcmd2dqsstartlatency: 04
N0.C0.D1.R1.S01: RdPtrOffsetTxDq: 06
N2.C1.D1.R1.S14: RdPtrOffsetTxDqs: 06
N4.C1.D1.R0.S04: RdPtrOffsetTxDq: 05
N6.C0.D1.R1.S06: RdPtrOffsetTxDq: 05
N0.C0.D1.R1.S01: RdPtrOffsetTxDqs: 07
N2.C1.D1.R1.S14: PiTxDqs: 57
N4.C1.D1.R0.S04: RdPtrOffsetTxDqs: 06
N6.C0.D1.R1.S06: RdPtrOffsetTxDqs: 06
N0.C0.D1.R1.S01: PiTxDqs: 40
N2.C1.D1.R1.S15: wrcmd2dqsstartlatency: 04
N4.C1.D1.R0.S04: PiTxDqs: 50
N6.C0.D1.R1.S06: PiTxDqs: 58
N0.C0.D1.R1.S02: wrcmd2dqsstartlatency: 04
N2.C1.D1.R1.S15: RdPtrOffsetTxDq: 05
N4.C1.D1.R0.S05: wrcmd2dqsstartlatency: 04
N6.C0.D1.R1.S07: wrcmd2dqsstartlatency: 04
N0.C0.D1.R1.S02: RdPtrOffsetTxDq: 05
N2.C1.D1.R1.S15: RdPtrOffsetTxDqs: 07
N4.C1.D1.R0.S05: RdPtrOffsetTxDq: 05
N6.C0.D1.R1.S07: RdPtrOffsetTxDq: 05
N0.C0.D1.R1.S02: RdPtrOffsetTxDqs: 07
N2.C1.D1.R1.S15: PiTxDqs: 04
N4.C1.D1.R0.S05: RdPtrOffsetTxDqs: 06
N6.C0.D1.R1.S07: RdPtrOffsetTxDqs: 07
N0.C0.D1.R1.S02: PiTxDqs: 30
N2.C1.D1.R1.S16: wrcmd2dqsstartlatency: 04
N4.C1.D1.R0.S05: PiTxDqs: 63
N6.C0.D1.R1.S07: PiTxDqs: 11
N0.C0.D1.R1.S03: wrcmd2dqsstartlatency: 04
N2.C1.D1.R1.S16: RdPtrOffsetTxDq: 05
N4.C1.D1.R0.S06: wrcmd2dqsstartlatency: 04
N6.C0.D1.R1.S08: wrcmd2dqsstartlatency: 04
N0.C0.D1.R1.S03: RdPtrOffsetTxDq: 05
N2.C1.D1.R1.S16: RdPtrOffsetTxDqs: 07
N4.C1.D1.R0.S06: RdPtrOffsetTxDq: 05
N6.C0.D1.R1.S08: RdPtrOffsetTxDq: 05
N0.C0.D1.R1.S03: RdPtrOffsetTxDqs: 07
N2.C1.D1.R1.S16: PiTxDqs: 25
N4.C1.D1.R0.S06: RdPtrOffsetTxDqs: 07
N6.C0.D1.R1.S08: RdPtrOffsetTxDqs: 06
N0.C0.D1.R1.S03: PiTxDqs: 13
N2.C1.D1.R1.S17: wrcmd2dqsstartlatency: 04
N4.C1.D1.R0.S06: PiTxDqs: 14
N6.C0.D1.R1.S08: PiTxDqs: 44
N0.C0.D1.R1.S04: wrcmd2dqsstartlatency: 04
N2.C1.D1.R1.S17: RdPtrOffsetTxDq: 05
N4.C1.D1.R0.S07: wrcmd2dqsstartlatency: 04
N6.C0.D1.R1.S09: wrcmd2dqsstartlatency: 04
N0.C0.D1.R1.S04: RdPtrOffsetTxDq: 05
N2.C1.D1.R1.S17: RdPtrOffsetTxDqs: 06
N4.C1.D1.R0.S07: RdPtrOffsetTxDq: 05
N6.C0.D1.R1.S09: RdPtrOffsetTxDq: 06
N0.C0.D1.R1.S04: RdPtrOffsetTxDqs: 06
N2.C1.D1.R1.S17: PiTxDqs: 53
N4.C1.D1.R0.S07: RdPtrOffsetTxDqs: 07
N6.C0.D1.R1.S09: RdPtrOffsetTxDqs: 07
N0.C0.D1.R1.S04: PiTxDqs: 42
N2.C1.D1.R1.S00: RdPtrOffsetTxDq: 07
N4.C1.D1.R0.S07: PiTxDqs: 30
N6.C0.D1.R1.S09: PiTxDqs: 49
N0.C0.D1.R1.S05: wrcmd2dqsstartlatency: 04
N2.C1.D1.R1.S01: RdPtrOffsetTxDq: 07
N4.C1.D1.R0.S08: wrcmd2dqsstartlatency: 04
N6.C0.D1.R1.S10: wrcmd2dqsstartlatency: 04
N0.C0.D1.R1.S05: RdPtrOffsetTxDq: 05
N2.C1.D1.R1.S02: RdPtrOffsetTxDq: 06
N4.C1.D1.R0.S08: RdPtrOffsetTxDq: 05
N6.C0.D1.R1.S10: RdPtrOffsetTxDq: 06
N0.C0.D1.R1.S05: RdPtrOffsetTxDqs: 06
N2.C1.D1.R1.S03: RdPtrOffsetTxDq: 06
N4.C1.D1.R0.S08: RdPtrOffsetTxDqs: 06
N6.C0.D1.R1.S10: RdPtrOffsetTxDqs: 07
N0.C0.D1.R1.S05: PiTxDqs: 63
N2.C1.D1.R1.S04: RdPtrOffsetTxDq: 06
N4.C1.D1.R0.S08: PiTxDqs: 63
N6.C0.D1.R1.S10: PiTxDqs: 35
N0.C0.D1.R1.S06: wrcmd2dqsstartlatency: 04
N2.C1.D1.R1.S05: RdPtrOffsetTxDq: 06
N4.C1.D1.R0.S09: wrcmd2dqsstartlatency: 04
N6.C0.D1.R1.S11: wrcmd2dqsstartlatency: 04
N0.C0.D1.R1.S06: RdPtrOffsetTxDq: 05
N2.C1.D1.R1.S06: RdPtrOffsetTxDq: 06
N4.C1.D1.R0.S09: RdPtrOffsetTxDq: 06
N6.C0.D1.R1.S11: RdPtrOffsetTxDq: 05
N0.C0.D1.R1.S06: RdPtrOffsetTxDqs: 06
N2.C1.D1.R1.S07: RdPtrOffsetTxDq: 06
N4.C1.D1.R0.S09: RdPtrOffsetTxDqs: 07
N6.C0.D1.R1.S11: RdPtrOffsetTxDqs: 07
N0.C0.D1.R1.S06: PiTxDqs: 63
N2.C1.D1.R1.S08: RdPtrOffsetTxDq: 06
N4.C1.D1.R0.S09: PiTxDqs: 60
N6.C0.D1.R1.S11: PiTxDqs: 22
N0.C0.D1.R1.S07: wrcmd2dqsstartlatency: 04
N2.C1.D1.R1.S09: RdPtrOffsetTxDq: 07
N4.C1.D1.R0.S10: wrcmd2dqsstartlatency: 04
N6.C0.D1.R1.S12: wrcmd2dqsstartlatency: 04
N0.C0.D1.R1.S07: RdPtrOffsetTxDq: 05
N2.C1.D1.R1.S10: RdPtrOffsetTxDq: 07
N4.C1.D1.R0.S10: RdPtrOffsetTxDq: 06
N6.C0.D1.R1.S12: RdPtrOffsetTxDq: 05
N0.C0.D1.R1.S07: RdPtrOffsetTxDqs: 07
N2.C1.D1.R1.S11: RdPtrOffsetTxDq: 06
N4.C1.D1.R0.S10: RdPtrOffsetTxDqs: 07
N6.C0.D1.R1.S12: RdPtrOffsetTxDqs: 07
N0.C0.D1.R1.S07: PiTxDqs: 17
N2.C1.D1.R1.S12: RdPtrOffsetTxDq: 06
N4.C1.D1.R0.S10: PiTxDqs: 44
N6.C0.D1.R1.S12: PiTxDqs: 07
N0.C0.D1.R1.S08: wrcmd2dqsstartlatency: 04
N2.C1.D1.R1.S13: RdPtrOffsetTxDq: 06
N4.C1.D1.R0.S11: wrcmd2dqsstartlatency: 04
N6.C0.D1.R1.S13: wrcmd2dqsstartlatency: 04
N0.C0.D1.R1.S08: RdPtrOffsetTxDq: 05
N2.C1.D1.R1.S14: RdPtrOffsetTxDq: 06
N4.C1.D1.R0.S11: RdPtrOffsetTxDq: 05
N6.C0.D1.R1.S13: RdPtrOffsetTxDq: 05
N0.C0.D1.R1.S08: RdPtrOffsetTxDqs: 06
N2.C1.D1.R1.S15: RdPtrOffsetTxDq: 06
N4.C1.D1.R0.S11: RdPtrOffsetTxDqs: 07
N6.C0.D1.R1.S13: RdPtrOffsetTxDqs: 06
N0.C0.D1.R1.S08: PiTxDqs: 47
N2.C1.D1.R1.S16: RdPtrOffsetTxDq: 06
N4.C1.D1.R0.S11: PiTxDqs: 35
N6.C0.D1.R1.S13: PiTxDqs: 36
N0.C0.D1.R1.S09: wrcmd2dqsstartlatency: 04
N2.C1.D1.R1.S17: RdPtrOffsetTxDq: 06
N4.C1.D1.R0.S12: wrcmd2dqsstartlatency: 04
N6.C0.D1.R1.S14: wrcmd2dqsstartlatency: 04
N0.C0.D1.R1.S09: RdPtrOffsetTxDq: 06
N2.C1.D1.R1.S00: RdPtrOffsetTxDq: 08
N4.C1.D1.R0.S12: RdPtrOffsetTxDq: 05
N6.C0.D1.R1.S14: RdPtrOffsetTxDq: 05
N0.C0.D1.R1.S09: RdPtrOffsetTxDqs: 07
N2.C1.D1.R1.S01: RdPtrOffsetTxDq: 08
N4.C1.D1.R0.S12: RdPtrOffsetTxDqs: 07
N6.C0.D1.R1.S14: RdPtrOffsetTxDqs: 06
N0.C0.D1.R1.S09: PiTxDqs: 56
N2.C1.D1.R1.S02: RdPtrOffsetTxDq: 07
N4.C1.D1.R0.S12: PiTxDqs: 20
N6.C0.D1.R1.S14: PiTxDqs: 55
N0.C0.D1.R1.S10: wrcmd2dqsstartlatency: 04
N2.C1.D1.R1.S03: RdPtrOffsetTxDq: 07
N4.C1.D1.R0.S13: wrcmd2dqsstartlatency: 04
N6.C0.D1.R1.S15: wrcmd2dqsstartlatency: 04
N0.C0.D1.R1.S10: RdPtrOffsetTxDq: 06
N2.C1.D1.R1.S04: RdPtrOffsetTxDq: 07
N4.C1.D1.R0.S13: RdPtrOffsetTxDq: 05
N6.C0.D1.R1.S15: RdPtrOffsetTxDq: 05
N0.C0.D1.R1.S10: RdPtrOffsetTxDqs: 07
N2.C1.D1.R1.S05: RdPtrOffsetTxDq: 07
N4.C1.D1.R0.S13: RdPtrOffsetTxDqs: 06
N6.C0.D1.R1.S15: RdPtrOffsetTxDqs: 06
N0.C0.D1.R1.S10: PiTxDqs: 42
N2.C1.D1.R1.S06: RdPtrOffsetTxDq: 07
N4.C1.D1.R0.S13: PiTxDqs: 50
N6.C0.D1.R1.S15: PiTxDqs: 58
N0.C0.D1.R1.S11: wrcmd2dqsstartlatency: 04
N2.C1.D1.R1.S07: RdPtrOffsetTxDq: 07
N4.C1.D1.R0.S14: wrcmd2dqsstartlatency: 04
N6.C0.D1.R1.S16: wrcmd2dqsstartlatency: 04
N0.C0.D1.R1.S11: RdPtrOffsetTxDq: 05
N2.C1.D1.R1.S08: RdPtrOffsetTxDq: 07
N4.C1.D1.R0.S14: RdPtrOffsetTxDq: 05
N6.C0.D1.R1.S16: RdPtrOffsetTxDq: 05
N0.C0.D1.R1.S11: RdPtrOffsetTxDqs: 07
N2.C1.D1.R1.S09: RdPtrOffsetTxDq: 08
N4.C1.D1.R0.S14: RdPtrOffsetTxDqs: 06
N6.C0.D1.R1.S16: RdPtrOffsetTxDqs: 07
N0.C0.D1.R1.S11: PiTxDqs: 30
N2.C1.D1.R1.S10: RdPtrOffsetTxDq: 08
N4.C1.D1.R0.S14: PiTxDqs: 63
N6.C0.D1.R1.S16: PiTxDqs: 08
N0.C0.D1.R1.S12: wrcmd2dqsstartlatency: 04
N2.C1.D1.R1.S11: RdPtrOffsetTxDq: 07
N4.C1.D1.R0.S15: wrcmd2dqsstartlatency: 04
N6.C0.D1.R1.S17: wrcmd2dqsstartlatency: 04
N0.C0.D1.R1.S12: RdPtrOffsetTxDq: 05
N2.C1.D1.R1.S12: RdPtrOffsetTxDq: 07
N4.C1.D1.R0.S15: RdPtrOffsetTxDq: 05
N6.C0.D1.R1.S17: RdPtrOffsetTxDq: 05
N0.C0.D1.R1.S12: RdPtrOffsetTxDqs: 07
N2.C1.D1.R1.S13: RdPtrOffsetTxDq: 07
N4.C1.D1.R0.S15: RdPtrOffsetTxDqs: 07
N6.C0.D1.R1.S17: RdPtrOffsetTxDqs: 06
N0.C0.D1.R1.S12: PiTxDqs: 14
N2.C1.D1.R1.S14: RdPtrOffsetTxDq: 07
N4.C1.D1.R0.S15: PiTxDqs: 14
N6.C0.D1.R1.S17: PiTxDqs: 44
N0.C0.D1.R1.S13: wrcmd2dqsstartlatency: 04
N2.C1.D1.R1.S15: RdPtrOffsetTxDq: 07
N4.C1.D1.R0.S16: wrcmd2dqsstartlatency: 04
N6.C0.D1.R1.S00: RdPtrOffsetTxDq: 07
N0.C0.D1.R1.S13: RdPtrOffsetTxDq: 05
N2.C1.D1.R1.S16: RdPtrOffsetTxDq: 07
N4.C1.D1.R0.S16: RdPtrOffsetTxDq: 05
N6.C0.D1.R1.S01: RdPtrOffsetTxDq: 06
N0.C0.D1.R1.S13: RdPtrOffsetTxDqs: 06
N2.C1.D1.R1.S17: RdPtrOffsetTxDq: 07
N4.C1.D1.R0.S16: RdPtrOffsetTxDqs: 07
N6.C0.D1.R1.S02: RdPtrOffsetTxDq: 06
N0.C0.D1.R1.S13: PiTxDqs: 45
N2.C1.D1.R1.S00: Total Delay in PI ticks: TxDQ = 982
N4.C1.D1.R0.S16: PiTxDqs: 33
N6.C0.D1.R1.S03: RdPtrOffsetTxDq: 06
N0.C0.D1.R1.S14: wrcmd2dqsstartlatency: 04
N2.C1.D1.R1.S01: Total Delay in PI ticks: TxDQ = 963
N4.C1.D1.R0.S17: wrcmd2dqsstartlatency: 04
N6.C0.D1.R1.S04: RdPtrOffsetTxDq: 06
N0.C0.D1.R1.S14: RdPtrOffsetTxDq: 05
N2.C1.D1.R1.S02: Total Delay in PI ticks: TxDQ = 955
N4.C1.D1.R0.S17: RdPtrOffsetTxDq: 05
N6.C0.D1.R1.S05: RdPtrOffsetTxDq: 06
N0.C0.D1.R1.S14: RdPtrOffsetTxDqs: 06
N2.C1.D1.R1.S03: Total Delay in PI ticks: TxDQ = 940
N4.C1.D1.R0.S17: RdPtrOffsetTxDqs: 06
N6.C0.D1.R1.S06: RdPtrOffsetTxDq: 06
N0.C0.D1.R1.S14: PiTxDqs: 62
N2.C1.D1.R1.S04: Total Delay in PI ticks: TxDQ = 907
N4.C1.D1.R0.S17: PiTxDqs: 62
N6.C0.D1.R1.S07: RdPtrOffsetTxDq: 06
N0.C0.D1.R1.S15: wrcmd2dqsstartlatency: 04
N2.C1.D1.R1.S05: Total Delay in PI ticks: TxDQ = 920
N4.C1.D1.R0.S00: RdPtrOffsetTxDq: 07
N6.C0.D1.R1.S08: RdPtrOffsetTxDq: 06
N0.C0.D1.R1.S15: RdPtrOffsetTxDq: 05
N2.C1.D1.R1.S06: Total Delay in PI ticks: TxDQ = 935
N4.C1.D1.R0.S01: RdPtrOffsetTxDq: 07
N6.C0.D1.R1.S09: RdPtrOffsetTxDq: 07
N0.C0.D1.R1.S15: RdPtrOffsetTxDqs: 07
N2.C1.D1.R1.S07: Total Delay in PI ticks: TxDQ = 951
N4.C1.D1.R0.S02: RdPtrOffsetTxDq: 06
N6.C0.D1.R1.S10: RdPtrOffsetTxDq: 07
N0.C0.D1.R1.S15: PiTxDqs: 00
N2.C1.D1.R1.S08: Total Delay in PI ticks: TxDQ = 916
N4.C1.D1.R0.S03: RdPtrOffsetTxDq: 06
N6.C0.D1.R1.S11: RdPtrOffsetTxDq: 06
N0.C0.D1.R1.S16: wrcmd2dqsstartlatency: 04
N2.C1.D1.R1.S09: Total Delay in PI ticks: TxDQ = 979
N4.C1.D1.R0.S04: RdPtrOffsetTxDq: 06
N6.C0.D1.R1.S12: RdPtrOffsetTxDq: 06
N0.C0.D1.R1.S16: RdPtrOffsetTxDq: 05
N2.C1.D1.R1.S10: Total Delay in PI ticks: TxDQ = 962
N4.C1.D1.R0.S05: RdPtrOffsetTxDq: 06
N6.C0.D1.R1.S13: RdPtrOffsetTxDq: 06
N0.C0.D1.R1.S16: RdPtrOffsetTxDqs: 07
N2.C1.D1.R1.S11: Total Delay in PI ticks: TxDQ = 957
N4.C1.D1.R0.S06: RdPtrOffsetTxDq: 06
N6.C0.D1.R1.S14: RdPtrOffsetTxDq: 06
N0.C0.D1.R1.S16: PiTxDqs: 16
N2.C1.D1.R1.S12: Total Delay in PI ticks: TxDQ = 942
N4.C1.D1.R0.S07: RdPtrOffsetTxDq: 06
N6.C0.D1.R1.S15: RdPtrOffsetTxDq: 06
N0.C0.D1.R1.S17: wrcmd2dqsstartlatency: 04
N2.C1.D1.R1.S13: Total Delay in PI ticks: TxDQ = 908
N4.C1.D1.R0.S08: RdPtrOffsetTxDq: 06
N6.C0.D1.R1.S16: RdPtrOffsetTxDq: 06
N0.C0.D1.R1.S17: RdPtrOffsetTxDq: 05
N2.C1.D1.R1.S14: Total Delay in PI ticks: TxDQ = 922
N4.C1.D1.R0.S09: RdPtrOffsetTxDq: 07
N6.C0.D1.R1.S17: RdPtrOffsetTxDq: 06
N0.C0.D1.R1.S17: RdPtrOffsetTxDqs: 06
N2.C1.D1.R1.S15: Total Delay in PI ticks: TxDQ = 933
N4.C1.D1.R0.S10: RdPtrOffsetTxDq: 07
N6.C0.D1.R1.S00: RdPtrOffsetTxDq: 08
N0.C0.D1.R1.S17: PiTxDqs: 49
N2.C1.D1.R1.S16: Total Delay in PI ticks: TxDQ = 952
N4.C1.D1.R0.S11: RdPtrOffsetTxDq: 06
N6.C0.D1.R1.S01: RdPtrOffsetTxDq: 07
N0.C0.D1.R1.S00: RdPtrOffsetTxDq: 07
N2.C1.D1.R1.S17: Total Delay in PI ticks: TxDQ = 917
N4.C1.D1.R0.S12: RdPtrOffsetTxDq: 06
N6.C0.D1.R1.S02: RdPtrOffsetTxDq: 07
N0.C0.D1.R1.S01: RdPtrOffsetTxDq: 07
N2.C1: Calculating Optimimum DQ/DQS Values
N4.C1.D1.R0.S13: RdPtrOffsetTxDq: 06
N6.C0.D1.R1.S03: RdPtrOffsetTxDq: 07
N0.C0.D1.R1.S02: RdPtrOffsetTxDq: 06
N4.C1.D1.R0.S14: RdPtrOffsetTxDq: 06
N6.C0.D1.R1.S04: RdPtrOffsetTxDq: 07
N0.C0.D1.R1.S03: RdPtrOffsetTxDq: 06
START_DATA_TX_DQ
N4.C1.D1.R0.S15: RdPtrOffsetTxDq: 06
N6.C0.D1.R1.S05: RdPtrOffsetTxDq: 07
N0.C0.D1.R1.S04: RdPtrOffsetTxDq: 06
N2.C1.S00: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 009, RdPtrOffsetTxDqs = 009
N4.C1.D1.R0.S16: RdPtrOffsetTxDq: 06
N6.C0.D1.R1.S06: RdPtrOffsetTxDq: 07
N0.C0.D1.R1.S05: RdPtrOffsetTxDq: 06
N2.C1.S00: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 009, RdPtrOffsetTxDqs = 009
N4.C1.D1.R0.S17: RdPtrOffsetTxDq: 06
N6.C0.D1.R1.S07: RdPtrOffsetTxDq: 07
N0.C0.D1.R1.S06: RdPtrOffsetTxDq: 06
N2.C1.S01: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 009
N4.C1.D1.R0.S00: RdPtrOffsetTxDq: 08
N6.C0.D1.R1.S08: RdPtrOffsetTxDq: 07
N0.C0.D1.R1.S07: RdPtrOffsetTxDq: 06
N2.C1.S01: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 009
N4.C1.D1.R0.S01: RdPtrOffsetTxDq: 08
N6.C0.D1.R1.S09: RdPtrOffsetTxDq: 08
N0.C0.D1.R1.S08: RdPtrOffsetTxDq: 06
N2.C1.S02: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 009
N4.C1.D1.R0.S02: RdPtrOffsetTxDq: 07
N6.C0.D1.R1.S10: RdPtrOffsetTxDq: 08
N0.C0.D1.R1.S09: RdPtrOffsetTxDq: 07
N2.C1.S02: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 009
N4.C1.D1.R0.S03: RdPtrOffsetTxDq: 07
N6.C0.D1.R1.S11: RdPtrOffsetTxDq: 07
N0.C0.D1.R1.S10: RdPtrOffsetTxDq: 07
N2.C1.S03: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 009
N4.C1.D1.R0.S04: RdPtrOffsetTxDq: 07
N6.C0.D1.R1.S12: RdPtrOffsetTxDq: 07
N0.C0.D1.R1.S11: RdPtrOffsetTxDq: 06
N2.C1.S03: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 009
N4.C1.D1.R0.S05: RdPtrOffsetTxDq: 07
N6.C0.D1.R1.S13: RdPtrOffsetTxDq: 07
N0.C0.D1.R1.S12: RdPtrOffsetTxDq: 06
N2.C1.S04: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 008
N4.C1.D1.R0.S06: RdPtrOffsetTxDq: 07
N6.C0.D1.R1.S14: RdPtrOffsetTxDq: 07
N0.C0.D1.R1.S13: RdPtrOffsetTxDq: 06
N2.C1.S04: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 008
N4.C1.D1.R0.S07: RdPtrOffsetTxDq: 07
N6.C0.D1.R1.S15: RdPtrOffsetTxDq: 07
N0.C0.D1.R1.S14: RdPtrOffsetTxDq: 06
N2.C1.S05: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 008
N4.C1.D1.R0.S08: RdPtrOffsetTxDq: 07
N6.C0.D1.R1.S16: RdPtrOffsetTxDq: 07
N0.C0.D1.R1.S15: RdPtrOffsetTxDq: 06
N2.C1.S05: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 008
N4.C1.D1.R0.S09: RdPtrOffsetTxDq: 08
N6.C0.D1.R1.S17: RdPtrOffsetTxDq: 07
N0.C0.D1.R1.S16: RdPtrOffsetTxDq: 06
N2.C1.S06: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 009
N4.C1.D1.R0.S10: RdPtrOffsetTxDq: 08
N6.C0.D1.R1.S00: Total Delay in PI ticks: TxDQ = 980
N0.C0.D1.R1.S17: RdPtrOffsetTxDq: 06
N2.C1.S06: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 009
N4.C1.D1.R0.S11: RdPtrOffsetTxDq: 07
N6.C0.D1.R1.S01: Total Delay in PI ticks: TxDQ = 962
N0.C0.D1.R1.S00: RdPtrOffsetTxDq: 08
N2.C1.S07: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 009
N4.C1.D1.R0.S12: RdPtrOffsetTxDq: 07
N6.C0.D1.R1.S02: Total Delay in PI ticks: TxDQ = 948
N0.C0.D1.R1.S01: RdPtrOffsetTxDq: 08
N2.C1.S07: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 009
N4.C1.D1.R0.S13: RdPtrOffsetTxDq: 07
N6.C0.D1.R1.S03: Total Delay in PI ticks: TxDQ = 935
N0.C0.D1.R1.S02: RdPtrOffsetTxDq: 07
N2.C1.S08: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 008
N4.C1.D1.R0.S14: RdPtrOffsetTxDq: 07
N6.C0.D1.R1.S04: Total Delay in PI ticks: TxDQ = 899
N0.C0.D1.R1.S03: RdPtrOffsetTxDq: 07
N2.C1.S08: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 008
N4.C1.D1.R0.S15: RdPtrOffsetTxDq: 07
N6.C0.D1.R1.S05: Total Delay in PI ticks: TxDQ = 919
N0.C0.D1.R1.S04: RdPtrOffsetTxDq: 07
N2.C1.D0.R0.S00: TxDqs: plus1 = 1, minus1 = 0, PI = 47, DB = 0
N4.C1.D1.R0.S16: RdPtrOffsetTxDq: 07
N6.C0.D1.R1.S06: Total Delay in PI ticks: TxDQ = 921
N0.C0.D1.R1.S05: RdPtrOffsetTxDq: 07
N2.C1.D0.R0.S00: TxDq : plus1 = 1, minus1 = 0, PI = 18, DB = 0
N4.C1.D1.R0.S17: RdPtrOffsetTxDq: 07
N6.C0.D1.R1.S07: Total Delay in PI ticks: TxDQ = 938
N0.C0.D1.R1.S06: RdPtrOffsetTxDq: 07
N2.C1.D0.R0.S01: TxDqs: plus1 = 1, minus1 = 0, PI = 31, DB = 0
N4.C1.D1.R0.S00: Total Delay in PI ticks: TxDQ = 989
N6.C0.D1.R1.S08: Total Delay in PI ticks: TxDQ = 908
N0.C0.D1.R1.S07: RdPtrOffsetTxDq: 07
N2.C1.D0.R0.S01: TxDq : plus1 = 1, minus1 = 0, PI = 62, DB = 1
N4.C1.D1.R0.S01: Total Delay in PI ticks: TxDQ = 971
N6.C0.D1.R1.S09: Total Delay in PI ticks: TxDQ = 977
N0.C0.D1.R1.S08: RdPtrOffsetTxDq: 07
N2.C1.D0.R0.S02: TxDqs: plus1 = 1, minus1 = 0, PI = 23, DB = 0
N4.C1.D1.R0.S02: Total Delay in PI ticks: TxDQ = 962
N6.C0.D1.R1.S10: Total Delay in PI ticks: TxDQ = 962
N0.C0.D1.R1.S09: RdPtrOffsetTxDq: 08
N2.C1.D0.R0.S02: TxDq : plus1 = 1, minus1 = 0, PI = 56, DB = 1
N4.C1.D1.R0.S03: Total Delay in PI ticks: TxDQ = 944
N6.C0.D1.R1.S11: Total Delay in PI ticks: TxDQ = 948
N0.C0.D1.R1.S10: RdPtrOffsetTxDq: 08
N2.C1.D0.R0.S03: TxDqs: plus1 = 1, minus1 = 0, PI = 06, DB = 1
N4.C1.D1.R0.S04: Total Delay in PI ticks: TxDQ = 911
N6.C0.D1.R1.S12: Total Delay in PI ticks: TxDQ = 933
N0.C0.D1.R1.S11: RdPtrOffsetTxDq: 07
N2.C1.D0.R0.S03: TxDq : plus1 = 1, minus1 = 0, PI = 39, DB = 0
N4.C1.D1.R0.S05: Total Delay in PI ticks: TxDQ = 923
N6.C0.D1.R1.S13: Total Delay in PI ticks: TxDQ = 898
N0.C0.D1.R1.S12: RdPtrOffsetTxDq: 07
N2.C1.D0.R0.S04: TxDqs: plus1 = 1, minus1 = 0, PI = 38, DB = 0
N4.C1.D1.R0.S06: Total Delay in PI ticks: TxDQ = 938
N6.C0.D1.R1.S14: Total Delay in PI ticks: TxDQ = 918
N0.C0.D1.R1.S13: RdPtrOffsetTxDq: 07
N2.C1.D0.R0.S04: TxDq : plus1 = 1, minus1 = 0, PI = 07, DB = 1
N4.C1.D1.R0.S07: Total Delay in PI ticks: TxDQ = 954
N6.C0.D1.R1.S15: Total Delay in PI ticks: TxDQ = 920
N0.C0.D1.R1.S14: RdPtrOffsetTxDq: 07
N2.C1.D0.R0.S05: TxDqs: plus1 = 1, minus1 = 0, PI = 52, DB = 1
N4.C1.D1.R0.S08: Total Delay in PI ticks: TxDQ = 924
N6.C0.D1.R1.S16: Total Delay in PI ticks: TxDQ = 935
N0.C0.D1.R1.S15: RdPtrOffsetTxDq: 07
N2.C1.D0.R0.S05: TxDq : plus1 = 1, minus1 = 0, PI = 19, DB = 0
N4.C1.D1.R0.S09: Total Delay in PI ticks: TxDQ = 985
N6.C0.D1.R1.S17: Total Delay in PI ticks: TxDQ = 907
N0.C0.D1.R1.S16: RdPtrOffsetTxDq: 07
N2.C1.D0.R0.S06: TxDqs: plus1 = 1, minus1 = 0, PI = 01, DB = 1
N4.C1.D1.R0.S10: Total Delay in PI ticks: TxDQ = 970
N6.C0: Calculating Optimimum DQ/DQS Values
N0.C0.D1.R1.S17: RdPtrOffsetTxDq: 07
N2.C1.D0.R0.S06: TxDq : plus1 = 1, minus1 = 0, PI = 33, DB = 0
N4.C1.D1.R0.S11: Total Delay in PI ticks: TxDQ = 961
N0.C0.D1.R1.S00: Total Delay in PI ticks: TxDQ = 983
N2.C1.D0.R0.S07: TxDqs: plus1 = 1, minus1 = 0, PI = 18, DB = 0
N4.C1.D1.R0.S12: Total Delay in PI ticks: TxDQ = 946
START_DATA_TX_DQ
N0.C0.D1.R1.S01: Total Delay in PI ticks: TxDQ = 967
N2.C1.D0.R0.S07: TxDq : plus1 = 1, minus1 = 0, PI = 48, DB = 0
N4.C1.D1.R0.S13: Total Delay in PI ticks: TxDQ = 911
N6.C0.S00: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 009, RdPtrOffsetTxDqs = 009
N0.C0.D1.R1.S02: Total Delay in PI ticks: TxDQ = 954
N2.C1.D0.R0.S08: TxDqs: plus1 = 1, minus1 = 0, PI = 52, DB = 1
N4.C1.D1.R0.S14: Total Delay in PI ticks: TxDQ = 922
N6.C0.S00: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 009, RdPtrOffsetTxDqs = 009
N0.C0.D1.R1.S03: Total Delay in PI ticks: TxDQ = 938
N2.C1.D0.R0.S08: TxDq : plus1 = 1, minus1 = 0, PI = 20, DB = 0
N4.C1.D1.R0.S15: Total Delay in PI ticks: TxDQ = 939
N6.C0.S01: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 009
N0.C0.D1.R1.S04: Total Delay in PI ticks: TxDQ = 905
N2.C1.D0.R0.S09: TxDqs: plus1 = 1, minus1 = 0, PI = 47, DB = 0
N4.C1.D1.R0.S16: Total Delay in PI ticks: TxDQ = 957
N6.C0.S01: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 009
N0.C0.D1.R1.S05: Total Delay in PI ticks: TxDQ = 924
N2.C1.D0.R0.S09: TxDq : plus1 = 1, minus1 = 0, PI = 17, DB = 0
N4.C1.D1.R0.S17: Total Delay in PI ticks: TxDQ = 923
N6.C0.S02: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 009
N0.C0.D1.R1.S06: Total Delay in PI ticks: TxDQ = 926
N2.C1.D0.R0.S10: TxDqs: plus1 = 1, minus1 = 0, PI = 31, DB = 0
N4.C1.D1.R1.S00: wrcmd2dqsstartlatency: 04
N6.C0.S02: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 009
N0.C0.D1.R1.S07: Total Delay in PI ticks: TxDQ = 943
N2.C1.D0.R0.S10: TxDq : plus1 = 1, minus1 = 0, PI = 63, DB = 1
N4.C1.D1.R1.S00: RdPtrOffsetTxDq: 06
N6.C0.S03: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 009
N0.C0.D1.R1.S08: Total Delay in PI ticks: TxDQ = 908
N2.C1.D0.R0.S11: TxDqs: plus1 = 1, minus1 = 0, PI = 23, DB = 0
N4.C1.D1.R1.S00: RdPtrOffsetTxDqs: 07
N6.C0.S03: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 009
N0.C0.D1.R1.S09: Total Delay in PI ticks: TxDQ = 982
N2.C1.D0.R0.S11: TxDq : plus1 = 1, minus1 = 0, PI = 58, DB = 1
N4.C1.D1.R1.S00: PiTxDqs: 58
N6.C0.S04: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 008
N0.C0.D1.R1.S10: Total Delay in PI ticks: TxDQ = 969
N2.C1.D0.R0.S12: TxDqs: plus1 = 1, minus1 = 0, PI = 06, DB = 1
N4.C1.D1.R1.S01: wrcmd2dqsstartlatency: 04
N6.C0.S04: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 008
N0.C0.D1.R1.S11: Total Delay in PI ticks: TxDQ = 954
N2.C1.D0.R0.S12: TxDq : plus1 = 1, minus1 = 0, PI = 39, DB = 0
N4.C1.D1.R1.S01: RdPtrOffsetTxDq: 06
N6.C0.S05: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 008
N0.C0.D1.R1.S12: Total Delay in PI ticks: TxDQ = 940
N2.C1.D0.R0.S13: TxDqs: plus1 = 1, minus1 = 0, PI = 37, DB = 0
N4.C1.D1.R1.S01: RdPtrOffsetTxDqs: 07
N6.C0.S05: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 008
N0.C0.D1.R1.S13: Total Delay in PI ticks: TxDQ = 906
N2.C1.D0.R0.S13: TxDq : plus1 = 1, minus1 = 0, PI = 07, DB = 1
N4.C1.D1.R1.S01: PiTxDqs: 43
N6.C0.S06: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 008
N0.C0.D1.R1.S14: Total Delay in PI ticks: TxDQ = 924
N2.C1.D0.R0.S14: TxDqs: plus1 = 1, minus1 = 0, PI = 52, DB = 1
N4.C1.D1.R1.S02: wrcmd2dqsstartlatency: 04
N6.C0.S06: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 008
N0.C0.D1.R1.S15: Total Delay in PI ticks: TxDQ = 925
N2.C1.D0.R0.S14: TxDq : plus1 = 1, minus1 = 0, PI = 21, DB = 0
N4.C1.D1.R1.S02: RdPtrOffsetTxDq: 05
N6.C0.S07: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 009
N0.C0.D1.R1.S16: Total Delay in PI ticks: TxDQ = 942
N2.C1.D0.R0.S15: TxDqs: plus1 = 1, minus1 = 0, PI = 02, DB = 1
N4.C1.D1.R1.S02: RdPtrOffsetTxDqs: 07
N6.C0.S07: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 009
N0.C0.D1.R1.S17: Total Delay in PI ticks: TxDQ = 910
N2.C1.D0.R0.S15: TxDq : plus1 = 1, minus1 = 0, PI = 35, DB = 0
N4.C1.D1.R1.S02: PiTxDqs: 33
N6.C0.S08: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 008
N0.C0: Calculating Optimimum DQ/DQS Values
N2.C1.D0.R0.S16: TxDqs: plus1 = 1, minus1 = 0, PI = 19, DB = 0
N4.C1.D1.R1.S03: wrcmd2dqsstartlatency: 04
N6.C0.S08: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 008
N2.C1.D0.R0.S16: TxDq : plus1 = 1, minus1 = 0, PI = 50, DB = 1
N4.C1.D1.R1.S03: RdPtrOffsetTxDq: 05
N6.C0.D0.R0.S00: TxDqs: plus1 = 1, minus1 = 0, PI = 51, DB = 1
START_DATA_TX_DQ
N2.C1.D0.R0.S17: TxDqs: plus1 = 1, minus1 = 0, PI = 52, DB = 1
N4.C1.D1.R1.S03: RdPtrOffsetTxDqs: 07
N6.C0.D0.R0.S00: TxDq : plus1 = 1, minus1 = 0, PI = 22, DB = 0
N0.C0.S00: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 009, RdPtrOffsetTxDqs = 009
N2.C1.D0.R0.S17: TxDq : plus1 = 1, minus1 = 0, PI = 21, DB = 0
N4.C1.D1.R1.S03: PiTxDqs: 19
N6.C0.D0.R0.S01: TxDqs: plus1 = 1, minus1 = 0, PI = 29, DB = 0
N0.C0.S00: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 009, RdPtrOffsetTxDqs = 009
N2.C1.D0.R1.S00: TxDqs: plus1 = 1, minus1 = 0, PI = 47, DB = 0
N4.C1.D1.R1.S04: wrcmd2dqsstartlatency: 04
N6.C0.D0.R0.S01: TxDq : plus1 = 1, minus1 = 0, PI = 62, DB = 1
N0.C0.S01: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 009, RdPtrOffsetTxDqs = 009
N2.C1.D0.R1.S00: TxDq : plus1 = 1, minus1 = 0, PI = 18, DB = 0
N4.C1.D1.R1.S04: RdPtrOffsetTxDq: 05
N6.C0.D0.R0.S02: TxDqs: plus1 = 1, minus1 = 0, PI = 19, DB = 0
N0.C0.S01: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 009, RdPtrOffsetTxDqs = 009
N2.C1.D0.R1.S01: TxDqs: plus1 = 1, minus1 = 0, PI = 31, DB = 0
N4.C1.D1.R1.S04: RdPtrOffsetTxDqs: 06
N6.C0.D0.R0.S02: TxDq : plus1 = 1, minus1 = 0, PI = 51, DB = 1
N0.C0.S02: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 009
N2.C1.D0.R1.S01: TxDq : plus1 = 1, minus1 = 0, PI = 62, DB = 1
N4.C1.D1.R1.S04: PiTxDqs: 50
N6.C0.D0.R0.S03: TxDqs: plus1 = 1, minus1 = 0, PI = 02, DB = 1
N0.C0.S02: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 009
N2.C1.D0.R1.S02: TxDqs: plus1 = 1, minus1 = 0, PI = 23, DB = 0
N4.C1.D1.R1.S05: wrcmd2dqsstartlatency: 04
N6.C0.D0.R0.S03: TxDq : plus1 = 1, minus1 = 0, PI = 33, DB = 0
N0.C0.S03: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 009
N2.C1.D0.R1.S02: TxDq : plus1 = 1, minus1 = 0, PI = 56, DB = 1
N4.C1.D1.R1.S05: RdPtrOffsetTxDq: 05
N6.C0.D0.R0.S04: TxDqs: plus1 = 1, minus1 = 0, PI = 33, DB = 0
N0.C0.S03: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 009
N2.C1.D0.R1.S03: TxDqs: plus1 = 1, minus1 = 0, PI = 06, DB = 1
N4.C1.D1.R1.S05: RdPtrOffsetTxDqs: 06
N6.C0.D0.R0.S04: TxDq : plus1 = 1, minus1 = 0, PI = 02, DB = 1
N0.C0.S04: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 008
N2.C1.D0.R1.S03: TxDq : plus1 = 1, minus1 = 0, PI = 39, DB = 0
N4.C1.D1.R1.S05: PiTxDqs: 63
N6.C0.D0.R0.S05: TxDqs: plus1 = 1, minus1 = 0, PI = 52, DB = 1
N0.C0.S04: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 008
N2.C1.D0.R1.S04: TxDqs: plus1 = 1, minus1 = 0, PI = 38, DB = 0
N4.C1.D1.R1.S06: wrcmd2dqsstartlatency: 04
N6.C0.D0.R0.S05: TxDq : plus1 = 1, minus1 = 0, PI = 19, DB = 0
N0.C0.S05: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 008
N2.C1.D0.R1.S04: TxDq : plus1 = 1, minus1 = 0, PI = 07, DB = 1
N4.C1.D1.R1.S06: RdPtrOffsetTxDq: 05
N6.C0.D0.R0.S06: TxDqs: plus1 = 1, minus1 = 0, PI = 55, DB = 1
N0.C0.S05: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 008
N2.C1.D0.R1.S05: TxDqs: plus1 = 1, minus1 = 0, PI = 52, DB = 1
N4.C1.D1.R1.S06: RdPtrOffsetTxDqs: 07
N6.C0.D0.R0.S06: TxDq : plus1 = 1, minus1 = 0, PI = 24, DB = 0
N0.C0.S06: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 008
N2.C1.D0.R1.S05: TxDq : plus1 = 1, minus1 = 0, PI = 19, DB = 0
N4.C1.D1.R1.S06: PiTxDqs: 09
N6.C0.D0.R0.S07: TxDqs: plus1 = 1, minus1 = 0, PI = 07, DB = 1
N0.C0.S06: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 008
N2.C1.D0.R1.S06: TxDqs: plus1 = 1, minus1 = 0, PI = 01, DB = 1
N4.C1.D1.R1.S07: wrcmd2dqsstartlatency: 04
N6.C0.D0.R0.S07: TxDq : plus1 = 1, minus1 = 0, PI = 37, DB = 0
N0.C0.S07: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 009
N2.C1.D0.R1.S06: TxDq : plus1 = 1, minus1 = 0, PI = 33, DB = 0
N4.C1.D1.R1.S07: RdPtrOffsetTxDq: 05
N6.C0.D0.R0.S08: TxDqs: plus1 = 1, minus1 = 0, PI = 45, DB = 0
N0.C0.S07: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 009
N2.C1.D0.R1.S07: TxDqs: plus1 = 1, minus1 = 0, PI = 18, DB = 0
N4.C1.D1.R1.S07: RdPtrOffsetTxDqs: 07
N6.C0.D0.R0.S08: TxDq : plus1 = 1, minus1 = 0, PI = 15, DB = 1
N0.C0.S08: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 008
N2.C1.D0.R1.S07: TxDq : plus1 = 1, minus1 = 0, PI = 48, DB = 0
N4.C1.D1.R1.S07: PiTxDqs: 29
N6.C0.D0.R0.S09: TxDqs: plus1 = 1, minus1 = 0, PI = 50, DB = 1
N0.C0.S08: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 008
N2.C1.D0.R1.S08: TxDqs: plus1 = 1, minus1 = 0, PI = 52, DB = 1
N4.C1.D1.R1.S08: wrcmd2dqsstartlatency: 04
N6.C0.D0.R0.S09: TxDq : plus1 = 1, minus1 = 0, PI = 17, DB = 0
N0.C0.D0.R0.S00: TxDqs: plus1 = 1, minus1 = 0, PI = 52, DB = 1
N2.C1.D0.R1.S08: TxDq : plus1 = 1, minus1 = 0, PI = 20, DB = 0
N4.C1.D1.R1.S08: RdPtrOffsetTxDq: 05
N6.C0.D0.R0.S10: TxDqs: plus1 = 1, minus1 = 0, PI = 30, DB = 0
N0.C0.D0.R0.S00: TxDq : plus1 = 1, minus1 = 0, PI = 20, DB = 0
N2.C1.D0.R1.S09: TxDqs: plus1 = 1, minus1 = 0, PI = 47, DB = 0
N4.C1.D1.R1.S08: RdPtrOffsetTxDqs: 06
N6.C0.D0.R0.S10: TxDq : plus1 = 1, minus1 = 0, PI = 61, DB = 1
N0.C0.D0.R0.S01: TxDqs: plus1 = 1, minus1 = 0, PI = 35, DB = 0
N2.C1.D0.R1.S09: TxDq : plus1 = 1, minus1 = 0, PI = 17, DB = 0
N4.C1.D1.R1.S08: PiTxDqs: 59
N6.C0.D0.R0.S11: TxDqs: plus1 = 1, minus1 = 0, PI = 18, DB = 0
N0.C0.D0.R0.S01: TxDq : plus1 = 1, minus1 = 0, PI = 02, DB = 1
N2.C1.D0.R1.S10: TxDqs: plus1 = 1, minus1 = 0, PI = 31, DB = 0
N4.C1.D1.R1.S09: wrcmd2dqsstartlatency: 04
N6.C0.D0.R0.S11: TxDq : plus1 = 1, minus1 = 0, PI = 50, DB = 1
N0.C0.D0.R0.S02: TxDqs: plus1 = 1, minus1 = 0, PI = 24, DB = 0
N2.C1.D0.R1.S10: TxDq : plus1 = 1, minus1 = 0, PI = 63, DB = 1
N4.C1.D1.R1.S09: RdPtrOffsetTxDq: 06
N6.C0.D0.R0.S12: TxDqs: plus1 = 1, minus1 = 0, PI = 05, DB = 1
N0.C0.D0.R0.S02: TxDq : plus1 = 1, minus1 = 0, PI = 54, DB = 1
N2.C1.D0.R1.S11: TxDqs: plus1 = 1, minus1 = 0, PI = 23, DB = 0
N4.C1.D1.R1.S09: RdPtrOffsetTxDqs: 07
N6.C0.D0.R0.S12: TxDq : plus1 = 1, minus1 = 0, PI = 36, DB = 0
N0.C0.D0.R0.S03: TxDqs: plus1 = 1, minus1 = 0, PI = 05, DB = 1
N2.C1.D0.R1.S11: TxDq : plus1 = 1, minus1 = 0, PI = 58, DB = 1
N4.C1.D1.R1.S09: PiTxDqs: 57
N6.C0.D0.R0.S13: TxDqs: plus1 = 1, minus1 = 0, PI = 34, DB = 0
N0.C0.D0.R0.S03: TxDq : plus1 = 1, minus1 = 0, PI = 36, DB = 0
N2.C1.D0.R1.S12: TxDqs: plus1 = 1, minus1 = 0, PI = 06, DB = 1
N4.C1.D1.R1.S10: wrcmd2dqsstartlatency: 04
N6.C0.D0.R0.S13: TxDq : plus1 = 1, minus1 = 0, PI = 02, DB = 1
N0.C0.D0.R0.S04: TxDqs: plus1 = 1, minus1 = 0, PI = 38, DB = 0
N2.C1.D0.R1.S12: TxDq : plus1 = 1, minus1 = 0, PI = 39, DB = 0
N4.C1.D1.R1.S10: RdPtrOffsetTxDq: 06
N6.C0.D0.R0.S14: TxDqs: plus1 = 1, minus1 = 0, PI = 52, DB = 1
N0.C0.D0.R0.S04: TxDq : plus1 = 1, minus1 = 0, PI = 06, DB = 1
N2.C1.D0.R1.S13: TxDqs: plus1 = 1, minus1 = 0, PI = 37, DB = 0
N4.C1.D1.R1.S10: RdPtrOffsetTxDqs: 07
N6.C0.D0.R0.S14: TxDq : plus1 = 1, minus1 = 0, PI = 20, DB = 0
N0.C0.D0.R0.S05: TxDqs: plus1 = 1, minus1 = 0, PI = 54, DB = 1
N2.C1.D0.R1.S13: TxDq : plus1 = 1, minus1 = 0, PI = 07, DB = 1
N4.C1.D1.R1.S10: PiTxDqs: 42
N6.C0.D0.R0.S15: TxDqs: plus1 = 1, minus1 = 0, PI = 54, DB = 1
N0.C0.D0.R0.S05: TxDq : plus1 = 1, minus1 = 0, PI = 21, DB = 0
N2.C1.D0.R1.S14: TxDqs: plus1 = 1, minus1 = 0, PI = 52, DB = 1
N4.C1.D1.R1.S11: wrcmd2dqsstartlatency: 04
N6.C0.D0.R0.S15: TxDq : plus1 = 1, minus1 = 0, PI = 21, DB = 0
N0.C0.D0.R0.S06: TxDqs: plus1 = 1, minus1 = 0, PI = 57, DB = 1
N2.C1.D0.R1.S14: TxDq : plus1 = 1, minus1 = 0, PI = 21, DB = 0
N4.C1.D1.R1.S11: RdPtrOffsetTxDq: 05
N6.C0.D0.R0.S16: TxDqs: plus1 = 1, minus1 = 0, PI = 07, DB = 1
N0.C0.D0.R0.S06: TxDq : plus1 = 1, minus1 = 0, PI = 23, DB = 0
N2.C1.D0.R1.S15: TxDqs: plus1 = 1, minus1 = 0, PI = 02, DB = 1
N4.C1.D1.R1.S11: RdPtrOffsetTxDqs: 07
N6.C0.D0.R0.S16: TxDq : plus1 = 1, minus1 = 0, PI = 38, DB = 0
N0.C0.D0.R0.S07: TxDqs: plus1 = 1, minus1 = 0, PI = 11, DB = 1
N2.C1.D0.R1.S15: TxDq : plus1 = 1, minus1 = 0, PI = 35, DB = 0
N4.C1.D1.R1.S11: PiTxDqs: 33
N6.C0.D0.R0.S17: TxDqs: plus1 = 1, minus1 = 0, PI = 46, DB = 0
N0.C0.D0.R0.S07: TxDq : plus1 = 1, minus1 = 0, PI = 41, DB = 0
N2.C1.D0.R1.S16: TxDqs: plus1 = 1, minus1 = 0, PI = 19, DB = 0
N4.C1.D1.R1.S12: wrcmd2dqsstartlatency: 04
N6.C0.D0.R0.S17: TxDq : plus1 = 1, minus1 = 0, PI = 14, DB = 1
N0.C0.D0.R0.S08: TxDqs: plus1 = 1, minus1 = 0, PI = 47, DB = 0
N2.C1.D0.R1.S16: TxDq : plus1 = 1, minus1 = 0, PI = 50, DB = 1
N4.C1.D1.R1.S12: RdPtrOffsetTxDq: 05
N6.C0.D0.R1.S00: TxDqs: plus1 = 1, minus1 = 0, PI = 51, DB = 1
N0.C0.D0.R0.S08: TxDq : plus1 = 1, minus1 = 0, PI = 14, DB = 1
N2.C1.D0.R1.S17: TxDqs: plus1 = 1, minus1 = 0, PI = 52, DB = 1
N4.C1.D1.R1.S12: RdPtrOffsetTxDqs: 07
N6.C0.D0.R1.S00: TxDq : plus1 = 1, minus1 = 0, PI = 22, DB = 0
N0.C0.D0.R0.S09: TxDqs: plus1 = 1, minus1 = 0, PI = 52, DB = 1
N2.C1.D0.R1.S17: TxDq : plus1 = 1, minus1 = 0, PI = 21, DB = 0
N4.C1.D1.R1.S12: PiTxDqs: 19
N6.C0.D0.R1.S01: TxDqs: plus1 = 1, minus1 = 0, PI = 29, DB = 0
N0.C0.D0.R0.S09: TxDq : plus1 = 1, minus1 = 0, PI = 21, DB = 0
N2.C1.D1.R0.S00: TxDqs: plus1 = 1, minus1 = 0, PI = 54, DB = 1
N4.C1.D1.R1.S13: wrcmd2dqsstartlatency: 04
N6.C0.D0.R1.S01: TxDq : plus1 = 1, minus1 = 0, PI = 62, DB = 1
N0.C0.D0.R0.S10: TxDqs: plus1 = 1, minus1 = 0, PI = 35, DB = 0
N2.C1.D1.R0.S00: TxDq : plus1 = 1, minus1 = 0, PI = 23, DB = 0
N4.C1.D1.R1.S13: RdPtrOffsetTxDq: 05
N6.C0.D0.R1.S02: TxDqs: plus1 = 1, minus1 = 0, PI = 19, DB = 0
N0.C0.D0.R0.S10: TxDq : plus1 = 1, minus1 = 0, PI = 02, DB = 1
N2.C1.D1.R0.S01: TxDqs: plus1 = 1, minus1 = 0, PI = 38, DB = 0
N4.C1.D1.R1.S13: RdPtrOffsetTxDqs: 06
N6.C0.D0.R1.S02: TxDq : plus1 = 1, minus1 = 0, PI = 51, DB = 1
N0.C0.D0.R0.S11: TxDqs: plus1 = 1, minus1 = 0, PI = 24, DB = 0
N2.C1.D1.R0.S01: TxDq : plus1 = 0, minus1 = 1, PI = 04, DB = 1
N4.C1.D1.R1.S13: PiTxDqs: 50
N6.C0.D0.R1.S03: TxDqs: plus1 = 1, minus1 = 0, PI = 02, DB = 1
N0.C0.D0.R0.S11: TxDq : plus1 = 1, minus1 = 0, PI = 54, DB = 1
N2.C1.D1.R0.S02: TxDqs: plus1 = 1, minus1 = 0, PI = 30, DB = 0
N4.C1.D1.R1.S14: wrcmd2dqsstartlatency: 04
N6.C0.D0.R1.S03: TxDq : plus1 = 1, minus1 = 0, PI = 33, DB = 0
N0.C0.D0.R0.S12: TxDqs: plus1 = 1, minus1 = 0, PI = 08, DB = 1
N2.C1.D1.R0.S02: TxDq : plus1 = 1, minus1 = 0, PI = 61, DB = 1
N4.C1.D1.R1.S14: RdPtrOffsetTxDq: 05
N6.C0.D0.R1.S04: TxDqs: plus1 = 1, minus1 = 0, PI = 33, DB = 0
N0.C0.D0.R0.S12: TxDq : plus1 = 1, minus1 = 0, PI = 38, DB = 0
N2.C1.D1.R0.S03: TxDqs: plus1 = 1, minus1 = 0, PI = 13, DB = 1
N4.C1.D1.R1.S14: RdPtrOffsetTxDqs: 06
N6.C0.D0.R1.S04: TxDq : plus1 = 1, minus1 = 0, PI = 02, DB = 1
N0.C0.D0.R0.S13: TxDqs: plus1 = 1, minus1 = 0, PI = 39, DB = 0
N2.C1.D1.R0.S03: TxDq : plus1 = 1, minus1 = 0, PI = 45, DB = 0
N4.C1.D1.R1.S14: PiTxDqs: 62
N6.C0.D0.R1.S05: TxDqs: plus1 = 1, minus1 = 0, PI = 52, DB = 1
N0.C0.D0.R0.S13: TxDq : plus1 = 1, minus1 = 0, PI = 07, DB = 1
N2.C1.D1.R0.S04: TxDqs: plus1 = 1, minus1 = 0, PI = 45, DB = 0
N4.C1.D1.R1.S15: wrcmd2dqsstartlatency: 04
N6.C0.D0.R1.S05: TxDq : plus1 = 1, minus1 = 0, PI = 19, DB = 0
N0.C0.D0.R0.S14: TxDqs: plus1 = 1, minus1 = 0, PI = 54, DB = 1
N2.C1.D1.R0.S04: TxDq : plus1 = 1, minus1 = 0, PI = 13, DB = 1
N4.C1.D1.R1.S15: RdPtrOffsetTxDq: 05
N6.C0.D0.R1.S06: TxDqs: plus1 = 1, minus1 = 0, PI = 55, DB = 1
N0.C0.D0.R0.S14: TxDq : plus1 = 1, minus1 = 0, PI = 22, DB = 0
N2.C1.D1.R0.S05: TxDqs: plus1 = 1, minus1 = 0, PI = 60, DB = 1
N4.C1.D1.R1.S15: RdPtrOffsetTxDqs: 07
N6.C0.D0.R1.S06: TxDq : plus1 = 1, minus1 = 0, PI = 24, DB = 0
N0.C0.D0.R0.S15: TxDqs: plus1 = 1, minus1 = 0, PI = 58, DB = 1
N2.C1.D1.R0.S05: TxDq : plus1 = 1, minus1 = 0, PI = 26, DB = 0
N4.C1.D1.R1.S15: PiTxDqs: 10
N6.C0.D0.R1.S07: TxDqs: plus1 = 1, minus1 = 0, PI = 07, DB = 1
N0.C0.D0.R0.S15: TxDq : plus1 = 1, minus1 = 0, PI = 25, DB = 0
N2.C1.D1.R0.S06: TxDqs: plus1 = 1, minus1 = 0, PI = 08, DB = 1
N4.C1.D1.R1.S16: wrcmd2dqsstartlatency: 04
N6.C0.D0.R1.S07: TxDq : plus1 = 1, minus1 = 0, PI = 37, DB = 0
N0.C0.D0.R0.S16: TxDqs: plus1 = 1, minus1 = 0, PI = 11, DB = 1
N2.C1.D1.R0.S06: TxDq : plus1 = 1, minus1 = 0, PI = 40, DB = 0
N4.C1.D1.R1.S16: RdPtrOffsetTxDq: 05
N6.C0.D0.R1.S08: TxDqs: plus1 = 1, minus1 = 0, PI = 45, DB = 0
N0.C0.D0.R0.S16: TxDq : plus1 = 1, minus1 = 0, PI = 42, DB = 0
N2.C1.D1.R0.S07: TxDqs: plus1 = 1, minus1 = 0, PI = 27, DB = 0
N4.C1.D1.R1.S16: RdPtrOffsetTxDqs: 07
N6.C0.D0.R1.S08: TxDq : plus1 = 1, minus1 = 0, PI = 15, DB = 1
N0.C0.D0.R0.S17: TxDqs: plus1 = 1, minus1 = 0, PI = 46, DB = 0
N2.C1.D1.R0.S07: TxDq : plus1 = 1, minus1 = 0, PI = 57, DB = 1
N4.C1.D1.R1.S16: PiTxDqs: 27
N6.C0.D0.R1.S09: TxDqs: plus1 = 1, minus1 = 0, PI = 50, DB = 1
N0.C0.D0.R0.S17: TxDq : plus1 = 1, minus1 = 0, PI = 12, DB = 1
N2.C1.D1.R0.S08: TxDqs: plus1 = 1, minus1 = 0, PI = 55, DB = 1
N4.C1.D1.R1.S17: wrcmd2dqsstartlatency: 04
N6.C0.D0.R1.S09: TxDq : plus1 = 1, minus1 = 0, PI = 17, DB = 0
N0.C0.D0.R1.S00: TxDqs: plus1 = 1, minus1 = 0, PI = 52, DB = 1
N2.C1.D1.R0.S08: TxDq : plus1 = 1, minus1 = 0, PI = 22, DB = 0
N4.C1.D1.R1.S17: RdPtrOffsetTxDq: 05
N6.C0.D0.R1.S10: TxDqs: plus1 = 1, minus1 = 0, PI = 30, DB = 0
N0.C0.D0.R1.S00: TxDq : plus1 = 1, minus1 = 0, PI = 20, DB = 0
N2.C1.D1.R0.S09: TxDqs: plus1 = 1, minus1 = 0, PI = 54, DB = 1
N4.C1.D1.R1.S17: RdPtrOffsetTxDqs: 06
N6.C0.D0.R1.S10: TxDq : plus1 = 1, minus1 = 0, PI = 61, DB = 1
N0.C0.D0.R1.S01: TxDqs: plus1 = 1, minus1 = 0, PI = 35, DB = 0
N2.C1.D1.R0.S09: TxDq : plus1 = 1, minus1 = 0, PI = 21, DB = 0
N4.C1.D1.R1.S17: PiTxDqs: 58
N6.C0.D0.R1.S11: TxDqs: plus1 = 1, minus1 = 0, PI = 18, DB = 0
N0.C0.D0.R1.S01: TxDq : plus1 = 1, minus1 = 0, PI = 02, DB = 1
N2.C1.D1.R0.S10: TxDqs: plus1 = 1, minus1 = 0, PI = 37, DB = 0
N4.C1.D1.R1.S00: RdPtrOffsetTxDq: 07
N6.C0.D0.R1.S11: TxDq : plus1 = 1, minus1 = 0, PI = 50, DB = 1
N0.C0.D0.R1.S02: TxDqs: plus1 = 1, minus1 = 0, PI = 24, DB = 0
N2.C1.D1.R0.S10: TxDq : plus1 = 0, minus1 = 1, PI = 04, DB = 1
N4.C1.D1.R1.S01: RdPtrOffsetTxDq: 07
N6.C0.D0.R1.S12: TxDqs: plus1 = 1, minus1 = 0, PI = 05, DB = 1
N0.C0.D0.R1.S02: TxDq : plus1 = 1, minus1 = 0, PI = 54, DB = 1
N2.C1.D1.R0.S11: TxDqs: plus1 = 1, minus1 = 0, PI = 30, DB = 0
N4.C1.D1.R1.S02: RdPtrOffsetTxDq: 06
N6.C0.D0.R1.S12: TxDq : plus1 = 1, minus1 = 0, PI = 36, DB = 0
N0.C0.D0.R1.S03: TxDqs: plus1 = 1, minus1 = 0, PI = 05, DB = 1
N2.C1.D1.R0.S11: TxDq : plus1 = 1, minus1 = 0, PI = 63, DB = 1
N4.C1.D1.R1.S03: RdPtrOffsetTxDq: 06
N6.C0.D0.R1.S13: TxDqs: plus1 = 1, minus1 = 0, PI = 34, DB = 0
N0.C0.D0.R1.S03: TxDq : plus1 = 1, minus1 = 0, PI = 36, DB = 0
N2.C1.D1.R0.S12: TxDqs: plus1 = 1, minus1 = 0, PI = 15, DB = 1
N4.C1.D1.R1.S04: RdPtrOffsetTxDq: 06
N6.C0.D0.R1.S13: TxDq : plus1 = 1, minus1 = 0, PI = 02, DB = 1
N0.C0.D0.R1.S04: TxDqs: plus1 = 1, minus1 = 0, PI = 38, DB = 0
N2.C1.D1.R0.S12: TxDq : plus1 = 1, minus1 = 0, PI = 47, DB = 0
N4.C1.D1.R1.S05: RdPtrOffsetTxDq: 06
N6.C0.D0.R1.S14: TxDqs: plus1 = 1, minus1 = 0, PI = 52, DB = 1
N0.C0.D0.R1.S04: TxDq : plus1 = 1, minus1 = 0, PI = 06, DB = 1
N2.C1.D1.R0.S13: TxDqs: plus1 = 1, minus1 = 0, PI = 45, DB = 0
N4.C1.D1.R1.S06: RdPtrOffsetTxDq: 06
N6.C0.D0.R1.S14: TxDq : plus1 = 1, minus1 = 0, PI = 20, DB = 0
N0.C0.D0.R1.S05: TxDqs: plus1 = 1, minus1 = 0, PI = 54, DB = 1
N2.C1.D1.R0.S13: TxDq : plus1 = 1, minus1 = 0, PI = 13, DB = 1
N4.C1.D1.R1.S07: RdPtrOffsetTxDq: 06
N6.C0.D0.R1.S15: TxDqs: plus1 = 1, minus1 = 0, PI = 54, DB = 1
N0.C0.D0.R1.S05: TxDq : plus1 = 1, minus1 = 0, PI = 21, DB = 0
N2.C1.D1.R0.S14: TxDqs: plus1 = 1, minus1 = 0, PI = 60, DB = 1
N4.C1.D1.R1.S08: RdPtrOffsetTxDq: 06
N6.C0.D0.R1.S15: TxDq : plus1 = 1, minus1 = 0, PI = 21, DB = 0
N0.C0.D0.R1.S06: TxDqs: plus1 = 1, minus1 = 0, PI = 57, DB = 1
N2.C1.D1.R0.S14: TxDq : plus1 = 1, minus1 = 0, PI = 28, DB = 0
N4.C1.D1.R1.S09: RdPtrOffsetTxDq: 07
N6.C0.D0.R1.S16: TxDqs: plus1 = 1, minus1 = 0, PI = 07, DB = 1
N0.C0.D0.R1.S06: TxDq : plus1 = 1, minus1 = 0, PI = 23, DB = 0
N2.C1.D1.R0.S15: TxDqs: plus1 = 1, minus1 = 0, PI = 06, DB = 1
N4.C1.D1.R1.S10: RdPtrOffsetTxDq: 07
N6.C0.D0.R1.S16: TxDq : plus1 = 1, minus1 = 0, PI = 38, DB = 0
N0.C0.D0.R1.S07: TxDqs: plus1 = 1, minus1 = 0, PI = 11, DB = 1
N2.C1.D1.R0.S15: TxDq : plus1 = 1, minus1 = 0, PI = 39, DB = 0
N4.C1.D1.R1.S11: RdPtrOffsetTxDq: 06
N6.C0.D0.R1.S17: TxDqs: plus1 = 1, minus1 = 0, PI = 46, DB = 0
N0.C0.D0.R1.S07: TxDq : plus1 = 1, minus1 = 0, PI = 41, DB = 0
N2.C1.D1.R0.S16: TxDqs: plus1 = 1, minus1 = 0, PI = 26, DB = 0
N4.C1.D1.R1.S12: RdPtrOffsetTxDq: 06
N6.C0.D0.R1.S17: TxDq : plus1 = 1, minus1 = 0, PI = 14, DB = 1
N0.C0.D0.R1.S08: TxDqs: plus1 = 1, minus1 = 0, PI = 47, DB = 0
N2.C1.D1.R0.S16: TxDq : plus1 = 1, minus1 = 0, PI = 57, DB = 1
N4.C1.D1.R1.S13: RdPtrOffsetTxDq: 06
N6.C0.D1.R0.S00: TxDqs: plus1 = 1, minus1 = 0, PI = 51, DB = 1
N0.C0.D0.R1.S08: TxDq : plus1 = 1, minus1 = 0, PI = 14, DB = 1
N2.C1.D1.R0.S17: TxDqs: plus1 = 1, minus1 = 0, PI = 56, DB = 1
N4.C1.D1.R1.S14: RdPtrOffsetTxDq: 06
N6.C0.D1.R0.S00: TxDq : plus1 = 1, minus1 = 0, PI = 22, DB = 0
N0.C0.D0.R1.S09: TxDqs: plus1 = 1, minus1 = 0, PI = 52, DB = 1
N2.C1.D1.R0.S17: TxDq : plus1 = 1, minus1 = 0, PI = 24, DB = 0
N4.C1.D1.R1.S15: RdPtrOffsetTxDq: 06
N6.C0.D1.R0.S01: TxDqs: plus1 = 1, minus1 = 0, PI = 35, DB = 0
N0.C0.D0.R1.S09: TxDq : plus1 = 1, minus1 = 0, PI = 21, DB = 0
N2.C1.D1.R1.S00: TxDqs: plus1 = 1, minus1 = 0, PI = 54, DB = 1
N4.C1.D1.R1.S16: RdPtrOffsetTxDq: 06
N6.C0.D1.R0.S01: TxDq : plus1 = 0, minus1 = 1, PI = 03, DB = 1
N0.C0.D0.R1.S10: TxDqs: plus1 = 1, minus1 = 0, PI = 35, DB = 0
N2.C1.D1.R1.S00: TxDq : plus1 = 1, minus1 = 0, PI = 23, DB = 0
N4.C1.D1.R1.S17: RdPtrOffsetTxDq: 06
N6.C0.D1.R0.S02: TxDqs: plus1 = 1, minus1 = 0, PI = 22, DB = 0
N0.C0.D0.R1.S10: TxDq : plus1 = 1, minus1 = 0, PI = 02, DB = 1
N2.C1.D1.R1.S01: TxDqs: plus1 = 1, minus1 = 0, PI = 38, DB = 0
N4.C1.D1.R1.S00: RdPtrOffsetTxDq: 08
N6.C0.D1.R0.S02: TxDq : plus1 = 1, minus1 = 0, PI = 54, DB = 1
N0.C0.D0.R1.S11: TxDqs: plus1 = 1, minus1 = 0, PI = 24, DB = 0
N2.C1.D1.R1.S01: TxDq : plus1 = 0, minus1 = 1, PI = 04, DB = 1
N4.C1.D1.R1.S01: RdPtrOffsetTxDq: 08
N6.C0.D1.R0.S03: TxDqs: plus1 = 1, minus1 = 0, PI = 09, DB = 1
N0.C0.D0.R1.S11: TxDq : plus1 = 1, minus1 = 0, PI = 54, DB = 1
N2.C1.D1.R1.S02: TxDqs: plus1 = 1, minus1 = 0, PI = 30, DB = 0
N4.C1.D1.R1.S02: RdPtrOffsetTxDq: 07
N6.C0.D1.R0.S03: TxDq : plus1 = 1, minus1 = 0, PI = 41, DB = 0
N0.C0.D0.R1.S12: TxDqs: plus1 = 1, minus1 = 0, PI = 08, DB = 1
N2.C1.D1.R1.S02: TxDq : plus1 = 1, minus1 = 0, PI = 61, DB = 1
N4.C1.D1.R1.S03: RdPtrOffsetTxDq: 07
N6.C0.D1.R0.S04: TxDqs: plus1 = 1, minus1 = 0, PI = 37, DB = 0
N0.C0.D0.R1.S12: TxDq : plus1 = 1, minus1 = 0, PI = 38, DB = 0
N2.C1.D1.R1.S03: TxDqs: plus1 = 1, minus1 = 0, PI = 13, DB = 1
N4.C1.D1.R1.S04: RdPtrOffsetTxDq: 07
N6.C0.D1.R0.S04: TxDq : plus1 = 1, minus1 = 0, PI = 05, DB = 1
N0.C0.D0.R1.S13: TxDqs: plus1 = 1, minus1 = 0, PI = 39, DB = 0
N2.C1.D1.R1.S03: TxDq : plus1 = 1, minus1 = 0, PI = 45, DB = 0
N4.C1.D1.R1.S05: RdPtrOffsetTxDq: 07
N6.C0.D1.R0.S05: TxDqs: plus1 = 1, minus1 = 0, PI = 56, DB = 1
N0.C0.D0.R1.S13: TxDq : plus1 = 1, minus1 = 0, PI = 07, DB = 1
N2.C1.D1.R1.S04: TxDqs: plus1 = 1, minus1 = 0, PI = 45, DB = 0
N4.C1.D1.R1.S06: RdPtrOffsetTxDq: 07
N6.C0.D1.R0.S05: TxDq : plus1 = 1, minus1 = 0, PI = 24, DB = 0
N0.C0.D0.R1.S14: TxDqs: plus1 = 1, minus1 = 0, PI = 54, DB = 1
N2.C1.D1.R1.S04: TxDq : plus1 = 1, minus1 = 0, PI = 13, DB = 1
N4.C1.D1.R1.S07: RdPtrOffsetTxDq: 07
N6.C0.D1.R0.S06: TxDqs: plus1 = 1, minus1 = 0, PI = 59, DB = 1
N0.C0.D0.R1.S14: TxDq : plus1 = 1, minus1 = 0, PI = 22, DB = 0
N2.C1.D1.R1.S05: TxDqs: plus1 = 1, minus1 = 0, PI = 60, DB = 1
N4.C1.D1.R1.S08: RdPtrOffsetTxDq: 07
N6.C0.D1.R0.S06: TxDq : plus1 = 1, minus1 = 0, PI = 26, DB = 0
N0.C0.D0.R1.S15: TxDqs: plus1 = 1, minus1 = 0, PI = 58, DB = 1
N2.C1.D1.R1.S05: TxDq : plus1 = 1, minus1 = 0, PI = 26, DB = 0
N4.C1.D1.R1.S09: RdPtrOffsetTxDq: 08
N6.C0.D1.R0.S07: TxDqs: plus1 = 1, minus1 = 0, PI = 12, DB = 1
N0.C0.D0.R1.S15: TxDq : plus1 = 1, minus1 = 0, PI = 25, DB = 0
N2.C1.D1.R1.S06: TxDqs: plus1 = 1, minus1 = 0, PI = 08, DB = 1
N4.C1.D1.R1.S10: RdPtrOffsetTxDq: 08
N6.C0.D1.R0.S07: TxDq : plus1 = 1, minus1 = 0, PI = 43, DB = 0
N0.C0.D0.R1.S16: TxDqs: plus1 = 1, minus1 = 0, PI = 11, DB = 1
N2.C1.D1.R1.S06: TxDq : plus1 = 1, minus1 = 0, PI = 40, DB = 0
N4.C1.D1.R1.S11: RdPtrOffsetTxDq: 07
N6.C0.D1.R0.S08: TxDqs: plus1 = 1, minus1 = 0, PI = 46, DB = 0
N0.C0.D0.R1.S16: TxDq : plus1 = 1, minus1 = 0, PI = 42, DB = 0
N2.C1.D1.R1.S07: TxDqs: plus1 = 1, minus1 = 0, PI = 27, DB = 0
N4.C1.D1.R1.S12: RdPtrOffsetTxDq: 07
N6.C0.D1.R0.S08: TxDq : plus1 = 1, minus1 = 0, PI = 14, DB = 1
N0.C0.D0.R1.S17: TxDqs: plus1 = 1, minus1 = 0, PI = 46, DB = 0
N2.C1.D1.R1.S07: TxDq : plus1 = 1, minus1 = 0, PI = 57, DB = 1
N4.C1.D1.R1.S13: RdPtrOffsetTxDq: 07
N6.C0.D1.R0.S09: TxDqs: plus1 = 1, minus1 = 0, PI = 52, DB = 1
N0.C0.D0.R1.S17: TxDq : plus1 = 1, minus1 = 0, PI = 12, DB = 1
N2.C1.D1.R1.S08: TxDqs: plus1 = 1, minus1 = 0, PI = 55, DB = 1
N4.C1.D1.R1.S14: RdPtrOffsetTxDq: 07
N6.C0.D1.R0.S09: TxDq : plus1 = 1, minus1 = 0, PI = 19, DB = 0
N0.C0.D1.R0.S00: TxDqs: plus1 = 1, minus1 = 0, PI = 58, DB = 1
N2.C1.D1.R1.S08: TxDq : plus1 = 1, minus1 = 0, PI = 22, DB = 0
N4.C1.D1.R1.S15: RdPtrOffsetTxDq: 07
N6.C0.D1.R0.S10: TxDqs: plus1 = 1, minus1 = 0, PI = 36, DB = 0
N0.C0.D1.R0.S00: TxDq : plus1 = 1, minus1 = 0, PI = 25, DB = 0
N2.C1.D1.R1.S09: TxDqs: plus1 = 1, minus1 = 0, PI = 54, DB = 1
N4.C1.D1.R1.S16: RdPtrOffsetTxDq: 07
N6.C0.D1.R0.S10: TxDq : plus1 = 0, minus1 = 1, PI = 03, DB = 1
N0.C0.D1.R0.S01: TxDqs: plus1 = 1, minus1 = 0, PI = 42, DB = 0
N2.C1.D1.R1.S09: TxDq : plus1 = 1, minus1 = 0, PI = 21, DB = 0
N4.C1.D1.R1.S17: RdPtrOffsetTxDq: 07
N6.C0.D1.R0.S11: TxDqs: plus1 = 1, minus1 = 0, PI = 22, DB = 0
N0.C0.D1.R0.S01: TxDq : plus1 = 1, minus1 = 0, PI = 09, DB = 1
N2.C1.D1.R1.S10: TxDqs: plus1 = 1, minus1 = 0, PI = 37, DB = 0
N4.C1.D1.R1.S00: Total Delay in PI ticks: TxDQ = 984
N6.C0.D1.R0.S11: TxDq : plus1 = 1, minus1 = 0, PI = 53, DB = 1
N0.C0.D1.R0.S02: TxDqs: plus1 = 1, minus1 = 0, PI = 31, DB = 0
N2.C1.D1.R1.S10: TxDq : plus1 = 0, minus1 = 1, PI = 04, DB = 1
N4.C1.D1.R1.S01: Total Delay in PI ticks: TxDQ = 968
N6.C0.D1.R0.S12: TxDqs: plus1 = 1, minus1 = 0, PI = 09, DB = 1
N0.C0.D1.R0.S02: TxDq : plus1 = 1, minus1 = 0, PI = 59, DB = 1
N2.C1.D1.R1.S11: TxDqs: plus1 = 1, minus1 = 0, PI = 30, DB = 0
N4.C1.D1.R1.S02: Total Delay in PI ticks: TxDQ = 956
N6.C0.D1.R0.S12: TxDq : plus1 = 1, minus1 = 0, PI = 39, DB = 0
N0.C0.D1.R0.S03: TxDqs: plus1 = 1, minus1 = 0, PI = 14, DB = 1
N2.C1.D1.R1.S11: TxDq : plus1 = 1, minus1 = 0, PI = 63, DB = 1
N4.C1.D1.R1.S03: Total Delay in PI ticks: TxDQ = 942
N6.C0.D1.R0.S13: TxDqs: plus1 = 1, minus1 = 0, PI = 38, DB = 0
N0.C0.D1.R0.S03: TxDq : plus1 = 1, minus1 = 0, PI = 43, DB = 0
N2.C1.D1.R1.S12: TxDqs: plus1 = 1, minus1 = 0, PI = 15, DB = 1
N4.C1.D1.R1.S04: Total Delay in PI ticks: TxDQ = 909
N6.C0.D1.R0.S13: TxDq : plus1 = 1, minus1 = 0, PI = 05, DB = 1
N0.C0.D1.R0.S04: TxDqs: plus1 = 1, minus1 = 0, PI = 43, DB = 0
N2.C1.D1.R1.S12: TxDq : plus1 = 1, minus1 = 0, PI = 47, DB = 0
N4.C1.D1.R1.S05: Total Delay in PI ticks: TxDQ = 923
N6.C0.D1.R0.S14: TxDqs: plus1 = 1, minus1 = 0, PI = 57, DB = 1
N0.C0.D1.R0.S04: TxDq : plus1 = 1, minus1 = 0, PI = 09, DB = 1
N2.C1.D1.R1.S13: TxDqs: plus1 = 1, minus1 = 0, PI = 45, DB = 0
N4.C1.D1.R1.S06: Total Delay in PI ticks: TxDQ = 934
N6.C0.D1.R0.S14: TxDq : plus1 = 1, minus1 = 0, PI = 24, DB = 0
N0.C0.D1.R0.S05: TxDqs: plus1 = 1, minus1 = 0, PI = 63, DB = 1
N2.C1.D1.R1.S13: TxDq : plus1 = 1, minus1 = 0, PI = 13, DB = 1
N4.C1.D1.R1.S07: Total Delay in PI ticks: TxDQ = 952
N6.C0.D1.R0.S15: TxDqs: plus1 = 1, minus1 = 0, PI = 59, DB = 1
N0.C0.D1.R0.S05: TxDq : plus1 = 1, minus1 = 0, PI = 28, DB = 0
N2.C1.D1.R1.S14: TxDqs: plus1 = 1, minus1 = 0, PI = 60, DB = 1
N4.C1.D1.R1.S08: Total Delay in PI ticks: TxDQ = 921
N6.C0.D1.R0.S15: TxDq : plus1 = 1, minus1 = 0, PI = 25, DB = 0
N0.C0.D1.R0.S06: TxDqs: plus1 = 1, minus1 = 0, PI = 63, DB = 1
N2.C1.D1.R1.S14: TxDq : plus1 = 1, minus1 = 0, PI = 28, DB = 0
N4.C1.D1.R1.S09: Total Delay in PI ticks: TxDQ = 981
N6.C0.D1.R0.S16: TxDqs: plus1 = 1, minus1 = 0, PI = 11, DB = 1
N0.C0.D1.R0.S06: TxDq : plus1 = 1, minus1 = 0, PI = 30, DB = 0
N2.C1.D1.R1.S15: TxDqs: plus1 = 1, minus1 = 0, PI = 06, DB = 1
N4.C1.D1.R1.S10: Total Delay in PI ticks: TxDQ = 968
N6.C0.D1.R0.S16: TxDq : plus1 = 1, minus1 = 0, PI = 42, DB = 0
N0.C0.D1.R0.S07: TxDqs: plus1 = 1, minus1 = 0, PI = 17, DB = 0
N2.C1.D1.R1.S15: TxDq : plus1 = 1, minus1 = 0, PI = 39, DB = 0
N4.C1.D1.R1.S11: Total Delay in PI ticks: TxDQ = 958
N6.C0.D1.R0.S17: TxDqs: plus1 = 1, minus1 = 0, PI = 46, DB = 0
N0.C0.D1.R0.S07: TxDq : plus1 = 1, minus1 = 0, PI = 47, DB = 0
N2.C1.D1.R1.S16: TxDqs: plus1 = 1, minus1 = 0, PI = 26, DB = 0
N4.C1.D1.R1.S12: Total Delay in PI ticks: TxDQ = 946
N6.C0.D1.R0.S17: TxDq : plus1 = 1, minus1 = 0, PI = 13, DB = 1
N0.C0.D1.R0.S08: TxDqs: plus1 = 1, minus1 = 0, PI = 50, DB = 1
N2.C1.D1.R1.S16: TxDq : plus1 = 1, minus1 = 0, PI = 57, DB = 1
N4.C1.D1.R1.S13: Total Delay in PI ticks: TxDQ = 909
N6.C0.D1.R1.S00: TxDqs: plus1 = 1, minus1 = 0, PI = 51, DB = 1
N0.C0.D1.R0.S08: TxDq : plus1 = 1, minus1 = 0, PI = 15, DB = 1
N2.C1.D1.R1.S17: TxDqs: plus1 = 1, minus1 = 0, PI = 56, DB = 1
N4.C1.D1.R1.S14: Total Delay in PI ticks: TxDQ = 922
N6.C0.D1.R1.S00: TxDq : plus1 = 1, minus1 = 0, PI = 22, DB = 0
N0.C0.D1.R0.S09: TxDqs: plus1 = 1, minus1 = 0, PI = 56, DB = 1
N2.C1.D1.R1.S17: TxDq : plus1 = 1, minus1 = 0, PI = 24, DB = 0
N4.C1.D1.R1.S15: Total Delay in PI ticks: TxDQ = 936
N6.C0.D1.R1.S01: TxDqs: plus1 = 1, minus1 = 0, PI = 35, DB = 0
N0.C0.D1.R0.S09: TxDq : plus1 = 1, minus1 = 0, PI = 23, DB = 0
END_DATA_TX_DQ
N4.C1.D1.R1.S16: Total Delay in PI ticks: TxDQ = 951
N6.C0.D1.R1.S01: TxDq : plus1 = 0, minus1 = 1, PI = 03, DB = 1
N0.C0.D1.R0.S10: TxDqs: plus1 = 1, minus1 = 0, PI = 43, DB = 0
N2.C2.D0.R0.S00: wrcmd2dqsstartlatency: 04
N4.C1.D1.R1.S17: Total Delay in PI ticks: TxDQ = 919
N6.C0.D1.R1.S02: TxDqs: plus1 = 1, minus1 = 0, PI = 22, DB = 0
N0.C0.D1.R0.S10: TxDq : plus1 = 1, minus1 = 0, PI = 10, DB = 1
N2.C2.D0.R0.S00: RdPtrOffsetTxDq: 06
N4.C1: Calculating Optimimum DQ/DQS Values
N6.C0.D1.R1.S02: TxDq : plus1 = 1, minus1 = 0, PI = 54, DB = 1
N0.C0.D1.R0.S11: TxDqs: plus1 = 1, minus1 = 0, PI = 30, DB = 0
N2.C2.D0.R0.S00: RdPtrOffsetTxDqs: 07
N6.C0.D1.R1.S03: TxDqs: plus1 = 1, minus1 = 0, PI = 09, DB = 1
N0.C0.D1.R0.S11: TxDq : plus1 = 1, minus1 = 0, PI = 59, DB = 1
N2.C2.D0.R0.S00: PiTxDqs: 50
START_DATA_TX_DQ
N6.C0.D1.R1.S03: TxDq : plus1 = 1, minus1 = 0, PI = 41, DB = 0
N0.C0.D1.R0.S12: TxDqs: plus1 = 1, minus1 = 0, PI = 15, DB = 1
N2.C2.D0.R0.S01: wrcmd2dqsstartlatency: 04
N4.C1.S00: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 009, RdPtrOffsetTxDqs = 009
N6.C0.D1.R1.S04: TxDqs: plus1 = 1, minus1 = 0, PI = 37, DB = 0
N0.C0.D1.R0.S12: TxDq : plus1 = 1, minus1 = 0, PI = 45, DB = 0
N2.C2.D0.R0.S01: RdPtrOffsetTxDq: 06
N4.C1.S00: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 009, RdPtrOffsetTxDqs = 009
N6.C0.D1.R1.S04: TxDq : plus1 = 1, minus1 = 0, PI = 05, DB = 1
N0.C0.D1.R0.S13: TxDqs: plus1 = 1, minus1 = 0, PI = 45, DB = 0
N2.C2.D0.R0.S01: RdPtrOffsetTxDqs: 07
N4.C1.S01: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 009, RdPtrOffsetTxDqs = 009
N6.C0.D1.R1.S05: TxDqs: plus1 = 1, minus1 = 0, PI = 56, DB = 1
N0.C0.D1.R0.S13: TxDq : plus1 = 1, minus1 = 0, PI = 11, DB = 1
N2.C2.D0.R0.S01: PiTxDqs: 35
N4.C1.S01: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 009, RdPtrOffsetTxDqs = 009
N6.C0.D1.R1.S05: TxDq : plus1 = 1, minus1 = 0, PI = 24, DB = 0
N0.C0.D1.R0.S14: TxDqs: plus1 = 1, minus1 = 0, PI = 62, DB = 1
N2.C2.D0.R0.S02: wrcmd2dqsstartlatency: 04
N4.C1.S02: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 009
N6.C0.D1.R1.S06: TxDqs: plus1 = 1, minus1 = 0, PI = 59, DB = 1
N0.C0.D1.R0.S14: TxDq : plus1 = 1, minus1 = 0, PI = 28, DB = 0
N2.C2.D0.R0.S02: RdPtrOffsetTxDq: 05
N4.C1.S02: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 009
N6.C0.D1.R1.S06: TxDq : plus1 = 1, minus1 = 0, PI = 26, DB = 0
N0.C0.D1.R0.S15: TxDqs: plus1 = 0, minus1 = 1, PI = 01, DB = 1
N2.C2.D0.R0.S02: RdPtrOffsetTxDqs: 07
N4.C1.S03: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 009
N6.C0.D1.R1.S07: TxDqs: plus1 = 1, minus1 = 0, PI = 12, DB = 1
N0.C0.D1.R0.S15: TxDq : plus1 = 1, minus1 = 0, PI = 30, DB = 0
N2.C2.D0.R0.S02: PiTxDqs: 24
N4.C1.S03: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 009
N6.C0.D1.R1.S07: TxDq : plus1 = 1, minus1 = 0, PI = 43, DB = 0
N0.C0.D1.R0.S16: TxDqs: plus1 = 1, minus1 = 0, PI = 17, DB = 0
N2.C2.D0.R0.S03: wrcmd2dqsstartlatency: 04
N4.C1.S04: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 008
N6.C0.D1.R1.S08: TxDqs: plus1 = 1, minus1 = 0, PI = 46, DB = 0
N0.C0.D1.R0.S16: TxDq : plus1 = 1, minus1 = 0, PI = 48, DB = 0
N2.C2.D0.R0.S03: RdPtrOffsetTxDq: 05
N4.C1.S04: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 008
N6.C0.D1.R1.S08: TxDq : plus1 = 1, minus1 = 0, PI = 14, DB = 1
N0.C0.D1.R0.S17: TxDqs: plus1 = 1, minus1 = 0, PI = 52, DB = 1
N2.C2.D0.R0.S03: RdPtrOffsetTxDqs: 07
N4.C1.S05: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 008
N6.C0.D1.R1.S09: TxDqs: plus1 = 1, minus1 = 0, PI = 52, DB = 1
N0.C0.D1.R0.S17: TxDq : plus1 = 1, minus1 = 0, PI = 17, DB = 0
N2.C2.D0.R0.S03: PiTxDqs: 06
N4.C1.S05: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 008
N6.C0.D1.R1.S09: TxDq : plus1 = 1, minus1 = 0, PI = 19, DB = 0
N0.C0.D1.R1.S00: TxDqs: plus1 = 1, minus1 = 0, PI = 58, DB = 1
N2.C2.D0.R0.S04: wrcmd2dqsstartlatency: 04
N4.C1.S06: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 009
N6.C0.D1.R1.S10: TxDqs: plus1 = 1, minus1 = 0, PI = 36, DB = 0
N0.C0.D1.R1.S00: TxDq : plus1 = 1, minus1 = 0, PI = 25, DB = 0
N2.C2.D0.R0.S04: RdPtrOffsetTxDq: 04
N4.C1.S06: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 009
N6.C0.D1.R1.S10: TxDq : plus1 = 0, minus1 = 1, PI = 03, DB = 1
N0.C0.D1.R1.S01: TxDqs: plus1 = 1, minus1 = 0, PI = 42, DB = 0
N2.C2.D0.R0.S04: RdPtrOffsetTxDqs: 06
N4.C1.S07: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 009
N6.C0.D1.R1.S11: TxDqs: plus1 = 1, minus1 = 0, PI = 22, DB = 0
N0.C0.D1.R1.S01: TxDq : plus1 = 1, minus1 = 0, PI = 09, DB = 1
N2.C2.D0.R0.S04: PiTxDqs: 29
N4.C1.S07: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 009
N6.C0.D1.R1.S11: TxDq : plus1 = 1, minus1 = 0, PI = 53, DB = 1
N0.C0.D1.R1.S02: TxDqs: plus1 = 1, minus1 = 0, PI = 31, DB = 0
N2.C2.D0.R0.S05: wrcmd2dqsstartlatency: 04
N4.C1.S08: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 008
N6.C0.D1.R1.S12: TxDqs: plus1 = 1, minus1 = 0, PI = 09, DB = 1
N0.C0.D1.R1.S02: TxDq : plus1 = 1, minus1 = 0, PI = 59, DB = 1
N2.C2.D0.R0.S05: RdPtrOffsetTxDq: 05
N4.C1.S08: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 008
N6.C0.D1.R1.S12: TxDq : plus1 = 1, minus1 = 0, PI = 39, DB = 0
N0.C0.D1.R1.S03: TxDqs: plus1 = 1, minus1 = 0, PI = 14, DB = 1
N2.C2.D0.R0.S05: RdPtrOffsetTxDqs: 06
N4.C1.D0.R0.S00: TxDqs: plus1 = 1, minus1 = 0, PI = 54, DB = 1
N6.C0.D1.R1.S13: TxDqs: plus1 = 1, minus1 = 0, PI = 38, DB = 0
N0.C0.D1.R1.S03: TxDq : plus1 = 1, minus1 = 0, PI = 43, DB = 0
N2.C2.D0.R0.S05: PiTxDqs: 60
N4.C1.D0.R0.S00: TxDq : plus1 = 1, minus1 = 0, PI = 22, DB = 0
N6.C0.D1.R1.S13: TxDq : plus1 = 1, minus1 = 0, PI = 05, DB = 1
N0.C0.D1.R1.S04: TxDqs: plus1 = 1, minus1 = 0, PI = 43, DB = 0
N2.C2.D0.R0.S06: wrcmd2dqsstartlatency: 04
N4.C1.D0.R0.S01: TxDqs: plus1 = 1, minus1 = 0, PI = 38, DB = 0
N6.C0.D1.R1.S14: TxDqs: plus1 = 1, minus1 = 0, PI = 57, DB = 1
N0.C0.D1.R1.S04: TxDq : plus1 = 1, minus1 = 0, PI = 09, DB = 1
N2.C2.D0.R0.S06: RdPtrOffsetTxDq: 05
N4.C1.D0.R0.S01: TxDq : plus1 = 1, minus1 = 0, PI = 05, DB = 1
N6.C0.D1.R1.S14: TxDq : plus1 = 1, minus1 = 0, PI = 24, DB = 0
N0.C0.D1.R1.S05: TxDqs: plus1 = 1, minus1 = 0, PI = 63, DB = 1
N2.C2.D0.R0.S06: RdPtrOffsetTxDqs: 06
N4.C1.D0.R0.S02: TxDqs: plus1 = 1, minus1 = 0, PI = 30, DB = 0
N6.C0.D1.R1.S15: TxDqs: plus1 = 1, minus1 = 0, PI = 59, DB = 1
N0.C0.D1.R1.S05: TxDq : plus1 = 1, minus1 = 0, PI = 28, DB = 0
N2.C2.D0.R0.S06: PiTxDqs: 56
N4.C1.D0.R0.S02: TxDq : plus1 = 1, minus1 = 0, PI = 60, DB = 1
N6.C0.D1.R1.S15: TxDq : plus1 = 1, minus1 = 0, PI = 25, DB = 0
N0.C0.D1.R1.S06: TxDqs: plus1 = 1, minus1 = 0, PI = 63, DB = 1
N2.C2.D0.R0.S07: wrcmd2dqsstartlatency: 04
N4.C1.D0.R0.S03: TxDqs: plus1 = 1, minus1 = 0, PI = 16, DB = 0
N6.C0.D1.R1.S16: TxDqs: plus1 = 1, minus1 = 0, PI = 11, DB = 1
N0.C0.D1.R1.S06: TxDq : plus1 = 1, minus1 = 0, PI = 30, DB = 0
N2.C2.D0.R0.S07: RdPtrOffsetTxDq: 05
N4.C1.D0.R0.S03: TxDq : plus1 = 1, minus1 = 0, PI = 46, DB = 0
N6.C0.D1.R1.S16: TxDq : plus1 = 1, minus1 = 0, PI = 42, DB = 0
N0.C0.D1.R1.S07: TxDqs: plus1 = 1, minus1 = 0, PI = 17, DB = 0
N2.C2.D0.R0.S07: RdPtrOffsetTxDqs: 07
N4.C1.D0.R0.S04: TxDqs: plus1 = 1, minus1 = 0, PI = 46, DB = 0
N6.C0.D1.R1.S17: TxDqs: plus1 = 1, minus1 = 0, PI = 46, DB = 0
N0.C0.D1.R1.S07: TxDq : plus1 = 1, minus1 = 0, PI = 47, DB = 0
N2.C2.D0.R0.S07: PiTxDqs: 14
N4.C1.D0.R0.S04: TxDq : plus1 = 1, minus1 = 0, PI = 13, DB = 1
N6.C0.D1.R1.S17: TxDq : plus1 = 1, minus1 = 0, PI = 13, DB = 1
N0.C0.D1.R1.S08: TxDqs: plus1 = 1, minus1 = 0, PI = 50, DB = 1
N2.C2.D0.R0.S08: wrcmd2dqsstartlatency: 04
N4.C1.D0.R0.S05: TxDqs: plus1 = 1, minus1 = 0, PI = 56, DB = 1
END_DATA_TX_DQ
N0.C0.D1.R1.S08: TxDq : plus1 = 1, minus1 = 0, PI = 15, DB = 1
N2.C2.D0.R0.S08: RdPtrOffsetTxDq: 05
N4.C1.D0.R0.S05: TxDq : plus1 = 1, minus1 = 0, PI = 23, DB = 0
N6.C1.D0.R0.S00: wrcmd2dqsstartlatency: 04
N0.C0.D1.R1.S09: TxDqs: plus1 = 1, minus1 = 0, PI = 56, DB = 1
N2.C2.D0.R0.S08: RdPtrOffsetTxDqs: 06
N4.C1.D0.R0.S06: TxDqs: plus1 = 1, minus1 = 0, PI = 08, DB = 1
N6.C1.D0.R0.S00: RdPtrOffsetTxDq: 06
N0.C0.D1.R1.S09: TxDq : plus1 = 1, minus1 = 0, PI = 23, DB = 0
N2.C2.D0.R0.S08: PiTxDqs: 52
N4.C1.D0.R0.S06: TxDq : plus1 = 1, minus1 = 0, PI = 39, DB = 0
N6.C1.D0.R0.S00: RdPtrOffsetTxDqs: 07
N0.C0.D1.R1.S10: TxDqs: plus1 = 1, minus1 = 0, PI = 43, DB = 0
N2.C2.D0.R0.S09: wrcmd2dqsstartlatency: 04
N4.C1.D0.R0.S07: TxDqs: plus1 = 1, minus1 = 0, PI = 24, DB = 0
N6.C1.D0.R0.S00: PiTxDqs: 54
N0.C0.D1.R1.S10: TxDq : plus1 = 1, minus1 = 0, PI = 10, DB = 1
N2.C2.D0.R0.S09: RdPtrOffsetTxDq: 06
N4.C1.D0.R0.S07: TxDq : plus1 = 1, minus1 = 0, PI = 53, DB = 1
N6.C1.D0.R0.S01: wrcmd2dqsstartlatency: 04
N0.C0.D1.R1.S11: TxDqs: plus1 = 1, minus1 = 0, PI = 30, DB = 0
N2.C2.D0.R0.S09: RdPtrOffsetTxDqs: 07
N4.C1.D0.R0.S08: TxDqs: plus1 = 1, minus1 = 0, PI = 60, DB = 1
N6.C1.D0.R0.S01: RdPtrOffsetTxDq: 06
N0.C0.D1.R1.S11: TxDq : plus1 = 1, minus1 = 0, PI = 59, DB = 1
N2.C2.D0.R0.S09: PiTxDqs: 52
N4.C1.D0.R0.S08: TxDq : plus1 = 1, minus1 = 0, PI = 27, DB = 0
N6.C1.D0.R0.S01: RdPtrOffsetTxDqs: 07
N0.C0.D1.R1.S12: TxDqs: plus1 = 1, minus1 = 0, PI = 15, DB = 1
N2.C2.D0.R0.S10: wrcmd2dqsstartlatency: 04
N4.C1.D0.R0.S09: TxDqs: plus1 = 1, minus1 = 0, PI = 55, DB = 1
N6.C1.D0.R0.S01: PiTxDqs: 38
N0.C0.D1.R1.S12: TxDq : plus1 = 1, minus1 = 0, PI = 45, DB = 0
N2.C2.D0.R0.S10: RdPtrOffsetTxDq: 06
N4.C1.D0.R0.S09: TxDq : plus1 = 1, minus1 = 0, PI = 21, DB = 0
N6.C1.D0.R0.S02: wrcmd2dqsstartlatency: 04
N0.C0.D1.R1.S13: TxDqs: plus1 = 1, minus1 = 0, PI = 45, DB = 0
N2.C2.D0.R0.S10: RdPtrOffsetTxDqs: 07
N4.C1.D0.R0.S10: TxDqs: plus1 = 1, minus1 = 0, PI = 40, DB = 0
N6.C1.D0.R0.S02: RdPtrOffsetTxDq: 05
N0.C0.D1.R1.S13: TxDq : plus1 = 1, minus1 = 0, PI = 11, DB = 1
N2.C2.D0.R0.S10: PiTxDqs: 34
N4.C1.D0.R0.S10: TxDq : plus1 = 1, minus1 = 0, PI = 07, DB = 1
N6.C1.D0.R0.S02: RdPtrOffsetTxDqs: 07
N0.C0.D1.R1.S14: TxDqs: plus1 = 1, minus1 = 0, PI = 62, DB = 1
N2.C2.D0.R0.S11: wrcmd2dqsstartlatency: 04
N4.C1.D0.R0.S11: TxDqs: plus1 = 1, minus1 = 0, PI = 31, DB = 0
N6.C1.D0.R0.S02: PiTxDqs: 28
N0.C0.D1.R1.S14: TxDq : plus1 = 1, minus1 = 0, PI = 28, DB = 0
N2.C2.D0.R0.S11: RdPtrOffsetTxDq: 05
N4.C1.D0.R0.S11: TxDq : plus1 = 1, minus1 = 0, PI = 62, DB = 1
N6.C1.D0.R0.S03: wrcmd2dqsstartlatency: 04
N0.C0.D1.R1.S15: TxDqs: plus1 = 0, minus1 = 1, PI = 01, DB = 1
N2.C2.D0.R0.S11: RdPtrOffsetTxDqs: 07
N4.C1.D0.R0.S12: TxDqs: plus1 = 1, minus1 = 0, PI = 16, DB = 0
N6.C1.D0.R0.S03: RdPtrOffsetTxDq: 05
N0.C0.D1.R1.S15: TxDq : plus1 = 1, minus1 = 0, PI = 30, DB = 0
N2.C2.D0.R0.S11: PiTxDqs: 24
N4.C1.D0.R0.S12: TxDq : plus1 = 1, minus1 = 0, PI = 48, DB = 0
N6.C1.D0.R0.S03: RdPtrOffsetTxDqs: 07
N0.C0.D1.R1.S16: TxDqs: plus1 = 1, minus1 = 0, PI = 17, DB = 0
N2.C2.D0.R0.S12: wrcmd2dqsstartlatency: 04
N4.C1.D0.R0.S13: TxDqs: plus1 = 1, minus1 = 0, PI = 46, DB = 0
N6.C1.D0.R0.S03: PiTxDqs: 12
N0.C0.D1.R1.S16: TxDq : plus1 = 1, minus1 = 0, PI = 48, DB = 0
N2.C2.D0.R0.S12: RdPtrOffsetTxDq: 05
N4.C1.D0.R0.S13: TxDq : plus1 = 1, minus1 = 0, PI = 12, DB = 1
N6.C1.D0.R0.S04: wrcmd2dqsstartlatency: 04
N0.C0.D1.R1.S17: TxDqs: plus1 = 1, minus1 = 0, PI = 52, DB = 1
N2.C2.D0.R0.S12: RdPtrOffsetTxDqs: 07
N4.C1.D0.R0.S14: TxDqs: plus1 = 1, minus1 = 0, PI = 58, DB = 1
N6.C1.D0.R0.S04: RdPtrOffsetTxDq: 05
N0.C0.D1.R1.S17: TxDq : plus1 = 1, minus1 = 0, PI = 17, DB = 0
N2.C2.D0.R0.S12: PiTxDqs: 08
N4.C1.D0.R0.S14: TxDq : plus1 = 1, minus1 = 0, PI = 25, DB = 0
N6.C1.D0.R0.S04: RdPtrOffsetTxDqs: 06
END_DATA_TX_DQ
N2.C2.D0.R0.S13: wrcmd2dqsstartlatency: 04
N4.C1.D0.R0.S15: TxDqs: plus1 = 1, minus1 = 0, PI = 09, DB = 1
N6.C1.D0.R0.S04: PiTxDqs: 43
N0.C1.D0.R0.S00: wrcmd2dqsstartlatency: 04
N2.C2.D0.R0.S13: RdPtrOffsetTxDq: 04
N4.C1.D0.R0.S15: TxDq : plus1 = 1, minus1 = 0, PI = 41, DB = 0
N6.C1.D0.R0.S05: wrcmd2dqsstartlatency: 04
N0.C1.D0.R0.S00: RdPtrOffsetTxDq: 06
N2.C2.D0.R0.S13: RdPtrOffsetTxDqs: 06
N4.C1.D0.R0.S16: TxDqs: plus1 = 1, minus1 = 0, PI = 24, DB = 0
N6.C1.D0.R0.S05: RdPtrOffsetTxDq: 05
N0.C1.D0.R0.S00: RdPtrOffsetTxDqs: 07
N2.C2.D0.R0.S13: PiTxDqs: 31
N4.C1.D0.R0.S16: TxDq : plus1 = 1, minus1 = 0, PI = 55, DB = 1
N6.C1.D0.R0.S05: RdPtrOffsetTxDqs: 06
N0.C1.D0.R0.S00: PiTxDqs: 59
N2.C2.D0.R0.S14: wrcmd2dqsstartlatency: 04
N4.C1.D0.R0.S17: TxDqs: plus1 = 1, minus1 = 0, PI = 60, DB = 1
N6.C1.D0.R0.S05: PiTxDqs: 57
N0.C1.D0.R0.S01: wrcmd2dqsstartlatency: 04
N2.C2.D0.R0.S14: RdPtrOffsetTxDq: 05
N4.C1.D0.R0.S17: TxDq : plus1 = 1, minus1 = 0, PI = 28, DB = 0
N6.C1.D0.R0.S06: wrcmd2dqsstartlatency: 04
N0.C1.D0.R0.S01: RdPtrOffsetTxDq: 06
N2.C2.D0.R0.S14: RdPtrOffsetTxDqs: 06
N4.C1.D0.R1.S00: TxDqs: plus1 = 1, minus1 = 0, PI = 54, DB = 1
N6.C1.D0.R0.S06: RdPtrOffsetTxDq: 05
N0.C1.D0.R0.S01: RdPtrOffsetTxDqs: 07
N2.C2.D0.R0.S14: PiTxDqs: 58
N4.C1.D0.R1.S00: TxDq : plus1 = 1, minus1 = 0, PI = 22, DB = 0
N6.C1.D0.R0.S06: RdPtrOffsetTxDqs: 07
N0.C1.D0.R0.S01: PiTxDqs: 39
N2.C2.D0.R0.S15: wrcmd2dqsstartlatency: 04
N4.C1.D0.R1.S01: TxDqs: plus1 = 1, minus1 = 0, PI = 38, DB = 0
N6.C1.D0.R0.S06: PiTxDqs: 10
N0.C1.D0.R0.S02: wrcmd2dqsstartlatency: 04
N2.C2.D0.R0.S15: RdPtrOffsetTxDq: 05
N4.C1.D0.R1.S01: TxDq : plus1 = 1, minus1 = 0, PI = 05, DB = 1
N6.C1.D0.R0.S07: wrcmd2dqsstartlatency: 04
N0.C1.D0.R0.S02: RdPtrOffsetTxDq: 05
N2.C2.D0.R0.S15: RdPtrOffsetTxDqs: 06
N4.C1.D0.R1.S02: TxDqs: plus1 = 1, minus1 = 0, PI = 30, DB = 0
N6.C1.D0.R0.S07: RdPtrOffsetTxDq: 05
N0.C1.D0.R0.S02: RdPtrOffsetTxDqs: 07
N2.C2.D0.R0.S15: PiTxDqs: 56
N4.C1.D0.R1.S02: TxDq : plus1 = 1, minus1 = 0, PI = 60, DB = 1
N6.C1.D0.R0.S07: RdPtrOffsetTxDqs: 07
N0.C1.D0.R0.S02: PiTxDqs: 33
N2.C2.D0.R0.S16: wrcmd2dqsstartlatency: 04
N4.C1.D0.R1.S03: TxDqs: plus1 = 1, minus1 = 0, PI = 16, DB = 0
N6.C1.D0.R0.S07: PiTxDqs: 25
N0.C1.D0.R0.S03: wrcmd2dqsstartlatency: 04
N2.C2.D0.R0.S16: RdPtrOffsetTxDq: 05
N4.C1.D0.R1.S03: TxDq : plus1 = 1, minus1 = 0, PI = 46, DB = 0
N6.C1.D0.R0.S08: wrcmd2dqsstartlatency: 04
N0.C1.D0.R0.S03: RdPtrOffsetTxDq: 05
N2.C2.D0.R0.S16: RdPtrOffsetTxDqs: 07
N4.C1.D0.R1.S04: TxDqs: plus1 = 1, minus1 = 0, PI = 46, DB = 0
N6.C1.D0.R0.S08: RdPtrOffsetTxDq: 05
N0.C1.D0.R0.S03: RdPtrOffsetTxDqs: 07
N2.C2.D0.R0.S16: PiTxDqs: 16
N4.C1.D0.R1.S04: TxDq : plus1 = 1, minus1 = 0, PI = 13, DB = 1
N6.C1.D0.R0.S08: RdPtrOffsetTxDqs: 06
N0.C1.D0.R0.S03: PiTxDqs: 13
N2.C2.D0.R0.S17: wrcmd2dqsstartlatency: 04
N4.C1.D0.R1.S05: TxDqs: plus1 = 1, minus1 = 0, PI = 56, DB = 1
N6.C1.D0.R0.S08: PiTxDqs: 59
N0.C1.D0.R0.S04: wrcmd2dqsstartlatency: 04
N2.C2.D0.R0.S17: RdPtrOffsetTxDq: 05
N4.C1.D0.R1.S05: TxDq : plus1 = 1, minus1 = 0, PI = 23, DB = 0
N6.C1.D0.R0.S09: wrcmd2dqsstartlatency: 04
N0.C1.D0.R0.S04: RdPtrOffsetTxDq: 05
N2.C2.D0.R0.S17: RdPtrOffsetTxDqs: 06
N4.C1.D0.R1.S06: TxDqs: plus1 = 1, minus1 = 0, PI = 08, DB = 1
N6.C1.D0.R0.S09: RdPtrOffsetTxDq: 06
N0.C1.D0.R0.S04: RdPtrOffsetTxDqs: 06
N2.C2.D0.R0.S17: PiTxDqs: 51
N4.C1.D0.R1.S06: TxDq : plus1 = 1, minus1 = 0, PI = 39, DB = 0
N6.C1.D0.R0.S09: RdPtrOffsetTxDqs: 07
N0.C1.D0.R0.S04: PiTxDqs: 42
N2.C2.D0.R0.S00: RdPtrOffsetTxDq: 07
N4.C1.D0.R1.S07: TxDqs: plus1 = 1, minus1 = 0, PI = 24, DB = 0
N6.C1.D0.R0.S09: PiTxDqs: 55
N0.C1.D0.R0.S05: wrcmd2dqsstartlatency: 04
N2.C2.D0.R0.S01: RdPtrOffsetTxDq: 07
N4.C1.D0.R1.S07: TxDq : plus1 = 1, minus1 = 0, PI = 53, DB = 1
N6.C1.D0.R0.S10: wrcmd2dqsstartlatency: 04
N0.C1.D0.R0.S05: RdPtrOffsetTxDq: 05
N2.C2.D0.R0.S02: RdPtrOffsetTxDq: 06
N4.C1.D0.R1.S08: TxDqs: plus1 = 1, minus1 = 0, PI = 60, DB = 1
N6.C1.D0.R0.S10: RdPtrOffsetTxDq: 06
N0.C1.D0.R0.S05: RdPtrOffsetTxDqs: 06
N2.C2.D0.R0.S03: RdPtrOffsetTxDq: 06
N4.C1.D0.R1.S08: TxDq : plus1 = 1, minus1 = 0, PI = 27, DB = 0
N6.C1.D0.R0.S10: RdPtrOffsetTxDqs: 07
N0.C1.D0.R0.S05: PiTxDqs: 60
N2.C2.D0.R0.S04: RdPtrOffsetTxDq: 05
N4.C1.D0.R1.S09: TxDqs: plus1 = 1, minus1 = 0, PI = 55, DB = 1
N6.C1.D0.R0.S10: PiTxDqs: 37
N0.C1.D0.R0.S06: wrcmd2dqsstartlatency: 04
N2.C2.D0.R0.S05: RdPtrOffsetTxDq: 06
N4.C1.D0.R1.S09: TxDq : plus1 = 1, minus1 = 0, PI = 21, DB = 0
N6.C1.D0.R0.S11: wrcmd2dqsstartlatency: 04
N0.C1.D0.R0.S06: RdPtrOffsetTxDq: 05
N2.C2.D0.R0.S06: RdPtrOffsetTxDq: 06
N4.C1.D0.R1.S10: TxDqs: plus1 = 1, minus1 = 0, PI = 40, DB = 0
N6.C1.D0.R0.S11: RdPtrOffsetTxDq: 05
N0.C1.D0.R0.S06: RdPtrOffsetTxDqs: 07
N2.C2.D0.R0.S07: RdPtrOffsetTxDq: 06
N4.C1.D0.R1.S10: TxDq : plus1 = 1, minus1 = 0, PI = 07, DB = 1
N6.C1.D0.R0.S11: RdPtrOffsetTxDqs: 07
N0.C1.D0.R0.S06: PiTxDqs: 11
N2.C2.D0.R0.S08: RdPtrOffsetTxDq: 06
N4.C1.D0.R1.S11: TxDqs: plus1 = 1, minus1 = 0, PI = 31, DB = 0
N6.C1.D0.R0.S11: PiTxDqs: 30
N0.C1.D0.R0.S07: wrcmd2dqsstartlatency: 04
N2.C2.D0.R0.S09: RdPtrOffsetTxDq: 07
N4.C1.D0.R1.S11: TxDq : plus1 = 1, minus1 = 0, PI = 62, DB = 1
N6.C1.D0.R0.S12: wrcmd2dqsstartlatency: 04
N0.C1.D0.R0.S07: RdPtrOffsetTxDq: 05
N2.C2.D0.R0.S10: RdPtrOffsetTxDq: 07
N4.C1.D0.R1.S12: TxDqs: plus1 = 1, minus1 = 0, PI = 16, DB = 0
N6.C1.D0.R0.S12: RdPtrOffsetTxDq: 05
N0.C1.D0.R0.S07: RdPtrOffsetTxDqs: 07
N2.C2.D0.R0.S11: RdPtrOffsetTxDq: 06
N4.C1.D0.R1.S12: TxDq : plus1 = 1, minus1 = 0, PI = 48, DB = 0
N6.C1.D0.R0.S12: RdPtrOffsetTxDqs: 07
N0.C1.D0.R0.S07: PiTxDqs: 27
N2.C2.D0.R0.S12: RdPtrOffsetTxDq: 06
N4.C1.D0.R1.S13: TxDqs: plus1 = 1, minus1 = 0, PI = 46, DB = 0
N6.C1.D0.R0.S12: PiTxDqs: 13
N0.C1.D0.R0.S08: wrcmd2dqsstartlatency: 04
N2.C2.D0.R0.S13: RdPtrOffsetTxDq: 05
N4.C1.D0.R1.S13: TxDq : plus1 = 1, minus1 = 0, PI = 12, DB = 1
N6.C1.D0.R0.S13: wrcmd2dqsstartlatency: 04
N0.C1.D0.R0.S08: RdPtrOffsetTxDq: 05
N2.C2.D0.R0.S14: RdPtrOffsetTxDq: 06
N4.C1.D0.R1.S14: TxDqs: plus1 = 1, minus1 = 0, PI = 58, DB = 1
N6.C1.D0.R0.S13: RdPtrOffsetTxDq: 05
N0.C1.D0.R0.S08: RdPtrOffsetTxDqs: 06
N2.C2.D0.R0.S15: RdPtrOffsetTxDq: 06
N4.C1.D0.R1.S14: TxDq : plus1 = 1, minus1 = 0, PI = 25, DB = 0
N6.C1.D0.R0.S13: RdPtrOffsetTxDqs: 06
N0.C1.D0.R0.S08: PiTxDqs: 58
N2.C2.D0.R0.S16: RdPtrOffsetTxDq: 06
N4.C1.D0.R1.S15: TxDqs: plus1 = 1, minus1 = 0, PI = 09, DB = 1
N6.C1.D0.R0.S13: PiTxDqs: 42
N0.C1.D0.R0.S09: wrcmd2dqsstartlatency: 04
N2.C2.D0.R0.S17: RdPtrOffsetTxDq: 06
N4.C1.D0.R1.S15: TxDq : plus1 = 1, minus1 = 0, PI = 41, DB = 0
N6.C1.D0.R0.S14: wrcmd2dqsstartlatency: 04
N0.C1.D0.R0.S09: RdPtrOffsetTxDq: 06
N2.C2.D0.R0.S00: RdPtrOffsetTxDq: 08
N4.C1.D0.R1.S16: TxDqs: plus1 = 1, minus1 = 0, PI = 24, DB = 0
N6.C1.D0.R0.S14: RdPtrOffsetTxDq: 05
N0.C1.D0.R0.S09: RdPtrOffsetTxDqs: 07
N2.C2.D0.R0.S01: RdPtrOffsetTxDq: 08
N4.C1.D0.R1.S16: TxDq : plus1 = 1, minus1 = 0, PI = 55, DB = 1
N6.C1.D0.R0.S14: RdPtrOffsetTxDqs: 06
N0.C1.D0.R0.S09: PiTxDqs: 58
N2.C2.D0.R0.S02: RdPtrOffsetTxDq: 07
N4.C1.D0.R1.S17: TxDqs: plus1 = 1, minus1 = 0, PI = 60, DB = 1
N6.C1.D0.R0.S14: PiTxDqs: 56
N0.C1.D0.R0.S10: wrcmd2dqsstartlatency: 04
N2.C2.D0.R0.S03: RdPtrOffsetTxDq: 07
N4.C1.D0.R1.S17: TxDq : plus1 = 1, minus1 = 0, PI = 28, DB = 0
N6.C1.D0.R0.S15: wrcmd2dqsstartlatency: 04
N0.C1.D0.R0.S10: RdPtrOffsetTxDq: 06
N2.C2.D0.R0.S04: RdPtrOffsetTxDq: 06
N4.C1.D1.R0.S00: TxDqs: plus1 = 1, minus1 = 0, PI = 60, DB = 1
N6.C1.D0.R0.S15: RdPtrOffsetTxDq: 05
N0.C1.D0.R0.S10: RdPtrOffsetTxDqs: 07
N2.C2.D0.R0.S05: RdPtrOffsetTxDq: 07
N4.C1.D1.R0.S00: TxDq : plus1 = 1, minus1 = 0, PI = 26, DB = 0
N6.C1.D0.R0.S15: RdPtrOffsetTxDqs: 07
N0.C1.D0.R0.S10: PiTxDqs: 40
N2.C2.D0.R0.S06: RdPtrOffsetTxDq: 07
N4.C1.D1.R0.S01: TxDqs: plus1 = 1, minus1 = 0, PI = 45, DB = 0
N6.C1.D0.R0.S15: PiTxDqs: 08
N0.C1.D0.R0.S11: wrcmd2dqsstartlatency: 04
N2.C2.D0.R0.S07: RdPtrOffsetTxDq: 07
N4.C1.D1.R0.S01: TxDq : plus1 = 1, minus1 = 0, PI = 09, DB = 1
N6.C1.D0.R0.S16: wrcmd2dqsstartlatency: 04
N0.C1.D0.R0.S11: RdPtrOffsetTxDq: 06
N2.C2.D0.R0.S08: RdPtrOffsetTxDq: 07
N4.C1.D1.R0.S02: TxDqs: plus1 = 1, minus1 = 0, PI = 34, DB = 0
N6.C1.D0.R0.S16: RdPtrOffsetTxDq: 05
N0.C1.D0.R0.S11: RdPtrOffsetTxDqs: 07
N2.C2.D0.R0.S09: RdPtrOffsetTxDq: 08
N4.C1.D1.R0.S02: TxDq : plus1 = 1, minus1 = 0, PI = 63, DB = 1
N6.C1.D0.R0.S16: RdPtrOffsetTxDqs: 07
N0.C1.D0.R0.S11: PiTxDqs: 34
N2.C2.D0.R0.S10: RdPtrOffsetTxDq: 08
N4.C1.D1.R0.S03: TxDqs: plus1 = 1, minus1 = 0, PI = 19, DB = 0
N6.C1.D0.R0.S16: PiTxDqs: 24
N0.C1.D0.R0.S12: wrcmd2dqsstartlatency: 04
N2.C2.D0.R0.S11: RdPtrOffsetTxDq: 07
N4.C1.D1.R0.S03: TxDq : plus1 = 1, minus1 = 0, PI = 47, DB = 0
N6.C1.D0.R0.S17: wrcmd2dqsstartlatency: 04
N0.C1.D0.R0.S12: RdPtrOffsetTxDq: 05
N2.C2.D0.R0.S12: RdPtrOffsetTxDq: 07
N4.C1.D1.R0.S04: TxDqs: plus1 = 1, minus1 = 0, PI = 50, DB = 1
N6.C1.D0.R0.S17: RdPtrOffsetTxDq: 05
N0.C1.D0.R0.S12: RdPtrOffsetTxDqs: 07
N2.C2.D0.R0.S13: RdPtrOffsetTxDq: 06
N4.C1.D1.R0.S04: TxDq : plus1 = 1, minus1 = 0, PI = 14, DB = 1
N6.C1.D0.R0.S17: RdPtrOffsetTxDqs: 06
N0.C1.D0.R0.S12: PiTxDqs: 15
N2.C2.D0.R0.S14: RdPtrOffsetTxDq: 07
N4.C1.D1.R0.S05: TxDqs: plus1 = 1, minus1 = 0, PI = 63, DB = 1
N6.C1.D0.R0.S17: PiTxDqs: 59
N0.C1.D0.R0.S13: wrcmd2dqsstartlatency: 04
N2.C2.D0.R0.S15: RdPtrOffsetTxDq: 07
N4.C1.D1.R0.S05: TxDq : plus1 = 1, minus1 = 0, PI = 27, DB = 0
N6.C1.D0.R0.S00: RdPtrOffsetTxDq: 07
N0.C1.D0.R0.S13: RdPtrOffsetTxDq: 05
N2.C2.D0.R0.S16: RdPtrOffsetTxDq: 07
N4.C1.D1.R0.S06: TxDqs: plus1 = 1, minus1 = 0, PI = 11, DB = 1
N6.C1.D0.R0.S01: RdPtrOffsetTxDq: 07
N0.C1.D0.R0.S13: RdPtrOffsetTxDqs: 06
N2.C2.D0.R0.S17: RdPtrOffsetTxDq: 07
N4.C1.D1.R0.S06: TxDq : plus1 = 1, minus1 = 0, PI = 40, DB = 0
N6.C1.D0.R0.S02: RdPtrOffsetTxDq: 06
N0.C1.D0.R0.S13: PiTxDqs: 43
N2.C2.D0.R0.S00: Total Delay in PI ticks: TxDQ = 980
N4.C1.D1.R0.S07: TxDqs: plus1 = 1, minus1 = 0, PI = 29, DB = 0
N6.C1.D0.R0.S03: RdPtrOffsetTxDq: 06
N0.C1.D0.R0.S14: wrcmd2dqsstartlatency: 04
N2.C2.D0.R0.S01: Total Delay in PI ticks: TxDQ = 963
N4.C1.D1.R0.S07: TxDq : plus1 = 1, minus1 = 0, PI = 57, DB = 1
N6.C1.D0.R0.S04: RdPtrOffsetTxDq: 06
N0.C1.D0.R0.S14: RdPtrOffsetTxDq: 05
N2.C2.D0.R0.S02: Total Delay in PI ticks: TxDQ = 953
N4.C1.D1.R0.S08: TxDqs: plus1 = 1, minus1 = 0, PI = 61, DB = 1
N6.C1.D0.R0.S05: RdPtrOffsetTxDq: 06
N0.C1.D0.R0.S14: RdPtrOffsetTxDqs: 06
N2.C2.D0.R0.S03: Total Delay in PI ticks: TxDQ = 933
N4.C1.D1.R0.S08: TxDq : plus1 = 1, minus1 = 0, PI = 26, DB = 0
N6.C1.D0.R0.S06: RdPtrOffsetTxDq: 06
N0.C1.D0.R0.S14: PiTxDqs: 58
N2.C2.D0.R0.S04: Total Delay in PI ticks: TxDQ = 895
N4.C1.D1.R0.S09: TxDqs: plus1 = 1, minus1 = 0, PI = 58, DB = 1
N6.C1.D0.R0.S07: RdPtrOffsetTxDq: 06
N0.C1.D0.R0.S15: wrcmd2dqsstartlatency: 04
N2.C2.D0.R0.S05: Total Delay in PI ticks: TxDQ = 922
N4.C1.D1.R0.S09: TxDq : plus1 = 1, minus1 = 0, PI = 23, DB = 0
N6.C1.D0.R0.S08: RdPtrOffsetTxDq: 06
N0.C1.D0.R0.S15: RdPtrOffsetTxDq: 05
N2.C2.D0.R0.S06: Total Delay in PI ticks: TxDQ = 921
N4.C1.D1.R0.S10: TxDqs: plus1 = 1, minus1 = 0, PI = 43, DB = 0
N6.C1.D0.R0.S09: RdPtrOffsetTxDq: 07
N0.C1.D0.R0.S15: RdPtrOffsetTxDqs: 07
N2.C2.D0.R0.S07: Total Delay in PI ticks: TxDQ = 940
N4.C1.D1.R0.S10: TxDq : plus1 = 1, minus1 = 0, PI = 09, DB = 1
N6.C1.D0.R0.S10: RdPtrOffsetTxDq: 07
N0.C1.D0.R0.S15: PiTxDqs: 10
N2.C2.D0.R0.S08: Total Delay in PI ticks: TxDQ = 916
N4.C1.D1.R0.S11: TxDqs: plus1 = 1, minus1 = 0, PI = 34, DB = 0
N6.C1.D0.R0.S11: RdPtrOffsetTxDq: 06
N0.C1.D0.R0.S16: wrcmd2dqsstartlatency: 04
N2.C2.D0.R0.S09: Total Delay in PI ticks: TxDQ = 979
N4.C1.D1.R0.S11: TxDq : plus1 = 1, minus1 = 0, PI = 63, DB = 1
N6.C1.D0.R0.S12: RdPtrOffsetTxDq: 06
N0.C1.D0.R0.S16: RdPtrOffsetTxDq: 05
N2.C2.D0.R0.S10: Total Delay in PI ticks: TxDQ = 963
N4.C1.D1.R0.S12: TxDqs: plus1 = 1, minus1 = 0, PI = 19, DB = 0
N6.C1.D0.R0.S13: RdPtrOffsetTxDq: 06
N0.C1.D0.R0.S16: RdPtrOffsetTxDqs: 07
N2.C2.D0.R0.S11: Total Delay in PI ticks: TxDQ = 954
N4.C1.D1.R0.S12: TxDq : plus1 = 1, minus1 = 0, PI = 50, DB = 1
N6.C1.D0.R0.S14: RdPtrOffsetTxDq: 06
N0.C1.D0.R0.S16: PiTxDqs: 27
N2.C2.D0.R0.S12: Total Delay in PI ticks: TxDQ = 934
N4.C1.D1.R0.S13: TxDqs: plus1 = 1, minus1 = 0, PI = 50, DB = 1
N6.C1.D0.R0.S15: RdPtrOffsetTxDq: 06
N0.C1.D0.R0.S17: wrcmd2dqsstartlatency: 04
N2.C2.D0.R0.S13: Total Delay in PI ticks: TxDQ = 896
N4.C1.D1.R0.S13: TxDq : plus1 = 1, minus1 = 0, PI = 14, DB = 1
N6.C1.D0.R0.S16: RdPtrOffsetTxDq: 06
N0.C1.D0.R0.S17: RdPtrOffsetTxDq: 05
N2.C2.D0.R0.S14: Total Delay in PI ticks: TxDQ = 922
N4.C1.D1.R0.S14: TxDqs: plus1 = 1, minus1 = 0, PI = 62, DB = 1
N6.C1.D0.R0.S17: RdPtrOffsetTxDq: 06
N0.C1.D0.R0.S17: RdPtrOffsetTxDqs: 06
N2.C2.D0.R0.S15: Total Delay in PI ticks: TxDQ = 920
N4.C1.D1.R0.S14: TxDq : plus1 = 1, minus1 = 0, PI = 26, DB = 0
N6.C1.D0.R0.S00: RdPtrOffsetTxDq: 08
N0.C1.D0.R0.S17: PiTxDqs: 61
N2.C2.D0.R0.S16: Total Delay in PI ticks: TxDQ = 943
N4.C1.D1.R0.S15: TxDqs: plus1 = 1, minus1 = 0, PI = 12, DB = 1
N6.C1.D0.R0.S01: RdPtrOffsetTxDq: 08
N0.C1.D0.R0.S00: RdPtrOffsetTxDq: 07
N2.C2.D0.R0.S17: Total Delay in PI ticks: TxDQ = 916
N4.C1.D1.R0.S15: TxDq : plus1 = 1, minus1 = 0, PI = 41, DB = 0
N6.C1.D0.R0.S02: RdPtrOffsetTxDq: 07
N0.C1.D0.R0.S01: RdPtrOffsetTxDq: 07
N2.C2.D0.R1.S00: wrcmd2dqsstartlatency: 04
N4.C1.D1.R0.S16: TxDqs: plus1 = 1, minus1 = 0, PI = 30, DB = 0
N6.C1.D0.R0.S03: RdPtrOffsetTxDq: 07
N0.C1.D0.R0.S02: RdPtrOffsetTxDq: 06
N2.C2.D0.R1.S00: RdPtrOffsetTxDq: 06
N4.C1.D1.R0.S16: TxDq : plus1 = 1, minus1 = 0, PI = 58, DB = 1
N6.C1.D0.R0.S04: RdPtrOffsetTxDq: 07
N0.C1.D0.R0.S03: RdPtrOffsetTxDq: 06
N2.C2.D0.R1.S00: RdPtrOffsetTxDqs: 07
N4.C1.D1.R0.S17: TxDqs: plus1 = 1, minus1 = 0, PI = 60, DB = 1
N6.C1.D0.R0.S05: RdPtrOffsetTxDq: 07
N0.C1.D0.R0.S04: RdPtrOffsetTxDq: 06
N2.C2.D0.R1.S00: PiTxDqs: 43
N4.C1.D1.R0.S17: TxDq : plus1 = 1, minus1 = 0, PI = 25, DB = 0
N6.C1.D0.R0.S06: RdPtrOffsetTxDq: 07
N0.C1.D0.R0.S05: RdPtrOffsetTxDq: 06
N2.C2.D0.R1.S01: wrcmd2dqsstartlatency: 04
N4.C1.D1.R1.S00: TxDqs: plus1 = 1, minus1 = 0, PI = 60, DB = 1
N6.C1.D0.R0.S07: RdPtrOffsetTxDq: 07
N0.C1.D0.R0.S06: RdPtrOffsetTxDq: 06
N2.C2.D0.R1.S01: RdPtrOffsetTxDq: 05
N4.C1.D1.R1.S00: TxDq : plus1 = 1, minus1 = 0, PI = 26, DB = 0
N6.C1.D0.R0.S08: RdPtrOffsetTxDq: 07
N0.C1.D0.R0.S07: RdPtrOffsetTxDq: 06
N2.C2.D0.R1.S01: RdPtrOffsetTxDqs: 07
N4.C1.D1.R1.S01: TxDqs: plus1 = 1, minus1 = 0, PI = 45, DB = 0
N6.C1.D0.R0.S09: RdPtrOffsetTxDq: 08
N0.C1.D0.R0.S08: RdPtrOffsetTxDq: 06
N2.C2.D0.R1.S01: PiTxDqs: 28
N4.C1.D1.R1.S01: TxDq : plus1 = 1, minus1 = 0, PI = 09, DB = 1
N6.C1.D0.R0.S10: RdPtrOffsetTxDq: 08
N0.C1.D0.R0.S09: RdPtrOffsetTxDq: 07
N2.C2.D0.R1.S02: wrcmd2dqsstartlatency: 04
N4.C1.D1.R1.S02: TxDqs: plus1 = 1, minus1 = 0, PI = 34, DB = 0
N6.C1.D0.R0.S11: RdPtrOffsetTxDq: 07
N0.C1.D0.R0.S10: RdPtrOffsetTxDq: 07
N2.C2.D0.R1.S02: RdPtrOffsetTxDq: 05
N4.C1.D1.R1.S02: TxDq : plus1 = 1, minus1 = 0, PI = 63, DB = 1
N6.C1.D0.R0.S12: RdPtrOffsetTxDq: 07
N0.C1.D0.R0.S11: RdPtrOffsetTxDq: 07
N2.C2.D0.R1.S02: RdPtrOffsetTxDqs: 07
N4.C1.D1.R1.S03: TxDqs: plus1 = 1, minus1 = 0, PI = 19, DB = 0
N6.C1.D0.R0.S13: RdPtrOffsetTxDq: 07
N0.C1.D0.R0.S12: RdPtrOffsetTxDq: 06
N2.C2.D0.R1.S02: PiTxDqs: 17
N4.C1.D1.R1.S03: TxDq : plus1 = 1, minus1 = 0, PI = 47, DB = 0
N6.C1.D0.R0.S14: RdPtrOffsetTxDq: 07
N0.C1.D0.R0.S13: RdPtrOffsetTxDq: 06
N2.C2.D0.R1.S03: wrcmd2dqsstartlatency: 04
N4.C1.D1.R1.S04: TxDqs: plus1 = 1, minus1 = 0, PI = 50, DB = 1
N6.C1.D0.R0.S15: RdPtrOffsetTxDq: 07
N0.C1.D0.R0.S14: RdPtrOffsetTxDq: 06
N2.C2.D0.R1.S03: RdPtrOffsetTxDq: 05
N4.C1.D1.R1.S04: TxDq : plus1 = 1, minus1 = 0, PI = 14, DB = 1
N6.C1.D0.R0.S16: RdPtrOffsetTxDq: 07
N0.C1.D0.R0.S15: RdPtrOffsetTxDq: 06
N2.C2.D0.R1.S03: RdPtrOffsetTxDqs: 07
N4.C1.D1.R1.S05: TxDqs: plus1 = 1, minus1 = 0, PI = 63, DB = 1
N6.C1.D0.R0.S17: RdPtrOffsetTxDq: 07
N0.C1.D0.R0.S16: RdPtrOffsetTxDq: 06
N2.C2.D0.R1.S03: PiTxDqs: 01
N4.C1.D1.R1.S05: TxDq : plus1 = 1, minus1 = 0, PI = 27, DB = 0
N6.C1.D0.R0.S00: Total Delay in PI ticks: TxDQ = 982
N0.C1.D0.R0.S17: RdPtrOffsetTxDq: 06
N2.C2.D0.R1.S04: wrcmd2dqsstartlatency: 04
N4.C1.D1.R1.S06: TxDqs: plus1 = 1, minus1 = 0, PI = 11, DB = 1
N6.C1.D0.R0.S01: Total Delay in PI ticks: TxDQ = 965
N0.C1.D0.R0.S00: RdPtrOffsetTxDq: 08
N2.C2.D0.R1.S04: RdPtrOffsetTxDq: 04
N4.C1.D1.R1.S06: TxDq : plus1 = 1, minus1 = 0, PI = 40, DB = 0
N6.C1.D0.R0.S02: Total Delay in PI ticks: TxDQ = 956
N0.C1.D0.R0.S01: RdPtrOffsetTxDq: 08
N2.C2.D0.R1.S04: RdPtrOffsetTxDqs: 06
N4.C1.D1.R1.S07: TxDqs: plus1 = 1, minus1 = 0, PI = 29, DB = 0
N6.C1.D0.R0.S03: Total Delay in PI ticks: TxDQ = 941
N0.C1.D0.R0.S02: RdPtrOffsetTxDq: 07
N2.C2.D0.R1.S04: PiTxDqs: 25
N4.C1.D1.R1.S07: TxDq : plus1 = 1, minus1 = 0, PI = 57, DB = 1
N6.C1.D0.R0.S04: Total Delay in PI ticks: TxDQ = 907
N0.C1.D0.R0.S03: RdPtrOffsetTxDq: 07
N2.C2.D0.R1.S05: wrcmd2dqsstartlatency: 04
N4.C1.D1.R1.S08: TxDqs: plus1 = 1, minus1 = 0, PI = 61, DB = 1
N6.C1.D0.R0.S05: Total Delay in PI ticks: TxDQ = 920
N0.C1.D0.R0.S04: RdPtrOffsetTxDq: 07
N2.C2.D0.R1.S05: RdPtrOffsetTxDq: 05
N4.C1.D1.R1.S08: TxDq : plus1 = 1, minus1 = 0, PI = 26, DB = 0
N6.C1.D0.R0.S06: Total Delay in PI ticks: TxDQ = 939
N0.C1.D0.R0.S05: RdPtrOffsetTxDq: 07
N2.C2.D0.R1.S05: RdPtrOffsetTxDqs: 06
N4.C1.D1.R1.S09: TxDqs: plus1 = 1, minus1 = 0, PI = 58, DB = 1
N6.C1.D0.R0.S07: Total Delay in PI ticks: TxDQ = 951
N0.C1.D0.R0.S06: RdPtrOffsetTxDq: 07
N2.C2.D0.R1.S05: PiTxDqs: 54
N4.C1.D1.R1.S09: TxDq : plus1 = 1, minus1 = 0, PI = 23, DB = 0
N6.C1.D0.R0.S08: Total Delay in PI ticks: TxDQ = 925
N0.C1.D0.R0.S07: RdPtrOffsetTxDq: 07
N2.C2.D0.R1.S06: wrcmd2dqsstartlatency: 04
N4.C1.D1.R1.S10: TxDqs: plus1 = 1, minus1 = 0, PI = 43, DB = 0
N6.C1.D0.R0.S09: Total Delay in PI ticks: TxDQ = 982
N0.C1.D0.R0.S08: RdPtrOffsetTxDq: 07
N2.C2.D0.R1.S06: RdPtrOffsetTxDq: 05
N4.C1.D1.R1.S10: TxDq : plus1 = 1, minus1 = 0, PI = 09, DB = 1
N6.C1.D0.R0.S10: Total Delay in PI ticks: TxDQ = 966
N0.C1.D0.R0.S09: RdPtrOffsetTxDq: 08
N2.C2.D0.R1.S06: RdPtrOffsetTxDqs: 06
N4.C1.D1.R1.S11: TxDqs: plus1 = 1, minus1 = 0, PI = 34, DB = 0
N6.C1.D0.R0.S11: Total Delay in PI ticks: TxDQ = 957
N0.C1.D0.R0.S10: RdPtrOffsetTxDq: 08
N2.C2.D0.R1.S06: PiTxDqs: 50
N4.C1.D1.R1.S11: TxDq : plus1 = 1, minus1 = 0, PI = 63, DB = 1
N6.C1.D0.R0.S12: Total Delay in PI ticks: TxDQ = 942
N0.C1.D0.R0.S11: RdPtrOffsetTxDq: 08
N2.C2.D0.R1.S07: wrcmd2dqsstartlatency: 04
N4.C1.D1.R1.S12: TxDqs: plus1 = 1, minus1 = 0, PI = 19, DB = 0
N6.C1.D0.R0.S13: Total Delay in PI ticks: TxDQ = 908
N0.C1.D0.R0.S12: RdPtrOffsetTxDq: 07
N2.C2.D0.R1.S07: RdPtrOffsetTxDq: 05
N4.C1.D1.R1.S12: TxDq : plus1 = 1, minus1 = 0, PI = 50, DB = 1
N6.C1.D0.R0.S14: Total Delay in PI ticks: TxDQ = 920
N0.C1.D0.R0.S13: RdPtrOffsetTxDq: 07
N2.C2.D0.R1.S07: RdPtrOffsetTxDqs: 07
N4.C1.D1.R1.S13: TxDqs: plus1 = 1, minus1 = 0, PI = 50, DB = 1
N6.C1.D0.R0.S15: Total Delay in PI ticks: TxDQ = 938
N0.C1.D0.R0.S14: RdPtrOffsetTxDq: 07
N2.C2.D0.R1.S07: PiTxDqs: 09
N4.C1.D1.R1.S13: TxDq : plus1 = 1, minus1 = 0, PI = 14, DB = 1
N6.C1.D0.R0.S16: Total Delay in PI ticks: TxDQ = 952
N0.C1.D0.R0.S15: RdPtrOffsetTxDq: 07
N2.C2.D0.R1.S08: wrcmd2dqsstartlatency: 04
N4.C1.D1.R1.S14: TxDqs: plus1 = 1, minus1 = 0, PI = 62, DB = 1
N6.C1.D0.R0.S17: Total Delay in PI ticks: TxDQ = 924
N0.C1.D0.R0.S16: RdPtrOffsetTxDq: 07
N2.C2.D0.R1.S08: RdPtrOffsetTxDq: 05
N4.C1.D1.R1.S14: TxDq : plus1 = 1, minus1 = 0, PI = 26, DB = 0
N6.C1.D0.R1.S00: wrcmd2dqsstartlatency: 04
N0.C1.D0.R0.S17: RdPtrOffsetTxDq: 07
N2.C2.D0.R1.S08: RdPtrOffsetTxDqs: 06
N4.C1.D1.R1.S15: TxDqs: plus1 = 1, minus1 = 0, PI = 12, DB = 1
N6.C1.D0.R1.S00: RdPtrOffsetTxDq: 06
N0.C1.D0.R0.S00: Total Delay in PI ticks: TxDQ = 987
N2.C2.D0.R1.S08: PiTxDqs: 42
N4.C1.D1.R1.S15: TxDq : plus1 = 1, minus1 = 0, PI = 41, DB = 0
N6.C1.D0.R1.S00: RdPtrOffsetTxDqs: 07
N0.C1.D0.R0.S01: Total Delay in PI ticks: TxDQ = 965
N2.C2.D0.R1.S09: wrcmd2dqsstartlatency: 04
N4.C1.D1.R1.S16: TxDqs: plus1 = 1, minus1 = 0, PI = 30, DB = 0
N6.C1.D0.R1.S00: PiTxDqs: 49
N0.C1.D0.R0.S02: Total Delay in PI ticks: TxDQ = 959
N2.C2.D0.R1.S09: RdPtrOffsetTxDq: 06
N4.C1.D1.R1.S16: TxDq : plus1 = 1, minus1 = 0, PI = 58, DB = 1
N6.C1.D0.R1.S01: wrcmd2dqsstartlatency: 04
N0.C1.D0.R0.S03: Total Delay in PI ticks: TxDQ = 939
N2.C2.D0.R1.S09: RdPtrOffsetTxDqs: 07
N4.C1.D1.R1.S17: TxDqs: plus1 = 1, minus1 = 0, PI = 60, DB = 1
N6.C1.D0.R1.S01: RdPtrOffsetTxDq: 05
N0.C1.D0.R0.S04: Total Delay in PI ticks: TxDQ = 904
N2.C2.D0.R1.S09: PiTxDqs: 42
N4.C1.D1.R1.S17: TxDq : plus1 = 1, minus1 = 0, PI = 25, DB = 0
N6.C1.D0.R1.S01: RdPtrOffsetTxDqs: 07
N0.C1.D0.R0.S05: Total Delay in PI ticks: TxDQ = 922
N2.C2.D0.R1.S10: wrcmd2dqsstartlatency: 04
END_DATA_TX_DQ
N6.C1.D0.R1.S01: PiTxDqs: 31
N0.C1.D0.R0.S06: Total Delay in PI ticks: TxDQ = 939
N2.C2.D0.R1.S10: RdPtrOffsetTxDq: 05
N4.C2.D0.R0.S00: wrcmd2dqsstartlatency: 04
N6.C1.D0.R1.S02: wrcmd2dqsstartlatency: 04
N0.C1.D0.R0.S07: Total Delay in PI ticks: TxDQ = 954
N2.C2.D0.R1.S10: RdPtrOffsetTxDqs: 07
N4.C2.D0.R0.S00: RdPtrOffsetTxDq: 06
N6.C1.D0.R1.S02: RdPtrOffsetTxDq: 05
N0.C1.D0.R0.S08: Total Delay in PI ticks: TxDQ = 920
N2.C2.D0.R1.S10: PiTxDqs: 28
N4.C2.D0.R0.S00: RdPtrOffsetTxDqs: 07
N6.C1.D0.R1.S02: RdPtrOffsetTxDqs: 07
N0.C1.D0.R0.S09: Total Delay in PI ticks: TxDQ = 985
N2.C2.D0.R1.S11: wrcmd2dqsstartlatency: 04
N4.C2.D0.R0.S00: PiTxDqs: 52
N6.C1.D0.R1.S02: PiTxDqs: 23
N0.C1.D0.R0.S10: Total Delay in PI ticks: TxDQ = 966
N2.C2.D0.R1.S11: RdPtrOffsetTxDq: 05
N4.C2.D0.R0.S01: wrcmd2dqsstartlatency: 04
N6.C1.D0.R1.S03: wrcmd2dqsstartlatency: 04
N0.C1.D0.R0.S11: Total Delay in PI ticks: TxDQ = 962
N2.C2.D0.R1.S11: RdPtrOffsetTxDqs: 07
N4.C2.D0.R0.S01: RdPtrOffsetTxDq: 06
N6.C1.D0.R1.S03: RdPtrOffsetTxDq: 05
N0.C1.D0.R0.S12: Total Delay in PI ticks: TxDQ = 942
N2.C2.D0.R1.S11: PiTxDqs: 19
N4.C2.D0.R0.S01: RdPtrOffsetTxDqs: 07
N6.C1.D0.R1.S03: RdPtrOffsetTxDqs: 07
N0.C1.D0.R0.S13: Total Delay in PI ticks: TxDQ = 906
N2.C2.D0.R1.S12: wrcmd2dqsstartlatency: 04
N4.C2.D0.R0.S01: PiTxDqs: 38
N6.C1.D0.R1.S03: PiTxDqs: 05
N0.C1.D0.R0.S14: Total Delay in PI ticks: TxDQ = 920
N2.C2.D0.R1.S12: RdPtrOffsetTxDq: 05
N4.C2.D0.R0.S02: wrcmd2dqsstartlatency: 04
N6.C1.D0.R1.S04: wrcmd2dqsstartlatency: 04
N0.C1.D0.R0.S15: Total Delay in PI ticks: TxDQ = 938
N2.C2.D0.R1.S12: RdPtrOffsetTxDqs: 07
N4.C2.D0.R0.S02: RdPtrOffsetTxDq: 05
N6.C1.D0.R1.S04: RdPtrOffsetTxDq: 05
N0.C1.D0.R0.S16: Total Delay in PI ticks: TxDQ = 953
N2.C2.D0.R1.S12: PiTxDqs: 03
N4.C2.D0.R0.S02: RdPtrOffsetTxDqs: 07
N6.C1.D0.R1.S04: RdPtrOffsetTxDqs: 06
N0.C1.D0.R0.S17: Total Delay in PI ticks: TxDQ = 925
N2.C2.D0.R1.S13: wrcmd2dqsstartlatency: 04
N4.C2.D0.R0.S02: PiTxDqs: 29
N6.C1.D0.R1.S04: PiTxDqs: 39
N0.C1.D0.R1.S00: wrcmd2dqsstartlatency: 04
N2.C2.D0.R1.S13: RdPtrOffsetTxDq: 04
N4.C2.D0.R0.S03: wrcmd2dqsstartlatency: 04
N6.C1.D0.R1.S05: wrcmd2dqsstartlatency: 04
N0.C1.D0.R1.S00: RdPtrOffsetTxDq: 06
N2.C2.D0.R1.S13: RdPtrOffsetTxDqs: 06
N4.C2.D0.R0.S03: RdPtrOffsetTxDq: 05
N6.C1.D0.R1.S05: RdPtrOffsetTxDq: 05
N0.C1.D0.R1.S00: RdPtrOffsetTxDqs: 07
N2.C2.D0.R1.S13: PiTxDqs: 25
N4.C2.D0.R0.S03: RdPtrOffsetTxDqs: 07
N6.C1.D0.R1.S05: RdPtrOffsetTxDqs: 06
N0.C1.D0.R1.S00: PiTxDqs: 50
N2.C2.D0.R1.S14: wrcmd2dqsstartlatency: 04
N4.C2.D0.R0.S03: PiTxDqs: 09
N6.C1.D0.R1.S05: PiTxDqs: 51
N0.C1.D0.R1.S01: wrcmd2dqsstartlatency: 04
N2.C2.D0.R1.S14: RdPtrOffsetTxDq: 05
N4.C2.D0.R0.S04: wrcmd2dqsstartlatency: 04
N6.C1.D0.R1.S06: wrcmd2dqsstartlatency: 04
N0.C1.D0.R1.S01: RdPtrOffsetTxDq: 05
N2.C2.D0.R1.S14: RdPtrOffsetTxDqs: 06
N4.C2.D0.R0.S04: RdPtrOffsetTxDq: 04
N6.C1.D0.R1.S06: RdPtrOffsetTxDq: 05
N0.C1.D0.R1.S01: RdPtrOffsetTxDqs: 07
N2.C2.D0.R1.S14: PiTxDqs: 54
N4.C2.D0.R0.S04: RdPtrOffsetTxDqs: 06
N6.C1.D0.R1.S06: RdPtrOffsetTxDqs: 07
N0.C1.D0.R1.S01: PiTxDqs: 32
N2.C2.D0.R1.S15: wrcmd2dqsstartlatency: 04
N4.C2.D0.R0.S04: PiTxDqs: 31
N6.C1.D0.R1.S06: PiTxDqs: 01
N0.C1.D0.R1.S02: wrcmd2dqsstartlatency: 04
N2.C2.D0.R1.S15: RdPtrOffsetTxDq: 05
N4.C2.D0.R0.S05: wrcmd2dqsstartlatency: 04
N6.C1.D0.R1.S07: wrcmd2dqsstartlatency: 04
N0.C1.D0.R1.S02: RdPtrOffsetTxDq: 05
N2.C2.D0.R1.S15: RdPtrOffsetTxDqs: 06
N4.C2.D0.R0.S05: RdPtrOffsetTxDq: 05
N6.C1.D0.R1.S07: RdPtrOffsetTxDq: 05
N0.C1.D0.R1.S02: RdPtrOffsetTxDqs: 07
N2.C2.D0.R1.S15: PiTxDqs: 51
N4.C2.D0.R0.S05: RdPtrOffsetTxDqs: 06
N6.C1.D0.R1.S07: RdPtrOffsetTxDqs: 07
N0.C1.D0.R1.S02: PiTxDqs: 25
N2.C2.D0.R1.S16: wrcmd2dqsstartlatency: 04
N4.C2.D0.R0.S05: PiTxDqs: 62
N6.C1.D0.R1.S07: PiTxDqs: 17
N0.C1.D0.R1.S03: wrcmd2dqsstartlatency: 04
N2.C2.D0.R1.S16: RdPtrOffsetTxDq: 05
N4.C2.D0.R0.S06: wrcmd2dqsstartlatency: 04
N6.C1.D0.R1.S08: wrcmd2dqsstartlatency: 04
N0.C1.D0.R1.S03: RdPtrOffsetTxDq: 05
N2.C2.D0.R1.S16: RdPtrOffsetTxDqs: 07
N4.C2.D0.R0.S06: RdPtrOffsetTxDq: 05
N6.C1.D0.R1.S08: RdPtrOffsetTxDq: 05
N0.C1.D0.R1.S03: RdPtrOffsetTxDqs: 07
N2.C2.D0.R1.S16: PiTxDqs: 10
N4.C2.D0.R0.S06: RdPtrOffsetTxDqs: 06
N6.C1.D0.R1.S08: RdPtrOffsetTxDqs: 06
N0.C1.D0.R1.S03: PiTxDqs: 08
N2.C2.D0.R1.S17: wrcmd2dqsstartlatency: 04
N4.C2.D0.R0.S06: PiTxDqs: 63
N6.C1.D0.R1.S08: PiTxDqs: 52
N0.C1.D0.R1.S04: wrcmd2dqsstartlatency: 04
N2.C2.D0.R1.S17: RdPtrOffsetTxDq: 05
N4.C2.D0.R0.S07: wrcmd2dqsstartlatency: 04
N6.C1.D0.R1.S09: wrcmd2dqsstartlatency: 04
N0.C1.D0.R1.S04: RdPtrOffsetTxDq: 05
N2.C2.D0.R1.S17: RdPtrOffsetTxDqs: 06
N4.C2.D0.R0.S07: RdPtrOffsetTxDq: 05
N6.C1.D0.R1.S09: RdPtrOffsetTxDq: 06
N0.C1.D0.R1.S04: RdPtrOffsetTxDqs: 06
N2.C2.D0.R1.S17: PiTxDqs: 42
N4.C2.D0.R0.S07: RdPtrOffsetTxDqs: 07
N6.C1.D0.R1.S09: RdPtrOffsetTxDqs: 07
N0.C1.D0.R1.S04: PiTxDqs: 36
N2.C2.D0.R1.S00: RdPtrOffsetTxDq: 07
N4.C2.D0.R0.S07: PiTxDqs: 15
N6.C1.D0.R1.S09: PiTxDqs: 47
N0.C1.D0.R1.S05: wrcmd2dqsstartlatency: 04
N2.C2.D0.R1.S01: RdPtrOffsetTxDq: 06
N4.C2.D0.R0.S08: wrcmd2dqsstartlatency: 04
N6.C1.D0.R1.S10: wrcmd2dqsstartlatency: 04
N0.C1.D0.R1.S05: RdPtrOffsetTxDq: 05
N2.C2.D0.R1.S02: RdPtrOffsetTxDq: 06
N4.C2.D0.R0.S08: RdPtrOffsetTxDq: 05
N6.C1.D0.R1.S10: RdPtrOffsetTxDq: 05
N0.C1.D0.R1.S05: RdPtrOffsetTxDqs: 06
N2.C2.D0.R1.S03: RdPtrOffsetTxDq: 06
N4.C2.D0.R0.S08: RdPtrOffsetTxDqs: 06
N6.C1.D0.R1.S10: RdPtrOffsetTxDqs: 07
N0.C1.D0.R1.S05: PiTxDqs: 53
N2.C2.D0.R1.S04: RdPtrOffsetTxDq: 05
N4.C2.D0.R0.S08: PiTxDqs: 55
N6.C1.D0.R1.S10: PiTxDqs: 31
N0.C1.D0.R1.S06: wrcmd2dqsstartlatency: 04
N2.C2.D0.R1.S05: RdPtrOffsetTxDq: 06
N4.C2.D0.R0.S09: wrcmd2dqsstartlatency: 04
N6.C1.D0.R1.S11: wrcmd2dqsstartlatency: 04
N0.C1.D0.R1.S06: RdPtrOffsetTxDq: 05
N2.C2.D0.R1.S06: RdPtrOffsetTxDq: 06
N4.C2.D0.R0.S09: RdPtrOffsetTxDq: 06
N6.C1.D0.R1.S11: RdPtrOffsetTxDq: 05
N0.C1.D0.R1.S06: RdPtrOffsetTxDqs: 07
N2.C2.D0.R1.S07: RdPtrOffsetTxDq: 06
N4.C2.D0.R0.S09: RdPtrOffsetTxDqs: 07
N6.C1.D0.R1.S11: RdPtrOffsetTxDqs: 07
N0.C1.D0.R1.S06: PiTxDqs: 02
N2.C2.D0.R1.S08: RdPtrOffsetTxDq: 06
N4.C2.D0.R0.S09: PiTxDqs: 55
N6.C1.D0.R1.S11: PiTxDqs: 23
N0.C1.D0.R1.S07: wrcmd2dqsstartlatency: 04
N2.C2.D0.R1.S09: RdPtrOffsetTxDq: 07
N4.C2.D0.R0.S10: wrcmd2dqsstartlatency: 04
N6.C1.D0.R1.S12: wrcmd2dqsstartlatency: 04
N0.C1.D0.R1.S07: RdPtrOffsetTxDq: 05
N2.C2.D0.R1.S10: RdPtrOffsetTxDq: 06
N4.C2.D0.R0.S10: RdPtrOffsetTxDq: 06
N6.C1.D0.R1.S12: RdPtrOffsetTxDq: 05
N0.C1.D0.R1.S07: RdPtrOffsetTxDqs: 07
N2.C2.D0.R1.S11: RdPtrOffsetTxDq: 06
N4.C2.D0.R0.S10: RdPtrOffsetTxDqs: 07
N6.C1.D0.R1.S12: RdPtrOffsetTxDqs: 07
N0.C1.D0.R1.S07: PiTxDqs: 20
N2.C2.D0.R1.S12: RdPtrOffsetTxDq: 06
N4.C2.D0.R0.S10: PiTxDqs: 41
N6.C1.D0.R1.S12: PiTxDqs: 06
N0.C1.D0.R1.S08: wrcmd2dqsstartlatency: 04
N2.C2.D0.R1.S13: RdPtrOffsetTxDq: 05
N4.C2.D0.R0.S11: wrcmd2dqsstartlatency: 04
N6.C1.D0.R1.S13: wrcmd2dqsstartlatency: 04
N0.C1.D0.R1.S08: RdPtrOffsetTxDq: 05
N2.C2.D0.R1.S14: RdPtrOffsetTxDq: 06
N4.C2.D0.R0.S11: RdPtrOffsetTxDq: 05
N6.C1.D0.R1.S13: RdPtrOffsetTxDq: 05
N0.C1.D0.R1.S08: RdPtrOffsetTxDqs: 06
N2.C2.D0.R1.S15: RdPtrOffsetTxDq: 06
N4.C2.D0.R0.S11: RdPtrOffsetTxDqs: 07
N6.C1.D0.R1.S13: RdPtrOffsetTxDqs: 06
N0.C1.D0.R1.S08: PiTxDqs: 53
N2.C2.D0.R1.S16: RdPtrOffsetTxDq: 06
N4.C2.D0.R0.S11: PiTxDqs: 29
N6.C1.D0.R1.S13: PiTxDqs: 37
N0.C1.D0.R1.S09: wrcmd2dqsstartlatency: 04
N2.C2.D0.R1.S17: RdPtrOffsetTxDq: 06
N4.C2.D0.R0.S12: wrcmd2dqsstartlatency: 04
N6.C1.D0.R1.S14: wrcmd2dqsstartlatency: 04
N0.C1.D0.R1.S09: RdPtrOffsetTxDq: 06
N2.C2.D0.R1.S00: RdPtrOffsetTxDq: 08
N4.C2.D0.R0.S12: RdPtrOffsetTxDq: 05
N6.C1.D0.R1.S14: RdPtrOffsetTxDq: 05
N0.C1.D0.R1.S09: RdPtrOffsetTxDqs: 07
N2.C2.D0.R1.S01: RdPtrOffsetTxDq: 07
N4.C2.D0.R0.S12: RdPtrOffsetTxDqs: 07
N6.C1.D0.R1.S14: RdPtrOffsetTxDqs: 06
N0.C1.D0.R1.S09: PiTxDqs: 49
N2.C2.D0.R1.S02: RdPtrOffsetTxDq: 07
N4.C2.D0.R0.S12: PiTxDqs: 10
N6.C1.D0.R1.S14: PiTxDqs: 49
N0.C1.D0.R1.S10: wrcmd2dqsstartlatency: 04
N2.C2.D0.R1.S03: RdPtrOffsetTxDq: 07
N4.C2.D0.R0.S13: wrcmd2dqsstartlatency: 04
N6.C1.D0.R1.S15: wrcmd2dqsstartlatency: 04
N0.C1.D0.R1.S10: RdPtrOffsetTxDq: 05
N2.C2.D0.R1.S04: RdPtrOffsetTxDq: 06
N4.C2.D0.R0.S13: RdPtrOffsetTxDq: 05
N6.C1.D0.R1.S15: RdPtrOffsetTxDq: 05
N0.C1.D0.R1.S10: RdPtrOffsetTxDqs: 07
N2.C2.D0.R1.S05: RdPtrOffsetTxDq: 07
N4.C2.D0.R0.S13: RdPtrOffsetTxDqs: 06
N6.C1.D0.R1.S15: RdPtrOffsetTxDqs: 07
N0.C1.D0.R1.S10: PiTxDqs: 33
N2.C2.D0.R1.S06: RdPtrOffsetTxDq: 07
N4.C2.D0.R0.S13: PiTxDqs: 34
N6.C1.D0.R1.S15: PiTxDqs: 01
N0.C1.D0.R1.S11: wrcmd2dqsstartlatency: 04
N2.C2.D0.R1.S07: RdPtrOffsetTxDq: 07
N4.C2.D0.R0.S14: wrcmd2dqsstartlatency: 04
N6.C1.D0.R1.S16: wrcmd2dqsstartlatency: 04
N0.C1.D0.R1.S11: RdPtrOffsetTxDq: 05
N2.C2.D0.R1.S08: RdPtrOffsetTxDq: 07
N4.C2.D0.R0.S14: RdPtrOffsetTxDq: 05
N6.C1.D0.R1.S16: RdPtrOffsetTxDq: 05
N0.C1.D0.R1.S11: RdPtrOffsetTxDqs: 07
N2.C2.D0.R1.S09: RdPtrOffsetTxDq: 08
N4.C2.D0.R0.S14: RdPtrOffsetTxDqs: 06
N6.C1.D0.R1.S16: RdPtrOffsetTxDqs: 07
N0.C1.D0.R1.S11: PiTxDqs: 23
N2.C2.D0.R1.S10: RdPtrOffsetTxDq: 07
N4.C2.D0.R0.S14: PiTxDqs: 62
N6.C1.D0.R1.S16: PiTxDqs: 18
N0.C1.D0.R1.S12: wrcmd2dqsstartlatency: 04
N2.C2.D0.R1.S11: RdPtrOffsetTxDq: 07
N4.C2.D0.R0.S15: wrcmd2dqsstartlatency: 04
N6.C1.D0.R1.S17: wrcmd2dqsstartlatency: 04
N0.C1.D0.R1.S12: RdPtrOffsetTxDq: 05
N2.C2.D0.R1.S12: RdPtrOffsetTxDq: 07
N4.C2.D0.R0.S15: RdPtrOffsetTxDq: 05
N6.C1.D0.R1.S17: RdPtrOffsetTxDq: 05
N0.C1.D0.R1.S12: RdPtrOffsetTxDqs: 07
N2.C2.D0.R1.S13: RdPtrOffsetTxDq: 06
N4.C2.D0.R0.S15: RdPtrOffsetTxDqs: 06
N6.C1.D0.R1.S17: RdPtrOffsetTxDqs: 06
N0.C1.D0.R1.S12: PiTxDqs: 09
N2.C2.D0.R1.S14: RdPtrOffsetTxDq: 07
N4.C2.D0.R0.S15: PiTxDqs: 62
N6.C1.D0.R1.S17: PiTxDqs: 50
N0.C1.D0.R1.S13: wrcmd2dqsstartlatency: 04
N2.C2.D0.R1.S15: RdPtrOffsetTxDq: 07
N4.C2.D0.R0.S16: wrcmd2dqsstartlatency: 04
N6.C1.D0.R1.S00: RdPtrOffsetTxDq: 07
N0.C1.D0.R1.S13: RdPtrOffsetTxDq: 05
N2.C2.D0.R1.S16: RdPtrOffsetTxDq: 07
N4.C2.D0.R0.S16: RdPtrOffsetTxDq: 05
N6.C1.D0.R1.S01: RdPtrOffsetTxDq: 06
N0.C1.D0.R1.S13: RdPtrOffsetTxDqs: 06
N2.C2.D0.R1.S17: RdPtrOffsetTxDq: 07
N4.C2.D0.R0.S16: RdPtrOffsetTxDqs: 07
N6.C1.D0.R1.S02: RdPtrOffsetTxDq: 06
N0.C1.D0.R1.S13: PiTxDqs: 39
N2.C2.D0.R1.S00: Total Delay in PI ticks: TxDQ = 972
N4.C2.D0.R0.S16: PiTxDqs: 16
N6.C1.D0.R1.S03: RdPtrOffsetTxDq: 06
N0.C1.D0.R1.S14: wrcmd2dqsstartlatency: 04
N2.C2.D0.R1.S01: Total Delay in PI ticks: TxDQ = 956
N4.C2.D0.R0.S17: wrcmd2dqsstartlatency: 04
N6.C1.D0.R1.S04: RdPtrOffsetTxDq: 06
N0.C1.D0.R1.S14: RdPtrOffsetTxDq: 05
N2.C2.D0.R1.S02: Total Delay in PI ticks: TxDQ = 948
N4.C2.D0.R0.S17: RdPtrOffsetTxDq: 05
N6.C1.D0.R1.S05: RdPtrOffsetTxDq: 06
N0.C1.D0.R1.S14: RdPtrOffsetTxDqs: 06
N2.C2.D0.R1.S03: Total Delay in PI ticks: TxDQ = 929
N4.C2.D0.R0.S17: RdPtrOffsetTxDqs: 06
N6.C1.D0.R1.S06: RdPtrOffsetTxDq: 06
N0.C1.D0.R1.S14: PiTxDqs: 56
N2.C2.D0.R1.S04: Total Delay in PI ticks: TxDQ = 891
N4.C2.D0.R0.S17: PiTxDqs: 51
N6.C1.D0.R1.S07: RdPtrOffsetTxDq: 06
N0.C1.D0.R1.S15: wrcmd2dqsstartlatency: 04
N2.C2.D0.R1.S05: Total Delay in PI ticks: TxDQ = 917
N4.C2.D0.R0.S00: RdPtrOffsetTxDq: 07
N6.C1.D0.R1.S08: RdPtrOffsetTxDq: 06
N0.C1.D0.R1.S15: RdPtrOffsetTxDq: 05
N2.C2.D0.R1.S06: Total Delay in PI ticks: TxDQ = 914
N4.C2.D0.R0.S01: RdPtrOffsetTxDq: 07
N6.C1.D0.R1.S09: RdPtrOffsetTxDq: 07
N0.C1.D0.R1.S15: RdPtrOffsetTxDqs: 07
N2.C2.D0.R1.S07: Total Delay in PI ticks: TxDQ = 936
N4.C2.D0.R0.S02: RdPtrOffsetTxDq: 06
N6.C1.D0.R1.S10: RdPtrOffsetTxDq: 06
N0.C1.D0.R1.S15: PiTxDqs: 02
N2.C2.D0.R1.S08: Total Delay in PI ticks: TxDQ = 906
N4.C2.D0.R0.S03: RdPtrOffsetTxDq: 06
N6.C1.D0.R1.S11: RdPtrOffsetTxDq: 06
N0.C1.D0.R1.S16: wrcmd2dqsstartlatency: 04
N2.C2.D0.R1.S09: Total Delay in PI ticks: TxDQ = 970
N4.C2.D0.R0.S04: RdPtrOffsetTxDq: 05
N6.C1.D0.R1.S12: RdPtrOffsetTxDq: 06
N0.C1.D0.R1.S16: RdPtrOffsetTxDq: 05
N2.C2.D0.R1.S10: Total Delay in PI ticks: TxDQ = 956
N4.C2.D0.R0.S05: RdPtrOffsetTxDq: 06
N6.C1.D0.R1.S13: RdPtrOffsetTxDq: 06
N0.C1.D0.R1.S16: RdPtrOffsetTxDqs: 07
N2.C2.D0.R1.S11: Total Delay in PI ticks: TxDQ = 949
N4.C2.D0.R0.S06: RdPtrOffsetTxDq: 06
N6.C1.D0.R1.S14: RdPtrOffsetTxDq: 06
N0.C1.D0.R1.S16: PiTxDqs: 23
N2.C2.D0.R1.S12: Total Delay in PI ticks: TxDQ = 931
N4.C2.D0.R0.S07: RdPtrOffsetTxDq: 06
N6.C1.D0.R1.S15: RdPtrOffsetTxDq: 06
N0.C1.D0.R1.S17: wrcmd2dqsstartlatency: 04
N2.C2.D0.R1.S13: Total Delay in PI ticks: TxDQ = 890
N4.C2.D0.R0.S08: RdPtrOffsetTxDq: 06
N6.C1.D0.R1.S16: RdPtrOffsetTxDq: 06
N0.C1.D0.R1.S17: RdPtrOffsetTxDq: 05
N2.C2.D0.R1.S14: Total Delay in PI ticks: TxDQ = 917
N4.C2.D0.R0.S09: RdPtrOffsetTxDq: 07
N6.C1.D0.R1.S17: RdPtrOffsetTxDq: 06
N0.C1.D0.R1.S17: RdPtrOffsetTxDqs: 06
N2.C2.D0.R1.S15: Total Delay in PI ticks: TxDQ = 914
N4.C2.D0.R0.S10: RdPtrOffsetTxDq: 07
N6.C1.D0.R1.S00: RdPtrOffsetTxDq: 08
N0.C1.D0.R1.S17: PiTxDqs: 51
N2.C2.D0.R1.S16: Total Delay in PI ticks: TxDQ = 938
N4.C2.D0.R0.S11: RdPtrOffsetTxDq: 06
N6.C1.D0.R1.S01: RdPtrOffsetTxDq: 07
N0.C1.D0.R1.S00: RdPtrOffsetTxDq: 07
N2.C2.D0.R1.S17: Total Delay in PI ticks: TxDQ = 907
N4.C2.D0.R0.S12: RdPtrOffsetTxDq: 06
N6.C1.D0.R1.S02: RdPtrOffsetTxDq: 07
N0.C1.D0.R1.S01: RdPtrOffsetTxDq: 06
N2.C2.D1.R0.S00: wrcmd2dqsstartlatency: 04
N4.C2.D0.R0.S13: RdPtrOffsetTxDq: 06
N6.C1.D0.R1.S03: RdPtrOffsetTxDq: 07
N0.C1.D0.R1.S02: RdPtrOffsetTxDq: 06
N2.C2.D1.R0.S00: RdPtrOffsetTxDq: 06
N4.C2.D0.R0.S14: RdPtrOffsetTxDq: 06
N6.C1.D0.R1.S04: RdPtrOffsetTxDq: 07
N0.C1.D0.R1.S03: RdPtrOffsetTxDq: 06
N2.C2.D1.R0.S00: RdPtrOffsetTxDqs: 07
N4.C2.D0.R0.S15: RdPtrOffsetTxDq: 06
N6.C1.D0.R1.S05: RdPtrOffsetTxDq: 07
N0.C1.D0.R1.S04: RdPtrOffsetTxDq: 06
N2.C2.D1.R0.S00: PiTxDqs: 50
N4.C2.D0.R0.S16: RdPtrOffsetTxDq: 06
N6.C1.D0.R1.S06: RdPtrOffsetTxDq: 07
N0.C1.D0.R1.S05: RdPtrOffsetTxDq: 06
N2.C2.D1.R0.S01: wrcmd2dqsstartlatency: 04
N4.C2.D0.R0.S17: RdPtrOffsetTxDq: 06
N6.C1.D0.R1.S07: RdPtrOffsetTxDq: 07
N0.C1.D0.R1.S06: RdPtrOffsetTxDq: 06
N2.C2.D1.R0.S01: RdPtrOffsetTxDq: 06
N4.C2.D0.R0.S00: RdPtrOffsetTxDq: 08
N6.C1.D0.R1.S08: RdPtrOffsetTxDq: 07
N0.C1.D0.R1.S07: RdPtrOffsetTxDq: 06
N2.C2.D1.R0.S01: RdPtrOffsetTxDqs: 07
N4.C2.D0.R0.S01: RdPtrOffsetTxDq: 08
N6.C1.D0.R1.S09: RdPtrOffsetTxDq: 08
N0.C1.D0.R1.S08: RdPtrOffsetTxDq: 06
N2.C2.D1.R0.S01: PiTxDqs: 39
N4.C2.D0.R0.S02: RdPtrOffsetTxDq: 07
N6.C1.D0.R1.S10: RdPtrOffsetTxDq: 07
N0.C1.D0.R1.S09: RdPtrOffsetTxDq: 07
N2.C2.D1.R0.S02: wrcmd2dqsstartlatency: 04
N4.C2.D0.R0.S03: RdPtrOffsetTxDq: 07
N6.C1.D0.R1.S11: RdPtrOffsetTxDq: 07
N0.C1.D0.R1.S10: RdPtrOffsetTxDq: 06
N2.C2.D1.R0.S02: RdPtrOffsetTxDq: 05
N4.C2.D0.R0.S04: RdPtrOffsetTxDq: 06
N6.C1.D0.R1.S12: RdPtrOffsetTxDq: 07
N0.C1.D0.R1.S11: RdPtrOffsetTxDq: 06
N2.C2.D1.R0.S02: RdPtrOffsetTxDqs: 07
N4.C2.D0.R0.S05: RdPtrOffsetTxDq: 07
N6.C1.D0.R1.S13: RdPtrOffsetTxDq: 07
N0.C1.D0.R1.S12: RdPtrOffsetTxDq: 06
N2.C2.D1.R0.S02: PiTxDqs: 25
N4.C2.D0.R0.S06: RdPtrOffsetTxDq: 07
N6.C1.D0.R1.S14: RdPtrOffsetTxDq: 07
N0.C1.D0.R1.S13: RdPtrOffsetTxDq: 06
N2.C2.D1.R0.S03: wrcmd2dqsstartlatency: 04
N4.C2.D0.R0.S07: RdPtrOffsetTxDq: 07
N6.C1.D0.R1.S15: RdPtrOffsetTxDq: 07
N0.C1.D0.R1.S14: RdPtrOffsetTxDq: 06
N2.C2.D1.R0.S03: RdPtrOffsetTxDq: 05
N4.C2.D0.R0.S08: RdPtrOffsetTxDq: 07
N6.C1.D0.R1.S16: RdPtrOffsetTxDq: 07
N0.C1.D0.R1.S15: RdPtrOffsetTxDq: 06
N2.C2.D1.R0.S03: RdPtrOffsetTxDqs: 07
N4.C2.D0.R0.S09: RdPtrOffsetTxDq: 08
N6.C1.D0.R1.S17: RdPtrOffsetTxDq: 07
N0.C1.D0.R1.S16: RdPtrOffsetTxDq: 06
N2.C2.D1.R0.S03: PiTxDqs: 15
N4.C2.D0.R0.S10: RdPtrOffsetTxDq: 08
N6.C1.D0.R1.S00: Total Delay in PI ticks: TxDQ = 977
N0.C1.D0.R1.S17: RdPtrOffsetTxDq: 06
N2.C2.D1.R0.S04: wrcmd2dqsstartlatency: 04
N4.C2.D0.R0.S11: RdPtrOffsetTxDq: 07
N6.C1.D0.R1.S01: Total Delay in PI ticks: TxDQ = 958
N0.C1.D0.R1.S00: RdPtrOffsetTxDq: 08
N2.C2.D1.R0.S04: RdPtrOffsetTxDq: 04
N4.C2.D0.R0.S12: RdPtrOffsetTxDq: 07
N6.C1.D0.R1.S02: Total Delay in PI ticks: TxDQ = 950
N0.C1.D0.R1.S01: RdPtrOffsetTxDq: 07
N2.C2.D1.R0.S04: RdPtrOffsetTxDqs: 06
N4.C2.D0.R0.S13: RdPtrOffsetTxDq: 07
N6.C1.D0.R1.S03: Total Delay in PI ticks: TxDQ = 933
N0.C1.D0.R1.S02: RdPtrOffsetTxDq: 07
N2.C2.D1.R0.S04: PiTxDqs: 34
N4.C2.D0.R0.S14: RdPtrOffsetTxDq: 07
N6.C1.D0.R1.S04: Total Delay in PI ticks: TxDQ = 903
N0.C1.D0.R1.S03: RdPtrOffsetTxDq: 07
N2.C2.D1.R0.S05: wrcmd2dqsstartlatency: 04
N4.C2.D0.R0.S15: RdPtrOffsetTxDq: 07
N6.C1.D0.R1.S05: Total Delay in PI ticks: TxDQ = 915
N0.C1.D0.R1.S04: RdPtrOffsetTxDq: 07
N2.C2.D1.R0.S05: RdPtrOffsetTxDq: 05
N4.C2.D0.R0.S16: RdPtrOffsetTxDq: 07
N6.C1.D0.R1.S06: Total Delay in PI ticks: TxDQ = 931
N0.C1.D0.R1.S05: RdPtrOffsetTxDq: 07
N2.C2.D1.R0.S05: RdPtrOffsetTxDqs: 07
N4.C2.D0.R0.S17: RdPtrOffsetTxDq: 07
N6.C1.D0.R1.S07: Total Delay in PI ticks: TxDQ = 943
N0.C1.D0.R1.S06: RdPtrOffsetTxDq: 07
N2.C2.D1.R0.S05: PiTxDqs: 00
N4.C2.D0.R0.S00: Total Delay in PI ticks: TxDQ = 978
N6.C1.D0.R1.S08: Total Delay in PI ticks: TxDQ = 917
N0.C1.D0.R1.S07: RdPtrOffsetTxDq: 07
N2.C2.D1.R0.S06: wrcmd2dqsstartlatency: 04
N4.C2.D0.R0.S01: Total Delay in PI ticks: TxDQ = 965
N6.C1.D0.R1.S09: Total Delay in PI ticks: TxDQ = 974
N0.C1.D0.R1.S08: RdPtrOffsetTxDq: 07
N2.C2.D1.R0.S06: RdPtrOffsetTxDq: 05
N4.C2.D0.R0.S02: Total Delay in PI ticks: TxDQ = 954
N6.C1.D0.R1.S10: Total Delay in PI ticks: TxDQ = 958
N0.C1.D0.R1.S09: RdPtrOffsetTxDq: 08
N2.C2.D1.R0.S06: RdPtrOffsetTxDqs: 06
N4.C2.D0.R0.S03: Total Delay in PI ticks: TxDQ = 935
N6.C1.D0.R1.S11: Total Delay in PI ticks: TxDQ = 950
N0.C1.D0.R1.S10: RdPtrOffsetTxDq: 07
N2.C2.D1.R0.S06: PiTxDqs: 60
N4.C2.D0.R0.S04: Total Delay in PI ticks: TxDQ = 896
N6.C1.D0.R1.S12: Total Delay in PI ticks: TxDQ = 934
N0.C1.D0.R1.S11: RdPtrOffsetTxDq: 07
N2.C2.D1.R0.S07: wrcmd2dqsstartlatency: 04
N4.C2.D0.R0.S05: Total Delay in PI ticks: TxDQ = 924
N6.C1.D0.R1.S13: Total Delay in PI ticks: TxDQ = 902
N0.C1.D0.R1.S12: RdPtrOffsetTxDq: 07
N2.C2.D1.R0.S07: RdPtrOffsetTxDq: 05
N4.C2.D0.R0.S06: Total Delay in PI ticks: TxDQ = 926
N6.C1.D0.R1.S14: Total Delay in PI ticks: TxDQ = 914
N0.C1.D0.R1.S13: RdPtrOffsetTxDq: 07
N2.C2.D1.R0.S07: RdPtrOffsetTxDqs: 07
N4.C2.D0.R0.S07: Total Delay in PI ticks: TxDQ = 942
N6.C1.D0.R1.S15: Total Delay in PI ticks: TxDQ = 932
N0.C1.D0.R1.S14: RdPtrOffsetTxDq: 07
N2.C2.D1.R0.S07: PiTxDqs: 19
N4.C2.D0.R0.S08: Total Delay in PI ticks: TxDQ = 917
N6.C1.D0.R1.S16: Total Delay in PI ticks: TxDQ = 946
N0.C1.D0.R1.S15: RdPtrOffsetTxDq: 07
N2.C2.D1.R0.S08: wrcmd2dqsstartlatency: 04
N4.C2.D0.R0.S09: Total Delay in PI ticks: TxDQ = 982
N6.C1.D0.R1.S17: Total Delay in PI ticks: TxDQ = 914
N0.C1.D0.R1.S16: RdPtrOffsetTxDq: 07
N2.C2.D1.R0.S08: RdPtrOffsetTxDq: 05
N4.C2.D0.R0.S10: Total Delay in PI ticks: TxDQ = 966
N6.C1.D1.R0.S00: wrcmd2dqsstartlatency: 04
N0.C1.D0.R1.S17: RdPtrOffsetTxDq: 07
N2.C2.D1.R0.S08: RdPtrOffsetTxDqs: 06
N4.C2.D0.R0.S11: Total Delay in PI ticks: TxDQ = 954
N6.C1.D1.R0.S00: RdPtrOffsetTxDq: 06
N0.C1.D0.R1.S00: Total Delay in PI ticks: TxDQ = 978
N2.C2.D1.R0.S08: PiTxDqs: 49
N4.C2.D0.R0.S12: Total Delay in PI ticks: TxDQ = 937
N6.C1.D1.R0.S00: RdPtrOffsetTxDqs: 07
N0.C1.D0.R1.S01: Total Delay in PI ticks: TxDQ = 959
N2.C2.D1.R0.S09: wrcmd2dqsstartlatency: 04
N4.C2.D0.R0.S13: Total Delay in PI ticks: TxDQ = 897
N6.C1.D1.R0.S00: PiTxDqs: 58
N0.C1.D0.R1.S02: Total Delay in PI ticks: TxDQ = 950
N2.C2.D1.R0.S09: RdPtrOffsetTxDq: 06
N4.C2.D0.R0.S14: Total Delay in PI ticks: TxDQ = 926
N6.C1.D1.R0.S01: wrcmd2dqsstartlatency: 04
N0.C1.D0.R1.S03: Total Delay in PI ticks: TxDQ = 935
N2.C2.D1.R0.S09: RdPtrOffsetTxDqs: 07
N4.C2.D0.R0.S15: Total Delay in PI ticks: TxDQ = 926
N6.C1.D1.R0.S01: RdPtrOffsetTxDq: 06
N0.C1.D0.R1.S04: Total Delay in PI ticks: TxDQ = 900
N2.C2.D1.R0.S09: PiTxDqs: 50
N4.C2.D0.R0.S16: Total Delay in PI ticks: TxDQ = 943
N6.C1.D1.R0.S01: RdPtrOffsetTxDqs: 07
N0.C1.D0.R1.S05: Total Delay in PI ticks: TxDQ = 915
N2.C2.D1.R0.S10: wrcmd2dqsstartlatency: 04
N4.C2.D0.R0.S17: Total Delay in PI ticks: TxDQ = 913
N6.C1.D1.R0.S01: PiTxDqs: 42
N0.C1.D0.R1.S06: Total Delay in PI ticks: TxDQ = 929
N2.C2.D1.R0.S10: RdPtrOffsetTxDq: 06
N4.C2.D0.R1.S00: wrcmd2dqsstartlatency: 04
N6.C1.D1.R0.S02: wrcmd2dqsstartlatency: 04
N0.C1.D0.R1.S07: Total Delay in PI ticks: TxDQ = 946
N2.C2.D1.R0.S10: RdPtrOffsetTxDqs: 07
N4.C2.D0.R1.S00: RdPtrOffsetTxDq: 06
N6.C1.D1.R0.S02: RdPtrOffsetTxDq: 05
N0.C1.D0.R1.S08: Total Delay in PI ticks: TxDQ = 916
N2.C2.D1.R0.S10: PiTxDqs: 39
N4.C2.D0.R1.S00: RdPtrOffsetTxDqs: 07
N6.C1.D1.R0.S02: RdPtrOffsetTxDqs: 07
N0.C1.D0.R1.S09: Total Delay in PI ticks: TxDQ = 975
N2.C2.D1.R0.S11: wrcmd2dqsstartlatency: 04
N4.C2.D0.R1.S00: PiTxDqs: 47
N6.C1.D1.R0.S02: PiTxDqs: 32
N0.C1.D0.R1.S10: Total Delay in PI ticks: TxDQ = 960
N2.C2.D1.R0.S11: RdPtrOffsetTxDq: 05
N4.C2.D0.R1.S01: wrcmd2dqsstartlatency: 04
N6.C1.D1.R0.S03: wrcmd2dqsstartlatency: 04
N0.C1.D0.R1.S11: Total Delay in PI ticks: TxDQ = 950
N2.C2.D1.R0.S11: RdPtrOffsetTxDqs: 07
N4.C2.D0.R1.S01: RdPtrOffsetTxDq: 05
N6.C1.D1.R0.S03: RdPtrOffsetTxDq: 05
N0.C1.D0.R1.S12: Total Delay in PI ticks: TxDQ = 937
N2.C2.D1.R0.S11: PiTxDqs: 26
N4.C2.D0.R1.S01: RdPtrOffsetTxDqs: 07
N6.C1.D1.R0.S03: RdPtrOffsetTxDqs: 07
N0.C1.D0.R1.S13: Total Delay in PI ticks: TxDQ = 901
N2.C2.D1.R0.S12: wrcmd2dqsstartlatency: 04
N4.C2.D0.R1.S01: PiTxDqs: 30
N6.C1.D1.R0.S03: PiTxDqs: 17
N0.C1.D0.R1.S14: Total Delay in PI ticks: TxDQ = 918
N2.C2.D1.R0.S12: RdPtrOffsetTxDq: 05
N4.C2.D0.R1.S02: wrcmd2dqsstartlatency: 04
N6.C1.D1.R0.S04: wrcmd2dqsstartlatency: 04
N0.C1.D0.R1.S15: Total Delay in PI ticks: TxDQ = 931
N2.C2.D1.R0.S12: RdPtrOffsetTxDqs: 07
N4.C2.D0.R1.S02: RdPtrOffsetTxDq: 05
N6.C1.D1.R0.S04: RdPtrOffsetTxDq: 05
N0.C1.D0.R1.S16: Total Delay in PI ticks: TxDQ = 949
N2.C2.D1.R0.S12: PiTxDqs: 15
N4.C2.D0.R1.S02: RdPtrOffsetTxDqs: 07
N6.C1.D1.R0.S04: RdPtrOffsetTxDqs: 06
N0.C1.D0.R1.S17: Total Delay in PI ticks: TxDQ = 916
N2.C2.D1.R0.S13: wrcmd2dqsstartlatency: 04
N4.C2.D0.R1.S02: PiTxDqs: 21
N6.C1.D1.R0.S04: PiTxDqs: 48
N0.C1.D1.R0.S00: wrcmd2dqsstartlatency: 04
N2.C2.D1.R0.S13: RdPtrOffsetTxDq: 05
N4.C2.D0.R1.S03: wrcmd2dqsstartlatency: 04
N6.C1.D1.R0.S05: wrcmd2dqsstartlatency: 04
N0.C1.D1.R0.S00: RdPtrOffsetTxDq: 06
N2.C2.D1.R0.S13: RdPtrOffsetTxDqs: 06
N4.C2.D0.R1.S03: RdPtrOffsetTxDq: 05
N6.C1.D1.R0.S05: RdPtrOffsetTxDq: 05
N0.C1.D1.R0.S00: RdPtrOffsetTxDqs: 07
N2.C2.D1.R0.S13: PiTxDqs: 35
N4.C2.D0.R1.S03: RdPtrOffsetTxDqs: 07
N6.C1.D1.R0.S05: RdPtrOffsetTxDqs: 06
N0.C1.D1.R0.S00: PiTxDqs: 61
N2.C2.D1.R0.S14: wrcmd2dqsstartlatency: 04
N4.C2.D0.R1.S03: PiTxDqs: 06
N6.C1.D1.R0.S05: PiTxDqs: 63
N0.C1.D1.R0.S01: wrcmd2dqsstartlatency: 04
N2.C2.D1.R0.S14: RdPtrOffsetTxDq: 05
N4.C2.D0.R1.S04: wrcmd2dqsstartlatency: 04
N6.C1.D1.R0.S06: wrcmd2dqsstartlatency: 04
N0.C1.D1.R0.S01: RdPtrOffsetTxDq: 06
N2.C2.D1.R0.S14: RdPtrOffsetTxDqs: 06
N4.C2.D0.R1.S04: RdPtrOffsetTxDq: 04
N6.C1.D1.R0.S06: RdPtrOffsetTxDq: 05
N0.C1.D1.R0.S01: RdPtrOffsetTxDqs: 07
N2.C2.D1.R0.S14: PiTxDqs: 63
N4.C2.D0.R1.S04: RdPtrOffsetTxDqs: 06
N6.C1.D1.R0.S06: RdPtrOffsetTxDqs: 07
N0.C1.D1.R0.S01: PiTxDqs: 43
N2.C2.D1.R0.S15: wrcmd2dqsstartlatency: 04
N4.C2.D0.R1.S04: PiTxDqs: 27
N6.C1.D1.R0.S06: PiTxDqs: 11
N0.C1.D1.R0.S02: wrcmd2dqsstartlatency: 04
N2.C2.D1.R0.S15: RdPtrOffsetTxDq: 05
N4.C2.D0.R1.S05: wrcmd2dqsstartlatency: 04
N6.C1.D1.R0.S07: wrcmd2dqsstartlatency: 04
N0.C1.D1.R0.S02: RdPtrOffsetTxDq: 05
N2.C2.D1.R0.S15: RdPtrOffsetTxDqs: 06
N4.C2.D0.R1.S05: RdPtrOffsetTxDq: 05
N6.C1.D1.R0.S07: RdPtrOffsetTxDq: 05
N0.C1.D1.R0.S02: RdPtrOffsetTxDqs: 07
N2.C2.D1.R0.S15: PiTxDqs: 60
N4.C2.D0.R1.S05: RdPtrOffsetTxDqs: 06
N6.C1.D1.R0.S07: RdPtrOffsetTxDqs: 07
N0.C1.D1.R0.S02: PiTxDqs: 35
N2.C2.D1.R0.S16: wrcmd2dqsstartlatency: 04
N4.C2.D0.R1.S05: PiTxDqs: 55
N6.C1.D1.R0.S07: PiTxDqs: 28
N0.C1.D1.R0.S03: wrcmd2dqsstartlatency: 04
N2.C2.D1.R0.S16: RdPtrOffsetTxDq: 05
N4.C2.D0.R1.S06: wrcmd2dqsstartlatency: 04
N6.C1.D1.R0.S08: wrcmd2dqsstartlatency: 04
N0.C1.D1.R0.S03: RdPtrOffsetTxDq: 05
N2.C2.D1.R0.S16: RdPtrOffsetTxDqs: 07
N4.C2.D0.R1.S06: RdPtrOffsetTxDq: 05
N6.C1.D1.R0.S08: RdPtrOffsetTxDq: 05
N0.C1.D1.R0.S03: RdPtrOffsetTxDqs: 07
N2.C2.D1.R0.S16: PiTxDqs: 19
N4.C2.D0.R1.S06: RdPtrOffsetTxDqs: 06
N6.C1.D1.R0.S08: RdPtrOffsetTxDqs: 06
N0.C1.D1.R0.S03: PiTxDqs: 23
N2.C2.D1.R0.S17: wrcmd2dqsstartlatency: 04
N4.C2.D0.R1.S06: PiTxDqs: 52
N6.C1.D1.R0.S08: PiTxDqs: 62
N0.C1.D1.R0.S04: wrcmd2dqsstartlatency: 04
N2.C2.D1.R0.S17: RdPtrOffsetTxDq: 05
N4.C2.D0.R1.S07: wrcmd2dqsstartlatency: 04
N6.C1.D1.R0.S09: wrcmd2dqsstartlatency: 04
N0.C1.D1.R0.S04: RdPtrOffsetTxDq: 05
N2.C2.D1.R0.S17: RdPtrOffsetTxDqs: 06
N4.C2.D0.R1.S07: RdPtrOffsetTxDq: 05
N6.C1.D1.R0.S09: RdPtrOffsetTxDq: 06
N0.C1.D1.R0.S04: RdPtrOffsetTxDqs: 06
N2.C2.D1.R0.S17: PiTxDqs: 49
N4.C2.D0.R1.S07: RdPtrOffsetTxDqs: 07
N6.C1.D1.R0.S09: RdPtrOffsetTxDqs: 07
N0.C1.D1.R0.S04: PiTxDqs: 51
N2.C2.D1.R0.S00: RdPtrOffsetTxDq: 07
N4.C2.D0.R1.S07: PiTxDqs: 11
N6.C1.D1.R0.S09: PiTxDqs: 58
N0.C1.D1.R0.S05: wrcmd2dqsstartlatency: 04
N2.C2.D1.R0.S01: RdPtrOffsetTxDq: 07
N4.C2.D0.R1.S08: wrcmd2dqsstartlatency: 04
N6.C1.D1.R0.S10: wrcmd2dqsstartlatency: 04
N0.C1.D1.R0.S05: RdPtrOffsetTxDq: 05
N2.C2.D1.R0.S02: RdPtrOffsetTxDq: 06
N4.C2.D0.R1.S08: RdPtrOffsetTxDq: 05
N6.C1.D1.R0.S10: RdPtrOffsetTxDq: 06
N0.C1.D1.R0.S05: RdPtrOffsetTxDqs: 07
N2.C2.D1.R0.S03: RdPtrOffsetTxDq: 06
N4.C2.D0.R1.S08: RdPtrOffsetTxDqs: 06
N6.C1.D1.R0.S10: RdPtrOffsetTxDqs: 07
N0.C1.D1.R0.S05: PiTxDqs: 01
N2.C2.D1.R0.S04: RdPtrOffsetTxDq: 05
N4.C2.D0.R1.S08: PiTxDqs: 46
N6.C1.D1.R0.S10: PiTxDqs: 42
N0.C1.D1.R0.S06: wrcmd2dqsstartlatency: 04
N2.C2.D1.R0.S05: RdPtrOffsetTxDq: 06
N4.C2.D0.R1.S09: wrcmd2dqsstartlatency: 04
N6.C1.D1.R0.S11: wrcmd2dqsstartlatency: 04
N0.C1.D1.R0.S06: RdPtrOffsetTxDq: 05
N2.C2.D1.R0.S06: RdPtrOffsetTxDq: 06
N4.C2.D0.R1.S09: RdPtrOffsetTxDq: 06
N6.C1.D1.R0.S11: RdPtrOffsetTxDq: 06
N0.C1.D1.R0.S06: RdPtrOffsetTxDqs: 07
N2.C2.D1.R0.S07: RdPtrOffsetTxDq: 06
N4.C2.D0.R1.S09: RdPtrOffsetTxDqs: 07
N6.C1.D1.R0.S11: RdPtrOffsetTxDqs: 07
N0.C1.D1.R0.S06: PiTxDqs: 18
N2.C2.D1.R0.S08: RdPtrOffsetTxDq: 06
N4.C2.D0.R1.S09: PiTxDqs: 47
N6.C1.D1.R0.S11: PiTxDqs: 33
N0.C1.D1.R0.S07: wrcmd2dqsstartlatency: 04
N2.C2.D1.R0.S09: RdPtrOffsetTxDq: 07
N4.C2.D0.R1.S10: wrcmd2dqsstartlatency: 04
N6.C1.D1.R0.S12: wrcmd2dqsstartlatency: 04
N0.C1.D1.R0.S07: RdPtrOffsetTxDq: 05
N2.C2.D1.R0.S10: RdPtrOffsetTxDq: 07
N4.C2.D0.R1.S10: RdPtrOffsetTxDq: 05
N6.C1.D1.R0.S12: RdPtrOffsetTxDq: 05
N0.C1.D1.R0.S07: RdPtrOffsetTxDqs: 07
N2.C2.D1.R0.S11: RdPtrOffsetTxDq: 06
N4.C2.D0.R1.S10: RdPtrOffsetTxDqs: 07
N6.C1.D1.R0.S12: RdPtrOffsetTxDqs: 07
N0.C1.D1.R0.S07: PiTxDqs: 34
N2.C2.D1.R0.S12: RdPtrOffsetTxDq: 06
N4.C2.D0.R1.S10: PiTxDqs: 33
N6.C1.D1.R0.S12: PiTxDqs: 18
N0.C1.D1.R0.S08: wrcmd2dqsstartlatency: 04
N2.C2.D1.R0.S13: RdPtrOffsetTxDq: 06
N4.C2.D0.R1.S11: wrcmd2dqsstartlatency: 04
N6.C1.D1.R0.S13: wrcmd2dqsstartlatency: 04
N0.C1.D1.R0.S08: RdPtrOffsetTxDq: 05
N2.C2.D1.R0.S14: RdPtrOffsetTxDq: 06
N4.C2.D0.R1.S11: RdPtrOffsetTxDq: 05
N6.C1.D1.R0.S13: RdPtrOffsetTxDq: 05
N0.C1.D1.R0.S08: RdPtrOffsetTxDqs: 07
N2.C2.D1.R0.S15: RdPtrOffsetTxDq: 06
N4.C2.D0.R1.S11: RdPtrOffsetTxDqs: 07
N6.C1.D1.R0.S13: RdPtrOffsetTxDqs: 06
N0.C1.D1.R0.S08: PiTxDqs: 02
N2.C2.D1.R0.S16: RdPtrOffsetTxDq: 06
N4.C2.D0.R1.S11: PiTxDqs: 21
N6.C1.D1.R0.S13: PiTxDqs: 49
N0.C1.D1.R0.S09: wrcmd2dqsstartlatency: 04
N2.C2.D1.R0.S17: RdPtrOffsetTxDq: 06
N4.C2.D0.R1.S12: wrcmd2dqsstartlatency: 04
N6.C1.D1.R0.S14: wrcmd2dqsstartlatency: 04
N0.C1.D1.R0.S09: RdPtrOffsetTxDq: 06
N2.C2.D1.R0.S00: RdPtrOffsetTxDq: 08
N4.C2.D0.R1.S12: RdPtrOffsetTxDq: 05
N6.C1.D1.R0.S14: RdPtrOffsetTxDq: 05
N0.C1.D1.R0.S09: RdPtrOffsetTxDqs: 07
N2.C2.D1.R0.S01: RdPtrOffsetTxDq: 08
N4.C2.D0.R1.S12: RdPtrOffsetTxDqs: 07
N6.C1.D1.R0.S14: RdPtrOffsetTxDqs: 06
N0.C1.D1.R0.S09: PiTxDqs: 62
N2.C2.D1.R0.S02: RdPtrOffsetTxDq: 07
N4.C2.D0.R1.S12: PiTxDqs: 07
N6.C1.D1.R0.S14: PiTxDqs: 61
N0.C1.D1.R0.S10: wrcmd2dqsstartlatency: 04
N2.C2.D1.R0.S03: RdPtrOffsetTxDq: 07
N4.C2.D0.R1.S13: wrcmd2dqsstartlatency: 04
N6.C1.D1.R0.S15: wrcmd2dqsstartlatency: 04
N0.C1.D1.R0.S10: RdPtrOffsetTxDq: 06
N2.C2.D1.R0.S04: RdPtrOffsetTxDq: 06
N4.C2.D0.R1.S13: RdPtrOffsetTxDq: 04
N6.C1.D1.R0.S15: RdPtrOffsetTxDq: 05
N0.C1.D1.R0.S10: RdPtrOffsetTxDqs: 07
N2.C2.D1.R0.S05: RdPtrOffsetTxDq: 07
N4.C2.D0.R1.S13: RdPtrOffsetTxDqs: 06
N6.C1.D1.R0.S15: RdPtrOffsetTxDqs: 07
N0.C1.D1.R0.S10: PiTxDqs: 44
N2.C2.D1.R0.S06: RdPtrOffsetTxDq: 07
N4.C2.D0.R1.S13: PiTxDqs: 28
N6.C1.D1.R0.S15: PiTxDqs: 10
N0.C1.D1.R0.S11: wrcmd2dqsstartlatency: 04
N2.C2.D1.R0.S07: RdPtrOffsetTxDq: 07
N4.C2.D0.R1.S14: wrcmd2dqsstartlatency: 04
N6.C1.D1.R0.S16: wrcmd2dqsstartlatency: 04
N0.C1.D1.R0.S11: RdPtrOffsetTxDq: 06
N2.C2.D1.R0.S08: RdPtrOffsetTxDq: 07
N4.C2.D0.R1.S14: RdPtrOffsetTxDq: 05
N6.C1.D1.R0.S16: RdPtrOffsetTxDq: 05
N0.C1.D1.R0.S11: RdPtrOffsetTxDqs: 07
N2.C2.D1.R0.S09: RdPtrOffsetTxDq: 08
N4.C2.D0.R1.S14: RdPtrOffsetTxDqs: 06
N6.C1.D1.R0.S16: RdPtrOffsetTxDqs: 07
N0.C1.D1.R0.S11: PiTxDqs: 36
N2.C2.D1.R0.S10: RdPtrOffsetTxDq: 08
N4.C2.D0.R1.S14: PiTxDqs: 56
N6.C1.D1.R0.S16: PiTxDqs: 32
N0.C1.D1.R0.S12: wrcmd2dqsstartlatency: 04
N2.C2.D1.R0.S11: RdPtrOffsetTxDq: 07
N4.C2.D0.R1.S15: wrcmd2dqsstartlatency: 04
N6.C1.D1.R0.S17: wrcmd2dqsstartlatency: 04
N0.C1.D1.R0.S12: RdPtrOffsetTxDq: 05
N2.C2.D1.R0.S12: RdPtrOffsetTxDq: 07
N4.C2.D0.R1.S15: RdPtrOffsetTxDq: 05
N6.C1.D1.R0.S17: RdPtrOffsetTxDq: 05
N0.C1.D1.R0.S12: RdPtrOffsetTxDqs: 07
N2.C2.D1.R0.S13: RdPtrOffsetTxDq: 07
N4.C2.D0.R1.S15: RdPtrOffsetTxDqs: 06
N6.C1.D1.R0.S17: RdPtrOffsetTxDqs: 06
N0.C1.D1.R0.S12: PiTxDqs: 23
N2.C2.D1.R0.S14: RdPtrOffsetTxDq: 07
N4.C2.D0.R1.S15: PiTxDqs: 53
N6.C1.D1.R0.S17: PiTxDqs: 61
N0.C1.D1.R0.S13: wrcmd2dqsstartlatency: 04
N2.C2.D1.R0.S15: RdPtrOffsetTxDq: 07
N4.C2.D0.R1.S16: wrcmd2dqsstartlatency: 04
N6.C1.D1.R0.S00: RdPtrOffsetTxDq: 07
N0.C1.D1.R0.S13: RdPtrOffsetTxDq: 05
N2.C2.D1.R0.S16: RdPtrOffsetTxDq: 07
N4.C2.D0.R1.S16: RdPtrOffsetTxDq: 05
N6.C1.D1.R0.S01: RdPtrOffsetTxDq: 07
N0.C1.D1.R0.S13: RdPtrOffsetTxDqs: 06
N2.C2.D1.R0.S17: RdPtrOffsetTxDq: 07
N4.C2.D0.R1.S16: RdPtrOffsetTxDqs: 07
N6.C1.D1.R0.S02: RdPtrOffsetTxDq: 06
N0.C1.D1.R0.S13: PiTxDqs: 51
N2.C2.D1.R0.S00: Total Delay in PI ticks: TxDQ = 979
N4.C2.D0.R1.S16: PiTxDqs: 09
N6.C1.D1.R0.S03: RdPtrOffsetTxDq: 06
N0.C1.D1.R0.S14: wrcmd2dqsstartlatency: 04
N2.C2.D1.R0.S01: Total Delay in PI ticks: TxDQ = 966
N4.C2.D0.R1.S17: wrcmd2dqsstartlatency: 04
N6.C1.D1.R0.S04: RdPtrOffsetTxDq: 06
N0.C1.D1.R0.S14: RdPtrOffsetTxDq: 05
N2.C2.D1.R0.S02: Total Delay in PI ticks: TxDQ = 955
N4.C2.D0.R1.S17: RdPtrOffsetTxDq: 05
N6.C1.D1.R0.S05: RdPtrOffsetTxDq: 06
N0.C1.D1.R0.S14: RdPtrOffsetTxDqs: 07
N2.C2.D1.R0.S03: Total Delay in PI ticks: TxDQ = 941
N4.C2.D0.R1.S17: RdPtrOffsetTxDqs: 06
N6.C1.D1.R0.S06: RdPtrOffsetTxDq: 06
N0.C1.D1.R0.S14: PiTxDqs: 02
N2.C2.D1.R0.S04: Total Delay in PI ticks: TxDQ = 898
N4.C2.D0.R1.S17: PiTxDqs: 45
N6.C1.D1.R0.S07: RdPtrOffsetTxDq: 06
N0.C1.D1.R0.S15: wrcmd2dqsstartlatency: 04
N2.C2.D1.R0.S05: Total Delay in PI ticks: TxDQ = 927
N4.C2.D0.R1.S00: RdPtrOffsetTxDq: 07
N6.C1.D1.R0.S08: RdPtrOffsetTxDq: 06
N0.C1.D1.R0.S15: RdPtrOffsetTxDq: 05
N2.C2.D1.R0.S06: Total Delay in PI ticks: TxDQ = 923
N4.C2.D0.R1.S01: RdPtrOffsetTxDq: 06
N6.C1.D1.R0.S09: RdPtrOffsetTxDq: 07
N0.C1.D1.R0.S15: RdPtrOffsetTxDqs: 07
N2.C2.D1.R0.S07: Total Delay in PI ticks: TxDQ = 946
N4.C2.D0.R1.S02: RdPtrOffsetTxDq: 06
N6.C1.D1.R0.S10: RdPtrOffsetTxDq: 07
N0.C1.D1.R0.S15: PiTxDqs: 16
N2.C2.D1.R0.S08: Total Delay in PI ticks: TxDQ = 911
N4.C2.D0.R1.S03: RdPtrOffsetTxDq: 06
N6.C1.D1.R0.S11: RdPtrOffsetTxDq: 07
N0.C1.D1.R0.S16: wrcmd2dqsstartlatency: 04
N2.C2.D1.R0.S09: Total Delay in PI ticks: TxDQ = 976
N4.C2.D0.R1.S04: RdPtrOffsetTxDq: 05
N6.C1.D1.R0.S12: RdPtrOffsetTxDq: 06
N0.C1.D1.R0.S16: RdPtrOffsetTxDq: 05
N2.C2.D1.R0.S10: Total Delay in PI ticks: TxDQ = 966
N4.C2.D0.R1.S05: RdPtrOffsetTxDq: 06
N6.C1.D1.R0.S13: RdPtrOffsetTxDq: 06
N0.C1.D1.R0.S16: RdPtrOffsetTxDqs: 07
N2.C2.D1.R0.S11: Total Delay in PI ticks: TxDQ = 955
N4.C2.D0.R1.S06: RdPtrOffsetTxDq: 06
N6.C1.D1.R0.S14: RdPtrOffsetTxDq: 06
N0.C1.D1.R0.S16: PiTxDqs: 33
N2.C2.D1.R0.S12: Total Delay in PI ticks: TxDQ = 940
N4.C2.D0.R1.S07: RdPtrOffsetTxDq: 06
N6.C1.D1.R0.S15: RdPtrOffsetTxDq: 06
N0.C1.D1.R0.S17: wrcmd2dqsstartlatency: 04
N2.C2.D1.R0.S13: Total Delay in PI ticks: TxDQ = 898
N4.C2.D0.R1.S08: RdPtrOffsetTxDq: 06
N6.C1.D1.R0.S16: RdPtrOffsetTxDq: 06
N0.C1.D1.R0.S17: RdPtrOffsetTxDq: 05
N2.C2.D1.R0.S14: Total Delay in PI ticks: TxDQ = 927
N4.C2.D0.R1.S09: RdPtrOffsetTxDq: 07
N6.C1.D1.R0.S17: RdPtrOffsetTxDq: 06
N0.C1.D1.R0.S17: RdPtrOffsetTxDqs: 07
N2.C2.D1.R0.S15: Total Delay in PI ticks: TxDQ = 923
N4.C2.D0.R1.S10: RdPtrOffsetTxDq: 06
N6.C1.D1.R0.S00: RdPtrOffsetTxDq: 08
N0.C1.D1.R0.S17: PiTxDqs: 00
N2.C2.D1.R0.S16: Total Delay in PI ticks: TxDQ = 947
N4.C2.D0.R1.S11: RdPtrOffsetTxDq: 06
N6.C1.D1.R0.S01: RdPtrOffsetTxDq: 08
N0.C1.D1.R0.S00: RdPtrOffsetTxDq: 07
N2.C2.D1.R0.S17: Total Delay in PI ticks: TxDQ = 911
N4.C2.D0.R1.S12: RdPtrOffsetTxDq: 06
N6.C1.D1.R0.S02: RdPtrOffsetTxDq: 07
N0.C1.D1.R0.S01: RdPtrOffsetTxDq: 07
N2.C2.D1.R1.S00: wrcmd2dqsstartlatency: 04
N4.C2.D0.R1.S13: RdPtrOffsetTxDq: 05
N6.C1.D1.R0.S03: RdPtrOffsetTxDq: 07
N0.C1.D1.R0.S02: RdPtrOffsetTxDq: 06
N2.C2.D1.R1.S00: RdPtrOffsetTxDq: 06
N4.C2.D0.R1.S14: RdPtrOffsetTxDq: 06
N6.C1.D1.R0.S04: RdPtrOffsetTxDq: 07
N0.C1.D1.R0.S03: RdPtrOffsetTxDq: 06
N2.C2.D1.R1.S00: RdPtrOffsetTxDqs: 07
N4.C2.D0.R1.S15: RdPtrOffsetTxDq: 06
N6.C1.D1.R0.S05: RdPtrOffsetTxDq: 07
N0.C1.D1.R0.S04: RdPtrOffsetTxDq: 06
N2.C2.D1.R1.S00: PiTxDqs: 49
N4.C2.D0.R1.S16: RdPtrOffsetTxDq: 06
N6.C1.D1.R0.S06: RdPtrOffsetTxDq: 07
N0.C1.D1.R0.S05: RdPtrOffsetTxDq: 06
N2.C2.D1.R1.S01: wrcmd2dqsstartlatency: 04
N4.C2.D0.R1.S17: RdPtrOffsetTxDq: 06
N6.C1.D1.R0.S07: RdPtrOffsetTxDq: 07
N0.C1.D1.R0.S06: RdPtrOffsetTxDq: 06
N2.C2.D1.R1.S01: RdPtrOffsetTxDq: 05
N4.C2.D0.R1.S00: RdPtrOffsetTxDq: 08
N6.C1.D1.R0.S08: RdPtrOffsetTxDq: 07
N0.C1.D1.R0.S07: RdPtrOffsetTxDq: 06
N2.C2.D1.R1.S01: RdPtrOffsetTxDqs: 07
N4.C2.D0.R1.S01: RdPtrOffsetTxDq: 07
N6.C1.D1.R0.S09: RdPtrOffsetTxDq: 08
N0.C1.D1.R0.S08: RdPtrOffsetTxDq: 06
N2.C2.D1.R1.S01: PiTxDqs: 33
N4.C2.D0.R1.S02: RdPtrOffsetTxDq: 07
N6.C1.D1.R0.S10: RdPtrOffsetTxDq: 08
N0.C1.D1.R0.S09: RdPtrOffsetTxDq: 07
N2.C2.D1.R1.S02: wrcmd2dqsstartlatency: 04
N4.C2.D0.R1.S03: RdPtrOffsetTxDq: 07
N6.C1.D1.R0.S11: RdPtrOffsetTxDq: 08
N0.C1.D1.R0.S10: RdPtrOffsetTxDq: 07
N2.C2.D1.R1.S02: RdPtrOffsetTxDq: 05
N4.C2.D0.R1.S04: RdPtrOffsetTxDq: 06
N6.C1.D1.R0.S12: RdPtrOffsetTxDq: 07
N0.C1.D1.R0.S11: RdPtrOffsetTxDq: 07
N2.C2.D1.R1.S02: RdPtrOffsetTxDqs: 07
N4.C2.D0.R1.S05: RdPtrOffsetTxDq: 07
N6.C1.D1.R0.S13: RdPtrOffsetTxDq: 07
N0.C1.D1.R0.S12: RdPtrOffsetTxDq: 06
N2.C2.D1.R1.S02: PiTxDqs: 21
N4.C2.D0.R1.S06: RdPtrOffsetTxDq: 07
N6.C1.D1.R0.S14: RdPtrOffsetTxDq: 07
N0.C1.D1.R0.S13: RdPtrOffsetTxDq: 06
N2.C2.D1.R1.S03: wrcmd2dqsstartlatency: 04
N4.C2.D0.R1.S07: RdPtrOffsetTxDq: 07
N6.C1.D1.R0.S15: RdPtrOffsetTxDq: 07
N0.C1.D1.R0.S14: RdPtrOffsetTxDq: 06
N2.C2.D1.R1.S03: RdPtrOffsetTxDq: 05
N4.C2.D0.R1.S08: RdPtrOffsetTxDq: 07
N6.C1.D1.R0.S16: RdPtrOffsetTxDq: 07
N0.C1.D1.R0.S15: RdPtrOffsetTxDq: 06
N2.C2.D1.R1.S03: RdPtrOffsetTxDqs: 07
N4.C2.D0.R1.S09: RdPtrOffsetTxDq: 08
N6.C1.D1.R0.S17: RdPtrOffsetTxDq: 07
N0.C1.D1.R0.S16: RdPtrOffsetTxDq: 06
N2.C2.D1.R1.S03: PiTxDqs: 10
N4.C2.D0.R1.S10: RdPtrOffsetTxDq: 07
N6.C1.D1.R0.S00: Total Delay in PI ticks: TxDQ = 986
N0.C1.D1.R0.S17: RdPtrOffsetTxDq: 06
N2.C2.D1.R1.S04: wrcmd2dqsstartlatency: 04
N4.C2.D0.R1.S11: RdPtrOffsetTxDq: 07
N6.C1.D1.R0.S01: Total Delay in PI ticks: TxDQ = 969
N0.C1.D1.R0.S00: RdPtrOffsetTxDq: 08
N2.C2.D1.R1.S04: RdPtrOffsetTxDq: 04
N4.C2.D0.R1.S12: RdPtrOffsetTxDq: 07
N6.C1.D1.R0.S02: Total Delay in PI ticks: TxDQ = 958
N0.C1.D1.R0.S01: RdPtrOffsetTxDq: 08
N2.C2.D1.R1.S04: RdPtrOffsetTxDqs: 06
N4.C2.D0.R1.S13: RdPtrOffsetTxDq: 06
N6.C1.D1.R0.S03: Total Delay in PI ticks: TxDQ = 945
N0.C1.D1.R0.S02: RdPtrOffsetTxDq: 07
N2.C2.D1.R1.S04: PiTxDqs: 29
N4.C2.D0.R1.S14: RdPtrOffsetTxDq: 07
N6.C1.D1.R0.S04: Total Delay in PI ticks: TxDQ = 910
N0.C1.D1.R0.S03: RdPtrOffsetTxDq: 07
N2.C2.D1.R1.S05: wrcmd2dqsstartlatency: 04
N4.C2.D0.R1.S15: RdPtrOffsetTxDq: 07
N6.C1.D1.R0.S05: Total Delay in PI ticks: TxDQ = 925
N0.C1.D1.R0.S04: RdPtrOffsetTxDq: 07
N2.C2.D1.R1.S05: RdPtrOffsetTxDq: 05
N4.C2.D0.R1.S16: RdPtrOffsetTxDq: 07
N6.C1.D1.R0.S06: Total Delay in PI ticks: TxDQ = 940
N0.C1.D1.R0.S05: RdPtrOffsetTxDq: 07
N2.C2.D1.R1.S05: RdPtrOffsetTxDqs: 06
N4.C2.D0.R1.S17: RdPtrOffsetTxDq: 07
N6.C1.D1.R0.S07: Total Delay in PI ticks: TxDQ = 955
N0.C1.D1.R0.S06: RdPtrOffsetTxDq: 07
N2.C2.D1.R1.S05: PiTxDqs: 62
N4.C2.D0.R1.S00: Total Delay in PI ticks: TxDQ = 974
N6.C1.D1.R0.S08: Total Delay in PI ticks: TxDQ = 926
N0.C1.D1.R0.S07: RdPtrOffsetTxDq: 07
N2.C2.D1.R1.S06: wrcmd2dqsstartlatency: 04
N4.C2.D0.R1.S01: Total Delay in PI ticks: TxDQ = 956
N6.C1.D1.R0.S09: Total Delay in PI ticks: TxDQ = 984
N0.C1.D1.R0.S08: RdPtrOffsetTxDq: 07
N2.C2.D1.R1.S06: RdPtrOffsetTxDq: 05
N4.C2.D0.R1.S02: Total Delay in PI ticks: TxDQ = 948
N6.C1.D1.R0.S10: Total Delay in PI ticks: TxDQ = 970
N0.C1.D1.R0.S09: RdPtrOffsetTxDq: 08
N2.C2.D1.R1.S06: RdPtrOffsetTxDqs: 06
N4.C2.D0.R1.S03: Total Delay in PI ticks: TxDQ = 932
N6.C1.D1.R0.S11: Total Delay in PI ticks: TxDQ = 960
N0.C1.D1.R0.S10: RdPtrOffsetTxDq: 08
N2.C2.D1.R1.S06: PiTxDqs: 54
N4.C2.D0.R1.S04: Total Delay in PI ticks: TxDQ = 892
N6.C1.D1.R0.S12: Total Delay in PI ticks: TxDQ = 946
N0.C1.D1.R0.S11: RdPtrOffsetTxDq: 08
N2.C2.D1.R1.S07: wrcmd2dqsstartlatency: 04
N4.C2.D0.R1.S05: Total Delay in PI ticks: TxDQ = 918
N6.C1.D1.R0.S13: Total Delay in PI ticks: TxDQ = 912
N0.C1.D1.R0.S12: RdPtrOffsetTxDq: 07
N2.C2.D1.R1.S07: RdPtrOffsetTxDq: 05
N4.C2.D0.R1.S06: Total Delay in PI ticks: TxDQ = 915
N6.C1.D1.R0.S14: Total Delay in PI ticks: TxDQ = 924
N0.C1.D1.R0.S13: RdPtrOffsetTxDq: 07
N2.C2.D1.R1.S07: RdPtrOffsetTxDqs: 07
N4.C2.D0.R1.S07: Total Delay in PI ticks: TxDQ = 936
N6.C1.D1.R0.S15: Total Delay in PI ticks: TxDQ = 939
N0.C1.D1.R0.S14: RdPtrOffsetTxDq: 07
N2.C2.D1.R1.S07: PiTxDqs: 17
N4.C2.D0.R1.S08: Total Delay in PI ticks: TxDQ = 907
N6.C1.D1.R0.S16: Total Delay in PI ticks: TxDQ = 959
N0.C1.D1.R0.S15: RdPtrOffsetTxDq: 07
N2.C2.D1.R1.S08: wrcmd2dqsstartlatency: 04
N4.C2.D0.R1.S09: Total Delay in PI ticks: TxDQ = 971
N6.C1.D1.R0.S17: Total Delay in PI ticks: TxDQ = 924
N0.C1.D1.R0.S16: RdPtrOffsetTxDq: 07
N2.C2.D1.R1.S08: RdPtrOffsetTxDq: 05
N4.C2.D0.R1.S10: Total Delay in PI ticks: TxDQ = 958
N6.C1.D1.R1.S00: wrcmd2dqsstartlatency: 04
N0.C1.D1.R0.S17: RdPtrOffsetTxDq: 07
N2.C2.D1.R1.S08: RdPtrOffsetTxDqs: 06
N4.C2.D0.R1.S11: Total Delay in PI ticks: TxDQ = 948
N6.C1.D1.R1.S00: RdPtrOffsetTxDq: 06
N0.C1.D1.R0.S00: Total Delay in PI ticks: TxDQ = 990
N2.C2.D1.R1.S08: PiTxDqs: 45
N4.C2.D0.R1.S12: Total Delay in PI ticks: TxDQ = 934
N6.C1.D1.R1.S00: RdPtrOffsetTxDqs: 07
N0.C1.D1.R0.S01: Total Delay in PI ticks: TxDQ = 970
N2.C2.D1.R1.S09: wrcmd2dqsstartlatency: 04
N4.C2.D0.R1.S13: Total Delay in PI ticks: TxDQ = 891
N6.C1.D1.R1.S00: PiTxDqs: 54
N0.C1.D1.R0.S02: Total Delay in PI ticks: TxDQ = 961
N2.C2.D1.R1.S09: RdPtrOffsetTxDq: 06
N4.C2.D0.R1.S14: Total Delay in PI ticks: TxDQ = 920
N6.C1.D1.R1.S01: wrcmd2dqsstartlatency: 04
N0.C1.D1.R0.S03: Total Delay in PI ticks: TxDQ = 949
N2.C2.D1.R1.S09: RdPtrOffsetTxDqs: 07
N4.C2.D0.R1.S15: Total Delay in PI ticks: TxDQ = 916
N6.C1.D1.R1.S01: RdPtrOffsetTxDq: 06
N0.C1.D1.R0.S04: Total Delay in PI ticks: TxDQ = 914
N2.C2.D1.R1.S09: PiTxDqs: 47
N4.C2.D0.R1.S16: Total Delay in PI ticks: TxDQ = 936
N6.C1.D1.R1.S01: RdPtrOffsetTxDqs: 07
N0.C1.D1.R0.S05: Total Delay in PI ticks: TxDQ = 926
N2.C2.D1.R1.S10: wrcmd2dqsstartlatency: 04
N4.C2.D0.R1.S17: Total Delay in PI ticks: TxDQ = 906
N6.C1.D1.R1.S01: PiTxDqs: 37
N0.C1.D1.R0.S06: Total Delay in PI ticks: TxDQ = 943
N2.C2.D1.R1.S10: RdPtrOffsetTxDq: 05
N4.C2.D1.R0.S00: wrcmd2dqsstartlatency: 04
N6.C1.D1.R1.S02: wrcmd2dqsstartlatency: 04
N0.C1.D1.R0.S07: Total Delay in PI ticks: TxDQ = 959
N2.C2.D1.R1.S10: RdPtrOffsetTxDqs: 07
N4.C2.D1.R0.S00: RdPtrOffsetTxDq: 06
N6.C1.D1.R1.S02: RdPtrOffsetTxDq: 05
N0.C1.D1.R0.S08: Total Delay in PI ticks: TxDQ = 927
N2.C2.D1.R1.S10: PiTxDqs: 34
N4.C2.D1.R0.S00: RdPtrOffsetTxDqs: 07
N6.C1.D1.R1.S02: RdPtrOffsetTxDqs: 07
N0.C1.D1.R0.S09: Total Delay in PI ticks: TxDQ = 987
N2.C2.D1.R1.S11: wrcmd2dqsstartlatency: 04
N4.C2.D1.R0.S00: PiTxDqs: 56
N6.C1.D1.R1.S02: PiTxDqs: 27
N0.C1.D1.R0.S10: Total Delay in PI ticks: TxDQ = 970
N2.C2.D1.R1.S11: RdPtrOffsetTxDq: 05
N4.C2.D1.R0.S01: wrcmd2dqsstartlatency: 04
N6.C1.D1.R1.S03: wrcmd2dqsstartlatency: 04
N0.C1.D1.R0.S11: Total Delay in PI ticks: TxDQ = 963
N2.C2.D1.R1.S11: RdPtrOffsetTxDqs: 07
N4.C2.D1.R0.S01: RdPtrOffsetTxDq: 06
N6.C1.D1.R1.S03: RdPtrOffsetTxDq: 05
N0.C1.D1.R0.S12: Total Delay in PI ticks: TxDQ = 949
N2.C2.D1.R1.S11: PiTxDqs: 24
N4.C2.D1.R0.S01: RdPtrOffsetTxDqs: 07
N6.C1.D1.R1.S03: RdPtrOffsetTxDqs: 07
N0.C1.D1.R0.S13: Total Delay in PI ticks: TxDQ = 913
N2.C2.D1.R1.S12: wrcmd2dqsstartlatency: 04
N4.C2.D1.R0.S01: PiTxDqs: 41
N6.C1.D1.R1.S03: PiTxDqs: 13
N0.C1.D1.R0.S14: Total Delay in PI ticks: TxDQ = 929
N2.C2.D1.R1.S12: RdPtrOffsetTxDq: 05
N4.C2.D1.R0.S02: wrcmd2dqsstartlatency: 04
N6.C1.D1.R1.S04: wrcmd2dqsstartlatency: 04
N0.C1.D1.R0.S15: Total Delay in PI ticks: TxDQ = 943
N2.C2.D1.R1.S12: RdPtrOffsetTxDqs: 07
N4.C2.D1.R0.S02: RdPtrOffsetTxDq: 05
N6.C1.D1.R1.S04: RdPtrOffsetTxDq: 05
N0.C1.D1.R0.S16: Total Delay in PI ticks: TxDQ = 959
N2.C2.D1.R1.S12: PiTxDqs: 09
N4.C2.D1.R0.S02: RdPtrOffsetTxDqs: 07
N6.C1.D1.R1.S04: RdPtrOffsetTxDqs: 06
N0.C1.D1.R0.S17: Total Delay in PI ticks: TxDQ = 926
N2.C2.D1.R1.S13: wrcmd2dqsstartlatency: 04
N4.C2.D1.R0.S02: PiTxDqs: 32
N6.C1.D1.R1.S04: PiTxDqs: 43
N0.C1.D1.R1.S00: wrcmd2dqsstartlatency: 04
N2.C2.D1.R1.S13: RdPtrOffsetTxDq: 04
N4.C2.D1.R0.S03: wrcmd2dqsstartlatency: 04
N6.C1.D1.R1.S05: wrcmd2dqsstartlatency: 04
N0.C1.D1.R1.S00: RdPtrOffsetTxDq: 06
N2.C2.D1.R1.S13: RdPtrOffsetTxDqs: 06
N4.C2.D1.R0.S03: RdPtrOffsetTxDq: 05
N6.C1.D1.R1.S05: RdPtrOffsetTxDq: 05
N0.C1.D1.R1.S00: RdPtrOffsetTxDqs: 07
N2.C2.D1.R1.S13: PiTxDqs: 31
N4.C2.D1.R0.S03: RdPtrOffsetTxDqs: 07
N6.C1.D1.R1.S05: RdPtrOffsetTxDqs: 06
N0.C1.D1.R1.S00: PiTxDqs: 58
N2.C2.D1.R1.S14: wrcmd2dqsstartlatency: 04
N4.C2.D1.R0.S03: PiTxDqs: 16
N6.C1.D1.R1.S05: PiTxDqs: 59
N0.C1.D1.R1.S01: wrcmd2dqsstartlatency: 04
N2.C2.D1.R1.S14: RdPtrOffsetTxDq: 05
N4.C2.D1.R0.S04: wrcmd2dqsstartlatency: 04
N6.C1.D1.R1.S06: wrcmd2dqsstartlatency: 04
N0.C1.D1.R1.S01: RdPtrOffsetTxDq: 06
N2.C2.D1.R1.S14: RdPtrOffsetTxDqs: 06
N4.C2.D1.R0.S04: RdPtrOffsetTxDq: 05
N6.C1.D1.R1.S06: RdPtrOffsetTxDq: 05
N0.C1.D1.R1.S01: RdPtrOffsetTxDqs: 07
N2.C2.D1.R1.S14: PiTxDqs: 61
N4.C2.D1.R0.S04: RdPtrOffsetTxDqs: 06
N6.C1.D1.R1.S06: RdPtrOffsetTxDqs: 07
N0.C1.D1.R1.S01: PiTxDqs: 41
N2.C2.D1.R1.S15: wrcmd2dqsstartlatency: 04
N4.C2.D1.R0.S04: PiTxDqs: 37
N6.C1.D1.R1.S06: PiTxDqs: 05
N0.C1.D1.R1.S02: wrcmd2dqsstartlatency: 04
N2.C2.D1.R1.S15: RdPtrOffsetTxDq: 05
N4.C2.D1.R0.S05: wrcmd2dqsstartlatency: 04
N6.C1.D1.R1.S07: wrcmd2dqsstartlatency: 04
N0.C1.D1.R1.S02: RdPtrOffsetTxDq: 05
N2.C2.D1.R1.S15: RdPtrOffsetTxDqs: 06
N4.C2.D1.R0.S05: RdPtrOffsetTxDq: 05
N6.C1.D1.R1.S07: RdPtrOffsetTxDq: 05
N0.C1.D1.R1.S02: RdPtrOffsetTxDqs: 07
N2.C2.D1.R1.S15: PiTxDqs: 55
N4.C2.D1.R0.S05: RdPtrOffsetTxDqs: 07
N6.C1.D1.R1.S07: RdPtrOffsetTxDqs: 07
N0.C1.D1.R1.S02: PiTxDqs: 33
N2.C2.D1.R1.S16: wrcmd2dqsstartlatency: 04
N4.C2.D1.R0.S05: PiTxDqs: 02
N6.C1.D1.R1.S07: PiTxDqs: 25
N0.C1.D1.R1.S03: wrcmd2dqsstartlatency: 04
N2.C2.D1.R1.S16: RdPtrOffsetTxDq: 05
N4.C2.D1.R0.S06: wrcmd2dqsstartlatency: 04
N6.C1.D1.R1.S08: wrcmd2dqsstartlatency: 04
N0.C1.D1.R1.S03: RdPtrOffsetTxDq: 05
N2.C2.D1.R1.S16: RdPtrOffsetTxDqs: 07
N4.C2.D1.R0.S06: RdPtrOffsetTxDq: 05
N6.C1.D1.R1.S08: RdPtrOffsetTxDq: 05
N0.C1.D1.R1.S03: RdPtrOffsetTxDqs: 07
N2.C2.D1.R1.S16: PiTxDqs: 16
N4.C2.D1.R0.S06: RdPtrOffsetTxDqs: 07
N6.C1.D1.R1.S08: RdPtrOffsetTxDqs: 06
N0.C1.D1.R1.S03: PiTxDqs: 19
N2.C2.D1.R1.S17: wrcmd2dqsstartlatency: 04
N4.C2.D1.R0.S06: PiTxDqs: 01
N6.C1.D1.R1.S08: PiTxDqs: 57
N0.C1.D1.R1.S04: wrcmd2dqsstartlatency: 04
N2.C2.D1.R1.S17: RdPtrOffsetTxDq: 05
N4.C2.D1.R0.S07: wrcmd2dqsstartlatency: 04
N6.C1.D1.R1.S09: wrcmd2dqsstartlatency: 04
N0.C1.D1.R1.S04: RdPtrOffsetTxDq: 05
N2.C2.D1.R1.S17: RdPtrOffsetTxDqs: 06
N4.C2.D1.R0.S07: RdPtrOffsetTxDq: 05
N6.C1.D1.R1.S09: RdPtrOffsetTxDq: 06
N0.C1.D1.R1.S04: RdPtrOffsetTxDqs: 06
N2.C2.D1.R1.S17: PiTxDqs: 44
N4.C2.D1.R0.S07: RdPtrOffsetTxDqs: 07
N6.C1.D1.R1.S09: RdPtrOffsetTxDqs: 07
N0.C1.D1.R1.S04: PiTxDqs: 49
N2.C2.D1.R1.S00: RdPtrOffsetTxDq: 07
N4.C2.D1.R0.S07: PiTxDqs: 19
N6.C1.D1.R1.S09: PiTxDqs: 53
N0.C1.D1.R1.S05: wrcmd2dqsstartlatency: 04
N2.C2.D1.R1.S01: RdPtrOffsetTxDq: 06
N4.C2.D1.R0.S08: wrcmd2dqsstartlatency: 04
N6.C1.D1.R1.S10: wrcmd2dqsstartlatency: 04
N0.C1.D1.R1.S05: RdPtrOffsetTxDq: 05
N2.C2.D1.R1.S02: RdPtrOffsetTxDq: 06
N4.C2.D1.R0.S08: RdPtrOffsetTxDq: 05
N6.C1.D1.R1.S10: RdPtrOffsetTxDq: 06
N0.C1.D1.R1.S05: RdPtrOffsetTxDqs: 06
N2.C2.D1.R1.S03: RdPtrOffsetTxDq: 06
N4.C2.D1.R0.S08: RdPtrOffsetTxDqs: 06
N6.C1.D1.R1.S10: RdPtrOffsetTxDqs: 07
N0.C1.D1.R1.S05: PiTxDqs: 62
N2.C2.D1.R1.S04: RdPtrOffsetTxDq: 05
N4.C2.D1.R0.S08: PiTxDqs: 55
N6.C1.D1.R1.S10: PiTxDqs: 39
N0.C1.D1.R1.S06: wrcmd2dqsstartlatency: 04
N2.C2.D1.R1.S05: RdPtrOffsetTxDq: 06
N4.C2.D1.R0.S09: wrcmd2dqsstartlatency: 04
N6.C1.D1.R1.S11: wrcmd2dqsstartlatency: 04
N0.C1.D1.R1.S06: RdPtrOffsetTxDq: 05
N2.C2.D1.R1.S06: RdPtrOffsetTxDq: 06
N4.C2.D1.R0.S09: RdPtrOffsetTxDq: 06
N6.C1.D1.R1.S11: RdPtrOffsetTxDq: 05
N0.C1.D1.R1.S06: RdPtrOffsetTxDqs: 07
N2.C2.D1.R1.S07: RdPtrOffsetTxDq: 06
N4.C2.D1.R0.S09: RdPtrOffsetTxDqs: 07
N6.C1.D1.R1.S11: RdPtrOffsetTxDqs: 07
N0.C1.D1.R1.S06: PiTxDqs: 10
N2.C2.D1.R1.S08: RdPtrOffsetTxDq: 06
N4.C2.D1.R0.S09: PiTxDqs: 57
N6.C1.D1.R1.S11: PiTxDqs: 30
N0.C1.D1.R1.S07: wrcmd2dqsstartlatency: 04
N2.C2.D1.R1.S09: RdPtrOffsetTxDq: 07
N4.C2.D1.R0.S10: wrcmd2dqsstartlatency: 04
N6.C1.D1.R1.S12: wrcmd2dqsstartlatency: 04
N0.C1.D1.R1.S07: RdPtrOffsetTxDq: 05
N2.C2.D1.R1.S10: RdPtrOffsetTxDq: 06
N4.C2.D1.R0.S10: RdPtrOffsetTxDq: 06
N6.C1.D1.R1.S12: RdPtrOffsetTxDq: 05
N0.C1.D1.R1.S07: RdPtrOffsetTxDqs: 07
N2.C2.D1.R1.S11: RdPtrOffsetTxDq: 06
N4.C2.D1.R0.S10: RdPtrOffsetTxDqs: 07
N6.C1.D1.R1.S12: RdPtrOffsetTxDqs: 07
N0.C1.D1.R1.S07: PiTxDqs: 33
N2.C2.D1.R1.S12: RdPtrOffsetTxDq: 06
N4.C2.D1.R0.S10: PiTxDqs: 43
N6.C1.D1.R1.S12: PiTxDqs: 16
N0.C1.D1.R1.S08: wrcmd2dqsstartlatency: 04
N2.C2.D1.R1.S13: RdPtrOffsetTxDq: 05
N4.C2.D1.R0.S11: wrcmd2dqsstartlatency: 04
N6.C1.D1.R1.S13: wrcmd2dqsstartlatency: 04
N0.C1.D1.R1.S08: RdPtrOffsetTxDq: 05
N2.C2.D1.R1.S14: RdPtrOffsetTxDq: 06
N4.C2.D1.R0.S11: RdPtrOffsetTxDq: 05
N6.C1.D1.R1.S13: RdPtrOffsetTxDq: 05
N0.C1.D1.R1.S08: RdPtrOffsetTxDqs: 06
N2.C2.D1.R1.S15: RdPtrOffsetTxDq: 06
N4.C2.D1.R0.S11: RdPtrOffsetTxDqs: 07
N6.C1.D1.R1.S13: RdPtrOffsetTxDqs: 06
N0.C1.D1.R1.S08: PiTxDqs: 60
N2.C2.D1.R1.S16: RdPtrOffsetTxDq: 06
N4.C2.D1.R0.S11: PiTxDqs: 32
N6.C1.D1.R1.S13: PiTxDqs: 44
N0.C1.D1.R1.S09: wrcmd2dqsstartlatency: 04
N2.C2.D1.R1.S17: RdPtrOffsetTxDq: 06
N4.C2.D1.R0.S12: wrcmd2dqsstartlatency: 04
N6.C1.D1.R1.S14: wrcmd2dqsstartlatency: 04
N0.C1.D1.R1.S09: RdPtrOffsetTxDq: 06
N2.C2.D1.R1.S00: RdPtrOffsetTxDq: 08
N4.C2.D1.R0.S12: RdPtrOffsetTxDq: 05
N6.C1.D1.R1.S14: RdPtrOffsetTxDq: 05
N0.C1.D1.R1.S09: RdPtrOffsetTxDqs: 07
N2.C2.D1.R1.S01: RdPtrOffsetTxDq: 07
N4.C2.D1.R0.S12: RdPtrOffsetTxDqs: 07
N6.C1.D1.R1.S14: RdPtrOffsetTxDqs: 06
N0.C1.D1.R1.S09: PiTxDqs: 58
N2.C2.D1.R1.S02: RdPtrOffsetTxDq: 07
N4.C2.D1.R0.S12: PiTxDqs: 16
N6.C1.D1.R1.S14: PiTxDqs: 59
N0.C1.D1.R1.S10: wrcmd2dqsstartlatency: 04
N2.C2.D1.R1.S03: RdPtrOffsetTxDq: 07
N4.C2.D1.R0.S13: wrcmd2dqsstartlatency: 04
N6.C1.D1.R1.S15: wrcmd2dqsstartlatency: 04
N0.C1.D1.R1.S10: RdPtrOffsetTxDq: 06
N2.C2.D1.R1.S04: RdPtrOffsetTxDq: 06
N4.C2.D1.R0.S13: RdPtrOffsetTxDq: 05
N6.C1.D1.R1.S15: RdPtrOffsetTxDq: 05
N0.C1.D1.R1.S10: RdPtrOffsetTxDqs: 07
N2.C2.D1.R1.S05: RdPtrOffsetTxDq: 07
N4.C2.D1.R0.S13: RdPtrOffsetTxDqs: 06
N6.C1.D1.R1.S15: RdPtrOffsetTxDqs: 07
N0.C1.D1.R1.S10: PiTxDqs: 43
N2.C2.D1.R1.S06: RdPtrOffsetTxDq: 07
N4.C2.D1.R0.S13: PiTxDqs: 38
N6.C1.D1.R1.S15: PiTxDqs: 05
N0.C1.D1.R1.S11: wrcmd2dqsstartlatency: 04
N2.C2.D1.R1.S07: RdPtrOffsetTxDq: 07
N4.C2.D1.R0.S14: wrcmd2dqsstartlatency: 04
N6.C1.D1.R1.S16: wrcmd2dqsstartlatency: 04
N0.C1.D1.R1.S11: RdPtrOffsetTxDq: 06
N2.C2.D1.R1.S08: RdPtrOffsetTxDq: 07
N4.C2.D1.R0.S14: RdPtrOffsetTxDq: 05
N6.C1.D1.R1.S16: RdPtrOffsetTxDq: 05
N0.C1.D1.R1.S11: RdPtrOffsetTxDqs: 07
N2.C2.D1.R1.S09: RdPtrOffsetTxDq: 08
N4.C2.D1.R0.S14: RdPtrOffsetTxDqs: 07
N6.C1.D1.R1.S16: RdPtrOffsetTxDqs: 07
N0.C1.D1.R1.S11: PiTxDqs: 35
N2.C2.D1.R1.S10: RdPtrOffsetTxDq: 07
N4.C2.D1.R0.S14: PiTxDqs: 01
N6.C1.D1.R1.S16: PiTxDqs: 26
N0.C1.D1.R1.S12: wrcmd2dqsstartlatency: 04
N2.C2.D1.R1.S11: RdPtrOffsetTxDq: 07
N4.C2.D1.R0.S15: wrcmd2dqsstartlatency: 04
N6.C1.D1.R1.S17: wrcmd2dqsstartlatency: 04
N0.C1.D1.R1.S12: RdPtrOffsetTxDq: 05
N2.C2.D1.R1.S12: RdPtrOffsetTxDq: 07
N4.C2.D1.R0.S15: RdPtrOffsetTxDq: 05
N6.C1.D1.R1.S17: RdPtrOffsetTxDq: 05
N0.C1.D1.R1.S12: RdPtrOffsetTxDqs: 07
N2.C2.D1.R1.S13: RdPtrOffsetTxDq: 06
N4.C2.D1.R0.S15: RdPtrOffsetTxDqs: 07
N6.C1.D1.R1.S17: RdPtrOffsetTxDqs: 06
N0.C1.D1.R1.S12: PiTxDqs: 20
N2.C2.D1.R1.S14: RdPtrOffsetTxDq: 07
N4.C2.D1.R0.S15: PiTxDqs: 01
N6.C1.D1.R1.S17: PiTxDqs: 57
N0.C1.D1.R1.S13: wrcmd2dqsstartlatency: 04
N2.C2.D1.R1.S15: RdPtrOffsetTxDq: 07
N4.C2.D1.R0.S16: wrcmd2dqsstartlatency: 04
N6.C1.D1.R1.S00: RdPtrOffsetTxDq: 07
N0.C1.D1.R1.S13: RdPtrOffsetTxDq: 05
N2.C2.D1.R1.S16: RdPtrOffsetTxDq: 07
N4.C2.D1.R0.S16: RdPtrOffsetTxDq: 05
N6.C1.D1.R1.S01: RdPtrOffsetTxDq: 07
N0.C1.D1.R1.S13: RdPtrOffsetTxDqs: 06
N2.C2.D1.R1.S17: RdPtrOffsetTxDq: 07
N4.C2.D1.R0.S16: RdPtrOffsetTxDqs: 07
N6.C1.D1.R1.S02: RdPtrOffsetTxDq: 06
N0.C1.D1.R1.S13: PiTxDqs: 49
N2.C2.D1.R1.S00: Total Delay in PI ticks: TxDQ = 977
N4.C2.D1.R0.S16: PiTxDqs: 21
N6.C1.D1.R1.S03: RdPtrOffsetTxDq: 06
N0.C1.D1.R1.S14: wrcmd2dqsstartlatency: 04
N2.C2.D1.R1.S01: Total Delay in PI ticks: TxDQ = 961
N4.C2.D1.R0.S17: wrcmd2dqsstartlatency: 04
N6.C1.D1.R1.S04: RdPtrOffsetTxDq: 06
N0.C1.D1.R1.S14: RdPtrOffsetTxDq: 05
N2.C2.D1.R1.S02: Total Delay in PI ticks: TxDQ = 950
N4.C2.D1.R0.S17: RdPtrOffsetTxDq: 05
N6.C1.D1.R1.S05: RdPtrOffsetTxDq: 06
N0.C1.D1.R1.S14: RdPtrOffsetTxDqs: 07
N2.C2.D1.R1.S03: Total Delay in PI ticks: TxDQ = 937
N4.C2.D1.R0.S17: RdPtrOffsetTxDqs: 06
N6.C1.D1.R1.S06: RdPtrOffsetTxDq: 06
N0.C1.D1.R1.S14: PiTxDqs: 01
N2.C2.D1.R1.S04: Total Delay in PI ticks: TxDQ = 894
N4.C2.D1.R0.S17: PiTxDqs: 54
N6.C1.D1.R1.S07: RdPtrOffsetTxDq: 06
N0.C1.D1.R1.S15: wrcmd2dqsstartlatency: 04
N2.C2.D1.R1.S05: Total Delay in PI ticks: TxDQ = 925
N4.C2.D1.R0.S00: RdPtrOffsetTxDq: 07
N6.C1.D1.R1.S08: RdPtrOffsetTxDq: 06
N0.C1.D1.R1.S15: RdPtrOffsetTxDq: 05
N2.C2.D1.R1.S06: Total Delay in PI ticks: TxDQ = 918
N4.C2.D1.R0.S01: RdPtrOffsetTxDq: 07
N6.C1.D1.R1.S09: RdPtrOffsetTxDq: 07
N0.C1.D1.R1.S15: RdPtrOffsetTxDqs: 07
N2.C2.D1.R1.S07: Total Delay in PI ticks: TxDQ = 943
N4.C2.D1.R0.S02: RdPtrOffsetTxDq: 06
N6.C1.D1.R1.S10: RdPtrOffsetTxDq: 07
N0.C1.D1.R1.S15: PiTxDqs: 12
N2.C2.D1.R1.S08: Total Delay in PI ticks: TxDQ = 908
N4.C2.D1.R0.S03: RdPtrOffsetTxDq: 06
N6.C1.D1.R1.S11: RdPtrOffsetTxDq: 06
N0.C1.D1.R1.S16: wrcmd2dqsstartlatency: 04
N2.C2.D1.R1.S09: Total Delay in PI ticks: TxDQ = 972
N4.C2.D1.R0.S04: RdPtrOffsetTxDq: 06
N6.C1.D1.R1.S12: RdPtrOffsetTxDq: 06
N0.C1.D1.R1.S16: RdPtrOffsetTxDq: 05
N2.C2.D1.R1.S10: Total Delay in PI ticks: TxDQ = 962
N4.C2.D1.R0.S05: RdPtrOffsetTxDq: 06
N6.C1.D1.R1.S13: RdPtrOffsetTxDq: 06
N0.C1.D1.R1.S16: RdPtrOffsetTxDqs: 07
N2.C2.D1.R1.S11: Total Delay in PI ticks: TxDQ = 952
N4.C2.D1.R0.S06: RdPtrOffsetTxDq: 06
N6.C1.D1.R1.S14: RdPtrOffsetTxDq: 06
N0.C1.D1.R1.S16: PiTxDqs: 30
N2.C2.D1.R1.S12: Total Delay in PI ticks: TxDQ = 935
N4.C2.D1.R0.S07: RdPtrOffsetTxDq: 06
N6.C1.D1.R1.S15: RdPtrOffsetTxDq: 06
N0.C1.D1.R1.S17: wrcmd2dqsstartlatency: 04
N2.C2.D1.R1.S13: Total Delay in PI ticks: TxDQ = 896
N4.C2.D1.R0.S08: RdPtrOffsetTxDq: 06
N6.C1.D1.R1.S16: RdPtrOffsetTxDq: 06
N0.C1.D1.R1.S17: RdPtrOffsetTxDq: 05
N2.C2.D1.R1.S14: Total Delay in PI ticks: TxDQ = 924
N4.C2.D1.R0.S09: RdPtrOffsetTxDq: 07
N6.C1.D1.R1.S17: RdPtrOffsetTxDq: 06
N0.C1.D1.R1.S17: RdPtrOffsetTxDqs: 06
N2.C2.D1.R1.S15: Total Delay in PI ticks: TxDQ = 919
N4.C2.D1.R0.S10: RdPtrOffsetTxDq: 07
N6.C1.D1.R1.S00: RdPtrOffsetTxDq: 08
N0.C1.D1.R1.S17: PiTxDqs: 61
N2.C2.D1.R1.S16: Total Delay in PI ticks: TxDQ = 941
N4.C2.D1.R0.S11: RdPtrOffsetTxDq: 06
N6.C1.D1.R1.S01: RdPtrOffsetTxDq: 08
N0.C1.D1.R1.S00: RdPtrOffsetTxDq: 07
N2.C2.D1.R1.S17: Total Delay in PI ticks: TxDQ = 908
N4.C2.D1.R0.S12: RdPtrOffsetTxDq: 06
N6.C1.D1.R1.S02: RdPtrOffsetTxDq: 07
N0.C1.D1.R1.S01: RdPtrOffsetTxDq: 07
N2.C2: Calculating Optimimum DQ/DQS Values
N4.C2.D1.R0.S13: RdPtrOffsetTxDq: 06
N6.C1.D1.R1.S03: RdPtrOffsetTxDq: 07
N0.C1.D1.R1.S02: RdPtrOffsetTxDq: 06
N4.C2.D1.R0.S14: RdPtrOffsetTxDq: 06
N6.C1.D1.R1.S04: RdPtrOffsetTxDq: 07
N0.C1.D1.R1.S03: RdPtrOffsetTxDq: 06
START_DATA_TX_DQ
N4.C2.D1.R0.S15: RdPtrOffsetTxDq: 06
N6.C1.D1.R1.S05: RdPtrOffsetTxDq: 07
N0.C1.D1.R1.S04: RdPtrOffsetTxDq: 06
N2.C2.S00: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 009, RdPtrOffsetTxDqs = 009
N4.C2.D1.R0.S16: RdPtrOffsetTxDq: 06
N6.C1.D1.R1.S06: RdPtrOffsetTxDq: 07
N0.C1.D1.R1.S05: RdPtrOffsetTxDq: 06
N2.C2.S00: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 009, RdPtrOffsetTxDqs = 009
N4.C2.D1.R0.S17: RdPtrOffsetTxDq: 06
N6.C1.D1.R1.S07: RdPtrOffsetTxDq: 07
N0.C1.D1.R1.S06: RdPtrOffsetTxDq: 06
N2.C2.S01: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 009
N4.C2.D1.R0.S00: RdPtrOffsetTxDq: 08
N6.C1.D1.R1.S08: RdPtrOffsetTxDq: 07
N0.C1.D1.R1.S07: RdPtrOffsetTxDq: 06
N2.C2.S01: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 009
N4.C2.D1.R0.S01: RdPtrOffsetTxDq: 08
N6.C1.D1.R1.S09: RdPtrOffsetTxDq: 08
N0.C1.D1.R1.S08: RdPtrOffsetTxDq: 06
N2.C2.S02: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 009
N4.C2.D1.R0.S02: RdPtrOffsetTxDq: 07
N6.C1.D1.R1.S10: RdPtrOffsetTxDq: 08
N0.C1.D1.R1.S09: RdPtrOffsetTxDq: 07
N2.C2.S02: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 009
N4.C2.D1.R0.S03: RdPtrOffsetTxDq: 07
N6.C1.D1.R1.S11: RdPtrOffsetTxDq: 07
N0.C1.D1.R1.S10: RdPtrOffsetTxDq: 07
N2.C2.S03: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 009
N4.C2.D1.R0.S04: RdPtrOffsetTxDq: 07
N6.C1.D1.R1.S12: RdPtrOffsetTxDq: 07
N0.C1.D1.R1.S11: RdPtrOffsetTxDq: 07
N2.C2.S03: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 009
N4.C2.D1.R0.S05: RdPtrOffsetTxDq: 07
N6.C1.D1.R1.S13: RdPtrOffsetTxDq: 07
N0.C1.D1.R1.S12: RdPtrOffsetTxDq: 06
N2.C2.S04: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 007, RdPtrOffsetTxDqs = 008
N4.C2.D1.R0.S06: RdPtrOffsetTxDq: 07
N6.C1.D1.R1.S14: RdPtrOffsetTxDq: 07
N0.C1.D1.R1.S13: RdPtrOffsetTxDq: 06
N2.C2.S04: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 007, RdPtrOffsetTxDqs = 008
N4.C2.D1.R0.S07: RdPtrOffsetTxDq: 07
N6.C1.D1.R1.S15: RdPtrOffsetTxDq: 07
N0.C1.D1.R1.S14: RdPtrOffsetTxDq: 06
N2.C2.S05: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 008
N4.C2.D1.R0.S08: RdPtrOffsetTxDq: 07
N6.C1.D1.R1.S16: RdPtrOffsetTxDq: 07
N0.C1.D1.R1.S15: RdPtrOffsetTxDq: 06
N2.C2.S05: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 008
N4.C2.D1.R0.S09: RdPtrOffsetTxDq: 08
N6.C1.D1.R1.S17: RdPtrOffsetTxDq: 07
N0.C1.D1.R1.S16: RdPtrOffsetTxDq: 06
N2.C2.S06: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 008
N4.C2.D1.R0.S10: RdPtrOffsetTxDq: 08
N6.C1.D1.R1.S00: Total Delay in PI ticks: TxDQ = 983
N0.C1.D1.R1.S17: RdPtrOffsetTxDq: 06
N2.C2.S06: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 008
N4.C2.D1.R0.S11: RdPtrOffsetTxDq: 07
N6.C1.D1.R1.S01: Total Delay in PI ticks: TxDQ = 964
N0.C1.D1.R1.S00: RdPtrOffsetTxDq: 08
N2.C2.S07: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 009
N4.C2.D1.R0.S12: RdPtrOffsetTxDq: 07
N6.C1.D1.R1.S02: Total Delay in PI ticks: TxDQ = 954
N0.C1.D1.R1.S01: RdPtrOffsetTxDq: 08
N2.C2.S07: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 009
N4.C2.D1.R0.S13: RdPtrOffsetTxDq: 07
N6.C1.D1.R1.S03: Total Delay in PI ticks: TxDQ = 940
N0.C1.D1.R1.S02: RdPtrOffsetTxDq: 07
N2.C2.S08: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 008
N4.C2.D1.R0.S14: RdPtrOffsetTxDq: 07
N6.C1.D1.R1.S04: Total Delay in PI ticks: TxDQ = 907
N0.C1.D1.R1.S03: RdPtrOffsetTxDq: 07
N2.C2.S08: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 008
N4.C2.D1.R0.S15: RdPtrOffsetTxDq: 07
N6.C1.D1.R1.S05: Total Delay in PI ticks: TxDQ = 922
N0.C1.D1.R1.S04: RdPtrOffsetTxDq: 07
N2.C2.D0.R0.S00: TxDqs: plus1 = 1, minus1 = 0, PI = 46, DB = 0
N4.C2.D1.R0.S16: RdPtrOffsetTxDq: 07
N6.C1.D1.R1.S06: Total Delay in PI ticks: TxDQ = 934
N0.C1.D1.R1.S05: RdPtrOffsetTxDq: 07
N2.C2.D0.R0.S00: TxDq : plus1 = 1, minus1 = 0, PI = 16, DB = 0
N4.C2.D1.R0.S17: RdPtrOffsetTxDq: 07
N6.C1.D1.R1.S07: Total Delay in PI ticks: TxDQ = 950
N0.C1.D1.R1.S06: RdPtrOffsetTxDq: 07
N2.C2.D0.R0.S01: TxDqs: plus1 = 1, minus1 = 0, PI = 31, DB = 0
N4.C2.D1.R0.S00: Total Delay in PI ticks: TxDQ = 982
N6.C1.D1.R1.S08: Total Delay in PI ticks: TxDQ = 920
N0.C1.D1.R1.S07: RdPtrOffsetTxDq: 07
N2.C2.D0.R0.S01: TxDq : plus1 = 1, minus1 = 0, PI = 63, DB = 1
N4.C2.D1.R0.S01: Total Delay in PI ticks: TxDQ = 967
N6.C1.D1.R1.S09: Total Delay in PI ticks: TxDQ = 980
N0.C1.D1.R1.S08: RdPtrOffsetTxDq: 07
N2.C2.D0.R0.S02: TxDqs: plus1 = 1, minus1 = 0, PI = 20, DB = 0
N4.C2.D1.R0.S02: Total Delay in PI ticks: TxDQ = 958
N6.C1.D1.R1.S10: Total Delay in PI ticks: TxDQ = 967
N0.C1.D1.R1.S09: RdPtrOffsetTxDq: 08
N2.C2.D0.R0.S02: TxDq : plus1 = 1, minus1 = 0, PI = 54, DB = 1
N4.C2.D1.R0.S03: Total Delay in PI ticks: TxDQ = 941
N6.C1.D1.R1.S11: Total Delay in PI ticks: TxDQ = 957
N0.C1.D1.R1.S10: RdPtrOffsetTxDq: 08
N2.C2.D0.R0.S03: TxDqs: plus1 = 1, minus1 = 0, PI = 03, DB = 1
N4.C2.D1.R0.S04: Total Delay in PI ticks: TxDQ = 901
N6.C1.D1.R1.S12: Total Delay in PI ticks: TxDQ = 944
N0.C1.D1.R1.S11: RdPtrOffsetTxDq: 08
N2.C2.D0.R0.S03: TxDq : plus1 = 1, minus1 = 0, PI = 35, DB = 0
N4.C2.D1.R0.S05: Total Delay in PI ticks: TxDQ = 928
N6.C1.D1.R1.S13: Total Delay in PI ticks: TxDQ = 909
N0.C1.D1.R1.S12: RdPtrOffsetTxDq: 07
N2.C2.D0.R0.S04: TxDqs: plus1 = 1, minus1 = 0, PI = 27, DB = 0
N4.C2.D1.R0.S06: Total Delay in PI ticks: TxDQ = 927
N6.C1.D1.R1.S14: Total Delay in PI ticks: TxDQ = 924
N0.C1.D1.R1.S13: RdPtrOffsetTxDq: 07
N2.C2.D0.R0.S04: TxDq : plus1 = 1, minus1 = 0, PI = 61, DB = 1
N4.C2.D1.R0.S07: Total Delay in PI ticks: TxDQ = 944
N6.C1.D1.R1.S15: Total Delay in PI ticks: TxDQ = 934
N0.C1.D1.R1.S14: RdPtrOffsetTxDq: 07
N2.C2.D0.R0.S05: TxDqs: plus1 = 1, minus1 = 0, PI = 57, DB = 1
N4.C2.D1.R0.S08: Total Delay in PI ticks: TxDQ = 917
N6.C1.D1.R1.S16: Total Delay in PI ticks: TxDQ = 953
N0.C1.D1.R1.S15: RdPtrOffsetTxDq: 07
N2.C2.D0.R0.S05: TxDq : plus1 = 1, minus1 = 0, PI = 23, DB = 0
N4.C2.D1.R0.S09: Total Delay in PI ticks: TxDQ = 982
N6.C1.D1.R1.S17: Total Delay in PI ticks: TxDQ = 919
N0.C1.D1.R1.S16: RdPtrOffsetTxDq: 07
N2.C2.D0.R0.S06: TxDqs: plus1 = 1, minus1 = 0, PI = 53, DB = 1
N4.C2.D1.R0.S10: Total Delay in PI ticks: TxDQ = 966
N6.C1: Calculating Optimimum DQ/DQS Values
N0.C1.D1.R1.S17: RdPtrOffsetTxDq: 07
N2.C2.D0.R0.S06: TxDq : plus1 = 1, minus1 = 0, PI = 21, DB = 0
N4.C2.D1.R0.S11: Total Delay in PI ticks: TxDQ = 958
N0.C1.D1.R1.S00: Total Delay in PI ticks: TxDQ = 985
N2.C2.D0.R0.S07: TxDqs: plus1 = 1, minus1 = 0, PI = 11, DB = 1
N4.C2.D1.R0.S12: Total Delay in PI ticks: TxDQ = 942
START_DATA_TX_DQ
N0.C1.D1.R1.S01: Total Delay in PI ticks: TxDQ = 967
N2.C2.D0.R0.S07: TxDq : plus1 = 1, minus1 = 0, PI = 42, DB = 0
N4.C2.D1.R0.S13: Total Delay in PI ticks: TxDQ = 900
N6.C1.S00: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 009, RdPtrOffsetTxDqs = 009
N0.C1.D1.R1.S02: Total Delay in PI ticks: TxDQ = 958
N2.C2.D0.R0.S08: TxDqs: plus1 = 1, minus1 = 0, PI = 47, DB = 0
N4.C2.D1.R0.S14: Total Delay in PI ticks: TxDQ = 928
N6.C1.S00: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 009, RdPtrOffsetTxDqs = 009
N0.C1.D1.R1.S03: Total Delay in PI ticks: TxDQ = 945
N2.C2.D0.R0.S08: TxDq : plus1 = 1, minus1 = 0, PI = 15, DB = 1
N4.C2.D1.R0.S15: Total Delay in PI ticks: TxDQ = 927
N6.C1.S01: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 009, RdPtrOffsetTxDqs = 009
N0.C1.D1.R1.S04: Total Delay in PI ticks: TxDQ = 911
N2.C2.D0.R0.S09: TxDqs: plus1 = 1, minus1 = 0, PI = 47, DB = 0
N4.C2.D1.R0.S16: Total Delay in PI ticks: TxDQ = 946
N6.C1.S01: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 009, RdPtrOffsetTxDqs = 009
N0.C1.D1.R1.S05: Total Delay in PI ticks: TxDQ = 923
N2.C2.D0.R0.S09: TxDq : plus1 = 1, minus1 = 0, PI = 14, DB = 1
N4.C2.D1.R0.S17: Total Delay in PI ticks: TxDQ = 916
N6.C1.S02: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 009
N0.C1.D1.R1.S06: Total Delay in PI ticks: TxDQ = 936
N2.C2.D0.R0.S10: TxDqs: plus1 = 1, minus1 = 0, PI = 31, DB = 0
N4.C2.D1.R1.S00: wrcmd2dqsstartlatency: 04
N6.C1.S02: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 009
N0.C1.D1.R1.S07: Total Delay in PI ticks: TxDQ = 959
N2.C2.D0.R0.S10: TxDq : plus1 = 1, minus1 = 0, PI = 63, DB = 1
N4.C2.D1.R1.S00: RdPtrOffsetTxDq: 06
N6.C1.S03: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 009
N0.C1.D1.R1.S08: Total Delay in PI ticks: TxDQ = 921
N2.C2.D0.R0.S11: TxDqs: plus1 = 1, minus1 = 0, PI = 21, DB = 0
N4.C2.D1.R1.S00: RdPtrOffsetTxDqs: 07
N6.C1.S03: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 009
N0.C1.D1.R1.S09: Total Delay in PI ticks: TxDQ = 983
N2.C2.D0.R0.S11: TxDq : plus1 = 1, minus1 = 0, PI = 55, DB = 1
N4.C2.D1.R1.S00: PiTxDqs: 51
N6.C1.S04: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 008
N0.C1.D1.R1.S10: Total Delay in PI ticks: TxDQ = 969
N2.C2.D0.R0.S12: TxDqs: plus1 = 1, minus1 = 0, PI = 05, DB = 1
N4.C2.D1.R1.S01: wrcmd2dqsstartlatency: 04
N6.C1.S04: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 008
N0.C1.D1.R1.S11: Total Delay in PI ticks: TxDQ = 962
N2.C2.D0.R0.S12: TxDq : plus1 = 1, minus1 = 0, PI = 36, DB = 0
N4.C2.D1.R1.S01: RdPtrOffsetTxDq: 05
N6.C1.S05: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 008
N0.C1.D1.R1.S12: Total Delay in PI ticks: TxDQ = 947
N2.C2.D0.R0.S13: TxDqs: plus1 = 1, minus1 = 0, PI = 28, DB = 0
N4.C2.D1.R1.S01: RdPtrOffsetTxDqs: 07
N6.C1.S05: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 008
N0.C1.D1.R1.S13: Total Delay in PI ticks: TxDQ = 911
N2.C2.D0.R0.S13: TxDq : plus1 = 1, minus1 = 0, PI = 61, DB = 1
N4.C2.D1.R1.S01: PiTxDqs: 38
N6.C1.S06: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 009
N0.C1.D1.R1.S14: Total Delay in PI ticks: TxDQ = 927
N2.C2.D0.R0.S14: TxDqs: plus1 = 1, minus1 = 0, PI = 56, DB = 1
N4.C2.D1.R1.S02: wrcmd2dqsstartlatency: 04
N6.C1.S06: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 009
N0.C1.D1.R1.S15: Total Delay in PI ticks: TxDQ = 939
N2.C2.D0.R0.S14: TxDq : plus1 = 1, minus1 = 0, PI = 23, DB = 0
N4.C2.D1.R1.S02: RdPtrOffsetTxDq: 05
N6.C1.S07: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 009
N0.C1.D1.R1.S16: Total Delay in PI ticks: TxDQ = 956
N2.C2.D0.R0.S15: TxDqs: plus1 = 1, minus1 = 0, PI = 53, DB = 1
N4.C2.D1.R1.S02: RdPtrOffsetTxDqs: 07
N6.C1.S07: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 009
N0.C1.D1.R1.S17: Total Delay in PI ticks: TxDQ = 922
N2.C2.D0.R0.S15: TxDq : plus1 = 1, minus1 = 0, PI = 21, DB = 0
N4.C2.D1.R1.S02: PiTxDqs: 28
N6.C1.S08: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 008
N0.C1: Calculating Optimimum DQ/DQS Values
N2.C2.D0.R0.S16: TxDqs: plus1 = 1, minus1 = 0, PI = 13, DB = 1
N4.C2.D1.R1.S03: wrcmd2dqsstartlatency: 04
N6.C1.S08: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 008
N2.C2.D0.R0.S16: TxDq : plus1 = 1, minus1 = 0, PI = 44, DB = 0
N4.C2.D1.R1.S03: RdPtrOffsetTxDq: 05
N6.C1.D0.R0.S00: TxDqs: plus1 = 1, minus1 = 0, PI = 51, DB = 1
START_DATA_TX_DQ
N2.C2.D0.R0.S17: TxDqs: plus1 = 1, minus1 = 0, PI = 46, DB = 0
N4.C2.D1.R1.S03: RdPtrOffsetTxDqs: 07
N6.C1.D0.R0.S00: TxDq : plus1 = 1, minus1 = 0, PI = 19, DB = 0
N0.C1.S00: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 009, RdPtrOffsetTxDqs = 009
N2.C2.D0.R0.S17: TxDq : plus1 = 1, minus1 = 0, PI = 15, DB = 1
N4.C2.D1.R1.S03: PiTxDqs: 14
N6.C1.D0.R0.S01: TxDqs: plus1 = 1, minus1 = 0, PI = 34, DB = 0
N0.C1.S00: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 009, RdPtrOffsetTxDqs = 009
N2.C2.D0.R1.S00: TxDqs: plus1 = 1, minus1 = 0, PI = 46, DB = 0
N4.C2.D1.R1.S04: wrcmd2dqsstartlatency: 04
N6.C1.D0.R0.S01: TxDq : plus1 = 1, minus1 = 0, PI = 01, DB = 1
N0.C1.S01: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 009, RdPtrOffsetTxDqs = 009
N2.C2.D0.R1.S00: TxDq : plus1 = 1, minus1 = 0, PI = 16, DB = 0
N4.C2.D1.R1.S04: RdPtrOffsetTxDq: 04
N6.C1.D0.R0.S02: TxDqs: plus1 = 1, minus1 = 0, PI = 25, DB = 0
N0.C1.S01: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 009, RdPtrOffsetTxDqs = 009
N2.C2.D0.R1.S01: TxDqs: plus1 = 1, minus1 = 0, PI = 31, DB = 0
N4.C2.D1.R1.S04: RdPtrOffsetTxDqs: 06
N6.C1.D0.R0.S02: TxDq : plus1 = 1, minus1 = 0, PI = 57, DB = 1
N0.C1.S02: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 009
N2.C2.D0.R1.S01: TxDq : plus1 = 1, minus1 = 0, PI = 63, DB = 1
N4.C2.D1.R1.S04: PiTxDqs: 35
N6.C1.D0.R0.S03: TxDqs: plus1 = 1, minus1 = 0, PI = 08, DB = 1
N0.C1.S02: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 009
N2.C2.D0.R1.S02: TxDqs: plus1 = 1, minus1 = 0, PI = 20, DB = 0
N4.C2.D1.R1.S05: wrcmd2dqsstartlatency: 04
N6.C1.D0.R0.S03: TxDq : plus1 = 1, minus1 = 0, PI = 41, DB = 0
N0.C1.S03: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 009
N2.C2.D0.R1.S02: TxDq : plus1 = 1, minus1 = 0, PI = 54, DB = 1
N4.C2.D1.R1.S05: RdPtrOffsetTxDq: 05
N6.C1.D0.R0.S04: TxDqs: plus1 = 1, minus1 = 0, PI = 41, DB = 0
N0.C1.S03: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 009
N2.C2.D0.R1.S03: TxDqs: plus1 = 1, minus1 = 0, PI = 03, DB = 1
N4.C2.D1.R1.S05: RdPtrOffsetTxDqs: 07
N6.C1.D0.R0.S04: TxDq : plus1 = 1, minus1 = 0, PI = 09, DB = 1
N0.C1.S04: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 008
N2.C2.D0.R1.S03: TxDq : plus1 = 1, minus1 = 0, PI = 35, DB = 0
N4.C2.D1.R1.S05: PiTxDqs: 00
N6.C1.D0.R0.S05: TxDqs: plus1 = 1, minus1 = 0, PI = 54, DB = 1
N0.C1.S04: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 008
N2.C2.D0.R1.S04: TxDqs: plus1 = 1, minus1 = 0, PI = 27, DB = 0
N4.C2.D1.R1.S06: wrcmd2dqsstartlatency: 04
N6.C1.D0.R0.S05: TxDq : plus1 = 1, minus1 = 0, PI = 21, DB = 0
N0.C1.S05: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 008
N2.C2.D0.R1.S04: TxDq : plus1 = 1, minus1 = 0, PI = 61, DB = 1
N4.C2.D1.R1.S06: RdPtrOffsetTxDq: 05
N6.C1.D0.R0.S06: TxDqs: plus1 = 1, minus1 = 0, PI = 05, DB = 1
N0.C1.S05: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 008
N2.C2.D0.R1.S05: TxDqs: plus1 = 1, minus1 = 0, PI = 57, DB = 1
N4.C2.D1.R1.S06: RdPtrOffsetTxDqs: 06
N6.C1.D0.R0.S06: TxDq : plus1 = 1, minus1 = 0, PI = 39, DB = 0
N0.C1.S06: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 009
N2.C2.D0.R1.S05: TxDq : plus1 = 1, minus1 = 0, PI = 23, DB = 0
N4.C2.D1.R1.S06: PiTxDqs: 59
N6.C1.D0.R0.S07: TxDqs: plus1 = 1, minus1 = 0, PI = 21, DB = 0
N0.C1.S06: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 009
N2.C2.D0.R1.S06: TxDqs: plus1 = 1, minus1 = 0, PI = 53, DB = 1
N4.C2.D1.R1.S07: wrcmd2dqsstartlatency: 04
N6.C1.D0.R0.S07: TxDq : plus1 = 1, minus1 = 0, PI = 51, DB = 1
N0.C1.S07: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 009
N2.C2.D0.R1.S06: TxDq : plus1 = 1, minus1 = 0, PI = 21, DB = 0
N4.C2.D1.R1.S07: RdPtrOffsetTxDq: 05
N6.C1.D0.R0.S08: TxDqs: plus1 = 1, minus1 = 0, PI = 55, DB = 1
N0.C1.S07: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 009
N2.C2.D0.R1.S07: TxDqs: plus1 = 1, minus1 = 0, PI = 11, DB = 1
N4.C2.D1.R1.S07: RdPtrOffsetTxDqs: 07
N6.C1.D0.R0.S08: TxDq : plus1 = 1, minus1 = 0, PI = 25, DB = 0
N0.C1.S08: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 008
N2.C2.D0.R1.S07: TxDq : plus1 = 1, minus1 = 0, PI = 42, DB = 0
N4.C2.D1.R1.S07: PiTxDqs: 17
N6.C1.D0.R0.S09: TxDqs: plus1 = 1, minus1 = 0, PI = 51, DB = 1
N0.C1.S08: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 008
N2.C2.D0.R1.S08: TxDqs: plus1 = 1, minus1 = 0, PI = 47, DB = 0
N4.C2.D1.R1.S08: wrcmd2dqsstartlatency: 04
N6.C1.D0.R0.S09: TxDq : plus1 = 1, minus1 = 0, PI = 18, DB = 0
N0.C1.D0.R0.S00: TxDqs: plus1 = 1, minus1 = 0, PI = 54, DB = 1
N2.C2.D0.R1.S08: TxDq : plus1 = 1, minus1 = 0, PI = 15, DB = 1
N4.C2.D1.R1.S08: RdPtrOffsetTxDq: 05
N6.C1.D0.R0.S10: TxDqs: plus1 = 1, minus1 = 0, PI = 34, DB = 0
N0.C1.D0.R0.S00: TxDq : plus1 = 1, minus1 = 0, PI = 22, DB = 0
N2.C2.D0.R1.S09: TxDqs: plus1 = 1, minus1 = 0, PI = 47, DB = 0
N4.C2.D1.R1.S08: RdPtrOffsetTxDqs: 06
N6.C1.D0.R0.S10: TxDq : plus1 = 1, minus1 = 0, PI = 02, DB = 1
N0.C1.D0.R0.S01: TxDqs: plus1 = 1, minus1 = 0, PI = 35, DB = 0
N2.C2.D0.R1.S09: TxDq : plus1 = 1, minus1 = 0, PI = 14, DB = 1
N4.C2.D1.R1.S08: PiTxDqs: 50
N6.C1.D0.R0.S11: TxDqs: plus1 = 1, minus1 = 0, PI = 26, DB = 0
N0.C1.D0.R0.S01: TxDq : plus1 = 1, minus1 = 0, PI = 02, DB = 1
N2.C2.D0.R1.S10: TxDqs: plus1 = 1, minus1 = 0, PI = 31, DB = 0
N4.C2.D1.R1.S09: wrcmd2dqsstartlatency: 04
N6.C1.D0.R0.S11: TxDq : plus1 = 1, minus1 = 0, PI = 57, DB = 1
N0.C1.D0.R0.S02: TxDqs: plus1 = 1, minus1 = 0, PI = 29, DB = 0
N2.C2.D0.R1.S10: TxDq : plus1 = 1, minus1 = 0, PI = 63, DB = 1
N4.C2.D1.R1.S09: RdPtrOffsetTxDq: 06
N6.C1.D0.R0.S12: TxDqs: plus1 = 1, minus1 = 0, PI = 09, DB = 1
N0.C1.D0.R0.S02: TxDq : plus1 = 1, minus1 = 0, PI = 58, DB = 1
N2.C2.D0.R1.S11: TxDqs: plus1 = 1, minus1 = 0, PI = 21, DB = 0
N4.C2.D1.R1.S09: RdPtrOffsetTxDqs: 07
N6.C1.D0.R0.S12: TxDq : plus1 = 1, minus1 = 0, PI = 42, DB = 0
N0.C1.D0.R0.S03: TxDqs: plus1 = 1, minus1 = 0, PI = 10, DB = 1
N2.C2.D0.R1.S11: TxDq : plus1 = 1, minus1 = 0, PI = 55, DB = 1
N4.C2.D1.R1.S09: PiTxDqs: 51
N6.C1.D0.R0.S13: TxDqs: plus1 = 1, minus1 = 0, PI = 39, DB = 0
N0.C1.D0.R0.S03: TxDq : plus1 = 1, minus1 = 0, PI = 41, DB = 0
N2.C2.D0.R1.S12: TxDqs: plus1 = 1, minus1 = 0, PI = 05, DB = 1
N4.C2.D1.R1.S10: wrcmd2dqsstartlatency: 04
N6.C1.D0.R0.S13: TxDq : plus1 = 1, minus1 = 0, PI = 09, DB = 1
N0.C1.D0.R0.S04: TxDqs: plus1 = 1, minus1 = 0, PI = 39, DB = 0
N2.C2.D0.R1.S12: TxDq : plus1 = 1, minus1 = 0, PI = 36, DB = 0
N4.C2.D1.R1.S10: RdPtrOffsetTxDq: 06
N6.C1.D0.R0.S14: TxDqs: plus1 = 1, minus1 = 0, PI = 52, DB = 1
N0.C1.D0.R0.S04: TxDq : plus1 = 1, minus1 = 0, PI = 06, DB = 1
N2.C2.D0.R1.S13: TxDqs: plus1 = 1, minus1 = 0, PI = 28, DB = 0
N4.C2.D1.R1.S10: RdPtrOffsetTxDqs: 07
N6.C1.D0.R0.S14: TxDq : plus1 = 1, minus1 = 0, PI = 21, DB = 0
N0.C1.D0.R0.S05: TxDqs: plus1 = 1, minus1 = 0, PI = 56, DB = 1
N2.C2.D0.R1.S13: TxDq : plus1 = 1, minus1 = 0, PI = 61, DB = 1
N4.C2.D1.R1.S10: PiTxDqs: 41
N6.C1.D0.R0.S15: TxDqs: plus1 = 1, minus1 = 0, PI = 04, DB = 1
N0.C1.D0.R0.S05: TxDq : plus1 = 1, minus1 = 0, PI = 22, DB = 0
N2.C2.D0.R1.S14: TxDqs: plus1 = 1, minus1 = 0, PI = 56, DB = 1
N4.C2.D1.R1.S11: wrcmd2dqsstartlatency: 04
N6.C1.D0.R0.S15: TxDq : plus1 = 1, minus1 = 0, PI = 39, DB = 0
N0.C1.D0.R0.S06: TxDqs: plus1 = 1, minus1 = 0, PI = 06, DB = 1
N2.C2.D0.R1.S14: TxDq : plus1 = 1, minus1 = 0, PI = 23, DB = 0
N4.C2.D1.R1.S11: RdPtrOffsetTxDq: 05
N6.C1.D0.R0.S16: TxDqs: plus1 = 1, minus1 = 0, PI = 21, DB = 0
N0.C1.D0.R0.S06: TxDq : plus1 = 1, minus1 = 0, PI = 38, DB = 0
N2.C2.D0.R1.S15: TxDqs: plus1 = 1, minus1 = 0, PI = 53, DB = 1
N4.C2.D1.R1.S11: RdPtrOffsetTxDqs: 07
N6.C1.D0.R0.S16: TxDq : plus1 = 1, minus1 = 0, PI = 53, DB = 1
N0.C1.D0.R0.S07: TxDqs: plus1 = 1, minus1 = 0, PI = 23, DB = 0
N2.C2.D0.R1.S15: TxDq : plus1 = 1, minus1 = 0, PI = 21, DB = 0
N4.C2.D1.R1.S11: PiTxDqs: 28
N6.C1.D0.R0.S17: TxDqs: plus1 = 1, minus1 = 0, PI = 54, DB = 1
N0.C1.D0.R0.S07: TxDq : plus1 = 1, minus1 = 0, PI = 54, DB = 1
N2.C2.D0.R1.S16: TxDqs: plus1 = 1, minus1 = 0, PI = 13, DB = 1
N4.C2.D1.R1.S12: wrcmd2dqsstartlatency: 04
N6.C1.D0.R0.S17: TxDq : plus1 = 1, minus1 = 0, PI = 23, DB = 0
N0.C1.D0.R0.S08: TxDqs: plus1 = 1, minus1 = 0, PI = 55, DB = 1
N2.C2.D0.R1.S16: TxDq : plus1 = 1, minus1 = 0, PI = 44, DB = 0
N4.C2.D1.R1.S12: RdPtrOffsetTxDq: 05
N6.C1.D0.R1.S00: TxDqs: plus1 = 1, minus1 = 0, PI = 51, DB = 1
N0.C1.D0.R0.S08: TxDq : plus1 = 1, minus1 = 0, PI = 22, DB = 0
N2.C2.D0.R1.S17: TxDqs: plus1 = 1, minus1 = 0, PI = 46, DB = 0
N4.C2.D1.R1.S12: RdPtrOffsetTxDqs: 07
N6.C1.D0.R1.S00: TxDq : plus1 = 1, minus1 = 0, PI = 19, DB = 0
N0.C1.D0.R0.S09: TxDqs: plus1 = 1, minus1 = 0, PI = 53, DB = 1
N2.C2.D0.R1.S17: TxDq : plus1 = 1, minus1 = 0, PI = 15, DB = 1
N4.C2.D1.R1.S12: PiTxDqs: 14
N6.C1.D0.R1.S01: TxDqs: plus1 = 1, minus1 = 0, PI = 34, DB = 0
N0.C1.D0.R0.S09: TxDq : plus1 = 1, minus1 = 0, PI = 20, DB = 0
N2.C2.D1.R0.S00: TxDqs: plus1 = 1, minus1 = 0, PI = 49, DB = 1
N4.C2.D1.R1.S13: wrcmd2dqsstartlatency: 04
N6.C1.D0.R1.S01: TxDq : plus1 = 1, minus1 = 0, PI = 01, DB = 1
N0.C1.D0.R0.S10: TxDqs: plus1 = 1, minus1 = 0, PI = 36, DB = 0
N2.C2.D1.R0.S00: TxDq : plus1 = 1, minus1 = 0, PI = 18, DB = 0
N4.C2.D1.R1.S13: RdPtrOffsetTxDq: 04
N6.C1.D0.R1.S02: TxDqs: plus1 = 1, minus1 = 0, PI = 25, DB = 0
N0.C1.D0.R0.S10: TxDq : plus1 = 1, minus1 = 0, PI = 03, DB = 1
N2.C2.D1.R0.S01: TxDqs: plus1 = 1, minus1 = 0, PI = 36, DB = 0
N4.C2.D1.R1.S13: RdPtrOffsetTxDqs: 06
N6.C1.D0.R1.S02: TxDq : plus1 = 1, minus1 = 0, PI = 57, DB = 1
N0.C1.D0.R0.S11: TxDqs: plus1 = 1, minus1 = 0, PI = 28, DB = 0
N2.C2.D1.R0.S01: TxDq : plus1 = 0, minus1 = 1, PI = 03, DB = 1
N4.C2.D1.R1.S13: PiTxDqs: 35
N6.C1.D0.R1.S03: TxDqs: plus1 = 1, minus1 = 0, PI = 08, DB = 1
N0.C1.D0.R0.S11: TxDq : plus1 = 1, minus1 = 0, PI = 60, DB = 1
N2.C2.D1.R0.S02: TxDqs: plus1 = 1, minus1 = 0, PI = 23, DB = 0
N4.C2.D1.R1.S14: wrcmd2dqsstartlatency: 04
N6.C1.D0.R1.S03: TxDq : plus1 = 1, minus1 = 0, PI = 41, DB = 0
N0.C1.D0.R0.S12: TxDqs: plus1 = 1, minus1 = 0, PI = 12, DB = 1
N2.C2.D1.R0.S02: TxDq : plus1 = 1, minus1 = 0, PI = 56, DB = 1
N4.C2.D1.R1.S14: RdPtrOffsetTxDq: 05
N6.C1.D0.R1.S04: TxDqs: plus1 = 1, minus1 = 0, PI = 41, DB = 0
N0.C1.D0.R0.S12: TxDq : plus1 = 1, minus1 = 0, PI = 43, DB = 0
N2.C2.D1.R0.S03: TxDqs: plus1 = 1, minus1 = 0, PI = 12, DB = 1
N4.C2.D1.R1.S14: RdPtrOffsetTxDqs: 07
N6.C1.D0.R1.S04: TxDq : plus1 = 1, minus1 = 0, PI = 09, DB = 1
N0.C1.D0.R0.S13: TxDqs: plus1 = 1, minus1 = 0, PI = 41, DB = 0
N2.C2.D1.R0.S03: TxDq : plus1 = 1, minus1 = 0, PI = 43, DB = 0
N4.C2.D1.R1.S14: PiTxDqs: 00
N6.C1.D0.R1.S05: TxDqs: plus1 = 1, minus1 = 0, PI = 54, DB = 1
N0.C1.D0.R0.S13: TxDq : plus1 = 1, minus1 = 0, PI = 07, DB = 1
N2.C2.D1.R0.S04: TxDqs: plus1 = 1, minus1 = 0, PI = 31, DB = 0
N4.C2.D1.R1.S15: wrcmd2dqsstartlatency: 04
N6.C1.D0.R1.S05: TxDq : plus1 = 1, minus1 = 0, PI = 21, DB = 0
N0.C1.D0.R0.S14: TxDqs: plus1 = 1, minus1 = 0, PI = 57, DB = 1
N2.C2.D1.R0.S04: TxDq : plus1 = 0, minus1 = 1, PI = 00, DB = 1
N4.C2.D1.R1.S15: RdPtrOffsetTxDq: 05
N6.C1.D0.R1.S06: TxDqs: plus1 = 1, minus1 = 0, PI = 05, DB = 1
N0.C1.D0.R0.S14: TxDq : plus1 = 1, minus1 = 0, PI = 23, DB = 0
N2.C2.D1.R0.S05: TxDqs: plus1 = 1, minus1 = 0, PI = 63, DB = 1
N4.C2.D1.R1.S15: RdPtrOffsetTxDqs: 06
N6.C1.D0.R1.S06: TxDq : plus1 = 1, minus1 = 0, PI = 39, DB = 0
N0.C1.D0.R0.S15: TxDqs: plus1 = 1, minus1 = 0, PI = 06, DB = 1
N2.C2.D1.R0.S05: TxDq : plus1 = 1, minus1 = 0, PI = 30, DB = 0
N4.C2.D1.R1.S15: PiTxDqs: 63
N6.C1.D0.R1.S07: TxDqs: plus1 = 1, minus1 = 0, PI = 21, DB = 0
N0.C1.D0.R0.S15: TxDq : plus1 = 1, minus1 = 0, PI = 38, DB = 0
N2.C2.D1.R0.S06: TxDqs: plus1 = 1, minus1 = 0, PI = 57, DB = 1
N4.C2.D1.R1.S16: wrcmd2dqsstartlatency: 04
N6.C1.D0.R1.S07: TxDq : plus1 = 1, minus1 = 0, PI = 51, DB = 1
N0.C1.D0.R0.S16: TxDqs: plus1 = 1, minus1 = 0, PI = 25, DB = 0
N2.C2.D1.R0.S06: TxDq : plus1 = 1, minus1 = 0, PI = 24, DB = 0
N4.C2.D1.R1.S16: RdPtrOffsetTxDq: 05
N6.C1.D0.R1.S08: TxDqs: plus1 = 1, minus1 = 0, PI = 55, DB = 1
N0.C1.D0.R0.S16: TxDq : plus1 = 1, minus1 = 0, PI = 55, DB = 1
N2.C2.D1.R0.S07: TxDqs: plus1 = 1, minus1 = 0, PI = 18, DB = 0
N4.C2.D1.R1.S16: RdPtrOffsetTxDqs: 07
N6.C1.D0.R1.S08: TxDq : plus1 = 1, minus1 = 0, PI = 25, DB = 0
N0.C1.D0.R0.S17: TxDqs: plus1 = 1, minus1 = 0, PI = 56, DB = 1
N2.C2.D1.R0.S07: TxDq : plus1 = 1, minus1 = 0, PI = 48, DB = 0
N4.C2.D1.R1.S16: PiTxDqs: 17
N6.C1.D0.R1.S09: TxDqs: plus1 = 1, minus1 = 0, PI = 51, DB = 1
N0.C1.D0.R0.S17: TxDq : plus1 = 1, minus1 = 0, PI = 24, DB = 0
N2.C2.D1.R0.S08: TxDqs: plus1 = 1, minus1 = 0, PI = 47, DB = 0
N4.C2.D1.R1.S17: wrcmd2dqsstartlatency: 04
N6.C1.D0.R1.S09: TxDq : plus1 = 1, minus1 = 0, PI = 18, DB = 0
N0.C1.D0.R1.S00: TxDqs: plus1 = 1, minus1 = 0, PI = 54, DB = 1
N2.C2.D1.R0.S08: TxDq : plus1 = 1, minus1 = 0, PI = 13, DB = 1
N4.C2.D1.R1.S17: RdPtrOffsetTxDq: 05
N6.C1.D0.R1.S10: TxDqs: plus1 = 1, minus1 = 0, PI = 34, DB = 0
N0.C1.D0.R1.S00: TxDq : plus1 = 1, minus1 = 0, PI = 22, DB = 0
N2.C2.D1.R0.S09: TxDqs: plus1 = 1, minus1 = 0, PI = 48, DB = 0
N4.C2.D1.R1.S17: RdPtrOffsetTxDqs: 06
N6.C1.D0.R1.S10: TxDq : plus1 = 1, minus1 = 0, PI = 02, DB = 1
N0.C1.D0.R1.S01: TxDqs: plus1 = 1, minus1 = 0, PI = 35, DB = 0
N2.C2.D1.R0.S09: TxDq : plus1 = 1, minus1 = 0, PI = 14, DB = 1
N4.C2.D1.R1.S17: PiTxDqs: 48
N6.C1.D0.R1.S11: TxDqs: plus1 = 1, minus1 = 0, PI = 26, DB = 0
N0.C1.D0.R1.S01: TxDq : plus1 = 1, minus1 = 0, PI = 02, DB = 1
N2.C2.D1.R0.S10: TxDqs: plus1 = 1, minus1 = 0, PI = 36, DB = 0
N4.C2.D1.R1.S00: RdPtrOffsetTxDq: 07
N6.C1.D0.R1.S11: TxDq : plus1 = 1, minus1 = 0, PI = 57, DB = 1
N0.C1.D0.R1.S02: TxDqs: plus1 = 1, minus1 = 0, PI = 29, DB = 0
N2.C2.D1.R0.S10: TxDq : plus1 = 0, minus1 = 1, PI = 04, DB = 1
N4.C2.D1.R1.S01: RdPtrOffsetTxDq: 06
N6.C1.D0.R1.S12: TxDqs: plus1 = 1, minus1 = 0, PI = 09, DB = 1
N0.C1.D0.R1.S02: TxDq : plus1 = 1, minus1 = 0, PI = 58, DB = 1
N2.C2.D1.R0.S11: TxDqs: plus1 = 1, minus1 = 0, PI = 25, DB = 0
N4.C2.D1.R1.S02: RdPtrOffsetTxDq: 06
N6.C1.D0.R1.S12: TxDq : plus1 = 1, minus1 = 0, PI = 42, DB = 0
N0.C1.D0.R1.S03: TxDqs: plus1 = 1, minus1 = 0, PI = 10, DB = 1
N2.C2.D1.R0.S11: TxDq : plus1 = 1, minus1 = 0, PI = 57, DB = 1
N4.C2.D1.R1.S03: RdPtrOffsetTxDq: 06
N6.C1.D0.R1.S13: TxDqs: plus1 = 1, minus1 = 0, PI = 39, DB = 0
N0.C1.D0.R1.S03: TxDq : plus1 = 1, minus1 = 0, PI = 41, DB = 0
N2.C2.D1.R0.S12: TxDqs: plus1 = 1, minus1 = 0, PI = 12, DB = 1
N4.C2.D1.R1.S04: RdPtrOffsetTxDq: 05
N6.C1.D0.R1.S13: TxDq : plus1 = 1, minus1 = 0, PI = 09, DB = 1
N0.C1.D0.R1.S04: TxDqs: plus1 = 1, minus1 = 0, PI = 39, DB = 0
N2.C2.D1.R0.S12: TxDq : plus1 = 1, minus1 = 0, PI = 41, DB = 0
N4.C2.D1.R1.S05: RdPtrOffsetTxDq: 06
N6.C1.D0.R1.S14: TxDqs: plus1 = 1, minus1 = 0, PI = 52, DB = 1
N0.C1.D0.R1.S04: TxDq : plus1 = 1, minus1 = 0, PI = 06, DB = 1
N2.C2.D1.R0.S13: TxDqs: plus1 = 1, minus1 = 0, PI = 33, DB = 0
N4.C2.D1.R1.S06: RdPtrOffsetTxDq: 06
N6.C1.D0.R1.S14: TxDq : plus1 = 1, minus1 = 0, PI = 21, DB = 0
N0.C1.D0.R1.S05: TxDqs: plus1 = 1, minus1 = 0, PI = 56, DB = 1
N2.C2.D1.R0.S13: TxDq : plus1 = 0, minus1 = 1, PI = 01, DB = 1
N4.C2.D1.R1.S07: RdPtrOffsetTxDq: 06
N6.C1.D0.R1.S15: TxDqs: plus1 = 1, minus1 = 0, PI = 04, DB = 1
N0.C1.D0.R1.S05: TxDq : plus1 = 1, minus1 = 0, PI = 22, DB = 0
N2.C2.D1.R0.S14: TxDqs: plus1 = 1, minus1 = 0, PI = 62, DB = 1
N4.C2.D1.R1.S08: RdPtrOffsetTxDq: 06
N6.C1.D0.R1.S15: TxDq : plus1 = 1, minus1 = 0, PI = 39, DB = 0
N0.C1.D0.R1.S06: TxDqs: plus1 = 1, minus1 = 0, PI = 06, DB = 1
N2.C2.D1.R0.S14: TxDq : plus1 = 1, minus1 = 0, PI = 29, DB = 0
N4.C2.D1.R1.S09: RdPtrOffsetTxDq: 07
N6.C1.D0.R1.S16: TxDqs: plus1 = 1, minus1 = 0, PI = 21, DB = 0
N0.C1.D0.R1.S06: TxDq : plus1 = 1, minus1 = 0, PI = 38, DB = 0
N2.C2.D1.R0.S15: TxDqs: plus1 = 1, minus1 = 0, PI = 57, DB = 1
N4.C2.D1.R1.S10: RdPtrOffsetTxDq: 07
N6.C1.D0.R1.S16: TxDq : plus1 = 1, minus1 = 0, PI = 53, DB = 1
N0.C1.D0.R1.S07: TxDqs: plus1 = 1, minus1 = 0, PI = 23, DB = 0
N2.C2.D1.R0.S15: TxDq : plus1 = 1, minus1 = 0, PI = 25, DB = 0
N4.C2.D1.R1.S11: RdPtrOffsetTxDq: 06
N6.C1.D0.R1.S17: TxDqs: plus1 = 1, minus1 = 0, PI = 54, DB = 1
N0.C1.D0.R1.S07: TxDq : plus1 = 1, minus1 = 0, PI = 54, DB = 1
N2.C2.D1.R0.S16: TxDqs: plus1 = 1, minus1 = 0, PI = 17, DB = 0
N4.C2.D1.R1.S12: RdPtrOffsetTxDq: 06
N6.C1.D0.R1.S17: TxDq : plus1 = 1, minus1 = 0, PI = 23, DB = 0
N0.C1.D0.R1.S08: TxDqs: plus1 = 1, minus1 = 0, PI = 55, DB = 1
N2.C2.D1.R0.S16: TxDq : plus1 = 1, minus1 = 0, PI = 48, DB = 0
N4.C2.D1.R1.S13: RdPtrOffsetTxDq: 05
N6.C1.D1.R0.S00: TxDqs: plus1 = 1, minus1 = 0, PI = 56, DB = 1
N0.C1.D0.R1.S08: TxDq : plus1 = 1, minus1 = 0, PI = 22, DB = 0
N2.C2.D1.R0.S17: TxDqs: plus1 = 1, minus1 = 0, PI = 46, DB = 0
N4.C2.D1.R1.S14: RdPtrOffsetTxDq: 06
N6.C1.D1.R0.S00: TxDq : plus1 = 1, minus1 = 0, PI = 24, DB = 0
N0.C1.D0.R1.S09: TxDqs: plus1 = 1, minus1 = 0, PI = 53, DB = 1
N2.C2.D1.R0.S17: TxDq : plus1 = 1, minus1 = 0, PI = 13, DB = 1
N4.C2.D1.R1.S15: RdPtrOffsetTxDq: 06
N6.C1.D1.R0.S01: TxDqs: plus1 = 1, minus1 = 0, PI = 39, DB = 0
N0.C1.D0.R1.S09: TxDq : plus1 = 1, minus1 = 0, PI = 20, DB = 0
N2.C2.D1.R1.S00: TxDqs: plus1 = 1, minus1 = 0, PI = 49, DB = 1
N4.C2.D1.R1.S16: RdPtrOffsetTxDq: 06
N6.C1.D1.R0.S01: TxDq : plus1 = 1, minus1 = 0, PI = 06, DB = 1
N0.C1.D0.R1.S10: TxDqs: plus1 = 1, minus1 = 0, PI = 36, DB = 0
N2.C2.D1.R1.S00: TxDq : plus1 = 1, minus1 = 0, PI = 18, DB = 0
N4.C2.D1.R1.S17: RdPtrOffsetTxDq: 06
N6.C1.D1.R0.S02: TxDqs: plus1 = 1, minus1 = 0, PI = 29, DB = 0
N0.C1.D0.R1.S10: TxDq : plus1 = 1, minus1 = 0, PI = 03, DB = 1
N2.C2.D1.R1.S01: TxDqs: plus1 = 1, minus1 = 0, PI = 36, DB = 0
N4.C2.D1.R1.S00: RdPtrOffsetTxDq: 08
N6.C1.D1.R0.S02: TxDq : plus1 = 1, minus1 = 0, PI = 60, DB = 1
N0.C1.D0.R1.S11: TxDqs: plus1 = 1, minus1 = 0, PI = 28, DB = 0
N2.C2.D1.R1.S01: TxDq : plus1 = 0, minus1 = 1, PI = 03, DB = 1
N4.C2.D1.R1.S01: RdPtrOffsetTxDq: 07
N6.C1.D1.R0.S03: TxDqs: plus1 = 1, minus1 = 0, PI = 15, DB = 1
N0.C1.D0.R1.S11: TxDq : plus1 = 1, minus1 = 0, PI = 60, DB = 1
N2.C2.D1.R1.S02: TxDqs: plus1 = 1, minus1 = 0, PI = 23, DB = 0
N4.C2.D1.R1.S02: RdPtrOffsetTxDq: 07
N6.C1.D1.R0.S03: TxDq : plus1 = 1, minus1 = 0, PI = 46, DB = 0
N0.C1.D0.R1.S12: TxDqs: plus1 = 1, minus1 = 0, PI = 12, DB = 1
N2.C2.D1.R1.S02: TxDq : plus1 = 1, minus1 = 0, PI = 56, DB = 1
N4.C2.D1.R1.S03: RdPtrOffsetTxDq: 07
N6.C1.D1.R0.S04: TxDqs: plus1 = 1, minus1 = 0, PI = 45, DB = 0
N0.C1.D0.R1.S12: TxDq : plus1 = 1, minus1 = 0, PI = 43, DB = 0
N2.C2.D1.R1.S03: TxDqs: plus1 = 1, minus1 = 0, PI = 12, DB = 1
N4.C2.D1.R1.S04: RdPtrOffsetTxDq: 06
N6.C1.D1.R0.S04: TxDq : plus1 = 1, minus1 = 0, PI = 12, DB = 1
N0.C1.D0.R1.S13: TxDqs: plus1 = 1, minus1 = 0, PI = 41, DB = 0
N2.C2.D1.R1.S03: TxDq : plus1 = 1, minus1 = 0, PI = 43, DB = 0
N4.C2.D1.R1.S05: RdPtrOffsetTxDq: 07
N6.C1.D1.R0.S05: TxDqs: plus1 = 1, minus1 = 0, PI = 61, DB = 1
N0.C1.D0.R1.S13: TxDq : plus1 = 1, minus1 = 0, PI = 07, DB = 1
N2.C2.D1.R1.S04: TxDqs: plus1 = 1, minus1 = 0, PI = 31, DB = 0
N4.C2.D1.R1.S06: RdPtrOffsetTxDq: 07
N6.C1.D1.R0.S05: TxDq : plus1 = 1, minus1 = 0, PI = 27, DB = 0
N0.C1.D0.R1.S14: TxDqs: plus1 = 1, minus1 = 0, PI = 57, DB = 1
N2.C2.D1.R1.S04: TxDq : plus1 = 0, minus1 = 1, PI = 00, DB = 1
N4.C2.D1.R1.S07: RdPtrOffsetTxDq: 07
N6.C1.D1.R0.S06: TxDqs: plus1 = 1, minus1 = 0, PI = 08, DB = 1
N0.C1.D0.R1.S14: TxDq : plus1 = 1, minus1 = 0, PI = 23, DB = 0
N2.C2.D1.R1.S05: TxDqs: plus1 = 1, minus1 = 0, PI = 63, DB = 1
N4.C2.D1.R1.S08: RdPtrOffsetTxDq: 07
N6.C1.D1.R0.S06: TxDq : plus1 = 1, minus1 = 0, PI = 41, DB = 0
N0.C1.D0.R1.S15: TxDqs: plus1 = 1, minus1 = 0, PI = 06, DB = 1
N2.C2.D1.R1.S05: TxDq : plus1 = 1, minus1 = 0, PI = 30, DB = 0
N4.C2.D1.R1.S09: RdPtrOffsetTxDq: 08
N6.C1.D1.R0.S07: TxDqs: plus1 = 1, minus1 = 0, PI = 26, DB = 0
N0.C1.D0.R1.S15: TxDq : plus1 = 1, minus1 = 0, PI = 38, DB = 0
N2.C2.D1.R1.S06: TxDqs: plus1 = 1, minus1 = 0, PI = 57, DB = 1
N4.C2.D1.R1.S10: RdPtrOffsetTxDq: 08
N6.C1.D1.R0.S07: TxDq : plus1 = 1, minus1 = 0, PI = 56, DB = 1
N0.C1.D0.R1.S16: TxDqs: plus1 = 1, minus1 = 0, PI = 25, DB = 0
N2.C2.D1.R1.S06: TxDq : plus1 = 1, minus1 = 0, PI = 24, DB = 0
N4.C2.D1.R1.S11: RdPtrOffsetTxDq: 07
N6.C1.D1.R0.S08: TxDqs: plus1 = 1, minus1 = 0, PI = 59, DB = 1
N0.C1.D0.R1.S16: TxDq : plus1 = 1, minus1 = 0, PI = 55, DB = 1
N2.C2.D1.R1.S07: TxDqs: plus1 = 1, minus1 = 0, PI = 18, DB = 0
N4.C2.D1.R1.S12: RdPtrOffsetTxDq: 07
N6.C1.D1.R0.S08: TxDq : plus1 = 1, minus1 = 0, PI = 27, DB = 0
N0.C1.D0.R1.S17: TxDqs: plus1 = 1, minus1 = 0, PI = 56, DB = 1
N2.C2.D1.R1.S07: TxDq : plus1 = 1, minus1 = 0, PI = 48, DB = 0
N4.C2.D1.R1.S13: RdPtrOffsetTxDq: 06
N6.C1.D1.R0.S09: TxDqs: plus1 = 1, minus1 = 0, PI = 55, DB = 1
N0.C1.D0.R1.S17: TxDq : plus1 = 1, minus1 = 0, PI = 24, DB = 0
N2.C2.D1.R1.S08: TxDqs: plus1 = 1, minus1 = 0, PI = 47, DB = 0
N4.C2.D1.R1.S14: RdPtrOffsetTxDq: 07
N6.C1.D1.R0.S09: TxDq : plus1 = 1, minus1 = 0, PI = 22, DB = 0
N0.C1.D1.R0.S00: TxDqs: plus1 = 1, minus1 = 0, PI = 59, DB = 1
N2.C2.D1.R1.S08: TxDq : plus1 = 1, minus1 = 0, PI = 13, DB = 1
N4.C2.D1.R1.S15: RdPtrOffsetTxDq: 07
N6.C1.D1.R0.S10: TxDqs: plus1 = 1, minus1 = 0, PI = 40, DB = 0
N0.C1.D1.R0.S00: TxDq : plus1 = 1, minus1 = 0, PI = 27, DB = 0
N2.C2.D1.R1.S09: TxDqs: plus1 = 1, minus1 = 0, PI = 48, DB = 0
N4.C2.D1.R1.S16: RdPtrOffsetTxDq: 07
N6.C1.D1.R0.S10: TxDq : plus1 = 1, minus1 = 0, PI = 08, DB = 1
N0.C1.D1.R0.S01: TxDqs: plus1 = 1, minus1 = 0, PI = 42, DB = 0
N2.C2.D1.R1.S09: TxDq : plus1 = 1, minus1 = 0, PI = 14, DB = 1
N4.C2.D1.R1.S17: RdPtrOffsetTxDq: 07
N6.C1.D1.R0.S11: TxDqs: plus1 = 1, minus1 = 0, PI = 31, DB = 0
N0.C1.D1.R0.S01: TxDq : plus1 = 1, minus1 = 0, PI = 08, DB = 1
N2.C2.D1.R1.S10: TxDqs: plus1 = 1, minus1 = 0, PI = 36, DB = 0
N4.C2.D1.R1.S00: Total Delay in PI ticks: TxDQ = 977
N6.C1.D1.R0.S11: TxDq : plus1 = 1, minus1 = 0, PI = 62, DB = 1
N0.C1.D1.R0.S02: TxDqs: plus1 = 1, minus1 = 0, PI = 34, DB = 0
N2.C2.D1.R1.S10: TxDq : plus1 = 0, minus1 = 1, PI = 04, DB = 1
N4.C2.D1.R1.S01: Total Delay in PI ticks: TxDQ = 962
N6.C1.D1.R0.S12: TxDqs: plus1 = 1, minus1 = 0, PI = 17, DB = 0
N0.C1.D1.R0.S02: TxDq : plus1 = 1, minus1 = 0, PI = 63, DB = 1
N2.C2.D1.R1.S11: TxDqs: plus1 = 1, minus1 = 0, PI = 25, DB = 0
N4.C2.D1.R1.S02: Total Delay in PI ticks: TxDQ = 953
N6.C1.D1.R0.S12: TxDq : plus1 = 1, minus1 = 0, PI = 49, DB = 1
N0.C1.D1.R0.S03: TxDqs: plus1 = 1, minus1 = 0, PI = 21, DB = 0
N2.C2.D1.R1.S11: TxDq : plus1 = 1, minus1 = 0, PI = 57, DB = 1
N4.C2.D1.R1.S03: Total Delay in PI ticks: TxDQ = 937
N6.C1.D1.R0.S13: TxDqs: plus1 = 1, minus1 = 0, PI = 46, DB = 0
N0.C1.D1.R0.S03: TxDq : plus1 = 1, minus1 = 0, PI = 51, DB = 1
N2.C2.D1.R1.S12: TxDqs: plus1 = 1, minus1 = 0, PI = 12, DB = 1
N4.C2.D1.R1.S04: Total Delay in PI ticks: TxDQ = 897
N6.C1.D1.R0.S13: TxDq : plus1 = 1, minus1 = 0, PI = 14, DB = 1
N0.C1.D1.R0.S04: TxDqs: plus1 = 1, minus1 = 0, PI = 50, DB = 1
N2.C2.D1.R1.S12: TxDq : plus1 = 1, minus1 = 0, PI = 41, DB = 0
N4.C2.D1.R1.S05: Total Delay in PI ticks: TxDQ = 927
N6.C1.D1.R0.S14: TxDqs: plus1 = 1, minus1 = 0, PI = 60, DB = 1
N0.C1.D1.R0.S04: TxDq : plus1 = 1, minus1 = 0, PI = 16, DB = 0
N2.C2.D1.R1.S13: TxDqs: plus1 = 1, minus1 = 0, PI = 33, DB = 0
N4.C2.D1.R1.S06: Total Delay in PI ticks: TxDQ = 920
N6.C1.D1.R0.S14: TxDq : plus1 = 1, minus1 = 0, PI = 28, DB = 0
N0.C1.D1.R0.S05: TxDqs: plus1 = 1, minus1 = 0, PI = 63, DB = 1
N2.C2.D1.R1.S13: TxDq : plus1 = 0, minus1 = 1, PI = 01, DB = 1
N4.C2.D1.R1.S07: Total Delay in PI ticks: TxDQ = 942
N6.C1.D1.R0.S15: TxDqs: plus1 = 1, minus1 = 0, PI = 07, DB = 1
N0.C1.D1.R0.S05: TxDq : plus1 = 1, minus1 = 0, PI = 28, DB = 0
N2.C2.D1.R1.S14: TxDqs: plus1 = 1, minus1 = 0, PI = 62, DB = 1
N4.C2.D1.R1.S08: Total Delay in PI ticks: TxDQ = 911
N6.C1.D1.R0.S15: TxDq : plus1 = 1, minus1 = 0, PI = 40, DB = 0
N0.C1.D1.R0.S06: TxDqs: plus1 = 1, minus1 = 0, PI = 14, DB = 1
N2.C2.D1.R1.S14: TxDq : plus1 = 1, minus1 = 0, PI = 29, DB = 0
N4.C2.D1.R1.S09: Total Delay in PI ticks: TxDQ = 976
N6.C1.D1.R0.S16: TxDqs: plus1 = 1, minus1 = 0, PI = 29, DB = 0
N0.C1.D1.R0.S06: TxDq : plus1 = 1, minus1 = 0, PI = 43, DB = 0
N2.C2.D1.R1.S15: TxDqs: plus1 = 1, minus1 = 0, PI = 57, DB = 1
N4.C2.D1.R1.S10: Total Delay in PI ticks: TxDQ = 964
N6.C1.D1.R0.S16: TxDq : plus1 = 1, minus1 = 0, PI = 60, DB = 1
N0.C1.D1.R0.S07: TxDqs: plus1 = 1, minus1 = 0, PI = 33, DB = 0
N2.C2.D1.R1.S15: TxDq : plus1 = 1, minus1 = 0, PI = 25, DB = 0
N4.C2.D1.R1.S11: Total Delay in PI ticks: TxDQ = 952
N6.C1.D1.R0.S17: TxDqs: plus1 = 1, minus1 = 0, PI = 59, DB = 1
N0.C1.D1.R0.S07: TxDq : plus1 = 1, minus1 = 0, PI = 63, DB = 1
N2.C2.D1.R1.S16: TxDqs: plus1 = 1, minus1 = 0, PI = 17, DB = 0
N4.C2.D1.R1.S12: Total Delay in PI ticks: TxDQ = 938
N6.C1.D1.R0.S17: TxDq : plus1 = 1, minus1 = 0, PI = 25, DB = 0
N0.C1.D1.R0.S08: TxDqs: plus1 = 1, minus1 = 0, PI = 63, DB = 1
N2.C2.D1.R1.S16: TxDq : plus1 = 1, minus1 = 0, PI = 48, DB = 0
N4.C2.D1.R1.S13: Total Delay in PI ticks: TxDQ = 897
N6.C1.D1.R1.S00: TxDqs: plus1 = 1, minus1 = 0, PI = 56, DB = 1
N0.C1.D1.R0.S08: TxDq : plus1 = 1, minus1 = 0, PI = 28, DB = 0
N2.C2.D1.R1.S17: TxDqs: plus1 = 1, minus1 = 0, PI = 46, DB = 0
N4.C2.D1.R1.S14: Total Delay in PI ticks: TxDQ = 927
N6.C1.D1.R1.S00: TxDq : plus1 = 1, minus1 = 0, PI = 24, DB = 0
N0.C1.D1.R0.S09: TxDqs: plus1 = 1, minus1 = 0, PI = 60, DB = 1
N2.C2.D1.R1.S17: TxDq : plus1 = 1, minus1 = 0, PI = 13, DB = 1
N4.C2.D1.R1.S15: Total Delay in PI ticks: TxDQ = 924
N6.C1.D1.R1.S01: TxDqs: plus1 = 1, minus1 = 0, PI = 39, DB = 0
N0.C1.D1.R0.S09: TxDq : plus1 = 1, minus1 = 0, PI = 25, DB = 0
END_DATA_TX_DQ
N4.C2.D1.R1.S16: Total Delay in PI ticks: TxDQ = 943
N6.C1.D1.R1.S01: TxDq : plus1 = 1, minus1 = 0, PI = 06, DB = 1
N0.C1.D1.R0.S10: TxDqs: plus1 = 1, minus1 = 0, PI = 43, DB = 0
N2.C3.D0.R0.S00: wrcmd2dqsstartlatency: 04
N4.C2.D1.R1.S17: Total Delay in PI ticks: TxDQ = 910
N6.C1.D1.R1.S02: TxDqs: plus1 = 1, minus1 = 0, PI = 29, DB = 0
N0.C1.D1.R0.S10: TxDq : plus1 = 1, minus1 = 0, PI = 09, DB = 1
N2.C3.D0.R0.S00: RdPtrOffsetTxDq: 06
N4.C2: Calculating Optimimum DQ/DQS Values
N6.C1.D1.R1.S02: TxDq : plus1 = 1, minus1 = 0, PI = 60, DB = 1
N0.C1.D1.R0.S11: TxDqs: plus1 = 1, minus1 = 0, PI = 35, DB = 0
N2.C3.D0.R0.S00: RdPtrOffsetTxDqs: 07
N6.C1.D1.R1.S03: TxDqs: plus1 = 1, minus1 = 0, PI = 15, DB = 1
N0.C1.D1.R0.S11: TxDq : plus1 = 0, minus1 = 1, PI = 02, DB = 1
N2.C3.D0.R0.S00: PiTxDqs: 53
START_DATA_TX_DQ
N6.C1.D1.R1.S03: TxDq : plus1 = 1, minus1 = 0, PI = 46, DB = 0
N0.C1.D1.R0.S12: TxDqs: plus1 = 1, minus1 = 0, PI = 21, DB = 0
N2.C3.D0.R0.S01: wrcmd2dqsstartlatency: 04
N4.C2.S00: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 009, RdPtrOffsetTxDqs = 009
N6.C1.D1.R1.S04: TxDqs: plus1 = 1, minus1 = 0, PI = 45, DB = 0
N0.C1.D1.R0.S12: TxDq : plus1 = 1, minus1 = 0, PI = 52, DB = 1
N2.C3.D0.R0.S01: RdPtrOffsetTxDq: 06
N4.C2.S00: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 009, RdPtrOffsetTxDqs = 009
N6.C1.D1.R1.S04: TxDq : plus1 = 1, minus1 = 0, PI = 12, DB = 1
N0.C1.D1.R0.S13: TxDqs: plus1 = 1, minus1 = 0, PI = 50, DB = 1
N2.C3.D0.R0.S01: RdPtrOffsetTxDqs: 07
N4.C2.S01: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 009, RdPtrOffsetTxDqs = 009
N6.C1.D1.R1.S05: TxDqs: plus1 = 1, minus1 = 0, PI = 61, DB = 1
N0.C1.D1.R0.S13: TxDq : plus1 = 1, minus1 = 0, PI = 16, DB = 0
N2.C3.D0.R0.S01: PiTxDqs: 40
N4.C2.S01: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 009, RdPtrOffsetTxDqs = 009
N6.C1.D1.R1.S05: TxDq : plus1 = 1, minus1 = 0, PI = 27, DB = 0
N0.C1.D1.R0.S14: TxDqs: plus1 = 0, minus1 = 1, PI = 01, DB = 1
N2.C3.D0.R0.S02: wrcmd2dqsstartlatency: 04
N4.C2.S02: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 009
N6.C1.D1.R1.S06: TxDqs: plus1 = 1, minus1 = 0, PI = 08, DB = 1
N0.C1.D1.R0.S14: TxDq : plus1 = 1, minus1 = 0, PI = 32, DB = 0
N2.C3.D0.R0.S02: RdPtrOffsetTxDq: 05
N4.C2.S02: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 009
N6.C1.D1.R1.S06: TxDq : plus1 = 1, minus1 = 0, PI = 41, DB = 0
N0.C1.D1.R0.S15: TxDqs: plus1 = 1, minus1 = 0, PI = 14, DB = 1
N2.C3.D0.R0.S02: RdPtrOffsetTxDqs: 07
N4.C2.S03: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 009
N6.C1.D1.R1.S07: TxDqs: plus1 = 1, minus1 = 0, PI = 26, DB = 0
N0.C1.D1.R0.S15: TxDq : plus1 = 1, minus1 = 0, PI = 45, DB = 0
N2.C3.D0.R0.S02: PiTxDqs: 28
N4.C2.S03: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 009
N6.C1.D1.R1.S07: TxDq : plus1 = 1, minus1 = 0, PI = 56, DB = 1
N0.C1.D1.R0.S16: TxDqs: plus1 = 1, minus1 = 0, PI = 31, DB = 0
N2.C3.D0.R0.S03: wrcmd2dqsstartlatency: 04
N4.C2.S04: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 007, RdPtrOffsetTxDqs = 008
N6.C1.D1.R1.S08: TxDqs: plus1 = 1, minus1 = 0, PI = 59, DB = 1
N0.C1.D1.R0.S16: TxDq : plus1 = 1, minus1 = 0, PI = 61, DB = 1
N2.C3.D0.R0.S03: RdPtrOffsetTxDq: 05
N4.C2.S04: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 007, RdPtrOffsetTxDqs = 008
N6.C1.D1.R1.S08: TxDq : plus1 = 1, minus1 = 0, PI = 27, DB = 0
N0.C1.D1.R0.S17: TxDqs: plus1 = 1, minus1 = 0, PI = 62, DB = 1
N2.C3.D0.R0.S03: RdPtrOffsetTxDqs: 07
N4.C2.S05: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 008
N6.C1.D1.R1.S09: TxDqs: plus1 = 1, minus1 = 0, PI = 55, DB = 1
N0.C1.D1.R0.S17: TxDq : plus1 = 1, minus1 = 0, PI = 28, DB = 0
N2.C3.D0.R0.S03: PiTxDqs: 12
N4.C2.S05: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 008
N6.C1.D1.R1.S09: TxDq : plus1 = 1, minus1 = 0, PI = 22, DB = 0
N0.C1.D1.R1.S00: TxDqs: plus1 = 1, minus1 = 0, PI = 59, DB = 1
N2.C3.D0.R0.S04: wrcmd2dqsstartlatency: 04
N4.C2.S06: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 008
N6.C1.D1.R1.S10: TxDqs: plus1 = 1, minus1 = 0, PI = 40, DB = 0
N0.C1.D1.R1.S00: TxDq : plus1 = 1, minus1 = 0, PI = 27, DB = 0
N2.C3.D0.R0.S04: RdPtrOffsetTxDq: 05
N4.C2.S06: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 008
N6.C1.D1.R1.S10: TxDq : plus1 = 1, minus1 = 0, PI = 08, DB = 1
N0.C1.D1.R1.S01: TxDqs: plus1 = 1, minus1 = 0, PI = 42, DB = 0
N2.C3.D0.R0.S04: RdPtrOffsetTxDqs: 06
N4.C2.S07: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 009
N6.C1.D1.R1.S11: TxDqs: plus1 = 1, minus1 = 0, PI = 31, DB = 0
N0.C1.D1.R1.S01: TxDq : plus1 = 1, minus1 = 0, PI = 08, DB = 1
N2.C3.D0.R0.S04: PiTxDqs: 43
N4.C2.S07: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 009
N6.C1.D1.R1.S11: TxDq : plus1 = 1, minus1 = 0, PI = 62, DB = 1
N0.C1.D1.R1.S02: TxDqs: plus1 = 1, minus1 = 0, PI = 34, DB = 0
N2.C3.D0.R0.S05: wrcmd2dqsstartlatency: 04
N4.C2.S08: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 008
N6.C1.D1.R1.S12: TxDqs: plus1 = 1, minus1 = 0, PI = 17, DB = 0
N0.C1.D1.R1.S02: TxDq : plus1 = 1, minus1 = 0, PI = 63, DB = 1
N2.C3.D0.R0.S05: RdPtrOffsetTxDq: 05
N4.C2.S08: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 008
N6.C1.D1.R1.S12: TxDq : plus1 = 1, minus1 = 0, PI = 49, DB = 1
N0.C1.D1.R1.S03: TxDqs: plus1 = 1, minus1 = 0, PI = 21, DB = 0
N2.C3.D0.R0.S05: RdPtrOffsetTxDqs: 06
N4.C2.D0.R0.S00: TxDqs: plus1 = 1, minus1 = 0, PI = 49, DB = 1
N6.C1.D1.R1.S13: TxDqs: plus1 = 1, minus1 = 0, PI = 46, DB = 0
N0.C1.D1.R1.S03: TxDq : plus1 = 1, minus1 = 0, PI = 51, DB = 1
N2.C3.D0.R0.S05: PiTxDqs: 56
N4.C2.D0.R0.S00: TxDq : plus1 = 1, minus1 = 0, PI = 16, DB = 0
N6.C1.D1.R1.S13: TxDq : plus1 = 1, minus1 = 0, PI = 14, DB = 1
N0.C1.D1.R1.S04: TxDqs: plus1 = 1, minus1 = 0, PI = 50, DB = 1
N2.C3.D0.R0.S06: wrcmd2dqsstartlatency: 04
N4.C2.D0.R0.S01: TxDqs: plus1 = 1, minus1 = 0, PI = 34, DB = 0
N6.C1.D1.R1.S14: TxDqs: plus1 = 1, minus1 = 0, PI = 60, DB = 1
N0.C1.D1.R1.S04: TxDq : plus1 = 1, minus1 = 0, PI = 16, DB = 0
N2.C3.D0.R0.S06: RdPtrOffsetTxDq: 05
N4.C2.D0.R0.S01: TxDq : plus1 = 1, minus1 = 0, PI = 00, DB = 1
N6.C1.D1.R1.S14: TxDq : plus1 = 1, minus1 = 0, PI = 28, DB = 0
N0.C1.D1.R1.S05: TxDqs: plus1 = 1, minus1 = 0, PI = 63, DB = 1
N2.C3.D0.R0.S06: RdPtrOffsetTxDqs: 07
N4.C2.D0.R0.S02: TxDqs: plus1 = 1, minus1 = 0, PI = 25, DB = 0
N6.C1.D1.R1.S15: TxDqs: plus1 = 1, minus1 = 0, PI = 07, DB = 1
N0.C1.D1.R1.S05: TxDq : plus1 = 1, minus1 = 0, PI = 28, DB = 0
N2.C3.D0.R0.S06: PiTxDqs: 08
N4.C2.D0.R0.S02: TxDq : plus1 = 1, minus1 = 0, PI = 55, DB = 1
N6.C1.D1.R1.S15: TxDq : plus1 = 1, minus1 = 0, PI = 40, DB = 0
N0.C1.D1.R1.S06: TxDqs: plus1 = 1, minus1 = 0, PI = 14, DB = 1
N2.C3.D0.R0.S07: wrcmd2dqsstartlatency: 04
N4.C2.D0.R0.S03: TxDqs: plus1 = 1, minus1 = 0, PI = 07, DB = 1
N6.C1.D1.R1.S16: TxDqs: plus1 = 1, minus1 = 0, PI = 29, DB = 0
N0.C1.D1.R1.S06: TxDq : plus1 = 1, minus1 = 0, PI = 43, DB = 0
N2.C3.D0.R0.S07: RdPtrOffsetTxDq: 05
N4.C2.D0.R0.S03: TxDq : plus1 = 1, minus1 = 0, PI = 37, DB = 0
N6.C1.D1.R1.S16: TxDq : plus1 = 1, minus1 = 0, PI = 60, DB = 1
N0.C1.D1.R1.S07: TxDqs: plus1 = 1, minus1 = 0, PI = 33, DB = 0
N2.C3.D0.R0.S07: RdPtrOffsetTxDqs: 07
N4.C2.D0.R0.S04: TxDqs: plus1 = 1, minus1 = 0, PI = 29, DB = 0
N6.C1.D1.R1.S17: TxDqs: plus1 = 1, minus1 = 0, PI = 59, DB = 1
N0.C1.D1.R1.S07: TxDq : plus1 = 1, minus1 = 0, PI = 63, DB = 1
N2.C3.D0.R0.S07: PiTxDqs: 23
N4.C2.D0.R0.S04: TxDq : plus1 = 1, minus1 = 0, PI = 62, DB = 1
N6.C1.D1.R1.S17: TxDq : plus1 = 1, minus1 = 0, PI = 25, DB = 0
N0.C1.D1.R1.S08: TxDqs: plus1 = 1, minus1 = 0, PI = 63, DB = 1
N2.C3.D0.R0.S08: wrcmd2dqsstartlatency: 04
N4.C2.D0.R0.S05: TxDqs: plus1 = 1, minus1 = 0, PI = 58, DB = 1
END_DATA_TX_DQ
N0.C1.D1.R1.S08: TxDq : plus1 = 1, minus1 = 0, PI = 28, DB = 0
N2.C3.D0.R0.S08: RdPtrOffsetTxDq: 05
N4.C2.D0.R0.S05: TxDq : plus1 = 1, minus1 = 0, PI = 25, DB = 0
N6.C2.D0.R0.S00: wrcmd2dqsstartlatency: 04
N0.C1.D1.R1.S09: TxDqs: plus1 = 1, minus1 = 0, PI = 60, DB = 1
N2.C3.D0.R0.S08: RdPtrOffsetTxDqs: 06
N4.C2.D0.R0.S06: TxDqs: plus1 = 1, minus1 = 0, PI = 57, DB = 1
N6.C2.D0.R0.S00: RdPtrOffsetTxDq: 06
N0.C1.D1.R1.S09: TxDq : plus1 = 1, minus1 = 0, PI = 25, DB = 0
N2.C3.D0.R0.S08: PiTxDqs: 61
N4.C2.D0.R0.S06: TxDq : plus1 = 1, minus1 = 0, PI = 24, DB = 0
N6.C2.D0.R0.S00: RdPtrOffsetTxDqs: 07
N0.C1.D1.R1.S10: TxDqs: plus1 = 1, minus1 = 0, PI = 43, DB = 0
N2.C3.D0.R0.S09: wrcmd2dqsstartlatency: 04
N4.C2.D0.R0.S07: TxDqs: plus1 = 1, minus1 = 0, PI = 13, DB = 1
N6.C2.D0.R0.S00: PiTxDqs: 48
N0.C1.D1.R1.S10: TxDq : plus1 = 1, minus1 = 0, PI = 09, DB = 1
N2.C3.D0.R0.S09: RdPtrOffsetTxDq: 06
N4.C2.D0.R0.S07: TxDq : plus1 = 1, minus1 = 0, PI = 43, DB = 0
N6.C2.D0.R0.S01: wrcmd2dqsstartlatency: 04
N0.C1.D1.R1.S11: TxDqs: plus1 = 1, minus1 = 0, PI = 35, DB = 0
N2.C3.D0.R0.S09: RdPtrOffsetTxDqs: 07
N4.C2.D0.R0.S08: TxDqs: plus1 = 1, minus1 = 0, PI = 50, DB = 1
N6.C2.D0.R0.S01: RdPtrOffsetTxDq: 06
N0.C1.D1.R1.S11: TxDq : plus1 = 0, minus1 = 1, PI = 02, DB = 1
N2.C3.D0.R0.S09: PiTxDqs: 56
N4.C2.D0.R0.S08: TxDq : plus1 = 1, minus1 = 0, PI = 16, DB = 0
N6.C2.D0.R0.S01: RdPtrOffsetTxDqs: 07
N0.C1.D1.R1.S12: TxDqs: plus1 = 1, minus1 = 0, PI = 21, DB = 0
N2.C3.D0.R0.S10: wrcmd2dqsstartlatency: 04
N4.C2.D0.R0.S09: TxDqs: plus1 = 1, minus1 = 0, PI = 51, DB = 1
N6.C2.D0.R0.S01: PiTxDqs: 35
N0.C1.D1.R1.S12: TxDq : plus1 = 1, minus1 = 0, PI = 52, DB = 1
N2.C3.D0.R0.S10: RdPtrOffsetTxDq: 06
N4.C2.D0.R0.S09: TxDq : plus1 = 1, minus1 = 0, PI = 16, DB = 0
N6.C2.D0.R0.S02: wrcmd2dqsstartlatency: 04
N0.C1.D1.R1.S13: TxDqs: plus1 = 1, minus1 = 0, PI = 50, DB = 1
N2.C3.D0.R0.S10: RdPtrOffsetTxDqs: 07
N4.C2.D0.R0.S10: TxDqs: plus1 = 1, minus1 = 0, PI = 37, DB = 0
N6.C2.D0.R0.S02: RdPtrOffsetTxDq: 05
N0.C1.D1.R1.S13: TxDq : plus1 = 1, minus1 = 0, PI = 16, DB = 0
N2.C3.D0.R0.S10: PiTxDqs: 42
N4.C2.D0.R0.S10: TxDq : plus1 = 1, minus1 = 0, PI = 02, DB = 1
N6.C2.D0.R0.S02: RdPtrOffsetTxDqs: 07
N0.C1.D1.R1.S14: TxDqs: plus1 = 0, minus1 = 1, PI = 01, DB = 1
N2.C3.D0.R0.S11: wrcmd2dqsstartlatency: 04
N4.C2.D0.R0.S11: TxDqs: plus1 = 1, minus1 = 0, PI = 25, DB = 0
N6.C2.D0.R0.S02: PiTxDqs: 24
N0.C1.D1.R1.S14: TxDq : plus1 = 1, minus1 = 0, PI = 32, DB = 0
N2.C3.D0.R0.S11: RdPtrOffsetTxDq: 05
N4.C2.D0.R0.S11: TxDq : plus1 = 1, minus1 = 0, PI = 55, DB = 1
N6.C2.D0.R0.S03: wrcmd2dqsstartlatency: 04
N0.C1.D1.R1.S15: TxDqs: plus1 = 1, minus1 = 0, PI = 14, DB = 1
N2.C3.D0.R0.S11: RdPtrOffsetTxDqs: 07
N4.C2.D0.R0.S12: TxDqs: plus1 = 1, minus1 = 0, PI = 08, DB = 1
N6.C2.D0.R0.S03: RdPtrOffsetTxDq: 05
N0.C1.D1.R1.S15: TxDq : plus1 = 1, minus1 = 0, PI = 45, DB = 0
N2.C3.D0.R0.S11: PiTxDqs: 28
N4.C2.D0.R0.S12: TxDq : plus1 = 1, minus1 = 0, PI = 39, DB = 0
N6.C2.D0.R0.S03: RdPtrOffsetTxDqs: 07
N0.C1.D1.R1.S16: TxDqs: plus1 = 1, minus1 = 0, PI = 31, DB = 0
N2.C3.D0.R0.S12: wrcmd2dqsstartlatency: 04
N4.C2.D0.R0.S13: TxDqs: plus1 = 1, minus1 = 0, PI = 31, DB = 0
N6.C2.D0.R0.S03: PiTxDqs: 04
N0.C1.D1.R1.S16: TxDq : plus1 = 1, minus1 = 0, PI = 61, DB = 1
N2.C3.D0.R0.S12: RdPtrOffsetTxDq: 05
N4.C2.D0.R0.S13: TxDq : plus1 = 1, minus1 = 0, PI = 62, DB = 1
N6.C2.D0.R0.S04: wrcmd2dqsstartlatency: 04
N0.C1.D1.R1.S17: TxDqs: plus1 = 1, minus1 = 0, PI = 62, DB = 1
N2.C3.D0.R0.S12: RdPtrOffsetTxDqs: 07
N4.C2.D0.R0.S14: TxDqs: plus1 = 1, minus1 = 0, PI = 59, DB = 1
N6.C2.D0.R0.S04: RdPtrOffsetTxDq: 05
N0.C1.D1.R1.S17: TxDq : plus1 = 1, minus1 = 0, PI = 28, DB = 0
N2.C3.D0.R0.S12: PiTxDqs: 14
N4.C2.D0.R0.S14: TxDq : plus1 = 1, minus1 = 0, PI = 27, DB = 0
N6.C2.D0.R0.S04: RdPtrOffsetTxDqs: 06
END_DATA_TX_DQ
N2.C3.D0.R0.S13: wrcmd2dqsstartlatency: 04
N4.C2.D0.R0.S15: TxDqs: plus1 = 1, minus1 = 0, PI = 57, DB = 1
N6.C2.D0.R0.S04: PiTxDqs: 30
N0.C2.D0.R0.S00: wrcmd2dqsstartlatency: 04
N2.C3.D0.R0.S13: RdPtrOffsetTxDq: 05
N4.C2.D0.R0.S15: TxDq : plus1 = 1, minus1 = 0, PI = 25, DB = 0
N6.C2.D0.R0.S05: wrcmd2dqsstartlatency: 04
N0.C2.D0.R0.S00: RdPtrOffsetTxDq: 06
N2.C3.D0.R0.S13: RdPtrOffsetTxDqs: 06
N4.C2.D0.R0.S16: TxDqs: plus1 = 1, minus1 = 0, PI = 12, DB = 1
N6.C2.D0.R0.S05: RdPtrOffsetTxDq: 05
N0.C2.D0.R0.S00: RdPtrOffsetTxDqs: 07
N2.C3.D0.R0.S13: PiTxDqs: 42
N4.C2.D0.R0.S16: TxDq : plus1 = 1, minus1 = 0, PI = 43, DB = 0
N6.C2.D0.R0.S05: RdPtrOffsetTxDqs: 06
N0.C2.D0.R0.S00: PiTxDqs: 55
N2.C3.D0.R0.S14: wrcmd2dqsstartlatency: 04
N4.C2.D0.R0.S17: TxDqs: plus1 = 1, minus1 = 0, PI = 48, DB = 0
N6.C2.D0.R0.S05: PiTxDqs: 59
N0.C2.D0.R0.S01: wrcmd2dqsstartlatency: 04
N2.C3.D0.R0.S14: RdPtrOffsetTxDq: 05
N4.C2.D0.R0.S17: TxDq : plus1 = 1, minus1 = 0, PI = 13, DB = 1
N6.C2.D0.R0.S06: wrcmd2dqsstartlatency: 04
N0.C2.D0.R0.S01: RdPtrOffsetTxDq: 06
N2.C3.D0.R0.S14: RdPtrOffsetTxDqs: 06
N4.C2.D0.R1.S00: TxDqs: plus1 = 1, minus1 = 0, PI = 49, DB = 1
N6.C2.D0.R0.S06: RdPtrOffsetTxDq: 05
N0.C2.D0.R0.S01: RdPtrOffsetTxDqs: 07
N2.C3.D0.R0.S14: PiTxDqs: 57
N4.C2.D0.R1.S00: TxDq : plus1 = 1, minus1 = 0, PI = 16, DB = 0
N6.C2.D0.R0.S06: RdPtrOffsetTxDqs: 06
N0.C2.D0.R0.S01: PiTxDqs: 39
N2.C3.D0.R0.S15: wrcmd2dqsstartlatency: 04
N4.C2.D0.R1.S01: TxDqs: plus1 = 1, minus1 = 0, PI = 34, DB = 0
N6.C2.D0.R0.S06: PiTxDqs: 61
N0.C2.D0.R0.S02: wrcmd2dqsstartlatency: 04
N2.C3.D0.R0.S15: RdPtrOffsetTxDq: 05
N4.C2.D0.R1.S01: TxDq : plus1 = 1, minus1 = 0, PI = 00, DB = 1
N6.C2.D0.R0.S07: wrcmd2dqsstartlatency: 04
N0.C2.D0.R0.S02: RdPtrOffsetTxDq: 05
N2.C3.D0.R0.S15: RdPtrOffsetTxDqs: 07
N4.C2.D0.R1.S02: TxDqs: plus1 = 1, minus1 = 0, PI = 25, DB = 0
N6.C2.D0.R0.S07: RdPtrOffsetTxDq: 05
N0.C2.D0.R0.S02: RdPtrOffsetTxDqs: 07
N2.C3.D0.R0.S15: PiTxDqs: 07
N4.C2.D0.R1.S02: TxDq : plus1 = 1, minus1 = 0, PI = 55, DB = 1
N6.C2.D0.R0.S07: RdPtrOffsetTxDqs: 07
N0.C2.D0.R0.S02: PiTxDqs: 29
N2.C3.D0.R0.S16: wrcmd2dqsstartlatency: 04
N4.C2.D0.R1.S03: TxDqs: plus1 = 1, minus1 = 0, PI = 07, DB = 1
N6.C2.D0.R0.S07: PiTxDqs: 15
N0.C2.D0.R0.S03: wrcmd2dqsstartlatency: 04
N2.C3.D0.R0.S16: RdPtrOffsetTxDq: 05
N4.C2.D0.R1.S03: TxDq : plus1 = 1, minus1 = 0, PI = 37, DB = 0
N6.C2.D0.R0.S08: wrcmd2dqsstartlatency: 04
N0.C2.D0.R0.S03: RdPtrOffsetTxDq: 05
N2.C3.D0.R0.S16: RdPtrOffsetTxDqs: 07
N4.C2.D0.R1.S04: TxDqs: plus1 = 1, minus1 = 0, PI = 29, DB = 0
N6.C2.D0.R0.S08: RdPtrOffsetTxDq: 05
N0.C2.D0.R0.S03: RdPtrOffsetTxDqs: 07
N2.C3.D0.R0.S16: PiTxDqs: 22
N4.C2.D0.R1.S04: TxDq : plus1 = 1, minus1 = 0, PI = 62, DB = 1
N6.C2.D0.R0.S08: RdPtrOffsetTxDqs: 06
N0.C2.D0.R0.S03: PiTxDqs: 10
N2.C3.D0.R0.S17: wrcmd2dqsstartlatency: 04
N4.C2.D0.R1.S05: TxDqs: plus1 = 1, minus1 = 0, PI = 58, DB = 1
N6.C2.D0.R0.S08: PiTxDqs: 49
N0.C2.D0.R0.S04: wrcmd2dqsstartlatency: 04
N2.C3.D0.R0.S17: RdPtrOffsetTxDq: 05
N4.C2.D0.R1.S05: TxDq : plus1 = 1, minus1 = 0, PI = 25, DB = 0
N6.C2.D0.R0.S09: wrcmd2dqsstartlatency: 04
N0.C2.D0.R0.S04: RdPtrOffsetTxDq: 05
N2.C3.D0.R0.S17: RdPtrOffsetTxDqs: 06
N4.C2.D0.R1.S06: TxDqs: plus1 = 1, minus1 = 0, PI = 57, DB = 1
N6.C2.D0.R0.S09: RdPtrOffsetTxDq: 06
N0.C2.D0.R0.S04: RdPtrOffsetTxDqs: 06
N2.C3.D0.R0.S17: PiTxDqs: 60
N4.C2.D0.R1.S06: TxDq : plus1 = 1, minus1 = 0, PI = 24, DB = 0
N6.C2.D0.R0.S09: RdPtrOffsetTxDqs: 07
N0.C2.D0.R0.S04: PiTxDqs: 37
N2.C3.D0.R0.S00: RdPtrOffsetTxDq: 07
N4.C2.D0.R1.S07: TxDqs: plus1 = 1, minus1 = 0, PI = 13, DB = 1
N6.C2.D0.R0.S09: PiTxDqs: 49
N0.C2.D0.R0.S05: wrcmd2dqsstartlatency: 04
N2.C3.D0.R0.S01: RdPtrOffsetTxDq: 07
N4.C2.D0.R1.S07: TxDq : plus1 = 1, minus1 = 0, PI = 43, DB = 0
N6.C2.D0.R0.S10: wrcmd2dqsstartlatency: 04
N0.C2.D0.R0.S05: RdPtrOffsetTxDq: 05
N2.C3.D0.R0.S02: RdPtrOffsetTxDq: 06
N4.C2.D0.R1.S08: TxDqs: plus1 = 1, minus1 = 0, PI = 50, DB = 1
N6.C2.D0.R0.S10: RdPtrOffsetTxDq: 06
N0.C2.D0.R0.S05: RdPtrOffsetTxDqs: 06
N2.C3.D0.R0.S03: RdPtrOffsetTxDq: 06
N4.C2.D0.R1.S08: TxDq : plus1 = 1, minus1 = 0, PI = 16, DB = 0
N6.C2.D0.R0.S10: RdPtrOffsetTxDqs: 07
N0.C2.D0.R0.S05: PiTxDqs: 63
N2.C3.D0.R0.S04: RdPtrOffsetTxDq: 06
N4.C2.D0.R1.S09: TxDqs: plus1 = 1, minus1 = 0, PI = 51, DB = 1
N6.C2.D0.R0.S10: PiTxDqs: 36
N0.C2.D0.R0.S06: wrcmd2dqsstartlatency: 04
N2.C3.D0.R0.S05: RdPtrOffsetTxDq: 06
N4.C2.D0.R1.S09: TxDq : plus1 = 1, minus1 = 0, PI = 16, DB = 0
N6.C2.D0.R0.S11: wrcmd2dqsstartlatency: 04
N0.C2.D0.R0.S06: RdPtrOffsetTxDq: 05
N2.C3.D0.R0.S06: RdPtrOffsetTxDq: 06
N4.C2.D0.R1.S10: TxDqs: plus1 = 1, minus1 = 0, PI = 37, DB = 0
N6.C2.D0.R0.S11: RdPtrOffsetTxDq: 05
N0.C2.D0.R0.S06: RdPtrOffsetTxDqs: 06
N2.C3.D0.R0.S07: RdPtrOffsetTxDq: 06
N4.C2.D0.R1.S10: TxDq : plus1 = 1, minus1 = 0, PI = 02, DB = 1
N6.C2.D0.R0.S11: RdPtrOffsetTxDqs: 07
N0.C2.D0.R0.S06: PiTxDqs: 63
N2.C3.D0.R0.S08: RdPtrOffsetTxDq: 06
N4.C2.D0.R1.S11: TxDqs: plus1 = 1, minus1 = 0, PI = 25, DB = 0
N6.C2.D0.R0.S11: PiTxDqs: 25
N0.C2.D0.R0.S07: wrcmd2dqsstartlatency: 04
N2.C3.D0.R0.S09: RdPtrOffsetTxDq: 07
N4.C2.D0.R1.S11: TxDq : plus1 = 1, minus1 = 0, PI = 55, DB = 1
N6.C2.D0.R0.S12: wrcmd2dqsstartlatency: 04
N0.C2.D0.R0.S07: RdPtrOffsetTxDq: 05
N2.C3.D0.R0.S10: RdPtrOffsetTxDq: 07
N4.C2.D0.R1.S12: TxDqs: plus1 = 1, minus1 = 0, PI = 08, DB = 1
N6.C2.D0.R0.S12: RdPtrOffsetTxDq: 05
N0.C2.D0.R0.S07: RdPtrOffsetTxDqs: 07
N2.C3.D0.R0.S11: RdPtrOffsetTxDq: 06
N4.C2.D0.R1.S12: TxDq : plus1 = 1, minus1 = 0, PI = 39, DB = 0
N6.C2.D0.R0.S12: RdPtrOffsetTxDqs: 07
N0.C2.D0.R0.S07: PiTxDqs: 18
N2.C3.D0.R0.S12: RdPtrOffsetTxDq: 06
N4.C2.D0.R1.S13: TxDqs: plus1 = 1, minus1 = 0, PI = 31, DB = 0
N6.C2.D0.R0.S12: PiTxDqs: 05
N0.C2.D0.R0.S08: wrcmd2dqsstartlatency: 04
N2.C3.D0.R0.S13: RdPtrOffsetTxDq: 06
N4.C2.D0.R1.S13: TxDq : plus1 = 1, minus1 = 0, PI = 62, DB = 1
N6.C2.D0.R0.S13: wrcmd2dqsstartlatency: 04
N0.C2.D0.R0.S08: RdPtrOffsetTxDq: 05
N2.C3.D0.R0.S14: RdPtrOffsetTxDq: 06
N4.C2.D0.R1.S14: TxDqs: plus1 = 1, minus1 = 0, PI = 59, DB = 1
N6.C2.D0.R0.S13: RdPtrOffsetTxDq: 04
N0.C2.D0.R0.S08: RdPtrOffsetTxDqs: 06
N2.C3.D0.R0.S15: RdPtrOffsetTxDq: 06
N4.C2.D0.R1.S14: TxDq : plus1 = 1, minus1 = 0, PI = 27, DB = 0
N6.C2.D0.R0.S13: RdPtrOffsetTxDqs: 06
N0.C2.D0.R0.S08: PiTxDqs: 57
N2.C3.D0.R0.S16: RdPtrOffsetTxDq: 06
N4.C2.D0.R1.S15: TxDqs: plus1 = 1, minus1 = 0, PI = 57, DB = 1
N6.C2.D0.R0.S13: PiTxDqs: 30
N0.C2.D0.R0.S09: wrcmd2dqsstartlatency: 04
N2.C3.D0.R0.S17: RdPtrOffsetTxDq: 06
N4.C2.D0.R1.S15: TxDq : plus1 = 1, minus1 = 0, PI = 25, DB = 0
N6.C2.D0.R0.S14: wrcmd2dqsstartlatency: 04
N0.C2.D0.R0.S09: RdPtrOffsetTxDq: 06
N2.C3.D0.R0.S00: RdPtrOffsetTxDq: 08
N4.C2.D0.R1.S16: TxDqs: plus1 = 1, minus1 = 0, PI = 12, DB = 1
N6.C2.D0.R0.S14: RdPtrOffsetTxDq: 05
N0.C2.D0.R0.S09: RdPtrOffsetTxDqs: 07
N2.C3.D0.R0.S01: RdPtrOffsetTxDq: 08
N4.C2.D0.R1.S16: TxDq : plus1 = 1, minus1 = 0, PI = 43, DB = 0
N6.C2.D0.R0.S14: RdPtrOffsetTxDqs: 06
N0.C2.D0.R0.S09: PiTxDqs: 56
N2.C3.D0.R0.S02: RdPtrOffsetTxDq: 07
N4.C2.D0.R1.S17: TxDqs: plus1 = 1, minus1 = 0, PI = 48, DB = 0
N6.C2.D0.R0.S14: PiTxDqs: 57
N0.C2.D0.R0.S10: wrcmd2dqsstartlatency: 04
N2.C3.D0.R0.S03: RdPtrOffsetTxDq: 07
N4.C2.D0.R1.S17: TxDq : plus1 = 1, minus1 = 0, PI = 13, DB = 1
N6.C2.D0.R0.S15: wrcmd2dqsstartlatency: 04
N0.C2.D0.R0.S10: RdPtrOffsetTxDq: 06
N2.C3.D0.R0.S04: RdPtrOffsetTxDq: 07
N4.C2.D1.R0.S00: TxDqs: plus1 = 1, minus1 = 0, PI = 53, DB = 1
N6.C2.D0.R0.S15: RdPtrOffsetTxDq: 05
N0.C2.D0.R0.S10: RdPtrOffsetTxDqs: 07
N2.C3.D0.R0.S05: RdPtrOffsetTxDq: 07
N4.C2.D1.R0.S00: TxDq : plus1 = 1, minus1 = 0, PI = 19, DB = 0
N6.C2.D0.R0.S15: RdPtrOffsetTxDqs: 06
N0.C2.D0.R0.S10: PiTxDqs: 42
N2.C3.D0.R0.S06: RdPtrOffsetTxDq: 07
N4.C2.D1.R0.S01: TxDqs: plus1 = 1, minus1 = 0, PI = 39, DB = 0
N6.C2.D0.R0.S15: PiTxDqs: 59
N0.C2.D0.R0.S11: wrcmd2dqsstartlatency: 04
N2.C3.D0.R0.S07: RdPtrOffsetTxDq: 07
N4.C2.D1.R0.S01: TxDq : plus1 = 1, minus1 = 0, PI = 04, DB = 1
N6.C2.D0.R0.S16: wrcmd2dqsstartlatency: 04
N0.C2.D0.R0.S11: RdPtrOffsetTxDq: 05
N2.C3.D0.R0.S08: RdPtrOffsetTxDq: 07
N4.C2.D1.R0.S02: TxDqs: plus1 = 1, minus1 = 0, PI = 30, DB = 0
N6.C2.D0.R0.S16: RdPtrOffsetTxDq: 05
N0.C2.D0.R0.S11: RdPtrOffsetTxDqs: 07
N2.C3.D0.R0.S09: RdPtrOffsetTxDq: 08
N4.C2.D1.R0.S02: TxDq : plus1 = 1, minus1 = 0, PI = 59, DB = 1
N6.C2.D0.R0.S16: RdPtrOffsetTxDqs: 07
N0.C2.D0.R0.S11: PiTxDqs: 30
N2.C3.D0.R0.S10: RdPtrOffsetTxDq: 08
N4.C2.D1.R0.S03: TxDqs: plus1 = 1, minus1 = 0, PI = 15, DB = 1
N6.C2.D0.R0.S16: PiTxDqs: 15
N0.C2.D0.R0.S12: wrcmd2dqsstartlatency: 04
N2.C3.D0.R0.S11: RdPtrOffsetTxDq: 07
N4.C2.D1.R0.S03: TxDq : plus1 = 1, minus1 = 0, PI = 43, DB = 0
N6.C2.D0.R0.S17: wrcmd2dqsstartlatency: 04
N0.C2.D0.R0.S12: RdPtrOffsetTxDq: 05
N2.C3.D0.R0.S12: RdPtrOffsetTxDq: 07
N4.C2.D1.R0.S04: TxDqs: plus1 = 1, minus1 = 0, PI = 36, DB = 0
N6.C2.D0.R0.S17: RdPtrOffsetTxDq: 05
N0.C2.D0.R0.S12: RdPtrOffsetTxDqs: 07
N2.C3.D0.R0.S13: RdPtrOffsetTxDq: 07
N4.C2.D1.R0.S04: TxDq : plus1 = 0, minus1 = 1, PI = 03, DB = 1
N6.C2.D0.R0.S17: RdPtrOffsetTxDqs: 06
N0.C2.D0.R0.S12: PiTxDqs: 09
N2.C3.D0.R0.S14: RdPtrOffsetTxDq: 07
N4.C2.D1.R0.S05: TxDqs: plus1 = 0, minus1 = 1, PI = 01, DB = 1
N6.C2.D0.R0.S17: PiTxDqs: 49
N0.C2.D0.R0.S13: wrcmd2dqsstartlatency: 04
N2.C3.D0.R0.S15: RdPtrOffsetTxDq: 07
N4.C2.D1.R0.S05: TxDq : plus1 = 1, minus1 = 0, PI = 31, DB = 0
N6.C2.D0.R0.S00: RdPtrOffsetTxDq: 07
N0.C2.D0.R0.S13: RdPtrOffsetTxDq: 05
N2.C3.D0.R0.S16: RdPtrOffsetTxDq: 07
N4.C2.D1.R0.S06: TxDqs: plus1 = 1, minus1 = 0, PI = 62, DB = 1
N6.C2.D0.R0.S01: RdPtrOffsetTxDq: 07
N0.C2.D0.R0.S13: RdPtrOffsetTxDqs: 06
N2.C3.D0.R0.S17: RdPtrOffsetTxDq: 07
N4.C2.D1.R0.S06: TxDq : plus1 = 1, minus1 = 0, PI = 27, DB = 0
N6.C2.D0.R0.S02: RdPtrOffsetTxDq: 06
N0.C2.D0.R0.S13: PiTxDqs: 34
N2.C3.D0.R0.S00: Total Delay in PI ticks: TxDQ = 981
N4.C2.D1.R0.S07: TxDqs: plus1 = 1, minus1 = 0, PI = 18, DB = 0
N6.C2.D0.R0.S03: RdPtrOffsetTxDq: 06
N0.C2.D0.R0.S14: wrcmd2dqsstartlatency: 04
N2.C3.D0.R0.S01: Total Delay in PI ticks: TxDQ = 967
N4.C2.D1.R0.S07: TxDq : plus1 = 1, minus1 = 0, PI = 47, DB = 0
N6.C2.D0.R0.S04: RdPtrOffsetTxDq: 06
N0.C2.D0.R0.S14: RdPtrOffsetTxDq: 05
N2.C3.D0.R0.S02: Total Delay in PI ticks: TxDQ = 956
N4.C2.D1.R0.S08: TxDqs: plus1 = 1, minus1 = 0, PI = 52, DB = 1
N6.C2.D0.R0.S05: RdPtrOffsetTxDq: 06
N0.C2.D0.R0.S14: RdPtrOffsetTxDqs: 06
N2.C3.D0.R0.S03: Total Delay in PI ticks: TxDQ = 940
N4.C2.D1.R0.S08: TxDq : plus1 = 1, minus1 = 0, PI = 18, DB = 0
N6.C2.D0.R0.S06: RdPtrOffsetTxDq: 06
N0.C2.D0.R0.S14: PiTxDqs: 62
N2.C3.D0.R0.S04: Total Delay in PI ticks: TxDQ = 906
N4.C2.D1.R0.S09: TxDqs: plus1 = 1, minus1 = 0, PI = 54, DB = 1
N6.C2.D0.R0.S07: RdPtrOffsetTxDq: 06
N0.C2.D0.R0.S15: wrcmd2dqsstartlatency: 04
N2.C3.D0.R0.S05: Total Delay in PI ticks: TxDQ = 919
N4.C2.D1.R0.S09: TxDq : plus1 = 1, minus1 = 0, PI = 19, DB = 0
N6.C2.D0.R0.S08: RdPtrOffsetTxDq: 06
N0.C2.D0.R0.S15: RdPtrOffsetTxDq: 05
N2.C3.D0.R0.S06: Total Delay in PI ticks: TxDQ = 936
N4.C2.D1.R0.S10: TxDqs: plus1 = 1, minus1 = 0, PI = 42, DB = 0
N6.C2.D0.R0.S09: RdPtrOffsetTxDq: 07
N0.C2.D0.R0.S15: RdPtrOffsetTxDqs: 07
N2.C3.D0.R0.S07: Total Delay in PI ticks: TxDQ = 950
N4.C2.D1.R0.S10: TxDq : plus1 = 1, minus1 = 0, PI = 05, DB = 1
N6.C2.D0.R0.S10: RdPtrOffsetTxDq: 07
N0.C2.D0.R0.S15: PiTxDqs: 00
N2.C3.D0.R0.S08: Total Delay in PI ticks: TxDQ = 925
N4.C2.D1.R0.S11: TxDqs: plus1 = 1, minus1 = 0, PI = 30, DB = 0
N6.C2.D0.R0.S11: RdPtrOffsetTxDq: 06
N0.C2.D0.R0.S16: wrcmd2dqsstartlatency: 04
N2.C3.D0.R0.S09: Total Delay in PI ticks: TxDQ = 982
N4.C2.D1.R0.S11: TxDq : plus1 = 1, minus1 = 0, PI = 59, DB = 1
N6.C2.D0.R0.S12: RdPtrOffsetTxDq: 06
N0.C2.D0.R0.S16: RdPtrOffsetTxDq: 05
N2.C3.D0.R0.S10: Total Delay in PI ticks: TxDQ = 970
N4.C2.D1.R0.S12: TxDqs: plus1 = 1, minus1 = 0, PI = 15, DB = 1
N6.C2.D0.R0.S13: RdPtrOffsetTxDq: 05
N0.C2.D0.R0.S16: RdPtrOffsetTxDqs: 07
N2.C3.D0.R0.S11: Total Delay in PI ticks: TxDQ = 957
N4.C2.D1.R0.S12: TxDq : plus1 = 1, minus1 = 0, PI = 44, DB = 0
N6.C2.D0.R0.S14: RdPtrOffsetTxDq: 06
N0.C2.D0.R0.S16: PiTxDqs: 18
N2.C3.D0.R0.S12: Total Delay in PI ticks: TxDQ = 941
N4.C2.D1.R0.S13: TxDqs: plus1 = 1, minus1 = 0, PI = 36, DB = 0
N6.C2.D0.R0.S15: RdPtrOffsetTxDq: 06
N0.C2.D0.R0.S17: wrcmd2dqsstartlatency: 04
N2.C3.D0.R0.S13: Total Delay in PI ticks: TxDQ = 907
N4.C2.D1.R0.S13: TxDq : plus1 = 0, minus1 = 1, PI = 02, DB = 1
N6.C2.D0.R0.S16: RdPtrOffsetTxDq: 06
N0.C2.D0.R0.S17: RdPtrOffsetTxDq: 05
N2.C3.D0.R0.S14: Total Delay in PI ticks: TxDQ = 921
N4.C2.D1.R0.S14: TxDqs: plus1 = 0, minus1 = 1, PI = 00, DB = 1
N6.C2.D0.R0.S17: RdPtrOffsetTxDq: 06
N0.C2.D0.R0.S17: RdPtrOffsetTxDqs: 06
N2.C3.D0.R0.S15: Total Delay in PI ticks: TxDQ = 935
N4.C2.D1.R0.S14: TxDq : plus1 = 1, minus1 = 0, PI = 31, DB = 0
N6.C2.D0.R0.S00: RdPtrOffsetTxDq: 08
N0.C2.D0.R0.S17: PiTxDqs: 56
N2.C3.D0.R0.S16: Total Delay in PI ticks: TxDQ = 950
N4.C2.D1.R0.S15: TxDqs: plus1 = 0, minus1 = 1, PI = 00, DB = 1
N6.C2.D0.R0.S01: RdPtrOffsetTxDq: 08
N0.C2.D0.R0.S00: RdPtrOffsetTxDq: 07
N2.C3.D0.R0.S17: Total Delay in PI ticks: TxDQ = 924
N4.C2.D1.R0.S15: TxDq : plus1 = 1, minus1 = 0, PI = 29, DB = 0
N6.C2.D0.R0.S02: RdPtrOffsetTxDq: 07
N0.C2.D0.R0.S01: RdPtrOffsetTxDq: 07
N2.C3.D0.R1.S00: wrcmd2dqsstartlatency: 04
N4.C2.D1.R0.S16: TxDqs: plus1 = 1, minus1 = 0, PI = 19, DB = 0
N6.C2.D0.R0.S03: RdPtrOffsetTxDq: 07
N0.C2.D0.R0.S02: RdPtrOffsetTxDq: 06
N2.C3.D0.R1.S00: RdPtrOffsetTxDq: 06
N4.C2.D1.R0.S16: TxDq : plus1 = 1, minus1 = 0, PI = 48, DB = 0
N6.C2.D0.R0.S04: RdPtrOffsetTxDq: 07
N0.C2.D0.R0.S03: RdPtrOffsetTxDq: 06
N2.C3.D0.R1.S00: RdPtrOffsetTxDqs: 07
N4.C2.D1.R0.S17: TxDqs: plus1 = 1, minus1 = 0, PI = 51, DB = 1
N6.C2.D0.R0.S05: RdPtrOffsetTxDq: 07
N0.C2.D0.R0.S04: RdPtrOffsetTxDq: 06
N2.C3.D0.R1.S00: PiTxDqs: 49
N4.C2.D1.R0.S17: TxDq : plus1 = 1, minus1 = 0, PI = 17, DB = 0
N6.C2.D0.R0.S06: RdPtrOffsetTxDq: 07
N0.C2.D0.R0.S05: RdPtrOffsetTxDq: 06
N2.C3.D0.R1.S01: wrcmd2dqsstartlatency: 04
N4.C2.D1.R1.S00: TxDqs: plus1 = 1, minus1 = 0, PI = 53, DB = 1
N6.C2.D0.R0.S07: RdPtrOffsetTxDq: 07
N0.C2.D0.R0.S06: RdPtrOffsetTxDq: 06
N2.C3.D0.R1.S01: RdPtrOffsetTxDq: 05
N4.C2.D1.R1.S00: TxDq : plus1 = 1, minus1 = 0, PI = 19, DB = 0
N6.C2.D0.R0.S08: RdPtrOffsetTxDq: 07
N0.C2.D0.R0.S07: RdPtrOffsetTxDq: 06
N2.C3.D0.R1.S01: RdPtrOffsetTxDqs: 07
N4.C2.D1.R1.S01: TxDqs: plus1 = 1, minus1 = 0, PI = 39, DB = 0
N6.C2.D0.R0.S09: RdPtrOffsetTxDq: 08
N0.C2.D0.R0.S08: RdPtrOffsetTxDq: 06
N2.C3.D0.R1.S01: PiTxDqs: 31
N4.C2.D1.R1.S01: TxDq : plus1 = 1, minus1 = 0, PI = 04, DB = 1
N6.C2.D0.R0.S10: RdPtrOffsetTxDq: 08
N0.C2.D0.R0.S09: RdPtrOffsetTxDq: 07
N2.C3.D0.R1.S02: wrcmd2dqsstartlatency: 04
N4.C2.D1.R1.S02: TxDqs: plus1 = 1, minus1 = 0, PI = 30, DB = 0
N6.C2.D0.R0.S11: RdPtrOffsetTxDq: 07
N0.C2.D0.R0.S10: RdPtrOffsetTxDq: 07
N2.C3.D0.R1.S02: RdPtrOffsetTxDq: 05
N4.C2.D1.R1.S02: TxDq : plus1 = 1, minus1 = 0, PI = 59, DB = 1
N6.C2.D0.R0.S12: RdPtrOffsetTxDq: 07
N0.C2.D0.R0.S11: RdPtrOffsetTxDq: 06
N2.C3.D0.R1.S02: RdPtrOffsetTxDqs: 07
N4.C2.D1.R1.S03: TxDqs: plus1 = 1, minus1 = 0, PI = 15, DB = 1
N6.C2.D0.R0.S13: RdPtrOffsetTxDq: 06
N0.C2.D0.R0.S12: RdPtrOffsetTxDq: 06
N2.C3.D0.R1.S02: PiTxDqs: 21
N4.C2.D1.R1.S03: TxDq : plus1 = 1, minus1 = 0, PI = 43, DB = 0
N6.C2.D0.R0.S14: RdPtrOffsetTxDq: 07
N0.C2.D0.R0.S13: RdPtrOffsetTxDq: 06
N2.C3.D0.R1.S03: wrcmd2dqsstartlatency: 04
N4.C2.D1.R1.S04: TxDqs: plus1 = 1, minus1 = 0, PI = 36, DB = 0
N6.C2.D0.R0.S15: RdPtrOffsetTxDq: 07
N0.C2.D0.R0.S14: RdPtrOffsetTxDq: 06
N2.C3.D0.R1.S03: RdPtrOffsetTxDq: 05
N4.C2.D1.R1.S04: TxDq : plus1 = 0, minus1 = 1, PI = 03, DB = 1
N6.C2.D0.R0.S16: RdPtrOffsetTxDq: 07
N0.C2.D0.R0.S15: RdPtrOffsetTxDq: 06
N2.C3.D0.R1.S03: RdPtrOffsetTxDqs: 07
N4.C2.D1.R1.S05: TxDqs: plus1 = 0, minus1 = 1, PI = 01, DB = 1
N6.C2.D0.R0.S17: RdPtrOffsetTxDq: 07
N0.C2.D0.R0.S16: RdPtrOffsetTxDq: 06
N2.C3.D0.R1.S03: PiTxDqs: 06
N4.C2.D1.R1.S05: TxDq : plus1 = 1, minus1 = 0, PI = 31, DB = 0
N6.C2.D0.R0.S00: Total Delay in PI ticks: TxDQ = 976
N0.C2.D0.R0.S17: RdPtrOffsetTxDq: 06
N2.C3.D0.R1.S04: wrcmd2dqsstartlatency: 04
N4.C2.D1.R1.S06: TxDqs: plus1 = 1, minus1 = 0, PI = 62, DB = 1
N6.C2.D0.R0.S01: Total Delay in PI ticks: TxDQ = 963
N0.C2.D0.R0.S00: RdPtrOffsetTxDq: 08
N2.C3.D0.R1.S04: RdPtrOffsetTxDq: 05
N4.C2.D1.R1.S06: TxDq : plus1 = 1, minus1 = 0, PI = 27, DB = 0
N6.C2.D0.R0.S02: Total Delay in PI ticks: TxDQ = 953
N0.C2.D0.R0.S01: RdPtrOffsetTxDq: 08
N2.C3.D0.R1.S04: RdPtrOffsetTxDqs: 06
N4.C2.D1.R1.S07: TxDqs: plus1 = 1, minus1 = 0, PI = 18, DB = 0
N6.C2.D0.R0.S03: Total Delay in PI ticks: TxDQ = 932
N0.C2.D0.R0.S02: RdPtrOffsetTxDq: 07
N2.C3.D0.R1.S04: PiTxDqs: 36
N4.C2.D1.R1.S07: TxDq : plus1 = 1, minus1 = 0, PI = 47, DB = 0
N6.C2.D0.R0.S04: Total Delay in PI ticks: TxDQ = 894
N0.C2.D0.R0.S03: RdPtrOffsetTxDq: 07
N2.C3.D0.R1.S05: wrcmd2dqsstartlatency: 04
N4.C2.D1.R1.S08: TxDqs: plus1 = 1, minus1 = 0, PI = 52, DB = 1
N6.C2.D0.R0.S05: Total Delay in PI ticks: TxDQ = 922
N0.C2.D0.R0.S04: RdPtrOffsetTxDq: 07
N2.C3.D0.R1.S05: RdPtrOffsetTxDq: 05
N4.C2.D1.R1.S08: TxDq : plus1 = 1, minus1 = 0, PI = 18, DB = 0
N6.C2.D0.R0.S06: Total Delay in PI ticks: TxDQ = 925
N0.C2.D0.R0.S05: RdPtrOffsetTxDq: 07
N2.C3.D0.R1.S05: RdPtrOffsetTxDqs: 06
N4.C2.D1.R1.S09: TxDqs: plus1 = 1, minus1 = 0, PI = 54, DB = 1
N6.C2.D0.R0.S07: Total Delay in PI ticks: TxDQ = 940
N0.C2.D0.R0.S06: RdPtrOffsetTxDq: 07
N2.C3.D0.R1.S05: PiTxDqs: 49
N4.C2.D1.R1.S09: TxDq : plus1 = 1, minus1 = 0, PI = 19, DB = 0
N6.C2.D0.R0.S08: Total Delay in PI ticks: TxDQ = 913
N0.C2.D0.R0.S07: RdPtrOffsetTxDq: 07
N2.C3.D0.R1.S06: wrcmd2dqsstartlatency: 04
N4.C2.D1.R1.S10: TxDqs: plus1 = 1, minus1 = 0, PI = 42, DB = 0
N6.C2.D0.R0.S09: Total Delay in PI ticks: TxDQ = 977
N0.C2.D0.R0.S08: RdPtrOffsetTxDq: 07
N2.C3.D0.R1.S06: RdPtrOffsetTxDq: 05
N4.C2.D1.R1.S10: TxDq : plus1 = 1, minus1 = 0, PI = 05, DB = 1
N6.C2.D0.R0.S10: Total Delay in PI ticks: TxDQ = 964
N0.C2.D0.R0.S09: RdPtrOffsetTxDq: 08
N2.C3.D0.R1.S06: RdPtrOffsetTxDqs: 07
N4.C2.D1.R1.S11: TxDqs: plus1 = 1, minus1 = 0, PI = 30, DB = 0
N6.C2.D0.R0.S11: Total Delay in PI ticks: TxDQ = 955
N0.C2.D0.R0.S10: RdPtrOffsetTxDq: 08
N2.C3.D0.R1.S06: PiTxDqs: 00
N4.C2.D1.R1.S11: TxDq : plus1 = 1, minus1 = 0, PI = 59, DB = 1
N6.C2.D0.R0.S12: Total Delay in PI ticks: TxDQ = 932
N0.C2.D0.R0.S11: RdPtrOffsetTxDq: 07
N2.C3.D0.R1.S07: wrcmd2dqsstartlatency: 04
N4.C2.D1.R1.S12: TxDqs: plus1 = 1, minus1 = 0, PI = 15, DB = 1
N6.C2.D0.R0.S13: Total Delay in PI ticks: TxDQ = 894
N0.C2.D0.R0.S12: RdPtrOffsetTxDq: 07
N2.C3.D0.R1.S07: RdPtrOffsetTxDq: 05
N4.C2.D1.R1.S12: TxDq : plus1 = 1, minus1 = 0, PI = 44, DB = 0
N6.C2.D0.R0.S14: Total Delay in PI ticks: TxDQ = 922
N0.C2.D0.R0.S13: RdPtrOffsetTxDq: 07
N2.C3.D0.R1.S07: RdPtrOffsetTxDqs: 07
N4.C2.D1.R1.S13: TxDqs: plus1 = 1, minus1 = 0, PI = 36, DB = 0
N6.C2.D0.R0.S15: Total Delay in PI ticks: TxDQ = 924
N0.C2.D0.R0.S14: RdPtrOffsetTxDq: 07
N2.C3.D0.R1.S07: PiTxDqs: 16
N4.C2.D1.R1.S13: TxDq : plus1 = 0, minus1 = 1, PI = 02, DB = 1
N6.C2.D0.R0.S16: Total Delay in PI ticks: TxDQ = 942
N0.C2.D0.R0.S15: RdPtrOffsetTxDq: 07
N2.C3.D0.R1.S08: wrcmd2dqsstartlatency: 04
N4.C2.D1.R1.S14: TxDqs: plus1 = 0, minus1 = 1, PI = 00, DB = 1
N6.C2.D0.R0.S17: Total Delay in PI ticks: TxDQ = 911
N0.C2.D0.R0.S16: RdPtrOffsetTxDq: 07
N2.C3.D0.R1.S08: RdPtrOffsetTxDq: 05
N4.C2.D1.R1.S14: TxDq : plus1 = 1, minus1 = 0, PI = 31, DB = 0
N6.C2.D0.R1.S00: wrcmd2dqsstartlatency: 04
N0.C2.D0.R0.S17: RdPtrOffsetTxDq: 07
N2.C3.D0.R1.S08: RdPtrOffsetTxDqs: 06
N4.C2.D1.R1.S15: TxDqs: plus1 = 0, minus1 = 1, PI = 00, DB = 1
N6.C2.D0.R1.S00: RdPtrOffsetTxDq: 06
N0.C2.D0.R0.S00: Total Delay in PI ticks: TxDQ = 983
N2.C3.D0.R1.S08: PiTxDqs: 53
N4.C2.D1.R1.S15: TxDq : plus1 = 1, minus1 = 0, PI = 29, DB = 0
N6.C2.D0.R1.S00: RdPtrOffsetTxDqs: 07
N0.C2.D0.R0.S01: Total Delay in PI ticks: TxDQ = 965
N2.C3.D0.R1.S09: wrcmd2dqsstartlatency: 04
N4.C2.D1.R1.S16: TxDqs: plus1 = 1, minus1 = 0, PI = 19, DB = 0
N6.C2.D0.R1.S00: PiTxDqs: 42
N0.C2.D0.R0.S02: Total Delay in PI ticks: TxDQ = 956
N2.C3.D0.R1.S09: RdPtrOffsetTxDq: 06
N4.C2.D1.R1.S16: TxDq : plus1 = 1, minus1 = 0, PI = 48, DB = 0
N6.C2.D0.R1.S01: wrcmd2dqsstartlatency: 04
N0.C2.D0.R0.S03: Total Delay in PI ticks: TxDQ = 936
N2.C3.D0.R1.S09: RdPtrOffsetTxDqs: 07
N4.C2.D1.R1.S17: TxDqs: plus1 = 1, minus1 = 0, PI = 51, DB = 1
N6.C2.D0.R1.S01: RdPtrOffsetTxDq: 05
N0.C2.D0.R0.S04: Total Delay in PI ticks: TxDQ = 901
N2.C3.D0.R1.S09: PiTxDqs: 47
N4.C2.D1.R1.S17: TxDq : plus1 = 1, minus1 = 0, PI = 17, DB = 0
N6.C2.D0.R1.S01: RdPtrOffsetTxDqs: 07
N0.C2.D0.R0.S05: Total Delay in PI ticks: TxDQ = 924
N2.C3.D0.R1.S10: wrcmd2dqsstartlatency: 04
END_DATA_TX_DQ
N6.C2.D0.R1.S01: PiTxDqs: 27
N0.C2.D0.R0.S06: Total Delay in PI ticks: TxDQ = 926
N2.C3.D0.R1.S10: RdPtrOffsetTxDq: 05
N4.C3.D0.R0.S00: wrcmd2dqsstartlatency: 04
N6.C2.D0.R1.S02: wrcmd2dqsstartlatency: 04
N0.C2.D0.R0.S07: Total Delay in PI ticks: TxDQ = 945
N2.C3.D0.R1.S10: RdPtrOffsetTxDqs: 07
N4.C3.D0.R0.S00: RdPtrOffsetTxDq: 06
N6.C2.D0.R1.S02: RdPtrOffsetTxDq: 05
N0.C2.D0.R0.S08: Total Delay in PI ticks: TxDQ = 919
N2.C3.D0.R1.S10: PiTxDqs: 32
N4.C3.D0.R0.S00: RdPtrOffsetTxDqs: 08
N6.C2.D0.R1.S02: RdPtrOffsetTxDqs: 07
N0.C2.D0.R0.S09: Total Delay in PI ticks: TxDQ = 982
N2.C3.D0.R1.S11: wrcmd2dqsstartlatency: 04
N4.C3.D0.R0.S00: PiTxDqs: 01
N6.C2.D0.R1.S02: PiTxDqs: 16
N0.C2.D0.R0.S10: Total Delay in PI ticks: TxDQ = 966
N2.C3.D0.R1.S11: RdPtrOffsetTxDq: 05
N4.C3.D0.R0.S01: wrcmd2dqsstartlatency: 04
N6.C2.D0.R1.S03: wrcmd2dqsstartlatency: 04
N0.C2.D0.R0.S11: Total Delay in PI ticks: TxDQ = 957
N2.C3.D0.R1.S11: RdPtrOffsetTxDqs: 07
N4.C3.D0.R0.S01: RdPtrOffsetTxDq: 06
N6.C2.D0.R1.S03: RdPtrOffsetTxDq: 05
N0.C2.D0.R0.S12: Total Delay in PI ticks: TxDQ = 935
N2.C3.D0.R1.S11: PiTxDqs: 22
N4.C3.D0.R0.S01: RdPtrOffsetTxDqs: 07
N6.C2.D0.R1.S03: RdPtrOffsetTxDqs: 06
N0.C2.D0.R0.S13: Total Delay in PI ticks: TxDQ = 898
N2.C3.D0.R1.S12: wrcmd2dqsstartlatency: 04
N4.C3.D0.R0.S01: PiTxDqs: 48
N6.C2.D0.R1.S03: PiTxDqs: 63
N0.C2.D0.R0.S14: Total Delay in PI ticks: TxDQ = 926
N2.C3.D0.R1.S12: RdPtrOffsetTxDq: 05
N4.C3.D0.R0.S02: wrcmd2dqsstartlatency: 04
N6.C2.D0.R1.S04: wrcmd2dqsstartlatency: 04
N0.C2.D0.R0.S15: Total Delay in PI ticks: TxDQ = 927
N2.C3.D0.R1.S12: RdPtrOffsetTxDqs: 07
N4.C3.D0.R0.S02: RdPtrOffsetTxDq: 06
N6.C2.D0.R1.S04: RdPtrOffsetTxDq: 04
N0.C2.D0.R0.S16: Total Delay in PI ticks: TxDQ = 942
N2.C3.D0.R1.S12: PiTxDqs: 08
N4.C3.D0.R0.S02: RdPtrOffsetTxDqs: 07
N6.C2.D0.R1.S04: RdPtrOffsetTxDqs: 06
N0.C2.D0.R0.S17: Total Delay in PI ticks: TxDQ = 918
N2.C3.D0.R1.S13: wrcmd2dqsstartlatency: 04
N4.C3.D0.R0.S02: PiTxDqs: 38
N6.C2.D0.R1.S04: PiTxDqs: 23
N0.C2.D0.R1.S00: wrcmd2dqsstartlatency: 04
N2.C3.D0.R1.S13: RdPtrOffsetTxDq: 05
N4.C3.D0.R0.S03: wrcmd2dqsstartlatency: 04
N6.C2.D0.R1.S05: wrcmd2dqsstartlatency: 04
N0.C2.D0.R1.S00: RdPtrOffsetTxDq: 06
N2.C3.D0.R1.S13: RdPtrOffsetTxDqs: 06
N4.C3.D0.R0.S03: RdPtrOffsetTxDq: 05
N6.C2.D0.R1.S05: RdPtrOffsetTxDq: 05
N0.C2.D0.R1.S00: RdPtrOffsetTxDqs: 07
N2.C3.D0.R1.S13: PiTxDqs: 36
N4.C3.D0.R0.S03: RdPtrOffsetTxDqs: 07
N6.C2.D0.R1.S05: RdPtrOffsetTxDqs: 06
N0.C2.D0.R1.S00: PiTxDqs: 47
N2.C3.D0.R1.S14: wrcmd2dqsstartlatency: 04
N4.C3.D0.R0.S03: PiTxDqs: 22
N6.C2.D0.R1.S05: PiTxDqs: 53
N0.C2.D0.R1.S01: wrcmd2dqsstartlatency: 04
N2.C3.D0.R1.S14: RdPtrOffsetTxDq: 05
N4.C3.D0.R0.S04: wrcmd2dqsstartlatency: 04
N6.C2.D0.R1.S06: wrcmd2dqsstartlatency: 04
N0.C2.D0.R1.S01: RdPtrOffsetTxDq: 05
N2.C3.D0.R1.S14: RdPtrOffsetTxDqs: 06
N4.C3.D0.R0.S04: RdPtrOffsetTxDq: 05
N6.C2.D0.R1.S06: RdPtrOffsetTxDq: 05
N0.C2.D0.R1.S01: RdPtrOffsetTxDqs: 07
N2.C3.D0.R1.S14: PiTxDqs: 50
N4.C3.D0.R0.S04: RdPtrOffsetTxDqs: 06
N6.C2.D0.R1.S06: RdPtrOffsetTxDqs: 06
N0.C2.D0.R1.S01: PiTxDqs: 34
N2.C3.D0.R1.S15: wrcmd2dqsstartlatency: 04
N4.C3.D0.R0.S04: PiTxDqs: 50
N6.C2.D0.R1.S06: PiTxDqs: 51
N0.C2.D0.R1.S02: wrcmd2dqsstartlatency: 04
N2.C3.D0.R1.S15: RdPtrOffsetTxDq: 05
N4.C3.D0.R0.S05: wrcmd2dqsstartlatency: 04
N6.C2.D0.R1.S07: wrcmd2dqsstartlatency: 04
N0.C2.D0.R1.S02: RdPtrOffsetTxDq: 05
N2.C3.D0.R1.S15: RdPtrOffsetTxDqs: 07
N4.C3.D0.R0.S05: RdPtrOffsetTxDq: 05
N6.C2.D0.R1.S07: RdPtrOffsetTxDq: 05
N0.C2.D0.R1.S02: RdPtrOffsetTxDqs: 07
N2.C3.D0.R1.S15: PiTxDqs: 00
N4.C3.D0.R0.S05: RdPtrOffsetTxDqs: 07
N6.C2.D0.R1.S07: RdPtrOffsetTxDqs: 07
N0.C2.D0.R1.S02: PiTxDqs: 24
N2.C3.D0.R1.S16: wrcmd2dqsstartlatency: 04
N4.C3.D0.R0.S05: PiTxDqs: 01
N6.C2.D0.R1.S07: PiTxDqs: 09
N0.C2.D0.R1.S03: wrcmd2dqsstartlatency: 04
N2.C3.D0.R1.S16: RdPtrOffsetTxDq: 05
N4.C3.D0.R0.S06: wrcmd2dqsstartlatency: 04
N6.C2.D0.R1.S08: wrcmd2dqsstartlatency: 04
N0.C2.D0.R1.S03: RdPtrOffsetTxDq: 05
N2.C3.D0.R1.S16: RdPtrOffsetTxDqs: 07
N4.C3.D0.R0.S06: RdPtrOffsetTxDq: 05
N6.C2.D0.R1.S08: RdPtrOffsetTxDq: 05
N0.C2.D0.R1.S03: RdPtrOffsetTxDqs: 07
N2.C3.D0.R1.S16: PiTxDqs: 18
N4.C3.D0.R0.S06: RdPtrOffsetTxDqs: 07
N6.C2.D0.R1.S08: RdPtrOffsetTxDqs: 06
N0.C2.D0.R1.S03: PiTxDqs: 06
N2.C3.D0.R1.S17: wrcmd2dqsstartlatency: 04
N4.C3.D0.R0.S06: PiTxDqs: 16
N6.C2.D0.R1.S08: PiTxDqs: 41
N0.C2.D0.R1.S04: wrcmd2dqsstartlatency: 04
N2.C3.D0.R1.S17: RdPtrOffsetTxDq: 05
N4.C3.D0.R0.S07: wrcmd2dqsstartlatency: 04
N6.C2.D0.R1.S09: wrcmd2dqsstartlatency: 04
N0.C2.D0.R1.S04: RdPtrOffsetTxDq: 04
N2.C3.D0.R1.S17: RdPtrOffsetTxDqs: 06
N4.C3.D0.R0.S07: RdPtrOffsetTxDq: 05
N6.C2.D0.R1.S09: RdPtrOffsetTxDq: 06
N0.C2.D0.R1.S04: RdPtrOffsetTxDqs: 06
N2.C3.D0.R1.S17: PiTxDqs: 53
N4.C3.D0.R0.S07: RdPtrOffsetTxDqs: 07
N6.C2.D0.R1.S09: RdPtrOffsetTxDqs: 07
N0.C2.D0.R1.S04: PiTxDqs: 31
N2.C3.D0.R1.S00: RdPtrOffsetTxDq: 07
N4.C3.D0.R0.S07: PiTxDqs: 30
N6.C2.D0.R1.S09: PiTxDqs: 39
N0.C2.D0.R1.S05: wrcmd2dqsstartlatency: 04
N2.C3.D0.R1.S01: RdPtrOffsetTxDq: 06
N4.C3.D0.R0.S08: wrcmd2dqsstartlatency: 04
N6.C2.D0.R1.S10: wrcmd2dqsstartlatency: 04
N0.C2.D0.R1.S05: RdPtrOffsetTxDq: 05
N2.C3.D0.R1.S02: RdPtrOffsetTxDq: 06
N4.C3.D0.R0.S08: RdPtrOffsetTxDq: 05
N6.C2.D0.R1.S10: RdPtrOffsetTxDq: 05
N0.C2.D0.R1.S05: RdPtrOffsetTxDqs: 06
N2.C3.D0.R1.S03: RdPtrOffsetTxDq: 06
N4.C3.D0.R0.S08: RdPtrOffsetTxDqs: 07
N6.C2.D0.R1.S10: RdPtrOffsetTxDqs: 07
N0.C2.D0.R1.S05: PiTxDqs: 60
N2.C3.D0.R1.S04: RdPtrOffsetTxDq: 06
N4.C3.D0.R0.S08: PiTxDqs: 06
N6.C2.D0.R1.S10: PiTxDqs: 27
N0.C2.D0.R1.S06: wrcmd2dqsstartlatency: 04
N2.C3.D0.R1.S05: RdPtrOffsetTxDq: 06
N4.C3.D0.R0.S09: wrcmd2dqsstartlatency: 04
N6.C2.D0.R1.S11: wrcmd2dqsstartlatency: 04
N0.C2.D0.R1.S06: RdPtrOffsetTxDq: 05
N2.C3.D0.R1.S06: RdPtrOffsetTxDq: 06
N4.C3.D0.R0.S09: RdPtrOffsetTxDq: 06
N6.C2.D0.R1.S11: RdPtrOffsetTxDq: 05
N0.C2.D0.R1.S06: RdPtrOffsetTxDqs: 06
N2.C3.D0.R1.S07: RdPtrOffsetTxDq: 06
N4.C3.D0.R0.S09: RdPtrOffsetTxDqs: 08
N6.C2.D0.R1.S11: RdPtrOffsetTxDqs: 07
N0.C2.D0.R1.S06: PiTxDqs: 55
N2.C3.D0.R1.S08: RdPtrOffsetTxDq: 06
N4.C3.D0.R0.S09: PiTxDqs: 01
N6.C2.D0.R1.S11: PiTxDqs: 17
N0.C2.D0.R1.S07: wrcmd2dqsstartlatency: 04
N2.C3.D0.R1.S09: RdPtrOffsetTxDq: 07
N4.C3.D0.R0.S10: wrcmd2dqsstartlatency: 04
N6.C2.D0.R1.S12: wrcmd2dqsstartlatency: 04
N0.C2.D0.R1.S07: RdPtrOffsetTxDq: 05
N2.C3.D0.R1.S10: RdPtrOffsetTxDq: 06
N4.C3.D0.R0.S10: RdPtrOffsetTxDq: 06
N6.C2.D0.R1.S12: RdPtrOffsetTxDq: 05
N0.C2.D0.R1.S07: RdPtrOffsetTxDqs: 07
N2.C3.D0.R1.S11: RdPtrOffsetTxDq: 06
N4.C3.D0.R0.S10: RdPtrOffsetTxDqs: 07
N6.C2.D0.R1.S12: RdPtrOffsetTxDqs: 07
N0.C2.D0.R1.S07: PiTxDqs: 14
N2.C3.D0.R1.S12: RdPtrOffsetTxDq: 06
N4.C3.D0.R0.S10: PiTxDqs: 47
N6.C2.D0.R1.S12: PiTxDqs: 02
N0.C2.D0.R1.S08: wrcmd2dqsstartlatency: 04
N2.C3.D0.R1.S13: RdPtrOffsetTxDq: 06
N4.C3.D0.R0.S11: wrcmd2dqsstartlatency: 04
N6.C2.D0.R1.S13: wrcmd2dqsstartlatency: 04
N0.C2.D0.R1.S08: RdPtrOffsetTxDq: 05
N2.C3.D0.R1.S14: RdPtrOffsetTxDq: 06
N4.C3.D0.R0.S11: RdPtrOffsetTxDq: 06
N6.C2.D0.R1.S13: RdPtrOffsetTxDq: 04
N0.C2.D0.R1.S08: RdPtrOffsetTxDqs: 06
N2.C3.D0.R1.S15: RdPtrOffsetTxDq: 06
N4.C3.D0.R0.S11: RdPtrOffsetTxDqs: 07
N6.C2.D0.R1.S13: RdPtrOffsetTxDqs: 06
N0.C2.D0.R1.S08: PiTxDqs: 48
N2.C3.D0.R1.S16: RdPtrOffsetTxDq: 06
N4.C3.D0.R0.S11: PiTxDqs: 36
N6.C2.D0.R1.S13: PiTxDqs: 23
N0.C2.D0.R1.S09: wrcmd2dqsstartlatency: 04
N2.C3.D0.R1.S17: RdPtrOffsetTxDq: 06
N4.C3.D0.R0.S12: wrcmd2dqsstartlatency: 04
N6.C2.D0.R1.S14: wrcmd2dqsstartlatency: 04
N0.C2.D0.R1.S09: RdPtrOffsetTxDq: 06
N2.C3.D0.R1.S00: RdPtrOffsetTxDq: 08
N4.C3.D0.R0.S12: RdPtrOffsetTxDq: 05
N6.C2.D0.R1.S14: RdPtrOffsetTxDq: 05
N0.C2.D0.R1.S09: RdPtrOffsetTxDqs: 07
N2.C3.D0.R1.S01: RdPtrOffsetTxDq: 07
N4.C3.D0.R0.S12: RdPtrOffsetTxDqs: 07
N6.C2.D0.R1.S14: RdPtrOffsetTxDqs: 06
N0.C2.D0.R1.S09: PiTxDqs: 49
N2.C3.D0.R1.S02: RdPtrOffsetTxDq: 07
N4.C3.D0.R0.S12: PiTxDqs: 24
N6.C2.D0.R1.S14: PiTxDqs: 53
N0.C2.D0.R1.S10: wrcmd2dqsstartlatency: 04
N2.C3.D0.R1.S03: RdPtrOffsetTxDq: 07
N4.C3.D0.R0.S13: wrcmd2dqsstartlatency: 04
N6.C2.D0.R1.S15: wrcmd2dqsstartlatency: 04
N0.C2.D0.R1.S10: RdPtrOffsetTxDq: 06
N2.C3.D0.R1.S04: RdPtrOffsetTxDq: 07
N4.C3.D0.R0.S13: RdPtrOffsetTxDq: 05
N6.C2.D0.R1.S15: RdPtrOffsetTxDq: 05
N0.C2.D0.R1.S10: RdPtrOffsetTxDqs: 07
N2.C3.D0.R1.S05: RdPtrOffsetTxDq: 07
N4.C3.D0.R0.S13: RdPtrOffsetTxDqs: 06
N6.C2.D0.R1.S15: RdPtrOffsetTxDqs: 06
N0.C2.D0.R1.S10: PiTxDqs: 35
N2.C3.D0.R1.S06: RdPtrOffsetTxDq: 07
N4.C3.D0.R0.S13: PiTxDqs: 51
N6.C2.D0.R1.S15: PiTxDqs: 53
N0.C2.D0.R1.S11: wrcmd2dqsstartlatency: 04
N2.C3.D0.R1.S07: RdPtrOffsetTxDq: 07
N4.C3.D0.R0.S14: wrcmd2dqsstartlatency: 04
N6.C2.D0.R1.S16: wrcmd2dqsstartlatency: 04
N0.C2.D0.R1.S11: RdPtrOffsetTxDq: 05
N2.C3.D0.R1.S08: RdPtrOffsetTxDq: 07
N4.C3.D0.R0.S14: RdPtrOffsetTxDq: 05
N6.C2.D0.R1.S16: RdPtrOffsetTxDq: 05
N0.C2.D0.R1.S11: RdPtrOffsetTxDqs: 07
N2.C3.D0.R1.S09: RdPtrOffsetTxDq: 08
N4.C3.D0.R0.S14: RdPtrOffsetTxDqs: 07
N6.C2.D0.R1.S16: RdPtrOffsetTxDqs: 07
N0.C2.D0.R1.S11: PiTxDqs: 23
N2.C3.D0.R1.S10: RdPtrOffsetTxDq: 07
N4.C3.D0.R0.S14: PiTxDqs: 00
N6.C2.D0.R1.S16: PiTxDqs: 09
N0.C2.D0.R1.S12: wrcmd2dqsstartlatency: 04
N2.C3.D0.R1.S11: RdPtrOffsetTxDq: 07
N4.C3.D0.R0.S15: wrcmd2dqsstartlatency: 04
N6.C2.D0.R1.S17: wrcmd2dqsstartlatency: 04
N0.C2.D0.R1.S12: RdPtrOffsetTxDq: 05
N2.C3.D0.R1.S12: RdPtrOffsetTxDq: 07
N4.C3.D0.R0.S15: RdPtrOffsetTxDq: 05
N6.C2.D0.R1.S17: RdPtrOffsetTxDq: 05
N0.C2.D0.R1.S12: RdPtrOffsetTxDqs: 07
N2.C3.D0.R1.S13: RdPtrOffsetTxDq: 07
N4.C3.D0.R0.S15: RdPtrOffsetTxDqs: 07
N6.C2.D0.R1.S17: RdPtrOffsetTxDqs: 06
N0.C2.D0.R1.S12: PiTxDqs: 06
N2.C3.D0.R1.S14: RdPtrOffsetTxDq: 07
N4.C3.D0.R0.S15: PiTxDqs: 17
N6.C2.D0.R1.S17: PiTxDqs: 41
N0.C2.D0.R1.S13: wrcmd2dqsstartlatency: 04
N2.C3.D0.R1.S15: RdPtrOffsetTxDq: 07
N4.C3.D0.R0.S16: wrcmd2dqsstartlatency: 04
N6.C2.D0.R1.S00: RdPtrOffsetTxDq: 07
N0.C2.D0.R1.S13: RdPtrOffsetTxDq: 04
N2.C3.D0.R1.S16: RdPtrOffsetTxDq: 07
N4.C3.D0.R0.S16: RdPtrOffsetTxDq: 05
N6.C2.D0.R1.S01: RdPtrOffsetTxDq: 06
N0.C2.D0.R1.S13: RdPtrOffsetTxDqs: 06
N2.C3.D0.R1.S17: RdPtrOffsetTxDq: 07
N4.C3.D0.R0.S16: RdPtrOffsetTxDqs: 07
N6.C2.D0.R1.S02: RdPtrOffsetTxDq: 06
N0.C2.D0.R1.S13: PiTxDqs: 30
N2.C3.D0.R1.S00: Total Delay in PI ticks: TxDQ = 975
N4.C3.D0.R0.S16: PiTxDqs: 30
N6.C2.D0.R1.S03: RdPtrOffsetTxDq: 06
N0.C2.D0.R1.S14: wrcmd2dqsstartlatency: 04
N2.C3.D0.R1.S01: Total Delay in PI ticks: TxDQ = 959
N4.C3.D0.R0.S17: wrcmd2dqsstartlatency: 04
N6.C2.D0.R1.S04: RdPtrOffsetTxDq: 05
N0.C2.D0.R1.S14: RdPtrOffsetTxDq: 05
N2.C3.D0.R1.S02: Total Delay in PI ticks: TxDQ = 949
N4.C3.D0.R0.S17: RdPtrOffsetTxDq: 05
N6.C2.D0.R1.S05: RdPtrOffsetTxDq: 06
N0.C2.D0.R1.S14: RdPtrOffsetTxDqs: 06
N2.C3.D0.R1.S03: Total Delay in PI ticks: TxDQ = 933
N4.C3.D0.R0.S17: RdPtrOffsetTxDqs: 07
N6.C2.D0.R1.S06: RdPtrOffsetTxDq: 06
N0.C2.D0.R1.S14: PiTxDqs: 56
N2.C3.D0.R1.S04: Total Delay in PI ticks: TxDQ = 900
N4.C3.D0.R0.S17: PiTxDqs: 02
N6.C2.D0.R1.S07: RdPtrOffsetTxDq: 06
N0.C2.D0.R1.S15: wrcmd2dqsstartlatency: 04
N2.C3.D0.R1.S05: Total Delay in PI ticks: TxDQ = 913
N4.C3.D0.R0.S00: RdPtrOffsetTxDq: 07
N6.C2.D0.R1.S08: RdPtrOffsetTxDq: 06
N0.C2.D0.R1.S15: RdPtrOffsetTxDq: 05
N2.C3.D0.R1.S06: Total Delay in PI ticks: TxDQ = 929
N4.C3.D0.R0.S01: RdPtrOffsetTxDq: 07
N6.C2.D0.R1.S09: RdPtrOffsetTxDq: 07
N0.C2.D0.R1.S15: RdPtrOffsetTxDqs: 06
N2.C3.D0.R1.S07: Total Delay in PI ticks: TxDQ = 943
N4.C3.D0.R0.S02: RdPtrOffsetTxDq: 07
N6.C2.D0.R1.S10: RdPtrOffsetTxDq: 06
N0.C2.D0.R1.S15: PiTxDqs: 56
N2.C3.D0.R1.S08: Total Delay in PI ticks: TxDQ = 917
N4.C3.D0.R0.S03: RdPtrOffsetTxDq: 06
N6.C2.D0.R1.S11: RdPtrOffsetTxDq: 06
N0.C2.D0.R1.S16: wrcmd2dqsstartlatency: 04
N2.C3.D0.R1.S09: Total Delay in PI ticks: TxDQ = 974
N4.C3.D0.R0.S04: RdPtrOffsetTxDq: 06
N6.C2.D0.R1.S12: RdPtrOffsetTxDq: 06
N0.C2.D0.R1.S16: RdPtrOffsetTxDq: 05
N2.C3.D0.R1.S10: Total Delay in PI ticks: TxDQ = 960
N4.C3.D0.R0.S05: RdPtrOffsetTxDq: 06
N6.C2.D0.R1.S13: RdPtrOffsetTxDq: 05
N0.C2.D0.R1.S16: RdPtrOffsetTxDqs: 07
N2.C3.D0.R1.S11: Total Delay in PI ticks: TxDQ = 951
N4.C3.D0.R0.S06: RdPtrOffsetTxDq: 06
N6.C2.D0.R1.S14: RdPtrOffsetTxDq: 06
N0.C2.D0.R1.S16: PiTxDqs: 16
N2.C3.D0.R1.S12: Total Delay in PI ticks: TxDQ = 935
N4.C3.D0.R0.S07: RdPtrOffsetTxDq: 06
N6.C2.D0.R1.S15: RdPtrOffsetTxDq: 06
N0.C2.D0.R1.S17: wrcmd2dqsstartlatency: 04
N2.C3.D0.R1.S13: Total Delay in PI ticks: TxDQ = 900
N4.C3.D0.R0.S08: RdPtrOffsetTxDq: 06
N6.C2.D0.R1.S16: RdPtrOffsetTxDq: 06
N0.C2.D0.R1.S17: RdPtrOffsetTxDq: 05
N2.C3.D0.R1.S14: Total Delay in PI ticks: TxDQ = 915
N4.C3.D0.R0.S09: RdPtrOffsetTxDq: 07
N6.C2.D0.R1.S17: RdPtrOffsetTxDq: 06
N0.C2.D0.R1.S17: RdPtrOffsetTxDqs: 06
N2.C3.D0.R1.S15: Total Delay in PI ticks: TxDQ = 929
N4.C3.D0.R0.S10: RdPtrOffsetTxDq: 07
N6.C2.D0.R1.S00: RdPtrOffsetTxDq: 08
N0.C2.D0.R1.S17: PiTxDqs: 46
N2.C3.D0.R1.S16: Total Delay in PI ticks: TxDQ = 946
N4.C3.D0.R0.S11: RdPtrOffsetTxDq: 07
N6.C2.D0.R1.S01: RdPtrOffsetTxDq: 07
N0.C2.D0.R1.S00: RdPtrOffsetTxDq: 07
N2.C3.D0.R1.S17: Total Delay in PI ticks: TxDQ = 917
N4.C3.D0.R0.S12: RdPtrOffsetTxDq: 06
N6.C2.D0.R1.S02: RdPtrOffsetTxDq: 07
N0.C2.D0.R1.S01: RdPtrOffsetTxDq: 06
N2.C3.D1.R0.S00: wrcmd2dqsstartlatency: 04
N4.C3.D0.R0.S13: RdPtrOffsetTxDq: 06
N6.C2.D0.R1.S03: RdPtrOffsetTxDq: 07
N0.C2.D0.R1.S02: RdPtrOffsetTxDq: 06
N2.C3.D1.R0.S00: RdPtrOffsetTxDq: 06
N4.C3.D0.R0.S14: RdPtrOffsetTxDq: 06
N6.C2.D0.R1.S04: RdPtrOffsetTxDq: 06
N0.C2.D0.R1.S03: RdPtrOffsetTxDq: 06
N2.C3.D1.R0.S00: RdPtrOffsetTxDqs: 07
N4.C3.D0.R0.S15: RdPtrOffsetTxDq: 06
N6.C2.D0.R1.S05: RdPtrOffsetTxDq: 07
N0.C2.D0.R1.S04: RdPtrOffsetTxDq: 05
N2.C3.D1.R0.S00: PiTxDqs: 60
N4.C3.D0.R0.S16: RdPtrOffsetTxDq: 06
N6.C2.D0.R1.S06: RdPtrOffsetTxDq: 07
N0.C2.D0.R1.S05: RdPtrOffsetTxDq: 06
N2.C3.D1.R0.S01: wrcmd2dqsstartlatency: 04
N4.C3.D0.R0.S17: RdPtrOffsetTxDq: 06
N6.C2.D0.R1.S07: RdPtrOffsetTxDq: 07
N0.C2.D0.R1.S06: RdPtrOffsetTxDq: 06
N2.C3.D1.R0.S01: RdPtrOffsetTxDq: 06
N4.C3.D0.R0.S00: RdPtrOffsetTxDq: 08
N6.C2.D0.R1.S08: RdPtrOffsetTxDq: 07
N0.C2.D0.R1.S07: RdPtrOffsetTxDq: 06
N2.C3.D1.R0.S01: RdPtrOffsetTxDqs: 07
N4.C3.D0.R0.S01: RdPtrOffsetTxDq: 08
N6.C2.D0.R1.S09: RdPtrOffsetTxDq: 08
N0.C2.D0.R1.S08: RdPtrOffsetTxDq: 06
N2.C3.D1.R0.S01: PiTxDqs: 45
N4.C3.D0.R0.S02: RdPtrOffsetTxDq: 08
N6.C2.D0.R1.S10: RdPtrOffsetTxDq: 07
N0.C2.D0.R1.S09: RdPtrOffsetTxDq: 07
N2.C3.D1.R0.S02: wrcmd2dqsstartlatency: 04
N4.C3.D0.R0.S03: RdPtrOffsetTxDq: 07
N6.C2.D0.R1.S11: RdPtrOffsetTxDq: 07
N0.C2.D0.R1.S10: RdPtrOffsetTxDq: 07
N2.C3.D1.R0.S02: RdPtrOffsetTxDq: 05
N4.C3.D0.R0.S04: RdPtrOffsetTxDq: 07
N6.C2.D0.R1.S12: RdPtrOffsetTxDq: 07
N0.C2.D0.R1.S11: RdPtrOffsetTxDq: 06
N2.C3.D1.R0.S02: RdPtrOffsetTxDqs: 07
N4.C3.D0.R0.S05: RdPtrOffsetTxDq: 07
N6.C2.D0.R1.S13: RdPtrOffsetTxDq: 06
N0.C2.D0.R1.S12: RdPtrOffsetTxDq: 06
N2.C3.D1.R0.S02: PiTxDqs: 33
N4.C3.D0.R0.S06: RdPtrOffsetTxDq: 07
N6.C2.D0.R1.S14: RdPtrOffsetTxDq: 07
N0.C2.D0.R1.S13: RdPtrOffsetTxDq: 05
N2.C3.D1.R0.S03: wrcmd2dqsstartlatency: 04
N4.C3.D0.R0.S07: RdPtrOffsetTxDq: 07
N6.C2.D0.R1.S15: RdPtrOffsetTxDq: 07
N0.C2.D0.R1.S14: RdPtrOffsetTxDq: 06
N2.C3.D1.R0.S03: RdPtrOffsetTxDq: 05
N4.C3.D0.R0.S08: RdPtrOffsetTxDq: 07
N6.C2.D0.R1.S16: RdPtrOffsetTxDq: 07
N0.C2.D0.R1.S15: RdPtrOffsetTxDq: 06
N2.C3.D1.R0.S03: RdPtrOffsetTxDqs: 07
N4.C3.D0.R0.S09: RdPtrOffsetTxDq: 08
N6.C2.D0.R1.S17: RdPtrOffsetTxDq: 07
N0.C2.D0.R1.S16: RdPtrOffsetTxDq: 06
N2.C3.D1.R0.S03: PiTxDqs: 19
N4.C3.D0.R0.S10: RdPtrOffsetTxDq: 08
N6.C2.D0.R1.S00: Total Delay in PI ticks: TxDQ = 971
N0.C2.D0.R1.S17: RdPtrOffsetTxDq: 06
N2.C3.D1.R0.S04: wrcmd2dqsstartlatency: 04
N4.C3.D0.R0.S11: RdPtrOffsetTxDq: 08
N6.C2.D0.R1.S01: Total Delay in PI ticks: TxDQ = 955
N0.C2.D0.R1.S00: RdPtrOffsetTxDq: 08
N2.C3.D1.R0.S04: RdPtrOffsetTxDq: 05
N4.C3.D0.R0.S12: RdPtrOffsetTxDq: 07
N6.C2.D0.R1.S02: Total Delay in PI ticks: TxDQ = 945
N0.C2.D0.R1.S01: RdPtrOffsetTxDq: 07
N2.C3.D1.R0.S04: RdPtrOffsetTxDqs: 06
N4.C3.D0.R0.S13: RdPtrOffsetTxDq: 07
N6.C2.D0.R1.S03: Total Delay in PI ticks: TxDQ = 926
N0.C2.D0.R1.S02: RdPtrOffsetTxDq: 07
N2.C3.D1.R0.S04: PiTxDqs: 48
N4.C3.D0.R0.S14: RdPtrOffsetTxDq: 07
N6.C2.D0.R1.S04: Total Delay in PI ticks: TxDQ = 889
N0.C2.D0.R1.S03: RdPtrOffsetTxDq: 07
N2.C3.D1.R0.S05: wrcmd2dqsstartlatency: 04
N4.C3.D0.R0.S15: RdPtrOffsetTxDq: 07
N6.C2.D0.R1.S05: Total Delay in PI ticks: TxDQ = 916
N0.C2.D0.R1.S04: RdPtrOffsetTxDq: 06
N2.C3.D1.R0.S05: RdPtrOffsetTxDq: 05
N4.C3.D0.R0.S16: RdPtrOffsetTxDq: 07
N6.C2.D0.R1.S06: Total Delay in PI ticks: TxDQ = 917
N0.C2.D0.R1.S05: RdPtrOffsetTxDq: 07
N2.C3.D1.R0.S05: RdPtrOffsetTxDqs: 06
N4.C3.D0.R0.S17: RdPtrOffsetTxDq: 07
N6.C2.D0.R1.S07: Total Delay in PI ticks: TxDQ = 935
N0.C2.D0.R1.S06: RdPtrOffsetTxDq: 07
N2.C3.D1.R0.S05: PiTxDqs: 62
N4.C3.D0.R0.S00: Total Delay in PI ticks: TxDQ = 990
N6.C2.D0.R1.S08: Total Delay in PI ticks: TxDQ = 906
N0.C2.D0.R1.S07: RdPtrOffsetTxDq: 07
N2.C3.D1.R0.S06: wrcmd2dqsstartlatency: 04
N4.C3.D0.R0.S01: Total Delay in PI ticks: TxDQ = 974
N6.C2.D0.R1.S09: Total Delay in PI ticks: TxDQ = 966
N0.C2.D0.R1.S08: RdPtrOffsetTxDq: 07
N2.C3.D1.R0.S06: RdPtrOffsetTxDq: 05
N4.C3.D0.R0.S02: Total Delay in PI ticks: TxDQ = 964
N6.C2.D0.R1.S10: Total Delay in PI ticks: TxDQ = 956
N0.C2.D0.R1.S09: RdPtrOffsetTxDq: 08
N2.C3.D1.R0.S06: RdPtrOffsetTxDqs: 07
N4.C3.D0.R0.S03: Total Delay in PI ticks: TxDQ = 948
N6.C2.D0.R1.S11: Total Delay in PI ticks: TxDQ = 947
N0.C2.D0.R1.S10: RdPtrOffsetTxDq: 08
N2.C3.D1.R0.S06: PiTxDqs: 11
N4.C3.D0.R0.S04: Total Delay in PI ticks: TxDQ = 912
N6.C2.D0.R1.S12: Total Delay in PI ticks: TxDQ = 931
N0.C2.D0.R1.S11: RdPtrOffsetTxDq: 07
N2.C3.D1.R0.S07: wrcmd2dqsstartlatency: 04
N4.C3.D0.R0.S05: Total Delay in PI ticks: TxDQ = 929
N6.C2.D0.R1.S13: Total Delay in PI ticks: TxDQ = 888
N0.C2.D0.R1.S12: RdPtrOffsetTxDq: 07
N2.C3.D1.R0.S07: RdPtrOffsetTxDq: 05
N4.C3.D0.R0.S06: Total Delay in PI ticks: TxDQ = 941
N6.C2.D0.R1.S14: Total Delay in PI ticks: TxDQ = 916
N0.C2.D0.R1.S13: RdPtrOffsetTxDq: 06
N2.C3.D1.R0.S07: RdPtrOffsetTxDqs: 07
N4.C3.D0.R0.S07: Total Delay in PI ticks: TxDQ = 956
N6.C2.D0.R1.S15: Total Delay in PI ticks: TxDQ = 916
N0.C2.D0.R1.S14: RdPtrOffsetTxDq: 07
N2.C3.D1.R0.S07: PiTxDqs: 29
N4.C3.D0.R0.S08: Total Delay in PI ticks: TxDQ = 932
N6.C2.D0.R1.S16: Total Delay in PI ticks: TxDQ = 938
N0.C2.D0.R1.S15: RdPtrOffsetTxDq: 07
N2.C3.D1.R0.S08: wrcmd2dqsstartlatency: 04
N4.C3.D0.R0.S09: Total Delay in PI ticks: TxDQ = 990
N6.C2.D0.R1.S17: Total Delay in PI ticks: TxDQ = 904
N0.C2.D0.R1.S16: RdPtrOffsetTxDq: 07
N2.C3.D1.R0.S08: RdPtrOffsetTxDq: 05
N4.C3.D0.R0.S10: Total Delay in PI ticks: TxDQ = 973
N6.C2.D1.R0.S00: wrcmd2dqsstartlatency: 04
N0.C2.D0.R1.S17: RdPtrOffsetTxDq: 07
N2.C3.D1.R0.S08: RdPtrOffsetTxDqs: 07
N4.C3.D0.R0.S11: Total Delay in PI ticks: TxDQ = 963
N6.C2.D1.R0.S00: RdPtrOffsetTxDq: 06
N0.C2.D0.R1.S00: Total Delay in PI ticks: TxDQ = 975
N2.C3.D1.R0.S08: PiTxDqs: 00
N4.C3.D0.R0.S12: Total Delay in PI ticks: TxDQ = 949
N6.C2.D1.R0.S00: RdPtrOffsetTxDqs: 07
N0.C2.D0.R1.S01: Total Delay in PI ticks: TxDQ = 961
N2.C3.D1.R0.S09: wrcmd2dqsstartlatency: 04
N4.C3.D0.R0.S13: Total Delay in PI ticks: TxDQ = 915
N6.C2.D1.R0.S00: PiTxDqs: 55
N0.C2.D0.R1.S02: Total Delay in PI ticks: TxDQ = 952
N2.C3.D1.R0.S09: RdPtrOffsetTxDq: 06
N4.C3.D0.R0.S14: Total Delay in PI ticks: TxDQ = 926
N6.C2.D1.R0.S01: wrcmd2dqsstartlatency: 04
N0.C2.D0.R1.S03: Total Delay in PI ticks: TxDQ = 932
N2.C3.D1.R0.S09: RdPtrOffsetTxDqs: 07
N4.C3.D0.R0.S15: Total Delay in PI ticks: TxDQ = 945
N6.C2.D1.R0.S01: RdPtrOffsetTxDq: 06
N0.C2.D0.R1.S04: Total Delay in PI ticks: TxDQ = 895
N2.C3.D1.R0.S09: PiTxDqs: 59
N4.C3.D0.R0.S16: Total Delay in PI ticks: TxDQ = 955
N6.C2.D1.R0.S01: RdPtrOffsetTxDqs: 07
N0.C2.D0.R1.S05: Total Delay in PI ticks: TxDQ = 921
N2.C3.D1.R0.S10: wrcmd2dqsstartlatency: 04
N4.C3.D0.R0.S17: Total Delay in PI ticks: TxDQ = 929
N6.C2.D1.R0.S01: PiTxDqs: 41
N0.C2.D0.R1.S06: Total Delay in PI ticks: TxDQ = 920
N2.C3.D1.R0.S10: RdPtrOffsetTxDq: 06
N4.C3.D0.R1.S00: wrcmd2dqsstartlatency: 04
N6.C2.D1.R0.S02: wrcmd2dqsstartlatency: 04
N0.C2.D0.R1.S07: Total Delay in PI ticks: TxDQ = 939
N2.C3.D1.R0.S10: RdPtrOffsetTxDqs: 07
N4.C3.D0.R1.S00: RdPtrOffsetTxDq: 06
N6.C2.D1.R0.S02: RdPtrOffsetTxDq: 05
N0.C2.D0.R1.S08: Total Delay in PI ticks: TxDQ = 910
N2.C3.D1.R0.S10: PiTxDqs: 45
N4.C3.D0.R1.S00: RdPtrOffsetTxDqs: 07
N6.C2.D1.R0.S02: RdPtrOffsetTxDqs: 07
N0.C2.D0.R1.S09: Total Delay in PI ticks: TxDQ = 977
N2.C3.D1.R0.S11: wrcmd2dqsstartlatency: 04
N4.C3.D0.R1.S00: PiTxDqs: 58
N6.C2.D1.R0.S02: PiTxDqs: 32
N0.C2.D0.R1.S10: Total Delay in PI ticks: TxDQ = 959
N2.C3.D1.R0.S11: RdPtrOffsetTxDq: 05
N4.C3.D0.R1.S01: wrcmd2dqsstartlatency: 04
N6.C2.D1.R0.S03: wrcmd2dqsstartlatency: 04
N0.C2.D0.R1.S11: Total Delay in PI ticks: TxDQ = 950
N2.C3.D1.R0.S11: RdPtrOffsetTxDqs: 07
N4.C3.D0.R1.S01: RdPtrOffsetTxDq: 06
N6.C2.D1.R0.S03: RdPtrOffsetTxDq: 05
N0.C2.D0.R1.S12: Total Delay in PI ticks: TxDQ = 932
N2.C3.D1.R0.S11: PiTxDqs: 32
N4.C3.D0.R1.S01: RdPtrOffsetTxDqs: 07
N6.C2.D1.R0.S03: RdPtrOffsetTxDqs: 07
N0.C2.D0.R1.S13: Total Delay in PI ticks: TxDQ = 893
N2.C3.D1.R0.S12: wrcmd2dqsstartlatency: 04
N4.C3.D0.R1.S01: PiTxDqs: 42
N6.C2.D1.R0.S03: PiTxDqs: 16
N0.C2.D0.R1.S14: Total Delay in PI ticks: TxDQ = 922
N2.C3.D1.R0.S12: RdPtrOffsetTxDq: 05
N4.C3.D0.R1.S02: wrcmd2dqsstartlatency: 04
N6.C2.D1.R0.S04: wrcmd2dqsstartlatency: 04
N0.C2.D0.R1.S15: Total Delay in PI ticks: TxDQ = 920
N2.C3.D1.R0.S12: RdPtrOffsetTxDqs: 07
N4.C3.D0.R1.S02: RdPtrOffsetTxDq: 05
N6.C2.D1.R0.S04: RdPtrOffsetTxDq: 05
N0.C2.D0.R1.S16: Total Delay in PI ticks: TxDQ = 940
N2.C3.D1.R0.S12: PiTxDqs: 19
N4.C3.D0.R1.S02: RdPtrOffsetTxDqs: 07
N6.C2.D1.R0.S04: RdPtrOffsetTxDqs: 06
N0.C2.D0.R1.S17: Total Delay in PI ticks: TxDQ = 908
N2.C3.D1.R0.S13: wrcmd2dqsstartlatency: 04
N4.C3.D0.R1.S02: PiTxDqs: 28
N6.C2.D1.R0.S04: PiTxDqs: 38
N0.C2.D1.R0.S00: wrcmd2dqsstartlatency: 04
N2.C3.D1.R0.S13: RdPtrOffsetTxDq: 05
N4.C3.D0.R1.S03: wrcmd2dqsstartlatency: 04
N6.C2.D1.R0.S05: wrcmd2dqsstartlatency: 04
N0.C2.D1.R0.S00: RdPtrOffsetTxDq: 06
N2.C3.D1.R0.S13: RdPtrOffsetTxDqs: 06
N4.C3.D0.R1.S03: RdPtrOffsetTxDq: 05
N6.C2.D1.R0.S05: RdPtrOffsetTxDq: 05
N0.C2.D1.R0.S00: RdPtrOffsetTxDqs: 07
N2.C3.D1.R0.S13: PiTxDqs: 49
N4.C3.D0.R1.S03: RdPtrOffsetTxDqs: 07
N6.C2.D1.R0.S05: RdPtrOffsetTxDqs: 07
N0.C2.D1.R0.S00: PiTxDqs: 57
N2.C3.D1.R0.S14: wrcmd2dqsstartlatency: 04
N4.C3.D0.R1.S03: PiTxDqs: 17
N6.C2.D1.R0.S05: PiTxDqs: 04
N0.C2.D1.R0.S01: wrcmd2dqsstartlatency: 04
N2.C3.D1.R0.S14: RdPtrOffsetTxDq: 05
N4.C3.D0.R1.S04: wrcmd2dqsstartlatency: 04
N6.C2.D1.R0.S06: wrcmd2dqsstartlatency: 04
N0.C2.D1.R0.S01: RdPtrOffsetTxDq: 06
N2.C3.D1.R0.S14: RdPtrOffsetTxDqs: 06
N4.C3.D0.R1.S04: RdPtrOffsetTxDq: 05
N6.C2.D1.R0.S06: RdPtrOffsetTxDq: 05
N0.C2.D1.R0.S01: RdPtrOffsetTxDqs: 07
N2.C3.D1.R0.S14: PiTxDqs: 60
N4.C3.D0.R1.S04: RdPtrOffsetTxDqs: 06
N6.C2.D1.R0.S06: RdPtrOffsetTxDqs: 07
N0.C2.D1.R0.S01: PiTxDqs: 42
N2.C3.D1.R0.S15: wrcmd2dqsstartlatency: 04
N4.C3.D0.R1.S04: PiTxDqs: 43
N6.C2.D1.R0.S06: PiTxDqs: 01
N0.C2.D1.R0.S02: wrcmd2dqsstartlatency: 04
N2.C3.D1.R0.S15: RdPtrOffsetTxDq: 05
N4.C3.D0.R1.S05: wrcmd2dqsstartlatency: 04
N6.C2.D1.R0.S07: wrcmd2dqsstartlatency: 04
N0.C2.D1.R0.S02: RdPtrOffsetTxDq: 05
N2.C3.D1.R0.S15: RdPtrOffsetTxDqs: 07
N4.C3.D0.R1.S05: RdPtrOffsetTxDq: 05
N6.C2.D1.R0.S07: RdPtrOffsetTxDq: 05
N0.C2.D1.R0.S02: RdPtrOffsetTxDqs: 07
N2.C3.D1.R0.S15: PiTxDqs: 10
N4.C3.D0.R1.S05: RdPtrOffsetTxDqs: 06
N6.C2.D1.R0.S07: RdPtrOffsetTxDqs: 07
N0.C2.D1.R0.S02: PiTxDqs: 34
N2.C3.D1.R0.S16: wrcmd2dqsstartlatency: 04
N4.C3.D0.R1.S05: PiTxDqs: 56
N6.C2.D1.R0.S07: PiTxDqs: 25
N0.C2.D1.R0.S03: wrcmd2dqsstartlatency: 04
N2.C3.D1.R0.S16: RdPtrOffsetTxDq: 05
N4.C3.D0.R1.S06: wrcmd2dqsstartlatency: 04
N6.C2.D1.R0.S08: wrcmd2dqsstartlatency: 04
N0.C2.D1.R0.S03: RdPtrOffsetTxDq: 05
N2.C3.D1.R0.S16: RdPtrOffsetTxDqs: 07
N4.C3.D0.R1.S06: RdPtrOffsetTxDq: 05
N6.C2.D1.R0.S08: RdPtrOffsetTxDq: 05
N0.C2.D1.R0.S03: RdPtrOffsetTxDqs: 07
N2.C3.D1.R0.S16: PiTxDqs: 29
N4.C3.D0.R1.S06: RdPtrOffsetTxDqs: 07
N6.C2.D1.R0.S08: RdPtrOffsetTxDqs: 06
N0.C2.D1.R0.S03: PiTxDqs: 16
N2.C3.D1.R0.S17: wrcmd2dqsstartlatency: 04
N4.C3.D0.R1.S06: PiTxDqs: 08
N6.C2.D1.R0.S08: PiTxDqs: 53
N0.C2.D1.R0.S04: wrcmd2dqsstartlatency: 04
N2.C3.D1.R0.S17: RdPtrOffsetTxDq: 05
N4.C3.D0.R1.S07: wrcmd2dqsstartlatency: 04
N6.C2.D1.R0.S09: wrcmd2dqsstartlatency: 04
N0.C2.D1.R0.S04: RdPtrOffsetTxDq: 05
N2.C3.D1.R0.S17: RdPtrOffsetTxDqs: 07
N4.C3.D0.R1.S07: RdPtrOffsetTxDq: 05
N6.C2.D1.R0.S09: RdPtrOffsetTxDq: 06
N0.C2.D1.R0.S04: RdPtrOffsetTxDqs: 06
N2.C3.D1.R0.S17: PiTxDqs: 00
N4.C3.D0.R1.S07: RdPtrOffsetTxDqs: 07
N6.C2.D1.R0.S09: RdPtrOffsetTxDqs: 07
N0.C2.D1.R0.S04: PiTxDqs: 38
N2.C3.D1.R0.S00: RdPtrOffsetTxDq: 07
N4.C3.D0.R1.S07: PiTxDqs: 24
N6.C2.D1.R0.S09: PiTxDqs: 56
N0.C2.D1.R0.S05: wrcmd2dqsstartlatency: 04
N2.C3.D1.R0.S01: RdPtrOffsetTxDq: 07
N4.C3.D0.R1.S08: wrcmd2dqsstartlatency: 04
N6.C2.D1.R0.S10: wrcmd2dqsstartlatency: 04
N0.C2.D1.R0.S05: RdPtrOffsetTxDq: 05
N2.C3.D1.R0.S02: RdPtrOffsetTxDq: 06
N4.C3.D0.R1.S08: RdPtrOffsetTxDq: 05
N6.C2.D1.R0.S10: RdPtrOffsetTxDq: 06
N0.C2.D1.R0.S05: RdPtrOffsetTxDqs: 07
N2.C3.D1.R0.S03: RdPtrOffsetTxDq: 06
N4.C3.D0.R1.S08: RdPtrOffsetTxDqs: 06
N6.C2.D1.R0.S10: RdPtrOffsetTxDqs: 07
N0.C2.D1.R0.S05: PiTxDqs: 04
N2.C3.D1.R0.S04: RdPtrOffsetTxDq: 06
N4.C3.D0.R1.S08: PiTxDqs: 59
N6.C2.D1.R0.S10: PiTxDqs: 41
N0.C2.D1.R0.S06: wrcmd2dqsstartlatency: 04
N2.C3.D1.R0.S05: RdPtrOffsetTxDq: 06
N4.C3.D0.R1.S09: wrcmd2dqsstartlatency: 04
N6.C2.D1.R0.S11: wrcmd2dqsstartlatency: 04
N0.C2.D1.R0.S06: RdPtrOffsetTxDq: 05
N2.C3.D1.R0.S06: RdPtrOffsetTxDq: 06
N4.C3.D0.R1.S09: RdPtrOffsetTxDq: 06
N6.C2.D1.R0.S11: RdPtrOffsetTxDq: 05
N0.C2.D1.R0.S06: RdPtrOffsetTxDqs: 07
N2.C3.D1.R0.S07: RdPtrOffsetTxDq: 06
N4.C3.D0.R1.S09: RdPtrOffsetTxDqs: 07
N6.C2.D1.R0.S11: RdPtrOffsetTxDqs: 07
N0.C2.D1.R0.S06: PiTxDqs: 01
N2.C3.D1.R0.S08: RdPtrOffsetTxDq: 06
N4.C3.D0.R1.S09: PiTxDqs: 57
N6.C2.D1.R0.S11: PiTxDqs: 32
N0.C2.D1.R0.S07: wrcmd2dqsstartlatency: 04
N2.C3.D1.R0.S09: RdPtrOffsetTxDq: 07
N4.C3.D0.R1.S10: wrcmd2dqsstartlatency: 04
N6.C2.D1.R0.S12: wrcmd2dqsstartlatency: 04
N0.C2.D1.R0.S07: RdPtrOffsetTxDq: 05
N2.C3.D1.R0.S10: RdPtrOffsetTxDq: 07
N4.C3.D0.R1.S10: RdPtrOffsetTxDq: 06
N6.C2.D1.R0.S12: RdPtrOffsetTxDq: 05
N0.C2.D1.R0.S07: RdPtrOffsetTxDqs: 07
N2.C3.D1.R0.S11: RdPtrOffsetTxDq: 06
N4.C3.D0.R1.S10: RdPtrOffsetTxDqs: 07
N6.C2.D1.R0.S12: RdPtrOffsetTxDqs: 07
N0.C2.D1.R0.S07: PiTxDqs: 22
N2.C3.D1.R0.S12: RdPtrOffsetTxDq: 06
N4.C3.D0.R1.S10: PiTxDqs: 42
N6.C2.D1.R0.S12: PiTxDqs: 16
N0.C2.D1.R0.S08: wrcmd2dqsstartlatency: 04
N2.C3.D1.R0.S13: RdPtrOffsetTxDq: 06
N4.C3.D0.R1.S11: wrcmd2dqsstartlatency: 04
N6.C2.D1.R0.S13: wrcmd2dqsstartlatency: 04
N0.C2.D1.R0.S08: RdPtrOffsetTxDq: 05
N2.C3.D1.R0.S14: RdPtrOffsetTxDq: 06
N4.C3.D0.R1.S11: RdPtrOffsetTxDq: 05
N6.C2.D1.R0.S13: RdPtrOffsetTxDq: 05
N0.C2.D1.R0.S08: RdPtrOffsetTxDqs: 06
N2.C3.D1.R0.S15: RdPtrOffsetTxDq: 06
N4.C3.D0.R1.S11: RdPtrOffsetTxDqs: 07
N6.C2.D1.R0.S13: RdPtrOffsetTxDqs: 06
N0.C2.D1.R0.S08: PiTxDqs: 56
N2.C3.D1.R0.S16: RdPtrOffsetTxDq: 06
N4.C3.D0.R1.S11: PiTxDqs: 29
N6.C2.D1.R0.S13: PiTxDqs: 38
N0.C2.D1.R0.S09: wrcmd2dqsstartlatency: 04
N2.C3.D1.R0.S17: RdPtrOffsetTxDq: 06
N4.C3.D0.R1.S12: wrcmd2dqsstartlatency: 04
N6.C2.D1.R0.S14: wrcmd2dqsstartlatency: 04
N0.C2.D1.R0.S09: RdPtrOffsetTxDq: 06
N2.C3.D1.R0.S00: RdPtrOffsetTxDq: 08
N4.C3.D0.R1.S12: RdPtrOffsetTxDq: 05
N6.C2.D1.R0.S14: RdPtrOffsetTxDq: 05
N0.C2.D1.R0.S09: RdPtrOffsetTxDqs: 07
N2.C3.D1.R0.S01: RdPtrOffsetTxDq: 08
N4.C3.D0.R1.S12: RdPtrOffsetTxDqs: 07
N6.C2.D1.R0.S14: RdPtrOffsetTxDqs: 07
N0.C2.D1.R0.S09: PiTxDqs: 55
N2.C3.D1.R0.S02: RdPtrOffsetTxDq: 07
N4.C3.D0.R1.S12: PiTxDqs: 19
N6.C2.D1.R0.S14: PiTxDqs: 04
N0.C2.D1.R0.S10: wrcmd2dqsstartlatency: 04
N2.C3.D1.R0.S03: RdPtrOffsetTxDq: 07
N4.C3.D0.R1.S13: wrcmd2dqsstartlatency: 04
N6.C2.D1.R0.S15: wrcmd2dqsstartlatency: 04
N0.C2.D1.R0.S10: RdPtrOffsetTxDq: 06
N2.C3.D1.R0.S04: RdPtrOffsetTxDq: 07
N4.C3.D0.R1.S13: RdPtrOffsetTxDq: 05
N6.C2.D1.R0.S15: RdPtrOffsetTxDq: 05
N0.C2.D1.R0.S10: RdPtrOffsetTxDqs: 07
N2.C3.D1.R0.S05: RdPtrOffsetTxDq: 07
N4.C3.D0.R1.S13: RdPtrOffsetTxDqs: 06
N6.C2.D1.R0.S15: RdPtrOffsetTxDqs: 07
N0.C2.D1.R0.S10: PiTxDqs: 44
N2.C3.D1.R0.S06: RdPtrOffsetTxDq: 07
N4.C3.D0.R1.S13: PiTxDqs: 43
N6.C2.D1.R0.S15: PiTxDqs: 00
N0.C2.D1.R0.S11: wrcmd2dqsstartlatency: 04
N2.C3.D1.R0.S07: RdPtrOffsetTxDq: 07
N4.C3.D0.R1.S14: wrcmd2dqsstartlatency: 04
N6.C2.D1.R0.S16: wrcmd2dqsstartlatency: 04
N0.C2.D1.R0.S11: RdPtrOffsetTxDq: 05
N2.C3.D1.R0.S08: RdPtrOffsetTxDq: 07
N4.C3.D0.R1.S14: RdPtrOffsetTxDq: 05
N6.C2.D1.R0.S16: RdPtrOffsetTxDq: 05
N0.C2.D1.R0.S11: RdPtrOffsetTxDqs: 07
N2.C3.D1.R0.S09: RdPtrOffsetTxDq: 08
N4.C3.D0.R1.S14: RdPtrOffsetTxDqs: 06
N6.C2.D1.R0.S16: RdPtrOffsetTxDqs: 07
N0.C2.D1.R0.S11: PiTxDqs: 32
N2.C3.D1.R0.S10: RdPtrOffsetTxDq: 08
N4.C3.D0.R1.S14: PiTxDqs: 58
N6.C2.D1.R0.S16: PiTxDqs: 23
N0.C2.D1.R0.S12: wrcmd2dqsstartlatency: 04
N2.C3.D1.R0.S11: RdPtrOffsetTxDq: 07
N4.C3.D0.R1.S15: wrcmd2dqsstartlatency: 04
N6.C2.D1.R0.S17: wrcmd2dqsstartlatency: 04
N0.C2.D1.R0.S12: RdPtrOffsetTxDq: 05
N2.C3.D1.R0.S12: RdPtrOffsetTxDq: 07
N4.C3.D0.R1.S15: RdPtrOffsetTxDq: 05
N6.C2.D1.R0.S17: RdPtrOffsetTxDq: 05
N0.C2.D1.R0.S12: RdPtrOffsetTxDqs: 07
N2.C3.D1.R0.S13: RdPtrOffsetTxDq: 07
N4.C3.D0.R1.S15: RdPtrOffsetTxDqs: 07
N6.C2.D1.R0.S17: RdPtrOffsetTxDqs: 06
N0.C2.D1.R0.S12: PiTxDqs: 14
N2.C3.D1.R0.S14: RdPtrOffsetTxDq: 07
N4.C3.D0.R1.S15: PiTxDqs: 09
N6.C2.D1.R0.S17: PiTxDqs: 55
N0.C2.D1.R0.S13: wrcmd2dqsstartlatency: 04
N2.C3.D1.R0.S15: RdPtrOffsetTxDq: 07
N4.C3.D0.R1.S16: wrcmd2dqsstartlatency: 04
N6.C2.D1.R0.S00: RdPtrOffsetTxDq: 07
N0.C2.D1.R0.S13: RdPtrOffsetTxDq: 05
N2.C3.D1.R0.S16: RdPtrOffsetTxDq: 07
N4.C3.D0.R1.S16: RdPtrOffsetTxDq: 05
N6.C2.D1.R0.S01: RdPtrOffsetTxDq: 07
N0.C2.D1.R0.S13: RdPtrOffsetTxDqs: 06
N2.C3.D1.R0.S17: RdPtrOffsetTxDq: 07
N4.C3.D0.R1.S16: RdPtrOffsetTxDqs: 07
N6.C2.D1.R0.S02: RdPtrOffsetTxDq: 06
N0.C2.D1.R0.S13: PiTxDqs: 39
N2.C3.D1.R0.S00: Total Delay in PI ticks: TxDQ = 988
N4.C3.D0.R1.S16: PiTxDqs: 25
N6.C2.D1.R0.S03: RdPtrOffsetTxDq: 06
N0.C2.D1.R0.S14: wrcmd2dqsstartlatency: 04
N2.C3.D1.R0.S01: Total Delay in PI ticks: TxDQ = 973
N4.C3.D0.R1.S17: wrcmd2dqsstartlatency: 04
N6.C2.D1.R0.S04: RdPtrOffsetTxDq: 06
N0.C2.D1.R0.S14: RdPtrOffsetTxDq: 05
N2.C3.D1.R0.S02: Total Delay in PI ticks: TxDQ = 959
N4.C3.D0.R1.S17: RdPtrOffsetTxDq: 05
N6.C2.D1.R0.S05: RdPtrOffsetTxDq: 06
N0.C2.D1.R0.S14: RdPtrOffsetTxDqs: 07
N2.C3.D1.R0.S03: Total Delay in PI ticks: TxDQ = 946
N4.C3.D0.R1.S17: RdPtrOffsetTxDqs: 06
N6.C2.D1.R0.S06: RdPtrOffsetTxDq: 06
N0.C2.D1.R0.S14: PiTxDqs: 00
N2.C3.D1.R0.S04: Total Delay in PI ticks: TxDQ = 911
N4.C3.D0.R1.S17: PiTxDqs: 59
N6.C2.D1.R0.S07: RdPtrOffsetTxDq: 06
N0.C2.D1.R0.S15: wrcmd2dqsstartlatency: 04
N2.C3.D1.R0.S05: Total Delay in PI ticks: TxDQ = 926
N4.C3.D0.R1.S00: RdPtrOffsetTxDq: 07
N6.C2.D1.R0.S08: RdPtrOffsetTxDq: 06
N0.C2.D1.R0.S15: RdPtrOffsetTxDq: 05
N2.C3.D1.R0.S06: Total Delay in PI ticks: TxDQ = 938
N4.C3.D0.R1.S01: RdPtrOffsetTxDq: 07
N6.C2.D1.R0.S09: RdPtrOffsetTxDq: 07
N0.C2.D1.R0.S15: RdPtrOffsetTxDqs: 07
N2.C3.D1.R0.S07: Total Delay in PI ticks: TxDQ = 956
N4.C3.D0.R1.S02: RdPtrOffsetTxDq: 06
N6.C2.D1.R0.S10: RdPtrOffsetTxDq: 07
N0.C2.D1.R0.S15: PiTxDqs: 04
N2.C3.D1.R0.S08: Total Delay in PI ticks: TxDQ = 927
N4.C3.D0.R1.S03: RdPtrOffsetTxDq: 06
N6.C2.D1.R0.S11: RdPtrOffsetTxDq: 06
N0.C2.D1.R0.S16: wrcmd2dqsstartlatency: 04
N2.C3.D1.R0.S09: Total Delay in PI ticks: TxDQ = 984
N4.C3.D0.R1.S04: RdPtrOffsetTxDq: 06
N6.C2.D1.R0.S12: RdPtrOffsetTxDq: 06
N0.C2.D1.R0.S16: RdPtrOffsetTxDq: 05
N2.C3.D1.R0.S10: Total Delay in PI ticks: TxDQ = 972
N4.C3.D0.R1.S05: RdPtrOffsetTxDq: 06
N6.C2.D1.R0.S13: RdPtrOffsetTxDq: 06
N0.C2.D1.R0.S16: RdPtrOffsetTxDqs: 07
N2.C3.D1.R0.S11: Total Delay in PI ticks: TxDQ = 960
N4.C3.D0.R1.S06: RdPtrOffsetTxDq: 06
N6.C2.D1.R0.S14: RdPtrOffsetTxDq: 06
N0.C2.D1.R0.S16: PiTxDqs: 22
N2.C3.D1.R0.S12: Total Delay in PI ticks: TxDQ = 945
N4.C3.D0.R1.S07: RdPtrOffsetTxDq: 06
N6.C2.D1.R0.S15: RdPtrOffsetTxDq: 06
N0.C2.D1.R0.S17: wrcmd2dqsstartlatency: 04
N2.C3.D1.R0.S13: Total Delay in PI ticks: TxDQ = 911
N4.C3.D0.R1.S08: RdPtrOffsetTxDq: 06
N6.C2.D1.R0.S16: RdPtrOffsetTxDq: 06
N0.C2.D1.R0.S17: RdPtrOffsetTxDq: 05
N2.C3.D1.R0.S14: Total Delay in PI ticks: TxDQ = 925
N4.C3.D0.R1.S09: RdPtrOffsetTxDq: 07
N6.C2.D1.R0.S17: RdPtrOffsetTxDq: 06
N0.C2.D1.R0.S17: RdPtrOffsetTxDqs: 06
N2.C3.D1.R0.S15: Total Delay in PI ticks: TxDQ = 938
N4.C3.D0.R1.S10: RdPtrOffsetTxDq: 07
N6.C2.D1.R0.S00: RdPtrOffsetTxDq: 08
N0.C2.D1.R0.S17: PiTxDqs: 56
N2.C3.D1.R0.S16: Total Delay in PI ticks: TxDQ = 956
N4.C3.D0.R1.S11: RdPtrOffsetTxDq: 06
N6.C2.D1.R0.S01: RdPtrOffsetTxDq: 08
N0.C2.D1.R0.S00: RdPtrOffsetTxDq: 07
N2.C3.D1.R0.S17: Total Delay in PI ticks: TxDQ = 926
N4.C3.D0.R1.S12: RdPtrOffsetTxDq: 06
N6.C2.D1.R0.S02: RdPtrOffsetTxDq: 07
N0.C2.D1.R0.S01: RdPtrOffsetTxDq: 07
N2.C3.D1.R1.S00: wrcmd2dqsstartlatency: 04
N4.C3.D0.R1.S13: RdPtrOffsetTxDq: 06
N6.C2.D1.R0.S03: RdPtrOffsetTxDq: 07
N0.C2.D1.R0.S02: RdPtrOffsetTxDq: 06
N2.C3.D1.R1.S00: RdPtrOffsetTxDq: 06
N4.C3.D0.R1.S14: RdPtrOffsetTxDq: 06
N6.C2.D1.R0.S04: RdPtrOffsetTxDq: 07
N0.C2.D1.R0.S03: RdPtrOffsetTxDq: 06
N2.C3.D1.R1.S00: RdPtrOffsetTxDqs: 07
N4.C3.D0.R1.S15: RdPtrOffsetTxDq: 06
N6.C2.D1.R0.S05: RdPtrOffsetTxDq: 07
N0.C2.D1.R0.S04: RdPtrOffsetTxDq: 06
N2.C3.D1.R1.S00: PiTxDqs: 57
N4.C3.D0.R1.S16: RdPtrOffsetTxDq: 06
N6.C2.D1.R0.S06: RdPtrOffsetTxDq: 07
N0.C2.D1.R0.S05: RdPtrOffsetTxDq: 06
N2.C3.D1.R1.S01: wrcmd2dqsstartlatency: 04
N4.C3.D0.R1.S17: RdPtrOffsetTxDq: 06
N6.C2.D1.R0.S07: RdPtrOffsetTxDq: 07
N0.C2.D1.R0.S06: RdPtrOffsetTxDq: 06
N2.C3.D1.R1.S01: RdPtrOffsetTxDq: 06
N4.C3.D0.R1.S00: RdPtrOffsetTxDq: 08
N6.C2.D1.R0.S08: RdPtrOffsetTxDq: 07
N0.C2.D1.R0.S07: RdPtrOffsetTxDq: 06
N2.C3.D1.R1.S01: RdPtrOffsetTxDqs: 07
N4.C3.D0.R1.S01: RdPtrOffsetTxDq: 08
N6.C2.D1.R0.S09: RdPtrOffsetTxDq: 08
N0.C2.D1.R0.S08: RdPtrOffsetTxDq: 06
N2.C3.D1.R1.S01: PiTxDqs: 41
N4.C3.D0.R1.S02: RdPtrOffsetTxDq: 07
N6.C2.D1.R0.S10: RdPtrOffsetTxDq: 08
N0.C2.D1.R0.S09: RdPtrOffsetTxDq: 07
N2.C3.D1.R1.S02: wrcmd2dqsstartlatency: 04
N4.C3.D0.R1.S03: RdPtrOffsetTxDq: 07
N6.C2.D1.R0.S11: RdPtrOffsetTxDq: 07
N0.C2.D1.R0.S10: RdPtrOffsetTxDq: 07
N2.C3.D1.R1.S02: RdPtrOffsetTxDq: 05
N4.C3.D0.R1.S04: RdPtrOffsetTxDq: 07
N6.C2.D1.R0.S12: RdPtrOffsetTxDq: 07
N0.C2.D1.R0.S11: RdPtrOffsetTxDq: 06
N2.C3.D1.R1.S02: RdPtrOffsetTxDqs: 07
N4.C3.D0.R1.S05: RdPtrOffsetTxDq: 07
N6.C2.D1.R0.S13: RdPtrOffsetTxDq: 07
N0.C2.D1.R0.S12: RdPtrOffsetTxDq: 06
N2.C3.D1.R1.S02: PiTxDqs: 28
N4.C3.D0.R1.S06: RdPtrOffsetTxDq: 07
N6.C2.D1.R0.S14: RdPtrOffsetTxDq: 07
N0.C2.D1.R0.S13: RdPtrOffsetTxDq: 06
N2.C3.D1.R1.S03: wrcmd2dqsstartlatency: 04
N4.C3.D0.R1.S07: RdPtrOffsetTxDq: 07
N6.C2.D1.R0.S15: RdPtrOffsetTxDq: 07
N0.C2.D1.R0.S14: RdPtrOffsetTxDq: 06
N2.C3.D1.R1.S03: RdPtrOffsetTxDq: 05
N4.C3.D0.R1.S08: RdPtrOffsetTxDq: 07
N6.C2.D1.R0.S16: RdPtrOffsetTxDq: 07
N0.C2.D1.R0.S15: RdPtrOffsetTxDq: 06
N2.C3.D1.R1.S03: RdPtrOffsetTxDqs: 07
N4.C3.D0.R1.S09: RdPtrOffsetTxDq: 08
N6.C2.D1.R0.S17: RdPtrOffsetTxDq: 07
N0.C2.D1.R0.S16: RdPtrOffsetTxDq: 06
N2.C3.D1.R1.S03: PiTxDqs: 16
N4.C3.D0.R1.S10: RdPtrOffsetTxDq: 08
N6.C2.D1.R0.S00: Total Delay in PI ticks: TxDQ = 983
N0.C2.D1.R0.S17: RdPtrOffsetTxDq: 06
N2.C3.D1.R1.S04: wrcmd2dqsstartlatency: 04
N4.C3.D0.R1.S11: RdPtrOffsetTxDq: 07
N6.C2.D1.R0.S01: Total Delay in PI ticks: TxDQ = 967
N0.C2.D1.R0.S00: RdPtrOffsetTxDq: 08
N2.C3.D1.R1.S04: RdPtrOffsetTxDq: 05
N4.C3.D0.R1.S12: RdPtrOffsetTxDq: 07
N6.C2.D1.R0.S02: Total Delay in PI ticks: TxDQ = 960
N0.C2.D1.R0.S01: RdPtrOffsetTxDq: 08
N2.C3.D1.R1.S04: RdPtrOffsetTxDqs: 06
N4.C3.D0.R1.S13: RdPtrOffsetTxDq: 07
N6.C2.D1.R0.S03: Total Delay in PI ticks: TxDQ = 942
N0.C2.D1.R0.S02: RdPtrOffsetTxDq: 07
N2.C3.D1.R1.S04: PiTxDqs: 44
N4.C3.D0.R1.S14: RdPtrOffsetTxDq: 07
N6.C2.D1.R0.S04: Total Delay in PI ticks: TxDQ = 902
N0.C2.D1.R0.S03: RdPtrOffsetTxDq: 07
N2.C3.D1.R1.S05: wrcmd2dqsstartlatency: 04
N4.C3.D0.R1.S15: RdPtrOffsetTxDq: 07
N6.C2.D1.R0.S05: Total Delay in PI ticks: TxDQ = 931
N0.C2.D1.R0.S04: RdPtrOffsetTxDq: 07
N2.C3.D1.R1.S05: RdPtrOffsetTxDq: 05
N4.C3.D0.R1.S16: RdPtrOffsetTxDq: 07
N6.C2.D1.R0.S06: Total Delay in PI ticks: TxDQ = 930
N0.C2.D1.R0.S05: RdPtrOffsetTxDq: 07
N2.C3.D1.R1.S05: RdPtrOffsetTxDqs: 06
N4.C3.D0.R1.S17: RdPtrOffsetTxDq: 07
N6.C2.D1.R0.S07: Total Delay in PI ticks: TxDQ = 951
N0.C2.D1.R0.S06: RdPtrOffsetTxDq: 07
N2.C3.D1.R1.S05: PiTxDqs: 58
N4.C3.D0.R1.S00: Total Delay in PI ticks: TxDQ = 985
N6.C2.D1.R0.S08: Total Delay in PI ticks: TxDQ = 916
N0.C2.D1.R0.S07: RdPtrOffsetTxDq: 07
N2.C3.D1.R1.S06: wrcmd2dqsstartlatency: 04
N4.C3.D0.R1.S01: Total Delay in PI ticks: TxDQ = 969
N6.C2.D1.R0.S09: Total Delay in PI ticks: TxDQ = 982
N0.C2.D1.R0.S08: RdPtrOffsetTxDq: 07
N2.C3.D1.R1.S06: RdPtrOffsetTxDq: 05
N4.C3.D0.R1.S02: Total Delay in PI ticks: TxDQ = 954
N6.C2.D1.R0.S10: Total Delay in PI ticks: TxDQ = 966
N0.C2.D1.R0.S09: RdPtrOffsetTxDq: 08
N2.C3.D1.R1.S06: RdPtrOffsetTxDqs: 07
N4.C3.D0.R1.S03: Total Delay in PI ticks: TxDQ = 943
N6.C2.D1.R0.S11: Total Delay in PI ticks: TxDQ = 959
N0.C2.D1.R0.S10: RdPtrOffsetTxDq: 08
N2.C3.D1.R1.S06: PiTxDqs: 07
N4.C3.D0.R1.S04: Total Delay in PI ticks: TxDQ = 905
N6.C2.D1.R0.S12: Total Delay in PI ticks: TxDQ = 941
N0.C2.D1.R0.S11: RdPtrOffsetTxDq: 07
N2.C3.D1.R1.S07: wrcmd2dqsstartlatency: 04
N4.C3.D0.R1.S05: Total Delay in PI ticks: TxDQ = 919
N6.C2.D1.R0.S13: Total Delay in PI ticks: TxDQ = 901
N0.C2.D1.R0.S12: RdPtrOffsetTxDq: 07
N2.C3.D1.R1.S07: RdPtrOffsetTxDq: 05
N4.C3.D0.R1.S06: Total Delay in PI ticks: TxDQ = 934
N6.C2.D1.R0.S14: Total Delay in PI ticks: TxDQ = 930
N0.C2.D1.R0.S13: RdPtrOffsetTxDq: 07
N2.C3.D1.R1.S07: RdPtrOffsetTxDqs: 07
N4.C3.D0.R1.S07: Total Delay in PI ticks: TxDQ = 949
N6.C2.D1.R0.S15: Total Delay in PI ticks: TxDQ = 928
N0.C2.D1.R0.S14: RdPtrOffsetTxDq: 07
N2.C3.D1.R1.S07: PiTxDqs: 26
N4.C3.D0.R1.S08: Total Delay in PI ticks: TxDQ = 922
N6.C2.D1.R0.S16: Total Delay in PI ticks: TxDQ = 949
N0.C2.D1.R0.S15: RdPtrOffsetTxDq: 07
N2.C3.D1.R1.S08: wrcmd2dqsstartlatency: 04
N4.C3.D0.R1.S09: Total Delay in PI ticks: TxDQ = 982
N6.C2.D1.R0.S17: Total Delay in PI ticks: TxDQ = 916
N0.C2.D1.R0.S16: RdPtrOffsetTxDq: 07
N2.C3.D1.R1.S08: RdPtrOffsetTxDq: 05
N4.C3.D0.R1.S10: Total Delay in PI ticks: TxDQ = 969
N6.C2.D1.R1.S00: wrcmd2dqsstartlatency: 04
N0.C2.D1.R0.S17: RdPtrOffsetTxDq: 07
N2.C3.D1.R1.S08: RdPtrOffsetTxDqs: 06
N4.C3.D0.R1.S11: Total Delay in PI ticks: TxDQ = 955
N6.C2.D1.R1.S00: RdPtrOffsetTxDq: 06
N0.C2.D1.R0.S00: Total Delay in PI ticks: TxDQ = 985
N2.C3.D1.R1.S08: PiTxDqs: 59
N4.C3.D0.R1.S12: Total Delay in PI ticks: TxDQ = 945
N6.C2.D1.R1.S00: RdPtrOffsetTxDqs: 07
N0.C2.D1.R0.S01: Total Delay in PI ticks: TxDQ = 968
N2.C3.D1.R1.S09: wrcmd2dqsstartlatency: 04
N4.C3.D0.R1.S13: Total Delay in PI ticks: TxDQ = 906
N6.C2.D1.R1.S00: PiTxDqs: 50
N0.C2.D1.R0.S02: Total Delay in PI ticks: TxDQ = 961
N2.C3.D1.R1.S09: RdPtrOffsetTxDq: 06
N4.C3.D0.R1.S14: Total Delay in PI ticks: TxDQ = 921
N6.C2.D1.R1.S01: wrcmd2dqsstartlatency: 04
N0.C2.D1.R0.S03: Total Delay in PI ticks: TxDQ = 941
N2.C3.D1.R1.S09: RdPtrOffsetTxDqs: 07
N4.C3.D0.R1.S15: Total Delay in PI ticks: TxDQ = 936
N6.C2.D1.R1.S01: RdPtrOffsetTxDq: 06
N0.C2.D1.R0.S04: Total Delay in PI ticks: TxDQ = 902
N2.C3.D1.R1.S09: PiTxDqs: 56
N4.C3.D0.R1.S16: Total Delay in PI ticks: TxDQ = 951
N6.C2.D1.R1.S01: RdPtrOffsetTxDqs: 07
N0.C2.D1.R0.S05: Total Delay in PI ticks: TxDQ = 929
N2.C3.D1.R1.S10: wrcmd2dqsstartlatency: 04
N4.C3.D0.R1.S17: Total Delay in PI ticks: TxDQ = 921
N6.C2.D1.R1.S01: PiTxDqs: 36
N0.C2.D1.R0.S06: Total Delay in PI ticks: TxDQ = 928
N2.C3.D1.R1.S10: RdPtrOffsetTxDq: 06
N4.C3.D1.R0.S00: wrcmd2dqsstartlatency: 04
N6.C2.D1.R1.S02: wrcmd2dqsstartlatency: 04
N0.C2.D1.R0.S07: Total Delay in PI ticks: TxDQ = 947
N2.C3.D1.R1.S10: RdPtrOffsetTxDqs: 07
N4.C3.D1.R0.S00: RdPtrOffsetTxDq: 06
N6.C2.D1.R1.S02: RdPtrOffsetTxDq: 05
N0.C2.D1.R0.S08: Total Delay in PI ticks: TxDQ = 917
N2.C3.D1.R1.S10: PiTxDqs: 41
N4.C3.D1.R0.S00: RdPtrOffsetTxDqs: 08
N6.C2.D1.R1.S02: RdPtrOffsetTxDqs: 07
N0.C2.D1.R0.S09: Total Delay in PI ticks: TxDQ = 980
N2.C3.D1.R1.S11: wrcmd2dqsstartlatency: 04
N4.C3.D1.R0.S00: PiTxDqs: 04
N6.C2.D1.R1.S02: PiTxDqs: 26
N0.C2.D1.R0.S10: Total Delay in PI ticks: TxDQ = 968
N2.C3.D1.R1.S11: RdPtrOffsetTxDq: 05
N4.C3.D1.R0.S01: wrcmd2dqsstartlatency: 04
N6.C2.D1.R1.S03: wrcmd2dqsstartlatency: 04
N0.C2.D1.R0.S11: Total Delay in PI ticks: TxDQ = 958
N2.C3.D1.R1.S11: RdPtrOffsetTxDqs: 07
N4.C3.D1.R0.S01: RdPtrOffsetTxDq: 06
N6.C2.D1.R1.S03: RdPtrOffsetTxDq: 05
N0.C2.D1.R0.S12: Total Delay in PI ticks: TxDQ = 939
N2.C3.D1.R1.S11: PiTxDqs: 29
N4.C3.D1.R0.S01: RdPtrOffsetTxDqs: 07
N6.C2.D1.R1.S03: RdPtrOffsetTxDqs: 07
N0.C2.D1.R0.S13: Total Delay in PI ticks: TxDQ = 902
N2.C3.D1.R1.S12: wrcmd2dqsstartlatency: 04
N4.C3.D1.R0.S01: PiTxDqs: 55
N6.C2.D1.R1.S03: PiTxDqs: 11
N0.C2.D1.R0.S14: Total Delay in PI ticks: TxDQ = 928
N2.C3.D1.R1.S12: RdPtrOffsetTxDq: 05
N4.C3.D1.R0.S02: wrcmd2dqsstartlatency: 04
N6.C2.D1.R1.S04: wrcmd2dqsstartlatency: 04
N0.C2.D1.R0.S15: Total Delay in PI ticks: TxDQ = 929
N2.C3.D1.R1.S12: RdPtrOffsetTxDqs: 07
N4.C3.D1.R0.S02: RdPtrOffsetTxDq: 06
N6.C2.D1.R1.S04: RdPtrOffsetTxDq: 05
N0.C2.D1.R0.S16: Total Delay in PI ticks: TxDQ = 945
N2.C3.D1.R1.S12: PiTxDqs: 16
N4.C3.D1.R0.S02: RdPtrOffsetTxDqs: 07
N6.C2.D1.R1.S04: RdPtrOffsetTxDqs: 06
N0.C2.D1.R0.S17: Total Delay in PI ticks: TxDQ = 917
N2.C3.D1.R1.S13: wrcmd2dqsstartlatency: 04
N4.C3.D1.R0.S02: PiTxDqs: 42
N6.C2.D1.R1.S04: PiTxDqs: 33
N0.C2.D1.R1.S00: wrcmd2dqsstartlatency: 04
N2.C3.D1.R1.S13: RdPtrOffsetTxDq: 05
N4.C3.D1.R0.S03: wrcmd2dqsstartlatency: 04
N6.C2.D1.R1.S05: wrcmd2dqsstartlatency: 04
N0.C2.D1.R1.S00: RdPtrOffsetTxDq: 06
N2.C3.D1.R1.S13: RdPtrOffsetTxDqs: 06
N4.C3.D1.R0.S03: RdPtrOffsetTxDq: 05
N6.C2.D1.R1.S05: RdPtrOffsetTxDq: 05
N0.C2.D1.R1.S00: RdPtrOffsetTxDqs: 07
N2.C3.D1.R1.S13: PiTxDqs: 44
N4.C3.D1.R0.S03: RdPtrOffsetTxDqs: 07
N6.C2.D1.R1.S05: RdPtrOffsetTxDqs: 07
N0.C2.D1.R1.S00: PiTxDqs: 52
N2.C3.D1.R1.S14: wrcmd2dqsstartlatency: 04
N4.C3.D1.R0.S03: PiTxDqs: 27
N6.C2.D1.R1.S05: PiTxDqs: 00
N0.C2.D1.R1.S01: wrcmd2dqsstartlatency: 04
N2.C3.D1.R1.S14: RdPtrOffsetTxDq: 05
N4.C3.D1.R0.S04: wrcmd2dqsstartlatency: 04
N6.C2.D1.R1.S06: wrcmd2dqsstartlatency: 04
N0.C2.D1.R1.S01: RdPtrOffsetTxDq: 06
N2.C3.D1.R1.S14: RdPtrOffsetTxDqs: 06
N4.C3.D1.R0.S04: RdPtrOffsetTxDq: 05
N6.C2.D1.R1.S06: RdPtrOffsetTxDq: 05
N0.C2.D1.R1.S01: RdPtrOffsetTxDqs: 07
N2.C3.D1.R1.S14: PiTxDqs: 57
N4.C3.D1.R0.S04: RdPtrOffsetTxDqs: 06
N6.C2.D1.R1.S06: RdPtrOffsetTxDqs: 06
N0.C2.D1.R1.S01: PiTxDqs: 40
N2.C3.D1.R1.S15: wrcmd2dqsstartlatency: 04
N4.C3.D1.R0.S04: PiTxDqs: 57
N6.C2.D1.R1.S06: PiTxDqs: 60
N0.C2.D1.R1.S02: wrcmd2dqsstartlatency: 04
N2.C3.D1.R1.S15: RdPtrOffsetTxDq: 05
N4.C3.D1.R0.S05: wrcmd2dqsstartlatency: 04
N6.C2.D1.R1.S07: wrcmd2dqsstartlatency: 04
N0.C2.D1.R1.S02: RdPtrOffsetTxDq: 05
N2.C3.D1.R1.S15: RdPtrOffsetTxDqs: 07
N4.C3.D1.R0.S05: RdPtrOffsetTxDq: 05
N6.C2.D1.R1.S07: RdPtrOffsetTxDq: 05
N0.C2.D1.R1.S02: RdPtrOffsetTxDqs: 07
N2.C3.D1.R1.S15: PiTxDqs: 07
N4.C3.D1.R0.S05: RdPtrOffsetTxDqs: 07
N6.C2.D1.R1.S07: RdPtrOffsetTxDqs: 07
N0.C2.D1.R1.S02: PiTxDqs: 29
N2.C3.D1.R1.S16: wrcmd2dqsstartlatency: 04
N4.C3.D1.R0.S05: PiTxDqs: 03
N6.C2.D1.R1.S07: PiTxDqs: 20
N0.C2.D1.R1.S03: wrcmd2dqsstartlatency: 04
N2.C3.D1.R1.S16: RdPtrOffsetTxDq: 05
N4.C3.D1.R0.S06: wrcmd2dqsstartlatency: 04
N6.C2.D1.R1.S08: wrcmd2dqsstartlatency: 04
N0.C2.D1.R1.S03: RdPtrOffsetTxDq: 05
N2.C3.D1.R1.S16: RdPtrOffsetTxDqs: 07
N4.C3.D1.R0.S06: RdPtrOffsetTxDq: 05
N6.C2.D1.R1.S08: RdPtrOffsetTxDq: 05
N0.C2.D1.R1.S03: RdPtrOffsetTxDqs: 07
N2.C3.D1.R1.S16: PiTxDqs: 25
N4.C3.D1.R0.S06: RdPtrOffsetTxDqs: 07
N6.C2.D1.R1.S08: RdPtrOffsetTxDqs: 06
N0.C2.D1.R1.S03: PiTxDqs: 12
N2.C3.D1.R1.S17: wrcmd2dqsstartlatency: 04
N4.C3.D1.R0.S06: PiTxDqs: 21
N6.C2.D1.R1.S08: PiTxDqs: 47
N0.C2.D1.R1.S04: wrcmd2dqsstartlatency: 04
N2.C3.D1.R1.S17: RdPtrOffsetTxDq: 05
N4.C3.D1.R0.S07: wrcmd2dqsstartlatency: 04
N6.C2.D1.R1.S09: wrcmd2dqsstartlatency: 04
N0.C2.D1.R1.S04: RdPtrOffsetTxDq: 05
N2.C3.D1.R1.S17: RdPtrOffsetTxDqs: 06
N4.C3.D1.R0.S07: RdPtrOffsetTxDq: 05
N6.C2.D1.R1.S09: RdPtrOffsetTxDq: 06
N0.C2.D1.R1.S04: RdPtrOffsetTxDqs: 06
N2.C3.D1.R1.S17: PiTxDqs: 58
N4.C3.D1.R0.S07: RdPtrOffsetTxDqs: 07
N6.C2.D1.R1.S09: RdPtrOffsetTxDqs: 07
N0.C2.D1.R1.S04: PiTxDqs: 37
N2.C3.D1.R1.S00: RdPtrOffsetTxDq: 07
N4.C3.D1.R0.S07: PiTxDqs: 36
N6.C2.D1.R1.S09: PiTxDqs: 48
N0.C2.D1.R1.S05: wrcmd2dqsstartlatency: 04
N2.C3.D1.R1.S01: RdPtrOffsetTxDq: 07
N4.C3.D1.R0.S08: wrcmd2dqsstartlatency: 04
N6.C2.D1.R1.S10: wrcmd2dqsstartlatency: 04
N0.C2.D1.R1.S05: RdPtrOffsetTxDq: 05
N2.C3.D1.R1.S02: RdPtrOffsetTxDq: 06
N4.C3.D1.R0.S08: RdPtrOffsetTxDq: 05
N6.C2.D1.R1.S10: RdPtrOffsetTxDq: 06
N0.C2.D1.R1.S05: RdPtrOffsetTxDqs: 07
N2.C3.D1.R1.S03: RdPtrOffsetTxDq: 06
N4.C3.D1.R0.S08: RdPtrOffsetTxDqs: 07
N6.C2.D1.R1.S10: RdPtrOffsetTxDqs: 07
N0.C2.D1.R1.S05: PiTxDqs: 01
N2.C3.D1.R1.S04: RdPtrOffsetTxDq: 06
N4.C3.D1.R0.S08: PiTxDqs: 07
N6.C2.D1.R1.S10: PiTxDqs: 36
N0.C2.D1.R1.S06: wrcmd2dqsstartlatency: 04
N2.C3.D1.R1.S05: RdPtrOffsetTxDq: 06
N4.C3.D1.R0.S09: wrcmd2dqsstartlatency: 04
N6.C2.D1.R1.S11: wrcmd2dqsstartlatency: 04
N0.C2.D1.R1.S06: RdPtrOffsetTxDq: 05
N2.C3.D1.R1.S06: RdPtrOffsetTxDq: 06
N4.C3.D1.R0.S09: RdPtrOffsetTxDq: 06
N6.C2.D1.R1.S11: RdPtrOffsetTxDq: 05
N0.C2.D1.R1.S06: RdPtrOffsetTxDqs: 06
N2.C3.D1.R1.S07: RdPtrOffsetTxDq: 06
N4.C3.D1.R0.S09: RdPtrOffsetTxDqs: 08
N6.C2.D1.R1.S11: RdPtrOffsetTxDqs: 07
N0.C2.D1.R1.S06: PiTxDqs: 60
N2.C3.D1.R1.S08: RdPtrOffsetTxDq: 06
N4.C3.D1.R0.S09: PiTxDqs: 04
N6.C2.D1.R1.S11: PiTxDqs: 28
N0.C2.D1.R1.S07: wrcmd2dqsstartlatency: 04
N2.C3.D1.R1.S09: RdPtrOffsetTxDq: 07
N4.C3.D1.R0.S10: wrcmd2dqsstartlatency: 04
N6.C2.D1.R1.S12: wrcmd2dqsstartlatency: 04
N0.C2.D1.R1.S07: RdPtrOffsetTxDq: 05
N2.C3.D1.R1.S10: RdPtrOffsetTxDq: 07
N4.C3.D1.R0.S10: RdPtrOffsetTxDq: 06
N6.C2.D1.R1.S12: RdPtrOffsetTxDq: 05
N0.C2.D1.R1.S07: RdPtrOffsetTxDqs: 07
N2.C3.D1.R1.S11: RdPtrOffsetTxDq: 06
N4.C3.D1.R0.S10: RdPtrOffsetTxDqs: 07
N6.C2.D1.R1.S12: RdPtrOffsetTxDqs: 07
N0.C2.D1.R1.S07: PiTxDqs: 18
N2.C3.D1.R1.S12: RdPtrOffsetTxDq: 06
N4.C3.D1.R0.S10: PiTxDqs: 56
N6.C2.D1.R1.S12: PiTxDqs: 15
N0.C2.D1.R1.S08: wrcmd2dqsstartlatency: 04
N2.C3.D1.R1.S13: RdPtrOffsetTxDq: 06
N4.C3.D1.R0.S11: wrcmd2dqsstartlatency: 04
N6.C2.D1.R1.S13: wrcmd2dqsstartlatency: 04
N0.C2.D1.R1.S08: RdPtrOffsetTxDq: 05
N2.C3.D1.R1.S14: RdPtrOffsetTxDq: 06
N4.C3.D1.R0.S11: RdPtrOffsetTxDq: 06
N6.C2.D1.R1.S13: RdPtrOffsetTxDq: 05
N0.C2.D1.R1.S08: RdPtrOffsetTxDqs: 06
N2.C3.D1.R1.S15: RdPtrOffsetTxDq: 06
N4.C3.D1.R0.S11: RdPtrOffsetTxDqs: 07
N6.C2.D1.R1.S13: RdPtrOffsetTxDqs: 06
N0.C2.D1.R1.S08: PiTxDqs: 49
N2.C3.D1.R1.S16: RdPtrOffsetTxDq: 06
N4.C3.D1.R0.S11: PiTxDqs: 42
N6.C2.D1.R1.S13: PiTxDqs: 34
N0.C2.D1.R1.S09: wrcmd2dqsstartlatency: 04
N2.C3.D1.R1.S17: RdPtrOffsetTxDq: 06
N4.C3.D1.R0.S12: wrcmd2dqsstartlatency: 04
N6.C2.D1.R1.S14: wrcmd2dqsstartlatency: 04
N0.C2.D1.R1.S09: RdPtrOffsetTxDq: 06
N2.C3.D1.R1.S00: RdPtrOffsetTxDq: 08
N4.C3.D1.R0.S12: RdPtrOffsetTxDq: 05
N6.C2.D1.R1.S14: RdPtrOffsetTxDq: 05
N0.C2.D1.R1.S09: RdPtrOffsetTxDqs: 07
N2.C3.D1.R1.S01: RdPtrOffsetTxDq: 08
N4.C3.D1.R0.S12: RdPtrOffsetTxDqs: 07
N6.C2.D1.R1.S14: RdPtrOffsetTxDqs: 06
N0.C2.D1.R1.S09: PiTxDqs: 54
N2.C3.D1.R1.S02: RdPtrOffsetTxDq: 07
N4.C3.D1.R0.S12: PiTxDqs: 31
N6.C2.D1.R1.S14: PiTxDqs: 62
N0.C2.D1.R1.S10: wrcmd2dqsstartlatency: 04
N2.C3.D1.R1.S03: RdPtrOffsetTxDq: 07
N4.C3.D1.R0.S13: wrcmd2dqsstartlatency: 04
N6.C2.D1.R1.S15: wrcmd2dqsstartlatency: 04
N0.C2.D1.R1.S10: RdPtrOffsetTxDq: 06
N2.C3.D1.R1.S04: RdPtrOffsetTxDq: 07
N4.C3.D1.R0.S13: RdPtrOffsetTxDq: 05
N6.C2.D1.R1.S15: RdPtrOffsetTxDq: 05
N0.C2.D1.R1.S10: RdPtrOffsetTxDqs: 07
N2.C3.D1.R1.S05: RdPtrOffsetTxDq: 07
N4.C3.D1.R0.S13: RdPtrOffsetTxDqs: 06
N6.C2.D1.R1.S15: RdPtrOffsetTxDqs: 06
N0.C2.D1.R1.S10: PiTxDqs: 41
N2.C3.D1.R1.S06: RdPtrOffsetTxDq: 07
N4.C3.D1.R0.S13: PiTxDqs: 55
N6.C2.D1.R1.S15: PiTxDqs: 62
N0.C2.D1.R1.S11: wrcmd2dqsstartlatency: 04
N2.C3.D1.R1.S07: RdPtrOffsetTxDq: 07
N4.C3.D1.R0.S14: wrcmd2dqsstartlatency: 04
N6.C2.D1.R1.S16: wrcmd2dqsstartlatency: 04
N0.C2.D1.R1.S11: RdPtrOffsetTxDq: 05
N2.C3.D1.R1.S08: RdPtrOffsetTxDq: 07
N4.C3.D1.R0.S14: RdPtrOffsetTxDq: 05
N6.C2.D1.R1.S16: RdPtrOffsetTxDq: 05
N0.C2.D1.R1.S11: RdPtrOffsetTxDqs: 07
N2.C3.D1.R1.S09: RdPtrOffsetTxDq: 08
N4.C3.D1.R0.S14: RdPtrOffsetTxDqs: 07
N6.C2.D1.R1.S16: RdPtrOffsetTxDqs: 07
N0.C2.D1.R1.S11: PiTxDqs: 31
N2.C3.D1.R1.S10: RdPtrOffsetTxDq: 08
N4.C3.D1.R0.S14: PiTxDqs: 07
N6.C2.D1.R1.S16: PiTxDqs: 20
N0.C2.D1.R1.S12: wrcmd2dqsstartlatency: 04
N2.C3.D1.R1.S11: RdPtrOffsetTxDq: 07
N4.C3.D1.R0.S15: wrcmd2dqsstartlatency: 04
N6.C2.D1.R1.S17: wrcmd2dqsstartlatency: 04
N0.C2.D1.R1.S12: RdPtrOffsetTxDq: 05
N2.C3.D1.R1.S12: RdPtrOffsetTxDq: 07
N4.C3.D1.R0.S15: RdPtrOffsetTxDq: 05
N6.C2.D1.R1.S17: RdPtrOffsetTxDq: 05
N0.C2.D1.R1.S12: RdPtrOffsetTxDqs: 07
N2.C3.D1.R1.S13: RdPtrOffsetTxDq: 07
N4.C3.D1.R0.S15: RdPtrOffsetTxDqs: 07
N6.C2.D1.R1.S17: RdPtrOffsetTxDqs: 06
N0.C2.D1.R1.S12: PiTxDqs: 13
N2.C3.D1.R1.S14: RdPtrOffsetTxDq: 07
N4.C3.D1.R0.S15: PiTxDqs: 20
N6.C2.D1.R1.S17: PiTxDqs: 48
N0.C2.D1.R1.S13: wrcmd2dqsstartlatency: 04
N2.C3.D1.R1.S15: RdPtrOffsetTxDq: 07
N4.C3.D1.R0.S16: wrcmd2dqsstartlatency: 04
N6.C2.D1.R1.S00: RdPtrOffsetTxDq: 07
N0.C2.D1.R1.S13: RdPtrOffsetTxDq: 05
N2.C3.D1.R1.S16: RdPtrOffsetTxDq: 07
N4.C3.D1.R0.S16: RdPtrOffsetTxDq: 05
N6.C2.D1.R1.S01: RdPtrOffsetTxDq: 07
N0.C2.D1.R1.S13: RdPtrOffsetTxDqs: 06
N2.C3.D1.R1.S17: RdPtrOffsetTxDq: 07
N4.C3.D1.R0.S16: RdPtrOffsetTxDqs: 07
N6.C2.D1.R1.S02: RdPtrOffsetTxDq: 06
N0.C2.D1.R1.S13: PiTxDqs: 39
N2.C3.D1.R1.S00: Total Delay in PI ticks: TxDQ = 984
N4.C3.D1.R0.S16: PiTxDqs: 36
N6.C2.D1.R1.S03: RdPtrOffsetTxDq: 06
N0.C2.D1.R1.S14: wrcmd2dqsstartlatency: 04
N2.C3.D1.R1.S01: Total Delay in PI ticks: TxDQ = 968
N4.C3.D1.R0.S17: wrcmd2dqsstartlatency: 04
N6.C2.D1.R1.S04: RdPtrOffsetTxDq: 06
N0.C2.D1.R1.S14: RdPtrOffsetTxDq: 05
N2.C3.D1.R1.S02: Total Delay in PI ticks: TxDQ = 955
N4.C3.D1.R0.S17: RdPtrOffsetTxDq: 05
N6.C2.D1.R1.S05: RdPtrOffsetTxDq: 06
N0.C2.D1.R1.S14: RdPtrOffsetTxDqs: 07
N2.C3.D1.R1.S03: Total Delay in PI ticks: TxDQ = 942
N4.C3.D1.R0.S17: RdPtrOffsetTxDqs: 07
N6.C2.D1.R1.S06: RdPtrOffsetTxDq: 06
N0.C2.D1.R1.S14: PiTxDqs: 00
N2.C3.D1.R1.S04: Total Delay in PI ticks: TxDQ = 907
N4.C3.D1.R0.S17: PiTxDqs: 08
N6.C2.D1.R1.S07: RdPtrOffsetTxDq: 06
N0.C2.D1.R1.S15: wrcmd2dqsstartlatency: 04
N2.C3.D1.R1.S05: Total Delay in PI ticks: TxDQ = 922
N4.C3.D1.R0.S00: RdPtrOffsetTxDq: 07
N6.C2.D1.R1.S08: RdPtrOffsetTxDq: 06
N0.C2.D1.R1.S15: RdPtrOffsetTxDq: 05
N2.C3.D1.R1.S06: Total Delay in PI ticks: TxDQ = 934
N4.C3.D1.R0.S01: RdPtrOffsetTxDq: 07
N6.C2.D1.R1.S09: RdPtrOffsetTxDq: 07
N0.C2.D1.R1.S15: RdPtrOffsetTxDqs: 06
N2.C3.D1.R1.S07: Total Delay in PI ticks: TxDQ = 953
N4.C3.D1.R0.S02: RdPtrOffsetTxDq: 07
N6.C2.D1.R1.S10: RdPtrOffsetTxDq: 07
N0.C2.D1.R1.S15: PiTxDqs: 62
N2.C3.D1.R1.S08: Total Delay in PI ticks: TxDQ = 921
N4.C3.D1.R0.S03: RdPtrOffsetTxDq: 06
N6.C2.D1.R1.S11: RdPtrOffsetTxDq: 06
N0.C2.D1.R1.S16: wrcmd2dqsstartlatency: 04
N2.C3.D1.R1.S09: Total Delay in PI ticks: TxDQ = 982
N4.C3.D1.R0.S04: RdPtrOffsetTxDq: 06
N6.C2.D1.R1.S12: RdPtrOffsetTxDq: 06
N0.C2.D1.R1.S16: RdPtrOffsetTxDq: 05
N2.C3.D1.R1.S10: Total Delay in PI ticks: TxDQ = 968
N4.C3.D1.R0.S05: RdPtrOffsetTxDq: 06
N6.C2.D1.R1.S13: RdPtrOffsetTxDq: 06
N0.C2.D1.R1.S16: RdPtrOffsetTxDqs: 07
N2.C3.D1.R1.S11: Total Delay in PI ticks: TxDQ = 957
N4.C3.D1.R0.S06: RdPtrOffsetTxDq: 06
N6.C2.D1.R1.S14: RdPtrOffsetTxDq: 06
N0.C2.D1.R1.S16: PiTxDqs: 23
N2.C3.D1.R1.S12: Total Delay in PI ticks: TxDQ = 942
N4.C3.D1.R0.S07: RdPtrOffsetTxDq: 06
N6.C2.D1.R1.S15: RdPtrOffsetTxDq: 06
N0.C2.D1.R1.S17: wrcmd2dqsstartlatency: 04
N2.C3.D1.R1.S13: Total Delay in PI ticks: TxDQ = 907
N4.C3.D1.R0.S08: RdPtrOffsetTxDq: 06
N6.C2.D1.R1.S16: RdPtrOffsetTxDq: 06
N0.C2.D1.R1.S17: RdPtrOffsetTxDq: 05
N2.C3.D1.R1.S14: Total Delay in PI ticks: TxDQ = 921
N4.C3.D1.R0.S09: RdPtrOffsetTxDq: 07
N6.C2.D1.R1.S17: RdPtrOffsetTxDq: 06
N0.C2.D1.R1.S17: RdPtrOffsetTxDqs: 06
N2.C3.D1.R1.S15: Total Delay in PI ticks: TxDQ = 935
N4.C3.D1.R0.S10: RdPtrOffsetTxDq: 07
N6.C2.D1.R1.S00: RdPtrOffsetTxDq: 08
N0.C2.D1.R1.S17: PiTxDqs: 50
N2.C3.D1.R1.S16: Total Delay in PI ticks: TxDQ = 952
N4.C3.D1.R0.S11: RdPtrOffsetTxDq: 07
N6.C2.D1.R1.S01: RdPtrOffsetTxDq: 08
N0.C2.D1.R1.S00: RdPtrOffsetTxDq: 07
N2.C3.D1.R1.S17: Total Delay in PI ticks: TxDQ = 920
N4.C3.D1.R0.S12: RdPtrOffsetTxDq: 06
N6.C2.D1.R1.S02: RdPtrOffsetTxDq: 07
N0.C2.D1.R1.S01: RdPtrOffsetTxDq: 07
N2.C3: Calculating Optimimum DQ/DQS Values
N4.C3.D1.R0.S13: RdPtrOffsetTxDq: 06
N6.C2.D1.R1.S03: RdPtrOffsetTxDq: 07
N0.C2.D1.R1.S02: RdPtrOffsetTxDq: 06
N4.C3.D1.R0.S14: RdPtrOffsetTxDq: 06
N6.C2.D1.R1.S04: RdPtrOffsetTxDq: 07
N0.C2.D1.R1.S03: RdPtrOffsetTxDq: 06
START_DATA_TX_DQ
N4.C3.D1.R0.S15: RdPtrOffsetTxDq: 06
N6.C2.D1.R1.S05: RdPtrOffsetTxDq: 07
N0.C2.D1.R1.S04: RdPtrOffsetTxDq: 06
N2.C3.S00: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 009, RdPtrOffsetTxDqs = 009
N4.C3.D1.R0.S16: RdPtrOffsetTxDq: 06
N6.C2.D1.R1.S06: RdPtrOffsetTxDq: 07
N0.C2.D1.R1.S05: RdPtrOffsetTxDq: 06
N2.C3.S00: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 009, RdPtrOffsetTxDqs = 009
N4.C3.D1.R0.S17: RdPtrOffsetTxDq: 06
N6.C2.D1.R1.S07: RdPtrOffsetTxDq: 07
N0.C2.D1.R1.S06: RdPtrOffsetTxDq: 06
N2.C3.S01: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 009, RdPtrOffsetTxDqs = 009
N4.C3.D1.R0.S00: RdPtrOffsetTxDq: 08
N6.C2.D1.R1.S08: RdPtrOffsetTxDq: 07
N0.C2.D1.R1.S07: RdPtrOffsetTxDq: 06
N2.C3.S01: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 009, RdPtrOffsetTxDqs = 009
N4.C3.D1.R0.S01: RdPtrOffsetTxDq: 08
N6.C2.D1.R1.S09: RdPtrOffsetTxDq: 08
N0.C2.D1.R1.S08: RdPtrOffsetTxDq: 06
N2.C3.S02: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 009
N4.C3.D1.R0.S02: RdPtrOffsetTxDq: 08
N6.C2.D1.R1.S10: RdPtrOffsetTxDq: 08
N0.C2.D1.R1.S09: RdPtrOffsetTxDq: 07
N2.C3.S02: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 009
N4.C3.D1.R0.S03: RdPtrOffsetTxDq: 07
N6.C2.D1.R1.S11: RdPtrOffsetTxDq: 07
N0.C2.D1.R1.S10: RdPtrOffsetTxDq: 07
N2.C3.S03: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 009
N4.C3.D1.R0.S04: RdPtrOffsetTxDq: 07
N6.C2.D1.R1.S12: RdPtrOffsetTxDq: 07
N0.C2.D1.R1.S11: RdPtrOffsetTxDq: 06
N2.C3.S03: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 009
N4.C3.D1.R0.S05: RdPtrOffsetTxDq: 07
N6.C2.D1.R1.S13: RdPtrOffsetTxDq: 07
N0.C2.D1.R1.S12: RdPtrOffsetTxDq: 06
N2.C3.S04: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 008
N4.C3.D1.R0.S06: RdPtrOffsetTxDq: 07
N6.C2.D1.R1.S14: RdPtrOffsetTxDq: 07
N0.C2.D1.R1.S13: RdPtrOffsetTxDq: 06
N2.C3.S04: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 008
N4.C3.D1.R0.S07: RdPtrOffsetTxDq: 07
N6.C2.D1.R1.S15: RdPtrOffsetTxDq: 07
N0.C2.D1.R1.S14: RdPtrOffsetTxDq: 06
N2.C3.S05: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 008
N4.C3.D1.R0.S08: RdPtrOffsetTxDq: 07
N6.C2.D1.R1.S16: RdPtrOffsetTxDq: 07
N0.C2.D1.R1.S15: RdPtrOffsetTxDq: 06
N2.C3.S05: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 008
N4.C3.D1.R0.S09: RdPtrOffsetTxDq: 08
N6.C2.D1.R1.S17: RdPtrOffsetTxDq: 07
N0.C2.D1.R1.S16: RdPtrOffsetTxDq: 06
N2.C3.S06: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 009
N4.C3.D1.R0.S10: RdPtrOffsetTxDq: 08
N6.C2.D1.R1.S00: Total Delay in PI ticks: TxDQ = 979
N0.C2.D1.R1.S17: RdPtrOffsetTxDq: 06
N2.C3.S06: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 009
N4.C3.D1.R0.S11: RdPtrOffsetTxDq: 08
N6.C2.D1.R1.S01: Total Delay in PI ticks: TxDQ = 963
N0.C2.D1.R1.S00: RdPtrOffsetTxDq: 08
N2.C3.S07: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 009
N4.C3.D1.R0.S12: RdPtrOffsetTxDq: 07
N6.C2.D1.R1.S02: Total Delay in PI ticks: TxDQ = 954
N0.C2.D1.R1.S01: RdPtrOffsetTxDq: 08
N2.C3.S07: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 009
N4.C3.D1.R0.S13: RdPtrOffsetTxDq: 07
N6.C2.D1.R1.S03: Total Delay in PI ticks: TxDQ = 939
N0.C2.D1.R1.S02: RdPtrOffsetTxDq: 07
N2.C3.S08: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 008
N4.C3.D1.R0.S14: RdPtrOffsetTxDq: 07
N6.C2.D1.R1.S04: Total Delay in PI ticks: TxDQ = 897
N0.C2.D1.R1.S03: RdPtrOffsetTxDq: 07
N2.C3.S08: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 008
N4.C3.D1.R0.S15: RdPtrOffsetTxDq: 07
N6.C2.D1.R1.S05: Total Delay in PI ticks: TxDQ = 928
N0.C2.D1.R1.S04: RdPtrOffsetTxDq: 07
N2.C3.D0.R0.S00: TxDqs: plus1 = 1, minus1 = 0, PI = 51, DB = 1
N4.C3.D1.R0.S16: RdPtrOffsetTxDq: 07
N6.C2.D1.R1.S06: Total Delay in PI ticks: TxDQ = 923
N0.C2.D1.R1.S05: RdPtrOffsetTxDq: 07
N2.C3.D0.R0.S00: TxDq : plus1 = 1, minus1 = 0, PI = 18, DB = 0
N4.C3.D1.R0.S17: RdPtrOffsetTxDq: 07
N6.C2.D1.R1.S07: Total Delay in PI ticks: TxDQ = 947
N0.C2.D1.R1.S06: RdPtrOffsetTxDq: 07
N2.C3.D0.R0.S01: TxDqs: plus1 = 1, minus1 = 0, PI = 35, DB = 0
N4.C3.D1.R0.S00: Total Delay in PI ticks: TxDQ = 993
N6.C2.D1.R1.S08: Total Delay in PI ticks: TxDQ = 909
N0.C2.D1.R1.S07: RdPtrOffsetTxDq: 07
N2.C3.D0.R0.S01: TxDq : plus1 = 1, minus1 = 0, PI = 03, DB = 1
N4.C3.D1.R0.S01: Total Delay in PI ticks: TxDQ = 979
N6.C2.D1.R1.S09: Total Delay in PI ticks: TxDQ = 974
N0.C2.D1.R1.S08: RdPtrOffsetTxDq: 07
N2.C3.D0.R0.S02: TxDqs: plus1 = 1, minus1 = 0, PI = 24, DB = 0
N4.C3.D1.R0.S02: Total Delay in PI ticks: TxDQ = 967
N6.C2.D1.R1.S10: Total Delay in PI ticks: TxDQ = 963
N0.C2.D1.R1.S09: RdPtrOffsetTxDq: 08
N2.C3.D0.R0.S02: TxDq : plus1 = 1, minus1 = 0, PI = 56, DB = 1
N4.C3.D1.R0.S03: Total Delay in PI ticks: TxDQ = 952
N6.C2.D1.R1.S11: Total Delay in PI ticks: TxDQ = 956
N0.C2.D1.R1.S10: RdPtrOffsetTxDq: 08
N2.C3.D0.R0.S03: TxDqs: plus1 = 1, minus1 = 0, PI = 09, DB = 1
N4.C3.D1.R0.S04: Total Delay in PI ticks: TxDQ = 916
N6.C2.D1.R1.S12: Total Delay in PI ticks: TxDQ = 941
N0.C2.D1.R1.S11: RdPtrOffsetTxDq: 07
N2.C3.D0.R0.S03: TxDq : plus1 = 1, minus1 = 0, PI = 40, DB = 0
N4.C3.D1.R0.S05: Total Delay in PI ticks: TxDQ = 929
N6.C2.D1.R1.S13: Total Delay in PI ticks: TxDQ = 897
N0.C2.D1.R1.S12: RdPtrOffsetTxDq: 07
N2.C3.D0.R0.S04: TxDqs: plus1 = 1, minus1 = 0, PI = 39, DB = 0
N4.C3.D1.R0.S06: Total Delay in PI ticks: TxDQ = 945
N6.C2.D1.R1.S14: Total Delay in PI ticks: TxDQ = 926
N0.C2.D1.R1.S13: RdPtrOffsetTxDq: 07
N2.C3.D0.R0.S04: TxDq : plus1 = 1, minus1 = 0, PI = 07, DB = 1
N4.C3.D1.R0.S07: Total Delay in PI ticks: TxDQ = 961
N6.C2.D1.R1.S15: Total Delay in PI ticks: TxDQ = 925
N0.C2.D1.R1.S14: RdPtrOffsetTxDq: 07
N2.C3.D0.R0.S05: TxDqs: plus1 = 1, minus1 = 0, PI = 52, DB = 1
N4.C3.D1.R0.S08: Total Delay in PI ticks: TxDQ = 931
N6.C2.D1.R1.S16: Total Delay in PI ticks: TxDQ = 947
N0.C2.D1.R1.S15: RdPtrOffsetTxDq: 07
N2.C3.D0.R0.S05: TxDq : plus1 = 1, minus1 = 0, PI = 20, DB = 0
N4.C3.D1.R0.S09: Total Delay in PI ticks: TxDQ = 991
N6.C2.D1.R1.S17: Total Delay in PI ticks: TxDQ = 909
N0.C2.D1.R1.S16: RdPtrOffsetTxDq: 07
N2.C3.D0.R0.S06: TxDqs: plus1 = 1, minus1 = 0, PI = 04, DB = 1
N4.C3.D1.R0.S10: Total Delay in PI ticks: TxDQ = 979
N6.C2: Calculating Optimimum DQ/DQS Values
N0.C2.D1.R1.S17: RdPtrOffsetTxDq: 07
N2.C3.D0.R0.S06: TxDq : plus1 = 1, minus1 = 0, PI = 36, DB = 0
N4.C3.D1.R0.S11: Total Delay in PI ticks: TxDQ = 965
N0.C2.D1.R1.S00: Total Delay in PI ticks: TxDQ = 980
N2.C3.D0.R0.S07: TxDqs: plus1 = 1, minus1 = 0, PI = 19, DB = 0
N4.C3.D1.R0.S12: Total Delay in PI ticks: TxDQ = 955
START_DATA_TX_DQ
N0.C2.D1.R1.S01: Total Delay in PI ticks: TxDQ = 965
N2.C3.D0.R0.S07: TxDq : plus1 = 1, minus1 = 0, PI = 50, DB = 1
N4.C3.D1.R0.S13: Total Delay in PI ticks: TxDQ = 916
N6.C2.S00: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 009, RdPtrOffsetTxDqs = 009
N0.C2.D1.R1.S02: Total Delay in PI ticks: TxDQ = 955
N2.C3.D0.R0.S08: TxDqs: plus1 = 1, minus1 = 0, PI = 57, DB = 1
N4.C3.D1.R0.S14: Total Delay in PI ticks: TxDQ = 931
N6.C2.S00: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 009, RdPtrOffsetTxDqs = 009
N0.C2.D1.R1.S03: Total Delay in PI ticks: TxDQ = 937
N2.C3.D0.R0.S08: TxDq : plus1 = 1, minus1 = 0, PI = 25, DB = 0
N4.C3.D1.R0.S15: Total Delay in PI ticks: TxDQ = 947
N6.C2.S01: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 009
N0.C2.D1.R1.S04: Total Delay in PI ticks: TxDQ = 900
N2.C3.D0.R0.S09: TxDqs: plus1 = 1, minus1 = 0, PI = 51, DB = 1
N4.C3.D1.R0.S16: Total Delay in PI ticks: TxDQ = 961
N6.C2.S01: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 009
N0.C2.D1.R1.S05: Total Delay in PI ticks: TxDQ = 926
N2.C3.D0.R0.S09: TxDq : plus1 = 1, minus1 = 0, PI = 18, DB = 0
N4.C3.D1.R0.S17: Total Delay in PI ticks: TxDQ = 932
N6.C2.S02: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 009
N0.C2.D1.R1.S06: Total Delay in PI ticks: TxDQ = 922
N2.C3.D0.R0.S10: TxDqs: plus1 = 1, minus1 = 0, PI = 37, DB = 0
N4.C3.D1.R1.S00: wrcmd2dqsstartlatency: 04
N6.C2.S02: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 009
N0.C2.D1.R1.S07: Total Delay in PI ticks: TxDQ = 943
N2.C3.D0.R0.S10: TxDq : plus1 = 1, minus1 = 0, PI = 05, DB = 1
N4.C3.D1.R1.S00: RdPtrOffsetTxDq: 06
N6.C2.S03: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 009
N0.C2.D1.R1.S08: Total Delay in PI ticks: TxDQ = 911
N2.C3.D0.R0.S11: TxDqs: plus1 = 1, minus1 = 0, PI = 25, DB = 0
N4.C3.D1.R1.S00: RdPtrOffsetTxDqs: 08
N6.C2.S03: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 009
N0.C2.D1.R1.S09: Total Delay in PI ticks: TxDQ = 979
N2.C3.D0.R0.S11: TxDq : plus1 = 1, minus1 = 0, PI = 58, DB = 1
N4.C3.D1.R1.S00: PiTxDqs: 03
N6.C2.S04: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 007, RdPtrOffsetTxDqs = 008
N0.C2.D1.R1.S10: Total Delay in PI ticks: TxDQ = 965
N2.C3.D0.R0.S12: TxDqs: plus1 = 1, minus1 = 0, PI = 11, DB = 1
N4.C3.D1.R1.S01: wrcmd2dqsstartlatency: 04
N6.C2.S04: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 007, RdPtrOffsetTxDqs = 008
N0.C2.D1.R1.S11: Total Delay in PI ticks: TxDQ = 957
N2.C3.D0.R0.S12: TxDq : plus1 = 1, minus1 = 0, PI = 42, DB = 0
N4.C3.D1.R1.S01: RdPtrOffsetTxDq: 06
N6.C2.S05: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 008
N0.C2.D1.R1.S12: Total Delay in PI ticks: TxDQ = 938
N2.C3.D0.R0.S13: TxDqs: plus1 = 1, minus1 = 0, PI = 39, DB = 0
N4.C3.D1.R1.S01: RdPtrOffsetTxDqs: 07
N6.C2.S05: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 008
N0.C2.D1.R1.S13: Total Delay in PI ticks: TxDQ = 902
N2.C3.D0.R0.S13: TxDq : plus1 = 1, minus1 = 0, PI = 07, DB = 1
N4.C3.D1.R1.S01: PiTxDqs: 51
N6.C2.S06: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 008
N0.C2.D1.R1.S14: Total Delay in PI ticks: TxDQ = 928
N2.C3.D0.R0.S14: TxDqs: plus1 = 1, minus1 = 0, PI = 53, DB = 1
N4.C3.D1.R1.S02: wrcmd2dqsstartlatency: 04
N6.C2.S06: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 008
N0.C2.D1.R1.S15: Total Delay in PI ticks: TxDQ = 923
N2.C3.D0.R0.S14: TxDq : plus1 = 1, minus1 = 0, PI = 22, DB = 0
N4.C3.D1.R1.S02: RdPtrOffsetTxDq: 06
N6.C2.S07: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 009
N0.C2.D1.R1.S16: Total Delay in PI ticks: TxDQ = 946
N2.C3.D0.R0.S15: TxDqs: plus1 = 1, minus1 = 0, PI = 03, DB = 1
N4.C3.D1.R1.S02: RdPtrOffsetTxDqs: 07
N6.C2.S07: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 009
N0.C2.D1.R1.S17: Total Delay in PI ticks: TxDQ = 911
N2.C3.D0.R0.S15: TxDq : plus1 = 1, minus1 = 0, PI = 36, DB = 0
N4.C3.D1.R1.S02: PiTxDqs: 38
N6.C2.S08: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 008
N0.C2: Calculating Optimimum DQ/DQS Values
N2.C3.D0.R0.S16: TxDqs: plus1 = 1, minus1 = 0, PI = 20, DB = 0
N4.C3.D1.R1.S03: wrcmd2dqsstartlatency: 04
N6.C2.S08: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 008
N2.C3.D0.R0.S16: TxDq : plus1 = 1, minus1 = 0, PI = 52, DB = 1
N4.C3.D1.R1.S03: RdPtrOffsetTxDq: 05
N6.C2.D0.R0.S00: TxDqs: plus1 = 1, minus1 = 0, PI = 45, DB = 0
START_DATA_TX_DQ
N2.C3.D0.R0.S17: TxDqs: plus1 = 1, minus1 = 0, PI = 56, DB = 1
N4.C3.D1.R1.S03: RdPtrOffsetTxDqs: 07
N6.C2.D0.R0.S00: TxDq : plus1 = 1, minus1 = 0, PI = 13, DB = 1
N0.C2.S00: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 009, RdPtrOffsetTxDqs = 009
N2.C3.D0.R0.S17: TxDq : plus1 = 1, minus1 = 0, PI = 24, DB = 0
N4.C3.D1.R1.S03: PiTxDqs: 27
N6.C2.D0.R0.S01: TxDqs: plus1 = 1, minus1 = 0, PI = 31, DB = 0
N0.C2.S00: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 009, RdPtrOffsetTxDqs = 009
N2.C3.D0.R1.S00: TxDqs: plus1 = 1, minus1 = 0, PI = 51, DB = 1
N4.C3.D1.R1.S04: wrcmd2dqsstartlatency: 04
N6.C2.D0.R0.S01: TxDq : plus1 = 1, minus1 = 0, PI = 63, DB = 1
N0.C2.S01: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 009, RdPtrOffsetTxDqs = 009
N2.C3.D0.R1.S00: TxDq : plus1 = 1, minus1 = 0, PI = 18, DB = 0
N4.C3.D1.R1.S04: RdPtrOffsetTxDq: 05
N6.C2.D0.R0.S02: TxDqs: plus1 = 1, minus1 = 0, PI = 20, DB = 0
N0.C2.S01: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 009, RdPtrOffsetTxDqs = 009
N2.C3.D0.R1.S01: TxDqs: plus1 = 1, minus1 = 0, PI = 35, DB = 0
N4.C3.D1.R1.S04: RdPtrOffsetTxDqs: 06
N6.C2.D0.R0.S02: TxDq : plus1 = 1, minus1 = 0, PI = 53, DB = 1
N0.C2.S02: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 009
N2.C3.D0.R1.S01: TxDq : plus1 = 1, minus1 = 0, PI = 03, DB = 1
N4.C3.D1.R1.S04: PiTxDqs: 53
N6.C2.D0.R0.S03: TxDqs: plus1 = 1, minus1 = 0, PI = 01, DB = 1
N0.C2.S02: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 009
N2.C3.D0.R1.S02: TxDqs: plus1 = 1, minus1 = 0, PI = 24, DB = 0
N4.C3.D1.R1.S05: wrcmd2dqsstartlatency: 04
N6.C2.D0.R0.S03: TxDq : plus1 = 1, minus1 = 0, PI = 33, DB = 0
N0.C2.S03: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 009
N2.C3.D0.R1.S02: TxDq : plus1 = 1, minus1 = 0, PI = 56, DB = 1
N4.C3.D1.R1.S05: RdPtrOffsetTxDq: 05
N6.C2.D0.R0.S04: TxDqs: plus1 = 1, minus1 = 0, PI = 26, DB = 0
N0.C2.S03: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 009
N2.C3.D0.R1.S03: TxDqs: plus1 = 1, minus1 = 0, PI = 09, DB = 1
N4.C3.D1.R1.S05: RdPtrOffsetTxDqs: 07
N6.C2.D0.R0.S04: TxDq : plus1 = 1, minus1 = 0, PI = 59, DB = 1
N0.C2.S04: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 007, RdPtrOffsetTxDqs = 008
N2.C3.D0.R1.S03: TxDq : plus1 = 1, minus1 = 0, PI = 40, DB = 0
N4.C3.D1.R1.S05: PiTxDqs: 02
N6.C2.D0.R0.S05: TxDqs: plus1 = 1, minus1 = 0, PI = 56, DB = 1
N0.C2.S04: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 007, RdPtrOffsetTxDqs = 008
N2.C3.D0.R1.S04: TxDqs: plus1 = 1, minus1 = 0, PI = 39, DB = 0
N4.C3.D1.R1.S06: wrcmd2dqsstartlatency: 04
N6.C2.D0.R0.S05: TxDq : plus1 = 1, minus1 = 0, PI = 23, DB = 0
N0.C2.S05: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 008
N2.C3.D0.R1.S04: TxDq : plus1 = 1, minus1 = 0, PI = 07, DB = 1
N4.C3.D1.R1.S06: RdPtrOffsetTxDq: 05
N6.C2.D0.R0.S06: TxDqs: plus1 = 1, minus1 = 0, PI = 56, DB = 1
N0.C2.S05: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 008
N2.C3.D0.R1.S05: TxDqs: plus1 = 1, minus1 = 0, PI = 52, DB = 1
N4.C3.D1.R1.S06: RdPtrOffsetTxDqs: 07
N6.C2.D0.R0.S06: TxDq : plus1 = 1, minus1 = 0, PI = 25, DB = 0
N0.C2.S06: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 008
N2.C3.D0.R1.S05: TxDq : plus1 = 1, minus1 = 0, PI = 20, DB = 0
N4.C3.D1.R1.S06: PiTxDqs: 16
N6.C2.D0.R0.S07: TxDqs: plus1 = 1, minus1 = 0, PI = 12, DB = 1
N0.C2.S06: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 008
N2.C3.D0.R1.S06: TxDqs: plus1 = 1, minus1 = 0, PI = 04, DB = 1
N4.C3.D1.R1.S07: wrcmd2dqsstartlatency: 04
N6.C2.D0.R0.S07: TxDq : plus1 = 1, minus1 = 0, PI = 41, DB = 0
N0.C2.S07: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 009
N2.C3.D0.R1.S06: TxDq : plus1 = 1, minus1 = 0, PI = 36, DB = 0
N4.C3.D1.R1.S07: RdPtrOffsetTxDq: 05
N6.C2.D0.R0.S08: TxDqs: plus1 = 1, minus1 = 0, PI = 45, DB = 0
N0.C2.S07: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 009
N2.C3.D0.R1.S07: TxDqs: plus1 = 1, minus1 = 0, PI = 19, DB = 0
N4.C3.D1.R1.S07: RdPtrOffsetTxDqs: 07
N6.C2.D0.R0.S08: TxDq : plus1 = 1, minus1 = 0, PI = 13, DB = 1
N0.C2.S08: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 008
N2.C3.D0.R1.S07: TxDq : plus1 = 1, minus1 = 0, PI = 50, DB = 1
N4.C3.D1.R1.S07: PiTxDqs: 33
N6.C2.D0.R0.S09: TxDqs: plus1 = 1, minus1 = 0, PI = 44, DB = 0
N0.C2.S08: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 008
N2.C3.D0.R1.S08: TxDqs: plus1 = 1, minus1 = 0, PI = 57, DB = 1
N4.C3.D1.R1.S08: wrcmd2dqsstartlatency: 04
N6.C2.D0.R0.S09: TxDq : plus1 = 1, minus1 = 0, PI = 11, DB = 1
N0.C2.D0.R0.S00: TxDqs: plus1 = 1, minus1 = 0, PI = 51, DB = 1
N2.C3.D0.R1.S08: TxDq : plus1 = 1, minus1 = 0, PI = 25, DB = 0
N4.C3.D1.R1.S08: RdPtrOffsetTxDq: 05
N6.C2.D0.R0.S10: TxDqs: plus1 = 1, minus1 = 0, PI = 31, DB = 0
N0.C2.D0.R0.S00: TxDq : plus1 = 1, minus1 = 0, PI = 19, DB = 0
N2.C3.D0.R1.S09: TxDqs: plus1 = 1, minus1 = 0, PI = 51, DB = 1
N4.C3.D1.R1.S08: RdPtrOffsetTxDqs: 07
N6.C2.D0.R0.S10: TxDq : plus1 = 0, minus1 = 1, PI = 00, DB = 1
N0.C2.D0.R0.S01: TxDqs: plus1 = 1, minus1 = 0, PI = 36, DB = 0
N2.C3.D0.R1.S09: TxDq : plus1 = 1, minus1 = 0, PI = 18, DB = 0
N4.C3.D1.R1.S08: PiTxDqs: 03
N6.C2.D0.R0.S11: TxDqs: plus1 = 1, minus1 = 0, PI = 21, DB = 0
N0.C2.D0.R0.S01: TxDq : plus1 = 1, minus1 = 0, PI = 03, DB = 1
N2.C3.D0.R1.S10: TxDqs: plus1 = 1, minus1 = 0, PI = 37, DB = 0
N4.C3.D1.R1.S09: wrcmd2dqsstartlatency: 04
N6.C2.D0.R0.S11: TxDq : plus1 = 1, minus1 = 0, PI = 55, DB = 1
N0.C2.D0.R0.S02: TxDqs: plus1 = 1, minus1 = 0, PI = 26, DB = 0
N2.C3.D0.R1.S10: TxDq : plus1 = 1, minus1 = 0, PI = 05, DB = 1
N4.C3.D1.R1.S09: RdPtrOffsetTxDq: 06
N6.C2.D0.R0.S12: TxDqs: plus1 = 1, minus1 = 0, PI = 03, DB = 1
N0.C2.D0.R0.S02: TxDq : plus1 = 1, minus1 = 0, PI = 58, DB = 1
N2.C3.D0.R1.S11: TxDqs: plus1 = 1, minus1 = 0, PI = 25, DB = 0
N4.C3.D1.R1.S09: RdPtrOffsetTxDqs: 08
N6.C2.D0.R0.S12: TxDq : plus1 = 1, minus1 = 0, PI = 35, DB = 0
N0.C2.D0.R0.S03: TxDqs: plus1 = 1, minus1 = 0, PI = 08, DB = 1
N2.C3.D0.R1.S11: TxDq : plus1 = 1, minus1 = 0, PI = 58, DB = 1
N4.C3.D1.R1.S09: PiTxDqs: 01
N6.C2.D0.R0.S13: TxDqs: plus1 = 1, minus1 = 0, PI = 26, DB = 0
N0.C2.D0.R0.S03: TxDq : plus1 = 1, minus1 = 0, PI = 38, DB = 0
N2.C3.D0.R1.S12: TxDqs: plus1 = 1, minus1 = 0, PI = 11, DB = 1
N4.C3.D1.R1.S10: wrcmd2dqsstartlatency: 04
N6.C2.D0.R0.S13: TxDq : plus1 = 1, minus1 = 0, PI = 59, DB = 1
N0.C2.D0.R0.S04: TxDqs: plus1 = 1, minus1 = 0, PI = 34, DB = 0
N2.C3.D0.R1.S12: TxDq : plus1 = 1, minus1 = 0, PI = 42, DB = 0
N4.C3.D1.R1.S10: RdPtrOffsetTxDq: 06
N6.C2.D0.R0.S14: TxDqs: plus1 = 1, minus1 = 0, PI = 55, DB = 1
N0.C2.D0.R0.S04: TxDq : plus1 = 0, minus1 = 1, PI = 02, DB = 1
N2.C3.D0.R1.S13: TxDqs: plus1 = 1, minus1 = 0, PI = 39, DB = 0
N4.C3.D1.R1.S10: RdPtrOffsetTxDqs: 07
N6.C2.D0.R0.S14: TxDq : plus1 = 1, minus1 = 0, PI = 23, DB = 0
N0.C2.D0.R0.S05: TxDqs: plus1 = 1, minus1 = 0, PI = 61, DB = 1
N2.C3.D0.R1.S13: TxDq : plus1 = 1, minus1 = 0, PI = 07, DB = 1
N4.C3.D1.R1.S10: PiTxDqs: 51
N6.C2.D0.R0.S15: TxDqs: plus1 = 1, minus1 = 0, PI = 56, DB = 1
N0.C2.D0.R0.S05: TxDq : plus1 = 1, minus1 = 0, PI = 26, DB = 0
N2.C3.D0.R1.S14: TxDqs: plus1 = 1, minus1 = 0, PI = 53, DB = 1
N4.C3.D1.R1.S11: wrcmd2dqsstartlatency: 04
N6.C2.D0.R0.S15: TxDq : plus1 = 1, minus1 = 0, PI = 24, DB = 0
N0.C2.D0.R0.S06: TxDqs: plus1 = 1, minus1 = 0, PI = 59, DB = 1
N2.C3.D0.R1.S14: TxDq : plus1 = 1, minus1 = 0, PI = 22, DB = 0
N4.C3.D1.R1.S11: RdPtrOffsetTxDq: 06
N6.C2.D0.R0.S16: TxDqs: plus1 = 1, minus1 = 0, PI = 12, DB = 1
N0.C2.D0.R0.S06: TxDq : plus1 = 1, minus1 = 0, PI = 27, DB = 0
N2.C3.D0.R1.S15: TxDqs: plus1 = 1, minus1 = 0, PI = 03, DB = 1
N4.C3.D1.R1.S11: RdPtrOffsetTxDqs: 07
N6.C2.D0.R0.S16: TxDq : plus1 = 1, minus1 = 0, PI = 44, DB = 0
N0.C2.D0.R0.S07: TxDqs: plus1 = 1, minus1 = 0, PI = 16, DB = 0
N2.C3.D0.R1.S15: TxDq : plus1 = 1, minus1 = 0, PI = 36, DB = 0
N4.C3.D1.R1.S11: PiTxDqs: 40
N6.C2.D0.R0.S17: TxDqs: plus1 = 1, minus1 = 0, PI = 45, DB = 0
N0.C2.D0.R0.S07: TxDq : plus1 = 1, minus1 = 0, PI = 46, DB = 0
N2.C3.D0.R1.S16: TxDqs: plus1 = 1, minus1 = 0, PI = 20, DB = 0
N4.C3.D1.R1.S12: wrcmd2dqsstartlatency: 04
N6.C2.D0.R0.S17: TxDq : plus1 = 1, minus1 = 0, PI = 11, DB = 1
N0.C2.D0.R0.S08: TxDqs: plus1 = 1, minus1 = 0, PI = 52, DB = 1
N2.C3.D0.R1.S16: TxDq : plus1 = 1, minus1 = 0, PI = 52, DB = 1
N4.C3.D1.R1.S12: RdPtrOffsetTxDq: 05
N6.C2.D0.R1.S00: TxDqs: plus1 = 1, minus1 = 0, PI = 45, DB = 0
N0.C2.D0.R0.S08: TxDq : plus1 = 1, minus1 = 0, PI = 18, DB = 0
N2.C3.D0.R1.S17: TxDqs: plus1 = 1, minus1 = 0, PI = 56, DB = 1
N4.C3.D1.R1.S12: RdPtrOffsetTxDqs: 07
N6.C2.D0.R1.S00: TxDq : plus1 = 1, minus1 = 0, PI = 13, DB = 1
N0.C2.D0.R0.S09: TxDqs: plus1 = 1, minus1 = 0, PI = 52, DB = 1
N2.C3.D0.R1.S17: TxDq : plus1 = 1, minus1 = 0, PI = 24, DB = 0
N4.C3.D1.R1.S12: PiTxDqs: 28
N6.C2.D0.R1.S01: TxDqs: plus1 = 1, minus1 = 0, PI = 31, DB = 0
N0.C2.D0.R0.S09: TxDq : plus1 = 1, minus1 = 0, PI = 19, DB = 0
N2.C3.D1.R0.S00: TxDqs: plus1 = 1, minus1 = 0, PI = 58, DB = 1
N4.C3.D1.R1.S13: wrcmd2dqsstartlatency: 04
N6.C2.D0.R1.S01: TxDq : plus1 = 1, minus1 = 0, PI = 63, DB = 1
N0.C2.D0.R0.S10: TxDqs: plus1 = 1, minus1 = 0, PI = 38, DB = 0
N2.C3.D1.R0.S00: TxDq : plus1 = 1, minus1 = 0, PI = 26, DB = 0
N4.C3.D1.R1.S13: RdPtrOffsetTxDq: 05
N6.C2.D0.R1.S02: TxDqs: plus1 = 1, minus1 = 0, PI = 20, DB = 0
N0.C2.D0.R0.S10: TxDq : plus1 = 1, minus1 = 0, PI = 02, DB = 1
N2.C3.D1.R0.S01: TxDqs: plus1 = 1, minus1 = 0, PI = 43, DB = 0
N4.C3.D1.R1.S13: RdPtrOffsetTxDqs: 06
N6.C2.D0.R1.S02: TxDq : plus1 = 1, minus1 = 0, PI = 53, DB = 1
N0.C2.D0.R0.S11: TxDqs: plus1 = 1, minus1 = 0, PI = 26, DB = 0
N2.C3.D1.R0.S01: TxDq : plus1 = 1, minus1 = 0, PI = 10, DB = 1
N4.C3.D1.R1.S13: PiTxDqs: 54
N6.C2.D0.R1.S03: TxDqs: plus1 = 1, minus1 = 0, PI = 01, DB = 1
N0.C2.D0.R0.S11: TxDq : plus1 = 1, minus1 = 0, PI = 57, DB = 1
N2.C3.D1.R0.S02: TxDqs: plus1 = 1, minus1 = 0, PI = 30, DB = 0
N4.C3.D1.R1.S14: wrcmd2dqsstartlatency: 04
N6.C2.D0.R1.S03: TxDq : plus1 = 1, minus1 = 0, PI = 33, DB = 0
N0.C2.D0.R0.S12: TxDqs: plus1 = 1, minus1 = 0, PI = 07, DB = 1
N2.C3.D1.R0.S02: TxDq : plus1 = 1, minus1 = 0, PI = 61, DB = 1
N4.C3.D1.R1.S14: RdPtrOffsetTxDq: 05
N6.C2.D0.R1.S04: TxDqs: plus1 = 1, minus1 = 0, PI = 26, DB = 0
N0.C2.D0.R0.S12: TxDq : plus1 = 1, minus1 = 0, PI = 37, DB = 0
N2.C3.D1.R0.S03: TxDqs: plus1 = 1, minus1 = 0, PI = 17, DB = 0
N4.C3.D1.R1.S14: RdPtrOffsetTxDqs: 07
N6.C2.D0.R1.S04: TxDq : plus1 = 1, minus1 = 0, PI = 59, DB = 1
N0.C2.D0.R0.S13: TxDqs: plus1 = 1, minus1 = 0, PI = 32, DB = 0
N2.C3.D1.R0.S03: TxDq : plus1 = 1, minus1 = 0, PI = 48, DB = 0
N4.C3.D1.R1.S14: PiTxDqs: 03
N6.C2.D0.R1.S05: TxDqs: plus1 = 1, minus1 = 0, PI = 56, DB = 1
N0.C2.D0.R0.S13: TxDq : plus1 = 1, minus1 = 0, PI = 63, DB = 1
N2.C3.D1.R0.S04: TxDqs: plus1 = 1, minus1 = 0, PI = 46, DB = 0
N4.C3.D1.R1.S15: wrcmd2dqsstartlatency: 04
N6.C2.D0.R1.S05: TxDq : plus1 = 1, minus1 = 0, PI = 23, DB = 0
N0.C2.D0.R0.S14: TxDqs: plus1 = 1, minus1 = 0, PI = 59, DB = 1
N2.C3.D1.R0.S04: TxDq : plus1 = 1, minus1 = 0, PI = 13, DB = 1
N4.C3.D1.R1.S15: RdPtrOffsetTxDq: 05
N6.C2.D0.R1.S06: TxDqs: plus1 = 1, minus1 = 0, PI = 56, DB = 1
N0.C2.D0.R0.S14: TxDq : plus1 = 1, minus1 = 0, PI = 28, DB = 0
N2.C3.D1.R0.S05: TxDqs: plus1 = 1, minus1 = 0, PI = 60, DB = 1
N4.C3.D1.R1.S15: RdPtrOffsetTxDqs: 07
N6.C2.D0.R1.S06: TxDq : plus1 = 1, minus1 = 0, PI = 25, DB = 0
N0.C2.D0.R0.S15: TxDqs: plus1 = 1, minus1 = 0, PI = 60, DB = 1
N2.C3.D1.R0.S05: TxDq : plus1 = 1, minus1 = 0, PI = 28, DB = 0
N4.C3.D1.R1.S15: PiTxDqs: 17
N6.C2.D0.R1.S07: TxDqs: plus1 = 1, minus1 = 0, PI = 12, DB = 1
N0.C2.D0.R0.S15: TxDq : plus1 = 1, minus1 = 0, PI = 27, DB = 0
N2.C3.D1.R0.S06: TxDqs: plus1 = 1, minus1 = 0, PI = 09, DB = 1
N4.C3.D1.R1.S16: wrcmd2dqsstartlatency: 04
N6.C2.D0.R1.S07: TxDq : plus1 = 1, minus1 = 0, PI = 41, DB = 0
N0.C2.D0.R0.S16: TxDqs: plus1 = 1, minus1 = 0, PI = 17, DB = 0
N2.C3.D1.R0.S06: TxDq : plus1 = 1, minus1 = 0, PI = 40, DB = 0
N4.C3.D1.R1.S16: RdPtrOffsetTxDq: 05
N6.C2.D0.R1.S08: TxDqs: plus1 = 1, minus1 = 0, PI = 45, DB = 0
N0.C2.D0.R0.S16: TxDq : plus1 = 1, minus1 = 0, PI = 45, DB = 0
N2.C3.D1.R0.S07: TxDqs: plus1 = 1, minus1 = 0, PI = 27, DB = 0
N4.C3.D1.R1.S16: RdPtrOffsetTxDqs: 07
N6.C2.D0.R1.S08: TxDq : plus1 = 1, minus1 = 0, PI = 13, DB = 1
N0.C2.D0.R0.S17: TxDqs: plus1 = 1, minus1 = 0, PI = 51, DB = 1
N2.C3.D1.R0.S07: TxDq : plus1 = 1, minus1 = 0, PI = 58, DB = 1
N4.C3.D1.R1.S16: PiTxDqs: 35
N6.C2.D0.R1.S09: TxDqs: plus1 = 1, minus1 = 0, PI = 44, DB = 0
N0.C2.D0.R0.S17: TxDq : plus1 = 1, minus1 = 0, PI = 17, DB = 0
N2.C3.D1.R0.S08: TxDqs: plus1 = 1, minus1 = 0, PI = 61, DB = 1
N4.C3.D1.R1.S17: wrcmd2dqsstartlatency: 04
N6.C2.D0.R1.S09: TxDq : plus1 = 1, minus1 = 0, PI = 11, DB = 1
N0.C2.D0.R1.S00: TxDqs: plus1 = 1, minus1 = 0, PI = 51, DB = 1
N2.C3.D1.R0.S08: TxDq : plus1 = 1, minus1 = 0, PI = 28, DB = 0
N4.C3.D1.R1.S17: RdPtrOffsetTxDq: 05
N6.C2.D0.R1.S10: TxDqs: plus1 = 1, minus1 = 0, PI = 31, DB = 0
N0.C2.D0.R1.S00: TxDq : plus1 = 1, minus1 = 0, PI = 19, DB = 0
N2.C3.D1.R0.S09: TxDqs: plus1 = 1, minus1 = 0, PI = 57, DB = 1
N4.C3.D1.R1.S17: RdPtrOffsetTxDqs: 07
N6.C2.D0.R1.S10: TxDq : plus1 = 0, minus1 = 1, PI = 00, DB = 1
N0.C2.D0.R1.S01: TxDqs: plus1 = 1, minus1 = 0, PI = 36, DB = 0
N2.C3.D1.R0.S09: TxDq : plus1 = 1, minus1 = 0, PI = 23, DB = 0
N4.C3.D1.R1.S17: PiTxDqs: 03
N6.C2.D0.R1.S11: TxDqs: plus1 = 1, minus1 = 0, PI = 21, DB = 0
N0.C2.D0.R1.S01: TxDq : plus1 = 1, minus1 = 0, PI = 03, DB = 1
N2.C3.D1.R0.S10: TxDqs: plus1 = 1, minus1 = 0, PI = 43, DB = 0
N4.C3.D1.R1.S00: RdPtrOffsetTxDq: 07
N6.C2.D0.R1.S11: TxDq : plus1 = 1, minus1 = 0, PI = 55, DB = 1
N0.C2.D0.R1.S02: TxDqs: plus1 = 1, minus1 = 0, PI = 26, DB = 0
N2.C3.D1.R0.S10: TxDq : plus1 = 1, minus1 = 0, PI = 10, DB = 1
N4.C3.D1.R1.S01: RdPtrOffsetTxDq: 07
N6.C2.D0.R1.S12: TxDqs: plus1 = 1, minus1 = 0, PI = 03, DB = 1
N0.C2.D0.R1.S02: TxDq : plus1 = 1, minus1 = 0, PI = 58, DB = 1
N2.C3.D1.R0.S11: TxDqs: plus1 = 1, minus1 = 0, PI = 30, DB = 0
N4.C3.D1.R1.S02: RdPtrOffsetTxDq: 07
N6.C2.D0.R1.S12: TxDq : plus1 = 1, minus1 = 0, PI = 35, DB = 0
N0.C2.D0.R1.S03: TxDqs: plus1 = 1, minus1 = 0, PI = 08, DB = 1
N2.C3.D1.R0.S11: TxDq : plus1 = 1, minus1 = 0, PI = 62, DB = 1
N4.C3.D1.R1.S03: RdPtrOffsetTxDq: 06
N6.C2.D0.R1.S13: TxDqs: plus1 = 1, minus1 = 0, PI = 26, DB = 0
N0.C2.D0.R1.S03: TxDq : plus1 = 1, minus1 = 0, PI = 38, DB = 0
N2.C3.D1.R0.S12: TxDqs: plus1 = 1, minus1 = 0, PI = 17, DB = 0
N4.C3.D1.R1.S04: RdPtrOffsetTxDq: 06
N6.C2.D0.R1.S13: TxDq : plus1 = 1, minus1 = 0, PI = 59, DB = 1
N0.C2.D0.R1.S04: TxDqs: plus1 = 1, minus1 = 0, PI = 34, DB = 0
N2.C3.D1.R0.S12: TxDq : plus1 = 1, minus1 = 0, PI = 47, DB = 0
N4.C3.D1.R1.S05: RdPtrOffsetTxDq: 06
N6.C2.D0.R1.S14: TxDqs: plus1 = 1, minus1 = 0, PI = 55, DB = 1
N0.C2.D0.R1.S04: TxDq : plus1 = 0, minus1 = 1, PI = 02, DB = 1
N2.C3.D1.R0.S13: TxDqs: plus1 = 1, minus1 = 0, PI = 46, DB = 0
N4.C3.D1.R1.S06: RdPtrOffsetTxDq: 06
N6.C2.D0.R1.S14: TxDq : plus1 = 1, minus1 = 0, PI = 23, DB = 0
N0.C2.D0.R1.S05: TxDqs: plus1 = 1, minus1 = 0, PI = 61, DB = 1
N2.C3.D1.R0.S13: TxDq : plus1 = 1, minus1 = 0, PI = 13, DB = 1
N4.C3.D1.R1.S07: RdPtrOffsetTxDq: 06
N6.C2.D0.R1.S15: TxDqs: plus1 = 1, minus1 = 0, PI = 56, DB = 1
N0.C2.D0.R1.S05: TxDq : plus1 = 1, minus1 = 0, PI = 26, DB = 0
N2.C3.D1.R0.S14: TxDqs: plus1 = 1, minus1 = 0, PI = 58, DB = 1
N4.C3.D1.R1.S08: RdPtrOffsetTxDq: 06
N6.C2.D0.R1.S15: TxDq : plus1 = 1, minus1 = 0, PI = 24, DB = 0
N0.C2.D0.R1.S06: TxDqs: plus1 = 1, minus1 = 0, PI = 59, DB = 1
N2.C3.D1.R0.S14: TxDq : plus1 = 1, minus1 = 0, PI = 27, DB = 0
N4.C3.D1.R1.S09: RdPtrOffsetTxDq: 07
N6.C2.D0.R1.S16: TxDqs: plus1 = 1, minus1 = 0, PI = 12, DB = 1
N0.C2.D0.R1.S06: TxDq : plus1 = 1, minus1 = 0, PI = 27, DB = 0
N2.C3.D1.R0.S15: TxDqs: plus1 = 1, minus1 = 0, PI = 08, DB = 1
N4.C3.D1.R1.S10: RdPtrOffsetTxDq: 07
N6.C2.D0.R1.S16: TxDq : plus1 = 1, minus1 = 0, PI = 44, DB = 0
N0.C2.D0.R1.S07: TxDqs: plus1 = 1, minus1 = 0, PI = 16, DB = 0
N2.C3.D1.R0.S15: TxDq : plus1 = 1, minus1 = 0, PI = 40, DB = 0
N4.C3.D1.R1.S11: RdPtrOffsetTxDq: 07
N6.C2.D0.R1.S17: TxDqs: plus1 = 1, minus1 = 0, PI = 45, DB = 0
N0.C2.D0.R1.S07: TxDq : plus1 = 1, minus1 = 0, PI = 46, DB = 0
N2.C3.D1.R0.S16: TxDqs: plus1 = 1, minus1 = 0, PI = 27, DB = 0
N4.C3.D1.R1.S12: RdPtrOffsetTxDq: 06
N6.C2.D0.R1.S17: TxDq : plus1 = 1, minus1 = 0, PI = 11, DB = 1
N0.C2.D0.R1.S08: TxDqs: plus1 = 1, minus1 = 0, PI = 52, DB = 1
N2.C3.D1.R0.S16: TxDq : plus1 = 1, minus1 = 0, PI = 58, DB = 1
N4.C3.D1.R1.S13: RdPtrOffsetTxDq: 06
N6.C2.D1.R0.S00: TxDqs: plus1 = 1, minus1 = 0, PI = 52, DB = 1
N0.C2.D0.R1.S08: TxDq : plus1 = 1, minus1 = 0, PI = 18, DB = 0
N2.C3.D1.R0.S17: TxDqs: plus1 = 1, minus1 = 0, PI = 61, DB = 1
N4.C3.D1.R1.S14: RdPtrOffsetTxDq: 06
N6.C2.D1.R0.S00: TxDq : plus1 = 1, minus1 = 0, PI = 21, DB = 0
N0.C2.D0.R1.S09: TxDqs: plus1 = 1, minus1 = 0, PI = 52, DB = 1
N2.C3.D1.R0.S17: TxDq : plus1 = 1, minus1 = 0, PI = 27, DB = 0
N4.C3.D1.R1.S15: RdPtrOffsetTxDq: 06
N6.C2.D1.R0.S01: TxDqs: plus1 = 1, minus1 = 0, PI = 38, DB = 0
N0.C2.D0.R1.S09: TxDq : plus1 = 1, minus1 = 0, PI = 19, DB = 0
N2.C3.D1.R1.S00: TxDqs: plus1 = 1, minus1 = 0, PI = 58, DB = 1
N4.C3.D1.R1.S16: RdPtrOffsetTxDq: 06
N6.C2.D1.R0.S01: TxDq : plus1 = 0, minus1 = 1, PI = 05, DB = 1
N0.C2.D0.R1.S10: TxDqs: plus1 = 1, minus1 = 0, PI = 38, DB = 0
N2.C3.D1.R1.S00: TxDq : plus1 = 1, minus1 = 0, PI = 26, DB = 0
N4.C3.D1.R1.S17: RdPtrOffsetTxDq: 06
N6.C2.D1.R0.S02: TxDqs: plus1 = 1, minus1 = 0, PI = 29, DB = 0
N0.C2.D0.R1.S10: TxDq : plus1 = 1, minus1 = 0, PI = 02, DB = 1
N2.C3.D1.R1.S01: TxDqs: plus1 = 1, minus1 = 0, PI = 43, DB = 0
N4.C3.D1.R1.S00: RdPtrOffsetTxDq: 08
N6.C2.D1.R0.S02: TxDq : plus1 = 1, minus1 = 0, PI = 61, DB = 1
N0.C2.D0.R1.S11: TxDqs: plus1 = 1, minus1 = 0, PI = 26, DB = 0
N2.C3.D1.R1.S01: TxDq : plus1 = 1, minus1 = 0, PI = 10, DB = 1
N4.C3.D1.R1.S01: RdPtrOffsetTxDq: 08
N6.C2.D1.R0.S03: TxDqs: plus1 = 1, minus1 = 0, PI = 13, DB = 1
N0.C2.D0.R1.S11: TxDq : plus1 = 1, minus1 = 0, PI = 57, DB = 1
N2.C3.D1.R1.S02: TxDqs: plus1 = 1, minus1 = 0, PI = 30, DB = 0
N4.C3.D1.R1.S02: RdPtrOffsetTxDq: 08
N6.C2.D1.R0.S03: TxDq : plus1 = 1, minus1 = 0, PI = 44, DB = 0
N0.C2.D0.R1.S12: TxDqs: plus1 = 1, minus1 = 0, PI = 07, DB = 1
N2.C3.D1.R1.S02: TxDq : plus1 = 1, minus1 = 0, PI = 61, DB = 1
N4.C3.D1.R1.S03: RdPtrOffsetTxDq: 07
N6.C2.D1.R0.S04: TxDqs: plus1 = 1, minus1 = 0, PI = 35, DB = 0
N0.C2.D0.R1.S12: TxDq : plus1 = 1, minus1 = 0, PI = 37, DB = 0
N2.C3.D1.R1.S03: TxDqs: plus1 = 1, minus1 = 0, PI = 17, DB = 0
N4.C3.D1.R1.S04: RdPtrOffsetTxDq: 07
N6.C2.D1.R0.S04: TxDq : plus1 = 0, minus1 = 1, PI = 03, DB = 1
N0.C2.D0.R1.S13: TxDqs: plus1 = 1, minus1 = 0, PI = 32, DB = 0
N2.C3.D1.R1.S03: TxDq : plus1 = 1, minus1 = 0, PI = 48, DB = 0
N4.C3.D1.R1.S05: RdPtrOffsetTxDq: 07
N6.C2.D1.R0.S05: TxDqs: plus1 = 0, minus1 = 1, PI = 02, DB = 1
N0.C2.D0.R1.S13: TxDq : plus1 = 1, minus1 = 0, PI = 63, DB = 1
N2.C3.D1.R1.S04: TxDqs: plus1 = 1, minus1 = 0, PI = 46, DB = 0
N4.C3.D1.R1.S06: RdPtrOffsetTxDq: 07
N6.C2.D1.R0.S05: TxDq : plus1 = 1, minus1 = 0, PI = 33, DB = 0
N0.C2.D0.R1.S14: TxDqs: plus1 = 1, minus1 = 0, PI = 59, DB = 1
N2.C3.D1.R1.S04: TxDq : plus1 = 1, minus1 = 0, PI = 13, DB = 1
N4.C3.D1.R1.S07: RdPtrOffsetTxDq: 07
N6.C2.D1.R0.S06: TxDqs: plus1 = 1, minus1 = 0, PI = 62, DB = 1
N0.C2.D0.R1.S14: TxDq : plus1 = 1, minus1 = 0, PI = 28, DB = 0
N2.C3.D1.R1.S05: TxDqs: plus1 = 1, minus1 = 0, PI = 60, DB = 1
N4.C3.D1.R1.S08: RdPtrOffsetTxDq: 07
N6.C2.D1.R0.S06: TxDq : plus1 = 1, minus1 = 0, PI = 30, DB = 0
N0.C2.D0.R1.S15: TxDqs: plus1 = 1, minus1 = 0, PI = 60, DB = 1
N2.C3.D1.R1.S05: TxDq : plus1 = 1, minus1 = 0, PI = 28, DB = 0
N4.C3.D1.R1.S09: RdPtrOffsetTxDq: 08
N6.C2.D1.R0.S07: TxDqs: plus1 = 1, minus1 = 0, PI = 22, DB = 0
N0.C2.D0.R1.S15: TxDq : plus1 = 1, minus1 = 0, PI = 27, DB = 0
N2.C3.D1.R1.S06: TxDqs: plus1 = 1, minus1 = 0, PI = 09, DB = 1
N4.C3.D1.R1.S10: RdPtrOffsetTxDq: 08
N6.C2.D1.R0.S07: TxDq : plus1 = 1, minus1 = 0, PI = 53, DB = 1
N0.C2.D0.R1.S16: TxDqs: plus1 = 1, minus1 = 0, PI = 17, DB = 0
N2.C3.D1.R1.S06: TxDq : plus1 = 1, minus1 = 0, PI = 40, DB = 0
N4.C3.D1.R1.S11: RdPtrOffsetTxDq: 08
N6.C2.D1.R0.S08: TxDqs: plus1 = 1, minus1 = 0, PI = 50, DB = 1
N0.C2.D0.R1.S16: TxDq : plus1 = 1, minus1 = 0, PI = 45, DB = 0
N2.C3.D1.R1.S07: TxDqs: plus1 = 1, minus1 = 0, PI = 27, DB = 0
N4.C3.D1.R1.S12: RdPtrOffsetTxDq: 07
N6.C2.D1.R0.S08: TxDq : plus1 = 1, minus1 = 0, PI = 16, DB = 0
N0.C2.D0.R1.S17: TxDqs: plus1 = 1, minus1 = 0, PI = 51, DB = 1
N2.C3.D1.R1.S07: TxDq : plus1 = 1, minus1 = 0, PI = 58, DB = 1
N4.C3.D1.R1.S13: RdPtrOffsetTxDq: 07
N6.C2.D1.R0.S09: TxDqs: plus1 = 1, minus1 = 0, PI = 52, DB = 1
N0.C2.D0.R1.S17: TxDq : plus1 = 1, minus1 = 0, PI = 17, DB = 0
N2.C3.D1.R1.S08: TxDqs: plus1 = 1, minus1 = 0, PI = 61, DB = 1
N4.C3.D1.R1.S14: RdPtrOffsetTxDq: 07
N6.C2.D1.R0.S09: TxDq : plus1 = 1, minus1 = 0, PI = 18, DB = 0
N0.C2.D1.R0.S00: TxDqs: plus1 = 1, minus1 = 0, PI = 54, DB = 1
N2.C3.D1.R1.S08: TxDq : plus1 = 1, minus1 = 0, PI = 28, DB = 0
N4.C3.D1.R1.S15: RdPtrOffsetTxDq: 07
N6.C2.D1.R0.S10: TxDqs: plus1 = 1, minus1 = 0, PI = 38, DB = 0
N0.C2.D1.R0.S00: TxDq : plus1 = 1, minus1 = 0, PI = 22, DB = 0
N2.C3.D1.R1.S09: TxDqs: plus1 = 1, minus1 = 0, PI = 57, DB = 1
N4.C3.D1.R1.S16: RdPtrOffsetTxDq: 07
N6.C2.D1.R0.S10: TxDq : plus1 = 0, minus1 = 1, PI = 04, DB = 1
N0.C2.D1.R0.S01: TxDqs: plus1 = 1, minus1 = 0, PI = 41, DB = 0
N2.C3.D1.R1.S09: TxDq : plus1 = 1, minus1 = 0, PI = 23, DB = 0
N4.C3.D1.R1.S17: RdPtrOffsetTxDq: 07
N6.C2.D1.R0.S11: TxDqs: plus1 = 1, minus1 = 0, PI = 30, DB = 0
N0.C2.D1.R0.S01: TxDq : plus1 = 1, minus1 = 0, PI = 06, DB = 1
N2.C3.D1.R1.S10: TxDqs: plus1 = 1, minus1 = 0, PI = 43, DB = 0
N4.C3.D1.R1.S00: Total Delay in PI ticks: TxDQ = 992
N6.C2.D1.R0.S11: TxDq : plus1 = 1, minus1 = 0, PI = 61, DB = 1
N0.C2.D1.R0.S02: TxDqs: plus1 = 1, minus1 = 0, PI = 31, DB = 0
N2.C3.D1.R1.S10: TxDq : plus1 = 1, minus1 = 0, PI = 10, DB = 1
N4.C3.D1.R1.S01: Total Delay in PI ticks: TxDQ = 977
N6.C2.D1.R0.S12: TxDqs: plus1 = 1, minus1 = 0, PI = 15, DB = 1
N0.C2.D1.R0.S02: TxDq : plus1 = 1, minus1 = 0, PI = 62, DB = 1
N2.C3.D1.R1.S11: TxDqs: plus1 = 1, minus1 = 0, PI = 30, DB = 0
N4.C3.D1.R1.S02: Total Delay in PI ticks: TxDQ = 963
N6.C2.D1.R0.S12: TxDq : plus1 = 1, minus1 = 0, PI = 45, DB = 0
N0.C2.D1.R0.S03: TxDqs: plus1 = 1, minus1 = 0, PI = 14, DB = 1
N2.C3.D1.R1.S11: TxDq : plus1 = 1, minus1 = 0, PI = 62, DB = 1
N4.C3.D1.R1.S03: Total Delay in PI ticks: TxDQ = 951
N6.C2.D1.R0.S13: TxDqs: plus1 = 1, minus1 = 0, PI = 36, DB = 0
N0.C2.D1.R0.S03: TxDq : plus1 = 1, minus1 = 0, PI = 43, DB = 0
N2.C3.D1.R1.S12: TxDqs: plus1 = 1, minus1 = 0, PI = 17, DB = 0
N4.C3.D1.R1.S04: Total Delay in PI ticks: TxDQ = 913
N6.C2.D1.R0.S13: TxDq : plus1 = 0, minus1 = 1, PI = 03, DB = 1
N0.C2.D1.R0.S04: TxDqs: plus1 = 1, minus1 = 0, PI = 37, DB = 0
N2.C3.D1.R1.S12: TxDq : plus1 = 1, minus1 = 0, PI = 47, DB = 0
N4.C3.D1.R1.S05: Total Delay in PI ticks: TxDQ = 928
N6.C2.D1.R0.S14: TxDqs: plus1 = 0, minus1 = 1, PI = 01, DB = 1
N0.C2.D1.R0.S04: TxDq : plus1 = 0, minus1 = 1, PI = 05, DB = 1
N2.C3.D1.R1.S13: TxDqs: plus1 = 1, minus1 = 0, PI = 46, DB = 0
N4.C3.D1.R1.S06: Total Delay in PI ticks: TxDQ = 939
N6.C2.D1.R0.S14: TxDq : plus1 = 1, minus1 = 0, PI = 32, DB = 0
N0.C2.D1.R0.S05: TxDqs: plus1 = 0, minus1 = 1, PI = 02, DB = 1
N2.C3.D1.R1.S13: TxDq : plus1 = 1, minus1 = 0, PI = 13, DB = 1
N4.C3.D1.R1.S07: Total Delay in PI ticks: TxDQ = 957
N6.C2.D1.R0.S15: TxDqs: plus1 = 1, minus1 = 0, PI = 63, DB = 1
N0.C2.D1.R0.S05: TxDq : plus1 = 1, minus1 = 0, PI = 31, DB = 0
N2.C3.D1.R1.S14: TxDqs: plus1 = 1, minus1 = 0, PI = 58, DB = 1
N4.C3.D1.R1.S08: Total Delay in PI ticks: TxDQ = 927
N6.C2.D1.R0.S15: TxDq : plus1 = 1, minus1 = 0, PI = 30, DB = 0
N0.C2.D1.R0.S06: TxDqs: plus1 = 1, minus1 = 0, PI = 62, DB = 1
N2.C3.D1.R1.S14: TxDq : plus1 = 1, minus1 = 0, PI = 27, DB = 0
N4.C3.D1.R1.S09: Total Delay in PI ticks: TxDQ = 987
N6.C2.D1.R0.S16: TxDqs: plus1 = 1, minus1 = 0, PI = 21, DB = 0
N0.C2.D1.R0.S06: TxDq : plus1 = 1, minus1 = 0, PI = 29, DB = 0
N2.C3.D1.R1.S15: TxDqs: plus1 = 1, minus1 = 0, PI = 08, DB = 1
N4.C3.D1.R1.S10: Total Delay in PI ticks: TxDQ = 976
N6.C2.D1.R0.S16: TxDq : plus1 = 1, minus1 = 0, PI = 52, DB = 1
N0.C2.D1.R0.S07: TxDqs: plus1 = 1, minus1 = 0, PI = 20, DB = 0
N2.C3.D1.R1.S15: TxDq : plus1 = 1, minus1 = 0, PI = 40, DB = 0
N4.C3.D1.R1.S11: Total Delay in PI ticks: TxDQ = 962
N6.C2.D1.R0.S17: TxDqs: plus1 = 1, minus1 = 0, PI = 51, DB = 1
N0.C2.D1.R0.S07: TxDq : plus1 = 1, minus1 = 0, PI = 49, DB = 1
N2.C3.D1.R1.S16: TxDqs: plus1 = 1, minus1 = 0, PI = 27, DB = 0
N4.C3.D1.R1.S12: Total Delay in PI ticks: TxDQ = 952
N6.C2.D1.R0.S17: TxDq : plus1 = 1, minus1 = 0, PI = 16, DB = 0
N0.C2.D1.R0.S08: TxDqs: plus1 = 1, minus1 = 0, PI = 52, DB = 1
N2.C3.D1.R1.S16: TxDq : plus1 = 1, minus1 = 0, PI = 58, DB = 1
N4.C3.D1.R1.S13: Total Delay in PI ticks: TxDQ = 915
N6.C2.D1.R1.S00: TxDqs: plus1 = 1, minus1 = 0, PI = 52, DB = 1
N0.C2.D1.R0.S08: TxDq : plus1 = 1, minus1 = 0, PI = 18, DB = 0
N2.C3.D1.R1.S17: TxDqs: plus1 = 1, minus1 = 0, PI = 61, DB = 1
N4.C3.D1.R1.S14: Total Delay in PI ticks: TxDQ = 928
N6.C2.D1.R1.S00: TxDq : plus1 = 1, minus1 = 0, PI = 21, DB = 0
N0.C2.D1.R0.S09: TxDqs: plus1 = 1, minus1 = 0, PI = 54, DB = 1
N2.C3.D1.R1.S17: TxDq : plus1 = 1, minus1 = 0, PI = 27, DB = 0
N4.C3.D1.R1.S15: Total Delay in PI ticks: TxDQ = 942
N6.C2.D1.R1.S01: TxDqs: plus1 = 1, minus1 = 0, PI = 38, DB = 0
N0.C2.D1.R0.S09: TxDq : plus1 = 1, minus1 = 0, PI = 19, DB = 0
END_DATA_TX_DQ
N4.C3.D1.R1.S16: Total Delay in PI ticks: TxDQ = 960
N6.C2.D1.R1.S01: TxDq : plus1 = 0, minus1 = 1, PI = 05, DB = 1
N0.C2.D1.R0.S10: TxDqs: plus1 = 1, minus1 = 0, PI = 42, DB = 0
N2: RunTrainStep: Final status = 0
N4.C3.D1.R1.S17: Total Delay in PI ticks: TxDQ = 927
N6.C2.D1.R1.S02: TxDqs: plus1 = 1, minus1 = 0, PI = 29, DB = 0
N0.C2.D1.R0.S10: TxDq : plus1 = 1, minus1 = 0, PI = 06, DB = 1

END - Basic Write DQ/DQS Training      Time         51756 ms
N4.C3: Calculating Optimimum DQ/DQS Values
N6.C2.D1.R1.S02: TxDq : plus1 = 1, minus1 = 0, PI = 61, DB = 1
N0.C2.D1.R0.S11: TxDqs: plus1 = 1, minus1 = 0, PI = 31, DB = 0
N2.C0: JCK cmd timing = 1N
N6.C2.D1.R1.S03: TxDqs: plus1 = 1, minus1 = 0, PI = 13, DB = 1
N0.C2.D1.R0.S11: TxDq : plus1 = 1, minus1 = 0, PI = 61, DB = 1
N2.C0: RdCmd2DataValidLatency = 21, (dlyFrmS = 15, clEff = 10, earlyCas = 0, selNTiming = 0)
START_DATA_TX_DQ
N6.C2.D1.R1.S03: TxDq : plus1 = 1, minus1 = 0, PI = 44, DB = 0
N0.C2.D1.R0.S12: TxDqs: plus1 = 1, minus1 = 0, PI = 13, DB = 1
N2.C1: RdCmd2DataValidLatency = 21, (dlyFrmS = 15, clEff = 10, earlyCas = 0, selNTiming = 0)
N4.C3.S00: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 009, RdPtrOffsetTxDqs = 009
N6.C2.D1.R1.S04: TxDqs: plus1 = 1, minus1 = 0, PI = 35, DB = 0
N0.C2.D1.R0.S12: TxDq : plus1 = 1, minus1 = 0, PI = 42, DB = 0
N2.C2: JCK cmd timing = 1N
N4.C3.S00: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 009, RdPtrOffsetTxDqs = 009
N6.C2.D1.R1.S04: TxDq : plus1 = 0, minus1 = 1, PI = 03, DB = 1
N0.C2.D1.R0.S13: TxDqs: plus1 = 1, minus1 = 0, PI = 39, DB = 0
N2.C2: RdCmd2DataValidLatency = 21, (dlyFrmS = 15, clEff = 10, earlyCas = 0, selNTiming = 0)
N4.C3.S01: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 009, RdPtrOffsetTxDqs = 009
N6.C2.D1.R1.S05: TxDqs: plus1 = 0, minus1 = 1, PI = 02, DB = 1
N0.C2.D1.R0.S13: TxDq : plus1 = 0, minus1 = 1, PI = 06, DB = 1
N2.C3: RdCmd2DataValidLatency = 21, (dlyFrmS = 15, clEff = 10, earlyCas = 0, selNTiming = 0)
N4.C3.S01: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 009, RdPtrOffsetTxDqs = 009
N6.C2.D1.R1.S05: TxDq : plus1 = 1, minus1 = 0, PI = 33, DB = 0
N0.C2.D1.R0.S14: TxDqs: plus1 = 0, minus1 = 1, PI = 00, DB = 1
N2: JckSetOdtDynTiming[2] BL8:
N4.C3.S02: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 009
N6.C2.D1.R1.S06: TxDqs: plus1 = 1, minus1 = 0, PI = 62, DB = 1
N0.C2.D1.R0.S14: TxDq : plus1 = 1, minus1 = 0, PI = 32, DB = 0
N4.C3.S02: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 009
N6.C2.D1.R1.S06: TxDq : plus1 = 1, minus1 = 0, PI = 30, DB = 0
N0.C2.D1.R0.S15: TxDqs: plus1 = 0, minus1 = 1, PI = 01, DB = 1
N2.C0: minRcvEnDelay = 208 maxRcvEnDelay = 304 ==> rdwidth = 6 rddly = 2 wrwidth = 6 wrdly = 0
N4.C3.S03: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 009
N6.C2.D1.R1.S07: TxDqs: plus1 = 1, minus1 = 0, PI = 22, DB = 0
N0.C2.D1.R0.S15: TxDq : plus1 = 1, minus1 = 0, PI = 30, DB = 0
N2.C1: minRcvEnDelay = 202 maxRcvEnDelay = 334 ==> rdwidth = 6 rddly = 2 wrwidth = 6 wrdly = 0
N4.C3.S03: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 009
N6.C2.D1.R1.S07: TxDq : plus1 = 1, minus1 = 0, PI = 53, DB = 1
N0.C2.D1.R0.S16: TxDqs: plus1 = 1, minus1 = 0, PI = 22, DB = 0
N2.C2: minRcvEnDelay = 203 maxRcvEnDelay = 306 ==> rdwidth = 6 rddly = 2 wrwidth = 6 wrdly = 0
N4.C3.S04: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 008
N6.C2.D1.R1.S08: TxDqs: plus1 = 1, minus1 = 0, PI = 50, DB = 1
N0.C2.D1.R0.S16: TxDq : plus1 = 1, minus1 = 0, PI = 49, DB = 1
N2.C3: minRcvEnDelay = 202 maxRcvEnDelay = 328 ==> rdwidth = 6 rddly = 2 wrwidth = 6 wrdly = 0
N4.C3.S04: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 008
N6.C2.D1.R1.S08: TxDq : plus1 = 1, minus1 = 0, PI = 16, DB = 0
N0.C2.D1.R0.S17: TxDqs: plus1 = 1, minus1 = 0, PI = 53, DB = 1
N2.C0: Memory Electrical TurnAround timings:
N4.C3.S05: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 008
N6.C2.D1.R1.S09: TxDqs: plus1 = 1, minus1 = 0, PI = 52, DB = 1
N0.C2.D1.R0.S17: TxDq : plus1 = 1, minus1 = 0, PI = 18, DB = 0
N2.C0:      tCCD  =  0, tWWDR =  3, tRRDD =  2, tWWDD =  3, tWRDR =  1, tWRDR_UPPER =  0, tRRDR =  0
N4.C3.S05: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 008
N6.C2.D1.R1.S09: TxDq : plus1 = 1, minus1 = 0, PI = 18, DB = 0
N0.C2.D1.R1.S00: TxDqs: plus1 = 1, minus1 = 0, PI = 54, DB = 1
N2.C0:      tRWDD =  2, tRWDR =  2, tWRDD =  1, tRWSR =  2
N4.C3.S06: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 009
N6.C2.D1.R1.S10: TxDqs: plus1 = 1, minus1 = 0, PI = 38, DB = 0
N0.C2.D1.R1.S00: TxDq : plus1 = 1, minus1 = 0, PI = 22, DB = 0
N2.C0: TCOTHP: T_RWSR = 0x2, T_RWDD = 0x2
N4.C3.S06: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 009
N6.C2.D1.R1.S10: TxDq : plus1 = 0, minus1 = 1, PI = 04, DB = 1
N0.C2.D1.R1.S01: TxDqs: plus1 = 1, minus1 = 0, PI = 41, DB = 0
N2.C0:      tCCD_WR =  0, tWRDS =  2, tRWDS =  2, tWWDS =  3, tRRDS =  1
N4.C3.S07: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 009
N6.C2.D1.R1.S11: TxDqs: plus1 = 1, minus1 = 0, PI = 30, DB = 0
N0.C2.D1.R1.S01: TxDq : plus1 = 1, minus1 = 0, PI = 06, DB = 1
N2.C1: Memory Electrical TurnAround timings:
N4.C3.S07: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 009
N6.C2.D1.R1.S11: TxDq : plus1 = 1, minus1 = 0, PI = 61, DB = 1
N0.C2.D1.R1.S02: TxDqs: plus1 = 1, minus1 = 0, PI = 31, DB = 0
N2.C1:      tCCD  =  0, tWWDR =  3, tRRDD =  2, tWWDD =  3, tWRDR =  1, tWRDR_UPPER =  0, tRRDR =  0
N4.C3.S08: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 008
N6.C2.D1.R1.S12: TxDqs: plus1 = 1, minus1 = 0, PI = 15, DB = 1
N0.C2.D1.R1.S02: TxDq : plus1 = 1, minus1 = 0, PI = 62, DB = 1
N2.C1:      tRWDD =  2, tRWDR =  2, tWRDD =  1, tRWSR =  2
N4.C3.S08: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 008
N6.C2.D1.R1.S12: TxDq : plus1 = 1, minus1 = 0, PI = 45, DB = 0
N0.C2.D1.R1.S03: TxDqs: plus1 = 1, minus1 = 0, PI = 14, DB = 1
N2.C1: TCOTHP: T_RWSR = 0x2, T_RWDD = 0x2
N4.C3.D0.R0.S00: TxDqs: plus1 = 1, minus1 = 0, PI = 61, DB = 1
N6.C2.D1.R1.S13: TxDqs: plus1 = 1, minus1 = 0, PI = 36, DB = 0
N0.C2.D1.R1.S03: TxDq : plus1 = 1, minus1 = 0, PI = 43, DB = 0
N2.C1:      tCCD_WR =  0, tWRDS =  2, tRWDS =  2, tWWDS =  3, tRRDS =  1
N4.C3.D0.R0.S00: TxDq : plus1 = 1, minus1 = 0, PI = 27, DB = 0
N6.C2.D1.R1.S13: TxDq : plus1 = 0, minus1 = 1, PI = 03, DB = 1
N0.C2.D1.R1.S04: TxDqs: plus1 = 1, minus1 = 0, PI = 37, DB = 0
N2.C2: Memory Electrical TurnAround timings:
N4.C3.D0.R0.S01: TxDqs: plus1 = 1, minus1 = 0, PI = 45, DB = 0
N6.C2.D1.R1.S14: TxDqs: plus1 = 0, minus1 = 1, PI = 01, DB = 1
N0.C2.D1.R1.S04: TxDq : plus1 = 0, minus1 = 1, PI = 05, DB = 1
N2.C2:      tCCD  =  0, tWWDR =  3, tRRDD =  2, tWWDD =  3, tWRDR =  1, tWRDR_UPPER =  0, tRRDR =  0
N4.C3.D0.R0.S01: TxDq : plus1 = 1, minus1 = 0, PI = 11, DB = 1
N6.C2.D1.R1.S14: TxDq : plus1 = 1, minus1 = 0, PI = 32, DB = 0
N0.C2.D1.R1.S05: TxDqs: plus1 = 0, minus1 = 1, PI = 02, DB = 1
N2.C2:      tRWDD =  2, tRWDR =  2, tWRDD =  1, tRWSR =  2
N4.C3.D0.R0.S02: TxDqs: plus1 = 1, minus1 = 0, PI = 33, DB = 0
N6.C2.D1.R1.S15: TxDqs: plus1 = 1, minus1 = 0, PI = 63, DB = 1
N0.C2.D1.R1.S05: TxDq : plus1 = 1, minus1 = 0, PI = 31, DB = 0
N2.C2: TCOTHP: T_RWSR = 0x2, T_RWDD = 0x2
N4.C3.D0.R0.S02: TxDq : plus1 = 1, minus1 = 0, PI = 63, DB = 1
N6.C2.D1.R1.S15: TxDq : plus1 = 1, minus1 = 0, PI = 30, DB = 0
N0.C2.D1.R1.S06: TxDqs: plus1 = 1, minus1 = 0, PI = 62, DB = 1
N2.C2:      tCCD_WR =  0, tWRDS =  2, tRWDS =  2, tWWDS =  3, tRRDS =  1
N4.C3.D0.R0.S03: TxDqs: plus1 = 1, minus1 = 0, PI = 19, DB = 0
N6.C2.D1.R1.S16: TxDqs: plus1 = 1, minus1 = 0, PI = 21, DB = 0
N0.C2.D1.R1.S06: TxDq : plus1 = 1, minus1 = 0, PI = 29, DB = 0
N2.C3: Memory Electrical TurnAround timings:
N4.C3.D0.R0.S03: TxDq : plus1 = 1, minus1 = 0, PI = 49, DB = 1
N6.C2.D1.R1.S16: TxDq : plus1 = 1, minus1 = 0, PI = 52, DB = 1
N0.C2.D1.R1.S07: TxDqs: plus1 = 1, minus1 = 0, PI = 20, DB = 0
N2.C3:      tCCD  =  0, tWWDR =  3, tRRDD =  2, tWWDD =  3, tWRDR =  1, tWRDR_UPPER =  0, tRRDR =  0
N4.C3.D0.R0.S04: TxDqs: plus1 = 1, minus1 = 0, PI = 46, DB = 0
N6.C2.D1.R1.S17: TxDqs: plus1 = 1, minus1 = 0, PI = 51, DB = 1
N0.C2.D1.R1.S07: TxDq : plus1 = 1, minus1 = 0, PI = 49, DB = 1
N2.C3:      tRWDD =  2, tRWDR =  2, tWRDD =  1, tRWSR =  2
N4.C3.D0.R0.S04: TxDq : plus1 = 1, minus1 = 0, PI = 12, DB = 1
N6.C2.D1.R1.S17: TxDq : plus1 = 1, minus1 = 0, PI = 16, DB = 0
N0.C2.D1.R1.S08: TxDqs: plus1 = 1, minus1 = 0, PI = 52, DB = 1
N2.C3: TCOTHP: T_RWSR = 0x2, T_RWDD = 0x2
N4.C3.D0.R0.S05: TxDqs: plus1 = 1, minus1 = 0, PI = 60, DB = 1
END_DATA_TX_DQ
N0.C2.D1.R1.S08: TxDq : plus1 = 1, minus1 = 0, PI = 18, DB = 0
N2.C3:      tCCD_WR =  0, tWRDS =  2, tRWDS =  2, tWWDS =  3, tRRDS =  1
N4.C3.D0.R0.S05: TxDq : plus1 = 1, minus1 = 0, PI = 28, DB = 0
N6.C3.D0.R0.S00: wrcmd2dqsstartlatency: 04
N0.C2.D1.R1.S09: TxDqs: plus1 = 1, minus1 = 0, PI = 54, DB = 1

START - Rd Timing Centering 2D Training
N4.C3.D0.R0.S06: TxDqs: plus1 = 1, minus1 = 0, PI = 12, DB = 1
N6.C3.D0.R0.S00: RdPtrOffsetTxDq: 06
N0.C2.D1.R1.S09: TxDq : plus1 = 1, minus1 = 0, PI = 19, DB = 0
N2: 

Adv Strobe Centering(MARGIN_RX_DQ): GetMultiVref: patternLength = 13, stepSize = 1, numPoints = 1
N4.C3.D0.R0.S06: TxDq : plus1 = 1, minus1 = 0, PI = 41, DB = 0
N6.C3.D0.R0.S00: RdPtrOffsetTxDqs: 07
N0.C2.D1.R1.S10: TxDqs: plus1 = 1, minus1 = 0, PI = 42, DB = 0
N2: GetMargins: Level = 1, group = 11, mode = 0, scope = 4
N4.C3.D0.R0.S07: TxDqs: plus1 = 1, minus1 = 0, PI = 27, DB = 0
N6.C3.D0.R0.S00: PiTxDqs: 58
N0.C2.D1.R1.S10: TxDq : plus1 = 1, minus1 = 0, PI = 06, DB = 1
N4.C3.D0.R0.S07: TxDq : plus1 = 1, minus1 = 0, PI = 56, DB = 1
N6.C3.D0.R0.S01: wrcmd2dqsstartlatency: 04
N0.C2.D1.R1.S11: TxDqs: plus1 = 1, minus1 = 0, PI = 31, DB = 0
N4.C3.D0.R0.S08: TxDqs: plus1 = 0, minus1 = 1, PI = 00, DB = 1
N6.C3.D0.R0.S01: RdPtrOffsetTxDq: 06
N0.C2.D1.R1.S11: TxDq : plus1 = 1, minus1 = 0, PI = 61, DB = 1
N4.C3.D0.R0.S08: TxDq : plus1 = 1, minus1 = 0, PI = 31, DB = 0
N6.C3.D0.R0.S01: RdPtrOffsetTxDqs: 07
N0.C2.D1.R1.S12: TxDqs: plus1 = 1, minus1 = 0, PI = 13, DB = 1
N4.C3.D0.R0.S09: TxDqs: plus1 = 1, minus1 = 0, PI = 61, DB = 1
N6.C3.D0.R0.S01: PiTxDqs: 43
N0.C2.D1.R1.S12: TxDq : plus1 = 1, minus1 = 0, PI = 42, DB = 0
N4.C3.D0.R0.S09: TxDq : plus1 = 1, minus1 = 0, PI = 26, DB = 0
N6.C3.D0.R0.S02: wrcmd2dqsstartlatency: 04
N0.C2.D1.R1.S13: TxDqs: plus1 = 1, minus1 = 0, PI = 39, DB = 0
N4.C3.D0.R0.S10: TxDqs: plus1 = 1, minus1 = 0, PI = 44, DB = 0
N6.C3.D0.R0.S02: RdPtrOffsetTxDq: 06
N0.C2.D1.R1.S13: TxDq : plus1 = 0, minus1 = 1, PI = 06, DB = 1
N4.C3.D0.R0.S10: TxDq : plus1 = 1, minus1 = 0, PI = 11, DB = 1
N6.C3.D0.R0.S02: RdPtrOffsetTxDqs: 07
N0.C2.D1.R1.S14: TxDqs: plus1 = 0, minus1 = 1, PI = 00, DB = 1
N4.C3.D0.R0.S11: TxDqs: plus1 = 1, minus1 = 0, PI = 32, DB = 0
N6.C3.D0.R0.S02: PiTxDqs: 36
N0.C2.D1.R1.S14: TxDq : plus1 = 1, minus1 = 0, PI = 32, DB = 0
N4.C3.D0.R0.S11: TxDq : plus1 = 1, minus1 = 0, PI = 63, DB = 1
N6.C3.D0.R0.S03: wrcmd2dqsstartlatency: 04
N0.C2.D1.R1.S15: TxDqs: plus1 = 0, minus1 = 1, PI = 01, DB = 1
N4.C3.D0.R0.S12: TxDqs: plus1 = 1, minus1 = 0, PI = 21, DB = 0
N6.C3.D0.R0.S03: RdPtrOffsetTxDq: 05
N0.C2.D1.R1.S15: TxDq : plus1 = 1, minus1 = 0, PI = 30, DB = 0
N4.C3.D0.R0.S12: TxDq : plus1 = 1, minus1 = 0, PI = 51, DB = 1
N6.C3.D0.R0.S03: RdPtrOffsetTxDqs: 07
N0.C2.D1.R1.S16: TxDqs: plus1 = 1, minus1 = 0, PI = 22, DB = 0
N4.C3.D0.R0.S13: TxDqs: plus1 = 1, minus1 = 0, PI = 47, DB = 0
N6.C3.D0.R0.S03: PiTxDqs: 19
N0.C2.D1.R1.S16: TxDq : plus1 = 1, minus1 = 0, PI = 49, DB = 1
N4.C3.D0.R0.S13: TxDq : plus1 = 1, minus1 = 0, PI = 14, DB = 1
N6.C3.D0.R0.S04: wrcmd2dqsstartlatency: 04
N0.C2.D1.R1.S17: TxDqs: plus1 = 1, minus1 = 0, PI = 53, DB = 1
N4.C3.D0.R0.S14: TxDqs: plus1 = 1, minus1 = 0, PI = 61, DB = 1
N6.C3.D0.R0.S04: RdPtrOffsetTxDq: 05
N0.C2.D1.R1.S17: TxDq : plus1 = 1, minus1 = 0, PI = 18, DB = 0
N4.C3.D0.R0.S14: TxDq : plus1 = 1, minus1 = 0, PI = 27, DB = 0
N6.C3.D0.R0.S04: RdPtrOffsetTxDqs: 06
END_DATA_TX_DQ
N4.C3.D0.R0.S15: TxDqs: plus1 = 1, minus1 = 0, PI = 13, DB = 1
N6.C3.D0.R0.S04: PiTxDqs: 46
N0.C3.D0.R0.S00: wrcmd2dqsstartlatency: 04
N4.C3.D0.R0.S15: TxDq : plus1 = 1, minus1 = 0, PI = 44, DB = 0
N6.C3.D0.R0.S05: wrcmd2dqsstartlatency: 04
N0.C3.D0.R0.S00: RdPtrOffsetTxDq: 06
N4.C3.D0.R0.S16: TxDqs: plus1 = 1, minus1 = 0, PI = 27, DB = 0
N6.C3.D0.R0.S05: RdPtrOffsetTxDq: 05
N0.C3.D0.R0.S00: RdPtrOffsetTxDqs: 08
N4.C3.D0.R0.S16: TxDq : plus1 = 1, minus1 = 0, PI = 57, DB = 1
N6.C3.D0.R0.S05: RdPtrOffsetTxDqs: 06
N0.C3.D0.R0.S00: PiTxDqs: 04
N4.C3.D0.R0.S17: TxDqs: plus1 = 1, minus1 = 0, PI = 62, DB = 1
N6.C3.D0.R0.S05: PiTxDqs: 59
N0.C3.D0.R0.S01: wrcmd2dqsstartlatency: 04
N4.C3.D0.R0.S17: TxDq : plus1 = 1, minus1 = 0, PI = 29, DB = 0
N6.C3.D0.R0.S06: wrcmd2dqsstartlatency: 04
N0.C3.D0.R0.S01: RdPtrOffsetTxDq: 06
N4.C3.D0.R1.S00: TxDqs: plus1 = 1, minus1 = 0, PI = 61, DB = 1
N6.C3.D0.R0.S06: RdPtrOffsetTxDq: 05
N0.C3.D0.R0.S01: RdPtrOffsetTxDqs: 07
N4.C3.D0.R1.S00: TxDq : plus1 = 1, minus1 = 0, PI = 27, DB = 0
N6.C3.D0.R0.S06: RdPtrOffsetTxDqs: 07
N0.C3.D0.R0.S01: PiTxDqs: 50
N4.C3.D0.R1.S01: TxDqs: plus1 = 1, minus1 = 0, PI = 45, DB = 0
N6.C3.D0.R0.S06: PiTxDqs: 12
N0.C3.D0.R0.S02: wrcmd2dqsstartlatency: 04
N4.C3.D0.R1.S01: TxDq : plus1 = 1, minus1 = 0, PI = 11, DB = 1
N6.C3.D0.R0.S07: wrcmd2dqsstartlatency: 04
N0.C3.D0.R0.S02: RdPtrOffsetTxDq: 06
N4.C3.D0.R1.S02: TxDqs: plus1 = 1, minus1 = 0, PI = 33, DB = 0
N6.C3.D0.R0.S07: RdPtrOffsetTxDq: 05
N0.C3.D0.R0.S02: RdPtrOffsetTxDqs: 07
N4.C3.D0.R1.S02: TxDq : plus1 = 1, minus1 = 0, PI = 63, DB = 1
N6.C3.D0.R0.S07: RdPtrOffsetTxDqs: 07
N0.C3.D0.R0.S02: PiTxDqs: 39
N4.C3.D0.R1.S03: TxDqs: plus1 = 1, minus1 = 0, PI = 19, DB = 0
N6.C3.D0.R0.S07: PiTxDqs: 27
N0.C3.D0.R0.S03: wrcmd2dqsstartlatency: 04
N4.C3.D0.R1.S03: TxDq : plus1 = 1, minus1 = 0, PI = 49, DB = 1
N6.C3.D0.R0.S08: wrcmd2dqsstartlatency: 04
N0.C3.D0.R0.S03: RdPtrOffsetTxDq: 05
N4.C3.D0.R1.S04: TxDqs: plus1 = 1, minus1 = 0, PI = 46, DB = 0
N6.C3.D0.R0.S08: RdPtrOffsetTxDq: 05
N0.C3.D0.R0.S03: RdPtrOffsetTxDqs: 07
N4.C3.D0.R1.S04: TxDq : plus1 = 1, minus1 = 0, PI = 12, DB = 1
N6.C3.D0.R0.S08: RdPtrOffsetTxDqs: 07
N0.C3.D0.R0.S03: PiTxDqs: 20
N4.C3.D0.R1.S05: TxDqs: plus1 = 1, minus1 = 0, PI = 60, DB = 1
N6.C3.D0.R0.S08: PiTxDqs: 01
N0.C3.D0.R0.S04: wrcmd2dqsstartlatency: 04
N4.C3.D0.R1.S05: TxDq : plus1 = 1, minus1 = 0, PI = 28, DB = 0
N6.C3.D0.R0.S09: wrcmd2dqsstartlatency: 04
N0.C3.D0.R0.S04: RdPtrOffsetTxDq: 05
N4.C3.D0.R1.S06: TxDqs: plus1 = 1, minus1 = 0, PI = 12, DB = 1
N6.C3.D0.R0.S09: RdPtrOffsetTxDq: 06
N0.C3.D0.R0.S04: RdPtrOffsetTxDqs: 06
N4.C3.D0.R1.S06: TxDq : plus1 = 1, minus1 = 0, PI = 41, DB = 0
N6.C3.D0.R0.S09: RdPtrOffsetTxDqs: 07
N0.C3.D0.R0.S04: PiTxDqs: 52
N4.C3.D0.R1.S07: TxDqs: plus1 = 1, minus1 = 0, PI = 27, DB = 0
N6.C3.D0.R0.S09: PiTxDqs: 59
N0.C3.D0.R0.S05: wrcmd2dqsstartlatency: 04
N4.C3.D0.R1.S07: TxDq : plus1 = 1, minus1 = 0, PI = 56, DB = 1
N6.C3.D0.R0.S10: wrcmd2dqsstartlatency: 04
N0.C3.D0.R0.S05: RdPtrOffsetTxDq: 05
N4.C3.D0.R1.S08: TxDqs: plus1 = 0, minus1 = 1, PI = 00, DB = 1
N6.C3.D0.R0.S10: RdPtrOffsetTxDq: 06
N0.C3.D0.R0.S05: RdPtrOffsetTxDqs: 07
N4.C3.D0.R1.S08: TxDq : plus1 = 1, minus1 = 0, PI = 31, DB = 0
N6.C3.D0.R0.S10: RdPtrOffsetTxDqs: 07
N0.C3.D0.R0.S05: PiTxDqs: 02
N4.C3.D0.R1.S09: TxDqs: plus1 = 1, minus1 = 0, PI = 61, DB = 1
N6.C3.D0.R0.S10: PiTxDqs: 43
N0.C3.D0.R0.S06: wrcmd2dqsstartlatency: 04
N4.C3.D0.R1.S09: TxDq : plus1 = 1, minus1 = 0, PI = 26, DB = 0
N6.C3.D0.R0.S11: wrcmd2dqsstartlatency: 04
N0.C3.D0.R0.S06: RdPtrOffsetTxDq: 05
N4.C3.D0.R1.S10: TxDqs: plus1 = 1, minus1 = 0, PI = 44, DB = 0
N6.C3.D0.R0.S11: RdPtrOffsetTxDq: 06
N0.C3.D0.R0.S06: RdPtrOffsetTxDqs: 07
N4.C3.D0.R1.S10: TxDq : plus1 = 1, minus1 = 0, PI = 11, DB = 1
N6.C3.D0.R0.S11: RdPtrOffsetTxDqs: 07
N0.C3.D0.R0.S06: PiTxDqs: 17
N4.C3.D0.R1.S11: TxDqs: plus1 = 1, minus1 = 0, PI = 32, DB = 0
N6.C3.D0.R0.S11: PiTxDqs: 34
N0.C3.D0.R0.S07: wrcmd2dqsstartlatency: 04
N4.C3.D0.R1.S11: TxDq : plus1 = 1, minus1 = 0, PI = 63, DB = 1
N6.C3.D0.R0.S12: wrcmd2dqsstartlatency: 04
N0.C3.D0.R0.S07: RdPtrOffsetTxDq: 06
N4.C3.D0.R1.S12: TxDqs: plus1 = 1, minus1 = 0, PI = 21, DB = 0
N6.C3.D0.R0.S12: RdPtrOffsetTxDq: 05
N0.C3.D0.R0.S07: RdPtrOffsetTxDqs: 07
N4.C3.D0.R1.S12: TxDq : plus1 = 1, minus1 = 0, PI = 51, DB = 1
N6.C3.D0.R0.S12: RdPtrOffsetTxDqs: 07
N0.C3.D0.R0.S07: PiTxDqs: 33
N4.C3.D0.R1.S13: TxDqs: plus1 = 1, minus1 = 0, PI = 47, DB = 0
N6.C3.D0.R0.S12: PiTxDqs: 17
N0.C3.D0.R0.S08: wrcmd2dqsstartlatency: 04
N4.C3.D0.R1.S13: TxDq : plus1 = 1, minus1 = 0, PI = 14, DB = 1
N6.C3.D0.R0.S13: wrcmd2dqsstartlatency: 04
N0.C3.D0.R0.S08: RdPtrOffsetTxDq: 05
N4.C3.D0.R1.S14: TxDqs: plus1 = 1, minus1 = 0, PI = 61, DB = 1
N6.C3.D0.R0.S13: RdPtrOffsetTxDq: 05
N0.C3.D0.R0.S08: RdPtrOffsetTxDqs: 07
N4.C3.D0.R1.S14: TxDq : plus1 = 1, minus1 = 0, PI = 27, DB = 0
N6.C3.D0.R0.S13: RdPtrOffsetTxDqs: 06
N0.C3.D0.R0.S08: PiTxDqs: 05
N4.C3.D0.R1.S15: TxDqs: plus1 = 1, minus1 = 0, PI = 13, DB = 1
N6.C3.D0.R0.S13: PiTxDqs: 46
N0.C3.D0.R0.S09: wrcmd2dqsstartlatency: 04
N4.C3.D0.R1.S15: TxDq : plus1 = 1, minus1 = 0, PI = 44, DB = 0
N6.C3.D0.R0.S14: wrcmd2dqsstartlatency: 04
N0.C3.D0.R0.S09: RdPtrOffsetTxDq: 06
N4.C3.D0.R1.S16: TxDqs: plus1 = 1, minus1 = 0, PI = 27, DB = 0
N6.C3.D0.R0.S14: RdPtrOffsetTxDq: 05
N0.C3.D0.R0.S09: RdPtrOffsetTxDqs: 08
N4.C3.D0.R1.S16: TxDq : plus1 = 1, minus1 = 0, PI = 57, DB = 1
N6.C3.D0.R0.S14: RdPtrOffsetTxDqs: 06
N0.C3.D0.R0.S09: PiTxDqs: 04
N4.C3.D0.R1.S17: TxDqs: plus1 = 1, minus1 = 0, PI = 62, DB = 1
N6.C3.D0.R0.S14: PiTxDqs: 60
N0.C3.D0.R0.S10: wrcmd2dqsstartlatency: 04
N4.C3.D0.R1.S17: TxDq : plus1 = 1, minus1 = 0, PI = 29, DB = 0
N6.C3.D0.R0.S15: wrcmd2dqsstartlatency: 04
N0.C3.D0.R0.S10: RdPtrOffsetTxDq: 06
N4.C3.D1.R0.S00: TxDqs: plus1 = 0, minus1 = 1, PI = 03, DB = 1
N6.C3.D0.R0.S15: RdPtrOffsetTxDq: 05
N0.C3.D0.R0.S10: RdPtrOffsetTxDqs: 07
START_DATA_RX_DQS_ADV
Results for N2.C0.D0.R0: 
           0   1   2   3   4   5   6   7   8   9  10  11  12  13  14  15  16  17
-------------------------------------------------------------------------------
Vref offset: 0
Left:    -24 -24 -24 -26 -26 -25 -18 -24 -26 -23 -23 -22 -26 -25 -25 -22 -25 -24
Right:    18  21  25  22  23  26  31  23  22  23  20  22  22  23  23  27  23  20
-------------------------------------------------------------------------------
Prev Pi:  33  33  33  34  35  33  34  34  36  32  33  33  34  33  32  33  34  34
New Pi:   30  32  33  32  34  33  40  34  34  32  32  33  32  32  31  35  33  32
Diff:     -3  -1   0  -2  -1   0   6   0  -2   0  -1   0  -2  -1  -1   2  -1  -2

Results for N2.C0.D0.R1: 
           0   1   2   3   4   5   6   7   8   9  10  11  12  13  14  15  16  17
-------------------------------------------------------------------------------
Vref offset: 0
Left:    -24 -25 -24 -26 -26 -25 -17 -24 -25 -23 -22 -23 -26 -24 -24 -22 -25 -25
Right:    18  23  25  24  24  26  31  24  19  22  19  24  22  25  24  25  23  21
-------------------------------------------------------------------------------
Prev Pi:  33  33  33  34  35  33  34  34  36  32  33  33  34  33  32  33  34  34
New Pi:   30  32  33  33  34  33  41  34  33  32  32  33  32  33  32  34  33  32
Diff:     -3  -1   0  -1  -1   0   7   0  -3   0  -1   0  -2   0   0   1  -1  -2

Results for N2.C0.D1.R0: 
           0   1   2   3   4   5   6   7   8   9  10  11  12  13  14  15  16  17
-------------------------------------------------------------------------------
Vref offset: 0
Left:    -24 -26 -23 -27 -25 -26 -17 -23 -23 -24 -23 -20 -25 -25 -25 -21 -24 -25
Right:    17  19  23  22  23  24  30  23  21  18  16  23  22  22  21  25  24  17
-------------------------------------------------------------------------------
Prev Pi:  35  36  35  36  36  35  36  36  37  35  35  35  35  35  34  35  35  36
New Pi:   32  33  35  34  35  34  42  36  36  32  32  36  34  34  32  37  35  32
Diff:     -3  -3   0  -2  -1  -1   6   0  -1  -3  -3   1  -1  -1  -2   2   0  -4

Results for N2.C0.D1.R1: 
           0   1   2   3   4   5   6   7   8   9  10  11  12  13  14  15  16  17
-------------------------------------------------------------------------------
Vref offset: 0
Left:    -24 -26 -24 -27 -26 -26 -17 -23 -22 -24 -22 -20 -25 -25 -25 -21 -24 -26
Right:    17  19  23  22  22  25  29  21  20  19  18  22  23  22  21  26  21  18
-------------------------------------------------------------------------------
Prev Pi:  35  36  35  36  36  35  36  36  37  35  35  35  35  35  34  35  35  36
New Pi:   32  33  35  34  34  35  42  35  36  33  33  36  34  34  32  37  34  32
Diff:     -3  -3   0  -2  -2   0   6  -1  -1  -2  -2   1  -1  -1  -2   2  -1  -4

Results for N2.C1.D0.R0: 
           0   1   2   3   4   5   6   7   8   9  10  11  12  13  14  15  16  17
-------------------------------------------------------------------------------
Vref offset: 0
Left:    -24 -26 -25 -25 -26 -22 -24 -26 -26 -24 -22 -26 -24 -22 -23 -23 -25 -19
Right:    23  24  25  24  26  27  24  27  22  21  24  23  22  21  24  22  23  23
-------------------------------------------------------------------------------
Prev Pi:  32  34  32  34  34  33  33  34  30  32  31  32  31  31  34  34  33  28
New Pi:   32  33  32  34  34  35  33  34  28  31  32  31  30  31  34  34  32  30
Diff:      0  -1   0   0   0   2   0   0  -2  -1   1  -1  -1   0   0   0  -1   2

Results for N2.C1.D0.R1: 
           0   1   2   3   4   5   6   7   8   9  10  11  12  13  14  15  16  17
-------------------------------------------------------------------------------
Vref offset: 0
Left:    -24 -27 -25 -25 -26 -23 -24 -26 -26 -24 -22 -27 -24 -21 -23 -22 -25 -20
Right:    22  24  26  24  25  25  21  24  22  22  23  22  22  26  20  19  24  22
-------------------------------------------------------------------------------
Prev Pi:  32  34  32  34  34  33  33  34  30  32  31  32  31  31  34  34  33  28
New Pi:   31  33  32  34  34  34  32  33  28  31  31  30  30  33  33  33  33  29
Diff:     -1  -1   0   0   0   1  -1  -1  -2  -1   0  -2  -1   2  -1  -1   0   1

Results for N2.C1.D1.R0: 
           0   1   2   3   4   5   6   7   8   9  10  11  12  13  14  15  16  17
-------------------------------------------------------------------------------
Vref offset: 0
Left:    -25 -27 -26 -24 -25 -22 -23 -26 -26 -24 -24 -25 -26 -22 -21 -22 -25 -20
Right:    21  22  22  21  25  24  21  23  19  21  20  23  18  25  18  22  22  20
-------------------------------------------------------------------------------
Prev Pi:  35  36  35  35  36  35  34  36  34  34  35  33  35  34  36  36  35  31
New Pi:   33  34  33  34  36  36  33  35  31  33  33  32  31  35  35  36  34  31
Diff:     -2  -2  -2  -1   0   1  -1  -1  -3  -1  -2  -1  -4   1  -1   0  -1   0

Results for N2.C1.D1.R1: 
           0   1   2   3   4   5   6   7   8   9  10  11  12  13  14  15  16  17
-------------------------------------------------------------------------------
Vref offset: 0
Left:    -26 -27 -25 -24 -26 -23 -23 -26 -26 -24 -23 -25 -26 -21 -20 -20 -24 -21
Right:    21  20  24  25  26  23  23  24  20  21  20  22  19  23  21  18  18  20
-------------------------------------------------------------------------------
Prev Pi:  35  36  35  35  36  35  34  36  34  34  35  33  35  34  36  36  35  31
New Pi:   33  33  35  35  36  35  34  35  31  33  34  32  32  35  36  35  32  31
Diff:     -2  -3   0   0   0   0   0  -1  -3  -1  -1  -1  -3   1   0  -1  -3   0

Results for N2.C2.D0.R0: 
           0   1   2   3   4   5   6   7   8   9  10  11  12  13  14  15  16  17
-------------------------------------------------------------------------------
Vref offset: 0
Left:    -23 -24 -27 -25 -24 -20 -24 -25 -25 -23 -24 -26 -27 -28 -24 -26 -26 -25
Right:    30  27  24  26  25  27  28  27  24  23  21  24  26  26  29  23  25  25
-------------------------------------------------------------------------------
Prev Pi:  33  34  35  34  33  36  33  37  35  35  34  36  35  33  36  36  36  35
New Pi:   36  35  34  34  33  39  35  38  35  35  33  35  35  32  38  35  36  35
Diff:      3   1  -1   0   0   3   2   1   0   0  -1  -1   0  -1   2  -1   0   0

Results for N2.C2.D0.R1: 
           0   1   2   3   4   5   6   7   8   9  10  11  12  13  14  15  16  17
-------------------------------------------------------------------------------
Vref offset: 0
Left:    -23 -24 -26 -25 -25 -20 -24 -25 -24 -23 -24 -26 -26 -27 -24 -27 -26 -24
Right:    31  25  24  27  24  25  27  27  26  23  25  24  28  26  27  24  26  26
-------------------------------------------------------------------------------
Prev Pi:  33  34  35  34  33  36  33  37  35  35  34  36  35  33  36  36  36  35
New Pi:   37  34  34  35  33  38  34  38  36  35  34  35  36  33  37  35  36  36
Diff:      4   0  -1   1   0   2   1   1   1   0   0  -1   1   0   1  -1   0   1

Results for N2.C2.D1.R0: 
           0   1   2   3   4   5   6   7   8   9  10  11  12  13  14  15  16  17
-------------------------------------------------------------------------------
Vref offset: 0
Left:    -22 -22 -25 -26 -23 -19 -24 -22 -22 -20 -22 -24 -25 -26 -23 -24 -24 -22
Right:    29  23  24  24  22  26  26  23  25  21  19  25  24  25  27  22  24  23
-------------------------------------------------------------------------------
Prev Pi:  35  35  37  36  36  36  35  39  36  37  36  37  36  34  37  38  37  37
New Pi:   38  35  37  35  36  39  36  39  37  37  35  37  36  34  39  37  37  37
Diff:      3   0   0  -1   0   3   1   0   1   0  -1   0   0   0   2  -1   0   0

Results for N2.C2.D1.R1: 
           0   1   2   3   4   5   6   7   8   9  10  11  12  13  14  15  16  17
-------------------------------------------------------------------------------
Vref offset: 0
Left:    -22 -22 -26 -26 -25 -20 -23 -22 -21 -20 -21 -23 -25 -25 -22 -24 -23 -24
Right:    31  24  22  25  22  27  25  23  24  23  19  25  26  26  28  21  23  25
-------------------------------------------------------------------------------
Prev Pi:  35  35  37  36  36  36  35  39  36  37  36  37  36  34  37  38  37  37
New Pi:   39  36  35  36  35  39  36  39  37  38  35  38  36  34  40  37  37  37
Diff:      4   1  -2   0  -1   3   1   0   1   1  -1   1   0   0   3  -1   0   0

Results for N2.C3.D0.R0: 
           0   1   2   3   4   5   6   7   8   9  10  11  12  13  14  15  16  17
-------------------------------------------------------------------------------
Vref offset: 0
Left:    -25 -26 -27 -26 -25 -25 -22 -23 -24 -20 -25 -26 -25 -23 -24 -27 -26 -22
Right:    31  25  25  25  27  31  26  26  24  24  25  21  26  28  31  26  24  25
-------------------------------------------------------------------------------
Prev Pi:  36  33  36  34  34  35  36  35  33  35  33  35  33  33  35  35  36  31
New Pi:   39  33  35  34  35  38  38  36  33  37  33  33  33  35  38  35  35  32
Diff:      3   0  -1   0   1   3   2   1   0   2   0  -2   0   2   3   0  -1   1

Results for N2.C3.D0.R1: 
           0   1   2   3   4   5   6   7   8   9  10  11  12  13  14  15  16  17
-------------------------------------------------------------------------------
Vref offset: 0
Left:    -24 -26 -27 -26 -25 -26 -22 -24 -24 -21 -25 -27 -25 -23 -25 -27 -26 -22
Right:    27  27  24  27  28  28  23  28  26  30  25  21  25  27  28  25  24  26
-------------------------------------------------------------------------------
Prev Pi:  36  33  36  34  34  35  36  35  33  35  33  35  33  33  35  35  36  31
New Pi:   37  33  35  34  35  36  36  37  34  39  33  32  33  35  36  34  35  33
Diff:      1   0  -1   0   1   1   0   2   1   4   0  -3   0   2   1  -1  -1   2

Results for N2.C3.D1.R0: 
           0   1   2   3   4   5   6   7   8   9  10  11  12  13  14  15  16  17
-------------------------------------------------------------------------------
Vref offset: 0
Left:    -23 -25 -25 -25 -24 -23 -21 -21 -25 -19 -25 -25 -25 -23 -23 -25 -24 -23
Right:    27  28  23  27  25  30  23  24  21  25  25  16  19  24  30  25  22  23
-------------------------------------------------------------------------------
Prev Pi:  38  34  37  35  36  36  37  37  36  37  35  36  35  35  36  36  37  35
New Pi:   40  35  36  36  36  39  38  38  34  40  35  32  32  35  39  36  36  35
Diff:      2   1  -1   1   0   3   1   1  -2   3   0  -4  -3   0   3   0  -1   0

Results for N2.C3.D1.R1: 
           0   1   2   3   4   5   6   7   8   9  10  11  12  13  14  15  16  17
-------------------------------------------------------------------------------
Vref offset: 0
Left:    -22 -24 -24 -25 -25 -24 -21 -21 -25 -19 -25 -25 -25 -22 -23 -25 -25 -24
Right:    27  27  23  27  25  30  24  23  22  28  24  20  21  24  30  24  23  21
-------------------------------------------------------------------------------
Prev Pi:  38  34  37  35  36  36  37  37  36  37  35  36  35  35  36  36  37  35
New Pi:   40  35  37  36  36  39  38  38  35  41  35  34  33  36  39  36  36  34
Diff:      2   1   0   1   0   3   1   1  -1   4   0  -2  -2   1   3   0  -1  -1

STOP_DATA_RX_DQS_ADV
N4.C3.D1.R0.S00: TxDq : plus1 = 1, minus1 = 0, PI = 32, DB = 0
N6.C3.D0.R0.S15: RdPtrOffsetTxDqs: 07
N0.C3.D0.R0.S10: PiTxDqs: 50
N2: RunTrainStep: Final status = 0
N4.C3.D1.R0.S01: TxDqs: plus1 = 1, minus1 = 0, PI = 53, DB = 1
N6.C3.D0.R0.S15: PiTxDqs: 10
N0.C3.D0.R0.S11: wrcmd2dqsstartlatency: 04

END - Rd Timing Centering 2D Training  Time         2357 ms
N4.C3.D1.R0.S01: TxDq : plus1 = 1, minus1 = 0, PI = 18, DB = 0
N6.C3.D0.R0.S16: wrcmd2dqsstartlatency: 04
N0.C3.D0.R0.S11: RdPtrOffsetTxDq: 06

START - Wr Timing Centering 2D Training
N4.C3.D1.R0.S02: TxDqs: plus1 = 1, minus1 = 0, PI = 40, DB = 0
N6.C3.D0.R0.S16: RdPtrOffsetTxDq: 05
N0.C3.D0.R0.S11: RdPtrOffsetTxDqs: 07
N2: 

Adv Strobe Centering(MARGIN_TX_DQ): GetMultiVref: patternLength = 13, stepSize = 1, numPoints = 1
N4.C3.D1.R0.S02: TxDq : plus1 = 0, minus1 = 1, PI = 05, DB = 1
N6.C3.D0.R0.S16: RdPtrOffsetTxDqs: 07
N0.C3.D0.R0.S11: PiTxDqs: 40
N2: GetMargins: Level = 1, group = 12, mode = 0, scope = 4
N4.C3.D1.R0.S03: TxDqs: plus1 = 1, minus1 = 0, PI = 27, DB = 0
N6.C3.D0.R0.S16: PiTxDqs: 28
N0.C3.D0.R0.S12: wrcmd2dqsstartlatency: 04
N4.C3.D1.R0.S03: TxDq : plus1 = 1, minus1 = 0, PI = 55, DB = 1
N6.C3.D0.R0.S17: wrcmd2dqsstartlatency: 04
N0.C3.D0.R0.S12: RdPtrOffsetTxDq: 05
N4.C3.D1.R0.S04: TxDqs: plus1 = 1, minus1 = 0, PI = 55, DB = 1
N6.C3.D0.R0.S17: RdPtrOffsetTxDq: 05
N0.C3.D0.R0.S12: RdPtrOffsetTxDqs: 07
N4.C3.D1.R0.S04: TxDq : plus1 = 1, minus1 = 0, PI = 18, DB = 0
N6.C3.D0.R0.S17: RdPtrOffsetTxDqs: 06
N0.C3.D0.R0.S12: PiTxDqs: 24
N4.C3.D1.R0.S05: TxDqs: plus1 = 0, minus1 = 1, PI = 02, DB = 1
N6.C3.D0.R0.S17: PiTxDqs: 63
N0.C3.D0.R0.S13: wrcmd2dqsstartlatency: 04
N4.C3.D1.R0.S05: TxDq : plus1 = 1, minus1 = 0, PI = 32, DB = 0
N6.C3.D0.R0.S00: RdPtrOffsetTxDq: 07
N0.C3.D0.R0.S13: RdPtrOffsetTxDq: 05
N4.C3.D1.R0.S06: TxDqs: plus1 = 1, minus1 = 0, PI = 18, DB = 0
N6.C3.D0.R0.S01: RdPtrOffsetTxDq: 07
N0.C3.D0.R0.S13: RdPtrOffsetTxDqs: 06
N4.C3.D1.R0.S06: TxDq : plus1 = 1, minus1 = 0, PI = 46, DB = 0
N6.C3.D0.R0.S02: RdPtrOffsetTxDq: 07
N0.C3.D0.R0.S13: PiTxDqs: 50
N4.C3.D1.R0.S07: TxDqs: plus1 = 1, minus1 = 0, PI = 34, DB = 0
N6.C3.D0.R0.S03: RdPtrOffsetTxDq: 06
N0.C3.D0.R0.S14: wrcmd2dqsstartlatency: 04
N4.C3.D1.R0.S07: TxDq : plus1 = 1, minus1 = 0, PI = 63, DB = 1
N6.C3.D0.R0.S04: RdPtrOffsetTxDq: 06
N0.C3.D0.R0.S14: RdPtrOffsetTxDq: 05
N4.C3.D1.R0.S08: TxDqs: plus1 = 0, minus1 = 1, PI = 05, DB = 1
N6.C3.D0.R0.S05: RdPtrOffsetTxDq: 06
N0.C3.D0.R0.S14: RdPtrOffsetTxDqs: 07
N4.C3.D1.R0.S08: TxDq : plus1 = 1, minus1 = 0, PI = 33, DB = 0
N6.C3.D0.R0.S06: RdPtrOffsetTxDq: 06
N0.C3.D0.R0.S14: PiTxDqs: 01
N4.C3.D1.R0.S09: TxDqs: plus1 = 0, minus1 = 1, PI = 02, DB = 1
N6.C3.D0.R0.S07: RdPtrOffsetTxDq: 06
N0.C3.D0.R0.S15: wrcmd2dqsstartlatency: 04
N4.C3.D1.R0.S09: TxDq : plus1 = 1, minus1 = 0, PI = 29, DB = 0
N6.C3.D0.R0.S08: RdPtrOffsetTxDq: 06
N0.C3.D0.R0.S15: RdPtrOffsetTxDq: 05
N4.C3.D1.R0.S10: TxDqs: plus1 = 1, minus1 = 0, PI = 53, DB = 1
N6.C3.D0.R0.S09: RdPtrOffsetTxDq: 07
N0.C3.D0.R0.S15: RdPtrOffsetTxDqs: 07
N4.C3.D1.R0.S10: TxDq : plus1 = 1, minus1 = 0, PI = 17, DB = 0
N6.C3.D0.R0.S10: RdPtrOffsetTxDq: 07
N0.C3.D0.R0.S15: PiTxDqs: 20
N4.C3.D1.R0.S11: TxDqs: plus1 = 1, minus1 = 0, PI = 41, DB = 0
N6.C3.D0.R0.S11: RdPtrOffsetTxDq: 07
N0.C3.D0.R0.S16: wrcmd2dqsstartlatency: 04
N4.C3.D1.R0.S11: TxDq : plus1 = 0, minus1 = 1, PI = 03, DB = 1
N6.C3.D0.R0.S12: RdPtrOffsetTxDq: 06
N0.C3.D0.R0.S16: RdPtrOffsetTxDq: 05
N4.C3.D1.R0.S12: TxDqs: plus1 = 1, minus1 = 0, PI = 29, DB = 0
N6.C3.D0.R0.S13: RdPtrOffsetTxDq: 06
N0.C3.D0.R0.S16: RdPtrOffsetTxDqs: 07
N4.C3.D1.R0.S12: TxDq : plus1 = 1, minus1 = 0, PI = 57, DB = 1
N6.C3.D0.R0.S14: RdPtrOffsetTxDq: 06
N0.C3.D0.R0.S16: PiTxDqs: 29
N4.C3.D1.R0.S13: TxDqs: plus1 = 1, minus1 = 0, PI = 54, DB = 1
N6.C3.D0.R0.S15: RdPtrOffsetTxDq: 06
N0.C3.D0.R0.S17: wrcmd2dqsstartlatency: 04
N4.C3.D1.R0.S13: TxDq : plus1 = 1, minus1 = 0, PI = 19, DB = 0
N6.C3.D0.R0.S16: RdPtrOffsetTxDq: 06
N0.C3.D0.R0.S17: RdPtrOffsetTxDq: 05
N4.C3.D1.R0.S14: TxDqs: plus1 = 0, minus1 = 1, PI = 05, DB = 1
N6.C3.D0.R0.S17: RdPtrOffsetTxDq: 06
N0.C3.D0.R0.S17: RdPtrOffsetTxDqs: 07
N4.C3.D1.R0.S14: TxDq : plus1 = 1, minus1 = 0, PI = 33, DB = 0
N6.C3.D0.R0.S00: RdPtrOffsetTxDq: 08
N0.C3.D0.R0.S17: PiTxDqs: 06
N4.C3.D1.R0.S15: TxDqs: plus1 = 1, minus1 = 0, PI = 18, DB = 0
N6.C3.D0.R0.S01: RdPtrOffsetTxDq: 08
N0.C3.D0.R0.S00: RdPtrOffsetTxDq: 07
N4.C3.D1.R0.S15: TxDq : plus1 = 1, minus1 = 0, PI = 48, DB = 0
N6.C3.D0.R0.S02: RdPtrOffsetTxDq: 08
N0.C3.D0.R0.S01: RdPtrOffsetTxDq: 07
N4.C3.D1.R0.S16: TxDqs: plus1 = 1, minus1 = 0, PI = 35, DB = 0
N6.C3.D0.R0.S03: RdPtrOffsetTxDq: 07
N0.C3.D0.R0.S02: RdPtrOffsetTxDq: 07
N4.C3.D1.R0.S16: TxDq : plus1 = 0, minus1 = 1, PI = 00, DB = 1
N6.C3.D0.R0.S04: RdPtrOffsetTxDq: 07
N0.C3.D0.R0.S03: RdPtrOffsetTxDq: 06
N4.C3.D1.R0.S17: TxDqs: plus1 = 0, minus1 = 1, PI = 05, DB = 1
N6.C3.D0.R0.S05: RdPtrOffsetTxDq: 07
N0.C3.D0.R0.S04: RdPtrOffsetTxDq: 06
N4.C3.D1.R0.S17: TxDq : plus1 = 1, minus1 = 0, PI = 33, DB = 0
N6.C3.D0.R0.S06: RdPtrOffsetTxDq: 07
N0.C3.D0.R0.S05: RdPtrOffsetTxDq: 06
N4.C3.D1.R1.S00: TxDqs: plus1 = 0, minus1 = 1, PI = 03, DB = 1
N6.C3.D0.R0.S07: RdPtrOffsetTxDq: 07
N0.C3.D0.R0.S06: RdPtrOffsetTxDq: 06
N4.C3.D1.R1.S00: TxDq : plus1 = 1, minus1 = 0, PI = 32, DB = 0
N6.C3.D0.R0.S08: RdPtrOffsetTxDq: 07
N0.C3.D0.R0.S07: RdPtrOffsetTxDq: 07
N4.C3.D1.R1.S01: TxDqs: plus1 = 1, minus1 = 0, PI = 53, DB = 1
N6.C3.D0.R0.S09: RdPtrOffsetTxDq: 08
N0.C3.D0.R0.S08: RdPtrOffsetTxDq: 06
N4.C3.D1.R1.S01: TxDq : plus1 = 1, minus1 = 0, PI = 18, DB = 0
N6.C3.D0.R0.S10: RdPtrOffsetTxDq: 08
N0.C3.D0.R0.S09: RdPtrOffsetTxDq: 07
N4.C3.D1.R1.S02: TxDqs: plus1 = 1, minus1 = 0, PI = 40, DB = 0
N6.C3.D0.R0.S11: RdPtrOffsetTxDq: 08
N0.C3.D0.R0.S10: RdPtrOffsetTxDq: 07
N4.C3.D1.R1.S02: TxDq : plus1 = 0, minus1 = 1, PI = 05, DB = 1
N6.C3.D0.R0.S12: RdPtrOffsetTxDq: 07
N0.C3.D0.R0.S11: RdPtrOffsetTxDq: 07
N4.C3.D1.R1.S03: TxDqs: plus1 = 1, minus1 = 0, PI = 27, DB = 0
N6.C3.D0.R0.S13: RdPtrOffsetTxDq: 07
N0.C3.D0.R0.S12: RdPtrOffsetTxDq: 06
N4.C3.D1.R1.S03: TxDq : plus1 = 1, minus1 = 0, PI = 55, DB = 1
N6.C3.D0.R0.S14: RdPtrOffsetTxDq: 07
N0.C3.D0.R0.S13: RdPtrOffsetTxDq: 06
N4.C3.D1.R1.S04: TxDqs: plus1 = 1, minus1 = 0, PI = 55, DB = 1
N6.C3.D0.R0.S15: RdPtrOffsetTxDq: 07
N0.C3.D0.R0.S14: RdPtrOffsetTxDq: 06
N4.C3.D1.R1.S04: TxDq : plus1 = 1, minus1 = 0, PI = 18, DB = 0
N6.C3.D0.R0.S16: RdPtrOffsetTxDq: 07
N0.C3.D0.R0.S15: RdPtrOffsetTxDq: 06
N4.C3.D1.R1.S05: TxDqs: plus1 = 0, minus1 = 1, PI = 02, DB = 1
N6.C3.D0.R0.S17: RdPtrOffsetTxDq: 07
N0.C3.D0.R0.S16: RdPtrOffsetTxDq: 06
N4.C3.D1.R1.S05: TxDq : plus1 = 1, minus1 = 0, PI = 32, DB = 0
N6.C3.D0.R0.S00: Total Delay in PI ticks: TxDQ = 986
N0.C3.D0.R0.S17: RdPtrOffsetTxDq: 06
N4.C3.D1.R1.S06: TxDqs: plus1 = 1, minus1 = 0, PI = 18, DB = 0
N6.C3.D0.R0.S01: Total Delay in PI ticks: TxDQ = 971
N0.C3.D0.R0.S00: RdPtrOffsetTxDq: 08
N4.C3.D1.R1.S06: TxDq : plus1 = 1, minus1 = 0, PI = 46, DB = 0
N6.C3.D0.R0.S02: Total Delay in PI ticks: TxDQ = 965
N0.C3.D0.R0.S01: RdPtrOffsetTxDq: 08
N4.C3.D1.R1.S07: TxDqs: plus1 = 1, minus1 = 0, PI = 34, DB = 0
N6.C3.D0.R0.S03: Total Delay in PI ticks: TxDQ = 946
N0.C3.D0.R0.S02: RdPtrOffsetTxDq: 08
N4.C3.D1.R1.S07: TxDq : plus1 = 1, minus1 = 0, PI = 63, DB = 1
N6.C3.D0.R0.S04: Total Delay in PI ticks: TxDQ = 908
N0.C3.D0.R0.S03: RdPtrOffsetTxDq: 07
N4.C3.D1.R1.S08: TxDqs: plus1 = 0, minus1 = 1, PI = 05, DB = 1
N6.C3.D0.R0.S05: Total Delay in PI ticks: TxDQ = 923
N0.C3.D0.R0.S04: RdPtrOffsetTxDq: 07
N4.C3.D1.R1.S08: TxDq : plus1 = 1, minus1 = 0, PI = 33, DB = 0
N6.C3.D0.R0.S06: Total Delay in PI ticks: TxDQ = 941
N0.C3.D0.R0.S05: RdPtrOffsetTxDq: 07
N4.C3.D1.R1.S09: TxDqs: plus1 = 0, minus1 = 1, PI = 02, DB = 1
N6.C3.D0.R0.S07: Total Delay in PI ticks: TxDQ = 954
N0.C3.D0.R0.S06: RdPtrOffsetTxDq: 07
N4.C3.D1.R1.S09: TxDq : plus1 = 1, minus1 = 0, PI = 29, DB = 0
N6.C3.D0.R0.S08: Total Delay in PI ticks: TxDQ = 928
N0.C3.D0.R0.S07: RdPtrOffsetTxDq: 08
N4.C3.D1.R1.S10: TxDqs: plus1 = 1, minus1 = 0, PI = 53, DB = 1
N6.C3.D0.R0.S09: Total Delay in PI ticks: TxDQ = 986
N0.C3.D0.R0.S08: RdPtrOffsetTxDq: 07
N4.C3.D1.R1.S10: TxDq : plus1 = 1, minus1 = 0, PI = 17, DB = 0
N6.C3.D0.R0.S10: Total Delay in PI ticks: TxDQ = 971
N0.C3.D0.R0.S09: RdPtrOffsetTxDq: 08
N4.C3.D1.R1.S11: TxDqs: plus1 = 1, minus1 = 0, PI = 41, DB = 0
N6.C3.D0.R0.S11: Total Delay in PI ticks: TxDQ = 962
N0.C3.D0.R0.S10: RdPtrOffsetTxDq: 08
N4.C3.D1.R1.S11: TxDq : plus1 = 0, minus1 = 1, PI = 03, DB = 1
N6.C3.D0.R0.S12: Total Delay in PI ticks: TxDQ = 944
N0.C3.D0.R0.S11: RdPtrOffsetTxDq: 08
N4.C3.D1.R1.S12: TxDqs: plus1 = 1, minus1 = 0, PI = 29, DB = 0
N6.C3.D0.R0.S13: Total Delay in PI ticks: TxDQ = 908
N0.C3.D0.R0.S12: RdPtrOffsetTxDq: 07
N4.C3.D1.R1.S12: TxDq : plus1 = 1, minus1 = 0, PI = 57, DB = 1
N6.C3.D0.R0.S14: Total Delay in PI ticks: TxDQ = 925
N0.C3.D0.R0.S13: RdPtrOffsetTxDq: 07
N4.C3.D1.R1.S13: TxDqs: plus1 = 1, minus1 = 0, PI = 54, DB = 1
N6.C3.D0.R0.S15: Total Delay in PI ticks: TxDQ = 939
N0.C3.D0.R0.S14: RdPtrOffsetTxDq: 07
N4.C3.D1.R1.S13: TxDq : plus1 = 1, minus1 = 0, PI = 19, DB = 0
N6.C3.D0.R0.S16: Total Delay in PI ticks: TxDQ = 957
N0.C3.D0.R0.S15: RdPtrOffsetTxDq: 07
N4.C3.D1.R1.S14: TxDqs: plus1 = 0, minus1 = 1, PI = 05, DB = 1
N6.C3.D0.R0.S17: Total Delay in PI ticks: TxDQ = 927
N0.C3.D0.R0.S16: RdPtrOffsetTxDq: 07
N4.C3.D1.R1.S14: TxDq : plus1 = 1, minus1 = 0, PI = 33, DB = 0
N6.C3.D0.R1.S00: wrcmd2dqsstartlatency: 04
N0.C3.D0.R0.S17: RdPtrOffsetTxDq: 07
N4.C3.D1.R1.S15: TxDqs: plus1 = 1, minus1 = 0, PI = 18, DB = 0
N6.C3.D0.R1.S00: RdPtrOffsetTxDq: 06
N0.C3.D0.R0.S00: Total Delay in PI ticks: TxDQ = 993
N4.C3.D1.R1.S15: TxDq : plus1 = 1, minus1 = 0, PI = 48, DB = 0
N6.C3.D0.R1.S00: RdPtrOffsetTxDqs: 07
N0.C3.D0.R0.S01: Total Delay in PI ticks: TxDQ = 976
N4.C3.D1.R1.S16: TxDqs: plus1 = 1, minus1 = 0, PI = 35, DB = 0
N6.C3.D0.R1.S00: PiTxDqs: 51
N0.C3.D0.R0.S02: Total Delay in PI ticks: TxDQ = 966
N4.C3.D1.R1.S16: TxDq : plus1 = 0, minus1 = 1, PI = 00, DB = 1
N6.C3.D0.R1.S01: wrcmd2dqsstartlatency: 04
N0.C3.D0.R0.S03: Total Delay in PI ticks: TxDQ = 947
N4.C3.D1.R1.S17: TxDqs: plus1 = 0, minus1 = 1, PI = 05, DB = 1
N6.C3.D0.R1.S01: RdPtrOffsetTxDq: 06
N0.C3.D0.R0.S04: Total Delay in PI ticks: TxDQ = 914
N4.C3.D1.R1.S17: TxDq : plus1 = 1, minus1 = 0, PI = 33, DB = 0
N6.C3.D0.R1.S01: RdPtrOffsetTxDqs: 07
N0.C3.D0.R0.S05: Total Delay in PI ticks: TxDQ = 928
END_DATA_TX_DQ
N6.C3.D0.R1.S01: PiTxDqs: 37
N0.C3.D0.R0.S06: Total Delay in PI ticks: TxDQ = 941
N4: RunTrainStep: Final status = 0
N6.C3.D0.R1.S02: wrcmd2dqsstartlatency: 04
N0.C3.D0.R0.S07: Total Delay in PI ticks: TxDQ = 959

END - Basic Write DQ/DQS Training      Time         53209 ms
N6.C3.D0.R1.S02: RdPtrOffsetTxDq: 05
N0.C3.D0.R0.S08: Total Delay in PI ticks: TxDQ = 932
N4.C0: JCK cmd timing = 1N
N6.C3.D0.R1.S02: RdPtrOffsetTxDqs: 07
N0.C3.D0.R0.S09: Total Delay in PI ticks: TxDQ = 992
N4.C0: RdCmd2DataValidLatency = 21, (dlyFrmS = 15, clEff = 10, earlyCas = 0, selNTiming = 0)
N6.C3.D0.R1.S02: PiTxDqs: 27
N0.C3.D0.R0.S10: Total Delay in PI ticks: TxDQ = 976
N4.C1: RdCmd2DataValidLatency = 21, (dlyFrmS = 15, clEff = 10, earlyCas = 0, selNTiming = 0)
N6.C3.D0.R1.S03: wrcmd2dqsstartlatency: 04
N0.C3.D0.R0.S11: Total Delay in PI ticks: TxDQ = 967
N4.C2: JCK cmd timing = 1N
N6.C3.D0.R1.S03: RdPtrOffsetTxDq: 05
N0.C3.D0.R0.S12: Total Delay in PI ticks: TxDQ = 949
N4.C2: RdCmd2DataValidLatency = 21, (dlyFrmS = 15, clEff = 10, earlyCas = 0, selNTiming = 0)
N6.C3.D0.R1.S03: RdPtrOffsetTxDqs: 07
N0.C3.D0.R0.S13: Total Delay in PI ticks: TxDQ = 914
N4.C3: RdCmd2DataValidLatency = 21, (dlyFrmS = 15, clEff = 10, earlyCas = 0, selNTiming = 0)
N6.C3.D0.R1.S03: PiTxDqs: 11
N0.C3.D0.R0.S14: Total Delay in PI ticks: TxDQ = 927
N4: JckSetOdtDynTiming[2] BL8:
N6.C3.D0.R1.S04: wrcmd2dqsstartlatency: 04
N0.C3.D0.R0.S15: Total Delay in PI ticks: TxDQ = 945
N6.C3.D0.R1.S04: RdPtrOffsetTxDq: 05
N0.C3.D0.R0.S16: Total Delay in PI ticks: TxDQ = 956
N6.C3.D0.R1.S04: RdPtrOffsetTxDqs: 06
N0.C3.D0.R0.S17: Total Delay in PI ticks: TxDQ = 934
N6.C3.D0.R1.S04: PiTxDqs: 39
N0.C3.D0.R1.S00: wrcmd2dqsstartlatency: 04
N4.C0: minRcvEnDelay = 199 maxRcvEnDelay = 301 ==> rdwidth = 6 rddly = 2 wrwidth = 6 wrdly = 0
N6.C3.D0.R1.S05: wrcmd2dqsstartlatency: 04
N0.C3.D0.R1.S00: RdPtrOffsetTxDq: 06
N4.C1: minRcvEnDelay = 194 maxRcvEnDelay = 329 ==> rdwidth = 6 rddly = 2 wrwidth = 6 wrdly = 0
N6.C3.D0.R1.S05: RdPtrOffsetTxDq: 05
N0.C3.D0.R1.S00: RdPtrOffsetTxDqs: 07
N4.C2: minRcvEnDelay = 197 maxRcvEnDelay = 302 ==> rdwidth = 6 rddly = 2 wrwidth = 6 wrdly = 0
N6.C3.D0.R1.S05: RdPtrOffsetTxDqs: 06
N0.C3.D0.R1.S00: PiTxDqs: 61
N4.C3: minRcvEnDelay = 202 maxRcvEnDelay = 330 ==> rdwidth = 6 rddly = 2 wrwidth = 6 wrdly = 0
N6.C3.D0.R1.S05: PiTxDqs: 54
N0.C3.D0.R1.S01: wrcmd2dqsstartlatency: 04
N4.C0: Memory Electrical TurnAround timings:
N6.C3.D0.R1.S06: wrcmd2dqsstartlatency: 04
N0.C3.D0.R1.S01: RdPtrOffsetTxDq: 06
N4.C0:      tCCD  =  0, tWWDR =  3, tRRDD =  2, tWWDD =  3, tWRDR =  1, tWRDR_UPPER =  0, tRRDR =  0
N6.C3.D0.R1.S06: RdPtrOffsetTxDq: 05
N0.C3.D0.R1.S01: RdPtrOffsetTxDqs: 07
N4.C0:      tRWDD =  2, tRWDR =  2, tWRDD =  1, tRWSR =  2
N6.C3.D0.R1.S06: RdPtrOffsetTxDqs: 07
N0.C3.D0.R1.S01: PiTxDqs: 42
N4.C0: TCOTHP: T_RWSR = 0x2, T_RWDD = 0x2
N6.C3.D0.R1.S06: PiTxDqs: 02
N0.C3.D0.R1.S02: wrcmd2dqsstartlatency: 04
N4.C0:      tCCD_WR =  0, tWRDS =  2, tRWDS =  2, tWWDS =  3, tRRDS =  1
N6.C3.D0.R1.S07: wrcmd2dqsstartlatency: 04
N0.C3.D0.R1.S02: RdPtrOffsetTxDq: 05
N4.C1: Memory Electrical TurnAround timings:
N6.C3.D0.R1.S07: RdPtrOffsetTxDq: 05
N0.C3.D0.R1.S02: RdPtrOffsetTxDqs: 07
N4.C1:      tCCD  =  0, tWWDR =  3, tRRDD =  2, tWWDD =  3, tWRDR =  1, tWRDR_UPPER =  0, tRRDR =  0
N6.C3.D0.R1.S07: RdPtrOffsetTxDqs: 07
N0.C3.D0.R1.S02: PiTxDqs: 32
N4.C1:      tRWDD =  2, tRWDR =  2, tWRDD =  1, tRWSR =  2
N6.C3.D0.R1.S07: PiTxDqs: 21
N0.C3.D0.R1.S03: wrcmd2dqsstartlatency: 04
N4.C1: TCOTHP: T_RWSR = 0x2, T_RWDD = 0x2
N6.C3.D0.R1.S08: wrcmd2dqsstartlatency: 04
N0.C3.D0.R1.S03: RdPtrOffsetTxDq: 05
N4.C1:      tCCD_WR =  0, tWRDS =  2, tRWDS =  2, tWWDS =  3, tRRDS =  1
N6.C3.D0.R1.S08: RdPtrOffsetTxDq: 05
N0.C3.D0.R1.S03: RdPtrOffsetTxDqs: 07
N4.C2: Memory Electrical TurnAround timings:
N6.C3.D0.R1.S08: RdPtrOffsetTxDqs: 06
N0.C3.D0.R1.S03: PiTxDqs: 17
N4.C2:      tCCD  =  0, tWWDR =  3, tRRDD =  2, tWWDD =  3, tWRDR =  1, tWRDR_UPPER =  0, tRRDR =  0
N6.C3.D0.R1.S08: PiTxDqs: 56
N0.C3.D0.R1.S04: wrcmd2dqsstartlatency: 04
N4.C2:      tRWDD =  2, tRWDR =  2, tWRDD =  1, tRWSR =  2
N6.C3.D0.R1.S09: wrcmd2dqsstartlatency: 04
N0.C3.D0.R1.S04: RdPtrOffsetTxDq: 05
N4.C2: TCOTHP: T_RWSR = 0x2, T_RWDD = 0x2
N6.C3.D0.R1.S09: RdPtrOffsetTxDq: 06
N0.C3.D0.R1.S04: RdPtrOffsetTxDqs: 06
N4.C2:      tCCD_WR =  0, tWRDS =  2, tRWDS =  2, tWWDS =  3, tRRDS =  1
N6.C3.D0.R1.S09: RdPtrOffsetTxDqs: 07
N0.C3.D0.R1.S04: PiTxDqs: 47
N4.C3: Memory Electrical TurnAround timings:
N6.C3.D0.R1.S09: PiTxDqs: 51
N0.C3.D0.R1.S05: wrcmd2dqsstartlatency: 04
N4.C3:      tCCD  =  0, tWWDR =  3, tRRDD =  2, tWWDD =  3, tWRDR =  1, tWRDR_UPPER =  0, tRRDR =  0
N6.C3.D0.R1.S10: wrcmd2dqsstartlatency: 04
N0.C3.D0.R1.S05: RdPtrOffsetTxDq: 05
N4.C3:      tRWDD =  2, tRWDR =  2, tWRDD =  1, tRWSR =  2
N6.C3.D0.R1.S10: RdPtrOffsetTxDq: 06
N0.C3.D0.R1.S05: RdPtrOffsetTxDqs: 06
N4.C3: TCOTHP: T_RWSR = 0x2, T_RWDD = 0x2
N6.C3.D0.R1.S10: RdPtrOffsetTxDqs: 07
N0.C3.D0.R1.S05: PiTxDqs: 59
N4.C3:      tCCD_WR =  0, tWRDS =  2, tRWDS =  2, tWWDS =  3, tRRDS =  1
N6.C3.D0.R1.S10: PiTxDqs: 36
N0.C3.D0.R1.S06: wrcmd2dqsstartlatency: 04

START - Rd Timing Centering 2D Training
N6.C3.D0.R1.S11: wrcmd2dqsstartlatency: 04
N0.C3.D0.R1.S06: RdPtrOffsetTxDq: 05
N4: 

Adv Strobe Centering(MARGIN_RX_DQ): GetMultiVref: patternLength = 13, stepSize = 1, numPoints = 1
N6.C3.D0.R1.S11: RdPtrOffsetTxDq: 05
N0.C3.D0.R1.S06: RdPtrOffsetTxDqs: 07
N6.C3.D0.R1.S11: RdPtrOffsetTxDqs: 07
N0.C3.D0.R1.S06: PiTxDqs: 10
N4: GetMargins: Level = 1, group = 11, mode = 0, scope = 4
N6.C3.D0.R1.S11: PiTxDqs: 25
N0.C3.D0.R1.S07: wrcmd2dqsstartlatency: 04
N6.C3.D0.R1.S12: wrcmd2dqsstartlatency: 04
N0.C3.D0.R1.S07: RdPtrOffsetTxDq: 05
N6.C3.D0.R1.S12: RdPtrOffsetTxDq: 05
N0.C3.D0.R1.S07: RdPtrOffsetTxDqs: 07
N6.C3.D0.R1.S12: RdPtrOffsetTxDqs: 07
N0.C3.D0.R1.S07: PiTxDqs: 27
N6.C3.D0.R1.S12: PiTxDqs: 12
N0.C3.D0.R1.S08: wrcmd2dqsstartlatency: 04
N6.C3.D0.R1.S13: wrcmd2dqsstartlatency: 04
N0.C3.D0.R1.S08: RdPtrOffsetTxDq: 05
N6.C3.D0.R1.S13: RdPtrOffsetTxDq: 05
N0.C3.D0.R1.S08: RdPtrOffsetTxDqs: 06
N6.C3.D0.R1.S13: RdPtrOffsetTxDqs: 06
N0.C3.D0.R1.S08: PiTxDqs: 62
N6.C3.D0.R1.S13: PiTxDqs: 39
N0.C3.D0.R1.S09: wrcmd2dqsstartlatency: 04
N6.C3.D0.R1.S14: wrcmd2dqsstartlatency: 04
N0.C3.D0.R1.S09: RdPtrOffsetTxDq: 06
N6.C3.D0.R1.S14: RdPtrOffsetTxDq: 05
N0.C3.D0.R1.S09: RdPtrOffsetTxDqs: 07
N6.C3.D0.R1.S14: RdPtrOffsetTxDqs: 06
N0.C3.D0.R1.S09: PiTxDqs: 61
N6.C3.D0.R1.S14: PiTxDqs: 52
N0.C3.D0.R1.S10: wrcmd2dqsstartlatency: 04
N6.C3.D0.R1.S15: wrcmd2dqsstartlatency: 04
N0.C3.D0.R1.S10: RdPtrOffsetTxDq: 06
N6.C3.D0.R1.S15: RdPtrOffsetTxDq: 05
N0.C3.D0.R1.S10: RdPtrOffsetTxDqs: 07
N6.C3.D0.R1.S15: RdPtrOffsetTxDqs: 07
N0.C3.D0.R1.S10: PiTxDqs: 42
N6.C3.D0.R1.S15: PiTxDqs: 02
N0.C3.D0.R1.S11: wrcmd2dqsstartlatency: 04
N6.C3.D0.R1.S16: wrcmd2dqsstartlatency: 04
N0.C3.D0.R1.S11: RdPtrOffsetTxDq: 06
N6.C3.D0.R1.S16: RdPtrOffsetTxDq: 05
N0.C3.D0.R1.S11: RdPtrOffsetTxDqs: 07
N6.C3.D0.R1.S16: RdPtrOffsetTxDqs: 07
N0.C3.D0.R1.S11: PiTxDqs: 33
N6.C3.D0.R1.S16: PiTxDqs: 22
N0.C3.D0.R1.S12: wrcmd2dqsstartlatency: 04
N6.C3.D0.R1.S17: wrcmd2dqsstartlatency: 04
N0.C3.D0.R1.S12: RdPtrOffsetTxDq: 05
N6.C3.D0.R1.S17: RdPtrOffsetTxDq: 05
N0.C3.D0.R1.S12: RdPtrOffsetTxDqs: 07
N6.C3.D0.R1.S17: RdPtrOffsetTxDqs: 06
N0.C3.D0.R1.S12: PiTxDqs: 21
N6.C3.D0.R1.S17: PiTxDqs: 55
N0.C3.D0.R1.S13: wrcmd2dqsstartlatency: 04
N6.C3.D0.R1.S00: RdPtrOffsetTxDq: 07
N0.C3.D0.R1.S13: RdPtrOffsetTxDq: 05
N6.C3.D0.R1.S01: RdPtrOffsetTxDq: 07
N0.C3.D0.R1.S13: RdPtrOffsetTxDqs: 06
N6.C3.D0.R1.S02: RdPtrOffsetTxDq: 06
N0.C3.D0.R1.S13: PiTxDqs: 48
N6.C3.D0.R1.S03: RdPtrOffsetTxDq: 06
N0.C3.D0.R1.S14: wrcmd2dqsstartlatency: 04
N6.C3.D0.R1.S04: RdPtrOffsetTxDq: 06
N0.C3.D0.R1.S14: RdPtrOffsetTxDq: 05
N6.C3.D0.R1.S05: RdPtrOffsetTxDq: 06
N0.C3.D0.R1.S14: RdPtrOffsetTxDqs: 06
N6.C3.D0.R1.S06: RdPtrOffsetTxDq: 06
N0.C3.D0.R1.S14: PiTxDqs: 61
N6.C3.D0.R1.S07: RdPtrOffsetTxDq: 06
N0.C3.D0.R1.S15: wrcmd2dqsstartlatency: 04
N6.C3.D0.R1.S08: RdPtrOffsetTxDq: 06
N0.C3.D0.R1.S15: RdPtrOffsetTxDq: 05
N6.C3.D0.R1.S09: RdPtrOffsetTxDq: 07
N0.C3.D0.R1.S15: RdPtrOffsetTxDqs: 07
N6.C3.D0.R1.S10: RdPtrOffsetTxDq: 07
N0.C3.D0.R1.S15: PiTxDqs: 09
N6.C3.D0.R1.S11: RdPtrOffsetTxDq: 06
N0.C3.D0.R1.S16: wrcmd2dqsstartlatency: 04
N6.C3.D0.R1.S12: RdPtrOffsetTxDq: 06
N0.C3.D0.R1.S16: RdPtrOffsetTxDq: 05
N6.C3.D0.R1.S13: RdPtrOffsetTxDq: 06
N0.C3.D0.R1.S16: RdPtrOffsetTxDqs: 07
N6.C3.D0.R1.S14: RdPtrOffsetTxDq: 06
N0.C3.D0.R1.S16: PiTxDqs: 27
N6.C3.D0.R1.S15: RdPtrOffsetTxDq: 06
N0.C3.D0.R1.S17: wrcmd2dqsstartlatency: 04
N6.C3.D0.R1.S16: RdPtrOffsetTxDq: 06
N0.C3.D0.R1.S17: RdPtrOffsetTxDq: 05
N6.C3.D0.R1.S17: RdPtrOffsetTxDq: 06
N0.C3.D0.R1.S17: RdPtrOffsetTxDqs: 06
N6.C3.D0.R1.S00: RdPtrOffsetTxDq: 08
N0.C3.D0.R1.S17: PiTxDqs: 62
N6.C3.D0.R1.S01: RdPtrOffsetTxDq: 08
N0.C3.D0.R1.S00: RdPtrOffsetTxDq: 07
N6.C3.D0.R1.S02: RdPtrOffsetTxDq: 07
N0.C3.D0.R1.S01: RdPtrOffsetTxDq: 07
N6.C3.D0.R1.S03: RdPtrOffsetTxDq: 07
N0.C3.D0.R1.S02: RdPtrOffsetTxDq: 06
N6.C3.D0.R1.S04: RdPtrOffsetTxDq: 07
N0.C3.D0.R1.S03: RdPtrOffsetTxDq: 06
N6.C3.D0.R1.S05: RdPtrOffsetTxDq: 07
N0.C3.D0.R1.S04: RdPtrOffsetTxDq: 06
N6.C3.D0.R1.S06: RdPtrOffsetTxDq: 07
N0.C3.D0.R1.S05: RdPtrOffsetTxDq: 06
N6.C3.D0.R1.S07: RdPtrOffsetTxDq: 07
N0.C3.D0.R1.S06: RdPtrOffsetTxDq: 06
N6.C3.D0.R1.S08: RdPtrOffsetTxDq: 07
N0.C3.D0.R1.S07: RdPtrOffsetTxDq: 06
N6.C3.D0.R1.S09: RdPtrOffsetTxDq: 08
N0.C3.D0.R1.S08: RdPtrOffsetTxDq: 06
N6.C3.D0.R1.S10: RdPtrOffsetTxDq: 08
N0.C3.D0.R1.S09: RdPtrOffsetTxDq: 07
N6.C3.D0.R1.S11: RdPtrOffsetTxDq: 07
N0.C3.D0.R1.S10: RdPtrOffsetTxDq: 07
N6.C3.D0.R1.S12: RdPtrOffsetTxDq: 07
N0.C3.D0.R1.S11: RdPtrOffsetTxDq: 07
N6.C3.D0.R1.S13: RdPtrOffsetTxDq: 07
N0.C3.D0.R1.S12: RdPtrOffsetTxDq: 06
N6.C3.D0.R1.S14: RdPtrOffsetTxDq: 07
N0.C3.D0.R1.S13: RdPtrOffsetTxDq: 06
N6.C3.D0.R1.S15: RdPtrOffsetTxDq: 07
N0.C3.D0.R1.S14: RdPtrOffsetTxDq: 06
N6.C3.D0.R1.S16: RdPtrOffsetTxDq: 07
N0.C3.D0.R1.S15: RdPtrOffsetTxDq: 06
N6.C3.D0.R1.S17: RdPtrOffsetTxDq: 07
N0.C3.D0.R1.S16: RdPtrOffsetTxDq: 06
N6.C3.D0.R1.S00: Total Delay in PI ticks: TxDQ = 980
N0.C3.D0.R1.S17: RdPtrOffsetTxDq: 06
N6.C3.D0.R1.S01: Total Delay in PI ticks: TxDQ = 965
N0.C3.D0.R1.S00: RdPtrOffsetTxDq: 08
N6.C3.D0.R1.S02: Total Delay in PI ticks: TxDQ = 955
N0.C3.D0.R1.S01: RdPtrOffsetTxDq: 08
N6.C3.D0.R1.S03: Total Delay in PI ticks: TxDQ = 938
N0.C3.D0.R1.S02: RdPtrOffsetTxDq: 07
N6.C3.D0.R1.S04: Total Delay in PI ticks: TxDQ = 901
N0.C3.D0.R1.S03: RdPtrOffsetTxDq: 07
N6.C3.D0.R1.S05: Total Delay in PI ticks: TxDQ = 917
N0.C3.D0.R1.S04: RdPtrOffsetTxDq: 07
N6.C3.D0.R1.S06: Total Delay in PI ticks: TxDQ = 931
N0.C3.D0.R1.S05: RdPtrOffsetTxDq: 07
N6.C3.D0.R1.S07: Total Delay in PI ticks: TxDQ = 947
N0.C3.D0.R1.S06: RdPtrOffsetTxDq: 07
N6.C3.D0.R1.S08: Total Delay in PI ticks: TxDQ = 919
N0.C3.D0.R1.S07: RdPtrOffsetTxDq: 07
N6.C3.D0.R1.S09: Total Delay in PI ticks: TxDQ = 977
N0.C3.D0.R1.S08: RdPtrOffsetTxDq: 07
N6.C3.D0.R1.S10: Total Delay in PI ticks: TxDQ = 965
N0.C3.D0.R1.S09: RdPtrOffsetTxDq: 08
N6.C3.D0.R1.S11: Total Delay in PI ticks: TxDQ = 953
N0.C3.D0.R1.S10: RdPtrOffsetTxDq: 08
N6.C3.D0.R1.S12: Total Delay in PI ticks: TxDQ = 941
N0.C3.D0.R1.S11: RdPtrOffsetTxDq: 08
N6.C3.D0.R1.S13: Total Delay in PI ticks: TxDQ = 902
N0.C3.D0.R1.S12: RdPtrOffsetTxDq: 07
N6.C3.D0.R1.S14: Total Delay in PI ticks: TxDQ = 917
N0.C3.D0.R1.S13: RdPtrOffsetTxDq: 07
N6.C3.D0.R1.S15: Total Delay in PI ticks: TxDQ = 932
N0.C3.D0.R1.S14: RdPtrOffsetTxDq: 07
N6.C3.D0.R1.S16: Total Delay in PI ticks: TxDQ = 949
N0.C3.D0.R1.S15: RdPtrOffsetTxDq: 07
N6.C3.D0.R1.S17: Total Delay in PI ticks: TxDQ = 918
N0.C3.D0.R1.S16: RdPtrOffsetTxDq: 07
N6.C3.D1.R0.S00: wrcmd2dqsstartlatency: 04
N0.C3.D0.R1.S17: RdPtrOffsetTxDq: 07
N6.C3.D1.R0.S00: RdPtrOffsetTxDq: 06
N0.C3.D0.R1.S00: Total Delay in PI ticks: TxDQ = 987
N6.C3.D1.R0.S00: RdPtrOffsetTxDqs: 08
N0.C3.D0.R1.S01: Total Delay in PI ticks: TxDQ = 968
N6.C3.D1.R0.S00: PiTxDqs: 01
N0.C3.D0.R1.S02: Total Delay in PI ticks: TxDQ = 958
N6.C3.D1.R0.S01: wrcmd2dqsstartlatency: 04
N0.C3.D0.R1.S03: Total Delay in PI ticks: TxDQ = 943
N6.C3.D1.R0.S01: RdPtrOffsetTxDq: 06
N0.C3.D0.R1.S04: Total Delay in PI ticks: TxDQ = 909
N6.C3.D1.R0.S01: RdPtrOffsetTxDqs: 07
N0.C3.D0.R1.S05: Total Delay in PI ticks: TxDQ = 922
N6.C3.D1.R0.S01: PiTxDqs: 48
N0.C3.D0.R1.S06: Total Delay in PI ticks: TxDQ = 937
N6.C3.D1.R0.S02: wrcmd2dqsstartlatency: 04
N0.C3.D0.R1.S07: Total Delay in PI ticks: TxDQ = 954
N6.C3.D1.R0.S02: RdPtrOffsetTxDq: 06
N0.C3.D0.R1.S08: Total Delay in PI ticks: TxDQ = 925
N6.C3.D1.R0.S02: RdPtrOffsetTxDqs: 07
N0.C3.D0.R1.S09: Total Delay in PI ticks: TxDQ = 987
N6.C3.D1.R0.S02: PiTxDqs: 37
N0.C3.D0.R1.S10: Total Delay in PI ticks: TxDQ = 968
N6.C3.D1.R0.S03: wrcmd2dqsstartlatency: 04
N0.C3.D0.R1.S11: Total Delay in PI ticks: TxDQ = 959
N6.C3.D1.R0.S03: RdPtrOffsetTxDq: 05
N0.C3.D0.R1.S12: Total Delay in PI ticks: TxDQ = 947
N6.C3.D1.R0.S03: RdPtrOffsetTxDqs: 07
N0.C3.D0.R1.S13: Total Delay in PI ticks: TxDQ = 910
N6.C3.D1.R0.S03: PiTxDqs: 24
N0.C3.D0.R1.S14: Total Delay in PI ticks: TxDQ = 924
N6.C3.D1.R0.S04: wrcmd2dqsstartlatency: 04
N0.C3.D0.R1.S15: Total Delay in PI ticks: TxDQ = 935
N6.C3.D1.R0.S04: RdPtrOffsetTxDq: 05
N0.C3.D0.R1.S16: Total Delay in PI ticks: TxDQ = 954
START_DATA_RX_DQS_ADV
Results for N4.C0.D0.R0: 
           0   1   2   3   4   5   6   7   8   9  10  11  12  13  14  15  16  17
-------------------------------------------------------------------------------
Vref offset: 0
Left:    -22 -17 -21 -18 -20 -21 -20 -19 -14 -20 -19 -19 -21 -20 -24 -20 -19 -18
Right:    21  17  14  17  15  15  15  18  22  17  14  20  20  16  14  16  22  25
-------------------------------------------------------------------------------
Prev Pi:  36  36  38  37  37  37  38  38  37  38  36  37  37  36  37  36  36  36
New Pi:   36  36  35  37  35  34  36  38  41  37  34  37  37  34  32  34  37  39
Diff:      0   0  -3   0  -2  -3  -2   0   4  -1  -2   0   0  -2  -5  -2   1   3

Results for N4.C0.D0.R1: 
           0   1   2   3   4   5   6   7   8   9  10  11  12  13  14  15  16  17
-------------------------------------------------------------------------------
Vref offset: 0
Left:    -22 -16 -21 -18 -20 -22 -19 -20 -14 -20 -20 -19 -22 -19 -23 -21 -18 -18
Right:    18  20  15  19  13  13  13  21  24  17  18  20  22  16  12  17  22  25
-------------------------------------------------------------------------------
Prev Pi:  36  36  38  37  37  37  38  38  37  38  36  37  37  36  37  36  36  36
New Pi:   34  38  35  37  34  33  35  38  42  37  35  37  37  35  32  34  38  39
Diff:     -2   2  -3   0  -3  -4  -3   0   5  -1  -1   0   0  -1  -5  -2   2   3

Results for N4.C0.D1.R0: 
           0   1   2   3   4   5   6   7   8   9  10  11  12  13  14  15  16  17
-------------------------------------------------------------------------------
Vref offset: 0
Left:    -21 -15 -20 -16 -19 -21 -18 -16 -15 -18 -18 -18 -21 -20 -22 -17 -18 -15
Right:    17  15  13  17  12  12  15  19  22  12  16  17  17  16  12  16  19  23
-------------------------------------------------------------------------------
Prev Pi:  37  38  39  37  38  38  39  40  40  40  37  38  39  37  38  37  39  38
New Pi:   35  38  36  37  35  34  38  41  43  37  36  38  37  35  33  37  39  42
Diff:     -2   0  -3   0  -3  -4  -1   1   3  -3  -1   0  -2  -2  -5   0   0   4

Results for N4.C0.D1.R1: 
           0   1   2   3   4   5   6   7   8   9  10  11  12  13  14  15  16  17
-------------------------------------------------------------------------------
Vref offset: 0
Left:    -21 -15 -20 -17 -20 -20 -17 -16 -15 -19 -19 -17 -22 -20 -21 -15 -17 -16
Right:    16  15  13  19  13  13  12  15  20  12  15  20  17  14  12  16  18  26
-------------------------------------------------------------------------------
Prev Pi:  37  38  39  37  38  38  39  40  40  40  37  38  39  37  38  37  39  38
New Pi:   35  38  36  38  35  35  37  40  42  37  35  39  37  34  34  37  39  43
Diff:     -2   0  -3   1  -3  -3  -2   0   2  -3  -2   1  -2  -3  -4   0   0   5

Results for N4.C1.D0.R0: 
           0   1   2   3   4   5   6   7   8   9  10  11  12  13  14  15  16  17
-------------------------------------------------------------------------------
Vref offset: 0
Left:    -20 -21 -18 -18 -20 -21 -19 -21 -20 -19 -22 -19 -22 -19 -19 -19 -17 -13
Right:    14  23  16  14  14  16  19  19  17  16  18  19  15  16  14   9  24  16
-------------------------------------------------------------------------------
Prev Pi:  37  37  37  37  37  36  39  39  38  36  35  34  36  37  34  38  36  38
New Pi:   34  38  36  35  34  34  39  38  37  35  33  34  33  36  32  33  39  39
Diff:     -3   1  -1  -2  -3  -2   0  -1  -1  -1  -2   0  -3  -1  -2  -5   3   1

Results for N4.C1.D0.R1: 
           0   1   2   3   4   5   6   7   8   9  10  11  12  13  14  15  16  17
-------------------------------------------------------------------------------
Vref offset: 0
Left:    -20 -21 -18 -18 -20 -20 -20 -21 -20 -19 -22 -19 -21 -19 -20 -20 -17 -14
Right:    16  21  13  15  14  14  18  21  20  16  20  20  14  15  14  11  23  19
-------------------------------------------------------------------------------
Prev Pi:  37  37  37  37  37  36  39  39  38  36  35  34  36  37  34  38  36  38
New Pi:   35  37  35  36  34  33  38  39  38  35  34  34  33  35  31  34  39  40
Diff:     -2   0  -2  -1  -3  -3  -1   0   0  -1  -1   0  -3  -2  -3  -4   3   2

Results for N4.C1.D1.R0: 
           0   1   2   3   4   5   6   7   8   9  10  11  12  13  14  15  16  17
-------------------------------------------------------------------------------
Vref offset: 0
Left:    -19 -20 -15 -12 -17 -20 -17 -18 -15 -17 -19 -15 -20 -17 -15 -14 -13  -8
Right:    13  21  14  11  12  12  17  16  18  13  17  19  11  12  13  11  21  17
-------------------------------------------------------------------------------
Prev Pi:  39  39  39  39  40  39  41  41  40  38  38  36  39  40  36  40  38  40
New Pi:   36  39  39  39  38  35  41  40  41  36  37  38  35  38  35  39  42  44
Diff:     -3   0   0   0  -2  -4   0  -1   1  -2  -1   2  -4  -2  -1  -1   4   4

Results for N4.C1.D1.R1: 
           0   1   2   3   4   5   6   7   8   9  10  11  12  13  14  15  16  17
-------------------------------------------------------------------------------
Vref offset: 0
Left:    -19 -21 -17 -12 -17 -20 -17 -17 -15 -18 -19 -16 -19 -16 -14 -14 -12  -9
Right:    11  20  13  13  10  13  16  17  15  14  17  17  11  12  13   9  20  18
-------------------------------------------------------------------------------
Prev Pi:  39  39  39  39  40  39  41  41  40  38  38  36  39  40  36  40  38  40
New Pi:   35  39  37  39  37  36  41  41  40  36  37  36  35  38  36  38  42  44
Diff:     -4   0  -2   0  -3  -3   0   0   0  -2  -1   0  -4  -2   0  -2   4   4

Results for N4.C2.D0.R0: 
           0   1   2   3   4   5   6   7   8   9  10  11  12  13  14  15  16  17
-------------------------------------------------------------------------------
Vref offset: 0
Left:    -21 -20 -20 -21 -17 -15 -20 -20 -20 -17 -13 -16 -18 -17 -19 -21 -19 -18
Right:    21  24  14  25  16  22  15  20  21  19  16  22  25  19  20  19  25  25
-------------------------------------------------------------------------------
Prev Pi:  36  37  36  35  36  37  38  37  38  36  38  34  36  32  38  37  35  36
New Pi:   36  39  33  37  36  40  36  37  38  37  39  37  39  33  38  36  38  39
Diff:      0   2  -3   2   0   3  -2   0   0   1   1   3   3   1   0  -1   3   3

Results for N4.C2.D0.R1: 
           0   1   2   3   4   5   6   7   8   9  10  11  12  13  14  15  16  17
-------------------------------------------------------------------------------
Vref offset: 0
Left:    -20 -20 -20 -22 -18 -13 -20 -20 -21 -19 -14 -15 -19 -18 -18 -21 -19 -19
Right:    21  28  15  26  14  23  14  20  20  21  20  23  24  18  18  19  21  25
-------------------------------------------------------------------------------
Prev Pi:  36  37  36  35  36  37  38  37  38  36  38  34  36  32  38  37  35  36
New Pi:   36  41  34  37  34  42  35  37  38  37  41  38  38  32  38  36  36  39
Diff:      0   4  -2   2  -2   5  -3   0   0   1   3   4   2   0   0  -1   1   3

Results for N4.C2.D1.R0: 
           0   1   2   3   4   5   6   7   8   9  10  11  12  13  14  15  16  17
-------------------------------------------------------------------------------
Vref offset: 0
Left:    -19 -19 -18 -18 -14 -10 -15 -14 -18 -14 -12 -10 -14 -16 -16 -20 -15 -15
Right:    18  21  15  23  13  21  15  17  19  21  15  21  24  14  17  14  20  22
-------------------------------------------------------------------------------
Prev Pi:  37  39  37  36  37  38  40  39  39  37  41  36  37  36  40  39  37  37
New Pi:   37  40  36  38  37  43  40  40  39  40  42  41  42  35  40  36  39  40
Diff:      0   1  -1   2   0   5   0   1   0   3   1   5   5  -1   0  -3   2   3

Results for N4.C2.D1.R1: 
           0   1   2   3   4   5   6   7   8   9  10  11  12  13  14  15  16  17
-------------------------------------------------------------------------------
Vref offset: 0
Left:    -20 -19 -18 -18 -14  -9 -15 -15 -17 -14 -13 -12 -15 -17 -16 -19 -16 -16
Right:    18  23  13  25  14  22  11  19  19  20  13  21  24  14  16  16  19  23
-------------------------------------------------------------------------------
Prev Pi:  37  39  37  36  37  38  40  39  39  37  41  36  37  36  40  39  37  37
New Pi:   36  41  35  39  37  44  38  41  40  40  41  40  41  35  40  38  38  40
Diff:     -1   2  -2   3   0   6  -2   2   1   3   0   4   4  -1   0  -1   1   3

Results for N4.C3.D0.R0: 
           0   1   2   3   4   5   6   7   8   9  10  11  12  13  14  15  16  17
-------------------------------------------------------------------------------
Vref offset: 0
Left:    -19 -20 -16 -19 -19 -19 -20 -16 -19 -20 -22 -21 -22 -23 -18 -19 -22 -20
Right:    21  19  23  23  19  22  18  17  25  17  20  22  20  24  25  18  22  20
-------------------------------------------------------------------------------
Prev Pi:  37  39  36  36  39  37  39  37  35  37  36  36  37  36  37  37  36  37
New Pi:   38  39  39  38  39  38  38  37  38  36  35  36  36  36  40  37  36  37
Diff:      1   0   3   2   0   1  -1   0   3  -1  -1   0  -1   0   3   0   0   0

Results for N4.C3.D0.R1: 
           0   1   2   3   4   5   6   7   8   9  10  11  12  13  14  15  16  17
-------------------------------------------------------------------------------
Vref offset: 0
Left:    -19 -20 -17 -19 -20 -19 -20 -17 -17 -21 -23 -21 -21 -22 -17 -20 -20 -22
Right:    22  19  22  24  18  21  17  19  22  20  19  21  21  21  25  17  22  20
-------------------------------------------------------------------------------
Prev Pi:  37  39  36  36  39  37  39  37  35  37  36  36  37  36  37  37  36  37
New Pi:   38  39  38  38  38  38  38  38  37  37  34  36  37  36  41  36  37  36
Diff:      1   0   2   2  -1   1  -1   1   2   0  -2   0   0   0   4  -1   1  -1

Results for N4.C3.D1.R0: 
           0   1   2   3   4   5   6   7   8   9  10  11  12  13  14  15  16  17
-------------------------------------------------------------------------------
Vref offset: 0
Left:    -16 -17 -15 -16 -13 -15 -17 -11 -12 -18 -20 -19 -19 -19 -14 -17 -18 -19
Right:    18  16  21  19  15  17  14  16  21  17  19  19  18  20  25  12  20  17
-------------------------------------------------------------------------------
Prev Pi:  40  41  38  39  41  40  40  38  36  39  38  37  39  37  39  40  37  39
New Pi:   41  41  41  40  42  41  39  40  40  39  38  37  39  37  44  38  38  38
Diff:      1   0   3   1   1   1  -1   2   4   0   0   0   0   0   5  -2   1  -1

Results for N4.C3.D1.R1: 
           0   1   2   3   4   5   6   7   8   9  10  11  12  13  14  15  16  17
-------------------------------------------------------------------------------
Vref offset: 0
Left:    -16 -17 -15 -17 -14 -16 -16 -11 -11 -18 -20 -20 -19 -19 -13 -16 -18 -19
Right:    18  18  17  20  16  17  16  14  21  18  21  20  18  21  24  12  19  18
-------------------------------------------------------------------------------
Prev Pi:  40  41  38  39  41  40  40  38  36  39  38  37  39  37  39  40  37  39
New Pi:   41  41  39  40  42  40  40  39  41  39  38  37  39  38  44  38  37  39
Diff:      1   0   1   1   1   0   0   1   5   0   0   0   0   1   5  -2   0   0

STOP_DATA_RX_DQS_ADV
N6.C3.D1.R0.S04: RdPtrOffsetTxDqs: 06
N0.C3.D0.R1.S17: Total Delay in PI ticks: TxDQ = 925
START_DATA_TX_DQ_ADV
Results for N2.C0.D0.R0: 
           0   1   2   3   4   5   6   7   8   9  10  11  12  13  14  15  16  17
-------------------------------------------------------------------------------
Vref offset: 0
Left:    -24 -25 -22 -24 -25 -23 -24 -23 -24 -25 -26 -24 -25 -26 -22 -24 -24 -23
Right:    24  27  29  28  25  28  26  25  23  26  26  27  27  24  27  28  26  24
-------------------------------------------------------------------------------
Prev Pi: 466 445 432 415 382 400 406 419 398 463 445 434 417 385 401 404 419 395
New Pi:  466 446 435 417 382 402 407 420 398 463 445 435 418 384 403 406 420 395
Diff:      0   1   3   2   0   2   1   1   0   0   0   1   1  -1   2   2   1   0

Results for N2.C0.D0.R1: 
           0   1   2   3   4   5   6   7   8   9  10  11  12  13  14  15  16  17
-------------------------------------------------------------------------------
Vref offset: 0
Left:    -25 -24 -22 -22 -24 -23 -23 -24 -23 -24 -26 -24 -26 -25 -22 -25 -23 -26
Right:    26  25  28  28  24  28  25  25  23  25  25  27  27  24  27  28  25  27
-------------------------------------------------------------------------------
Prev Pi: 466 445 432 415 382 400 406 419 398 463 445 434 417 385 401 404 419 395
New Pi:  466 445 435 418 382 402 407 419 398 463 445 435 417 385 403 405 420 395
Diff:      0   0   3   3   0   2   1   0   0   0   0   1   0   0   2   1   1   0

Results for N2.C0.D1.R0: 
           0   1   2   3   4   5   6   7   8   9  10  11  12  13  14  15  16  17
-------------------------------------------------------------------------------
Vref offset: 0
Left:    -25 -26 -24 -24 -25 -24 -22 -20 -23 -23 -25 -22 -22 -26 -22 -22 -21 -23
Right:    24  23  25  25  21  23  22  24  24  22  23  25  23  22  23  25  26  25
-------------------------------------------------------------------------------
Prev Pi: 470 455 439 424 390 409 413 428 400 468 455 441 425 391 410 411 427 398
New Pi:  470 454 439 424 388 409 413 430 400 468 454 442 425 389 410 412 429 399
Diff:      0  -1   0   0  -2   0   0   2   0   0  -1   1   0  -2   0   1   2   1

Results for N2.C0.D1.R1: 
           0   1   2   3   4   5   6   7   8   9  10  11  12  13  14  15  16  17
-------------------------------------------------------------------------------
Vref offset: 0
Left:    -26 -23 -23 -21 -22 -22 -22 -21 -23 -26 -25 -24 -22 -27 -23 -22 -22 -23
Right:    25  22  24  24  21  22  22  23  22  22  24  25  25  23  25  26  25  26
-------------------------------------------------------------------------------
Prev Pi: 470 455 439 424 390 409 413 428 400 468 455 441 425 391 410 411 427 398
New Pi:  470 455 439 425 390 409 413 429 400 466 455 441 426 389 411 413 428 399
Diff:      0   0   0   1   0   0   0   1   0  -2   0   0   1  -2   1   2   1   1

Results for N2.C1.D0.R0: 
           0   1   2   3   4   5   6   7   8   9  10  11  12  13  14  15  16  17
-------------------------------------------------------------------------------
Vref offset: 0
Left:    -24 -23 -25 -24 -25 -22 -21 -20 -24 -24 -24 -25 -24 -26 -22 -21 -21 -24
Right:    24  26  24  26  24  26  24  26  26  23  26  24  26  25  25  25  26  27
-------------------------------------------------------------------------------
Prev Pi: 466 446 440 423 391 403 417 432 404 465 447 442 423 391 405 419 434 405
New Pi:  466 447 440 424 391 405 418 435 405 465 448 442 424 391 406 421 436 406
Diff:      0   1   0   1   0   2   1   3   1   0   1   0   1   0   1   2   2   1

Results for N2.C1.D0.R1: 
           0   1   2   3   4   5   6   7   8   9  10  11  12  13  14  15  16  17
-------------------------------------------------------------------------------
Vref offset: 0
Left:    -24 -22 -26 -24 -24 -21 -21 -21 -24 -25 -24 -26 -23 -26 -22 -22 -20 -24
Right:    24  26  23  25  24  27  24  25  25  23  24  24  26  25  26  25  25  28
-------------------------------------------------------------------------------
Prev Pi: 466 446 440 423 391 403 417 432 404 465 447 442 423 391 405 419 434 405
New Pi:  466 448 439 423 391 406 418 434 404 464 447 441 424 391 407 420 436 407
Diff:      0   2  -1   0   0   3   1   2   0  -1   0  -1   1   0   2   1   2   2

Results for N2.C1.D1.R0: 
           0   1   2   3   4   5   6   7   8   9  10  11  12  13  14  15  16  17
-------------------------------------------------------------------------------
Vref offset: 0
Left:    -21 -22 -23 -24 -23 -20 -21 -19 -22 -19 -22 -22 -23 -23 -20 -23 -18 -23
Right:    23  23  22  23  21  23  21  24  23  23  22  25  21  24  22  23  24  25
-------------------------------------------------------------------------------
Prev Pi: 471 452 445 429 397 410 424 441 406 469 452 447 431 397 412 423 441 408
New Pi:  472 452 445 429 396 411 424 443 406 471 452 448 430 397 413 423 444 409
Diff:      1   0   0   0  -1   1   0   2   0   2   0   1  -1   0   1   0   3   1

Results for N2.C1.D1.R1: 
           0   1   2   3   4   5   6   7   8   9  10  11  12  13  14  15  16  17
-------------------------------------------------------------------------------
Vref offset: 0
Left:    -22 -20 -22 -21 -21 -20 -20 -19 -22 -20 -22 -23 -22 -23 -20 -23 -18 -24
Right:    23  23  21  22  23  24  20  23  22  23  23  22  22  25  22  23  24  25
-------------------------------------------------------------------------------
Prev Pi: 471 452 445 429 397 410 424 441 406 469 452 447 431 397 412 423 441 408
New Pi:  471 453 445 429 398 412 424 443 406 470 452 447 431 398 413 423 444 408
Diff:      0   1   0   0   1   2   0   2   0   1   0   0   0   1   1   0   3   0

Results for N2.C2.D0.R0: 
           0   1   2   3   4   5   6   7   8   9  10  11  12  13  14  15  16  17
-------------------------------------------------------------------------------
Vref offset: 0
Left:    -25 -23 -24 -26 -25 -24 -24 -22 -26 -24 -25 -25 -25 -25 -24 -24 -22 -25
Right:    25  25  26  27  25  25  25  27  21  25  25  25  26  26  25  27  27  22
-------------------------------------------------------------------------------
Prev Pi: 464 447 438 419 381 407 405 426 399 462 447 439 420 381 407 405 428 399
New Pi:  464 448 439 419 381 407 405 428 397 462 447 439 420 381 407 406 430 398
Diff:      0   1   1   0   0   0   0   2  -2   0   0   0   0   0   0   1   2  -1

Results for N2.C2.D0.R1: 
           0   1   2   3   4   5   6   7   8   9  10  11  12  13  14  15  16  17
-------------------------------------------------------------------------------
Vref offset: 0
Left:    -26 -23 -23 -24 -24 -23 -23 -23 -26 -25 -25 -25 -25 -25 -24 -24 -22 -26
Right:    25  25  25  25  24  25  25  25  21  25  24  25  27  26  26  26  25  24
-------------------------------------------------------------------------------
Prev Pi: 464 447 438 419 381 407 405 426 399 462 447 439 420 381 407 405 428 399
New Pi:  464 448 439 419 381 408 406 427 397 462 447 439 421 381 408 406 429 398
Diff:      0   1   1   0   0   1   1   1  -2   0   0   0   1   0   1   1   1  -1

Results for N2.C2.D1.R0: 
           0   1   2   3   4   5   6   7   8   9  10  11  12  13  14  15  16  17
-------------------------------------------------------------------------------
Vref offset: 0
Left:    -24 -22 -24 -25 -24 -24 -22 -20 -24 -23 -24 -23 -24 -24 -24 -22 -21 -22
Right:    23  24  22  22  22  22  23  24  21  21  21  23  22  24  22  23  25  21
-------------------------------------------------------------------------------
Prev Pi: 466 451 440 427 384 414 408 432 397 462 452 441 425 385 413 409 432 397
New Pi:  466 452 439 426 383 413 408 434 396 461 451 441 424 385 412 409 434 397
Diff:      0   1  -1  -1  -1  -1   0   2  -1  -1  -1   0  -1   0  -1   0   2   0

Results for N2.C2.D1.R1: 
           0   1   2   3   4   5   6   7   8   9  10  11  12  13  14  15  16  17
-------------------------------------------------------------------------------
Vref offset: 0
Left:    -24 -21 -24 -23 -21 -23 -21 -21 -24 -24 -24 -24 -24 -24 -24 -23 -21 -25
Right:    23  24  20  21  24  22  23  23  20  23  21  23  22  26  21  24  23  23
-------------------------------------------------------------------------------
Prev Pi: 466 451 440 427 384 414 408 432 397 462 452 441 425 385 413 409 432 397
New Pi:  466 452 438 426 385 414 409 433 395 462 451 441 424 386 412 409 433 396
Diff:      0   1  -2  -1   1   0   1   1  -2   0  -1   0  -1   1  -1   0   1  -1

Results for N2.C3.D0.R0: 
           0   1   2   3   4   5   6   7   8   9  10  11  12  13  14  15  16  17
-------------------------------------------------------------------------------
Vref offset: 0
Left:    -23 -23 -26 -23 -25 -21 -22 -21 -24 -21 -22 -23 -23 -25 -22 -22 -22 -24
Right:    27  27  25  26  25  26  23  26  25  25  27  26  26  26  26  25  26  26
-------------------------------------------------------------------------------
Prev Pi: 466 451 440 424 391 404 420 434 409 466 453 442 426 391 406 420 436 408
New Pi:  468 453 440 425 391 406 420 436 409 468 455 443 427 391 408 421 438 409
Diff:      2   2   0   1   0   2   0   2   0   2   2   1   1   0   2   1   2   1

Results for N2.C3.D0.R1: 
           0   1   2   3   4   5   6   7   8   9  10  11  12  13  14  15  16  17
-------------------------------------------------------------------------------
Vref offset: 0
Left:    -23 -21 -24 -23 -24 -21 -21 -22 -24 -23 -23 -24 -24 -25 -22 -22 -22 -25
Right:    25  27  24  27  25  28  23  26  23  26  25  25  27  26  27  25  25  27
-------------------------------------------------------------------------------
Prev Pi: 466 451 440 424 391 404 420 434 409 466 453 442 426 391 406 420 436 408
New Pi:  467 454 440 426 391 407 421 436 409 467 454 442 427 391 408 421 437 409
Diff:      1   3   0   2   0   3   1   2   0   1   1   0   1   0   2   1   1   1

Results for N2.C3.D1.R0: 
           0   1   2   3   4   5   6   7   8   9  10  11  12  13  14  15  16  17
-------------------------------------------------------------------------------
Vref offset: 0
Left:    -23 -21 -23 -23 -23 -20 -22 -18 -21 -22 -21 -21 -22 -22 -19 -22 -18 -23
Right:    23  25  22  22  24  23  21  23  22  22  23  25  23  22  23  24  24  25
-------------------------------------------------------------------------------
Prev Pi: 474 458 445 432 397 412 424 442 412 471 458 446 431 397 411 424 442 411
New Pi:  474 460 445 432 397 413 424 444 412 471 459 448 431 397 413 425 445 412
Diff:      0   2   0   0   0   1   0   2   0   0   1   2   0   0   2   1   3   1

Results for N2.C3.D1.R1: 
           0   1   2   3   4   5   6   7   8   9  10  11  12  13  14  15  16  17
-------------------------------------------------------------------------------
Vref offset: 0
Left:    -23 -19 -21 -22 -21 -19 -21 -20 -21 -21 -21 -23 -22 -22 -20 -22 -19 -23
Right:    23  24  21  24  23  23  21  23  21  23  24  24  25  24  23  24  24  26
-------------------------------------------------------------------------------
Prev Pi: 474 458 445 432 397 412 424 442 412 471 458 446 431 397 411 424 442 411
New Pi:  474 460 445 433 398 414 424 443 412 472 459 446 432 398 412 425 444 412
Diff:      0   2   0   1   1   2   0   1   0   1   1   0   1   1   1   1   2   1

STOP_DATA_TX_DQ_ADV
N4: RunTrainStep: Final status = 0
N6.C3.D1.R0.S04: PiTxDqs: 52
N0.C3.D1.R0.S00: wrcmd2dqsstartlatency: 04
N2: RunTrainStep: Final status = 0

END - Rd Timing Centering 2D Training  Time         5027 ms
N6.C3.D1.R0.S05: wrcmd2dqsstartlatency: 04
N0.C3.D1.R0.S00: RdPtrOffsetTxDq: 06

END - Wr Timing Centering 2D Training  Time         6656 ms

START - Wr Timing Centering 2D Training
N6.C3.D1.R0.S05: RdPtrOffsetTxDq: 05
N0.C3.D1.R0.S00: RdPtrOffsetTxDqs: 08

START - Rd Voltage Training
N4: 

Adv Strobe Centering(MARGIN_TX_DQ): GetMultiVref: patternLength = 13, stepSize = 1, numPoints = 1
N6.C3.D1.R0.S05: RdPtrOffsetTxDqs: 07
N0.C3.D1.R0.S00: PiTxDqs: 06
N2: RX Vref Training...
N6.C3.D1.R0.S05: PiTxDqs: 00
N0.C3.D1.R0.S01: wrcmd2dqsstartlatency: 04
N2: GetMargins: Level = 1, group = 13, mode = 2, scope = 4
N4: GetMargins: Level = 1, group = 12, mode = 0, scope = 4
N6.C3.D1.R0.S06: wrcmd2dqsstartlatency: 04
N0.C3.D1.R0.S01: RdPtrOffsetTxDq: 06
N6.C3.D1.R0.S06: RdPtrOffsetTxDq: 05
N0.C3.D1.R0.S01: RdPtrOffsetTxDqs: 07
N6.C3.D1.R0.S06: RdPtrOffsetTxDqs: 07
N0.C3.D1.R0.S01: PiTxDqs: 51
N6.C3.D1.R0.S06: PiTxDqs: 16
N0.C3.D1.R0.S02: wrcmd2dqsstartlatency: 04
N6.C3.D1.R0.S07: wrcmd2dqsstartlatency: 04
N0.C3.D1.R0.S02: RdPtrOffsetTxDq: 06
N6.C3.D1.R0.S07: RdPtrOffsetTxDq: 05
N0.C3.D1.R0.S02: RdPtrOffsetTxDqs: 07
N6.C3.D1.R0.S07: RdPtrOffsetTxDqs: 07
N0.C3.D1.R0.S02: PiTxDqs: 43
N6.C3.D1.R0.S07: PiTxDqs: 34
N0.C3.D1.R0.S03: wrcmd2dqsstartlatency: 04
N6.C3.D1.R0.S08: wrcmd2dqsstartlatency: 04
N0.C3.D1.R0.S03: RdPtrOffsetTxDq: 05
N6.C3.D1.R0.S08: RdPtrOffsetTxDq: 05
N0.C3.D1.R0.S03: RdPtrOffsetTxDqs: 07
N6.C3.D1.R0.S08: RdPtrOffsetTxDqs: 07
N0.C3.D1.R0.S03: PiTxDqs: 24
N6.C3.D1.R0.S08: PiTxDqs: 03
N0.C3.D1.R0.S04: wrcmd2dqsstartlatency: 04
N6.C3.D1.R0.S09: wrcmd2dqsstartlatency: 04
N0.C3.D1.R0.S04: RdPtrOffsetTxDq: 05
N6.C3.D1.R0.S09: RdPtrOffsetTxDq: 06
N0.C3.D1.R0.S04: RdPtrOffsetTxDqs: 06
N6.C3.D1.R0.S09: RdPtrOffsetTxDqs: 08
N0.C3.D1.R0.S04: PiTxDqs: 54
N6.C3.D1.R0.S09: PiTxDqs: 00
N0.C3.D1.R0.S05: wrcmd2dqsstartlatency: 04
N6.C3.D1.R0.S10: wrcmd2dqsstartlatency: 04
N0.C3.D1.R0.S05: RdPtrOffsetTxDq: 05
N6.C3.D1.R0.S10: RdPtrOffsetTxDq: 06
N0.C3.D1.R0.S05: RdPtrOffsetTxDqs: 07
N6.C3.D1.R0.S10: RdPtrOffsetTxDqs: 07
N0.C3.D1.R0.S05: PiTxDqs: 04
N6.C3.D1.R0.S10: PiTxDqs: 48
N0.C3.D1.R0.S06: wrcmd2dqsstartlatency: 04
N6.C3.D1.R0.S11: wrcmd2dqsstartlatency: 04
N0.C3.D1.R0.S06: RdPtrOffsetTxDq: 05
N6.C3.D1.R0.S11: RdPtrOffsetTxDq: 06
N0.C3.D1.R0.S06: RdPtrOffsetTxDqs: 07
N6.C3.D1.R0.S11: RdPtrOffsetTxDqs: 07
N0.C3.D1.R0.S06: PiTxDqs: 18
N6.C3.D1.R0.S11: PiTxDqs: 37
N0.C3.D1.R0.S07: wrcmd2dqsstartlatency: 04
N6.C3.D1.R0.S12: wrcmd2dqsstartlatency: 04
N0.C3.D1.R0.S07: RdPtrOffsetTxDq: 06
N6.C3.D1.R0.S12: RdPtrOffsetTxDq: 05
N0.C3.D1.R0.S07: RdPtrOffsetTxDqs: 07
N6.C3.D1.R0.S12: RdPtrOffsetTxDqs: 07
N0.C3.D1.R0.S07: PiTxDqs: 35
N6.C3.D1.R0.S12: PiTxDqs: 24
N0.C3.D1.R0.S08: wrcmd2dqsstartlatency: 04
N6.C3.D1.R0.S13: wrcmd2dqsstartlatency: 04
N0.C3.D1.R0.S08: RdPtrOffsetTxDq: 05
N6.C3.D1.R0.S13: RdPtrOffsetTxDq: 05
N0.C3.D1.R0.S08: RdPtrOffsetTxDqs: 07
N6.C3.D1.R0.S13: RdPtrOffsetTxDqs: 06
N0.C3.D1.R0.S08: PiTxDqs: 04
N6.C3.D1.R0.S13: PiTxDqs: 51
N0.C3.D1.R0.S09: wrcmd2dqsstartlatency: 04
N6.C3.D1.R0.S14: wrcmd2dqsstartlatency: 04
N0.C3.D1.R0.S09: RdPtrOffsetTxDq: 06
N6.C3.D1.R0.S14: RdPtrOffsetTxDq: 05
N0.C3.D1.R0.S09: RdPtrOffsetTxDqs: 08
N6.C3.D1.R0.S14: RdPtrOffsetTxDqs: 07
N0.C3.D1.R0.S09: PiTxDqs: 06
N6.C3.D1.R0.S14: PiTxDqs: 01
N0.C3.D1.R0.S10: wrcmd2dqsstartlatency: 04
N6.C3.D1.R0.S15: wrcmd2dqsstartlatency: 04
N0.C3.D1.R0.S10: RdPtrOffsetTxDq: 06
N6.C3.D1.R0.S15: RdPtrOffsetTxDq: 05
N0.C3.D1.R0.S10: RdPtrOffsetTxDqs: 07
N6.C3.D1.R0.S15: RdPtrOffsetTxDqs: 07
N0.C3.D1.R0.S10: PiTxDqs: 53
N6.C3.D1.R0.S15: PiTxDqs: 15
N0.C3.D1.R0.S11: wrcmd2dqsstartlatency: 04
N6.C3.D1.R0.S16: wrcmd2dqsstartlatency: 04
N0.C3.D1.R0.S11: RdPtrOffsetTxDq: 06
N6.C3.D1.R0.S16: RdPtrOffsetTxDq: 06
N0.C3.D1.R0.S11: RdPtrOffsetTxDqs: 07
N6.C3.D1.R0.S16: RdPtrOffsetTxDqs: 07
N0.C3.D1.R0.S11: PiTxDqs: 43
N6.C3.D1.R0.S16: PiTxDqs: 34
N0.C3.D1.R0.S12: wrcmd2dqsstartlatency: 04
N6.C3.D1.R0.S17: wrcmd2dqsstartlatency: 04
N0.C3.D1.R0.S12: RdPtrOffsetTxDq: 05
N6.C3.D1.R0.S17: RdPtrOffsetTxDq: 05
N0.C3.D1.R0.S12: RdPtrOffsetTxDqs: 07
N6.C3.D1.R0.S17: RdPtrOffsetTxDqs: 07
N0.C3.D1.R0.S12: PiTxDqs: 25
N6.C3.D1.R0.S17: PiTxDqs: 03
N0.C3.D1.R0.S13: wrcmd2dqsstartlatency: 04
N6.C3.D1.R0.S00: RdPtrOffsetTxDq: 07
N0.C3.D1.R0.S13: RdPtrOffsetTxDq: 05
N6.C3.D1.R0.S01: RdPtrOffsetTxDq: 07
N0.C3.D1.R0.S13: RdPtrOffsetTxDqs: 06
N6.C3.D1.R0.S02: RdPtrOffsetTxDq: 07
N0.C3.D1.R0.S13: PiTxDqs: 56
N6.C3.D1.R0.S03: RdPtrOffsetTxDq: 06
N0.C3.D1.R0.S14: wrcmd2dqsstartlatency: 04
N6.C3.D1.R0.S04: RdPtrOffsetTxDq: 06
N0.C3.D1.R0.S14: RdPtrOffsetTxDq: 05
N6.C3.D1.R0.S05: RdPtrOffsetTxDq: 06
N0.C3.D1.R0.S14: RdPtrOffsetTxDqs: 07
N6.C3.D1.R0.S06: RdPtrOffsetTxDq: 06
N0.C3.D1.R0.S14: PiTxDqs: 05
N6.C3.D1.R0.S07: RdPtrOffsetTxDq: 06
N0.C3.D1.R0.S15: wrcmd2dqsstartlatency: 04
N6.C3.D1.R0.S08: RdPtrOffsetTxDq: 06
N0.C3.D1.R0.S15: RdPtrOffsetTxDq: 05
N6.C3.D1.R0.S09: RdPtrOffsetTxDq: 07
N0.C3.D1.R0.S15: RdPtrOffsetTxDqs: 07
N6.C3.D1.R0.S10: RdPtrOffsetTxDq: 07
N0.C3.D1.R0.S15: PiTxDqs: 21
N6.C3.D1.R0.S11: RdPtrOffsetTxDq: 07
N0.C3.D1.R0.S16: wrcmd2dqsstartlatency: 04
N6.C3.D1.R0.S12: RdPtrOffsetTxDq: 06
N0.C3.D1.R0.S16: RdPtrOffsetTxDq: 05
N6.C3.D1.R0.S13: RdPtrOffsetTxDq: 06
N0.C3.D1.R0.S16: RdPtrOffsetTxDqs: 07
N6.C3.D1.R0.S14: RdPtrOffsetTxDq: 06
N0.C3.D1.R0.S16: PiTxDqs: 33
N6.C3.D1.R0.S15: RdPtrOffsetTxDq: 06
N0.C3.D1.R0.S17: wrcmd2dqsstartlatency: 04
N6.C3.D1.R0.S16: RdPtrOffsetTxDq: 07
N0.C3.D1.R0.S17: RdPtrOffsetTxDq: 05
N6.C3.D1.R0.S17: RdPtrOffsetTxDq: 06
N0.C3.D1.R0.S17: RdPtrOffsetTxDqs: 07
N6.C3.D1.R0.S00: RdPtrOffsetTxDq: 08
N0.C3.D1.R0.S17: PiTxDqs: 03
N6.C3.D1.R0.S01: RdPtrOffsetTxDq: 08
N0.C3.D1.R0.S00: RdPtrOffsetTxDq: 07
N6.C3.D1.R0.S02: RdPtrOffsetTxDq: 08
N0.C3.D1.R0.S01: RdPtrOffsetTxDq: 07
N6.C3.D1.R0.S03: RdPtrOffsetTxDq: 07
N0.C3.D1.R0.S02: RdPtrOffsetTxDq: 07
N6.C3.D1.R0.S04: RdPtrOffsetTxDq: 07
N0.C3.D1.R0.S03: RdPtrOffsetTxDq: 06
N6.C3.D1.R0.S05: RdPtrOffsetTxDq: 07
N0.C3.D1.R0.S04: RdPtrOffsetTxDq: 06
N6.C3.D1.R0.S06: RdPtrOffsetTxDq: 07
N0.C3.D1.R0.S05: RdPtrOffsetTxDq: 06
N6.C3.D1.R0.S07: RdPtrOffsetTxDq: 07
N0.C3.D1.R0.S06: RdPtrOffsetTxDq: 06
N6.C3.D1.R0.S08: RdPtrOffsetTxDq: 07
N0.C3.D1.R0.S07: RdPtrOffsetTxDq: 07
N6.C3.D1.R0.S09: RdPtrOffsetTxDq: 08
N0.C3.D1.R0.S08: RdPtrOffsetTxDq: 06
N6.C3.D1.R0.S10: RdPtrOffsetTxDq: 08
N0.C3.D1.R0.S09: RdPtrOffsetTxDq: 07
N6.C3.D1.R0.S11: RdPtrOffsetTxDq: 08
N0.C3.D1.R0.S10: RdPtrOffsetTxDq: 07
N6.C3.D1.R0.S12: RdPtrOffsetTxDq: 07
N0.C3.D1.R0.S11: RdPtrOffsetTxDq: 07
N6.C3.D1.R0.S13: RdPtrOffsetTxDq: 07
N0.C3.D1.R0.S12: RdPtrOffsetTxDq: 06
N6.C3.D1.R0.S14: RdPtrOffsetTxDq: 07
N0.C3.D1.R0.S13: RdPtrOffsetTxDq: 06
N6.C3.D1.R0.S15: RdPtrOffsetTxDq: 07
N0.C3.D1.R0.S14: RdPtrOffsetTxDq: 06
N6.C3.D1.R0.S16: RdPtrOffsetTxDq: 08
N0.C3.D1.R0.S15: RdPtrOffsetTxDq: 06
N6.C3.D1.R0.S17: RdPtrOffsetTxDq: 07
N0.C3.D1.R0.S16: RdPtrOffsetTxDq: 06
N6.C3.D1.R0.S00: Total Delay in PI ticks: TxDQ = 992
N0.C3.D1.R0.S17: RdPtrOffsetTxDq: 06
N6.C3.D1.R0.S01: Total Delay in PI ticks: TxDQ = 975
N0.C3.D1.R0.S00: RdPtrOffsetTxDq: 08
N6.C3.D1.R0.S02: Total Delay in PI ticks: TxDQ = 965
N0.C3.D1.R0.S01: RdPtrOffsetTxDq: 08
N6.C3.D1.R0.S03: Total Delay in PI ticks: TxDQ = 950
N0.C3.D1.R0.S02: RdPtrOffsetTxDq: 08
N6.C3.D1.R0.S04: Total Delay in PI ticks: TxDQ = 914
N0.C3.D1.R0.S03: RdPtrOffsetTxDq: 07
N6.C3.D1.R0.S05: Total Delay in PI ticks: TxDQ = 927
N0.C3.D1.R0.S04: RdPtrOffsetTxDq: 07
N6.C3.D1.R0.S06: Total Delay in PI ticks: TxDQ = 943
N0.C3.D1.R0.S05: RdPtrOffsetTxDq: 07
N6.C3.D1.R0.S07: Total Delay in PI ticks: TxDQ = 959
N0.C3.D1.R0.S06: RdPtrOffsetTxDq: 07
N6.C3.D1.R0.S08: Total Delay in PI ticks: TxDQ = 930
N0.C3.D1.R0.S07: RdPtrOffsetTxDq: 08
N6.C3.D1.R0.S09: Total Delay in PI ticks: TxDQ = 989
N0.C3.D1.R0.S08: RdPtrOffsetTxDq: 07
N6.C3.D1.R0.S10: Total Delay in PI ticks: TxDQ = 975
N0.C3.D1.R0.S09: RdPtrOffsetTxDq: 08
N6.C3.D1.R0.S11: Total Delay in PI ticks: TxDQ = 965
N0.C3.D1.R0.S10: RdPtrOffsetTxDq: 08
N6.C3.D1.R0.S12: Total Delay in PI ticks: TxDQ = 950
N0.C3.D1.R0.S11: RdPtrOffsetTxDq: 08
N6.C3.D1.R0.S13: Total Delay in PI ticks: TxDQ = 914
N0.C3.D1.R0.S12: RdPtrOffsetTxDq: 07
N6.C3.D1.R0.S14: Total Delay in PI ticks: TxDQ = 930
N0.C3.D1.R0.S13: RdPtrOffsetTxDq: 07
N6.C3.D1.R0.S15: Total Delay in PI ticks: TxDQ = 942
N0.C3.D1.R0.S14: RdPtrOffsetTxDq: 07
N6.C3.D1.R0.S16: Total Delay in PI ticks: TxDQ = 962
N0.C3.D1.R0.S15: RdPtrOffsetTxDq: 07
N6.C3.D1.R0.S17: Total Delay in PI ticks: TxDQ = 929
N0.C3.D1.R0.S16: RdPtrOffsetTxDq: 07
N6.C3.D1.R1.S00: wrcmd2dqsstartlatency: 04
N0.C3.D1.R0.S17: RdPtrOffsetTxDq: 07
N6.C3.D1.R1.S00: RdPtrOffsetTxDq: 06
N0.C3.D1.R0.S00: Total Delay in PI ticks: TxDQ = 994
N6.C3.D1.R1.S00: RdPtrOffsetTxDqs: 07
N0.C3.D1.R0.S01: Total Delay in PI ticks: TxDQ = 976
N6.C3.D1.R1.S00: PiTxDqs: 60
N0.C3.D1.R0.S02: Total Delay in PI ticks: TxDQ = 968
N6.C3.D1.R1.S01: wrcmd2dqsstartlatency: 04
N0.C3.D1.R0.S03: Total Delay in PI ticks: TxDQ = 949
N6.C3.D1.R1.S01: RdPtrOffsetTxDq: 06
N0.C3.D1.R0.S04: Total Delay in PI ticks: TxDQ = 915
N6.C3.D1.R1.S01: RdPtrOffsetTxDqs: 07
N0.C3.D1.R0.S05: Total Delay in PI ticks: TxDQ = 930
N6.C3.D1.R1.S01: PiTxDqs: 43
N0.C3.D1.R0.S06: Total Delay in PI ticks: TxDQ = 942
N6.C3.D1.R1.S02: wrcmd2dqsstartlatency: 04
N0.C3.D1.R0.S07: Total Delay in PI ticks: TxDQ = 961
N6.C3.D1.R1.S02: RdPtrOffsetTxDq: 05
N0.C3.D1.R0.S08: Total Delay in PI ticks: TxDQ = 930
N6.C3.D1.R1.S02: RdPtrOffsetTxDqs: 07
N0.C3.D1.R0.S09: Total Delay in PI ticks: TxDQ = 994
N6.C3.D1.R1.S02: PiTxDqs: 32
N0.C3.D1.R0.S10: Total Delay in PI ticks: TxDQ = 978
N6.C3.D1.R1.S03: wrcmd2dqsstartlatency: 04
N0.C3.D1.R0.S11: Total Delay in PI ticks: TxDQ = 967
N6.C3.D1.R1.S03: RdPtrOffsetTxDq: 05
N0.C3.D1.R0.S12: Total Delay in PI ticks: TxDQ = 949
N6.C3.D1.R1.S03: RdPtrOffsetTxDqs: 07
N0.C3.D1.R0.S13: Total Delay in PI ticks: TxDQ = 917
N6.C3.D1.R1.S03: PiTxDqs: 20
N0.C3.D1.R0.S14: Total Delay in PI ticks: TxDQ = 931
N6.C3.D1.R1.S04: wrcmd2dqsstartlatency: 04
N0.C3.D1.R0.S15: Total Delay in PI ticks: TxDQ = 944
N6.C3.D1.R1.S04: RdPtrOffsetTxDq: 05
N0.C3.D1.R0.S16: Total Delay in PI ticks: TxDQ = 959
N6.C3.D1.R1.S04: RdPtrOffsetTxDqs: 06
N0.C3.D1.R0.S17: Total Delay in PI ticks: TxDQ = 929
N6.C3.D1.R1.S04: PiTxDqs: 48
N0.C3.D1.R1.S00: wrcmd2dqsstartlatency: 04
N6.C3.D1.R1.S05: wrcmd2dqsstartlatency: 04
N0.C3.D1.R1.S00: RdPtrOffsetTxDq: 06
N6.C3.D1.R1.S05: RdPtrOffsetTxDq: 05
N0.C3.D1.R1.S00: RdPtrOffsetTxDqs: 08
N6.C3.D1.R1.S05: RdPtrOffsetTxDqs: 06
N0.C3.D1.R1.S00: PiTxDqs: 04
N6.C3.D1.R1.S05: PiTxDqs: 60
N0.C3.D1.R1.S01: wrcmd2dqsstartlatency: 04
N6.C3.D1.R1.S06: wrcmd2dqsstartlatency: 04
N0.C3.D1.R1.S01: RdPtrOffsetTxDq: 06
N6.C3.D1.R1.S06: RdPtrOffsetTxDq: 05
N0.C3.D1.R1.S01: RdPtrOffsetTxDqs: 07
N6.C3.D1.R1.S06: RdPtrOffsetTxDqs: 07
N0.C3.D1.R1.S01: PiTxDqs: 49
N6.C3.D1.R1.S06: PiTxDqs: 10
N0.C3.D1.R1.S02: wrcmd2dqsstartlatency: 04
N6.C3.D1.R1.S07: wrcmd2dqsstartlatency: 04
N0.C3.D1.R1.S02: RdPtrOffsetTxDq: 06
N6.C3.D1.R1.S07: RdPtrOffsetTxDq: 05
N0.C3.D1.R1.S02: RdPtrOffsetTxDqs: 07
N6.C3.D1.R1.S07: RdPtrOffsetTxDqs: 07
N0.C3.D1.R1.S02: PiTxDqs: 39
N6.C3.D1.R1.S07: PiTxDqs: 29
N0.C3.D1.R1.S03: wrcmd2dqsstartlatency: 04
N6.C3.D1.R1.S08: wrcmd2dqsstartlatency: 04
N0.C3.D1.R1.S03: RdPtrOffsetTxDq: 05
N6.C3.D1.R1.S08: RdPtrOffsetTxDq: 05
N0.C3.D1.R1.S03: RdPtrOffsetTxDqs: 07
N6.C3.D1.R1.S08: RdPtrOffsetTxDqs: 06
N0.C3.D1.R1.S03: PiTxDqs: 24
N6.C3.D1.R1.S08: PiTxDqs: 60
N0.C3.D1.R1.S04: wrcmd2dqsstartlatency: 04
N6.C3.D1.R1.S09: wrcmd2dqsstartlatency: 04
N0.C3.D1.R1.S04: RdPtrOffsetTxDq: 05
N6.C3.D1.R1.S09: RdPtrOffsetTxDq: 06
N0.C3.D1.R1.S04: RdPtrOffsetTxDqs: 06
N6.C3.D1.R1.S09: RdPtrOffsetTxDqs: 07
N0.C3.D1.R1.S04: PiTxDqs: 52
N6.C3.D1.R1.S09: PiTxDqs: 59
N0.C3.D1.R1.S05: wrcmd2dqsstartlatency: 04
N6.C3.D1.R1.S10: wrcmd2dqsstartlatency: 04
N0.C3.D1.R1.S05: RdPtrOffsetTxDq: 05
N6.C3.D1.R1.S10: RdPtrOffsetTxDq: 06
N0.C3.D1.R1.S05: RdPtrOffsetTxDqs: 07
N6.C3.D1.R1.S10: RdPtrOffsetTxDqs: 07
N0.C3.D1.R1.S05: PiTxDqs: 01
N6.C3.D1.R1.S10: PiTxDqs: 43
N0.C3.D1.R1.S06: wrcmd2dqsstartlatency: 04
N6.C3.D1.R1.S11: wrcmd2dqsstartlatency: 04
N0.C3.D1.R1.S06: RdPtrOffsetTxDq: 05
N6.C3.D1.R1.S11: RdPtrOffsetTxDq: 06
N0.C3.D1.R1.S06: RdPtrOffsetTxDqs: 07
N6.C3.D1.R1.S11: RdPtrOffsetTxDqs: 07
N0.C3.D1.R1.S06: PiTxDqs: 16
N6.C3.D1.R1.S11: PiTxDqs: 35
N0.C3.D1.R1.S07: wrcmd2dqsstartlatency: 04
N6.C3.D1.R1.S12: wrcmd2dqsstartlatency: 04
N0.C3.D1.R1.S07: RdPtrOffsetTxDq: 05
N6.C3.D1.R1.S12: RdPtrOffsetTxDq: 05
N0.C3.D1.R1.S07: RdPtrOffsetTxDqs: 07
N6.C3.D1.R1.S12: RdPtrOffsetTxDqs: 07
N0.C3.D1.R1.S07: PiTxDqs: 34
N6.C3.D1.R1.S12: PiTxDqs: 20
N0.C3.D1.R1.S08: wrcmd2dqsstartlatency: 04
N6.C3.D1.R1.S13: wrcmd2dqsstartlatency: 04
N0.C3.D1.R1.S08: RdPtrOffsetTxDq: 05
N6.C3.D1.R1.S13: RdPtrOffsetTxDq: 05
N0.C3.D1.R1.S08: RdPtrOffsetTxDqs: 07
N6.C3.D1.R1.S13: RdPtrOffsetTxDqs: 06
N0.C3.D1.R1.S08: PiTxDqs: 01
N6.C3.D1.R1.S13: PiTxDqs: 47
N0.C3.D1.R1.S09: wrcmd2dqsstartlatency: 04
N6.C3.D1.R1.S14: wrcmd2dqsstartlatency: 04
N0.C3.D1.R1.S09: RdPtrOffsetTxDq: 06
N6.C3.D1.R1.S14: RdPtrOffsetTxDq: 05
N0.C3.D1.R1.S09: RdPtrOffsetTxDqs: 08
N6.C3.D1.R1.S14: RdPtrOffsetTxDqs: 06
N0.C3.D1.R1.S09: PiTxDqs: 03
N6.C3.D1.R1.S14: PiTxDqs: 60
N0.C3.D1.R1.S10: wrcmd2dqsstartlatency: 04
N6.C3.D1.R1.S15: wrcmd2dqsstartlatency: 04
N0.C3.D1.R1.S10: RdPtrOffsetTxDq: 06
N6.C3.D1.R1.S15: RdPtrOffsetTxDq: 05
N0.C3.D1.R1.S10: RdPtrOffsetTxDqs: 07
N6.C3.D1.R1.S15: RdPtrOffsetTxDqs: 07
N0.C3.D1.R1.S10: PiTxDqs: 50
N6.C3.D1.R1.S15: PiTxDqs: 09
N0.C3.D1.R1.S11: wrcmd2dqsstartlatency: 04
N6.C3.D1.R1.S16: wrcmd2dqsstartlatency: 04
N0.C3.D1.R1.S11: RdPtrOffsetTxDq: 06
N6.C3.D1.R1.S16: RdPtrOffsetTxDq: 05
N0.C3.D1.R1.S11: RdPtrOffsetTxDqs: 07
N6.C3.D1.R1.S16: RdPtrOffsetTxDqs: 07
N0.C3.D1.R1.S11: PiTxDqs: 39
N6.C3.D1.R1.S16: PiTxDqs: 28
N0.C3.D1.R1.S12: wrcmd2dqsstartlatency: 04
N6.C3.D1.R1.S17: wrcmd2dqsstartlatency: 04
N0.C3.D1.R1.S12: RdPtrOffsetTxDq: 05
N6.C3.D1.R1.S17: RdPtrOffsetTxDq: 05
N0.C3.D1.R1.S12: RdPtrOffsetTxDqs: 07
N6.C3.D1.R1.S17: RdPtrOffsetTxDqs: 06
N0.C3.D1.R1.S12: PiTxDqs: 26
N6.C3.D1.R1.S17: PiTxDqs: 60
N0.C3.D1.R1.S13: wrcmd2dqsstartlatency: 04
N6.C3.D1.R1.S00: RdPtrOffsetTxDq: 07
N0.C3.D1.R1.S13: RdPtrOffsetTxDq: 05
N6.C3.D1.R1.S01: RdPtrOffsetTxDq: 07
N0.C3.D1.R1.S13: RdPtrOffsetTxDqs: 06
N6.C3.D1.R1.S02: RdPtrOffsetTxDq: 06
N0.C3.D1.R1.S13: PiTxDqs: 55
N6.C3.D1.R1.S03: RdPtrOffsetTxDq: 06
N0.C3.D1.R1.S14: wrcmd2dqsstartlatency: 04
N6.C3.D1.R1.S04: RdPtrOffsetTxDq: 06
N0.C3.D1.R1.S14: RdPtrOffsetTxDq: 05
N6.C3.D1.R1.S05: RdPtrOffsetTxDq: 06
N0.C3.D1.R1.S14: RdPtrOffsetTxDqs: 07
N6.C3.D1.R1.S06: RdPtrOffsetTxDq: 06
N0.C3.D1.R1.S14: PiTxDqs: 03
N6.C3.D1.R1.S07: RdPtrOffsetTxDq: 06
N0.C3.D1.R1.S15: wrcmd2dqsstartlatency: 04
N6.C3.D1.R1.S08: RdPtrOffsetTxDq: 06
N0.C3.D1.R1.S15: RdPtrOffsetTxDq: 05
N6.C3.D1.R1.S09: RdPtrOffsetTxDq: 07
N0.C3.D1.R1.S15: RdPtrOffsetTxDqs: 07
N6.C3.D1.R1.S10: RdPtrOffsetTxDq: 07
N0.C3.D1.R1.S15: PiTxDqs: 16
N6.C3.D1.R1.S11: RdPtrOffsetTxDq: 07
N0.C3.D1.R1.S16: wrcmd2dqsstartlatency: 04
N6.C3.D1.R1.S12: RdPtrOffsetTxDq: 06
N0.C3.D1.R1.S16: RdPtrOffsetTxDq: 05
N6.C3.D1.R1.S13: RdPtrOffsetTxDq: 06
N0.C3.D1.R1.S16: RdPtrOffsetTxDqs: 07
N6.C3.D1.R1.S14: RdPtrOffsetTxDq: 06
N0.C3.D1.R1.S16: PiTxDqs: 31
N6.C3.D1.R1.S15: RdPtrOffsetTxDq: 06
N0.C3.D1.R1.S17: wrcmd2dqsstartlatency: 04
N6.C3.D1.R1.S16: RdPtrOffsetTxDq: 06
N0.C3.D1.R1.S17: RdPtrOffsetTxDq: 05
N6.C3.D1.R1.S17: RdPtrOffsetTxDq: 06
N0.C3.D1.R1.S17: RdPtrOffsetTxDqs: 07
N6.C3.D1.R1.S00: RdPtrOffsetTxDq: 08
N0.C3.D1.R1.S17: PiTxDqs: 01
N6.C3.D1.R1.S01: RdPtrOffsetTxDq: 08
N0.C3.D1.R1.S00: RdPtrOffsetTxDq: 07
N6.C3.D1.R1.S02: RdPtrOffsetTxDq: 07
N0.C3.D1.R1.S01: RdPtrOffsetTxDq: 07
N6.C3.D1.R1.S03: RdPtrOffsetTxDq: 07
N0.C3.D1.R1.S02: RdPtrOffsetTxDq: 07
N6.C3.D1.R1.S04: RdPtrOffsetTxDq: 07
N0.C3.D1.R1.S03: RdPtrOffsetTxDq: 06
N6.C3.D1.R1.S05: RdPtrOffsetTxDq: 07
N0.C3.D1.R1.S04: RdPtrOffsetTxDq: 06
N6.C3.D1.R1.S06: RdPtrOffsetTxDq: 07
N0.C3.D1.R1.S05: RdPtrOffsetTxDq: 06
N6.C3.D1.R1.S07: RdPtrOffsetTxDq: 07
N0.C3.D1.R1.S06: RdPtrOffsetTxDq: 06
N6.C3.D1.R1.S08: RdPtrOffsetTxDq: 07
N0.C3.D1.R1.S07: RdPtrOffsetTxDq: 06
N6.C3.D1.R1.S09: RdPtrOffsetTxDq: 08
N0.C3.D1.R1.S08: RdPtrOffsetTxDq: 06
N6.C3.D1.R1.S10: RdPtrOffsetTxDq: 08
N0.C3.D1.R1.S09: RdPtrOffsetTxDq: 07
N6.C3.D1.R1.S11: RdPtrOffsetTxDq: 08
N0.C3.D1.R1.S10: RdPtrOffsetTxDq: 07
N6.C3.D1.R1.S12: RdPtrOffsetTxDq: 07
N0.C3.D1.R1.S11: RdPtrOffsetTxDq: 07
N6.C3.D1.R1.S13: RdPtrOffsetTxDq: 07
N0.C3.D1.R1.S12: RdPtrOffsetTxDq: 06
N6.C3.D1.R1.S14: RdPtrOffsetTxDq: 07
N0.C3.D1.R1.S13: RdPtrOffsetTxDq: 06
N6.C3.D1.R1.S15: RdPtrOffsetTxDq: 07
N0.C3.D1.R1.S14: RdPtrOffsetTxDq: 06
N6.C3.D1.R1.S16: RdPtrOffsetTxDq: 07
N0.C3.D1.R1.S15: RdPtrOffsetTxDq: 06
N6.C3.D1.R1.S17: RdPtrOffsetTxDq: 07
N0.C3.D1.R1.S16: RdPtrOffsetTxDq: 06
N6.C3.D1.R1.S00: Total Delay in PI ticks: TxDQ = 989
N0.C3.D1.R1.S17: RdPtrOffsetTxDq: 06
N6.C3.D1.R1.S01: Total Delay in PI ticks: TxDQ = 971
N0.C3.D1.R1.S00: RdPtrOffsetTxDq: 08
N6.C3.D1.R1.S02: Total Delay in PI ticks: TxDQ = 959
N0.C3.D1.R1.S01: RdPtrOffsetTxDq: 08
N6.C3.D1.R1.S03: Total Delay in PI ticks: TxDQ = 947
N0.C3.D1.R1.S02: RdPtrOffsetTxDq: 08
N6.C3.D1.R1.S04: Total Delay in PI ticks: TxDQ = 909
N0.C3.D1.R1.S03: RdPtrOffsetTxDq: 07
N6.C3.D1.R1.S05: Total Delay in PI ticks: TxDQ = 924
N0.C3.D1.R1.S04: RdPtrOffsetTxDq: 07
N6.C3.D1.R1.S06: Total Delay in PI ticks: TxDQ = 938
N0.C3.D1.R1.S05: RdPtrOffsetTxDq: 07
N6.C3.D1.R1.S07: Total Delay in PI ticks: TxDQ = 955
N0.C3.D1.R1.S06: RdPtrOffsetTxDq: 07
N6.C3.D1.R1.S08: Total Delay in PI ticks: TxDQ = 923
N0.C3.D1.R1.S07: RdPtrOffsetTxDq: 07
N6.C3.D1.R1.S09: Total Delay in PI ticks: TxDQ = 985
N0.C3.D1.R1.S08: RdPtrOffsetTxDq: 07
N6.C3.D1.R1.S10: Total Delay in PI ticks: TxDQ = 971
N0.C3.D1.R1.S09: RdPtrOffsetTxDq: 08
N6.C3.D1.R1.S11: Total Delay in PI ticks: TxDQ = 962
N0.C3.D1.R1.S10: RdPtrOffsetTxDq: 08
N6.C3.D1.R1.S12: Total Delay in PI ticks: TxDQ = 948
N0.C3.D1.R1.S11: RdPtrOffsetTxDq: 08
N6.C3.D1.R1.S13: Total Delay in PI ticks: TxDQ = 909
N0.C3.D1.R1.S12: RdPtrOffsetTxDq: 07
N6.C3.D1.R1.S14: Total Delay in PI ticks: TxDQ = 925
N0.C3.D1.R1.S13: RdPtrOffsetTxDq: 07
N6.C3.D1.R1.S15: Total Delay in PI ticks: TxDQ = 937
N0.C3.D1.R1.S14: RdPtrOffsetTxDq: 07
N6.C3.D1.R1.S16: Total Delay in PI ticks: TxDQ = 956
N0.C3.D1.R1.S15: RdPtrOffsetTxDq: 07
N6.C3.D1.R1.S17: Total Delay in PI ticks: TxDQ = 923
N0.C3.D1.R1.S16: RdPtrOffsetTxDq: 07
N6.C3: Calculating Optimimum DQ/DQS Values
N0.C3.D1.R1.S17: RdPtrOffsetTxDq: 07
N0.C3.D1.R1.S00: Total Delay in PI ticks: TxDQ = 993
N0.C3.D1.R1.S01: Total Delay in PI ticks: TxDQ = 974
N0.C3.D1.R1.S02: Total Delay in PI ticks: TxDQ = 963
N0.C3.D1.R1.S03: Total Delay in PI ticks: TxDQ = 949
START_DATA_TX_DQ
N0.C3.D1.R1.S04: Total Delay in PI ticks: TxDQ = 914
N6.C3.S00: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 009, RdPtrOffsetTxDqs = 009
N0.C3.D1.R1.S05: Total Delay in PI ticks: TxDQ = 927
N6.C3.S00: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 009, RdPtrOffsetTxDqs = 009
N0.C3.D1.R1.S06: Total Delay in PI ticks: TxDQ = 940
N6.C3.S01: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 009, RdPtrOffsetTxDqs = 009
N0.C3.D1.R1.S07: Total Delay in PI ticks: TxDQ = 959
N6.C3.S01: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 009, RdPtrOffsetTxDqs = 009
N0.C3.D1.R1.S08: Total Delay in PI ticks: TxDQ = 925
N6.C3.S02: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 009
N0.C3.D1.R1.S09: Total Delay in PI ticks: TxDQ = 990
N6.C3.S02: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 009
N0.C3.D1.R1.S10: Total Delay in PI ticks: TxDQ = 975
N6.C3.S03: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 009
N0.C3.D1.R1.S11: Total Delay in PI ticks: TxDQ = 964
N6.C3.S03: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 009
N0.C3.D1.R1.S12: Total Delay in PI ticks: TxDQ = 950
N6.C3.S04: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 008
N0.C3.D1.R1.S13: Total Delay in PI ticks: TxDQ = 916
N6.C3.S04: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 008
N0.C3.D1.R1.S14: Total Delay in PI ticks: TxDQ = 929
N6.C3.S05: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 008
N0.C3.D1.R1.S15: Total Delay in PI ticks: TxDQ = 940
N6.C3.S05: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 008
N0.C3.D1.R1.S16: Total Delay in PI ticks: TxDQ = 957
N6.C3.S06: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 009
N0.C3.D1.R1.S17: Total Delay in PI ticks: TxDQ = 927
N6.C3.S06: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 009
N0.C3: Calculating Optimimum DQ/DQS Values
N6.C3.S07: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 009
N6.C3.S07: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 009
N6.C3.S08: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 008
START_DATA_TX_DQ
N6.C3.S08: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 008
N0.C3.S00: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 009, RdPtrOffsetTxDqs = 010
N6.C3.D0.R0.S00: TxDqs: plus1 = 1, minus1 = 0, PI = 54, DB = 1
N0.C3.S00: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 009, RdPtrOffsetTxDqs = 010
N6.C3.D0.R0.S00: TxDq : plus1 = 1, minus1 = 0, PI = 23, DB = 0
N0.C3.S01: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 009, RdPtrOffsetTxDqs = 009
N6.C3.D0.R0.S01: TxDqs: plus1 = 1, minus1 = 0, PI = 40, DB = 0
N0.C3.S01: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 009, RdPtrOffsetTxDqs = 009
N6.C3.D0.R0.S01: TxDq : plus1 = 1, minus1 = 0, PI = 08, DB = 1
N0.C3.S02: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 009, RdPtrOffsetTxDqs = 009
N6.C3.D0.R0.S02: TxDqs: plus1 = 1, minus1 = 0, PI = 31, DB = 0
N0.C3.S02: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 009, RdPtrOffsetTxDqs = 009
N6.C3.D0.R0.S02: TxDq : plus1 = 0, minus1 = 1, PI = 00, DB = 1
N0.C3.S03: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 009
START_DATA_TX_DQ_ADV
Results for N4.C0.D0.R0: 
           0   1   2   3   4   5   6   7   8   9  10  11  12  13  14  15  16  17
-------------------------------------------------------------------------------
Vref offset: 0
Left:    -21 -20 -21 -21 -22 -20 -20 -19 -21 -22 -20 -20 -20 -21 -22 -20 -21 -20
Right:    18  17  18  19  17  19  19  17  17  17  17  18  19  21  19  20  20  17
-------------------------------------------------------------------------------
Prev Pi: 470 449 440 422 390 407 409 425 402 469 449 438 422 390 405 410 426 400
New Pi:  469 448 439 421 388 407 409 424 400 467 448 437 422 390 404 410 426 399
Diff:     -1  -1  -1  -1  -2   0   0  -1  -2  -2  -1  -1   0   0  -1   0   0  -1

Results for N4.C0.D0.R1: 
           0   1   2   3   4   5   6   7   8   9  10  11  12  13  14  15  16  17
-------------------------------------------------------------------------------
Vref offset: 0
Left:    -23 -20 -20 -22 -22 -19 -20 -19 -19 -22 -20 -22 -21 -21 -22 -20 -20 -21
Right:    19  18  18  19  17  19  19  17  17  15  19  19  20  19  18  21  20  18
-------------------------------------------------------------------------------
Prev Pi: 470 449 440 422 390 407 409 425 402 469 449 438 422 390 405 410 426 400
New Pi:  468 448 439 421 388 407 409 424 401 466 449 437 422 389 403 410 426 399
Diff:     -2  -1  -1  -1  -2   0   0  -1  -1  -3   0  -1   0  -1  -2   0   0  -1

Results for N4.C0.D1.R0: 
           0   1   2   3   4   5   6   7   8   9  10  11  12  13  14  15  16  17
-------------------------------------------------------------------------------
Vref offset: 0
Left:    -20 -19 -20 -19 -21 -20 -17 -17 -20 -21 -19 -20 -19 -20 -19 -18 -18 -19
Right:    17  15  16  15  14  15  18  15  16  16  16  16  18  19  16  18  18  16
-------------------------------------------------------------------------------
Prev Pi: 472 456 443 425 392 410 413 430 401 472 457 442 429 393 411 415 430 401
New Pi:  471 454 441 423 389 408 413 429 399 470 456 440 429 393 410 415 430 400
Diff:     -1  -2  -2  -2  -3  -2   0  -1  -2  -2  -1  -2   0   0  -1   0   0  -1

Results for N4.C0.D1.R1: 
           0   1   2   3   4   5   6   7   8   9  10  11  12  13  14  15  16  17
-------------------------------------------------------------------------------
Vref offset: 0
Left:    -21 -20 -20 -19 -20 -19 -16 -17 -19 -22 -20 -20 -21 -20 -20 -19 -17 -19
Right:    16  15  16  17  15  14  18  15  17  16  17  17  17  19  14  18  18  16
-------------------------------------------------------------------------------
Prev Pi: 472 456 443 425 392 410 413 430 401 472 457 442 429 393 411 415 430 401
New Pi:  470 454 441 424 390 408 414 429 400 469 456 441 427 393 408 415 430 400
Diff:     -2  -2  -2  -1  -2  -2   1  -1  -1  -3  -1  -1  -2   0  -3   0   0  -1

Results for N4.C1.D0.R0: 
           0   1   2   3   4   5   6   7   8   9  10  11  12  13  14  15  16  17
-------------------------------------------------------------------------------
Vref offset: 0
Left:    -19 -20 -19 -21 -21 -20 -19 -18 -20 -20 -20 -20 -21 -21 -17 -17 -20 -20
Right:    17  17  15  18  18  18  17  18  20  16  19  20  18  20  19  17  18  17
-------------------------------------------------------------------------------
Prev Pi: 470 453 444 430 397 407 423 437 411 469 455 446 432 396 409 425 439 412
New Pi:  469 452 442 429 396 406 422 437 411 467 455 446 431 396 410 425 438 411
Diff:     -1  -1  -2  -1  -1  -1  -1   0   0  -2   0   0  -1   0   1   0  -1  -1

Results for N4.C1.D0.R1: 
           0   1   2   3   4   5   6   7   8   9  10  11  12  13  14  15  16  17
-------------------------------------------------------------------------------
Vref offset: 0
Left:    -21 -19 -18 -21 -21 -19 -17 -19 -19 -19 -20 -20 -21 -21 -18 -18 -19 -22
Right:    19  18  18  17  18  18  18  17  20  16  18  18  18  19  18  18  19  21
-------------------------------------------------------------------------------
Prev Pi: 470 453 444 430 397 407 423 437 411 469 455 446 432 396 409 425 439 412
New Pi:  469 453 444 428 396 407 423 436 411 468 454 445 431 395 409 425 439 412
Diff:     -1   0   0  -2  -1   0   0  -1   0  -1  -1  -1  -1  -1   0   0   0   0

Results for N4.C1.D1.R0: 
           0   1   2   3   4   5   6   7   8   9  10  11  12  13  14  15  16  17
-------------------------------------------------------------------------------
Vref offset: 0
Left:    -17 -16 -19 -19 -19 -17 -16 -17 -18 -20 -19 -20 -22 -20 -17 -14 -17 -19
Right:    16  16  13  13  14  16  16  15  16  13  17  16  14  17  16  17  17  17
-------------------------------------------------------------------------------
Prev Pi: 474 457 447 431 398 411 424 441 410 471 457 447 434 398 410 425 442 409
New Pi:  474 457 444 428 396 411 424 440 409 468 456 445 430 397 410 426 442 408
Diff:      0   0  -3  -3  -2   0   0  -1  -1  -3  -1  -2  -4  -1   0   1   0  -1

Results for N4.C1.D1.R1: 
           0   1   2   3   4   5   6   7   8   9  10  11  12  13  14  15  16  17
-------------------------------------------------------------------------------
Vref offset: 0
Left:    -18 -16 -20 -20 -20 -16 -16 -17 -19 -19 -20 -19 -21 -21 -17 -16 -18 -20
Right:    16  17  14  14  15  16  15  15  16  13  17  17  15  17  16  19  15  17
-------------------------------------------------------------------------------
Prev Pi: 474 457 447 431 398 411 424 441 410 471 457 447 434 398 410 425 442 409
New Pi:  473 457 444 428 396 411 424 440 409 468 456 446 431 396 410 426 441 408
Diff:     -1   0  -3  -3  -2   0   0  -1  -1  -3  -1  -1  -3  -2   0   1  -1  -1

Results for N4.C2.D0.R0: 
           0   1   2   3   4   5   6   7   8   9  10  11  12  13  14  15  16  17
-------------------------------------------------------------------------------
Vref offset: 0
Left:    -20 -19 -17 -23 -22 -20 -19 -20 -19 -18 -21 -18 -22 -21 -21 -20 -22 -18
Right:    17  19  18  18  18  16  18  19  16  21  17  20  19  21  18  21  19  19
-------------------------------------------------------------------------------
Prev Pi: 464 448 439 421 382 409 408 427 400 464 450 439 423 382 411 409 427 397
New Pi:  463 448 439 419 380 407 408 427 399 465 448 440 422 382 410 409 426 397
Diff:     -1   0   0  -2  -2  -2   0   0  -1   1  -2   1  -1   0  -1   0  -1   0

Results for N4.C2.D0.R1: 
           0   1   2   3   4   5   6   7   8   9  10  11  12  13  14  15  16  17
-------------------------------------------------------------------------------
Vref offset: 0
Left:    -21 -19 -17 -22 -23 -20 -19 -20 -20 -19 -21 -17 -22 -21 -21 -20 -21 -19
Right:    19  18  18  18  18  16  19  19  15  18  18  19  19  21  19  21  19  18
-------------------------------------------------------------------------------
Prev Pi: 464 448 439 421 382 409 408 427 400 464 450 439 423 382 411 409 427 397
New Pi:  463 448 439 419 380 407 408 427 398 464 449 440 422 382 410 409 426 397
Diff:     -1   0   0  -2  -2  -2   0   0  -2   0  -1   1  -1   0  -1   0  -1   0

Results for N4.C2.D1.R0: 
           0   1   2   3   4   5   6   7   8   9  10  11  12  13  14  15  16  17
-------------------------------------------------------------------------------
Vref offset: 0
Left:    -20 -19 -20 -19 -20 -18 -19 -17 -21 -21 -19 -20 -18 -21 -20 -15 -18 -19
Right:    14  15  13  16  13  15  15  16  14  13  16  14  18  16  15  19  17  14
-------------------------------------------------------------------------------
Prev Pi: 467 452 443 427 387 415 411 431 402 467 453 443 428 386 415 413 432 401
New Pi:  464 450 440 426 384 414 409 431 399 463 452 440 428 384 413 415 432 399
Diff:     -3  -2  -3  -1  -3  -1  -2   0  -3  -4  -1  -3   0  -2  -2   2   0  -2

Results for N4.C2.D1.R1: 
           0   1   2   3   4   5   6   7   8   9  10  11  12  13  14  15  16  17
-------------------------------------------------------------------------------
Vref offset: 0
Left:    -22 -20 -19 -20 -20 -17 -18 -18 -20 -21 -20 -20 -20 -21 -20 -17 -19 -20
Right:    15  15  14  18  14  16  15  16  13  14  16  14  18  18  16  20  17  13
-------------------------------------------------------------------------------
Prev Pi: 467 452 443 427 387 415 411 431 402 467 453 443 428 386 415 413 432 401
New Pi:  464 450 441 426 384 415 410 430 399 464 451 440 427 385 413 414 431 398
Diff:     -3  -2  -2  -1  -3   0  -1  -1  -3  -3  -2  -3  -1  -1  -2   1  -1  -3

Results for N4.C3.D0.R0: 
           0   1   2   3   4   5   6   7   8   9  10  11  12  13  14  15  16  17
-------------------------------------------------------------------------------
Vref offset: 0
Left:    -20 -20 -19 -22 -22 -19 -18 -16 -21 -19 -20 -21 -20 -22 -19 -18 -18 -22
Right:    21  21  19  20  19  18  18  20  18  19  20  17  19  20  21  18  19  18
-------------------------------------------------------------------------------
Prev Pi: 475 459 447 433 396 412 425 440 415 474 459 447 435 398 411 428 441 413
New Pi:  475 459 447 432 395 412 425 442 414 474 459 445 435 397 412 428 441 411
Diff:      0   0   0  -1  -1   0   0   2  -1   0   0  -2   0  -1   1   0   0  -2

Results for N4.C3.D0.R1: 
           0   1   2   3   4   5   6   7   8   9  10  11  12  13  14  15  16  17
-------------------------------------------------------------------------------
Vref offset: 0
Left:    -20 -19 -19 -21 -22 -19 -17 -17 -21 -20 -21 -21 -20 -21 -17 -19 -18 -23
Right:    18  21  18  19  18  18  18  19  19  19  21  17  19  20  20  20  21  18
-------------------------------------------------------------------------------
Prev Pi: 475 459 447 433 396 412 425 440 415 474 459 447 435 398 411 428 441 413
New Pi:  474 460 447 432 394 412 425 441 414 474 459 445 435 398 412 428 442 411
Diff:     -1   1   0  -1  -2   0   0   1  -1   0   0  -2   0   0   1   0   1  -2

Results for N4.C3.D1.R0: 
           0   1   2   3   4   5   6   7   8   9  10  11  12  13  14  15  16  17
-------------------------------------------------------------------------------
Vref offset: 0
Left:    -17 -20 -20 -19 -20 -17 -17 -15 -17 -18 -18 -18 -18 -19 -16 -17 -17 -19
Right:    16  16  15  17  15  16  15  15  16  16  18  17  16  18  17  17  17  16
-------------------------------------------------------------------------------
Prev Pi: 480 466 453 439 402 416 430 447 417 477 465 451 441 403 417 432 448 417
New Pi:  480 464 451 438 400 416 429 447 417 476 465 451 440 403 417 432 448 416
Diff:      0  -2  -2  -1  -2   0  -1   0   0  -1   0   0  -1   0   0   0   0  -1

Results for N4.C3.D1.R1: 
           0   1   2   3   4   5   6   7   8   9  10  11  12  13  14  15  16  17
-------------------------------------------------------------------------------
Vref offset: 0
Left:    -21 -19 -19 -19 -19 -16 -17 -16 -18 -18 -19 -19 -19 -20 -16 -18 -16 -19
Right:    17  17  16  17  16  17  14  17  15  16  17  16  15  17  17  17  18  16
-------------------------------------------------------------------------------
Prev Pi: 480 466 453 439 402 416 430 447 417 477 465 451 441 403 417 432 448 417
New Pi:  478 465 452 438 401 416 429 447 416 476 464 450 439 402 417 432 449 416
Diff:     -2  -1  -1  -1  -1   0  -1   0  -1  -1  -1  -1  -2  -1   0   0   1  -1

STOP_DATA_TX_DQ_ADV
N6.C3.D0.R0.S03: TxDqs: plus1 = 1, minus1 = 0, PI = 15, DB = 1
N0.C3.S03: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 009
N2.C0: Read Vref - Strobe:0 Worst Left Edge:-29, Worst Right Edge:31, Center:1
N4: RunTrainStep: Final status = 0
N6.C3.D0.R0.S03: TxDq : plus1 = 1, minus1 = 0, PI = 46, DB = 0
N0.C3.S04: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 008
N2.C0: Read Vref - Strobe:1 Worst Left Edge:-29, Worst Right Edge:31, Center:1

END - Wr Timing Centering 2D Training  Time         5154 ms
N6.C3.D0.R0.S04: TxDqs: plus1 = 1, minus1 = 0, PI = 42, DB = 0
N0.C3.S04: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 008
N2.C0: Read Vref - Strobe:2 Worst Left Edge:-31, Worst Right Edge:31, Center:0

START - Rd Voltage Training
N6.C3.D0.R0.S04: TxDq : plus1 = 1, minus1 = 0, PI = 08, DB = 1
N0.C3.S05: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 008
N2.C0: Read Vref - Strobe:3 Worst Left Edge:-29, Worst Right Edge:31, Center:1
N4: RX Vref Training...
N6.C3.D0.R0.S05: TxDqs: plus1 = 1, minus1 = 0, PI = 56, DB = 1
N0.C3.S05: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 008
N2.C0: Read Vref - Strobe:4 Worst Left Edge:-25, Worst Right Edge:31, Center:3
N4: GetMargins: Level = 1, group = 13, mode = 2, scope = 4
N6.C3.D0.R0.S05: TxDq : plus1 = 1, minus1 = 0, PI = 24, DB = 0
N0.C3.S06: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 009
N2.C0: Read Vref - Strobe:5 Worst Left Edge:-29, Worst Right Edge:31, Center:1
N6.C3.D0.R0.S06: TxDqs: plus1 = 1, minus1 = 0, PI = 07, DB = 1
N0.C3.S06: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 009
N2.C0: Read Vref - Strobe:6 Worst Left Edge:-30, Worst Right Edge:30, Center:0
N6.C3.D0.R0.S06: TxDq : plus1 = 1, minus1 = 0, PI = 40, DB = 0
N0.C3.S07: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 009
N2.C0: Read Vref - Strobe:7 Worst Left Edge:-24, Worst Right Edge:31, Center:3
N6.C3.D0.R0.S07: TxDqs: plus1 = 1, minus1 = 0, PI = 24, DB = 0
N0.C3.S07: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 009
N2.C0: Read Vref - Strobe:8 Worst Left Edge:-25, Worst Right Edge:31, Center:3
N6.C3.D0.R0.S07: TxDq : plus1 = 1, minus1 = 0, PI = 54, DB = 1
N0.C3.S08: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 009
N2.C0: Read Vref - Strobe:9 Worst Left Edge:-31, Worst Right Edge:31, Center:0
N6.C3.D0.R0.S08: TxDqs: plus1 = 1, minus1 = 0, PI = 60, DB = 1
N0.C3.S08: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 009
N2.C0: Read Vref - Strobe:10 Worst Left Edge:-31, Worst Right Edge:31, Center:0
N6.C3.D0.R0.S08: TxDq : plus1 = 1, minus1 = 0, PI = 27, DB = 0
N0.C3.D0.R0.S00: TxDqs: plus1 = 1, minus1 = 0, PI = 00, DB = 1
N2.C0: Read Vref - Strobe:11 Worst Left Edge:-27, Worst Right Edge:31, Center:2
N6.C3.D0.R0.S09: TxDqs: plus1 = 1, minus1 = 0, PI = 55, DB = 1
N0.C3.D0.R0.S00: TxDq : plus1 = 1, minus1 = 0, PI = 30, DB = 0
N2.C0: Read Vref - Strobe:12 Worst Left Edge:-31, Worst Right Edge:31, Center:0
N6.C3.D0.R0.S09: TxDq : plus1 = 1, minus1 = 0, PI = 21, DB = 0
N0.C3.D0.R0.S01: TxDqs: plus1 = 1, minus1 = 0, PI = 46, DB = 0
N2.C0: Read Vref - Strobe:13 Worst Left Edge:-30, Worst Right Edge:31, Center:0
N6.C3.D0.R0.S10: TxDqs: plus1 = 1, minus1 = 0, PI = 39, DB = 0
N0.C3.D0.R0.S01: TxDq : plus1 = 1, minus1 = 0, PI = 12, DB = 1
N2.C0: Read Vref - Strobe:14 Worst Left Edge:-23, Worst Right Edge:31, Center:4
N6.C3.D0.R0.S10: TxDq : plus1 = 1, minus1 = 0, PI = 08, DB = 1
N0.C3.D0.R0.S02: TxDqs: plus1 = 1, minus1 = 0, PI = 35, DB = 0
N2.C0: Read Vref - Strobe:15 Worst Left Edge:-29, Worst Right Edge:31, Center:1
N6.C3.D0.R0.S11: TxDqs: plus1 = 1, minus1 = 0, PI = 29, DB = 0
N0.C3.D0.R0.S02: TxDq : plus1 = 1, minus1 = 0, PI = 02, DB = 1
N2.C0: Read Vref - Strobe:16 Worst Left Edge:-28, Worst Right Edge:31, Center:1
N6.C3.D0.R0.S11: TxDq : plus1 = 1, minus1 = 0, PI = 61, DB = 1
N0.C3.D0.R0.S03: TxDqs: plus1 = 1, minus1 = 0, PI = 18, DB = 0
N2.C0: Read Vref - Strobe:17 Worst Left Edge:-29, Worst Right Edge:31, Center:1
N6.C3.D0.R0.S12: TxDqs: plus1 = 1, minus1 = 0, PI = 14, DB = 1
N0.C3.D0.R0.S03: TxDq : plus1 = 1, minus1 = 0, PI = 49, DB = 1
N2.C1: Read Vref - Strobe:0 Worst Left Edge:-30, Worst Right Edge:31, Center:0
N6.C3.D0.R0.S12: TxDq : plus1 = 1, minus1 = 0, PI = 46, DB = 0
N0.C3.D0.R0.S04: TxDqs: plus1 = 1, minus1 = 0, PI = 49, DB = 1
N2.C1: Read Vref - Strobe:1 Worst Left Edge:-27, Worst Right Edge:31, Center:2
N6.C3.D0.R0.S13: TxDqs: plus1 = 1, minus1 = 0, PI = 42, DB = 0
N0.C3.D0.R0.S04: TxDq : plus1 = 1, minus1 = 0, PI = 15, DB = 1
N2.C1: Read Vref - Strobe:2 Worst Left Edge:-26, Worst Right Edge:31, Center:2
N6.C3.D0.R0.S13: TxDq : plus1 = 1, minus1 = 0, PI = 09, DB = 1
N0.C3.D0.R0.S05: TxDqs: plus1 = 1, minus1 = 0, PI = 62, DB = 1
N2.C1: Read Vref - Strobe:3 Worst Left Edge:-31, Worst Right Edge:31, Center:0
N6.C3.D0.R0.S14: TxDqs: plus1 = 1, minus1 = 0, PI = 56, DB = 1
N0.C3.D0.R0.S05: TxDq : plus1 = 1, minus1 = 0, PI = 29, DB = 0
N2.C1: Read Vref - Strobe:4 Worst Left Edge:-27, Worst Right Edge:31, Center:2
N6.C3.D0.R0.S14: TxDq : plus1 = 1, minus1 = 0, PI = 25, DB = 0
N0.C3.D0.R0.S06: TxDqs: plus1 = 1, minus1 = 0, PI = 13, DB = 1
N2.C1: Read Vref - Strobe:5 Worst Left Edge:-27, Worst Right Edge:31, Center:2
N6.C3.D0.R0.S15: TxDqs: plus1 = 1, minus1 = 0, PI = 06, DB = 1
N0.C3.D0.R0.S06: TxDq : plus1 = 1, minus1 = 0, PI = 43, DB = 0
N2.C1: Read Vref - Strobe:6 Worst Left Edge:-23, Worst Right Edge:31, Center:4
N6.C3.D0.R0.S15: TxDq : plus1 = 1, minus1 = 0, PI = 39, DB = 0
N0.C3.D0.R0.S07: TxDqs: plus1 = 1, minus1 = 0, PI = 30, DB = 0
N2.C1: Read Vref - Strobe:7 Worst Left Edge:-28, Worst Right Edge:31, Center:1
N6.C3.D0.R0.S16: TxDqs: plus1 = 1, minus1 = 0, PI = 25, DB = 0
N0.C3.D0.R0.S07: TxDq : plus1 = 1, minus1 = 0, PI = 60, DB = 1
N2.C1: Read Vref - Strobe:8 Worst Left Edge:-27, Worst Right Edge:31, Center:2
N6.C3.D0.R0.S16: TxDq : plus1 = 1, minus1 = 0, PI = 57, DB = 1
N0.C3.D0.R0.S08: TxDqs: plus1 = 1, minus1 = 0, PI = 01, DB = 1
N2.C1: Read Vref - Strobe:9 Worst Left Edge:-26, Worst Right Edge:31, Center:2
N6.C3.D0.R0.S17: TxDqs: plus1 = 1, minus1 = 0, PI = 59, DB = 1
N0.C3.D0.R0.S08: TxDq : plus1 = 1, minus1 = 0, PI = 32, DB = 0
N2.C1: Read Vref - Strobe:10 Worst Left Edge:-26, Worst Right Edge:31, Center:2
N6.C3.D0.R0.S17: TxDq : plus1 = 1, minus1 = 0, PI = 26, DB = 0
N0.C3.D0.R0.S09: TxDqs: plus1 = 1, minus1 = 0, PI = 00, DB = 1
N2.C1: Read Vref - Strobe:11 Worst Left Edge:-28, Worst Right Edge:31, Center:1
N6.C3.D0.R1.S00: TxDqs: plus1 = 1, minus1 = 0, PI = 54, DB = 1
N0.C3.D0.R0.S09: TxDq : plus1 = 1, minus1 = 0, PI = 29, DB = 0
N2.C1: Read Vref - Strobe:12 Worst Left Edge:-23, Worst Right Edge:31, Center:4
N6.C3.D0.R1.S00: TxDq : plus1 = 1, minus1 = 0, PI = 23, DB = 0
N0.C3.D0.R0.S10: TxDqs: plus1 = 1, minus1 = 0, PI = 46, DB = 0
N2.C1: Read Vref - Strobe:13 Worst Left Edge:-23, Worst Right Edge:31, Center:4
N6.C3.D0.R1.S01: TxDqs: plus1 = 1, minus1 = 0, PI = 40, DB = 0
N0.C3.D0.R0.S10: TxDq : plus1 = 1, minus1 = 0, PI = 12, DB = 1
N2.C1: Read Vref - Strobe:14 Worst Left Edge:-22, Worst Right Edge:31, Center:4
N6.C3.D0.R1.S01: TxDq : plus1 = 1, minus1 = 0, PI = 08, DB = 1
N0.C3.D0.R0.S11: TxDqs: plus1 = 1, minus1 = 0, PI = 36, DB = 0
N2.C1: Read Vref - Strobe:15 Worst Left Edge:-31, Worst Right Edge:31, Center:0
N6.C3.D0.R1.S02: TxDqs: plus1 = 1, minus1 = 0, PI = 31, DB = 0
N0.C3.D0.R0.S11: TxDq : plus1 = 1, minus1 = 0, PI = 03, DB = 1
N2.C1: Read Vref - Strobe:16 Worst Left Edge:-27, Worst Right Edge:31, Center:2
N6.C3.D0.R1.S02: TxDq : plus1 = 0, minus1 = 1, PI = 00, DB = 1
N0.C3.D0.R0.S12: TxDqs: plus1 = 1, minus1 = 0, PI = 22, DB = 0
N2.C1: Read Vref - Strobe:17 Worst Left Edge:-25, Worst Right Edge:31, Center:3
N6.C3.D0.R1.S03: TxDqs: plus1 = 1, minus1 = 0, PI = 15, DB = 1
N0.C3.D0.R0.S12: TxDq : plus1 = 1, minus1 = 0, PI = 52, DB = 1
N2.C2: Read Vref - Strobe:0 Worst Left Edge:-29, Worst Right Edge:31, Center:1
N6.C3.D0.R1.S03: TxDq : plus1 = 1, minus1 = 0, PI = 46, DB = 0
N0.C3.D0.R0.S13: TxDqs: plus1 = 1, minus1 = 0, PI = 49, DB = 1
N2.C2: Read Vref - Strobe:1 Worst Left Edge:-24, Worst Right Edge:31, Center:3
N6.C3.D0.R1.S04: TxDqs: plus1 = 1, minus1 = 0, PI = 42, DB = 0
N0.C3.D0.R0.S13: TxDq : plus1 = 1, minus1 = 0, PI = 16, DB = 0
N2.C2: Read Vref - Strobe:2 Worst Left Edge:-27, Worst Right Edge:31, Center:2
N6.C3.D0.R1.S04: TxDq : plus1 = 1, minus1 = 0, PI = 08, DB = 1
N0.C3.D0.R0.S14: TxDqs: plus1 = 1, minus1 = 0, PI = 63, DB = 1
N2.C2: Read Vref - Strobe:3 Worst Left Edge:-26, Worst Right Edge:31, Center:2
N6.C3.D0.R1.S05: TxDqs: plus1 = 1, minus1 = 0, PI = 56, DB = 1
N0.C3.D0.R0.S14: TxDq : plus1 = 1, minus1 = 0, PI = 29, DB = 0
N2.C2: Read Vref - Strobe:4 Worst Left Edge:-23, Worst Right Edge:31, Center:4
N6.C3.D0.R1.S05: TxDq : plus1 = 1, minus1 = 0, PI = 24, DB = 0
N0.C3.D0.R0.S15: TxDqs: plus1 = 1, minus1 = 0, PI = 14, DB = 1
N2.C2: Read Vref - Strobe:5 Worst Left Edge:-23, Worst Right Edge:31, Center:4
N6.C3.D0.R1.S06: TxDqs: plus1 = 1, minus1 = 0, PI = 07, DB = 1
N0.C3.D0.R0.S15: TxDq : plus1 = 1, minus1 = 0, PI = 44, DB = 0
N2.C2: Read Vref - Strobe:6 Worst Left Edge:-26, Worst Right Edge:31, Center:2
N6.C3.D0.R1.S06: TxDq : plus1 = 1, minus1 = 0, PI = 40, DB = 0
N0.C3.D0.R0.S16: TxDqs: plus1 = 1, minus1 = 0, PI = 28, DB = 0
N2.C2: Read Vref - Strobe:7 Worst Left Edge:-22, Worst Right Edge:31, Center:4
N6.C3.D0.R1.S07: TxDqs: plus1 = 1, minus1 = 0, PI = 24, DB = 0
N0.C3.D0.R0.S16: TxDq : plus1 = 1, minus1 = 0, PI = 59, DB = 1
N2.C2: Read Vref - Strobe:8 Worst Left Edge:-31, Worst Right Edge:31, Center:0
N6.C3.D0.R1.S07: TxDq : plus1 = 1, minus1 = 0, PI = 54, DB = 1
N0.C3.D0.R0.S17: TxDqs: plus1 = 1, minus1 = 0, PI = 02, DB = 1
N2.C2: Read Vref - Strobe:9 Worst Left Edge:-24, Worst Right Edge:31, Center:3
N6.C3.D0.R1.S08: TxDqs: plus1 = 1, minus1 = 0, PI = 60, DB = 1
N0.C3.D0.R0.S17: TxDq : plus1 = 1, minus1 = 0, PI = 33, DB = 0
N2.C2: Read Vref - Strobe:10 Worst Left Edge:-21, Worst Right Edge:31, Center:5
N6.C3.D0.R1.S08: TxDq : plus1 = 1, minus1 = 0, PI = 27, DB = 0
N0.C3.D0.R1.S00: TxDqs: plus1 = 1, minus1 = 0, PI = 00, DB = 1
N2.C2: Read Vref - Strobe:11 Worst Left Edge:-30, Worst Right Edge:31, Center:0
N6.C3.D0.R1.S09: TxDqs: plus1 = 1, minus1 = 0, PI = 55, DB = 1
N0.C3.D0.R1.S00: TxDq : plus1 = 1, minus1 = 0, PI = 30, DB = 0
N2.C2: Read Vref - Strobe:12 Worst Left Edge:-30, Worst Right Edge:31, Center:0
N6.C3.D0.R1.S09: TxDq : plus1 = 1, minus1 = 0, PI = 21, DB = 0
N0.C3.D0.R1.S01: TxDqs: plus1 = 1, minus1 = 0, PI = 46, DB = 0
N2.C2: Read Vref - Strobe:13 Worst Left Edge:-27, Worst Right Edge:31, Center:2
N6.C3.D0.R1.S10: TxDqs: plus1 = 1, minus1 = 0, PI = 39, DB = 0
N0.C3.D0.R1.S01: TxDq : plus1 = 1, minus1 = 0, PI = 12, DB = 1
N2.C2: Read Vref - Strobe:14 Worst Left Edge:-31, Worst Right Edge:31, Center:0
N6.C3.D0.R1.S10: TxDq : plus1 = 1, minus1 = 0, PI = 08, DB = 1
N0.C3.D0.R1.S02: TxDqs: plus1 = 1, minus1 = 0, PI = 35, DB = 0
N2.C2: Read Vref - Strobe:15 Worst Left Edge:-22, Worst Right Edge:31, Center:4
N6.C3.D0.R1.S11: TxDqs: plus1 = 1, minus1 = 0, PI = 29, DB = 0
N0.C3.D0.R1.S02: TxDq : plus1 = 1, minus1 = 0, PI = 02, DB = 1
N2.C2: Read Vref - Strobe:16 Worst Left Edge:-25, Worst Right Edge:31, Center:3
N6.C3.D0.R1.S11: TxDq : plus1 = 1, minus1 = 0, PI = 61, DB = 1
N0.C3.D0.R1.S03: TxDqs: plus1 = 1, minus1 = 0, PI = 18, DB = 0
N2.C2: Read Vref - Strobe:17 Worst Left Edge:-30, Worst Right Edge:31, Center:0
N6.C3.D0.R1.S12: TxDqs: plus1 = 1, minus1 = 0, PI = 14, DB = 1
N0.C3.D0.R1.S03: TxDq : plus1 = 1, minus1 = 0, PI = 49, DB = 1
N2.C3: Read Vref - Strobe:0 Worst Left Edge:-25, Worst Right Edge:31, Center:3
N6.C3.D0.R1.S12: TxDq : plus1 = 1, minus1 = 0, PI = 46, DB = 0
N0.C3.D0.R1.S04: TxDqs: plus1 = 1, minus1 = 0, PI = 49, DB = 1
N2.C3: Read Vref - Strobe:1 Worst Left Edge:-28, Worst Right Edge:31, Center:1
N6.C3.D0.R1.S13: TxDqs: plus1 = 1, minus1 = 0, PI = 42, DB = 0
N0.C3.D0.R1.S04: TxDq : plus1 = 1, minus1 = 0, PI = 15, DB = 1
N2.C3: Read Vref - Strobe:2 Worst Left Edge:-29, Worst Right Edge:31, Center:1
N6.C3.D0.R1.S13: TxDq : plus1 = 1, minus1 = 0, PI = 09, DB = 1
N0.C3.D0.R1.S05: TxDqs: plus1 = 1, minus1 = 0, PI = 62, DB = 1
N2.C3: Read Vref - Strobe:3 Worst Left Edge:-31, Worst Right Edge:31, Center:0
N6.C3.D0.R1.S14: TxDqs: plus1 = 1, minus1 = 0, PI = 56, DB = 1
N0.C3.D0.R1.S05: TxDq : plus1 = 1, minus1 = 0, PI = 29, DB = 0
N2.C3: Read Vref - Strobe:4 Worst Left Edge:-24, Worst Right Edge:31, Center:3
N6.C3.D0.R1.S14: TxDq : plus1 = 1, minus1 = 0, PI = 25, DB = 0
N0.C3.D0.R1.S06: TxDqs: plus1 = 1, minus1 = 0, PI = 13, DB = 1
N2.C3: Read Vref - Strobe:5 Worst Left Edge:-31, Worst Right Edge:31, Center:0
N6.C3.D0.R1.S15: TxDqs: plus1 = 1, minus1 = 0, PI = 06, DB = 1
N0.C3.D0.R1.S06: TxDq : plus1 = 1, minus1 = 0, PI = 43, DB = 0
N2.C3: Read Vref - Strobe:6 Worst Left Edge:-26, Worst Right Edge:31, Center:2
N6.C3.D0.R1.S15: TxDq : plus1 = 1, minus1 = 0, PI = 39, DB = 0
N0.C3.D0.R1.S07: TxDqs: plus1 = 1, minus1 = 0, PI = 30, DB = 0
N2.C3: Read Vref - Strobe:7 Worst Left Edge:-26, Worst Right Edge:31, Center:2
N6.C3.D0.R1.S16: TxDqs: plus1 = 1, minus1 = 0, PI = 25, DB = 0
N0.C3.D0.R1.S07: TxDq : plus1 = 1, minus1 = 0, PI = 60, DB = 1
N2.C3: Read Vref - Strobe:8 Worst Left Edge:-30, Worst Right Edge:31, Center:0
N6.C3.D0.R1.S16: TxDq : plus1 = 1, minus1 = 0, PI = 57, DB = 1
N0.C3.D0.R1.S08: TxDqs: plus1 = 1, minus1 = 0, PI = 01, DB = 1
N2.C3: Read Vref - Strobe:9 Worst Left Edge:-28, Worst Right Edge:31, Center:1
N6.C3.D0.R1.S17: TxDqs: plus1 = 1, minus1 = 0, PI = 59, DB = 1
N0.C3.D0.R1.S08: TxDq : plus1 = 1, minus1 = 0, PI = 32, DB = 0
N2.C3: Read Vref - Strobe:10 Worst Left Edge:-29, Worst Right Edge:31, Center:1
N6.C3.D0.R1.S17: TxDq : plus1 = 1, minus1 = 0, PI = 26, DB = 0
N0.C3.D0.R1.S09: TxDqs: plus1 = 1, minus1 = 0, PI = 00, DB = 1
N2.C3: Read Vref - Strobe:11 Worst Left Edge:-20, Worst Right Edge:31, Center:5
N6.C3.D1.R0.S00: TxDqs: plus1 = 1, minus1 = 0, PI = 62, DB = 1
N0.C3.D0.R1.S09: TxDq : plus1 = 1, minus1 = 0, PI = 29, DB = 0
N2.C3: Read Vref - Strobe:12 Worst Left Edge:-27, Worst Right Edge:31, Center:2
N6.C3.D1.R0.S00: TxDq : plus1 = 1, minus1 = 0, PI = 30, DB = 0
N0.C3.D0.R1.S10: TxDqs: plus1 = 1, minus1 = 0, PI = 46, DB = 0
N2.C3: Read Vref - Strobe:13 Worst Left Edge:-29, Worst Right Edge:31, Center:1
N6.C3.D1.R0.S01: TxDqs: plus1 = 1, minus1 = 0, PI = 45, DB = 0
N0.C3.D0.R1.S10: TxDq : plus1 = 1, minus1 = 0, PI = 12, DB = 1
N2.C3: Read Vref - Strobe:14 Worst Left Edge:-30, Worst Right Edge:31, Center:0
N6.C3.D1.R0.S01: TxDq : plus1 = 1, minus1 = 0, PI = 13, DB = 1
N0.C3.D0.R1.S11: TxDqs: plus1 = 1, minus1 = 0, PI = 36, DB = 0
N2.C3: Read Vref - Strobe:15 Worst Left Edge:-28, Worst Right Edge:31, Center:1
N6.C3.D1.R0.S02: TxDqs: plus1 = 1, minus1 = 0, PI = 34, DB = 0
N0.C3.D0.R1.S11: TxDq : plus1 = 1, minus1 = 0, PI = 03, DB = 1
N2.C3: Read Vref - Strobe:16 Worst Left Edge:-27, Worst Right Edge:31, Center:2
N6.C3.D1.R0.S02: TxDq : plus1 = 0, minus1 = 1, PI = 02, DB = 1
N0.C3.D0.R1.S12: TxDqs: plus1 = 1, minus1 = 0, PI = 22, DB = 0
N2.C3: Read Vref - Strobe:17 Worst Left Edge:-26, Worst Right Edge:31, Center:2
N6.C3.D1.R0.S03: TxDqs: plus1 = 1, minus1 = 0, PI = 22, DB = 0
N0.C3.D0.R1.S12: TxDq : plus1 = 1, minus1 = 0, PI = 52, DB = 1
N2: RunTrainStep: Final status = 0
N6.C3.D1.R0.S03: TxDq : plus1 = 1, minus1 = 0, PI = 52, DB = 1
N0.C3.D0.R1.S13: TxDqs: plus1 = 1, minus1 = 0, PI = 49, DB = 1

END - Rd Voltage Training              Time         6763 ms
N6.C3.D1.R0.S04: TxDqs: plus1 = 1, minus1 = 0, PI = 50, DB = 1
N0.C3.D0.R1.S13: TxDq : plus1 = 1, minus1 = 0, PI = 16, DB = 0
N2.C0.D0.R0.S00: StoreJckWorstRank: worst rank = 0, greatestDelay = 1326
N6.C3.D1.R0.S04: TxDq : plus1 = 1, minus1 = 0, PI = 15, DB = 1
N0.C3.D0.R1.S14: TxDqs: plus1 = 1, minus1 = 0, PI = 63, DB = 1
N2.C0.D0.R0.S07: StoreJckWorstRaLoading PEIM at 0x000FFFD5CC0 EntryPoint=0x000FFFD6C90 
Register PPI Notify: F894643D-C449-42D1-8EA8-85BDD8C65BDE
Loading PEIM at 0x000FFFD91A0 EntryPoint=0x000FFFD9AE0 
Install PPI: E6AF1F7B-FC3F-46DA-A828-A3B457A44282
Loading PEIM at 0x000FFFE51E0 EntryPoint=0x000FFFE5B20 
Register PPI Notify: F894643D-C449-42D1-8EA8-85BDD8C65BDE
Loading PEIM at 0x000FFFEB7A0 EntryPoint=0x000FFFEC258 
InstallPchSpi() Start
Install PPI: A38C6898-2B5C-4FF6-9326-2E63212E56C2
SPI PPI Installed
InstallPchSpi() End
Loading PEIM at 0x000FFFEDEE0 EntryPoint=0x000FFFEE658 
Loading PEIM at 0x000FFD55520 EntryPoint=0x000FFD55750 
Loading PEIM at 0x000FFD558A0 EntryPoint=0x000FFD56228 
Install PPI: 7F19E716-419C-4E79-8E37-C2BD84EB6528
Flash Map PEIM Loaded
Loading PEIM at 0x000FFD56E20 EntryPoint=0x000FFD57928 
Force an S5 exit path.
Install PPI: EE0EA811-FBD9-4777-B95A-BA4F71101F74
Install PPI: E5EE2066-FAA1-4DFA-924E-B1E3A8EE30E8
[HECI] MBAR not programmed in PEI phase, using default 0xFEDB0000
Loading PEIM at 0x000FFD5C680 EntryPoint=0x000FFD5D5D0 
[SPS] Waiting for ME firmware initialization
Register PPI Notify: 605EA650-C65C-42E1-BA80-91A52AB618C6
Loading PEIM at 0x000FFD5E6C0 EntryPoint=0x000FFD5EFF8 
InitializePchSmbusPeim() Start
Install PPI: 9CA93627-B65B-4324-A202-C0B461764543
Notify: PPI Guid: 9CA93627-B65B-4324-A202-C0B461764543, Peim notify entry point: FFFC2924
PEI SmbusExecute() Start
PEI SmbusExecute() End
Expected Clock Generator ID is 11, populated 31
PEI SmbusExecute() Start
PEI SmbusExecute() End
Register PPI Notify: F894643D-C449-42D1-8EA8-85BDD8C65BDE
InitializePchSmbusPeim() End
Loading PEIM at 0x000FFD5FFC0 EntryPoint=0x000FFD60AC0 
GUID HOB gEfiPlatformTxtDeviceMemoryGuid not found!
GUID HOB gEfiPlatformTxtPolicyDataGuid not found! Error when do TxtPei Init.
Loading PEIM at 0x000FFD61D20 EntryPoint=0x000FFD8C5F8 
Loading NV Setup variable.
ScrambleEn = 0x1
CMOS_LTSX_OFFSET(2A)= 0x00: for LT/TPM policy
Emulation Value is: 0!
Running on hardware
InitHeap() 
OemInitSerialDebug() 
Boot Mode check: Mode=1 OK

RC Version: 01400003 
QPI Init starting...


******* QPI Setup Structure *******
PPINrOptIn: 0
Bus   Ratio: 1 1 1 1
IO    Ratio: 1 1 1 1
MMIOL Ratio: 1 1 1 1
LegacyVgaSoc: 0
MmioP2pDis: 0
IsocAzaliaVc1En: 0
DebugPrintLevel: 15
AltRtid2S: 0
ClusterOnDieEn: 0
IBPECIEn: 0
E2EParityEn: 0
EarlySnoopEn: 0
DegradePrecedence: 0
QpiLinkSpeedMode: 1 (FAST)
QpiLinkSpeed: 6
QpiLinkL0pEn: 1
QpiLinkL1En: 1
QpiLinkL0rEn: 2
QpiLbEn: 0
IioUniphyDisable (per socket):   0  0  0  0
QpiLinkCreditReduce: 0
QpiConfigTxWci: 11
QpiCrcMode: 0
QpiCpuSktHotPlugEn: 0
QpiCpuSktHotPlugTopology: 0
QpiSkuMismatchCheck: 1
QpiPortDisable (per port):  S0:0 0 0   S1:0 0 0   S2:0 0 0   S3:0 0 0 
QpiLinkCreditReduce (per port):  S0:0 0 0   S1:0 0 0   S2:0 0 0   S3:0 0 0 
QpiLinkSpeed (per port):  S0:6 6 6   S1:6 6 6   S2:6 6 6   S3:6 6 6 
QpiProbeType (per port):  S0:0 0 0   S1:0 0 0   S2:0 0 0   S3:0 0 0 
QpiConfigTxWci (per port):  S0:11 11 11   S1:11 11 11   S2:11 11 11   S3:11 11 11 
Rsvd (per port):  S0:0 0 0   S1:0 0 0   S2:0 0 0   S3:0 0 0 


******* Common Setup Structure *******
mmCfgBase: 0x80000000 
mmCfgSize: 0x10000000
mmiolBase: 0x90000000 
mmiolSize: 0x6C000000 
mmiohBase: 0x00003800-00000000
mmiohSize: 128 GB 
numaEn: 1 
isocEn: 1 
mesegEn: 0 
dcaEn: 1 


******* Common Var Structure *******
resetRequired: 0 
state: 0 
numCpus: 0 
socketPresentBitMap: 0x01 
busIio: 0x00 0x00 0x00 0x00
busUncore: 0x3F 0x00 0x00 0x00 
mmCfgBase: 0x80000000 


;******* Collecting Early System Information - START *******Checkpoint Code: Socket 0, 0xA1, 0x00, 0x1FFF

    SocketId: 0    CAPID4: 0x04000582
;  SBSP Socket: 0   SKU: 0x04   SubSKU: 0x03   Stepping: 0x04   CAPID4[sbsp]: 0x04000582
;  Total Cbos: 18   Cbo List: 0x3FFFF   Total HA: 02   Total R3Qpi: 02   Total QpiAgent: 03

;  TotCpus: 4  CpuList: 0x0F 
;  busIio:    0x00 0x40 0x80 0xC0 
;  busUncore: 0x3F 0x7F 0xBF 0xFF 
;  Reset Type: Warm Reset   Link Speed: Fast Speed
;******* Collecting Early System Information - END   *******


;******* Setting up Minimum Path - START *******Checkpoint Code: Socket 0, 0xA3, 0x01, 0x0000


; Constructing SBSP minimum path Topology Tree 
; -------------------------------------------- 

; Adding SBSP (CPU0) to the treeCheckpoint Code: Socket 0, 0xA3, 0x02, 0x0020

   CPU0 Link Exchange
   UseQpiPcSts = 1 : LEP0(1,CPU1) : LEP1(1,CPU2) : LEP2(2,CPU3)


; Adding CPU1 to the treeCheckpoint Code: Socket 0, 0xA3, 0x01, 0x0040
Checkpoint Code: Socket 0, 0xA3, 0x05, 0x0040

;   Setting path between SBSP and CPU1. 
;   In SBSP setting route to CPU1 using port 0. 
;   In CPU1 using port 1 to set the R2PCIe route. 


; Adding CPU2 to the treeCheckpoint Code: Socket 0, 0xA3, 0x01, 0x0080
Checkpoint Code: Socket 0, 0xA3, 0x05, 0x0080

;   Setting path between SBSP and CPU2. 
;   In SBSP setting route to CPU2 using port 1. 
;   In CPU2 using port 1 to set the R2PCIe route. 


; Adding CPU3 to the treeCheckpoint Code: Socket 0, 0xA3, 0x01, 0x0100
Checkpoint Code: Socket 0, 0xA3, 0x05, 0x0100

;   Setting path between SBSP and CPU3. 
;   In SBSP setting route to CPU3 using port 2. 
;   In CPU3 using port 2 to set the R2PCIe route. 

    SocketId: 1    CAPID4: 0x04000582Checkpoint Code: Socket 0, 0xA3, 0x02, 0x0040

   CPU1 Link Exchange
   UseQpiPcSts = 1 : LEP0(1,CPU3) : LEP1(0,CPU0) : LEP2(0,CPU2)
Checkpoint Code: Socket 0, 0xA3, 0x03, 0x0040

    SocketId: 2    CAPID4: 0x04000582Checkpoint Code: Socket 0, 0xA3, 0x02, 0x0080

   CPU2 Link Exchange
   UseQpiPcSts = 1 : LEP0(2,CPU1) : LEP1(1,CPU0) : LEP2(0,CPU3)
Checkpoint Code: Socket 0, 0xA3, 0x03, 0x0080

    SocketId: 3    CAPID4: 0x04000582Checkpoint Code: Socket 0, 0xA3, 0x02, 0x0100

   CPU3 Link Exchange
   UseQpiPcSts = 1 : LEP0(2,CPU2) : LEP1(0,CPU1) : LEP2(2,CPU0)
Checkpoint Code: Socket 0, 0xA3, 0x03, 0x0100


;SBSP Minimum Path Tree
;----------------------
;Index  Socket  ParentPort  Hop  ParentIndex
; 00     CPU0    --         0     --
; 01     CPU1    01         1     00
; 02     CPU2    01         1     00
; 03     CPU3    02         1     00
;******* Setting up Minimum Path - END   *******


;******* Initialize MCTP - START *******
;******* Initialize MCTP - END   *******


;******* Check for QPI Topology Degradation - START *******Checkpoint Code: Socket 0, 0xA7, 0x01, 0x1FFF



;Link Exchange Parameter
;-----------------------
;CPU0 : LEP0(1:CPU1) : LEP1(1:CPU2) : LEP2(2:CPU3) 
;CPU1 : LEP0(1:CPU3) : LEP1(0:CPU0) : LEP2(0:CPU2) 
;CPU2 : LEP0(2:CPU1) : LEP1(1:CPU0) : LEP2(0:CPU3) 
;CPU3 : LEP0(2:CPU2) : LEP1(0:CPU1) : LEP2(2:CPU0) 
;  Already Reduced to Supported Topology

;  System will be treated 4S Configuration


;******* Check for QPI Topology Degradation - END *******


;******* Checking QPIRC Input Structure - START *******

;    Sys configuration Type = 1
;******* Checking QPIRC Input Structure - END   *******


;******* Allocate RTIDs - START *******
;    RTIDs Distribution :   TotPerCbo - 06
;    First Pool         :   TotPerCbo - 03   TotExtra - 05   TotAsym - 05
;    Second Pool        :   TotPerCbo - 03   TotExtra - 09   TotAsym - 09

; RTID Allocation Table
; ---------------------

;          Local          Neighbor
;          -----          --------
;         Base  Size    Base  Size

;  First Pool
;  ----------
;  WB      00  01         00  01 
;  UBOX    01  04         01  04 
;  MESEG   00  00         00  00 
;  CBO00   05  03         05  03 
;  CBO01   08  03         08  03 
;  CBO02   11  03         11  03 
;  CBO03   14  03         14  03 
;  CBO04   17  04         17  04 
;  CBO05   21  03         21  03 
;  CBO06   24  03         24  03 
;  CBO07   27  03         27  03 
;  CBO08   30  04         30  04 
;  CBO09   34  03         34  03 
;  CBO10   37  04         37  04 
;  CBO11   41  03         41  03 
;  CBO12   44  04         44  04 
;  CBO13   48  03         48  03 
;  CBO14   51  04         51  04 
;  CBO15   55  03         55  03 
;  CBO16   58  03         58  03 
;  CBO17   61  03         61  03 
;  CBO18   00  00         00  00 
;  CBO19   00  00         00  00 
;  CBO20   00  00         00  00 
;  CBO21   00  00         00  00 
;  CBO22   00  00         00  00 
;  CBO23   00  00         00  00 

;  Second Pool
;  ----------
;  CBO00   01  04         01  04 
;  CBO01   05  03         05  03 
;  CBO02   08  04         08  04 
;  CBO03   12  03         12  03 
;  CBO04   15  03         15  03 
;  CBO05   18  03         18  03 
;  CBO06   21  03         21  03 
;  CBO07   24  04         24  04 
;  CBO08   28  03         28  03 
;  CBO09   31  04         31  04 
;  CBO10   35  03         35  03 
;  CBO11   38  04         38  04 
;  CBO12   42  03         42  03 
;  CBO13   45  04         45  04 
;  CBO14   49  03         49  03 
;  CBO15   52  04         52  04 
;  CBO16   56  03         56  03 
;  CBO17   59  03         59  03 
;  CBO18   00  00         00  00 
;  CBO19   00  00         00  00 
;  CBO20   00  00         00  00 
;  CBO21   00  00         00  00 
;  CBO22   00  00         00  00 
;  CBO23   00  00         00  00 




;******* Allocate RTIDs - END *******


;******* Cacluate Resource Allocation - START *******Checkpoint Code: Socket 0, 0xA9, 0x01, 0x1FFF


;CPU Resource Allocation
;-----------------------
;CPU0   Bus: 0x00 - 0x3F  IO: 0x0000 - 0x3FFF  IOAPIC: 0xFEC00000 - 0xFEC3FFFF  MMIOL: 0x90000000 - 0xABFFFFFF  MMIOH: 0x00003800 00000000 - 0x0000381F FFFFFFFF
;CPU1   Bus: 0x40 - 0x7F  IO: 0x4000 - 0x7FFF  IOAPIC: 0xFEC40000 - 0xFEC7FFFF  MMIOL: 0xAC000000 - 0xC7FFFFFF  MMIOH: 0x00003820 00000000 - 0x0000383F FFFFFFFF
;CPU2   Bus: 0x80 - 0xBF  IO: 0x8000 - 0xBFFF  IOAPIC: 0xFEC80000 - 0xFECBFFFF  MMIOL: 0xC8000000 - 0xE3FFFFFF  MMIOH: 0x00003840 00000000 - 0x0000385F FFFFFFFF
;CPU3   Bus: 0xC0 - 0xFF  IO: 0xC000 - 0xFFFF  IOAPIC: 0xFECC0000 - 0xFECFFFFF  MMIOL: 0xE4000000 - 0xFBFFFFFF  MMIOH: 0x00003860 00000000 - 0x0000387F FFFFFFFF

;******* Cacluate Resource Allocation - END   *******


;******* Check for QPI Topology change across reset - START *******


;******* Check for QPI Topology change across reset - END *******


;******* Phy/Link Updates On Warm Reset - START *******
;  Force unused links to disabled/low power state.
;  Socket 0 QPI Link 0 Freq is currently 96.
;  Socket 0 QPI Link 1 Freq is currently 96.
;  Socket 0 QPI Link 2 Freq is currently 96.
;  Socket 1 QPI Link 0 Freq is currently 96.
;  Socket 1 QPI Link 1 Freq is currently 96.
;  Socket 1 QPI Link 2 Freq is currently 96.
;  Socket 2 QPI Link 0 Freq is currently 96.
;  Socket 2 QPI Link 1 Freq is currently 96.
;  Socket 2 QPI Link 2 Freq is currently 96.
;  Socket 3 QPI Link 0 Freq is currently 96.
;  Socket 3 QPI Link 1 Freq is currently 96.
;  Socket 3 QPI Link 2 Freq is currently 96.
;  System wide QPI Freq is currently 96.
;******* Phy/Link Updates On Warm Reset - END *******


;******* Sync Up PBSPs - START *******
;    Verifying if the remote socket(s) checked-in. 
;******* Sync Up PBSPs - END   *******
;  Wait for mailbox ready
;  Send Data portion of command.  Socket = 0 Data sent == 0x0
;  Send Pcode mailbox command. Socket = 0 Command sent == 0x91
;  Wait for mailbox ready
;  Wait for mailbox ready
;  Send Data portion of command.  Socket = 1 Data sent == 0x0
;  Send Pcode mailbox command. Socket = 1 Command sent == 0x91
;  Wait for mailbox ready
;  Wait for mailbox ready
;  Send Data portion of command.  Socket = 2 Data sent == 0x0
;  Send Pcode mailbox command. Socket = 2 Command sent == 0x91
;  Wait for mailbox ready
;  Wait for mailbox ready
;  Send Data portion of command.  Socket = 3 Data sent == 0x0
;  Send Pcode mailbox command. Socket = 3 Command sent == 0x91
;  Wait for mailbox ready


;******* Program Route Back Table - START *******Checkpoint Code: Socket 0, 0xAA, 0x04, 0x1FFF


; RBT Entries: 
; 000 : 0x00 
; 001 : 0x1F 
; 002 : 0x1F 
; 003 : 0x1F 
; 004 : 0x1F 
; 005 : 0x00 
; 006 : 0x00 
; 007 : 0x00 
; 008 : 0x01 
; 009 : 0x01 
; 010 : 0x01 
; 011 : 0x02 
; 012 : 0x02 
; 013 : 0x02 
; 014 : 0x03 
; 015 : 0x03 
; 016 : 0x03 
; 017 : 0x04 
; 018 : 0x04 
; 019 : 0x04 
; 020 : 0x04 
; 021 : 0x05 
; 022 : 0x05 
; 023 : 0x05 
; 024 : 0x06 
; 025 : 0x06 
; 026 : 0x06 
; 027 : 0x07 
; 028 : 0x07 
; 029 : 0x07 
; 030 : 0x08 
; 031 : 0x08 
; 032 : 0x08 
; 033 : 0x08 
; 034 : 0x09 
; 035 : 0x09 
; 036 : 0x09 
; 037 : 0x0A 
; 038 : 0x0A 
; 039 : 0x0A 
; 040 : 0x0A 
; 041 : 0x0B 
; 042 : 0x0B 
; 043 : 0x0B 
; 044 : 0x0C 
; 045 : 0x0C 
; 046 : 0x0C 
; 047 : 0x0C 
; 048 : 0x0D 
; 049 : 0x0D 
; 050 : 0x0D 
; 051 : 0x0E 
; 052 : 0x0E 
; 053 : 0x0E 
; 054 : 0x0E 
; 055 : 0x0F 
; 056 : 0x0F 
; 057 : 0x0F 
; 058 : 0x10 
; 059 : 0x10 
; 060 : 0x10 
; 061 : 0x11 
; 062 : 0x11 
; 063 : 0x11 
; 064 : 0x00 
; 065 : 0x00 
; 066 : 0x00 
; 067 : 0x00 
; 068 : 0x00 
; 069 : 0x01 
; 070 : 0x01 
; 071 : 0x01 
; 072 : 0x02 
; 073 : 0x02 
; 074 : 0x02 
; 075 : 0x02 
; 076 : 0x03 
; 077 : 0x03 
; 078 : 0x03 
; 079 : 0x04 
; 080 : 0x04 
; 081 : 0x04 
; 082 : 0x05 
; 083 : 0x05 
; 084 : 0x05 
; 085 : 0x06 
; 086 : 0x06 
; 087 : 0x06 
; 088 : 0x07 
; 089 : 0x07 
; 090 : 0x07 
; 091 : 0x07 
; 092 : 0x08 
; 093 : 0x08 
; 094 : 0x08 
; 095 : 0x09 
; 096 : 0x09 
; 097 : 0x09 
; 098 : 0x09 
; 099 : 0x0A 
; 100 : 0x0A 
; 101 : 0x0A 
; 102 : 0x0B 
; 103 : 0x0B 
; 104 : 0x0B 
; 105 : 0x0B 
; 106 : 0x0C 
; 107 : 0x0C 
; 108 : 0x0C 
; 109 : 0x0D 
; 110 : 0x0D 
; 111 : 0x0D 
; 112 : 0x0D 
; 113 : 0x0E 
; 114 : 0x0E 
; 115 : 0x0E 
; 116 : 0x0F 
; 117 : 0x0F 
; 118 : 0x0F 
; 119 : 0x0F 
; 120 : 0x10 
; 121 : 0x10 
; 122 : 0x10 
; 123 : 0x11 
; 124 : 0x11 
; 125 : 0x11 
; 126 : 0x00 
; 127 : 0x00 
;******* Program Route Back Table - END   *******


;******* Topology Dicovery and Optimum Route Calculation - START *******Checkpoint Code: Socket 0, 0xA7, 0x02, 0x1FFF


;  Locating the Rings Present in the Topology

;  No Rings Found

;  Constructing Topology TreeCheckpoint Code: Socket 0, 0xA7, 0x03, 0x1FE0


; Adjacency Table
; ----------------
;S0 P0 VN0 TX (00) :   S1 P1 VN0 RX (17)
;S0 P0 VN0 RX (01) :
;S0 P1 VN0 TX (04) :   S2 P1 VN0 RX (29)
;S0 P1 VN0 RX (05) :
;S0 P2 VN0 TX (08) :   S3 P2 VN0 RX (45)
;S0 P2 VN0 RX (09) :
;S1 P0 VN0 TX (12) :   S3 P1 VN0 RX (41)
;S1 P0 VN0 RX (13) :
;S1 P1 VN0 TX (16) :   S0 P0 VN0 RX (01)
;S1 P1 VN0 RX (17) :
;S1 P2 VN0 TX (20) :   S2 P0 VN0 RX (25)
;S1 P2 VN0 RX (21) :
;S2 P0 VN0 TX (24) :   S1 P2 VN0 RX (21)
;S2 P0 VN0 RX (25) :
;S2 P1 VN0 TX (28) :   S0 P1 VN0 RX (05)
;S2 P1 VN0 RX (29) :
;S2 P2 VN0 TX (32) :   S3 P0 VN0 RX (37)
;S2 P2 VN0 RX (33) :
;S3 P0 VN0 TX (36) :   S2 P2 VN0 RX (33)
;S3 P0 VN0 RX (37) :
;S3 P1 VN0 TX (40) :   S1 P0 VN0 RX (13)
;S3 P1 VN0 RX (41) :
;S3 P2 VN0 TX (44) :   S0 P2 VN0 RX (09)
;S3 P2 VN0 RX (45) :

; Checking for Deadlock...

;CPU0 Topology Tree
;-------------------
;Index  Socket  ParentSocket  ParentPort  ParentIndex  Hop
; 00     CPU0       --            --          --        0
; 01     CPU1      CPU0           01          00        1
; 02     CPU2      CPU0           01          00        1
; 03     CPU3      CPU0           02          00        1

;CPU1 Topology Tree
;-------------------
;Index  Socket  ParentSocket  ParentPort  ParentIndex  Hop
; 00     CPU1       --            --          --        0
; 01     CPU3      CPU1           01          00        1
; 02     CPU0      CPU1           00          00        1
; 03     CPU2      CPU1           00          00        1

;CPU2 Topology Tree
;-------------------
;Index  Socket  ParentSocket  ParentPort  ParentIndex  Hop
; 00     CPU2       --            --          --        0
; 01     CPU1      CPU2           02          00        1
; 02     CPU0      CPU2           01          00        1
; 03     CPU3      CPU2           00          00        1

;CPU3 Topology Tree
;-------------------
;Index  Socket  ParentSocket  ParentPort  ParentIndex  Hop
; 00     CPU3       --            --          --        0
; 01     CPU2      CPU3           02          00        1
; 02     CPU1      CPU3           00          00        1
; 03     CPU0      CPU3           02          00        1
;
"S0 P0 VN0 TX" -> "S1 P1 VN0 RX";
"S0 P1 VN0 TX" -> "S2 P1 VN0 RX";
"S0 P2 VN0 TX" -> "S3 P2 VN0 RX";
;
"S1 P0 VN0 TX" -> "S3 P1 VN0 RX";
"S1 P1 VN0 TX" -> "S0 P0 VN0 RX";
"S1 P2 VN0 TX" -> "S2 P0 VN0 RX";
;
"S2 P0 VN0 TX" -> "S1 P2 VN0 RX";
"S2 P1 VN0 TX" -> "S0 P1 VN0 RX";
"S2 P2 VN0 TX" -> "S3 P0 VN0 RX";
;
"S3 P0 VN0 TX" -> "S2 P2 VN0 RX";
"S3 P1 VN0 TX" -> "S1 P0 VN0 RX";
"S3 P2 VN0 TX" -> "S0 P2 VN0 RX";
; Calculating Route for CPU0 Checkpoint Code: Socket 0, 0xA7, 0x04, 0x0020

; Calculating Route for CPU1 Checkpoint Code: Socket 0, 0xA7, 0x04, 0x0040

; Calculating Route for CPU2 Checkpoint Code: Socket 0, 0xA7, 0x04, 0x0080

; Calculating Route for CPU3 Checkpoint Code: Socket 0, 0xA7, 0x04, 0x0100



;CPU 0 Routing Table
;-------------------
;DestSocket  Port
;   CPU1       0
;   CPU2       1
;   CPU3       2


;CPU 1 Routing Table
;-------------------
;DestSocket  Port
;   CPU0       1
;   CPU2       2
;   CPU3       0


;CPU 2 Routing Table
;-------------------
;DestSocket  Port
;   CPU0       1
;   CPU1       0
;   CPU3       2


;CPU 3 Routing Table
;-------------------
;DestSocket  Port
;   CPU0       2
;   CPU1       1
;   CPU2       0


;******* Topology Dicovery and Optimum Route Calculation - END   *******


;******* Program Optimum Route Table Settings - START *******Checkpoint Code: Socket 0, 0xA8, 0xFF, 0x1FFF

;******* Program Optimum Route Table Settings - END   *******


;******* Program Final IO SAD Setting - START *******Checkpoint Code: Socket 0, 0xA9, 0x02, 0x1FFF
Checkpoint Code: Socket 0, 0xA9, 0x02, 0x1FFF
Checkpoint Code: Socket 0, 0xA9, 0x03, 0x0027
Checkpoint Code: Socket 0, 0xA9, 0x03, 0x0047
Checkpoint Code: Socket 0, 0xA9, 0x03, 0x0087
Checkpoint Code: Socket 0, 0xA9, 0x03, 0x0107

;******* Program Final IO SAD Setting - END   *******


;******* Program Misc. QPI Parameters - START *******Checkpoint Code: Socket 0, 0xAA, 0x05, 0x1FFF

    Lock QPI DFX.
;******* Program Misc. QPI Parameters - END   *******


;******* Program Home Agent Credits - START *******Checkpoint Code: Socket 0, 0xAA, 0x03, 0x1FFF

;******* Program Home Agent Credits - END   *******


;******* Program System Coherency Registers - START *******Checkpoint Code: Socket 0, 0xAE, 0x00, 0x1FFF

;******* Program System Coherency Registers - END   *******


;******* Check for S3 Resume - START *******
;******* Check for S3 Resume - END   *******


;******* Collect Previous Boot Error - START *******
;******* Collect Previous Boot Error - END   *******


******* QPI Output Structure *******
OutLegacyVgaSoc: 0
OutIsocEn: 0
OutMesegEn: 0
OutIsocAzaliaVc1En: 0
OutClusterOnDieEn: 0
OutIBPECIEn: 0
OutE2EParityEn: 0
OutEarlySnoopEn: 0
QpiCurrentLinkSpeedMode: 1 (FAST)
OutQpiLinkSpeed: 5
OutQpiLinkL0pEn: 0
OutQpiLinkL1En: 1
OutQpiLinkL0rEn: 2
OutIioUniphyDisable: 0, 0, 0, 0
OutQpiCrcMode: 0
OutClusterOnDieReduction: 0

QpiInternalGlobal->BtModeEn: 1
QpiInternalGlobal->BtMode: 1
QpiInternalGlobal->BtMode2Alt: 0
QpiInternalGlobal->SnoopFanoutEn: 0
QpiInternalGlobal->SysSnoopMode: 3Checkpoint Code: Socket 0, 0xAF, 0x00, 0x1FFF

;******* QPIRC Exit  *******

QPI Init completed! Reset Requested: 0
SetBIOSInitDone: Setting RST_CPL bit1 everywhere...
BIOS_RST_CPL_1 set on socket 1
BIOS_RST_CPL_1 set on socket 2
BIOS_RST_CPL_1 set on socket 3
BIOS_RST_CPL_1 set on socket 0
SetBIOSInitDone: Clear DMICtrlAutoPmCmplt...
DMICTRL.auto_complete_pm cleared on socket 0
Pipe Init starting...Pass PIPE_DISPATCH_SYNCH_PSYSHOST
Pass PeiPipeSlaveInit
Pass pointer to host
Copy host structure

Synch of host structure to Socket 1 starting...
Pass PIPE_DISPATCH_SYNCH_PSYSHOST
N1 Checked into Pipe
Pass PeiPipeSlaveInit
Pass pointer to host
Copy host structure

Synch of host structure to Socket 2 starting...
Pass PIPE_DISPATCH_SYNCH_PSYSHOST
N2 Checked into Pipe
Pass PeiPipeSlaveInit
Pass pointer to host
Copy host structure

Synch of host structure to Socket 3 starting...
Pipe Init completed! Reset Requested: 0
N3 Checked into Pipe
CPU Feature Early Config starting...
Config IOT/OCLA Start: resetRequired = 0 

Config IOT/OCLA end. resetRequired = 0 
CPU miscellaneous configuration...
CPUMISC Current socket:         00
PcodeMailboxStatus = 0,  PCU_MISC_CONFIG  = 9840000
CPUMISC Current socket:         01
PcodeMailboxStatus = 0,  PCU_MISC_CONFIG  = 9840000
CPUMISC Current socket:         02
PcodeMailboxStatus = 0,  PCU_MISC_CONFIG  = 9840000
CPUMISC Current socket:         03
PcodeMailboxStatus = 0,  PCU_MISC_CONFIG  = 9840000
completed!
CPU Feature Early Config completed! Reset Requested: 0
Collect Previous Boot errors - start

CpuType = 0, CpuSubType = 2

MemoryQpiInitHsxlib: CPU_HSX_EX, CPU_BDX_EX
PrevBootErrors - Valid MCA UC entries: 0
Collect Previous Boot errors - end
START_MRC_RUN

sizeof sysHost = 286634

sizeof sysVar = 73483

sizeof memVar = 41569

sizeof cpuVar = 600

sizeof qpi_host_out = 494

sizeof commonVar = 1636

sizeof sysNvram = 208995

sizeof cpuNvram = 20

sizeof memNvram = 1505

sizeof qpiNvram = 56

sizeof commonNvram = 207414

sizeof commonImcNvram = 25925

sizeof nodeIMC = 3856

sizeof ddrChannel = 825

sizeof vmseChannelNvram = 2407

sizeof channelNvram = 5134

sizeof jckddrvar = 32076

sizeof sysHostSetup = 1698

struct sysHost.common {
  options:         00000005
      PROMOTE_WARN_EN         1
      PROMOTE_MRC_WARN_EN     0
      HALT_ON_ERROR_EN        1
  lowGap:          20
  highGap:         01
  serialDebugMsgLvl:0012
  bsdBreakpoint:   00
  maxAddrMem:      40000
  debugPort:       80
  nvramPtr:        00000000
  sysHostBufferPtr:00000000
  mmCfgBase:       80000000
  mmCfgSize:       10000000
  mmiohSize:       00000080
  pchumaEn:        00
  numaEn:          01
  isocEn:          01
  dcaEn:           01
  bdatEn:          00
  consoleComPort:  3F8
  ptrrSupport      01

struct sysHost.setup.mem {
  options:         C990DEA8
      TEMPHIGH_EN              0
      PDWN_IBT_OFF_EN          0
      PDWN_SR_CKE_MODE         0
      OPP_SELF_REF_EN          1
      MDLL_SHUT_DOWN_EN        0
      PAGE_POLICY              1
      ALLOW2XREF_EN            0
      MULTI_THREAD_MRC_EN      1
      ADAPTIVE_PAGE_EN         0
      CMD_CLK_TRAINING_EN      1
      SCRAMBLE_EN              1
      NUMA_AWARE               1
      ECC_CHECK_EN             1
      BALANCED_4WAY_EN         0
      CA_PARITY_EN             1
      SPLIT_BELOW_4GB_EN       0
      MARGIN_RANKS_EN          1
      MEMORY_TEST_FAST_BOOT_EN 1
      ATTEMPT_FAST_BOOT        0
      ZQ_CALIBRATION_EN        1
      PC6_CMD_ADDR_STANDBY_EN  0
      PROC_EIST_EN  1
      LRD_SUBRNK_C2CAS_TIM_EN  1
      DIMM_LRDIMM_3DS_SUPPORT  0
      PROMOTE_MEM_TRAIN_ERRORS 0
      PROMOTE_MEM_RAS_WARNINGS 0
      VMSE_CLOCK_STOP_EN 1
      SAFE_MC_BGF_PSV_EN            1

  options2:         16B003BA
      ADR_SUPPORT_EN                0
      HA_EARLY_WRITE_POST_EN        1
      MC_CHANNEL_HASH_MODE          0
      UNUSED_MEM_CHANNEL_INPUTS_EN  1
      PDA_EN                        0
      READ_VREF_CENTER_EN           1
      WRITE_VREF_CENTER_EN          1
      CMD_2_DATA_TUNING             1
      THERMAL_SENSOR_EN             1
      CATASTROPHIC_TRIP_EN          1
      VUNIT_CLOCK_GATING_EN         0
      TUNIT_CLOCK_GATING_EN         0
      MUNIT_CLOCK_GATING_EN         0
      DUNIT_CLOCK_GATING_EN         0
      CPGC_MEMORY_TEST_EN           0
      CPGC_MEMORY_ECC_EN            1
      OPP_READ_DURING_WMM           0
      PSMI_SUPPORT_EN               0
      JCK_PWR_MGMT_EN               0
      DISPLAY_EYE_EN   0
      ADVANCED_CLK_TRAINING         0
      RXVREF_PERSTROBE_TRAINING     0
      ADVANCED_STROBE_CENTERING     1
      ODT TIMING MODE               1
      EXT_DIMM_VREF_CIRCUIT         0
      BIOS_VMSE_RESET               1
      JCK_SAVE_ERRLOGS              0
      JKT_ERROR_FLOW                0
      VMSE_DISABLE_RCOMP            0
      MXB_RANK_SHARING_MODE         1
      JCK PER DIMM PARITY ERROR EN  0
      DDR4_DIMM_ISOLATION_ENABLE    0

  vmseOptions:         0000E041
      VMSE_MODE_2_1             1
      VMSE_PREAMBLE_2UI         0
      SAFE_TURN_AROUND_TIMINGS  0
      VMSE_RANK_MARGIN_TOOL_EN  0
      VMT Pattern Length (loop count)  00
      VMSE_NB_PERST_EN          0
      VMSE_SB_PERST_EN          1
      RESTORE_VMSE_TRAININGS_ON_FAST_BOOT          0
      VMSE_DATA_SCRAMBLING_EN  1
      VMSE_CMD_SCRAMBLING_EN   1
      VMSE_CMD_SCR_ON_RETRY_EN 1

  RASmodeEx:       06
      DEVTAGGING_EN        0
      Bank SDDC_EN        0
      DMNDSCRB_EN        1
      PTRLSCRB_EN        1
      DDDC_EN            0
      Bank DDDC_EN       0
      A7_MODE            0
      DDDC_WIREKILL      0
      GLOBAL_RAS_POLICY  0

  RASmode:         00
      RK_SPARE             0
      CH_LOCKSTEP          0
      CH_MIRROR            0

struct sysHost.setup.mem {
  VMSE PI Increment:        02
  VMSE VREF Increment:      04
  enforcePOR:      00
  ddrFreqLimit:    00
  nodeInter:       02
  chInter:         04
  rankInter:       08
  dimmTypeSupport: 02
  pdwnCkMode:      00
  MemPwrSave:      01
  ckeThrottling:   01
  olttPeakBWLIMITPercent: 00
  thermalThrottlingOptions:  08
      CLTT_EN             1
      MH_OUTPUT_EN        0
      MH_SENSE_EN         0
  dramraplen:      02
  dramraplbwlimittf: 01
  dramraplRefreshBase: 0A
  dramMaint: 02
  electricalThrottling:  00
  forceRankMult:   00
  lrdimmModuleDelay: 01
  cmdClkEyeWidth:  64
  rmtPatternLength:0F
  patrolScrubDuration:18
  spareErrTh:      0x7FFF
  WirekillRankTh:  0x02
  leakyBktLo:      0x28
  leakyBktHi:      0x29
  scrambleSeedLow: 00000000
  scrambleSeedHigh:00000000
  check_pm_sts:    00
  check_platform_detect: 00
  pushtoCasLatency:        0x16
  phaseShedding:           0x01
  laiMode:                 0x00
  tolm:                    0x01
  mcODTOverride:           0x00
  numSparTrans:            0x0004
  earlyCmdTraining:        0x01
  nbErrTh:             0xFF
  sbErrTh:                 0x1FFF
  vmseLinkFailTh:          0x07
  migrationSpareMask       0x00
  memMirroringMode:        0x00
  memMirorEnableMap:       0x00
      MIRROR_SCRUB     1
  partialMirrorSize[00] = 0001 [64MB] 
  struct ddrIMCSetup[00] {
    enabled:        00000001
    ddrVddLimit:    00
    struct ddrChannelSetup[00] {
      enabled:       01
      batterybacked: 00
      rankMask:      FF
      numDimmSlots:  03
      struct ddrDimmSetup[00] {
        mapOut[00]: 00
        mapOut[01]: 00
        mapOut[02]: 00
        mapOut[03]: 00
    };
      struct ddrDimmSetup[01] {
        mapOut[00]: 00
        mapOut[01]: 00
        mapOut[02]: 00
        mapOut[03]: 00
    };
      struct ddrDimmSetup[02] {
        mapOut[00]: 00
        mapOut[01]: 00
        mapOut[02]: 00
        mapOut[03]: 00
    };
    };
    struct ddrChannelSetup[01] {
      enabled:       01
      batterybacked: 00
      rankMask:      FF
      numDimmSlots:  03
      struct ddrDimmSetup[00] {
        mapOut[00]: 00
        mapOut[01]: 00
        mapOut[02]: 00
        mapOut[03]: 00
    };
      struct ddrDimmSetup[01] {
        mapOut[00]: 00
        mapOut[01]: 00
        mapOut[02]: 00
        mapOut[03]: 00
    };
      struct ddrDimmSetup[02] {
        mapOut[00]: 00
        mapOut[01]: 00
        mapOut[02]: 00
        mapOut[03]: 00
    };
    };
    struct ddrChannelSetup[02] {
      enabled:       01
      batterybacked: 00
      rankMask:      FF
      numDimmSlots:  03
      struct ddrDimmSetup[00] {
        mapOut[00]: 00
        mapOut[01]: 00
        mapOut[02]: 00
        mapOut[03]: 00
    };
      struct ddrDimmSetup[01] {
        mapOut[00]: 00
        mapOut[01]: 00
        mapOut[02]: 00
        mapOut[03]: 00
    };
      struct ddrDimmSetup[02] {
        mapOut[00]: 00
        mapOut[01]: 00
        mapOut[02]: 00
        mapOut[03]: 00
    };
    };
    struct ddrChannelSetup[03] {
      enabled:       01
      batterybacked: 00
      rankMask:      FF
      numDimmSlots:  03
      struct ddrDimmSetup[00] {
        mapOut[00]: 00
        mapOut[01]: 00
        mapOut[02]: 00
        mapOut[03]: 00
    };
      struct ddrDimmSetup[01] {
        mapOut[00]: 00
        mapOut[01]: 00
        mapOut[02]: 00
        mapOut[03]: 00
    };
      struct ddrDimmSetup[02] {
        mapOut[00]: 00
        mapOut[01]: 00
        mapOut[02]: 00
        mapOut[03]: 00
    };
    };
  partialMirrorSize[01] = 0001 [64MB] 
  struct ddrIMCSetup[01] {
    enabled:        00000001
    ddrVddLimit:    00
    struct ddrChannelSetup[00] {
      enabled:       01
      batterybacked: 00
      rankMask:      FF
      numDimmSlots:  03
      struct ddrDimmSetup[00] {
        mapOut[00]: 00
        mapOut[01]: 00
        mapOut[02]: 00
        mapOut[03]: 00
    };
      struct ddrDimmSetup[01] {
        mapOut[00]: 00
        mapOut[01]: 00
        mapOut[02]: 00
        mapOut[03]: 00
    };
      struct ddrDimmSetup[02] {
        mapOut[00]: 00
        mapOut[01]: 00
        mapOut[02]: 00
        mapOut[03]: 00
    };
    };
    struct ddrChannelSetup[01] {
      enabled:       01
      batterybacked: 00
      rankMask:      FF
      numDimmSlots:  03
      struct ddrDimmSetup[00] {
        mapOut[00]: 00
        mapOut[01]: 00
        mapOut[02]: 00
        mapOut[03]: 00
    };
      struct ddrDimmSetup[01] {
        mapOut[00]: 00
        mapOut[01]: 00
        mapOut[02]: 00
        mapOut[03]: 00
    };
      struct ddrDimmSetup[02] {
        mapOut[00]: 00
        mapOut[01]: 00
        mapOut[02]: 00
        mapOut[03]: 00
    };
    };
    struct ddrChannelSetup[02] {
      enabled:       01
      batterybacked: 00
      rankMask:      FF
      numDimmSlots:  03
      struct ddrDimmSetup[00] {
        mapOut[00]: 00
        mapOut[01]: 00
        mapOut[02]: 00
        mapOut[03]: 00
    };
      struct ddrDimmSetup[01] {
        mapOut[00]: 00
        mapOut[01]: 00
        mapOut[02]: 00
        mapOut[03]: 00
    };
      struct ddrDimmSetup[02] {
        mapOut[00]: 00
        mapOut[01]: 00
        mapOut[02]: 00
        mapOut[03]: 00
    };
    };
    struct ddrChannelSetup[03] {
      enabled:       01
      batterybacked: 00
      rankMask:      FF
      numDimmSlots:  03
      struct ddrDimmSetup[00] {
        mapOut[00]: 00
        mapOut[01]: 00
        mapOut[02]: 00
        mapOut[03]: 00
    };
      struct ddrDimmSetup[01] {
        mapOut[00]: 00
        mapOut[01]: 00
        mapOut[02]: 00
        mapOut[03]: 00
    };
      struct ddrDimmSetup[02] {
        mapOut[00]: 00
        mapOut[01]: 00
        mapOut[02]: 00
        mapOut[03]: 00
    };
    };
  };
}; //struct sysHost.setup

CPU Frequency: 0  2500 (MHz)
N0: warm reset bit is not set, force ColdBoot.
N0: Clearing the MRC NVRAM structure.
N0: nvram node enabled = 0x1
N1: warm reset bit is not set, force ColdBoot.
N1: nvram node enabled = 0x1
bootMode = NormalBoot. Taking the normal boot path through MRC.
subBootMode = ColdBoot. Taking the cold boot sub-path through MRC.
CPU type is CPU_HSX and stepping is D0_REV_HSX: Apply all HSX D0/E0 WAs
Checkpoint Code: Socket 0, 0xB0, 0x02, 0x0000
Checkpoint Code: Socket 0, 0xB0, 0x10, 0x0000
N0: InitMemoryRiser: Stage 0 - Init VPP
N0: InitMemoryRiser: Read Initial SLTCON Data = 0x3C0
N0: InitMemoryRiser: slotCon.Bits.power_controller_control = 0, slotCon.Bits.power_indicator_control = 1
N0: InitMemoryRiser: Write SLTCON Data = 0x1E5
N0: InitMemoryRiser: Initialize hotplug events 
N1: InitMemoryRiser: Read Initial SLTCON Data = 0x3C0
N0: InitMemoryRiser: slotCon.Bits.power_controller_control = 0, slotCon.Bits.power_indicator_control = 1
N1: InitMemoryRiser: Write SLTCON Data = 0x1E5
N1: InitMemoryRiser: Initialize hotplug events 
N0: InitMemoryRiser: vpp enabled set. Skip update. vppMemN1org Data = 0x3
Checkpoint Code: Socket 0, 0xB0, 0x11, 0x0000
N0: InitMemoryRiser: Stage 1 - Init SLTCon
N0: InitMemoryRiser: Read Initial SLTCON Data = 0x1E5
Checkpoint Code: Socket 0, 0xB0, 0x11, 0x0000
N1: InitMemoryRiser: Stage 1 - Init SLTCon
N1: InitMemoryRiser: Read Initial SLTCON Data = 0x1E5
Checkpoint Code: Socket 0, 0xB0, 0x14, 0x0000
N0: InitMemoryRiser: Power Enable Good detection
N0: InitMemoryRiser: Power Enable Good
Checkpoint Code: Socket 0, 0xB0, 0x14, 0x0000
N1: InitMemoryRiser: Power Enable Good detection
N1: InitMemoryRiser: Power Enable Good
Checkpoint Code: Socket 0, 0xB0, 0x04, 0x0001
N0: VmseResetViaVpp: Write SLTCON Data = 0x9E5
N0: VmseResetViaVpp: Write SLTCON Data = 0x1E5
N1: VmseResetViaVpp: Write SLTCON Data = 0x9E5
N1: VmseResetViaVpp: Write SLTCON Data = 0x1E5
Multi-Threaded MRC Init
Dispatch S1 for mem init
Skt1 Entering MRC

sizeof sysHost = 286634

sizeof sysVar = 73483

sizeof memVar = 41569

sizeof cpuVar = 600

sizeof qpi_host_out = 494

sizeof commonVar = 1636

sizeof sysNvram = 208995

sizeof cpuNvram = 20

sizeof memNvram = 1505

sizeof qpiNvram = 56

sizeof commonNvram = 207414

sizeof commonImcNvram = 25925

sizeof nodeIMC = 3856

sizeof ddrChannel = 825

sizeof vmseChannelNvram = 2407

sizeof channelNvram = 5134

sizeof jckddrvar = 32076

sizeof sysHostSetup = 1698

struct sysHost.common {
  options:         00000005
      PROMOTE_WARN_EN         1
      PROMOTE_MRC_WARN_EN     0
      HALT_ON_ERROR_EN        1
  lowGap:          20
  highGap:         01
  serialDebugMsgLvl:0012
  bsdBreakpoint:   00
  maxAddrMem:      40000
  debugPort:       80
  nvramPtr:        00000000
  sysHostBufferPtr:00000000
  mmCfgBase:       80000000
  mmCfgSize:       10000000
  mmiohSize:       00000080
  pchumaEn:        00
  numaEn:          01
  isocEn:          01
  dcaEn:           01
  bdatEn:          00
  consoleComPort:  3F8
  ptrrSupport      01

struct sysHost.setup.mem {
  options:         C990DEA8
      TEMPHIGH_EN              0
      PDWN_IBT_OFF_EN          0
      PDWN_SR_CKE_MODE         0
      OPP_SELF_REF_EN          1
      MDLL_SHUT_DOWN_EN        0
      PAGE_POLICY              1
      ALLOW2XREF_EN            0
      MULTI_THREAD_MRC_EN      1
      ADAPTIVE_PAGE_EN         0
      CMD_CLK_TRAINING_EN      1
      SCRAMBLE_EN              1
      NUMA_AWARE               1
      ECC_CHECK_EN             1
      BALANCED_4WAY_EN         0
      CA_PARITY_EN             1
      SPLIT_BELOW_4GB_EN       0
      MARGIN_RANKS_EN          1
      MEMORY_TEST_FAST_BOOT_EN 1
      ATTEMPT_FAST_BOOT        0
      ZQ_CALIBRATION_EN        1
      PC6_CMD_ADDR_STANDBY_EN  0
      PROC_EIST_EN  1
      LRD_SUBRNK_C2CAS_TIM_EN  1
      DIMM_LRDIMM_3DS_SUPPORT  0
      PROMOTE_MEM_TRAIN_ERRORS 0
      PROMOTE_MEM_RAS_WARNINGS 0
      VMSE_CLOCK_STOP_EN 1
      SAFE_MC_BGF_PSV_EN            1

  options2:         16B003BA
      ADR_SUPPORT_EN                0
      HA_EARLY_WRITE_POST_EN        1
      MC_CHANNEL_HASH_MODE          0
      UNUSED_MEM_CHANNEL_INPUTS_EN  1
      PDA_EN                        0
      READ_VREF_CENTER_EN           1
      WRITE_VREF_CENTER_EN          1
      CMD_2_DATA_TUNING             1
      THERMAL_SENSOR_EN             1
      CATASTROPHIC_TRIP_EN          1
      VUNIT_CLOCK_GATING_EN         0
      TUNIT_CLOCK_GATING_EN         0
      MUNIT_CLOCK_GATING_EN         0
      DUNIT_CLOCK_GATING_EN         0
      CPGC_MEMORY_TEST_EN           0
      CPGC_MEMORY_ECC_EN            1
      OPP_READ_DURING_WMM           0
      PSMI_SUPPORT_EN               0
      JCK_PWR_MGMT_EN               0
      DISPLAY_EYE_EN   0
      ADVANCED_CLK_TRAINING         0
      RXVREF_PERSTROBE_TRAINING     0
      ADVANCED_STROBE_CENTERING     1
      ODT TIMING MODE               1
      EXT_DIMM_VREF_CIRCUIT         0
      BIOS_VMSE_RESET               1
      JCK_SAVE_ERRLOGS              0
      JKT_ERROR_FLOW                0
      VMSE_DISABLE_RCOMP            0
      MXB_RANK_SHARING_MODE         1
      JCK PER DIMM PARITY ERROR EN  0
      DDR4_DIMM_ISOLATION_ENABLE    0

  vmseOptions:         0000E041
      VMSE_MODE_2_1             1
      VMSE_PREAMBLE_2UI         0
      SAFE_TURN_AROUND_TIMINGS  0
      VMSE_RANK_MARGIN_TOOL_EN  0
      VMT Pattern Length (loop count)  00
      VMSE_NB_PERST_EN          0
      VMSE_SB_PERST_EN          1
      RESTORE_VMSE_TRAININGS_ON_FAST_BOOT          0
      VMSE_DATA_SCRAMBLING_EN  1
      VMSE_CMD_SCRAMBLING_EN   1
      VMSE_CMD_SCR_ON_RETRY_EN 1

  RASmodeEx:       06
      DEVTAGGING_EN        0
      Bank SDDC_EN        0
      DMNDSCRB_EN        1
      PTRLSCRB_EN        1
      DDDC_EN            0
      Bank DDDC_EN       0
      A7_MODE            0
      DDDC_WIREKILL      0
      GLOBAL_RAS_POLICY  0

  RASmode:         00
      RK_SPARE             0
      CH_LOCKSTEP          0
      CH_MIRROR            0

struct sysHost.setup.mem {
  VMSE PI Increment:        02
  VMSE VREF Increment:      04
  enforcePOR:      00
  ddrFreqLimit:    00
  nodeInter:       02
  chInter:         04
  rankInter:       08
  dimmTypeSupport: 02
  pdwnCkMode:      00
  MemPwrSave:      01
  ckeThrottling:   01
  olttPeakBWLIMITPercent: 00
  thermalThrottlingOptions:  08
      CLTT_EN             1
      MH_OUTPUT_EN        0
      MH_SENSE_EN         0
  dramraplen:      02
  dramraplbwlimittf: 01
  dramraplRefreshBase: 0A
  dramMaint: 02
  electricalThrottling:  00
  forceRankMult:   00
  lrdimmModuleDelay: 01
  cmdClkEyeWidth:  64
  rmtPatternLength:0F
  patrolScrubDuration:18
  spareErrTh:      0x7FFF
  WirekillRankTh:  0x02
  leakyBktLo:      0x28
  leakyBktHi:      0x29
  scrambleSeedLow: 00000000
  scrambleSeedHigh:00000000
  check_pm_sts:    00
  check_platform_detect: 00
  pushtoCasLatency:        0x16
  phaseShedding:           0x01
  laiMode:                 0x00
  tolm:                    0x01
  mcODTOverride:           0x00
  numSparTrans:            0x0004
  earlyCmdTraining:        0x01
  nbErrTh:             0xFF
  sbErrTh:                 0x1FFF
  vmseLinkFailTh:          0x07
  migrationSpareMask       0x00
  memMirroringMode:        0x00
  memMirorEnableMap:       0x00
      MIRROR_SCRUB     1
  partialMirrorSize[02] = 0001 [64MB] 
  struct ddrIMCSetup[02] {
    enabled:        00000001
    ddrVddLimit:    00
    struct ddrChannelSetup[00] {
      enabled:       01
      batterybacked: 00
      rankMask:      FF
      numDimmSlots:  03
      struct ddrDimmSetup[00] {
        mapOut[00]: 00
        mapOut[01]: 00
        mapOut[02]: 00
        mapOut[03]: 00
    };
      struct ddrDimmSetup[01] {
        mapOut[00]: 00
        mapOut[01]: 00
        mapOut[02]: 00
        mapOut[03]: 00
    };
      struct ddrDimmSetup[02] {
        mapOut[00]: 00
        mapOut[01]: 00
        mapOut[02]: 00
        mapOut[03]: 00
    };
    };
    struct ddrChannelSetup[01] {
      enabled:       01
      batterybacked: 00
      rankMask:      FF
      numDimmSlots:  03
      struct ddrDimmSetup[00] {
        mapOut[00]: 00
        mapOut[01]: 00
        mapOut[02]: 00
        mapOut[03]: 00
    };
      struct ddrDimmSetup[01] {
        mapOut[00]: 00
        mapOut[01]: 00
        mapOut[02]: 00
        mapOut[03]: 00
    };
      struct ddrDimmSetup[02] {
        mapOut[00]: 00
        mapOut[01]: 00
        mapOut[02]: 00
        mapOut[03]: 00
    };
    };
    struct ddrChannelSetup[02] {
      enabled:       01
      batterybacked: 00
      rankMask:      FF
      numDimmSlots:  03
      struct ddrDimmSetup[00] {
        mapOut[00]: 00
        mapOut[01]: 00
        mapOut[02]: 00
        mapOut[03]: 00
    };
      struct ddrDimmSetup[01] {
        mapOut[00]: 00
        mapOut[01]: 00
        mapOut[02]: 00
        mapOut[03]: 00
    };
      struct ddrDimmSetup[02] {
        mapOut[00]: 00
        mapOut[01]: 00
        mapOut[02]: 00
        mapOut[03]: 00
    };
    };
    struct ddrChannelSetup[03] {
      enabled:       01
      batterybacked: 00
      rankMask:      FF
      numDimmSlots:  03
      struct ddrDimmSetup[00] {
        mapOut[00]: 00
        mapOut[01]: 00
        mapOut[02]: 00
        mapOut[03]: 00
    };
      struct ddrDimmSetup[01] {
        mapOut[00]: 00
        mapOut[01]: 00
        mapOut[02]: 00
        mapOut[03]: 00
    };
      struct ddrDimmSetup[02] {
        mapOut[00]: 00
        mapOut[01]: 00
        mapOut[02]: 00
        mapOut[03]: 00
    };
    };
  partialMirrorSize[03] = 0001 [64MB] 
  struct ddrIMCSetup[03] {
    enabled:        00000001
    ddrVddLimit:    00
    struct ddrChannelSetup[00] {
      enabled:       01
      batterybacked: 00
      rankMask:      FF
      numDimmSlots:  03
      struct ddrDimmSetup[00] {
        mapOut[00]: 00
        mapOut[01]: 00
        mapOut[02]: 00
        mapOut[03]: 00
    };
      struct ddrDimmSetup[01] {
        mapOut[00]: 00
        mapOut[01]: 00
        mapOut[02]: 00
        mapOut[03]: 00
    };
      struct ddrDimmSetup[02] {
        mapOut[00]: 00
        mapOut[01]: 00
        mapOut[02]: 00
        mapOut[03]: 00
    };
    };
    struct ddrChannelSetup[01] {
      enabled:       01
      batterybacked: 00
      rankMask:      FF
      numDimmSlots:  03
      struct ddrDimmSetup[00] {
        mapOut[00]: 00
        mapOut[01]: 00
        mapOut[02]: 00
        mapOut[03]: 00
    };
      struct ddrDimmSetup[01] {
        mapOut[00]: 00
        mapOut[01]: 00
        mapOut[02]: 00
        mapOut[03]: 00
    };
      struct ddrDimmSetup[02] {
        mapOut[00]: 00
        mapOut[01]: 00
        mapOut[02]: 00
        mapOut[03]: 00
    };
    };
    struct ddrChannelSetup[02] {
      enabled:       01
      batterybacked: 00
      rankMask:      FF
      numDimmSlots:  03
      struct ddrDimmSetup[00] {
        mapOut[00]: 00
        mapOut[01]: 00
        mapOut[02]: 00
        mapOut[03]: 00
    };
      struct ddrDimmSetup[01] {
        mapOut[00]: 00
        mapOut[01]: 00
        mapOut[02]: 00
        mapOut[03]: 00
    };
      struct ddrDimmSetup[02] {
        mapOut[00]: 00
        mapOut[01]: 00
        mapOut[02]: 00
        mapOut[03]: 00
    };
    };
    struct ddrChannelSetup[03] {
      enabled:       01
      batterybacked: 00
      rankMask:      FF
      numDimmSlots:  03
      struct ddrDimmSetup[00] {
        mapOut[00]: 00
        mapOut[01]: 00
        mapOut[02]: 00
        mapOut[03]: 00
    };
      struct ddrDimmSetup[01] {
        mapOut[00]: 00
        mapOut[01]: 00
        mapOut[02]: 00
        mapOut[03]: 00
    };
      struct ddrDimmSetup[02] {
        mapOut[00]: 00
        mapOut[01]: 00
        mapOut[02]: 00
        mapOut[03]: 00
    };
    };
  };
}; //struct sysHost.setup

CPU Frequency: 0  2500 (MHz)
N2: warm reset bit is not set, force ColdBoot.
N2: Clearing the MRC NVRAM structure.
N2: nvram node enabled = 0x1
N3: warm reset bit is not set, force ColdBoot.
N3: nvram node enabled = 0x1
bootMode = NormalBoot. Taking the normal boot path through MRC.
subBootMode = ColdBoot. Taking the cold boot sub-path through MRC.
CPU type is CPU_HSX and stepping is D0_REV_HSX: Apply all HSX D0/E0 WAs
N2: InitMemoryRiser: Stage 0 - Init VPP
N2: InitMemoryRiser: Read Initial SLTCON Data = 0x3C0
N2: InitMemoryRiser: slotCon.Bits.power_controller_control = 0, slotCon.Bits.power_indicator_control = 1
N2: InitMemoryRiser: Write SLTCON Data = 0x1E5
N2: InitMemoryRiser: Initialize hotplug events 
N3: InitMemoryRiser: Read Initial SLTCON Data = 0x3C0
N2: InitMemoryRiser: slotCon.Bits.power_controller_control = 0, slotCon.Bits.power_indicator_control = 1
N3: InitMemoryRiser: Write SLTCON Data = 0x1E5
N3: InitMemoryRiser: Initialize hotplug events 
N2: InitMemoryRiser: vpp enabled set. Skip update. vppMemN1org Data = 0x3
N2: InitMemoryRiser: Stage 1 - Init SLTCon
N2: InitMemoryRiser: Read Initial SLTCON Data = 0x1E5
N3: InitMemoryRiser: Stage 1 - Init SLTCon
N3: InitMemoryRiser: Read Initial SLTCON Data = 0x1E5
N2: InitMemoryRiser: Power Enable Good detection
N2: InitMemoryRiser: Power Enable Good
N3: InitMemoryRiser: Power Enable Good detection
N3: InitMemoryRiser: Power Enable Good
N2: VmseResetViaVpp: Write SLTCON Data = 0x9E5
N2: VmseResetViaVpp: Write SLTCON Data = 0x1E5
N3: VmseResetViaVpp: Write SLTCON Data = 0x9E5
N3: VmseResetViaVpp: Write SLTCON Data = 0x1E5
Dispatch S2 for mem init
N2: Init Throttling (Early)
Skt2 Entering MRC
N2: Detect DIMM Config

sizeof sysHost = 286634

sizeof sysVar = 73483

sizeof memVar = 41569

sizeof cpuVar = 600

sizeof qpi_host_out = 494

sizeof commonVar = 1636

sizeof sysNvram = 208995

sizeof cpuNvram = 20

sizeof memNvram = 1505

sizeof qpiNvram = 56

sizeof commonNvram = 207414

sizeof commonImcNvram = 25925

sizeof nodeIMC = 3856

sizeof ddrChannel = 825

sizeof vmseChannelNvram = 2407

sizeof channelNvram = 5134

sizeof jckddrvar = 32076

sizeof sysHostSetup = 1698

struct sysHost.common {
  options:         00000005
      PROMOTE_WARN_EN         1
      PROMOTE_MRC_WARN_EN     0
      HALT_ON_ERROR_EN        1
  lowGap:          20
  highGap:         01
  serialDebugMsgLvl:0012
  bsdBreakpoint:   00
  maxAddrMem:      40000
  debugPort:       80
  nvramPtr:        00000000
  sysHostBufferPtr:00000000
  mmCfgBase:       80000000
  mmCfgSize:       10000000
  mmiohSize:       00000080
  pchumaEn:        00
  numaEn:          01
  isocEn:          01
  dcaEn:           01
  bdatEn:          00
  consoleComPort:  3F8
  ptrrSupport      01

struct sysHost.setup.mem {
  options:         C990DEA8
      TEMPHIGH_EN              0
      PDWN_IBT_OFF_EN          0
      PDWN_SR_CKE_MODE         0
      OPP_SELF_REF_EN          1
      MDLL_SHUT_DOWN_EN        0
      PAGE_POLICY              1
      ALLOW2XREF_EN            0
      MULTI_THREAD_MRC_EN      1
      ADAPTIVE_PAGE_EN         0
      CMD_CLK_TRAINING_EN      1
      SCRAMBLE_EN              1
      NUMA_AWARE               1
      ECC_CHECK_EN             1
      BALANCED_4WAY_EN         0
      CA_PARITY_EN             1
      SPLIT_BELOW_4GB_EN       0
      MARGIN_RANKS_EN          1
      MEMORY_TEST_FAST_BOOT_EN 1
      ATTEMPT_FAST_BOOT        0
      ZQ_CALIBRATION_EN        1
      PC6_CMD_ADDR_STANDBY_EN  0
      PROC_EIST_EN  1
      LRD_SUBRNK_C2CAS_TIM_EN  1
      DIMM_LRDIMM_3DS_SUPPORT  0
      PROMOTE_MEM_TRAIN_ERRORS 0
      PROMOTE_MEM_RAS_WARNINGS 0
      VMSE_CLOCK_STOP_EN 1
      SAFE_MC_BGF_PSV_EN            1

  options2:         16B003BA
      ADR_SUPPORT_EN                0
      HA_EARLY_WRITE_POST_EN        1
      MC_CHANNEL_HASH_MODE          0
      UNUSED_MEM_CHANNEL_INPUTS_EN  1
      PDA_EN                        0
      READ_VREF_CENTER_EN           1
      WRITE_VREF_CENTER_EN          1
      CMD_2_DATA_TUNING             1
      THERMAL_SENSOR_EN             1
      CATASTROPHIC_TRIP_EN          1
      VUNIT_CLOCK_GATING_EN         0
      TUNIT_CLOCK_GATING_EN         0
      MUNIT_CLOCK_GATING_EN         0
      DUNIT_CLOCK_GATING_EN         0
      CPGC_MEMORY_TEST_EN           0
      CPGC_MEMORY_ECC_EN            1
      OPP_READ_DURING_WMM           0
      PSMI_SUPPORT_EN               0
      JCK_PWR_MGMT_EN               0
      DISPLAY_EYE_EN   0
      ADVANCED_CLK_TRAINING         0
      RXVREF_PERSTROBE_TRAINING     0
      ADVANCED_STROBE_CENTERING     1
      ODT TIMING MODE               1
      EXT_DIMM_VREF_CIRCUIT         0
      BIOS_VMSE_RESET               1
      JCK_SAVE_ERRLOGS              0
      JKT_ERROR_FLOW                0
      VMSE_DISABLE_RCOMP            0
      MXB_RANK_SHARING_MODE         1
      JCK PER DIMM PARITY ERROR EN  0
      DDR4_DIMM_ISOLATION_ENABLE    0

  vmseOptions:         0000E041
      VMSE_MODE_2_1             1
      VMSE_PREAMBLE_2UI         0
      SAFE_TURN_AROUND_TIMINGS  0
      VMSE_RANK_MARGIN_TOOL_EN  0
      VMT Pattern Length (loop count)  00
      VMSE_NB_PERST_EN          0
      VMSE_SB_PERST_EN          1
      RESTORE_VMSE_TRAININGS_ON_FAST_BOOT          0
      VMSE_DATA_SCRAMBLING_EN  1
      VMSE_CMD_SCRAMBLING_EN   1
      VMSE_CMD_SCR_ON_RETRY_EN 1

  RASmodeEx:       06
      DEVTAGGING_EN        0
      Bank SDDC_EN        0
      DMNDSCRB_EN        1
      PTRLSCRB_EN        1
      DDDC_EN            0
      Bank DDDC_EN       0
      A7_MODE            0
      DDDC_WIREKILL      0
      GLOBAL_RAS_POLICY  0

  RASmode:         00
      RK_SPARE             0
      CH_LOCKSTEP          0
      CH_MIRROR            0

struct sysHost.setup.mem {
  VMSE PI Increment:        02
  VMSE VREF Increment:      04
  enforcePOR:      00
  ddrFreqLimit:    00
  nodeInter:       02
  chInter:         04
  rankInter:       08
  dimmTypeSupport: 02
  pdwnCkMode:      00
  MemPwrSave:      01
  ckeThrottling:   01
  olttPeakBWLIMITPercent: 00
  thermalThrottlingOptions:  08
      CLTT_EN             1
      MH_OUTPUT_EN        0
      MH_SENSE_EN         0
  dramraplen:      02
  dramraplbwlimittf: 01
  dramraplRefreshBase: 0A
  dramMaint: 02
  electricalThrottling:  00
  forceRankMult:   00
  lrdimmModuleDelay: 01
  cmdClkEyeWidth:  64
  rmtPatternLength:0F
  patrolScrubDuration:18
  spareErrTh:      0x7FFF
  WirekillRankTh:  0x02
  leakyBktLo:      0x28
  leakyBktHi:      0x29
  scrambleSeedLow: 00000000
  scrambleSeedHigh:00000000
  check_pm_sts:    00
  check_platform_detect: 00
  pushtoCasLatency:        0x16
  phaseShedding:           0x01
  laiMode:                 0x00
  tolm:                    0x01
  mcODTOverride:           0x00
  numSparTrans:            0x0004
  earlyCmdTraining:        0x01
  nbErrTh:             0xFF
  sbErrTh:                 0x1FFF
  vmseLinkFailTh:          0x07
  migrationSpareMask       0x00
  memMirroringMode:        0x00
  memMirorEnableMap:       0x00
      MIRROR_SCRUB     1
  partialMirrorSize[04] = 0001 [64MB] 
  struct ddrIMCSetup[04] {
    enabled:        00000001
    ddrVddLimit:    00
    struct ddrChannelSetup[00] {
      enabled:       01
      batterybacked: 00
      rankMask:      FF
      numDimmSlots:  03
      struct ddrDimmSetup[00] {
        mapOut[00]: 00
        mapOut[01]: 00
        mapOut[02]: 00
        mapOut[03]: 00
    };
      struct ddrDimmSetup[01] {
        mapOut[00]: 00
        mapOut[01]: 00
        mapOut[02]: 00
        mapOut[03]: 00
    };
      struct ddrDimmSetup[02] {
        mapOut[00]: 00
        mapOut[01]: 00
        mapOut[02]: 00
        mapOut[03]: 00
    };
    };
    struct ddrChannelSetup[01] {
      enabled:       01
      batterybacked: 00
      rankMask:      FF
      numDimmSlots:  03
      struct ddrDimmSetup[00] {
        mapOut[00]: 00
        mapOut[01]: 00
        mapOut[02]: 00
        mapOut[03]: 00
    };
      struct ddrDimmSetup[01] {
        mapOut[00]: 00
        mapOut[01]: 00
        mapOut[02]: 00
        mapOut[03]: 00
    };
      struct ddrDimmSetup[02] {
        mapOut[00]: 00
        mapOut[01]: 00
        mapOut[02]: 00
        mapOut[03]: 00
    };
    };
    struct ddrChannelSetup[02] {
      enabled:       01
      batterybacked: 00
      rankMask:      FF
      numDimmSlots:  03
      struct ddrDimmSetup[00] {
        mapOut[00]: 00
        mapOut[01]: 00
        mapOut[02]: 00
        mapOut[03]: 00
    };
      struct ddrDimmSetup[01] {
        mapOut[00]: 00
        mapOut[01]: 00
        mapOut[02]: 00
        mapOut[03]: 00
    };
      struct ddrDimmSetup[02] {
        mapOut[00]: 00
        mapOut[01]: 00
        mapOut[02]: 00
        mapOut[03]: 00
    };
    };
    struct ddrChannelSetup[03] {
      enabled:       01
      batterybacked: 00
      rankMask:      FF
      numDimmSlots:  03
      struct ddrDimmSetup[00] {
        mapOut[00]: 00
        mapOut[01]: 00
        mapOut[02]: 00
        mapOut[03]: 00
    };
      struct ddrDimmSetup[01] {
        mapOut[00]: 00
        mapOut[01]: 00
        mapOut[02]: 00
        mapOut[03]: 00
    };
      struct ddrDimmSetup[02] {
        mapOut[00]: 00
        mapOut[01]: 00
        mapOut[02]: 00
        mapOut[03]: 00
    };
    };
  partialMirrorSize[05] = 0001 [64MB] 
  struct ddrIMCSetup[05] {
    enabled:        00000001
    ddrVddLimit:    00
    struct ddrChannelSetup[00] {
      enabled:       01
      batterybacked: 00
      rankMask:      FF
      numDimmSlots:  03
      struct ddrDimmSetup[00] {
        mapOut[00]: 00
        mapOut[01]: 00
        mapOut[02]: 00
        mapOut[03]: 00
    };
      struct ddrDimmSetup[01] {
        mapOut[00]: 00
        mapOut[01]: 00
        mapOut[02]: 00
        mapOut[03]: 00
    };
      struct ddrDimmSetup[02] {
        mapOut[00]: 00
        mapOut[01]: 00
        mapOut[02]: 00
        mapOut[03]: 00
    };
    };
    struct ddrChannelSetup[01] {
      enabled:       01
      batterybacked: 00
      rankMask:      FF
      numDimmSlots:  03
      struct ddrDimmSetup[00] {
        mapOut[00]: 00
        mapOut[01]: 00
        mapOut[02]: 00
        mapOut[03]: 00
    };
      struct ddrDimmSetup[01] {
        mapOut[00]: 00
        mapOut[01]: 00
        mapOut[02]: 00
        mapOut[03]: 00
    };
      struct ddrDimmSetup[02] {
        mapOut[00]: 00
        mapOut[01]: 00
        mapOut[02]: 00
        mapOut[03]: 00
    };
    };
    struct ddrChannelSetup[02] {
      enabled:       01
      batterybacked: 00
      rankMask:      FF
      numDimmSlots:  03
      struct ddrDimmSetup[00] {
        mapOut[00]: 00
        mapOut[01]: 00
        mapOut[02]: 00
        mapOut[03]: 00
    };
      struct ddrDimmSetup[01] {
        mapOut[00]: 00
        mapOut[01]: 00
        mapOut[02]: 00
        mapOut[03]: 00
    };
      struct ddrDimmSetup[02] {
        mapOut[00]: 00
        mapOut[01]: 00
        mapOut[02]: 00
        mapOut[03]: 00
    };
    };
    struct ddrChannelSetup[03] {
      enabled:       01
      batterybacked: 00
      rankMask:      FF
      numDimmSlots:  03
      struct ddrDimmSetup[00] {
        mapOut[00]: 00
        mapOut[01]: 00
        mapOut[02]: 00
        mapOut[03]: 00
    };
      struct ddrDimmSetup[01] {
        mapOut[00]: 00
        mapOut[01]: 00
        mapOut[02]: 00
        mapOut[03]: 00
    };
      struct ddrDimmSetup[02] {
        mapOut[00]: 00
        mapOut[01]: 00
        mapOut[02]: 00
        mapOut[03]: 00
    };
    };
  };
}; //struct sysHost.setup

CPU Frequency: 0  2500 (MHz)
Set SMBUS Clock Frequency to 6650 for DDR Frequency 1330
N4: warm reset bit is not set, force ColdBoot.
N4: Clearing the MRC NVRAM structure.
N4: nvram node enabled = 0x1
N5: warm reset bit is not set, force ColdBoot.
N5: nvram node enabled = 0x1
bootMode = NormalBoot. Taking the normal boot path through MRC.
subBootMode = ColdBoot. Taking the cold boot sub-path through MRC.
CPU type is CPU_HSX and stepping is D0_REV_HSX: Apply all HSX D0/E0 WAs
N4: InitMemoryRiser: Stage 0 - Init VPP
N4: InitMemoryRiser: Read Initial SLTCON Data = 0x3C0
N4: InitMemoryRiser: slotCon.Bits.power_controller_control = 0, slotCon.Bits.power_indicator_control = 1
N4: InitMemoryRiser: Write SLTCON Data = 0x1E5
N4: InitMemoryRiser: Initialize hotplug events 
N5: InitMemoryRiser: Read Initial SLTCON Data = 0x3C0
N4: InitMemoryRiser: slotCon.Bits.power_controller_control = 0, slotCon.Bits.power_indicator_control = 1
N5: InitMemoryRiser: Write SLTCON Data = 0x1E5
N5: InitMemoryRiser: Initialize hotplug events 
N4: InitMemoryRiser: vpp enabled set. Skip update. vppMemN1org Data = 0x3
N4: InitMemoryRiser: Stage 1 - Init SLTCon
N4: InitMemoryRiser: Read Initial SLTCON Data = 0x1E5
N5: InitMemoryRiser: Stage 1 - Init SLTCon
N5: InitMemoryRiser: Read Initial SLTCON Data = 0x1E5
N4: InitMemoryRiser: Power Enable Good detection
N4: InitMemoryRiser: Power Enable Good
N5: InitMemoryRiser: Power Enable Good detection
N5: InitMemoryRiser: Power Enable Good
N4: VmseResetViaVpp: Write SLTCON Data = 0x9E5
N4: VmseResetViaVpp: Write SLTCON Data = 0x1E5
N5: VmseResetViaVpp: Write SLTCON Data = 0x9E5
N5: VmseResetViaVpp: Write SLTCON Data = 0x1E5
N2.C0: Jordan Creek Rev ID = 33
N2.C0: Setting Rev ID  = C1_REV
N2.C1: Jordan Creek Rev ID = 33
N2.C1: Setting Rev ID  = C1_REV
SMBUS read fail status = 0xE0000005
RETRY
SMBUS read fail status = 0xE000000B
RETRY
SMBUS read fail status = 0xE0000005
RETRY
SMBUS read fail status = 0xE000000B
RETRY
SMBUS read fail status = 0xE0000005
RETRY
SMBUS read fail status = 0xE000000B
RETRY
SMBUS read fail status = 0xE0000005
RETRY
SMBUS read fail status = 0xE000000B
RETRY

DIMM Detect time            3343 ms
N3: Init Throttling (Early)
N3: Detect DIMM Config
Set SMBUS Clock Frequency to 6650 for DDR Frequency 1330
Dispatch S3 for mem init
N4: Init Throttling (Early)
Skt3 Entering MRC
N4: Detect DIMM Config

sizeof sysHost = 286634

sizeof sysVar = 73483

sizeof memVar = 41569

sizeof cpuVar = 600

sizeof qpi_host_out = 494

sizeof commonVar = 1636

sizeof sysNvram = 208995

sizeof cpuNvram = 20

sizeof memNvram = 1505

sizeof qpiNvram = 56

sizeof commonNvram = 207414

sizeof commonImcNvram = 25925

sizeof nodeIMC = 3856

sizeof ddrChannel = 825

sizeof vmseChannelNvram = 2407

sizeof channelNvram = 5134

sizeof jckddrvar = 32076

sizeof sysHostSetup = 1698

struct sysHost.common {
  options:         00000005
      PROMOTE_WARN_EN         1
      PROMOTE_MRC_WARN_EN     0
      HALT_ON_ERROR_EN        1
  lowGap:          20
  highGap:         01
  serialDebugMsgLvl:0012
  bsdBreakpoint:   00
  maxAddrMem:      40000
  debugPort:       80
  nvramPtr:        00000000
  sysHostBufferPtr:00000000
  mmCfgBase:       80000000
  mmCfgSize:       10000000
  mmiohSize:       00000080
  pchumaEn:        00
  numaEn:          01
  isocEn:          01
  dcaEn:           01
  bdatEn:          00
  consoleComPort:  3F8
  ptrrSupport      01

struct sysHost.setup.mem {
  options:         C990DEA8
      TEMPHIGH_EN              0
      PDWN_IBT_OFF_EN          0
      PDWN_SR_CKE_MODE         0
      OPP_SELF_REF_EN          1
      MDLL_SHUT_DOWN_EN        0
      PAGE_POLICY              1
      ALLOW2XREF_EN            0
      MULTI_THREAD_MRC_EN      1
      ADAPTIVE_PAGE_EN         0
      CMD_CLK_TRAINING_EN      1
      SCRAMBLE_EN              1
      NUMA_AWARE               1
      ECC_CHECK_EN             1
      BALANCED_4WAY_EN         0
      CA_PARITY_EN             1
      SPLIT_BELOW_4GB_EN       0
      MARGIN_RANKS_EN          1
      MEMORY_TEST_FAST_BOOT_EN 1
      ATTEMPT_FAST_BOOT        0
      ZQ_CALIBRATION_EN        1
      PC6_CMD_ADDR_STANDBY_EN  0
      PROC_EIST_EN  1
      LRD_SUBRNK_C2CAS_TIM_EN  1
      DIMM_LRDIMM_3DS_SUPPORT  0
      PROMOTE_MEM_TRAIN_ERRORS 0
      PROMOTE_MEM_RAS_WARNINGS 0
      VMSE_CLOCK_STOP_EN 1
      SAFE_MC_BGF_PSV_EN            1

  options2:         16B003BA
      ADR_SUPPORT_EN                0
      HA_EARLY_WRITE_POST_EN        1
      MC_CHANNEL_HASH_MODE          0
      UNUSED_MEM_CHANNEL_INPUTS_EN  1
      PDA_EN                        0
      READ_VREF_CENTER_EN           1
      WRITE_VREF_CENTER_EN          1
      CMD_2_DATA_TUNING             1
      THERMAL_SENSOR_EN             1
      CATASTROPHIC_TRIP_EN          1
      VUNIT_CLOCK_GATING_EN         0
      TUNIT_CLOCK_GATING_EN         0
      MUNIT_CLOCK_GATING_EN         0
      DUNIT_CLOCK_GATING_EN         0
      CPGC_MEMORY_TEST_EN           0
      CPGC_MEMORY_ECC_EN            1
      OPP_READ_DURING_WMM           0
      PSMI_SUPPORT_EN               0
      JCK_PWR_MGMT_EN               0
      DISPLAY_EYE_EN   0
      ADVANCED_CLK_TRAINING         0
      RXVREF_PERSTROBE_TRAINING     0
      ADVANCED_STROBE_CENTERING     1
      ODT TIMING MODE               1
      EXT_DIMM_VREF_CIRCUIT         0
      BIOS_VMSE_RESET               1
      JCK_SAVE_ERRLOGS              0
      JKT_ERROR_FLOW                0
      VMSE_DISABLE_RCOMP            0
      MXB_RANK_SHARING_MODE         1
      JCK PER DIMM PARITY ERROR EN  0
      DDR4_DIMM_ISOLATION_ENABLE    0

  vmseOptions:         0000E041
      VMSE_MODE_2_1             1
      VMSE_PREAMBLE_2UI         0
      SAFE_TURN_AROUND_TIMINGS  0
      VMSE_RANK_MARGIN_TOOL_EN  0
      VMT Pattern Length (loop count)  00
      VMSE_NB_PERST_EN          0
      VMSE_SB_PERST_EN          1
      RESTORE_VMSE_TRAININGS_ON_FAST_BOOT          0
      VMSE_DATA_SCRAMBLING_EN  1
      VMSE_CMD_SCRAMBLING_EN   1
      VMSE_CMD_SCR_ON_RETRY_EN 1

  RASmodeEx:       06
      DEVTAGGING_EN        0
      Bank SDDC_EN        0
      DMNDSCRB_EN        1
      PTRLSCRB_EN        1
      DDDC_EN            0
      Bank DDDC_EN       0
      A7_MODE            0
      DDDC_WIREKILL      0
      GLOBAL_RAS_POLICY  0

  RASmode:         00
      RK_SPARE             0
      CH_LOCKSTEP          0
      CH_MIRROR            0

struct sysHost.setup.mem {
  VMSE PI Increment:        02
  VMSE VREF Increment:      04
  enforcePOR:      00
  ddrFreqLimit:    00
  nodeInter:       02
  chInter:         04
  rankInter:       08
  dimmTypeSupport: 02
  pdwnCkMode:      00
  MemPwrSave:      01
  ckeThrottling:   01
  olttPeakBWLIMITPercent: 00
  thermalThrottlingOptions:  08
      CLTT_EN             1
      MH_OUTPUT_EN        0
      MH_SENSE_EN         0
  dramraplen:      02
  dramraplbwlimittf: 01
  dramraplRefreshBase: 0A
  dramMaint: 02
  electricalThrottling:  00
  forceRankMult:   00
  lrdimmModuleDelay: 01
  cmdClkEyeWidth:  64
  rmtPatternLength:0F
  patrolScrubDuration:18
  spareErrTh:      0x7FFF
  WirekillRankTh:  0x02
  leakyBktLo:      0x28
  leakyBktHi:      0x29
  scrambleSeedLow: 00000000
  scrambleSeedHigh:00000000
  check_pm_sts:    00
  check_platform_detect: 00
  pushtoCasLatency:        0x16
  phaseShedding:           0x01
  laiMode:                 0x00
  tolm:                    0x01
  mcODTOverride:           0x00
  numSparTrans:            0x0004
  earlyCmdTraining:        0x01
  nbErrTh:             0xFF
  sbErrTh:                 0x1FFF
  vmseLinkFailTh:          0x07
  migrationSpareMask       0x00
  memMirroringMode:        0x00
  memMirorEnableMap:       0x00
      MIRROR_SCRUB     1
  partialMirrorSize[06] = 0001 [64MB] 
  struct ddrIMCSetup[06] {
    enabled:        00000001
    ddrVddLimit:    00
    struct ddrChannelSetup[00] {
      enabled:       01
      batterybacked: 00
      rankMask:      FF
      numDimmSlots:  03
      struct ddrDimmSetup[00] {
        mapOut[00]: 00
        mapOut[01]: 00
        mapOut[02]: 00
        mapOut[03]: 00
    };
      struct ddrDimmSetup[01] {
        mapOut[00]: 00
        mapOut[01]: 00
        mapOut[02]: 00
        mapOut[03]: 00
    };
      struct ddrDimmSetup[02] {
        mapOut[00]: 00
        mapOut[01]: 00
        mapOut[02]: 00
        mapOut[03]: 00
    };
    };
    struct ddrChannelSetup[01] {
      enabled:       01
      batterybacked: 00
      rankMask:      FF
      numDimmSlots:  03
      struct ddrDimmSetup[00] {
        mapOut[00]: 00
        mapOut[01]: 00
        mapOut[02]: 00
        mapOut[03]: 00
    };
      struct ddrDimmSetup[01] {
        mapOut[00]: 00
        mapOut[01]: 00
        mapOut[02]: 00
        mapOut[03]: 00
    };
      struct ddrDimmSetup[02] {
        mapOut[00]: 00
        mapOut[01]: 00
        mapOut[02]: 00
        mapOut[03]: 00
    };
    };
    struct ddrChannelSetup[02] {
      enabled:       01
      batterybacked: 00
      rankMask:      FF
      numDimmSlots:  03
      struct ddrDimmSetup[00] {
        mapOut[00]: 00
        mapOut[01]: 00
        mapOut[02]: 00
        mapOut[03]: 00
    };
      struct ddrDimmSetup[01] {
        mapOut[00]: 00
        mapOut[01]: 00
        mapOut[02]: 00
        mapOut[03]: 00
    };
      struct ddrDimmSetup[02] {
        mapOut[00]: 00
        mapOut[01]: 00
        mapOut[02]: 00
        mapOut[03]: 00
    };
    };
    struct ddrChannelSetup[03] {
      enabled:       01
      batterybacked: 00
      rankMask:      FF
      numDimmSlots:  03
      struct ddrDimmSetup[00] {
        mapOut[00]: 00
        mapOut[01]: 00
        mapOut[02]: 00
        mapOut[03]: 00
    };
      struct ddrDimmSetup[01] {
        mapOut[00]: 00
        mapOut[01]: 00
        mapOut[02]: 00
        mapOut[03]: 00
    };
      struct ddrDimmSetup[02] {
        mapOut[00]: 00
        mapOut[01]: 00
        mapOut[02]: 00
        mapOut[03]: 00
    };
    };
  partialMirrorSize[07] = 0001 [64MB] 
  struct ddrIMCSetup[07] {
    enabled:        00000001
    ddrVddLimit:    00
    struct ddrChannelSetup[00] {
      enabled:       01
      batterybacked: 00
      rankMask:      FF
      numDimmSlots:  03
      struct ddrDimmSetup[00] {
        mapOut[00]: 00
        mapOut[01]: 00
        mapOut[02]: 00
        mapOut[03]: 00
    };
      struct ddrDimmSetup[01] {
        mapOut[00]: 00
        mapOut[01]: 00
        mapOut[02]: 00
        mapOut[03]: 00
    };
      struct ddrDimmSetup[02] {
        mapOut[00]: 00
        mapOut[01]: 00
        mapOut[02]: 00
        mapOut[03]: 00
    };
    };
    struct ddrChannelSetup[01] {
      enabled:       01
      batterybacked: 00
      rankMask:      FF
      numDimmSlots:  03
      struct ddrDimmSetup[00] {
        mapOut[00]: 00
        mapOut[01]: 00
        mapOut[02]: 00
        mapOut[03]: 00
    };
      struct ddrDimmSetup[01] {
        mapOut[00]: 00
        mapOut[01]: 00
        mapOut[02]: 00
        mapOut[03]: 00
    };
      struct ddrDimmSetup[02] {
        mapOut[00]: 00
        mapOut[01]: 00
        mapOut[02]: 00
        mapOut[03]: 00
    };
    };
    struct ddrChannelSetup[02] {
      enabled:       01
      batterybacked: 00
      rankMask:      FF
      numDimmSlots:  03
      struct ddrDimmSetup[00] {
        mapOut[00]: 00
        mapOut[01]: 00
        mapOut[02]: 00
        mapOut[03]: 00
    };
      struct ddrDimmSetup[01] {
        mapOut[00]: 00
        mapOut[01]: 00
        mapOut[02]: 00
        mapOut[03]: 00
    };
      struct ddrDimmSetup[02] {
        mapOut[00]: 00
        mapOut[01]: 00
        mapOut[02]: 00
        mapOut[03]: 00
    };
    };
    struct ddrChannelSetup[03] {
      enabled:       01
      batterybacked: 00
      rankMask:      FF
      numDimmSlots:  03
      struct ddrDimmSetup[00] {
        mapOut[00]: 00
        mapOut[01]: 00
        mapOut[02]: 00
        mapOut[03]: 00
    };
      struct ddrDimmSetup[01] {
        mapOut[00]: 00
        mapOut[01]: 00
        mapOut[02]: 00
        mapOut[03]: 00
    };
      struct ddrDimmSetup[02] {
        mapOut[00]: 00
        mapOut[01]: 00
        mapOut[02]: 00
        mapOut[03]: 00
    };
    };
  };
}; //struct sysHost.setup

CPU Frequency: 0  2500 (MHz)
Set SMBUS Clock Frequency to 6650 for DDR Frequency 1330
N6: warm reset bit is not set, force ColdBoot.
N6: Clearing the MRC NVRAM structure.
N6: nvram node enabled = 0x1
N7: warm reset bit is not set, force ColdBoot.
N7: nvram node enabled = 0x1
bootMode = NormalBoot. Taking the normal boot path through MRC.
subBootMode = ColdBoot. Taking the cold boot sub-path through MRC.
CPU type is CPU_HSX and stepping is D0_REV_HSX: Apply all HSX D0/E0 WAs
N3.C0: Jordan Creek Rev ID = 33
N6: InitMemoryRiser: Stage 0 - Init VPP
N3.C0: Setting Rev ID  = C1_REV
N6: InitMemoryRiser: Read Initial SLTCON Data = 0x3C0
N6: InitMemoryRiser: slotCon.Bits.power_controller_control = 0, slotCon.Bits.power_indicator_control = 1
N3.C1: Jordan Creek Rev ID = 33
N6: InitMemoryRiser: Write SLTCON Data = 0x1E5
N3.C1: Setting Rev ID  = C1_REV
N6: InitMemoryRiser: Initialize hotplug events 
N7: InitMemoryRiser: Read Initial SLTCON Data = 0x3C0
SMBUS read fail status = 0xE0000001
RETRY
N6: InitMemoryRiser: slotCon.Bits.power_controller_control = 0, slotCon.Bits.power_indicator_control = 1
N7: InitMemoryRiser: Write SLTCON Data = 0x1E5
N7: InitMemoryRiser: Initialize hotplug events 
N6: InitMemoryRiser: vpp enabled set. Skip update. vppMemN1org Data = 0x3
N6: InitMemoryRiser: Stage 1 - Init SLTCon
N6: InitMemoryRiser: Read Initial SLTCON Data = 0x1E5
SMBUS read fail status = 0xE0000003
RETRY
N7: InitMemoryRiser: Stage 1 - Init SLTCon
SMBUS read fail status = 0xE0000007
RETRY
N7: InitMemoryRiser: Read Initial SLTCON Data = 0x1E5
SMBUS read fail status = 0xE000000F
RETRY
SMBUS read fail status = 0xE0000001
RETRY
SMBUS read fail status = 0xE0000003
RETRY
SMBUS read fail status = 0xE0000007
RETRY
SMBUS read fail status = 0xE000000F
RETRY
SMBUS read fail status = 0xE0000001
RETRY
SMBUS read fail status = 0xE0000003
RETRY
SMBUS read fail status = 0xE0000007
RETRY
SMBUS read fail status = 0xE000000F
RETRY
SMBUS read fail status = 0xE0000001
RETRY
SMBUS read fail status = 0xE0000003
RETRY
SMBUS read fail status = 0xE0000007
RETRY
SMBUS read fail status = 0xE000000F
RETRY

DIMM Detect time            2450 ms
Send data from S1 to S0
N6: InitMemoryRiser: Power Enable Good detection
N6: InitMemoryRiser: Power Enable Good
N7: InitMemoryRiser: Power Enable Good detection
N7: InitMemoryRiser: Power Enable Good
N6: VmseResetViaVpp: Write SLTCON Data = 0x9E5
N6: VmseResetViaVpp: Write SLTCON Data = 0x1E5
N7: VmseResetViaVpp: Write SLTCON Data = 0x9E5
N7: VmseResetViaVpp: Write SLTCON Data = 0x1E5
N4.C0: Jordan Creek Rev ID = 33
N4.C0: Setting Rev ID  = C1_REV
N4.C1: Jordan Creek Rev ID = 33
N4.C1: Setting Rev ID  = C1_REV
SMBUS read fail status = 0xE0000005
RETRY
SMBUS read fail status = 0xE000000B
RETRY
SMBUS read fail status = 0xE0000005
RETRY
SMBUS read fail status = 0xE000000B
RETRY
SMBUS read fail status = 0xE0000005
RETRY
SMBUS read fail status = 0xE000000B
RETRY
SMBUS read fail status = 0xE0000005
RETRY
SMBUS read fail status = 0xE000000B
RETRY

DIMM Detect time            3343 ms
N5: Init Throttling (Early)
N5: Detect DIMM Config
Set SMBUS Clock Frequency to 6650 for DDR Frequency 1330
N0: Init Throttling (Early)
N6: Init Throttling (Early)
Checkpoint Code: Socket 0, 0xB0, 0x00, 0x0000
N6: Detect DIMM Config
N0: Detect DIMM Config
Set SMBUS Clock Frequency to 6650 for DDR Frequency 1330
Set SMBUS Clock Frequency to 6650 for DDR Frequency 1330
N5.C0: Jordan Creek Rev ID = 33
N5.C0: Setting Rev ID  = C1_REV
N5.C1: Jordan Creek Rev ID = 33
N5.C1: Setting Rev ID  = C1_REV
SMBUS read fail status = 0xE0000001
RETRY
SMBUS read fail status = 0xE0000003
RETRY
SMBUS read fail status = 0xE0000007
RETRY
SMBUS read fail status = 0xE000000F
RETRY
SMBUS read fail status = 0xE0000001
RETRY
SMBUS read fail status = 0xE0000003
RETRY
SMBUS read fail status = 0xE0000007
RETRY
SMBUS read fail status = 0xE000000F
RETRY
SMBUS read fail status = 0xE0000001
RETRY
SMBUS read fail status = 0xE0000003
RETRY
SMBUS read fail status = 0xE0000007
RETRY
SMBUS read fail status = 0xE000000F
RETRY
SMBUS read fail status = 0xE0000001
RETRY
SMBUS read fail status = 0xE0000003
RETRY
SMBUS read fail status = 0xE0000007
RETRY
SMBUS read fail status = 0xE000000F
RETRY

DIMM Detect time            2412 ms
Send data from S2 to S0
N6.C0: Jordan Creek Rev ID = 33
N6.C0: Setting Rev ID  = C1_REV
N0.C0: Jordan Creek Rev ID = 33
N0.C0: Setting Rev ID  = C1_REV
N6.C1: Jordan Creek Rev ID = 33
N6.C1: Setting Rev ID  = C1_REV
N0.C1: Jordan Creek Rev ID = 33
N0.C1: Setting Rev ID  = C1_REV
SMBUS read fail status = 0xE0000005
RETRY
SMBUS read fail status = 0xE0000005
RETRY
SMBUS read fail status = 0xE000000B
RETRY
SMBUS read fail status = 0xE000000B
RETRY
SMBUS read fail status = 0xE0000005
RETRY
SMBUS read fail status = 0xE0000005
RETRY
SMBUS read fail status = 0xE000000B
RETRY
SMBUS read fail status = 0xE000000B
RETRY
SMBUS read fail status = 0xE0000005
RETRY
SMBUS read fail status = 0xE0000005
RETRY
SMBUS read fail status = 0xE000000B
RETRY
SMBUS read fail status = 0xE000000B
RETRY
SMBUS read fail status = 0xE0000005
RETRY
SMBUS read fail status = 0xE0000005
RETRY
SMBUS read fail status = 0xE000000B
RETRY

DIMM Detect time            2260 ms
SMBUS read fail status = 0xE000000B
RETRY
N7: Init Throttling (Early)

DIMM Detect time            2266 ms
N7: Detect DIMM Config
N1: Init Throttling (Early)
Set SMBUS Clock Frequency to 6650 for DDR Frequency 1330
Checkpoint Code: Socket 0, 0xB0, 0x00, 0x0000
N1: Detect DIMM Config
Set SMBUS Clock Frequency to 6650 for DDR Frequency 1330
N7.C0: Jordan Creek Rev ID = 33
N7.C0: Setting Rev ID  = C1_REV
N1.C0: Jordan Creek Rev ID = 33
N7.C1: Jordan Creek Rev ID = 33
N1.C0: Setting Rev ID  = C1_REV
N7.C1: Setting Rev ID  = C1_REV
SMBUS read fail status = 0xE0000001
RETRY
N1.C1: Jordan Creek Rev ID = 33
N1.C1: Setting Rev ID  = C1_REV
SMBUS read fail status = 0xE0000001
RETRY
SMBUS read fail status = 0xE0000003
RETRY
SMBUS read fail status = 0xE0000007
RETRY
SMBUS read fail status = 0xE0000003
RETRY
SMBUS read fail status = 0xE0000007
RETRY
SMBUS read fail status = 0xE000000F
RETRY
SMBUS read fail status = 0xE0000001
RETRY
SMBUS read fail status = 0xE000000F
RETRY
SMBUS read fail status = 0xE0000001
RETRY
SMBUS read fail status = 0xE0000003
RETRY
SMBUS read fail status = 0xE0000007
RETRY
SMBUS read fail status = 0xE0000003
RETRY
SMBUS read fail status = 0xE0000007
RETRY
SMBUS read fail status = 0xE000000F
RETRY
SMBUS read fail status = 0xE0000001
RETRY
SMBUS read fail status = 0xE000000F
RETRY
SMBUS read fail status = 0xE0000001
RETRY
SMBUS read fail status = 0xE0000003
RETRY
SMBUS read fail status = 0xE0000007
RETRY
SMBUS read fail status = 0xE0000003
RETRY
SMBUS read fail status = 0xE0000007
RETRY
SMBUS read fail status = 0xE000000F
RETRY
SMBUS read fail status = 0xE0000001
RETRY
SMBUS read fail status = 0xE000000F
RETRY
SMBUS read fail status = 0xE0000001
RETRY
SMBUS read fail status = 0xE0000003
RETRY
SMBUS read fail status = 0xE0000007
RETRY
SMBUS read fail status = 0xE0000003
RETRY
SMBUS read fail status = 0xE0000007
RETRY
SMBUS read fail status = 0xE000000F
RETRY

DIMM Detect time            2419 ms
Send data from S3 to S0
SMBUS read fail status = 0xE000000F
RETRY

DIMM Detect time            2419 ms
Get Var data from S1 to S0
Get NVRAM data from S1 to S0
Get Var data from S2 to S0
Get NVRAM data from S2 to S0
Get Var data from S3 to S0
Get NVRAM data from S3 to S0
Node   | Channel | DIMM |  Bus Segment | SMBUS Address
-------|---------|------|--------------|--------------
   0   |    0    |   0  |      0       |       0      - Present
   0   |    0    |   1  |      0       |       1      - Present
   0   |    0    |   2  |      0       |       2      - Not Present
   0   |    1    |   0  |      0       |       4      - Present
   0   |    1    |   1  |      0       |       5      - Present
   0   |    1    |   2  |      0       |       6      - Not Present
   0   |    2    |   0  |      1       |       0      - Present
   0   |    2    |   1  |      1       |       1      - Present
   0   |    2    |   2  |      1       |       2      - Not Present
   0   |    3    |   0  |      1       |       4      - Present
   0   |    3    |   1  |      1       |       5      - Present
   0   |    3    |   2  |      1       |       6      - Not Present
Node   | Channel | DIMM |  Bus Segment | SMBUS Address
-------|---------|------|--------------|--------------
   1   |    0    |   0  |      0       |       0      - Present
   1   |    0    |   1  |      0       |       1      - Not Present
   1   |    0    |   2  |      0       |       2      - Not Present
   1   |    1    |   0  |      0       |       4      - Present
   1   |    1    |   1  |      0       |       5      - Not Present
   1   |    1    |   2  |      0       |       6      - Not Present
   1   |    2    |   0  |      1       |       0      - Present
   1   |    2    |   1  |      1       |       1      - Not Present
   1   |    2    |   2  |      1       |       2      - Not Present
   1   |    3    |   0  |      1       |       4      - Present
   1   |    3    |   1  |      1       |       5      - Not Present
   1   |    3    |   2  |      1       |       6      - Not Present
Node   | Channel | DIMM |  Bus Segment | SMBUS Address
-------|---------|------|--------------|--------------
   2   |    0    |   0  |      0       |       0      - Present
   2   |    0    |   1  |      0       |       1      - Present
   2   |    0    |   2  |      0       |       2      - Not Present
   2   |    1    |   0  |      0       |       4      - Present
   2   |    1    |   1  |      0       |       5      - Present
   2   |    1    |   2  |      0       |       6      - Not Present
   2   |    2    |   0  |      1       |       0      - Present
   2   |    2    |   1  |      1       |       1      - Present
   2   |    2    |   2  |      1       |       2      - Not Present
   2   |    3    |   0  |      1       |       4      - Present
   2   |    3    |   1  |      1       |       5      - Present
   2   |    3    |   2  |      1       |       6      - Not Present
Node   | Channel | DIMM |  Bus Segment | SMBUS Address
-------|---------|------|--------------|--------------
   3   |    0    |   0  |      0       |       0      - Present
   3   |    0    |   1  |      0       |       1      - Not Present
   3   |    0    |   2  |      0       |       2      - Not Present
   3   |    1    |   0  |      0       |       4      - Present
   3   |    1    |   1  |      0       |       5      - Not Present
   3   |    1    |   2  |      0       |       6      - Not Present
   3   |    2    |   0  |      1       |       0      - Present
   3   |    2    |   1  |      1       |       1      - Not Present
   3   |    2    |   2  |      1       |       2      - Not Present
   3   |    3    |   0  |      1       |       4      - Present
   3   |    3    |   1  |      1       |       5      - Not Present
   3   |    3    |   2  |      1       |       6      - Not Present
Node   | Channel | DIMM |  Bus Segment | SMBUS Address
-------|---------|------|--------------|--------------
   4   |    0    |   0  |      0       |       0      - Present
   4   |    0    |   1  |      0       |       1      - Present
   4   |    0    |   2  |      0       |       2      - Not Present
   4   |    1    |   0  |      0       |       4      - Present
   4   |    1    |   1  |      0       |       5      - Present
   4   |    1    |   2  |      0       |       6      - Not Present
   4   |    2    |   0  |      1       |       0      - Present
   4   |    2    |   1  |      1       |       1      - Present
   4   |    2    |   2  |      1       |       2      - Not Present
   4   |    3    |   0  |      1       |       4      - Present
   4   |    3    |   1  |      1       |       5      - Present
   4   |    3    |   2  |      1       |       6      - Not Present
Node   | Channel | DIMM |  Bus Segment | SMBUS Address
-------|---------|------|--------------|--------------
   5   |    0    |   0  |      0       |       0      - Present
   5   |    0    |   1  |      0       |       1      - Not Present
   5   |    0    |   2  |      0       |       2      - Not Present
   5   |    1    |   0  |      0       |       4      - Present
   5   |    1    |   1  |      0       |       5      - Not Present
   5   |    1    |   2  |      0       |       6      - Not Present
   5   |    2    |   0  |      1       |       0      - Present
   5   |    2    |   1  |      1       |       1      - Not Present
   5   |    2    |   2  |      1       |       2      - Not Present
   5   |    3    |   0  |      1       |       4      - Present
   5   |    3    |   1  |      1       |       5      - Not Present
   5   |    3    |   2  |      1       |       6      - Not Present
Node   | Channel | DIMM |  Bus Segment | SMBUS Address
-------|---------|------|--------------|--------------
   6   |    0    |   0  |      0       |       0      - Present
   6   |    0    |   1  |      0       |       1      - Present
   6   |    0    |   2  |      0       |       2      - Not Present
   6   |    1    |   0  |      0       |       4      - Present
   6   |    1    |   1  |      0       |       5      - Present
   6   |    1    |   2  |      0       |       6      - Not Present
   6   |    2    |   0  |      1       |       0      - Present
   6   |    2    |   1  |      1       |       1      - Present
   6   |    2    |   2  |      1       |       2      - Not Present
   6   |    3    |   0  |      1       |       4      - Present
   6   |    3    |   1  |      1       |       5      - Present
   6   |    3    |   2  |      1       |       6      - Not Present
Node   | Channel | DIMM |  Bus Segment | SMBUS Address
-------|---------|------|--------------|--------------
   7   |    0    |   0  |      0       |       0      - Present
   7   |    0    |   1  |      0       |       1      - Not Present
   7   |    0    |   2  |      0       |       2      - Not Present
   7   |    1    |   0  |      0       |       4      - Present
   7   |    1    |   1  |      0       |       5      - Not Present
   7   |    1    |   2  |      0       |       6      - Not Present
   7   |    2    |   0  |      1       |       0      - Present
   7   |    2    |   1  |      1       |       1      - Not Present
   7   |    2    |   2  |      1       |       2      - Not Present
   7   |    3    |   0  |      1       |       4      - Present
   7   |    3    |   1  |      1       |       5      - Not Present
   7   |    3    |   2  |      1       |       6      - Not Present
N0.C0.D0: techIndex = 4. Num Ranks = 2
N0.C0.D1: techIndex = 4. Num Ranks = 2
N0.C1.D0: techIndex = 4. Num Ranks = 2
N0.C1.D1: techIndex = 4. Num Ranks = 2
N0.C2.D0: techIndex = 4. Num Ranks = 2
N0.C2.D1: techIndex = 4. Num Ranks = 2
N0.C3.D0: techIndex = 4. Num Ranks = 2
N0.C3.D1: techIndex = 4. Num Ranks = 2
N1.C0.D0: techIndex = 6. Num Ranks = 2
N1.C1.D0: techIndex = 6. Num Ranks = 2
N1.C2.D0: techIndex = 6. Num Ranks = 2
N1.C3.D0: techIndex = 6. Num Ranks = 2
N2.C0.D0: techIndex = 4. Num Ranks = 2
N2.C0.D1: techIndex = 4. Num Ranks = 2
N2.C1.D0: techIndex = 4. Num Ranks = 2
N2.C1.D1: techIndex = 4. Num Ranks = 2
N2.C2.D0: techIndex = 4. Num Ranks = 2
N2.C2.D1: techIndex = 4. Num Ranks = 2
N2.C3.D0: techIndex = 4. Num Ranks = 2
N2.C3.D1: techIndex = 4. Num Ranks = 2
N3.C0.D0: techIndex = 6. Num Ranks = 2
N3.C1.D0: techIndex = 6. Num Ranks = 2
N3.C2.D0: techIndex = 6. Num Ranks = 2
N3.C3.D0: techIndex = 6. Num Ranks = 2
N4.C0.D0: techIndex = 4. Num Ranks = 2
N4.C0.D1: techIndex = 4. Num Ranks = 2
N4.C1.D0: techIndex = 4. Num Ranks = 2
N4.C1.D1: techIndex = 4. Num Ranks = 2
N4.C2.D0: techIndex = 4. Num Ranks = 2
N4.C2.D1: techIndex = 4. Num Ranks = 2
N4.C3.D0: techIndex = 4. Num Ranks = 2
N4.C3.D1: techIndex = 4. Num Ranks = 2
N5.C0.D0: techIndex = 6. Num Ranks = 2
N5.C1.D0: techIndex = 6. Num Ranks = 2
N5.C2.D0: techIndex = 6. Num Ranks = 2
N5.C3.D0: techIndex = 6. Num Ranks = 2
N6.C0.D0: techIndex = 4. Num Ranks = 2
N6.C0.D1: techIndex = 4. Num Ranks = 2
N6.C1.D0: techIndex = 4. Num Ranks = 2
N6.C1.D1: techIndex = 4. Num Ranks = 2
N6.C2.D0: techIndex = 4. Num Ranks = 2
N6.C2.D1: techIndex = 4. Num Ranks = 2
N6.C3.D0: techIndex = 4. Num Ranks = 2
N6.C3.D1: techIndex = 4. Num Ranks = 2
N7.C0.D0: techIndex = 6. Num Ranks = 2
N7.C1.D0: techIndex = 6. Num Ranks = 2
N7.C2.D0: techIndex = 6. Num Ranks = 2
N7.C3.D0: techIndex = 6. Num Ranks = 2
N8: RDIMM DDR3 population
Checkpoint Code: Socket 0, 0xB2, 0x00, 0x0000
Check Dimm Ranks
Check DIMM population
N0.C0.D0: Number of ranks = 2
N0.C0.D1: Number of ranks = 2
N0.C0.D0.R0: ENABLED
N0.C0.D0.R1: ENABLED
N0.C0.D1.R0: ENABLED
N0.C0.D1.R1: ENABLED
N0.C0: TermRnkMsk = 0x2000011
N0.C1.D0: Number of ranks = 2
N0.C1.D1: Number of ranks = 2
N0.C1.D0.R0: ENABLED
N0.C1.D0.R1: ENABLED
N0.C1.D1.R0: ENABLED
N0.C1.D1.R1: ENABLED
N0.C1: TermRnkMsk = 0x2000011
N0.C2.D0: Number of ranks = 2
N0.C2.D1: Number of ranks = 2
N0.C2.D0.R0: ENABLED
N0.C2.D0.R1: ENABLED
N0.C2.D1.R0: ENABLED
N0.C2.D1.R1: ENABLED
N0.C2: TermRnkMsk = 0x2000011
N0.C3.D0: Number of ranks = 2
N0.C3.D1: Number of ranks = 2
N0.C3.D0.R0: ENABLED
N0.C3.D0.R1: ENABLED
N0.C3.D1.R0: ENABLED
N0.C3.D1.R1: ENABLED
N0.C3: TermRnkMsk = 0x2000011
N1.C0.D0: Number of ranks = 2
N1.C0.D0.R0: ENABLED
N1.C0.D0.R1: ENABLED
N1.C0: TermRnkMsk = 0x2000001
N1.C1.D0: Number of ranks = 2
N1.C1.D0.R0: ENABLED
N1.C1.D0.R1: ENABLED
N1.C1: TermRnkMsk = 0x2000001
N1.C2.D0: Number of ranks = 2
N1.C2.D0.R0: ENABLED
N1.C2.D0.R1: ENABLED
N1.C2: TermRnkMsk = 0x2000001
N1.C3.D0: Number of ranks = 2
N1.C3.D0.R0: ENABLED
N1.C3.D0.R1: ENABLED
N1.C3: TermRnkMsk = 0x2000001
N2.C0.D0: Number of ranks = 2
N2.C0.D1: Number of ranks = 2
N2.C0.D0.R0: ENABLED
N2.C0.D0.R1: ENABLED
N2.C0.D1.R0: ENABLED
N2.C0.D1.R1: ENABLED
N2.C0: TermRnkMsk = 0x2000011
N2.C1.D0: Number of ranks = 2
N2.C1.D1: Number of ranks = 2
N2.C1.D0.R0: ENABLED
N2.C1.D0.R1: ENABLED
N2.C1.D1.R0: ENABLED
N2.C1.D1.R1: ENABLED
N2.C1: TermRnkMsk = 0x2000011
N2.C2.D0: Number of ranks = 2
N2.C2.D1: Number of ranks = 2
N2.C2.D0.R0: ENABLED
N2.C2.D0.R1: ENABLED
N2.C2.D1.R0: ENABLED
N2.C2.D1.R1: ENABLED
N2.C2: TermRnkMsk = 0x2000011
N2.C3.D0: Number of ranks = 2
N2.C3.D1: Number of ranks = 2
N2.C3.D0.R0: ENABLED
N2.C3.D0.R1: ENABLED
N2.C3.D1.R0: ENABLED
N2.C3.D1.R1: ENABLED
N2.C3: TermRnkMsk = 0x2000011
N3.C0.D0: Number of ranks = 2
N3.C0.D0.R0: ENABLED
N3.C0.D0.R1: ENABLED
N3.C0: TermRnkMsk = 0x2000001
N3.C1.D0: Number of ranks = 2
N3.C1.D0.R0: ENABLED
N3.C1.D0.R1: ENABLED
N3.C1: TermRnkMsk = 0x2000001
N3.C2.D0: Number of ranks = 2
N3.C2.D0.R0: ENABLED
N3.C2.D0.R1: ENABLED
N3.C2: TermRnkMsk = 0x2000001
N3.C3.D0: Number of ranks = 2
N3.C3.D0.R0: ENABLED
N3.C3.D0.R1: ENABLED
N3.C3: TermRnkMsk = 0x2000001
N4.C0.D0: Number of ranks = 2
N4.C0.D1: Number of ranks = 2
N4.C0.D0.R0: ENABLED
N4.C0.D0.R1: ENABLED
N4.C0.D1.R0: ENABLED
N4.C0.D1.R1: ENABLED
N4.C0: TermRnkMsk = 0x2000011
N4.C1.D0: Number of ranks = 2
N4.C1.D1: Number of ranks = 2
N4.C1.D0.R0: ENABLED
N4.C1.D0.R1: ENABLED
N4.C1.D1.R0: ENABLED
N4.C1.D1.R1: ENABLED
N4.C1: TermRnkMsk = 0x2000011
N4.C2.D0: Number of ranks = 2
N4.C2.D1: Number of ranks = 2
N4.C2.D0.R0: ENABLED
N4.C2.D0.R1: ENABLED
N4.C2.D1.R0: ENABLED
N4.C2.D1.R1: ENABLED
N4.C2: TermRnkMsk = 0x2000011
N4.C3.D0: Number of ranks = 2
N4.C3.D1: Number of ranks = 2
N4.C3.D0.R0: ENABLED
N4.C3.D0.R1: ENABLED
N4.C3.D1.R0: ENABLED
N4.C3.D1.R1: ENABLED
N4.C3: TermRnkMsk = 0x2000011
N5.C0.D0: Number of ranks = 2
N5.C0.D0.R0: ENABLED
N5.C0.D0.R1: ENABLED
N5.C0: TermRnkMsk = 0x2000001
N5.C1.D0: Number of ranks = 2
N5.C1.D0.R0: ENABLED
N5.C1.D0.R1: ENABLED
N5.C1: TermRnkMsk = 0x2000001
N5.C2.D0: Number of ranks = 2
N5.C2.D0.R0: ENABLED
N5.C2.D0.R1: ENABLED
N5.C2: TermRnkMsk = 0x2000001
N5.C3.D0: Number of ranks = 2
N5.C3.D0.R0: ENABLED
N5.C3.D0.R1: ENABLED
N5.C3: TermRnkMsk = 0x2000001
N6.C0.D0: Number of ranks = 2
N6.C0.D1: Number of ranks = 2
N6.C0.D0.R0: ENABLED
N6.C0.D0.R1: ENABLED
N6.C0.D1.R0: ENABLED
N6.C0.D1.R1: ENABLED
N6.C0: TermRnkMsk = 0x2000011
N6.C1.D0: Number of ranks = 2
N6.C1.D1: Number of ranks = 2
N6.C1.D0.R0: ENABLED
N6.C1.D0.R1: ENABLED
N6.C1.D1.R0: ENABLED
N6.C1.D1.R1: ENABLED
N6.C1: TermRnkMsk = 0x2000011
N6.C2.D0: Number of ranks = 2
N6.C2.D1: Number of ranks = 2
N6.C2.D0.R0: ENABLED
N6.C2.D0.R1: ENABLED
N6.C2.D1.R0: ENABLED
N6.C2.D1.R1: ENABLED
N6.C2: TermRnkMsk = 0x2000011
N6.C3.D0: Number of ranks = 2
N6.C3.D1: Number of ranks = 2
N6.C3.D0.R0: ENABLED
N6.C3.D0.R1: ENABLED
N6.C3.D1.R0: ENABLED
N6.C3.D1.R1: ENABLED
N6.C3: TermRnkMsk = 0x2000011
N7.C0.D0: Number of ranks = 2
N7.C0.D0.R0: ENABLED
N7.C0.D0.R1: ENABLED
N7.C0: TermRnkMsk = 0x2000001
N7.C1.D0: Number of ranks = 2
N7.C1.D0.R0: ENABLED
N7.C1.D0.R1: ENABLED
N7.C1: TermRnkMsk = 0x2000001
N7.C2.D0: Number of ranks = 2
N7.C2.D0.R0: ENABLED
N7.C2.D0.R1: ENABLED
N7.C2: TermRnkMsk = 0x2000001
N7.C3.D0: Number of ranks = 2
N7.C3.D0.R0: ENABLED
N7.C3.D0.R1: ENABLED
N7.C3: TermRnkMsk = 0x2000001
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CheckDimmRanks time            973 ms
Checkpoint Code: Socket 0, 0xB3, 0x00, 0x0000
Capid2.Bits.qpi_allowed_cfclk_ratio_dis = 9 
Capid2.Bits.qpi_allowed_cfclk_ratio_dis = 9 
Capid2.Bits.qpi_allowed_cfclk_ratio_dis = 9 
Capid2.Bits.qpi_allowed_cfclk_ratio_dis = 9 
Capid2.Bits.qpi_allowed_cfclk_ratio_dis = 9 
Capid2.Bits.qpi_allowed_cfclk_ratio_dis = 9 
Capid2.Bits.qpi_allowed_cfclk_ratio_dis = 9 
Capid2.Bits.qpi_allowed_cfclk_ratio_dis = 9 
DDR Freq Limit = 3
Init DDR Clocks
N0.C0: POR Vdd LUT Index = 42
N0.C0: POR Vdd LUT Index = 43
N0.C0: Checks if the requested Vdd 0x02 is supported - SUCCESS
N0.C1: POR Vdd LUT Index = 42
N0.C1: POR Vdd LUT Index = 43
N0.C1: Checks if the requested Vdd 0x02 is supported - SUCCESS
N0.C2: POR Vdd LUT Index = 42
N0.C2: POR Vdd LUT Index = 43
N0.C2: Checks if the requested Vdd 0x02 is supported - SUCCESS
N0.C3: POR Vdd LUT Index = 42
N0.C3: POR Vdd LUT Index = 43
N0.C3: Checks if the requested Vdd 0x02 is supported - SUCCESS
N2.C0: POR Vdd LUT Index = 42
N2.C0: POR Vdd LUT Index = 43
N2.C0: Checks if the requested Vdd 0x02 is supported - SUCCESS
N2.C1: POR Vdd LUT Index = 42
N2.C1: POR Vdd LUT Index = 43
N2.C1: Checks if the requested Vdd 0x02 is supported - SUCCESS
N2.C2: POR Vdd LUT Index = 42
N2.C2: POR Vdd LUT Index = 43
N2.C2: Checks if the requested Vdd 0x02 is supported - SUCCESS
N2.C3: POR Vdd LUT Index = 42
N2.C3: POR Vdd LUT Index = 43
N2.C3: Checks if the requested Vdd 0x02 is supported - SUCCESS
N4.C0: POR Vdd LUT Index = 42
N4.C0: POR Vdd LUT Index = 43
N4.C0: Checks if the requested Vdd 0x02 is supported - SUCCESS
N4.C1: POR Vdd LUT Index = 42
N4.C1: POR Vdd LUT Index = 43
N4.C1: Checks if the requested Vdd 0x02 is supported - SUCCESS
N4.C2: POR Vdd LUT Index = 42
N4.C2: POR Vdd LUT Index = 43
N4.C2: Checks if the requested Vdd 0x02 is supported - SUCCESS
N4.C3: POR Vdd LUT Index = 42
N4.C3: POR Vdd LUT Index = 43
N4.C3: Checks if the requested Vdd 0x02 is supported - SUCCESS
N6.C0: POR Vdd LUT Index = 42
N6.C0: POR Vdd LUT Index = 43
N6.C0: Checks if the requested Vdd 0x02 is supported - SUCCESS
N6.C1: POR Vdd LUT Index = 42
N6.C1: POR Vdd LUT Index = 43
N6.C1: Checks if the requested Vdd 0x02 is supported - SUCCESS
N6.C2: POR Vdd LUT Index = 42
N6.C2: POR Vdd LUT Index = 43
N6.C2: Checks if the requested Vdd 0x02 is supported - SUCCESS
N6.C3: POR Vdd LUT Index = 42
N6.C3: POR Vdd LUT Index = 43
N6.C3: Checks if the requested Vdd 0x02 is supported - SUCCESS
N0: commonTck = 10, ddrFreq set to 3
N0.C0: Common Dram Vdd = 0
N0.C0: GetPORDDRFreq found freqTable LUT index 42. ddrFreq = 2
N0.C0: GetPORDDRFreq = 2
N0.C0: SPD Dimm Freq = 3 vs POR Freq = 2
N0.C0: Freq Override = 2
N0.C1: Common Dram Vdd = 0
N0.C1: GetPORDDRFreq found freqTable LUT index 42. ddrFreq = 2
N0.C1: GetPORDDRFreq = 2
N0.C1: SPD Dimm Freq = 2 vs POR Freq = 2
N0.C1: Freq Override = 2
N0.C2: Common Dram Vdd = 0
N0.C2: GetPORDDRFreq found freqTable LUT index 42. ddrFreq = 2
N0.C2: GetPORDDRFreq = 2
N0.C2: SPD Dimm Freq = 2 vs POR Freq = 2
N0.C2: Freq Override = 2
N0.C3: Common Dram Vdd = 0
N0.C3: GetPORDDRFreq found freqTable LUT index 42. ddrFreq = 2
N0.C3: GetPORDDRFreq = 2
N0.C3: SPD Dimm Freq = 2 vs POR Freq = 2
N0.C3: Freq Override = 2
N0: For JCK1 enforce MaxDdrFreq to be 1333MT/s. The 1600MT/s is not supported for vmse_2xfc 0 in 2:1 mode
N1: commonTck = 10, ddrFreq set to 3
N1.C0: Common Dram Vdd = 0
N1.C0: GetPORDDRFreq found freqTable LUT index 38. ddrFreq = 2
N1.C0: GetPORDDRFreq = 2
N1.C0: SPD Dimm Freq = 3 vs POR Freq = 2
N1.C0: Freq Override = 2
N1.C1: Common Dram Vdd = 0
N1.C1: GetPORDDRFreq found freqTable LUT index 38. ddrFreq = 2
N1.C1: GetPORDDRFreq = 2
N1.C1: SPD Dimm Freq = 2 vs POR Freq = 2
N1.C1: Freq Override = 2
N1.C2: Common Dram Vdd = 0
N1.C2: GetPORDDRFreq found freqTable LUT index 38. ddrFreq = 2
N1.C2: GetPORDDRFreq = 2
N1.C2: SPD Dimm Freq = 2 vs POR Freq = 2
N1.C2: Freq Override = 2
N1.C3: Common Dram Vdd = 0
N1.C3: GetPORDDRFreq found freqTable LUT index 38. ddrFreq = 2
N1.C3: GetPORDDRFreq = 2
N1.C3: SPD Dimm Freq = 2 vs POR Freq = 2
N1.C3: Freq Override = 2
N1: For JCK1 enforce MaxDdrFreq to be 1333MT/s. The 1600MT/s is not supported for vmse_2xfc 0 in 2:1 mode
N2: commonTck = 12, ddrFreq set to 2
N2.C0: Common Dram Vdd = 0
N2.C0: GetPORDDRFreq found freqTable LUT index 42. ddrFreq = 2
N2.C0: GetPORDDRFreq = 2
N2.C0: SPD Dimm Freq = 2 vs POR Freq = 2
N2.C0: Freq Override = 2
N2.C1: Common Dram Vdd = 0
N2.C1: GetPORDDRFreq found freqTable LUT index 42. ddrFreq = 2
N2.C1: GetPORDDRFreq = 2
N2.C1: SPD Dimm Freq = 2 vs POR Freq = 2
N2.C1: Freq Override = 2
N2.C2: Common Dram Vdd = 0
N2.C2: GetPORDDRFreq found freqTable LUT index 42. ddrFreq = 2
N2.C2: GetPORDDRFreq = 2
N2.C2: SPD Dimm Freq = 2 vs POR Freq = 2
N2.C2: Freq Override = 2
N2.C3: Common Dram Vdd = 0
N2.C3: GetPORDDRFreq found freqTable LUT index 42. ddrFreq = 2
N2.C3: GetPORDDRFreq = 2
N2.C3: SPD Dimm Freq = 2 vs POR Freq = 2
N2.C3: Freq Override = 2
N2: For JCK1 enforce MaxDdrFreq to be 1333MT/s. The 1600MT/s is not supported for vmse_2xfc 0 in 2:1 mode
N3: commonTck = 10, ddrFreq set to 3
N3.C0: Common Dram Vdd = 0
N3.C0: GetPORDDRFreq found freqTable LUT index 38. ddrFreq = 2
N3.C0: GetPORDDRFreq = 2
N3.C0: SPD Dimm Freq = 3 vs POR Freq = 2
N3.C0: Freq Override = 2
N3.C1: Common Dram Vdd = 0
N3.C1: GetPORDDRFreq found freqTable LUT index 38. ddrFreq = 2
N3.C1: GetPORDDRFreq = 2
N3.C1: SPD Dimm Freq = 2 vs POR Freq = 2
N3.C1: Freq Override = 2
N3.C2: Common Dram Vdd = 0
N3.C2: GetPORDDRFreq found freqTable LUT index 38. ddrFreq = 2
N3.C2: GetPORDDRFreq = 2
N3.C2: SPD Dimm Freq = 2 vs POR Freq = 2
N3.C2: Freq Override = 2
N3.C3: Common Dram Vdd = 0
N3.C3: GetPORDDRFreq found freqTable LUT index 38. ddrFreq = 2
N3.C3: GetPORDDRFreq = 2
N3.C3: SPD Dimm Freq = 2 vs POR Freq = 2
N3.C3: Freq Override = 2
N3: For JCK1 enforce MaxDdrFreq to be 1333MT/s. The 1600MT/s is not supported for vmse_2xfc 0 in 2:1 mode
N4: commonTck = 10, ddrFreq set to 3
N4.C0: Common Dram Vdd = 0
N4.C0: GetPORDDRFreq found freqTable LUT index 42. ddrFreq = 2
N4.C0: GetPORDDRFreq = 2
N4.C0: SPD Dimm Freq = 3 vs POR Freq = 2
N4.C0: Freq Override = 2
N4.C1: Common Dram Vdd = 0
N4.C1: GetPORDDRFreq found freqTable LUT index 42. ddrFreq = 2
N4.C1: GetPORDDRFreq = 2
N4.C1: SPD Dimm Freq = 2 vs POR Freq = 2
N4.C1: Freq Override = 2
N4.C2: Common Dram Vdd = 0
N4.C2: GetPORDDRFreq found freqTable LUT index 42. ddrFreq = 2
N4.C2: GetPORDDRFreq = 2
N4.C2: SPD Dimm Freq = 2 vs POR Freq = 2
N4.C2: Freq Override = 2
N4.C3: Common Dram Vdd = 0
N4.C3: GetPORDDRFreq found freqTable LUT index 42. ddrFreq = 2
N4.C3: GetPORDDRFreq = 2
N4.C3: SPD Dimm Freq = 2 vs POR Freq = 2
N4.C3: Freq Override = 2
N4: For JCK1 enforce MaxDdrFreq to be 1333MT/s. The 1600MT/s is not supported for vmse_2xfc 0 in 2:1 mode
N5: commonTck = 10, ddrFreq set to 3
N5.C0: Common Dram Vdd = 0
N5.C0: GetPORDDRFreq found freqTable LUT index 38. ddrFreq = 2
N5.C0: GetPORDDRFreq = 2
N5.C0: SPD Dimm Freq = 3 vs POR Freq = 2
N5.C0: Freq Override = 2
N5.C1: Common Dram Vdd = 0
N5.C1: GetPORDDRFreq found freqTable LUT index 38. ddrFreq = 2
N5.C1: GetPORDDRFreq = 2
N5.C1: SPD Dimm Freq = 2 vs POR Freq = 2
N5.C1: Freq Override = 2
N5.C2: Common Dram Vdd = 0
N5.C2: GetPORDDRFreq found freqTable LUT index 38. ddrFreq = 2
N5.C2: GetPORDDRFreq = 2
N5.C2: SPD Dimm Freq = 2 vs POR Freq = 2
N5.C2: Freq Override = 2
N5.C3: Common Dram Vdd = 0
N5.C3: GetPORDDRFreq found freqTable LUT index 38. ddrFreq = 2
N5.C3: GetPORDDRFreq = 2
N5.C3: SPD Dimm Freq = 2 vs POR Freq = 2
N5.C3: Freq Override = 2
N5: For JCK1 enforce MaxDdrFreq to be 1333MT/s. The 1600MT/s is not supported for vmse_2xfc 0 in 2:1 mode
N6: commonTck = 12, ddrFreq set to 2
N6.C0: Common Dram Vdd = 0
N6.C0: GetPORDDRFreq found freqTable LUT index 42. ddrFreq = 2
N6.C0: GetPORDDRFreq = 2
N6.C0: SPD Dimm Freq = 2 vs POR Freq = 2
N6.C0: Freq Override = 2
N6.C1: Common Dram Vdd = 0
N6.C1: GetPORDDRFreq found freqTable LUT index 42. ddrFreq = 2
N6.C1: GetPORDDRFreq = 2
N6.C1: SPD Dimm Freq = 2 vs POR Freq = 2
N6.C1: Freq Override = 2
N6.C2: Common Dram Vdd = 0
N6.C2: GetPORDDRFreq found freqTable LUT index 42. ddrFreq = 2
N6.C2: GetPORDDRFreq = 2
N6.C2: SPD Dimm Freq = 2 vs POR Freq = 2
N6.C2: Freq Override = 2
N6.C3: Common Dram Vdd = 0
N6.C3: GetPORDDRFreq found freqTable LUT index 42. ddrFreq = 2
N6.C3: GetPORDDRFreq = 2
N6.C3: SPD Dimm Freq = 2 vs POR Freq = 2
N6.C3: Freq Override = 2
N6: For JCK1 enforce MaxDdrFreq to be 1333MT/s. The 1600MT/s is not supported for vmse_2xfc 0 in 2:1 mode
N7: commonTck = 10, ddrFreq set to 3
N7.C0: Common Dram Vdd = 0
N7.C0: GetPORDDRFreq found freqTable LUT index 38. ddrFreq = 2
N7.C0: GetPORDDRFreq = 2
N7.C0: SPD Dimm Freq = 3 vs POR Freq = 2
N7.C0: Freq Override = 2
N7.C1: Common Dram Vdd = 0
N7.C1: GetPORDDRFreq found freqTable LUT index 38. ddrFreq = 2
N7.C1: GetPORDDRFreq = 2
N7.C1: SPD Dimm Freq = 2 vs POR Freq = 2
N7.C1: Freq Override = 2
N7.C2: Common Dram Vdd = 0
N7.C2: GetPORDDRFreq found freqTable LUT index 38. ddrFreq = 2
N7.C2: GetPORDDRFreq = 2
N7.C2: SPD Dimm Freq = 2 vs POR Freq = 2
N7.C2: Freq Override = 2
N7.C3: Common Dram Vdd = 0
N7.C3: GetPORDDRFreq found freqTable LUT index 38. ddrFreq = 2
N7.C3: GetPORDDRFreq = 2
N7.C3: SPD Dimm Freq = 2 vs POR Freq = 2
N7.C3: Freq Override = 2
N7: For JCK1 enforce MaxDdrFreq to be 1333MT/s. The 1600MT/s is not supported for vmse_2xfc 0 in 2:1 mode
N8: System common freq = 2
System freq at boot = 2
N0: Node freq = 2
N1: Node freq = 2
N2: Node freq = 2
N3: Node freq = 2
N4: Node freq = 2
N5: Node freq = 2
N6: Node freq = 2
N7: Node freq = 2
Memory behind Node 0 running at DDR Freq - 1333Mhz, Running at VMSE Freq - 2667Mhz in 2:1 mode
Memory behind Node 1 running at DDR Freq - 1333Mhz, Running at VMSE Freq - 2667Mhz in 2:1 mode
Memory behind Node 2 running at DDR Freq - 1333Mhz, Running at VMSE Freq - 2667Mhz in 2:1 mode
Memory behind Node 3 running at DDR Freq - 1333Mhz, Running at VMSE Freq - 2667Mhz in 2:1 mode
Memory behind Node 4 running at DDR Freq - 1333Mhz, Running at VMSE Freq - 2667Mhz in 2:1 mode
Memory behind Node 5 running at DDR Freq - 1333Mhz, Running at VMSE Freq - 2667Mhz in 2:1 mode
Memory behind Node 6 running at DDR Freq - 1333Mhz, Running at VMSE Freq - 2667Mhz in 2:1 mode
Memory behind Node 7 running at DDR Freq - 1333Mhz, Running at VMSE Freq - 2667Mhz in 2:1 mode
Get data from S0 to S1
Get data from S0 to S2
Get data from S0 to S3
N0: SetLowVoltage: Checkpoint Code: Socket 0, 0xB4, 0xFB, 0x0000
Setting N0 Vdd to 1.5V
N0: CMD_ACTIVE_VR_MASK = 0x0, ACTIVE_VR_MASK = 0xF 
N0: DDR Voltage: N0: 1.50V
N0: GetSvidEncodingPerProtocol: VrMode = 0x1, SvidEncodingValue = 0xFB 
N1: SetLowVoltage: Checkpoint Code: Socket 0, 0xB4, 0xFB, 0x0000
Setting N1 Vdd to 1.5V
N1: CMD_ACTIVE_VR_MASK = 0x0, ACTIVE_VR_MASK = 0xF 
N1: DDR Voltage: N1: 1.50V
N1: GetSvidEncodingPerProtocol: VrMode = 0x1, SvidEncodingValue = 0xFB 
N2: SetLowVoltage: Checkpoint Code: Socket 0, 0xB4, 0xFB, 0x0000
Setting N2 Vdd to 1.5V
N2: CMD_ACTIVE_VR_MASK = 0x0, ACTIVE_VR_MASK = 0xF 
N2: DDR Voltage: N2: 1.50V
N2: GetSvidEncodingPerProtocol: VrMode = 0x1, SvidEncodingValue = 0xFB 
N3: SetLowVoltage: Checkpoint Code: Socket 0, 0xB4, 0xFB, 0x0000
Setting N3 Vdd to 1.5V
N3: CMD_ACTIVE_VR_MASK = 0x0, ACTIVE_VR_MASK = 0xF 
N3: DDR Voltage: N3: 1.50V
N3: GetSvidEncodingPerProtocol: VrMode = 0x1, SvidEncodingValue = 0xFB 
N4: SetLowVoltage: Checkpoint Code: Socket 0, 0xB4, 0xFB, 0x0000
Setting N4 Vdd to 1.5V
N4: CMD_ACTIVE_VR_MASK = 0x0, ACTIVE_VR_MASK = 0xF 
N4: DDR Voltage: N4: 1.50V
N4: GetSvidEncodingPerProtocol: VrMode = 0x1, SvidEncodingValue = 0xFB 
N5: SetLowVoltage: Checkpoint Code: Socket 0, 0xB4, 0xFB, 0x0000
Setting N5 Vdd to 1.5V
N5: CMD_ACTIVE_VR_MASK = 0x0, ACTIVE_VR_MASK = 0xF 
N5: DDR Voltage: N5: 1.50V
N5: GetSvidEncodingPerProtocol: VrMode = 0x1, SvidEncodingValue = 0xFB 
N6: SetLowVoltage: Checkpoint Code: Socket 0, 0xB4, 0xFB, 0x0000
Setting N6 Vdd to 1.5V
N6: CMD_ACTIVE_VR_MASK = 0x0, ACTIVE_VR_MASK = 0xF 
N6: DDR Voltage: N6: 1.50V
N6: GetSvidEncodingPerProtocol: VrMode = 0x1, SvidEncodingValue = 0xFB 
N7: SetLowVoltage: Checkpoint Code: Socket 0, 0xB4, 0xFB, 0x0000
Setting N7 Vdd to 1.5V
N7: CMD_ACTIVE_VR_MASK = 0x0, ACTIVE_VR_MASK = 0xF 
N7: DDR Voltage: N7: 1.50V
N7: GetSvidEncodingPerProtocol: VrMode = 0x1, SvidEncodingValue = 0xFB 
Send data from S0 to S1
Send data from S0 to S2
N2: GatherSPDData
Gather SPD Data
N2.C0.D0: tWR in MTB units: 0x78
N4: GatherSPDData
Send data from S0 to S3
Gather SPD Data
N4.C0.D0: tWR in MTB units: 0x78
N6: GatherSPDData
Checkpoint Code: Socket 0, 0xB5, 0x00, 0x0000
Gather SPD Data
N0: GatherSPDData
Gather SPD Data
N6.C0.D0: tWR in MTB units: 0x78
N0.C0.D0: tWR in MTB units: 0x78
N2.C1.D0: tWR in MTB units: 0x78
N4.C1.D0: tWR in MTB units: 0x78
N6.C1.D0: tWR in MTB units: 0x78
N0.C1.D0: tWR in MTB units: 0x78
N2.C2.D0: tWR in MTB units: 0x78
N4.C2.D0: tWR in MTB units: 0x78
N6.C2.D0: tWR in MTB units: 0x78
N0.C2.D0: tWR in MTB units: 0x78
N2.C3.D0: tWR in MTB units: 0x78
N4.C3.D0: tWR in MTB units: 0x78
N6.C3.D0: tWR in MTB units: 0x78
N0.C3.D0: tWR in MTB units: 0x78

GatherSPDData time            194 ms
N2: GlobalEarlyConfig
N2: Global Early Configuration
N2.C0: GlobalEarlyConfig: mcmntChknbit.frc_mddl_on = 1

GatherSPDData time            193 ms
N2.C0.D0: Config DIMMMTR_0_MCDDC_DESC_REG: 000C502D
N4: GlobalEarlyConfig
N2.C0.D1: Config DIMMMTR_0_MCDDC_DESC_REG: 000C502D
N4: Global Early Configuration

GatherSPDData time            193 ms

GatherSPDData time            193 ms
N2.C0: RX Vref Default = 32
N4.C0: GlobalEarlyConfig: mcmntChknbit.frc_mddl_on = 1
N6: GlobalEarlyConfig
N0: GlobalEarlyConfig
N2.C1: GlobalEarlyConfig: mcmntChknbit.frc_mddl_on = 1
N4.C0.D0: Config DIMMMTR_0_MCDDC_DESC_REG: 000C502D
N6: Global Early Configuration
N0: Global Early Configuration
N2.C1.D0: Config DIMMMTR_0_MCDDC_DESC_REG: 000C502D
N4.C0.D1: Config DIMMMTR_0_MCDDC_DESC_REG: 000C502D
N6.C0: GlobalEarlyConfig: mcmntChknbit.frc_mddl_on = 1
N0.C0: GlobalEarlyConfig: mcmntChknbit.frc_mddl_on = 1
N2.C1.D1: Config DIMMMTR_0_MCDDC_DESC_REG: 000C502D
N4.C0: RX Vref Default = 32
N6.C0.D0: Config DIMMMTR_0_MCDDC_DESC_REG: 000C502D
N0.C0.D0: Config DIMMMTR_0_MCDDC_DESC_REG: 000C502D
N2.C1: RX Vref Default = 32
N4.C1: GlobalEarlyConfig: mcmntChknbit.frc_mddl_on = 1
N6.C0.D1: Config DIMMMTR_0_MCDDC_DESC_REG: 000C502D
N0.C0.D1: Config DIMMMTR_0_MCDDC_DESC_REG: 000C502D
N2.C2: GlobalEarlyConfig: mcmntChknbit.frc_mddl_on = 1
N4.C1.D0: Config DIMMMTR_0_MCDDC_DESC_REG: 000C502D
N6.C0: RX Vref Default = 32
N0.C0: RX Vref Default = 32
N2.C2.D0: Config DIMMMTR_0_MCDDC_DESC_REG: 000C502D
N4.C1.D1: Config DIMMMTR_0_MCDDC_DESC_REG: 000C502D
N6.C1: GlobalEarlyConfig: mcmntChknbit.frc_mddl_on = 1
N0.C1: GlobalEarlyConfig: mcmntChknbit.frc_mddl_on = 1
N2.C2.D1: Config DIMMMTR_0_MCDDC_DESC_REG: 000C502D
N4.C1: RX Vref Default = 32
N6.C1.D0: Config DIMMMTR_0_MCDDC_DESC_REG: 000C502D
N0.C1.D0: Config DIMMMTR_0_MCDDC_DESC_REG: 000C502D
N2.C2: RX Vref Default = 32
N4.C2: GlobalEarlyConfig: mcmntChknbit.frc_mddl_on = 1
N6.C1.D1: Config DIMMMTR_0_MCDDC_DESC_REG: 000C502D
N0.C1.D1: Config DIMMMTR_0_MCDDC_DESC_REG: 000C502D
N2.C3: GlobalEarlyConfig: mcmntChknbit.frc_mddl_on = 1
N4.C2.D0: Config DIMMMTR_0_MCDDC_DESC_REG: 000C502D
N6.C1: RX Vref Default = 32
N0.C1: RX Vref Default = 32
N2.C3.D0: Config DIMMMTR_0_MCDDC_DESC_REG: 000C502D
N4.C2.D1: Config DIMMMTR_0_MCDDC_DESC_REG: 000C502D
N6.C2: GlobalEarlyConfig: mcmntChknbit.frc_mddl_on = 1
N0.C2: GlobalEarlyConfig: mcmntChknbit.frc_mddl_on = 1
N2.C3.D1: Config DIMMMTR_0_MCDDC_DESC_REG: 000C502D
N4.C2: RX Vref Default = 32
N6.C2.D0: Config DIMMMTR_0_MCDDC_DESC_REG: 000C502D
N0.C2.D0: Config DIMMMTR_0_MCDDC_DESC_REG: 000C502D
N2.C3: RX Vref Default = 32
N4.C3: GlobalEarlyConfig: mcmntChknbit.frc_mddl_on = 1
N6.C2.D1: Config DIMMMTR_0_MCDDC_DESC_REG: 000C502D
N0.C2.D1: Config DIMMMTR_0_MCDDC_DESC_REG: 000C502D
N2: ChannelEarlyConfig
N4.C3.D0: Config DIMMMTR_0_MCDDC_DESC_REG: 000C502D
N6.C2: RX Vref Default = 32
N0.C2: RX Vref Default = 32
N2: Channel Early Configuration
N4.C3.D1: Config DIMMMTR_0_MCDDC_DESC_REG: 000C502D
N6.C3: GlobalEarlyConfig: mcmntChknbit.frc_mddl_on = 1
N0.C3: GlobalEarlyConfig: mcmntChknbit.frc_mddl_on = 1
N2.C0: Enable = 1
N4.C3: RX Vref Default = 32
N6.C3.D0: Config DIMMMTR_0_MCDDC_DESC_REG: 000C502D
N0.C3.D0: Config DIMMMTR_0_MCDDC_DESC_REG: 000C502D
N2.C0.D0: Enable = 1
N4: ChannelEarlyConfig
N6.C3.D1: Config DIMMMTR_0_MCDDC_DESC_REG: 000C502D
N0.C3.D1: Config DIMMMTR_0_MCDDC_DESC_REG: 000C502D
N2.C0.D0.R0: Enable = 1
N4: Channel Early Configuration
N6.C3: RX Vref Default = 32
N0.C3: RX Vref Default = 32
N2.C0.D0.R0: ENABLED: ckeMask = 00000001
N4.C0: Enable = 1
N6: ChannelEarlyConfig
Checkpoint Code: Socket 0, 0xB8, 0x00, 0x0000
N2.C0.D0.R1: Enable = 1
N4.C0.D0: Enable = 1
N6: Channel Early Configuration
N0: ChannelEarlyConfig
N2.C0.D0.R1: ENABLED: ckeMask = 00000003
N4.C0.D0.R0: Enable = 1
N6.C0: Enable = 1
N0: Channel Early Configuration
N2.C0.D0.R2: Enable = 0
N4.C0.D0.R0: ENABLED: ckeMask = 00000001
N6.C0.D0: Enable = 1
N0.C0: Enable = 1
N2.C0.D0.R3: Enable = 0
N4.C0.D0.R1: Enable = 1
N6.C0.D0.R0: Enable = 1
N0.C0.D0: Enable = 1
N2.C0.D1: Enable = 1
N4.C0.D0.R1: ENABLED: ckeMask = 00000003
N6.C0.D0.R0: ENABLED: ckeMask = 00000001
N0.C0.D0.R0: Enable = 1
N2.C0.D1.R0: Enable = 1
N4.C0.D0.R2: Enable = 0
N6.C0.D0.R1: Enable = 1
N0.C0.D0.R0: ENABLED: ckeMask = 00000001
N2.C0.D1.R0: ENABLED: ckeMask = 00000007
N4.C0.D0.R3: Enable = 0
N6.C0.D0.R1: ENABLED: ckeMask = 00000003
N0.C0.D0.R1: Enable = 1
N2.C0.D1.R1: Enable = 1
N4.C0.D1: Enable = 1
N6.C0.D0.R2: Enable = 0
N0.C0.D0.R1: ENABLED: ckeMask = 00000003
N2.C0.D1.R1: ENABLED: ckeMask = 0000000F
N4.C0.D1.R0: Enable = 1
N6.C0.D0.R3: Enable = 0
N0.C0.D0.R2: Enable = 0
N2.C0.D1.R2: Enable = 0
N4.C0.D1.R0: ENABLED: ckeMask = 00000007
N6.C0.D1: Enable = 1
N0.C0.D0.R3: Enable = 0
N2.C0.D1.R3: Enable = 0
N4.C0.D1.R1: Enable = 1
N6.C0.D1.R0: Enable = 1
N0.C0.D1: Enable = 1
N2.C0.D2: Enable = 0
N4.C0.D1.R1: ENABLED: ckeMask = 0000000F
N6.C0.D1.R0: ENABLED: ckeMask = 00000007
N0.C0.D1.R0: Enable = 1
N2.C1: Enable = 1
N4.C0.D1.R2: Enable = 0
N6.C0.D1.R1: Enable = 1
N0.C0.D1.R0: ENABLED: ckeMask = 00000007
N2.C1.D0: Enable = 1
N4.C0.D1.R3: Enable = 0
N6.C0.D1.R1: ENABLED: ckeMask = 0000000F
N0.C0.D1.R1: Enable = 1
N2.C1.D0.R0: Enable = 1
N4.C0.D2: Enable = 0
N6.C0.D1.R2: Enable = 0
N0.C0.D1.R1: ENABLED: ckeMask = 0000000F
N2.C1.D0.R0: ENABLED: ckeMask = 00000001
N4.C1: Enable = 1
N6.C0.D1.R3: Enable = 0
N0.C0.D1.R2: Enable = 0
N2.C1.D0.R1: Enable = 1
N4.C1.D0: Enable = 1
N6.C0.D2: Enable = 0
N0.C0.D1.R3: Enable = 0
N2.C1.D0.R1: ENABLED: ckeMask = 00000003
N4.C1.D0.R0: Enable = 1
N6.C1: Enable = 1
N0.C0.D2: Enable = 0
N2.C1.D0.R2: Enable = 0
N4.C1.D0.R0: ENABLED: ckeMask = 00000001
N6.C1.D0: Enable = 1
N0.C1: Enable = 1
N2.C1.D0.R3: Enable = 0
N4.C1.D0.R1: Enable = 1
N6.C1.D0.R0: Enable = 1
N0.C1.D0: Enable = 1
N2.C1.D1: Enable = 1
N4.C1.D0.R1: ENABLED: ckeMask = 00000003
N6.C1.D0.R0: ENABLED: ckeMask = 00000001
N0.C1.D0.R0: Enable = 1
N2.C1.D1.R0: Enable = 1
N4.C1.D0.R2: Enable = 0
N6.C1.D0.R1: Enable = 1
N0.C1.D0.R0: ENABLED: ckeMask = 00000001
N2.C1.D1.R0: ENABLED: ckeMask = 00000007
N4.C1.D0.R3: Enable = 0
N6.C1.D0.R1: ENABLED: ckeMask = 00000003
N0.C1.D0.R1: Enable = 1
N2.C1.D1.R1: Enable = 1
N4.C1.D1: Enable = 1
N6.C1.D0.R2: Enable = 0
N0.C1.D0.R1: ENABLED: ckeMask = 00000003
N2.C1.D1.R1: ENABLED: ckeMask = 0000000F
N4.C1.D1.R0: Enable = 1
N6.C1.D0.R3: Enable = 0
N0.C1.D0.R2: Enable = 0
N2.C1.D1.R2: Enable = 0
N4.C1.D1.R0: ENABLED: ckeMask = 00000007
N6.C1.D1: Enable = 1
N0.C1.D0.R3: Enable = 0
N2.C1.D1.R3: Enable = 0
N4.C1.D1.R1: Enable = 1
N6.C1.D1.R0: Enable = 1
N0.C1.D1: Enable = 1
N2.C1.D2: Enable = 0
N4.C1.D1.R1: ENABLED: ckeMask = 0000000F
N6.C1.D1.R0: ENABLED: ckeMask = 00000007
N0.C1.D1.R0: Enable = 1
N2.C2: Enable = 1
N4.C1.D1.R2: Enable = 0
N6.C1.D1.R1: Enable = 1
N0.C1.D1.R0: ENABLED: ckeMask = 00000007
N2.C2.D0: Enable = 1
N4.C1.D1.R3: Enable = 0
N6.C1.D1.R1: ENABLED: ckeMask = 0000000F
N0.C1.D1.R1: Enable = 1
N2.C2.D0.R0: Enable = 1
N4.C1.D2: Enable = 0
N6.C1.D1.R2: Enable = 0
N0.C1.D1.R1: ENABLED: ckeMask = 0000000F
N2.C2.D0.R0: ENABLED: ckeMask = 00000001
N4.C2: Enable = 1
N6.C1.D1.R3: Enable = 0
N0.C1.D1.R2: Enable = 0
N2.C2.D0.R1: Enable = 1
N4.C2.D0: Enable = 1
N6.C1.D2: Enable = 0
N0.C1.D1.R3: Enable = 0
N2.C2.D0.R1: ENABLED: ckeMask = 00000003
N4.C2.D0.R0: Enable = 1
N6.C2: Enable = 1
N0.C1.D2: Enable = 0
N2.C2.D0.R2: Enable = 0
N4.C2.D0.R0: ENABLED: ckeMask = 00000001
N6.C2.D0: Enable = 1
N0.C2: Enable = 1
N2.C2.D0.R3: Enable = 0
N4.C2.D0.R1: Enable = 1
N6.C2.D0.R0: Enable = 1
N0.C2.D0: Enable = 1
N2.C2.D1: Enable = 1
N4.C2.D0.R1: ENABLED: ckeMask = 00000003
N6.C2.D0.R0: ENABLED: ckeMask = 00000001
N0.C2.D0.R0: Enable = 1
N2.C2.D1.R0: Enable = 1
N4.C2.D0.R2: Enable = 0
N6.C2.D0.R1: Enable = 1
N0.C2.D0.R0: ENABLED: ckeMask = 00000001
N2.C2.D1.R0: ENABLED: ckeMask = 00000007
N4.C2.D0.R3: Enable = 0
N6.C2.D0.R1: ENABLED: ckeMask = 00000003
N0.C2.D0.R1: Enable = 1
N2.C2.D1.R1: Enable = 1
N4.C2.D1: Enable = 1
N6.C2.D0.R2: Enable = 0
N0.C2.D0.R1: ENABLED: ckeMask = 00000003
N2.C2.D1.R1: ENABLED: ckeMask = 0000000F
N4.C2.D1.R0: Enable = 1
N6.C2.D0.R3: Enable = 0
N0.C2.D0.R2: Enable = 0
N2.C2.D1.R2: Enable = 0
N4.C2.D1.R0: ENABLED: ckeMask = 00000007
N6.C2.D1: Enable = 1
N0.C2.D0.R3: Enable = 0
N2.C2.D1.R3: Enable = 0
N4.C2.D1.R1: Enable = 1
N6.C2.D1.R0: Enable = 1
N0.C2.D1: Enable = 1
N2.C2.D2: Enable = 0
N4.C2.D1.R1: ENABLED: ckeMask = 0000000F
N6.C2.D1.R0: ENABLED: ckeMask = 00000007
N0.C2.D1.R0: Enable = 1
N2.C3: Enable = 1
N4.C2.D1.R2: Enable = 0
N6.C2.D1.R1: Enable = 1
N0.C2.D1.R0: ENABLED: ckeMask = 00000007
N2.C3.D0: Enable = 1
N4.C2.D1.R3: Enable = 0
N6.C2.D1.R1: ENABLED: ckeMask = 0000000F
N0.C2.D1.R1: Enable = 1
N2.C3.D0.R0: Enable = 1
N4.C2.D2: Enable = 0
N6.C2.D1.R2: Enable = 0
N0.C2.D1.R1: ENABLED: ckeMask = 0000000F
N2.C3.D0.R0: ENABLED: ckeMask = 00000001
N4.C3: Enable = 1
N6.C2.D1.R3: Enable = 0
N0.C2.D1.R2: Enable = 0
N2.C3.D0.R1: Enable = 1
N4.C3.D0: Enable = 1
N6.C2.D2: Enable = 0
N0.C2.D1.R3: Enable = 0
N2.C3.D0.R1: ENABLED: ckeMask = 00000003
N4.C3.D0.R0: Enable = 1
N6.C3: Enable = 1
N0.C2.D2: Enable = 0
N2.C3.D0.R2: Enable = 0
N4.C3.D0.R0: ENABLED: ckeMask = 00000001
N6.C3.D0: Enable = 1
N0.C3: Enable = 1
N2.C3.D0.R3: Enable = 0
N4.C3.D0.R1: Enable = 1
N6.C3.D0.R0: Enable = 1
N0.C3.D0: Enable = 1
N2.C3.D1: Enable = 1
N4.C3.D0.R1: ENABLED: ckeMask = 00000003
N6.C3.D0.R0: ENABLED: ckeMask = 00000001
N0.C3.D0.R0: Enable = 1
N2.C3.D1.R0: Enable = 1
N4.C3.D0.R2: Enable = 0
N6.C3.D0.R1: Enable = 1
N0.C3.D0.R0: ENABLED: ckeMask = 00000001
N2.C3.D1.R0: ENABLED: ckeMask = 00000007
N4.C3.D0.R3: Enable = 0
N6.C3.D0.R1: ENABLED: ckeMask = 00000003
N0.C3.D0.R1: Enable = 1
N2.C3.D1.R1: Enable = 1
N4.C3.D1: Enable = 1
N6.C3.D0.R2: Enable = 0
N0.C3.D0.R1: ENABLED: ckeMask = 00000003
N2.C3.D1.R1: ENABLED: ckeMask = 0000000F
N4.C3.D1.R0: Enable = 1
N6.C3.D0.R3: Enable = 0
N0.C3.D0.R2: Enable = 0
N2.C3.D1.R2: Enable = 0
N4.C3.D1.R0: ENABLED: ckeMask = 00000007
N6.C3.D1: Enable = 1
N0.C3.D0.R3: Enable = 0
N2.C3.D1.R3: Enable = 0
N4.C3.D1.R1: Enable = 1
N6.C3.D1.R0: Enable = 1
N0.C3.D1: Enable = 1
N2.C3.D2: Enable = 0
N4.C3.D1.R1: ENABLED: ckeMask = 0000000F
N6.C3.D1.R0: ENABLED: ckeMask = 00000007
N0.C3.D1.R0: Enable = 1
N2: Memory Timings:
N4.C3.D1.R2: Enable = 0
N6.C3.D1.R1: Enable = 1
N0.C3.D1.R0: ENABLED: ckeMask = 00000007
N2.C0: nCL = 9
N4.C3.D1.R3: Enable = 0
N6.C3.D1.R1: ENABLED: ckeMask = 0000000F
N0.C3.D1.R1: Enable = 1
N2.C0: nCWL = 7
N4.C3.D2: Enable = 0
N6.C3.D1.R2: Enable = 0
N0.C3.D1.R1: ENABLED: ckeMask = 0000000F
N2.C0: nRP = 9
N4: Memory Timings:
N6.C3.D1.R3: Enable = 0
N0.C3.D1.R2: Enable = 0
N2.C0: nRCD = 9
N4.C0: nCL = 9
N6.C3.D2: Enable = 0
N0.C3.D1.R3: Enable = 0
N2.C0: nRRD = 4
N4.C0: nCWL = 7
N6: Memory Timings:
N0.C3.D2: Enable = 0
N2.C0: nWTR = 5
N4.C0: nRP = 9
N6.C0: nCL = 9
N0: Memory Timings:
N2.C0: nRAS = 24
N4.C0: nRCD = 9
N6.C0: nCWL = 7
N0.C0: nCL = 9
N2.C0: nRTP = 5
N4.C0: nRRD = 4
N6.C0: nRP = 9
N0.C0: nCWL = 7
N2.C0: nWR = 10
N4.C0: nWTR = 5
N6.C0: nRCD = 9
N0.C0: nRP = 9
N2.C0: nFAW = 20
N4.C0: nRAS = 24
N6.C0: nRRD = 4
N0.C0: nRCD = 9
N2.C0: nRC = 33
N4.C0: nRTP = 5
N6.C0: nWTR = 5
N0.C0: nRRD = 4
N2.C0: nRFC = 107
N4.C0: nWR = 10
N6.C0: nRAS = 24
N0.C0: nWTR = 5
N2.C0: casSup = 0x3C
N4.C0: nFAW = 20
N6.C0: nRTP = 5
N0.C0: nRAS = 24
N2.C0: trrMode = 0
N4.C0: nRC = 33
N6.C0: nWR = 10
N0.C0: nRTP = 5
N2.C0: twoXRefresh = 0
N4.C0: nRFC = 107
N6.C0: nFAW = 20
N0.C0: nWR = 10
N2.C0: t_stagger_ref = 0x4B
N4.C0: casSup = 0xFC
N6.C0: nRC = 33
N0.C0: nFAW = 20
N2.C0: tcsrftp.Bits.t_xsdll = 512
N4.C0: trrMode = 0
N6.C0: nRFC = 107
N0.C0: nRC = 33
N2.C0: Common CL = 9
Common CWL = 7
N4.C0: twoXRefresh = 0
N6.C0: casSup = 0x3C
N0.C0: nRFC = 107
N2: Memory Timings:
N4.C0: t_stagger_ref = 0x4B
N6.C0: trrMode = 0
N0.C0: casSup = 0xFC
N2.C1: nCL = 9
N4.C0: tcsrftp.Bits.t_xsdll = 512
N6.C0: twoXRefresh = 0
N0.C0: trrMode = 0
N2.C1: nCWL = 7
N4.C0: Common CL = 9
Common CWL = 7
N6.C0: t_stagger_ref = 0x4B
N0.C0: twoXRefresh = 0
N2.C1: nRP = 9
N4: Memory Timings:
N6.C0: tcsrftp.Bits.t_xsdll = 512
N0.C0: t_stagger_ref = 0x4B
N2.C1: nRCD = 9
N4.C1: nCL = 9
N6.C0: Common CL = 9
Common CWL = 7
N0.C0: tcsrftp.Bits.t_xsdll = 512
N2.C1: nRRD = 4
N4.C1: nCWL = 7
N6: Memory Timings:
N0.C0: Common CL = 9
Common CWL = 7
N2.C1: nWTR = 5
N4.C1: nRP = 9
N6.C1: nCL = 9
N0: Memory Timings:
N2.C1: nRAS = 24
N4.C1: nRCD = 9
N6.C1: nCWL = 7
N0.C1: nCL = 9
N2.C1: nRTP = 5
N4.C1: nRRD = 4
N6.C1: nRP = 9
N0.C1: nCWL = 7
N2.C1: nWR = 10
N4.C1: nWTR = 5
N6.C1: nRCD = 9
N0.C1: nRP = 9
N2.C1: nFAW = 20
N4.C1: nRAS = 24
N6.C1: nRRD = 4
N0.C1: nRCD = 9
N2.C1: nRC = 33
N4.C1: nRTP = 5
N6.C1: nWTR = 5
N0.C1: nRRD = 4
N2.C1: nRFC = 107
N4.C1: nWR = 10
N6.C1: nRAS = 24
N0.C1: nWTR = 5
N2.C1: casSup = 0x3C
N4.C1: nFAW = 20
N6.C1: nRTP = 5
N0.C1: nRAS = 24
N2.C1: trrMode = 0
N4.C1: nRC = 33
N6.C1: nWR = 10
N0.C1: nRTP = 5
N2.C1: twoXRefresh = 0
N4.C1: nRFC = 107
N6.C1: nFAW = 20
N0.C1: nWR = 10
N2.C1: t_stagger_ref = 0x4B
N4.C1: casSup = 0xFC
N6.C1: nRC = 33
N0.C1: nFAW = 20
N2.C1: tcsrftp.Bits.t_xsdll = 512
N4.C1: trrMode = 0
N6.C1: nRFC = 107
N0.C1: nRC = 33
N2.C1: Common CL = 9
Common CWL = 7
N4.C1: twoXRefresh = 0
N6.C1: casSup = 0x3C
N0.C1: nRFC = 107
N2: Memory Timings:
N4.C1: t_stagger_ref = 0x4B
N6.C1: trrMode = 0
N0.C1: casSup = 0xFC
N2.C2: nCL = 9
N4.C1: tcsrftp.Bits.t_xsdll = 512
N6.C1: twoXRefresh = 0
N0.C1: trrMode = 0
N2.C2: nCWL = 7
N4.C1: Common CL = 9
Common CWL = 7
N6.C1: t_stagger_ref = 0x4B
N0.C1: twoXRefresh = 0
N2.C2: nRP = 9
N4: Memory Timings:
N6.C1: tcsrftp.Bits.t_xsdll = 512
N0.C1: t_stagger_ref = 0x4B
N2.C2: nRCD = 9
N4.C2: nCL = 9
N6.C1: Common CL = 9
Common CWL = 7
N0.C1: tcsrftp.Bits.t_xsdll = 512
N2.C2: nRRD = 4
N4.C2: nCWL = 7
N6: Memory Timings:
N0.C1: Common CL = 9
Common CWL = 7
N2.C2: nWTR = 5
N4.C2: nRP = 9
N6.C2: nCL = 9
N0: Memory Timings:
N2.C2: nRAS = 24
N4.C2: nRCD = 9
N6.C2: nCWL = 7
N0.C2: nCL = 9
N2.C2: nRTP = 5
N4.C2: nRRD = 4
N6.C2: nRP = 9
N0.C2: nCWL = 7
N2.C2: nWR = 10
N4.C2: nWTR = 5
N6.C2: nRCD = 9
N0.C2: nRP = 9
N2.C2: nFAW = 20
N4.C2: nRAS = 24
N6.C2: nRRD = 4
N0.C2: nRCD = 9
N2.C2: nRC = 33
N4.C2: nRTP = 5
N6.C2: nWTR = 5
N0.C2: nRRD = 4
N2.C2: nRFC = 107
N4.C2: nWR = 10
N6.C2: nRAS = 24
N0.C2: nWTR = 5
N2.C2: casSup = 0x3C
N4.C2: nFAW = 20
N6.C2: nRTP = 5
N0.C2: nRAS = 24
N2.C2: trrMode = 0
N4.C2: nRC = 33
N6.C2: nWR = 10
N0.C2: nRTP = 5
N2.C2: twoXRefresh = 0
N4.C2: nRFC = 107
N6.C2: nFAW = 20
N0.C2: nWR = 10
N2.C2: t_stagger_ref = 0x4B
N4.C2: casSup = 0xFC
N6.C2: nRC = 33
N0.C2: nFAW = 20
N2.C2: tcsrftp.Bits.t_xsdll = 512
N4.C2: trrMode = 0
N6.C2: nRFC = 107
N0.C2: nRC = 33
N2.C2: Common CL = 9
Common CWL = 7
N4.C2: twoXRefresh = 0
N6.C2: casSup = 0x3C
N0.C2: nRFC = 107
N2: Memory Timings:
N4.C2: t_stagger_ref = 0x4B
N6.C2: trrMode = 0
N0.C2: casSup = 0xFC
N2.C3: nCL = 9
N4.C2: tcsrftp.Bits.t_xsdll = 512
N6.C2: twoXRefresh = 0
N0.C2: trrMode = 0
N2.C3: nCWL = 7
N4.C2: Common CL = 9
Common CWL = 7
N6.C2: t_stagger_ref = 0x4B
N0.C2: twoXRefresh = 0
N2.C3: nRP = 9
N4: Memory Timings:
N6.C2: tcsrftp.Bits.t_xsdll = 512
N0.C2: t_stagger_ref = 0x4B
N2.C3: nRCD = 9
N4.C3: nCL = 9
N6.C2: Common CL = 9
Common CWL = 7
N0.C2: tcsrftp.Bits.t_xsdll = 512
N2.C3: nRRD = 4
N4.C3: nCWL = 7
N6: Memory Timings:
N0.C2: Common CL = 9
Common CWL = 7
N2.C3: nWTR = 5
N4.C3: nRP = 9
N6.C3: nCL = 9
N0: Memory Timings:
N2.C3: nRAS = 24
N4.C3: nRCD = 9
N6.C3: nCWL = 7
N0.C3: nCL = 9
N2.C3: nRTP = 5
N4.C3: nRRD = 4
N6.C3: nRP = 9
N0.C3: nCWL = 7
N2.C3: nWR = 10
N4.C3: nWTR = 5
N6.C3: nRCD = 9
N0.C3: nRP = 9
N2.C3: nFAW = 20
N4.C3: nRAS = 24
N6.C3: nRRD = 4
N0.C3: nRCD = 9
N2.C3: nRC = 33
N4.C3: nRTP = 5
N6.C3: nWTR = 5
N0.C3: nRRD = 4
N2.C3: nRFC = 107
N4.C3: nWR = 10
N6.C3: nRAS = 24
N0.C3: nWTR = 5
N2.C3: casSup = 0x3C
N4.C3: nFAW = 20
N6.C3: nRTP = 5
N0.C3: nRAS = 24
N2.C3: trrMode = 0
N4.C3: nRC = 33
N6.C3: nWR = 10
N0.C3: nRTP = 5
N2.C3: twoXRefresh = 0
N4.C3: nRFC = 107
N6.C3: nFAW = 20
N0.C3: nWR = 10
N2.C3: t_stagger_ref = 0x4B
N4.C3: casSup = 0xFC
N6.C3: nRC = 33
N0.C3: nFAW = 20
N2.C3: tcsrftp.Bits.t_xsdll = 512
N4.C3: trrMode = 0
N6.C3: nRFC = 107
N0.C3: nRC = 33
N2.C3: Common CL = 9
Common CWL = 7
N4.C3: twoXRefresh = 0
N6.C3: casSup = 0x3C
N0.C3: nRFC = 107
N2: PreVmseTraining
N4.C3: t_stagger_ref = 0x4B
N6.C3: trrMode = 0
N0.C3: casSup = 0xFC
N2.C0: InitHostVmseCfg
N4.C3: tcsrftp.Bits.t_xsdll = 512
N6.C3: twoXRefresh = 0
N0.C3: trrMode = 0
N2.C0: vmse_wr_turnaround = 0x7 
N4.C3: Common CL = 9
Common CWL = 7
N6.C3: t_stagger_ref = 0x4B
N0.C3: twoXRefresh = 0
N2.C2: InitHostVmseCfg
N4: PreVmseTraining
N6.C3: tcsrftp.Bits.t_xsdll = 512
N0.C3: t_stagger_ref = 0x4B
N2.C2: vmse_wr_turnaround = 0x7 
N4.C0: InitHostVmseCfg
N6.C3: Common CL = 9
Common CWL = 7
N0.C3: tcsrftp.Bits.t_xsdll = 512
N2: HsxInitDdrioInterface
N4.C0: vmse_wr_turnaround = 0x7 
N6: PreVmseTraining
N0.C3: Common CL = 9
Common CWL = 7
N2.C0: rxVref = 0x5F
N4.C2: InitHostVmseCfg
N6.C0: InitHostVmseCfg
Checkpoint Code: Socket 0, 0xB6, 0x00, 0x0000
N2.C1: rxVref = 0x5F
N4.C2: vmse_wr_turnaround = 0x7 
N6.C0: vmse_wr_turnaround = 0x7 
N0: PreVmseTraining
N2: HsxVmseCompInit
N4: HsxInitDdrioInterface
N6.C2: InitHostVmseCfg
Checkpoint Code: Socket 0, 0xB6, 0x01, 0x0000
N2: VmseCrossoverCalib
N2: Enable xovercal
N2: vmse_modes =          1,  0
N2.C0: piDelay CMDn  CMDs  CTL  CKE  CLK   0  1  2  3  4  5  6  7  8  9 10 11 12 13 14 15 16 17
          0       0     0    0    0    0   1  1  1  1  0  0  1  1  0  1  1  1  1  0  0  1  1  0 
          1       0     0    0    0    0   1  1  1  1  0  1  1  1  0  1  1  1  1  0  1  1  1  0 
          2       0     0    0    0    0   1  1  1  1  0  1  1  1  1  1  1  1  1  0  1  1  1  1 
          3       0     0    1    0    0   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
          4       0     0    1    0    0   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
          5       0     0    1    1    0   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
          6       0     0    1    1    0   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
          7       0     0    1    1    0   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
          8       0     0    1    1    0   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
          9       0     0    1    1    0   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         10       0     0    1    1    0   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         11       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         12       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         13       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         14       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         15       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         16       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         17       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         18       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         19       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         20       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         21       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         22       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         23       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         24       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         25       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         26       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         27       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         28       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         29       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         30       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         31       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         32       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         33       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         34       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         35       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         36       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         37       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         38       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         39       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         40       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         41       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         42       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         43       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         44       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         45       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         46       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         47       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         48       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         49       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         50       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         51       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         52       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         53       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         54       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         55       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         56       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         57       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         58       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         59       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         60       0     0    1    1    1   0  1  1  1  1  1  1  1  1  0  1  1  1  1  1  1  1  1 
         61       0     0    1    1    1   X  0  1  1  1  1  1  1  1  X  0  1  1  1  1  1  1  1 
         62       0     0    1    1    1   X  X  1  1  1  1  1  1  1  X  X  1  1  1  1  1  1  1 
         63       0     0    1    1    1   X  X  1  1  1  1  1  0  1  X  X  1  1  1  1  1  0  1 
N2.C0: setting ddrcrinvertpiclk
          0       0     0    1    1    1   X  X  0  1  1  1  0  X  1  X  X  0  1  1  1  0  X  1 
          1       0     0    1    1    1   X  X  0  1  1  1  0  X  1  X  X  0  1  1  1  0  X  1 
          2       0     0    1    1    1   X  X  0  0  1  1  0  X  1  X  X  0  0  1  1  0  X  1 
          3       0     0    1    1    1   X  X  0  X  1  0  0  X  0  X  X  0  X  1  0  0  X  0 
          4       0     0    0    1    1   X  X  0  X  0  X  0  X  X  X  X  0  X  0  X  0  X  X 
          5       0     0    X    1    1   X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0  X  X 
          6       0     0    X    1    1   X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0  X  X 
          7       0     0    X    0    1   X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0  X  X 
          8       0     0    X    X    1   X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0  X  X 
          9       0     0    X    X    1   X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0  X  X 
         10       0     0    X    X    1   X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0  X  X 
         11       0     0    X    X    1   X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0  X  X 
         12       0     0    X    X    0   X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0  X  X 
         13       0     0    X    X    X   X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0  X  X 
         14       0     0    X    X    X   X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0  X  X 
         15       0     0    X    X    X   X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0  X  X 
         16       0     0    X    X    X   X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0  X  X 
         17       0     0    X    X    X   X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0  X  X 
         18       0     0    X    X    X   X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0  X  X 
         19       0     0    X    X    X   X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0  X  X 
         20       0     0    X    X    X   X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0  X  X 
         21       0     0    X    X    X   X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0  X  X 
         22       0     0    X    X    X   X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0  X  X 
         23       0     0    X    X    X   X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0  X  X 
         24       0     0    X    X    X   X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0  X  X 
         25       0     0    X    X    X   X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0  X  X 
         26       0     0    X    X    X   X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0  X  X 
         27       0     0    X    X    X   X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0  X  X 
         28       0     0    X    X    X   X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0  X  X 
         29       0     0    X    X    X   X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0  X  X 
         30       0     0    X    X    X   X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0  X  X 
         31       0     0    X    X    X   X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0  X  X 
         32       0     0    X    X    X   X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0  X  X 
         33       0     0    X    X    X   X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0  X  X 
         34       0     0    X    X    X   X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0  X  X 
         35       0     0    X    X    X   X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0  X  X 
         36       0     0    X    X    X   X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0  X  X 
         37       0     0    X    X    X   X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0  X  X 
         38       0     0    X    X    X   X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0  X  X 
         39       0     0    X    X    X   X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0  X  X 
         40       0     0    X    X    X   X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0  X  X 
         41       0     0    X    X    X   X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0  X  X 
         42       0     0    X    X    X   X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0  X  X 
         43       0     0    X    X    X   X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0  X  X 
         44       0     0    X    X    X   X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0  X  X 
         45       0     0    X    X    X   X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0  X  X 
         46       0     0    X    X    X   X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0  X  X 
         47       0     0    X    X    X   X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0  X  X 
         48       0     0    X    X    X   X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0  X  X 
         49       0     0    X    X    X   X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0  X  X 
         50       0     0    X    X    X   X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0  X  X 
         51       0     0    X    X    X   X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0  X  X 
         52       0     0    X    X    X   X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0  X  X 
         53       0     0    X    X    X   X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0  X  X 
         54       0     0    X    X    X   X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0  X  X 
         55       0     0    X    X    X   X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0  X  X 
         56       0     0    X    X    X   X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0  X  X 
         57       0     0    X    X    X   X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0  X  X 
         58       0     0    X    X    X   X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0  X  X 
         59       0     0    X    X    X   X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0  X  X 
         60       0     0    X    X    X   X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0  X  X 
         61       0     0    X    X    X   X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0  X  X 
         62       0     0    X    X    X   X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0  X  X 
         63       0     0    X    X    X   X  X  1  X  X  X  1  X  X  X  X  1  X  X  X  1  X  X 
N2.C0: CMD-N xovercal offset = 0
N2.C0: CMD-S xovercal offset = 0
N2.C0: CTL xovercal offset   = 4
N2.C0: CKE xovercal offset   = 7
N2.C0: CLK xovercal offset   = 12
N2.C0.S18: STROBE                     0   1   2   3   4   5   6   7   8   9  10  11  12  13  14  15  16  17
N2.C0.S18: Rec En xovercal offset =  60  61   0   2   4   3   0  63   3  60  61   0   2   4   3   0  63   3 
N2.C0.S18: Tx Dqs xovercal offset =  60  63   0  63  63  63   0  63  63  63  63   0  63  63  63   0  63  63 
N2.C0.S18: Tx Dq xovercal offset  =  60  61   0   2   4   3   0  63   3  60  61   0   2   4   3   0  63   3 
N2.C0:         CMDn  CMDs  CTL  CKE  CLK   0  1  2  3  4  5  6  7  8
N2.C0: offsets:  0     0     4N2: getComplexCkeSetupTime defaultOffset = 98
N2: getComplexCkeSetupTime = 98
    7   12
Ctl Offsets Delta / final ctl offset / final cke offset /  98  /  38  /   9
Cke invertpiclk / Ctl invertpiclk / 0x0  /  0x0
N2: getComplexClkSetupTime defaultOffset = 0
N2: getComplexClkSetupTime = 0
ClkSetupTime = 12
N2: getComplexDqSetupTime defaultOffset = 0
N2: getComplexDqSetupTime = 0
N2.C0.S00: txdqoffset delta = 0, dq invertpiclk = 0
N2: getComplexDqsSetupTime defaultOffset = 40
N2: getComplexDqsSetupTime = 40
N2.C0.S00: txdqsoffset delta = 40
N2: getComplexRcvEnSetupTime defaultOffset = 37
N2: getComplexRcvEnSetupTime = 37
N2.C0.S00: rcvenoffset delta = 37
N2.C0.S00: Final txdqoffset / txdqsoffset / rcvenoffset / 28 /  4 /  1
N2: getComplexDqSetupTime defaultOffset = 0
N2: getComplexDqSetupTime = 0
N2.C0.S01: txdqoffset delta = 0, dq invertpiclk = 0
N2: getComplexDqsSetupTime defaultOffset = 40
N2: getComplexDqsSetupTime = 40
N2.C0.S01: txdqsoffset delta = 40
N2: getComplexRcvEnSetupTime defaultOffset = 37
N2: getComplexRcvEnSetupTime = 37
N2.C0.S01: rcvenoffset delta = 37
N2.C0.S01: Final txdqoffset / txdqsoffset / rcvenoffset / 61 / 37 / 34
N2: getComplexDqSetupTime defaultOffset = 0
N2: getComplexDqSetupTime = 0
N2.C0.S02: txdqoffset delta = 0, dq invertpiclk = 3
N2: getComplexDqsSetupTime defaultOffset = 40
N2: getComplexDqsSetupTime = 40
N2.C0.S02: txdqsoffset delta = 40
N2: getComplexRcvEnSetupTime defaultOffset = 37
N2: getComplexRcvEnSetupTime = 37
N2.C0.S02: rcvenoffset delta = 37
N2.C0.S02: Final txdqoffset / txdqsoffset / rcvenoffset / 32 /  8 /  5
N2: getComplexDqSetupTime defaultOffset = 0
N2: getComplexDqSetupTime = 0
N2.C0.S03: txdqoffset delta = 0, dq invertpiclk = 3
N2: getComplexDqsSetupTime defaultOffset = 40
N2: getComplexDqsSetupTime = 40
N2.C0.S03: txdqsoffset delta = 40
N2: getComplexRcvEnSetupTime defaultOffset = 37
N2: getComplexRcvEnSetupTime = 37
N2.C0.S03: rcvenoffset delta = 37
N2.C0.S03: Final txdqoffset / txdqsoffset / rcvenoffset /  2 / 42 / 39
N2: getComplexDqSetupTime defaultOffset = 0
N2: getComplexDqSetupTime = 0
N2.C0.S04: txdqoffset delta = 0, dq invertpiclk = 3
N2: getComplexDqsSetupTime defaultOffset = 40
N2: getComplexDqsSetupTime = 40
N2.C0.S04: txdqsoffset delta = 40
N2: getComplexRcvEnSetupTime defaultOffset = 37
N2: getComplexRcvEnSetupTime = 37
N2.C0.S04: rcvenoffset delta = 37
N2.C0.S04: Final txdqoffset / txdqsoffset / rcvenoffset / 36 / 12 /  9
N2: getComplexDqSetupTime defaultOffset = 0
N2: getComplexDqSetupTime = 0
N2.C0.S05: txdqoffset delta = 0, dq invertpiclk = 3
N2: getComplexDqsSetupTime defaultOffset = 40
N2: getComplexDqsSetupTime = 40
N2.C0.S05: txdqsoffset delta = 40
N2: getComplexRcvEnSetupTime defaultOffset = 37
N2: getComplexRcvEnSetupTime = 37
N2.C0.S05: rcvenoffset delta = 37
N2.C0.S05: Final txdqoffset / txdqsoffset / rcvenoffset /  3 / 43 / 40
N2: getComplexDqSetupTime defaultOffset = 0
N2: getComplexDqSetupTime = 0
N2.C0.S06: txdqoffset delta = 0, dq invertpiclk = 3
N2: getComplexDqsSetupTime defaultOffset = 40
N2: getComplexDqsSetupTime = 40
N2.C0.S06: txdqsoffset delta = 40
N2: getComplexRcvEnSetupTime defaultOffset = 37
N2: getComplexRcvEnSetupTime = 37
N2.C0.S06: rcvenoffset delta = 37
N2.C0.S06: Final txdqoffset / txdqsoffset / rcvenoffset / 32 /  8 /  5
N2: getComplexDqSetupTime defaultOffset = 0
N2: getComplexDqSetupTime = 0
N2.C0.S07: txdqoffset delta = 0, dq invertpiclk = 0
N2: getComplexDqsSetupTime defaultOffset = 40
N2: getComplexDqsSetupTime = 40
N2.C0.S07: txdqsoffset delta = 40
N2: getComplexRcvEnSetupTime defaultOffset = 37
N2: getComplexRcvEnSetupTime = 37
N2.C0.S07: rcvenoffset delta = 37
N2.C0.S07: Final txdqoffset / txdqsoffset / rcvenoffset / 63 / 39 / 36
N2: getComplexDqSetupTime defaultOffset = 0
N2: getComplexDqSetupTime = 0
N2.C0.S08: txdqoffset delta = 0, dq invertpiclk = 3
N2: getComplexDqsSetupTime defaultOffset = 40
N2: getComplexDqsSetupTime = 40
N2.C0.S08: txdqsoffset delta = 40
N2: getComplexRcvEnSetupTime defaultOffset = 37
N2: getComplexRcvEnSetupTime = 37
N2.C0.S08: rcvenoffset delta = 37
N2.C0.S08: Final txdqoffset / txdqsoffset / rcvenoffset / 35 / 11 /  8

N2: vmse_modes =          1,  0
N2.C1: piDelay CMDn  CMDs  CTL  CKE  CLK   0  1  2  3  4  5  6  7  8  9 10 11 12 13 14 15 16 17
          0       0     0    1    0    0   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
          1       0     0    1    0    0   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
          2       0     0    1    1    0   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
          3       0     0    1    1    0   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
          4       0     0    1    1    0   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
          5       0     0    1    1    0   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
          6       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
          7       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
          8       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
          9       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         10       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         11       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         12       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         13       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         14       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         15       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         16       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         17       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         18       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         19       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         20       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         21       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         22       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         23       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         24       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         25       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         26       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         27       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         28       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         29       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         30       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         31       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         32       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         33       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         34       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         35       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         36       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         37       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         38       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         39       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         40       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         41       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         42       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         43       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         44       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         45       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         46       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         47       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         48       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         49       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         50       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         51       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         52       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         53       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         54       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         55       0     0    1    1    1   0  1  1  1  1  1  1  1  1  0  1  1  1  1  1  1  1  1 
         56       0     0    1    1    1   X  1  1  1  1  1  1  1  1  X  1  1  1  1  1  1  1  1 
         57       0     0    1    1    1   X  0  1  1  1  1  1  1  1  X  0  1  1  1  1  1  1  1 
         58       0     0    1    1    1   X  X  1  1  1  1  1  1  1  X  X  1  1  1  1  1  1  1 
         59       0     0    1    1    1   X  X  1  1  1  1  1  1  1  X  X  1  1  1  1  1  1  1 
         60       0     0    1    1    1   X  X  0  1  1  1  1  0  1  X  X  0  1  1  1  1  0  1 
         61       0     0    1    1    1   X  X  X  1  1  1  0  X  1  X  X  X  1  1  1  0  X  1 
         62       0     0    1    1    1   X  X  X  1  1  1  X  X  1  X  X  X  1  1  1  X  X  1 
         63       0     0    1    1    1   X  X  X  0  1  0  X  X  1  X  X  X  0  1  0  X  X  1 
N2.C1: setting ddrcrinvertpiclk
          0       0     0    0    1    1   X  X  X  X  1  X  X  X  0  X  X  X  X  1  X  X  X  0 
          1       0     0    0    1    1   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
          2       0     0    0    1    1   X  X  X  X  X  X  X  X  0  X  X  X  X  X  X  X  X  0 
          3       0     0    0    0    1   X  X  X  X  X  X  X  X  0  X  X  X  X  X  X  X  X  0 
          4       0     0    0    X    1   X  X  X  X  X  X  X  X  0  X  X  X  X  X  X  X  X  0 
          5       0     0    0    X    1   X  X  X  X  X  X  X  X  0  X  X  X  X  X  X  X  X  0 
          6       0     0    0    X    1   X  X  X  X  X  X  X  X  0  X  X  X  X  X  X  X  X  0 
          7       0     0    0    X    1   X  X  X  X  X  X  X  X  0  X  X  X  X  X  X  X  X  0 
          8       0     0    0    X    0   X  X  X  X  X  X  X  X  0  X  X  X  X  X  X  X  X  0 
          9       0     0    0    X    X   X  X  X  X  X  X  X  X  0  X  X  X  X  X  X  X  X  0 
         10       0     0    0    X    X   X  X  X  X  X  X  X  X  0  X  X  X  X  X  X  X  X  0 
         11       0     0    0    X    X   X  X  X  X  X  X  X  X  0  X  X  X  X  X  X  X  X  0 
         12       0     0    0    X    X   X  X  X  X  X  X  X  X  0  X  X  X  X  X  X  X  X  0 
         13       0     0    0    X    X   X  X  X  X  X  X  X  X  0  X  X  X  X  X  X  X  X  0 
         14       0     0    0    X    X   X  X  X  X  X  X  X  X  0  X  X  X  X  X  X  X  X  0 
         15       0     0    0    X    X   X  X  X  X  X  X  X  X  0  X  X  X  X  X  X  X  X  0 
         16       0     0    0    X    X   X  X  X  X  X  X  X  X  0  X  X  X  X  X  X  X  X  0 
         17       0     0    0    X    X   X  X  X  X  X  X  X  X  0  X  X  X  X  X  X  X  X  0 
         18       0     0    0    X    X   X  X  X  X  X  X  X  X  0  X  X  X  X  X  X  X  X  0 
         19       0     0    0    X    X   X  X  X  X  X  X  X  X  0  X  X  X  X  X  X  X  X  0 
         20       0     0    0    X    X   X  X  X  X  X  X  X  X  0  X  X  X  X  X  X  X  X  0 
         21       0     0    0    X    X   X  X  X  X  X  X  X  X  0  X  X  X  X  X  X  X  X  0 
         22       0     0    0    X    X   X  X  X  X  X  X  X  X  0  X  X  X  X  X  X  X  X  0 
         23       0     0    0    X    X   X  X  X  X  X  X  X  X  0  X  X  X  X  X  X  X  X  0 
         24       0     0    0    X    X   X  X  X  X  X  X  X  X  0  X  X  X  X  X  X  X  X  0 
         25       0     0    0    X    X   X  X  X  X  X  X  X  X  0  X  X  X  X  X  X  X  X  0 
         26       0     0    0    X    X   X  X  X  X  X  X  X  X  0  X  X  X  X  X  X  X  X  0 
         27       0     0    0    X    X   X  X  X  X  X  X  X  X  0  X  X  X  X  X  X  X  X  0 
         28       0     0    0    X    X   X  X  X  X  X  X  X  X  0  X  X  X  X  X  X  X  X  0 
         29       0     0    0    X    X   X  X  X  X  X  X  X  X  0  X  X  X  X  X  X  X  X  0 
         30       0     0    0    X    X   X  X  X  X  X  X  X  X  0  X  X  X  X  X  X  X  X  0 
         31       0     0    0    X    X   X  X  X  X  X  X  X  X  0  X  X  X  X  X  X  X  X  0 
         32       0     0    0    X    X   X  X  X  X  X  X  X  X  0  X  X  X  X  X  X  X  X  0 
         33       0     0    0    X    X   X  X  X  X  X  X  X  X  0  X  X  X  X  X  X  X  X  0 
         34       0     0    0    X    X   X  X  X  X  X  X  X  X  0  X  X  X  X  X  X  X  X  0 
         35       0     0    0    X    X   X  X  X  X  X  X  X  X  0  X  X  X  X  X  X  X  X  0 
         36       0     0    0    X    X   X  X  X  X  X  X  X  X  0  X  X  X  X  X  X  X  X  0 
         37       0     0    0    X    X   X  X  X  X  X  X  X  X  0  X  X  X  X  X  X  X  X  0 
         38       0     0    0    X    X   X  X  X  X  X  X  X  X  0  X  X  X  X  X  X  X  X  0 
         39       0     0    0    X    X   X  X  X  X  X  X  X  X  0  X  X  X  X  X  X  X  X  0 
         40       0     0    0    X    X   X  X  X  X  X  X  X  X  0  X  X  X  X  X  X  X  X  0 
         41       0     0    0    X    X   X  X  X  X  X  X  X  X  0  X  X  X  X  X  X  X  X  0 
         42       0     0    0    X    X   X  X  X  X  X  X  X  X  0  X  X  X  X  X  X  X  X  0 
         43       0     0    0    X    X   X  X  X  X  X  X  X  X  0  X  X  X  X  X  X  X  X  0 
         44       0     0    0    X    X   X  X  X  X  X  X  X  X  0  X  X  X  X  X  X  X  X  0 
         45       0     0    0    X    X   X  X  X  X  X  X  X  X  0  X  X  X  X  X  X  X  X  0 
         46       0     0    0    X    X   X  X  X  X  X  X  X  X  0  X  X  X  X  X  X  X  X  0 
         47       0     0    0    X    X   X  X  X  X  X  X  X  X  0  X  X  X  X  X  X  X  X  0 
         48       0     0    0    X    X   X  X  X  X  X  X  X  X  0  X  X  X  X  X  X  X  X  0 
         49       0     0    0    X    X   X  X  X  X  X  X  X  X  0  X  X  X  X  X  X  X  X  0 
         50       0     0    0    X    X   X  X  X  X  X  X  X  X  0  X  X  X  X  X  X  X  X  0 
         51       0     0    0    X    X   X  X  X  X  X  X  X  X  0  X  X  X  X  X  X  X  X  0 
         52       0     0    0    X    X   X  X  X  X  X  X  X  X  0  X  X  X  X  X  X  X  X  0 
         53       0     0    0    X    X   X  X  X  X  X  X  X  X  0  X  X  X  X  X  X  X  X  0 
         54       0     0    0    X    X   X  X  X  X  X  X  X  X  0  X  X  X  X  X  X  X  X  0 
         55       0     0    0    X    X   X  X  X  X  X  X  X  X  0  X  X  X  X  X  X  X  X  0 
         56       0     0    0    X    X   X  X  X  X  X  X  X  X  0  X  X  X  X  X  X  X  X  0 
         57       0     0    0    X    X   X  X  X  X  X  X  X  X  0  X  X  X  X  X  X  X  X  0 
         58       0     0    0    X    X   X  X  X  X  X  X  X  X  0  X  X  X  X  X  X  X  X  0 
         59       0     0    0    X    X   X  X  X  X  X  X  X  X  0  X  X  X  X  X  X  X  X  0 
         60       0     0    0    X    X   X  X  X  X  X  X  X  X  0  X  X  X  X  X  X  X  X  0 
         61       0     0    0    X    X   X  X  X  X  X  X  X  X  0  X  X  X  X  X  X  X  X  0 
         62       0     0    0    X    X   X  X  X  X  X  X  X  X  0  X  X  X  X  X  X  X  X  0 
         63       0     0    0    X    X   X  X  X  X  X  X  X  X  0  X  X  X  X  X  X  X  X  0 
N2.C1: CMD-N xovercal offset = 0
N2.C1: CMD-S xovercal offset = 0
N2.C1: CTL xovercal offset   = 0
N2.C1: CKE xovercal offset   = 3
N2.C1: CLK xovercal offset   = 8
N2.C1.S18: STROBE                     0   1   2   3   4   5   6   7   8   9  10  11  12  13  14  15  16  17
N2.C1.S18: Rec En xovercal offset =  55  57  60  63   1  63  61  60   0  55  57  60  63   1  63  61  60   0 
N2.C1.S18: Tx Dqs xovercal offset =  55  63  63  63  63  63  63  63   0  63  63  63  63  63  63  63  63   0 
N2.C1.S18: Tx Dq xovercal offset  =  55  57  60  63   1  63  61  60   0  55  57  60  63   1  63  61  60   0 
N2.C1:         CMDn  CMDs  CTL  CKE  CLK   0  1  2  3  4  5  6  7  8
N2.C1: offsets:  0     0     0N2: getComplexCkeSetupTime defaultOffset = 98
N2: getComplexCkeSetupTime = 98
    3    8
Ctl Offsets Delta / final ctl offset / final cke offset /  98  /   2  /  37
Cke invertpiclk / Ctl invertpiclk / 0x0  /  0x0
N2: getComplexClkSetupTime defaultOffset = 0
N2: getComplexClkSetupTime = 0
ClkSetupTime = 40
N2: getComplexDqSetupTime defaultOffset = 0
N2: getComplexDqSetupTime = 0
N2.C1.S00: txdqoffset delta = 0, dq invertpiclk = 0
N2: getComplexDqsSetupTime defaultOffset = 40
N2: getComplexDqsSetupTime = 40
N2.C1.S00: txdqsoffset delta = 40
N2: getComplexRcvEnSetupTime defaultOffset = 37
N2: getComplexRcvEnSetupTime = 37
N2.C1.S00: rcvenoffset delta = 37
N2.C1.S00: Final txdqoffset / txdqsoffset / rcvenoffset / 55 / 31 / 28
N2: getComplexDqSetupTime defaultOffset = 0
N2: getComplexDqSetupTime = 0
N2.C1.S01: txdqoffset delta = 0, dq invertpiclk = 0
N2: getComplexDqsSetupTime defaultOffset = 40
N2: getComplexDqsSetupTime = 40
N2.C1.S01: txdqsoffset delta = 40
N2: getComplexRcvEnSetupTime defaultOffset = 37
N2: getComplexRcvEnSetupTime = 37
N2.C1.S01: rcvenoffset delta = 37
N2.C1.S01: Final txdqoffset / txdqsoffset / rcvenoffset / 25 /  1 / 62
N2: getComplexDqSetupTime defaultOffset = 0
N2: getComplexDqSetupTime = 0
N2.C1.S02: txdqoffset delta = 0, dq invertpiclk = 0
N2: getComplexDqsSetupTime defaultOffset = 40
N2: getComplexDqsSetupTime = 40
N2.C1.S02: txdqsoffset delta = 40
N2: getComplexRcvEnSetupTime defaultOffset = 37
N2: getComplexRcvEnSetupTime = 37
N2.C1.S02: rcvenoffset delta = 37
N2.C1.S02: Final txdqoffset / txdqsoffset / rcvenoffset / 60 / 36 / 33
N2: getComplexDqSetupTime defaultOffset = 0
N2: getComplexDqSetupTime = 0
N2.C1.S03: txdqoffset delta = 0, dq invertpiclk = 0
N2: getComplexDqsSetupTime defaultOffset = 40
N2: getComplexDqsSetupTime = 40
N2.C1.S03: txdqsoffset delta = 40
N2: getComplexRcvEnSetupTime defaultOffset = 37
N2: getComplexRcvEnSetupTime = 37
N2.C1.S03: rcvenoffset delta = 37
N2.C1.S03: Final txdqoffset / txdqsoffset / rcvenoffset / 31 /  7 /  4
N2: getComplexDqSetupTime defaultOffset = 0
N2: getComplexDqSetupTime = 0
N2.C1.S04: txdqoffset delta = 0, dq invertpiclk = 3
N2: getComplexDqsSetupTime defaultOffset = 40
N2: getComplexDqsSetupTime = 40
N2.C1.S04: txdqsoffset delta = 40
N2: getComplexRcvEnSetupTime defaultOffset = 37
N2: getComplexRcvEnSetupTime = 37
N2.C1.S04: rcvenoffset delta = 37
N2.C1.S04: Final txdqoffset / txdqsoffset / rcvenoffset /  1 / 41 / 38
N2: getComplexDqSetupTime defaultOffset = 0
N2: getComplexDqSetupTime = 0
N2.C1.S05: txdqoffset delta = 0, dq invertpiclk = 0
N2: getComplexDqsSetupTime defaultOffset = 40
N2: getComplexDqsSetupTime = 40
N2.C1.S05: txdqsoffset delta = 40
N2: getComplexRcvEnSetupTime defaultOffset = 37
N2: getComplexRcvEnSetupTime = 37
N2.C1.S05: rcvenoffset delta = 37
N2.C1.S05: Final txdqoffset / txdqsoffset / rcvenoffset / 31 /  7 /  4
N2: getComplexDqSetupTime defaultOffset = 0
N2: getComplexDqSetupTime = 0
N2.C1.S06: txdqoffset delta = 0, dq invertpiclk = 0
N2: getComplexDqsSetupTime defaultOffset = 40
N2: getComplexDqsSetupTime = 40
N2.C1.S06: txdqsoffset delta = 40
N2: getComplexRcvEnSetupTime defaultOffset = 37
N2: getComplexRcvEnSetupTime = 37
N2.C1.S06: rcvenoffset delta = 37
N2.C1.S06: Final txdqoffset / txdqsoffset / rcvenoffset / 61 / 37 / 34
N2: getComplexDqSetupTime defaultOffset = 0
N2: getComplexDqSetupTime = 0
N2.C1.S07: txdqoffset delta = 0, dq invertpiclk = 0
N2: getComplexDqsSetupTime defaultOffset = 40
N2: getComplexDqsSetupTime = 40
N2.C1.S07: txdqsoffset delta = 40
N2: getComplexRcvEnSetupTime defaultOffset = 37
N2: getComplexRcvEnSetupTime = 37
N2.C1.S07: rcvenoffset delta = 37
N2.C1.S07: Final txdqoffset / txdqsoffset / rcvenoffset / 28 /  4 /  1
N2: getComplexDqSetupTime defaultOffset = 0
N2: getComplexDqSetupTime = 0
N2.C1.S08: txdqoffset delta = 0, dq invertpiclk = 3
N2: getComplexDqsSetupTime defaultOffset = 40
N2: getComplexDqsSetupTime = 40
N2.C1.S08: txdqsoffset delta = 40
N2: getComplexRcvEnSetupTime defaultOffset = 37
N2: getComplexRcvEnSetupTime = 37
N2.C1.S08: rcvenoffset delta = 37
N2.C1.S08: Final txdqoffset / txdqsoffset / rcvenoffset /  0 / 40 / 37

N4.C0: rxVref = 0x5F
N6.C2: vmse_wr_turnaround = 0x7 
N0.C0: InitHostVmseCfg
N4.C1: rxVref = 0x5F
N6: HsxInitDdrioInterface
N0.C0: vmse_wr_turnaround = 0x7 
N4: HsxVmseCompInit
N6.C0: rxVref = 0x5F
Checkpoint Code: Socket 0, 0xB6, 0x01, 0x0000
N2: SetupJckSmbCfg: JCK VLINFREQ set to: 0x820F1028
N4: VmseCrossoverCalib
N4: Enable xovercal
N4: vmse_modes =          1,  0
N4.C0: piDelay CMDn  CMDs  CTL  CKE  CLK   0  1  2  3  4  5  6  7  8  9 10 11 12 13 14 15 16 17
          0       0     0    0    0    0   1  1  1  1  0  1  1  1  0  1  1  1  1  0  1  1  1  0 
          1       0     0    1    0    0   1  1  1  1  1  1  1  1  0  1  1  1  1  1  1  1  1  0 
          2       0     0    1    0    0   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
          3       0     0    1    0    0   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
          4       0     0    1    1    0   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
          5       0     0    1    1    0   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
          6       0     0    1    1    0   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
          7       0     0    1    1    0   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
          8       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
          9       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         10       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         11       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         12       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         13       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         14       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         15       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         16       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         17       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         18       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         19       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         20       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         21       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         22       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         23       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         24       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         25       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         26       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         27       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         28       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         29       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         30       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         31       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         32       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         33       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         34       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         35       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         36       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         37       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         38       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         39       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         40       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         41       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         42       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         43       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         44       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         45       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         46       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         47       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         48       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         49       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         50       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         51       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         52       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         53       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         54       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         55       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         56       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         57       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         58       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         59       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         60       0     0    1    1    1   0  0  1  1  1  1  1  1  1  0  0  1  1  1  1  1  1  1 
         61       0     0    1    1    1   X  X  1  1  1  1  1  1  1  X  X  1  1  1  1  1  1  1 
         62       0     0    1    1    1   X  X  1  1  1  1  1  1  1  X  X  1  1  1  1  1  1  1 
         63       0     0    1    1    1   X  X  0  1  1  1  1  0  1  X  X  0  1  1  1  1  0  1 
N4.C0: setting ddrcrinvertpiclk
          0       0     0    1    1    1   X  X  X  0  1  1  0  X  1  X  X  X  0  1  1  0  X  1 
          1       0     0    1    1    1   X  X  X  0  1  0  0  X  1  X  X  X  0  1  0  0  X  1 
          2       0     0    1    1    1   X  X  X  0  0  X  0  X  1  X  X  X  0  0  X  0  X  1 
          3       0     0    0    1    1   X  X  X  0  X  X  0  X  0  X  X  X  0  X  X  0  X  0 
          4       0     0    X    1    1   X  X  X  0  X  X  0  X  X  X  X  X  0  X  X  0  X  X 
          5       0     0    X    0    1   X  X  X  0  X  X  0  X  X  X  X  X  0  X  X  0  X  X 
          6       0     0    X    X    1   X  X  X  0  X  X  0  X  X  X  X  X  0  X  X  0  X  X 
          7       0     0    X    X    1   X  X  X  0  X  X  0  X  X  X  X  X  0  X  X  0  X  X 
          8       0     0    X    X    1   X  X  X  0  X  X  0  X  X  X  X  X  0  X  X  0  X  X 
          9       0     0    X    X    0   X  X  X  0  X  X  0  X  X  X  X  X  0  X  X  0  X  X 
         10       0     0    X    X    X   X  X  X  0  X  X  0  X  X  X  X  X  0  X  X  0  X  X 
         11       0     0    X    X    X   X  X  X  0  X  X  0  X  X  X  X  X  0  X  X  0  X  X 
         12       0     0    X    X    X   X  X  X  0  X  X  0  X  X  X  X  X  0  X  X  0  X  X 
         13       0     0    X    X    X   X  X  X  0  X  X  0  X  X  X  X  X  0  X  X  0  X  X 
         14       0     0    X    X    X   X  X  X  0  X  X  0  X  X  X  X  X  0  X  X  0  X  X 
         15       0     0    X    X    X   X  X  X  0  X  X  0  X  X  X  X  X  0  X  X  0  X  X 
         16       0     0    X    X    X   X  X  X  0  X  X  0  X  X  X  X  X  0  X  X  0  X  X 
         17       0     0    X    X    X   X  X  X  0  X  X  0  X  X  X  X  X  0  X  X  0  X  X 
         18       0     0    X    X    X   X  X  X  0  X  X  0  X  X  X  X  X  0  X  X  0  X  X 
         19       0     0    X    X    X   X  X  X  0  X  X  0  X  X  X  X  X  0  X  X  0  X  X 
         20       0     0    X    X    X   X  X  X  0  X  X  0  X  X  X  X  X  0  X  X  0  X  X 
         21       0     0    X    X    X   X  X  X  0  X  X  0  X  X  X  X  X  0  X  X  0  X  X 
         22       0     0    X    X    X   X  X  X  0  X  X  0  X  X  X  X  X  0  X  X  0  X  X 
         23       0     0    X    X    X   X  X  X  0  X  X  0  X  X  X  X  X  0  X  X  0  X  X 
         24       0     0    X    X    X   X  X  X  0  X  X  0  X  X  X  X  X  0  X  X  0  X  X 
         25       0     0    X    X    X   X  X  X  0  X  X  0  X  X  X  X  X  0  X  X  0  X  X 
         26       0     0    X    X    X   X  X  X  0  X  X  0  X  X  X  X  X  0  X  X  0  X  X 
         27       0     0    X    X    X   X  X  X  0  X  X  0  X  X  X  X  X  0  X  X  0  X  X 
         28       0     0    X    X    X   X  X  X  0  X  X  0  X  X  X  X  X  0  X  X  0  X  X 
         29       0     0    X    X    X   X  X  X  0  X  X  0  X  X  X  X  X  0  X  X  0  X  X 
         30       0     0    X    X    X   X  X  X  0  X  X  0  X  X  X  X  X  0  X  X  0  X  X 
         31       0     0    X    X    X   X  X  X  0  X  X  0  X  X  X  X  X  0  X  X  0  X  X 
         32       0     0    X    X    X   X  X  X  0  X  X  0  X  X  X  X  X  0  X  X  0  X  X 
         33       0     0    X    X    X   X  X  X  0  X  X  0  X  X  X  X  X  0  X  X  0  X  X 
         34       0     0    X    X    X   X  X  X  0  X  X  0  X  X  X  X  X  0  X  X  0  X  X 
         35       0     0    X    X    X   X  X  X  0  X  X  0  X  X  X  X  X  0  X  X  0  X  X 
         36       0     0    X    X    X   X  X  X  0  X  X  0  X  X  X  X  X  0  X  X  0  X  X 
         37       0     0    X    X    X   X  X  X  0  X  X  0  X  X  X  X  X  0  X  X  0  X  X 
         38       0     0    X    X    X   X  X  X  0  X  X  0  X  X  X  X  X  0  X  X  0  X  X 
         39       0     0    X    X    X   X  X  X  0  X  X  0  X  X  X  X  X  0  X  X  0  X  X 
         40       0     0    X    X    X   X  X  X  0  X  X  0  X  X  X  X  X  0  X  X  0  X  X 
         41       0     0    X    X    X   X  X  X  0  X  X  0  X  X  X  X  X  0  X  X  0  X  X 
         42       0     0    X    X    X   X  X  X  0  X  X  0  X  X  X  X  X  0  X  X  0  X  X 
         43       0     0    X    X    X   X  X  X  0  X  X  0  X  X  X  X  X  0  X  X  0  X  X 
         44       0     0    X    X    X   X  X  X  0  X  X  0  X  X  X  X  X  0  X  X  0  X  X 
         45       0     0    X    X    X   X  X  X  0  X  X  0  X  X  X  X  X  0  X  X  0  X  X 
         46       0     0    X    X    X   X  X  X  0  X  X  0  X  X  X  X  X  0  X  X  0  X  X 
         47       0     0    X    X    X   X  X  X  0  X  X  0  X  X  X  X  X  0  X  X  0  X  X 
         48       0     0    X    X    X   X  X  X  0  X  X  0  X  X  X  X  X  0  X  X  0  X  X 
         49       0     0    X    X    X   X  X  X  0  X  X  0  X  X  X  X  X  0  X  X  0  X  X 
         50       0     0    X    X    X   X  X  X  0  X  X  0  X  X  X  X  X  0  X  X  0  X  X 
         51       0     0    X    X    X   X  X  X  0  X  X  0  X  X  X  X  X  0  X  X  0  X  X 
         52       0     0    X    X    X   X  X  X  0  X  X  0  X  X  X  X  X  0  X  X  0  X  X 
         53       0     0    X    X    X   X  X  X  0  X  X  0  X  X  X  X  X  0  X  X  0  X  X 
         54       0     0    X    X    X   X  X  X  0  X  X  0  X  X  X  X  X  0  X  X  0  X  X 
         55       0     0    X    X    X   X  X  X  0  X  X  0  X  X  X  X  X  0  X  X  0  X  X 
         56       0     0    X    X    X   X  X  X  0  X  X  0  X  X  X  X  X  0  X  X  0  X  X 
         57       0     0    X    X    X   X  X  X  0  X  X  0  X  X  X  X  X  0  X  X  0  X  X 
         58       0     0    X    X    X   X  X  X  0  X  X  0  X  X  X  X  X  0  X  X  0  X  X 
         59       0     0    X    X    X   X  X  X  0  X  X  0  X  X  X  X  X  0  X  X  0  X  X 
         60       0     0    X    X    X   X  X  X  0  X  X  0  X  X  X  X  X  0  X  X  0  X  X 
         61       0     0    X    X    X   X  X  X  0  X  X  0  X  X  X  X  X  0  X  X  0  X  X 
         62       0     0    X    X    X   X  X  X  0  X  X  0  X  X  X  X  X  0  X  X  0  X  X 
         63       0     0    X    X    X   X  X  X  0  X  X  1  X  X  X  X  X  0  X  X  1  X  X 
N4.C0: CMD-N xovercal offset = 0
N4.C0: CMD-S xovercal offset = 0
N4.C0: CTL xovercal offset   = 3
N4.C0: CKE xovercal offset   = 5
N4.C0: CLK xovercal offset   = 9
N4.C0.S18: STROBE                     0   1   2   3   4   5   6   7   8   9  10  11  12  13  14  15  16  17
N4.C0.S18: Rec En xovercal offset =  60  60  63   0   2   1   0  63   3  60  60  63   0   2   1   0  63   3 
N4.C0.S18: Tx Dqs xovercal offset =  60  63  63   0  63  63   0  63  63  63  63  63   0  63  63   0  63  63 
N4.C0.S18: Tx Dq xovercal offset  =  60  60  63   0   2   1   0  63   3  60  60  63   0   2   1   0  63   3 
N4.C0:         CMDn  CMDs  CTL  CKE  CLK   0  1  2  3  4  5  6  7  8
N4.C0: offsets:  0     0     3N4: getComplexCkeSetupTime defaultOffset = 98
N4: getComplexCkeSetupTime = 98
    5    9
Ctl Offsets Delta / final ctl offset / final cke offset /  98  /  37  /   7
Cke invertpiclk / Ctl invertpiclk / 0x0  /  0x0
N4: getComplexClkSetupTime defaultOffset = 0
N4: getComplexClkSetupTime = 0
ClkSetupTime = 9
N4: getComplexDqSetupTime defaultOffset = 0
N4: getComplexDqSetupTime = 0
N4.C0.S00: txdqoffset delta = 0, dq invertpiclk = 0
N4: getComplexDqsSetupTime defaultOffset = 40
N4: getComplexDqsSetupTime = 40
N4.C0.S00: txdqsoffset delta = 40
N4: getComplexRcvEnSetupTime defaultOffset = 37
N4: getComplexRcvEnSetupTime = 37
N4.C0.S00: rcvenoffset delta = 37
N4.C0.S00: Final txdqoffset / txdqsoffset / rcvenoffset / 28 /  4 /  1
N4: getComplexDqSetupTime defaultOffset = 0
N4: getComplexDqSetupTime = 0
N4.C0.S01: txdqoffset delta = 0, dq invertpiclk = 0
N4: getComplexDqsSetupTime defaultOffset = 40
N4: getComplexDqsSetupTime = 40
N4.C0.S01: txdqsoffset delta = 40
N4: getComplexRcvEnSetupTime defaultOffset = 37
N4: getComplexRcvEnSetupTime = 37
N4.C0.S01: rcvenoffset delta = 37
N4.C0.S01: Final txdqoffset / txdqsoffset / rcvenoffset / 60 / 36 / 33
N4: getComplexDqSetupTime defaultOffset = 0
N4: getComplexDqSetupTime = 0
N4.C0.S02: txdqoffset delta = 0, dq invertpiclk = 0
N4: getComplexDqsSetupTime defaultOffset = 40
N4: getComplexDqsSetupTime = 40
N4.C0.S02: txdqsoffset delta = 40
N4: getComplexRcvEnSetupTime defaultOffset = 37
N4: getComplexRcvEnSetupTime = 37
N4.C0.S02: rcvenoffset delta = 37
N4.C0.S02: Final txdqoffset / txdqsoffset / rcvenoffset / 31 /  7 /  4
N4: getComplexDqSetupTime defaultOffset = 0
N4: getComplexDqSetupTime = 0
N4.C0.S03: txdqoffset delta = 0, dq invertpiclk = 3
N4: getComplexDqsSetupTime defaultOffset = 40
N4: getComplexDqsSetupTime = 40
N4.C0.S03: txdqsoffset delta = 40
N4: getComplexRcvEnSetupTime defaultOffset = 37
N4: getComplexRcvEnSetupTime = 37
N4.C0.S03: rcvenoffset delta = 37
N4.C0.S03: Final txdqoffset / txdqsoffset / rcvenoffset /  0 / 40 / 37
N4: getComplexDqSetupTime defaultOffset = 0
N4: getComplexDqSetupTime = 0
N4.C0.S04: txdqoffset delta = 0, dq invertpiclk = 3
N4: getComplexDqsSetupTime defaultOffset = 40
N4: getComplexDqsSetupTime = 40
N4.C0.S04: txdqsoffset delta = 40
N4: getComplexRcvEnSetupTime defaultOffset = 37
N4: getComplexRcvEnSetupTime = 37
N4.C0.S04: rcvenoffset delta = 37
N4.C0.S04: Final txdqoffset / txdqsoffset / rcvenoffset / 34 / 10 /  7
N4: getComplexDqSetupTime defaultOffset = 0
N4: getComplexDqSetupTime = 0
N4.C0.S05: txdqoffset delta = 0, dq invertpiclk = 3
N4: getComplexDqsSetupTime defaultOffset = 40
N4: getComplexDqsSetupTime = 40
N4.C0.S05: txdqsoffset delta = 40
N4: getComplexRcvEnSetupTime defaultOffset = 37
N4: getComplexRcvEnSetupTime = 37
N4.C0.S05: rcvenoffset delta = 37
N4.C0.S05: Final txdqoffset / txdqsoffset / rcvenoffset /  1 / 41 / 38
N4: getComplexDqSetupTime defaultOffset = 0
N4: getComplexDqSetupTime = 0
N4.C0.S06: txdqoffset delta = 0, dq invertpiclk = 3
N4: getComplexDqsSetupTime defaultOffset = 40
N4: getComplexDqsSetupTime = 40
N4.C0.S06: txdqsoffset delta = 40
N4: getComplexRcvEnSetupTime defaultOffset = 37
N4: getComplexRcvEnSetupTime = 37
N4.C0.S06: rcvenoffset delta = 37
N4.C0.S06: Final txdqoffset / txdqsoffset / rcvenoffset / 32 /  8 /  5
N4: getComplexDqSetupTime defaultOffset = 0
N4: getComplexDqSetupTime = 0
N4.C0.S07: txdqoffset delta = 0, dq invertpiclk = 0
N4: getComplexDqsSetupTime defaultOffset = 40
N4: getComplexDqsSetupTime = 40
N4.C0.S07: txdqsoffset delta = 40
N4: getComplexRcvEnSetupTime defaultOffset = 37
N4: getComplexRcvEnSetupTime = 37
N4.C0.S07: rcvenoffset delta = 37
N4.C0.S07: Final txdqoffset / txdqsoffset / rcvenoffset / 63 / 39 / 36
N4: getComplexDqSetupTime defaultOffset = 0
N4: getComplexDqSetupTime = 0
N4.C0.S08: txdqoffset delta = 0, dq invertpiclk = 3
N4: getComplexDqsSetupTime defaultOffset = 40
N4: getComplexDqsSetupTime = 40
N4.C0.S08: txdqsoffset delta = 40
N4: getComplexRcvEnSetupTime defaultOffset = 37
N4: getComplexRcvEnSetupTime = 37
N4.C0.S08: rcvenoffset delta = 37
N4.C0.S08: Final txdqoffset / txdqsoffset / rcvenoffset / 35 / 11 /  8

N4: vmse_modes =          1,  0
N4.C1: piDelay CMDn  CMDs  CTL  CKE  CLK   0  1  2  3  4  5  6  7  8  9 10 11 12 13 14 15 16 17
          0       0     0    1    1    0   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
          1       0     0    1    1    0   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
          2       0     0    1    1    0   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
          3       0     0    1    1    0   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
          4       0     0    1    1    0   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
          5       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
          6       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
          7       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
          8       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
          9       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         10       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         11       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         12       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         13       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         14       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         15       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         16       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         17       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         18       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         19       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         20       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         21       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         22       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         23       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         24       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         25       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         26       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         27       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         28       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         29       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         30       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         31       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         32       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         33       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         34       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         35       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         36       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         37       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         38       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         39       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         40       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         41       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         42       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         43       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         44       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         45       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         46       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         47       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         48       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         49       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         50       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         51       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         52       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         53       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         54       0     0    1    1    1   0  1  1  1  1  1  1  1  1  0  1  1  1  1  1  1  1  1 
         55       0     0    1    1    1   X  1  1  1  1  1  1  1  1  X  1  1  1  1  1  1  1  1 
         56       0     0    1    1    1   X  0  1  1  1  1  1  1  1  X  0  1  1  1  1  1  1  1 
         57       0     0    1    1    1   X  X  1  1  1  1  1  1  1  X  X  1  1  1  1  1  1  1 
         58       0     0    1    1    1   X  X  1  1  1  1  1  1  1  X  X  1  1  1  1  1  1  1 
         59       0     0    1    1    1   X  X  0  1  1  1  1  0  1  X  X  0  1  1  1  1  0  1 
         60       0     0    1    1    1   X  X  X  1  1  1  0  X  1  X  X  X  1  1  1  0  X  1 
         61       0     0    1    1    1   X  X  X  0  1  0  X  X  1  X  X  X  0  1  0  X  X  1 
         62       0     0    1    1    1   X  X  X  X  1  X  X  X  1  X  X  X  X  1  X  X  X  1 
         63       0     0    1    1    1   X  X  X  X  1  X  X  X  1  X  X  X  X  1  X  X  X  1 
N4.C1: setting ddrcrinvertpiclk
          0       0     0    0    1    1   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
          1       0     0    0    1    1   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
          2       0     0    0    0    1   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
          3       0     0    0    X    1   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
          4       0     0    0    X    1   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
          5       0     0    0    X    1   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
          6       0     0    0    X    0   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
          7       0     0    0    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
          8       0     0    0    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
          9       0     0    0    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         10       0     0    0    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         11       0     0    0    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         12       0     0    0    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         13       0     0    0    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         14       0     0    0    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         15       0     0    0    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         16       0     0    0    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         17       0     0    0    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         18       0     0    0    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         19       0     0    0    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         20       0     0    0    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         21       0     0    0    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         22       0     0    0    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         23       0     0    0    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         24       0     0    0    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         25       0     0    0    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         26       0     0    0    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         27       0     0    0    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         28       0     0    0    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         29       0     0    0    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         30       0     0    0    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         31       0     0    0    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         32       0     0    0    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         33       0     0    0    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         34       0     0    0    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         35       0     0    0    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         36       0     0    0    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         37       0     0    0    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         38       0     0    0    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         39       0     0    0    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         40       0     0    0    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         41       0     0    0    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         42       0     0    0    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         43       0     0    0    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         44       0     0    0    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         45       0     0    0    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         46       0     0    0    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         47       0     0    0    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         48       0     0    0    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         49       0     0    0    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         50       0     0    0    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         51       0     0    0    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         52       0     0    0    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         53       0     0    0    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         54       0     0    0    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         55       0     0    0    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         56       0     0    0    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         57       0     0    0    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         58       0     0    0    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         59       0     0    0    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         60       0     0    0    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         61       0     0    0    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         62       0     0    0    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         63       0     0    1    X    X   X  X  X  X  1  X  X  X  1  X  X  X  X  1  X  X  X  1 
N4.C1: CMD-N xovercal offset = 0
N4.C1: CMD-S xovercal offset = 0
N4.C1: CTL xovercal offset   = 0
N4.C1: CKE xovercal offset   = 2
N4.C1: CLK xovercal offset   = 6
N4.C1.S18: STROBE                     0   1   2   3   4   5   6   7   8   9  10  11  12  13  14  15  16  17
N4.C1.S18: Rec En xovercal offset =  54  56  59  61   0  61  60  59   0  54  56  59  61   0  61  60  59   0 
N4.C1.S18: Tx Dqs xovercal offset =  54  63  63  63   0  63  63  63   0  63  63  63  63   0  63  63  63   0 
N4.C1.S18: Tx Dq xovercal offset  =  54  56  59  61   0  61  60  59   0  54  56  59  61   0  61  60  59   0 
N4.C1:         CMDn  CMDs  CTL  CKE  CLK   0  1  2  3  4  5  6  7  8
N4.C1: offsets:  0     0     0N4: getComplexCkeSetupTime defaultOffset = 98
N4: getComplexCkeSetupTime = 98
    2    6
Ctl Offsets Delta / final ctl offset / final cke offset /  98  /   2  /  36
Cke invertpiclk / Ctl invertpiclk / 0x0  /  0x0
N4: getComplexClkSetupTime defaultOffset = 0
N4: getComplexClkSetupTime = 0
ClkSetupTime = 38
N4: getComplexDqSetupTime defaultOffset = 0
N4: getComplexDqSetupTime = 0
N4.C1.S00: txdqoffset delta = 0, dq invertpiclk = 0
N4: getComplexDqsSetupTime defaultOffset = 40
N4: getComplexDqsSetupTime = 40
N4.C1.S00: txdqsoffset delta = 40
N4: getComplexRcvEnSetupTime defaultOffset = 37
N4: getComplexRcvEnSetupTime = 37
N4.C1.S00: rcvenoffset delta = 37
N4.C1.S00: Final txdqoffset / txdqsoffset / rcvenoffset / 54 / 30 / 27
N4: getComplexDqSetupTime defaultOffset = 0
N4: getComplexDqSetupTime = 0
N4.C1.S01: txdqoffset delta = 0, dq invertpiclk = 0
N4: getComplexDqsSetupTime defaultOffset = 40
N4: getComplexDqsSetupTime = 40
N4.C1.S01: txdqsoffset delta = 40
N4: getComplexRcvEnSetupTime defaultOffset = 37
N4: getComplexRcvEnSetupTime = 37
N4.C1.S01: rcvenoffset delta = 37
N4.C1.S01: Final txdqoffset / txdqsoffset / rcvenoffset / 24 /  0 / 61
N4: getComplexDqSetupTime defaultOffset = 0
N4: getComplexDqSetupTime = 0
N4.C1.S02: txdqoffset delta = 0, dq invertpiclk = 0
N4: getComplexDqsSetupTime defaultOffset = 40
N4: getComplexDqsSetupTime = 40
N4.C1.S02: txdqsoffset delta = 40
N4: getComplexRcvEnSetupTime defaultOffset = 37
N4: getComplexRcvEnSetupTime = 37
N4.C1.S02: rcvenoffset delta = 37
N4.C1.S02: Final txdqoffset / txdqsoffset / rcvenoffset / 59 / 35 / 32
N4: getComplexDqSetupTime defaultOffset = 0
N4: getComplexDqSetupTime = 0
N4.C1.S03: txdqoffset delta = 0, dq invertpiclk = 0
N4: getComplexDqsSetupTime defaultOffset = 40
N4: getComplexDqsSetupTime = 40
N4.C1.S03: txdqsoffset delta = 40
N4: getComplexRcvEnSetupTime defaultOffset = 37
N4: getComplexRcvEnSetupTime = 37
N4.C1.S03: rcvenoffset delta = 37
N4.C1.S03: Final txdqoffset / txdqsoffset / rcvenoffset / 29 /  5 /  2
N4: getComplexDqSetupTime defaultOffset = 0
N4: getComplexDqSetupTime = 0
N4.C1.S04: txdqoffset delta = 0, dq invertpiclk = 3
N4: getComplexDqsSetupTime defaultOffset = 40
N4: getComplexDqsSetupTime = 40
N4.C1.S04: txdqsoffset delta = 40
N4: getComplexRcvEnSetupTime defaultOffset = 37
N4: getComplexRcvEnSetupTime = 37
N4.C1.S04: rcvenoffset delta = 37
N4.C1.S04: Final txdqoffset / txdqsoffset / rcvenoffset /  0 / 40 / 37
N4: getComplexDqSetupTime defaultOffset = 0
N4: getComplexDqSetupTime = 0
N4.C1.S05: txdqoffset delta = 0, dq invertpiclk = 0
N4: getComplexDqsSetupTime defaultOffset = 40
N4: getComplexDqsSetupTime = 40
N4.C1.S05: txdqsoffset delta = 40
N4: getComplexRcvEnSetupTime defaultOffset = 37
N4: getComplexRcvEnSetupTime = 37
N4.C1.S05: rcvenoffset delta = 37
N4.C1.S05: Final txdqoffset / txdqsoffset / rcvenoffset / 29 /  5 /  2
N4: getComplexDqSetupTime defaultOffset = 0
N4: getComplexDqSetupTime = 0
N4.C1.S06: txdqoffset delta = 0, dq invertpiclk = 0
N4: getComplexDqsSetupTime defaultOffset = 40
N4: getComplexDqsSetupTime = 40
N4.C1.S06: txdqsoffset delta = 40
N4: getComplexRcvEnSetupTime defaultOffset = 37
N4: getComplexRcvEnSetupTime = 37
N4.C1.S06: rcvenoffset delta = 37
N4.C1.S06: Final txdqoffset / txdqsoffset / rcvenoffset / 60 / 36 / 33
N4: getComplexDqSetupTime defaultOffset = 0
N4: getComplexDqSetupTime = 0
N4.C1.S07: txdqoffset delta = 0, dq invertpiclk = 0
N4: getComplexDqsSetupTime defaultOffset = 40
N4: getComplexDqsSetupTime = 40
N4.C1.S07: txdqsoffset delta = 40
N4: getComplexRcvEnSetupTime defaultOffset = 37
N4: getComplexRcvEnSetupTime = 37
N4.C1.S07: rcvenoffset delta = 37
N4.C1.S07: Final txdqoffset / txdqsoffset / rcvenoffset / 27 /  3 /  0
N4: getComplexDqSetupTime defaultOffset = 0
N4: getComplexDqSetupTime = 0
N4.C1.S08: txdqoffset delta = 0, dq invertpiclk = 3
N4: getComplexDqsSetupTime defaultOffset = 40
N4: getComplexDqsSetupTime = 40
N4.C1.S08: txdqsoffset delta = 40
N4: getComplexRcvEnSetupTime defaultOffset = 37
N4: getComplexRcvEnSetupTime = 37
N4.C1.S08: rcvenoffset delta = 37
N4.C1.S08: Final txdqoffset / txdqsoffset / rcvenoffset /  0 / 40 / 37

N6.C1: rxVref = 0x5F
N0.C2: InitHostVmseCfg
N2: SetupJckSmbCfg: PLL is locked.
N6: HsxVmseCompInit
N0.C2: vmse_wr_turnaround = 0x7 
N2.C0: SetupJckSmbCfg: dlyFrms = 15
N6: VmseCrossoverCalib
N6: Enable xovercal
N6: vmse_modes =          1,  0
N6.C0: piDelay CMDn  CMDs  CTL  CKE  CLK   0  1  2  3  4  5  6  7  8  9 10 11 12 13 14 15 16 17
          0       0     0    1    0    0   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
          1       0     0    1    0    0   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
          2       0     0    1    1    0   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
          3       0     0    1    1    0   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
          4       0     0    1    1    0   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
          5       0     0    1    1    0   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
          6       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
          7       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
          8       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
          9       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         10       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         11       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         12       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         13       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         14       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         15       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         16       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         17       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         18       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         19       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         20       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         21       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         22       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         23       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         24       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         25       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         26       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         27       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         28       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         29       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         30       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         31       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         32       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         33       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         34       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         35       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         36       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         37       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         38       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         39       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         40       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         41       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         42       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         43       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         44       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         45       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         46       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         47       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         48       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         49       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         50       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         51       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         52       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         53       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         54       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         55       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         56       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         57       0     0    1    1    1   0  1  1  1  1  1  1  1  1  0  1  1  1  1  1  1  1  1 
         58       0     0    1    1    1   X  1  1  1  1  1  1  1  1  X  1  1  1  1  1  1  1  1 
         59       0     0    1    1    1   X  0  1  1  1  1  1  1  1  X  0  1  1  1  1  1  1  1 
         60       0     0    1    1    1   X  X  0  1  1  1  1  1  1  X  X  0  1  1  1  1  1  1 
         61       0     0    1    1    1   X  X  X  1  1  1  0  0  1  X  X  X  1  1  1  0  0  1 
         62       0     0    1    1    1   X  X  X  0  1  1  X  X  1  X  X  X  0  1  1  X  X  1 
         63       0     0    1    1    1   X  X  X  X  1  1  X  X  1  X  X  X  X  1  1  X  X  1 
N6.C0: setting ddrcrinvertpiclk
          0       0     0    1    1    1   X  X  X  X  1  0  X  X  1  X  X  X  X  1  0  X  X  1 
          1       0     0    0    1    1   X  X  X  X  0  0  X  X  0  X  X  X  X  0  0  X  X  0 
          2       0     0    X    1    1   X  X  X  X  X  0  X  X  X  X  X  X  X  X  0  X  X  X 
          3       0     0    X    0    1   X  X  X  X  X  0  X  X  X  X  X  X  X  X  0  X  X  X 
          4       0     0    X    X    1   X  X  X  X  X  0  X  X  X  X  X  X  X  X  0  X  X  X 
          5       0     0    X    X    1   X  X  X  X  X  0  X  X  X  X  X  X  X  X  0  X  X  X 
          6       0     0    X    X    1   X  X  X  X  X  0  X  X  X  X  X  X  X  X  0  X  X  X 
          7       0     0    X    X    1   X  X  X  X  X  0  X  X  X  X  X  X  X  X  0  X  X  X 
          8       0     0    X    X    0   X  X  X  X  X  0  X  X  X  X  X  X  X  X  0  X  X  X 
          9       0     0    X    X    X   X  X  X  X  X  0  X  X  X  X  X  X  X  X  0  X  X  X 
         10       0     0    X    X    X   X  X  X  X  X  0  X  X  X  X  X  X  X  X  0  X  X  X 
         11       0     0    X    X    X   X  X  X  X  X  0  X  X  X  X  X  X  X  X  0  X  X  X 
         12       0     0    X    X    X   X  X  X  X  X  0  X  X  X  X  X  X  X  X  0  X  X  X 
         13       0     0    X    X    X   X  X  X  X  X  0  X  X  X  X  X  X  X  X  0  X  X  X 
         14       0     0    X    X    X   X  X  X  X  X  0  X  X  X  X  X  X  X  X  0  X  X  X 
         15       0     0    X    X    X   X  X  X  X  X  0  X  X  X  X  X  X  X  X  0  X  X  X 
         16       0     0    X    X    X   X  X  X  X  X  0  X  X  X  X  X  X  X  X  0  X  X  X 
         17       0     0    X    X    X   X  X  X  X  X  0  X  X  X  X  X  X  X  X  0  X  X  X 
         18       0     0    X    X    X   X  X  X  X  X  0  X  X  X  X  X  X  X  X  0  X  X  X 
         19       0     0    X    X    X   X  X  X  X  X  0  X  X  X  X  X  X  X  X  0  X  X  X 
         20       0     0    X    X    X   X  X  X  X  X  0  X  X  X  X  X  X  X  X  0  X  X  X 
         21       0     0    X    X    X   X  X  X  X  X  0  X  X  X  X  X  X  X  X  0  X  X  X 
         22       0     0    X    X    X   X  X  X  X  X  0  X  X  X  X  X  X  X  X  0  X  X  X 
         23       0     0    X    X    X   X  X  X  X  X  0  X  X  X  X  X  X  X  X  0  X  X  X 
         24       0     0    X    X    X   X  X  X  X  X  0  X  X  X  X  X  X  X  X  0  X  X  X 
         25       0     0    X    X    X   X  X  X  X  X  0  X  X  X  X  X  X  X  X  0  X  X  X 
         26       0     0    X    X    X   X  X  X  X  X  0  X  X  X  X  X  X  X  X  0  X  X  X 
         27       0     0    X    X    X   X  X  X  X  X  0  X  X  X  X  X  X  X  X  0  X  X  X 
         28       0     0    X    X    X   X  X  X  X  X  0  X  X  X  X  X  X  X  X  0  X  X  X 
         29       0     0    X    X    X   X  X  X  X  X  0  X  X  X  X  X  X  X  X  0  X  X  X 
         30       0     0    X    X    X   X  X  X  X  X  0  X  X  X  X  X  X  X  X  0  X  X  X 
         31       0     0    X    X    X   X  X  X  X  X  0  X  X  X  X  X  X  X  X  0  X  X  X 
         32       0     0    X    X    X   X  X  X  X  X  0  X  X  X  X  X  X  X  X  0  X  X  X 
         33       0     0    X    X    X   X  X  X  X  X  0  X  X  X  X  X  X  X  X  0  X  X  X 
         34       0     0    X    X    X   X  X  X  X  X  0  X  X  X  X  X  X  X  X  0  X  X  X 
         35       0     0    X    X    X   X  X  X  X  X  0  X  X  X  X  X  X  X  X  0  X  X  X 
         36       0     0    X    X    X   X  X  X  X  X  0  X  X  X  X  X  X  X  X  0  X  X  X 
         37       0     0    X    X    X   X  X  X  X  X  0  X  X  X  X  X  X  X  X  0  X  X  X 
         38       0     0    X    X    X   X  X  X  X  X  0  X  X  X  X  X  X  X  X  0  X  X  X 
         39       0     0    X    X    X   X  X  X  X  X  0  X  X  X  X  X  X  X  X  0  X  X  X 
         40       0     0    X    X    X   X  X  X  X  X  0  X  X  X  X  X  X  X  X  0  X  X  X 
         41       0     0    X    X    X   X  X  X  X  X  0  X  X  X  X  X  X  X  X  0  X  X  X 
         42       0     0    X    X    X   X  X  X  X  X  0  X  X  X  X  X  X  X  X  0  X  X  X 
         43       0     0    X    X    X   X  X  X  X  X  0  X  X  X  X  X  X  X  X  0  X  X  X 
         44       0     0    X    X    X   X  X  X  X  X  0  X  X  X  X  X  X  X  X  0  X  X  X 
         45       0     0    X    X    X   X  X  X  X  X  0  X  X  X  X  X  X  X  X  0  X  X  X 
         46       0     0    X    X    X   X  X  X  X  X  0  X  X  X  X  X  X  X  X  0  X  X  X 
         47       0     0    X    X    X   X  X  X  X  X  0  X  X  X  X  X  X  X  X  0  X  X  X 
         48       0     0    X    X    X   X  X  X  X  X  0  X  X  X  X  X  X  X  X  0  X  X  X 
         49       0     0    X    X    X   X  X  X  X  X  0  X  X  X  X  X  X  X  X  0  X  X  X 
         50       0     0    X    X    X   X  X  X  X  X  0  X  X  X  X  X  X  X  X  0  X  X  X 
         51       0     0    X    X    X   X  X  X  X  X  0  X  X  X  X  X  X  X  X  0  X  X  X 
         52       0     0    X    X    X   X  X  X  X  X  0  X  X  X  X  X  X  X  X  0  X  X  X 
         53       0     0    X    X    X   X  X  X  X  X  0  X  X  X  X  X  X  X  X  0  X  X  X 
         54       0     0    X    X    X   X  X  X  X  X  0  X  X  X  X  X  X  X  X  0  X  X  X 
         55       0     0    X    X    X   X  X  X  X  X  0  X  X  X  X  X  X  X  X  0  X  X  X 
         56       0     0    X    X    X   X  X  X  X  X  0  X  X  X  X  X  X  X  X  0  X  X  X 
         57       0     0    X    X    X   X  X  X  X  X  0  X  X  X  X  X  X  X  X  0  X  X  X 
         58       0     0    X    X    X   X  X  X  X  X  0  X  X  X  X  X  X  X  X  0  X  X  X 
         59       0     0    X    X    X   X  X  X  X  X  0  X  X  X  X  X  X  X  X  0  X  X  X 
         60       0     0    X    X    X   X  X  X  X  X  0  X  X  X  X  X  X  X  X  0  X  X  X 
         61       0     0    X    X    X   X  X  X  X  X  0  X  X  X  X  X  X  X  X  0  X  X  X 
         62       0     0    X    X    X   X  X  X  X  X  1  X  X  X  X  X  X  X  X  1  X  X  X 
         63       0     0    X    X    X   X  X  X  X  X  1  X  X  X  X  X  X  X  X  1  X  X  X 
N6.C0: CMD-N xovercal offset = 0
N6.C0: CMD-S xovercal offset = 0
N6.C0: CTL xovercal offset   = 1
N6.C0: CKE xovercal offset   = 3
N6.C0: CLK xovercal offset   = 8
N6.C0.S18: STROBE                     0   1   2   3   4   5   6   7   8   9  10  11  12  13  14  15  16  17
N6.C0.S18: Rec En xovercal offset =  57  59  60  62   1   0  61  61   1  57  59  60  62   1   0  61  61   1 
N6.C0.S18: Tx Dqs xovercal offset =  57  63  63  63  63   0  63  63  63  63  63  63  63  63   0  63  63  63 
N6.C0.S18: Tx Dq xovercal offset  =  57  59  60  62   1   0  61  61   1  57  59  60  62   1   0  61  61   1 
N6.C0:         CMDn  CMDs  CTL  CKE  CLK   0  1  2  3  4  5  6  7  8
N6.C0: offsets:  0     0     1N6: getComplexCkeSetupTime defaultOffset = 98
N6: getComplexCkeSetupTime = 98
    3    8
Ctl Offsets Delta / final ctl offset / final cke offset /  98  /  35  /   5
Cke invertpiclk / Ctl invertpiclk / 0x0  /  0x0
N6: getComplexClkSetupTime defaultOffset = 0
N6: getComplexClkSetupTime = 0
ClkSetupTime = 8
N6: getComplexDqSetupTime defaultOffset = 0
N6: getComplexDqSetupTime = 0
N6.C0.S00: txdqoffset delta = 0, dq invertpiclk = 0
N6: getComplexDqsSetupTime defaultOffset = 40
N6: getComplexDqsSetupTime = 40
N6.C0.S00: txdqsoffset delta = 40
N6: getComplexRcvEnSetupTime defaultOffset = 37
N6: getComplexRcvEnSetupTime = 37
N6.C0.S00: rcvenoffset delta = 37
N6.C0.S00: Final txdqoffset / txdqsoffset / rcvenoffset / 25 /  1 / 62
N6: getComplexDqSetupTime defaultOffset = 0
N6: getComplexDqSetupTime = 0
N6.C0.S01: txdqoffset delta = 0, dq invertpiclk = 0
N6: getComplexDqsSetupTime defaultOffset = 40
N6: getComplexDqsSetupTime = 40
N6.C0.S01: txdqsoffset delta = 40
N6: getComplexRcvEnSetupTime defaultOffset = 37
N6: getComplexRcvEnSetupTime = 37
N6.C0.S01: rcvenoffset delta = 37
N6.C0.S01: Final txdqoffset / txdqsoffset / rcvenoffset / 59 / 35 / 32
N6: getComplexDqSetupTime defaultOffset = 0
N6: getComplexDqSetupTime = 0
N6.C0.S02: txdqoffset delta = 0, dq invertpiclk = 0
N6: getComplexDqsSetupTime defaultOffset = 40
N6: getComplexDqsSetupTime = 40
N6.C0.S02: txdqsoffset delta = 40
N6: getComplexRcvEnSetupTime defaultOffset = 37
N6: getComplexRcvEnSetupTime = 37
N6.C0.S02: rcvenoffset delta = 37
N6.C0.S02: Final txdqoffset / txdqsoffset / rcvenoffset / 28 /  4 /  1
N6: getComplexDqSetupTime defaultOffset = 0
N6: getComplexDqSetupTime = 0
N6.C0.S03: txdqoffset delta = 0, dq invertpiclk = 0
N6: getComplexDqsSetupTime defaultOffset = 40
N6: getComplexDqsSetupTime = 40
N6.C0.S03: txdqsoffset delta = 40
N6: getComplexRcvEnSetupTime defaultOffset = 37
N6: getComplexRcvEnSetupTime = 37
N6.C0.S03: rcvenoffset delta = 37
N6.C0.S03: Final txdqoffset / txdqsoffset / rcvenoffset / 62 / 38 / 35
N6: getComplexDqSetupTime defaultOffset = 0
N6: getComplexDqSetupTime = 0
N6.C0.S04: txdqoffset delta = 0, dq invertpiclk = 3
N6: getComplexDqsSetupTime defaultOffset = 40
N6: getComplexDqsSetupTime = 40
N6.C0.S04: txdqsoffset delta = 40
N6: getComplexRcvEnSetupTime defaultOffset = 37
N6: getComplexRcvEnSetupTime = 37
N6.C0.S04: rcvenoffset delta = 37
N6.C0.S04: Final txdqoffset / txdqsoffset / rcvenoffset / 33 /  9 /  6
N6: getComplexDqSetupTime defaultOffset = 0
N6: getComplexDqSetupTime = 0
N6.C0.S05: txdqoffset delta = 0, dq invertpiclk = 3
N6: getComplexDqsSetupTime defaultOffset = 40
N6: getComplexDqsSetupTime = 40
N6.C0.S05: txdqsoffset delta = 40
N6: getComplexRcvEnSetupTime defaultOffset = 37
N6: getComplexRcvEnSetupTime = 37
N6.C0.S05: rcvenoffset delta = 37
N6.C0.S05: Final txdqoffset / txdqsoffset / rcvenoffset /  0 / 40 / 37
N6: getComplexDqSetupTime defaultOffset = 0
N6: getComplexDqSetupTime = 0
N6.C0.S06: txdqoffset delta = 0, dq invertpiclk = 0
N6: getComplexDqsSetupTime defaultOffset = 40
N6: getComplexDqsSetupTime = 40
N6.C0.S06: txdqsoffset delta = 40
N6: getComplexRcvEnSetupTime defaultOffset = 37
N6: getComplexRcvEnSetupTime = 37
N6.C0.S06: rcvenoffset delta = 37
N6.C0.S06: Final txdqoffset / txdqsoffset / rcvenoffset / 29 /  5 /  2
N6: getComplexDqSetupTime defaultOffset = 0
N6: getComplexDqSetupTime = 0
N6.C0.S07: txdqoffset delta = 0, dq invertpiclk = 0
N6: getComplexDqsSetupTime defaultOffset = 40
N6: getComplexDqsSetupTime = 40
N6.C0.S07: txdqsoffset delta = 40
N6: getComplexRcvEnSetupTime defaultOffset = 37
N6: getComplexRcvEnSetupTime = 37
N6.C0.S07: rcvenoffset delta = 37
N6.C0.S07: Final txdqoffset / txdqsoffset / rcvenoffset / 61 / 37 / 34
N6: getComplexDqSetupTime defaultOffset = 0
N6: getComplexDqSetupTime = 0
N6.C0.S08: txdqoffset delta = 0, dq invertpiclk = 3
N6: getComplexDqsSetupTime defaultOffset = 40
N6: getComplexDqsSetupTime = 40
N6.C0.S08: txdqsoffset delta = 40
N6: getComplexRcvEnSetupTime defaultOffset = 37
N6: getComplexRcvEnSetupTime = 37
N6.C0.S08: rcvenoffset delta = 37
N6.C0.S08: Final txdqoffset / txdqsoffset / rcvenoffset / 33 /  9 /  6

N6: vmse_modes =          1,  0
N6.C1: piDelay CMDn  CMDs  CTL  CKE  CLK   0  1  2  3  4  5  6  7  8  9 10 11 12 13 14 15 16 17
          0       0     0    1    1    0   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
          1       0     0    1    1    0   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
          2       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
          3       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
          4       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
          5       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
          6       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
          7       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
          8       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
          9       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         10       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         11       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         12       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         13       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         14       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         15       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         16       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         17       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         18       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         19       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         20       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         21       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         22       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         23       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         24       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         25       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         26       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         27       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         28       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         29       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         30       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         31       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         32       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         33       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         34       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         35       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         36       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         37       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         38       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         39       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         40       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         41       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         42       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         43       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         44       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         45       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         46       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         47       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         48       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         49       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         50       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         51       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         52       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         53       0     0    1    1    1   0  1  1  1  1  1  1  1  1  0  1  1  1  1  1  1  1  1 
         54       0     0    1    1    1   X  0  1  1  1  1  1  1  1  X  0  1  1  1  1  1  1  1 
         55       0     0    1    1    1   X  X  1  1  1  1  1  1  1  X  X  1  1  1  1  1  1  1 
         56       0     0    1    1    1   X  X  1  1  1  1  1  0  1  X  X  1  1  1  1  1  1  1 
         57       0     0    1    1    1   X  X  0  1  1  1  1  X  1  X  X  0  1  1  1  1  0  1 
         58       0     0    1    1    1   X  X  X  1  1  1  0  X  1  X  X  X  1  1  1  0  X  1 
         59       0     0    1    1    1   X  X  X  1  1  1  X  X  1  X  X  X  1  1  1  X  X  1 
         60       0     0    1    1    1   X  X  X  0  1  0  X  X  1  X  X  X  0  1  0  X  X  1 
         61       0     0    1    1    1   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         62       0     0    0    1    1   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
         63       0     0    X    1    1   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
N6.C1: setting ddrcrinvertpiclk
          0       0     0    X    0    1   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
          1       0     0    X    0    1   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
          2       0     0    X    0    1   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
          3       0     0    X    0    0   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
          4       0     0    X    0    X   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
          5       0     0    X    0    X   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
          6       0     0    X    0    X   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
          7       0     0    X    0    X   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
          8       0     0    X    0    X   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
          9       0     0    X    0    X   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
         10       0     0    X    0    X   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
         11       0     0    X    0    X   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
         12       0     0    X    0    X   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
         13       0     0    X    0    X   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
         14       0     0    X    0    X   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
         15       0     0    X    0    X   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
         16       0     0    X    0    X   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
         17       0     0    X    0    X   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
         18       0     0    X    0    X   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
         19       0     0    X    0    X   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
         20       0     0    X    0    X   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
         21       0     0    X    0    X   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
         22       0     0    X    0    X   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
         23       0     0    X    0    X   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
         24       0     0    X    0    X   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
         25       0     0    X    0    X   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
         26       0     0    X    0    X   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
         27       0     0    X    0    X   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
         28       0     0    X    0    X   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
         29       0     0    X    0    X   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
         30       0     0    X    0    X   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
         31       0     0    X    0    X   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
         32       0     0    X    0    X   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
         33       0     0    X    0    X   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
         34       0     0    X    0    X   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
         35       0     0    X    0    X   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
         36       0     0    X    0    X   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
         37       0     0    X    0    X   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
         38       0     0    X    0    X   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
         39       0     0    X    0    X   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
         40       0     0    X    0    X   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
         41       0     0    X    0    X   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
         42       0     0    X    0    X   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
         43       0     0    X    0    X   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
         44       0     0    X    0    X   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
         45       0     0    X    0    X   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
         46       0     0    X    0    X   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
         47       0     0    X    0    X   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
         48       0     0    X    0    X   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
         49       0     0    X    0    X   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
         50       0     0    X    0    X   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
         51       0     0    X    0    X   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
         52       0     0    X    0    X   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
         53       0     0    X    0    X   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
         54       0     0    X    0    X   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
         55       0     0    X    0    X   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
         56       0     0    X    0    X   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
         57       0     0    X    0    X   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
         58       0     0    X    0    X   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
         59       0     0    X    0    X   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
         60       0     0    X    0    X   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
         61       0     0    X    0    X   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
         62       0     0    X    0    X   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
         63       0     0    X    1    X   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
N6.C1: CMD-N xovercal offset = 0
N6.C1: CMD-S xovercal offset = 0
N6.C1: CTL xovercal offset   = 62
N6.C1: CKE xovercal offset   = 0
N6.C1: CLK xovercal offset   = 3
N6.C1.S18: STROBE                     0   1   2   3   4   5   6   7   8   9  10  11  12  13  14  15  16  17
N6.C1.S18: Rec En xovercal offset =  53  54  57  60  61  60  58  56  61  53  54  57  60  61  60  58  57  61 
N6.C1.S18: Tx Dqs xovercal offset =  53  63  63  63  63  63  63  63  63  63  63  63  63  63  63  63  63  63 
N6.C1.S18: Tx Dq xovercal offset  =  53  54  57  60  61  60  58  56  61  53  54  57  60  61  60  58  57  61 
N6.C1:         CMDn  CMDs  CTL  CKE  CLK   0  1  2  3  4  5  6  7  8
N6.C1: offsets:  0     0    62N6: getComplexCkeSetupTime defaultOffset = 98
N6: getComplexCkeSetupTime = 98
    0    3
Ctl Offsets Delta / final ctl offset / final cke offset /  98  /   0  /  34
Cke invertpiclk / Ctl invertpiclk / 0x0  /  0x0
N6: getComplexClkSetupTime defaultOffset = 0
N6: getComplexClkSetupTime = 0
ClkSetupTime = 35
N6: getComplexDqSetupTime defaultOffset = 0
N6: getComplexDqSetupTime = 0
N6.C1.S00: txdqoffset delta = 0, dq invertpiclk = 0
N6: getComplexDqsSetupTime defaultOffset = 40
N6: getComplexDqsSetupTime = 40
N6.C1.S00: txdqsoffset delta = 40
N6: getComplexRcvEnSetupTime defaultOffset = 37
N6: getComplexRcvEnSetupTime = 37
N6.C1.S00: rcvenoffset delta = 37
N6.C1.S00: Final txdqoffset / txdqsoffset / rcvenoffset / 53 / 29 / 26
N6: getComplexDqSetupTime defaultOffset = 0
N6: getComplexDqSetupTime = 0
N6.C1.S01: txdqoffset delta = 0, dq invertpiclk = 0
N6: getComplexDqsSetupTime defaultOffset = 40
N6: getComplexDqsSetupTime = 40
N6.C1.S01: txdqsoffset delta = 40
N6: getComplexRcvEnSetupTime defaultOffset = 37
N6: getComplexRcvEnSetupTime = 37
N6.C1.S01: rcvenoffset delta = 37
N6.C1.S01: Final txdqoffset / txdqsoffset / rcvenoffset / 22 / 62 / 59
N6: getComplexDqSetupTime defaultOffset = 0
N6: getComplexDqSetupTime = 0
N6.C1.S02: txdqoffset delta = 0, dq invertpiclk = 0
N6: getComplexDqsSetupTime defaultOffset = 40
N6: getComplexDqsSetupTime = 40
N6.C1.S02: txdqsoffset delta = 40
N6: getComplexRcvEnSetupTime defaultOffset = 37
N6: getComplexRcvEnSetupTime = 37
N6.C1.S02: rcvenoffset delta = 37
N6.C1.S02: Final txdqoffset / txdqsoffset / rcvenoffset / 57 / 33 / 30
N6: getComplexDqSetupTime defaultOffset = 0
N6: getComplexDqSetupTime = 0
N6.C1.S03: txdqoffset delta = 0, dq invertpiclk = 0
N6: getComplexDqsSetupTime defaultOffset = 40
N6: getComplexDqsSetupTime = 40
N6.C1.S03: txdqsoffset delta = 40
N6: getComplexRcvEnSetupTime defaultOffset = 37
N6: getComplexRcvEnSetupTime = 37
N6.C1.S03: rcvenoffset delta = 37
N6.C1.S03: Final txdqoffset / txdqsoffset / rcvenoffset / 28 /  4 /  1
N6: getComplexDqSetupTime defaultOffset = 0
N6: getComplexDqSetupTime = 0
N6.C1.S04: txdqoffset delta = 0, dq invertpiclk = 0
N6: getComplexDqsSetupTime defaultOffset = 40
N6: getComplexDqsSetupTime = 40
N6.C1.S04: txdqsoffset delta = 40
N6: getComplexRcvEnSetupTime defaultOffset = 37
N6: getComplexRcvEnSetupTime = 37
N6.C1.S04: rcvenoffset delta = 37
N6.C1.S04: Final txdqoffset / txdqsoffset / rcvenoffset / 61 / 37 / 34
N6: getComplexDqSetupTime defaultOffset = 0
N6: getComplexDqSetupTime = 0
N6.C1.S05: txdqoffset delta = 0, dq invertpiclk = 0
N6: getComplexDqsSetupTime defaultOffset = 40
N6: getComplexDqsSetupTime = 40
N6.C1.S05: txdqsoffset delta = 40
N6: getComplexRcvEnSetupTime defaultOffset = 37
N6: getComplexRcvEnSetupTime = 37
N6.C1.S05: rcvenoffset delta = 37
N6.C1.S05: Final txdqoffset / txdqsoffset / rcvenoffset / 28 /  4 /  1
N6: getComplexDqSetupTime defaultOffset = 0
N6: getComplexDqSetupTime = 0
N6.C1.S06: txdqoffset delta = 0, dq invertpiclk = 0
N6: getComplexDqsSetupTime defaultOffset = 40
N6: getComplexDqsSetupTime = 40
N6.C1.S06: txdqsoffset delta = 40
N6: getComplexRcvEnSetupTime defaultOffset = 37
N6: getComplexRcvEnSetupTime = 37
N6.C1.S06: rcvenoffset delta = 37
N6.C1.S06: Final txdqoffset / txdqsoffset / rcvenoffset / 58 / 34 / 31
N6: getComplexDqSetupTime defaultOffset = 0
N6: getComplexDqSetupTime = 0
N6.C1.S07: txdqoffset delta = 0, dq invertpiclk = 0
N6: getComplexDqsSetupTime defaultOffset = 40
N6: getComplexDqsSetupTime = 40
N6.C1.S07: txdqsoffset delta = 40
N6: getComplexRcvEnSetupTime defaultOffset = 37
N6: getComplexRcvEnSetupTime = 37
N6.C1.S07: rcvenoffset delta = 37
N6.C1.S07: Final txdqoffset / txdqsoffset / rcvenoffset / 24 /  0 / 61
N6: getComplexDqSetupTime defaultOffset = 0
N6: getComplexDqSetupTime = 0
N6.C1.S08: txdqoffset delta = 0, dq invertpiclk = 0
N6: getComplexDqsSetupTime defaultOffset = 40
N6: getComplexDqsSetupTime = 40
N6.C1.S08: txdqsoffset delta = 40
N6: getComplexRcvEnSetupTime defaultOffset = 37
N6: getComplexRcvEnSetupTime = 37
N6.C1.S08: rcvenoffset delta = 37
N6.C1.S08: Final txdqoffset / txdqsoffset / rcvenoffset / 61 / 37 / 34

Checkpoint Code: Socket 0, 0xB6, 0x02, 0x0000
N2.C0: cwleffective = 8
N4: SetupJckSmbCfg: JCK VLINFREQ set to: 0x820F1028
N0: HsxInitDdrioInterface
N2.C0: PreVMSE Training raw cleff = 9, raw cwleff = 7
N0.C0: rxVref = 0x5F
N4: SetupJckSmbCfg: PLL is locked.
N6: SetupJckSmbCfg: JCK VLINFREQ set to: 0x820F1028
N0.C1: rxVref = 0x5F
N2.C0: vmseratio = 0, revisionId = 5, vmse_mode = 1, QCRM_ENABLE = 0
N4.C0: SetupJckSmbCfg: dlyFrms = 15
N6: SetupJckSmbCfg: PLL is locked.
N0: HsxVmseCompInit
N2: SetupJckSmbCfg: JCK wpsyncrcven = 5, wpsyncdata = 10
N4.C0: cwleffective = 8
N6.C0: SetupJckSmbCfg: dlyFrms = 15
Checkpoint Code: Socket 0, 0xB6, 0x58, 0x0000
N0: VmseCrossoverCalib
N0: Enable xovercal
N0: vmse_modes =          1,  0
N0.C0: piDelay CMDn  CMDs  CTL  CKE  CLK   0  1  2  3  4  5  6  7  8  9 10 11 12 13 14 15 16 17
          0       0     0    0    0    0   1  1  1  1  0  1  1  1  0  1  1  1  1  0  1  1  1  0 
          1       0     0    0    0    0   1  1  1  1  0  1  1  1  1  1  1  1  1  0  1  1  1  1 
          2       0     0    1    0    0   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
          3       0     0    1    0    0   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
          4       0     0    1    1    0   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
          5       0     0    1    1    0   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
          6       0     0    1    1    0   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
          7       0     0    1    1    0   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
          8       0     0    1    1    0   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
          9       0     0    1    1    0   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         10       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         11       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         12       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         13       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         14       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         15       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         16       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         17       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         18       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         19       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         20       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         21       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         22       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         23       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         24       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         25       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         26       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         27       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         28       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         29       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         30       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         31       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         32       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         33       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         34       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         35       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         36       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         37       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         38       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         39       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         40       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         41       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         42       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         43       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         44       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         45       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         46       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         47       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         48       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         49       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         50       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         51       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         52       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         53       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         54       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         55       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         56       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         57       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         58       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         59       0     0    1    1    1   0  1  1  1  1  1  1  1  1  0  1  1  1  1  1  1  1  1 
         60       0     0    1    1    1   X  0  1  1  1  1  1  1  1  X  0  1  1  1  1  1  1  1 
         61       0     0    1    1    1   X  X  1  1  1  1  1  1  1  X  X  1  1  1  1  1  1  1 
         62       0     0    1    1    1   X  X  1  1  1  1  1  0  1  X  X  1  1  1  1  1  0  1 
         63       0     0    1    1    1   X  X  0  1  1  1  0  X  1  X  X  0  1  1  1  0  X  1 
N0.C0: setting ddrcrinvertpiclk
          0       0     0    1    1    1   X  X  X  1  1  1  X  X  1  X  X  X  1  1  1  X  X  1 
          1       0     0    1    1    1   X  X  X  0  1  1  X  X  1  X  X  X  0  1  1  X  X  1 
          2       0     0    1    1    1   X  X  X  X  1  0  X  X  0  X  X  X  X  1  0  X  X  0 
          3       0     0    1    1    1   X  X  X  X  0  X  X  X  X  X  X  X  X  0  X  X  X  X 
          4       0     0    0    1    1   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
          5       0     0    X    1    1   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
          6       0     0    X    0    1   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
          7       0     0    X    X    1   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
          8       0     0    X    X    1   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
          9       0     0    X    X    1   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
         10       0     0    X    X    1   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
         11       0     0    X    X    0   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
         12       0     0    X    X    X   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
         13       0     0    X    X    X   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
         14       0     0    X    X    X   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
         15       0     0    X    X    X   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
         16       0     0    X    X    X   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
         17       0     0    X    X    X   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
         18       0     0    X    X    X   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
         19       0     0    X    X    X   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
         20       0     0    X    X    X   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
         21       0     0    X    X    X   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
         22       0     0    X    X    X   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
         23       0     0    X    X    X   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
         24       0     0    X    X    X   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
         25       0     0    X    X    X   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
         26       0     0    X    X    X   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
         27       0     0    X    X    X   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
         28       0     0    X    X    X   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
         29       0     0    X    X    X   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
         30       0     0    X    X    X   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
         31       0     0    X    X    X   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
         32       0     0    X    X    X   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
         33       0     0    X    X    X   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
         34       0     0    X    X    X   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
         35       0     0    X    X    X   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
         36       0     0    X    X    X   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
         37       0     0    X    X    X   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
         38       0     0    X    X    X   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
         39       0     0    X    X    X   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
         40       0     0    X    X    X   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
         41       0     0    X    X    X   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
         42       0     0    X    X    X   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
         43       0     0    X    X    X   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
         44       0     0    X    X    X   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
         45       0     0    X    X    X   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
         46       0     0    X    X    X   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
         47       0     0    X    X    X   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
         48       0     0    X    X    X   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
         49       0     0    X    X    X   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
         50       0     0    X    X    X   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
         51       0     0    X    X    X   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
         52       0     0    X    X    X   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
         53       0     0    X    X    X   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
         54       0     0    X    X    X   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
         55       0     0    X    X    X   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
         56       0     0    X    X    X   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
         57       0     0    X    X    X   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
         58       0     0    X    X    X   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
         59       0     0    X    X    X   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
         60       0     0    X    X    X   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
         61       0     0    X    X    X   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
         62       0     0    X    X    X   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
         63       0     0    X    X    X   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
N0.C0: CMD-N xovercal offset = 0
N0.C0: CMD-S xovercal offset = 0
N0.C0: CTL xovercal offset   = 4
N0.C0: CKE xovercal offset   = 6
N0.C0: CLK xovercal offset   = 11
N0.C0.S18: STROBE                     0   1   2   3   4   5   6   7   8   9  10  11  12  13  14  15  16  17
N0.C0.S18: Rec En xovercal offset =  59  60  63   1   3   2  63  62   2  59  60  63   1   3   2  63  62   2 
N0.C0.S18: Tx Dqs xovercal offset =  59  63  63  63  63  63  63  63  63  63  63  63  63  63  63  63  63  63 
N0.C0.S18: Tx Dq xovercal offset  =  59  60  63   1   3   2  63  62   2  59  60  63   1   3   2  63  62   2 
N0.C0:         CMDn  CMDs  CTL  CKE  CLK   0  1  2  3  4  5  6  7  8
N0.C0: offsets:  0     0     4N0: getComplexCkeSetupTime defaultOffset = 98
N0: getComplexCkeSetupTime = 98
    6   11
Ctl Offsets Delta / final ctl offset / final cke offset /  98  /  38  /   8
Cke invertpiclk / Ctl invertpiclk / 0x0  /  0x0
N0: getComplexClkSetupTime defaultOffset = 0
N0: getComplexClkSetupTime = 0
ClkSetupTime = 11
N0: getComplexDqSetupTime defaultOffset = 0
N0: getComplexDqSetupTime = 0
N0.C0.S00: txdqoffset delta = 0, dq invertpiclk = 0
N0: getComplexDqsSetupTime defaultOffset = 40
N0: getComplexDqsSetupTime = 40
N0.C0.S00: txdqsoffset delta = 40
N0: getComplexRcvEnSetupTime defaultOffset = 37
N0: getComplexRcvEnSetupTime = 37
N0.C0.S00: rcvenoffset delta = 37
N0.C0.S00: Final txdqoffset / txdqsoffset / rcvenoffset / 27 /  3 /  0
N0: getComplexDqSetupTime defaultOffset = 0
N0: getComplexDqSetupTime = 0
N0.C0.S01: txdqoffset delta = 0, dq invertpiclk = 0
N0: getComplexDqsSetupTime defaultOffset = 40
N0: getComplexDqsSetupTime = 40
N0.C0.S01: txdqsoffset delta = 40
N0: getComplexRcvEnSetupTime defaultOffset = 37
N0: getComplexRcvEnSetupTime = 37
N0.C0.S01: rcvenoffset delta = 37
N0.C0.S01: Final txdqoffset / txdqsoffset / rcvenoffset / 60 / 36 / 33
N0: getComplexDqSetupTime defaultOffset = 0
N0: getComplexDqSetupTime = 0
N0.C0.S02: txdqoffset delta = 0, dq invertpiclk = 0
N0: getComplexDqsSetupTime defaultOffset = 40
N0: getComplexDqsSetupTime = 40
N0.C0.S02: txdqsoffset delta = 40
N0: getComplexRcvEnSetupTime defaultOffset = 37
N0: getComplexRcvEnSetupTime = 37
N0.C0.S02: rcvenoffset delta = 37
N0.C0.S02: Final txdqoffset / txdqsoffset / rcvenoffset / 31 /  7 /  4
N0: getComplexDqSetupTime defaultOffset = 0
N0: getComplexDqSetupTime = 0
N0.C0.S03: txdqoffset delta = 0, dq invertpiclk = 3
N0: getComplexDqsSetupTime defaultOffset = 40
N0: getComplexDqsSetupTime = 40
N0.C0.S03: txdqsoffset delta = 40
N0: getComplexRcvEnSetupTime defaultOffset = 37
N0: getComplexRcvEnSetupTime = 37
N0.C0.S03: rcvenoffset delta = 37
N0.C0.S03: Final txdqoffset / txdqsoffset / rcvenoffset /  1 / 41 / 38
N0: getComplexDqSetupTime defaultOffset = 0
N0: getComplexDqSetupTime = 0
N0.C0.S04: txdqoffset delta = 0, dq invertpiclk = 3
N0: getComplexDqsSetupTime defaultOffset = 40
N0: getComplexDqsSetupTime = 40
N0.C0.S04: txdqsoffset delta = 40
N0: getComplexRcvEnSetupTime defaultOffset = 37
N0: getComplexRcvEnSetupTime = 37
N0.C0.S04: rcvenoffset delta = 37
N0.C0.S04: Final txdqoffset / txdqsoffset / rcvenoffset / 35 / 11 /  8
N0: getComplexDqSetupTime defaultOffset = 0
N0: getComplexDqSetupTime = 0
N0.C0.S05: txdqoffset delta = 0, dq invertpiclk = 3
N0: getComplexDqsSetupTime defaultOffset = 40
N0: getComplexDqsSetupTime = 40
N0.C0.S05: txdqsoffset delta = 40
N0: getComplexRcvEnSetupTime defaultOffset = 37
N0: getComplexRcvEnSetupTime = 37
N0.C0.S05: rcvenoffset delta = 37
N0.C0.S05: Final txdqoffset / txdqsoffset / rcvenoffset /  2 / 42 / 39
N0: getComplexDqSetupTime defaultOffset = 0
N0: getComplexDqSetupTime = 0
N0.C0.S06: txdqoffset delta = 0, dq invertpiclk = 0
N0: getComplexDqsSetupTime defaultOffset = 40
N0: getComplexDqsSetupTime = 40
N0.C0.S06: txdqsoffset delta = 40
N0: getComplexRcvEnSetupTime defaultOffset = 37
N0: getComplexRcvEnSetupTime = 37
N0.C0.S06: rcvenoffset delta = 37
N0.C0.S06: Final txdqoffset / txdqsoffset / rcvenoffset / 31 /  7 /  4
N0: getComplexDqSetupTime defaultOffset = 0
N0: getComplexDqSetupTime = 0
N0.C0.S07: txdqoffset delta = 0, dq invertpiclk = 0
N0: getComplexDqsSetupTime defaultOffset = 40
N0: getComplexDqsSetupTime = 40
N0.C0.S07: txdqsoffset delta = 40
N0: getComplexRcvEnSetupTime defaultOffset = 37
N0: getComplexRcvEnSetupTime = 37
N0.C0.S07: rcvenoffset delta = 37
N0.C0.S07: Final txdqoffset / txdqsoffset / rcvenoffset / 62 / 38 / 35
N0: getComplexDqSetupTime defaultOffset = 0
N0: getComplexDqSetupTime = 0
N0.C0.S08: txdqoffset delta = 0, dq invertpiclk = 3
N0: getComplexDqsSetupTime defaultOffset = 40
N0: getComplexDqsSetupTime = 40
N0.C0.S08: txdqsoffset delta = 40
N0: getComplexRcvEnSetupTime defaultOffset = 37
N0: getComplexRcvEnSetupTime = 37
N0.C0.S08: rcvenoffset delta = 37
N0.C0.S08: Final txdqoffset / txdqsoffset / rcvenoffset / 34 / 10 /  7

N0: vmse_modes =          1,  0
N0.C1: piDelay CMDn  CMDs  CTL  CKE  CLK   0  1  2  3  4  5  6  7  8  9 10 11 12 13 14 15 16 17
          0       0     0    1    1    0   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
          1       0     0    1    1    0   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
          2       0     0    1    1    0   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
          3       0     0    1    1    0   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
          4       0     0    1    1    0   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
          5       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
          6       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
          7       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
          8       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
          9       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         10       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         11       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         12       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         13       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         14       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         15       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         16       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         17       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         18       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         19       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         20       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         21       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         22       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         23       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         24       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         25       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         26       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         27       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         28       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         29       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         30       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         31       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         32       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         33       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         34       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         35       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         36       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         37       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         38       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         39       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         40       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         41       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         42       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         43       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         44       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         45       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         46       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         47       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         48       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         49       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         50       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         51       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         52       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         53       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         54       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         55       0     0    1    1    1   0  1  1  1  1  1  1  1  1  0  1  1  1  1  1  1  1  1 
         56       0     0    1    1    1   X  1  1  1  1  1  1  1  1  X  1  1  1  1  1  1  1  1 
         57       0     0    1    1    1   X  0  1  1  1  1  1  1  1  X  0  1  1  1  1  1  1  1 
         58       0     0    1    1    1   X  X  1  1  1  1  1  1  1  X  X  1  1  1  1  1  1  1 
         59       0     0    1    1    1   X  X  1  1  1  1  1  0  1  X  X  1  1  1  1  1  0  1 
         60       0     0    1    1    1   X  X  0  1  1  1  1  X  1  X  X  0  1  1  1  1  X  1 
         61       0     0    1    1    1   X  X  X  0  1  1  0  X  1  X  X  X  1  1  1  0  X  1 
         62       0     0    1    1    1   X  X  X  X  1  0  X  X  1  X  X  X  0  1  0  X  X  1 
         63       0     0    1    1    1   X  X  X  X  1  X  X  X  1  X  X  X  X  1  X  X  X  1 
N0.C1: setting ddrcrinvertpiclk
          0       0     0    0    1    1   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
          1       0     0    0    1    1   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
          2       0     0    0    0    1   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
          3       0     0    0    X    1   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
          4       0     0    0    X    1   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
          5       0     0    0    X    1   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
          6       0     0    0    X    0   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
          7       0     0    0    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
          8       0     0    0    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
          9       0     0    0    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         10       0     0    0    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         11       0     0    0    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         12       0     0    0    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         13       0     0    0    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         14       0     0    0    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         15       0     0    0    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         16       0     0    0    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         17       0     0    0    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         18       0     0    0    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         19       0     0    0    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         20       0     0    0    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         21       0     0    0    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         22       0     0    0    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         23       0     0    0    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         24       0     0    0    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         25       0     0    0    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         26       0     0    0    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         27       0     0    0    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         28       0     0    0    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         29       0     0    0    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         30       0     0    0    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         31       0     0    0    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         32       0     0    0    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         33       0     0    0    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         34       0     0    0    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         35       0     0    0    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         36       0     0    0    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         37       0     0    0    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         38       0     0    0    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         39       0     0    0    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         40       0     0    0    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         41       0     0    0    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         42       0     0    0    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         43       0     0    0    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         44       0     0    0    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         45       0     0    0    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         46       0     0    0    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         47       0     0    0    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         48       0     0    0    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         49       0     0    0    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         50       0     0    0    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         51       0     0    0    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         52       0     0    0    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         53       0     0    0    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         54       0     0    0    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         55       0     0    0    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         56       0     0    0    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         57       0     0    0    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         58       0     0    0    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         59       0     0    0    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         60       0     0    0    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         61       0     0    0    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         62       0     0    0    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         63       0     0    0    X    X   X  X  X  X  1  X  X  X  1  X  X  X  X  1  X  X  X  1 
N0.C1: CMD-N xovercal offset = 0
N0.C1: CMD-S xovercal offset = 0
N0.C1: CTL xovercal offset   = 0
N0.C1: CKE xovercal offset   = 2
N0.C1: CLK xovercal offset   = 6
N0.C1.S18: STROBE                     0   1   2   3   4   5   6   7   8   9  10  11  12  13  14  15  16  17
N0.C1.S18: Rec En xovercal offset =  55  57  60  61   0  62  61  59   0  55  57  60  62   0  62  61  59   0 
N0.C1.S18: Tx Dqs xovercal offset =  55  63  63  63   0  63  63  63   0  63  63  63  63   0  63  63  63   0 
N0.C1.S18: Tx Dq xovercal offset  =  55  57  60  61   0  62  61  59   0  55  57  60  62   0  62  61  59   0 
N0.C1:         CMDn  CMDs  CTL  CKE  CLK   0  1  2  3  4  5  6  7  8
N0.C1: offsets:  0     0     0N0: getComplexCkeSetupTime defaultOffset = 98
N0: getComplexCkeSetupTime = 98
    2    6
Ctl Offsets Delta / final ctl offset / final cke offset /  98  /   2  /  36
Cke invertpiclk / Ctl invertpiclk / 0x0  /  0x0
N0: getComplexClkSetupTime defaultOffset = 0
N0: getComplexClkSetupTime = 0
ClkSetupTime = 38
N0: getComplexDqSetupTime defaultOffset = 0
N0: getComplexDqSetupTime = 0
N0.C1.S00: txdqoffset delta = 0, dq invertpiclk = 0
N0: getComplexDqsSetupTime defaultOffset = 40
N0: getComplexDqsSetupTime = 40
N0.C1.S00: txdqsoffset delta = 40
N0: getComplexRcvEnSetupTime defaultOffset = 37
N0: getComplexRcvEnSetupTime = 37
N0.C1.S00: rcvenoffset delta = 37
N0.C1.S00: Final txdqoffset / txdqsoffset / rcvenoffset / 55 / 31 / 28
N0: getComplexDqSetupTime defaultOffset = 0
N0: getComplexDqSetupTime = 0
N0.C1.S01: txdqoffset delta = 0, dq invertpiclk = 0
N0: getComplexDqsSetupTime defaultOffset = 40
N0: getComplexDqsSetupTime = 40
N0.C1.S01: txdqsoffset delta = 40
N0: getComplexRcvEnSetupTime defaultOffset = 37
N0: getComplexRcvEnSetupTime = 37
N0.C1.S01: rcvenoffset delta = 37
N0.C1.S01: Final txdqoffset / txdqsoffset / rcvenoffset / 25 /  1 / 62
N0: getComplexDqSetupTime defaultOffset = 0
N0: getComplexDqSetupTime = 0
N0.C1.S02: txdqoffset delta = 0, dq invertpiclk = 0
N0: getComplexDqsSetupTime defaultOffset = 40
N0: getComplexDqsSetupTime = 40
N0.C1.S02: txdqsoffset delta = 40
N0: getComplexRcvEnSetupTime defaultOffset = 37
N0: getComplexRcvEnSetupTime = 37
N0.C1.S02: rcvenoffset delta = 37
N0.C1.S02: Final txdqoffset / txdqsoffset / rcvenoffset / 60 / 36 / 33
N0: getComplexDqSetupTime defaultOffset = 0
N0: getComplexDqSetupTime = 0
N0.C1.S03: txdqoffset delta = 0, dq invertpiclk = 0
N0: getComplexDqsSetupTime defaultOffset = 40
N0: getComplexDqsSetupTime = 40
N0.C1.S03: txdqsoffset delta = 40
N0: getComplexRcvEnSetupTime defaultOffset = 37
N0: getComplexRcvEnSetupTime = 37
N0.C1.S03: rcvenoffset delta = 37
N0.C1.S03: Final txdqoffset / txdqsoffset / rcvenoffset / 29 /  5 /  2
N0: getComplexDqSetupTime defaultOffset = 0
N0: getComplexDqSetupTime = 0
N0.C1.S04: txdqoffset delta = 0, dq invertpiclk = 3
N0: getComplexDqsSetupTime defaultOffset = 40
N0: getComplexDqsSetupTime = 40
N0.C1.S04: txdqsoffset delta = 40
N0: getComplexRcvEnSetupTime defaultOffset = 37
N0: getComplexRcvEnSetupTime = 37
N0.C1.S04: rcvenoffset delta = 37
N0.C1.S04: Final txdqoffset / txdqsoffset / rcvenoffset /  0 / 40 / 37
N0: getComplexDqSetupTime defaultOffset = 0
N0: getComplexDqSetupTime = 0
N0.C1.S05: txdqoffset delta = 0, dq invertpiclk = 0
N0: getComplexDqsSetupTime defaultOffset = 40
N0: getComplexDqsSetupTime = 40
N0.C1.S05: txdqsoffset delta = 40
N0: getComplexRcvEnSetupTime defaultOffset = 37
N0: getComplexRcvEnSetupTime = 37
N0.C1.S05: rcvenoffset delta = 37
N0.C1.S05: Final txdqoffset / txdqsoffset / rcvenoffset / 30 /  6 /  3
N0: getComplexDqSetupTime defaultOffset = 0
N0: getComplexDqSetupTime = 0
N0.C1.S06: txdqoffset delta = 0, dq invertpiclk = 0
N0: getComplexDqsSetupTime defaultOffset = 40
N0: getComplexDqsSetupTime = 40
N0.C1.S06: txdqsoffset delta = 40
N0: getComplexRcvEnSetupTime defaultOffset = 37
N0: getComplexRcvEnSetupTime = 37
N0.C1.S06: rcvenoffset delta = 37
N0.C1.S06: Final txdqoffset / txdqsoffset / rcvenoffset / 61 / 37 / 34
N0: getComplexDqSetupTime defaultOffset = 0
N0: getComplexDqSetupTime = 0
N0.C1.S07: txdqoffset delta = 0, dq invertpiclk = 0
N0: getComplexDqsSetupTime defaultOffset = 40
N0: getComplexDqsSetupTime = 40
N0.C1.S07: txdqsoffset delta = 40
N0: getComplexRcvEnSetupTime defaultOffset = 37
N0: getComplexRcvEnSetupTime = 37
N0.C1.S07: rcvenoffset delta = 37
N0.C1.S07: Final txdqoffset / txdqsoffset / rcvenoffset / 27 /  3 /  0
N0: getComplexDqSetupTime defaultOffset = 0
N0: getComplexDqSetupTime = 0
N0.C1.S08: txdqoffset delta = 0, dq invertpiclk = 3
N0: getComplexDqsSetupTime defaultOffset = 40
N0: getComplexDqsSetupTime = 40
N0.C1.S08: txdqsoffset delta = 40
N0: getComplexRcvEnSetupTime defaultOffset = 37
N0: getComplexRcvEnSetupTime = 37
N0.C1.S08: rcvenoffset delta = 37
N0.C1.S08: Final txdqoffset / txdqsoffset / rcvenoffset /  0 / 40 / 37

N2.C0: SELF CAL 
N4.C0: PreVMSE Training raw cleff = 9, raw cwleff = 7
N6.C0: cwleffective = 8
N6.C0: PreVMSE Training raw cleff = 9, raw cwleff = 7
N2.C0: JckCompCodeCheck: Phase 1 - Comp Code Results
N4.C0: vmseratio = 0, revisionId = 5, vmse_mode = 1, QCRM_ENABLE = 0
N6.C0: vmseratio = 0, revisionId = 5, vmse_mode = 1, QCRM_ENABLE = 0
N0: SetupJckSmbCfg: JCK VLINFREQ set to: 0x820F1028
N2.C0: Cycle ron_up ron_eq_up ron_dn ron_eq_dn odt scomp_up scom_dn tcomp_l2h tcomp_h2l   bad_training
N4: SetupJckSmbCfg: JCK wpsyncrcven = 5, wpsyncdata = 10
N6: SetupJckSmbCfg: JCK wpsyncrcven = 5, wpsyncdata = 10
N0: SetupJckSmbCfg: PLL is locked.
N0.C0: SetupJckSmbCfg: dlyFrms = 15
N0.C0: cwleffective = 8
N2.C0:  0       42     42       38      31      38     16      16        8       31       0
N0.C0: PreVMSE Training raw cleff = 9, raw cwleff = 7
N0.C0: vmseratio = 0, revisionId = 5, vmse_mode = 1, QCRM_ENABLE = 0
N0: SetupJckSmbCfg: JCK wpsyncrcven = 5, wpsyncdata = 10
N2.C0:  1       42     42       38      31      38     16      16        8       31       0
N2.C0:  2       42     42       38      31      38     16      16        8       31       0
N2.C0:  3       42     42       38      31      38     16      16        8       31       0
N2.C0:  4       42     42       38      31      38     16      16        8       31       0
N2.C0:  5       42     42       38      31      38     16      16        8       31       0
N2.C0:  6       42     42       38      31      38     15      15        8       31       0
N2.C0:  7       42     42       38      31      38     16      16        8       31       0
N2.C0:  8       42     42       38      31      38     16      16        8       31       0
N2.C0:  9       42     42       38      31      38     16      16        8       31       0
N2.C0: JckCompCodeCheck: Phase 2 - Check for bad ron_up vs average: num = 10, ron_up_avg = 42, ron_up_75avg = 31
N2.C0: Cycle ron_up ron_eq_up ron_dn ron_eq_dn odt scomp_up scom_dn tcomp_l2h tcomp_h2l   bad_training
N4.C0: SELF CAL 
N6.C0: SELF CAL 
N2.C0: JckCompCodeCheck: Phase 3 - Comp Code Limits
N2.C0: ron_up_limitdn   ron_dn_limitup   ron_eq_dn_limtdn  odt_limitdn
N4.C0: JckCompCodeCheck: Phase 1 - Comp Code Results
N6.C0: JckCompCodeCheck: Phase 1 - Comp Code Results
N2.C0:     26                45                20             24
N4.C0: Cycle ron_up ron_eq_up ron_dn ron_eq_dn odt scomp_up scom_dn tcomp_l2h tcomp_h2l   bad_training
N6.C0: Cycle ron_up ron_eq_up ron_dn ron_eq_dn odt scomp_up scom_dn tcomp_l2h tcomp_h2l   bad_training
N2.C0: JckCompCodeCheck: Phase 3 - SUCCESS
N2.C0: VmseOverrideJckCompCodes
N0.C0: SELF CAL 
N4.C0:  0       42     42       39      32      39     14      14        8       31       0
N0.C0: JckCompCodeCheck: Phase 1 - Comp Code Results
N6.C0:  0       42     42       38      29      39     17      17        5       31       0
N0.C0: Cycle ron_up ron_eq_up ron_dn ron_eq_dn odt scomp_up scom_dn tcomp_l2h tcomp_h2l   bad_training
N4.C0:  1       42     42       39      32      39     15      15        8       31       0
N6.C0:  1       42     42       38      31      39     16      16        6       31       0
N0.C0:  0       41     41       37      33      38     16      16       31        8       0
N4.C0:  2       42     42       39      32      39     15      15        8       31       0
N6.C0:  2       42     42       38      31      39     16      16        5       31       0
N0.C0:  1       41     41       37      33      38     16      16       31        8       0
N4.C0:  3       42     42       39      32      39     14      14        8       31       0
N6.C0:  3       42     42       38      31      39     17      17        5       31       0
N0.C0:  2       41     41       37      32      38     15      15       31        8       0
N4.C0:  4       42     42       39      32      39     15      15        8       31       0
N6.C0:  4       42     42       38      31      39     17      17        5       31       0
N0.C0:  3       41     41       37      30      38     16      16       31        8       0
N4.C0:  5       42     42       39      32      39     14      14        8       31       0
N6.C0:  5       42     42       38      31      39     17      17       11       31       0
N0.C0:  4       41     41       37      32      38     15      15       31        8       0
N4.C0:  6       42     42       39      32      38     14      14        8       31       0
N6.C0:  6       42     42       38      31      39     16      16        7       31       0
N0.C0:  5       41     41       37      33      38     16      16       31        8       0
N4.C0:  7       42     42       39      32      39     14      14        8       31       0
N6.C0:  7       42     42       38      31      39     17      17        6       31       0
N0.C0:  6       41     41       37      33      38     15      15       31        8       0
N4.C0:  8       42     42       39      32      39     14      14        8       31       0
N6.C0:  8       21     21       19      13      39     16      16        8       31       0
N0.C0:  7       41     41       37      33      38     16      16       31        8       0
N4.C0:  9       42     42       39      31      39     14      14        8       31       0
N4.C0: JckCompCodeCheck: Phase 2 - Check for bad ron_up vs average: num = 10, ron_up_avg = 42, ron_up_75avg = 31
N6.C0:  9       21     21       19      13      39     17      17        8       31       0
N0.C0:  8       41     41       37      33      38     16      16       31        8       0
N4.C0: Cycle ron_up ron_eq_up ron_dn ron_eq_dn odt scomp_up scom_dn tcomp_l2h tcomp_h2l   bad_training
N6.C0: JckCompCodeCheck: Phase 2 - Check for bad ron_up vs average: num = 10, ron_up_avg = 37, ron_up_75avg = 27
N4.C0: JckCompCodeCheck: Phase 3 - Comp Code Limits
N6.C0: Cycle ron_up ron_eq_up ron_dn ron_eq_dn odt scomp_up scom_dn tcomp_l2h tcomp_h2l   bad_training
N0.C0:  9       41     41       37      33      38     15      15       31        8       0
N4.C0: ron_up_limitdn   ron_dn_limitup   ron_eq_dn_limtdn  odt_limitdn
N6.C0:  8       21     21       19      13      39     16      16        8       31       1
N0.C0: JckCompCodeCheck: Phase 2 - Check for bad ron_up vs average: num = 10, ron_up_avg = 41, ron_up_75avg = 30
N4.C0:     26                46                21             24
N6.C0:  9       21     21       19      13      39     17      17        8       31       1
N0.C0: Cycle ron_up ron_eq_up ron_dn ron_eq_dn odt scomp_up scom_dn tcomp_l2h tcomp_h2l   bad_training
N4.C0: JckCompCodeCheck: Phase 3 - SUCCESS
N6.C0: JckCompCodeCheck: Phase 3 - Comp Code Limits
N0.C0: JckCompCodeCheck: Phase 3 - Comp Code Limits
N4.C0: VmseOverrideJckCompCodes
N6.C0: ron_up_limitdn   ron_dn_limitup   ron_eq_dn_limtdn  odt_limitdn
N0.C0: ron_up_limitdn   ron_dn_limitup   ron_eq_dn_limtdn  odt_limitdn
N6.C0:     26                45                20             24
N0.C0:     25                45                21             24
N6.C0: JckCompCodeCheck: Phase 4 - Retry Comp Code Results
N0.C0: JckCompCodeCheck: Phase 3 - SUCCESS
N6.C0: Cycle ron_up ron_eq_up ron_dn ron_eq_dn odt scomp_up scom_dn tcomp_l2h tcomp_h2l
N0.C0: VmseOverrideJckCompCodes
N6.C0:  0       21     21       19      13      39     17      17        8       31      -31747384
N6.C0:  1       43     43       39      31      39     17      17        5       31      -31747384
N6.C0: JckCompCodeCheck: Phase 4 - SUCCESS
N6.C0: VmseOverrideJckCompCodes
N2: SetupJckSmbCfg: JCK VLINFREQ set to: 0x820F1028
N2: SetupJckSmbCfg: PLL is locked.
N2.C2: SetupJckSmbCfg: dlyFrms = 15
N2.C2: cwleffective = 8
N2.C2: PreVMSE Training raw cleff = 9, raw cwleff = 7
N2.C2: vmseratio = 0, revisionId = 5, vmse_mode = 1, QCRM_ENABLE = 0
N2: SetupJckSmbCfg: JCK wpsyncrcven = 5, wpsyncdata = 10
N2.C1: SELF CAL 
N2.C1: JckCompCodeCheck: Phase 1 - Comp Code Results
N2.C1: Cycle ron_up ron_eq_up ron_dn ron_eq_dn odt scomp_up scom_dn tcomp_l2h tcomp_h2l   bad_training
N4: SetupJckSmbCfg: JCK VLINFREQ set to: 0x820F1028
N2.C1:  0       42     42       39      27      38     15      15        6       31       0
N4: SetupJckSmbCfg: PLL is locked.
Checkpoint Code: Socket 0, 0xB6, 0xA0, 0x0000
N4.C2: SetupJckSmbCfg: dlyFrms = 15
N4.C2: cwleffective = 8
N4.C2: PreVMSE Training raw cleff = 9, raw cwleff = 7
N2.C1:  1       42     42       39      32      38     15      15        8       31       0
N4.C2: vmseratio = 0, revisionId = 5, vmse_mode = 1, QCRM_ENABLE = 0
N0: SetupJckSmbCfg: JCK VLINFREQ set to: 0x820F1028
N4: SetupJckSmbCfg: JCK wpsyncrcven = 5, wpsyncdata = 10
N0: SetupJckSmbCfg: PLL is locked.
N0.C2: SetupJckSmbCfg: dlyFrms = 15
N2.C1:  2       42     42       39      32      38     15      15        6       31       0
N0.C2: cwleffective = 8
N0.C2: PreVMSE Training raw cleff = 9, raw cwleff = 7
N0.C2: vmseratio = 0, revisionId = 5, vmse_mode = 1, QCRM_ENABLE = 0
N0: SetupJckSmbCfg: JCK wpsyncrcven = 5, wpsyncdata = 10
N2.C1:  3       42     42       39      27      38     15      15        6       31       0
N6: SetupJckSmbCfg: JCK VLINFREQ set to: 0x820F1028
N6: SetupJckSmbCfg: PLL is locked.
N6.C2: SetupJckSmbCfg: dlyFrms = 15
N2.C1:  4       42     42       39      32      38     15      15        7       31       0
N6.C2: cwleffective = 8
N6.C2: PreVMSE Training raw cleff = 9, raw cwleff = 7
N6.C2: vmseratio = 0, revisionId = 5, vmse_mode = 1, QCRM_ENABLE = 0
N6: SetupJckSmbCfg: JCK wpsyncrcven = 5, wpsyncdata = 10
N2.C1:  5       42     42       39      32      38     15      15        7       31       0
N2.C1:  6       42     42       39      31      38     15      15        8       31       0
N2.C1:  7       42     42       39      31      38     15      15        7       31       0
N2.C1:  8       42     42       39      32      38     15      15        8       31       0
N2.C1:  9       42     42       39      32      38     15      15        7       31       0
N2.C1: JckCompCodeCheck: Phase 2 - Check for bad ron_up vs average: num = 10, ron_up_avg = 42, ron_up_75avg = 31
N2.C1: Cycle ron_up ron_eq_up ron_dn ron_eq_dn odt scomp_up scom_dn tcomp_l2h tcomp_h2l   bad_training
N2.C1: JckCompCodeCheck: Phase 3 - Comp Code Limits
N2.C1: ron_up_limitdn   ron_dn_limitup   ron_eq_dn_limtdn  odt_limitdn
N2.C1:     26                46                21             24
N2.C1: JckCompCodeCheck: Phase 3 - SUCCESS
N2.C1: VmseOverrideJckCompCodes
N4.C1: SELF CAL 
N4.C1: JckCompCodeCheck: Phase 1 - Comp Code Results
N4.C1: Cycle ron_up ron_eq_up ron_dn ron_eq_dn odt scomp_up scom_dn tcomp_l2h tcomp_h2l   bad_training
N0.C1: SELF CAL 
N4.C1:  0       42     42       39      31      38     14      14       14       31       0
N0.C1: JckCompCodeCheck: Phase 1 - Comp Code Results
N0.C1: Cycle ron_up ron_eq_up ron_dn ron_eq_dn odt scomp_up scom_dn tcomp_l2h tcomp_h2l   bad_training
N4.C1:  1       42     42       39      31      38     14      14       14       31       0
N0.C1:  0       41     41       37      32      38     16      16        8       31       0
N4.C1:  2       42     42       39      31      38     14      14       14       31       0
N6.C1: SELF CAL 
N0.C1:  1       41     41       37      32      38     16      16        8       31       0
N6.C1: JckCompCodeCheck: Phase 1 - Comp Code Results
N6.C1: Cycle ron_up ron_eq_up ron_dn ron_eq_dn odt scomp_up scom_dn tcomp_l2h tcomp_h2l   bad_training
N4.C1:  3       42     42       39      31      38     14      14       15       31       0
N0.C1:  2       41     41       37      32      38     15      15        8       31       0
N6.C1:  0       41     41       38      30      38     15      15        8       31       0
N4.C1:  4       42     42       39      30      38     14      14       15       31       0
N0.C1:  3       41     41       37      31      38     16      16        8       31       0
N6.C1:  1       41     41       38      30      38     15      15       10       31       0
N4.C1:  5       42     42       39      31      38     14      14       15       31       0
N0.C1:  4       41     41       37      32      38     16      16        8       31       0
N6.C1:  2       41     41       38      29      38     15      15        9       31       0
N4.C1:  6       42     42       39      31      38     14      14       16       31       0
N0.C1:  5       41     41       37      31      38     16      16        8       31       0
N6.C1:  3       41     41       38      30      38     15      15        9       31       0
N4.C1:  7       42     42       39      29      38     16      16       12       31       0
N0.C1:  6       41     41       37      32      38     16      16        8       31       0
N6.C1:  4       41     41       38      30      38     15      15        8       31       0
N4.C1:  8       42     42       39      31      38     14      14       14       31       0
N0.C1:  7       41     41       37      32      38     16      16        8       31       0
N6.C1:  5       41     41       38      30      38     15      15        7       31       0
N4.C1:  9       42     42       39      31      38     14      14       13       31       0
N4.C1: JckCompCodeCheck: Phase 2 - Check for bad ron_up vs average: num = 10, ron_up_avg = 42, ron_up_75avg = 31
N0.C1:  8       41     41       37      29      38     16      16        8       31       0
N4.C1: Cycle ron_up ron_eq_up ron_dn ron_eq_dn odt scomp_up scom_dn tcomp_l2h tcomp_h2l   bad_training
N6.C1:  6       41     41       38      30      38     15      15        8       31       0
N4.C1: JckCompCodeCheck: Phase 3 - Comp Code Limits
N4.C1: ron_up_limitdn   ron_dn_limitup   ron_eq_dn_limtdn  odt_limitdn
N0.C1:  9       41     41       37      32      38     16      16        8       31       0
N4.C1:     26                46                20             24
N0.C1: JckCompCodeCheck: Phase 2 - Check for bad ron_up vs average: num = 10, ron_up_avg = 41, ron_up_75avg = 30
N4.C1: JckCompCodeCheck: Phase 3 - SUCCESS
N6.C1:  7       41     41       38      30      38     15      15        8       31       0
N0.C1: Cycle ron_up ron_eq_up ron_dn ron_eq_dn odt scomp_up scom_dn tcomp_l2h tcomp_h2l   bad_training
N4.C1: VmseOverrideJckCompCodes
N0.C1: JckCompCodeCheck: Phase 3 - Comp Code Limits
N0.C1: ron_up_limitdn   ron_dn_limitup   ron_eq_dn_limtdn  odt_limitdn
N0.C1:     25                45                21             24
N6.C1:  8       41     41       38      30      38     15      15        7       31       0
N0.C1: JckCompCodeCheck: Phase 3 - SUCCESS
N0.C1: VmseOverrideJckCompCodes
N6.C1:  9       41     41       38      30      38     15      15        8       31       0
N6.C1: JckCompCodeCheck: Phase 2 - Check for bad ron_up vs average: num = 10, ron_up_avg = 41, ron_up_75avg = 30
N6.C1: Cycle ron_up ron_eq_up ron_dn ron_eq_dn odt scomp_up scom_dn tcomp_l2h tcomp_h2l   bad_training
N6.C1: JckCompCodeCheck: Phase 3 - Comp Code Limits
N6.C1: ron_up_limitdn   ron_dn_limitup   ron_eq_dn_limtdn  odt_limitdn
N2: Start VMSE training Sequence
N6.C1:     25                45                20             24
N2: ddrCh0.enabled = 1
N6.C1: JckCompCodeCheck: Phase 3 - SUCCESS
N2: ddrCh1.enabled = 1
N6.C1: VmseOverrideJckCompCodes
N2: ddrCh2.enabled = 1
N2: ddrCh3.enabled = 1
N2: VMSE0.enabled = 1
N2: VMSE1.enabled = 1
N2: CpgcVmseTraining for VMSE0
N2: Initialize VMSE Channels

START - VMSE Detect DC
N2: HsxVmseCompInit
N2.C0: Skip DC Detect check for CMD results
N2.C0: Skip DC Detect check for CMD results
N2: HsxVmseCompInit
N2.C0: VmseDetectDC: SUCCESS
N2.C0: VmseDetectClock
N2.C0: VmseDetectClock: SUCCESS

END - VMSE Detect DC                   Time         212 ms

START - MXB Clock Train
N2.C0: VmseAdjustVckVoc: retrain Clock DCC.
   dcc1_vck = 0x3F, dcc2_vck = 0x39, preampvoc = 0xE
N2.C0: VmseRefVckResync: ddrFreq = 0x2, VMSE_MODE_2_1 = 1, VMSE_PREAMBLE_2UI = 0
N2.C0: VmseRefVckResync: VLINKFREQNXT set to: 0x20F940A
N2.C0: VmseTrainClockAlign: JCK clkadjcnt =0

END - MXB Clock Train                  Time         222 ms

START - VMSE Train Command
N2.C0.B00: HsxCtlXoverInit: invertPiClk = 0x0, RankUsed = 0xFFF, Training = 0x38FFF09
N2.C0.B01: HsxCtlXoverInit: invertPiClk = 0x0, RankUsed = 0xFFF, Training = 0x38FFF26
N2.C0: VmseTrainCmdFine: vmse link sts = 0x4947
N4: Start VMSE training Sequence
N4: ddrCh0.enabled = 1
N4: ddrCh1.enabled = 1
N4: ddrCh2.enabled = 1
N4: ddrCh3.enabled = 1
N4: VMSE0.enabled = 1
N4: VMSE1.enabled = 1
N4: CpgcVmseTraining for VMSE0
N4: Initialize VMSE Channels

START - VMSE Detect DC
N4: HsxVmseCompInit
Checkpoint Code: Socket 0, 0xB6, 0xA0, 0x0000
N4.C0: Skip DC Detect check for CMD results
Checkpoint Code: Socket 0, 0xB6, 0x10, 0x0000
N0: Start VMSE training Sequence
N0: ddrCh0.enabled = 1
N0: ddrCh1.enabled = 1
N4.C0: Skip DC Detect check for CMD results
N0: ddrCh2.enabled = 1
N4: HsxVmseCompInit
N0: ddrCh3.enabled = 1
N4.C0: VmseDetectDC: SUCCESS
N0: VMSE0.enabled = 1
N4.C0: VmseDetectClock
N0: VMSE1.enabled = 1
N0: CpgcVmseTraining for VMSE0
Checkpoint Code: Socket 0, 0xB6, 0x11, 0x0000
N0: Initialize VMSE Channels

START - VMSE Detect DC
Checkpoint Code: Socket 0, 0xB6, 0x46, 0x0000
N0: HsxVmseCompInit
Checkpoint Code: Socket 0, 0xB6, 0x80, 0x0000
N0.C0: Skip DC Detect check for CMD results
N6: Start VMSE training Sequence
N6: ddrCh0.enabled = 1
N0.C0: Skip DC Detect check for CMD results
N6: ddrCh1.enabled = 1
N0: HsxVmseCompInit
N6: ddrCh2.enabled = 1
Checkpoint Code: Socket 0, 0xB6, 0x81, 0x0000
N6: ddrCh3.enabled = 1
N0.C0: VmseDetectDC: SUCCESS
N6: VMSE0.enabled = 1
N0.C0: VmseDetectClock
N6: VMSE1.enabled = 1
N6: CpgcVmseTraining for VMSE0
N6: Initialize VMSE Channels

START - VMSE Detect DC
N6: HsxVmseCompInit
N6.C0: Skip DC Detect check for CMD results
N6.C0: Skip DC Detect check for CMD results
N6: HsxVmseCompInit
N6.C0: VmseDetectDC: SUCCESS
N6.C0: VmseDetectClock
N4.C0: VmseDetectClock: SUCCESS

END - VMSE Detect DC                   Time         223 ms

START - MXB Clock Train
N0.C0: VmseDetectClock: SUCCESS

END - VMSE Detect DC                   Time         237 ms

START - MXB Clock Train
Checkpoint Code: Socket 0, 0xB6, 0x48, 0x0000
N4.C0: VmseAdjustVckVoc: retrain Clock DCC.
   dcc1_vck = 0x3F, dcc2_vck = 0x2D, preampvoc = 0xA
Checkpoint Code: Socket 0, 0xB6, 0x6C, 0x0000
N6.C0: VmseDetectClock: SUCCESS

END - VMSE Detect DC                   Time         214 ms

START - MXB Clock Train
N4.C0: VmseAdjustVckVoc: retrain Clock DCC.
   dcc1_vck = 0x3F, dcc2_vck = 0x1F, preampvoc = 0xB
N0.C0: VmseRefVckResync: ddrFreq = 0x2, VMSE_MODE_2_1 = 1, VMSE_PREAMBLE_2UI = 0
N0.C0: VmseRefVckResync: VLINKFREQNXT set to: 0x20F940A
N4.C0: VmseRefVckResync: ddrFreq = 0x2, VMSE_MODE_2_1 = 1, VMSE_PREAMBLE_2UI = 0
N6.C0: VmseAdjustVckVoc: retrain Clock DCC.
   dcc1_vck = 0x6, dcc2_vck = 0x3F, preampvoc = 0xE
N0.C0: VmseTrainClockAlign: JCK clkadjcnt =3
N4.C0: VmseRefVckResync: VLINKFREQNXT set to: 0x20F940A

END - MXB Clock Train                  Time         168 ms

START - VMSE Train Command
Checkpoint Code: Socket 0, 0xB6, 0x4A, 0x0000
N4.C0: VmseTrainClockAlign: JCK clkadjcnt =2
N0.C0.B00: HsxCtlXoverInit: invertPiClk = 0x0, RankUsed = 0xFFF, Training = 0x38FFF08

END - MXB Clock Train                  Time         291 ms
N6.C0: VmseRefVckResync: ddrFreq = 0x2, VMSE_MODE_2_1 = 1, VMSE_PREAMBLE_2UI = 0
N0.C0.B01: HsxCtlXoverInit: invertPiClk = 0x0, RankUsed = 0xFFF, Training = 0x38FFF26

START - VMSE Train Command
Checkpoint Code: Socket 0, 0xB6, 0x60, 0x0000
N6.C0: VmseRefVckResync: VLINKFREQNXT set to: 0x20F940A
N4.C0.B00: HsxCtlXoverInit: invertPiClk = 0x0, RankUsed = 0xFFF, Training = 0x38FFF07
N4.C0.B01: HsxCtlXoverInit: invertPiClk = 0x0, RankUsed = 0xFFF, Training = 0x38FFF25
N6.C0: VmseTrainClockAlign: JCK clkadjcnt =7
Checkpoint Code: Socket 0, 0xB6, 0x5A, 0x0000

END - MXB Clock Train                  Time         234 ms

START - VMSE Train Command
N0.C0: VmseTrainCmdFine: vmse link sts = 0x4947
N6.C0.B00: HsxCtlXoverInit: invertPiClk = 0x0, RankUsed = 0xFFF, Training = 0x38FFF05
N6.C0.B01: HsxCtlXoverInit: invertPiClk = 0x0, RankUsed = 0xFFF, Training = 0x38FFF23
N4.C0: VmseTrainCmdFine: vmse link sts = 0x4947
N6.C0: VmseTrainCmdFine: vmse link sts = 0x4947
Entry 0 - TrainDcc - DCCStart: 58, VocStart: 14, DCCFinal: 18, VocFinal: 14
Entry 1 - TrainDcc - DCCStart: 40, VocStart: 14, DCCFinal: 32, VocFinal: 14
Entry 0 - TrainDcc - DCCStart: 17, VocStart: 17, DCCFinal: 17, VocFinal: 17
Entry 1 - TrainDcc - DCCStart: 28, VocStart: 17, DCCFinal: 20, VocFinal: 17
Entry 0 - TrainDcc - DCCStart: 4, VocStart: 14, DCCFinal: 12, VocFinal: 14
Entry 1 - TrainDcc - DCCStart: 51, VocStart: 14, DCCFinal: 27, VocFinal: 14
N2.C0.S00: VmseCmdFineTraining Final: centerPi = 0x60, PiEw = 0x2F, centerVref = 0x39, vrefHeight = 0x43
N2.C0.S01: VmseCmdFineTraining Final: centerPi = 0x60, PiEw = 0x30, centerVref = 0x3A, vrefHeight = 0x41
N2.C0.S02: VmseCmdFineTraining Final: centerPi = 0x5E, PiEw = 0x33, centerVref = 0x36, vrefHeight = 0x47
N2.C0.S03: VmseCmdFineTraining Final: centerPi = 0x62, PiEw = 0x32, centerVref = 0x3C, vrefHeight = 0x41
N2.C0.S04: VmseCmdFineTraining Final: centerPi = 0x59, PiEw = 0x2F, centerVref = 0x3A, vrefHeight = 0x43
N2.C0.S05: VmseCmdFineTraining Final: centerPi = 0x5F, PiEw = 0x31, centerVref = 0x36, vrefHeight = 0x47
N2.C0.S06: VmseCmdFineTraining Final: centerPi = 0x5D, PiEw = 0x30, centerVref = 0x3D, vrefHeight = 0x45
N2.C0.S07: VmseCmdFineTraining Final: centerPi = 0x5F, PiEw = 0x31, centerVref = 0x38, vrefHeight = 0x43
N2.C0.S08: VmseCmdFineTraining Final: centerPi = 0x5A, PiEw = 0x30, centerVref = 0x3A, vrefHeight = 0x41
N2.C0.S09: VmseCmdFineTraining Final: centerPi = 0x5E, PiEw = 0x2D, centerVref = 0x39, vrefHeight = 0x3F
N2.C0.S10: VmseCmdFineTraining Final: centerPi = 0x61, PiEw = 0x2D, centerVref = 0x35, vrefHeight = 0x45
N2.C0.S11: VmseCmdFineTraining Final: centerPi = 0x5A, PiEw = 0x2D, centerVref = 0x38, vrefHeight = 0x43
N2.C0.S12: VmseCmdFineTraining Final: centerPi = 0x5F, PiEw = 0x2F, centerVref = 0x3B, vrefHeight = 0x47
N2.C0.S13: VmseCmdFineTraining Final: centerPi = 0x5A, PiEw = 0x2F, centerVref = 0x39, vrefHeight = 0x41
N2.C0.S14: VmseCmdFineTraining Final: centerPi = 0x60, PiEw = 0x2E, centerVref = 0x39, vrefHeight = 0x47
N2.C0.S15: VmseCmdFineTraining Final: centerPi = 0x63, PiEw = 0x2F, centerVref = 0x40, vrefHeight = 0x41
N2.C0.S16: VmseCmdFineTraining Final: centerPi = 0x5C, PiEw = 0x2C, centerVref = 0x36, vrefHeight = 0x45
Entry 0 - TrainDcc - DCCStart: 60, VocStart: 11, DCCFinal: 12, VocFinal: 11
Entry 1 - TrainDcc - DCCStart: 23, VocStart: 11, DCCFinal: 15, VocFinal: 11

END - VMSE Train Command               Time         7208 ms

START - VMSE Train Read Leveling
N2.C0: VmseReadLevelFineSetup: Initial RT = 101, Initial IO Latency = 0, Initial IO Comp = 15
N2.C0: VmseRLWLFineSearchAll: Entry
N2.C0: FINE READ LEVEL DELAY
N2.C0.S00: RCVEN DELAY = 153
N2.C0.S01: RCVEN DELAY = 153
N2.C0.S02: RCVEN DELAY = 46
N2.C0.S03: RCVEN DELAY = 49
N2.C0.S04: RCVEN DELAY = 61
N0.C0.S00: VmseCmdFineTraining Final: centerPi = 0x60, PiEw = 0x2F, centerVref = 0x3E, vrefHeight = 0x3D
N2.C0.S05: RCVEN DELAY = 130
N0.C0.S01: VmseCmdFineTraining Final: centerPi = 0x60, PiEw = 0x2D, centerVref = 0x3A, vrefHeight = 0x43
N2.C0.S06: RCVEN DELAY = 58
N0.C0.S02: VmseCmdFineTraining Final: centerPi = 0x5D, PiEw = 0x32, centerVref = 0x39, vrefHeight = 0x43
N2.C0.S07: RCVEN DELAY = 129
N0.C0.S03: VmseCmdFineTraining Final: centerPi = 0x60, PiEw = 0x30, centerVref = 0x3C, vrefHeight = 0x3D
N2.C0.S08: RCVEN DELAY = 84
N0.C0.S04: VmseCmdFineTraining Final: centerPi = 0x57, PiEw = 0x2F, centerVref = 0x3F, vrefHeight = 0x3B
N2.C0.S00: READ LEVEL: FINAL RCVEN DELAY (both nibbles) = 122
N0.C0.S05: VmseCmdFineTraining Final: centerPi = 0x5B, PiEw = 0x30, centerVref = 0x3B, vrefHeight = 0x3F
N2.C0.S01: READ LEVEL: FINAL RCVEN DELAY (both nibbles) = 122
N0.C0.S06: VmseCmdFineTraining Final: centerPi = 0x5D, PiEw = 0x30, centerVref = 0x3C, vrefHeight = 0x41
N2.C0.S02: READ LEVEL: FINAL RCVEN DELAY (both nibbles) = 144
N0.C0.S07: VmseCmdFineTraining Final: centerPi = 0x5D, PiEw = 0x31, centerVref = 0x3E, vrefHeight = 0x3D
N2.C0.S03: READ LEVEL: FINAL RCVEN DELAY (both nibbles) = 146
N0.C0.S08: VmseCmdFineTraining Final: centerPi = 0x59, PiEw = 0x31, centerVref = 0x3E, vrefHeight = 0x41
N2.C0.S04: READ LEVEL: FINAL RCVEN DELAY (both nibbles) = 161
N0.C0.S09: VmseCmdFineTraining Final: centerPi = 0x5C, PiEw = 0x2F, centerVref = 0x3D, vrefHeight = 0x3B
N2.C0.S05: READ LEVEL: FINAL RCVEN DELAY (both nibbles) = 99
N0.C0.S10: VmseCmdFineTraining Final: centerPi = 0x5E, PiEw = 0x30, centerVref = 0x3E, vrefHeight = 0x3D
N2.C0.S06: READ LEVEL: FINAL RCVEN DELAY (both nibbles) = 155
N0.C0.S11: VmseCmdFineTraining Final: centerPi = 0x58, PiEw = 0x2F, centerVref = 0x3B, vrefHeight = 0x41
N2.C0.S07: READ LEVEL: FINAL RCVEN DELAY (both nibbles) = 97
N0.C0.S12: VmseCmdFineTraining Final: centerPi = 0x5F, PiEw = 0x30, centerVref = 0x3A, vrefHeight = 0x43
N2.C0.S08: READ LEVEL: FINAL RCVEN DELAY (both nibbles) = 183
N0.C0.S13: VmseCmdFineTraining Final: centerPi = 0x56, PiEw = 0x30, centerVref = 0x41, vrefHeight = 0x37
N2.C0.D0.S09: READ LEVEL: FINAL RT (all ranks) = 83, FINAL IO LATENCY (all ranks) = 2
N0.C0.S14: VmseCmdFineTraining Final: centerPi = 0x5D, PiEw = 0x31, centerVref = 0x41, vrefHeight = 0x3F
N2.C0.D1.S09: READ LEVEL: FINAL RT (all ranks) = 83, FINAL IO LATENCY (all ranks) = 2
N6.C0.S00: VmseCmdFineTraining Final: centerPi = 0x60, PiEw = 0x2F, centerVref = 0x3D, vrefHeight = 0x41
N0.C0.S15: VmseCmdFineTraining Final: centerPi = 0x5F, PiEw = 0x30, centerVref = 0x3D, vrefHeight = 0x39

END - VMSE Train Read Leveling         Time         426 ms
N6.C0.S01: VmseCmdFineTraining Final: centerPi = 0x5E, PiEw = 0x2E, centerVref = 0x35, vrefHeight = 0x47
N0.C0.S16: VmseCmdFineTraining Final: centerPi = 0x5B, PiEw = 0x2E, centerVref = 0x3D, vrefHeight = 0x41

START - VMSE Train Read
N6.C0.S02: VmseCmdFineTraining Final: centerPi = 0x5C, PiEw = 0x31, centerVref = 0x39, vrefHeight = 0x47
N6.C0.S03: VmseCmdFineTraining Final: centerPi = 0x61, PiEw = 0x30, centerVref = 0x38, vrefHeight = 0x43
N6.C0.S04: VmseCmdFineTraining Final: centerPi = 0x58, PiEw = 0x2E, centerVref = 0x3C, vrefHeight = 0x45
N6.C0.S05: VmseCmdFineTraining Final: centerPi = 0x5A, PiEw = 0x2F, centerVref = 0x36, vrefHeight = 0x45
N6.C0.S06: VmseCmdFineTraining Final: centerPi = 0x5D, PiEw = 0x31, centerVref = 0x3B, vrefHeight = 0x49
N6.C0.S07: VmseCmdFineTraining Final: centerPi = 0x5D, PiEw = 0x30, centerVref = 0x37, vrefHeight = 0x45
N6.C0.S08: VmseCmdFineTraining Final: centerPi = 0x59, PiEw = 0x32, centerVref = 0x39, vrefHeight = 0x41
N6.C0.S09: VmseCmdFineTraining Final: centerPi = 0x5C, PiEw = 0x2F, centerVref = 0x3B, vrefHeight = 0x3F
N6.C0.S10: VmseCmdFineTraining Final: centerPi = 0x5F, PiEw = 0x2E, centerVref = 0x3B, vrefHeight = 0x3F
N6.C0.S11: VmseCmdFineTraining Final: centerPi = 0x5A, PiEw = 0x2F, centerVref = 0x39, vrefHeight = 0x47
N6.C0.S12: VmseCmdFineTraining Final: centerPi = 0x5F, PiEw = 0x30, centerVref = 0x39, vrefHeight = 0x47
N6.C0.S13: VmseCmdFineTraining Final: centerPi = 0x59, PiEw = 0x31, centerVref = 0x38, vrefHeight = 0x43
N6.C0.S14: VmseCmdFineTraining Final: centerPi = 0x5E, PiEw = 0x30, centerVref = 0x37, vrefHeight = 0x47
N6.C0.S15: VmseCmdFineTraining Final: centerPi = 0x63, PiEw = 0x31, centerVref = 0x33, vrefHeight = 0x45

END - VMSE Train Command               Time         7201 ms
N6.C0.S16: VmseCmdFineTraining Final: centerPi = 0x5D, PiEw = 0x2D, centerVref = 0x36, vrefHeight = 0x47

START - VMSE Train Read Leveling
Checkpoint Code: Socket 0, 0xB6, 0x4E, 0x0000
N0.C0: VmseReadLevelFineSetup: Initial RT = 101, Initial IO Latency = 0, Initial IO Comp = 15
N0.C0: VmseRLWLFineSearchAll: Entry
N0.C0: FINE READ LEVEL DELAY

END - VMSE Train Command               Time         7252 ms
N0.C0.S00: RCVEN DELAY = 31

START - VMSE Train Read Leveling
N0.C0.S01: RCVEN DELAY = 154
N0.C0.S02: RCVEN DELAY = 46
N0.C0.S03: RCVEN DELAY = 50
N0.C0.S04: RCVEN DELAY = 123
N0.C0.S05: RCVEN DELAY = 133
N0.C0.S06: RCVEN DELAY = 126
N0.C0.S07: RCVEN DELAY = 131
N0.C0.S08: RCVEN DELAY = 148
N0.C0.S00: READ LEVEL: FINAL RCVEN DELAY (both nibbles) = 130
N0.C0.S01: READ LEVEL: FINAL RCVEN DELAY (both nibbles) = 122
N0.C0.S02: READ LEVEL: FINAL RCVEN DELAY (both nibbles) = 143
N4.C0.S00: VmseCmdFineTraining Final: centerPi = 0x61, PiEw = 0x30, centerVref = 0x38, vrefHeight = 0x3F
N0.C0.S03: READ LEVEL: FINAL RCVEN DELAY (both nibbles) = 148
N4.C0.S01: VmseCmdFineTraining Final: centerPi = 0x5C, PiEw = 0x2D, centerVref = 0x46, vrefHeight = 0x3F
N0.C0.S04: READ LEVEL: FINAL RCVEN DELAY (both nibbles) = 91
N4.C0.S02: VmseCmdFineTraining Final: centerPi = 0x5C, PiEw = 0x31, centerVref = 0x3D, vrefHeight = 0x41
N6.C0: VmseReadLevelFineSetup: Initial RT = 101, Initial IO Latency = 0, Initial IO Comp = 15
N0.C0.S05: READ LEVEL: FINAL RCVEN DELAY (both nibbles) = 103
N4.C0.S03: VmseCmdFineTraining Final: centerPi = 0x5E, PiEw = 0x30, centerVref = 0x3E, vrefHeight = 0x41
N0.C0.S06: READ LEVEL: FINAL RCVEN DELAY (both nibbles) = 93
N4.C0.S04: VmseCmdFineTraining Final: centerPi = 0x55, PiEw = 0x30, centerVref = 0x3C, vrefHeight = 0x3D
N0.C0.S07: READ LEVEL: FINAL RCVEN DELAY (both nibbles) = 100
N4.C0.S05: VmseCmdFineTraining Final: centerPi = 0x57, PiEw = 0x2F, centerVref = 0x3F, vrefHeight = 0x3F
N6.C0: VmseRLWLFineSearchAll: Entry
N0.C0.S08: READ LEVEL: FINAL RCVEN DELAY (both nibbles) = 117
N4.C0.S06: VmseCmdFineTraining Final: centerPi = 0x61, PiEw = 0x31, centerVref = 0x2F, vrefHeight = 0x47
N6.C0: FINE READ LEVEL DELAY
N0.C0.D0.S09: READ LEVEL: FINAL RT (all ranks) = 83, FINAL IO LATENCY (all ranks) = 2
N4.C0.S07: VmseCmdFineTraining Final: centerPi = 0x5D, PiEw = 0x32, centerVref = 0x37, vrefHeight = 0x41
N6.C0.S00: RCVEN DELAY = 32
N0.C0.D1.S09: READ LEVEL: FINAL RT (all ranks) = 83, FINAL IO LATENCY (all ranks) = 2
N4.C0.S08: VmseCmdFineTraining Final: centerPi = 0x58, PiEw = 0x31, centerVref = 0x39, vrefHeight = 0x3F
N6.C0.S01: RCVEN DELAY = 154

END - VMSE Train Read Leveling         Time         390 ms
N4.C0.S09: VmseCmdFineTraining Final: centerPi = 0x5B, PiEw = 0x2D, centerVref = 0x42, vrefHeight = 0x3B
N6.C0.S02: RCVEN DELAY = 45

START - VMSE Train Read
N4.C0.S10: VmseCmdFineTraining Final: centerPi = 0x5A, PiEw = 0x2E, centerVref = 0x44, vrefHeight = 0x3D
N6.C0.S03: RCVEN DELAY = 47
Checkpoint Code: Socket 0, 0xB6, 0x50, 0x0000
N4.C0.S11: VmseCmdFineTraining Final: centerPi = 0x56, PiEw = 0x30, centerVref = 0x3B, vrefHeight = 0x41
N6.C0.S04: RCVEN DELAY = 125
N4.C0.S12: VmseCmdFineTraining Final: centerPi = 0x5E, PiEw = 0x31, centerVref = 0x38, vrefHeight = 0x43
N6.C0.S05: RCVEN DELAY = 133
N4.C0.S13: VmseCmdFineTraining Final: centerPi = 0x57, PiEw = 0x31, centerVref = 0x38, vrefHeight = 0x41
N6.C0.S06: RCVEN DELAY = 125
N4.C0.S14: VmseCmdFineTraining Final: centerPi = 0x5E, PiEw = 0x33, centerVref = 0x3A, vrefHeight = 0x45
N6.C0.S07: RCVEN DELAY = 132
N4.C0.S15: VmseCmdFineTraining Final: centerPi = 0x60, PiEw = 0x2D, centerVref = 0x3D, vrefHeight = 0x3F
N6.C0.S08: RCVEN DELAY = 148
N4.C0.S16: VmseCmdFineTraining Final: centerPi = 0x5A, PiEw = 0x2D, centerVref = 0x3C, vrefHeight = 0x41
N6.C0.S00: READ LEVEL: FINAL RCVEN DELAY (both nibbles) = 259
N6.C0.S01: READ LEVEL: FINAL RCVEN DELAY (both nibbles) = 251
N6.C0.S02: READ LEVEL: FINAL RCVEN DELAY (both nibbles) = 271
N6.C0.S03: READ LEVEL: FINAL RCVEN DELAY (both nibbles) = 274
N6.C0.S04: READ LEVEL: FINAL RCVEN DELAY (both nibbles) = 221
N6.C0.S05: READ LEVEL: FINAL RCVEN DELAY (both nibbles) = 232
N6.C0.S06: READ LEVEL: FINAL RCVEN DELAY (both nibbles) = 221
N6.C0.S07: READ LEVEL: FINAL RCVEN DELAY (both nibbles) = 229
N6.C0.S08: READ LEVEL: FINAL RCVEN DELAY (both nibbles) = 245
N6.C0.D0.S09: READ LEVEL: FINAL RT (all ranks) = 85, FINAL IO LATENCY (all ranks) = 4
N6.C0.D1.S09: READ LEVEL: FINAL RT (all ranks) = 85, FINAL IO LATENCY (all ranks) = 4

END - VMSE Train Read Leveling         Time         440 ms

START - VMSE Train Read

END - VMSE Train Command               Time         7850 ms

START - VMSE Train Read Leveling
N4.C0: VmseReadLevelFineSetup: Initial RT = 101, Initial IO Latency = 0, Initial IO Comp = 15
N4.C0: VmseRLWLFineSearchAll: Entry
N4.C0: FINE READ LEVEL DELAY
N4.C0.S00: RCVEN DELAY = 150
N4.C0.S01: RCVEN DELAY = 144
N4.C0.S02: RCVEN DELAY = 37
N4.C0.S03: RCVEN DELAY = 40
N4.C0.S04: RCVEN DELAY = 119
N4.C0.S05: RCVEN DELAY = 125
N4.C0.S06: RCVEN DELAY = 119
N4.C0.S07: RCVEN DELAY = 122
N4.C0.S08: RCVEN DELAY = 142
N4.C0.S00: READ LEVEL: FINAL RCVEN DELAY (both nibbles) = 248
N4.C0.S01: READ LEVEL: FINAL RCVEN DELAY (both nibbles) = 240
N4.C0.S02: READ LEVEL: FINAL RCVEN DELAY (both nibbles) = 264
N4.C0.S03: READ LEVEL: FINAL RCVEN DELAY (both nibbles) = 267
N4.C0.S04: READ LEVEL: FINAL RCVEN DELAY (both nibbles) = 215
N4.C0.S05: READ LEVEL: FINAL RCVEN DELAY (both nibbles) = 223
N4.C0.S06: READ LEVEL: FINAL RCVEN DELAY (both nibbles) = 215
N4.C0.S07: READ LEVEL: FINAL RCVEN DELAY (both nibbles) = 218
N4.C0.S08: READ LEVEL: FINAL RCVEN DELAY (both nibbles) = 240
N4.C0.D0.S09: READ LEVEL: FINAL RT (all ranks) = 85, FINAL IO LATENCY (all ranks) = 4
N4.C0.D1.S09: READ LEVEL: FINAL RT (all ranks) = 85, FINAL IO LATENCY (all ranks) = 4

END - VMSE Train Read Leveling         Time         265 ms

START - VMSE Train Read

END - VMSE Train Read                  Time         4053 ms

START - VMSE Train Level Tx DQS DCC
N2.C0: VmseLevelTxDqsDccExecute: MXB DQS DCC Finished Successfully

END - VMSE Train Level Tx DQS DCC      Time         12 ms

START - VMSE Train Write Leveling
N2.C0: VmseWriteLevelFineSetup: Set push to data delay = 6, Global TX DQS delay = 0
N2.C0: VmseRLWLFineSearchAll: Entry
N2.C0: FINE WRITE LEVEL DELAY
N2.C0.S00: TX DQS DELAY = 116
N2.C0.S01: TX DQS DELAY = 118
N2.C0.S02: TX DQS DELAY = 95
N2.C0.S03: TX DQS DELAY = 97
N2.C0.S04: TX DQS DELAY = 86
N2.C0.S05: TX DQS DELAY = 140
N2.C0.S06: TX DQS DELAY = 84
N2.C0.S07: TX DQS DELAY = 140
N2.C0.S08: TX DQS DELAY = 51
N2.C0: VmseWriteLevelCoarseSetup: Set push to data delay = 6, Global TX DQS delay = 0
N2.C0: VmseWriteLevelCoarseExecute
N2.C0: VmseWLCoarseUpdatePD: New push to data delay = 6, New global TxDQS delay = 1
N2.C0: VmseWLCoarseUpdatePD: New push to data delay = 7, New global TxDQS delay = 0
N2.C0: VmseWLCoarseUpdatePD: New push to data delay = 7, New global TxDQS delay = 1
N2.C0: VmseWLCoarseUpdatePD: New push to data delay = 8, New global TxDQS delay = 0
N2.C0.S00: FINAL TX DQS BEFORE TxFIFO CHECK = 85
N2.C0.S01: FINAL TX DQS BEFORE TxFIFO CHECK = 88
N2.C0.S02: FINAL TX DQS BEFORE TxFIFO CHECK = 64
N2.C0.S03: FINAL TX DQS BEFORE TxFIFO CHECK = 67
N2.C0.S04: FINAL TX DQS BEFORE TxFIFO CHECK = 184
N2.C0.S05: FINAL TX DQS BEFORE TxFIFO CHECK = 109
N2.C0.S06: FINAL TX DQS BEFORE TxFIFO CHECK = 180
N2.C0.S07: FINAL TX DQS BEFORE TxFIFO CHECK = 111
N2.C0.S08: FINAL TX DQS BEFORE TxFIFO CHECK = 147
N2.C0: ResolveTxFIFOPtrSeparation: Smallest PI (64) < MIN ALLOWED DELAY (176) 
N2.C0: VmseIncTxFifoPtrSeparation: New push to data delay = 7
N2.C0.S00: VmseIncTxFifoPtrSeparation: pi adjustment = 128, FINAL TX DQS DELAY = 341
N2.C0.S01: VmseIncTxFifoPtrSeparation: pi adjustment = 128, FINAL TX DQS DELAY = 344
N2.C0.S02: VmseIncTxFifoPtrSeparation: pi adjustment = 128, FINAL TX DQS DELAY = 320
N2.C0.S03: VmseIncTxFifoPtrSeparation: pi adjustment = 128, FINAL TX DQS DELAY = 323
N2.C0.S04: VmseIncTxFifoPtrSeparation: pi adjustment = 128, FINAL TX DQS DELAY = 440
N2.C0.S05: VmseIncTxFifoPtrSeparation: pi adjustment = 128, FINAL TX DQS DELAY = 365
N2.C0.S06: VmseIncTxFifoPtrSeparation: pi adjustment = 128, FINAL TX DQS DELAY = 436
N2.C0.S07: VmseIncTxFifoPtrSeparation: pi adjustment = 128, FINAL TX DQS DELAY = 367
N2.C0.S08: VmseIncTxFifoPtrSeparation: pi adjustment = 128, FINAL TX DQS DELAY = 403

END - VMSE Train Write Leveling        Time         243 ms

START - VMSE Train Write

END - VMSE Train Read                  Time         3969 ms

START - VMSE Train Level Tx DQS DCC
Checkpoint Code: Socket 0, 0xB6, 0x52, 0x0000
N0.C0: VmseLevelTxDqsDccExecute: MXB DQS DCC Finished Successfully

END - VMSE Train Level Tx DQS DCC      Time         17 ms

START - VMSE Train Write Leveling
Checkpoint Code: Socket 0, 0xB6, 0x54, 0x0000
N0.C0: VmseWriteLevelFineSetup: Set push to data delay = 6, Global TX DQS delay = 0
N0.C0: VmseRLWLFineSearchAll: Entry
N0.C0: FINE WRITE LEVEL DELAY
N0.C0.S00: TX DQS DELAY = 114
N0.C0.S01: TX DQS DELAY = 114
N0.C0.S02: TX DQS DELAY = 100
N0.C0.S03: TX DQS DELAY = 98
N0.C0.S04: TX DQS DELAY = 146
N0.C0.S05: TX DQS DELAY = 141
N0.C0.S06: TX DQS DELAY = 145
N0.C0.S07: TX DQS DELAY = 141
N0.C0.S08: TX DQS DELAY = 116
N0.C0: VmseWriteLevelCoarseSetup: Set push to data delay = 6, Global TX DQS delay = 0
N0.C0: VmseWriteLevelCoarseExecute
Checkpoint Code: Socket 0, 0xB6, 0xAC, 0x0000
N0.C0: VmseWLCoarseUpdatePD: New push to data delay = 6, New global TxDQS delay = 1
N0.C0: VmseWLCoarseUpdatePD: New push to data delay = 7, New global TxDQS delay = 0
N0.C0: VmseWLCoarseUpdatePD: New push to data delay = 7, New global TxDQS delay = 1
N0.C0: VmseWLCoarseUpdatePD: New push to data delay = 8, New global TxDQS delay = 0

END - VMSE Train Read                  Time         3920 ms
N0.C0.S00: FINAL TX DQS BEFORE TxFIFO CHECK = 85

START - VMSE Train Level Tx DQS DCC
N0.C0.S01: FINAL TX DQS BEFORE TxFIFO CHECK = 85
N0.C0.S02: FINAL TX DQS BEFORE TxFIFO CHECK = 71
N6.C0: VmseLevelTxDqsDccExecute: MXB DQS DCC Finished Successfully
N0.C0.S03: FINAL TX DQS BEFORE TxFIFO CHECK = 67

END - VMSE Train Level Tx DQS DCC      Time         17 ms
N0.C0.S04: FINAL TX DQS BEFORE TxFIFO CHECK = 117

START - VMSE Train Write Leveling
N0.C0.S05: FINAL TX DQS BEFORE TxFIFO CHECK = 112
N6.C0: VmseWriteLevelFineSetup: Set push to data delay = 6, Global TX DQS delay = 0
N0.C0.S06: FINAL TX DQS BEFORE TxFIFO CHECK = 115
N0.C0.S07: FINAL TX DQS BEFORE TxFIFO CHECK = 112
N6.C0: VmseRLWLFineSearchAll: Entry
N0.C0.S08: FINAL TX DQS BEFORE TxFIFO CHECK = 89
N6.C0: FINE WRITE LEVEL DELAY
N0.C0: ResolveTxFIFOPtrSeparation: Smallest PI (67) < MIN ALLOWED DELAY (176) 
N6.C0.S00: TX DQS DELAY = 116
N0.C0: VmseIncTxFifoPtrSeparation: New push to data delay = 7
N6.C0.S01: TX DQS DELAY = 119
N0.C0.S00: VmseIncTxFifoPtrSeparation: pi adjustment = 128, FINAL TX DQS DELAY = 341
N6.C0.S02: TX DQS DELAY = 104
N0.C0.S01: VmseIncTxFifoPtrSeparation: pi adjustment = 128, FINAL TX DQS DELAY = 341
N6.C0.S03: TX DQS DELAY = 104
N0.C0.S02: VmseIncTxFifoPtrSeparation: pi adjustment = 128, FINAL TX DQS DELAY = 327
N6.C0.S04: TX DQS DELAY = 151
N0.C0.S03: VmseIncTxFifoPtrSeparation: pi adjustment = 128, FINAL TX DQS DELAY = 323
N6.C0.S05: TX DQS DELAY = 141
N0.C0.S04: VmseIncTxFifoPtrSeparation: pi adjustment = 128, FINAL TX DQS DELAY = 373
N6.C0.S06: TX DQS DELAY = 147
N0.C0.S05: VmseIncTxFifoPtrSeparation: pi adjustment = 128, FINAL TX DQS DELAY = 368
N6.C0.S07: TX DQS DELAY = 144
N0.C0.S06: VmseIncTxFifoPtrSeparation: pi adjustment = 128, FINAL TX DQS DELAY = 371
N6.C0.S08: TX DQS DELAY = 116
N0.C0.S07: VmseIncTxFifoPtrSeparation: pi adjustment = 128, FINAL TX DQS DELAY = 368
N6.C0: VmseWriteLevelCoarseSetup: Set push to data delay = 6, Global TX DQS delay = 0
N0.C0.S08: VmseIncTxFifoPtrSeparation: pi adjustment = 128, FINAL TX DQS DELAY = 345
N6.C0: VmseWriteLevelCoarseExecute

END - VMSE Train Write Leveling        Time         336 ms
N6.C0: VmseWLCoarseUpdatePD: New push to data delay = 6, New global TxDQS delay = 1

START - VMSE Train Write
N6.C0: VmseWLCoarseUpdatePD: New push to data delay = 7, New global TxDQS delay = 0
Checkpoint Code: Socket 0, 0xB6, 0x56, 0x0000
N6.C0: VmseWLCoarseUpdatePD: New push to data delay = 7, New global TxDQS delay = 1
N6.C0: VmseWLCoarseUpdatePD: New push to data delay = 8, New global TxDQS delay = 0
N6.C0: VmseWLCoarseUpdatePD: New push to data delay = 8, New global TxDQS delay = 1
N6.C0.S00: FINAL TX DQS BEFORE TxFIFO CHECK = 213
N6.C0.S01: FINAL TX DQS BEFORE TxFIFO CHECK = 218
N6.C0.S02: FINAL TX DQS BEFORE TxFIFO CHECK = 201
N6.C0.S03: FINAL TX DQS BEFORE TxFIFO CHECK = 201
N6.C0.S04: FINAL TX DQS BEFORE TxFIFO CHECK = 246
N6.C0.S05: FINAL TX DQS BEFORE TxFIFO CHECK = 237
N6.C0.S06: FINAL TX DQS BEFORE TxFIFO CHECK = 245
N6.C0.S07: FINAL TX DQS BEFORE TxFIFO CHECK = 243
N6.C0.S08: FINAL TX DQS BEFORE TxFIFO CHECK = 216

END - VMSE Train Read                  Time         3907 ms

END - VMSE Train Write Leveling        Time         284 ms

START - VMSE Train Level Tx DQS DCC

START - VMSE Train Write
N4.C0: VmseLevelTxDqsDccExecute: MXB DQS DCC Finished Successfully
N4.C0.S01: VmseAdjustDqsVoc: retrain DQS DCC.
N4.C0.S01:    dcc1_dqs = 0x0, preampvoc = 0x7
N4.C0: VmseLevelTxDqsDccExecute: MXB DQS DCC Finished Successfully

END - VMSE Train Level Tx DQS DCC      Time         34 ms

START - VMSE Train Write Leveling
N4.C0: VmseWriteLevelFineSetup: Set push to data delay = 6, Global TX DQS delay = 0
N4.C0: VmseRLWLFineSearchAll: Entry
N4.C0: FINE WRITE LEVEL DELAY
N4.C0.S00: TX DQS DELAY = 105
N4.C0.S01: TX DQS DELAY = 111
N4.C0.S02: TX DQS DELAY = 92
N4.C0.S03: TX DQS DELAY = 88
N4.C0.S04: TX DQS DELAY = 144
N4.C0.S05: TX DQS DELAY = 135
N4.C0.S06: TX DQS DELAY = 138
N4.C0.S07: TX DQS DELAY = 132
N4.C0.S08: TX DQS DELAY = 108
N4.C0: VmseWriteLevelCoarseSetup: Set push to data delay = 6, Global TX DQS delay = 0
N4.C0: VmseWriteLevelCoarseExecute
N4.C0: VmseWLCoarseUpdatePD: New push to data delay = 6, New global TxDQS delay = 1
N4.C0: VmseWLCoarseUpdatePD: New push to data delay = 7, New global TxDQS delay = 0
N4.C0: VmseWLCoarseUpdatePD: New push to data delay = 7, New global TxDQS delay = 1
N4.C0: VmseWLCoarseUpdatePD: New push to data delay = 8, New global TxDQS delay = 0
N4.C0: VmseWLCoarseUpdatePD: New push to data delay = 8, New global TxDQS delay = 1
N4.C0.S00: FINAL TX DQS BEFORE TxFIFO CHECK = 201
N4.C0.S01: FINAL TX DQS BEFORE TxFIFO CHECK = 210
N4.C0.S02: FINAL TX DQS BEFORE TxFIFO CHECK = 190
N4.C0.S03: FINAL TX DQS BEFORE TxFIFO CHECK = 187
N4.C0.S04: FINAL TX DQS BEFORE TxFIFO CHECK = 242
N4.C0.S05: FINAL TX DQS BEFORE TxFIFO CHECK = 232
N4.C0.S06: FINAL TX DQS BEFORE TxFIFO CHECK = 236
N4.C0.S07: FINAL TX DQS BEFORE TxFIFO CHECK = 230
N4.C0.S08: FINAL TX DQS BEFORE TxFIFO CHECK = 206

END - VMSE Train Write Leveling        Time         155 ms

START - VMSE Train Write
Entry 0 - TrainDcc - DCCStart: 30, VocStart: 9, DCCFinal: 30, VocFinal: 9
Entry 1 - TrainDcc - DCCStart: 58, VocStart: 12, DCCFinal: 58, VocFinal: 12
Entry 2 - TrainDcc - DCCStart: 27, VocStart: 16, DCCFinal: 27, VocFinal: 16
Entry 3 - TrainDcc - DCCStart: 36, VocStart: 13, DCCFinal: 36, VocFinal: 13
Entry 4 - TrainDcc - DCCStart: 45, VocStart: 8, DCCFinal: 45, VocFinal: 8
Entry 5 - TrainDcc - DCCStart: 32, VocStart: 15, DCCFinal: 32, VocFinal: 15
Entry 6 - TrainDcc - DCCStart: 53, VocStart: 11, DCCFinal: 53, VocFinal: 11
Entry 7 - TrainDcc - DCCStart: 6, VocStart: 16, DCCFinal: 6, VocFinal: 16
Entry 8 - TrainDcc - DCCStart: 39, VocStart: 12, DCCFinal: 39, VocFinal: 12
N2.C0.S00: VmseWriteTraining Final: centerPi = 0x3C, PiEw = 0x29, centerVref = 0x41, vrefHeight = 0x2F
N2.C0.S01: VmseWriteTraining Final: centerPi = 0x3C, PiEw = 0x29, centerVref = 0x3E, vrefHeight = 0x2D
N2.C0.S02: VmseWriteTraining Final: centerPi = 0x3A, PiEw = 0x22, centerVref = 0x3E, vrefHeight = 0x2D
N2.C0.S03: VmseWriteTraining Final: centerPi = 0x39, PiEw = 0x25, centerVref = 0x3F, vrefHeight = 0x2F
N2.C0.S04: VmseWriteTraining Final: centerPi = 0x3E, PiEw = 0x23, centerVref = 0x3E, vrefHeight = 0x29
N2.C0.S05: VmseWriteTraining Final: centerPi = 0x40, PiEw = 0x29, centerVref = 0x3D, vrefHeight = 0x2F
N2.C0.S06: VmseWriteTraining Final: centerPi = 0x3F, PiEw = 0x26, centerVref = 0x3B, vrefHeight = 0x2B
N2.C0.S07: VmseWriteTraining Final: centerPi = 0x3B, PiEw = 0x22, centerVref = 0x3D, vrefHeight = 0x27
N2.C0.S08: VmseWriteTraining Final: centerPi = 0x39, PiEw = 0x28, centerVref = 0x3F, vrefHeight = 0x2F
N2.C0.S09: VmseWriteTraining Final: centerPi = 0x3A, PiEw = 0x29, centerVref = 0x3D, vrefHeight = 0x2F
N2.C0.S10: VmseWriteTraining Final: centerPi = 0x37, PiEw = 0x26, centerVref = 0x3E, vrefHeight = 0x2F
N2.C0.S11: VmseWriteTraining Final: centerPi = 0x35, PiEw = 0x2B, centerVref = 0x43, vrefHeight = 0x2F
N2.C0.S12: VmseWriteTraining Final: centerPi = 0x3D, PiEw = 0x29, centerVref = 0x3E, vrefHeight = 0x2D
N2.C0.S13: VmseWriteTraining Final: centerPi = 0x3B, PiEw = 0x28, centerVref = 0x3D, vrefHeight = 0x2B
N2.C0.S14: VmseWriteTraining Final: centerPi = 0x3E, PiEw = 0x24, centerVref = 0x3D, vrefHeight = 0x31
Entry 0 - TrainDcc - DCCStart: 11, VocStart: 12, DCCFinal: 43, VocFinal: 12
N2.C0.S15: VmseWriteTraining Final: centerPi = 0x3C, PiEw = 0x2A, centerVref = 0x42, vrefHeight = 0x2F
Entry 1 - TrainDcc - DCCStart: 4, VocStart: 9, DCCFinal: 4, VocFinal: 9
N2.C0.S16: VmseWriteTraining Final: centerPi = 0x3A, PiEw = 0x21, centerVref = 0x40, vrefHeight = 0x23
Entry 2 - TrainDcc - DCCStart: 14, VocStart: 9, DCCFinal: 14, VocFinal: 9
N2.C0.S17: VmseWriteTraining Final: centerPi = 0x3C, PiEw = 0x24, centerVref = 0x3F, vrefHeight = 0x29
Entry 3 - TrainDcc - DCCStart: 19, VocStart: 14, DCCFinal: 19, VocFinal: 14
N2.C0.S18: VmseWriteTraining Final: centerPi = 0x3A, PiEw = 0x23, centerVref = 0x3F, vrefHeight = 0x2B
Entry 4 - TrainDcc - DCCStart: 1, VocStart: 17, DCCFinal: 1, VocFinal: 25
N2.C0.S19: VmseWriteTraining Final: centerPi = 0x37, PiEw = 0x29, centerVref = 0x3E, vrefHeight = 0x29
Entry 5 - TrainDcc - DCCStart: 21, VocStart: 13, DCCFinal: 21, VocFinal: 13
N2.C0.S20: VmseWriteTraining Final: centerPi = 0x40, PiEw = 0x26, centerVref = 0x3E, vrefHeight = 0x29
Entry 6 - TrainDcc - DCCStart: 18, VocStart: 14, DCCFinal: 18, VocFinal: 15
N2.C0.S21: VmseWriteTraining Final: centerPi = 0x40, PiEw = 0x27, centerVref = 0x3C, vrefHeight = 0x29
Entry 7 - TrainDcc - DCCStart: 15, VocStart: 9, DCCFinal: 15, VocFinal: 9
N2.C0.S22: VmseWriteTraining Final: centerPi = 0x3D, PiEw = 0x24, centerVref = 0x40, vrefHeight = 0x2B
Entry 0 - TrainDcc - DCCStart: 26, VocStart: 16, DCCFinal: 26, VocFinal: 16
Entry 8 - TrainDcc - DCCStart: 4, VocStart: 11, DCCFinal: 4, VocFinal: 11
N2.C0.S23: VmseWriteTraining Final: centerPi = 0x40, PiEw = 0x2B, centerVref = 0x43, vrefHeight = 0x2B
Entry 1 - TrainDcc - DCCStart: 20, VocStart: 11, DCCFinal: 20, VocFinal: 11
N2.C0.S24: VmseWriteTraining Final: centerPi = 0x3A, PiEw = 0x2B, centerVref = 0x41, vrefHeight = 0x2B
Entry 2 - TrainDcc - DCCStart: 11, VocStart: 13, DCCFinal: 11, VocFinal: 13
N2.C0.S25: VmseWriteTraining Final: centerPi = 0x3A, PiEw = 0x28, centerVref = 0x43, vrefHeight = 0x2D
Entry 3 - TrainDcc - DCCStart: 11, VocStart: 9, DCCFinal: 11, VocFinal: 9
N2.C0.S26: VmseWriteTraining Final: centerPi = 0x38, PiEw = 0x26, centerVref = 0x40, vrefHeight = 0x2D
Entry 4 - TrainDcc - DCCStart: 27, VocStart: 12, DCCFinal: 27, VocFinal: 12
N2.C0.S27: VmseWriteTraining Final: centerPi = 0x3A, PiEw = 0x28, centerVref = 0x3B, vrefHeight = 0x2F
Entry 5 - TrainDcc - DCCStart: 11, VocStart: 13, DCCFinal: 11, VocFinal: 13
N2.C0.S28: VmseWriteTraining Final: centerPi = 0x3C, PiEw = 0x29, centerVref = 0x3B, vrefHeight = 0x2B
Entry 6 - TrainDcc - DCCStart: 8, VocStart: 12, DCCFinal: 8, VocFinal: 17
N2.C0.S29: VmseWriteTraining Final: centerPi = 0x3B, PiEw = 0x24, centerVref = 0x3F, vrefHeight = 0x29
Entry 7 - TrainDcc - DCCStart: 12, VocStart: 17, DCCFinal: 12, VocFinal: 17
N2.C0.S30: VmseWriteTraining Final: centerPi = 0x3D, PiEw = 0x25, centerVref = 0x3B, vrefHeight = 0x2B
Entry 8 - TrainDcc - DCCStart: 11, VocStart: 13, DCCFinal: 11, VocFinal: 13
N2.C0.S31: VmseWriteTraining Final: centerPi = 0x3A, PiEw = 0x2A, centerVref = 0x43, vrefHeight = 0x29
N2.C0.S32: VmseWriteTraining Final: centerPi = 0x39, PiEw = 0x2B, centerVref = 0x40, vrefHeight = 0x31
N2.C0.S33: VmseWriteTraining Final: centerPi = 0x3C, PiEw = 0x27, centerVref = 0x39, vrefHeight = 0x33
N2.C0.S34: VmseWriteTraining Final: centerPi = 0x36, PiEw = 0x2A, centerVref = 0x42, vrefHeight = 0x31
N2.C0.S35: VmseWriteTraining Final: centerPi = 0x39, PiEw = 0x2C, centerVref = 0x36, vrefHeight = 0x33
N2.C0.S36: VmseWriteTraining Final: centerPi = 0x3C, PiEw = 0x29, centerVref = 0x3E, vrefHeight = 0x31
Entry 0 - TrainDcc - DCCStart: 27, VocStart: 14, DCCFinal: 27, VocFinal: 14
N2.C0.S37: VmseWriteTraining Final: centerPi = 0x3E, PiEw = 0x27, centerVref = 0x37, vrefHeight = 0x2F
Entry 1 - TrainDcc - DCCStart: 18, VocStart: 7, DCCFinal: 18, VocFinal: 7
N2.C0.S38: VmseWriteTraining Final: centerPi = 0x39, PiEw = 0x27, centerVref = 0x3F, vrefHeight = 0x31
Entry 2 - TrainDcc - DCCStart: 32, VocStart: 14, DCCFinal: 40, VocFinal: 14
N2.C0.S39: VmseWriteTraining Final: centerPi = 0x3C, PiEw = 0x2A, centerVref = 0x3C, vrefHeight = 0x31
Entry 3 - TrainDcc - DCCStart: 3, VocStart: 18, DCCFinal: 3, VocFinal: 18
N0.C0.S00: VmseWriteTraining Final: centerPi = 0x39, PiEw = 0x2A, centerVref = 0x41, vrefHeight = 0x28
N2.C0.S40: VmseWriteTraining Final: centerPi = 0x39, PiEw = 0x2C, centerVref = 0x3E, vrefHeight = 0x2D
Entry 4 - TrainDcc - DCCStart: 31, VocStart: 12, DCCFinal: 31, VocFinal: 12
N0.C0.S01: VmseWriteTraining Final: centerPi = 0x39, PiEw = 0x28, centerVref = 0x3D, vrefHeight = 0x26
N2.C0.S41: VmseWriteTraining Final: centerPi = 0x3B, PiEw = 0x28, centerVref = 0x3D, vrefHeight = 0x2D
Entry 5 - TrainDcc - DCCStart: 15, VocStart: 13, DCCFinal: 15, VocFinal: 13
N0.C0.S02: VmseWriteTraining Final: centerPi = 0x38, PiEw = 0x28, centerVref = 0x41, vrefHeight = 0x26
N2.C0.S42: VmseWriteTraining Final: centerPi = 0x35, PiEw = 0x29, centerVref = 0x3D, vrefHeight = 0x2B
Entry 6 - TrainDcc - DCCStart: 17, VocStart: 9, DCCFinal: 17, VocFinal: 11
N0.C0.S03: VmseWriteTraining Final: centerPi = 0x39, PiEw = 0x25, centerVref = 0x41, vrefHeight = 0x28
N2.C0.S43: VmseWriteTraining Final: centerPi = 0x37, PiEw = 0x2A, centerVref = 0x3F, vrefHeight = 0x2F
Entry 7 - TrainDcc - DCCStart: 11, VocStart: 12, DCCFinal: 11, VocFinal: 12
N0.C0.S04: VmseWriteTraining Final: centerPi = 0x3D, PiEw = 0x22, centerVref = 0x3E, vrefHeight = 0x26
N2.C0.S44: VmseWriteTraining Final: centerPi = 0x3C, PiEw = 0x2D, centerVref = 0x41, vrefHeight = 0x2D
Entry 8 - TrainDcc - DCCStart: 34, VocStart: 16, DCCFinal: 34, VocFinal: 16
N0.C0.S05: VmseWriteTraining Final: centerPi = 0x3B, PiEw = 0x25, centerVref = 0x44, vrefHeight = 0x26
N2.C0.S45: VmseWriteTraining Final: centerPi = 0x40, PiEw = 0x26, centerVref = 0x3F, vrefHeight = 0x2F
N6.C0.S00: VmseWriteTraining Final: centerPi = 0x3B, PiEw = 0x2B, centerVref = 0x41, vrefHeight = 0x2C
N0.C0.S06: VmseWriteTraining Final: centerPi = 0x3C, PiEw = 0x25, centerVref = 0x41, vrefHeight = 0x26
N2.C0.S46: VmseWriteTraining Final: centerPi = 0x3C, PiEw = 0x27, centerVref = 0x3D, vrefHeight = 0x2D
N6.C0.S01: VmseWriteTraining Final: centerPi = 0x3A, PiEw = 0x2A, centerVref = 0x41, vrefHeight = 0x2E
N0.C0.S07: VmseWriteTraining Final: centerPi = 0x3C, PiEw = 0x23, centerVref = 0x3B, vrefHeight = 0x24
N2.C0.S47: VmseWriteTraining Final: centerPi = 0x3B, PiEw = 0x2A, centerVref = 0x41, vrefHeight = 0x2B
N6.C0.S02: VmseWriteTraining Final: centerPi = 0x3A, PiEw = 0x23, centerVref = 0x3E, vrefHeight = 0x2C
N0.C0.S08: VmseWriteTraining Final: centerPi = 0x3E, PiEw = 0x24, centerVref = 0x40, vrefHeight = 0x28
N2.C0.S48: VmseWriteTraining Final: centerPi = 0x39, PiEw = 0x27, centerVref = 0x3B, vrefHeight = 0x2D
N6.C0.S03: VmseWriteTraining Final: centerPi = 0x3B, PiEw = 0x27, centerVref = 0x3B, vrefHeight = 0x30
N0.C0.S09: VmseWriteTraining Final: centerPi = 0x3C, PiEw = 0x23, centerVref = 0x40, vrefHeight = 0x28
N2.C0.S49: VmseWriteTraining Final: centerPi = 0x3A, PiEw = 0x2B, centerVref = 0x38, vrefHeight = 0x31
N6.C0.S04: VmseWriteTraining Final: centerPi = 0x40, PiEw = 0x24, centerVref = 0x3C, vrefHeight = 0x2E
N0.C0.S10: VmseWriteTraining Final: centerPi = 0x3A, PiEw = 0x20, centerVref = 0x3F, vrefHeight = 0x28
N2.C0.S50: VmseWriteTraining Final: centerPi = 0x37, PiEw = 0x22, centerVref = 0x3D, vrefHeight = 0x2F
N6.C0.S05: VmseWriteTraining Final: centerPi = 0x3E, PiEw = 0x25, centerVref = 0x3C, vrefHeight = 0x2C
N0.C0.S11: VmseWriteTraining Final: centerPi = 0x3A, PiEw = 0x26, centerVref = 0x43, vrefHeight = 0x2A
N2.C0.S51: VmseWriteTraining Final: centerPi = 0x35, PiEw = 0x29, centerVref = 0x3A, vrefHeight = 0x31
N6.C0.S06: VmseWriteTraining Final: centerPi = 0x3E, PiEw = 0x25, centerVref = 0x3F, vrefHeight = 0x2A
N0.C0.S12: VmseWriteTraining Final: centerPi = 0x40, PiEw = 0x25, centerVref = 0x3C, vrefHeight = 0x26
N2.C0.S52: VmseWriteTraining Final: centerPi = 0x3C, PiEw = 0x27, centerVref = 0x3B, vrefHeight = 0x2D
N6.C0.S07: VmseWriteTraining Final: centerPi = 0x3D, PiEw = 0x22, centerVref = 0x3D, vrefHeight = 0x28
N0.C0.S13: VmseWriteTraining Final: centerPi = 0x3F, PiEw = 0x23, centerVref = 0x46, vrefHeight = 0x26
N2.C0.S53: VmseWriteTraining Final: centerPi = 0x3B, PiEw = 0x27, centerVref = 0x40, vrefHeight = 0x2B
N6.C0.S08: VmseWriteTraining Final: centerPi = 0x3A, PiEw = 0x28, centerVref = 0x43, vrefHeight = 0x2C
N0.C0.S14: VmseWriteTraining Final: centerPi = 0x3F, PiEw = 0x24, centerVref = 0x3E, vrefHeight = 0x26
N2.C0.S54: VmseWriteTraining Final: centerPi = 0x3C, PiEw = 0x28, centerVref = 0x3E, vrefHeight = 0x31
N4.C0.S00: VmseWriteTraining Final: centerPi = 0x3A, PiEw = 0x2A, centerVref = 0x47, vrefHeight = 0x28
N6.C0.S09: VmseWriteTraining Final: centerPi = 0x3A, PiEw = 0x29, centerVref = 0x44, vrefHeight = 0x2C
N0.C0.S15: VmseWriteTraining Final: centerPi = 0x40, PiEw = 0x27, centerVref = 0x3B, vrefHeight = 0x28
N2.C0.S55: VmseWriteTraining Final: centerPi = 0x3B, PiEw = 0x28, centerVref = 0x3F, vrefHeight = 0x2D
N4.C0.S01: VmseWriteTraining Final: centerPi = 0x3A, PiEw = 0x27, centerVref = 0x3E, vrefHeight = 0x28
N6.C0.S10: VmseWriteTraining Final: centerPi = 0x39, PiEw = 0x26, centerVref = 0x3B, vrefHeight = 0x30
N0.C0.S16: VmseWriteTraining Final: centerPi = 0x3B, PiEw = 0x29, centerVref = 0x45, vrefHeight = 0x22
N2.C0.S56: VmseWriteTraining Final: centerPi = 0x3F, PiEw = 0x2A, centerVref = 0x3D, vrefHeight = 0x2F
N4.C0.S02: VmseWriteTraining Final: centerPi = 0x3A, PiEw = 0x26, centerVref = 0x42, vrefHeight = 0x26
N6.C0.S11: VmseWriteTraining Final: centerPi = 0x3B, PiEw = 0x29, centerVref = 0x3D, vrefHeight = 0x2E
N0.C0.S17: VmseWriteTraining Final: centerPi = 0x3D, PiEw = 0x22, centerVref = 0x3F, vrefHeight = 0x24
N2.C0.S57: VmseWriteTraining Final: centerPi = 0x3E, PiEw = 0x2D, centerVref = 0x3F, vrefHeight = 0x2F
N4.C0.S03: VmseWriteTraining Final: centerPi = 0x39, PiEw = 0x23, centerVref = 0x41, vrefHeight = 0x2C
N6.C0.S12: VmseWriteTraining Final: centerPi = 0x3E, PiEw = 0x27, centerVref = 0x43, vrefHeight = 0x2E
N0.C0.S18: VmseWriteTraining Final: centerPi = 0x3B, PiEw = 0x22, centerVref = 0x3F, vrefHeight = 0x26
N2.C0.S58: VmseWriteTraining Final: centerPi = 0x3C, PiEw = 0x28, centerVref = 0x3F, vrefHeight = 0x2B
N4.C0.S04: VmseWriteTraining Final: centerPi = 0x3C, PiEw = 0x23, centerVref = 0x3F, vrefHeight = 0x24
N6.C0.S13: VmseWriteTraining Final: centerPi = 0x3E, PiEw = 0x27, centerVref = 0x3E, vrefHeight = 0x2E
N0.C0.S19: VmseWriteTraining Final: centerPi = 0x38, PiEw = 0x27, centerVref = 0x45, vrefHeight = 0x26
N2.C0.S59: VmseWriteTraining Final: centerPi = 0x3A, PiEw = 0x2A, centerVref = 0x3D, vrefHeight = 0x2B
N4.C0.S05: VmseWriteTraining Final: centerPi = 0x3E, PiEw = 0x2A, centerVref = 0x42, vrefHeight = 0x26
N6.C0.S14: VmseWriteTraining Final: centerPi = 0x3B, PiEw = 0x26, centerVref = 0x3F, vrefHeight = 0x2E
N0.C0.S20: VmseWriteTraining Final: centerPi = 0x42, PiEw = 0x24, centerVref = 0x3D, vrefHeight = 0x28
N2.C0.S60: VmseWriteTraining Final: centerPi = 0x44, PiEw = 0x29, centerVref = 0x3B, vrefHeight = 0x31
N4.C0.S06: VmseWriteTraining Final: centerPi = 0x3C, PiEw = 0x26, centerVref = 0x42, vrefHeight = 0x28
N6.C0.S15: VmseWriteTraining Final: centerPi = 0x41, PiEw = 0x26, centerVref = 0x3A, vrefHeight = 0x30
N0.C0.S21: VmseWriteTraining Final: centerPi = 0x40, PiEw = 0x24, centerVref = 0x44, vrefHeight = 0x22
N2.C0.S61: VmseWriteTraining Final: centerPi = 0x41, PiEw = 0x26, centerVref = 0x43, vrefHeight = 0x2B
N4.C0.S07: VmseWriteTraining Final: centerPi = 0x3B, PiEw = 0x26, centerVref = 0x3F, vrefHeight = 0x24
N6.C0.S16: VmseWriteTraining Final: centerPi = 0x3C, PiEw = 0x2A, centerVref = 0x3E, vrefHeight = 0x26
N0.C0.S22: VmseWriteTraining Final: centerPi = 0x3B, PiEw = 0x22, centerVref = 0x40, vrefHeight = 0x22
N2.C0.S62: VmseWriteTraining Final: centerPi = 0x42, PiEw = 0x28, centerVref = 0x3D, vrefHeight = 0x2D
N4.C0.S08: VmseWriteTraining Final: centerPi = 0x3E, PiEw = 0x20, centerVref = 0x3D, vrefHeight = 0x28
N6.C0.S17: VmseWriteTraining Final: centerPi = 0x3D, PiEw = 0x24, centerVref = 0x41, vrefHeight = 0x26
N0.C0.S23: VmseWriteTraining Final: centerPi = 0x3E, PiEw = 0x24, centerVref = 0x40, vrefHeight = 0x26
N2.C0.S63: VmseWriteTraining Final: centerPi = 0x40, PiEw = 0x2B, centerVref = 0x40, vrefHeight = 0x2B
N4.C0.S09: VmseWriteTraining Final: centerPi = 0x38, PiEw = 0x2B, centerVref = 0x41, vrefHeight = 0x28
N6.C0.S18: VmseWriteTraining Final: centerPi = 0x39, PiEw = 0x24, centerVref = 0x3C, vrefHeight = 0x28
N0.C0.S24: VmseWriteTraining Final: centerPi = 0x3A, PiEw = 0x27, centerVref = 0x40, vrefHeight = 0x22
N2.C0.S64: VmseWriteTraining Final: centerPi = 0x3A, PiEw = 0x2B, centerVref = 0x44, vrefHeight = 0x2D
N4.C0.S10: VmseWriteTraining Final: centerPi = 0x36, PiEw = 0x25, centerVref = 0x3E, vrefHeight = 0x2A
N6.C0.S19: VmseWriteTraining Final: centerPi = 0x39, PiEw = 0x29, centerVref = 0x42, vrefHeight = 0x2C
N0.C0.S25: VmseWriteTraining Final: centerPi = 0x3A, PiEw = 0x26, centerVref = 0x3E, vrefHeight = 0x26
N2.C0.S65: VmseWriteTraining Final: centerPi = 0x3A, PiEw = 0x2A, centerVref = 0x3F, vrefHeight = 0x2F
N4.C0.S11: VmseWriteTraining Final: centerPi = 0x3B, PiEw = 0x24, centerVref = 0x3E, vrefHeight = 0x28
N6.C0.S20: VmseWriteTraining Final: centerPi = 0x40, PiEw = 0x26, centerVref = 0x3D, vrefHeight = 0x28
N0.C0.S26: VmseWriteTraining Final: centerPi = 0x39, PiEw = 0x22, centerVref = 0x3E, vrefHeight = 0x26
N2.C0.S66: VmseWriteTraining Final: centerPi = 0x39, PiEw = 0x23, centerVref = 0x3C, vrefHeight = 0x2D
N4.C0.S12: VmseWriteTraining Final: centerPi = 0x3E, PiEw = 0x26, centerVref = 0x3E, vrefHeight = 0x26
N6.C0.S21: VmseWriteTraining Final: centerPi = 0x41, PiEw = 0x24, centerVref = 0x38, vrefHeight = 0x2A
N0.C0.S27: VmseWriteTraining Final: centerPi = 0x38, PiEw = 0x2B, centerVref = 0x3F, vrefHeight = 0x28
N2.C0.S67: VmseWriteTraining Final: centerPi = 0x3B, PiEw = 0x21, centerVref = 0x3D, vrefHeight = 0x2F
N4.C0.S13: VmseWriteTraining Final: centerPi = 0x3E, PiEw = 0x28, centerVref = 0x41, vrefHeight = 0x28
N6.C0.S22: VmseWriteTraining Final: centerPi = 0x3D, PiEw = 0x24, centerVref = 0x3D, vrefHeight = 0x2A
N0.C0.S28: VmseWriteTraining Final: centerPi = 0x3D, PiEw = 0x29, centerVref = 0x41, vrefHeight = 0x24
N2.C0.S68: VmseWriteTraining Final: centerPi = 0x3D, PiEw = 0x25, centerVref = 0x3E, vrefHeight = 0x2B
N4.C0.S14: VmseWriteTraining Final: centerPi = 0x3C, PiEw = 0x26, centerVref = 0x41, vrefHeight = 0x28
N6.C0.S23: VmseWriteTraining Final: centerPi = 0x3F, PiEw = 0x24, centerVref = 0x3E, vrefHeight = 0x2A
N0.C0.S29: VmseWriteTraining Final: centerPi = 0x3D, PiEw = 0x27, centerVref = 0x40, vrefHeight = 0x22
N2.C0.S69: VmseWriteTraining Final: centerPi = 0x3E, PiEw = 0x28, centerVref = 0x46, vrefHeight = 0x33
N4.C0.S15: VmseWriteTraining Final: centerPi = 0x3D, PiEw = 0x2B, centerVref = 0x43, vrefHeight = 0x28
N6.C0.S24: VmseWriteTraining Final: centerPi = 0x3B, PiEw = 0x2B, centerVref = 0x42, vrefHeight = 0x28
N0.C0.S30: VmseWriteTraining Final: centerPi = 0x3F, PiEw = 0x24, centerVref = 0x40, vrefHeight = 0x24
N2.C0.S70: VmseWriteTraining Final: centerPi = 0x3C, PiEw = 0x23, centerVref = 0x3C, vrefHeight = 0x2B
N4.C0.S16: VmseWriteTraining Final: centerPi = 0x3D, PiEw = 0x25, centerVref = 0x42, vrefHeight = 0x1E
N6.C0.S25: VmseWriteTraining Final: centerPi = 0x39, PiEw = 0x29, centerVref = 0x41, vrefHeight = 0x2A
N0.C0.S31: VmseWriteTraining Final: centerPi = 0x3F, PiEw = 0x2A, centerVref = 0x42, vrefHeight = 0x26
N2.C0.S71: VmseWriteTraining Final: centerPi = 0x3D, PiEw = 0x27, centerVref = 0x3E, vrefHeight = 0x2D
N4.C0.S17: VmseWriteTraining Final: centerPi = 0x3A, PiEw = 0x27, centerVref = 0x3E, vrefHeight = 0x22
N6.C0.S26: VmseWriteTraining Final: centerPi = 0x39, PiEw = 0x20, centerVref = 0x3F, vrefHeight = 0x28
N0.C0.S32: VmseWriteTraining Final: centerPi = 0x3C, PiEw = 0x2A, centerVref = 0x42, vrefHeight = 0x28

END - VMSE Train Write                 Time         3363 ms
N4.C0.S18: VmseWriteTraining Final: centerPi = 0x38, PiEw = 0x21, centerVref = 0x41, vrefHeight = 0x24
N6.C0.S27: VmseWriteTraining Final: centerPi = 0x36, PiEw = 0x2C, centerVref = 0x41, vrefHeight = 0x2E
N0.C0.S33: VmseWriteTraining Final: centerPi = 0x41, PiEw = 0x27, centerVref = 0x3B, vrefHeight = 0x2C
N2: 
Total VMSE trainings latency = 15894 ms
N4.C0.S19: VmseWriteTraining Final: centerPi = 0x3A, PiEw = 0x26, centerVref = 0x3C, vrefHeight = 0x28
N6.C0.S28: VmseWriteTraining Final: centerPi = 0x3F, PiEw = 0x25, centerVref = 0x3D, vrefHeight = 0x2C
N0.C0.S34: VmseWriteTraining Final: centerPi = 0x3D, PiEw = 0x29, centerVref = 0x43, vrefHeight = 0x2C
N2: CpgcVmseTraining for VMSE1
N4.C0.S20: VmseWriteTraining Final: centerPi = 0x3F, PiEw = 0x25, centerVref = 0x42, vrefHeight = 0x26
N6.C0.S29: VmseWriteTraining Final: centerPi = 0x3C, PiEw = 0x25, centerVref = 0x3F, vrefHeight = 0x2A
N0.C0.S35: VmseWriteTraining Final: centerPi = 0x39, PiEw = 0x28, centerVref = 0x3A, vrefHeight = 0x2A
N2: Initialize VMSE Channels
N4.C0.S21: VmseWriteTraining Final: centerPi = 0x3C, PiEw = 0x27, centerVref = 0x44, vrefHeight = 0x20
N6.C0.S30: VmseWriteTraining Final: centerPi = 0x3D, PiEw = 0x22, centerVref = 0x3C, vrefHeight = 0x2C
N0.C0.S36: VmseWriteTraining Final: centerPi = 0x42, PiEw = 0x27, centerVref = 0x3E, vrefHeight = 0x2A

START - VMSE Detect DC
N4.C0.S22: VmseWriteTraining Final: centerPi = 0x3F, PiEw = 0x1F, centerVref = 0x3E, vrefHeight = 0x22
N6.C0.S31: VmseWriteTraining Final: centerPi = 0x3E, PiEw = 0x29, centerVref = 0x3F, vrefHeight = 0x2C
N0.C0.S37: VmseWriteTraining Final: centerPi = 0x41, PiEw = 0x28, centerVref = 0x3F, vrefHeight = 0x26
N2: HsxVmseCompInit
N4.C0.S23: VmseWriteTraining Final: centerPi = 0x3D, PiEw = 0x28, centerVref = 0x3F, vrefHeight = 0x24
N6.C0.S32: VmseWriteTraining Final: centerPi = 0x3A, PiEw = 0x29, centerVref = 0x3F, vrefHeight = 0x30
N0.C0.S38: VmseWriteTraining Final: centerPi = 0x3F, PiEw = 0x27, centerVref = 0x3C, vrefHeight = 0x2A
N2.C1: Skip DC Detect check for CMD results
N4.C0.S24: VmseWriteTraining Final: centerPi = 0x3F, PiEw = 0x22, centerVref = 0x40, vrefHeight = 0x22
N6.C0.S33: VmseWriteTraining Final: centerPi = 0x37, PiEw = 0x29, centerVref = 0x40, vrefHeight = 0x2C
N0.C0.S39: VmseWriteTraining Final: centerPi = 0x42, PiEw = 0x26, centerVref = 0x38, vrefHeight = 0x2A
N2.C1: Skip DC Detect check for CMD results
N4.C0.S25: VmseWriteTraining Final: centerPi = 0x3D, PiEw = 0x25, centerVref = 0x40, vrefHeight = 0x26
N6.C0.S34: VmseWriteTraining Final: centerPi = 0x38, PiEw = 0x29, centerVref = 0x40, vrefHeight = 0x30
N0.C0.S40: VmseWriteTraining Final: centerPi = 0x37, PiEw = 0x2B, centerVref = 0x42, vrefHeight = 0x26
N2: HsxVmseCompInit
N4.C0.S26: VmseWriteTraining Final: centerPi = 0x3C, PiEw = 0x19, centerVref = 0x41, vrefHeight = 0x26
N6.C0.S35: VmseWriteTraining Final: centerPi = 0x36, PiEw = 0x2C, centerVref = 0x40, vrefHeight = 0x30
N0.C0.S41: VmseWriteTraining Final: centerPi = 0x3C, PiEw = 0x27, centerVref = 0x3C, vrefHeight = 0x2A
N2.C1: VmseDetectDC: SUCCESS
N4.C0.S27: VmseWriteTraining Final: centerPi = 0x3A, PiEw = 0x27, centerVref = 0x3D, vrefHeight = 0x28
N6.C0.S36: VmseWriteTraining Final: centerPi = 0x3C, PiEw = 0x28, centerVref = 0x3C, vrefHeight = 0x2E
N0.C0.S42: VmseWriteTraining Final: centerPi = 0x3A, PiEw = 0x27, centerVref = 0x3F, vrefHeight = 0x28
N2.C1: VmseDetectClock
N4.C0.S28: VmseWriteTraining Final: centerPi = 0x40, PiEw = 0x20, centerVref = 0x39, vrefHeight = 0x22
N6.C0.S37: VmseWriteTraining Final: centerPi = 0x3E, PiEw = 0x27, centerVref = 0x3C, vrefHeight = 0x2E
N0.C0.S43: VmseWriteTraining Final: centerPi = 0x38, PiEw = 0x24, centerVref = 0x3F, vrefHeight = 0x2A
N4.C0.S29: VmseWriteTraining Final: centerPi = 0x40, PiEw = 0x22, centerVref = 0x3F, vrefHeight = 0x24
N6.C0.S38: VmseWriteTraining Final: centerPi = 0x39, PiEw = 0x26, centerVref = 0x3E, vrefHeight = 0x30
N0.C0.S44: VmseWriteTraining Final: centerPi = 0x3D, PiEw = 0x27, centerVref = 0x3D, vrefHeight = 0x28
N4.C0.S30: VmseWriteTraining Final: centerPi = 0x3F, PiEw = 0x1F, centerVref = 0x3D, vrefHeight = 0x24
N6.C0.S39: VmseWriteTraining Final: centerPi = 0x3D, PiEw = 0x29, centerVref = 0x3B, vrefHeight = 0x2E
N0.C0.S45: VmseWriteTraining Final: centerPi = 0x3F, PiEw = 0x27, centerVref = 0x3F, vrefHeight = 0x28
N4.C0.S31: VmseWriteTraining Final: centerPi = 0x41, PiEw = 0x27, centerVref = 0x3E, vrefHeight = 0x26
N6.C0.S40: VmseWriteTraining Final: centerPi = 0x3A, PiEw = 0x2A, centerVref = 0x3C, vrefHeight = 0x2E
N0.C0.S46: VmseWriteTraining Final: centerPi = 0x3C, PiEw = 0x24, centerVref = 0x3E, vrefHeight = 0x26
N4.C0.S32: VmseWriteTraining Final: centerPi = 0x3D, PiEw = 0x24, centerVref = 0x44, vrefHeight = 0x2A
N6.C0.S41: VmseWriteTraining Final: centerPi = 0x3B, PiEw = 0x2A, centerVref = 0x40, vrefHeight = 0x2E
N0.C0.S47: VmseWriteTraining Final: centerPi = 0x3C, PiEw = 0x28, centerVref = 0x3E, vrefHeight = 0x28
N4.C0.S33: VmseWriteTraining Final: centerPi = 0x39, PiEw = 0x23, centerVref = 0x40, vrefHeight = 0x2A
N6.C0.S42: VmseWriteTraining Final: centerPi = 0x3E, PiEw = 0x23, centerVref = 0x3B, vrefHeight = 0x30
N0.C0.S48: VmseWriteTraining Final: centerPi = 0x3A, PiEw = 0x24, centerVref = 0x41, vrefHeight = 0x24
N2.C1: VmseDetectClock: SUCCESS
N4.C0.S34: VmseWriteTraining Final: centerPi = 0x39, PiEw = 0x26, centerVref = 0x40, vrefHeight = 0x2E
N6.C0.S43: VmseWriteTraining Final: centerPi = 0x3A, PiEw = 0x28, centerVref = 0x3A, vrefHeight = 0x27
N0.C0.S49: VmseWriteTraining Final: centerPi = 0x3A, PiEw = 0x25, centerVref = 0x42, vrefHeight = 0x2A

END - VMSE Detect DC                   Time         417 ms
N4.C0.S35: VmseWriteTraining Final: centerPi = 0x35, PiEw = 0x24, centerVref = 0x41, vrefHeight = 0x2A
N6.C0.S44: VmseWriteTraining Final: centerPi = 0x40, PiEw = 0x26, centerVref = 0x3F, vrefHeight = 0x2C
N0.C0.S50: VmseWriteTraining Final: centerPi = 0x39, PiEw = 0x24, centerVref = 0x3A, vrefHeight = 0x26

START - MXB Clock Train
N4.C0.S36: VmseWriteTraining Final: centerPi = 0x3F, PiEw = 0x21, centerVref = 0x3B, vrefHeight = 0x28
N6.C0.S45: VmseWriteTraining Final: centerPi = 0x40, PiEw = 0x24, centerVref = 0x3D, vrefHeight = 0x2C
N0.C0.S51: VmseWriteTraining Final: centerPi = 0x36, PiEw = 0x28, centerVref = 0x40, vrefHeight = 0x26
N4.C0.S37: VmseWriteTraining Final: centerPi = 0x3A, PiEw = 0x22, centerVref = 0x41, vrefHeight = 0x20
N6.C0.S46: VmseWriteTraining Final: centerPi = 0x3D, PiEw = 0x25, centerVref = 0x39, vrefHeight = 0x2C
N0.C0.S52: VmseWriteTraining Final: centerPi = 0x3D, PiEw = 0x22, centerVref = 0x3D, vrefHeight = 0x24
N4.C0.S38: VmseWriteTraining Final: centerPi = 0x3A, PiEw = 0x23, centerVref = 0x3D, vrefHeight = 0x28
N6.C0.S47: VmseWriteTraining Final: centerPi = 0x3C, PiEw = 0x25, centerVref = 0x3B, vrefHeight = 0x2E
N0.C0.S53: VmseWriteTraining Final: centerPi = 0x3F, PiEw = 0x25, centerVref = 0x3C, vrefHeight = 0x26
N2.C2: VmseRefVckResync: ddrFreq = 0x2, VMSE_MODE_2_1 = 1, VMSE_PREAMBLE_2UI = 0
N4.C0.S39: VmseWriteTraining Final: centerPi = 0x3D, PiEw = 0x29, centerVref = 0x3F, vrefHeight = 0x2C
N6.C0.S48: VmseWriteTraining Final: centerPi = 0x3A, PiEw = 0x23, centerVref = 0x3E, vrefHeight = 0x28
N0.C0.S54: VmseWriteTraining Final: centerPi = 0x3C, PiEw = 0x22, centerVref = 0x41, vrefHeight = 0x24
N2.C2: VmseRefVckResync: VLINKFREQNXT set to: 0x20F940A
N4.C0.S40: VmseWriteTraining Final: centerPi = 0x38, PiEw = 0x28, centerVref = 0x44, vrefHeight = 0x24
N6.C0.S49: VmseWriteTraining Final: centerPi = 0x3E, PiEw = 0x29, centerVref = 0x39, vrefHeight = 0x30
N0.C0.S55: VmseWriteTraining Final: centerPi = 0x3E, PiEw = 0x24, centerVref = 0x42, vrefHeight = 0x26
N2.C1: VmseTrainClockAlign: JCK clkadjcnt =2
N4.C0.S41: VmseWriteTraining Final: centerPi = 0x3D, PiEw = 0x24, centerVref = 0x38, vrefHeight = 0x2C
N6.C0.S50: VmseWriteTraining Final: centerPi = 0x3A, PiEw = 0x22, centerVref = 0x40, vrefHeight = 0x2A
N0.C0.S56: VmseWriteTraining Final: centerPi = 0x3E, PiEw = 0x28, centerVref = 0x43, vrefHeight = 0x24

END - MXB Clock Train                  Time         189 ms
N4.C0.S42: VmseWriteTraining Final: centerPi = 0x3C, PiEw = 0x25, centerVref = 0x41, vrefHeight = 0x2A
N6.C0.S51: VmseWriteTraining Final: centerPi = 0x37, PiEw = 0x24, centerVref = 0x3C, vrefHeight = 0x2A
N0.C0.S57: VmseWriteTraining Final: centerPi = 0x3F, PiEw = 0x29, centerVref = 0x40, vrefHeight = 0x2A

START - VMSE Train Command
N4.C0.S43: VmseWriteTraining Final: centerPi = 0x38, PiEw = 0x27, centerVref = 0x3C, vrefHeight = 0x28
N6.C0.S52: VmseWriteTraining Final: centerPi = 0x40, PiEw = 0x26, centerVref = 0x39, vrefHeight = 0x2C
N0.C0.S58: VmseWriteTraining Final: centerPi = 0x3C, PiEw = 0x24, centerVref = 0x38, vrefHeight = 0x28
N2.C1.B00: HsxCtlXoverInit: invertPiClk = 0x0, RankUsed = 0xFFF, Training = 0x38FFF25
N4.C0.S44: VmseWriteTraining Final: centerPi = 0x39, PiEw = 0x27, centerVref = 0x40, vrefHeight = 0x22
N6.C0.S53: VmseWriteTraining Final: centerPi = 0x40, PiEw = 0x28, centerVref = 0x3A, vrefHeight = 0x2E
N0.C0.S59: VmseWriteTraining Final: centerPi = 0x3A, PiEw = 0x27, centerVref = 0x3D, vrefHeight = 0x28
N2.C1.B01: HsxCtlXoverInit: invertPiClk = 0x0, RankUsed = 0xFFF, Training = 0x38FFF02
N4.C0.S45: VmseWriteTraining Final: centerPi = 0x40, PiEw = 0x24, centerVref = 0x42, vrefHeight = 0x28
N6.C0.S54: VmseWriteTraining Final: centerPi = 0x3F, PiEw = 0x26, centerVref = 0x39, vrefHeight = 0x2C
N0.C0.S60: VmseWriteTraining Final: centerPi = 0x42, PiEw = 0x27, centerVref = 0x42, vrefHeight = 0x28
N4.C0.S46: VmseWriteTraining Final: centerPi = 0x3B, PiEw = 0x27, centerVref = 0x3A, vrefHeight = 0x26
N6.C0.S55: VmseWriteTraining Final: centerPi = 0x3D, PiEw = 0x27, centerVref = 0x3D, vrefHeight = 0x2A
N0.C0.S61: VmseWriteTraining Final: centerPi = 0x41, PiEw = 0x26, centerVref = 0x3F, vrefHeight = 0x26
N2.C1: VmseTrainCmdFine: vmse link sts = 0x4947
N4.C0.S47: VmseWriteTraining Final: centerPi = 0x3A, PiEw = 0x26, centerVref = 0x3B, vrefHeight = 0x28
N6.C0.S56: VmseWriteTraining Final: centerPi = 0x3F, PiEw = 0x2A, centerVref = 0x3D, vrefHeight = 0x30
N0.C0.S62: VmseWriteTraining Final: centerPi = 0x42, PiEw = 0x25, centerVref = 0x3A, vrefHeight = 0x26
N4.C0.S48: VmseWriteTraining Final: centerPi = 0x3E, PiEw = 0x21, centerVref = 0x3D, vrefHeight = 0x28
N6.C0.S57: VmseWriteTraining Final: centerPi = 0x3E, PiEw = 0x2A, centerVref = 0x3C, vrefHeight = 0x30
N0.C0.S63: VmseWriteTraining Final: centerPi = 0x41, PiEw = 0x28, centerVref = 0x3D, vrefHeight = 0x28
N4.C0.S49: VmseWriteTraining Final: centerPi = 0x39, PiEw = 0x26, centerVref = 0x40, vrefHeight = 0x2A
N6.C0.S58: VmseWriteTraining Final: centerPi = 0x3D, PiEw = 0x26, centerVref = 0x3A, vrefHeight = 0x2E
N0.C0.S64: VmseWriteTraining Final: centerPi = 0x3C, PiEw = 0x25, centerVref = 0x43, vrefHeight = 0x24
N4.C0.S50: VmseWriteTraining Final: centerPi = 0x38, PiEw = 0x23, centerVref = 0x3B, vrefHeight = 0x28
N6.C0.S59: VmseWriteTraining Final: centerPi = 0x3A, PiEw = 0x2C, centerVref = 0x3B, vrefHeight = 0x29
N0.C0.S65: VmseWriteTraining Final: centerPi = 0x3B, PiEw = 0x26, centerVref = 0x42, vrefHeight = 0x26
N4.C0.S51: VmseWriteTraining Final: centerPi = 0x39, PiEw = 0x27, centerVref = 0x3F, vrefHeight = 0x28
N6.C0.S60: VmseWriteTraining Final: centerPi = 0x40, PiEw = 0x28, centerVref = 0x3B, vrefHeight = 0x2E
N0.C0.S66: VmseWriteTraining Final: centerPi = 0x3A, PiEw = 0x1F, centerVref = 0x43, vrefHeight = 0x24
N4.C0.S52: VmseWriteTraining Final: centerPi = 0x3B, PiEw = 0x25, centerVref = 0x3F, vrefHeight = 0x24
N6.C0.S61: VmseWriteTraining Final: centerPi = 0x41, PiEw = 0x24, centerVref = 0x42, vrefHeight = 0x2E
N0.C0.S67: VmseWriteTraining Final: centerPi = 0x3A, PiEw = 0x27, centerVref = 0x41, vrefHeight = 0x28
N4.C0.S53: VmseWriteTraining Final: centerPi = 0x3D, PiEw = 0x28, centerVref = 0x3B, vrefHeight = 0x28
N6.C0.S62: VmseWriteTraining Final: centerPi = 0x41, PiEw = 0x26, centerVref = 0x3D, vrefHeight = 0x2E
N0.C0.S68: VmseWriteTraining Final: centerPi = 0x40, PiEw = 0x24, centerVref = 0x41, vrefHeight = 0x26
N4.C0.S54: VmseWriteTraining Final: centerPi = 0x3B, PiEw = 0x25, centerVref = 0x3E, vrefHeight = 0x22
N6.C0.S63: VmseWriteTraining Final: centerPi = 0x41, PiEw = 0x29, centerVref = 0x40, vrefHeight = 0x30
N0.C0.S69: VmseWriteTraining Final: centerPi = 0x41, PiEw = 0x1E, centerVref = 0x44, vrefHeight = 0x26
N4.C0.S55: VmseWriteTraining Final: centerPi = 0x3B, PiEw = 0x27, centerVref = 0x3F, vrefHeight = 0x24
N6.C0.S64: VmseWriteTraining Final: centerPi = 0x3B, PiEw = 0x27, centerVref = 0x3F, vrefHeight = 0x2C
N0.C0.S70: VmseWriteTraining Final: centerPi = 0x3F, PiEw = 0x22, centerVref = 0x3F, vrefHeight = 0x24
N4.C0.S56: VmseWriteTraining Final: centerPi = 0x3D, PiEw = 0x28, centerVref = 0x43, vrefHeight = 0x28
N6.C0.S65: VmseWriteTraining Final: centerPi = 0x3D, PiEw = 0x28, centerVref = 0x3B, vrefHeight = 0x2C
N0.C0.S71: VmseWriteTraining Final: centerPi = 0x3E, PiEw = 0x23, centerVref = 0x42, vrefHeight = 0x22
N4.C0.S57: VmseWriteTraining Final: centerPi = 0x3E, PiEw = 0x28, centerVref = 0x42, vrefHeight = 0x2A
N6.C0.S66: VmseWriteTraining Final: centerPi = 0x3B, PiEw = 0x1C, centerVref = 0x3C, vrefHeight = 0x2A

END - VMSE Train Write                 Time         4154 ms
N4.C0.S58: VmseWriteTraining Final: centerPi = 0x3A, PiEw = 0x28, centerVref = 0x3C, vrefHeight = 0x26
N6.C0.S67: VmseWriteTraining Final: centerPi = 0x39, PiEw = 0x26, centerVref = 0x3A, vrefHeight = 0x2C
Checkpoint Code: Socket 0, 0xB6, 0x64, 0x0000
N4.C0.S59: VmseWriteTraining Final: centerPi = 0x38, PiEw = 0x21, centerVref = 0x41, vrefHeight = 0x26
N6.C0.S68: VmseWriteTraining Final: centerPi = 0x3E, PiEw = 0x27, centerVref = 0x3E, vrefHeight = 0x2A
N0: 
Total VMSE trainings latency = 16654 ms
N4.C0.S60: VmseWriteTraining Final: centerPi = 0x45, PiEw = 0x25, centerVref = 0x40, vrefHeight = 0x2C
N6.C0.S69: VmseWriteTraining Final: centerPi = 0x42, PiEw = 0x20, centerVref = 0x3C, vrefHeight = 0x2E
N0: CpgcVmseTraining for VMSE1
N4.C0.S61: VmseWriteTraining Final: centerPi = 0x43, PiEw = 0x23, centerVref = 0x42, vrefHeight = 0x26
N6.C0.S70: VmseWriteTraining Final: centerPi = 0x3E, PiEw = 0x23, centerVref = 0x39, vrefHeight = 0x2C
Checkpoint Code: Socket 0, 0xB6, 0x11, 0x0000
N4.C0.S62: VmseWriteTraining Final: centerPi = 0x3F, PiEw = 0x29, centerVref = 0x3B, vrefHeight = 0x28
N6.C0.S71: VmseWriteTraining Final: centerPi = 0x3E, PiEw = 0x26, centerVref = 0x3A, vrefHeight = 0x2A
N0: Initialize VMSE Channels
N4.C0.S63: VmseWriteTraining Final: centerPi = 0x45, PiEw = 0x25, centerVref = 0x3A, vrefHeight = 0x2A

END - VMSE Train Write                 Time         4201 ms

START - VMSE Detect DC
N4.C0.S64: VmseWriteTraining Final: centerPi = 0x3B, PiEw = 0x23, centerVref = 0x41, vrefHeight = 0x24
N6: 
Total VMSE trainings latency = 16696 ms
Checkpoint Code: Socket 0, 0xB6, 0x46, 0x0000
N4.C0.S65: VmseWriteTraining Final: centerPi = 0x3F, PiEw = 0x23, centerVref = 0x3A, vrefHeight = 0x2A
N6: CpgcVmseTraining for VMSE1
N0: HsxVmseCompInit
N4.C0.S66: VmseWriteTraining Final: centerPi = 0x3F, PiEw = 0x20, centerVref = 0x3C, vrefHeight = 0x28
N6: Initialize VMSE Channels
Checkpoint Code: Socket 0, 0xB6, 0x80, 0x0000
N4.C0.S67: VmseWriteTraining Final: centerPi = 0x37, PiEw = 0x2B, centerVref = 0x42, vrefHeight = 0x26

START - VMSE Detect DC
N0.C1: Skip DC Detect check for CMD results
N4.C0.S68: VmseWriteTraining Final: centerPi = 0x40, PiEw = 0x29, centerVref = 0x3E, vrefHeight = 0x26
N6: HsxVmseCompInit
N0.C1: Skip DC Detect check for CMD results
N4.C0.S69: VmseWriteTraining Final: centerPi = 0x3E, PiEw = 0x26, centerVref = 0x3A, vrefHeight = 0x26
N6.C1: Skip DC Detect check for CMD results
N0: HsxVmseCompInit
N4.C0.S70: VmseWriteTraining Final: centerPi = 0x3B, PiEw = 0x1D, centerVref = 0x41, vrefHeight = 0x20
N6.C1: Skip DC Detect check for CMD results
Checkpoint Code: Socket 0, 0xB6, 0x81, 0x0000
N4.C0.S71: VmseWriteTraining Final: centerPi = 0x3C, PiEw = 0x26, centerVref = 0x46, vrefHeight = 0x22
N6: HsxVmseCompInit
N0.C1: VmseDetectDC: SUCCESS

END - VMSE Train Write                 Time         4159 ms
N6.C1: VmseDetectDC: SUCCESS
N0.C1: VmseDetectClock
N4: 
Total VMSE trainings latency = 17003 ms
N6.C1: VmseDetectClock
N4: CpgcVmseTraining for VMSE1
N4: Initialize VMSE Channels

START - VMSE Detect DC
N4: HsxVmseCompInit
N4.C1: Skip DC Detect check for CMD results
N4.C1: Skip DC Detect check for CMD results
N4: HsxVmseCompInit
N4.C1: VmseDetectDC: SUCCESS
N4.C1: VmseDetectClock
N0.C1: VmseDetectClock: SUCCESS

END - VMSE Detect DC                   Time         329 ms
N6.C1: VmseDetectClock: SUCCESS

START - MXB Clock Train

END - VMSE Detect DC                   Time         269 ms
Checkpoint Code: Socket 0, 0xB6, 0x48, 0x0000

START - MXB Clock Train
N4.C1: VmseDetectClock: SUCCESS
Checkpoint Code: Socket 0, 0xB6, 0x6C, 0x0000

END - VMSE Detect DC                   Time         211 ms

START - MXB Clock Train
N6.C2: VmseRefVckResync: ddrFreq = 0x2, VMSE_MODE_2_1 = 1, VMSE_PREAMBLE_2UI = 0
N0.C1: VmseAdjustVckVoc: retrain Clock DCC.
   dcc1_vck = 0xC, dcc2_vck = 0x3F, preampvoc = 0x8
Checkpoint Code: Socket 0, 0xB6, 0x6C, 0x0000
N6.C2: VmseRefVckResync: VLINKFREQNXT set to: 0x20F940A
N4.C1: VmseAdjustVckVoc: retrain Clock DCC.
   dcc1_vck = 0x3F, dcc2_vck = 0x29, preampvoc = 0xB
N6.C1: VmseTrainClockAlign: JCK clkadjcnt =0

END - MXB Clock Train                  Time         157 ms

START - VMSE Train Command
N0.C1: VmseAdjustVckVoc: retrain Clock DCC.
   dcc1_vck = 0x9, dcc2_vck = 0x3F, preampvoc = 0x9
Checkpoint Code: Socket 0, 0xB6, 0x6C, 0x0000
N6.C1.B00: HsxCtlXoverInit: invertPiClk = 0x0, RankUsed = 0xFFF, Training = 0x38FFF22
N6.C1.B01: HsxCtlXoverInit: invertPiClk = 0x0, RankUsed = 0xFFF, Training = 0x38FFF00
N4.C1: VmseAdjustVckVoc: retrain Clock DCC.
   dcc1_vck = 0x3F, dcc2_vck = 0x1F, preampvoc = 0xC
N0.C1: VmseAdjustVckVoc: retrain Clock DCC.
   dcc1_vck = 0x7, dcc2_vck = 0x3F, preampvoc = 0xA
Checkpoint Code: Socket 0, 0xB6, 0x6C, 0x0000
N4.C2: VmseRefVckResync: ddrFreq = 0x2, VMSE_MODE_2_1 = 1, VMSE_PREAMBLE_2UI = 0
N6.C1: VmseTrainCmdFine: vmse link sts = 0x4947
N4.C2: VmseRefVckResync: VLINKFREQNXT set to: 0x20F940A
N0.C2: VmseRefVckResync: ddrFreq = 0x2, VMSE_MODE_2_1 = 1, VMSE_PREAMBLE_2UI = 0
N4.C1: VmseTrainClockAlign: JCK clkadjcnt =4
N0.C2: VmseRefVckResync: VLINKFREQNXT set to: 0x20F940A

END - MXB Clock Train                  Time         288 ms

START - VMSE Train Command
N4.C1.B00: HsxCtlXoverInit: invertPiClk = 0x0, RankUsed = 0xFFF, Training = 0x38FFF24
N0.C1: VmseTrainClockAlign: JCK clkadjcnt =1
N4.C1.B01: HsxCtlXoverInit: invertPiClk = 0x0, RankUsed = 0xFFF, Training = 0x38FFF02

END - MXB Clock Train                  Time         395 ms

START - VMSE Train Command
Checkpoint Code: Socket 0, 0xB6, 0x4A, 0x0000
N0.C1.B00: HsxCtlXoverInit: invertPiClk = 0x0, RankUsed = 0xFFF, Training = 0x38FFF24
N0.C1.B01: HsxCtlXoverInit: invertPiClk = 0x0, RankUsed = 0xFFF, Training = 0x38FFF02
Checkpoint Code: Socket 0, 0xB6, 0x60, 0x0000
N4.C1: VmseTrainCmdFine: vmse link sts = 0x4947
Checkpoint Code: Socket 0, 0xB6, 0x5A, 0x0000
N0.C1: VmseTrainCmdFine: vmse link sts = 0x4947
Entry 0 - TrainDcc - DCCStart: 33, VocStart: 13, DCCFinal: 33, VocFinal: 13
Entry 1 - TrainDcc - DCCStart: 45, VocStart: 13, DCCFinal: 37, VocFinal: 13
Entry 0 - TrainDcc - DCCStart: 4, VocStart: 10, DCCFinal: 0, VocFinal: 10
Entry 1 - TrainDcc - DCCStart: 61, VocStart: 10, DCCFinal: 37, VocFinal: 10
Entry 0 - TrainDcc - DCCStart: 56, VocStart: 12, DCCFinal: 8, VocFinal: 12
Entry 1 - TrainDcc - DCCStart: 23, VocStart: 12, DCCFinal: 23, VocFinal: 12
N2.C1.S00: VmseCmdFineTraining Final: centerPi = 0x5F, PiEw = 0x30, centerVref = 0x3B, vrefHeight = 0x4B
N2.C1.S01: VmseCmdFineTraining Final: centerPi = 0x5D, PiEw = 0x2F, centerVref = 0x3E, vrefHeight = 0x4D
N2.C1.S02: VmseCmdFineTraining Final: centerPi = 0x5C, PiEw = 0x35, centerVref = 0x3D, vrefHeight = 0x4F
N2.C1.S03: VmseCmdFineTraining Final: centerPi = 0x60, PiEw = 0x32, centerVref = 0x34, vrefHeight = 0x4F
N2.C1.S04: VmseCmdFineTraining Final: centerPi = 0x56, PiEw = 0x32, centerVref = 0x35, vrefHeight = 0x4D
N2.C1.S05: VmseCmdFineTraining Final: centerPi = 0x5A, PiEw = 0x31, centerVref = 0x39, vrefHeight = 0x4D
N2.C1.S06: VmseCmdFineTraining Final: centerPi = 0x5F, PiEw = 0x32, centerVref = 0x31, vrefHeight = 0x4F
N2.C1.S07: VmseCmdFineTraining Final: centerPi = 0x5E, PiEw = 0x34, centerVref = 0x33, vrefHeight = 0x4F
N2.C1.S08: VmseCmdFineTraining Final: centerPi = 0x56, PiEw = 0x33, centerVref = 0x3B, vrefHeight = 0x4B
N2.C1.S09: VmseCmdFineTraining Final: centerPi = 0x5D, PiEw = 0x31, centerVref = 0x35, vrefHeight = 0x47
N2.C1.S10: VmseCmdFineTraining Final: centerPi = 0x5C, PiEw = 0x2F, centerVref = 0x3C, vrefHeight = 0x4B
N2.C1.S11: VmseCmdFineTraining Final: centerPi = 0x57, PiEw = 0x2F, centerVref = 0x3A, vrefHeight = 0x49
N2.C1.S12: VmseCmdFineTraining Final: centerPi = 0x5C, PiEw = 0x31, centerVref = 0x35, vrefHeight = 0x4B
N2.C1.S13: VmseCmdFineTraining Final: centerPi = 0x58, PiEw = 0x32, centerVref = 0x3A, vrefHeight = 0x49
N2.C1.S14: VmseCmdFineTraining Final: centerPi = 0x5E, PiEw = 0x36, centerVref = 0x3B, vrefHeight = 0x51
N2.C1.S15: VmseCmdFineTraining Final: centerPi = 0x5F, PiEw = 0x31, centerVref = 0x3A, vrefHeight = 0x49
N2.C1.S16: VmseCmdFineTraining Final: centerPi = 0x5C, PiEw = 0x30, centerVref = 0x3A, vrefHeight = 0x4F

END - VMSE Train Command               Time         7244 ms

START - VMSE Train Read Leveling
Entry 0 - TrainDcc - DCCStart: 57, VocStart: 7, DCCFinal: 41, VocFinal: 7
Entry 1 - TrainDcc - DCCStart: 29, VocStart: 7, DCCFinal: 29, VocFinal: 7
N2.C1: VmseReadLevelFineSetup: Initial RT = 101, Initial IO Latency = 0, Initial IO Comp = 15
N2.C1: VmseRLWLFineSearchAll: Entry
N2.C1: FINE READ LEVEL DELAY
N2.C1.S00: RCVEN DELAY = 71
N2.C1.S01: RCVEN DELAY = 68
N2.C1.S02: RCVEN DELAY = 70
N2.C1.S03: RCVEN DELAY = 47
N2.C1.S04: RCVEN DELAY = 70
N2.C1.S05: RCVEN DELAY = 49
N2.C1.S06: RCVEN DELAY = 76
N2.C1.S07: RCVEN DELAY = 49
N2.C1.S08: RCVEN DELAY = 47
N2.C1.S00: READ LEVEL: FINAL RCVEN DELAY (both nibbles) = 40
N2.C1.S01: READ LEVEL: FINAL RCVEN DELAY (both nibbles) = 39
N2.C1.S02: READ LEVEL: FINAL RCVEN DELAY (both nibbles) = 39
N2.C1.S03: READ LEVEL: FINAL RCVEN DELAY (both nibbles) = 16
N2.C1.S04: READ LEVEL: FINAL RCVEN DELAY (both nibbles) = 39
N2.C1.S05: READ LEVEL: FINAL RCVEN DELAY (both nibbles) = 19
N2.C1.S06: READ LEVEL: FINAL RCVEN DELAY (both nibbles) = 47
N2.C1.S07: READ LEVEL: FINAL RCVEN DELAY (both nibbles) = 19
N2.C1.S08: READ LEVEL: FINAL RCVEN DELAY (both nibbles) = 16
N0.C1.S00: VmseCmdFineTraining Final: centerPi = 0x64, PiEw = 0x30, centerVref = 0x3E, vrefHeight = 0x49
N2.C1.D0.S09: READ LEVEL: FINAL RT (all ranks) = 83, FINAL IO LATENCY (all ranks) = 2
N0.C1.S01: VmseCmdFineTraining Final: centerPi = 0x62, PiEw = 0x30, centerVref = 0x3D, vrefHeight = 0x4B
N2.C1.D1.S09: READ LEVEL: FINAL RT (all ranks) = 83, FINAL IO LATENCY (all ranks) = 2
N0.C1.S02: VmseCmdFineTraining Final: centerPi = 0x61, PiEw = 0x34, centerVref = 0x37, vrefHeight = 0x47

END - VMSE Train Read Leveling         Time         285 ms
N0.C1.S03: VmseCmdFineTraining Final: centerPi = 0x61, PiEw = 0x2F, centerVref = 0x3F, vrefHeight = 0x47

START - VMSE Train Read
N0.C1.S04: VmseCmdFineTraining Final: centerPi = 0x5A, PiEw = 0x31, centerVref = 0x38, vrefHeight = 0x49
N0.C1.S05: VmseCmdFineTraining Final: centerPi = 0x5D, PiEw = 0x31, centerVref = 0x3F, vrefHeight = 0x47
N0.C1.S06: VmseCmdFineTraining Final: centerPi = 0x5E, PiEw = 0x30, centerVref = 0x3D, vrefHeight = 0x4B
N0.C1.S07: VmseCmdFineTraining Final: centerPi = 0x61, PiEw = 0x33, centerVref = 0x3A, vrefHeight = 0x49
N0.C1.S08: VmseCmdFineTraining Final: centerPi = 0x58, PiEw = 0x31, centerVref = 0x3C, vrefHeight = 0x45
N0.C1.S09: VmseCmdFineTraining Final: centerPi = 0x5C, PiEw = 0x2D, centerVref = 0x3B, vrefHeight = 0x47
N0.C1.S10: VmseCmdFineTraining Final: centerPi = 0x5D, PiEw = 0x2C, centerVref = 0x3E, vrefHeight = 0x47
N0.C1.S11: VmseCmdFineTraining Final: centerPi = 0x58, PiEw = 0x30, centerVref = 0x3C, vrefHeight = 0x4B
N0.C1.S12: VmseCmdFineTraining Final: centerPi = 0x5C, PiEw = 0x2F, centerVref = 0x3F, vrefHeight = 0x47
N0.C1.S13: VmseCmdFineTraining Final: centerPi = 0x59, PiEw = 0x31, centerVref = 0x40, vrefHeight = 0x47
N0.C1.S14: VmseCmdFineTraining Final: centerPi = 0x5D, PiEw = 0x31, centerVref = 0x39, vrefHeight = 0x45
N0.C1.S15: VmseCmdFineTraining Final: centerPi = 0x60, PiEw = 0x30, centerVref = 0x3C, vrefHeight = 0x45
N0.C1.S16: VmseCmdFineTraining Final: centerPi = 0x5A, PiEw = 0x30, centerVref = 0x3D, vrefHeight = 0x47
N4.C1.S00: VmseCmdFineTraining Final: centerPi = 0x61, PiEw = 0x31, centerVref = 0x39, vrefHeight = 0x4B
N4.C1.S01: VmseCmdFineTraining Final: centerPi = 0x5E, PiEw = 0x2F, centerVref = 0x3D, vrefHeight = 0x47
N4.C1.S02: VmseCmdFineTraining Final: centerPi = 0x5C, PiEw = 0x36, centerVref = 0x3B, vrefHeight = 0x49
N4.C1.S03: VmseCmdFineTraining Final: centerPi = 0x5F, PiEw = 0x31, centerVref = 0x3B, vrefHeight = 0x49
N4.C1.S04: VmseCmdFineTraining Final: centerPi = 0x56, PiEw = 0x31, centerVref = 0x3F, vrefHeight = 0x4B
N4.C1.S05: VmseCmdFineTraining Final: centerPi = 0x5D, PiEw = 0x32, centerVref = 0x39, vrefHeight = 0x49

END - VMSE Train Command               Time         6454 ms
N4.C1.S06: VmseCmdFineTraining Final: centerPi = 0x5D, PiEw = 0x31, centerVref = 0x3B, vrefHeight = 0x4D

START - VMSE Train Read Leveling
N4.C1.S07: VmseCmdFineTraining Final: centerPi = 0x5E, PiEw = 0x34, centerVref = 0x3B, vrefHeight = 0x49
Checkpoint Code: Socket 0, 0xB6, 0x4E, 0x0000
N4.C1.S08: VmseCmdFineTraining Final: centerPi = 0x57, PiEw = 0x31, centerVref = 0x3C, vrefHeight = 0x47
N4.C1.S09: VmseCmdFineTraining Final: centerPi = 0x5D, PiEw = 0x31, centerVref = 0x37, vrefHeight = 0x49
N4.C1.S10: VmseCmdFineTraining Final: centerPi = 0x5D, PiEw = 0x2F, centerVref = 0x3A, vrefHeight = 0x49
N4.C1.S11: VmseCmdFineTraining Final: centerPi = 0x56, PiEw = 0x31, centerVref = 0x40, vrefHeight = 0x47
N4.C1.S12: VmseCmdFineTraining Final: centerPi = 0x5C, PiEw = 0x2F, centerVref = 0x39, vrefHeight = 0x47
N4.C1.S13: VmseCmdFineTraining Final: centerPi = 0x57, PiEw = 0x32, centerVref = 0x38, vrefHeight = 0x49
N4.C1.S14: VmseCmdFineTraining Final: centerPi = 0x5C, PiEw = 0x32, centerVref = 0x3B, vrefHeight = 0x49
N4.C1.S15: VmseCmdFineTraining Final: centerPi = 0x60, PiEw = 0x30, centerVref = 0x3C, vrefHeight = 0x47
N4.C1.S16: VmseCmdFineTraining Final: centerPi = 0x59, PiEw = 0x2F, centerVref = 0x40, vrefHeight = 0x49
N0.C1: VmseReadLevelFineSetup: Initial RT = 101, Initial IO Latency = 0, Initial IO Comp = 15
N0.C1: VmseRLWLFineSearchAll: Entry
N0.C1: FINE READ LEVEL DELAY
N0.C1.S00: RCVEN DELAY = 79
N0.C1.S01: RCVEN DELAY = 75
N0.C1.S02: RCVEN DELAY = 76
N0.C1.S03: RCVEN DELAY = 55
N0.C1.S04: RCVEN DELAY = 82
N0.C1.S05: RCVEN DELAY = 57
N0.C1.S06: RCVEN DELAY = 85
N0.C1.S07: RCVEN DELAY = 61
N0.C1.S08: RCVEN DELAY = 54
N0.C1.S00: READ LEVEL: FINAL RCVEN DELAY (both nibbles) = 176
N0.C1.S01: READ LEVEL: FINAL RCVEN DELAY (both nibbles) = 173
N0.C1.S02: READ LEVEL: FINAL RCVEN DELAY (both nibbles) = 173
N0.C1.S03: READ LEVEL: FINAL RCVEN DELAY (both nibbles) = 151
N0.C1.S04: READ LEVEL: FINAL RCVEN DELAY (both nibbles) = 181
N0.C1.S05: READ LEVEL: FINAL RCVEN DELAY (both nibbles) = 154
N0.C1.S06: READ LEVEL: FINAL RCVEN DELAY (both nibbles) = 182
N0.C1.S07: READ LEVEL: FINAL RCVEN DELAY (both nibbles) = 158
N0.C1.S08: READ LEVEL: FINAL RCVEN DELAY (both nibbles) = 151
N0.C1.D0.S09: READ LEVEL: FINAL RT (all ranks) = 83, FINAL IO LATENCY (all ranks) = 2

END - VMSE Train Command               Time         6796 ms
N0.C1.D1.S09: READ LEVEL: FINAL RT (all ranks) = 83, FINAL IO LATENCY (all ranks) = 2

START - VMSE Train Read Leveling

END - VMSE Train Read Leveling         Time         297 ms

START - VMSE Train Read
Checkpoint Code: Socket 0, 0xB6, 0x50, 0x0000
N6.C1.S00: VmseCmdFineTraining Final: centerPi = 0x62, PiEw = 0x33, centerVref = 0x39, vrefHeight = 0x4D
N6.C1.S01: VmseCmdFineTraining Final: centerPi = 0x63, PiEw = 0x30, centerVref = 0x2F, vrefHeight = 0x53
N6.C1.S02: VmseCmdFineTraining Final: centerPi = 0x5E, PiEw = 0x37, centerVref = 0x36, vrefHeight = 0x4F
N6.C1.S03: VmseCmdFineTraining Final: centerPi = 0x60, PiEw = 0x31, centerVref = 0x3A, vrefHeight = 0x4F
N6.C1.S04: VmseCmdFineTraining Final: centerPi = 0x5B, PiEw = 0x31, centerVref = 0x38, vrefHeight = 0x4D
N6.C1.S05: VmseCmdFineTraining Final: centerPi = 0x5C, PiEw = 0x32, centerVref = 0x38, vrefHeight = 0x4F
N4.C1: VmseReadLevelFineSetup: Initial RT = 101, Initial IO Latency = 0, Initial IO Comp = 15
N6.C1.S06: VmseCmdFineTraining Final: centerPi = 0x5F, PiEw = 0x31, centerVref = 0x31, vrefHeight = 0x51
N6.C1.S07: VmseCmdFineTraining Final: centerPi = 0x62, PiEw = 0x35, centerVref = 0x2F, vrefHeight = 0x51
N6.C1.S08: VmseCmdFineTraining Final: centerPi = 0x57, PiEw = 0x33, centerVref = 0x38, vrefHeight = 0x4B
N6.C1.S09: VmseCmdFineTraining Final: centerPi = 0x5C, PiEw = 0x30, centerVref = 0x3D, vrefHeight = 0x49
N4.C1: VmseRLWLFineSearchAll: Entry
N6.C1.S10: VmseCmdFineTraining Final: centerPi = 0x5C, PiEw = 0x2F, centerVref = 0x34, vrefHeight = 0x4B
N4.C1: FINE READ LEVEL DELAY
N6.C1.S11: VmseCmdFineTraining Final: centerPi = 0x57, PiEw = 0x33, centerVref = 0x3B, vrefHeight = 0x4D
N4.C1.S00: RCVEN DELAY = 77
N6.C1.S12: VmseCmdFineTraining Final: centerPi = 0x5D, PiEw = 0x31, centerVref = 0x3B, vrefHeight = 0x4D
N4.C1.S01: RCVEN DELAY = 70
N6.C1.S13: VmseCmdFineTraining Final: centerPi = 0x58, PiEw = 0x32, centerVref = 0x3A, vrefHeight = 0x49
N4.C1.S02: RCVEN DELAY = 79
N6.C1.S14: VmseCmdFineTraining Final: centerPi = 0x5C, PiEw = 0x32, centerVref = 0x3D, vrefHeight = 0x4B
N4.C1.S03: RCVEN DELAY = 52
N6.C1.S15: VmseCmdFineTraining Final: centerPi = 0x61, PiEw = 0x34, centerVref = 0x3B, vrefHeight = 0x4D
N4.C1.S04: RCVEN DELAY = 77
N6.C1.S16: VmseCmdFineTraining Final: centerPi = 0x5C, PiEw = 0x30, centerVref = 0x3A, vrefHeight = 0x4F
N4.C1.S05: RCVEN DELAY = 52
N4.C1.S06: RCVEN DELAY = 82
N4.C1.S07: RCVEN DELAY = 61
N4.C1.S08: RCVEN DELAY = 55
N4.C1.S00: READ LEVEL: FINAL RCVEN DELAY (both nibbles) = 46
N4.C1.S01: READ LEVEL: FINAL RCVEN DELAY (both nibbles) = 39
N4.C1.S02: READ LEVEL: FINAL RCVEN DELAY (both nibbles) = 50
N4.C1.S03: READ LEVEL: FINAL RCVEN DELAY (both nibbles) = 21
N4.C1.S04: READ LEVEL: FINAL RCVEN DELAY (both nibbles) = 46
N4.C1.S05: READ LEVEL: FINAL RCVEN DELAY (both nibbles) = 21
N4.C1.S06: READ LEVEL: FINAL RCVEN DELAY (both nibbles) = 51
N4.C1.S07: READ LEVEL: FINAL RCVEN DELAY (both nibbles) = 31
N4.C1.S08: READ LEVEL: FINAL RCVEN DELAY (both nibbles) = 27
N4.C1.D0.S09: READ LEVEL: FINAL RT (all ranks) = 83, FINAL IO LATENCY (all ranks) = 2
N4.C1.D1.S09: READ LEVEL: FINAL RT (all ranks) = 83, FINAL IO LATENCY (all ranks) = 2

END - VMSE Train Read Leveling         Time         353 ms

START - VMSE Train Read

END - VMSE Train Command               Time         7413 ms

START - VMSE Train Read Leveling
N6.C1: VmseReadLevelFineSetup: Initial RT = 101, Initial IO Latency = 0, Initial IO Comp = 15
N6.C1: VmseRLWLFineSearchAll: Entry
N6.C1: FINE READ LEVEL DELAY
N6.C1.S00: RCVEN DELAY = 70
N6.C1.S01: RCVEN DELAY = 63
N6.C1.S02: RCVEN DELAY = 68
N6.C1.S03: RCVEN DELAY = 43
N6.C1.S04: RCVEN DELAY = 71
N6.C1.S05: RCVEN DELAY = 47
N6.C1.S06: RCVEN DELAY = 73
N6.C1.S07: RCVEN DELAY = 54
N6.C1.S08: RCVEN DELAY = 49
N6.C1.S00: READ LEVEL: FINAL RCVEN DELAY (both nibbles) = 42
N6.C1.S01: READ LEVEL: FINAL RCVEN DELAY (both nibbles) = 31
N6.C1.S02: READ LEVEL: FINAL RCVEN DELAY (both nibbles) = 37
N6.C1.S03: READ LEVEL: FINAL RCVEN DELAY (both nibbles) = 12
N6.C1.S04: READ LEVEL: FINAL RCVEN DELAY (both nibbles) = 42
N6.C1.S05: READ LEVEL: FINAL RCVEN DELAY (both nibbles) = 18
N6.C1.S06: READ LEVEL: FINAL RCVEN DELAY (both nibbles) = 42
N6.C1.S07: READ LEVEL: FINAL RCVEN DELAY (both nibbles) = 24
N6.C1.S08: READ LEVEL: FINAL RCVEN DELAY (both nibbles) = 18
N6.C1.D0.S09: READ LEVEL: FINAL RT (all ranks) = 83, FINAL IO LATENCY (all ranks) = 2
N6.C1.D1.S09: READ LEVEL: FINAL RT (all ranks) = 83, FINAL IO LATENCY (all ranks) = 2

END - VMSE Train Read Leveling         Time         263 ms

START - VMSE Train Read

END - VMSE Train Read                  Time         3900 ms

START - VMSE Train Level Tx DQS DCC
N2.C1: VmseLevelTxDqsDccExecute: MXB DQS DCC Finished Successfully
N2.C1.S01: VmseAdjustDqsVoc: retrain DQS DCC.
N2.C1.S01:    dcc1_dqs = 0x0, preampvoc = 0xA
N2.C1.S07: VmseAdjustDqsVoc: retrain DQS DCC.
N2.C1.S07:    dcc1_dqs = 0x3F, preampvoc = 0xA
N2.C1: VmseLevelTxDqsDccExecute: MXB DQS DCC Finished Successfully

END - VMSE Train Level Tx DQS DCC      Time         44 ms

START - VMSE Train Write Leveling
N2.C1: VmseWriteLevelFineSetup: Set push to data delay = 6, Global TX DQS delay = 0
N2.C1: VmseRLWLFineSearchAll: Entry
N2.C1: FINE WRITE LEVEL DELAY
N2.C1.S00: TX DQS DELAY = 56
N2.C1.S01: TX DQS DELAY = 57
N2.C1.S02: TX DQS DELAY = 56
N2.C1.S03: TX DQS DELAY = 86
N2.C1.S04: TX DQS DELAY = 52
N2.C1.S05: TX DQS DELAY = 81
N2.C1.S06: TX DQS DELAY = 46
N2.C1.S07: TX DQS DELAY = 74
N2.C1.S08: TX DQS DELAY = 75
N2.C1: VmseWriteLevelCoarseSetup: Set push to data delay = 6, Global TX DQS delay = 0
N2.C1: VmseWriteLevelCoarseExecute
N2.C1: VmseWLCoarseUpdatePD: New push to data delay = 6, New global TxDQS delay = 1
N2.C1: VmseWLCoarseUpdatePD: New push to data delay = 7, New global TxDQS delay = 0
N2.C1: VmseWLCoarseUpdatePD: New push to data delay = 7, New global TxDQS delay = 1
N2.C1: VmseWLCoarseUpdatePD: New push to data delay = 8, New global TxDQS delay = 0
N2.C1: VmseWLCoarseUpdatePD: New push to data delay = 8, New global TxDQS delay = 1
N2.C1.S00: FINAL TX DQS BEFORE TxFIFO CHECK = 155
N2.C1.S01: FINAL TX DQS BEFORE TxFIFO CHECK = 156
N2.C1.S02: FINAL TX DQS BEFORE TxFIFO CHECK = 154
N2.C1.S03: FINAL TX DQS BEFORE TxFIFO CHECK = 186
N2.C1.S04: FINAL TX DQS BEFORE TxFIFO CHECK = 152
N2.C1.S05: FINAL TX DQS BEFORE TxFIFO CHECK = 178
N2.C1.S06: FINAL TX DQS BEFORE TxFIFO CHECK = 144
N2.C1.S07: FINAL TX DQS BEFORE TxFIFO CHECK = 171
N2.C1.S08: FINAL TX DQS BEFORE TxFIFO CHECK = 172
N2.C1: ResolveTxFIFOPtrSeparation: Smallest PI (144) < MIN ALLOWED DELAY (176) 
N2.C1: VmseIncTxFifoPtrSeparation: New push to data delay = 7
N2.C1.S00: VmseIncTxFifoPtrSeparation: pi adjustment = 256, FINAL TX DQS DELAY = 411
N2.C1.S01: VmseIncTxFifoPtrSeparation: pi adjustment = 256, FINAL TX DQS DELAY = 412
N2.C1.S02: VmseIncTxFifoPtrSeparation: pi adjustment = 256, FINAL TX DQS DELAY = 410
N2.C1.S03: VmseIncTxFifoPtrSeparation: pi adjustment = 256, FINAL TX DQS DELAY = 442
N2.C1.S04: VmseIncTxFifoPtrSeparation: pi adjustment = 256, FINAL TX DQS DELAY = 408
N2.C1.S05: VmseIncTxFifoPtrSeparation: pi adjustment = 256, FINAL TX DQS DELAY = 434
N2.C1.S06: VmseIncTxFifoPtrSeparation: pi adjustment = 256, FINAL TX DQS DELAY = 400
N2.C1.S07: VmseIncTxFifoPtrSeparation: pi adjustment = 256, FINAL TX DQS DELAY = 427
N2.C1.S08: VmseIncTxFifoPtrSeparation: pi adjustment = 256, FINAL TX DQS DELAY = 428

END - VMSE Train Write Leveling        Time         252 ms

START - VMSE Train Write

END - VMSE Train Read                  Time         3892 ms

START - VMSE Train Level Tx DQS DCC
Checkpoint Code: Socket 0, 0xB6, 0x52, 0x0000
N0.C1: VmseLevelTxDqsDccExecute: MXB DQS DCC Finished Successfully

END - VMSE Train Level Tx DQS DCC      Time         17 ms

START - VMSE Train Write Leveling
Checkpoint Code: Socket 0, 0xB6, 0x54, 0x0000
N0.C1: VmseWriteLevelFineSetup: Set push to data delay = 6, Global TX DQS delay = 0
N0.C1: VmseRLWLFineSearchAll: Entry
N0.C1: FINE WRITE LEVEL DELAY
N0.C1.S00: TX DQS DELAY = 62
N0.C1.S01: TX DQS DELAY = 64
N0.C1.S02: TX DQS DELAY = 58
N0.C1.S03: TX DQS DELAY = 88
N0.C1.S04: TX DQS DELAY = 62
N0.C1.S05: TX DQS DELAY = 82
N0.C1.S06: TX DQS DELAY = 50
N0.C1.S07: TX DQS DELAY = 77
N0.C1.S08: TX DQS DELAY = 77
N0.C1: VmseWriteLevelCoarseSetup: Set push to data delay = 6, Global TX DQS delay = 0
N0.C1: VmseWriteLevelCoarseExecute
Checkpoint Code: Socket 0, 0xB6, 0xAC, 0x0000
N0.C1: VmseWLCoarseUpdatePD: New push to data delay = 6, New global TxDQS delay = 1
N0.C1: VmseWLCoarseUpdatePD: New push to data delay = 7, New global TxDQS delay = 0
N0.C1: VmseWLCoarseUpdatePD: New push to data delay = 7, New global TxDQS delay = 1
N0.C1: VmseWLCoarseUpdatePD: New push to data delay = 8, New global TxDQS delay = 0
N0.C1: VmseWLCoarseUpdatePD: New push to data delay = 8, New global TxDQS delay = 1
N0.C1: VmseWLCoarseUpdatePD: New push to data delay = 9, New global TxDQS delay = 0
N0.C1.S00: FINAL TX DQS BEFORE TxFIFO CHECK = 32
N0.C1.S01: FINAL TX DQS BEFORE TxFIFO CHECK = 35
N0.C1.S02: FINAL TX DQS BEFORE TxFIFO CHECK = 28
N0.C1.S03: FINAL TX DQS BEFORE TxFIFO CHECK = 60
N0.C1.S04: FINAL TX DQS BEFORE TxFIFO CHECK = 32
N0.C1.S05: FINAL TX DQS BEFORE TxFIFO CHECK = 54
N0.C1.S06: FINAL TX DQS BEFORE TxFIFO CHECK = 20
N0.C1.S07: FINAL TX DQS BEFORE TxFIFO CHECK = 47
N0.C1.S08: FINAL TX DQS BEFORE TxFIFO CHECK = 47
N0.C1: ResolveTxFIFOPtrSeparation: Smallest PI (20) < MIN ALLOWED DELAY (176) 
N0.C1: VmseIncTxFifoPtrSeparation: New push to data delay = 8
N0.C1.S00: VmseIncTxFifoPtrSeparation: pi adjustment = 128, FINAL TX DQS DELAY = 288
N0.C1.S01: VmseIncTxFifoPtrSeparation: pi adjustment = 128, FINAL TX DQS DELAY = 291
N0.C1.S02: VmseIncTxFifoPtrSeparation: pi adjustment = 128, FINAL TX DQS DELAY = 284
N0.C1.S03: VmseIncTxFifoPtrSeparation: pi adjustment = 128, FINAL TX DQS DELAY = 316
N0.C1.S04: VmseIncTxFifoPtrSeparation: pi adjustment = 128, FINAL TX DQS DELAY = 288
N0.C1.S05: VmseIncTxFifoPtrSeparation: pi adjustment = 128, FINAL TX DQS DELAY = 310
N0.C1.S06: VmseIncTxFifoPtrSeparation: pi adjustment = 128, FINAL TX DQS DELAY = 276
N0.C1.S07: VmseIncTxFifoPtrSeparation: pi adjustment = 128, FINAL TX DQS DELAY = 303
N0.C1.S08: VmseIncTxFifoPtrSeparation: pi adjustment = 128, FINAL TX DQS DELAY = 303

END - VMSE Train Write Leveling        Time         269 ms

START - VMSE Train Write
Checkpoint Code: Socket 0, 0xB6, 0x56, 0x0000

END - VMSE Train Read                  Time         3878 ms

START - VMSE Train Level Tx DQS DCC
N4.C1: VmseLevelTxDqsDccExecute: MXB DQS DCC Finished Successfully
N4.C1.S07: VmseAdjustDqsVoc: retrain DQS DCC.
N4.C1.S07:    dcc1_dqs = 0x0, preampvoc = 0xC
N4.C1: VmseLevelTxDqsDccExecute: MXB DQS DCC Finished Successfully

END - VMSE Train Level Tx DQS DCC      Time         34 ms

START - VMSE Train Write Leveling
N4.C1: VmseWriteLevelFineSetup: Set push to data delay = 6, Global TX DQS delay = 0
N4.C1: VmseRLWLFineSearchAll: Entry
N4.C1: FINE WRITE LEVEL DELAY
N4.C1.S00: TX DQS DELAY = 57
N4.C1.S01: TX DQS DELAY = 62
N4.C1.S02: TX DQS DELAY = 56
N4.C1.S03: TX DQS DELAY = 86
N4.C1.S04: TX DQS DELAY = 56
N4.C1.S05: TX DQS DELAY = 81
N4.C1.S06: TX DQS DELAY = 47
N4.C1.S07: TX DQS DELAY = 69
N4.C1.S08: TX DQS DELAY = 72
N4.C1: VmseWriteLevelCoarseSetup: Set push to data delay = 6, Global TX DQS delay = 0
N4.C1: VmseWriteLevelCoarseExecute
N4.C1: VmseWLCoarseUpdatePD: New push to data delay = 6, New global TxDQS delay = 1
N4.C1: VmseWLCoarseUpdatePD: New push to data delay = 7, New global TxDQS delay = 0
N4.C1: VmseWLCoarseUpdatePD: New push to data delay = 7, New global TxDQS delay = 1
N4.C1: VmseWLCoarseUpdatePD: New push to data delay = 8, New global TxDQS delay = 0
N4.C1: VmseWLCoarseUpdatePD: New push to data delay = 8, New global TxDQS delay = 1
N4.C1.S00: FINAL TX DQS BEFORE TxFIFO CHECK = 155
N4.C1.S01: FINAL TX DQS BEFORE TxFIFO CHECK = 161
N4.C1.S02: FINAL TX DQS BEFORE TxFIFO CHECK = 153
N4.C1.S03: FINAL TX DQS BEFORE TxFIFO CHECK = 185
N4.C1.S04: FINAL TX DQS BEFORE TxFIFO CHECK = 153
N4.C1.S05: FINAL TX DQS BEFORE TxFIFO CHECK = 179
N4.C1.S06: FINAL TX DQS BEFORE TxFIFO CHECK = 144
N4.C1.S07: FINAL TX DQS BEFORE TxFIFO CHECK = 168
N4.C1.S08: FINAL TX DQS BEFORE TxFIFO CHECK = 171
N4.C1: ResolveTxFIFOPtrSeparation: Smallest PI (144) < MIN ALLOWED DELAY (176) 
N4.C1: VmseIncTxFifoPtrSeparation: New push to data delay = 7
N4.C1.S00: VmseIncTxFifoPtrSeparation: pi adjustment = 256, FINAL TX DQS DELAY = 411
N4.C1.S01: VmseIncTxFifoPtrSeparation: pi adjustment = 256, FINAL TX DQS DELAY = 417
N4.C1.S02: VmseIncTxFifoPtrSeparation: pi adjustment = 256, FINAL TX DQS DELAY = 409
N4.C1.S03: VmseIncTxFifoPtrSeparation: pi adjustment = 256, FINAL TX DQS DELAY = 441
N4.C1.S04: VmseIncTxFifoPtrSeparation: pi adjustment = 256, FINAL TX DQS DELAY = 409
N4.C1.S05: VmseIncTxFifoPtrSeparation: pi adjustment = 256, FINAL TX DQS DELAY = 435
N4.C1.S06: VmseIncTxFifoPtrSeparation: pi adjustment = 256, FINAL TX DQS DELAY = 400
N4.C1.S07: VmseIncTxFifoPtrSeparation: pi adjustment = 256, FINAL TX DQS DELAY = 424
N4.C1.S08: VmseIncTxFifoPtrSeparation: pi adjustment = 256, FINAL TX DQS DELAY = 427

END - VMSE Train Write Leveling        Time         251 ms

START - VMSE Train Write

END - VMSE Train Read                  Time         3898 ms

START - VMSE Train Level Tx DQS DCC
N6.C1: VmseLevelTxDqsDccExecute: MXB DQS DCC Finished Successfully

END - VMSE Train Level Tx DQS DCC      Time         12 ms

START - VMSE Train Write Leveling
N6.C1: VmseWriteLevelFineSetup: Set push to data delay = 6, Global TX DQS delay = 0
N6.C1: VmseRLWLFineSearchAll: Entry
N6.C1: FINE WRITE LEVEL DELAY
N6.C1.S00: TX DQS DELAY = 56
N6.C1.S01: TX DQS DELAY = 60
N6.C1.S02: TX DQS DELAY = 48
N6.C1.S03: TX DQS DELAY = 81
N6.C1.S04: TX DQS DELAY = 51
N6.C1.S05: TX DQS DELAY = 78
N6.C1.S06: TX DQS DELAY = 42
N6.C1.S07: TX DQS DELAY = 71
N6.C1.S08: TX DQS DELAY = 69
N6.C1: VmseWriteLevelCoarseSetup: Set push to data delay = 6, Global TX DQS delay = 0
N6.C1: VmseWriteLevelCoarseExecute
N6.C1: VmseWLCoarseUpdatePD: New push to data delay = 6, New global TxDQS delay = 1
N6.C1: VmseWLCoarseUpdatePD: New push to data delay = 7, New global TxDQS delay = 0
N6.C1: VmseWLCoarseUpdatePD: New push to data delay = 7, New global TxDQS delay = 1
N6.C1: VmseWLCoarseUpdatePD: New push to data delay = 8, New global TxDQS delay = 0
Entry 0 - TrainDcc - DCCStart: 5, VocStart: 12, DCCFinal: 37, VocFinal: 12
N6.C1: VmseWLCoarseUpdatePD: New push to data delay = 8, New global TxDQS delay = 1
Entry 1 - TrainDcc - DCCStart: 4, VocStart: 10, DCCFinal: 4, VocFinal: 10
N6.C1.S00: FINAL TX DQS BEFORE TxFIFO CHECK = 153
Entry 2 - TrainDcc - DCCStart: 10, VocStart: 13, DCCFinal: 34, VocFinal: 13
N6.C1.S01: FINAL TX DQS BEFORE TxFIFO CHECK = 157
Entry 3 - TrainDcc - DCCStart: 49, VocStart: 12, DCCFinal: 49, VocFinal: 12
N6.C1.S02: FINAL TX DQS BEFORE TxFIFO CHECK = 145
Entry 4 - TrainDcc - DCCStart: 22, VocStart: 16, DCCFinal: 22, VocFinal: 23
N6.C1.S03: FINAL TX DQS BEFORE TxFIFO CHECK = 179
Entry 5 - TrainDcc - DCCStart: 59, VocStart: 11, DCCFinal: 59, VocFinal: 11
N6.C1.S04: FINAL TX DQS BEFORE TxFIFO CHECK = 149
Entry 6 - TrainDcc - DCCStart: 27, VocStart: 20, DCCFinal: 27, VocFinal: 28
N6.C1.S05: FINAL TX DQS BEFORE TxFIFO CHECK = 177
Entry 7 - TrainDcc - DCCStart: 57, VocStart: 10, DCCFinal: 57, VocFinal: 10
N6.C1.S06: FINAL TX DQS BEFORE TxFIFO CHECK = 140
Entry 8 - TrainDcc - DCCStart: 11, VocStart: 10, DCCFinal: 11, VocFinal: 10
N6.C1.S07: FINAL TX DQS BEFORE TxFIFO CHECK = 168
N6.C1.S08: FINAL TX DQS BEFORE TxFIFO CHECK = 168
N6.C1: ResolveTxFIFOPtrSeparation: Smallest PI (140) < MIN ALLOWED DELAY (176) 
N6.C1: VmseIncTxFifoPtrSeparation: New push to data delay = 7
N6.C1.S00: VmseIncTxFifoPtrSeparation: pi adjustment = 256, FINAL TX DQS DELAY = 409
N6.C1.S01: VmseIncTxFifoPtrSeparation: pi adjustment = 256, FINAL TX DQS DELAY = 413
N6.C1.S02: VmseIncTxFifoPtrSeparation: pi adjustment = 256, FINAL TX DQS DELAY = 401
N6.C1.S03: VmseIncTxFifoPtrSeparation: pi adjustment = 256, FINAL TX DQS DELAY = 435
N6.C1.S04: VmseIncTxFifoPtrSeparation: pi adjustment = 256, FINAL TX DQS DELAY = 405
N6.C1.S05: VmseIncTxFifoPtrSeparation: pi adjustment = 256, FINAL TX DQS DELAY = 433
N6.C1.S06: VmseIncTxFifoPtrSeparation: pi adjustment = 256, FINAL TX DQS DELAY = 396
N6.C1.S07: VmseIncTxFifoPtrSeparation: pi adjustment = 256, FINAL TX DQS DELAY = 424
N6.C1.S08: VmseIncTxFifoPtrSeparation: pi adjustment = 256, FINAL TX DQS DELAY = 424

END - VMSE Train Write Leveling        Time         324 ms

START - VMSE Train Write
N2.C1.S00: VmseWriteTraining Final: centerPi = 0x3A, PiEw = 0x2C, centerVref = 0x3F, vrefHeight = 0x30
N2.C1.S01: VmseWriteTraining Final: centerPi = 0x3A, PiEw = 0x2B, centerVref = 0x39, vrefHeight = 0x30
N2.C1.S02: VmseWriteTraining Final: centerPi = 0x35, PiEw = 0x29, centerVref = 0x3F, vrefHeight = 0x2A
N2.C1.S03: VmseWriteTraining Final: centerPi = 0x39, PiEw = 0x29, centerVref = 0x3C, vrefHeight = 0x2E
N2.C1.S04: VmseWriteTraining Final: centerPi = 0x3E, PiEw = 0x2B, centerVref = 0x3A, vrefHeight = 0x2E
N2.C1.S05: VmseWriteTraining Final: centerPi = 0x3C, PiEw = 0x2D, centerVref = 0x3D, vrefHeight = 0x2C
N2.C1.S06: VmseWriteTraining Final: centerPi = 0x3B, PiEw = 0x2B, centerVref = 0x3E, vrefHeight = 0x2E
Entry 0 - TrainDcc - DCCStart: 6, VocStart: 14, DCCFinal: 14, VocFinal: 14
N2.C1.S07: VmseWriteTraining Final: centerPi = 0x3E, PiEw = 0x2B, centerVref = 0x39, vrefHeight = 0x2E
Entry 1 - TrainDcc - DCCStart: 17, VocStart: 17, DCCFinal: 17, VocFinal: 17
N2.C1.S08: VmseWriteTraining Final: centerPi = 0x3F, PiEw = 0x23, centerVref = 0x40, vrefHeight = 0x2E
Entry 2 - TrainDcc - DCCStart: 6, VocStart: 14, DCCFinal: 54, VocFinal: 14
N2.C1.S09: VmseWriteTraining Final: centerPi = 0x40, PiEw = 0x29, centerVref = 0x3D, vrefHeight = 0x30
Entry 3 - TrainDcc - DCCStart: 8, VocStart: 11, DCCFinal: 8, VocFinal: 11
N2.C1.S10: VmseWriteTraining Final: centerPi = 0x3D, PiEw = 0x25, centerVref = 0x3F, vrefHeight = 0x2C
Entry 4 - TrainDcc - DCCStart: 30, VocStart: 16, DCCFinal: 30, VocFinal: 16
N2.C1.S11: VmseWriteTraining Final: centerPi = 0x3A, PiEw = 0x28, centerVref = 0x3D, vrefHeight = 0x2C
Entry 5 - TrainDcc - DCCStart: 9, VocStart: 12, DCCFinal: 9, VocFinal: 12
N2.C1.S12: VmseWriteTraining Final: centerPi = 0x42, PiEw = 0x26, centerVref = 0x41, vrefHeight = 0x2E
Entry 6 - TrainDcc - DCCStart: 13, VocStart: 10, DCCFinal: 13, VocFinal: 10
N2.C1.S13: VmseWriteTraining Final: centerPi = 0x41, PiEw = 0x28, centerVref = 0x3B, vrefHeight = 0x2E
Entry 7 - TrainDcc - DCCStart: 13, VocStart: 14, DCCFinal: 13, VocFinal: 14
N2.C1.S14: VmseWriteTraining Final: centerPi = 0x40, PiEw = 0x24, centerVref = 0x3C, vrefHeight = 0x2E
Entry 8 - TrainDcc - DCCStart: 13, VocStart: 10, DCCFinal: 13, VocFinal: 10
N2.C1.S15: VmseWriteTraining Final: centerPi = 0x41, PiEw = 0x28, centerVref = 0x3F, vrefHeight = 0x2E
N2.C1.S16: VmseWriteTraining Final: centerPi = 0x3B, PiEw = 0x25, centerVref = 0x3C, vrefHeight = 0x2C
N2.C1.S17: VmseWriteTraining Final: centerPi = 0x38, PiEw = 0x29, centerVref = 0x39, vrefHeight = 0x2C
N2.C1.S18: VmseWriteTraining Final: centerPi = 0x37, PiEw = 0x29, centerVref = 0x39, vrefHeight = 0x30
N2.C1.S19: VmseWriteTraining Final: centerPi = 0x35, PiEw = 0x2E, centerVref = 0x3E, vrefHeight = 0x30
N2.C1.S20: VmseWriteTraining Final: centerPi = 0x3D, PiEw = 0x29, centerVref = 0x3F, vrefHeight = 0x2C
N2.C1.S21: VmseWriteTraining Final: centerPi = 0x3A, PiEw = 0x28, centerVref = 0x3E, vrefHeight = 0x2C
N2.C1.S22: VmseWriteTraining Final: centerPi = 0x3B, PiEw = 0x29, centerVref = 0x3A, vrefHeight = 0x2A
N2.C1.S23: VmseWriteTraining Final: centerPi = 0x3A, PiEw = 0x29, centerVref = 0x3E, vrefHeight = 0x2A
N2.C1.S24: VmseWriteTraining Final: centerPi = 0x38, PiEw = 0x29, centerVref = 0x3E, vrefHeight = 0x2E
N2.C1.S25: VmseWriteTraining Final: centerPi = 0x37, PiEw = 0x2B, centerVref = 0x3F, vrefHeight = 0x2E
N2.C1.S26: VmseWriteTraining Final: centerPi = 0x38, PiEw = 0x29, centerVref = 0x3C, vrefHeight = 0x2E
N2.C1.S27: VmseWriteTraining Final: centerPi = 0x39, PiEw = 0x28, centerVref = 0x39, vrefHeight = 0x30
N2.C1.S28: VmseWriteTraining Final: centerPi = 0x3C, PiEw = 0x25, centerVref = 0x3B, vrefHeight = 0x28
N2.C1.S29: VmseWriteTraining Final: centerPi = 0x3D, PiEw = 0x24, centerVref = 0x38, vrefHeight = 0x2C
N2.C1.S30: VmseWriteTraining Final: centerPi = 0x3D, PiEw = 0x28, centerVref = 0x3B, vrefHeight = 0x30
N2.C1.S31: VmseWriteTraining Final: centerPi = 0x3C, PiEw = 0x27, centerVref = 0x41, vrefHeight = 0x2A
N2.C1.S32: VmseWriteTraining Final: centerPi = 0x39, PiEw = 0x2B, centerVref = 0x41, vrefHeight = 0x2C
N2.C1.S33: VmseWriteTraining Final: centerPi = 0x40, PiEw = 0x27, centerVref = 0x37, vrefHeight = 0x30
N2.C1.S34: VmseWriteTraining Final: centerPi = 0x3D, PiEw = 0x28, centerVref = 0x3C, vrefHeight = 0x2E
N2.C1.S35: VmseWriteTraining Final: centerPi = 0x3B, PiEw = 0x28, centerVref = 0x3A, vrefHeight = 0x30
N2.C1.S36: VmseWriteTraining Final: centerPi = 0x3F, PiEw = 0x29, centerVref = 0x3F, vrefHeight = 0x2C
Entry 0 - TrainDcc - DCCStart: 30, VocStart: 16, DCCFinal: 63, VocFinal: 16
N2.C1.S37: VmseWriteTraining Final: centerPi = 0x3B, PiEw = 0x29, centerVref = 0x3C, vrefHeight = 0x2A
Entry 1 - TrainDcc - DCCStart: 14, VocStart: 12, DCCFinal: 14, VocFinal: 12
N0.C1.S00: VmseWriteTraining Final: centerPi = 0x39, PiEw = 0x2A, centerVref = 0x48, vrefHeight = 0x28
N2.C1.S38: VmseWriteTraining Final: centerPi = 0x3D, PiEw = 0x28, centerVref = 0x3D, vrefHeight = 0x2E
Entry 2 - TrainDcc - DCCStart: 34, VocStart: 16, DCCFinal: 34, VocFinal: 16
N0.C1.S01: VmseWriteTraining Final: centerPi = 0x3B, PiEw = 0x2C, centerVref = 0x3F, vrefHeight = 0x2C
N2.C1.S39: VmseWriteTraining Final: centerPi = 0x3C, PiEw = 0x29, centerVref = 0x3D, vrefHeight = 0x2C
Entry 3 - TrainDcc - DCCStart: 16, VocStart: 17, DCCFinal: 16, VocFinal: 17
N0.C1.S02: VmseWriteTraining Final: centerPi = 0x39, PiEw = 0x27, centerVref = 0x41, vrefHeight = 0x28
N2.C1.S40: VmseWriteTraining Final: centerPi = 0x36, PiEw = 0x2B, centerVref = 0x46, vrefHeight = 0x2E
Entry 4 - TrainDcc - DCCStart: 43, VocStart: 12, DCCFinal: 43, VocFinal: 12
N0.C1.S03: VmseWriteTraining Final: centerPi = 0x38, PiEw = 0x28, centerVref = 0x3C, vrefHeight = 0x2A
N2.C1.S41: VmseWriteTraining Final: centerPi = 0x37, PiEw = 0x2C, centerVref = 0x40, vrefHeight = 0x2E
Entry 5 - TrainDcc - DCCStart: 13, VocStart: 11, DCCFinal: 13, VocFinal: 11
N0.C1.S04: VmseWriteTraining Final: centerPi = 0x3F, PiEw = 0x27, centerVref = 0x41, vrefHeight = 0x28
N2.C1.S42: VmseWriteTraining Final: centerPi = 0x38, PiEw = 0x29, centerVref = 0x3C, vrefHeight = 0x2E
Entry 6 - TrainDcc - DCCStart: 22, VocStart: 13, DCCFinal: 22, VocFinal: 13
N0.C1.S05: VmseWriteTraining Final: centerPi = 0x3E, PiEw = 0x27, centerVref = 0x3E, vrefHeight = 0x26
N2.C1.S43: VmseWriteTraining Final: centerPi = 0x37, PiEw = 0x2A, centerVref = 0x3E, vrefHeight = 0x2E
Entry 7 - TrainDcc - DCCStart: 4, VocStart: 12, DCCFinal: 4, VocFinal: 12
N0.C1.S06: VmseWriteTraining Final: centerPi = 0x3F, PiEw = 0x28, centerVref = 0x3C, vrefHeight = 0x2A
N2.C1.S44: VmseWriteTraining Final: centerPi = 0x41, PiEw = 0x26, centerVref = 0x3B, vrefHeight = 0x30
Entry 8 - TrainDcc - DCCStart: 24, VocStart: 13, DCCFinal: 24, VocFinal: 13
N0.C1.S07: VmseWriteTraining Final: centerPi = 0x3E, PiEw = 0x29, centerVref = 0x40, vrefHeight = 0x2A
N2.C1.S45: VmseWriteTraining Final: centerPi = 0x3C, PiEw = 0x2B, centerVref = 0x3D, vrefHeight = 0x2C
N0.C1.S08: VmseWriteTraining Final: centerPi = 0x3B, PiEw = 0x27, centerVref = 0x44, vrefHeight = 0x28
N2.C1.S46: VmseWriteTraining Final: centerPi = 0x3D, PiEw = 0x25, centerVref = 0x3A, vrefHeight = 0x30
N0.C1.S09: VmseWriteTraining Final: centerPi = 0x3C, PiEw = 0x2A, centerVref = 0x40, vrefHeight = 0x2A
N2.C1.S47: VmseWriteTraining Final: centerPi = 0x3C, PiEw = 0x2B, centerVref = 0x3D, vrefHeight = 0x2E
N0.C1.S10: VmseWriteTraining Final: centerPi = 0x3B, PiEw = 0x27, centerVref = 0x3E, vrefHeight = 0x2A
N2.C1.S48: VmseWriteTraining Final: centerPi = 0x3B, PiEw = 0x29, centerVref = 0x3E, vrefHeight = 0x2A
N0.C1.S11: VmseWriteTraining Final: centerPi = 0x3A, PiEw = 0x28, centerVref = 0x3E, vrefHeight = 0x2A
N2.C1.S49: VmseWriteTraining Final: centerPi = 0x3D, PiEw = 0x2B, centerVref = 0x3D, vrefHeight = 0x30
N0.C1.S12: VmseWriteTraining Final: centerPi = 0x41, PiEw = 0x28, centerVref = 0x41, vrefHeight = 0x2A
N2.C1.S50: VmseWriteTraining Final: centerPi = 0x3A, PiEw = 0x28, centerVref = 0x40, vrefHeight = 0x2E
N0.C1.S13: VmseWriteTraining Final: centerPi = 0x41, PiEw = 0x28, centerVref = 0x3E, vrefHeight = 0x28
N2.C1.S51: VmseWriteTraining Final: centerPi = 0x39, PiEw = 0x2D, centerVref = 0x3B, vrefHeight = 0x2E
N0.C1.S14: VmseWriteTraining Final: centerPi = 0x3F, PiEw = 0x27, centerVref = 0x3E, vrefHeight = 0x2A
N2.C1.S52: VmseWriteTraining Final: centerPi = 0x42, PiEw = 0x28, centerVref = 0x3A, vrefHeight = 0x2E
N0.C1.S15: VmseWriteTraining Final: centerPi = 0x3F, PiEw = 0x2D, centerVref = 0x43, vrefHeight = 0x2A
N2.C1.S53: VmseWriteTraining Final: centerPi = 0x41, PiEw = 0x29, centerVref = 0x3B, vrefHeight = 0x2C
N0.C1.S16: VmseWriteTraining Final: centerPi = 0x39, PiEw = 0x28, centerVref = 0x40, vrefHeight = 0x28
N2.C1.S54: VmseWriteTraining Final: centerPi = 0x3E, PiEw = 0x25, centerVref = 0x40, vrefHeight = 0x2C
N0.C1.S17: VmseWriteTraining Final: centerPi = 0x38, PiEw = 0x29, centerVref = 0x40, vrefHeight = 0x26
N2.C1.S55: VmseWriteTraining Final: centerPi = 0x3E, PiEw = 0x2B, centerVref = 0x3A, vrefHeight = 0x30
N0.C1.S18: VmseWriteTraining Final: centerPi = 0x36, PiEw = 0x28, centerVref = 0x3B, vrefHeight = 0x2A
N2.C1.S56: VmseWriteTraining Final: centerPi = 0x3A, PiEw = 0x29, centerVref = 0x3F, vrefHeight = 0x2C
N0.C1.S19: VmseWriteTraining Final: centerPi = 0x35, PiEw = 0x29, centerVref = 0x3D, vrefHeight = 0x28
N2.C1.S57: VmseWriteTraining Final: centerPi = 0x3A, PiEw = 0x2C, centerVref = 0x3F, vrefHeight = 0x30
N4.C1.S00: VmseWriteTraining Final: centerPi = 0x38, PiEw = 0x2B, centerVref = 0x41, vrefHeight = 0x28
Entry 0 - TrainDcc - DCCStart: 12, VocStart: 22, DCCFinal: 52, VocFinal: 22
N0.C1.S20: VmseWriteTraining Final: centerPi = 0x3C, PiEw = 0x2A, centerVref = 0x43, vrefHeight = 0x28
N2.C1.S58: VmseWriteTraining Final: centerPi = 0x39, PiEw = 0x29, centerVref = 0x3B, vrefHeight = 0x30
N4.C1.S01: VmseWriteTraining Final: centerPi = 0x35, PiEw = 0x29, centerVref = 0x46, vrefHeight = 0x26
Entry 1 - TrainDcc - DCCStart: 17, VocStart: 10, DCCFinal: 17, VocFinal: 10
N0.C1.S21: VmseWriteTraining Final: centerPi = 0x3A, PiEw = 0x28, centerVref = 0x3F, vrefHeight = 0x28
N2.C1.S59: VmseWriteTraining Final: centerPi = 0x38, PiEw = 0x2D, centerVref = 0x3E, vrefHeight = 0x2E
N4.C1.S02: VmseWriteTraining Final: centerPi = 0x35, PiEw = 0x2B, centerVref = 0x41, vrefHeight = 0x28
Entry 2 - TrainDcc - DCCStart: 1, VocStart: 12, DCCFinal: 33, VocFinal: 12
N0.C1.S22: VmseWriteTraining Final: centerPi = 0x38, PiEw = 0x28, centerVref = 0x3D, vrefHeight = 0x26
N2.C1.S60: VmseWriteTraining Final: centerPi = 0x3C, PiEw = 0x2B, centerVref = 0x3C, vrefHeight = 0x2E
N4.C1.S03: VmseWriteTraining Final: centerPi = 0x36, PiEw = 0x2A, centerVref = 0x3F, vrefHeight = 0x28
Entry 3 - TrainDcc - DCCStart: 15, VocStart: 13, DCCFinal: 15, VocFinal: 13
N0.C1.S23: VmseWriteTraining Final: centerPi = 0x39, PiEw = 0x2A, centerVref = 0x45, vrefHeight = 0x28
N2.C1.S61: VmseWriteTraining Final: centerPi = 0x3B, PiEw = 0x27, centerVref = 0x3F, vrefHeight = 0x2C
N4.C1.S04: VmseWriteTraining Final: centerPi = 0x3E, PiEw = 0x23, centerVref = 0x3A, vrefHeight = 0x28
Entry 4 - TrainDcc - DCCStart: 12, VocStart: 10, DCCFinal: 12, VocFinal: 18
N0.C1.S24: VmseWriteTraining Final: centerPi = 0x3C, PiEw = 0x24, centerVref = 0x3E, vrefHeight = 0x28
N2.C1.S62: VmseWriteTraining Final: centerPi = 0x3B, PiEw = 0x2C, centerVref = 0x3B, vrefHeight = 0x30
N4.C1.S05: VmseWriteTraining Final: centerPi = 0x3A, PiEw = 0x2A, centerVref = 0x3F, vrefHeight = 0x28
Entry 5 - TrainDcc - DCCStart: 5, VocStart: 13, DCCFinal: 5, VocFinal: 13
N0.C1.S25: VmseWriteTraining Final: centerPi = 0x3D, PiEw = 0x26, centerVref = 0x3C, vrefHeight = 0x2C
N2.C1.S63: VmseWriteTraining Final: centerPi = 0x3A, PiEw = 0x2A, centerVref = 0x3C, vrefHeight = 0x2C
N4.C1.S06: VmseWriteTraining Final: centerPi = 0x3A, PiEw = 0x27, centerVref = 0x41, vrefHeight = 0x28
Entry 6 - TrainDcc - DCCStart: 12, VocStart: 11, DCCFinal: 12, VocFinal: 16
N0.C1.S26: VmseWriteTraining Final: centerPi = 0x3D, PiEw = 0x27, centerVref = 0x41, vrefHeight = 0x2C
N2.C1.S64: VmseWriteTraining Final: centerPi = 0x38, PiEw = 0x29, centerVref = 0x41, vrefHeight = 0x28
N4.C1.S07: VmseWriteTraining Final: centerPi = 0x38, PiEw = 0x29, centerVref = 0x40, vrefHeight = 0x2A
Entry 7 - TrainDcc - DCCStart: 15, VocStart: 13, DCCFinal: 15, VocFinal: 13
N0.C1.S27: VmseWriteTraining Final: centerPi = 0x3A, PiEw = 0x24, centerVref = 0x3D, vrefHeight = 0x2C
N2.C1.S65: VmseWriteTraining Final: centerPi = 0x38, PiEw = 0x25, centerVref = 0x39, vrefHeight = 0x28
N4.C1.S08: VmseWriteTraining Final: centerPi = 0x3A, PiEw = 0x2B, centerVref = 0x42, vrefHeight = 0x2A
Entry 8 - TrainDcc - DCCStart: 5, VocStart: 13, DCCFinal: 5, VocFinal: 13
N0.C1.S28: VmseWriteTraining Final: centerPi = 0x3F, PiEw = 0x20, centerVref = 0x40, vrefHeight = 0x22
N2.C1.S66: VmseWriteTraining Final: centerPi = 0x38, PiEw = 0x23, centerVref = 0x3A, vrefHeight = 0x2C
N4.C1.S09: VmseWriteTraining Final: centerPi = 0x3E, PiEw = 0x28, centerVref = 0x42, vrefHeight = 0x2A
N0.C1.S29: VmseWriteTraining Final: centerPi = 0x3F, PiEw = 0x25, centerVref = 0x3B, vrefHeight = 0x24
N2.C1.S67: VmseWriteTraining Final: centerPi = 0x3C, PiEw = 0x22, centerVref = 0x3A, vrefHeight = 0x30
N4.C1.S10: VmseWriteTraining Final: centerPi = 0x3C, PiEw = 0x25, centerVref = 0x41, vrefHeight = 0x2C
N0.C1.S30: VmseWriteTraining Final: centerPi = 0x41, PiEw = 0x23, centerVref = 0x3F, vrefHeight = 0x2A
N2.C1.S68: VmseWriteTraining Final: centerPi = 0x40, PiEw = 0x27, centerVref = 0x3C, vrefHeight = 0x2E
N4.C1.S11: VmseWriteTraining Final: centerPi = 0x37, PiEw = 0x2B, centerVref = 0x41, vrefHeight = 0x2C
N0.C1.S31: VmseWriteTraining Final: centerPi = 0x3F, PiEw = 0x26, centerVref = 0x3C, vrefHeight = 0x26
N2.C1.S69: VmseWriteTraining Final: centerPi = 0x3D, PiEw = 0x25, centerVref = 0x3D, vrefHeight = 0x2A
N4.C1.S12: VmseWriteTraining Final: centerPi = 0x42, PiEw = 0x23, centerVref = 0x40, vrefHeight = 0x2C
N0.C1.S32: VmseWriteTraining Final: centerPi = 0x3A, PiEw = 0x2A, centerVref = 0x42, vrefHeight = 0x26
N2.C1.S70: VmseWriteTraining Final: centerPi = 0x40, PiEw = 0x23, centerVref = 0x39, vrefHeight = 0x30
N4.C1.S13: VmseWriteTraining Final: centerPi = 0x3E, PiEw = 0x28, centerVref = 0x3C, vrefHeight = 0x26
N0.C1.S33: VmseWriteTraining Final: centerPi = 0x3C, PiEw = 0x2B, centerVref = 0x3C, vrefHeight = 0x2A
N2.C1.S71: VmseWriteTraining Final: centerPi = 0x3D, PiEw = 0x28, centerVref = 0x42, vrefHeight = 0x2A
N4.C1.S14: VmseWriteTraining Final: centerPi = 0x40, PiEw = 0x24, centerVref = 0x3D, vrefHeight = 0x2C
N0.C1.S34: VmseWriteTraining Final: centerPi = 0x39, PiEw = 0x28, centerVref = 0x3F, vrefHeight = 0x2C

END - VMSE Train Write                 Time         3077 ms
N4.C1.S15: VmseWriteTraining Final: centerPi = 0x3F, PiEw = 0x2B, centerVref = 0x46, vrefHeight = 0x28
N0.C1.S35: VmseWriteTraining Final: centerPi = 0x37, PiEw = 0x2A, centerVref = 0x41, vrefHeight = 0x2A
N2: 
Total VMSE trainings latency = 15687 ms
N4.C1.S16: VmseWriteTraining Final: centerPi = 0x38, PiEw = 0x25, centerVref = 0x40, vrefHeight = 0x26
N0.C1.S36: VmseWriteTraining Final: centerPi = 0x3F, PiEw = 0x28, centerVref = 0x3F, vrefHeight = 0x28
N3: GatherSPDData
N4.C1.S17: VmseWriteTraining Final: centerPi = 0x36, PiEw = 0x24, centerVref = 0x3F, vrefHeight = 0x24
N0.C1.S37: VmseWriteTraining Final: centerPi = 0x3C, PiEw = 0x27, centerVref = 0x3E, vrefHeight = 0x26
Gather SPD Data
N4.C1.S18: VmseWriteTraining Final: centerPi = 0x34, PiEw = 0x27, centerVref = 0x3F, vrefHeight = 0x28
N0.C1.S38: VmseWriteTraining Final: centerPi = 0x3F, PiEw = 0x28, centerVref = 0x3B, vrefHeight = 0x2A
N3.C0.D0: tWR in MTB units: 0x78
N4.C1.S19: VmseWriteTraining Final: centerPi = 0x35, PiEw = 0x2A, centerVref = 0x3B, vrefHeight = 0x2C
N6.C1.S00: VmseWriteTraining Final: centerPi = 0x36, PiEw = 0x2B, centerVref = 0x40, vrefHeight = 0x2E
N0.C1.S39: VmseWriteTraining Final: centerPi = 0x3E, PiEw = 0x2A, centerVref = 0x3F, vrefHeight = 0x2A
N3.C1.D0: tWR in MTB units: 0x78
N4.C1.S20: VmseWriteTraining Final: centerPi = 0x3C, PiEw = 0x29, centerVref = 0x3E, vrefHeight = 0x26
N6.C1.S01: VmseWriteTraining Final: centerPi = 0x39, PiEw = 0x29, centerVref = 0x40, vrefHeight = 0x2E
N0.C1.S40: VmseWriteTraining Final: centerPi = 0x3C, PiEw = 0x27, centerVref = 0x3E, vrefHeight = 0x28
N3.C2.D0: tWR in MTB units: 0x78
N4.C1.S21: VmseWriteTraining Final: centerPi = 0x3D, PiEw = 0x26, centerVref = 0x3E, vrefHeight = 0x26
N6.C1.S02: VmseWriteTraining Final: centerPi = 0x33, PiEw = 0x2C, centerVref = 0x3C, vrefHeight = 0x2E
N0.C1.S41: VmseWriteTraining Final: centerPi = 0x3C, PiEw = 0x2B, centerVref = 0x42, vrefHeight = 0x2A
N3.C3.D0: tWR in MTB units: 0x78
N4.C1.S22: VmseWriteTraining Final: centerPi = 0x39, PiEw = 0x26, centerVref = 0x3D, vrefHeight = 0x28
N6.C1.S03: VmseWriteTraining Final: centerPi = 0x38, PiEw = 0x27, centerVref = 0x39, vrefHeight = 0x30
N0.C1.S42: VmseWriteTraining Final: centerPi = 0x3A, PiEw = 0x22, centerVref = 0x40, vrefHeight = 0x2A

GatherSPDData time            152 ms
N4.C1.S23: VmseWriteTraining Final: centerPi = 0x39, PiEw = 0x25, centerVref = 0x3F, vrefHeight = 0x24
N6.C1.S04: VmseWriteTraining Final: centerPi = 0x3D, PiEw = 0x2B, centerVref = 0x39, vrefHeight = 0x2E
N0.C1.S43: VmseWriteTraining Final: centerPi = 0x3A, PiEw = 0x29, centerVref = 0x42, vrefHeight = 0x26
N3: GlobalEarlyConfig
N4.C1.S24: VmseWriteTraining Final: centerPi = 0x3A, PiEw = 0x26, centerVref = 0x3D, vrefHeight = 0x28
N6.C1.S05: VmseWriteTraining Final: centerPi = 0x38, PiEw = 0x2A, centerVref = 0x40, vrefHeight = 0x2C
N0.C1.S44: VmseWriteTraining Final: centerPi = 0x40, PiEw = 0x24, centerVref = 0x3B, vrefHeight = 0x28
N3: Global Early Configuration
N4.C1.S25: VmseWriteTraining Final: centerPi = 0x3C, PiEw = 0x27, centerVref = 0x3E, vrefHeight = 0x2A
N6.C1.S06: VmseWriteTraining Final: centerPi = 0x39, PiEw = 0x2C, centerVref = 0x3C, vrefHeight = 0x2E
N0.C1.S45: VmseWriteTraining Final: centerPi = 0x40, PiEw = 0x28, centerVref = 0x42, vrefHeight = 0x26
N3.C0: GlobalEarlyConfig: mcmntChknbit.frc_mddl_on = 1
N4.C1.S26: VmseWriteTraining Final: centerPi = 0x3A, PiEw = 0x28, centerVref = 0x3C, vrefHeight = 0x2C
N6.C1.S07: VmseWriteTraining Final: centerPi = 0x39, PiEw = 0x2A, centerVref = 0x3B, vrefHeight = 0x2C
N0.C1.S46: VmseWriteTraining Final: centerPi = 0x3F, PiEw = 0x25, centerVref = 0x41, vrefHeight = 0x2A
N3.C0.D0: Config DIMMMTR_0_MCDDC_DESC_REG: 000C5051
N4.C1.S27: VmseWriteTraining Final: centerPi = 0x39, PiEw = 0x2A, centerVref = 0x3C, vrefHeight = 0x2A
N6.C1.S08: VmseWriteTraining Final: centerPi = 0x37, PiEw = 0x2B, centerVref = 0x45, vrefHeight = 0x2E
N0.C1.S47: VmseWriteTraining Final: centerPi = 0x3E, PiEw = 0x2B, centerVref = 0x44, vrefHeight = 0x2A
N3.C0: RX Vref Default = 32
N4.C1.S28: VmseWriteTraining Final: centerPi = 0x3D, PiEw = 0x20, centerVref = 0x3B, vrefHeight = 0x20
N6.C1.S09: VmseWriteTraining Final: centerPi = 0x3C, PiEw = 0x28, centerVref = 0x3D, vrefHeight = 0x30
N0.C1.S48: VmseWriteTraining Final: centerPi = 0x3D, PiEw = 0x28, centerVref = 0x41, vrefHeight = 0x24
N3.C1: GlobalEarlyConfig: mcmntChknbit.frc_mddl_on = 1
N4.C1.S29: VmseWriteTraining Final: centerPi = 0x40, PiEw = 0x21, centerVref = 0x3E, vrefHeight = 0x26
N6.C1.S10: VmseWriteTraining Final: centerPi = 0x3A, PiEw = 0x2A, centerVref = 0x3F, vrefHeight = 0x30
N0.C1.S49: VmseWriteTraining Final: centerPi = 0x3E, PiEw = 0x28, centerVref = 0x39, vrefHeight = 0x28
N3.C1.D0: Config DIMMMTR_0_MCDDC_DESC_REG: 000C5051
N4.C1.S30: VmseWriteTraining Final: centerPi = 0x3E, PiEw = 0x23, centerVref = 0x41, vrefHeight = 0x2A
N6.C1.S11: VmseWriteTraining Final: centerPi = 0x36, PiEw = 0x29, centerVref = 0x43, vrefHeight = 0x2C
N0.C1.S50: VmseWriteTraining Final: centerPi = 0x3C, PiEw = 0x25, centerVref = 0x40, vrefHeight = 0x28
N3.C1: RX Vref Default = 32
N4.C1.S31: VmseWriteTraining Final: centerPi = 0x3D, PiEw = 0x26, centerVref = 0x3B, vrefHeight = 0x24
N6.C1.S12: VmseWriteTraining Final: centerPi = 0x40, PiEw = 0x27, centerVref = 0x3C, vrefHeight = 0x2E
N0.C1.S51: VmseWriteTraining Final: centerPi = 0x3C, PiEw = 0x2A, centerVref = 0x40, vrefHeight = 0x2A
N3.C2: GlobalEarlyConfig: mcmntChknbit.frc_mddl_on = 1
N4.C1.S32: VmseWriteTraining Final: centerPi = 0x38, PiEw = 0x26, centerVref = 0x3D, vrefHeight = 0x26
N6.C1.S13: VmseWriteTraining Final: centerPi = 0x3D, PiEw = 0x27, centerVref = 0x41, vrefHeight = 0x2E
N0.C1.S52: VmseWriteTraining Final: centerPi = 0x41, PiEw = 0x26, centerVref = 0x41, vrefHeight = 0x28
N3.C2.D0: Config DIMMMTR_0_MCDDC_DESC_REG: 000C5051
N4.C1.S33: VmseWriteTraining Final: centerPi = 0x38, PiEw = 0x29, centerVref = 0x3F, vrefHeight = 0x28
N6.C1.S14: VmseWriteTraining Final: centerPi = 0x3F, PiEw = 0x26, centerVref = 0x3B, vrefHeight = 0x30
N0.C1.S53: VmseWriteTraining Final: centerPi = 0x41, PiEw = 0x29, centerVref = 0x3D, vrefHeight = 0x24
N3.C2: RX Vref Default = 32
N4.C1.S34: VmseWriteTraining Final: centerPi = 0x38, PiEw = 0x24, centerVref = 0x3F, vrefHeight = 0x2C
N6.C1.S15: VmseWriteTraining Final: centerPi = 0x3C, PiEw = 0x2C, centerVref = 0x40, vrefHeight = 0x2E
N0.C1.S54: VmseWriteTraining Final: centerPi = 0x40, PiEw = 0x26, centerVref = 0x3F, vrefHeight = 0x28
N3.C3: GlobalEarlyConfig: mcmntChknbit.frc_mddl_on = 1
N4.C1.S35: VmseWriteTraining Final: centerPi = 0x37, PiEw = 0x29, centerVref = 0x40, vrefHeight = 0x2E
N6.C1.S16: VmseWriteTraining Final: centerPi = 0x37, PiEw = 0x29, centerVref = 0x41, vrefHeight = 0x2C
N0.C1.S55: VmseWriteTraining Final: centerPi = 0x40, PiEw = 0x27, centerVref = 0x3F, vrefHeight = 0x28
N3.C3.D0: Config DIMMMTR_0_MCDDC_DESC_REG: 000C5051
N4.C1.S36: VmseWriteTraining Final: centerPi = 0x3F, PiEw = 0x28, centerVref = 0x3E, vrefHeight = 0x2A
N6.C1.S17: VmseWriteTraining Final: centerPi = 0x34, PiEw = 0x27, centerVref = 0x42, vrefHeight = 0x28
N0.C1.S56: VmseWriteTraining Final: centerPi = 0x3C, PiEw = 0x28, centerVref = 0x3F, vrefHeight = 0x28
N3.C3: RX Vref Default = 32
N4.C1.S37: VmseWriteTraining Final: centerPi = 0x3C, PiEw = 0x28, centerVref = 0x42, vrefHeight = 0x28
N6.C1.S18: VmseWriteTraining Final: centerPi = 0x39, PiEw = 0x27, centerVref = 0x3F, vrefHeight = 0x30
N0.C1.S57: VmseWriteTraining Final: centerPi = 0x3D, PiEw = 0x29, centerVref = 0x42, vrefHeight = 0x2A
N3: ChannelEarlyConfig
N4.C1.S38: VmseWriteTraining Final: centerPi = 0x3B, PiEw = 0x26, centerVref = 0x3C, vrefHeight = 0x2A
N6.C1.S19: VmseWriteTraining Final: centerPi = 0x35, PiEw = 0x2B, centerVref = 0x3C, vrefHeight = 0x2E
N0.C1.S58: VmseWriteTraining Final: centerPi = 0x3C, PiEw = 0x2B, centerVref = 0x42, vrefHeight = 0x2A
N3: Channel Early Configuration
N4.C1.S39: VmseWriteTraining Final: centerPi = 0x3B, PiEw = 0x26, centerVref = 0x3E, vrefHeight = 0x28
N6.C1.S20: VmseWriteTraining Final: centerPi = 0x39, PiEw = 0x28, centerVref = 0x3F, vrefHeight = 0x2C
N0.C1.S59: VmseWriteTraining Final: centerPi = 0x3B, PiEw = 0x29, centerVref = 0x3E, vrefHeight = 0x2A
N3.C0: Enable = 1
N4.C1.S40: VmseWriteTraining Final: centerPi = 0x3B, PiEw = 0x25, centerVref = 0x3F, vrefHeight = 0x28
N6.C1.S21: VmseWriteTraining Final: centerPi = 0x3A, PiEw = 0x26, centerVref = 0x3C, vrefHeight = 0x2C
N0.C1.S60: VmseWriteTraining Final: centerPi = 0x40, PiEw = 0x28, centerVref = 0x3D, vrefHeight = 0x28
N3.C0.D0: Enable = 1
N4.C1.S41: VmseWriteTraining Final: centerPi = 0x3C, PiEw = 0x2A, centerVref = 0x3E, vrefHeight = 0x2A
N6.C1.S22: VmseWriteTraining Final: centerPi = 0x38, PiEw = 0x27, centerVref = 0x3B, vrefHeight = 0x28
N0.C1.S61: VmseWriteTraining Final: centerPi = 0x40, PiEw = 0x27, centerVref = 0x42, vrefHeight = 0x26
N3.C0.D0.R0: Enable = 1
N4.C1.S42: VmseWriteTraining Final: centerPi = 0x37, PiEw = 0x26, centerVref = 0x3A, vrefHeight = 0x28
N6.C1.S23: VmseWriteTraining Final: centerPi = 0x3B, PiEw = 0x29, centerVref = 0x3C, vrefHeight = 0x2E
N0.C1.S62: VmseWriteTraining Final: centerPi = 0x40, PiEw = 0x2A, centerVref = 0x3E, vrefHeight = 0x28
N3.C0.D0.R0: ENABLED: ckeMask = 00000001
N4.C1.S43: VmseWriteTraining Final: centerPi = 0x38, PiEw = 0x27, centerVref = 0x3D, vrefHeight = 0x2A
N6.C1.S24: VmseWriteTraining Final: centerPi = 0x3B, PiEw = 0x26, centerVref = 0x41, vrefHeight = 0x2E
N0.C1.S63: VmseWriteTraining Final: centerPi = 0x40, PiEw = 0x2A, centerVref = 0x40, vrefHeight = 0x2A
N3.C0.D0.R1: Enable = 1
N4.C1.S44: VmseWriteTraining Final: centerPi = 0x3D, PiEw = 0x25, centerVref = 0x3C, vrefHeight = 0x2C
N6.C1.S25: VmseWriteTraining Final: centerPi = 0x39, PiEw = 0x2A, centerVref = 0x3F, vrefHeight = 0x2E
N0.C1.S64: VmseWriteTraining Final: centerPi = 0x3A, PiEw = 0x24, centerVref = 0x42, vrefHeight = 0x26
N3.C0.D0.R1: ENABLED: ckeMask = 00000003
N4.C1.S45: VmseWriteTraining Final: centerPi = 0x3A, PiEw = 0x28, centerVref = 0x40, vrefHeight = 0x26
N6.C1.S26: VmseWriteTraining Final: centerPi = 0x3C, PiEw = 0x23, centerVref = 0x3A, vrefHeight = 0x32
N0.C1.S65: VmseWriteTraining Final: centerPi = 0x37, PiEw = 0x24, centerVref = 0x3F, vrefHeight = 0x24
N3.C0.D0.R2: Enable = 0
N4.C1.S46: VmseWriteTraining Final: centerPi = 0x41, PiEw = 0x20, centerVref = 0x3A, vrefHeight = 0x2C
N6.C1.S27: VmseWriteTraining Final: centerPi = 0x39, PiEw = 0x29, centerVref = 0x3B, vrefHeight = 0x2E
N0.C1.S66: VmseWriteTraining Final: centerPi = 0x39, PiEw = 0x22, centerVref = 0x3E, vrefHeight = 0x26
N3.C0.D0.R3: Enable = 0
N4.C1.S47: VmseWriteTraining Final: centerPi = 0x3B, PiEw = 0x2C, centerVref = 0x42, vrefHeight = 0x28
N6.C1.S28: VmseWriteTraining Final: centerPi = 0x3F, PiEw = 0x1E, centerVref = 0x35, vrefHeight = 0x28
N0.C1.S67: VmseWriteTraining Final: centerPi = 0x3A, PiEw = 0x23, centerVref = 0x3D, vrefHeight = 0x2C
N3.C0.D1: Enable = 0
N4.C1.S48: VmseWriteTraining Final: centerPi = 0x38, PiEw = 0x29, centerVref = 0x45, vrefHeight = 0x24
N6.C1.S29: VmseWriteTraining Final: centerPi = 0x3B, PiEw = 0x25, centerVref = 0x3D, vrefHeight = 0x28
N0.C1.S68: VmseWriteTraining Final: centerPi = 0x3F, PiEw = 0x27, centerVref = 0x3C, vrefHeight = 0x2A
N3.C0.D2: Enable = 0
N4.C1.S49: VmseWriteTraining Final: centerPi = 0x40, PiEw = 0x25, centerVref = 0x3A, vrefHeight = 0x2A
N6.C1.S30: VmseWriteTraining Final: centerPi = 0x41, PiEw = 0x27, centerVref = 0x3D, vrefHeight = 0x30
N0.C1.S69: VmseWriteTraining Final: centerPi = 0x3E, PiEw = 0x24, centerVref = 0x43, vrefHeight = 0x28
N3.C1: Enable = 1
N4.C1.S50: VmseWriteTraining Final: centerPi = 0x3A, PiEw = 0x2A, centerVref = 0x40, vrefHeight = 0x28
N6.C1.S31: VmseWriteTraining Final: centerPi = 0x3E, PiEw = 0x27, centerVref = 0x39, vrefHeight = 0x2C
N0.C1.S70: VmseWriteTraining Final: centerPi = 0x3D, PiEw = 0x24, centerVref = 0x40, vrefHeight = 0x2A
N3.C1.D0: Enable = 1
N4.C1.S51: VmseWriteTraining Final: centerPi = 0x3B, PiEw = 0x2B, centerVref = 0x3F, vrefHeight = 0x2C
N6.C1.S32: VmseWriteTraining Final: centerPi = 0x3F, PiEw = 0x23, centerVref = 0x3C, vrefHeight = 0x2C
N0.C1.S71: VmseWriteTraining Final: centerPi = 0x3D, PiEw = 0x27, centerVref = 0x3F, vrefHeight = 0x28
N3.C1.D0.R0: Enable = 1
N4.C1.S52: VmseWriteTraining Final: centerPi = 0x43, PiEw = 0x24, centerVref = 0x3B, vrefHeight = 0x2C
N6.C1.S33: VmseWriteTraining Final: centerPi = 0x38, PiEw = 0x2D, centerVref = 0x42, vrefHeight = 0x2C

END - VMSE Train Write                 Time         3794 ms
N3.C1.D0.R0: ENABLED: ckeMask = 00000001
N4.C1.S53: VmseWriteTraining Final: centerPi = 0x40, PiEw = 0x29, centerVref = 0x3E, vrefHeight = 0x26
N6.C1.S34: VmseWriteTraining Final: centerPi = 0x3F, PiEw = 0x24, centerVref = 0x39, vrefHeight = 0x30
Checkpoint Code: Socket 0, 0xB6, 0x64, 0x0000
N3.C1.D0.R1: Enable = 1
N4.C1.S54: VmseWriteTraining Final: centerPi = 0x3D, PiEw = 0x27, centerVref = 0x40, vrefHeight = 0x2A
N6.C1.S35: VmseWriteTraining Final: centerPi = 0x3C, PiEw = 0x2A, centerVref = 0x3B, vrefHeight = 0x30
N0: 
Total VMSE trainings latency = 15621 ms
N3.C1.D0.R1: ENABLED: ckeMask = 00000003
N4.C1.S55: VmseWriteTraining Final: centerPi = 0x3E, PiEw = 0x25, centerVref = 0x3F, vrefHeight = 0x28
N6.C1.S36: VmseWriteTraining Final: centerPi = 0x3E, PiEw = 0x25, centerVref = 0x41, vrefHeight = 0x2E
Checkpoint Code: Socket 0, 0xB5, 0x00, 0x0000
N3.C1.D0.R2: Enable = 0
N4.C1.S56: VmseWriteTraining Final: centerPi = 0x3C, PiEw = 0x27, centerVref = 0x3E, vrefHeight = 0x26
N6.C1.S37: VmseWriteTraining Final: centerPi = 0x3D, PiEw = 0x28, centerVref = 0x3E, vrefHeight = 0x2A
N1: GatherSPDData
N3.C1.D0.R3: Enable = 0
N4.C1.S57: VmseWriteTraining Final: centerPi = 0x3D, PiEw = 0x29, centerVref = 0x43, vrefHeight = 0x28
N6.C1.S38: VmseWriteTraining Final: centerPi = 0x3E, PiEw = 0x27, centerVref = 0x3C, vrefHeight = 0x2E
Gather SPD Data
N3.C1.D1: Enable = 0
N4.C1.S58: VmseWriteTraining Final: centerPi = 0x3F, PiEw = 0x25, centerVref = 0x3A, vrefHeight = 0x2A
N6.C1.S39: VmseWriteTraining Final: centerPi = 0x42, PiEw = 0x26, centerVref = 0x3F, vrefHeight = 0x2E
N1.C0.D0: tWR in MTB units: 0x78
N3.C1.D2: Enable = 0
N4.C1.S59: VmseWriteTraining Final: centerPi = 0x3C, PiEw = 0x25, centerVref = 0x40, vrefHeight = 0x28
N6.C1.S40: VmseWriteTraining Final: centerPi = 0x3E, PiEw = 0x26, centerVref = 0x40, vrefHeight = 0x2E
N1.C1.D0: tWR in MTB units: 0x78
N3.C2: Enable = 1
N4.C1.S60: VmseWriteTraining Final: centerPi = 0x43, PiEw = 0x24, centerVref = 0x3B, vrefHeight = 0x28
N6.C1.S41: VmseWriteTraining Final: centerPi = 0x3E, PiEw = 0x2A, centerVref = 0x3B, vrefHeight = 0x30
N1.C2.D0: tWR in MTB units: 0x78
N3.C2.D0: Enable = 1
N4.C1.S61: VmseWriteTraining Final: centerPi = 0x3F, PiEw = 0x26, centerVref = 0x3E, vrefHeight = 0x26
N6.C1.S42: VmseWriteTraining Final: centerPi = 0x3F, PiEw = 0x23, centerVref = 0x34, vrefHeight = 0x32
N1.C3.D0: tWR in MTB units: 0x78
N3.C2.D0.R0: Enable = 1
N4.C1.S62: VmseWriteTraining Final: centerPi = 0x41, PiEw = 0x29, centerVref = 0x3C, vrefHeight = 0x2A
N6.C1.S43: VmseWriteTraining Final: centerPi = 0x3E, PiEw = 0x23, centerVref = 0x3C, vrefHeight = 0x30

GatherSPDData time            128 ms
N3.C2.D0.R0: ENABLED: ckeMask = 00000001
N4.C1.S63: VmseWriteTraining Final: centerPi = 0x41, PiEw = 0x25, centerVref = 0x42, vrefHeight = 0x28
N6.C1.S44: VmseWriteTraining Final: centerPi = 0x3F, PiEw = 0x26, centerVref = 0x3D, vrefHeight = 0x2E
N1: GlobalEarlyConfig
N3.C2.D0.R1: Enable = 1
N4.C1.S64: VmseWriteTraining Final: centerPi = 0x37, PiEw = 0x29, centerVref = 0x3F, vrefHeight = 0x24
N6.C1.S45: VmseWriteTraining Final: centerPi = 0x41, PiEw = 0x25, centerVref = 0x3C, vrefHeight = 0x2E
N1: Global Early Configuration
N3.C2.D0.R1: ENABLED: ckeMask = 00000003
N4.C1.S65: VmseWriteTraining Final: centerPi = 0x36, PiEw = 0x23, centerVref = 0x40, vrefHeight = 0x24
N6.C1.S46: VmseWriteTraining Final: centerPi = 0x3D, PiEw = 0x2B, centerVref = 0x3F, vrefHeight = 0x30
N1.C0: GlobalEarlyConfig: mcmntChknbit.frc_mddl_on = 1
N3.C2.D0.R2: Enable = 0
N4.C1.S66: VmseWriteTraining Final: centerPi = 0x35, PiEw = 0x27, centerVref = 0x41, vrefHeight = 0x24
N6.C1.S47: VmseWriteTraining Final: centerPi = 0x3F, PiEw = 0x29, centerVref = 0x44, vrefHeight = 0x2C
N1.C0.D0: Config DIMMMTR_0_MCDDC_DESC_REG: 000C5051
N3.C2.D0.R3: Enable = 0
N4.C1.S67: VmseWriteTraining Final: centerPi = 0x3A, PiEw = 0x23, centerVref = 0x3D, vrefHeight = 0x2A
N6.C1.S48: VmseWriteTraining Final: centerPi = 0x3B, PiEw = 0x28, centerVref = 0x44, vrefHeight = 0x28
N1.C0: RX Vref Default = 32
N3.C2.D1: Enable = 0
N4.C1.S68: VmseWriteTraining Final: centerPi = 0x3E, PiEw = 0x27, centerVref = 0x45, vrefHeight = 0x28
N6.C1.S49: VmseWriteTraining Final: centerPi = 0x3D, PiEw = 0x2A, centerVref = 0x3B, vrefHeight = 0x30
N1.C1: GlobalEarlyConfig: mcmntChknbit.frc_mddl_on = 1
N3.C2.D2: Enable = 0
N4.C1.S69: VmseWriteTraining Final: centerPi = 0x3D, PiEw = 0x23, centerVref = 0x3E, vrefHeight = 0x28
N6.C1.S50: VmseWriteTraining Final: centerPi = 0x3C, PiEw = 0x27, centerVref = 0x40, vrefHeight = 0x30
N1.C1.D0: Config DIMMMTR_0_MCDDC_DESC_REG: 000C5051
N3.C3: Enable = 1
N4.C1.S70: VmseWriteTraining Final: centerPi = 0x3D, PiEw = 0x26, centerVref = 0x3F, vrefHeight = 0x2C
N6.C1.S51: VmseWriteTraining Final: centerPi = 0x38, PiEw = 0x2A, centerVref = 0x3E, vrefHeight = 0x30
N1.C1: RX Vref Default = 32
N3.C3.D0: Enable = 1
N4.C1.S71: VmseWriteTraining Final: centerPi = 0x3C, PiEw = 0x26, centerVref = 0x3C, vrefHeight = 0x26
N6.C1.S52: VmseWriteTraining Final: centerPi = 0x40, PiEw = 0x27, centerVref = 0x3E, vrefHeight = 0x2E
N1.C2: GlobalEarlyConfig: mcmntChknbit.frc_mddl_on = 1
N3.C3.D0.R0: Enable = 1

END - VMSE Train Write                 Time         4020 ms
N6.C1.S53: VmseWriteTraining Final: centerPi = 0x3D, PiEw = 0x27, centerVref = 0x3B, vrefHeight = 0x2A
N1.C2.D0: Config DIMMMTR_0_MCDDC_DESC_REG: 000C5051
N3.C3.D0.R0: ENABLED: ckeMask = 00000001
N4: 
Total VMSE trainings latency = 15953 ms
N6.C1.S54: VmseWriteTraining Final: centerPi = 0x3F, PiEw = 0x27, centerVref = 0x3D, vrefHeight = 0x2E
N1.C2: RX Vref Default = 32
N3.C3.D0.R1: Enable = 1
N5: GatherSPDData
N6.C1.S55: VmseWriteTraining Final: centerPi = 0x3E, PiEw = 0x28, centerVref = 0x41, vrefHeight = 0x2C
N1.C3: GlobalEarlyConfig: mcmntChknbit.frc_mddl_on = 1
N3.C3.D0.R1: ENABLED: ckeMask = 00000003
Gather SPD Data
N6.C1.S56: VmseWriteTraining Final: centerPi = 0x39, PiEw = 0x2A, centerVref = 0x45, vrefHeight = 0x2C
N1.C3.D0: Config DIMMMTR_0_MCDDC_DESC_REG: 000C5051
N3.C3.D0.R2: Enable = 0
N5.C0.D0: tWR in MTB units: 0x78
N6.C1.S57: VmseWriteTraining Final: centerPi = 0x3A, PiEw = 0x2B, centerVref = 0x38, vrefHeight = 0x2E
N1.C3: RX Vref Default = 32
N3.C3.D0.R3: Enable = 0
N6.C1.S58: VmseWriteTraining Final: centerPi = 0x3A, PiEw = 0x2B, centerVref = 0x3F, vrefHeight = 0x2C
Checkpoint Code: Socket 0, 0xB8, 0x00, 0x0000
N3.C3.D1: Enable = 0
N5.C1.D0: tWR in MTB units: 0x78
N6.C1.S59: VmseWriteTraining Final: centerPi = 0x39, PiEw = 0x2D, centerVref = 0x3E, vrefHeight = 0x2E
N1: ChannelEarlyConfig
N3.C3.D2: Enable = 0
N6.C1.S60: VmseWriteTraining Final: centerPi = 0x40, PiEw = 0x26, centerVref = 0x39, vrefHeight = 0x2E
N1: Channel Early Configuration
N3: Memory Timings:
N5.C2.D0: tWR in MTB units: 0x78
N6.C1.S61: VmseWriteTraining Final: centerPi = 0x3E, PiEw = 0x24, centerVref = 0x41, vrefHeight = 0x2C
N1.C0: Enable = 1
N3.C0: nCL = 9
N6.C1.S62: VmseWriteTraining Final: centerPi = 0x3F, PiEw = 0x27, centerVref = 0x43, vrefHeight = 0x30
N1.C0.D0: Enable = 1
N3.C0: nCWL = 7
N5.C3.D0: tWR in MTB units: 0x78
N6.C1.S63: VmseWriteTraining Final: centerPi = 0x3F, PiEw = 0x28, centerVref = 0x41, vrefHeight = 0x2E
N1.C0.D0.R0: Enable = 1
N3.C0: nRP = 9
N6.C1.S64: VmseWriteTraining Final: centerPi = 0x39, PiEw = 0x26, centerVref = 0x40, vrefHeight = 0x2E
N1.C0.D0.R0: ENABLED: ckeMask = 00000001
N3.C0: nRCD = 9

GatherSPDData time            148 ms
N6.C1.S65: VmseWriteTraining Final: centerPi = 0x37, PiEw = 0x24, centerVref = 0x3E, vrefHeight = 0x2A
N1.C0.D0.R1: Enable = 1
N3.C0: nRRD = 4
N5: GlobalEarlyConfig
N6.C1.S66: VmseWriteTraining Final: centerPi = 0x39, PiEw = 0x20, centerVref = 0x3C, vrefHeight = 0x2A
N1.C0.D0.R1: ENABLED: ckeMask = 00000003
N3.C0: nWTR = 5
N5: Global Early Configuration
N6.C1.S67: VmseWriteTraining Final: centerPi = 0x3B, PiEw = 0x26, centerVref = 0x3E, vrefHeight = 0x2E
N1.C0.D0.R2: Enable = 0
N3.C0: nRAS = 24
N5.C0: GlobalEarlyConfig: mcmntChknbit.frc_mddl_on = 1
N6.C1.S68: VmseWriteTraining Final: centerPi = 0x3E, PiEw = 0x25, centerVref = 0x40, vrefHeight = 0x2A
N1.C0.D0.R3: Enable = 0
N3.C0: nRTP = 5
N5.C0.D0: Config DIMMMTR_0_MCDDC_DESC_REG: 000C5051
N6.C1.S69: VmseWriteTraining Final: centerPi = 0x3E, PiEw = 0x23, centerVref = 0x3D, vrefHeight = 0x2C
N1.C0.D1: Enable = 0
N3.C0: nWR = 10
N5.C0: RX Vref Default = 32
N6.C1.S70: VmseWriteTraining Final: centerPi = 0x3F, PiEw = 0x23, centerVref = 0x3A, vrefHeight = 0x2E
N1.C0.D2: Enable = 0
N3.C0: nFAW = 20
N5.C1: GlobalEarlyConfig: mcmntChknbit.frc_mddl_on = 1
N6.C1.S71: VmseWriteTraining Final: centerPi = 0x3E, PiEw = 0x26, centerVref = 0x41, vrefHeight = 0x2C
N1.C1: Enable = 1
N3.C0: nRC = 33
N5.C1.D0: Config DIMMMTR_0_MCDDC_DESC_REG: 000C5051

END - VMSE Train Write                 Time         4009 ms
N1.C1.D0: Enable = 1
N3.C0: nRFC = 174
N5.C1: RX Vref Default = 32
N6: 
Total VMSE trainings latency = 16458 ms
N1.C1.D0.R0: Enable = 1
N3.C0: casSup = 0xFC
N5.C2: GlobalEarlyConfig: mcmntChknbit.frc_mddl_on = 1
N7: GatherSPDData
N1.C1.D0.R0: ENABLED: ckeMask = 00000001
N3.C0: trrMode = 0
N5.C2.D0: Config DIMMMTR_0_MCDDC_DESC_REG: 000C5051
Gather SPD Data
N1.C1.D0.R1: Enable = 1
N3.C0: twoXRefresh = 0
N5.C2: RX Vref Default = 32
N7.C0.D0: tWR in MTB units: 0x78
N1.C1.D0.R1: ENABLED: ckeMask = 00000003
N3.C0: t_stagger_ref = 0x86
N5.C3: GlobalEarlyConfig: mcmntChknbit.frc_mddl_on = 1
N1.C1.D0.R2: Enable = 0
N3.C0: tcsrftp.Bits.t_xsdll = 512
N5.C3.D0: Config DIMMMTR_0_MCDDC_DESC_REG: 000C5051
N7.C1.D0: tWR in MTB units: 0x78
N1.C1.D0.R3: Enable = 0
N3.C0: Common CL = 9
Common CWL = 7
N5.C3: RX Vref Default = 32
N1.C1.D1: Enable = 0
N3: Memory Timings:
N5: ChannelEarlyConfig
N1.C1.D2: Enable = 0
N3.C1: nCL = 9
N5: Channel Early Configuration
N7.C2.D0: tWR in MTB units: 0x78
N1.C2: Enable = 1
N3.C1: nCWL = 7
N5.C0: Enable = 1
N1.C2.D0: Enable = 1
N3.C1: nRP = 9
N5.C0.D0: Enable = 1
N1.C2.D0.R0: Enable = 1
N3.C1: nRCD = 9
N5.C0.D0.R0: Enable = 1
N1.C2.D0.R0: ENABLED: ckeMask = 00000001
N3.C1: nRRD = 4
N5.C0.D0.R0: ENABLED: ckeMask = 00000001
N7.C3.D0: tWR in MTB units: 0x78
N1.C2.D0.R1: Enable = 1
N3.C1: nWTR = 5
N5.C0.D0.R1: Enable = 1
N1.C2.D0.R1: ENABLED: ckeMask = 00000003
N3.C1: nRAS = 24
N5.C0.D0.R1: ENABLED: ckeMask = 00000003

GatherSPDData time            119 ms
N1.C2.D0.R2: Enable = 0
N3.C1: nRTP = 5
N5.C0.D0.R2: Enable = 0
N7: GlobalEarlyConfig
N1.C2.D0.R3: Enable = 0
N3.C1: nWR = 10
N5.C0.D0.R3: Enable = 0
N7: Global Early Configuration
N1.C2.D1: Enable = 0
N3.C1: nFAW = 20
N5.C0.D1: Enable = 0
N7.C0: GlobalEarlyConfig: mcmntChknbit.frc_mddl_on = 1
N1.C2.D2: Enable = 0
N3.C1: nRC = 33
N5.C0.D2: Enable = 0
N7.C0.D0: Config DIMMMTR_0_MCDDC_DESC_REG: 000C5051
N1.C3: Enable = 1
N3.C1: nRFC = 174
N5.C1: Enable = 1
N7.C0: RX Vref Default = 32
N1.C3.D0: Enable = 1
N3.C1: casSup = 0xFC
N5.C1.D0: Enable = 1
N7.C1: GlobalEarlyConfig: mcmntChknbit.frc_mddl_on = 1
N1.C3.D0.R0: Enable = 1
N3.C1: trrMode = 0
N5.C1.D0.R0: Enable = 1
N7.C1.D0: Config DIMMMTR_0_MCDDC_DESC_REG: 000C5051
N1.C3.D0.R0: ENABLED: ckeMask = 00000001
N3.C1: twoXRefresh = 0
N5.C1.D0.R0: ENABLED: ckeMask = 00000001
N7.C1: RX Vref Default = 32
N1.C3.D0.R1: Enable = 1
N3.C1: t_stagger_ref = 0x86
N5.C1.D0.R1: Enable = 1
N7.C2: GlobalEarlyConfig: mcmntChknbit.frc_mddl_on = 1
N1.C3.D0.R1: ENABLED: ckeMask = 00000003
N3.C1: tcsrftp.Bits.t_xsdll = 512
N5.C1.D0.R1: ENABLED: ckeMask = 00000003
N7.C2.D0: Config DIMMMTR_0_MCDDC_DESC_REG: 000C5051
N1.C3.D0.R2: Enable = 0
N3.C1: Common CL = 9
Common CWL = 7
N5.C1.D0.R2: Enable = 0
N7.C2: RX Vref Default = 32
N1.C3.D0.R3: Enable = 0
N3: Memory Timings:
N5.C1.D0.R3: Enable = 0
N7.C3: GlobalEarlyConfig: mcmntChknbit.frc_mddl_on = 1
N1.C3.D1: Enable = 0
N3.C2: nCL = 9
N5.C1.D1: Enable = 0
N7.C3.D0: Config DIMMMTR_0_MCDDC_DESC_REG: 000C5051
N1.C3.D2: Enable = 0
N3.C2: nCWL = 7
N5.C1.D2: Enable = 0
N7.C3: RX Vref Default = 32
N1: Memory Timings:
N3.C2: nRP = 9
N5.C2: Enable = 1
N7: ChannelEarlyConfig
N1.C0: nCL = 9
N3.C2: nRCD = 9
N5.C2.D0: Enable = 1
N7: Channel Early Configuration
N1.C0: nCWL = 7
N3.C2: nRRD = 4
N5.C2.D0.R0: Enable = 1
N7.C0: Enable = 1
N1.C0: nRP = 9
N3.C2: nWTR = 5
N5.C2.D0.R0: ENABLED: ckeMask = 00000001
N7.C0.D0: Enable = 1
N1.C0: nRCD = 9
N3.C2: nRAS = 24
N5.C2.D0.R1: Enable = 1
N7.C0.D0.R0: Enable = 1
N1.C0: nRRD = 4
N3.C2: nRTP = 5
N5.C2.D0.R1: ENABLED: ckeMask = 00000003
N7.C0.D0.R0: ENABLED: ckeMask = 00000001
N1.C0: nWTR = 5
N3.C2: nWR = 10
N5.C2.D0.R2: Enable = 0
N7.C0.D0.R1: Enable = 1
N1.C0: nRAS = 24
N3.C2: nFAW = 20
N5.C2.D0.R3: Enable = 0
N7.C0.D0.R1: ENABLED: ckeMask = 00000003
N1.C0: nRTP = 5
N3.C2: nRC = 33
N5.C2.D1: Enable = 0
N7.C0.D0.R2: Enable = 0
N1.C0: nWR = 10
N3.C2: nRFC = 174
N5.C2.D2: Enable = 0
N7.C0.D0.R3: Enable = 0
N1.C0: nFAW = 20
N3.C2: casSup = 0xFC
N5.C3: Enable = 1
N7.C0.D1: Enable = 0
N1.C0: nRC = 33
N3.C2: trrMode = 0
N5.C3.D0: Enable = 1
N7.C0.D2: Enable = 0
N1.C0: nRFC = 174
N3.C2: twoXRefresh = 0
N5.C3.D0.R0: Enable = 1
N7.C1: Enable = 1
N1.C0: casSup = 0xFC
N3.C2: t_stagger_ref = 0x86
N5.C3.D0.R0: ENABLED: ckeMask = 00000001
N7.C1.D0: Enable = 1
N1.C0: trrMode = 0
N3.C2: tcsrftp.Bits.t_xsdll = 512
N5.C3.D0.R1: Enable = 1
N7.C1.D0.R0: Enable = 1
N1.C0: twoXRefresh = 0
N3.C2: Common CL = 9
Common CWL = 7
N5.C3.D0.R1: ENABLED: ckeMask = 00000003
N7.C1.D0.R0: ENABLED: ckeMask = 00000001
N1.C0: t_stagger_ref = 0x86
N3: Memory Timings:
N5.C3.D0.R2: Enable = 0
N7.C1.D0.R1: Enable = 1
N1.C0: tcsrftp.Bits.t_xsdll = 512
N3.C3: nCL = 9
N5.C3.D0.R3: Enable = 0
N7.C1.D0.R1: ENABLED: ckeMask = 00000003
N1.C0: Common CL = 9
Common CWL = 7
N3.C3: nCWL = 7
N5.C3.D1: Enable = 0
N7.C1.D0.R2: Enable = 0
N1: Memory Timings:
N3.C3: nRP = 9
N5.C3.D2: Enable = 0
N7.C1.D0.R3: Enable = 0
N1.C1: nCL = 9
N3.C3: nRCD = 9
N5: Memory Timings:
N7.C1.D1: Enable = 0
N1.C1: nCWL = 7
N3.C3: nRRD = 4
N5.C0: nCL = 9
N7.C1.D2: Enable = 0
N1.C1: nRP = 9
N3.C3: nWTR = 5
N5.C0: nCWL = 7
N7.C2: Enable = 1
N1.C1: nRCD = 9
N3.C3: nRAS = 24
N5.C0: nRP = 9
N7.C2.D0: Enable = 1
N1.C1: nRRD = 4
N3.C3: nRTP = 5
N5.C0: nRCD = 9
N7.C2.D0.R0: Enable = 1
N1.C1: nWTR = 5
N3.C3: nWR = 10
N5.C0: nRRD = 4
N7.C2.D0.R0: ENABLED: ckeMask = 00000001
N1.C1: nRAS = 24
N3.C3: nFAW = 20
N5.C0: nWTR = 5
N7.C2.D0.R1: Enable = 1
N1.C1: nRTP = 5
N3.C3: nRC = 33
N5.C0: nRAS = 24
N7.C2.D0.R1: ENABLED: ckeMask = 00000003
N1.C1: nWR = 10
N3.C3: nRFC = 174
N5.C0: nRTP = 5
N7.C2.D0.R2: Enable = 0
N1.C1: nFAW = 20
N3.C3: casSup = 0xFC
N5.C0: nWR = 10
N7.C2.D0.R3: Enable = 0
N1.C1: nRC = 33
N3.C3: trrMode = 0
N5.C0: nFAW = 20
N7.C2.D1: Enable = 0
N1.C1: nRFC = 174
N3.C3: twoXRefresh = 0
N5.C0: nRC = 33
N7.C2.D2: Enable = 0
N1.C1: casSup = 0xFC
N3.C3: t_stagger_ref = 0x86
N5.C0: nRFC = 174
N7.C3: Enable = 1
N1.C1: trrMode = 0
N3.C3: tcsrftp.Bits.t_xsdll = 512
N5.C0: casSup = 0xFC
N7.C3.D0: Enable = 1
N1.C1: twoXRefresh = 0
N3.C3: Common CL = 9
Common CWL = 7
N5.C0: trrMode = 0
N7.C3.D0.R0: Enable = 1
N1.C1: t_stagger_ref = 0x86
N3: PreVmseTraining
N5.C0: twoXRefresh = 0
N7.C3.D0.R0: ENABLED: ckeMask = 00000001
N1.C1: tcsrftp.Bits.t_xsdll = 512
N3.C0: InitHostVmseCfg
N5.C0: t_stagger_ref = 0x86
N7.C3.D0.R1: Enable = 1
N1.C1: Common CL = 9
Common CWL = 7
N3.C0: vmse_wr_turnaround = 0x7 
N5.C0: tcsrftp.Bits.t_xsdll = 512
N7.C3.D0.R1: ENABLED: ckeMask = 00000003
N1: Memory Timings:
N3.C2: InitHostVmseCfg
N5.C0: Common CL = 9
Common CWL = 7
N7.C3.D0.R2: Enable = 0
N1.C2: nCL = 9
N3.C2: vmse_wr_turnaround = 0x7 
N5: Memory Timings:
N7.C3.D0.R3: Enable = 0
N1.C2: nCWL = 7
N3: HsxInitDdrioInterface
N5.C1: nCL = 9
N7.C3.D1: Enable = 0
N1.C2: nRP = 9
N3.C0: rxVref = 0x5F
N5.C1: nCWL = 7
N7.C3.D2: Enable = 0
N1.C2: nRCD = 9
N3.C1: rxVref = 0x5F
N5.C1: nRP = 9
N7: Memory Timings:
N1.C2: nRRD = 4
N3: HsxVmseCompInit
N5.C1: nRCD = 9
N7.C0: nCL = 9
N1.C2: nWTR = 5
N3: VmseCrossoverCalib
N3: Enable xovercal
N3: vmse_modes =          1,  0
N3.C0: piDelay CMDn  CMDs  CTL  CKE  CLK   0  1  2  3  4  5  6  7  8  9 10 11 12 13 14 15 16 17
          0       0     0    0    0    0   1  1  1  0  0  0  1  1  0  1  1  1  0  0  0  1  1  0 
          1       0     0    0    0    0   1  1  1  1  0  0  1  1  0  1  1  1  1  0  0  1  1  0 
          2       0     0    0    0    0   1  1  1  1  0  1  1  1  0  1  1  1  1  0  1  1  1  0 
          3       0     0    0    0    0   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
          4       0     0    1    0    0   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
          5       0     0    1    0    0   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
          6       0     0    1    1    0   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
          7       0     0    1    1    0   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
          8       0     0    1    1    0   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
          9       0     0    1    1    0   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         10       0     0    1    1    0   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         11       0     0    1    1    0   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         12       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         13       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         14       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         15       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         16       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         17       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         18       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         19       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         20       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         21       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         22       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         23       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         24       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         25       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         26       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         27       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         28       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         29       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         30       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         31       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         32       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         33       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         34       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         35       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         36       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         37       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         38       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         39       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         40       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         41       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         42       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         43       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         44       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         45       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         46       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         47       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         48       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         49       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         50       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         51       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         52       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         53       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         54       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         55       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         56       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         57       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         58       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         59       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         60       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         61       0     0    1    1    1   0  0  1  1  1  1  1  1  1  0  0  1  1  1  1  1  1  1 
         62       0     0    1    1    1   X  X  1  1  1  1  1  1  1  X  X  1  1  1  1  1  1  1 
         63       0     0    1    1    1   X  X  1  1  1  1  1  1  1  X  X  1  1  1  1  1  1  1 
N3.C0: setting ddrcrinvertpiclk
          0       0     0    1    1    1   X  X  0  1  1  1  0  0  1  X  X  0  1  1  1  0  0  1 
          1       0     0    1    1    1   X  X  0  1  1  1  0  0  1  X  X  0  1  1  1  0  0  1 
          2       0     0    1    1    1   X  X  0  1  1  1  0  0  1  X  X  0  1  1  1  0  0  1 
          3       0     0    1    1    1   X  X  0  0  1  1  0  0  1  X  X  0  0  1  1  0  0  1 
          4       0     0    1    1    1   X  X  0  X  1  0  0  0  1  X  X  0  X  1  0  0  0  1 
          5       0     0    0    1    1   X  X  0  X  0  X  0  0  0  X  X  0  X  0  X  0  0  0 
          6       0     0    X    1    1   X  X  0  X  X  X  0  0  X  X  X  0  X  X  X  0  0  X 
          7       0     0    X    1    1   X  X  0  X  X  X  0  0  X  X  X  0  X  X  X  0  0  X 
          8       0     0    X    0    1   X  X  0  X  X  X  0  0  X  X  X  0  X  X  X  0  0  X 
          9       0     0    X    X    1   X  X  0  X  X  X  0  0  X  X  X  0  X  X  X  0  0  X 
         10       0     0    X    X    1   X  X  0  X  X  X  0  0  X  X  X  0  X  X  X  0  0  X 
         11       0     0    X    X    1   X  X  0  X  X  X  0  0  X  X  X  0  X  X  X  0  0  X 
         12       0     0    X    X    1   X  X  0  X  X  X  0  0  X  X  X  0  X  X  X  0  0  X 
         13       0     0    X    X    0   X  X  0  X  X  X  0  0  X  X  X  0  X  X  X  0  0  X 
         14       0     0    X    X    X   X  X  0  X  X  X  0  0  X  X  X  0  X  X  X  0  0  X 
         15       0     0    X    X    X   X  X  0  X  X  X  0  0  X  X  X  0  X  X  X  0  0  X 
         16       0     0    X    X    X   X  X  0  X  X  X  0  0  X  X  X  0  X  X  X  0  0  X 
         17       0     0    X    X    X   X  X  0  X  X  X  0  0  X  X  X  0  X  X  X  0  0  X 
         18       0     0    X    X    X   X  X  0  X  X  X  0  0  X  X  X  0  X  X  X  0  0  X 
         19       0     0    X    X    X   X  X  0  X  X  X  0  0  X  X  X  0  X  X  X  0  0  X 
         20       0     0    X    X    X   X  X  0  X  X  X  0  0  X  X  X  0  X  X  X  0  0  X 
         21       0     0    X    X    X   X  X  0  X  X  X  0  0  X  X  X  0  X  X  X  0  0  X 
         22       0     0    X    X    X   X  X  0  X  X  X  0  0  X  X  X  0  X  X  X  0  0  X 
         23       0     0    X    X    X   X  X  0  X  X  X  0  0  X  X  X  0  X  X  X  0  0  X 
         24       0     0    X    X    X   X  X  0  X  X  X  0  0  X  X  X  0  X  X  X  0  0  X 
         25       0     0    X    X    X   X  X  0  X  X  X  0  0  X  X  X  0  X  X  X  0  0  X 
         26       0     0    X    X    X   X  X  0  X  X  X  0  0  X  X  X  0  X  X  X  0  0  X 
         27       0     0    X    X    X   X  X  0  X  X  X  0  0  X  X  X  0  X  X  X  0  0  X 
         28       0     0    X    X    X   X  X  0  X  X  X  0  0  X  X  X  0  X  X  X  0  0  X 
         29       0     0    X    X    X   X  X  0  X  X  X  0  0  X  X  X  0  X  X  X  0  0  X 
         30       0     0    X    X    X   X  X  0  X  X  X  0  0  X  X  X  0  X  X  X  0  0  X 
         31       0     0    X    X    X   X  X  0  X  X  X  0  0  X  X  X  0  X  X  X  0  0  X 
         32       0     0    X    X    X   X  X  0  X  X  X  0  0  X  X  X  0  X  X  X  0  0  X 
         33       0     0    X    X    X   X  X  0  X  X  X  0  0  X  X  X  0  X  X  X  0  0  X 
         34       0     0    X    X    X   X  X  0  X  X  X  0  0  X  X  X  0  X  X  X  0  0  X 
         35       0     0    X    X    X   X  X  0  X  X  X  0  0  X  X  X  0  X  X  X  0  0  X 
         36       0     0    X    X    X   X  X  0  X  X  X  0  0  X  X  X  0  X  X  X  0  0  X 
         37       0     0    X    X    X   X  X  0  X  X  X  0  0  X  X  X  0  X  X  X  0  0  X 
         38       0     0    X    X    X   X  X  0  X  X  X  0  0  X  X  X  0  X  X  X  0  0  X 
         39       0     0    X    X    X   X  X  0  X  X  X  0  0  X  X  X  0  X  X  X  0  0  X 
         40       0     0    X    X    X   X  X  0  X  X  X  0  0  X  X  X  0  X  X  X  0  0  X 
         41       0     0    X    X    X   X  X  0  X  X  X  0  0  X  X  X  0  X  X  X  0  0  X 
         42       0     0    X    X    X   X  X  0  X  X  X  0  0  X  X  X  0  X  X  X  0  0  X 
         43       0     0    X    X    X   X  X  0  X  X  X  0  0  X  X  X  0  X  X  X  0  0  X 
         44       0     0    X    X    X   X  X  0  X  X  X  0  0  X  X  X  0  X  X  X  0  0  X 
         45       0     0    X    X    X   X  X  0  X  X  X  0  0  X  X  X  0  X  X  X  0  0  X 
         46       0     0    X    X    X   X  X  0  X  X  X  0  0  X  X  X  0  X  X  X  0  0  X 
         47       0     0    X    X    X   X  X  0  X  X  X  0  0  X  X  X  0  X  X  X  0  0  X 
         48       0     0    X    X    X   X  X  0  X  X  X  0  0  X  X  X  0  X  X  X  0  0  X 
         49       0     0    X    X    X   X  X  0  X  X  X  0  0  X  X  X  0  X  X  X  0  0  X 
         50       0     0    X    X    X   X  X  0  X  X  X  0  0  X  X  X  0  X  X  X  0  0  X 
         51       0     0    X    X    X   X  X  0  X  X  X  0  0  X  X  X  0  X  X  X  0  0  X 
         52       0     0    X    X    X   X  X  0  X  X  X  0  0  X  X  X  0  X  X  X  0  0  X 
         53       0     0    X    X    X   X  X  0  X  X  X  0  0  X  X  X  0  X  X  X  0  0  X 
         54       0     0    X    X    X   X  X  0  X  X  X  0  0  X  X  X  0  X  X  X  0  0  X 
         55       0     0    X    X    X   X  X  0  X  X  X  0  0  X  X  X  0  X  X  X  0  0  X 
         56       0     0    X    X    X   X  X  0  X  X  X  0  0  X  X  X  0  X  X  X  0  0  X 
         57       0     0    X    X    X   X  X  0  X  X  X  0  0  X  X  X  0  X  X  X  0  0  X 
         58       0     0    X    X    X   X  X  0  X  X  X  0  0  X  X  X  0  X  X  X  0  0  X 
         59       0     0    X    X    X   X  X  0  X  X  X  0  0  X  X  X  0  X  X  X  0  0  X 
         60       0     0    X    X    X   X  X  0  X  X  X  0  0  X  X  X  0  X  X  X  0  0  X 
         61       0     0    X    X    X   X  X  0  X  X  X  0  0  X  X  X  0  X  X  X  0  0  X 
         62       0     0    X    X    X   X  X  0  X  X  X  0  0  X  X  X  0  X  X  X  0  0  X 
         63       0     0    X    X    X   X  X  1  X  X  X  1  1  X  X  X  1  X  X  X  1  1  X 
N3.C0: CMD-N xovercal offset = 0
N3.C0: CMD-S xovercal offset = 0
N3.C0: CTL xovercal offset   = 5
N3.C0: CKE xovercal offset   = 8
N3.C0: CLK xovercal offset   = 13
N3.C0.S18: STROBE                     0   1   2   3   4   5   6   7   8   9  10  11  12  13  14  15  16  17
N3.C0.S18: Rec En xovercal offset =  61  61   0   3   5   4   0   0   5  61  61   0   3   5   4   0   0   5 
N3.C0.S18: Tx Dqs xovercal offset =  61  63   0  63  63  63   0   0  63  63  63   0  63  63  63   0   0  63 
N3.C0.S18: Tx Dq xovercal offset  =  61  61   0   3   5   4   0   0   5  61  61   0   3   5   4   0   0   5 
N3.C0:         CMDn  CMDs  CTL  CKE  CLK   0  1  2  3  4  5  6  7  8
N3.C0: offsets:  0     0     5N3: getComplexCkeSetupTime defaultOffset = 98
N3: getComplexCkeSetupTime = 98
    8   13
Ctl Offsets Delta / final ctl offset / final cke offset /  98  /  39  /  10
Cke invertpiclk / Ctl invertpiclk / 0x0  /  0x0
N3: getComplexClkSetupTime defaultOffset = 0
N3: getComplexClkSetupTime = 0
ClkSetupTime = 13
N3: getComplexDqSetupTime defaultOffset = 0
N3: getComplexDqSetupTime = 0
N3.C0.S00: txdqoffset delta = 0, dq invertpiclk = 0
N3: getComplexDqsSetupTime defaultOffset = 40
N3: getComplexDqsSetupTime = 40
N3.C0.S00: txdqsoffset delta = 40
N3: getComplexRcvEnSetupTime defaultOffset = 37
N3: getComplexRcvEnSetupTime = 37
N3.C0.S00: rcvenoffset delta = 37
N3.C0.S00: Final txdqoffset / txdqsoffset / rcvenoffset / 29 /  5 /  2
N3: getComplexDqSetupTime defaultOffset = 0
N3: getComplexDqSetupTime = 0
N3.C0.S01: txdqoffset delta = 0, dq invertpiclk = 0
N3: getComplexDqsSetupTime defaultOffset = 40
N3: getComplexDqsSetupTime = 40
N3.C0.S01: txdqsoffset delta = 40
N3: getComplexRcvEnSetupTime defaultOffset = 37
N3: getComplexRcvEnSetupTime = 37
N3.C0.S01: rcvenoffset delta = 37
N3.C0.S01: Final txdqoffset / txdqsoffset / rcvenoffset / 61 / 37 / 34
N3: getComplexDqSetupTime defaultOffset = 0
N3: getComplexDqSetupTime = 0
N3.C0.S02: txdqoffset delta = 0, dq invertpiclk = 3
N3: getComplexDqsSetupTime defaultOffset = 40
N3: getComplexDqsSetupTime = 40
N3.C0.S02: txdqsoffset delta = 40
N3: getComplexRcvEnSetupTime defaultOffset = 37
N3: getComplexRcvEnSetupTime = 37
N3.C0.S02: rcvenoffset delta = 37
N3.C0.S02: Final txdqoffset / txdqsoffset / rcvenoffset / 32 /  8 /  5
N3: getComplexDqSetupTime defaultOffset = 0
N3: getComplexDqSetupTime = 0
N3.C0.S03: txdqoffset delta = 0, dq invertpiclk = 3
N3: getComplexDqsSetupTime defaultOffset = 40
N3: getComplexDqsSetupTime = 40
N3.C0.S03: txdqsoffset delta = 40
N3: getComplexRcvEnSetupTime defaultOffset = 37
N3: getComplexRcvEnSetupTime = 37
N3.C0.S03: rcvenoffset delta = 37
N3.C0.S03: Final txdqoffset / txdqsoffset / rcvenoffset /  3 / 43 / 40
N3: getComplexDqSetupTime defaultOffset = 0
N3: getComplexDqSetupTime = 0
N3.C0.S04: txdqoffset delta = 0, dq invertpiclk = 3
N3: getComplexDqsSetupTime defaultOffset = 40
N3: getComplexDqsSetupTime = 40
N3.C0.S04: txdqsoffset delta = 40
N3: getComplexRcvEnSetupTime defaultOffset = 37
N3: getComplexRcvEnSetupTime = 37
N3.C0.S04: rcvenoffset delta = 37
N3.C0.S04: Final txdqoffset / txdqsoffset / rcvenoffset / 37 / 13 / 10
N3: getComplexDqSetupTime defaultOffset = 0
N3: getComplexDqSetupTime = 0
N3.C0.S05: txdqoffset delta = 0, dq invertpiclk = 3
N3: getComplexDqsSetupTime defaultOffset = 40
N3: getComplexDqsSetupTime = 40
N3.C0.S05: txdqsoffset delta = 40
N3: getComplexRcvEnSetupTime defaultOffset = 37
N3: getComplexRcvEnSetupTime = 37
N3.C0.S05: rcvenoffset delta = 37
N3.C0.S05: Final txdqoffset / txdqsoffset / rcvenoffset /  4 / 44 / 41
N3: getComplexDqSetupTime defaultOffset = 0
N3: getComplexDqSetupTime = 0
N3.C0.S06: txdqoffset delta = 0, dq invertpiclk = 3
N3: getComplexDqsSetupTime defaultOffset = 40
N3: getComplexDqsSetupTime = 40
N3.C0.S06: txdqsoffset delta = 40
N3: getComplexRcvEnSetupTime defaultOffset = 37
N3: getComplexRcvEnSetupTime = 37
N3.C0.S06: rcvenoffset delta = 37
N3.C0.S06: Final txdqoffset / txdqsoffset / rcvenoffset / 32 /  8 /  5
N3: getComplexDqSetupTime defaultOffset = 0
N3: getComplexDqSetupTime = 0
N3.C0.S07: txdqoffset delta = 0, dq invertpiclk = 3
N3: getComplexDqsSetupTime defaultOffset = 40
N3: getComplexDqsSetupTime = 40
N3.C0.S07: txdqsoffset delta = 40
N3: getComplexRcvEnSetupTime defaultOffset = 37
N3: getComplexRcvEnSetupTime = 37
N3.C0.S07: rcvenoffset delta = 37
N3.C0.S07: Final txdqoffset / txdqsoffset / rcvenoffset /  0 / 40 / 37
N3: getComplexDqSetupTime defaultOffset = 0
N3: getComplexDqSetupTime = 0
N3.C0.S08: txdqoffset delta = 0, dq invertpiclk = 3
N3: getComplexDqsSetupTime defaultOffset = 40
N3: getComplexDqsSetupTime = 40
N3.C0.S08: txdqsoffset delta = 40
N3: getComplexRcvEnSetupTime defaultOffset = 37
N3: getComplexRcvEnSetupTime = 37
N3.C0.S08: rcvenoffset delta = 37
N3.C0.S08: Final txdqoffset / txdqsoffset / rcvenoffset / 37 / 13 / 10

N3: vmse_modes =          1,  0
N3.C1: piDelay CMDn  CMDs  CTL  CKE  CLK   0  1  2  3  4  5  6  7  8  9 10 11 12 13 14 15 16 17
          0       0     0    1    0    0   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
          1       0     0    1    0    0   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
          2       0     0    1    0    0   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
          3       0     0    1    1    0   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
          4       0     0    1    1    0   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
          5       0     0    1    1    0   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
          6       0     0    1    1    0   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
          7       0     0    1    1    0   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
          8       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
          9       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         10       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         11       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         12       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         13       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         14       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         15       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         16       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         17       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         18       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         19       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         20       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         21       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         22       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         23       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         24       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         25       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         26       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         27       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         28       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         29       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         30       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         31       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         32       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         33       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         34       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         35       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         36       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         37       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         38       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         39       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         40       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         41       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         42       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         43       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         44       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         45       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         46       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         47       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         48       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         49       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         50       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         51       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         52       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         53       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         54       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         55       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         56       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         57       0     0    1    1    1   0  1  1  1  1  1  1  1  1  0  1  1  1  1  1  1  1  1 
         58       0     0    1    1    1   X  0  1  1  1  1  1  1  1  X  0  1  1  1  1  1  1  1 
         59       0     0    1    1    1   X  X  1  1  1  1  1  1  1  X  X  1  1  1  1  1  1  1 
         60       0     0    1    1    1   X  X  1  1  1  1  1  0  1  X  X  1  1  1  1  1  0  1 
         61       0     0    1    1    1   X  X  0  1  1  1  1  X  1  X  X  0  1  1  1  1  X  1 
         62       0     0    1    1    1   X  X  X  1  1  1  0  X  1  X  X  X  1  1  1  0  X  1 
         63       0     0    1    1    1   X  X  X  0  1  1  X  X  1  X  X  X  0  1  0  X  X  1 
N3.C1: setting ddrcrinvertpiclk
          0       0     0    1    1    1   X  X  X  X  1  0  X  X  1  X  X  X  X  1  X  X  X  1 
          1       0     0    0    1    1   X  X  X  X  1  0  X  X  1  X  X  X  X  1  X  X  X  0 
          2       0     0    X    1    1   X  X  X  X  0  0  X  X  0  X  X  X  X  0  X  X  X  X 
          3       0     0    X    1    1   X  X  X  X  X  0  X  X  X  X  X  X  X  X  X  X  X  X 
          4       0     0    X    0    1   X  X  X  X  X  0  X  X  X  X  X  X  X  X  X  X  X  X 
          5       0     0    X    X    1   X  X  X  X  X  0  X  X  X  X  X  X  X  X  X  X  X  X 
          6       0     0    X    X    1   X  X  X  X  X  0  X  X  X  X  X  X  X  X  X  X  X  X 
          7       0     0    X    X    1   X  X  X  X  X  0  X  X  X  X  X  X  X  X  X  X  X  X 
          8       0     0    X    X    1   X  X  X  X  X  0  X  X  X  X  X  X  X  X  X  X  X  X 
          9       0     0    X    X    0   X  X  X  X  X  0  X  X  X  X  X  X  X  X  X  X  X  X 
         10       0     0    X    X    X   X  X  X  X  X  0  X  X  X  X  X  X  X  X  X  X  X  X 
         11       0     0    X    X    X   X  X  X  X  X  0  X  X  X  X  X  X  X  X  X  X  X  X 
         12       0     0    X    X    X   X  X  X  X  X  0  X  X  X  X  X  X  X  X  X  X  X  X 
         13       0     0    X    X    X   X  X  X  X  X  0  X  X  X  X  X  X  X  X  X  X  X  X 
         14       0     0    X    X    X   X  X  X  X  X  0  X  X  X  X  X  X  X  X  X  X  X  X 
         15       0     0    X    X    X   X  X  X  X  X  0  X  X  X  X  X  X  X  X  X  X  X  X 
         16       0     0    X    X    X   X  X  X  X  X  0  X  X  X  X  X  X  X  X  X  X  X  X 
         17       0     0    X    X    X   X  X  X  X  X  0  X  X  X  X  X  X  X  X  X  X  X  X 
         18       0     0    X    X    X   X  X  X  X  X  0  X  X  X  X  X  X  X  X  X  X  X  X 
         19       0     0    X    X    X   X  X  X  X  X  0  X  X  X  X  X  X  X  X  X  X  X  X 
         20       0     0    X    X    X   X  X  X  X  X  0  X  X  X  X  X  X  X  X  X  X  X  X 
         21       0     0    X    X    X   X  X  X  X  X  0  X  X  X  X  X  X  X  X  X  X  X  X 
         22       0     0    X    X    X   X  X  X  X  X  0  X  X  X  X  X  X  X  X  X  X  X  X 
         23       0     0    X    X    X   X  X  X  X  X  0  X  X  X  X  X  X  X  X  X  X  X  X 
         24       0     0    X    X    X   X  X  X  X  X  0  X  X  X  X  X  X  X  X  X  X  X  X 
         25       0     0    X    X    X   X  X  X  X  X  0  X  X  X  X  X  X  X  X  X  X  X  X 
         26       0     0    X    X    X   X  X  X  X  X  0  X  X  X  X  X  X  X  X  X  X  X  X 
         27       0     0    X    X    X   X  X  X  X  X  0  X  X  X  X  X  X  X  X  X  X  X  X 
         28       0     0    X    X    X   X  X  X  X  X  0  X  X  X  X  X  X  X  X  X  X  X  X 
         29       0     0    X    X    X   X  X  X  X  X  0  X  X  X  X  X  X  X  X  X  X  X  X 
         30       0     0    X    X    X   X  X  X  X  X  0  X  X  X  X  X  X  X  X  X  X  X  X 
         31       0     0    X    X    X   X  X  X  X  X  0  X  X  X  X  X  X  X  X  X  X  X  X 
         32       0     0    X    X    X   X  X  X  X  X  0  X  X  X  X  X  X  X  X  X  X  X  X 
         33       0     0    X    X    X   X  X  X  X  X  0  X  X  X  X  X  X  X  X  X  X  X  X 
         34       0     0    X    X    X   X  X  X  X  X  0  X  X  X  X  X  X  X  X  X  X  X  X 
         35       0     0    X    X    X   X  X  X  X  X  0  X  X  X  X  X  X  X  X  X  X  X  X 
         36       0     0    X    X    X   X  X  X  X  X  0  X  X  X  X  X  X  X  X  X  X  X  X 
         37       0     0    X    X    X   X  X  X  X  X  0  X  X  X  X  X  X  X  X  X  X  X  X 
         38       0     0    X    X    X   X  X  X  X  X  0  X  X  X  X  X  X  X  X  X  X  X  X 
         39       0     0    X    X    X   X  X  X  X  X  0  X  X  X  X  X  X  X  X  X  X  X  X 
         40       0     0    X    X    X   X  X  X  X  X  0  X  X  X  X  X  X  X  X  X  X  X  X 
         41       0     0    X    X    X   X  X  X  X  X  0  X  X  X  X  X  X  X  X  X  X  X  X 
         42       0     0    X    X    X   X  X  X  X  X  0  X  X  X  X  X  X  X  X  X  X  X  X 
         43       0     0    X    X    X   X  X  X  X  X  0  X  X  X  X  X  X  X  X  X  X  X  X 
         44       0     0    X    X    X   X  X  X  X  X  0  X  X  X  X  X  X  X  X  X  X  X  X 
         45       0     0    X    X    X   X  X  X  X  X  0  X  X  X  X  X  X  X  X  X  X  X  X 
         46       0     0    X    X    X   X  X  X  X  X  0  X  X  X  X  X  X  X  X  X  X  X  X 
         47       0     0    X    X    X   X  X  X  X  X  0  X  X  X  X  X  X  X  X  X  X  X  X 
         48       0     0    X    X    X   X  X  X  X  X  0  X  X  X  X  X  X  X  X  X  X  X  X 
         49       0     0    X    X    X   X  X  X  X  X  0  X  X  X  X  X  X  X  X  X  X  X  X 
         50       0     0    X    X    X   X  X  X  X  X  0  X  X  X  X  X  X  X  X  X  X  X  X 
         51       0     0    X    X    X   X  X  X  X  X  0  X  X  X  X  X  X  X  X  X  X  X  X 
         52       0     0    X    X    X   X  X  X  X  X  0  X  X  X  X  X  X  X  X  X  X  X  X 
         53       0     0    X    X    X   X  X  X  X  X  0  X  X  X  X  X  X  X  X  X  X  X  X 
         54       0     0    X    X    X   X  X  X  X  X  0  X  X  X  X  X  X  X  X  X  X  X  X 
         55       0     0    X    X    X   X  X  X  X  X  0  X  X  X  X  X  X  X  X  X  X  X  X 
         56       0     0    X    X    X   X  X  X  X  X  0  X  X  X  X  X  X  X  X  X  X  X  X 
         57       0     0    X    X    X   X  X  X  X  X  0  X  X  X  X  X  X  X  X  X  X  X  X 
         58       0     0    X    X    X   X  X  X  X  X  0  X  X  X  X  X  X  X  X  X  X  X  X 
         59       0     0    X    X    X   X  X  X  X  X  0  X  X  X  X  X  X  X  X  X  X  X  X 
         60       0     0    X    X    X   X  X  X  X  X  0  X  X  X  X  X  X  X  X  X  X  X  X 
         61       0     0    X    X    X   X  X  X  X  X  0  X  X  X  X  X  X  X  X  X  X  X  X 
         62       0     0    X    X    X   X  X  X  X  X  1  X  X  X  X  X  X  X  X  X  X  X  X 
         63       0     0    X    X    X   X  X  X  X  X  1  X  X  X  X  X  X  X  X  X  X  X  X 
N3.C1: CMD-N xovercal offset = 0
N3.C1: CMD-S xovercal offset = 0
N3.C1: CTL xovercal offset   = 1
N3.C1: CKE xovercal offset   = 4
N3.C1: CLK xovercal offset   = 9
N3.C1.S18: STROBE                     0   1   2   3   4   5   6   7   8   9  10  11  12  13  14  15  16  17
N3.C1.S18: Rec En xovercal offset =  57  58  61  63   2   0  62  60   2  57  58  61  63   2  63  62  60   1 
N3.C1.S18: Tx Dqs xovercal offset =  57  63  63  63  63   0  63  63  63  63  63  63  63  63  63  63  63  63 
N3.C1.S18: Tx Dq xovercal offset  =  57  58  61  63   2   0  62  60   2  57  58  61  63   2  63  62  60   1 
N3.C1:         CMDn  CMDs  CTL  CKE  CLK   0  1  2  3  4  5  6  7  8
N3.C1: offsets:  0     0     1N3: getComplexCkeSetupTime defaultOffset = 98
N3: getComplexCkeSetupTime = 98
    4    9
Ctl Offsets Delta / final ctl offset / final cke offset /  98  /   3  /  38
Cke invertpiclk / Ctl invertpiclk / 0x0  /  0x0
N3: getComplexClkSetupTime defaultOffset = 0
N3: getComplexClkSetupTime = 0
ClkSetupTime = 41
N3: getComplexDqSetupTime defaultOffset = 0
N3: getComplexDqSetupTime = 0
N3.C1.S00: txdqoffset delta = 0, dq invertpiclk = 0
N3: getComplexDqsSetupTime defaultOffset = 40
N3: getComplexDqsSetupTime = 40
N3.C1.S00: txdqsoffset delta = 40
N3: getComplexRcvEnSetupTime defaultOffset = 37
N3: getComplexRcvEnSetupTime = 37
N3.C1.S00: rcvenoffset delta = 37
N3.C1.S00: Final txdqoffset / txdqsoffset / rcvenoffset / 57 / 33 / 30
N3: getComplexDqSetupTime defaultOffset = 0
N3: getComplexDqSetupTime = 0
N3.C1.S01: txdqoffset delta = 0, dq invertpiclk = 0
N3: getComplexDqsSetupTime defaultOffset = 40
N3: getComplexDqsSetupTime = 40
N3.C1.S01: txdqsoffset delta = 40
N3: getComplexRcvEnSetupTime defaultOffset = 37
N3: getComplexRcvEnSetupTime = 37
N3.C1.S01: rcvenoffset delta = 37
N3.C1.S01: Final txdqoffset / txdqsoffset / rcvenoffset / 26 /  2 / 63
N3: getComplexDqSetupTime defaultOffset = 0
N3: getComplexDqSetupTime = 0
N3.C1.S02: txdqoffset delta = 0, dq invertpiclk = 0
N3: getComplexDqsSetupTime defaultOffset = 40
N3: getComplexDqsSetupTime = 40
N3.C1.S02: txdqsoffset delta = 40
N3: getComplexRcvEnSetupTime defaultOffset = 37
N3: getComplexRcvEnSetupTime = 37
N3.C1.S02: rcvenoffset delta = 37
N3.C1.S02: Final txdqoffset / txdqsoffset / rcvenoffset / 61 / 37 / 34
N3: getComplexDqSetupTime defaultOffset = 0
N3: getComplexDqSetupTime = 0
N3.C1.S03: txdqoffset delta = 0, dq invertpiclk = 0
N3: getComplexDqsSetupTime defaultOffset = 40
N3: getComplexDqsSetupTime = 40
N3.C1.S03: txdqsoffset delta = 40
N3: getComplexRcvEnSetupTime defaultOffset = 37
N3: getComplexRcvEnSetupTime = 37
N3.C1.S03: rcvenoffset delta = 37
N3.C1.S03: Final txdqoffset / txdqsoffset / rcvenoffset / 31 /  7 /  4
N3: getComplexDqSetupTime defaultOffset = 0
N3: getComplexDqSetupTime = 0
N3.C1.S04: txdqoffset delta = 0, dq invertpiclk = 3
N3: getComplexDqsSetupTime defaultOffset = 40
N3: getComplexDqsSetupTime = 40
N3.C1.S04: txdqsoffset delta = 40
N3: getComplexRcvEnSetupTime defaultOffset = 37
N3: getComplexRcvEnSetupTime = 37
N3.C1.S04: rcvenoffset delta = 37
N3.C1.S04: Final txdqoffset / txdqsoffset / rcvenoffset /  2 / 42 / 39
N3: getComplexDqSetupTime defaultOffset = 0
N3: getComplexDqSetupTime = 0
N3.C1.S05: txdqoffset delta = 0, dq invertpiclk = 3
N3: getComplexDqsSetupTime defaultOffset = 40
N3: getComplexDqsSetupTime = 40
N3.C1.S05: txdqsoffset delta = 40
N3: getComplexRcvEnSetupTime defaultOffset = 37
N3: getComplexRcvEnSetupTime = 37
N3.C1.S05: rcvenoffset delta = 37
N3.C1.S05: Final txdqoffset / txdqsoffset / rcvenoffset / 32 /  8 /  5
N3: getComplexDqSetupTime defaultOffset = 0
N3: getComplexDqSetupTime = 0
N3.C1.S06: txdqoffset delta = 0, dq invertpiclk = 0
N3: getComplexDqsSetupTime defaultOffset = 40
N3: getComplexDqsSetupTime = 40
N3.C1.S06: txdqsoffset delta = 40
N3: getComplexRcvEnSetupTime defaultOffset = 37
N3: getComplexRcvEnSetupTime = 37
N3.C1.S06: rcvenoffset delta = 37
N3.C1.S06: Final txdqoffset / txdqsoffset / rcvenoffset / 62 / 38 / 35
N3: getComplexDqSetupTime defaultOffset = 0
N3: getComplexDqSetupTime = 0
N3.C1.S07: txdqoffset delta = 0, dq invertpiclk = 0
N3: getComplexDqsSetupTime defaultOffset = 40
N3: getComplexDqsSetupTime = 40
N3.C1.S07: txdqsoffset delta = 40
N3: getComplexRcvEnSetupTime defaultOffset = 37
N3: getComplexRcvEnSetupTime = 37
N3.C1.S07: rcvenoffset delta = 37
N3.C1.S07: Final txdqoffset / txdqsoffset / rcvenoffset / 28 /  4 /  1
N3: getComplexDqSetupTime defaultOffset = 0
N3: getComplexDqSetupTime = 0
N3.C1.S08: txdqoffset delta = 0, dq invertpiclk = 3
N3: getComplexDqsSetupTime defaultOffset = 40
N3: getComplexDqsSetupTime = 40
N3.C1.S08: txdqsoffset delta = 40
N3: getComplexRcvEnSetupTime defaultOffset = 37
N3: getComplexRcvEnSetupTime = 37
N3.C1.S08: rcvenoffset delta = 37
N3.C1.S08: Final txdqoffset / txdqsoffset / rcvenoffset /  2 / 42 / 39

N5.C1: nRRD = 4
N7.C0: nCWL = 7
N1.C2: nRAS = 24
N5.C1: nWTR = 5
N7.C0: nRP = 9
N1.C2: nRTP = 5
N5.C1: nRAS = 24
N7.C0: nRCD = 9
N1.C2: nWR = 10
N5.C1: nRTP = 5
N7.C0: nRRD = 4
N1.C2: nFAW = 20
N5.C1: nWR = 10
N7.C0: nWTR = 5
N1.C2: nRC = 33
N3: SetupJckSmbCfg: JCK VLINFREQ set to: 0x820F1028
N5.C1: nFAW = 20
N7.C0: nRAS = 24
N1.C2: nRFC = 174
N5.C1: nRC = 33
N7.C0: nRTP = 5
N1.C2: casSup = 0xFC
N3: SetupJckSmbCfg: PLL is locked.
N5.C1: nRFC = 174
N7.C0: nWR = 10
N1.C2: trrMode = 0
N3.C0: SetupJckSmbCfg: dlyFrms = 15
N5.C1: casSup = 0xFC
N7.C0: nFAW = 20
N1.C2: twoXRefresh = 0
N3.C0: cwleffective = 8
N5.C1: trrMode = 0
N7.C0: nRC = 33
N1.C2: t_stagger_ref = 0x86
N3.C0: PreVMSE Training raw cleff = 9, raw cwleff = 7
N5.C1: twoXRefresh = 0
N7.C0: nRFC = 174
N1.C2: tcsrftp.Bits.t_xsdll = 512
N5.C1: t_stagger_ref = 0x86
N7.C0: casSup = 0xFC
N1.C2: Common CL = 9
Common CWL = 7
N3.C0: vmseratio = 0, revisionId = 5, vmse_mode = 1, QCRM_ENABLE = 0
N5.C1: tcsrftp.Bits.t_xsdll = 512
N7.C0: trrMode = 0
N1: Memory Timings:
N3: SetupJckSmbCfg: JCK wpsyncrcven = 5, wpsyncdata = 10
N5.C1: Common CL = 9
Common CWL = 7
N7.C0: twoXRefresh = 0
N1.C3: nCL = 9
N5: Memory Timings:
N7.C0: t_stagger_ref = 0x86
N1.C3: nCWL = 7
N5.C2: nCL = 9
N7.C0: tcsrftp.Bits.t_xsdll = 512
N1.C3: nRP = 9
N5.C2: nCWL = 7
N7.C0: Common CL = 9
Common CWL = 7
N1.C3: nRCD = 9
N5.C2: nRP = 9
N7: Memory Timings:
N1.C3: nRRD = 4
N5.C2: nRCD = 9
N7.C1: nCL = 9
N1.C3: nWTR = 5
N5.C2: nRRD = 4
N7.C1: nCWL = 7
N1.C3: nRAS = 24
N5.C2: nWTR = 5
N7.C1: nRP = 9
N1.C3: nRTP = 5
N5.C2: nRAS = 24
N7.C1: nRCD = 9
N1.C3: nWR = 10
N5.C2: nRTP = 5
N7.C1: nRRD = 4
N1.C3: nFAW = 20
N5.C2: nWR = 10
N7.C1: nWTR = 5
N1.C3: nRC = 33
N5.C2: nFAW = 20
N7.C1: nRAS = 24
N1.C3: nRFC = 174
N5.C2: nRC = 33
N7.C1: nRTP = 5
N1.C3: casSup = 0xFC
N5.C2: nRFC = 174
N7.C1: nWR = 10
N1.C3: trrMode = 0
N5.C2: casSup = 0xFC
N7.C1: nFAW = 20
N1.C3: twoXRefresh = 0
N5.C2: trrMode = 0
N7.C1: nRC = 33
N1.C3: t_stagger_ref = 0x86
N5.C2: twoXRefresh = 0
N7.C1: nRFC = 174
N1.C3: tcsrftp.Bits.t_xsdll = 512
N5.C2: t_stagger_ref = 0x86
N7.C1: casSup = 0xFC
N1.C3: Common CL = 9
Common CWL = 7
N5.C2: tcsrftp.Bits.t_xsdll = 512
N7.C1: trrMode = 0
Checkpoint Code: Socket 0, 0xB6, 0x00, 0x0000
N5.C2: Common CL = 9
Common CWL = 7
N7.C1: twoXRefresh = 0
N1: PreVmseTraining
N5: Memory Timings:
N7.C1: t_stagger_ref = 0x86
Checkpoint Code: Socket 0, 0xB6, 0x01, 0x0000
N5.C3: nCL = 9
N7.C1: tcsrftp.Bits.t_xsdll = 512
N1.C0: InitHostVmseCfg
N5.C3: nCWL = 7
N7.C1: Common CL = 9
Common CWL = 7
N1.C0: vmse_wr_turnaround = 0x7 
N5.C3: nRP = 9
N7: Memory Timings:
Checkpoint Code: Socket 0, 0xB6, 0x01, 0x0000
N5.C3: nRCD = 9
N7.C2: nCL = 9
N1.C2: InitHostVmseCfg
N5.C3: nRRD = 4
N7.C2: nCWL = 7
N1.C2: vmse_wr_turnaround = 0x7 
N5.C3: nWTR = 5
N7.C2: nRP = 9
Checkpoint Code: Socket 0, 0xB6, 0x02, 0x0000
N5.C3: nRAS = 24
N7.C2: nRCD = 9
N1: HsxInitDdrioInterface
N5.C3: nRTP = 5
N7.C2: nRRD = 4
N1.C0: rxVref = 0x5F
N5.C3: nWR = 10
N7.C2: nWTR = 5
N1.C1: rxVref = 0x5F
N5.C3: nFAW = 20
N7.C2: nRAS = 24
N1: HsxVmseCompInit
N5.C3: nRC = 33
N7.C2: nRTP = 5
Checkpoint Code: Socket 0, 0xB6, 0x58, 0x0000
N1: VmseCrossoverCalib
N1: Enable xovercal
N1: vmse_modes =          1,  0
N1.C0: piDelay CMDn  CMDs  CTL  CKE  CLK   0  1  2  3  4  5  6  7  8  9 10 11 12 13 14 15 16 17
          0       0     0    0    0    0   1  1  1  1  0  1  1  1  0  1  1  1  1  0  1  1  1  0 
          1       0     0    0    0    0   1  1  1  1  0  1  1  1  1  1  1  1  1  0  1  1  1  1 
          2       0     0    0    0    0   1  1  1  1  0  1  1  1  1  1  1  1  1  1  1  1  1  1 
          3       0     0    1    0    0   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
          4       0     0    1    0    0   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
          5       0     0    1    1    0   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
          6       0     0    1    1    0   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
          7       0     0    1    1    0   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
          8       0     0    1    1    0   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
          9       0     0    1    1    0   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         10       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         11       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         12       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         13       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         14       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         15       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         16       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         17       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         18       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         19       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         20       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         21       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         22       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         23       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         24       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         25       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         26       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         27       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         28       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         29       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         30       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         31       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         32       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         33       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         34       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         35       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         36       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         37       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         38       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         39       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         40       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         41       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         42       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         43       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         44       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         45       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         46       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         47       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         48       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         49       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         50       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         51       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         52       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         53       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         54       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         55       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         56       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         57       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         58       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         59       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         60       0     0    1    1    1   0  1  1  1  1  1  1  1  1  0  1  1  1  1  1  1  1  1 
         61       0     0    1    1    1   X  0  1  1  1  1  1  1  1  X  0  1  1  1  1  1  1  1 
         62       0     0    1    1    1   X  X  1  1  1  1  1  1  1  X  X  1  1  1  1  1  1  1 
         63       0     0    1    1    1   X  X  0  1  1  1  1  1  1  X  X  0  1  1  1  1  1  1 
N1.C0: setting ddrcrinvertpiclk
          0       0     0    1    1    1   X  X  X  1  1  1  0  0  1  X  X  X  1  1  1  0  0  1 
          1       0     0    1    1    1   X  X  X  0  1  1  0  0  1  X  X  X  0  1  1  0  0  1 
          2       0     0    1    1    1   X  X  X  X  1  0  0  0  1  X  X  X  X  1  0  0  0  1 
          3       0     0    1    1    1   X  X  X  X  1  X  0  0  0  X  X  X  X  1  X  0  0  0 
          4       0     0    0    1    1   X  X  X  X  0  X  0  0  X  X  X  X  X  0  X  0  0  X 
          5       0     0    X    1    1   X  X  X  X  X  X  0  0  X  X  X  X  X  X  X  0  0  X 
          6       0     0    X    0    1   X  X  X  X  X  X  0  0  X  X  X  X  X  X  X  0  0  X 
          7       0     0    X    X    1   X  X  X  X  X  X  0  0  X  X  X  X  X  X  X  0  0  X 
          8       0     0    X    X    1   X  X  X  X  X  X  0  0  X  X  X  X  X  X  X  0  0  X 
          9       0     0    X    X    1   X  X  X  X  X  X  0  0  X  X  X  X  X  X  X  0  0  X 
         10       0     0    X    X    1   X  X  X  X  X  X  0  0  X  X  X  X  X  X  X  0  0  X 
         11       0     0    X    X    0   X  X  X  X  X  X  0  0  X  X  X  X  X  X  X  0  0  X 
         12       0     0    X    X    X   X  X  X  X  X  X  0  0  X  X  X  X  X  X  X  0  0  X 
         13       0     0    X    X    X   X  X  X  X  X  X  0  0  X  X  X  X  X  X  X  0  0  X 
         14       0     0    X    X    X   X  X  X  X  X  X  0  0  X  X  X  X  X  X  X  0  0  X 
         15       0     0    X    X    X   X  X  X  X  X  X  0  0  X  X  X  X  X  X  X  0  0  X 
         16       0     0    X    X    X   X  X  X  X  X  X  0  0  X  X  X  X  X  X  X  0  0  X 
         17       0     0    X    X    X   X  X  X  X  X  X  0  0  X  X  X  X  X  X  X  0  0  X 
         18       0     0    X    X    X   X  X  X  X  X  X  0  0  X  X  X  X  X  X  X  0  0  X 
         19       0     0    X    X    X   X  X  X  X  X  X  0  0  X  X  X  X  X  X  X  0  0  X 
         20       0     0    X    X    X   X  X  X  X  X  X  0  0  X  X  X  X  X  X  X  0  0  X 
         21       0     0    X    X    X   X  X  X  X  X  X  0  0  X  X  X  X  X  X  X  0  0  X 
         22       0     0    X    X    X   X  X  X  X  X  X  0  0  X  X  X  X  X  X  X  0  0  X 
         23       0     0    X    X    X   X  X  X  X  X  X  0  0  X  X  X  X  X  X  X  0  0  X 
         24       0     0    X    X    X   X  X  X  X  X  X  0  0  X  X  X  X  X  X  X  0  0  X 
         25       0     0    X    X    X   X  X  X  X  X  X  0  0  X  X  X  X  X  X  X  0  0  X 
         26       0     0    X    X    X   X  X  X  X  X  X  0  0  X  X  X  X  X  X  X  0  0  X 
         27       0     0    X    X    X   X  X  X  X  X  X  0  0  X  X  X  X  X  X  X  0  0  X 
         28       0     0    X    X    X   X  X  X  X  X  X  0  0  X  X  X  X  X  X  X  0  0  X 
         29       0     0    X    X    X   X  X  X  X  X  X  0  0  X  X  X  X  X  X  X  0  0  X 
         30       0     0    X    X    X   X  X  X  X  X  X  0  0  X  X  X  X  X  X  X  0  0  X 
         31       0     0    X    X    X   X  X  X  X  X  X  0  0  X  X  X  X  X  X  X  0  0  X 
         32       0     0    X    X    X   X  X  X  X  X  X  0  0  X  X  X  X  X  X  X  0  0  X 
         33       0     0    X    X    X   X  X  X  X  X  X  0  0  X  X  X  X  X  X  X  0  0  X 
         34       0     0    X    X    X   X  X  X  X  X  X  0  0  X  X  X  X  X  X  X  0  0  X 
         35       0     0    X    X    X   X  X  X  X  X  X  0  0  X  X  X  X  X  X  X  0  0  X 
         36       0     0    X    X    X   X  X  X  X  X  X  0  0  X  X  X  X  X  X  X  0  0  X 
         37       0     0    X    X    X   X  X  X  X  X  X  0  0  X  X  X  X  X  X  X  0  0  X 
         38       0     0    X    X    X   X  X  X  X  X  X  0  0  X  X  X  X  X  X  X  0  0  X 
         39       0     0    X    X    X   X  X  X  X  X  X  0  0  X  X  X  X  X  X  X  0  0  X 
         40       0     0    X    X    X   X  X  X  X  X  X  0  0  X  X  X  X  X  X  X  0  0  X 
         41       0     0    X    X    X   X  X  X  X  X  X  0  0  X  X  X  X  X  X  X  0  0  X 
         42       0     0    X    X    X   X  X  X  X  X  X  0  0  X  X  X  X  X  X  X  0  0  X 
         43       0     0    X    X    X   X  X  X  X  X  X  0  0  X  X  X  X  X  X  X  0  0  X 
         44       0     0    X    X    X   X  X  X  X  X  X  0  0  X  X  X  X  X  X  X  0  0  X 
         45       0     0    X    X    X   X  X  X  X  X  X  0  0  X  X  X  X  X  X  X  0  0  X 
         46       0     0    X    X    X   X  X  X  X  X  X  0  0  X  X  X  X  X  X  X  0  0  X 
         47       0     0    X    X    X   X  X  X  X  X  X  0  0  X  X  X  X  X  X  X  0  0  X 
         48       0     0    X    X    X   X  X  X  X  X  X  0  0  X  X  X  X  X  X  X  0  0  X 
         49       0     0    X    X    X   X  X  X  X  X  X  0  0  X  X  X  X  X  X  X  0  0  X 
         50       0     0    X    X    X   X  X  X  X  X  X  0  0  X  X  X  X  X  X  X  0  0  X 
         51       0     0    X    X    X   X  X  X  X  X  X  0  0  X  X  X  X  X  X  X  0  0  X 
         52       0     0    X    X    X   X  X  X  X  X  X  0  0  X  X  X  X  X  X  X  0  0  X 
         53       0     0    X    X    X   X  X  X  X  X  X  0  0  X  X  X  X  X  X  X  0  0  X 
         54       0     0    X    X    X   X  X  X  X  X  X  0  0  X  X  X  X  X  X  X  0  0  X 
         55       0     0    X    X    X   X  X  X  X  X  X  0  0  X  X  X  X  X  X  X  0  0  X 
         56       0     0    X    X    X   X  X  X  X  X  X  0  0  X  X  X  X  X  X  X  0  0  X 
         57       0     0    X    X    X   X  X  X  X  X  X  0  0  X  X  X  X  X  X  X  0  0  X 
         58       0     0    X    X    X   X  X  X  X  X  X  0  0  X  X  X  X  X  X  X  0  0  X 
         59       0     0    X    X    X   X  X  X  X  X  X  0  0  X  X  X  X  X  X  X  0  0  X 
         60       0     0    X    X    X   X  X  X  X  X  X  0  0  X  X  X  X  X  X  X  0  0  X 
         61       0     0    X    X    X   X  X  X  X  X  X  0  0  X  X  X  X  X  X  X  0  0  X 
         62       0     0    X    X    X   X  X  X  X  X  X  0  0  X  X  X  X  X  X  X  0  0  X 
         63       0     0    X    X    X   X  X  X  X  X  X  1  1  X  X  X  X  X  X  X  1  1  X 
N1.C0: CMD-N xovercal offset = 0
N1.C0: CMD-S xovercal offset = 0
N1.C0: CTL xovercal offset   = 4
N1.C0: CKE xovercal offset   = 6
N1.C0: CLK xovercal offset   = 11
N1.C0.S18: STROBE                     0   1   2   3   4   5   6   7   8   9  10  11  12  13  14  15  16  17
N1.C0.S18: Rec En xovercal offset =  60  61  63   1   4   2   0   0   3  60  61  63   1   4   2   0   0   3 
N1.C0.S18: Tx Dqs xovercal offset =  60  63  63  63  63  63   0   0  63  63  63  63  63  63  63   0   0  63 
N1.C0.S18: Tx Dq xovercal offset  =  60  61  63   1   4   2   0   0   3  60  61  63   1   4   2   0   0   3 
N1.C0:         CMDn  CMDs  CTL  CKE  CLK   0  1  2  3  4  5  6  7  8
N1.C0: offsets:  0     0     4N1: getComplexCkeSetupTime defaultOffset = 98
N1: getComplexCkeSetupTime = 98
    6   11
Ctl Offsets Delta / final ctl offset / final cke offset /  98  /  38  /   8
Cke invertpiclk / Ctl invertpiclk / 0x0  /  0x0
N1: getComplexClkSetupTime defaultOffset = 0
N1: getComplexClkSetupTime = 0
ClkSetupTime = 11
N1: getComplexDqSetupTime defaultOffset = 0
N1: getComplexDqSetupTime = 0
N1.C0.S00: txdqoffset delta = 0, dq invertpiclk = 0
N1: getComplexDqsSetupTime defaultOffset = 40
N1: getComplexDqsSetupTime = 40
N1.C0.S00: txdqsoffset delta = 40
N1: getComplexRcvEnSetupTime defaultOffset = 37
N1: getComplexRcvEnSetupTime = 37
N1.C0.S00: rcvenoffset delta = 37
N1.C0.S00: Final txdqoffset / txdqsoffset / rcvenoffset / 28 /  4 /  1
N1: getComplexDqSetupTime defaultOffset = 0
N1: getComplexDqSetupTime = 0
N1.C0.S01: txdqoffset delta = 0, dq invertpiclk = 0
N1: getComplexDqsSetupTime defaultOffset = 40
N1: getComplexDqsSetupTime = 40
N1.C0.S01: txdqsoffset delta = 40
N1: getComplexRcvEnSetupTime defaultOffset = 37
N1: getComplexRcvEnSetupTime = 37
N1.C0.S01: rcvenoffset delta = 37
N1.C0.S01: Final txdqoffset / txdqsoffset / rcvenoffset / 61 / 37 / 34
N1: getComplexDqSetupTime defaultOffset = 0
N1: getComplexDqSetupTime = 0
N1.C0.S02: txdqoffset delta = 0, dq invertpiclk = 0
N1: getComplexDqsSetupTime defaultOffset = 40
N1: getComplexDqsSetupTime = 40
N1.C0.S02: txdqsoffset delta = 40
N1: getComplexRcvEnSetupTime defaultOffset = 37
N1: getComplexRcvEnSetupTime = 37
N1.C0.S02: rcvenoffset delta = 37
N1.C0.S02: Final txdqoffset / txdqsoffset / rcvenoffset / 31 /  7 /  4
N1: getComplexDqSetupTime defaultOffset = 0
N1: getComplexDqSetupTime = 0
N1.C0.S03: txdqoffset delta = 0, dq invertpiclk = 3
N1: getComplexDqsSetupTime defaultOffset = 40
N1: getComplexDqsSetupTime = 40
N1.C0.S03: txdqsoffset delta = 40
N1: getComplexRcvEnSetupTime defaultOffset = 37
N1: getComplexRcvEnSetupTime = 37
N1.C0.S03: rcvenoffset delta = 37
N1.C0.S03: Final txdqoffset / txdqsoffset / rcvenoffset /  1 / 41 / 38
N1: getComplexDqSetupTime defaultOffset = 0
N1: getComplexDqSetupTime = 0
N1.C0.S04: txdqoffset delta = 0, dq invertpiclk = 3
N1: getComplexDqsSetupTime defaultOffset = 40
N1: getComplexDqsSetupTime = 40
N1.C0.S04: txdqsoffset delta = 40
N1: getComplexRcvEnSetupTime defaultOffset = 37
N1: getComplexRcvEnSetupTime = 37
N1.C0.S04: rcvenoffset delta = 37
N1.C0.S04: Final txdqoffset / txdqsoffset / rcvenoffset / 36 / 12 /  9
N1: getComplexDqSetupTime defaultOffset = 0
N1: getComplexDqSetupTime = 0
N1.C0.S05: txdqoffset delta = 0, dq invertpiclk = 3
N1: getComplexDqsSetupTime defaultOffset = 40
N1: getComplexDqsSetupTime = 40
N1.C0.S05: txdqsoffset delta = 40
N1: getComplexRcvEnSetupTime defaultOffset = 37
N1: getComplexRcvEnSetupTime = 37
N1.C0.S05: rcvenoffset delta = 37
N1.C0.S05: Final txdqoffset / txdqsoffset / rcvenoffset /  2 / 42 / 39
N1: getComplexDqSetupTime defaultOffset = 0
N1: getComplexDqSetupTime = 0
N1.C0.S06: txdqoffset delta = 0, dq invertpiclk = 3
N1: getComplexDqsSetupTime defaultOffset = 40
N1: getComplexDqsSetupTime = 40
N1.C0.S06: txdqsoffset delta = 40
N1: getComplexRcvEnSetupTime defaultOffset = 37
N1: getComplexRcvEnSetupTime = 37
N1.C0.S06: rcvenoffset delta = 37
N1.C0.S06: Final txdqoffset / txdqsoffset / rcvenoffset / 32 /  8 /  5
N1: getComplexDqSetupTime defaultOffset = 0
N1: getComplexDqSetupTime = 0
N1.C0.S07: txdqoffset delta = 0, dq invertpiclk = 3
N1: getComplexDqsSetupTime defaultOffset = 40
N1: getComplexDqsSetupTime = 40
N1.C0.S07: txdqsoffset delta = 40
N1: getComplexRcvEnSetupTime defaultOffset = 37
N1: getComplexRcvEnSetupTime = 37
N1.C0.S07: rcvenoffset delta = 37
N1.C0.S07: Final txdqoffset / txdqsoffset / rcvenoffset /  0 / 40 / 37
N1: getComplexDqSetupTime defaultOffset = 0
N1: getComplexDqSetupTime = 0
N1.C0.S08: txdqoffset delta = 0, dq invertpiclk = 3
N1: getComplexDqsSetupTime defaultOffset = 40
N1: getComplexDqsSetupTime = 40
N1.C0.S08: txdqsoffset delta = 40
N1: getComplexRcvEnSetupTime defaultOffset = 37
N1: getComplexRcvEnSetupTime = 37
N1.C0.S08: rcvenoffset delta = 37
N1.C0.S08: Final txdqoffset / txdqsoffset / rcvenoffset / 35 / 11 /  8

N1: vmse_modes =          1,  0
N1.C1: piDelay CMDn  CMDs  CTL  CKE  CLK   0  1  2  3  4  5  6  7  8  9 10 11 12 13 14 15 16 17
          0       0     0    1    0    0   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
          1       0     0    1    1    0   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
          2       0     0    1    1    0   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
          3       0     0    1    1    0   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
          4       0     0    1    1    0   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
          5       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
          6       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
          7       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
          8       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
          9       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         10       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         11       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         12       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         13       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         14       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         15       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         16       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         17       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         18       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         19       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         20       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         21       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         22       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         23       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         24       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         25       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         26       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         27       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         28       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         29       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         30       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         31       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         32       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         33       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         34       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         35       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         36       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         37       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         38       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         39       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         40       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         41       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         42       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         43       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         44       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         45       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         46       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         47       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         48       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         49       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         50       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         51       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         52       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         53       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         54       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         55       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         56       0     0    1    1    1   0  1  1  1  1  1  1  1  1  0  1  1  1  1  1  1  1  1 
         57       0     0    1    1    1   X  0  1  1  1  1  1  1  1  X  0  1  1  1  1  1  1  1 
         58       0     0    1    1    1   X  X  1  1  1  1  1  1  1  X  X  1  1  1  1  1  1  1 
         59       0     0    1    1    1   X  X  0  1  1  1  1  0  1  X  X  0  1  1  1  1  0  1 
         60       0     0    1    1    1   X  X  X  1  1  1  0  X  1  X  X  X  1  1  1  0  X  1 
         61       0     0    1    1    1   X  X  X  0  1  1  X  X  1  X  X  X  0  1  1  X  X  1 
         62       0     0    1    1    1   X  X  X  X  1  0  X  X  1  X  X  X  X  1  0  X  X  1 
         63       0     0    1    1    1   X  X  X  X  1  X  X  X  1  X  X  X  X  1  X  X  X  1 
N1.C1: setting ddrcrinvertpiclk
          0       0     0    0    1    1   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
          1       0     0    0    1    1   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
          2       0     0    0    0    1   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
          3       0     0    0    X    1   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
          4       0     0    0    X    1   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
          5       0     0    0    X    1   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
          6       0     0    0    X    0   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
          7       0     0    0    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
          8       0     0    0    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
          9       0     0    0    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         10       0     0    0    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         11       0     0    0    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         12       0     0    0    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         13       0     0    0    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         14       0     0    0    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         15       0     0    0    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         16       0     0    0    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         17       0     0    0    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         18       0     0    0    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         19       0     0    0    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         20       0     0    0    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         21       0     0    0    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         22       0     0    0    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         23       0     0    0    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         24       0     0    0    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         25       0     0    0    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         26       0     0    0    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         27       0     0    0    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         28       0     0    0    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         29       0     0    0    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         30       0     0    0    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         31       0     0    0    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         32       0     0    0    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         33       0     0    0    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         34       0     0    0    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         35       0     0    0    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         36       0     0    0    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         37       0     0    0    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         38       0     0    0    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         39       0     0    0    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         40       0     0    0    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         41       0     0    0    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         42       0     0    0    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         43       0     0    0    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         44       0     0    0    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         45       0     0    0    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         46       0     0    0    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         47       0     0    0    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         48       0     0    0    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         49       0     0    0    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         50       0     0    0    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         51       0     0    0    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         52       0     0    0    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         53       0     0    0    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         54       0     0    0    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         55       0     0    0    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         56       0     0    0    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         57       0     0    0    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         58       0     0    0    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         59       0     0    0    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         60       0     0    0    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         61       0     0    0    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         62       0     0    0    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
         63       0     0    0    X    X   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
N1.C1: CMD-N xovercal offset = 0
N1.C1: CMD-S xovercal offset = 0
N1.C1: CTL xovercal offset   = 0
N1.C1: CKE xovercal offset   = 2
N1.C1: CLK xovercal offset   = 6
N1.C1.S18: STROBE                     0   1   2   3   4   5   6   7   8   9  10  11  12  13  14  15  16  17
N1.C1.S18: Rec En xovercal offset =  56  57  59  61   0  62  60  59   0  56  57  59  61   0  62  60  59   0 
N1.C1.S18: Tx Dqs xovercal offset =  56  63  63  63   0  63  63  63   0  63  63  63  63   0  63  63  63   0 
N1.C1.S18: Tx Dq xovercal offset  =  56  57  59  61   0  62  60  59   0  56  57  59  61   0  62  60  59   0 
N1.C1:         CMDn  CMDs  CTL  CKE  CLK   0  1  2  3  4  5  6  7  8
N1.C1: offsets:  0     0     0N1: getComplexCkeSetupTime defaultOffset = 98
N1: getComplexCkeSetupTime = 98
    2    6
Ctl Offsets Delta / final ctl offset / final cke offset /  98  /   2  /  36
Cke invertpiclk / Ctl invertpiclk / 0x0  /  0x0
N1: getComplexClkSetupTime defaultOffset = 0
N1: getComplexClkSetupTime = 0
ClkSetupTime = 38
N1: getComplexDqSetupTime defaultOffset = 0
N1: getComplexDqSetupTime = 0
N1.C1.S00: txdqoffset delta = 0, dq invertpiclk = 0
N1: getComplexDqsSetupTime defaultOffset = 40
N1: getComplexDqsSetupTime = 40
N1.C1.S00: txdqsoffset delta = 40
N1: getComplexRcvEnSetupTime defaultOffset = 37
N1: getComplexRcvEnSetupTime = 37
N1.C1.S00: rcvenoffset delta = 37
N1.C1.S00: Final txdqoffset / txdqsoffset / rcvenoffset / 56 / 32 / 29
N1: getComplexDqSetupTime defaultOffset = 0
N1: getComplexDqSetupTime = 0
N1.C1.S01: txdqoffset delta = 0, dq invertpiclk = 0
N1: getComplexDqsSetupTime defaultOffset = 40
N1: getComplexDqsSetupTime = 40
N1.C1.S01: txdqsoffset delta = 40
N1: getComplexRcvEnSetupTime defaultOffset = 37
N1: getComplexRcvEnSetupTime = 37
N1.C1.S01: rcvenoffset delta = 37
N1.C1.S01: Final txdqoffset / txdqsoffset / rcvenoffset / 25 /  1 / 62
N1: getComplexDqSetupTime defaultOffset = 0
N1: getComplexDqSetupTime = 0
N1.C1.S02: txdqoffset delta = 0, dq invertpiclk = 0
N1: getComplexDqsSetupTime defaultOffset = 40
N1: getComplexDqsSetupTime = 40
N1.C1.S02: txdqsoffset delta = 40
N1: getComplexRcvEnSetupTime defaultOffset = 37
N1: getComplexRcvEnSetupTime = 37
N1.C1.S02: rcvenoffset delta = 37
N1.C1.S02: Final txdqoffset / txdqsoffset / rcvenoffset / 59 / 35 / 32
N1: getComplexDqSetupTime defaultOffset = 0
N1: getComplexDqSetupTime = 0
N1.C1.S03: txdqoffset delta = 0, dq invertpiclk = 0
N1: getComplexDqsSetupTime defaultOffset = 40
N1: getComplexDqsSetupTime = 40
N1.C1.S03: txdqsoffset delta = 40
N1: getComplexRcvEnSetupTime defaultOffset = 37
N1: getComplexRcvEnSetupTime = 37
N1.C1.S03: rcvenoffset delta = 37
N1.C1.S03: Final txdqoffset / txdqsoffset / rcvenoffset / 29 /  5 /  2
N1: getComplexDqSetupTime defaultOffset = 0
N1: getComplexDqSetupTime = 0
N1.C1.S04: txdqoffset delta = 0, dq invertpiclk = 3
N1: getComplexDqsSetupTime defaultOffset = 40
N1: getComplexDqsSetupTime = 40
N1.C1.S04: txdqsoffset delta = 40
N1: getComplexRcvEnSetupTime defaultOffset = 37
N1: getComplexRcvEnSetupTime = 37
N1.C1.S04: rcvenoffset delta = 37
N1.C1.S04: Final txdqoffset / txdqsoffset / rcvenoffset /  0 / 40 / 37
N1: getComplexDqSetupTime defaultOffset = 0
N1: getComplexDqSetupTime = 0
N1.C1.S05: txdqoffset delta = 0, dq invertpiclk = 0
N1: getComplexDqsSetupTime defaultOffset = 40
N1: getComplexDqsSetupTime = 40
N1.C1.S05: txdqsoffset delta = 40
N1: getComplexRcvEnSetupTime defaultOffset = 37
N1: getComplexRcvEnSetupTime = 37
N1.C1.S05: rcvenoffset delta = 37
N1.C1.S05: Final txdqoffset / txdqsoffset / rcvenoffset / 30 /  6 /  3
N1: getComplexDqSetupTime defaultOffset = 0
N1: getComplexDqSetupTime = 0
N1.C1.S06: txdqoffset delta = 0, dq invertpiclk = 0
N1: getComplexDqsSetupTime defaultOffset = 40
N1: getComplexDqsSetupTime = 40
N1.C1.S06: txdqsoffset delta = 40
N1: getComplexRcvEnSetupTime defaultOffset = 37
N1: getComplexRcvEnSetupTime = 37
N1.C1.S06: rcvenoffset delta = 37
N1.C1.S06: Final txdqoffset / txdqsoffset / rcvenoffset / 60 / 36 / 33
N1: getComplexDqSetupTime defaultOffset = 0
N1: getComplexDqSetupTime = 0
N1.C1.S07: txdqoffset delta = 0, dq invertpiclk = 0
N1: getComplexDqsSetupTime defaultOffset = 40
N1: getComplexDqsSetupTime = 40
N1.C1.S07: txdqsoffset delta = 40
N1: getComplexRcvEnSetupTime defaultOffset = 37
N1: getComplexRcvEnSetupTime = 37
N1.C1.S07: rcvenoffset delta = 37
N1.C1.S07: Final txdqoffset / txdqsoffset / rcvenoffset / 27 /  3 /  0
N1: getComplexDqSetupTime defaultOffset = 0
N1: getComplexDqSetupTime = 0
N1.C1.S08: txdqoffset delta = 0, dq invertpiclk = 3
N1: getComplexDqsSetupTime defaultOffset = 40
N1: getComplexDqsSetupTime = 40
N1.C1.S08: txdqsoffset delta = 40
N1: getComplexRcvEnSetupTime defaultOffset = 37
N1: getComplexRcvEnSetupTime = 37
N1.C1.S08: rcvenoffset delta = 37
N1.C1.S08: Final txdqoffset / txdqsoffset / rcvenoffset /  0 / 40 / 37

N3.C0: SELF CAL 
N5.C3: nRFC = 174
N7.C2: nWR = 10
N5.C3: casSup = 0xFC
N7.C2: nFAW = 20
N5.C3: trrMode = 0
N7.C2: nRC = 33
N5.C3: twoXRefresh = 0
N7.C2: nRFC = 174
N3.C0: JckCompCodeCheck: Phase 1 - Comp Code Results
N5.C3: t_stagger_ref = 0x86
N7.C2: casSup = 0xFC
N1: SetupJckSmbCfg: JCK VLINFREQ set to: 0x820F1028
N3.C0: Cycle ron_up ron_eq_up ron_dn ron_eq_dn odt scomp_up scom_dn tcomp_l2h tcomp_h2l   bad_training
N5.C3: tcsrftp.Bits.t_xsdll = 512
N7.C2: trrMode = 0
N1: SetupJckSmbCfg: PLL is locked.
N5.C3: Common CL = 9
Common CWL = 7
N7.C2: twoXRefresh = 0
N1.C0: SetupJckSmbCfg: dlyFrms = 15
N5: PreVmseTraining
N7.C2: t_stagger_ref = 0x86
N5.C0: InitHostVmseCfg
N7.C2: tcsrftp.Bits.t_xsdll = 512
N1.C0: cwleffective = 8
N3.C0:  0       42     42       39      33      38     16      16       31        8       0
N5.C0: vmse_wr_turnaround = 0x7 
N7.C2: Common CL = 9
Common CWL = 7
N1.C0: PreVMSE Training raw cleff = 9, raw cwleff = 7
N5.C2: InitHostVmseCfg
N7: Memory Timings:
N5.C2: vmse_wr_turnaround = 0x7 
N7.C3: nCL = 9
N1.C0: vmseratio = 0, revisionId = 5, vmse_mode = 1, QCRM_ENABLE = 0
N5: HsxInitDdrioInterface
N7.C3: nCWL = 7
N3.C0:  1       21     21       20      14      38     16      16        8       31       0
N5.C0: rxVref = 0x5F
N7.C3: nRP = 9
N1: SetupJckSmbCfg: JCK wpsyncrcven = 5, wpsyncdata = 10
N5.C1: rxVref = 0x5F
N7.C3: nRCD = 9
N5: HsxVmseCompInit
N7.C3: nRRD = 4
N5: VmseCrossoverCalib
N5: Enable xovercal
N5: vmse_modes =          1,  0
N5.C0: piDelay CMDn  CMDs  CTL  CKE  CLK   0  1  2  3  4  5  6  7  8  9 10 11 12 13 14 15 16 17
          0       0     0    0    0    0   1  1  1  1  0  0  1  1  0  1  1  1  1  0  0  1  1  0 
          1       0     0    0    0    0   1  1  1  1  0  0  1  1  0  1  1  1  1  0  0  1  1  0 
          2       0     0    0    0    0   1  1  1  1  0  1  1  1  0  1  1  1  1  0  1  1  1  0 
          3       0     0    1    0    0   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
          4       0     0    1    1    0   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
          5       0     0    1    1    0   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
          6       0     0    1    1    0   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
          7       0     0    1    1    0   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
          8       0     0    1    1    0   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
          9       0     0    1    1    0   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         10       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         11       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         12       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         13       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         14       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         15       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         16       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         17       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         18       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         19       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         20       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         21       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         22       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         23       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         24       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         25       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         26       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         27       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         28       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         29       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         30       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         31       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         32       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         33       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         34       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         35       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         36       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         37       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         38       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         39       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         40       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         41       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         42       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         43       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         44       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         45       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         46       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         47       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         48       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         49       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         50       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         51       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         52       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         53       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         54       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         55       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         56       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         57       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         58       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         59       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         60       0     0    1    1    1   0  1  1  1  1  1  1  1  1  0  1  1  1  1  1  1  1  1 
         61       0     0    1    1    1   X  1  1  1  1  1  1  1  1  X  1  1  1  1  1  1  1  1 
         62       0     0    1    1    1   X  1  1  1  1  1  1  1  1  X  1  1  1  1  1  1  1  1 
         63       0     0    1    1    1   X  0  1  1  1  1  1  1  1  X  0  1  1  1  1  1  1  1 
N5.C0: setting ddrcrinvertpiclk
          0       0     0    1    1    1   X  X  0  1  1  1  0  0  1  X  X  0  1  1  1  0  0  1 
          1       0     0    1    1    1   X  X  0  0  1  1  0  0  1  X  X  0  0  1  1  0  0  1 
          2       0     0    1    1    1   X  X  0  X  1  1  0  0  1  X  X  0  X  1  1  0  0  1 
          3       0     0    1    1    1   X  X  0  X  1  0  0  0  1  X  X  0  X  1  0  0  0  1 
          4       0     0    0    1    1   X  X  0  X  0  X  0  0  0  X  X  0  X  0  X  0  0  0 
          5       0     0    X    0    1   X  X  0  X  X  X  0  0  X  X  X  0  X  X  X  0  0  X 
          6       0     0    X    X    1   X  X  0  X  X  X  0  0  X  X  X  0  X  X  X  0  0  X 
          7       0     0    X    X    1   X  X  0  X  X  X  0  0  X  X  X  0  X  X  X  0  0  X 
          8       0     0    X    X    1   X  X  0  X  X  X  0  0  X  X  X  0  X  X  X  0  0  X 
          9       0     0    X    X    1   X  X  0  X  X  X  0  0  X  X  X  0  X  X  X  0  0  X 
         10       0     0    X    X    1   X  X  0  X  X  X  0  0  X  X  X  0  X  X  X  0  0  X 
         11       0     0    X    X    0   X  X  0  X  X  X  0  0  X  X  X  0  X  X  X  0  0  X 
         12       0     0    X    X    X   X  X  0  X  X  X  0  0  X  X  X  0  X  X  X  0  0  X 
         13       0     0    X    X    X   X  X  0  X  X  X  0  0  X  X  X  0  X  X  X  0  0  X 
         14       0     0    X    X    X   X  X  0  X  X  X  0  0  X  X  X  0  X  X  X  0  0  X 
         15       0     0    X    X    X   X  X  0  X  X  X  0  0  X  X  X  0  X  X  X  0  0  X 
         16       0     0    X    X    X   X  X  0  X  X  X  0  0  X  X  X  0  X  X  X  0  0  X 
         17       0     0    X    X    X   X  X  0  X  X  X  0  0  X  X  X  0  X  X  X  0  0  X 
         18       0     0    X    X    X   X  X  0  X  X  X  0  0  X  X  X  0  X  X  X  0  0  X 
         19       0     0    X    X    X   X  X  0  X  X  X  0  0  X  X  X  0  X  X  X  0  0  X 
         20       0     0    X    X    X   X  X  0  X  X  X  0  0  X  X  X  0  X  X  X  0  0  X 
         21       0     0    X    X    X   X  X  0  X  X  X  0  0  X  X  X  0  X  X  X  0  0  X 
         22       0     0    X    X    X   X  X  0  X  X  X  0  0  X  X  X  0  X  X  X  0  0  X 
         23       0     0    X    X    X   X  X  0  X  X  X  0  0  X  X  X  0  X  X  X  0  0  X 
         24       0     0    X    X    X   X  X  0  X  X  X  0  0  X  X  X  0  X  X  X  0  0  X 
         25       0     0    X    X    X   X  X  0  X  X  X  0  0  X  X  X  0  X  X  X  0  0  X 
         26       0     0    X    X    X   X  X  0  X  X  X  0  0  X  X  X  0  X  X  X  0  0  X 
         27       0     0    X    X    X   X  X  0  X  X  X  0  0  X  X  X  0  X  X  X  0  0  X 
         28       0     0    X    X    X   X  X  0  X  X  X  0  0  X  X  X  0  X  X  X  0  0  X 
         29       0     0    X    X    X   X  X  0  X  X  X  0  0  X  X  X  0  X  X  X  0  0  X 
         30       0     0    X    X    X   X  X  0  X  X  X  0  0  X  X  X  0  X  X  X  0  0  X 
         31       0     0    X    X    X   X  X  0  X  X  X  0  0  X  X  X  0  X  X  X  0  0  X 
         32       0     0    X    X    X   X  X  0  X  X  X  0  0  X  X  X  0  X  X  X  0  0  X 
         33       0     0    X    X    X   X  X  0  X  X  X  0  0  X  X  X  0  X  X  X  0  0  X 
         34       0     0    X    X    X   X  X  0  X  X  X  0  0  X  X  X  0  X  X  X  0  0  X 
         35       0     0    X    X    X   X  X  0  X  X  X  0  0  X  X  X  0  X  X  X  0  0  X 
         36       0     0    X    X    X   X  X  0  X  X  X  0  0  X  X  X  0  X  X  X  0  0  X 
         37       0     0    X    X    X   X  X  0  X  X  X  0  0  X  X  X  0  X  X  X  0  0  X 
         38       0     0    X    X    X   X  X  0  X  X  X  0  0  X  X  X  0  X  X  X  0  0  X 
         39       0     0    X    X    X   X  X  0  X  X  X  0  0  X  X  X  0  X  X  X  0  0  X 
         40       0     0    X    X    X   X  X  0  X  X  X  0  0  X  X  X  0  X  X  X  0  0  X 
         41       0     0    X    X    X   X  X  0  X  X  X  0  0  X  X  X  0  X  X  X  0  0  X 
         42       0     0    X    X    X   X  X  0  X  X  X  0  0  X  X  X  0  X  X  X  0  0  X 
         43       0     0    X    X    X   X  X  0  X  X  X  0  0  X  X  X  0  X  X  X  0  0  X 
         44       0     0    X    X    X   X  X  0  X  X  X  0  0  X  X  X  0  X  X  X  0  0  X 
         45       0     0    X    X    X   X  X  0  X  X  X  0  0  X  X  X  0  X  X  X  0  0  X 
         46       0     0    X    X    X   X  X  0  X  X  X  0  0  X  X  X  0  X  X  X  0  0  X 
         47       0     0    X    X    X   X  X  0  X  X  X  0  0  X  X  X  0  X  X  X  0  0  X 
         48       0     0    X    X    X   X  X  0  X  X  X  0  0  X  X  X  0  X  X  X  0  0  X 
         49       0     0    X    X    X   X  X  0  X  X  X  0  0  X  X  X  0  X  X  X  0  0  X 
         50       0     0    X    X    X   X  X  0  X  X  X  0  0  X  X  X  0  X  X  X  0  0  X 
         51       0     0    X    X    X   X  X  0  X  X  X  0  0  X  X  X  0  X  X  X  0  0  X 
         52       0     0    X    X    X   X  X  0  X  X  X  0  0  X  X  X  0  X  X  X  0  0  X 
         53       0     0    X    X    X   X  X  0  X  X  X  0  0  X  X  X  0  X  X  X  0  0  X 
         54       0     0    X    X    X   X  X  0  X  X  X  0  0  X  X  X  0  X  X  X  0  0  X 
         55       0     0    X    X    X   X  X  0  X  X  X  0  0  X  X  X  0  X  X  X  0  0  X 
         56       0     0    X    X    X   X  X  0  X  X  X  0  0  X  X  X  0  X  X  X  0  0  X 
         57       0     0    X    X    X   X  X  0  X  X  X  0  0  X  X  X  0  X  X  X  0  0  X 
         58       0     0    X    X    X   X  X  0  X  X  X  0  0  X  X  X  0  X  X  X  0  0  X 
         59       0     0    X    X    X   X  X  0  X  X  X  0  0  X  X  X  0  X  X  X  0  0  X 
         60       0     0    X    X    X   X  X  0  X  X  X  0  0  X  X  X  0  X  X  X  0  0  X 
         61       0     0    X    X    X   X  X  0  X  X  X  0  0  X  X  X  0  X  X  X  0  0  X 
         62       0     0    X    X    X   X  X  0  X  X  X  0  0  X  X  X  0  X  X  X  0  0  X 
         63       0     0    X    X    X   X  X  1  X  X  X  0  0  X  X  X  1  X  X  X  0  0  X 
N5.C0: CMD-N xovercal offset = 0
N5.C0: CMD-S xovercal offset = 0
N5.C0: CTL xovercal offset   = 4
N5.C0: CKE xovercal offset   = 5
N5.C0: CLK xovercal offset   = 11
N5.C0.S18: STROBE                     0   1   2   3   4   5   6   7   8   9  10  11  12  13  14  15  16  17
N5.C0.S18: Rec En xovercal offset =  60  63   0   1   4   3   0   0   4  60  63   0   1   4   3   0   0   4 
N5.C0.S18: Tx Dqs xovercal offset =  60  63   0  63  63  63   0   0  63  63  63   0  63  63  63   0   0  63 
N5.C0.S18: Tx Dq xovercal offset  =  60  63   0   1   4   3   0   0   4  60  63   0   1   4   3   0   0   4 
N5.C0:         CMDn  CMDs  CTL  CKE  CLK   0  1  2  3  4  5  6  7  8
N5.C0: offsets:  0     0     4N5: getComplexCkeSetupTime defaultOffset = 98
N5: getComplexCkeSetupTime = 98
    5   11
Ctl Offsets Delta / final ctl offset / final cke offset /  98  /  38  /   7
Cke invertpiclk / Ctl invertpiclk / 0x0  /  0x0
N5: getComplexClkSetupTime defaultOffset = 0
N5: getComplexClkSetupTime = 0
ClkSetupTime = 11
N5: getComplexDqSetupTime defaultOffset = 0
N5: getComplexDqSetupTime = 0
N5.C0.S00: txdqoffset delta = 0, dq invertpiclk = 0
N5: getComplexDqsSetupTime defaultOffset = 40
N5: getComplexDqsSetupTime = 40
N5.C0.S00: txdqsoffset delta = 40
N5: getComplexRcvEnSetupTime defaultOffset = 37
N5: getComplexRcvEnSetupTime = 37
N5.C0.S00: rcvenoffset delta = 37
N5.C0.S00: Final txdqoffset / txdqsoffset / rcvenoffset / 28 /  4 /  1
N5: getComplexDqSetupTime defaultOffset = 0
N5: getComplexDqSetupTime = 0
N5.C0.S01: txdqoffset delta = 0, dq invertpiclk = 0
N5: getComplexDqsSetupTime defaultOffset = 40
N5: getComplexDqsSetupTime = 40
N5.C0.S01: txdqsoffset delta = 40
N5: getComplexRcvEnSetupTime defaultOffset = 37
N5: getComplexRcvEnSetupTime = 37
N5.C0.S01: rcvenoffset delta = 37
N5.C0.S01: Final txdqoffset / txdqsoffset / rcvenoffset / 63 / 39 / 36
N5: getComplexDqSetupTime defaultOffset = 0
N5: getComplexDqSetupTime = 0
N5.C0.S02: txdqoffset delta = 0, dq invertpiclk = 3
N5: getComplexDqsSetupTime defaultOffset = 40
N5: getComplexDqsSetupTime = 40
N5.C0.S02: txdqsoffset delta = 40
N5: getComplexRcvEnSetupTime defaultOffset = 37
N5: getComplexRcvEnSetupTime = 37
N5.C0.S02: rcvenoffset delta = 37
N5.C0.S02: Final txdqoffset / txdqsoffset / rcvenoffset / 32 /  8 /  5
N5: getComplexDqSetupTime defaultOffset = 0
N5: getComplexDqSetupTime = 0
N5.C0.S03: txdqoffset delta = 0, dq invertpiclk = 3
N5: getComplexDqsSetupTime defaultOffset = 40
N5: getComplexDqsSetupTime = 40
N5.C0.S03: txdqsoffset delta = 40
N5: getComplexRcvEnSetupTime defaultOffset = 37
N5: getComplexRcvEnSetupTime = 37
N5.C0.S03: rcvenoffset delta = 37
N5.C0.S03: Final txdqoffset / txdqsoffset / rcvenoffset /  1 / 41 / 38
N5: getComplexDqSetupTime defaultOffset = 0
N5: getComplexDqSetupTime = 0
N5.C0.S04: txdqoffset delta = 0, dq invertpiclk = 3
N5: getComplexDqsSetupTime defaultOffset = 40
N5: getComplexDqsSetupTime = 40
N5.C0.S04: txdqsoffset delta = 40
N5: getComplexRcvEnSetupTime defaultOffset = 37
N5: getComplexRcvEnSetupTime = 37
N5.C0.S04: rcvenoffset delta = 37
N5.C0.S04: Final txdqoffset / txdqsoffset / rcvenoffset / 36 / 12 /  9
N5: getComplexDqSetupTime defaultOffset = 0
N5: getComplexDqSetupTime = 0
N5.C0.S05: txdqoffset delta = 0, dq invertpiclk = 3
N5: getComplexDqsSetupTime defaultOffset = 40
N5: getComplexDqsSetupTime = 40
N5.C0.S05: txdqsoffset delta = 40
N5: getComplexRcvEnSetupTime defaultOffset = 37
N5: getComplexRcvEnSetupTime = 37
N5.C0.S05: rcvenoffset delta = 37
N5.C0.S05: Final txdqoffset / txdqsoffset / rcvenoffset /  3 / 43 / 40
N5: getComplexDqSetupTime defaultOffset = 0
N5: getComplexDqSetupTime = 0
N5.C0.S06: txdqoffset delta = 0, dq invertpiclk = 3
N5: getComplexDqsSetupTime defaultOffset = 40
N5: getComplexDqsSetupTime = 40
N5.C0.S06: txdqsoffset delta = 40
N5: getComplexRcvEnSetupTime defaultOffset = 37
N5: getComplexRcvEnSetupTime = 37
N5.C0.S06: rcvenoffset delta = 37
N5.C0.S06: Final txdqoffset / txdqsoffset / rcvenoffset / 32 /  8 /  5
N5: getComplexDqSetupTime defaultOffset = 0
N5: getComplexDqSetupTime = 0
N5.C0.S07: txdqoffset delta = 0, dq invertpiclk = 3
N5: getComplexDqsSetupTime defaultOffset = 40
N5: getComplexDqsSetupTime = 40
N5.C0.S07: txdqsoffset delta = 40
N5: getComplexRcvEnSetupTime defaultOffset = 37
N5: getComplexRcvEnSetupTime = 37
N5.C0.S07: rcvenoffset delta = 37
N5.C0.S07: Final txdqoffset / txdqsoffset / rcvenoffset /  0 / 40 / 37
N5: getComplexDqSetupTime defaultOffset = 0
N5: getComplexDqSetupTime = 0
N5.C0.S08: txdqoffset delta = 0, dq invertpiclk = 3
N5: getComplexDqsSetupTime defaultOffset = 40
N5: getComplexDqsSetupTime = 40
N5.C0.S08: txdqsoffset delta = 40
N5: getComplexRcvEnSetupTime defaultOffset = 37
N5: getComplexRcvEnSetupTime = 37
N5.C0.S08: rcvenoffset delta = 37
N5.C0.S08: Final txdqoffset / txdqsoffset / rcvenoffset / 36 / 12 /  9

N5: vmse_modes =          1,  0
N5.C1: piDelay CMDn  CMDs  CTL  CKE  CLK   0  1  2  3  4  5  6  7  8  9 10 11 12 13 14 15 16 17
          0       0     0    1    0    0   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
          1       0     0    1    1    0   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
          2       0     0    1    1    0   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
          3       0     0    1    1    0   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
          4       0     0    1    1    0   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
          5       0     0    1    1    0   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
          6       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
          7       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
          8       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
          9       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         10       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         11       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         12       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         13       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         14       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         15       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         16       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         17       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         18       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         19       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         20       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         21       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         22       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         23       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         24       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         25       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         26       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         27       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         28       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         29       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         30       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         31       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         32       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         33       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         34       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         35       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         36       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         37       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         38       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         39       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         40       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         41       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         42       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         43       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         44       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         45       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         46       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         47       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         48       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         49       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         50       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         51       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         52       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         53       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         54       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         55       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         56       0     0    1    1    1   0  1  1  1  1  1  1  1  1  0  1  1  1  1  1  1  1  1 
         57       0     0    1    1    1   X  1  1  1  1  1  1  1  1  X  1  1  1  1  1  1  1  1 
         58       0     0    1    1    1   X  0  1  1  1  1  1  1  1  X  0  1  1  1  1  1  1  1 
         59       0     0    1    1    1   X  X  1  1  1  1  1  1  1  X  X  1  1  1  1  1  1  1 
         60       0     0    1    1    1   X  X  0  1  1  1  1  0  1  X  X  0  1  1  1  1  0  1 
         61       0     0    1    1    1   X  X  X  0  1  1  1  X  1  X  X  X  0  1  1  1  X  1 
         62       0     0    1    1    1   X  X  X  X  1  0  0  X  1  X  X  X  X  1  0  0  X  1 
         63       0     0    1    1    1   X  X  X  X  1  X  X  X  1  X  X  X  X  1  X  X  X  1 
N5.C1: setting ddrcrinvertpiclk
          0       0     0    0    1    1   X  X  X  X  1  X  X  X  0  X  X  X  X  1  X  X  X  0 
          1       0     0    0    1    1   X  X  X  X  0  X  X  X  0  X  X  X  X  0  X  X  X  0 
          2       0     0    0    1    1   X  X  X  X  X  X  X  X  0  X  X  X  X  X  X  X  X  0 
          3       0     0    0    0    1   X  X  X  X  X  X  X  X  0  X  X  X  X  X  X  X  X  0 
          4       0     0    0    X    1   X  X  X  X  X  X  X  X  0  X  X  X  X  X  X  X  X  0 
          5       0     0    0    X    1   X  X  X  X  X  X  X  X  0  X  X  X  X  X  X  X  X  0 
          6       0     0    0    X    1   X  X  X  X  X  X  X  X  0  X  X  X  X  X  X  X  X  0 
          7       0     0    0    X    0   X  X  X  X  X  X  X  X  0  X  X  X  X  X  X  X  X  0 
          8       0     0    0    X    X   X  X  X  X  X  X  X  X  0  X  X  X  X  X  X  X  X  0 
          9       0     0    0    X    X   X  X  X  X  X  X  X  X  0  X  X  X  X  X  X  X  X  0 
         10       0     0    0    X    X   X  X  X  X  X  X  X  X  0  X  X  X  X  X  X  X  X  0 
         11       0     0    0    X    X   X  X  X  X  X  X  X  X  0  X  X  X  X  X  X  X  X  0 
         12       0     0    0    X    X   X  X  X  X  X  X  X  X  0  X  X  X  X  X  X  X  X  0 
         13       0     0    0    X    X   X  X  X  X  X  X  X  X  0  X  X  X  X  X  X  X  X  0 
         14       0     0    0    X    X   X  X  X  X  X  X  X  X  0  X  X  X  X  X  X  X  X  0 
         15       0     0    0    X    X   X  X  X  X  X  X  X  X  0  X  X  X  X  X  X  X  X  0 
         16       0     0    0    X    X   X  X  X  X  X  X  X  X  0  X  X  X  X  X  X  X  X  0 
         17       0     0    0    X    X   X  X  X  X  X  X  X  X  0  X  X  X  X  X  X  X  X  0 
         18       0     0    0    X    X   X  X  X  X  X  X  X  X  0  X  X  X  X  X  X  X  X  0 
         19       0     0    0    X    X   X  X  X  X  X  X  X  X  0  X  X  X  X  X  X  X  X  0 
         20       0     0    0    X    X   X  X  X  X  X  X  X  X  0  X  X  X  X  X  X  X  X  0 
         21       0     0    0    X    X   X  X  X  X  X  X  X  X  0  X  X  X  X  X  X  X  X  0 
         22       0     0    0    X    X   X  X  X  X  X  X  X  X  0  X  X  X  X  X  X  X  X  0 
         23       0     0    0    X    X   X  X  X  X  X  X  X  X  0  X  X  X  X  X  X  X  X  0 
         24       0     0    0    X    X   X  X  X  X  X  X  X  X  0  X  X  X  X  X  X  X  X  0 
         25       0     0    0    X    X   X  X  X  X  X  X  X  X  0  X  X  X  X  X  X  X  X  0 
         26       0     0    0    X    X   X  X  X  X  X  X  X  X  0  X  X  X  X  X  X  X  X  0 
         27       0     0    0    X    X   X  X  X  X  X  X  X  X  0  X  X  X  X  X  X  X  X  0 
         28       0     0    0    X    X   X  X  X  X  X  X  X  X  0  X  X  X  X  X  X  X  X  0 
         29       0     0    0    X    X   X  X  X  X  X  X  X  X  0  X  X  X  X  X  X  X  X  0 
         30       0     0    0    X    X   X  X  X  X  X  X  X  X  0  X  X  X  X  X  X  X  X  0 
         31       0     0    0    X    X   X  X  X  X  X  X  X  X  0  X  X  X  X  X  X  X  X  0 
         32       0     0    0    X    X   X  X  X  X  X  X  X  X  0  X  X  X  X  X  X  X  X  0 
         33       0     0    0    X    X   X  X  X  X  X  X  X  X  0  X  X  X  X  X  X  X  X  0 
         34       0     0    0    X    X   X  X  X  X  X  X  X  X  0  X  X  X  X  X  X  X  X  0 
         35       0     0    0    X    X   X  X  X  X  X  X  X  X  0  X  X  X  X  X  X  X  X  0 
         36       0     0    0    X    X   X  X  X  X  X  X  X  X  0  X  X  X  X  X  X  X  X  0 
         37       0     0    0    X    X   X  X  X  X  X  X  X  X  0  X  X  X  X  X  X  X  X  0 
         38       0     0    0    X    X   X  X  X  X  X  X  X  X  0  X  X  X  X  X  X  X  X  0 
         39       0     0    0    X    X   X  X  X  X  X  X  X  X  0  X  X  X  X  X  X  X  X  0 
         40       0     0    0    X    X   X  X  X  X  X  X  X  X  0  X  X  X  X  X  X  X  X  0 
         41       0     0    0    X    X   X  X  X  X  X  X  X  X  0  X  X  X  X  X  X  X  X  0 
         42       0     0    0    X    X   X  X  X  X  X  X  X  X  0  X  X  X  X  X  X  X  X  0 
         43       0     0    0    X    X   X  X  X  X  X  X  X  X  0  X  X  X  X  X  X  X  X  0 
         44       0     0    0    X    X   X  X  X  X  X  X  X  X  0  X  X  X  X  X  X  X  X  0 
         45       0     0    0    X    X   X  X  X  X  X  X  X  X  0  X  X  X  X  X  X  X  X  0 
         46       0     0    0    X    X   X  X  X  X  X  X  X  X  0  X  X  X  X  X  X  X  X  0 
         47       0     0    0    X    X   X  X  X  X  X  X  X  X  0  X  X  X  X  X  X  X  X  0 
         48       0     0    0    X    X   X  X  X  X  X  X  X  X  0  X  X  X  X  X  X  X  X  0 
         49       0     0    0    X    X   X  X  X  X  X  X  X  X  0  X  X  X  X  X  X  X  X  0 
         50       0     0    0    X    X   X  X  X  X  X  X  X  X  0  X  X  X  X  X  X  X  X  0 
         51       0     0    0    X    X   X  X  X  X  X  X  X  X  0  X  X  X  X  X  X  X  X  0 
         52       0     0    0    X    X   X  X  X  X  X  X  X  X  0  X  X  X  X  X  X  X  X  0 
         53       0     0    0    X    X   X  X  X  X  X  X  X  X  0  X  X  X  X  X  X  X  X  0 
         54       0     0    0    X    X   X  X  X  X  X  X  X  X  0  X  X  X  X  X  X  X  X  0 
         55       0     0    0    X    X   X  X  X  X  X  X  X  X  0  X  X  X  X  X  X  X  X  0 
         56       0     0    0    X    X   X  X  X  X  X  X  X  X  0  X  X  X  X  X  X  X  X  0 
         57       0     0    0    X    X   X  X  X  X  X  X  X  X  0  X  X  X  X  X  X  X  X  0 
         58       0     0    0    X    X   X  X  X  X  X  X  X  X  0  X  X  X  X  X  X  X  X  0 
         59       0     0    0    X    X   X  X  X  X  X  X  X  X  0  X  X  X  X  X  X  X  X  0 
         60       0     0    0    X    X   X  X  X  X  X  X  X  X  0  X  X  X  X  X  X  X  X  0 
         61       0     0    0    X    X   X  X  X  X  X  X  X  X  0  X  X  X  X  X  X  X  X  0 
         62       0     0    0    X    X   X  X  X  X  X  X  X  X  0  X  X  X  X  X  X  X  X  0 
         63       0     0    0    X    X   X  X  X  X  X  X  X  X  0  X  X  X  X  X  X  X  X  0 
N5.C1: CMD-N xovercal offset = 0
N5.C1: CMD-S xovercal offset = 0
N5.C1: CTL xovercal offset   = 0
N5.C1: CKE xovercal offset   = 3
N5.C1: CLK xovercal offset   = 7
N5.C1.S18: STROBE                     0   1   2   3   4   5   6   7   8   9  10  11  12  13  14  15  16  17
N5.C1.S18: Rec En xovercal offset =  56  58  60  61   1  62  62  60   0  56  58  60  61   1  62  62  60   0 
N5.C1.S18: Tx Dqs xovercal offset =  56  63  63  63  63  63  63  63   0  63  63  63  63  63  63  63  63   0 
N5.C1.S18: Tx Dq xovercal offset  =  56  58  60  61   1  62  62  60   0  56  58  60  61   1  62  62  60   0 
N5.C1:         CMDn  CMDs  CTL  CKE  CLK   0  1  2  3  4  5  6  7  8
N5.C1: offsets:  0     0     0N5: getComplexCkeSetupTime defaultOffset = 98
N5: getComplexCkeSetupTime = 98
    3    7
Ctl Offsets Delta / final ctl offset / final cke offset /  98  /   2  /  37
Cke invertpiclk / Ctl invertpiclk / 0x0  /  0x0
N5: getComplexClkSetupTime defaultOffset = 0
N5: getComplexClkSetupTime = 0
ClkSetupTime = 39
N5: getComplexDqSetupTime defaultOffset = 0
N5: getComplexDqSetupTime = 0
N5.C1.S00: txdqoffset delta = 0, dq invertpiclk = 0
N5: getComplexDqsSetupTime defaultOffset = 40
N5: getComplexDqsSetupTime = 40
N5.C1.S00: txdqsoffset delta = 40
N5: getComplexRcvEnSetupTime defaultOffset = 37
N5: getComplexRcvEnSetupTime = 37
N5.C1.S00: rcvenoffset delta = 37
N5.C1.S00: Final txdqoffset / txdqsoffset / rcvenoffset / 56 / 32 / 29
N5: getComplexDqSetupTime defaultOffset = 0
N5: getComplexDqSetupTime = 0
N5.C1.S01: txdqoffset delta = 0, dq invertpiclk = 0
N5: getComplexDqsSetupTime defaultOffset = 40
N5: getComplexDqsSetupTime = 40
N5.C1.S01: txdqsoffset delta = 40
N5: getComplexRcvEnSetupTime defaultOffset = 37
N5: getComplexRcvEnSetupTime = 37
N5.C1.S01: rcvenoffset delta = 37
N5.C1.S01: Final txdqoffset / txdqsoffset / rcvenoffset / 26 /  2 / 63
N5: getComplexDqSetupTime defaultOffset = 0
N5: getComplexDqSetupTime = 0
N5.C1.S02: txdqoffset delta = 0, dq invertpiclk = 0
N5: getComplexDqsSetupTime defaultOffset = 40
N5: getComplexDqsSetupTime = 40
N5.C1.S02: txdqsoffset delta = 40
N5: getComplexRcvEnSetupTime defaultOffset = 37
N5: getComplexRcvEnSetupTime = 37
N5.C1.S02: rcvenoffset delta = 37
N5.C1.S02: Final txdqoffset / txdqsoffset / rcvenoffset / 60 / 36 / 33
N5: getComplexDqSetupTime defaultOffset = 0
N5: getComplexDqSetupTime = 0
N5.C1.S03: txdqoffset delta = 0, dq invertpiclk = 0
N5: getComplexDqsSetupTime defaultOffset = 40
N5: getComplexDqsSetupTime = 40
N5.C1.S03: txdqsoffset delta = 40
N5: getComplexRcvEnSetupTime defaultOffset = 37
N5: getComplexRcvEnSetupTime = 37
N5.C1.S03: rcvenoffset delta = 37
N5.C1.S03: Final txdqoffset / txdqsoffset / rcvenoffset / 29 /  5 /  2
N5: getComplexDqSetupTime defaultOffset = 0
N5: getComplexDqSetupTime = 0
N5.C1.S04: txdqoffset delta = 0, dq invertpiclk = 3
N5: getComplexDqsSetupTime defaultOffset = 40
N5: getComplexDqsSetupTime = 40
N5.C1.S04: txdqsoffset delta = 40
N5: getComplexRcvEnSetupTime defaultOffset = 37
N5: getComplexRcvEnSetupTime = 37
N5.C1.S04: rcvenoffset delta = 37
N5.C1.S04: Final txdqoffset / txdqsoffset / rcvenoffset /  1 / 41 / 38
N5: getComplexDqSetupTime defaultOffset = 0
N5: getComplexDqSetupTime = 0
N5.C1.S05: txdqoffset delta = 0, dq invertpiclk = 0
N5: getComplexDqsSetupTime defaultOffset = 40
N5: getComplexDqsSetupTime = 40
N5.C1.S05: txdqsoffset delta = 40
N5: getComplexRcvEnSetupTime defaultOffset = 37
N5: getComplexRcvEnSetupTime = 37
N5.C1.S05: rcvenoffset delta = 37
N5.C1.S05: Final txdqoffset / txdqsoffset / rcvenoffset / 30 /  6 /  3
N5: getComplexDqSetupTime defaultOffset = 0
N5: getComplexDqSetupTime = 0
N5.C1.S06: txdqoffset delta = 0, dq invertpiclk = 0
N5: getComplexDqsSetupTime defaultOffset = 40
N5: getComplexDqsSetupTime = 40
N5.C1.S06: txdqsoffset delta = 40
N5: getComplexRcvEnSetupTime defaultOffset = 37
N5: getComplexRcvEnSetupTime = 37
N5.C1.S06: rcvenoffset delta = 37
N5.C1.S06: Final txdqoffset / txdqsoffset / rcvenoffset / 62 / 38 / 35
N5: getComplexDqSetupTime defaultOffset = 0
N5: getComplexDqSetupTime = 0
N5.C1.S07: txdqoffset delta = 0, dq invertpiclk = 0
N5: getComplexDqsSetupTime defaultOffset = 40
N5: getComplexDqsSetupTime = 40
N5.C1.S07: txdqsoffset delta = 40
N5: getComplexRcvEnSetupTime defaultOffset = 37
N5: getComplexRcvEnSetupTime = 37
N5.C1.S07: rcvenoffset delta = 37
N5.C1.S07: Final txdqoffset / txdqsoffset / rcvenoffset / 28 /  4 /  1
N5: getComplexDqSetupTime defaultOffset = 0
N5: getComplexDqSetupTime = 0
N5.C1.S08: txdqoffset delta = 0, dq invertpiclk = 3
N5: getComplexDqsSetupTime defaultOffset = 40
N5: getComplexDqsSetupTime = 40
N5.C1.S08: txdqsoffset delta = 40
N5: getComplexRcvEnSetupTime defaultOffset = 37
N5: getComplexRcvEnSetupTime = 37
N5.C1.S08: rcvenoffset delta = 37
N5.C1.S08: Final txdqoffset / txdqsoffset / rcvenoffset /  0 / 40 / 37

N7.C3: nWTR = 5
N1.C0: SELF CAL 
N3.C0:  2       42     42       39      34      38     16      16        8       31       0
N7.C3: nRAS = 24
N7.C3: nRTP = 5
N7.C3: nWR = 10
N1.C0: JckCompCodeCheck: Phase 1 - Comp Code Results
N7.C3: nFAW = 20
N1.C0: Cycle ron_up ron_eq_up ron_dn ron_eq_dn odt scomp_up scom_dn tcomp_l2h tcomp_h2l   bad_training
N5: SetupJckSmbCfg: JCK VLINFREQ set to: 0x820F1028
N7.C3: nRC = 33
N7.C3: nRFC = 174
N3.C0:  3       42     42       38      34      38     16      16       31        8       0
N5: SetupJckSmbCfg: PLL is locked.
N7.C3: casSup = 0xFC
N7.C3: trrMode = 0
N7.C3: twoXRefresh = 0
N5.C0: SetupJckSmbCfg: dlyFrms = 15
N7.C3: t_stagger_ref = 0x86
N1.C0:  0       41     41       38      31      38     14      14        8       31       0
N5.C0: cwleffective = 8
N7.C3: tcsrftp.Bits.t_xsdll = 512
N3.C0:  4       42     42       39      34      38     16      16        8       31       0
N5.C0: PreVMSE Training raw cleff = 9, raw cwleff = 7
N7.C3: Common CL = 9
Common CWL = 7
N7: PreVmseTraining
N7.C0: InitHostVmseCfg
N5.C0: vmseratio = 0, revisionId = 5, vmse_mode = 1, QCRM_ENABLE = 0
N7.C0: vmse_wr_turnaround = 0x7 
N1.C0:  1       41     41       39      29      38     14      14        8       31       0
N3.C0:  5       42     42       39      29      38     16      16       31        8       0
N5: SetupJckSmbCfg: JCK wpsyncrcven = 5, wpsyncdata = 10
N7.C2: InitHostVmseCfg
N7.C2: vmse_wr_turnaround = 0x7 
N7: HsxInitDdrioInterface
N7.C0: rxVref = 0x5F
N7.C1: rxVref = 0x5F
N7: HsxVmseCompInit
N7: VmseCrossoverCalib
N7: Enable xovercal
N7: vmse_modes =          1,  0
N7.C0: piDelay CMDn  CMDs  CTL  CKE  CLK   0  1  2  3  4  5  6  7  8  9 10 11 12 13 14 15 16 17
          0       0     0    0    0    0   1  1  1  1  0  1  1  1  1  1  1  1  1  0  1  1  1  1 
          1       0     0    1    0    0   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
          2       0     0    1    0    0   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
          3       0     0    1    1    0   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
          4       0     0    1    1    0   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
          5       0     0    1    1    0   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
          6       0     0    1    1    0   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
          7       0     0    1    1    0   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
          8       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
          9       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         10       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         11       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         12       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         13       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         14       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         15       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         16       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         17       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         18       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         19       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         20       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         21       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         22       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         23       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         24       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         25       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         26       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         27       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         28       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         29       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         30       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         31       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         32       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         33       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         34       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         35       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         36       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         37       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         38       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         39       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         40       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         41       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         42       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         43       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         44       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         45       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         46       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         47       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         48       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         49       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         50       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         51       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         52       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         53       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         54       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         55       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         56       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         57       0     0    1    1    1   0  1  1  1  1  1  1  1  1  0  1  1  1  1  1  1  1  1 
         58       0     0    1    1    1   X  1  1  1  1  1  1  1  1  X  1  1  1  1  1  1  1  1 
         59       0     0    1    1    1   X  1  1  1  1  1  1  1  1  X  1  1  1  1  1  1  1  1 
         60       0     0    1    1    1   X  0  1  1  1  1  1  1  1  X  0  1  1  1  1  1  1  1 
         61       0     0    1    1    1   X  X  1  1  1  1  1  1  1  X  X  1  1  1  1  1  1  1 
         62       0     0    1    1    1   X  X  0  1  1  1  0  0  1  X  X  0  1  1  1  0  0  1 
         63       0     0    1    1    1   X  X  X  1  1  1  X  X  1  X  X  X  1  1  1  X  X  1 
N7.C0: setting ddrcrinvertpiclk
          0       0     0    1    1    1   X  X  X  0  1  0  X  X  1  X  X  X  0  1  0  X  X  1 
          1       0     0    1    1    1   X  X  X  0  1  0  X  X  1  X  X  X  0  1  0  X  X  1 
          2       0     0    0    1    1   X  X  X  0  0  0  X  X  0  X  X  X  0  0  0  X  X  0 
          3       0     0    X    1    1   X  X  X  0  X  0  X  X  X  X  X  X  0  X  0  X  X  X 
          4       0     0    X    0    1   X  X  X  0  X  0  X  X  X  X  X  X  0  X  0  X  X  X 
          5       0     0    X    X    1   X  X  X  0  X  0  X  X  X  X  X  X  0  X  0  X  X  X 
          6       0     0    X    X    1   X  X  X  0  X  0  X  X  X  X  X  X  0  X  0  X  X  X 
          7       0     0    X    X    1   X  X  X  0  X  0  X  X  X  X  X  X  0  X  0  X  X  X 
          8       0     0    X    X    1   X  X  X  0  X  0  X  X  X  X  X  X  0  X  0  X  X  X 
          9       0     0    X    X    1   X  X  X  0  X  0  X  X  X  X  X  X  0  X  0  X  X  X 
         10       0     0    X    X    0   X  X  X  0  X  0  X  X  X  X  X  X  0  X  0  X  X  X 
         11       0     0    X    X    X   X  X  X  0  X  0  X  X  X  X  X  X  0  X  0  X  X  X 
         12       0     0    X    X    X   X  X  X  0  X  0  X  X  X  X  X  X  0  X  0  X  X  X 
         13       0     0    X    X    X   X  X  X  0  X  0  X  X  X  X  X  X  0  X  0  X  X  X 
         14       0     0    X    X    X   X  X  X  0  X  0  X  X  X  X  X  X  0  X  0  X  X  X 
         15       0     0    X    X    X   X  X  X  0  X  0  X  X  X  X  X  X  0  X  0  X  X  X 
         16       0     0    X    X    X   X  X  X  0  X  0  X  X  X  X  X  X  0  X  0  X  X  X 
         17       0     0    X    X    X   X  X  X  0  X  0  X  X  X  X  X  X  0  X  0  X  X  X 
         18       0     0    X    X    X   X  X  X  0  X  0  X  X  X  X  X  X  0  X  0  X  X  X 
         19       0     0    X    X    X   X  X  X  0  X  0  X  X  X  X  X  X  0  X  0  X  X  X 
         20       0     0    X    X    X   X  X  X  0  X  0  X  X  X  X  X  X  0  X  0  X  X  X 
         21       0     0    X    X    X   X  X  X  0  X  0  X  X  X  X  X  X  0  X  0  X  X  X 
         22       0     0    X    X    X   X  X  X  0  X  0  X  X  X  X  X  X  0  X  0  X  X  X 
         23       0     0    X    X    X   X  X  X  0  X  0  X  X  X  X  X  X  0  X  0  X  X  X 
         24       0     0    X    X    X   X  X  X  0  X  0  X  X  X  X  X  X  0  X  0  X  X  X 
         25       0     0    X    X    X   X  X  X  0  X  0  X  X  X  X  X  X  0  X  0  X  X  X 
         26       0     0    X    X    X   X  X  X  0  X  0  X  X  X  X  X  X  0  X  0  X  X  X 
         27       0     0    X    X    X   X  X  X  0  X  0  X  X  X  X  X  X  0  X  0  X  X  X 
         28       0     0    X    X    X   X  X  X  0  X  0  X  X  X  X  X  X  0  X  0  X  X  X 
         29       0     0    X    X    X   X  X  X  0  X  0  X  X  X  X  X  X  0  X  0  X  X  X 
         30       0     0    X    X    X   X  X  X  0  X  0  X  X  X  X  X  X  0  X  0  X  X  X 
         31       0     0    X    X    X   X  X  X  0  X  0  X  X  X  X  X  X  0  X  0  X  X  X 
         32       0     0    X    X    X   X  X  X  0  X  0  X  X  X  X  X  X  0  X  0  X  X  X 
         33       0     0    X    X    X   X  X  X  0  X  0  X  X  X  X  X  X  0  X  0  X  X  X 
         34       0     0    X    X    X   X  X  X  0  X  0  X  X  X  X  X  X  0  X  0  X  X  X 
         35       0     0    X    X    X   X  X  X  0  X  0  X  X  X  X  X  X  0  X  0  X  X  X 
         36       0     0    X    X    X   X  X  X  0  X  0  X  X  X  X  X  X  0  X  0  X  X  X 
         37       0     0    X    X    X   X  X  X  0  X  0  X  X  X  X  X  X  0  X  0  X  X  X 
         38       0     0    X    X    X   X  X  X  0  X  0  X  X  X  X  X  X  0  X  0  X  X  X 
         39       0     0    X    X    X   X  X  X  0  X  0  X  X  X  X  X  X  0  X  0  X  X  X 
         40       0     0    X    X    X   X  X  X  0  X  0  X  X  X  X  X  X  0  X  0  X  X  X 
         41       0     0    X    X    X   X  X  X  0  X  0  X  X  X  X  X  X  0  X  0  X  X  X 
         42       0     0    X    X    X   X  X  X  0  X  0  X  X  X  X  X  X  0  X  0  X  X  X 
         43       0     0    X    X    X   X  X  X  0  X  0  X  X  X  X  X  X  0  X  0  X  X  X 
         44       0     0    X    X    X   X  X  X  0  X  0  X  X  X  X  X  X  0  X  0  X  X  X 
         45       0     0    X    X    X   X  X  X  0  X  0  X  X  X  X  X  X  0  X  0  X  X  X 
         46       0     0    X    X    X   X  X  X  0  X  0  X  X  X  X  X  X  0  X  0  X  X  X 
         47       0     0    X    X    X   X  X  X  0  X  0  X  X  X  X  X  X  0  X  0  X  X  X 
         48       0     0    X    X    X   X  X  X  0  X  0  X  X  X  X  X  X  0  X  0  X  X  X 
         49       0     0    X    X    X   X  X  X  0  X  0  X  X  X  X  X  X  0  X  0  X  X  X 
         50       0     0    X    X    X   X  X  X  0  X  0  X  X  X  X  X  X  0  X  0  X  X  X 
         51       0     0    X    X    X   X  X  X  0  X  0  X  X  X  X  X  X  0  X  0  X  X  X 
         52       0     0    X    X    X   X  X  X  0  X  0  X  X  X  X  X  X  0  X  0  X  X  X 
         53       0     0    X    X    X   X  X  X  0  X  0  X  X  X  X  X  X  0  X  0  X  X  X 
         54       0     0    X    X    X   X  X  X  0  X  0  X  X  X  X  X  X  0  X  0  X  X  X 
         55       0     0    X    X    X   X  X  X  0  X  0  X  X  X  X  X  X  0  X  0  X  X  X 
         56       0     0    X    X    X   X  X  X  0  X  0  X  X  X  X  X  X  0  X  0  X  X  X 
         57       0     0    X    X    X   X  X  X  0  X  0  X  X  X  X  X  X  0  X  0  X  X  X 
         58       0     0    X    X    X   X  X  X  0  X  0  X  X  X  X  X  X  0  X  0  X  X  X 
         59       0     0    X    X    X   X  X  X  0  X  0  X  X  X  X  X  X  0  X  0  X  X  X 
         60       0     0    X    X    X   X  X  X  0  X  0  X  X  X  X  X  X  0  X  0  X  X  X 
         61       0     0    X    X    X   X  X  X  0  X  0  X  X  X  X  X  X  0  X  0  X  X  X 
         62       0     0    X    X    X   X  X  X  0  X  0  X  X  X  X  X  X  0  X  0  X  X  X 
         63       0     0    X    X    X   X  X  X  0  X  0  X  X  X  X  X  X  0  X  0  X  X  X 
N7.C0: CMD-N xovercal offset = 0
N7.C0: CMD-S xovercal offset = 0
N7.C0: CTL xovercal offset   = 2
N7.C0: CKE xovercal offset   = 4
N7.C0: CLK xovercal offset   = 10
N7.C0.S18: STROBE                     0   1   2   3   4   5   6   7   8   9  10  11  12  13  14  15  16  17
N7.C0.S18: Rec En xovercal offset =  57  60  62   0   2   0  62  62   2  57  60  62   0   2   0  62  62   2 
N7.C0.S18: Tx Dqs xovercal offset =  57  63  63   0  63   0  63  63  63  63  63  63   0  63   0  63  63  63 
N7.C0.S18: Tx Dq xovercal offset  =  57  60  62   0   2   0  62  62   2  57  60  62   0   2   0  62  62   2 
N7.C0:         CMDn  CMDs  CTL  CKE  CLK   0  1  2  3  4  5  6  7  8
N7.C0: offsets:  0     0     2N7: getComplexCkeSetupTime defaultOffset = 98
N7: getComplexCkeSetupTime = 98
    4   10
Ctl Offsets Delta / final ctl offset / final cke offset /  98  /  36  /   6
Cke invertpiclk / Ctl invertpiclk / 0x0  /  0x0
N7: getComplexClkSetupTime defaultOffset = 0
N7: getComplexClkSetupTime = 0
ClkSetupTime = 10
N7: getComplexDqSetupTime defaultOffset = 0
N7: getComplexDqSetupTime = 0
N7.C0.S00: txdqoffset delta = 0, dq invertpiclk = 0
N7: getComplexDqsSetupTime defaultOffset = 40
N7: getComplexDqsSetupTime = 40
N7.C0.S00: txdqsoffset delta = 40
N7: getComplexRcvEnSetupTime defaultOffset = 37
N7: getComplexRcvEnSetupTime = 37
N7.C0.S00: rcvenoffset delta = 37
N7.C0.S00: Final txdqoffset / txdqsoffset / rcvenoffset / 25 /  1 / 62
N7: getComplexDqSetupTime defaultOffset = 0
N7: getComplexDqSetupTime = 0
N7.C0.S01: txdqoffset delta = 0, dq invertpiclk = 0
N7: getComplexDqsSetupTime defaultOffset = 40
N7: getComplexDqsSetupTime = 40
N7.C0.S01: txdqsoffset delta = 40
N7: getComplexRcvEnSetupTime defaultOffset = 37
N7: getComplexRcvEnSetupTime = 37
N7.C0.S01: rcvenoffset delta = 37
N7.C0.S01: Final txdqoffset / txdqsoffset / rcvenoffset / 60 / 36 / 33
N7: getComplexDqSetupTime defaultOffset = 0
N7: getComplexDqSetupTime = 0
N7.C0.S02: txdqoffset delta = 0, dq invertpiclk = 0
N7: getComplexDqsSetupTime defaultOffset = 40
N7: getComplexDqsSetupTime = 40
N7.C0.S02: txdqsoffset delta = 40
N7: getComplexRcvEnSetupTime defaultOffset = 37
N7: getComplexRcvEnSetupTime = 37
N7.C0.S02: rcvenoffset delta = 37
N7.C0.S02: Final txdqoffset / txdqsoffset / rcvenoffset / 30 /  6 /  3
N7: getComplexDqSetupTime defaultOffset = 0
N7: getComplexDqSetupTime = 0
N7.C0.S03: txdqoffset delta = 0, dq invertpiclk = 3
N7: getComplexDqsSetupTime defaultOffset = 40
N7: getComplexDqsSetupTime = 40
N7.C0.S03: txdqsoffset delta = 40
N7: getComplexRcvEnSetupTime defaultOffset = 37
N7: getComplexRcvEnSetupTime = 37
N7.C0.S03: rcvenoffset delta = 37
N7.C0.S03: Final txdqoffset / txdqsoffset / rcvenoffset /  0 / 40 / 37
N7: getComplexDqSetupTime defaultOffset = 0
N7: getComplexDqSetupTime = 0
N7.C0.S04: txdqoffset delta = 0, dq invertpiclk = 3
N7: getComplexDqsSetupTime defaultOffset = 40
N7: getComplexDqsSetupTime = 40
N7.C0.S04: txdqsoffset delta = 40
N7: getComplexRcvEnSetupTime defaultOffset = 37
N7: getComplexRcvEnSetupTime = 37
N7.C0.S04: rcvenoffset delta = 37
N7.C0.S04: Final txdqoffset / txdqsoffset / rcvenoffset / 34 / 10 /  7
N7: getComplexDqSetupTime defaultOffset = 0
N7: getComplexDqSetupTime = 0
N7.C0.S05: txdqoffset delta = 0, dq invertpiclk = 3
N7: getComplexDqsSetupTime defaultOffset = 40
N7: getComplexDqsSetupTime = 40
N7.C0.S05: txdqsoffset delta = 40
N7: getComplexRcvEnSetupTime defaultOffset = 37
N7: getComplexRcvEnSetupTime = 37
N7.C0.S05: rcvenoffset delta = 37
N7.C0.S05: Final txdqoffset / txdqsoffset / rcvenoffset /  0 / 40 / 37
N7: getComplexDqSetupTime defaultOffset = 0
N7: getComplexDqSetupTime = 0
N7.C0.S06: txdqoffset delta = 0, dq invertpiclk = 0
N7: getComplexDqsSetupTime defaultOffset = 40
N7: getComplexDqsSetupTime = 40
N7.C0.S06: txdqsoffset delta = 40
N7: getComplexRcvEnSetupTime defaultOffset = 37
N7: getComplexRcvEnSetupTime = 37
N7.C0.S06: rcvenoffset delta = 37
N7.C0.S06: Final txdqoffset / txdqsoffset / rcvenoffset / 30 /  6 /  3
N7: getComplexDqSetupTime defaultOffset = 0
N7: getComplexDqSetupTime = 0
N7.C0.S07: txdqoffset delta = 0, dq invertpiclk = 0
N7: getComplexDqsSetupTime defaultOffset = 40
N7: getComplexDqsSetupTime = 40
N7.C0.S07: txdqsoffset delta = 40
N7: getComplexRcvEnSetupTime defaultOffset = 37
N7: getComplexRcvEnSetupTime = 37
N7.C0.S07: rcvenoffset delta = 37
N7.C0.S07: Final txdqoffset / txdqsoffset / rcvenoffset / 62 / 38 / 35
N7: getComplexDqSetupTime defaultOffset = 0
N7: getComplexDqSetupTime = 0
N7.C0.S08: txdqoffset delta = 0, dq invertpiclk = 3
N7: getComplexDqsSetupTime defaultOffset = 40
N7: getComplexDqsSetupTime = 40
N7.C0.S08: txdqsoffset delta = 40
N7: getComplexRcvEnSetupTime defaultOffset = 37
N7: getComplexRcvEnSetupTime = 37
N7.C0.S08: rcvenoffset delta = 37
N7.C0.S08: Final txdqoffset / txdqsoffset / rcvenoffset / 34 / 10 /  7

N7: vmse_modes =          1,  0
N7.C1: piDelay CMDn  CMDs  CTL  CKE  CLK   0  1  2  3  4  5  6  7  8  9 10 11 12 13 14 15 16 17
          0       0     0    1    1    0   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
          1       0     0    1    1    0   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
          2       0     0    1    1    0   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
          3       0     0    1    1    0   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
          4       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
          5       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
          6       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
          7       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
          8       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
          9       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         10       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         11       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         12       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         13       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         14       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         15       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         16       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         17       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         18       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         19       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         20       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         21       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         22       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         23       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         24       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         25       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         26       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         27       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         28       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         29       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         30       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         31       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         32       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         33       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         34       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         35       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         36       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         37       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         38       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         39       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         40       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         41       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         42       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         43       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         44       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         45       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         46       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         47       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         48       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         49       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         50       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         51       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         52       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         53       0     0    1    1    1   1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1 
         54       0     0    1    1    1   0  1  1  1  1  1  1  1  1  0  1  1  1  1  1  1  1  1 
         55       0     0    1    1    1   X  1  1  1  1  1  1  1  1  X  1  1  1  1  1  1  1  1 
         56       0     0    1    1    1   X  0  1  1  1  1  1  1  1  X  0  1  1  1  1  1  1  1 
         57       0     0    1    1    1   X  X  1  1  1  1  1  1  1  X  X  1  1  1  1  1  1  1 
         58       0     0    1    1    1   X  X  0  1  1  1  0  0  1  X  X  0  1  1  1  0  0  1 
         59       0     0    1    1    1   X  X  X  1  1  1  X  X  1  X  X  X  1  1  1  X  X  1 
         60       0     0    1    1    1   X  X  X  0  1  1  X  X  1  X  X  X  0  1  1  X  X  1 
         61       0     0    1    1    1   X  X  X  X  1  0  X  X  1  X  X  X  X  1  0  X  X  1 
         62       0     0    1    1    1   X  X  X  X  1  X  X  X  0  X  X  X  X  1  X  X  X  0 
         63       0     0    0    1    1   X  X  X  X  0  X  X  X  X  X  X  X  X  0  X  X  X  X 
N7.C1: setting ddrcrinvertpiclk
          0       0     0    X    1    1   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
          1       0     0    X    0    1   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
          2       0     0    X    X    1   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
          3       0     0    X    X    1   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
          4       0     0    X    X    1   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
          5       0     0    X    X    0   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
          6       0     0    X    X    X   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
          7       0     0    X    X    X   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
          8       0     0    X    X    X   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
          9       0     0    X    X    X   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
         10       0     0    X    X    X   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
         11       0     0    X    X    X   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
         12       0     0    X    X    X   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
         13       0     0    X    X    X   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
         14       0     0    X    X    X   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
         15       0     0    X    X    X   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
         16       0     0    X    X    X   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
         17       0     0    X    X    X   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
         18       0     0    X    X    X   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
         19       0     0    X    X    X   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
         20       0     0    X    X    X   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
         21       0     0    X    X    X   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
         22       0     0    X    X    X   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
         23       0     0    X    X    X   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
         24       0     0    X    X    X   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
         25       0     0    X    X    X   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
         26       0     0    X    X    X   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
         27       0     0    X    X    X   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
         28       0     0    X    X    X   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
         29       0     0    X    X    X   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
         30       0     0    X    X    X   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
         31       0     0    X    X    X   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
         32       0     0    X    X    X   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
         33       0     0    X    X    X   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
         34       0     0    X    X    X   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
         35       0     0    X    X    X   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
         36       0     0    X    X    X   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
         37       0     0    X    X    X   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
         38       0     0    X    X    X   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
         39       0     0    X    X    X   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
         40       0     0    X    X    X   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
         41       0     0    X    X    X   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
         42       0     0    X    X    X   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
         43       0     0    X    X    X   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
         44       0     0    X    X    X   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
         45       0     0    X    X    X   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
         46       0     0    X    X    X   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
         47       0     0    X    X    X   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
         48       0     0    X    X    X   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
         49       0     0    X    X    X   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
         50       0     0    X    X    X   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
         51       0     0    X    X    X   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
         52       0     0    X    X    X   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
         53       0     0    X    X    X   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
         54       0     0    X    X    X   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
         55       0     0    X    X    X   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
         56       0     0    X    X    X   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
         57       0     0    X    X    X   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
         58       0     0    X    X    X   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
         59       0     0    X    X    X   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
         60       0     0    X    X    X   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
         61       0     0    X    X    X   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
         62       0     0    X    X    X   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
         63       0     0    X    X    X   X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X 
N7.C1: CMD-N xovercal offset = 0
N7.C1: CMD-S xovercal offset = 0
N7.C1: CTL xovercal offset   = 63
N7.C1: CKE xovercal offset   = 1
N7.C1: CLK xovercal offset   = 5
N7.C1.S18: STROBE                     0   1   2   3   4   5   6   7   8   9  10  11  12  13  14  15  16  17
N7.C1.S18: Rec En xovercal offset =  54  56  58  60  63  61  58  58  62  54  56  58  60  63  61  58  58  62 
N7.C1.S18: Tx Dqs xovercal offset =  54  63  63  63  63  63  63  63  63  63  63  63  63  63  63  63  63  63 
N7.C1.S18: Tx Dq xovercal offset  =  54  56  58  60  63  61  58  58  62  54  56  58  60  63  61  58  58  62 
N7.C1:         CMDn  CMDs  CTL  CKE  CLK   0  1  2  3  4  5  6  7  8
N7.C1: offsets:  0     0    63N7: getComplexCkeSetupTime defaultOffset = 98
N7: getComplexCkeSetupTime = 98
    1    5
Ctl Offsets Delta / final ctl offset / final cke offset /  98  /   1  /  35
Cke invertpiclk / Ctl invertpiclk / 0x0  /  0x0
N7: getComplexClkSetupTime defaultOffset = 0
N7: getComplexClkSetupTime = 0
ClkSetupTime = 37
N7: getComplexDqSetupTime defaultOffset = 0
N7: getComplexDqSetupTime = 0
N7.C1.S00: txdqoffset delta = 0, dq invertpiclk = 0
N7: getComplexDqsSetupTime defaultOffset = 40
N7: getComplexDqsSetupTime = 40
N7.C1.S00: txdqsoffset delta = 40
N7: getComplexRcvEnSetupTime defaultOffset = 37
N7: getComplexRcvEnSetupTime = 37
N7.C1.S00: rcvenoffset delta = 37
N7.C1.S00: Final txdqoffset / txdqsoffset / rcvenoffset / 54 / 30 / 27
N7: getComplexDqSetupTime defaultOffset = 0
N7: getComplexDqSetupTime = 0
N7.C1.S01: txdqoffset delta = 0, dq invertpiclk = 0
N7: getComplexDqsSetupTime defaultOffset = 40
N7: getComplexDqsSetupTime = 40
N7.C1.S01: txdqsoffset delta = 40
N7: getComplexRcvEnSetupTime defaultOffset = 37
N7: getComplexRcvEnSetupTime = 37
N7.C1.S01: rcvenoffset delta = 37
N7.C1.S01: Final txdqoffset / txdqsoffset / rcvenoffset / 24 /  0 / 61
N7: getComplexDqSetupTime defaultOffset = 0
N7: getComplexDqSetupTime = 0
N7.C1.S02: txdqoffset delta = 0, dq invertpiclk = 0
N7: getComplexDqsSetupTime defaultOffset = 40
N7: getComplexDqsSetupTime = 40
N7.C1.S02: txdqsoffset delta = 40
N7: getComplexRcvEnSetupTime defaultOffset = 37
N7: getComplexRcvEnSetupTime = 37
N7.C1.S02: rcvenoffset delta = 37
N7.C1.S02: Final txdqoffset / txdqsoffset / rcvenoffset / 58 / 34 / 31
N7: getComplexDqSetupTime defaultOffset = 0
N7: getComplexDqSetupTime = 0
N7.C1.S03: txdqoffset delta = 0, dq invertpiclk = 0
N7: getComplexDqsSetupTime defaultOffset = 40
N7: getComplexDqsSetupTime = 40
N7.C1.S03: txdqsoffset delta = 40
N7: getComplexRcvEnSetupTime defaultOffset = 37
N7: getComplexRcvEnSetupTime = 37
N7.C1.S03: rcvenoffset delta = 37
N7.C1.S03: Final txdqoffset / txdqsoffset / rcvenoffset / 28 /  4 /  1
N7: getComplexDqSetupTime defaultOffset = 0
N7: getComplexDqSetupTime = 0
N7.C1.S04: txdqoffset delta = 0, dq invertpiclk = 0
N7: getComplexDqsSetupTime defaultOffset = 40
N7: getComplexDqsSetupTime = 40
N7.C1.S04: txdqsoffset delta = 40
N7: getComplexRcvEnSetupTime defaultOffset = 37
N7: getComplexRcvEnSetupTime = 37
N7.C1.S04: rcvenoffset delta = 37
N7.C1.S04: Final txdqoffset / txdqsoffset / rcvenoffset / 63 / 39 / 36
N7: getComplexDqSetupTime defaultOffset = 0
N7: getComplexDqSetupTime = 0
N7.C1.S05: txdqoffset delta = 0, dq invertpiclk = 0
N7: getComplexDqsSetupTime defaultOffset = 40
N7: getComplexDqsSetupTime = 40
N7.C1.S05: txdqsoffset delta = 40
N7: getComplexRcvEnSetupTime defaultOffset = 37
N7: getComplexRcvEnSetupTime = 37
N7.C1.S05: rcvenoffset delta = 37
N7.C1.S05: Final txdqoffset / txdqsoffset / rcvenoffset / 29 /  5 /  2
N7: getComplexDqSetupTime defaultOffset = 0
N7: getComplexDqSetupTime = 0
N7.C1.S06: txdqoffset delta = 0, dq invertpiclk = 0
N7: getComplexDqsSetupTime defaultOffset = 40
N7: getComplexDqsSetupTime = 40
N7.C1.S06: txdqsoffset delta = 40
N7: getComplexRcvEnSetupTime defaultOffset = 37
N7: getComplexRcvEnSetupTime = 37
N7.C1.S06: rcvenoffset delta = 37
N7.C1.S06: Final txdqoffset / txdqsoffset / rcvenoffset / 58 / 34 / 31
N7: getComplexDqSetupTime defaultOffset = 0
N7: getComplexDqSetupTime = 0
N7.C1.S07: txdqoffset delta = 0, dq invertpiclk = 0
N7: getComplexDqsSetupTime defaultOffset = 40
N7: getComplexDqsSetupTime = 40
N7.C1.S07: txdqsoffset delta = 40
N7: getComplexRcvEnSetupTime defaultOffset = 37
N7: getComplexRcvEnSetupTime = 37
N7.C1.S07: rcvenoffset delta = 37
N7.C1.S07: Final txdqoffset / txdqsoffset / rcvenoffset / 26 /  2 / 63
N7: getComplexDqSetupTime defaultOffset = 0
N7: getComplexDqSetupTime = 0
N7.C1.S08: txdqoffset delta = 0, dq invertpiclk = 0
N7: getComplexDqsSetupTime defaultOffset = 40
N7: getComplexDqsSetupTime = 40
N7.C1.S08: txdqsoffset delta = 40
N7: getComplexRcvEnSetupTime defaultOffset = 37
N7: getComplexRcvEnSetupTime = 37
N7.C1.S08: rcvenoffset delta = 37
N7.C1.S08: Final txdqoffset / txdqsoffset / rcvenoffset / 62 / 38 / 35

N1.C0:  2       41     41       39      30      38     14      14       31        8       0
N3.C0:  6       42     42       39      33      38     16      16       31        8       0
N5.C0: SELF CAL 
N7: SetupJckSmbCfg: JCK VLINFREQ set to: 0x820F1028
N5.C0: JckCompCodeCheck: Phase 1 - Comp Code Results
N7: SetupJckSmbCfg: PLL is locked.
N1.C0:  3       42     42       39      31      38     14      14       31        8       0
N3.C0:  7       42     42       39      33      38     16      16        8       31       0
N5.C0: Cycle ron_up ron_eq_up ron_dn ron_eq_dn odt scomp_up scom_dn tcomp_l2h tcomp_h2l   bad_training
N7.C0: SetupJckSmbCfg: dlyFrms = 15
N7.C0: cwleffective = 8
N1.C0:  4       41     41       39      29      38     14      14       31        8       0
N3.C0:  8       42     42       39      31      38     16      16       31        8       0
N7.C0: PreVMSE Training raw cleff = 9, raw cwleff = 7
N5.C0:  0       42     42       39      33      38     15      15        8       31       0
N7.C0: vmseratio = 0, revisionId = 5, vmse_mode = 1, QCRM_ENABLE = 0
N1.C0:  5       41     41       39      28      38     14      14       31        8       0
N3.C0:  9       42     42       39      33      38     16      16        8       31       0
N7: SetupJckSmbCfg: JCK wpsyncrcven = 5, wpsyncdata = 10
N3.C0: JckCompCodeCheck: Phase 2 - Check for bad ron_up vs average: num = 10, ron_up_avg = 39, ron_up_75avg = 29
N5.C0:  1       42     42       39      33      38     15      15        8       31       0
N1.C0:  6       41     41       39      30      38     14      14       31        8       0
N3.C0: Cycle ron_up ron_eq_up ron_dn ron_eq_dn odt scomp_up scom_dn tcomp_l2h tcomp_h2l   bad_training
N3.C0:  1       21     21       20      14      38     16      16        8       31       1
N3.C0: JckCompCodeCheck: Phase 3 - Comp Code Limits
N5.C0:  2       42     42       39      33      38     15      15        8       31       0
N1.C0:  7       41     41       39      28      38     14      14       31        8       0
N3.C0: ron_up_limitdn   ron_dn_limitup   ron_eq_dn_limtdn  odt_limitdn
N3.C0:     26                45                22             24
N3.C0: JckCompCodeCheck: Phase 3 - SUCCESS
N3.C0: VmseOverrideJckCompCodes
N5.C0:  3       42     42       39      33      38     15      15        8       31       0
N1.C0:  8       41     41       39      29      38     14      14        8       31       0
N5.C0:  4       42     42       39      33      38     15      15        8       31       0
N1.C0:  9       41     41       39      29      38     14      14        8       31       0
N1.C0: JckCompCodeCheck: Phase 2 - Check for bad ron_up vs average: num = 10, ron_up_avg = 41, ron_up_75avg = 30
N1.C0: Cycle ron_up ron_eq_up ron_dn ron_eq_dn odt scomp_up scom_dn tcomp_l2h tcomp_h2l   bad_training
N5.C0:  5       42     42       39      31      38     15      15        8       31       0
N1.C0: JckCompCodeCheck: Phase 3 - Comp Code Limits
N1.C0: ron_up_limitdn   ron_dn_limitup   ron_eq_dn_limtdn  odt_limitdn
N1.C0:     26                45                20             24
N1.C0: JckCompCodeCheck: Phase 3 - SUCCESS
N1.C0: VmseOverrideJckCompCodes
N5.C0:  6       42     42       39      33      38     15      15        8       31       0
N5.C0:  7       42     42       39      33      38     15      15        8       31       0
N5.C0:  8       42     42       39      33      38     15      15        8       31       0
N5.C0:  9       42     42       39      33      38     15      15        8       31       0
N5.C0: JckCompCodeCheck: Phase 2 - Check for bad ron_up vs average: num = 10, ron_up_avg = 42, ron_up_75avg = 31
N5.C0: Cycle ron_up ron_eq_up ron_dn ron_eq_dn odt scomp_up scom_dn tcomp_l2h tcomp_h2l   bad_training
N5.C0: JckCompCodeCheck: Phase 3 - Comp Code Limits
N5.C0: ron_up_limitdn   ron_dn_limitup   ron_eq_dn_limtdn  odt_limitdn
N5.C0:     26                46                21             24
N5.C0: JckCompCodeCheck: Phase 3 - SUCCESS
N5.C0: VmseOverrideJckCompCodes
N7.C0: SELF CAL 
N7.C0: JckCompCodeCheck: Phase 1 - Comp Code Results
N7.C0: Cycle ron_up ron_eq_up ron_dn ron_eq_dn odt scomp_up scom_dn tcomp_l2h tcomp_h2l   bad_training
N7.C0:  0       41     41       36      31      38     15      15        9       31       0
N7.C0:  1       41     41       36      31      38     16      16        7       31       0
N7.C0:  2       41     41       37      29      38     16      16        4       31       0
N7.C0:  3       41     41       37      29      38     15      15       10       31       0
N7.C0:  4       41     41       36      31      38     15      15        9       31       0
N7.C0:  5       41     41       36      31      38     16      16       10       31       0
N7.C0:  6       41     41       36      31      38     16      16        3       31       0
N7.C0:  7       41     41       36      31      38     16      16        4       31       0
N7.C0:  8       41     41       36      31      38     16      16       10       31       0
N3: SetupJckSmbCfg: JCK VLINFREQ set to: 0x820F1028
N3: SetupJckSmbCfg: PLL is locked.
N3.C2: SetupJckSmbCfg: dlyFrms = 15
N7.C0:  9       41     41       36      31      38     15      15       10       31       0
N3.C2: cwleffective = 8
N7.C0: JckCompCodeCheck: Phase 2 - Check for bad ron_up vs average: num = 10, ron_up_avg = 41, ron_up_75avg = 30
N3.C2: PreVMSE Training raw cleff = 9, raw cwleff = 7
N7.C0: Cycle ron_up ron_eq_up ron_dn ron_eq_dn odt scomp_up scom_dn tcomp_l2h tcomp_h2l   bad_training
N3.C2: vmseratio = 0, revisionId = 5, vmse_mode = 1, QCRM_ENABLE = 0
N7.C0: JckCompCodeCheck: Phase 3 - Comp Code Limits
N7.C0: ron_up_limitdn   ron_dn_limitup   ron_eq_dn_limtdn  odt_limitdn
N3: SetupJckSmbCfg: JCK wpsyncrcven = 5, wpsyncdata = 10
N7.C0:     25                44                20             24
Checkpoint Code: Socket 0, 0xB6, 0xA0, 0x0000
N7.C0: JckCompCodeCheck: Phase 3 - SUCCESS
N7.C0: VmseOverrideJckCompCodes
N1: SetupJckSmbCfg: JCK VLINFREQ set to: 0x820F1028
N1: SetupJckSmbCfg: PLL is locked.
N1.C2: SetupJckSmbCfg: dlyFrms = 15
N1.C2: cwleffective = 8
N1.C2: PreVMSE Training raw cleff = 9, raw cwleff = 7
N1.C2: vmseratio = 0, revisionId = 5, vmse_mode = 1, QCRM_ENABLE = 0
N1: SetupJckSmbCfg: JCK wpsyncrcven = 5, wpsyncdata = 10
N5: SetupJckSmbCfg: JCK VLINFREQ set to: 0x820F1028
N5: SetupJckSmbCfg: PLL is locked.
N5.C2: SetupJckSmbCfg: dlyFrms = 15
N5.C2: cwleffective = 8
N5.C2: PreVMSE Training raw cleff = 9, raw cwleff = 7
N5.C2: vmseratio = 0, revisionId = 5, vmse_mode = 1, QCRM_ENABLE = 0
N5: SetupJckSmbCfg: JCK wpsyncrcven = 5, wpsyncdata = 10
N3.C1: SELF CAL 
N3.C1: JckCompCodeCheck: Phase 1 - Comp Code Results
N3.C1: Cycle ron_up ron_eq_up ron_dn ron_eq_dn odt scomp_up scom_dn tcomp_l2h tcomp_h2l   bad_training
N3.C1:  0       42     42       39      32      38     15      15       12       31       0
N3.C1:  1       42     42       39      32      38     15      15       12       31       0
N1.C1: SELF CAL 
N1.C1: JckCompCodeCheck: Phase 1 - Comp Code Results
N1.C1: Cycle ron_up ron_eq_up ron_dn ron_eq_dn odt scomp_up scom_dn tcomp_l2h tcomp_h2l   bad_training
N3.C1:  2       42     42       39      33      39     16      16       11       31       0
N1.C1:  0       42     42       37      31      38     15      15       20       31       0
N3.C1:  3       42     42       39      33      38     16      16       12       31       0
N1.C1:  1       42     42       37      31      38     14      14       19       31       0
N3.C1:  4       42     42       39      33      38     15      15       14       31       0
N1.C1:  2       42     42       37      31      38     14      14       21       31       0
N3.C1:  5       42     42       39      33      38     16      16       12       31       0
N5.C1: SELF CAL 
N5.C1: JckCompCodeCheck: Phase 1 - Comp Code Results
N1.C1:  3       42     42       37      31      38     15      15       20       31       0
N3.C1:  6       42     42       39      33      38     16      16       12       31       0
N5.C1: Cycle ron_up ron_eq_up ron_dn ron_eq_dn odt scomp_up scom_dn tcomp_l2h tcomp_h2l   bad_training
N7: SetupJckSmbCfg: JCK VLINFREQ set to: 0x820F1028
N1.C1:  4       42     42       37      32      38     14      14       20       31       0
N7: SetupJckSmbCfg: PLL is locked.
N3.C1:  7       42     42       39      31      38     15      15       15       31       0
N5.C1:  0       41     41       38      30      38     15      15       31        8       0
N7.C2: SetupJckSmbCfg: dlyFrms = 15
N1.C1:  5       42     42       37      31      38     15      15       20       31       0
N7.C2: cwleffective = 8
N3.C1:  8       42     42       39      33      38     16      16       13       31       0
N7.C2: PreVMSE Training raw cleff = 9, raw cwleff = 7
N5.C1:  1       41     41       38      31      38     15      15       31        8       0
N7.C2: vmseratio = 0, revisionId = 5, vmse_mode = 1, QCRM_ENABLE = 0
N1.C1:  6       42     42       37      31      38     14      14       24       31       0
N3.C1:  9       42     42       39      32      38     15      15       12       31       0
N7: SetupJckSmbCfg: JCK wpsyncrcven = 5, wpsyncdata = 10
N3.C1: JckCompCodeCheck: Phase 2 - Check for bad ron_up vs average: num = 10, ron_up_avg = 42, ron_up_75avg = 31
N5.C1:  2       41     41       38      30      38     15      15       31        8       0
N1.C1:  7       42     42       37      31      38     14      14       22       31       0
N3.C1: Cycle ron_up ron_eq_up ron_dn ron_eq_dn odt scomp_up scom_dn tcomp_l2h tcomp_h2l   bad_training
N3.C1: JckCompCodeCheck: Phase 3 - Comp Code Limits
N3.C1: ron_up_limitdn   ron_dn_limitup   ron_eq_dn_limtdn  odt_limitdn
N5.C1:  3       41     41       38      30      38     15      15       31        8       0
N1.C1:  8       42     42       37      32      38     15      15       20       31       0
N3.C1:     26                46                21             24
N3.C1: JckCompCodeCheck: Phase 3 - SUCCESS
N3.C1: VmseOverrideJckCompCodes
N5.C1:  4       41     41       38      30      38     15      15       31        8       0
N1.C1:  9       42     42       37      31      38     14      14       21       31       0
N1.C1: JckCompCodeCheck: Phase 2 - Check for bad ron_up vs average: num = 10, ron_up_avg = 42, ron_up_75avg = 31
N1.C1: Cycle ron_up ron_eq_up ron_dn ron_eq_dn odt scomp_up scom_dn tcomp_l2h tcomp_h2l   bad_training
N5.C1:  5       41     41       38      30      38     15      15       31        8       0
N1.C1: JckCompCodeCheck: Phase 3 - Comp Code Limits
N1.C1: ron_up_limitdn   ron_dn_limitup   ron_eq_dn_limtdn  odt_limitdn
N1.C1:     26                45                21             24
N1.C1: JckCompCodeCheck: Phase 3 - SUCCESS
N1.C1: VmseOverrideJckCompCodes
N5.C1:  6       41     41       38      30      38     15      15       31        8       0
N5.C1:  7       41     41       38      30      38     15      15       31        8       0
N5.C1:  8       41     41       38      31      38     15      15       31        8       0
N5.C1:  9       41     41       37      31      38     15      15       31        8       0
N5.C1: JckCompCodeCheck: Phase 2 - Check for bad ron_up vs average: num = 10, ron_up_avg = 41, ron_up_75avg = 30
N5.C1: Cycle ron_up ron_eq_up ron_dn ron_eq_dn odt scomp_up scom_dn tcomp_l2h tcomp_h2l   bad_training
N5.C1: JckCompCodeCheck: Phase 3 - Comp Code Limits
N5.C1: ron_up_limitdn   ron_dn_limitup   ron_eq_dn_limtdn  odt_limitdn
N5.C1:     25                45                20             24
N5.C1: JckCompCodeCheck: Phase 3 - SUCCESS
N5.C1: VmseOverrideJckCompCodes
N7.C1: SELF CAL 
N7.C1: JckCompCodeCheck: Phase 1 - Comp Code Results
N7.C1: Cycle ron_up ron_eq_up ron_dn ron_eq_dn odt scomp_up scom_dn tcomp_l2h tcomp_h2l   bad_training
N7.C1:  0       42     42       39      31      39     16      16        8       31       0
N7.C1:  1       42     42       39      32      39     16      16        8       31       0
N7.C1:  2       20     20       19      14      39     16      16        8       31       0
N7.C1:  3       42     42       39      32      39     16      16        8       31       0
N7.C1:  4       42     42       39      32      39     16      16        8       31       0
N7.C1:  5       42     42       39      32      39     16      16        8       31       0
N7.C1:  6       42     42       39      32      39     16      16        8       31       0
N7.C1:  7       42     42       39      32      39     16      16        8       31       0
N3: Start VMSE training Sequence
N3: ddrCh0.enabled = 1
N3: ddrCh1.enabled = 1
N3: ddrCh2.enabled = 1
N3: ddrCh3.enabled = 1
N3: VMSE0.enabled = 1
N3: VMSE1.enabled = 1
N7.C1:  8       42     42       39      32      39     16      16        8       31       0
N3: CpgcVmseTraining for VMSE0
N3: Initialize VMSE Channels

START - VMSE Detect DC
N3: HsxVmseCompInit
N3.C0: Skip DC Detect check for CMD results
N7.C1:  9       42     42       39      31      39     16      16        8       31       0
N3.C0: Skip DC Detect check for CMD results
N7.C1: JckCompCodeCheck: Phase 2 - Check for bad ron_up vs average: num = 10, ron_up_avg = 39, ron_up_75avg = 29
Checkpoint Code: Socket 0, 0xB6, 0xA0, 0x0000
N3: HsxVmseCompInit
N7.C1: Cycle ron_up ron_eq_up ron_dn ron_eq_dn odt scomp_up scom_dn tcomp_l2h tcomp_h2l   bad_training
Checkpoint Code: Socket 0, 0xB6, 0x10, 0x0000
N3.C0: VmseDetectDC: SUCCESS
N7.C1:  2       20     20       19      14      39     16      16        8       31       1
N1: Start VMSE training Sequence
N3.C0: VmseDetectClock
N7.C1: JckCompCodeCheck: Phase 3 - Comp Code Limits
N1: ddrCh0.enabled = 1
N7.C1: ron_up_limitdn   ron_dn_limitup   ron_eq_dn_limtdn  odt_limitdn
N1: ddrCh1.enabled = 1
N7.C1:     26                46                21             24
N1: ddrCh2.enabled = 1
N7.C1: JckCompCodeCheck: Phase 3 - SUCCESS
N1: ddrCh3.enabled = 1
N7.C1: VmseOverrideJckCompCodes
N1: VMSE0.enabled = 1
N1: VMSE1.enabled = 1
N1: CpgcVmseTraining for VMSE0
Checkpoint Code: Socket 0, 0xB6, 0x11, 0x0000
N1: Initialize VMSE Channels

START - VMSE Detect DC
Checkpoint Code: Socket 0, 0xB6, 0x46, 0x0000
N1: HsxVmseCompInit
Checkpoint Code: Socket 0, 0xB6, 0x80, 0x0000
N1.C0: Skip DC Detect check for CMD results
N1.C0: Skip DC Detect check for CMD results
N1: HsxVmseCompInit
Checkpoint Code: Socket 0, 0xB6, 0x81, 0x0000
N1.C0: VmseDetectDC: SUCCESS
N1.C0: VmseDetectClock
N5: Start VMSE training Sequence
N5: ddrCh0.enabled = 1
N5: ddrCh1.enabled = 1
N5: ddrCh2.enabled = 1
N5: ddrCh3.enabled = 1
N5: VMSE0.enabled = 1
N3.C0: VmseDetectClock: SUCCESS
N5: VMSE1.enabled = 1

END - VMSE Detect DC                   Time         261 ms
N5: CpgcVmseTraining for VMSE0

START - MXB Clock Train
N5: Initialize VMSE Channels

START - VMSE Detect DC
N5: HsxVmseCompInit
N5.C0: Skip DC Detect check for CMD results
N5.C0: Skip DC Detect check for CMD results
N5: HsxVmseCompInit
N5.C0: VmseDetectDC: SUCCESS
N5.C0: VmseDetectClock
N3.C0: VmseRefVckResync: ddrFreq = 0x2, VMSE_MODE_2_1 = 1, VMSE_PREAMBLE_2UI = 0
N1.C0: VmseDetectClock: SUCCESS

END - VMSE Detect DC                   Time         226 ms

START - MXB Clock Train
Checkpoint Code: Socket 0, 0xB6, 0x48, 0x0000
N3.C0: VmseRefVckResync: VLINKFREQNXT set to: 0x20F940A
N3.C0: VmseTrainClockAlign: JCK clkadjcnt =0
Checkpoint Code: Socket 0, 0xB6, 0x6C, 0x0000

END - MXB Clock Train                  Time         156 ms

START - VMSE Train Command
N3.C0.B00: HsxCtlXoverInit: invertPiClk = 0x0, RankUsed = 0xFFF, Training = 0x38FFF0A
N3.C0.B01: HsxCtlXoverInit: invertPiClk = 0x0, RankUsed = 0xFFF, Training = 0x38FFF27
N1.C0: VmseAdjustVckVoc: retrain Clock DCC.
   dcc1_vck = 0x17, dcc2_vck = 0x3F, preampvoc = 0x9
N5.C0: VmseDetectClock: SUCCESS
Checkpoint Code: Socket 0, 0xB6, 0x6C, 0x0000

END - VMSE Detect DC                   Time         219 ms

START - MXB Clock Train
N3.C0: VmseTrainCmdFine: vmse link sts = 0x4947
N1.C0: VmseAdjustVckVoc: retrain Clock DCC.
   dcc1_vck = 0x13, dcc2_vck = 0x3F, preampvoc = 0xA
Checkpoint Code: Socket 0, 0xB6, 0x6C, 0x0000
N5.C0: VmseRefVckResync: ddrFreq = 0x2, VMSE_MODE_2_1 = 1, VMSE_PREAMBLE_2UI = 0
N1.C0: VmseRefVckResync: ddrFreq = 0x2, VMSE_MODE_2_1 = 1, VMSE_PREAMBLE_2UI = 0
N5.C0: VmseRefVckResync: VLINKFREQNXT set to: 0x20F940A
N1.C0: VmseRefVckResync: VLINKFREQNXT set to: 0x20F940A
N5.C0: VmseTrainClockAlign: JCK clkadjcnt =0

END - MXB Clock Train                  Time         161 ms

START - VMSE Train Command
N1.C0: VmseTrainClockAlign: JCK clkadjcnt =4

END - MXB Clock Train                  Time         315 ms
N5.C0.B00: HsxCtlXoverInit: invertPiClk = 0x0, RankUsed = 0xFFF, Training = 0x38FFF07

START - VMSE Train Command
N5.C0.B01: HsxCtlXoverInit: invertPiClk = 0x0, RankUsed = 0xFFF, Training = 0x38FFF26
Checkpoint Code: Socket 0, 0xB6, 0x4A, 0x0000
N1.C0.B00: HsxCtlXoverInit: invertPiClk = 0x0, RankUsed = 0xFFF, Training = 0x38FFF08
N1.C0.B01: HsxCtlXoverInit: invertPiClk = 0x0, RankUsed = 0xFFF, Training = 0x38FFF26
Checkpoint Code: Socket 0, 0xB6, 0x60, 0x0000
N5.C0: VmseTrainCmdFine: vmse link sts = 0x4947
Checkpoint Code: Socket 0, 0xB6, 0x5A, 0x0000
N7: Start VMSE training Sequence
N7: ddrCh0.enabled = 1
N7: ddrCh1.enabled = 1
N7: ddrCh2.enabled = 1
N7: ddrCh3.enabled = 1
N1.C0: VmseTrainCmdFine: vmse link sts = 0x4947
N7: VMSE0.enabled = 1
N7: VMSE1.enabled = 1
N7: CpgcVmseTraining for VMSE0
N7: Initialize VMSE Channels

START - VMSE Detect DC
N7: HsxVmseCompInit
N7.C0: Skip DC Detect check for CMD results
N7.C0: Skip DC Detect check for CMD results
N7: HsxVmseCompInit
N7.C0: VmseDetectDC: SUCCESS
N7.C0: VmseDetectClock
N7.C0: VmseDetectClock: SUCCESS

END - VMSE Detect DC                   Time         211 ms

START - MXB Clock Train
N7.C0: VmseRefVckResync: ddrFreq = 0x2, VMSE_MODE_2_1 = 1, VMSE_PREAMBLE_2UI = 0
N7.C0: VmseRefVckResync: VLINKFREQNXT set to: 0x20F940A
N7.C0: VmseTrainClockAlign: JCK clkadjcnt =7

END - MXB Clock Train                  Time         156 ms

START - VMSE Train Command
N7.C0.B00: HsxCtlXoverInit: invertPiClk = 0x0, RankUsed = 0xFFF, Training = 0x38FFF06
N7.C0.B01: HsxCtlXoverInit: invertPiClk = 0x0, RankUsed = 0xFFF, Training = 0x38FFF24
N7.C0: VmseTrainCmdFine: vmse link sts = 0x4947
Entry 0 - TrainDcc - DCCStart: 13, VocStart: 9, DCCFinal: 13, VocFinal: 9
Entry 1 - TrainDcc - DCCStart: 14, VocStart: 9, DCCFinal: 14, VocFinal: 9
Entry 0 - TrainDcc - DCCStart: 9, VocStart: 12, DCCFinal: 9, VocFinal: 12
Entry 0 - TrainDcc - DCCStart: 10, VocStart: 10, DCCFinal: 10, VocFinal: 10
Entry 1 - TrainDcc - DCCStart: 30, VocStart: 12, DCCFinal: 30, VocFinal: 12
Entry 1 - TrainDcc - DCCStart: 48, VocStart: 10, DCCFinal: 56, VocFinal: 10
Entry 0 - TrainDcc - DCCStart: 14, VocStart: 19, DCCFinal: 22, VocFinal: 19
Entry 1 - TrainDcc - DCCStart: 38, VocStart: 19, DCCFinal: 22, VocFinal: 19
N3.C0.S00: VmseCmdFineTraining Final: centerPi = 0x65, PiEw = 0x2E, centerVref = 0x3B, vrefHeight = 0x45
N3.C0.S01: VmseCmdFineTraining Final: centerPi = 0x5F, PiEw = 0x2E, centerVref = 0x3A, vrefHeight = 0x49
N3.C0.S02: VmseCmdFineTraining Final: centerPi = 0x5D, PiEw = 0x32, centerVref = 0x3C, vrefHeight = 0x45
N3.C0.S03: VmseCmdFineTraining Final: centerPi = 0x62, PiEw = 0x31, centerVref = 0x3B, vrefHeight = 0x47
N3.C0.S04: VmseCmdFineTraining Final: centerPi = 0x5B, PiEw = 0x2B, centerVref = 0x39, vrefHeight = 0x43
N3.C0.S05: VmseCmdFineTraining Final: centerPi = 0x5B, PiEw = 0x2F, centerVref = 0x3C, vrefHeight = 0x43
N3.C0.S06: VmseCmdFineTraining Final: centerPi = 0x5B, PiEw = 0x2E, centerVref = 0x3F, vrefHeight = 0x45
N3.C0.S07: VmseCmdFineTraining Final: centerPi = 0x5F, PiEw = 0x30, centerVref = 0x3D, vrefHeight = 0x47
N3.C0.S08: VmseCmdFineTraining Final: centerPi = 0x5B, PiEw = 0x32, centerVref = 0x40, vrefHeight = 0x45
N3.C0.S09: VmseCmdFineTraining Final: centerPi = 0x60, PiEw = 0x32, centerVref = 0x38, vrefHeight = 0x45
N3.C0.S10: VmseCmdFineTraining Final: centerPi = 0x5E, PiEw = 0x2E, centerVref = 0x3A, vrefHeight = 0x41
N3.C0.S11: VmseCmdFineTraining Final: centerPi = 0x5B, PiEw = 0x2B, centerVref = 0x37, vrefHeight = 0x47
N3.C0.S12: VmseCmdFineTraining Final: centerPi = 0x62, PiEw = 0x30, centerVref = 0x3A, vrefHeight = 0x47
N3.C0.S13: VmseCmdFineTraining Final: centerPi = 0x5B, PiEw = 0x32, centerVref = 0x36, vrefHeight = 0x43
N3.C0.S14: VmseCmdFineTraining Final: centerPi = 0x63, PiEw = 0x34, centerVref = 0x43, vrefHeight = 0x4B
N3.C0.S15: VmseCmdFineTraining Final: centerPi = 0x65, PiEw = 0x32, centerVref = 0x35, vrefHeight = 0x49
N3.C0.S16: VmseCmdFineTraining Final: centerPi = 0x5B, PiEw = 0x30, centerVref = 0x37, vrefHeight = 0x41

END - VMSE Train Command               Time         7233 ms

START - VMSE Train Read Leveling
N7.C0.S00: VmseCmdFineTraining Final: centerPi = 0x63, PiEw = 0x2E, centerVref = 0x3C, vrefHeight = 0x43
N3.C0: VmseReadLevelFineSetup: Initial RT = 101, Initial IO Latency = 0, Initial IO Comp = 15
N7.C0.S01: VmseCmdFineTraining Final: centerPi = 0x62, PiEw = 0x30, centerVref = 0x38, vrefHeight = 0x47
N5.C0.S00: VmseCmdFineTraining Final: centerPi = 0x5F, PiEw = 0x2E, centerVref = 0x3B, vrefHeight = 0x45
N7.C0.S02: VmseCmdFineTraining Final: centerPi = 0x5E, PiEw = 0x33, centerVref = 0x3B, vrefHeight = 0x45
N1.C0.S00: VmseCmdFineTraining Final: centerPi = 0x64, PiEw = 0x30, centerVref = 0x3E, vrefHeight = 0x43
N3.C0: VmseRLWLFineSearchAll: Entry
N5.C0.S01: VmseCmdFineTraining Final: centerPi = 0x5D, PiEw = 0x30, centerVref = 0x37, vrefHeight = 0x47
N7.C0.S03: VmseCmdFineTraining Final: centerPi = 0x61, PiEw = 0x30, centerVref = 0x3A, vrefHeight = 0x43
N1.C0.S01: VmseCmdFineTraining Final: centerPi = 0x62, PiEw = 0x31, centerVref = 0x3A, vrefHeight = 0x47
N3.C0: FINE READ LEVEL DELAY
N5.C0.S02: VmseCmdFineTraining Final: centerPi = 0x5B, PiEw = 0x32, centerVref = 0x39, vrefHeight = 0x47
N7.C0.S04: VmseCmdFineTraining Final: centerPi = 0x5B, PiEw = 0x30, centerVref = 0x34, vrefHeight = 0x47
N1.C0.S02: VmseCmdFineTraining Final: centerPi = 0x60, PiEw = 0x35, centerVref = 0x37, vrefHeight = 0x49
N3.C0.S00: RCVEN DELAY = 83
N5.C0.S03: VmseCmdFineTraining Final: centerPi = 0x5E, PiEw = 0x31, centerVref = 0x3A, vrefHeight = 0x45
N7.C0.S05: VmseCmdFineTraining Final: centerPi = 0x5B, PiEw = 0x2F, centerVref = 0x3F, vrefHeight = 0x41
N1.C0.S03: VmseCmdFineTraining Final: centerPi = 0x60, PiEw = 0x33, centerVref = 0x3B, vrefHeight = 0x45
N3.C0.S01: RCVEN DELAY = 47
N5.C0.S04: VmseCmdFineTraining Final: centerPi = 0x57, PiEw = 0x30, centerVref = 0x3D, vrefHeight = 0x41
N7.C0.S06: VmseCmdFineTraining Final: centerPi = 0x5C, PiEw = 0x30, centerVref = 0x3D, vrefHeight = 0x43
N1.C0.S04: VmseCmdFineTraining Final: centerPi = 0x57, PiEw = 0x2F, centerVref = 0x42, vrefHeight = 0x45
N3.C0.S02: RCVEN DELAY = 91
N5.C0.S05: VmseCmdFineTraining Final: centerPi = 0x57, PiEw = 0x30, centerVref = 0x3B, vrefHeight = 0x43
N7.C0.S07: VmseCmdFineTraining Final: centerPi = 0x60, PiEw = 0x32, centerVref = 0x3B, vrefHeight = 0x47
N1.C0.S05: VmseCmdFineTraining Final: centerPi = 0x5C, PiEw = 0x2F, centerVref = 0x39, vrefHeight = 0x45
N3.C0.S03: RCVEN DELAY = 69
N5.C0.S06: VmseCmdFineTraining Final: centerPi = 0x59, PiEw = 0x2F, centerVref = 0x3A, vrefHeight = 0x45
N7.C0.S08: VmseCmdFineTraining Final: centerPi = 0x58, PiEw = 0x31, centerVref = 0x3A, vrefHeight = 0x3F
N1.C0.S06: VmseCmdFineTraining Final: centerPi = 0x5D, PiEw = 0x31, centerVref = 0x39, vrefHeight = 0x47
N3.C0.S04: RCVEN DELAY = 157
N5.C0.S07: VmseCmdFineTraining Final: centerPi = 0x5C, PiEw = 0x31, centerVref = 0x3D, vrefHeight = 0x47
N7.C0.S09: VmseCmdFineTraining Final: centerPi = 0x5F, PiEw = 0x31, centerVref = 0x3B, vrefHeight = 0x45
N1.C0.S07: VmseCmdFineTraining Final: centerPi = 0x65, PiEw = 0x35, centerVref = 0x35, vrefHeight = 0x49
N3.C0.S05: RCVEN DELAY = 42
N5.C0.S08: VmseCmdFineTraining Final: centerPi = 0x58, PiEw = 0x31, centerVref = 0x40, vrefHeight = 0x45
N7.C0.S10: VmseCmdFineTraining Final: centerPi = 0x5E, PiEw = 0x2F, centerVref = 0x3E, vrefHeight = 0x43
N1.C0.S08: VmseCmdFineTraining Final: centerPi = 0x56, PiEw = 0x32, centerVref = 0x3C, vrefHeight = 0x41
N3.C0.S06: RCVEN DELAY = 39
N5.C0.S09: VmseCmdFineTraining Final: centerPi = 0x5D, PiEw = 0x30, centerVref = 0x39, vrefHeight = 0x43
N7.C0.S11: VmseCmdFineTraining Final: centerPi = 0x59, PiEw = 0x31, centerVref = 0x3A, vrefHeight = 0x47
N1.C0.S09: VmseCmdFineTraining Final: centerPi = 0x5E, PiEw = 0x31, centerVref = 0x36, vrefHeight = 0x45
N3.C0.S07: RCVEN DELAY = 157
N5.C0.S10: VmseCmdFineTraining Final: centerPi = 0x5C, PiEw = 0x2E, centerVref = 0x3C, vrefHeight = 0x41
N7.C0.S12: VmseCmdFineTraining Final: centerPi = 0x5F, PiEw = 0x31, centerVref = 0x38, vrefHeight = 0x47
N1.C0.S10: VmseCmdFineTraining Final: centerPi = 0x5B, PiEw = 0x2E, centerVref = 0x32, vrefHeight = 0x3F
N3.C0.S08: RCVEN DELAY = 102
N5.C0.S11: VmseCmdFineTraining Final: centerPi = 0x57, PiEw = 0x2F, centerVref = 0x38, vrefHeight = 0x47
N7.C0.S13: VmseCmdFineTraining Final: centerPi = 0x58, PiEw = 0x30, centerVref = 0x40, vrefHeight = 0x41
N1.C0.S11: VmseCmdFineTraining Final: centerPi = 0x56, PiEw = 0x2C, centerVref = 0x39, vrefHeight = 0x43
N3.C0.S00: READ LEVEL: FINAL RCVEN DELAY (both nibbles) = 181
N5.C0.S12: VmseCmdFineTraining Final: centerPi = 0x5E, PiEw = 0x30, centerVref = 0x3C, vrefHeight = 0x47
N7.C0.S14: VmseCmdFineTraining Final: centerPi = 0x5E, PiEw = 0x33, centerVref = 0x3D, vrefHeight = 0x47
N1.C0.S12: VmseCmdFineTraining Final: centerPi = 0x5E, PiEw = 0x30, centerVref = 0x3A, vrefHeight = 0x47
N3.C0.S01: READ LEVEL: FINAL RCVEN DELAY (both nibbles) = 146
N5.C0.S13: VmseCmdFineTraining Final: centerPi = 0x59, PiEw = 0x2F, centerVref = 0x39, vrefHeight = 0x43
N7.C0.S15: VmseCmdFineTraining Final: centerPi = 0x61, PiEw = 0x2F, centerVref = 0x3C, vrefHeight = 0x47
N1.C0.S13: VmseCmdFineTraining Final: centerPi = 0x57, PiEw = 0x2F, centerVref = 0x3A, vrefHeight = 0x41
N3.C0.S02: READ LEVEL: FINAL RCVEN DELAY (both nibbles) = 189
N5.C0.S14: VmseCmdFineTraining Final: centerPi = 0x5E, PiEw = 0x32, centerVref = 0x37, vrefHeight = 0x47
N7.C0.S16: VmseCmdFineTraining Final: centerPi = 0x5C, PiEw = 0x2C, centerVref = 0x35, vrefHeight = 0x47
N1.C0.S14: VmseCmdFineTraining Final: centerPi = 0x5F, PiEw = 0x33, centerVref = 0x37, vrefHeight = 0x49
N3.C0.S03: READ LEVEL: FINAL RCVEN DELAY (both nibbles) = 164
N5.C0.S15: VmseCmdFineTraining Final: centerPi = 0x5F, PiEw = 0x2E, centerVref = 0x3B, vrefHeight = 0x45
N1.C0.S15: VmseCmdFineTraining Final: centerPi = 0x5D, PiEw = 0x30, centerVref = 0x3B, vrefHeight = 0x45
N3.C0.S04: READ LEVEL: FINAL RCVEN DELAY (both nibbles) = 126
N5.C0.S16: VmseCmdFineTraining Final: centerPi = 0x5B, PiEw = 0x2F, centerVref = 0x40, vrefHeight = 0x43
N1.C0.S16: VmseCmdFineTraining Final: centerPi = 0x5B, PiEw = 0x2E, centerVref = 0x37, vrefHeight = 0x47
N3.C0.S05: READ LEVEL: FINAL RCVEN DELAY (both nibbles) = 141
N3.C0.S06: READ LEVEL: FINAL RCVEN DELAY (both nibbles) = 136
N3.C0.S07: READ LEVEL: FINAL RCVEN DELAY (both nibbles) = 126
N3.C0.S08: READ LEVEL: FINAL RCVEN DELAY (both nibbles) = 199
N3.C0.D0.S09: READ LEVEL: FINAL RT (all ranks) = 83, FINAL IO LATENCY (all ranks) = 2
N3.C0.D1.S09: READ LEVEL: FINAL RT (all ranks) = 83, FINAL IO LATENCY (all ranks) = 2

END - VMSE Train Read Leveling         Time         782 ms

START - VMSE Train Read

END - VMSE Train Command               Time         7229 ms

START - VMSE Train Read Leveling

END - VMSE Train Command               Time         7879 ms

START - VMSE Train Read Leveling

END - VMSE Train Command               Time         7858 ms

START - VMSE Train Read Leveling
Checkpoint Code: Socket 0, 0xB6, 0x4E, 0x0000
N7.C0: VmseReadLevelFineSetup: Initial RT = 101, Initial IO Latency = 0, Initial IO Comp = 15
N7.C0: VmseRLWLFineSearchAll: Entry
N7.C0: FINE READ LEVEL DELAY
N5.C0: VmseReadLevelFineSetup: Initial RT = 101, Initial IO Latency = 0, Initial IO Comp = 15
N7.C0.S00: RCVEN DELAY = 128
N7.C0.S01: RCVEN DELAY = 92
N1.C0: VmseReadLevelFineSetup: Initial RT = 101, Initial IO Latency = 0, Initial IO Comp = 15
N7.C0.S02: RCVEN DELAY = 137
N7.C0.S03: RCVEN DELAY = 112
N7.C0.S04: RCVEN DELAY = 76
N7.C0.S05: RCVEN DELAY = 87
N7.C0.S06: RCVEN DELAY = 86
N7.C0.S07: RCVEN DELAY = 71
N7.C0.S08: RCVEN DELAY = 81
N5.C0: VmseRLWLFineSearchAll: Entry
N7.C0.S00: READ LEVEL: FINAL RCVEN DELAY (both nibbles) = 97
N5.C0: FINE READ LEVEL DELAY
N7.C0.S01: READ LEVEL: FINAL RCVEN DELAY (both nibbles) = 60
N1.C0: VmseRLWLFineSearchAll: Entry
N5.C0.S00: RCVEN DELAY = 57
N7.C0.S02: READ LEVEL: FINAL RCVEN DELAY (both nibbles) = 104
N1.C0: FINE READ LEVEL DELAY
N5.C0.S01: RCVEN DELAY = 148
N7.C0.S03: READ LEVEL: FINAL RCVEN DELAY (both nibbles) = 82
N1.C0.S00: RCVEN DELAY = 131
N5.C0.S02: RCVEN DELAY = 54
N7.C0.S04: READ LEVEL: FINAL RCVEN DELAY (both nibbles) = 44
N1.C0.S01: RCVEN DELAY = 98
N5.C0.S03: RCVEN DELAY = 38
N7.C0.S05: READ LEVEL: FINAL RCVEN DELAY (both nibbles) = 57
N1.C0.S02: RCVEN DELAY = 140
N5.C0.S04: RCVEN DELAY = 134
N7.C0.S06: READ LEVEL: FINAL RCVEN DELAY (both nibbles) = 54
N1.C0.S03: RCVEN DELAY = 120
N5.C0.S05: RCVEN DELAY = 143
N7.C0.S07: READ LEVEL: FINAL RCVEN DELAY (both nibbles) = 40
N1.C0.S04: RCVEN DELAY = 79
N5.C0.S06: RCVEN DELAY = 142
N7.C0.S08: READ LEVEL: FINAL RCVEN DELAY (both nibbles) = 51
N1.C0.S05: RCVEN DELAY = 92
N5.C0.S07: RCVEN DELAY = 129
N7.C0.D0.S09: READ LEVEL: FINAL RT (all ranks) = 83, FINAL IO LATENCY (all ranks) = 2
N1.C0.S06: RCVEN DELAY = 88
N5.C0.S08: RCVEN DELAY = 139
N7.C0.D1.S09: READ LEVEL: FINAL RT (all ranks) = 83, FINAL IO LATENCY (all ranks) = 2
N1.C0.S07: RCVEN DELAY = 76
N5.C0.S00: READ LEVEL: FINAL RCVEN DELAY (both nibbles) = 156

END - VMSE Train Read Leveling         Time         347 ms
N1.C0.S08: RCVEN DELAY = 86
N5.C0.S01: READ LEVEL: FINAL RCVEN DELAY (both nibbles) = 116

START - VMSE Train Read
N1.C0.S00: READ LEVEL: FINAL RCVEN DELAY (both nibbles) = 229
N5.C0.S02: READ LEVEL: FINAL RCVEN DELAY (both nibbles) = 153
N1.C0.S01: READ LEVEL: FINAL RCVEN DELAY (both nibbles) = 198
N5.C0.S03: READ LEVEL: FINAL RCVEN DELAY (both nibbles) = 136
N1.C0.S02: READ LEVEL: FINAL RCVEN DELAY (both nibbles) = 237
N5.C0.S04: READ LEVEL: FINAL RCVEN DELAY (both nibbles) = 103
N1.C0.S03: READ LEVEL: FINAL RCVEN DELAY (both nibbles) = 218
N5.C0.S05: READ LEVEL: FINAL RCVEN DELAY (both nibbles) = 111
N1.C0.S04: READ LEVEL: FINAL RCVEN DELAY (both nibbles) = 178
N5.C0.S06: READ LEVEL: FINAL RCVEN DELAY (both nibbles) = 110
N1.C0.S05: READ LEVEL: FINAL RCVEN DELAY (both nibbles) = 187
N5.C0.S07: READ LEVEL: FINAL RCVEN DELAY (both nibbles) = 98
N1.C0.S06: READ LEVEL: FINAL RCVEN DELAY (both nibbles) = 186
N5.C0.S08: READ LEVEL: FINAL RCVEN DELAY (both nibbles) = 107
N1.C0.S07: READ LEVEL: FINAL RCVEN DELAY (both nibbles) = 172
N5.C0.D0.S09: READ LEVEL: FINAL RT (all ranks) = 83, FINAL IO LATENCY (all ranks) = 2
N1.C0.S08: READ LEVEL: FINAL RCVEN DELAY (both nibbles) = 182
N5.C0.D1.S09: READ LEVEL: FINAL RT (all ranks) = 83, FINAL IO LATENCY (all ranks) = 2
N1.C0.D0.S09: READ LEVEL: FINAL RT (all ranks) = 83, FINAL IO LATENCY (all ranks) = 2

END - VMSE Train Read Leveling         Time         442 ms
N1.C0.D1.S09: READ LEVEL: FINAL RT (all ranks) = 83, FINAL IO LATENCY (all ranks) = 2

START - VMSE Train Read

END - VMSE Train Read Leveling         Time         456 ms

START - VMSE Train Read
Checkpoint Code: Socket 0, 0xB6, 0x50, 0x0000

END - VMSE Train Read                  Time         4001 ms

START - VMSE Train Level Tx DQS DCC
N3.C0: VmseLevelTxDqsDccExecute: MXB DQS DCC Finished Successfully

END - VMSE Train Level Tx DQS DCC      Time         12 ms

START - VMSE Train Write Leveling
N3.C0: VmseWriteLevelFineSetup: Set push to data delay = 6, Global TX DQS delay = 0
N3.C0: VmseRLWLFineSearchAll: Entry
N3.C0: FINE WRITE LEVEL DELAY
N3.C0.S00: TX DQS DELAY = 116
N3.C0.S01: TX DQS DELAY = 155
N3.C0.S02: TX DQS DELAY = 111
N3.C0.S03: TX DQS DELAY = 133
N3.C0.S04: TX DQS DELAY = 40
N3.C0.S05: TX DQS DELAY = 159
N3.C0.S06: TX DQS DELAY = 159
N3.C0.S07: TX DQS DELAY = 47
N3.C0.S08: TX DQS DELAY = 93
N3.C0: VmseWriteLevelCoarseSetup: Set push to data delay = 6, Global TX DQS delay = 0
N3.C0: VmseWriteLevelCoarseExecute
N3.C0: VmseWLCoarseUpdatePD: New push to data delay = 6, New global TxDQS delay = 1
N3.C0: VmseWLCoarseUpdatePD: New push to data delay = 7, New global TxDQS delay = 0
N3.C0: VmseWLCoarseUpdatePD: New push to data delay = 7, New global TxDQS delay = 1
N3.C0: VmseWLCoarseUpdatePD: New push to data delay = 8, New global TxDQS delay = 0
N3.C0.S00: FINAL TX DQS BEFORE TxFIFO CHECK = 85
N3.C0.S01: FINAL TX DQS BEFORE TxFIFO CHECK = 124
N3.C0.S02: FINAL TX DQS BEFORE TxFIFO CHECK = 81
N3.C0.S03: FINAL TX DQS BEFORE TxFIFO CHECK = 100
N3.C0.S04: FINAL TX DQS BEFORE TxFIFO CHECK = 138
N3.C0.S05: FINAL TX DQS BEFORE TxFIFO CHECK = 129
N3.C0.S06: FINAL TX DQS BEFORE TxFIFO CHECK = 129
N3.C0.S07: FINAL TX DQS BEFORE TxFIFO CHECK = 144
N3.C0.S08: FINAL TX DQS BEFORE TxFIFO CHECK = 189
N3.C0: ResolveTxFIFOPtrSeparation: Smallest PI (81) < MIN ALLOWED DELAY (176) 
N3.C0: VmseIncTxFifoPtrSeparation: New push to data delay = 7
N3.C0.S00: VmseIncTxFifoPtrSeparation: pi adjustment = 128, FINAL TX DQS DELAY = 341
N3.C0.S01: VmseIncTxFifoPtrSeparation: pi adjustment = 128, FINAL TX DQS DELAY = 380
N3.C0.S02: VmseIncTxFifoPtrSeparation: pi adjustment = 128, FINAL TX DQS DELAY = 337
N3.C0.S03: VmseIncTxFifoPtrSeparation: pi adjustment = 128, FINAL TX DQS DELAY = 356
N3.C0.S04: VmseIncTxFifoPtrSeparation: pi adjustment = 128, FINAL TX DQS DELAY = 394
N3.C0.S05: VmseIncTxFifoPtrSeparation: pi adjustment = 128, FINAL TX DQS DELAY = 385
N3.C0.S06: VmseIncTxFifoPtrSeparation: pi adjustment = 128, FINAL TX DQS DELAY = 385
N3.C0.S07: VmseIncTxFifoPtrSeparation: pi adjustment = 128, FINAL TX DQS DELAY = 400
N3.C0.S08: VmseIncTxFifoPtrSeparation: pi adjustment = 128, FINAL TX DQS DELAY = 445

END - VMSE Train Write Leveling        Time         243 ms

START - VMSE Train Write

END - VMSE Train Read                  Time         4043 ms

START - VMSE Train Level Tx DQS DCC
N7.C0: VmseLevelTxDqsDccExecute: MXB DQS DCC Finished Successfully

END - VMSE Train Level Tx DQS DCC      Time         12 ms

START - VMSE Train Write Leveling
N7.C0: VmseWriteLevelFineSetup: Set push to data delay = 6, Global TX DQS delay = 0
N7.C0: VmseRLWLFineSearchAll: Entry

END - VMSE Train Read                  Time         3940 ms
N7.C0: FINE WRITE LEVEL DELAY

START - VMSE Train Level Tx DQS DCC
N7.C0.S00: TX DQS DELAY = 47
N7.C0.S01: TX DQS DELAY = 82
N5.C0: VmseLevelTxDqsDccExecute: MXB DQS DCC Finished Successfully
N7.C0.S02: TX DQS DELAY = 42

END - VMSE Train Level Tx DQS DCC      Time         13 ms
N7.C0.S03: TX DQS DELAY = 66

START - VMSE Train Write Leveling
N7.C0.S04: TX DQS DELAY = 101
N5.C0: VmseWriteLevelFineSetup: Set push to data delay = 6, Global TX DQS delay = 0
N7.C0.S05: TX DQS DELAY = 90

END - VMSE Train Read                  Time         3984 ms
N5.C0: VmseRLWLFineSearchAll: Entry
N7.C0.S06: TX DQS DELAY = 90

START - VMSE Train Level Tx DQS DCC
N5.C0: FINE WRITE LEVEL DELAY
N7.C0.S07: TX DQS DELAY = 105
Checkpoint Code: Socket 0, 0xB6, 0x52, 0x0000
N5.C0.S00: TX DQS DELAY = 106
N7.C0.S08: TX DQS DELAY = 83
N1.C0: VmseLevelTxDqsDccExecute: MXB DQS DCC Finished Successfully
N5.C0.S01: TX DQS DELAY = 140
N7.C0: VmseWriteLevelCoarseSetup: Set push to data delay = 6, Global TX DQS delay = 0

END - VMSE Train Level Tx DQS DCC      Time         25 ms
N5.C0.S02: TX DQS DELAY = 109
N7.C0: VmseWriteLevelCoarseExecute

START - VMSE Train Write Leveling
N5.C0.S03: TX DQS DELAY = 123
N7.C0: VmseWLCoarseUpdatePD: New push to data delay = 6, New global TxDQS delay = 1
Checkpoint Code: Socket 0, 0xB6, 0x54, 0x0000
N5.C0.S04: TX DQS DELAY = 158
N7.C0: VmseWLCoarseUpdatePD: New push to data delay = 7, New global TxDQS delay = 0
N1.C0: VmseWriteLevelFineSetup: Set push to data delay = 6, Global TX DQS delay = 0
N5.C0.S05: TX DQS DELAY = 152
N7.C0: VmseWLCoarseUpdatePD: New push to data delay = 7, New global TxDQS delay = 1
N1.C0: VmseRLWLFineSearchAll: Entry
N5.C0.S06: TX DQS DELAY = 151
N7.C0: VmseWLCoarseUpdatePD: New push to data delay = 8, New global TxDQS delay = 0
N1.C0: FINE WRITE LEVEL DELAY
N5.C0.S07: TX DQS DELAY = 38
N7.C0.S00: FINAL TX DQS BEFORE TxFIFO CHECK = 16
N1.C0.S00: TX DQS DELAY = 45
N5.C0.S08: TX DQS DELAY = 144
N7.C0.S01: FINAL TX DQS BEFORE TxFIFO CHECK = 47
N1.C0.S01: TX DQS DELAY = 79
N5.C0: VmseWriteLevelCoarseSetup: Set push to data delay = 6, Global TX DQS delay = 0
N7.C0.S02: FINAL TX DQS BEFORE TxFIFO CHECK = 12
N1.C0.S02: TX DQS DELAY = 41
N5.C0: VmseWriteLevelCoarseExecute
N7.C0.S03: FINAL TX DQS BEFORE TxFIFO CHECK = 35
N1.C0.S03: TX DQS DELAY = 62
N5.C0: VmseWLCoarseUpdatePD: New push to data delay = 6, New global TxDQS delay = 1
N7.C0.S04: FINAL TX DQS BEFORE TxFIFO CHECK = 71
N1.C0.S04: TX DQS DELAY = 98
N5.C0: VmseWLCoarseUpdatePD: New push to data delay = 7, New global TxDQS delay = 0
N7.C0.S05: FINAL TX DQS BEFORE TxFIFO CHECK = 58
N1.C0.S05: TX DQS DELAY = 83
N5.C0: VmseWLCoarseUpdatePD: New push to data delay = 7, New global TxDQS delay = 1
N7.C0.S06: FINAL TX DQS BEFORE TxFIFO CHECK = 61
N1.C0.S06: TX DQS DELAY = 87
N5.C0: VmseWLCoarseUpdatePD: New push to data delay = 8, New global TxDQS delay = 0
N7.C0.S07: FINAL TX DQS BEFORE TxFIFO CHECK = 74
N1.C0.S07: TX DQS DELAY = 98
N5.C0.S00: FINAL TX DQS BEFORE TxFIFO CHECK = 77
N7.C0.S08: FINAL TX DQS BEFORE TxFIFO CHECK = 52
N1.C0.S08: TX DQS DELAY = 85
N5.C0.S01: FINAL TX DQS BEFORE TxFIFO CHECK = 111
N7.C0: ResolveTxFIFOPtrSeparation: Smallest PI (12) < MIN ALLOWED DELAY (176) 
N1.C0: VmseWriteLevelCoarseSetup: Set push to data delay = 6, Global TX DQS delay = 0
N5.C0.S02: FINAL TX DQS BEFORE TxFIFO CHECK = 80
N7.C0: VmseIncTxFifoPtrSeparation: New push to data delay = 7
N1.C0: VmseWriteLevelCoarseExecute
N5.C0.S03: FINAL TX DQS BEFORE TxFIFO CHECK = 94
N7.C0.S00: VmseIncTxFifoPtrSeparation: pi adjustment = 128, FINAL TX DQS DELAY = 272
Checkpoint Code: Socket 0, 0xB6, 0xAC, 0x0000
N5.C0.S04: FINAL TX DQS BEFORE TxFIFO CHECK = 128
N7.C0.S01: VmseIncTxFifoPtrSeparation: pi adjustment = 128, FINAL TX DQS DELAY = 303
N1.C0: VmseWLCoarseUpdatePD: New push to data delay = 6, New global TxDQS delay = 1
N5.C0.S05: FINAL TX DQS BEFORE TxFIFO CHECK = 122
N7.C0.S02: VmseIncTxFifoPtrSeparation: pi adjustment = 128, FINAL TX DQS DELAY = 268
N1.C0: VmseWLCoarseUpdatePD: New push to data delay = 7, New global TxDQS delay = 0
N5.C0.S06: FINAL TX DQS BEFORE TxFIFO CHECK = 120
N7.C0.S03: VmseIncTxFifoPtrSeparation: pi adjustment = 128, FINAL TX DQS DELAY = 291
N1.C0: VmseWLCoarseUpdatePD: New push to data delay = 7, New global TxDQS delay = 1
N5.C0.S07: FINAL TX DQS BEFORE TxFIFO CHECK = 135
N7.C0.S04: VmseIncTxFifoPtrSeparation: pi adjustment = 128, FINAL TX DQS DELAY = 327
N1.C0: VmseWLCoarseUpdatePD: New push to data delay = 8, New global TxDQS delay = 0
N5.C0.S08: FINAL TX DQS BEFORE TxFIFO CHECK = 115
N7.C0.S05: VmseIncTxFifoPtrSeparation: pi adjustment = 128, FINAL TX DQS DELAY = 314
N1.C0: VmseWLCoarseUpdatePD: New push to data delay = 8, New global TxDQS delay = 1
N5.C0: ResolveTxFIFOPtrSeparation: Smallest PI (77) < MIN ALLOWED DELAY (176) 
N7.C0.S06: VmseIncTxFifoPtrSeparation: pi adjustment = 128, FINAL TX DQS DELAY = 317
N1.C0.S00: FINAL TX DQS BEFORE TxFIFO CHECK = 142
N5.C0: VmseIncTxFifoPtrSeparation: New push to data delay = 7
N7.C0.S07: VmseIncTxFifoPtrSeparation: pi adjustment = 128, FINAL TX DQS DELAY = 330
N1.C0.S01: FINAL TX DQS BEFORE TxFIFO CHECK = 176
N5.C0.S00: VmseIncTxFifoPtrSeparation: pi adjustment = 128, FINAL TX DQS DELAY = 333
N7.C0.S08: VmseIncTxFifoPtrSeparation: pi adjustment = 128, FINAL TX DQS DELAY = 308
N1.C0.S02: FINAL TX DQS BEFORE TxFIFO CHECK = 140
N5.C0.S01: VmseIncTxFifoPtrSeparation: pi adjustment = 128, FINAL TX DQS DELAY = 367

END - VMSE Train Write Leveling        Time         593 ms
N1.C0.S03: FINAL TX DQS BEFORE TxFIFO CHECK = 160
N5.C0.S02: VmseIncTxFifoPtrSeparation: pi adjustment = 128, FINAL TX DQS DELAY = 336

START - VMSE Train Write
N1.C0.S04: FINAL TX DQS BEFORE TxFIFO CHECK = 198
N5.C0.S03: VmseIncTxFifoPtrSeparation: pi adjustment = 128, FINAL TX DQS DELAY = 350
N1.C0.S05: FINAL TX DQS BEFORE TxFIFO CHECK = 183
N5.C0.S04: VmseIncTxFifoPtrSeparation: pi adjustment = 128, FINAL TX DQS DELAY = 384
N1.C0.S06: FINAL TX DQS BEFORE TxFIFO CHECK = 186
N5.C0.S05: VmseIncTxFifoPtrSeparation: pi adjustment = 128, FINAL TX DQS DELAY = 378
N1.C0.S07: FINAL TX DQS BEFORE TxFIFO CHECK = 198
N5.C0.S06: VmseIncTxFifoPtrSeparation: pi adjustment = 128, FINAL TX DQS DELAY = 376
N1.C0.S08: FINAL TX DQS BEFORE TxFIFO CHECK = 184
N5.C0.S07: VmseIncTxFifoPtrSeparation: pi adjustment = 128, FINAL TX DQS DELAY = 391
N1.C0: ResolveTxFIFOPtrSeparation: Smallest PI (140) < MIN ALLOWED DELAY (176) 
N5.C0.S08: VmseIncTxFifoPtrSeparation: pi adjustment = 128, FINAL TX DQS DELAY = 371
N1.C0: VmseIncTxFifoPtrSeparation: New push to data delay = 7

END - VMSE Train Write Leveling        Time         659 ms
N1.C0.S00: VmseIncTxFifoPtrSeparation: pi adjustment = 256, FINAL TX DQS DELAY = 398

START - VMSE Train Write
N1.C0.S01: VmseIncTxFifoPtrSeparation: pi adjustment = 256, FINAL TX DQS DELAY = 432
N1.C0.S02: VmseIncTxFifoPtrSeparation: pi adjustment = 256, FINAL TX DQS DELAY = 396
N1.C0.S03: VmseIncTxFifoPtrSeparation: pi adjustment = 256, FINAL TX DQS DELAY = 416
N1.C0.S04: VmseIncTxFifoPtrSeparation: pi adjustment = 256, FINAL TX DQS DELAY = 454
N1.C0.S05: VmseIncTxFifoPtrSeparation: pi adjustment = 256, FINAL TX DQS DELAY = 439
N1.C0.S06: VmseIncTxFifoPtrSeparation: pi adjustment = 256, FINAL TX DQS DELAY = 442
N1.C0.S07: VmseIncTxFifoPtrSeparation: pi adjustment = 256, FINAL TX DQS DELAY = 454
N1.C0.S08: VmseIncTxFifoPtrSeparation: pi adjustment = 256, FINAL TX DQS DELAY = 440

END - VMSE Train Write Leveling        Time         669 ms

START - VMSE Train Write
Checkpoint Code: Socket 0, 0xB6, 0x56, 0x0000
Entry 0 - TrainDcc - DCCStart: 9, VocStart: 10, DCCFinal: 9, VocFinal: 10
Entry 1 - TrainDcc - DCCStart: 14, VocStart: 16, DCCFinal: 14, VocFinal: 16
Entry 2 - TrainDcc - DCCStart: 22, VocStart: 9, DCCFinal: 22, VocFinal: 9
Entry 3 - TrainDcc - DCCStart: 14, VocStart: 12, DCCFinal: 14, VocFinal: 12
Entry 4 - TrainDcc - DCCStart: 14, VocStart: 6, DCCFinal: 14, VocFinal: 10
Entry 5 - TrainDcc - DCCStart: 9, VocStart: 16, DCCFinal: 9, VocFinal: 16
Entry 6 - TrainDcc - DCCStart: 2, VocStart: 10, DCCFinal: 2, VocFinal: 19
Entry 7 - TrainDcc - DCCStart: 3, VocStart: 9, DCCFinal: 3, VocFinal: 9
Entry 8 - TrainDcc - DCCStart: 14, VocStart: 12, DCCFinal: 14, VocFinal: 12
N3.C0.S00: VmseWriteTraining Final: centerPi = 0x3E, PiEw = 0x27, centerVref = 0x46, vrefHeight = 0x2A
N3.C0.S01: VmseWriteTraining Final: centerPi = 0x3F, PiEw = 0x27, centerVref = 0x3C, vrefHeight = 0x2A
N3.C0.S02: VmseWriteTraining Final: centerPi = 0x3D, PiEw = 0x28, centerVref = 0x3F, vrefHeight = 0x2C
N3.C0.S03: VmseWriteTraining Final: centerPi = 0x39, PiEw = 0x28, centerVref = 0x41, vrefHeight = 0x28
N3.C0.S04: VmseWriteTraining Final: centerPi = 0x42, PiEw = 0x28, centerVref = 0x3F, vrefHeight = 0x28
N3.C0.S05: VmseWriteTraining Final: centerPi = 0x40, PiEw = 0x26, centerVref = 0x41, vrefHeight = 0x24
N3.C0.S06: VmseWriteTraining Final: centerPi = 0x40, PiEw = 0x28, centerVref = 0x3E, vrefHeight = 0x28
N3.C0.S07: VmseWriteTraining Final: centerPi = 0x43, PiEw = 0x25, centerVref = 0x41, vrefHeight = 0x2A
N3.C0.S08: VmseWriteTraining Final: centerPi = 0x3D, PiEw = 0x27, centerVref = 0x43, vrefHeight = 0x2C
N3.C0.S09: VmseWriteTraining Final: centerPi = 0x3B, PiEw = 0x29, centerVref = 0x3E, vrefHeight = 0x2C
N3.C0.S10: VmseWriteTraining Final: centerPi = 0x39, PiEw = 0x25, centerVref = 0x3E, vrefHeight = 0x2E
N3.C0.S11: VmseWriteTraining Final: centerPi = 0x38, PiEw = 0x2B, centerVref = 0x3F, vrefHeight = 0x2E
N3.C0.S12: VmseWriteTraining Final: centerPi = 0x41, PiEw = 0x23, centerVref = 0x3B, vrefHeight = 0x2C
N3.C0.S13: VmseWriteTraining Final: centerPi = 0x3F, PiEw = 0x27, centerVref = 0x3F, vrefHeight = 0x2A
N3.C0.S14: VmseWriteTraining Final: centerPi = 0x3E, PiEw = 0x23, centerVref = 0x3E, vrefHeight = 0x2A
N3.C0.S15: VmseWriteTraining Final: centerPi = 0x3E, PiEw = 0x27, centerVref = 0x3F, vrefHeight = 0x2A
N3.C0.S16: VmseWriteTraining Final: centerPi = 0x3E, PiEw = 0x28, centerVref = 0x3F, vrefHeight = 0x26
N3.C0.S17: VmseWriteTraining Final: centerPi = 0x3B, PiEw = 0x24, centerVref = 0x3F, vrefHeight = 0x28
N3.C0.S18: VmseWriteTraining Final: centerPi = 0x39, PiEw = 0x23, centerVref = 0x3D, vrefHeight = 0x26
N3.C0.S19: VmseWriteTraining Final: centerPi = 0x38, PiEw = 0x27, centerVref = 0x3C, vrefHeight = 0x26
N3.C0.S20: VmseWriteTraining Final: centerPi = 0x3F, PiEw = 0x27, centerVref = 0x3F, vrefHeight = 0x26
N3.C0.S21: VmseWriteTraining Final: centerPi = 0x3F, PiEw = 0x26, centerVref = 0x43, vrefHeight = 0x26
N3.C0.S22: VmseWriteTraining Final: centerPi = 0x3F, PiEw = 0x26, centerVref = 0x3D, vrefHeight = 0x28
N3.C0.S23: VmseWriteTraining Final: centerPi = 0x3F, PiEw = 0x27, centerVref = 0x40, vrefHeight = 0x28
N3.C0.S24: VmseWriteTraining Final: centerPi = 0x3C, PiEw = 0x29, centerVref = 0x3E, vrefHeight = 0x26
N3.C0.S25: VmseWriteTraining Final: centerPi = 0x3B, PiEw = 0x26, centerVref = 0x3A, vrefHeight = 0x28
N3.C0.S26: VmseWriteTraining Final: centerPi = 0x3C, PiEw = 0x26, centerVref = 0x3E, vrefHeight = 0x2A
N3.C0.S27: VmseWriteTraining Final: centerPi = 0x3A, PiEw = 0x2B, centerVref = 0x3B, vrefHeight = 0x28
N3.C0.S28: VmseWriteTraining Final: centerPi = 0x40, PiEw = 0x23, centerVref = 0x3E, vrefHeight = 0x2A
N3.C0.S29: VmseWriteTraining Final: centerPi = 0x3F, PiEw = 0x29, centerVref = 0x3F, vrefHeight = 0x28
N3.C0.S30: VmseWriteTraining Final: centerPi = 0x41, PiEw = 0x25, centerVref = 0x3E, vrefHeight = 0x2A
N3.C0.S31: VmseWriteTraining Final: centerPi = 0x40, PiEw = 0x28, centerVref = 0x41, vrefHeight = 0x28
N3.C0.S32: VmseWriteTraining Final: centerPi = 0x3D, PiEw = 0x2B, centerVref = 0x3F, vrefHeight = 0x2C
N3.C0.S33: VmseWriteTraining Final: centerPi = 0x3C, PiEw = 0x25, centerVref = 0x3D, vrefHeight = 0x2C
N3.C0.S34: VmseWriteTraining Final: centerPi = 0x3A, PiEw = 0x2A, centerVref = 0x39, vrefHeight = 0x2C
N3.C0.S35: VmseWriteTraining Final: centerPi = 0x38, PiEw = 0x2B, centerVref = 0x3E, vrefHeight = 0x2C
N3.C0.S36: VmseWriteTraining Final: centerPi = 0x41, PiEw = 0x26, centerVref = 0x3B, vrefHeight = 0x2C
N3.C0.S37: VmseWriteTraining Final: centerPi = 0x41, PiEw = 0x26, centerVref = 0x41, vrefHeight = 0x2A
N3.C0.S38: VmseWriteTraining Final: centerPi = 0x3D, PiEw = 0x25, centerVref = 0x40, vrefHeight = 0x2E
N3.C0.S39: VmseWriteTraining Final: centerPi = 0x3F, PiEw = 0x25, centerVref = 0x43, vrefHeight = 0x2A
N3.C0.S40: VmseWriteTraining Final: centerPi = 0x3C, PiEw = 0x2A, centerVref = 0x43, vrefHeight = 0x2A
N3.C0.S41: VmseWriteTraining Final: centerPi = 0x3D, PiEw = 0x26, centerVref = 0x3E, vrefHeight = 0x2A
N3.C0.S42: VmseWriteTraining Final: centerPi = 0x3E, PiEw = 0x25, centerVref = 0x3B, vrefHeight = 0x2C
N3.C0.S43: VmseWriteTraining Final: centerPi = 0x3C, PiEw = 0x27, centerVref = 0x38, vrefHeight = 0x2C
Entry 0 - TrainDcc - DCCStart: 21, VocStart: 12, DCCFinal: 5, VocFinal: 12
N3.C0.S44: VmseWriteTraining Final: centerPi = 0x40, PiEw = 0x26, centerVref = 0x45, vrefHeight = 0x26
Entry 1 - TrainDcc - DCCStart: 42, VocStart: 13, DCCFinal: 42, VocFinal: 13
N3.C0.S45: VmseWriteTraining Final: centerPi = 0x3F, PiEw = 0x23, centerVref = 0x3F, vrefHeight = 0x26
Entry 2 - TrainDcc - DCCStart: 30, VocStart: 17, DCCFinal: 62, VocFinal: 17
N3.C0.S46: VmseWriteTraining Final: centerPi = 0x3F, PiEw = 0x20, centerVref = 0x43, vrefHeight = 0x28
Entry 0 - TrainDcc - DCCStart: 9, VocStart: 14, DCCFinal: 17, VocFinal: 14
Entry 3 - TrainDcc - DCCStart: 46, VocStart: 19, DCCFinal: 46, VocFinal: 19
N3.C0.S47: VmseWriteTraining Final: centerPi = 0x3E, PiEw = 0x22, centerVref = 0x3D, vrefHeight = 0x28
Entry 1 - TrainDcc - DCCStart: 9, VocStart: 11, DCCFinal: 9, VocFinal: 11
Entry 4 - TrainDcc - DCCStart: 18, VocStart: 11, DCCFinal: 18, VocFinal: 11
N3.C0.S48: VmseWriteTraining Final: centerPi = 0x39, PiEw = 0x22, centerVref = 0x45, vrefHeight = 0x22
Entry 2 - TrainDcc - DCCStart: 16, VocStart: 12, DCCFinal: 32, VocFinal: 12
Entry 5 - TrainDcc - DCCStart: 26, VocStart: 8, DCCFinal: 26, VocFinal: 8
N3.C0.S49: VmseWriteTraining Final: centerPi = 0x3C, PiEw = 0x21, centerVref = 0x43, vrefHeight = 0x24
Entry 3 - TrainDcc - DCCStart: 2, VocStart: 13, DCCFinal: 2, VocFinal: 13
Entry 6 - TrainDcc - DCCStart: 6, VocStart: 16, DCCFinal: 6, VocFinal: 21
N3.C0.S50: VmseWriteTraining Final: centerPi = 0x3C, PiEw = 0x25, centerVref = 0x40, vrefHeight = 0x28
Entry 4 - TrainDcc - DCCStart: 5, VocStart: 12, DCCFinal: 5, VocFinal: 19
Entry 7 - TrainDcc - DCCStart: 37, VocStart: 12, DCCFinal: 37, VocFinal: 12
Entry 0 - TrainDcc - DCCStart: 3, VocStart: 12, DCCFinal: 43, VocFinal: 12
N3.C0.S51: VmseWriteTraining Final: centerPi = 0x38, PiEw = 0x25, centerVref = 0x3C, vrefHeight = 0x28
Entry 5 - TrainDcc - DCCStart: 14, VocStart: 13, DCCFinal: 14, VocFinal: 13
Entry 8 - TrainDcc - DCCStart: 11, VocStart: 17, DCCFinal: 11, VocFinal: 17
Entry 1 - TrainDcc - DCCStart: 11, VocStart: 14, DCCFinal: 11, VocFinal: 14
N3.C0.S52: VmseWriteTraining Final: centerPi = 0x42, PiEw = 0x22, centerVref = 0x40, vrefHeight = 0x2A
Entry 6 - TrainDcc - DCCStart: 12, VocStart: 17, DCCFinal: 12, VocFinal: 23
Entry 2 - TrainDcc - DCCStart: 11, VocStart: 17, DCCFinal: 27, VocFinal: 17
N3.C0.S53: VmseWriteTraining Final: centerPi = 0x44, PiEw = 0x29, centerVref = 0x3D, vrefHeight = 0x2C
Entry 7 - TrainDcc - DCCStart: 12, VocStart: 12, DCCFinal: 12, VocFinal: 12
Entry 3 - TrainDcc - DCCStart: 23, VocStart: 14, DCCFinal: 23, VocFinal: 14
N3.C0.S54: VmseWriteTraining Final: centerPi = 0x42, PiEw = 0x26, centerVref = 0x3C, vrefHeight = 0x2A
Entry 8 - TrainDcc - DCCStart: 5, VocStart: 9, DCCFinal: 5, VocFinal: 9
Entry 4 - TrainDcc - DCCStart: 10, VocStart: 12, DCCFinal: 10, VocFinal: 20
N3.C0.S55: VmseWriteTraining Final: centerPi = 0x41, PiEw = 0x25, centerVref = 0x3F, vrefHeight = 0x2A
Entry 5 - TrainDcc - DCCStart: 1, VocStart: 11, DCCFinal: 1, VocFinal: 11
N3.C0.S56: VmseWriteTraining Final: centerPi = 0x3E, PiEw = 0x27, centerVref = 0x3E, vrefHeight = 0x28
Entry 6 - TrainDcc - DCCStart: 3, VocStart: 14, DCCFinal: 3, VocFinal: 22
N3.C0.S57: VmseWriteTraining Final: centerPi = 0x3E, PiEw = 0x24, centerVref = 0x3D, vrefHeight = 0x2C
Entry 7 - TrainDcc - DCCStart: 6, VocStart: 13, DCCFinal: 6, VocFinal: 13
N3.C0.S58: VmseWriteTraining Final: centerPi = 0x3D, PiEw = 0x24, centerVref = 0x3D, vrefHeight = 0x2E
Entry 8 - TrainDcc - DCCStart: 7, VocStart: 10, DCCFinal: 7, VocFinal: 10
N3.C0.S59: VmseWriteTraining Final: centerPi = 0x3B, PiEw = 0x21, centerVref = 0x3E, vrefHeight = 0x2C
N3.C0.S60: VmseWriteTraining Final: centerPi = 0x43, PiEw = 0x21, centerVref = 0x3A, vrefHeight = 0x2A
N3.C0.S61: VmseWriteTraining Final: centerPi = 0x44, PiEw = 0x22, centerVref = 0x41, vrefHeight = 0x2A
N3.C0.S62: VmseWriteTraining Final: centerPi = 0x40, PiEw = 0x23, centerVref = 0x40, vrefHeight = 0x2C
N3.C0.S63: VmseWriteTraining Final: centerPi = 0x41, PiEw = 0x2B, centerVref = 0x3F, vrefHeight = 0x2C
N3.C0.S64: VmseWriteTraining Final: centerPi = 0x3E, PiEw = 0x29, centerVref = 0x41, vrefHeight = 0x28
N3.C0.S65: VmseWriteTraining Final: centerPi = 0x40, PiEw = 0x1E, centerVref = 0x40, vrefHeight = 0x2A
N3.C0.S66: VmseWriteTraining Final: centerPi = 0x3D, PiEw = 0x23, centerVref = 0x3C, vrefHeight = 0x2A
N3.C0.S67: VmseWriteTraining Final: centerPi = 0x3E, PiEw = 0x29, centerVref = 0x3E, vrefHeight = 0x2E
N3.C0.S68: VmseWriteTraining Final: centerPi = 0x43, PiEw = 0x26, centerVref = 0x3C, vrefHeight = 0x2A
N3.C0.S69: VmseWriteTraining Final: centerPi = 0x3F, PiEw = 0x27, centerVref = 0x46, vrefHeight = 0x28
N7.C0.S00: VmseWriteTraining Final: centerPi = 0x3D, PiEw = 0x27, centerVref = 0x46, vrefHeight = 0x2C
N3.C0.S70: VmseWriteTraining Final: centerPi = 0x42, PiEw = 0x23, centerVref = 0x3D, vrefHeight = 0x28
N7.C0.S01: VmseWriteTraining Final: centerPi = 0x3C, PiEw = 0x25, centerVref = 0x40, vrefHeight = 0x28
N3.C0.S71: VmseWriteTraining Final: centerPi = 0x41, PiEw = 0x28, centerVref = 0x3F, vrefHeight = 0x2C
N7.C0.S02: VmseWriteTraining Final: centerPi = 0x3E, PiEw = 0x27, centerVref = 0x40, vrefHeight = 0x2A

END - VMSE Train Write                 Time         2478 ms
N5.C0.S00: VmseWriteTraining Final: centerPi = 0x3C, PiEw = 0x28, centerVref = 0x44, vrefHeight = 0x26
N7.C0.S03: VmseWriteTraining Final: centerPi = 0x3C, PiEw = 0x25, centerVref = 0x46, vrefHeight = 0x28
N3: 
Total VMSE trainings latency = 15265 ms
N5.C0.S01: VmseWriteTraining Final: centerPi = 0x3D, PiEw = 0x28, centerVref = 0x41, vrefHeight = 0x28
N7.C0.S04: VmseWriteTraining Final: centerPi = 0x43, PiEw = 0x25, centerVref = 0x3D, vrefHeight = 0x26
N3: CpgcVmseTraining for VMSE1
N5.C0.S02: VmseWriteTraining Final: centerPi = 0x3A, PiEw = 0x24, centerVref = 0x3D, vrefHeight = 0x28
N7.C0.S05: VmseWriteTraining Final: centerPi = 0x43, PiEw = 0x24, centerVref = 0x44, vrefHeight = 0x2A
N3: Initialize VMSE Channels
N5.C0.S03: VmseWriteTraining Final: centerPi = 0x3A, PiEw = 0x25, centerVref = 0x40, vrefHeight = 0x26
N7.C0.S06: VmseWriteTraining Final: centerPi = 0x41, PiEw = 0x25, centerVref = 0x3F, vrefHeight = 0x28
N1.C0.S00: VmseWriteTraining Final: centerPi = 0x3B, PiEw = 0x27, centerVref = 0x44, vrefHeight = 0x2E

START - VMSE Detect DC
N5.C0.S04: VmseWriteTraining Final: centerPi = 0x40, PiEw = 0x26, centerVref = 0x41, vrefHeight = 0x24
N7.C0.S07: VmseWriteTraining Final: centerPi = 0x3F, PiEw = 0x23, centerVref = 0x3E, vrefHeight = 0x26
N1.C0.S01: VmseWriteTraining Final: centerPi = 0x39, PiEw = 0x24, centerVref = 0x44, vrefHeight = 0x28
N3: HsxVmseCompInit
N5.C0.S05: VmseWriteTraining Final: centerPi = 0x3E, PiEw = 0x2A, centerVref = 0x43, vrefHeight = 0x26
N7.C0.S08: VmseWriteTraining Final: centerPi = 0x3E, PiEw = 0x26, centerVref = 0x3F, vrefHeight = 0x2C
N1.C0.S02: VmseWriteTraining Final: centerPi = 0x3D, PiEw = 0x23, centerVref = 0x39, vrefHeight = 0x2C
N3.C1: Skip DC Detect check for CMD results
N5.C0.S06: VmseWriteTraining Final: centerPi = 0x3D, PiEw = 0x23, centerVref = 0x40, vrefHeight = 0x26
N7.C0.S09: VmseWriteTraining Final: centerPi = 0x3A, PiEw = 0x27, centerVref = 0x3D, vrefHeight = 0x2C
N1.C0.S03: VmseWriteTraining Final: centerPi = 0x37, PiEw = 0x28, centerVref = 0x3D, vrefHeight = 0x2C
N3.C1: Skip DC Detect check for CMD results
N5.C0.S07: VmseWriteTraining Final: centerPi = 0x40, PiEw = 0x27, centerVref = 0x40, vrefHeight = 0x26
N7.C0.S10: VmseWriteTraining Final: centerPi = 0x38, PiEw = 0x26, centerVref = 0x40, vrefHeight = 0x2E
N1.C0.S04: VmseWriteTraining Final: centerPi = 0x3B, PiEw = 0x24, centerVref = 0x40, vrefHeight = 0x22
N3: HsxVmseCompInit
N5.C0.S08: VmseWriteTraining Final: centerPi = 0x3C, PiEw = 0x24, centerVref = 0x44, vrefHeight = 0x2A
N7.C0.S11: VmseWriteTraining Final: centerPi = 0x3A, PiEw = 0x28, centerVref = 0x43, vrefHeight = 0x30
N1.C0.S05: VmseWriteTraining Final: centerPi = 0x3C, PiEw = 0x2A, centerVref = 0x3F, vrefHeight = 0x28
N3.C1: VmseDetectDC: SUCCESS
N5.C0.S09: VmseWriteTraining Final: centerPi = 0x3B, PiEw = 0x24, centerVref = 0x3D, vrefHeight = 0x28
N7.C0.S12: VmseWriteTraining Final: centerPi = 0x3E, PiEw = 0x28, centerVref = 0x40, vrefHeight = 0x2A
N1.C0.S06: VmseWriteTraining Final: centerPi = 0x3B, PiEw = 0x29, centerVref = 0x40, vrefHeight = 0x2A
N3.C1: VmseDetectClock
N5.C0.S10: VmseWriteTraining Final: centerPi = 0x3B, PiEw = 0x20, centerVref = 0x3E, vrefHeight = 0x2A
N7.C0.S13: VmseWriteTraining Final: centerPi = 0x3E, PiEw = 0x25, centerVref = 0x3E, vrefHeight = 0x2C
N1.C0.S07: VmseWriteTraining Final: centerPi = 0x3E, PiEw = 0x28, centerVref = 0x3C, vrefHeight = 0x2A
N5.C0.S11: VmseWriteTraining Final: centerPi = 0x3A, PiEw = 0x2A, centerVref = 0x42, vrefHeight = 0x2A
N7.C0.S14: VmseWriteTraining Final: centerPi = 0x3B, PiEw = 0x26, centerVref = 0x45, vrefHeight = 0x2C
N1.C0.S08: VmseWriteTraining Final: centerPi = 0x3C, PiEw = 0x2A, centerVref = 0x42, vrefHeight = 0x2C
N5.C0.S12: VmseWriteTraining Final: centerPi = 0x41, PiEw = 0x24, centerVref = 0x3F, vrefHeight = 0x2A
N7.C0.S15: VmseWriteTraining Final: centerPi = 0x3B, PiEw = 0x26, centerVref = 0x3F, vrefHeight = 0x2C
N1.C0.S09: VmseWriteTraining Final: centerPi = 0x3E, PiEw = 0x22, centerVref = 0x3A, vrefHeight = 0x28
N5.C0.S13: VmseWriteTraining Final: centerPi = 0x40, PiEw = 0x25, centerVref = 0x3D, vrefHeight = 0x24
N7.C0.S16: VmseWriteTraining Final: centerPi = 0x3B, PiEw = 0x27, centerVref = 0x45, vrefHeight = 0x26
N1.C0.S10: VmseWriteTraining Final: centerPi = 0x3B, PiEw = 0x26, centerVref = 0x3E, vrefHeight = 0x2E
N5.C0.S14: VmseWriteTraining Final: centerPi = 0x3E, PiEw = 0x22, centerVref = 0x3D, vrefHeight = 0x28
N7.C0.S17: VmseWriteTraining Final: centerPi = 0x38, PiEw = 0x29, centerVref = 0x3F, vrefHeight = 0x28
N1.C0.S11: VmseWriteTraining Final: centerPi = 0x3C, PiEw = 0x25, centerVref = 0x40, vrefHeight = 0x2E
N5.C0.S15: VmseWriteTraining Final: centerPi = 0x3F, PiEw = 0x23, centerVref = 0x41, vrefHeight = 0x28
N7.C0.S18: VmseWriteTraining Final: centerPi = 0x3C, PiEw = 0x24, centerVref = 0x3A, vrefHeight = 0x2A
N1.C0.S12: VmseWriteTraining Final: centerPi = 0x43, PiEw = 0x20, centerVref = 0x3A, vrefHeight = 0x2C
N3.C1: VmseDetectClock: SUCCESS
N5.C0.S16: VmseWriteTraining Final: centerPi = 0x3C, PiEw = 0x26, centerVref = 0x44, vrefHeight = 0x22
N7.C0.S19: VmseWriteTraining Final: centerPi = 0x3A, PiEw = 0x2B, centerVref = 0x3B, vrefHeight = 0x2C
N1.C0.S13: VmseWriteTraining Final: centerPi = 0x42, PiEw = 0x22, centerVref = 0x3E, vrefHeight = 0x2C

END - VMSE Detect DC                   Time         417 ms
N5.C0.S17: VmseWriteTraining Final: centerPi = 0x3B, PiEw = 0x26, centerVref = 0x3E, vrefHeight = 0x26
N7.C0.S20: VmseWriteTraining Final: centerPi = 0x42, PiEw = 0x25, centerVref = 0x3D, vrefHeight = 0x2C
N1.C0.S14: VmseWriteTraining Final: centerPi = 0x41, PiEw = 0x23, centerVref = 0x3F, vrefHeight = 0x2C

START - MXB Clock Train
N5.C0.S18: VmseWriteTraining Final: centerPi = 0x39, PiEw = 0x27, centerVref = 0x40, vrefHeight = 0x26
N7.C0.S21: VmseWriteTraining Final: centerPi = 0x3E, PiEw = 0x28, centerVref = 0x3F, vrefHeight = 0x28
N1.C0.S15: VmseWriteTraining Final: centerPi = 0x3D, PiEw = 0x2B, centerVref = 0x41, vrefHeight = 0x28
N5.C0.S19: VmseWriteTraining Final: centerPi = 0x36, PiEw = 0x2A, centerVref = 0x41, vrefHeight = 0x28
N7.C0.S22: VmseWriteTraining Final: centerPi = 0x3D, PiEw = 0x26, centerVref = 0x3B, vrefHeight = 0x28
N1.C0.S16: VmseWriteTraining Final: centerPi = 0x3C, PiEw = 0x26, centerVref = 0x3E, vrefHeight = 0x26
N5.C0.S20: VmseWriteTraining Final: centerPi = 0x3F, PiEw = 0x27, centerVref = 0x3C, vrefHeight = 0x26
N7.C0.S23: VmseWriteTraining Final: centerPi = 0x3B, PiEw = 0x27, centerVref = 0x40, vrefHeight = 0x26
N1.C0.S17: VmseWriteTraining Final: centerPi = 0x38, PiEw = 0x1F, centerVref = 0x48, vrefHeight = 0x22
N3.C2: VmseRefVckResync: ddrFreq = 0x2, VMSE_MODE_2_1 = 1, VMSE_PREAMBLE_2UI = 0
N5.C0.S21: VmseWriteTraining Final: centerPi = 0x3D, PiEw = 0x23, centerVref = 0x3E, vrefHeight = 0x22
N7.C0.S24: VmseWriteTraining Final: centerPi = 0x37, PiEw = 0x29, centerVref = 0x41, vrefHeight = 0x24
N1.C0.S18: VmseWriteTraining Final: centerPi = 0x39, PiEw = 0x25, centerVref = 0x43, vrefHeight = 0x28
N3.C2: VmseRefVckResync: VLINKFREQNXT set to: 0x20F940A
N5.C0.S22: VmseWriteTraining Final: centerPi = 0x3D, PiEw = 0x23, centerVref = 0x3B, vrefHeight = 0x28
N7.C0.S25: VmseWriteTraining Final: centerPi = 0x38, PiEw = 0x23, centerVref = 0x3F, vrefHeight = 0x28
N1.C0.S19: VmseWriteTraining Final: centerPi = 0x36, PiEw = 0x2A, centerVref = 0x40, vrefHeight = 0x28
N3.C1: VmseTrainClockAlign: JCK clkadjcnt =3
N5.C0.S23: VmseWriteTraining Final: centerPi = 0x3E, PiEw = 0x28, centerVref = 0x3F, vrefHeight = 0x24
N7.C0.S26: VmseWriteTraining Final: centerPi = 0x39, PiEw = 0x25, centerVref = 0x43, vrefHeight = 0x2C
N1.C0.S20: VmseWriteTraining Final: centerPi = 0x3F, PiEw = 0x1E, centerVref = 0x3F, vrefHeight = 0x22

END - MXB Clock Train                  Time         189 ms
N5.C0.S24: VmseWriteTraining Final: centerPi = 0x3D, PiEw = 0x22, centerVref = 0x3B, vrefHeight = 0x22
N7.C0.S27: VmseWriteTraining Final: centerPi = 0x39, PiEw = 0x24, centerVref = 0x3C, vrefHeight = 0x2A
N1.C0.S21: VmseWriteTraining Final: centerPi = 0x3E, PiEw = 0x29, centerVref = 0x44, vrefHeight = 0x26

START - VMSE Train Command
N5.C0.S25: VmseWriteTraining Final: centerPi = 0x3D, PiEw = 0x27, centerVref = 0x41, vrefHeight = 0x28
N7.C0.S28: VmseWriteTraining Final: centerPi = 0x3C, PiEw = 0x25, centerVref = 0x3B, vrefHeight = 0x28
N1.C0.S22: VmseWriteTraining Final: centerPi = 0x3B, PiEw = 0x27, centerVref = 0x3B, vrefHeight = 0x2A
N3.C1.B00: HsxCtlXoverInit: invertPiClk = 0x0, RankUsed = 0xFFF, Training = 0x38FFF26
N5.C0.S26: VmseWriteTraining Final: centerPi = 0x3C, PiEw = 0x25, centerVref = 0x3F, vrefHeight = 0x28
N7.C0.S29: VmseWriteTraining Final: centerPi = 0x3A, PiEw = 0x2A, centerVref = 0x44, vrefHeight = 0x2A
N1.C0.S23: VmseWriteTraining Final: centerPi = 0x3D, PiEw = 0x26, centerVref = 0x3D, vrefHeight = 0x28
N3.C1.B01: HsxCtlXoverInit: invertPiClk = 0x0, RankUsed = 0xFFF, Training = 0x38FFF03
N5.C0.S27: VmseWriteTraining Final: centerPi = 0x3A, PiEw = 0x28, centerVref = 0x3F, vrefHeight = 0x24
N7.C0.S30: VmseWriteTraining Final: centerPi = 0x3B, PiEw = 0x26, centerVref = 0x3E, vrefHeight = 0x26
N1.C0.S24: VmseWriteTraining Final: centerPi = 0x39, PiEw = 0x28, centerVref = 0x41, vrefHeight = 0x24
N5.C0.S28: VmseWriteTraining Final: centerPi = 0x40, PiEw = 0x22, centerVref = 0x3F, vrefHeight = 0x24
N7.C0.S31: VmseWriteTraining Final: centerPi = 0x3D, PiEw = 0x27, centerVref = 0x3B, vrefHeight = 0x28
N1.C0.S25: VmseWriteTraining Final: centerPi = 0x3C, PiEw = 0x24, centerVref = 0x3C, vrefHeight = 0x2A
N5.C0.S29: VmseWriteTraining Final: centerPi = 0x42, PiEw = 0x23, centerVref = 0x3F, vrefHeight = 0x24
N7.C0.S32: VmseWriteTraining Final: centerPi = 0x3C, PiEw = 0x26, centerVref = 0x3E, vrefHeight = 0x2A
N1.C0.S26: VmseWriteTraining Final: centerPi = 0x39, PiEw = 0x24, centerVref = 0x42, vrefHeight = 0x2A
N3.C1: VmseTrainCmdFine: vmse link sts = 0x4947
N5.C0.S30: VmseWriteTraining Final: centerPi = 0x40, PiEw = 0x25, centerVref = 0x40, vrefHeight = 0x26
N7.C0.S33: VmseWriteTraining Final: centerPi = 0x38, PiEw = 0x2A, centerVref = 0x41, vrefHeight = 0x2A
N1.C0.S27: VmseWriteTraining Final: centerPi = 0x38, PiEw = 0x24, centerVref = 0x42, vrefHeight = 0x28
N5.C0.S31: VmseWriteTraining Final: centerPi = 0x41, PiEw = 0x26, centerVref = 0x3B, vrefHeight = 0x24
N7.C0.S34: VmseWriteTraining Final: centerPi = 0x39, PiEw = 0x25, centerVref = 0x45, vrefHeight = 0x2C
N1.C0.S28: VmseWriteTraining Final: centerPi = 0x3E, PiEw = 0x1E, centerVref = 0x3C, vrefHeight = 0x28
N5.C0.S32: VmseWriteTraining Final: centerPi = 0x3C, PiEw = 0x28, centerVref = 0x3E, vrefHeight = 0x26
N7.C0.S35: VmseWriteTraining Final: centerPi = 0x38, PiEw = 0x28, centerVref = 0x3F, vrefHeight = 0x2C
N1.C0.S29: VmseWriteTraining Final: centerPi = 0x3D, PiEw = 0x28, centerVref = 0x44, vrefHeight = 0x26
N5.C0.S33: VmseWriteTraining Final: centerPi = 0x3C, PiEw = 0x2A, centerVref = 0x44, vrefHeight = 0x2A
N7.C0.S36: VmseWriteTraining Final: centerPi = 0x40, PiEw = 0x25, centerVref = 0x3D, vrefHeight = 0x2C
N1.C0.S30: VmseWriteTraining Final: centerPi = 0x3E, PiEw = 0x25, centerVref = 0x3D, vrefHeight = 0x26
N5.C0.S34: VmseWriteTraining Final: centerPi = 0x3B, PiEw = 0x28, centerVref = 0x3B, vrefHeight = 0x2C
N7.C0.S37: VmseWriteTraining Final: centerPi = 0x3F, PiEw = 0x26, centerVref = 0x45, vrefHeight = 0x2A
N1.C0.S31: VmseWriteTraining Final: centerPi = 0x3E, PiEw = 0x26, centerVref = 0x40, vrefHeight = 0x26
N5.C0.S35: VmseWriteTraining Final: centerPi = 0x3A, PiEw = 0x2B, centerVref = 0x43, vrefHeight = 0x2C
N7.C0.S38: VmseWriteTraining Final: centerPi = 0x3F, PiEw = 0x26, centerVref = 0x3F, vrefHeight = 0x2C
N1.C0.S32: VmseWriteTraining Final: centerPi = 0x3A, PiEw = 0x29, centerVref = 0x41, vrefHeight = 0x28
N5.C0.S36: VmseWriteTraining Final: centerPi = 0x41, PiEw = 0x29, centerVref = 0x3B, vrefHeight = 0x2A
N7.C0.S39: VmseWriteTraining Final: centerPi = 0x3F, PiEw = 0x27, centerVref = 0x40, vrefHeight = 0x2A
N1.C0.S33: VmseWriteTraining Final: centerPi = 0x3B, PiEw = 0x22, centerVref = 0x3F, vrefHeight = 0x2A
N5.C0.S37: VmseWriteTraining Final: centerPi = 0x43, PiEw = 0x27, centerVref = 0x40, vrefHeight = 0x2A
N7.C0.S40: VmseWriteTraining Final: centerPi = 0x36, PiEw = 0x28, centerVref = 0x49, vrefHeight = 0x28
N1.C0.S34: VmseWriteTraining Final: centerPi = 0x36, PiEw = 0x27, centerVref = 0x3B, vrefHeight = 0x2C
N5.C0.S38: VmseWriteTraining Final: centerPi = 0x3D, PiEw = 0x27, centerVref = 0x40, vrefHeight = 0x2A
N7.C0.S41: VmseWriteTraining Final: centerPi = 0x3B, PiEw = 0x2B, centerVref = 0x40, vrefHeight = 0x2A
N1.C0.S35: VmseWriteTraining Final: centerPi = 0x3E, PiEw = 0x26, centerVref = 0x3F, vrefHeight = 0x2E
N5.C0.S39: VmseWriteTraining Final: centerPi = 0x41, PiEw = 0x2A, centerVref = 0x3A, vrefHeight = 0x2A
N7.C0.S42: VmseWriteTraining Final: centerPi = 0x39, PiEw = 0x28, centerVref = 0x3A, vrefHeight = 0x2C
N1.C0.S36: VmseWriteTraining Final: centerPi = 0x41, PiEw = 0x26, centerVref = 0x3A, vrefHeight = 0x2C
N5.C0.S40: VmseWriteTraining Final: centerPi = 0x3B, PiEw = 0x26, centerVref = 0x40, vrefHeight = 0x28
N7.C0.S43: VmseWriteTraining Final: centerPi = 0x38, PiEw = 0x24, centerVref = 0x3D, vrefHeight = 0x28
N1.C0.S37: VmseWriteTraining Final: centerPi = 0x3D, PiEw = 0x28, centerVref = 0x42, vrefHeight = 0x28
N5.C0.S41: VmseWriteTraining Final: centerPi = 0x3A, PiEw = 0x2C, centerVref = 0x41, vrefHeight = 0x28
N7.C0.S44: VmseWriteTraining Final: centerPi = 0x41, PiEw = 0x27, centerVref = 0x3C, vrefHeight = 0x2A
N1.C0.S38: VmseWriteTraining Final: centerPi = 0x3B, PiEw = 0x2B, centerVref = 0x41, vrefHeight = 0x2C
N5.C0.S42: VmseWriteTraining Final: centerPi = 0x37, PiEw = 0x23, centerVref = 0x3D, vrefHeight = 0x28
N7.C0.S45: VmseWriteTraining Final: centerPi = 0x3D, PiEw = 0x25, centerVref = 0x3F, vrefHeight = 0x28
N1.C0.S39: VmseWriteTraining Final: centerPi = 0x42, PiEw = 0x29, centerVref = 0x3B, vrefHeight = 0x2E
N5.C0.S43: VmseWriteTraining Final: centerPi = 0x3A, PiEw = 0x26, centerVref = 0x39, vrefHeight = 0x28
N7.C0.S46: VmseWriteTraining Final: centerPi = 0x3C, PiEw = 0x25, centerVref = 0x3C, vrefHeight = 0x2A
N1.C0.S40: VmseWriteTraining Final: centerPi = 0x3D, PiEw = 0x25, centerVref = 0x3F, vrefHeight = 0x28
N5.C0.S44: VmseWriteTraining Final: centerPi = 0x3E, PiEw = 0x25, centerVref = 0x3C, vrefHeight = 0x26
N7.C0.S47: VmseWriteTraining Final: centerPi = 0x3D, PiEw = 0x27, centerVref = 0x3D, vrefHeight = 0x28
N1.C0.S41: VmseWriteTraining Final: centerPi = 0x40, PiEw = 0x24, centerVref = 0x40, vrefHeight = 0x26
N5.C0.S45: VmseWriteTraining Final: centerPi = 0x3D, PiEw = 0x25, centerVref = 0x41, vrefHeight = 0x28
N7.C0.S48: VmseWriteTraining Final: centerPi = 0x3C, PiEw = 0x26, centerVref = 0x3F, vrefHeight = 0x26
N1.C0.S42: VmseWriteTraining Final: centerPi = 0x3C, PiEw = 0x24, centerVref = 0x3B, vrefHeight = 0x28
N5.C0.S46: VmseWriteTraining Final: centerPi = 0x3E, PiEw = 0x21, centerVref = 0x3E, vrefHeight = 0x26
N7.C0.S49: VmseWriteTraining Final: centerPi = 0x3D, PiEw = 0x27, centerVref = 0x3D, vrefHeight = 0x2A
N1.C0.S43: VmseWriteTraining Final: centerPi = 0x3D, PiEw = 0x1F, centerVref = 0x3F, vrefHeight = 0x2A
N5.C0.S47: VmseWriteTraining Final: centerPi = 0x3D, PiEw = 0x24, centerVref = 0x42, vrefHeight = 0x26
N7.C0.S50: VmseWriteTraining Final: centerPi = 0x3C, PiEw = 0x23, centerVref = 0x3F, vrefHeight = 0x28
N1.C0.S44: VmseWriteTraining Final: centerPi = 0x41, PiEw = 0x22, centerVref = 0x3D, vrefHeight = 0x28
N5.C0.S48: VmseWriteTraining Final: centerPi = 0x3A, PiEw = 0x26, centerVref = 0x3E, vrefHeight = 0x22
N7.C0.S51: VmseWriteTraining Final: centerPi = 0x37, PiEw = 0x27, centerVref = 0x3F, vrefHeight = 0x28
N1.C0.S45: VmseWriteTraining Final: centerPi = 0x41, PiEw = 0x24, centerVref = 0x3C, vrefHeight = 0x28
N5.C0.S49: VmseWriteTraining Final: centerPi = 0x3A, PiEw = 0x28, centerVref = 0x3E, vrefHeight = 0x2A
N7.C0.S52: VmseWriteTraining Final: centerPi = 0x41, PiEw = 0x25, centerVref = 0x3F, vrefHeight = 0x28
N1.C0.S46: VmseWriteTraining Final: centerPi = 0x41, PiEw = 0x21, centerVref = 0x44, vrefHeight = 0x2A
N5.C0.S50: VmseWriteTraining Final: centerPi = 0x38, PiEw = 0x29, centerVref = 0x41, vrefHeight = 0x28
N7.C0.S53: VmseWriteTraining Final: centerPi = 0x40, PiEw = 0x25, centerVref = 0x3F, vrefHeight = 0x28
N1.C0.S47: VmseWriteTraining Final: centerPi = 0x3E, PiEw = 0x26, centerVref = 0x41, vrefHeight = 0x2A
N5.C0.S51: VmseWriteTraining Final: centerPi = 0x36, PiEw = 0x28, centerVref = 0x3E, vrefHeight = 0x28
N7.C0.S54: VmseWriteTraining Final: centerPi = 0x40, PiEw = 0x24, centerVref = 0x3E, vrefHeight = 0x26
N1.C0.S48: VmseWriteTraining Final: centerPi = 0x3C, PiEw = 0x24, centerVref = 0x3E, vrefHeight = 0x26
N5.C0.S52: VmseWriteTraining Final: centerPi = 0x3F, PiEw = 0x26, centerVref = 0x40, vrefHeight = 0x2A
N7.C0.S55: VmseWriteTraining Final: centerPi = 0x41, PiEw = 0x28, centerVref = 0x39, vrefHeight = 0x2C
N1.C0.S49: VmseWriteTraining Final: centerPi = 0x3D, PiEw = 0x29, centerVref = 0x3E, vrefHeight = 0x2A
N5.C0.S53: VmseWriteTraining Final: centerPi = 0x3F, PiEw = 0x27, centerVref = 0x3D, vrefHeight = 0x28
N7.C0.S56: VmseWriteTraining Final: centerPi = 0x39, PiEw = 0x26, centerVref = 0x45, vrefHeight = 0x28
N1.C0.S50: VmseWriteTraining Final: centerPi = 0x3C, PiEw = 0x24, centerVref = 0x3F, vrefHeight = 0x28
N5.C0.S54: VmseWriteTraining Final: centerPi = 0x3D, PiEw = 0x24, centerVref = 0x40, vrefHeight = 0x26
N7.C0.S57: VmseWriteTraining Final: centerPi = 0x3B, PiEw = 0x28, centerVref = 0x3D, vrefHeight = 0x2C
N1.C0.S51: VmseWriteTraining Final: centerPi = 0x39, PiEw = 0x27, centerVref = 0x3D, vrefHeight = 0x28
N5.C0.S55: VmseWriteTraining Final: centerPi = 0x3D, PiEw = 0x27, centerVref = 0x3D, vrefHeight = 0x28
N7.C0.S58: VmseWriteTraining Final: centerPi = 0x36, PiEw = 0x28, centerVref = 0x3D, vrefHeight = 0x2A
N1.C0.S52: VmseWriteTraining Final: centerPi = 0x41, PiEw = 0x26, centerVref = 0x3F, vrefHeight = 0x28
N5.C0.S56: VmseWriteTraining Final: centerPi = 0x3C, PiEw = 0x24, centerVref = 0x3E, vrefHeight = 0x26
N7.C0.S59: VmseWriteTraining Final: centerPi = 0x34, PiEw = 0x26, centerVref = 0x3E, vrefHeight = 0x2C
N1.C0.S53: VmseWriteTraining Final: centerPi = 0x43, PiEw = 0x26, centerVref = 0x3D, vrefHeight = 0x28
N5.C0.S57: VmseWriteTraining Final: centerPi = 0x3D, PiEw = 0x23, centerVref = 0x3F, vrefHeight = 0x28
N7.C0.S60: VmseWriteTraining Final: centerPi = 0x3F, PiEw = 0x27, centerVref = 0x3B, vrefHeight = 0x2C
N1.C0.S54: VmseWriteTraining Final: centerPi = 0x40, PiEw = 0x27, centerVref = 0x3F, vrefHeight = 0x28
N5.C0.S58: VmseWriteTraining Final: centerPi = 0x3B, PiEw = 0x24, centerVref = 0x3D, vrefHeight = 0x28
N7.C0.S61: VmseWriteTraining Final: centerPi = 0x3E, PiEw = 0x23, centerVref = 0x3F, vrefHeight = 0x28
N1.C0.S55: VmseWriteTraining Final: centerPi = 0x41, PiEw = 0x29, centerVref = 0x3F, vrefHeight = 0x2C
N5.C0.S59: VmseWriteTraining Final: centerPi = 0x36, PiEw = 0x26, centerVref = 0x42, vrefHeight = 0x28
N7.C0.S62: VmseWriteTraining Final: centerPi = 0x38, PiEw = 0x23, centerVref = 0x3F, vrefHeight = 0x24
N1.C0.S56: VmseWriteTraining Final: centerPi = 0x3E, PiEw = 0x23, centerVref = 0x44, vrefHeight = 0x26
N5.C0.S60: VmseWriteTraining Final: centerPi = 0x42, PiEw = 0x26, centerVref = 0x3B, vrefHeight = 0x28
N7.C0.S63: VmseWriteTraining Final: centerPi = 0x3C, PiEw = 0x29, centerVref = 0x42, vrefHeight = 0x2C
N1.C0.S57: VmseWriteTraining Final: centerPi = 0x3F, PiEw = 0x23, centerVref = 0x3C, vrefHeight = 0x2A
N5.C0.S61: VmseWriteTraining Final: centerPi = 0x40, PiEw = 0x1E, centerVref = 0x3C, vrefHeight = 0x28
N7.C0.S64: VmseWriteTraining Final: centerPi = 0x3F, PiEw = 0x23, centerVref = 0x3E, vrefHeight = 0x2A
N1.C0.S58: VmseWriteTraining Final: centerPi = 0x3B, PiEw = 0x27, centerVref = 0x41, vrefHeight = 0x26
N5.C0.S62: VmseWriteTraining Final: centerPi = 0x3E, PiEw = 0x22, centerVref = 0x3B, vrefHeight = 0x28
N7.C0.S65: VmseWriteTraining Final: centerPi = 0x39, PiEw = 0x24, centerVref = 0x44, vrefHeight = 0x22
N1.C0.S59: VmseWriteTraining Final: centerPi = 0x38, PiEw = 0x26, centerVref = 0x43, vrefHeight = 0x28
N5.C0.S63: VmseWriteTraining Final: centerPi = 0x3F, PiEw = 0x24, centerVref = 0x3D, vrefHeight = 0x28
N7.C0.S66: VmseWriteTraining Final: centerPi = 0x3F, PiEw = 0x21, centerVref = 0x3E, vrefHeight = 0x2A
N1.C0.S60: VmseWriteTraining Final: centerPi = 0x40, PiEw = 0x22, centerVref = 0x3F, vrefHeight = 0x28
N5.C0.S64: VmseWriteTraining Final: centerPi = 0x3F, PiEw = 0x1F, centerVref = 0x3F, vrefHeight = 0x26
N7.C0.S67: VmseWriteTraining Final: centerPi = 0x3B, PiEw = 0x29, centerVref = 0x38, vrefHeight = 0x28
N1.C0.S61: VmseWriteTraining Final: centerPi = 0x41, PiEw = 0x23, centerVref = 0x41, vrefHeight = 0x28
N5.C0.S65: VmseWriteTraining Final: centerPi = 0x3D, PiEw = 0x1F, centerVref = 0x3E, vrefHeight = 0x22
N7.C0.S68: VmseWriteTraining Final: centerPi = 0x41, PiEw = 0x26, centerVref = 0x3E, vrefHeight = 0x2A
N1.C0.S62: VmseWriteTraining Final: centerPi = 0x40, PiEw = 0x1E, centerVref = 0x40, vrefHeight = 0x2A
N5.C0.S66: VmseWriteTraining Final: centerPi = 0x3D, PiEw = 0x20, centerVref = 0x3B, vrefHeight = 0x24
N7.C0.S69: VmseWriteTraining Final: centerPi = 0x3F, PiEw = 0x22, centerVref = 0x3E, vrefHeight = 0x26
N1.C0.S63: VmseWriteTraining Final: centerPi = 0x40, PiEw = 0x27, centerVref = 0x43, vrefHeight = 0x2A
N5.C0.S67: VmseWriteTraining Final: centerPi = 0x3B, PiEw = 0x25, centerVref = 0x3E, vrefHeight = 0x2A
N7.C0.S70: VmseWriteTraining Final: centerPi = 0x40, PiEw = 0x25, centerVref = 0x40, vrefHeight = 0x2A
N1.C0.S64: VmseWriteTraining Final: centerPi = 0x3D, PiEw = 0x21, centerVref = 0x46, vrefHeight = 0x28
N5.C0.S68: VmseWriteTraining Final: centerPi = 0x43, PiEw = 0x20, centerVref = 0x3E, vrefHeight = 0x26
N7.C0.S71: VmseWriteTraining Final: centerPi = 0x40, PiEw = 0x24, centerVref = 0x3F, vrefHeight = 0x28
N1.C0.S65: VmseWriteTraining Final: centerPi = 0x3A, PiEw = 0x21, centerVref = 0x3E, vrefHeight = 0x26
N5.C0.S69: VmseWriteTraining Final: centerPi = 0x41, PiEw = 0x20, centerVref = 0x41, vrefHeight = 0x28

END - VMSE Train Write                 Time         3987 ms
N1.C0.S66: VmseWriteTraining Final: centerPi = 0x3A, PiEw = 0x1F, centerVref = 0x3E, vrefHeight = 0x24
N5.C0.S70: VmseWriteTraining Final: centerPi = 0x40, PiEw = 0x1F, centerVref = 0x3F, vrefHeight = 0x28
N7: 
Total VMSE trainings latency = 16725 ms
N1.C0.S67: VmseWriteTraining Final: centerPi = 0x38, PiEw = 0x2A, centerVref = 0x41, vrefHeight = 0x2A
N5.C0.S71: VmseWriteTraining Final: centerPi = 0x41, PiEw = 0x24, centerVref = 0x37, vrefHeight = 0x26
N7: CpgcVmseTraining for VMSE1
N1.C0.S68: VmseWriteTraining Final: centerPi = 0x41, PiEw = 0x22, centerVref = 0x41, vrefHeight = 0x28

END - VMSE Train Write                 Time         3950 ms
N7: Initialize VMSE Channels
N1.C0.S69: VmseWriteTraining Final: centerPi = 0x3F, PiEw = 0x21, centerVref = 0x3E, vrefHeight = 0x28
N5: 
Total VMSE trainings latency = 17404 ms

START - VMSE Detect DC
N1.C0.S70: VmseWriteTraining Final: centerPi = 0x40, PiEw = 0x22, centerVref = 0x3E, vrefHeight = 0x26
N5: CpgcVmseTraining for VMSE1
N7: HsxVmseCompInit
N1.C0.S71: VmseWriteTraining Final: centerPi = 0x40, PiEw = 0x24, centerVref = 0x3A, vrefHeight = 0x26
N5: Initialize VMSE Channels
N7.C1: Skip DC Detect check for CMD results

END - VMSE Train Write                 Time         3938 ms

START - VMSE Detect DC
Checkpoint Code: Socket 0, 0xB6, 0x64, 0x0000
N5: HsxVmseCompInit
N7.C1: Skip DC Detect check for CMD results
N1: 
Total VMSE trainings latency = 17609 ms
N7: HsxVmseCompInit
N1: CpgcVmseTraining for VMSE1
N5.C1: Skip DC Detect check for CMD results
N7.C1: VmseDetectDC: SUCCESS
Checkpoint Code: Socket 0, 0xB6, 0x11, 0x0000
N7.C1: VmseDetectClock
N1: Initialize VMSE Channels
N5.C1: Skip DC Detect check for CMD results

START - VMSE Detect DC
N5: HsxVmseCompInit
Checkpoint Code: Socket 0, 0xB6, 0x46, 0x0000
N5.C1: VmseDetectDC: SUCCESS
N1: HsxVmseCompInit
N5.C1: VmseDetectClock
Checkpoint Code: Socket 0, 0xB6, 0x80, 0x0000
N1.C1: Skip DC Detect check for CMD results
N1.C1: Skip DC Detect check for CMD results
N1: HsxVmseCompInit
Checkpoint Code: Socket 0, 0xB6, 0x81, 0x0000
N1.C1: VmseDetectDC: SUCCESS
N1.C1: VmseDetectClock
N7.C1: VmseDetectClock: SUCCESS

END - VMSE Detect DC                   Time         252 ms

START - MXB Clock Train
N5.C1: VmseDetectClock: SUCCESS

END - VMSE Detect DC                   Time         233 ms

START - MXB Clock Train
N1.C1: VmseDetectClock: SUCCESS

END - VMSE Detect DC                   Time         234 ms

START - MXB Clock Train
Checkpoint Code: Socket 0, 0xB6, 0x48, 0x0000
N7.C2: VmseRefVckResync: ddrFreq = 0x2, VMSE_MODE_2_1 = 1, VMSE_PREAMBLE_2UI = 0
N5.C2: VmseRefVckResync: ddrFreq = 0x2, VMSE_MODE_2_1 = 1, VMSE_PREAMBLE_2UI = 0
N7.C2: VmseRefVckResync: VLINKFREQNXT set to: 0x20F940A
Checkpoint Code: Socket 0, 0xB6, 0x6C, 0x0000
N5.C2: VmseRefVckResync: VLINKFREQNXT set to: 0x20F940A
N7.C1: VmseTrainClockAlign: JCK clkadjcnt =0

END - MXB Clock Train                  Time         159 ms

START - VMSE Train Command
N5.C1: VmseTrainClockAlign: JCK clkadjcnt =3

END - MXB Clock Train                  Time         156 ms
N7.C1.B00: HsxCtlXoverInit: invertPiClk = 0x0, RankUsed = 0xFFF, Training = 0x38FFF23
N1.C1: VmseAdjustVckVoc: retrain Clock DCC.
   dcc1_vck = 0x3D, dcc2_vck = 0x3F, preampvoc = 0xA

START - VMSE Train Command
N7.C1.B01: HsxCtlXoverInit: invertPiClk = 0x0, RankUsed = 0xFFF, Training = 0x38FFF01
Checkpoint Code: Socket 0, 0xB6, 0x6C, 0x0000
N5.C1.B00: HsxCtlXoverInit: invertPiClk = 0x0, RankUsed = 0xFFF, Training = 0x38FFF25
N5.C1.B01: HsxCtlXoverInit: invertPiClk = 0x0, RankUsed = 0xFFF, Training = 0x38FFF02
N1.C1: VmseAdjustVckVoc: retrain Clock DCC.
   dcc1_vck = 0x31, dcc2_vck = 0x3F, preampvoc = 0xB
Checkpoint Code: Socket 0, 0xB6, 0x6C, 0x0000
N5.C1: VmseTrainCmdFine: vmse link sts = 0x4947
N7.C1: VmseTrainCmdFine: vmse link sts = 0x4947
N1.C1: VmseAdjustVckVoc: retrain Clock DCC.
   dcc1_vck = 0x21, dcc2_vck = 0x3F, preampvoc = 0xC
Checkpoint Code: Socket 0, 0xB6, 0x6C, 0x0000
N1.C2: VmseRefVckResync: ddrFreq = 0x2, VMSE_MODE_2_1 = 1, VMSE_PREAMBLE_2UI = 0
N1.C2: VmseRefVckResync: VLINKFREQNXT set to: 0x20F940A
N1.C1: VmseTrainClockAlign: JCK clkadjcnt =4

END - MXB Clock Train                  Time         414 ms

START - VMSE Train Command
Checkpoint Code: Socket 0, 0xB6, 0x4A, 0x0000
N1.C1.B00: HsxCtlXoverInit: invertPiClk = 0x0, RankUsed = 0xFFF, Training = 0x38FFF24
N1.C1.B01: HsxCtlXoverInit: invertPiClk = 0x0, RankUsed = 0xFFF, Training = 0x38FFF02
Checkpoint Code: Socket 0, 0xB6, 0x60, 0x0000
Checkpoint Code: Socket 0, 0xB6, 0x5A, 0x0000
N1.C1: VmseTrainCmdFine: vmse link sts = 0x4947
Entry 0 - TrainDcc - DCCStart: 7, VocStart: 11, DCCFinal: 15, VocFinal: 11
Entry 1 - TrainDcc - DCCStart: 56, VocStart: 11, DCCFinal: 40, VocFinal: 11
N3.C1.S00: VmseCmdFineTraining Final: centerPi = 0x60, PiEw = 0x30, centerVref = 0x3F, vrefHeight = 0x43
N3.C1.S01: VmseCmdFineTraining Final: centerPi = 0x5D, PiEw = 0x2F, centerVref = 0x3B, vrefHeight = 0x47
N3.C1.S02: VmseCmdFineTraining Final: centerPi = 0x5B, PiEw = 0x33, centerVref = 0x3C, vrefHeight = 0x45
N3.C1.S03: VmseCmdFineTraining Final: centerPi = 0x5F, PiEw = 0x2F, centerVref = 0x3C, vrefHeight = 0x45
N3.C1.S04: VmseCmdFineTraining Final: centerPi = 0x56, PiEw = 0x2E, centerVref = 0x3B, vrefHeight = 0x43
N3.C1.S05: VmseCmdFineTraining Final: centerPi = 0x5B, PiEw = 0x31, centerVref = 0x3F, vrefHeight = 0x45
N3.C1.S06: VmseCmdFineTraining Final: centerPi = 0x5A, PiEw = 0x2F, centerVref = 0x3B, vrefHeight = 0x47
N3.C1.S07: VmseCmdFineTraining Final: centerPi = 0x5D, PiEw = 0x31, centerVref = 0x3C, vrefHeight = 0x47
N3.C1.S08: VmseCmdFineTraining Final: centerPi = 0x56, PiEw = 0x2B, centerVref = 0x3D, vrefHeight = 0x3D
N3.C1.S09: VmseCmdFineTraining Final: centerPi = 0x59, PiEw = 0x30, centerVref = 0x40, vrefHeight = 0x3F
N3.C1.S10: VmseCmdFineTraining Final: centerPi = 0x59, PiEw = 0x2D, centerVref = 0x3B, vrefHeight = 0x41
N3.C1.S11: VmseCmdFineTraining Final: centerPi = 0x54, PiEw = 0x2E, centerVref = 0x43, vrefHeight = 0x3D
N3.C1.S12: VmseCmdFineTraining Final: centerPi = 0x5A, PiEw = 0x2D, centerVref = 0x3B, vrefHeight = 0x43
N3.C1.S13: VmseCmdFineTraining Final: centerPi = 0x56, PiEw = 0x2E, centerVref = 0x40, vrefHeight = 0x43
N3.C1.S14: VmseCmdFineTraining Final: centerPi = 0x59, PiEw = 0x33, centerVref = 0x3D, vrefHeight = 0x3F
N3.C1.S15: VmseCmdFineTraining Final: centerPi = 0x5E, PiEw = 0x2F, centerVref = 0x3F, vrefHeight = 0x3F
N3.C1.S16: VmseCmdFineTraining Final: centerPi = 0x5A, PiEw = 0x2E, centerVref = 0x39, vrefHeight = 0x47

END - VMSE Train Command               Time         7454 ms

START - VMSE Train Read Leveling
N3.C1: VmseReadLevelFineSetup: Initial RT = 101, Initial IO Latency = 0, Initial IO Comp = 15
N3.C1: VmseRLWLFineSearchAll: Entry
N3.C1: FINE READ LEVEL DELAY
N3.C1.S00: RCVEN DELAY = 45
N3.C1.S01: RCVEN DELAY = 42
N3.C1.S02: RCVEN DELAY = 31
N3.C1.S03: RCVEN DELAY = 39
N3.C1.S04: RCVEN DELAY = 137
N3.C1.S05: RCVEN DELAY = 129
N3.C1.S06: RCVEN DELAY = 123
N3.C1.S07: RCVEN DELAY = 123
N3.C1.S08: RCVEN DELAY = 120
N3.C1.S00: READ LEVEL: FINAL RCVEN DELAY (both nibbles) = 270
N3.C1.S01: READ LEVEL: FINAL RCVEN DELAY (both nibbles) = 267
N3.C1.S02: READ LEVEL: FINAL RCVEN DELAY (both nibbles) = 257
Entry 0 - TrainDcc - DCCStart: 25, VocStart: 10, DCCFinal: 17, VocFinal: 10
N3.C1.S03: READ LEVEL: FINAL RCVEN DELAY (both nibbles) = 265
Entry 1 - TrainDcc - DCCStart: 59, VocStart: 10, DCCFinal: 59, VocFinal: 10
N3.C1.S04: READ LEVEL: FINAL RCVEN DELAY (both nibbles) = 235
N3.C1.S05: READ LEVEL: FINAL RCVEN DELAY (both nibbles) = 227
N3.C1.S06: READ LEVEL: FINAL RCVEN DELAY (both nibbles) = 221
N3.C1.S07: READ LEVEL: FINAL RCVEN DELAY (both nibbles) = 221
N3.C1.S08: READ LEVEL: FINAL RCVEN DELAY (both nibbles) = 218
N3.C1.D0.S09: READ LEVEL: FINAL RT (all ranks) = 85, FINAL IO LATENCY (all ranks) = 4
N3.C1.D1.S09: READ LEVEL: FINAL RT (all ranks) = 85, FINAL IO LATENCY (all ranks) = 4

END - VMSE Train Read Leveling         Time         280 ms

START - VMSE Train Read
Entry 0 - TrainDcc - DCCStart: 35, VocStart: 9, DCCFinal: 27, VocFinal: 9
Entry 1 - TrainDcc - DCCStart: 8, VocStart: 9, DCCFinal: 24, VocFinal: 9
Entry 0 - TrainDcc - DCCStart: 26, VocStart: 12, DCCFinal: 26, VocFinal: 12
Entry 1 - TrainDcc - DCCStart: 49, VocStart: 12, DCCFinal: 17, VocFinal: 12
N5.C1.S00: VmseCmdFineTraining Final: centerPi = 0x60, PiEw = 0x32, centerVref = 0x3D, vrefHeight = 0x43
N5.C1.S01: VmseCmdFineTraining Final: centerPi = 0x5D, PiEw = 0x2F, centerVref = 0x3B, vrefHeight = 0x47
N5.C1.S02: VmseCmdFineTraining Final: centerPi = 0x5B, PiEw = 0x33, centerVref = 0x3B, vrefHeight = 0x45
N5.C1.S03: VmseCmdFineTraining Final: centerPi = 0x60, PiEw = 0x30, centerVref = 0x39, vrefHeight = 0x45
N5.C1.S04: VmseCmdFineTraining Final: centerPi = 0x56, PiEw = 0x30, centerVref = 0x3D, vrefHeight = 0x45
N5.C1.S05: VmseCmdFineTraining Final: centerPi = 0x5A, PiEw = 0x2F, centerVref = 0x3B, vrefHeight = 0x43
N5.C1.S06: VmseCmdFineTraining Final: centerPi = 0x5B, PiEw = 0x2F, centerVref = 0x3D, vrefHeight = 0x47
N5.C1.S07: VmseCmdFineTraining Final: centerPi = 0x5D, PiEw = 0x34, centerVref = 0x3A, vrefHeight = 0x45
N5.C1.S08: VmseCmdFineTraining Final: centerPi = 0x57, PiEw = 0x2F, centerVref = 0x3B, vrefHeight = 0x3F
N5.C1.S09: VmseCmdFineTraining Final: centerPi = 0x5A, PiEw = 0x30, centerVref = 0x3D, vrefHeight = 0x3F
N5.C1.S10: VmseCmdFineTraining Final: centerPi = 0x5B, PiEw = 0x2E, centerVref = 0x3E, vrefHeight = 0x45
N5.C1.S11: VmseCmdFineTraining Final: centerPi = 0x56, PiEw = 0x2E, centerVref = 0x3B, vrefHeight = 0x43
N5.C1.S12: VmseCmdFineTraining Final: centerPi = 0x5C, PiEw = 0x2D, centerVref = 0x37, vrefHeight = 0x43
N5.C1.S13: VmseCmdFineTraining Final: centerPi = 0x57, PiEw = 0x30, centerVref = 0x3D, vrefHeight = 0x43
N5.C1.S14: VmseCmdFineTraining Final: centerPi = 0x59, PiEw = 0x31, centerVref = 0x3B, vrefHeight = 0x43
N5.C1.S15: VmseCmdFineTraining Final: centerPi = 0x5F, PiEw = 0x2E, centerVref = 0x3A, vrefHeight = 0x45
N5.C1.S16: VmseCmdFineTraining Final: centerPi = 0x5A, PiEw = 0x2E, centerVref = 0x3E, vrefHeight = 0x45

END - VMSE Train Command               Time         6867 ms

START - VMSE Train Read Leveling
N5.C1: VmseReadLevelFineSetup: Initial RT = 101, Initial IO Latency = 0, Initial IO Comp = 15
N7.C1.S00: VmseCmdFineTraining Final: centerPi = 0x61, PiEw = 0x31, centerVref = 0x3A, vrefHeight = 0x43
N7.C1.S01: VmseCmdFineTraining Final: centerPi = 0x60, PiEw = 0x2F, centerVref = 0x39, vrefHeight = 0x47
N5.C1: VmseRLWLFineSearchAll: Entry
N7.C1.S02: VmseCmdFineTraining Final: centerPi = 0x5E, PiEw = 0x32, centerVref = 0x38, vrefHeight = 0x43
N5.C1: FINE READ LEVEL DELAY
N7.C1.S03: VmseCmdFineTraining Final: centerPi = 0x60, PiEw = 0x2F, centerVref = 0x42, vrefHeight = 0x41
N5.C1.S00: RCVEN DELAY = 41
N7.C1.S04: VmseCmdFineTraining Final: centerPi = 0x5D, PiEw = 0x2E, centerVref = 0x34, vrefHeight = 0x47
N5.C1.S01: RCVEN DELAY = 36
N7.C1.S05: VmseCmdFineTraining Final: centerPi = 0x5E, PiEw = 0x30, centerVref = 0x3C, vrefHeight = 0x45
N5.C1.S02: RCVEN DELAY = 151
N7.C1.S06: VmseCmdFineTraining Final: centerPi = 0x61, PiEw = 0x30, centerVref = 0x38, vrefHeight = 0x42
N5.C1.S03: RCVEN DELAY = 35
N7.C1.S07: VmseCmdFineTraining Final: centerPi = 0x61, PiEw = 0x32, centerVref = 0x39, vrefHeight = 0x45
N5.C1.S04: RCVEN DELAY = 131
N7.C1.S08: VmseCmdFineTraining Final: centerPi = 0x5A, PiEw = 0x2E, centerVref = 0x3C, vrefHeight = 0x3F
N5.C1.S05: RCVEN DELAY = 121
N7.C1.S09: VmseCmdFineTraining Final: centerPi = 0x5E, PiEw = 0x2D, centerVref = 0x3B, vrefHeight = 0x43
N5.C1.S06: RCVEN DELAY = 118
N7.C1.S10: VmseCmdFineTraining Final: centerPi = 0x5D, PiEw = 0x2E, centerVref = 0x3D, vrefHeight = 0x43
N5.C1.S07: RCVEN DELAY = 114
N7.C1.S11: VmseCmdFineTraining Final: centerPi = 0x58, PiEw = 0x2E, centerVref = 0x37, vrefHeight = 0x45
N5.C1.S08: RCVEN DELAY = 119
N7.C1.S12: VmseCmdFineTraining Final: centerPi = 0x5D, PiEw = 0x2D, centerVref = 0x41, vrefHeight = 0x3B
N5.C1.S00: READ LEVEL: FINAL RCVEN DELAY (both nibbles) = 140
N7.C1.S13: VmseCmdFineTraining Final: centerPi = 0x59, PiEw = 0x31, centerVref = 0x3D, vrefHeight = 0x3D
N1.C1.S00: VmseCmdFineTraining Final: centerPi = 0x61, PiEw = 0x33, centerVref = 0x3B, vrefHeight = 0x43
N5.C1.S01: READ LEVEL: FINAL RCVEN DELAY (both nibbles) = 135
N7.C1.S14: VmseCmdFineTraining Final: centerPi = 0x5E, PiEw = 0x2F, centerVref = 0x39, vrefHeight = 0x43
N1.C1.S01: VmseCmdFineTraining Final: centerPi = 0x61, PiEw = 0x30, centerVref = 0x39, vrefHeight = 0x47
N5.C1.S02: READ LEVEL: FINAL RCVEN DELAY (both nibbles) = 121
N7.C1.S15: VmseCmdFineTraining Final: centerPi = 0x60, PiEw = 0x2F, centerVref = 0x40, vrefHeight = 0x3D
N1.C1.S02: VmseCmdFineTraining Final: centerPi = 0x61, PiEw = 0x33, centerVref = 0x37, vrefHeight = 0x49
N5.C1.S03: READ LEVEL: FINAL RCVEN DELAY (both nibbles) = 133
N7.C1.S16: VmseCmdFineTraining Final: centerPi = 0x5C, PiEw = 0x2E, centerVref = 0x3C, vrefHeight = 0x45
N1.C1.S03: VmseCmdFineTraining Final: centerPi = 0x5E, PiEw = 0x30, centerVref = 0x3F, vrefHeight = 0x3D
N5.C1.S04: READ LEVEL: FINAL RCVEN DELAY (both nibbles) = 101
N1.C1.S04: VmseCmdFineTraining Final: centerPi = 0x58, PiEw = 0x30, centerVref = 0x38, vrefHeight = 0x41
N5.C1.S05: READ LEVEL: FINAL RCVEN DELAY (both nibbles) = 90
N1.C1.S05: VmseCmdFineTraining Final: centerPi = 0x5C, PiEw = 0x2F, centerVref = 0x38, vrefHeight = 0x47
N5.C1.S06: READ LEVEL: FINAL RCVEN DELAY (both nibbles) = 87
N1.C1.S06: VmseCmdFineTraining Final: centerPi = 0x5E, PiEw = 0x31, centerVref = 0x37, vrefHeight = 0x49
N5.C1.S07: READ LEVEL: FINAL RCVEN DELAY (both nibbles) = 84
N1.C1.S07: VmseCmdFineTraining Final: centerPi = 0x60, PiEw = 0x32, centerVref = 0x3D, vrefHeight = 0x45
N5.C1.S08: READ LEVEL: FINAL RCVEN DELAY (both nibbles) = 88
N1.C1.S08: VmseCmdFineTraining Final: centerPi = 0x58, PiEw = 0x2F, centerVref = 0x38, vrefHeight = 0x41
N5.C1.D0.S09: READ LEVEL: FINAL RT (all ranks) = 83, FINAL IO LATENCY (all ranks) = 2
N1.C1.S09: VmseCmdFineTraining Final: centerPi = 0x5B, PiEw = 0x2F, centerVref = 0x3D, vrefHeight = 0x3F
N5.C1.D1.S09: READ LEVEL: FINAL RT (all ranks) = 83, FINAL IO LATENCY (all ranks) = 2
N1.C1.S10: VmseCmdFineTraining Final: centerPi = 0x5B, PiEw = 0x2D, centerVref = 0x3D, vrefHeight = 0x43

END - VMSE Train Read Leveling         Time         548 ms
N1.C1.S11: VmseCmdFineTraining Final: centerPi = 0x57, PiEw = 0x2E, centerVref = 0x3F, vrefHeight = 0x43

START - VMSE Train Read

END - VMSE Train Command               Time         7492 ms
N1.C1.S12: VmseCmdFineTraining Final: centerPi = 0x5D, PiEw = 0x2F, centerVref = 0x38, vrefHeight = 0x43

START - VMSE Train Read Leveling
N1.C1.S13: VmseCmdFineTraining Final: centerPi = 0x59, PiEw = 0x2F, centerVref = 0x3A, vrefHeight = 0x43
N1.C1.S14: VmseCmdFineTraining Final: centerPi = 0x5C, PiEw = 0x31, centerVref = 0x3C, vrefHeight = 0x43
N1.C1.S15: VmseCmdFineTraining Final: centerPi = 0x65, PiEw = 0x30, centerVref = 0x35, vrefHeight = 0x49
N1.C1.S16: VmseCmdFineTraining Final: centerPi = 0x5D, PiEw = 0x2F, centerVref = 0x37, vrefHeight = 0x47
N7.C1: VmseReadLevelFineSetup: Initial RT = 101, Initial IO Latency = 0, Initial IO Comp = 15
N7.C1: VmseRLWLFineSearchAll: Entry
N7.C1: FINE READ LEVEL DELAY
N7.C1.S00: RCVEN DELAY = 117
N7.C1.S01: RCVEN DELAY = 113
N7.C1.S02: RCVEN DELAY = 94
N7.C1.S03: RCVEN DELAY = 109
N7.C1.S04: RCVEN DELAY = 138
N7.C1.S05: RCVEN DELAY = 68
N7.C1.S06: RCVEN DELAY = 130
N7.C1.S07: RCVEN DELAY = 60
N7.C1.S08: RCVEN DELAY = 58
N7.C1.S00: READ LEVEL: FINAL RCVEN DELAY (both nibbles) = 86
N7.C1.S01: READ LEVEL: FINAL RCVEN DELAY (both nibbles) = 80
N7.C1.S02: READ LEVEL: FINAL RCVEN DELAY (both nibbles) = 65

END - VMSE Train Command               Time         7389 ms
N7.C1.S03: READ LEVEL: FINAL RCVEN DELAY (both nibbles) = 80

START - VMSE Train Read Leveling
N7.C1.S04: READ LEVEL: FINAL RCVEN DELAY (both nibbles) = 107
Checkpoint Code: Socket 0, 0xB6, 0x4E, 0x0000
N7.C1.S05: READ LEVEL: FINAL RCVEN DELAY (both nibbles) = 40
N7.C1.S06: READ LEVEL: FINAL RCVEN DELAY (both nibbles) = 102
N7.C1.S07: READ LEVEL: FINAL RCVEN DELAY (both nibbles) = 30
N7.C1.S08: READ LEVEL: FINAL RCVEN DELAY (both nibbles) = 30
N7.C1.D0.S09: READ LEVEL: FINAL RT (all ranks) = 85, FINAL IO LATENCY (all ranks) = 2
N7.C1.D1.S09: READ LEVEL: FINAL RT (all ranks) = 85, FINAL IO LATENCY (all ranks) = 2

END - VMSE Train Read Leveling         Time         278 ms

START - VMSE Train Read
N1.C1: VmseReadLevelFineSetup: Initial RT = 101, Initial IO Latency = 0, Initial IO Comp = 15
N1.C1: VmseRLWLFineSearchAll: Entry
N1.C1: FINE READ LEVEL DELAY
N1.C1.S00: RCVEN DELAY = 38
N1.C1.S01: RCVEN DELAY = 39
N1.C1.S02: RCVEN DELAY = 151
N1.C1.S03: RCVEN DELAY = 31
N1.C1.S04: RCVEN DELAY = 130
N1.C1.S05: RCVEN DELAY = 124
N1.C1.S06: RCVEN DELAY = 117
N1.C1.S07: RCVEN DELAY = 116
N1.C1.S08: RCVEN DELAY = 113
N1.C1.S00: READ LEVEL: FINAL RCVEN DELAY (both nibbles) = 263
N1.C1.S01: READ LEVEL: FINAL RCVEN DELAY (both nibbles) = 264
N1.C1.S02: READ LEVEL: FINAL RCVEN DELAY (both nibbles) = 250
N1.C1.S03: READ LEVEL: FINAL RCVEN DELAY (both nibbles) = 259
N1.C1.S04: READ LEVEL: FINAL RCVEN DELAY (both nibbles) = 226
N1.C1.S05: READ LEVEL: FINAL RCVEN DELAY (both nibbles) = 222
N1.C1.S06: READ LEVEL: FINAL RCVEN DELAY (both nibbles) = 215
N1.C1.S07: READ LEVEL: FINAL RCVEN DELAY (both nibbles) = 213
N1.C1.S08: READ LEVEL: FINAL RCVEN DELAY (both nibbles) = 211
N1.C1.D0.S09: READ LEVEL: FINAL RT (all ranks) = 85, FINAL IO LATENCY (all ranks) = 4
N1.C1.D1.S09: READ LEVEL: FINAL RT (all ranks) = 85, FINAL IO LATENCY (all ranks) = 4

END - VMSE Train Read Leveling         Time         276 ms

START - VMSE Train Read
Checkpoint Code: Socket 0, 0xB6, 0x50, 0x0000

END - VMSE Train Read                  Time         4050 ms

START - VMSE Train Level Tx DQS DCC
N3.C1: VmseLevelTxDqsDccExecute: MXB DQS DCC Finished Successfully
N3.C1.S05: VmseAdjustDqsVoc: retrain DQS DCC.
N3.C1.S05:    dcc1_dqs = 0x3F, preampvoc = 0xC
N3.C1: VmseLevelTxDqsDccExecute: MXB DQS DCC Finished Successfully

END - VMSE Train Level Tx DQS DCC      Time         34 ms

START - VMSE Train Write Leveling
N3.C1: VmseWriteLevelFineSetup: Set push to data delay = 6, Global TX DQS delay = 0
N3.C1: VmseRLWLFineSearchAll: Entry
N3.C1: FINE WRITE LEVEL DELAY
N3.C1.S00: TX DQS DELAY = 64
N3.C1.S01: TX DQS DELAY = 67
N3.C1.S02: TX DQS DELAY = 79
N3.C1.S03: TX DQS DELAY = 71
N3.C1.S04: TX DQS DELAY = 99
N3.C1.S05: TX DQS DELAY = 107
N3.C1.S06: TX DQS DELAY = 107
N3.C1.S07: TX DQS DELAY = 109
N3.C1.S08: TX DQS DELAY = 105
N3.C1: VmseWriteLevelCoarseSetup: Set push to data delay = 6, Global TX DQS delay = 0
N3.C1: VmseWriteLevelCoarseExecute
N3.C1: VmseWLCoarseUpdatePD: New push to data delay = 6, New global TxDQS delay = 1
N3.C1: VmseWLCoarseUpdatePD: New push to data delay = 7, New global TxDQS delay = 0
N3.C1: VmseWLCoarseUpdatePD: New push to data delay = 7, New global TxDQS delay = 1
N3.C1: VmseWLCoarseUpdatePD: New push to data delay = 8, New global TxDQS delay = 0
N3.C1: VmseWLCoarseUpdatePD: New push to data delay = 8, New global TxDQS delay = 1
N3.C1: VmseWLCoarseUpdatePD: New push to data delay = 9, New global TxDQS delay = 0
N3.C1.S00: FINAL TX DQS BEFORE TxFIFO CHECK = 32
N3.C1.S01: FINAL TX DQS BEFORE TxFIFO CHECK = 37
N3.C1.S02: FINAL TX DQS BEFORE TxFIFO CHECK = 49
N3.C1.S03: FINAL TX DQS BEFORE TxFIFO CHECK = 40
N3.C1.S04: FINAL TX DQS BEFORE TxFIFO CHECK = 67
N3.C1.S05: FINAL TX DQS BEFORE TxFIFO CHECK = 76
N3.C1.S06: FINAL TX DQS BEFORE TxFIFO CHECK = 76
N3.C1.S07: FINAL TX DQS BEFORE TxFIFO CHECK = 80
N3.C1.S08: FINAL TX DQS BEFORE TxFIFO CHECK = 75
N3.C1: ResolveTxFIFOPtrSeparation: Smallest PI (32) < MIN ALLOWED DELAY (176) 
N3.C1: VmseIncTxFifoPtrSeparation: New push to data delay = 8
N3.C1.S00: VmseIncTxFifoPtrSeparation: pi adjustment = 128, FINAL TX DQS DELAY = 288
N3.C1.S01: VmseIncTxFifoPtrSeparation: pi adjustment = 128, FINAL TX DQS DELAY = 293
N3.C1.S02: VmseIncTxFifoPtrSeparation: pi adjustment = 128, FINAL TX DQS DELAY = 305
N3.C1.S03: VmseIncTxFifoPtrSeparation: pi adjustment = 128, FINAL TX DQS DELAY = 296
N3.C1.S04: VmseIncTxFifoPtrSeparation: pi adjustment = 128, FINAL TX DQS DELAY = 323
N3.C1.S05: VmseIncTxFifoPtrSeparation: pi adjustment = 128, FINAL TX DQS DELAY = 332
N3.C1.S06: VmseIncTxFifoPtrSeparation: pi adjustment = 128, FINAL TX DQS DELAY = 332
N3.C1.S07: VmseIncTxFifoPtrSeparation: pi adjustment = 128, FINAL TX DQS DELAY = 336
N3.C1.S08: VmseIncTxFifoPtrSeparation: pi adjustment = 128, FINAL TX DQS DELAY = 331

END - VMSE Train Write Leveling        Time         260 ms

START - VMSE Train Write
Entry 0 - TrainDcc - DCCStart: 33, VocStart: 11, DCCFinal: 33, VocFinal: 11
Entry 1 - TrainDcc - DCCStart: 44, VocStart: 10, DCCFinal: 44, VocFinal: 10
Entry 2 - TrainDcc - DCCStart: 24, VocStart: 17, DCCFinal: 40, VocFinal: 17
Entry 3 - TrainDcc - DCCStart: 34, VocStart: 17, DCCFinal: 34, VocFinal: 17
Entry 4 - TrainDcc - DCCStart: 25, VocStart: 14, DCCFinal: 25, VocFinal: 18
Entry 5 - TrainDcc - DCCStart: 19, VocStart: 12, DCCFinal: 19, VocFinal: 12
Entry 6 - TrainDcc - DCCStart: 34, VocStart: 7, DCCFinal: 34, VocFinal: 7
Entry 7 - TrainDcc - DCCStart: 11, VocStart: 11, DCCFinal: 11, VocFinal: 11
Entry 8 - TrainDcc - DCCStart: 19, VocStart: 14, DCCFinal: 19, VocFinal: 14

END - VMSE Train Read                  Time         3949 ms

START - VMSE Train Level Tx DQS DCC
N5.C1: VmseLevelTxDqsDccExecute: MXB DQS DCC Finished Successfully

END - VMSE Train Level Tx DQS DCC      Time         12 ms
N3.C1.S00: VmseWriteTraining Final: centerPi = 0x38, PiEw = 0x29, centerVref = 0x42, vrefHeight = 0x26

START - VMSE Train Write Leveling
N3.C1.S01: VmseWriteTraining Final: centerPi = 0x3A, PiEw = 0x27, centerVref = 0x42, vrefHeight = 0x28
N5.C1: VmseWriteLevelFineSetup: Set push to data delay = 6, Global TX DQS delay = 0
N3.C1.S02: VmseWriteTraining Final: centerPi = 0x39, PiEw = 0x25, centerVref = 0x3C, vrefHeight = 0x2C
N5.C1: VmseRLWLFineSearchAll: Entry
N3.C1.S03: VmseWriteTraining Final: centerPi = 0x37, PiEw = 0x28, centerVref = 0x3F, vrefHeight = 0x2A
N5.C1: FINE WRITE LEVEL DELAY
N3.C1.S04: VmseWriteTraining Final: centerPi = 0x3E, PiEw = 0x27, centerVref = 0x3D, vrefHeight = 0x2A
N5.C1.S00: TX DQS DELAY = 64
N3.C1.S05: VmseWriteTraining Final: centerPi = 0x3D, PiEw = 0x27, centerVref = 0x41, vrefHeight = 0x28
N5.C1.S01: TX DQS DELAY = 64
N3.C1.S06: VmseWriteTraining Final: centerPi = 0x3C, PiEw = 0x26, centerVref = 0x3E, vrefHeight = 0x28
N5.C1.S02: TX DQS DELAY = 81
N3.C1.S07: VmseWriteTraining Final: centerPi = 0x3B, PiEw = 0x22, centerVref = 0x43, vrefHeight = 0x26
N5.C1.S03: TX DQS DELAY = 70
N3.C1.S08: VmseWriteTraining Final: centerPi = 0x3A, PiEw = 0x2B, centerVref = 0x42, vrefHeight = 0x2A
N5.C1.S04: TX DQS DELAY = 98
N3.C1.S09: VmseWriteTraining Final: centerPi = 0x3B, PiEw = 0x26, centerVref = 0x3C, vrefHeight = 0x2A
N5.C1.S05: TX DQS DELAY = 103
N3.C1.S10: VmseWriteTraining Final: centerPi = 0x39, PiEw = 0x26, centerVref = 0x3F, vrefHeight = 0x2A
N5.C1.S06: TX DQS DELAY = 107
N3.C1.S11: VmseWriteTraining Final: centerPi = 0x39, PiEw = 0x2C, centerVref = 0x41, vrefHeight = 0x2A
N5.C1.S07: TX DQS DELAY = 110
N3.C1.S12: VmseWriteTraining Final: centerPi = 0x3F, PiEw = 0x25, centerVref = 0x41, vrefHeight = 0x28
N5.C1.S08: TX DQS DELAY = 108
N3.C1.S13: VmseWriteTraining Final: centerPi = 0x3E, PiEw = 0x28, centerVref = 0x3F, vrefHeight = 0x28
N5.C1: VmseWriteLevelCoarseSetup: Set push to data delay = 6, Global TX DQS delay = 0
N3.C1.S14: VmseWriteTraining Final: centerPi = 0x3D, PiEw = 0x23, centerVref = 0x3D, vrefHeight = 0x2C
N5.C1: VmseWriteLevelCoarseExecute
N3.C1.S15: VmseWriteTraining Final: centerPi = 0x3C, PiEw = 0x28, centerVref = 0x45, vrefHeight = 0x28
N5.C1: VmseWLCoarseUpdatePD: New push to data delay = 6, New global TxDQS delay = 1
N3.C1.S16: VmseWriteTraining Final: centerPi = 0x39, PiEw = 0x27, centerVref = 0x44, vrefHeight = 0x2A
N5.C1: VmseWLCoarseUpdatePD: New push to data delay = 7, New global TxDQS delay = 0
N3.C1.S17: VmseWriteTraining Final: centerPi = 0x3C, PiEw = 0x28, centerVref = 0x3C, vrefHeight = 0x2A
N5.C1: VmseWLCoarseUpdatePD: New push to data delay = 7, New global TxDQS delay = 1
N3.C1.S18: VmseWriteTraining Final: centerPi = 0x37, PiEw = 0x25, centerVref = 0x3E, vrefHeight = 0x28
N5.C1: VmseWLCoarseUpdatePD: New push to data delay = 8, New global TxDQS delay = 0
N3.C1.S19: VmseWriteTraining Final: centerPi = 0x38, PiEw = 0x2C, centerVref = 0x42, vrefHeight = 0x2E
N5.C1: VmseWLCoarseUpdatePD: New push to data delay = 8, New global TxDQS delay = 1
N3.C1.S20: VmseWriteTraining Final: centerPi = 0x3D, PiEw = 0x26, centerVref = 0x3A, vrefHeight = 0x2A
N5.C1.S00: FINAL TX DQS BEFORE TxFIFO CHECK = 162

END - VMSE Train Read                  Time         4011 ms
N3.C1.S21: VmseWriteTraining Final: centerPi = 0x3F, PiEw = 0x22, centerVref = 0x3F, vrefHeight = 0x28
N5.C1.S01: FINAL TX DQS BEFORE TxFIFO CHECK = 162

START - VMSE Train Level Tx DQS DCC
N3.C1.S22: VmseWriteTraining Final: centerPi = 0x3C, PiEw = 0x25, centerVref = 0x41, vrefHeight = 0x2C
N5.C1.S02: FINAL TX DQS BEFORE TxFIFO CHECK = 177
N7.C1: VmseLevelTxDqsDccExecute: MXB DQS DCC Finished Successfully
N3.C1.S23: VmseWriteTraining Final: centerPi = 0x3C, PiEw = 0x28, centerVref = 0x3E, vrefHeight = 0x2A
N5.C1.S03: FINAL TX DQS BEFORE TxFIFO CHECK = 167
N7.C1.S04: VmseAdjustDqsVoc: retrain DQS DCC.
N3.C1.S24: VmseWriteTraining Final: centerPi = 0x38, PiEw = 0x28, centerVref = 0x41, vrefHeight = 0x28
N5.C1.S04: FINAL TX DQS BEFORE TxFIFO CHECK = 196
N7.C1.S04:    dcc1_dqs = 0x3F, preampvoc = 0xE
N3.C1.S25: VmseWriteTraining Final: centerPi = 0x3A, PiEw = 0x29, centerVref = 0x3D, vrefHeight = 0x28
N5.C1.S05: FINAL TX DQS BEFORE TxFIFO CHECK = 200
N7.C1.S08: VmseAdjustDqsVoc: retrain DQS DCC.
N3.C1.S26: VmseWriteTraining Final: centerPi = 0x38, PiEw = 0x29, centerVref = 0x41, vrefHeight = 0x2C
N5.C1.S06: FINAL TX DQS BEFORE TxFIFO CHECK = 204
N7.C1.S08:    dcc1_dqs = 0x0, preampvoc = 0xC
N3.C1.S27: VmseWriteTraining Final: centerPi = 0x38, PiEw = 0x2E, centerVref = 0x41, vrefHeight = 0x2C
N5.C1.S07: FINAL TX DQS BEFORE TxFIFO CHECK = 206
N7.C1: VmseLevelTxDqsDccExecute: MXB DQS DCC Finished Successfully
N3.C1.S28: VmseWriteTraining Final: centerPi = 0x3B, PiEw = 0x29, centerVref = 0x42, vrefHeight = 0x28
N5.C1.S08: FINAL TX DQS BEFORE TxFIFO CHECK = 206
N7.C1.S08: VmseAdjustDqsVoc: retrain DQS DCC.
N3.C1.S29: VmseWriteTraining Final: centerPi = 0x3A, PiEw = 0x29, centerVref = 0x42, vrefHeight = 0x26
N5.C1: ResolveTxFIFOPtrSeparation: Smallest PI (162) < MIN ALLOWED DELAY (176) 
N7.C1.S08:    dcc1_dqs = 0x0, preampvoc = 0xB
N3.C1.S30: VmseWriteTraining Final: centerPi = 0x3D, PiEw = 0x29, centerVref = 0x41, vrefHeight = 0x2C
N5.C1: VmseIncTxFifoPtrSeparation: New push to data delay = 7
N7.C1: VmseLevelTxDqsDccExecute: MXB DQS DCC Finished Successfully

END - VMSE Train Read                  Time         4005 ms
N3.C1.S31: VmseWriteTraining Final: centerPi = 0x3D, PiEw = 0x2A, centerVref = 0x40, vrefHeight = 0x2A
N5.C1.S00: VmseIncTxFifoPtrSeparation: pi adjustment = 256, FINAL TX DQS DELAY = 418

END - VMSE Train Level Tx DQS DCC      Time         202 ms

START - VMSE Train Level Tx DQS DCC
N3.C1.S32: VmseWriteTraining Final: centerPi = 0x3F, PiEw = 0x25, centerVref = 0x40, vrefHeight = 0x2A
N5.C1.S01: VmseIncTxFifoPtrSeparation: pi adjustment = 256, FINAL TX DQS DELAY = 418

START - VMSE Train Write Leveling
Checkpoint Code: Socket 0, 0xB6, 0x52, 0x0000
N3.C1.S33: VmseWriteTraining Final: centerPi = 0x3B, PiEw = 0x29, centerVref = 0x3D, vrefHeight = 0x2A
N5.C1.S02: VmseIncTxFifoPtrSeparation: pi adjustment = 256, FINAL TX DQS DELAY = 433
N7.C1: VmseWriteLevelFineSetup: Set push to data delay = 6, Global TX DQS delay = 0
N1.C1: VmseLevelTxDqsDccExecute: MXB DQS DCC Finished Successfully
N3.C1.S34: VmseWriteTraining Final: centerPi = 0x3B, PiEw = 0x28, centerVref = 0x3E, vrefHeight = 0x2C
N5.C1.S03: VmseIncTxFifoPtrSeparation: pi adjustment = 256, FINAL TX DQS DELAY = 423
N7.C1: VmseRLWLFineSearchAll: Entry
N1.C1.S08: VmseAdjustDqsVoc: retrain DQS DCC.
N3.C1.S35: VmseWriteTraining Final: centerPi = 0x39, PiEw = 0x2C, centerVref = 0x40, vrefHeight = 0x2E
N5.C1.S04: VmseIncTxFifoPtrSeparation: pi adjustment = 256, FINAL TX DQS DELAY = 452
N7.C1: FINE WRITE LEVEL DELAY
N1.C1.S08:    dcc1_dqs = 0x0, preampvoc = 0xC
N3.C1.S36: VmseWriteTraining Final: centerPi = 0x3F, PiEw = 0x28, centerVref = 0x3E, vrefHeight = 0x2A
N5.C1.S05: VmseIncTxFifoPtrSeparation: pi adjustment = 256, FINAL TX DQS DELAY = 456
N7.C1.S00: TX DQS DELAY = 138
N1.C1: VmseLevelTxDqsDccExecute: MXB DQS DCC Finished Successfully
N3.C1.S37: VmseWriteTraining Final: centerPi = 0x3E, PiEw = 0x27, centerVref = 0x3E, vrefHeight = 0x2A
N5.C1.S06: VmseIncTxFifoPtrSeparation: pi adjustment = 256, FINAL TX DQS DELAY = 460
N7.C1.S01: TX DQS DELAY = 138

END - VMSE Train Level Tx DQS DCC      Time         152 ms
N3.C1.S38: VmseWriteTraining Final: centerPi = 0x3D, PiEw = 0x28, centerVref = 0x3C, vrefHeight = 0x2A
N5.C1.S07: VmseIncTxFifoPtrSeparation: pi adjustment = 256, FINAL TX DQS DELAY = 462
N7.C1.S02: TX DQS DELAY = 152

START - VMSE Train Write Leveling
N3.C1.S39: VmseWriteTraining Final: centerPi = 0x3E, PiEw = 0x26, centerVref = 0x3F, vrefHeight = 0x28
N5.C1.S08: VmseIncTxFifoPtrSeparation: pi adjustment = 256, FINAL TX DQS DELAY = 462
N7.C1.S03: TX DQS DELAY = 144
Checkpoint Code: Socket 0, 0xB6, 0x54, 0x0000
N3.C1.S40: VmseWriteTraining Final: centerPi = 0x3A, PiEw = 0x29, centerVref = 0x3F, vrefHeight = 0x24

END - VMSE Train Write Leveling        Time         824 ms
N7.C1.S04: TX DQS DELAY = 108
N1.C1: VmseWriteLevelFineSetup: Set push to data delay = 6, Global TX DQS delay = 0
N3.C1.S41: VmseWriteTraining Final: centerPi = 0x3C, PiEw = 0x24, centerVref = 0x3D, vrefHeight = 0x26

START - VMSE Train Write
N7.C1.S05: TX DQS DELAY = 50
N1.C1: VmseRLWLFineSearchAll: Entry
N3.C1.S42: VmseWriteTraining Final: centerPi = 0x37, PiEw = 0x20, centerVref = 0x3F, vrefHeight = 0x24
N7.C1.S06: TX DQS DELAY = 119
N1.C1: FINE WRITE LEVEL DELAY
N3.C1.S43: VmseWriteTraining Final: centerPi = 0x38, PiEw = 0x22, centerVref = 0x43, vrefHeight = 0x28
N7.C1.S07: TX DQS DELAY = 54
N1.C1.S00: TX DQS DELAY = 62
N3.C1.S44: VmseWriteTraining Final: centerPi = 0x3F, PiEw = 0x24, centerVref = 0x3F, vrefHeight = 0x28
N7.C1.S08: TX DQS DELAY = 50
N1.C1.S01: TX DQS DELAY = 62
N3.C1.S45: VmseWriteTraining Final: centerPi = 0x3B, PiEw = 0x1E, centerVref = 0x40, vrefHeight = 0x24
N7.C1: VmseWriteLevelCoarseSetup: Set push to data delay = 6, Global TX DQS delay = 0
N1.C1.S02: TX DQS DELAY = 77
N3.C1.S46: VmseWriteTraining Final: centerPi = 0x3D, PiEw = 0x23, centerVref = 0x3E, vrefHeight = 0x26
N7.C1: VmseWriteLevelCoarseExecute
N1.C1.S03: TX DQS DELAY = 67
N3.C1.S47: VmseWriteTraining Final: centerPi = 0x3E, PiEw = 0x27, centerVref = 0x3F, vrefHeight = 0x28
N7.C1: VmseWLCoarseUpdatePD: New push to data delay = 6, New global TxDQS delay = 1
N1.C1.S04: TX DQS DELAY = 93
N3.C1.S48: VmseWriteTraining Final: centerPi = 0x3B, PiEw = 0x28, centerVref = 0x3E, vrefHeight = 0x26
N7.C1: VmseWLCoarseUpdatePD: New push to data delay = 7, New global TxDQS delay = 0
N1.C1.S05: TX DQS DELAY = 102
N3.C1.S49: VmseWriteTraining Final: centerPi = 0x3D, PiEw = 0x28, centerVref = 0x3E, vrefHeight = 0x2C
N7.C1: VmseWLCoarseUpdatePD: New push to data delay = 7, New global TxDQS delay = 1
N1.C1.S06: TX DQS DELAY = 105
N3.C1.S50: VmseWriteTraining Final: centerPi = 0x3C, PiEw = 0x27, centerVref = 0x3F, vrefHeight = 0x2C
N7.C1: VmseWLCoarseUpdatePD: New push to data delay = 8, New global TxDQS delay = 0
N1.C1.S07: TX DQS DELAY = 105
N3.C1.S51: VmseWriteTraining Final: centerPi = 0x39, PiEw = 0x26, centerVref = 0x3F, vrefHeight = 0x2E
N7.C1: VmseWLCoarseUpdatePD: New push to data delay = 8, New global TxDQS delay = 1
N1.C1.S08: TX DQS DELAY = 99
N3.C1.S52: VmseWriteTraining Final: centerPi = 0x40, PiEw = 0x25, centerVref = 0x41, vrefHeight = 0x2C
N7.C1: VmseWLCoarseUpdatePD: New push to data delay = 9, New global TxDQS delay = 0
N1.C1: VmseWriteLevelCoarseSetup: Set push to data delay = 6, Global TX DQS delay = 0
N3.C1.S53: VmseWriteTraining Final: centerPi = 0x3D, PiEw = 0x24, centerVref = 0x3F, vrefHeight = 0x24
N7.C1: VmseWLCoarseUpdatePD: New push to data delay = 9, New global TxDQS delay = 1
N1.C1: VmseWriteLevelCoarseExecute
N3.C1.S54: VmseWriteTraining Final: centerPi = 0x3E, PiEw = 0x26, centerVref = 0x3C, vrefHeight = 0x2A
N7.C1.S00: FINAL TX DQS BEFORE TxFIFO CHECK = 108
Checkpoint Code: Socket 0, 0xB6, 0xAC, 0x0000
N3.C1.S55: VmseWriteTraining Final: centerPi = 0x3E, PiEw = 0x27, centerVref = 0x40, vrefHeight = 0x28
N7.C1.S01: FINAL TX DQS BEFORE TxFIFO CHECK = 108
N1.C1: VmseWLCoarseUpdatePD: New push to data delay = 6, New global TxDQS delay = 1
N3.C1.S56: VmseWriteTraining Final: centerPi = 0x3C, PiEw = 0x26, centerVref = 0x44, vrefHeight = 0x26
N7.C1.S02: FINAL TX DQS BEFORE TxFIFO CHECK = 119
N1.C1: VmseWLCoarseUpdatePD: New push to data delay = 7, New global TxDQS delay = 0
N3.C1.S57: VmseWriteTraining Final: centerPi = 0x40, PiEw = 0x24, centerVref = 0x3D, vrefHeight = 0x2C
N7.C1.S03: FINAL TX DQS BEFORE TxFIFO CHECK = 114
N1.C1: VmseWLCoarseUpdatePD: New push to data delay = 7, New global TxDQS delay = 1
N3.C1.S58: VmseWriteTraining Final: centerPi = 0x3E, PiEw = 0x28, centerVref = 0x41, vrefHeight = 0x2A
N7.C1.S04: FINAL TX DQS BEFORE TxFIFO CHECK = 208
N1.C1: VmseWLCoarseUpdatePD: New push to data delay = 8, New global TxDQS delay = 0
N3.C1.S59: VmseWriteTraining Final: centerPi = 0x3D, PiEw = 0x2D, centerVref = 0x41, vrefHeight = 0x2A
N7.C1.S05: FINAL TX DQS BEFORE TxFIFO CHECK = 148
N1.C1: VmseWLCoarseUpdatePD: New push to data delay = 8, New global TxDQS delay = 1
N3.C1.S60: VmseWriteTraining Final: centerPi = 0x43, PiEw = 0x25, centerVref = 0x39, vrefHeight = 0x28
N7.C1.S06: FINAL TX DQS BEFORE TxFIFO CHECK = 216
N1.C1: VmseWLCoarseUpdatePD: New push to data delay = 9, New global TxDQS delay = 0
N3.C1.S61: VmseWriteTraining Final: centerPi = 0x43, PiEw = 0x26, centerVref = 0x3E, vrefHeight = 0x26
N7.C1.S07: FINAL TX DQS BEFORE TxFIFO CHECK = 150
N1.C1.S00: FINAL TX DQS BEFORE TxFIFO CHECK = 32
N3.C1.S62: VmseWriteTraining Final: centerPi = 0x42, PiEw = 0x23, centerVref = 0x3D, vrefHeight = 0x2A
N7.C1.S08: FINAL TX DQS BEFORE TxFIFO CHECK = 149
N1.C1.S01: FINAL TX DQS BEFORE TxFIFO CHECK = 32
N3.C1.S63: VmseWriteTraining Final: centerPi = 0x41, PiEw = 0x22, centerVref = 0x40, vrefHeight = 0x2A
N7.C1: ResolveTxFIFOPtrSeparation: Smallest PI (108) < MIN ALLOWED DELAY (176) 
N1.C1.S02: FINAL TX DQS BEFORE TxFIFO CHECK = 46
N3.C1.S64: VmseWriteTraining Final: centerPi = 0x38, PiEw = 0x28, centerVref = 0x44, vrefHeight = 0x28
N7.C1: VmseIncTxFifoPtrSeparation: New push to data delay = 8
N1.C1.S03: FINAL TX DQS BEFORE TxFIFO CHECK = 37
N3.C1.S65: VmseWriteTraining Final: centerPi = 0x39, PiEw = 0x28, centerVref = 0x3F, vrefHeight = 0x2C
N7.C1.S00: VmseIncTxFifoPtrSeparation: pi adjustment = 256, FINAL TX DQS DELAY = 364
N1.C1.S04: FINAL TX DQS BEFORE TxFIFO CHECK = 62
N3.C1.S66: VmseWriteTraining Final: centerPi = 0x3A, PiEw = 0x2A, centerVref = 0x41, vrefHeight = 0x2C
N7.C1.S01: VmseIncTxFifoPtrSeparation: pi adjustment = 256, FINAL TX DQS DELAY = 364
N1.C1.S05: FINAL TX DQS BEFORE TxFIFO CHECK = 69
N3.C1.S67: VmseWriteTraining Final: centerPi = 0x39, PiEw = 0x28, centerVref = 0x3E, vrefHeight = 0x2E
N7.C1.S02: VmseIncTxFifoPtrSeparation: pi adjustment = 256, FINAL TX DQS DELAY = 375
N1.C1.S06: FINAL TX DQS BEFORE TxFIFO CHECK = 75
N3.C1.S68: VmseWriteTraining Final: centerPi = 0x3E, PiEw = 0x23, centerVref = 0x40, vrefHeight = 0x26
N7.C1.S03: VmseIncTxFifoPtrSeparation: pi adjustment = 256, FINAL TX DQS DELAY = 370
N1.C1.S07: FINAL TX DQS BEFORE TxFIFO CHECK = 75
N3.C1.S69: VmseWriteTraining Final: centerPi = 0x3C, PiEw = 0x24, centerVref = 0x40, vrefHeight = 0x28
N7.C1.S04: VmseIncTxFifoPtrSeparation: pi adjustment = 256, FINAL TX DQS DELAY = 464
N1.C1.S08: FINAL TX DQS BEFORE TxFIFO CHECK = 69
N3.C1.S70: VmseWriteTraining Final: centerPi = 0x3B, PiEw = 0x21, centerVref = 0x3D, vrefHeight = 0x28
N7.C1.S05: VmseIncTxFifoPtrSeparation: pi adjustment = 256, FINAL TX DQS DELAY = 404
N1.C1: ResolveTxFIFOPtrSeparation: Smallest PI (32) < MIN ALLOWED DELAY (176) 
N3.C1.S71: VmseWriteTraining Final: centerPi = 0x3C, PiEw = 0x25, centerVref = 0x3E, vrefHeight = 0x2A
N7.C1.S06: VmseIncTxFifoPtrSeparation: pi adjustment = 256, FINAL TX DQS DELAY = 472
N1.C1: VmseIncTxFifoPtrSeparation: New push to data delay = 8

END - VMSE Train Write                 Time         2947 ms
N7.C1.S07: VmseIncTxFifoPtrSeparation: pi adjustment = 256, FINAL TX DQS DELAY = 406
N1.C1.S00: VmseIncTxFifoPtrSeparation: pi adjustment = 128, FINAL TX DQS DELAY = 288
N3: 
Total VMSE trainings latency = 15885 ms
N7.C1.S08: VmseIncTxFifoPtrSeparation: pi adjustment = 256, FINAL TX DQS DELAY = 405
N1.C1.S01: VmseIncTxFifoPtrSeparation: pi adjustment = 128, FINAL TX DQS DELAY = 288
N2: PostVmseTraining

END - VMSE Train Write Leveling        Time         1010 ms
N1.C1.S02: VmseIncTxFifoPtrSeparation: pi adjustment = 128, FINAL TX DQS DELAY = 302
N2.C0: PostVmseTraining

START - VMSE Train Write
N1.C1.S03: VmseIncTxFifoPtrSeparation: pi adjustment = 128, FINAL TX DQS DELAY = 293
N2.C0: PostVMSE Training VMSE Health Check Passed
N1.C1.S04: VmseIncTxFifoPtrSeparation: pi adjustment = 128, FINAL TX DQS DELAY = 318
N2.C1: PostVmseTraining
N1.C1.S05: VmseIncTxFifoPtrSeparation: pi adjustment = 128, FINAL TX DQS DELAY = 325
N2.C2: PostVMSE Training VMSE Health Check Passed
N1.C1.S06: VmseIncTxFifoPtrSeparation: pi adjustment = 128, FINAL TX DQS DELAY = 331
N2: PreDdrTraining
N1.C1.S07: VmseIncTxFifoPtrSeparation: pi adjustment = 128, FINAL TX DQS DELAY = 331
N2: PreDdrTraining[QCRM=OFF]
N1.C1.S08: VmseIncTxFifoPtrSeparation: pi adjustment = 128, FINAL TX DQS DELAY = 325
N2.C0.D0: CheckRankPopLocal: dimmPresent: 1, numRanks = 2

END - VMSE Train Write Leveling        Time         930 ms
N2.C0.D0.R0: CheckRankPopLocal: mapOut: 0, enabled = 1

START - VMSE Train Write
N2.C0.D0.R1: CheckRankPopLocal: mapOut: 0, enabled = 1
Checkpoint Code: Socket 0, 0xB6, 0x56, 0x0000
N2.C0.D1: CheckRankPopLocal: dimmPresent: 1, numRanks = 2
N2.C0.D1.R0: CheckRankPopLocal: mapOut: 0, enabled = 1
N2.C0.D1.R1: CheckRankPopLocal: mapOut: 0, enabled = 1
N2.C0.D2: CheckRankPopLocal: dimmPresent: 0, numRanks = 0
N2.C0.D0: CheckRankPopLocal: amap: 0x00000000
N2.C0.D1: CheckRankPopLocal: amap: 0x00000000
N2.C0.D2: CheckRankPopLocal: amap: 0x00000000
N2.C1.D0: CheckRankPopLocal: dimmPresent: 1, numRanks = 2
N2.C1.D0.R0: CheckRankPopLocal: mapOut: 0, enabled = 1
N2.C1.D0.R1: CheckRankPopLocal: mapOut: 0, enabled = 1
N2.C1.D1: CheckRankPopLocal: dimmPresent: 1, numRanks = 2
N2.C1.D1.R0: CheckRankPopLocal: mapOut: 0, enabled = 1
N2.C1.D1.R1: CheckRankPopLocal: mapOut: 0, enabled = 1
N2.C1.D2: CheckRankPopLocal: dimmPresent: 0, numRanks = 0
N2.C1.D0: CheckRankPopLocal: amap: 0x00000000
N2.C1.D1: CheckRankPopLocal: amap: 0x00000000
N2.C1.D2: CheckRankPopLocal: amap: 0x00000000
N2.C2.D0: CheckRankPopLocal: dimmPresent: 1, numRanks = 2
N2.C2.D0.R0: CheckRankPopLocal: mapOut: 0, enabled = 1
N2.C2.D0.R1: CheckRankPopLocal: mapOut: 0, enabled = 1
Entry 0 - TrainDcc - DCCStart: 23, VocStart: 14, DCCFinal: 23, VocFinal: 14
N2.C2.D1: CheckRankPopLocal: dimmPresent: 1, numRanks = 2
Entry 1 - TrainDcc - DCCStart: 23, VocStart: 12, DCCFinal: 23, VocFinal: 12
N2.C2.D1.R0: CheckRankPopLocal: mapOut: 0, enabled = 1
Entry 2 - TrainDcc - DCCStart: 26, VocStart: 10, DCCFinal: 63, VocFinal: 11
N2.C2.D1.R1: CheckRankPopLocal: mapOut: 0, enabled = 1
Entry 3 - TrainDcc - DCCStart: 16, VocStart: 12, DCCFinal: 16, VocFinal: 12
N2.C2.D2: CheckRankPopLocal: dimmPresent: 0, numRanks = 0
Entry 4 - TrainDcc - DCCStart: 39, VocStart: 11, DCCFinal: 39, VocFinal: 15
N2.C2.D0: CheckRankPopLocal: amap: 0x00000000
Entry 5 - TrainDcc - DCCStart: 33, VocStart: 10, DCCFinal: 33, VocFinal: 10
N2.C2.D1: CheckRankPopLocal: amap: 0x00000000
Entry 6 - TrainDcc - DCCStart: 32, VocStart: 13, DCCFinal: 32, VocFinal: 13
N2.C2.D2: CheckRankPopLocal: amap: 0x00000000
Entry 7 - TrainDcc - DCCStart: 19, VocStart: 14, DCCFinal: 19, VocFinal: 14
N2.C3.D0: CheckRankPopLocal: dimmPresent: 1, numRanks = 2
Entry 8 - TrainDcc - DCCStart: 33, VocStart: 17, DCCFinal: 33, VocFinal: 17
N2.C3.D0.R0: CheckRankPopLocal: mapOut: 0, enabled = 1
N2.C3.D0.R1: CheckRankPopLocal: mapOut: 0, enabled = 1
N2.C3.D1: CheckRankPopLocal: dimmPresent: 1, numRanks = 2
N2.C3.D1.R0: CheckRankPopLocal: mapOut: 0, enabled = 1
N2.C3.D1.R1: CheckRankPopLocal: mapOut: 0, enabled = 1
N2.C3.D2: CheckRankPopLocal: dimmPresent: 0, numRanks = 0
N2.C3.D0: CheckRankPopLocal: amap: 0x00000000
N2.C3.D1: CheckRankPopLocal: amap: 0x00000000
N2.C3.D2: CheckRankPopLocal: amap: 0x00000000
N2.C0: JCK cmd timing = 3N
N2.C0: RdCmd2DataValidLatency = 20, (dlyFrmS = 15, clEff = 10, earlyCas = 0, selNTiming = 2)
N2.C0: CLK0_CFG: 0x000FFF30
N2.C0: DDR_RANKCTL: 0x000FEA40
N2.C0: MCODT = 0 ( 50 ohms)
N2.C0.D0.R0: Rtt_wr = 120, Rtt_nom = 20
N5.C1.S60: ParamSweep: EdgeLeft = 0x39 EdgeRight = 0x3F MinEyeSize not reached 
N2.C0.D0.R1: Rtt_wr = 120, Rtt_nom = 0
N2.C0.D1.R0: Rtt_wr = 120, Rtt_nom = 20
N2.C0.D1.R1: Rtt_wr = 120, Rtt_nom = 0
N2.C0: ODTRDCTL00 = 0x01000104
N2.C0: ODTRDCTL01 = 0x00000001
N2.C0: ODTWRCTL00 = 0x05000185
N2.C0: ODTWRCTL01 = 0x00000009
N2.C1: RdCmd2DataValidLatency = 20, (dlyFrmS = 15, clEff = 10, earlyCas = 0, selNTiming = 2)
N2.C1: CLK0_CFG: 0x000FF330
N2.C1: DDR_RANKCTL: 0x000FEA40
N2.C1: MCODT = 0 ( 50 ohms)
N2.C1.D0.R0: Rtt_wr = 120, Rtt_nom = 20
N2.C1.D0.R1: Rtt_wr = 120, Rtt_nom = 0
N2.C1.D1.R0: Rtt_wr = 120, Rtt_nom = 20
N2.C1.D1.R1: Rtt_wr = 120, Rtt_nom = 0
N2.C1: ODTRDCTL00 = 0x01000104
N2.C1: ODTRDCTL01 = 0x00000001
N2.C1: ODTWRCTL00 = 0x05000185
N2.C1: ODTWRCTL01 = 0x00000009
N2.C2: JCK cmd timing = 3N
N2.C2: RdCmd2DataValidLatency = 20, (dlyFrmS = 15, clEff = 10, earlyCas = 0, selNTiming = 2)
N2.C2: CLK0_CFG: 0x000FFF30
N2.C2: DDR_RANKCTL: 0x000FEA40
N2.C2: MCODT = 0 ( 50 ohms)
N2.C2.D0.R0: Rtt_wr = 120, Rtt_nom = 20
N2.C2.D0.R1: Rtt_wr = 120, Rtt_nom = 0
N2.C2.D1.R0: Rtt_wr = 120, Rtt_nom = 20
N2.C2.D1.R1: Rtt_wr = 120, Rtt_nom = 0
N2.C2: ODTRDCTL00 = 0x01000104
N2.C2: ODTRDCTL01 = 0x00000001
N2.C2: ODTWRCTL00 = 0x05000185
N2.C2: ODTWRCTL01 = 0x00000009
N2.C3: RdCmd2DataValidLatency = 20, (dlyFrmS = 15, clEff = 10, earlyCas = 0, selNTiming = 2)
N2.C3: CLK0_CFG: 0x000FF330
N2.C3: DDR_RANKCTL: 0x000FEA40
N2.C3: MCODT = 0 ( 50 ohms)
N2.C3.D0.R0: Rtt_wr = 120, Rtt_nom = 20
N2.C3.D0.R1: Rtt_wr = 120, Rtt_nom = 0
N2.C3.D1.R0: Rtt_wr = 120, Rtt_nom = 20
N2.C3.D1.R1: Rtt_wr = 120, Rtt_nom = 0
N2.C3: ODTRDCTL00 = 0x01000104
N2.C3: ODTRDCTL01 = 0x00000001
N2.C3: ODTWRCTL00 = 0x05000185
N2.C3: ODTWRCTL01 = 0x00000009
N5.C1.S00: VmseWriteTraining Final: centerPi = 0x38, PiEw = 0x28, centerVref = 0x48, vrefHeight = 0x26
N2.C0.D0: PreDdrTraining: Program dimmmtr 0xC502D
N5.C1.S01: VmseWriteTraining Final: centerPi = 0x3C, PiEw = 0x25, centerVref = 0x3B, vrefHeight = 0x28
N2.C0.D1: PreDdrTraining: Program dimmmtr 0xC502D
N5.C1.S02: VmseWriteTraining Final: centerPi = 0x37, PiEw = 0x23, centerVref = 0x3E, vrefHeight = 0x24
N2.C1.D0: PreDdrTraining: Program dimmmtr 0xC502D
N5.C1.S03: VmseWriteTraining Final: centerPi = 0x38, PiEw = 0x2A, centerVref = 0x3F, vrefHeight = 0x28
N2.C1.D1: PreDdrTraining: Program dimmmtr 0xC502D
N5.C1.S04: VmseWriteTraining Final: centerPi = 0x3E, PiEw = 0x27, centerVref = 0x3E, vrefHeight = 0x26
N2.C2.D0: PreDdrTraining: Program dimmmtr 0xC502D
N5.C1.S05: VmseWriteTraining Final: centerPi = 0x3D, PiEw = 0x26, centerVref = 0x43, vrefHeight = 0x26
N2.C2.D1: PreDdrTraining: Program dimmmtr 0xC502D
N5.C1.S06: VmseWriteTraining Final: centerPi = 0x3B, PiEw = 0x24, centerVref = 0x40, vrefHeight = 0x26
N2.C3.D0: PreDdrTraining: Program dimmmtr 0xC502D
N5.C1.S07: VmseWriteTraining Final: centerPi = 0x3C, PiEw = 0x27, centerVref = 0x3D, vrefHeight = 0x24
N2.C3.D1: PreDdrTraining: Program dimmmtr 0xC502D
N5.C1.S08: VmseWriteTraining Final: centerPi = 0x3A, PiEw = 0x24, centerVref = 0x45, vrefHeight = 0x24
N2: InitializeDdrioForUse
N5.C1.S09: VmseWriteTraining Final: centerPi = 0x3B, PiEw = 0x26, centerVref = 0x3E, vrefHeight = 0x26
N2: SetupJckForBL: setting BL to 8
N5.C1.S10: VmseWriteTraining Final: centerPi = 0x3A, PiEw = 0x27, centerVref = 0x3E, vrefHeight = 0x28
N2.C0: ODTTIMCTL (INIT RELAX) rdwidth = 10 rddly = 0 wrwidth = 8 wrdly = 0
N5.C1.S11: VmseWriteTraining Final: centerPi = 0x36, PiEw = 0x2A, centerVref = 0x3F, vrefHeight = 0x28
N2.C1: ODTTIMCTL (INIT RELAX) rdwidth = 10 rddly = 0 wrwidth = 8 wrdly = 0
N5.C1.S12: VmseWriteTraining Final: centerPi = 0x3E, PiEw = 0x24, centerVref = 0x3D, vrefHeight = 0x24
N2.C2: ODTTIMCTL (INIT RELAX) rdwidth = 10 rddly = 0 wrwidth = 8 wrdly = 0
N5.C1.S13: VmseWriteTraining Final: centerPi = 0x3D, PiEw = 0x28, centerVref = 0x3F, vrefHeight = 0x24
N2.C3: ODTTIMCTL (INIT RELAX) rdwidth = 10 rddly = 0 wrwidth = 8 wrdly = 0
N5.C1.S14: VmseWriteTraining Final: centerPi = 0x3E, PiEw = 0x25, centerVref = 0x3D, vrefHeight = 0x28
N2: JckDdrTraining
N5.C1.S15: VmseWriteTraining Final: centerPi = 0x3E, PiEw = 0x25, centerVref = 0x3D, vrefHeight = 0x26
N2: InitializeDdrioForTraining: QCRM Disabled
N5.C1.S16: VmseWriteTraining Final: centerPi = 0x39, PiEw = 0x26, centerVref = 0x42, vrefHeight = 0x26
N2.C0: InitializeDdrioForTraining: cleff = 10
N5.C1.S17: VmseWriteTraining Final: centerPi = 0x38, PiEw = 0x28, centerVref = 0x3D, vrefHeight = 0x28
N2.C0: InitializeDdrioForTraining: cwleff = 8
N5.C1.S18: VmseWriteTraining Final: centerPi = 0x37, PiEw = 0x27, centerVref = 0x41, vrefHeight = 0x24
N2.C0: InitializeDdrioForTraining: initial ddrInitIndexRx = 4 ddrInitIndexTx = 2
N5.C1.S19: VmseWriteTraining Final: centerPi = 0x36, PiEw = 0x29, centerVref = 0x3E, vrefHeight = 0x28
N2.C0: InitializeDdrioForTraining: initial RdCmd2RcvEnLatency = 5
N5.C1.S20: VmseWriteTraining Final: centerPi = 0x3C, PiEw = 0x27, centerVref = 0x3F, vrefHeight = 0x26
N2.C0: InitializeDdrioForTraining: initial RdPtrOffsetRcvEn = 4
N5.C1.S21: VmseWriteTraining Final: centerPi = 0x3C, PiEw = 0x25, centerVref = 0x3D, vrefHeight = 0x24
N2.C0: InitializeDdrioForTraining: initial rkrdptroffsetrcvenb = 6
N5.C1.S22: VmseWriteTraining Final: centerPi = 0x3A, PiEw = 0x23, centerVref = 0x3D, vrefHeight = 0x24
N2.C0: InitializeDdrioForTraining: initial rkrdptroffsetdrvenrcvenb = 5
N5.C1.S23: VmseWriteTraining Final: centerPi = 0x3A, PiEw = 0x28, centerVref = 0x41, vrefHeight = 0x24
N2.C0: InitializeDdrioForTraining: initial WrCmd2DqsStartLatency = 4
N5.C1.S24: VmseWriteTraining Final: centerPi = 0x3C, PiEw = 0x25, centerVref = 0x40, vrefHeight = 0x26
N2.C0: InitializeDdrioForTraining: initial RdPtrOffsetDqs = 10
N5.C1.S25: VmseWriteTraining Final: centerPi = 0x3A, PiEw = 0x29, centerVref = 0x40, vrefHeight = 0x26
N2.C0: InitializeDdrioForTraining: initial RdCmd2RcvEnLatency = 5
N5.C1.S26: VmseWriteTraining Final: centerPi = 0x39, PiEw = 0x24, centerVref = 0x40, vrefHeight = 0x28
N2.C0: InitializeDdrioForTraining: initial WrCmd2DqsStartLatency = 4
N5.C1.S27: VmseWriteTraining Final: centerPi = 0x3A, PiEw = 0x2A, centerVref = 0x3F, vrefHeight = 0x2C
Entry 0 - TrainDcc - DCCStart: 19, VocStart: 13, DCCFinal: 19, VocFinal: 13
N2.C0: InitializeDdrioForTraining: initial RdPtrOffsetRcvEn = 4
N5.C1.S28: VmseWriteTraining Final: centerPi = 0x3D, PiEw = 0x27, centerVref = 0x3A, vrefHeight = 0x26
Entry 1 - TrainDcc - DCCStart: 8, VocStart: 14, DCCFinal: 8, VocFinal: 14
N2.C0: InitializeDdrioForTraining: initial RdPtrOffsetDqs = 6
N5.C1.S29: VmseWriteTraining Final: centerPi = 0x3E, PiEw = 0x27, centerVref = 0x3E, vrefHeight = 0x22
Entry 2 - TrainDcc - DCCStart: 44, VocStart: 13, DCCFinal: 36, VocFinal: 13
N2.C0: InitializeDdrioForTraining: initial RdPtrOffsetDq = 5
N5.C1.S30: VmseWriteTraining Final: centerPi = 0x3F, PiEw = 0x27, centerVref = 0x3D, vrefHeight = 0x28
Entry 3 - TrainDcc - DCCStart: 39, VocStart: 13, DCCFinal: 39, VocFinal: 13
N2.C1: InitializeDdrioForTraining: cleff = 10
N5.C1.S31: VmseWriteTraining Final: centerPi = 0x3F, PiEw = 0x2A, centerVref = 0x3B, vrefHeight = 0x28
Entry 4 - TrainDcc - DCCStart: 32, VocStart: 14, DCCFinal: 32, VocFinal: 14
N2.C1: InitializeDdrioForTraining: cwleff = 8
N5.C1.S32: VmseWriteTraining Final: centerPi = 0x3B, PiEw = 0x28, centerVref = 0x43, vrefHeight = 0x26
Entry 5 - TrainDcc - DCCStart: 26, VocStart: 12, DCCFinal: 26, VocFinal: 12
N2.C1: InitializeDdrioForTraining: initial ddrInitIndexRx = 4 ddrInitIndexTx = 2
N5.C1.S33: VmseWriteTraining Final: centerPi = 0x3B, PiEw = 0x29, centerVref = 0x3E, vrefHeight = 0x26
Entry 6 - TrainDcc - DCCStart: 59, VocStart: 13, DCCFinal: 59, VocFinal: 13
Entry 0 - TrainDcc - DCCStart: 37, VocStart: 13, DCCFinal: 53, VocFinal: 13
N2.C1: InitializeDdrioForTraining: initial RdCmd2RcvEnLatency = 5
N5.C1.S34: VmseWriteTraining Final: centerPi = 0x39, PiEw = 0x25, centerVref = 0x3E, vrefHeight = 0x2A
Entry 7 - TrainDcc - DCCStart: 17, VocStart: 9, DCCFinal: 17, VocFinal: 9
Entry 1 - TrainDcc - DCCStart: 10, VocStart: 11, DCCFinal: 10, VocFinal: 11
N2.C1: InitializeDdrioForTraining: initial RdPtrOffsetRcvEn = 4
N5.C1.S35: VmseWriteTraining Final: centerPi = 0x37, PiEw = 0x29, centerVref = 0x3C, vrefHeight = 0x2C
Entry 8 - TrainDcc - DCCStart: 10, VocStart: 11, DCCFinal: 10, VocFinal: 11
Entry 2 - TrainDcc - DCCStart: 31, VocStart: 12, DCCFinal: 47, VocFinal: 12
N2.C1: InitializeDdrioForTraining: initial rkrdptroffsetrcvenb = 6
N5.C1.S36: VmseWriteTraining Final: centerPi = 0x3E, PiEw = 0x27, centerVref = 0x3B, vrefHeight = 0x28
Entry 3 - TrainDcc - DCCStart: 16, VocStart: 13, DCCFinal: 16, VocFinal: 13
N2.C1: InitializeDdrioForTraining: initial rkrdptroffsetdrvenrcvenb = 5
N5.C1.S37: VmseWriteTraining Final: centerPi = 0x3C, PiEw = 0x24, centerVref = 0x3F, vrefHeight = 0x24
Entry 4 - TrainDcc - DCCStart: 27, VocStart: 11, DCCFinal: 27, VocFinal: 15
N2.C1: InitializeDdrioForTraining: initial WrCmd2DqsStartLatency = 4
N5.C1.S38: VmseWriteTraining Final: centerPi = 0x3D, PiEw = 0x25, centerVref = 0x43, vrefHeight = 0x28
Entry 5 - TrainDcc - DCCStart: 31, VocStart: 16, DCCFinal: 31, VocFinal: 16
N2.C1: InitializeDdrioForTraining: initial RdPtrOffsetDqs = 10
N5.C1.S39: VmseWriteTraining Final: centerPi = 0x3B, PiEw = 0x26, centerVref = 0x3E, vrefHeight = 0x26
Entry 6 - TrainDcc - DCCStart: 19, VocStart: 12, DCCFinal: 19, VocFinal: 20
N2.C1: InitializeDdrioForTraining: initial RdCmd2RcvEnLatency = 5
N5.C1.S40: VmseWriteTraining Final: centerPi = 0x39, PiEw = 0x28, centerVref = 0x41, vrefHeight = 0x24
Entry 7 - TrainDcc - DCCStart: 14, VocStart: 11, DCCFinal: 14, VocFinal: 11
N2.C1: InitializeDdrioForTraining: initial WrCmd2DqsStartLatency = 4
N5.C1.S41: VmseWriteTraining Final: centerPi = 0x39, PiEw = 0x24, centerVref = 0x3C, vrefHeight = 0x22
Entry 8 - TrainDcc - DCCStart: 10, VocStart: 12, DCCFinal: 10, VocFinal: 12
N2.C1: InitializeDdrioForTraining: initial RdPtrOffsetRcvEn = 4
N5.C1.S42: VmseWriteTraining Final: centerPi = 0x35, PiEw = 0x22, centerVref = 0x3D, vrefHeight = 0x20
N2.C1: InitializeDdrioForTraining: initial RdPtrOffsetDqs = 6
N5.C1.S43: VmseWriteTraining Final: centerPi = 0x36, PiEw = 0x22, centerVref = 0x3B, vrefHeight = 0x24
N2.C1: InitializeDdrioForTraining: initial RdPtrOffsetDq = 5
N5.C1.S44: VmseWriteTraining Final: centerPi = 0x3E, PiEw = 0x25, centerVref = 0x3E, vrefHeight = 0x26
N2.C2: InitializeDdrioForTraining: cleff = 10
N5.C1.S45: VmseWriteTraining Final: centerPi = 0x3B, PiEw = 0x1F, centerVref = 0x3A, vrefHeight = 0x22
N2.C2: InitializeDdrioForTraining: cwleff = 8
N5.C1.S46: VmseWriteTraining Final: centerPi = 0x3D, PiEw = 0x22, centerVref = 0x3D, vrefHeight = 0x24
N2.C2: InitializeDdrioForTraining: initial ddrInitIndexRx = 4 ddrInitIndexTx = 2
N5.C1.S47: VmseWriteTraining Final: centerPi = 0x3B, PiEw = 0x27, centerVref = 0x3A, vrefHeight = 0x26
N2.C2: InitializeDdrioForTraining: initial RdCmd2RcvEnLatency = 5
N5.C1.S48: VmseWriteTraining Final: centerPi = 0x3A, PiEw = 0x29, centerVref = 0x41, vrefHeight = 0x24
N7.C1.S00: VmseWriteTraining Final: centerPi = 0x3B, PiEw = 0x26, centerVref = 0x40, vrefHeight = 0x2A
N2.C2: InitializeDdrioForTraining: initial RdPtrOffsetRcvEn = 4
N5.C1.S49: VmseWriteTraining Final: centerPi = 0x3C, PiEw = 0x27, centerVref = 0x3F, vrefHeight = 0x2A
N7.C1.S01: VmseWriteTraining Final: centerPi = 0x3B, PiEw = 0x29, centerVref = 0x41, vrefHeight = 0x2A
N2.C2: InitializeDdrioForTraining: initial rkrdptroffsetrcvenb = 6
N5.C1.S50: VmseWriteTraining Final: centerPi = 0x3A, PiEw = 0x24, centerVref = 0x3E, vrefHeight = 0x2A
N7.C1.S02: VmseWriteTraining Final: centerPi = 0x39, PiEw = 0x25, centerVref = 0x42, vrefHeight = 0x2A
N2.C2: InitializeDdrioForTraining: initial rkrdptroffsetdrvenrcvenb = 5
N5.C1.S51: VmseWriteTraining Final: centerPi = 0x3B, PiEw = 0x2C, centerVref = 0x3B, vrefHeight = 0x2C
N7.C1.S03: VmseWriteTraining Final: centerPi = 0x3C, PiEw = 0x2A, centerVref = 0x3E, vrefHeight = 0x2E
N2.C2: InitializeDdrioForTraining: initial WrCmd2DqsStartLatency = 4
N5.C1.S52: VmseWriteTraining Final: centerPi = 0x3E, PiEw = 0x24, centerVref = 0x3F, vrefHeight = 0x28
N7.C1.S04: VmseWriteTraining Final: centerPi = 0x40, PiEw = 0x27, centerVref = 0x40, vrefHeight = 0x2A
N2.C2: InitializeDdrioForTraining: initial RdPtrOffsetDqs = 10
N5.C1.S53: VmseWriteTraining Final: centerPi = 0x3E, PiEw = 0x24, centerVref = 0x3D, vrefHeight = 0x26
N7.C1.S05: VmseWriteTraining Final: centerPi = 0x3F, PiEw = 0x27, centerVref = 0x3A, vrefHeight = 0x2A
N2.C2: InitializeDdrioForTraining: initial RdCmd2RcvEnLatency = 5
N5.C1.S54: VmseWriteTraining Final: centerPi = 0x3E, PiEw = 0x27, centerVref = 0x3C, vrefHeight = 0x2A
N7.C1.S06: VmseWriteTraining Final: centerPi = 0x3E, PiEw = 0x24, centerVref = 0x42, vrefHeight = 0x2A
N1.C1.S00: VmseWriteTraining Final: centerPi = 0x38, PiEw = 0x27, centerVref = 0x3F, vrefHeight = 0x28
N2.C2: InitializeDdrioForTraining: initial WrCmd2DqsStartLatency = 4
N5.C1.S55: VmseWriteTraining Final: centerPi = 0x3C, PiEw = 0x25, centerVref = 0x40, vrefHeight = 0x26
N7.C1.S07: VmseWriteTraining Final: centerPi = 0x3D, PiEw = 0x24, centerVref = 0x44, vrefHeight = 0x26
N1.C1.S01: VmseWriteTraining Final: centerPi = 0x37, PiEw = 0x27, centerVref = 0x3E, vrefHeight = 0x28
N2.C2: InitializeDdrioForTraining: initial RdPtrOffsetRcvEn = 4
N5.C1.S56: VmseWriteTraining Final: centerPi = 0x3B, PiEw = 0x24, centerVref = 0x40, vrefHeight = 0x26
N7.C1.S08: VmseWriteTraining Final: centerPi = 0x3D, PiEw = 0x27, centerVref = 0x41, vrefHeight = 0x28
N1.C1.S02: VmseWriteTraining Final: centerPi = 0x36, PiEw = 0x26, centerVref = 0x41, vrefHeight = 0x26
N2.C2: InitializeDdrioForTraining: initial RdPtrOffsetDqs = 6
N5.C1.S57: VmseWriteTraining Final: centerPi = 0x3C, PiEw = 0x23, centerVref = 0x3F, vrefHeight = 0x28
N7.C1.S09: VmseWriteTraining Final: centerPi = 0x3D, PiEw = 0x27, centerVref = 0x43, vrefHeight = 0x26
N1.C1.S03: VmseWriteTraining Final: centerPi = 0x35, PiEw = 0x29, centerVref = 0x3B, vrefHeight = 0x2A
N2.C2: InitializeDdrioForTraining: initial RdPtrOffsetDq = 5
N5.C1.S58: VmseWriteTraining Final: centerPi = 0x3B, PiEw = 0x28, centerVref = 0x3B, vrefHeight = 0x2C
N7.C1.S10: VmseWriteTraining Final: centerPi = 0x3C, PiEw = 0x28, centerVref = 0x41, vrefHeight = 0x2C
N1.C1.S04: VmseWriteTraining Final: centerPi = 0x3C, PiEw = 0x25, centerVref = 0x45, vrefHeight = 0x26
N2.C3: InitializeDdrioForTraining: cleff = 10
N5.C1.S59: VmseWriteTraining Final: centerPi = 0x39, PiEw = 0x2D, centerVref = 0x3E, vrefHeight = 0x2A
N7.C1.S11: VmseWriteTraining Final: centerPi = 0x39, PiEw = 0x25, centerVref = 0x3E, vrefHeight = 0x26
N1.C1.S05: VmseWriteTraining Final: centerPi = 0x39, PiEw = 0x27, centerVref = 0x42, vrefHeight = 0x28
N2.C3: InitializeDdrioForTraining: cwleff = 8
N5.C1.S60: VmseWriteTraining Final: centerPi = 0x40, PiEw = 0x26, centerVref = 0x38, vrefHeight = 0x26
N7.C1.S12: VmseWriteTraining Final: centerPi = 0x42, PiEw = 0x27, centerVref = 0x40, vrefHeight = 0x2A
N1.C1.S06: VmseWriteTraining Final: centerPi = 0x3E, PiEw = 0x26, centerVref = 0x40, vrefHeight = 0x2C
N2.C3: InitializeDdrioForTraining: initial ddrInitIndexRx = 4 ddrInitIndexTx = 2
N5.C1.S61: VmseWriteTraining Final: centerPi = 0x3E, PiEw = 0x23, centerVref = 0x3F, vrefHeight = 0x24
N7.C1.S13: VmseWriteTraining Final: centerPi = 0x41, PiEw = 0x27, centerVref = 0x46, vrefHeight = 0x2A
N1.C1.S07: VmseWriteTraining Final: centerPi = 0x3E, PiEw = 0x25, centerVref = 0x3D, vrefHeight = 0x2C
N2.C3: InitializeDdrioForTraining: initial RdCmd2RcvEnLatency = 5
N5.C1.S62: VmseWriteTraining Final: centerPi = 0x40, PiEw = 0x25, centerVref = 0x40, vrefHeight = 0x2A
N7.C1.S14: VmseWriteTraining Final: centerPi = 0x43, PiEw = 0x1E, centerVref = 0x41, vrefHeight = 0x2C
N1.C1.S08: VmseWriteTraining Final: centerPi = 0x3E, PiEw = 0x1F, centerVref = 0x3A, vrefHeight = 0x2A
N2.C3: InitializeDdrioForTraining: initial RdPtrOffsetRcvEn = 4
N5.C1.S63: VmseWriteTraining Final: centerPi = 0x3C, PiEw = 0x27, centerVref = 0x3E, vrefHeight = 0x26
N7.C1.S15: VmseWriteTraining Final: centerPi = 0x41, PiEw = 0x28, centerVref = 0x40, vrefHeight = 0x2A
N1.C1.S09: VmseWriteTraining Final: centerPi = 0x3C, PiEw = 0x26, centerVref = 0x3E, vrefHeight = 0x2A
N2.C3: InitializeDdrioForTraining: initial rkrdptroffsetrcvenb = 6
N5.C1.S64: VmseWriteTraining Final: centerPi = 0x39, PiEw = 0x28, centerVref = 0x45, vrefHeight = 0x28
N7.C1.S16: VmseWriteTraining Final: centerPi = 0x3D, PiEw = 0x25, centerVref = 0x42, vrefHeight = 0x28
N1.C1.S10: VmseWriteTraining Final: centerPi = 0x3B, PiEw = 0x23, centerVref = 0x3D, vrefHeight = 0x2C
N2.C3: InitializeDdrioForTraining: initial rkrdptroffsetdrvenrcvenb = 5
N5.C1.S65: VmseWriteTraining Final: centerPi = 0x37, PiEw = 0x29, centerVref = 0x3E, vrefHeight = 0x28
N7.C1.S17: VmseWriteTraining Final: centerPi = 0x3B, PiEw = 0x25, centerVref = 0x43, vrefHeight = 0x2A
N1.C1.S11: VmseWriteTraining Final: centerPi = 0x3A, PiEw = 0x29, centerVref = 0x42, vrefHeight = 0x2A
N2.C3: InitializeDdrioForTraining: initial WrCmd2DqsStartLatency = 4
N5.C1.S66: VmseWriteTraining Final: centerPi = 0x38, PiEw = 0x25, centerVref = 0x3B, vrefHeight = 0x28
N7.C1.S18: VmseWriteTraining Final: centerPi = 0x3A, PiEw = 0x23, centerVref = 0x3D, vrefHeight = 0x2A
N1.C1.S12: VmseWriteTraining Final: centerPi = 0x3F, PiEw = 0x25, centerVref = 0x3F, vrefHeight = 0x28
N2.C3: InitializeDdrioForTraining: initial RdPtrOffsetDqs = 10
N5.C1.S67: VmseWriteTraining Final: centerPi = 0x38, PiEw = 0x26, centerVref = 0x3C, vrefHeight = 0x2A
N7.C1.S19: VmseWriteTraining Final: centerPi = 0x38, PiEw = 0x2B, centerVref = 0x3E, vrefHeight = 0x2A
N1.C1.S13: VmseWriteTraining Final: centerPi = 0x3E, PiEw = 0x28, centerVref = 0x42, vrefHeight = 0x26
N2.C3: InitializeDdrioForTraining: initial RdCmd2RcvEnLatency = 5
N5.C1.S68: VmseWriteTraining Final: centerPi = 0x3E, PiEw = 0x26, centerVref = 0x41, vrefHeight = 0x28
N7.C1.S20: VmseWriteTraining Final: centerPi = 0x3F, PiEw = 0x27, centerVref = 0x44, vrefHeight = 0x2C
N1.C1.S14: VmseWriteTraining Final: centerPi = 0x43, PiEw = 0x20, centerVref = 0x3A, vrefHeight = 0x2E
N2.C3: InitializeDdrioForTraining: initial WrCmd2DqsStartLatency = 4
N5.C1.S69: VmseWriteTraining Final: centerPi = 0x3E, PiEw = 0x26, centerVref = 0x3F, vrefHeight = 0x28
N7.C1.S21: VmseWriteTraining Final: centerPi = 0x3D, PiEw = 0x27, centerVref = 0x40, vrefHeight = 0x2A
N1.C1.S15: VmseWriteTraining Final: centerPi = 0x3B, PiEw = 0x24, centerVref = 0x45, vrefHeight = 0x26
N2.C3: InitializeDdrioForTraining: initial RdPtrOffsetRcvEn = 4
N5.C1.S70: VmseWriteTraining Final: centerPi = 0x3B, PiEw = 0x26, centerVref = 0x3D, vrefHeight = 0x28
N7.C1.S22: VmseWriteTraining Final: centerPi = 0x3C, PiEw = 0x25, centerVref = 0x44, vrefHeight = 0x2A
N1.C1.S16: VmseWriteTraining Final: centerPi = 0x38, PiEw = 0x2A, centerVref = 0x41, vrefHeight = 0x28
N2.C3: InitializeDdrioForTraining: initial RdPtrOffsetDqs = 6
N5.C1.S71: VmseWriteTraining Final: centerPi = 0x3C, PiEw = 0x25, centerVref = 0x40, vrefHeight = 0x2A
N7.C1.S23: VmseWriteTraining Final: centerPi = 0x3C, PiEw = 0x27, centerVref = 0x3F, vrefHeight = 0x28
N1.C1.S17: VmseWriteTraining Final: centerPi = 0x37, PiEw = 0x27, centerVref = 0x3F, vrefHeight = 0x28
N2.C3: InitializeDdrioForTraining: initial RdPtrOffsetDq = 5

END - VMSE Train Write                 Time         3235 ms
N7.C1.S24: VmseWriteTraining Final: centerPi = 0x3A, PiEw = 0x29, centerVref = 0x3C, vrefHeight = 0x28
N1.C1.S18: VmseWriteTraining Final: centerPi = 0x3C, PiEw = 0x23, centerVref = 0x3E, vrefHeight = 0x2A
N2: DdrClockStopWa
N5: 
Total VMSE trainings latency = 16037 ms
N7.C1.S25: VmseWriteTraining Final: centerPi = 0x3A, PiEw = 0x2A, centerVref = 0x40, vrefHeight = 0x2A
N1.C1.S19: VmseWriteTraining Final: centerPi = 0x37, PiEw = 0x2A, centerVref = 0x3E, vrefHeight = 0x2A
N2: JckSetOdtRelaxTiming:
N4: PostVmseTraining
N7.C1.S26: VmseWriteTraining Final: centerPi = 0x37, PiEw = 0x28, centerVref = 0x45, vrefHeight = 0x2A
N1.C1.S20: VmseWriteTraining Final: centerPi = 0x3C, PiEw = 0x25, centerVref = 0x3A, vrefHeight = 0x2A
N2.C0: ODTTIMCTL (INIT RELAX) rdwidth = 10 rddly = 0 wrwidth = 8 wrdly = 0
N4.C0: PostVmseTraining
N7.C1.S27: VmseWriteTraining Final: centerPi = 0x39, PiEw = 0x2D, centerVref = 0x3B, vrefHeight = 0x2C
N1.C1.S21: VmseWriteTraining Final: centerPi = 0x3B, PiEw = 0x22, centerVref = 0x3D, vrefHeight = 0x28
N2.C0.S00: DDRIOHSIODATA0_LATCTL1 = 08040804
N4.C0: PostVMSE Training VMSE Health Check Passed
N7.C1.S28: VmseWriteTraining Final: centerPi = 0x3F, PiEw = 0x25, centerVref = 0x40, vrefHeight = 0x2A
N1.C1.S22: VmseWriteTraining Final: centerPi = 0x3C, PiEw = 0x23, centerVref = 0x3E, vrefHeight = 0x2A
N2.C0.S01: DDRIOHSIODATA0_LATCTL1 = 08040804
N4.C1: PostVmseTraining
N7.C1.S29: VmseWriteTraining Final: centerPi = 0x3D, PiEw = 0x28, centerVref = 0x3F, vrefHeight = 0x26
N1.C1.S23: VmseWriteTraining Final: centerPi = 0x3A, PiEw = 0x27, centerVref = 0x47, vrefHeight = 0x28
N2.C0.S02: DDRIOHSIODATA0_LATCTL1 = 08040804
N4.C2: PostVMSE Training VMSE Health Check Passed
N7.C1.S30: VmseWriteTraining Final: centerPi = 0x3E, PiEw = 0x27, centerVref = 0x3F, vrefHeight = 0x2C
N1.C1.S24: VmseWriteTraining Final: centerPi = 0x39, PiEw = 0x23, centerVref = 0x41, vrefHeight = 0x28
N2.C0.S03: DDRIOHSIODATA0_LATCTL1 = 08040804
N4: PreDdrTraining
N7.C1.S31: VmseWriteTraining Final: centerPi = 0x3D, PiEw = 0x29, centerVref = 0x3D, vrefHeight = 0x2A
N1.C1.S25: VmseWriteTraining Final: centerPi = 0x37, PiEw = 0x27, centerVref = 0x40, vrefHeight = 0x26
N2.C0.S04: DDRIOHSIODATA0_LATCTL1 = 08040804
N4: PreDdrTraining[QCRM=OFF]
N7.C1.S32: VmseWriteTraining Final: centerPi = 0x3D, PiEw = 0x2B, centerVref = 0x3F, vrefHeight = 0x2C
N1.C1.S26: VmseWriteTraining Final: centerPi = 0x3A, PiEw = 0x23, centerVref = 0x41, vrefHeight = 0x2C
N2.C0.S05: DDRIOHSIODATA0_LATCTL1 = 08040804
N4.C0.D0: CheckRankPopLocal: dimmPresent: 1, numRanks = 2
N7.C1.S33: VmseWriteTraining Final: centerPi = 0x3D, PiEw = 0x2A, centerVref = 0x3A, vrefHeight = 0x2E
N1.C1.S27: VmseWriteTraining Final: centerPi = 0x3A, PiEw = 0x27, centerVref = 0x3C, vrefHeight = 0x2C
N2.C0.S06: DDRIOHSIODATA0_LATCTL1 = 08040804
N4.C0.D0.R0: CheckRankPopLocal: mapOut: 0, enabled = 1
N7.C1.S34: VmseWriteTraining Final: centerPi = 0x39, PiEw = 0x29, centerVref = 0x43, vrefHeight = 0x2A
N1.C1.S28: VmseWriteTraining Final: centerPi = 0x40, PiEw = 0x24, centerVref = 0x3E, vrefHeight = 0x2A
N2.C0.S07: DDRIOHSIODATA0_LATCTL1 = 08040804
N4.C0.D0.R1: CheckRankPopLocal: mapOut: 0, enabled = 1
N7.C1.S35: VmseWriteTraining Final: centerPi = 0x3A, PiEw = 0x26, centerVref = 0x3D, vrefHeight = 0x2E
N1.C1.S29: VmseWriteTraining Final: centerPi = 0x3C, PiEw = 0x26, centerVref = 0x41, vrefHeight = 0x26
N2.C0.S08: DDRIOHSIODATA0_LATCTL1 = 08040804
N4.C0.D1: CheckRankPopLocal: dimmPresent: 1, numRanks = 2
N7.C1.S36: VmseWriteTraining Final: centerPi = 0x3F, PiEw = 0x26, centerVref = 0x46, vrefHeight = 0x2C
N1.C1.S30: VmseWriteTraining Final: centerPi = 0x3A, PiEw = 0x2A, centerVref = 0x42, vrefHeight = 0x28
N2.C1: ODTTIMCTL (INIT RELAX) rdwidth = 10 rddly = 0 wrwidth = 8 wrdly = 0
N4.C0.D1.R0: CheckRankPopLocal: mapOut: 0, enabled = 1
N7.C1.S37: VmseWriteTraining Final: centerPi = 0x3E, PiEw = 0x25, centerVref = 0x45, vrefHeight = 0x2A
N1.C1.S31: VmseWriteTraining Final: centerPi = 0x42, PiEw = 0x21, centerVref = 0x3D, vrefHeight = 0x2A
N2.C1.S00: DDRIOHSIODATA0_LATCTL1 = 08040804
N4.C0.D1.R1: CheckRankPopLocal: mapOut: 0, enabled = 1
N7.C1.S38: VmseWriteTraining Final: centerPi = 0x40, PiEw = 0x27, centerVref = 0x3D, vrefHeight = 0x2C
N1.C1.S32: VmseWriteTraining Final: centerPi = 0x3D, PiEw = 0x24, centerVref = 0x3A, vrefHeight = 0x2A
N2.C1.S01: DDRIOHSIODATA0_LATCTL1 = 08040804
N4.C0.D2: CheckRankPopLocal: dimmPresent: 0, numRanks = 0
N7.C1.S39: VmseWriteTraining Final: centerPi = 0x40, PiEw = 0x25, centerVref = 0x3E, vrefHeight = 0x2E
N1.C1.S33: VmseWriteTraining Final: centerPi = 0x3F, PiEw = 0x26, centerVref = 0x38, vrefHeight = 0x2C
N2.C1.S02: DDRIOHSIODATA0_LATCTL1 = 08040804
N4.C0.D0: CheckRankPopLocal: amap: 0x00000000
N7.C1.S40: VmseWriteTraining Final: centerPi = 0x3A, PiEw = 0x24, centerVref = 0x46, vrefHeight = 0x2A
N1.C1.S34: VmseWriteTraining Final: centerPi = 0x3B, PiEw = 0x27, centerVref = 0x3E, vrefHeight = 0x2E
N2.C1.S03: DDRIOHSIODATA0_LATCTL1 = 08040804
N4.C0.D1: CheckRankPopLocal: amap: 0x00000000
N7.C1.S41: VmseWriteTraining Final: centerPi = 0x37, PiEw = 0x26, centerVref = 0x3F, vrefHeight = 0x26
N1.C1.S35: VmseWriteTraining Final: centerPi = 0x3E, PiEw = 0x25, centerVref = 0x3A, vrefHeight = 0x30
N2.C1.S04: DDRIOHSIODATA0_LATCTL1 = 08040804
N4.C0.D2: CheckRankPopLocal: amap: 0x00000000
N7.C1.S42: VmseWriteTraining Final: centerPi = 0x3C, PiEw = 0x23, centerVref = 0x3C, vrefHeight = 0x2A
N1.C1.S36: VmseWriteTraining Final: centerPi = 0x3E, PiEw = 0x29, centerVref = 0x3C, vrefHeight = 0x2A
N2.C1.S05: DDRIOHSIODATA0_LATCTL1 = 08040804
N4.C1.D0: CheckRankPopLocal: dimmPresent: 1, numRanks = 2
N7.C1.S43: VmseWriteTraining Final: centerPi = 0x39, PiEw = 0x27, centerVref = 0x3E, vrefHeight = 0x2A
N1.C1.S37: VmseWriteTraining Final: centerPi = 0x43, PiEw = 0x25, centerVref = 0x34, vrefHeight = 0x2E
N2.C1.S06: DDRIOHSIODATA0_LATCTL1 = 08040804
N4.C1.D0.R0: CheckRankPopLocal: mapOut: 0, enabled = 1
N7.C1.S44: VmseWriteTraining Final: centerPi = 0x40, PiEw = 0x28, centerVref = 0x3B, vrefHeight = 0x2A
N1.C1.S38: VmseWriteTraining Final: centerPi = 0x3A, PiEw = 0x28, centerVref = 0x3E, vrefHeight = 0x2A
N2.C1.S07: DDRIOHSIODATA0_LATCTL1 = 08040804
N4.C1.D0.R1: CheckRankPopLocal: mapOut: 0, enabled = 1
N7.C1.S45: VmseWriteTraining Final: centerPi = 0x3E, PiEw = 0x25, centerVref = 0x3E, vrefHeight = 0x2A
N1.C1.S39: VmseWriteTraining Final: centerPi = 0x3B, PiEw = 0x28, centerVref = 0x3F, vrefHeight = 0x28
N2.C1.S08: DDRIOHSIODATA0_LATCTL1 = 08040804
N4.C1.D1: CheckRankPopLocal: dimmPresent: 1, numRanks = 2
N7.C1.S46: VmseWriteTraining Final: centerPi = 0x3C, PiEw = 0x24, centerVref = 0x3F, vrefHeight = 0x28
N1.C1.S40: VmseWriteTraining Final: centerPi = 0x3D, PiEw = 0x1E, centerVref = 0x3B, vrefHeight = 0x26
N2.C2: ODTTIMCTL (INIT RELAX) rdwidth = 10 rddly = 0 wrwidth = 8 wrdly = 0
N4.C1.D1.R0: CheckRankPopLocal: mapOut: 0, enabled = 1
N7.C1.S47: VmseWriteTraining Final: centerPi = 0x3E, PiEw = 0x27, centerVref = 0x3E, vrefHeight = 0x2A
N1.C1.S41: VmseWriteTraining Final: centerPi = 0x37, PiEw = 0x28, centerVref = 0x41, vrefHeight = 0x24
N2.C2.S00: DDRIOHSIODATA0_LATCTL1 = 08040804
N4.C1.D1.R1: CheckRankPopLocal: mapOut: 0, enabled = 1
N7.C1.S48: VmseWriteTraining Final: centerPi = 0x3C, PiEw = 0x28, centerVref = 0x41, vrefHeight = 0x28
N1.C1.S42: VmseWriteTraining Final: centerPi = 0x37, PiEw = 0x1E, centerVref = 0x3F, vrefHeight = 0x22
N2.C2.S01: DDRIOHSIODATA0_LATCTL1 = 08040804
N4.C1.D2: CheckRankPopLocal: dimmPresent: 0, numRanks = 0
N7.C1.S49: VmseWriteTraining Final: centerPi = 0x3E, PiEw = 0x2A, centerVref = 0x3B, vrefHeight = 0x30
N1.C1.S43: VmseWriteTraining Final: centerPi = 0x36, PiEw = 0x21, centerVref = 0x3B, vrefHeight = 0x26
N2.C2.S02: DDRIOHSIODATA0_LATCTL1 = 08040804
N4.C1.D0: CheckRankPopLocal: amap: 0x00000000
N7.C1.S50: VmseWriteTraining Final: centerPi = 0x3B, PiEw = 0x24, centerVref = 0x3D, vrefHeight = 0x2E
N1.C1.S44: VmseWriteTraining Final: centerPi = 0x3D, PiEw = 0x27, centerVref = 0x42, vrefHeight = 0x28
N2.C2.S03: DDRIOHSIODATA0_LATCTL1 = 08040804
N4.C1.D1: CheckRankPopLocal: amap: 0x00000000
N7.C1.S51: VmseWriteTraining Final: centerPi = 0x3E, PiEw = 0x2B, centerVref = 0x3F, vrefHeight = 0x30
N1.C1.S45: VmseWriteTraining Final: centerPi = 0x3B, PiEw = 0x1E, centerVref = 0x3F, vrefHeight = 0x24
N2.C2.S04: DDRIOHSIODATA0_LATCTL1 = 08040804
N4.C1.D2: CheckRankPopLocal: amap: 0x00000000
N7.C1.S52: VmseWriteTraining Final: centerPi = 0x41, PiEw = 0x28, centerVref = 0x3C, vrefHeight = 0x2C
N1.C1.S46: VmseWriteTraining Final: centerPi = 0x3F, PiEw = 0x23, centerVref = 0x38, vrefHeight = 0x26
N2.C2.S05: DDRIOHSIODATA0_LATCTL1 = 08040804
N4.C2.D0: CheckRankPopLocal: dimmPresent: 1, numRanks = 2
N7.C1.S53: VmseWriteTraining Final: centerPi = 0x3F, PiEw = 0x24, centerVref = 0x40, vrefHeight = 0x2A
N1.C1.S47: VmseWriteTraining Final: centerPi = 0x3C, PiEw = 0x28, centerVref = 0x43, vrefHeight = 0x28
N2.C2.S06: DDRIOHSIODATA0_LATCTL1 = 08040804
N4.C2.D0.R0: CheckRankPopLocal: mapOut: 0, enabled = 1
N7.C1.S54: VmseWriteTraining Final: centerPi = 0x3F, PiEw = 0x29, centerVref = 0x3D, vrefHeight = 0x2E
N1.C1.S48: VmseWriteTraining Final: centerPi = 0x3F, PiEw = 0x22, centerVref = 0x3C, vrefHeight = 0x26
N2.C2.S07: DDRIOHSIODATA0_LATCTL1 = 08040804
N4.C2.D0.R1: CheckRankPopLocal: mapOut: 0, enabled = 1
N7.C1.S55: VmseWriteTraining Final: centerPi = 0x3C, PiEw = 0x25, centerVref = 0x3F, vrefHeight = 0x2A
N1.C1.S49: VmseWriteTraining Final: centerPi = 0x42, PiEw = 0x24, centerVref = 0x3D, vrefHeight = 0x2C
N2.C2.S08: DDRIOHSIODATA0_LATCTL1 = 08040804
N4.C2.D1: CheckRankPopLocal: dimmPresent: 1, numRanks = 2
N7.C1.S56: VmseWriteTraining Final: centerPi = 0x3C, PiEw = 0x28, centerVref = 0x41, vrefHeight = 0x28
N1.C1.S50: VmseWriteTraining Final: centerPi = 0x3A, PiEw = 0x29, centerVref = 0x41, vrefHeight = 0x2E
N2.C3: ODTTIMCTL (INIT RELAX) rdwidth = 10 rddly = 0 wrwidth = 8 wrdly = 0
N4.C2.D1.R0: CheckRankPopLocal: mapOut: 0, enabled = 1
N7.C1.S57: VmseWriteTraining Final: centerPi = 0x3E, PiEw = 0x2D, centerVref = 0x43, vrefHeight = 0x2C
N1.C1.S51: VmseWriteTraining Final: centerPi = 0x3C, PiEw = 0x29, centerVref = 0x3B, vrefHeight = 0x2E
N2.C3.S00: DDRIOHSIODATA0_LATCTL1 = 08040804
N4.C2.D1.R1: CheckRankPopLocal: mapOut: 0, enabled = 1
N7.C1.S58: VmseWriteTraining Final: centerPi = 0x3D, PiEw = 0x2A, centerVref = 0x3C, vrefHeight = 0x2E
N1.C1.S52: VmseWriteTraining Final: centerPi = 0x41, PiEw = 0x29, centerVref = 0x3B, vrefHeight = 0x2C
N2.C3.S01: DDRIOHSIODATA0_LATCTL1 = 08040804
N4.C2.D2: CheckRankPopLocal: dimmPresent: 0, numRanks = 0
N7.C1.S59: VmseWriteTraining Final: centerPi = 0x3B, PiEw = 0x2C, centerVref = 0x3F, vrefHeight = 0x2C
N1.C1.S53: VmseWriteTraining Final: centerPi = 0x3E, PiEw = 0x23, centerVref = 0x3D, vrefHeight = 0x28
N2.C3.S02: DDRIOHSIODATA0_LATCTL1 = 08040804
N4.C2.D0: CheckRankPopLocal: amap: 0x00000000
N7.C1.S60: VmseWriteTraining Final: centerPi = 0x40, PiEw = 0x26, centerVref = 0x40, vrefHeight = 0x2A
N1.C1.S54: VmseWriteTraining Final: centerPi = 0x3E, PiEw = 0x26, centerVref = 0x3D, vrefHeight = 0x28
N2.C3.S03: DDRIOHSIODATA0_LATCTL1 = 08040804
N4.C2.D1: CheckRankPopLocal: amap: 0x00000000
N7.C1.S61: VmseWriteTraining Final: centerPi = 0x3F, PiEw = 0x25, centerVref = 0x3E, vrefHeight = 0x28
N1.C1.S55: VmseWriteTraining Final: centerPi = 0x3C, PiEw = 0x25, centerVref = 0x40, vrefHeight = 0x26
N2.C3.S04: DDRIOHSIODATA0_LATCTL1 = 08040804
N4.C2.D2: CheckRankPopLocal: amap: 0x00000000
N7.C1.S62: VmseWriteTraining Final: centerPi = 0x41, PiEw = 0x26, centerVref = 0x40, vrefHeight = 0x2A
N1.C1.S56: VmseWriteTraining Final: centerPi = 0x3D, PiEw = 0x22, centerVref = 0x44, vrefHeight = 0x26
N2.C3.S05: DDRIOHSIODATA0_LATCTL1 = 08040804
N4.C3.D0: CheckRankPopLocal: dimmPresent: 1, numRanks = 2
N7.C1.S63: VmseWriteTraining Final: centerPi = 0x3F, PiEw = 0x29, centerVref = 0x43, vrefHeight = 0x2A
N1.C1.S57: VmseWriteTraining Final: centerPi = 0x3D, PiEw = 0x28, centerVref = 0x41, vrefHeight = 0x2C
N2.C3.S06: DDRIOHSIODATA0_LATCTL1 = 08040804
N4.C3.D0.R0: CheckRankPopLocal: mapOut: 0, enabled = 1
N7.C1.S64: VmseWriteTraining Final: centerPi = 0x3C, PiEw = 0x28, centerVref = 0x40, vrefHeight = 0x2A
N1.C1.S58: VmseWriteTraining Final: centerPi = 0x3A, PiEw = 0x28, centerVref = 0x3D, vrefHeight = 0x2C
N2.C3.S07: DDRIOHSIODATA0_LATCTL1 = 08040804
N4.C3.D0.R1: CheckRankPopLocal: mapOut: 0, enabled = 1
N7.C1.S65: VmseWriteTraining Final: centerPi = 0x39, PiEw = 0x25, centerVref = 0x45, vrefHeight = 0x2C
N1.C1.S59: VmseWriteTraining Final: centerPi = 0x39, PiEw = 0x2A, centerVref = 0x3E, vrefHeight = 0x2A
N2.C3.S08: DDRIOHSIODATA0_LATCTL1 = 08040804
N4.C3.D1: CheckRankPopLocal: dimmPresent: 1, numRanks = 2
N7.C1.S66: VmseWriteTraining Final: centerPi = 0x3A, PiEw = 0x23, centerVref = 0x42, vrefHeight = 0x2C
N1.C1.S60: VmseWriteTraining Final: centerPi = 0x40, PiEw = 0x26, centerVref = 0x3C, vrefHeight = 0x2A

START - Early Command Training
N4.C3.D1.R0: CheckRankPopLocal: mapOut: 0, enabled = 1
N7.C1.S67: VmseWriteTraining Final: centerPi = 0x38, PiEw = 0x2C, centerVref = 0x41, vrefHeight = 0x2C
N1.C1.S61: VmseWriteTraining Final: centerPi = 0x3F, PiEw = 0x26, centerVref = 0x41, vrefHeight = 0x28
N2.C0: DDRIOHSIODATA0_LATCTL1 = 08040804
N4.C3.D1.R1: CheckRankPopLocal: mapOut: 0, enabled = 1
N7.C1.S68: VmseWriteTraining Final: centerPi = 0x43, PiEw = 0x21, centerVref = 0x39, vrefHeight = 0x2C
N1.C1.S62: VmseWriteTraining Final: centerPi = 0x42, PiEw = 0x21, centerVref = 0x38, vrefHeight = 0x2C
N2.C0: RdCmd2DataValidLatency = 20, (dlyFrmS = 15, clEff = 10, earlyCas = 0, selNTiming = 2)
N4.C3.D2: CheckRankPopLocal: dimmPresent: 0, numRanks = 0
N7.C1.S69: VmseWriteTraining Final: centerPi = 0x3F, PiEw = 0x25, centerVref = 0x38, vrefHeight = 0x2A
N1.C1.S63: VmseWriteTraining Final: centerPi = 0x3D, PiEw = 0x26, centerVref = 0x42, vrefHeight = 0x28
N2.C0: SettingForTrainingStep: RdCmd2RcvEnLatency = 5
N4.C3.D0: CheckRankPopLocal: amap: 0x00000000
N7.C1.S70: VmseWriteTraining Final: centerPi = 0x3D, PiEw = 0x26, centerVref = 0x41, vrefHeight = 0x2A
N1.C1.S64: VmseWriteTraining Final: centerPi = 0x3F, PiEw = 0x21, centerVref = 0x3E, vrefHeight = 0x2C
N2.C0: SettingForTrainingStep: Programming 7 tick initial value to CTL signals
N4.C3.D1: CheckRankPopLocal: amap: 0x00000000
N7.C1.S71: VmseWriteTraining Final: centerPi = 0x3F, PiEw = 0x23, centerVref = 0x3B, vrefHeight = 0x2C
N1.C1.S65: VmseWriteTraining Final: centerPi = 0x38, PiEw = 0x27, centerVref = 0x3E, vrefHeight = 0x26
N2.C1: DDRIOHSIODATA0_LATCTL1 = 08040804
N4.C3.D2: CheckRankPopLocal: amap: 0x00000000

END - VMSE Train Write                 Time         4022 ms
N1.C1.S66: VmseWriteTraining Final: centerPi = 0x3C, PiEw = 0x1F, centerVref = 0x3C, vrefHeight = 0x2C
N2.C1: RdCmd2DataValidLatency = 20, (dlyFrmS = 15, clEff = 10, earlyCas = 0, selNTiming = 2)
N4.C0: JCK cmd timing = 3N
N7: 
Total VMSE trainings latency = 17651 ms
N1.C1.S67: VmseWriteTraining Final: centerPi = 0x37, PiEw = 0x24, centerVref = 0x4B, vrefHeight = 0x30
N2.C1: SettingForTrainingStep: RdCmd2RcvEnLatency = 5
N4.C0: RdCmd2DataValidLatency = 20, (dlyFrmS = 15, clEff = 10, earlyCas = 0, selNTiming = 2)
N6: PostVmseTraining
N1.C1.S68: VmseWriteTraining Final: centerPi = 0x3E, PiEw = 0x23, centerVref = 0x43, vrefHeight = 0x28
N2.C1: SettingForTrainingStep: Programming 10 tick initial value to CTL signals
N4.C0: CLK0_CFG: 0x000FFF30
N6.C0: PostVmseTraining
N1.C1.S69: VmseWriteTraining Final: centerPi = 0x40, PiEw = 0x24, centerVref = 0x3C, vrefHeight = 0x2A
N2.C2: DDRIOHSIODATA0_LATCTL1 = 08040804
N4.C0: DDR_RANKCTL: 0x000FEA40
N6.C0: PostVMSE Training VMSE Health Check Passed
N1.C1.S70: VmseWriteTraining Final: centerPi = 0x3E, PiEw = 0x21, centerVref = 0x40, vrefHeight = 0x2C
N2.C2: RdCmd2DataValidLatency = 20, (dlyFrmS = 15, clEff = 10, earlyCas = 0, selNTiming = 2)
N4.C0: MCODT = 0 ( 50 ohms)
N6.C1: PostVmseTraining
N1.C1.S71: VmseWriteTraining Final: centerPi = 0x3C, PiEw = 0x23, centerVref = 0x3C, vrefHeight = 0x2A
N2.C2: SettingForTrainingStep: RdCmd2RcvEnLatency = 5
N4.C0.D0.R0: Rtt_wr = 120, Rtt_nom = 20
N6.C2: PostVMSE Training VMSE Health Check Passed

END - VMSE Train Write                 Time         4099 ms
N2.C2: SettingForTrainingStep: Programming 7 tick initial value to CTL signals
N4.C0.D0.R1: Rtt_wr = 120, Rtt_nom = 0
N6: PreDdrTraining
Checkpoint Code: Socket 0, 0xB6, 0x64, 0x0000
N2.C3: DDRIOHSIODATA0_LATCTL1 = 08040804
N4.C0.D1.R0: Rtt_wr = 120, Rtt_nom = 20
N6: PreDdrTraining[QCRM=OFF]
N1: 
Total VMSE trainings latency = 17733 ms
N2.C3: RdCmd2DataValidLatency = 20, (dlyFrmS = 15, clEff = 10, earlyCas = 0, selNTiming = 2)
N4.C0.D1.R1: Rtt_wr = 120, Rtt_nom = 0
N6.C0.D0: CheckRankPopLocal: dimmPresent: 1, numRanks = 2
N0: PostVmseTraining
N2.C3: SettingForTrainingStep: RdCmd2RcvEnLatency = 5
N4.C0: ODTRDCTL00 = 0x01000104
N6.C0.D0.R0: CheckRankPopLocal: mapOut: 0, enabled = 1
Checkpoint Code: Socket 0, 0xB6, 0x5C, 0x0000
N2.C3: SettingForTrainingStep: Programming 10 tick initial value to CTL signals
N4.C0: ODTRDCTL01 = 0x00000001
N6.C0.D0.R1: CheckRankPopLocal: mapOut: 0, enabled = 1
N0.C0: PostVmseTraining
N2: FSM Basic Clock Training
N4.C0: ODTWRCTL00 = 0x05000185
N6.C0.D1: CheckRankPopLocal: dimmPresent: 1, numRanks = 2
N0.C0: PostVMSE Training VMSE Health Check Passed
N2.C0: JCK cmd timing = 1N
N4.C0: ODTWRCTL01 = 0x00000009
N6.C0.D1.R0: CheckRankPopLocal: mapOut: 0, enabled = 1
N0.C1: PostVmseTraining
N2.C0: RdCmd2DataValidLatency = 21, (dlyFrmS = 15, clEff = 10, earlyCas = 0, selNTiming = 0)
N4.C1: RdCmd2DataValidLatency = 20, (dlyFrmS = 15, clEff = 10, earlyCas = 0, selNTiming = 2)
N6.C0.D1.R1: CheckRankPopLocal: mapOut: 0, enabled = 1
N0.C2: PostVMSE Training VMSE Health Check Passed
N2.C1: RdCmd2DataValidLatency = 21, (dlyFrmS = 15, clEff = 10, earlyCas = 0, selNTiming = 0)
N4.C1: CLK0_CFG: 0x000FF330
N6.C0.D2: CheckRankPopLocal: dimmPresent: 0, numRanks = 0
N0: PreDdrTraining
N2.C2: JCK cmd timing = 1N
N4.C1: DDR_RANKCTL: 0x000FEA40
N6.C0.D0: CheckRankPopLocal: amap: 0x00000000
N0: PreDdrTraining[QCRM=OFF]
N2.C2: RdCmd2DataValidLatency = 21, (dlyFrmS = 15, clEff = 10, earlyCas = 0, selNTiming = 0)
N4.C1: MCODT = 0 ( 50 ohms)
N6.C0.D1: CheckRankPopLocal: amap: 0x00000000
N0.C0.D0: CheckRankPopLocal: dimmPresent: 1, numRanks = 2
N2.C3: RdCmd2DataValidLatency = 21, (dlyFrmS = 15, clEff = 10, earlyCas = 0, selNTiming = 0)
N4.C1.D0.R0: Rtt_wr = 120, Rtt_nom = 20
N6.C0.D2: CheckRankPopLocal: amap: 0x00000000
N0.C0.D0.R0: CheckRankPopLocal: mapOut: 0, enabled = 1
N4.C1.D0.R1: Rtt_wr = 120, Rtt_nom = 0
N6.C1.D0: CheckRankPopLocal: dimmPresent: 1, numRanks = 2
N0.C0.D0.R1: CheckRankPopLocal: mapOut: 0, enabled = 1
N4.C1.D1.R0: Rtt_wr = 120, Rtt_nom = 20
N6.C1.D0.R0: CheckRankPopLocal: mapOut: 0, enabled = 1
N0.C0.D1: CheckRankPopLocal: dimmPresent: 1, numRanks = 2
N4.C1.D1.R1: Rtt_wr = 120, Rtt_nom = 0
N6.C1.D0.R1: CheckRankPopLocal: mapOut: 0, enabled = 1
N0.C0.D1.R0: CheckRankPopLocal: mapOut: 0, enabled = 1
N4.C1: ODTRDCTL00 = 0x01000104
N6.C1.D1: CheckRankPopLocal: dimmPresent: 1, numRanks = 2
N0.C0.D1.R1: CheckRankPopLocal: mapOut: 0, enabled = 1
N4.C1: ODTRDCTL01 = 0x00000001
N6.C1.D1.R0: CheckRankPopLocal: mapOut: 0, enabled = 1
N0.C0.D2: CheckRankPopLocal: dimmPresent: 0, numRanks = 0
N4.C1: ODTWRCTL00 = 0x05000185
N6.C1.D1.R1: CheckRankPopLocal: mapOut: 0, enabled = 1
N0.C0.D0: CheckRankPopLocal: amap: 0x00000000
N4.C1: ODTWRCTL01 = 0x00000009
N6.C1.D2: CheckRankPopLocal: dimmPresent: 0, numRanks = 0
N0.C0.D1: CheckRankPopLocal: amap: 0x00000000
N4.C2: JCK cmd timing = 3N
N6.C1.D0: CheckRankPopLocal: amap: 0x00000000
N0.C0.D2: CheckRankPopLocal: amap: 0x00000000
N4.C2: RdCmd2DataValidLatency = 20, (dlyFrmS = 15, clEff = 10, earlyCas = 0, selNTiming = 2)
N6.C1.D1: CheckRankPopLocal: amap: 0x00000000
N0.C1.D0: CheckRankPopLocal: dimmPresent: 1, numRanks = 2
N4.C2: CLK0_CFG: 0x000FFF30
N6.C1.D2: CheckRankPopLocal: amap: 0x00000000
N0.C1.D0.R0: CheckRankPopLocal: mapOut: 0, enabled = 1
N4.C2: DDR_RANKCTL: 0x000FEA40
N6.C2.D0: CheckRankPopLocal: dimmPresent: 1, numRanks = 2
N0.C1.D0.R1: CheckRankPopLocal: mapOut: 0, enabled = 1
N4.C2: MCODT = 0 ( 50 ohms)
N6.C2.D0.R0: CheckRankPopLocal: mapOut: 0, enabled = 1
N0.C1.D1: CheckRankPopLocal: dimmPresent: 1, numRanks = 2
N4.C2.D0.R0: Rtt_wr = 120, Rtt_nom = 20
N6.C2.D0.R1: CheckRankPopLocal: mapOut: 0, enabled = 1
N0.C1.D1.R0: CheckRankPopLocal: mapOut: 0, enabled = 1
N4.C2.D0.R1: Rtt_wr = 120, Rtt_nom = 0
N6.C2.D1: CheckRankPopLocal: dimmPresent: 1, numRanks = 2
N0.C1.D1.R1: CheckRankPopLocal: mapOut: 0, enabled = 1
N4.C2.D1.R0: Rtt_wr = 120, Rtt_nom = 20
N6.C2.D1.R0: CheckRankPopLocal: mapOut: 0, enabled = 1
N0.C1.D2: CheckRankPopLocal: dimmPresent: 0, numRanks = 0
N4.C2.D1.R1: Rtt_wr = 120, Rtt_nom = 0
N6.C2.D1.R1: CheckRankPopLocal: mapOut: 0, enabled = 1
N0.C1.D0: CheckRankPopLocal: amap: 0x00000000
N4.C2: ODTRDCTL00 = 0x01000104
N6.C2.D2: CheckRankPopLocal: dimmPresent: 0, numRanks = 0
N0.C1.D1: CheckRankPopLocal: amap: 0x00000000
N4.C2: ODTRDCTL01 = 0x00000001
N6.C2.D0: CheckRankPopLocal: amap: 0x00000000
N0.C1.D2: CheckRankPopLocal: amap: 0x00000000
N4.C2: ODTWRCTL00 = 0x05000185
N6.C2.D1: CheckRankPopLocal: amap: 0x00000000
N0.C2.D0: CheckRankPopLocal: dimmPresent: 1, numRanks = 2
N4.C2: ODTWRCTL01 = 0x00000009
N6.C2.D2: CheckRankPopLocal: amap: 0x00000000
N0.C2.D0.R0: CheckRankPopLocal: mapOut: 0, enabled = 1
N4.C3: RdCmd2DataValidLatency = 20, (dlyFrmS = 15, clEff = 10, earlyCas = 0, selNTiming = 2)
N6.C3.D0: CheckRankPopLocal: dimmPresent: 1, numRanks = 2
N0.C2.D0.R1: CheckRankPopLocal: mapOut: 0, enabled = 1
N4.C3: CLK0_CFG: 0x000FF330
N6.C3.D0.R0: CheckRankPopLocal: mapOut: 0, enabled = 1
N0.C2.D1: CheckRankPopLocal: dimmPresent: 1, numRanks = 2
N4.C3: DDR_RANKCTL: 0x000FEA40
N6.C3.D0.R1: CheckRankPopLocal: mapOut: 0, enabled = 1
N0.C2.D1.R0: CheckRankPopLocal: mapOut: 0, enabled = 1
N4.C3: MCODT = 0 ( 50 ohms)
N6.C3.D1: CheckRankPopLocal: dimmPresent: 1, numRanks = 2
N0.C2.D1.R1: CheckRankPopLocal: mapOut: 0, enabled = 1
N4.C3.D0.R0: Rtt_wr = 120, Rtt_nom = 20
N6.C3.D1.R0: CheckRankPopLocal: mapOut: 0, enabled = 1
N0.C2.D2: CheckRankPopLocal: dimmPresent: 0, numRanks = 0
N4.C3.D0.R1: Rtt_wr = 120, Rtt_nom = 0
N6.C3.D1.R1: CheckRankPopLocal: mapOut: 0, enabled = 1
N0.C2.D0: CheckRankPopLocal: amap: 0x00000000
N4.C3.D1.R0: Rtt_wr = 120, Rtt_nom = 20
N6.C3.D2: CheckRankPopLocal: dimmPresent: 0, numRanks = 0
N0.C2.D1: CheckRankPopLocal: amap: 0x00000000
N4.C3.D1.R1: Rtt_wr = 120, Rtt_nom = 0
N6.C3.D0: CheckRankPopLocal: amap: 0x00000000
N0.C2.D2: CheckRankPopLocal: amap: 0x00000000
N4.C3: ODTRDCTL00 = 0x01000104
N6.C3.D1: CheckRankPopLocal: amap: 0x00000000
N0.C3.D0: CheckRankPopLocal: dimmPresent: 1, numRanks = 2
N4.C3: ODTRDCTL01 = 0x00000001
N6.C3.D2: CheckRankPopLocal: amap: 0x00000000
N0.C3.D0.R0: CheckRankPopLocal: mapOut: 0, enabled = 1
N4.C3: ODTWRCTL00 = 0x05000185
N6.C0: JCK cmd timing = 3N
N0.C3.D0.R1: CheckRankPopLocal: mapOut: 0, enabled = 1
N4.C3: ODTWRCTL01 = 0x00000009
N6.C0: RdCmd2DataValidLatency = 20, (dlyFrmS = 15, clEff = 10, earlyCas = 0, selNTiming = 2)
N0.C3.D1: CheckRankPopLocal: dimmPresent: 1, numRanks = 2
N4.C0.D0: PreDdrTraining: Program dimmmtr 0xC502D
N6.C0: CLK0_CFG: 0x000FFF30
N0.C3.D1.R0: CheckRankPopLocal: mapOut: 0, enabled = 1
N4.C0.D1: PreDdrTraining: Program dimmmtr 0xC502D
N6.C0: DDR_RANKCTL: 0x000FEA40
N0.C3.D1.R1: CheckRankPopLocal: mapOut: 0, enabled = 1
N4.C1.D0: PreDdrTraining: Program dimmmtr 0xC502D
N6.C0: MCODT = 0 ( 50 ohms)
N0.C3.D2: CheckRankPopLocal: dimmPresent: 0, numRanks = 0
N4.C1.D1: PreDdrTraining: Program dimmmtr 0xC502D
N6.C0.D0.R0: Rtt_wr = 120, Rtt_nom = 20
N0.C3.D0: CheckRankPopLocal: amap: 0x00000000
N4.C2.D0: PreDdrTraining: Program dimmmtr 0xC502D
N6.C0.D0.R1: Rtt_wr = 120, Rtt_nom = 0
N0.C3.D1: CheckRankPopLocal: amap: 0x00000000
N4.C2.D1: PreDdrTraining: Program dimmmtr 0xC502D
N6.C0.D1.R0: Rtt_wr = 120, Rtt_nom = 20
N0.C3.D2: CheckRankPopLocal: amap: 0x00000000
N4.C3.D0: PreDdrTraining: Program dimmmtr 0xC502D
N6.C0.D1.R1: Rtt_wr = 120, Rtt_nom = 0
N0.C0: JCK cmd timing = 3N
N4.C3.D1: PreDdrTraining: Program dimmmtr 0xC502D
N6.C0: ODTRDCTL00 = 0x01000104
N0.C0: RdCmd2DataValidLatency = 20, (dlyFrmS = 15, clEff = 10, earlyCas = 0, selNTiming = 2)
N4: InitializeDdrioForUse
N6.C0: ODTRDCTL01 = 0x00000001
N0.C0: CLK0_CFG: 0x000FFF30
N4: SetupJckForBL: setting BL to 8
N6.C0: ODTWRCTL00 = 0x05000185
N0.C0: DDR_RANKCTL: 0x000FEA40
N4.C0: ODTTIMCTL (INIT RELAX) rdwidth = 10 rddly = 0 wrwidth = 8 wrdly = 0
N6.C0: ODTWRCTL01 = 0x00000009
N0.C0: MCODT = 0 ( 50 ohms)
N4.C1: ODTTIMCTL (INIT RELAX) rdwidth = 10 rddly = 0 wrwidth = 8 wrdly = 0
N6.C1: RdCmd2DataValidLatency = 20, (dlyFrmS = 15, clEff = 10, earlyCas = 0, selNTiming = 2)
N0.C0.D0.R0: Rtt_wr = 120, Rtt_nom = 20
N4.C2: ODTTIMCTL (INIT RELAX) rdwidth = 10 rddly = 0 wrwidth = 8 wrdly = 0
N6.C1: CLK0_CFG: 0x000FF330
N0.C0.D0.R1: Rtt_wr = 120, Rtt_nom = 0
N4.C3: ODTTIMCTL (INIT RELAX) rdwidth = 10 rddly = 0 wrwidth = 8 wrdly = 0
N6.C1: DDR_RANKCTL: 0x000FEA40
N0.C0.D1.R0: Rtt_wr = 120, Rtt_nom = 20
N6.C1: MCODT = 0 ( 50 ohms)
N0.C0.D1.R1: Rtt_wr = 120, Rtt_nom = 0
N4: JckDdrTraining
N6.C1.D0.R0: Rtt_wr = 120, Rtt_nom = 20
N0.C0: ODTRDCTL00 = 0x01000104
N4: InitializeDdrioForTraining: QCRM Disabled
N6.C1.D0.R1: Rtt_wr = 120, Rtt_nom = 0
N0.C0: ODTRDCTL01 = 0x00000001
N4.C0: InitializeDdrioForTraining: cleff = 10
N6.C1.D1.R0: Rtt_wr = 120, Rtt_nom = 20
N0.C0: ODTWRCTL00 = 0x05000185
N4.C0: InitializeDdrioForTraining: cwleff = 8
N6.C1.D1.R1: Rtt_wr = 120, Rtt_nom = 0
N0.C0: ODTWRCTL01 = 0x00000009
N4.C0: InitializeDdrioForTraining: initial ddrInitIndexRx = 4 ddrInitIndexTx = 2
N6.C1: ODTRDCTL00 = 0x01000104
N0.C1: RdCmd2DataValidLatency = 20, (dlyFrmS = 15, clEff = 10, earlyCas = 0, selNTiming = 2)
N4.C0: InitializeDdrioForTraining: initial RdCmd2RcvEnLatency = 5
N6.C1: ODTRDCTL01 = 0x00000001
N0.C1: CLK0_CFG: 0x000FF330
N4.C0: InitializeDdrioForTraining: initial RdPtrOffsetRcvEn = 4
N6.C1: ODTWRCTL00 = 0x05000185
N0.C1: DDR_RANKCTL: 0x000FEA40
N4.C0: InitializeDdrioForTraining: initial rkrdptroffsetrcvenb = 6
N6.C1: ODTWRCTL01 = 0x00000009
N0.C1: MCODT = 0 ( 50 ohms)
N4.C0: InitializeDdrioForTraining: initial rkrdptroffsetdrvenrcvenb = 5
N6.C2: JCK cmd timing = 3N
N0.C1.D0.R0: Rtt_wr = 120, Rtt_nom = 20
N4.C0: InitializeDdrioForTraining: initial WrCmd2DqsStartLatency = 4
N6.C2: RdCmd2DataValidLatency = 20, (dlyFrmS = 15, clEff = 10, earlyCas = 0, selNTiming = 2)
N0.C1.D0.R1: Rtt_wr = 120, Rtt_nom = 0
N4.C0: InitializeDdrioForTraining: initial RdPtrOffsetDqs = 10
N6.C2: CLK0_CFG: 0x000FFF30
N0.C1.D1.R0: Rtt_wr = 120, Rtt_nom = 20
N4.C0: InitializeDdrioForTraining: initial RdCmd2RcvEnLatency = 5
N6.C2: DDR_RANKCTL: 0x000FEA40
N0.C1.D1.R1: Rtt_wr = 120, Rtt_nom = 0
N4.C0: InitializeDdrioForTraining: initial WrCmd2DqsStartLatency = 4
N6.C2: MCODT = 0 ( 50 ohms)
N0.C1: ODTRDCTL00 = 0x01000104
N4.C0: InitializeDdrioForTraining: initial RdPtrOffsetRcvEn = 4
N6.C2.D0.R0: Rtt_wr = 120, Rtt_nom = 20
N0.C1: ODTRDCTL01 = 0x00000001
N4.C0: InitializeDdrioForTraining: initial RdPtrOffsetDqs = 6
N6.C2.D0.R1: Rtt_wr = 120, Rtt_nom = 0
N0.C1: ODTWRCTL00 = 0x05000185
N4.C0: InitializeDdrioForTraining: initial RdPtrOffsetDq = 5
N6.C2.D1.R0: Rtt_wr = 120, Rtt_nom = 20
N0.C1: ODTWRCTL01 = 0x00000009
N4.C1: InitializeDdrioForTraining: cleff = 10
N6.C2.D1.R1: Rtt_wr = 120, Rtt_nom = 0
N0.C2: JCK cmd timing = 3N
N4.C1: InitializeDdrioForTraining: cwleff = 8
N6.C2: ODTRDCTL00 = 0x01000104
N0.C2: RdCmd2DataValidLatency = 20, (dlyFrmS = 15, clEff = 10, earlyCas = 0, selNTiming = 2)
N4.C1: InitializeDdrioForTraining: initial ddrInitIndexRx = 4 ddrInitIndexTx = 2
N6.C2: ODTRDCTL01 = 0x00000001
N0.C2: CLK0_CFG: 0x000FFF30
N4.C1: InitializeDdrioForTraining: initial RdCmd2RcvEnLatency = 5
N6.C2: ODTWRCTL00 = 0x05000185
N0.C2: DDR_RANKCTL: 0x000FEA40
N4.C1: InitializeDdrioForTraining: initial RdPtrOffsetRcvEn = 4
N6.C2: ODTWRCTL01 = 0x00000009
N0.C2: MCODT = 0 ( 50 ohms)
N4.C1: InitializeDdrioForTraining: initial rkrdptroffsetrcvenb = 6
N6.C3: RdCmd2DataValidLatency = 20, (dlyFrmS = 15, clEff = 10, earlyCas = 0, selNTiming = 2)
N0.C2.D0.R0: Rtt_wr = 120, Rtt_nom = 20
N4.C1: InitializeDdrioForTraining: initial rkrdptroffsetdrvenrcvenb = 5
N6.C3: CLK0_CFG: 0x000FF330
N0.C2.D0.R1: Rtt_wr = 120, Rtt_nom = 0
N4.C1: InitializeDdrioForTraining: initial WrCmd2DqsStartLatency = 4
N6.C3: DDR_RANKCTL: 0x000FEA40
N0.C2.D1.R0: Rtt_wr = 120, Rtt_nom = 20
N4.C1: InitializeDdrioForTraining: initial RdPtrOffsetDqs = 10
N6.C3: MCODT = 0 ( 50 ohms)
N0.C2.D1.R1: Rtt_wr = 120, Rtt_nom = 0
N4.C1: InitializeDdrioForTraining: initial RdCmd2RcvEnLatency = 5
N6.C3.D0.R0: Rtt_wr = 120, Rtt_nom = 20
N0.C2: ODTRDCTL00 = 0x01000104
N4.C1: InitializeDdrioForTraining: initial WrCmd2DqsStartLatency = 4
N6.C3.D0.R1: Rtt_wr = 120, Rtt_nom = 0
N0.C2: ODTRDCTL01 = 0x00000001
N4.C1: InitializeDdrioForTraining: initial RdPtrOffsetRcvEn = 4
N6.C3.D1.R0: Rtt_wr = 120, Rtt_nom = 20
N0.C2: ODTWRCTL00 = 0x05000185
N4.C1: InitializeDdrioForTraining: initial RdPtrOffsetDqs = 6
N6.C3.D1.R1: Rtt_wr = 120, Rtt_nom = 0
N0.C2: ODTWRCTL01 = 0x00000009
N4.C1: InitializeDdrioForTraining: initial RdPtrOffsetDq = 5
N6.C3: ODTRDCTL00 = 0x01000104
N0.C3: RdCmd2DataValidLatency = 20, (dlyFrmS = 15, clEff = 10, earlyCas = 0, selNTiming = 2)
N4.C2: InitializeDdrioForTraining: cleff = 10
N6.C3: ODTRDCTL01 = 0x00000001
N0.C3: CLK0_CFG: 0x000FF330
N4.C2: InitializeDdrioForTraining: cwleff = 8
N6.C3: ODTWRCTL00 = 0x05000185
N0.C3: DDR_RANKCTL: 0x000FEA40
N4.C2: InitializeDdrioForTraining: initial ddrInitIndexRx = 4 ddrInitIndexTx = 2
N6.C3: ODTWRCTL01 = 0x00000009
N0.C3: MCODT = 0 ( 50 ohms)
N4.C2: InitializeDdrioForTraining: initial RdCmd2RcvEnLatency = 5
N6.C0.D0: PreDdrTraining: Program dimmmtr 0xC502D
N0.C3.D0.R0: Rtt_wr = 120, Rtt_nom = 20
N4.C2: InitializeDdrioForTraining: initial RdPtrOffsetRcvEn = 4
N6.C0.D1: PreDdrTraining: Program dimmmtr 0xC502D
N0.C3.D0.R1: Rtt_wr = 120, Rtt_nom = 0
N4.C2: InitializeDdrioForTraining: initial rkrdptroffsetrcvenb = 6
N6.C1.D0: PreDdrTraining: Program dimmmtr 0xC502D
N0.C3.D1.R0: Rtt_wr = 120, Rtt_nom = 20
N4.C2: InitializeDdrioForTraining: initial rkrdptroffsetdrvenrcvenb = 5
N6.C1.D1: PreDdrTraining: Program dimmmtr 0xC502D
N0.C3.D1.R1: Rtt_wr = 120, Rtt_nom = 0
N4.C2: InitializeDdrioForTraining: initial WrCmd2DqsStartLatency = 4
N6.C2.D0: PreDdrTraining: Program dimmmtr 0xC502D
N0.C3: ODTRDCTL00 = 0x01000104
N4.C2: InitializeDdrioForTraining: initial RdPtrOffsetDqs = 10
N6.C2.D1: PreDdrTraining: Program dimmmtr 0xC502D
N0.C3: ODTRDCTL01 = 0x00000001
N4.C2: InitializeDdrioForTraining: initial RdCmd2RcvEnLatency = 5
N6.C3.D0: PreDdrTraining: Program dimmmtr 0xC502D
N0.C3: ODTWRCTL00 = 0x05000185
N4.C2: InitializeDdrioForTraining: initial WrCmd2DqsStartLatency = 4
N6.C3.D1: PreDdrTraining: Program dimmmtr 0xC502D
N0.C3: ODTWRCTL01 = 0x00000009
N4.C2: InitializeDdrioForTraining: initial RdPtrOffsetRcvEn = 4
N6: InitializeDdrioForUse
N0.C0.D0: PreDdrTraining: Program dimmmtr 0xC502D
N4.C2: InitializeDdrioForTraining: initial RdPtrOffsetDqs = 6
N6: SetupJckForBL: setting BL to 8
N0.C0.D1: PreDdrTraining: Program dimmmtr 0xC502D
N4.C2: InitializeDdrioForTraining: initial RdPtrOffsetDq = 5
N6.C0: ODTTIMCTL (INIT RELAX) rdwidth = 10 rddly = 0 wrwidth = 8 wrdly = 0
N0.C1.D0: PreDdrTraining: Program dimmmtr 0xC502D
N4.C3: InitializeDdrioForTraining: cleff = 10
N6.C1: ODTTIMCTL (INIT RELAX) rdwidth = 10 rddly = 0 wrwidth = 8 wrdly = 0
N0.C1.D1: PreDdrTraining: Program dimmmtr 0xC502D
N4.C3: InitializeDdrioForTraining: cwleff = 8
N6.C2: ODTTIMCTL (INIT RELAX) rdwidth = 10 rddly = 0 wrwidth = 8 wrdly = 0
N0.C2.D0: PreDdrTraining: Program dimmmtr 0xC502D
N4.C3: InitializeDdrioForTraining: initial ddrInitIndexRx = 4 ddrInitIndexTx = 2
N6.C3: ODTTIMCTL (INIT RELAX) rdwidth = 10 rddly = 0 wrwidth = 8 wrdly = 0
N0.C2.D1: PreDdrTraining: Program dimmmtr 0xC502D
N4.C3: InitializeDdrioForTraining: initial RdCmd2RcvEnLatency = 5
N6: JckDdrTraining
N0.C3.D0: PreDdrTraining: Program dimmmtr 0xC502D
N4.C3: InitializeDdrioForTraining: initial RdPtrOffsetRcvEn = 4
N6: InitializeDdrioForTraining: QCRM Disabled
N0.C3.D1: PreDdrTraining: Program dimmmtr 0xC502D
N4.C3: InitializeDdrioForTraining: initial rkrdptroffsetrcvenb = 6
N6.C0: InitializeDdrioForTraining: cleff = 10
N0: InitializeDdrioForUse
N4.C3: InitializeDdrioForTraining: initial rkrdptroffsetdrvenrcvenb = 5
N6.C0: InitializeDdrioForTraining: cwleff = 8
N0: SetupJckForBL: setting BL to 8
N4.C3: InitializeDdrioForTraining: initial WrCmd2DqsStartLatency = 4
N6.C0: InitializeDdrioForTraining: initial ddrInitIndexRx = 4 ddrInitIndexTx = 2
N0.C0: ODTTIMCTL (INIT RELAX) rdwidth = 10 rddly = 0 wrwidth = 8 wrdly = 0
N4.C3: InitializeDdrioForTraining: initial RdPtrOffsetDqs = 10
N6.C0: InitializeDdrioForTraining: initial RdCmd2RcvEnLatency = 5
N0.C1: ODTTIMCTL (INIT RELAX) rdwidth = 10 rddly = 0 wrwidth = 8 wrdly = 0
N4.C3: InitializeDdrioForTraining: initial RdCmd2RcvEnLatency = 5
N6.C0: InitializeDdrioForTraining: initial RdPtrOffsetRcvEn = 4
N0.C2: ODTTIMCTL (INIT RELAX) rdwidth = 10 rddly = 0 wrwidth = 8 wrdly = 0
N4.C3: InitializeDdrioForTraining: initial WrCmd2DqsStartLatency = 4
N6.C0: InitializeDdrioForTraining: initial rkrdptroffsetrcvenb = 6
N0.C3: ODTTIMCTL (INIT RELAX) rdwidth = 10 rddly = 0 wrwidth = 8 wrdly = 0
N4.C3: InitializeDdrioForTraining: initial RdPtrOffsetRcvEn = 4
N6.C0: InitializeDdrioForTraining: initial rkrdptroffsetdrvenrcvenb = 5
N0: JckDdrTraining
N4.C3: InitializeDdrioForTraining: initial RdPtrOffsetDqs = 6
N6.C0: InitializeDdrioForTraining: initial WrCmd2DqsStartLatency = 4
N0: InitializeDdrioForTraining: QCRM Disabled
N4.C3: InitializeDdrioForTraining: initial RdPtrOffsetDq = 5
N6.C0: InitializeDdrioForTraining: initial RdPtrOffsetDqs = 10
N0.C0: InitializeDdrioForTraining: cleff = 10
N4: DdrClockStopWa
N6.C0: InitializeDdrioForTraining: initial RdCmd2RcvEnLatency = 5
N0.C0: InitializeDdrioForTraining: cwleff = 8
N4: JckSetOdtRelaxTiming:
N6.C0: InitializeDdrioForTraining: initial WrCmd2DqsStartLatency = 4
N0.C0: InitializeDdrioForTraining: initial ddrInitIndexRx = 4 ddrInitIndexTx = 2
N4.C0: ODTTIMCTL (INIT RELAX) rdwidth = 10 rddly = 0 wrwidth = 8 wrdly = 0
N6.C0: InitializeDdrioForTraining: initial RdPtrOffsetRcvEn = 4
N0.C0: InitializeDdrioForTraining: initial RdCmd2RcvEnLatency = 5
N4.C0.S00: DDRIOHSIODATA0_LATCTL1 = 08040804
N6.C0: InitializeDdrioForTraining: initial RdPtrOffsetDqs = 6
N0.C0: InitializeDdrioForTraining: initial RdPtrOffsetRcvEn = 4
N4.C0.S01: DDRIOHSIODATA0_LATCTL1 = 08040804
N6.C0: InitializeDdrioForTraining: initial RdPtrOffsetDq = 5
N0.C0: InitializeDdrioForTraining: initial rkrdptroffsetrcvenb = 6
N4.C0.S02: DDRIOHSIODATA0_LATCTL1 = 08040804
N6.C1: InitializeDdrioForTraining: cleff = 10
N0.C0: InitializeDdrioForTraining: initial rkrdptroffsetdrvenrcvenb = 5
N4.C0.S03: DDRIOHSIODATA0_LATCTL1 = 08040804
N6.C1: InitializeDdrioForTraining: cwleff = 8
N0.C0: InitializeDdrioForTraining: initial WrCmd2DqsStartLatency = 4
N4.C0.S04: DDRIOHSIODATA0_LATCTL1 = 08040804
N6.C1: InitializeDdrioForTraining: initial ddrInitIndexRx = 4 ddrInitIndexTx = 2
N0.C0: InitializeDdrioForTraining: initial RdPtrOffsetDqs = 10
N4.C0.S05: DDRIOHSIODATA0_LATCTL1 = 08040804
N6.C1: InitializeDdrioForTraining: initial RdCmd2RcvEnLatency = 5
N0.C0: InitializeDdrioForTraining: initial RdCmd2RcvEnLatency = 5
N4.C0.S06: DDRIOHSIODATA0_LATCTL1 = 08040804
N6.C1: InitializeDdrioForTraining: initial RdPtrOffsetRcvEn = 4
N0.C0: InitializeDdrioForTraining: initial WrCmd2DqsStartLatency = 4
N4.C0.S07: DDRIOHSIODATA0_LATCTL1 = 08040804
N6.C1: InitializeDdrioForTraining: initial rkrdptroffsetrcvenb = 6
N0.C0: InitializeDdrioForTraining: initial RdPtrOffsetRcvEn = 4
N4.C0.S08: DDRIOHSIODATA0_LATCTL1 = 08040804
N6.C1: InitializeDdrioForTraining: initial rkrdptroffsetdrvenrcvenb = 5
N0.C0: InitializeDdrioForTraining: initial RdPtrOffsetDqs = 6
N4.C1: ODTTIMCTL (INIT RELAX) rdwidth = 10 rddly = 0 wrwidth = 8 wrdly = 0
N6.C1: InitializeDdrioForTraining: initial WrCmd2DqsStartLatency = 4
N0.C0: InitializeDdrioForTraining: initial RdPtrOffsetDq = 5
N4.C1.S00: DDRIOHSIODATA0_LATCTL1 = 08040804
N6.C1: InitializeDdrioForTraining: initial RdPtrOffsetDqs = 10
N0.C1: InitializeDdrioForTraining: cleff = 10
N4.C1.S01: DDRIOHSIODATA0_LATCTL1 = 08040804
N6.C1: InitializeDdrioForTraining: initial RdCmd2RcvEnLatency = 5
N0.C1: InitializeDdrioForTraining: cwleff = 8
N4.C1.S02: DDRIOHSIODATA0_LATCTL1 = 08040804
N6.C1: InitializeDdrioForTraining: initial WrCmd2DqsStartLatency = 4
N0.C1: InitializeDdrioForTraining: initial ddrInitIndexRx = 4 ddrInitIndexTx = 2
N4.C1.S03: DDRIOHSIODATA0_LATCTL1 = 08040804
N6.C1: InitializeDdrioForTraining: initial RdPtrOffsetRcvEn = 4
N0.C1: InitializeDdrioForTraining: initial RdCmd2RcvEnLatency = 5
N4.C1.S04: DDRIOHSIODATA0_LATCTL1 = 08040804
N6.C1: InitializeDdrioForTraining: initial RdPtrOffsetDqs = 6
N0.C1: InitializeDdrioForTraining: initial RdPtrOffsetRcvEn = 4
N4.C1.S05: DDRIOHSIODATA0_LATCTL1 = 08040804
N6.C1: InitializeDdrioForTraining: initial RdPtrOffsetDq = 5
N0.C1: InitializeDdrioForTraining: initial rkrdptroffsetrcvenb = 6
N4.C1.S06: DDRIOHSIODATA0_LATCTL1 = 08040804
N6.C2: InitializeDdrioForTraining: cleff = 10
N0.C1: InitializeDdrioForTraining: initial rkrdptroffsetdrvenrcvenb = 5
N4.C1.S07: DDRIOHSIODATA0_LATCTL1 = 08040804
N6.C2: InitializeDdrioForTraining: cwleff = 8
N0.C1: InitializeDdrioForTraining: initial WrCmd2DqsStartLatency = 4
N4.C1.S08: DDRIOHSIODATA0_LATCTL1 = 08040804
N6.C2: InitializeDdrioForTraining: initial ddrInitIndexRx = 4 ddrInitIndexTx = 2
N0.C1: InitializeDdrioForTraining: initial RdPtrOffsetDqs = 10
N4.C2: ODTTIMCTL (INIT RELAX) rdwidth = 10 rddly = 0 wrwidth = 8 wrdly = 0
N6.C2: InitializeDdrioForTraining: initial RdCmd2RcvEnLatency = 5
N0.C1: InitializeDdrioForTraining: initial RdCmd2RcvEnLatency = 5
N4.C2.S00: DDRIOHSIODATA0_LATCTL1 = 08040804
N6.C2: InitializeDdrioForTraining: initial RdPtrOffsetRcvEn = 4
N0.C1: InitializeDdrioForTraining: initial WrCmd2DqsStartLatency = 4
N4.C2.S01: DDRIOHSIODATA0_LATCTL1 = 08040804
N6.C2: InitializeDdrioForTraining: initial rkrdptroffsetrcvenb = 6
N0.C1: InitializeDdrioForTraining: initial RdPtrOffsetRcvEn = 4
N4.C2.S02: DDRIOHSIODATA0_LATCTL1 = 08040804
N6.C2: InitializeDdrioForTraining: initial rkrdptroffsetdrvenrcvenb = 5
N0.C1: InitializeDdrioForTraining: initial RdPtrOffsetDqs = 6
N4.C2.S03: DDRIOHSIODATA0_LATCTL1 = 08040804
N6.C2: InitializeDdrioForTraining: initial WrCmd2DqsStartLatency = 4
N0.C1: InitializeDdrioForTraining: initial RdPtrOffsetDq = 5
N4.C2.S04: DDRIOHSIODATA0_LATCTL1 = 08040804
N6.C2: InitializeDdrioForTraining: initial RdPtrOffsetDqs = 10
N0.C2: InitializeDdrioForTraining: cleff = 10
N4.C2.S05: DDRIOHSIODATA0_LATCTL1 = 08040804
N6.C2: InitializeDdrioForTraining: initial RdCmd2RcvEnLatency = 5
N0.C2: InitializeDdrioForTraining: cwleff = 8
N4.C2.S06: DDRIOHSIODATA0_LATCTL1 = 08040804
N6.C2: InitializeDdrioForTraining: initial WrCmd2DqsStartLatency = 4
N0.C2: InitializeDdrioForTraining: initial ddrInitIndexRx = 4 ddrInitIndexTx = 2
N4.C2.S07: DDRIOHSIODATA0_LATCTL1 = 08040804
N6.C2: InitializeDdrioForTraining: initial RdPtrOffsetRcvEn = 4
N0.C2: InitializeDdrioForTraining: initial RdCmd2RcvEnLatency = 5
N4.C2.S08: DDRIOHSIODATA0_LATCTL1 = 08040804
N6.C2: InitializeDdrioForTraining: initial RdPtrOffsetDqs = 6
N0.C2: InitializeDdrioForTraining: initial RdPtrOffsetRcvEn = 4
N4.C3: ODTTIMCTL (INIT RELAX) rdwidth = 10 rddly = 0 wrwidth = 8 wrdly = 0
N6.C2: InitializeDdrioForTraining: initial RdPtrOffsetDq = 5
N0.C2: InitializeDdrioForTraining: initial rkrdptroffsetrcvenb = 6
N4.C3.S00: DDRIOHSIODATA0_LATCTL1 = 08040804
N6.C3: InitializeDdrioForTraining: cleff = 10
N0.C2: InitializeDdrioForTraining: initial rkrdptroffsetdrvenrcvenb = 5
N4.C3.S01: DDRIOHSIODATA0_LATCTL1 = 08040804
N6.C3: InitializeDdrioForTraining: cwleff = 8
N0.C2: InitializeDdrioForTraining: initial WrCmd2DqsStartLatency = 4
N4.C3.S02: DDRIOHSIODATA0_LATCTL1 = 08040804
N6.C3: InitializeDdrioForTraining: initial ddrInitIndexRx = 4 ddrInitIndexTx = 2
N0.C2: InitializeDdrioForTraining: initial RdPtrOffsetDqs = 10
N4.C3.S03: DDRIOHSIODATA0_LATCTL1 = 08040804
N6.C3: InitializeDdrioForTraining: initial RdCmd2RcvEnLatency = 5
N0.C2: InitializeDdrioForTraining: initial RdCmd2RcvEnLatency = 5
N4.C3.S04: DDRIOHSIODATA0_LATCTL1 = 08040804
N6.C3: InitializeDdrioForTraining: initial RdPtrOffsetRcvEn = 4
N0.C2: InitializeDdrioForTraining: initial WrCmd2DqsStartLatency = 4
N4.C3.S05: DDRIOHSIODATA0_LATCTL1 = 08040804
N6.C3: InitializeDdrioForTraining: initial rkrdptroffsetrcvenb = 6
N0.C2: InitializeDdrioForTraining: initial RdPtrOffsetRcvEn = 4
N4.C3.S06: DDRIOHSIODATA0_LATCTL1 = 08040804
N6.C3: InitializeDdrioForTraining: initial rkrdptroffsetdrvenrcvenb = 5
N0.C2: InitializeDdrioForTraining: initial RdPtrOffsetDqs = 6
N4.C3.S07: DDRIOHSIODATA0_LATCTL1 = 08040804
N6.C3: InitializeDdrioForTraining: initial WrCmd2DqsStartLatency = 4
N0.C2: InitializeDdrioForTraining: initial RdPtrOffsetDq = 5
N4.C3.S08: DDRIOHSIODATA0_LATCTL1 = 08040804
N6.C3: InitializeDdrioForTraining: initial RdPtrOffsetDqs = 10
N0.C3: InitializeDdrioForTraining: cleff = 10

START - Early Command Training
N6.C3: InitializeDdrioForTraining: initial RdCmd2RcvEnLatency = 5
N0.C3: InitializeDdrioForTraining: cwleff = 8
N4.C0: DDRIOHSIODATA0_LATCTL1 = 08040804
N6.C3: InitializeDdrioForTraining: initial WrCmd2DqsStartLatency = 4
N0.C3: InitializeDdrioForTraining: initial ddrInitIndexRx = 4 ddrInitIndexTx = 2
N4.C0: RdCmd2DataValidLatency = 20, (dlyFrmS = 15, clEff = 10, earlyCas = 0, selNTiming = 2)
N6.C3: InitializeDdrioForTraining: initial RdPtrOffsetRcvEn = 4
N0.C3: InitializeDdrioForTraining: initial RdCmd2RcvEnLatency = 5
N4.C0: SettingForTrainingStep: RdCmd2RcvEnLatency = 5
N6.C3: InitializeDdrioForTraining: initial RdPtrOffsetDqs = 6
N0.C3: InitializeDdrioForTraining: initial RdPtrOffsetRcvEn = 4
N4.C0: SettingForTrainingStep: Programming 7 tick initial value to CTL signals
N6.C3: InitializeDdrioForTraining: initial RdPtrOffsetDq = 5
N0.C3: InitializeDdrioForTraining: initial rkrdptroffsetrcvenb = 6
N4.C1: DDRIOHSIODATA0_LATCTL1 = 08040804
N6: DdrClockStopWa
N0.C3: InitializeDdrioForTraining: initial rkrdptroffsetdrvenrcvenb = 5
N4.C1: RdCmd2DataValidLatency = 20, (dlyFrmS = 15, clEff = 10, earlyCas = 0, selNTiming = 2)
N6: JckSetOdtRelaxTiming:
N0.C3: InitializeDdrioForTraining: initial WrCmd2DqsStartLatency = 4
N4.C1: SettingForTrainingStep: RdCmd2RcvEnLatency = 5
N6.C0: ODTTIMCTL (INIT RELAX) rdwidth = 10 rddly = 0 wrwidth = 8 wrdly = 0
N0.C3: InitializeDdrioForTraining: initial RdPtrOffsetDqs = 10
N4.C1: SettingForTrainingStep: Programming 10 tick initial value to CTL signals
N6.C0.S00: DDRIOHSIODATA0_LATCTL1 = 08040804
N0.C3: InitializeDdrioForTraining: initial RdCmd2RcvEnLatency = 5
N4.C2: DDRIOHSIODATA0_LATCTL1 = 08040804
N6.C0.S01: DDRIOHSIODATA0_LATCTL1 = 08040804
N0.C3: InitializeDdrioForTraining: initial WrCmd2DqsStartLatency = 4
N4.C2: RdCmd2DataValidLatency = 20, (dlyFrmS = 15, clEff = 10, earlyCas = 0, selNTiming = 2)
N6.C0.S02: DDRIOHSIODATA0_LATCTL1 = 08040804
N0.C3: InitializeDdrioForTraining: initial RdPtrOffsetRcvEn = 4
N4.C2: SettingForTrainingStep: RdCmd2RcvEnLatency = 5
N6.C0.S03: DDRIOHSIODATA0_LATCTL1 = 08040804
N0.C3: InitializeDdrioForTraining: initial RdPtrOffsetDqs = 6
N4.C2: SettingForTrainingStep: Programming 7 tick initial value to CTL signals
N6.C0.S04: DDRIOHSIODATA0_LATCTL1 = 08040804
N0.C3: InitializeDdrioForTraining: initial RdPtrOffsetDq = 5
N4.C3: DDRIOHSIODATA0_LATCTL1 = 08040804
N6.C0.S05: DDRIOHSIODATA0_LATCTL1 = 08040804
N0: DdrClockStopWa
N4.C3: RdCmd2DataValidLatency = 20, (dlyFrmS = 15, clEff = 10, earlyCas = 0, selNTiming = 2)
N6.C0.S06: DDRIOHSIODATA0_LATCTL1 = 08040804
N0: JckSetOdtRelaxTiming:
N4.C3: SettingForTrainingStep: RdCmd2RcvEnLatency = 5
N6.C0.S07: DDRIOHSIODATA0_LATCTL1 = 08040804
N0.C0: ODTTIMCTL (INIT RELAX) rdwidth = 10 rddly = 0 wrwidth = 8 wrdly = 0
N4.C3: SettingForTrainingStep: Programming 10 tick initial value to CTL signals
N6.C0.S08: DDRIOHSIODATA0_LATCTL1 = 08040804
N0.C0.S00: DDRIOHSIODATA0_LATCTL1 = 08040804
N4: FSM Basic Clock Training
N6.C1: ODTTIMCTL (INIT RELAX) rdwidth = 10 rddly = 0 wrwidth = 8 wrdly = 0
N0.C0.S01: DDRIOHSIODATA0_LATCTL1 = 08040804
N4.C0: JCK cmd timing = 1N
N6.C1.S00: DDRIOHSIODATA0_LATCTL1 = 08040804
N0.C0.S02: DDRIOHSIODATA0_LATCTL1 = 08040804
N4.C0: RdCmd2DataValidLatency = 21, (dlyFrmS = 15, clEff = 10, earlyCas = 0, selNTiming = 0)
N6.C1.S01: DDRIOHSIODATA0_LATCTL1 = 08040804
N0.C0.S03: DDRIOHSIODATA0_LATCTL1 = 08040804
N4.C1: RdCmd2DataValidLatency = 21, (dlyFrmS = 15, clEff = 10, earlyCas = 0, selNTiming = 0)
N6.C1.S02: DDRIOHSIODATA0_LATCTL1 = 08040804
N0.C0.S04: DDRIOHSIODATA0_LATCTL1 = 08040804
N4.C2: JCK cmd timing = 1N
N6.C1.S03: DDRIOHSIODATA0_LATCTL1 = 08040804
N0.C0.S05: DDRIOHSIODATA0_LATCTL1 = 08040804
N4.C2: RdCmd2DataValidLatency = 21, (dlyFrmS = 15, clEff = 10, earlyCas = 0, selNTiming = 0)
N6.C1.S04: DDRIOHSIODATA0_LATCTL1 = 08040804
N0.C0.S06: DDRIOHSIODATA0_LATCTL1 = 08040804
N4.C3: RdCmd2DataValidLatency = 21, (dlyFrmS = 15, clEff = 10, earlyCas = 0, selNTiming = 0)
N6.C1.S05: DDRIOHSIODATA0_LATCTL1 = 08040804
N0.C0.S07: DDRIOHSIODATA0_LATCTL1 = 08040804
N6.C1.S06: DDRIOHSIODATA0_LATCTL1 = 08040804
N0.C0.S08: DDRIOHSIODATA0_LATCTL1 = 08040804
N6.C1.S07: DDRIOHSIODATA0_LATCTL1 = 08040804
N0.C1: ODTTIMCTL (INIT RELAX) rdwidth = 10 rddly = 0 wrwidth = 8 wrdly = 0
N6.C1.S08: DDRIOHSIODATA0_LATCTL1 = 08040804
N0.C1.S00: DDRIOHSIODATA0_LATCTL1 = 08040804
N6.C2: ODTTIMCTL (INIT RELAX) rdwidth = 10 rddly = 0 wrwidth = 8 wrdly = 0
N0.C1.S01: DDRIOHSIODATA0_LATCTL1 = 08040804
N6.C2.S00: DDRIOHSIODATA0_LATCTL1 = 08040804
N0.C1.S02: DDRIOHSIODATA0_LATCTL1 = 08040804
N6.C2.S01: DDRIOHSIODATA0_LATCTL1 = 08040804
N0.C1.S03: DDRIOHSIODATA0_LATCTL1 = 08040804
N6.C2.S02: DDRIOHSIODATA0_LATCTL1 = 08040804
N0.C1.S04: DDRIOHSIODATA0_LATCTL1 = 08040804
N6.C2.S03: DDRIOHSIODATA0_LATCTL1 = 08040804
N0.C1.S05: DDRIOHSIODATA0_LATCTL1 = 08040804
N6.C2.S04: DDRIOHSIODATA0_LATCTL1 = 08040804
N0.C1.S06: DDRIOHSIODATA0_LATCTL1 = 08040804
N6.C2.S05: DDRIOHSIODATA0_LATCTL1 = 08040804
N0.C1.S07: DDRIOHSIODATA0_LATCTL1 = 08040804
N6.C2.S06: DDRIOHSIODATA0_LATCTL1 = 08040804
N0.C1.S08: DDRIOHSIODATA0_LATCTL1 = 08040804
N6.C2.S07: DDRIOHSIODATA0_LATCTL1 = 08040804
N0.C2: ODTTIMCTL (INIT RELAX) rdwidth = 10 rddly = 0 wrwidth = 8 wrdly = 0
N6.C2.S08: DDRIOHSIODATA0_LATCTL1 = 08040804
N0.C2.S00: DDRIOHSIODATA0_LATCTL1 = 08040804
N6.C3: ODTTIMCTL (INIT RELAX) rdwidth = 10 rddly = 0 wrwidth = 8 wrdly = 0
N0.C2.S01: DDRIOHSIODATA0_LATCTL1 = 08040804
N6.C3.S00: DDRIOHSIODATA0_LATCTL1 = 08040804
N0.C2.S02: DDRIOHSIODATA0_LATCTL1 = 08040804
N6.C3.S01: DDRIOHSIODATA0_LATCTL1 = 08040804
N0.C2.S03: DDRIOHSIODATA0_LATCTL1 = 08040804
N6.C3.S02: DDRIOHSIODATA0_LATCTL1 = 08040804
N0.C2.S04: DDRIOHSIODATA0_LATCTL1 = 08040804
N6.C3.S03: DDRIOHSIODATA0_LATCTL1 = 08040804
N0.C2.S05: DDRIOHSIODATA0_LATCTL1 = 08040804
N6.C3.S04: DDRIOHSIODATA0_LATCTL1 = 08040804
N0.C2.S06: DDRIOHSIODATA0_LATCTL1 = 08040804
N6.C3.S05: DDRIOHSIODATA0_LATCTL1 = 08040804
N0.C2.S07: DDRIOHSIODATA0_LATCTL1 = 08040804
N6.C3.S06: DDRIOHSIODATA0_LATCTL1 = 08040804
N0.C2.S08: DDRIOHSIODATA0_LATCTL1 = 08040804
N6.C3.S07: DDRIOHSIODATA0_LATCTL1 = 08040804
N0.C3: ODTTIMCTL (INIT RELAX) rdwidth = 10 rddly = 0 wrwidth = 8 wrdly = 0
N6.C3.S08: DDRIOHSIODATA0_LATCTL1 = 08040804
N0.C3.S00: DDRIOHSIODATA0_LATCTL1 = 08040804

START - Early Command Training
N0.C3.S01: DDRIOHSIODATA0_LATCTL1 = 08040804
N6.C0: DDRIOHSIODATA0_LATCTL1 = 08040804
N0.C3.S02: DDRIOHSIODATA0_LATCTL1 = 08040804
N6.C0: RdCmd2DataValidLatency = 20, (dlyFrmS = 15, clEff = 10, earlyCas = 0, selNTiming = 2)
N0.C3.S03: DDRIOHSIODATA0_LATCTL1 = 08040804
N6.C0: SettingForTrainingStep: RdCmd2RcvEnLatency = 5
N0.C3.S04: DDRIOHSIODATA0_LATCTL1 = 08040804
N6.C0: SettingForTrainingStep: Programming 7 tick initial value to CTL signals
N0.C3.S05: DDRIOHSIODATA0_LATCTL1 = 08040804
N6.C1: DDRIOHSIODATA0_LATCTL1 = 08040804
N0.C3.S06: DDRIOHSIODATA0_LATCTL1 = 08040804
N6.C1: RdCmd2DataValidLatency = 20, (dlyFrmS = 15, clEff = 10, earlyCas = 0, selNTiming = 2)
N0.C3.S07: DDRIOHSIODATA0_LATCTL1 = 08040804
N6.C1: SettingForTrainingStep: RdCmd2RcvEnLatency = 5
N0.C3.S08: DDRIOHSIODATA0_LATCTL1 = 08040804
N6.C1: SettingForTrainingStep: Programming 10 tick initial value to CTL signals

START - Early Command Training
N6.C2: DDRIOHSIODATA0_LATCTL1 = 08040804
Checkpoint Code: Socket 0, 0xB7, 0x00, 0x0000
N6.C2: RdCmd2DataValidLatency = 20, (dlyFrmS = 15, clEff = 10, earlyCas = 0, selNTiming = 2)
N0.C0: DDRIOHSIODATA0_LATCTL1 = 08040804
N6.C2: SettingForTrainingStep: RdCmd2RcvEnLatency = 5
N0.C0: RdCmd2DataValidLatency = 20, (dlyFrmS = 15, clEff = 10, earlyCas = 0, selNTiming = 2)
N6.C2: SettingForTrainingStep: Programming 7 tick initial value to CTL signals
N0.C0: SettingForTrainingStep: RdCmd2RcvEnLatency = 5
N6.C3: DDRIOHSIODATA0_LATCTL1 = 08040804
N0.C0: SettingForTrainingStep: Programming 7 tick initial value to CTL signals
N6.C3: RdCmd2DataValidLatency = 20, (dlyFrmS = 15, clEff = 10, earlyCas = 0, selNTiming = 2)
N0.C1: DDRIOHSIODATA0_LATCTL1 = 08040804
N2.C0.D0: CalcFinalClock(90,121) = 22
N6.C3: SettingForTrainingStep: RdCmd2RcvEnLatency = 5
N0.C1: RdCmd2DataValidLatency = 20, (dlyFrmS = 15, clEff = 10, earlyCas = 0, selNTiming = 2)
N2.C0.D1: CalcFinalClock(99,113) = 27
N6.C3: SettingForTrainingStep: Programming 10 tick initial value to CTL signals
N0.C1: SettingForTrainingStep: RdCmd2RcvEnLatency = 5
N2.C1.D0: CalcFinalClock(94,112) = 22
N6: FSM Basic Clock Training
N0.C1: SettingForTrainingStep: Programming 10 tick initial value to CTL signals
N2.C1.D1: CalcFinalClock(100,118) = 31
N6.C0: JCK cmd timing = 1N
N0.C2: DDRIOHSIODATA0_LATCTL1 = 08040804
N6.C0: RdCmd2DataValidLatency = 21, (dlyFrmS = 15, clEff = 10, earlyCas = 0, selNTiming = 0)
N0.C2: RdCmd2DataValidLatency = 20, (dlyFrmS = 15, clEff = 10, earlyCas = 0, selNTiming = 2)
N2.C2.D0: CalcFinalClock(90,118) = 21
N6.C1: RdCmd2DataValidLatency = 21, (dlyFrmS = 15, clEff = 10, earlyCas = 0, selNTiming = 0)
N0.C2: SettingForTrainingStep: RdCmd2RcvEnLatency = 5
N2.C2.D1: CalcFinalClock(98,113) = 26
N6.C2: JCK cmd timing = 1N
N0.C2: SettingForTrainingStep: Programming 7 tick initial value to CTL signals
N2.C3.D0: CalcFinalClock(94,107) = 19
N6.C2: RdCmd2DataValidLatency = 21, (dlyFrmS = 15, clEff = 10, earlyCas = 0, selNTiming = 0)
N0.C3: DDRIOHSIODATA0_LATCTL1 = 08040804
N2.C3.D1: CalcFinalClock(95,118) = 26
N6.C3: RdCmd2DataValidLatency = 21, (dlyFrmS = 15, clEff = 10, earlyCas = 0, selNTiming = 0)
N0.C3: RdCmd2DataValidLatency = 20, (dlyFrmS = 15, clEff = 10, earlyCas = 0, selNTiming = 2)
N2.C0: JCK cmd timing = 3N
N0.C3: SettingForTrainingStep: RdCmd2RcvEnLatency = 5
N2.C0: RdCmd2DataValidLatency = 20, (dlyFrmS = 15, clEff = 10, earlyCas = 0, selNTiming = 2)
N0.C3: SettingForTrainingStep: Programming 10 tick initial value to CTL signals
N2.C1: RdCmd2DataValidLatency = 20, (dlyFrmS = 15, clEff = 10, earlyCas = 0, selNTiming = 2)
N0: FSM Basic Clock Training
N2.C2: JCK cmd timing = 3N
N0.C0: JCK cmd timing = 1N
N2.C2: RdCmd2DataValidLatency = 20, (dlyFrmS = 15, clEff = 10, earlyCas = 0, selNTiming = 2)
N0.C0: RdCmd2DataValidLatency = 21, (dlyFrmS = 15, clEff = 10, earlyCas = 0, selNTiming = 0)
N2.C3: RdCmd2DataValidLatency = 20, (dlyFrmS = 15, clEff = 10, earlyCas = 0, selNTiming = 2)
N0.C1: RdCmd2DataValidLatency = 21, (dlyFrmS = 15, clEff = 10, earlyCas = 0, selNTiming = 0)
N2: RunTrainStep: Final status = 0
N0.C2: JCK cmd timing = 1N

END - Early Command Training           Time         4143 ms
N0.C2: RdCmd2DataValidLatency = 21, (dlyFrmS = 15, clEff = 10, earlyCas = 0, selNTiming = 0)

START - Basic Read DQ/DQS Training
N0.C3: RdCmd2DataValidLatency = 21, (dlyFrmS = 15, clEff = 10, earlyCas = 0, selNTiming = 0)
N2.C0: RdCmd2DataValidLatency = 20, (dlyFrmS = 15, clEff = 10, earlyCas = 0, selNTiming = 2)
N2.C0: SettingForTrainingStep: RdCmd2RcvEnLatency = 5
N2.C1: RdCmd2DataValidLatency = 20, (dlyFrmS = 15, clEff = 10, earlyCas = 0, selNTiming = 2)
N2.C1: SettingForTrainingStep: RdCmd2RcvEnLatency = 5
N2.C2: RdCmd2DataValidLatency = 20, (dlyFrmS = 15, clEff = 10, earlyCas = 0, selNTiming = 2)
N2.C2: SettingForTrainingStep: RdCmd2RcvEnLatency = 5
N2.C3: RdCmd2DataValidLatency = 20, (dlyFrmS = 15, clEff = 10, earlyCas = 0, selNTiming = 2)
N2.C3: SettingForTrainingStep: RdCmd2RcvEnLatency = 5
N2.C0.D0.R0.S00: RdDqDqs FSM results: Left = 04, Right = 61, center = 32
N2.C0.D0.R0.S00: RxDqsDelay = 032
N2.C0.D0.R0.S01: RdDqDqs FSM results: Left = 06, Right = 58, center = 32
N2.C0.D0.R0.S01: RxDqsDelay = 032
N2.C0.D0.R0.S02: RdDqDqs FSM results: Left = 03, Right = 63, center = 33
N2.C0.D0.R0.S02: RxDqsDelay = 033
N2.C0.D0.R0.S03: RdDqDqs FSM results: Left = 06, Right = 61, center = 33
N2.C0.D0.R0.S03: RxDqsDelay = 033
N2.C0.D0.R0.S04: RdDqDqs FSM results: Left = 06, Right = 63, center = 34
N2.C0.D0.R0.S04: RxDqsDelay = 034
N2.C0.D0.R0.S05: RdDqDqs FSM results: Left = 06, Right = 63, center = 34
N2.C0.D0.R0.S05: RxDqsDelay = 034
N2.C0.D0.R0.S06: RdDqDqs FSM results: Left = 07, Right = 63, center = 35
N2.C0.D0.R0.S06: RxDqsDelay = 035
N2.C0.D0.R0.S07: RdDqDqs FSM results: Left = 05, Right = 63, center = 34
N2.C0.D0.R0.S07: RxDqsDelay = 034
N2.C0.D0.R0.S08: RdDqDqs FSM results: Left = 09, Right = 63, center = 36
N2.C0.D0.R0.S08: RxDqsDelay = 036
N2.C0.D0.R0.S09: RdDqDqs FSM results: Left = 05, Right = 60, center = 32
N2.C0.D0.R0.S09: RxDqsDelay = 032
N2.C0.D0.R0.S10: RdDqDqs FSM results: Left = 07, Right = 59, center = 33
N2.C0.D0.R0.S10: RxDqsDelay = 033
N2.C0.D0.R0.S11: RdDqDqs FSM results: Left = 05, Right = 63, center = 34
N2.C0.D0.R0.S11: RxDqsDelay = 034
N2.C0.D0.R0.S12: RdDqDqs FSM results: Left = 05, Right = 63, center = 34
N2.C0.D0.R0.S12: RxDqsDelay = 034
N2.C0.D0.R0.S13: RdDqDqs FSM results: Left = 04, Right = 63, center = 33
N2.C0.D0.R0.S13: RxDqsDelay = 033
N2.C0.D0.R0.S14: RdDqDqs FSM results: Left = 03, Right = 63, center = 33
N2.C0.D0.R0.S14: RxDqsDelay = 033
N2.C0.D0.R0.S15: RdDqDqs FSM results: Left = 04, Right = 63, center = 33
N2.C0.D0.R0.S15: RxDqsDelay = 033
N2.C0.D0.R0.S16: RdDqDqs FSM results: Left = 05, Right = 63, center = 34
N2.C0.D0.R0.S16: RxDqsDelay = 034
N2.C0.D0.R0.S17: RdDqDqs FSM results: Left = 08, Right = 60, center = 34
N2.C0.D0.R0.S17: RxDqsDelay = 034
N2.C0.D0.R1.S00: RdDqDqs FSM results: Left = 05, Right = 63, center = 34
N2.C0.D0.R1.S00: RxDqsDelay = 034
N2.C0.D0.R1.S01: RdDqDqs FSM results: Left = 06, Right = 63, center = 34
N2.C0.D0.R1.S01: RxDqsDelay = 034
N2.C0.D0.R1.S02: RdDqDqs FSM results: Left = 03, Right = 63, center = 33
N2.C0.D0.R1.S02: RxDqsDelay = 033
N2.C0.D0.R1.S03: RdDqDqs FSM results: Left = 07, Right = 63, center = 35
N2.C0.D0.R1.S03: RxDqsDelay = 035
N2.C0.D0.R1.S04: RdDqDqs FSM results: Left = 07, Right = 63, center = 35
N2.C0.D0.R1.S04: RxDqsDelay = 035
N2.C0.D0.R1.S05: RdDqDqs FSM results: Left = 05, Right = 63, center = 34
N2.C0.D0.R1.S05: RxDqsDelay = 034
N2.C0.D0.R1.S06: RdDqDqs FSM results: Left = 06, Right = 63, center = 34
N2.C0.D0.R1.S06: RxDqsDelay = 034
N2.C0.D0.R1.S07: RdDqDqs FSM results: Left = 06, Right = 63, center = 34
N2.C0.D0.R1.S07: RxDqsDelay = 034
N2.C0.D0.R1.S08: RdDqDqs FSM results: Left = 09, Right = 63, center = 36
N2.C0.D0.R1.S08: RxDqsDelay = 036
N2.C0.D0.R1.S09: RdDqDqs FSM results: Left = 04, Right = 63, center = 33
N2.C0.D0.R1.S09: RxDqsDelay = 033
N2.C0.D0.R1.S10: RdDqDqs FSM results: Left = 07, Right = 61, center = 34
N2.C0.D0.R1.S10: RxDqsDelay = 034
N2.C0.D0.R1.S11: RdDqDqs FSM results: Left = 04, Right = 63, center = 33
N2.C0.D0.R1.S11: RxDqsDelay = 033
N2.C0.D0.R1.S12: RdDqDqs FSM results: Left = 05, Right = 63, center = 34
N2.C0.D0.R1.S12: RxDqsDelay = 034
N2.C0.D0.R1.S13: RdDqDqs FSM results: Left = 04, Right = 63, center = 33
N2.C0.D0.R1.S13: RxDqsDelay = 033
N2.C0.D0.R1.S14: RdDqDqs FSM results: Left = 03, Right = 63, center = 33
N2.C0.D0.R1.S14: RxDqsDelay = 033
N2.C0.D0.R1.S15: RdDqDqs FSM results: Left = 05, Right = 63, center = 34
N2.C0.D0.R1.S15: RxDqsDelay = 034
N2.C0.D0.R1.S16: RdDqDqs FSM results: Left = 05, Right = 63, center = 34
N2.C0.D0.R1.S16: RxDqsDelay = 034
N2.C0.D0.R1.S17: RdDqDqs FSM results: Left = 07, Right = 61, center = 34
N2.C0.D0.R1.S17: RxDqsDelay = 034
N2.C0.D1.R0.S00: RdDqDqs FSM results: Left = 08, Right = 63, center = 35
N2.C0.D1.R0.S00: RxDqsDelay = 035
N2.C0.D1.R0.S01: RdDqDqs FSM results: Left = 09, Right = 63, center = 36
N2.C0.D1.R0.S01: RxDqsDelay = 036
N2.C0.D1.R0.S02: RdDqDqs FSM results: Left = 07, Right = 63, center = 35
N2.C0.D1.R0.S02: RxDqsDelay = 035
N2.C0.D1.R0.S03: RdDqDqs FSM results: Left = 09, Right = 63, center = 36
N2.C0.D1.R0.S03: RxDqsDelay = 036
N2.C0.D1.R0.S04: RdDqDqs FSM results: Left = 10, Right = 63, center = 36
N2.C0.D1.R0.S04: RxDqsDelay = 036
N2.C0.D1.R0.S05: RdDqDqs FSM results: Left = 08, Right = 63, center = 35
N2.C0.D1.R0.S05: RxDqsDelay = 035
N2.C0.D1.R0.S06: RdDqDqs FSM results: Left = 10, Right = 63, center = 36
N2.C0.D1.R0.S06: RxDqsDelay = 036
N2.C0.D1.R0.S07: RdDqDqs FSM results: Left = 09, Right = 63, center = 36
N2.C0.D1.R0.S07: RxDqsDelay = 036
N2.C0.D1.R0.S08: RdDqDqs FSM results: Left = 11, Right = 63, center = 37
N2.C0.D1.R0.S08: RxDqsDelay = 037
N2.C0.D1.R0.S09: RdDqDqs FSM results: Left = 08, Right = 63, center = 35
N2.C0.D1.R0.S09: RxDqsDelay = 035
N2.C0.D1.R0.S10: RdDqDqs FSM results: Left = 10, Right = 63, center = 36
N2.C0.D1.R0.S10: RxDqsDelay = 036
N2.C0.D1.R0.S11: RdDqDqs FSM results: Left = 08, Right = 63, center = 35
N2.C0.D1.R0.S11: RxDqsDelay = 035
N2.C0.D1.R0.S12: RdDqDqs FSM results: Left = 08, Right = 63, center = 35
N2.C0.D1.R0.S12: RxDqsDelay = 035
N2.C0.D1.R0.S13: RdDqDqs FSM results: Left = 08, Right = 63, center = 35
N2.C0.D1.R0.S13: RxDqsDelay = 035
N2.C0.D1.R0.S14: RdDqDqs FSM results: Left = 06, Right = 63, center = 34
N2.C0.D1.R0.S14: RxDqsDelay = 034
N2.C0.D1.R0.S15: RdDqDqs FSM results: Left = 08, Right = 63, center = 35
N2.C0.D1.R0.S15: RxDqsDelay = 035
N2.C0.D1.R0.S16: RdDqDqs FSM results: Left = 08, Right = 63, center = 35
N2.C0.D1.R0.S16: RxDqsDelay = 035
N2.C0.D1.R0.S17: RdDqDqs FSM results: Left = 10, Right = 63, center = 36
N2.C0.D1.R0.S17: RxDqsDelay = 036
N2.C0.D1.R1.S00: RdDqDqs FSM results: Left = 09, Right = 63, center = 36
N2.C0.D1.R1.S00: RxDqsDelay = 036
N2.C0.D1.R1.S01: RdDqDqs FSM results: Left = 08, Right = 63, center = 35
N2.C0.D1.R1.S01: RxDqsDelay = 035
N2.C0.D1.R1.S02: RdDqDqs FSM results: Left = 07, Right = 63, center = 35
N2.C0.D1.R1.S02: RxDqsDelay = 035
N2.C0.D1.R1.S03: RdDqDqs FSM results: Left = 09, Right = 63, center = 36
N2.C0.D1.R1.S03: RxDqsDelay = 036
N2.C0.D1.R1.S04: RdDqDqs FSM results: Left = 09, Right = 63, center = 36
N2.C0.D1.R1.S04: RxDqsDelay = 036
N2.C0.D1.R1.S05: RdDqDqs FSM results: Left = 07, Right = 63, center = 35
N2.C0.D1.R1.S05: RxDqsDelay = 035
N2.C0.D1.R1.S06: RdDqDqs FSM results: Left = 11, Right = 63, center = 37
N2.C0.D1.R1.S06: RxDqsDelay = 037
N2.C0.D1.R1.S07: RdDqDqs FSM results: Left = 10, Right = 63, center = 36
N2.C0.D1.R1.S07: RxDqsDelay = 036
N2.C0.D1.R1.S08: RdDqDqs FSM results: Left = 12, Right = 63, center = 37
N2.C0.D1.R1.S08: RxDqsDelay = 037
N2.C0.D1.R1.S09: RdDqDqs FSM results: Left = 08, Right = 63, center = 35
N2.C0.D1.R1.S09: RxDqsDelay = 035
N2.C0.D1.R1.S10: RdDqDqs FSM results: Left = 10, Right = 63, center = 36
N2.C0.D1.R1.S10: RxDqsDelay = 036
N2.C0.D1.R1.S11: RdDqDqs FSM results: Left = 07, Right = 63, center = 35
N2.C0.D1.R1.S11: RxDqsDelay = 035
N2.C0.D1.R1.S12: RdDqDqs FSM results: Left = 08, Right = 63, center = 35
N2.C0.D1.R1.S12: RxDqsDelay = 035
N2.C0.D1.R1.S13: RdDqDqs FSM results: Left = 08, Right = 63, center = 35
N2.C0.D1.R1.S13: RxDqsDelay = 035
N2.C0.D1.R1.S14: RdDqDqs FSM results: Left = 06, Right = 63, center = 34
N2.C0.D1.R1.S14: RxDqsDelay = 034
N2.C0.D1.R1.S15: RdDqDqs FSM results: Left = 08, Right = 63, center = 35
N2.C0.D1.R1.S15: RxDqsDelay = 035
N2.C0.D1.R1.S16: RdDqDqs FSM results: Left = 08, Right = 63, center = 35
N2.C0.D1.R1.S16: RxDqsDelay = 035
N2.C0.D1.R1.S17: RdDqDqs FSM results: Left = 10, Right = 63, center = 36
N2.C0.D1.R1.S17: RxDqsDelay = 036
START_DATA_RX_DQS
N2.C0.R0.S00: PI = 33
N2.C0.R0.S01: PI = 33
N2.C0.R0.S02: PI = 33
N2.C0.R0.S03: PI = 34
N2.C0.R0.S04: PI = 34
N2.C0.R0.S05: PI = 34
N2.C0.R0.S06: PI = 34
N2.C0.R0.S07: PI = 34
N2.C0.R0.S08: PI = 36
N2.C0.R0.S09: PI = 32
N2.C0.R0.S10: PI = 33
N2.C0.R0.S11: PI = 33
N2.C0.R0.S12: PI = 34
N2.C0.R0.S13: PI = 33
N2.C0.R0.S14: PI = 33
N2.C0.R0.S15: PI = 33
N2.C0.R0.S16: PI = 34
N2.C0.R0.S17: PI = 34
N2.C0.R0.S00: PI = 33
N2.C0.R0.S01: PI = 33
N2.C0.R0.S02: PI = 33
N2.C0.R0.S03: PI = 34
N2.C0.R0.S04: PI = 34
N2.C0.R0.S05: PI = 34
N2.C0.R0.S06: PI = 34
N2.C0.R0.S07: PI = 34
N2.C0.R0.S08: PI = 36
N2.C0.R0.S09: PI = 32
N2.C0.R0.S10: PI = 33
N2.C0.R0.S11: PI = 33
N2.C0.R0.S12: PI = 34
N2.C0.R0.S13: PI = 33
N2.C0.R0.S14: PI = 33
N2.C0.R0.S15: PI = 33
N2.C0.R0.S16: PI = 34
N2.C0.R0.S17: PI = 34
N2.C0.R2.S00: PI = 35
N2.C0.R2.S01: PI = 35
N2.C0.R2.S02: PI = 35
N2.C0.R2.S03: PI = 36
N2.C0.R2.S04: PI = 36
N2.C0.R2.S05: PI = 35
N2.C0.R2.S06: PI = 36
N2.C0.R2.S07: PI = 36
N2.C0.R2.S08: PI = 37
N2.C0.R2.S09: PI = 35
N2.C0.R2.S10: PI = 36
N2.C0.R2.S11: PI = 35
N2.C0.R2.S12: PI = 35
N2.C0.R2.S13: PI = 35
N2.C0.R2.S14: PI = 34
N2.C0.R2.S15: PI = 35
N2.C0.R2.S16: PI = 35
N2.C0.R2.S17: PI = 36
N2.C0.R2.S00: PI = 35
N2.C0.R2.S01: PI = 35
N2.C0.R2.S02: PI = 35
N2.C0.R2.S03: PI = 36
N2.C0.R2.S04: PI = 36
N2.C0.R2.S05: PI = 35
N2.C0.R2.S06: PI = 36
N2.C0.R2.S07: PI = 36
N2.C0.R2.S08: PI = 37
N2.C0.R2.S09: PI = 35
N2.C0.R2.S10: PI = 36
N2.C0.R2.S11: PI = 35
N2.C0.R2.S12: PI = 35
N2.C0.R2.S13: PI = 35
N2.C0.R2.S14: PI = 34
N2.C0.R2.S15: PI = 35
N2.C0.R2.S16: PI = 35
N2.C0.R2.S17: PI = 36
STOP_DATA_RX_DQS
N2.C1.D0.R0.S00: RdDqDqs FSM results: Left = 04, Right = 63, center = 33
N2.C1.D0.R0.S00: RxDqsDelay = 033
N2.C1.D0.R0.S01: RdDqDqs FSM results: Left = 05, Right = 63, center = 34
N2.C1.D0.R0.S01: RxDqsDelay = 034
N2.C1.D0.R0.S02: RdDqDqs FSM results: Left = 03, Right = 63, center = 33
N2.C1.D0.R0.S02: RxDqsDelay = 033
N2.C1.D0.R0.S03: RdDqDqs FSM results: Left = 07, Right = 63, center = 35
N2.C1.D0.R0.S03: RxDqsDelay = 035
N2.C1.D0.R0.S04: RdDqDqs FSM results: Left = 07, Right = 63, center = 35
N2.C1.D0.R0.S04: RxDqsDelay = 035
N2.C1.D0.R0.S05: RdDqDqs FSM results: Left = 04, Right = 63, center = 33
N2.C1.D0.R0.S05: RxDqsDelay = 033
N2.C1.D0.R0.S06: RdDqDqs FSM results: Left = 04, Right = 63, center = 33
N2.C1.D0.R0.S06: RxDqsDelay = 033
N2.C1.D0.R0.S07: RdDqDqs FSM results: Left = 06, Right = 63, center = 34
N2.C1.D0.R0.S07: RxDqsDelay = 034
N2.C1.D0.R0.S08: RdDqDqs FSM results: Left = 03, Right = 58, center = 30
N2.C1.D0.R0.S08: RxDqsDelay = 030
N2.C1.D0.R0.S09: RdDqDqs FSM results: Left = 03, Right = 60, center = 31
N2.C1.D0.R0.S09: RxDqsDelay = 031
N2.C1.D0.R0.S10: RdDqDqs FSM results: Left = 04, Right = 60, center = 32
N2.C1.D0.R0.S10: RxDqsDelay = 032
N2.C1.D0.R0.S11: RdDqDqs FSM results: Left = 02, Right = 61, center = 31
N2.C1.D0.R0.S11: RxDqsDelay = 031
N2.C1.D0.R0.S12: RdDqDqs FSM results: Left = 05, Right = 58, center = 31
N2.C1.D0.R0.S12: RxDqsDelay = 031
N2.C1.D0.R0.S13: RdDqDqs FSM results: Left = 03, Right = 57, center = 30
N2.C1.D0.R0.S13: RxDqsDelay = 030
N2.C1.D0.R0.S14: RdDqDqs FSM results: Left = 08, Right = 63, center = 35
N2.C1.D0.R0.S14: RxDqsDelay = 035
N2.C1.D0.R0.S15: RdDqDqs FSM results: Left = 06, Right = 63, center = 34
N2.C1.D0.R0.S15: RxDqsDelay = 034
N2.C1.D0.R0.S16: RdDqDqs FSM results: Left = 05, Right = 63, center = 34
N2.C1.D0.R0.S16: RxDqsDelay = 034
N2.C1.D0.R0.S17: RdDqDqs FSM results: Left = 01, Right = 56, center = 28
N2.C1.D0.R0.S17: RxDqsDelay = 028
N2.C1.D0.R1.S00: RdDqDqs FSM results: Left = 04, Right = 61, center = 32
N2.C1.D0.R1.S00: RxDqsDelay = 032
N2.C1.D0.R1.S01: RdDqDqs FSM results: Left = 05, Right = 63, center = 34
N2.C1.D0.R1.S01: RxDqsDelay = 034
N2.C1.D0.R1.S02: RdDqDqs FSM results: Left = 03, Right = 63, center = 33
N2.C1.D0.R1.S02: RxDqsDelay = 033
N2.C1.D0.R1.S03: RdDqDqs FSM results: Left = 06, Right = 63, center = 34
N2.C1.D0.R1.S03: RxDqsDelay = 034
N2.C1.D0.R1.S04: RdDqDqs FSM results: Left = 06, Right = 63, center = 34
N2.C1.D0.R1.S04: RxDqsDelay = 034
N2.C1.D0.R1.S05: RdDqDqs FSM results: Left = 04, Right = 63, center = 33
N2.C1.D0.R1.S05: RxDqsDelay = 033
N2.C1.D0.R1.S06: RdDqDqs FSM results: Left = 04, Right = 60, center = 32
N2.C1.D0.R1.S06: RxDqsDelay = 032
N2.C1.D0.R1.S07: RdDqDqs FSM results: Left = 05, Right = 63, center = 34
N2.C1.D0.R1.S07: RxDqsDelay = 034
N2.C1.D0.R1.S08: RdDqDqs FSM results: Left = 02, Right = 59, center = 30
N2.C1.D0.R1.S08: RxDqsDelay = 030
N2.C1.D0.R1.S09: RdDqDqs FSM results: Left = 04, Right = 61, center = 32
N2.C1.D0.R1.S09: RxDqsDelay = 032
N2.C1.D0.R1.S10: RdDqDqs FSM results: Left = 04, Right = 58, center = 31
N2.C1.D0.R1.S10: RxDqsDelay = 031
N2.C1.D0.R1.S11: RdDqDqs FSM results: Left = 02, Right = 63, center = 32
N2.C1.D0.R1.S11: RxDqsDelay = 032
N2.C1.D0.R1.S12: RdDqDqs FSM results: Left = 06, Right = 58, center = 32
N2.C1.D0.R1.S12: RxDqsDelay = 032
N2.C1.D0.R1.S13: RdDqDqs FSM results: Left = 04, Right = 60, center = 32
N2.C1.D0.R1.S13: RxDqsDelay = 032
N2.C1.D0.R1.S14: RdDqDqs FSM results: Left = 07, Right = 60, center = 33
N2.C1.D0.R1.S14: RxDqsDelay = 033
N2.C1.D0.R1.S15: RdDqDqs FSM results: Left = 06, Right = 63, center = 34
N2.C1.D0.R1.S15: RxDqsDelay = 034
N2.C1.D0.R1.S16: RdDqDqs FSM results: Left = 05, Right = 63, center = 34
N2.C1.D0.R1.S16: RxDqsDelay = 034
N2.C1.D0.R1.S17: RdDqDqs FSM results: Left = 02, Right = 53, center = 27
N2.C1.D0.R1.S17: RxDqsDelay = 027
N2.C1.D1.R0.S00: RdDqDqs FSM results: Left = 08, Right = 63, center = 35
N2.C1.D1.R0.S00: RxDqsDelay = 035
N2.C1.D1.R0.S01: RdDqDqs FSM results: Left = 09, Right = 63, center = 36
N2.C1.D1.R0.S01: RxDqsDelay = 036
N2.C1.D1.R0.S02: RdDqDqs FSM results: Left = 07, Right = 63, center = 35
N2.C1.D1.R0.S02: RxDqsDelay = 035
N2.C1.D1.R0.S03: RdDqDqs FSM results: Left = 09, Right = 63, center = 36
N2.C1.D1.R0.S03: RxDqsDelay = 036
N2.C1.D1.R0.S04: RdDqDqs FSM results: Left = 10, Right = 63, center = 36
N2.C1.D1.R0.S04: RxDqsDelay = 036
N2.C1.D1.R0.S05: RdDqDqs FSM results: Left = 07, Right = 63, center = 35
N2.C1.D1.R0.S05: RxDqsDelay = 035
N2.C1.D1.R0.S06: RdDqDqs FSM results: Left = 06, Right = 63, center = 34
N2.C1.D1.R0.S06: RxDqsDelay = 034
N2.C1.D1.R0.S07: RdDqDqs FSM results: Left = 09, Right = 63, center = 36
N2.C1.D1.R0.S07: RxDqsDelay = 036
N2.C1.D1.R0.S08: RdDqDqs FSM results: Left = 06, Right = 63, center = 34
N2.C1.D1.R0.S08: RxDqsDelay = 034
N2.C1.D1.R0.S09: RdDqDqs FSM results: Left = 07, Right = 63, center = 35
N2.C1.D1.R0.S09: RxDqsDelay = 035
N2.C1.D1.R0.S10: RdDqDqs FSM results: Left = 07, Right = 63, center = 35
N2.C1.D1.R0.S10: RxDqsDelay = 035
N2.C1.D1.R0.S11: RdDqDqs FSM results: Left = 05, Right = 63, center = 34
N2.C1.D1.R0.S11: RxDqsDelay = 034
N2.C1.D1.R0.S12: RdDqDqs FSM results: Left = 08, Right = 63, center = 35
N2.C1.D1.R0.S12: RxDqsDelay = 035
N2.C1.D1.R0.S13: RdDqDqs FSM results: Left = 07, Right = 63, center = 35
N2.C1.D1.R0.S13: RxDqsDelay = 035
N2.C1.D1.R0.S14: RdDqDqs FSM results: Left = 10, Right = 63, center = 36
N2.C1.D1.R0.S14: RxDqsDelay = 036
N2.C1.D1.R0.S15: RdDqDqs FSM results: Left = 09, Right = 63, center = 36
N2.C1.D1.R0.S15: RxDqsDelay = 036
N2.C1.D1.R0.S16: RdDqDqs FSM results: Left = 08, Right = 63, center = 35
N2.C1.D1.R0.S16: RxDqsDelay = 035
N2.C1.D1.R0.S17: RdDqDqs FSM results: Left = 04, Right = 58, center = 31
N2.C1.D1.R0.S17: RxDqsDelay = 031
N2.C1.D1.R1.S00: RdDqDqs FSM results: Left = 08, Right = 63, center = 35
N2.C1.D1.R1.S00: RxDqsDelay = 035
N2.C1.D1.R1.S01: RdDqDqs FSM results: Left = 10, Right = 63, center = 36
N2.C1.D1.R1.S01: RxDqsDelay = 036
N2.C1.D1.R1.S02: RdDqDqs FSM results: Left = 07, Right = 63, center = 35
N2.C1.D1.R1.S02: RxDqsDelay = 035
N2.C1.D1.R1.S03: RdDqDqs FSM results: Left = 09, Right = 63, center = 36
N2.C1.D1.R1.S03: RxDqsDelay = 036
N2.C1.D1.R1.S04: RdDqDqs FSM results: Left = 09, Right = 63, center = 36
N2.C1.D1.R1.S04: RxDqsDelay = 036
N2.C1.D1.R1.S05: RdDqDqs FSM results: Left = 07, Right = 63, center = 35
N2.C1.D1.R1.S05: RxDqsDelay = 035
N2.C1.D1.R1.S06: RdDqDqs FSM results: Left = 07, Right = 63, center = 35
N2.C1.D1.R1.S06: RxDqsDelay = 035
N2.C1.D1.R1.S07: RdDqDqs FSM results: Left = 08, Right = 63, center = 35
N2.C1.D1.R1.S07: RxDqsDelay = 035
N2.C1.D1.R1.S08: RdDqDqs FSM results: Left = 06, Right = 63, center = 34
N2.C1.D1.R1.S08: RxDqsDelay = 034
N2.C1.D1.R1.S09: RdDqDqs FSM results: Left = 08, Right = 63, center = 35
N2.C1.D1.R1.S09: RxDqsDelay = 035
N2.C1.D1.R1.S10: RdDqDqs FSM results: Left = 07, Right = 63, center = 35
N2.C1.D1.R1.S10: RxDqsDelay = 035
N2.C1.D1.R1.S11: RdDqDqs FSM results: Left = 05, Right = 63, center = 34
N2.C1.D1.R1.S11: RxDqsDelay = 034
N2.C1.D1.R1.S12: RdDqDqs FSM results: Left = 08, Right = 63, center = 35
N2.C1.D1.R1.S12: RxDqsDelay = 035
N2.C1.D1.R1.S13: RdDqDqs FSM results: Left = 08, Right = 63, center = 35
N2.C1.D1.R1.S13: RxDqsDelay = 035
N2.C1.D1.R1.S14: RdDqDqs FSM results: Left = 11, Right = 63, center = 37
N2.C1.D1.R1.S14: RxDqsDelay = 037
N2.C1.D1.R1.S15: RdDqDqs FSM results: Left = 09, Right = 63, center = 36
N2.C1.D1.R1.S15: RxDqsDelay = 036
N2.C1.D1.R1.S16: RdDqDqs FSM results: Left = 08, Right = 63, center = 35
N2.C1.D1.R1.S16: RxDqsDelay = 035
N2.C1.D1.R1.S17: RdDqDqs FSM results: Left = 04, Right = 58, center = 31
N2.C1.D1.R1.S17: RxDqsDelay = 031
START_DATA_RX_DQS
N2.C1.R0.S00: PI = 32
N2.C1.R0.S01: PI = 34
N2.C1.R0.S02: PI = 33
N2.C1.R0.S03: PI = 34
N2.C1.R0.S04: PI = 34
N2.C1.R0.S05: PI = 33
N2.C1.R0.S06: PI = 32
N2.C1.R0.S07: PI = 34
N2.C1.R0.S08: PI = 30
N2.C1.R0.S09: PI = 31
N2.C1.R0.S10: PI = 31
N2.C1.R0.S11: PI = 31
N2.C1.R0.S12: PI = 31
N2.C1.R0.S13: PI = 31
N2.C1.R0.S14: PI = 34
N2.C1.R0.S15: PI = 34
N2.C1.R0.S16: PI = 34
N2.C1.R0.S17: PI = 27
N2.C1.R0.S00: PI = 32
N2.C1.R0.S01: PI = 34
N2.C1.R0.S02: PI = 33
N2.C1.R0.S03: PI = 34
N2.C1.R0.S04: PI = 34
N2.C1.R0.S05: PI = 33
N2.C1.R0.S06: PI = 32
N2.C1.R0.S07: PI = 34
N2.C1.R0.S08: PI = 30
N2.C1.R0.S09: PI = 31
N2.C1.R0.S10: PI = 31
N2.C1.R0.S11: PI = 31
N2.C1.R0.S12: PI = 31
N2.C1.R0.S13: PI = 31
N2.C1.R0.S14: PI = 34
N2.C1.R0.S15: PI = 34
N2.C1.R0.S16: PI = 34
N2.C1.R0.S17: PI = 27
N2.C1.R2.S00: PI = 35
N2.C1.R2.S01: PI = 36
N2.C1.R2.S02: PI = 35
N2.C1.R2.S03: PI = 36
N2.C1.R2.S04: PI = 36
N2.C1.R2.S05: PI = 35
N2.C1.R2.S06: PI = 34
N2.C1.R2.S07: PI = 35
N2.C1.R2.S08: PI = 34
N2.C1.R2.S09: PI = 35
N2.C1.R2.S10: PI = 35
N2.C1.R2.S11: PI = 34
N2.C1.R2.S12: PI = 35
N2.C1.R2.S13: PI = 35
N2.C1.R2.S14: PI = 36
N2.C1.R2.S15: PI = 36
N2.C1.R2.S16: PI = 35
N2.C1.R2.S17: PI = 31
N2.C1.R2.S00: PI = 35
N2.C1.R2.S01: PI = 36
N2.C1.R2.S02: PI = 35
N2.C1.R2.S03: PI = 36
N2.C1.R2.S04: PI = 36
N2.C1.R2.S05: PI = 35
N2.C1.R2.S06: PI = 34
N2.C1.R2.S07: PI = 35
N2.C1.R2.S08: PI = 34
N2.C1.R2.S09: PI = 35
N2.C1.R2.S10: PI = 35
N2.C1.R2.S11: PI = 34
N2.C1.R2.S12: PI = 35
N2.C1.R2.S13: PI = 35
N2.C1.R2.S14: PI = 36
N2.C1.R2.S15: PI = 36
N2.C1.R2.S16: PI = 35
N2.C1.R2.S17: PI = 31
STOP_DATA_RX_DQS
N2.C2.D0.R0.S00: RdDqDqs FSM results: Left = 04, Right = 63, center = 33
N2.C2.D0.R0.S00: RxDqsDelay = 033
N2.C2.D0.R0.S01: RdDqDqs FSM results: Left = 05, Right = 63, center = 34
N2.C2.D0.R0.S01: RxDqsDelay = 034
N2.C2.D0.R0.S02: RdDqDqs FSM results: Left = 07, Right = 63, center = 35
N2.C2.D0.R0.S02: RxDqsDelay = 035
N2.C2.D0.R0.S03: RdDqDqs FSM results: Left = 06, Right = 63, center = 34
N2.C2.D0.R0.S03: RxDqsDelay = 034
N2.C2.D0.R0.S04: RdDqDqs FSM results: Left = 04, Right = 63, center = 33
N2.C2.D0.R0.S04: RxDqsDelay = 033
N2.C2.D0.R0.S05: RdDqDqs FSM results: Left = 09, Right = 63, center = 36
N2.C2.D0.R0.S05: RxDqsDelay = 036
N2.C2.D0.R0.S06: RdDqDqs FSM results: Left = 05, Right = 63, center = 34
N2.C2.D0.R0.S06: RxDqsDelay = 034
N2.C2.D0.R0.S07: RdDqDqs FSM results: Left = 11, Right = 63, center = 37
N2.C2.D0.R0.S07: RxDqsDelay = 037
N2.C2.D0.R0.S08: RdDqDqs FSM results: Left = 07, Right = 63, center = 35
N2.C2.D0.R0.S08: RxDqsDelay = 035
N2.C2.D0.R0.S09: RdDqDqs FSM results: Left = 07, Right = 63, center = 35
N2.C2.D0.R0.S09: RxDqsDelay = 035
N2.C2.D0.R0.S10: RdDqDqs FSM results: Left = 06, Right = 60, center = 33
N2.C2.D0.R0.S10: RxDqsDelay = 033
N2.C2.D0.R0.S11: RdDqDqs FSM results: Left = 09, Right = 63, center = 36
N2.C2.D0.R0.S11: RxDqsDelay = 036
N2.C2.D0.R0.S12: RdDqDqs FSM results: Left = 07, Right = 63, center = 35
N2.C2.D0.R0.S12: RxDqsDelay = 035
N2.C2.D0.R0.S13: RdDqDqs FSM results: Left = 03, Right = 63, center = 33
N2.C2.D0.R0.S13: RxDqsDelay = 033
N2.C2.D0.R0.S14: RdDqDqs FSM results: Left = 09, Right = 63, center = 36
N2.C2.D0.R0.S14: RxDqsDelay = 036
N2.C2.D0.R0.S15: RdDqDqs FSM results: Left = 10, Right = 63, center = 36
N2.C2.D0.R0.S15: RxDqsDelay = 036
N2.C2.D0.R0.S16: RdDqDqs FSM results: Left = 09, Right = 63, center = 36
N2.C2.D0.R0.S16: RxDqsDelay = 036
N2.C2.D0.R0.S17: RdDqDqs FSM results: Left = 09, Right = 63, center = 36
N2.C2.D0.R0.S17: RxDqsDelay = 036
N2.C2.D0.R1.S00: RdDqDqs FSM results: Left = 04, Right = 63, center = 33
N2.C2.D0.R1.S00: RxDqsDelay = 033
N2.C2.D0.R1.S01: RdDqDqs FSM results: Left = 05, Right = 63, center = 34
N2.C2.D0.R1.S01: RxDqsDelay = 034
N2.C2.D0.R1.S02: RdDqDqs FSM results: Left = 08, Right = 63, center = 35
N2.C2.D0.R1.S02: RxDqsDelay = 035
N2.C2.D0.R1.S03: RdDqDqs FSM results: Left = 06, Right = 63, center = 34
N2.C2.D0.R1.S03: RxDqsDelay = 034
N2.C2.D0.R1.S04: RdDqDqs FSM results: Left = 03, Right = 63, center = 33
N2.C2.D0.R1.S04: RxDqsDelay = 033
N2.C2.D0.R1.S05: RdDqDqs FSM results: Left = 09, Right = 63, center = 36
N2.C2.D0.R1.S05: RxDqsDelay = 036
N2.C2.D0.R1.S06: RdDqDqs FSM results: Left = 04, Right = 63, center = 33
N2.C2.D0.R1.S06: RxDqsDelay = 033
N2.C2.D0.R1.S07: RdDqDqs FSM results: Left = 11, Right = 63, center = 37
N2.C2.D0.R1.S07: RxDqsDelay = 037
N2.C2.D0.R1.S08: RdDqDqs FSM results: Left = 07, Right = 63, center = 35
N2.C2.D0.R1.S08: RxDqsDelay = 035
N2.C2.D0.R1.S09: RdDqDqs FSM results: Left = 07, Right = 63, center = 35
N2.C2.D0.R1.S09: RxDqsDelay = 035
N2.C2.D0.R1.S10: RdDqDqs FSM results: Left = 07, Right = 63, center = 35
N2.C2.D0.R1.S10: RxDqsDelay = 035
N2.C2.D0.R1.S11: RdDqDqs FSM results: Left = 10, Right = 63, center = 36
N2.C2.D0.R1.S11: RxDqsDelay = 036
N2.C2.D0.R1.S12: RdDqDqs FSM results: Left = 08, Right = 63, center = 35
N2.C2.D0.R1.S12: RxDqsDelay = 035
N2.C2.D0.R1.S13: RdDqDqs FSM results: Left = 03, Right = 63, center = 33
N2.C2.D0.R1.S13: RxDqsDelay = 033
N2.C2.D0.R1.S14: RdDqDqs FSM results: Left = 09, Right = 63, center = 36
N2.C2.D0.R1.S14: RxDqsDelay = 036
N2.C2.D0.R1.S15: RdDqDqs FSM results: Left = 09, Right = 63, center = 36
N2.C2.D0.R1.S15: RxDqsDelay = 036
N2.C2.D0.R1.S16: RdDqDqs FSM results: Left = 09, Right = 63, center = 36
N2.C2.D0.R1.S16: RxDqsDelay = 036
N2.C2.D0.R1.S17: RdDqDqs FSM results: Left = 08, Right = 63, center = 35
N2.C2.D0.R1.S17: RxDqsDelay = 035
N2.C2.D1.R0.S00: RdDqDqs FSM results: Left = 08, Right = 63, center = 35
N2.C2.D1.R0.S00: RxDqsDelay = 035
N2.C2.D1.R0.S01: RdDqDqs FSM results: Left = 09, Right = 63, center = 36
N2.C2.D1.R0.S01: RxDqsDelay = 036
N2.C2.D1.R0.S02: RdDqDqs FSM results: Left = 12, Right = 63, center = 37
N2.C2.D1.R0.S02: RxDqsDelay = 037
N2.C2.D1.R0.S03: RdDqDqs FSM results: Left = 09, Right = 63, center = 36
N2.C2.D1.R0.S03: RxDqsDelay = 036
N2.C2.D1.R0.S04: RdDqDqs FSM results: Left = 10, Right = 63, center = 36
N2.C2.D1.R0.S04: RxDqsDelay = 036
N2.C2.D1.R0.S05: RdDqDqs FSM results: Left = 10, Right = 63, center = 36
N2.C2.D1.R0.S05: RxDqsDelay = 036
N2.C2.D1.R0.S06: RdDqDqs FSM results: Left = 08, Right = 63, center = 35
N2.C2.D1.R0.S06: RxDqsDelay = 035
N2.C2.D1.R0.S07: RdDqDqs FSM results: Left = 15, Right = 63, center = 39
N2.C2.D1.R0.S07: RxDqsDelay = 039
N2.C2.D1.R0.S08: RdDqDqs FSM results: Left = 10, Right = 63, center = 36
N2.C2.D1.R0.S08: RxDqsDelay = 036
N2.C2.D1.R0.S09: RdDqDqs FSM results: Left = 11, Right = 63, center = 37
N2.C2.D1.R0.S09: RxDqsDelay = 037
N2.C2.D1.R0.S10: RdDqDqs FSM results: Left = 10, Right = 63, center = 36
N2.C2.D1.R0.S10: RxDqsDelay = 036
N2.C2.D1.R0.S11: RdDqDqs FSM results: Left = 11, Right = 63, center = 37
N2.C2.D1.R0.S11: RxDqsDelay = 037
N2.C2.D1.R0.S12: RdDqDqs FSM results: Left = 10, Right = 63, center = 36
N2.C2.D1.R0.S12: RxDqsDelay = 036
N2.C2.D1.R0.S13: RdDqDqs FSM results: Left = 05, Right = 63, center = 34
N2.C2.D1.R0.S13: RxDqsDelay = 034
N2.C2.D1.R0.S14: RdDqDqs FSM results: Left = 11, Right = 63, center = 37
N2.C2.D1.R0.S14: RxDqsDelay = 037
N2.C2.D1.R0.S15: RdDqDqs FSM results: Left = 14, Right = 63, center = 38
N2.C2.D1.R0.S15: RxDqsDelay = 038
N2.C2.D1.R0.S16: RdDqDqs FSM results: Left = 12, Right = 63, center = 37
N2.C2.D1.R0.S16: RxDqsDelay = 037
N2.C2.D1.R0.S17: RdDqDqs FSM results: Left = 12, Right = 63, center = 37
N2.C2.D1.R0.S17: RxDqsDelay = 037
N2.C2.D1.R1.S00: RdDqDqs FSM results: Left = 08, Right = 63, center = 35
N2.C2.D1.R1.S00: RxDqsDelay = 035
N2.C2.D1.R1.S01: RdDqDqs FSM results: Left = 09, Right = 63, center = 36
N2.C2.D1.R1.S01: RxDqsDelay = 036
N2.C2.D1.R1.S02: RdDqDqs FSM results: Left = 11, Right = 63, center = 37
N2.C2.D1.R1.S02: RxDqsDelay = 037
N2.C2.D1.R1.S03: RdDqDqs FSM results: Left = 08, Right = 63, center = 35
N2.C2.D1.R1.S03: RxDqsDelay = 035
N2.C2.D1.R1.S04: RdDqDqs FSM results: Left = 09, Right = 63, center = 36
N2.C2.D1.R1.S04: RxDqsDelay = 036
N2.C2.D1.R1.S05: RdDqDqs FSM results: Left = 10, Right = 63, center = 36
N2.C2.D1.R1.S05: RxDqsDelay = 036
N2.C2.D1.R1.S06: RdDqDqs FSM results: Left = 08, Right = 63, center = 35
N2.C2.D1.R1.S06: RxDqsDelay = 035
N2.C2.D1.R1.S07: RdDqDqs FSM results: Left = 15, Right = 63, center = 39
N2.C2.D1.R1.S07: RxDqsDelay = 039
N2.C2.D1.R1.S08: RdDqDqs FSM results: Left = 10, Right = 63, center = 36
N2.C2.D1.R1.S08: RxDqsDelay = 036
N2.C2.D1.R1.S09: RdDqDqs FSM results: Left = 11, Right = 63, center = 37
N2.C2.D1.R1.S09: RxDqsDelay = 037
N2.C2.D1.R1.S10: RdDqDqs FSM results: Left = 10, Right = 63, center = 36
N2.C2.D1.R1.S10: RxDqsDelay = 036
N2.C2.D1.R1.S11: RdDqDqs FSM results: Left = 11, Right = 63, center = 37
N2.C2.D1.R1.S11: RxDqsDelay = 037
N2.C2.D1.R1.S12: RdDqDqs FSM results: Left = 10, Right = 63, center = 36
N2.C2.D1.R1.S12: RxDqsDelay = 036
N2.C2.D1.R1.S13: RdDqDqs FSM results: Left = 07, Right = 63, center = 35
N2.C2.D1.R1.S13: RxDqsDelay = 035
N2.C2.D1.R1.S14: RdDqDqs FSM results: Left = 11, Right = 63, center = 37
N2.C2.D1.R1.S14: RxDqsDelay = 037
N2.C2.D1.R1.S15: RdDqDqs FSM results: Left = 13, Right = 63, center = 38
N2.C2.D1.R1.S15: RxDqsDelay = 038
N2.C2.D1.R1.S16: RdDqDqs FSM results: Left = 12, Right = 63, center = 37
N2.C2.D1.R1.S16: RxDqsDelay = 037
N2.C2.D1.R1.S17: RdDqDqs FSM results: Left = 11, Right = 63, center = 37
N2.C2.D1.R1.S17: RxDqsDelay = 037
START_DATA_RX_DQS
N2.C2.R0.S00: PI = 33
N2.C2.R0.S01: PI = 34
N2.C2.R0.S02: PI = 35
N2.C2.R0.S03: PI = 34
N2.C2.R0.S04: PI = 33
N2.C2.R0.S05: PI = 36
N2.C2.R0.S06: PI = 33
N2.C2.R0.S07: PI = 37
N2.C2.R0.S08: PI = 35
N2.C2.R0.S09: PI = 35
N2.C2.R0.S10: PI = 34
N2.C2.R0.S11: PI = 36
N2.C2.R0.S12: PI = 35
N2.C2.R0.S13: PI = 33
N2.C2.R0.S14: PI = 36
N2.C2.R0.S15: PI = 36
N2.C2.R0.S16: PI = 36
N2.C2.R0.S17: PI = 35
N2.C2.R0.S00: PI = 33
N2.C2.R0.S01: PI = 34
N2.C2.R0.S02: PI = 35
N2.C2.R0.S03: PI = 34
N2.C2.R0.S04: PI = 33
N2.C2.R0.S05: PI = 36
N2.C2.R0.S06: PI = 33
N2.C2.R0.S07: PI = 37
N2.C2.R0.S08: PI = 35
N2.C2.R0.S09: PI = 35
N2.C2.R0.S10: PI = 34
N2.C2.R0.S11: PI = 36
N2.C2.R0.S12: PI = 35
N2.C2.R0.S13: PI = 33
N2.C2.R0.S14: PI = 36
N2.C2.R0.S15: PI = 36
N2.C2.R0.S16: PI = 36
N2.C2.R0.S17: PI = 35
N2.C2.R2.S00: PI = 35
N2.C2.R2.S01: PI = 36
N2.C2.R2.S02: PI = 37
N2.C2.R2.S03: PI = 35
N2.C2.R2.S04: PI = 36
N2.C2.R2.S05: PI = 36
N2.C2.R2.S06: PI = 35
N2.C2.R2.S07: PI = 39
N2.C2.R2.S08: PI = 36
N2.C2.R2.S09: PI = 37
N2.C2.R2.S10: PI = 36
N2.C2.R2.S11: PI = 37
N2.C2.R2.S12: PI = 36
N2.C2.R2.S13: PI = 34
N2.C2.R2.S14: PI = 37
N2.C2.R2.S15: PI = 38
N2.C2.R2.S16: PI = 37
N2.C2.R2.S17: PI = 37
N2.C2.R2.S00: PI = 35
N2.C2.R2.S01: PI = 36
N4.C0.D0: CalcFinalClock(89,121) = 21
N2.C2.R2.S02: PI = 37
N2.C2.R2.S03: PI = 35
N2.C2.R2.S04: PI = 36
N2.C2.R2.S05: PI = 36
N4.C0.D1: CalcFinalClock(96,114) = 25
N2.C2.R2.S06: PI = 35
N2.C2.R2.S07: PI = 39
N2.C2.R2.S08: PI = 36
N2.C2.R2.S09: PI = 37
N4.C1.D0: CalcFinalClock(97,112) = 25
N2.C2.R2.S10: PI = 36
N2.C2.R2.S11: PI = 37
N2.C2.R2.S12: PI = 36
N2.C2.R2.S13: PI = 34
N4.C1.D1: CalcFinalClock(99,119) = 30
N2.C2.R2.S14: PI = 37
N2.C2.R2.S15: PI = 38
N2.C2.R2.S16: PI = 37
N2.C2.R2.S17: PI = 37
N4.C2.D0: CalcFinalClock(87,122) = 20
STOP_DATA_RX_DQS
N2.C3.D0.R0.S00: RdDqDqs FSM results: Left = 10, Right = 63, center = 36
N4.C2.D1: CalcFinalClock(97,114) = 26
N2.C3.D0.R0.S00: RxDqsDelay = 036
N2.C3.D0.R0.S01: RdDqDqs FSM results: Left = 03, Right = 63, center = 33
N4.C3.D0: CalcFinalClock(95,109) = 21
N2.C3.D0.R0.S01: RxDqsDelay = 033
N2.C3.D0.R0.S02: RdDqDqs FSM results: Left = 09, Right = 63, center = 36
N4.C3.D1: CalcFinalClock(100,117) = 30
N2.C3.D0.R0.S02: RxDqsDelay = 036
N2.C3.D0.R0.S03: RdDqDqs FSM results: Left = 05, Right = 63, center = 34
N4.C0: JCK cmd timing = 3N
N2.C3.D0.R0.S03: RxDqsDelay = 034
N4.C0: RdCmd2DataValidLatency = 20, (dlyFrmS = 15, clEff = 10, earlyCas = 0, selNTiming = 2)
N2.C3.D0.R0.S04: RdDqDqs FSM results: Left = 06, Right = 63, center = 34
N4.C1: RdCmd2DataValidLatency = 20, (dlyFrmS = 15, clEff = 10, earlyCas = 0, selNTiming = 2)
N2.C3.D0.R0.S04: RxDqsDelay = 034
N4.C2: JCK cmd timing = 3N
N2.C3.D0.R0.S05: RdDqDqs FSM results: Left = 07, Right = 63, center = 35
N4.C2: RdCmd2DataValidLatency = 20, (dlyFrmS = 15, clEff = 10, earlyCas = 0, selNTiming = 2)
N2.C3.D0.R0.S05: RxDqsDelay = 035
N4.C3: RdCmd2DataValidLatency = 20, (dlyFrmS = 15, clEff = 10, earlyCas = 0, selNTiming = 2)
N2.C3.D0.R0.S06: RdDqDqs FSM results: Left = 10, Right = 63, center = 36
N4: RunTrainStep: Final status = 0
N2.C3.D0.R0.S06: RxDqsDelay = 036

END - Early Command Training           Time         4419 ms
N2.C3.D0.R0.S07: RdDqDqs FSM results: Left = 08, Right = 63, center = 35
N2.C3.D0.R0.S07: RxDqsDelay = 035

START - Basic Read DQ/DQS Training
N2.C3.D0.R0.S08: RdDqDqs FSM results: Left = 04, Right = 63, center = 33
N4.C0: RdCmd2DataValidLatency = 20, (dlyFrmS = 15, clEff = 10, earlyCas = 0, selNTiming = 2)
N2.C3.D0.R0.S08: RxDqsDelay = 033
N4.C0: SettingForTrainingStep: RdCmd2RcvEnLatency = 5
N2.C3.D0.R0.S09: RdDqDqs FSM results: Left = 09, Right = 63, center = 36
N4.C1: RdCmd2DataValidLatency = 20, (dlyFrmS = 15, clEff = 10, earlyCas = 0, selNTiming = 2)
N2.C3.D0.R0.S09: RxDqsDelay = 036
N4.C1: SettingForTrainingStep: RdCmd2RcvEnLatency = 5
N2.C3.D0.R0.S10: RdDqDqs FSM results: Left = 04, Right = 63, center = 33
N4.C2: RdCmd2DataValidLatency = 20, (dlyFrmS = 15, clEff = 10, earlyCas = 0, selNTiming = 2)
N2.C3.D0.R0.S10: RxDqsDelay = 033
N4.C2: SettingForTrainingStep: RdCmd2RcvEnLatency = 5
N2.C3.D0.R0.S11: RdDqDqs FSM results: Left = 09, Right = 61, center = 35
N4.C3: RdCmd2DataValidLatency = 20, (dlyFrmS = 15, clEff = 10, earlyCas = 0, selNTiming = 2)
N2.C3.D0.R0.S11: RxDqsDelay = 035
N4.C3: SettingForTrainingStep: RdCmd2RcvEnLatency = 5
N2.C3.D0.R0.S12: RdDqDqs FSM results: Left = 05, Right = 63, center = 34
N4.C0.D0.R0.S00: RdDqDqs FSM results: Left = 10, Right = 63, center = 36
N2.C3.D0.R0.S12: RxDqsDelay = 034
N4.C0.D0.R0.S00: RxDqsDelay = 036
N2.C3.D0.R0.S13: RdDqDqs FSM results: Left = 04, Right = 63, center = 33
N4.C0.D0.R0.S01: RdDqDqs FSM results: Left = 10, Right = 63, center = 36
N2.C3.D0.R0.S13: RxDqsDelay = 033
N4.C0.D0.R0.S01: RxDqsDelay = 036
N2.C3.D0.R0.S14: RdDqDqs FSM results: Left = 07, Right = 63, center = 35
N4.C0.D0.R0.S02: RdDqDqs FSM results: Left = 13, Right = 63, center = 38
N2.C3.D0.R0.S14: RxDqsDelay = 035
N4.C0.D0.R0.S02: RxDqsDelay = 038
N2.C3.D0.R0.S15: RdDqDqs FSM results: Left = 06, Right = 63, center = 34
N4.C0.D0.R0.S03: RdDqDqs FSM results: Left = 12, Right = 63, center = 37
N2.C3.D0.R0.S15: RxDqsDelay = 034
N4.C0.D0.R0.S03: RxDqsDelay = 037
N2.C3.D0.R0.S16: RdDqDqs FSM results: Left = 10, Right = 63, center = 36
N4.C0.D0.R0.S04: RdDqDqs FSM results: Left = 11, Right = 63, center = 37
N2.C3.D0.R0.S16: RxDqsDelay = 036
N4.C0.D0.R0.S04: RxDqsDelay = 037
N2.C3.D0.R0.S17: RdDqDqs FSM results: Left = 04, Right = 59, center = 31
N4.C0.D0.R0.S05: RdDqDqs FSM results: Left = 11, Right = 63, center = 37
N2.C3.D0.R0.S17: RxDqsDelay = 031
N4.C0.D0.R0.S05: RxDqsDelay = 037
N2.C3.D0.R1.S00: RdDqDqs FSM results: Left = 10, Right = 63, center = 36
N4.C0.D0.R0.S06: RdDqDqs FSM results: Left = 14, Right = 63, center = 38
N2.C3.D0.R1.S00: RxDqsDelay = 036
N4.C0.D0.R0.S06: RxDqsDelay = 038
N2.C3.D0.R1.S01: RdDqDqs FSM results: Left = 04, Right = 63, center = 33
N4.C0.D0.R0.S07: RdDqDqs FSM results: Left = 13, Right = 63, center = 38
N2.C3.D0.R1.S01: RxDqsDelay = 033
N4.C0.D0.R0.S07: RxDqsDelay = 038
N2.C3.D0.R1.S02: RdDqDqs FSM results: Left = 10, Right = 63, center = 36
N4.C0.D0.R0.S08: RdDqDqs FSM results: Left = 12, Right = 63, center = 37
N2.C3.D0.R1.S02: RxDqsDelay = 036
N4.C0.D0.R0.S08: RxDqsDelay = 037
N2.C3.D0.R1.S03: RdDqDqs FSM results: Left = 04, Right = 63, center = 33
N4.C0.D0.R0.S09: RdDqDqs FSM results: Left = 13, Right = 63, center = 38
N2.C3.D0.R1.S03: RxDqsDelay = 033
N4.C0.D0.R0.S09: RxDqsDelay = 038
N2.C3.D0.R1.S04: RdDqDqs FSM results: Left = 06, Right = 63, center = 34
N4.C0.D0.R0.S10: RdDqDqs FSM results: Left = 11, Right = 63, center = 37
N2.C3.D0.R1.S04: RxDqsDelay = 034
N4.C0.D0.R0.S10: RxDqsDelay = 037
N2.C3.D0.R1.S05: RdDqDqs FSM results: Left = 07, Right = 63, center = 35
N4.C0.D0.R0.S11: RdDqDqs FSM results: Left = 11, Right = 63, center = 37
N6.C0.D0: CalcFinalClock(92,119) = 23
N2.C3.D0.R1.S05: RxDqsDelay = 035
N4.C0.D0.R0.S11: RxDqsDelay = 037
N0.C0.D0: CalcFinalClock(93,119) = 24
N2.C3.D0.R1.S06: RdDqDqs FSM results: Left = 09, Right = 63, center = 36
N4.C0.D0.R0.S12: RdDqDqs FSM results: Left = 12, Right = 63, center = 37
N6.C0.D1: CalcFinalClock(98,112) = 26
N0.C0.D1: CalcFinalClock(99,112) = 27
N2.C3.D0.R1.S06: RxDqsDelay = 036
N4.C0.D0.R0.S12: RxDqsDelay = 037
N6.C1.D0: CalcFinalClock(98,110) = 25
N0.C1.D0: CalcFinalClock(97,111) = 24
N2.C3.D0.R1.S07: RdDqDqs FSM results: Left = 07, Right = 63, center = 35
N4.C0.D0.R0.S13: RdDqDqs FSM results: Left = 10, Right = 63, center = 36
N6.C1.D1: CalcFinalClock(102,121) = 34
N0.C1.D1: CalcFinalClock(101,119) = 32
N2.C3.D0.R1.S07: RxDqsDelay = 035
N4.C0.D0.R0.S13: RxDqsDelay = 036
N6.C2.D0: CalcFinalClock(88,122) = 21
N0.C2.D0: CalcFinalClock(92,120) = 24
N2.C3.D0.R1.S08: RdDqDqs FSM results: Left = 04, Right = 63, center = 33
N4.C0.D0.R0.S14: RdDqDqs FSM results: Left = 11, Right = 63, center = 37
N6.C2.D1: CalcFinalClock(99,112) = 27
N0.C2.D1: CalcFinalClock(101,113) = 29
N2.C3.D0.R1.S08: RxDqsDelay = 033
N4.C0.D0.R0.S14: RxDqsDelay = 037
N6.C3.D0: CalcFinalClock(98,107) = 23
N0.C3.D0: CalcFinalClock(98,109) = 24
N2.C3.D0.R1.S09: RdDqDqs FSM results: Left = 08, Right = 63, center = 35
N4.C0.D0.R0.S15: RdDqDqs FSM results: Left = 09, Right = 63, center = 36
N6.C3.D1: CalcFinalClock(98,116) = 28
N0.C3.D1: CalcFinalClock(96,119) = 27
N2.C3.D0.R1.S09: RxDqsDelay = 035
N4.C0.D0.R0.S15: RxDqsDelay = 036
N6.C0: JCK cmd timing = 3N
N0.C0: JCK cmd timing = 3N
N2.C3.D0.R1.S10: RdDqDqs FSM results: Left = 04, Right = 63, center = 33
N4.C0.D0.R0.S16: RdDqDqs FSM results: Left = 11, Right = 63, center = 37
N6.C0: RdCmd2DataValidLatency = 20, (dlyFrmS = 15, clEff = 10, earlyCas = 0, selNTiming = 2)
N0.C0: RdCmd2DataValidLatency = 20, (dlyFrmS = 15, clEff = 10, earlyCas = 0, selNTiming = 2)
N2.C3.D0.R1.S10: RxDqsDelay = 033
N4.C0.D0.R0.S16: RxDqsDelay = 037
N6.C1: RdCmd2DataValidLatency = 20, (dlyFrmS = 15, clEff = 10, earlyCas = 0, selNTiming = 2)
N0.C1: RdCmd2DataValidLatency = 20, (dlyFrmS = 15, clEff = 10, earlyCas = 0, selNTiming = 2)
N2.C3.D0.R1.S11: RdDqDqs FSM results: Left = 08, Right = 63, center = 35
N4.C0.D0.R0.S17: RdDqDqs FSM results: Left = 10, Right = 63, center = 36
N6.C2: JCK cmd timing = 3N
N0.C2: JCK cmd timing = 3N
N2.C3.D0.R1.S11: RxDqsDelay = 035
N4.C0.D0.R0.S17: RxDqsDelay = 036
N6.C2: RdCmd2DataValidLatency = 20, (dlyFrmS = 15, clEff = 10, earlyCas = 0, selNTiming = 2)
N0.C2: RdCmd2DataValidLatency = 20, (dlyFrmS = 15, clEff = 10, earlyCas = 0, selNTiming = 2)
N2.C3.D0.R1.S12: RdDqDqs FSM results: Left = 04, Right = 63, center = 33
N4.C0.D0.R1.S00: RdDqDqs FSM results: Left = 10, Right = 63, center = 36
N6.C3: RdCmd2DataValidLatency = 20, (dlyFrmS = 15, clEff = 10, earlyCas = 0, selNTiming = 2)
N0.C3: RdCmd2DataValidLatency = 20, (dlyFrmS = 15, clEff = 10, earlyCas = 0, selNTiming = 2)
N2.C3.D0.R1.S12: RxDqsDelay = 033
N4.C0.D0.R1.S00: RxDqsDelay = 036
N6: RunTrainStep: Final status = 0
N0: RunTrainStep: Final status = 0
N2.C3.D0.R1.S13: RdDqDqs FSM results: Left = 04, Right = 63, center = 33
N4.C0.D0.R1.S01: RdDqDqs FSM results: Left = 10, Right = 63, center = 36

END - Early Command Training           Time         4475 ms

END - Early Command Training           Time         4379 ms
N2.C3.D0.R1.S13: RxDqsDelay = 033
N4.C0.D0.R1.S01: RxDqsDelay = 036

START - Basic Read DQ/DQS Training

START - Basic Read DQ/DQS Training
N2.C3.D0.R1.S14: RdDqDqs FSM results: Left = 07, Right = 63, center = 35
N4.C0.D0.R1.S02: RdDqDqs FSM results: Left = 13, Right = 63, center = 38
N6.C0: RdCmd2DataValidLatency = 20, (dlyFrmS = 15, clEff = 10, earlyCas = 0, selNTiming = 2)
Checkpoint Code: Socket 0, 0xB7, 0x01, 0x0000
N2.C3.D0.R1.S14: RxDqsDelay = 035
N4.C0.D0.R1.S02: RxDqsDelay = 038
N6.C0: SettingForTrainingStep: RdCmd2RcvEnLatency = 5
N0.C0: RdCmd2DataValidLatency = 20, (dlyFrmS = 15, clEff = 10, earlyCas = 0, selNTiming = 2)
N2.C3.D0.R1.S15: RdDqDqs FSM results: Left = 07, Right = 63, center = 35
N4.C0.D0.R1.S03: RdDqDqs FSM results: Left = 12, Right = 63, center = 37
N6.C1: RdCmd2DataValidLatency = 20, (dlyFrmS = 15, clEff = 10, earlyCas = 0, selNTiming = 2)
N0.C0: SettingForTrainingStep: RdCmd2RcvEnLatency = 5
N2.C3.D0.R1.S15: RxDqsDelay = 035
N4.C0.D0.R1.S03: RxDqsDelay = 037
N6.C1: SettingForTrainingStep: RdCmd2RcvEnLatency = 5
N0.C1: RdCmd2DataValidLatency = 20, (dlyFrmS = 15, clEff = 10, earlyCas = 0, selNTiming = 2)
N2.C3.D0.R1.S16: RdDqDqs FSM results: Left = 10, Right = 63, center = 36
N4.C0.D0.R1.S04: RdDqDqs FSM results: Left = 12, Right = 63, center = 37
N6.C2: RdCmd2DataValidLatency = 20, (dlyFrmS = 15, clEff = 10, earlyCas = 0, selNTiming = 2)
N0.C1: SettingForTrainingStep: RdCmd2RcvEnLatency = 5
N2.C3.D0.R1.S16: RxDqsDelay = 036
N4.C0.D0.R1.S04: RxDqsDelay = 037
N6.C2: SettingForTrainingStep: RdCmd2RcvEnLatency = 5
N0.C2: RdCmd2DataValidLatency = 20, (dlyFrmS = 15, clEff = 10, earlyCas = 0, selNTiming = 2)
N2.C3.D0.R1.S17: RdDqDqs FSM results: Left = 04, Right = 61, center = 32
N4.C0.D0.R1.S05: RdDqDqs FSM results: Left = 11, Right = 63, center = 37
N6.C3: RdCmd2DataValidLatency = 20, (dlyFrmS = 15, clEff = 10, earlyCas = 0, selNTiming = 2)
N0.C2: SettingForTrainingStep: RdCmd2RcvEnLatency = 5
N2.C3.D0.R1.S17: RxDqsDelay = 032
N4.C0.D0.R1.S05: RxDqsDelay = 037
N6.C3: SettingForTrainingStep: RdCmd2RcvEnLatency = 5
N0.C3: RdCmd2DataValidLatency = 20, (dlyFrmS = 15, clEff = 10, earlyCas = 0, selNTiming = 2)
N2.C3.D1.R0.S00: RdDqDqs FSM results: Left = 14, Right = 63, center = 38
N4.C0.D0.R1.S06: RdDqDqs FSM results: Left = 15, Right = 63, center = 39
N6.C0.D0.R0.S00: RdDqDqs FSM results: Left = 04, Right = 59, center = 31
N0.C3: SettingForTrainingStep: RdCmd2RcvEnLatency = 5
N2.C3.D1.R0.S00: RxDqsDelay = 038
N4.C0.D0.R1.S06: RxDqsDelay = 039
N6.C0.D0.R0.S00: RxDqsDelay = 031
N0.C0.D0.R0.S00: RdDqDqs FSM results: Left = 03, Right = 61, center = 32
N2.C3.D1.R0.S01: RdDqDqs FSM results: Left = 07, Right = 63, center = 35
N4.C0.D0.R1.S07: RdDqDqs FSM results: Left = 13, Right = 63, center = 38
N6.C0.D0.R0.S01: RdDqDqs FSM results: Left = 03, Right = 63, center = 33
N0.C0.D0.R0.S00: RxDqsDelay = 032
N2.C3.D1.R0.S01: RxDqsDelay = 035
N4.C0.D0.R1.S07: RxDqsDelay = 038
N6.C0.D0.R0.S01: RxDqsDelay = 033
N0.C0.D0.R0.S01: RdDqDqs FSM results: Left = 04, Right = 63, center = 33
N2.C3.D1.R0.S02: RdDqDqs FSM results: Left = 12, Right = 63, center = 37
N4.C0.D0.R1.S08: RdDqDqs FSM results: Left = 12, Right = 63, center = 37
N6.C0.D0.R0.S02: RdDqDqs FSM results: Left = 04, Right = 63, center = 33
N0.C0.D0.R0.S01: RxDqsDelay = 033
N2.C3.D1.R0.S02: RxDqsDelay = 037
N4.C0.D0.R1.S08: RxDqsDelay = 037
N6.C0.D0.R0.S02: RxDqsDelay = 033
N0.C0.D0.R0.S02: RdDqDqs FSM results: Left = 04, Right = 63, center = 33
N2.C3.D1.R0.S03: RdDqDqs FSM results: Left = 07, Right = 63, center = 35
N4.C0.D0.R1.S09: RdDqDqs FSM results: Left = 13, Right = 63, center = 38
N6.C0.D0.R0.S03: RdDqDqs FSM results: Left = 04, Right = 63, center = 33
N0.C0.D0.R0.S02: RxDqsDelay = 033
N2.C3.D1.R0.S03: RxDqsDelay = 035
N4.C0.D0.R1.S09: RxDqsDelay = 038
N6.C0.D0.R0.S03: RxDqsDelay = 033
N0.C0.D0.R0.S03: RdDqDqs FSM results: Left = 03, Right = 63, center = 33
N2.C3.D1.R0.S04: RdDqDqs FSM results: Left = 11, Right = 63, center = 37
N4.C0.D0.R1.S10: RdDqDqs FSM results: Left = 10, Right = 63, center = 36
N6.C0.D0.R0.S04: RdDqDqs FSM results: Left = 03, Right = 63, center = 33
N0.C0.D0.R0.S03: RxDqsDelay = 033
N2.C3.D1.R0.S04: RxDqsDelay = 037
N4.C0.D0.R1.S10: RxDqsDelay = 036
N6.C0.D0.R0.S04: RxDqsDelay = 033
N0.C0.D0.R0.S04: RdDqDqs FSM results: Left = 05, Right = 63, center = 34
N2.C3.D1.R0.S05: RdDqDqs FSM results: Left = 10, Right = 63, center = 36
N4.C0.D0.R1.S11: RdDqDqs FSM results: Left = 11, Right = 63, center = 37
N6.C0.D0.R0.S05: RdDqDqs FSM results: Left = 06, Right = 63, center = 34
N0.C0.D0.R0.S04: RxDqsDelay = 034
N2.C3.D1.R0.S05: RxDqsDelay = 036
N4.C0.D0.R1.S11: RxDqsDelay = 037
N6.C0.D0.R0.S05: RxDqsDelay = 034
N0.C0.D0.R0.S05: RdDqDqs FSM results: Left = 06, Right = 63, center = 34
N2.C3.D1.R0.S06: RdDqDqs FSM results: Left = 11, Right = 63, center = 37
N4.C0.D0.R1.S12: RdDqDqs FSM results: Left = 13, Right = 63, center = 38
N6.C0.D0.R0.S06: RdDqDqs FSM results: Left = 04, Right = 63, center = 33
N0.C0.D0.R0.S05: RxDqsDelay = 034
N2.C3.D1.R0.S06: RxDqsDelay = 037
N4.C0.D0.R1.S12: RxDqsDelay = 038
N6.C0.D0.R0.S06: RxDqsDelay = 033
N0.C0.D0.R0.S06: RdDqDqs FSM results: Left = 04, Right = 63, center = 33
N2.C3.D1.R0.S07: RdDqDqs FSM results: Left = 12, Right = 63, center = 37
N4.C0.D0.R1.S13: RdDqDqs FSM results: Left = 10, Right = 63, center = 36
N6.C0.D0.R0.S07: RdDqDqs FSM results: Left = 05, Right = 63, center = 34
N0.C0.D0.R0.S06: RxDqsDelay = 033
N2.C3.D1.R0.S07: RxDqsDelay = 037
N4.C0.D0.R1.S13: RxDqsDelay = 036
N6.C0.D0.R0.S07: RxDqsDelay = 034
N0.C0.D0.R0.S07: RdDqDqs FSM results: Left = 05, Right = 63, center = 34
N2.C3.D1.R0.S08: RdDqDqs FSM results: Left = 09, Right = 63, center = 36
N4.C0.D0.R1.S14: RdDqDqs FSM results: Left = 12, Right = 63, center = 37
N6.C0.D0.R0.S08: RdDqDqs FSM results: Left = 05, Right = 63, center = 34
N0.C0.D0.R0.S07: RxDqsDelay = 034
N2.C3.D1.R0.S08: RxDqsDelay = 036
N4.C0.D0.R1.S14: RxDqsDelay = 037
N6.C0.D0.R0.S08: RxDqsDelay = 034
N0.C0.D0.R0.S08: RdDqDqs FSM results: Left = 03, Right = 63, center = 33
N2.C3.D1.R0.S09: RdDqDqs FSM results: Left = 12, Right = 63, center = 37
N4.C0.D0.R1.S15: RdDqDqs FSM results: Left = 09, Right = 63, center = 36
N6.C0.D0.R0.S09: RdDqDqs FSM results: Left = 04, Right = 63, center = 33
N0.C0.D0.R0.S08: RxDqsDelay = 033
N2.C3.D1.R0.S09: RxDqsDelay = 037
N4.C0.D0.R1.S15: RxDqsDelay = 036
N6.C0.D0.R0.S09: RxDqsDelay = 033
N0.C0.D0.R0.S09: RdDqDqs FSM results: Left = 04, Right = 63, center = 33
N2.C3.D1.R0.S10: RdDqDqs FSM results: Left = 08, Right = 63, center = 35
N4.C0.D0.R1.S16: RdDqDqs FSM results: Left = 10, Right = 63, center = 36
N6.C0.D0.R0.S10: RdDqDqs FSM results: Left = 03, Right = 59, center = 31
N0.C0.D0.R0.S09: RxDqsDelay = 033
N2.C3.D1.R0.S10: RxDqsDelay = 035
N4.C0.D0.R1.S16: RxDqsDelay = 036
N6.C0.D0.R0.S10: RxDqsDelay = 031
N0.C0.D0.R0.S10: RdDqDqs FSM results: Left = 03, Right = 63, center = 33
N2.C3.D1.R0.S11: RdDqDqs FSM results: Left = 10, Right = 63, center = 36
N4.C0.D0.R1.S17: RdDqDqs FSM results: Left = 10, Right = 63, center = 36
N6.C0.D0.R0.S11: RdDqDqs FSM results: Left = 05, Right = 63, center = 34
N0.C0.D0.R0.S10: RxDqsDelay = 033
N2.C3.D1.R0.S11: RxDqsDelay = 036
N4.C0.D0.R1.S17: RxDqsDelay = 036
N6.C0.D0.R0.S11: RxDqsDelay = 034
N0.C0.D0.R0.S11: RdDqDqs FSM results: Left = 03, Right = 63, center = 33
N2.C3.D1.R0.S12: RdDqDqs FSM results: Left = 08, Right = 63, center = 35
N4.C0.D1.R0.S00: RdDqDqs FSM results: Left = 13, Right = 63, center = 38
N6.C0.D0.R0.S12: RdDqDqs FSM results: Left = 04, Right = 63, center = 33
N0.C0.D0.R0.S11: RxDqsDelay = 033
N2.C3.D1.R0.S12: RxDqsDelay = 035
N4.C0.D1.R0.S00: RxDqsDelay = 038
N6.C0.D0.R0.S12: RxDqsDelay = 033
N0.C0.D0.R0.S12: RdDqDqs FSM results: Left = 05, Right = 63, center = 34
N2.C3.D1.R0.S13: RdDqDqs FSM results: Left = 08, Right = 63, center = 35
N4.C0.D1.R0.S01: RdDqDqs FSM results: Left = 15, Right = 63, center = 39
N6.C0.D0.R0.S13: RdDqDqs FSM results: Left = 03, Right = 63, center = 33
N0.C0.D0.R0.S12: RxDqsDelay = 034
N2.C3.D1.R0.S13: RxDqsDelay = 035
N4.C0.D1.R0.S01: RxDqsDelay = 039
N6.C0.D0.R0.S13: RxDqsDelay = 033
N0.C0.D0.R0.S13: RdDqDqs FSM results: Left = 06, Right = 63, center = 34
N2.C3.D1.R0.S14: RdDqDqs FSM results: Left = 10, Right = 63, center = 36
N4.C0.D1.R0.S02: RdDqDqs FSM results: Left = 16, Right = 63, center = 39
N6.C0.D0.R0.S14: RdDqDqs FSM results: Left = 06, Right = 63, center = 34
N0.C0.D0.R0.S13: RxDqsDelay = 034
N2.C3.D1.R0.S14: RxDqsDelay = 036
N4.C0.D1.R0.S02: RxDqsDelay = 039
N6.C0.D0.R0.S14: RxDqsDelay = 034
N0.C0.D0.R0.S14: RdDqDqs FSM results: Left = 03, Right = 63, center = 33
N2.C3.D1.R0.S15: RdDqDqs FSM results: Left = 10, Right = 63, center = 36
N4.C0.D1.R0.S03: RdDqDqs FSM results: Left = 13, Right = 63, center = 38
N6.C0.D0.R0.S15: RdDqDqs FSM results: Left = 07, Right = 63, center = 35
N0.C0.D0.R0.S14: RxDqsDelay = 033
N2.C3.D1.R0.S15: RxDqsDelay = 036
N4.C0.D1.R0.S03: RxDqsDelay = 038
N6.C0.D0.R0.S15: RxDqsDelay = 035
N0.C0.D0.R0.S15: RdDqDqs FSM results: Left = 03, Right = 61, center = 32
N2.C3.D1.R0.S16: RdDqDqs FSM results: Left = 12, Right = 63, center = 37
N4.C0.D1.R0.S04: RdDqDqs FSM results: Left = 15, Right = 63, center = 39
N6.C0.D0.R0.S16: RdDqDqs FSM results: Left = 08, Right = 63, center = 35
N0.C0.D0.R0.S15: RxDqsDelay = 032
N2.C3.D1.R0.S16: RxDqsDelay = 037
N4.C0.D1.R0.S04: RxDqsDelay = 039
N6.C0.D0.R0.S16: RxDqsDelay = 035
N0.C0.D0.R0.S16: RdDqDqs FSM results: Left = 03, Right = 63, center = 33
N2.C3.D1.R0.S17: RdDqDqs FSM results: Left = 08, Right = 63, center = 35
N4.C0.D1.R0.S05: RdDqDqs FSM results: Left = 13, Right = 63, center = 38
N6.C0.D0.R0.S17: RdDqDqs FSM results: Left = 08, Right = 63, center = 35
N0.C0.D0.R0.S16: RxDqsDelay = 033
N2.C3.D1.R0.S17: RxDqsDelay = 035
N4.C0.D1.R0.S05: RxDqsDelay = 038
N6.C0.D0.R0.S17: RxDqsDelay = 035
N0.C0.D0.R0.S17: RdDqDqs FSM results: Left = 05, Right = 63, center = 34
N2.C3.D1.R1.S00: RdDqDqs FSM results: Left = 15, Right = 63, center = 39
N4.C0.D1.R0.S06: RdDqDqs FSM results: Left = 16, Right = 63, center = 39
N6.C0.D0.R1.S00: RdDqDqs FSM results: Left = 05, Right = 60, center = 32
N0.C0.D0.R0.S17: RxDqsDelay = 034
N2.C3.D1.R1.S00: RxDqsDelay = 039
N4.C0.D1.R0.S06: RxDqsDelay = 039
N6.C0.D0.R1.S00: RxDqsDelay = 032
N0.C0.D0.R1.S00: RdDqDqs FSM results: Left = 03, Right = 63, center = 33
N2.C3.D1.R1.S01: RdDqDqs FSM results: Left = 07, Right = 63, center = 35
N4.C0.D1.R0.S07: RdDqDqs FSM results: Left = 17, Right = 63, center = 40
N6.C0.D0.R1.S01: RdDqDqs FSM results: Left = 04, Right = 63, center = 33
N0.C0.D0.R1.S00: RxDqsDelay = 033
N2.C3.D1.R1.S01: RxDqsDelay = 035
N4.C0.D1.R0.S07: RxDqsDelay = 040
N6.C0.D0.R1.S01: RxDqsDelay = 033
N0.C0.D0.R1.S01: RdDqDqs FSM results: Left = 03, Right = 63, center = 33
N2.C3.D1.R1.S02: RdDqDqs FSM results: Left = 12, Right = 63, center = 37
N4.C0.D1.R0.S08: RdDqDqs FSM results: Left = 17, Right = 63, center = 40
N6.C0.D0.R1.S02: RdDqDqs FSM results: Left = 05, Right = 63, center = 34
N0.C0.D0.R1.S01: RxDqsDelay = 033
N2.C3.D1.R1.S02: RxDqsDelay = 037
N4.C0.D1.R0.S08: RxDqsDelay = 040
N6.C0.D0.R1.S02: RxDqsDelay = 034
N0.C0.D0.R1.S02: RdDqDqs FSM results: Left = 04, Right = 63, center = 33
N2.C3.D1.R1.S03: RdDqDqs FSM results: Left = 07, Right = 63, center = 35
N4.C0.D1.R0.S09: RdDqDqs FSM results: Left = 17, Right = 63, center = 40
N6.C0.D0.R1.S03: RdDqDqs FSM results: Left = 04, Right = 63, center = 33
N0.C0.D0.R1.S02: RxDqsDelay = 033
N2.C3.D1.R1.S03: RxDqsDelay = 035
N4.C0.D1.R0.S09: RxDqsDelay = 040
N6.C0.D0.R1.S03: RxDqsDelay = 033
N0.C0.D0.R1.S03: RdDqDqs FSM results: Left = 04, Right = 63, center = 33
N2.C3.D1.R1.S04: RdDqDqs FSM results: Left = 10, Right = 63, center = 36
N4.C0.D1.R0.S10: RdDqDqs FSM results: Left = 13, Right = 63, center = 38
N6.C0.D0.R1.S04: RdDqDqs FSM results: Left = 04, Right = 63, center = 33
N0.C0.D0.R1.S03: RxDqsDelay = 033
N2.C3.D1.R1.S04: RxDqsDelay = 036
N4.C0.D1.R0.S10: RxDqsDelay = 038
N6.C0.D0.R1.S04: RxDqsDelay = 033
N0.C0.D0.R1.S04: RdDqDqs FSM results: Left = 05, Right = 63, center = 34
N2.C3.D1.R1.S05: RdDqDqs FSM results: Left = 10, Right = 63, center = 36
N4.C0.D1.R0.S11: RdDqDqs FSM results: Left = 13, Right = 63, center = 38
N6.C0.D0.R1.S05: RdDqDqs FSM results: Left = 05, Right = 63, center = 34
N0.C0.D0.R1.S04: RxDqsDelay = 034
N2.C3.D1.R1.S05: RxDqsDelay = 036
N4.C0.D1.R0.S11: RxDqsDelay = 038
N6.C0.D0.R1.S05: RxDqsDelay = 034
N0.C0.D0.R1.S05: RdDqDqs FSM results: Left = 08, Right = 63, center = 35
N2.C3.D1.R1.S06: RdDqDqs FSM results: Left = 11, Right = 63, center = 37
N4.C0.D1.R0.S12: RdDqDqs FSM results: Left = 15, Right = 63, center = 39
N6.C0.D0.R1.S06: RdDqDqs FSM results: Left = 04, Right = 63, center = 33
N0.C0.D0.R1.S05: RxDqsDelay = 035
N2.C3.D1.R1.S06: RxDqsDelay = 037
N4.C0.D1.R0.S12: RxDqsDelay = 039
N6.C0.D0.R1.S06: RxDqsDelay = 033
N0.C0.D0.R1.S06: RdDqDqs FSM results: Left = 04, Right = 63, center = 33
N2.C3.D1.R1.S07: RdDqDqs FSM results: Left = 11, Right = 63, center = 37
N4.C0.D1.R0.S13: RdDqDqs FSM results: Left = 14, Right = 63, center = 38
N6.C0.D0.R1.S07: RdDqDqs FSM results: Left = 05, Right = 63, center = 34
N0.C0.D0.R1.S06: RxDqsDelay = 033
N2.C3.D1.R1.S07: RxDqsDelay = 037
N4.C0.D1.R0.S13: RxDqsDelay = 038
N6.C0.D0.R1.S07: RxDqsDelay = 034
N0.C0.D0.R1.S07: RdDqDqs FSM results: Left = 06, Right = 63, center = 34
N2.C3.D1.R1.S08: RdDqDqs FSM results: Left = 09, Right = 63, center = 36
N4.C0.D1.R0.S14: RdDqDqs FSM results: Left = 14, Right = 63, center = 38
N6.C0.D0.R1.S08: RdDqDqs FSM results: Left = 05, Right = 63, center = 34
N0.C0.D0.R1.S07: RxDqsDelay = 034
N2.C3.D1.R1.S08: RxDqsDelay = 036
N4.C0.D1.R0.S14: RxDqsDelay = 038
N6.C0.D0.R1.S08: RxDqsDelay = 034
N0.C0.D0.R1.S08: RdDqDqs FSM results: Left = 03, Right = 63, center = 33
N2.C3.D1.R1.S09: RdDqDqs FSM results: Left = 12, Right = 63, center = 37
N4.C0.D1.R0.S15: RdDqDqs FSM results: Left = 12, Right = 63, center = 37
N6.C0.D0.R1.S09: RdDqDqs FSM results: Left = 05, Right = 63, center = 34
N0.C0.D0.R1.S08: RxDqsDelay = 033
N2.C3.D1.R1.S09: RxDqsDelay = 037
N4.C0.D1.R0.S15: RxDqsDelay = 037
N6.C0.D0.R1.S09: RxDqsDelay = 034
N0.C0.D0.R1.S09: RdDqDqs FSM results: Left = 04, Right = 63, center = 33
N2.C3.D1.R1.S10: RdDqDqs FSM results: Left = 08, Right = 63, center = 35
N4.C0.D1.R0.S16: RdDqDqs FSM results: Left = 15, Right = 63, center = 39
N6.C0.D0.R1.S10: RdDqDqs FSM results: Left = 04, Right = 59, center = 31
N0.C0.D0.R1.S09: RxDqsDelay = 033
N2.C3.D1.R1.S10: RxDqsDelay = 035
N4.C0.D1.R0.S16: RxDqsDelay = 039
N6.C0.D0.R1.S10: RxDqsDelay = 031
N0.C0.D0.R1.S10: RdDqDqs FSM results: Left = 05, Right = 63, center = 34
N2.C3.D1.R1.S11: RdDqDqs FSM results: Left = 10, Right = 63, center = 36
N4.C0.D1.R0.S17: RdDqDqs FSM results: Left = 15, Right = 63, center = 39
N6.C0.D0.R1.S11: RdDqDqs FSM results: Left = 04, Right = 61, center = 32
N0.C0.D0.R1.S10: RxDqsDelay = 034
N2.C3.D1.R1.S11: RxDqsDelay = 036
N4.C0.D1.R0.S17: RxDqsDelay = 039
N6.C0.D0.R1.S11: RxDqsDelay = 032
N0.C0.D0.R1.S11: RdDqDqs FSM results: Left = 03, Right = 63, center = 33
N2.C3.D1.R1.S12: RdDqDqs FSM results: Left = 08, Right = 63, center = 35
N4.C0.D1.R1.S00: RdDqDqs FSM results: Left = 12, Right = 63, center = 37
N6.C0.D0.R1.S12: RdDqDqs FSM results: Left = 05, Right = 63, center = 34
N0.C0.D0.R1.S11: RxDqsDelay = 033
N2.C3.D1.R1.S12: RxDqsDelay = 035
N4.C0.D1.R1.S00: RxDqsDelay = 037
N6.C0.D0.R1.S12: RxDqsDelay = 034
N0.C0.D0.R1.S12: RdDqDqs FSM results: Left = 04, Right = 63, center = 33
N2.C3.D1.R1.S13: RdDqDqs FSM results: Left = 09, Right = 63, center = 36
N4.C0.D1.R1.S01: RdDqDqs FSM results: Left = 14, Right = 63, center = 38
N6.C0.D0.R1.S13: RdDqDqs FSM results: Left = 04, Right = 63, center = 33
N0.C0.D0.R1.S12: RxDqsDelay = 033
N2.C3.D1.R1.S13: RxDqsDelay = 036
N4.C0.D1.R1.S01: RxDqsDelay = 038
N6.C0.D0.R1.S13: RxDqsDelay = 033
N0.C0.D0.R1.S13: RdDqDqs FSM results: Left = 06, Right = 63, center = 34
N2.C3.D1.R1.S14: RdDqDqs FSM results: Left = 11, Right = 63, center = 37
N4.C0.D1.R1.S02: RdDqDqs FSM results: Left = 16, Right = 63, center = 39
N6.C0.D0.R1.S14: RdDqDqs FSM results: Left = 06, Right = 63, center = 34
N0.C0.D0.R1.S13: RxDqsDelay = 034
N2.C3.D1.R1.S14: RxDqsDelay = 037
N4.C0.D1.R1.S02: RxDqsDelay = 039
N6.C0.D0.R1.S14: RxDqsDelay = 034
N0.C0.D0.R1.S14: RdDqDqs FSM results: Left = 04, Right = 63, center = 33
N2.C3.D1.R1.S15: RdDqDqs FSM results: Left = 11, Right = 63, center = 37
N4.C0.D1.R1.S03: RdDqDqs FSM results: Left = 12, Right = 63, center = 37
N6.C0.D0.R1.S15: RdDqDqs FSM results: Left = 06, Right = 63, center = 34
N0.C0.D0.R1.S14: RxDqsDelay = 033
N2.C3.D1.R1.S15: RxDqsDelay = 037
N4.C0.D1.R1.S03: RxDqsDelay = 037
N6.C0.D0.R1.S15: RxDqsDelay = 034
N0.C0.D0.R1.S15: RdDqDqs FSM results: Left = 03, Right = 63, center = 33
N2.C3.D1.R1.S16: RdDqDqs FSM results: Left = 12, Right = 63, center = 37
N4.C0.D1.R1.S04: RdDqDqs FSM results: Left = 14, Right = 63, center = 38
N6.C0.D0.R1.S16: RdDqDqs FSM results: Left = 09, Right = 63, center = 36
N0.C0.D0.R1.S15: RxDqsDelay = 033
N2.C3.D1.R1.S16: RxDqsDelay = 037
N4.C0.D1.R1.S04: RxDqsDelay = 038
N6.C0.D0.R1.S16: RxDqsDelay = 036
N0.C0.D0.R1.S16: RdDqDqs FSM results: Left = 02, Right = 63, center = 32
N2.C3.D1.R1.S17: RdDqDqs FSM results: Left = 07, Right = 63, center = 35
N4.C0.D1.R1.S05: RdDqDqs FSM results: Left = 13, Right = 63, center = 38
N6.C0.D0.R1.S17: RdDqDqs FSM results: Left = 06, Right = 63, center = 34
N0.C0.D0.R1.S16: RxDqsDelay = 032
N2.C3.D1.R1.S17: RxDqsDelay = 035
N4.C0.D1.R1.S05: RxDqsDelay = 038
N6.C0.D0.R1.S17: RxDqsDelay = 034
N0.C0.D0.R1.S17: RdDqDqs FSM results: Left = 05, Right = 63, center = 34
START_DATA_RX_DQS
N4.C0.D1.R1.S06: RdDqDqs FSM results: Left = 17, Right = 63, center = 40
N6.C0.D1.R0.S00: RdDqDqs FSM results: Left = 07, Right = 61, center = 34
N0.C0.D0.R1.S17: RxDqsDelay = 034
N2.C3.R0.S00: PI = 36
N4.C0.D1.R1.S06: RxDqsDelay = 040
N6.C0.D1.R0.S00: RxDqsDelay = 034
N0.C0.D1.R0.S00: RdDqDqs FSM results: Left = 07, Right = 63, center = 35
N2.C3.R0.S01: PI = 33
N4.C0.D1.R1.S07: RdDqDqs FSM results: Left = 18, Right = 63, center = 40
N6.C0.D1.R0.S01: RdDqDqs FSM results: Left = 07, Right = 63, center = 35
N0.C0.D1.R0.S00: RxDqsDelay = 035
N2.C3.R0.S02: PI = 36
N4.C0.D1.R1.S07: RxDqsDelay = 040
N6.C0.D1.R0.S01: RxDqsDelay = 035
N0.C0.D1.R0.S01: RdDqDqs FSM results: Left = 08, Right = 63, center = 35
N2.C3.R0.S03: PI = 33
N4.C0.D1.R1.S08: RdDqDqs FSM results: Left = 17, Right = 63, center = 40
N6.C0.D1.R0.S02: RdDqDqs FSM results: Left = 09, Right = 63, center = 36
N0.C0.D1.R0.S01: RxDqsDelay = 035
N2.C3.R0.S04: PI = 34
N4.C0.D1.R1.S08: RxDqsDelay = 040
N6.C0.D1.R0.S02: RxDqsDelay = 036
N0.C0.D1.R0.S02: RdDqDqs FSM results: Left = 08, Right = 63, center = 35
N2.C3.R0.S05: PI = 35
N4.C0.D1.R1.S09: RdDqDqs FSM results: Left = 18, Right = 63, center = 40
N6.C0.D1.R0.S03: RdDqDqs FSM results: Left = 06, Right = 63, center = 34
N0.C0.D1.R0.S02: RxDqsDelay = 035
N2.C3.R0.S06: PI = 36
N4.C0.D1.R1.S09: RxDqsDelay = 040
N6.C0.D1.R0.S03: RxDqsDelay = 034
N0.C0.D1.R0.S03: RdDqDqs FSM results: Left = 06, Right = 63, center = 34
N2.C3.R0.S07: PI = 35
N4.C0.D1.R1.S10: RdDqDqs FSM results: Left = 12, Right = 63, center = 37
N6.C0.D1.R0.S04: RdDqDqs FSM results: Left = 06, Right = 63, center = 34
N0.C0.D1.R0.S03: RxDqsDelay = 034
N2.C3.R0.S08: PI = 33
N4.C0.D1.R1.S10: RxDqsDelay = 037
N6.C0.D1.R0.S04: RxDqsDelay = 034
N0.C0.D1.R0.S04: RdDqDqs FSM results: Left = 08, Right = 63, center = 35
N2.C3.R0.S09: PI = 35
N4.C0.D1.R1.S11: RdDqDqs FSM results: Left = 13, Right = 63, center = 38
N6.C0.D1.R0.S05: RdDqDqs FSM results: Left = 09, Right = 63, center = 36
N0.C0.D1.R0.S04: RxDqsDelay = 035
N2.C3.R0.S10: PI = 33
N4.C0.D1.R1.S11: RxDqsDelay = 038
N6.C0.D1.R0.S05: RxDqsDelay = 036
N0.C0.D1.R0.S05: RdDqDqs FSM results: Left = 10, Right = 63, center = 36
N2.C3.R0.S11: PI = 35
N4.C0.D1.R1.S12: RdDqDqs FSM results: Left = 15, Right = 63, center = 39
N6.C0.D1.R0.S06: RdDqDqs FSM results: Left = 09, Right = 63, center = 36
N0.C0.D1.R0.S05: RxDqsDelay = 036
N2.C3.R0.S12: PI = 33
N4.C0.D1.R1.S12: RxDqsDelay = 039
N6.C0.D1.R0.S06: RxDqsDelay = 036
N0.C0.D1.R0.S06: RdDqDqs FSM results: Left = 09, Right = 63, center = 36
N2.C3.R0.S13: PI = 33
N4.C0.D1.R1.S13: RdDqDqs FSM results: Left = 13, Right = 63, center = 38
N6.C0.D1.R0.S07: RdDqDqs FSM results: Left = 10, Right = 63, center = 36
N0.C0.D1.R0.S06: RxDqsDelay = 036
N2.C3.R0.S14: PI = 35
N4.C0.D1.R1.S13: RxDqsDelay = 038
N6.C0.D1.R0.S07: RxDqsDelay = 036
N0.C0.D1.R0.S07: RdDqDqs FSM results: Left = 09, Right = 63, center = 36
N2.C3.R0.S15: PI = 34
N4.C0.D1.R1.S14: RdDqDqs FSM results: Left = 14, Right = 63, center = 38
N6.C0.D1.R0.S08: RdDqDqs FSM results: Left = 10, Right = 63, center = 36
N0.C0.D1.R0.S07: RxDqsDelay = 036
N2.C3.R0.S16: PI = 36
N4.C0.D1.R1.S14: RxDqsDelay = 038
N6.C0.D1.R0.S08: RxDqsDelay = 036
N0.C0.D1.R0.S08: RdDqDqs FSM results: Left = 06, Right = 63, center = 34
N2.C3.R0.S17: PI = 31
N4.C0.D1.R1.S15: RdDqDqs FSM results: Left = 12, Right = 63, center = 37
N6.C0.D1.R0.S09: RdDqDqs FSM results: Left = 07, Right = 63, center = 35
N0.C0.D1.R0.S08: RxDqsDelay = 034
N2.C3.R0.S00: PI = 36
N4.C0.D1.R1.S15: RxDqsDelay = 037
N6.C0.D1.R0.S09: RxDqsDelay = 035
N0.C0.D1.R0.S09: RdDqDqs FSM results: Left = 09, Right = 63, center = 36
N2.C3.R0.S01: PI = 33
N4.C0.D1.R1.S16: RdDqDqs FSM results: Left = 14, Right = 63, center = 38
N6.C0.D1.R0.S10: RdDqDqs FSM results: Left = 07, Right = 63, center = 35
N0.C0.D1.R0.S09: RxDqsDelay = 036
N2.C3.R0.S02: PI = 36
N4.C0.D1.R1.S16: RxDqsDelay = 038
N6.C0.D1.R0.S10: RxDqsDelay = 035
N0.C0.D1.R0.S10: RdDqDqs FSM results: Left = 08, Right = 63, center = 35
N2.C3.R0.S03: PI = 33
N4.C0.D1.R1.S17: RdDqDqs FSM results: Left = 14, Right = 63, center = 38
N6.C0.D1.R0.S11: RdDqDqs FSM results: Left = 07, Right = 63, center = 35
N0.C0.D1.R0.S10: RxDqsDelay = 035
N2.C3.R0.S04: PI = 34
N4.C0.D1.R1.S17: RxDqsDelay = 038
N6.C0.D1.R0.S11: RxDqsDelay = 035
N0.C0.D1.R0.S11: RdDqDqs FSM results: Left = 06, Right = 63, center = 34
N2.C3.R0.S05: PI = 35
START_DATA_RX_DQS
N6.C0.D1.R0.S12: RdDqDqs FSM results: Left = 07, Right = 63, center = 35
N0.C0.D1.R0.S11: RxDqsDelay = 034
N2.C3.R0.S06: PI = 36
N4.C0.R0.S00: PI = 36
N6.C0.D1.R0.S12: RxDqsDelay = 035
N0.C0.D1.R0.S12: RdDqDqs FSM results: Left = 08, Right = 63, center = 35
N2.C3.R0.S07: PI = 35
N4.C0.R0.S01: PI = 36
N6.C0.D1.R0.S13: RdDqDqs FSM results: Left = 08, Right = 63, center = 35
N0.C0.D1.R0.S12: RxDqsDelay = 035
N2.C3.R0.S08: PI = 33
N4.C0.R0.S02: PI = 38
N6.C0.D1.R0.S13: RxDqsDelay = 035
N0.C0.D1.R0.S13: RdDqDqs FSM results: Left = 09, Right = 63, center = 36
N2.C3.R0.S09: PI = 35
N4.C0.R0.S03: PI = 37
N6.C0.D1.R0.S14: RdDqDqs FSM results: Left = 09, Right = 63, center = 36
N0.C0.D1.R0.S13: RxDqsDelay = 036
N2.C3.R0.S10: PI = 33
N4.C0.R0.S04: PI = 37
N6.C0.D1.R0.S14: RxDqsDelay = 036
N0.C0.D1.R0.S14: RdDqDqs FSM results: Left = 05, Right = 63, center = 34
N2.C3.R0.S11: PI = 35
N4.C0.R0.S05: PI = 37
N6.C0.D1.R0.S15: RdDqDqs FSM results: Left = 10, Right = 63, center = 36
N0.C0.D1.R0.S14: RxDqsDelay = 034
N2.C3.R0.S12: PI = 33
N4.C0.R0.S06: PI = 38
N6.C0.D1.R0.S15: RxDqsDelay = 036
N0.C0.D1.R0.S15: RdDqDqs FSM results: Left = 04, Right = 63, center = 33
N2.C3.R0.S13: PI = 33
N4.C0.R0.S07: PI = 38
N6.C0.D1.R0.S16: RdDqDqs FSM results: Left = 11, Right = 63, center = 37
N0.C0.D1.R0.S15: RxDqsDelay = 033
N2.C3.R0.S14: PI = 35
N4.C0.R0.S08: PI = 37
N6.C0.D1.R0.S16: RxDqsDelay = 037
N0.C0.D1.R0.S16: RdDqDqs FSM results: Left = 05, Right = 63, center = 34
N2.C3.R0.S15: PI = 34
N4.C0.R0.S09: PI = 38
N6.C0.D1.R0.S17: RdDqDqs FSM results: Left = 10, Right = 63, center = 36
N0.C0.D1.R0.S16: RxDqsDelay = 034
N2.C3.R0.S16: PI = 36
N4.C0.R0.S10: PI = 36
N6.C0.D1.R0.S17: RxDqsDelay = 036
N0.C0.D1.R0.S17: RdDqDqs FSM results: Left = 07, Right = 63, center = 35
N2.C3.R0.S17: PI = 31
N4.C0.R0.S11: PI = 37
N6.C0.D1.R1.S00: RdDqDqs FSM results: Left = 08, Right = 63, center = 35
N0.C0.D1.R0.S17: RxDqsDelay = 035
N2.C3.R2.S00: PI = 38
N4.C0.R0.S12: PI = 37
N6.C0.D1.R1.S00: RxDqsDelay = 035
N0.C0.D1.R1.S00: RdDqDqs FSM results: Left = 07, Right = 63, center = 35
N2.C3.R2.S01: PI = 35
N4.C0.R0.S13: PI = 36
N6.C0.D1.R1.S01: RdDqDqs FSM results: Left = 07, Right = 63, center = 35
N0.C0.D1.R1.S00: RxDqsDelay = 035
N2.C3.R2.S02: PI = 37
N4.C0.R0.S14: PI = 37
N6.C0.D1.R1.S01: RxDqsDelay = 035
N0.C0.D1.R1.S01: RdDqDqs FSM results: Left = 07, Right = 63, center = 35
N2.C3.R2.S03: PI = 35
N4.C0.R0.S15: PI = 36
N6.C0.D1.R1.S02: RdDqDqs FSM results: Left = 09, Right = 63, center = 36
N0.C0.D1.R1.S01: RxDqsDelay = 035
N2.C3.R2.S04: PI = 36
N4.C0.R0.S16: PI = 36
N6.C0.D1.R1.S02: RxDqsDelay = 036
N0.C0.D1.R1.S02: RdDqDqs FSM results: Left = 08, Right = 63, center = 35
N2.C3.R2.S05: PI = 36
N4.C0.R0.S17: PI = 36
N6.C0.D1.R1.S03: RdDqDqs FSM results: Left = 07, Right = 63, center = 35
N0.C0.D1.R1.S02: RxDqsDelay = 035
N2.C3.R2.S06: PI = 37
N4.C0.R0.S00: PI = 36
N6.C0.D1.R1.S03: RxDqsDelay = 035
N0.C0.D1.R1.S03: RdDqDqs FSM results: Left = 07, Right = 63, center = 35
N2.C3.R2.S07: PI = 37
N4.C0.R0.S01: PI = 36
N6.C0.D1.R1.S04: RdDqDqs FSM results: Left = 07, Right = 63, center = 35
N0.C0.D1.R1.S03: RxDqsDelay = 035
N2.C3.R2.S08: PI = 36
N4.C0.R0.S02: PI = 38
N6.C0.D1.R1.S04: RxDqsDelay = 035
N0.C0.D1.R1.S04: RdDqDqs FSM results: Left = 08, Right = 63, center = 35
N2.C3.R2.S09: PI = 37
N4.C0.R0.S03: PI = 37
N6.C0.D1.R1.S05: RdDqDqs FSM results: Left = 08, Right = 63, center = 35
N0.C0.D1.R1.S04: RxDqsDelay = 035
N2.C3.R2.S10: PI = 35
N4.C0.R0.S04: PI = 37
N6.C0.D1.R1.S05: RxDqsDelay = 035
N0.C0.D1.R1.S05: RdDqDqs FSM results: Left = 10, Right = 63, center = 36
N2.C3.R2.S11: PI = 36
N4.C0.R0.S05: PI = 37
N6.C0.D1.R1.S06: RdDqDqs FSM results: Left = 07, Right = 63, center = 35
N0.C0.D1.R1.S05: RxDqsDelay = 036
N2.C3.R2.S12: PI = 35
N4.C0.R0.S06: PI = 38
N6.C0.D1.R1.S06: RxDqsDelay = 035
N0.C0.D1.R1.S06: RdDqDqs FSM results: Left = 10, Right = 63, center = 36
N2.C3.R2.S13: PI = 35
N4.C0.R0.S07: PI = 38
N6.C0.D1.R1.S07: RdDqDqs FSM results: Left = 10, Right = 63, center = 36
N0.C0.D1.R1.S06: RxDqsDelay = 036
N2.C3.R2.S14: PI = 36
N4.C0.R0.S08: PI = 37
N6.C0.D1.R1.S07: RxDqsDelay = 036
N0.C0.D1.R1.S07: RdDqDqs FSM results: Left = 09, Right = 63, center = 36
N2.C3.R2.S15: PI = 36
N4.C0.R0.S09: PI = 38
N6.C0.D1.R1.S08: RdDqDqs FSM results: Left = 10, Right = 63, center = 36
N0.C0.D1.R1.S07: RxDqsDelay = 036
N2.C3.R2.S16: PI = 37
N4.C0.R0.S10: PI = 36
N6.C0.D1.R1.S08: RxDqsDelay = 036
N0.C0.D1.R1.S08: RdDqDqs FSM results: Left = 06, Right = 63, center = 34
N2.C3.R2.S17: PI = 35
N4.C0.R0.S11: PI = 37
N6.C0.D1.R1.S09: RdDqDqs FSM results: Left = 08, Right = 63, center = 35
N0.C0.D1.R1.S08: RxDqsDelay = 034
N2.C3.R2.S00: PI = 38
N4.C0.R0.S12: PI = 37
N6.C0.D1.R1.S09: RxDqsDelay = 035
N0.C0.D1.R1.S09: RdDqDqs FSM results: Left = 11, Right = 63, center = 37
N2.C3.R2.S01: PI = 35
N4.C0.R0.S13: PI = 36
N6.C0.D1.R1.S10: RdDqDqs FSM results: Left = 06, Right = 61, center = 33
N0.C0.D1.R1.S09: RxDqsDelay = 037
N2.C3.R2.S02: PI = 37
N4.C0.R0.S14: PI = 37
N6.C0.D1.R1.S10: RxDqsDelay = 033
N0.C0.D1.R1.S10: RdDqDqs FSM results: Left = 09, Right = 63, center = 36
N2.C3.R2.S03: PI = 35
N4.C0.R0.S15: PI = 36
N6.C0.D1.R1.S11: RdDqDqs FSM results: Left = 08, Right = 63, center = 35
N0.C0.D1.R1.S10: RxDqsDelay = 036
N2.C3.R2.S04: PI = 36
N4.C0.R0.S16: PI = 36
N6.C0.D1.R1.S11: RxDqsDelay = 035
N0.C0.D1.R1.S11: RdDqDqs FSM results: Left = 06, Right = 63, center = 34
N2.C3.R2.S05: PI = 36
N4.C0.R0.S17: PI = 36
N6.C0.D1.R1.S12: RdDqDqs FSM results: Left = 07, Right = 63, center = 35
N0.C0.D1.R1.S11: RxDqsDelay = 034
N2.C3.R2.S06: PI = 37
N4.C0.R2.S00: PI = 37
N6.C0.D1.R1.S12: RxDqsDelay = 035
N0.C0.D1.R1.S12: RdDqDqs FSM results: Left = 08, Right = 63, center = 35
N2.C3.R2.S07: PI = 37
N4.C0.R2.S01: PI = 38
N6.C0.D1.R1.S13: RdDqDqs FSM results: Left = 09, Right = 63, center = 36
N0.C0.D1.R1.S12: RxDqsDelay = 035
N2.C3.R2.S08: PI = 36
N4.C0.R2.S02: PI = 39
N6.C0.D1.R1.S13: RxDqsDelay = 036
N0.C0.D1.R1.S13: RdDqDqs FSM results: Left = 09, Right = 63, center = 36
N2.C3.R2.S09: PI = 37
N4.C0.R2.S03: PI = 37
N6.C0.D1.R1.S14: RdDqDqs FSM results: Left = 10, Right = 63, center = 36
N0.C0.D1.R1.S13: RxDqsDelay = 036
N2.C3.R2.S10: PI = 35
N4.C0.R2.S04: PI = 38
N6.C0.D1.R1.S14: RxDqsDelay = 036
N0.C0.D1.R1.S14: RdDqDqs FSM results: Left = 05, Right = 63, center = 34
N2.C3.R2.S11: PI = 36
N4.C0.R2.S05: PI = 38
N6.C0.D1.R1.S15: RdDqDqs FSM results: Left = 11, Right = 63, center = 37
N0.C0.D1.R1.S14: RxDqsDelay = 034
N2.C3.R2.S12: PI = 35
N4.C0.R2.S06: PI = 39
N6.C0.D1.R1.S15: RxDqsDelay = 037
N0.C0.D1.R1.S15: RdDqDqs FSM results: Left = 04, Right = 63, center = 33
N2.C3.R2.S13: PI = 35
N4.C0.R2.S07: PI = 40
N6.C0.D1.R1.S16: RdDqDqs FSM results: Left = 11, Right = 63, center = 37
N0.C0.D1.R1.S15: RxDqsDelay = 033
N2.C3.R2.S14: PI = 36
N4.C0.R2.S08: PI = 40
N6.C0.D1.R1.S16: RxDqsDelay = 037
N0.C0.D1.R1.S16: RdDqDqs FSM results: Left = 05, Right = 63, center = 34
N2.C3.R2.S15: PI = 36
N4.C0.R2.S09: PI = 40
N6.C0.D1.R1.S17: RdDqDqs FSM results: Left = 09, Right = 63, center = 36
N0.C0.D1.R1.S16: RxDqsDelay = 034
N2.C3.R2.S16: PI = 37
N4.C0.R2.S10: PI = 37
N6.C0.D1.R1.S17: RxDqsDelay = 036
N0.C0.D1.R1.S17: RdDqDqs FSM results: Left = 07, Right = 63, center = 35
N2.C3.R2.S17: PI = 35
N4.C0.R2.S11: PI = 38
START_DATA_RX_DQS
N0.C0.D1.R1.S17: RxDqsDelay = 035
STOP_DATA_RX_DQS
N4.C0.R2.S12: PI = 39
N6.C0.R0.S00: PI = 31
START_DATA_RX_DQS
N2: RunTrainStep: Final status = 0
N4.C0.R2.S13: PI = 38
N6.C0.R0.S01: PI = 33
N0.C0.R0.S00: PI = 32

END - Basic Read DQ/DQS Training       Time         7217 ms
N4.C0.R2.S14: PI = 38
N6.C0.R0.S02: PI = 33
N0.C0.R0.S01: PI = 33

START - Basic Receive Enable Training
N4.C0.R2.S15: PI = 37
N6.C0.R0.S03: PI = 33
N0.C0.R0.S02: PI = 33
N2.C0: QCRM debug: extraRcvEnLatency = 0
N4.C0.R2.S16: PI = 38
N6.C0.R0.S04: PI = 33
N0.C0.R0.S03: PI = 33
N2.C0: SettingForTrainingStep: RdCmd2RcvEnLatency = 10, RdPtrOffsetRcvEn = 4
N4.C0.R2.S17: PI = 38
N6.C0.R0.S05: PI = 34
N0.C0.R0.S04: PI = 34
N2.C1: QCRM debug: extraRcvEnLatency = 0
N4.C0.R2.S00: PI = 37
N6.C0.R0.S06: PI = 33
N0.C0.R0.S05: PI = 34
N2.C1: SettingForTrainingStep: RdCmd2RcvEnLatency = 10, RdPtrOffsetRcvEn = 4
N4.C0.R2.S01: PI = 38
N6.C0.R0.S07: PI = 34
N0.C0.R0.S06: PI = 33
N2.C2: QCRM debug: extraRcvEnLatency = 0
N4.C0.R2.S02: PI = 39
N6.C0.R0.S08: PI = 34
N0.C0.R0.S07: PI = 34
N2.C2: SettingForTrainingStep: RdCmd2RcvEnLatency = 10, RdPtrOffsetRcvEn = 4
N4.C0.R2.S03: PI = 37
N6.C0.R0.S09: PI = 33
N0.C0.R0.S08: PI = 33
N2.C3: QCRM debug: extraRcvEnLatency = 0
N4.C0.R2.S04: PI = 38
N6.C0.R0.S10: PI = 31
N0.C0.R0.S09: PI = 33
N2.C3: SettingForTrainingStep: RdCmd2RcvEnLatency = 10, RdPtrOffsetRcvEn = 4
N4.C0.R2.S05: PI = 38
N6.C0.R0.S11: PI = 33
N0.C0.R0.S10: PI = 33
N2.C0.D0.R0: RcvEnFine: Initial RdCmd2RcvEnLatency = 10, Initial RdPtrOffsetRcvEn = 4
N4.C0.R2.S06: PI = 39
N6.C0.R0.S12: PI = 33
N0.C0.R0.S11: PI = 33
N4.C0.R2.S07: PI = 40
N6.C0.R0.S13: PI = 33
N0.C0.R0.S12: PI = 33
N2.C0.D0.R0.S00: Rcv En Fine Value = 271
N4.C0.R2.S08: PI = 40
N6.C0.R0.S14: PI = 34
N0.C0.R0.S13: PI = 34
N2.C0.D0.R0.S01: Rcv En Fine Value = 379
N4.C0.R2.S09: PI = 40
N6.C0.R0.S15: PI = 34
N0.C0.R0.S14: PI = 33
N2.C0.D0.R0.S02: Rcv En Fine Value = 351
N4.C0.R2.S10: PI = 37
N6.C0.R0.S16: PI = 35
N0.C0.R0.S15: PI = 32
N2.C0.D0.R0.S03: Rcv En Fine Value = 329
N4.C0.R2.S11: PI = 38
N6.C0.R0.S17: PI = 34
N0.C0.R0.S16: PI = 32
N2.C0.D0.R0.S04: Rcv En Fine Value = 321
N4.C0.R2.S12: PI = 39
N6.C0.R0.S00: PI = 31
N0.C0.R0.S17: PI = 34
N2.C0.D0.R0.S05: Rcv En Fine Value = 347
N4.C0.R2.S13: PI = 38
N6.C0.R0.S01: PI = 33
N0.C0.R0.S00: PI = 32
N2.C0.D0.R0.S06: Rcv En Fine Value = 376
N4.C0.R2.S14: PI = 38
N6.C0.R0.S02: PI = 33
N0.C0.R0.S01: PI = 33
N2.C0.D0.R0.S07: Rcv En Fine Value = 272
N4.C0.R2.S15: PI = 37
N6.C0.R0.S03: PI = 33
N0.C0.R0.S02: PI = 33
N2.C0.D0.R0.S08: Rcv En Fine Value = 319
N4.C0.R2.S16: PI = 38
N6.C0.R0.S04: PI = 33
N0.C0.R0.S03: PI = 33
N2.C0.D0.R0.S09: Rcv En Fine Value = 271
N4.C0.R2.S17: PI = 38
N6.C0.R0.S05: PI = 34
N0.C0.R0.S04: PI = 34
N2.C0.D0.R0.S10: Rcv En Fine Value = 378
STOP_DATA_RX_DQS
N6.C0.R0.S06: PI = 33
N0.C0.R0.S05: PI = 34
N2.C0.D0.R0.S11: Rcv En Fine Value = 351
N4.C1.D0.R0.S00: RdDqDqs FSM results: Left = 12, Right = 63, center = 37
N6.C0.R0.S07: PI = 34
N0.C0.R0.S06: PI = 33
N2.C0.D0.R0.S12: Rcv En Fine Value = 331
N4.C1.D0.R0.S00: RxDqsDelay = 037
N6.C0.R0.S08: PI = 34
N0.C0.R0.S07: PI = 34
N2.C0.D0.R0.S13: Rcv En Fine Value = 320
N4.C1.D0.R0.S01: RdDqDqs FSM results: Left = 11, Right = 63, center = 37
N6.C0.R0.S09: PI = 33
N0.C0.R0.S08: PI = 33
N2.C0.D0.R0.S14: Rcv En Fine Value = 345
N4.C1.D0.R0.S01: RxDqsDelay = 037
N6.C0.R0.S10: PI = 31
N0.C0.R0.S09: PI = 33
N2.C0.D0.R0.S15: Rcv En Fine Value = 379
N4.C1.D0.R0.S02: RdDqDqs FSM results: Left = 11, Right = 63, center = 37
N6.C0.R0.S11: PI = 33
N0.C0.R0.S10: PI = 33
N2.C0.D0.R0.S16: Rcv En Fine Value = 272
N4.C1.D0.R0.S02: RxDqsDelay = 037
N6.C0.R0.S12: PI = 33
N0.C0.R0.S11: PI = 33
N2.C0.D0.R0.S17: Rcv En Fine Value = 316
N4.C1.D0.R0.S03: RdDqDqs FSM results: Left = 12, Right = 63, center = 37
N6.C0.R0.S13: PI = 33
N0.C0.R0.S12: PI = 33
N2.C0.D0.R0: Starting preamble search lower nibbles
N4.C1.D0.R0.S03: RxDqsDelay = 037
N6.C0.R0.S14: PI = 34
N0.C0.R0.S13: PI = 34
N2.C0.D0.R0.S00: PI = 015, PtrOffset = 004
N4.C1.D0.R0.S04: RdDqDqs FSM results: Left = 13, Right = 63, center = 38
N6.C0.R0.S15: PI = 34
N0.C0.R0.S14: PI = 33
N2.C0.D0.R0.S01: PI = 059, PtrOffset = 005
N4.C1.D0.R0.S04: RxDqsDelay = 038
N6.C0.R0.S16: PI = 35
N0.C0.R0.S15: PI = 32
N2.C0.D0.R0.S02: PI = 031, PtrOffset = 005
N4.C1.D0.R0.S05: RdDqDqs FSM results: Left = 11, Right = 63, center = 37
N6.C0.R0.S17: PI = 34
N0.C0.R0.S16: PI = 32
N2.C0.D0.R0.S03: PI = 009, PtrOffset = 005
N4.C1.D0.R0.S05: RxDqsDelay = 037
N6.C0.R2.S00: PI = 34
N0.C0.R0.S17: PI = 34
N2.C0.D0.R0.S04: PI = 001, PtrOffset = 005
N4.C1.D0.R0.S06: RdDqDqs FSM results: Left = 16, Right = 63, center = 39
N6.C0.R2.S01: PI = 35
N0.C0.R2.S00: PI = 35
N2.C0.D0.R0.S05: PI = 027, PtrOffset = 005
N4.C1.D0.R0.S06: RxDqsDelay = 039
N6.C0.R2.S02: PI = 36
N0.C0.R2.S01: PI = 35
N2.C0.D0.R0.S06: PI = 056, PtrOffset = 005
N4.C1.D0.R0.S07: RdDqDqs FSM results: Left = 16, Right = 63, center = 39
N6.C0.R2.S03: PI = 34
N0.C0.R2.S02: PI = 35
N2.C0.D0.R0.S07: PI = 016, PtrOffset = 004
N4.C1.D0.R0.S07: RxDqsDelay = 039
N6.C0.R2.S04: PI = 34
N0.C0.R2.S03: PI = 34
N2.C0.D0.R0.S08: PI = 063, PtrOffset = 004
N4.C1.D0.R0.S08: RdDqDqs FSM results: Left = 14, Right = 63, center = 38
N6.C0.R2.S05: PI = 35
N0.C0.R2.S04: PI = 35
N2.C0.D0.R0.S00: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N4.C1.D0.R0.S08: RxDqsDelay = 038
N6.C0.R2.S06: PI = 35
N0.C0.R2.S05: PI = 36
N2.C0.D0.R0.S01: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N4.C1.D0.R0.S09: RdDqDqs FSM results: Left = 10, Right = 63, center = 36
N6.C0.R2.S07: PI = 36
N0.C0.R2.S06: PI = 36
N2.C0.D0.R0.S02: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N4.C1.D0.R0.S09: RxDqsDelay = 036
N6.C0.R2.S08: PI = 36
N0.C0.R2.S07: PI = 36
N2.C0.D0.R0.S03: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N4.C1.D0.R0.S10: RdDqDqs FSM results: Left = 09, Right = 63, center = 36
N6.C0.R2.S09: PI = 35
N0.C0.R2.S08: PI = 34
N2.C0.D0.R0.S04: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N4.C1.D0.R0.S10: RxDqsDelay = 036
N6.C0.R2.S10: PI = 34
N0.C0.R2.S09: PI = 36
N2.C0.D0.R0.S05: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N4.C1.D0.R0.S11: RdDqDqs FSM results: Left = 06, Right = 63, center = 34
N6.C0.R2.S11: PI = 35
N0.C0.R2.S10: PI = 35
N2.C0.D0.R0.S06: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N4.C1.D0.R0.S11: RxDqsDelay = 034
N6.C0.R2.S12: PI = 35
N0.C0.R2.S11: PI = 34
N2.C0.D0.R0.S07: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N4.C1.D0.R0.S12: RdDqDqs FSM results: Left = 10, Right = 63, center = 36
N6.C0.R2.S13: PI = 35
N0.C0.R2.S12: PI = 35
N2.C0.D0.R0.S08: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N4.C1.D0.R0.S12: RxDqsDelay = 036
N6.C0.R2.S14: PI = 36
N0.C0.R2.S13: PI = 36
N2.C0.D0.R0.S00: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N4.C1.D0.R0.S13: RdDqDqs FSM results: Left = 12, Right = 63, center = 37
N6.C0.R2.S15: PI = 36
N0.C0.R2.S14: PI = 34
N2.C0.D0.R0.S01: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N4.C1.D0.R0.S13: RxDqsDelay = 037
N6.C0.R2.S16: PI = 37
N0.C0.R2.S15: PI = 33
N2.C0.D0.R0.S02: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N4.C1.D0.R0.S14: RdDqDqs FSM results: Left = 09, Right = 63, center = 36
N6.C0.R2.S17: PI = 36
N0.C0.R2.S16: PI = 34
N2.C0.D0.R0.S03: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N4.C1.D0.R0.S14: RxDqsDelay = 036
N6.C0.R2.S00: PI = 34
N0.C0.R2.S17: PI = 35
N2.C0.D0.R0.S04: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N4.C1.D0.R0.S15: RdDqDqs FSM results: Left = 16, Right = 63, center = 39
N6.C0.R2.S01: PI = 35
N0.C0.R2.S00: PI = 35
N2.C0.D0.R0.S05: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N4.C1.D0.R0.S15: RxDqsDelay = 039
N6.C0.R2.S02: PI = 36
N0.C0.R2.S01: PI = 35
N2.C0.D0.R0.S06: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N4.C1.D0.R0.S16: RdDqDqs FSM results: Left = 11, Right = 63, center = 37
N6.C0.R2.S03: PI = 34
N0.C0.R2.S02: PI = 35
N2.C0.D0.R0.S07: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N4.C1.D0.R0.S16: RxDqsDelay = 037
N6.C0.R2.S04: PI = 34
N0.C0.R2.S03: PI = 34
N2.C0.D0.R0.S08: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N4.C1.D0.R0.S17: RdDqDqs FSM results: Left = 13, Right = 63, center = 38
N6.C0.R2.S05: PI = 35
N0.C0.R2.S04: PI = 35
N2.C0.D0.R0.S00: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N4.C1.D0.R0.S17: RxDqsDelay = 038
N6.C0.R2.S06: PI = 35
N0.C0.R2.S05: PI = 36
N2.C0.D0.R0.S01: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N4.C1.D0.R1.S00: RdDqDqs FSM results: Left = 11, Right = 63, center = 37
N6.C0.R2.S07: PI = 36
N0.C0.R2.S06: PI = 36
N2.C0.D0.R0.S02: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N4.C1.D0.R1.S00: RxDqsDelay = 037
N6.C0.R2.S08: PI = 36
N0.C0.R2.S07: PI = 36
N2.C0.D0.R0.S03: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N4.C1.D0.R1.S01: RdDqDqs FSM results: Left = 11, Right = 63, center = 37
N6.C0.R2.S09: PI = 35
N0.C0.R2.S08: PI = 34
N2.C0.D0.R0.S04: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N4.C1.D0.R1.S01: RxDqsDelay = 037
N6.C0.R2.S10: PI = 34
N0.C0.R2.S09: PI = 36
N2.C0.D0.R0.S05: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N4.C1.D0.R1.S02: RdDqDqs FSM results: Left = 12, Right = 63, center = 37
N6.C0.R2.S11: PI = 35
N0.C0.R2.S10: PI = 35
N2.C0.D0.R0.S06: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N4.C1.D0.R1.S02: RxDqsDelay = 037
N6.C0.R2.S12: PI = 35
N0.C0.R2.S11: PI = 34
N2.C0.D0.R0.S07: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N4.C1.D0.R1.S03: RdDqDqs FSM results: Left = 12, Right = 63, center = 37
N6.C0.R2.S13: PI = 35
N0.C0.R2.S12: PI = 35
N2.C0.D0.R0.S08: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N4.C1.D0.R1.S03: RxDqsDelay = 037
N6.C0.R2.S14: PI = 36
N0.C0.R2.S13: PI = 36
N2.C0.D0.R0.S00: Preamble found at Latency = 008
N4.C1.D0.R1.S04: RdDqDqs FSM results: Left = 13, Right = 63, center = 38
N6.C0.R2.S15: PI = 36
N0.C0.R2.S14: PI = 34
N2.C0.D0.R0.S07: Preamble found at Latency = 008
N4.C1.D0.R1.S04: RxDqsDelay = 038
N6.C0.R2.S16: PI = 37
N0.C0.R2.S15: PI = 33
N2.C0.D0.R0.S00: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N4.C1.D0.R1.S05: RdDqDqs FSM results: Left = 11, Right = 61, center = 36
N6.C0.R2.S17: PI = 36
N0.C0.R2.S16: PI = 34
N2.C0.D0.R0.S01: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N4.C1.D0.R1.S05: RxDqsDelay = 036
STOP_DATA_RX_DQS
N0.C0.R2.S17: PI = 35
N2.C0.D0.R0.S02: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N4.C1.D0.R1.S06: RdDqDqs FSM results: Left = 16, Right = 63, center = 39
N6.C1.D0.R0.S00: RdDqDqs FSM results: Left = 04, Right = 59, center = 31
STOP_DATA_RX_DQS
N2.C0.D0.R0.S03: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N4.C1.D0.R1.S06: RxDqsDelay = 039
N6.C1.D0.R0.S00: RxDqsDelay = 031
N0.C1.D0.R0.S00: RdDqDqs FSM results: Left = 02, Right = 63, center = 32
N2.C0.D0.R0.S04: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N4.C1.D0.R1.S07: RdDqDqs FSM results: Left = 15, Right = 63, center = 39
N6.C1.D0.R0.S01: RdDqDqs FSM results: Left = 05, Right = 63, center = 34
N0.C1.D0.R0.S00: RxDqsDelay = 032
N2.C0.D0.R0.S05: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N4.C1.D0.R1.S07: RxDqsDelay = 039
N6.C1.D0.R0.S01: RxDqsDelay = 034
N0.C1.D0.R0.S01: RdDqDqs FSM results: Left = 06, Right = 63, center = 34
N2.C0.D0.R0.S06: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N4.C1.D0.R1.S08: RdDqDqs FSM results: Left = 13, Right = 63, center = 38
N6.C1.D0.R0.S02: RdDqDqs FSM results: Left = 03, Right = 63, center = 33
N0.C1.D0.R0.S01: RxDqsDelay = 034
N2.C0.D0.R0.S07: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N4.C1.D0.R1.S08: RxDqsDelay = 038
N6.C1.D0.R0.S02: RxDqsDelay = 033
N0.C1.D0.R0.S02: RdDqDqs FSM results: Left = 06, Right = 63, center = 34
N2.C0.D0.R0.S08: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N4.C1.D0.R1.S09: RdDqDqs FSM results: Left = 11, Right = 63, center = 37
N6.C1.D0.R0.S03: RdDqDqs FSM results: Left = 03, Right = 63, center = 33
N0.C1.D0.R0.S02: RxDqsDelay = 034
N2.C0.D0.R0.S01: Preamble found at Latency = 007
N4.C1.D0.R1.S09: RxDqsDelay = 037
N6.C1.D0.R0.S03: RxDqsDelay = 033
N0.C1.D0.R0.S03: RdDqDqs FSM results: Left = 04, Right = 63, center = 33
N2.C0.D0.R0.S02: Preamble found at Latency = 007
N4.C1.D0.R1.S10: RdDqDqs FSM results: Left = 08, Right = 63, center = 35
N6.C1.D0.R0.S04: RdDqDqs FSM results: Left = 05, Right = 63, center = 34
N0.C1.D0.R0.S03: RxDqsDelay = 033
N2.C0.D0.R0.S03: Preamble found at Latency = 007
N4.C1.D0.R1.S10: RxDqsDelay = 035
N6.C1.D0.R0.S04: RxDqsDelay = 034
N0.C1.D0.R0.S04: RdDqDqs FSM results: Left = 02, Right = 63, center = 32
N2.C0.D0.R0.S04: Preamble found at Latency = 007
N4.C1.D0.R1.S11: RdDqDqs FSM results: Left = 07, Right = 63, center = 35
N6.C1.D0.R0.S05: RdDqDqs FSM results: Left = 05, Right = 63, center = 34
N0.C1.D0.R0.S04: RxDqsDelay = 032
N2.C0.D0.R0.S05: Preamble found at Latency = 007
N4.C1.D0.R1.S11: RxDqsDelay = 035
N6.C1.D0.R0.S05: RxDqsDelay = 034
N0.C1.D0.R0.S05: RdDqDqs FSM results: Left = 05, Right = 63, center = 34
N2.C0.D0.R0.S06: Preamble found at Latency = 007
N4.C1.D0.R1.S12: RdDqDqs FSM results: Left = 10, Right = 63, center = 36
N6.C1.D0.R0.S06: RdDqDqs FSM results: Left = 04, Right = 63, center = 33
N0.C1.D0.R0.S05: RxDqsDelay = 034
N2.C0.D0.R0.S08: Preamble found at Latency = 007
N4.C1.D0.R1.S12: RxDqsDelay = 036
N6.C1.D0.R0.S06: RxDqsDelay = 033
N0.C1.D0.R0.S06: RdDqDqs FSM results: Left = 05, Right = 63, center = 34
N2.C0.D0.R0.S00: Total Receive Enable Delay = 1327
N4.C1.D0.R1.S13: RdDqDqs FSM results: Left = 12, Right = 63, center = 37
N6.C1.D0.R0.S07: RdDqDqs FSM results: Left = 05, Right = 63, center = 34
N0.C1.D0.R0.S06: RxDqsDelay = 034
N2.C0.D0.R0.S01: Total Receive Enable Delay = 1307
N4.C1.D0.R1.S13: RxDqsDelay = 037
N6.C1.D0.R0.S07: RxDqsDelay = 034
N0.C1.D0.R0.S07: RdDqDqs FSM results: Left = 05, Right = 61, center = 33
N2.C0.D0.R0.S02: Total Receive Enable Delay = 1279
N4.C1.D0.R1.S14: RdDqDqs FSM results: Left = 08, Right = 58, center = 33
N6.C1.D0.R0.S08: RdDqDqs FSM results: Left = 03, Right = 63, center = 33
N0.C1.D0.R0.S07: RxDqsDelay = 033
N2.C0.D0.R0.S03: Total Receive Enable Delay = 1257
N4.C1.D0.R1.S14: RxDqsDelay = 033
N6.C1.D0.R0.S08: RxDqsDelay = 033
N0.C1.D0.R0.S08: RdDqDqs FSM results: Left = 02, Right = 63, center = 32
N2.C0.D0.R0.S04: Total Receive Enable Delay = 1249
N4.C1.D0.R1.S15: RdDqDqs FSM results: Left = 14, Right = 63, center = 38
N6.C1.D0.R0.S09: RdDqDqs FSM results: Left = 07, Right = 63, center = 35
N0.C1.D0.R0.S08: RxDqsDelay = 032
N2.C0.D0.R0.S05: Total Receive Enable Delay = 1275
N4.C1.D0.R1.S15: RxDqsDelay = 038
N6.C1.D0.R0.S09: RxDqsDelay = 035
N0.C1.D0.R0.S09: RdDqDqs FSM results: Left = 04, Right = 63, center = 33
N2.C0.D0.R0.S06: Total Receive Enable Delay = 1304
N4.C1.D0.R1.S16: RdDqDqs FSM results: Left = 10, Right = 63, center = 36
N6.C1.D0.R0.S10: RdDqDqs FSM results: Left = 04, Right = 63, center = 33
N0.C1.D0.R0.S09: RxDqsDelay = 033
N2.C0.D0.R0.S07: Total Receive Enable Delay = 1328
N4.C1.D0.R1.S16: RxDqsDelay = 036
N6.C1.D0.R0.S10: RxDqsDelay = 033
N0.C1.D0.R0.S10: RdDqDqs FSM results: Left = 05, Right = 63, center = 34
N2.C0.D0.R0.S08: Total Receive Enable Delay = 1247
N4.C1.D0.R1.S17: RdDqDqs FSM results: Left = 12, Right = 63, center = 37
N6.C1.D0.R0.S11: RdDqDqs FSM results: Left = 02, Right = 61, center = 31
N0.C1.D0.R0.S10: RxDqsDelay = 034
N2.C0.D0.R0: Starting preamble search upper nibbles
N4.C1.D0.R1.S17: RxDqsDelay = 037
N6.C1.D0.R0.S11: RxDqsDelay = 031
N0.C1.D0.R0.S11: RdDqDqs FSM results: Left = 02, Right = 63, center = 32
N2.C0.D0.R0.S09: PI = 015, PtrOffset = 004
N4.C1.D1.R0.S00: RdDqDqs FSM results: Left = 15, Right = 63, center = 39
N6.C1.D0.R0.S12: RdDqDqs FSM results: Left = 03, Right = 63, center = 33
N0.C1.D0.R0.S11: RxDqsDelay = 032
N2.C0.D0.R0.S10: PI = 058, PtrOffset = 005
N4.C1.D1.R0.S00: RxDqsDelay = 039
N6.C1.D0.R0.S12: RxDqsDelay = 033
N0.C1.D0.R0.S12: RdDqDqs FSM results: Left = 04, Right = 63, center = 33
N2.C0.D0.R0.S11: PI = 031, PtrOffset = 005
N4.C1.D1.R0.S01: RdDqDqs FSM results: Left = 15, Right = 63, center = 39
N6.C1.D0.R0.S13: RdDqDqs FSM results: Left = 05, Right = 63, center = 34
N0.C1.D0.R0.S12: RxDqsDelay = 033
N2.C0.D0.R0.S12: PI = 011, PtrOffset = 005
N4.C1.D1.R0.S01: RxDqsDelay = 039
N6.C1.D0.R0.S13: RxDqsDelay = 034
N0.C1.D0.R0.S13: RdDqDqs FSM results: Left = 03, Right = 63, center = 33
N2.C0.D0.R0.S13: PI = 000, PtrOffset = 005
N4.C1.D1.R0.S02: RdDqDqs FSM results: Left = 17, Right = 63, center = 40
N6.C1.D0.R0.S14: RdDqDqs FSM results: Left = 05, Right = 63, center = 34
N0.C1.D0.R0.S13: RxDqsDelay = 033
N2.C0.D0.R0.S14: PI = 025, PtrOffset = 005
N4.C1.D1.R0.S02: RxDqsDelay = 040
N6.C1.D0.R0.S14: RxDqsDelay = 034
N0.C1.D0.R0.S14: RdDqDqs FSM results: Left = 06, Right = 63, center = 34
N2.C0.D0.R0.S15: PI = 059, PtrOffset = 005
N4.C1.D1.R0.S03: RdDqDqs FSM results: Left = 17, Right = 63, center = 40
N6.C1.D0.R0.S15: RdDqDqs FSM results: Left = 06, Right = 59, center = 32
N0.C1.D0.R0.S14: RxDqsDelay = 034
N2.C0.D0.R0.S16: PI = 016, PtrOffset = 004
N4.C1.D1.R0.S03: RxDqsDelay = 040
N6.C1.D0.R0.S15: RxDqsDelay = 032
N0.C1.D0.R0.S15: RdDqDqs FSM results: Left = 03, Right = 63, center = 33
N2.C0.D0.R0.S17: PI = 060, PtrOffset = 004
N4.C1.D1.R0.S04: RdDqDqs FSM results: Left = 19, Right = 63, center = 41
N6.C1.D0.R0.S16: RdDqDqs FSM results: Left = 08, Right = 63, center = 35
N0.C1.D0.R0.S15: RxDqsDelay = 033
N2.C0.D0.R0.S09: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N4.C1.D1.R0.S04: RxDqsDelay = 041
N6.C1.D0.R0.S16: RxDqsDelay = 035
N0.C1.D0.R0.S16: RdDqDqs FSM results: Left = 03, Right = 63, center = 33
N2.C0.D0.R0.S10: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N4.C1.D1.R0.S05: RdDqDqs FSM results: Left = 15, Right = 63, center = 39
N6.C1.D0.R0.S17: RdDqDqs FSM results: Left = 03, Right = 63, center = 33
N0.C1.D0.R0.S16: RxDqsDelay = 033
N2.C0.D0.R0.S11: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N4.C1.D1.R0.S05: RxDqsDelay = 039
N6.C1.D0.R0.S17: RxDqsDelay = 033
N0.C1.D0.R0.S17: RdDqDqs FSM results: Left = 01, Right = 61, center = 31
N2.C0.D0.R0.S12: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N4.C1.D1.R0.S06: RdDqDqs FSM results: Left = 18, Right = 63, center = 40
N6.C1.D0.R1.S00: RdDqDqs FSM results: Left = 03, Right = 63, center = 33
N0.C1.D0.R0.S17: RxDqsDelay = 031
N2.C0.D0.R0.S13: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N4.C1.D1.R0.S06: RxDqsDelay = 040
N6.C1.D0.R1.S00: RxDqsDelay = 033
N0.C1.D0.R1.S00: RdDqDqs FSM results: Left = 03, Right = 63, center = 33
N2.C0.D0.R0.S14: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N4.C1.D1.R0.S07: RdDqDqs FSM results: Left = 19, Right = 63, center = 41
N6.C1.D0.R1.S01: RdDqDqs FSM results: Left = 07, Right = 63, center = 35
N0.C1.D0.R1.S00: RxDqsDelay = 033
N2.C0.D0.R0.S15: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N4.C1.D1.R0.S07: RxDqsDelay = 041
N6.C1.D0.R1.S01: RxDqsDelay = 035
N0.C1.D0.R1.S01: RdDqDqs FSM results: Left = 05, Right = 63, center = 34
N2.C0.D0.R0.S16: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N4.C1.D1.R0.S08: RdDqDqs FSM results: Left = 16, Right = 63, center = 39
N6.C1.D0.R1.S02: RdDqDqs FSM results: Left = 02, Right = 63, center = 32
N0.C1.D0.R1.S01: RxDqsDelay = 034
N2.C0.D0.R0.S17: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N4.C1.D1.R0.S08: RxDqsDelay = 039
N6.C1.D0.R1.S02: RxDqsDelay = 032
N0.C1.D0.R1.S02: RdDqDqs FSM results: Left = 05, Right = 63, center = 34
N2.C0.D0.R0.S09: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N4.C1.D1.R0.S09: RdDqDqs FSM results: Left = 13, Right = 63, center = 38
N6.C1.D0.R1.S03: RdDqDqs FSM results: Left = 04, Right = 63, center = 33
N0.C1.D0.R1.S02: RxDqsDelay = 034
N2.C0.D0.R0.S10: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N4.C1.D1.R0.S09: RxDqsDelay = 038
N6.C1.D0.R1.S03: RxDqsDelay = 033
N0.C1.D0.R1.S03: RdDqDqs FSM results: Left = 04, Right = 63, center = 33
N2.C0.D0.R0.S11: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N4.C1.D1.R0.S10: RdDqDqs FSM results: Left = 13, Right = 63, center = 38
N6.C1.D0.R1.S04: RdDqDqs FSM results: Left = 05, Right = 63, center = 34
N0.C1.D0.R1.S03: RxDqsDelay = 033
N2.C0.D0.R0.S12: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N4.C1.D1.R0.S10: RxDqsDelay = 038
N6.C1.D0.R1.S04: RxDqsDelay = 034
N0.C1.D0.R1.S04: RdDqDqs FSM results: Left = 02, Right = 63, center = 32
N2.C0.D0.R0.S13: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N4.C1.D1.R0.S11: RdDqDqs FSM results: Left = 09, Right = 63, center = 36
N6.C1.D0.R1.S05: RdDqDqs FSM results: Left = 06, Right = 63, center = 34
N0.C1.D0.R1.S04: RxDqsDelay = 032
N2.C0.D0.R0.S14: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N4.C1.D1.R0.S11: RxDqsDelay = 036
N6.C1.D0.R1.S05: RxDqsDelay = 034
N0.C1.D0.R1.S05: RdDqDqs FSM results: Left = 04, Right = 63, center = 33
N2.C0.D0.R0.S15: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N4.C1.D1.R0.S12: RdDqDqs FSM results: Left = 15, Right = 63, center = 39
N6.C1.D0.R1.S06: RdDqDqs FSM results: Left = 04, Right = 63, center = 33
N0.C1.D0.R1.S05: RxDqsDelay = 033
N2.C0.D0.R0.S16: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N4.C1.D1.R0.S12: RxDqsDelay = 039
N6.C1.D0.R1.S06: RxDqsDelay = 033
N0.C1.D0.R1.S06: RdDqDqs FSM results: Left = 05, Right = 63, center = 34
N2.C0.D0.R0.S17: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N4.C1.D1.R0.S13: RdDqDqs FSM results: Left = 17, Right = 63, center = 40
N6.C1.D0.R1.S07: RdDqDqs FSM results: Left = 05, Right = 63, center = 34
N0.C1.D0.R1.S06: RxDqsDelay = 034
N2.C0.D0.R0.S09: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N4.C1.D1.R0.S13: RxDqsDelay = 040
N6.C1.D0.R1.S07: RxDqsDelay = 034
N0.C1.D0.R1.S07: RdDqDqs FSM results: Left = 03, Right = 63, center = 33
N2.C0.D0.R0.S10: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N4.C1.D1.R0.S14: RdDqDqs FSM results: Left = 12, Right = 61, center = 36
N6.C1.D0.R1.S08: RdDqDqs FSM results: Left = 03, Right = 63, center = 33
N0.C1.D0.R1.S07: RxDqsDelay = 033
N2.C0.D0.R0.S11: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N4.C1.D1.R0.S14: RxDqsDelay = 036
N6.C1.D0.R1.S08: RxDqsDelay = 033
N0.C1.D0.R1.S08: RdDqDqs FSM results: Left = 02, Right = 63, center = 32
N2.C0.D0.R0.S12: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N4.C1.D1.R0.S15: RdDqDqs FSM results: Left = 18, Right = 63, center = 40
N6.C1.D0.R1.S09: RdDqDqs FSM results: Left = 07, Right = 63, center = 35
N0.C1.D0.R1.S08: RxDqsDelay = 032
N2.C0.D0.R0.S13: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N4.C1.D1.R0.S15: RxDqsDelay = 040
N6.C1.D0.R1.S09: RxDqsDelay = 035
N0.C1.D0.R1.S09: RdDqDqs FSM results: Left = 04, Right = 63, center = 33
N2.C0.D0.R0.S14: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N4.C1.D1.R0.S16: RdDqDqs FSM results: Left = 15, Right = 63, center = 39
N6.C1.D0.R1.S10: RdDqDqs FSM results: Left = 04, Right = 63, center = 33
N0.C1.D0.R1.S09: RxDqsDelay = 033
N2.C0.D0.R0.S15: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N4.C1.D1.R0.S16: RxDqsDelay = 039
N6.C1.D0.R1.S10: RxDqsDelay = 033
N0.C1.D0.R1.S10: RdDqDqs FSM results: Left = 05, Right = 63, center = 34
N2.C0.D0.R0.S16: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N4.C1.D1.R0.S17: RdDqDqs FSM results: Left = 17, Right = 63, center = 40
N6.C1.D0.R1.S11: RdDqDqs FSM results: Left = 02, Right = 59, center = 30
N0.C1.D0.R1.S10: RxDqsDelay = 034
N2.C0.D0.R0.S17: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N4.C1.D1.R0.S17: RxDqsDelay = 040
N6.C1.D0.R1.S11: RxDqsDelay = 030
N0.C1.D0.R1.S11: RdDqDqs FSM results: Left = 02, Right = 63, center = 32
N2.C0.D0.R0.S09: Preamble found at Latency = 008
N4.C1.D1.R1.S00: RdDqDqs FSM results: Left = 15, Right = 63, center = 39
N6.C1.D0.R1.S12: RdDqDqs FSM results: Left = 04, Right = 63, center = 33
N0.C1.D0.R1.S11: RxDqsDelay = 032
N2.C0.D0.R0.S16: Preamble found at Latency = 008
N4.C1.D1.R1.S00: RxDqsDelay = 039
N6.C1.D0.R1.S12: RxDqsDelay = 033
N0.C1.D0.R1.S12: RdDqDqs FSM results: Left = 04, Right = 63, center = 33
N2.C0.D0.R0.S09: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N4.C1.D1.R1.S01: RdDqDqs FSM results: Left = 15, Right = 63, center = 39
N6.C1.D0.R1.S13: RdDqDqs FSM results: Left = 05, Right = 63, center = 34
N0.C1.D0.R1.S12: RxDqsDelay = 033
N2.C0.D0.R0.S10: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N4.C1.D1.R1.S01: RxDqsDelay = 039
N6.C1.D0.R1.S13: RxDqsDelay = 034
N0.C1.D0.R1.S13: RdDqDqs FSM results: Left = 02, Right = 63, center = 32
N2.C0.D0.R0.S11: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N4.C1.D1.R1.S02: RdDqDqs FSM results: Left = 16, Right = 63, center = 39
N6.C1.D0.R1.S14: RdDqDqs FSM results: Left = 05, Right = 63, center = 34
N0.C1.D0.R1.S13: RxDqsDelay = 032
N2.C0.D0.R0.S12: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N4.C1.D1.R1.S02: RxDqsDelay = 039
N6.C1.D0.R1.S14: RxDqsDelay = 034
N0.C1.D0.R1.S14: RdDqDqs FSM results: Left = 05, Right = 63, center = 34
N2.C0.D0.R0.S13: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N4.C1.D1.R1.S03: RdDqDqs FSM results: Left = 16, Right = 63, center = 39
N6.C1.D0.R1.S15: RdDqDqs FSM results: Left = 06, Right = 60, center = 33
N0.C1.D0.R1.S14: RxDqsDelay = 034
N2.C0.D0.R0.S14: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N4.C1.D1.R1.S03: RxDqsDelay = 039
N6.C1.D0.R1.S15: RxDqsDelay = 033
N0.C1.D0.R1.S15: RdDqDqs FSM results: Left = 03, Right = 63, center = 33
N2.C0.D0.R0.S15: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N4.C1.D1.R1.S04: RdDqDqs FSM results: Left = 19, Right = 63, center = 41
N6.C1.D0.R1.S16: RdDqDqs FSM results: Left = 07, Right = 63, center = 35
N0.C1.D0.R1.S15: RxDqsDelay = 033
N2.C0.D0.R0.S16: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N4.C1.D1.R1.S04: RxDqsDelay = 041
N6.C1.D0.R1.S16: RxDqsDelay = 035
N0.C1.D0.R1.S16: RdDqDqs FSM results: Left = 03, Right = 60, center = 31
N2.C0.D0.R0.S17: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N4.C1.D1.R1.S05: RdDqDqs FSM results: Left = 16, Right = 63, center = 39
N6.C1.D0.R1.S17: RdDqDqs FSM results: Left = 03, Right = 63, center = 33
N0.C1.D0.R1.S16: RxDqsDelay = 031
N2.C0.D0.R0.S10: Preamble found at Latency = 007
N4.C1.D1.R1.S05: RxDqsDelay = 039
N6.C1.D0.R1.S17: RxDqsDelay = 033
N0.C1.D0.R1.S17: RdDqDqs FSM results: Left = 01, Right = 61, center = 31
N2.C0.D0.R0.S11: Preamble found at Latency = 007
N4.C1.D1.R1.S06: RdDqDqs FSM results: Left = 19, Right = 63, center = 41
N6.C1.D1.R0.S00: RdDqDqs FSM results: Left = 07, Right = 63, center = 35
N0.C1.D0.R1.S17: RxDqsDelay = 031
N2.C0.D0.R0.S12: Preamble found at Latency = 007
N4.C1.D1.R1.S06: RxDqsDelay = 041
N6.C1.D1.R0.S00: RxDqsDelay = 035
N0.C1.D1.R0.S00: RdDqDqs FSM results: Left = 06, Right = 63, center = 34
N2.C0.D0.R0.S13: Preamble found at Latency = 007
N4.C1.D1.R1.S07: RdDqDqs FSM results: Left = 20, Right = 63, center = 41
N6.C1.D1.R0.S01: RdDqDqs FSM results: Left = 09, Right = 63, center = 36
N0.C1.D1.R0.S00: RxDqsDelay = 034
N2.C0.D0.R0.S14: Preamble found at Latency = 007
N4.C1.D1.R1.S07: RxDqsDelay = 041
N6.C1.D1.R0.S01: RxDqsDelay = 036
N0.C1.D1.R0.S01: RdDqDqs FSM results: Left = 08, Right = 63, center = 35
N2.C0.D0.R0.S15: Preamble found at Latency = 007
N4.C1.D1.R1.S08: RdDqDqs FSM results: Left = 17, Right = 63, center = 40
N6.C1.D1.R0.S02: RdDqDqs FSM results: Left = 06, Right = 63, center = 34
N0.C1.D1.R0.S01: RxDqsDelay = 035
N2.C0.D0.R0.S17: Preamble found at Latency = 007
N4.C1.D1.R1.S08: RxDqsDelay = 040
N6.C1.D1.R0.S02: RxDqsDelay = 034
N0.C1.D1.R0.S02: RdDqDqs FSM results: Left = 09, Right = 63, center = 36
N2.C0.D0.R0: Preamble found for all upper nibbles, adjusting Pi, Offset to center into preamble
N4.C1.D1.R1.S09: RdDqDqs FSM results: Left = 13, Right = 63, center = 38
N6.C1.D1.R0.S03: RdDqDqs FSM results: Left = 08, Right = 63, center = 35
N0.C1.D1.R0.S02: RxDqsDelay = 036
N2.C0.D0.R0.S09: Total Receive Enable Delay = 1327
N4.C1.D1.R1.S09: RxDqsDelay = 038
N6.C1.D1.R0.S03: RxDqsDelay = 035
N0.C1.D1.R0.S03: RdDqDqs FSM results: Left = 06, Right = 63, center = 34
N2.C0.D0.R0.S10: Total Receive Enable Delay = 1306
N4.C1.D1.R1.S10: RdDqDqs FSM results: Left = 13, Right = 63, center = 38
N6.C1.D1.R0.S04: RdDqDqs FSM results: Left = 09, Right = 63, center = 36
N0.C1.D1.R0.S03: RxDqsDelay = 034
N2.C0.D0.R0.S11: Total Receive Enable Delay = 1279
N4.C1.D1.R1.S10: RxDqsDelay = 038
N6.C1.D1.R0.S04: RxDqsDelay = 036
N0.C1.D1.R0.S04: RdDqDqs FSM results: Left = 06, Right = 63, center = 34
N2.C0.D0.R0.S12: Total Receive Enable Delay = 1259
N4.C1.D1.R1.S11: RdDqDqs FSM results: Left = 09, Right = 63, center = 36
N6.C1.D1.R0.S05: RdDqDqs FSM results: Left = 09, Right = 63, center = 36
N0.C1.D1.R0.S04: RxDqsDelay = 034
N2.C0.D0.R0.S13: Total Receive Enable Delay = 1248
N4.C1.D1.R1.S11: RxDqsDelay = 036
N6.C1.D1.R0.S05: RxDqsDelay = 036
N0.C1.D1.R0.S05: RdDqDqs FSM results: Left = 08, Right = 63, center = 35
N2.C0.D0.R0.S14: Total Receive Enable Delay = 1273
N4.C1.D1.R1.S12: RdDqDqs FSM results: Left = 16, Right = 63, center = 39
N6.C1.D1.R0.S06: RdDqDqs FSM results: Left = 09, Right = 63, center = 36
N0.C1.D1.R0.S05: RxDqsDelay = 035
N2.C0.D0.R0.S15: Total Receive Enable Delay = 1307
N4.C1.D1.R1.S12: RxDqsDelay = 039
N6.C1.D1.R0.S06: RxDqsDelay = 036
N0.C1.D1.R0.S06: RdDqDqs FSM results: Left = 08, Right = 63, center = 35
N2.C0.D0.R0.S16: Total Receive Enable Delay = 1328
N4.C1.D1.R1.S13: RdDqDqs FSM results: Left = 17, Right = 63, center = 40
N6.C1.D1.R0.S07: RdDqDqs FSM results: Left = 08, Right = 63, center = 35
N0.C1.D1.R0.S06: RxDqsDelay = 035
N2.C0.D0.R0.S17: Total Receive Enable Delay = 1244
N4.C1.D1.R1.S13: RxDqsDelay = 040
N6.C1.D1.R0.S07: RxDqsDelay = 035
N0.C1.D1.R0.S07: RdDqDqs FSM results: Left = 08, Right = 63, center = 35
N2.C0.D0.R1: RcvEnFine: Initial RdCmd2RcvEnLatency = 10, Initial RdPtrOffsetRcvEn = 4
N4.C1.D1.R1.S14: RdDqDqs FSM results: Left = 12, Right = 63, center = 37
N6.C1.D1.R0.S08: RdDqDqs FSM results: Left = 07, Right = 63, center = 35
N0.C1.D1.R0.S07: RxDqsDelay = 035
N2.C0.D0.R1.S00: Rcv En Fine Value = 271
N4.C1.D1.R1.S14: RxDqsDelay = 037
N6.C1.D1.R0.S08: RxDqsDelay = 035
N0.C1.D1.R0.S08: RdDqDqs FSM results: Left = 05, Right = 63, center = 34
N2.C0.D0.R1.S01: Rcv En Fine Value = 379
N4.C1.D1.R1.S15: RdDqDqs FSM results: Left = 18, Right = 63, center = 40
N6.C1.D1.R0.S09: RdDqDqs FSM results: Left = 12, Right = 63, center = 37
N0.C1.D1.R0.S08: RxDqsDelay = 034
N2.C0.D0.R1.S02: Rcv En Fine Value = 350
N4.C1.D1.R1.S15: RxDqsDelay = 040
N6.C1.D1.R0.S09: RxDqsDelay = 037
N0.C1.D1.R0.S09: RdDqDqs FSM results: Left = 08, Right = 63, center = 35
N2.C0.D0.R1.S03: Rcv En Fine Value = 328
N4.C1.D1.R1.S16: RdDqDqs FSM results: Left = 14, Right = 63, center = 38
N6.C1.D1.R0.S10: RdDqDqs FSM results: Left = 08, Right = 63, center = 35
N0.C1.D1.R0.S09: RxDqsDelay = 035
N2.C0.D0.R1.S04: Rcv En Fine Value = 322
N4.C1.D1.R1.S16: RxDqsDelay = 038
N6.C1.D1.R0.S10: RxDqsDelay = 035
N0.C1.D1.R0.S10: RdDqDqs FSM results: Left = 09, Right = 63, center = 36
N2.C0.D0.R1.S05: Rcv En Fine Value = 346
N4.C1.D1.R1.S17: RdDqDqs FSM results: Left = 18, Right = 63, center = 40
N6.C1.D1.R0.S11: RdDqDqs FSM results: Left = 04, Right = 63, center = 33
N0.C1.D1.R0.S10: RxDqsDelay = 036
N2.C0.D0.R1.S06: Rcv En Fine Value = 380
N4.C1.D1.R1.S17: RxDqsDelay = 040
N6.C1.D1.R0.S11: RxDqsDelay = 033
N0.C1.D1.R0.S11: RdDqDqs FSM results: Left = 05, Right = 63, center = 34
N2.C0.D0.R1.S07: Rcv En Fine Value = 272
START_DATA_RX_DQS
N6.C1.D1.R0.S12: RdDqDqs FSM results: Left = 06, Right = 63, center = 34
N0.C1.D1.R0.S11: RxDqsDelay = 034
N2.C0.D0.R1.S08: Rcv En Fine Value = 316
N4.C1.R0.S00: PI = 37
N6.C1.D1.R0.S12: RxDqsDelay = 034
N0.C1.D1.R0.S12: RdDqDqs FSM results: Left = 06, Right = 63, center = 34
N2.C0.D0.R1.S09: Rcv En Fine Value = 270
N4.C1.R0.S01: PI = 37
N6.C1.D1.R0.S13: RdDqDqs FSM results: Left = 08, Right = 63, center = 35
N0.C1.D1.R0.S12: RxDqsDelay = 034
N2.C0.D0.R1.S10: Rcv En Fine Value = 381
N4.C1.R0.S02: PI = 37
N6.C1.D1.R0.S13: RxDqsDelay = 035
N0.C1.D1.R0.S13: RdDqDqs FSM results: Left = 07, Right = 63, center = 35
N2.C0.D0.R1.S11: Rcv En Fine Value = 352
N4.C1.R0.S03: PI = 37
N6.C1.D1.R0.S14: RdDqDqs FSM results: Left = 09, Right = 63, center = 36
N0.C1.D1.R0.S13: RxDqsDelay = 035
N2.C0.D0.R1.S12: Rcv En Fine Value = 331
N4.C1.R0.S04: PI = 38
N6.C1.D1.R0.S14: RxDqsDelay = 036
N0.C1.D1.R0.S14: RdDqDqs FSM results: Left = 07, Right = 63, center = 35
N2.C0.D0.R1.S13: Rcv En Fine Value = 320
N4.C1.R0.S05: PI = 36
N6.C1.D1.R0.S15: RdDqDqs FSM results: Left = 10, Right = 63, center = 36
N0.C1.D1.R0.S14: RxDqsDelay = 035
N2.C0.D0.R1.S14: Rcv En Fine Value = 345
N4.C1.R0.S06: PI = 39
N6.C1.D1.R0.S15: RxDqsDelay = 036
N0.C1.D1.R0.S15: RdDqDqs FSM results: Left = 05, Right = 63, center = 34
N2.C0.D0.R1.S15: Rcv En Fine Value = 378
N4.C1.R0.S07: PI = 39
N6.C1.D1.R0.S16: RdDqDqs FSM results: Left = 10, Right = 63, center = 36
N0.C1.D1.R0.S15: RxDqsDelay = 034
N2.C0.D0.R1.S16: Rcv En Fine Value = 271
N4.C1.R0.S08: PI = 38
N6.C1.D1.R0.S16: RxDqsDelay = 036
N0.C1.D1.R0.S16: RdDqDqs FSM results: Left = 05, Right = 63, center = 34
N2.C0.D0.R1.S17: Rcv En Fine Value = 316
N4.C1.R0.S09: PI = 36
N6.C1.D1.R0.S17: RdDqDqs FSM results: Left = 07, Right = 63, center = 35
N0.C1.D1.R0.S16: RxDqsDelay = 034
N2.C0.D0.R1: Starting preamble search lower nibbles
N4.C1.R0.S10: PI = 35
N6.C1.D1.R0.S17: RxDqsDelay = 035
N0.C1.D1.R0.S17: RdDqDqs FSM results: Left = 04, Right = 63, center = 33
N2.C0.D0.R1.S00: PI = 015, PtrOffset = 004
N4.C1.R0.S11: PI = 34
N6.C1.D1.R1.S00: RdDqDqs FSM results: Left = 07, Right = 63, center = 35
N0.C1.D1.R0.S17: RxDqsDelay = 033
N2.C0.D0.R1.S01: PI = 059, PtrOffset = 005
N4.C1.R0.S12: PI = 36
N6.C1.D1.R1.S00: RxDqsDelay = 035
N0.C1.D1.R1.S00: RdDqDqs FSM results: Left = 06, Right = 63, center = 34
N2.C0.D0.R1.S02: PI = 030, PtrOffset = 005
N4.C1.R0.S13: PI = 37
N6.C1.D1.R1.S01: RdDqDqs FSM results: Left = 10, Right = 63, center = 36
N0.C1.D1.R1.S00: RxDqsDelay = 034
N2.C0.D0.R1.S03: PI = 008, PtrOffset = 005
N4.C1.R0.S14: PI = 34
N6.C1.D1.R1.S01: RxDqsDelay = 036
N0.C1.D1.R1.S01: RdDqDqs FSM results: Left = 08, Right = 63, center = 35
N2.C0.D0.R1.S04: PI = 002, PtrOffset = 005
N4.C1.R0.S15: PI = 38
N6.C1.D1.R1.S02: RdDqDqs FSM results: Left = 05, Right = 63, center = 34
N0.C1.D1.R1.S01: RxDqsDelay = 035
N2.C0.D0.R1.S05: PI = 026, PtrOffset = 005
N4.C1.R0.S16: PI = 36
N6.C1.D1.R1.S02: RxDqsDelay = 034
N0.C1.D1.R1.S02: RdDqDqs FSM results: Left = 08, Right = 63, center = 35
N2.C0.D0.R1.S06: PI = 060, PtrOffset = 005
N4.C1.R0.S17: PI = 37
N6.C1.D1.R1.S03: RdDqDqs FSM results: Left = 07, Right = 63, center = 35
N0.C1.D1.R1.S02: RxDqsDelay = 035
N2.C0.D0.R1.S07: PI = 016, PtrOffset = 004
N4.C1.R0.S00: PI = 37
N6.C1.D1.R1.S03: RxDqsDelay = 035
N0.C1.D1.R1.S03: RdDqDqs FSM results: Left = 06, Right = 63, center = 34
N2.C0.D0.R1.S08: PI = 060, PtrOffset = 004
N4.C1.R0.S01: PI = 37
N6.C1.D1.R1.S04: RdDqDqs FSM results: Left = 08, Right = 63, center = 35
N0.C1.D1.R1.S03: RxDqsDelay = 034
N2.C0.D0.R1.S00: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N4.C1.R0.S02: PI = 37
N6.C1.D1.R1.S04: RxDqsDelay = 035
N0.C1.D1.R1.S04: RdDqDqs FSM results: Left = 06, Right = 63, center = 34
N2.C0.D0.R1.S01: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N4.C1.R0.S03: PI = 37
N6.C1.D1.R1.S05: RdDqDqs FSM results: Left = 09, Right = 63, center = 36
N0.C1.D1.R1.S04: RxDqsDelay = 034
N2.C0.D0.R1.S02: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N4.C1.R0.S04: PI = 38
N6.C1.D1.R1.S05: RxDqsDelay = 036
N0.C1.D1.R1.S05: RdDqDqs FSM results: Left = 08, Right = 63, center = 35
N2.C0.D0.R1.S03: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N4.C1.R0.S05: PI = 36
N6.C1.D1.R1.S06: RdDqDqs FSM results: Left = 10, Right = 63, center = 36
N0.C1.D1.R1.S05: RxDqsDelay = 035
N2.C0.D0.R1.S04: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N4.C1.R0.S06: PI = 39
N6.C1.D1.R1.S06: RxDqsDelay = 036
N0.C1.D1.R1.S06: RdDqDqs FSM results: Left = 08, Right = 63, center = 35
N2.C0.D0.R1.S05: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N4.C1.R0.S07: PI = 39
N6.C1.D1.R1.S07: RdDqDqs FSM results: Left = 09, Right = 63, center = 36
N0.C1.D1.R1.S06: RxDqsDelay = 035
N2.C0.D0.R1.S06: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N4.C1.R0.S08: PI = 38
N6.C1.D1.R1.S07: RxDqsDelay = 036
N0.C1.D1.R1.S07: RdDqDqs FSM results: Left = 08, Right = 61, center = 34
N2.C0.D0.R1.S07: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N4.C1.R0.S09: PI = 36
N6.C1.D1.R1.S08: RdDqDqs FSM results: Left = 08, Right = 63, center = 35
N0.C1.D1.R1.S07: RxDqsDelay = 034
N2.C0.D0.R1.S08: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N4.C1.R0.S10: PI = 35
N6.C1.D1.R1.S08: RxDqsDelay = 035
N0.C1.D1.R1.S08: RdDqDqs FSM results: Left = 05, Right = 63, center = 34
N2.C0.D0.R1.S00: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N4.C1.R0.S11: PI = 34
N6.C1.D1.R1.S09: RdDqDqs FSM results: Left = 12, Right = 63, center = 37
N0.C1.D1.R1.S08: RxDqsDelay = 034
N2.C0.D0.R1.S01: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N4.C1.R0.S12: PI = 36
N6.C1.D1.R1.S09: RxDqsDelay = 037
N0.C1.D1.R1.S09: RdDqDqs FSM results: Left = 08, Right = 63, center = 35
N2.C0.D0.R1.S02: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N4.C1.R0.S13: PI = 37
N6.C1.D1.R1.S10: RdDqDqs FSM results: Left = 08, Right = 63, center = 35
N0.C1.D1.R1.S09: RxDqsDelay = 035
N2.C0.D0.R1.S03: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N4.C1.R0.S14: PI = 34
N6.C1.D1.R1.S10: RxDqsDelay = 035
N0.C1.D1.R1.S10: RdDqDqs FSM results: Left = 09, Right = 63, center = 36
N2.C0.D0.R1.S04: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N4.C1.R0.S15: PI = 38
N6.C1.D1.R1.S11: RdDqDqs FSM results: Left = 04, Right = 63, center = 33
N0.C1.D1.R1.S10: RxDqsDelay = 036
N2.C0.D0.R1.S05: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N4.C1.R0.S16: PI = 36
N6.C1.D1.R1.S11: RxDqsDelay = 033
N0.C1.D1.R1.S11: RdDqDqs FSM results: Left = 03, Right = 63, center = 33
N2.C0.D0.R1.S06: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N4.C1.R0.S17: PI = 37
N6.C1.D1.R1.S12: RdDqDqs FSM results: Left = 07, Right = 63, center = 35
N0.C1.D1.R1.S11: RxDqsDelay = 033
N2.C0.D0.R1.S07: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N4.C1.R2.S00: PI = 39
N6.C1.D1.R1.S12: RxDqsDelay = 035
N0.C1.D1.R1.S12: RdDqDqs FSM results: Left = 06, Right = 63, center = 34
N2.C0.D0.R1.S08: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N4.C1.R2.S01: PI = 39
N6.C1.D1.R1.S13: RdDqDqs FSM results: Left = 10, Right = 63, center = 36
N0.C1.D1.R1.S12: RxDqsDelay = 034
N2.C0.D0.R1.S00: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N4.C1.R2.S02: PI = 39
N6.C1.D1.R1.S13: RxDqsDelay = 036
N0.C1.D1.R1.S13: RdDqDqs FSM results: Left = 06, Right = 63, center = 34
N2.C0.D0.R1.S01: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N4.C1.R2.S03: PI = 39
N6.C1.D1.R1.S14: RdDqDqs FSM results: Left = 09, Right = 63, center = 36
N0.C1.D1.R1.S13: RxDqsDelay = 034
N2.C0.D0.R1.S02: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N4.C1.R2.S04: PI = 41
N6.C1.D1.R1.S14: RxDqsDelay = 036
N0.C1.D1.R1.S14: RdDqDqs FSM results: Left = 05, Right = 63, center = 34
N2.C0.D0.R1.S03: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N4.C1.R2.S05: PI = 39
N6.C1.D1.R1.S15: RdDqDqs FSM results: Left = 09, Right = 63, center = 36
N0.C1.D1.R1.S14: RxDqsDelay = 034
N2.C0.D0.R1.S04: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N4.C1.R2.S06: PI = 40
N6.C1.D1.R1.S15: RxDqsDelay = 036
N0.C1.D1.R1.S15: RdDqDqs FSM results: Left = 05, Right = 63, center = 34
N2.C0.D0.R1.S05: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N4.C1.R2.S07: PI = 41
N6.C1.D1.R1.S16: RdDqDqs FSM results: Left = 09, Right = 63, center = 36
N0.C1.D1.R1.S15: RxDqsDelay = 034
N2.C0.D0.R1.S06: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N4.C1.R2.S08: PI = 39
N6.C1.D1.R1.S16: RxDqsDelay = 036
N0.C1.D1.R1.S16: RdDqDqs FSM results: Left = 05, Right = 63, center = 34
N2.C0.D0.R1.S07: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N4.C1.R2.S09: PI = 38
N6.C1.D1.R1.S17: RdDqDqs FSM results: Left = 06, Right = 63, center = 34
N0.C1.D1.R1.S16: RxDqsDelay = 034
N2.C0.D0.R1.S08: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N4.C1.R2.S10: PI = 38
N6.C1.D1.R1.S17: RxDqsDelay = 034
N0.C1.D1.R1.S17: RdDqDqs FSM results: Left = 04, Right = 63, center = 33
N2.C0.D0.R1.S00: Preamble found at Latency = 008
N4.C1.R2.S11: PI = 36
START_DATA_RX_DQS
N0.C1.D1.R1.S17: RxDqsDelay = 033
N2.C0.D0.R1.S07: Preamble found at Latency = 008
N4.C1.R2.S12: PI = 39
N6.C1.R0.S00: PI = 32
START_DATA_RX_DQS
N2.C0.D0.R1.S00: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N4.C1.R2.S13: PI = 40
N6.C1.R0.S01: PI = 34
N0.C1.R0.S00: PI = 32
N2.C0.D0.R1.S01: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N4.C1.R2.S14: PI = 36
N6.C1.R0.S02: PI = 32
N0.C1.R0.S01: PI = 34
N2.C0.D0.R1.S02: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N4.C1.R2.S15: PI = 40
N6.C1.R0.S03: PI = 33
N0.C1.R0.S02: PI = 34
N2.C0.D0.R1.S03: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N4.C1.R2.S16: PI = 38
N6.C1.R0.S04: PI = 34
N0.C1.R0.S03: PI = 33
N2.C0.D0.R1.S04: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N4.C1.R2.S17: PI = 40
N6.C1.R0.S05: PI = 34
N0.C1.R0.S04: PI = 32
N2.C0.D0.R1.S05: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N4.C1.R2.S00: PI = 39
N6.C1.R0.S06: PI = 33
N0.C1.R0.S05: PI = 33
N2.C0.D0.R1.S06: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N4.C1.R2.S01: PI = 39
N6.C1.R0.S07: PI = 34
N0.C1.R0.S06: PI = 34
N2.C0.D0.R1.S07: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N4.C1.R2.S02: PI = 39
N6.C1.R0.S08: PI = 33
N0.C1.R0.S07: PI = 33
N2.C0.D0.R1.S08: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N4.C1.R2.S03: PI = 39
N6.C1.R0.S09: PI = 35
N0.C1.R0.S08: PI = 32
N2.C0.D0.R1.S01: Preamble found at Latency = 007
N4.C1.R2.S04: PI = 41
N6.C1.R0.S10: PI = 33
N0.C1.R0.S09: PI = 33
N2.C0.D0.R1.S02: Preamble found at Latency = 007
N4.C1.R2.S05: PI = 39
N6.C1.R0.S11: PI = 30
N0.C1.R0.S10: PI = 34
N2.C0.D0.R1.S03: Preamble found at Latency = 007
N4.C1.R2.S06: PI = 40
N6.C1.R0.S12: PI = 33
N0.C1.R0.S11: PI = 32
N2.C0.D0.R1.S04: Preamble found at Latency = 007
N4.C1.R2.S07: PI = 41
N6.C1.R0.S13: PI = 34
N0.C1.R0.S12: PI = 33
N2.C0.D0.R1.S05: Preamble found at Latency = 007
N4.C1.R2.S08: PI = 39
N6.C1.R0.S14: PI = 34
N0.C1.R0.S13: PI = 32
N2.C0.D0.R1.S06: Preamble found at Latency = 007
N4.C1.R2.S09: PI = 38
N6.C1.R0.S15: PI = 32
N0.C1.R0.S14: PI = 34
N2.C0.D0.R1.S08: Preamble found at Latency = 007
N4.C1.R2.S10: PI = 38
N6.C1.R0.S16: PI = 35
N0.C1.R0.S15: PI = 33
N2.C0.D0.R1.S00: Total Receive Enable Delay = 1327
N4.C1.R2.S11: PI = 36
N6.C1.R0.S17: PI = 33
N0.C1.R0.S16: PI = 32
N2.C0.D0.R1.S01: Total Receive Enable Delay = 1307
N4.C1.R2.S12: PI = 39
N6.C1.R0.S00: PI = 32
N0.C1.R0.S17: PI = 31
N2.C0.D0.R1.S02: Total Receive Enable Delay = 1278
N4.C1.R2.S13: PI = 40
N6.C1.R0.S01: PI = 34
N0.C1.R0.S00: PI = 32
N2.C0.D0.R1.S03: Total Receive Enable Delay = 1256
N4.C1.R2.S14: PI = 36
N6.C1.R0.S02: PI = 32
N0.C1.R0.S01: PI = 34
N2.C0.D0.R1.S04: Total Receive Enable Delay = 1250
N4.C1.R2.S15: PI = 40
N6.C1.R0.S03: PI = 33
N0.C1.R0.S02: PI = 34
N2.C0.D0.R1.S05: Total Receive Enable Delay = 1274
N4.C1.R2.S16: PI = 38
N6.C1.R0.S04: PI = 34
N0.C1.R0.S03: PI = 33
N2.C0.D0.R1.S06: Total Receive Enable Delay = 1308
N4.C1.R2.S17: PI = 40
N6.C1.R0.S05: PI = 34
N0.C1.R0.S04: PI = 32
N2.C0.D0.R1.S07: Total Receive Enable Delay = 1328
STOP_DATA_RX_DQS
N6.C1.R0.S06: PI = 33
N0.C1.R0.S05: PI = 33
N2.C0.D0.R1.S08: Total Receive Enable Delay = 1244
N4.C2.D0.R0.S00: RdDqDqs FSM results: Left = 09, Right = 63, center = 36
N6.C1.R0.S07: PI = 34
N0.C1.R0.S06: PI = 34
N2.C0.D0.R1: Starting preamble search upper nibbles
N4.C2.D0.R0.S00: RxDqsDelay = 036
N6.C1.R0.S08: PI = 33
N0.C1.R0.S07: PI = 33
N2.C0.D0.R1.S09: PI = 014, PtrOffset = 004
N4.C2.D0.R0.S01: RdDqDqs FSM results: Left = 12, Right = 63, center = 37
N6.C1.R0.S09: PI = 35
N0.C1.R0.S08: PI = 32
N2.C0.D0.R1.S10: PI = 061, PtrOffset = 005
N4.C2.D0.R0.S01: RxDqsDelay = 037
N6.C1.R0.S10: PI = 33
N0.C1.R0.S09: PI = 33
N2.C0.D0.R1.S11: PI = 032, PtrOffset = 005
N4.C2.D0.R0.S02: RdDqDqs FSM results: Left = 10, Right = 63, center = 36
N6.C1.R0.S11: PI = 30
N0.C1.R0.S10: PI = 34
N2.C0.D0.R1.S12: PI = 011, PtrOffset = 005
N4.C2.D0.R0.S02: RxDqsDelay = 036
N6.C1.R0.S12: PI = 33
N0.C1.R0.S11: PI = 32
N2.C0.D0.R1.S13: PI = 000, PtrOffset = 005
N4.C2.D0.R0.S03: RdDqDqs FSM results: Left = 08, Right = 63, center = 35
N6.C1.R0.S13: PI = 34
N0.C1.R0.S12: PI = 33
N2.C0.D0.R1.S14: PI = 025, PtrOffset = 005
N4.C2.D0.R0.S03: RxDqsDelay = 035
N6.C1.R0.S14: PI = 34
N0.C1.R0.S13: PI = 32
N2.C0.D0.R1.S15: PI = 058, PtrOffset = 005
N4.C2.D0.R0.S04: RdDqDqs FSM results: Left = 10, Right = 63, center = 36
N6.C1.R0.S15: PI = 32
N0.C1.R0.S14: PI = 34
N2.C0.D0.R1.S16: PI = 015, PtrOffset = 004
N4.C2.D0.R0.S04: RxDqsDelay = 036
N6.C1.R0.S16: PI = 35
N0.C1.R0.S15: PI = 33
N2.C0.D0.R1.S17: PI = 060, PtrOffset = 004
N4.C2.D0.R0.S05: RdDqDqs FSM results: Left = 12, Right = 63, center = 37
N6.C1.R0.S17: PI = 33
N0.C1.R0.S16: PI = 32
N2.C0.D0.R1.S09: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N4.C2.D0.R0.S05: RxDqsDelay = 037
N6.C1.R2.S00: PI = 35
N0.C1.R0.S17: PI = 31
N2.C0.D0.R1.S10: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N4.C2.D0.R0.S06: RdDqDqs FSM results: Left = 13, Right = 63, center = 38
N6.C1.R2.S01: PI = 36
N0.C1.R2.S00: PI = 34
N2.C0.D0.R1.S11: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N4.C2.D0.R0.S06: RxDqsDelay = 038
N6.C1.R2.S02: PI = 34
N0.C1.R2.S01: PI = 35
N2.C0.D0.R1.S12: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N4.C2.D0.R0.S07: RdDqDqs FSM results: Left = 12, Right = 63, center = 37
N6.C1.R2.S03: PI = 35
N0.C1.R2.S02: PI = 35
N2.C0.D0.R1.S13: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N4.C2.D0.R0.S07: RxDqsDelay = 037
N6.C1.R2.S04: PI = 35
N0.C1.R2.S03: PI = 34
N2.C0.D0.R1.S14: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N4.C2.D0.R0.S08: RdDqDqs FSM results: Left = 12, Right = 63, center = 37
N6.C1.R2.S05: PI = 36
N0.C1.R2.S04: PI = 34
N2.C0.D0.R1.S15: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N4.C2.D0.R0.S08: RxDqsDelay = 037
N6.C1.R2.S06: PI = 36
N0.C1.R2.S05: PI = 35
N2.C0.D0.R1.S16: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N4.C2.D0.R0.S09: RdDqDqs FSM results: Left = 09, Right = 63, center = 36
N6.C1.R2.S07: PI = 35
N0.C1.R2.S06: PI = 35
N2.C0.D0.R1.S17: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N4.C2.D0.R0.S09: RxDqsDelay = 036
N6.C1.R2.S08: PI = 35
N0.C1.R2.S07: PI = 34
N2.C0.D0.R1.S09: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N4.C2.D0.R0.S10: RdDqDqs FSM results: Left = 15, Right = 63, center = 39
N6.C1.R2.S09: PI = 37
N0.C1.R2.S08: PI = 34
N2.C0.D0.R1.S10: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N4.C2.D0.R0.S10: RxDqsDelay = 039
N6.C1.R2.S10: PI = 35
N0.C1.R2.S09: PI = 35
N2.C0.D0.R1.S11: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N4.C2.D0.R0.S11: RdDqDqs FSM results: Left = 05, Right = 63, center = 34
N6.C1.R2.S11: PI = 33
N0.C1.R2.S10: PI = 36
N2.C0.D0.R1.S12: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N4.C2.D0.R0.S11: RxDqsDelay = 034
N6.C1.R2.S12: PI = 34
N0.C1.R2.S11: PI = 33
N2.C0.D0.R1.S13: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N4.C2.D0.R0.S12: RdDqDqs FSM results: Left = 10, Right = 63, center = 36
N6.C1.R2.S13: PI = 35
N0.C1.R2.S12: PI = 34
N2.C0.D0.R1.S14: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N4.C2.D0.R0.S12: RxDqsDelay = 036
N6.C1.R2.S14: PI = 36
N0.C1.R2.S13: PI = 34
N2.C0.D0.R1.S15: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N4.C2.D0.R0.S13: RdDqDqs FSM results: Left = 06, Right = 59, center = 32
N6.C1.R2.S15: PI = 36
N0.C1.R2.S14: PI = 34
N2.C0.D0.R1.S16: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N4.C2.D0.R0.S13: RxDqsDelay = 032
N6.C1.R2.S16: PI = 36
N0.C1.R2.S15: PI = 34
N2.C0.D0.R1.S17: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N4.C2.D0.R0.S14: RdDqDqs FSM results: Left = 14, Right = 63, center = 38
N6.C1.R2.S17: PI = 34
N0.C1.R2.S16: PI = 34
N2.C0.D0.R1.S09: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N4.C2.D0.R0.S14: RxDqsDelay = 038
N6.C1.R2.S00: PI = 35
N0.C1.R2.S17: PI = 33
N2.C0.D0.R1.S10: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N4.C2.D0.R0.S15: RdDqDqs FSM results: Left = 11, Right = 63, center = 37
N6.C1.R2.S01: PI = 36
N0.C1.R2.S00: PI = 34
N2.C0.D0.R1.S11: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N4.C2.D0.R0.S15: RxDqsDelay = 037
N6.C1.R2.S02: PI = 34
N0.C1.R2.S01: PI = 35
N2.C0.D0.R1.S12: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N4.C2.D0.R0.S16: RdDqDqs FSM results: Left = 09, Right = 63, center = 36
N6.C1.R2.S03: PI = 35
N0.C1.R2.S02: PI = 35
N2.C0.D0.R1.S13: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N4.C2.D0.R0.S16: RxDqsDelay = 036
N6.C1.R2.S04: PI = 35
N0.C1.R2.S03: PI = 34
N2.C0.D0.R1.S14: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N4.C2.D0.R0.S17: RdDqDqs FSM results: Left = 09, Right = 63, center = 36
N6.C1.R2.S05: PI = 36
N0.C1.R2.S04: PI = 34
N2.C0.D0.R1.S15: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N4.C2.D0.R0.S17: RxDqsDelay = 036
N6.C1.R2.S06: PI = 36
N0.C1.R2.S05: PI = 35
N2.C0.D0.R1.S16: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N4.C2.D0.R1.S00: RdDqDqs FSM results: Left = 09, Right = 63, center = 36
N6.C1.R2.S07: PI = 35
N0.C1.R2.S06: PI = 35
N2.C0.D0.R1.S17: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N4.C2.D0.R1.S00: RxDqsDelay = 036
N6.C1.R2.S08: PI = 35
N0.C1.R2.S07: PI = 34
N2.C0.D0.R1.S09: Preamble found at Latency = 008
N4.C2.D0.R1.S01: RdDqDqs FSM results: Left = 12, Right = 63, center = 37
N6.C1.R2.S09: PI = 37
N0.C1.R2.S08: PI = 34
N2.C0.D0.R1.S16: Preamble found at Latency = 008
N4.C2.D0.R1.S01: RxDqsDelay = 037
N6.C1.R2.S10: PI = 35
N0.C1.R2.S09: PI = 35
N2.C0.D0.R1.S09: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N4.C2.D0.R1.S02: RdDqDqs FSM results: Left = 09, Right = 63, center = 36
N6.C1.R2.S11: PI = 33
N0.C1.R2.S10: PI = 36
N2.C0.D0.R1.S10: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N4.C2.D0.R1.S02: RxDqsDelay = 036
N6.C1.R2.S12: PI = 34
N0.C1.R2.S11: PI = 33
N2.C0.D0.R1.S11: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N4.C2.D0.R1.S03: RdDqDqs FSM results: Left = 09, Right = 63, center = 36
N6.C1.R2.S13: PI = 35
N0.C1.R2.S12: PI = 34
N2.C0.D0.R1.S12: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N4.C2.D0.R1.S03: RxDqsDelay = 036
N6.C1.R2.S14: PI = 36
N0.C1.R2.S13: PI = 34
N2.C0.D0.R1.S13: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N4.C2.D0.R1.S04: RdDqDqs FSM results: Left = 10, Right = 63, center = 36
N6.C1.R2.S15: PI = 36
N0.C1.R2.S14: PI = 34
N2.C0.D0.R1.S14: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N4.C2.D0.R1.S04: RxDqsDelay = 036
N6.C1.R2.S16: PI = 36
N0.C1.R2.S15: PI = 34
N2.C0.D0.R1.S15: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N4.C2.D0.R1.S05: RdDqDqs FSM results: Left = 11, Right = 63, center = 37
N6.C1.R2.S17: PI = 34
N0.C1.R2.S16: PI = 34
N2.C0.D0.R1.S16: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N4.C2.D0.R1.S05: RxDqsDelay = 037
STOP_DATA_RX_DQS
N0.C1.R2.S17: PI = 33
N2.C0.D0.R1.S17: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N4.C2.D0.R1.S06: RdDqDqs FSM results: Left = 13, Right = 63, center = 38
N6.C2.D0.R0.S00: RdDqDqs FSM results: Left = 01, Right = 63, center = 32
STOP_DATA_RX_DQS
N2.C0.D0.R1.S10: Preamble found at Latency = 007
N4.C2.D0.R1.S06: RxDqsDelay = 038
N6.C2.D0.R0.S00: RxDqsDelay = 032
N0.C2.D0.R0.S00: RdDqDqs FSM results: Left = 03, Right = 63, center = 33
N2.C0.D0.R1.S11: Preamble found at Latency = 007
N4.C2.D0.R1.S07: RdDqDqs FSM results: Left = 11, Right = 63, center = 37
N6.C2.D0.R0.S01: RdDqDqs FSM results: Left = 05, Right = 63, center = 34
N0.C2.D0.R0.S00: RxDqsDelay = 033
N2.C0.D0.R1.S12: Preamble found at Latency = 007
N4.C2.D0.R1.S07: RxDqsDelay = 037
N6.C2.D0.R0.S01: RxDqsDelay = 034
N0.C2.D0.R0.S01: RdDqDqs FSM results: Left = 07, Right = 63, center = 35
N2.C0.D0.R1.S13: Preamble found at Latency = 007
N4.C2.D0.R1.S08: RdDqDqs FSM results: Left = 13, Right = 63, center = 38
N6.C2.D0.R0.S02: RdDqDqs FSM results: Left = 03, Right = 63, center = 33
N0.C2.D0.R0.S01: RxDqsDelay = 035
N2.C0.D0.R1.S14: Preamble found at Latency = 007
N4.C2.D0.R1.S08: RxDqsDelay = 038
N6.C2.D0.R0.S02: RxDqsDelay = 033
N0.C2.D0.R0.S02: RdDqDqs FSM results: Left = 05, Right = 63, center = 34
N2.C0.D0.R1.S15: Preamble found at Latency = 007
N4.C2.D0.R1.S09: RdDqDqs FSM results: Left = 09, Right = 63, center = 36
N6.C2.D0.R0.S03: RdDqDqs FSM results: Left = 04, Right = 63, center = 33
N0.C2.D0.R0.S02: RxDqsDelay = 034
N2.C0.D0.R1.S17: Preamble found at Latency = 007
N4.C2.D0.R1.S09: RxDqsDelay = 036
N6.C2.D0.R0.S03: RxDqsDelay = 033
N0.C2.D0.R0.S03: RdDqDqs FSM results: Left = 07, Right = 63, center = 35
N2.C0.D0.R1: Preamble found for all upper nibbles, adjusting Pi, Offset to center into preamble
N4.C2.D0.R1.S10: RdDqDqs FSM results: Left = 14, Right = 63, center = 38
N6.C2.D0.R0.S04: RdDqDqs FSM results: Left = 02, Right = 59, center = 30
N0.C2.D0.R0.S03: RxDqsDelay = 035
N2.C0.D0.R1.S09: Total Receive Enable Delay = 1326
N4.C2.D0.R1.S10: RxDqsDelay = 038
N6.C2.D0.R0.S04: RxDqsDelay = 030
N0.C2.D0.R0.S04: RdDqDqs FSM results: Left = 03, Right = 63, center = 33
N2.C0.D0.R1.S10: Total Receive Enable Delay = 1309
N4.C2.D0.R1.S11: RdDqDqs FSM results: Left = 06, Right = 63, center = 34
N6.C2.D0.R0.S05: RdDqDqs FSM results: Left = 07, Right = 63, center = 35
N0.C2.D0.R0.S04: RxDqsDelay = 033
N2.C0.D0.R1.S11: Total Receive Enable Delay = 1280
N4.C2.D0.R1.S11: RxDqsDelay = 034
N6.C2.D0.R0.S05: RxDqsDelay = 035
N0.C2.D0.R0.S05: RdDqDqs FSM results: Left = 07, Right = 63, center = 35
N2.C0.D0.R1.S12: Total Receive Enable Delay = 1259
N4.C2.D0.R1.S12: RdDqDqs FSM results: Left = 10, Right = 63, center = 36
N6.C2.D0.R0.S06: RdDqDqs FSM results: Left = 05, Right = 63, center = 34
N0.C2.D0.R0.S05: RxDqsDelay = 035
N2.C0.D0.R1.S13: Total Receive Enable Delay = 1248
N4.C2.D0.R1.S12: RxDqsDelay = 036
N6.C2.D0.R0.S06: RxDqsDelay = 034
N0.C2.D0.R0.S06: RdDqDqs FSM results: Left = 07, Right = 63, center = 35
N2.C0.D0.R1.S14: Total Receive Enable Delay = 1273
N4.C2.D0.R1.S13: RdDqDqs FSM results: Left = 06, Right = 59, center = 32
N6.C2.D0.R0.S07: RdDqDqs FSM results: Left = 09, Right = 63, center = 36
N0.C2.D0.R0.S06: RxDqsDelay = 035
N2.C0.D0.R1.S15: Total Receive Enable Delay = 1306
N4.C2.D0.R1.S13: RxDqsDelay = 032
N6.C2.D0.R0.S07: RxDqsDelay = 036
N0.C2.D0.R0.S07: RdDqDqs FSM results: Left = 05, Right = 63, center = 34
N2.C0.D0.R1.S16: Total Receive Enable Delay = 1327
N4.C2.D0.R1.S14: RdDqDqs FSM results: Left = 14, Right = 63, center = 38
N6.C2.D0.R0.S08: RdDqDqs FSM results: Left = 09, Right = 63, center = 36
N0.C2.D0.R0.S07: RxDqsDelay = 034
N2.C0.D0.R1.S17: Total Receive Enable Delay = 1244
N4.C2.D0.R1.S14: RxDqsDelay = 038
N6.C2.D0.R0.S08: RxDqsDelay = 036
N0.C2.D0.R0.S08: RdDqDqs FSM results: Left = 04, Right = 63, center = 33
N2.C0.D1.R0: RcvEnFine: Initial RdCmd2RcvEnLatency = 10, Initial RdPtrOffsetRcvEn = 4
N4.C2.D0.R1.S15: RdDqDqs FSM results: Left = 11, Right = 63, center = 37
N6.C2.D0.R0.S09: RdDqDqs FSM results: Left = 04, Right = 63, center = 33
N0.C2.D0.R0.S08: RxDqsDelay = 033
N2.C0.D1.R0.S00: Rcv En Fine Value = 256
N4.C2.D0.R1.S15: RxDqsDelay = 037
N6.C2.D0.R0.S09: RxDqsDelay = 033
N0.C2.D0.R0.S09: RdDqDqs FSM results: Left = 02, Right = 61, center = 31
N2.C0.D1.R0.S01: Rcv En Fine Value = 369
N4.C2.D0.R1.S16: RdDqDqs FSM results: Left = 09, Right = 63, center = 36
N6.C2.D0.R0.S10: RdDqDqs FSM results: Left = 02, Right = 63, center = 32
N0.C2.D0.R0.S09: RxDqsDelay = 031
N2.C0.D1.R0.S02: Rcv En Fine Value = 339
N4.C2.D0.R1.S16: RxDqsDelay = 036
N6.C2.D0.R0.S10: RxDqsDelay = 032
N0.C2.D0.R0.S10: RdDqDqs FSM results: Left = 04, Right = 63, center = 33
N2.C0.D1.R0.S03: Rcv En Fine Value = 318
N4.C2.D0.R1.S17: RdDqDqs FSM results: Left = 10, Right = 63, center = 36
N6.C2.D0.R0.S11: RdDqDqs FSM results: Left = 02, Right = 63, center = 32
N0.C2.D0.R0.S10: RxDqsDelay = 033
N2.C0.D1.R0.S04: Rcv En Fine Value = 312
N4.C2.D0.R1.S17: RxDqsDelay = 036
N6.C2.D0.R0.S11: RxDqsDelay = 032
N0.C2.D0.R0.S11: RdDqDqs FSM results: Left = 03, Right = 63, center = 33
N2.C0.D1.R0.S05: Rcv En Fine Value = 335
N4.C2.D1.R0.S00: RdDqDqs FSM results: Left = 13, Right = 63, center = 38
N6.C2.D0.R0.S12: RdDqDqs FSM results: Left = 04, Right = 63, center = 33
N0.C2.D0.R0.S11: RxDqsDelay = 033
N2.C0.D1.R0.S06: Rcv En Fine Value = 366
N4.C2.D1.R0.S00: RxDqsDelay = 038
N6.C2.D0.R0.S12: RxDqsDelay = 033
N0.C2.D0.R0.S12: RdDqDqs FSM results: Left = 04, Right = 63, center = 33
N2.C0.D1.R0.S07: Rcv En Fine Value = 261
N4.C2.D1.R0.S01: RdDqDqs FSM results: Left = 16, Right = 63, center = 39
N6.C2.D0.R0.S13: RdDqDqs FSM results: Left = 03, Right = 63, center = 33
N0.C2.D0.R0.S12: RxDqsDelay = 033
N2.C0.D1.R0.S08: Rcv En Fine Value = 305
N4.C2.D1.R0.S01: RxDqsDelay = 039
N6.C2.D0.R0.S13: RxDqsDelay = 033
N0.C2.D0.R0.S13: RdDqDqs FSM results: Left = 04, Right = 63, center = 33
N2.C0.D1.R0.S09: Rcv En Fine Value = 259
N4.C2.D1.R0.S02: RdDqDqs FSM results: Left = 11, Right = 63, center = 37
N6.C2.D0.R0.S14: RdDqDqs FSM results: Left = 05, Right = 63, center = 34
N0.C2.D0.R0.S13: RxDqsDelay = 033
N2.C0.D1.R0.S10: Rcv En Fine Value = 365
N4.C2.D1.R0.S02: RxDqsDelay = 037
N6.C2.D0.R0.S14: RxDqsDelay = 034
N0.C2.D0.R0.S14: RdDqDqs FSM results: Left = 05, Right = 63, center = 34
N2.C0.D1.R0.S11: Rcv En Fine Value = 339
N4.C2.D1.R0.S03: RdDqDqs FSM results: Left = 10, Right = 63, center = 36
N6.C2.D0.R0.S15: RdDqDqs FSM results: Left = 03, Right = 63, center = 33
N0.C2.D0.R0.S14: RxDqsDelay = 034
N2.C0.D1.R0.S12: Rcv En Fine Value = 318
N4.C2.D1.R0.S03: RxDqsDelay = 036
N6.C2.D0.R0.S15: RxDqsDelay = 033
N0.C2.D0.R0.S15: RdDqDqs FSM results: Left = 05, Right = 63, center = 34
N2.C0.D1.R0.S13: Rcv En Fine Value = 310
N4.C2.D1.R0.S04: RdDqDqs FSM results: Left = 12, Right = 63, center = 37
N6.C2.D0.R0.S16: RdDqDqs FSM results: Left = 06, Right = 63, center = 34
N0.C2.D0.R0.S15: RxDqsDelay = 034
N2.C0.D1.R0.S14: Rcv En Fine Value = 333
N4.C2.D1.R0.S04: RxDqsDelay = 037
N6.C2.D0.R0.S16: RxDqsDelay = 034
N0.C2.D0.R0.S16: RdDqDqs FSM results: Left = 04, Right = 63, center = 33
N2.C0.D1.R0.S15: Rcv En Fine Value = 362
N4.C2.D1.R0.S05: RdDqDqs FSM results: Left = 13, Right = 63, center = 38
N6.C2.D0.R0.S17: RdDqDqs FSM results: Left = 02, Right = 60, center = 31
N0.C2.D0.R0.S16: RxDqsDelay = 033
N2.C0.D1.R0.S16: Rcv En Fine Value = 259
N4.C2.D1.R0.S05: RxDqsDelay = 038
N6.C2.D0.R0.S17: RxDqsDelay = 031
N0.C2.D0.R0.S17: RdDqDqs FSM results: Left = 07, Right = 63, center = 35
N2.C0.D1.R0.S17: Rcv En Fine Value = 304
N4.C2.D1.R0.S06: RdDqDqs FSM results: Left = 17, Right = 63, center = 40
N6.C2.D0.R1.S00: RdDqDqs FSM results: Left = 01, Right = 59, center = 30
N0.C2.D0.R0.S17: RxDqsDelay = 035
N2.C0.D1.R0: Starting preamble search lower nibbles
N4.C2.D1.R0.S06: RxDqsDelay = 040
N6.C2.D0.R1.S00: RxDqsDelay = 030
N0.C2.D0.R1.S00: RdDqDqs FSM results: Left = 04, Right = 63, center = 33
N2.C0.D1.R0.S00: PI = 000, PtrOffset = 004
N4.C2.D1.R0.S07: RdDqDqs FSM results: Left = 16, Right = 63, center = 39
N6.C2.D0.R1.S01: RdDqDqs FSM results: Left = 06, Right = 63, center = 34
N0.C2.D0.R1.S00: RxDqsDelay = 033
N2.C0.D1.R0.S01: PI = 049, PtrOffset = 005
N4.C2.D1.R0.S07: RxDqsDelay = 039
N6.C2.D0.R1.S01: RxDqsDelay = 034
N0.C2.D0.R1.S01: RdDqDqs FSM results: Left = 08, Right = 63, center = 35
N2.C0.D1.R0.S02: PI = 019, PtrOffset = 005
N4.C2.D1.R0.S08: RdDqDqs FSM results: Left = 16, Right = 63, center = 39
N6.C2.D0.R1.S02: RdDqDqs FSM results: Left = 03, Right = 63, center = 33
N0.C2.D0.R1.S01: RxDqsDelay = 035
N2.C0.D1.R0.S03: PI = 062, PtrOffset = 004
N4.C2.D1.R0.S08: RxDqsDelay = 039
N6.C2.D0.R1.S02: RxDqsDelay = 033
N0.C2.D0.R1.S02: RdDqDqs FSM results: Left = 04, Right = 63, center = 33
N2.C0.D1.R0.S04: PI = 056, PtrOffset = 004
N4.C2.D1.R0.S09: RdDqDqs FSM results: Left = 12, Right = 63, center = 37
N6.C2.D0.R1.S03: RdDqDqs FSM results: Left = 05, Right = 63, center = 34
N0.C2.D0.R1.S02: RxDqsDelay = 033
N2.C0.D1.R0.S05: PI = 015, PtrOffset = 005
N4.C2.D1.R0.S09: RxDqsDelay = 037
N6.C2.D0.R1.S03: RxDqsDelay = 034
N0.C2.D0.R1.S03: RdDqDqs FSM results: Left = 06, Right = 63, center = 34
N2.C0.D1.R0.S06: PI = 046, PtrOffset = 005
N4.C2.D1.R0.S10: RdDqDqs FSM results: Left = 20, Right = 63, center = 41
N6.C2.D0.R1.S04: RdDqDqs FSM results: Left = 02, Right = 61, center = 31
N0.C2.D0.R1.S03: RxDqsDelay = 034
N2.C0.D1.R0.S07: PI = 005, PtrOffset = 004
N4.C2.D1.R0.S10: RxDqsDelay = 041
N6.C2.D0.R1.S04: RxDqsDelay = 031
N0.C2.D0.R1.S04: RdDqDqs FSM results: Left = 03, Right = 63, center = 33
N2.C0.D1.R0.S08: PI = 049, PtrOffset = 004
N4.C2.D1.R0.S11: RdDqDqs FSM results: Left = 10, Right = 63, center = 36
N6.C2.D0.R1.S05: RdDqDqs FSM results: Left = 07, Right = 63, center = 35
N0.C2.D0.R1.S04: RxDqsDelay = 033
N2.C0.D1.R0.S00: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N4.C2.D1.R0.S11: RxDqsDelay = 036
N6.C2.D0.R1.S05: RxDqsDelay = 035
N0.C2.D0.R1.S05: RdDqDqs FSM results: Left = 07, Right = 63, center = 35
N2.C0.D1.R0.S01: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N4.C2.D1.R0.S12: RdDqDqs FSM results: Left = 14, Right = 63, center = 38
N6.C2.D0.R1.S06: RdDqDqs FSM results: Left = 05, Right = 63, center = 34
N0.C2.D0.R1.S05: RxDqsDelay = 035
N2.C0.D1.R0.S02: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N4.C2.D1.R0.S12: RxDqsDelay = 038
N6.C2.D0.R1.S06: RxDqsDelay = 034
N0.C2.D0.R1.S06: RdDqDqs FSM results: Left = 07, Right = 63, center = 35
N2.C0.D1.R0.S03: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N4.C2.D1.R0.S13: RdDqDqs FSM results: Left = 09, Right = 63, center = 36
N6.C2.D0.R1.S07: RdDqDqs FSM results: Left = 08, Right = 63, center = 35
N0.C2.D0.R1.S06: RxDqsDelay = 035
N2.C0.D1.R0.S04: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N4.C2.D1.R0.S13: RxDqsDelay = 036
N6.C2.D0.R1.S07: RxDqsDelay = 035
N0.C2.D0.R1.S07: RdDqDqs FSM results: Left = 05, Right = 63, center = 34
N2.C0.D1.R0.S05: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N4.C2.D1.R0.S14: RdDqDqs FSM results: Left = 18, Right = 63, center = 40
N6.C2.D0.R1.S08: RdDqDqs FSM results: Left = 09, Right = 63, center = 36
N0.C2.D0.R1.S07: RxDqsDelay = 034
N2.C0.D1.R0.S06: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N4.C2.D1.R0.S14: RxDqsDelay = 040
N6.C2.D0.R1.S08: RxDqsDelay = 036
N0.C2.D0.R1.S08: RdDqDqs FSM results: Left = 04, Right = 63, center = 33
N2.C0.D1.R0.S07: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N4.C2.D1.R0.S15: RdDqDqs FSM results: Left = 16, Right = 63, center = 39
N6.C2.D0.R1.S09: RdDqDqs FSM results: Left = 04, Right = 63, center = 33
N0.C2.D0.R1.S08: RxDqsDelay = 033
N2.C0.D1.R0.S08: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N4.C2.D1.R0.S15: RxDqsDelay = 039
N6.C2.D0.R1.S09: RxDqsDelay = 033
N0.C2.D0.R1.S09: RdDqDqs FSM results: Left = 03, Right = 60, center = 31
N2.C0.D1.R0.S00: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N4.C2.D1.R0.S16: RdDqDqs FSM results: Left = 12, Right = 63, center = 37
N6.C2.D0.R1.S10: RdDqDqs FSM results: Left = 03, Right = 63, center = 33
N0.C2.D0.R1.S09: RxDqsDelay = 031
N2.C0.D1.R0.S01: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N4.C2.D1.R0.S16: RxDqsDelay = 037
N6.C2.D0.R1.S10: RxDqsDelay = 033
N0.C2.D0.R1.S10: RdDqDqs FSM results: Left = 04, Right = 63, center = 33
N2.C0.D1.R0.S02: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N4.C2.D1.R0.S17: RdDqDqs FSM results: Left = 13, Right = 63, center = 38
N6.C2.D0.R1.S11: RdDqDqs FSM results: Left = 01, Right = 63, center = 32
N0.C2.D0.R1.S10: RxDqsDelay = 033
N2.C0.D1.R0.S03: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N4.C2.D1.R0.S17: RxDqsDelay = 038
N6.C2.D0.R1.S11: RxDqsDelay = 032
N0.C2.D0.R1.S11: RdDqDqs FSM results: Left = 03, Right = 63, center = 33
N2.C0.D1.R0.S04: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N4.C2.D1.R1.S00: RdDqDqs FSM results: Left = 12, Right = 63, center = 37
N6.C2.D0.R1.S12: RdDqDqs FSM results: Left = 04, Right = 63, center = 33
N0.C2.D0.R1.S11: RxDqsDelay = 033
N2.C0.D1.R0.S05: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N4.C2.D1.R1.S00: RxDqsDelay = 037
N6.C2.D0.R1.S12: RxDqsDelay = 033
N0.C2.D0.R1.S12: RdDqDqs FSM results: Left = 04, Right = 63, center = 33
N2.C0.D1.R0.S06: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N4.C2.D1.R1.S01: RdDqDqs FSM results: Left = 16, Right = 63, center = 39
N6.C2.D0.R1.S13: RdDqDqs FSM results: Left = 02, Right = 61, center = 31
N0.C2.D0.R1.S12: RxDqsDelay = 033
N2.C0.D1.R0.S07: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N4.C2.D1.R1.S01: RxDqsDelay = 039
N6.C2.D0.R1.S13: RxDqsDelay = 031
N0.C2.D0.R1.S13: RdDqDqs FSM results: Left = 04, Right = 63, center = 33
N2.C0.D1.R0.S08: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N4.C2.D1.R1.S02: RdDqDqs FSM results: Left = 11, Right = 63, center = 37
N6.C2.D0.R1.S14: RdDqDqs FSM results: Left = 04, Right = 63, center = 33
N0.C2.D0.R1.S13: RxDqsDelay = 033
N2.C0.D1.R0.S00: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N4.C2.D1.R1.S02: RxDqsDelay = 037
N6.C2.D0.R1.S14: RxDqsDelay = 033
N0.C2.D0.R1.S14: RdDqDqs FSM results: Left = 03, Right = 63, center = 33
N2.C0.D1.R0.S01: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N4.C2.D1.R1.S03: RdDqDqs FSM results: Left = 10, Right = 63, center = 36
N6.C2.D0.R1.S15: RdDqDqs FSM results: Left = 03, Right = 63, center = 33
N0.C2.D0.R1.S14: RxDqsDelay = 033
N2.C0.D1.R0.S02: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N4.C2.D1.R1.S03: RxDqsDelay = 036
N6.C2.D0.R1.S15: RxDqsDelay = 033
N0.C2.D0.R1.S15: RdDqDqs FSM results: Left = 06, Right = 63, center = 34
N2.C0.D1.R0.S03: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N4.C2.D1.R1.S04: RdDqDqs FSM results: Left = 12, Right = 63, center = 37
N6.C2.D0.R1.S16: RdDqDqs FSM results: Left = 06, Right = 63, center = 34
N0.C2.D0.R1.S15: RxDqsDelay = 034
N2.C0.D1.R0.S04: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N4.C2.D1.R1.S04: RxDqsDelay = 037
N6.C2.D0.R1.S16: RxDqsDelay = 034
N0.C2.D0.R1.S16: RdDqDqs FSM results: Left = 05, Right = 63, center = 34
N2.C0.D1.R0.S05: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N4.C2.D1.R1.S05: RdDqDqs FSM results: Left = 14, Right = 63, center = 38
N6.C2.D0.R1.S17: RdDqDqs FSM results: Left = 02, Right = 59, center = 30
N0.C2.D0.R1.S16: RxDqsDelay = 034
N2.C0.D1.R0.S06: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N4.C2.D1.R1.S05: RxDqsDelay = 038
N6.C2.D0.R1.S17: RxDqsDelay = 030
N0.C2.D0.R1.S17: RdDqDqs FSM results: Left = 05, Right = 63, center = 34
N2.C0.D1.R0.S07: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N4.C2.D1.R1.S06: RdDqDqs FSM results: Left = 18, Right = 63, center = 40
N6.C2.D1.R0.S00: RdDqDqs FSM results: Left = 04, Right = 63, center = 33
N0.C2.D0.R1.S17: RxDqsDelay = 034
N2.C0.D1.R0.S08: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N4.C2.D1.R1.S06: RxDqsDelay = 040
N6.C2.D1.R0.S00: RxDqsDelay = 033
N0.C2.D1.R0.S00: RdDqDqs FSM results: Left = 07, Right = 63, center = 35
N2.C0.D1.R0.S00: Preamble found at Latency = 008
N4.C2.D1.R1.S07: RdDqDqs FSM results: Left = 15, Right = 63, center = 39
N6.C2.D1.R0.S01: RdDqDqs FSM results: Left = 09, Right = 63, center = 36
N0.C2.D1.R0.S00: RxDqsDelay = 035
N2.C0.D1.R0.S07: Preamble found at Latency = 008
N4.C2.D1.R1.S07: RxDqsDelay = 039
N6.C2.D1.R0.S01: RxDqsDelay = 036
N0.C2.D1.R0.S01: RdDqDqs FSM results: Left = 11, Right = 63, center = 37
N2.C0.D1.R0.S00: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N4.C2.D1.R1.S08: RdDqDqs FSM results: Left = 17, Right = 63, center = 40
N6.C2.D1.R0.S02: RdDqDqs FSM results: Left = 08, Right = 63, center = 35
N0.C2.D1.R0.S01: RxDqsDelay = 037
N2.C0.D1.R0.S01: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N4.C2.D1.R1.S08: RxDqsDelay = 040
N6.C2.D1.R0.S02: RxDqsDelay = 035
N0.C2.D1.R0.S02: RdDqDqs FSM results: Left = 09, Right = 63, center = 36
N2.C0.D1.R0.S02: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N4.C2.D1.R1.S09: RdDqDqs FSM results: Left = 12, Right = 63, center = 37
N6.C2.D1.R0.S03: RdDqDqs FSM results: Left = 08, Right = 63, center = 35
N0.C2.D1.R0.S02: RxDqsDelay = 036
N2.C0.D1.R0.S03: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N4.C2.D1.R1.S09: RxDqsDelay = 037
N6.C2.D1.R0.S03: RxDqsDelay = 035
N0.C2.D1.R0.S03: RdDqDqs FSM results: Left = 09, Right = 63, center = 36
N2.C0.D1.R0.S04: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N4.C2.D1.R1.S10: RdDqDqs FSM results: Left = 19, Right = 63, center = 41
N6.C2.D1.R0.S04: RdDqDqs FSM results: Left = 06, Right = 63, center = 34
N0.C2.D1.R0.S03: RxDqsDelay = 036
N2.C0.D1.R0.S05: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N4.C2.D1.R1.S10: RxDqsDelay = 041
N6.C2.D1.R0.S04: RxDqsDelay = 034
N0.C2.D1.R0.S04: RdDqDqs FSM results: Left = 09, Right = 63, center = 36
N2.C0.D1.R0.S06: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N4.C2.D1.R1.S11: RdDqDqs FSM results: Left = 10, Right = 63, center = 36
N6.C2.D1.R0.S05: RdDqDqs FSM results: Left = 09, Right = 63, center = 36
N0.C2.D1.R0.S04: RxDqsDelay = 036
N2.C0.D1.R0.S07: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N4.C2.D1.R1.S11: RxDqsDelay = 036
N6.C2.D1.R0.S05: RxDqsDelay = 036
N0.C2.D1.R0.S05: RdDqDqs FSM results: Left = 09, Right = 63, center = 36
N2.C0.D1.R0.S08: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N4.C2.D1.R1.S12: RdDqDqs FSM results: Left = 12, Right = 63, center = 37
N6.C2.D1.R0.S06: RdDqDqs FSM results: Left = 10, Right = 63, center = 36
N0.C2.D1.R0.S05: RxDqsDelay = 036
N2.C0.D1.R0.S01: Preamble found at Latency = 007
N4.C2.D1.R1.S12: RxDqsDelay = 037
N6.C2.D1.R0.S06: RxDqsDelay = 036
N0.C2.D1.R0.S06: RdDqDqs FSM results: Left = 11, Right = 63, center = 37
N2.C0.D1.R0.S02: Preamble found at Latency = 007
N4.C2.D1.R1.S13: RdDqDqs FSM results: Left = 09, Right = 63, center = 36
N6.C2.D1.R0.S07: RdDqDqs FSM results: Left = 11, Right = 63, center = 37
N0.C2.D1.R0.S06: RxDqsDelay = 037
N2.C0.D1.R0.S03: Preamble found at Latency = 007
N4.C2.D1.R1.S13: RxDqsDelay = 036
N6.C2.D1.R0.S07: RxDqsDelay = 037
N0.C2.D1.R0.S07: RdDqDqs FSM results: Left = 08, Right = 63, center = 35
N2.C0.D1.R0.S04: Preamble found at Latency = 007
N4.C2.D1.R1.S14: RdDqDqs FSM results: Left = 17, Right = 63, center = 40
N6.C2.D1.R0.S08: RdDqDqs FSM results: Left = 11, Right = 63, center = 37
N0.C2.D1.R0.S07: RxDqsDelay = 035
N2.C0.D1.R0.S05: Preamble found at Latency = 007
N4.C2.D1.R1.S14: RxDqsDelay = 040
N6.C2.D1.R0.S08: RxDqsDelay = 037
N0.C2.D1.R0.S08: RdDqDqs FSM results: Left = 09, Right = 63, center = 36
N2.C0.D1.R0.S06: Preamble found at Latency = 007
N4.C2.D1.R1.S15: RdDqDqs FSM results: Left = 15, Right = 63, center = 39
N6.C2.D1.R0.S09: RdDqDqs FSM results: Left = 09, Right = 63, center = 36
N0.C2.D1.R0.S08: RxDqsDelay = 036
N2.C0.D1.R0.S08: Preamble found at Latency = 007
N4.C2.D1.R1.S15: RxDqsDelay = 039
N6.C2.D1.R0.S09: RxDqsDelay = 036
N0.C2.D1.R0.S09: RdDqDqs FSM results: Left = 06, Right = 63, center = 34
N2.C0.D1.R0.S00: Total Receive Enable Delay = 1312
N4.C2.D1.R1.S16: RdDqDqs FSM results: Left = 11, Right = 63, center = 37
N6.C2.D1.R0.S10: RdDqDqs FSM results: Left = 05, Right = 63, center = 34
N0.C2.D1.R0.S09: RxDqsDelay = 034
N2.C0.D1.R0.S01: Total Receive Enable Delay = 1297
N4.C2.D1.R1.S16: RxDqsDelay = 037
N6.C2.D1.R0.S10: RxDqsDelay = 034
N0.C2.D1.R0.S10: RdDqDqs FSM results: Left = 08, Right = 63, center = 35
N2.C0.D1.R0.S02: Total Receive Enable Delay = 1267
N4.C2.D1.R1.S17: RdDqDqs FSM results: Left = 12, Right = 63, center = 37
N6.C2.D1.R0.S11: RdDqDqs FSM results: Left = 04, Right = 63, center = 33
N0.C2.D1.R0.S10: RxDqsDelay = 035
N2.C0.D1.R0.S03: Total Receive Enable Delay = 1246
N4.C2.D1.R1.S17: RxDqsDelay = 037
N6.C2.D1.R0.S11: RxDqsDelay = 033
N0.C2.D1.R0.S11: RdDqDqs FSM results: Left = 05, Right = 63, center = 34
N2.C0.D1.R0.S04: Total Receive Enable Delay = 1240
START_DATA_RX_DQS
N6.C2.D1.R0.S12: RdDqDqs FSM results: Left = 07, Right = 63, center = 35
N0.C2.D1.R0.S11: RxDqsDelay = 034
N2.C0.D1.R0.S05: Total Receive Enable Delay = 1263
N4.C2.R0.S00: PI = 36
N6.C2.D1.R0.S12: RxDqsDelay = 035
N0.C2.D1.R0.S12: RdDqDqs FSM results: Left = 09, Right = 63, center = 36
N2.C0.D1.R0.S06: Total Receive Enable Delay = 1294
N4.C2.R0.S01: PI = 37
N6.C2.D1.R0.S13: RdDqDqs FSM results: Left = 05, Right = 63, center = 34
N0.C2.D1.R0.S12: RxDqsDelay = 036
N2.C0.D1.R0.S07: Total Receive Enable Delay = 1317
N4.C2.R0.S02: PI = 36
N6.C2.D1.R0.S13: RxDqsDelay = 034
N0.C2.D1.R0.S13: RdDqDqs FSM results: Left = 07, Right = 63, center = 35
N2.C0.D1.R0.S08: Total Receive Enable Delay = 1233
N4.C2.R0.S03: PI = 35
N6.C2.D1.R0.S14: RdDqDqs FSM results: Left = 08, Right = 63, center = 35
N0.C2.D1.R0.S13: RxDqsDelay = 035
N2.C0.D1.R0: Starting preamble search upper nibbles
N4.C2.R0.S04: PI = 36
N6.C2.D1.R0.S14: RxDqsDelay = 035
N0.C2.D1.R0.S14: RdDqDqs FSM results: Left = 08, Right = 63, center = 35
N2.C0.D1.R0.S09: PI = 003, PtrOffset = 004
N4.C2.R0.S05: PI = 37
N6.C2.D1.R0.S15: RdDqDqs FSM results: Left = 06, Right = 63, center = 34
N0.C2.D1.R0.S14: RxDqsDelay = 035
N2.C0.D1.R0.S10: PI = 045, PtrOffset = 005
N4.C2.R0.S06: PI = 38
N6.C2.D1.R0.S15: RxDqsDelay = 034
N0.C2.D1.R0.S15: RdDqDqs FSM results: Left = 09, Right = 63, center = 36
N2.C0.D1.R0.S11: PI = 019, PtrOffset = 005
N4.C2.R0.S07: PI = 37
N6.C2.D1.R0.S16: RdDqDqs FSM results: Left = 10, Right = 63, center = 36
N0.C2.D1.R0.S15: RxDqsDelay = 036
N2.C0.D1.R0.S12: PI = 062, PtrOffset = 004
N4.C2.R0.S08: PI = 37
N6.C2.D1.R0.S16: RxDqsDelay = 036
N0.C2.D1.R0.S16: RdDqDqs FSM results: Left = 08, Right = 63, center = 35
N2.C0.D1.R0.S13: PI = 054, PtrOffset = 004
N4.C2.R0.S09: PI = 36
N6.C2.D1.R0.S17: RdDqDqs FSM results: Left = 05, Right = 63, center = 34
N0.C2.D1.R0.S16: RxDqsDelay = 035
N2.C0.D1.R0.S14: PI = 013, PtrOffset = 005
N4.C2.R0.S10: PI = 38
N6.C2.D1.R0.S17: RxDqsDelay = 034
N0.C2.D1.R0.S17: RdDqDqs FSM results: Left = 10, Right = 63, center = 36
N2.C0.D1.R0.S15: PI = 042, PtrOffset = 005
N4.C2.R0.S11: PI = 34
N6.C2.D1.R1.S00: RdDqDqs FSM results: Left = 04, Right = 63, center = 33
N0.C2.D1.R0.S17: RxDqsDelay = 036
N2.C0.D1.R0.S16: PI = 003, PtrOffset = 004
N4.C2.R0.S12: PI = 36
N6.C2.D1.R1.S00: RxDqsDelay = 033
N0.C2.D1.R1.S00: RdDqDqs FSM results: Left = 07, Right = 63, center = 35
N2.C0.D1.R0.S17: PI = 048, PtrOffset = 004
N4.C2.R0.S13: PI = 32
N6.C2.D1.R1.S01: RdDqDqs FSM results: Left = 09, Right = 63, center = 36
N0.C2.D1.R1.S00: RxDqsDelay = 035
N2.C0.D1.R0.S09: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N4.C2.R0.S14: PI = 38
N6.C2.D1.R1.S01: RxDqsDelay = 036
N0.C2.D1.R1.S01: RdDqDqs FSM results: Left = 11, Right = 63, center = 37
N2.C0.D1.R0.S10: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N4.C2.R0.S15: PI = 37
N6.C2.D1.R1.S02: RdDqDqs FSM results: Left = 07, Right = 63, center = 35
N0.C2.D1.R1.S01: RxDqsDelay = 037
N2.C0.D1.R0.S11: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N4.C2.R0.S16: PI = 36
N6.C2.D1.R1.S02: RxDqsDelay = 035
N0.C2.D1.R1.S02: RdDqDqs FSM results: Left = 09, Right = 63, center = 36
N2.C0.D1.R0.S12: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N4.C2.R0.S17: PI = 36
N6.C2.D1.R1.S03: RdDqDqs FSM results: Left = 09, Right = 63, center = 36
N0.C2.D1.R1.S02: RxDqsDelay = 036
N2.C0.D1.R0.S13: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N4.C2.R0.S00: PI = 36
N6.C2.D1.R1.S03: RxDqsDelay = 036
N0.C2.D1.R1.S03: RdDqDqs FSM results: Left = 09, Right = 63, center = 36
N2.C0.D1.R0.S14: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N4.C2.R0.S01: PI = 37
N6.C2.D1.R1.S04: RdDqDqs FSM results: Left = 05, Right = 63, center = 34
N0.C2.D1.R1.S03: RxDqsDelay = 036
N2.C0.D1.R0.S15: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N4.C2.R0.S02: PI = 36
N6.C2.D1.R1.S04: RxDqsDelay = 034
N0.C2.D1.R1.S04: RdDqDqs FSM results: Left = 09, Right = 63, center = 36
N2.C0.D1.R0.S16: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N4.C2.R0.S03: PI = 35
N6.C2.D1.R1.S05: RdDqDqs FSM results: Left = 09, Right = 63, center = 36
N0.C2.D1.R1.S04: RxDqsDelay = 036
N2.C0.D1.R0.S17: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N4.C2.R0.S04: PI = 36
N6.C2.D1.R1.S05: RxDqsDelay = 036
N0.C2.D1.R1.S05: RdDqDqs FSM results: Left = 08, Right = 63, center = 35
N2.C0.D1.R0.S09: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N4.C2.R0.S05: PI = 37
N6.C2.D1.R1.S06: RdDqDqs FSM results: Left = 10, Right = 63, center = 36
N0.C2.D1.R1.S05: RxDqsDelay = 035
N2.C0.D1.R0.S10: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N4.C2.R0.S06: PI = 38
N6.C2.D1.R1.S06: RxDqsDelay = 036
N0.C2.D1.R1.S06: RdDqDqs FSM results: Left = 10, Right = 63, center = 36
N2.C0.D1.R0.S11: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N4.C2.R0.S07: PI = 37
N6.C2.D1.R1.S07: RdDqDqs FSM results: Left = 11, Right = 63, center = 37
N0.C2.D1.R1.S06: RxDqsDelay = 036
N2.C0.D1.R0.S12: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N4.C2.R0.S08: PI = 37
N6.C2.D1.R1.S07: RxDqsDelay = 037
N0.C2.D1.R1.S07: RdDqDqs FSM results: Left = 09, Right = 63, center = 36
N2.C0.D1.R0.S13: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N4.C2.R0.S09: PI = 36
N6.C2.D1.R1.S08: RdDqDqs FSM results: Left = 11, Right = 63, center = 37
N0.C2.D1.R1.S07: RxDqsDelay = 036
N2.C0.D1.R0.S14: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N4.C2.R0.S10: PI = 38
N6.C2.D1.R1.S08: RxDqsDelay = 037
N0.C2.D1.R1.S08: RdDqDqs FSM results: Left = 09, Right = 63, center = 36
N2.C0.D1.R0.S15: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N4.C2.R0.S11: PI = 34
N6.C2.D1.R1.S09: RdDqDqs FSM results: Left = 09, Right = 63, center = 36
N0.C2.D1.R1.S08: RxDqsDelay = 036
N2.C0.D1.R0.S16: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N4.C2.R0.S12: PI = 36
N6.C2.D1.R1.S09: RxDqsDelay = 036
N0.C2.D1.R1.S09: RdDqDqs FSM results: Left = 05, Right = 63, center = 34
N2.C0.D1.R0.S17: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N4.C2.R0.S13: PI = 32
N6.C2.D1.R1.S10: RdDqDqs FSM results: Left = 05, Right = 63, center = 34
N0.C2.D1.R1.S09: RxDqsDelay = 034
N2.C0.D1.R0.S09: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N4.C2.R0.S14: PI = 38
N6.C2.D1.R1.S10: RxDqsDelay = 034
N0.C2.D1.R1.S10: RdDqDqs FSM results: Left = 09, Right = 63, center = 36
N2.C0.D1.R0.S10: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N4.C2.R0.S15: PI = 37
N6.C2.D1.R1.S11: RdDqDqs FSM results: Left = 05, Right = 63, center = 34
N0.C2.D1.R1.S10: RxDqsDelay = 036
N2.C0.D1.R0.S11: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N4.C2.R0.S16: PI = 36
N6.C2.D1.R1.S11: RxDqsDelay = 034
N0.C2.D1.R1.S11: RdDqDqs FSM results: Left = 06, Right = 63, center = 34
N2.C0.D1.R0.S12: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N4.C2.R0.S17: PI = 36
N6.C2.D1.R1.S12: RdDqDqs FSM results: Left = 08, Right = 63, center = 35
N0.C2.D1.R1.S11: RxDqsDelay = 034
N2.C0.D1.R0.S13: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N4.C2.R2.S00: PI = 37
N6.C2.D1.R1.S12: RxDqsDelay = 035
N0.C2.D1.R1.S12: RdDqDqs FSM results: Left = 09, Right = 63, center = 36
N2.C0.D1.R0.S14: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N4.C2.R2.S01: PI = 39
N6.C2.D1.R1.S13: RdDqDqs FSM results: Left = 06, Right = 63, center = 34
N0.C2.D1.R1.S12: RxDqsDelay = 036
N2.C0.D1.R0.S15: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N4.C2.R2.S02: PI = 37
N6.C2.D1.R1.S13: RxDqsDelay = 034
N0.C2.D1.R1.S13: RdDqDqs FSM results: Left = 07, Right = 63, center = 35
N2.C0.D1.R0.S16: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N4.C2.R2.S03: PI = 36
N6.C2.D1.R1.S14: RdDqDqs FSM results: Left = 07, Right = 63, center = 35
N0.C2.D1.R1.S13: RxDqsDelay = 035
N2.C0.D1.R0.S17: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N4.C2.R2.S04: PI = 37
N6.C2.D1.R1.S14: RxDqsDelay = 035
N0.C2.D1.R1.S14: RdDqDqs FSM results: Left = 07, Right = 63, center = 35
N2.C0.D1.R0.S09: Preamble found at Latency = 008
N4.C2.R2.S05: PI = 38
N6.C2.D1.R1.S15: RdDqDqs FSM results: Left = 05, Right = 63, center = 34
N0.C2.D1.R1.S14: RxDqsDelay = 035
N2.C0.D1.R0.S16: Preamble found at Latency = 008
N4.C2.R2.S06: PI = 40
N6.C2.D1.R1.S15: RxDqsDelay = 034
N0.C2.D1.R1.S15: RdDqDqs FSM results: Left = 09, Right = 63, center = 36
N2.C0.D1.R0.S09: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N4.C2.R2.S07: PI = 39
N6.C2.D1.R1.S16: RdDqDqs FSM results: Left = 09, Right = 63, center = 36
N0.C2.D1.R1.S15: RxDqsDelay = 036
N2.C0.D1.R0.S10: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N4.C2.R2.S08: PI = 39
N6.C2.D1.R1.S16: RxDqsDelay = 036
N0.C2.D1.R1.S16: RdDqDqs FSM results: Left = 09, Right = 63, center = 36
N2.C0.D1.R0.S11: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N4.C2.R2.S09: PI = 37
N6.C2.D1.R1.S17: RdDqDqs FSM results: Left = 05, Right = 63, center = 34
N0.C2.D1.R1.S16: RxDqsDelay = 036
N2.C0.D1.R0.S12: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N4.C2.R2.S10: PI = 41
N6.C2.D1.R1.S17: RxDqsDelay = 034
N0.C2.D1.R1.S17: RdDqDqs FSM results: Left = 09, Right = 63, center = 36
N2.C0.D1.R0.S13: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N4.C2.R2.S11: PI = 36
START_DATA_RX_DQS
N0.C2.D1.R1.S17: RxDqsDelay = 036
N2.C0.D1.R0.S14: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N4.C2.R2.S12: PI = 37
N6.C2.R0.S00: PI = 31
START_DATA_RX_DQS
N2.C0.D1.R0.S15: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N4.C2.R2.S13: PI = 36
N6.C2.R0.S01: PI = 34
N0.C2.R0.S00: PI = 33
N2.C0.D1.R0.S16: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N4.C2.R2.S14: PI = 40
N6.C2.R0.S02: PI = 33
N0.C2.R0.S01: PI = 35
N2.C0.D1.R0.S17: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N4.C2.R2.S15: PI = 39
N6.C2.R0.S03: PI = 33
N0.C2.R0.S02: PI = 33
N2.C0.D1.R0.S10: Preamble found at Latency = 007
N4.C2.R2.S16: PI = 37
N6.C2.R0.S04: PI = 30
N0.C2.R0.S03: PI = 34
N2.C0.D1.R0.S11: Preamble found at Latency = 007
N4.C2.R2.S17: PI = 37
N6.C2.R0.S05: PI = 35
N0.C2.R0.S04: PI = 33
N2.C0.D1.R0.S12: Preamble found at Latency = 007
N4.C2.R2.S00: PI = 37
N6.C2.R0.S06: PI = 34
N0.C2.R0.S05: PI = 35
N2.C0.D1.R0.S13: Preamble found at Latency = 007
N4.C2.R2.S01: PI = 39
N6.C2.R0.S07: PI = 35
N0.C2.R0.S06: PI = 35
N2.C0.D1.R0.S14: Preamble found at Latency = 007
N4.C2.R2.S02: PI = 37
N6.C2.R0.S08: PI = 36
N0.C2.R0.S07: PI = 34
N2.C0.D1.R0.S15: Preamble found at Latency = 007
N4.C2.R2.S03: PI = 36
N6.C2.R0.S09: PI = 33
N0.C2.R0.S08: PI = 33
N2.C0.D1.R0.S17: Preamble found at Latency = 007
N4.C2.R2.S04: PI = 37
N6.C2.R0.S10: PI = 32
N0.C2.R0.S09: PI = 31
N2.C0.D1.R0: Preamble found for all upper nibbles, adjusting Pi, Offset to center into preamble
N4.C2.R2.S05: PI = 38
N6.C2.R0.S11: PI = 32
N0.C2.R0.S10: PI = 33
N2.C0.D1.R0.S09: Total Receive Enable Delay = 1315
N4.C2.R2.S06: PI = 40
N6.C2.R0.S12: PI = 33
N0.C2.R0.S11: PI = 33
N2.C0.D1.R0.S10: Total Receive Enable Delay = 1293
N4.C2.R2.S07: PI = 39
N6.C2.R0.S13: PI = 32
N0.C2.R0.S12: PI = 33
N2.C0.D1.R0.S11: Total Receive Enable Delay = 1267
N4.C2.R2.S08: PI = 39
N6.C2.R0.S14: PI = 33
N0.C2.R0.S13: PI = 33
N2.C0.D1.R0.S12: Total Receive Enable Delay = 1246
N4.C2.R2.S09: PI = 37
N6.C2.R0.S15: PI = 33
N0.C2.R0.S14: PI = 33
N2.C0.D1.R0.S13: Total Receive Enable Delay = 1238
N4.C2.R2.S10: PI = 41
N6.C2.R0.S16: PI = 34
N0.C2.R0.S15: PI = 34
N2.C0.D1.R0.S14: Total Receive Enable Delay = 1261
N4.C2.R2.S11: PI = 36
N6.C2.R0.S17: PI = 30
N0.C2.R0.S16: PI = 33
N2.C0.D1.R0.S15: Total Receive Enable Delay = 1290
N4.C2.R2.S12: PI = 37
N6.C2.R0.S00: PI = 31
N0.C2.R0.S17: PI = 34
N2.C0.D1.R0.S16: Total Receive Enable Delay = 1315
N4.C2.R2.S13: PI = 36
N6.C2.R0.S01: PI = 34
N0.C2.R0.S00: PI = 33
N2.C0.D1.R0.S17: Total Receive Enable Delay = 1232
N4.C2.R2.S14: PI = 40
N6.C2.R0.S02: PI = 33
N0.C2.R0.S01: PI = 35
N2.C0.D1.R1: RcvEnFine: Initial RdCmd2RcvEnLatency = 10, Initial RdPtrOffsetRcvEn = 4
N4.C2.R2.S15: PI = 39
N6.C2.R0.S03: PI = 33
N0.C2.R0.S02: PI = 33
N4.C2.R2.S16: PI = 37
N6.C2.R0.S04: PI = 30
N0.C2.R0.S03: PI = 34
N2.C0.D1.R1.S00: Rcv En Fine Value = 257
N4.C2.R2.S17: PI = 37
N6.C2.R0.S05: PI = 35
N0.C2.R0.S04: PI = 33
N2.C0.D1.R1.S01: Rcv En Fine Value = 369
STOP_DATA_RX_DQS
N6.C2.R0.S06: PI = 34
N0.C2.R0.S05: PI = 35
N2.C0.D1.R1.S02: Rcv En Fine Value = 338
N4.C3.D0.R0.S00: RdDqDqs FSM results: Left = 13, Right = 63, center = 38
N6.C2.R0.S07: PI = 35
N0.C2.R0.S06: PI = 35
N2.C0.D1.R1.S03: Rcv En Fine Value = 318
N4.C3.D0.R0.S00: RxDqsDelay = 038
N6.C2.R0.S08: PI = 36
N0.C2.R0.S07: PI = 34
N2.C0.D1.R1.S04: Rcv En Fine Value = 310
N4.C3.D0.R0.S01: RdDqDqs FSM results: Left = 16, Right = 63, center = 39
N6.C2.R0.S09: PI = 33
N0.C2.R0.S08: PI = 33
N2.C0.D1.R1.S05: Rcv En Fine Value = 334
N4.C3.D0.R0.S01: RxDqsDelay = 039
N6.C2.R0.S10: PI = 32
N0.C2.R0.S09: PI = 31
N2.C0.D1.R1.S06: Rcv En Fine Value = 365
N4.C3.D0.R0.S02: RdDqDqs FSM results: Left = 10, Right = 63, center = 36
N6.C2.R0.S11: PI = 32
N0.C2.R0.S10: PI = 33
N2.C0.D1.R1.S07: Rcv En Fine Value = 260
N4.C3.D0.R0.S02: RxDqsDelay = 036
N6.C2.R0.S12: PI = 33
N0.C2.R0.S11: PI = 33
N2.C0.D1.R1.S08: Rcv En Fine Value = 308
N4.C3.D0.R0.S03: RdDqDqs FSM results: Left = 10, Right = 63, center = 36
N6.C2.R0.S13: PI = 32
N0.C2.R0.S12: PI = 33
N2.C0.D1.R1.S09: Rcv En Fine Value = 257
N4.C3.D0.R0.S03: RxDqsDelay = 036
N6.C2.R0.S14: PI = 33
N0.C2.R0.S13: PI = 33
N2.C0.D1.R1.S10: Rcv En Fine Value = 366
N4.C3.D0.R0.S04: RdDqDqs FSM results: Left = 16, Right = 63, center = 39
N6.C2.R0.S15: PI = 33
N0.C2.R0.S14: PI = 33
N2.C0.D1.R1.S11: Rcv En Fine Value = 338
N4.C3.D0.R0.S04: RxDqsDelay = 039
N6.C2.R0.S16: PI = 34
N0.C2.R0.S15: PI = 34
N2.C0.D1.R1.S12: Rcv En Fine Value = 319
N4.C3.D0.R0.S05: RdDqDqs FSM results: Left = 13, Right = 63, center = 38
N6.C2.R0.S17: PI = 30
N0.C2.R0.S16: PI = 33
N2.C0.D1.R1.S13: Rcv En Fine Value = 309
N4.C3.D0.R0.S05: RxDqsDelay = 038
N6.C2.R2.S00: PI = 33
N0.C2.R0.S17: PI = 34
N2.C0.D1.R1.S14: Rcv En Fine Value = 333
N4.C3.D0.R0.S06: RdDqDqs FSM results: Left = 16, Right = 63, center = 39
N6.C2.R2.S01: PI = 36
N0.C2.R2.S00: PI = 35
N2.C0.D1.R1.S15: Rcv En Fine Value = 364
N4.C3.D0.R0.S06: RxDqsDelay = 039
N6.C2.R2.S02: PI = 35
N0.C2.R2.S01: PI = 37
N2.C0.D1.R1.S16: Rcv En Fine Value = 259
N4.C3.D0.R0.S07: RdDqDqs FSM results: Left = 11, Right = 63, center = 37
N6.C2.R2.S03: PI = 35
N0.C2.R2.S02: PI = 36
N2.C0.D1.R1.S17: Rcv En Fine Value = 304
N4.C3.D0.R0.S07: RxDqsDelay = 037
N6.C2.R2.S04: PI = 34
N0.C2.R2.S03: PI = 36
N2.C0.D1.R1: Starting preamble search lower nibbles
N4.C3.D0.R0.S08: RdDqDqs FSM results: Left = 07, Right = 63, center = 35
N6.C2.R2.S05: PI = 36
N0.C2.R2.S04: PI = 36
N2.C0.D1.R1.S00: PI = 001, PtrOffset = 004
N4.C3.D0.R0.S08: RxDqsDelay = 035
N6.C2.R2.S06: PI = 36
N0.C2.R2.S05: PI = 35
N2.C0.D1.R1.S01: PI = 049, PtrOffset = 005
N4.C3.D0.R0.S09: RdDqDqs FSM results: Left = 13, Right = 63, center = 38
N6.C2.R2.S07: PI = 37
N0.C2.R2.S06: PI = 36
N2.C0.D1.R1.S02: PI = 018, PtrOffset = 005
N4.C3.D0.R0.S09: RxDqsDelay = 038
N6.C2.R2.S08: PI = 37
N0.C2.R2.S07: PI = 35
N2.C0.D1.R1.S03: PI = 062, PtrOffset = 004
N4.C3.D0.R0.S10: RdDqDqs FSM results: Left = 10, Right = 63, center = 36
N6.C2.R2.S09: PI = 36
N0.C2.R2.S08: PI = 36
N2.C0.D1.R1.S04: PI = 054, PtrOffset = 004
N4.C3.D0.R0.S10: RxDqsDelay = 036
N6.C2.R2.S10: PI = 34
N0.C2.R2.S09: PI = 34
N2.C0.D1.R1.S05: PI = 014, PtrOffset = 005
N4.C3.D0.R0.S11: RdDqDqs FSM results: Left = 10, Right = 63, center = 36
N6.C2.R2.S11: PI = 33
N0.C2.R2.S10: PI = 35
N2.C0.D1.R1.S06: PI = 045, PtrOffset = 005
N4.C3.D0.R0.S11: RxDqsDelay = 036
N6.C2.R2.S12: PI = 35
N0.C2.R2.S11: PI = 34
N2.C0.D1.R1.S07: PI = 004, PtrOffset = 004
N4.C3.D0.R0.S12: RdDqDqs FSM results: Left = 12, Right = 63, center = 37
N6.C2.R2.S13: PI = 34
N0.C2.R2.S12: PI = 36
N2.C0.D1.R1.S08: PI = 052, PtrOffset = 004
N4.C3.D0.R0.S12: RxDqsDelay = 037
N6.C2.R2.S14: PI = 35
N0.C2.R2.S13: PI = 35
N2.C0.D1.R1.S00: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N4.C3.D0.R0.S13: RdDqDqs FSM results: Left = 09, Right = 63, center = 36
N6.C2.R2.S15: PI = 34
N0.C2.R2.S14: PI = 35
N2.C0.D1.R1.S01: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N4.C3.D0.R0.S13: RxDqsDelay = 036
N6.C2.R2.S16: PI = 36
N0.C2.R2.S15: PI = 36
N2.C0.D1.R1.S02: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N4.C3.D0.R0.S14: RdDqDqs FSM results: Left = 13, Right = 63, center = 38
N6.C2.R2.S17: PI = 34
N0.C2.R2.S16: PI = 35
N2.C0.D1.R1.S03: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N4.C3.D0.R0.S14: RxDqsDelay = 038
N6.C2.R2.S00: PI = 33
N0.C2.R2.S17: PI = 36
N2.C0.D1.R1.S04: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N4.C3.D0.R0.S15: RdDqDqs FSM results: Left = 13, Right = 63, center = 38
N6.C2.R2.S01: PI = 36
N0.C2.R2.S00: PI = 35
N2.C0.D1.R1.S05: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N4.C3.D0.R0.S15: RxDqsDelay = 038
N6.C2.R2.S02: PI = 35
N0.C2.R2.S01: PI = 37
N2.C0.D1.R1.S06: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N4.C3.D0.R0.S16: RdDqDqs FSM results: Left = 08, Right = 63, center = 35
N6.C2.R2.S03: PI = 35
N0.C2.R2.S02: PI = 36
N2.C0.D1.R1.S07: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N4.C3.D0.R0.S16: RxDqsDelay = 035
N6.C2.R2.S04: PI = 34
N0.C2.R2.S03: PI = 36
N2.C0.D1.R1.S08: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N4.C3.D0.R0.S17: RdDqDqs FSM results: Left = 11, Right = 63, center = 37
N6.C2.R2.S05: PI = 36
N0.C2.R2.S04: PI = 36
N2.C0.D1.R1.S00: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N4.C3.D0.R0.S17: RxDqsDelay = 037
N6.C2.R2.S06: PI = 36
N0.C2.R2.S05: PI = 35
N2.C0.D1.R1.S01: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N4.C3.D0.R1.S00: RdDqDqs FSM results: Left = 12, Right = 63, center = 37
N6.C2.R2.S07: PI = 37
N0.C2.R2.S06: PI = 36
N2.C0.D1.R1.S02: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N4.C3.D0.R1.S00: RxDqsDelay = 037
N6.C2.R2.S08: PI = 37
N0.C2.R2.S07: PI = 35
N2.C0.D1.R1.S03: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N4.C3.D0.R1.S01: RdDqDqs FSM results: Left = 16, Right = 63, center = 39
N6.C2.R2.S09: PI = 36
N0.C2.R2.S08: PI = 36
N2.C0.D1.R1.S04: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N4.C3.D0.R1.S01: RxDqsDelay = 039
N6.C2.R2.S10: PI = 34
N0.C2.R2.S09: PI = 34
N2.C0.D1.R1.S05: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N4.C3.D0.R1.S02: RdDqDqs FSM results: Left = 10, Right = 63, center = 36
N6.C2.R2.S11: PI = 33
N0.C2.R2.S10: PI = 35
N2.C0.D1.R1.S06: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N4.C3.D0.R1.S02: RxDqsDelay = 036
N6.C2.R2.S12: PI = 35
N0.C2.R2.S11: PI = 34
N2.C0.D1.R1.S07: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N4.C3.D0.R1.S03: RdDqDqs FSM results: Left = 10, Right = 63, center = 36
N6.C2.R2.S13: PI = 34
N0.C2.R2.S12: PI = 36
N2.C0.D1.R1.S08: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N4.C3.D0.R1.S03: RxDqsDelay = 036
N6.C2.R2.S14: PI = 35
N0.C2.R2.S13: PI = 35
N2.C0.D1.R1.S00: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N4.C3.D0.R1.S04: RdDqDqs FSM results: Left = 15, Right = 63, center = 39
N6.C2.R2.S15: PI = 34
N0.C2.R2.S14: PI = 35
N2.C0.D1.R1.S01: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N4.C3.D0.R1.S04: RxDqsDelay = 039
N6.C2.R2.S16: PI = 36
N0.C2.R2.S15: PI = 36
N2.C0.D1.R1.S02: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N4.C3.D0.R1.S05: RdDqDqs FSM results: Left = 13, Right = 63, center = 38
N6.C2.R2.S17: PI = 34
N0.C2.R2.S16: PI = 35
N2.C0.D1.R1.S03: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N4.C3.D0.R1.S05: RxDqsDelay = 038
STOP_DATA_RX_DQS
N0.C2.R2.S17: PI = 36
N2.C0.D1.R1.S04: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N4.C3.D0.R1.S06: RdDqDqs FSM results: Left = 16, Right = 63, center = 39
N6.C3.D0.R0.S00: RdDqDqs FSM results: Left = 03, Right = 59, center = 31
STOP_DATA_RX_DQS
N2.C0.D1.R1.S05: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N4.C3.D0.R1.S06: RxDqsDelay = 039
N6.C3.D0.R0.S00: RxDqsDelay = 031
N0.C3.D0.R0.S00: RdDqDqs FSM results: Left = 06, Right = 63, center = 34
N2.C0.D1.R1.S06: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N4.C3.D0.R1.S07: RdDqDqs FSM results: Left = 11, Right = 63, center = 37
N6.C3.D0.R0.S01: RdDqDqs FSM results: Left = 03, Right = 63, center = 33
N0.C3.D0.R0.S00: RxDqsDelay = 034
N2.C0.D1.R1.S07: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N4.C3.D0.R1.S07: RxDqsDelay = 037
N6.C3.D0.R0.S01: RxDqsDelay = 033
N0.C3.D0.R0.S01: RdDqDqs FSM results: Left = 05, Right = 63, center = 34
N2.C0.D1.R1.S08: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N4.C3.D0.R1.S08: RdDqDqs FSM results: Left = 07, Right = 63, center = 35
N6.C3.D0.R0.S02: RdDqDqs FSM results: Left = 03, Right = 63, center = 33
N0.C3.D0.R0.S01: RxDqsDelay = 034
N2.C0.D1.R1.S00: Preamble found at Latency = 008
N4.C3.D0.R1.S08: RxDqsDelay = 035
N6.C3.D0.R0.S02: RxDqsDelay = 033
N0.C3.D0.R0.S02: RdDqDqs FSM results: Left = 04, Right = 63, center = 33
N2.C0.D1.R1.S07: Preamble found at Latency = 008
N4.C3.D0.R1.S09: RdDqDqs FSM results: Left = 12, Right = 63, center = 37
N6.C3.D0.R0.S03: RdDqDqs FSM results: Left = 04, Right = 61, center = 32
N0.C3.D0.R0.S02: RxDqsDelay = 033
N2.C0.D1.R1.S00: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N4.C3.D0.R1.S09: RxDqsDelay = 037
N6.C3.D0.R0.S03: RxDqsDelay = 032
N0.C3.D0.R0.S03: RdDqDqs FSM results: Left = 05, Right = 63, center = 34
N2.C0.D1.R1.S01: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N4.C3.D0.R1.S10: RdDqDqs FSM results: Left = 09, Right = 63, center = 36
N6.C3.D0.R0.S04: RdDqDqs FSM results: Left = 10, Right = 63, center = 36
N0.C3.D0.R0.S03: RxDqsDelay = 034
N2.C0.D1.R1.S02: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N4.C3.D0.R1.S10: RxDqsDelay = 036
N6.C3.D0.R0.S04: RxDqsDelay = 036
N0.C3.D0.R0.S04: RdDqDqs FSM results: Left = 07, Right = 63, center = 35
N2.C0.D1.R1.S03: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N4.C3.D0.R1.S11: RdDqDqs FSM results: Left = 10, Right = 63, center = 36
N6.C3.D0.R0.S05: RdDqDqs FSM results: Left = 06, Right = 63, center = 34
N0.C3.D0.R0.S04: RxDqsDelay = 035
N2.C0.D1.R1.S04: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N4.C3.D0.R1.S11: RxDqsDelay = 036
N6.C3.D0.R0.S05: RxDqsDelay = 034
N0.C3.D0.R0.S05: RdDqDqs FSM results: Left = 05, Right = 63, center = 34
N2.C0.D1.R1.S05: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N4.C3.D0.R1.S12: RdDqDqs FSM results: Left = 11, Right = 63, center = 37
N6.C3.D0.R0.S06: RdDqDqs FSM results: Left = 04, Right = 63, center = 33
N0.C3.D0.R0.S05: RxDqsDelay = 034
N2.C0.D1.R1.S06: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N4.C3.D0.R1.S12: RxDqsDelay = 037
N6.C3.D0.R0.S06: RxDqsDelay = 033
N0.C3.D0.R0.S06: RdDqDqs FSM results: Left = 07, Right = 63, center = 35
N2.C0.D1.R1.S07: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N4.C3.D0.R1.S13: RdDqDqs FSM results: Left = 09, Right = 63, center = 36
N6.C3.D0.R0.S07: RdDqDqs FSM results: Left = 07, Right = 63, center = 35
N0.C3.D0.R0.S06: RxDqsDelay = 035
N2.C0.D1.R1.S08: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N4.C3.D0.R1.S13: RxDqsDelay = 036
N6.C3.D0.R0.S07: RxDqsDelay = 035
N0.C3.D0.R0.S07: RdDqDqs FSM results: Left = 04, Right = 63, center = 33
N2.C0.D1.R1.S01: Preamble found at Latency = 007
N4.C3.D0.R1.S14: RdDqDqs FSM results: Left = 11, Right = 63, center = 37
N6.C3.D0.R0.S08: RdDqDqs FSM results: Left = 03, Right = 63, center = 33
N0.C3.D0.R0.S07: RxDqsDelay = 033
N2.C0.D1.R1.S02: Preamble found at Latency = 007
N4.C3.D0.R1.S14: RxDqsDelay = 037
N6.C3.D0.R0.S08: RxDqsDelay = 033
N0.C3.D0.R0.S08: RdDqDqs FSM results: Left = 03, Right = 63, center = 33
N2.C0.D1.R1.S03: Preamble found at Latency = 007
N4.C3.D0.R1.S15: RdDqDqs FSM results: Left = 13, Right = 63, center = 38
N6.C3.D0.R0.S09: RdDqDqs FSM results: Left = 06, Right = 63, center = 34
N0.C3.D0.R0.S08: RxDqsDelay = 033
N2.C0.D1.R1.S04: Preamble found at Latency = 007
N4.C3.D0.R1.S15: RxDqsDelay = 038
N6.C3.D0.R0.S09: RxDqsDelay = 034
N0.C3.D0.R0.S09: RdDqDqs FSM results: Left = 10, Right = 63, center = 36
N2.C0.D1.R1.S05: Preamble found at Latency = 007
N4.C3.D0.R1.S16: RdDqDqs FSM results: Left = 09, Right = 63, center = 36
N6.C3.D0.R0.S10: RdDqDqs FSM results: Left = 04, Right = 59, center = 31
N0.C3.D0.R0.S09: RxDqsDelay = 036
N2.C0.D1.R1.S06: Preamble found at Latency = 007
N4.C3.D0.R1.S16: RxDqsDelay = 036
N6.C3.D0.R0.S10: RxDqsDelay = 031
N0.C3.D0.R0.S10: RdDqDqs FSM results: Left = 04, Right = 63, center = 33
N2.C0.D1.R1.S08: Preamble found at Latency = 007
N4.C3.D0.R1.S17: RdDqDqs FSM results: Left = 11, Right = 63, center = 37
N6.C3.D0.R0.S11: RdDqDqs FSM results: Left = 03, Right = 63, center = 33
N0.C3.D0.R0.S10: RxDqsDelay = 033
N2.C0.D1.R1.S00: Total Receive Enable Delay = 1313
N4.C3.D0.R1.S17: RxDqsDelay = 037
N6.C3.D0.R0.S11: RxDqsDelay = 033
N0.C3.D0.R0.S11: RdDqDqs FSM results: Left = 02, Right = 63, center = 32
N2.C0.D1.R1.S01: Total Receive Enable Delay = 1297
N4.C3.D1.R0.S00: RdDqDqs FSM results: Left = 18, Right = 63, center = 40
N6.C3.D0.R0.S12: RdDqDqs FSM results: Left = 06, Right = 63, center = 34
N0.C3.D0.R0.S11: RxDqsDelay = 032
N2.C0.D1.R1.S02: Total Receive Enable Delay = 1266
N4.C3.D1.R0.S00: RxDqsDelay = 040
N6.C3.D0.R0.S12: RxDqsDelay = 034
N0.C3.D0.R0.S12: RdDqDqs FSM results: Left = 05, Right = 63, center = 34
N2.C0.D1.R1.S03: Total Receive Enable Delay = 1246
N4.C3.D1.R0.S01: RdDqDqs FSM results: Left = 20, Right = 63, center = 41
N6.C3.D0.R0.S13: RdDqDqs FSM results: Left = 06, Right = 63, center = 34
N0.C3.D0.R0.S12: RxDqsDelay = 034
N2.C0.D1.R1.S04: Total Receive Enable Delay = 1238
N4.C3.D1.R0.S01: RxDqsDelay = 041
N6.C3.D0.R0.S13: RxDqsDelay = 034
N0.C3.D0.R0.S13: RdDqDqs FSM results: Left = 08, Right = 63, center = 35
N2.C0.D1.R1.S05: Total Receive Enable Delay = 1262
N4.C3.D1.R0.S02: RdDqDqs FSM results: Left = 12, Right = 63, center = 37
N6.C3.D0.R0.S14: RdDqDqs FSM results: Left = 03, Right = 58, center = 30
N0.C3.D0.R0.S13: RxDqsDelay = 035
N2.C0.D1.R1.S06: Total Receive Enable Delay = 1293
N4.C3.D1.R0.S02: RxDqsDelay = 037
N6.C3.D0.R0.S14: RxDqsDelay = 030
N0.C3.D0.R0.S14: RdDqDqs FSM results: Left = 03, Right = 63, center = 33
N2.C0.D1.R1.S07: Total Receive Enable Delay = 1316
N4.C3.D1.R0.S03: RdDqDqs FSM results: Left = 15, Right = 63, center = 39
N6.C3.D0.R0.S15: RdDqDqs FSM results: Left = 03, Right = 60, center = 31
N0.C3.D0.R0.S14: RxDqsDelay = 033
N2.C0.D1.R1.S08: Total Receive Enable Delay = 1236
N4.C3.D1.R0.S03: RxDqsDelay = 039
N6.C3.D0.R0.S15: RxDqsDelay = 031
N0.C3.D0.R0.S15: RdDqDqs FSM results: Left = 05, Right = 63, center = 34
N2.C0.D1.R1: Starting preamble search upper nibbles
N4.C3.D1.R0.S04: RdDqDqs FSM results: Left = 20, Right = 63, center = 41
N6.C3.D0.R0.S16: RdDqDqs FSM results: Left = 03, Right = 63, center = 33
N0.C3.D0.R0.S15: RxDqsDelay = 034
N2.C0.D1.R1.S09: PI = 001, PtrOffset = 004
N4.C3.D1.R0.S04: RxDqsDelay = 041
N6.C3.D0.R0.S16: RxDqsDelay = 033
N0.C3.D0.R0.S16: RdDqDqs FSM results: Left = 04, Right = 63, center = 33
N2.C0.D1.R1.S10: PI = 046, PtrOffset = 005
N4.C3.D1.R0.S05: RdDqDqs FSM results: Left = 18, Right = 63, center = 40
N6.C3.D0.R0.S17: RdDqDqs FSM results: Left = 04, Right = 63, center = 33
N0.C3.D0.R0.S16: RxDqsDelay = 033
N2.C0.D1.R1.S11: PI = 018, PtrOffset = 005
N4.C3.D1.R0.S05: RxDqsDelay = 040
N6.C3.D0.R0.S17: RxDqsDelay = 033
N0.C3.D0.R0.S17: RdDqDqs FSM results: Left = 03, Right = 63, center = 33
N2.C0.D1.R1.S12: PI = 063, PtrOffset = 004
N4.C3.D1.R0.S06: RdDqDqs FSM results: Left = 19, Right = 63, center = 41
N6.C3.D0.R1.S00: RdDqDqs FSM results: Left = 03, Right = 60, center = 31
N0.C3.D0.R0.S17: RxDqsDelay = 033
N2.C0.D1.R1.S13: PI = 053, PtrOffset = 004
N4.C3.D1.R0.S06: RxDqsDelay = 041
N6.C3.D0.R1.S00: RxDqsDelay = 031
N0.C3.D0.R1.S00: RdDqDqs FSM results: Left = 07, Right = 63, center = 35
N2.C0.D1.R1.S14: PI = 013, PtrOffset = 005
N4.C3.D1.R0.S07: RdDqDqs FSM results: Left = 14, Right = 63, center = 38
N6.C3.D0.R1.S01: RdDqDqs FSM results: Left = 04, Right = 63, center = 33
N0.C3.D0.R1.S00: RxDqsDelay = 035
N2.C0.D1.R1.S15: PI = 044, PtrOffset = 005
N4.C3.D1.R0.S07: RxDqsDelay = 038
N6.C3.D0.R1.S01: RxDqsDelay = 033
N0.C3.D0.R1.S01: RdDqDqs FSM results: Left = 05, Right = 63, center = 34
N2.C0.D1.R1.S16: PI = 003, PtrOffset = 004
N4.C3.D1.R0.S08: RdDqDqs FSM results: Left = 10, Right = 63, center = 36
N6.C3.D0.R1.S02: RdDqDqs FSM results: Left = 03, Right = 63, center = 33
N0.C3.D0.R1.S01: RxDqsDelay = 034
N2.C0.D1.R1.S17: PI = 048, PtrOffset = 004
N4.C3.D1.R0.S08: RxDqsDelay = 036
N6.C3.D0.R1.S02: RxDqsDelay = 033
N0.C3.D0.R1.S02: RdDqDqs FSM results: Left = 03, Right = 63, center = 33
N2.C0.D1.R1.S09: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N4.C3.D1.R0.S09: RdDqDqs FSM results: Left = 16, Right = 63, center = 39
N6.C3.D0.R1.S03: RdDqDqs FSM results: Left = 04, Right = 63, center = 33
N0.C3.D0.R1.S02: RxDqsDelay = 033
N2.C0.D1.R1.S10: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N4.C3.D1.R0.S09: RxDqsDelay = 039
N6.C3.D0.R1.S03: RxDqsDelay = 033
N0.C3.D0.R1.S03: RdDqDqs FSM results: Left = 06, Right = 63, center = 34
N2.C0.D1.R1.S11: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N4.C3.D1.R0.S10: RdDqDqs FSM results: Left = 15, Right = 63, center = 39
N6.C3.D0.R1.S04: RdDqDqs FSM results: Left = 10, Right = 63, center = 36
N0.C3.D0.R1.S03: RxDqsDelay = 034
N2.C0.D1.R1.S12: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N4.C3.D1.R0.S10: RxDqsDelay = 039
N6.C3.D0.R1.S04: RxDqsDelay = 036
N0.C3.D0.R1.S04: RdDqDqs FSM results: Left = 07, Right = 63, center = 35
N2.C0.D1.R1.S13: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N4.C3.D1.R0.S11: RdDqDqs FSM results: Left = 12, Right = 63, center = 37
N6.C3.D0.R1.S05: RdDqDqs FSM results: Left = 05, Right = 63, center = 34
N0.C3.D0.R1.S04: RxDqsDelay = 035
N2.C0.D1.R1.S14: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N4.C3.D1.R0.S11: RxDqsDelay = 037
N6.C3.D0.R1.S05: RxDqsDelay = 034
N0.C3.D0.R1.S05: RdDqDqs FSM results: Left = 05, Right = 63, center = 34
N2.C0.D1.R1.S15: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N4.C3.D1.R0.S12: RdDqDqs FSM results: Left = 15, Right = 63, center = 39
N6.C3.D0.R1.S06: RdDqDqs FSM results: Left = 04, Right = 63, center = 33
N0.C3.D0.R1.S05: RxDqsDelay = 034
N2.C0.D1.R1.S16: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N4.C3.D1.R0.S12: RxDqsDelay = 039
N6.C3.D0.R1.S06: RxDqsDelay = 033
N0.C3.D0.R1.S06: RdDqDqs FSM results: Left = 07, Right = 63, center = 35
N2.C0.D1.R1.S17: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N4.C3.D1.R0.S13: RdDqDqs FSM results: Left = 12, Right = 63, center = 37
N6.C3.D0.R1.S07: RdDqDqs FSM results: Left = 05, Right = 63, center = 34
N0.C3.D0.R1.S06: RxDqsDelay = 035
N2.C0.D1.R1.S09: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N4.C3.D1.R0.S13: RxDqsDelay = 037
N6.C3.D0.R1.S07: RxDqsDelay = 034
N0.C3.D0.R1.S07: RdDqDqs FSM results: Left = 04, Right = 63, center = 33
N2.C0.D1.R1.S10: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N4.C3.D1.R0.S14: RdDqDqs FSM results: Left = 16, Right = 63, center = 39
N6.C3.D0.R1.S08: RdDqDqs FSM results: Left = 03, Right = 63, center = 33
N0.C3.D0.R1.S07: RxDqsDelay = 033
N2.C0.D1.R1.S11: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N4.C3.D1.R0.S14: RxDqsDelay = 039
N6.C3.D0.R1.S08: RxDqsDelay = 033
N0.C3.D0.R1.S08: RdDqDqs FSM results: Left = 02, Right = 63, center = 32
N2.C0.D1.R1.S12: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N4.C3.D1.R0.S15: RdDqDqs FSM results: Left = 17, Right = 63, center = 40
N6.C3.D0.R1.S09: RdDqDqs FSM results: Left = 06, Right = 63, center = 34
N0.C3.D0.R1.S08: RxDqsDelay = 032
N2.C0.D1.R1.S13: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N4.C3.D1.R0.S15: RxDqsDelay = 040
N6.C3.D0.R1.S09: RxDqsDelay = 034
N0.C3.D0.R1.S09: RdDqDqs FSM results: Left = 09, Right = 63, center = 36
N2.C0.D1.R1.S14: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N4.C3.D1.R0.S16: RdDqDqs FSM results: Left = 11, Right = 63, center = 37
N6.C3.D0.R1.S10: RdDqDqs FSM results: Left = 04, Right = 63, center = 33
N0.C3.D0.R1.S09: RxDqsDelay = 036
N2.C0.D1.R1.S15: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N4.C3.D1.R0.S16: RxDqsDelay = 037
N6.C3.D0.R1.S10: RxDqsDelay = 033
N0.C3.D0.R1.S10: RdDqDqs FSM results: Left = 04, Right = 63, center = 33
N2.C0.D1.R1.S16: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N4.C3.D1.R0.S17: RdDqDqs FSM results: Left = 16, Right = 63, center = 39
N6.C3.D0.R1.S11: RdDqDqs FSM results: Left = 03, Right = 63, center = 33
N0.C3.D0.R1.S10: RxDqsDelay = 033
N2.C0.D1.R1.S17: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N4.C3.D1.R0.S17: RxDqsDelay = 039
N6.C3.D0.R1.S11: RxDqsDelay = 033
N0.C3.D0.R1.S11: RdDqDqs FSM results: Left = 03, Right = 63, center = 33
N2.C0.D1.R1.S09: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N4.C3.D1.R1.S00: RdDqDqs FSM results: Left = 17, Right = 63, center = 40
N6.C3.D0.R1.S12: RdDqDqs FSM results: Left = 08, Right = 63, center = 35
N0.C3.D0.R1.S11: RxDqsDelay = 033
N2.C0.D1.R1.S10: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N4.C3.D1.R1.S00: RxDqsDelay = 040
N6.C3.D0.R1.S12: RxDqsDelay = 035
N0.C3.D0.R1.S12: RdDqDqs FSM results: Left = 05, Right = 63, center = 34
N2.C0.D1.R1.S11: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N4.C3.D1.R1.S01: RdDqDqs FSM results: Left = 20, Right = 63, center = 41
N6.C3.D0.R1.S13: RdDqDqs FSM results: Left = 06, Right = 63, center = 34
N0.C3.D0.R1.S12: RxDqsDelay = 034
N2.C0.D1.R1.S12: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N4.C3.D1.R1.S01: RxDqsDelay = 041
N6.C3.D0.R1.S13: RxDqsDelay = 034
N0.C3.D0.R1.S13: RdDqDqs FSM results: Left = 07, Right = 63, center = 35
N2.C0.D1.R1.S13: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N4.C3.D1.R1.S02: RdDqDqs FSM results: Left = 13, Right = 63, center = 38
N6.C3.D0.R1.S14: RdDqDqs FSM results: Left = 02, Right = 57, center = 29
N0.C3.D0.R1.S13: RxDqsDelay = 035
N2.C0.D1.R1.S14: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N4.C3.D1.R1.S02: RxDqsDelay = 038
N6.C3.D0.R1.S14: RxDqsDelay = 029
N0.C3.D0.R1.S14: RdDqDqs FSM results: Left = 03, Right = 63, center = 33
N2.C0.D1.R1.S15: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N4.C3.D1.R1.S03: RdDqDqs FSM results: Left = 16, Right = 63, center = 39
N6.C3.D0.R1.S15: RdDqDqs FSM results: Left = 03, Right = 60, center = 31
N0.C3.D0.R1.S14: RxDqsDelay = 033
N2.C0.D1.R1.S16: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N4.C3.D1.R1.S03: RxDqsDelay = 039
N6.C3.D0.R1.S15: RxDqsDelay = 031
N0.C3.D0.R1.S15: RdDqDqs FSM results: Left = 06, Right = 63, center = 34
N2.C0.D1.R1.S17: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N4.C3.D1.R1.S04: RdDqDqs FSM results: Left = 19, Right = 63, center = 41
N6.C3.D0.R1.S16: RdDqDqs FSM results: Left = 02, Right = 58, center = 30
N0.C3.D0.R1.S15: RxDqsDelay = 034
N2.C0.D1.R1.S09: Preamble found at Latency = 008
N4.C3.D1.R1.S04: RxDqsDelay = 041
N6.C3.D0.R1.S16: RxDqsDelay = 030
N0.C3.D0.R1.S16: RdDqDqs FSM results: Left = 03, Right = 63, center = 33
N2.C0.D1.R1.S16: Preamble found at Latency = 008
N4.C3.D1.R1.S05: RdDqDqs FSM results: Left = 17, Right = 63, center = 40
N6.C3.D0.R1.S17: RdDqDqs FSM results: Left = 05, Right = 63, center = 34
N0.C3.D0.R1.S16: RxDqsDelay = 033
N2.C0.D1.R1.S09: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N4.C3.D1.R1.S05: RxDqsDelay = 040
N6.C3.D0.R1.S17: RxDqsDelay = 034
N0.C3.D0.R1.S17: RdDqDqs FSM results: Left = 03, Right = 63, center = 33
N2.C0.D1.R1.S10: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N4.C3.D1.R1.S06: RdDqDqs FSM results: Left = 19, Right = 63, center = 41
N6.C3.D1.R0.S00: RdDqDqs FSM results: Left = 05, Right = 63, center = 34
N0.C3.D0.R1.S17: RxDqsDelay = 033
N2.C0.D1.R1.S11: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N4.C3.D1.R1.S06: RxDqsDelay = 041
N6.C3.D1.R0.S00: RxDqsDelay = 034
N0.C3.D1.R0.S00: RdDqDqs FSM results: Left = 10, Right = 63, center = 36
N2.C0.D1.R1.S12: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N4.C3.D1.R1.S07: RdDqDqs FSM results: Left = 15, Right = 63, center = 39
N6.C3.D1.R0.S01: RdDqDqs FSM results: Left = 06, Right = 63, center = 34
N0.C3.D1.R0.S00: RxDqsDelay = 036
N2.C0.D1.R1.S13: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N4.C3.D1.R1.S07: RxDqsDelay = 039
N6.C3.D1.R0.S01: RxDqsDelay = 034
N0.C3.D1.R0.S01: RdDqDqs FSM results: Left = 09, Right = 63, center = 36
N2.C0.D1.R1.S14: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N4.C3.D1.R1.S08: RdDqDqs FSM results: Left = 11, Right = 63, center = 37
N6.C3.D1.R0.S02: RdDqDqs FSM results: Left = 06, Right = 63, center = 34
N0.C3.D1.R0.S01: RxDqsDelay = 036
N2.C0.D1.R1.S15: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N4.C3.D1.R1.S08: RxDqsDelay = 037
N6.C3.D1.R0.S02: RxDqsDelay = 034
N0.C3.D1.R0.S02: RdDqDqs FSM results: Left = 09, Right = 63, center = 36
N2.C0.D1.R1.S16: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N4.C3.D1.R1.S09: RdDqDqs FSM results: Left = 16, Right = 63, center = 39
N6.C3.D1.R0.S03: RdDqDqs FSM results: Left = 06, Right = 63, center = 34
N0.C3.D1.R0.S02: RxDqsDelay = 036
N2.C0.D1.R1.S17: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N4.C3.D1.R1.S09: RxDqsDelay = 039
N6.C3.D1.R0.S03: RxDqsDelay = 034
N0.C3.D1.R0.S03: RdDqDqs FSM results: Left = 10, Right = 63, center = 36
N2.C0.D1.R1.S10: Preamble found at Latency = 007
N4.C3.D1.R1.S10: RdDqDqs FSM results: Left = 14, Right = 63, center = 38
N6.C3.D1.R0.S04: RdDqDqs FSM results: Left = 14, Right = 63, center = 38
N0.C3.D1.R0.S03: RxDqsDelay = 036
N2.C0.D1.R1.S11: Preamble found at Latency = 007
N4.C3.D1.R1.S10: RxDqsDelay = 038
N6.C3.D1.R0.S04: RxDqsDelay = 038
N0.C3.D1.R0.S04: RdDqDqs FSM results: Left = 10, Right = 63, center = 36
N2.C0.D1.R1.S12: Preamble found at Latency = 007
N4.C3.D1.R1.S11: RdDqDqs FSM results: Left = 12, Right = 63, center = 37
N6.C3.D1.R0.S05: RdDqDqs FSM results: Left = 09, Right = 63, center = 36
N0.C3.D1.R0.S04: RxDqsDelay = 036
N2.C0.D1.R1.S13: Preamble found at Latency = 007
N4.C3.D1.R1.S11: RxDqsDelay = 037
N6.C3.D1.R0.S05: RxDqsDelay = 036
N0.C3.D1.R0.S05: RdDqDqs FSM results: Left = 09, Right = 63, center = 36
N2.C0.D1.R1.S14: Preamble found at Latency = 007
N4.C3.D1.R1.S12: RdDqDqs FSM results: Left = 15, Right = 63, center = 39
N6.C3.D1.R0.S06: RdDqDqs FSM results: Left = 09, Right = 63, center = 36
N0.C3.D1.R0.S05: RxDqsDelay = 036
N2.C0.D1.R1.S15: Preamble found at Latency = 007
N4.C3.D1.R1.S12: RxDqsDelay = 039
N6.C3.D1.R0.S06: RxDqsDelay = 036
N0.C3.D1.R0.S06: RdDqDqs FSM results: Left = 10, Right = 63, center = 36
N2.C0.D1.R1.S17: Preamble found at Latency = 007
N4.C3.D1.R1.S13: RdDqDqs FSM results: Left = 12, Right = 63, center = 37
N6.C3.D1.R0.S07: RdDqDqs FSM results: Left = 09, Right = 63, center = 36
N0.C3.D1.R0.S06: RxDqsDelay = 036
N2.C0.D1.R1: Preamble found for all upper nibbles, adjusting Pi, Offset to center into preamble
N4.C3.D1.R1.S13: RxDqsDelay = 037
N6.C3.D1.R0.S07: RxDqsDelay = 036
N0.C3.D1.R0.S07: RdDqDqs FSM results: Left = 07, Right = 63, center = 35
N2.C0.D1.R1.S09: Total Receive Enable Delay = 1313
N4.C3.D1.R1.S14: RdDqDqs FSM results: Left = 17, Right = 63, center = 40
N6.C3.D1.R0.S08: RdDqDqs FSM results: Left = 07, Right = 63, center = 35
N0.C3.D1.R0.S07: RxDqsDelay = 035
N2.C0.D1.R1.S10: Total Receive Enable Delay = 1294
N4.C3.D1.R1.S14: RxDqsDelay = 040
N6.C3.D1.R0.S08: RxDqsDelay = 035
N0.C3.D1.R0.S08: RdDqDqs FSM results: Left = 05, Right = 63, center = 34
N2.C0.D1.R1.S11: Total Receive Enable Delay = 1266
N4.C3.D1.R1.S15: RdDqDqs FSM results: Left = 18, Right = 63, center = 40
N6.C3.D1.R0.S09: RdDqDqs FSM results: Left = 10, Right = 63, center = 36
N0.C3.D1.R0.S08: RxDqsDelay = 034
N2.C0.D1.R1.S12: Total Receive Enable Delay = 1247
N4.C3.D1.R1.S15: RxDqsDelay = 040
N6.C3.D1.R0.S09: RxDqsDelay = 036
N0.C3.D1.R0.S09: RdDqDqs FSM results: Left = 14, Right = 63, center = 38
N2.C0.D1.R1.S13: Total Receive Enable Delay = 1237
N4.C3.D1.R1.S16: RdDqDqs FSM results: Left = 11, Right = 63, center = 37
N6.C3.D1.R0.S10: RdDqDqs FSM results: Left = 07, Right = 63, center = 35
N0.C3.D1.R0.S09: RxDqsDelay = 038
N2.C0.D1.R1.S14: Total Receive Enable Delay = 1261
N4.C3.D1.R1.S16: RxDqsDelay = 037
N6.C3.D1.R0.S10: RxDqsDelay = 035
N0.C3.D1.R0.S10: RdDqDqs FSM results: Left = 08, Right = 63, center = 35
N2.C0.D1.R1.S15: Total Receive Enable Delay = 1292
N4.C3.D1.R1.S17: RdDqDqs FSM results: Left = 15, Right = 63, center = 39
N6.C3.D1.R0.S11: RdDqDqs FSM results: Left = 06, Right = 63, center = 34
N0.C3.D1.R0.S10: RxDqsDelay = 035
N2.C0.D1.R1.S16: Total Receive Enable Delay = 1315
N4.C3.D1.R1.S17: RxDqsDelay = 039
N6.C3.D1.R0.S11: RxDqsDelay = 034
N0.C3.D1.R0.S11: RdDqDqs FSM results: Left = 04, Right = 63, center = 33
N2.C0.D1.R1.S17: Total Receive Enable Delay = 1232
START_DATA_RX_DQS
N6.C3.D1.R0.S12: RdDqDqs FSM results: Left = 09, Right = 63, center = 36
N0.C3.D1.R0.S11: RxDqsDelay = 033
START_DATA_REC_EN
N4.C3.R0.S00: PI = 37
N6.C3.D1.R0.S12: RxDqsDelay = 036
N0.C3.D1.R0.S12: RdDqDqs FSM results: Left = 07, Right = 63, center = 35
N2.C0.S00: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N4.C3.R0.S01: PI = 39
N6.C3.D1.R0.S13: RdDqDqs FSM results: Left = 09, Right = 63, center = 36
N0.C3.D1.R0.S12: RxDqsDelay = 035
N2.C0.S01: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N4.C3.R0.S02: PI = 36
N6.C3.D1.R0.S13: RxDqsDelay = 036
N0.C3.D1.R0.S13: RdDqDqs FSM results: Left = 10, Right = 63, center = 36
N2.C0.S02: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 5
N4.C3.R0.S03: PI = 36
N6.C3.D1.R0.S14: RdDqDqs FSM results: Left = 03, Right = 61, center = 32
N0.C3.D1.R0.S13: RxDqsDelay = 036
N2.C0.S03: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 5
N4.C3.R0.S04: PI = 39
N6.C3.D1.R0.S14: RxDqsDelay = 032
N0.C3.D1.R0.S14: RdDqDqs FSM results: Left = 06, Right = 63, center = 34
N2.C0.S04: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 5
N4.C3.R0.S05: PI = 38
N6.C3.D1.R0.S15: RdDqDqs FSM results: Left = 05, Right = 63, center = 34
N0.C3.D1.R0.S14: RxDqsDelay = 034
N2.C0.S05: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 5
N4.C3.R0.S06: PI = 39
N6.C3.D1.R0.S15: RxDqsDelay = 034
N0.C3.D1.R0.S15: RdDqDqs FSM results: Left = 08, Right = 63, center = 35
N2.C0.S06: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N4.C3.R0.S07: PI = 37
N6.C3.D1.R0.S16: RdDqDqs FSM results: Left = 05, Right = 60, center = 32
N0.C3.D1.R0.S15: RxDqsDelay = 035
N2.C0.S07: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N4.C3.R0.S08: PI = 35
N6.C3.D1.R0.S16: RxDqsDelay = 032
N0.C3.D1.R0.S16: RdDqDqs FSM results: Left = 08, Right = 63, center = 35
N2.C0.S08: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 5
N4.C3.R0.S09: PI = 37
N6.C3.D1.R0.S17: RdDqDqs FSM results: Left = 09, Right = 63, center = 36
N0.C3.D1.R0.S16: RxDqsDelay = 035
N2.C0.S09: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N4.C3.R0.S10: PI = 36
N6.C3.D1.R0.S17: RxDqsDelay = 036
N0.C3.D1.R0.S17: RdDqDqs FSM results: Left = 07, Right = 63, center = 35
N2.C0.S10: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N4.C3.R0.S11: PI = 36
N6.C3.D1.R1.S00: RdDqDqs FSM results: Left = 05, Right = 60, center = 32
N0.C3.D1.R0.S17: RxDqsDelay = 035
N2.C0.S11: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 5
N4.C3.R0.S12: PI = 37
N6.C3.D1.R1.S00: RxDqsDelay = 032
N0.C3.D1.R1.S00: RdDqDqs FSM results: Left = 09, Right = 63, center = 36
N2.C0.S12: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 5
N4.C3.R0.S13: PI = 36
N6.C3.D1.R1.S01: RdDqDqs FSM results: Left = 07, Right = 63, center = 35
N0.C3.D1.R1.S00: RxDqsDelay = 036
N2.C0.S13: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 5
N4.C3.R0.S14: PI = 37
N6.C3.D1.R1.S01: RxDqsDelay = 035
N0.C3.D1.R1.S01: RdDqDqs FSM results: Left = 09, Right = 63, center = 36
N2.C0.S14: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 5
N4.C3.R0.S15: PI = 38
N6.C3.D1.R1.S02: RdDqDqs FSM results: Left = 06, Right = 63, center = 34
N0.C3.D1.R1.S01: RxDqsDelay = 036
N2.C0.S15: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N4.C3.R0.S16: PI = 35
N6.C3.D1.R1.S02: RxDqsDelay = 034
N0.C3.D1.R1.S02: RdDqDqs FSM results: Left = 08, Right = 63, center = 35
N2.C0.S16: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N4.C3.R0.S17: PI = 37
N6.C3.D1.R1.S03: RdDqDqs FSM results: Left = 06, Right = 63, center = 34
N0.C3.D1.R1.S02: RxDqsDelay = 035
N2.C0.S17: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 5
N4.C3.R0.S00: PI = 37
N6.C3.D1.R1.S03: RxDqsDelay = 034
N0.C3.D1.R1.S03: RdDqDqs FSM results: Left = 09, Right = 63, center = 36
N2.C0.D0.R0.S00: RcvEn: plus1 = 1, minus1 = 0, PI = 47, DB = 0
N4.C3.R0.S01: PI = 39
N6.C3.D1.R1.S04: RdDqDqs FSM results: Left = 13, Right = 63, center = 38
N0.C3.D1.R1.S03: RxDqsDelay = 036
N2.C0.D0.R0.S01: RcvEn: plus1 = 1, minus1 = 0, PI = 27, DB = 0
N4.C3.R0.S02: PI = 36
N6.C3.D1.R1.S04: RxDqsDelay = 038
N0.C3.D1.R1.S04: RdDqDqs FSM results: Left = 10, Right = 63, center = 36
N2.C0.D0.R0.S02: RcvEn: plus1 = 1, minus1 = 0, PI = 62, DB = 1
N4.C3.R0.S03: PI = 36
N6.C3.D1.R1.S05: RdDqDqs FSM results: Left = 08, Right = 63, center = 35
N0.C3.D1.R1.S04: RxDqsDelay = 036
N2.C0.D0.R0.S03: RcvEn: plus1 = 1, minus1 = 0, PI = 40, DB = 0
N4.C3.R0.S04: PI = 39
N6.C3.D1.R1.S05: RxDqsDelay = 035
N0.C3.D1.R1.S05: RdDqDqs FSM results: Left = 09, Right = 63, center = 36
N2.C0.D0.R0.S04: RcvEn: plus1 = 1, minus1 = 0, PI = 33, DB = 0
N4.C3.R0.S05: PI = 38
N6.C3.D1.R1.S06: RdDqDqs FSM results: Left = 09, Right = 63, center = 36
N0.C3.D1.R1.S05: RxDqsDelay = 036
N2.C0.D0.R0.S05: RcvEn: plus1 = 1, minus1 = 0, PI = 58, DB = 1
N4.C3.R0.S06: PI = 39
N6.C3.D1.R1.S06: RxDqsDelay = 036
N0.C3.D1.R1.S06: RdDqDqs FSM results: Left = 10, Right = 63, center = 36
N2.C0.D0.R0.S06: RcvEn: plus1 = 1, minus1 = 0, PI = 26, DB = 0
N4.C3.R0.S07: PI = 37
N6.C3.D1.R1.S07: RdDqDqs FSM results: Left = 09, Right = 63, center = 36
N0.C3.D1.R1.S06: RxDqsDelay = 036
N2.C0.D0.R0.S07: RcvEn: plus1 = 1, minus1 = 0, PI = 48, DB = 0
N4.C3.R0.S08: PI = 35
N6.C3.D1.R1.S07: RxDqsDelay = 036
N0.C3.D1.R1.S07: RdDqDqs FSM results: Left = 07, Right = 63, center = 35
N2.C0.D0.R0.S08: RcvEn: plus1 = 1, minus1 = 0, PI = 29, DB = 0
N4.C3.R0.S09: PI = 37
N6.C3.D1.R1.S08: RdDqDqs FSM results: Left = 07, Right = 63, center = 35
N0.C3.D1.R1.S07: RxDqsDelay = 035
N2.C0.D0.R0.S09: RcvEn: plus1 = 1, minus1 = 0, PI = 46, DB = 0
N4.C3.R0.S10: PI = 36
N6.C3.D1.R1.S08: RxDqsDelay = 035
N0.C3.D1.R1.S08: RdDqDqs FSM results: Left = 05, Right = 63, center = 34
N2.C0.D0.R0.S10: RcvEn: plus1 = 1, minus1 = 0, PI = 27, DB = 0
N4.C3.R0.S11: PI = 36
N6.C3.D1.R1.S09: RdDqDqs FSM results: Left = 10, Right = 63, center = 36
N0.C3.D1.R1.S08: RxDqsDelay = 034
N2.C0.D0.R0.S11: RcvEn: plus1 = 1, minus1 = 0, PI = 63, DB = 1
N4.C3.R0.S12: PI = 37
N6.C3.D1.R1.S09: RxDqsDelay = 036
N0.C3.D1.R1.S09: RdDqDqs FSM results: Left = 13, Right = 63, center = 38
N2.C0.D0.R0.S12: RcvEn: plus1 = 1, minus1 = 0, PI = 43, DB = 0
N4.C3.R0.S13: PI = 36
N6.C3.D1.R1.S10: RdDqDqs FSM results: Left = 07, Right = 63, center = 35
N0.C3.D1.R1.S09: RxDqsDelay = 038
N2.C0.D0.R0.S13: RcvEn: plus1 = 1, minus1 = 0, PI = 32, DB = 0
N4.C3.R0.S14: PI = 37
N6.C3.D1.R1.S10: RxDqsDelay = 035
N0.C3.D1.R1.S10: RdDqDqs FSM results: Left = 08, Right = 63, center = 35
N2.C0.D0.R0.S14: RcvEn: plus1 = 1, minus1 = 0, PI = 57, DB = 1
N4.C3.R0.S15: PI = 38
N6.C3.D1.R1.S11: RdDqDqs FSM results: Left = 07, Right = 63, center = 35
N0.C3.D1.R1.S10: RxDqsDelay = 035
N2.C0.D0.R0.S15: RcvEn: plus1 = 1, minus1 = 0, PI = 26, DB = 0
N4.C3.R0.S16: PI = 35
N6.C3.D1.R1.S11: RxDqsDelay = 035
N0.C3.D1.R1.S11: RdDqDqs FSM results: Left = 05, Right = 63, center = 34
N2.C0.D0.R0.S16: RcvEn: plus1 = 1, minus1 = 0, PI = 47, DB = 0
N4.C3.R0.S17: PI = 37
N6.C3.D1.R1.S12: RdDqDqs FSM results: Left = 09, Right = 63, center = 36
N0.C3.D1.R1.S11: RxDqsDelay = 034
N2.C0.D0.R0.S17: RcvEn: plus1 = 1, minus1 = 0, PI = 28, DB = 0
N4.C3.R2.S00: PI = 40
N6.C3.D1.R1.S12: RxDqsDelay = 036
N0.C3.D1.R1.S12: RdDqDqs FSM results: Left = 06, Right = 63, center = 34
N2.C0.D0.R1.S00: RcvEn: plus1 = 1, minus1 = 0, PI = 47, DB = 0
N4.C3.R2.S01: PI = 41
N6.C3.D1.R1.S13: RdDqDqs FSM results: Left = 10, Right = 63, center = 36
N0.C3.D1.R1.S12: RxDqsDelay = 034
N2.C0.D0.R1.S01: RcvEn: plus1 = 1, minus1 = 0, PI = 27, DB = 0
N4.C3.R2.S02: PI = 37
N6.C3.D1.R1.S13: RxDqsDelay = 036
N0.C3.D1.R1.S13: RdDqDqs FSM results: Left = 10, Right = 63, center = 36
N2.C0.D0.R1.S02: RcvEn: plus1 = 1, minus1 = 0, PI = 62, DB = 1
N4.C3.R2.S03: PI = 39
N6.C3.D1.R1.S14: RdDqDqs FSM results: Left = 03, Right = 59, center = 31
N0.C3.D1.R1.S13: RxDqsDelay = 036
N2.C0.D0.R1.S03: RcvEn: plus1 = 1, minus1 = 0, PI = 40, DB = 0
N4.C3.R2.S04: PI = 41
N6.C3.D1.R1.S14: RxDqsDelay = 031
N0.C3.D1.R1.S14: RdDqDqs FSM results: Left = 05, Right = 63, center = 34
N2.C0.D0.R1.S04: RcvEn: plus1 = 1, minus1 = 0, PI = 33, DB = 0
N4.C3.R2.S05: PI = 40
N6.C3.D1.R1.S15: RdDqDqs FSM results: Left = 06, Right = 63, center = 34
N0.C3.D1.R1.S14: RxDqsDelay = 034
N2.C0.D0.R1.S05: RcvEn: plus1 = 1, minus1 = 0, PI = 58, DB = 1
N4.C3.R2.S06: PI = 41
N6.C3.D1.R1.S15: RxDqsDelay = 034
N0.C3.D1.R1.S15: RdDqDqs FSM results: Left = 06, Right = 63, center = 34
N2.C0.D0.R1.S06: RcvEn: plus1 = 1, minus1 = 0, PI = 26, DB = 0
N4.C3.R2.S07: PI = 38
N6.C3.D1.R1.S16: RdDqDqs FSM results: Left = 05, Right = 61, center = 33
N0.C3.D1.R1.S15: RxDqsDelay = 034
N2.C0.D0.R1.S07: RcvEn: plus1 = 1, minus1 = 0, PI = 48, DB = 0
N4.C3.R2.S08: PI = 36
N6.C3.D1.R1.S16: RxDqsDelay = 033
N0.C3.D1.R1.S16: RdDqDqs FSM results: Left = 06, Right = 63, center = 34
N2.C0.D0.R1.S08: RcvEn: plus1 = 1, minus1 = 0, PI = 29, DB = 0
N4.C3.R2.S09: PI = 39
N6.C3.D1.R1.S17: RdDqDqs FSM results: Left = 09, Right = 63, center = 36
N0.C3.D1.R1.S16: RxDqsDelay = 034
N2.C0.D0.R1.S09: RcvEn: plus1 = 1, minus1 = 0, PI = 46, DB = 0
N4.C3.R2.S10: PI = 38
N6.C3.D1.R1.S17: RxDqsDelay = 036
N0.C3.D1.R1.S17: RdDqDqs FSM results: Left = 07, Right = 63, center = 35
N2.C0.D0.R1.S10: RcvEn: plus1 = 1, minus1 = 0, PI = 27, DB = 0
N4.C3.R2.S11: PI = 37
START_DATA_RX_DQS
N0.C3.D1.R1.S17: RxDqsDelay = 035
N2.C0.D0.R1.S11: RcvEn: plus1 = 1, minus1 = 0, PI = 63, DB = 1
N4.C3.R2.S12: PI = 39
N6.C3.R0.S00: PI = 31
START_DATA_RX_DQS
N2.C0.D0.R1.S12: RcvEn: plus1 = 1, minus1 = 0, PI = 43, DB = 0
N4.C3.R2.S13: PI = 37
N6.C3.R0.S01: PI = 33
N0.C3.R0.S00: PI = 34
N2.C0.D0.R1.S13: RcvEn: plus1 = 1, minus1 = 0, PI = 32, DB = 0
N4.C3.R2.S14: PI = 39
N6.C3.R0.S02: PI = 33
N0.C3.R0.S01: PI = 34
N2.C0.D0.R1.S14: RcvEn: plus1 = 1, minus1 = 0, PI = 57, DB = 1
N4.C3.R2.S15: PI = 40
N6.C3.R0.S03: PI = 32
N0.C3.R0.S02: PI = 33
N2.C0.D0.R1.S15: RcvEn: plus1 = 1, minus1 = 0, PI = 26, DB = 0
N4.C3.R2.S16: PI = 37
N6.C3.R0.S04: PI = 36
N0.C3.R0.S03: PI = 34
N2.C0.D0.R1.S16: RcvEn: plus1 = 1, minus1 = 0, PI = 47, DB = 0
N4.C3.R2.S17: PI = 39
N6.C3.R0.S05: PI = 34
N0.C3.R0.S04: PI = 35
N2.C0.D0.R1.S17: RcvEn: plus1 = 1, minus1 = 0, PI = 28, DB = 0
N4.C3.R2.S00: PI = 40
N6.C3.R0.S06: PI = 33
N0.C3.R0.S05: PI = 34
N2.C0.D1.R0.S00: RcvEn: plus1 = 1, minus1 = 0, PI = 32, DB = 0
N4.C3.R2.S01: PI = 41
N6.C3.R0.S07: PI = 34
N0.C3.R0.S06: PI = 35
N2.C0.D1.R0.S01: RcvEn: plus1 = 1, minus1 = 0, PI = 17, DB = 0
N4.C3.R2.S02: PI = 37
N6.C3.R0.S08: PI = 33
N0.C3.R0.S07: PI = 33
N2.C0.D1.R0.S02: RcvEn: plus1 = 1, minus1 = 0, PI = 50, DB = 1
N4.C3.R2.S03: PI = 39
N6.C3.R0.S09: PI = 34
N0.C3.R0.S08: PI = 32
N2.C0.D1.R0.S03: RcvEn: plus1 = 1, minus1 = 0, PI = 30, DB = 0
N4.C3.R2.S04: PI = 41
N6.C3.R0.S10: PI = 32
N0.C3.R0.S09: PI = 36
N2.C0.D1.R0.S04: RcvEn: plus1 = 1, minus1 = 0, PI = 23, DB = 0
N4.C3.R2.S05: PI = 40
N6.C3.R0.S11: PI = 33
N0.C3.R0.S10: PI = 33
N2.C0.D1.R0.S05: RcvEn: plus1 = 1, minus1 = 0, PI = 46, DB = 0
N4.C3.R2.S06: PI = 41
N6.C3.R0.S12: PI = 34
N0.C3.R0.S11: PI = 32
N2.C0.D1.R0.S06: RcvEn: plus1 = 1, minus1 = 0, PI = 13, DB = 1
N4.C3.R2.S07: PI = 38
N6.C3.R0.S13: PI = 34
N0.C3.R0.S12: PI = 34
N2.C0.D1.R0.S07: RcvEn: plus1 = 1, minus1 = 0, PI = 36, DB = 0
N4.C3.R2.S08: PI = 36
N6.C3.R0.S14: PI = 29
N0.C3.R0.S13: PI = 35
N2.C0.D1.R0.S08: RcvEn: plus1 = 1, minus1 = 0, PI = 18, DB = 0
N4.C3.R2.S09: PI = 39
N6.C3.R0.S15: PI = 31
N0.C3.R0.S14: PI = 33
N2.C0.D1.R0.S09: RcvEn: plus1 = 1, minus1 = 0, PI = 34, DB = 0
N4.C3.R2.S10: PI = 38
N6.C3.R0.S16: PI = 31
N0.C3.R0.S15: PI = 34
N2.C0.D1.R0.S10: RcvEn: plus1 = 1, minus1 = 0, PI = 13, DB = 1
N4.C3.R2.S11: PI = 37
N6.C3.R0.S17: PI = 33
N0.C3.R0.S16: PI = 33
N2.C0.D1.R0.S11: RcvEn: plus1 = 1, minus1 = 0, PI = 50, DB = 1
N4.C3.R2.S12: PI = 39
N6.C3.R0.S00: PI = 31
N0.C3.R0.S17: PI = 33
N2.C0.D1.R0.S12: RcvEn: plus1 = 1, minus1 = 0, PI = 30, DB = 0
N4.C3.R2.S13: PI = 37
N6.C3.R0.S01: PI = 33
N0.C3.R0.S00: PI = 34
N2.C0.D1.R0.S13: RcvEn: plus1 = 1, minus1 = 0, PI = 21, DB = 0
N4.C3.R2.S14: PI = 39
N6.C3.R0.S02: PI = 33
N0.C3.R0.S01: PI = 34
N2.C0.D1.R0.S14: RcvEn: plus1 = 1, minus1 = 0, PI = 45, DB = 0
N4.C3.R2.S15: PI = 40
N6.C3.R0.S03: PI = 32
N0.C3.R0.S02: PI = 33
N2.C0.D1.R0.S15: RcvEn: plus1 = 1, minus1 = 0, PI = 11, DB = 1
N4.C3.R2.S16: PI = 37
N6.C3.R0.S04: PI = 36
N0.C3.R0.S03: PI = 34
N2.C0.D1.R0.S16: RcvEn: plus1 = 1, minus1 = 0, PI = 35, DB = 0
N4.C3.R2.S17: PI = 39
N6.C3.R0.S05: PI = 34
N0.C3.R0.S04: PI = 35
N2.C0.D1.R0.S17: RcvEn: plus1 = 1, minus1 = 0, PI = 16, DB = 0
STOP_DATA_RX_DQS
N6.C3.R0.S06: PI = 33
N0.C3.R0.S05: PI = 34
N2.C0.D1.R1.S00: RcvEn: plus1 = 1, minus1 = 0, PI = 32, DB = 0
N4: RunTrainStep: Final status = 0
N6.C3.R0.S07: PI = 34
N0.C3.R0.S06: PI = 35
N2.C0.D1.R1.S01: RcvEn: plus1 = 1, minus1 = 0, PI = 17, DB = 0

END - Basic Read DQ/DQS Training       Time         17134 ms
N6.C3.R0.S08: PI = 33
N0.C3.R0.S07: PI = 33
N2.C0.D1.R1.S02: RcvEn: plus1 = 1, minus1 = 0, PI = 50, DB = 1

START - Basic Receive Enable Training
N6.C3.R0.S09: PI = 34
N0.C3.R0.S08: PI = 32
N2.C0.D1.R1.S03: RcvEn: plus1 = 1, minus1 = 0, PI = 30, DB = 0
N4.C0: QCRM debug: extraRcvEnLatency = 0
N6.C3.R0.S10: PI = 32
N0.C3.R0.S09: PI = 36
N2.C0.D1.R1.S04: RcvEn: plus1 = 1, minus1 = 0, PI = 23, DB = 0
N4.C0: SettingForTrainingStep: RdCmd2RcvEnLatency = 10, RdPtrOffsetRcvEn = 4
N6.C3.R0.S11: PI = 33
N0.C3.R0.S10: PI = 33
N2.C0.D1.R1.S05: RcvEn: plus1 = 1, minus1 = 0, PI = 46, DB = 0
N4.C1: QCRM debug: extraRcvEnLatency = 0
N6.C3.R0.S12: PI = 34
N0.C3.R0.S11: PI = 32
N2.C0.D1.R1.S06: RcvEn: plus1 = 1, minus1 = 0, PI = 13, DB = 1
N4.C1: SettingForTrainingStep: RdCmd2RcvEnLatency = 10, RdPtrOffsetRcvEn = 4
N6.C3.R0.S13: PI = 34
N0.C3.R0.S12: PI = 34
N2.C0.D1.R1.S07: RcvEn: plus1 = 1, minus1 = 0, PI = 36, DB = 0
N4.C2: QCRM debug: extraRcvEnLatency = 0
N6.C3.R0.S14: PI = 29
N0.C3.R0.S13: PI = 35
N2.C0.D1.R1.S08: RcvEn: plus1 = 1, minus1 = 0, PI = 18, DB = 0
N4.C2: SettingForTrainingStep: RdCmd2RcvEnLatency = 10, RdPtrOffsetRcvEn = 4
N6.C3.R0.S15: PI = 31
N0.C3.R0.S14: PI = 33
N2.C0.D1.R1.S09: RcvEn: plus1 = 1, minus1 = 0, PI = 34, DB = 0
N4.C3: QCRM debug: extraRcvEnLatency = 0
N6.C3.R0.S16: PI = 31
N0.C3.R0.S15: PI = 34
N2.C0.D1.R1.S10: RcvEn: plus1 = 1, minus1 = 0, PI = 13, DB = 1
N4.C3: SettingForTrainingStep: RdCmd2RcvEnLatency = 10, RdPtrOffsetRcvEn = 4
N6.C3.R0.S17: PI = 33
N0.C3.R0.S16: PI = 33
N2.C0.D1.R1.S11: RcvEn: plus1 = 1, minus1 = 0, PI = 50, DB = 1
N4.C0.D0.R0: RcvEnFine: Initial RdCmd2RcvEnLatency = 10, Initial RdPtrOffsetRcvEn = 4
N6.C3.R2.S00: PI = 33
N0.C3.R0.S17: PI = 33
N2.C0.D1.R1.S12: RcvEn: plus1 = 1, minus1 = 0, PI = 30, DB = 0
N4.C0.D0.R0.S00: Rcv En Fine Value = 267
N6.C3.R2.S01: PI = 34
N0.C3.R2.S00: PI = 36
N2.C0.D1.R1.S13: RcvEn: plus1 = 1, minus1 = 0, PI = 21, DB = 0
N4.C0.D0.R0.S01: Rcv En Fine Value = 374
N6.C3.R2.S02: PI = 34
N0.C3.R2.S01: PI = 36
N2.C0.D1.R1.S14: RcvEn: plus1 = 1, minus1 = 0, PI = 45, DB = 0
N4.C0.D0.R0.S02: Rcv En Fine Value = 348
N6.C3.R2.S03: PI = 34
N0.C3.R2.S02: PI = 35
N2.C0.D1.R1.S15: RcvEn: plus1 = 1, minus1 = 0, PI = 11, DB = 1
N4.C0.D0.R0.S03: Rcv En Fine Value = 326
N6.C3.R2.S04: PI = 38
N0.C3.R2.S03: PI = 36
N2.C0.D1.R1.S16: RcvEn: plus1 = 1, minus1 = 0, PI = 35, DB = 0
N4.C0.D0.R0.S04: Rcv En Fine Value = 320
N6.C3.R2.S05: PI = 35
N0.C3.R2.S04: PI = 36
N2.C0.D1.R1.S17: RcvEn: plus1 = 1, minus1 = 0, PI = 16, DB = 0
N4.C0.D0.R0.S05: Rcv En Fine Value = 344
N6.C3.R2.S06: PI = 36
N0.C3.R2.S05: PI = 36
STOP_DATA_REC_EN
N4.C0.D0.R0.S06: Rcv En Fine Value = 374
N6.C3.R2.S07: PI = 36
N0.C3.R2.S06: PI = 36
N2.C1.D0.R0: RcvEnFine: Initial RdCmd2RcvEnLatency = 10, Initial RdPtrOffsetRcvEn = 4
N4.C0.D0.R0.S07: Rcv En Fine Value = 268
N6.C3.R2.S08: PI = 35
N0.C3.R2.S07: PI = 35
N2.C1.D0.R0.S00: Rcv En Fine Value = 317
N4.C0.D0.R0.S08: Rcv En Fine Value = 312
N6.C3.R2.S09: PI = 36
N0.C3.R2.S08: PI = 34
N2.C1.D0.R0.S01: Rcv En Fine Value = 298
N4.C0.D0.R0.S09: Rcv En Fine Value = 266
N6.C3.R2.S10: PI = 35
N0.C3.R2.S09: PI = 38
N2.C1.D0.R0.S02: Rcv En Fine Value = 270
N4.C0.D0.R0.S10: Rcv En Fine Value = 376
N6.C3.R2.S11: PI = 34
N0.C3.R2.S10: PI = 35
N2.C1.D0.R0.S03: Rcv En Fine Value = 378
N4.C0.D0.R0.S11: Rcv En Fine Value = 348
N6.C3.R2.S12: PI = 36
N0.C3.R2.S11: PI = 33
N2.C1.D0.R0.S04: Rcv En Fine Value = 372
N4.C0.D0.R0.S12: Rcv En Fine Value = 326
N6.C3.R2.S13: PI = 36
N0.C3.R2.S12: PI = 34
N2.C1.D0.R0.S05: Rcv En Fine Value = 268
N4.C0.D0.R0.S13: Rcv En Fine Value = 319
N6.C3.R2.S14: PI = 31
N0.C3.R2.S13: PI = 36
N2.C1.D0.R0.S06: Rcv En Fine Value = 293
N4.C0.D0.R0.S14: Rcv En Fine Value = 342
N6.C3.R2.S15: PI = 34
N0.C3.R2.S14: PI = 34
N2.C1.D0.R0.S07: Rcv En Fine Value = 312
N4.C0.D0.R0.S15: Rcv En Fine Value = 371
N6.C3.R2.S16: PI = 32
N0.C3.R2.S15: PI = 34
N2.C1.D0.R0.S08: Rcv En Fine Value = 358
N4.C0.D0.R0.S16: Rcv En Fine Value = 266
N6.C3.R2.S17: PI = 36
N0.C3.R2.S16: PI = 34
N2.C1.D0.R0.S09: Rcv En Fine Value = 318
N4.C0.D0.R0.S17: Rcv En Fine Value = 311
N6.C3.R2.S00: PI = 33
N0.C3.R2.S17: PI = 35
N2.C1.D0.R0.S10: Rcv En Fine Value = 299
N4.C0.D0.R0: Starting preamble search lower nibbles
N6.C3.R2.S01: PI = 34
N0.C3.R2.S00: PI = 36
N2.C1.D0.R0.S11: Rcv En Fine Value = 270
N4.C0.D0.R0.S00: PI = 011, PtrOffset = 004
N6.C3.R2.S02: PI = 34
N0.C3.R2.S01: PI = 36
N2.C1.D0.R0.S12: Rcv En Fine Value = 379
N4.C0.D0.R0.S01: PI = 054, PtrOffset = 005
N6.C3.R2.S03: PI = 34
N0.C3.R2.S02: PI = 35
N2.C1.D0.R0.S13: Rcv En Fine Value = 369
N4.C0.D0.R0.S02: PI = 028, PtrOffset = 005
N6.C3.R2.S04: PI = 38
N0.C3.R2.S03: PI = 36
N2.C1.D0.R0.S14: Rcv En Fine Value = 268
N4.C0.D0.R0.S03: PI = 006, PtrOffset = 005
N6.C3.R2.S05: PI = 35
N0.C3.R2.S04: PI = 36
N2.C1.D0.R0.S15: Rcv En Fine Value = 294
N4.C0.D0.R0.S04: PI = 000, PtrOffset = 005
N6.C3.R2.S06: PI = 36
N0.C3.R2.S05: PI = 36
N2.C1.D0.R0.S16: Rcv En Fine Value = 310
N4.C0.D0.R0.S05: PI = 024, PtrOffset = 005
N6.C3.R2.S07: PI = 36
N0.C3.R2.S06: PI = 36
N2.C1.D0.R0.S17: Rcv En Fine Value = 359
N4.C0.D0.R0.S06: PI = 054, PtrOffset = 005
N6.C3.R2.S08: PI = 35
N0.C3.R2.S07: PI = 35
N2.C1.D0.R0: Starting preamble search lower nibbles
N4.C0.D0.R0.S07: PI = 012, PtrOffset = 004
N6.C3.R2.S09: PI = 36
N0.C3.R2.S08: PI = 34
N2.C1.D0.R0.S00: PI = 061, PtrOffset = 004
N4.C0.D0.R0.S08: PI = 056, PtrOffset = 004
N6.C3.R2.S10: PI = 35
N0.C3.R2.S09: PI = 38
N2.C1.D0.R0.S01: PI = 042, PtrOffset = 004
N4.C0.D0.R0.S00: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N6.C3.R2.S11: PI = 34
N0.C3.R2.S10: PI = 35
N2.C1.D0.R0.S02: PI = 014, PtrOffset = 004
N4.C0.D0.R0.S01: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N6.C3.R2.S12: PI = 36
N0.C3.R2.S11: PI = 33
N2.C1.D0.R0.S03: PI = 058, PtrOffset = 005
N4.C0.D0.R0.S02: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N6.C3.R2.S13: PI = 36
N0.C3.R2.S12: PI = 34
N2.C1.D0.R0.S04: PI = 052, PtrOffset = 005
N4.C0.D0.R0.S03: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N6.C3.R2.S14: PI = 31
N0.C3.R2.S13: PI = 36
N2.C1.D0.R0.S05: PI = 012, PtrOffset = 004
N4.C0.D0.R0.S04: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N6.C3.R2.S15: PI = 34
N0.C3.R2.S14: PI = 34
N2.C1.D0.R0.S06: PI = 037, PtrOffset = 004
N4.C0.D0.R0.S05: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N6.C3.R2.S16: PI = 32
N0.C3.R2.S15: PI = 34
N2.C1.D0.R0.S07: PI = 056, PtrOffset = 004
N4.C0.D0.R0.S06: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N6.C3.R2.S17: PI = 36
N0.C3.R2.S16: PI = 34
N2.C1.D0.R0.S08: PI = 038, PtrOffset = 005
N4.C0.D0.R0.S07: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
STOP_DATA_RX_DQS
N0.C3.R2.S17: PI = 35
N2.C1.D0.R0.S00: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N4.C0.D0.R0.S08: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N6: RunTrainStep: Final status = 0
STOP_DATA_RX_DQS
N2.C1.D0.R0.S01: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N4.C0.D0.R0.S00: RcvEnCoarse: Latency = 009, RdPtr Offset = 4

END - Basic Read DQ/DQS Training       Time         17137 ms
N0: RunTrainStep: Final status = 0
N2.C1.D0.R0.S02: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N4.C0.D0.R0.S01: RcvEnCoarse: Latency = 009, RdPtr Offset = 5

START - Basic Receive Enable Training

END - Basic Read DQ/DQS Training       Time         17158 ms
N2.C1.D0.R0.S03: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N4.C0.D0.R0.S02: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N6.C0: QCRM debug: extraRcvEnLatency = 0

START - Basic Receive Enable Training
N2.C1.D0.R0.S04: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N4.C0.D0.R0.S03: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N6.C0: SettingForTrainingStep: RdCmd2RcvEnLatency = 10, RdPtrOffsetRcvEn = 4
Checkpoint Code: Socket 0, 0xB7, 0x02, 0x0000
N2.C1.D0.R0.S05: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N4.C0.D0.R0.S04: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N6.C1: QCRM debug: extraRcvEnLatency = 0
N0.C0: QCRM debug: extraRcvEnLatency = 0
N2.C1.D0.R0.S06: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N4.C0.D0.R0.S05: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N6.C1: SettingForTrainingStep: RdCmd2RcvEnLatency = 10, RdPtrOffsetRcvEn = 4
N0.C0: SettingForTrainingStep: RdCmd2RcvEnLatency = 10, RdPtrOffsetRcvEn = 4
N2.C1.D0.R0.S07: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N4.C0.D0.R0.S06: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N6.C2: QCRM debug: extraRcvEnLatency = 0
N0.C1: QCRM debug: extraRcvEnLatency = 0
N2.C1.D0.R0.S08: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N4.C0.D0.R0.S07: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N6.C2: SettingForTrainingStep: RdCmd2RcvEnLatency = 10, RdPtrOffsetRcvEn = 4
N0.C1: SettingForTrainingStep: RdCmd2RcvEnLatency = 10, RdPtrOffsetRcvEn = 4
N2.C1.D0.R0.S00: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N4.C0.D0.R0.S08: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N6.C3: QCRM debug: extraRcvEnLatency = 0
N0.C2: QCRM debug: extraRcvEnLatency = 0
N2.C1.D0.R0.S01: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N4.C0.D0.R0.S00: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N6.C3: SettingForTrainingStep: RdCmd2RcvEnLatency = 10, RdPtrOffsetRcvEn = 4
N0.C2: SettingForTrainingStep: RdCmd2RcvEnLatency = 10, RdPtrOffsetRcvEn = 4
N2.C1.D0.R0.S02: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N4.C0.D0.R0.S01: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N6.C0.D0.R0: RcvEnFine: Initial RdCmd2RcvEnLatency = 10, Initial RdPtrOffsetRcvEn = 4
N0.C3: QCRM debug: extraRcvEnLatency = 0
N2.C1.D0.R0.S03: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N4.C0.D0.R0.S02: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N6.C0.D0.R0.S00: Rcv En Fine Value = 278
N0.C3: SettingForTrainingStep: RdCmd2RcvEnLatency = 10, RdPtrOffsetRcvEn = 4
N2.C1.D0.R0.S04: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N4.C0.D0.R0.S03: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N6.C0.D0.R0.S01: Rcv En Fine Value = 383
N0.C0.D0.R0: RcvEnFine: Initial RdCmd2RcvEnLatency = 10, Initial RdPtrOffsetRcvEn = 4
N2.C1.D0.R0.S05: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N4.C0.D0.R0.S04: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N6.C0.D0.R0.S02: Rcv En Fine Value = 355
N0.C0.D0.R0.S00: Rcv En Fine Value = 264
N2.C1.D0.R0.S06: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N4.C0.D0.R0.S05: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N6.C0.D0.R0.S03: Rcv En Fine Value = 336
N0.C0.D0.R0.S01: Rcv En Fine Value = 375
N2.C1.D0.R0.S07: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N4.C0.D0.R0.S06: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N6.C0.D0.R0.S04: Rcv En Fine Value = 328
N0.C0.D0.R0.S02: Rcv En Fine Value = 347
N2.C1.D0.R0.S08: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N4.C0.D0.R0.S07: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N6.C0.D0.R0.S05: Rcv En Fine Value = 350
N0.C0.D0.R0.S03: Rcv En Fine Value = 329
N2.C1.D0.R0.S00: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N4.C0.D0.R0.S08: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N6.C0.D0.R0.S06: Rcv En Fine Value = 382
N0.C0.D0.R0.S04: Rcv En Fine Value = 320
N2.C1.D0.R0.S01: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N4.C0.D0.R0.S00: Preamble found at Latency = 008
N6.C0.D0.R0.S07: Rcv En Fine Value = 275
N0.C0.D0.R0.S05: Rcv En Fine Value = 341
N2.C1.D0.R0.S02: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N4.C0.D0.R0.S07: Preamble found at Latency = 008
N6.C0.D0.R0.S08: Rcv En Fine Value = 323
N0.C0.D0.R0.S06: Rcv En Fine Value = 377
N2.C1.D0.R0.S03: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N4.C0.D0.R0.S00: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N6.C0.D0.R0.S09: Rcv En Fine Value = 275
N0.C0.D0.R0.S07: Rcv En Fine Value = 270
N2.C1.D0.R0.S04: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N4.C0.D0.R0.S01: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N6.C0.D0.R0.S10: Rcv En Fine Value = 382
N0.C0.D0.R0.S08: Rcv En Fine Value = 316
N2.C1.D0.R0.S05: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N4.C0.D0.R0.S02: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N6.C0.D0.R0.S11: Rcv En Fine Value = 355
N0.C0.D0.R0.S09: Rcv En Fine Value = 267
N2.C1.D0.R0.S06: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N4.C0.D0.R0.S03: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N6.C0.D0.R0.S12: Rcv En Fine Value = 335
N0.C0.D0.R0.S10: Rcv En Fine Value = 373
N2.C1.D0.R0.S07: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N4.C0.D0.R0.S04: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N6.C0.D0.R0.S13: Rcv En Fine Value = 327
N0.C0.D0.R0.S11: Rcv En Fine Value = 344
N2.C1.D0.R0.S08: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N4.C0.D0.R0.S05: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N6.C0.D0.R0.S14: Rcv En Fine Value = 351
N0.C0.D0.R0.S12: Rcv En Fine Value = 327
N2.C1.D0.R0.S00: Preamble found at Latency = 008
N4.C0.D0.R0.S06: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N6.C0.D0.R0.S15: Rcv En Fine Value = 380
N0.C0.D0.R0.S13: Rcv En Fine Value = 321
N2.C1.D0.R0.S01: Preamble found at Latency = 008
N4.C0.D0.R0.S07: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N6.C0.D0.R0.S16: Rcv En Fine Value = 276
N0.C0.D0.R0.S14: Rcv En Fine Value = 343
N2.C1.D0.R0.S02: Preamble found at Latency = 008
N4.C0.D0.R0.S08: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N6.C0.D0.R0.S17: Rcv En Fine Value = 321
N0.C0.D0.R0.S15: Rcv En Fine Value = 374
N2.C1.D0.R0.S05: Preamble found at Latency = 008
N4.C0.D0.R0.S01: Preamble found at Latency = 007
N6.C0.D0.R0: Starting preamble search lower nibbles
N0.C0.D0.R0.S16: Rcv En Fine Value = 270
N2.C1.D0.R0.S06: Preamble found at Latency = 008
N4.C0.D0.R0.S02: Preamble found at Latency = 007
N6.C0.D0.R0.S00: PI = 022, PtrOffset = 004
N0.C0.D0.R0.S17: Rcv En Fine Value = 314
N2.C1.D0.R0.S07: Preamble found at Latency = 008
N4.C0.D0.R0.S03: Preamble found at Latency = 007
N6.C0.D0.R0.S01: PI = 063, PtrOffset = 005
N0.C0.D0.R0: Starting preamble search lower nibbles
N2.C1.D0.R0.S00: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N4.C0.D0.R0.S04: Preamble found at Latency = 007
N6.C0.D0.R0.S02: PI = 035, PtrOffset = 005
N0.C0.D0.R0.S00: PI = 008, PtrOffset = 004
N2.C1.D0.R0.S01: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N4.C0.D0.R0.S05: Preamble found at Latency = 007
N6.C0.D0.R0.S03: PI = 016, PtrOffset = 005
N0.C0.D0.R0.S01: PI = 055, PtrOffset = 005
N2.C1.D0.R0.S02: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N4.C0.D0.R0.S06: Preamble found at Latency = 007
N6.C0.D0.R0.S04: PI = 008, PtrOffset = 005
N0.C0.D0.R0.S02: PI = 027, PtrOffset = 005
N2.C1.D0.R0.S03: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N4.C0.D0.R0.S08: Preamble found at Latency = 007
N6.C0.D0.R0.S05: PI = 030, PtrOffset = 005
N0.C0.D0.R0.S03: PI = 009, PtrOffset = 005
N2.C1.D0.R0.S04: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N4.C0.D0.R0.S00: Total Receive Enable Delay = 1323
N6.C0.D0.R0.S06: PI = 062, PtrOffset = 005
N0.C0.D0.R0.S04: PI = 000, PtrOffset = 005
N2.C1.D0.R0.S05: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N4.C0.D0.R0.S01: Total Receive Enable Delay = 1302
N6.C0.D0.R0.S07: PI = 019, PtrOffset = 004
N0.C0.D0.R0.S05: PI = 021, PtrOffset = 005
N2.C1.D0.R0.S06: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N4.C0.D0.R0.S02: Total Receive Enable Delay = 1276
N6.C0.D0.R0.S08: PI = 003, PtrOffset = 005
N0.C0.D0.R0.S06: PI = 057, PtrOffset = 005
N2.C1.D0.R0.S07: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N4.C0.D0.R0.S03: Total Receive Enable Delay = 1254
N6.C0.D0.R0.S00: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N0.C0.D0.R0.S07: PI = 014, PtrOffset = 004
N2.C1.D0.R0.S08: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N4.C0.D0.R0.S04: Total Receive Enable Delay = 1248
N6.C0.D0.R0.S01: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N0.C0.D0.R0.S08: PI = 060, PtrOffset = 004
N2.C1.D0.R0.S03: Preamble found at Latency = 007
N4.C0.D0.R0.S05: Total Receive Enable Delay = 1272
N6.C0.D0.R0.S02: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N0.C0.D0.R0.S00: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N2.C1.D0.R0.S04: Preamble found at Latency = 007
N4.C0.D0.R0.S06: Total Receive Enable Delay = 1302
N6.C0.D0.R0.S03: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N0.C0.D0.R0.S01: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N2.C1.D0.R0.S08: Preamble found at Latency = 007
N4.C0.D0.R0.S07: Total Receive Enable Delay = 1324
N6.C0.D0.R0.S04: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N0.C0.D0.R0.S02: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N2.C1.D0.R0.S00: Total Receive Enable Delay = 1373
N4.C0.D0.R0.S08: Total Receive Enable Delay = 1240
N6.C0.D0.R0.S05: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N0.C0.D0.R0.S03: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N2.C1.D0.R0.S01: Total Receive Enable Delay = 1354
N4.C0.D0.R0: Starting preamble search upper nibbles
N6.C0.D0.R0.S06: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N0.C0.D0.R0.S04: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N2.C1.D0.R0.S02: Total Receive Enable Delay = 1326
N4.C0.D0.R0.S09: PI = 010, PtrOffset = 004
N6.C0.D0.R0.S07: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N0.C0.D0.R0.S05: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N2.C1.D0.R0.S03: Total Receive Enable Delay = 1306
N4.C0.D0.R0.S10: PI = 056, PtrOffset = 005
N6.C0.D0.R0.S08: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N0.C0.D0.R0.S06: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N2.C1.D0.R0.S04: Total Receive Enable Delay = 1300
N4.C0.D0.R0.S11: PI = 028, PtrOffset = 005
N6.C0.D0.R0.S00: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N0.C0.D0.R0.S07: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N2.C1.D0.R0.S05: Total Receive Enable Delay = 1324
N4.C0.D0.R0.S12: PI = 006, PtrOffset = 005
N6.C0.D0.R0.S01: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N0.C0.D0.R0.S08: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N2.C1.D0.R0.S06: Total Receive Enable Delay = 1349
N4.C0.D0.R0.S13: PI = 063, PtrOffset = 004
N6.C0.D0.R0.S02: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N0.C0.D0.R0.S00: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N2.C1.D0.R0.S07: Total Receive Enable Delay = 1368
N4.C0.D0.R0.S14: PI = 022, PtrOffset = 005
N6.C0.D0.R0.S03: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N0.C0.D0.R0.S01: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N2.C1.D0.R0.S08: Total Receive Enable Delay = 1286
N4.C0.D0.R0.S15: PI = 051, PtrOffset = 005
N6.C0.D0.R0.S04: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N0.C0.D0.R0.S02: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N2.C1.D0.R0: Starting preamble search upper nibbles
N4.C0.D0.R0.S16: PI = 010, PtrOffset = 004
N6.C0.D0.R0.S05: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N0.C0.D0.R0.S03: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N2.C1.D0.R0.S09: PI = 062, PtrOffset = 004
N4.C0.D0.R0.S17: PI = 055, PtrOffset = 004
N6.C0.D0.R0.S06: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N0.C0.D0.R0.S04: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N2.C1.D0.R0.S10: PI = 043, PtrOffset = 004
N4.C0.D0.R0.S09: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N6.C0.D0.R0.S07: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N0.C0.D0.R0.S05: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N2.C1.D0.R0.S11: PI = 014, PtrOffset = 004
N4.C0.D0.R0.S10: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N6.C0.D0.R0.S08: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N0.C0.D0.R0.S06: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N2.C1.D0.R0.S12: PI = 059, PtrOffset = 005
N4.C0.D0.R0.S11: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N6.C0.D0.R0.S00: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N0.C0.D0.R0.S07: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N2.C1.D0.R0.S13: PI = 049, PtrOffset = 005
N4.C0.D0.R0.S12: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N6.C0.D0.R0.S01: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N0.C0.D0.R0.S08: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N2.C1.D0.R0.S14: PI = 012, PtrOffset = 004
N4.C0.D0.R0.S13: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N6.C0.D0.R0.S02: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N0.C0.D0.R0.S00: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N2.C1.D0.R0.S15: PI = 038, PtrOffset = 004
N4.C0.D0.R0.S14: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N6.C0.D0.R0.S03: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N0.C0.D0.R0.S01: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N2.C1.D0.R0.S16: PI = 054, PtrOffset = 004
N4.C0.D0.R0.S15: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N6.C0.D0.R0.S04: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N0.C0.D0.R0.S02: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N2.C1.D0.R0.S17: PI = 039, PtrOffset = 005
N4.C0.D0.R0.S16: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N6.C0.D0.R0.S05: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N0.C0.D0.R0.S03: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N2.C1.D0.R0.S09: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N4.C0.D0.R0.S17: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N6.C0.D0.R0.S06: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N0.C0.D0.R0.S04: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N2.C1.D0.R0.S10: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N4.C0.D0.R0.S09: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N6.C0.D0.R0.S07: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N0.C0.D0.R0.S05: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N2.C1.D0.R0.S11: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N4.C0.D0.R0.S10: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N6.C0.D0.R0.S08: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N0.C0.D0.R0.S06: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N2.C1.D0.R0.S12: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N4.C0.D0.R0.S11: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N6.C0.D0.R0.S00: Preamble found at Latency = 008
N0.C0.D0.R0.S07: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N2.C1.D0.R0.S13: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N4.C0.D0.R0.S12: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N6.C0.D0.R0.S07: Preamble found at Latency = 008
N0.C0.D0.R0.S08: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N2.C1.D0.R0.S14: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N4.C0.D0.R0.S13: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N6.C0.D0.R0.S00: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N0.C0.D0.R0.S00: Preamble found at Latency = 008
N2.C1.D0.R0.S15: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N4.C0.D0.R0.S14: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N6.C0.D0.R0.S01: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N0.C0.D0.R0.S07: Preamble found at Latency = 008
N2.C1.D0.R0.S16: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N4.C0.D0.R0.S15: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N6.C0.D0.R0.S02: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N0.C0.D0.R0.S00: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N2.C1.D0.R0.S17: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N4.C0.D0.R0.S16: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N6.C0.D0.R0.S03: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N0.C0.D0.R0.S01: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N2.C1.D0.R0.S09: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N4.C0.D0.R0.S17: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N6.C0.D0.R0.S04: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N0.C0.D0.R0.S02: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N2.C1.D0.R0.S10: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N4.C0.D0.R0.S09: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N6.C0.D0.R0.S05: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N0.C0.D0.R0.S03: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N2.C1.D0.R0.S11: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N4.C0.D0.R0.S10: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N6.C0.D0.R0.S06: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N0.C0.D0.R0.S04: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N2.C1.D0.R0.S12: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N4.C0.D0.R0.S11: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N6.C0.D0.R0.S07: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N0.C0.D0.R0.S05: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N2.C1.D0.R0.S13: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N4.C0.D0.R0.S12: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N6.C0.D0.R0.S08: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N0.C0.D0.R0.S06: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N2.C1.D0.R0.S14: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N4.C0.D0.R0.S13: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N6.C0.D0.R0.S01: Preamble found at Latency = 007
N0.C0.D0.R0.S07: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N2.C1.D0.R0.S15: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N4.C0.D0.R0.S14: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N6.C0.D0.R0.S02: Preamble found at Latency = 007
N0.C0.D0.R0.S08: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N2.C1.D0.R0.S16: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N4.C0.D0.R0.S15: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N6.C0.D0.R0.S03: Preamble found at Latency = 007
N0.C0.D0.R0.S01: Preamble found at Latency = 007
N2.C1.D0.R0.S17: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N4.C0.D0.R0.S16: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N6.C0.D0.R0.S04: Preamble found at Latency = 007
N0.C0.D0.R0.S02: Preamble found at Latency = 007
N2.C1.D0.R0.S09: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N4.C0.D0.R0.S17: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N6.C0.D0.R0.S05: Preamble found at Latency = 007
N0.C0.D0.R0.S03: Preamble found at Latency = 007
N2.C1.D0.R0.S10: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N4.C0.D0.R0.S09: Preamble found at Latency = 008
N6.C0.D0.R0.S06: Preamble found at Latency = 007
N0.C0.D0.R0.S04: Preamble found at Latency = 007
N2.C1.D0.R0.S11: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N4.C0.D0.R0.S16: Preamble found at Latency = 008
N6.C0.D0.R0.S08: Preamble found at Latency = 007
N0.C0.D0.R0.S05: Preamble found at Latency = 007
N2.C1.D0.R0.S12: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N4.C0.D0.R0.S09: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N6.C0.D0.R0.S00: Total Receive Enable Delay = 1334
N0.C0.D0.R0.S06: Preamble found at Latency = 007
N2.C1.D0.R0.S13: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N4.C0.D0.R0.S10: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N6.C0.D0.R0.S01: Total Receive Enable Delay = 1311
N0.C0.D0.R0.S08: Preamble found at Latency = 007
N2.C1.D0.R0.S14: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N4.C0.D0.R0.S11: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N6.C0.D0.R0.S02: Total Receive Enable Delay = 1283
N0.C0.D0.R0.S00: Total Receive Enable Delay = 1320
N2.C1.D0.R0.S15: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N4.C0.D0.R0.S12: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N6.C0.D0.R0.S03: Total Receive Enable Delay = 1264
N0.C0.D0.R0.S01: Total Receive Enable Delay = 1303
N2.C1.D0.R0.S16: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N4.C0.D0.R0.S13: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N6.C0.D0.R0.S04: Total Receive Enable Delay = 1256
N0.C0.D0.R0.S02: Total Receive Enable Delay = 1275
N2.C1.D0.R0.S17: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N4.C0.D0.R0.S14: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N6.C0.D0.R0.S05: Total Receive Enable Delay = 1278
N0.C0.D0.R0.S03: Total Receive Enable Delay = 1257
N2.C1.D0.R0.S09: Preamble found at Latency = 008
N4.C0.D0.R0.S15: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N6.C0.D0.R0.S06: Total Receive Enable Delay = 1310
N0.C0.D0.R0.S04: Total Receive Enable Delay = 1248
N2.C1.D0.R0.S10: Preamble found at Latency = 008
N4.C0.D0.R0.S16: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N6.C0.D0.R0.S07: Total Receive Enable Delay = 1331
N0.C0.D0.R0.S05: Total Receive Enable Delay = 1269
N2.C1.D0.R0.S11: Preamble found at Latency = 008
N4.C0.D0.R0.S17: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N6.C0.D0.R0.S08: Total Receive Enable Delay = 1251
N0.C0.D0.R0.S06: Total Receive Enable Delay = 1305
N2.C1.D0.R0.S14: Preamble found at Latency = 008
N4.C0.D0.R0.S10: Preamble found at Latency = 007
N6.C0.D0.R0: Starting preamble search upper nibbles
N0.C0.D0.R0.S07: Total Receive Enable Delay = 1326
N2.C1.D0.R0.S15: Preamble found at Latency = 008
N4.C0.D0.R0.S11: Preamble found at Latency = 007
N6.C0.D0.R0.S09: PI = 019, PtrOffset = 004
N0.C0.D0.R0.S08: Total Receive Enable Delay = 1244
N2.C1.D0.R0.S16: Preamble found at Latency = 008
N4.C0.D0.R0.S12: Preamble found at Latency = 007
N6.C0.D0.R0.S10: PI = 062, PtrOffset = 005
N0.C0.D0.R0: Starting preamble search upper nibbles
N2.C1.D0.R0.S09: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N4.C0.D0.R0.S13: Preamble found at Latency = 007
N6.C0.D0.R0.S11: PI = 035, PtrOffset = 005
N0.C0.D0.R0.S09: PI = 011, PtrOffset = 004
N2.C1.D0.R0.S10: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N4.C0.D0.R0.S14: Preamble found at Latency = 007
N6.C0.D0.R0.S12: PI = 015, PtrOffset = 005
N0.C0.D0.R0.S10: PI = 053, PtrOffset = 005
N2.C1.D0.R0.S11: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N4.C0.D0.R0.S15: Preamble found at Latency = 007
N6.C0.D0.R0.S13: PI = 007, PtrOffset = 005
N0.C0.D0.R0.S11: PI = 024, PtrOffset = 005
N2.C1.D0.R0.S12: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N4.C0.D0.R0.S17: Preamble found at Latency = 007
N6.C0.D0.R0.S14: PI = 031, PtrOffset = 005
N0.C0.D0.R0.S12: PI = 007, PtrOffset = 005
N2.C1.D0.R0.S13: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N4.C0.D0.R0: Preamble found for all upper nibbles, adjusting Pi, Offset to center into preamble
N6.C0.D0.R0.S15: PI = 060, PtrOffset = 005
N0.C0.D0.R0.S13: PI = 001, PtrOffset = 005
N2.C1.D0.R0.S14: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N4.C0.D0.R0.S09: Total Receive Enable Delay = 1322
N6.C0.D0.R0.S16: PI = 020, PtrOffset = 004
N0.C0.D0.R0.S14: PI = 023, PtrOffset = 005
N2.C1.D0.R0.S15: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N4.C0.D0.R0.S10: Total Receive Enable Delay = 1304
N6.C0.D0.R0.S17: PI = 001, PtrOffset = 005
N0.C0.D0.R0.S15: PI = 054, PtrOffset = 005
N2.C1.D0.R0.S16: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N4.C0.D0.R0.S11: Total Receive Enable Delay = 1276
N6.C0.D0.R0.S09: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N0.C0.D0.R0.S16: PI = 014, PtrOffset = 004
N2.C1.D0.R0.S17: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N4.C0.D0.R0.S12: Total Receive Enable Delay = 1254
N6.C0.D0.R0.S10: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N0.C0.D0.R0.S17: PI = 058, PtrOffset = 004
N2.C1.D0.R0.S12: Preamble found at Latency = 007
N4.C0.D0.R0.S13: Total Receive Enable Delay = 1247
N6.C0.D0.R0.S11: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N0.C0.D0.R0.S09: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N2.C1.D0.R0.S13: Preamble found at Latency = 007
N4.C0.D0.R0.S14: Total Receive Enable Delay = 1270
N6.C0.D0.R0.S12: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N0.C0.D0.R0.S10: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N2.C1.D0.R0.S17: Preamble found at Latency = 007
N4.C0.D0.R0.S15: Total Receive Enable Delay = 1299
N6.C0.D0.R0.S13: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N0.C0.D0.R0.S11: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N2.C1.D0.R0: Preamble found for all upper nibbles, adjusting Pi, Offset to center into preamble
N4.C0.D0.R0.S16: Total Receive Enable Delay = 1322
N6.C0.D0.R0.S14: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N0.C0.D0.R0.S12: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N2.C1.D0.R0.S09: Total Receive Enable Delay = 1374
N4.C0.D0.R0.S17: Total Receive Enable Delay = 1239
N6.C0.D0.R0.S15: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N0.C0.D0.R0.S13: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N2.C1.D0.R0.S10: Total Receive Enable Delay = 1355
N4.C0.D0.R1: RcvEnFine: Initial RdCmd2RcvEnLatency = 10, Initial RdPtrOffsetRcvEn = 4
N6.C0.D0.R0.S16: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N0.C0.D0.R0.S14: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N2.C1.D0.R0.S11: Total Receive Enable Delay = 1326
N4.C0.D0.R1.S00: Rcv En Fine Value = 266
N6.C0.D0.R0.S17: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N0.C0.D0.R0.S15: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N2.C1.D0.R0.S12: Total Receive Enable Delay = 1307
N4.C0.D0.R1.S01: Rcv En Fine Value = 376
N6.C0.D0.R0.S09: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N0.C0.D0.R0.S16: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N2.C1.D0.R0.S13: Total Receive Enable Delay = 1297
N4.C0.D0.R1.S02: Rcv En Fine Value = 348
N6.C0.D0.R0.S10: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N0.C0.D0.R0.S17: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N2.C1.D0.R0.S14: Total Receive Enable Delay = 1324
N4.C0.D0.R1.S03: Rcv En Fine Value = 322
N6.C0.D0.R0.S11: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N0.C0.D0.R0.S09: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N2.C1.D0.R0.S15: Total Receive Enable Delay = 1350
N4.C0.D0.R1.S04: Rcv En Fine Value = 318
N6.C0.D0.R0.S12: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N0.C0.D0.R0.S10: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N2.C1.D0.R0.S16: Total Receive Enable Delay = 1366
N4.C0.D0.R1.S05: Rcv En Fine Value = 341
N6.C0.D0.R0.S13: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N0.C0.D0.R0.S11: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N2.C1.D0.R0.S17: Total Receive Enable Delay = 1287
N4.C0.D0.R1.S06: Rcv En Fine Value = 374
N6.C0.D0.R0.S14: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N0.C0.D0.R0.S12: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N2.C1.D0.R1: RcvEnFine: Initial RdCmd2RcvEnLatency = 10, Initial RdPtrOffsetRcvEn = 4
N4.C0.D0.R1.S07: Rcv En Fine Value = 269
N6.C0.D0.R0.S15: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N0.C0.D0.R0.S13: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N2.C1.D0.R1.S00: Rcv En Fine Value = 319
N4.C0.D0.R1.S08: Rcv En Fine Value = 315
N6.C0.D0.R0.S16: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N0.C0.D0.R0.S14: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N2.C1.D0.R1.S01: Rcv En Fine Value = 298
N4.C0.D0.R1.S09: Rcv En Fine Value = 266
N6.C0.D0.R0.S17: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N0.C0.D0.R0.S15: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N2.C1.D0.R1.S02: Rcv En Fine Value = 269
N4.C0.D0.R1.S10: Rcv En Fine Value = 377
N6.C0.D0.R0.S09: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N0.C0.D0.R0.S16: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N2.C1.D0.R1.S03: Rcv En Fine Value = 377
N4.C0.D0.R1.S11: Rcv En Fine Value = 347
N6.C0.D0.R0.S10: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N0.C0.D0.R0.S17: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N2.C1.D0.R1.S04: Rcv En Fine Value = 371
N4.C0.D0.R1.S12: Rcv En Fine Value = 324
N6.C0.D0.R0.S11: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N0.C0.D0.R0.S09: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N2.C1.D0.R1.S05: Rcv En Fine Value = 267
N4.C0.D0.R1.S13: Rcv En Fine Value = 317
N6.C0.D0.R0.S12: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N0.C0.D0.R0.S10: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N2.C1.D0.R1.S06: Rcv En Fine Value = 290
N4.C0.D0.R1.S14: Rcv En Fine Value = 337
N6.C0.D0.R0.S13: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N0.C0.D0.R0.S11: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N2.C1.D0.R1.S07: Rcv En Fine Value = 314
N4.C0.D0.R1.S15: Rcv En Fine Value = 372
N6.C0.D0.R0.S14: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N0.C0.D0.R0.S12: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N2.C1.D0.R1.S08: Rcv En Fine Value = 358
N4.C0.D0.R1.S16: Rcv En Fine Value = 267
N6.C0.D0.R0.S15: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N0.C0.D0.R0.S13: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N2.C1.D0.R1.S09: Rcv En Fine Value = 319
N4.C0.D0.R1.S17: Rcv En Fine Value = 311
N6.C0.D0.R0.S16: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N0.C0.D0.R0.S14: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N2.C1.D0.R1.S10: Rcv En Fine Value = 301
N4.C0.D0.R1: Starting preamble search lower nibbles
N6.C0.D0.R0.S17: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N0.C0.D0.R0.S15: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N2.C1.D0.R1.S11: Rcv En Fine Value = 268
N4.C0.D0.R1.S00: PI = 010, PtrOffset = 004
N6.C0.D0.R0.S09: Preamble found at Latency = 008
N0.C0.D0.R0.S16: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N2.C1.D0.R1.S12: Rcv En Fine Value = 378
N4.C0.D0.R1.S01: PI = 056, PtrOffset = 005
N6.C0.D0.R0.S16: Preamble found at Latency = 008
N0.C0.D0.R0.S17: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N2.C1.D0.R1.S13: Rcv En Fine Value = 371
N4.C0.D0.R1.S02: PI = 028, PtrOffset = 005
N6.C0.D0.R0.S09: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N0.C0.D0.R0.S09: Preamble found at Latency = 008
N2.C1.D0.R1.S14: Rcv En Fine Value = 267
N4.C0.D0.R1.S03: PI = 002, PtrOffset = 005
N6.C0.D0.R0.S10: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N0.C0.D0.R0.S16: Preamble found at Latency = 008
N2.C1.D0.R1.S15: Rcv En Fine Value = 293
N4.C0.D0.R1.S04: PI = 062, PtrOffset = 004
N6.C0.D0.R0.S11: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N0.C0.D0.R0.S09: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N2.C1.D0.R1.S16: Rcv En Fine Value = 315
N4.C0.D0.R1.S05: PI = 021, PtrOffset = 005
N6.C0.D0.R0.S12: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N0.C0.D0.R0.S10: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N2.C1.D0.R1.S17: Rcv En Fine Value = 360
N4.C0.D0.R1.S06: PI = 054, PtrOffset = 005
N6.C0.D0.R0.S13: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N0.C0.D0.R0.S11: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N2.C1.D0.R1: Starting preamble search lower nibbles
N4.C0.D0.R1.S07: PI = 013, PtrOffset = 004
N6.C0.D0.R0.S14: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N0.C0.D0.R0.S12: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N2.C1.D0.R1.S00: PI = 063, PtrOffset = 004
N4.C0.D0.R1.S08: PI = 059, PtrOffset = 004
N6.C0.D0.R0.S15: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N0.C0.D0.R0.S13: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N2.C1.D0.R1.S01: PI = 042, PtrOffset = 004
N4.C0.D0.R1.S00: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N6.C0.D0.R0.S16: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N0.C0.D0.R0.S14: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N2.C1.D0.R1.S02: PI = 013, PtrOffset = 004
N4.C0.D0.R1.S01: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N6.C0.D0.R0.S17: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N0.C0.D0.R0.S15: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N2.C1.D0.R1.S03: PI = 057, PtrOffset = 005
N4.C0.D0.R1.S02: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N6.C0.D0.R0.S10: Preamble found at Latency = 007
N0.C0.D0.R0.S16: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N2.C1.D0.R1.S04: PI = 051, PtrOffset = 005
N4.C0.D0.R1.S03: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N6.C0.D0.R0.S11: Preamble found at Latency = 007
N0.C0.D0.R0.S17: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N2.C1.D0.R1.S05: PI = 011, PtrOffset = 004
N4.C0.D0.R1.S04: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N6.C0.D0.R0.S12: Preamble found at Latency = 007
N0.C0.D0.R0.S10: Preamble found at Latency = 007
N2.C1.D0.R1.S06: PI = 034, PtrOffset = 004
N4.C0.D0.R1.S05: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N6.C0.D0.R0.S13: Preamble found at Latency = 007
N0.C0.D0.R0.S11: Preamble found at Latency = 007
N2.C1.D0.R1.S07: PI = 058, PtrOffset = 004
N4.C0.D0.R1.S06: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N6.C0.D0.R0.S14: Preamble found at Latency = 007
N0.C0.D0.R0.S12: Preamble found at Latency = 007
N2.C1.D0.R1.S08: PI = 038, PtrOffset = 005
N4.C0.D0.R1.S07: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N6.C0.D0.R0.S15: Preamble found at Latency = 007
N0.C0.D0.R0.S13: Preamble found at Latency = 007
N2.C1.D0.R1.S00: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N4.C0.D0.R1.S08: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N6.C0.D0.R0.S17: Preamble found at Latency = 007
N0.C0.D0.R0.S14: Preamble found at Latency = 007
N2.C1.D0.R1.S01: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N4.C0.D0.R1.S00: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N6.C0.D0.R0: Preamble found for all upper nibbles, adjusting Pi, Offset to center into preamble
N0.C0.D0.R0.S15: Preamble found at Latency = 007
N2.C1.D0.R1.S02: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N4.C0.D0.R1.S01: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N6.C0.D0.R0.S09: Total Receive Enable Delay = 1331
N0.C0.D0.R0.S17: Preamble found at Latency = 007
N2.C1.D0.R1.S03: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N4.C0.D0.R1.S02: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N6.C0.D0.R0.S10: Total Receive Enable Delay = 1310
N0.C0.D0.R0: Preamble found for all upper nibbles, adjusting Pi, Offset to center into preamble
N2.C1.D0.R1.S04: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N4.C0.D0.R1.S03: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N6.C0.D0.R0.S11: Total Receive Enable Delay = 1283
N0.C0.D0.R0.S09: Total Receive Enable Delay = 1323
N2.C1.D0.R1.S05: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N4.C0.D0.R1.S04: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N6.C0.D0.R0.S12: Total Receive Enable Delay = 1263
N0.C0.D0.R0.S10: Total Receive Enable Delay = 1301
N2.C1.D0.R1.S06: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N4.C0.D0.R1.S05: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N6.C0.D0.R0.S13: Total Receive Enable Delay = 1255
N0.C0.D0.R0.S11: Total Receive Enable Delay = 1272
N2.C1.D0.R1.S07: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N4.C0.D0.R1.S06: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N6.C0.D0.R0.S14: Total Receive Enable Delay = 1279
N0.C0.D0.R0.S12: Total Receive Enable Delay = 1255
N2.C1.D0.R1.S08: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N4.C0.D0.R1.S07: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N6.C0.D0.R0.S15: Total Receive Enable Delay = 1308
N0.C0.D0.R0.S13: Total Receive Enable Delay = 1249
N2.C1.D0.R1.S00: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N4.C0.D0.R1.S08: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N6.C0.D0.R0.S16: Total Receive Enable Delay = 1332
N0.C0.D0.R0.S14: Total Receive Enable Delay = 1271
N2.C1.D0.R1.S01: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N4.C0.D0.R1.S00: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N6.C0.D0.R0.S17: Total Receive Enable Delay = 1249
N0.C0.D0.R0.S15: Total Receive Enable Delay = 1302
N2.C1.D0.R1.S02: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N4.C0.D0.R1.S01: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N6.C0.D0.R1: RcvEnFine: Initial RdCmd2RcvEnLatency = 10, Initial RdPtrOffsetRcvEn = 4
N0.C0.D0.R0.S16: Total Receive Enable Delay = 1326
N2.C1.D0.R1.S03: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N4.C0.D0.R1.S02: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N6.C0.D0.R1.S00: Rcv En Fine Value = 277
N0.C0.D0.R0.S17: Total Receive Enable Delay = 1242
N2.C1.D0.R1.S04: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N4.C0.D0.R1.S03: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N6.C0.D0.R1.S01: Rcv En Fine Value = 256
N0.C0.D0.R1: RcvEnFine: Initial RdCmd2RcvEnLatency = 10, Initial RdPtrOffsetRcvEn = 4
N2.C1.D0.R1.S05: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N4.C0.D0.R1.S04: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N6.C0.D0.R1.S02: Rcv En Fine Value = 354
N0.C0.D0.R1.S00: Rcv En Fine Value = 269
N2.C1.D0.R1.S06: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N4.C0.D0.R1.S05: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N6.C0.D0.R1.S03: Rcv En Fine Value = 335
N0.C0.D0.R1.S01: Rcv En Fine Value = 376
N2.C1.D0.R1.S07: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N4.C0.D0.R1.S06: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N6.C0.D0.R1.S04: Rcv En Fine Value = 328
N0.C0.D0.R1.S02: Rcv En Fine Value = 346
N2.C1.D0.R1.S08: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N4.C0.D0.R1.S07: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N6.C0.D0.R1.S05: Rcv En Fine Value = 349
N0.C0.D0.R1.S03: Rcv En Fine Value = 329
N2.C1.D0.R1.S00: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N4.C0.D0.R1.S08: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N6.C0.D0.R1.S06: Rcv En Fine Value = 383
N0.C0.D0.R1.S04: Rcv En Fine Value = 319
N2.C1.D0.R1.S01: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N4.C0.D0.R1.S00: Preamble found at Latency = 008
N6.C0.D0.R1.S07: Rcv En Fine Value = 276
N0.C0.D0.R1.S05: Rcv En Fine Value = 341
N2.C1.D0.R1.S02: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N4.C0.D0.R1.S07: Preamble found at Latency = 008
N6.C0.D0.R1.S08: Rcv En Fine Value = 323
N0.C0.D0.R1.S06: Rcv En Fine Value = 378
N2.C1.D0.R1.S03: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N4.C0.D0.R1.S00: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N6.C0.D0.R1.S09: Rcv En Fine Value = 272
N0.C0.D0.R1.S07: Rcv En Fine Value = 269
N2.C1.D0.R1.S04: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N4.C0.D0.R1.S01: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N6.C0.D0.R1.S10: Rcv En Fine Value = 258
N0.C0.D0.R1.S08: Rcv En Fine Value = 314
N2.C1.D0.R1.S05: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N4.C0.D0.R1.S02: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N6.C0.D0.R1.S11: Rcv En Fine Value = 354
N0.C0.D0.R1.S09: Rcv En Fine Value = 264
N2.C1.D0.R1.S06: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N4.C0.D0.R1.S03: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N6.C0.D0.R1.S12: Rcv En Fine Value = 334
N0.C0.D0.R1.S10: Rcv En Fine Value = 375
N2.C1.D0.R1.S07: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N4.C0.D0.R1.S04: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N6.C0.D0.R1.S13: Rcv En Fine Value = 326
N0.C0.D0.R1.S11: Rcv En Fine Value = 348
N2.C1.D0.R1.S08: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N4.C0.D0.R1.S05: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N6.C0.D0.R1.S14: Rcv En Fine Value = 349
N0.C0.D0.R1.S12: Rcv En Fine Value = 327
N2.C1.D0.R1.S00: Preamble found at Latency = 008
N4.C0.D0.R1.S06: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N6.C0.D0.R1.S15: Rcv En Fine Value = 382
N0.C0.D0.R1.S13: Rcv En Fine Value = 316
N2.C1.D0.R1.S01: Preamble found at Latency = 008
N4.C0.D0.R1.S07: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N6.C0.D0.R1.S16: Rcv En Fine Value = 275
N0.C0.D0.R1.S14: Rcv En Fine Value = 340
N2.C1.D0.R1.S02: Preamble found at Latency = 008
N4.C0.D0.R1.S08: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N6.C0.D0.R1.S17: Rcv En Fine Value = 321
N0.C0.D0.R1.S15: Rcv En Fine Value = 377
N2.C1.D0.R1.S05: Preamble found at Latency = 008
N4.C0.D0.R1.S01: Preamble found at Latency = 007
N6.C0.D0.R1: Starting preamble search lower nibbles
N0.C0.D0.R1.S16: Rcv En Fine Value = 269
N2.C1.D0.R1.S06: Preamble found at Latency = 008
N4.C0.D0.R1.S02: Preamble found at Latency = 007
N6.C0.D0.R1.S00: PI = 021, PtrOffset = 004
N0.C0.D0.R1.S17: Rcv En Fine Value = 312
N2.C1.D0.R1.S07: Preamble found at Latency = 008
N4.C0.D0.R1.S03: Preamble found at Latency = 007
N6.C0.D0.R1.S01: PI = 000, PtrOffset = 004
N0.C0.D0.R1: Starting preamble search lower nibbles
N2.C1.D0.R1.S00: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N4.C0.D0.R1.S04: Preamble found at Latency = 007
N6.C0.D0.R1.S02: PI = 034, PtrOffset = 005
N0.C0.D0.R1.S00: PI = 013, PtrOffset = 004
N2.C1.D0.R1.S01: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N4.C0.D0.R1.S05: Preamble found at Latency = 007
N6.C0.D0.R1.S03: PI = 015, PtrOffset = 005
N0.C0.D0.R1.S01: PI = 056, PtrOffset = 005
N2.C1.D0.R1.S02: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N4.C0.D0.R1.S06: Preamble found at Latency = 007
N6.C0.D0.R1.S04: PI = 008, PtrOffset = 005
N0.C0.D0.R1.S02: PI = 026, PtrOffset = 005
N2.C1.D0.R1.S03: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N4.C0.D0.R1.S08: Preamble found at Latency = 007
N6.C0.D0.R1.S05: PI = 029, PtrOffset = 005
N0.C0.D0.R1.S03: PI = 009, PtrOffset = 005
N2.C1.D0.R1.S04: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N4.C0.D0.R1.S00: Total Receive Enable Delay = 1322
N6.C0.D0.R1.S06: PI = 063, PtrOffset = 005
N0.C0.D0.R1.S04: PI = 063, PtrOffset = 004
N2.C1.D0.R1.S05: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N4.C0.D0.R1.S01: Total Receive Enable Delay = 1304
N6.C0.D0.R1.S07: PI = 020, PtrOffset = 004
N0.C0.D0.R1.S05: PI = 021, PtrOffset = 005
N2.C1.D0.R1.S06: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N4.C0.D0.R1.S02: Total Receive Enable Delay = 1276
N6.C0.D0.R1.S08: PI = 003, PtrOffset = 005
N0.C0.D0.R1.S06: PI = 058, PtrOffset = 005
N2.C1.D0.R1.S07: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N4.C0.D0.R1.S03: Total Receive Enable Delay = 1250
N6.C0.D0.R1.S00: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N0.C0.D0.R1.S07: PI = 013, PtrOffset = 004
N2.C1.D0.R1.S08: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N4.C0.D0.R1.S04: Total Receive Enable Delay = 1246
N6.C0.D0.R1.S01: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N0.C0.D0.R1.S08: PI = 058, PtrOffset = 004
N2.C1.D0.R1.S03: Preamble found at Latency = 007
N4.C0.D0.R1.S05: Total Receive Enable Delay = 1269
N6.C0.D0.R1.S02: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N0.C0.D0.R1.S00: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N2.C1.D0.R1.S04: Preamble found at Latency = 007
N4.C0.D0.R1.S06: Total Receive Enable Delay = 1302
N6.C0.D0.R1.S03: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N0.C0.D0.R1.S01: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N2.C1.D0.R1.S08: Preamble found at Latency = 007
N4.C0.D0.R1.S07: Total Receive Enable Delay = 1325
N6.C0.D0.R1.S04: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N0.C0.D0.R1.S02: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N2.C1.D0.R1.S00: Total Receive Enable Delay = 1375
N4.C0.D0.R1.S08: Total Receive Enable Delay = 1243
N6.C0.D0.R1.S05: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N0.C0.D0.R1.S03: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N2.C1.D0.R1.S01: Total Receive Enable Delay = 1354
N4.C0.D0.R1: Starting preamble search upper nibbles
N6.C0.D0.R1.S06: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N0.C0.D0.R1.S04: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N2.C1.D0.R1.S02: Total Receive Enable Delay = 1325
N4.C0.D0.R1.S09: PI = 010, PtrOffset = 004
N6.C0.D0.R1.S07: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N0.C0.D0.R1.S05: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N2.C1.D0.R1.S03: Total Receive Enable Delay = 1305
N4.C0.D0.R1.S10: PI = 057, PtrOffset = 005
N6.C0.D0.R1.S08: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N0.C0.D0.R1.S06: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N2.C1.D0.R1.S04: Total Receive Enable Delay = 1299
N4.C0.D0.R1.S11: PI = 027, PtrOffset = 005
N6.C0.D0.R1.S00: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N0.C0.D0.R1.S07: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N2.C1.D0.R1.S05: Total Receive Enable Delay = 1323
N4.C0.D0.R1.S12: PI = 004, PtrOffset = 005
N6.C0.D0.R1.S01: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N0.C0.D0.R1.S08: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N2.C1.D0.R1.S06: Total Receive Enable Delay = 1346
N4.C0.D0.R1.S13: PI = 061, PtrOffset = 004
N6.C0.D0.R1.S02: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N0.C0.D0.R1.S00: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N2.C1.D0.R1.S07: Total Receive Enable Delay = 1370
N4.C0.D0.R1.S14: PI = 017, PtrOffset = 005
N6.C0.D0.R1.S03: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N0.C0.D0.R1.S01: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N2.C1.D0.R1.S08: Total Receive Enable Delay = 1286
N4.C0.D0.R1.S15: PI = 052, PtrOffset = 005
N6.C0.D0.R1.S04: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N0.C0.D0.R1.S02: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N2.C1.D0.R1: Starting preamble search upper nibbles
N4.C0.D0.R1.S16: PI = 011, PtrOffset = 004
N6.C0.D0.R1.S05: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N0.C0.D0.R1.S03: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N2.C1.D0.R1.S09: PI = 063, PtrOffset = 004
N4.C0.D0.R1.S17: PI = 055, PtrOffset = 004
N6.C0.D0.R1.S06: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N0.C0.D0.R1.S04: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N2.C1.D0.R1.S10: PI = 045, PtrOffset = 004
N4.C0.D0.R1.S09: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N6.C0.D0.R1.S07: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N0.C0.D0.R1.S05: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N2.C1.D0.R1.S11: PI = 012, PtrOffset = 004
N4.C0.D0.R1.S10: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N6.C0.D0.R1.S08: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N0.C0.D0.R1.S06: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N2.C1.D0.R1.S12: PI = 058, PtrOffset = 005
N4.C0.D0.R1.S11: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N6.C0.D0.R1.S00: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N0.C0.D0.R1.S07: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N2.C1.D0.R1.S13: PI = 051, PtrOffset = 005
N4.C0.D0.R1.S12: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N6.C0.D0.R1.S01: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N0.C0.D0.R1.S08: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N2.C1.D0.R1.S14: PI = 011, PtrOffset = 004
N4.C0.D0.R1.S13: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N6.C0.D0.R1.S02: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N0.C0.D0.R1.S00: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N2.C1.D0.R1.S15: PI = 037, PtrOffset = 004
N4.C0.D0.R1.S14: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N6.C0.D0.R1.S03: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N0.C0.D0.R1.S01: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N2.C1.D0.R1.S16: PI = 059, PtrOffset = 004
N4.C0.D0.R1.S15: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N6.C0.D0.R1.S04: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N0.C0.D0.R1.S02: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N2.C1.D0.R1.S17: PI = 040, PtrOffset = 005
N4.C0.D0.R1.S16: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N6.C0.D0.R1.S05: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N0.C0.D0.R1.S03: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N2.C1.D0.R1.S09: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N4.C0.D0.R1.S17: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N6.C0.D0.R1.S06: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N0.C0.D0.R1.S04: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N2.C1.D0.R1.S10: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N4.C0.D0.R1.S09: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N6.C0.D0.R1.S07: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N0.C0.D0.R1.S05: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N2.C1.D0.R1.S11: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N4.C0.D0.R1.S10: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N6.C0.D0.R1.S08: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N0.C0.D0.R1.S06: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N2.C1.D0.R1.S12: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N4.C0.D0.R1.S11: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N6.C0.D0.R1.S00: Preamble found at Latency = 008
N0.C0.D0.R1.S07: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N2.C1.D0.R1.S13: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N4.C0.D0.R1.S12: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N6.C0.D0.R1.S01: Preamble found at Latency = 008
N0.C0.D0.R1.S08: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N2.C1.D0.R1.S14: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N4.C0.D0.R1.S13: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N6.C0.D0.R1.S07: Preamble found at Latency = 008
N0.C0.D0.R1.S00: Preamble found at Latency = 008
N2.C1.D0.R1.S15: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N4.C0.D0.R1.S14: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N6.C0.D0.R1.S00: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N0.C0.D0.R1.S07: Preamble found at Latency = 008
N2.C1.D0.R1.S16: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N4.C0.D0.R1.S15: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N6.C0.D0.R1.S01: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N0.C0.D0.R1.S00: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N2.C1.D0.R1.S17: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N4.C0.D0.R1.S16: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N6.C0.D0.R1.S02: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N0.C0.D0.R1.S01: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N2.C1.D0.R1.S09: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N4.C0.D0.R1.S17: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N6.C0.D0.R1.S03: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N0.C0.D0.R1.S02: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N2.C1.D0.R1.S10: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N4.C0.D0.R1.S09: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N6.C0.D0.R1.S04: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N0.C0.D0.R1.S03: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N2.C1.D0.R1.S11: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N4.C0.D0.R1.S10: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N6.C0.D0.R1.S05: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N0.C0.D0.R1.S04: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N2.C1.D0.R1.S12: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N4.C0.D0.R1.S11: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N6.C0.D0.R1.S06: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N0.C0.D0.R1.S05: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N2.C1.D0.R1.S13: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N4.C0.D0.R1.S12: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N6.C0.D0.R1.S07: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N0.C0.D0.R1.S06: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N2.C1.D0.R1.S14: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N4.C0.D0.R1.S13: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N6.C0.D0.R1.S08: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N0.C0.D0.R1.S07: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N2.C1.D0.R1.S15: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N4.C0.D0.R1.S14: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N6.C0.D0.R1.S02: Preamble found at Latency = 007
N0.C0.D0.R1.S08: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N2.C1.D0.R1.S16: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N4.C0.D0.R1.S15: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N6.C0.D0.R1.S03: Preamble found at Latency = 007
N0.C0.D0.R1.S01: Preamble found at Latency = 007
N2.C1.D0.R1.S17: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N4.C0.D0.R1.S16: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N6.C0.D0.R1.S04: Preamble found at Latency = 007
N0.C0.D0.R1.S02: Preamble found at Latency = 007
N2.C1.D0.R1.S09: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N4.C0.D0.R1.S17: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N6.C0.D0.R1.S05: Preamble found at Latency = 007
N0.C0.D0.R1.S03: Preamble found at Latency = 007
N2.C1.D0.R1.S10: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N4.C0.D0.R1.S09: Preamble found at Latency = 008
N6.C0.D0.R1.S06: Preamble found at Latency = 007
N0.C0.D0.R1.S04: Preamble found at Latency = 007
N2.C1.D0.R1.S11: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N4.C0.D0.R1.S16: Preamble found at Latency = 008
N6.C0.D0.R1.S08: Preamble found at Latency = 007
N0.C0.D0.R1.S05: Preamble found at Latency = 007
N2.C1.D0.R1.S12: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N4.C0.D0.R1.S09: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N6.C0.D0.R1.S00: Total Receive Enable Delay = 1333
N0.C0.D0.R1.S06: Preamble found at Latency = 007
N2.C1.D0.R1.S13: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N4.C0.D0.R1.S10: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N6.C0.D0.R1.S01: Total Receive Enable Delay = 1312
N0.C0.D0.R1.S08: Preamble found at Latency = 007
N2.C1.D0.R1.S14: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N4.C0.D0.R1.S11: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N6.C0.D0.R1.S02: Total Receive Enable Delay = 1282
N0.C0.D0.R1.S00: Total Receive Enable Delay = 1325
N2.C1.D0.R1.S15: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N4.C0.D0.R1.S12: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N6.C0.D0.R1.S03: Total Receive Enable Delay = 1263
N0.C0.D0.R1.S01: Total Receive Enable Delay = 1304
N2.C1.D0.R1.S16: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N4.C0.D0.R1.S13: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N6.C0.D0.R1.S04: Total Receive Enable Delay = 1256
N0.C0.D0.R1.S02: Total Receive Enable Delay = 1274
N2.C1.D0.R1.S17: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N4.C0.D0.R1.S14: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N6.C0.D0.R1.S05: Total Receive Enable Delay = 1277
N0.C0.D0.R1.S03: Total Receive Enable Delay = 1257
N2.C1.D0.R1.S09: Preamble found at Latency = 008
N4.C0.D0.R1.S15: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N6.C0.D0.R1.S06: Total Receive Enable Delay = 1311
N0.C0.D0.R1.S04: Total Receive Enable Delay = 1247
N2.C1.D0.R1.S10: Preamble found at Latency = 008
N4.C0.D0.R1.S16: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N6.C0.D0.R1.S07: Total Receive Enable Delay = 1332
N0.C0.D0.R1.S05: Total Receive Enable Delay = 1269
N2.C1.D0.R1.S11: Preamble found at Latency = 008
N4.C0.D0.R1.S17: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N6.C0.D0.R1.S08: Total Receive Enable Delay = 1251
N0.C0.D0.R1.S06: Total Receive Enable Delay = 1306
N2.C1.D0.R1.S14: Preamble found at Latency = 008
N4.C0.D0.R1.S10: Preamble found at Latency = 007
N6.C0.D0.R1: Starting preamble search upper nibbles
N0.C0.D0.R1.S07: Total Receive Enable Delay = 1325
N2.C1.D0.R1.S15: Preamble found at Latency = 008
N4.C0.D0.R1.S11: Preamble found at Latency = 007
N6.C0.D0.R1.S09: PI = 016, PtrOffset = 004
N0.C0.D0.R1.S08: Total Receive Enable Delay = 1242
N2.C1.D0.R1.S16: Preamble found at Latency = 008
N4.C0.D0.R1.S12: Preamble found at Latency = 007
N6.C0.D0.R1.S10: PI = 002, PtrOffset = 004
N0.C0.D0.R1: Starting preamble search upper nibbles
N2.C1.D0.R1.S09: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N4.C0.D0.R1.S13: Preamble found at Latency = 007
N6.C0.D0.R1.S11: PI = 034, PtrOffset = 005
N0.C0.D0.R1.S09: PI = 008, PtrOffset = 004
N2.C1.D0.R1.S10: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N4.C0.D0.R1.S14: Preamble found at Latency = 007
N6.C0.D0.R1.S12: PI = 014, PtrOffset = 005
N0.C0.D0.R1.S10: PI = 055, PtrOffset = 005
N2.C1.D0.R1.S11: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N4.C0.D0.R1.S15: Preamble found at Latency = 007
N6.C0.D0.R1.S13: PI = 006, PtrOffset = 005
N0.C0.D0.R1.S11: PI = 028, PtrOffset = 005
N2.C1.D0.R1.S12: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N4.C0.D0.R1.S17: Preamble found at Latency = 007
N6.C0.D0.R1.S14: PI = 029, PtrOffset = 005
N0.C0.D0.R1.S12: PI = 007, PtrOffset = 005
N2.C1.D0.R1.S13: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N4.C0.D0.R1: Preamble found for all upper nibbles, adjusting Pi, Offset to center into preamble
N6.C0.D0.R1.S15: PI = 062, PtrOffset = 005
N0.C0.D0.R1.S13: PI = 060, PtrOffset = 004
N2.C1.D0.R1.S14: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N4.C0.D0.R1.S09: Total Receive Enable Delay = 1322
N6.C0.D0.R1.S16: PI = 019, PtrOffset = 004
N0.C0.D0.R1.S14: PI = 020, PtrOffset = 005
N2.C1.D0.R1.S15: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N4.C0.D0.R1.S10: Total Receive Enable Delay = 1305
N6.C0.D0.R1.S17: PI = 001, PtrOffset = 005
N0.C0.D0.R1.S15: PI = 057, PtrOffset = 005
N2.C1.D0.R1.S16: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N4.C0.D0.R1.S11: Total Receive Enable Delay = 1275
N6.C0.D0.R1.S09: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N0.C0.D0.R1.S16: PI = 013, PtrOffset = 004
N2.C1.D0.R1.S17: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N4.C0.D0.R1.S12: Total Receive Enable Delay = 1252
N6.C0.D0.R1.S10: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N0.C0.D0.R1.S17: PI = 056, PtrOffset = 004
N2.C1.D0.R1.S12: Preamble found at Latency = 007
N4.C0.D0.R1.S13: Total Receive Enable Delay = 1245
N6.C0.D0.R1.S11: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N0.C0.D0.R1.S09: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N2.C1.D0.R1.S13: Preamble found at Latency = 007
N4.C0.D0.R1.S14: Total Receive Enable Delay = 1265
N6.C0.D0.R1.S12: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N0.C0.D0.R1.S10: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N2.C1.D0.R1.S17: Preamble found at Latency = 007
N4.C0.D0.R1.S15: Total Receive Enable Delay = 1300
N6.C0.D0.R1.S13: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N0.C0.D0.R1.S11: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N2.C1.D0.R1: Preamble found for all upper nibbles, adjusting Pi, Offset to center into preamble
N4.C0.D0.R1.S16: Total Receive Enable Delay = 1323
N6.C0.D0.R1.S14: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N0.C0.D0.R1.S12: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N2.C1.D0.R1.S09: Total Receive Enable Delay = 1375
N4.C0.D0.R1.S17: Total Receive Enable Delay = 1239
N6.C0.D0.R1.S15: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N0.C0.D0.R1.S13: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N2.C1.D0.R1.S10: Total Receive Enable Delay = 1357
N4.C0.D1.R0: RcvEnFine: Initial RdCmd2RcvEnLatency = 10, Initial RdPtrOffsetRcvEn = 4
N6.C0.D0.R1.S16: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N0.C0.D0.R1.S14: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N2.C1.D0.R1.S11: Total Receive Enable Delay = 1324
N4.C0.D1.R0.S00: Rcv En Fine Value = 379
N6.C0.D0.R1.S17: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N0.C0.D0.R1.S15: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N2.C1.D0.R1.S12: Total Receive Enable Delay = 1306
N4.C0.D1.R0.S01: Rcv En Fine Value = 358
N6.C0.D0.R1.S09: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N0.C0.D0.R1.S16: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N2.C1.D0.R1.S13: Total Receive Enable Delay = 1299
N4.C0.D1.R0.S02: Rcv En Fine Value = 330
N6.C0.D0.R1.S10: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N0.C0.D0.R1.S17: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N2.C1.D0.R1.S14: Total Receive Enable Delay = 1323
N4.C0.D1.R0.S03: Rcv En Fine Value = 308
N6.C0.D0.R1.S11: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N0.C0.D0.R1.S09: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N2.C1.D0.R1.S15: Total Receive Enable Delay = 1349
N4.C0.D1.R0.S04: Rcv En Fine Value = 304
N6.C0.D0.R1.S12: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N0.C0.D0.R1.S10: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N2.C1.D0.R1.S16: Total Receive Enable Delay = 1371
N4.C0.D1.R0.S05: Rcv En Fine Value = 329
N6.C0.D0.R1.S13: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N0.C0.D0.R1.S11: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N2.C1.D0.R1.S17: Total Receive Enable Delay = 1288
N4.C0.D1.R0.S06: Rcv En Fine Value = 359
N6.C0.D0.R1.S14: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N0.C0.D0.R1.S12: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N2.C1.D1.R0: RcvEnFine: Initial RdCmd2RcvEnLatency = 10, Initial RdPtrOffsetRcvEn = 4
N4.C0.D1.R0.S07: Rcv En Fine Value = 381
N6.C0.D0.R1.S15: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N0.C0.D0.R1.S13: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N2.C1.D1.R0.S00: Rcv En Fine Value = 302
N4.C0.D1.R0.S08: Rcv En Fine Value = 298
N6.C0.D0.R1.S16: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N0.C0.D0.R1.S14: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N2.C1.D1.R0.S01: Rcv En Fine Value = 285
N4.C0.D1.R0.S09: Rcv En Fine Value = 379
N6.C0.D0.R1.S17: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N0.C0.D0.R1.S15: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N2.C1.D1.R0.S02: Rcv En Fine Value = 256
N4.C0.D1.R0.S10: Rcv En Fine Value = 360
N6.C0.D0.R1.S09: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N0.C0.D0.R1.S16: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N2.C1.D1.R0.S03: Rcv En Fine Value = 362
N4.C0.D1.R0.S11: Rcv En Fine Value = 331
N6.C0.D0.R1.S10: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N0.C0.D0.R1.S17: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N2.C1.D1.R0.S04: Rcv En Fine Value = 356
N4.C0.D1.R0.S12: Rcv En Fine Value = 307
N6.C0.D0.R1.S11: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N0.C0.D0.R1.S09: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N2.C1.D1.R0.S05: Rcv En Fine Value = 382
N4.C0.D1.R0.S13: Rcv En Fine Value = 304
N6.C0.D0.R1.S12: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N0.C0.D0.R1.S10: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N2.C1.D1.R0.S06: Rcv En Fine Value = 276
N4.C0.D1.R0.S14: Rcv En Fine Value = 325
N6.C0.D0.R1.S13: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N0.C0.D0.R1.S11: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N2.C1.D1.R0.S07: Rcv En Fine Value = 297
N4.C0.D1.R0.S15: Rcv En Fine Value = 356
N6.C0.D0.R1.S14: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N0.C0.D0.R1.S12: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N2.C1.D1.R0.S08: Rcv En Fine Value = 343
N4.C0.D1.R0.S16: Rcv En Fine Value = 379
N6.C0.D0.R1.S15: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N0.C0.D0.R1.S13: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N2.C1.D1.R0.S09: Rcv En Fine Value = 304
N4.C0.D1.R0.S17: Rcv En Fine Value = 296
N6.C0.D0.R1.S16: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N0.C0.D0.R1.S14: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N2.C1.D1.R0.S10: Rcv En Fine Value = 286
N4.C0.D1.R0: Starting preamble search lower nibbles
N6.C0.D0.R1.S17: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N0.C0.D0.R1.S15: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N2.C1.D1.R0.S11: Rcv En Fine Value = 383
N4.C0.D1.R0.S00: PI = 059, PtrOffset = 005
N6.C0.D0.R1.S09: Preamble found at Latency = 008
N0.C0.D0.R1.S16: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N2.C1.D1.R0.S12: Rcv En Fine Value = 364
N4.C0.D1.R0.S01: PI = 038, PtrOffset = 005
N6.C0.D0.R1.S10: Preamble found at Latency = 008
N0.C0.D0.R1.S17: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N2.C1.D1.R0.S13: Rcv En Fine Value = 356
N4.C0.D1.R0.S02: PI = 010, PtrOffset = 005
N6.C0.D0.R1.S16: Preamble found at Latency = 008
N0.C0.D0.R1.S09: Preamble found at Latency = 008
N2.C1.D1.R0.S14: Rcv En Fine Value = 381
N4.C0.D1.R0.S03: PI = 052, PtrOffset = 004
N6.C0.D0.R1.S09: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N0.C0.D0.R1.S16: Preamble found at Latency = 008
N2.C1.D1.R0.S15: Rcv En Fine Value = 278
N4.C0.D1.R0.S04: PI = 048, PtrOffset = 004
N6.C0.D0.R1.S10: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N0.C0.D0.R1.S09: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N2.C1.D1.R0.S16: Rcv En Fine Value = 299
N4.C0.D1.R0.S05: PI = 009, PtrOffset = 005
N6.C0.D0.R1.S11: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N0.C0.D0.R1.S10: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N2.C1.D1.R0.S17: Rcv En Fine Value = 345
N4.C0.D1.R0.S06: PI = 039, PtrOffset = 005
N6.C0.D0.R1.S12: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N0.C0.D0.R1.S11: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N2.C1.D1.R0: Starting preamble search lower nibbles
N4.C0.D1.R0.S07: PI = 061, PtrOffset = 005
N6.C0.D0.R1.S13: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N0.C0.D0.R1.S12: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N2.C1.D1.R0.S00: PI = 046, PtrOffset = 004
N4.C0.D1.R0.S08: PI = 042, PtrOffset = 004
N6.C0.D0.R1.S14: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N0.C0.D0.R1.S13: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N2.C1.D1.R0.S01: PI = 029, PtrOffset = 004
N4.C0.D1.R0.S00: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N6.C0.D0.R1.S15: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N0.C0.D0.R1.S14: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N2.C1.D1.R0.S02: PI = 000, PtrOffset = 004
N4.C0.D1.R0.S01: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N6.C0.D0.R1.S16: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N0.C0.D0.R1.S15: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N2.C1.D1.R0.S03: PI = 042, PtrOffset = 005
N4.C0.D1.R0.S02: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N6.C0.D0.R1.S17: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N0.C0.D0.R1.S16: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N2.C1.D1.R0.S04: PI = 036, PtrOffset = 005
N4.C0.D1.R0.S03: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N6.C0.D0.R1.S11: Preamble found at Latency = 007
N0.C0.D0.R1.S17: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N2.C1.D1.R0.S05: PI = 062, PtrOffset = 005
N4.C0.D1.R0.S04: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N6.C0.D0.R1.S12: Preamble found at Latency = 007
N0.C0.D0.R1.S10: Preamble found at Latency = 007
N2.C1.D1.R0.S06: PI = 020, PtrOffset = 004
N4.C0.D1.R0.S05: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N6.C0.D0.R1.S13: Preamble found at Latency = 007
N0.C0.D0.R1.S11: Preamble found at Latency = 007
N2.C1.D1.R0.S07: PI = 041, PtrOffset = 004
N4.C0.D1.R0.S06: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N6.C0.D0.R1.S14: Preamble found at Latency = 007
N0.C0.D0.R1.S12: Preamble found at Latency = 007
N2.C1.D1.R0.S08: PI = 023, PtrOffset = 005
N4.C0.D1.R0.S07: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N6.C0.D0.R1.S15: Preamble found at Latency = 007
N0.C0.D0.R1.S13: Preamble found at Latency = 007
N2.C1.D1.R0.S00: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N4.C0.D1.R0.S08: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N6.C0.D0.R1.S17: Preamble found at Latency = 007
N0.C0.D0.R1.S14: Preamble found at Latency = 007
N2.C1.D1.R0.S01: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N4.C0.D1.R0.S00: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N6.C0.D0.R1: Preamble found for all upper nibbles, adjusting Pi, Offset to center into preamble
N0.C0.D0.R1.S15: Preamble found at Latency = 007
N2.C1.D1.R0.S02: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N4.C0.D1.R0.S01: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N6.C0.D0.R1.S09: Total Receive Enable Delay = 1328
N0.C0.D0.R1.S17: Preamble found at Latency = 007
N2.C1.D1.R0.S03: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N4.C0.D1.R0.S02: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N6.C0.D0.R1.S10: Total Receive Enable Delay = 1314
N0.C0.D0.R1: Preamble found for all upper nibbles, adjusting Pi, Offset to center into preamble
N2.C1.D1.R0.S04: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N4.C0.D1.R0.S03: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N6.C0.D0.R1.S11: Total Receive Enable Delay = 1282
N0.C0.D0.R1.S09: Total Receive Enable Delay = 1320
N2.C1.D1.R0.S05: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N4.C0.D1.R0.S04: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N6.C0.D0.R1.S12: Total Receive Enable Delay = 1262
N0.C0.D0.R1.S10: Total Receive Enable Delay = 1303
N2.C1.D1.R0.S06: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N4.C0.D1.R0.S05: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N6.C0.D0.R1.S13: Total Receive Enable Delay = 1254
N0.C0.D0.R1.S11: Total Receive Enable Delay = 1276
N2.C1.D1.R0.S07: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N4.C0.D1.R0.S06: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N6.C0.D0.R1.S14: Total Receive Enable Delay = 1277
N0.C0.D0.R1.S12: Total Receive Enable Delay = 1255
N2.C1.D1.R0.S08: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N4.C0.D1.R0.S07: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N6.C0.D0.R1.S15: Total Receive Enable Delay = 1310
N0.C0.D0.R1.S13: Total Receive Enable Delay = 1244
N2.C1.D1.R0.S00: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N4.C0.D1.R0.S08: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N6.C0.D0.R1.S16: Total Receive Enable Delay = 1331
N0.C0.D0.R1.S14: Total Receive Enable Delay = 1268
N2.C1.D1.R0.S01: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N4.C0.D1.R0.S00: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N6.C0.D0.R1.S17: Total Receive Enable Delay = 1249
N0.C0.D0.R1.S15: Total Receive Enable Delay = 1305
N2.C1.D1.R0.S02: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N4.C0.D1.R0.S01: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N6.C0.D1.R0: RcvEnFine: Initial RdCmd2RcvEnLatency = 10, Initial RdPtrOffsetRcvEn = 4
N0.C0.D0.R1.S16: Total Receive Enable Delay = 1325
N2.C1.D1.R0.S03: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N4.C0.D1.R0.S02: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N6.C0.D1.R0.S00: Rcv En Fine Value = 258
N0.C0.D0.R1.S17: Total Receive Enable Delay = 1240
N2.C1.D1.R0.S04: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N4.C0.D1.R0.S03: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N6.C0.D1.R0.S01: Rcv En Fine Value = 366
N0.C0.D1.R0: RcvEnFine: Initial RdCmd2RcvEnLatency = 10, Initial RdPtrOffsetRcvEn = 4
N2.C1.D1.R0.S05: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N4.C0.D1.R0.S04: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N6.C0.D1.R0.S02: Rcv En Fine Value = 338
N0.C0.D1.R0.S00: Rcv En Fine Value = 380
N2.C1.D1.R0.S06: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N4.C0.D1.R0.S05: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N6.C0.D1.R0.S03: Rcv En Fine Value = 316
N0.C0.D1.R0.S01: Rcv En Fine Value = 355
N2.C1.D1.R0.S07: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N4.C0.D1.R0.S06: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N6.C0.D1.R0.S04: Rcv En Fine Value = 310
N0.C0.D1.R0.S02: Rcv En Fine Value = 331
N2.C1.D1.R0.S08: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N4.C0.D1.R0.S07: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N6.C0.D1.R0.S05: Rcv En Fine Value = 331
N0.C0.D1.R0.S03: Rcv En Fine Value = 310
N2.C1.D1.R0.S00: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N4.C0.D1.R0.S08: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N6.C0.D1.R0.S06: Rcv En Fine Value = 365
N0.C0.D1.R0.S04: Rcv En Fine Value = 304
N2.C1.D1.R0.S01: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N4.C0.D1.R0.S00: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N6.C0.D1.R0.S07: Rcv En Fine Value = 259
N0.C0.D1.R0.S05: Rcv En Fine Value = 325
N2.C1.D1.R0.S02: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N4.C0.D1.R0.S01: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N6.C0.D1.R0.S08: Rcv En Fine Value = 305
N0.C0.D1.R0.S06: Rcv En Fine Value = 361
N2.C1.D1.R0.S03: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N4.C0.D1.R0.S02: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N6.C0.D1.R0.S09: Rcv En Fine Value = 257
N0.C0.D1.R0.S07: Rcv En Fine Value = 256
N2.C1.D1.R0.S04: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N4.C0.D1.R0.S03: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N6.C0.D1.R0.S10: Rcv En Fine Value = 364
N0.C0.D1.R0.S08: Rcv En Fine Value = 297
N2.C1.D1.R0.S05: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N4.C0.D1.R0.S04: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N6.C0.D1.R0.S11: Rcv En Fine Value = 333
N0.C0.D1.R0.S09: Rcv En Fine Value = 379
N2.C1.D1.R0.S06: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N4.C0.D1.R0.S05: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N6.C0.D1.R0.S12: Rcv En Fine Value = 316
N0.C0.D1.R0.S10: Rcv En Fine Value = 355
N2.C1.D1.R0.S07: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N4.C0.D1.R0.S06: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N6.C0.D1.R0.S13: Rcv En Fine Value = 309
N0.C0.D1.R0.S11: Rcv En Fine Value = 330
N2.C1.D1.R0.S08: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N4.C0.D1.R0.S07: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N6.C0.D1.R0.S14: Rcv En Fine Value = 330
N0.C0.D1.R0.S12: Rcv En Fine Value = 312
N2.C1.D1.R0.S00: Preamble found at Latency = 008
N4.C0.D1.R0.S08: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N6.C0.D1.R0.S15: Rcv En Fine Value = 362
N0.C0.D1.R0.S13: Rcv En Fine Value = 304
N2.C1.D1.R0.S01: Preamble found at Latency = 008
N4.C0.D1.R0.S00: Preamble found at Latency = 007
N6.C0.D1.R0.S16: Rcv En Fine Value = 256
N0.C0.D1.R0.S14: Rcv En Fine Value = 326
N2.C1.D1.R0.S02: Preamble found at Latency = 008
N4.C0.D1.R0.S01: Preamble found at Latency = 007
N6.C0.D1.R0.S17: Rcv En Fine Value = 302
N0.C0.D1.R0.S15: Rcv En Fine Value = 357
N2.C1.D1.R0.S06: Preamble found at Latency = 008
N4.C0.D1.R0.S02: Preamble found at Latency = 007
N6.C0.D1.R0: Starting preamble search lower nibbles
N0.C0.D1.R0.S16: Rcv En Fine Value = 381
N2.C1.D1.R0.S07: Preamble found at Latency = 008
N4.C0.D1.R0.S03: Preamble found at Latency = 007
N6.C0.D1.R0.S00: PI = 002, PtrOffset = 004
N0.C0.D1.R0.S17: Rcv En Fine Value = 292
N2.C1.D1.R0.S00: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N4.C0.D1.R0.S04: Preamble found at Latency = 007
N6.C0.D1.R0.S01: PI = 046, PtrOffset = 005
N0.C0.D1.R0: Starting preamble search lower nibbles
N2.C1.D1.R0.S01: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N4.C0.D1.R0.S05: Preamble found at Latency = 007
N6.C0.D1.R0.S02: PI = 018, PtrOffset = 005
N0.C0.D1.R0.S00: PI = 060, PtrOffset = 005
N2.C1.D1.R0.S02: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N4.C0.D1.R0.S06: Preamble found at Latency = 007
N6.C0.D1.R0.S03: PI = 060, PtrOffset = 004
N0.C0.D1.R0.S01: PI = 035, PtrOffset = 005
N2.C1.D1.R0.S03: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N4.C0.D1.R0.S07: Preamble found at Latency = 007
N6.C0.D1.R0.S04: PI = 054, PtrOffset = 004
N0.C0.D1.R0.S02: PI = 011, PtrOffset = 005
N2.C1.D1.R0.S04: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N4.C0.D1.R0.S08: Preamble found at Latency = 007
N6.C0.D1.R0.S05: PI = 011, PtrOffset = 005
N0.C0.D1.R0.S03: PI = 054, PtrOffset = 004
N2.C1.D1.R0.S05: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N4.C0.D1.R0.S00: Total Receive Enable Delay = 1307
N6.C0.D1.R0.S06: PI = 045, PtrOffset = 005
N0.C0.D1.R0.S04: PI = 048, PtrOffset = 004
N2.C1.D1.R0.S06: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N4.C0.D1.R0.S01: Total Receive Enable Delay = 1286
N6.C0.D1.R0.S07: PI = 003, PtrOffset = 004
N0.C0.D1.R0.S05: PI = 005, PtrOffset = 005
N2.C1.D1.R0.S07: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N4.C0.D1.R0.S02: Total Receive Enable Delay = 1258
N6.C0.D1.R0.S08: PI = 049, PtrOffset = 004
N0.C0.D1.R0.S06: PI = 041, PtrOffset = 005
N2.C1.D1.R0.S08: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N4.C0.D1.R0.S03: Total Receive Enable Delay = 1236
N6.C0.D1.R0.S00: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N0.C0.D1.R0.S07: PI = 000, PtrOffset = 004
N2.C1.D1.R0.S03: Preamble found at Latency = 007
N4.C0.D1.R0.S04: Total Receive Enable Delay = 1232
N6.C0.D1.R0.S01: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N0.C0.D1.R0.S08: PI = 041, PtrOffset = 004
N2.C1.D1.R0.S04: Preamble found at Latency = 007
N4.C0.D1.R0.S05: Total Receive Enable Delay = 1257
N6.C0.D1.R0.S02: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N0.C0.D1.R0.S00: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N2.C1.D1.R0.S05: Preamble found at Latency = 007
N4.C0.D1.R0.S06: Total Receive Enable Delay = 1287
N6.C0.D1.R0.S03: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N0.C0.D1.R0.S01: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N2.C1.D1.R0.S08: Preamble found at Latency = 007
N4.C0.D1.R0.S07: Total Receive Enable Delay = 1309
N6.C0.D1.R0.S04: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N0.C0.D1.R0.S02: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N2.C1.D1.R0.S00: Total Receive Enable Delay = 1358
N4.C0.D1.R0.S08: Total Receive Enable Delay = 1226
N6.C0.D1.R0.S05: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N0.C0.D1.R0.S03: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N2.C1.D1.R0.S01: Total Receive Enable Delay = 1341
N4.C0.D1.R0: Starting preamble search upper nibbles
N6.C0.D1.R0.S06: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N0.C0.D1.R0.S04: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N2.C1.D1.R0.S02: Total Receive Enable Delay = 1312
N4.C0.D1.R0.S09: PI = 059, PtrOffset = 005
N6.C0.D1.R0.S07: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N0.C0.D1.R0.S05: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N2.C1.D1.R0.S03: Total Receive Enable Delay = 1290
N4.C0.D1.R0.S10: PI = 040, PtrOffset = 005
N6.C0.D1.R0.S08: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N0.C0.D1.R0.S06: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N2.C1.D1.R0.S04: Total Receive Enable Delay = 1284
N4.C0.D1.R0.S11: PI = 011, PtrOffset = 005
N6.C0.D1.R0.S00: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N0.C0.D1.R0.S07: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N2.C1.D1.R0.S05: Total Receive Enable Delay = 1310
N4.C0.D1.R0.S12: PI = 051, PtrOffset = 004
N6.C0.D1.R0.S01: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N0.C0.D1.R0.S08: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N2.C1.D1.R0.S06: Total Receive Enable Delay = 1332
N4.C0.D1.R0.S13: PI = 048, PtrOffset = 004
N6.C0.D1.R0.S02: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N0.C0.D1.R0.S00: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N2.C1.D1.R0.S07: Total Receive Enable Delay = 1353
N4.C0.D1.R0.S14: PI = 005, PtrOffset = 005
N6.C0.D1.R0.S03: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N0.C0.D1.R0.S01: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N2.C1.D1.R0.S08: Total Receive Enable Delay = 1271
N4.C0.D1.R0.S15: PI = 036, PtrOffset = 005
N6.C0.D1.R0.S04: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N0.C0.D1.R0.S02: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N2.C1.D1.R0: Starting preamble search upper nibbles
N4.C0.D1.R0.S16: PI = 059, PtrOffset = 005
N6.C0.D1.R0.S05: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N0.C0.D1.R0.S03: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N2.C1.D1.R0.S09: PI = 048, PtrOffset = 004
N4.C0.D1.R0.S17: PI = 040, PtrOffset = 004
N6.C0.D1.R0.S06: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N0.C0.D1.R0.S04: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N2.C1.D1.R0.S10: PI = 030, PtrOffset = 004
N4.C0.D1.R0.S09: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N6.C0.D1.R0.S07: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N0.C0.D1.R0.S05: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N2.C1.D1.R0.S11: PI = 063, PtrOffset = 005
N4.C0.D1.R0.S10: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N6.C0.D1.R0.S08: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N0.C0.D1.R0.S06: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N2.C1.D1.R0.S12: PI = 044, PtrOffset = 005
N4.C0.D1.R0.S11: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N6.C0.D1.R0.S00: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N0.C0.D1.R0.S07: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N2.C1.D1.R0.S13: PI = 036, PtrOffset = 005
N4.C0.D1.R0.S12: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N6.C0.D1.R0.S01: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N0.C0.D1.R0.S08: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N2.C1.D1.R0.S14: PI = 061, PtrOffset = 005
N4.C0.D1.R0.S13: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N6.C0.D1.R0.S02: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N0.C0.D1.R0.S00: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N2.C1.D1.R0.S15: PI = 022, PtrOffset = 004
N4.C0.D1.R0.S14: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N6.C0.D1.R0.S03: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N0.C0.D1.R0.S01: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N2.C1.D1.R0.S16: PI = 043, PtrOffset = 004
N4.C0.D1.R0.S15: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N6.C0.D1.R0.S04: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N0.C0.D1.R0.S02: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N2.C1.D1.R0.S17: PI = 025, PtrOffset = 005
N4.C0.D1.R0.S16: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N6.C0.D1.R0.S05: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N0.C0.D1.R0.S03: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N2.C1.D1.R0.S09: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N4.C0.D1.R0.S17: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N6.C0.D1.R0.S06: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N0.C0.D1.R0.S04: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N2.C1.D1.R0.S10: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N4.C0.D1.R0.S09: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N6.C0.D1.R0.S07: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N0.C0.D1.R0.S05: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N2.C1.D1.R0.S11: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N4.C0.D1.R0.S10: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N6.C0.D1.R0.S08: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N0.C0.D1.R0.S06: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N2.C1.D1.R0.S12: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N4.C0.D1.R0.S11: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N6.C0.D1.R0.S00: Preamble found at Latency = 008
N0.C0.D1.R0.S07: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N2.C1.D1.R0.S13: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N4.C0.D1.R0.S12: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N6.C0.D1.R0.S07: Preamble found at Latency = 008
N0.C0.D1.R0.S08: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N2.C1.D1.R0.S14: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N4.C0.D1.R0.S13: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N6.C0.D1.R0.S00: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N0.C0.D1.R0.S07: Preamble found at Latency = 008
N2.C1.D1.R0.S15: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N4.C0.D1.R0.S14: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N6.C0.D1.R0.S01: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N0.C0.D1.R0.S00: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N2.C1.D1.R0.S16: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N4.C0.D1.R0.S15: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N6.C0.D1.R0.S02: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N0.C0.D1.R0.S01: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N2.C1.D1.R0.S17: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N4.C0.D1.R0.S16: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N6.C0.D1.R0.S03: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N0.C0.D1.R0.S02: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N2.C1.D1.R0.S09: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N4.C0.D1.R0.S17: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N6.C0.D1.R0.S04: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N0.C0.D1.R0.S03: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N2.C1.D1.R0.S10: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N4.C0.D1.R0.S09: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N6.C0.D1.R0.S05: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N0.C0.D1.R0.S04: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N2.C1.D1.R0.S11: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N4.C0.D1.R0.S10: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N6.C0.D1.R0.S06: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N0.C0.D1.R0.S05: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N2.C1.D1.R0.S12: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N4.C0.D1.R0.S11: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N6.C0.D1.R0.S07: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N0.C0.D1.R0.S06: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N2.C1.D1.R0.S13: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N4.C0.D1.R0.S12: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N6.C0.D1.R0.S08: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N0.C0.D1.R0.S07: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N2.C1.D1.R0.S14: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N4.C0.D1.R0.S13: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N6.C0.D1.R0.S01: Preamble found at Latency = 007
N0.C0.D1.R0.S08: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N2.C1.D1.R0.S15: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N4.C0.D1.R0.S14: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N6.C0.D1.R0.S02: Preamble found at Latency = 007
N0.C0.D1.R0.S00: Preamble found at Latency = 007
N2.C1.D1.R0.S16: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N4.C0.D1.R0.S15: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N6.C0.D1.R0.S03: Preamble found at Latency = 007
N0.C0.D1.R0.S01: Preamble found at Latency = 007
N2.C1.D1.R0.S17: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N4.C0.D1.R0.S16: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N6.C0.D1.R0.S04: Preamble found at Latency = 007
N0.C0.D1.R0.S02: Preamble found at Latency = 007
N2.C1.D1.R0.S09: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N4.C0.D1.R0.S17: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N6.C0.D1.R0.S05: Preamble found at Latency = 007
N0.C0.D1.R0.S03: Preamble found at Latency = 007
N2.C1.D1.R0.S10: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N4.C0.D1.R0.S09: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N6.C0.D1.R0.S06: Preamble found at Latency = 007
N0.C0.D1.R0.S04: Preamble found at Latency = 007
N2.C1.D1.R0.S11: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N4.C0.D1.R0.S10: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N6.C0.D1.R0.S08: Preamble found at Latency = 007
N0.C0.D1.R0.S05: Preamble found at Latency = 007
N2.C1.D1.R0.S12: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N4.C0.D1.R0.S11: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N6.C0.D1.R0.S00: Total Receive Enable Delay = 1314
N0.C0.D1.R0.S06: Preamble found at Latency = 007
N2.C1.D1.R0.S13: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N4.C0.D1.R0.S12: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N6.C0.D1.R0.S01: Total Receive Enable Delay = 1294
N0.C0.D1.R0.S08: Preamble found at Latency = 007
N2.C1.D1.R0.S14: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N4.C0.D1.R0.S13: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N6.C0.D1.R0.S02: Total Receive Enable Delay = 1266
N0.C0.D1.R0.S00: Total Receive Enable Delay = 1308
N2.C1.D1.R0.S15: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N4.C0.D1.R0.S14: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N6.C0.D1.R0.S03: Total Receive Enable Delay = 1244
N0.C0.D1.R0.S01: Total Receive Enable Delay = 1283
N2.C1.D1.R0.S16: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N4.C0.D1.R0.S15: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N6.C0.D1.R0.S04: Total Receive Enable Delay = 1238
N0.C0.D1.R0.S02: Total Receive Enable Delay = 1259
N2.C1.D1.R0.S17: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N4.C0.D1.R0.S16: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N6.C0.D1.R0.S05: Total Receive Enable Delay = 1259
N0.C0.D1.R0.S03: Total Receive Enable Delay = 1238
N2.C1.D1.R0.S09: Preamble found at Latency = 008
N4.C0.D1.R0.S17: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N6.C0.D1.R0.S06: Total Receive Enable Delay = 1293
N0.C0.D1.R0.S04: Total Receive Enable Delay = 1232
N2.C1.D1.R0.S10: Preamble found at Latency = 008
N4.C0.D1.R0.S09: Preamble found at Latency = 007
N6.C0.D1.R0.S07: Total Receive Enable Delay = 1315
N0.C0.D1.R0.S05: Total Receive Enable Delay = 1253
N2.C1.D1.R0.S15: Preamble found at Latency = 008
N4.C0.D1.R0.S10: Preamble found at Latency = 007
N6.C0.D1.R0.S08: Total Receive Enable Delay = 1233
N0.C0.D1.R0.S06: Total Receive Enable Delay = 1289
N2.C1.D1.R0.S16: Preamble found at Latency = 008
N4.C0.D1.R0.S11: Preamble found at Latency = 007
N6.C0.D1.R0: Starting preamble search upper nibbles
N0.C0.D1.R0.S07: Total Receive Enable Delay = 1312
N2.C1.D1.R0.S09: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N4.C0.D1.R0.S12: Preamble found at Latency = 007
N6.C0.D1.R0.S09: PI = 001, PtrOffset = 004
N0.C0.D1.R0.S08: Total Receive Enable Delay = 1225
N2.C1.D1.R0.S10: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N4.C0.D1.R0.S13: Preamble found at Latency = 007
N6.C0.D1.R0.S10: PI = 044, PtrOffset = 005
N0.C0.D1.R0: Starting preamble search upper nibbles
N2.C1.D1.R0.S11: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N4.C0.D1.R0.S14: Preamble found at Latency = 007
N6.C0.D1.R0.S11: PI = 013, PtrOffset = 005
N0.C0.D1.R0.S09: PI = 059, PtrOffset = 005
N2.C1.D1.R0.S12: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N4.C0.D1.R0.S15: Preamble found at Latency = 007
N6.C0.D1.R0.S12: PI = 060, PtrOffset = 004
N0.C0.D1.R0.S10: PI = 035, PtrOffset = 005
N2.C1.D1.R0.S13: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N4.C0.D1.R0.S16: Preamble found at Latency = 007
N6.C0.D1.R0.S13: PI = 053, PtrOffset = 004
N0.C0.D1.R0.S11: PI = 010, PtrOffset = 005
N2.C1.D1.R0.S14: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N4.C0.D1.R0.S17: Preamble found at Latency = 007
N6.C0.D1.R0.S14: PI = 010, PtrOffset = 005
N0.C0.D1.R0.S12: PI = 056, PtrOffset = 004
N2.C1.D1.R0.S15: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N4.C0.D1.R0: Preamble found for all upper nibbles, adjusting Pi, Offset to center into preamble
N6.C0.D1.R0.S15: PI = 042, PtrOffset = 005
N0.C0.D1.R0.S13: PI = 048, PtrOffset = 004
N2.C1.D1.R0.S16: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N4.C0.D1.R0.S09: Total Receive Enable Delay = 1307
N6.C0.D1.R0.S16: PI = 000, PtrOffset = 004
N0.C0.D1.R0.S14: PI = 006, PtrOffset = 005
N2.C1.D1.R0.S17: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N4.C0.D1.R0.S10: Total Receive Enable Delay = 1288
N6.C0.D1.R0.S17: PI = 046, PtrOffset = 004
N0.C0.D1.R0.S15: PI = 037, PtrOffset = 005
N2.C1.D1.R0.S11: Preamble found at Latency = 007
N4.C0.D1.R0.S11: Total Receive Enable Delay = 1259
N6.C0.D1.R0.S09: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N0.C0.D1.R0.S16: PI = 061, PtrOffset = 005
N2.C1.D1.R0.S12: Preamble found at Latency = 007
N4.C0.D1.R0.S12: Total Receive Enable Delay = 1235
N6.C0.D1.R0.S10: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N0.C0.D1.R0.S17: PI = 036, PtrOffset = 004
N2.C1.D1.R0.S13: Preamble found at Latency = 007
N4.C0.D1.R0.S13: Total Receive Enable Delay = 1232
N6.C0.D1.R0.S11: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N0.C0.D1.R0.S09: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N2.C1.D1.R0.S14: Preamble found at Latency = 007
N4.C0.D1.R0.S14: Total Receive Enable Delay = 1253
N6.C0.D1.R0.S12: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N0.C0.D1.R0.S10: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N2.C1.D1.R0.S17: Preamble found at Latency = 007
N4.C0.D1.R0.S15: Total Receive Enable Delay = 1284
N6.C0.D1.R0.S13: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N0.C0.D1.R0.S11: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N2.C1.D1.R0: Preamble found for all upper nibbles, adjusting Pi, Offset to center into preamble
N4.C0.D1.R0.S16: Total Receive Enable Delay = 1307
N6.C0.D1.R0.S14: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N0.C0.D1.R0.S12: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N2.C1.D1.R0.S09: Total Receive Enable Delay = 1360
N4.C0.D1.R0.S17: Total Receive Enable Delay = 1224
N6.C0.D1.R0.S15: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N0.C0.D1.R0.S13: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N2.C1.D1.R0.S10: Total Receive Enable Delay = 1342
N4.C0.D1.R1: RcvEnFine: Initial RdCmd2RcvEnLatency = 10, Initial RdPtrOffsetRcvEn = 4
N6.C0.D1.R0.S16: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N0.C0.D1.R0.S14: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N2.C1.D1.R0.S11: Total Receive Enable Delay = 1311
N4.C0.D1.R1.S00: Rcv En Fine Value = 378
N6.C0.D1.R0.S17: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N0.C0.D1.R0.S15: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N2.C1.D1.R0.S12: Total Receive Enable Delay = 1292
N4.C0.D1.R1.S01: Rcv En Fine Value = 361
N6.C0.D1.R0.S09: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N0.C0.D1.R0.S16: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N2.C1.D1.R0.S13: Total Receive Enable Delay = 1284
N4.C0.D1.R1.S02: Rcv En Fine Value = 329
N6.C0.D1.R0.S10: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N0.C0.D1.R0.S17: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N2.C1.D1.R0.S14: Total Receive Enable Delay = 1309
N4.C0.D1.R1.S03: Rcv En Fine Value = 306
N6.C0.D1.R0.S11: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N0.C0.D1.R0.S09: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N2.C1.D1.R0.S15: Total Receive Enable Delay = 1334
N4.C0.D1.R1.S04: Rcv En Fine Value = 303
N6.C0.D1.R0.S12: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N0.C0.D1.R0.S10: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N2.C1.D1.R0.S16: Total Receive Enable Delay = 1355
N4.C0.D1.R1.S05: Rcv En Fine Value = 328
N6.C0.D1.R0.S13: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N0.C0.D1.R0.S11: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N2.C1.D1.R0.S17: Total Receive Enable Delay = 1273
N4.C0.D1.R1.S06: Rcv En Fine Value = 358
N6.C0.D1.R0.S14: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N0.C0.D1.R0.S12: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N2.C1.D1.R1: RcvEnFine: Initial RdCmd2RcvEnLatency = 10, Initial RdPtrOffsetRcvEn = 4
N4.C0.D1.R1.S07: Rcv En Fine Value = 379
N6.C0.D1.R0.S15: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N0.C0.D1.R0.S13: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N2.C1.D1.R1.S00: Rcv En Fine Value = 303
N4.C0.D1.R1.S08: Rcv En Fine Value = 300
N6.C0.D1.R0.S16: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N0.C0.D1.R0.S14: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N2.C1.D1.R1.S01: Rcv En Fine Value = 282
N4.C0.D1.R1.S09: Rcv En Fine Value = 377
N6.C0.D1.R0.S17: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N0.C0.D1.R0.S15: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N2.C1.D1.R1.S02: Rcv En Fine Value = 382
N4.C0.D1.R1.S10: Rcv En Fine Value = 360
N6.C0.D1.R0.S09: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N0.C0.D1.R0.S16: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N2.C1.D1.R1.S03: Rcv En Fine Value = 363
N4.C0.D1.R1.S11: Rcv En Fine Value = 329
N6.C0.D1.R0.S10: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N0.C0.D1.R0.S17: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N2.C1.D1.R1.S04: Rcv En Fine Value = 356
N4.C0.D1.R1.S12: Rcv En Fine Value = 308
N6.C0.D1.R0.S11: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N0.C0.D1.R0.S09: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N2.C1.D1.R1.S05: Rcv En Fine Value = 380
N4.C0.D1.R1.S13: Rcv En Fine Value = 302
N6.C0.D1.R0.S12: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N0.C0.D1.R0.S10: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N2.C1.D1.R1.S06: Rcv En Fine Value = 277
N4.C0.D1.R1.S14: Rcv En Fine Value = 323
N6.C0.D1.R0.S13: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N0.C0.D1.R0.S11: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N2.C1.D1.R1.S07: Rcv En Fine Value = 296
N4.C0.D1.R1.S15: Rcv En Fine Value = 357
N6.C0.D1.R0.S14: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N0.C0.D1.R0.S12: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N2.C1.D1.R1.S08: Rcv En Fine Value = 345
N4.C0.D1.R1.S16: Rcv En Fine Value = 378
N6.C0.D1.R0.S15: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N0.C0.D1.R0.S13: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N2.C1.D1.R1.S09: Rcv En Fine Value = 304
N4.C0.D1.R1.S17: Rcv En Fine Value = 296
N6.C0.D1.R0.S16: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N0.C0.D1.R0.S14: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N2.C1.D1.R1.S10: Rcv En Fine Value = 284
N4.C0.D1.R1: Starting preamble search lower nibbles
N6.C0.D1.R0.S17: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N0.C0.D1.R0.S15: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N2.C1.D1.R1.S11: Rcv En Fine Value = 383
N4.C0.D1.R1.S00: PI = 058, PtrOffset = 005
N6.C0.D1.R0.S09: Preamble found at Latency = 008
N0.C0.D1.R0.S16: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N2.C1.D1.R1.S12: Rcv En Fine Value = 364
N4.C0.D1.R1.S01: PI = 041, PtrOffset = 005
N6.C0.D1.R0.S16: Preamble found at Latency = 008
N0.C0.D1.R0.S17: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N2.C1.D1.R1.S13: Rcv En Fine Value = 355
N4.C0.D1.R1.S02: PI = 009, PtrOffset = 005
N6.C0.D1.R0.S09: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N0.C0.D1.R0.S09: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N2.C1.D1.R1.S14: Rcv En Fine Value = 379
N4.C0.D1.R1.S03: PI = 050, PtrOffset = 004
N6.C0.D1.R0.S10: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N0.C0.D1.R0.S10: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N2.C1.D1.R1.S15: Rcv En Fine Value = 279
N4.C0.D1.R1.S04: PI = 047, PtrOffset = 004
N6.C0.D1.R0.S11: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N0.C0.D1.R0.S11: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N2.C1.D1.R1.S16: Rcv En Fine Value = 297
N4.C0.D1.R1.S05: PI = 008, PtrOffset = 005
N6.C0.D1.R0.S12: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N0.C0.D1.R0.S12: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N2.C1.D1.R1.S17: Rcv En Fine Value = 345
N4.C0.D1.R1.S06: PI = 038, PtrOffset = 005
N6.C0.D1.R0.S13: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N0.C0.D1.R0.S13: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N2.C1.D1.R1: Starting preamble search lower nibbles
N4.C0.D1.R1.S07: PI = 059, PtrOffset = 005
N6.C0.D1.R0.S14: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N0.C0.D1.R0.S14: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N2.C1.D1.R1.S00: PI = 047, PtrOffset = 004
N4.C0.D1.R1.S08: PI = 044, PtrOffset = 004
N6.C0.D1.R0.S15: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N0.C0.D1.R0.S15: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N2.C1.D1.R1.S01: PI = 026, PtrOffset = 004
N4.C0.D1.R1.S00: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N6.C0.D1.R0.S16: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N0.C0.D1.R0.S16: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N2.C1.D1.R1.S02: PI = 062, PtrOffset = 005
N4.C0.D1.R1.S01: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N6.C0.D1.R0.S17: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N0.C0.D1.R0.S17: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N2.C1.D1.R1.S03: PI = 043, PtrOffset = 005
N4.C0.D1.R1.S02: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N6.C0.D1.R0.S10: Preamble found at Latency = 007
N0.C0.D1.R0.S09: Preamble found at Latency = 007
N2.C1.D1.R1.S04: PI = 036, PtrOffset = 005
N4.C0.D1.R1.S03: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N6.C0.D1.R0.S11: Preamble found at Latency = 007
N0.C0.D1.R0.S10: Preamble found at Latency = 007
N2.C1.D1.R1.S05: PI = 060, PtrOffset = 005
N4.C0.D1.R1.S04: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N6.C0.D1.R0.S12: Preamble found at Latency = 007
N0.C0.D1.R0.S11: Preamble found at Latency = 007
N2.C1.D1.R1.S06: PI = 021, PtrOffset = 004
N4.C0.D1.R1.S05: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N6.C0.D1.R0.S13: Preamble found at Latency = 007
N0.C0.D1.R0.S12: Preamble found at Latency = 007
N2.C1.D1.R1.S07: PI = 040, PtrOffset = 004
N4.C0.D1.R1.S06: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N6.C0.D1.R0.S14: Preamble found at Latency = 007
N0.C0.D1.R0.S13: Preamble found at Latency = 007
N2.C1.D1.R1.S08: PI = 025, PtrOffset = 005
N4.C0.D1.R1.S07: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N6.C0.D1.R0.S15: Preamble found at Latency = 007
N0.C0.D1.R0.S14: Preamble found at Latency = 007
N2.C1.D1.R1.S00: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N4.C0.D1.R1.S08: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N6.C0.D1.R0.S17: Preamble found at Latency = 007
N0.C0.D1.R0.S15: Preamble found at Latency = 007
N2.C1.D1.R1.S01: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N4.C0.D1.R1.S00: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N6.C0.D1.R0: Preamble found for all upper nibbles, adjusting Pi, Offset to center into preamble
N0.C0.D1.R0.S16: Preamble found at Latency = 007
N2.C1.D1.R1.S02: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N4.C0.D1.R1.S01: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N6.C0.D1.R0.S09: Total Receive Enable Delay = 1313
N0.C0.D1.R0.S17: Preamble found at Latency = 007
N2.C1.D1.R1.S03: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N4.C0.D1.R1.S02: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N6.C0.D1.R0.S10: Total Receive Enable Delay = 1292
N0.C0.D1.R0: Preamble found for all upper nibbles, adjusting Pi, Offset to center into preamble
N2.C1.D1.R1.S04: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N4.C0.D1.R1.S03: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N6.C0.D1.R0.S11: Total Receive Enable Delay = 1261
N0.C0.D1.R0.S09: Total Receive Enable Delay = 1307
N2.C1.D1.R1.S05: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N4.C0.D1.R1.S04: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N6.C0.D1.R0.S12: Total Receive Enable Delay = 1244
N0.C0.D1.R0.S10: Total Receive Enable Delay = 1283
N2.C1.D1.R1.S06: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N4.C0.D1.R1.S05: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N6.C0.D1.R0.S13: Total Receive Enable Delay = 1237
N0.C0.D1.R0.S11: Total Receive Enable Delay = 1258
N2.C1.D1.R1.S07: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N4.C0.D1.R1.S06: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N6.C0.D1.R0.S14: Total Receive Enable Delay = 1258
N0.C0.D1.R0.S12: Total Receive Enable Delay = 1240
N2.C1.D1.R1.S08: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N4.C0.D1.R1.S07: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N6.C0.D1.R0.S15: Total Receive Enable Delay = 1290
N0.C0.D1.R0.S13: Total Receive Enable Delay = 1232
N2.C1.D1.R1.S00: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N4.C0.D1.R1.S08: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N6.C0.D1.R0.S16: Total Receive Enable Delay = 1312
N0.C0.D1.R0.S14: Total Receive Enable Delay = 1254
N2.C1.D1.R1.S01: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N4.C0.D1.R1.S00: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N6.C0.D1.R0.S17: Total Receive Enable Delay = 1230
N0.C0.D1.R0.S15: Total Receive Enable Delay = 1285
N2.C1.D1.R1.S02: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N4.C0.D1.R1.S01: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N6.C0.D1.R1: RcvEnFine: Initial RdCmd2RcvEnLatency = 10, Initial RdPtrOffsetRcvEn = 4
N0.C0.D1.R0.S16: Total Receive Enable Delay = 1309
N2.C1.D1.R1.S03: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N4.C0.D1.R1.S02: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N6.C0.D1.R1.S00: Rcv En Fine Value = 261
N0.C0.D1.R0.S17: Total Receive Enable Delay = 1220
N2.C1.D1.R1.S04: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N4.C0.D1.R1.S03: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N6.C0.D1.R1.S01: Rcv En Fine Value = 365
N0.C0.D1.R1: RcvEnFine: Initial RdCmd2RcvEnLatency = 10, Initial RdPtrOffsetRcvEn = 4
N2.C1.D1.R1.S05: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N4.C0.D1.R1.S04: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N6.C0.D1.R1.S02: Rcv En Fine Value = 335
N0.C0.D1.R1.S00: Rcv En Fine Value = 380
N2.C1.D1.R1.S06: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N4.C0.D1.R1.S05: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N6.C0.D1.R1.S03: Rcv En Fine Value = 315
N0.C0.D1.R1.S01: Rcv En Fine Value = 361
N2.C1.D1.R1.S07: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N4.C0.D1.R1.S06: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N6.C0.D1.R1.S04: Rcv En Fine Value = 308
N0.C0.D1.R1.S02: Rcv En Fine Value = 331
N2.C1.D1.R1.S08: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N4.C0.D1.R1.S07: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N6.C0.D1.R1.S05: Rcv En Fine Value = 331
N0.C0.D1.R1.S03: Rcv En Fine Value = 313
N2.C1.D1.R1.S00: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N4.C0.D1.R1.S08: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N6.C0.D1.R1.S06: Rcv En Fine Value = 365
N0.C0.D1.R1.S04: Rcv En Fine Value = 304
N2.C1.D1.R1.S01: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N4.C0.D1.R1.S00: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N6.C0.D1.R1.S07: Rcv En Fine Value = 259
N0.C0.D1.R1.S05: Rcv En Fine Value = 324
N2.C1.D1.R1.S02: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N4.C0.D1.R1.S01: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N6.C0.D1.R1.S08: Rcv En Fine Value = 306
N0.C0.D1.R1.S06: Rcv En Fine Value = 360
N2.C1.D1.R1.S03: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N4.C0.D1.R1.S02: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N6.C0.D1.R1.S09: Rcv En Fine Value = 256
N0.C0.D1.R1.S07: Rcv En Fine Value = 381
N2.C1.D1.R1.S04: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N4.C0.D1.R1.S03: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N6.C0.D1.R1.S10: Rcv En Fine Value = 364
N0.C0.D1.R1.S08: Rcv En Fine Value = 299
N2.C1.D1.R1.S05: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N4.C0.D1.R1.S04: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N6.C0.D1.R1.S11: Rcv En Fine Value = 332
N0.C0.D1.R1.S09: Rcv En Fine Value = 378
N2.C1.D1.R1.S06: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N4.C0.D1.R1.S05: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N6.C0.D1.R1.S12: Rcv En Fine Value = 314
N0.C0.D1.R1.S10: Rcv En Fine Value = 360
N2.C1.D1.R1.S07: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N4.C0.D1.R1.S06: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N6.C0.D1.R1.S13: Rcv En Fine Value = 309
N0.C0.D1.R1.S11: Rcv En Fine Value = 330
N2.C1.D1.R1.S08: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N4.C0.D1.R1.S07: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N6.C0.D1.R1.S14: Rcv En Fine Value = 330
N0.C0.D1.R1.S12: Rcv En Fine Value = 311
N2.C1.D1.R1.S00: Preamble found at Latency = 008
N4.C0.D1.R1.S08: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N6.C0.D1.R1.S15: Rcv En Fine Value = 362
N0.C0.D1.R1.S13: Rcv En Fine Value = 302
N2.C1.D1.R1.S01: Preamble found at Latency = 008
N4.C0.D1.R1.S00: Preamble found at Latency = 007
N6.C0.D1.R1.S16: Rcv En Fine Value = 257
N0.C0.D1.R1.S14: Rcv En Fine Value = 326
N2.C1.D1.R1.S06: Preamble found at Latency = 008
N4.C0.D1.R1.S01: Preamble found at Latency = 007
N6.C0.D1.R1.S17: Rcv En Fine Value = 301
N0.C0.D1.R1.S15: Rcv En Fine Value = 361
N2.C1.D1.R1.S07: Preamble found at Latency = 008
N4.C0.D1.R1.S02: Preamble found at Latency = 007
N6.C0.D1.R1: Starting preamble search lower nibbles
N0.C0.D1.R1.S16: Rcv En Fine Value = 380
N2.C1.D1.R1.S00: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N4.C0.D1.R1.S03: Preamble found at Latency = 007
N6.C0.D1.R1.S00: PI = 005, PtrOffset = 004
N0.C0.D1.R1.S17: Rcv En Fine Value = 297
N2.C1.D1.R1.S01: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N4.C0.D1.R1.S04: Preamble found at Latency = 007
N6.C0.D1.R1.S01: PI = 045, PtrOffset = 005
N0.C0.D1.R1: Starting preamble search lower nibbles
N2.C1.D1.R1.S02: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N4.C0.D1.R1.S05: Preamble found at Latency = 007
N6.C0.D1.R1.S02: PI = 015, PtrOffset = 005
N0.C0.D1.R1.S00: PI = 060, PtrOffset = 005
N2.C1.D1.R1.S03: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N4.C0.D1.R1.S06: Preamble found at Latency = 007
N6.C0.D1.R1.S03: PI = 059, PtrOffset = 004
N0.C0.D1.R1.S01: PI = 041, PtrOffset = 005
N2.C1.D1.R1.S04: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N4.C0.D1.R1.S07: Preamble found at Latency = 007
N6.C0.D1.R1.S04: PI = 052, PtrOffset = 004
N0.C0.D1.R1.S02: PI = 011, PtrOffset = 005
N2.C1.D1.R1.S05: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N4.C0.D1.R1.S08: Preamble found at Latency = 007
N6.C0.D1.R1.S05: PI = 011, PtrOffset = 005
N0.C0.D1.R1.S03: PI = 057, PtrOffset = 004
N2.C1.D1.R1.S06: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N4.C0.D1.R1.S00: Total Receive Enable Delay = 1306
N6.C0.D1.R1.S06: PI = 045, PtrOffset = 005
N0.C0.D1.R1.S04: PI = 048, PtrOffset = 004
N2.C1.D1.R1.S07: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N4.C0.D1.R1.S01: Total Receive Enable Delay = 1289
N6.C0.D1.R1.S07: PI = 003, PtrOffset = 004
N0.C0.D1.R1.S05: PI = 004, PtrOffset = 005
N2.C1.D1.R1.S08: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N4.C0.D1.R1.S02: Total Receive Enable Delay = 1257
N6.C0.D1.R1.S08: PI = 050, PtrOffset = 004
N0.C0.D1.R1.S06: PI = 040, PtrOffset = 005
N2.C1.D1.R1.S02: Preamble found at Latency = 007
N4.C0.D1.R1.S03: Total Receive Enable Delay = 1234
N6.C0.D1.R1.S00: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N0.C0.D1.R1.S07: PI = 061, PtrOffset = 005
N2.C1.D1.R1.S03: Preamble found at Latency = 007
N4.C0.D1.R1.S04: Total Receive Enable Delay = 1231
N6.C0.D1.R1.S01: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N0.C0.D1.R1.S08: PI = 043, PtrOffset = 004
N2.C1.D1.R1.S04: Preamble found at Latency = 007
N4.C0.D1.R1.S05: Total Receive Enable Delay = 1256
N6.C0.D1.R1.S02: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N0.C0.D1.R1.S00: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N2.C1.D1.R1.S05: Preamble found at Latency = 007
N4.C0.D1.R1.S06: Total Receive Enable Delay = 1286
N6.C0.D1.R1.S03: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N0.C0.D1.R1.S01: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N2.C1.D1.R1.S08: Preamble found at Latency = 007
N4.C0.D1.R1.S07: Total Receive Enable Delay = 1307
N6.C0.D1.R1.S04: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N0.C0.D1.R1.S02: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N2.C1.D1.R1.S00: Total Receive Enable Delay = 1359
N4.C0.D1.R1.S08: Total Receive Enable Delay = 1228
N6.C0.D1.R1.S05: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N0.C0.D1.R1.S03: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N2.C1.D1.R1.S01: Total Receive Enable Delay = 1338
N4.C0.D1.R1: Starting preamble search upper nibbles
N6.C0.D1.R1.S06: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N0.C0.D1.R1.S04: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N2.C1.D1.R1.S02: Total Receive Enable Delay = 1310
N4.C0.D1.R1.S09: PI = 057, PtrOffset = 005
N6.C0.D1.R1.S07: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N0.C0.D1.R1.S05: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N2.C1.D1.R1.S03: Total Receive Enable Delay = 1291
N4.C0.D1.R1.S10: PI = 040, PtrOffset = 005
N6.C0.D1.R1.S08: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N0.C0.D1.R1.S06: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N2.C1.D1.R1.S04: Total Receive Enable Delay = 1284
N4.C0.D1.R1.S11: PI = 009, PtrOffset = 005
N6.C0.D1.R1.S00: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N0.C0.D1.R1.S07: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N2.C1.D1.R1.S05: Total Receive Enable Delay = 1308
N4.C0.D1.R1.S12: PI = 052, PtrOffset = 004
N6.C0.D1.R1.S01: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N0.C0.D1.R1.S08: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N2.C1.D1.R1.S06: Total Receive Enable Delay = 1333
N4.C0.D1.R1.S13: PI = 046, PtrOffset = 004
N6.C0.D1.R1.S02: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N0.C0.D1.R1.S00: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N2.C1.D1.R1.S07: Total Receive Enable Delay = 1352
N4.C0.D1.R1.S14: PI = 003, PtrOffset = 005
N6.C0.D1.R1.S03: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N0.C0.D1.R1.S01: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N2.C1.D1.R1.S08: Total Receive Enable Delay = 1273
N4.C0.D1.R1.S15: PI = 037, PtrOffset = 005
N6.C0.D1.R1.S04: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N0.C0.D1.R1.S02: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N2.C1.D1.R1: Starting preamble search upper nibbles
N4.C0.D1.R1.S16: PI = 058, PtrOffset = 005
N6.C0.D1.R1.S05: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N0.C0.D1.R1.S03: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N2.C1.D1.R1.S09: PI = 048, PtrOffset = 004
N4.C0.D1.R1.S17: PI = 040, PtrOffset = 004
N6.C0.D1.R1.S06: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N0.C0.D1.R1.S04: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N2.C1.D1.R1.S10: PI = 028, PtrOffset = 004
N4.C0.D1.R1.S09: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N6.C0.D1.R1.S07: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N0.C0.D1.R1.S05: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N2.C1.D1.R1.S11: PI = 063, PtrOffset = 005
N4.C0.D1.R1.S10: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N6.C0.D1.R1.S08: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N0.C0.D1.R1.S06: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N2.C1.D1.R1.S12: PI = 044, PtrOffset = 005
N4.C0.D1.R1.S11: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N6.C0.D1.R1.S00: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N0.C0.D1.R1.S07: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N2.C1.D1.R1.S13: PI = 035, PtrOffset = 005
N4.C0.D1.R1.S12: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N6.C0.D1.R1.S01: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N0.C0.D1.R1.S08: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N2.C1.D1.R1.S14: PI = 059, PtrOffset = 005
N4.C0.D1.R1.S13: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N6.C0.D1.R1.S02: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N0.C0.D1.R1.S00: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N2.C1.D1.R1.S15: PI = 023, PtrOffset = 004
N4.C0.D1.R1.S14: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N6.C0.D1.R1.S03: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N0.C0.D1.R1.S01: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N2.C1.D1.R1.S16: PI = 041, PtrOffset = 004
N4.C0.D1.R1.S15: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N6.C0.D1.R1.S04: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N0.C0.D1.R1.S02: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N2.C1.D1.R1.S17: PI = 025, PtrOffset = 005
N4.C0.D1.R1.S16: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N6.C0.D1.R1.S05: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N0.C0.D1.R1.S03: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N2.C1.D1.R1.S09: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N4.C0.D1.R1.S17: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N6.C0.D1.R1.S06: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N0.C0.D1.R1.S04: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N2.C1.D1.R1.S10: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N4.C0.D1.R1.S09: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N6.C0.D1.R1.S07: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N0.C0.D1.R1.S05: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N2.C1.D1.R1.S11: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N4.C0.D1.R1.S10: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N6.C0.D1.R1.S08: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N0.C0.D1.R1.S06: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N2.C1.D1.R1.S12: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N4.C0.D1.R1.S11: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N6.C0.D1.R1.S00: Preamble found at Latency = 008
N0.C0.D1.R1.S07: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N2.C1.D1.R1.S13: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N4.C0.D1.R1.S12: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N6.C0.D1.R1.S07: Preamble found at Latency = 008
N0.C0.D1.R1.S08: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N2.C1.D1.R1.S14: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N4.C0.D1.R1.S13: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N6.C0.D1.R1.S00: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N0.C0.D1.R1.S00: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N2.C1.D1.R1.S15: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N4.C0.D1.R1.S14: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N6.C0.D1.R1.S01: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N0.C0.D1.R1.S01: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N2.C1.D1.R1.S16: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N4.C0.D1.R1.S15: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N6.C0.D1.R1.S02: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N0.C0.D1.R1.S02: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N2.C1.D1.R1.S17: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N4.C0.D1.R1.S16: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N6.C0.D1.R1.S03: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N0.C0.D1.R1.S03: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N2.C1.D1.R1.S09: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N4.C0.D1.R1.S17: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N6.C0.D1.R1.S04: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N0.C0.D1.R1.S04: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N2.C1.D1.R1.S10: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N4.C0.D1.R1.S09: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N6.C0.D1.R1.S05: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N0.C0.D1.R1.S05: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N2.C1.D1.R1.S11: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N4.C0.D1.R1.S10: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N6.C0.D1.R1.S06: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N0.C0.D1.R1.S06: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N2.C1.D1.R1.S12: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N4.C0.D1.R1.S11: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N6.C0.D1.R1.S07: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N0.C0.D1.R1.S07: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N2.C1.D1.R1.S13: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N4.C0.D1.R1.S12: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N6.C0.D1.R1.S08: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N0.C0.D1.R1.S08: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N2.C1.D1.R1.S14: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N4.C0.D1.R1.S13: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N6.C0.D1.R1.S01: Preamble found at Latency = 007
N0.C0.D1.R1.S00: Preamble found at Latency = 007
N2.C1.D1.R1.S15: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N4.C0.D1.R1.S14: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N6.C0.D1.R1.S02: Preamble found at Latency = 007
N0.C0.D1.R1.S01: Preamble found at Latency = 007
N2.C1.D1.R1.S16: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N4.C0.D1.R1.S15: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N6.C0.D1.R1.S03: Preamble found at Latency = 007
N0.C0.D1.R1.S02: Preamble found at Latency = 007
N2.C1.D1.R1.S17: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N4.C0.D1.R1.S16: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N6.C0.D1.R1.S04: Preamble found at Latency = 007
N0.C0.D1.R1.S03: Preamble found at Latency = 007
N2.C1.D1.R1.S09: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N4.C0.D1.R1.S17: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N6.C0.D1.R1.S05: Preamble found at Latency = 007
N0.C0.D1.R1.S04: Preamble found at Latency = 007
N2.C1.D1.R1.S10: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N4.C0.D1.R1.S09: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N6.C0.D1.R1.S06: Preamble found at Latency = 007
N0.C0.D1.R1.S05: Preamble found at Latency = 007
N2.C1.D1.R1.S11: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N4.C0.D1.R1.S10: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N6.C0.D1.R1.S08: Preamble found at Latency = 007
N0.C0.D1.R1.S06: Preamble found at Latency = 007
N2.C1.D1.R1.S12: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N4.C0.D1.R1.S11: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N6.C0.D1.R1.S00: Total Receive Enable Delay = 1317
N0.C0.D1.R1.S07: Preamble found at Latency = 007
N2.C1.D1.R1.S13: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N4.C0.D1.R1.S12: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N6.C0.D1.R1.S01: Total Receive Enable Delay = 1293
N0.C0.D1.R1.S08: Preamble found at Latency = 007
N2.C1.D1.R1.S14: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N4.C0.D1.R1.S13: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N6.C0.D1.R1.S02: Total Receive Enable Delay = 1263
N0.C0.D1.R1.S00: Total Receive Enable Delay = 1308
N2.C1.D1.R1.S15: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N4.C0.D1.R1.S14: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N6.C0.D1.R1.S03: Total Receive Enable Delay = 1243
N0.C0.D1.R1.S01: Total Receive Enable Delay = 1289
N2.C1.D1.R1.S16: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N4.C0.D1.R1.S15: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N6.C0.D1.R1.S04: Total Receive Enable Delay = 1236
N0.C0.D1.R1.S02: Total Receive Enable Delay = 1259
N2.C1.D1.R1.S17: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N4.C0.D1.R1.S16: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N6.C0.D1.R1.S05: Total Receive Enable Delay = 1259
N0.C0.D1.R1.S03: Total Receive Enable Delay = 1241
N2.C1.D1.R1.S09: Preamble found at Latency = 008
N4.C0.D1.R1.S17: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N6.C0.D1.R1.S06: Total Receive Enable Delay = 1293
N0.C0.D1.R1.S04: Total Receive Enable Delay = 1232
N2.C1.D1.R1.S10: Preamble found at Latency = 008
N4.C0.D1.R1.S09: Preamble found at Latency = 007
N6.C0.D1.R1.S07: Total Receive Enable Delay = 1315
N0.C0.D1.R1.S05: Total Receive Enable Delay = 1252
N2.C1.D1.R1.S15: Preamble found at Latency = 008
N4.C0.D1.R1.S10: Preamble found at Latency = 007
N6.C0.D1.R1.S08: Total Receive Enable Delay = 1234
N0.C0.D1.R1.S06: Total Receive Enable Delay = 1288
N2.C1.D1.R1.S16: Preamble found at Latency = 008
N4.C0.D1.R1.S11: Preamble found at Latency = 007
N6.C0.D1.R1: Starting preamble search upper nibbles
N0.C0.D1.R1.S07: Total Receive Enable Delay = 1309
N2.C1.D1.R1.S09: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N4.C0.D1.R1.S12: Preamble found at Latency = 007
N6.C0.D1.R1.S09: PI = 000, PtrOffset = 004
N0.C0.D1.R1.S08: Total Receive Enable Delay = 1227
N2.C1.D1.R1.S10: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N4.C0.D1.R1.S13: Preamble found at Latency = 007
N6.C0.D1.R1.S10: PI = 044, PtrOffset = 005
N0.C0.D1.R1: Starting preamble search upper nibbles
N2.C1.D1.R1.S11: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N4.C0.D1.R1.S14: Preamble found at Latency = 007
N6.C0.D1.R1.S11: PI = 012, PtrOffset = 005
N0.C0.D1.R1.S09: PI = 058, PtrOffset = 005
N2.C1.D1.R1.S12: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N4.C0.D1.R1.S15: Preamble found at Latency = 007
N6.C0.D1.R1.S12: PI = 058, PtrOffset = 004
N0.C0.D1.R1.S10: PI = 040, PtrOffset = 005
N2.C1.D1.R1.S13: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N4.C0.D1.R1.S16: Preamble found at Latency = 007
N6.C0.D1.R1.S13: PI = 053, PtrOffset = 004
N0.C0.D1.R1.S11: PI = 010, PtrOffset = 005
N2.C1.D1.R1.S14: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N4.C0.D1.R1.S17: Preamble found at Latency = 007
N6.C0.D1.R1.S14: PI = 010, PtrOffset = 005
N0.C0.D1.R1.S12: PI = 055, PtrOffset = 004
N2.C1.D1.R1.S15: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N4.C0.D1.R1: Preamble found for all upper nibbles, adjusting Pi, Offset to center into preamble
N6.C0.D1.R1.S15: PI = 042, PtrOffset = 005
N0.C0.D1.R1.S13: PI = 046, PtrOffset = 004
N2.C1.D1.R1.S16: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N4.C0.D1.R1.S09: Total Receive Enable Delay = 1305
N6.C0.D1.R1.S16: PI = 001, PtrOffset = 004
N0.C0.D1.R1.S14: PI = 006, PtrOffset = 005
N2.C1.D1.R1.S17: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N4.C0.D1.R1.S10: Total Receive Enable Delay = 1288
N6.C0.D1.R1.S17: PI = 045, PtrOffset = 004
N0.C0.D1.R1.S15: PI = 041, PtrOffset = 005
N2.C1.D1.R1.S11: Preamble found at Latency = 007
N4.C0.D1.R1.S11: Total Receive Enable Delay = 1257
N6.C0.D1.R1.S09: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N0.C0.D1.R1.S16: PI = 060, PtrOffset = 005
N2.C1.D1.R1.S12: Preamble found at Latency = 007
N4.C0.D1.R1.S12: Total Receive Enable Delay = 1236
N6.C0.D1.R1.S10: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N0.C0.D1.R1.S17: PI = 041, PtrOffset = 004
N2.C1.D1.R1.S13: Preamble found at Latency = 007
N4.C0.D1.R1.S13: Total Receive Enable Delay = 1230
N6.C0.D1.R1.S11: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N0.C0.D1.R1.S09: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N2.C1.D1.R1.S14: Preamble found at Latency = 007
N4.C0.D1.R1.S14: Total Receive Enable Delay = 1251
N6.C0.D1.R1.S12: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N0.C0.D1.R1.S10: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N2.C1.D1.R1.S17: Preamble found at Latency = 007
N4.C0.D1.R1.S15: Total Receive Enable Delay = 1285
N6.C0.D1.R1.S13: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N0.C0.D1.R1.S11: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N2.C1.D1.R1: Preamble found for all upper nibbles, adjusting Pi, Offset to center into preamble
N4.C0.D1.R1.S16: Total Receive Enable Delay = 1306
N6.C0.D1.R1.S14: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N0.C0.D1.R1.S12: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N2.C1.D1.R1.S09: Total Receive Enable Delay = 1360
N4.C0.D1.R1.S17: Total Receive Enable Delay = 1224
N6.C0.D1.R1.S15: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N0.C0.D1.R1.S13: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N2.C1.D1.R1.S10: Total Receive Enable Delay = 1340
START_DATA_REC_EN
N6.C0.D1.R1.S16: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N0.C0.D1.R1.S14: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N2.C1.D1.R1.S11: Total Receive Enable Delay = 1311
N4.C0.S00: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N6.C0.D1.R1.S17: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N0.C0.D1.R1.S15: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N2.C1.D1.R1.S12: Total Receive Enable Delay = 1292
N4.C0.S01: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N6.C0.D1.R1.S09: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N0.C0.D1.R1.S16: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N2.C1.D1.R1.S13: Total Receive Enable Delay = 1283
N4.C0.S02: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 5
N6.C0.D1.R1.S10: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N0.C0.D1.R1.S17: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N2.C1.D1.R1.S14: Total Receive Enable Delay = 1307
N4.C0.S03: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 5
N6.C0.D1.R1.S11: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N0.C0.D1.R1.S09: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N2.C1.D1.R1.S15: Total Receive Enable Delay = 1335
N4.C0.S04: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 5
N6.C0.D1.R1.S12: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N0.C0.D1.R1.S10: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N2.C1.D1.R1.S16: Total Receive Enable Delay = 1353
N4.C0.S05: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 5
N6.C0.D1.R1.S13: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N0.C0.D1.R1.S11: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N2.C1.D1.R1.S17: Total Receive Enable Delay = 1273
N4.C0.S06: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N6.C0.D1.R1.S14: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N0.C0.D1.R1.S12: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
START_DATA_REC_EN
N4.C0.S07: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N6.C0.D1.R1.S15: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N0.C0.D1.R1.S13: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N2.C1.S00: RdCmd2RcvEnLatency = 9, RdPtrOffsetRcvEn = 5
N4.C0.S08: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 5
N6.C0.D1.R1.S16: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N0.C0.D1.R1.S14: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N2.C1.S01: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N4.C0.S09: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N6.C0.D1.R1.S17: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N0.C0.D1.R1.S15: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N2.C1.S02: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N4.C0.S10: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N6.C0.D1.R1.S09: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N0.C0.D1.R1.S16: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N2.C1.S03: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N4.C0.S11: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 5
N6.C0.D1.R1.S10: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N0.C0.D1.R1.S17: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N2.C1.S04: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N4.C0.S12: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 5
N6.C0.D1.R1.S11: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N0.C0.D1.R1.S09: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N2.C1.S05: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N4.C0.S13: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 5
N6.C0.D1.R1.S12: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N0.C0.D1.R1.S10: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N2.C1.S06: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N4.C0.S14: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 5
N6.C0.D1.R1.S13: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N0.C0.D1.R1.S11: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N2.C1.S07: RdCmd2RcvEnLatency = 9, RdPtrOffsetRcvEn = 5
N4.C0.S15: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N6.C0.D1.R1.S14: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N0.C0.D1.R1.S12: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N2.C1.S08: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 5
N4.C0.S16: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N6.C0.D1.R1.S15: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N0.C0.D1.R1.S13: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N2.C1.S09: RdCmd2RcvEnLatency = 9, RdPtrOffsetRcvEn = 5
N4.C0.S17: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 5
N6.C0.D1.R1.S16: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N0.C0.D1.R1.S14: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N2.C1.S10: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N4.C0.D0.R0.S00: RcvEn: plus1 = 1, minus1 = 0, PI = 42, DB = 0
N6.C0.D1.R1.S17: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N0.C0.D1.R1.S15: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N2.C1.S11: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N4.C0.D0.R0.S01: RcvEn: plus1 = 1, minus1 = 0, PI = 23, DB = 0
N6.C0.D1.R1.S09: Preamble found at Latency = 008
N0.C0.D1.R1.S16: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N2.C1.S12: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N4.C0.D0.R0.S02: RcvEn: plus1 = 1, minus1 = 0, PI = 60, DB = 1
N6.C0.D1.R1.S16: Preamble found at Latency = 008
N0.C0.D1.R1.S17: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N2.C1.S13: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N4.C0.D0.R0.S03: RcvEn: plus1 = 1, minus1 = 0, PI = 36, DB = 0
N6.C0.D1.R1.S09: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N0.C0.D1.R1.S09: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N2.C1.S14: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N4.C0.D0.R0.S04: RcvEn: plus1 = 1, minus1 = 0, PI = 31, DB = 0
N6.C0.D1.R1.S10: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N0.C0.D1.R1.S10: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N2.C1.S15: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N4.C0.D0.R0.S05: RcvEn: plus1 = 1, minus1 = 0, PI = 54, DB = 1
N6.C0.D1.R1.S11: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N0.C0.D1.R1.S11: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N2.C1.S16: RdCmd2RcvEnLatency = 9, RdPtrOffsetRcvEn = 5
N4.C0.D0.R0.S06: RcvEn: plus1 = 1, minus1 = 0, PI = 22, DB = 0
N6.C0.D1.R1.S12: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N0.C0.D1.R1.S12: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N2.C1.S17: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 5
N4.C0.D0.R0.S07: RcvEn: plus1 = 1, minus1 = 0, PI = 44, DB = 0
N6.C0.D1.R1.S13: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N0.C0.D1.R1.S13: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N2.C1.D0.R0.S00: RcvEn: plus1 = 1, minus1 = 0, PI = 30, DB = 0
N4.C0.D0.R0.S08: RcvEn: plus1 = 1, minus1 = 0, PI = 25, DB = 0
N6.C0.D1.R1.S14: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N0.C0.D1.R1.S14: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N2.C1.D0.R0.S01: RcvEn: plus1 = 0, minus1 = 1, PI = 10, DB = 1
N4.C0.D0.R0.S09: RcvEn: plus1 = 1, minus1 = 0, PI = 42, DB = 0
N6.C0.D1.R1.S15: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N0.C0.D1.R1.S15: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N2.C1.D0.R0.S02: RcvEn: plus1 = 1, minus1 = 0, PI = 45, DB = 0
N4.C0.D0.R0.S10: RcvEn: plus1 = 1, minus1 = 0, PI = 24, DB = 0
N6.C0.D1.R1.S16: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N0.C0.D1.R1.S16: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N2.C1.D0.R0.S03: RcvEn: plus1 = 1, minus1 = 0, PI = 25, DB = 0
N4.C0.D0.R0.S11: RcvEn: plus1 = 1, minus1 = 0, PI = 59, DB = 1
N6.C0.D1.R1.S17: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N0.C0.D1.R1.S17: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N2.C1.D0.R0.S04: RcvEn: plus1 = 1, minus1 = 0, PI = 19, DB = 0
N4.C0.D0.R0.S12: RcvEn: plus1 = 1, minus1 = 0, PI = 37, DB = 0
N6.C0.D1.R1.S10: Preamble found at Latency = 007
N0.C0.D1.R1.S09: Preamble found at Latency = 007
N2.C1.D0.R0.S05: RcvEn: plus1 = 1, minus1 = 0, PI = 43, DB = 0
N4.C0.D0.R0.S13: RcvEn: plus1 = 1, minus1 = 0, PI = 30, DB = 0
N6.C0.D1.R1.S11: Preamble found at Latency = 007
N0.C0.D1.R1.S10: Preamble found at Latency = 007
N2.C1.D0.R0.S06: RcvEn: plus1 = 0, minus1 = 1, PI = 03, DB = 1
N4.C0.D0.R0.S14: RcvEn: plus1 = 1, minus1 = 0, PI = 51, DB = 1
N6.C0.D1.R1.S12: Preamble found at Latency = 007
N0.C0.D1.R1.S11: Preamble found at Latency = 007
N2.C1.D0.R0.S07: RcvEn: plus1 = 1, minus1 = 0, PI = 25, DB = 0
N4.C0.D0.R0.S15: RcvEn: plus1 = 1, minus1 = 0, PI = 19, DB = 0
N6.C0.D1.R1.S13: Preamble found at Latency = 007
N0.C0.D1.R1.S12: Preamble found at Latency = 007
N2.C1.D0.R0.S08: RcvEn: plus1 = 0, minus1 = 1, PI = 06, DB = 1
N4.C0.D0.R0.S16: RcvEn: plus1 = 1, minus1 = 0, PI = 42, DB = 0
N6.C0.D1.R1.S14: Preamble found at Latency = 007
N0.C0.D1.R1.S13: Preamble found at Latency = 007
N2.C1.D0.R0.S09: RcvEn: plus1 = 1, minus1 = 0, PI = 30, DB = 0
N4.C0.D0.R0.S17: RcvEn: plus1 = 1, minus1 = 0, PI = 23, DB = 0
N6.C0.D1.R1.S15: Preamble found at Latency = 007
N0.C0.D1.R1.S14: Preamble found at Latency = 007
N2.C1.D0.R0.S10: RcvEn: plus1 = 0, minus1 = 1, PI = 12, DB = 1
N4.C0.D0.R1.S00: RcvEn: plus1 = 1, minus1 = 0, PI = 42, DB = 0
N6.C0.D1.R1.S17: Preamble found at Latency = 007
N0.C0.D1.R1.S15: Preamble found at Latency = 007
N2.C1.D0.R0.S11: RcvEn: plus1 = 1, minus1 = 0, PI = 45, DB = 0
N4.C0.D0.R1.S01: RcvEn: plus1 = 1, minus1 = 0, PI = 23, DB = 0
N6.C0.D1.R1: Preamble found for all upper nibbles, adjusting Pi, Offset to center into preamble
N0.C0.D1.R1.S16: Preamble found at Latency = 007
N2.C1.D0.R0.S12: RcvEn: plus1 = 1, minus1 = 0, PI = 26, DB = 0
N4.C0.D0.R1.S02: RcvEn: plus1 = 1, minus1 = 0, PI = 60, DB = 1
N6.C0.D1.R1.S09: Total Receive Enable Delay = 1312
N0.C0.D1.R1.S17: Preamble found at Latency = 007
N2.C1.D0.R0.S13: RcvEn: plus1 = 1, minus1 = 0, PI = 18, DB = 0
N4.C0.D0.R1.S03: RcvEn: plus1 = 1, minus1 = 0, PI = 36, DB = 0
N6.C0.D1.R1.S10: Total Receive Enable Delay = 1292
N0.C0.D1.R1: Preamble found for all upper nibbles, adjusting Pi, Offset to center into preamble
N2.C1.D0.R0.S14: RcvEn: plus1 = 1, minus1 = 0, PI = 43, DB = 0
N4.C0.D0.R1.S04: RcvEn: plus1 = 1, minus1 = 0, PI = 31, DB = 0
N6.C0.D1.R1.S11: Total Receive Enable Delay = 1260
N0.C0.D1.R1.S09: Total Receive Enable Delay = 1306
N2.C1.D0.R0.S15: RcvEn: plus1 = 0, minus1 = 1, PI = 05, DB = 1
N4.C0.D0.R1.S05: RcvEn: plus1 = 1, minus1 = 0, PI = 54, DB = 1
N6.C0.D1.R1.S12: Total Receive Enable Delay = 1242
N0.C0.D1.R1.S10: Total Receive Enable Delay = 1288
N2.C1.D0.R0.S16: RcvEn: plus1 = 1, minus1 = 0, PI = 24, DB = 0
N4.C0.D0.R1.S06: RcvEn: plus1 = 1, minus1 = 0, PI = 22, DB = 0
N6.C0.D1.R1.S13: Total Receive Enable Delay = 1237
N0.C0.D1.R1.S11: Total Receive Enable Delay = 1258
N2.C1.D0.R0.S17: RcvEn: plus1 = 0, minus1 = 1, PI = 07, DB = 1
N4.C0.D0.R1.S07: RcvEn: plus1 = 1, minus1 = 0, PI = 44, DB = 0
N6.C0.D1.R1.S14: Total Receive Enable Delay = 1258
N0.C0.D1.R1.S12: Total Receive Enable Delay = 1239
N2.C1.D0.R1.S00: RcvEn: plus1 = 1, minus1 = 0, PI = 30, DB = 0
N4.C0.D0.R1.S08: RcvEn: plus1 = 1, minus1 = 0, PI = 25, DB = 0
N6.C0.D1.R1.S15: Total Receive Enable Delay = 1290
N0.C0.D1.R1.S13: Total Receive Enable Delay = 1230
N2.C1.D0.R1.S01: RcvEn: plus1 = 0, minus1 = 1, PI = 10, DB = 1
N4.C0.D0.R1.S09: RcvEn: plus1 = 1, minus1 = 0, PI = 42, DB = 0
N6.C0.D1.R1.S16: Total Receive Enable Delay = 1313
N0.C0.D1.R1.S14: Total Receive Enable Delay = 1254
N2.C1.D0.R1.S02: RcvEn: plus1 = 1, minus1 = 0, PI = 45, DB = 0
N4.C0.D0.R1.S10: RcvEn: plus1 = 1, minus1 = 0, PI = 24, DB = 0
N6.C0.D1.R1.S17: Total Receive Enable Delay = 1229
N0.C0.D1.R1.S15: Total Receive Enable Delay = 1289
N2.C1.D0.R1.S03: RcvEn: plus1 = 1, minus1 = 0, PI = 25, DB = 0
N4.C0.D0.R1.S11: RcvEn: plus1 = 1, minus1 = 0, PI = 59, DB = 1
START_DATA_REC_EN
N0.C0.D1.R1.S16: Total Receive Enable Delay = 1308
N2.C1.D0.R1.S04: RcvEn: plus1 = 1, minus1 = 0, PI = 19, DB = 0
N4.C0.D0.R1.S12: RcvEn: plus1 = 1, minus1 = 0, PI = 37, DB = 0
N6.C0.S00: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N0.C0.D1.R1.S17: Total Receive Enable Delay = 1225
N2.C1.D0.R1.S05: RcvEn: plus1 = 1, minus1 = 0, PI = 43, DB = 0
N4.C0.D0.R1.S13: RcvEn: plus1 = 1, minus1 = 0, PI = 30, DB = 0
N6.C0.S01: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
START_DATA_REC_EN
N2.C1.D0.R1.S06: RcvEn: plus1 = 0, minus1 = 1, PI = 03, DB = 1
N4.C0.D0.R1.S14: RcvEn: plus1 = 1, minus1 = 0, PI = 51, DB = 1
N6.C0.S02: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 5
N0.C0.S00: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N2.C1.D0.R1.S07: RcvEn: plus1 = 1, minus1 = 0, PI = 25, DB = 0
N4.C0.D0.R1.S15: RcvEn: plus1 = 1, minus1 = 0, PI = 19, DB = 0
N6.C0.S03: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 5
N0.C0.S01: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N2.C1.D0.R1.S08: RcvEn: plus1 = 0, minus1 = 1, PI = 06, DB = 1
N4.C0.D0.R1.S16: RcvEn: plus1 = 1, minus1 = 0, PI = 42, DB = 0
N6.C0.S04: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 5
N0.C0.S02: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 5
N2.C1.D0.R1.S09: RcvEn: plus1 = 1, minus1 = 0, PI = 30, DB = 0
N4.C0.D0.R1.S17: RcvEn: plus1 = 1, minus1 = 0, PI = 23, DB = 0
N6.C0.S05: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 5
N0.C0.S03: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 5
N2.C1.D0.R1.S10: RcvEn: plus1 = 0, minus1 = 1, PI = 12, DB = 1
N4.C0.D1.R0.S00: RcvEn: plus1 = 1, minus1 = 0, PI = 26, DB = 0
N6.C0.S06: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N0.C0.S04: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 5
N2.C1.D0.R1.S11: RcvEn: plus1 = 1, minus1 = 0, PI = 45, DB = 0
N4.C0.D1.R0.S01: RcvEn: plus1 = 1, minus1 = 0, PI = 07, DB = 1
N6.C0.S07: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N0.C0.S05: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 5
N2.C1.D0.R1.S12: RcvEn: plus1 = 1, minus1 = 0, PI = 26, DB = 0
N4.C0.D1.R0.S02: RcvEn: plus1 = 1, minus1 = 0, PI = 41, DB = 0
N6.C0.S08: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 5
N0.C0.S06: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N2.C1.D0.R1.S13: RcvEn: plus1 = 1, minus1 = 0, PI = 18, DB = 0
N4.C0.D1.R0.S03: RcvEn: plus1 = 1, minus1 = 0, PI = 19, DB = 0
N6.C0.S09: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N0.C0.S07: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N2.C1.D0.R1.S14: RcvEn: plus1 = 1, minus1 = 0, PI = 43, DB = 0
N4.C0.D1.R0.S04: RcvEn: plus1 = 1, minus1 = 0, PI = 15, DB = 1
N6.C0.S10: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N0.C0.S08: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 5
N2.C1.D0.R1.S15: RcvEn: plus1 = 0, minus1 = 1, PI = 05, DB = 1
N4.C0.D1.R0.S05: RcvEn: plus1 = 1, minus1 = 0, PI = 40, DB = 0
N6.C0.S11: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 5
N0.C0.S09: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N2.C1.D0.R1.S16: RcvEn: plus1 = 1, minus1 = 0, PI = 24, DB = 0
N4.C0.D1.R0.S06: RcvEn: plus1 = 1, minus1 = 0, PI = 06, DB = 1
N6.C0.S12: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 5
N0.C0.S10: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N2.C1.D0.R1.S17: RcvEn: plus1 = 0, minus1 = 1, PI = 07, DB = 1
N4.C0.D1.R0.S07: RcvEn: plus1 = 1, minus1 = 0, PI = 28, DB = 0
N6.C0.S13: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 5
N0.C0.S11: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 5
N2.C1.D1.R0.S00: RcvEn: plus1 = 1, minus1 = 0, PI = 14, DB = 1
N4.C0.D1.R0.S08: RcvEn: plus1 = 1, minus1 = 0, PI = 11, DB = 1
N6.C0.S14: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 5
N0.C0.S12: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 5
N2.C1.D1.R0.S01: RcvEn: plus1 = 1, minus1 = 0, PI = 59, DB = 1
N4.C0.D1.R0.S09: RcvEn: plus1 = 1, minus1 = 0, PI = 26, DB = 0
N6.C0.S15: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N0.C0.S13: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 5
N2.C1.D1.R0.S02: RcvEn: plus1 = 1, minus1 = 0, PI = 31, DB = 0
N4.C0.D1.R0.S10: RcvEn: plus1 = 1, minus1 = 0, PI = 08, DB = 1
N6.C0.S16: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N0.C0.S14: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 5
N2.C1.D1.R0.S03: RcvEn: plus1 = 1, minus1 = 0, PI = 10, DB = 1
N4.C0.D1.R0.S11: RcvEn: plus1 = 1, minus1 = 0, PI = 42, DB = 0
N6.C0.S17: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 5
N0.C0.S15: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N2.C1.D1.R0.S04: RcvEn: plus1 = 1, minus1 = 0, PI = 04, DB = 1
N4.C0.D1.R0.S12: RcvEn: plus1 = 1, minus1 = 0, PI = 19, DB = 0
N6.C0.D0.R0.S00: RcvEn: plus1 = 1, minus1 = 0, PI = 53, DB = 1
N0.C0.S16: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N2.C1.D1.R0.S05: RcvEn: plus1 = 1, minus1 = 0, PI = 29, DB = 0
N4.C0.D1.R0.S13: RcvEn: plus1 = 1, minus1 = 0, PI = 15, DB = 1
N6.C0.D0.R0.S01: RcvEn: plus1 = 1, minus1 = 0, PI = 31, DB = 0
N0.C0.S17: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 5
N2.C1.D1.R0.S06: RcvEn: plus1 = 1, minus1 = 0, PI = 52, DB = 1
N4.C0.D1.R0.S14: RcvEn: plus1 = 1, minus1 = 0, PI = 36, DB = 0
N6.C0.D0.R0.S02: RcvEn: plus1 = 0, minus1 = 1, PI = 02, DB = 1
N0.C0.D0.R0.S00: RcvEn: plus1 = 1, minus1 = 0, PI = 42, DB = 0
N2.C1.D1.R0.S07: RcvEn: plus1 = 1, minus1 = 0, PI = 08, DB = 1
N4.C0.D1.R0.S15: RcvEn: plus1 = 1, minus1 = 0, PI = 04, DB = 1
N6.C0.D0.R0.S03: RcvEn: plus1 = 1, minus1 = 0, PI = 47, DB = 0
N0.C0.D0.R0.S01: RcvEn: plus1 = 1, minus1 = 0, PI = 23, DB = 0
N2.C1.D1.R0.S08: RcvEn: plus1 = 1, minus1 = 0, PI = 56, DB = 1
N4.C0.D1.R0.S16: RcvEn: plus1 = 1, minus1 = 0, PI = 26, DB = 0
N6.C0.D0.R0.S04: RcvEn: plus1 = 1, minus1 = 0, PI = 40, DB = 0
N0.C0.D0.R0.S02: RcvEn: plus1 = 1, minus1 = 0, PI = 58, DB = 1
N2.C1.D1.R0.S09: RcvEn: plus1 = 1, minus1 = 0, PI = 16, DB = 0
N4.C0.D1.R0.S17: RcvEn: plus1 = 1, minus1 = 0, PI = 08, DB = 1
N6.C0.D0.R0.S05: RcvEn: plus1 = 1, minus1 = 0, PI = 61, DB = 1
N0.C0.D0.R0.S03: RcvEn: plus1 = 1, minus1 = 0, PI = 41, DB = 0
N2.C1.D1.R0.S10: RcvEn: plus1 = 1, minus1 = 0, PI = 61, DB = 1
N4.C0.D1.R1.S00: RcvEn: plus1 = 1, minus1 = 0, PI = 26, DB = 0
N6.C0.D0.R0.S06: RcvEn: plus1 = 1, minus1 = 0, PI = 30, DB = 0
N0.C0.D0.R0.S04: RcvEn: plus1 = 1, minus1 = 0, PI = 31, DB = 0
N2.C1.D1.R0.S11: RcvEn: plus1 = 1, minus1 = 0, PI = 31, DB = 0
N4.C0.D1.R1.S01: RcvEn: plus1 = 1, minus1 = 0, PI = 07, DB = 1
N6.C0.D0.R0.S07: RcvEn: plus1 = 1, minus1 = 0, PI = 51, DB = 1
N0.C0.D0.R0.S05: RcvEn: plus1 = 1, minus1 = 0, PI = 53, DB = 1
N2.C1.D1.R0.S12: RcvEn: plus1 = 1, minus1 = 0, PI = 12, DB = 1
N4.C0.D1.R1.S02: RcvEn: plus1 = 1, minus1 = 0, PI = 41, DB = 0
N6.C0.D0.R0.S08: RcvEn: plus1 = 1, minus1 = 0, PI = 35, DB = 0
N0.C0.D0.R0.S06: RcvEn: plus1 = 1, minus1 = 0, PI = 25, DB = 0
N2.C1.D1.R0.S13: RcvEn: plus1 = 1, minus1 = 0, PI = 03, DB = 1
N4.C0.D1.R1.S03: RcvEn: plus1 = 1, minus1 = 0, PI = 19, DB = 0
N6.C0.D0.R0.S09: RcvEn: plus1 = 1, minus1 = 0, PI = 49, DB = 1
N0.C0.D0.R0.S07: RcvEn: plus1 = 1, minus1 = 0, PI = 45, DB = 0
N2.C1.D1.R0.S14: RcvEn: plus1 = 1, minus1 = 0, PI = 28, DB = 0
N4.C0.D1.R1.S04: RcvEn: plus1 = 1, minus1 = 0, PI = 15, DB = 1
N6.C0.D0.R0.S10: RcvEn: plus1 = 1, minus1 = 0, PI = 32, DB = 0
N0.C0.D0.R0.S08: RcvEn: plus1 = 1, minus1 = 0, PI = 27, DB = 0
N2.C1.D1.R0.S15: RcvEn: plus1 = 1, minus1 = 0, PI = 54, DB = 1
N4.C0.D1.R1.S05: RcvEn: plus1 = 1, minus1 = 0, PI = 40, DB = 0
N6.C0.D0.R0.S11: RcvEn: plus1 = 0, minus1 = 1, PI = 02, DB = 1
N0.C0.D0.R0.S09: RcvEn: plus1 = 1, minus1 = 0, PI = 41, DB = 0
N2.C1.D1.R0.S16: RcvEn: plus1 = 1, minus1 = 0, PI = 10, DB = 1
N4.C0.D1.R1.S06: RcvEn: plus1 = 1, minus1 = 0, PI = 06, DB = 1
N6.C0.D0.R0.S12: RcvEn: plus1 = 1, minus1 = 0, PI = 46, DB = 0
N0.C0.D0.R0.S10: RcvEn: plus1 = 1, minus1 = 0, PI = 22, DB = 0
N2.C1.D1.R0.S17: RcvEn: plus1 = 1, minus1 = 0, PI = 57, DB = 1
N4.C0.D1.R1.S07: RcvEn: plus1 = 1, minus1 = 0, PI = 28, DB = 0
N6.C0.D0.R0.S13: RcvEn: plus1 = 1, minus1 = 0, PI = 38, DB = 0
N0.C0.D0.R0.S11: RcvEn: plus1 = 1, minus1 = 0, PI = 58, DB = 1
N2.C1.D1.R1.S00: RcvEn: plus1 = 1, minus1 = 0, PI = 14, DB = 1
N4.C0.D1.R1.S08: RcvEn: plus1 = 1, minus1 = 0, PI = 11, DB = 1
N6.C0.D0.R0.S14: RcvEn: plus1 = 1, minus1 = 0, PI = 62, DB = 1
N0.C0.D0.R0.S12: RcvEn: plus1 = 1, minus1 = 0, PI = 39, DB = 0
N2.C1.D1.R1.S01: RcvEn: plus1 = 1, minus1 = 0, PI = 59, DB = 1
N4.C0.D1.R1.S09: RcvEn: plus1 = 1, minus1 = 0, PI = 26, DB = 0
N6.C0.D0.R0.S15: RcvEn: plus1 = 1, minus1 = 0, PI = 29, DB = 0
N0.C0.D0.R0.S13: RcvEn: plus1 = 1, minus1 = 0, PI = 30, DB = 0
N2.C1.D1.R1.S02: RcvEn: plus1 = 1, minus1 = 0, PI = 31, DB = 0
N4.C0.D1.R1.S10: RcvEn: plus1 = 1, minus1 = 0, PI = 08, DB = 1
N6.C0.D0.R0.S16: RcvEn: plus1 = 1, minus1 = 0, PI = 51, DB = 1
N0.C0.D0.R0.S14: RcvEn: plus1 = 1, minus1 = 0, PI = 53, DB = 1
N2.C1.D1.R1.S03: RcvEn: plus1 = 1, minus1 = 0, PI = 10, DB = 1
N4.C0.D1.R1.S11: RcvEn: plus1 = 1, minus1 = 0, PI = 42, DB = 0
N6.C0.D0.R0.S17: RcvEn: plus1 = 1, minus1 = 0, PI = 33, DB = 0
N0.C0.D0.R0.S15: RcvEn: plus1 = 1, minus1 = 0, PI = 23, DB = 0
N2.C1.D1.R1.S04: RcvEn: plus1 = 1, minus1 = 0, PI = 04, DB = 1
N4.C0.D1.R1.S12: RcvEn: plus1 = 1, minus1 = 0, PI = 19, DB = 0
N6.C0.D0.R1.S00: RcvEn: plus1 = 1, minus1 = 0, PI = 53, DB = 1
N0.C0.D0.R0.S16: RcvEn: plus1 = 1, minus1 = 0, PI = 45, DB = 0
N2.C1.D1.R1.S05: RcvEn: plus1 = 1, minus1 = 0, PI = 29, DB = 0
N4.C0.D1.R1.S13: RcvEn: plus1 = 1, minus1 = 0, PI = 15, DB = 1
N6.C0.D0.R1.S01: RcvEn: plus1 = 1, minus1 = 0, PI = 31, DB = 0
N0.C0.D0.R0.S17: RcvEn: plus1 = 1, minus1 = 0, PI = 25, DB = 0
N2.C1.D1.R1.S06: RcvEn: plus1 = 1, minus1 = 0, PI = 52, DB = 1
N4.C0.D1.R1.S14: RcvEn: plus1 = 1, minus1 = 0, PI = 36, DB = 0
N6.C0.D0.R1.S02: RcvEn: plus1 = 0, minus1 = 1, PI = 02, DB = 1
N0.C0.D0.R1.S00: RcvEn: plus1 = 1, minus1 = 0, PI = 42, DB = 0
N2.C1.D1.R1.S07: RcvEn: plus1 = 1, minus1 = 0, PI = 08, DB = 1
N4.C0.D1.R1.S15: RcvEn: plus1 = 1, minus1 = 0, PI = 04, DB = 1
N6.C0.D0.R1.S03: RcvEn: plus1 = 1, minus1 = 0, PI = 47, DB = 0
N0.C0.D0.R1.S01: RcvEn: plus1 = 1, minus1 = 0, PI = 23, DB = 0
N2.C1.D1.R1.S08: RcvEn: plus1 = 1, minus1 = 0, PI = 56, DB = 1
N4.C0.D1.R1.S16: RcvEn: plus1 = 1, minus1 = 0, PI = 26, DB = 0
N6.C0.D0.R1.S04: RcvEn: plus1 = 1, minus1 = 0, PI = 40, DB = 0
N0.C0.D0.R1.S02: RcvEn: plus1 = 1, minus1 = 0, PI = 58, DB = 1
N2.C1.D1.R1.S09: RcvEn: plus1 = 1, minus1 = 0, PI = 16, DB = 0
N4.C0.D1.R1.S17: RcvEn: plus1 = 1, minus1 = 0, PI = 08, DB = 1
N6.C0.D0.R1.S05: RcvEn: plus1 = 1, minus1 = 0, PI = 61, DB = 1
N0.C0.D0.R1.S03: RcvEn: plus1 = 1, minus1 = 0, PI = 41, DB = 0
N2.C1.D1.R1.S10: RcvEn: plus1 = 1, minus1 = 0, PI = 61, DB = 1
STOP_DATA_REC_EN
N6.C0.D0.R1.S06: RcvEn: plus1 = 1, minus1 = 0, PI = 30, DB = 0
N0.C0.D0.R1.S04: RcvEn: plus1 = 1, minus1 = 0, PI = 31, DB = 0
N2.C1.D1.R1.S11: RcvEn: plus1 = 1, minus1 = 0, PI = 31, DB = 0
N4.C1.D0.R0: RcvEnFine: Initial RdCmd2RcvEnLatency = 10, Initial RdPtrOffsetRcvEn = 4
N6.C0.D0.R1.S07: RcvEn: plus1 = 1, minus1 = 0, PI = 51, DB = 1
N0.C0.D0.R1.S05: RcvEn: plus1 = 1, minus1 = 0, PI = 53, DB = 1
N2.C1.D1.R1.S12: RcvEn: plus1 = 1, minus1 = 0, PI = 12, DB = 1
N4.C1.D0.R0.S00: Rcv En Fine Value = 318
N6.C0.D0.R1.S08: RcvEn: plus1 = 1, minus1 = 0, PI = 35, DB = 0
N0.C0.D0.R1.S06: RcvEn: plus1 = 1, minus1 = 0, PI = 25, DB = 0
N2.C1.D1.R1.S13: RcvEn: plus1 = 1, minus1 = 0, PI = 03, DB = 1
N4.C1.D0.R0.S01: Rcv En Fine Value = 297
N6.C0.D0.R1.S09: RcvEn: plus1 = 1, minus1 = 0, PI = 49, DB = 1
N0.C0.D0.R1.S07: RcvEn: plus1 = 1, minus1 = 0, PI = 45, DB = 0
N2.C1.D1.R1.S14: RcvEn: plus1 = 1, minus1 = 0, PI = 28, DB = 0
N4.C1.D0.R0.S02: Rcv En Fine Value = 269
N6.C0.D0.R1.S10: RcvEn: plus1 = 1, minus1 = 0, PI = 32, DB = 0
N0.C0.D0.R1.S08: RcvEn: plus1 = 1, minus1 = 0, PI = 27, DB = 0
N2.C1.D1.R1.S15: RcvEn: plus1 = 1, minus1 = 0, PI = 54, DB = 1
N4.C1.D0.R0.S03: Rcv En Fine Value = 378
N6.C0.D0.R1.S11: RcvEn: plus1 = 0, minus1 = 1, PI = 02, DB = 1
N0.C0.D0.R1.S09: RcvEn: plus1 = 1, minus1 = 0, PI = 41, DB = 0
N2.C1.D1.R1.S16: RcvEn: plus1 = 1, minus1 = 0, PI = 10, DB = 1
N4.C1.D0.R0.S04: Rcv En Fine Value = 369
N6.C0.D0.R1.S12: RcvEn: plus1 = 1, minus1 = 0, PI = 46, DB = 0
N0.C0.D0.R1.S10: RcvEn: plus1 = 1, minus1 = 0, PI = 22, DB = 0
N2.C1.D1.R1.S17: RcvEn: plus1 = 1, minus1 = 0, PI = 57, DB = 1
N4.C1.D0.R0.S05: Rcv En Fine Value = 267
N6.C0.D0.R1.S13: RcvEn: plus1 = 1, minus1 = 0, PI = 38, DB = 0
N0.C0.D0.R1.S11: RcvEn: plus1 = 1, minus1 = 0, PI = 58, DB = 1
STOP_DATA_REC_EN
N4.C1.D0.R0.S06: Rcv En Fine Value = 289
N6.C0.D0.R1.S14: RcvEn: plus1 = 1, minus1 = 0, PI = 62, DB = 1
N0.C0.D0.R1.S12: RcvEn: plus1 = 1, minus1 = 0, PI = 39, DB = 0
N2.C2.D0.R0: RcvEnFine: Initial RdCmd2RcvEnLatency = 10, Initial RdPtrOffsetRcvEn = 4
N4.C1.D0.R0.S07: Rcv En Fine Value = 308
N6.C0.D0.R1.S15: RcvEn: plus1 = 1, minus1 = 0, PI = 29, DB = 0
N0.C0.D0.R1.S13: RcvEn: plus1 = 1, minus1 = 0, PI = 30, DB = 0
N2.C2.D0.R0.S00: Rcv En Fine Value = 273
N4.C1.D0.R0.S08: Rcv En Fine Value = 356
N6.C0.D0.R1.S16: RcvEn: plus1 = 1, minus1 = 0, PI = 51, DB = 1
N0.C0.D0.R1.S14: RcvEn: plus1 = 1, minus1 = 0, PI = 53, DB = 1
N2.C2.D0.R0.S01: Rcv En Fine Value = 381
N4.C1.D0.R0.S09: Rcv En Fine Value = 318
N6.C0.D0.R1.S17: RcvEn: plus1 = 1, minus1 = 0, PI = 33, DB = 0
N0.C0.D0.R1.S15: RcvEn: plus1 = 1, minus1 = 0, PI = 23, DB = 0
N2.C2.D0.R0.S02: Rcv En Fine Value = 348
N4.C1.D0.R0.S10: Rcv En Fine Value = 299
N6.C0.D1.R0.S00: RcvEn: plus1 = 1, minus1 = 0, PI = 35, DB = 0
N0.C0.D0.R1.S16: RcvEn: plus1 = 1, minus1 = 0, PI = 45, DB = 0
N2.C2.D0.R0.S03: Rcv En Fine Value = 329
N4.C1.D0.R0.S11: Rcv En Fine Value = 269
N6.C0.D1.R0.S01: RcvEn: plus1 = 1, minus1 = 0, PI = 13, DB = 1
N0.C0.D0.R1.S17: RcvEn: plus1 = 1, minus1 = 0, PI = 25, DB = 0
N2.C2.D0.R0.S04: Rcv En Fine Value = 329
N4.C1.D0.R0.S12: Rcv En Fine Value = 379
N6.C0.D1.R0.S02: RcvEn: plus1 = 1, minus1 = 0, PI = 48, DB = 0
N0.C0.D1.R0.S00: RcvEn: plus1 = 1, minus1 = 0, PI = 28, DB = 0
N2.C2.D0.R0.S05: Rcv En Fine Value = 341
N4.C1.D0.R0.S13: Rcv En Fine Value = 369
N6.C0.D1.R0.S03: RcvEn: plus1 = 1, minus1 = 0, PI = 27, DB = 0
N0.C0.D1.R0.S01: RcvEn: plus1 = 1, minus1 = 0, PI = 06, DB = 1
N2.C2.D0.R0.S06: Rcv En Fine Value = 378
N4.C1.D0.R0.S14: Rcv En Fine Value = 267
N6.C0.D1.R0.S04: RcvEn: plus1 = 1, minus1 = 0, PI = 21, DB = 0
N0.C0.D1.R0.S02: RcvEn: plus1 = 1, minus1 = 0, PI = 43, DB = 0
N2.C2.D0.R0.S07: Rcv En Fine Value = 270
N4.C1.D0.R0.S15: Rcv En Fine Value = 291
N6.C0.D1.R0.S05: RcvEn: plus1 = 1, minus1 = 0, PI = 43, DB = 0
N0.C0.D1.R0.S03: RcvEn: plus1 = 1, minus1 = 0, PI = 23, DB = 0
N2.C2.D0.R0.S08: Rcv En Fine Value = 317
N4.C1.D0.R0.S16: Rcv En Fine Value = 310
N6.C0.D1.R0.S06: RcvEn: plus1 = 1, minus1 = 0, PI = 13, DB = 1
N0.C0.D1.R0.S04: RcvEn: plus1 = 1, minus1 = 0, PI = 16, DB = 0
N2.C2.D0.R0.S09: Rcv En Fine Value = 275
N4.C1.D0.R0.S17: Rcv En Fine Value = 356
N6.C0.D1.R0.S07: RcvEn: plus1 = 1, minus1 = 0, PI = 35, DB = 0
N0.C0.D1.R0.S05: RcvEn: plus1 = 1, minus1 = 0, PI = 36, DB = 0
N2.C2.D0.R0.S10: Rcv En Fine Value = 380
N4.C1.D0.R0: Starting preamble search lower nibbles
N6.C0.D1.R0.S08: RcvEn: plus1 = 1, minus1 = 0, PI = 17, DB = 0
N0.C0.D1.R0.S06: RcvEn: plus1 = 1, minus1 = 0, PI = 08, DB = 1
N2.C2.D0.R0.S11: Rcv En Fine Value = 348
N4.C1.D0.R0.S00: PI = 062, PtrOffset = 004
N6.C0.D1.R0.S09: RcvEn: plus1 = 1, minus1 = 0, PI = 32, DB = 0
N0.C0.D1.R0.S07: RcvEn: plus1 = 1, minus1 = 0, PI = 30, DB = 0
N2.C2.D0.R0.S12: Rcv En Fine Value = 331
N4.C1.D0.R0.S01: PI = 041, PtrOffset = 004
N6.C0.D1.R0.S10: RcvEn: plus1 = 1, minus1 = 0, PI = 12, DB = 1
N0.C0.D1.R0.S08: RcvEn: plus1 = 1, minus1 = 0, PI = 10, DB = 1
N2.C2.D0.R0.S13: Rcv En Fine Value = 329
N4.C1.D0.R0.S02: PI = 013, PtrOffset = 004
N6.C0.D1.R0.S11: RcvEn: plus1 = 1, minus1 = 0, PI = 44, DB = 0
N0.C0.D1.R0.S09: RcvEn: plus1 = 1, minus1 = 0, PI = 26, DB = 0
N2.C2.D0.R0.S14: Rcv En Fine Value = 341
N4.C1.D0.R0.S03: PI = 058, PtrOffset = 005
N6.C0.D1.R0.S12: RcvEn: plus1 = 1, minus1 = 0, PI = 27, DB = 0
N0.C0.D1.R0.S10: RcvEn: plus1 = 1, minus1 = 0, PI = 05, DB = 1
N2.C2.D0.R0.S15: Rcv En Fine Value = 378
N4.C1.D0.R0.S04: PI = 049, PtrOffset = 005
N6.C0.D1.R0.S13: RcvEn: plus1 = 1, minus1 = 0, PI = 21, DB = 0
N0.C0.D1.R0.S11: RcvEn: plus1 = 1, minus1 = 0, PI = 42, DB = 0
N2.C2.D0.R0.S16: Rcv En Fine Value = 269
N4.C1.D0.R0.S05: PI = 011, PtrOffset = 004
N6.C0.D1.R0.S14: RcvEn: plus1 = 1, minus1 = 0, PI = 42, DB = 0
N0.C0.D1.R0.S12: RcvEn: plus1 = 1, minus1 = 0, PI = 23, DB = 0
N2.C2.D0.R0.S17: Rcv En Fine Value = 313
N4.C1.D0.R0.S06: PI = 033, PtrOffset = 004
N6.C0.D1.R0.S15: RcvEn: plus1 = 1, minus1 = 0, PI = 10, DB = 1
N0.C0.D1.R0.S13: RcvEn: plus1 = 1, minus1 = 0, PI = 15, DB = 1
N2.C2.D0.R0: Starting preamble search lower nibbles
N4.C1.D0.R0.S07: PI = 052, PtrOffset = 004
N6.C0.D1.R0.S16: RcvEn: plus1 = 1, minus1 = 0, PI = 32, DB = 0
N0.C0.D1.R0.S14: RcvEn: plus1 = 1, minus1 = 0, PI = 38, DB = 0
N2.C2.D0.R0.S00: PI = 017, PtrOffset = 004
N4.C1.D0.R0.S08: PI = 036, PtrOffset = 005
N6.C0.D1.R0.S17: RcvEn: plus1 = 1, minus1 = 0, PI = 13, DB = 1
N0.C0.D1.R0.S15: RcvEn: plus1 = 1, minus1 = 0, PI = 07, DB = 1
N2.C2.D0.R0.S01: PI = 061, PtrOffset = 005
N4.C1.D0.R0.S00: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N6.C0.D1.R1.S00: RcvEn: plus1 = 1, minus1 = 0, PI = 35, DB = 0
N0.C0.D1.R0.S16: RcvEn: plus1 = 1, minus1 = 0, PI = 28, DB = 0
N2.C2.D0.R0.S02: PI = 028, PtrOffset = 005
N4.C1.D0.R0.S01: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N6.C0.D1.R1.S01: RcvEn: plus1 = 1, minus1 = 0, PI = 13, DB = 1
N0.C0.D1.R0.S17: RcvEn: plus1 = 1, minus1 = 0, PI = 06, DB = 1
N2.C2.D0.R0.S03: PI = 009, PtrOffset = 005
N4.C1.D0.R0.S02: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N6.C0.D1.R1.S02: RcvEn: plus1 = 1, minus1 = 0, PI = 48, DB = 0
N0.C0.D1.R1.S00: RcvEn: plus1 = 1, minus1 = 0, PI = 28, DB = 0
N2.C2.D0.R0.S04: PI = 009, PtrOffset = 005
N4.C1.D0.R0.S03: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N6.C0.D1.R1.S03: RcvEn: plus1 = 1, minus1 = 0, PI = 27, DB = 0
N0.C0.D1.R1.S01: RcvEn: plus1 = 1, minus1 = 0, PI = 06, DB = 1
N2.C2.D0.R0.S05: PI = 021, PtrOffset = 005
N4.C1.D0.R0.S04: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N6.C0.D1.R1.S04: RcvEn: plus1 = 1, minus1 = 0, PI = 21, DB = 0
N0.C0.D1.R1.S02: RcvEn: plus1 = 1, minus1 = 0, PI = 43, DB = 0
N2.C2.D0.R0.S06: PI = 058, PtrOffset = 005
N4.C1.D0.R0.S05: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N6.C0.D1.R1.S05: RcvEn: plus1 = 1, minus1 = 0, PI = 43, DB = 0
N0.C0.D1.R1.S03: RcvEn: plus1 = 1, minus1 = 0, PI = 23, DB = 0
N2.C2.D0.R0.S07: PI = 014, PtrOffset = 004
N4.C1.D0.R0.S06: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N6.C0.D1.R1.S06: RcvEn: plus1 = 1, minus1 = 0, PI = 13, DB = 1
N0.C0.D1.R1.S04: RcvEn: plus1 = 1, minus1 = 0, PI = 16, DB = 0
N2.C2.D0.R0.S08: PI = 061, PtrOffset = 004
N4.C1.D0.R0.S07: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N6.C0.D1.R1.S07: RcvEn: plus1 = 1, minus1 = 0, PI = 35, DB = 0
N0.C0.D1.R1.S05: RcvEn: plus1 = 1, minus1 = 0, PI = 36, DB = 0
N2.C2.D0.R0.S00: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N4.C1.D0.R0.S08: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N6.C0.D1.R1.S08: RcvEn: plus1 = 1, minus1 = 0, PI = 17, DB = 0
N0.C0.D1.R1.S06: RcvEn: plus1 = 1, minus1 = 0, PI = 08, DB = 1
N2.C2.D0.R0.S01: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N4.C1.D0.R0.S00: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N6.C0.D1.R1.S09: RcvEn: plus1 = 1, minus1 = 0, PI = 32, DB = 0
N0.C0.D1.R1.S07: RcvEn: plus1 = 1, minus1 = 0, PI = 30, DB = 0
N2.C2.D0.R0.S02: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N4.C1.D0.R0.S01: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N6.C0.D1.R1.S10: RcvEn: plus1 = 1, minus1 = 0, PI = 12, DB = 1
N0.C0.D1.R1.S08: RcvEn: plus1 = 1, minus1 = 0, PI = 10, DB = 1
N2.C2.D0.R0.S03: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N4.C1.D0.R0.S02: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N6.C0.D1.R1.S11: RcvEn: plus1 = 1, minus1 = 0, PI = 44, DB = 0
N0.C0.D1.R1.S09: RcvEn: plus1 = 1, minus1 = 0, PI = 26, DB = 0
N2.C2.D0.R0.S04: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N4.C1.D0.R0.S03: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N6.C0.D1.R1.S12: RcvEn: plus1 = 1, minus1 = 0, PI = 27, DB = 0
N0.C0.D1.R1.S10: RcvEn: plus1 = 1, minus1 = 0, PI = 05, DB = 1
N2.C2.D0.R0.S05: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N4.C1.D0.R0.S04: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N6.C0.D1.R1.S13: RcvEn: plus1 = 1, minus1 = 0, PI = 21, DB = 0
N0.C0.D1.R1.S11: RcvEn: plus1 = 1, minus1 = 0, PI = 42, DB = 0
N2.C2.D0.R0.S06: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N4.C1.D0.R0.S05: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N6.C0.D1.R1.S14: RcvEn: plus1 = 1, minus1 = 0, PI = 42, DB = 0
N0.C0.D1.R1.S12: RcvEn: plus1 = 1, minus1 = 0, PI = 23, DB = 0
N2.C2.D0.R0.S07: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N4.C1.D0.R0.S06: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N6.C0.D1.R1.S15: RcvEn: plus1 = 1, minus1 = 0, PI = 10, DB = 1
N0.C0.D1.R1.S13: RcvEn: plus1 = 1, minus1 = 0, PI = 15, DB = 1
N2.C2.D0.R0.S08: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N4.C1.D0.R0.S07: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N6.C0.D1.R1.S16: RcvEn: plus1 = 1, minus1 = 0, PI = 32, DB = 0
N0.C0.D1.R1.S14: RcvEn: plus1 = 1, minus1 = 0, PI = 38, DB = 0
N2.C2.D0.R0.S00: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N4.C1.D0.R0.S08: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N6.C0.D1.R1.S17: RcvEn: plus1 = 1, minus1 = 0, PI = 13, DB = 1
N0.C0.D1.R1.S15: RcvEn: plus1 = 1, minus1 = 0, PI = 07, DB = 1
N2.C2.D0.R0.S01: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N4.C1.D0.R0.S00: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
STOP_DATA_REC_EN
N0.C0.D1.R1.S16: RcvEn: plus1 = 1, minus1 = 0, PI = 28, DB = 0
N2.C2.D0.R0.S02: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N4.C1.D0.R0.S01: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N6.C1.D0.R0: RcvEnFine: Initial RdCmd2RcvEnLatency = 10, Initial RdPtrOffsetRcvEn = 4
N0.C0.D1.R1.S17: RcvEn: plus1 = 1, minus1 = 0, PI = 06, DB = 1
N2.C2.D0.R0.S03: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N4.C1.D0.R0.S02: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N6.C1.D0.R0.S00: Rcv En Fine Value = 322
STOP_DATA_REC_EN
N2.C2.D0.R0.S04: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N4.C1.D0.R0.S03: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N6.C1.D0.R0.S01: Rcv En Fine Value = 302
N0.C1.D0.R0: RcvEnFine: Initial RdCmd2RcvEnLatency = 10, Initial RdPtrOffsetRcvEn = 4
N2.C2.D0.R0.S05: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N4.C1.D0.R0.S04: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N6.C1.D0.R0.S02: Rcv En Fine Value = 273
N0.C1.D0.R0.S00: Rcv En Fine Value = 318
N2.C2.D0.R0.S06: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N4.C1.D0.R0.S05: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N6.C1.D0.R0.S03: Rcv En Fine Value = 379
N0.C1.D0.R0.S01: Rcv En Fine Value = 296
N2.C2.D0.R0.S07: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N4.C1.D0.R0.S06: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N6.C1.D0.R0.S04: Rcv En Fine Value = 373
N0.C1.D0.R0.S02: Rcv En Fine Value = 268
N2.C2.D0.R0.S08: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N4.C1.D0.R0.S07: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N6.C1.D0.R0.S05: Rcv En Fine Value = 270
N0.C1.D0.R0.S03: Rcv En Fine Value = 378
N2.C2.D0.R0.S00: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N4.C1.D0.R0.S08: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N6.C1.D0.R0.S06: Rcv En Fine Value = 291
N0.C1.D0.R0.S04: Rcv En Fine Value = 369
N2.C2.D0.R0.S01: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N4.C1.D0.R0.S00: Preamble found at Latency = 008
N6.C1.D0.R0.S07: Rcv En Fine Value = 317
N0.C1.D0.R0.S05: Rcv En Fine Value = 268
N2.C2.D0.R0.S02: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N4.C1.D0.R0.S01: Preamble found at Latency = 008
N6.C1.D0.R0.S08: Rcv En Fine Value = 361
N0.C1.D0.R0.S06: Rcv En Fine Value = 288
N2.C2.D0.R0.S03: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N4.C1.D0.R0.S02: Preamble found at Latency = 008
N6.C1.D0.R0.S09: Rcv En Fine Value = 322
N0.C1.D0.R0.S07: Rcv En Fine Value = 311
N2.C2.D0.R0.S04: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N4.C1.D0.R0.S05: Preamble found at Latency = 008
N6.C1.D0.R0.S10: Rcv En Fine Value = 303
N0.C1.D0.R0.S08: Rcv En Fine Value = 356
N2.C2.D0.R0.S05: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N4.C1.D0.R0.S06: Preamble found at Latency = 008
N6.C1.D0.R0.S11: Rcv En Fine Value = 273
N0.C1.D0.R0.S09: Rcv En Fine Value = 318
N2.C2.D0.R0.S06: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N4.C1.D0.R0.S07: Preamble found at Latency = 008
N6.C1.D0.R0.S12: Rcv En Fine Value = 382
N0.C1.D0.R0.S10: Rcv En Fine Value = 297
N2.C2.D0.R0.S07: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N4.C1.D0.R0.S00: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N6.C1.D0.R0.S13: Rcv En Fine Value = 375
N0.C1.D0.R0.S11: Rcv En Fine Value = 269
N2.C2.D0.R0.S08: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N4.C1.D0.R0.S01: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N6.C1.D0.R0.S14: Rcv En Fine Value = 270
N0.C1.D0.R0.S12: Rcv En Fine Value = 378
N2.C2.D0.R0.S00: Preamble found at Latency = 008
N4.C1.D0.R0.S02: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N6.C1.D0.R0.S15: Rcv En Fine Value = 293
N0.C1.D0.R0.S13: Rcv En Fine Value = 368
N2.C2.D0.R0.S07: Preamble found at Latency = 008
N4.C1.D0.R0.S03: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N6.C1.D0.R0.S16: Rcv En Fine Value = 315
N0.C1.D0.R0.S14: Rcv En Fine Value = 264
N2.C2.D0.R0.S00: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N4.C1.D0.R0.S04: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N6.C1.D0.R0.S17: Rcv En Fine Value = 361
N0.C1.D0.R0.S15: Rcv En Fine Value = 289
N2.C2.D0.R0.S01: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N4.C1.D0.R0.S05: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N6.C1.D0.R0: Starting preamble search lower nibbles
N0.C1.D0.R0.S16: Rcv En Fine Value = 310
N2.C2.D0.R0.S02: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N4.C1.D0.R0.S06: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N6.C1.D0.R0.S00: PI = 002, PtrOffset = 005
N0.C1.D0.R0.S17: Rcv En Fine Value = 357
N2.C2.D0.R0.S03: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N4.C1.D0.R0.S07: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N6.C1.D0.R0.S01: PI = 046, PtrOffset = 004
N0.C1.D0.R0: Starting preamble search lower nibbles
N2.C2.D0.R0.S04: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N4.C1.D0.R0.S08: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N6.C1.D0.R0.S02: PI = 017, PtrOffset = 004
N0.C1.D0.R0.S00: PI = 062, PtrOffset = 004
N2.C2.D0.R0.S05: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N4.C1.D0.R0.S03: Preamble found at Latency = 007
N6.C1.D0.R0.S03: PI = 059, PtrOffset = 005
N0.C1.D0.R0.S01: PI = 040, PtrOffset = 004
N2.C2.D0.R0.S06: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N4.C1.D0.R0.S04: Preamble found at Latency = 007
N6.C1.D0.R0.S04: PI = 053, PtrOffset = 005
N0.C1.D0.R0.S02: PI = 012, PtrOffset = 004
N2.C2.D0.R0.S07: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N4.C1.D0.R0.S08: Preamble found at Latency = 007
N6.C1.D0.R0.S05: PI = 014, PtrOffset = 004
N0.C1.D0.R0.S03: PI = 058, PtrOffset = 005
N2.C2.D0.R0.S08: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N4.C1.D0.R0.S00: Total Receive Enable Delay = 1374
N6.C1.D0.R0.S06: PI = 035, PtrOffset = 004
N0.C1.D0.R0.S04: PI = 049, PtrOffset = 005
N2.C2.D0.R0.S01: Preamble found at Latency = 007
N4.C1.D0.R0.S01: Total Receive Enable Delay = 1353
N6.C1.D0.R0.S07: PI = 061, PtrOffset = 004
N0.C1.D0.R0.S05: PI = 012, PtrOffset = 004
N2.C2.D0.R0.S02: Preamble found at Latency = 007
N4.C1.D0.R0.S02: Total Receive Enable Delay = 1325
N6.C1.D0.R0.S08: PI = 041, PtrOffset = 005
N0.C1.D0.R0.S06: PI = 032, PtrOffset = 004
N2.C2.D0.R0.S03: Preamble found at Latency = 007
N4.C1.D0.R0.S03: Total Receive Enable Delay = 1306
N6.C1.D0.R0.S00: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N0.C1.D0.R0.S07: PI = 055, PtrOffset = 004
N2.C2.D0.R0.S04: Preamble found at Latency = 007
N4.C1.D0.R0.S04: Total Receive Enable Delay = 1297
N6.C1.D0.R0.S01: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N0.C1.D0.R0.S08: PI = 036, PtrOffset = 005
N2.C2.D0.R0.S05: Preamble found at Latency = 007
N4.C1.D0.R0.S05: Total Receive Enable Delay = 1323
N6.C1.D0.R0.S02: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N0.C1.D0.R0.S00: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N2.C2.D0.R0.S06: Preamble found at Latency = 007
N4.C1.D0.R0.S06: Total Receive Enable Delay = 1345
N6.C1.D0.R0.S03: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N0.C1.D0.R0.S01: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N2.C2.D0.R0.S08: Preamble found at Latency = 007
N4.C1.D0.R0.S07: Total Receive Enable Delay = 1364
N6.C1.D0.R0.S04: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N0.C1.D0.R0.S02: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N2.C2.D0.R0.S00: Total Receive Enable Delay = 1329
N4.C1.D0.R0.S08: Total Receive Enable Delay = 1284
N6.C1.D0.R0.S05: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N0.C1.D0.R0.S03: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N2.C2.D0.R0.S01: Total Receive Enable Delay = 1309
N4.C1.D0.R0: Starting preamble search upper nibbles
N6.C1.D0.R0.S06: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N0.C1.D0.R0.S04: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N2.C2.D0.R0.S02: Total Receive Enable Delay = 1276
N4.C1.D0.R0.S09: PI = 062, PtrOffset = 004
N6.C1.D0.R0.S07: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N0.C1.D0.R0.S05: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N2.C2.D0.R0.S03: Total Receive Enable Delay = 1257
N4.C1.D0.R0.S10: PI = 043, PtrOffset = 004
N6.C1.D0.R0.S08: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N0.C1.D0.R0.S06: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N2.C2.D0.R0.S04: Total Receive Enable Delay = 1257
N4.C1.D0.R0.S11: PI = 013, PtrOffset = 004
N6.C1.D0.R0.S00: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N0.C1.D0.R0.S07: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N2.C2.D0.R0.S05: Total Receive Enable Delay = 1269
N4.C1.D0.R0.S12: PI = 059, PtrOffset = 005
N6.C1.D0.R0.S01: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N0.C1.D0.R0.S08: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N2.C2.D0.R0.S06: Total Receive Enable Delay = 1306
N4.C1.D0.R0.S13: PI = 049, PtrOffset = 005
N6.C1.D0.R0.S02: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N0.C1.D0.R0.S00: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N2.C2.D0.R0.S07: Total Receive Enable Delay = 1326
N4.C1.D0.R0.S14: PI = 011, PtrOffset = 004
N6.C1.D0.R0.S03: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N0.C1.D0.R0.S01: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N2.C2.D0.R0.S08: Total Receive Enable Delay = 1245
N4.C1.D0.R0.S15: PI = 035, PtrOffset = 004
N6.C1.D0.R0.S04: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N0.C1.D0.R0.S02: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N2.C2.D0.R0: Starting preamble search upper nibbles
N4.C1.D0.R0.S16: PI = 054, PtrOffset = 004
N6.C1.D0.R0.S05: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N0.C1.D0.R0.S03: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N2.C2.D0.R0.S09: PI = 019, PtrOffset = 004
N4.C1.D0.R0.S17: PI = 036, PtrOffset = 005
N6.C1.D0.R0.S06: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N0.C1.D0.R0.S04: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N2.C2.D0.R0.S10: PI = 060, PtrOffset = 005
N4.C1.D0.R0.S09: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N6.C1.D0.R0.S07: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N0.C1.D0.R0.S05: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N2.C2.D0.R0.S11: PI = 028, PtrOffset = 005
N4.C1.D0.R0.S10: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N6.C1.D0.R0.S08: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N0.C1.D0.R0.S06: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N2.C2.D0.R0.S12: PI = 011, PtrOffset = 005
N4.C1.D0.R0.S11: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N6.C1.D0.R0.S00: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N0.C1.D0.R0.S07: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N2.C2.D0.R0.S13: PI = 009, PtrOffset = 005
N4.C1.D0.R0.S12: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N6.C1.D0.R0.S01: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N0.C1.D0.R0.S08: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N2.C2.D0.R0.S14: PI = 021, PtrOffset = 005
N4.C1.D0.R0.S13: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N6.C1.D0.R0.S02: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N0.C1.D0.R0.S00: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N2.C2.D0.R0.S15: PI = 058, PtrOffset = 005
N4.C1.D0.R0.S14: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N6.C1.D0.R0.S03: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N0.C1.D0.R0.S01: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N2.C2.D0.R0.S16: PI = 013, PtrOffset = 004
N4.C1.D0.R0.S15: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N6.C1.D0.R0.S04: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N0.C1.D0.R0.S02: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N2.C2.D0.R0.S17: PI = 057, PtrOffset = 004
N4.C1.D0.R0.S16: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N6.C1.D0.R0.S05: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N0.C1.D0.R0.S03: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N2.C2.D0.R0.S09: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N4.C1.D0.R0.S17: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N6.C1.D0.R0.S06: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N0.C1.D0.R0.S04: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N2.C2.D0.R0.S10: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N4.C1.D0.R0.S09: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N6.C1.D0.R0.S07: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N0.C1.D0.R0.S05: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N2.C2.D0.R0.S11: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N4.C1.D0.R0.S10: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N6.C1.D0.R0.S08: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N0.C1.D0.R0.S06: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N2.C2.D0.R0.S12: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N4.C1.D0.R0.S11: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N6.C1.D0.R0.S00: Preamble found at Latency = 008
N0.C1.D0.R0.S07: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N2.C2.D0.R0.S13: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N4.C1.D0.R0.S12: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N6.C1.D0.R0.S01: Preamble found at Latency = 008
N0.C1.D0.R0.S08: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N2.C2.D0.R0.S14: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N4.C1.D0.R0.S13: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N6.C1.D0.R0.S02: Preamble found at Latency = 008
N0.C1.D0.R0.S00: Preamble found at Latency = 008
N2.C2.D0.R0.S15: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N4.C1.D0.R0.S14: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N6.C1.D0.R0.S05: Preamble found at Latency = 008
N0.C1.D0.R0.S01: Preamble found at Latency = 008
N2.C2.D0.R0.S16: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N4.C1.D0.R0.S15: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N6.C1.D0.R0.S06: Preamble found at Latency = 008
N0.C1.D0.R0.S02: Preamble found at Latency = 008
N2.C2.D0.R0.S17: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N4.C1.D0.R0.S16: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N6.C1.D0.R0.S07: Preamble found at Latency = 008
N0.C1.D0.R0.S05: Preamble found at Latency = 008
N2.C2.D0.R0.S09: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N4.C1.D0.R0.S17: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N6.C1.D0.R0.S00: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N0.C1.D0.R0.S06: Preamble found at Latency = 008
N2.C2.D0.R0.S10: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N4.C1.D0.R0.S09: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N6.C1.D0.R0.S01: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N0.C1.D0.R0.S07: Preamble found at Latency = 008
N2.C2.D0.R0.S11: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N4.C1.D0.R0.S10: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N6.C1.D0.R0.S02: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N0.C1.D0.R0.S00: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N2.C2.D0.R0.S12: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N4.C1.D0.R0.S11: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N6.C1.D0.R0.S03: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N0.C1.D0.R0.S01: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N2.C2.D0.R0.S13: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N4.C1.D0.R0.S12: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N6.C1.D0.R0.S04: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N0.C1.D0.R0.S02: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N2.C2.D0.R0.S14: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N4.C1.D0.R0.S13: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N6.C1.D0.R0.S05: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N0.C1.D0.R0.S03: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N2.C2.D0.R0.S15: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N4.C1.D0.R0.S14: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N6.C1.D0.R0.S06: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N0.C1.D0.R0.S04: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N2.C2.D0.R0.S16: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N4.C1.D0.R0.S15: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N6.C1.D0.R0.S07: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N0.C1.D0.R0.S05: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N2.C2.D0.R0.S17: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N4.C1.D0.R0.S16: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N6.C1.D0.R0.S08: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N0.C1.D0.R0.S06: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N2.C2.D0.R0.S09: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N4.C1.D0.R0.S17: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N6.C1.D0.R0.S03: Preamble found at Latency = 007
N0.C1.D0.R0.S07: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N2.C2.D0.R0.S10: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N4.C1.D0.R0.S09: Preamble found at Latency = 008
N6.C1.D0.R0.S04: Preamble found at Latency = 007
N0.C1.D0.R0.S08: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N2.C2.D0.R0.S11: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N4.C1.D0.R0.S10: Preamble found at Latency = 008
N6.C1.D0.R0.S08: Preamble found at Latency = 007
N0.C1.D0.R0.S03: Preamble found at Latency = 007
N2.C2.D0.R0.S12: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N4.C1.D0.R0.S11: Preamble found at Latency = 008
N6.C1.D0.R0.S00: Total Receive Enable Delay = 1378
N0.C1.D0.R0.S04: Preamble found at Latency = 007
N2.C2.D0.R0.S13: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N4.C1.D0.R0.S14: Preamble found at Latency = 008
N6.C1.D0.R0.S01: Total Receive Enable Delay = 1358
N0.C1.D0.R0.S08: Preamble found at Latency = 007
N2.C2.D0.R0.S14: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N4.C1.D0.R0.S15: Preamble found at Latency = 008
N6.C1.D0.R0.S02: Total Receive Enable Delay = 1329
N0.C1.D0.R0.S00: Total Receive Enable Delay = 1374
N2.C2.D0.R0.S15: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N4.C1.D0.R0.S16: Preamble found at Latency = 008
N6.C1.D0.R0.S03: Total Receive Enable Delay = 1307
N0.C1.D0.R0.S01: Total Receive Enable Delay = 1352
N2.C2.D0.R0.S16: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N4.C1.D0.R0.S09: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N6.C1.D0.R0.S04: Total Receive Enable Delay = 1301
N0.C1.D0.R0.S02: Total Receive Enable Delay = 1324
N2.C2.D0.R0.S17: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N4.C1.D0.R0.S10: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N6.C1.D0.R0.S05: Total Receive Enable Delay = 1326
N0.C1.D0.R0.S03: Total Receive Enable Delay = 1306
N2.C2.D0.R0.S09: Preamble found at Latency = 008
N4.C1.D0.R0.S11: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N6.C1.D0.R0.S06: Total Receive Enable Delay = 1347
N0.C1.D0.R0.S04: Total Receive Enable Delay = 1297
N2.C2.D0.R0.S16: Preamble found at Latency = 008
N4.C1.D0.R0.S12: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N6.C1.D0.R0.S07: Total Receive Enable Delay = 1373
N0.C1.D0.R0.S05: Total Receive Enable Delay = 1324
N2.C2.D0.R0.S09: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N4.C1.D0.R0.S13: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N6.C1.D0.R0.S08: Total Receive Enable Delay = 1289
N0.C1.D0.R0.S06: Total Receive Enable Delay = 1344
N2.C2.D0.R0.S10: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N4.C1.D0.R0.S14: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N6.C1.D0.R0: Starting preamble search upper nibbles
N0.C1.D0.R0.S07: Total Receive Enable Delay = 1367
N2.C2.D0.R0.S11: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N4.C1.D0.R0.S15: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N6.C1.D0.R0.S09: PI = 002, PtrOffset = 005
N0.C1.D0.R0.S08: Total Receive Enable Delay = 1284
N2.C2.D0.R0.S12: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N4.C1.D0.R0.S16: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N6.C1.D0.R0.S10: PI = 047, PtrOffset = 004
N0.C1.D0.R0: Starting preamble search upper nibbles
N2.C2.D0.R0.S13: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N4.C1.D0.R0.S17: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N6.C1.D0.R0.S11: PI = 017, PtrOffset = 004
N0.C1.D0.R0.S09: PI = 062, PtrOffset = 004
N2.C2.D0.R0.S14: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N4.C1.D0.R0.S12: Preamble found at Latency = 007
N6.C1.D0.R0.S12: PI = 062, PtrOffset = 005
N0.C1.D0.R0.S10: PI = 041, PtrOffset = 004
N2.C2.D0.R0.S15: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N4.C1.D0.R0.S13: Preamble found at Latency = 007
N6.C1.D0.R0.S13: PI = 055, PtrOffset = 005
N0.C1.D0.R0.S11: PI = 013, PtrOffset = 004
N2.C2.D0.R0.S16: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N4.C1.D0.R0.S17: Preamble found at Latency = 007
N6.C1.D0.R0.S14: PI = 014, PtrOffset = 004
N0.C1.D0.R0.S12: PI = 058, PtrOffset = 005
N2.C2.D0.R0.S17: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N4.C1.D0.R0: Preamble found for all upper nibbles, adjusting Pi, Offset to center into preamble
N6.C1.D0.R0.S15: PI = 037, PtrOffset = 004
N0.C1.D0.R0.S13: PI = 048, PtrOffset = 005
N2.C2.D0.R0.S10: Preamble found at Latency = 007
N4.C1.D0.R0.S09: Total Receive Enable Delay = 1374
N6.C1.D0.R0.S16: PI = 059, PtrOffset = 004
N0.C1.D0.R0.S14: PI = 008, PtrOffset = 004
N2.C2.D0.R0.S11: Preamble found at Latency = 007
N4.C1.D0.R0.S10: Total Receive Enable Delay = 1355
N6.C1.D0.R0.S17: PI = 041, PtrOffset = 005
N0.C1.D0.R0.S15: PI = 033, PtrOffset = 004
N2.C2.D0.R0.S12: Preamble found at Latency = 007
N4.C1.D0.R0.S11: Total Receive Enable Delay = 1325
N6.C1.D0.R0.S09: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N0.C1.D0.R0.S16: PI = 054, PtrOffset = 004
N2.C2.D0.R0.S13: Preamble found at Latency = 007
N4.C1.D0.R0.S12: Total Receive Enable Delay = 1307
N6.C1.D0.R0.S10: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N0.C1.D0.R0.S17: PI = 037, PtrOffset = 005
N2.C2.D0.R0.S14: Preamble found at Latency = 007
N4.C1.D0.R0.S13: Total Receive Enable Delay = 1297
N6.C1.D0.R0.S11: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N0.C1.D0.R0.S09: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N2.C2.D0.R0.S15: Preamble found at Latency = 007
N4.C1.D0.R0.S14: Total Receive Enable Delay = 1323
N6.C1.D0.R0.S12: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N0.C1.D0.R0.S10: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N2.C2.D0.R0.S17: Preamble found at Latency = 007
N4.C1.D0.R0.S15: Total Receive Enable Delay = 1347
N6.C1.D0.R0.S13: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N0.C1.D0.R0.S11: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N2.C2.D0.R0: Preamble found for all upper nibbles, adjusting Pi, Offset to center into preamble
N4.C1.D0.R0.S16: Total Receive Enable Delay = 1366
N6.C1.D0.R0.S14: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N0.C1.D0.R0.S12: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N2.C2.D0.R0.S09: Total Receive Enable Delay = 1331
N4.C1.D0.R0.S17: Total Receive Enable Delay = 1284
N6.C1.D0.R0.S15: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N0.C1.D0.R0.S13: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N2.C2.D0.R0.S10: Total Receive Enable Delay = 1308
N4.C1.D0.R1: RcvEnFine: Initial RdCmd2RcvEnLatency = 10, Initial RdPtrOffsetRcvEn = 4
N6.C1.D0.R0.S16: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N0.C1.D0.R0.S14: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N2.C2.D0.R0.S11: Total Receive Enable Delay = 1276
N4.C1.D0.R1.S00: Rcv En Fine Value = 318
N6.C1.D0.R0.S17: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N0.C1.D0.R0.S15: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N2.C2.D0.R0.S12: Total Receive Enable Delay = 1259
N4.C1.D0.R1.S01: Rcv En Fine Value = 297
N6.C1.D0.R0.S09: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N0.C1.D0.R0.S16: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N2.C2.D0.R0.S13: Total Receive Enable Delay = 1257
N4.C1.D0.R1.S02: Rcv En Fine Value = 267
N6.C1.D0.R0.S10: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N0.C1.D0.R0.S17: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N2.C2.D0.R0.S14: Total Receive Enable Delay = 1269
N4.C1.D0.R1.S03: Rcv En Fine Value = 373
N6.C1.D0.R0.S11: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N0.C1.D0.R0.S09: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N2.C2.D0.R0.S15: Total Receive Enable Delay = 1306
N4.C1.D0.R1.S04: Rcv En Fine Value = 369
N6.C1.D0.R0.S12: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N0.C1.D0.R0.S10: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N2.C2.D0.R0.S16: Total Receive Enable Delay = 1325
N4.C1.D0.R1.S05: Rcv En Fine Value = 265
N6.C1.D0.R0.S13: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N0.C1.D0.R0.S11: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N2.C2.D0.R0.S17: Total Receive Enable Delay = 1241
N4.C1.D0.R1.S06: Rcv En Fine Value = 290
N6.C1.D0.R0.S14: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N0.C1.D0.R0.S12: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N2.C2.D0.R1: RcvEnFine: Initial RdCmd2RcvEnLatency = 10, Initial RdPtrOffsetRcvEn = 4
N4.C1.D0.R1.S07: Rcv En Fine Value = 310
N6.C1.D0.R0.S15: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N0.C1.D0.R0.S13: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N2.C2.D0.R1.S00: Rcv En Fine Value = 273
N4.C1.D0.R1.S08: Rcv En Fine Value = 357
N6.C1.D0.R0.S16: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N0.C1.D0.R0.S14: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N2.C2.D0.R1.S01: Rcv En Fine Value = 380
N4.C1.D0.R1.S09: Rcv En Fine Value = 318
N6.C1.D0.R0.S17: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N0.C1.D0.R0.S15: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N2.C2.D0.R1.S02: Rcv En Fine Value = 348
N4.C1.D0.R1.S10: Rcv En Fine Value = 300
N6.C1.D0.R0.S09: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N0.C1.D0.R0.S16: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N2.C2.D0.R1.S03: Rcv En Fine Value = 330
N4.C1.D0.R1.S11: Rcv En Fine Value = 268
N6.C1.D0.R0.S10: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N0.C1.D0.R0.S17: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N2.C2.D0.R1.S04: Rcv En Fine Value = 330
N4.C1.D0.R1.S12: Rcv En Fine Value = 375
N6.C1.D0.R0.S11: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N0.C1.D0.R0.S09: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N2.C2.D0.R1.S05: Rcv En Fine Value = 342
N4.C1.D0.R1.S13: Rcv En Fine Value = 368
N6.C1.D0.R0.S12: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N0.C1.D0.R0.S10: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N2.C2.D0.R1.S06: Rcv En Fine Value = 380
N4.C1.D0.R1.S14: Rcv En Fine Value = 266
N6.C1.D0.R0.S13: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N0.C1.D0.R0.S11: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N2.C2.D0.R1.S07: Rcv En Fine Value = 270
N4.C1.D0.R1.S15: Rcv En Fine Value = 292
N6.C1.D0.R0.S14: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N0.C1.D0.R0.S12: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N2.C2.D0.R1.S08: Rcv En Fine Value = 317
N4.C1.D0.R1.S16: Rcv En Fine Value = 310
N6.C1.D0.R0.S15: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N0.C1.D0.R0.S13: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N2.C2.D0.R1.S09: Rcv En Fine Value = 273
N4.C1.D0.R1.S17: Rcv En Fine Value = 357
N6.C1.D0.R0.S16: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N0.C1.D0.R0.S14: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N2.C2.D0.R1.S10: Rcv En Fine Value = 380
N4.C1.D0.R1: Starting preamble search lower nibbles
N6.C1.D0.R0.S17: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N0.C1.D0.R0.S15: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N2.C2.D0.R1.S11: Rcv En Fine Value = 348
N4.C1.D0.R1.S00: PI = 062, PtrOffset = 004
N6.C1.D0.R0.S09: Preamble found at Latency = 008
N0.C1.D0.R0.S16: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N2.C2.D0.R1.S12: Rcv En Fine Value = 330
N4.C1.D0.R1.S01: PI = 041, PtrOffset = 004
N6.C1.D0.R0.S10: Preamble found at Latency = 008
N0.C1.D0.R0.S17: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N2.C2.D0.R1.S13: Rcv En Fine Value = 329
N4.C1.D0.R1.S02: PI = 011, PtrOffset = 004
N6.C1.D0.R0.S11: Preamble found at Latency = 008
N0.C1.D0.R0.S09: Preamble found at Latency = 008
N2.C2.D0.R1.S14: Rcv En Fine Value = 339
N4.C1.D0.R1.S03: PI = 053, PtrOffset = 005
N6.C1.D0.R0.S14: Preamble found at Latency = 008
N0.C1.D0.R0.S10: Preamble found at Latency = 008
N2.C2.D0.R1.S15: Rcv En Fine Value = 375
N4.C1.D0.R1.S04: PI = 049, PtrOffset = 005
N6.C1.D0.R0.S15: Preamble found at Latency = 008
N0.C1.D0.R0.S11: Preamble found at Latency = 008
N2.C2.D0.R1.S16: Rcv En Fine Value = 270
N4.C1.D0.R1.S05: PI = 009, PtrOffset = 004
N6.C1.D0.R0.S16: Preamble found at Latency = 008
N0.C1.D0.R0.S14: Preamble found at Latency = 008
N2.C2.D0.R1.S17: Rcv En Fine Value = 313
N4.C1.D0.R1.S06: PI = 034, PtrOffset = 004
N6.C1.D0.R0.S09: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N0.C1.D0.R0.S15: Preamble found at Latency = 008
N2.C2.D0.R1: Starting preamble search lower nibbles
N4.C1.D0.R1.S07: PI = 054, PtrOffset = 004
N6.C1.D0.R0.S10: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N0.C1.D0.R0.S16: Preamble found at Latency = 008
N2.C2.D0.R1.S00: PI = 017, PtrOffset = 004
N4.C1.D0.R1.S08: PI = 037, PtrOffset = 005
N6.C1.D0.R0.S11: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N0.C1.D0.R0.S09: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N2.C2.D0.R1.S01: PI = 060, PtrOffset = 005
N4.C1.D0.R1.S00: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N6.C1.D0.R0.S12: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N0.C1.D0.R0.S10: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N2.C2.D0.R1.S02: PI = 028, PtrOffset = 005
N4.C1.D0.R1.S01: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N6.C1.D0.R0.S13: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N0.C1.D0.R0.S11: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N2.C2.D0.R1.S03: PI = 010, PtrOffset = 005
N4.C1.D0.R1.S02: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N6.C1.D0.R0.S14: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N0.C1.D0.R0.S12: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N2.C2.D0.R1.S04: PI = 010, PtrOffset = 005
N4.C1.D0.R1.S03: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N6.C1.D0.R0.S15: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N0.C1.D0.R0.S13: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N2.C2.D0.R1.S05: PI = 022, PtrOffset = 005
N4.C1.D0.R1.S04: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N6.C1.D0.R0.S16: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N0.C1.D0.R0.S14: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N2.C2.D0.R1.S06: PI = 060, PtrOffset = 005
N4.C1.D0.R1.S05: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N6.C1.D0.R0.S17: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N0.C1.D0.R0.S15: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N2.C2.D0.R1.S07: PI = 014, PtrOffset = 004
N4.C1.D0.R1.S06: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N6.C1.D0.R0.S12: Preamble found at Latency = 007
N0.C1.D0.R0.S16: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N2.C2.D0.R1.S08: PI = 061, PtrOffset = 004
N4.C1.D0.R1.S07: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N6.C1.D0.R0.S13: Preamble found at Latency = 007
N0.C1.D0.R0.S17: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N2.C2.D0.R1.S00: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N4.C1.D0.R1.S08: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N6.C1.D0.R0.S17: Preamble found at Latency = 007
N0.C1.D0.R0.S12: Preamble found at Latency = 007
N2.C2.D0.R1.S01: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N4.C1.D0.R1.S00: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N6.C1.D0.R0: Preamble found for all upper nibbles, adjusting Pi, Offset to center into preamble
N0.C1.D0.R0.S13: Preamble found at Latency = 007
N2.C2.D0.R1.S02: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N4.C1.D0.R1.S01: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N6.C1.D0.R0.S09: Total Receive Enable Delay = 1378
N0.C1.D0.R0.S17: Preamble found at Latency = 007
N2.C2.D0.R1.S03: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N4.C1.D0.R1.S02: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N6.C1.D0.R0.S10: Total Receive Enable Delay = 1359
N0.C1.D0.R0: Preamble found for all upper nibbles, adjusting Pi, Offset to center into preamble
N2.C2.D0.R1.S04: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N4.C1.D0.R1.S03: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N6.C1.D0.R0.S11: Total Receive Enable Delay = 1329
N0.C1.D0.R0.S09: Total Receive Enable Delay = 1374
N2.C2.D0.R1.S05: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N4.C1.D0.R1.S04: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N6.C1.D0.R0.S12: Total Receive Enable Delay = 1310
N0.C1.D0.R0.S10: Total Receive Enable Delay = 1353
N2.C2.D0.R1.S06: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N4.C1.D0.R1.S05: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N6.C1.D0.R0.S13: Total Receive Enable Delay = 1303
N0.C1.D0.R0.S11: Total Receive Enable Delay = 1325
N2.C2.D0.R1.S07: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N4.C1.D0.R1.S06: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N6.C1.D0.R0.S14: Total Receive Enable Delay = 1326
N0.C1.D0.R0.S12: Total Receive Enable Delay = 1306
N2.C2.D0.R1.S08: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N4.C1.D0.R1.S07: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N6.C1.D0.R0.S15: Total Receive Enable Delay = 1349
N0.C1.D0.R0.S13: Total Receive Enable Delay = 1296
N2.C2.D0.R1.S00: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N4.C1.D0.R1.S08: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N6.C1.D0.R0.S16: Total Receive Enable Delay = 1371
N0.C1.D0.R0.S14: Total Receive Enable Delay = 1320
N2.C2.D0.R1.S01: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N4.C1.D0.R1.S00: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N6.C1.D0.R0.S17: Total Receive Enable Delay = 1289
N0.C1.D0.R0.S15: Total Receive Enable Delay = 1345
N2.C2.D0.R1.S02: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N4.C1.D0.R1.S01: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N6.C1.D0.R1: RcvEnFine: Initial RdCmd2RcvEnLatency = 10, Initial RdPtrOffsetRcvEn = 4
N0.C1.D0.R0.S16: Total Receive Enable Delay = 1366
N2.C2.D0.R1.S03: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N4.C1.D0.R1.S02: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N6.C1.D0.R1.S00: Rcv En Fine Value = 324
N0.C1.D0.R0.S17: Total Receive Enable Delay = 1285
N2.C2.D0.R1.S04: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N4.C1.D0.R1.S03: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N6.C1.D0.R1.S01: Rcv En Fine Value = 303
N0.C1.D0.R1: RcvEnFine: Initial RdCmd2RcvEnLatency = 10, Initial RdPtrOffsetRcvEn = 4
N2.C2.D0.R1.S05: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N4.C1.D0.R1.S04: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N6.C1.D0.R1.S02: Rcv En Fine Value = 270
N0.C1.D0.R1.S00: Rcv En Fine Value = 320
N2.C2.D0.R1.S06: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N4.C1.D0.R1.S05: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N6.C1.D0.R1.S03: Rcv En Fine Value = 379
N0.C1.D0.R1.S01: Rcv En Fine Value = 298
N2.C2.D0.R1.S07: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N4.C1.D0.R1.S06: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N6.C1.D0.R1.S04: Rcv En Fine Value = 371
N0.C1.D0.R1.S02: Rcv En Fine Value = 265
N2.C2.D0.R1.S08: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N4.C1.D0.R1.S07: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N6.C1.D0.R1.S05: Rcv En Fine Value = 270
N0.C1.D0.R1.S03: Rcv En Fine Value = 376
N2.C2.D0.R1.S00: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N4.C1.D0.R1.S08: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N6.C1.D0.R1.S06: Rcv En Fine Value = 294
N0.C1.D0.R1.S04: Rcv En Fine Value = 368
N2.C2.D0.R1.S01: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N4.C1.D0.R1.S00: Preamble found at Latency = 008
N6.C1.D0.R1.S07: Rcv En Fine Value = 314
N0.C1.D0.R1.S05: Rcv En Fine Value = 265
N2.C2.D0.R1.S02: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N4.C1.D0.R1.S01: Preamble found at Latency = 008
N6.C1.D0.R1.S08: Rcv En Fine Value = 362
N0.C1.D0.R1.S06: Rcv En Fine Value = 288
N2.C2.D0.R1.S03: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N4.C1.D0.R1.S02: Preamble found at Latency = 008
N6.C1.D0.R1.S09: Rcv En Fine Value = 321
N0.C1.D0.R1.S07: Rcv En Fine Value = 313
N2.C2.D0.R1.S04: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N4.C1.D0.R1.S05: Preamble found at Latency = 008
N6.C1.D0.R1.S10: Rcv En Fine Value = 303
N0.C1.D0.R1.S08: Rcv En Fine Value = 356
N2.C2.D0.R1.S05: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N4.C1.D0.R1.S06: Preamble found at Latency = 008
N6.C1.D0.R1.S11: Rcv En Fine Value = 269
N0.C1.D0.R1.S09: Rcv En Fine Value = 318
N2.C2.D0.R1.S06: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N4.C1.D0.R1.S07: Preamble found at Latency = 008
N6.C1.D0.R1.S12: Rcv En Fine Value = 382
N0.C1.D0.R1.S10: Rcv En Fine Value = 298
N2.C2.D0.R1.S07: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N4.C1.D0.R1.S00: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N6.C1.D0.R1.S13: Rcv En Fine Value = 374
N0.C1.D0.R1.S11: Rcv En Fine Value = 269
N2.C2.D0.R1.S08: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N4.C1.D0.R1.S01: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N6.C1.D0.R1.S14: Rcv En Fine Value = 270
N0.C1.D0.R1.S12: Rcv En Fine Value = 377
N2.C2.D0.R1.S00: Preamble found at Latency = 008
N4.C1.D0.R1.S02: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N6.C1.D0.R1.S15: Rcv En Fine Value = 294
N0.C1.D0.R1.S13: Rcv En Fine Value = 369
N2.C2.D0.R1.S07: Preamble found at Latency = 008
N4.C1.D0.R1.S03: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N6.C1.D0.R1.S16: Rcv En Fine Value = 315
N0.C1.D0.R1.S14: Rcv En Fine Value = 267
N2.C2.D0.R1.S00: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N4.C1.D0.R1.S04: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N6.C1.D0.R1.S17: Rcv En Fine Value = 361
N0.C1.D0.R1.S15: Rcv En Fine Value = 290
N2.C2.D0.R1.S01: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N4.C1.D0.R1.S05: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N6.C1.D0.R1: Starting preamble search lower nibbles
N0.C1.D0.R1.S16: Rcv En Fine Value = 312
N2.C2.D0.R1.S02: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N4.C1.D0.R1.S06: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N6.C1.D0.R1.S00: PI = 004, PtrOffset = 005
N0.C1.D0.R1.S17: Rcv En Fine Value = 359
N2.C2.D0.R1.S03: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N4.C1.D0.R1.S07: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N6.C1.D0.R1.S01: PI = 047, PtrOffset = 004
N0.C1.D0.R1: Starting preamble search lower nibbles
N2.C2.D0.R1.S04: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N4.C1.D0.R1.S08: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N6.C1.D0.R1.S02: PI = 014, PtrOffset = 004
N0.C1.D0.R1.S00: PI = 000, PtrOffset = 005
N2.C2.D0.R1.S05: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N4.C1.D0.R1.S03: Preamble found at Latency = 007
N6.C1.D0.R1.S03: PI = 059, PtrOffset = 005
N0.C1.D0.R1.S01: PI = 042, PtrOffset = 004
N2.C2.D0.R1.S06: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N4.C1.D0.R1.S04: Preamble found at Latency = 007
N6.C1.D0.R1.S04: PI = 051, PtrOffset = 005
N0.C1.D0.R1.S02: PI = 009, PtrOffset = 004
N2.C2.D0.R1.S07: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N4.C1.D0.R1.S08: Preamble found at Latency = 007
N6.C1.D0.R1.S05: PI = 014, PtrOffset = 004
N0.C1.D0.R1.S03: PI = 056, PtrOffset = 005
N2.C2.D0.R1.S08: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N4.C1.D0.R1.S00: Total Receive Enable Delay = 1374
N6.C1.D0.R1.S06: PI = 038, PtrOffset = 004
N0.C1.D0.R1.S04: PI = 048, PtrOffset = 005
N2.C2.D0.R1.S01: Preamble found at Latency = 007
N4.C1.D0.R1.S01: Total Receive Enable Delay = 1353
N6.C1.D0.R1.S07: PI = 058, PtrOffset = 004
N0.C1.D0.R1.S05: PI = 009, PtrOffset = 004
N2.C2.D0.R1.S02: Preamble found at Latency = 007
N4.C1.D0.R1.S02: Total Receive Enable Delay = 1323
N6.C1.D0.R1.S08: PI = 042, PtrOffset = 005
N0.C1.D0.R1.S06: PI = 032, PtrOffset = 004
N2.C2.D0.R1.S03: Preamble found at Latency = 007
N4.C1.D0.R1.S03: Total Receive Enable Delay = 1301
N6.C1.D0.R1.S00: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N0.C1.D0.R1.S07: PI = 057, PtrOffset = 004
N2.C2.D0.R1.S04: Preamble found at Latency = 007
N4.C1.D0.R1.S04: Total Receive Enable Delay = 1297
N6.C1.D0.R1.S01: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N0.C1.D0.R1.S08: PI = 036, PtrOffset = 005
N2.C2.D0.R1.S05: Preamble found at Latency = 007
N4.C1.D0.R1.S05: Total Receive Enable Delay = 1321
N6.C1.D0.R1.S02: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N0.C1.D0.R1.S00: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N2.C2.D0.R1.S06: Preamble found at Latency = 007
N4.C1.D0.R1.S06: Total Receive Enable Delay = 1346
N6.C1.D0.R1.S03: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N0.C1.D0.R1.S01: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N2.C2.D0.R1.S08: Preamble found at Latency = 007
N4.C1.D0.R1.S07: Total Receive Enable Delay = 1366
N6.C1.D0.R1.S04: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N0.C1.D0.R1.S02: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N2.C2.D0.R1.S00: Total Receive Enable Delay = 1329
N4.C1.D0.R1.S08: Total Receive Enable Delay = 1285
N6.C1.D0.R1.S05: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N0.C1.D0.R1.S03: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N2.C2.D0.R1.S01: Total Receive Enable Delay = 1308
N4.C1.D0.R1: Starting preamble search upper nibbles
N6.C1.D0.R1.S06: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N0.C1.D0.R1.S04: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N2.C2.D0.R1.S02: Total Receive Enable Delay = 1276
N4.C1.D0.R1.S09: PI = 062, PtrOffset = 004
N6.C1.D0.R1.S07: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N0.C1.D0.R1.S05: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N2.C2.D0.R1.S03: Total Receive Enable Delay = 1258
N4.C1.D0.R1.S10: PI = 044, PtrOffset = 004
N6.C1.D0.R1.S08: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N0.C1.D0.R1.S06: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N2.C2.D0.R1.S04: Total Receive Enable Delay = 1258
N4.C1.D0.R1.S11: PI = 012, PtrOffset = 004
N6.C1.D0.R1.S00: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N0.C1.D0.R1.S07: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N2.C2.D0.R1.S05: Total Receive Enable Delay = 1270
N4.C1.D0.R1.S12: PI = 055, PtrOffset = 005
N6.C1.D0.R1.S01: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N0.C1.D0.R1.S08: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N2.C2.D0.R1.S06: Total Receive Enable Delay = 1308
N4.C1.D0.R1.S13: PI = 048, PtrOffset = 005
N6.C1.D0.R1.S02: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N0.C1.D0.R1.S00: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N2.C2.D0.R1.S07: Total Receive Enable Delay = 1326
N4.C1.D0.R1.S14: PI = 010, PtrOffset = 004
N6.C1.D0.R1.S03: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N0.C1.D0.R1.S01: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N2.C2.D0.R1.S08: Total Receive Enable Delay = 1245
N4.C1.D0.R1.S15: PI = 036, PtrOffset = 004
N6.C1.D0.R1.S04: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N0.C1.D0.R1.S02: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N2.C2.D0.R1: Starting preamble search upper nibbles
N4.C1.D0.R1.S16: PI = 054, PtrOffset = 004
N6.C1.D0.R1.S05: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N0.C1.D0.R1.S03: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N2.C2.D0.R1.S09: PI = 017, PtrOffset = 004
N4.C1.D0.R1.S17: PI = 037, PtrOffset = 005
N6.C1.D0.R1.S06: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N0.C1.D0.R1.S04: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N2.C2.D0.R1.S10: PI = 060, PtrOffset = 005
N4.C1.D0.R1.S09: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N6.C1.D0.R1.S07: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N0.C1.D0.R1.S05: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N2.C2.D0.R1.S11: PI = 028, PtrOffset = 005
N4.C1.D0.R1.S10: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N6.C1.D0.R1.S08: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N0.C1.D0.R1.S06: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N2.C2.D0.R1.S12: PI = 010, PtrOffset = 005
N4.C1.D0.R1.S11: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N6.C1.D0.R1.S00: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N0.C1.D0.R1.S07: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N2.C2.D0.R1.S13: PI = 009, PtrOffset = 005
N4.C1.D0.R1.S12: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N6.C1.D0.R1.S01: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N0.C1.D0.R1.S08: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N2.C2.D0.R1.S14: PI = 019, PtrOffset = 005
N4.C1.D0.R1.S13: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N6.C1.D0.R1.S02: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N0.C1.D0.R1.S00: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N2.C2.D0.R1.S15: PI = 055, PtrOffset = 005
N4.C1.D0.R1.S14: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N6.C1.D0.R1.S03: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N0.C1.D0.R1.S01: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N2.C2.D0.R1.S16: PI = 014, PtrOffset = 004
N4.C1.D0.R1.S15: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N6.C1.D0.R1.S04: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N0.C1.D0.R1.S02: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N2.C2.D0.R1.S17: PI = 057, PtrOffset = 004
N4.C1.D0.R1.S16: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N6.C1.D0.R1.S05: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N0.C1.D0.R1.S03: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N2.C2.D0.R1.S09: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N4.C1.D0.R1.S17: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N6.C1.D0.R1.S06: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N0.C1.D0.R1.S04: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N2.C2.D0.R1.S10: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N4.C1.D0.R1.S09: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N6.C1.D0.R1.S07: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N0.C1.D0.R1.S05: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N2.C2.D0.R1.S11: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N4.C1.D0.R1.S10: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N6.C1.D0.R1.S08: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N0.C1.D0.R1.S06: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N2.C2.D0.R1.S12: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N4.C1.D0.R1.S11: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N6.C1.D0.R1.S00: Preamble found at Latency = 008
N0.C1.D0.R1.S07: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N2.C2.D0.R1.S13: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N4.C1.D0.R1.S12: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N6.C1.D0.R1.S01: Preamble found at Latency = 008
N0.C1.D0.R1.S08: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N2.C2.D0.R1.S14: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N4.C1.D0.R1.S13: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N6.C1.D0.R1.S02: Preamble found at Latency = 008
N0.C1.D0.R1.S00: Preamble found at Latency = 008
N2.C2.D0.R1.S15: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N4.C1.D0.R1.S14: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N6.C1.D0.R1.S05: Preamble found at Latency = 008
N0.C1.D0.R1.S01: Preamble found at Latency = 008
N2.C2.D0.R1.S16: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N4.C1.D0.R1.S15: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N6.C1.D0.R1.S06: Preamble found at Latency = 008
N0.C1.D0.R1.S02: Preamble found at Latency = 008
N2.C2.D0.R1.S17: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N4.C1.D0.R1.S16: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N6.C1.D0.R1.S07: Preamble found at Latency = 008
N0.C1.D0.R1.S05: Preamble found at Latency = 008
N2.C2.D0.R1.S09: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N4.C1.D0.R1.S17: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N6.C1.D0.R1.S00: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N0.C1.D0.R1.S06: Preamble found at Latency = 008
N2.C2.D0.R1.S10: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N4.C1.D0.R1.S09: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N6.C1.D0.R1.S01: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N0.C1.D0.R1.S07: Preamble found at Latency = 008
N2.C2.D0.R1.S11: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N4.C1.D0.R1.S10: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N6.C1.D0.R1.S02: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N0.C1.D0.R1.S00: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N2.C2.D0.R1.S12: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N4.C1.D0.R1.S11: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N6.C1.D0.R1.S03: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N0.C1.D0.R1.S01: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N2.C2.D0.R1.S13: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N4.C1.D0.R1.S12: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N6.C1.D0.R1.S04: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N0.C1.D0.R1.S02: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N2.C2.D0.R1.S14: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N4.C1.D0.R1.S13: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N6.C1.D0.R1.S05: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N0.C1.D0.R1.S03: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N2.C2.D0.R1.S15: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N4.C1.D0.R1.S14: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N6.C1.D0.R1.S06: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N0.C1.D0.R1.S04: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N2.C2.D0.R1.S16: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N4.C1.D0.R1.S15: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N6.C1.D0.R1.S07: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N0.C1.D0.R1.S05: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N2.C2.D0.R1.S17: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N4.C1.D0.R1.S16: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N6.C1.D0.R1.S08: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N0.C1.D0.R1.S06: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N2.C2.D0.R1.S09: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N4.C1.D0.R1.S17: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N6.C1.D0.R1.S03: Preamble found at Latency = 007
N0.C1.D0.R1.S07: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N2.C2.D0.R1.S10: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N4.C1.D0.R1.S09: Preamble found at Latency = 008
N6.C1.D0.R1.S04: Preamble found at Latency = 007
N0.C1.D0.R1.S08: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N2.C2.D0.R1.S11: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N4.C1.D0.R1.S10: Preamble found at Latency = 008
N6.C1.D0.R1.S08: Preamble found at Latency = 007
N0.C1.D0.R1.S03: Preamble found at Latency = 007
N2.C2.D0.R1.S12: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N4.C1.D0.R1.S11: Preamble found at Latency = 008
N6.C1.D0.R1.S00: Total Receive Enable Delay = 1380
N0.C1.D0.R1.S04: Preamble found at Latency = 007
N2.C2.D0.R1.S13: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N4.C1.D0.R1.S14: Preamble found at Latency = 008
N6.C1.D0.R1.S01: Total Receive Enable Delay = 1359
N0.C1.D0.R1.S08: Preamble found at Latency = 007
N2.C2.D0.R1.S14: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N4.C1.D0.R1.S15: Preamble found at Latency = 008
N6.C1.D0.R1.S02: Total Receive Enable Delay = 1326
N0.C1.D0.R1.S00: Total Receive Enable Delay = 1376
N2.C2.D0.R1.S15: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N4.C1.D0.R1.S16: Preamble found at Latency = 008
N6.C1.D0.R1.S03: Total Receive Enable Delay = 1307
N0.C1.D0.R1.S01: Total Receive Enable Delay = 1354
N2.C2.D0.R1.S16: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N4.C1.D0.R1.S09: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N6.C1.D0.R1.S04: Total Receive Enable Delay = 1299
N0.C1.D0.R1.S02: Total Receive Enable Delay = 1321
N2.C2.D0.R1.S17: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N4.C1.D0.R1.S10: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N6.C1.D0.R1.S05: Total Receive Enable Delay = 1326
N0.C1.D0.R1.S03: Total Receive Enable Delay = 1304
N2.C2.D0.R1.S09: Preamble found at Latency = 008
N4.C1.D0.R1.S11: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N6.C1.D0.R1.S06: Total Receive Enable Delay = 1350
N0.C1.D0.R1.S04: Total Receive Enable Delay = 1296
N2.C2.D0.R1.S16: Preamble found at Latency = 008
N4.C1.D0.R1.S12: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N6.C1.D0.R1.S07: Total Receive Enable Delay = 1370
N0.C1.D0.R1.S05: Total Receive Enable Delay = 1321
N2.C2.D0.R1.S09: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N4.C1.D0.R1.S13: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N6.C1.D0.R1.S08: Total Receive Enable Delay = 1290
N0.C1.D0.R1.S06: Total Receive Enable Delay = 1344
N2.C2.D0.R1.S10: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N4.C1.D0.R1.S14: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N6.C1.D0.R1: Starting preamble search upper nibbles
N0.C1.D0.R1.S07: Total Receive Enable Delay = 1369
N2.C2.D0.R1.S11: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N4.C1.D0.R1.S15: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N6.C1.D0.R1.S09: PI = 001, PtrOffset = 005
N0.C1.D0.R1.S08: Total Receive Enable Delay = 1284
N2.C2.D0.R1.S12: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N4.C1.D0.R1.S16: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N6.C1.D0.R1.S10: PI = 047, PtrOffset = 004
N0.C1.D0.R1: Starting preamble search upper nibbles
N2.C2.D0.R1.S13: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N4.C1.D0.R1.S17: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N6.C1.D0.R1.S11: PI = 013, PtrOffset = 004
N0.C1.D0.R1.S09: PI = 062, PtrOffset = 004
N2.C2.D0.R1.S14: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N4.C1.D0.R1.S12: Preamble found at Latency = 007
N6.C1.D0.R1.S12: PI = 062, PtrOffset = 005
N0.C1.D0.R1.S10: PI = 042, PtrOffset = 004
N2.C2.D0.R1.S15: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N4.C1.D0.R1.S13: Preamble found at Latency = 007
N6.C1.D0.R1.S13: PI = 054, PtrOffset = 005
N0.C1.D0.R1.S11: PI = 013, PtrOffset = 004
N2.C2.D0.R1.S16: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N4.C1.D0.R1.S17: Preamble found at Latency = 007
N6.C1.D0.R1.S14: PI = 014, PtrOffset = 004
N0.C1.D0.R1.S12: PI = 057, PtrOffset = 005
N2.C2.D0.R1.S17: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N4.C1.D0.R1: Preamble found for all upper nibbles, adjusting Pi, Offset to center into preamble
N6.C1.D0.R1.S15: PI = 038, PtrOffset = 004
N0.C1.D0.R1.S13: PI = 049, PtrOffset = 005
N2.C2.D0.R1.S10: Preamble found at Latency = 007
N4.C1.D0.R1.S09: Total Receive Enable Delay = 1374
N6.C1.D0.R1.S16: PI = 059, PtrOffset = 004
N0.C1.D0.R1.S14: PI = 011, PtrOffset = 004
N2.C2.D0.R1.S11: Preamble found at Latency = 007
N4.C1.D0.R1.S10: Total Receive Enable Delay = 1356
N6.C1.D0.R1.S17: PI = 041, PtrOffset = 005
N0.C1.D0.R1.S15: PI = 034, PtrOffset = 004
N2.C2.D0.R1.S12: Preamble found at Latency = 007
N4.C1.D0.R1.S11: Total Receive Enable Delay = 1324
N6.C1.D0.R1.S09: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N0.C1.D0.R1.S16: PI = 056, PtrOffset = 004
N2.C2.D0.R1.S13: Preamble found at Latency = 007
N4.C1.D0.R1.S12: Total Receive Enable Delay = 1303
N6.C1.D0.R1.S10: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N0.C1.D0.R1.S17: PI = 039, PtrOffset = 005
N2.C2.D0.R1.S14: Preamble found at Latency = 007
N4.C1.D0.R1.S13: Total Receive Enable Delay = 1296
N6.C1.D0.R1.S11: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N0.C1.D0.R1.S09: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N2.C2.D0.R1.S15: Preamble found at Latency = 007
N4.C1.D0.R1.S14: Total Receive Enable Delay = 1322
N6.C1.D0.R1.S12: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N0.C1.D0.R1.S10: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N2.C2.D0.R1.S17: Preamble found at Latency = 007
N4.C1.D0.R1.S15: Total Receive Enable Delay = 1348
N6.C1.D0.R1.S13: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N0.C1.D0.R1.S11: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N2.C2.D0.R1: Preamble found for all upper nibbles, adjusting Pi, Offset to center into preamble
N4.C1.D0.R1.S16: Total Receive Enable Delay = 1366
N6.C1.D0.R1.S14: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N0.C1.D0.R1.S12: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N2.C2.D0.R1.S09: Total Receive Enable Delay = 1329
N4.C1.D0.R1.S17: Total Receive Enable Delay = 1285
N6.C1.D0.R1.S15: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N0.C1.D0.R1.S13: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N2.C2.D0.R1.S10: Total Receive Enable Delay = 1308
N4.C1.D1.R0: RcvEnFine: Initial RdCmd2RcvEnLatency = 10, Initial RdPtrOffsetRcvEn = 4
N6.C1.D0.R1.S16: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N0.C1.D0.R1.S14: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N2.C2.D0.R1.S11: Total Receive Enable Delay = 1276
N4.C1.D1.R0.S00: Rcv En Fine Value = 300
N6.C1.D0.R1.S17: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N0.C1.D0.R1.S15: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N2.C2.D0.R1.S12: Total Receive Enable Delay = 1258
N4.C1.D1.R0.S01: Rcv En Fine Value = 276
N6.C1.D0.R1.S09: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N0.C1.D0.R1.S16: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N2.C2.D0.R1.S13: Total Receive Enable Delay = 1257
N4.C1.D1.R0.S02: Rcv En Fine Value = 376
N6.C1.D0.R1.S10: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N0.C1.D0.R1.S17: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N2.C2.D0.R1.S14: Total Receive Enable Delay = 1267
N4.C1.D1.R0.S03: Rcv En Fine Value = 356
N6.C1.D0.R1.S11: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N0.C1.D0.R1.S09: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N2.C2.D0.R1.S15: Total Receive Enable Delay = 1303
N4.C1.D1.R0.S04: Rcv En Fine Value = 348
N6.C1.D0.R1.S12: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N0.C1.D0.R1.S10: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N2.C2.D0.R1.S16: Total Receive Enable Delay = 1326
N4.C1.D1.R0.S05: Rcv En Fine Value = 375
N6.C1.D0.R1.S13: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N0.C1.D0.R1.S11: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N2.C2.D0.R1.S17: Total Receive Enable Delay = 1241
N4.C1.D1.R0.S06: Rcv En Fine Value = 272
N6.C1.D0.R1.S14: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N0.C1.D0.R1.S12: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N2.C2.D1.R0: RcvEnFine: Initial RdCmd2RcvEnLatency = 10, Initial RdPtrOffsetRcvEn = 4
N4.C1.D1.R0.S07: Rcv En Fine Value = 290
N6.C1.D0.R1.S15: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N0.C1.D0.R1.S13: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N2.C2.D1.R0.S00: Rcv En Fine Value = 258
N4.C1.D1.R0.S08: Rcv En Fine Value = 335
N6.C1.D0.R1.S16: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N0.C1.D0.R1.S14: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N2.C2.D1.R0.S01: Rcv En Fine Value = 364
N4.C1.D1.R0.S09: Rcv En Fine Value = 300
N6.C1.D0.R1.S17: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N0.C1.D0.R1.S15: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N2.C2.D1.R0.S02: Rcv En Fine Value = 333
N4.C1.D1.R0.S10: Rcv En Fine Value = 280
N6.C1.D0.R1.S09: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N0.C1.D0.R1.S16: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N2.C2.D1.R0.S03: Rcv En Fine Value = 315
N4.C1.D1.R0.S11: Rcv En Fine Value = 383
N6.C1.D0.R1.S10: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N0.C1.D0.R1.S17: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N2.C2.D1.R0.S04: Rcv En Fine Value = 316
N4.C1.D1.R0.S12: Rcv En Fine Value = 359
N6.C1.D0.R1.S11: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N0.C1.D0.R1.S09: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N2.C2.D1.R0.S05: Rcv En Fine Value = 327
N4.C1.D1.R0.S13: Rcv En Fine Value = 348
N6.C1.D0.R1.S12: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N0.C1.D0.R1.S10: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N2.C2.D1.R0.S06: Rcv En Fine Value = 365
N4.C1.D1.R0.S14: Rcv En Fine Value = 374
N6.C1.D0.R1.S13: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N0.C1.D0.R1.S11: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N2.C2.D1.R0.S07: Rcv En Fine Value = 382
N4.C1.D1.R0.S15: Rcv En Fine Value = 273
N6.C1.D0.R1.S14: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N0.C1.D0.R1.S12: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N2.C2.D1.R0.S08: Rcv En Fine Value = 303
N4.C1.D1.R0.S16: Rcv En Fine Value = 293
N6.C1.D0.R1.S15: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N0.C1.D0.R1.S13: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N2.C2.D1.R0.S09: Rcv En Fine Value = 259
N4.C1.D1.R0.S17: Rcv En Fine Value = 337
N6.C1.D0.R1.S16: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N0.C1.D0.R1.S14: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N2.C2.D1.R0.S10: Rcv En Fine Value = 365
N4.C1.D1.R0: Starting preamble search lower nibbles
N6.C1.D0.R1.S17: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N0.C1.D0.R1.S15: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N2.C2.D1.R0.S11: Rcv En Fine Value = 333
N4.C1.D1.R0.S00: PI = 044, PtrOffset = 004
N6.C1.D0.R1.S09: Preamble found at Latency = 008
N0.C1.D0.R1.S16: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N2.C2.D1.R0.S12: Rcv En Fine Value = 313
N4.C1.D1.R0.S01: PI = 020, PtrOffset = 004
N6.C1.D0.R1.S10: Preamble found at Latency = 008
N0.C1.D0.R1.S17: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N2.C2.D1.R0.S13: Rcv En Fine Value = 315
N4.C1.D1.R0.S02: PI = 056, PtrOffset = 005
N6.C1.D0.R1.S11: Preamble found at Latency = 008
N0.C1.D0.R1.S09: Preamble found at Latency = 008
N2.C2.D1.R0.S14: Rcv En Fine Value = 325
N4.C1.D1.R0.S03: PI = 036, PtrOffset = 005
N6.C1.D0.R1.S14: Preamble found at Latency = 008
N0.C1.D0.R1.S10: Preamble found at Latency = 008
N2.C2.D1.R0.S15: Rcv En Fine Value = 362
N4.C1.D1.R0.S04: PI = 028, PtrOffset = 005
N6.C1.D0.R1.S15: Preamble found at Latency = 008
N0.C1.D0.R1.S11: Preamble found at Latency = 008
N2.C2.D1.R0.S16: Rcv En Fine Value = 380
N4.C1.D1.R0.S05: PI = 055, PtrOffset = 005
N6.C1.D0.R1.S16: Preamble found at Latency = 008
N0.C1.D0.R1.S14: Preamble found at Latency = 008
N2.C2.D1.R0.S17: Rcv En Fine Value = 298
N4.C1.D1.R0.S06: PI = 016, PtrOffset = 004
N6.C1.D0.R1.S09: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N0.C1.D0.R1.S15: Preamble found at Latency = 008
N2.C2.D1.R0: Starting preamble search lower nibbles
N4.C1.D1.R0.S07: PI = 034, PtrOffset = 004
N6.C1.D0.R1.S10: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N0.C1.D0.R1.S16: Preamble found at Latency = 008
N2.C2.D1.R0.S00: PI = 002, PtrOffset = 004
N4.C1.D1.R0.S08: PI = 015, PtrOffset = 005
N6.C1.D0.R1.S11: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N0.C1.D0.R1.S09: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N2.C2.D1.R0.S01: PI = 044, PtrOffset = 005
N4.C1.D1.R0.S00: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N6.C1.D0.R1.S12: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N0.C1.D0.R1.S10: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N2.C2.D1.R0.S02: PI = 013, PtrOffset = 005
N4.C1.D1.R0.S01: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N6.C1.D0.R1.S13: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N0.C1.D0.R1.S11: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N2.C2.D1.R0.S03: PI = 059, PtrOffset = 004
N4.C1.D1.R0.S02: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N6.C1.D0.R1.S14: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N0.C1.D0.R1.S12: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N2.C2.D1.R0.S04: PI = 060, PtrOffset = 004
N4.C1.D1.R0.S03: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N6.C1.D0.R1.S15: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N0.C1.D0.R1.S13: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N2.C2.D1.R0.S05: PI = 007, PtrOffset = 005
N4.C1.D1.R0.S04: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N6.C1.D0.R1.S16: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N0.C1.D0.R1.S14: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N2.C2.D1.R0.S06: PI = 045, PtrOffset = 005
N4.C1.D1.R0.S05: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N6.C1.D0.R1.S17: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N0.C1.D0.R1.S15: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N2.C2.D1.R0.S07: PI = 062, PtrOffset = 005
N4.C1.D1.R0.S06: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N6.C1.D0.R1.S12: Preamble found at Latency = 007
N0.C1.D0.R1.S16: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N2.C2.D1.R0.S08: PI = 047, PtrOffset = 004
N4.C1.D1.R0.S07: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N6.C1.D0.R1.S13: Preamble found at Latency = 007
N0.C1.D0.R1.S17: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N2.C2.D1.R0.S00: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N4.C1.D1.R0.S08: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N6.C1.D0.R1.S17: Preamble found at Latency = 007
N0.C1.D0.R1.S12: Preamble found at Latency = 007
N2.C2.D1.R0.S01: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N4.C1.D1.R0.S00: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N6.C1.D0.R1: Preamble found for all upper nibbles, adjusting Pi, Offset to center into preamble
N0.C1.D0.R1.S13: Preamble found at Latency = 007
N2.C2.D1.R0.S02: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N4.C1.D1.R0.S01: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N6.C1.D0.R1.S09: Total Receive Enable Delay = 1377
N0.C1.D0.R1.S17: Preamble found at Latency = 007
N2.C2.D1.R0.S03: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N4.C1.D1.R0.S02: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N6.C1.D0.R1.S10: Total Receive Enable Delay = 1359
N0.C1.D0.R1: Preamble found for all upper nibbles, adjusting Pi, Offset to center into preamble
N2.C2.D1.R0.S04: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N4.C1.D1.R0.S03: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N6.C1.D0.R1.S11: Total Receive Enable Delay = 1325
N0.C1.D0.R1.S09: Total Receive Enable Delay = 1374
N2.C2.D1.R0.S05: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N4.C1.D1.R0.S04: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N6.C1.D0.R1.S12: Total Receive Enable Delay = 1310
N0.C1.D0.R1.S10: Total Receive Enable Delay = 1354
N2.C2.D1.R0.S06: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N4.C1.D1.R0.S05: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N6.C1.D0.R1.S13: Total Receive Enable Delay = 1302
N0.C1.D0.R1.S11: Total Receive Enable Delay = 1325
N2.C2.D1.R0.S07: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N4.C1.D1.R0.S06: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N6.C1.D0.R1.S14: Total Receive Enable Delay = 1326
N0.C1.D0.R1.S12: Total Receive Enable Delay = 1305
N2.C2.D1.R0.S08: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N4.C1.D1.R0.S07: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N6.C1.D0.R1.S15: Total Receive Enable Delay = 1350
N0.C1.D0.R1.S13: Total Receive Enable Delay = 1297
N2.C2.D1.R0.S00: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N4.C1.D1.R0.S08: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N6.C1.D0.R1.S16: Total Receive Enable Delay = 1371
N0.C1.D0.R1.S14: Total Receive Enable Delay = 1323
N2.C2.D1.R0.S01: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N4.C1.D1.R0.S00: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N6.C1.D0.R1.S17: Total Receive Enable Delay = 1289
N0.C1.D0.R1.S15: Total Receive Enable Delay = 1346
N2.C2.D1.R0.S02: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N4.C1.D1.R0.S01: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N6.C1.D1.R0: RcvEnFine: Initial RdCmd2RcvEnLatency = 10, Initial RdPtrOffsetRcvEn = 4
N0.C1.D0.R1.S16: Total Receive Enable Delay = 1368
N2.C2.D1.R0.S03: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N4.C1.D1.R0.S02: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N6.C1.D1.R0.S00: Rcv En Fine Value = 309
N0.C1.D0.R1.S17: Total Receive Enable Delay = 1287
N2.C2.D1.R0.S04: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N4.C1.D1.R0.S03: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N6.C1.D1.R0.S01: Rcv En Fine Value = 288
N0.C1.D1.R0: RcvEnFine: Initial RdCmd2RcvEnLatency = 10, Initial RdPtrOffsetRcvEn = 4
N2.C2.D1.R0.S05: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N4.C1.D1.R0.S04: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N6.C1.D1.R0.S02: Rcv En Fine Value = 257
N0.C1.D1.R0.S00: Rcv En Fine Value = 297
N2.C2.D1.R0.S06: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N4.C1.D1.R0.S05: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N6.C1.D1.R0.S03: Rcv En Fine Value = 364
N0.C1.D1.R0.S01: Rcv En Fine Value = 276
N2.C2.D1.R0.S07: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N4.C1.D1.R0.S06: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N6.C1.D1.R0.S04: Rcv En Fine Value = 360
N0.C1.D1.R0.S02: Rcv En Fine Value = 374
N2.C2.D1.R0.S08: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N4.C1.D1.R0.S07: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N6.C1.D1.R0.S05: Rcv En Fine Value = 256
N0.C1.D1.R0.S03: Rcv En Fine Value = 356
N2.C2.D1.R0.S00: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N4.C1.D1.R0.S08: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N6.C1.D1.R0.S06: Rcv En Fine Value = 279
N0.C1.D1.R0.S04: Rcv En Fine Value = 348
N2.C2.D1.R0.S01: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N4.C1.D1.R0.S00: Preamble found at Latency = 008
N6.C1.D1.R0.S07: Rcv En Fine Value = 298
N0.C1.D1.R0.S05: Rcv En Fine Value = 375
N2.C2.D1.R0.S02: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N4.C1.D1.R0.S01: Preamble found at Latency = 008
N6.C1.D1.R0.S08: Rcv En Fine Value = 349
N0.C1.D1.R0.S06: Rcv En Fine Value = 268
N2.C2.D1.R0.S03: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N4.C1.D1.R0.S06: Preamble found at Latency = 008
N6.C1.D1.R0.S09: Rcv En Fine Value = 309
N0.C1.D1.R0.S07: Rcv En Fine Value = 290
N2.C2.D1.R0.S04: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N4.C1.D1.R0.S07: Preamble found at Latency = 008
N6.C1.D1.R0.S10: Rcv En Fine Value = 289
N0.C1.D1.R0.S08: Rcv En Fine Value = 334
N2.C2.D1.R0.S05: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N4.C1.D1.R0.S00: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N6.C1.D1.R0.S11: Rcv En Fine Value = 258
N0.C1.D1.R0.S09: Rcv En Fine Value = 297
N2.C2.D1.R0.S06: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N4.C1.D1.R0.S01: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N6.C1.D1.R0.S12: Rcv En Fine Value = 367
N0.C1.D1.R0.S10: Rcv En Fine Value = 274
N2.C2.D1.R0.S07: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N4.C1.D1.R0.S02: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N6.C1.D1.R0.S13: Rcv En Fine Value = 358
N0.C1.D1.R0.S11: Rcv En Fine Value = 376
N2.C2.D1.R0.S08: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N4.C1.D1.R0.S03: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N6.C1.D1.R0.S14: Rcv En Fine Value = 256
N0.C1.D1.R0.S12: Rcv En Fine Value = 353
N2.C2.D1.R0.S00: Preamble found at Latency = 008
N4.C1.D1.R0.S04: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N6.C1.D1.R0.S15: Rcv En Fine Value = 278
N0.C1.D1.R0.S13: Rcv En Fine Value = 350
N2.C2.D1.R0.S00: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N4.C1.D1.R0.S05: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N6.C1.D1.R0.S16: Rcv En Fine Value = 300
N0.C1.D1.R0.S14: Rcv En Fine Value = 375
N2.C2.D1.R0.S01: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N4.C1.D1.R0.S06: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N6.C1.D1.R0.S17: Rcv En Fine Value = 345
N0.C1.D1.R0.S15: Rcv En Fine Value = 267
N2.C2.D1.R0.S02: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N4.C1.D1.R0.S07: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N6.C1.D1.R0: Starting preamble search lower nibbles
N0.C1.D1.R0.S16: Rcv En Fine Value = 291
N2.C2.D1.R0.S03: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N4.C1.D1.R0.S08: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N6.C1.D1.R0.S00: PI = 053, PtrOffset = 004
N0.C1.D1.R0.S17: Rcv En Fine Value = 338
N2.C2.D1.R0.S04: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N4.C1.D1.R0.S02: Preamble found at Latency = 007
N6.C1.D1.R0.S01: PI = 032, PtrOffset = 004
N0.C1.D1.R0: Starting preamble search lower nibbles
N2.C2.D1.R0.S05: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N4.C1.D1.R0.S03: Preamble found at Latency = 007
N6.C1.D1.R0.S02: PI = 001, PtrOffset = 004
N0.C1.D1.R0.S00: PI = 041, PtrOffset = 004
N2.C2.D1.R0.S06: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N4.C1.D1.R0.S04: Preamble found at Latency = 007
N6.C1.D1.R0.S03: PI = 044, PtrOffset = 005
N0.C1.D1.R0.S01: PI = 020, PtrOffset = 004
N2.C2.D1.R0.S07: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N4.C1.D1.R0.S05: Preamble found at Latency = 007
N6.C1.D1.R0.S04: PI = 040, PtrOffset = 005
N0.C1.D1.R0.S02: PI = 054, PtrOffset = 005
N2.C2.D1.R0.S08: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N4.C1.D1.R0.S08: Preamble found at Latency = 007
N6.C1.D1.R0.S05: PI = 000, PtrOffset = 004
N0.C1.D1.R0.S03: PI = 036, PtrOffset = 005
N2.C2.D1.R0.S01: Preamble found at Latency = 007
N4.C1.D1.R0.S00: Total Receive Enable Delay = 1356
N6.C1.D1.R0.S06: PI = 023, PtrOffset = 004
N0.C1.D1.R0.S04: PI = 028, PtrOffset = 005
N2.C2.D1.R0.S02: Preamble found at Latency = 007
N4.C1.D1.R0.S01: Total Receive Enable Delay = 1332
N6.C1.D1.R0.S07: PI = 042, PtrOffset = 004
N0.C1.D1.R0.S05: PI = 055, PtrOffset = 005
N2.C2.D1.R0.S03: Preamble found at Latency = 007
N4.C1.D1.R0.S02: Total Receive Enable Delay = 1304
N6.C1.D1.R0.S08: PI = 029, PtrOffset = 005
N0.C1.D1.R0.S06: PI = 012, PtrOffset = 004
N2.C2.D1.R0.S04: Preamble found at Latency = 007
N4.C1.D1.R0.S03: Total Receive Enable Delay = 1284
N6.C1.D1.R0.S00: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N0.C1.D1.R0.S07: PI = 034, PtrOffset = 004
N2.C2.D1.R0.S05: Preamble found at Latency = 007
N4.C1.D1.R0.S04: Total Receive Enable Delay = 1276
N6.C1.D1.R0.S01: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N0.C1.D1.R0.S08: PI = 014, PtrOffset = 005
N2.C2.D1.R0.S06: Preamble found at Latency = 007
N4.C1.D1.R0.S05: Total Receive Enable Delay = 1303
N6.C1.D1.R0.S02: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N0.C1.D1.R0.S00: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N2.C2.D1.R0.S07: Preamble found at Latency = 007
N4.C1.D1.R0.S06: Total Receive Enable Delay = 1328
N6.C1.D1.R0.S03: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N0.C1.D1.R0.S01: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N2.C2.D1.R0.S08: Preamble found at Latency = 007
N4.C1.D1.R0.S07: Total Receive Enable Delay = 1346
N6.C1.D1.R0.S04: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N0.C1.D1.R0.S02: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N2.C2.D1.R0.S00: Total Receive Enable Delay = 1314
N4.C1.D1.R0.S08: Total Receive Enable Delay = 1263
N6.C1.D1.R0.S05: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N0.C1.D1.R0.S03: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N2.C2.D1.R0.S01: Total Receive Enable Delay = 1292
N4.C1.D1.R0: Starting preamble search upper nibbles
N6.C1.D1.R0.S06: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N0.C1.D1.R0.S04: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N2.C2.D1.R0.S02: Total Receive Enable Delay = 1261
N4.C1.D1.R0.S09: PI = 044, PtrOffset = 004
N6.C1.D1.R0.S07: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N0.C1.D1.R0.S05: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N2.C2.D1.R0.S03: Total Receive Enable Delay = 1243
N4.C1.D1.R0.S10: PI = 024, PtrOffset = 004
N6.C1.D1.R0.S08: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N0.C1.D1.R0.S06: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N2.C2.D1.R0.S04: Total Receive Enable Delay = 1244
N4.C1.D1.R0.S11: PI = 063, PtrOffset = 005
N6.C1.D1.R0.S00: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N0.C1.D1.R0.S07: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N2.C2.D1.R0.S05: Total Receive Enable Delay = 1255
N4.C1.D1.R0.S12: PI = 039, PtrOffset = 005
N6.C1.D1.R0.S01: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N0.C1.D1.R0.S08: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N2.C2.D1.R0.S06: Total Receive Enable Delay = 1293
N4.C1.D1.R0.S13: PI = 028, PtrOffset = 005
N6.C1.D1.R0.S02: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N0.C1.D1.R0.S00: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N2.C2.D1.R0.S07: Total Receive Enable Delay = 1310
N4.C1.D1.R0.S14: PI = 054, PtrOffset = 005
N6.C1.D1.R0.S03: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N0.C1.D1.R0.S01: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N2.C2.D1.R0.S08: Total Receive Enable Delay = 1231
N4.C1.D1.R0.S15: PI = 017, PtrOffset = 004
N6.C1.D1.R0.S04: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N0.C1.D1.R0.S02: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N2.C2.D1.R0: Starting preamble search upper nibbles
N4.C1.D1.R0.S16: PI = 037, PtrOffset = 004
N6.C1.D1.R0.S05: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N0.C1.D1.R0.S03: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N2.C2.D1.R0.S09: PI = 003, PtrOffset = 004
N4.C1.D1.R0.S17: PI = 017, PtrOffset = 005
N6.C1.D1.R0.S06: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N0.C1.D1.R0.S04: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N2.C2.D1.R0.S10: PI = 045, PtrOffset = 005
N4.C1.D1.R0.S09: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N6.C1.D1.R0.S07: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N0.C1.D1.R0.S05: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N2.C2.D1.R0.S11: PI = 013, PtrOffset = 005
N4.C1.D1.R0.S10: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N6.C1.D1.R0.S08: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N0.C1.D1.R0.S06: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N2.C2.D1.R0.S12: PI = 057, PtrOffset = 004
N4.C1.D1.R0.S11: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N6.C1.D1.R0.S00: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N0.C1.D1.R0.S07: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N2.C2.D1.R0.S13: PI = 059, PtrOffset = 004
N4.C1.D1.R0.S12: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N6.C1.D1.R0.S01: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N0.C1.D1.R0.S08: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N2.C2.D1.R0.S14: PI = 005, PtrOffset = 005
N4.C1.D1.R0.S13: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N6.C1.D1.R0.S02: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N0.C1.D1.R0.S00: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N2.C2.D1.R0.S15: PI = 042, PtrOffset = 005
N4.C1.D1.R0.S14: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N6.C1.D1.R0.S03: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N0.C1.D1.R0.S01: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N2.C2.D1.R0.S16: PI = 060, PtrOffset = 005
N4.C1.D1.R0.S15: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N6.C1.D1.R0.S04: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N0.C1.D1.R0.S02: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N2.C2.D1.R0.S17: PI = 042, PtrOffset = 004
N4.C1.D1.R0.S16: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N6.C1.D1.R0.S05: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N0.C1.D1.R0.S03: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N2.C2.D1.R0.S09: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N4.C1.D1.R0.S17: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N6.C1.D1.R0.S06: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N0.C1.D1.R0.S04: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N2.C2.D1.R0.S10: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N4.C1.D1.R0.S09: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N6.C1.D1.R0.S07: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N0.C1.D1.R0.S05: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N2.C2.D1.R0.S11: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N4.C1.D1.R0.S10: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N6.C1.D1.R0.S08: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N0.C1.D1.R0.S06: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N2.C2.D1.R0.S12: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N4.C1.D1.R0.S11: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N6.C1.D1.R0.S00: Preamble found at Latency = 008
N0.C1.D1.R0.S07: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N2.C2.D1.R0.S13: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N4.C1.D1.R0.S12: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N6.C1.D1.R0.S01: Preamble found at Latency = 008
N0.C1.D1.R0.S08: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N2.C2.D1.R0.S14: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N4.C1.D1.R0.S13: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N6.C1.D1.R0.S02: Preamble found at Latency = 008
N0.C1.D1.R0.S00: Preamble found at Latency = 008
N2.C2.D1.R0.S15: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N4.C1.D1.R0.S14: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N6.C1.D1.R0.S05: Preamble found at Latency = 008
N0.C1.D1.R0.S01: Preamble found at Latency = 008
N2.C2.D1.R0.S16: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N4.C1.D1.R0.S15: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N6.C1.D1.R0.S06: Preamble found at Latency = 008
N0.C1.D1.R0.S06: Preamble found at Latency = 008
N2.C2.D1.R0.S17: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N4.C1.D1.R0.S16: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N6.C1.D1.R0.S07: Preamble found at Latency = 008
N0.C1.D1.R0.S07: Preamble found at Latency = 008
N2.C2.D1.R0.S09: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N4.C1.D1.R0.S17: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N6.C1.D1.R0.S00: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N0.C1.D1.R0.S00: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N2.C2.D1.R0.S10: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N4.C1.D1.R0.S09: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N6.C1.D1.R0.S01: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N0.C1.D1.R0.S01: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N2.C2.D1.R0.S11: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N4.C1.D1.R0.S10: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N6.C1.D1.R0.S02: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N0.C1.D1.R0.S02: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N2.C2.D1.R0.S12: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N4.C1.D1.R0.S11: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N6.C1.D1.R0.S03: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N0.C1.D1.R0.S03: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N2.C2.D1.R0.S13: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N4.C1.D1.R0.S12: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N6.C1.D1.R0.S04: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N0.C1.D1.R0.S04: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N2.C2.D1.R0.S14: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N4.C1.D1.R0.S13: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N6.C1.D1.R0.S05: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N0.C1.D1.R0.S05: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N2.C2.D1.R0.S15: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N4.C1.D1.R0.S14: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N6.C1.D1.R0.S06: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N0.C1.D1.R0.S06: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N2.C2.D1.R0.S16: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N4.C1.D1.R0.S15: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N6.C1.D1.R0.S07: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N0.C1.D1.R0.S07: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N2.C2.D1.R0.S17: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N4.C1.D1.R0.S16: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N6.C1.D1.R0.S08: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N0.C1.D1.R0.S08: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N2.C2.D1.R0.S09: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N4.C1.D1.R0.S17: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N6.C1.D1.R0.S03: Preamble found at Latency = 007
N0.C1.D1.R0.S02: Preamble found at Latency = 007
N2.C2.D1.R0.S10: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N4.C1.D1.R0.S09: Preamble found at Latency = 008
N6.C1.D1.R0.S04: Preamble found at Latency = 007
N0.C1.D1.R0.S03: Preamble found at Latency = 007
N2.C2.D1.R0.S11: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N4.C1.D1.R0.S10: Preamble found at Latency = 008
N6.C1.D1.R0.S08: Preamble found at Latency = 007
N0.C1.D1.R0.S04: Preamble found at Latency = 007
N2.C2.D1.R0.S12: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N4.C1.D1.R0.S15: Preamble found at Latency = 008
N6.C1.D1.R0.S00: Total Receive Enable Delay = 1365
N0.C1.D1.R0.S05: Preamble found at Latency = 007
N2.C2.D1.R0.S13: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N4.C1.D1.R0.S16: Preamble found at Latency = 008
N6.C1.D1.R0.S01: Total Receive Enable Delay = 1344
N0.C1.D1.R0.S08: Preamble found at Latency = 007
N2.C2.D1.R0.S14: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N4.C1.D1.R0.S09: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N6.C1.D1.R0.S02: Total Receive Enable Delay = 1313
N0.C1.D1.R0.S00: Total Receive Enable Delay = 1353
N2.C2.D1.R0.S15: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N4.C1.D1.R0.S10: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N6.C1.D1.R0.S03: Total Receive Enable Delay = 1292
N0.C1.D1.R0.S01: Total Receive Enable Delay = 1332
N2.C2.D1.R0.S16: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N4.C1.D1.R0.S11: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N6.C1.D1.R0.S04: Total Receive Enable Delay = 1288
N0.C1.D1.R0.S02: Total Receive Enable Delay = 1302
N2.C2.D1.R0.S17: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N4.C1.D1.R0.S12: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N6.C1.D1.R0.S05: Total Receive Enable Delay = 1312
N0.C1.D1.R0.S03: Total Receive Enable Delay = 1284
N2.C2.D1.R0.S09: Preamble found at Latency = 008
N4.C1.D1.R0.S13: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N6.C1.D1.R0.S06: Total Receive Enable Delay = 1335
N0.C1.D1.R0.S04: Total Receive Enable Delay = 1276
N2.C2.D1.R0.S09: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N4.C1.D1.R0.S14: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N6.C1.D1.R0.S07: Total Receive Enable Delay = 1354
N0.C1.D1.R0.S05: Total Receive Enable Delay = 1303
N2.C2.D1.R0.S10: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N4.C1.D1.R0.S15: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N6.C1.D1.R0.S08: Total Receive Enable Delay = 1277
N0.C1.D1.R0.S06: Total Receive Enable Delay = 1324
N2.C2.D1.R0.S11: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N4.C1.D1.R0.S16: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N6.C1.D1.R0: Starting preamble search upper nibbles
N0.C1.D1.R0.S07: Total Receive Enable Delay = 1346
N2.C2.D1.R0.S12: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N4.C1.D1.R0.S17: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N6.C1.D1.R0.S09: PI = 053, PtrOffset = 004
N0.C1.D1.R0.S08: Total Receive Enable Delay = 1262
N2.C2.D1.R0.S13: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N4.C1.D1.R0.S11: Preamble found at Latency = 007
N6.C1.D1.R0.S10: PI = 033, PtrOffset = 004
N0.C1.D1.R0: Starting preamble search upper nibbles
N2.C2.D1.R0.S14: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N4.C1.D1.R0.S12: Preamble found at Latency = 007
N6.C1.D1.R0.S11: PI = 002, PtrOffset = 004
N0.C1.D1.R0.S09: PI = 041, PtrOffset = 004
N2.C2.D1.R0.S15: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N4.C1.D1.R0.S13: Preamble found at Latency = 007
N6.C1.D1.R0.S12: PI = 047, PtrOffset = 005
N0.C1.D1.R0.S10: PI = 018, PtrOffset = 004
N2.C2.D1.R0.S16: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N4.C1.D1.R0.S14: Preamble found at Latency = 007
N6.C1.D1.R0.S13: PI = 038, PtrOffset = 005
N0.C1.D1.R0.S11: PI = 056, PtrOffset = 005
N2.C2.D1.R0.S17: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N4.C1.D1.R0.S17: Preamble found at Latency = 007
N6.C1.D1.R0.S14: PI = 000, PtrOffset = 004
N0.C1.D1.R0.S12: PI = 033, PtrOffset = 005
N2.C2.D1.R0.S10: Preamble found at Latency = 007
N4.C1.D1.R0: Preamble found for all upper nibbles, adjusting Pi, Offset to center into preamble
N6.C1.D1.R0.S15: PI = 022, PtrOffset = 004
N0.C1.D1.R0.S13: PI = 030, PtrOffset = 005
N2.C2.D1.R0.S11: Preamble found at Latency = 007
N4.C1.D1.R0.S09: Total Receive Enable Delay = 1356
N6.C1.D1.R0.S16: PI = 044, PtrOffset = 004
N0.C1.D1.R0.S14: PI = 055, PtrOffset = 005
N2.C2.D1.R0.S12: Preamble found at Latency = 007
N4.C1.D1.R0.S10: Total Receive Enable Delay = 1336
N6.C1.D1.R0.S17: PI = 025, PtrOffset = 005
N0.C1.D1.R0.S15: PI = 011, PtrOffset = 004
N2.C2.D1.R0.S13: Preamble found at Latency = 007
N4.C1.D1.R0.S11: Total Receive Enable Delay = 1311
N6.C1.D1.R0.S09: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N0.C1.D1.R0.S16: PI = 035, PtrOffset = 004
N2.C2.D1.R0.S14: Preamble found at Latency = 007
N4.C1.D1.R0.S12: Total Receive Enable Delay = 1287
N6.C1.D1.R0.S10: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N0.C1.D1.R0.S17: PI = 018, PtrOffset = 005
N2.C2.D1.R0.S15: Preamble found at Latency = 007
N4.C1.D1.R0.S13: Total Receive Enable Delay = 1276
N6.C1.D1.R0.S11: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N0.C1.D1.R0.S09: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N2.C2.D1.R0.S16: Preamble found at Latency = 007
N4.C1.D1.R0.S14: Total Receive Enable Delay = 1302
N6.C1.D1.R0.S12: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N0.C1.D1.R0.S10: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N2.C2.D1.R0.S17: Preamble found at Latency = 007
N4.C1.D1.R0.S15: Total Receive Enable Delay = 1329
N6.C1.D1.R0.S13: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N0.C1.D1.R0.S11: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N2.C2.D1.R0: Preamble found for all upper nibbles, adjusting Pi, Offset to center into preamble
N4.C1.D1.R0.S16: Total Receive Enable Delay = 1349
N6.C1.D1.R0.S14: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N0.C1.D1.R0.S12: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N2.C2.D1.R0.S09: Total Receive Enable Delay = 1315
N4.C1.D1.R0.S17: Total Receive Enable Delay = 1265
N6.C1.D1.R0.S15: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N0.C1.D1.R0.S13: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N2.C2.D1.R0.S10: Total Receive Enable Delay = 1293
N4.C1.D1.R1: RcvEnFine: Initial RdCmd2RcvEnLatency = 10, Initial RdPtrOffsetRcvEn = 4
N6.C1.D1.R0.S16: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N0.C1.D1.R0.S14: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N2.C2.D1.R0.S11: Total Receive Enable Delay = 1261
N4.C1.D1.R1.S00: Rcv En Fine Value = 299
N6.C1.D1.R0.S17: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N0.C1.D1.R0.S15: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N2.C2.D1.R0.S12: Total Receive Enable Delay = 1241
N4.C1.D1.R1.S01: Rcv En Fine Value = 278
N6.C1.D1.R0.S09: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N0.C1.D1.R0.S16: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N2.C2.D1.R0.S13: Total Receive Enable Delay = 1243
N4.C1.D1.R1.S02: Rcv En Fine Value = 375
N6.C1.D1.R0.S10: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N0.C1.D1.R0.S17: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N2.C2.D1.R0.S14: Total Receive Enable Delay = 1253
N4.C1.D1.R1.S03: Rcv En Fine Value = 355
N6.C1.D1.R0.S11: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N0.C1.D1.R0.S09: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N2.C2.D1.R0.S15: Total Receive Enable Delay = 1290
N4.C1.D1.R1.S04: Rcv En Fine Value = 349
N6.C1.D1.R0.S12: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N0.C1.D1.R0.S10: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N2.C2.D1.R0.S16: Total Receive Enable Delay = 1308
N4.C1.D1.R1.S05: Rcv En Fine Value = 373
N6.C1.D1.R0.S13: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N0.C1.D1.R0.S11: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N2.C2.D1.R0.S17: Total Receive Enable Delay = 1226
N4.C1.D1.R1.S06: Rcv En Fine Value = 270
N6.C1.D1.R0.S14: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N0.C1.D1.R0.S12: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N2.C2.D1.R1: RcvEnFine: Initial RdCmd2RcvEnLatency = 10, Initial RdPtrOffsetRcvEn = 4
N4.C1.D1.R1.S07: Rcv En Fine Value = 289
N6.C1.D1.R0.S15: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N0.C1.D1.R0.S13: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N2.C2.D1.R1.S00: Rcv En Fine Value = 260
N4.C1.D1.R1.S08: Rcv En Fine Value = 337
N6.C1.D1.R0.S16: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N0.C1.D1.R0.S14: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N2.C2.D1.R1.S01: Rcv En Fine Value = 365
N4.C1.D1.R1.S09: Rcv En Fine Value = 299
N6.C1.D1.R0.S17: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N0.C1.D1.R0.S15: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N2.C2.D1.R1.S02: Rcv En Fine Value = 332
N4.C1.D1.R1.S10: Rcv En Fine Value = 280
N6.C1.D1.R0.S09: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N0.C1.D1.R0.S16: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N2.C2.D1.R1.S03: Rcv En Fine Value = 313
N4.C1.D1.R1.S11: Rcv En Fine Value = 377
N6.C1.D1.R0.S10: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N0.C1.D1.R0.S17: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N2.C2.D1.R1.S04: Rcv En Fine Value = 316
N4.C1.D1.R1.S12: Rcv En Fine Value = 359
N6.C1.D1.R0.S11: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N0.C1.D1.R0.S09: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N2.C2.D1.R1.S05: Rcv En Fine Value = 327
N4.C1.D1.R1.S13: Rcv En Fine Value = 347
N6.C1.D1.R0.S12: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N0.C1.D1.R0.S10: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N2.C2.D1.R1.S06: Rcv En Fine Value = 365
N4.C1.D1.R1.S14: Rcv En Fine Value = 372
N6.C1.D1.R0.S13: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N0.C1.D1.R0.S11: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N2.C2.D1.R1.S07: Rcv En Fine Value = 381
N4.C1.D1.R1.S15: Rcv En Fine Value = 273
N6.C1.D1.R0.S14: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N0.C1.D1.R0.S12: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N2.C2.D1.R1.S08: Rcv En Fine Value = 302
N4.C1.D1.R1.S16: Rcv En Fine Value = 293
N6.C1.D1.R0.S15: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N0.C1.D1.R0.S13: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N2.C2.D1.R1.S09: Rcv En Fine Value = 259
N4.C1.D1.R1.S17: Rcv En Fine Value = 338
N6.C1.D1.R0.S16: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N0.C1.D1.R0.S14: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N2.C2.D1.R1.S10: Rcv En Fine Value = 364
N4.C1.D1.R1: Starting preamble search lower nibbles
N6.C1.D1.R0.S17: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N0.C1.D1.R0.S15: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N2.C2.D1.R1.S11: Rcv En Fine Value = 332
N4.C1.D1.R1.S00: PI = 043, PtrOffset = 004
N6.C1.D1.R0.S09: Preamble found at Latency = 008
N0.C1.D1.R0.S16: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N2.C2.D1.R1.S12: Rcv En Fine Value = 315
N4.C1.D1.R1.S01: PI = 022, PtrOffset = 004
N6.C1.D1.R0.S10: Preamble found at Latency = 008
N0.C1.D1.R0.S17: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N2.C2.D1.R1.S13: Rcv En Fine Value = 316
N4.C1.D1.R1.S02: PI = 055, PtrOffset = 005
N6.C1.D1.R0.S11: Preamble found at Latency = 008
N0.C1.D1.R0.S09: Preamble found at Latency = 008
N2.C2.D1.R1.S14: Rcv En Fine Value = 323
N4.C1.D1.R1.S03: PI = 035, PtrOffset = 005
N6.C1.D1.R0.S14: Preamble found at Latency = 008
N0.C1.D1.R0.S10: Preamble found at Latency = 008
N2.C2.D1.R1.S15: Rcv En Fine Value = 362
N4.C1.D1.R1.S04: PI = 029, PtrOffset = 005
N6.C1.D1.R0.S15: Preamble found at Latency = 008
N0.C1.D1.R0.S15: Preamble found at Latency = 008
N2.C2.D1.R1.S16: Rcv En Fine Value = 382
N4.C1.D1.R1.S05: PI = 053, PtrOffset = 005
N6.C1.D1.R0.S16: Preamble found at Latency = 008
N0.C1.D1.R0.S16: Preamble found at Latency = 008
N2.C2.D1.R1.S17: Rcv En Fine Value = 300
N4.C1.D1.R1.S06: PI = 014, PtrOffset = 004
N6.C1.D1.R0.S09: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N0.C1.D1.R0.S09: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N2.C2.D1.R1: Starting preamble search lower nibbles
N4.C1.D1.R1.S07: PI = 033, PtrOffset = 004
N6.C1.D1.R0.S10: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N0.C1.D1.R0.S10: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N2.C2.D1.R1.S00: PI = 004, PtrOffset = 004
N4.C1.D1.R1.S08: PI = 017, PtrOffset = 005
N6.C1.D1.R0.S11: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N0.C1.D1.R0.S11: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N2.C2.D1.R1.S01: PI = 045, PtrOffset = 005
N4.C1.D1.R1.S00: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N6.C1.D1.R0.S12: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N0.C1.D1.R0.S12: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N2.C2.D1.R1.S02: PI = 012, PtrOffset = 005
N4.C1.D1.R1.S01: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N6.C1.D1.R0.S13: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N0.C1.D1.R0.S13: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N2.C2.D1.R1.S03: PI = 057, PtrOffset = 004
N4.C1.D1.R1.S02: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N6.C1.D1.R0.S14: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N0.C1.D1.R0.S14: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N2.C2.D1.R1.S04: PI = 060, PtrOffset = 004
N4.C1.D1.R1.S03: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N6.C1.D1.R0.S15: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N0.C1.D1.R0.S15: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N2.C2.D1.R1.S05: PI = 007, PtrOffset = 005
N4.C1.D1.R1.S04: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N6.C1.D1.R0.S16: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N0.C1.D1.R0.S16: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N2.C2.D1.R1.S06: PI = 045, PtrOffset = 005
N4.C1.D1.R1.S05: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N6.C1.D1.R0.S17: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N0.C1.D1.R0.S17: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N2.C2.D1.R1.S07: PI = 061, PtrOffset = 005
N4.C1.D1.R1.S06: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N6.C1.D1.R0.S12: Preamble found at Latency = 007
N0.C1.D1.R0.S11: Preamble found at Latency = 007
N2.C2.D1.R1.S08: PI = 046, PtrOffset = 004
N4.C1.D1.R1.S07: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N6.C1.D1.R0.S13: Preamble found at Latency = 007
N0.C1.D1.R0.S12: Preamble found at Latency = 007
N2.C2.D1.R1.S00: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N4.C1.D1.R1.S08: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N6.C1.D1.R0.S17: Preamble found at Latency = 007
N0.C1.D1.R0.S13: Preamble found at Latency = 007
N2.C2.D1.R1.S01: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N4.C1.D1.R1.S00: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N6.C1.D1.R0: Preamble found for all upper nibbles, adjusting Pi, Offset to center into preamble
N0.C1.D1.R0.S14: Preamble found at Latency = 007
N2.C2.D1.R1.S02: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N4.C1.D1.R1.S01: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N6.C1.D1.R0.S09: Total Receive Enable Delay = 1365
N0.C1.D1.R0.S17: Preamble found at Latency = 007
N2.C2.D1.R1.S03: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N4.C1.D1.R1.S02: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N6.C1.D1.R0.S10: Total Receive Enable Delay = 1345
N0.C1.D1.R0: Preamble found for all upper nibbles, adjusting Pi, Offset to center into preamble
N2.C2.D1.R1.S04: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N4.C1.D1.R1.S03: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N6.C1.D1.R0.S11: Total Receive Enable Delay = 1314
N0.C1.D1.R0.S09: Total Receive Enable Delay = 1353
N2.C2.D1.R1.S05: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N4.C1.D1.R1.S04: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N6.C1.D1.R0.S12: Total Receive Enable Delay = 1295
N0.C1.D1.R0.S10: Total Receive Enable Delay = 1330
N2.C2.D1.R1.S06: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N4.C1.D1.R1.S05: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N6.C1.D1.R0.S13: Total Receive Enable Delay = 1286
N0.C1.D1.R0.S11: Total Receive Enable Delay = 1304
N2.C2.D1.R1.S07: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N4.C1.D1.R1.S06: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N6.C1.D1.R0.S14: Total Receive Enable Delay = 1312
N0.C1.D1.R0.S12: Total Receive Enable Delay = 1281
N2.C2.D1.R1.S08: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N4.C1.D1.R1.S07: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N6.C1.D1.R0.S15: Total Receive Enable Delay = 1334
N0.C1.D1.R0.S13: Total Receive Enable Delay = 1278
N2.C2.D1.R1.S00: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N4.C1.D1.R1.S08: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N6.C1.D1.R0.S16: Total Receive Enable Delay = 1356
N0.C1.D1.R0.S14: Total Receive Enable Delay = 1303
N2.C2.D1.R1.S01: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N4.C1.D1.R1.S00: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N6.C1.D1.R0.S17: Total Receive Enable Delay = 1273
N0.C1.D1.R0.S15: Total Receive Enable Delay = 1323
N2.C2.D1.R1.S02: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N4.C1.D1.R1.S01: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N6.C1.D1.R1: RcvEnFine: Initial RdCmd2RcvEnLatency = 10, Initial RdPtrOffsetRcvEn = 4
N0.C1.D1.R0.S16: Total Receive Enable Delay = 1347
N2.C2.D1.R1.S03: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N4.C1.D1.R1.S02: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N6.C1.D1.R1.S00: Rcv En Fine Value = 311
N0.C1.D1.R0.S17: Total Receive Enable Delay = 1266
N2.C2.D1.R1.S04: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N4.C1.D1.R1.S03: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N6.C1.D1.R1.S01: Rcv En Fine Value = 287
N0.C1.D1.R1: RcvEnFine: Initial RdCmd2RcvEnLatency = 10, Initial RdPtrOffsetRcvEn = 4
N2.C2.D1.R1.S05: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N4.C1.D1.R1.S04: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N6.C1.D1.R1.S02: Rcv En Fine Value = 256
N0.C1.D1.R1.S00: Rcv En Fine Value = 299
N2.C2.D1.R1.S06: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N4.C1.D1.R1.S05: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N6.C1.D1.R1.S03: Rcv En Fine Value = 362
N0.C1.D1.R1.S01: Rcv En Fine Value = 274
N2.C2.D1.R1.S07: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N4.C1.D1.R1.S06: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N6.C1.D1.R1.S04: Rcv En Fine Value = 359
N0.C1.D1.R1.S02: Rcv En Fine Value = 375
N2.C2.D1.R1.S08: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N4.C1.D1.R1.S07: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N6.C1.D1.R1.S05: Rcv En Fine Value = 382
N0.C1.D1.R1.S03: Rcv En Fine Value = 356
N2.C2.D1.R1.S00: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N4.C1.D1.R1.S08: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N6.C1.D1.R1.S06: Rcv En Fine Value = 278
N0.C1.D1.R1.S04: Rcv En Fine Value = 345
N2.C2.D1.R1.S01: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N4.C1.D1.R1.S00: Preamble found at Latency = 008
N6.C1.D1.R1.S07: Rcv En Fine Value = 298
N0.C1.D1.R1.S05: Rcv En Fine Value = 373
N2.C2.D1.R1.S02: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N4.C1.D1.R1.S01: Preamble found at Latency = 008
N6.C1.D1.R1.S08: Rcv En Fine Value = 347
N0.C1.D1.R1.S06: Rcv En Fine Value = 269
N2.C2.D1.R1.S03: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N4.C1.D1.R1.S06: Preamble found at Latency = 008
N6.C1.D1.R1.S09: Rcv En Fine Value = 307
N0.C1.D1.R1.S07: Rcv En Fine Value = 287
N2.C2.D1.R1.S04: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N4.C1.D1.R1.S07: Preamble found at Latency = 008
N6.C1.D1.R1.S10: Rcv En Fine Value = 289
N0.C1.D1.R1.S08: Rcv En Fine Value = 336
N2.C2.D1.R1.S05: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N4.C1.D1.R1.S00: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N6.C1.D1.R1.S11: Rcv En Fine Value = 256
N0.C1.D1.R1.S09: Rcv En Fine Value = 295
N2.C2.D1.R1.S06: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N4.C1.D1.R1.S01: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N6.C1.D1.R1.S12: Rcv En Fine Value = 368
N0.C1.D1.R1.S10: Rcv En Fine Value = 276
N2.C2.D1.R1.S07: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N4.C1.D1.R1.S02: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N6.C1.D1.R1.S13: Rcv En Fine Value = 359
N0.C1.D1.R1.S11: Rcv En Fine Value = 374
N2.C2.D1.R1.S08: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N4.C1.D1.R1.S03: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N6.C1.D1.R1.S14: Rcv En Fine Value = 383
N0.C1.D1.R1.S12: Rcv En Fine Value = 355
N2.C2.D1.R1.S00: Preamble found at Latency = 008
N4.C1.D1.R1.S04: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N6.C1.D1.R1.S15: Rcv En Fine Value = 278
N0.C1.D1.R1.S13: Rcv En Fine Value = 349
N2.C2.D1.R1.S00: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N4.C1.D1.R1.S05: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N6.C1.D1.R1.S16: Rcv En Fine Value = 302
N0.C1.D1.R1.S14: Rcv En Fine Value = 376
N2.C2.D1.R1.S01: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N4.C1.D1.R1.S06: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N6.C1.D1.R1.S17: Rcv En Fine Value = 347
N0.C1.D1.R1.S15: Rcv En Fine Value = 269
N2.C2.D1.R1.S02: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N4.C1.D1.R1.S07: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N6.C1.D1.R1: Starting preamble search lower nibbles
N0.C1.D1.R1.S16: Rcv En Fine Value = 288
N2.C2.D1.R1.S03: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N4.C1.D1.R1.S08: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N6.C1.D1.R1.S00: PI = 055, PtrOffset = 004
N0.C1.D1.R1.S17: Rcv En Fine Value = 336
N2.C2.D1.R1.S04: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N4.C1.D1.R1.S02: Preamble found at Latency = 007
N6.C1.D1.R1.S01: PI = 031, PtrOffset = 004
N0.C1.D1.R1: Starting preamble search lower nibbles
N2.C2.D1.R1.S05: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N4.C1.D1.R1.S03: Preamble found at Latency = 007
N6.C1.D1.R1.S02: PI = 000, PtrOffset = 004
N0.C1.D1.R1.S00: PI = 043, PtrOffset = 004
N2.C2.D1.R1.S06: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N4.C1.D1.R1.S04: Preamble found at Latency = 007
N6.C1.D1.R1.S03: PI = 042, PtrOffset = 005
N0.C1.D1.R1.S01: PI = 018, PtrOffset = 004
N2.C2.D1.R1.S07: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N4.C1.D1.R1.S05: Preamble found at Latency = 007
N6.C1.D1.R1.S04: PI = 039, PtrOffset = 005
N0.C1.D1.R1.S02: PI = 055, PtrOffset = 005
N2.C2.D1.R1.S08: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N4.C1.D1.R1.S08: Preamble found at Latency = 007
N6.C1.D1.R1.S05: PI = 062, PtrOffset = 005
N0.C1.D1.R1.S03: PI = 036, PtrOffset = 005
N2.C2.D1.R1.S01: Preamble found at Latency = 007
N4.C1.D1.R1.S00: Total Receive Enable Delay = 1355
N6.C1.D1.R1.S06: PI = 022, PtrOffset = 004
N0.C1.D1.R1.S04: PI = 025, PtrOffset = 005
N2.C2.D1.R1.S02: Preamble found at Latency = 007
N4.C1.D1.R1.S01: Total Receive Enable Delay = 1334
N6.C1.D1.R1.S07: PI = 042, PtrOffset = 004
N0.C1.D1.R1.S05: PI = 053, PtrOffset = 005
N2.C2.D1.R1.S03: Preamble found at Latency = 007
N4.C1.D1.R1.S02: Total Receive Enable Delay = 1303
N6.C1.D1.R1.S08: PI = 027, PtrOffset = 005
N0.C1.D1.R1.S06: PI = 013, PtrOffset = 004
N2.C2.D1.R1.S04: Preamble found at Latency = 007
N4.C1.D1.R1.S03: Total Receive Enable Delay = 1283
N6.C1.D1.R1.S00: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N0.C1.D1.R1.S07: PI = 031, PtrOffset = 004
N2.C2.D1.R1.S05: Preamble found at Latency = 007
N4.C1.D1.R1.S04: Total Receive Enable Delay = 1277
N6.C1.D1.R1.S01: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N0.C1.D1.R1.S08: PI = 016, PtrOffset = 005
N2.C2.D1.R1.S06: Preamble found at Latency = 007
N4.C1.D1.R1.S05: Total Receive Enable Delay = 1301
N6.C1.D1.R1.S02: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N0.C1.D1.R1.S00: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N2.C2.D1.R1.S07: Preamble found at Latency = 007
N4.C1.D1.R1.S06: Total Receive Enable Delay = 1326
N6.C1.D1.R1.S03: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N0.C1.D1.R1.S01: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N2.C2.D1.R1.S08: Preamble found at Latency = 007
N4.C1.D1.R1.S07: Total Receive Enable Delay = 1345
N6.C1.D1.R1.S04: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N0.C1.D1.R1.S02: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N2.C2.D1.R1.S00: Total Receive Enable Delay = 1316
N4.C1.D1.R1.S08: Total Receive Enable Delay = 1265
N6.C1.D1.R1.S05: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N0.C1.D1.R1.S03: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N2.C2.D1.R1.S01: Total Receive Enable Delay = 1293
N4.C1.D1.R1: Starting preamble search upper nibbles
N6.C1.D1.R1.S06: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N0.C1.D1.R1.S04: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N2.C2.D1.R1.S02: Total Receive Enable Delay = 1260
N4.C1.D1.R1.S09: PI = 043, PtrOffset = 004
N6.C1.D1.R1.S07: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N0.C1.D1.R1.S05: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N2.C2.D1.R1.S03: Total Receive Enable Delay = 1241
N4.C1.D1.R1.S10: PI = 024, PtrOffset = 004
N6.C1.D1.R1.S08: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N0.C1.D1.R1.S06: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N2.C2.D1.R1.S04: Total Receive Enable Delay = 1244
N4.C1.D1.R1.S11: PI = 057, PtrOffset = 005
N6.C1.D1.R1.S00: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N0.C1.D1.R1.S07: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N2.C2.D1.R1.S05: Total Receive Enable Delay = 1255
N4.C1.D1.R1.S12: PI = 039, PtrOffset = 005
N6.C1.D1.R1.S01: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N0.C1.D1.R1.S08: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N2.C2.D1.R1.S06: Total Receive Enable Delay = 1293
N4.C1.D1.R1.S13: PI = 027, PtrOffset = 005
N6.C1.D1.R1.S02: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N0.C1.D1.R1.S00: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N2.C2.D1.R1.S07: Total Receive Enable Delay = 1309
N4.C1.D1.R1.S14: PI = 052, PtrOffset = 005
N6.C1.D1.R1.S03: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N0.C1.D1.R1.S01: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N2.C2.D1.R1.S08: Total Receive Enable Delay = 1230
N4.C1.D1.R1.S15: PI = 017, PtrOffset = 004
N6.C1.D1.R1.S04: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N0.C1.D1.R1.S02: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N2.C2.D1.R1: Starting preamble search upper nibbles
N4.C1.D1.R1.S16: PI = 037, PtrOffset = 004
N6.C1.D1.R1.S05: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N0.C1.D1.R1.S03: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N2.C2.D1.R1.S09: PI = 003, PtrOffset = 004
N4.C1.D1.R1.S17: PI = 018, PtrOffset = 005
N6.C1.D1.R1.S06: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N0.C1.D1.R1.S04: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N2.C2.D1.R1.S10: PI = 044, PtrOffset = 005
N4.C1.D1.R1.S09: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N6.C1.D1.R1.S07: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N0.C1.D1.R1.S05: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N2.C2.D1.R1.S11: PI = 012, PtrOffset = 005
N4.C1.D1.R1.S10: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N6.C1.D1.R1.S08: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N0.C1.D1.R1.S06: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N2.C2.D1.R1.S12: PI = 059, PtrOffset = 004
N4.C1.D1.R1.S11: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N6.C1.D1.R1.S00: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N0.C1.D1.R1.S07: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N2.C2.D1.R1.S13: PI = 060, PtrOffset = 004
N4.C1.D1.R1.S12: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N6.C1.D1.R1.S01: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N0.C1.D1.R1.S08: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N2.C2.D1.R1.S14: PI = 003, PtrOffset = 005
N4.C1.D1.R1.S13: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N6.C1.D1.R1.S02: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N0.C1.D1.R1.S00: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N2.C2.D1.R1.S15: PI = 042, PtrOffset = 005
N4.C1.D1.R1.S14: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N6.C1.D1.R1.S03: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N0.C1.D1.R1.S01: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N2.C2.D1.R1.S16: PI = 062, PtrOffset = 005
N4.C1.D1.R1.S15: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N6.C1.D1.R1.S04: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N0.C1.D1.R1.S02: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N2.C2.D1.R1.S17: PI = 044, PtrOffset = 004
N4.C1.D1.R1.S16: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N6.C1.D1.R1.S05: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N0.C1.D1.R1.S03: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N2.C2.D1.R1.S09: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N4.C1.D1.R1.S17: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N6.C1.D1.R1.S06: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N0.C1.D1.R1.S04: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N2.C2.D1.R1.S10: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N4.C1.D1.R1.S09: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N6.C1.D1.R1.S07: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N0.C1.D1.R1.S05: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N2.C2.D1.R1.S11: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N4.C1.D1.R1.S10: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N6.C1.D1.R1.S08: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N0.C1.D1.R1.S06: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N2.C2.D1.R1.S12: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N4.C1.D1.R1.S11: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N6.C1.D1.R1.S00: Preamble found at Latency = 008
N0.C1.D1.R1.S07: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N2.C2.D1.R1.S13: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N4.C1.D1.R1.S12: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N6.C1.D1.R1.S01: Preamble found at Latency = 008
N0.C1.D1.R1.S08: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N2.C2.D1.R1.S14: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N4.C1.D1.R1.S13: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N6.C1.D1.R1.S02: Preamble found at Latency = 008
N0.C1.D1.R1.S00: Preamble found at Latency = 008
N2.C2.D1.R1.S15: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N4.C1.D1.R1.S14: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N6.C1.D1.R1.S06: Preamble found at Latency = 008
N0.C1.D1.R1.S01: Preamble found at Latency = 008
N2.C2.D1.R1.S16: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N4.C1.D1.R1.S15: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N6.C1.D1.R1.S07: Preamble found at Latency = 008
N0.C1.D1.R1.S06: Preamble found at Latency = 008
N2.C2.D1.R1.S17: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N4.C1.D1.R1.S16: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N6.C1.D1.R1.S00: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N0.C1.D1.R1.S07: Preamble found at Latency = 008
N2.C2.D1.R1.S09: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N4.C1.D1.R1.S17: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N6.C1.D1.R1.S01: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N0.C1.D1.R1.S00: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N2.C2.D1.R1.S10: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N4.C1.D1.R1.S09: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N6.C1.D1.R1.S02: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N0.C1.D1.R1.S01: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N2.C2.D1.R1.S11: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N4.C1.D1.R1.S10: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N6.C1.D1.R1.S03: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N0.C1.D1.R1.S02: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N2.C2.D1.R1.S12: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N4.C1.D1.R1.S11: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N6.C1.D1.R1.S04: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N0.C1.D1.R1.S03: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N2.C2.D1.R1.S13: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N4.C1.D1.R1.S12: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N6.C1.D1.R1.S05: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N0.C1.D1.R1.S04: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N2.C2.D1.R1.S14: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N4.C1.D1.R1.S13: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N6.C1.D1.R1.S06: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N0.C1.D1.R1.S05: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N2.C2.D1.R1.S15: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N4.C1.D1.R1.S14: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N6.C1.D1.R1.S07: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N0.C1.D1.R1.S06: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N2.C2.D1.R1.S16: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N4.C1.D1.R1.S15: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N6.C1.D1.R1.S08: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N0.C1.D1.R1.S07: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N2.C2.D1.R1.S17: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N4.C1.D1.R1.S16: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N6.C1.D1.R1.S03: Preamble found at Latency = 007
N0.C1.D1.R1.S08: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N2.C2.D1.R1.S09: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N4.C1.D1.R1.S17: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N6.C1.D1.R1.S04: Preamble found at Latency = 007
N0.C1.D1.R1.S02: Preamble found at Latency = 007
N2.C2.D1.R1.S10: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N4.C1.D1.R1.S09: Preamble found at Latency = 008
N6.C1.D1.R1.S05: Preamble found at Latency = 007
N0.C1.D1.R1.S03: Preamble found at Latency = 007
N2.C2.D1.R1.S11: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N4.C1.D1.R1.S10: Preamble found at Latency = 008
N6.C1.D1.R1.S08: Preamble found at Latency = 007
N0.C1.D1.R1.S04: Preamble found at Latency = 007
N2.C2.D1.R1.S12: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N4.C1.D1.R1.S15: Preamble found at Latency = 008
N6.C1.D1.R1.S00: Total Receive Enable Delay = 1367
N0.C1.D1.R1.S05: Preamble found at Latency = 007
N2.C2.D1.R1.S13: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N4.C1.D1.R1.S16: Preamble found at Latency = 008
N6.C1.D1.R1.S01: Total Receive Enable Delay = 1343
N0.C1.D1.R1.S08: Preamble found at Latency = 007
N2.C2.D1.R1.S14: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N4.C1.D1.R1.S09: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N6.C1.D1.R1.S02: Total Receive Enable Delay = 1312
N0.C1.D1.R1.S00: Total Receive Enable Delay = 1355
N2.C2.D1.R1.S15: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N4.C1.D1.R1.S10: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N6.C1.D1.R1.S03: Total Receive Enable Delay = 1290
N0.C1.D1.R1.S01: Total Receive Enable Delay = 1330
N2.C2.D1.R1.S16: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N4.C1.D1.R1.S11: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N6.C1.D1.R1.S04: Total Receive Enable Delay = 1287
N0.C1.D1.R1.S02: Total Receive Enable Delay = 1303
N2.C2.D1.R1.S17: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N4.C1.D1.R1.S12: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N6.C1.D1.R1.S05: Total Receive Enable Delay = 1310
N0.C1.D1.R1.S03: Total Receive Enable Delay = 1284
N2.C2.D1.R1.S09: Preamble found at Latency = 008
N4.C1.D1.R1.S13: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N6.C1.D1.R1.S06: Total Receive Enable Delay = 1334
N0.C1.D1.R1.S04: Total Receive Enable Delay = 1273
N2.C2.D1.R1.S09: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N4.C1.D1.R1.S14: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N6.C1.D1.R1.S07: Total Receive Enable Delay = 1354
N0.C1.D1.R1.S05: Total Receive Enable Delay = 1301
N2.C2.D1.R1.S10: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N4.C1.D1.R1.S15: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N6.C1.D1.R1.S08: Total Receive Enable Delay = 1275
N0.C1.D1.R1.S06: Total Receive Enable Delay = 1325
N2.C2.D1.R1.S11: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N4.C1.D1.R1.S16: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N6.C1.D1.R1: Starting preamble search upper nibbles
N0.C1.D1.R1.S07: Total Receive Enable Delay = 1343
N2.C2.D1.R1.S12: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N4.C1.D1.R1.S17: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N6.C1.D1.R1.S09: PI = 051, PtrOffset = 004
N0.C1.D1.R1.S08: Total Receive Enable Delay = 1264
N2.C2.D1.R1.S13: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N4.C1.D1.R1.S11: Preamble found at Latency = 007
N6.C1.D1.R1.S10: PI = 033, PtrOffset = 004
N0.C1.D1.R1: Starting preamble search upper nibbles
N2.C2.D1.R1.S14: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N4.C1.D1.R1.S12: Preamble found at Latency = 007
N6.C1.D1.R1.S11: PI = 000, PtrOffset = 004
N0.C1.D1.R1.S09: PI = 039, PtrOffset = 004
N2.C2.D1.R1.S15: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N4.C1.D1.R1.S13: Preamble found at Latency = 007
N6.C1.D1.R1.S12: PI = 048, PtrOffset = 005
N0.C1.D1.R1.S10: PI = 020, PtrOffset = 004
N2.C2.D1.R1.S16: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N4.C1.D1.R1.S14: Preamble found at Latency = 007
N6.C1.D1.R1.S13: PI = 039, PtrOffset = 005
N0.C1.D1.R1.S11: PI = 054, PtrOffset = 005
N2.C2.D1.R1.S17: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N4.C1.D1.R1.S17: Preamble found at Latency = 007
N6.C1.D1.R1.S14: PI = 063, PtrOffset = 005
N0.C1.D1.R1.S12: PI = 035, PtrOffset = 005
N2.C2.D1.R1.S10: Preamble found at Latency = 007
N4.C1.D1.R1: Preamble found for all upper nibbles, adjusting Pi, Offset to center into preamble
N6.C1.D1.R1.S15: PI = 022, PtrOffset = 004
N0.C1.D1.R1.S13: PI = 029, PtrOffset = 005
N2.C2.D1.R1.S11: Preamble found at Latency = 007
N4.C1.D1.R1.S09: Total Receive Enable Delay = 1355
N6.C1.D1.R1.S16: PI = 046, PtrOffset = 004
N0.C1.D1.R1.S14: PI = 056, PtrOffset = 005
N2.C2.D1.R1.S12: Preamble found at Latency = 007
N4.C1.D1.R1.S10: Total Receive Enable Delay = 1336
N6.C1.D1.R1.S17: PI = 027, PtrOffset = 005
N0.C1.D1.R1.S15: PI = 013, PtrOffset = 004
N2.C2.D1.R1.S13: Preamble found at Latency = 007
N4.C1.D1.R1.S11: Total Receive Enable Delay = 1305
N6.C1.D1.R1.S09: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N0.C1.D1.R1.S16: PI = 032, PtrOffset = 004
N2.C2.D1.R1.S14: Preamble found at Latency = 007
N4.C1.D1.R1.S12: Total Receive Enable Delay = 1287
N6.C1.D1.R1.S10: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N0.C1.D1.R1.S17: PI = 016, PtrOffset = 005
N2.C2.D1.R1.S15: Preamble found at Latency = 007
N4.C1.D1.R1.S13: Total Receive Enable Delay = 1275
N6.C1.D1.R1.S11: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N0.C1.D1.R1.S09: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N2.C2.D1.R1.S16: Preamble found at Latency = 007
N4.C1.D1.R1.S14: Total Receive Enable Delay = 1300
N6.C1.D1.R1.S12: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N0.C1.D1.R1.S10: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N2.C2.D1.R1.S17: Preamble found at Latency = 007
N4.C1.D1.R1.S15: Total Receive Enable Delay = 1329
N6.C1.D1.R1.S13: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N0.C1.D1.R1.S11: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N2.C2.D1.R1: Preamble found for all upper nibbles, adjusting Pi, Offset to center into preamble
N4.C1.D1.R1.S16: Total Receive Enable Delay = 1349
N6.C1.D1.R1.S14: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N0.C1.D1.R1.S12: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N2.C2.D1.R1.S09: Total Receive Enable Delay = 1315
N4.C1.D1.R1.S17: Total Receive Enable Delay = 1266
N6.C1.D1.R1.S15: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N0.C1.D1.R1.S13: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N2.C2.D1.R1.S10: Total Receive Enable Delay = 1292
START_DATA_REC_EN
N6.C1.D1.R1.S16: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N0.C1.D1.R1.S14: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N2.C2.D1.R1.S11: Total Receive Enable Delay = 1260
N4.C1.S00: RdCmd2RcvEnLatency = 9, RdPtrOffsetRcvEn = 5
N6.C1.D1.R1.S17: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N0.C1.D1.R1.S15: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N2.C2.D1.R1.S12: Total Receive Enable Delay = 1243
N4.C1.S01: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N6.C1.D1.R1.S09: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N0.C1.D1.R1.S16: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N2.C2.D1.R1.S13: Total Receive Enable Delay = 1244
N4.C1.S02: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N6.C1.D1.R1.S10: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N0.C1.D1.R1.S17: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N2.C2.D1.R1.S14: Total Receive Enable Delay = 1251
N4.C1.S03: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N6.C1.D1.R1.S11: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N0.C1.D1.R1.S09: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N2.C2.D1.R1.S15: Total Receive Enable Delay = 1290
N4.C1.S04: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 5
N6.C1.D1.R1.S12: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N0.C1.D1.R1.S10: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N2.C2.D1.R1.S16: Total Receive Enable Delay = 1310
N4.C1.S05: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N6.C1.D1.R1.S13: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N0.C1.D1.R1.S11: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N2.C2.D1.R1.S17: Total Receive Enable Delay = 1228
N4.C1.S06: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N6.C1.D1.R1.S14: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N0.C1.D1.R1.S12: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
START_DATA_REC_EN
N4.C1.S07: RdCmd2RcvEnLatency = 9, RdPtrOffsetRcvEn = 5
N6.C1.D1.R1.S15: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N0.C1.D1.R1.S13: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N2.C2.S00: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N4.C1.S08: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 5
N6.C1.D1.R1.S16: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N0.C1.D1.R1.S14: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N2.C2.S01: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N4.C1.S09: RdCmd2RcvEnLatency = 9, RdPtrOffsetRcvEn = 5
N6.C1.D1.R1.S17: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N0.C1.D1.R1.S15: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N2.C2.S02: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 5
N4.C1.S10: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N6.C1.D1.R1.S09: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N0.C1.D1.R1.S16: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N2.C2.S03: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 5
N4.C1.S11: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N6.C1.D1.R1.S10: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N0.C1.D1.R1.S17: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N2.C2.S04: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 5
N4.C1.S12: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N6.C1.D1.R1.S11: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N0.C1.D1.R1.S09: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N2.C2.S05: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 5
N4.C1.S13: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 5
N6.C1.D1.R1.S12: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N0.C1.D1.R1.S10: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N2.C2.S06: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N4.C1.S14: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N6.C1.D1.R1.S13: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N0.C1.D1.R1.S11: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N2.C2.S07: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N4.C1.S15: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N6.C1.D1.R1.S14: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N0.C1.D1.R1.S12: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N2.C2.S08: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 5
N4.C1.S16: RdCmd2RcvEnLatency = 9, RdPtrOffsetRcvEn = 5
N6.C1.D1.R1.S15: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N0.C1.D1.R1.S13: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N2.C2.S09: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N4.C1.S17: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 5
N6.C1.D1.R1.S16: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N0.C1.D1.R1.S14: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N2.C2.S10: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N4.C1.D0.R0.S00: RcvEn: plus1 = 1, minus1 = 0, PI = 30, DB = 0
N6.C1.D1.R1.S17: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N0.C1.D1.R1.S15: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N2.C2.S11: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 5
N4.C1.D0.R0.S01: RcvEn: plus1 = 0, minus1 = 1, PI = 09, DB = 1
N6.C1.D1.R1.S09: Preamble found at Latency = 008
N0.C1.D1.R1.S16: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N2.C2.S12: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 5
N4.C1.D0.R0.S02: RcvEn: plus1 = 1, minus1 = 0, PI = 44, DB = 0
N6.C1.D1.R1.S10: Preamble found at Latency = 008
N0.C1.D1.R1.S17: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N2.C2.S13: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 5
N4.C1.D0.R0.S03: RcvEn: plus1 = 1, minus1 = 0, PI = 23, DB = 0
N6.C1.D1.R1.S11: Preamble found at Latency = 008
N0.C1.D1.R1.S09: Preamble found at Latency = 008
N2.C2.S14: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 5
N4.C1.D0.R0.S04: RcvEn: plus1 = 0, minus1 = 1, PI = 17, DB = 0
N6.C1.D1.R1.S15: Preamble found at Latency = 008
N0.C1.D1.R1.S10: Preamble found at Latency = 008
N2.C2.S15: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N4.C1.D0.R0.S05: RcvEn: plus1 = 1, minus1 = 0, PI = 42, DB = 0
N6.C1.D1.R1.S16: Preamble found at Latency = 008
N0.C1.D1.R1.S15: Preamble found at Latency = 008
N2.C2.S16: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N4.C1.D0.R0.S06: RcvEn: plus1 = 0, minus1 = 1, PI = 01, DB = 1
N6.C1.D1.R1.S09: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N0.C1.D1.R1.S16: Preamble found at Latency = 008
N2.C2.S17: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 5
N4.C1.D0.R0.S07: RcvEn: plus1 = 1, minus1 = 0, PI = 21, DB = 0
N6.C1.D1.R1.S10: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N0.C1.D1.R1.S09: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N2.C2.D0.R0.S00: RcvEn: plus1 = 1, minus1 = 0, PI = 49, DB = 1
N4.C1.D0.R0.S08: RcvEn: plus1 = 0, minus1 = 1, PI = 04, DB = 1
N6.C1.D1.R1.S11: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N0.C1.D1.R1.S10: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N2.C2.D0.R0.S01: RcvEn: plus1 = 1, minus1 = 0, PI = 28, DB = 0
N4.C1.D0.R0.S09: RcvEn: plus1 = 1, minus1 = 0, PI = 30, DB = 0
N6.C1.D1.R1.S12: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N0.C1.D1.R1.S11: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N2.C2.D0.R0.S02: RcvEn: plus1 = 1, minus1 = 0, PI = 60, DB = 1
N4.C1.D0.R0.S10: RcvEn: plus1 = 0, minus1 = 1, PI = 11, DB = 1
N6.C1.D1.R1.S13: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N0.C1.D1.R1.S12: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N2.C2.D0.R0.S03: RcvEn: plus1 = 1, minus1 = 0, PI = 41, DB = 0
N4.C1.D0.R0.S11: RcvEn: plus1 = 1, minus1 = 0, PI = 44, DB = 0
N6.C1.D1.R1.S14: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N0.C1.D1.R1.S13: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N2.C2.D0.R0.S04: RcvEn: plus1 = 1, minus1 = 0, PI = 41, DB = 0
N4.C1.D0.R0.S12: RcvEn: plus1 = 1, minus1 = 0, PI = 25, DB = 0
N6.C1.D1.R1.S15: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N0.C1.D1.R1.S14: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N2.C2.D0.R0.S05: RcvEn: plus1 = 1, minus1 = 0, PI = 53, DB = 1
N4.C1.D0.R0.S13: RcvEn: plus1 = 0, minus1 = 1, PI = 16, DB = 0
N6.C1.D1.R1.S16: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N0.C1.D1.R1.S15: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N2.C2.D0.R0.S06: RcvEn: plus1 = 1, minus1 = 0, PI = 27, DB = 0
N4.C1.D0.R0.S14: RcvEn: plus1 = 1, minus1 = 0, PI = 42, DB = 0
N6.C1.D1.R1.S17: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N0.C1.D1.R1.S16: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N2.C2.D0.R0.S07: RcvEn: plus1 = 1, minus1 = 0, PI = 46, DB = 0
N4.C1.D0.R0.S15: RcvEn: plus1 = 0, minus1 = 1, PI = 03, DB = 1
N6.C1.D1.R1.S12: Preamble found at Latency = 007
N0.C1.D1.R1.S17: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N2.C2.D0.R0.S08: RcvEn: plus1 = 1, minus1 = 0, PI = 29, DB = 0
N4.C1.D0.R0.S16: RcvEn: plus1 = 1, minus1 = 0, PI = 22, DB = 0
N6.C1.D1.R1.S13: Preamble found at Latency = 007
N0.C1.D1.R1.S11: Preamble found at Latency = 007
N2.C2.D0.R0.S09: RcvEn: plus1 = 1, minus1 = 0, PI = 50, DB = 1
N4.C1.D0.R0.S17: RcvEn: plus1 = 0, minus1 = 1, PI = 04, DB = 1
N6.C1.D1.R1.S14: Preamble found at Latency = 007
N0.C1.D1.R1.S12: Preamble found at Latency = 007
N2.C2.D0.R0.S10: RcvEn: plus1 = 1, minus1 = 0, PI = 28, DB = 0
N4.C1.D0.R1.S00: RcvEn: plus1 = 1, minus1 = 0, PI = 30, DB = 0
N6.C1.D1.R1.S17: Preamble found at Latency = 007
N0.C1.D1.R1.S13: Preamble found at Latency = 007
N2.C2.D0.R0.S11: RcvEn: plus1 = 1, minus1 = 0, PI = 60, DB = 1
N4.C1.D0.R1.S01: RcvEn: plus1 = 0, minus1 = 1, PI = 09, DB = 1
N6.C1.D1.R1: Preamble found for all upper nibbles, adjusting Pi, Offset to center into preamble
N0.C1.D1.R1.S14: Preamble found at Latency = 007
N2.C2.D0.R0.S12: RcvEn: plus1 = 1, minus1 = 0, PI = 42, DB = 0
N4.C1.D0.R1.S02: RcvEn: plus1 = 1, minus1 = 0, PI = 44, DB = 0
N6.C1.D1.R1.S09: Total Receive Enable Delay = 1363
N0.C1.D1.R1.S17: Preamble found at Latency = 007
N2.C2.D0.R0.S13: RcvEn: plus1 = 1, minus1 = 0, PI = 41, DB = 0
N4.C1.D0.R1.S03: RcvEn: plus1 = 1, minus1 = 0, PI = 23, DB = 0
N6.C1.D1.R1.S10: Total Receive Enable Delay = 1345
N0.C1.D1.R1: Preamble found for all upper nibbles, adjusting Pi, Offset to center into preamble
N2.C2.D0.R0.S14: RcvEn: plus1 = 1, minus1 = 0, PI = 52, DB = 1
N4.C1.D0.R1.S04: RcvEn: plus1 = 0, minus1 = 1, PI = 17, DB = 0
N6.C1.D1.R1.S11: Total Receive Enable Delay = 1312
N0.C1.D1.R1.S09: Total Receive Enable Delay = 1351
N2.C2.D0.R0.S15: RcvEn: plus1 = 1, minus1 = 0, PI = 24, DB = 0
N4.C1.D0.R1.S05: RcvEn: plus1 = 1, minus1 = 0, PI = 42, DB = 0
N6.C1.D1.R1.S12: Total Receive Enable Delay = 1296
N0.C1.D1.R1.S10: Total Receive Enable Delay = 1332
N2.C2.D0.R0.S16: RcvEn: plus1 = 1, minus1 = 0, PI = 45, DB = 0
N4.C1.D0.R1.S06: RcvEn: plus1 = 0, minus1 = 1, PI = 01, DB = 1
N6.C1.D1.R1.S13: Total Receive Enable Delay = 1287
N0.C1.D1.R1.S11: Total Receive Enable Delay = 1302
N2.C2.D0.R0.S17: RcvEn: plus1 = 1, minus1 = 0, PI = 25, DB = 0
N4.C1.D0.R1.S07: RcvEn: plus1 = 1, minus1 = 0, PI = 21, DB = 0
N6.C1.D1.R1.S14: Total Receive Enable Delay = 1311
N0.C1.D1.R1.S12: Total Receive Enable Delay = 1283
N2.C2.D0.R1.S00: RcvEn: plus1 = 1, minus1 = 0, PI = 49, DB = 1
N4.C1.D0.R1.S08: RcvEn: plus1 = 0, minus1 = 1, PI = 04, DB = 1
N6.C1.D1.R1.S15: Total Receive Enable Delay = 1334
N0.C1.D1.R1.S13: Total Receive Enable Delay = 1277
N2.C2.D0.R1.S01: RcvEn: plus1 = 1, minus1 = 0, PI = 28, DB = 0
N4.C1.D0.R1.S09: RcvEn: plus1 = 1, minus1 = 0, PI = 30, DB = 0
N6.C1.D1.R1.S16: Total Receive Enable Delay = 1358
N0.C1.D1.R1.S14: Total Receive Enable Delay = 1304
N2.C2.D0.R1.S02: RcvEn: plus1 = 1, minus1 = 0, PI = 60, DB = 1
N4.C1.D0.R1.S10: RcvEn: plus1 = 0, minus1 = 1, PI = 11, DB = 1
N6.C1.D1.R1.S17: Total Receive Enable Delay = 1275
N0.C1.D1.R1.S15: Total Receive Enable Delay = 1325
N2.C2.D0.R1.S03: RcvEn: plus1 = 1, minus1 = 0, PI = 41, DB = 0
N4.C1.D0.R1.S11: RcvEn: plus1 = 1, minus1 = 0, PI = 44, DB = 0
START_DATA_REC_EN
N0.C1.D1.R1.S16: Total Receive Enable Delay = 1344
N2.C2.D0.R1.S04: RcvEn: plus1 = 1, minus1 = 0, PI = 41, DB = 0
N4.C1.D0.R1.S12: RcvEn: plus1 = 1, minus1 = 0, PI = 25, DB = 0
N6.C1.S00: RdCmd2RcvEnLatency = 9, RdPtrOffsetRcvEn = 5
N0.C1.D1.R1.S17: Total Receive Enable Delay = 1264
N2.C2.D0.R1.S05: RcvEn: plus1 = 1, minus1 = 0, PI = 53, DB = 1
N4.C1.D0.R1.S13: RcvEn: plus1 = 0, minus1 = 1, PI = 16, DB = 0
N6.C1.S01: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
START_DATA_REC_EN
N2.C2.D0.R1.S06: RcvEn: plus1 = 1, minus1 = 0, PI = 27, DB = 0
N4.C1.D0.R1.S14: RcvEn: plus1 = 1, minus1 = 0, PI = 42, DB = 0
N6.C1.S02: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N0.C1.S00: RdCmd2RcvEnLatency = 9, RdPtrOffsetRcvEn = 5
N2.C2.D0.R1.S07: RcvEn: plus1 = 1, minus1 = 0, PI = 46, DB = 0
N4.C1.D0.R1.S15: RcvEn: plus1 = 0, minus1 = 1, PI = 03, DB = 1
N6.C1.S03: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N0.C1.S01: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N2.C2.D0.R1.S08: RcvEn: plus1 = 1, minus1 = 0, PI = 29, DB = 0
N4.C1.D0.R1.S16: RcvEn: plus1 = 1, minus1 = 0, PI = 22, DB = 0
N6.C1.S04: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N0.C1.S02: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N2.C2.D0.R1.S09: RcvEn: plus1 = 1, minus1 = 0, PI = 50, DB = 1
N4.C1.D0.R1.S17: RcvEn: plus1 = 0, minus1 = 1, PI = 04, DB = 1
N6.C1.S05: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N0.C1.S03: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N2.C2.D0.R1.S10: RcvEn: plus1 = 1, minus1 = 0, PI = 28, DB = 0
N4.C1.D1.R0.S00: RcvEn: plus1 = 1, minus1 = 0, PI = 11, DB = 1
N6.C1.S06: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N0.C1.S04: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 5
N2.C2.D0.R1.S11: RcvEn: plus1 = 1, minus1 = 0, PI = 60, DB = 1
N4.C1.D1.R0.S01: RcvEn: plus1 = 1, minus1 = 0, PI = 53, DB = 1
N6.C1.S07: RdCmd2RcvEnLatency = 9, RdPtrOffsetRcvEn = 5
N0.C1.S05: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N2.C2.D0.R1.S12: RcvEn: plus1 = 1, minus1 = 0, PI = 42, DB = 0
N4.C1.D1.R0.S02: RcvEn: plus1 = 1, minus1 = 0, PI = 23, DB = 0
N6.C1.S08: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 5
N0.C1.S06: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N2.C2.D0.R1.S13: RcvEn: plus1 = 1, minus1 = 0, PI = 41, DB = 0
N4.C1.D1.R0.S03: RcvEn: plus1 = 1, minus1 = 0, PI = 03, DB = 1
N6.C1.S09: RdCmd2RcvEnLatency = 9, RdPtrOffsetRcvEn = 5
N0.C1.S07: RdCmd2RcvEnLatency = 9, RdPtrOffsetRcvEn = 5
N2.C2.D0.R1.S14: RcvEn: plus1 = 1, minus1 = 0, PI = 52, DB = 1
N4.C1.D1.R0.S04: RcvEn: plus1 = 1, minus1 = 0, PI = 60, DB = 1
N6.C1.S10: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N0.C1.S08: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 5
N2.C2.D0.R1.S15: RcvEn: plus1 = 1, minus1 = 0, PI = 24, DB = 0
N4.C1.D1.R0.S05: RcvEn: plus1 = 1, minus1 = 0, PI = 22, DB = 0
N6.C1.S11: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N0.C1.S09: RdCmd2RcvEnLatency = 9, RdPtrOffsetRcvEn = 5
N2.C2.D0.R1.S16: RcvEn: plus1 = 1, minus1 = 0, PI = 45, DB = 0
N4.C1.D1.R0.S06: RcvEn: plus1 = 1, minus1 = 0, PI = 47, DB = 0
N6.C1.S12: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N0.C1.S10: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N2.C2.D0.R1.S17: RcvEn: plus1 = 1, minus1 = 0, PI = 25, DB = 0
N4.C1.D1.R0.S07: RcvEn: plus1 = 1, minus1 = 0, PI = 01, DB = 1
N6.C1.S13: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N0.C1.S11: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N2.C2.D1.R0.S00: RcvEn: plus1 = 1, minus1 = 0, PI = 35, DB = 0
N4.C1.D1.R0.S08: RcvEn: plus1 = 1, minus1 = 0, PI = 48, DB = 0
N6.C1.S14: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N0.C1.S12: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N2.C2.D1.R0.S01: RcvEn: plus1 = 1, minus1 = 0, PI = 12, DB = 1
N4.C1.D1.R0.S09: RcvEn: plus1 = 1, minus1 = 0, PI = 11, DB = 1
N6.C1.S15: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N0.C1.S13: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 5
N2.C2.D1.R0.S02: RcvEn: plus1 = 1, minus1 = 0, PI = 44, DB = 0
N4.C1.D1.R0.S10: RcvEn: plus1 = 1, minus1 = 0, PI = 56, DB = 1
N6.C1.S16: RdCmd2RcvEnLatency = 9, RdPtrOffsetRcvEn = 5
N0.C1.S14: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N2.C2.D1.R0.S03: RcvEn: plus1 = 1, minus1 = 0, PI = 26, DB = 0
N4.C1.D1.R0.S11: RcvEn: plus1 = 1, minus1 = 0, PI = 28, DB = 0
N6.C1.S17: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 5
N0.C1.S15: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N2.C2.D1.R0.S04: RcvEn: plus1 = 1, minus1 = 0, PI = 28, DB = 0
N4.C1.D1.R0.S12: RcvEn: plus1 = 1, minus1 = 0, PI = 07, DB = 1
N6.C1.D0.R0.S00: RcvEn: plus1 = 1, minus1 = 0, PI = 35, DB = 0
N0.C1.S16: RdCmd2RcvEnLatency = 9, RdPtrOffsetRcvEn = 5
N2.C2.D1.R0.S05: RcvEn: plus1 = 1, minus1 = 0, PI = 39, DB = 0
N4.C1.D1.R0.S13: RcvEn: plus1 = 1, minus1 = 0, PI = 59, DB = 1
N6.C1.D0.R0.S01: RcvEn: plus1 = 0, minus1 = 1, PI = 14, DB = 1
N0.C1.S17: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 5
N2.C2.D1.R0.S06: RcvEn: plus1 = 1, minus1 = 0, PI = 13, DB = 1
N4.C1.D1.R0.S14: RcvEn: plus1 = 1, minus1 = 0, PI = 21, DB = 0
N6.C1.D0.R0.S02: RcvEn: plus1 = 1, minus1 = 0, PI = 47, DB = 0
N0.C1.D0.R0.S00: RcvEn: plus1 = 1, minus1 = 0, PI = 31, DB = 0
N2.C2.D1.R0.S07: RcvEn: plus1 = 1, minus1 = 0, PI = 29, DB = 0
N4.C1.D1.R0.S15: RcvEn: plus1 = 1, minus1 = 0, PI = 49, DB = 1
N6.C1.D0.R0.S03: RcvEn: plus1 = 1, minus1 = 0, PI = 27, DB = 0
N0.C1.D0.R0.S01: RcvEn: plus1 = 0, minus1 = 1, PI = 09, DB = 1
N2.C2.D1.R0.S08: RcvEn: plus1 = 1, minus1 = 0, PI = 14, DB = 1
N4.C1.D1.R0.S16: RcvEn: plus1 = 1, minus1 = 0, PI = 05, DB = 1
N6.C1.D0.R0.S04: RcvEn: plus1 = 1, minus1 = 0, PI = 20, DB = 0
N0.C1.D0.R0.S02: RcvEn: plus1 = 1, minus1 = 0, PI = 42, DB = 0
N2.C2.D1.R0.S09: RcvEn: plus1 = 1, minus1 = 0, PI = 35, DB = 0
N4.C1.D1.R0.S17: RcvEn: plus1 = 1, minus1 = 0, PI = 49, DB = 1
N6.C1.D0.R0.S05: RcvEn: plus1 = 1, minus1 = 0, PI = 46, DB = 0
N0.C1.D0.R0.S03: RcvEn: plus1 = 1, minus1 = 0, PI = 25, DB = 0
N2.C2.D1.R0.S10: RcvEn: plus1 = 1, minus1 = 0, PI = 12, DB = 1
N4.C1.D1.R1.S00: RcvEn: plus1 = 1, minus1 = 0, PI = 11, DB = 1
N6.C1.D0.R0.S06: RcvEn: plus1 = 0, minus1 = 1, PI = 04, DB = 1
N0.C1.D0.R0.S04: RcvEn: plus1 = 0, minus1 = 1, PI = 16, DB = 0
N2.C2.D1.R0.S11: RcvEn: plus1 = 1, minus1 = 0, PI = 44, DB = 0
N4.C1.D1.R1.S01: RcvEn: plus1 = 1, minus1 = 0, PI = 53, DB = 1
N6.C1.D0.R0.S07: RcvEn: plus1 = 1, minus1 = 0, PI = 27, DB = 0
N0.C1.D0.R0.S05: RcvEn: plus1 = 1, minus1 = 0, PI = 42, DB = 0
N2.C2.D1.R0.S12: RcvEn: plus1 = 1, minus1 = 0, PI = 26, DB = 0
N4.C1.D1.R1.S02: RcvEn: plus1 = 1, minus1 = 0, PI = 23, DB = 0
N6.C1.D0.R0.S08: RcvEn: plus1 = 0, minus1 = 1, PI = 09, DB = 1
N0.C1.D0.R0.S06: RcvEn: plus1 = 0, minus1 = 1, PI = 00, DB = 1
N2.C2.D1.R0.S13: RcvEn: plus1 = 1, minus1 = 0, PI = 27, DB = 0
N4.C1.D1.R1.S03: RcvEn: plus1 = 1, minus1 = 0, PI = 03, DB = 1
N6.C1.D0.R0.S09: RcvEn: plus1 = 1, minus1 = 0, PI = 33, DB = 0
N0.C1.D0.R0.S07: RcvEn: plus1 = 1, minus1 = 0, PI = 24, DB = 0
N2.C2.D1.R0.S14: RcvEn: plus1 = 1, minus1 = 0, PI = 36, DB = 0
N4.C1.D1.R1.S04: RcvEn: plus1 = 1, minus1 = 0, PI = 60, DB = 1
N6.C1.D0.R0.S10: RcvEn: plus1 = 0, minus1 = 1, PI = 15, DB = 1
N0.C1.D0.R0.S08: RcvEn: plus1 = 0, minus1 = 1, PI = 04, DB = 1
N2.C2.D1.R0.S15: RcvEn: plus1 = 1, minus1 = 0, PI = 10, DB = 1
N4.C1.D1.R1.S05: RcvEn: plus1 = 1, minus1 = 0, PI = 22, DB = 0
N6.C1.D0.R0.S11: RcvEn: plus1 = 1, minus1 = 0, PI = 47, DB = 0
N0.C1.D0.R0.S09: RcvEn: plus1 = 1, minus1 = 0, PI = 30, DB = 0
N2.C2.D1.R0.S16: RcvEn: plus1 = 1, minus1 = 0, PI = 29, DB = 0
N4.C1.D1.R1.S06: RcvEn: plus1 = 1, minus1 = 0, PI = 47, DB = 0
N6.C1.D0.R0.S12: RcvEn: plus1 = 1, minus1 = 0, PI = 30, DB = 0
N0.C1.D0.R0.S10: RcvEn: plus1 = 0, minus1 = 1, PI = 09, DB = 1
N2.C2.D1.R0.S17: RcvEn: plus1 = 1, minus1 = 0, PI = 11, DB = 1
N4.C1.D1.R1.S07: RcvEn: plus1 = 1, minus1 = 0, PI = 01, DB = 1
N6.C1.D0.R0.S13: RcvEn: plus1 = 1, minus1 = 0, PI = 22, DB = 0
N0.C1.D0.R0.S11: RcvEn: plus1 = 1, minus1 = 0, PI = 45, DB = 0
N2.C2.D1.R1.S00: RcvEn: plus1 = 1, minus1 = 0, PI = 35, DB = 0
N4.C1.D1.R1.S08: RcvEn: plus1 = 1, minus1 = 0, PI = 48, DB = 0
N6.C1.D0.R0.S14: RcvEn: plus1 = 1, minus1 = 0, PI = 46, DB = 0
N0.C1.D0.R0.S12: RcvEn: plus1 = 1, minus1 = 0, PI = 25, DB = 0
N2.C2.D1.R1.S01: RcvEn: plus1 = 1, minus1 = 0, PI = 12, DB = 1
N4.C1.D1.R1.S09: RcvEn: plus1 = 1, minus1 = 0, PI = 11, DB = 1
N6.C1.D0.R0.S15: RcvEn: plus1 = 0, minus1 = 1, PI = 05, DB = 1
N0.C1.D0.R0.S13: RcvEn: plus1 = 0, minus1 = 1, PI = 16, DB = 0
N2.C2.D1.R1.S02: RcvEn: plus1 = 1, minus1 = 0, PI = 44, DB = 0
N4.C1.D1.R1.S10: RcvEn: plus1 = 1, minus1 = 0, PI = 56, DB = 1
N6.C1.D0.R0.S16: RcvEn: plus1 = 1, minus1 = 0, PI = 27, DB = 0
N0.C1.D0.R0.S14: RcvEn: plus1 = 1, minus1 = 0, PI = 41, DB = 0
N2.C2.D1.R1.S03: RcvEn: plus1 = 1, minus1 = 0, PI = 26, DB = 0
N4.C1.D1.R1.S11: RcvEn: plus1 = 1, minus1 = 0, PI = 28, DB = 0
N6.C1.D0.R0.S17: RcvEn: plus1 = 0, minus1 = 1, PI = 09, DB = 1
N0.C1.D0.R0.S15: RcvEn: plus1 = 0, minus1 = 1, PI = 01, DB = 1
N2.C2.D1.R1.S04: RcvEn: plus1 = 1, minus1 = 0, PI = 28, DB = 0
N4.C1.D1.R1.S12: RcvEn: plus1 = 1, minus1 = 0, PI = 07, DB = 1
N6.C1.D0.R1.S00: RcvEn: plus1 = 1, minus1 = 0, PI = 35, DB = 0
N0.C1.D0.R0.S16: RcvEn: plus1 = 1, minus1 = 0, PI = 23, DB = 0
N2.C2.D1.R1.S05: RcvEn: plus1 = 1, minus1 = 0, PI = 39, DB = 0
N4.C1.D1.R1.S13: RcvEn: plus1 = 1, minus1 = 0, PI = 59, DB = 1
N6.C1.D0.R1.S01: RcvEn: plus1 = 0, minus1 = 1, PI = 14, DB = 1
N0.C1.D0.R0.S17: RcvEn: plus1 = 0, minus1 = 1, PI = 06, DB = 1
N2.C2.D1.R1.S06: RcvEn: plus1 = 1, minus1 = 0, PI = 13, DB = 1
N4.C1.D1.R1.S14: RcvEn: plus1 = 1, minus1 = 0, PI = 21, DB = 0
N6.C1.D0.R1.S02: RcvEn: plus1 = 1, minus1 = 0, PI = 47, DB = 0
N0.C1.D0.R1.S00: RcvEn: plus1 = 1, minus1 = 0, PI = 31, DB = 0
N2.C2.D1.R1.S07: RcvEn: plus1 = 1, minus1 = 0, PI = 29, DB = 0
N4.C1.D1.R1.S15: RcvEn: plus1 = 1, minus1 = 0, PI = 49, DB = 1
N6.C1.D0.R1.S03: RcvEn: plus1 = 1, minus1 = 0, PI = 27, DB = 0
N0.C1.D0.R1.S01: RcvEn: plus1 = 0, minus1 = 1, PI = 09, DB = 1
N2.C2.D1.R1.S08: RcvEn: plus1 = 1, minus1 = 0, PI = 14, DB = 1
N4.C1.D1.R1.S16: RcvEn: plus1 = 1, minus1 = 0, PI = 05, DB = 1
N6.C1.D0.R1.S04: RcvEn: plus1 = 1, minus1 = 0, PI = 20, DB = 0
N0.C1.D0.R1.S02: RcvEn: plus1 = 1, minus1 = 0, PI = 42, DB = 0
N2.C2.D1.R1.S09: RcvEn: plus1 = 1, minus1 = 0, PI = 35, DB = 0
N4.C1.D1.R1.S17: RcvEn: plus1 = 1, minus1 = 0, PI = 49, DB = 1
N6.C1.D0.R1.S05: RcvEn: plus1 = 1, minus1 = 0, PI = 46, DB = 0
N0.C1.D0.R1.S03: RcvEn: plus1 = 1, minus1 = 0, PI = 25, DB = 0
N2.C2.D1.R1.S10: RcvEn: plus1 = 1, minus1 = 0, PI = 12, DB = 1
STOP_DATA_REC_EN
N6.C1.D0.R1.S06: RcvEn: plus1 = 0, minus1 = 1, PI = 04, DB = 1
N0.C1.D0.R1.S04: RcvEn: plus1 = 0, minus1 = 1, PI = 16, DB = 0
N2.C2.D1.R1.S11: RcvEn: plus1 = 1, minus1 = 0, PI = 44, DB = 0
N4.C2.D0.R0: RcvEnFine: Initial RdCmd2RcvEnLatency = 10, Initial RdPtrOffsetRcvEn = 4
N6.C1.D0.R1.S07: RcvEn: plus1 = 1, minus1 = 0, PI = 27, DB = 0
N0.C1.D0.R1.S05: RcvEn: plus1 = 1, minus1 = 0, PI = 42, DB = 0
N2.C2.D1.R1.S12: RcvEn: plus1 = 1, minus1 = 0, PI = 26, DB = 0
N4.C2.D0.R0.S00: Rcv En Fine Value = 271
N6.C1.D0.R1.S08: RcvEn: plus1 = 0, minus1 = 1, PI = 09, DB = 1
N0.C1.D0.R1.S06: RcvEn: plus1 = 0, minus1 = 1, PI = 00, DB = 1
N2.C2.D1.R1.S13: RcvEn: plus1 = 1, minus1 = 0, PI = 27, DB = 0
N4.C2.D0.R0.S01: Rcv En Fine Value = 374
N6.C1.D0.R1.S09: RcvEn: plus1 = 1, minus1 = 0, PI = 33, DB = 0
N0.C1.D0.R1.S07: RcvEn: plus1 = 1, minus1 = 0, PI = 24, DB = 0
N2.C2.D1.R1.S14: RcvEn: plus1 = 1, minus1 = 0, PI = 36, DB = 0
N4.C2.D0.R0.S02: Rcv En Fine Value = 346
N6.C1.D0.R1.S10: RcvEn: plus1 = 0, minus1 = 1, PI = 15, DB = 1
N0.C1.D0.R1.S08: RcvEn: plus1 = 0, minus1 = 1, PI = 04, DB = 1
N2.C2.D1.R1.S15: RcvEn: plus1 = 1, minus1 = 0, PI = 10, DB = 1
N4.C2.D0.R0.S03: Rcv En Fine Value = 324
N6.C1.D0.R1.S11: RcvEn: plus1 = 1, minus1 = 0, PI = 47, DB = 0
N0.C1.D0.R1.S09: RcvEn: plus1 = 1, minus1 = 0, PI = 30, DB = 0
N2.C2.D1.R1.S16: RcvEn: plus1 = 1, minus1 = 0, PI = 29, DB = 0
N4.C2.D0.R0.S04: Rcv En Fine Value = 326
N6.C1.D0.R1.S12: RcvEn: plus1 = 1, minus1 = 0, PI = 30, DB = 0
N0.C1.D0.R1.S10: RcvEn: plus1 = 0, minus1 = 1, PI = 09, DB = 1
N2.C2.D1.R1.S17: RcvEn: plus1 = 1, minus1 = 0, PI = 11, DB = 1
N4.C2.D0.R0.S05: Rcv En Fine Value = 336
N6.C1.D0.R1.S13: RcvEn: plus1 = 1, minus1 = 0, PI = 22, DB = 0
N0.C1.D0.R1.S11: RcvEn: plus1 = 1, minus1 = 0, PI = 45, DB = 0
STOP_DATA_REC_EN
N4.C2.D0.R0.S06: Rcv En Fine Value = 374
N6.C1.D0.R1.S14: RcvEn: plus1 = 1, minus1 = 0, PI = 46, DB = 0
N0.C1.D0.R1.S12: RcvEn: plus1 = 1, minus1 = 0, PI = 25, DB = 0
N2.C3.D0.R0: RcvEnFine: Initial RdCmd2RcvEnLatency = 10, Initial RdPtrOffsetRcvEn = 4
N4.C2.D0.R0.S07: Rcv En Fine Value = 262
N6.C1.D0.R1.S15: RcvEn: plus1 = 0, minus1 = 1, PI = 05, DB = 1
N0.C1.D0.R1.S13: RcvEn: plus1 = 0, minus1 = 1, PI = 16, DB = 0
N2.C3.D0.R0.S00: Rcv En Fine Value = 319
N4.C2.D0.R0.S08: Rcv En Fine Value = 311
N6.C1.D0.R1.S16: RcvEn: plus1 = 1, minus1 = 0, PI = 27, DB = 0
N0.C1.D0.R1.S14: RcvEn: plus1 = 1, minus1 = 0, PI = 41, DB = 0
N2.C3.D0.R0.S01: Rcv En Fine Value = 294
N4.C2.D0.R0.S09: Rcv En Fine Value = 268
N6.C1.D0.R1.S17: RcvEn: plus1 = 0, minus1 = 1, PI = 09, DB = 1
N0.C1.D0.R1.S15: RcvEn: plus1 = 0, minus1 = 1, PI = 01, DB = 1
N2.C3.D0.R0.S02: Rcv En Fine Value = 268
N4.C2.D0.R0.S10: Rcv En Fine Value = 374
N6.C1.D1.R0.S00: RcvEn: plus1 = 1, minus1 = 0, PI = 22, DB = 0
N0.C1.D0.R1.S16: RcvEn: plus1 = 1, minus1 = 0, PI = 23, DB = 0
N2.C3.D0.R0.S03: Rcv En Fine Value = 373
N4.C2.D0.R0.S11: Rcv En Fine Value = 341
N6.C1.D1.R0.S01: RcvEn: plus1 = 1, minus1 = 0, PI = 63, DB = 1
N0.C1.D0.R1.S17: RcvEn: plus1 = 0, minus1 = 1, PI = 06, DB = 1
N2.C3.D0.R0.S04: Rcv En Fine Value = 369
N4.C2.D0.R0.S12: Rcv En Fine Value = 323
N6.C1.D1.R0.S02: RcvEn: plus1 = 1, minus1 = 0, PI = 32, DB = 0
N0.C1.D1.R0.S00: RcvEn: plus1 = 1, minus1 = 0, PI = 10, DB = 1
N2.C3.D0.R0.S05: Rcv En Fine Value = 265
N4.C2.D0.R0.S13: Rcv En Fine Value = 323
N6.C1.D1.R0.S03: RcvEn: plus1 = 1, minus1 = 0, PI = 11, DB = 1
N0.C1.D1.R0.S01: RcvEn: plus1 = 1, minus1 = 0, PI = 51, DB = 1
N2.C3.D0.R0.S06: Rcv En Fine Value = 289
N4.C2.D0.R0.S14: Rcv En Fine Value = 339
N6.C1.D1.R0.S04: RcvEn: plus1 = 1, minus1 = 0, PI = 07, DB = 1
N0.C1.D1.R0.S02: RcvEn: plus1 = 1, minus1 = 0, PI = 22, DB = 0
N2.C3.D0.R0.S07: Rcv En Fine Value = 310
N4.C2.D0.R0.S15: Rcv En Fine Value = 374
N6.C1.D1.R0.S05: RcvEn: plus1 = 1, minus1 = 0, PI = 31, DB = 0
N0.C1.D1.R0.S03: RcvEn: plus1 = 1, minus1 = 0, PI = 04, DB = 1
N2.C3.D0.R0.S08: Rcv En Fine Value = 354
N4.C2.D0.R0.S16: Rcv En Fine Value = 263
N6.C1.D1.R0.S06: RcvEn: plus1 = 1, minus1 = 0, PI = 54, DB = 1
N0.C1.D1.R0.S04: RcvEn: plus1 = 1, minus1 = 0, PI = 58, DB = 1
N2.C3.D0.R0.S09: Rcv En Fine Value = 319
N4.C2.D0.R0.S17: Rcv En Fine Value = 307
N6.C1.D1.R0.S07: RcvEn: plus1 = 1, minus1 = 0, PI = 10, DB = 1
N0.C1.D1.R0.S05: RcvEn: plus1 = 1, minus1 = 0, PI = 22, DB = 0
N2.C3.D0.R0.S10: Rcv En Fine Value = 295
N4.C2.D0.R0: Starting preamble search lower nibbles
N6.C1.D1.R0.S08: RcvEn: plus1 = 1, minus1 = 0, PI = 60, DB = 1
N0.C1.D1.R0.S06: RcvEn: plus1 = 1, minus1 = 0, PI = 44, DB = 0
N2.C3.D0.R0.S11: Rcv En Fine Value = 267
N4.C2.D0.R0.S00: PI = 015, PtrOffset = 004
N6.C1.D1.R0.S09: RcvEn: plus1 = 1, minus1 = 0, PI = 20, DB = 0
N0.C1.D1.R0.S07: RcvEn: plus1 = 1, minus1 = 0, PI = 00, DB = 1
N2.C3.D0.R0.S12: Rcv En Fine Value = 374
N4.C2.D0.R0.S01: PI = 054, PtrOffset = 005
N6.C1.D1.R0.S10: RcvEn: plus1 = 0, minus1 = 1, PI = 01, DB = 1
N0.C1.D1.R0.S08: RcvEn: plus1 = 1, minus1 = 0, PI = 47, DB = 0
N2.C3.D0.R0.S13: Rcv En Fine Value = 370
N4.C2.D0.R0.S02: PI = 026, PtrOffset = 005
N6.C1.D1.R0.S11: RcvEn: plus1 = 1, minus1 = 0, PI = 33, DB = 0
N0.C1.D1.R0.S09: RcvEn: plus1 = 1, minus1 = 0, PI = 08, DB = 1
N2.C3.D0.R0.S14: Rcv En Fine Value = 267
N4.C2.D0.R0.S03: PI = 004, PtrOffset = 005
N6.C1.D1.R0.S12: RcvEn: plus1 = 1, minus1 = 0, PI = 15, DB = 1
N0.C1.D1.R0.S10: RcvEn: plus1 = 1, minus1 = 0, PI = 51, DB = 1
N2.C3.D0.R0.S15: Rcv En Fine Value = 290
N4.C2.D0.R0.S04: PI = 006, PtrOffset = 005
N6.C1.D1.R0.S13: RcvEn: plus1 = 1, minus1 = 0, PI = 06, DB = 1
N0.C1.D1.R0.S11: RcvEn: plus1 = 1, minus1 = 0, PI = 23, DB = 0
N2.C3.D0.R0.S16: Rcv En Fine Value = 312
N4.C2.D0.R0.S05: PI = 016, PtrOffset = 005
N6.C1.D1.R0.S14: RcvEn: plus1 = 1, minus1 = 0, PI = 31, DB = 0
N0.C1.D1.R0.S12: RcvEn: plus1 = 1, minus1 = 0, PI = 02, DB = 1
N2.C3.D0.R0.S17: Rcv En Fine Value = 357
N4.C2.D0.R0.S06: PI = 054, PtrOffset = 005
N6.C1.D1.R0.S15: RcvEn: plus1 = 1, minus1 = 0, PI = 54, DB = 1
N0.C1.D1.R0.S13: RcvEn: plus1 = 1, minus1 = 0, PI = 61, DB = 1
N2.C3.D0.R0: Starting preamble search lower nibbles
N4.C2.D0.R0.S07: PI = 006, PtrOffset = 004
N6.C1.D1.R0.S16: RcvEn: plus1 = 1, minus1 = 0, PI = 13, DB = 1
N0.C1.D1.R0.S14: RcvEn: plus1 = 1, minus1 = 0, PI = 23, DB = 0
N2.C3.D0.R0.S00: PI = 063, PtrOffset = 004
N4.C2.D0.R0.S08: PI = 055, PtrOffset = 004
N6.C1.D1.R0.S17: RcvEn: plus1 = 1, minus1 = 0, PI = 58, DB = 1
N0.C1.D1.R0.S15: RcvEn: plus1 = 1, minus1 = 0, PI = 44, DB = 0
N2.C3.D0.R0.S01: PI = 038, PtrOffset = 004
N4.C2.D0.R0.S00: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N6.C1.D1.R1.S00: RcvEn: plus1 = 1, minus1 = 0, PI = 22, DB = 0
N0.C1.D1.R0.S16: RcvEn: plus1 = 1, minus1 = 0, PI = 01, DB = 1
N2.C3.D0.R0.S02: PI = 012, PtrOffset = 004
N4.C2.D0.R0.S01: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N6.C1.D1.R1.S01: RcvEn: plus1 = 1, minus1 = 0, PI = 63, DB = 1
N0.C1.D1.R0.S17: RcvEn: plus1 = 1, minus1 = 0, PI = 49, DB = 1
N2.C3.D0.R0.S03: PI = 053, PtrOffset = 005
N4.C2.D0.R0.S02: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N6.C1.D1.R1.S02: RcvEn: plus1 = 1, minus1 = 0, PI = 32, DB = 0
N0.C1.D1.R1.S00: RcvEn: plus1 = 1, minus1 = 0, PI = 10, DB = 1
N2.C3.D0.R0.S04: PI = 049, PtrOffset = 005
N4.C2.D0.R0.S03: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N6.C1.D1.R1.S03: RcvEn: plus1 = 1, minus1 = 0, PI = 11, DB = 1
N0.C1.D1.R1.S01: RcvEn: plus1 = 1, minus1 = 0, PI = 51, DB = 1
N2.C3.D0.R0.S05: PI = 009, PtrOffset = 004
N4.C2.D0.R0.S04: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N6.C1.D1.R1.S04: RcvEn: plus1 = 1, minus1 = 0, PI = 07, DB = 1
N0.C1.D1.R1.S02: RcvEn: plus1 = 1, minus1 = 0, PI = 22, DB = 0
N2.C3.D0.R0.S06: PI = 033, PtrOffset = 004
N4.C2.D0.R0.S05: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N6.C1.D1.R1.S05: RcvEn: plus1 = 1, minus1 = 0, PI = 31, DB = 0
N0.C1.D1.R1.S03: RcvEn: plus1 = 1, minus1 = 0, PI = 04, DB = 1
N2.C3.D0.R0.S07: PI = 054, PtrOffset = 004
N4.C2.D0.R0.S06: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N6.C1.D1.R1.S06: RcvEn: plus1 = 1, minus1 = 0, PI = 54, DB = 1
N0.C1.D1.R1.S04: RcvEn: plus1 = 1, minus1 = 0, PI = 58, DB = 1
N2.C3.D0.R0.S08: PI = 034, PtrOffset = 005
N4.C2.D0.R0.S07: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N6.C1.D1.R1.S07: RcvEn: plus1 = 1, minus1 = 0, PI = 10, DB = 1
N0.C1.D1.R1.S05: RcvEn: plus1 = 1, minus1 = 0, PI = 22, DB = 0
N2.C3.D0.R0.S00: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N4.C2.D0.R0.S08: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N6.C1.D1.R1.S08: RcvEn: plus1 = 1, minus1 = 0, PI = 60, DB = 1
N0.C1.D1.R1.S06: RcvEn: plus1 = 1, minus1 = 0, PI = 44, DB = 0
N2.C3.D0.R0.S01: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N4.C2.D0.R0.S00: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N6.C1.D1.R1.S09: RcvEn: plus1 = 1, minus1 = 0, PI = 20, DB = 0
N0.C1.D1.R1.S07: RcvEn: plus1 = 1, minus1 = 0, PI = 00, DB = 1
N2.C3.D0.R0.S02: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N4.C2.D0.R0.S01: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N6.C1.D1.R1.S10: RcvEn: plus1 = 0, minus1 = 1, PI = 01, DB = 1
N0.C1.D1.R1.S08: RcvEn: plus1 = 1, minus1 = 0, PI = 47, DB = 0
N2.C3.D0.R0.S03: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N4.C2.D0.R0.S02: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N6.C1.D1.R1.S11: RcvEn: plus1 = 1, minus1 = 0, PI = 33, DB = 0
N0.C1.D1.R1.S09: RcvEn: plus1 = 1, minus1 = 0, PI = 08, DB = 1
N2.C3.D0.R0.S04: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N4.C2.D0.R0.S03: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N6.C1.D1.R1.S12: RcvEn: plus1 = 1, minus1 = 0, PI = 15, DB = 1
N0.C1.D1.R1.S10: RcvEn: plus1 = 1, minus1 = 0, PI = 51, DB = 1
N2.C3.D0.R0.S05: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N4.C2.D0.R0.S04: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N6.C1.D1.R1.S13: RcvEn: plus1 = 1, minus1 = 0, PI = 06, DB = 1
N0.C1.D1.R1.S11: RcvEn: plus1 = 1, minus1 = 0, PI = 23, DB = 0
N2.C3.D0.R0.S06: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N4.C2.D0.R0.S05: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N6.C1.D1.R1.S14: RcvEn: plus1 = 1, minus1 = 0, PI = 31, DB = 0
N0.C1.D1.R1.S12: RcvEn: plus1 = 1, minus1 = 0, PI = 02, DB = 1
N2.C3.D0.R0.S07: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N4.C2.D0.R0.S06: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N6.C1.D1.R1.S15: RcvEn: plus1 = 1, minus1 = 0, PI = 54, DB = 1
N0.C1.D1.R1.S13: RcvEn: plus1 = 1, minus1 = 0, PI = 61, DB = 1
N2.C3.D0.R0.S08: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N4.C2.D0.R0.S07: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N6.C1.D1.R1.S16: RcvEn: plus1 = 1, minus1 = 0, PI = 13, DB = 1
N0.C1.D1.R1.S14: RcvEn: plus1 = 1, minus1 = 0, PI = 23, DB = 0
N2.C3.D0.R0.S00: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N4.C2.D0.R0.S08: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N6.C1.D1.R1.S17: RcvEn: plus1 = 1, minus1 = 0, PI = 58, DB = 1
N0.C1.D1.R1.S15: RcvEn: plus1 = 1, minus1 = 0, PI = 44, DB = 0
N2.C3.D0.R0.S01: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N4.C2.D0.R0.S00: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
STOP_DATA_REC_EN
N0.C1.D1.R1.S16: RcvEn: plus1 = 1, minus1 = 0, PI = 01, DB = 1
N2.C3.D0.R0.S02: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N4.C2.D0.R0.S01: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N6.C2.D0.R0: RcvEnFine: Initial RdCmd2RcvEnLatency = 10, Initial RdPtrOffsetRcvEn = 4
N0.C1.D1.R1.S17: RcvEn: plus1 = 1, minus1 = 0, PI = 49, DB = 1
N2.C3.D0.R0.S03: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N4.C2.D0.R0.S02: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N6.C2.D0.R0.S00: Rcv En Fine Value = 277
STOP_DATA_REC_EN
N2.C3.D0.R0.S04: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N4.C2.D0.R0.S03: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N6.C2.D0.R0.S01: Rcv En Fine Value = 380
N0.C2.D0.R0: RcvEnFine: Initial RdCmd2RcvEnLatency = 10, Initial RdPtrOffsetRcvEn = 4
N2.C3.D0.R0.S05: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N4.C2.D0.R0.S04: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N6.C2.D0.R0.S02: Rcv En Fine Value = 352
N0.C2.D0.R0.S00: Rcv En Fine Value = 273
N2.C3.D0.R0.S06: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N4.C2.D0.R0.S05: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N6.C2.D0.R0.S03: Rcv En Fine Value = 331
N0.C2.D0.R0.S01: Rcv En Fine Value = 380
N2.C3.D0.R0.S07: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N4.C2.D0.R0.S06: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N6.C2.D0.R0.S04: Rcv En Fine Value = 333
N0.C2.D0.R0.S02: Rcv En Fine Value = 348
N2.C3.D0.R0.S08: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N4.C2.D0.R0.S07: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N6.C2.D0.R0.S05: Rcv En Fine Value = 342
N0.C2.D0.R0.S03: Rcv En Fine Value = 327
N2.C3.D0.R0.S00: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N4.C2.D0.R0.S08: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N6.C2.D0.R0.S06: Rcv En Fine Value = 380
N0.C2.D0.R0.S04: Rcv En Fine Value = 329
N2.C3.D0.R0.S01: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N4.C2.D0.R0.S00: Preamble found at Latency = 008
N6.C2.D0.R0.S07: Rcv En Fine Value = 269
N0.C2.D0.R0.S05: Rcv En Fine Value = 341
N2.C3.D0.R0.S02: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N4.C2.D0.R0.S07: Preamble found at Latency = 008
N6.C2.D0.R0.S08: Rcv En Fine Value = 316
N0.C2.D0.R0.S06: Rcv En Fine Value = 378
N2.C3.D0.R0.S03: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N4.C2.D0.R0.S00: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N6.C2.D0.R0.S09: Rcv En Fine Value = 274
N0.C2.D0.R0.S07: Rcv En Fine Value = 270
N2.C3.D0.R0.S04: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N4.C2.D0.R0.S01: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N6.C2.D0.R0.S10: Rcv En Fine Value = 382
N0.C2.D0.R0.S08: Rcv En Fine Value = 316
N2.C3.D0.R0.S05: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N4.C2.D0.R0.S02: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N6.C2.D0.R0.S11: Rcv En Fine Value = 351
N0.C2.D0.R0.S09: Rcv En Fine Value = 274
N2.C3.D0.R0.S06: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N4.C2.D0.R0.S03: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N6.C2.D0.R0.S12: Rcv En Fine Value = 333
N0.C2.D0.R0.S10: Rcv En Fine Value = 376
N2.C3.D0.R0.S07: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N4.C2.D0.R0.S04: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N6.C2.D0.R0.S13: Rcv En Fine Value = 329
N0.C2.D0.R0.S11: Rcv En Fine Value = 348
N2.C3.D0.R0.S08: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N4.C2.D0.R0.S05: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N6.C2.D0.R0.S14: Rcv En Fine Value = 341
N0.C2.D0.R0.S12: Rcv En Fine Value = 328
N2.C3.D0.R0.S00: Preamble found at Latency = 008
N4.C2.D0.R0.S06: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N6.C2.D0.R0.S15: Rcv En Fine Value = 382
N0.C2.D0.R0.S13: Rcv En Fine Value = 330
N2.C3.D0.R0.S01: Preamble found at Latency = 008
N4.C2.D0.R0.S07: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N6.C2.D0.R0.S16: Rcv En Fine Value = 269
N0.C2.D0.R0.S14: Rcv En Fine Value = 341
N2.C3.D0.R0.S02: Preamble found at Latency = 008
N4.C2.D0.R0.S08: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N6.C2.D0.R0.S17: Rcv En Fine Value = 319
N0.C2.D0.R0.S15: Rcv En Fine Value = 378
N2.C3.D0.R0.S05: Preamble found at Latency = 008
N4.C2.D0.R0.S01: Preamble found at Latency = 007
N6.C2.D0.R0: Starting preamble search lower nibbles
N0.C2.D0.R0.S16: Rcv En Fine Value = 270
N2.C3.D0.R0.S06: Preamble found at Latency = 008
N4.C2.D0.R0.S02: Preamble found at Latency = 007
N6.C2.D0.R0.S00: PI = 021, PtrOffset = 004
N0.C2.D0.R0.S17: Rcv En Fine Value = 312
N2.C3.D0.R0.S07: Preamble found at Latency = 008
N4.C2.D0.R0.S03: Preamble found at Latency = 007
N6.C2.D0.R0.S01: PI = 060, PtrOffset = 005
N0.C2.D0.R0: Starting preamble search lower nibbles
N2.C3.D0.R0.S00: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N4.C2.D0.R0.S04: Preamble found at Latency = 007
N6.C2.D0.R0.S02: PI = 032, PtrOffset = 005
N0.C2.D0.R0.S00: PI = 017, PtrOffset = 004
N2.C3.D0.R0.S01: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N4.C2.D0.R0.S05: Preamble found at Latency = 007
N6.C2.D0.R0.S03: PI = 011, PtrOffset = 005
N0.C2.D0.R0.S01: PI = 060, PtrOffset = 005
N2.C3.D0.R0.S02: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N4.C2.D0.R0.S06: Preamble found at Latency = 007
N6.C2.D0.R0.S04: PI = 013, PtrOffset = 005
N0.C2.D0.R0.S02: PI = 028, PtrOffset = 005
N2.C3.D0.R0.S03: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N4.C2.D0.R0.S08: Preamble found at Latency = 007
N6.C2.D0.R0.S05: PI = 022, PtrOffset = 005
N0.C2.D0.R0.S03: PI = 007, PtrOffset = 005
N2.C3.D0.R0.S04: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N4.C2.D0.R0.S00: Total Receive Enable Delay = 1327
N6.C2.D0.R0.S06: PI = 060, PtrOffset = 005
N0.C2.D0.R0.S04: PI = 009, PtrOffset = 005
N2.C3.D0.R0.S05: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N4.C2.D0.R0.S01: Total Receive Enable Delay = 1302
N6.C2.D0.R0.S07: PI = 013, PtrOffset = 004
N0.C2.D0.R0.S05: PI = 021, PtrOffset = 005
N2.C3.D0.R0.S06: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N4.C2.D0.R0.S02: Total Receive Enable Delay = 1274
N6.C2.D0.R0.S08: PI = 060, PtrOffset = 004
N0.C2.D0.R0.S06: PI = 058, PtrOffset = 005
N2.C3.D0.R0.S07: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N4.C2.D0.R0.S03: Total Receive Enable Delay = 1252
N6.C2.D0.R0.S00: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N0.C2.D0.R0.S07: PI = 014, PtrOffset = 004
N2.C3.D0.R0.S08: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N4.C2.D0.R0.S04: Total Receive Enable Delay = 1254
N6.C2.D0.R0.S01: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N0.C2.D0.R0.S08: PI = 060, PtrOffset = 004
N2.C3.D0.R0.S03: Preamble found at Latency = 007
N4.C2.D0.R0.S05: Total Receive Enable Delay = 1264
N6.C2.D0.R0.S02: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N0.C2.D0.R0.S00: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N2.C3.D0.R0.S04: Preamble found at Latency = 007
N4.C2.D0.R0.S06: Total Receive Enable Delay = 1302
N6.C2.D0.R0.S03: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N0.C2.D0.R0.S01: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N2.C3.D0.R0.S08: Preamble found at Latency = 007
N4.C2.D0.R0.S07: Total Receive Enable Delay = 1318
N6.C2.D0.R0.S04: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N0.C2.D0.R0.S02: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N2.C3.D0.R0.S00: Total Receive Enable Delay = 1375
N4.C2.D0.R0.S08: Total Receive Enable Delay = 1239
N6.C2.D0.R0.S05: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N0.C2.D0.R0.S03: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N2.C3.D0.R0.S01: Total Receive Enable Delay = 1350
N4.C2.D0.R0: Starting preamble search upper nibbles
N6.C2.D0.R0.S06: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N0.C2.D0.R0.S04: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N2.C3.D0.R0.S02: Total Receive Enable Delay = 1324
N4.C2.D0.R0.S09: PI = 012, PtrOffset = 004
N6.C2.D0.R0.S07: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N0.C2.D0.R0.S05: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N2.C3.D0.R0.S03: Total Receive Enable Delay = 1301
N4.C2.D0.R0.S10: PI = 054, PtrOffset = 005
N6.C2.D0.R0.S08: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N0.C2.D0.R0.S06: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N2.C3.D0.R0.S04: Total Receive Enable Delay = 1297
N4.C2.D0.R0.S11: PI = 021, PtrOffset = 005
N6.C2.D0.R0.S00: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N0.C2.D0.R0.S07: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N2.C3.D0.R0.S05: Total Receive Enable Delay = 1321
N4.C2.D0.R0.S12: PI = 003, PtrOffset = 005
N6.C2.D0.R0.S01: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N0.C2.D0.R0.S08: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N2.C3.D0.R0.S06: Total Receive Enable Delay = 1345
N4.C2.D0.R0.S13: PI = 003, PtrOffset = 005
N6.C2.D0.R0.S02: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N0.C2.D0.R0.S00: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N2.C3.D0.R0.S07: Total Receive Enable Delay = 1366
N4.C2.D0.R0.S14: PI = 019, PtrOffset = 005
N6.C2.D0.R0.S03: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N0.C2.D0.R0.S01: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N2.C3.D0.R0.S08: Total Receive Enable Delay = 1282
N4.C2.D0.R0.S15: PI = 054, PtrOffset = 005
N6.C2.D0.R0.S04: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N0.C2.D0.R0.S02: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N2.C3.D0.R0: Starting preamble search upper nibbles
N4.C2.D0.R0.S16: PI = 007, PtrOffset = 004
N6.C2.D0.R0.S05: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N0.C2.D0.R0.S03: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N2.C3.D0.R0.S09: PI = 063, PtrOffset = 004
N4.C2.D0.R0.S17: PI = 051, PtrOffset = 004
N6.C2.D0.R0.S06: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N0.C2.D0.R0.S04: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N2.C3.D0.R0.S10: PI = 039, PtrOffset = 004
N4.C2.D0.R0.S09: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N6.C2.D0.R0.S07: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N0.C2.D0.R0.S05: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N2.C3.D0.R0.S11: PI = 011, PtrOffset = 004
N4.C2.D0.R0.S10: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N6.C2.D0.R0.S08: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N0.C2.D0.R0.S06: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N2.C3.D0.R0.S12: PI = 054, PtrOffset = 005
N4.C2.D0.R0.S11: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N6.C2.D0.R0.S00: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N0.C2.D0.R0.S07: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N2.C3.D0.R0.S13: PI = 050, PtrOffset = 005
N4.C2.D0.R0.S12: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N6.C2.D0.R0.S01: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N0.C2.D0.R0.S08: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N2.C3.D0.R0.S14: PI = 011, PtrOffset = 004
N4.C2.D0.R0.S13: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N6.C2.D0.R0.S02: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N0.C2.D0.R0.S00: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N2.C3.D0.R0.S15: PI = 034, PtrOffset = 004
N4.C2.D0.R0.S14: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N6.C2.D0.R0.S03: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N0.C2.D0.R0.S01: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N2.C3.D0.R0.S16: PI = 056, PtrOffset = 004
N4.C2.D0.R0.S15: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N6.C2.D0.R0.S04: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N0.C2.D0.R0.S02: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N2.C3.D0.R0.S17: PI = 037, PtrOffset = 005
N4.C2.D0.R0.S16: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N6.C2.D0.R0.S05: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N0.C2.D0.R0.S03: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N2.C3.D0.R0.S09: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N4.C2.D0.R0.S17: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N6.C2.D0.R0.S06: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N0.C2.D0.R0.S04: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N2.C3.D0.R0.S10: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N4.C2.D0.R0.S09: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N6.C2.D0.R0.S07: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N0.C2.D0.R0.S05: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N2.C3.D0.R0.S11: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N4.C2.D0.R0.S10: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N6.C2.D0.R0.S08: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N0.C2.D0.R0.S06: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N2.C3.D0.R0.S12: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N4.C2.D0.R0.S11: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N6.C2.D0.R0.S00: Preamble found at Latency = 008
N0.C2.D0.R0.S07: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N2.C3.D0.R0.S13: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N4.C2.D0.R0.S12: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N6.C2.D0.R0.S07: Preamble found at Latency = 008
N0.C2.D0.R0.S08: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N2.C3.D0.R0.S14: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N4.C2.D0.R0.S13: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N6.C2.D0.R0.S00: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N0.C2.D0.R0.S00: Preamble found at Latency = 008
N2.C3.D0.R0.S15: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N4.C2.D0.R0.S14: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N6.C2.D0.R0.S01: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N0.C2.D0.R0.S07: Preamble found at Latency = 008
N2.C3.D0.R0.S16: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N4.C2.D0.R0.S15: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N6.C2.D0.R0.S02: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N0.C2.D0.R0.S00: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N2.C3.D0.R0.S17: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N4.C2.D0.R0.S16: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N6.C2.D0.R0.S03: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N0.C2.D0.R0.S01: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N2.C3.D0.R0.S09: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N4.C2.D0.R0.S17: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N6.C2.D0.R0.S04: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N0.C2.D0.R0.S02: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N2.C3.D0.R0.S10: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N4.C2.D0.R0.S09: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N6.C2.D0.R0.S05: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N0.C2.D0.R0.S03: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N2.C3.D0.R0.S11: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N4.C2.D0.R0.S10: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N6.C2.D0.R0.S06: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N0.C2.D0.R0.S04: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N2.C3.D0.R0.S12: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N4.C2.D0.R0.S11: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N6.C2.D0.R0.S07: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N0.C2.D0.R0.S05: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N2.C3.D0.R0.S13: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N4.C2.D0.R0.S12: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N6.C2.D0.R0.S08: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N0.C2.D0.R0.S06: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N2.C3.D0.R0.S14: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N4.C2.D0.R0.S13: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N6.C2.D0.R0.S01: Preamble found at Latency = 007
N0.C2.D0.R0.S07: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N2.C3.D0.R0.S15: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N4.C2.D0.R0.S14: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N6.C2.D0.R0.S02: Preamble found at Latency = 007
N0.C2.D0.R0.S08: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N2.C3.D0.R0.S16: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N4.C2.D0.R0.S15: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N6.C2.D0.R0.S03: Preamble found at Latency = 007
N0.C2.D0.R0.S01: Preamble found at Latency = 007
N2.C3.D0.R0.S17: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N4.C2.D0.R0.S16: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N6.C2.D0.R0.S04: Preamble found at Latency = 007
N0.C2.D0.R0.S02: Preamble found at Latency = 007
N2.C3.D0.R0.S09: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N4.C2.D0.R0.S17: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N6.C2.D0.R0.S05: Preamble found at Latency = 007
N0.C2.D0.R0.S03: Preamble found at Latency = 007
N2.C3.D0.R0.S10: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N4.C2.D0.R0.S09: Preamble found at Latency = 008
N6.C2.D0.R0.S06: Preamble found at Latency = 007
N0.C2.D0.R0.S04: Preamble found at Latency = 007
N2.C3.D0.R0.S11: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N4.C2.D0.R0.S16: Preamble found at Latency = 008
N6.C2.D0.R0.S08: Preamble found at Latency = 007
N0.C2.D0.R0.S05: Preamble found at Latency = 007
N2.C3.D0.R0.S12: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N4.C2.D0.R0.S09: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N6.C2.D0.R0.S00: Total Receive Enable Delay = 1333
N0.C2.D0.R0.S06: Preamble found at Latency = 007
N2.C3.D0.R0.S13: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N4.C2.D0.R0.S10: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N6.C2.D0.R0.S01: Total Receive Enable Delay = 1308
N0.C2.D0.R0.S08: Preamble found at Latency = 007
N2.C3.D0.R0.S14: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N4.C2.D0.R0.S11: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N6.C2.D0.R0.S02: Total Receive Enable Delay = 1280
N0.C2.D0.R0.S00: Total Receive Enable Delay = 1329
N2.C3.D0.R0.S15: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N4.C2.D0.R0.S12: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N6.C2.D0.R0.S03: Total Receive Enable Delay = 1259
N0.C2.D0.R0.S01: Total Receive Enable Delay = 1308
N2.C3.D0.R0.S16: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N4.C2.D0.R0.S13: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N6.C2.D0.R0.S04: Total Receive Enable Delay = 1261
N0.C2.D0.R0.S02: Total Receive Enable Delay = 1276
N2.C3.D0.R0.S17: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N4.C2.D0.R0.S14: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N6.C2.D0.R0.S05: Total Receive Enable Delay = 1270
N0.C2.D0.R0.S03: Total Receive Enable Delay = 1255
N2.C3.D0.R0.S09: Preamble found at Latency = 008
N4.C2.D0.R0.S15: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N6.C2.D0.R0.S06: Total Receive Enable Delay = 1308
N0.C2.D0.R0.S04: Total Receive Enable Delay = 1257
N2.C3.D0.R0.S10: Preamble found at Latency = 008
N4.C2.D0.R0.S16: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N6.C2.D0.R0.S07: Total Receive Enable Delay = 1325
N0.C2.D0.R0.S05: Total Receive Enable Delay = 1269
N2.C3.D0.R0.S11: Preamble found at Latency = 008
N4.C2.D0.R0.S17: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N6.C2.D0.R0.S08: Total Receive Enable Delay = 1244
N0.C2.D0.R0.S06: Total Receive Enable Delay = 1306
N2.C3.D0.R0.S14: Preamble found at Latency = 008
N4.C2.D0.R0.S10: Preamble found at Latency = 007
N6.C2.D0.R0: Starting preamble search upper nibbles
N0.C2.D0.R0.S07: Total Receive Enable Delay = 1326
N2.C3.D0.R0.S15: Preamble found at Latency = 008
N4.C2.D0.R0.S11: Preamble found at Latency = 007
N6.C2.D0.R0.S09: PI = 018, PtrOffset = 004
N0.C2.D0.R0.S08: Total Receive Enable Delay = 1244
N2.C3.D0.R0.S16: Preamble found at Latency = 008
N4.C2.D0.R0.S12: Preamble found at Latency = 007
N6.C2.D0.R0.S10: PI = 062, PtrOffset = 005
N0.C2.D0.R0: Starting preamble search upper nibbles
N2.C3.D0.R0.S09: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N4.C2.D0.R0.S13: Preamble found at Latency = 007
N6.C2.D0.R0.S11: PI = 031, PtrOffset = 005
N0.C2.D0.R0.S09: PI = 018, PtrOffset = 004
N2.C3.D0.R0.S10: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N4.C2.D0.R0.S14: Preamble found at Latency = 007
N6.C2.D0.R0.S12: PI = 013, PtrOffset = 005
N0.C2.D0.R0.S10: PI = 056, PtrOffset = 005
N2.C3.D0.R0.S11: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N4.C2.D0.R0.S15: Preamble found at Latency = 007
N6.C2.D0.R0.S13: PI = 009, PtrOffset = 005
N0.C2.D0.R0.S11: PI = 028, PtrOffset = 005
N2.C3.D0.R0.S12: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N4.C2.D0.R0.S17: Preamble found at Latency = 007
N6.C2.D0.R0.S14: PI = 021, PtrOffset = 005
N0.C2.D0.R0.S12: PI = 008, PtrOffset = 005
N2.C3.D0.R0.S13: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N4.C2.D0.R0: Preamble found for all upper nibbles, adjusting Pi, Offset to center into preamble
N6.C2.D0.R0.S15: PI = 062, PtrOffset = 005
N0.C2.D0.R0.S13: PI = 010, PtrOffset = 005
N2.C3.D0.R0.S14: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N4.C2.D0.R0.S09: Total Receive Enable Delay = 1324
N6.C2.D0.R0.S16: PI = 013, PtrOffset = 004
N0.C2.D0.R0.S14: PI = 021, PtrOffset = 005
N2.C3.D0.R0.S15: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N4.C2.D0.R0.S10: Total Receive Enable Delay = 1302
N6.C2.D0.R0.S17: PI = 063, PtrOffset = 004
N0.C2.D0.R0.S15: PI = 058, PtrOffset = 005
N2.C3.D0.R0.S16: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N4.C2.D0.R0.S11: Total Receive Enable Delay = 1269
N6.C2.D0.R0.S09: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N0.C2.D0.R0.S16: PI = 014, PtrOffset = 004
N2.C3.D0.R0.S17: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N4.C2.D0.R0.S12: Total Receive Enable Delay = 1251
N6.C2.D0.R0.S10: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N0.C2.D0.R0.S17: PI = 056, PtrOffset = 004
N2.C3.D0.R0.S12: Preamble found at Latency = 007
N4.C2.D0.R0.S13: Total Receive Enable Delay = 1251
N6.C2.D0.R0.S11: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N0.C2.D0.R0.S09: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N2.C3.D0.R0.S13: Preamble found at Latency = 007
N4.C2.D0.R0.S14: Total Receive Enable Delay = 1267
N6.C2.D0.R0.S12: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N0.C2.D0.R0.S10: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N2.C3.D0.R0.S17: Preamble found at Latency = 007
N4.C2.D0.R0.S15: Total Receive Enable Delay = 1302
N6.C2.D0.R0.S13: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N0.C2.D0.R0.S11: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N2.C3.D0.R0: Preamble found for all upper nibbles, adjusting Pi, Offset to center into preamble
N4.C2.D0.R0.S16: Total Receive Enable Delay = 1319
N6.C2.D0.R0.S14: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N0.C2.D0.R0.S12: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N2.C3.D0.R0.S09: Total Receive Enable Delay = 1375
N4.C2.D0.R0.S17: Total Receive Enable Delay = 1235
N6.C2.D0.R0.S15: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N0.C2.D0.R0.S13: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N2.C3.D0.R0.S10: Total Receive Enable Delay = 1351
N4.C2.D0.R1: RcvEnFine: Initial RdCmd2RcvEnLatency = 10, Initial RdPtrOffsetRcvEn = 4
N6.C2.D0.R0.S16: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N0.C2.D0.R0.S14: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N2.C3.D0.R0.S11: Total Receive Enable Delay = 1323
N4.C2.D0.R1.S00: Rcv En Fine Value = 270
N6.C2.D0.R0.S17: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N0.C2.D0.R0.S15: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N2.C3.D0.R0.S12: Total Receive Enable Delay = 1302
N4.C2.D0.R1.S01: Rcv En Fine Value = 375
N6.C2.D0.R0.S09: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N0.C2.D0.R0.S16: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N2.C3.D0.R0.S13: Total Receive Enable Delay = 1298
N4.C2.D0.R1.S02: Rcv En Fine Value = 344
N6.C2.D0.R0.S10: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N0.C2.D0.R0.S17: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N2.C3.D0.R0.S14: Total Receive Enable Delay = 1323
N4.C2.D0.R1.S03: Rcv En Fine Value = 321
N6.C2.D0.R0.S11: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N0.C2.D0.R0.S09: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N2.C3.D0.R0.S15: Total Receive Enable Delay = 1346
N4.C2.D0.R1.S04: Rcv En Fine Value = 323
N6.C2.D0.R0.S12: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N0.C2.D0.R0.S10: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N2.C3.D0.R0.S16: Total Receive Enable Delay = 1368
N4.C2.D0.R1.S05: Rcv En Fine Value = 334
N6.C2.D0.R0.S13: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N0.C2.D0.R0.S11: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N2.C3.D0.R0.S17: Total Receive Enable Delay = 1285
N4.C2.D0.R1.S06: Rcv En Fine Value = 375
N6.C2.D0.R0.S14: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N0.C2.D0.R0.S12: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N2.C3.D0.R1: RcvEnFine: Initial RdCmd2RcvEnLatency = 10, Initial RdPtrOffsetRcvEn = 4
N4.C2.D0.R1.S07: Rcv En Fine Value = 262
N6.C2.D0.R0.S15: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N0.C2.D0.R0.S13: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N2.C3.D0.R1.S00: Rcv En Fine Value = 317
N4.C2.D0.R1.S08: Rcv En Fine Value = 311
N6.C2.D0.R0.S16: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N0.C2.D0.R0.S14: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N2.C3.D0.R1.S01: Rcv En Fine Value = 296
N4.C2.D0.R1.S09: Rcv En Fine Value = 267
N6.C2.D0.R0.S17: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N0.C2.D0.R0.S15: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N2.C3.D0.R1.S02: Rcv En Fine Value = 267
N4.C2.D0.R1.S10: Rcv En Fine Value = 375
N6.C2.D0.R0.S09: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N0.C2.D0.R0.S16: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N2.C3.D0.R1.S03: Rcv En Fine Value = 374
N4.C2.D0.R1.S11: Rcv En Fine Value = 343
N6.C2.D0.R0.S10: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N0.C2.D0.R0.S17: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N2.C3.D0.R1.S04: Rcv En Fine Value = 368
N4.C2.D0.R1.S12: Rcv En Fine Value = 323
N6.C2.D0.R0.S11: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N0.C2.D0.R0.S09: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N2.C3.D0.R1.S05: Rcv En Fine Value = 265
N4.C2.D0.R1.S13: Rcv En Fine Value = 322
N6.C2.D0.R0.S12: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N0.C2.D0.R0.S10: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N2.C3.D0.R1.S06: Rcv En Fine Value = 289
N4.C2.D0.R1.S14: Rcv En Fine Value = 337
N6.C2.D0.R0.S13: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N0.C2.D0.R0.S11: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N2.C3.D0.R1.S07: Rcv En Fine Value = 311
N4.C2.D0.R1.S15: Rcv En Fine Value = 374
N6.C2.D0.R0.S14: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N0.C2.D0.R0.S12: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N2.C3.D0.R1.S08: Rcv En Fine Value = 355
N4.C2.D0.R1.S16: Rcv En Fine Value = 264
N6.C2.D0.R0.S15: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N0.C2.D0.R0.S13: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N2.C3.D0.R1.S09: Rcv En Fine Value = 319
N4.C2.D0.R1.S17: Rcv En Fine Value = 309
N6.C2.D0.R0.S16: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N0.C2.D0.R0.S14: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N2.C3.D0.R1.S10: Rcv En Fine Value = 297
N4.C2.D0.R1: Starting preamble search lower nibbles
N6.C2.D0.R0.S17: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N0.C2.D0.R0.S15: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N2.C3.D0.R1.S11: Rcv En Fine Value = 267
N4.C2.D0.R1.S00: PI = 014, PtrOffset = 004
N6.C2.D0.R0.S09: Preamble found at Latency = 008
N0.C2.D0.R0.S16: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N2.C3.D0.R1.S12: Rcv En Fine Value = 375
N4.C2.D0.R1.S01: PI = 055, PtrOffset = 005
N6.C2.D0.R0.S16: Preamble found at Latency = 008
N0.C2.D0.R0.S17: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N2.C3.D0.R1.S13: Rcv En Fine Value = 371
N4.C2.D0.R1.S02: PI = 024, PtrOffset = 005
N6.C2.D0.R0.S09: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N0.C2.D0.R0.S09: Preamble found at Latency = 008
N2.C3.D0.R1.S14: Rcv En Fine Value = 264
N4.C2.D0.R1.S03: PI = 001, PtrOffset = 005
N6.C2.D0.R0.S10: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N0.C2.D0.R0.S16: Preamble found at Latency = 008
N2.C3.D0.R1.S15: Rcv En Fine Value = 290
N4.C2.D0.R1.S04: PI = 003, PtrOffset = 005
N6.C2.D0.R0.S11: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N0.C2.D0.R0.S09: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N2.C3.D0.R1.S16: Rcv En Fine Value = 313
N4.C2.D0.R1.S05: PI = 014, PtrOffset = 005
N6.C2.D0.R0.S12: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N0.C2.D0.R0.S10: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N2.C3.D0.R1.S17: Rcv En Fine Value = 356
N4.C2.D0.R1.S06: PI = 055, PtrOffset = 005
N6.C2.D0.R0.S13: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N0.C2.D0.R0.S11: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N2.C3.D0.R1: Starting preamble search lower nibbles
N4.C2.D0.R1.S07: PI = 006, PtrOffset = 004
N6.C2.D0.R0.S14: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N0.C2.D0.R0.S12: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N2.C3.D0.R1.S00: PI = 061, PtrOffset = 004
N4.C2.D0.R1.S08: PI = 055, PtrOffset = 004
N6.C2.D0.R0.S15: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N0.C2.D0.R0.S13: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N2.C3.D0.R1.S01: PI = 040, PtrOffset = 004
N4.C2.D0.R1.S00: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N6.C2.D0.R0.S16: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N0.C2.D0.R0.S14: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N2.C3.D0.R1.S02: PI = 011, PtrOffset = 004
N4.C2.D0.R1.S01: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N6.C2.D0.R0.S17: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N0.C2.D0.R0.S15: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N2.C3.D0.R1.S03: PI = 054, PtrOffset = 005
N4.C2.D0.R1.S02: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N6.C2.D0.R0.S10: Preamble found at Latency = 007
N0.C2.D0.R0.S16: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N2.C3.D0.R1.S04: PI = 048, PtrOffset = 005
N4.C2.D0.R1.S03: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N6.C2.D0.R0.S11: Preamble found at Latency = 007
N0.C2.D0.R0.S17: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N2.C3.D0.R1.S05: PI = 009, PtrOffset = 004
N4.C2.D0.R1.S04: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N6.C2.D0.R0.S12: Preamble found at Latency = 007
N0.C2.D0.R0.S10: Preamble found at Latency = 007
N2.C3.D0.R1.S06: PI = 033, PtrOffset = 004
N4.C2.D0.R1.S05: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N6.C2.D0.R0.S13: Preamble found at Latency = 007
N0.C2.D0.R0.S11: Preamble found at Latency = 007
N2.C3.D0.R1.S07: PI = 055, PtrOffset = 004
N4.C2.D0.R1.S06: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N6.C2.D0.R0.S14: Preamble found at Latency = 007
N0.C2.D0.R0.S12: Preamble found at Latency = 007
N2.C3.D0.R1.S08: PI = 035, PtrOffset = 005
N4.C2.D0.R1.S07: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N6.C2.D0.R0.S15: Preamble found at Latency = 007
N0.C2.D0.R0.S13: Preamble found at Latency = 007
N2.C3.D0.R1.S00: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N4.C2.D0.R1.S08: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N6.C2.D0.R0.S17: Preamble found at Latency = 007
N0.C2.D0.R0.S14: Preamble found at Latency = 007
N2.C3.D0.R1.S01: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N4.C2.D0.R1.S00: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N6.C2.D0.R0: Preamble found for all upper nibbles, adjusting Pi, Offset to center into preamble
N0.C2.D0.R0.S15: Preamble found at Latency = 007
N2.C3.D0.R1.S02: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N4.C2.D0.R1.S01: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N6.C2.D0.R0.S09: Total Receive Enable Delay = 1330
N0.C2.D0.R0.S17: Preamble found at Latency = 007
N2.C3.D0.R1.S03: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N4.C2.D0.R1.S02: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N6.C2.D0.R0.S10: Total Receive Enable Delay = 1310
N0.C2.D0.R0: Preamble found for all upper nibbles, adjusting Pi, Offset to center into preamble
N2.C3.D0.R1.S04: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N4.C2.D0.R1.S03: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N6.C2.D0.R0.S11: Total Receive Enable Delay = 1279
N0.C2.D0.R0.S09: Total Receive Enable Delay = 1330
N2.C3.D0.R1.S05: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N4.C2.D0.R1.S04: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N6.C2.D0.R0.S12: Total Receive Enable Delay = 1261
N0.C2.D0.R0.S10: Total Receive Enable Delay = 1304
N2.C3.D0.R1.S06: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N4.C2.D0.R1.S05: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N6.C2.D0.R0.S13: Total Receive Enable Delay = 1257
N0.C2.D0.R0.S11: Total Receive Enable Delay = 1276
N2.C3.D0.R1.S07: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N4.C2.D0.R1.S06: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N6.C2.D0.R0.S14: Total Receive Enable Delay = 1269
N0.C2.D0.R0.S12: Total Receive Enable Delay = 1256
N2.C3.D0.R1.S08: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N4.C2.D0.R1.S07: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N6.C2.D0.R0.S15: Total Receive Enable Delay = 1310
N0.C2.D0.R0.S13: Total Receive Enable Delay = 1258
N2.C3.D0.R1.S00: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N4.C2.D0.R1.S08: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N6.C2.D0.R0.S16: Total Receive Enable Delay = 1325
N0.C2.D0.R0.S14: Total Receive Enable Delay = 1269
N2.C3.D0.R1.S01: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N4.C2.D0.R1.S00: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N6.C2.D0.R0.S17: Total Receive Enable Delay = 1247
N0.C2.D0.R0.S15: Total Receive Enable Delay = 1306
N2.C3.D0.R1.S02: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N4.C2.D0.R1.S01: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N6.C2.D0.R1: RcvEnFine: Initial RdCmd2RcvEnLatency = 10, Initial RdPtrOffsetRcvEn = 4
N0.C2.D0.R0.S16: Total Receive Enable Delay = 1326
N2.C3.D0.R1.S03: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N4.C2.D0.R1.S02: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N6.C2.D0.R1.S00: Rcv En Fine Value = 275
N0.C2.D0.R0.S17: Total Receive Enable Delay = 1240
N2.C3.D0.R1.S04: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N4.C2.D0.R1.S03: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N6.C2.D0.R1.S01: Rcv En Fine Value = 376
N0.C2.D0.R1: RcvEnFine: Initial RdCmd2RcvEnLatency = 10, Initial RdPtrOffsetRcvEn = 4
N2.C3.D0.R1.S05: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N4.C2.D0.R1.S04: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N6.C2.D0.R1.S02: Rcv En Fine Value = 350
N0.C2.D0.R1.S00: Rcv En Fine Value = 273
N2.C3.D0.R1.S06: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N4.C2.D0.R1.S05: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N6.C2.D0.R1.S03: Rcv En Fine Value = 330
N0.C2.D0.R1.S01: Rcv En Fine Value = 380
N2.C3.D0.R1.S07: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N4.C2.D0.R1.S06: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N6.C2.D0.R1.S04: Rcv En Fine Value = 331
N0.C2.D0.R1.S02: Rcv En Fine Value = 350
N2.C3.D0.R1.S08: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N4.C2.D0.R1.S07: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N6.C2.D0.R1.S05: Rcv En Fine Value = 342
N0.C2.D0.R1.S03: Rcv En Fine Value = 327
N2.C3.D0.R1.S00: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N4.C2.D0.R1.S08: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N6.C2.D0.R1.S06: Rcv En Fine Value = 383
N0.C2.D0.R1.S04: Rcv En Fine Value = 329
N2.C3.D0.R1.S01: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N4.C2.D0.R1.S00: Preamble found at Latency = 008
N6.C2.D0.R1.S07: Rcv En Fine Value = 270
N0.C2.D0.R1.S05: Rcv En Fine Value = 341
N2.C3.D0.R1.S02: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N4.C2.D0.R1.S07: Preamble found at Latency = 008
N6.C2.D0.R1.S08: Rcv En Fine Value = 315
N0.C2.D0.R1.S06: Rcv En Fine Value = 379
N2.C3.D0.R1.S03: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N4.C2.D0.R1.S00: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N6.C2.D0.R1.S09: Rcv En Fine Value = 273
N0.C2.D0.R1.S07: Rcv En Fine Value = 269
N2.C3.D0.R1.S04: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N4.C2.D0.R1.S01: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N6.C2.D0.R1.S10: Rcv En Fine Value = 381
N0.C2.D0.R1.S08: Rcv En Fine Value = 317
N2.C3.D0.R1.S05: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N4.C2.D0.R1.S02: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N6.C2.D0.R1.S11: Rcv En Fine Value = 349
N0.C2.D0.R1.S09: Rcv En Fine Value = 272
N2.C3.D0.R1.S06: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N4.C2.D0.R1.S03: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N6.C2.D0.R1.S12: Rcv En Fine Value = 331
N0.C2.D0.R1.S10: Rcv En Fine Value = 379
N2.C3.D0.R1.S07: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N4.C2.D0.R1.S04: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N6.C2.D0.R1.S13: Rcv En Fine Value = 330
N0.C2.D0.R1.S11: Rcv En Fine Value = 349
N2.C3.D0.R1.S08: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N4.C2.D0.R1.S05: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N6.C2.D0.R1.S14: Rcv En Fine Value = 341
N0.C2.D0.R1.S12: Rcv En Fine Value = 328
N2.C3.D0.R1.S00: Preamble found at Latency = 008
N4.C2.D0.R1.S06: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N6.C2.D0.R1.S15: Rcv En Fine Value = 383
N0.C2.D0.R1.S13: Rcv En Fine Value = 329
N2.C3.D0.R1.S01: Preamble found at Latency = 008
N4.C2.D0.R1.S07: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N6.C2.D0.R1.S16: Rcv En Fine Value = 270
N0.C2.D0.R1.S14: Rcv En Fine Value = 340
N2.C3.D0.R1.S02: Preamble found at Latency = 008
N4.C2.D0.R1.S08: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N6.C2.D0.R1.S17: Rcv En Fine Value = 319
N0.C2.D0.R1.S15: Rcv En Fine Value = 379
N2.C3.D0.R1.S05: Preamble found at Latency = 008
N4.C2.D0.R1.S01: Preamble found at Latency = 007
N6.C2.D0.R1: Starting preamble search lower nibbles
N0.C2.D0.R1.S16: Rcv En Fine Value = 269
N2.C3.D0.R1.S06: Preamble found at Latency = 008
N4.C2.D0.R1.S02: Preamble found at Latency = 007
N6.C2.D0.R1.S00: PI = 019, PtrOffset = 004
N0.C2.D0.R1.S17: Rcv En Fine Value = 311
N2.C3.D0.R1.S07: Preamble found at Latency = 008
N4.C2.D0.R1.S03: Preamble found at Latency = 007
N6.C2.D0.R1.S01: PI = 056, PtrOffset = 005
N0.C2.D0.R1: Starting preamble search lower nibbles
N2.C3.D0.R1.S00: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N4.C2.D0.R1.S04: Preamble found at Latency = 007
N6.C2.D0.R1.S02: PI = 030, PtrOffset = 005
N0.C2.D0.R1.S00: PI = 017, PtrOffset = 004
N2.C3.D0.R1.S01: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N4.C2.D0.R1.S05: Preamble found at Latency = 007
N6.C2.D0.R1.S03: PI = 010, PtrOffset = 005
N0.C2.D0.R1.S01: PI = 060, PtrOffset = 005
N2.C3.D0.R1.S02: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N4.C2.D0.R1.S06: Preamble found at Latency = 007
N6.C2.D0.R1.S04: PI = 011, PtrOffset = 005
N0.C2.D0.R1.S02: PI = 030, PtrOffset = 005
N2.C3.D0.R1.S03: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N4.C2.D0.R1.S08: Preamble found at Latency = 007
N6.C2.D0.R1.S05: PI = 022, PtrOffset = 005
N0.C2.D0.R1.S03: PI = 007, PtrOffset = 005
N2.C3.D0.R1.S04: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N4.C2.D0.R1.S00: Total Receive Enable Delay = 1326
N6.C2.D0.R1.S06: PI = 063, PtrOffset = 005
N0.C2.D0.R1.S04: PI = 009, PtrOffset = 005
N2.C3.D0.R1.S05: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N4.C2.D0.R1.S01: Total Receive Enable Delay = 1303
N6.C2.D0.R1.S07: PI = 014, PtrOffset = 004
N0.C2.D0.R1.S05: PI = 021, PtrOffset = 005
N2.C3.D0.R1.S06: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N4.C2.D0.R1.S02: Total Receive Enable Delay = 1272
N6.C2.D0.R1.S08: PI = 059, PtrOffset = 004
N0.C2.D0.R1.S06: PI = 059, PtrOffset = 005
N2.C3.D0.R1.S07: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N4.C2.D0.R1.S03: Total Receive Enable Delay = 1249
N6.C2.D0.R1.S00: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N0.C2.D0.R1.S07: PI = 013, PtrOffset = 004
N2.C3.D0.R1.S08: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N4.C2.D0.R1.S04: Total Receive Enable Delay = 1251
N6.C2.D0.R1.S01: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N0.C2.D0.R1.S08: PI = 061, PtrOffset = 004
N2.C3.D0.R1.S03: Preamble found at Latency = 007
N4.C2.D0.R1.S05: Total Receive Enable Delay = 1262
N6.C2.D0.R1.S02: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N0.C2.D0.R1.S00: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N2.C3.D0.R1.S04: Preamble found at Latency = 007
N4.C2.D0.R1.S06: Total Receive Enable Delay = 1303
N6.C2.D0.R1.S03: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N0.C2.D0.R1.S01: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N2.C3.D0.R1.S08: Preamble found at Latency = 007
N4.C2.D0.R1.S07: Total Receive Enable Delay = 1318
N6.C2.D0.R1.S04: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N0.C2.D0.R1.S02: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N2.C3.D0.R1.S00: Total Receive Enable Delay = 1373
N4.C2.D0.R1.S08: Total Receive Enable Delay = 1239
N6.C2.D0.R1.S05: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N0.C2.D0.R1.S03: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N2.C3.D0.R1.S01: Total Receive Enable Delay = 1352
N4.C2.D0.R1: Starting preamble search upper nibbles
N6.C2.D0.R1.S06: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N0.C2.D0.R1.S04: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N2.C3.D0.R1.S02: Total Receive Enable Delay = 1323
N4.C2.D0.R1.S09: PI = 011, PtrOffset = 004
N6.C2.D0.R1.S07: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N0.C2.D0.R1.S05: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N2.C3.D0.R1.S03: Total Receive Enable Delay = 1302
N4.C2.D0.R1.S10: PI = 055, PtrOffset = 005
N6.C2.D0.R1.S08: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N0.C2.D0.R1.S06: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N2.C3.D0.R1.S04: Total Receive Enable Delay = 1296
N4.C2.D0.R1.S11: PI = 023, PtrOffset = 005
N6.C2.D0.R1.S00: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N0.C2.D0.R1.S07: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N2.C3.D0.R1.S05: Total Receive Enable Delay = 1321
N4.C2.D0.R1.S12: PI = 003, PtrOffset = 005
N6.C2.D0.R1.S01: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N0.C2.D0.R1.S08: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N2.C3.D0.R1.S06: Total Receive Enable Delay = 1345
N4.C2.D0.R1.S13: PI = 002, PtrOffset = 005
N6.C2.D0.R1.S02: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N0.C2.D0.R1.S00: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N2.C3.D0.R1.S07: Total Receive Enable Delay = 1367
N4.C2.D0.R1.S14: PI = 017, PtrOffset = 005
N6.C2.D0.R1.S03: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N0.C2.D0.R1.S01: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N2.C3.D0.R1.S08: Total Receive Enable Delay = 1283
N4.C2.D0.R1.S15: PI = 054, PtrOffset = 005
N6.C2.D0.R1.S04: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N0.C2.D0.R1.S02: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N2.C3.D0.R1: Starting preamble search upper nibbles
N4.C2.D0.R1.S16: PI = 008, PtrOffset = 004
N6.C2.D0.R1.S05: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N0.C2.D0.R1.S03: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N2.C3.D0.R1.S09: PI = 063, PtrOffset = 004
N4.C2.D0.R1.S17: PI = 053, PtrOffset = 004
N6.C2.D0.R1.S06: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N0.C2.D0.R1.S04: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N2.C3.D0.R1.S10: PI = 041, PtrOffset = 004
N4.C2.D0.R1.S09: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N6.C2.D0.R1.S07: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N0.C2.D0.R1.S05: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N2.C3.D0.R1.S11: PI = 011, PtrOffset = 004
N4.C2.D0.R1.S10: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N6.C2.D0.R1.S08: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N0.C2.D0.R1.S06: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N2.C3.D0.R1.S12: PI = 055, PtrOffset = 005
N4.C2.D0.R1.S11: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N6.C2.D0.R1.S00: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N0.C2.D0.R1.S07: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N2.C3.D0.R1.S13: PI = 051, PtrOffset = 005
N4.C2.D0.R1.S12: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N6.C2.D0.R1.S01: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N0.C2.D0.R1.S08: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N2.C3.D0.R1.S14: PI = 008, PtrOffset = 004
N4.C2.D0.R1.S13: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N6.C2.D0.R1.S02: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N0.C2.D0.R1.S00: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N2.C3.D0.R1.S15: PI = 034, PtrOffset = 004
N4.C2.D0.R1.S14: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N6.C2.D0.R1.S03: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N0.C2.D0.R1.S01: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N2.C3.D0.R1.S16: PI = 057, PtrOffset = 004
N4.C2.D0.R1.S15: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N6.C2.D0.R1.S04: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N0.C2.D0.R1.S02: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N2.C3.D0.R1.S17: PI = 036, PtrOffset = 005
N4.C2.D0.R1.S16: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N6.C2.D0.R1.S05: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N0.C2.D0.R1.S03: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N2.C3.D0.R1.S09: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N4.C2.D0.R1.S17: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N6.C2.D0.R1.S06: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N0.C2.D0.R1.S04: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N2.C3.D0.R1.S10: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N4.C2.D0.R1.S09: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N6.C2.D0.R1.S07: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N0.C2.D0.R1.S05: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N2.C3.D0.R1.S11: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N4.C2.D0.R1.S10: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N6.C2.D0.R1.S08: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N0.C2.D0.R1.S06: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N2.C3.D0.R1.S12: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N4.C2.D0.R1.S11: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N6.C2.D0.R1.S00: Preamble found at Latency = 008
N0.C2.D0.R1.S07: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N2.C3.D0.R1.S13: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N4.C2.D0.R1.S12: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N6.C2.D0.R1.S07: Preamble found at Latency = 008
N0.C2.D0.R1.S08: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N2.C3.D0.R1.S14: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N4.C2.D0.R1.S13: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N6.C2.D0.R1.S00: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N0.C2.D0.R1.S00: Preamble found at Latency = 008
N2.C3.D0.R1.S15: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N4.C2.D0.R1.S14: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N6.C2.D0.R1.S01: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N0.C2.D0.R1.S07: Preamble found at Latency = 008
N2.C3.D0.R1.S16: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N4.C2.D0.R1.S15: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N6.C2.D0.R1.S02: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N0.C2.D0.R1.S00: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N2.C3.D0.R1.S17: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N4.C2.D0.R1.S16: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N6.C2.D0.R1.S03: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N0.C2.D0.R1.S01: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N2.C3.D0.R1.S09: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N4.C2.D0.R1.S17: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N6.C2.D0.R1.S04: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N0.C2.D0.R1.S02: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N2.C3.D0.R1.S10: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N4.C2.D0.R1.S09: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N6.C2.D0.R1.S05: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N0.C2.D0.R1.S03: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N2.C3.D0.R1.S11: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N4.C2.D0.R1.S10: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N6.C2.D0.R1.S06: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N0.C2.D0.R1.S04: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N2.C3.D0.R1.S12: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N4.C2.D0.R1.S11: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N6.C2.D0.R1.S07: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N0.C2.D0.R1.S05: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N2.C3.D0.R1.S13: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N4.C2.D0.R1.S12: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N6.C2.D0.R1.S08: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N0.C2.D0.R1.S06: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N2.C3.D0.R1.S14: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N4.C2.D0.R1.S13: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N6.C2.D0.R1.S01: Preamble found at Latency = 007
N0.C2.D0.R1.S07: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N2.C3.D0.R1.S15: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N4.C2.D0.R1.S14: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N6.C2.D0.R1.S02: Preamble found at Latency = 007
N0.C2.D0.R1.S08: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N2.C3.D0.R1.S16: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N4.C2.D0.R1.S15: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N6.C2.D0.R1.S03: Preamble found at Latency = 007
N0.C2.D0.R1.S01: Preamble found at Latency = 007
N2.C3.D0.R1.S17: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N4.C2.D0.R1.S16: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N6.C2.D0.R1.S04: Preamble found at Latency = 007
N0.C2.D0.R1.S02: Preamble found at Latency = 007
N2.C3.D0.R1.S09: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N4.C2.D0.R1.S17: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N6.C2.D0.R1.S05: Preamble found at Latency = 007
N0.C2.D0.R1.S03: Preamble found at Latency = 007
N2.C3.D0.R1.S10: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N4.C2.D0.R1.S09: Preamble found at Latency = 008
N6.C2.D0.R1.S06: Preamble found at Latency = 007
N0.C2.D0.R1.S04: Preamble found at Latency = 007
N2.C3.D0.R1.S11: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N4.C2.D0.R1.S16: Preamble found at Latency = 008
N6.C2.D0.R1.S08: Preamble found at Latency = 007
N0.C2.D0.R1.S05: Preamble found at Latency = 007
N2.C3.D0.R1.S12: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N4.C2.D0.R1.S09: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N6.C2.D0.R1.S00: Total Receive Enable Delay = 1331
N0.C2.D0.R1.S06: Preamble found at Latency = 007
N2.C3.D0.R1.S13: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N4.C2.D0.R1.S10: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N6.C2.D0.R1.S01: Total Receive Enable Delay = 1304
N0.C2.D0.R1.S08: Preamble found at Latency = 007
N2.C3.D0.R1.S14: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N4.C2.D0.R1.S11: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N6.C2.D0.R1.S02: Total Receive Enable Delay = 1278
N0.C2.D0.R1.S00: Total Receive Enable Delay = 1329
N2.C3.D0.R1.S15: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N4.C2.D0.R1.S12: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N6.C2.D0.R1.S03: Total Receive Enable Delay = 1258
N0.C2.D0.R1.S01: Total Receive Enable Delay = 1308
N2.C3.D0.R1.S16: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N4.C2.D0.R1.S13: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N6.C2.D0.R1.S04: Total Receive Enable Delay = 1259
N0.C2.D0.R1.S02: Total Receive Enable Delay = 1278
N2.C3.D0.R1.S17: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N4.C2.D0.R1.S14: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N6.C2.D0.R1.S05: Total Receive Enable Delay = 1270
N0.C2.D0.R1.S03: Total Receive Enable Delay = 1255
N2.C3.D0.R1.S09: Preamble found at Latency = 008
N4.C2.D0.R1.S15: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N6.C2.D0.R1.S06: Total Receive Enable Delay = 1311
N0.C2.D0.R1.S04: Total Receive Enable Delay = 1257
N2.C3.D0.R1.S10: Preamble found at Latency = 008
N4.C2.D0.R1.S16: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N6.C2.D0.R1.S07: Total Receive Enable Delay = 1326
N0.C2.D0.R1.S05: Total Receive Enable Delay = 1269
N2.C3.D0.R1.S11: Preamble found at Latency = 008
N4.C2.D0.R1.S17: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N6.C2.D0.R1.S08: Total Receive Enable Delay = 1243
N0.C2.D0.R1.S06: Total Receive Enable Delay = 1307
N2.C3.D0.R1.S14: Preamble found at Latency = 008
N4.C2.D0.R1.S10: Preamble found at Latency = 007
N6.C2.D0.R1: Starting preamble search upper nibbles
N0.C2.D0.R1.S07: Total Receive Enable Delay = 1325
N2.C3.D0.R1.S15: Preamble found at Latency = 008
N4.C2.D0.R1.S11: Preamble found at Latency = 007
N6.C2.D0.R1.S09: PI = 017, PtrOffset = 004
N0.C2.D0.R1.S08: Total Receive Enable Delay = 1245
N2.C3.D0.R1.S16: Preamble found at Latency = 008
N4.C2.D0.R1.S12: Preamble found at Latency = 007
N6.C2.D0.R1.S10: PI = 061, PtrOffset = 005
N0.C2.D0.R1: Starting preamble search upper nibbles
N2.C3.D0.R1.S09: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N4.C2.D0.R1.S13: Preamble found at Latency = 007
N6.C2.D0.R1.S11: PI = 029, PtrOffset = 005
N0.C2.D0.R1.S09: PI = 016, PtrOffset = 004
N2.C3.D0.R1.S10: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N4.C2.D0.R1.S14: Preamble found at Latency = 007
N6.C2.D0.R1.S12: PI = 011, PtrOffset = 005
N0.C2.D0.R1.S10: PI = 059, PtrOffset = 005
N2.C3.D0.R1.S11: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N4.C2.D0.R1.S15: Preamble found at Latency = 007
N6.C2.D0.R1.S13: PI = 010, PtrOffset = 005
N0.C2.D0.R1.S11: PI = 029, PtrOffset = 005
N2.C3.D0.R1.S12: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N4.C2.D0.R1.S17: Preamble found at Latency = 007
N6.C2.D0.R1.S14: PI = 021, PtrOffset = 005
N0.C2.D0.R1.S12: PI = 008, PtrOffset = 005
N2.C3.D0.R1.S13: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N4.C2.D0.R1: Preamble found for all upper nibbles, adjusting Pi, Offset to center into preamble
N6.C2.D0.R1.S15: PI = 063, PtrOffset = 005
N0.C2.D0.R1.S13: PI = 009, PtrOffset = 005
N2.C3.D0.R1.S14: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N4.C2.D0.R1.S09: Total Receive Enable Delay = 1323
N6.C2.D0.R1.S16: PI = 014, PtrOffset = 004
N0.C2.D0.R1.S14: PI = 020, PtrOffset = 005
N2.C3.D0.R1.S15: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N4.C2.D0.R1.S10: Total Receive Enable Delay = 1303
N6.C2.D0.R1.S17: PI = 063, PtrOffset = 004
N0.C2.D0.R1.S15: PI = 059, PtrOffset = 005
N2.C3.D0.R1.S16: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N4.C2.D0.R1.S11: Total Receive Enable Delay = 1271
N6.C2.D0.R1.S09: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N0.C2.D0.R1.S16: PI = 013, PtrOffset = 004
N2.C3.D0.R1.S17: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N4.C2.D0.R1.S12: Total Receive Enable Delay = 1251
N6.C2.D0.R1.S10: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N0.C2.D0.R1.S17: PI = 055, PtrOffset = 004
N2.C3.D0.R1.S12: Preamble found at Latency = 007
N4.C2.D0.R1.S13: Total Receive Enable Delay = 1250
N6.C2.D0.R1.S11: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N0.C2.D0.R1.S09: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N2.C3.D0.R1.S13: Preamble found at Latency = 007
N4.C2.D0.R1.S14: Total Receive Enable Delay = 1265
N6.C2.D0.R1.S12: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N0.C2.D0.R1.S10: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N2.C3.D0.R1.S17: Preamble found at Latency = 007
N4.C2.D0.R1.S15: Total Receive Enable Delay = 1302
N6.C2.D0.R1.S13: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N0.C2.D0.R1.S11: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N2.C3.D0.R1: Preamble found for all upper nibbles, adjusting Pi, Offset to center into preamble
N4.C2.D0.R1.S16: Total Receive Enable Delay = 1320
N6.C2.D0.R1.S14: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N0.C2.D0.R1.S12: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N2.C3.D0.R1.S09: Total Receive Enable Delay = 1375
N4.C2.D0.R1.S17: Total Receive Enable Delay = 1237
N6.C2.D0.R1.S15: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N0.C2.D0.R1.S13: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N2.C3.D0.R1.S10: Total Receive Enable Delay = 1353
N4.C2.D1.R0: RcvEnFine: Initial RdCmd2RcvEnLatency = 10, Initial RdPtrOffsetRcvEn = 4
N6.C2.D0.R1.S16: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N0.C2.D0.R1.S14: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N2.C3.D0.R1.S11: Total Receive Enable Delay = 1323
N4.C2.D1.R0.S00: Rcv En Fine Value = 382
N6.C2.D0.R1.S17: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N0.C2.D0.R1.S15: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N2.C3.D0.R1.S12: Total Receive Enable Delay = 1303
N4.C2.D1.R0.S01: Rcv En Fine Value = 358
N6.C2.D0.R1.S09: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N0.C2.D0.R1.S16: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N2.C3.D0.R1.S13: Total Receive Enable Delay = 1299
N4.C2.D1.R0.S02: Rcv En Fine Value = 332
N6.C2.D0.R1.S10: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N0.C2.D0.R1.S17: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N2.C3.D0.R1.S14: Total Receive Enable Delay = 1320
N4.C2.D1.R0.S03: Rcv En Fine Value = 307
N6.C2.D0.R1.S11: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N0.C2.D0.R1.S09: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N2.C3.D0.R1.S15: Total Receive Enable Delay = 1346
N4.C2.D1.R0.S04: Rcv En Fine Value = 307
N6.C2.D0.R1.S12: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N0.C2.D0.R1.S10: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N2.C3.D0.R1.S16: Total Receive Enable Delay = 1369
N4.C2.D1.R0.S05: Rcv En Fine Value = 322
N6.C2.D0.R1.S13: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N0.C2.D0.R1.S11: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N2.C3.D0.R1.S17: Total Receive Enable Delay = 1284
N4.C2.D1.R0.S06: Rcv En Fine Value = 358
N6.C2.D0.R1.S14: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N0.C2.D0.R1.S12: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N2.C3.D1.R0: RcvEnFine: Initial RdCmd2RcvEnLatency = 10, Initial RdPtrOffsetRcvEn = 4
N4.C2.D1.R0.S07: Rcv En Fine Value = 375
N6.C2.D0.R1.S15: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N0.C2.D0.R1.S13: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N2.C3.D1.R0.S00: Rcv En Fine Value = 303
N4.C2.D1.R0.S08: Rcv En Fine Value = 296
N6.C2.D0.R1.S16: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N0.C2.D0.R1.S14: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N2.C3.D1.R0.S01: Rcv En Fine Value = 282
N4.C2.D1.R0.S09: Rcv En Fine Value = 383
N6.C2.D0.R1.S17: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N0.C2.D0.R1.S15: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N2.C3.D1.R0.S02: Rcv En Fine Value = 381
N4.C2.D1.R0.S10: Rcv En Fine Value = 358
N6.C2.D0.R1.S09: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N0.C2.D0.R1.S16: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N2.C3.D1.R0.S03: Rcv En Fine Value = 359
N4.C2.D1.R0.S11: Rcv En Fine Value = 328
N6.C2.D0.R1.S10: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N0.C2.D0.R1.S17: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N2.C3.D1.R0.S04: Rcv En Fine Value = 353
N4.C2.D1.R0.S12: Rcv En Fine Value = 307
N6.C2.D0.R1.S11: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N0.C2.D0.R1.S09: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N2.C3.D1.R0.S05: Rcv En Fine Value = 378
N4.C2.D1.R0.S13: Rcv En Fine Value = 308
N6.C2.D0.R1.S12: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N0.C2.D0.R1.S10: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N2.C3.D1.R0.S06: Rcv En Fine Value = 275
N4.C2.D1.R0.S14: Rcv En Fine Value = 323
N6.C2.D0.R1.S13: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N0.C2.D0.R1.S11: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N2.C3.D1.R0.S07: Rcv En Fine Value = 298
N4.C2.D1.R0.S15: Rcv En Fine Value = 358
N6.C2.D0.R1.S14: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N0.C2.D0.R1.S12: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N2.C3.D1.R0.S08: Rcv En Fine Value = 343
N4.C2.D1.R0.S16: Rcv En Fine Value = 375
N6.C2.D0.R1.S15: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N0.C2.D0.R1.S13: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N2.C3.D1.R0.S09: Rcv En Fine Value = 304
N4.C2.D1.R0.S17: Rcv En Fine Value = 293
N6.C2.D0.R1.S16: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N0.C2.D0.R1.S14: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N2.C3.D1.R0.S10: Rcv En Fine Value = 282
N4.C2.D1.R0: Starting preamble search lower nibbles
N6.C2.D0.R1.S17: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N0.C2.D0.R1.S15: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N2.C3.D1.R0.S11: Rcv En Fine Value = 383
N4.C2.D1.R0.S00: PI = 062, PtrOffset = 005
N6.C2.D0.R1.S09: Preamble found at Latency = 008
N0.C2.D0.R1.S16: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N2.C3.D1.R0.S12: Rcv En Fine Value = 361
N4.C2.D1.R0.S01: PI = 038, PtrOffset = 005
N6.C2.D0.R1.S16: Preamble found at Latency = 008
N0.C2.D0.R1.S17: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N2.C3.D1.R0.S13: Rcv En Fine Value = 354
N4.C2.D1.R0.S02: PI = 012, PtrOffset = 005
N6.C2.D0.R1.S09: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N0.C2.D0.R1.S09: Preamble found at Latency = 008
N2.C3.D1.R0.S14: Rcv En Fine Value = 382
N4.C2.D1.R0.S03: PI = 051, PtrOffset = 004
N6.C2.D0.R1.S10: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N0.C2.D0.R1.S16: Preamble found at Latency = 008
N2.C3.D1.R0.S15: Rcv En Fine Value = 275
N4.C2.D1.R0.S04: PI = 051, PtrOffset = 004
N6.C2.D0.R1.S11: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N0.C2.D0.R1.S09: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N2.C3.D1.R0.S16: Rcv En Fine Value = 300
N4.C2.D1.R0.S05: PI = 002, PtrOffset = 005
N6.C2.D0.R1.S12: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N0.C2.D0.R1.S10: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N2.C3.D1.R0.S17: Rcv En Fine Value = 342
N4.C2.D1.R0.S06: PI = 038, PtrOffset = 005
N6.C2.D0.R1.S13: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N0.C2.D0.R1.S11: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N2.C3.D1.R0: Starting preamble search lower nibbles
N4.C2.D1.R0.S07: PI = 055, PtrOffset = 005
N6.C2.D0.R1.S14: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N0.C2.D0.R1.S12: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N2.C3.D1.R0.S00: PI = 047, PtrOffset = 004
N4.C2.D1.R0.S08: PI = 040, PtrOffset = 004
N6.C2.D0.R1.S15: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N0.C2.D0.R1.S13: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N2.C3.D1.R0.S01: PI = 026, PtrOffset = 004
N4.C2.D1.R0.S00: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N6.C2.D0.R1.S16: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N0.C2.D0.R1.S14: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N2.C3.D1.R0.S02: PI = 061, PtrOffset = 005
N4.C2.D1.R0.S01: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N6.C2.D0.R1.S17: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N0.C2.D0.R1.S15: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N2.C3.D1.R0.S03: PI = 039, PtrOffset = 005
N4.C2.D1.R0.S02: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N6.C2.D0.R1.S10: Preamble found at Latency = 007
N0.C2.D0.R1.S16: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N2.C3.D1.R0.S04: PI = 033, PtrOffset = 005
N4.C2.D1.R0.S03: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N6.C2.D0.R1.S11: Preamble found at Latency = 007
N0.C2.D0.R1.S17: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N2.C3.D1.R0.S05: PI = 058, PtrOffset = 005
N4.C2.D1.R0.S04: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N6.C2.D0.R1.S12: Preamble found at Latency = 007
N0.C2.D0.R1.S10: Preamble found at Latency = 007
N2.C3.D1.R0.S06: PI = 019, PtrOffset = 004
N4.C2.D1.R0.S05: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N6.C2.D0.R1.S13: Preamble found at Latency = 007
N0.C2.D0.R1.S11: Preamble found at Latency = 007
N2.C3.D1.R0.S07: PI = 042, PtrOffset = 004
N4.C2.D1.R0.S06: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N6.C2.D0.R1.S14: Preamble found at Latency = 007
N0.C2.D0.R1.S12: Preamble found at Latency = 007
N2.C3.D1.R0.S08: PI = 023, PtrOffset = 005
N4.C2.D1.R0.S07: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N6.C2.D0.R1.S15: Preamble found at Latency = 007
N0.C2.D0.R1.S13: Preamble found at Latency = 007
N2.C3.D1.R0.S00: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N4.C2.D1.R0.S08: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N6.C2.D0.R1.S17: Preamble found at Latency = 007
N0.C2.D0.R1.S14: Preamble found at Latency = 007
N2.C3.D1.R0.S01: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N4.C2.D1.R0.S00: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N6.C2.D0.R1: Preamble found for all upper nibbles, adjusting Pi, Offset to center into preamble
N0.C2.D0.R1.S15: Preamble found at Latency = 007
N2.C3.D1.R0.S02: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N4.C2.D1.R0.S01: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N6.C2.D0.R1.S09: Total Receive Enable Delay = 1329
N0.C2.D0.R1.S17: Preamble found at Latency = 007
N2.C3.D1.R0.S03: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N4.C2.D1.R0.S02: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N6.C2.D0.R1.S10: Total Receive Enable Delay = 1309
N0.C2.D0.R1: Preamble found for all upper nibbles, adjusting Pi, Offset to center into preamble
N2.C3.D1.R0.S04: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N4.C2.D1.R0.S03: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N6.C2.D0.R1.S11: Total Receive Enable Delay = 1277
N0.C2.D0.R1.S09: Total Receive Enable Delay = 1328
N2.C3.D1.R0.S05: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N4.C2.D1.R0.S04: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N6.C2.D0.R1.S12: Total Receive Enable Delay = 1259
N0.C2.D0.R1.S10: Total Receive Enable Delay = 1307
N2.C3.D1.R0.S06: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N4.C2.D1.R0.S05: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N6.C2.D0.R1.S13: Total Receive Enable Delay = 1258
N0.C2.D0.R1.S11: Total Receive Enable Delay = 1277
N2.C3.D1.R0.S07: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N4.C2.D1.R0.S06: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N6.C2.D0.R1.S14: Total Receive Enable Delay = 1269
N0.C2.D0.R1.S12: Total Receive Enable Delay = 1256
N2.C3.D1.R0.S08: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N4.C2.D1.R0.S07: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N6.C2.D0.R1.S15: Total Receive Enable Delay = 1311
N0.C2.D0.R1.S13: Total Receive Enable Delay = 1257
N2.C3.D1.R0.S00: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N4.C2.D1.R0.S08: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N6.C2.D0.R1.S16: Total Receive Enable Delay = 1326
N0.C2.D0.R1.S14: Total Receive Enable Delay = 1268
N2.C3.D1.R0.S01: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N4.C2.D1.R0.S00: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N6.C2.D0.R1.S17: Total Receive Enable Delay = 1247
N0.C2.D0.R1.S15: Total Receive Enable Delay = 1307
N2.C3.D1.R0.S02: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N4.C2.D1.R0.S01: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N6.C2.D1.R0: RcvEnFine: Initial RdCmd2RcvEnLatency = 10, Initial RdPtrOffsetRcvEn = 4
N0.C2.D0.R1.S16: Total Receive Enable Delay = 1325
N2.C3.D1.R0.S03: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N4.C2.D1.R0.S02: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N6.C2.D1.R0.S00: Rcv En Fine Value = 266
N0.C2.D0.R1.S17: Total Receive Enable Delay = 1239
N2.C3.D1.R0.S04: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N4.C2.D1.R0.S03: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N6.C2.D1.R0.S01: Rcv En Fine Value = 368
N0.C2.D1.R0: RcvEnFine: Initial RdCmd2RcvEnLatency = 10, Initial RdPtrOffsetRcvEn = 4
N2.C3.D1.R0.S05: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N4.C2.D1.R0.S04: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N6.C2.D1.R0.S02: Rcv En Fine Value = 341
N0.C2.D1.R0.S00: Rcv En Fine Value = 382
N2.C3.D1.R0.S06: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N4.C2.D1.R0.S05: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N6.C2.D1.R0.S03: Rcv En Fine Value = 323
N0.C2.D1.R0.S01: Rcv En Fine Value = 360
N2.C3.D1.R0.S07: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N4.C2.D1.R0.S06: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N6.C2.D1.R0.S04: Rcv En Fine Value = 321
N0.C2.D1.R0.S02: Rcv En Fine Value = 329
N2.C3.D1.R0.S08: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N4.C2.D1.R0.S07: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N6.C2.D1.R0.S05: Rcv En Fine Value = 334
N0.C2.D1.R0.S03: Rcv En Fine Value = 307
N2.C3.D1.R0.S00: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N4.C2.D1.R0.S08: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N6.C2.D1.R0.S06: Rcv En Fine Value = 370
N0.C2.D1.R0.S04: Rcv En Fine Value = 310
N2.C3.D1.R0.S01: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N4.C2.D1.R0.S00: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N6.C2.D1.R0.S07: Rcv En Fine Value = 260
N0.C2.D1.R0.S05: Rcv En Fine Value = 322
N2.C3.D1.R0.S02: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N4.C2.D1.R0.S01: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N6.C2.D1.R0.S08: Rcv En Fine Value = 308
N0.C2.D1.R0.S06: Rcv En Fine Value = 359
N2.C3.D1.R0.S03: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N4.C2.D1.R0.S02: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N6.C2.D1.R0.S09: Rcv En Fine Value = 265
N0.C2.D1.R0.S07: Rcv En Fine Value = 378
N2.C3.D1.R0.S04: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N4.C2.D1.R0.S03: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N6.C2.D1.R0.S10: Rcv En Fine Value = 369
N0.C2.D1.R0.S08: Rcv En Fine Value = 296
N2.C3.D1.R0.S05: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N4.C2.D1.R0.S04: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N6.C2.D1.R0.S11: Rcv En Fine Value = 340
N0.C2.D1.R0.S09: Rcv En Fine Value = 379
N2.C3.D1.R0.S06: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N4.C2.D1.R0.S05: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N6.C2.D1.R0.S12: Rcv En Fine Value = 321
N0.C2.D1.R0.S10: Rcv En Fine Value = 357
N2.C3.D1.R0.S07: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N4.C2.D1.R0.S06: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N6.C2.D1.R0.S13: Rcv En Fine Value = 321
N0.C2.D1.R0.S11: Rcv En Fine Value = 328
N2.C3.D1.R0.S08: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N4.C2.D1.R0.S07: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N6.C2.D1.R0.S14: Rcv En Fine Value = 330
N0.C2.D1.R0.S12: Rcv En Fine Value = 307
N2.C3.D1.R0.S00: Preamble found at Latency = 008
N4.C2.D1.R0.S08: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N6.C2.D1.R0.S15: Rcv En Fine Value = 371
N0.C2.D1.R0.S13: Rcv En Fine Value = 311
N2.C3.D1.R0.S01: Preamble found at Latency = 008
N4.C2.D1.R0.S00: Preamble found at Latency = 007
N6.C2.D1.R0.S16: Rcv En Fine Value = 261
N0.C2.D1.R0.S14: Rcv En Fine Value = 323
N2.C3.D1.R0.S06: Preamble found at Latency = 008
N4.C2.D1.R0.S01: Preamble found at Latency = 007
N6.C2.D1.R0.S17: Rcv En Fine Value = 309
N0.C2.D1.R0.S15: Rcv En Fine Value = 359
N2.C3.D1.R0.S07: Preamble found at Latency = 008
N4.C2.D1.R0.S02: Preamble found at Latency = 007
N6.C2.D1.R0: Starting preamble search lower nibbles
N0.C2.D1.R0.S16: Rcv En Fine Value = 376
N2.C3.D1.R0.S00: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N4.C2.D1.R0.S03: Preamble found at Latency = 007
N6.C2.D1.R0.S00: PI = 010, PtrOffset = 004
N0.C2.D1.R0.S17: Rcv En Fine Value = 295
N2.C3.D1.R0.S01: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N4.C2.D1.R0.S04: Preamble found at Latency = 007
N6.C2.D1.R0.S01: PI = 048, PtrOffset = 005
N0.C2.D1.R0: Starting preamble search lower nibbles
N2.C3.D1.R0.S02: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N4.C2.D1.R0.S05: Preamble found at Latency = 007
N6.C2.D1.R0.S02: PI = 021, PtrOffset = 005
N0.C2.D1.R0.S00: PI = 062, PtrOffset = 005
N2.C3.D1.R0.S03: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N4.C2.D1.R0.S06: Preamble found at Latency = 007
N6.C2.D1.R0.S03: PI = 003, PtrOffset = 005
N0.C2.D1.R0.S01: PI = 040, PtrOffset = 005
N2.C3.D1.R0.S04: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N4.C2.D1.R0.S07: Preamble found at Latency = 007
N6.C2.D1.R0.S04: PI = 001, PtrOffset = 005
N0.C2.D1.R0.S02: PI = 009, PtrOffset = 005
N2.C3.D1.R0.S05: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N4.C2.D1.R0.S08: Preamble found at Latency = 007
N6.C2.D1.R0.S05: PI = 014, PtrOffset = 005
N0.C2.D1.R0.S03: PI = 051, PtrOffset = 004
N2.C3.D1.R0.S06: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N4.C2.D1.R0.S00: Total Receive Enable Delay = 1310
N6.C2.D1.R0.S06: PI = 050, PtrOffset = 005
N0.C2.D1.R0.S04: PI = 054, PtrOffset = 004
N2.C3.D1.R0.S07: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N4.C2.D1.R0.S01: Total Receive Enable Delay = 1286
N6.C2.D1.R0.S07: PI = 004, PtrOffset = 004
N0.C2.D1.R0.S05: PI = 002, PtrOffset = 005
N2.C3.D1.R0.S08: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N4.C2.D1.R0.S02: Total Receive Enable Delay = 1260
N6.C2.D1.R0.S08: PI = 052, PtrOffset = 004
N0.C2.D1.R0.S06: PI = 039, PtrOffset = 005
N2.C3.D1.R0.S02: Preamble found at Latency = 007
N4.C2.D1.R0.S03: Total Receive Enable Delay = 1235
N6.C2.D1.R0.S00: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N0.C2.D1.R0.S07: PI = 058, PtrOffset = 005
N2.C3.D1.R0.S03: Preamble found at Latency = 007
N4.C2.D1.R0.S04: Total Receive Enable Delay = 1235
N6.C2.D1.R0.S01: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N0.C2.D1.R0.S08: PI = 040, PtrOffset = 004
N2.C3.D1.R0.S04: Preamble found at Latency = 007
N4.C2.D1.R0.S05: Total Receive Enable Delay = 1250
N6.C2.D1.R0.S02: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N0.C2.D1.R0.S00: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N2.C3.D1.R0.S05: Preamble found at Latency = 007
N4.C2.D1.R0.S06: Total Receive Enable Delay = 1286
N6.C2.D1.R0.S03: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N0.C2.D1.R0.S01: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N2.C3.D1.R0.S08: Preamble found at Latency = 007
N4.C2.D1.R0.S07: Total Receive Enable Delay = 1303
N6.C2.D1.R0.S04: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N0.C2.D1.R0.S02: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N2.C3.D1.R0.S00: Total Receive Enable Delay = 1359
N4.C2.D1.R0.S08: Total Receive Enable Delay = 1224
N6.C2.D1.R0.S05: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N0.C2.D1.R0.S03: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N2.C3.D1.R0.S01: Total Receive Enable Delay = 1338
N4.C2.D1.R0: Starting preamble search upper nibbles
N6.C2.D1.R0.S06: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N0.C2.D1.R0.S04: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N2.C3.D1.R0.S02: Total Receive Enable Delay = 1309
N4.C2.D1.R0.S09: PI = 063, PtrOffset = 005
N6.C2.D1.R0.S07: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N0.C2.D1.R0.S05: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N2.C3.D1.R0.S03: Total Receive Enable Delay = 1287
N4.C2.D1.R0.S10: PI = 038, PtrOffset = 005
N6.C2.D1.R0.S08: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N0.C2.D1.R0.S06: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N2.C3.D1.R0.S04: Total Receive Enable Delay = 1281
N4.C2.D1.R0.S11: PI = 008, PtrOffset = 005
N6.C2.D1.R0.S00: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N0.C2.D1.R0.S07: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N2.C3.D1.R0.S05: Total Receive Enable Delay = 1306
N4.C2.D1.R0.S12: PI = 051, PtrOffset = 004
N6.C2.D1.R0.S01: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N0.C2.D1.R0.S08: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N2.C3.D1.R0.S06: Total Receive Enable Delay = 1331
N4.C2.D1.R0.S13: PI = 052, PtrOffset = 004
N6.C2.D1.R0.S02: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N0.C2.D1.R0.S00: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N2.C3.D1.R0.S07: Total Receive Enable Delay = 1354
N4.C2.D1.R0.S14: PI = 003, PtrOffset = 005
N6.C2.D1.R0.S03: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N0.C2.D1.R0.S01: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N2.C3.D1.R0.S08: Total Receive Enable Delay = 1271
N4.C2.D1.R0.S15: PI = 038, PtrOffset = 005
N6.C2.D1.R0.S04: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N0.C2.D1.R0.S02: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N2.C3.D1.R0: Starting preamble search upper nibbles
N4.C2.D1.R0.S16: PI = 055, PtrOffset = 005
N6.C2.D1.R0.S05: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N0.C2.D1.R0.S03: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N2.C3.D1.R0.S09: PI = 048, PtrOffset = 004
N4.C2.D1.R0.S17: PI = 037, PtrOffset = 004
N6.C2.D1.R0.S06: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N0.C2.D1.R0.S04: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N2.C3.D1.R0.S10: PI = 026, PtrOffset = 004
N4.C2.D1.R0.S09: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N6.C2.D1.R0.S07: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N0.C2.D1.R0.S05: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N2.C3.D1.R0.S11: PI = 063, PtrOffset = 005
N4.C2.D1.R0.S10: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N6.C2.D1.R0.S08: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N0.C2.D1.R0.S06: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N2.C3.D1.R0.S12: PI = 041, PtrOffset = 005
N4.C2.D1.R0.S11: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N6.C2.D1.R0.S00: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N0.C2.D1.R0.S07: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N2.C3.D1.R0.S13: PI = 034, PtrOffset = 005
N4.C2.D1.R0.S12: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N6.C2.D1.R0.S01: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N0.C2.D1.R0.S08: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N2.C3.D1.R0.S14: PI = 062, PtrOffset = 005
N4.C2.D1.R0.S13: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N6.C2.D1.R0.S02: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N0.C2.D1.R0.S00: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N2.C3.D1.R0.S15: PI = 019, PtrOffset = 004
N4.C2.D1.R0.S14: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N6.C2.D1.R0.S03: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N0.C2.D1.R0.S01: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N2.C3.D1.R0.S16: PI = 044, PtrOffset = 004
N4.C2.D1.R0.S15: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N6.C2.D1.R0.S04: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N0.C2.D1.R0.S02: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N2.C3.D1.R0.S17: PI = 022, PtrOffset = 005
N4.C2.D1.R0.S16: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N6.C2.D1.R0.S05: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N0.C2.D1.R0.S03: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N2.C3.D1.R0.S09: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N4.C2.D1.R0.S17: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N6.C2.D1.R0.S06: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N0.C2.D1.R0.S04: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N2.C3.D1.R0.S10: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N4.C2.D1.R0.S09: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N6.C2.D1.R0.S07: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N0.C2.D1.R0.S05: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N2.C3.D1.R0.S11: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N4.C2.D1.R0.S10: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N6.C2.D1.R0.S08: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N0.C2.D1.R0.S06: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N2.C3.D1.R0.S12: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N4.C2.D1.R0.S11: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N6.C2.D1.R0.S00: Preamble found at Latency = 008
N0.C2.D1.R0.S07: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N2.C3.D1.R0.S13: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N4.C2.D1.R0.S12: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N6.C2.D1.R0.S07: Preamble found at Latency = 008
N0.C2.D1.R0.S08: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N2.C3.D1.R0.S14: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N4.C2.D1.R0.S13: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N6.C2.D1.R0.S00: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N0.C2.D1.R0.S00: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N2.C3.D1.R0.S15: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N4.C2.D1.R0.S14: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N6.C2.D1.R0.S01: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N0.C2.D1.R0.S01: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N2.C3.D1.R0.S16: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N4.C2.D1.R0.S15: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N6.C2.D1.R0.S02: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N0.C2.D1.R0.S02: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N2.C3.D1.R0.S17: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N4.C2.D1.R0.S16: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N6.C2.D1.R0.S03: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N0.C2.D1.R0.S03: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N2.C3.D1.R0.S09: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N4.C2.D1.R0.S17: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N6.C2.D1.R0.S04: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N0.C2.D1.R0.S04: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N2.C3.D1.R0.S10: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N4.C2.D1.R0.S09: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N6.C2.D1.R0.S05: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N0.C2.D1.R0.S05: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N2.C3.D1.R0.S11: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N4.C2.D1.R0.S10: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N6.C2.D1.R0.S06: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N0.C2.D1.R0.S06: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N2.C3.D1.R0.S12: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N4.C2.D1.R0.S11: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N6.C2.D1.R0.S07: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N0.C2.D1.R0.S07: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N2.C3.D1.R0.S13: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N4.C2.D1.R0.S12: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N6.C2.D1.R0.S08: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N0.C2.D1.R0.S08: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N2.C3.D1.R0.S14: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N4.C2.D1.R0.S13: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N6.C2.D1.R0.S01: Preamble found at Latency = 007
N0.C2.D1.R0.S00: Preamble found at Latency = 007
N2.C3.D1.R0.S15: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N4.C2.D1.R0.S14: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N6.C2.D1.R0.S02: Preamble found at Latency = 007
N0.C2.D1.R0.S01: Preamble found at Latency = 007
N2.C3.D1.R0.S16: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N4.C2.D1.R0.S15: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N6.C2.D1.R0.S03: Preamble found at Latency = 007
N0.C2.D1.R0.S02: Preamble found at Latency = 007
N2.C3.D1.R0.S17: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N4.C2.D1.R0.S16: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N6.C2.D1.R0.S04: Preamble found at Latency = 007
N0.C2.D1.R0.S03: Preamble found at Latency = 007
N2.C3.D1.R0.S09: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N4.C2.D1.R0.S17: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N6.C2.D1.R0.S05: Preamble found at Latency = 007
N0.C2.D1.R0.S04: Preamble found at Latency = 007
N2.C3.D1.R0.S10: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N4.C2.D1.R0.S09: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N6.C2.D1.R0.S06: Preamble found at Latency = 007
N0.C2.D1.R0.S05: Preamble found at Latency = 007
N2.C3.D1.R0.S11: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N4.C2.D1.R0.S10: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N6.C2.D1.R0.S08: Preamble found at Latency = 007
N0.C2.D1.R0.S06: Preamble found at Latency = 007
N2.C3.D1.R0.S12: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N4.C2.D1.R0.S11: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N6.C2.D1.R0.S00: Total Receive Enable Delay = 1322
N0.C2.D1.R0.S07: Preamble found at Latency = 007
N2.C3.D1.R0.S13: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N4.C2.D1.R0.S12: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N6.C2.D1.R0.S01: Total Receive Enable Delay = 1296
N0.C2.D1.R0.S08: Preamble found at Latency = 007
N2.C3.D1.R0.S14: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N4.C2.D1.R0.S13: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N6.C2.D1.R0.S02: Total Receive Enable Delay = 1269
N0.C2.D1.R0.S00: Total Receive Enable Delay = 1310
N2.C3.D1.R0.S15: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N4.C2.D1.R0.S14: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N6.C2.D1.R0.S03: Total Receive Enable Delay = 1251
N0.C2.D1.R0.S01: Total Receive Enable Delay = 1288
N2.C3.D1.R0.S16: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N4.C2.D1.R0.S15: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N6.C2.D1.R0.S04: Total Receive Enable Delay = 1249
N0.C2.D1.R0.S02: Total Receive Enable Delay = 1257
N2.C3.D1.R0.S17: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N4.C2.D1.R0.S16: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N6.C2.D1.R0.S05: Total Receive Enable Delay = 1262
N0.C2.D1.R0.S03: Total Receive Enable Delay = 1235
N2.C3.D1.R0.S09: Preamble found at Latency = 008
N4.C2.D1.R0.S17: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N6.C2.D1.R0.S06: Total Receive Enable Delay = 1298
N0.C2.D1.R0.S04: Total Receive Enable Delay = 1238
N2.C3.D1.R0.S10: Preamble found at Latency = 008
N4.C2.D1.R0.S09: Preamble found at Latency = 007
N6.C2.D1.R0.S07: Total Receive Enable Delay = 1316
N0.C2.D1.R0.S05: Total Receive Enable Delay = 1250
N2.C3.D1.R0.S15: Preamble found at Latency = 008
N4.C2.D1.R0.S10: Preamble found at Latency = 007
N6.C2.D1.R0.S08: Total Receive Enable Delay = 1236
N0.C2.D1.R0.S06: Total Receive Enable Delay = 1287
N2.C3.D1.R0.S16: Preamble found at Latency = 008
N4.C2.D1.R0.S11: Preamble found at Latency = 007
N6.C2.D1.R0: Starting preamble search upper nibbles
N0.C2.D1.R0.S07: Total Receive Enable Delay = 1306
N2.C3.D1.R0.S09: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N4.C2.D1.R0.S12: Preamble found at Latency = 007
N6.C2.D1.R0.S09: PI = 009, PtrOffset = 004
N0.C2.D1.R0.S08: Total Receive Enable Delay = 1224
N2.C3.D1.R0.S10: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N4.C2.D1.R0.S13: Preamble found at Latency = 007
N6.C2.D1.R0.S10: PI = 049, PtrOffset = 005
N0.C2.D1.R0: Starting preamble search upper nibbles
N2.C3.D1.R0.S11: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N4.C2.D1.R0.S14: Preamble found at Latency = 007
N6.C2.D1.R0.S11: PI = 020, PtrOffset = 005
N0.C2.D1.R0.S09: PI = 059, PtrOffset = 005
N2.C3.D1.R0.S12: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N4.C2.D1.R0.S15: Preamble found at Latency = 007
N6.C2.D1.R0.S12: PI = 001, PtrOffset = 005
N0.C2.D1.R0.S10: PI = 037, PtrOffset = 005
N2.C3.D1.R0.S13: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N4.C2.D1.R0.S16: Preamble found at Latency = 007
N6.C2.D1.R0.S13: PI = 001, PtrOffset = 005
N0.C2.D1.R0.S11: PI = 008, PtrOffset = 005
N2.C3.D1.R0.S14: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N4.C2.D1.R0.S17: Preamble found at Latency = 007
N6.C2.D1.R0.S14: PI = 010, PtrOffset = 005
N0.C2.D1.R0.S12: PI = 051, PtrOffset = 004
N2.C3.D1.R0.S15: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N4.C2.D1.R0: Preamble found for all upper nibbles, adjusting Pi, Offset to center into preamble
N6.C2.D1.R0.S15: PI = 051, PtrOffset = 005
N0.C2.D1.R0.S13: PI = 055, PtrOffset = 004
N2.C3.D1.R0.S16: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N4.C2.D1.R0.S09: Total Receive Enable Delay = 1311
N6.C2.D1.R0.S16: PI = 005, PtrOffset = 004
N0.C2.D1.R0.S14: PI = 003, PtrOffset = 005
N2.C3.D1.R0.S17: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N4.C2.D1.R0.S10: Total Receive Enable Delay = 1286
N6.C2.D1.R0.S17: PI = 053, PtrOffset = 004
N0.C2.D1.R0.S15: PI = 039, PtrOffset = 005
N2.C3.D1.R0.S11: Preamble found at Latency = 007
N4.C2.D1.R0.S11: Total Receive Enable Delay = 1256
N6.C2.D1.R0.S09: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N0.C2.D1.R0.S16: PI = 056, PtrOffset = 005
N2.C3.D1.R0.S12: Preamble found at Latency = 007
N4.C2.D1.R0.S12: Total Receive Enable Delay = 1235
N6.C2.D1.R0.S10: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N0.C2.D1.R0.S17: PI = 039, PtrOffset = 004
N2.C3.D1.R0.S13: Preamble found at Latency = 007
N4.C2.D1.R0.S13: Total Receive Enable Delay = 1236
N6.C2.D1.R0.S11: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N0.C2.D1.R0.S09: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N2.C3.D1.R0.S14: Preamble found at Latency = 007
N4.C2.D1.R0.S14: Total Receive Enable Delay = 1251
N6.C2.D1.R0.S12: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N0.C2.D1.R0.S10: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N2.C3.D1.R0.S17: Preamble found at Latency = 007
N4.C2.D1.R0.S15: Total Receive Enable Delay = 1286
N6.C2.D1.R0.S13: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N0.C2.D1.R0.S11: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N2.C3.D1.R0: Preamble found for all upper nibbles, adjusting Pi, Offset to center into preamble
N4.C2.D1.R0.S16: Total Receive Enable Delay = 1303
N6.C2.D1.R0.S14: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N0.C2.D1.R0.S12: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N2.C3.D1.R0.S09: Total Receive Enable Delay = 1360
N4.C2.D1.R0.S17: Total Receive Enable Delay = 1221
N6.C2.D1.R0.S15: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N0.C2.D1.R0.S13: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N2.C3.D1.R0.S10: Total Receive Enable Delay = 1338
N4.C2.D1.R1: RcvEnFine: Initial RdCmd2RcvEnLatency = 10, Initial RdPtrOffsetRcvEn = 4
N6.C2.D1.R0.S16: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N0.C2.D1.R0.S14: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N2.C3.D1.R0.S11: Total Receive Enable Delay = 1311
N4.C2.D1.R1.S00: Rcv En Fine Value = 381
N6.C2.D1.R0.S17: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N0.C2.D1.R0.S15: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N2.C3.D1.R0.S12: Total Receive Enable Delay = 1289
N4.C2.D1.R1.S01: Rcv En Fine Value = 359
N6.C2.D1.R0.S09: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N0.C2.D1.R0.S16: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N2.C3.D1.R0.S13: Total Receive Enable Delay = 1282
N4.C2.D1.R1.S02: Rcv En Fine Value = 329
N6.C2.D1.R0.S10: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N0.C2.D1.R0.S17: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N2.C3.D1.R0.S14: Total Receive Enable Delay = 1310
N4.C2.D1.R1.S03: Rcv En Fine Value = 302
N6.C2.D1.R0.S11: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N0.C2.D1.R0.S09: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N2.C3.D1.R0.S15: Total Receive Enable Delay = 1331
N4.C2.D1.R1.S04: Rcv En Fine Value = 309
N6.C2.D1.R0.S12: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N0.C2.D1.R0.S10: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N2.C3.D1.R0.S16: Total Receive Enable Delay = 1356
N4.C2.D1.R1.S05: Rcv En Fine Value = 319
N6.C2.D1.R0.S13: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N0.C2.D1.R0.S11: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N2.C3.D1.R0.S17: Total Receive Enable Delay = 1270
N4.C2.D1.R1.S06: Rcv En Fine Value = 358
N6.C2.D1.R0.S14: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N0.C2.D1.R0.S12: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N2.C3.D1.R1: RcvEnFine: Initial RdCmd2RcvEnLatency = 10, Initial RdPtrOffsetRcvEn = 4
N4.C2.D1.R1.S07: Rcv En Fine Value = 374
N6.C2.D1.R0.S15: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N0.C2.D1.R0.S13: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N2.C3.D1.R1.S00: Rcv En Fine Value = 302
N4.C2.D1.R1.S08: Rcv En Fine Value = 295
N6.C2.D1.R0.S16: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N0.C2.D1.R0.S14: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N2.C3.D1.R1.S01: Rcv En Fine Value = 281
N4.C2.D1.R1.S09: Rcv En Fine Value = 380
N6.C2.D1.R0.S17: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N0.C2.D1.R0.S15: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N2.C3.D1.R1.S02: Rcv En Fine Value = 380
N4.C2.D1.R1.S10: Rcv En Fine Value = 357
N6.C2.D1.R0.S09: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N0.C2.D1.R0.S16: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N2.C3.D1.R1.S03: Rcv En Fine Value = 359
N4.C2.D1.R1.S11: Rcv En Fine Value = 326
N6.C2.D1.R0.S10: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N0.C2.D1.R0.S17: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N2.C3.D1.R1.S04: Rcv En Fine Value = 354
N4.C2.D1.R1.S12: Rcv En Fine Value = 304
N6.C2.D1.R0.S11: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N0.C2.D1.R0.S09: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N2.C3.D1.R1.S05: Rcv En Fine Value = 379
N4.C2.D1.R1.S13: Rcv En Fine Value = 307
N6.C2.D1.R0.S12: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N0.C2.D1.R0.S10: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N2.C3.D1.R1.S06: Rcv En Fine Value = 277
N4.C2.D1.R1.S14: Rcv En Fine Value = 322
N6.C2.D1.R0.S13: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N0.C2.D1.R0.S11: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N2.C3.D1.R1.S07: Rcv En Fine Value = 298
N4.C2.D1.R1.S15: Rcv En Fine Value = 357
N6.C2.D1.R0.S14: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N0.C2.D1.R0.S12: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N2.C3.D1.R1.S08: Rcv En Fine Value = 341
N4.C2.D1.R1.S16: Rcv En Fine Value = 372
N6.C2.D1.R0.S15: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N0.C2.D1.R0.S13: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N2.C3.D1.R1.S09: Rcv En Fine Value = 303
N4.C2.D1.R1.S17: Rcv En Fine Value = 291
N6.C2.D1.R0.S16: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N0.C2.D1.R0.S14: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N2.C3.D1.R1.S10: Rcv En Fine Value = 281
N4.C2.D1.R1: Starting preamble search lower nibbles
N6.C2.D1.R0.S17: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N0.C2.D1.R0.S15: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N2.C3.D1.R1.S11: Rcv En Fine Value = 381
N4.C2.D1.R1.S00: PI = 061, PtrOffset = 005
N6.C2.D1.R0.S09: Preamble found at Latency = 008
N0.C2.D1.R0.S16: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N2.C3.D1.R1.S12: Rcv En Fine Value = 363
N4.C2.D1.R1.S01: PI = 039, PtrOffset = 005
N6.C2.D1.R0.S16: Preamble found at Latency = 008
N0.C2.D1.R0.S17: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N2.C3.D1.R1.S13: Rcv En Fine Value = 355
N4.C2.D1.R1.S02: PI = 009, PtrOffset = 005
N6.C2.D1.R0.S09: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N0.C2.D1.R0.S09: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N2.C3.D1.R1.S14: Rcv En Fine Value = 377
N4.C2.D1.R1.S03: PI = 046, PtrOffset = 004
N6.C2.D1.R0.S10: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N0.C2.D1.R0.S10: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N2.C3.D1.R1.S15: Rcv En Fine Value = 278
N4.C2.D1.R1.S04: PI = 053, PtrOffset = 004
N6.C2.D1.R0.S11: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N0.C2.D1.R0.S11: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N2.C3.D1.R1.S16: Rcv En Fine Value = 298
N4.C2.D1.R1.S05: PI = 063, PtrOffset = 004
N6.C2.D1.R0.S12: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N0.C2.D1.R0.S12: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N2.C3.D1.R1.S17: Rcv En Fine Value = 341
N4.C2.D1.R1.S06: PI = 038, PtrOffset = 005
N6.C2.D1.R0.S13: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N0.C2.D1.R0.S13: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N2.C3.D1.R1: Starting preamble search lower nibbles
N4.C2.D1.R1.S07: PI = 054, PtrOffset = 005
N6.C2.D1.R0.S14: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N0.C2.D1.R0.S14: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N2.C3.D1.R1.S00: PI = 046, PtrOffset = 004
N4.C2.D1.R1.S08: PI = 039, PtrOffset = 004
N6.C2.D1.R0.S15: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N0.C2.D1.R0.S15: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N2.C3.D1.R1.S01: PI = 025, PtrOffset = 004
N4.C2.D1.R1.S00: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N6.C2.D1.R0.S16: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N0.C2.D1.R0.S16: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N2.C3.D1.R1.S02: PI = 060, PtrOffset = 005
N4.C2.D1.R1.S01: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N6.C2.D1.R0.S17: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N0.C2.D1.R0.S17: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N2.C3.D1.R1.S03: PI = 039, PtrOffset = 005
N4.C2.D1.R1.S02: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N6.C2.D1.R0.S10: Preamble found at Latency = 007
N0.C2.D1.R0.S09: Preamble found at Latency = 007
N2.C3.D1.R1.S04: PI = 034, PtrOffset = 005
N4.C2.D1.R1.S03: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N6.C2.D1.R0.S11: Preamble found at Latency = 007
N0.C2.D1.R0.S10: Preamble found at Latency = 007
N2.C3.D1.R1.S05: PI = 059, PtrOffset = 005
N4.C2.D1.R1.S04: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N6.C2.D1.R0.S12: Preamble found at Latency = 007
N0.C2.D1.R0.S11: Preamble found at Latency = 007
N2.C3.D1.R1.S06: PI = 021, PtrOffset = 004
N4.C2.D1.R1.S05: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N6.C2.D1.R0.S13: Preamble found at Latency = 007
N0.C2.D1.R0.S12: Preamble found at Latency = 007
N2.C3.D1.R1.S07: PI = 042, PtrOffset = 004
N4.C2.D1.R1.S06: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N6.C2.D1.R0.S14: Preamble found at Latency = 007
N0.C2.D1.R0.S13: Preamble found at Latency = 007
N2.C3.D1.R1.S08: PI = 021, PtrOffset = 005
N4.C2.D1.R1.S07: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N6.C2.D1.R0.S15: Preamble found at Latency = 007
N0.C2.D1.R0.S14: Preamble found at Latency = 007
N2.C3.D1.R1.S00: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N4.C2.D1.R1.S08: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N6.C2.D1.R0.S17: Preamble found at Latency = 007
N0.C2.D1.R0.S15: Preamble found at Latency = 007
N2.C3.D1.R1.S01: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N4.C2.D1.R1.S00: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N6.C2.D1.R0: Preamble found for all upper nibbles, adjusting Pi, Offset to center into preamble
N0.C2.D1.R0.S16: Preamble found at Latency = 007
N2.C3.D1.R1.S02: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N4.C2.D1.R1.S01: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N6.C2.D1.R0.S09: Total Receive Enable Delay = 1321
N0.C2.D1.R0.S17: Preamble found at Latency = 007
N2.C3.D1.R1.S03: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N4.C2.D1.R1.S02: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N6.C2.D1.R0.S10: Total Receive Enable Delay = 1297
N0.C2.D1.R0: Preamble found for all upper nibbles, adjusting Pi, Offset to center into preamble
N2.C3.D1.R1.S04: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N4.C2.D1.R1.S03: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N6.C2.D1.R0.S11: Total Receive Enable Delay = 1268
N0.C2.D1.R0.S09: Total Receive Enable Delay = 1307
N2.C3.D1.R1.S05: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N4.C2.D1.R1.S04: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N6.C2.D1.R0.S12: Total Receive Enable Delay = 1249
N0.C2.D1.R0.S10: Total Receive Enable Delay = 1285
N2.C3.D1.R1.S06: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N4.C2.D1.R1.S05: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N6.C2.D1.R0.S13: Total Receive Enable Delay = 1249
N0.C2.D1.R0.S11: Total Receive Enable Delay = 1256
N2.C3.D1.R1.S07: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N4.C2.D1.R1.S06: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N6.C2.D1.R0.S14: Total Receive Enable Delay = 1258
N0.C2.D1.R0.S12: Total Receive Enable Delay = 1235
N2.C3.D1.R1.S08: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N4.C2.D1.R1.S07: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N6.C2.D1.R0.S15: Total Receive Enable Delay = 1299
N0.C2.D1.R0.S13: Total Receive Enable Delay = 1239
N2.C3.D1.R1.S00: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N4.C2.D1.R1.S08: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N6.C2.D1.R0.S16: Total Receive Enable Delay = 1317
N0.C2.D1.R0.S14: Total Receive Enable Delay = 1251
N2.C3.D1.R1.S01: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N4.C2.D1.R1.S00: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N6.C2.D1.R0.S17: Total Receive Enable Delay = 1237
N0.C2.D1.R0.S15: Total Receive Enable Delay = 1287
N2.C3.D1.R1.S02: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N4.C2.D1.R1.S01: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N6.C2.D1.R1: RcvEnFine: Initial RdCmd2RcvEnLatency = 10, Initial RdPtrOffsetRcvEn = 4
N0.C2.D1.R0.S16: Total Receive Enable Delay = 1304
N2.C3.D1.R1.S03: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N4.C2.D1.R1.S02: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N6.C2.D1.R1.S00: Rcv En Fine Value = 266
N0.C2.D1.R0.S17: Total Receive Enable Delay = 1223
N2.C3.D1.R1.S04: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N4.C2.D1.R1.S03: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N6.C2.D1.R1.S01: Rcv En Fine Value = 368
N0.C2.D1.R1: RcvEnFine: Initial RdCmd2RcvEnLatency = 10, Initial RdPtrOffsetRcvEn = 4
N2.C3.D1.R1.S05: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N4.C2.D1.R1.S04: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N6.C2.D1.R1.S02: Rcv En Fine Value = 341
N0.C2.D1.R1.S00: Rcv En Fine Value = 382
N2.C3.D1.R1.S06: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N4.C2.D1.R1.S05: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N6.C2.D1.R1.S03: Rcv En Fine Value = 321
N0.C2.D1.R1.S01: Rcv En Fine Value = 359
N2.C3.D1.R1.S07: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N4.C2.D1.R1.S06: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N6.C2.D1.R1.S04: Rcv En Fine Value = 321
N0.C2.D1.R1.S02: Rcv En Fine Value = 327
N2.C3.D1.R1.S08: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N4.C2.D1.R1.S07: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N6.C2.D1.R1.S05: Rcv En Fine Value = 333
N0.C2.D1.R1.S03: Rcv En Fine Value = 307
N2.C3.D1.R1.S00: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N4.C2.D1.R1.S08: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N6.C2.D1.R1.S06: Rcv En Fine Value = 373
N0.C2.D1.R1.S04: Rcv En Fine Value = 309
N2.C3.D1.R1.S01: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N4.C2.D1.R1.S00: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N6.C2.D1.R1.S07: Rcv En Fine Value = 260
N0.C2.D1.R1.S05: Rcv En Fine Value = 321
N2.C3.D1.R1.S02: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N4.C2.D1.R1.S01: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N6.C2.D1.R1.S08: Rcv En Fine Value = 306
N0.C2.D1.R1.S06: Rcv En Fine Value = 360
N2.C3.D1.R1.S03: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N4.C2.D1.R1.S02: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N6.C2.D1.R1.S09: Rcv En Fine Value = 263
N0.C2.D1.R1.S07: Rcv En Fine Value = 376
N2.C3.D1.R1.S04: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N4.C2.D1.R1.S03: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N6.C2.D1.R1.S10: Rcv En Fine Value = 373
N0.C2.D1.R1.S08: Rcv En Fine Value = 298
N2.C3.D1.R1.S05: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N4.C2.D1.R1.S04: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N6.C2.D1.R1.S11: Rcv En Fine Value = 338
N0.C2.D1.R1.S09: Rcv En Fine Value = 383
N2.C3.D1.R1.S06: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N4.C2.D1.R1.S05: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N6.C2.D1.R1.S12: Rcv En Fine Value = 322
N0.C2.D1.R1.S10: Rcv En Fine Value = 358
N2.C3.D1.R1.S07: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N4.C2.D1.R1.S06: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N6.C2.D1.R1.S13: Rcv En Fine Value = 320
N0.C2.D1.R1.S11: Rcv En Fine Value = 327
N2.C3.D1.R1.S08: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N4.C2.D1.R1.S07: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N6.C2.D1.R1.S14: Rcv En Fine Value = 331
N0.C2.D1.R1.S12: Rcv En Fine Value = 306
N2.C3.D1.R1.S00: Preamble found at Latency = 008
N4.C2.D1.R1.S08: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N6.C2.D1.R1.S15: Rcv En Fine Value = 371
N0.C2.D1.R1.S13: Rcv En Fine Value = 310
N2.C3.D1.R1.S01: Preamble found at Latency = 008
N4.C2.D1.R1.S00: Preamble found at Latency = 007
N6.C2.D1.R1.S16: Rcv En Fine Value = 261
N0.C2.D1.R1.S14: Rcv En Fine Value = 321
N2.C3.D1.R1.S06: Preamble found at Latency = 008
N4.C2.D1.R1.S01: Preamble found at Latency = 007
N6.C2.D1.R1.S17: Rcv En Fine Value = 308
N0.C2.D1.R1.S15: Rcv En Fine Value = 360
N2.C3.D1.R1.S07: Preamble found at Latency = 008
N4.C2.D1.R1.S02: Preamble found at Latency = 007
N6.C2.D1.R1: Starting preamble search lower nibbles
N0.C2.D1.R1.S16: Rcv En Fine Value = 378
N2.C3.D1.R1.S00: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N4.C2.D1.R1.S03: Preamble found at Latency = 007
N6.C2.D1.R1.S00: PI = 010, PtrOffset = 004
N0.C2.D1.R1.S17: Rcv En Fine Value = 293
N2.C3.D1.R1.S01: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N4.C2.D1.R1.S04: Preamble found at Latency = 007
N6.C2.D1.R1.S01: PI = 048, PtrOffset = 005
N0.C2.D1.R1: Starting preamble search lower nibbles
N2.C3.D1.R1.S02: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N4.C2.D1.R1.S05: Preamble found at Latency = 007
N6.C2.D1.R1.S02: PI = 021, PtrOffset = 005
N0.C2.D1.R1.S00: PI = 062, PtrOffset = 005
N2.C3.D1.R1.S03: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N4.C2.D1.R1.S06: Preamble found at Latency = 007
N6.C2.D1.R1.S03: PI = 001, PtrOffset = 005
N0.C2.D1.R1.S01: PI = 039, PtrOffset = 005
N2.C3.D1.R1.S04: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N4.C2.D1.R1.S07: Preamble found at Latency = 007
N6.C2.D1.R1.S04: PI = 001, PtrOffset = 005
N0.C2.D1.R1.S02: PI = 007, PtrOffset = 005
N2.C3.D1.R1.S05: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N4.C2.D1.R1.S08: Preamble found at Latency = 007
N6.C2.D1.R1.S05: PI = 013, PtrOffset = 005
N0.C2.D1.R1.S03: PI = 051, PtrOffset = 004
N2.C3.D1.R1.S06: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N4.C2.D1.R1.S00: Total Receive Enable Delay = 1309
N6.C2.D1.R1.S06: PI = 053, PtrOffset = 005
N0.C2.D1.R1.S04: PI = 053, PtrOffset = 004
N2.C3.D1.R1.S07: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N4.C2.D1.R1.S01: Total Receive Enable Delay = 1287
N6.C2.D1.R1.S07: PI = 004, PtrOffset = 004
N0.C2.D1.R1.S05: PI = 001, PtrOffset = 005
N2.C3.D1.R1.S08: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N4.C2.D1.R1.S02: Total Receive Enable Delay = 1257
N6.C2.D1.R1.S08: PI = 050, PtrOffset = 004
N0.C2.D1.R1.S06: PI = 040, PtrOffset = 005
N2.C3.D1.R1.S02: Preamble found at Latency = 007
N4.C2.D1.R1.S03: Total Receive Enable Delay = 1230
N6.C2.D1.R1.S00: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N0.C2.D1.R1.S07: PI = 056, PtrOffset = 005
N2.C3.D1.R1.S03: Preamble found at Latency = 007
N4.C2.D1.R1.S04: Total Receive Enable Delay = 1237
N6.C2.D1.R1.S01: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N0.C2.D1.R1.S08: PI = 042, PtrOffset = 004
N2.C3.D1.R1.S04: Preamble found at Latency = 007
N4.C2.D1.R1.S05: Total Receive Enable Delay = 1247
N6.C2.D1.R1.S02: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N0.C2.D1.R1.S00: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N2.C3.D1.R1.S05: Preamble found at Latency = 007
N4.C2.D1.R1.S06: Total Receive Enable Delay = 1286
N6.C2.D1.R1.S03: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N0.C2.D1.R1.S01: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N2.C3.D1.R1.S08: Preamble found at Latency = 007
N4.C2.D1.R1.S07: Total Receive Enable Delay = 1302
N6.C2.D1.R1.S04: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N0.C2.D1.R1.S02: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N2.C3.D1.R1.S00: Total Receive Enable Delay = 1358
N4.C2.D1.R1.S08: Total Receive Enable Delay = 1223
N6.C2.D1.R1.S05: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N0.C2.D1.R1.S03: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N2.C3.D1.R1.S01: Total Receive Enable Delay = 1337
N4.C2.D1.R1: Starting preamble search upper nibbles
N6.C2.D1.R1.S06: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N0.C2.D1.R1.S04: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N2.C3.D1.R1.S02: Total Receive Enable Delay = 1308
N4.C2.D1.R1.S09: PI = 060, PtrOffset = 005
N6.C2.D1.R1.S07: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N0.C2.D1.R1.S05: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N2.C3.D1.R1.S03: Total Receive Enable Delay = 1287
N4.C2.D1.R1.S10: PI = 037, PtrOffset = 005
N6.C2.D1.R1.S08: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N0.C2.D1.R1.S06: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N2.C3.D1.R1.S04: Total Receive Enable Delay = 1282
N4.C2.D1.R1.S11: PI = 006, PtrOffset = 005
N6.C2.D1.R1.S00: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N0.C2.D1.R1.S07: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N2.C3.D1.R1.S05: Total Receive Enable Delay = 1307
N4.C2.D1.R1.S12: PI = 048, PtrOffset = 004
N6.C2.D1.R1.S01: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N0.C2.D1.R1.S08: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N2.C3.D1.R1.S06: Total Receive Enable Delay = 1333
N4.C2.D1.R1.S13: PI = 051, PtrOffset = 004
N6.C2.D1.R1.S02: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N0.C2.D1.R1.S00: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N2.C3.D1.R1.S07: Total Receive Enable Delay = 1354
N4.C2.D1.R1.S14: PI = 002, PtrOffset = 005
N6.C2.D1.R1.S03: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N0.C2.D1.R1.S01: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N2.C3.D1.R1.S08: Total Receive Enable Delay = 1269
N4.C2.D1.R1.S15: PI = 037, PtrOffset = 005
N6.C2.D1.R1.S04: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N0.C2.D1.R1.S02: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N2.C3.D1.R1: Starting preamble search upper nibbles
N4.C2.D1.R1.S16: PI = 052, PtrOffset = 005
N6.C2.D1.R1.S05: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N0.C2.D1.R1.S03: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N2.C3.D1.R1.S09: PI = 047, PtrOffset = 004
N4.C2.D1.R1.S17: PI = 035, PtrOffset = 004
N6.C2.D1.R1.S06: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N0.C2.D1.R1.S04: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N2.C3.D1.R1.S10: PI = 025, PtrOffset = 004
N4.C2.D1.R1.S09: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N6.C2.D1.R1.S07: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N0.C2.D1.R1.S05: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N2.C3.D1.R1.S11: PI = 061, PtrOffset = 005
N4.C2.D1.R1.S10: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N6.C2.D1.R1.S08: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N0.C2.D1.R1.S06: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N2.C3.D1.R1.S12: PI = 043, PtrOffset = 005
N4.C2.D1.R1.S11: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N6.C2.D1.R1.S00: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N0.C2.D1.R1.S07: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N2.C3.D1.R1.S13: PI = 035, PtrOffset = 005
N4.C2.D1.R1.S12: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N6.C2.D1.R1.S01: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N0.C2.D1.R1.S08: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N2.C3.D1.R1.S14: PI = 057, PtrOffset = 005
N4.C2.D1.R1.S13: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N6.C2.D1.R1.S02: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N0.C2.D1.R1.S00: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N2.C3.D1.R1.S15: PI = 022, PtrOffset = 004
N4.C2.D1.R1.S14: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N6.C2.D1.R1.S03: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N0.C2.D1.R1.S01: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N2.C3.D1.R1.S16: PI = 042, PtrOffset = 004
N4.C2.D1.R1.S15: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N6.C2.D1.R1.S04: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N0.C2.D1.R1.S02: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N2.C3.D1.R1.S17: PI = 021, PtrOffset = 005
N4.C2.D1.R1.S16: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N6.C2.D1.R1.S05: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N0.C2.D1.R1.S03: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N2.C3.D1.R1.S09: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N4.C2.D1.R1.S17: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N6.C2.D1.R1.S06: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N0.C2.D1.R1.S04: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N2.C3.D1.R1.S10: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N4.C2.D1.R1.S09: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N6.C2.D1.R1.S07: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N0.C2.D1.R1.S05: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N2.C3.D1.R1.S11: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N4.C2.D1.R1.S10: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N6.C2.D1.R1.S08: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N0.C2.D1.R1.S06: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N2.C3.D1.R1.S12: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N4.C2.D1.R1.S11: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N6.C2.D1.R1.S00: Preamble found at Latency = 008
N0.C2.D1.R1.S07: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N2.C3.D1.R1.S13: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N4.C2.D1.R1.S12: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N6.C2.D1.R1.S07: Preamble found at Latency = 008
N0.C2.D1.R1.S08: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N2.C3.D1.R1.S14: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N4.C2.D1.R1.S13: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N6.C2.D1.R1.S00: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N0.C2.D1.R1.S00: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N2.C3.D1.R1.S15: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N4.C2.D1.R1.S14: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N6.C2.D1.R1.S01: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N0.C2.D1.R1.S01: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N2.C3.D1.R1.S16: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N4.C2.D1.R1.S15: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N6.C2.D1.R1.S02: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N0.C2.D1.R1.S02: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N2.C3.D1.R1.S17: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N4.C2.D1.R1.S16: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N6.C2.D1.R1.S03: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N0.C2.D1.R1.S03: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N2.C3.D1.R1.S09: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N4.C2.D1.R1.S17: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N6.C2.D1.R1.S04: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N0.C2.D1.R1.S04: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N2.C3.D1.R1.S10: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N4.C2.D1.R1.S09: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N6.C2.D1.R1.S05: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N0.C2.D1.R1.S05: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N2.C3.D1.R1.S11: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N4.C2.D1.R1.S10: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N6.C2.D1.R1.S06: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N0.C2.D1.R1.S06: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N2.C3.D1.R1.S12: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N4.C2.D1.R1.S11: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N6.C2.D1.R1.S07: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N0.C2.D1.R1.S07: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N2.C3.D1.R1.S13: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N4.C2.D1.R1.S12: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N6.C2.D1.R1.S08: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N0.C2.D1.R1.S08: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N2.C3.D1.R1.S14: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N4.C2.D1.R1.S13: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N6.C2.D1.R1.S01: Preamble found at Latency = 007
N0.C2.D1.R1.S00: Preamble found at Latency = 007
N2.C3.D1.R1.S15: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N4.C2.D1.R1.S14: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N6.C2.D1.R1.S02: Preamble found at Latency = 007
N0.C2.D1.R1.S01: Preamble found at Latency = 007
N2.C3.D1.R1.S16: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N4.C2.D1.R1.S15: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N6.C2.D1.R1.S03: Preamble found at Latency = 007
N0.C2.D1.R1.S02: Preamble found at Latency = 007
N2.C3.D1.R1.S17: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N4.C2.D1.R1.S16: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N6.C2.D1.R1.S04: Preamble found at Latency = 007
N0.C2.D1.R1.S03: Preamble found at Latency = 007
N2.C3.D1.R1.S09: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N4.C2.D1.R1.S17: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N6.C2.D1.R1.S05: Preamble found at Latency = 007
N0.C2.D1.R1.S04: Preamble found at Latency = 007
N2.C3.D1.R1.S10: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N4.C2.D1.R1.S09: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N6.C2.D1.R1.S06: Preamble found at Latency = 007
N0.C2.D1.R1.S05: Preamble found at Latency = 007
N2.C3.D1.R1.S11: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N4.C2.D1.R1.S10: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N6.C2.D1.R1.S08: Preamble found at Latency = 007
N0.C2.D1.R1.S06: Preamble found at Latency = 007
N2.C3.D1.R1.S12: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N4.C2.D1.R1.S11: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N6.C2.D1.R1.S00: Total Receive Enable Delay = 1322
N0.C2.D1.R1.S07: Preamble found at Latency = 007
N2.C3.D1.R1.S13: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N4.C2.D1.R1.S12: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N6.C2.D1.R1.S01: Total Receive Enable Delay = 1296
N0.C2.D1.R1.S08: Preamble found at Latency = 007
N2.C3.D1.R1.S14: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N4.C2.D1.R1.S13: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N6.C2.D1.R1.S02: Total Receive Enable Delay = 1269
N0.C2.D1.R1.S00: Total Receive Enable Delay = 1310
N2.C3.D1.R1.S15: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N4.C2.D1.R1.S14: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N6.C2.D1.R1.S03: Total Receive Enable Delay = 1249
N0.C2.D1.R1.S01: Total Receive Enable Delay = 1287
N2.C3.D1.R1.S16: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N4.C2.D1.R1.S15: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N6.C2.D1.R1.S04: Total Receive Enable Delay = 1249
N0.C2.D1.R1.S02: Total Receive Enable Delay = 1255
N2.C3.D1.R1.S17: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N4.C2.D1.R1.S16: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N6.C2.D1.R1.S05: Total Receive Enable Delay = 1261
N0.C2.D1.R1.S03: Total Receive Enable Delay = 1235
N2.C3.D1.R1.S09: Preamble found at Latency = 008
N4.C2.D1.R1.S17: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N6.C2.D1.R1.S06: Total Receive Enable Delay = 1301
N0.C2.D1.R1.S04: Total Receive Enable Delay = 1237
N2.C3.D1.R1.S10: Preamble found at Latency = 008
N4.C2.D1.R1.S09: Preamble found at Latency = 007
N6.C2.D1.R1.S07: Total Receive Enable Delay = 1316
N0.C2.D1.R1.S05: Total Receive Enable Delay = 1249
N2.C3.D1.R1.S15: Preamble found at Latency = 008
N4.C2.D1.R1.S10: Preamble found at Latency = 007
N6.C2.D1.R1.S08: Total Receive Enable Delay = 1234
N0.C2.D1.R1.S06: Total Receive Enable Delay = 1288
N2.C3.D1.R1.S16: Preamble found at Latency = 008
N4.C2.D1.R1.S11: Preamble found at Latency = 007
N6.C2.D1.R1: Starting preamble search upper nibbles
N0.C2.D1.R1.S07: Total Receive Enable Delay = 1304
N2.C3.D1.R1.S09: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N4.C2.D1.R1.S12: Preamble found at Latency = 007
N6.C2.D1.R1.S09: PI = 007, PtrOffset = 004
N0.C2.D1.R1.S08: Total Receive Enable Delay = 1226
N2.C3.D1.R1.S10: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N4.C2.D1.R1.S13: Preamble found at Latency = 007
N6.C2.D1.R1.S10: PI = 053, PtrOffset = 005
N0.C2.D1.R1: Starting preamble search upper nibbles
N2.C3.D1.R1.S11: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N4.C2.D1.R1.S14: Preamble found at Latency = 007
N6.C2.D1.R1.S11: PI = 018, PtrOffset = 005
N0.C2.D1.R1.S09: PI = 063, PtrOffset = 005
N2.C3.D1.R1.S12: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N4.C2.D1.R1.S15: Preamble found at Latency = 007
N6.C2.D1.R1.S12: PI = 002, PtrOffset = 005
N0.C2.D1.R1.S10: PI = 038, PtrOffset = 005
N2.C3.D1.R1.S13: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N4.C2.D1.R1.S16: Preamble found at Latency = 007
N6.C2.D1.R1.S13: PI = 000, PtrOffset = 005
N0.C2.D1.R1.S11: PI = 007, PtrOffset = 005
N2.C3.D1.R1.S14: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N4.C2.D1.R1.S17: Preamble found at Latency = 007
N6.C2.D1.R1.S14: PI = 011, PtrOffset = 005
N0.C2.D1.R1.S12: PI = 050, PtrOffset = 004
N2.C3.D1.R1.S15: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N4.C2.D1.R1: Preamble found for all upper nibbles, adjusting Pi, Offset to center into preamble
N6.C2.D1.R1.S15: PI = 051, PtrOffset = 005
N0.C2.D1.R1.S13: PI = 054, PtrOffset = 004
N2.C3.D1.R1.S16: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N4.C2.D1.R1.S09: Total Receive Enable Delay = 1308
N6.C2.D1.R1.S16: PI = 005, PtrOffset = 004
N0.C2.D1.R1.S14: PI = 001, PtrOffset = 005
N2.C3.D1.R1.S17: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N4.C2.D1.R1.S10: Total Receive Enable Delay = 1285
N6.C2.D1.R1.S17: PI = 052, PtrOffset = 004
N0.C2.D1.R1.S15: PI = 040, PtrOffset = 005
N2.C3.D1.R1.S11: Preamble found at Latency = 007
N4.C2.D1.R1.S11: Total Receive Enable Delay = 1254
N6.C2.D1.R1.S09: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N0.C2.D1.R1.S16: PI = 058, PtrOffset = 005
N2.C3.D1.R1.S12: Preamble found at Latency = 007
N4.C2.D1.R1.S12: Total Receive Enable Delay = 1232
N6.C2.D1.R1.S10: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N0.C2.D1.R1.S17: PI = 037, PtrOffset = 004
N2.C3.D1.R1.S13: Preamble found at Latency = 007
N4.C2.D1.R1.S13: Total Receive Enable Delay = 1235
N6.C2.D1.R1.S11: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N0.C2.D1.R1.S09: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N2.C3.D1.R1.S14: Preamble found at Latency = 007
N4.C2.D1.R1.S14: Total Receive Enable Delay = 1250
N6.C2.D1.R1.S12: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N0.C2.D1.R1.S10: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N2.C3.D1.R1.S17: Preamble found at Latency = 007
N4.C2.D1.R1.S15: Total Receive Enable Delay = 1285
N6.C2.D1.R1.S13: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N0.C2.D1.R1.S11: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N2.C3.D1.R1: Preamble found for all upper nibbles, adjusting Pi, Offset to center into preamble
N4.C2.D1.R1.S16: Total Receive Enable Delay = 1300
N6.C2.D1.R1.S14: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N0.C2.D1.R1.S12: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N2.C3.D1.R1.S09: Total Receive Enable Delay = 1359
N4.C2.D1.R1.S17: Total Receive Enable Delay = 1219
N6.C2.D1.R1.S15: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N0.C2.D1.R1.S13: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N2.C3.D1.R1.S10: Total Receive Enable Delay = 1337
START_DATA_REC_EN
N6.C2.D1.R1.S16: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N0.C2.D1.R1.S14: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N2.C3.D1.R1.S11: Total Receive Enable Delay = 1309
N4.C2.S00: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N6.C2.D1.R1.S17: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N0.C2.D1.R1.S15: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N2.C3.D1.R1.S12: Total Receive Enable Delay = 1291
N4.C2.S01: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N6.C2.D1.R1.S09: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N0.C2.D1.R1.S16: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N2.C3.D1.R1.S13: Total Receive Enable Delay = 1283
N4.C2.S02: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 5
N6.C2.D1.R1.S10: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N0.C2.D1.R1.S17: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N2.C3.D1.R1.S14: Total Receive Enable Delay = 1305
N4.C2.S03: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 5
N6.C2.D1.R1.S11: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N0.C2.D1.R1.S09: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N2.C3.D1.R1.S15: Total Receive Enable Delay = 1334
N4.C2.S04: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 5
N6.C2.D1.R1.S12: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N0.C2.D1.R1.S10: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N2.C3.D1.R1.S16: Total Receive Enable Delay = 1354
N4.C2.S05: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 5
N6.C2.D1.R1.S13: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N0.C2.D1.R1.S11: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N2.C3.D1.R1.S17: Total Receive Enable Delay = 1269
N4.C2.S06: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N6.C2.D1.R1.S14: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N0.C2.D1.R1.S12: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
START_DATA_REC_EN
N4.C2.S07: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N6.C2.D1.R1.S15: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N0.C2.D1.R1.S13: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N2.C3.S00: RdCmd2RcvEnLatency = 9, RdPtrOffsetRcvEn = 5
N4.C2.S08: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 5
N6.C2.D1.R1.S16: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N0.C2.D1.R1.S14: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N2.C3.S01: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N4.C2.S09: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N6.C2.D1.R1.S17: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N0.C2.D1.R1.S15: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N2.C3.S02: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N4.C2.S10: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N6.C2.D1.R1.S09: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N0.C2.D1.R1.S16: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N2.C3.S03: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N4.C2.S11: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 5
N6.C2.D1.R1.S10: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N0.C2.D1.R1.S17: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N2.C3.S04: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N4.C2.S12: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 5
N6.C2.D1.R1.S11: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N0.C2.D1.R1.S09: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N2.C3.S05: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N4.C2.S13: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 5
N6.C2.D1.R1.S12: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N0.C2.D1.R1.S10: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N2.C3.S06: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N4.C2.S14: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 5
N6.C2.D1.R1.S13: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N0.C2.D1.R1.S11: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N2.C3.S07: RdCmd2RcvEnLatency = 9, RdPtrOffsetRcvEn = 5
N4.C2.S15: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N6.C2.D1.R1.S14: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N0.C2.D1.R1.S12: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N2.C3.S08: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 5
N4.C2.S16: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N6.C2.D1.R1.S15: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N0.C2.D1.R1.S13: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N2.C3.S09: RdCmd2RcvEnLatency = 9, RdPtrOffsetRcvEn = 5
N4.C2.S17: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 5
N6.C2.D1.R1.S16: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N0.C2.D1.R1.S14: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N2.C3.S10: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N4.C2.D0.R0.S00: RcvEn: plus1 = 1, minus1 = 0, PI = 46, DB = 0
N6.C2.D1.R1.S17: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N0.C2.D1.R1.S15: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N2.C3.S11: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N4.C2.D0.R0.S01: RcvEn: plus1 = 1, minus1 = 0, PI = 22, DB = 0
N6.C2.D1.R1.S09: Preamble found at Latency = 008
N0.C2.D1.R1.S16: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N2.C3.S12: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N4.C2.D0.R0.S02: RcvEn: plus1 = 1, minus1 = 0, PI = 57, DB = 1
N6.C2.D1.R1.S16: Preamble found at Latency = 008
N0.C2.D1.R1.S17: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N2.C3.S13: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N4.C2.D0.R0.S03: RcvEn: plus1 = 1, minus1 = 0, PI = 34, DB = 0
N6.C2.D1.R1.S09: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N0.C2.D1.R1.S09: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N2.C3.S14: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N4.C2.D0.R0.S04: RcvEn: plus1 = 1, minus1 = 0, PI = 36, DB = 0
N6.C2.D1.R1.S10: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N0.C2.D1.R1.S10: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N2.C3.S15: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N4.C2.D0.R0.S05: RcvEn: plus1 = 1, minus1 = 0, PI = 47, DB = 0
N6.C2.D1.R1.S11: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N0.C2.D1.R1.S11: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N2.C3.S16: RdCmd2RcvEnLatency = 9, RdPtrOffsetRcvEn = 5
N4.C2.D0.R0.S06: RcvEn: plus1 = 1, minus1 = 0, PI = 22, DB = 0
N6.C2.D1.R1.S12: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N0.C2.D1.R1.S12: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N2.C3.S17: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 5
N4.C2.D0.R0.S07: RcvEn: plus1 = 1, minus1 = 0, PI = 38, DB = 0
N6.C2.D1.R1.S13: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N0.C2.D1.R1.S13: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N2.C3.D0.R0.S00: RcvEn: plus1 = 1, minus1 = 0, PI = 30, DB = 0
N4.C2.D0.R0.S08: RcvEn: plus1 = 1, minus1 = 0, PI = 23, DB = 0
N6.C2.D1.R1.S14: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N0.C2.D1.R1.S14: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N2.C3.D0.R0.S01: RcvEn: plus1 = 0, minus1 = 1, PI = 07, DB = 1
N4.C2.D0.R0.S09: RcvEn: plus1 = 1, minus1 = 0, PI = 43, DB = 0
N6.C2.D1.R1.S15: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N0.C2.D1.R1.S15: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N2.C3.D0.R0.S02: RcvEn: plus1 = 1, minus1 = 0, PI = 43, DB = 0
N4.C2.D0.R0.S10: RcvEn: plus1 = 1, minus1 = 0, PI = 22, DB = 0
N6.C2.D1.R1.S16: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N0.C2.D1.R1.S16: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N2.C3.D0.R0.S03: RcvEn: plus1 = 1, minus1 = 0, PI = 21, DB = 0
N4.C2.D0.R0.S11: RcvEn: plus1 = 1, minus1 = 0, PI = 54, DB = 1
N6.C2.D1.R1.S17: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N0.C2.D1.R1.S17: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N2.C3.D0.R0.S04: RcvEn: plus1 = 1, minus1 = 0, PI = 16, DB = 0
N4.C2.D0.R0.S12: RcvEn: plus1 = 1, minus1 = 0, PI = 35, DB = 0
N6.C2.D1.R1.S10: Preamble found at Latency = 007
N0.C2.D1.R1.S09: Preamble found at Latency = 007
N2.C3.D0.R0.S05: RcvEn: plus1 = 1, minus1 = 0, PI = 41, DB = 0
N4.C2.D0.R0.S13: RcvEn: plus1 = 1, minus1 = 0, PI = 34, DB = 0
N6.C2.D1.R1.S11: Preamble found at Latency = 007
N0.C2.D1.R1.S10: Preamble found at Latency = 007
N2.C3.D0.R0.S06: RcvEn: plus1 = 0, minus1 = 1, PI = 01, DB = 1
N4.C2.D0.R0.S14: RcvEn: plus1 = 1, minus1 = 0, PI = 50, DB = 1
N6.C2.D1.R1.S12: Preamble found at Latency = 007
N0.C2.D1.R1.S11: Preamble found at Latency = 007
N2.C3.D0.R0.S07: RcvEn: plus1 = 1, minus1 = 0, PI = 22, DB = 0
N4.C2.D0.R0.S15: RcvEn: plus1 = 1, minus1 = 0, PI = 22, DB = 0
N6.C2.D1.R1.S13: Preamble found at Latency = 007
N0.C2.D1.R1.S12: Preamble found at Latency = 007
N2.C3.D0.R0.S08: RcvEn: plus1 = 0, minus1 = 1, PI = 02, DB = 1
N4.C2.D0.R0.S16: RcvEn: plus1 = 1, minus1 = 0, PI = 39, DB = 0
N6.C2.D1.R1.S14: Preamble found at Latency = 007
N0.C2.D1.R1.S13: Preamble found at Latency = 007
N2.C3.D0.R0.S09: RcvEn: plus1 = 1, minus1 = 0, PI = 31, DB = 0
N4.C2.D0.R0.S17: RcvEn: plus1 = 1, minus1 = 0, PI = 20, DB = 0
N6.C2.D1.R1.S15: Preamble found at Latency = 007
N0.C2.D1.R1.S14: Preamble found at Latency = 007
N2.C3.D0.R0.S10: RcvEn: plus1 = 0, minus1 = 1, PI = 08, DB = 1
N4.C2.D0.R1.S00: RcvEn: plus1 = 1, minus1 = 0, PI = 46, DB = 0
N6.C2.D1.R1.S17: Preamble found at Latency = 007
N0.C2.D1.R1.S15: Preamble found at Latency = 007
N2.C3.D0.R0.S11: RcvEn: plus1 = 1, minus1 = 0, PI = 43, DB = 0
N4.C2.D0.R1.S01: RcvEn: plus1 = 1, minus1 = 0, PI = 22, DB = 0
N6.C2.D1.R1: Preamble found for all upper nibbles, adjusting Pi, Offset to center into preamble
N0.C2.D1.R1.S16: Preamble found at Latency = 007
N2.C3.D0.R0.S12: RcvEn: plus1 = 1, minus1 = 0, PI = 22, DB = 0
N4.C2.D0.R1.S02: RcvEn: plus1 = 1, minus1 = 0, PI = 57, DB = 1
N6.C2.D1.R1.S09: Total Receive Enable Delay = 1319
N0.C2.D1.R1.S17: Preamble found at Latency = 007
N2.C3.D0.R0.S13: RcvEn: plus1 = 1, minus1 = 0, PI = 18, DB = 0
N4.C2.D0.R1.S03: RcvEn: plus1 = 1, minus1 = 0, PI = 34, DB = 0
N6.C2.D1.R1.S10: Total Receive Enable Delay = 1301
N0.C2.D1.R1: Preamble found for all upper nibbles, adjusting Pi, Offset to center into preamble
N2.C3.D0.R0.S14: RcvEn: plus1 = 1, minus1 = 0, PI = 41, DB = 0
N4.C2.D0.R1.S04: RcvEn: plus1 = 1, minus1 = 0, PI = 36, DB = 0
N6.C2.D1.R1.S11: Total Receive Enable Delay = 1266
N0.C2.D1.R1.S09: Total Receive Enable Delay = 1311
N2.C3.D0.R0.S15: RcvEn: plus1 = 0, minus1 = 1, PI = 02, DB = 1
N4.C2.D0.R1.S05: RcvEn: plus1 = 1, minus1 = 0, PI = 47, DB = 0
N6.C2.D1.R1.S12: Total Receive Enable Delay = 1250
N0.C2.D1.R1.S10: Total Receive Enable Delay = 1286
N2.C3.D0.R0.S16: RcvEn: plus1 = 1, minus1 = 0, PI = 24, DB = 0
N4.C2.D0.R1.S06: RcvEn: plus1 = 1, minus1 = 0, PI = 22, DB = 0
N6.C2.D1.R1.S13: Total Receive Enable Delay = 1248
N0.C2.D1.R1.S11: Total Receive Enable Delay = 1255
N2.C3.D0.R0.S17: RcvEn: plus1 = 0, minus1 = 1, PI = 04, DB = 1
N4.C2.D0.R1.S07: RcvEn: plus1 = 1, minus1 = 0, PI = 38, DB = 0
N6.C2.D1.R1.S14: Total Receive Enable Delay = 1259
N0.C2.D1.R1.S12: Total Receive Enable Delay = 1234
N2.C3.D0.R1.S00: RcvEn: plus1 = 1, minus1 = 0, PI = 30, DB = 0
N4.C2.D0.R1.S08: RcvEn: plus1 = 1, minus1 = 0, PI = 23, DB = 0
N6.C2.D1.R1.S15: Total Receive Enable Delay = 1299
N0.C2.D1.R1.S13: Total Receive Enable Delay = 1238
N2.C3.D0.R1.S01: RcvEn: plus1 = 0, minus1 = 1, PI = 07, DB = 1
N4.C2.D0.R1.S09: RcvEn: plus1 = 1, minus1 = 0, PI = 43, DB = 0
N6.C2.D1.R1.S16: Total Receive Enable Delay = 1317
N0.C2.D1.R1.S14: Total Receive Enable Delay = 1249
N2.C3.D0.R1.S02: RcvEn: plus1 = 1, minus1 = 0, PI = 43, DB = 0
N4.C2.D0.R1.S10: RcvEn: plus1 = 1, minus1 = 0, PI = 22, DB = 0
N6.C2.D1.R1.S17: Total Receive Enable Delay = 1236
N0.C2.D1.R1.S15: Total Receive Enable Delay = 1288
N2.C3.D0.R1.S03: RcvEn: plus1 = 1, minus1 = 0, PI = 21, DB = 0
N4.C2.D0.R1.S11: RcvEn: plus1 = 1, minus1 = 0, PI = 54, DB = 1
START_DATA_REC_EN
N0.C2.D1.R1.S16: Total Receive Enable Delay = 1306
N2.C3.D0.R1.S04: RcvEn: plus1 = 1, minus1 = 0, PI = 16, DB = 0
N4.C2.D0.R1.S12: RcvEn: plus1 = 1, minus1 = 0, PI = 35, DB = 0
N6.C2.S00: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N0.C2.D1.R1.S17: Total Receive Enable Delay = 1221
N2.C3.D0.R1.S05: RcvEn: plus1 = 1, minus1 = 0, PI = 41, DB = 0
N4.C2.D0.R1.S13: RcvEn: plus1 = 1, minus1 = 0, PI = 34, DB = 0
N6.C2.S01: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
START_DATA_REC_EN
N2.C3.D0.R1.S06: RcvEn: plus1 = 0, minus1 = 1, PI = 01, DB = 1
N4.C2.D0.R1.S14: RcvEn: plus1 = 1, minus1 = 0, PI = 50, DB = 1
N6.C2.S02: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 5
N0.C2.S00: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N2.C3.D0.R1.S07: RcvEn: plus1 = 1, minus1 = 0, PI = 22, DB = 0
N4.C2.D0.R1.S15: RcvEn: plus1 = 1, minus1 = 0, PI = 22, DB = 0
N6.C2.S03: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 5
N0.C2.S01: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N2.C3.D0.R1.S08: RcvEn: plus1 = 0, minus1 = 1, PI = 02, DB = 1
N4.C2.D0.R1.S16: RcvEn: plus1 = 1, minus1 = 0, PI = 39, DB = 0
N6.C2.S04: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 5
N0.C2.S02: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 5
N2.C3.D0.R1.S09: RcvEn: plus1 = 1, minus1 = 0, PI = 31, DB = 0
N4.C2.D0.R1.S17: RcvEn: plus1 = 1, minus1 = 0, PI = 20, DB = 0
N6.C2.S05: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 5
N0.C2.S03: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 5
N2.C3.D0.R1.S10: RcvEn: plus1 = 0, minus1 = 1, PI = 08, DB = 1
N4.C2.D1.R0.S00: RcvEn: plus1 = 1, minus1 = 0, PI = 29, DB = 0
N6.C2.S06: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N0.C2.S04: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 5
N2.C3.D0.R1.S11: RcvEn: plus1 = 1, minus1 = 0, PI = 43, DB = 0
N4.C2.D1.R0.S01: RcvEn: plus1 = 1, minus1 = 0, PI = 06, DB = 1
N6.C2.S07: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N0.C2.S05: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 5
N2.C3.D0.R1.S12: RcvEn: plus1 = 1, minus1 = 0, PI = 22, DB = 0
N4.C2.D1.R0.S02: RcvEn: plus1 = 1, minus1 = 0, PI = 42, DB = 0
N6.C2.S08: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 5
N0.C2.S06: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N2.C3.D0.R1.S13: RcvEn: plus1 = 1, minus1 = 0, PI = 18, DB = 0
N4.C2.D1.R0.S03: RcvEn: plus1 = 1, minus1 = 0, PI = 16, DB = 0
N6.C2.S09: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N0.C2.S07: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N2.C3.D0.R1.S14: RcvEn: plus1 = 1, minus1 = 0, PI = 41, DB = 0
N4.C2.D1.R0.S04: RcvEn: plus1 = 1, minus1 = 0, PI = 20, DB = 0
N6.C2.S10: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N0.C2.S08: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 5
N2.C3.D0.R1.S15: RcvEn: plus1 = 0, minus1 = 1, PI = 02, DB = 1
N4.C2.D1.R0.S05: RcvEn: plus1 = 1, minus1 = 0, PI = 32, DB = 0
N6.C2.S11: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 5
N0.C2.S09: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N2.C3.D0.R1.S16: RcvEn: plus1 = 1, minus1 = 0, PI = 24, DB = 0
N4.C2.D1.R0.S06: RcvEn: plus1 = 1, minus1 = 0, PI = 06, DB = 1
N6.C2.S12: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 5
N0.C2.S10: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N2.C3.D0.R1.S17: RcvEn: plus1 = 0, minus1 = 1, PI = 04, DB = 1
N4.C2.D1.R0.S07: RcvEn: plus1 = 1, minus1 = 0, PI = 22, DB = 0
N6.C2.S13: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 5
N0.C2.S11: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 5
N2.C3.D1.R0.S00: RcvEn: plus1 = 1, minus1 = 0, PI = 14, DB = 1
N4.C2.D1.R0.S08: RcvEn: plus1 = 1, minus1 = 0, PI = 07, DB = 1
N6.C2.S14: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 5
N0.C2.S12: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 5
N2.C3.D1.R0.S01: RcvEn: plus1 = 1, minus1 = 0, PI = 57, DB = 1
N4.C2.D1.R0.S09: RcvEn: plus1 = 1, minus1 = 0, PI = 29, DB = 0
N6.C2.S15: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N0.C2.S13: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 5
N2.C3.D1.R0.S02: RcvEn: plus1 = 1, minus1 = 0, PI = 28, DB = 0
N4.C2.D1.R0.S10: RcvEn: plus1 = 1, minus1 = 0, PI = 05, DB = 1
N6.C2.S16: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N0.C2.S14: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 5
N2.C3.D1.R0.S03: RcvEn: plus1 = 1, minus1 = 0, PI = 07, DB = 1
N4.C2.D1.R0.S11: RcvEn: plus1 = 1, minus1 = 0, PI = 39, DB = 0
N6.C2.S17: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 5
N0.C2.S15: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N2.C3.D1.R0.S04: RcvEn: plus1 = 1, minus1 = 0, PI = 01, DB = 1
N4.C2.D1.R0.S12: RcvEn: plus1 = 1, minus1 = 0, PI = 17, DB = 0
N6.C2.D0.R0.S00: RcvEn: plus1 = 1, minus1 = 0, PI = 52, DB = 1
N0.C2.S16: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N2.C3.D1.R0.S05: RcvEn: plus1 = 1, minus1 = 0, PI = 26, DB = 0
N4.C2.D1.R0.S13: RcvEn: plus1 = 1, minus1 = 0, PI = 19, DB = 0
N6.C2.D0.R0.S01: RcvEn: plus1 = 1, minus1 = 0, PI = 26, DB = 0
N0.C2.S17: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 5
N2.C3.D1.R0.S06: RcvEn: plus1 = 1, minus1 = 0, PI = 52, DB = 1
N4.C2.D1.R0.S14: RcvEn: plus1 = 1, minus1 = 0, PI = 34, DB = 0
N6.C2.D0.R0.S02: RcvEn: plus1 = 1, minus1 = 0, PI = 63, DB = 1
N0.C2.D0.R0.S00: RcvEn: plus1 = 1, minus1 = 0, PI = 49, DB = 1
N2.C3.D1.R0.S07: RcvEn: plus1 = 1, minus1 = 0, PI = 10, DB = 1
N4.C2.D1.R0.S15: RcvEn: plus1 = 1, minus1 = 0, PI = 05, DB = 1
N6.C2.D0.R0.S03: RcvEn: plus1 = 1, minus1 = 0, PI = 42, DB = 0
N0.C2.D0.R0.S01: RcvEn: plus1 = 1, minus1 = 0, PI = 28, DB = 0
N2.C3.D1.R0.S08: RcvEn: plus1 = 1, minus1 = 0, PI = 54, DB = 1
N4.C2.D1.R0.S16: RcvEn: plus1 = 1, minus1 = 0, PI = 21, DB = 0
N6.C2.D0.R0.S04: RcvEn: plus1 = 1, minus1 = 0, PI = 44, DB = 0
N0.C2.D0.R0.S02: RcvEn: plus1 = 1, minus1 = 0, PI = 61, DB = 1
N2.C3.D1.R0.S09: RcvEn: plus1 = 1, minus1 = 0, PI = 15, DB = 1
N4.C2.D1.R0.S17: RcvEn: plus1 = 1, minus1 = 0, PI = 04, DB = 1
N6.C2.D0.R0.S05: RcvEn: plus1 = 1, minus1 = 0, PI = 54, DB = 1
N0.C2.D0.R0.S03: RcvEn: plus1 = 1, minus1 = 0, PI = 39, DB = 0
N2.C3.D1.R0.S10: RcvEn: plus1 = 1, minus1 = 0, PI = 57, DB = 1
N4.C2.D1.R1.S00: RcvEn: plus1 = 1, minus1 = 0, PI = 29, DB = 0
N6.C2.D0.R0.S06: RcvEn: plus1 = 1, minus1 = 0, PI = 29, DB = 0
N0.C2.D0.R0.S04: RcvEn: plus1 = 1, minus1 = 0, PI = 41, DB = 0
N2.C3.D1.R0.S11: RcvEn: plus1 = 1, minus1 = 0, PI = 30, DB = 0
N4.C2.D1.R1.S01: RcvEn: plus1 = 1, minus1 = 0, PI = 06, DB = 1
N6.C2.D0.R0.S07: RcvEn: plus1 = 1, minus1 = 0, PI = 45, DB = 0
N0.C2.D0.R0.S05: RcvEn: plus1 = 1, minus1 = 0, PI = 53, DB = 1
N2.C3.D1.R0.S12: RcvEn: plus1 = 1, minus1 = 0, PI = 10, DB = 1
N4.C2.D1.R1.S02: RcvEn: plus1 = 1, minus1 = 0, PI = 42, DB = 0
N6.C2.D0.R0.S08: RcvEn: plus1 = 1, minus1 = 0, PI = 27, DB = 0
N0.C2.D0.R0.S06: RcvEn: plus1 = 1, minus1 = 0, PI = 26, DB = 0
N2.C3.D1.R0.S13: RcvEn: plus1 = 1, minus1 = 0, PI = 02, DB = 1
N4.C2.D1.R1.S03: RcvEn: plus1 = 1, minus1 = 0, PI = 16, DB = 0
N6.C2.D0.R0.S09: RcvEn: plus1 = 1, minus1 = 0, PI = 49, DB = 1
N0.C2.D0.R0.S07: RcvEn: plus1 = 1, minus1 = 0, PI = 45, DB = 0
N2.C3.D1.R0.S14: RcvEn: plus1 = 1, minus1 = 0, PI = 27, DB = 0
N4.C2.D1.R1.S04: RcvEn: plus1 = 1, minus1 = 0, PI = 20, DB = 0
N6.C2.D0.R0.S10: RcvEn: plus1 = 1, minus1 = 0, PI = 29, DB = 0
N0.C2.D0.R0.S08: RcvEn: plus1 = 1, minus1 = 0, PI = 28, DB = 0
N2.C3.D1.R0.S15: RcvEn: plus1 = 1, minus1 = 0, PI = 52, DB = 1
N4.C2.D1.R1.S05: RcvEn: plus1 = 1, minus1 = 0, PI = 32, DB = 0
N6.C2.D0.R0.S11: RcvEn: plus1 = 1, minus1 = 0, PI = 62, DB = 1
N0.C2.D0.R0.S09: RcvEn: plus1 = 1, minus1 = 0, PI = 49, DB = 1
N2.C3.D1.R0.S16: RcvEn: plus1 = 1, minus1 = 0, PI = 11, DB = 1
N4.C2.D1.R1.S06: RcvEn: plus1 = 1, minus1 = 0, PI = 06, DB = 1
N6.C2.D0.R0.S12: RcvEn: plus1 = 1, minus1 = 0, PI = 44, DB = 0
N0.C2.D0.R0.S10: RcvEn: plus1 = 1, minus1 = 0, PI = 25, DB = 0
N2.C3.D1.R0.S17: RcvEn: plus1 = 1, minus1 = 0, PI = 53, DB = 1
N4.C2.D1.R1.S07: RcvEn: plus1 = 1, minus1 = 0, PI = 22, DB = 0
N6.C2.D0.R0.S13: RcvEn: plus1 = 1, minus1 = 0, PI = 41, DB = 0
N0.C2.D0.R0.S11: RcvEn: plus1 = 1, minus1 = 0, PI = 60, DB = 1
N2.C3.D1.R1.S00: RcvEn: plus1 = 1, minus1 = 0, PI = 14, DB = 1
N4.C2.D1.R1.S08: RcvEn: plus1 = 1, minus1 = 0, PI = 07, DB = 1
N6.C2.D0.R0.S14: RcvEn: plus1 = 1, minus1 = 0, PI = 53, DB = 1
N0.C2.D0.R0.S12: RcvEn: plus1 = 1, minus1 = 0, PI = 40, DB = 0
N2.C3.D1.R1.S01: RcvEn: plus1 = 1, minus1 = 0, PI = 57, DB = 1
N4.C2.D1.R1.S09: RcvEn: plus1 = 1, minus1 = 0, PI = 29, DB = 0
N6.C2.D0.R0.S15: RcvEn: plus1 = 1, minus1 = 0, PI = 30, DB = 0
N0.C2.D0.R0.S13: RcvEn: plus1 = 1, minus1 = 0, PI = 41, DB = 0
N2.C3.D1.R1.S02: RcvEn: plus1 = 1, minus1 = 0, PI = 28, DB = 0
N4.C2.D1.R1.S10: RcvEn: plus1 = 1, minus1 = 0, PI = 05, DB = 1
N6.C2.D0.R0.S16: RcvEn: plus1 = 1, minus1 = 0, PI = 45, DB = 0
N0.C2.D0.R0.S14: RcvEn: plus1 = 1, minus1 = 0, PI = 52, DB = 1
N2.C3.D1.R1.S03: RcvEn: plus1 = 1, minus1 = 0, PI = 07, DB = 1
N4.C2.D1.R1.S11: RcvEn: plus1 = 1, minus1 = 0, PI = 39, DB = 0
N6.C2.D0.R0.S17: RcvEn: plus1 = 1, minus1 = 0, PI = 31, DB = 0
N0.C2.D0.R0.S15: RcvEn: plus1 = 1, minus1 = 0, PI = 26, DB = 0
N2.C3.D1.R1.S04: RcvEn: plus1 = 1, minus1 = 0, PI = 01, DB = 1
N4.C2.D1.R1.S12: RcvEn: plus1 = 1, minus1 = 0, PI = 17, DB = 0
N6.C2.D0.R1.S00: RcvEn: plus1 = 1, minus1 = 0, PI = 52, DB = 1
N0.C2.D0.R0.S16: RcvEn: plus1 = 1, minus1 = 0, PI = 45, DB = 0
N2.C3.D1.R1.S05: RcvEn: plus1 = 1, minus1 = 0, PI = 26, DB = 0
N4.C2.D1.R1.S13: RcvEn: plus1 = 1, minus1 = 0, PI = 19, DB = 0
N6.C2.D0.R1.S01: RcvEn: plus1 = 1, minus1 = 0, PI = 26, DB = 0
N0.C2.D0.R0.S17: RcvEn: plus1 = 1, minus1 = 0, PI = 23, DB = 0
N2.C3.D1.R1.S06: RcvEn: plus1 = 1, minus1 = 0, PI = 52, DB = 1
N4.C2.D1.R1.S14: RcvEn: plus1 = 1, minus1 = 0, PI = 34, DB = 0
N6.C2.D0.R1.S02: RcvEn: plus1 = 1, minus1 = 0, PI = 63, DB = 1
N0.C2.D0.R1.S00: RcvEn: plus1 = 1, minus1 = 0, PI = 49, DB = 1
N2.C3.D1.R1.S07: RcvEn: plus1 = 1, minus1 = 0, PI = 10, DB = 1
N4.C2.D1.R1.S15: RcvEn: plus1 = 1, minus1 = 0, PI = 05, DB = 1
N6.C2.D0.R1.S03: RcvEn: plus1 = 1, minus1 = 0, PI = 42, DB = 0
N0.C2.D0.R1.S01: RcvEn: plus1 = 1, minus1 = 0, PI = 28, DB = 0
N2.C3.D1.R1.S08: RcvEn: plus1 = 1, minus1 = 0, PI = 54, DB = 1
N4.C2.D1.R1.S16: RcvEn: plus1 = 1, minus1 = 0, PI = 21, DB = 0
N6.C2.D0.R1.S04: RcvEn: plus1 = 1, minus1 = 0, PI = 44, DB = 0
N0.C2.D0.R1.S02: RcvEn: plus1 = 1, minus1 = 0, PI = 61, DB = 1
N2.C3.D1.R1.S09: RcvEn: plus1 = 1, minus1 = 0, PI = 15, DB = 1
N4.C2.D1.R1.S17: RcvEn: plus1 = 1, minus1 = 0, PI = 04, DB = 1
N6.C2.D0.R1.S05: RcvEn: plus1 = 1, minus1 = 0, PI = 54, DB = 1
N0.C2.D0.R1.S03: RcvEn: plus1 = 1, minus1 = 0, PI = 39, DB = 0
N2.C3.D1.R1.S10: RcvEn: plus1 = 1, minus1 = 0, PI = 57, DB = 1
STOP_DATA_REC_EN
N6.C2.D0.R1.S06: RcvEn: plus1 = 1, minus1 = 0, PI = 29, DB = 0
N0.C2.D0.R1.S04: RcvEn: plus1 = 1, minus1 = 0, PI = 41, DB = 0
N2.C3.D1.R1.S11: RcvEn: plus1 = 1, minus1 = 0, PI = 30, DB = 0
N4.C3.D0.R0: RcvEnFine: Initial RdCmd2RcvEnLatency = 10, Initial RdPtrOffsetRcvEn = 4
N6.C2.D0.R1.S07: RcvEn: plus1 = 1, minus1 = 0, PI = 45, DB = 0
N0.C2.D0.R1.S05: RcvEn: plus1 = 1, minus1 = 0, PI = 53, DB = 1
N2.C3.D1.R1.S12: RcvEn: plus1 = 1, minus1 = 0, PI = 10, DB = 1
N4.C3.D0.R0.S00: Rcv En Fine Value = 317
N6.C2.D0.R1.S08: RcvEn: plus1 = 1, minus1 = 0, PI = 27, DB = 0
N0.C2.D0.R1.S06: RcvEn: plus1 = 1, minus1 = 0, PI = 26, DB = 0
N2.C3.D1.R1.S13: RcvEn: plus1 = 1, minus1 = 0, PI = 02, DB = 1
N4.C3.D0.R0.S01: Rcv En Fine Value = 298
N6.C2.D0.R1.S09: RcvEn: plus1 = 1, minus1 = 0, PI = 49, DB = 1
N0.C2.D0.R1.S07: RcvEn: plus1 = 1, minus1 = 0, PI = 45, DB = 0
N2.C3.D1.R1.S14: RcvEn: plus1 = 1, minus1 = 0, PI = 27, DB = 0
N4.C3.D0.R0.S02: Rcv En Fine Value = 269
N6.C2.D0.R1.S10: RcvEn: plus1 = 1, minus1 = 0, PI = 29, DB = 0
N0.C2.D0.R1.S08: RcvEn: plus1 = 1, minus1 = 0, PI = 28, DB = 0
N2.C3.D1.R1.S15: RcvEn: plus1 = 1, minus1 = 0, PI = 52, DB = 1
N4.C3.D0.R0.S03: Rcv En Fine Value = 375
N6.C2.D0.R1.S11: RcvEn: plus1 = 1, minus1 = 0, PI = 62, DB = 1
N0.C2.D0.R1.S09: RcvEn: plus1 = 1, minus1 = 0, PI = 49, DB = 1
N2.C3.D1.R1.S16: RcvEn: plus1 = 1, minus1 = 0, PI = 11, DB = 1
N4.C3.D0.R0.S04: Rcv En Fine Value = 370
N6.C2.D0.R1.S12: RcvEn: plus1 = 1, minus1 = 0, PI = 44, DB = 0
N0.C2.D0.R1.S10: RcvEn: plus1 = 1, minus1 = 0, PI = 25, DB = 0
N2.C3.D1.R1.S17: RcvEn: plus1 = 1, minus1 = 0, PI = 53, DB = 1
N4.C3.D0.R0.S05: Rcv En Fine Value = 265
N6.C2.D0.R1.S13: RcvEn: plus1 = 1, minus1 = 0, PI = 41, DB = 0
N0.C2.D0.R1.S11: RcvEn: plus1 = 1, minus1 = 0, PI = 60, DB = 1
STOP_DATA_REC_EN
N4.C3.D0.R0.S06: Rcv En Fine Value = 290
N6.C2.D0.R1.S14: RcvEn: plus1 = 1, minus1 = 0, PI = 53, DB = 1
N0.C2.D0.R1.S12: RcvEn: plus1 = 1, minus1 = 0, PI = 40, DB = 0
N2.C0.D0.R0.S00: StoreJckWorstRank: worst rank = 0, greatestDelay = 1327
N4.C3.D0.R0.S07: Rcv En Fine Value = 312
N6.C2.D0.R1.S15: RcvEn: plus1 = 1, minus1 = 0, PI = 30, DB = 0
N0.C2.D0.R1.S13: RcvEn: plus1 = 1, minus1 = 0, PI = 41, DB = 0
N2.C0.D0.R0.S07: StoreJckWorstRank: worst rank = 0, greatestDelay = 1328
N4.C3.D0.R0.S08: Rcv En Fine Value = 353
N6.C2.D0.R1.S16: RcvEn: plus1 = 1, minus1 = 0, PI = 45, DB = 0
N0.C2.D0.R1.S14: RcvEn: plus1 = 1, minus1 = 0, PI = 52, DB = 1
N2.C1.D0.R0.S00: StoreJckWorstRank: worst rank = 0, greatestDelay = 1373
N4.C3.D0.R0.S09: Rcv En Fine Value = 316
N6.C2.D0.R1.S17: RcvEn: plus1 = 1, minus1 = 0, PI = 31, DB = 0
N0.C2.D0.R1.S15: RcvEn: plus1 = 1, minus1 = 0, PI = 26, DB = 0
N2.C1.D0.R0.S09: StoreJckWorstRank: worst rank = 0, greatestDelay = 1374
N4.C3.D0.R0.S10: Rcv En Fine Value = 298
N6.C2.D1.R0.S00: RcvEn: plus1 = 1, minus1 = 0, PI = 42, DB = 0
N0.C2.D0.R1.S16: RcvEn: plus1 = 1, minus1 = 0, PI = 45, DB = 0
N2.C1.D0.R1.S00: StoreJckWorstRank: worst rank = 1, greatestDelay = 1375
N4.C3.D0.R0.S11: Rcv En Fine Value = 270
N6.C2.D1.R0.S01: RcvEn: plus1 = 1, minus1 = 0, PI = 16, DB = 0
N0.C2.D0.R1.S17: RcvEn: plus1 = 1, minus1 = 0, PI = 23, DB = 0
N2.C0: StoreJckWorstRank: final value: worst rank = 1
N4.C3.D0.R0.S12: Rcv En Fine Value = 376
N6.C2.D1.R0.S02: RcvEn: plus1 = 1, minus1 = 0, PI = 53, DB = 1
N0.C2.D1.R0.S00: RcvEn: plus1 = 1, minus1 = 0, PI = 30, DB = 0
N2.C2.D0.R0.S00: StoreJckWorstRank: worst rank = 0, greatestDelay = 1329
N4.C3.D0.R0.S13: Rcv En Fine Value = 369
N6.C2.D1.R0.S03: RcvEn: plus1 = 1, minus1 = 0, PI = 34, DB = 0
N0.C2.D1.R0.S01: RcvEn: plus1 = 1, minus1 = 0, PI = 07, DB = 1
N2.C2.D0.R0.S09: StoreJckWorstRank: worst rank = 0, greatestDelay = 1331
N4.C3.D0.R0.S14: Rcv En Fine Value = 266
N6.C2.D1.R0.S04: RcvEn: plus1 = 1, minus1 = 0, PI = 33, DB = 0
N0.C2.D1.R0.S02: RcvEn: plus1 = 1, minus1 = 0, PI = 40, DB = 0
N2.C3.D0.R0.S00: StoreJckWorstRank: worst rank = 0, greatestDelay = 1375
N4.C3.D0.R0.S15: Rcv En Fine Value = 290
N6.C2.D1.R0.S05: RcvEn: plus1 = 1, minus1 = 0, PI = 45, DB = 0
N0.C2.D1.R0.S03: RcvEn: plus1 = 1, minus1 = 0, PI = 19, DB = 0
N2.C1: StoreJckWorstRank: final value: worst rank = 0
N4.C3.D0.R0.S16: Rcv En Fine Value = 314
N6.C2.D1.R0.S06: RcvEn: plus1 = 1, minus1 = 0, PI = 19, DB = 0
N0.C2.D1.R0.S04: RcvEn: plus1 = 1, minus1 = 0, PI = 21, DB = 0
N2: RunTrainStep: Final status = 0
N4.C3.D0.R0.S17: Rcv En Fine Value = 354
N6.C2.D1.R0.S07: RcvEn: plus1 = 1, minus1 = 0, PI = 36, DB = 0
N0.C2.D1.R0.S05: RcvEn: plus1 = 1, minus1 = 0, PI = 33, DB = 0

END - Basic Receive Enable Training    Time         62201 ms
N4.C3.D0.R0: Starting preamble search lower nibbles
N6.C2.D1.R0.S08: RcvEn: plus1 = 1, minus1 = 0, PI = 19, DB = 0
N0.C2.D1.R0.S06: RcvEn: plus1 = 1, minus1 = 0, PI = 07, DB = 1
N2.C0.S00: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  6
N4.C3.D0.R0.S00: PI = 061, PtrOffset = 004
N6.C2.D1.R0.S09: RcvEn: plus1 = 1, minus1 = 0, PI = 40, DB = 0
N0.C2.D1.R0.S07: RcvEn: plus1 = 1, minus1 = 0, PI = 25, DB = 0
N2.C0.S01: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  6
N4.C3.D0.R0.S01: PI = 042, PtrOffset = 004
N6.C2.D1.R0.S10: RcvEn: plus1 = 1, minus1 = 0, PI = 19, DB = 0
N0.C2.D1.R0.S08: RcvEn: plus1 = 1, minus1 = 0, PI = 09, DB = 1
N2.C0.S02: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  5
N4.C3.D0.R0.S02: PI = 013, PtrOffset = 004
N6.C2.D1.R0.S11: RcvEn: plus1 = 1, minus1 = 0, PI = 51, DB = 1
N0.C2.D1.R0.S09: RcvEn: plus1 = 1, minus1 = 0, PI = 29, DB = 0
N2.C0.S03: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  5
N4.C3.D0.R0.S03: PI = 055, PtrOffset = 005
N6.C2.D1.R0.S12: RcvEn: plus1 = 1, minus1 = 0, PI = 33, DB = 0
N0.C2.D1.R0.S10: RcvEn: plus1 = 1, minus1 = 0, PI = 05, DB = 1
N2.C0.S04: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  5
N4.C3.D0.R0.S04: PI = 050, PtrOffset = 005
N6.C2.D1.R0.S13: RcvEn: plus1 = 1, minus1 = 0, PI = 32, DB = 0
N0.C2.D1.R0.S11: RcvEn: plus1 = 1, minus1 = 0, PI = 39, DB = 0
N2.C0.S05: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  5
N4.C3.D0.R0.S05: PI = 009, PtrOffset = 004
N6.C2.D1.R0.S14: RcvEn: plus1 = 1, minus1 = 0, PI = 42, DB = 0
N0.C2.D1.R0.S12: RcvEn: plus1 = 1, minus1 = 0, PI = 18, DB = 0
N2.C0.S06: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  6
N4.C3.D0.R0.S06: PI = 034, PtrOffset = 004
N6.C2.D1.R0.S15: RcvEn: plus1 = 1, minus1 = 0, PI = 19, DB = 0
N0.C2.D1.R0.S13: RcvEn: plus1 = 1, minus1 = 0, PI = 22, DB = 0
N2.C0.S07: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  6
N4.C3.D0.R0.S07: PI = 056, PtrOffset = 004
N6.C2.D1.R0.S16: RcvEn: plus1 = 1, minus1 = 0, PI = 37, DB = 0
N0.C2.D1.R0.S14: RcvEn: plus1 = 1, minus1 = 0, PI = 34, DB = 0
N2.C0.S08: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  5
N4.C3.D0.R0.S08: PI = 033, PtrOffset = 005
N6.C2.D1.R0.S17: RcvEn: plus1 = 1, minus1 = 0, PI = 20, DB = 0
N0.C2.D1.R0.S15: RcvEn: plus1 = 1, minus1 = 0, PI = 07, DB = 1
N2.C1.S00: SuppressionWindowAdjustmentRd: latency =  9, rdptroffset =  5
N4.C3.D0.R0.S00: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N6.C2.D1.R1.S00: RcvEn: plus1 = 1, minus1 = 0, PI = 42, DB = 0
N0.C2.D1.R0.S16: RcvEn: plus1 = 1, minus1 = 0, PI = 25, DB = 0
N2.C1.S01: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  6
N4.C3.D0.R0.S01: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N6.C2.D1.R1.S01: RcvEn: plus1 = 1, minus1 = 0, PI = 16, DB = 0
N0.C2.D1.R0.S17: RcvEn: plus1 = 1, minus1 = 0, PI = 06, DB = 1
N2.C1.S02: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  6
N4.C3.D0.R0.S02: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N6.C2.D1.R1.S02: RcvEn: plus1 = 1, minus1 = 0, PI = 53, DB = 1
N0.C2.D1.R1.S00: RcvEn: plus1 = 1, minus1 = 0, PI = 30, DB = 0
N2.C1.S03: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  6
N4.C3.D0.R0.S03: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N6.C2.D1.R1.S03: RcvEn: plus1 = 1, minus1 = 0, PI = 34, DB = 0
N0.C2.D1.R1.S01: RcvEn: plus1 = 1, minus1 = 0, PI = 07, DB = 1
N2.C1.S04: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  6
N4.C3.D0.R0.S04: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N6.C2.D1.R1.S04: RcvEn: plus1 = 1, minus1 = 0, PI = 33, DB = 0
N0.C2.D1.R1.S02: RcvEn: plus1 = 1, minus1 = 0, PI = 40, DB = 0
N2.C1.S05: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  6
N4.C3.D0.R0.S05: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N6.C2.D1.R1.S05: RcvEn: plus1 = 1, minus1 = 0, PI = 45, DB = 0
N0.C2.D1.R1.S03: RcvEn: plus1 = 1, minus1 = 0, PI = 19, DB = 0
N2.C1.S06: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  6
N4.C3.D0.R0.S06: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N6.C2.D1.R1.S06: RcvEn: plus1 = 1, minus1 = 0, PI = 19, DB = 0
N0.C2.D1.R1.S04: RcvEn: plus1 = 1, minus1 = 0, PI = 21, DB = 0
N2.C1.S07: SuppressionWindowAdjustmentRd: latency =  9, rdptroffset =  5
N4.C3.D0.R0.S07: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N6.C2.D1.R1.S07: RcvEn: plus1 = 1, minus1 = 0, PI = 36, DB = 0
N0.C2.D1.R1.S05: RcvEn: plus1 = 1, minus1 = 0, PI = 33, DB = 0
N2.C1.S08: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  5
N4.C3.D0.R0.S08: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N6.C2.D1.R1.S08: RcvEn: plus1 = 1, minus1 = 0, PI = 19, DB = 0
N0.C2.D1.R1.S06: RcvEn: plus1 = 1, minus1 = 0, PI = 07, DB = 1
N2.C2.S00: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  6
N4.C3.D0.R0.S00: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N6.C2.D1.R1.S09: RcvEn: plus1 = 1, minus1 = 0, PI = 40, DB = 0
N0.C2.D1.R1.S07: RcvEn: plus1 = 1, minus1 = 0, PI = 25, DB = 0
N2.C2.S01: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  6
N4.C3.D0.R0.S01: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N6.C2.D1.R1.S10: RcvEn: plus1 = 1, minus1 = 0, PI = 19, DB = 0
N0.C2.D1.R1.S08: RcvEn: plus1 = 1, minus1 = 0, PI = 09, DB = 1
N2.C2.S02: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  5
N4.C3.D0.R0.S02: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N6.C2.D1.R1.S11: RcvEn: plus1 = 1, minus1 = 0, PI = 51, DB = 1
N0.C2.D1.R1.S09: RcvEn: plus1 = 1, minus1 = 0, PI = 29, DB = 0
N2.C2.S03: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  5
N4.C3.D0.R0.S03: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N6.C2.D1.R1.S12: RcvEn: plus1 = 1, minus1 = 0, PI = 33, DB = 0
N0.C2.D1.R1.S10: RcvEn: plus1 = 1, minus1 = 0, PI = 05, DB = 1
N2.C2.S04: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  5
N4.C3.D0.R0.S04: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N6.C2.D1.R1.S13: RcvEn: plus1 = 1, minus1 = 0, PI = 32, DB = 0
N0.C2.D1.R1.S11: RcvEn: plus1 = 1, minus1 = 0, PI = 39, DB = 0
N2.C2.S05: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  5
N4.C3.D0.R0.S05: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N6.C2.D1.R1.S14: RcvEn: plus1 = 1, minus1 = 0, PI = 42, DB = 0
N0.C2.D1.R1.S12: RcvEn: plus1 = 1, minus1 = 0, PI = 18, DB = 0
N2.C2.S06: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  6
N4.C3.D0.R0.S06: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N6.C2.D1.R1.S15: RcvEn: plus1 = 1, minus1 = 0, PI = 19, DB = 0
N0.C2.D1.R1.S13: RcvEn: plus1 = 1, minus1 = 0, PI = 22, DB = 0
N2.C2.S07: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  6
N4.C3.D0.R0.S07: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N6.C2.D1.R1.S16: RcvEn: plus1 = 1, minus1 = 0, PI = 37, DB = 0
N0.C2.D1.R1.S14: RcvEn: plus1 = 1, minus1 = 0, PI = 34, DB = 0
N2.C2.S08: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  5
N4.C3.D0.R0.S08: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N6.C2.D1.R1.S17: RcvEn: plus1 = 1, minus1 = 0, PI = 20, DB = 0
N0.C2.D1.R1.S15: RcvEn: plus1 = 1, minus1 = 0, PI = 07, DB = 1
N2.C3.S00: SuppressionWindowAdjustmentRd: latency =  9, rdptroffset =  5
N4.C3.D0.R0.S00: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
STOP_DATA_REC_EN
N0.C2.D1.R1.S16: RcvEn: plus1 = 1, minus1 = 0, PI = 25, DB = 0
N2.C3.S01: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  6
N4.C3.D0.R0.S01: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N6.C3.D0.R0: RcvEnFine: Initial RdCmd2RcvEnLatency = 10, Initial RdPtrOffsetRcvEn = 4
N0.C2.D1.R1.S17: RcvEn: plus1 = 1, minus1 = 0, PI = 06, DB = 1
N2.C3.S02: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  6
N4.C3.D0.R0.S02: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N6.C3.D0.R0.S00: Rcv En Fine Value = 323
STOP_DATA_REC_EN
N2.C3.S03: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  6
N4.C3.D0.R0.S03: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N6.C3.D0.R0.S01: Rcv En Fine Value = 304
N0.C3.D0.R0: RcvEnFine: Initial RdCmd2RcvEnLatency = 10, Initial RdPtrOffsetRcvEn = 4
N2.C3.S04: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  6
N4.C3.D0.R0.S04: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N6.C3.D0.R0.S02: Rcv En Fine Value = 277
N0.C3.D0.R0.S00: Rcv En Fine Value = 317
N2.C3.S05: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  6
N4.C3.D0.R0.S05: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N6.C3.D0.R0.S03: Rcv En Fine Value = 381
N0.C3.D0.R0.S01: Rcv En Fine Value = 300
N2.C3.S06: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  6
N4.C3.D0.R0.S06: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N6.C3.D0.R0.S04: Rcv En Fine Value = 372
N0.C3.D0.R0.S02: Rcv En Fine Value = 271
N2.C3.S07: SuppressionWindowAdjustmentRd: latency =  9, rdptroffset =  5
N4.C3.D0.R0.S07: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N6.C3.D0.R0.S05: Rcv En Fine Value = 270
N0.C3.D0.R0.S03: Rcv En Fine Value = 375
N2.C3.S08: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  5
N4.C3.D0.R0.S08: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N6.C3.D0.R0.S06: Rcv En Fine Value = 295
N0.C3.D0.R0.S04: Rcv En Fine Value = 372

START - Basic Write Level Training
N4.C3.D0.R0.S00: Preamble found at Latency = 008
N6.C3.D0.R0.S07: Rcv En Fine Value = 316
N0.C3.D0.R0.S05: Rcv En Fine Value = 270
N2: START WRITE LEVEL:
N4.C3.D0.R0.S01: Preamble found at Latency = 008
N6.C3.D0.R0.S08: Rcv En Fine Value = 362
N0.C3.D0.R0.S06: Rcv En Fine Value = 290
N2.C0.D0.R0: ODT Override: 0x5
N4.C3.D0.R0.S02: Preamble found at Latency = 008
N6.C3.D0.R0.S09: Rcv En Fine Value = 321
N0.C3.D0.R0.S07: Rcv En Fine Value = 315
N2.C0.D0.R0.S00: Write Level Fine Value = 499
N4.C3.D0.R0.S05: Preamble found at Latency = 008
N6.C3.D0.R0.S10: Rcv En Fine Value = 302
N0.C3.D0.R0.S08: Rcv En Fine Value = 357
N2.C0.D0.R0.S01: Write Level Fine Value = 477
N4.C3.D0.R0.S06: Preamble found at Latency = 008
N6.C3.D0.R0.S11: Rcv En Fine Value = 275
N0.C3.D0.R0.S09: Rcv En Fine Value = 319
N2.C0.D0.R0.S02: Write Level Fine Value = 469
N4.C3.D0.R0.S07: Preamble found at Latency = 008
N6.C3.D0.R0.S12: Rcv En Fine Value = 378
N0.C3.D0.R0.S10: Rcv En Fine Value = 300
N2.C0.D0.R0.S03: Write Level Fine Value = 451
N4.C3.D0.R0.S00: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N6.C3.D0.R0.S13: Rcv En Fine Value = 374
N0.C3.D0.R0.S11: Rcv En Fine Value = 272
N2.C0.D0.R0.S04: Write Level Fine Value = 418
N4.C3.D0.R0.S01: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N6.C3.D0.R0.S14: Rcv En Fine Value = 276
N0.C3.D0.R0.S12: Rcv En Fine Value = 377
N2.C0.D0.R0.S05: Write Level Fine Value = 435
N4.C3.D0.R0.S02: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N6.C3.D0.R0.S15: Rcv En Fine Value = 297
N0.C3.D0.R0.S13: Rcv En Fine Value = 371
N2.C0.D0.R0.S06: Write Level Fine Value = 442
N4.C3.D0.R0.S03: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N6.C3.D0.R0.S16: Rcv En Fine Value = 317
N0.C3.D0.R0.S14: Rcv En Fine Value = 270
N2.C0.D0.R0.S07: Write Level Fine Value = 453
N4.C3.D0.R0.S04: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N6.C3.D0.R0.S17: Rcv En Fine Value = 362
N0.C3.D0.R0.S15: Rcv En Fine Value = 293
N2.C0.D0.R0.S08: Write Level Fine Value = 431
N4.C3.D0.R0.S05: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N6.C3.D0.R0: Starting preamble search lower nibbles
N0.C3.D0.R0.S16: Rcv En Fine Value = 317
N2.C0.D0.R0.S09: Write Level Fine Value = 503
N4.C3.D0.R0.S06: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N6.C3.D0.R0.S00: PI = 003, PtrOffset = 005
N0.C3.D0.R0.S17: Rcv En Fine Value = 354
N2.C0.D0.R0.S10: Write Level Fine Value = 478
N4.C3.D0.R0.S07: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N6.C3.D0.R0.S01: PI = 048, PtrOffset = 004
N0.C3.D0.R0: Starting preamble search lower nibbles
N2.C0.D0.R0.S11: Write Level Fine Value = 469
N4.C3.D0.R0.S08: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N6.C3.D0.R0.S02: PI = 021, PtrOffset = 004
N0.C3.D0.R0.S00: PI = 061, PtrOffset = 004
N2.C0.D0.R0.S12: Write Level Fine Value = 452
N4.C3.D0.R0.S03: Preamble found at Latency = 007
N6.C3.D0.R0.S03: PI = 061, PtrOffset = 005
N0.C3.D0.R0.S01: PI = 044, PtrOffset = 004
N2.C0.D0.R0.S13: Write Level Fine Value = 420
N4.C3.D0.R0.S04: Preamble found at Latency = 007
N6.C3.D0.R0.S04: PI = 052, PtrOffset = 005
N0.C3.D0.R0.S02: PI = 015, PtrOffset = 004
N2.C0.D0.R0.S14: Write Level Fine Value = 436
N4.C3.D0.R0.S08: Preamble found at Latency = 007
N6.C3.D0.R0.S05: PI = 014, PtrOffset = 004
N0.C3.D0.R0.S03: PI = 055, PtrOffset = 005
N2.C0.D0.R0.S15: Write Level Fine Value = 439
N4.C3.D0.R0.S00: Total Receive Enable Delay = 1373
N6.C3.D0.R0.S06: PI = 039, PtrOffset = 004
N0.C3.D0.R0.S04: PI = 052, PtrOffset = 005
N2.C0.D0.R0.S16: Write Level Fine Value = 453
N4.C3.D0.R0.S01: Total Receive Enable Delay = 1354
N6.C3.D0.R0.S07: PI = 060, PtrOffset = 004
N0.C3.D0.R0.S05: PI = 014, PtrOffset = 004
N2.C0.D0.R0.S17: Write Level Fine Value = 431
N4.C3.D0.R0.S02: Total Receive Enable Delay = 1325
N6.C3.D0.R0.S08: PI = 042, PtrOffset = 005
N0.C3.D0.R0.S06: PI = 034, PtrOffset = 004
N2.C0.D0.R1: ODT Override: 0x6
N4.C3.D0.R0.S03: Total Receive Enable Delay = 1303
N6.C3.D0.R0.S00: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N0.C3.D0.R0.S07: PI = 059, PtrOffset = 004
N2.C0.D0.R1.S00: Write Level Fine Value = 495
N4.C3.D0.R0.S04: Total Receive Enable Delay = 1298
N6.C3.D0.R0.S01: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N0.C3.D0.R0.S08: PI = 037, PtrOffset = 005
N2.C0.D0.R1.S01: Write Level Fine Value = 475
N4.C3.D0.R0.S05: Total Receive Enable Delay = 1321
N6.C3.D0.R0.S02: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N0.C3.D0.R0.S00: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N2.C0.D0.R1.S02: Write Level Fine Value = 461
N4.C3.D0.R0.S06: Total Receive Enable Delay = 1346
N6.C3.D0.R0.S03: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N0.C3.D0.R0.S01: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N2.C0.D0.R1.S03: Write Level Fine Value = 444
N4.C3.D0.R0.S07: Total Receive Enable Delay = 1368
N6.C3.D0.R0.S04: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N0.C3.D0.R0.S02: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N2.C0.D0.R1.S04: Write Level Fine Value = 411
N4.C3.D0.R0.S08: Total Receive Enable Delay = 1281
N6.C3.D0.R0.S05: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N0.C3.D0.R0.S03: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N2.C0.D0.R1.S05: Write Level Fine Value = 428
N4.C3.D0.R0: Starting preamble search upper nibbles
N6.C3.D0.R0.S06: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N0.C3.D0.R0.S04: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N2.C0.D0.R1.S06: Write Level Fine Value = 434
N4.C3.D0.R0.S09: PI = 060, PtrOffset = 004
N6.C3.D0.R0.S07: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N0.C3.D0.R0.S05: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N2.C0.D0.R1.S07: Write Level Fine Value = 448
N4.C3.D0.R0.S10: PI = 042, PtrOffset = 004
N6.C3.D0.R0.S08: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N0.C3.D0.R0.S06: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N2.C0.D0.R1.S08: Write Level Fine Value = 422
N4.C3.D0.R0.S11: PI = 014, PtrOffset = 004
N6.C3.D0.R0.S00: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N0.C3.D0.R0.S07: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N2.C0.D0.R1.S09: Write Level Fine Value = 490
N4.C3.D0.R0.S12: PI = 056, PtrOffset = 005
N6.C3.D0.R0.S01: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N0.C3.D0.R0.S08: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N2.C0.D0.R1.S10: Write Level Fine Value = 473
N4.C3.D0.R0.S13: PI = 049, PtrOffset = 005
N6.C3.D0.R0.S02: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N0.C3.D0.R0.S00: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N2.C0.D0.R1.S11: Write Level Fine Value = 463
N4.C3.D0.R0.S14: PI = 010, PtrOffset = 004
N6.C3.D0.R0.S03: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N0.C3.D0.R0.S01: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N2.C0.D0.R1.S12: Write Level Fine Value = 448
N4.C3.D0.R0.S15: PI = 034, PtrOffset = 004
N6.C3.D0.R0.S04: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N0.C3.D0.R0.S02: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N2.C0.D0.R1.S13: Write Level Fine Value = 411
N4.C3.D0.R0.S16: PI = 058, PtrOffset = 004
N6.C3.D0.R0.S05: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N0.C3.D0.R0.S03: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N2.C0.D0.R1.S14: Write Level Fine Value = 429
N4.C3.D0.R0.S17: PI = 034, PtrOffset = 005
N6.C3.D0.R0.S06: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N0.C3.D0.R0.S04: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N2.C0.D0.R1.S15: Write Level Fine Value = 434
N4.C3.D0.R0.S09: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N6.C3.D0.R0.S07: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N0.C3.D0.R0.S05: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N2.C0.D0.R1.S16: Write Level Fine Value = 449
N4.C3.D0.R0.S10: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N6.C3.D0.R0.S08: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N0.C3.D0.R0.S06: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N2.C0.D0.R1.S17: Write Level Fine Value = 423
N4.C3.D0.R0.S11: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N6.C3.D0.R0.S00: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N0.C3.D0.R0.S07: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N2.C0.D1.R0: ODT Override: 0x5
N4.C3.D0.R0.S12: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N6.C3.D0.R0.S01: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N0.C3.D0.R0.S08: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N2.C0.D1.R0.S00: Write Level Fine Value = 504
N4.C3.D0.R0.S13: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N6.C3.D0.R0.S02: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N0.C3.D0.R0.S00: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N2.C0.D1.R0.S01: Write Level Fine Value = 486
N4.C3.D0.R0.S14: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N6.C3.D0.R0.S03: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N0.C3.D0.R0.S01: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N2.C0.D1.R0.S02: Write Level Fine Value = 474
N4.C3.D0.R0.S15: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N6.C3.D0.R0.S04: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N0.C3.D0.R0.S02: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N2.C0.D1.R0.S03: Write Level Fine Value = 458
N4.C3.D0.R0.S16: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N6.C3.D0.R0.S05: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N0.C3.D0.R0.S03: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N2.C0.D1.R0.S04: Write Level Fine Value = 425
N4.C3.D0.R0.S17: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N6.C3.D0.R0.S06: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N0.C3.D0.R0.S04: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N2.C0.D1.R0.S05: Write Level Fine Value = 443
N4.C3.D0.R0.S09: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N6.C3.D0.R0.S07: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N0.C3.D0.R0.S05: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N2.C0.D1.R0.S06: Write Level Fine Value = 445
N4.C3.D0.R0.S10: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N6.C3.D0.R0.S08: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N0.C3.D0.R0.S06: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N2.C0.D1.R0.S07: Write Level Fine Value = 462
N4.C3.D0.R0.S11: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N6.C3.D0.R0.S00: Preamble found at Latency = 008
N0.C3.D0.R0.S07: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N2.C0.D1.R0.S08: Write Level Fine Value = 432
N4.C3.D0.R0.S12: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N6.C3.D0.R0.S01: Preamble found at Latency = 008
N0.C3.D0.R0.S08: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N2.C0.D1.R0.S09: Write Level Fine Value = 505
N4.C3.D0.R0.S13: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N6.C3.D0.R0.S02: Preamble found at Latency = 008
N0.C3.D0.R0.S00: Preamble found at Latency = 008
N2.C0.D1.R0.S10: Write Level Fine Value = 485
N4.C3.D0.R0.S14: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N6.C3.D0.R0.S05: Preamble found at Latency = 008
N0.C3.D0.R0.S01: Preamble found at Latency = 008
N2.C0.D1.R0.S11: Write Level Fine Value = 477
N4.C3.D0.R0.S15: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N6.C3.D0.R0.S06: Preamble found at Latency = 008
N0.C3.D0.R0.S02: Preamble found at Latency = 008
N2.C0.D1.R0.S12: Write Level Fine Value = 461
N4.C3.D0.R0.S16: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N6.C3.D0.R0.S07: Preamble found at Latency = 008
N0.C3.D0.R0.S05: Preamble found at Latency = 008
N2.C0.D1.R0.S13: Write Level Fine Value = 426
N4.C3.D0.R0.S17: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N6.C3.D0.R0.S00: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N0.C3.D0.R0.S06: Preamble found at Latency = 008
N2.C0.D1.R0.S14: Write Level Fine Value = 444
N4.C3.D0.R0.S09: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N6.C3.D0.R0.S01: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N0.C3.D0.R0.S07: Preamble found at Latency = 008
N2.C0.D1.R0.S15: Write Level Fine Value = 446
N4.C3.D0.R0.S10: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N6.C3.D0.R0.S02: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N0.C3.D0.R0.S00: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N2.C0.D1.R0.S16: Write Level Fine Value = 462
N4.C3.D0.R0.S11: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N6.C3.D0.R0.S03: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N0.C3.D0.R0.S01: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N2.C0.D1.R0.S17: Write Level Fine Value = 434
N4.C3.D0.R0.S12: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N6.C3.D0.R0.S04: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N0.C3.D0.R0.S02: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N2.C0.D1.R1: ODT Override: 0x9
N4.C3.D0.R0.S13: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N6.C3.D0.R0.S05: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N0.C3.D0.R0.S03: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N2.C0.D1.R1.S00: Write Level Fine Value = 499
N4.C3.D0.R0.S14: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N6.C3.D0.R0.S06: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N0.C3.D0.R0.S04: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N2.C0.D1.R1.S01: Write Level Fine Value = 484
N4.C3.D0.R0.S15: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N6.C3.D0.R0.S07: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N0.C3.D0.R0.S05: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N2.C0.D1.R1.S02: Write Level Fine Value = 470
N4.C3.D0.R0.S16: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N6.C3.D0.R0.S08: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N0.C3.D0.R0.S06: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N2.C0.D1.R1.S03: Write Level Fine Value = 454
N4.C3.D0.R0.S17: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N6.C3.D0.R0.S03: Preamble found at Latency = 007
N0.C3.D0.R0.S07: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N2.C0.D1.R1.S04: Write Level Fine Value = 420
N4.C3.D0.R0.S09: Preamble found at Latency = 008
N6.C3.D0.R0.S04: Preamble found at Latency = 007
N0.C3.D0.R0.S08: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N2.C0.D1.R1.S05: Write Level Fine Value = 439
N4.C3.D0.R0.S10: Preamble found at Latency = 008
N6.C3.D0.R0.S08: Preamble found at Latency = 007
N0.C3.D0.R0.S03: Preamble found at Latency = 007
N2.C0.D1.R1.S06: Write Level Fine Value = 443
N4.C3.D0.R0.S11: Preamble found at Latency = 008
N6.C3.D0.R0.S00: Total Receive Enable Delay = 1379
N0.C3.D0.R0.S04: Preamble found at Latency = 007
N2.C0.D1.R1.S07: Write Level Fine Value = 460
N4.C3.D0.R0.S14: Preamble found at Latency = 008
N6.C3.D0.R0.S01: Total Receive Enable Delay = 1360
N0.C3.D0.R0.S08: Preamble found at Latency = 007
N2.C0.D1.R1.S08: Write Level Fine Value = 429
N4.C3.D0.R0.S15: Preamble found at Latency = 008
N6.C3.D0.R0.S02: Total Receive Enable Delay = 1333
N0.C3.D0.R0.S00: Total Receive Enable Delay = 1373
N2.C0.D1.R1.S09: Write Level Fine Value = 499
N4.C3.D0.R0.S16: Preamble found at Latency = 008
N6.C3.D0.R0.S03: Total Receive Enable Delay = 1309
N0.C3.D0.R0.S01: Total Receive Enable Delay = 1356
N2.C0.D1.R1.S10: Write Level Fine Value = 484
N4.C3.D0.R0.S09: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N6.C3.D0.R0.S04: Total Receive Enable Delay = 1300
N0.C3.D0.R0.S02: Total Receive Enable Delay = 1327
N2.C0.D1.R1.S11: Write Level Fine Value = 472
N4.C3.D0.R0.S10: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N6.C3.D0.R0.S05: Total Receive Enable Delay = 1326
N0.C3.D0.R0.S03: Total Receive Enable Delay = 1303
N2.C0.D1.R1.S12: Write Level Fine Value = 459
N4.C3.D0.R0.S11: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N6.C3.D0.R0.S06: Total Receive Enable Delay = 1351
N0.C3.D0.R0.S04: Total Receive Enable Delay = 1300
N2.C0.D1.R1.S13: Write Level Fine Value = 421
N4.C3.D0.R0.S12: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N6.C3.D0.R0.S07: Total Receive Enable Delay = 1372
N0.C3.D0.R0.S05: Total Receive Enable Delay = 1326
N2.C0.D1.R1.S14: Write Level Fine Value = 438
N4.C3.D0.R0.S13: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N6.C3.D0.R0.S08: Total Receive Enable Delay = 1290
N0.C3.D0.R0.S06: Total Receive Enable Delay = 1346
N2.C0.D1.R1.S15: Write Level Fine Value = 443
N4.C3.D0.R0.S14: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N6.C3.D0.R0: Starting preamble search upper nibbles
N0.C3.D0.R0.S07: Total Receive Enable Delay = 1371
N2.C0.D1.R1.S16: Write Level Fine Value = 459
N4.C3.D0.R0.S15: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N6.C3.D0.R0.S09: PI = 001, PtrOffset = 005
N0.C3.D0.R0.S08: Total Receive Enable Delay = 1285
N2.C0.D1.R1.S17: Write Level Fine Value = 429
N4.C3.D0.R0.S16: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N6.C3.D0.R0.S10: PI = 046, PtrOffset = 004
N0.C3.D0.R0: Starting preamble search upper nibbles
N2.C1.D0.R0: ODT Override: 0x5
N4.C3.D0.R0.S17: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N6.C3.D0.R0.S11: PI = 019, PtrOffset = 004
N0.C3.D0.R0.S09: PI = 063, PtrOffset = 004
N2.C1.D0.R0.S00: Write Level Fine Value = 498
N4.C3.D0.R0.S12: Preamble found at Latency = 007
N6.C3.D0.R0.S12: PI = 058, PtrOffset = 005
N0.C3.D0.R0.S10: PI = 044, PtrOffset = 004
N2.C1.D0.R0.S01: Write Level Fine Value = 480
N4.C3.D0.R0.S13: Preamble found at Latency = 007
N6.C3.D0.R0.S13: PI = 054, PtrOffset = 005
N0.C3.D0.R0.S11: PI = 016, PtrOffset = 004
N2.C1.D0.R0.S02: Write Level Fine Value = 475
N4.C3.D0.R0.S17: Preamble found at Latency = 007
N6.C3.D0.R0.S14: PI = 020, PtrOffset = 004
N0.C3.D0.R0.S12: PI = 057, PtrOffset = 005
N2.C1.D0.R0.S03: Write Level Fine Value = 456
N4.C3.D0.R0: Preamble found for all upper nibbles, adjusting Pi, Offset to center into preamble
N6.C3.D0.R0.S15: PI = 041, PtrOffset = 004
N0.C3.D0.R0.S13: PI = 051, PtrOffset = 005
N2.C1.D0.R0.S04: Write Level Fine Value = 424
N4.C3.D0.R0.S09: Total Receive Enable Delay = 1372
N6.C3.D0.R0.S16: PI = 061, PtrOffset = 004
N0.C3.D0.R0.S14: PI = 014, PtrOffset = 004
N2.C1.D0.R0.S05: Write Level Fine Value = 439
N4.C3.D0.R0.S10: Total Receive Enable Delay = 1354
N6.C3.D0.R0.S17: PI = 042, PtrOffset = 005
N0.C3.D0.R0.S15: PI = 037, PtrOffset = 004
N2.C1.D0.R0.S06: Write Level Fine Value = 451
N4.C3.D0.R0.S11: Total Receive Enable Delay = 1326
N6.C3.D0.R0.S09: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N0.C3.D0.R0.S16: PI = 061, PtrOffset = 004
N2.C1.D0.R0.S07: Write Level Fine Value = 467
N4.C3.D0.R0.S12: Total Receive Enable Delay = 1304
N6.C3.D0.R0.S10: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N0.C3.D0.R0.S17: PI = 034, PtrOffset = 005
N2.C1.D0.R0.S08: Write Level Fine Value = 439
N4.C3.D0.R0.S13: Total Receive Enable Delay = 1297
N6.C3.D0.R0.S11: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N0.C3.D0.R0.S09: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N2.C1.D0.R0.S09: Write Level Fine Value = 498
N4.C3.D0.R0.S14: Total Receive Enable Delay = 1322
N6.C3.D0.R0.S12: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N0.C3.D0.R0.S10: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N2.C1.D0.R0.S10: Write Level Fine Value = 480
N4.C3.D0.R0.S15: Total Receive Enable Delay = 1346
N6.C3.D0.R0.S13: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N0.C3.D0.R0.S11: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N2.C1.D0.R0.S11: Write Level Fine Value = 474
N4.C3.D0.R0.S16: Total Receive Enable Delay = 1370
N6.C3.D0.R0.S14: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N0.C3.D0.R0.S12: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N2.C1.D0.R0.S12: Write Level Fine Value = 456
N4.C3.D0.R0.S17: Total Receive Enable Delay = 1282
N6.C3.D0.R0.S15: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N0.C3.D0.R0.S13: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N2.C1.D0.R0.S13: Write Level Fine Value = 424
N4.C3.D0.R1: RcvEnFine: Initial RdCmd2RcvEnLatency = 10, Initial RdPtrOffsetRcvEn = 4
N6.C3.D0.R0.S16: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N0.C3.D0.R0.S14: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N2.C1.D0.R0.S14: Write Level Fine Value = 438
N4.C3.D0.R1.S00: Rcv En Fine Value = 317
N6.C3.D0.R0.S17: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N0.C3.D0.R0.S15: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N2.C1.D0.R0.S15: Write Level Fine Value = 451
N4.C3.D0.R1.S01: Rcv En Fine Value = 297
N6.C3.D0.R0.S09: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N0.C3.D0.R0.S16: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N2.C1.D0.R0.S16: Write Level Fine Value = 470
N4.C3.D0.R1.S02: Rcv En Fine Value = 267
N6.C3.D0.R0.S10: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N0.C3.D0.R0.S17: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N2.C1.D0.R0.S17: Write Level Fine Value = 438
N4.C3.D0.R1.S03: Rcv En Fine Value = 374
N6.C3.D0.R0.S11: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N0.C3.D0.R0.S09: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N2.C1.D0.R1: ODT Override: 0x6
N4.C3.D0.R1.S04: Rcv En Fine Value = 367
N6.C3.D0.R0.S12: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N0.C3.D0.R0.S10: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N2.C1.D0.R1.S00: Write Level Fine Value = 490
N4.C3.D0.R1.S05: Rcv En Fine Value = 265
N6.C3.D0.R0.S13: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N0.C3.D0.R0.S11: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N2.C1.D0.R1.S01: Write Level Fine Value = 473
N4.C3.D0.R1.S06: Rcv En Fine Value = 289
N6.C3.D0.R0.S14: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N0.C3.D0.R0.S12: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N2.C1.D0.R1.S02: Write Level Fine Value = 467
N4.C3.D0.R1.S07: Rcv En Fine Value = 310
N6.C3.D0.R0.S15: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N0.C3.D0.R0.S13: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N2.C1.D0.R1.S03: Write Level Fine Value = 450
N4.C3.D0.R1.S08: Rcv En Fine Value = 352
N6.C3.D0.R0.S16: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N0.C3.D0.R0.S14: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N2.C1.D0.R1.S04: Write Level Fine Value = 418
N4.C3.D0.R1.S09: Rcv En Fine Value = 317
N6.C3.D0.R0.S17: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N0.C3.D0.R0.S15: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N2.C1.D0.R1.S05: Write Level Fine Value = 432
N4.C3.D0.R1.S10: Rcv En Fine Value = 297
N6.C3.D0.R0.S09: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N0.C3.D0.R0.S16: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N2.C1.D0.R1.S06: Write Level Fine Value = 443
N4.C3.D0.R1.S11: Rcv En Fine Value = 269
N6.C3.D0.R0.S10: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N0.C3.D0.R0.S17: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N2.C1.D0.R1.S07: Write Level Fine Value = 461
N4.C3.D0.R1.S12: Rcv En Fine Value = 376
N6.C3.D0.R0.S11: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N0.C3.D0.R0.S09: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N2.C1.D0.R1.S08: Write Level Fine Value = 431
N4.C3.D0.R1.S13: Rcv En Fine Value = 368
N6.C3.D0.R0.S12: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N0.C3.D0.R0.S10: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N2.C1.D0.R1.S09: Write Level Fine Value = 489
N4.C3.D0.R1.S14: Rcv En Fine Value = 267
N6.C3.D0.R0.S13: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N0.C3.D0.R0.S11: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N2.C1.D0.R1.S10: Write Level Fine Value = 473
N4.C3.D0.R1.S15: Rcv En Fine Value = 292
N6.C3.D0.R0.S14: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N0.C3.D0.R0.S12: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N2.C1.D0.R1.S11: Write Level Fine Value = 466
N4.C3.D0.R1.S16: Rcv En Fine Value = 314
N6.C3.D0.R0.S15: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N0.C3.D0.R0.S13: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N2.C1.D0.R1.S12: Write Level Fine Value = 451
N4.C3.D0.R1.S17: Rcv En Fine Value = 355
N6.C3.D0.R0.S16: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N0.C3.D0.R0.S14: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N2.C1.D0.R1.S13: Write Level Fine Value = 417
N4.C3.D0.R1: Starting preamble search lower nibbles
N6.C3.D0.R0.S17: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N0.C3.D0.R0.S15: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N2.C1.D0.R1.S14: Write Level Fine Value = 432
N4.C3.D0.R1.S00: PI = 061, PtrOffset = 004
N6.C3.D0.R0.S09: Preamble found at Latency = 008
N0.C3.D0.R0.S16: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N2.C1.D0.R1.S15: Write Level Fine Value = 444
N4.C3.D0.R1.S01: PI = 041, PtrOffset = 004
N6.C3.D0.R0.S10: Preamble found at Latency = 008
N0.C3.D0.R0.S17: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N2.C1.D0.R1.S16: Write Level Fine Value = 463
N4.C3.D0.R1.S02: PI = 011, PtrOffset = 004
N6.C3.D0.R0.S11: Preamble found at Latency = 008
N0.C3.D0.R0.S09: Preamble found at Latency = 008
N2.C1.D0.R1.S17: Write Level Fine Value = 432
N4.C3.D0.R1.S03: PI = 054, PtrOffset = 005
N6.C3.D0.R0.S14: Preamble found at Latency = 008
N0.C3.D0.R0.S10: Preamble found at Latency = 008
N2.C1.D1.R0: ODT Override: 0x5
N4.C3.D0.R1.S04: PI = 047, PtrOffset = 005
N6.C3.D0.R0.S15: Preamble found at Latency = 008
N0.C3.D0.R0.S11: Preamble found at Latency = 008
N2.C1.D1.R0.S00: Write Level Fine Value = 502
N4.C3.D0.R1.S05: PI = 009, PtrOffset = 004
N6.C3.D0.R0.S16: Preamble found at Latency = 008
N0.C3.D0.R0.S14: Preamble found at Latency = 008
N2.C1.D1.R0.S01: Write Level Fine Value = 487
N4.C3.D0.R1.S06: PI = 033, PtrOffset = 004
N6.C3.D0.R0.S09: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N0.C3.D0.R0.S15: Preamble found at Latency = 008
N2.C1.D1.R0.S02: Write Level Fine Value = 480
N4.C3.D0.R1.S07: PI = 054, PtrOffset = 004
N6.C3.D0.R0.S10: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N0.C3.D0.R0.S16: Preamble found at Latency = 008
N2.C1.D1.R0.S03: Write Level Fine Value = 462
N4.C3.D0.R1.S08: PI = 032, PtrOffset = 005
N6.C3.D0.R0.S11: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N0.C3.D0.R0.S09: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N2.C1.D1.R0.S04: Write Level Fine Value = 431
N4.C3.D0.R1.S00: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N6.C3.D0.R0.S12: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N0.C3.D0.R0.S10: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N2.C1.D1.R0.S05: Write Level Fine Value = 446
N4.C3.D0.R1.S01: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N6.C3.D0.R0.S13: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N0.C3.D0.R0.S11: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N2.C1.D1.R0.S06: Write Level Fine Value = 457
N4.C3.D0.R1.S02: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N6.C3.D0.R0.S14: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N0.C3.D0.R0.S12: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N2.C1.D1.R0.S07: Write Level Fine Value = 475
N4.C3.D0.R1.S03: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N6.C3.D0.R0.S15: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N0.C3.D0.R0.S13: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N2.C1.D1.R0.S08: Write Level Fine Value = 442
N4.C3.D0.R1.S04: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N6.C3.D0.R0.S16: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N0.C3.D0.R0.S14: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N2.C1.D1.R0.S09: Write Level Fine Value = 504
N4.C3.D0.R1.S05: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N6.C3.D0.R0.S17: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N0.C3.D0.R0.S15: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N2.C1.D1.R0.S10: Write Level Fine Value = 486
N4.C3.D0.R1.S06: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N6.C3.D0.R0.S12: Preamble found at Latency = 007
N0.C3.D0.R0.S16: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N2.C1.D1.R0.S11: Write Level Fine Value = 480
N4.C3.D0.R1.S07: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N6.C3.D0.R0.S13: Preamble found at Latency = 007
N0.C3.D0.R0.S17: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N2.C1.D1.R0.S12: Write Level Fine Value = 464
N4.C3.D0.R1.S08: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N6.C3.D0.R0.S17: Preamble found at Latency = 007
N0.C3.D0.R0.S12: Preamble found at Latency = 007
N2.C1.D1.R0.S13: Write Level Fine Value = 430
N4.C3.D0.R1.S00: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N6.C3.D0.R0: Preamble found for all upper nibbles, adjusting Pi, Offset to center into preamble
N0.C3.D0.R0.S13: Preamble found at Latency = 007
N2.C1.D1.R0.S14: Write Level Fine Value = 445
N4.C3.D0.R1.S01: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N6.C3.D0.R0.S09: Total Receive Enable Delay = 1377
N0.C3.D0.R0.S17: Preamble found at Latency = 007
N2.C1.D1.R0.S15: Write Level Fine Value = 457
N4.C3.D0.R1.S02: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N6.C3.D0.R0.S10: Total Receive Enable Delay = 1358
N0.C3.D0.R0: Preamble found for all upper nibbles, adjusting Pi, Offset to center into preamble
N2.C1.D1.R0.S16: Write Level Fine Value = 474
N4.C3.D0.R1.S03: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N6.C3.D0.R0.S11: Total Receive Enable Delay = 1331
N0.C3.D0.R0.S09: Total Receive Enable Delay = 1375
N2.C1.D1.R0.S17: Write Level Fine Value = 442
N4.C3.D0.R1.S04: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N6.C3.D0.R0.S12: Total Receive Enable Delay = 1306
N0.C3.D0.R0.S10: Total Receive Enable Delay = 1356
N2.C1.D1.R1: ODT Override: 0x9
N4.C3.D0.R1.S05: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N6.C3.D0.R0.S13: Total Receive Enable Delay = 1302
N0.C3.D0.R0.S11: Total Receive Enable Delay = 1328
N2.C1.D1.R1.S00: Write Level Fine Value = 498
N4.C3.D0.R1.S06: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N6.C3.D0.R0.S14: Total Receive Enable Delay = 1332
N0.C3.D0.R0.S12: Total Receive Enable Delay = 1305
N2.C1.D1.R1.S01: Write Level Fine Value = 482
N4.C3.D0.R1.S07: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N6.C3.D0.R0.S15: Total Receive Enable Delay = 1353
N0.C3.D0.R0.S13: Total Receive Enable Delay = 1299
N2.C1.D1.R1.S02: Write Level Fine Value = 475
N4.C3.D0.R1.S08: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N6.C3.D0.R0.S16: Total Receive Enable Delay = 1373
N0.C3.D0.R0.S14: Total Receive Enable Delay = 1326
N2.C1.D1.R1.S03: Write Level Fine Value = 458
N4.C3.D0.R1.S00: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N6.C3.D0.R0.S17: Total Receive Enable Delay = 1290
N0.C3.D0.R0.S15: Total Receive Enable Delay = 1349
N2.C1.D1.R1.S04: Write Level Fine Value = 426
N4.C3.D0.R1.S01: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N6.C3.D0.R1: RcvEnFine: Initial RdCmd2RcvEnLatency = 10, Initial RdPtrOffsetRcvEn = 4
N0.C3.D0.R0.S16: Total Receive Enable Delay = 1373
N2.C1.D1.R1.S05: Write Level Fine Value = 441
N4.C3.D0.R1.S02: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N6.C3.D0.R1.S00: Rcv En Fine Value = 325
N0.C3.D0.R0.S17: Total Receive Enable Delay = 1282
N2.C1.D1.R1.S06: Write Level Fine Value = 453
N4.C3.D0.R1.S03: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N6.C3.D0.R1.S01: Rcv En Fine Value = 301
N0.C3.D0.R1: RcvEnFine: Initial RdCmd2RcvEnLatency = 10, Initial RdPtrOffsetRcvEn = 4
N2.C1.D1.R1.S07: Write Level Fine Value = 472
N4.C3.D0.R1.S04: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N6.C3.D0.R1.S02: Rcv En Fine Value = 273
N0.C3.D0.R1.S00: Rcv En Fine Value = 319
N2.C1.D1.R1.S08: Write Level Fine Value = 438
N4.C3.D0.R1.S05: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N6.C3.D0.R1.S03: Rcv En Fine Value = 377
N0.C3.D0.R1.S01: Rcv En Fine Value = 298
N2.C1.D1.R1.S09: Write Level Fine Value = 497
N4.C3.D0.R1.S06: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N6.C3.D0.R1.S04: Rcv En Fine Value = 372
N0.C3.D0.R1.S02: Rcv En Fine Value = 270
N2.C1.D1.R1.S10: Write Level Fine Value = 482
N4.C3.D0.R1.S07: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N6.C3.D0.R1.S05: Rcv En Fine Value = 272
N0.C3.D0.R1.S03: Rcv En Fine Value = 373
N2.C1.D1.R1.S11: Write Level Fine Value = 475
N4.C3.D0.R1.S08: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N6.C3.D0.R1.S06: Rcv En Fine Value = 296
N0.C3.D0.R1.S04: Rcv En Fine Value = 370
N2.C1.D1.R1.S12: Write Level Fine Value = 462
N4.C3.D0.R1.S00: Preamble found at Latency = 008
N6.C3.D0.R1.S07: Rcv En Fine Value = 314
N0.C3.D0.R1.S05: Rcv En Fine Value = 266
N2.C1.D1.R1.S13: Write Level Fine Value = 425
N4.C3.D0.R1.S01: Preamble found at Latency = 008
N6.C3.D0.R1.S08: Rcv En Fine Value = 360
N0.C3.D0.R1.S06: Rcv En Fine Value = 291
N2.C1.D1.R1.S14: Write Level Fine Value = 440
N4.C3.D0.R1.S02: Preamble found at Latency = 008
N6.C3.D0.R1.S09: Rcv En Fine Value = 320
N0.C3.D0.R1.S07: Rcv En Fine Value = 312
N2.C1.D1.R1.S15: Write Level Fine Value = 451
N4.C3.D0.R1.S05: Preamble found at Latency = 008
N6.C3.D0.R1.S10: Rcv En Fine Value = 304
N0.C3.D0.R1.S08: Rcv En Fine Value = 359
N2.C1.D1.R1.S16: Write Level Fine Value = 472
N4.C3.D0.R1.S06: Preamble found at Latency = 008
N6.C3.D0.R1.S11: Rcv En Fine Value = 274
N0.C3.D0.R1.S09: Rcv En Fine Value = 317
N2.C1.D1.R1.S17: Write Level Fine Value = 437
N4.C3.D0.R1.S07: Preamble found at Latency = 008
N6.C3.D0.R1.S12: Rcv En Fine Value = 379
N0.C3.D0.R1.S10: Rcv En Fine Value = 300
N2.C2.D0.R0: ODT Override: 0x5
N4.C3.D0.R1.S00: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N6.C3.D0.R1.S13: Rcv En Fine Value = 372
N0.C3.D0.R1.S11: Rcv En Fine Value = 271
N2.C2.D0.R0.S00: Write Level Fine Value = 497
N4.C3.D0.R1.S01: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N6.C3.D0.R1.S14: Rcv En Fine Value = 275
N0.C3.D0.R1.S12: Rcv En Fine Value = 377
N2.C2.D0.R0.S01: Write Level Fine Value = 482
N4.C3.D0.R1.S02: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N6.C3.D0.R1.S15: Rcv En Fine Value = 298
N0.C3.D0.R1.S13: Rcv En Fine Value = 367
N2.C2.D0.R0.S02: Write Level Fine Value = 472
N4.C3.D0.R1.S03: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N6.C3.D0.R1.S16: Rcv En Fine Value = 317
N0.C3.D0.R1.S14: Rcv En Fine Value = 267
N2.C2.D0.R0.S03: Write Level Fine Value = 454
N4.C3.D0.R1.S04: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N6.C3.D0.R1.S17: Rcv En Fine Value = 362
N0.C3.D0.R1.S15: Rcv En Fine Value = 291
N2.C2.D0.R0.S04: Write Level Fine Value = 413
N4.C3.D0.R1.S05: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N6.C3.D0.R1: Starting preamble search lower nibbles
N0.C3.D0.R1.S16: Rcv En Fine Value = 314
N2.C2.D0.R0.S05: Write Level Fine Value = 442
N4.C3.D0.R1.S06: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N6.C3.D0.R1.S00: PI = 005, PtrOffset = 005
N0.C3.D0.R1.S17: Rcv En Fine Value = 355
N2.C2.D0.R0.S06: Write Level Fine Value = 441
N4.C3.D0.R1.S07: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N6.C3.D0.R1.S01: PI = 045, PtrOffset = 004
N0.C3.D0.R1: Starting preamble search lower nibbles
N2.C2.D0.R0.S07: Write Level Fine Value = 463
N4.C3.D0.R1.S08: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N6.C3.D0.R1.S02: PI = 017, PtrOffset = 004
N0.C3.D0.R1.S00: PI = 063, PtrOffset = 004
N2.C2.D0.R0.S08: Write Level Fine Value = 435
N4.C3.D0.R1.S03: Preamble found at Latency = 007
N6.C3.D0.R1.S03: PI = 057, PtrOffset = 005
N0.C3.D0.R1.S01: PI = 042, PtrOffset = 004
N2.C2.D0.R0.S09: Write Level Fine Value = 499
N4.C3.D0.R1.S04: Preamble found at Latency = 007
N6.C3.D0.R1.S04: PI = 052, PtrOffset = 005
N0.C3.D0.R1.S02: PI = 014, PtrOffset = 004
N2.C2.D0.R0.S10: Write Level Fine Value = 481
N4.C3.D0.R1.S08: Preamble found at Latency = 007
N6.C3.D0.R1.S05: PI = 016, PtrOffset = 004
N0.C3.D0.R1.S03: PI = 053, PtrOffset = 005
N2.C2.D0.R0.S11: Write Level Fine Value = 471
N4.C3.D0.R1.S00: Total Receive Enable Delay = 1373
N6.C3.D0.R1.S06: PI = 040, PtrOffset = 004
N0.C3.D0.R1.S04: PI = 050, PtrOffset = 005
N2.C2.D0.R0.S12: Write Level Fine Value = 455
N4.C3.D0.R1.S01: Total Receive Enable Delay = 1353
N6.C3.D0.R1.S07: PI = 058, PtrOffset = 004
N0.C3.D0.R1.S05: PI = 010, PtrOffset = 004
N2.C2.D0.R0.S13: Write Level Fine Value = 414
N4.C3.D0.R1.S02: Total Receive Enable Delay = 1323
N6.C3.D0.R1.S08: PI = 040, PtrOffset = 005
N0.C3.D0.R1.S06: PI = 035, PtrOffset = 004
N2.C2.D0.R0.S14: Write Level Fine Value = 441
N4.C3.D0.R1.S03: Total Receive Enable Delay = 1302
N6.C3.D0.R1.S00: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N0.C3.D0.R1.S07: PI = 056, PtrOffset = 004
N2.C2.D0.R0.S15: Write Level Fine Value = 440
N4.C3.D0.R1.S04: Total Receive Enable Delay = 1295
N6.C3.D0.R1.S01: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N0.C3.D0.R1.S08: PI = 039, PtrOffset = 005
N2.C2.D0.R0.S16: Write Level Fine Value = 464
N4.C3.D0.R1.S05: Total Receive Enable Delay = 1321
N6.C3.D0.R1.S02: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N0.C3.D0.R1.S00: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N2.C2.D0.R0.S17: Write Level Fine Value = 434
N4.C3.D0.R1.S06: Total Receive Enable Delay = 1345
N6.C3.D0.R1.S03: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N0.C3.D0.R1.S01: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N2.C2.D0.R1: ODT Override: 0x6
N4.C3.D0.R1.S07: Total Receive Enable Delay = 1366
N6.C3.D0.R1.S04: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N0.C3.D0.R1.S02: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N2.C2.D0.R1.S00: Write Level Fine Value = 490
N4.C3.D0.R1.S08: Total Receive Enable Delay = 1280
N6.C3.D0.R1.S05: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N0.C3.D0.R1.S03: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N2.C2.D0.R1.S01: Write Level Fine Value = 476
N4.C3.D0.R1: Starting preamble search upper nibbles
N6.C3.D0.R1.S06: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N0.C3.D0.R1.S04: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N2.C2.D0.R1.S02: Write Level Fine Value = 465
N4.C3.D0.R1.S09: PI = 061, PtrOffset = 004
N6.C3.D0.R1.S07: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N0.C3.D0.R1.S05: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N2.C2.D0.R1.S03: Write Level Fine Value = 447
N4.C3.D0.R1.S10: PI = 041, PtrOffset = 004
N6.C3.D0.R1.S08: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N0.C3.D0.R1.S06: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N2.C2.D0.R1.S04: Write Level Fine Value = 407
N4.C3.D0.R1.S11: PI = 013, PtrOffset = 004
N6.C3.D0.R1.S00: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N0.C3.D0.R1.S07: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N2.C2.D0.R1.S05: Write Level Fine Value = 436
N4.C3.D0.R1.S12: PI = 056, PtrOffset = 005
N6.C3.D0.R1.S01: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N0.C3.D0.R1.S08: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N2.C2.D0.R1.S06: Write Level Fine Value = 433
N4.C3.D0.R1.S13: PI = 048, PtrOffset = 005
N6.C3.D0.R1.S02: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N0.C3.D0.R1.S00: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N2.C2.D0.R1.S07: Write Level Fine Value = 457
N4.C3.D0.R1.S14: PI = 011, PtrOffset = 004
N6.C3.D0.R1.S03: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N0.C3.D0.R1.S01: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N2.C2.D0.R1.S08: Write Level Fine Value = 425
N4.C3.D0.R1.S15: PI = 036, PtrOffset = 004
N6.C3.D0.R1.S04: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N0.C3.D0.R1.S02: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N2.C2.D0.R1.S09: Write Level Fine Value = 489
N4.C3.D0.R1.S16: PI = 058, PtrOffset = 004
N6.C3.D0.R1.S05: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N0.C3.D0.R1.S03: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N2.C2.D0.R1.S10: Write Level Fine Value = 476
N4.C3.D0.R1.S17: PI = 035, PtrOffset = 005
N6.C3.D0.R1.S06: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N0.C3.D0.R1.S04: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N2.C2.D0.R1.S11: Write Level Fine Value = 465
N4.C3.D0.R1.S09: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N6.C3.D0.R1.S07: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N0.C3.D0.R1.S05: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N2.C2.D0.R1.S12: Write Level Fine Value = 449
N4.C3.D0.R1.S10: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N6.C3.D0.R1.S08: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N0.C3.D0.R1.S06: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N2.C2.D0.R1.S13: Write Level Fine Value = 407
N4.C3.D0.R1.S11: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N6.C3.D0.R1.S00: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N0.C3.D0.R1.S07: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N2.C2.D0.R1.S14: Write Level Fine Value = 436
N4.C3.D0.R1.S12: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N6.C3.D0.R1.S01: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N0.C3.D0.R1.S08: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N2.C2.D0.R1.S15: Write Level Fine Value = 434
N4.C3.D0.R1.S13: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N6.C3.D0.R1.S02: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N0.C3.D0.R1.S00: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N2.C2.D0.R1.S16: Write Level Fine Value = 458
N4.C3.D0.R1.S14: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N6.C3.D0.R1.S03: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N0.C3.D0.R1.S01: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N2.C2.D0.R1.S17: Write Level Fine Value = 425
N4.C3.D0.R1.S15: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N6.C3.D0.R1.S04: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N0.C3.D0.R1.S02: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N2.C2.D1.R0: ODT Override: 0x5
N4.C3.D0.R1.S16: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N6.C3.D0.R1.S05: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N0.C3.D0.R1.S03: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N2.C2.D1.R0.S00: Write Level Fine Value = 498
N4.C3.D0.R1.S17: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N6.C3.D0.R1.S06: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N0.C3.D0.R1.S04: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N2.C2.D1.R0.S01: Write Level Fine Value = 486
N4.C3.D0.R1.S09: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N6.C3.D0.R1.S07: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N0.C3.D0.R1.S05: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N2.C2.D1.R0.S02: Write Level Fine Value = 474
N4.C3.D0.R1.S10: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N6.C3.D0.R1.S08: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N0.C3.D0.R1.S06: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N2.C2.D1.R0.S03: Write Level Fine Value = 461
N4.C3.D0.R1.S11: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N6.C3.D0.R1.S00: Preamble found at Latency = 008
N0.C3.D0.R1.S07: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N2.C2.D1.R0.S04: Write Level Fine Value = 418
N4.C3.D0.R1.S12: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N6.C3.D0.R1.S01: Preamble found at Latency = 008
N0.C3.D0.R1.S08: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N2.C2.D1.R0.S05: Write Level Fine Value = 448
N4.C3.D0.R1.S13: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N6.C3.D0.R1.S02: Preamble found at Latency = 008
N0.C3.D0.R1.S00: Preamble found at Latency = 008
N2.C2.D1.R0.S06: Write Level Fine Value = 445
N4.C3.D0.R1.S14: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N6.C3.D0.R1.S05: Preamble found at Latency = 008
N0.C3.D0.R1.S01: Preamble found at Latency = 008
N2.C2.D1.R0.S07: Write Level Fine Value = 467
N4.C3.D0.R1.S15: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N6.C3.D0.R1.S06: Preamble found at Latency = 008
N0.C3.D0.R1.S02: Preamble found at Latency = 008
N2.C2.D1.R0.S08: Write Level Fine Value = 433
N4.C3.D0.R1.S16: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N6.C3.D0.R1.S07: Preamble found at Latency = 008
N0.C3.D0.R1.S05: Preamble found at Latency = 008
N2.C2.D1.R0.S09: Write Level Fine Value = 498
N4.C3.D0.R1.S17: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N6.C3.D0.R1.S00: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N0.C3.D0.R1.S06: Preamble found at Latency = 008
N2.C2.D1.R0.S10: Write Level Fine Value = 486
N4.C3.D0.R1.S09: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N6.C3.D0.R1.S01: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N0.C3.D0.R1.S07: Preamble found at Latency = 008
N2.C2.D1.R0.S11: Write Level Fine Value = 474
N4.C3.D0.R1.S10: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N6.C3.D0.R1.S02: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N0.C3.D0.R1.S00: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N2.C2.D1.R0.S12: Write Level Fine Value = 460
N4.C3.D0.R1.S11: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N6.C3.D0.R1.S03: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N0.C3.D0.R1.S01: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N2.C2.D1.R0.S13: Write Level Fine Value = 420
N4.C3.D0.R1.S12: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N6.C3.D0.R1.S04: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N0.C3.D0.R1.S02: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N2.C2.D1.R0.S14: Write Level Fine Value = 447
N4.C3.D0.R1.S13: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N6.C3.D0.R1.S05: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N0.C3.D0.R1.S03: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N2.C2.D1.R0.S15: Write Level Fine Value = 445
N4.C3.D0.R1.S14: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N6.C3.D0.R1.S06: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N0.C3.D0.R1.S04: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N2.C2.D1.R0.S16: Write Level Fine Value = 467
N4.C3.D0.R1.S15: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N6.C3.D0.R1.S07: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N0.C3.D0.R1.S05: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N2.C2.D1.R0.S17: Write Level Fine Value = 434
N4.C3.D0.R1.S16: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N6.C3.D0.R1.S08: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N0.C3.D0.R1.S06: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N2.C2.D1.R1: ODT Override: 0x9
N4.C3.D0.R1.S17: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N6.C3.D0.R1.S03: Preamble found at Latency = 007
N0.C3.D0.R1.S07: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N2.C2.D1.R1.S00: Write Level Fine Value = 497
N4.C3.D0.R1.S09: Preamble found at Latency = 008
N6.C3.D0.R1.S04: Preamble found at Latency = 007
N0.C3.D0.R1.S08: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N2.C2.D1.R1.S01: Write Level Fine Value = 481
N4.C3.D0.R1.S10: Preamble found at Latency = 008
N6.C3.D0.R1.S08: Preamble found at Latency = 007
N0.C3.D0.R1.S03: Preamble found at Latency = 007
N2.C2.D1.R1.S02: Write Level Fine Value = 469
N4.C3.D0.R1.S11: Preamble found at Latency = 008
N6.C3.D0.R1.S00: Total Receive Enable Delay = 1381
N0.C3.D0.R1.S04: Preamble found at Latency = 007
N2.C2.D1.R1.S03: Write Level Fine Value = 457
N4.C3.D0.R1.S14: Preamble found at Latency = 008
N6.C3.D0.R1.S01: Total Receive Enable Delay = 1357
N0.C3.D0.R1.S08: Preamble found at Latency = 007
N2.C2.D1.R1.S04: Write Level Fine Value = 414
N4.C3.D0.R1.S15: Preamble found at Latency = 008
N6.C3.D0.R1.S02: Total Receive Enable Delay = 1329
N0.C3.D0.R1.S00: Total Receive Enable Delay = 1375
N2.C2.D1.R1.S05: Write Level Fine Value = 445
N4.C3.D0.R1.S16: Preamble found at Latency = 008
N6.C3.D0.R1.S03: Total Receive Enable Delay = 1305
N0.C3.D0.R1.S01: Total Receive Enable Delay = 1354
N2.C2.D1.R1.S06: Write Level Fine Value = 439
N4.C3.D0.R1.S09: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N6.C3.D0.R1.S04: Total Receive Enable Delay = 1300
N0.C3.D0.R1.S02: Total Receive Enable Delay = 1326
N2.C2.D1.R1.S07: Write Level Fine Value = 465
N4.C3.D0.R1.S10: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N6.C3.D0.R1.S05: Total Receive Enable Delay = 1328
N0.C3.D0.R1.S03: Total Receive Enable Delay = 1301
N2.C2.D1.R1.S08: Write Level Fine Value = 431
N4.C3.D0.R1.S11: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N6.C3.D0.R1.S06: Total Receive Enable Delay = 1352
N0.C3.D0.R1.S04: Total Receive Enable Delay = 1298
N2.C2.D1.R1.S09: Write Level Fine Value = 494
N4.C3.D0.R1.S12: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N6.C3.D0.R1.S07: Total Receive Enable Delay = 1370
N0.C3.D0.R1.S05: Total Receive Enable Delay = 1322
N2.C2.D1.R1.S10: Write Level Fine Value = 482
N4.C3.D0.R1.S13: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N6.C3.D0.R1.S08: Total Receive Enable Delay = 1288
N0.C3.D0.R1.S06: Total Receive Enable Delay = 1347
N2.C2.D1.R1.S11: Write Level Fine Value = 471
N4.C3.D0.R1.S14: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N6.C3.D0.R1: Starting preamble search upper nibbles
N0.C3.D0.R1.S07: Total Receive Enable Delay = 1368
N2.C2.D1.R1.S12: Write Level Fine Value = 457
N4.C3.D0.R1.S15: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N6.C3.D0.R1.S09: PI = 000, PtrOffset = 005
N0.C3.D0.R1.S08: Total Receive Enable Delay = 1287
N2.C2.D1.R1.S13: Write Level Fine Value = 415
N4.C3.D0.R1.S16: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N6.C3.D0.R1.S10: PI = 048, PtrOffset = 004
N0.C3.D0.R1: Starting preamble search upper nibbles
N2.C2.D1.R1.S14: Write Level Fine Value = 444
N4.C3.D0.R1.S17: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N6.C3.D0.R1.S11: PI = 018, PtrOffset = 004
N0.C3.D0.R1.S09: PI = 061, PtrOffset = 004
N2.C2.D1.R1.S15: Write Level Fine Value = 440
N4.C3.D0.R1.S12: Preamble found at Latency = 007
N6.C3.D0.R1.S12: PI = 059, PtrOffset = 005
N0.C3.D0.R1.S10: PI = 044, PtrOffset = 004
N2.C2.D1.R1.S16: Write Level Fine Value = 464
N4.C3.D0.R1.S13: Preamble found at Latency = 007
N6.C3.D0.R1.S13: PI = 052, PtrOffset = 005
N0.C3.D0.R1.S11: PI = 015, PtrOffset = 004
N2.C2.D1.R1.S17: Write Level Fine Value = 428
N4.C3.D0.R1.S17: Preamble found at Latency = 007
N6.C3.D0.R1.S14: PI = 019, PtrOffset = 004
N0.C3.D0.R1.S12: PI = 057, PtrOffset = 005
N2.C3.D0.R0: ODT Override: 0x5
N4.C3.D0.R1: Preamble found for all upper nibbles, adjusting Pi, Offset to center into preamble
N6.C3.D0.R1.S15: PI = 042, PtrOffset = 004
N0.C3.D0.R1.S13: PI = 047, PtrOffset = 005
N2.C3.D0.R0.S00: Write Level Fine Value = 503
N4.C3.D0.R1.S09: Total Receive Enable Delay = 1373
N6.C3.D0.R1.S16: PI = 061, PtrOffset = 004
N0.C3.D0.R1.S14: PI = 011, PtrOffset = 004
N2.C3.D0.R0.S01: Write Level Fine Value = 487
N4.C3.D0.R1.S10: Total Receive Enable Delay = 1353
N6.C3.D0.R1.S17: PI = 042, PtrOffset = 005
N0.C3.D0.R1.S15: PI = 035, PtrOffset = 004
N2.C3.D0.R0.S02: Write Level Fine Value = 479
N4.C3.D0.R1.S11: Total Receive Enable Delay = 1325
N6.C3.D0.R1.S09: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N0.C3.D0.R1.S16: PI = 058, PtrOffset = 004
N2.C3.D0.R0.S03: Write Level Fine Value = 460
N4.C3.D0.R1.S12: Total Receive Enable Delay = 1304
N6.C3.D0.R1.S10: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N0.C3.D0.R1.S17: PI = 035, PtrOffset = 005
N2.C3.D0.R0.S04: Write Level Fine Value = 427
N4.C3.D0.R1.S13: Total Receive Enable Delay = 1296
N6.C3.D0.R1.S11: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N0.C3.D0.R1.S09: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N2.C3.D0.R0.S05: Write Level Fine Value = 439
N4.C3.D0.R1.S14: Total Receive Enable Delay = 1323
N6.C3.D0.R1.S12: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N0.C3.D0.R1.S10: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N2.C3.D0.R0.S06: Write Level Fine Value = 455
N4.C3.D0.R1.S15: Total Receive Enable Delay = 1348
N6.C3.D0.R1.S13: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N0.C3.D0.R1.S11: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N2.C3.D0.R0.S07: Write Level Fine Value = 471
N4.C3.D0.R1.S16: Total Receive Enable Delay = 1370
N6.C3.D0.R1.S14: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N0.C3.D0.R1.S12: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N2.C3.D0.R0.S08: Write Level Fine Value = 445
N4.C3.D0.R1.S17: Total Receive Enable Delay = 1283
N6.C3.D0.R1.S15: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N0.C3.D0.R1.S13: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N2.C3.D0.R0.S09: Write Level Fine Value = 504
N4.C3.D1.R0: RcvEnFine: Initial RdCmd2RcvEnLatency = 10, Initial RdPtrOffsetRcvEn = 4
N6.C3.D0.R1.S16: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N0.C3.D0.R1.S14: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N2.C3.D0.R0.S10: Write Level Fine Value = 488
N4.C3.D1.R0.S00: Rcv En Fine Value = 303
N6.C3.D0.R1.S17: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N0.C3.D0.R1.S15: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N2.C3.D0.R0.S11: Write Level Fine Value = 479
N4.C3.D1.R0.S01: Rcv En Fine Value = 284
N6.C3.D0.R1.S09: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N0.C3.D0.R1.S16: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N2.C3.D0.R0.S12: Write Level Fine Value = 462
N4.C3.D1.R0.S02: Rcv En Fine Value = 256
N6.C3.D0.R1.S10: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N0.C3.D0.R1.S17: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N2.C3.D0.R0.S13: Write Level Fine Value = 426
N4.C3.D1.R0.S03: Rcv En Fine Value = 363
N6.C3.D0.R1.S11: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N0.C3.D0.R1.S09: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N2.C3.D0.R0.S14: Write Level Fine Value = 440
N4.C3.D1.R0.S04: Rcv En Fine Value = 355
N6.C3.D0.R1.S12: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N0.C3.D0.R1.S10: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N2.C3.D0.R0.S15: Write Level Fine Value = 454
N4.C3.D1.R0.S05: Rcv En Fine Value = 382
N6.C3.D0.R1.S13: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N0.C3.D0.R1.S11: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N2.C3.D0.R0.S16: Write Level Fine Value = 468
N4.C3.D1.R0.S06: Rcv En Fine Value = 276
N6.C3.D0.R1.S14: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N0.C3.D0.R1.S12: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N2.C3.D0.R0.S17: Write Level Fine Value = 445
N4.C3.D1.R0.S07: Rcv En Fine Value = 300
N6.C3.D0.R1.S15: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N0.C3.D0.R1.S13: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N2.C3.D0.R1: ODT Override: 0x6
N4.C3.D1.R0.S08: Rcv En Fine Value = 343
N6.C3.D0.R1.S16: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N0.C3.D0.R1.S14: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N2.C3.D0.R1.S00: Write Level Fine Value = 498
N4.C3.D1.R0.S09: Rcv En Fine Value = 304
N6.C3.D0.R1.S17: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N0.C3.D0.R1.S15: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N2.C3.D0.R1.S01: Write Level Fine Value = 478
N4.C3.D1.R0.S10: Rcv En Fine Value = 281
N6.C3.D0.R1.S09: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N0.C3.D0.R1.S16: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N2.C3.D0.R1.S02: Write Level Fine Value = 470
N4.C3.D1.R0.S11: Rcv En Fine Value = 382
N6.C3.D0.R1.S10: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N0.C3.D0.R1.S17: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N2.C3.D0.R1.S03: Write Level Fine Value = 455
N4.C3.D1.R0.S12: Rcv En Fine Value = 363
N6.C3.D0.R1.S11: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N0.C3.D0.R1.S09: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N2.C3.D0.R1.S04: Write Level Fine Value = 420
N4.C3.D1.R0.S13: Rcv En Fine Value = 355
N6.C3.D0.R1.S12: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N0.C3.D0.R1.S10: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N2.C3.D0.R1.S05: Write Level Fine Value = 433
N4.C3.D1.R0.S14: Rcv En Fine Value = 383
N6.C3.D0.R1.S13: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N0.C3.D0.R1.S11: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N2.C3.D0.R1.S06: Write Level Fine Value = 447
N4.C3.D1.R0.S15: Rcv En Fine Value = 276
N6.C3.D0.R1.S14: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N0.C3.D0.R1.S12: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N2.C3.D0.R1.S07: Write Level Fine Value = 464
N4.C3.D1.R0.S16: Rcv En Fine Value = 299
N6.C3.D0.R1.S15: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N0.C3.D0.R1.S13: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N2.C3.D0.R1.S08: Write Level Fine Value = 438
N4.C3.D1.R0.S17: Rcv En Fine Value = 343
N6.C3.D0.R1.S16: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N0.C3.D0.R1.S14: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N2.C3.D0.R1.S09: Write Level Fine Value = 495
N4.C3.D1.R0: Starting preamble search lower nibbles
N6.C3.D0.R1.S17: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N0.C3.D0.R1.S15: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N2.C3.D0.R1.S10: Write Level Fine Value = 479
N4.C3.D1.R0.S00: PI = 047, PtrOffset = 004
N6.C3.D0.R1.S09: Preamble found at Latency = 008
N0.C3.D0.R1.S16: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N2.C3.D0.R1.S11: Write Level Fine Value = 472
N4.C3.D1.R0.S01: PI = 028, PtrOffset = 004
N6.C3.D0.R1.S10: Preamble found at Latency = 008
N0.C3.D0.R1.S17: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N2.C3.D0.R1.S12: Write Level Fine Value = 457
N4.C3.D1.R0.S02: PI = 000, PtrOffset = 004
N6.C3.D0.R1.S11: Preamble found at Latency = 008
N0.C3.D0.R1.S09: Preamble found at Latency = 008
N2.C3.D0.R1.S13: Write Level Fine Value = 421
N4.C3.D1.R0.S03: PI = 043, PtrOffset = 005
N6.C3.D0.R1.S14: Preamble found at Latency = 008
N0.C3.D0.R1.S10: Preamble found at Latency = 008
N2.C3.D0.R1.S14: Write Level Fine Value = 433
N4.C3.D1.R0.S04: PI = 035, PtrOffset = 005
N6.C3.D0.R1.S15: Preamble found at Latency = 008
N0.C3.D0.R1.S11: Preamble found at Latency = 008
N2.C3.D0.R1.S15: Write Level Fine Value = 448
N4.C3.D1.R0.S05: PI = 062, PtrOffset = 005
N6.C3.D0.R1.S16: Preamble found at Latency = 008
N0.C3.D0.R1.S14: Preamble found at Latency = 008
N2.C3.D0.R1.S16: Write Level Fine Value = 465
N4.C3.D1.R0.S06: PI = 020, PtrOffset = 004
N6.C3.D0.R1.S09: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N0.C3.D0.R1.S15: Preamble found at Latency = 008
N2.C3.D0.R1.S17: Write Level Fine Value = 437
N4.C3.D1.R0.S07: PI = 044, PtrOffset = 004
N6.C3.D0.R1.S10: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N0.C3.D0.R1.S16: Preamble found at Latency = 008
N2.C3.D1.R0: ODT Override: 0x5
N4.C3.D1.R0.S08: PI = 023, PtrOffset = 005
N6.C3.D0.R1.S11: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N0.C3.D0.R1.S09: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N2.C3.D1.R0.S00: Write Level Fine Value = 508
N4.C3.D1.R0.S00: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N6.C3.D0.R1.S12: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N0.C3.D0.R1.S10: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N2.C3.D1.R0.S01: Write Level Fine Value = 492
N4.C3.D1.R0.S01: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N6.C3.D0.R1.S13: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N0.C3.D0.R1.S11: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N2.C3.D1.R0.S02: Write Level Fine Value = 484
N4.C3.D1.R0.S02: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N6.C3.D0.R1.S14: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N0.C3.D0.R1.S12: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N2.C3.D1.R0.S03: Write Level Fine Value = 466
N4.C3.D1.R0.S03: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N6.C3.D0.R1.S15: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N0.C3.D0.R1.S13: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N2.C3.D1.R0.S04: Write Level Fine Value = 431
N4.C3.D1.R0.S04: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N6.C3.D0.R1.S16: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N0.C3.D0.R1.S14: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N2.C3.D1.R0.S05: Write Level Fine Value = 445
N4.C3.D1.R0.S05: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N6.C3.D0.R1.S17: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N0.C3.D0.R1.S15: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N2.C3.D1.R0.S06: Write Level Fine Value = 458
N4.C3.D1.R0.S06: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N6.C3.D0.R1.S12: Preamble found at Latency = 007
N0.C3.D0.R1.S16: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N2.C3.D1.R0.S07: Write Level Fine Value = 476
N4.C3.D1.R0.S07: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N6.C3.D0.R1.S13: Preamble found at Latency = 007
N0.C3.D0.R1.S17: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N2.C3.D1.R0.S08: Write Level Fine Value = 449
N4.C3.D1.R0.S08: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N6.C3.D0.R1.S17: Preamble found at Latency = 007
N0.C3.D0.R1.S12: Preamble found at Latency = 007
N2.C3.D1.R0.S09: Write Level Fine Value = 507
N4.C3.D1.R0.S00: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N6.C3.D0.R1: Preamble found for all upper nibbles, adjusting Pi, Offset to center into preamble
N0.C3.D0.R1.S13: Preamble found at Latency = 007
N2.C3.D1.R0.S10: Write Level Fine Value = 492
N4.C3.D1.R0.S01: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N6.C3.D0.R1.S09: Total Receive Enable Delay = 1376
N0.C3.D0.R1.S17: Preamble found at Latency = 007
N2.C3.D1.R0.S11: Write Level Fine Value = 482
N4.C3.D1.R0.S02: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N6.C3.D0.R1.S10: Total Receive Enable Delay = 1360
N0.C3.D0.R1: Preamble found for all upper nibbles, adjusting Pi, Offset to center into preamble
N2.C3.D1.R0.S12: Write Level Fine Value = 468
N4.C3.D1.R0.S03: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N6.C3.D0.R1.S11: Total Receive Enable Delay = 1330
N0.C3.D0.R1.S09: Total Receive Enable Delay = 1373
N2.C3.D1.R0.S13: Write Level Fine Value = 433
N4.C3.D1.R0.S04: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N6.C3.D0.R1.S12: Total Receive Enable Delay = 1307
N0.C3.D0.R1.S10: Total Receive Enable Delay = 1356
N2.C3.D1.R0.S14: Write Level Fine Value = 443
N4.C3.D1.R0.S05: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N6.C3.D0.R1.S13: Total Receive Enable Delay = 1300
N0.C3.D0.R1.S11: Total Receive Enable Delay = 1327
N2.C3.D1.R0.S15: Write Level Fine Value = 458
N4.C3.D1.R0.S06: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N6.C3.D0.R1.S14: Total Receive Enable Delay = 1331
N0.C3.D0.R1.S12: Total Receive Enable Delay = 1305
N2.C3.D1.R0.S16: Write Level Fine Value = 475
N4.C3.D1.R0.S07: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N6.C3.D0.R1.S15: Total Receive Enable Delay = 1354
N0.C3.D0.R1.S13: Total Receive Enable Delay = 1295
N2.C3.D1.R0.S17: Write Level Fine Value = 448
N4.C3.D1.R0.S08: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N6.C3.D0.R1.S16: Total Receive Enable Delay = 1373
N0.C3.D0.R1.S14: Total Receive Enable Delay = 1323
N2.C3.D1.R1: ODT Override: 0x9
N4.C3.D1.R0.S00: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N6.C3.D0.R1.S17: Total Receive Enable Delay = 1290
N0.C3.D0.R1.S15: Total Receive Enable Delay = 1347
N2.C3.D1.R1.S00: Write Level Fine Value = 506
N4.C3.D1.R0.S01: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N6.C3.D1.R0: RcvEnFine: Initial RdCmd2RcvEnLatency = 10, Initial RdPtrOffsetRcvEn = 4
N0.C3.D0.R1.S16: Total Receive Enable Delay = 1370
N2.C3.D1.R1.S01: Write Level Fine Value = 487
N4.C3.D1.R0.S02: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N6.C3.D1.R0.S00: Rcv En Fine Value = 308
N0.C3.D0.R1.S17: Total Receive Enable Delay = 1283
N2.C3.D1.R1.S02: Write Level Fine Value = 478
N4.C3.D1.R0.S03: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N6.C3.D1.R0.S01: Rcv En Fine Value = 289
N0.C3.D1.R0: RcvEnFine: Initial RdCmd2RcvEnLatency = 10, Initial RdPtrOffsetRcvEn = 4
N2.C3.D1.R1.S03: Write Level Fine Value = 463
N4.C3.D1.R0.S04: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N6.C3.D1.R0.S02: Rcv En Fine Value = 262
N0.C3.D1.R0.S00: Rcv En Fine Value = 304
N2.C3.D1.R1.S04: Write Level Fine Value = 428
N4.C3.D1.R0.S05: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N6.C3.D1.R0.S03: Rcv En Fine Value = 365
N0.C3.D1.R0.S01: Rcv En Fine Value = 286
N2.C3.D1.R1.S05: Write Level Fine Value = 441
N4.C3.D1.R0.S06: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N6.C3.D1.R0.S04: Rcv En Fine Value = 359
N0.C3.D1.R0.S02: Rcv En Fine Value = 381
N2.C3.D1.R1.S06: Write Level Fine Value = 455
N4.C3.D1.R0.S07: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N6.C3.D1.R0.S05: Rcv En Fine Value = 262
N0.C3.D1.R0.S03: Rcv En Fine Value = 358
N2.C3.D1.R1.S07: Write Level Fine Value = 473
N4.C3.D1.R0.S08: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N6.C3.D1.R0.S06: Rcv En Fine Value = 280
N0.C3.D1.R0.S04: Rcv En Fine Value = 355
N2.C3.D1.R1.S08: Write Level Fine Value = 443
N4.C3.D1.R0.S00: Preamble found at Latency = 008
N6.C3.D1.R0.S07: Rcv En Fine Value = 303
N0.C3.D1.R0.S05: Rcv En Fine Value = 379
N2.C3.D1.R1.S09: Write Level Fine Value = 505
N4.C3.D1.R0.S01: Preamble found at Latency = 008
N6.C3.D1.R0.S08: Rcv En Fine Value = 347
N0.C3.D1.R0.S06: Rcv En Fine Value = 274
N2.C3.D1.R1.S10: Write Level Fine Value = 486
N4.C3.D1.R0.S02: Preamble found at Latency = 008
N6.C3.D1.R0.S09: Rcv En Fine Value = 307
N0.C3.D1.R0.S07: Rcv En Fine Value = 298
N2.C3.D1.R1.S11: Write Level Fine Value = 480
N4.C3.D1.R0.S06: Preamble found at Latency = 008
N6.C3.D1.R0.S10: Rcv En Fine Value = 288
N0.C3.D1.R0.S08: Rcv En Fine Value = 342
N2.C3.D1.R1.S12: Write Level Fine Value = 463
N4.C3.D1.R0.S07: Preamble found at Latency = 008
N6.C3.D1.R0.S11: Rcv En Fine Value = 261
N0.C3.D1.R0.S09: Rcv En Fine Value = 303
N2.C3.D1.R1.S13: Write Level Fine Value = 427
N4.C3.D1.R0.S00: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N6.C3.D1.R0.S12: Rcv En Fine Value = 366
N0.C3.D1.R0.S10: Rcv En Fine Value = 284
N2.C3.D1.R1.S14: Write Level Fine Value = 440
N4.C3.D1.R0.S01: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N6.C3.D1.R0.S13: Rcv En Fine Value = 360
N0.C3.D1.R0.S11: Rcv En Fine Value = 256
N2.C3.D1.R1.S15: Write Level Fine Value = 455
N4.C3.D1.R0.S02: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N6.C3.D1.R0.S14: Rcv En Fine Value = 262
N0.C3.D1.R0.S12: Rcv En Fine Value = 361
N2.C3.D1.R1.S16: Write Level Fine Value = 472
N4.C3.D1.R0.S03: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N6.C3.D1.R0.S15: Rcv En Fine Value = 280
N0.C3.D1.R0.S13: Rcv En Fine Value = 352
N2.C3.D1.R1.S17: Write Level Fine Value = 443
N4.C3.D1.R0.S04: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N6.C3.D1.R0.S16: Rcv En Fine Value = 304
N0.C3.D1.R0.S14: Rcv En Fine Value = 380
N2: END WRITE LEVEL:
N4.C3.D1.R0.S05: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N6.C3.D1.R0.S17: Rcv En Fine Value = 345
N0.C3.D1.R0.S15: Rcv En Fine Value = 276
N2: START WRITE LEVEL COARSE:
N4.C3.D1.R0.S06: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N6.C3.D1.R0: Starting preamble search lower nibbles
N0.C3.D1.R0.S16: Rcv En Fine Value = 301
N4.C3.D1.R0.S07: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N6.C3.D1.R0.S00: PI = 052, PtrOffset = 004
N0.C3.D1.R0.S17: Rcv En Fine Value = 340
N4.C3.D1.R0.S08: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N6.C3.D1.R0.S01: PI = 033, PtrOffset = 004
N0.C3.D1.R0: Starting preamble search lower nibbles
N4.C3.D1.R0.S03: Preamble found at Latency = 007
N6.C3.D1.R0.S02: PI = 006, PtrOffset = 004
N0.C3.D1.R0.S00: PI = 048, PtrOffset = 004
N4.C3.D1.R0.S04: Preamble found at Latency = 007
N6.C3.D1.R0.S03: PI = 045, PtrOffset = 005
N0.C3.D1.R0.S01: PI = 030, PtrOffset = 004
N4.C3.D1.R0.S05: Preamble found at Latency = 007
N6.C3.D1.R0.S04: PI = 039, PtrOffset = 005
N0.C3.D1.R0.S02: PI = 061, PtrOffset = 005
N2.C0.D0.R0: Write Training Coarse, lower nibbles / bytes
N4.C3.D1.R0.S08: Preamble found at Latency = 007
N6.C3.D1.R0.S05: PI = 006, PtrOffset = 004
N0.C3.D1.R0.S03: PI = 038, PtrOffset = 005
N2.C0.D0.R0.S00: Dq Delay estimate: 467
N4.C3.D1.R0.S00: Total Receive Enable Delay = 1359
N6.C3.D1.R0.S06: PI = 024, PtrOffset = 004
N0.C3.D1.R0.S04: PI = 035, PtrOffset = 005
N2.C0.D0.R0.S01: Dq Delay estimate: 445
N4.C3.D1.R0.S01: Total Receive Enable Delay = 1340
N6.C3.D1.R0.S07: PI = 047, PtrOffset = 004
N0.C3.D1.R0.S05: PI = 059, PtrOffset = 005
N2.C0.D0.R0.S02: Dq Delay estimate: 436
N4.C3.D1.R0.S02: Total Receive Enable Delay = 1312
N6.C3.D1.R0.S08: PI = 027, PtrOffset = 005
N0.C3.D1.R0.S06: PI = 018, PtrOffset = 004
N2.C0.D0.R0.S03: Dq Delay estimate: 418
N4.C3.D1.R0.S03: Total Receive Enable Delay = 1291
N6.C3.D1.R0.S00: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N0.C3.D1.R0.S07: PI = 042, PtrOffset = 004
N2.C0.D0.R0.S04: Dq Delay estimate: 384
N4.C3.D1.R0.S04: Total Receive Enable Delay = 1283
N6.C3.D1.R0.S01: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N0.C3.D1.R0.S08: PI = 022, PtrOffset = 005
N2.C0.D0.R0.S05: Dq Delay estimate: 401
N4.C3.D1.R0.S05: Total Receive Enable Delay = 1310
N6.C3.D1.R0.S02: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N0.C3.D1.R0.S00: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N2.C0.D0.R0.S06: Dq Delay estimate: 407
N4.C3.D1.R0.S06: Total Receive Enable Delay = 1332
N6.C3.D1.R0.S03: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N0.C3.D1.R0.S01: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N2.C0.D0.R0.S07: Dq Delay estimate: 419
N4.C3.D1.R0.S07: Total Receive Enable Delay = 1356
N6.C3.D1.R0.S04: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N0.C3.D1.R0.S02: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N2.C0.D0.R0.S08: Dq Delay estimate: 395
N4.C3.D1.R0.S08: Total Receive Enable Delay = 1271
N6.C3.D1.R0.S05: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N0.C3.D1.R0.S03: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
ACCM: 0F 0F9F9F9F DF0F0F0F
N4.C3.D1.R0: Starting preamble search upper nibbles
N6.C3.D1.R0.S06: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N0.C3.D1.R0.S04: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
ACCM: 0F 0F9F9F9F DF0F0F0F
N4.C3.D1.R0.S09: PI = 048, PtrOffset = 004
N6.C3.D1.R0.S07: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N0.C3.D1.R0.S05: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
ACCM: 0F FF9F9F9F FFFFFFFF
N4.C3.D1.R0.S10: PI = 025, PtrOffset = 004
N6.C3.D1.R0.S08: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N0.C3.D1.R0.S06: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
ACCM: 0F FF9F9F9F FFFFFFFF
N4.C3.D1.R0.S11: PI = 062, PtrOffset = 005
N6.C3.D1.R0.S00: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N0.C3.D1.R0.S07: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N2.C0.D0.R0: CheckMCTest: result = 0x1FFFF
N4.C3.D1.R0.S12: PI = 043, PtrOffset = 005
N6.C3.D1.R0.S01: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N0.C3.D1.R0.S08: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
ACCM: 0F 0FDFDF9F DF0F0F0F
N4.C3.D1.R0.S13: PI = 035, PtrOffset = 005
N6.C3.D1.R0.S02: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N0.C3.D1.R0.S00: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
ACCM: 0F 0FDFDF9F DF0F0F0F
N4.C3.D1.R0.S14: PI = 063, PtrOffset = 005
N6.C3.D1.R0.S03: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N0.C3.D1.R0.S01: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
ACCM: 0F FFDFDF9F FFFFFFFF
N4.C3.D1.R0.S15: PI = 020, PtrOffset = 004
N6.C3.D1.R0.S04: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N0.C3.D1.R0.S02: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
ACCM: 0F FFDFDF9F FFFFFFFF
N4.C3.D1.R0.S16: PI = 043, PtrOffset = 004
N6.C3.D1.R0.S05: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N0.C3.D1.R0.S03: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N2.C0.D0.R0: CheckMCTest: result = 0x1FFFF
N4.C3.D1.R0.S17: PI = 023, PtrOffset = 005
N6.C3.D1.R0.S06: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N0.C3.D1.R0.S04: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
ACCM: 0F 0FDFDFDF DF0F0F0F
N4.C3.D1.R0.S09: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N6.C3.D1.R0.S07: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N0.C3.D1.R0.S05: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
ACCM: 0F 0FDFDFDF DF0F0F0F
N4.C3.D1.R0.S10: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N6.C3.D1.R0.S08: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N0.C3.D1.R0.S06: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
ACCM: 0B FBDBD0D0 FBF0F0F0
N4.C3.D1.R0.S11: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N6.C3.D1.R0.S00: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N0.C3.D1.R0.S07: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
ACCM: 0B FBDBD0D0 FBF0F0F0
N4.C3.D1.R0.S12: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N6.C3.D1.R0.S01: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N0.C3.D1.R0.S08: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N2.C0.D0.R0: CheckMCTest: result = 0x1FFFF
N4.C3.D1.R0.S13: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N6.C3.D1.R0.S02: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N0.C3.D1.R0.S00: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
ACCM: 0F 0FDFDFDF DF0F0F0F
N4.C3.D1.R0.S14: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N6.C3.D1.R0.S03: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N0.C3.D1.R0.S01: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
ACCM: 0F 0FDFDFDF DF0F0F0F
N4.C3.D1.R0.S15: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N6.C3.D1.R0.S04: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N0.C3.D1.R0.S02: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
ACCM: 0B FFDFD0DD FBF0F0FD
N4.C3.D1.R0.S16: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N6.C3.D1.R0.S05: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N0.C3.D1.R0.S03: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
ACCM: 0B FFDFD0DD FBF0F0FD
N4.C3.D1.R0.S17: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N6.C3.D1.R0.S06: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N0.C3.D1.R0.S04: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N2.C0.D0.R0: CheckMCTest: result = 0x1FFFF
N4.C3.D1.R0.S09: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N6.C3.D1.R0.S07: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N0.C3.D1.R0.S05: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
ACCM: 00 00D0D0D0 D0000000
N4.C3.D1.R0.S10: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N6.C3.D1.R0.S08: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N0.C3.D1.R0.S06: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
ACCM: 00 00D0D0D0 D0000000
N4.C3.D1.R0.S11: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N6.C3.D1.R0.S00: Preamble found at Latency = 008
N0.C3.D1.R0.S07: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
ACCM: 00 F0D0D0D0 F0F0F0F0
N4.C3.D1.R0.S12: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N6.C3.D1.R0.S01: Preamble found at Latency = 008
N0.C3.D1.R0.S08: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
ACCM: 00 F0D0D0D0 F0F0F0F0
N4.C3.D1.R0.S13: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N6.C3.D1.R0.S02: Preamble found at Latency = 008
N0.C3.D1.R0.S00: Preamble found at Latency = 008
N2.C0.D0.R0: CheckMCTest: result = 0x1FE00
N4.C3.D1.R0.S14: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N6.C3.D1.R0.S05: Preamble found at Latency = 008
N0.C3.D1.R0.S01: Preamble found at Latency = 008
ACCM: 00 00D0D0D0 D0000000
N4.C3.D1.R0.S15: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N6.C3.D1.R0.S06: Preamble found at Latency = 008
N0.C3.D1.R0.S06: Preamble found at Latency = 008
ACCM: 00 00D0D0D0 D0000000
N4.C3.D1.R0.S16: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N6.C3.D1.R0.S07: Preamble found at Latency = 008
N0.C3.D1.R0.S07: Preamble found at Latency = 008
ACCM: 00 F0D0D0D0 F0F0F0F0
N4.C3.D1.R0.S17: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N6.C3.D1.R0.S00: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N0.C3.D1.R0.S00: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
ACCM: 00 F0D0D0D0 F0F0F0F0
N4.C3.D1.R0.S09: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N6.C3.D1.R0.S01: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N0.C3.D1.R0.S01: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N2.C0.D0.R0: CheckMCTest: result = 0x1FE00
N4.C3.D1.R0.S10: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N6.C3.D1.R0.S02: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N0.C3.D1.R0.S02: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N2.C0.D0.R0.S00: Offset Found: RdPtrOffsetDqs = 007
N4.C3.D1.R0.S11: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N6.C3.D1.R0.S03: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N0.C3.D1.R0.S03: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N2.C0.D0.R0.S01: Offset Found: RdPtrOffsetDqs = 007
N4.C3.D1.R0.S12: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N6.C3.D1.R0.S04: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N0.C3.D1.R0.S04: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N2.C0.D0.R0.S02: Offset Found: RdPtrOffsetDqs = 007
N4.C3.D1.R0.S13: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N6.C3.D1.R0.S05: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N0.C3.D1.R0.S05: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N2.C0.D0.R0.S03: Offset Found: RdPtrOffsetDqs = 007
N4.C3.D1.R0.S14: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N6.C3.D1.R0.S06: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N0.C3.D1.R0.S06: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N2.C0.D0.R0.S04: Offset Found: RdPtrOffsetDqs = 006
N4.C3.D1.R0.S15: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N6.C3.D1.R0.S07: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N0.C3.D1.R0.S07: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N2.C0.D0.R0.S05: Offset Found: RdPtrOffsetDqs = 006
N4.C3.D1.R0.S16: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N6.C3.D1.R0.S08: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N0.C3.D1.R0.S08: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N2.C0.D0.R0.S06: Offset Found: RdPtrOffsetDqs = 006
N4.C3.D1.R0.S17: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N6.C3.D1.R0.S03: Preamble found at Latency = 007
N0.C3.D1.R0.S02: Preamble found at Latency = 007
N2.C0.D0.R0.S07: Offset Found: RdPtrOffsetDqs = 007
N4.C3.D1.R0.S09: Preamble found at Latency = 008
N6.C3.D1.R0.S04: Preamble found at Latency = 007
N0.C3.D1.R0.S03: Preamble found at Latency = 007
N2.C0.D0.R0.S08: Offset Found: RdPtrOffsetDqs = 006
N4.C3.D1.R0.S10: Preamble found at Latency = 008
N6.C3.D1.R0.S08: Preamble found at Latency = 007
N0.C3.D1.R0.S04: Preamble found at Latency = 007
N2.C0.D0.R0: Write Training Coarse, upper nibbles
N4.C3.D1.R0.S15: Preamble found at Latency = 008
N6.C3.D1.R0.S00: Total Receive Enable Delay = 1364
N0.C3.D1.R0.S05: Preamble found at Latency = 007
N2.C0.D0.R0.S09: Dq Delay estimate: 471
N4.C3.D1.R0.S16: Preamble found at Latency = 008
N6.C3.D1.R0.S01: Total Receive Enable Delay = 1345
N0.C3.D1.R0.S08: Preamble found at Latency = 007
N2.C0.D0.R0.S10: Dq Delay estimate: 445
N4.C3.D1.R0.S09: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N6.C3.D1.R0.S02: Total Receive Enable Delay = 1318
N0.C3.D1.R0.S00: Total Receive Enable Delay = 1360
N2.C0.D0.R0.S11: Dq Delay estimate: 435
N4.C3.D1.R0.S10: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N6.C3.D1.R0.S03: Total Receive Enable Delay = 1293
N0.C3.D1.R0.S01: Total Receive Enable Delay = 1342
N2.C0.D0.R0.S12: Dq Delay estimate: 418
N4.C3.D1.R0.S11: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N6.C3.D1.R0.S04: Total Receive Enable Delay = 1287
N0.C3.D1.R0.S02: Total Receive Enable Delay = 1309
N2.C0.D0.R0.S13: Dq Delay estimate: 387
N4.C3.D1.R0.S12: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N6.C3.D1.R0.S05: Total Receive Enable Delay = 1318
N0.C3.D1.R0.S03: Total Receive Enable Delay = 1286
N2.C0.D0.R0.S14: Dq Delay estimate: 403
N4.C3.D1.R0.S13: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N6.C3.D1.R0.S06: Total Receive Enable Delay = 1336
N0.C3.D1.R0.S04: Total Receive Enable Delay = 1283
N2.C0.D0.R0.S15: Dq Delay estimate: 406
N4.C3.D1.R0.S14: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N6.C3.D1.R0.S07: Total Receive Enable Delay = 1359
N0.C3.D1.R0.S05: Total Receive Enable Delay = 1307
N2.C0.D0.R0.S16: Dq Delay estimate: 419
N4.C3.D1.R0.S15: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N6.C3.D1.R0.S08: Total Receive Enable Delay = 1275
N0.C3.D1.R0.S06: Total Receive Enable Delay = 1330
N2.C0.D0.R0.S17: Dq Delay estimate: 397
N4.C3.D1.R0.S16: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N6.C3.D1.R0: Starting preamble search upper nibbles
N0.C3.D1.R0.S07: Total Receive Enable Delay = 1354
ACCM: F0 F0F0F0F0 F0F0F0F0
N4.C3.D1.R0.S17: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N6.C3.D1.R0.S09: PI = 051, PtrOffset = 004
N0.C3.D1.R0.S08: Total Receive Enable Delay = 1270
ACCM: F0 F0F0F0F0 F0F0F0F0
N4.C3.D1.R0.S11: Preamble found at Latency = 007
N6.C3.D1.R0.S10: PI = 032, PtrOffset = 004
N0.C3.D1.R0: Starting preamble search upper nibbles
ACCM: F0 F0F0F0F0 F0F0F0F0
N4.C3.D1.R0.S12: Preamble found at Latency = 007
N6.C3.D1.R0.S11: PI = 005, PtrOffset = 004
N0.C3.D1.R0.S09: PI = 047, PtrOffset = 004
ACCM: F0 F0F0F0F0 F0F0F0F0
N4.C3.D1.R0.S13: Preamble found at Latency = 007
N6.C3.D1.R0.S12: PI = 046, PtrOffset = 005
N0.C3.D1.R0.S10: PI = 028, PtrOffset = 004
N2.C0.D0.R0: CheckMCTest: result = 0x3FE00
N4.C3.D1.R0.S14: Preamble found at Latency = 007
N6.C3.D1.R0.S13: PI = 040, PtrOffset = 005
N0.C3.D1.R0.S11: PI = 000, PtrOffset = 004
ACCM: F0 F0F0F0F0 F0F0F0F0
N4.C3.D1.R0.S17: Preamble found at Latency = 007
N6.C3.D1.R0.S14: PI = 006, PtrOffset = 004
N0.C3.D1.R0.S12: PI = 041, PtrOffset = 005
ACCM: F0 F0F0F0F0 F0F0F0F0
N4.C3.D1.R0: Preamble found for all upper nibbles, adjusting Pi, Offset to center into preamble
N6.C3.D1.R0.S15: PI = 024, PtrOffset = 004
N0.C3.D1.R0.S13: PI = 032, PtrOffset = 005
ACCM: F0 F0F0F0F0 F0F0F0F0
N4.C3.D1.R0.S09: Total Receive Enable Delay = 1360
N6.C3.D1.R0.S16: PI = 048, PtrOffset = 004
N0.C3.D1.R0.S14: PI = 060, PtrOffset = 005
ACCM: F0 F0F0F0F0 F0F0F0F0
N4.C3.D1.R0.S10: Total Receive Enable Delay = 1337
N6.C3.D1.R0.S17: PI = 025, PtrOffset = 005
N0.C3.D1.R0.S15: PI = 020, PtrOffset = 004
N2.C0.D0.R0: CheckMCTest: result = 0x3FE00
N4.C3.D1.R0.S11: Total Receive Enable Delay = 1310
N6.C3.D1.R0.S09: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N0.C3.D1.R0.S16: PI = 045, PtrOffset = 004
ACCM: F0 F0F0F0F0 F0F0F0F0
N4.C3.D1.R0.S12: Total Receive Enable Delay = 1291
N6.C3.D1.R0.S10: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N0.C3.D1.R0.S17: PI = 020, PtrOffset = 005
ACCM: F0 F0F0F0F0 F0F0F0F0
N4.C3.D1.R0.S13: Total Receive Enable Delay = 1283
N6.C3.D1.R0.S11: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N0.C3.D1.R0.S09: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
ACCM: 00 00B00000 B0000000
N4.C3.D1.R0.S14: Total Receive Enable Delay = 1311
N6.C3.D1.R0.S12: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N0.C3.D1.R0.S10: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
ACCM: 00 00B00000 B0000000
N4.C3.D1.R0.S15: Total Receive Enable Delay = 1332
N6.C3.D1.R0.S13: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N0.C3.D1.R0.S11: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N2.C0.D0.R0: CheckMCTest: result = 0x3FE00
N4.C3.D1.R0.S16: Total Receive Enable Delay = 1355
N6.C3.D1.R0.S14: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N0.C3.D1.R0.S12: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
ACCM: F0 F0F0F0F0 F0F0F0F0
N4.C3.D1.R0.S17: Total Receive Enable Delay = 1271
N6.C3.D1.R0.S15: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N0.C3.D1.R0.S13: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
ACCM: F0 F0F0F0F0 F0F0F0F0
N4.C3.D1.R1: RcvEnFine: Initial RdCmd2RcvEnLatency = 10, Initial RdPtrOffsetRcvEn = 4
N6.C3.D1.R0.S16: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N0.C3.D1.R0.S14: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
ACCM: 00 00F00000 F0000000
N4.C3.D1.R1.S00: Rcv En Fine Value = 304
N6.C3.D1.R0.S17: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N0.C3.D1.R0.S15: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
ACCM: 00 00F00000 F0000000
N4.C3.D1.R1.S01: Rcv En Fine Value = 283
N6.C3.D1.R0.S09: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N0.C3.D1.R0.S16: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N2.C0.D0.R0: CheckMCTest: result = 0x3FE00
N4.C3.D1.R1.S02: Rcv En Fine Value = 380
N6.C3.D1.R0.S10: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N0.C3.D1.R0.S17: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N2.C0.D0.R0: CheckMCTest: passed
N4.C3.D1.R1.S03: Rcv En Fine Value = 361
N6.C3.D1.R0.S11: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N0.C3.D1.R0.S09: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N2.C0.D0.R0: CheckMCTest: passed
N4.C3.D1.R1.S04: Rcv En Fine Value = 355
N6.C3.D1.R0.S12: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N0.C3.D1.R0.S10: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N2.C0.D0.R0.S09: Offset Found: RdPtrOffsetDqs = 007
N4.C3.D1.R1.S05: Rcv En Fine Value = 379
N6.C3.D1.R0.S13: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N0.C3.D1.R0.S11: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N2.C0.D0.R0.S10: Offset Found: RdPtrOffsetDqs = 007
N4.C3.D1.R1.S06: Rcv En Fine Value = 277
N6.C3.D1.R0.S14: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N0.C3.D1.R0.S12: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N2.C0.D0.R0.S11: Offset Found: RdPtrOffsetDqs = 007
N4.C3.D1.R1.S07: Rcv En Fine Value = 298
N6.C3.D1.R0.S15: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N0.C3.D1.R0.S13: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N2.C0.D0.R0.S12: Offset Found: RdPtrOffsetDqs = 007
N4.C3.D1.R1.S08: Rcv En Fine Value = 338
N6.C3.D1.R0.S16: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N0.C3.D1.R0.S14: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N2.C0.D0.R0.S13: Offset Found: RdPtrOffsetDqs = 006
N4.C3.D1.R1.S09: Rcv En Fine Value = 306
N6.C3.D1.R0.S17: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N0.C3.D1.R0.S15: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N2.C0.D0.R0.S14: Offset Found: RdPtrOffsetDqs = 006
N4.C3.D1.R1.S10: Rcv En Fine Value = 283
N6.C3.D1.R0.S09: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N0.C3.D1.R0.S16: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N2.C0.D0.R0.S15: Offset Found: RdPtrOffsetDqs = 006
N4.C3.D1.R1.S11: Rcv En Fine Value = 257
N6.C3.D1.R0.S10: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N0.C3.D1.R0.S17: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N2.C0.D0.R0.S16: Offset Found: RdPtrOffsetDqs = 007
N4.C3.D1.R1.S12: Rcv En Fine Value = 364
N6.C3.D1.R0.S11: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N0.C3.D1.R0.S09: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N2.C0.D0.R0.S17: Offset Found: RdPtrOffsetDqs = 006
N4.C3.D1.R1.S13: Rcv En Fine Value = 355
N6.C3.D1.R0.S12: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N0.C3.D1.R0.S10: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N2.C0.D0.R1: Write Training Coarse, lower nibbles / bytes
N4.C3.D1.R1.S14: Rcv En Fine Value = 379
N6.C3.D1.R0.S13: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N0.C3.D1.R0.S11: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N2.C0.D0.R1.S00: Dq Delay estimate: 461
N4.C3.D1.R1.S15: Rcv En Fine Value = 277
N6.C3.D1.R0.S14: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N0.C3.D1.R0.S12: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N2.C0.D0.R1.S01: Dq Delay estimate: 441
N4.C3.D1.R1.S16: Rcv En Fine Value = 299
N6.C3.D1.R0.S15: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N0.C3.D1.R0.S13: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N2.C0.D0.R1.S02: Dq Delay estimate: 428
N4.C3.D1.R1.S17: Rcv En Fine Value = 343
N6.C3.D1.R0.S16: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N0.C3.D1.R0.S14: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N2.C0.D0.R1.S03: Dq Delay estimate: 409
N4.C3.D1.R1: Starting preamble search lower nibbles
N6.C3.D1.R0.S17: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N0.C3.D1.R0.S15: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N2.C0.D0.R1.S04: Dq Delay estimate: 376
N4.C3.D1.R1.S00: PI = 048, PtrOffset = 004
N6.C3.D1.R0.S09: Preamble found at Latency = 008
N0.C3.D1.R0.S16: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N2.C0.D0.R1.S05: Dq Delay estimate: 394
N4.C3.D1.R1.S01: PI = 027, PtrOffset = 004
N6.C3.D1.R0.S10: Preamble found at Latency = 008
N0.C3.D1.R0.S17: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N2.C0.D0.R1.S06: Dq Delay estimate: 400
N4.C3.D1.R1.S02: PI = 060, PtrOffset = 005
N6.C3.D1.R0.S11: Preamble found at Latency = 008
N0.C3.D1.R0.S09: Preamble found at Latency = 008
N2.C0.D0.R1.S07: Dq Delay estimate: 414
N4.C3.D1.R1.S03: PI = 041, PtrOffset = 005
N6.C3.D1.R0.S14: Preamble found at Latency = 008
N0.C3.D1.R0.S10: Preamble found at Latency = 008
N2.C0.D0.R1.S08: Dq Delay estimate: 386
N4.C3.D1.R1.S04: PI = 035, PtrOffset = 005
N6.C3.D1.R0.S15: Preamble found at Latency = 008
N0.C3.D1.R0.S11: Preamble found at Latency = 008
ACCM: 0F 0F0F0F0F 0F0F0F0F
N4.C3.D1.R1.S05: PI = 059, PtrOffset = 005
N6.C3.D1.R0.S16: Preamble found at Latency = 008
N0.C3.D1.R0.S15: Preamble found at Latency = 008
ACCM: 0F 0F0F0F0F 0F0F0F0F
N4.C3.D1.R1.S06: PI = 021, PtrOffset = 004
N6.C3.D1.R0.S09: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N0.C3.D1.R0.S16: Preamble found at Latency = 008
ACCM: 0F 0F0F0F0F 0F0F0F0F
N4.C3.D1.R1.S07: PI = 042, PtrOffset = 004
N6.C3.D1.R0.S10: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N0.C3.D1.R0.S09: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
ACCM: 0F 0F0F0F0F 0F0F0F0F
N4.C3.D1.R1.S08: PI = 018, PtrOffset = 005
N6.C3.D1.R0.S11: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N0.C3.D1.R0.S10: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N2.C0.D0.R1: CheckMCTest: result = 0x1FF
N4.C3.D1.R1.S00: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N6.C3.D1.R0.S12: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N0.C3.D1.R0.S11: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
ACCM: 0F 0F0F0F0F 0F0F0F0F
N4.C3.D1.R1.S01: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N6.C3.D1.R0.S13: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N0.C3.D1.R0.S12: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
ACCM: 0F 0F0F0F0F 0F0F0F0F
N4.C3.D1.R1.S02: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N6.C3.D1.R0.S14: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N0.C3.D1.R0.S13: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
ACCM: 0F 0F0F0F0F 0F0F0F0F
N4.C3.D1.R1.S03: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N6.C3.D1.R0.S15: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N0.C3.D1.R0.S14: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
ACCM: 0F 0F0F0F0F 0F0F0F0F
N4.C3.D1.R1.S04: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N6.C3.D1.R0.S16: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N0.C3.D1.R0.S15: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N2.C0.D0.R1: CheckMCTest: result = 0x1FF
N4.C3.D1.R1.S05: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N6.C3.D1.R0.S17: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N0.C3.D1.R0.S16: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
ACCM: 0F 0F0F0F0F 0F0F0F0F
N4.C3.D1.R1.S06: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N6.C3.D1.R0.S12: Preamble found at Latency = 007
N0.C3.D1.R0.S17: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
ACCM: 0F 0F0F0F0F 0F0F0F0F
N4.C3.D1.R1.S07: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N6.C3.D1.R0.S13: Preamble found at Latency = 007
N0.C3.D1.R0.S12: Preamble found at Latency = 007
ACCM: 00 0000000B 00000B00
N4.C3.D1.R1.S08: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N6.C3.D1.R0.S17: Preamble found at Latency = 007
N0.C3.D1.R0.S13: Preamble found at Latency = 007
ACCM: 00 0000000B 00000B00
N4.C3.D1.R1.S00: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N6.C3.D1.R0: Preamble found for all upper nibbles, adjusting Pi, Offset to center into preamble
N0.C3.D1.R0.S14: Preamble found at Latency = 007
N2.C0.D0.R1: CheckMCTest: result = 0x1FF
N4.C3.D1.R1.S01: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N6.C3.D1.R0.S09: Total Receive Enable Delay = 1363
N0.C3.D1.R0.S17: Preamble found at Latency = 007
ACCM: 0F 0F0F0F0F 0F0F0F0F
N4.C3.D1.R1.S02: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N6.C3.D1.R0.S10: Total Receive Enable Delay = 1344
N0.C3.D1.R0: Preamble found for all upper nibbles, adjusting Pi, Offset to center into preamble
ACCM: 0F 0F0F0F0F 0F0F0F0F
N4.C3.D1.R1.S03: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N6.C3.D1.R0.S11: Total Receive Enable Delay = 1317
N0.C3.D1.R0.S09: Total Receive Enable Delay = 1359
ACCM: 00 0000000B 00000F00
N4.C3.D1.R1.S04: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N6.C3.D1.R0.S12: Total Receive Enable Delay = 1294
N0.C3.D1.R0.S10: Total Receive Enable Delay = 1340
ACCM: 00 0000000B 00000F00
N4.C3.D1.R1.S05: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N6.C3.D1.R0.S13: Total Receive Enable Delay = 1288
N0.C3.D1.R0.S11: Total Receive Enable Delay = 1312
N2.C0.D0.R1: CheckMCTest: result = 0x1FF
N4.C3.D1.R1.S06: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N6.C3.D1.R0.S14: Total Receive Enable Delay = 1318
N0.C3.D1.R0.S12: Total Receive Enable Delay = 1289
N2.C0.D0.R1: CheckMCTest: passed
N4.C3.D1.R1.S07: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N6.C3.D1.R0.S15: Total Receive Enable Delay = 1336
N0.C3.D1.R0.S13: Total Receive Enable Delay = 1280
N2.C0.D0.R1: CheckMCTest: passed
N4.C3.D1.R1.S08: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N6.C3.D1.R0.S16: Total Receive Enable Delay = 1360
N0.C3.D1.R0.S14: Total Receive Enable Delay = 1308
N2.C0.D0.R1.S00: Offset Found: RdPtrOffsetDqs = 007
N4.C3.D1.R1.S00: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N6.C3.D1.R0.S17: Total Receive Enable Delay = 1273
N0.C3.D1.R0.S15: Total Receive Enable Delay = 1332
N2.C0.D0.R1.S01: Offset Found: RdPtrOffsetDqs = 007
N4.C3.D1.R1.S01: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N6.C3.D1.R1: RcvEnFine: Initial RdCmd2RcvEnLatency = 10, Initial RdPtrOffsetRcvEn = 4
N0.C3.D1.R0.S16: Total Receive Enable Delay = 1357
N2.C0.D0.R1.S02: Offset Found: RdPtrOffsetDqs = 007
N4.C3.D1.R1.S02: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N6.C3.D1.R1.S00: Rcv En Fine Value = 311
N0.C3.D1.R0.S17: Total Receive Enable Delay = 1268
N2.C0.D0.R1.S03: Offset Found: RdPtrOffsetDqs = 006
N4.C3.D1.R1.S03: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N6.C3.D1.R1.S01: Rcv En Fine Value = 288
N0.C3.D1.R1: RcvEnFine: Initial RdCmd2RcvEnLatency = 10, Initial RdPtrOffsetRcvEn = 4
N2.C0.D0.R1.S04: Offset Found: RdPtrOffsetDqs = 006
N4.C3.D1.R1.S04: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N6.C3.D1.R1.S02: Rcv En Fine Value = 260
N0.C3.D1.R1.S00: Rcv En Fine Value = 302
N2.C0.D0.R1.S05: Offset Found: RdPtrOffsetDqs = 006
N4.C3.D1.R1.S05: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N6.C3.D1.R1.S03: Rcv En Fine Value = 365
N0.C3.D1.R1.S01: Rcv En Fine Value = 282
N2.C0.D0.R1.S06: Offset Found: RdPtrOffsetDqs = 006
N4.C3.D1.R1.S06: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N6.C3.D1.R1.S04: Rcv En Fine Value = 358
N0.C3.D1.R1.S02: Rcv En Fine Value = 381
N2.C0.D0.R1.S07: Offset Found: RdPtrOffsetDqs = 007
N4.C3.D1.R1.S07: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N6.C3.D1.R1.S05: Rcv En Fine Value = 258
N0.C3.D1.R1.S03: Rcv En Fine Value = 358
N2.C0.D0.R1.S08: Offset Found: RdPtrOffsetDqs = 006
N4.C3.D1.R1.S08: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N6.C3.D1.R1.S06: Rcv En Fine Value = 282
N0.C3.D1.R1.S04: Rcv En Fine Value = 352
N2.C0.D0.R1: Write Training Coarse, upper nibbles
N4.C3.D1.R1.S00: Preamble found at Latency = 008
N6.C3.D1.R1.S07: Rcv En Fine Value = 301
N0.C3.D1.R1.S05: Rcv En Fine Value = 378
N2.C0.D0.R1.S09: Dq Delay estimate: 457
N4.C3.D1.R1.S01: Preamble found at Latency = 008
N6.C3.D1.R1.S08: Rcv En Fine Value = 346
N0.C3.D1.R1.S06: Rcv En Fine Value = 274
N2.C0.D0.R1.S10: Dq Delay estimate: 439
N4.C3.D1.R1.S06: Preamble found at Latency = 008
N6.C3.D1.R1.S09: Rcv En Fine Value = 305
N0.C3.D1.R1.S07: Rcv En Fine Value = 296
N2.C0.D0.R1.S11: Dq Delay estimate: 430
N4.C3.D1.R1.S07: Preamble found at Latency = 008
N6.C3.D1.R1.S10: Rcv En Fine Value = 288
N0.C3.D1.R1.S08: Rcv En Fine Value = 341
N2.C0.D0.R1.S12: Dq Delay estimate: 414
N4.C3.D1.R1.S00: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N6.C3.D1.R1.S11: Rcv En Fine Value = 261
N0.C3.D1.R1.S09: Rcv En Fine Value = 302
N2.C0.D0.R1.S13: Dq Delay estimate: 378
N4.C3.D1.R1.S01: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N6.C3.D1.R1.S12: Rcv En Fine Value = 365
N0.C3.D1.R1.S10: Rcv En Fine Value = 285
N2.C0.D0.R1.S14: Dq Delay estimate: 396
N4.C3.D1.R1.S02: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N6.C3.D1.R1.S13: Rcv En Fine Value = 359
N0.C3.D1.R1.S11: Rcv En Fine Value = 380
N2.C0.D0.R1.S15: Dq Delay estimate: 400
N4.C3.D1.R1.S03: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N6.C3.D1.R1.S14: Rcv En Fine Value = 262
N0.C3.D1.R1.S12: Rcv En Fine Value = 361
N2.C0.D0.R1.S16: Dq Delay estimate: 415
N4.C3.D1.R1.S04: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N6.C3.D1.R1.S15: Rcv En Fine Value = 284
N0.C3.D1.R1.S13: Rcv En Fine Value = 353
N2.C0.D0.R1.S17: Dq Delay estimate: 389
N4.C3.D1.R1.S05: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N6.C3.D1.R1.S16: Rcv En Fine Value = 303
N0.C3.D1.R1.S14: Rcv En Fine Value = 379
ACCM: F0 F0F0F0F0 F0F0F0F0
N4.C3.D1.R1.S06: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N6.C3.D1.R1.S17: Rcv En Fine Value = 346
N0.C3.D1.R1.S15: Rcv En Fine Value = 276
ACCM: F0 F0F0F0F0 F0F0F0F0
N4.C3.D1.R1.S07: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N6.C3.D1.R1: Starting preamble search lower nibbles
N0.C3.D1.R1.S16: Rcv En Fine Value = 302
ACCM: F0 F0F0F0F0 F0F0F0F0
N4.C3.D1.R1.S08: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N6.C3.D1.R1.S00: PI = 055, PtrOffset = 004
N0.C3.D1.R1.S17: Rcv En Fine Value = 338
ACCM: F0 F0F0F0F0 F0F0F0F0
N4.C3.D1.R1.S02: Preamble found at Latency = 007
N6.C3.D1.R1.S01: PI = 032, PtrOffset = 004
N0.C3.D1.R1: Starting preamble search lower nibbles
N2.C0.D0.R1: CheckMCTest: result = 0x3FE00
N4.C3.D1.R1.S03: Preamble found at Latency = 007
N6.C3.D1.R1.S02: PI = 004, PtrOffset = 004
N0.C3.D1.R1.S00: PI = 046, PtrOffset = 004
ACCM: F0 F0F0F0F0 F0F0F0F0
N4.C3.D1.R1.S04: Preamble found at Latency = 007
N6.C3.D1.R1.S03: PI = 045, PtrOffset = 005
N0.C3.D1.R1.S01: PI = 026, PtrOffset = 004
ACCM: F0 F0F0F0F0 F0F0F0F0
N4.C3.D1.R1.S05: Preamble found at Latency = 007
N6.C3.D1.R1.S04: PI = 038, PtrOffset = 005
N0.C3.D1.R1.S02: PI = 061, PtrOffset = 005
ACCM: F0 F0F0F0F0 F0F0F0F0
N4.C3.D1.R1.S08: Preamble found at Latency = 007
N6.C3.D1.R1.S05: PI = 002, PtrOffset = 004
N0.C3.D1.R1.S03: PI = 038, PtrOffset = 005
ACCM: F0 F0F0F0F0 F0F0F0F0
N4.C3.D1.R1.S00: Total Receive Enable Delay = 1360
N6.C3.D1.R1.S06: PI = 026, PtrOffset = 004
N0.C3.D1.R1.S04: PI = 032, PtrOffset = 005
N2.C0.D0.R1: CheckMCTest: result = 0x3FE00
N4.C3.D1.R1.S01: Total Receive Enable Delay = 1339
N6.C3.D1.R1.S07: PI = 045, PtrOffset = 004
N0.C3.D1.R1.S05: PI = 058, PtrOffset = 005
ACCM: F0 F0F0F0F0 F0F0F0F0
N4.C3.D1.R1.S02: Total Receive Enable Delay = 1308
N6.C3.D1.R1.S08: PI = 026, PtrOffset = 005
N0.C3.D1.R1.S06: PI = 018, PtrOffset = 004
ACCM: F0 F0F0F0F0 F0F0F0F0
N4.C3.D1.R1.S03: Total Receive Enable Delay = 1289
N6.C3.D1.R1.S00: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N0.C3.D1.R1.S07: PI = 040, PtrOffset = 004
ACCM: 00 000000B0 00000000
N4.C3.D1.R1.S04: Total Receive Enable Delay = 1283
N6.C3.D1.R1.S01: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N0.C3.D1.R1.S08: PI = 021, PtrOffset = 005
ACCM: 00 000000B0 00000000
N4.C3.D1.R1.S05: Total Receive Enable Delay = 1307
N6.C3.D1.R1.S02: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N0.C3.D1.R1.S00: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N2.C0.D0.R1: CheckMCTest: result = 0x3FE00
N4.C3.D1.R1.S06: Total Receive Enable Delay = 1333
N6.C3.D1.R1.S03: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N0.C3.D1.R1.S01: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
ACCM: F0 F0F0F0F0 F0F0F0F0
N4.C3.D1.R1.S07: Total Receive Enable Delay = 1354
N6.C3.D1.R1.S04: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N0.C3.D1.R1.S02: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
ACCM: F0 F0F0F0F0 F0F0F0F0
N4.C3.D1.R1.S08: Total Receive Enable Delay = 1266
N6.C3.D1.R1.S05: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N0.C3.D1.R1.S03: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
ACCM: 00 000000B0 00000000
N4.C3.D1.R1: Starting preamble search upper nibbles
N6.C3.D1.R1.S06: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N0.C3.D1.R1.S04: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
ACCM: 00 000000B0 00000000
N4.C3.D1.R1.S09: PI = 050, PtrOffset = 004
N6.C3.D1.R1.S07: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N0.C3.D1.R1.S05: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N2.C0.D0.R1: CheckMCTest: result = 0x3FE00
N4.C3.D1.R1.S10: PI = 027, PtrOffset = 004
N6.C3.D1.R1.S08: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N0.C3.D1.R1.S06: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N2.C0.D0.R1: CheckMCTest: passed
N4.C3.D1.R1.S11: PI = 001, PtrOffset = 004
N6.C3.D1.R1.S00: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N0.C3.D1.R1.S07: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N2.C0.D0.R1: CheckMCTest: passed
N4.C3.D1.R1.S12: PI = 044, PtrOffset = 005
N6.C3.D1.R1.S01: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N0.C3.D1.R1.S08: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N2.C0.D0.R1.S09: Offset Found: RdPtrOffsetDqs = 007
N4.C3.D1.R1.S13: PI = 035, PtrOffset = 005
N6.C3.D1.R1.S02: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N0.C3.D1.R1.S00: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N2.C0.D0.R1.S10: Offset Found: RdPtrOffsetDqs = 007
N4.C3.D1.R1.S14: PI = 059, PtrOffset = 005
N6.C3.D1.R1.S03: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N0.C3.D1.R1.S01: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N2.C0.D0.R1.S11: Offset Found: RdPtrOffsetDqs = 007
N4.C3.D1.R1.S15: PI = 021, PtrOffset = 004
N6.C3.D1.R1.S04: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N0.C3.D1.R1.S02: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N2.C0.D0.R1.S12: Offset Found: RdPtrOffsetDqs = 007
N4.C3.D1.R1.S16: PI = 043, PtrOffset = 004
N6.C3.D1.R1.S05: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N0.C3.D1.R1.S03: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N2.C0.D0.R1.S13: Offset Found: RdPtrOffsetDqs = 006
N4.C3.D1.R1.S17: PI = 023, PtrOffset = 005
N6.C3.D1.R1.S06: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N0.C3.D1.R1.S04: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N2.C0.D0.R1.S14: Offset Found: RdPtrOffsetDqs = 006
N4.C3.D1.R1.S09: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N6.C3.D1.R1.S07: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N0.C3.D1.R1.S05: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N2.C0.D0.R1.S15: Offset Found: RdPtrOffsetDqs = 006
N4.C3.D1.R1.S10: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N6.C3.D1.R1.S08: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N0.C3.D1.R1.S06: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N2.C0.D0.R1.S16: Offset Found: RdPtrOffsetDqs = 007
N4.C3.D1.R1.S11: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N6.C3.D1.R1.S00: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N0.C3.D1.R1.S07: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N2.C0.D0.R1.S17: Offset Found: RdPtrOffsetDqs = 006
N4.C3.D1.R1.S12: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N6.C3.D1.R1.S01: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N0.C3.D1.R1.S08: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N2.C0.D1.R0: Write Training Coarse, lower nibbles / bytes
N4.C3.D1.R1.S13: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N6.C3.D1.R1.S02: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N0.C3.D1.R1.S00: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N2.C0.D1.R0.S00: Dq Delay estimate: 469
N4.C3.D1.R1.S14: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N6.C3.D1.R1.S03: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N0.C3.D1.R1.S01: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N2.C0.D1.R0.S01: Dq Delay estimate: 450
N4.C3.D1.R1.S15: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N6.C3.D1.R1.S04: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N0.C3.D1.R1.S02: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N2.C0.D1.R0.S02: Dq Delay estimate: 439
N4.C3.D1.R1.S16: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N6.C3.D1.R1.S05: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N0.C3.D1.R1.S03: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N2.C0.D1.R0.S03: Dq Delay estimate: 422
N4.C3.D1.R1.S17: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N6.C3.D1.R1.S06: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N0.C3.D1.R1.S04: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N2.C0.D1.R0.S04: Dq Delay estimate: 389
N4.C3.D1.R1.S09: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N6.C3.D1.R1.S07: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N0.C3.D1.R1.S05: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N2.C0.D1.R0.S05: Dq Delay estimate: 408
N4.C3.D1.R1.S10: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N6.C3.D1.R1.S08: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N0.C3.D1.R1.S06: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N2.C0.D1.R0.S06: Dq Delay estimate: 409
N4.C3.D1.R1.S11: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N6.C3.D1.R1.S00: Preamble found at Latency = 008
N0.C3.D1.R1.S07: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N2.C0.D1.R0.S07: Dq Delay estimate: 426
N4.C3.D1.R1.S12: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N6.C3.D1.R1.S01: Preamble found at Latency = 008
N0.C3.D1.R1.S08: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N2.C0.D1.R0.S08: Dq Delay estimate: 395
N4.C3.D1.R1.S13: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N6.C3.D1.R1.S02: Preamble found at Latency = 008
N0.C3.D1.R1.S00: Preamble found at Latency = 008
ACCM: 0F 0F0F0F0F 0F0F0F0F
N4.C3.D1.R1.S14: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N6.C3.D1.R1.S05: Preamble found at Latency = 008
N0.C3.D1.R1.S01: Preamble found at Latency = 008
ACCM: 0F 0F0F0F0F 0F0F0F0F
N4.C3.D1.R1.S15: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N6.C3.D1.R1.S06: Preamble found at Latency = 008
N0.C3.D1.R1.S06: Preamble found at Latency = 008
ACCM: 0F 0F0F0F0F 0F0F0F0F
N4.C3.D1.R1.S16: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N6.C3.D1.R1.S07: Preamble found at Latency = 008
N0.C3.D1.R1.S07: Preamble found at Latency = 008
ACCM: 0F FF0F0FFF FFFFFF0F
N4.C3.D1.R1.S17: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N6.C3.D1.R1.S00: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N0.C3.D1.R1.S00: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N2.C0.D1.R0: CheckMCTest: result = 0x13DFF
N4.C3.D1.R1.S09: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N6.C3.D1.R1.S01: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N0.C3.D1.R1.S01: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
ACCM: 0F 0F0F0F0F 0F0F0F0F
N4.C3.D1.R1.S10: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N6.C3.D1.R1.S02: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N0.C3.D1.R1.S02: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
ACCM: 0F 0F0F0F0F 0F0F0F0F
N4.C3.D1.R1.S11: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N6.C3.D1.R1.S03: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N0.C3.D1.R1.S03: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
ACCM: 0F 0F0F0F0F 0F0F0F0F
N4.C3.D1.R1.S12: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N6.C3.D1.R1.S04: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N0.C3.D1.R1.S04: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
ACCM: 0F FF0F0FFF FFFFFF0F
N4.C3.D1.R1.S13: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N6.C3.D1.R1.S05: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N0.C3.D1.R1.S05: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N2.C0.D1.R0: CheckMCTest: result = 0x13DFF
N4.C3.D1.R1.S14: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N6.C3.D1.R1.S06: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N0.C3.D1.R1.S06: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
ACCM: 0F 0F0F0F0F 0F0F0F0F
N4.C3.D1.R1.S15: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N6.C3.D1.R1.S07: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N0.C3.D1.R1.S07: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
ACCM: 0F 0F0F0F0F 0F0F0F0F
N4.C3.D1.R1.S16: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N6.C3.D1.R1.S08: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N0.C3.D1.R1.S08: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
ACCM: 00 0B0B0000 0000000B
N4.C3.D1.R1.S17: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N6.C3.D1.R1.S03: Preamble found at Latency = 007
N0.C3.D1.R1.S02: Preamble found at Latency = 007
ACCM: 00 FB0B00F0 F0F0F00B
N4.C3.D1.R1.S09: Preamble found at Latency = 008
N6.C3.D1.R1.S04: Preamble found at Latency = 007
N0.C3.D1.R1.S03: Preamble found at Latency = 007
N2.C0.D1.R0: CheckMCTest: result = 0x13DFF
N4.C3.D1.R1.S10: Preamble found at Latency = 008
N6.C3.D1.R1.S08: Preamble found at Latency = 007
N0.C3.D1.R1.S04: Preamble found at Latency = 007
ACCM: 0F 0F0F0F0F 0F0F0F0F
N4.C3.D1.R1.S11: Preamble found at Latency = 008
N6.C3.D1.R1.S00: Total Receive Enable Delay = 1367
N0.C3.D1.R1.S05: Preamble found at Latency = 007
ACCM: 0F 0F0F0F0F 0F0F0F0F
N4.C3.D1.R1.S15: Preamble found at Latency = 008
N6.C3.D1.R1.S01: Total Receive Enable Delay = 1344
N0.C3.D1.R1.S08: Preamble found at Latency = 007
ACCM: 00 0F0F000D 0000000F
N4.C3.D1.R1.S16: Preamble found at Latency = 008
N6.C3.D1.R1.S02: Total Receive Enable Delay = 1316
N0.C3.D1.R1.S00: Total Receive Enable Delay = 1358
ACCM: 00 FF0F00FD F0F0F00F
N4.C3.D1.R1.S09: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N6.C3.D1.R1.S03: Total Receive Enable Delay = 1293
N0.C3.D1.R1.S01: Total Receive Enable Delay = 1338
N2.C0.D1.R0: CheckMCTest: result = 0x13DFF
N4.C3.D1.R1.S10: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N6.C3.D1.R1.S04: Total Receive Enable Delay = 1286
N0.C3.D1.R1.S02: Total Receive Enable Delay = 1309
ACCM: 00 00000000 00000000
N4.C3.D1.R1.S11: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N6.C3.D1.R1.S05: Total Receive Enable Delay = 1314
N0.C3.D1.R1.S03: Total Receive Enable Delay = 1286
ACCM: 00 00000000 00000000
N4.C3.D1.R1.S12: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N6.C3.D1.R1.S06: Total Receive Enable Delay = 1338
N0.C3.D1.R1.S04: Total Receive Enable Delay = 1280
ACCM: 00 00000000 00000000
N4.C3.D1.R1.S13: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N6.C3.D1.R1.S07: Total Receive Enable Delay = 1357
N0.C3.D1.R1.S05: Total Receive Enable Delay = 1306
ACCM: 00 F00000F0 F0F0F000
N4.C3.D1.R1.S14: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N6.C3.D1.R1.S08: Total Receive Enable Delay = 1274
N0.C3.D1.R1.S06: Total Receive Enable Delay = 1330
N2.C0.D1.R0: CheckMCTest: result = 0x13C00
N4.C3.D1.R1.S15: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N6.C3.D1.R1: Starting preamble search upper nibbles
N0.C3.D1.R1.S07: Total Receive Enable Delay = 1352
ACCM: 00 00000000 00000000
N4.C3.D1.R1.S16: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N6.C3.D1.R1.S09: PI = 049, PtrOffset = 004
N0.C3.D1.R1.S08: Total Receive Enable Delay = 1269
ACCM: 00 00000000 00000000
N4.C3.D1.R1.S17: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N6.C3.D1.R1.S10: PI = 032, PtrOffset = 004
N0.C3.D1.R1: Starting preamble search upper nibbles
ACCM: 00 00000000 00000000
N4.C3.D1.R1.S12: Preamble found at Latency = 007
N6.C3.D1.R1.S11: PI = 005, PtrOffset = 004
N0.C3.D1.R1.S09: PI = 046, PtrOffset = 004
ACCM: 00 F00000F0 F0F0F000
N4.C3.D1.R1.S13: Preamble found at Latency = 007
N6.C3.D1.R1.S12: PI = 045, PtrOffset = 005
N0.C3.D1.R1.S10: PI = 029, PtrOffset = 004
N2.C0.D1.R0: CheckMCTest: result = 0x13C00
N4.C3.D1.R1.S14: Preamble found at Latency = 007
N6.C3.D1.R1.S13: PI = 039, PtrOffset = 005
N0.C3.D1.R1.S11: PI = 060, PtrOffset = 005
N2.C0.D1.R0.S00: Offset Found: RdPtrOffsetDqs = 007
N4.C3.D1.R1.S17: Preamble found at Latency = 007
N6.C3.D1.R1.S14: PI = 006, PtrOffset = 004
N0.C3.D1.R1.S12: PI = 041, PtrOffset = 005
N2.C0.D1.R0.S01: Offset Found: RdPtrOffsetDqs = 007
N4.C3.D1.R1: Preamble found for all upper nibbles, adjusting Pi, Offset to center into preamble
N6.C3.D1.R1.S15: PI = 028, PtrOffset = 004
N0.C3.D1.R1.S13: PI = 033, PtrOffset = 005
N2.C0.D1.R0.S02: Offset Found: RdPtrOffsetDqs = 007
N4.C3.D1.R1.S09: Total Receive Enable Delay = 1362
N6.C3.D1.R1.S16: PI = 047, PtrOffset = 004
N0.C3.D1.R1.S14: PI = 059, PtrOffset = 005
N2.C0.D1.R0.S03: Offset Found: RdPtrOffsetDqs = 007
N4.C3.D1.R1.S10: Total Receive Enable Delay = 1339
N6.C3.D1.R1.S17: PI = 026, PtrOffset = 005
N0.C3.D1.R1.S15: PI = 020, PtrOffset = 004
N2.C0.D1.R0.S04: Offset Found: RdPtrOffsetDqs = 006
N4.C3.D1.R1.S11: Total Receive Enable Delay = 1313
N6.C3.D1.R1.S09: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N0.C3.D1.R1.S16: PI = 046, PtrOffset = 004
N2.C0.D1.R0.S05: Offset Found: RdPtrOffsetDqs = 006
N4.C3.D1.R1.S12: Total Receive Enable Delay = 1292
N6.C3.D1.R1.S10: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N0.C3.D1.R1.S17: PI = 018, PtrOffset = 005
N2.C0.D1.R0.S06: Offset Found: RdPtrOffsetDqs = 006
N4.C3.D1.R1.S13: Total Receive Enable Delay = 1283
N6.C3.D1.R1.S11: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N0.C3.D1.R1.S09: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N2.C0.D1.R0.S07: Offset Found: RdPtrOffsetDqs = 007
N4.C3.D1.R1.S14: Total Receive Enable Delay = 1307
N6.C3.D1.R1.S12: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N0.C3.D1.R1.S10: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N2.C0.D1.R0.S08: Offset Found: RdPtrOffsetDqs = 006
N4.C3.D1.R1.S15: Total Receive Enable Delay = 1333
N6.C3.D1.R1.S13: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N0.C3.D1.R1.S11: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N2.C0.D1.R0: Write Training Coarse, upper nibbles
N4.C3.D1.R1.S16: Total Receive Enable Delay = 1355
N6.C3.D1.R1.S14: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N0.C3.D1.R1.S12: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N2.C0.D1.R0.S09: Dq Delay estimate: 470
N4.C3.D1.R1.S17: Total Receive Enable Delay = 1271
N6.C3.D1.R1.S15: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N0.C3.D1.R1.S13: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N2.C0.D1.R0.S10: Dq Delay estimate: 449
START_DATA_REC_EN
N6.C3.D1.R1.S16: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N0.C3.D1.R1.S14: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N2.C0.D1.R0.S11: Dq Delay estimate: 442
N4.C3.S00: RdCmd2RcvEnLatency = 9, RdPtrOffsetRcvEn = 5
N6.C3.D1.R1.S17: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N0.C3.D1.R1.S15: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N2.C0.D1.R0.S12: Dq Delay estimate: 426
N4.C3.S01: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N6.C3.D1.R1.S09: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N0.C3.D1.R1.S16: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N2.C0.D1.R0.S13: Dq Delay estimate: 391
N4.C3.S02: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N6.C3.D1.R1.S10: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N0.C3.D1.R1.S17: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N2.C0.D1.R0.S14: Dq Delay estimate: 410
N4.C3.S03: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N6.C3.D1.R1.S11: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N0.C3.D1.R1.S09: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N2.C0.D1.R0.S15: Dq Delay estimate: 411
N4.C3.S04: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N6.C3.D1.R1.S12: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N0.C3.D1.R1.S10: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N2.C0.D1.R0.S16: Dq Delay estimate: 427
N4.C3.S05: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N6.C3.D1.R1.S13: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N0.C3.D1.R1.S11: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N2.C0.D1.R0.S17: Dq Delay estimate: 398
N4.C3.S06: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N6.C3.D1.R1.S14: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N0.C3.D1.R1.S12: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
ACCM: F0 F0F0F0F0 F0F0F0F0
N4.C3.S07: RdCmd2RcvEnLatency = 9, RdPtrOffsetRcvEn = 5
N6.C3.D1.R1.S15: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N0.C3.D1.R1.S13: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
ACCM: F0 F0F0F0F0 F0F0F0F0
N4.C3.S08: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 5
N6.C3.D1.R1.S16: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N0.C3.D1.R1.S14: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
ACCM: F0 F0F0F0F0 F0F0F0F0
N4.C3.S09: RdCmd2RcvEnLatency = 9, RdPtrOffsetRcvEn = 5
N6.C3.D1.R1.S17: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N0.C3.D1.R1.S15: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
ACCM: F0 F0F0F0F0 F0F0F0F0
N4.C3.S10: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N6.C3.D1.R1.S09: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N0.C3.D1.R1.S16: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N2.C0.D1.R0: CheckMCTest: result = 0x3FE00
N4.C3.S11: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N6.C3.D1.R1.S10: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N0.C3.D1.R1.S17: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
ACCM: F0 F0F0F0F0 F0F0F0F0
N4.C3.S12: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N6.C3.D1.R1.S11: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N0.C3.D1.R1.S09: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
ACCM: F0 F0F0F0F0 F0F0F0F0
N4.C3.S13: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N6.C3.D1.R1.S12: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N0.C3.D1.R1.S10: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
ACCM: F0 F0F0F0F0 F0F0F0F0
N4.C3.S14: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N6.C3.D1.R1.S13: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N0.C3.D1.R1.S11: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
ACCM: F0 F0F0F0F0 F0F0F0F0
N4.C3.S15: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N6.C3.D1.R1.S14: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N0.C3.D1.R1.S12: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N2.C0.D1.R0: CheckMCTest: result = 0x3FE00
N4.C3.S16: RdCmd2RcvEnLatency = 9, RdPtrOffsetRcvEn = 5
N6.C3.D1.R1.S15: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N0.C3.D1.R1.S13: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
ACCM: F0 F0F0F0F0 F0F0F0F0
N4.C3.S17: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 5
N6.C3.D1.R1.S16: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N0.C3.D1.R1.S14: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
ACCM: F0 F0F0F0F0 F0F0F0F0
N4.C3.D0.R0.S00: RcvEn: plus1 = 1, minus1 = 0, PI = 29, DB = 0
N6.C3.D1.R1.S17: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N0.C3.D1.R1.S15: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
ACCM: 00 00B00000 00000000
N4.C3.D0.R0.S01: RcvEn: plus1 = 0, minus1 = 1, PI = 09, DB = 1
N6.C3.D1.R1.S09: Preamble found at Latency = 008
N0.C3.D1.R1.S16: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
ACCM: 00 00B00000 00000000
N4.C3.D0.R0.S02: RcvEn: plus1 = 1, minus1 = 0, PI = 44, DB = 0
N6.C3.D1.R1.S10: Preamble found at Latency = 008
N0.C3.D1.R1.S17: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N2.C0.D1.R0: CheckMCTest: result = 0x3FE00
N4.C3.D0.R0.S03: RcvEn: plus1 = 1, minus1 = 0, PI = 22, DB = 0
N6.C3.D1.R1.S11: Preamble found at Latency = 008
N0.C3.D1.R1.S09: Preamble found at Latency = 008
ACCM: F0 F0F0F0F0 F0F0F0F0
N4.C3.D0.R0.S04: RcvEn: plus1 = 1, minus1 = 0, PI = 16, DB = 0
N6.C3.D1.R1.S14: Preamble found at Latency = 008
N0.C3.D1.R1.S10: Preamble found at Latency = 008
ACCM: F0 F0F0F0F0 F0F0F0F0
N4.C3.D0.R0.S05: RcvEn: plus1 = 1, minus1 = 0, PI = 41, DB = 0
N6.C3.D1.R1.S15: Preamble found at Latency = 008
N0.C3.D1.R1.S15: Preamble found at Latency = 008
ACCM: 00 00F00000 00000000
N4.C3.D0.R0.S06: RcvEn: plus1 = 0, minus1 = 1, PI = 01, DB = 1
N6.C3.D1.R1.S16: Preamble found at Latency = 008
N0.C3.D1.R1.S16: Preamble found at Latency = 008
ACCM: 00 00F00000 00000000
N4.C3.D0.R0.S07: RcvEn: plus1 = 1, minus1 = 0, PI = 23, DB = 0
N6.C3.D1.R1.S09: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N0.C3.D1.R1.S09: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N2.C0.D1.R0: CheckMCTest: result = 0x3FE00
N4.C3.D0.R0.S08: RcvEn: plus1 = 0, minus1 = 1, PI = 00, DB = 1
N6.C3.D1.R1.S10: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N0.C3.D1.R1.S10: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N2.C0.D1.R0: CheckMCTest: passed
N4.C3.D0.R0.S09: RcvEn: plus1 = 1, minus1 = 0, PI = 28, DB = 0
N6.C3.D1.R1.S11: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N0.C3.D1.R1.S11: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N2.C0.D1.R0: CheckMCTest: passed
N4.C3.D0.R0.S10: RcvEn: plus1 = 0, minus1 = 1, PI = 09, DB = 1
N6.C3.D1.R1.S12: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N0.C3.D1.R1.S12: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N2.C0.D1.R0.S09: Offset Found: RdPtrOffsetDqs = 007
N4.C3.D0.R0.S11: RcvEn: plus1 = 1, minus1 = 0, PI = 45, DB = 0
N6.C3.D1.R1.S13: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N0.C3.D1.R1.S13: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N2.C0.D1.R0.S10: Offset Found: RdPtrOffsetDqs = 007
N4.C3.D0.R0.S12: RcvEn: plus1 = 1, minus1 = 0, PI = 24, DB = 0
N6.C3.D1.R1.S14: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N0.C3.D1.R1.S14: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N2.C0.D1.R0.S11: Offset Found: RdPtrOffsetDqs = 007
N4.C3.D0.R0.S13: RcvEn: plus1 = 1, minus1 = 0, PI = 16, DB = 0
N6.C3.D1.R1.S15: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N0.C3.D1.R1.S15: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N2.C0.D1.R0.S12: Offset Found: RdPtrOffsetDqs = 007
N4.C3.D0.R0.S14: RcvEn: plus1 = 1, minus1 = 0, PI = 42, DB = 0
N6.C3.D1.R1.S16: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N0.C3.D1.R1.S16: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N2.C0.D1.R0.S13: Offset Found: RdPtrOffsetDqs = 006
N4.C3.D0.R0.S15: RcvEn: plus1 = 0, minus1 = 1, PI = 03, DB = 1
N6.C3.D1.R1.S17: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N0.C3.D1.R1.S17: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N2.C0.D1.R0.S14: Offset Found: RdPtrOffsetDqs = 006
N4.C3.D0.R0.S16: RcvEn: plus1 = 1, minus1 = 0, PI = 26, DB = 0
N6.C3.D1.R1.S12: Preamble found at Latency = 007
N0.C3.D1.R1.S11: Preamble found at Latency = 007
N2.C0.D1.R0.S15: Offset Found: RdPtrOffsetDqs = 006
N4.C3.D0.R0.S17: RcvEn: plus1 = 0, minus1 = 1, PI = 02, DB = 1
N6.C3.D1.R1.S13: Preamble found at Latency = 007
N0.C3.D1.R1.S12: Preamble found at Latency = 007
N2.C0.D1.R0.S16: Offset Found: RdPtrOffsetDqs = 007
N4.C3.D0.R1.S00: RcvEn: plus1 = 1, minus1 = 0, PI = 29, DB = 0
N6.C3.D1.R1.S17: Preamble found at Latency = 007
N0.C3.D1.R1.S13: Preamble found at Latency = 007
N2.C0.D1.R0.S17: Offset Found: RdPtrOffsetDqs = 006
N4.C3.D0.R1.S01: RcvEn: plus1 = 0, minus1 = 1, PI = 09, DB = 1
N6.C3.D1.R1: Preamble found for all upper nibbles, adjusting Pi, Offset to center into preamble
N0.C3.D1.R1.S14: Preamble found at Latency = 007
N2.C0.D1.R1: Write Training Coarse, lower nibbles / bytes
N4.C3.D0.R1.S02: RcvEn: plus1 = 1, minus1 = 0, PI = 44, DB = 0
N6.C3.D1.R1.S09: Total Receive Enable Delay = 1361
N0.C3.D1.R1.S17: Preamble found at Latency = 007
N2.C0.D1.R1.S00: Dq Delay estimate: 463
N4.C3.D0.R1.S03: RcvEn: plus1 = 1, minus1 = 0, PI = 22, DB = 0
N6.C3.D1.R1.S10: Total Receive Enable Delay = 1344
N0.C3.D1.R1: Preamble found for all upper nibbles, adjusting Pi, Offset to center into preamble
N2.C0.D1.R1.S01: Dq Delay estimate: 449
N4.C3.D0.R1.S04: RcvEn: plus1 = 1, minus1 = 0, PI = 16, DB = 0
N6.C3.D1.R1.S11: Total Receive Enable Delay = 1317
N0.C3.D1.R1.S09: Total Receive Enable Delay = 1358
N2.C0.D1.R1.S02: Dq Delay estimate: 435
N4.C3.D0.R1.S05: RcvEn: plus1 = 1, minus1 = 0, PI = 41, DB = 0
N6.C3.D1.R1.S12: Total Receive Enable Delay = 1293
N0.C3.D1.R1.S10: Total Receive Enable Delay = 1341
N2.C0.D1.R1.S03: Dq Delay estimate: 418
N4.C3.D0.R1.S06: RcvEn: plus1 = 0, minus1 = 1, PI = 01, DB = 1
N6.C3.D1.R1.S13: Total Receive Enable Delay = 1287
N0.C3.D1.R1.S11: Total Receive Enable Delay = 1308
N2.C0.D1.R1.S04: Dq Delay estimate: 384
N4.C3.D0.R1.S07: RcvEn: plus1 = 1, minus1 = 0, PI = 23, DB = 0
N6.C3.D1.R1.S14: Total Receive Enable Delay = 1318
N0.C3.D1.R1.S12: Total Receive Enable Delay = 1289
N2.C0.D1.R1.S05: Dq Delay estimate: 404
N4.C3.D0.R1.S08: RcvEn: plus1 = 0, minus1 = 1, PI = 00, DB = 1
N6.C3.D1.R1.S15: Total Receive Enable Delay = 1340
N0.C3.D1.R1.S13: Total Receive Enable Delay = 1281
N2.C0.D1.R1.S06: Dq Delay estimate: 406
N4.C3.D0.R1.S09: RcvEn: plus1 = 1, minus1 = 0, PI = 28, DB = 0
N6.C3.D1.R1.S16: Total Receive Enable Delay = 1359
N0.C3.D1.R1.S14: Total Receive Enable Delay = 1307
N2.C0.D1.R1.S07: Dq Delay estimate: 424
N4.C3.D0.R1.S10: RcvEn: plus1 = 0, minus1 = 1, PI = 09, DB = 1
N6.C3.D1.R1.S17: Total Receive Enable Delay = 1274
N0.C3.D1.R1.S15: Total Receive Enable Delay = 1332
N2.C0.D1.R1.S08: Dq Delay estimate: 392
N4.C3.D0.R1.S11: RcvEn: plus1 = 1, minus1 = 0, PI = 45, DB = 0
START_DATA_REC_EN
N0.C3.D1.R1.S16: Total Receive Enable Delay = 1358
ACCM: 0F 0F0F0F0F 0F0F0F0F
N4.C3.D0.R1.S12: RcvEn: plus1 = 1, minus1 = 0, PI = 24, DB = 0
N6.C3.S00: RdCmd2RcvEnLatency = 9, RdPtrOffsetRcvEn = 5
N0.C3.D1.R1.S17: Total Receive Enable Delay = 1266
ACCM: 0F 0F0F0F0F 0F0F0F0F
N4.C3.D0.R1.S13: RcvEn: plus1 = 1, minus1 = 0, PI = 16, DB = 0
N6.C3.S01: RdCmd2RcvEnLatency = 9, RdPtrOffsetRcvEn = 5
START_DATA_REC_EN
ACCM: 0F 0F0F0F0F 0F0F0F0F
N4.C3.D0.R1.S14: RcvEn: plus1 = 1, minus1 = 0, PI = 42, DB = 0
N6.C3.S02: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N0.C3.S00: RdCmd2RcvEnLatency = 9, RdPtrOffsetRcvEn = 5
ACCM: 0F 0F0F0F0F 0F0F0F0F
N4.C3.D0.R1.S15: RcvEn: plus1 = 0, minus1 = 1, PI = 03, DB = 1
N6.C3.S03: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N0.C3.S01: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N2.C0.D1.R1: CheckMCTest: result = 0x1FF
N4.C3.D0.R1.S16: RcvEn: plus1 = 1, minus1 = 0, PI = 26, DB = 0
N6.C3.S04: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N0.C3.S02: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
ACCM: 0F 0F0F0F0F 0F0F0F0F
N4.C3.D0.R1.S17: RcvEn: plus1 = 0, minus1 = 1, PI = 02, DB = 1
N6.C3.S05: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N0.C3.S03: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
ACCM: 0F 0F0F0F0F 0F0F0F0F
N4.C3.D1.R0.S00: RcvEn: plus1 = 1, minus1 = 0, PI = 15, DB = 1
N6.C3.S06: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N0.C3.S04: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
ACCM: 0F 0F0F0F0F 0F0F0F0F
N4.C3.D1.R0.S01: RcvEn: plus1 = 1, minus1 = 0, PI = 59, DB = 1
N6.C3.S07: RdCmd2RcvEnLatency = 9, RdPtrOffsetRcvEn = 5
N0.C3.S05: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
ACCM: 0F 0F0F0F0F 0F0F0F0F
N4.C3.D1.R0.S02: RcvEn: plus1 = 1, minus1 = 0, PI = 30, DB = 0
N6.C3.S08: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 5
N0.C3.S06: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N2.C0.D1.R1: CheckMCTest: result = 0x1FF
N4.C3.D1.R0.S03: RcvEn: plus1 = 1, minus1 = 0, PI = 10, DB = 1
N6.C3.S09: RdCmd2RcvEnLatency = 9, RdPtrOffsetRcvEn = 5
N0.C3.S07: RdCmd2RcvEnLatency = 9, RdPtrOffsetRcvEn = 5
ACCM: 0F 0F0F0F0F 0F0F0F0F
N4.C3.D1.R0.S04: RcvEn: plus1 = 1, minus1 = 0, PI = 03, DB = 1
N6.C3.S10: RdCmd2RcvEnLatency = 9, RdPtrOffsetRcvEn = 5
N0.C3.S08: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 5
ACCM: 0F 0F0F0F0F 0F0F0F0F
N4.C3.D1.R0.S05: RcvEn: plus1 = 1, minus1 = 0, PI = 28, DB = 0
N6.C3.S11: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N0.C3.S09: RdCmd2RcvEnLatency = 9, RdPtrOffsetRcvEn = 5
ACCM: 00 000B000B 0000000B
N4.C3.D1.R0.S06: RcvEn: plus1 = 1, minus1 = 0, PI = 52, DB = 1
N6.C3.S12: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N0.C3.S10: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
ACCM: 00 000B000B 0000000B
N4.C3.D1.R0.S07: RcvEn: plus1 = 1, minus1 = 0, PI = 11, DB = 1
N6.C3.S13: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N0.C3.S11: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N2.C0.D1.R1: CheckMCTest: result = 0x1FF
N4.C3.D1.R0.S08: RcvEn: plus1 = 1, minus1 = 0, PI = 52, DB = 1
N6.C3.S14: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N0.C3.S12: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
ACCM: 0F 0F0F0F0F 0F0F0F0F
N4.C3.D1.R0.S09: RcvEn: plus1 = 1, minus1 = 0, PI = 17, DB = 0
N6.C3.S15: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N0.C3.S13: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
ACCM: 0F 0F0F0F0F 0F0F0F0F
N4.C3.D1.R0.S10: RcvEn: plus1 = 1, minus1 = 0, PI = 58, DB = 1
N6.C3.S16: RdCmd2RcvEnLatency = 9, RdPtrOffsetRcvEn = 5
N0.C3.S14: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
ACCM: 00 000B0D0F 0000000B
N4.C3.D1.R0.S11: RcvEn: plus1 = 1, minus1 = 0, PI = 31, DB = 0
N6.C3.S17: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 5
N0.C3.S15: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
ACCM: 00 000B0D0F 0000000B
N4.C3.D1.R0.S12: RcvEn: plus1 = 1, minus1 = 0, PI = 11, DB = 1
N6.C3.D0.R0.S00: RcvEn: plus1 = 1, minus1 = 0, PI = 36, DB = 0
N0.C3.S16: RdCmd2RcvEnLatency = 9, RdPtrOffsetRcvEn = 5
N2.C0.D1.R1: CheckMCTest: result = 0x1FF
N4.C3.D1.R0.S13: RcvEn: plus1 = 1, minus1 = 0, PI = 03, DB = 1
N6.C3.D0.R0.S01: RcvEn: plus1 = 1, minus1 = 0, PI = 14, DB = 1
N0.C3.S17: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 5
N2.C0.D1.R1: CheckMCTest: passed
N4.C3.D1.R0.S14: RcvEn: plus1 = 1, minus1 = 0, PI = 29, DB = 0
N6.C3.D0.R0.S02: RcvEn: plus1 = 1, minus1 = 0, PI = 51, DB = 1
N0.C3.D0.R0.S00: RcvEn: plus1 = 1, minus1 = 0, PI = 30, DB = 0
N2.C0.D1.R1: CheckMCTest: passed
N4.C3.D1.R0.S15: RcvEn: plus1 = 1, minus1 = 0, PI = 52, DB = 1
N6.C3.D0.R0.S03: RcvEn: plus1 = 1, minus1 = 0, PI = 27, DB = 0
N0.C3.D0.R0.S01: RcvEn: plus1 = 0, minus1 = 1, PI = 11, DB = 1
N2.C0.D1.R1.S00: Offset Found: RdPtrOffsetDqs = 007
N4.C3.D1.R0.S16: RcvEn: plus1 = 1, minus1 = 0, PI = 11, DB = 1
N6.C3.D0.R0.S04: RcvEn: plus1 = 1, minus1 = 0, PI = 20, DB = 0
N0.C3.D0.R0.S02: RcvEn: plus1 = 1, minus1 = 0, PI = 46, DB = 0
N2.C0.D1.R1.S01: Offset Found: RdPtrOffsetDqs = 007
N4.C3.D1.R0.S17: RcvEn: plus1 = 1, minus1 = 0, PI = 55, DB = 1
N6.C3.D0.R0.S05: RcvEn: plus1 = 1, minus1 = 0, PI = 47, DB = 0
N0.C3.D0.R0.S03: RcvEn: plus1 = 1, minus1 = 0, PI = 22, DB = 0
N2.C0.D1.R1.S02: Offset Found: RdPtrOffsetDqs = 007
N4.C3.D1.R1.S00: RcvEn: plus1 = 1, minus1 = 0, PI = 15, DB = 1
N6.C3.D0.R0.S06: RcvEn: plus1 = 0, minus1 = 1, PI = 07, DB = 1
N0.C3.D0.R0.S04: RcvEn: plus1 = 1, minus1 = 0, PI = 19, DB = 0
N2.C0.D1.R1.S03: Offset Found: RdPtrOffsetDqs = 007
N4.C3.D1.R1.S01: RcvEn: plus1 = 1, minus1 = 0, PI = 59, DB = 1
N6.C3.D0.R0.S07: RcvEn: plus1 = 1, minus1 = 0, PI = 27, DB = 0
N0.C3.D0.R0.S05: RcvEn: plus1 = 1, minus1 = 0, PI = 44, DB = 0
N2.C0.D1.R1.S04: Offset Found: RdPtrOffsetDqs = 006
N4.C3.D1.R1.S02: RcvEn: plus1 = 1, minus1 = 0, PI = 30, DB = 0
N6.C3.D0.R0.S08: RcvEn: plus1 = 0, minus1 = 1, PI = 09, DB = 1
N0.C3.D0.R0.S06: RcvEn: plus1 = 0, minus1 = 1, PI = 02, DB = 1
N2.C0.D1.R1.S05: Offset Found: RdPtrOffsetDqs = 006
N4.C3.D1.R1.S03: RcvEn: plus1 = 1, minus1 = 0, PI = 10, DB = 1
N6.C3.D0.R0.S09: RcvEn: plus1 = 1, minus1 = 0, PI = 32, DB = 0
N0.C3.D0.R0.S07: RcvEn: plus1 = 1, minus1 = 0, PI = 25, DB = 0
N2.C0.D1.R1.S06: Offset Found: RdPtrOffsetDqs = 006
N4.C3.D1.R1.S04: RcvEn: plus1 = 1, minus1 = 0, PI = 03, DB = 1
N6.C3.D0.R0.S10: RcvEn: plus1 = 1, minus1 = 0, PI = 15, DB = 1
N0.C3.D0.R0.S08: RcvEn: plus1 = 0, minus1 = 1, PI = 06, DB = 1
N2.C0.D1.R1.S07: Offset Found: RdPtrOffsetDqs = 007
N4.C3.D1.R1.S05: RcvEn: plus1 = 1, minus1 = 0, PI = 28, DB = 0
N6.C3.D0.R0.S11: RcvEn: plus1 = 1, minus1 = 0, PI = 50, DB = 1
N0.C3.D0.R0.S09: RcvEn: plus1 = 1, minus1 = 0, PI = 30, DB = 0
N2.C0.D1.R1.S08: Offset Found: RdPtrOffsetDqs = 006
N4.C3.D1.R1.S06: RcvEn: plus1 = 1, minus1 = 0, PI = 52, DB = 1
N6.C3.D0.R0.S12: RcvEn: plus1 = 1, minus1 = 0, PI = 26, DB = 0
N0.C3.D0.R0.S10: RcvEn: plus1 = 0, minus1 = 1, PI = 12, DB = 1
N2.C0.D1.R1: Write Training Coarse, upper nibbles
N4.C3.D1.R1.S07: RcvEn: plus1 = 1, minus1 = 0, PI = 11, DB = 1
N6.C3.D0.R0.S13: RcvEn: plus1 = 1, minus1 = 0, PI = 21, DB = 0
N0.C3.D0.R0.S11: RcvEn: plus1 = 1, minus1 = 0, PI = 47, DB = 0
N2.C0.D1.R1.S09: Dq Delay estimate: 464
N4.C3.D1.R1.S08: RcvEn: plus1 = 1, minus1 = 0, PI = 52, DB = 1
N6.C3.D0.R0.S14: RcvEn: plus1 = 1, minus1 = 0, PI = 51, DB = 1
N0.C3.D0.R0.S12: RcvEn: plus1 = 1, minus1 = 0, PI = 25, DB = 0
N2.C0.D1.R1.S10: Dq Delay estimate: 448
N4.C3.D1.R1.S09: RcvEn: plus1 = 1, minus1 = 0, PI = 17, DB = 0
N6.C3.D0.R0.S15: RcvEn: plus1 = 0, minus1 = 1, PI = 09, DB = 1
N0.C3.D0.R0.S13: RcvEn: plus1 = 1, minus1 = 0, PI = 17, DB = 0
N2.C0.D1.R1.S11: Dq Delay estimate: 437
N4.C3.D1.R1.S10: RcvEn: plus1 = 1, minus1 = 0, PI = 58, DB = 1
N6.C3.D0.R0.S16: RcvEn: plus1 = 1, minus1 = 0, PI = 29, DB = 0
N0.C3.D0.R0.S14: RcvEn: plus1 = 1, minus1 = 0, PI = 44, DB = 0
N2.C0.D1.R1.S12: Dq Delay estimate: 424
N4.C3.D1.R1.S11: RcvEn: plus1 = 1, minus1 = 0, PI = 31, DB = 0
N6.C3.D0.R0.S17: RcvEn: plus1 = 0, minus1 = 1, PI = 10, DB = 1
N0.C3.D0.R0.S15: RcvEn: plus1 = 0, minus1 = 1, PI = 04, DB = 1
N2.C0.D1.R1.S13: Dq Delay estimate: 386
N4.C3.D1.R1.S12: RcvEn: plus1 = 1, minus1 = 0, PI = 11, DB = 1
N6.C3.D0.R1.S00: RcvEn: plus1 = 1, minus1 = 0, PI = 36, DB = 0
N0.C3.D0.R0.S16: RcvEn: plus1 = 1, minus1 = 0, PI = 27, DB = 0
N2.C0.D1.R1.S14: Dq Delay estimate: 404
N4.C3.D1.R1.S13: RcvEn: plus1 = 1, minus1 = 0, PI = 03, DB = 1
N6.C3.D0.R1.S01: RcvEn: plus1 = 1, minus1 = 0, PI = 14, DB = 1
N0.C3.D0.R0.S17: RcvEn: plus1 = 0, minus1 = 1, PI = 02, DB = 1
N2.C0.D1.R1.S15: Dq Delay estimate: 408
N4.C3.D1.R1.S14: RcvEn: plus1 = 1, minus1 = 0, PI = 29, DB = 0
N6.C3.D0.R1.S02: RcvEn: plus1 = 1, minus1 = 0, PI = 51, DB = 1
N0.C3.D0.R1.S00: RcvEn: plus1 = 1, minus1 = 0, PI = 30, DB = 0
N2.C0.D1.R1.S16: Dq Delay estimate: 424
N4.C3.D1.R1.S15: RcvEn: plus1 = 1, minus1 = 0, PI = 52, DB = 1
N6.C3.D0.R1.S03: RcvEn: plus1 = 1, minus1 = 0, PI = 27, DB = 0
N0.C3.D0.R1.S01: RcvEn: plus1 = 0, minus1 = 1, PI = 11, DB = 1
N2.C0.D1.R1.S17: Dq Delay estimate: 393
N4.C3.D1.R1.S16: RcvEn: plus1 = 1, minus1 = 0, PI = 11, DB = 1
N6.C3.D0.R1.S04: RcvEn: plus1 = 1, minus1 = 0, PI = 20, DB = 0
N0.C3.D0.R1.S02: RcvEn: plus1 = 1, minus1 = 0, PI = 46, DB = 0
ACCM: F0 F0F0F0F0 F0F0F0F0
N4.C3.D1.R1.S17: RcvEn: plus1 = 1, minus1 = 0, PI = 55, DB = 1
N6.C3.D0.R1.S05: RcvEn: plus1 = 1, minus1 = 0, PI = 47, DB = 0
N0.C3.D0.R1.S03: RcvEn: plus1 = 1, minus1 = 0, PI = 22, DB = 0
ACCM: F0 F0F0F0F0 F0F0F0F0
STOP_DATA_REC_EN
N6.C3.D0.R1.S06: RcvEn: plus1 = 0, minus1 = 1, PI = 07, DB = 1
N0.C3.D0.R1.S04: RcvEn: plus1 = 1, minus1 = 0, PI = 19, DB = 0
ACCM: F0 F0F0F0F0 F0F0F0F0
N4.C0.D0.R0.S00: StoreJckWorstRank: worst rank = 0, greatestDelay = 1323
N6.C3.D0.R1.S07: RcvEn: plus1 = 1, minus1 = 0, PI = 27, DB = 0
N0.C3.D0.R1.S05: RcvEn: plus1 = 1, minus1 = 0, PI = 44, DB = 0
ACCM: F0 F0F0F0F0 F0F0F0F0
N4.C0.D0.R0.S07: StoreJckWorstRank: worst rank = 0, greatestDelay = 1324
N6.C3.D0.R1.S08: RcvEn: plus1 = 0, minus1 = 1, PI = 09, DB = 1
N0.C3.D0.R1.S06: RcvEn: plus1 = 0, minus1 = 1, PI = 02, DB = 1
N2.C0.D1.R1: CheckMCTest: result = 0x3FE00
N4.C0.D0.R1.S07: StoreJckWorstRank: worst rank = 1, greatestDelay = 1325
N6.C3.D0.R1.S09: RcvEn: plus1 = 1, minus1 = 0, PI = 32, DB = 0
N0.C3.D0.R1.S07: RcvEn: plus1 = 1, minus1 = 0, PI = 25, DB = 0
ACCM: F0 F0F0F0F0 F0F0F0F0
N4.C1.D0.R0.S00: StoreJckWorstRank: worst rank = 0, greatestDelay = 1374
N6.C3.D0.R1.S10: RcvEn: plus1 = 1, minus1 = 0, PI = 15, DB = 1
N0.C3.D0.R1.S08: RcvEn: plus1 = 0, minus1 = 1, PI = 06, DB = 1
ACCM: F0 F0F0F0F0 F0F0F0F0
N4.C0: StoreJckWorstRank: final value: worst rank = 0
N6.C3.D0.R1.S11: RcvEn: plus1 = 1, minus1 = 0, PI = 50, DB = 1
N0.C3.D0.R1.S09: RcvEn: plus1 = 1, minus1 = 0, PI = 30, DB = 0
ACCM: F0 F0F0F0F0 F0F0F0F0
N4.C2.D0.R0.S00: StoreJckWorstRank: worst rank = 0, greatestDelay = 1327
N6.C3.D0.R1.S12: RcvEn: plus1 = 1, minus1 = 0, PI = 26, DB = 0
N0.C3.D0.R1.S10: RcvEn: plus1 = 0, minus1 = 1, PI = 12, DB = 1
ACCM: F0 F0F0F0F0 F0F0F0F0
N4.C3.D0.R0.S00: StoreJckWorstRank: worst rank = 0, greatestDelay = 1373
N6.C3.D0.R1.S13: RcvEn: plus1 = 1, minus1 = 0, PI = 21, DB = 0
N0.C3.D0.R1.S11: RcvEn: plus1 = 1, minus1 = 0, PI = 47, DB = 0
N2.C0.D1.R1: CheckMCTest: result = 0x3FE00
N4.C1: StoreJckWorstRank: final value: worst rank = 0
N6.C3.D0.R1.S14: RcvEn: plus1 = 1, minus1 = 0, PI = 51, DB = 1
N0.C3.D0.R1.S12: RcvEn: plus1 = 1, minus1 = 0, PI = 25, DB = 0
ACCM: F0 F0F0F0F0 F0F0F0F0
N4: RunTrainStep: Final status = 0
N6.C3.D0.R1.S15: RcvEn: plus1 = 0, minus1 = 1, PI = 09, DB = 1
N0.C3.D0.R1.S13: RcvEn: plus1 = 1, minus1 = 0, PI = 17, DB = 0
ACCM: F0 F0F0F0F0 F0F0F0F0

END - Basic Receive Enable Training    Time         64065 ms
N6.C3.D0.R1.S16: RcvEn: plus1 = 1, minus1 = 0, PI = 29, DB = 0
N0.C3.D0.R1.S14: RcvEn: plus1 = 1, minus1 = 0, PI = 44, DB = 0
ACCM: 00 00B00000 00000000
N4.C0.S00: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  6
N6.C3.D0.R1.S17: RcvEn: plus1 = 0, minus1 = 1, PI = 10, DB = 1
N0.C3.D0.R1.S15: RcvEn: plus1 = 0, minus1 = 1, PI = 04, DB = 1
ACCM: 00 00B00000 00000000
N4.C0.S01: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  6
N6.C3.D1.R0.S00: RcvEn: plus1 = 1, minus1 = 0, PI = 21, DB = 0
N0.C3.D0.R1.S16: RcvEn: plus1 = 1, minus1 = 0, PI = 27, DB = 0
N2.C0.D1.R1: CheckMCTest: result = 0x3FE00
N4.C0.S02: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  5
N6.C3.D1.R0.S01: RcvEn: plus1 = 1, minus1 = 0, PI = 00, DB = 1
N0.C3.D0.R1.S17: RcvEn: plus1 = 0, minus1 = 1, PI = 02, DB = 1
ACCM: F0 F0F0F0F0 F0F0F0F0
N4.C0.S03: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  5
N6.C3.D1.R0.S02: RcvEn: plus1 = 1, minus1 = 0, PI = 37, DB = 0
N0.C3.D1.R0.S00: RcvEn: plus1 = 1, minus1 = 0, PI = 15, DB = 1
ACCM: F0 F0F0F0F0 F0F0F0F0
N4.C0.S04: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  5
N6.C3.D1.R0.S03: RcvEn: plus1 = 1, minus1 = 0, PI = 13, DB = 1
N0.C3.D1.R0.S01: RcvEn: plus1 = 1, minus1 = 0, PI = 60, DB = 1
ACCM: 00 00F00000 00000000
N4.C0.S05: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  5
N6.C3.D1.R0.S04: RcvEn: plus1 = 1, minus1 = 0, PI = 06, DB = 1
N0.C3.D1.R0.S02: RcvEn: plus1 = 1, minus1 = 0, PI = 29, DB = 0
ACCM: 00 00F00000 00000000
N4.C0.S06: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  6
N6.C3.D1.R0.S05: RcvEn: plus1 = 1, minus1 = 0, PI = 36, DB = 0
N0.C3.D1.R0.S03: RcvEn: plus1 = 1, minus1 = 0, PI = 06, DB = 1
N2.C0.D1.R1: CheckMCTest: result = 0x3FE00
N4.C0.S07: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  6
N6.C3.D1.R0.S06: RcvEn: plus1 = 1, minus1 = 0, PI = 57, DB = 1
N0.C3.D1.R0.S04: RcvEn: plus1 = 1, minus1 = 0, PI = 01, DB = 1
N2.C0.D1.R1: CheckMCTest: passed
N4.C0.S08: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  5
N6.C3.D1.R0.S07: RcvEn: plus1 = 1, minus1 = 0, PI = 14, DB = 1
N0.C3.D1.R0.S05: RcvEn: plus1 = 1, minus1 = 0, PI = 26, DB = 0
N2.C0.D1.R1: CheckMCTest: passed
N4.C1.S00: SuppressionWindowAdjustmentRd: latency =  9, rdptroffset =  5
N6.C3.D1.R0.S08: RcvEn: plus1 = 1, minus1 = 0, PI = 58, DB = 1
N0.C3.D1.R0.S06: RcvEn: plus1 = 1, minus1 = 0, PI = 50, DB = 1
N2.C0.D1.R1.S09: Offset Found: RdPtrOffsetDqs = 007
N4.C1.S01: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  6
N6.C3.D1.R0.S09: RcvEn: plus1 = 1, minus1 = 0, PI = 18, DB = 0
N0.C3.D1.R0.S07: RcvEn: plus1 = 1, minus1 = 0, PI = 09, DB = 1
N2.C0.D1.R1.S10: Offset Found: RdPtrOffsetDqs = 007
N4.C1.S02: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  6
N6.C3.D1.R0.S10: RcvEn: plus1 = 1, minus1 = 0, PI = 00, DB = 1
N0.C3.D1.R0.S08: RcvEn: plus1 = 1, minus1 = 0, PI = 53, DB = 1
N2.C0.D1.R1.S11: Offset Found: RdPtrOffsetDqs = 007
N4.C1.S03: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  6
N6.C3.D1.R0.S11: RcvEn: plus1 = 1, minus1 = 0, PI = 37, DB = 0
N0.C3.D1.R0.S09: RcvEn: plus1 = 1, minus1 = 0, PI = 14, DB = 1
N2.C0.D1.R1.S12: Offset Found: RdPtrOffsetDqs = 007
N4.C1.S04: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  5
N6.C3.D1.R0.S12: RcvEn: plus1 = 1, minus1 = 0, PI = 13, DB = 1
N0.C3.D1.R0.S10: RcvEn: plus1 = 1, minus1 = 0, PI = 60, DB = 1
N2.C0.D1.R1.S13: Offset Found: RdPtrOffsetDqs = 006
N4.C1.S05: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  6
N6.C3.D1.R0.S13: RcvEn: plus1 = 1, minus1 = 0, PI = 07, DB = 1
N0.C3.D1.R0.S11: RcvEn: plus1 = 1, minus1 = 0, PI = 30, DB = 0
N2.C0.D1.R1.S14: Offset Found: RdPtrOffsetDqs = 006
N4.C1.S06: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  6
N6.C3.D1.R0.S14: RcvEn: plus1 = 1, minus1 = 0, PI = 38, DB = 0
N0.C3.D1.R0.S12: RcvEn: plus1 = 1, minus1 = 0, PI = 09, DB = 1
N2.C0.D1.R1.S15: Offset Found: RdPtrOffsetDqs = 006
N4.C1.S07: SuppressionWindowAdjustmentRd: latency =  9, rdptroffset =  5
N6.C3.D1.R0.S15: RcvEn: plus1 = 1, minus1 = 0, PI = 58, DB = 1
N0.C3.D1.R0.S13: RcvEn: plus1 = 1, minus1 = 0, PI = 00, DB = 1
N2.C0.D1.R1.S16: Offset Found: RdPtrOffsetDqs = 007
N4.C1.S08: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  5
N6.C3.D1.R0.S16: RcvEn: plus1 = 1, minus1 = 0, PI = 15, DB = 1
N0.C3.D1.R0.S14: RcvEn: plus1 = 1, minus1 = 0, PI = 27, DB = 0
N2.C0.D1.R1.S17: Offset Found: RdPtrOffsetDqs = 006
N4.C2.S00: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  6
N6.C3.D1.R0.S17: RcvEn: plus1 = 1, minus1 = 0, PI = 57, DB = 1
N0.C3.D1.R0.S15: RcvEn: plus1 = 1, minus1 = 0, PI = 52, DB = 1
N2.C0: Calculating Optimimum DQS Values
N4.C2.S01: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  6
N6.C3.D1.R1.S00: RcvEn: plus1 = 1, minus1 = 0, PI = 21, DB = 0
N0.C3.D1.R0.S16: RcvEn: plus1 = 1, minus1 = 0, PI = 13, DB = 1
N2.C0.D0.R0.S00: Total Delay in PI ticks: TxDQS = 1011, TxDQ = 979
N4.C2.S02: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  5
N6.C3.D1.R1.S01: RcvEn: plus1 = 1, minus1 = 0, PI = 00, DB = 1
N0.C3.D1.R0.S17: RcvEn: plus1 = 1, minus1 = 0, PI = 51, DB = 1
N2.C0.D0.R0.S01: Total Delay in PI ticks: TxDQS = 989, TxDQ = 957
N4.C2.S03: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  5
N6.C3.D1.R1.S02: RcvEn: plus1 = 1, minus1 = 0, PI = 37, DB = 0
N0.C3.D1.R1.S00: RcvEn: plus1 = 1, minus1 = 0, PI = 15, DB = 1
N2.C0.D0.R0.S02: Total Delay in PI ticks: TxDQS = 981, TxDQ = 948
N4.C2.S04: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  5
N6.C3.D1.R1.S03: RcvEn: plus1 = 1, minus1 = 0, PI = 13, DB = 1
N0.C3.D1.R1.S01: RcvEn: plus1 = 1, minus1 = 0, PI = 60, DB = 1
N2.C0.D0.R0.S03: Total Delay in PI ticks: TxDQS = 963, TxDQ = 930
N4.C2.S05: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  5
N6.C3.D1.R1.S04: RcvEn: plus1 = 1, minus1 = 0, PI = 06, DB = 1
N0.C3.D1.R1.S02: RcvEn: plus1 = 1, minus1 = 0, PI = 29, DB = 0
N2.C0.D0.R0.S04: Total Delay in PI ticks: TxDQS = 930, TxDQ = 896
N4.C2.S06: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  6
N6.C3.D1.R1.S05: RcvEn: plus1 = 1, minus1 = 0, PI = 36, DB = 0
N0.C3.D1.R1.S03: RcvEn: plus1 = 1, minus1 = 0, PI = 06, DB = 1
N2.C0.D0.R0.S05: Total Delay in PI ticks: TxDQS = 947, TxDQ = 913
N4.C2.S07: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  6
N6.C3.D1.R1.S06: RcvEn: plus1 = 1, minus1 = 0, PI = 57, DB = 1
N0.C3.D1.R1.S04: RcvEn: plus1 = 1, minus1 = 0, PI = 01, DB = 1
N2.C0.D0.R0.S06: Total Delay in PI ticks: TxDQS = 954, TxDQ = 919
N4.C2.S08: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  5
N6.C3.D1.R1.S07: RcvEn: plus1 = 1, minus1 = 0, PI = 14, DB = 1
N0.C3.D1.R1.S05: RcvEn: plus1 = 1, minus1 = 0, PI = 26, DB = 0
N2.C0.D0.R0.S07: Total Delay in PI ticks: TxDQS = 965, TxDQ = 931
N4.C3.S00: SuppressionWindowAdjustmentRd: latency =  9, rdptroffset =  5
N6.C3.D1.R1.S08: RcvEn: plus1 = 1, minus1 = 0, PI = 58, DB = 1
N0.C3.D1.R1.S06: RcvEn: plus1 = 1, minus1 = 0, PI = 50, DB = 1
N2.C0.D0.R0.S08: Total Delay in PI ticks: TxDQS = 943, TxDQ = 907
N4.C3.S01: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  6
N6.C3.D1.R1.S09: RcvEn: plus1 = 1, minus1 = 0, PI = 18, DB = 0
N0.C3.D1.R1.S07: RcvEn: plus1 = 1, minus1 = 0, PI = 09, DB = 1
N2.C0.D0.R0.S09: Total Delay in PI ticks: TxDQS = 1015, TxDQ = 983
N4.C3.S02: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  6
N6.C3.D1.R1.S10: RcvEn: plus1 = 1, minus1 = 0, PI = 00, DB = 1
N0.C3.D1.R1.S08: RcvEn: plus1 = 1, minus1 = 0, PI = 53, DB = 1
N2.C0.D0.R0.S10: Total Delay in PI ticks: TxDQS = 990, TxDQ = 957
N4.C3.S03: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  6
N6.C3.D1.R1.S11: RcvEn: plus1 = 1, minus1 = 0, PI = 37, DB = 0
N0.C3.D1.R1.S09: RcvEn: plus1 = 1, minus1 = 0, PI = 14, DB = 1
N2.C0.D0.R0.S11: Total Delay in PI ticks: TxDQS = 981, TxDQ = 947
N4.C3.S04: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  6
N6.C3.D1.R1.S12: RcvEn: plus1 = 1, minus1 = 0, PI = 13, DB = 1
N0.C3.D1.R1.S10: RcvEn: plus1 = 1, minus1 = 0, PI = 60, DB = 1
N2.C0.D0.R0.S12: Total Delay in PI ticks: TxDQS = 964, TxDQ = 930
N4.C3.S05: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  6
N6.C3.D1.R1.S13: RcvEn: plus1 = 1, minus1 = 0, PI = 07, DB = 1
N0.C3.D1.R1.S11: RcvEn: plus1 = 1, minus1 = 0, PI = 30, DB = 0
N2.C0.D0.R0.S13: Total Delay in PI ticks: TxDQS = 932, TxDQ = 899
N4.C3.S06: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  6
N6.C3.D1.R1.S14: RcvEn: plus1 = 1, minus1 = 0, PI = 38, DB = 0
N0.C3.D1.R1.S12: RcvEn: plus1 = 1, minus1 = 0, PI = 09, DB = 1
N2.C0.D0.R0.S14: Total Delay in PI ticks: TxDQS = 948, TxDQ = 915
N4.C3.S07: SuppressionWindowAdjustmentRd: latency =  9, rdptroffset =  5
N6.C3.D1.R1.S15: RcvEn: plus1 = 1, minus1 = 0, PI = 58, DB = 1
N0.C3.D1.R1.S13: RcvEn: plus1 = 1, minus1 = 0, PI = 00, DB = 1
N2.C0.D0.R0.S15: Total Delay in PI ticks: TxDQS = 951, TxDQ = 918
N4.C3.S08: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  5
N6.C3.D1.R1.S16: RcvEn: plus1 = 1, minus1 = 0, PI = 15, DB = 1
N0.C3.D1.R1.S14: RcvEn: plus1 = 1, minus1 = 0, PI = 27, DB = 0
N2.C0.D0.R0.S16: Total Delay in PI ticks: TxDQS = 965, TxDQ = 931

START - Basic Write Level Training
N6.C3.D1.R1.S17: RcvEn: plus1 = 1, minus1 = 0, PI = 57, DB = 1
N0.C3.D1.R1.S15: RcvEn: plus1 = 1, minus1 = 0, PI = 52, DB = 1
N2.C0.D0.R0.S17: Total Delay in PI ticks: TxDQS = 943, TxDQ = 909
N4: START WRITE LEVEL:
STOP_DATA_REC_EN
N0.C3.D1.R1.S16: RcvEn: plus1 = 1, minus1 = 0, PI = 13, DB = 1
N2.C0.D0.R1.S00: Total Delay in PI ticks: TxDQS = 1007, TxDQ = 973
N4.C0.D0.R0: ODT Override: 0x5
N6.C0.D0.R0.S00: StoreJckWorstRank: worst rank = 0, greatestDelay = 1334
N0.C3.D1.R1.S17: RcvEn: plus1 = 1, minus1 = 0, PI = 51, DB = 1
N2.C0.D0.R1.S01: Total Delay in PI ticks: TxDQS = 987, TxDQ = 953
N4.C0.D0.R0.S00: Write Level Fine Value = 508
N6.C1.D0.R0.S00: StoreJckWorstRank: worst rank = 0, greatestDelay = 1378
STOP_DATA_REC_EN
N2.C0.D0.R1.S02: Total Delay in PI ticks: TxDQS = 973, TxDQ = 940
N4.C0.D0.R0.S01: Write Level Fine Value = 488
N6.C1.D0.R1.S00: StoreJckWorstRank: worst rank = 1, greatestDelay = 1380
N0.C0.D0.R0.S00: StoreJckWorstRank: worst rank = 0, greatestDelay = 1320
N2.C0.D0.R1.S03: Total Delay in PI ticks: TxDQS = 956, TxDQ = 921
N4.C0.D0.R0.S02: Write Level Fine Value = 477
N6.C0: StoreJckWorstRank: final value: worst rank = 1
N0.C0.D0.R0.S07: StoreJckWorstRank: worst rank = 0, greatestDelay = 1326
N2.C0.D0.R1.S04: Total Delay in PI ticks: TxDQS = 923, TxDQ = 888
N4.C0.D0.R0.S03: Write Level Fine Value = 457
N6.C2.D0.R0.S00: StoreJckWorstRank: worst rank = 0, greatestDelay = 1333
N0.C1.D0.R0.S00: StoreJckWorstRank: worst rank = 0, greatestDelay = 1374
N2.C0.D0.R1.S05: Total Delay in PI ticks: TxDQS = 940, TxDQ = 906
N4.C0.D0.R0.S04: Write Level Fine Value = 429
N6.C3.D0.R0.S00: StoreJckWorstRank: worst rank = 0, greatestDelay = 1379
N0.C1.D0.R1.S00: StoreJckWorstRank: worst rank = 1, greatestDelay = 1376
N2.C0.D0.R1.S06: Total Delay in PI ticks: TxDQS = 946, TxDQ = 912
N4.C0.D0.R0.S05: Write Level Fine Value = 446
N6.C3.D0.R1.S00: StoreJckWorstRank: worst rank = 1, greatestDelay = 1381
N0.C0: StoreJckWorstRank: final value: worst rank = 1
N2.C0.D0.R1.S07: Total Delay in PI ticks: TxDQS = 960, TxDQ = 926
N4.C0.D0.R0.S06: Write Level Fine Value = 446
N6.C1: StoreJckWorstRank: final value: worst rank = 1
N0.C2.D0.R0.S00: StoreJckWorstRank: worst rank = 0, greatestDelay = 1329
N2.C0.D0.R1.S08: Total Delay in PI ticks: TxDQS = 934, TxDQ = 898
N4.C0.D0.R0.S07: Write Level Fine Value = 462
N6: RunTrainStep: Final status = 0
N0.C2.D0.R0.S09: StoreJckWorstRank: worst rank = 0, greatestDelay = 1330
N2.C0.D0.R1.S09: Total Delay in PI ticks: TxDQS = 1002, TxDQ = 969
N4.C0.D0.R0.S08: Write Level Fine Value = 439

END - Basic Receive Enable Training    Time         64573 ms
N0.C3.D0.R0.S00: StoreJckWorstRank: worst rank = 0, greatestDelay = 1373
N2.C0.D0.R1.S10: Total Delay in PI ticks: TxDQS = 985, TxDQ = 951
N4.C0.D0.R0.S09: Write Level Fine Value = 506
N6.C0.S00: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  6
N0.C3.D0.R0.S09: StoreJckWorstRank: worst rank = 0, greatestDelay = 1375
N2.C0.D0.R1.S11: Total Delay in PI ticks: TxDQS = 975, TxDQ = 942
N4.C0.D0.R0.S10: Write Level Fine Value = 486
N6.C0.S01: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  6
N0.C1: StoreJckWorstRank: final value: worst rank = 0
N2.C0.D0.R1.S12: Total Delay in PI ticks: TxDQS = 960, TxDQ = 926
N4.C0.D0.R0.S11: Write Level Fine Value = 473
N6.C0.S02: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  5
N0: RunTrainStep: Final status = 0
N2.C0.D0.R1.S13: Total Delay in PI ticks: TxDQS = 923, TxDQ = 890
N4.C0.D0.R0.S12: Write Level Fine Value = 458
N6.C0.S03: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  5

END - Basic Receive Enable Training    Time         64655 ms
N2.C0.D0.R1.S14: Total Delay in PI ticks: TxDQS = 941, TxDQ = 908
N4.C0.D0.R0.S13: Write Level Fine Value = 428
N6.C0.S04: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  5
N0.C0.S00: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  6
N2.C0.D0.R1.S15: Total Delay in PI ticks: TxDQS = 946, TxDQ = 912
N4.C0.D0.R0.S14: Write Level Fine Value = 441
N6.C0.S05: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  5
N0.C0.S01: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  6
N2.C0.D0.R1.S16: Total Delay in PI ticks: TxDQS = 961, TxDQ = 927
N4.C0.D0.R0.S15: Write Level Fine Value = 445
N6.C0.S06: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  6
N0.C0.S02: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  5
N2.C0.D0.R1.S17: Total Delay in PI ticks: TxDQS = 935, TxDQ = 901
N4.C0.D0.R0.S16: Write Level Fine Value = 462
N6.C0.S07: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  6
N0.C0.S03: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  5
N2.C0.D1.R0.S00: Total Delay in PI ticks: TxDQS = 1016, TxDQ = 981
N4.C0.D0.R0.S17: Write Level Fine Value = 439
N6.C0.S08: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  5
N0.C0.S04: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  5
N2.C0.D1.R0.S01: Total Delay in PI ticks: TxDQS = 998, TxDQ = 962
N4.C0.D0.R1: ODT Override: 0x6
N6.C1.S00: SuppressionWindowAdjustmentRd: latency =  9, rdptroffset =  5
N0.C0.S05: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  5
N2.C0.D1.R0.S02: Total Delay in PI ticks: TxDQS = 986, TxDQ = 951
N4.C0.D0.R1.S00: Write Level Fine Value = 499
N6.C1.S01: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  6
N0.C0.S06: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  6
N2.C0.D1.R0.S03: Total Delay in PI ticks: TxDQS = 970, TxDQ = 934
N4.C0.D0.R1.S01: Write Level Fine Value = 481
N6.C1.S02: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  6
N0.C0.S07: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  6
N2.C0.D1.R0.S04: Total Delay in PI ticks: TxDQS = 937, TxDQ = 901
N4.C0.D0.R1.S02: Write Level Fine Value = 470
N6.C1.S03: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  6
N0.C0.S08: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  5
N2.C0.D1.R0.S05: Total Delay in PI ticks: TxDQS = 955, TxDQ = 920
N4.C0.D0.R1.S03: Write Level Fine Value = 454
N6.C1.S04: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  6
N0.C1.S00: SuppressionWindowAdjustmentRd: latency =  9, rdptroffset =  5
N2.C0.D1.R0.S06: Total Delay in PI ticks: TxDQS = 957, TxDQ = 921
N4.C0.D0.R1.S04: Write Level Fine Value = 418
N6.C1.S05: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  6
N0.C1.S01: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  6
N2.C0.D1.R0.S07: Total Delay in PI ticks: TxDQS = 974, TxDQ = 938
N4.C0.D0.R1.S05: Write Level Fine Value = 437
N6.C1.S06: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  6
N0.C1.S02: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  6
N2.C0.D1.R0.S08: Total Delay in PI ticks: TxDQS = 944, TxDQ = 907
N4.C0.D0.R1.S06: Write Level Fine Value = 437
N6.C1.S07: SuppressionWindowAdjustmentRd: latency =  9, rdptroffset =  5
N0.C1.S03: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  6
N2.C0.D1.R0.S09: Total Delay in PI ticks: TxDQS = 1017, TxDQ = 982
N4.C0.D0.R1.S07: Write Level Fine Value = 454
N6.C1.S08: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  5
N0.C1.S04: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  5
N2.C0.D1.R0.S10: Total Delay in PI ticks: TxDQS = 997, TxDQ = 961
N4.C0.D0.R1.S08: Write Level Fine Value = 431
N6.C2.S00: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  6
N0.C1.S05: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  6
N2.C0.D1.R0.S11: Total Delay in PI ticks: TxDQS = 989, TxDQ = 954
N4.C0.D0.R1.S09: Write Level Fine Value = 497
N6.C2.S01: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  6
N0.C1.S06: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  6
N2.C0.D1.R0.S12: Total Delay in PI ticks: TxDQS = 973, TxDQ = 938
N4.C0.D0.R1.S10: Write Level Fine Value = 481
N6.C2.S02: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  5
N0.C1.S07: SuppressionWindowAdjustmentRd: latency =  9, rdptroffset =  5
N2.C0.D1.R0.S13: Total Delay in PI ticks: TxDQS = 938, TxDQ = 903
N4.C0.D0.R1.S11: Write Level Fine Value = 471
N6.C2.S03: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  5
N0.C1.S08: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  5
N2.C0.D1.R0.S14: Total Delay in PI ticks: TxDQS = 956, TxDQ = 922
N4.C0.D0.R1.S12: Write Level Fine Value = 455
N6.C2.S04: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  5
N0.C2.S00: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  6
N2.C0.D1.R0.S15: Total Delay in PI ticks: TxDQS = 958, TxDQ = 923
N4.C0.D0.R1.S13: Write Level Fine Value = 422
N6.C2.S05: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  5
N0.C2.S01: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  6
N2.C0.D1.R0.S16: Total Delay in PI ticks: TxDQS = 974, TxDQ = 939
N4.C0.D0.R1.S14: Write Level Fine Value = 435
N6.C2.S06: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  6
N0.C2.S02: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  5
N2.C0.D1.R0.S17: Total Delay in PI ticks: TxDQS = 946, TxDQ = 910
N4.C0.D0.R1.S15: Write Level Fine Value = 439
N6.C2.S07: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  6
N0.C2.S03: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  5
N2.C0.D1.R1.S00: Total Delay in PI ticks: TxDQS = 1011, TxDQ = 975
N4.C0.D0.R1.S16: Write Level Fine Value = 455
N6.C2.S08: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  5
N0.C2.S04: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  5
N2.C0.D1.R1.S01: Total Delay in PI ticks: TxDQS = 996, TxDQ = 961
N4.C0.D0.R1.S17: Write Level Fine Value = 428
N6.C3.S00: SuppressionWindowAdjustmentRd: latency =  9, rdptroffset =  5
N0.C2.S05: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  5
N2.C0.D1.R1.S02: Total Delay in PI ticks: TxDQS = 982, TxDQ = 947
N4.C0.D1.R0: ODT Override: 0x5
N6.C3.S01: SuppressionWindowAdjustmentRd: latency =  9, rdptroffset =  5
N0.C2.S06: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  6
N2.C0.D1.R1.S03: Total Delay in PI ticks: TxDQS = 966, TxDQ = 930
N4.C0.D1.R0.S00: Write Level Fine Value = 507
N6.C3.S02: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  6
N0.C2.S07: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  6
N2.C0.D1.R1.S04: Total Delay in PI ticks: TxDQS = 932, TxDQ = 896
N4.C0.D1.R0.S01: Write Level Fine Value = 494
N6.C3.S03: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  6
N0.C2.S08: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  5
N2.C0.D1.R1.S05: Total Delay in PI ticks: TxDQS = 951, TxDQ = 916
N4.C0.D1.R0.S02: Write Level Fine Value = 480
N6.C3.S04: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  6
N0.C3.S00: SuppressionWindowAdjustmentRd: latency =  9, rdptroffset =  5
N2.C0.D1.R1.S06: Total Delay in PI ticks: TxDQS = 955, TxDQ = 918
N4.C0.D1.R0.S03: Write Level Fine Value = 464
N6.C3.S05: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  6
N0.C3.S01: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  6
N2.C0.D1.R1.S07: Total Delay in PI ticks: TxDQS = 972, TxDQ = 936
N4.C0.D1.R0.S04: Write Level Fine Value = 431
N6.C3.S06: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  6
N0.C3.S02: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  6
N2.C0.D1.R1.S08: Total Delay in PI ticks: TxDQS = 941, TxDQ = 904
N4.C0.D1.R0.S05: Write Level Fine Value = 449
N6.C3.S07: SuppressionWindowAdjustmentRd: latency =  9, rdptroffset =  5
N0.C3.S03: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  6
N2.C0.D1.R1.S09: Total Delay in PI ticks: TxDQS = 1011, TxDQ = 976
N4.C0.D1.R0.S06: Write Level Fine Value = 449
N6.C3.S08: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  5
N0.C3.S04: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  6
N2.C0.D1.R1.S10: Total Delay in PI ticks: TxDQS = 996, TxDQ = 960
N4.C0.D1.R0.S07: Write Level Fine Value = 465

START - Basic Write Level Training
N0.C3.S05: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  6
N2.C0.D1.R1.S11: Total Delay in PI ticks: TxDQS = 984, TxDQ = 949
N4.C0.D1.R0.S08: Write Level Fine Value = 438
N6: START WRITE LEVEL:
N0.C3.S06: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  6
N2.C0.D1.R1.S12: Total Delay in PI ticks: TxDQS = 971, TxDQ = 936
N4.C0.D1.R0.S09: Write Level Fine Value = 505
N6.C0.D0.R0: ODT Override: 0x5
N0.C3.S07: SuppressionWindowAdjustmentRd: latency =  9, rdptroffset =  5
N2.C0.D1.R1.S13: Total Delay in PI ticks: TxDQS = 933, TxDQ = 898
N4.C0.D1.R0.S10: Write Level Fine Value = 494
N6.C0.D0.R0.S00: Write Level Fine Value = 503
N0.C3.S08: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  5
N2.C0.D1.R1.S14: Total Delay in PI ticks: TxDQS = 950, TxDQ = 916
N4.C0.D1.R0.S11: Write Level Fine Value = 480
N6.C0.D0.R0.S01: Write Level Fine Value = 481

START - Basic Write Level Training
N2.C0.D1.R1.S15: Total Delay in PI ticks: TxDQS = 955, TxDQ = 920
N4.C0.D1.R0.S12: Write Level Fine Value = 464
N6.C0.D0.R0.S02: Write Level Fine Value = 471
Checkpoint Code: Socket 0, 0xB7, 0x03, 0x0000
N2.C0.D1.R1.S16: Total Delay in PI ticks: TxDQS = 971, TxDQ = 936
N4.C0.D1.R0.S13: Write Level Fine Value = 431
N6.C0.D0.R0.S03: Write Level Fine Value = 454
N0: START WRITE LEVEL:
N2.C0.D1.R1.S17: Total Delay in PI ticks: TxDQS = 941, TxDQ = 905
N4.C0.D1.R0.S14: Write Level Fine Value = 448
N6.C0.D0.R0.S04: Write Level Fine Value = 420
N0.C0.D0.R0: ODT Override: 0x5
N2.C1.D0.R0: Write Training Coarse, lower nibbles / bytes
N4.C0.D1.R0.S15: Write Level Fine Value = 448
N6.C0.D0.R0.S05: Write Level Fine Value = 440
N0.C0.D0.R0.S00: Write Level Fine Value = 503
N2.C1.D0.R0.S00: Dq Delay estimate: 465
N4.C0.D1.R0.S16: Write Level Fine Value = 465
N6.C0.D0.R0.S06: Write Level Fine Value = 444
N0.C0.D0.R0.S01: Write Level Fine Value = 485
N2.C1.D0.R0.S01: Dq Delay estimate: 446
N4.C0.D1.R0.S17: Write Level Fine Value = 438
N6.C0.D0.R0.S07: Write Level Fine Value = 461
N0.C0.D0.R0.S02: Write Level Fine Value = 476
N2.C1.D0.R0.S02: Dq Delay estimate: 442
N4.C0.D1.R1: ODT Override: 0x9
N6.C0.D0.R0.S08: Write Level Fine Value = 434
N0.C0.D0.R0.S03: Write Level Fine Value = 457
N2.C1.D0.R0.S03: Dq Delay estimate: 421
N4.C0.D1.R1.S00: Write Level Fine Value = 505
N6.C0.D0.R0.S09: Write Level Fine Value = 504
N0.C0.D0.R0.S04: Write Level Fine Value = 425
N2.C1.D0.R0.S04: Dq Delay estimate: 389
N4.C0.D1.R1.S01: Write Level Fine Value = 490
N6.C0.D0.R0.S10: Write Level Fine Value = 481
N0.C0.D0.R0.S05: Write Level Fine Value = 441
N2.C1.D0.R0.S05: Dq Delay estimate: 406
N4.C0.D1.R1.S02: Write Level Fine Value = 478
N6.C0.D0.R0.S11: Write Level Fine Value = 471
N0.C0.D0.R0.S06: Write Level Fine Value = 445
N2.C1.D0.R0.S06: Dq Delay estimate: 418
N4.C0.D1.R1.S03: Write Level Fine Value = 462
N6.C0.D0.R0.S12: Write Level Fine Value = 455
N0.C0.D0.R0.S07: Write Level Fine Value = 462
N2.C1.D0.R0.S07: Dq Delay estimate: 433
N4.C0.D1.R1.S04: Write Level Fine Value = 426
N6.C0.D0.R0.S13: Write Level Fine Value = 421
N0.C0.D0.R0.S08: Write Level Fine Value = 436
N2.C1.D0.R0.S08: Dq Delay estimate: 409
N4.C0.D1.R1.S05: Write Level Fine Value = 446
N6.C0.D0.R0.S14: Write Level Fine Value = 440
N0.C0.D0.R0.S09: Write Level Fine Value = 505
ACCM: 9F 0FFF9F9F 0F0F0F0F
N4.C0.D1.R1.S06: Write Level Fine Value = 446
N6.C0.D0.R0.S15: Write Level Fine Value = 443
N0.C0.D0.R0.S10: Write Level Fine Value = 485
ACCM: 9F 0FFF9F9F 0F0F0F0F
N4.C0.D1.R1.S07: Write Level Fine Value = 463
N6.C0.D0.R0.S16: Write Level Fine Value = 459
N0.C0.D0.R0.S11: Write Level Fine Value = 476
ACCM: 9F FFFF9F9F FFFFFFFF
N4.C0.D1.R1.S08: Write Level Fine Value = 433
N6.C0.D0.R0.S17: Write Level Fine Value = 436
N0.C0.D0.R0.S12: Write Level Fine Value = 460
ACCM: 9F FFFF9F9F FFFFFFFF
N4.C0.D1.R1.S09: Write Level Fine Value = 505
N6.C0.D0.R1: ODT Override: 0x6
N0.C0.D0.R0.S13: Write Level Fine Value = 426
N2.C1.D0.R0: CheckMCTest: result = 0x3FFFF
N4.C0.D1.R1.S10: Write Level Fine Value = 491
N6.C0.D0.R1.S00: Write Level Fine Value = 496
N0.C0.D0.R0.S14: Write Level Fine Value = 441
ACCM: DF 0FFFDFDF 0F0F0F0F
N4.C0.D1.R1.S11: Write Level Fine Value = 478
N6.C0.D0.R1.S01: Write Level Fine Value = 476
N0.C0.D0.R0.S15: Write Level Fine Value = 445
ACCM: DF 0FFFDFDF 0F0F0F0F
N4.C0.D1.R1.S12: Write Level Fine Value = 464
N6.C0.D0.R1.S02: Write Level Fine Value = 465
N0.C0.D0.R0.S16: Write Level Fine Value = 463
ACCM: DF FFFFDFDF FFFFFFFF
N4.C0.D1.R1.S13: Write Level Fine Value = 429
N6.C0.D0.R1.S03: Write Level Fine Value = 448
N0.C0.D0.R0.S17: Write Level Fine Value = 434
ACCM: DF FFFFDFDF FFFFFFFF
N4.C0.D1.R1.S14: Write Level Fine Value = 445
N6.C0.D0.R1.S04: Write Level Fine Value = 414
N0.C0.D0.R1: ODT Override: 0x6
N2.C1.D0.R0: CheckMCTest: result = 0x3FFFF
N4.C0.D1.R1.S15: Write Level Fine Value = 447
N6.C0.D0.R1.S05: Write Level Fine Value = 434
N0.C0.D0.R1.S00: Write Level Fine Value = 498
ACCM: DF 0FFFDFDF 0F0F0F0F
N4.C0.D1.R1.S16: Write Level Fine Value = 463
N6.C0.D0.R1.S06: Write Level Fine Value = 436
N0.C0.D0.R1.S01: Write Level Fine Value = 480
ACCM: DF 0FFFDFDF 0F0F0F0F
N4.C0.D1.R1.S17: Write Level Fine Value = 432
N6.C0.D0.R1.S07: Write Level Fine Value = 454
N0.C0.D0.R1.S02: Write Level Fine Value = 467
ACCM: D0 FBFBDBDB FBF0FBFB
N4.C1.D0.R0: ODT Override: 0x5
N6.C0.D0.R1.S08: Write Level Fine Value = 426
N0.C0.D0.R1.S03: Write Level Fine Value = 451
ACCM: D0 FBFBDBDB FBF0FBFB
N4.C1.D0.R0.S00: Write Level Fine Value = 507
N6.C0.D0.R1.S09: Write Level Fine Value = 494
N0.C0.D0.R1.S04: Write Level Fine Value = 419
N2.C1.D0.R0: CheckMCTest: result = 0x3FFFF
N4.C1.D0.R0.S01: Write Level Fine Value = 489
N6.C0.D0.R1.S10: Write Level Fine Value = 477
N0.C0.D0.R1.S05: Write Level Fine Value = 435
ACCM: DF 0FFFDFDF 0F0F0F0F
N4.C1.D0.R0.S02: Write Level Fine Value = 483
N6.C0.D0.R1.S11: Write Level Fine Value = 464
N0.C0.D0.R1.S06: Write Level Fine Value = 438
ACCM: DF 0FFFDFDF 0F0F0F0F
N4.C1.D0.R0.S03: Write Level Fine Value = 470
N6.C0.D0.R1.S12: Write Level Fine Value = 453
N0.C0.D0.R1.S07: Write Level Fine Value = 454
ACCM: D0 FFFFDFDF FFFDFFFF
N4.C1.D0.R0.S04: Write Level Fine Value = 433
N6.C0.D0.R1.S13: Write Level Fine Value = 415
N0.C0.D0.R1.S08: Write Level Fine Value = 427
ACCM: D0 FFFFDFDF FFFDFFFF
N4.C1.D0.R0.S05: Write Level Fine Value = 443
N6.C0.D0.R1.S14: Write Level Fine Value = 433
N0.C0.D0.R1.S09: Write Level Fine Value = 495
N2.C1.D0.R0: CheckMCTest: result = 0x3FFFF
N4.C1.D0.R0.S06: Write Level Fine Value = 463
N6.C0.D0.R1.S15: Write Level Fine Value = 436
N0.C0.D0.R1.S10: Write Level Fine Value = 481
ACCM: D0 00F0D0D0 00000000
N4.C1.D0.R0.S07: Write Level Fine Value = 475
N6.C0.D0.R1.S16: Write Level Fine Value = 454
N0.C0.D0.R1.S11: Write Level Fine Value = 469
ACCM: D0 00F0D0D0 00000000
N4.C1.D0.R0.S08: Write Level Fine Value = 448
N6.C0.D0.R1.S17: Write Level Fine Value = 426
N0.C0.D0.R1.S12: Write Level Fine Value = 454
ACCM: D0 F0F0D0D0 F0F0F0F0
N4.C1.D0.R0.S09: Write Level Fine Value = 509
N6.C0.D1.R0: ODT Override: 0x5
N0.C0.D0.R1.S13: Write Level Fine Value = 419
ACCM: D0 F0F0D0D0 F0F0F0F0
N4.C1.D0.R0.S10: Write Level Fine Value = 491
N6.C0.D1.R0.S00: Write Level Fine Value = 500
N0.C0.D0.R1.S14: Write Level Fine Value = 437
N2.C1.D0.R0: CheckMCTest: result = 0x3FE00
N4.C1.D0.R0.S11: Write Level Fine Value = 485
N6.C0.D1.R0.S01: Write Level Fine Value = 482
N0.C0.D0.R1.S15: Write Level Fine Value = 440
ACCM: D0 00F0D0D0 00000000
N4.C1.D0.R0.S12: Write Level Fine Value = 466
N6.C0.D1.R0.S02: Write Level Fine Value = 471
N0.C0.D0.R1.S16: Write Level Fine Value = 456
ACCM: D0 00F0D0D0 00000000
N4.C1.D0.R0.S13: Write Level Fine Value = 434
N6.C0.D1.R0.S03: Write Level Fine Value = 458
N0.C0.D0.R1.S17: Write Level Fine Value = 426
ACCM: D0 F0F0D0D0 F0F0F0F0
N4.C1.D0.R0.S14: Write Level Fine Value = 447
N6.C0.D1.R0.S04: Write Level Fine Value = 421
N0.C0.D1.R0: ODT Override: 0x5
ACCM: D0 F0F0D0D0 F0F0F0F0
N4.C1.D0.R0.S15: Write Level Fine Value = 459
N6.C0.D1.R0.S05: Write Level Fine Value = 440
N0.C0.D1.R0.S00: Write Level Fine Value = 510
N2.C1.D0.R0: CheckMCTest: result = 0x3FE00
N4.C1.D0.R0.S16: Write Level Fine Value = 475
N6.C0.D1.R0.S06: Write Level Fine Value = 444
N0.C0.D1.R0.S01: Write Level Fine Value = 492
N2.C1.D0.R0.S00: Offset Found: RdPtrOffsetDqs = 007
N4.C1.D0.R0.S17: Write Level Fine Value = 450
N6.C0.D1.R0.S07: Write Level Fine Value = 461
N0.C0.D1.R0.S02: Write Level Fine Value = 480
N2.C1.D0.R0.S01: Offset Found: RdPtrOffsetDqs = 007
N4.C1.D0.R1: ODT Override: 0x6
N6.C0.D1.R0.S08: Write Level Fine Value = 431
N0.C0.D1.R0.S03: Write Level Fine Value = 463
N2.C1.D0.R0.S02: Offset Found: RdPtrOffsetDqs = 007
N4.C1.D0.R1.S00: Write Level Fine Value = 499
N6.C0.D1.R0.S09: Write Level Fine Value = 503
N0.C0.D1.R0.S04: Write Level Fine Value = 430
N2.C1.D0.R0.S03: Offset Found: RdPtrOffsetDqs = 007
N4.C1.D0.R1.S01: Write Level Fine Value = 485
N6.C0.D1.R0.S10: Write Level Fine Value = 485
N0.C0.D1.R0.S05: Write Level Fine Value = 448
N2.C1.D0.R0.S04: Offset Found: RdPtrOffsetDqs = 006
N4.C1.D0.R1.S02: Write Level Fine Value = 475
N6.C0.D1.R0.S11: Write Level Fine Value = 470
N0.C0.D1.R0.S06: Write Level Fine Value = 448
N2.C1.D0.R0.S05: Offset Found: RdPtrOffsetDqs = 006
N4.C1.D0.R1.S03: Write Level Fine Value = 461
N6.C0.D1.R0.S12: Write Level Fine Value = 458
N0.C0.D1.R0.S07: Write Level Fine Value = 468
N2.C1.D0.R0.S06: Offset Found: RdPtrOffsetDqs = 007
N4.C1.D0.R1.S04: Write Level Fine Value = 426
N6.C0.D1.R0.S13: Write Level Fine Value = 422
N0.C0.D1.R0.S08: Write Level Fine Value = 438
N2.C1.D0.R0.S07: Offset Found: RdPtrOffsetDqs = 007
N4.C1.D0.R1.S05: Write Level Fine Value = 440
N6.C0.D1.R0.S14: Write Level Fine Value = 441
N0.C0.D1.R0.S09: Write Level Fine Value = 507
N2.C1.D0.R0.S08: Offset Found: RdPtrOffsetDqs = 006
N4.C1.D0.R1.S06: Write Level Fine Value = 451
N6.C0.D1.R0.S15: Write Level Fine Value = 445
N0.C0.D1.R0.S10: Write Level Fine Value = 492
N2.C1.D0.R0: Write Training Coarse, upper nibbles
N4.C1.D0.R1.S07: Write Level Fine Value = 472
N6.C0.D1.R0.S16: Write Level Fine Value = 462
N0.C0.D1.R0.S11: Write Level Fine Value = 479
N2.C1.D0.R0.S09: Dq Delay estimate: 467
N4.C1.D0.R1.S08: Write Level Fine Value = 441
N6.C0.D1.R0.S17: Write Level Fine Value = 432
N0.C0.D1.R0.S12: Write Level Fine Value = 466
N2.C1.D0.R0.S10: Dq Delay estimate: 448
N4.C1.D0.R1.S09: Write Level Fine Value = 498
N6.C0.D1.R1: ODT Override: 0x9
N0.C0.D1.R0.S13: Write Level Fine Value = 431
N2.C1.D0.R0.S11: Dq Delay estimate: 443
N4.C1.D0.R1.S10: Write Level Fine Value = 486
N6.C0.D1.R1.S00: Write Level Fine Value = 496
N0.C0.D1.R0.S14: Write Level Fine Value = 447
N2.C1.D0.R0.S12: Dq Delay estimate: 425
N4.C1.D0.R1.S11: Write Level Fine Value = 475
N6.C0.D1.R1.S01: Write Level Fine Value = 480
N0.C0.D1.R0.S15: Write Level Fine Value = 451
N2.C1.D0.R0.S13: Dq Delay estimate: 394
N4.C1.D0.R1.S12: Write Level Fine Value = 462
N6.C0.D1.R1.S02: Write Level Fine Value = 466
N0.C0.D1.R0.S16: Write Level Fine Value = 470
N2.C1.D0.R0.S14: Dq Delay estimate: 403
N4.C1.D0.R1.S13: Write Level Fine Value = 427
N6.C0.D1.R1.S03: Write Level Fine Value = 454
N0.C0.D1.R0.S17: Write Level Fine Value = 439
N2.C1.D0.R0.S15: Dq Delay estimate: 417
N4.C1.D0.R1.S14: Write Level Fine Value = 441
N6.C0.D1.R1.S04: Write Level Fine Value = 418
N0.C0.D1.R1: ODT Override: 0x9
N2.C1.D0.R0.S16: Dq Delay estimate: 436
N4.C1.D0.R1.S15: Write Level Fine Value = 456
N6.C0.D1.R1.S05: Write Level Fine Value = 438
N0.C0.D1.R1.S00: Write Level Fine Value = 505
N2.C1.D0.R0.S17: Dq Delay estimate: 410
N4.C1.D0.R1.S16: Write Level Fine Value = 471
N6.C0.D1.R1.S06: Write Level Fine Value = 440
N0.C0.D1.R1.S01: Write Level Fine Value = 489
ACCM: F0 F0F0F0F0 F0F0F0F0
N4.C1.D0.R1.S17: Write Level Fine Value = 441
N6.C0.D1.R1.S07: Write Level Fine Value = 456
N0.C0.D1.R1.S02: Write Level Fine Value = 478
ACCM: F0 F0F0F0F0 F0F0F0F0
N4.C1.D1.R0: ODT Override: 0x5
N6.C0.D1.R1.S08: Write Level Fine Value = 426
N0.C0.D1.R1.S03: Write Level Fine Value = 462
ACCM: F0 F0F0F0F0 F0F0F0F0
N4.C1.D1.R0.S00: Write Level Fine Value = 509
N6.C0.D1.R1.S09: Write Level Fine Value = 497
N0.C0.D1.R1.S04: Write Level Fine Value = 428
ACCM: F0 F0F0F0F0 F0F0F0F0
N4.C1.D1.R0.S01: Write Level Fine Value = 493
N6.C0.D1.R1.S10: Write Level Fine Value = 481
N0.C0.D1.R1.S05: Write Level Fine Value = 448
N2.C1.D0.R0: CheckMCTest: result = 0x3FE00
N4.C1.D1.R0.S02: Write Level Fine Value = 483
N6.C0.D1.R1.S11: Write Level Fine Value = 470
N0.C0.D1.R1.S06: Write Level Fine Value = 448
ACCM: F0 F0F0F0F0 F0F0F0F0
N4.C1.D1.R0.S03: Write Level Fine Value = 467
N6.C0.D1.R1.S12: Write Level Fine Value = 454
N0.C0.D1.R1.S07: Write Level Fine Value = 464
ACCM: F0 F0F0F0F0 F0F0F0F0
N4.C1.D1.R0.S04: Write Level Fine Value = 433
N6.C0.D1.R1.S13: Write Level Fine Value = 418
N0.C0.D1.R1.S08: Write Level Fine Value = 432
ACCM: F0 F0F0F0F0 F0F0F0F0
N4.C1.D1.R0.S05: Write Level Fine Value = 446
N6.C0.D1.R1.S14: Write Level Fine Value = 437
N0.C0.D1.R1.S09: Write Level Fine Value = 505
ACCM: F0 F0F0F0F0 F0F0F0F0
N4.C1.D1.R0.S06: Write Level Fine Value = 461
N6.C0.D1.R1.S15: Write Level Fine Value = 440
N0.C0.D1.R1.S10: Write Level Fine Value = 490
N2.C1.D0.R0: CheckMCTest: result = 0x3FE00
N4.C1.D1.R0.S07: Write Level Fine Value = 476
N6.C0.D1.R1.S16: Write Level Fine Value = 455
N0.C0.D1.R1.S11: Write Level Fine Value = 478
ACCM: F0 F0F0F0F0 F0F0F0F0
N4.C1.D1.R0.S08: Write Level Fine Value = 446
N6.C0.D1.R1.S17: Write Level Fine Value = 426
N0.C0.D1.R1.S12: Write Level Fine Value = 463
ACCM: F0 F0F0F0F0 F0F0F0F0
N4.C1.D1.R0.S09: Write Level Fine Value = 507
N6.C1.D0.R0: ODT Override: 0x5
N0.C0.D1.R1.S13: Write Level Fine Value = 430
ACCM: 00 B0B0B0B0 B00000B0
N4.C1.D1.R0.S10: Write Level Fine Value = 491
N6.C1.D0.R0.S00: Write Level Fine Value = 500
N0.C0.D1.R1.S14: Write Level Fine Value = 446
ACCM: 00 B0B0B0B0 B00000B0
N4.C1.D1.R0.S11: Write Level Fine Value = 482
N6.C1.D0.R0.S01: Write Level Fine Value = 485
N0.C0.D1.R1.S15: Write Level Fine Value = 449
N2.C1.D0.R0: CheckMCTest: result = 0x3FE00
N4.C1.D1.R0.S12: Write Level Fine Value = 467
N6.C1.D0.R0.S02: Write Level Fine Value = 475
N0.C0.D1.R1.S16: Write Level Fine Value = 464
ACCM: F0 F0F0F0F0 F0F0F0F0
N4.C1.D1.R0.S13: Write Level Fine Value = 432
N6.C1.D0.R0.S03: Write Level Fine Value = 459
N0.C0.D1.R1.S17: Write Level Fine Value = 433
ACCM: F0 F0F0F0F0 F0F0F0F0
N4.C1.D1.R0.S14: Write Level Fine Value = 446
N6.C1.D0.R0.S04: Write Level Fine Value = 426
N0.C1.D0.R0: ODT Override: 0x5
ACCM: 00 F0F0F0F0 F000D0F0
N4.C1.D1.R0.S15: Write Level Fine Value = 459
N6.C1.D0.R0.S05: Write Level Fine Value = 441
N0.C1.D0.R0.S00: Write Level Fine Value = 506
ACCM: 00 F0F0F0F0 F000D0F0
N4.C1.D1.R0.S16: Write Level Fine Value = 480
N6.C1.D0.R0.S06: Write Level Fine Value = 456
N0.C1.D0.R0.S01: Write Level Fine Value = 487
N2.C1.D0.R0: CheckMCTest: result = 0x3FE00
N4.C1.D1.R0.S17: Write Level Fine Value = 444
N6.C1.D0.R0.S07: Write Level Fine Value = 472
N0.C1.D0.R0.S02: Write Level Fine Value = 482
N2.C1.D0.R0: CheckMCTest: passed
N4.C1.D1.R1: ODT Override: 0x9
N6.C1.D0.R0.S08: Write Level Fine Value = 443
N0.C1.D0.R0.S03: Write Level Fine Value = 463
N2.C1.D0.R0: CheckMCTest: passed
N4.C1.D1.R1.S00: Write Level Fine Value = 506
N6.C1.D0.R0.S09: Write Level Fine Value = 501
N0.C1.D0.R0.S04: Write Level Fine Value = 428
N2.C1.D0.R0.S09: Offset Found: RdPtrOffsetDqs = 007
N4.C1.D1.R1.S01: Write Level Fine Value = 490
N6.C1.D0.R0.S10: Write Level Fine Value = 484
N0.C1.D0.R0.S05: Write Level Fine Value = 444
N2.C1.D0.R0.S10: Offset Found: RdPtrOffsetDqs = 007
N4.C1.D1.R1.S02: Write Level Fine Value = 480
N6.C1.D0.R0.S11: Write Level Fine Value = 477
N0.C1.D0.R0.S06: Write Level Fine Value = 461
N2.C1.D0.R0.S11: Offset Found: RdPtrOffsetDqs = 007
N4.C1.D1.R1.S03: Write Level Fine Value = 466
N6.C1.D0.R0.S12: Write Level Fine Value = 460
N0.C1.D0.R0.S07: Write Level Fine Value = 476
N2.C1.D0.R0.S12: Offset Found: RdPtrOffsetDqs = 007
N4.C1.D1.R1.S04: Write Level Fine Value = 431
N6.C1.D0.R0.S13: Write Level Fine Value = 425
N0.C1.D0.R0.S08: Write Level Fine Value = 443
N2.C1.D0.R0.S13: Offset Found: RdPtrOffsetDqs = 006
N4.C1.D1.R1.S05: Write Level Fine Value = 445
N6.C1.D0.R0.S14: Write Level Fine Value = 438
N0.C1.D0.R0.S09: Write Level Fine Value = 506
N2.C1.D0.R0.S14: Offset Found: RdPtrOffsetDqs = 006
N4.C1.D1.R1.S06: Write Level Fine Value = 456
N6.C1.D0.R0.S15: Write Level Fine Value = 454
N0.C1.D0.R0.S10: Write Level Fine Value = 488
N2.C1.D0.R0.S15: Offset Found: RdPtrOffsetDqs = 007
N4.C1.D1.R1.S07: Write Level Fine Value = 474
N6.C1.D0.R0.S16: Write Level Fine Value = 470
N0.C1.D0.R0.S11: Write Level Fine Value = 482
N2.C1.D0.R0.S16: Offset Found: RdPtrOffsetDqs = 007
N4.C1.D1.R1.S08: Write Level Fine Value = 442
N6.C1.D0.R0.S17: Write Level Fine Value = 442
N0.C1.D0.R0.S12: Write Level Fine Value = 463
N2.C1.D0.R0.S17: Offset Found: RdPtrOffsetDqs = 006
N4.C1.D1.R1.S09: Write Level Fine Value = 504
N6.C1.D0.R1: ODT Override: 0x6
N0.C1.D0.R0.S13: Write Level Fine Value = 429
N2.C1.D0.R1: Write Training Coarse, lower nibbles / bytes
N4.C1.D1.R1.S10: Write Level Fine Value = 489
N6.C1.D0.R1.S00: Write Level Fine Value = 496
N0.C1.D0.R0.S14: Write Level Fine Value = 443
N2.C1.D0.R1.S00: Dq Delay estimate: 458
N4.C1.D1.R1.S11: Write Level Fine Value = 479
N6.C1.D0.R1.S01: Write Level Fine Value = 477
N0.C1.D0.R0.S15: Write Level Fine Value = 458
N2.C1.D0.R1.S01: Dq Delay estimate: 439
N4.C1.D1.R1.S12: Write Level Fine Value = 466
N6.C1.D0.R1.S02: Write Level Fine Value = 467
N0.C1.D0.R0.S16: Write Level Fine Value = 476
N2.C1.D0.R1.S02: Dq Delay estimate: 434
N4.C1.D1.R1.S13: Write Level Fine Value = 431
N6.C1.D0.R1.S03: Write Level Fine Value = 452
N0.C1.D0.R0.S17: Write Level Fine Value = 446
N2.C1.D0.R1.S03: Dq Delay estimate: 416
N4.C1.D1.R1.S14: Write Level Fine Value = 444
N6.C1.D0.R1.S04: Write Level Fine Value = 422
N0.C1.D0.R1: ODT Override: 0x6
N2.C1.D0.R1.S04: Dq Delay estimate: 384
N4.C1.D1.R1.S15: Write Level Fine Value = 456
N6.C1.D0.R1.S05: Write Level Fine Value = 434
N0.C1.D0.R1.S00: Write Level Fine Value = 497
N2.C1.D0.R1.S05: Dq Delay estimate: 399
N4.C1.D1.R1.S16: Write Level Fine Value = 474
N6.C1.D0.R1.S06: Write Level Fine Value = 447
N0.C1.D0.R1.S01: Write Level Fine Value = 480
N2.C1.D0.R1.S06: Dq Delay estimate: 411
N4.C1.D1.R1.S17: Write Level Fine Value = 441
N6.C1.D0.R1.S07: Write Level Fine Value = 465
N0.C1.D0.R1.S02: Write Level Fine Value = 473
N2.C1.D0.R1.S07: Dq Delay estimate: 427
N4.C2.D0.R0: ODT Override: 0x5
N6.C1.D0.R1.S08: Write Level Fine Value = 435
N0.C1.D0.R1.S03: Write Level Fine Value = 457
N2.C1.D0.R1.S08: Dq Delay estimate: 401
N4.C2.D0.R0.S00: Write Level Fine Value = 499
N6.C1.D0.R1.S09: Write Level Fine Value = 493
N0.C1.D0.R1.S04: Write Level Fine Value = 422
ACCM: 0F 0F0F0F0F 0F0F0F0F
N4.C2.D0.R0.S01: Write Level Fine Value = 485
N6.C1.D0.R1.S10: Write Level Fine Value = 477
N0.C1.D0.R1.S05: Write Level Fine Value = 437
ACCM: 0F 0F0F0F0F 0F0F0F0F
N4.C2.D0.R0.S02: Write Level Fine Value = 475
N6.C1.D0.R1.S11: Write Level Fine Value = 469
N0.C1.D0.R1.S06: Write Level Fine Value = 451
ACCM: 0F 0F0F0F0F 0F0F0F0F
N4.C2.D0.R0.S03: Write Level Fine Value = 457
N6.C1.D0.R1.S12: Write Level Fine Value = 453
N0.C1.D0.R1.S07: Write Level Fine Value = 469
ACCM: 0F 0F0F0F0F 0F0F0F0F
N4.C2.D0.R0.S04: Write Level Fine Value = 414
N6.C1.D0.R1.S13: Write Level Fine Value = 419
N0.C1.D0.R1.S08: Write Level Fine Value = 438
N2.C1.D0.R1: CheckMCTest: result = 0x1FF
N4.C2.D0.R0.S05: Write Level Fine Value = 444
N6.C1.D0.R1.S14: Write Level Fine Value = 432
N0.C1.D0.R1.S09: Write Level Fine Value = 496
ACCM: 0F 0F0F0F0F 0F0F0F0F
N4.C2.D0.R0.S06: Write Level Fine Value = 446
N6.C1.D0.R1.S15: Write Level Fine Value = 447
N0.C1.D0.R1.S10: Write Level Fine Value = 481
ACCM: 0F 0F0F0F0F 0F0F0F0F
N4.C2.D0.R0.S07: Write Level Fine Value = 464
N6.C1.D0.R1.S16: Write Level Fine Value = 466
N0.C1.D0.R1.S11: Write Level Fine Value = 473
ACCM: 0F 0F0F0F0F 0F0F0F0F
N4.C2.D0.R0.S08: Write Level Fine Value = 437
N6.C1.D0.R1.S17: Write Level Fine Value = 433
N0.C1.D0.R1.S12: Write Level Fine Value = 458
ACCM: 0F 0F0F0F0F 0F0F0F0F
N4.C2.D0.R0.S09: Write Level Fine Value = 502
N6.C1.D1.R0: ODT Override: 0x5
N0.C1.D0.R1.S13: Write Level Fine Value = 424
N2.C1.D0.R1: CheckMCTest: result = 0x1FF
N4.C2.D0.R0.S10: Write Level Fine Value = 488
N6.C1.D1.R0.S00: Write Level Fine Value = 506
N0.C1.D0.R1.S14: Write Level Fine Value = 439
ACCM: 0F 0F0F0F0F 0F0F0F0F
N4.C2.D0.R0.S11: Write Level Fine Value = 476
N6.C1.D1.R0.S01: Write Level Fine Value = 490
N0.C1.D0.R1.S15: Write Level Fine Value = 450
ACCM: 0F 0F0F0F0F 0F0F0F0F
N4.C2.D0.R0.S12: Write Level Fine Value = 458
N6.C1.D1.R0.S02: Write Level Fine Value = 480
N0.C1.D0.R1.S16: Write Level Fine Value = 471
ACCM: 00 0000000B 0B000B0B
N4.C2.D0.R0.S13: Write Level Fine Value = 417
N6.C1.D1.R0.S03: Write Level Fine Value = 464
N0.C1.D0.R1.S17: Write Level Fine Value = 437
ACCM: 00 0000000B 0B000B0B
N4.C2.D0.R0.S14: Write Level Fine Value = 446
N6.C1.D1.R0.S04: Write Level Fine Value = 432
N0.C1.D1.R0: ODT Override: 0x5
N2.C1.D0.R1: CheckMCTest: result = 0x1FF
N4.C2.D0.R0.S15: Write Level Fine Value = 446
N6.C1.D1.R0.S05: Write Level Fine Value = 446
N0.C1.D1.R0.S00: Write Level Fine Value = 505
ACCM: 0F 0F0F0F0F 0F0F0F0F
N4.C2.D0.R0.S16: Write Level Fine Value = 465
N6.C1.D1.R0.S06: Write Level Fine Value = 458
N0.C1.D1.R0.S01: Write Level Fine Value = 488
ACCM: 0F 0F0F0F0F 0F0F0F0F
N4.C2.D0.R0.S17: Write Level Fine Value = 434
N6.C1.D1.R0.S07: Write Level Fine Value = 476
N0.C1.D1.R0.S02: Write Level Fine Value = 481
ACCM: 00 0000000F 0F000B0F
N4.C2.D0.R1: ODT Override: 0x6
N6.C1.D1.R0.S08: Write Level Fine Value = 446
N0.C1.D1.R0.S03: Write Level Fine Value = 467
ACCM: 00 0000000F 0F000B0F
N4.C2.D0.R1.S00: Write Level Fine Value = 492
N6.C1.D1.R0.S09: Write Level Fine Value = 505
N0.C1.D1.R0.S04: Write Level Fine Value = 433
N2.C1.D0.R1: CheckMCTest: result = 0x1FF
N4.C2.D0.R1.S01: Write Level Fine Value = 478
N6.C1.D1.R0.S10: Write Level Fine Value = 489
N0.C1.D1.R0.S05: Write Level Fine Value = 444
N2.C1.D0.R1: CheckMCTest: passed
N4.C2.D0.R1.S02: Write Level Fine Value = 467
N6.C1.D1.R0.S11: Write Level Fine Value = 481
N0.C1.D1.R0.S06: Write Level Fine Value = 463
N2.C1.D0.R1: CheckMCTest: passed
N4.C2.D0.R1.S03: Write Level Fine Value = 452
N6.C1.D1.R0.S12: Write Level Fine Value = 466
N0.C1.D1.R0.S07: Write Level Fine Value = 478
N2.C1.D0.R1.S00: Offset Found: RdPtrOffsetDqs = 007
N4.C2.D0.R1.S04: Write Level Fine Value = 408
N6.C1.D1.R0.S13: Write Level Fine Value = 433
N0.C1.D1.R0.S08: Write Level Fine Value = 445
N2.C1.D0.R1.S01: Offset Found: RdPtrOffsetDqs = 007
N4.C2.D0.R1.S05: Write Level Fine Value = 438
N6.C1.D1.R0.S14: Write Level Fine Value = 446
N0.C1.D1.R0.S09: Write Level Fine Value = 505
N2.C1.D0.R1.S02: Offset Found: RdPtrOffsetDqs = 007
N4.C2.D0.R1.S06: Write Level Fine Value = 435
N6.C1.D1.R0.S15: Write Level Fine Value = 457
N0.C1.D1.R0.S10: Write Level Fine Value = 488
N2.C1.D0.R1.S03: Offset Found: RdPtrOffsetDqs = 007
N4.C2.D0.R1.S07: Write Level Fine Value = 459
N6.C1.D1.R0.S16: Write Level Fine Value = 480
N0.C1.D1.R0.S11: Write Level Fine Value = 482
N2.C1.D0.R1.S04: Offset Found: RdPtrOffsetDqs = 006
N4.C2.D0.R1.S08: Write Level Fine Value = 430
N6.C1.D1.R0.S17: Write Level Fine Value = 445
N0.C1.D1.R0.S12: Write Level Fine Value = 466
N2.C1.D0.R1.S05: Offset Found: RdPtrOffsetDqs = 006
N4.C2.D0.R1.S09: Write Level Fine Value = 492
N6.C1.D1.R1: ODT Override: 0x9
N0.C1.D1.R0.S13: Write Level Fine Value = 431
N2.C1.D0.R1.S06: Offset Found: RdPtrOffsetDqs = 006
N4.C2.D0.R1.S10: Write Level Fine Value = 480
N6.C1.D1.R1.S00: Write Level Fine Value = 502
N0.C1.D1.R0.S14: Write Level Fine Value = 445
N2.C1.D0.R1.S07: Offset Found: RdPtrOffsetDqs = 007
N4.C2.D0.R1.S11: Write Level Fine Value = 467
N6.C1.D1.R1.S01: Write Level Fine Value = 484
N0.C1.D1.R0.S15: Write Level Fine Value = 458
N2.C1.D0.R1.S08: Offset Found: RdPtrOffsetDqs = 006
N4.C2.D0.R1.S12: Write Level Fine Value = 454
N6.C1.D1.R1.S02: Write Level Fine Value = 476
N0.C1.D1.R0.S16: Write Level Fine Value = 476
N2.C1.D0.R1: Write Training Coarse, upper nibbles
N4.C2.D0.R1.S13: Write Level Fine Value = 410
N6.C1.D1.R1.S03: Write Level Fine Value = 460
N0.C1.D1.R0.S17: Write Level Fine Value = 444
N2.C1.D0.R1.S09: Dq Delay estimate: 457
N4.C2.D0.R1.S14: Write Level Fine Value = 439
N6.C1.D1.R1.S04: Write Level Fine Value = 427
N0.C1.D1.R1: ODT Override: 0x9
N2.C1.D0.R1.S10: Dq Delay estimate: 442
N4.C2.D0.R1.S15: Write Level Fine Value = 437
N6.C1.D1.R1.S05: Write Level Fine Value = 443
N0.C1.D1.R1.S00: Write Level Fine Value = 502
N2.C1.D0.R1.S11: Dq Delay estimate: 434
N4.C2.D0.R1.S16: Write Level Fine Value = 457
N6.C1.D1.R1.S06: Write Level Fine Value = 452
N0.C1.D1.R1.S01: Write Level Fine Value = 484
N2.C1.D0.R1.S12: Dq Delay estimate: 419
N4.C2.D0.R1.S17: Write Level Fine Value = 427
N6.C1.D1.R1.S07: Write Level Fine Value = 474
N0.C1.D1.R1.S02: Write Level Fine Value = 476
N2.C1.D0.R1.S13: Dq Delay estimate: 385
N4.C2.D1.R0: ODT Override: 0x5
N6.C1.D1.R1.S08: Write Level Fine Value = 440
N0.C1.D1.R1.S03: Write Level Fine Value = 464
N2.C1.D0.R1.S14: Dq Delay estimate: 399
N4.C2.D1.R0.S00: Write Level Fine Value = 503
N6.C1.D1.R1.S09: Write Level Fine Value = 500
N0.C1.D1.R1.S04: Write Level Fine Value = 429
N2.C1.D0.R1.S15: Dq Delay estimate: 410
N4.C2.D1.R0.S01: Write Level Fine Value = 489
N6.C1.D1.R1.S10: Write Level Fine Value = 487
N0.C1.D1.R1.S05: Write Level Fine Value = 443
N2.C1.D0.R1.S16: Dq Delay estimate: 429
N4.C2.D1.R0.S02: Write Level Fine Value = 479
N6.C1.D1.R1.S11: Write Level Fine Value = 478
N0.C1.D1.R1.S06: Write Level Fine Value = 456
N2.C1.D0.R1.S17: Dq Delay estimate: 405
N4.C2.D1.R0.S03: Write Level Fine Value = 463
N6.C1.D1.R1.S12: Write Level Fine Value = 463
N0.C1.D1.R1.S07: Write Level Fine Value = 475
ACCM: F0 F0F0F0F0 F0F0F0F0
N4.C2.D1.R0.S04: Write Level Fine Value = 421
N6.C1.D1.R1.S13: Write Level Fine Value = 428
N0.C1.D1.R1.S08: Write Level Fine Value = 441
ACCM: F0 F0F0F0F0 F0F0F0F0
N4.C2.D1.R0.S05: Write Level Fine Value = 449
N6.C1.D1.R1.S14: Write Level Fine Value = 443
N0.C1.D1.R1.S09: Write Level Fine Value = 502
ACCM: F0 F0F0F0F0 F0F0F0F0
N4.C2.D1.R0.S06: Write Level Fine Value = 449
N6.C1.D1.R1.S15: Write Level Fine Value = 452
N0.C1.D1.R1.S10: Write Level Fine Value = 488
ACCM: F0 F0F0F0F0 F0F0F0F0
N4.C2.D1.R0.S07: Write Level Fine Value = 469
N6.C1.D1.R1.S16: Write Level Fine Value = 474
N0.C1.D1.R1.S11: Write Level Fine Value = 480
N2.C1.D0.R1: CheckMCTest: result = 0x3FE00
N4.C2.D1.R0.S08: Write Level Fine Value = 437
N6.C1.D1.R1.S17: Write Level Fine Value = 441
N0.C1.D1.R1.S12: Write Level Fine Value = 464
ACCM: F0 F0F0F0F0 F0F0F0F0
N4.C2.D1.R0.S09: Write Level Fine Value = 504
N6.C2.D0.R0: ODT Override: 0x5
N0.C1.D1.R1.S13: Write Level Fine Value = 430
ACCM: F0 F0F0F0F0 F0F0F0F0
N4.C2.D1.R0.S10: Write Level Fine Value = 489
N6.C2.D0.R0.S00: Write Level Fine Value = 495
N0.C1.D1.R1.S14: Write Level Fine Value = 444
ACCM: F0 F0F0F0F0 F0F0F0F0
N4.C2.D1.R0.S11: Write Level Fine Value = 480
N6.C2.D0.R0.S01: Write Level Fine Value = 481
N0.C1.D1.R1.S15: Write Level Fine Value = 457
ACCM: F0 F0F0F0F0 F0F0F0F0
N4.C2.D1.R0.S12: Write Level Fine Value = 464
N6.C2.D0.R0.S02: Write Level Fine Value = 473
N0.C1.D1.R1.S16: Write Level Fine Value = 475
N2.C1.D0.R1: CheckMCTest: result = 0x3FE00
N4.C2.D1.R0.S13: Write Level Fine Value = 422
N6.C2.D0.R0.S03: Write Level Fine Value = 451
N0.C1.D1.R1.S17: Write Level Fine Value = 443
ACCM: F0 F0F0F0F0 F0F0F0F0
N4.C2.D1.R0.S14: Write Level Fine Value = 448
N6.C2.D0.R0.S04: Write Level Fine Value = 413
N0.C2.D0.R0: ODT Override: 0x5
ACCM: F0 F0F0F0F0 F0F0F0F0
N4.C2.D1.R0.S15: Write Level Fine Value = 449
N6.C2.D0.R0.S05: Write Level Fine Value = 441
N0.C2.D0.R0.S00: Write Level Fine Value = 501
ACCM: 00 000000B0 B0000000
N4.C2.D1.R0.S16: Write Level Fine Value = 469
N6.C2.D0.R0.S06: Write Level Fine Value = 441
N0.C2.D0.R0.S01: Write Level Fine Value = 486
ACCM: 00 000000B0 B0000000
N4.C2.D1.R0.S17: Write Level Fine Value = 437
N6.C2.D0.R0.S07: Write Level Fine Value = 463
N0.C2.D0.R0.S02: Write Level Fine Value = 475
N2.C1.D0.R1: CheckMCTest: result = 0x3FE00
N4.C2.D1.R1: ODT Override: 0x9
N6.C2.D0.R0.S08: Write Level Fine Value = 432
N0.C2.D0.R0.S03: Write Level Fine Value = 459
ACCM: F0 F0F0F0F0 F0F0F0F0
N4.C2.D1.R1.S00: Write Level Fine Value = 499
N6.C2.D0.R0.S09: Write Level Fine Value = 496
N0.C2.D0.R0.S04: Write Level Fine Value = 420
ACCM: F0 F0F0F0F0 F0F0F0F0
N4.C2.D1.R1.S01: Write Level Fine Value = 486
N6.C2.D0.R0.S10: Write Level Fine Value = 481
N0.C2.D0.R0.S05: Write Level Fine Value = 448
ACCM: 00 000000F0 B000D000
N4.C2.D1.R1.S02: Write Level Fine Value = 475
N6.C2.D0.R0.S11: Write Level Fine Value = 473
N0.C2.D0.R0.S06: Write Level Fine Value = 447
ACCM: 00 000000F0 B000D000
N4.C2.D1.R1.S03: Write Level Fine Value = 461
N6.C2.D0.R0.S12: Write Level Fine Value = 452
N0.C2.D0.R0.S07: Write Level Fine Value = 466
N2.C1.D0.R1: CheckMCTest: result = 0x3FE00
N4.C2.D1.R1.S04: Write Level Fine Value = 418
N6.C2.D0.R0.S13: Write Level Fine Value = 413
N0.C2.D0.R0.S08: Write Level Fine Value = 440
N2.C1.D0.R1: CheckMCTest: passed
N4.C2.D1.R1.S05: Write Level Fine Value = 447
N6.C2.D0.R0.S14: Write Level Fine Value = 440
N0.C2.D0.R0.S09: Write Level Fine Value = 503
N2.C1.D0.R1: CheckMCTest: passed
N4.C2.D1.R1.S06: Write Level Fine Value = 442
N6.C2.D0.R0.S15: Write Level Fine Value = 441
N0.C2.D0.R0.S10: Write Level Fine Value = 489
N2.C1.D0.R1.S09: Offset Found: RdPtrOffsetDqs = 007
N4.C2.D1.R1.S07: Write Level Fine Value = 466
N6.C2.D0.R0.S16: Write Level Fine Value = 462
N0.C2.D0.R0.S11: Write Level Fine Value = 478
N2.C1.D0.R1.S10: Offset Found: RdPtrOffsetDqs = 007
N4.C2.D1.R1.S08: Write Level Fine Value = 433
N6.C2.D0.R0.S17: Write Level Fine Value = 432
N0.C2.D0.R0.S12: Write Level Fine Value = 458
N2.C1.D0.R1.S11: Offset Found: RdPtrOffsetDqs = 007
N4.C2.D1.R1.S09: Write Level Fine Value = 498
N6.C2.D0.R1: ODT Override: 0x6
N0.C2.D0.R0.S13: Write Level Fine Value = 417
N2.C1.D0.R1.S12: Offset Found: RdPtrOffsetDqs = 007
N4.C2.D1.R1.S10: Write Level Fine Value = 488
N6.C2.D0.R1.S00: Write Level Fine Value = 488
N0.C2.D0.R0.S14: Write Level Fine Value = 446
N2.C1.D0.R1.S13: Offset Found: RdPtrOffsetDqs = 006
N4.C2.D1.R1.S11: Write Level Fine Value = 475
N6.C2.D0.R1.S01: Write Level Fine Value = 473
N0.C2.D0.R0.S15: Write Level Fine Value = 448
N2.C1.D0.R1.S14: Offset Found: RdPtrOffsetDqs = 006
N4.C2.D1.R1.S12: Write Level Fine Value = 461
N6.C2.D0.R1.S02: Write Level Fine Value = 464
N0.C2.D0.R0.S16: Write Level Fine Value = 467
N2.C1.D0.R1.S15: Offset Found: RdPtrOffsetDqs = 006
N4.C2.D1.R1.S13: Write Level Fine Value = 418
N6.C2.D0.R1.S03: Write Level Fine Value = 445
N0.C2.D0.R0.S17: Write Level Fine Value = 439
N2.C1.D0.R1.S16: Offset Found: RdPtrOffsetDqs = 007
N4.C2.D1.R1.S14: Write Level Fine Value = 447
N6.C2.D0.R1.S04: Write Level Fine Value = 406
N0.C2.D0.R1: ODT Override: 0x6
N2.C1.D0.R1.S17: Offset Found: RdPtrOffsetDqs = 006
N4.C2.D1.R1.S15: Write Level Fine Value = 447
N6.C2.D0.R1.S05: Write Level Fine Value = 436
N0.C2.D0.R1.S00: Write Level Fine Value = 494
N2.C1.D1.R0: Write Training Coarse, lower nibbles / bytes
N4.C2.D1.R1.S16: Write Level Fine Value = 465
N6.C2.D0.R1.S06: Write Level Fine Value = 433
N0.C2.D0.R1.S01: Write Level Fine Value = 481
N2.C1.D1.R0.S00: Dq Delay estimate: 467
N4.C2.D1.R1.S17: Write Level Fine Value = 431
N6.C2.D0.R1.S07: Write Level Fine Value = 457
N0.C2.D0.R1.S02: Write Level Fine Value = 471
N2.C1.D1.R0.S01: Dq Delay estimate: 451
N4.C3.D0.R0: ODT Override: 0x5
N6.C2.D0.R1.S08: Write Level Fine Value = 424
N0.C2.D0.R1.S03: Write Level Fine Value = 454
N2.C1.D1.R0.S02: Dq Delay estimate: 445
N4.C3.D0.R0.S00: Write Level Fine Value = 385
N6.C2.D0.R1.S09: Write Level Fine Value = 487
N0.C2.D0.R1.S04: Write Level Fine Value = 414
N2.C1.D1.R0.S03: Dq Delay estimate: 426
N4.C3.D0.R0.S01: Write Level Fine Value = 494
N6.C2.D0.R1.S10: Write Level Fine Value = 474
N0.C2.D0.R1.S05: Write Level Fine Value = 444
N2.C1.D1.R0.S04: Dq Delay estimate: 395
N4.C3.D0.R0.S02: Write Level Fine Value = 487
N6.C2.D0.R1.S11: Write Level Fine Value = 465
N0.C2.D0.R1.S06: Write Level Fine Value = 439
N2.C1.D1.R0.S05: Dq Delay estimate: 411
N4.C3.D0.R0.S03: Write Level Fine Value = 469
N6.C2.D0.R1.S12: Write Level Fine Value = 448
N0.C2.D0.R1.S07: Write Level Fine Value = 462
N2.C1.D1.R0.S06: Dq Delay estimate: 423
N4.C3.D0.R0.S04: Write Level Fine Value = 433
N6.C2.D0.R1.S13: Write Level Fine Value = 406
N0.C2.D0.R1.S08: Write Level Fine Value = 432
N2.C1.D1.R0.S07: Dq Delay estimate: 439
N4.C3.D0.R0.S05: Write Level Fine Value = 447
N6.C2.D0.R1.S14: Write Level Fine Value = 437
N0.C2.D0.R1.S09: Write Level Fine Value = 496
N2.C1.D1.R0.S08: Dq Delay estimate: 408
N4.C3.D0.R0.S06: Write Level Fine Value = 461
N6.C2.D0.R1.S15: Write Level Fine Value = 436
N0.C2.D0.R1.S10: Write Level Fine Value = 481
ACCM: 0F 0F0F0F0F 0F0F0F0F
N4.C3.D0.R0.S07: Write Level Fine Value = 479
N6.C2.D0.R1.S16: Write Level Fine Value = 456
N0.C2.D0.R1.S11: Write Level Fine Value = 472
ACCM: 0F 0F0F0F0F 0F0F0F0F
N4.C3.D0.R0.S08: Write Level Fine Value = 452
N6.C2.D0.R1.S17: Write Level Fine Value = 425
N0.C2.D0.R1.S12: Write Level Fine Value = 454
ACCM: 0F 0F0F0F0F 0F0F0F0F
N4.C3.D0.R0.S09: Write Level Fine Value = 384
N6.C2.D1.R0: ODT Override: 0x5
N0.C2.D0.R1.S13: Write Level Fine Value = 414
ACCM: 0F FF0F0F0F FFFFFF0F
N4.C3.D0.R0.S10: Write Level Fine Value = 493
N6.C2.D1.R0.S00: Write Level Fine Value = 503
N0.C2.D0.R1.S14: Write Level Fine Value = 441
N2.C1.D1.R0: CheckMCTest: result = 0x11DFF
N4.C3.D0.R0.S11: Write Level Fine Value = 485
N6.C2.D1.R0.S01: Write Level Fine Value = 488
N0.C2.D0.R1.S15: Write Level Fine Value = 439
ACCM: 0F 0F0F0F0F 0F0F0F0F
N4.C3.D0.R0.S12: Write Level Fine Value = 470
N6.C2.D1.R0.S02: Write Level Fine Value = 481
N0.C2.D0.R1.S16: Write Level Fine Value = 464
ACCM: 0F 0F0F0F0F 0F0F0F0F
N4.C3.D0.R0.S13: Write Level Fine Value = 433
N6.C2.D1.R0.S03: Write Level Fine Value = 464
N0.C2.D0.R1.S17: Write Level Fine Value = 430
ACCM: 0F 0F0F0F0F 0F0F0F0F
N4.C3.D0.R0.S14: Write Level Fine Value = 446
N6.C2.D1.R0.S04: Write Level Fine Value = 422
N0.C2.D1.R0: ODT Override: 0x5
ACCM: 0F FF0F0F0F FFFFFF0F
N4.C3.D0.R0.S15: Write Level Fine Value = 463
N6.C2.D1.R0.S05: Write Level Fine Value = 451
N0.C2.D1.R0.S00: Write Level Fine Value = 503
N2.C1.D1.R0: CheckMCTest: result = 0x11DFF
N4.C3.D0.R0.S16: Write Level Fine Value = 478
N6.C2.D1.R0.S06: Write Level Fine Value = 448
N0.C2.D1.R0.S01: Write Level Fine Value = 488
ACCM: 0F 0F0F0F0F 0F0F0F0F
N4.C3.D0.R0.S17: Write Level Fine Value = 450
N6.C2.D1.R0.S07: Write Level Fine Value = 473
N0.C2.D1.R0.S02: Write Level Fine Value = 481
ACCM: 0F 0F0F0F0F 0F0F0F0F
N4.C3.D0.R1: ODT Override: 0x6
N6.C2.D1.R0.S08: Write Level Fine Value = 436
N0.C2.D1.R0.S03: Write Level Fine Value = 465
ACCM: 00 0B0B0B0B 00000B0B
N4.C3.D0.R1.S00: Write Level Fine Value = 505
N6.C2.D1.R0.S09: Write Level Fine Value = 503
N0.C2.D1.R0.S04: Write Level Fine Value = 422
ACCM: 00 FB0B0B0B F0F0FB0B
N4.C3.D0.R1.S01: Write Level Fine Value = 489
N6.C2.D1.R0.S10: Write Level Fine Value = 489
N0.C2.D1.R0.S05: Write Level Fine Value = 452
N2.C1.D1.R0: CheckMCTest: result = 0x11DFF
N4.C3.D0.R1.S02: Write Level Fine Value = 476
N6.C2.D1.R0.S11: Write Level Fine Value = 481
N0.C2.D1.R0.S06: Write Level Fine Value = 448
ACCM: 0F 0F0F0F0F 0F0F0F0F
N4.C3.D0.R1.S03: Write Level Fine Value = 465
N6.C2.D1.R0.S12: Write Level Fine Value = 464
N0.C2.D1.R0.S07: Write Level Fine Value = 470
ACCM: 0F 0F0F0F0F 0F0F0F0F
N4.C3.D0.R1.S04: Write Level Fine Value = 426
N6.C2.D1.R0.S13: Write Level Fine Value = 422
N0.C2.D1.R0.S08: Write Level Fine Value = 439
ACCM: 00 0F0F0F0F 000D0F0F
N4.C3.D0.R1.S05: Write Level Fine Value = 439
N6.C2.D1.R0.S14: Write Level Fine Value = 451
N0.C2.D1.R0.S09: Write Level Fine Value = 501
ACCM: 00 FF0F0F0F F0FDFF0F
N4.C3.D0.R1.S06: Write Level Fine Value = 454
N6.C2.D1.R0.S15: Write Level Fine Value = 448
N0.C2.D1.R0.S10: Write Level Fine Value = 491
N2.C1.D1.R0: CheckMCTest: result = 0x11DFF
N4.C3.D0.R1.S07: Write Level Fine Value = 473
N6.C2.D1.R0.S16: Write Level Fine Value = 471
N0.C2.D1.R0.S11: Write Level Fine Value = 480
ACCM: 00 00000000 00000000
N4.C3.D0.R1.S08: Write Level Fine Value = 442
N6.C2.D1.R0.S17: Write Level Fine Value = 439
N0.C2.D1.R0.S12: Write Level Fine Value = 462
ACCM: 00 00000000 00000000
N4.C3.D0.R1.S09: Write Level Fine Value = 503
N6.C2.D1.R1: ODT Override: 0x9
N0.C2.D1.R0.S13: Write Level Fine Value = 423
ACCM: 00 00000000 00000000
N4.C3.D0.R1.S10: Write Level Fine Value = 489
N6.C2.D1.R1.S00: Write Level Fine Value = 498
N0.C2.D1.R0.S14: Write Level Fine Value = 449
ACCM: 00 F0000000 F0F0F000
N4.C3.D0.R1.S11: Write Level Fine Value = 476
N6.C2.D1.R1.S01: Write Level Fine Value = 483
N0.C2.D1.R0.S15: Write Level Fine Value = 451
N2.C1.D1.R0: CheckMCTest: result = 0x11C00
N4.C3.D0.R1.S12: Write Level Fine Value = 467
N6.C2.D1.R1.S02: Write Level Fine Value = 475
N0.C2.D1.R0.S16: Write Level Fine Value = 470
ACCM: 00 00000000 00000000
N4.C3.D0.R1.S13: Write Level Fine Value = 425
N6.C2.D1.R1.S03: Write Level Fine Value = 458
N0.C2.D1.R0.S17: Write Level Fine Value = 439
ACCM: 00 00000000 00000000
N4.C3.D0.R1.S14: Write Level Fine Value = 441
N6.C2.D1.R1.S04: Write Level Fine Value = 417
N0.C2.D1.R1: ODT Override: 0x9
ACCM: 00 00000000 00000000
N4.C3.D0.R1.S15: Write Level Fine Value = 456
N6.C2.D1.R1.S05: Write Level Fine Value = 448
N0.C2.D1.R1.S00: Write Level Fine Value = 499
ACCM: 00 F0000000 F0F0F000
N4.C3.D0.R1.S16: Write Level Fine Value = 474
N6.C2.D1.R1.S06: Write Level Fine Value = 443
N0.C2.D1.R1.S01: Write Level Fine Value = 486
N2.C1.D1.R0: CheckMCTest: result = 0x11C00
N4.C3.D0.R1.S17: Write Level Fine Value = 442
N6.C2.D1.R1.S07: Write Level Fine Value = 469
N0.C2.D1.R1.S02: Write Level Fine Value = 476
N2.C1.D1.R0.S00: Offset Found: RdPtrOffsetDqs = 007
N4.C3.D1.R0: ODT Override: 0x5
N6.C2.D1.R1.S08: Write Level Fine Value = 432
N0.C2.D1.R1.S03: Write Level Fine Value = 460
N2.C1.D1.R0.S01: Offset Found: RdPtrOffsetDqs = 007
N4.C3.D1.R0.S00: Write Level Fine Value = 388
N6.C2.D1.R1.S09: Write Level Fine Value = 496
N0.C2.D1.R1.S04: Write Level Fine Value = 421
N2.C1.D1.R0.S02: Offset Found: RdPtrOffsetDqs = 007
N4.C3.D1.R0.S01: Write Level Fine Value = 502
N6.C2.D1.R1.S10: Write Level Fine Value = 483
N0.C2.D1.R1.S05: Write Level Fine Value = 449
N2.C1.D1.R0.S03: Offset Found: RdPtrOffsetDqs = 007
N4.C3.D1.R0.S02: Write Level Fine Value = 491
N6.C2.D1.R1.S11: Write Level Fine Value = 477
N0.C2.D1.R1.S06: Write Level Fine Value = 444
N2.C1.D1.R0.S04: Offset Found: RdPtrOffsetDqs = 006
N4.C3.D1.R0.S03: Write Level Fine Value = 475
N6.C2.D1.R1.S12: Write Level Fine Value = 463
N0.C2.D1.R1.S07: Write Level Fine Value = 466
N2.C1.D1.R0.S05: Offset Found: RdPtrOffsetDqs = 006
N4.C3.D1.R0.S04: Write Level Fine Value = 441
N6.C2.D1.R1.S13: Write Level Fine Value = 418
N0.C2.D1.R1.S08: Write Level Fine Value = 432
N2.C1.D1.R0.S06: Offset Found: RdPtrOffsetDqs = 007
N4.C3.D1.R0.S05: Write Level Fine Value = 450
N6.C2.D1.R1.S14: Write Level Fine Value = 446
N0.C2.D1.R1.S09: Write Level Fine Value = 499
N2.C1.D1.R0.S07: Offset Found: RdPtrOffsetDqs = 007
N4.C3.D1.R0.S06: Write Level Fine Value = 469
N6.C2.D1.R1.S15: Write Level Fine Value = 446
N0.C2.D1.R1.S10: Write Level Fine Value = 488
N2.C1.D1.R0.S08: Offset Found: RdPtrOffsetDqs = 006
N4.C3.D1.R0.S07: Write Level Fine Value = 485
N6.C2.D1.R1.S16: Write Level Fine Value = 469
N0.C2.D1.R1.S11: Write Level Fine Value = 479
N2.C1.D1.R0: Write Training Coarse, upper nibbles
N4.C3.D1.R0.S08: Write Level Fine Value = 455
N6.C2.D1.R1.S17: Write Level Fine Value = 432
N0.C2.D1.R1.S12: Write Level Fine Value = 462
N2.C1.D1.R0.S09: Dq Delay estimate: 469
N4.C3.D1.R0.S09: Write Level Fine Value = 387
N6.C3.D0.R0: ODT Override: 0x5
N0.C2.D1.R1.S13: Write Level Fine Value = 422
N2.C1.D1.R0.S10: Dq Delay estimate: 451
N4.C3.D1.R0.S10: Write Level Fine Value = 502
N6.C3.D0.R0.S00: Write Level Fine Value = 506
N0.C2.D1.R1.S14: Write Level Fine Value = 448
N2.C1.D1.R0.S11: Dq Delay estimate: 446
N4.C3.D1.R0.S11: Write Level Fine Value = 491
N6.C3.D0.R0.S01: Write Level Fine Value = 490
N0.C2.D1.R1.S15: Write Level Fine Value = 446
N2.C1.D1.R0.S12: Dq Delay estimate: 429
N4.C3.D1.R0.S12: Write Level Fine Value = 479
N6.C3.D0.R0.S02: Write Level Fine Value = 483
N0.C2.D1.R1.S16: Write Level Fine Value = 471
N2.C1.D1.R0.S13: Dq Delay estimate: 395
N4.C3.D1.R0.S13: Write Level Fine Value = 439
N6.C3.D0.R0.S03: Write Level Fine Value = 466
N0.C2.D1.R1.S17: Write Level Fine Value = 433
N2.C1.D1.R0.S14: Dq Delay estimate: 409
N4.C3.D1.R0.S14: Write Level Fine Value = 456
N6.C3.D0.R0.S04: Write Level Fine Value = 429
N0.C3.D0.R0: ODT Override: 0x5
N2.C1.D1.R0.S15: Dq Delay estimate: 421
N4.C3.D1.R0.S15: Write Level Fine Value = 467
N6.C3.D0.R0.S05: Write Level Fine Value = 442
N0.C3.D0.R0.S00: Write Level Fine Value = 386
N2.C1.D1.R0.S16: Dq Delay estimate: 439
N4.C3.D1.R0.S16: Write Level Fine Value = 485
N6.C3.D0.R0.S06: Write Level Fine Value = 458
N0.C3.D0.R0.S01: Write Level Fine Value = 497
N2.C1.D1.R0.S17: Dq Delay estimate: 411
N4.C3.D1.R0.S17: Write Level Fine Value = 456
N6.C3.D0.R0.S07: Write Level Fine Value = 474
N0.C3.D0.R0.S02: Write Level Fine Value = 486
ACCM: F0 F0F0F0F0 F0F0F0F0
N4.C3.D1.R1: ODT Override: 0x9
N6.C3.D0.R0.S08: Write Level Fine Value = 448
N0.C3.D0.R0.S03: Write Level Fine Value = 467
ACCM: F0 F0F0F0F0 F0F0F0F0
N4.C3.D1.R1.S00: Write Level Fine Value = 386
N6.C3.D0.R0.S09: Write Level Fine Value = 507
N0.C3.D0.R0.S04: Write Level Fine Value = 436
ACCM: F0 F0F0F0F0 F0F0F0F0
N4.C3.D1.R1.S01: Write Level Fine Value = 498
N6.C3.D0.R0.S10: Write Level Fine Value = 490
N0.C3.D0.R0.S05: Write Level Fine Value = 449
ACCM: F0 F0F0F0F0 F0F0F0F0
N4.C3.D1.R1.S02: Write Level Fine Value = 487
N6.C3.D0.R0.S11: Write Level Fine Value = 481
N0.C3.D0.R0.S06: Write Level Fine Value = 464
N2.C1.D1.R0: CheckMCTest: result = 0x3FE00
N4.C3.D1.R1.S03: Write Level Fine Value = 474
N6.C3.D0.R0.S12: Write Level Fine Value = 464
N0.C3.D0.R0.S07: Write Level Fine Value = 482
ACCM: F0 F0F0F0F0 F0F0F0F0
N4.C3.D1.R1.S04: Write Level Fine Value = 436
N6.C3.D0.R0.S13: Write Level Fine Value = 429
N0.C3.D0.R0.S08: Write Level Fine Value = 451
ACCM: F0 F0F0F0F0 F0F0F0F0
N4.C3.D1.R1.S05: Write Level Fine Value = 450
N6.C3.D0.R0.S14: Write Level Fine Value = 443
N0.C3.D0.R0.S09: Write Level Fine Value = 385
ACCM: F0 F0F0F0F0 F0F0F0F0
N4.C3.D1.R1.S06: Write Level Fine Value = 464
N6.C3.D0.R0.S15: Write Level Fine Value = 457
N0.C3.D0.R0.S10: Write Level Fine Value = 497
ACCM: F0 F0F0F0F0 F0F0F0F0
N4.C3.D1.R1.S07: Write Level Fine Value = 482
N6.C3.D0.R0.S16: Write Level Fine Value = 475
N0.C3.D0.R0.S11: Write Level Fine Value = 487
N2.C1.D1.R0: CheckMCTest: result = 0x3FE00
N4.C3.D1.R1.S08: Write Level Fine Value = 451
N6.C3.D0.R0.S17: Write Level Fine Value = 446
N0.C3.D0.R0.S12: Write Level Fine Value = 472
ACCM: F0 F0F0F0F0 F0F0F0F0
N4.C3.D1.R1.S09: Write Level Fine Value = 385
N6.C3.D0.R1: ODT Override: 0x6
N0.C3.D0.R0.S13: Write Level Fine Value = 435
ACCM: F0 F0F0F0F0 F0F0F0F0
N4.C3.D1.R1.S10: Write Level Fine Value = 499
N6.C3.D0.R1.S00: Write Level Fine Value = 499
N0.C3.D0.R0.S14: Write Level Fine Value = 448
ACCM: 00 B0B0B0B0 B00000B0
N4.C3.D1.R1.S11: Write Level Fine Value = 488
N6.C3.D0.R1.S01: Write Level Fine Value = 484
N0.C3.D0.R0.S15: Write Level Fine Value = 466
ACCM: 00 B0B0B0B0 B00000B0
N4.C3.D1.R1.S12: Write Level Fine Value = 476
N6.C3.D0.R1.S02: Write Level Fine Value = 474
N0.C3.D0.R0.S16: Write Level Fine Value = 477
N2.C1.D1.R0: CheckMCTest: result = 0x3FE00
N4.C3.D1.R1.S13: Write Level Fine Value = 439
N6.C3.D0.R1.S03: Write Level Fine Value = 458
N0.C3.D0.R0.S17: Write Level Fine Value = 454
ACCM: F0 F0F0F0F0 F0F0F0F0
N4.C3.D1.R1.S14: Write Level Fine Value = 451
N6.C3.D0.R1.S04: Write Level Fine Value = 421
N0.C3.D0.R1: ODT Override: 0x6
ACCM: F0 F0F0F0F0 F0F0F0F0
N4.C3.D1.R1.S15: Write Level Fine Value = 465
N6.C3.D0.R1.S05: Write Level Fine Value = 436
N0.C3.D0.R1.S00: Write Level Fine Value = 507
ACCM: 00 F0F0F0F0 B00000F0
N4.C3.D1.R1.S16: Write Level Fine Value = 484
N6.C3.D0.R1.S06: Write Level Fine Value = 450
N0.C3.D0.R1.S01: Write Level Fine Value = 489
ACCM: 00 F0F0F0F0 B00000F0
N4.C3.D1.R1.S17: Write Level Fine Value = 451
N6.C3.D0.R1.S07: Write Level Fine Value = 467
N0.C3.D0.R1.S02: Write Level Fine Value = 479
N2.C1.D1.R0: CheckMCTest: result = 0x3FE00
N4: END WRITE LEVEL:
N6.C3.D0.R1.S08: Write Level Fine Value = 439
N0.C3.D0.R1.S03: Write Level Fine Value = 465
N2.C1.D1.R0: CheckMCTest: passed
N4: START WRITE LEVEL COARSE:
N6.C3.D0.R1.S09: Write Level Fine Value = 498
N0.C3.D0.R1.S04: Write Level Fine Value = 431
N2.C1.D1.R0: CheckMCTest: passed
N6.C3.D0.R1.S10: Write Level Fine Value = 483
N0.C3.D0.R1.S05: Write Level Fine Value = 442
N2.C1.D1.R0.S09: Offset Found: RdPtrOffsetDqs = 007
N6.C3.D0.R1.S11: Write Level Fine Value = 473
N0.C3.D0.R1.S06: Write Level Fine Value = 457
N2.C1.D1.R0.S10: Offset Found: RdPtrOffsetDqs = 007
N6.C3.D0.R1.S12: Write Level Fine Value = 459
N0.C3.D0.R1.S07: Write Level Fine Value = 475
N2.C1.D1.R0.S11: Offset Found: RdPtrOffsetDqs = 007
N6.C3.D0.R1.S13: Write Level Fine Value = 421
N0.C3.D0.R1.S08: Write Level Fine Value = 445
N2.C1.D1.R0.S12: Offset Found: RdPtrOffsetDqs = 007
N6.C3.D0.R1.S14: Write Level Fine Value = 435
N0.C3.D0.R1.S09: Write Level Fine Value = 506
N2.C1.D1.R0.S13: Offset Found: RdPtrOffsetDqs = 006
N4.C0.D0.R0: Write Training Coarse, lower nibbles / bytes
N6.C3.D0.R1.S15: Write Level Fine Value = 449
N0.C3.D0.R1.S10: Write Level Fine Value = 490
N2.C1.D1.R0.S14: Offset Found: RdPtrOffsetDqs = 006
N4.C0.D0.R0.S00: Dq Delay estimate: 472
N6.C3.D0.R1.S16: Write Level Fine Value = 468
N0.C3.D0.R1.S11: Write Level Fine Value = 479
N2.C1.D1.R0.S15: Offset Found: RdPtrOffsetDqs = 007
N4.C0.D0.R0.S01: Dq Delay estimate: 452
N6.C3.D0.R1.S17: Write Level Fine Value = 437
N0.C3.D0.R1.S12: Write Level Fine Value = 468
N2.C1.D1.R0.S16: Offset Found: RdPtrOffsetDqs = 007
N4.C0.D0.R0.S02: Dq Delay estimate: 439
N6.C3.D1.R0: ODT Override: 0x5
N0.C3.D0.R1.S13: Write Level Fine Value = 431
N2.C1.D1.R0.S17: Offset Found: RdPtrOffsetDqs = 006
N4.C0.D0.R0.S03: Dq Delay estimate: 420
N6.C3.D1.R0.S00: Write Level Fine Value = 386
N0.C3.D0.R1.S14: Write Level Fine Value = 443
N2.C1.D1.R1: Write Training Coarse, lower nibbles / bytes
N4.C0.D0.R0.S04: Dq Delay estimate: 392
N6.C3.D1.R0.S01: Write Level Fine Value = 496
N0.C3.D0.R1.S15: Write Level Fine Value = 456
N2.C1.D1.R1.S00: Dq Delay estimate: 463
N4.C0.D0.R0.S05: Dq Delay estimate: 409
N6.C3.D1.R0.S02: Write Level Fine Value = 484
N0.C3.D0.R1.S16: Write Level Fine Value = 475
N2.C1.D1.R1.S01: Dq Delay estimate: 446
N4.C0.D0.R0.S06: Dq Delay estimate: 408
N6.C3.D1.R0.S03: Write Level Fine Value = 471
N0.C3.D0.R1.S17: Write Level Fine Value = 445
N2.C1.D1.R1.S02: Dq Delay estimate: 440
N4.C0.D0.R0.S07: Dq Delay estimate: 424
N6.C3.D1.R0.S04: Write Level Fine Value = 435
N0.C3.D1.R0: ODT Override: 0x5
N2.C1.D1.R1.S03: Dq Delay estimate: 422
N4.C0.D0.R0.S08: Dq Delay estimate: 402
N6.C3.D1.R0.S05: Write Level Fine Value = 448
N0.C3.D1.R0.S00: Write Level Fine Value = 388
N2.C1.D1.R1.S04: Dq Delay estimate: 390
ACCM: 9F 0FFFFF9F 0F0F0F0F
N6.C3.D1.R0.S06: Write Level Fine Value = 463
N0.C3.D1.R0.S01: Write Level Fine Value = 498
N2.C1.D1.R1.S05: Dq Delay estimate: 406
ACCM: 9F 0FFFFF9F 0F0F0F0F
N6.C3.D1.R0.S07: Write Level Fine Value = 481
N0.C3.D1.R0.S02: Write Level Fine Value = 491
N2.C1.D1.R1.S06: Dq Delay estimate: 418
ACCM: 9F FFFFFF9F FFFFFFFF
N6.C3.D1.R0.S08: Write Level Fine Value = 451
N0.C3.D1.R0.S03: Write Level Fine Value = 472
N2.C1.D1.R1.S07: Dq Delay estimate: 437
ACCM: 9F FFFFFF9F FFFFFFFF
N6.C3.D1.R0.S09: Write Level Fine Value = 386
N0.C3.D1.R0.S04: Write Level Fine Value = 438
N2.C1.D1.R1.S08: Dq Delay estimate: 404
N4.C0.D0.R0: CheckMCTest: result = 0x3FFFF
N6.C3.D1.R0.S10: Write Level Fine Value = 495
N0.C3.D1.R0.S05: Write Level Fine Value = 451
ACCM: 0F 0F0F0F0F 0F0F0F0F
ACCM: DF 0FFFFFDF 0F0F0F0F
N6.C3.D1.R0.S11: Write Level Fine Value = 485
N0.C3.D1.R0.S06: Write Level Fine Value = 465
ACCM: 0F 0F0F0F0F 0F0F0F0F
ACCM: DF 0FFFFFDF 0F0F0F0F
N6.C3.D1.R0.S12: Write Level Fine Value = 471
N0.C3.D1.R0.S07: Write Level Fine Value = 484
ACCM: 0F 0F0F0F0F 0F0F0F0F
ACCM: DF FFFFFFDF FFFFFFFF
N6.C3.D1.R0.S13: Write Level Fine Value = 435
N0.C3.D1.R0.S08: Write Level Fine Value = 452
ACCM: 0F 0F0F0F0F 0F0F0F0F
ACCM: DF FFFFFFDF FFFFFFFF
N6.C3.D1.R0.S14: Write Level Fine Value = 449
N0.C3.D1.R0.S09: Write Level Fine Value = 389
N2.C1.D1.R1: CheckMCTest: result = 0x1FF
N4.C0.D0.R0: CheckMCTest: result = 0x3FFFF
N6.C3.D1.R0.S15: Write Level Fine Value = 463
N0.C3.D1.R0.S10: Write Level Fine Value = 500
ACCM: 0F 0F0F0F0F 0F0F0F0F
ACCM: DF 0FDFFFDF 0F0F0F0F
N6.C3.D1.R0.S16: Write Level Fine Value = 481
N0.C3.D1.R0.S11: Write Level Fine Value = 490
ACCM: 0F 0F0F0F0F 0F0F0F0F
ACCM: DF 0FDFFFDF 0F0F0F0F
N6.C3.D1.R0.S17: Write Level Fine Value = 451
N0.C3.D1.R0.S12: Write Level Fine Value = 474
ACCM: 0F 0F0F0F0F 0F0F0F0F
ACCM: DB F0FBFBDB F0F0F0FB
N6.C3.D1.R1: ODT Override: 0x9
N0.C3.D1.R0.S13: Write Level Fine Value = 439
ACCM: 0F 0F0F0F0F 0F0F0F0F
ACCM: DB F0FBFBDB F0F0F0FB
N6.C3.D1.R1.S00: Write Level Fine Value = 508
N0.C3.D1.R0.S14: Write Level Fine Value = 452
N2.C1.D1.R1: CheckMCTest: result = 0x1FF
N4.C0.D0.R0: CheckMCTest: result = 0x3FFFF
N6.C3.D1.R1.S01: Write Level Fine Value = 491
N0.C3.D1.R0.S15: Write Level Fine Value = 467
ACCM: 0F 0F0F0F0F 0F0F0F0F
ACCM: DF 0FDFFFDF 0F0F0F0F
N6.C3.D1.R1.S02: Write Level Fine Value = 480
N0.C3.D1.R0.S16: Write Level Fine Value = 482
ACCM: 0F 0F0F0F0F 0F0F0F0F
ACCM: DF 0FDFFFDF 0F0F0F0F
N6.C3.D1.R1.S03: Write Level Fine Value = 468
N0.C3.D1.R0.S17: Write Level Fine Value = 450
ACCM: 00 0000000B 0B000000
ACCM: DB F0FFFFDF F0F0F0FF
N6.C3.D1.R1.S04: Write Level Fine Value = 432
N0.C3.D1.R1: ODT Override: 0x9
ACCM: 00 0000000B 0B000000
ACCM: DB F0FFFFDF F0F0F0FF
N6.C3.D1.R1.S05: Write Level Fine Value = 445
N0.C3.D1.R1.S00: Write Level Fine Value = 386
N2.C1.D1.R1: CheckMCTest: result = 0x1FF
N4.C0.D0.R0: CheckMCTest: result = 0x3FFFF
N6.C3.D1.R1.S06: Write Level Fine Value = 459
N0.C3.D1.R1.S01: Write Level Fine Value = 497
ACCM: 0F 0F0F0F0F 0F0F0F0F
ACCM: D0 00F0F0D0 00000000
N6.C3.D1.R1.S07: Write Level Fine Value = 476
N0.C3.D1.R1.S02: Write Level Fine Value = 486
ACCM: 0F 0F0F0F0F 0F0F0F0F
ACCM: D0 00F0F0D0 00000000
N6.C3.D1.R1.S08: Write Level Fine Value = 445
N0.C3.D1.R1.S03: Write Level Fine Value = 472
ACCM: 00 0000000F 0F00000D
ACCM: D0 F0F0F0D0 F0F0F0F0
N6.C3.D1.R1.S09: Write Level Fine Value = 507
N0.C3.D1.R1.S04: Write Level Fine Value = 436
ACCM: 00 0000000F 0F00000D
ACCM: D0 F0F0F0D0 F0F0F0F0
N6.C3.D1.R1.S10: Write Level Fine Value = 491
N0.C3.D1.R1.S05: Write Level Fine Value = 449
N2.C1.D1.R1: CheckMCTest: result = 0x1FF
N4.C0.D0.R0: CheckMCTest: result = 0x3FE00
N6.C3.D1.R1.S11: Write Level Fine Value = 483
N0.C3.D1.R1.S06: Write Level Fine Value = 462
N2.C1.D1.R1: CheckMCTest: passed
ACCM: D0 00F0F0D0 00000000
N6.C3.D1.R1.S12: Write Level Fine Value = 468
N0.C3.D1.R1.S07: Write Level Fine Value = 482
N2.C1.D1.R1: CheckMCTest: passed
ACCM: D0 00F0F0D0 00000000
N6.C3.D1.R1.S13: Write Level Fine Value = 431
N0.C3.D1.R1.S08: Write Level Fine Value = 449
N2.C1.D1.R1.S00: Offset Found: RdPtrOffsetDqs = 007
ACCM: D0 F0F0F0D0 F0F0F0F0
N6.C3.D1.R1.S14: Write Level Fine Value = 445
N0.C3.D1.R1.S09: Write Level Fine Value = 385
N2.C1.D1.R1.S01: Offset Found: RdPtrOffsetDqs = 007
ACCM: D0 F0F0F0D0 F0F0F0F0
N6.C3.D1.R1.S15: Write Level Fine Value = 457
N0.C3.D1.R1.S10: Write Level Fine Value = 498
N2.C1.D1.R1.S02: Offset Found: RdPtrOffsetDqs = 007
N4.C0.D0.R0: CheckMCTest: result = 0x3FE00
N6.C3.D1.R1.S16: Write Level Fine Value = 475
N0.C3.D1.R1.S11: Write Level Fine Value = 486
N2.C1.D1.R1.S03: Offset Found: RdPtrOffsetDqs = 007
N4.C0.D0.R0.S00: Offset Found: RdPtrOffsetDqs = 007
N6.C3.D1.R1.S17: Write Level Fine Value = 445
N0.C3.D1.R1.S12: Write Level Fine Value = 473
N2.C1.D1.R1.S04: Offset Found: RdPtrOffsetDqs = 006
N4.C0.D0.R0.S01: Offset Found: RdPtrOffsetDqs = 007
N6: END WRITE LEVEL:
N0.C3.D1.R1.S13: Write Level Fine Value = 439
N2.C1.D1.R1.S05: Offset Found: RdPtrOffsetDqs = 006
N4.C0.D0.R0.S02: Offset Found: RdPtrOffsetDqs = 007
N6: START WRITE LEVEL COARSE:
N0.C3.D1.R1.S14: Write Level Fine Value = 450
N2.C1.D1.R1.S06: Offset Found: RdPtrOffsetDqs = 007
N4.C0.D0.R0.S03: Offset Found: RdPtrOffsetDqs = 007
N0.C3.D1.R1.S15: Write Level Fine Value = 464
N2.C1.D1.R1.S07: Offset Found: RdPtrOffsetDqs = 007
N4.C0.D0.R0.S04: Offset Found: RdPtrOffsetDqs = 006
N0.C3.D1.R1.S16: Write Level Fine Value = 478
N2.C1.D1.R1.S08: Offset Found: RdPtrOffsetDqs = 006
N4.C0.D0.R0.S05: Offset Found: RdPtrOffsetDqs = 006
N0.C3.D1.R1.S17: Write Level Fine Value = 449
N2.C1.D1.R1: Write Training Coarse, upper nibbles
N4.C0.D0.R0.S06: Offset Found: RdPtrOffsetDqs = 006
N0: END WRITE LEVEL:
N2.C1.D1.R1.S09: Dq Delay estimate: 462
N4.C0.D0.R0.S07: Offset Found: RdPtrOffsetDqs = 007
Checkpoint Code: Socket 0, 0xB7, 0x04, 0x0000
N2.C1.D1.R1.S10: Dq Delay estimate: 447
N4.C0.D0.R0.S08: Offset Found: RdPtrOffsetDqs = 006
N6.C0.D0.R0: Write Training Coarse, lower nibbles / bytes
N0: START WRITE LEVEL COARSE:
N2.C1.D1.R1.S11: Dq Delay estimate: 441
N4.C0.D0.R0: Write Training Coarse, upper nibbles
N6.C0.D0.R0.S00: Dq Delay estimate: 472
N2.C1.D1.R1.S12: Dq Delay estimate: 427
N4.C0.D0.R0.S09: Dq Delay estimate: 468
N6.C0.D0.R0.S01: Dq Delay estimate: 448
N2.C1.D1.R1.S13: Dq Delay estimate: 390
N4.C0.D0.R0.S10: Dq Delay estimate: 449
N6.C0.D0.R0.S02: Dq Delay estimate: 438
N2.C1.D1.R1.S14: Dq Delay estimate: 403
N4.C0.D0.R0.S11: Dq Delay estimate: 436
N6.C0.D0.R0.S03: Dq Delay estimate: 421
N2.C1.D1.R1.S15: Dq Delay estimate: 415
N4.C0.D0.R0.S12: Dq Delay estimate: 421
N6.C0.D0.R0.S04: Dq Delay estimate: 387
N2.C1.D1.R1.S16: Dq Delay estimate: 437
N4.C0.D0.R0.S13: Dq Delay estimate: 392
N6.C0.D0.R0.S05: Dq Delay estimate: 406
N0.C0.D0.R0: Write Training Coarse, lower nibbles / bytes
N2.C1.D1.R1.S17: Dq Delay estimate: 406
N4.C0.D0.R0.S14: Dq Delay estimate: 404
N6.C0.D0.R0.S06: Dq Delay estimate: 411
N0.C0.D0.R0.S00: Dq Delay estimate: 471
ACCM: F0 F0F0F0F0 F0F0F0F0
N4.C0.D0.R0.S15: Dq Delay estimate: 409
N6.C0.D0.R0.S07: Dq Delay estimate: 427
N0.C0.D0.R0.S01: Dq Delay estimate: 452
ACCM: F0 F0F0F0F0 F0F0F0F0
N4.C0.D0.R0.S16: Dq Delay estimate: 425
N6.C0.D0.R0.S08: Dq Delay estimate: 400
N0.C0.D0.R0.S02: Dq Delay estimate: 443
ACCM: F0 F0F0F0F0 F0F0F0F0
N4.C0.D0.R0.S17: Dq Delay estimate: 403
ACCM: 0F 0F9F9F9F 0F0F0F0F
N0.C0.D0.R0.S03: Dq Delay estimate: 424
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: 0F 0F9F9F9F 0F0F0F0F
N0.C0.D0.R0.S04: Dq Delay estimate: 391
N2.C1.D1.R1: CheckMCTest: result = 0x3FE00
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: 0F FF9F9F9F FFFFFFFF
N0.C0.D0.R0.S05: Dq Delay estimate: 407
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: 0F FF9F9F9F FFFFFFFF
N0.C0.D0.R0.S06: Dq Delay estimate: 412
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: F0 F0F0F0F0 F0F0F0F0
N6.C0.D0.R0: CheckMCTest: result = 0x1FFFF
N0.C0.D0.R0.S07: Dq Delay estimate: 428
ACCM: F0 F0F0F0F0 F0F0F0F0
N4.C0.D0.R0: CheckMCTest: result = 0x3FE00
ACCM: 0F 0FDFDFDF 0F0F0F0F
N0.C0.D0.R0.S08: Dq Delay estimate: 403
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: 0F 0FDFDFDF 0F0F0F0F
ACCM: 9F 0FFFFF9F 0F0F0F0F
N2.C1.D1.R1: CheckMCTest: result = 0x3FE00
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: 0F FFDFDFDF FFFFFFFF
ACCM: 9F 0FFFFF9F 0F0F0F0F
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: 0F FFDFDFDF FFFFFFFF
ACCM: 9F FFFFFF9F FFFFFFFF
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: F0 F0F0F0F0 F0F0F0F0
N6.C0.D0.R0: CheckMCTest: result = 0x1FFFF
ACCM: 9F FFFFFF9F FFFFFFFF
ACCM: 00 000000B0 B0000000
N4.C0.D0.R0: CheckMCTest: result = 0x3FE00
ACCM: DF 0FDFDFDF 0F0F0F0F
N0.C0.D0.R0: CheckMCTest: result = 0x3FFFF
ACCM: 00 000000B0 B0000000
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: DF 0FDFDFDF 0F0F0F0F
ACCM: 9F 0FFFFFDF 0F0F0F0F
N2.C1.D1.R1: CheckMCTest: result = 0x3FE00
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: D0 FBDBDBD0 F0F0F0F0
ACCM: 9F 0FFFFFDF 0F0F0F0F
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: B0 000000B0 B00000B0
ACCM: D0 FBDBDBD0 F0F0F0F0
ACCM: 9F FFFFFFDF FFFFFFFF
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: B0 000000B0 B00000B0
N6.C0.D0.R0: CheckMCTest: result = 0x3FFFF
ACCM: 9F FFFFFFDF FFFFFFFF
ACCM: 00 000000F0 F0000000
N4.C0.D0.R0: CheckMCTest: result = 0x3FE00
ACCM: DF 0FDFDFDF 0F0F0F0F
N0.C0.D0.R0: CheckMCTest: result = 0x3FFFF
ACCM: 00 000000F0 F0000000
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: DF 0FDFDFDF 0F0F0F0F
ACCM: DF 0FFFFFDF 0F0F0F0F
N2.C1.D1.R1: CheckMCTest: result = 0x3FE00
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: D0 FFDFDFD0 F0F0FDFD
ACCM: DF 0FFFFFDF 0F0F0F0F
N2.C1.D1.R1: CheckMCTest: passed
ACCM: F0 000000B0 B00000F0
ACCM: D0 FFDFDFD0 F0F0FDFD
ACCM: D0 FBFBF0DB F0FBF0F0
N2.C1.D1.R1: CheckMCTest: passed
ACCM: F0 000000B0 B00000F0
N6.C0.D0.R0: CheckMCTest: result = 0x3FFFF
ACCM: D0 FBFBF0DB F0FBF0F0
N2.C1.D1.R1.S09: Offset Found: RdPtrOffsetDqs = 007
N4.C0.D0.R0: CheckMCTest: result = 0x3FE00
ACCM: 00 00D0D0D0 00000000
N0.C0.D0.R0: CheckMCTest: result = 0x3FFFF
N2.C1.D1.R1.S10: Offset Found: RdPtrOffsetDqs = 007
N4.C0.D0.R0: CheckMCTest: passed
ACCM: 00 00D0D0D0 00000000
ACCM: DF 0FFFFFDF 0F0F0F0F
N2.C1.D1.R1.S11: Offset Found: RdPtrOffsetDqs = 007
N4.C0.D0.R0: CheckMCTest: passed
ACCM: 00 F0D0D0D0 F0F0F0F0
ACCM: DF 0FFFFFDF 0F0F0F0F
N2.C1.D1.R1.S12: Offset Found: RdPtrOffsetDqs = 007
N4.C0.D0.R0.S09: Offset Found: RdPtrOffsetDqs = 007
ACCM: 00 F0D0D0D0 F0F0F0F0
ACCM: D0 FFFFF0DF F0FFF0F0
N2.C1.D1.R1.S13: Offset Found: RdPtrOffsetDqs = 006
N4.C0.D0.R0.S10: Offset Found: RdPtrOffsetDqs = 007
N6.C0.D0.R0: CheckMCTest: result = 0x1FE00
ACCM: D0 FFFFF0DF F0FFF0F0
N2.C1.D1.R1.S14: Offset Found: RdPtrOffsetDqs = 006
N4.C0.D0.R0.S11: Offset Found: RdPtrOffsetDqs = 007
ACCM: 00 00D0D0D0 00000000
N0.C0.D0.R0: CheckMCTest: result = 0x3FFFF
N2.C1.D1.R1.S15: Offset Found: RdPtrOffsetDqs = 007
N4.C0.D0.R0.S12: Offset Found: RdPtrOffsetDqs = 007
ACCM: 00 00D0D0D0 00000000
ACCM: D0 00F0F0D0 00000000
N2.C1.D1.R1.S16: Offset Found: RdPtrOffsetDqs = 007
N4.C0.D0.R0.S13: Offset Found: RdPtrOffsetDqs = 006
ACCM: 00 F0D0D0D0 F0F0F0F0
ACCM: D0 00F0F0D0 00000000
N2.C1.D1.R1.S17: Offset Found: RdPtrOffsetDqs = 006
N4.C0.D0.R0.S14: Offset Found: RdPtrOffsetDqs = 006
ACCM: 00 F0D0D0D0 F0F0F0F0
ACCM: D0 F0F0F0D0 F0F0F0F0
N2.C1: Calculating Optimimum DQS Values
N4.C0.D0.R0.S15: Offset Found: RdPtrOffsetDqs = 006
N6.C0.D0.R0: CheckMCTest: result = 0x1FE00
ACCM: D0 F0F0F0D0 F0F0F0F0
N2.C1.D0.R0.S00: Total Delay in PI ticks: TxDQS = 1010, TxDQ = 977
N4.C0.D0.R0.S16: Offset Found: RdPtrOffsetDqs = 007
N6.C0.D0.R0.S00: Offset Found: RdPtrOffsetDqs = 007
N0.C0.D0.R0: CheckMCTest: result = 0x3FE00
N2.C1.D0.R0.S01: Total Delay in PI ticks: TxDQS = 992, TxDQ = 958
N4.C0.D0.R0.S17: Offset Found: RdPtrOffsetDqs = 006
N6.C0.D0.R0.S01: Offset Found: RdPtrOffsetDqs = 007
ACCM: D0 00F0F0D0 00000000
N2.C1.D0.R0.S02: Total Delay in PI ticks: TxDQS = 987, TxDQ = 954
N4.C0.D0.R1: Write Training Coarse, lower nibbles / bytes
N6.C0.D0.R0.S02: Offset Found: RdPtrOffsetDqs = 007
ACCM: D0 00F0F0D0 00000000
N2.C1.D0.R0.S03: Total Delay in PI ticks: TxDQS = 968, TxDQ = 933
N4.C0.D0.R1.S00: Dq Delay estimate: 463
N6.C0.D0.R0.S03: Offset Found: RdPtrOffsetDqs = 007
ACCM: D0 F0F0F0D0 F0F0F0F0
N2.C1.D0.R0.S04: Total Delay in PI ticks: TxDQS = 936, TxDQ = 901
N4.C0.D0.R1.S01: Dq Delay estimate: 445
N6.C0.D0.R0.S04: Offset Found: RdPtrOffsetDqs = 006
ACCM: D0 F0F0F0D0 F0F0F0F0
N2.C1.D0.R0.S05: Total Delay in PI ticks: TxDQS = 951, TxDQ = 918
N4.C0.D0.R1.S02: Dq Delay estimate: 432
N6.C0.D0.R0.S05: Offset Found: RdPtrOffsetDqs = 006
N0.C0.D0.R0: CheckMCTest: result = 0x3FE00
N2.C1.D0.R0.S06: Total Delay in PI ticks: TxDQS = 963, TxDQ = 930
N4.C0.D0.R1.S03: Dq Delay estimate: 417
N6.C0.D0.R0.S06: Offset Found: RdPtrOffsetDqs = 006
N0.C0.D0.R0.S00: Offset Found: RdPtrOffsetDqs = 007
N2.C1.D0.R0.S07: Total Delay in PI ticks: TxDQS = 979, TxDQ = 945
N4.C0.D0.R1.S04: Dq Delay estimate: 381
N6.C0.D0.R0.S07: Offset Found: RdPtrOffsetDqs = 007
N0.C0.D0.R0.S01: Offset Found: RdPtrOffsetDqs = 007
N2.C1.D0.R0.S08: Total Delay in PI ticks: TxDQS = 951, TxDQ = 921
N4.C0.D0.R1.S05: Dq Delay estimate: 400
N6.C0.D0.R0.S08: Offset Found: RdPtrOffsetDqs = 006
N0.C0.D0.R0.S02: Offset Found: RdPtrOffsetDqs = 007
N2.C1.D0.R0.S09: Total Delay in PI ticks: TxDQS = 1010, TxDQ = 979
N4.C0.D0.R1.S06: Dq Delay estimate: 398
N6.C0.D0.R0: Write Training Coarse, upper nibbles
N0.C0.D0.R0.S03: Offset Found: RdPtrOffsetDqs = 007
N2.C1.D0.R0.S10: Total Delay in PI ticks: TxDQS = 992, TxDQ = 960
N4.C0.D0.R1.S07: Dq Delay estimate: 416
N6.C0.D0.R0.S09: Dq Delay estimate: 471
N0.C0.D0.R0.S04: Offset Found: RdPtrOffsetDqs = 006
N2.C1.D0.R0.S11: Total Delay in PI ticks: TxDQS = 986, TxDQ = 955
N4.C0.D0.R1.S08: Dq Delay estimate: 394
N6.C0.D0.R0.S10: Dq Delay estimate: 450
N0.C0.D0.R0.S05: Offset Found: RdPtrOffsetDqs = 006
N2.C1.D0.R0.S12: Total Delay in PI ticks: TxDQS = 968, TxDQ = 937
ACCM: 0F 0F0F0F0F 0F0F0F0F
N6.C0.D0.R0.S11: Dq Delay estimate: 437
N0.C0.D0.R0.S06: Offset Found: RdPtrOffsetDqs = 006
N2.C1.D0.R0.S13: Total Delay in PI ticks: TxDQS = 936, TxDQ = 906
ACCM: 0F 0F0F0F0F 0F0F0F0F
N6.C0.D0.R0.S12: Dq Delay estimate: 422
N0.C0.D0.R0.S07: Offset Found: RdPtrOffsetDqs = 007
N2.C1.D0.R0.S14: Total Delay in PI ticks: TxDQS = 950, TxDQ = 915
ACCM: 0F 0F0F0F0F 0F0F0F0F
N6.C0.D0.R0.S13: Dq Delay estimate: 388
N0.C0.D0.R0.S08: Offset Found: RdPtrOffsetDqs = 006
N2.C1.D0.R0.S15: Total Delay in PI ticks: TxDQS = 963, TxDQ = 929
ACCM: 0F 0F0F0F0F 0F0F0F0F
N6.C0.D0.R0.S14: Dq Delay estimate: 406
N0.C0.D0.R0: Write Training Coarse, upper nibbles
N2.C1.D0.R0.S16: Total Delay in PI ticks: TxDQS = 982, TxDQ = 948
N4.C0.D0.R1: CheckMCTest: result = 0x1FF
N6.C0.D0.R0.S15: Dq Delay estimate: 408
N0.C0.D0.R0.S09: Dq Delay estimate: 472
N2.C1.D0.R0.S17: Total Delay in PI ticks: TxDQS = 950, TxDQ = 922
ACCM: 0F 0F0F0F0F 0F0F0F0F
N6.C0.D0.R0.S16: Dq Delay estimate: 424
N0.C0.D0.R0.S10: Dq Delay estimate: 452
N2.C1.D0.R1.S00: Total Delay in PI ticks: TxDQS = 1002, TxDQ = 970
ACCM: 0F 0F0F0F0F 0F0F0F0F
N6.C0.D0.R0.S17: Dq Delay estimate: 401
N0.C0.D0.R0.S11: Dq Delay estimate: 443
N2.C1.D0.R1.S01: Total Delay in PI ticks: TxDQS = 985, TxDQ = 951
ACCM: 0F 0F0F0F0F 0F0F0F0F
ACCM: F0 F0F0F0F0 F0F0F0F0
N0.C0.D0.R0.S12: Dq Delay estimate: 426
N2.C1.D0.R1.S02: Total Delay in PI ticks: TxDQS = 979, TxDQ = 946
ACCM: 0F 0F0F0F0F 0F0F0F0F
ACCM: F0 F0F0F0F0 F0F0F0F0
N0.C0.D0.R0.S13: Dq Delay estimate: 392
N2.C1.D0.R1.S03: Total Delay in PI ticks: TxDQS = 962, TxDQ = 928
N4.C0.D0.R1: CheckMCTest: result = 0x1FF
ACCM: F0 F0F0F0F0 F0F0F0F0
N0.C0.D0.R0.S14: Dq Delay estimate: 408
N2.C1.D0.R1.S04: Total Delay in PI ticks: TxDQS = 930, TxDQ = 896
ACCM: 0F 0F0F0F0F 0F0F0F0F
ACCM: F0 F0F0F0F0 F0F0F0F0
N0.C0.D0.R0.S15: Dq Delay estimate: 413
N2.C1.D0.R1.S05: Total Delay in PI ticks: TxDQS = 944, TxDQ = 911
ACCM: 0F 0F0F0F0F 0F0F0F0F
N6.C0.D0.R0: CheckMCTest: result = 0x3FE00
N0.C0.D0.R0.S16: Dq Delay estimate: 430
N2.C1.D0.R1.S06: Total Delay in PI ticks: TxDQS = 955, TxDQ = 923
ACCM: 00 0000000B 0000000B
ACCM: F0 F0F0F0F0 F0F0F0F0
N0.C0.D0.R0.S17: Dq Delay estimate: 400
N2.C1.D0.R1.S07: Total Delay in PI ticks: TxDQS = 973, TxDQ = 939
ACCM: 00 0000000B 0000000B
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: F0 F0F0F0F0 F0F0F0F0
N2.C1.D0.R1.S08: Total Delay in PI ticks: TxDQS = 943, TxDQ = 913
N4.C0.D0.R1: CheckMCTest: result = 0x1FF
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: F0 F0F0F0F0 F0F0F0F0
N2.C1.D0.R1.S09: Total Delay in PI ticks: TxDQS = 1001, TxDQ = 969
ACCM: 0F 0F0F0F0F 0F0F0F0F
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: F0 F0F0F0F0 F0F0F0F0
N2.C1.D0.R1.S10: Total Delay in PI ticks: TxDQS = 985, TxDQ = 954
ACCM: 0F 0F0F0F0F 0F0F0F0F
N6.C0.D0.R0: CheckMCTest: result = 0x3FE00
ACCM: F0 F0F0F0F0 F0F0F0F0
N2.C1.D0.R1.S11: Total Delay in PI ticks: TxDQS = 978, TxDQ = 946
ACCM: 00 0000000B 0000000F
ACCM: F0 F0F0F0F0 F0F0F0F0
N0.C0.D0.R0: CheckMCTest: result = 0x3FE00
N2.C1.D0.R1.S12: Total Delay in PI ticks: TxDQS = 963, TxDQ = 931
ACCM: 00 0000000B 0000000F
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: F0 F0F0F0F0 F0F0F0F0
N2.C1.D0.R1.S13: Total Delay in PI ticks: TxDQS = 929, TxDQ = 897
N4.C0.D0.R1: CheckMCTest: result = 0x1FF
ACCM: 00 00B00000 0000B000
ACCM: F0 F0F0F0F0 F0F0F0F0
N2.C1.D0.R1.S14: Total Delay in PI ticks: TxDQS = 944, TxDQ = 911
N4.C0.D0.R1: CheckMCTest: passed
ACCM: 00 00B00000 0000B000
ACCM: F0 F0F0F0F0 F0F0F0F0
N2.C1.D0.R1.S15: Total Delay in PI ticks: TxDQS = 956, TxDQ = 922
N4.C0.D0.R1: CheckMCTest: passed
N6.C0.D0.R0: CheckMCTest: result = 0x3FE00
ACCM: F0 F0F0F0F0 F0F0F0F0
N2.C1.D0.R1.S16: Total Delay in PI ticks: TxDQS = 975, TxDQ = 941
N4.C0.D0.R1.S00: Offset Found: RdPtrOffsetDqs = 007
ACCM: F0 F0F0F0F0 F0F0F0F0
N0.C0.D0.R0: CheckMCTest: result = 0x3FE00
N2.C1.D0.R1.S17: Total Delay in PI ticks: TxDQS = 944, TxDQ = 917
N4.C0.D0.R1.S01: Offset Found: RdPtrOffsetDqs = 007
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: F0 F0F0F0F0 F0F0F0F0
N2.C1.D1.R0.S00: Total Delay in PI ticks: TxDQS = 1014, TxDQ = 979
N4.C0.D0.R1.S02: Offset Found: RdPtrOffsetDqs = 007
ACCM: 00 00F00000 0000F000
ACCM: F0 F0F0F0F0 F0F0F0F0
N2.C1.D1.R0.S01: Total Delay in PI ticks: TxDQS = 999, TxDQ = 963
N4.C0.D0.R1.S03: Offset Found: RdPtrOffsetDqs = 007
ACCM: 00 00F00000 0000F000
ACCM: 00 B000B0B0 B0B000B0
N2.C1.D1.R0.S02: Total Delay in PI ticks: TxDQS = 992, TxDQ = 957
N4.C0.D0.R1.S04: Offset Found: RdPtrOffsetDqs = 006
N6.C0.D0.R0: CheckMCTest: result = 0x3FE00
ACCM: 00 B000B0B0 B0B000B0
N2.C1.D1.R0.S03: Total Delay in PI ticks: TxDQS = 974, TxDQ = 938
N4.C0.D0.R1.S05: Offset Found: RdPtrOffsetDqs = 006
N6.C0.D0.R0: CheckMCTest: passed
N0.C0.D0.R0: CheckMCTest: result = 0x3FE00
N2.C1.D1.R0.S04: Total Delay in PI ticks: TxDQS = 943, TxDQ = 907
N4.C0.D0.R1.S06: Offset Found: RdPtrOffsetDqs = 006
N6.C0.D0.R0: CheckMCTest: passed
ACCM: F0 F0F0F0F0 F0F0F0F0
N2.C1.D1.R0.S05: Total Delay in PI ticks: TxDQS = 958, TxDQ = 923
N4.C0.D0.R1.S07: Offset Found: RdPtrOffsetDqs = 007
N6.C0.D0.R0.S09: Offset Found: RdPtrOffsetDqs = 007
ACCM: F0 F0F0F0F0 F0F0F0F0
N2.C1.D1.R0.S06: Total Delay in PI ticks: TxDQS = 969, TxDQ = 935
N4.C0.D0.R1.S08: Offset Found: RdPtrOffsetDqs = 006
N6.C0.D0.R0.S10: Offset Found: RdPtrOffsetDqs = 007
ACCM: 00 F000F0B0 F0F000F0
N2.C1.D1.R0.S07: Total Delay in PI ticks: TxDQS = 987, TxDQ = 951
N4.C0.D0.R1: Write Training Coarse, upper nibbles
N6.C0.D0.R0.S11: Offset Found: RdPtrOffsetDqs = 007
ACCM: 00 F000F0B0 F0F000F0
N2.C1.D1.R0.S08: Total Delay in PI ticks: TxDQS = 954, TxDQ = 920
N4.C0.D0.R1.S09: Dq Delay estimate: 459
N6.C0.D0.R0.S12: Offset Found: RdPtrOffsetDqs = 007
N0.C0.D0.R0: CheckMCTest: result = 0x3FE00
N2.C1.D1.R0.S09: Total Delay in PI ticks: TxDQS = 1016, TxDQ = 981
N4.C0.D0.R1.S10: Dq Delay estimate: 445
N6.C0.D0.R0.S13: Offset Found: RdPtrOffsetDqs = 006
N0.C0.D0.R0: CheckMCTest: passed
N2.C1.D1.R0.S10: Total Delay in PI ticks: TxDQS = 998, TxDQ = 963
N4.C0.D0.R1.S11: Dq Delay estimate: 434
N6.C0.D0.R0.S14: Offset Found: RdPtrOffsetDqs = 006
N0.C0.D0.R0: CheckMCTest: passed
N2.C1.D1.R0.S11: Total Delay in PI ticks: TxDQS = 992, TxDQ = 958
N4.C0.D0.R1.S12: Dq Delay estimate: 417
N6.C0.D0.R0.S15: Offset Found: RdPtrOffsetDqs = 006
N0.C0.D0.R0.S09: Offset Found: RdPtrOffsetDqs = 007
N2.C1.D1.R0.S12: Total Delay in PI ticks: TxDQS = 976, TxDQ = 941
N4.C0.D0.R1.S13: Dq Delay estimate: 386
N6.C0.D0.R0.S16: Offset Found: RdPtrOffsetDqs = 007
N0.C0.D0.R0.S10: Offset Found: RdPtrOffsetDqs = 007
N2.C1.D1.R0.S13: Total Delay in PI ticks: TxDQS = 942, TxDQ = 907
N4.C0.D0.R1.S14: Dq Delay estimate: 398
N6.C0.D0.R0.S17: Offset Found: RdPtrOffsetDqs = 006
N0.C0.D0.R0.S11: Offset Found: RdPtrOffsetDqs = 007
N2.C1.D1.R0.S14: Total Delay in PI ticks: TxDQS = 957, TxDQ = 921
N4.C0.D0.R1.S15: Dq Delay estimate: 403
N6.C0.D0.R1: Write Training Coarse, lower nibbles / bytes
N0.C0.D0.R0.S12: Offset Found: RdPtrOffsetDqs = 007
N2.C1.D1.R0.S15: Total Delay in PI ticks: TxDQS = 969, TxDQ = 933
N4.C0.D0.R1.S16: Dq Delay estimate: 419
N6.C0.D0.R1.S00: Dq Delay estimate: 464
N0.C0.D0.R0.S13: Offset Found: RdPtrOffsetDqs = 006
N2.C1.D1.R0.S16: Total Delay in PI ticks: TxDQS = 986, TxDQ = 951
N4.C0.D0.R1.S17: Dq Delay estimate: 392
N6.C0.D0.R1.S01: Dq Delay estimate: 443
N0.C0.D0.R0.S14: Offset Found: RdPtrOffsetDqs = 006
N2.C1.D1.R0.S17: Total Delay in PI ticks: TxDQS = 954, TxDQ = 923
ACCM: F0 F0F0F0F0 F0F0F0F0
N6.C0.D0.R1.S02: Dq Delay estimate: 431
N0.C0.D0.R0.S15: Offset Found: RdPtrOffsetDqs = 006
N2.C1.D1.R1.S00: Total Delay in PI ticks: TxDQS = 1010, TxDQ = 975
ACCM: F0 F0F0F0F0 F0F0F0F0
N6.C0.D0.R1.S03: Dq Delay estimate: 415
N0.C0.D0.R0.S16: Offset Found: RdPtrOffsetDqs = 007
N2.C1.D1.R1.S01: Total Delay in PI ticks: TxDQS = 994, TxDQ = 958
ACCM: F0 F0F0F0F0 F0F0F0F0
N6.C0.D0.R1.S04: Dq Delay estimate: 381
N0.C0.D0.R0.S17: Offset Found: RdPtrOffsetDqs = 006
N2.C1.D1.R1.S02: Total Delay in PI ticks: TxDQS = 987, TxDQ = 952
ACCM: F0 F0F0F0F0 F0F0F0F0
N6.C0.D0.R1.S05: Dq Delay estimate: 400
N0.C0.D0.R1: Write Training Coarse, lower nibbles / bytes
N2.C1.D1.R1.S03: Total Delay in PI ticks: TxDQS = 970, TxDQ = 934
N4.C0.D0.R1: CheckMCTest: result = 0x3FE00
N6.C0.D0.R1.S06: Dq Delay estimate: 403
N0.C0.D0.R1.S00: Dq Delay estimate: 465
N2.C1.D1.R1.S04: Total Delay in PI ticks: TxDQS = 938, TxDQ = 902
ACCM: F0 F0F0F0F0 F0F0F0F0
N6.C0.D0.R1.S07: Dq Delay estimate: 420
N0.C0.D0.R1.S01: Dq Delay estimate: 447
N2.C1.D1.R1.S05: Total Delay in PI ticks: TxDQS = 953, TxDQ = 918
ACCM: F0 F0F0F0F0 F0F0F0F0
N6.C0.D0.R1.S08: Dq Delay estimate: 392
N0.C0.D0.R1.S02: Dq Delay estimate: 434
N2.C1.D1.R1.S06: Total Delay in PI ticks: TxDQS = 965, TxDQ = 930
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: 0F 0F0F0F0F 0F0F0F0F
N0.C0.D0.R1.S03: Dq Delay estimate: 418
N2.C1.D1.R1.S07: Total Delay in PI ticks: TxDQS = 984, TxDQ = 949
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: 0F 0F0F0F0F 0F0F0F0F
N0.C0.D0.R1.S04: Dq Delay estimate: 385
N2.C1.D1.R1.S08: Total Delay in PI ticks: TxDQS = 950, TxDQ = 916
N4.C0.D0.R1: CheckMCTest: result = 0x3FE00
ACCM: 0F 0F0F0F0F 0F0F0F0F
N0.C0.D0.R1.S05: Dq Delay estimate: 400
N2.C1.D1.R1.S09: Total Delay in PI ticks: TxDQS = 1009, TxDQ = 974
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: 0F 0F0F0F0F 0F0F0F0F
N0.C0.D0.R1.S06: Dq Delay estimate: 405
N2.C1.D1.R1.S10: Total Delay in PI ticks: TxDQS = 994, TxDQ = 959
ACCM: F0 F0F0F0F0 F0F0F0F0
N6.C0.D0.R1: CheckMCTest: result = 0x1FF
N0.C0.D0.R1.S07: Dq Delay estimate: 420
N2.C1.D1.R1.S11: Total Delay in PI ticks: TxDQS = 987, TxDQ = 953
ACCM: 00 00000000 00B0B000
ACCM: 0F 0F0F0F0F 0F0F0F0F
N0.C0.D0.R1.S08: Dq Delay estimate: 394
N2.C1.D1.R1.S12: Total Delay in PI ticks: TxDQS = 974, TxDQ = 939
ACCM: 00 00000000 00B0B000
ACCM: 0F 0F0F0F0F 0F0F0F0F
ACCM: 0F 0F0F0F0F 0F0F0F0F
N2.C1.D1.R1.S13: Total Delay in PI ticks: TxDQS = 937, TxDQ = 902
N4.C0.D0.R1: CheckMCTest: result = 0x3FE00
ACCM: 0F 0F0F0F0F 0F0F0F0F
ACCM: 0F 0F0F0F0F 0F0F0F0F
N2.C1.D1.R1.S14: Total Delay in PI ticks: TxDQS = 952, TxDQ = 915
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: 0F 0F0F0F0F 0F0F0F0F
ACCM: 0F 0F0F0F0F 0F0F0F0F
N2.C1.D1.R1.S15: Total Delay in PI ticks: TxDQS = 963, TxDQ = 927
ACCM: F0 F0F0F0F0 F0F0F0F0
N6.C0.D0.R1: CheckMCTest: result = 0x1FF
ACCM: 0F 0F0F0F0F 0F0F0F0F
N2.C1.D1.R1.S16: Total Delay in PI ticks: TxDQS = 984, TxDQ = 949
ACCM: 00 00000000 00F0F000
ACCM: 0F 0F0F0F0F 0F0F0F0F
N0.C0.D0.R1: CheckMCTest: result = 0x1FF
N2.C1.D1.R1.S17: Total Delay in PI ticks: TxDQS = 949, TxDQ = 918
ACCM: 00 00000000 00F0F000
ACCM: 0F 0F0F0F0F 0F0F0F0F
ACCM: 0F 0F0F0F0F 0F0F0F0F
N2.C2.D0.R0: Write Training Coarse, lower nibbles / bytes
N4.C0.D0.R1: CheckMCTest: result = 0x3FE00
ACCM: 00 0000000B 0B000B0B
ACCM: 0F 0F0F0F0F 0F0F0F0F
N2.C2.D0.R0.S00: Dq Delay estimate: 464
N4.C0.D0.R1: CheckMCTest: passed
ACCM: 00 0000000B 0B000B0B
ACCM: 0F 0F0F0F0F 0F0F0F0F
N2.C2.D0.R0.S01: Dq Delay estimate: 448
N4.C0.D0.R1: CheckMCTest: passed
N6.C0.D0.R1: CheckMCTest: result = 0x1FF
ACCM: 0F 0F0F0F0F 0F0F0F0F
N2.C2.D0.R0.S02: Dq Delay estimate: 437
N4.C0.D0.R1.S09: Offset Found: RdPtrOffsetDqs = 007
ACCM: 0F 0F0F0F0F 0F0F0F0F
N0.C0.D0.R1: CheckMCTest: result = 0x1FF
N2.C2.D0.R0.S03: Dq Delay estimate: 420
N4.C0.D0.R1.S10: Offset Found: RdPtrOffsetDqs = 007
ACCM: 0F 0F0F0F0F 0F0F0F0F
ACCM: 0F 0F0F0F0F 0F0F0F0F
N2.C2.D0.R0.S04: Dq Delay estimate: 380
N4.C0.D0.R1.S11: Offset Found: RdPtrOffsetDqs = 007
ACCM: 00 0000000B 0B000F0F
ACCM: 0F 0F0F0F0F 0F0F0F0F
N2.C2.D0.R0.S05: Dq Delay estimate: 406
N4.C0.D0.R1.S12: Offset Found: RdPtrOffsetDqs = 007
ACCM: 00 0000000B 0B000F0F
ACCM: 0B 0B0B0000 00000000
N2.C2.D0.R0.S06: Dq Delay estimate: 407
N4.C0.D0.R1.S13: Offset Found: RdPtrOffsetDqs = 006
N6.C0.D0.R1: CheckMCTest: result = 0x1FF
ACCM: 0B 0B0B0000 00000000
N2.C2.D0.R0.S07: Dq Delay estimate: 426
N4.C0.D0.R1.S14: Offset Found: RdPtrOffsetDqs = 006
N6.C0.D0.R1: CheckMCTest: passed
N0.C0.D0.R1: CheckMCTest: result = 0x1FF
N2.C2.D0.R0.S08: Dq Delay estimate: 400
N4.C0.D0.R1.S15: Offset Found: RdPtrOffsetDqs = 006
N6.C0.D0.R1: CheckMCTest: passed
ACCM: 0F 0F0F0F0F 0F0F0F0F
ACCM: 0F 0F9F9F9F 0F0F0F0F
N4.C0.D0.R1.S16: Offset Found: RdPtrOffsetDqs = 007
N6.C0.D0.R1.S00: Offset Found: RdPtrOffsetDqs = 007
ACCM: 0F 0F0F0F0F 0F0F0F0F
ACCM: 0F 0F9F9F9F 0F0F0F0F
N4.C0.D0.R1.S17: Offset Found: RdPtrOffsetDqs = 006
N6.C0.D0.R1.S01: Offset Found: RdPtrOffsetDqs = 007
ACCM: 0F 0F0F0000 00000000
ACCM: 0F FF9F9F9F FFFFFFFF
N4.C0.D1.R0: Write Training Coarse, lower nibbles / bytes
N6.C0.D0.R1.S02: Offset Found: RdPtrOffsetDqs = 007
ACCM: 0F 0F0F0000 00000000
ACCM: 0F FF9F9F9F FFFFFFFF
N4.C0.D1.R0.S00: Dq Delay estimate: 469
N6.C0.D0.R1.S03: Offset Found: RdPtrOffsetDqs = 007
N0.C0.D0.R1: CheckMCTest: result = 0x1FF
N2.C2.D0.R0: CheckMCTest: result = 0x1FFFF
N4.C0.D1.R0.S01: Dq Delay estimate: 455
N6.C0.D0.R1.S04: Offset Found: RdPtrOffsetDqs = 006
N0.C0.D0.R1: CheckMCTest: passed
ACCM: 0F 0FDFDFDF 0F0F0F0F
N4.C0.D1.R0.S02: Dq Delay estimate: 441
N6.C0.D0.R1.S05: Offset Found: RdPtrOffsetDqs = 006
N0.C0.D0.R1: CheckMCTest: passed
ACCM: 0F 0FDFDFDF 0F0F0F0F
N4.C0.D1.R0.S03: Dq Delay estimate: 426
N6.C0.D0.R1.S06: Offset Found: RdPtrOffsetDqs = 006
N0.C0.D0.R1.S00: Offset Found: RdPtrOffsetDqs = 007
ACCM: 0F FFDFDFDF FFFFFFFF
N4.C0.D1.R0.S04: Dq Delay estimate: 392
N6.C0.D0.R1.S07: Offset Found: RdPtrOffsetDqs = 007
N0.C0.D0.R1.S01: Offset Found: RdPtrOffsetDqs = 007
ACCM: 0F FFDFDFDF FFFFFFFF
N4.C0.D1.R0.S05: Dq Delay estimate: 411
N6.C0.D0.R1.S08: Offset Found: RdPtrOffsetDqs = 006
N0.C0.D0.R1.S02: Offset Found: RdPtrOffsetDqs = 007
N2.C2.D0.R0: CheckMCTest: result = 0x1FFFF
N4.C0.D1.R0.S06: Dq Delay estimate: 410
N6.C0.D0.R1: Write Training Coarse, upper nibbles
N0.C0.D0.R1.S03: Offset Found: RdPtrOffsetDqs = 007
ACCM: 0F 0FDFDFDF 0F0F0F0F
N4.C0.D1.R0.S07: Dq Delay estimate: 425
N6.C0.D0.R1.S09: Dq Delay estimate: 460
N0.C0.D0.R1.S04: Offset Found: RdPtrOffsetDqs = 006
ACCM: 0F 0FDFDFDF 0F0F0F0F
N4.C0.D1.R0.S08: Dq Delay estimate: 398
N6.C0.D0.R1.S10: Dq Delay estimate: 446
N0.C0.D0.R1.S05: Offset Found: RdPtrOffsetDqs = 006
ACCM: 00 FBD0DBDA F0F0F0F0
ACCM: 0F 0F0F0F0F 0F0F0F0F
N6.C0.D0.R1.S11: Dq Delay estimate: 432
N0.C0.D0.R1.S06: Offset Found: RdPtrOffsetDqs = 006
ACCM: 00 FBD0DBDA F0F0F0F0
ACCM: 0F 0F0F0F0F 0F0F0F0F
N6.C0.D0.R1.S12: Dq Delay estimate: 419
N0.C0.D0.R1.S07: Offset Found: RdPtrOffsetDqs = 007
N2.C2.D0.R0: CheckMCTest: result = 0x1FFFF
ACCM: 0F 0F0F0F0F 0F0F0F0F
N6.C0.D0.R1.S13: Dq Delay estimate: 382
N0.C0.D0.R1.S08: Offset Found: RdPtrOffsetDqs = 006
ACCM: 0F 0FDFDFDF 0F0F0F0F
ACCM: 0F FF0F0F0F FFFFFF0F
N6.C0.D0.R1.S14: Dq Delay estimate: 399
N0.C0.D0.R1: Write Training Coarse, upper nibbles
ACCM: 0F 0FDFDFDF 0F0F0F0F
N4.C0.D1.R0: CheckMCTest: result = 0x11DFF
N6.C0.D0.R1.S15: Dq Delay estimate: 402
N0.C0.D0.R1.S09: Dq Delay estimate: 462
ACCM: 00 FFDDDFDA F0F0F0FD
ACCM: 0F 0F0F0F0F 0F0F0F0F
N6.C0.D0.R1.S16: Dq Delay estimate: 418
N0.C0.D0.R1.S10: Dq Delay estimate: 447
ACCM: 00 FFDDDFDA F0F0F0FD
ACCM: 0F 0F0F0F0F 0F0F0F0F
N6.C0.D0.R1.S17: Dq Delay estimate: 392
N0.C0.D0.R1.S11: Dq Delay estimate: 436
N2.C2.D0.R0: CheckMCTest: result = 0x1FFFF
ACCM: 0F 0F0F0F0F 0F0F0F0F
ACCM: F0 F0F0F0F0 F0F0F0F0
N0.C0.D0.R1.S12: Dq Delay estimate: 421
ACCM: 00 00D0D0D0 00000000
ACCM: 0F FF0F0F0F FFFFFF0F
ACCM: F0 F0F0F0F0 F0F0F0F0
N0.C0.D0.R1.S13: Dq Delay estimate: 385
ACCM: 00 00D0D0D0 00000000
N4.C0.D1.R0: CheckMCTest: result = 0x11DFF
ACCM: F0 F0F0F0F0 F0F0F0F0
N0.C0.D0.R1.S14: Dq Delay estimate: 404
ACCM: 00 F0D0D0D0 F0F0F0F0
ACCM: 0F 0F0F0F0F 0F0F0F0F
ACCM: F0 F0F0F0F0 F0F0F0F0
N0.C0.D0.R1.S15: Dq Delay estimate: 407
ACCM: 00 F0D0D0D0 F0F0F0F0
ACCM: 0F 0F0F0F0F 0F0F0F0F
N6.C0.D0.R1: CheckMCTest: result = 0x3FE00
N0.C0.D0.R1.S16: Dq Delay estimate: 424
N2.C2.D0.R0: CheckMCTest: result = 0x1FE00
ACCM: 00 000B0000 000B0B00
ACCM: F0 F0F0F0F0 F0F0F0F0
N0.C0.D0.R1.S17: Dq Delay estimate: 392
ACCM: 00 00D0D0D0 00000000
ACCM: 00 F00B0000 F0FBFB00
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: 00 00D0D0D0 00000000
N4.C0.D1.R0: CheckMCTest: result = 0x11DFF
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: 00 F0D0D0D0 F0F0F0F0
ACCM: 0F 0F0F0F0F 0F0F0F0F
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: 00 F0D0D0D0 F0F0F0F0
ACCM: 0F 0F0F0F0F 0F0F0F0F
N6.C0.D0.R1: CheckMCTest: result = 0x3FE00
ACCM: F0 F0F0F0F0 F0F0F0F0
N2.C2.D0.R0: CheckMCTest: result = 0x1FE00
ACCM: 00 000F0000 000F0F00
ACCM: F0 F0F0F0F0 F0F0F0F0
N0.C0.D0.R1: CheckMCTest: result = 0x3FE00
N2.C2.D0.R0.S00: Offset Found: RdPtrOffsetDqs = 007
ACCM: 00 F00F0000 F0FFFF00
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: F0 F0F0F0F0 F0F0F0F0
N2.C2.D0.R0.S01: Offset Found: RdPtrOffsetDqs = 007
N4.C0.D1.R0: CheckMCTest: result = 0x11DFF
ACCM: 00 000000B0 0000B000
ACCM: F0 F0F0F0F0 F0F0F0F0
N2.C2.D0.R0.S02: Offset Found: RdPtrOffsetDqs = 007
ACCM: 00 00000000 00000000
ACCM: 00 000000B0 0000B000
ACCM: F0 F0F0F0F0 F0F0F0F0
N2.C2.D0.R0.S03: Offset Found: RdPtrOffsetDqs = 007
ACCM: 00 00000000 00000000
N6.C0.D0.R1: CheckMCTest: result = 0x3FE00
ACCM: F0 F0F0F0F0 F0F0F0F0
N2.C2.D0.R0.S04: Offset Found: RdPtrOffsetDqs = 006
ACCM: 00 00000000 00000000
ACCM: F0 F0F0F0F0 F0F0F0F0
N0.C0.D0.R1: CheckMCTest: result = 0x3FE00
N2.C2.D0.R0.S05: Offset Found: RdPtrOffsetDqs = 006
ACCM: 00 F0000000 F0F0F000
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: F0 F0F0F0F0 F0F0F0F0
N2.C2.D0.R0.S06: Offset Found: RdPtrOffsetDqs = 006
N4.C0.D1.R0: CheckMCTest: result = 0x11C00
ACCM: 00 000000B0 0000F000
ACCM: F0 F0F0F0F0 F0F0F0F0
N2.C2.D0.R0.S07: Offset Found: RdPtrOffsetDqs = 007
ACCM: 00 00000000 00000000
ACCM: 00 000000B0 0000F000
ACCM: 00 B000B0B0 00B0B000
N2.C2.D0.R0.S08: Offset Found: RdPtrOffsetDqs = 006
ACCM: 00 00000000 00000000
N6.C0.D0.R1: CheckMCTest: result = 0x3FE00
ACCM: 00 B000B0B0 00B0B000
N2.C2.D0.R0: Write Training Coarse, upper nibbles
ACCM: 00 00000000 00000000
N6.C0.D0.R1: CheckMCTest: passed
N0.C0.D0.R1: CheckMCTest: result = 0x3FE00
N2.C2.D0.R0.S09: Dq Delay estimate: 464
ACCM: 00 F0000000 F0F0F000
N6.C0.D0.R1: CheckMCTest: passed
ACCM: F0 F0F0F0F0 F0F0F0F0
N2.C2.D0.R0.S10: Dq Delay estimate: 448
N4.C0.D1.R0: CheckMCTest: result = 0x11C00
N6.C0.D0.R1.S09: Offset Found: RdPtrOffsetDqs = 007
ACCM: F0 F0F0F0F0 F0F0F0F0
N2.C2.D0.R0.S11: Dq Delay estimate: 435
N4.C0.D1.R0.S00: Offset Found: RdPtrOffsetDqs = 007
N6.C0.D0.R1.S10: Offset Found: RdPtrOffsetDqs = 007
ACCM: 00 F000F0F0 00F0F000
N2.C2.D0.R0.S12: Dq Delay estimate: 420
N4.C0.D1.R0.S01: Offset Found: RdPtrOffsetDqs = 007
N6.C0.D0.R1.S11: Offset Found: RdPtrOffsetDqs = 007
ACCM: 00 F000F0F0 00F0F000
N2.C2.D0.R0.S13: Dq Delay estimate: 381
N4.C0.D1.R0.S02: Offset Found: RdPtrOffsetDqs = 007
N6.C0.D0.R1.S12: Offset Found: RdPtrOffsetDqs = 007
N0.C0.D0.R1: CheckMCTest: result = 0x3FE00
N2.C2.D0.R0.S14: Dq Delay estimate: 405
N4.C0.D1.R0.S03: Offset Found: RdPtrOffsetDqs = 007
N6.C0.D0.R1.S13: Offset Found: RdPtrOffsetDqs = 006
N0.C0.D0.R1: CheckMCTest: passed
N2.C2.D0.R0.S15: Dq Delay estimate: 404
N4.C0.D1.R0.S04: Offset Found: RdPtrOffsetDqs = 006
N6.C0.D0.R1.S14: Offset Found: RdPtrOffsetDqs = 006
N0.C0.D0.R1: CheckMCTest: passed
N2.C2.D0.R0.S16: Dq Delay estimate: 428
N4.C0.D1.R0.S05: Offset Found: RdPtrOffsetDqs = 007
N6.C0.D0.R1.S15: Offset Found: RdPtrOffsetDqs = 006
N0.C0.D0.R1.S09: Offset Found: RdPtrOffsetDqs = 007
N2.C2.D0.R0.S17: Dq Delay estimate: 398
N4.C0.D1.R0.S06: Offset Found: RdPtrOffsetDqs = 007
N6.C0.D0.R1.S16: Offset Found: RdPtrOffsetDqs = 007
N0.C0.D0.R1.S10: Offset Found: RdPtrOffsetDqs = 007
ACCM: F0 F0F0F0F0 F0F0F0F0
N4.C0.D1.R0.S07: Offset Found: RdPtrOffsetDqs = 007
N6.C0.D0.R1.S17: Offset Found: RdPtrOffsetDqs = 006
N0.C0.D0.R1.S11: Offset Found: RdPtrOffsetDqs = 007
ACCM: F0 F0F0F0F0 F0F0F0F0
N4.C0.D1.R0.S08: Offset Found: RdPtrOffsetDqs = 006
N6.C0.D1.R0: Write Training Coarse, lower nibbles / bytes
N0.C0.D0.R1.S12: Offset Found: RdPtrOffsetDqs = 007
ACCM: F0 F0F0F0F0 F0F0F0F0
N4.C0.D1.R0: Write Training Coarse, upper nibbles
N6.C0.D1.R0.S00: Dq Delay estimate: 466
N0.C0.D0.R1.S13: Offset Found: RdPtrOffsetDqs = 006
ACCM: F0 F0F0F0F0 F0F0F0F0
N4.C0.D1.R0.S09: Dq Delay estimate: 465
N6.C0.D1.R0.S01: Dq Delay estimate: 447
N0.C0.D0.R1.S14: Offset Found: RdPtrOffsetDqs = 006
N2.C2.D0.R0: CheckMCTest: result = 0x3FE00
N4.C0.D1.R0.S10: Dq Delay estimate: 456
N6.C0.D1.R0.S02: Dq Delay estimate: 435
N0.C0.D0.R1.S15: Offset Found: RdPtrOffsetDqs = 006
ACCM: F0 F0F0F0F0 F0F0F0F0
N4.C0.D1.R0.S11: Dq Delay estimate: 442
N6.C0.D1.R0.S03: Dq Delay estimate: 424
N0.C0.D0.R1.S16: Offset Found: RdPtrOffsetDqs = 007
ACCM: F0 F0F0F0F0 F0F0F0F0
N4.C0.D1.R0.S12: Dq Delay estimate: 425
N6.C0.D1.R0.S04: Dq Delay estimate: 387
N0.C0.D0.R1.S17: Offset Found: RdPtrOffsetDqs = 006
ACCM: F0 F0F0F0F0 F0F0F0F0
N4.C0.D1.R0.S13: Dq Delay estimate: 393
N6.C0.D1.R0.S05: Dq Delay estimate: 404
N0.C0.D1.R0: Write Training Coarse, lower nibbles / bytes
ACCM: F0 F0F0F0F0 F0F0F0F0
N4.C0.D1.R0.S14: Dq Delay estimate: 410
N6.C0.D1.R0.S06: Dq Delay estimate: 408
N0.C0.D1.R0.S00: Dq Delay estimate: 475
N2.C2.D0.R0: CheckMCTest: result = 0x3FE00
N4.C0.D1.R0.S15: Dq Delay estimate: 411
N6.C0.D1.R0.S07: Dq Delay estimate: 425
N0.C0.D1.R0.S01: Dq Delay estimate: 457
ACCM: F0 F0F0F0F0 F0F0F0F0
N4.C0.D1.R0.S16: Dq Delay estimate: 426
N6.C0.D1.R0.S08: Dq Delay estimate: 395
N0.C0.D1.R0.S02: Dq Delay estimate: 445
ACCM: F0 F0F0F0F0 F0F0F0F0
N4.C0.D1.R0.S17: Dq Delay estimate: 399
ACCM: 0F 0F0F0F0F DF0F0F0F
N0.C0.D1.R0.S03: Dq Delay estimate: 429
ACCM: 00 B0B0B000 B0B00000
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: 0F 0F0F0F0F DF0F0F0F
N0.C0.D1.R0.S04: Dq Delay estimate: 395
ACCM: 00 B0B0B000 B0B00000
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: 0F 0F0F0F0F DF0F0F0F
N0.C0.D1.R0.S05: Dq Delay estimate: 412
N2.C2.D0.R0: CheckMCTest: result = 0x3FE00
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: 0F FF0F0FFF FFFFFF0F
N0.C0.D1.R0.S06: Dq Delay estimate: 412
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: F0 F0F0F0F0 F0F0F0F0
N6.C0.D1.R0: CheckMCTest: result = 0x13DFF
N0.C0.D1.R0.S07: Dq Delay estimate: 432
ACCM: F0 F0F0F0F0 F0F0F0F0
N4.C0.D1.R0: CheckMCTest: result = 0x3FE00
ACCM: 0F 0F0F0F0F DF0F0F0F
N0.C0.D1.R0.S08: Dq Delay estimate: 404
ACCM: 00 F0F0F000 F0F00000
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: 0F 0F0F0F0F DF0F0F0F
ACCM: 0F 0F0F0F0F 0F0F0F0F
ACCM: 00 F0F0F000 F0F00000
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: 0F 0F0F0F0F DF0F0F0F
ACCM: 0F 0F0F0F0F 0F0F0F0F
N2.C2.D0.R0: CheckMCTest: result = 0x3FE00
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: 0F FF0F0FFF FFFFFF0F
ACCM: 0F 0F0F0F0F 0F0F0F0F
N2.C2.D0.R0: CheckMCTest: passed
ACCM: F0 F0F0F0F0 F0F0F0F0
N6.C0.D1.R0: CheckMCTest: result = 0x13DFF
ACCM: 0F FF0F0F0F FFFFFF0F
N2.C2.D0.R0: CheckMCTest: passed
N4.C0.D1.R0: CheckMCTest: result = 0x3FE00
ACCM: 0F 0F0F0F0F 0F0F0F0F
N0.C0.D1.R0: CheckMCTest: result = 0x11DFF
N2.C2.D0.R0.S09: Offset Found: RdPtrOffsetDqs = 007
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: 0F 0F0F0F0F 0F0F0F0F
ACCM: 0F 0F0F0F0F 0F0F0F0F
N2.C2.D0.R0.S10: Offset Found: RdPtrOffsetDqs = 007
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: 00 0B000000 0B00000B
ACCM: 0F 0F0F0F0F 0F0F0F0F
N2.C2.D0.R0.S11: Offset Found: RdPtrOffsetDqs = 007
ACCM: 00 0000B0B0 0000B000
ACCM: 00 FB0000F0 FBF0F00B
ACCM: 0F 0F0F0F0F 0F0F0F0F
N2.C2.D0.R0.S12: Offset Found: RdPtrOffsetDqs = 007
ACCM: 00 0000B0B0 0000B000
N6.C0.D1.R0: CheckMCTest: result = 0x13DFF
ACCM: 0F FF0F0F0F FFFFFF0F
N2.C2.D0.R0.S13: Offset Found: RdPtrOffsetDqs = 006
N4.C0.D1.R0: CheckMCTest: result = 0x3FE00
ACCM: 0F 0F0F0F0F 0F0F0F0F
N0.C0.D1.R0: CheckMCTest: result = 0x11DFF
N2.C2.D0.R0.S14: Offset Found: RdPtrOffsetDqs = 006
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: 0F 0F0F0F0F 0F0F0F0F
ACCM: 0F 0F0F0F0F 0F0F0F0F
N2.C2.D0.R0.S15: Offset Found: RdPtrOffsetDqs = 006
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: 00 0B000000 0F00000F
ACCM: 0F 0F0F0F0F 0F0F0F0F
N2.C2.D0.R0.S16: Offset Found: RdPtrOffsetDqs = 007
ACCM: 00 0000F0F0 0000F000
ACCM: 00 FB0000F0 FFF0F00F
ACCM: 0B 0B000B00 0B000B0B
N2.C2.D0.R0.S17: Offset Found: RdPtrOffsetDqs = 006
ACCM: 00 0000F0F0 0000F000
N6.C0.D1.R0: CheckMCTest: result = 0x13DFF
ACCM: 0B FB000B00 FBF0FB0B
N2.C2.D0.R1: Write Training Coarse, lower nibbles / bytes
N4.C0.D1.R0: CheckMCTest: result = 0x3FE00
ACCM: 00 00000000 00000000
N0.C0.D1.R0: CheckMCTest: result = 0x11DFF
N2.C2.D0.R1.S00: Dq Delay estimate: 457
N4.C0.D1.R0: CheckMCTest: passed
ACCM: 00 00000000 00000000
ACCM: 0F 0F0F0F0F 0F0F0F0F
N2.C2.D0.R1.S01: Dq Delay estimate: 442
N4.C0.D1.R0: CheckMCTest: passed
ACCM: 00 00000000 00000000
ACCM: 0F 0F0F0F0F 0F0F0F0F
N2.C2.D0.R1.S02: Dq Delay estimate: 430
N4.C0.D1.R0.S09: Offset Found: RdPtrOffsetDqs = 007
ACCM: 00 F00000F0 F0F0F000
ACCM: 0F 0F000F00 0B000F0F
N2.C2.D0.R1.S03: Dq Delay estimate: 413
N4.C0.D1.R0.S10: Offset Found: RdPtrOffsetDqs = 007
N6.C0.D1.R0: CheckMCTest: result = 0x13C00
ACCM: 0F FF000F00 FBF0FF0F
N2.C2.D0.R1.S04: Dq Delay estimate: 374
N4.C0.D1.R0.S11: Offset Found: RdPtrOffsetDqs = 007
ACCM: 00 00000000 00000000
N0.C0.D1.R0: CheckMCTest: result = 0x11DFF
N2.C2.D0.R1.S05: Dq Delay estimate: 400
N4.C0.D1.R0.S12: Offset Found: RdPtrOffsetDqs = 007
ACCM: 00 00000000 00000000
ACCM: 00 00000000 00000000
N2.C2.D0.R1.S06: Dq Delay estimate: 400
N4.C0.D1.R0.S13: Offset Found: RdPtrOffsetDqs = 006
ACCM: 00 00000000 00000000
ACCM: 00 00000000 00000000
N2.C2.D0.R1.S07: Dq Delay estimate: 420
N4.C0.D1.R0.S14: Offset Found: RdPtrOffsetDqs = 007
ACCM: 00 F00000F0 F0F0F000
ACCM: 00 00000000 00000000
N2.C2.D0.R1.S08: Dq Delay estimate: 390
N4.C0.D1.R0.S15: Offset Found: RdPtrOffsetDqs = 007
N6.C0.D1.R0: CheckMCTest: result = 0x13C00
ACCM: 00 F0000000 F0F0F000
ACCM: 0F 0F0F0F0F 0F0F0F0F
N4.C0.D1.R0.S16: Offset Found: RdPtrOffsetDqs = 007
N6.C0.D1.R0.S00: Offset Found: RdPtrOffsetDqs = 007
N0.C0.D1.R0: CheckMCTest: result = 0x11C00
ACCM: 0F 0F0F0F0F 0F0F0F0F
N4.C0.D1.R0.S17: Offset Found: RdPtrOffsetDqs = 006
N6.C0.D1.R0.S01: Offset Found: RdPtrOffsetDqs = 007
ACCM: 00 00000000 00000000
ACCM: 0F 0F0F0F0F 0F0F0F0F
N4.C0.D1.R1: Write Training Coarse, lower nibbles / bytes
N6.C0.D1.R0.S02: Offset Found: RdPtrOffsetDqs = 007
ACCM: 00 00000000 00000000
ACCM: 0F 0F0F0F0F 0F0F0F0F
N4.C0.D1.R1.S00: Dq Delay estimate: 468
N6.C0.D1.R0.S03: Offset Found: RdPtrOffsetDqs = 007
ACCM: 00 00000000 00000000
N2.C2.D0.R1: CheckMCTest: result = 0x1FF
N4.C0.D1.R1.S01: Dq Delay estimate: 452
N6.C0.D1.R0.S04: Offset Found: RdPtrOffsetDqs = 006
ACCM: 00 F0000000 F0F0F000
ACCM: 0F 0F0F0F0F 0F0F0F0F
N4.C0.D1.R1.S02: Dq Delay estimate: 439
N6.C0.D1.R0.S05: Offset Found: RdPtrOffsetDqs = 006
N0.C0.D1.R0: CheckMCTest: result = 0x11C00
ACCM: 0F 0F0F0F0F 0F0F0F0F
N4.C0.D1.R1.S03: Dq Delay estimate: 425
N6.C0.D1.R0.S06: Offset Found: RdPtrOffsetDqs = 006
N0.C0.D1.R0.S00: Offset Found: RdPtrOffsetDqs = 007
ACCM: 0F 0F0F0F0F 0F0F0F0F
N4.C0.D1.R1.S04: Dq Delay estimate: 388
N6.C0.D1.R0.S07: Offset Found: RdPtrOffsetDqs = 007
N0.C0.D1.R0.S01: Offset Found: RdPtrOffsetDqs = 007
ACCM: 0F 0F0F0F0F 0F0F0F0F
N4.C0.D1.R1.S05: Dq Delay estimate: 408
N6.C0.D1.R0.S08: Offset Found: RdPtrOffsetDqs = 006
N0.C0.D1.R0.S02: Offset Found: RdPtrOffsetDqs = 007
N2.C2.D0.R1: CheckMCTest: result = 0x1FF
N4.C0.D1.R1.S06: Dq Delay estimate: 406
N6.C0.D1.R0: Write Training Coarse, upper nibbles
N0.C0.D1.R0.S03: Offset Found: RdPtrOffsetDqs = 007
ACCM: 0F 0F0F0F0F 0F0F0F0F
N4.C0.D1.R1.S07: Dq Delay estimate: 423
N6.C0.D1.R0.S09: Dq Delay estimate: 468
N0.C0.D1.R0.S04: Offset Found: RdPtrOffsetDqs = 006
ACCM: 0F 0F0F0F0F 0F0F0F0F
N4.C0.D1.R1.S08: Dq Delay estimate: 393
N6.C0.D1.R0.S10: Dq Delay estimate: 450
N0.C0.D1.R0.S05: Offset Found: RdPtrOffsetDqs = 007
ACCM: 00 0B00000B 0B000000
ACCM: 0F 0F0F0F0F 0F0F0F0F
N6.C0.D1.R0.S11: Dq Delay estimate: 435
N0.C0.D1.R0.S06: Offset Found: RdPtrOffsetDqs = 007
ACCM: 00 0B00000B 0B000000
ACCM: 0F 0F0F0F0F 0F0F0F0F
N6.C0.D1.R0.S12: Dq Delay estimate: 423
N0.C0.D1.R0.S07: Offset Found: RdPtrOffsetDqs = 007
N2.C2.D0.R1: CheckMCTest: result = 0x1FF
ACCM: 0F 0F0F0F0F 0F0F0F0F
N6.C0.D1.R0.S13: Dq Delay estimate: 387
N0.C0.D1.R0.S08: Offset Found: RdPtrOffsetDqs = 006
ACCM: 0F 0F0F0F0F 0F0F0F0F
ACCM: 0F 0F0F0F0F 0F0F0F0F
N6.C0.D1.R0.S14: Dq Delay estimate: 405
N0.C0.D1.R0: Write Training Coarse, upper nibbles
ACCM: 0F 0F0F0F0F 0F0F0F0F
N4.C0.D1.R1: CheckMCTest: result = 0x1FF
N6.C0.D1.R0.S15: Dq Delay estimate: 409
N0.C0.D1.R0.S09: Dq Delay estimate: 471
ACCM: 00 0F00000F 0F000000
ACCM: 0F 0F0F0F0F 0F0F0F0F
N6.C0.D1.R0.S16: Dq Delay estimate: 425
N0.C0.D1.R0.S10: Dq Delay estimate: 457
ACCM: 00 0F00000F 0F000000
ACCM: 0F 0F0F0F0F 0F0F0F0F
N6.C0.D1.R0.S17: Dq Delay estimate: 396
N0.C0.D1.R0.S11: Dq Delay estimate: 445
N2.C2.D0.R1: CheckMCTest: result = 0x1FF
ACCM: 0F 0F0F0F0F 0F0F0F0F
ACCM: F0 F0F0F0F0 F0F0F0F0
N0.C0.D1.R0.S12: Dq Delay estimate: 431
N2.C2.D0.R1: CheckMCTest: passed
ACCM: 0F 0F0F0F0F 0F0F0F0F
ACCM: F0 F0F0F0F0 F0F0F0F0
N0.C0.D1.R0.S13: Dq Delay estimate: 395
N2.C2.D0.R1: CheckMCTest: passed
N4.C0.D1.R1: CheckMCTest: result = 0x1FF
ACCM: F0 F0F0F0F0 F0F0F0F0
N0.C0.D1.R0.S14: Dq Delay estimate: 413
N2.C2.D0.R1.S00: Offset Found: RdPtrOffsetDqs = 007
ACCM: 0F 0F0F0F0F 0F0F0F0F
ACCM: F0 F0F0F0F0 F0F0F0F0
N0.C0.D1.R0.S15: Dq Delay estimate: 418
N2.C2.D0.R1.S01: Offset Found: RdPtrOffsetDqs = 007
ACCM: 0F 0F0F0F0F 0F0F0F0F
N6.C0.D1.R0: CheckMCTest: result = 0x3FE00
N0.C0.D1.R0.S16: Dq Delay estimate: 436
N2.C2.D0.R1.S02: Offset Found: RdPtrOffsetDqs = 007
ACCM: 0B 0000000B 00000000
ACCM: F0 F0F0F0F0 F0F0F0F0
N0.C0.D1.R0.S17: Dq Delay estimate: 404
N2.C2.D0.R1.S03: Offset Found: RdPtrOffsetDqs = 006
ACCM: 0B 0000000B 00000000
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: F0 F0F0F0F0 F0F0F0F0
N2.C2.D0.R1.S04: Offset Found: RdPtrOffsetDqs = 006
N4.C0.D1.R1: CheckMCTest: result = 0x1FF
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: F0 F0F0F0F0 F0F0F0F0
N2.C2.D0.R1.S05: Offset Found: RdPtrOffsetDqs = 006
ACCM: 0F 0F0F0F0F 0F0F0F0F
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: F0 F0F0F0F0 F0F0F0F0
N2.C2.D0.R1.S06: Offset Found: RdPtrOffsetDqs = 006
ACCM: 0F 0F0F0F0F 0F0F0F0F
N6.C0.D1.R0: CheckMCTest: result = 0x3FE00
ACCM: F0 F0F0F0F0 F0F0F0F0
N2.C2.D0.R1.S07: Offset Found: RdPtrOffsetDqs = 007
ACCM: 0F 0D00000F 00000000
ACCM: F0 F0F0F0F0 F0F0F0F0
N0.C0.D1.R0: CheckMCTest: result = 0x3FE00
N2.C2.D0.R1.S08: Offset Found: RdPtrOffsetDqs = 006
ACCM: 0F 0D00000F 00000000
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: F0 F0F0F0F0 F0F0F0F0
N2.C2.D0.R1: Write Training Coarse, upper nibbles
N4.C0.D1.R1: CheckMCTest: result = 0x1FF
ACCM: 00 B0B00000 0000B0B0
ACCM: F0 F0F0F0F0 F0F0F0F0
N2.C2.D0.R1.S09: Dq Delay estimate: 454
N4.C0.D1.R1: CheckMCTest: passed
ACCM: 00 B0B00000 0000B0B0
ACCM: F0 F0F0F0F0 F0F0F0F0
N2.C2.D0.R1.S10: Dq Delay estimate: 441
N4.C0.D1.R1: CheckMCTest: passed
N6.C0.D1.R0: CheckMCTest: result = 0x3FE00
ACCM: F0 F0F0F0F0 F0F0F0F0
N2.C2.D0.R1.S11: Dq Delay estimate: 429
N4.C0.D1.R1.S00: Offset Found: RdPtrOffsetDqs = 007
ACCM: F0 F0F0F0F0 F0F0F0F0
N0.C0.D1.R0: CheckMCTest: result = 0x3FE00
N2.C2.D0.R1.S12: Dq Delay estimate: 414
N4.C0.D1.R1.S01: Offset Found: RdPtrOffsetDqs = 007
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: F0 F0F0F0F0 F0F0F0F0
N2.C2.D0.R1.S13: Dq Delay estimate: 374
N4.C0.D1.R1.S02: Offset Found: RdPtrOffsetDqs = 007
ACCM: 00 B0F00000 0000F0F0
ACCM: F0 F0F0F0F0 F0F0F0F0
N2.C2.D0.R1.S14: Dq Delay estimate: 400
N4.C0.D1.R1.S03: Offset Found: RdPtrOffsetDqs = 007
ACCM: 00 B0F00000 0000F0F0
ACCM: B0 B0000000 B0B0B000
N2.C2.D0.R1.S15: Dq Delay estimate: 398
N4.C0.D1.R1.S04: Offset Found: RdPtrOffsetDqs = 006
N6.C0.D1.R0: CheckMCTest: result = 0x3FE00
ACCM: B0 B0000000 B0B0B000
N2.C2.D0.R1.S16: Dq Delay estimate: 422
N4.C0.D1.R1.S05: Offset Found: RdPtrOffsetDqs = 006
N6.C0.D1.R0: CheckMCTest: passed
N0.C0.D1.R0: CheckMCTest: result = 0x3FE00
N2.C2.D0.R1.S17: Dq Delay estimate: 390
N4.C0.D1.R1.S06: Offset Found: RdPtrOffsetDqs = 006
N6.C0.D1.R0: CheckMCTest: passed
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: F0 F0F0F0F0 F0F0F0F0
N4.C0.D1.R1.S07: Offset Found: RdPtrOffsetDqs = 007
N6.C0.D1.R0.S09: Offset Found: RdPtrOffsetDqs = 007
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: F0 F0F0F0F0 F0F0F0F0
N4.C0.D1.R1.S08: Offset Found: RdPtrOffsetDqs = 006
N6.C0.D1.R0.S10: Offset Found: RdPtrOffsetDqs = 007
ACCM: F0 F0000000 F0F0F000
ACCM: F0 F0F0F0F0 F0F0F0F0
N4.C0.D1.R1: Write Training Coarse, upper nibbles
N6.C0.D1.R0.S11: Offset Found: RdPtrOffsetDqs = 007
ACCM: F0 F0000000 F0F0F000
ACCM: F0 F0F0F0F0 F0F0F0F0
N4.C0.D1.R1.S09: Dq Delay estimate: 465
N6.C0.D1.R0.S12: Offset Found: RdPtrOffsetDqs = 007
N0.C0.D1.R0: CheckMCTest: result = 0x3FE00
N2.C2.D0.R1: CheckMCTest: result = 0x3FE00
N4.C0.D1.R1.S10: Dq Delay estimate: 454
N6.C0.D1.R0.S13: Offset Found: RdPtrOffsetDqs = 006
N0.C0.D1.R0: CheckMCTest: passed
ACCM: F0 F0F0F0F0 F0F0F0F0
N4.C0.D1.R1.S11: Dq Delay estimate: 440
N6.C0.D1.R0.S14: Offset Found: RdPtrOffsetDqs = 006
N0.C0.D1.R0: CheckMCTest: passed
ACCM: F0 F0F0F0F0 F0F0F0F0
N4.C0.D1.R1.S12: Dq Delay estimate: 425
N6.C0.D1.R0.S15: Offset Found: RdPtrOffsetDqs = 006
N0.C0.D1.R0.S09: Offset Found: RdPtrOffsetDqs = 007
ACCM: F0 F0F0F0F0 F0F0F0F0
N4.C0.D1.R1.S13: Dq Delay estimate: 391
N6.C0.D1.R0.S16: Offset Found: RdPtrOffsetDqs = 007
N0.C0.D1.R0.S10: Offset Found: RdPtrOffsetDqs = 007
ACCM: F0 F0F0F0F0 F0F0F0F0
N4.C0.D1.R1.S14: Dq Delay estimate: 407
N6.C0.D1.R0.S17: Offset Found: RdPtrOffsetDqs = 006
N0.C0.D1.R0.S11: Offset Found: RdPtrOffsetDqs = 007
N2.C2.D0.R1: CheckMCTest: result = 0x3FE00
N4.C0.D1.R1.S15: Dq Delay estimate: 410
N6.C0.D1.R1: Write Training Coarse, lower nibbles / bytes
N0.C0.D1.R0.S12: Offset Found: RdPtrOffsetDqs = 007
ACCM: F0 F0F0F0F0 F0F0F0F0
N4.C0.D1.R1.S16: Dq Delay estimate: 425
N6.C0.D1.R1.S00: Dq Delay estimate: 461
N0.C0.D1.R0.S13: Offset Found: RdPtrOffsetDqs = 006
ACCM: F0 F0F0F0F0 F0F0F0F0
N4.C0.D1.R1.S17: Dq Delay estimate: 394
N6.C0.D1.R1.S01: Dq Delay estimate: 445
N0.C0.D1.R0.S14: Offset Found: RdPtrOffsetDqs = 006
ACCM: 00 B00000B0 00B00000
ACCM: F0 F0F0F0F0 F0F0F0F0
N6.C0.D1.R1.S02: Dq Delay estimate: 430
N0.C0.D1.R0.S15: Offset Found: RdPtrOffsetDqs = 007
ACCM: 00 B00000B0 00B00000
ACCM: F0 F0F0F0F0 F0F0F0F0
N6.C0.D1.R1.S03: Dq Delay estimate: 419
N0.C0.D1.R0.S16: Offset Found: RdPtrOffsetDqs = 007
N2.C2.D0.R1: CheckMCTest: result = 0x3FE00
ACCM: F0 F0F0F0F0 F0F0F0F0
N6.C0.D1.R1.S04: Dq Delay estimate: 383
N0.C0.D1.R0.S17: Offset Found: RdPtrOffsetDqs = 006
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: F0 F0F0F0F0 F0F0F0F0
N6.C0.D1.R1.S05: Dq Delay estimate: 403
N0.C0.D1.R1: Write Training Coarse, lower nibbles / bytes
ACCM: F0 F0F0F0F0 F0F0F0F0
N4.C0.D1.R1: CheckMCTest: result = 0x3FE00
N6.C0.D1.R1.S06: Dq Delay estimate: 405
N0.C0.D1.R1.S00: Dq Delay estimate: 470
ACCM: 00 F00000B0 00F00000
ACCM: F0 F0F0F0F0 F0F0F0F0
N6.C0.D1.R1.S07: Dq Delay estimate: 420
N0.C0.D1.R1.S01: Dq Delay estimate: 454
ACCM: 00 F00000B0 00F00000
ACCM: F0 F0F0F0F0 F0F0F0F0
N6.C0.D1.R1.S08: Dq Delay estimate: 390
N0.C0.D1.R1.S02: Dq Delay estimate: 443
N2.C2.D0.R1: CheckMCTest: result = 0x3FE00
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: 0F 0F0F0F0F 0F0F0F0F
N0.C0.D1.R1.S03: Dq Delay estimate: 427
N2.C2.D0.R1: CheckMCTest: passed
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: 0F 0F0F0F0F 0F0F0F0F
N0.C0.D1.R1.S04: Dq Delay estimate: 393
N2.C2.D0.R1: CheckMCTest: passed
N4.C0.D1.R1: CheckMCTest: result = 0x3FE00
ACCM: 0F 0F0F0F0F 0F0F0F0F
N0.C0.D1.R1.S05: Dq Delay estimate: 412
N2.C2.D0.R1.S09: Offset Found: RdPtrOffsetDqs = 007
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: 0F 0F0F0F0F 0F0F0F0F
N0.C0.D1.R1.S06: Dq Delay estimate: 412
N2.C2.D0.R1.S10: Offset Found: RdPtrOffsetDqs = 007
ACCM: F0 F0F0F0F0 F0F0F0F0
N6.C0.D1.R1: CheckMCTest: result = 0x1FF
N0.C0.D1.R1.S07: Dq Delay estimate: 428
N2.C2.D0.R1.S11: Offset Found: RdPtrOffsetDqs = 007
ACCM: 00 000000B0 00B0B000
ACCM: 0F 0F0F0F0F 0F0F0F0F
N0.C0.D1.R1.S08: Dq Delay estimate: 398
N2.C2.D0.R1.S12: Offset Found: RdPtrOffsetDqs = 007
ACCM: 00 000000B0 00B0B000
ACCM: 0F 0F0F0F0F 0F0F0F0F
ACCM: 0F 0F0F0F0F 0F0F0F0F
N2.C2.D0.R1.S13: Offset Found: RdPtrOffsetDqs = 006
N4.C0.D1.R1: CheckMCTest: result = 0x3FE00
ACCM: 0F 0F0F0F0F 0F0F0F0F
ACCM: 0F 0F0F0F0F 0F0F0F0F
N2.C2.D0.R1.S14: Offset Found: RdPtrOffsetDqs = 006
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: 0F 0F0F0F0F 0F0F0F0F
ACCM: 0F 0F0F0F0F 0F0F0F0F
N2.C2.D0.R1.S15: Offset Found: RdPtrOffsetDqs = 006
ACCM: F0 F0F0F0F0 F0F0F0F0
N6.C0.D1.R1: CheckMCTest: result = 0x1FF
ACCM: 0F 0F0F0F0F 0F0F0F0F
N2.C2.D0.R1.S16: Offset Found: RdPtrOffsetDqs = 007
ACCM: 00 000000F0 00F0F000
ACCM: 0F 0F0F0F0F 0F0F0F0F
N0.C0.D1.R1: CheckMCTest: result = 0x1FF
N2.C2.D0.R1.S17: Offset Found: RdPtrOffsetDqs = 006
ACCM: 00 000000F0 00F0F000
ACCM: 0F 0F0F0F0F 0F0F0F0F
ACCM: 0F 0F0F0F0F 0F0F0F0F
N2.C2.D1.R0: Write Training Coarse, lower nibbles / bytes
N4.C0.D1.R1: CheckMCTest: result = 0x3FE00
ACCM: 00 00000000 00000B0B
ACCM: 0F 0F0F0F0F 0F0F0F0F
N2.C2.D1.R0.S00: Dq Delay estimate: 463
N4.C0.D1.R1: CheckMCTest: passed
ACCM: 00 00000000 00000B0B
ACCM: 0F 0F0F0F0F 0F0F0F0F
N2.C2.D1.R0.S01: Dq Delay estimate: 450
N4.C0.D1.R1: CheckMCTest: passed
N6.C0.D1.R1: CheckMCTest: result = 0x1FF
ACCM: 0F 0F0F0F0F 0F0F0F0F
N2.C2.D1.R0.S02: Dq Delay estimate: 437
N4.C0.D1.R1.S09: Offset Found: RdPtrOffsetDqs = 007
ACCM: 0F 0F0F0F0F 0F0F0F0F
N0.C0.D1.R1: CheckMCTest: result = 0x1FF
N2.C2.D1.R0.S03: Dq Delay estimate: 425
N4.C0.D1.R1.S10: Offset Found: RdPtrOffsetDqs = 007
ACCM: 0F 0F0F0F0F 0F0F0F0F
ACCM: 0F 0F0F0F0F 0F0F0F0F
N2.C2.D1.R0.S04: Dq Delay estimate: 382
N4.C0.D1.R1.S11: Offset Found: RdPtrOffsetDqs = 007
ACCM: 00 00000000 00000B0F
ACCM: 0F 0F0F0F0F 0F0F0F0F
N2.C2.D1.R0.S05: Dq Delay estimate: 412
N4.C0.D1.R1.S12: Offset Found: RdPtrOffsetDqs = 007
ACCM: 00 00000000 00000B0F
ACCM: 00 0B000B00 0B000B0B
N2.C2.D1.R0.S06: Dq Delay estimate: 410
N4.C0.D1.R1.S13: Offset Found: RdPtrOffsetDqs = 006
N6.C0.D1.R1: CheckMCTest: result = 0x1FF
ACCM: 00 0B000B00 0B000B0B
N2.C2.D1.R0.S07: Dq Delay estimate: 428
N4.C0.D1.R1.S14: Offset Found: RdPtrOffsetDqs = 006
N6.C0.D1.R1: CheckMCTest: passed
N0.C0.D1.R1: CheckMCTest: result = 0x1FF
N2.C2.D1.R0.S08: Dq Delay estimate: 397
N4.C0.D1.R1.S15: Offset Found: RdPtrOffsetDqs = 006
N6.C0.D1.R1: CheckMCTest: passed
ACCM: 0F 0F0F0F0F 0F0F0F0F
ACCM: 0F 0F0F0F0F 0F0F0F0F
N4.C0.D1.R1.S16: Offset Found: RdPtrOffsetDqs = 007
N6.C0.D1.R1.S00: Offset Found: RdPtrOffsetDqs = 007
ACCM: 0F 0F0F0F0F 0F0F0F0F
ACCM: 0F 0F0F0F0F 0F0F0F0F
N4.C0.D1.R1.S17: Offset Found: RdPtrOffsetDqs = 006
N6.C0.D1.R1.S01: Offset Found: RdPtrOffsetDqs = 007
ACCM: 00 0F000F00 0F000F0F
ACCM: 0F 0F0F0F0F 0F0F0F0F
N4.C0: Calculating Optimimum DQS Values
N6.C0.D1.R1.S02: Offset Found: RdPtrOffsetDqs = 007
ACCM: 00 0F000F00 0F000F0F
ACCM: 0F FF0F0FFF FFFFFF0F
N4.C0.D0.R0.S00: Total Delay in PI ticks: TxDQS = 1020, TxDQ = 984
N6.C0.D1.R1.S03: Offset Found: RdPtrOffsetDqs = 007
N0.C0.D1.R1: CheckMCTest: result = 0x1FF
N2.C2.D1.R0: CheckMCTest: result = 0x13DFF
N4.C0.D0.R0.S01: Total Delay in PI ticks: TxDQS = 1000, TxDQ = 964
N6.C0.D1.R1.S04: Offset Found: RdPtrOffsetDqs = 006
N0.C0.D1.R1: CheckMCTest: passed
ACCM: 0F 0F0F0F0F 0F0F0F0F
N4.C0.D0.R0.S02: Total Delay in PI ticks: TxDQS = 989, TxDQ = 951
N6.C0.D1.R1.S05: Offset Found: RdPtrOffsetDqs = 006
N0.C0.D1.R1: CheckMCTest: passed
ACCM: 0F 0F0F0F0F 0F0F0F0F
N4.C0.D0.R0.S03: Total Delay in PI ticks: TxDQS = 969, TxDQ = 932
N6.C0.D1.R1.S06: Offset Found: RdPtrOffsetDqs = 006
N0.C0.D1.R1.S00: Offset Found: RdPtrOffsetDqs = 007
ACCM: 0F 0F0F0F0F 0F0F0F0F
N4.C0.D0.R0.S04: Total Delay in PI ticks: TxDQS = 941, TxDQ = 904
N6.C0.D1.R1.S07: Offset Found: RdPtrOffsetDqs = 007
N0.C0.D1.R1.S01: Offset Found: RdPtrOffsetDqs = 007
ACCM: 0F FF0F0FFF FFFFFF0F
N4.C0.D0.R0.S05: Total Delay in PI ticks: TxDQS = 958, TxDQ = 921
N6.C0.D1.R1.S08: Offset Found: RdPtrOffsetDqs = 006
N0.C0.D1.R1.S02: Offset Found: RdPtrOffsetDqs = 007
N2.C2.D1.R0: CheckMCTest: result = 0x13DFF
N4.C0.D0.R0.S06: Total Delay in PI ticks: TxDQS = 958, TxDQ = 920
N6.C0.D1.R1: Write Training Coarse, upper nibbles
N0.C0.D1.R1.S03: Offset Found: RdPtrOffsetDqs = 007
ACCM: 0F 0F0F0F0F 0F0F0F0F
N4.C0.D0.R0.S07: Total Delay in PI ticks: TxDQS = 974, TxDQ = 936
N6.C0.D1.R1.S09: Dq Delay estimate: 462
N0.C0.D1.R1.S04: Offset Found: RdPtrOffsetDqs = 006
ACCM: 0F 0F0F0F0F 0F0F0F0F
N4.C0.D0.R0.S08: Total Delay in PI ticks: TxDQS = 951, TxDQ = 914
N6.C0.D1.R1.S10: Dq Delay estimate: 448
N0.C0.D1.R1.S05: Offset Found: RdPtrOffsetDqs = 007
ACCM: 00 000B0B0B 0000000B
N4.C0.D0.R0.S09: Total Delay in PI ticks: TxDQS = 1018, TxDQ = 980
N6.C0.D1.R1.S11: Dq Delay estimate: 435
N0.C0.D1.R1.S06: Offset Found: RdPtrOffsetDqs = 007
ACCM: 00 F00B0BFB F0F0F00B
N4.C0.D0.R0.S10: Total Delay in PI ticks: TxDQS = 998, TxDQ = 961
N6.C0.D1.R1.S12: Dq Delay estimate: 419
N0.C0.D1.R1.S07: Offset Found: RdPtrOffsetDqs = 007
N2.C2.D1.R0: CheckMCTest: result = 0x13DFF
N4.C0.D0.R0.S11: Total Delay in PI ticks: TxDQS = 985, TxDQ = 948
N6.C0.D1.R1.S13: Dq Delay estimate: 382
N0.C0.D1.R1.S08: Offset Found: RdPtrOffsetDqs = 006
ACCM: 0F 0F0F0F0F 0F0F0F0F
N4.C0.D0.R0.S12: Total Delay in PI ticks: TxDQS = 970, TxDQ = 933
N6.C0.D1.R1.S14: Dq Delay estimate: 401
N0.C0.D1.R1: Write Training Coarse, upper nibbles
ACCM: 0F 0F0F0F0F 0F0F0F0F
N4.C0.D0.R0.S13: Total Delay in PI ticks: TxDQS = 940, TxDQ = 904
N6.C0.D1.R1.S15: Dq Delay estimate: 403
N0.C0.D1.R1.S09: Dq Delay estimate: 468
ACCM: 00 000F0F0F 0C00000F
N4.C0.D0.R0.S14: Total Delay in PI ticks: TxDQS = 953, TxDQ = 916
N6.C0.D1.R1.S16: Dq Delay estimate: 418
N0.C0.D1.R1.S10: Dq Delay estimate: 454
ACCM: 00 F00F0FFF FCF0F00F
N4.C0.D0.R0.S15: Total Delay in PI ticks: TxDQS = 957, TxDQ = 921
N6.C0.D1.R1.S17: Dq Delay estimate: 390
N0.C0.D1.R1.S11: Dq Delay estimate: 444
N2.C2.D1.R0: CheckMCTest: result = 0x13DFF
N4.C0.D0.R0.S16: Total Delay in PI ticks: TxDQS = 974, TxDQ = 937
ACCM: F0 F0F0F0F0 F0F0F0F0
N0.C0.D1.R1.S12: Dq Delay estimate: 428
ACCM: 00 00000000 00000000
N4.C0.D0.R0.S17: Total Delay in PI ticks: TxDQS = 951, TxDQ = 915
ACCM: F0 F0F0F0F0 F0F0F0F0
N0.C0.D1.R1.S13: Dq Delay estimate: 394
ACCM: 00 00000000 00000000
N4.C0.D0.R1.S00: Total Delay in PI ticks: TxDQS = 1011, TxDQ = 975
ACCM: F0 F0F0F0F0 F0F0F0F0
N0.C0.D1.R1.S14: Dq Delay estimate: 412
ACCM: 00 00000000 00000000
N4.C0.D0.R1.S01: Total Delay in PI ticks: TxDQS = 993, TxDQ = 957
ACCM: F0 F0F0F0F0 F0F0F0F0
N0.C0.D1.R1.S15: Dq Delay estimate: 416
ACCM: 00 F00000F0 F0F0F000
N4.C0.D0.R1.S02: Total Delay in PI ticks: TxDQS = 982, TxDQ = 944
N6.C0.D1.R1: CheckMCTest: result = 0x3FE00
N0.C0.D1.R1.S16: Dq Delay estimate: 430
N2.C2.D1.R0: CheckMCTest: result = 0x13C00
N4.C0.D0.R1.S03: Total Delay in PI ticks: TxDQS = 966, TxDQ = 929
ACCM: F0 F0F0F0F0 F0F0F0F0
N0.C0.D1.R1.S17: Dq Delay estimate: 398
ACCM: 00 00000000 00000000
N4.C0.D0.R1.S04: Total Delay in PI ticks: TxDQS = 930, TxDQ = 893
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: 00 00000000 00000000
N4.C0.D0.R1.S05: Total Delay in PI ticks: TxDQS = 949, TxDQ = 912
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: 00 00000000 00000000
N4.C0.D0.R1.S06: Total Delay in PI ticks: TxDQS = 949, TxDQ = 910
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: 00 F00000F0 F0F0F000
N4.C0.D0.R1.S07: Total Delay in PI ticks: TxDQS = 966, TxDQ = 928
N6.C0.D1.R1: CheckMCTest: result = 0x3FE00
ACCM: F0 F0F0F0F0 F0F0F0F0
N2.C2.D1.R0: CheckMCTest: result = 0x13C00
N4.C0.D0.R1.S08: Total Delay in PI ticks: TxDQS = 943, TxDQ = 906
ACCM: F0 F0F0F0F0 F0F0F0F0
N0.C0.D1.R1: CheckMCTest: result = 0x3FE00
N2.C2.D1.R0.S00: Offset Found: RdPtrOffsetDqs = 007
N4.C0.D0.R1.S09: Total Delay in PI ticks: TxDQS = 1009, TxDQ = 971
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: F0 F0F0F0F0 F0F0F0F0
N2.C2.D1.R0.S01: Offset Found: RdPtrOffsetDqs = 007
N4.C0.D0.R1.S10: Total Delay in PI ticks: TxDQS = 993, TxDQ = 957
ACCM: 00 B0000000 0000B0B0
ACCM: F0 F0F0F0F0 F0F0F0F0
N2.C2.D1.R0.S02: Offset Found: RdPtrOffsetDqs = 007
N4.C0.D0.R1.S11: Total Delay in PI ticks: TxDQS = 983, TxDQ = 946
ACCM: 00 B0000000 0000B0B0
ACCM: F0 F0F0F0F0 F0F0F0F0
N2.C2.D1.R0.S03: Offset Found: RdPtrOffsetDqs = 007
N4.C0.D0.R1.S12: Total Delay in PI ticks: TxDQS = 967, TxDQ = 929
N6.C0.D1.R1: CheckMCTest: result = 0x3FE00
ACCM: F0 F0F0F0F0 F0F0F0F0
N2.C2.D1.R0.S04: Offset Found: RdPtrOffsetDqs = 006
N4.C0.D0.R1.S13: Total Delay in PI ticks: TxDQS = 934, TxDQ = 898
ACCM: F0 F0F0F0F0 F0F0F0F0
N0.C0.D1.R1: CheckMCTest: result = 0x3FE00
N2.C2.D1.R0.S05: Offset Found: RdPtrOffsetDqs = 007
N4.C0.D0.R1.S14: Total Delay in PI ticks: TxDQS = 947, TxDQ = 910
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: F0 F0F0F0F0 F0F0F0F0
N2.C2.D1.R0.S06: Offset Found: RdPtrOffsetDqs = 006
N4.C0.D0.R1.S15: Total Delay in PI ticks: TxDQS = 951, TxDQ = 915
ACCM: 00 F0000000 0000F0B0
ACCM: F0 F0F0F0F0 F0F0F0F0
N2.C2.D1.R0.S07: Offset Found: RdPtrOffsetDqs = 007
N4.C0.D0.R1.S16: Total Delay in PI ticks: TxDQS = 967, TxDQ = 931
ACCM: 00 F0000000 0000F0B0
ACCM: 00 0000B0B0 00B000B0
N2.C2.D1.R0.S08: Offset Found: RdPtrOffsetDqs = 006
N4.C0.D0.R1.S17: Total Delay in PI ticks: TxDQS = 940, TxDQ = 904
N6.C0.D1.R1: CheckMCTest: result = 0x3FE00
ACCM: 00 0000B0B0 00B000B0
N2.C2.D1.R0: Write Training Coarse, upper nibbles
N4.C0.D1.R0.S00: Total Delay in PI ticks: TxDQS = 1019, TxDQ = 981
N6.C0.D1.R1: CheckMCTest: passed
N0.C0.D1.R1: CheckMCTest: result = 0x3FE00
N2.C2.D1.R0.S09: Dq Delay estimate: 461
N4.C0.D1.R0.S01: Total Delay in PI ticks: TxDQS = 1006, TxDQ = 967
N6.C0.D1.R1: CheckMCTest: passed
ACCM: F0 F0F0F0F0 F0F0F0F0
N2.C2.D1.R0.S10: Dq Delay estimate: 450
N4.C0.D1.R0.S02: Total Delay in PI ticks: TxDQS = 992, TxDQ = 953
N6.C0.D1.R1.S09: Offset Found: RdPtrOffsetDqs = 007
ACCM: F0 F0F0F0F0 F0F0F0F0
N2.C2.D1.R0.S11: Dq Delay estimate: 437
N4.C0.D1.R0.S03: Total Delay in PI ticks: TxDQS = 976, TxDQ = 938
N6.C0.D1.R1.S10: Offset Found: RdPtrOffsetDqs = 007
ACCM: 00 0000F0B0 00F000F0
N2.C2.D1.R0.S12: Dq Delay estimate: 424
N4.C0.D1.R0.S04: Total Delay in PI ticks: TxDQS = 943, TxDQ = 904
N6.C0.D1.R1.S11: Offset Found: RdPtrOffsetDqs = 007
ACCM: 00 0000F0B0 00F000F0
N2.C2.D1.R0.S13: Dq Delay estimate: 386
N4.C0.D1.R0.S05: Total Delay in PI ticks: TxDQS = 961, TxDQ = 923
N6.C0.D1.R1.S12: Offset Found: RdPtrOffsetDqs = 007
N0.C0.D1.R1: CheckMCTest: result = 0x3FE00
N2.C2.D1.R0.S14: Dq Delay estimate: 410
N4.C0.D1.R0.S06: Total Delay in PI ticks: TxDQS = 961, TxDQ = 922
N6.C0.D1.R1.S13: Offset Found: RdPtrOffsetDqs = 006
N0.C0.D1.R1: CheckMCTest: passed
N2.C2.D1.R0.S15: Dq Delay estimate: 407
N4.C0.D1.R0.S07: Total Delay in PI ticks: TxDQS = 977, TxDQ = 937
N6.C0.D1.R1.S14: Offset Found: RdPtrOffsetDqs = 006
N0.C0.D1.R1: CheckMCTest: passed
N2.C2.D1.R0.S16: Dq Delay estimate: 430
N4.C0.D1.R0.S08: Total Delay in PI ticks: TxDQS = 950, TxDQ = 910
N6.C0.D1.R1.S15: Offset Found: RdPtrOffsetDqs = 006
N0.C0.D1.R1.S09: Offset Found: RdPtrOffsetDqs = 007
N2.C2.D1.R0.S17: Dq Delay estimate: 397
N4.C0.D1.R0.S09: Total Delay in PI ticks: TxDQS = 1017, TxDQ = 977
N6.C0.D1.R1.S16: Offset Found: RdPtrOffsetDqs = 007
N0.C0.D1.R1.S10: Offset Found: RdPtrOffsetDqs = 007
ACCM: F0 F0F0F0F0 F0F0F0F0
N4.C0.D1.R0.S10: Total Delay in PI ticks: TxDQS = 1006, TxDQ = 968
N6.C0.D1.R1.S17: Offset Found: RdPtrOffsetDqs = 006
N0.C0.D1.R1.S11: Offset Found: RdPtrOffsetDqs = 007
ACCM: F0 F0F0F0F0 F0F0F0F0
N4.C0.D1.R0.S11: Total Delay in PI ticks: TxDQS = 992, TxDQ = 954
N6.C0: Calculating Optimimum DQS Values
N0.C0.D1.R1.S12: Offset Found: RdPtrOffsetDqs = 007
ACCM: F0 F0F0F0F0 F0F0F0F0
N4.C0.D1.R0.S12: Total Delay in PI ticks: TxDQS = 976, TxDQ = 937
N6.C0.D0.R0.S00: Total Delay in PI ticks: TxDQS = 1015, TxDQ = 984
N0.C0.D1.R1.S13: Offset Found: RdPtrOffsetDqs = 006
ACCM: F0 F0F0F0F0 F0F0F0F0
N4.C0.D1.R0.S13: Total Delay in PI ticks: TxDQS = 943, TxDQ = 905
N6.C0.D0.R0.S01: Total Delay in PI ticks: TxDQS = 993, TxDQ = 960
N0.C0.D1.R1.S14: Offset Found: RdPtrOffsetDqs = 006
N2.C2.D1.R0: CheckMCTest: result = 0x3FE00
N4.C0.D1.R0.S14: Total Delay in PI ticks: TxDQS = 960, TxDQ = 922
N6.C0.D0.R0.S02: Total Delay in PI ticks: TxDQS = 983, TxDQ = 950
N0.C0.D1.R1.S15: Offset Found: RdPtrOffsetDqs = 007
ACCM: F0 F0F0F0F0 F0F0F0F0
N4.C0.D1.R0.S15: Total Delay in PI ticks: TxDQS = 960, TxDQ = 923
N6.C0.D0.R0.S03: Total Delay in PI ticks: TxDQS = 966, TxDQ = 933
N0.C0.D1.R1.S16: Offset Found: RdPtrOffsetDqs = 007
ACCM: F0 F0F0F0F0 F0F0F0F0
N4.C0.D1.R0.S16: Total Delay in PI ticks: TxDQS = 977, TxDQ = 938
N6.C0.D0.R0.S04: Total Delay in PI ticks: TxDQS = 932, TxDQ = 899
N0.C0.D1.R1.S17: Offset Found: RdPtrOffsetDqs = 006
ACCM: F0 F0F0F0F0 F0F0F0F0
N4.C0.D1.R0.S17: Total Delay in PI ticks: TxDQS = 950, TxDQ = 911
N6.C0.D0.R0.S05: Total Delay in PI ticks: TxDQS = 952, TxDQ = 918
N0.C0: Calculating Optimimum DQS Values
ACCM: F0 F0F0F0F0 F0F0F0F0
N4.C0.D1.R1.S00: Total Delay in PI ticks: TxDQS = 1017, TxDQ = 980
N6.C0.D0.R0.S06: Total Delay in PI ticks: TxDQS = 956, TxDQ = 923
N0.C0.D0.R0.S00: Total Delay in PI ticks: TxDQS = 1015, TxDQ = 983
N2.C2.D1.R0: CheckMCTest: result = 0x3FE00
N4.C0.D1.R1.S01: Total Delay in PI ticks: TxDQS = 1002, TxDQ = 964
N6.C0.D0.R0.S07: Total Delay in PI ticks: TxDQS = 973, TxDQ = 939
N0.C0.D0.R0.S01: Total Delay in PI ticks: TxDQS = 997, TxDQ = 964
ACCM: F0 F0F0F0F0 F0F0F0F0
N4.C0.D1.R1.S02: Total Delay in PI ticks: TxDQS = 990, TxDQ = 951
N6.C0.D0.R0.S08: Total Delay in PI ticks: TxDQS = 946, TxDQ = 912
N0.C0.D0.R0.S02: Total Delay in PI ticks: TxDQS = 988, TxDQ = 955
ACCM: F0 F0F0F0F0 F0F0F0F0
N4.C0.D1.R1.S03: Total Delay in PI ticks: TxDQS = 974, TxDQ = 937
N6.C0.D0.R0.S09: Total Delay in PI ticks: TxDQS = 1016, TxDQ = 983
N0.C0.D0.R0.S03: Total Delay in PI ticks: TxDQS = 969, TxDQ = 936
ACCM: 00 00B00000 00000000
N4.C0.D1.R1.S04: Total Delay in PI ticks: TxDQS = 938, TxDQ = 900
N6.C0.D0.R0.S10: Total Delay in PI ticks: TxDQS = 993, TxDQ = 962
N0.C0.D0.R0.S04: Total Delay in PI ticks: TxDQS = 937, TxDQ = 903
ACCM: 00 00B00000 00000000
N4.C0.D1.R1.S05: Total Delay in PI ticks: TxDQS = 958, TxDQ = 920
N6.C0.D0.R0.S11: Total Delay in PI ticks: TxDQS = 983, TxDQ = 949
N0.C0.D0.R0.S05: Total Delay in PI ticks: TxDQS = 953, TxDQ = 919
N2.C2.D1.R0: CheckMCTest: result = 0x3FE00
N4.C0.D1.R1.S06: Total Delay in PI ticks: TxDQS = 958, TxDQ = 918
N6.C0.D0.R0.S12: Total Delay in PI ticks: TxDQS = 967, TxDQ = 934
N0.C0.D0.R0.S06: Total Delay in PI ticks: TxDQS = 957, TxDQ = 924
ACCM: F0 F0F0F0F0 F0F0F0F0
N4.C0.D1.R1.S07: Total Delay in PI ticks: TxDQS = 975, TxDQ = 935
N6.C0.D0.R0.S13: Total Delay in PI ticks: TxDQS = 933, TxDQ = 900
N0.C0.D0.R0.S07: Total Delay in PI ticks: TxDQS = 974, TxDQ = 940
ACCM: F0 F0F0F0F0 F0F0F0F0
N4.C0.D1.R1.S08: Total Delay in PI ticks: TxDQS = 945, TxDQ = 905
N6.C0.D0.R0.S14: Total Delay in PI ticks: TxDQS = 952, TxDQ = 918
N0.C0.D0.R0.S08: Total Delay in PI ticks: TxDQS = 948, TxDQ = 915
ACCM: 00 00F00000 00000000
N4.C0.D1.R1.S09: Total Delay in PI ticks: TxDQS = 1017, TxDQ = 977
N6.C0.D0.R0.S15: Total Delay in PI ticks: TxDQS = 955, TxDQ = 920
N0.C0.D0.R0.S09: Total Delay in PI ticks: TxDQS = 1017, TxDQ = 984
ACCM: 00 00F00000 00000000
N4.C0.D1.R1.S10: Total Delay in PI ticks: TxDQS = 1003, TxDQ = 966
N6.C0.D0.R0.S16: Total Delay in PI ticks: TxDQS = 971, TxDQ = 936
N0.C0.D0.R0.S10: Total Delay in PI ticks: TxDQS = 997, TxDQ = 964
N2.C2.D1.R0: CheckMCTest: result = 0x3FE00
N4.C0.D1.R1.S11: Total Delay in PI ticks: TxDQS = 990, TxDQ = 952
N6.C0.D0.R0.S17: Total Delay in PI ticks: TxDQS = 948, TxDQ = 913
N0.C0.D0.R0.S11: Total Delay in PI ticks: TxDQS = 988, TxDQ = 955
N2.C2.D1.R0: CheckMCTest: passed
N4.C0.D1.R1.S12: Total Delay in PI ticks: TxDQS = 976, TxDQ = 937
N6.C0.D0.R1.S00: Total Delay in PI ticks: TxDQS = 1008, TxDQ = 976
N0.C0.D0.R0.S12: Total Delay in PI ticks: TxDQS = 972, TxDQ = 938
N2.C2.D1.R0: CheckMCTest: passed
N4.C0.D1.R1.S13: Total Delay in PI ticks: TxDQS = 941, TxDQ = 903
N6.C0.D0.R1.S01: Total Delay in PI ticks: TxDQS = 988, TxDQ = 955
N0.C0.D0.R0.S13: Total Delay in PI ticks: TxDQS = 938, TxDQ = 904
N2.C2.D1.R0.S09: Offset Found: RdPtrOffsetDqs = 007
N4.C0.D1.R1.S14: Total Delay in PI ticks: TxDQS = 957, TxDQ = 919
N6.C0.D0.R1.S02: Total Delay in PI ticks: TxDQS = 977, TxDQ = 943
N0.C0.D0.R0.S14: Total Delay in PI ticks: TxDQS = 953, TxDQ = 920
N2.C2.D1.R0.S10: Offset Found: RdPtrOffsetDqs = 007
N4.C0.D1.R1.S15: Total Delay in PI ticks: TxDQS = 959, TxDQ = 922
N6.C0.D0.R1.S03: Total Delay in PI ticks: TxDQS = 960, TxDQ = 927
N0.C0.D0.R0.S15: Total Delay in PI ticks: TxDQS = 957, TxDQ = 925
N2.C2.D1.R0.S11: Offset Found: RdPtrOffsetDqs = 007
N4.C0.D1.R1.S16: Total Delay in PI ticks: TxDQS = 975, TxDQ = 937
N6.C0.D0.R1.S04: Total Delay in PI ticks: TxDQS = 926, TxDQ = 893
N0.C0.D0.R0.S16: Total Delay in PI ticks: TxDQS = 975, TxDQ = 942
N2.C2.D1.R0.S12: Offset Found: RdPtrOffsetDqs = 007
N4.C0.D1.R1.S17: Total Delay in PI ticks: TxDQS = 944, TxDQ = 906
N6.C0.D0.R1.S05: Total Delay in PI ticks: TxDQS = 946, TxDQ = 912
N0.C0.D0.R0.S17: Total Delay in PI ticks: TxDQS = 946, TxDQ = 912
N2.C2.D1.R0.S13: Offset Found: RdPtrOffsetDqs = 006
N4.C1.D0.R0: Write Training Coarse, lower nibbles / bytes
N6.C0.D0.R1.S06: Total Delay in PI ticks: TxDQS = 948, TxDQ = 915
N0.C0.D0.R1.S00: Total Delay in PI ticks: TxDQS = 1010, TxDQ = 977
N2.C2.D1.R0.S14: Offset Found: RdPtrOffsetDqs = 006
N4.C1.D0.R0.S00: Dq Delay estimate: 470
N6.C0.D0.R1.S07: Total Delay in PI ticks: TxDQS = 966, TxDQ = 932
N0.C0.D0.R1.S01: Total Delay in PI ticks: TxDQS = 992, TxDQ = 959
N2.C2.D1.R0.S15: Offset Found: RdPtrOffsetDqs = 006
N4.C1.D0.R0.S01: Dq Delay estimate: 452
N6.C0.D0.R1.S08: Total Delay in PI ticks: TxDQS = 938, TxDQ = 904
N0.C0.D0.R1.S02: Total Delay in PI ticks: TxDQS = 979, TxDQ = 946
N2.C2.D1.R0.S16: Offset Found: RdPtrOffsetDqs = 007
N4.C1.D0.R0.S02: Dq Delay estimate: 446
N6.C0.D0.R1.S09: Total Delay in PI ticks: TxDQS = 1006, TxDQ = 972
N0.C0.D0.R1.S03: Total Delay in PI ticks: TxDQS = 963, TxDQ = 930
N2.C2.D1.R0.S17: Offset Found: RdPtrOffsetDqs = 006
N4.C1.D0.R0.S03: Dq Delay estimate: 433
N6.C0.D0.R1.S10: Total Delay in PI ticks: TxDQS = 989, TxDQ = 958
N0.C0.D0.R1.S04: Total Delay in PI ticks: TxDQS = 931, TxDQ = 897
N2.C2.D1.R1: Write Training Coarse, lower nibbles / bytes
N4.C1.D0.R0.S04: Dq Delay estimate: 395
N6.C0.D0.R1.S11: Total Delay in PI ticks: TxDQS = 976, TxDQ = 944
N0.C0.D0.R1.S05: Total Delay in PI ticks: TxDQS = 947, TxDQ = 912
N2.C2.D1.R1.S00: Dq Delay estimate: 462
N4.C1.D0.R0.S05: Dq Delay estimate: 406
N6.C0.D0.R1.S12: Total Delay in PI ticks: TxDQS = 965, TxDQ = 931
N0.C0.D0.R1.S06: Total Delay in PI ticks: TxDQS = 950, TxDQ = 917
N2.C2.D1.R1.S01: Dq Delay estimate: 445
N4.C1.D0.R0.S06: Dq Delay estimate: 424
N6.C0.D0.R1.S13: Total Delay in PI ticks: TxDQS = 927, TxDQ = 894
N0.C0.D0.R1.S07: Total Delay in PI ticks: TxDQS = 966, TxDQ = 932
N2.C2.D1.R1.S02: Dq Delay estimate: 432
N4.C1.D0.R0.S07: Dq Delay estimate: 436
N6.C0.D0.R1.S14: Total Delay in PI ticks: TxDQS = 945, TxDQ = 911
N0.C0.D0.R1.S08: Total Delay in PI ticks: TxDQS = 939, TxDQ = 906
N2.C2.D1.R1.S03: Dq Delay estimate: 422
N4.C1.D0.R0.S08: Dq Delay estimate: 410
N6.C0.D0.R1.S15: Total Delay in PI ticks: TxDQS = 948, TxDQ = 914
N0.C0.D0.R1.S09: Total Delay in PI ticks: TxDQS = 1007, TxDQ = 974
N2.C2.D1.R1.S04: Dq Delay estimate: 378
ACCM: DF 0F0F0F9F 0F0F0F0F
N6.C0.D0.R1.S16: Total Delay in PI ticks: TxDQS = 966, TxDQ = 930
N0.C0.D0.R1.S10: Total Delay in PI ticks: TxDQS = 993, TxDQ = 959
N2.C2.D1.R1.S05: Dq Delay estimate: 409
ACCM: DF 0F0F0F9F 0F0F0F0F
N6.C0.D0.R1.S17: Total Delay in PI ticks: TxDQS = 938, TxDQ = 904
N0.C0.D0.R1.S11: Total Delay in PI ticks: TxDQS = 981, TxDQ = 948
N2.C2.D1.R1.S06: Dq Delay estimate: 404
ACCM: FF FFFFFF9F FFFFFFFF
N6.C0.D1.R0.S00: Total Delay in PI ticks: TxDQS = 1012, TxDQ = 978
N0.C0.D0.R1.S12: Total Delay in PI ticks: TxDQS = 966, TxDQ = 933
N2.C2.D1.R1.S07: Dq Delay estimate: 426
ACCM: FF FFFFFF9F FFFFFFFF
N6.C0.D1.R0.S01: Total Delay in PI ticks: TxDQS = 994, TxDQ = 959
N0.C0.D0.R1.S13: Total Delay in PI ticks: TxDQS = 931, TxDQ = 897
N2.C2.D1.R1.S08: Dq Delay estimate: 395
N4.C1.D0.R0: CheckMCTest: result = 0x3FFFF
N6.C0.D1.R0.S02: Total Delay in PI ticks: TxDQS = 983, TxDQ = 947
N0.C0.D0.R1.S14: Total Delay in PI ticks: TxDQS = 949, TxDQ = 916
ACCM: 0F 0F0F0F0F 0F0F0F0F
ACCM: DF 0F0F0FDF 0F0F0F0F
N6.C0.D1.R0.S03: Total Delay in PI ticks: TxDQS = 970, TxDQ = 936
N0.C0.D0.R1.S15: Total Delay in PI ticks: TxDQS = 952, TxDQ = 919
ACCM: 0F 0F0F0F0F 0F0F0F0F
ACCM: DF 0F0F0FDF 0F0F0F0F
N6.C0.D1.R0.S04: Total Delay in PI ticks: TxDQS = 933, TxDQ = 899
N0.C0.D0.R1.S16: Total Delay in PI ticks: TxDQS = 968, TxDQ = 936
ACCM: 0F 0F0F0F0F 0F0F0F0F
ACCM: FF FFFFFFDF FFFFFFFF
N6.C0.D1.R0.S05: Total Delay in PI ticks: TxDQS = 952, TxDQ = 916
N0.C0.D0.R1.S17: Total Delay in PI ticks: TxDQS = 938, TxDQ = 904
ACCM: 0F 0F0F0F0F 0F0F0F0F
ACCM: FF FFFFFFDF FFFFFFFF
N6.C0.D1.R0.S06: Total Delay in PI ticks: TxDQS = 956, TxDQ = 920
N0.C0.D1.R0.S00: Total Delay in PI ticks: TxDQS = 1022, TxDQ = 987
N2.C2.D1.R1: CheckMCTest: result = 0x1FF
N4.C1.D0.R0: CheckMCTest: result = 0x3FFFF
N6.C0.D1.R0.S07: Total Delay in PI ticks: TxDQS = 973, TxDQ = 937
N0.C0.D1.R0.S01: Total Delay in PI ticks: TxDQS = 1004, TxDQ = 969
ACCM: 0F 0F0F0F0F 0F0F0F0F
ACCM: DF 0F0F0FDF 0F0F0F0F
N6.C0.D1.R0.S08: Total Delay in PI ticks: TxDQS = 943, TxDQ = 907
N0.C0.D1.R0.S02: Total Delay in PI ticks: TxDQS = 992, TxDQ = 957
ACCM: 0F 0F0F0F0F 0F0F0F0F
ACCM: DF 0F0F0FDF 0F0F0F0F
N6.C0.D1.R0.S09: Total Delay in PI ticks: TxDQS = 1015, TxDQ = 980
N0.C0.D1.R0.S03: Total Delay in PI ticks: TxDQS = 975, TxDQ = 941
ACCM: 0F 0F0F0F0F 0F0F0F0F
ACCM: F0 FBF0F0DB FBF0F0F0
N6.C0.D1.R0.S10: Total Delay in PI ticks: TxDQS = 997, TxDQ = 962
N0.C0.D1.R0.S04: Total Delay in PI ticks: TxDQS = 942, TxDQ = 907
ACCM: 0F 0F0F0F0F 0F0F0F0F
ACCM: F0 FBF0F0DB FBF0F0F0
N6.C0.D1.R0.S11: Total Delay in PI ticks: TxDQS = 982, TxDQ = 947
N0.C0.D1.R0.S05: Total Delay in PI ticks: TxDQS = 960, TxDQ = 924
N2.C2.D1.R1: CheckMCTest: result = 0x1FF
N4.C1.D0.R0: CheckMCTest: result = 0x3FFFF
N6.C0.D1.R0.S12: Total Delay in PI ticks: TxDQS = 970, TxDQ = 935
N0.C0.D1.R0.S06: Total Delay in PI ticks: TxDQS = 960, TxDQ = 924
ACCM: 0F 0F0F0F0F 0F0F0F0F
ACCM: DF 0F0F0FDF 0F0F0F0F
N6.C0.D1.R0.S13: Total Delay in PI ticks: TxDQS = 934, TxDQ = 899
N0.C0.D1.R0.S07: Total Delay in PI ticks: TxDQS = 980, TxDQ = 944
ACCM: 0F 0F0F0F0F 0F0F0F0F
ACCM: DF 0F0F0FDF 0F0F0F0F
N6.C0.D1.R0.S14: Total Delay in PI ticks: TxDQS = 953, TxDQ = 917
N0.C0.D1.R0.S08: Total Delay in PI ticks: TxDQS = 950, TxDQ = 916
ACCM: 00 00000B0A 000B0000
ACCM: F0 FFFDF0DF FFF0F0F0
N6.C0.D1.R0.S15: Total Delay in PI ticks: TxDQS = 957, TxDQ = 921
N0.C0.D1.R0.S09: Total Delay in PI ticks: TxDQS = 1019, TxDQ = 983
ACCM: 00 00000B0A 000B0000
ACCM: F0 FFFDF0DF FFF0F0F0
N6.C0.D1.R0.S16: Total Delay in PI ticks: TxDQS = 974, TxDQ = 937
N0.C0.D1.R0.S10: Total Delay in PI ticks: TxDQS = 1004, TxDQ = 969
N2.C2.D1.R1: CheckMCTest: result = 0x1FF
N4.C1.D0.R0: CheckMCTest: result = 0x3FFFF
N6.C0.D1.R0.S17: Total Delay in PI ticks: TxDQS = 944, TxDQ = 908
N0.C0.D1.R0.S11: Total Delay in PI ticks: TxDQS = 991, TxDQ = 957
ACCM: 0F 0F0F0F0F 0F0F0F0F
ACCM: D0 000000D0 00000000
N6.C0.D1.R1.S00: Total Delay in PI ticks: TxDQS = 1008, TxDQ = 973
N0.C0.D1.R0.S12: Total Delay in PI ticks: TxDQS = 978, TxDQ = 943
ACCM: 0F 0F0F0F0F 0F0F0F0F
ACCM: D0 000000D0 00000000
N6.C0.D1.R1.S01: Total Delay in PI ticks: TxDQS = 992, TxDQ = 957
N0.C0.D1.R0.S13: Total Delay in PI ticks: TxDQS = 943, TxDQ = 907
ACCM: 00 00000F0E 000F0000
ACCM: F0 F0F0F0D0 F0F0F0F0
N6.C0.D1.R1.S02: Total Delay in PI ticks: TxDQS = 978, TxDQ = 942
N0.C0.D1.R0.S14: Total Delay in PI ticks: TxDQS = 959, TxDQ = 925
ACCM: 00 00000F0E 000F0000
ACCM: F0 F0F0F0D0 F0F0F0F0
N6.C0.D1.R1.S03: Total Delay in PI ticks: TxDQS = 966, TxDQ = 931
N0.C0.D1.R0.S15: Total Delay in PI ticks: TxDQS = 963, TxDQ = 930
N2.C2.D1.R1: CheckMCTest: result = 0x1FF
N4.C1.D0.R0: CheckMCTest: result = 0x3FE00
N6.C0.D1.R1.S04: Total Delay in PI ticks: TxDQS = 930, TxDQ = 895
N0.C0.D1.R0.S16: Total Delay in PI ticks: TxDQS = 982, TxDQ = 948
N2.C2.D1.R1: CheckMCTest: passed
ACCM: D0 000000D0 00000000
N6.C0.D1.R1.S05: Total Delay in PI ticks: TxDQS = 950, TxDQ = 915
N0.C0.D1.R0.S17: Total Delay in PI ticks: TxDQS = 951, TxDQ = 916
N2.C2.D1.R1: CheckMCTest: passed
ACCM: D0 000000D0 00000000
N6.C0.D1.R1.S06: Total Delay in PI ticks: TxDQS = 952, TxDQ = 917
N0.C0.D1.R1.S00: Total Delay in PI ticks: TxDQS = 1017, TxDQ = 982
N2.C2.D1.R1.S00: Offset Found: RdPtrOffsetDqs = 007
ACCM: F0 F0F0F0D0 F0F0F0F0
N6.C0.D1.R1.S07: Total Delay in PI ticks: TxDQS = 968, TxDQ = 932
N0.C0.D1.R1.S01: Total Delay in PI ticks: TxDQS = 1001, TxDQ = 966
N2.C2.D1.R1.S01: Offset Found: RdPtrOffsetDqs = 007
ACCM: F0 F0F0F0D0 F0F0F0F0
N6.C0.D1.R1.S08: Total Delay in PI ticks: TxDQS = 938, TxDQ = 902
N0.C0.D1.R1.S02: Total Delay in PI ticks: TxDQS = 990, TxDQ = 955
N2.C2.D1.R1.S02: Offset Found: RdPtrOffsetDqs = 007
N4.C1.D0.R0: CheckMCTest: result = 0x3FE00
N6.C0.D1.R1.S09: Total Delay in PI ticks: TxDQS = 1009, TxDQ = 974
N0.C0.D1.R1.S03: Total Delay in PI ticks: TxDQS = 974, TxDQ = 939
N2.C2.D1.R1.S03: Offset Found: RdPtrOffsetDqs = 007
N4.C1.D0.R0.S00: Offset Found: RdPtrOffsetDqs = 007
N6.C0.D1.R1.S10: Total Delay in PI ticks: TxDQS = 993, TxDQ = 960
N0.C0.D1.R1.S04: Total Delay in PI ticks: TxDQS = 940, TxDQ = 905
N2.C2.D1.R1.S04: Offset Found: RdPtrOffsetDqs = 006
N4.C1.D0.R0.S01: Offset Found: RdPtrOffsetDqs = 007
N6.C0.D1.R1.S11: Total Delay in PI ticks: TxDQS = 982, TxDQ = 947
N0.C0.D1.R1.S05: Total Delay in PI ticks: TxDQS = 960, TxDQ = 924
N2.C2.D1.R1.S05: Offset Found: RdPtrOffsetDqs = 006
N4.C1.D0.R0.S02: Offset Found: RdPtrOffsetDqs = 007
N6.C0.D1.R1.S12: Total Delay in PI ticks: TxDQS = 966, TxDQ = 931
N0.C0.D1.R1.S06: Total Delay in PI ticks: TxDQS = 960, TxDQ = 924
N2.C2.D1.R1.S06: Offset Found: RdPtrOffsetDqs = 006
N4.C1.D0.R0.S03: Offset Found: RdPtrOffsetDqs = 007
N6.C0.D1.R1.S13: Total Delay in PI ticks: TxDQS = 930, TxDQ = 894
N0.C0.D1.R1.S07: Total Delay in PI ticks: TxDQS = 976, TxDQ = 940
N2.C2.D1.R1.S07: Offset Found: RdPtrOffsetDqs = 007
N4.C1.D0.R0.S04: Offset Found: RdPtrOffsetDqs = 006
N6.C0.D1.R1.S14: Total Delay in PI ticks: TxDQS = 949, TxDQ = 913
N0.C0.D1.R1.S08: Total Delay in PI ticks: TxDQS = 944, TxDQ = 910
N2.C2.D1.R1.S08: Offset Found: RdPtrOffsetDqs = 006
N4.C1.D0.R0.S05: Offset Found: RdPtrOffsetDqs = 006
N6.C0.D1.R1.S15: Total Delay in PI ticks: TxDQS = 952, TxDQ = 915
N0.C0.D1.R1.S09: Total Delay in PI ticks: TxDQS = 1017, TxDQ = 980
N2.C2.D1.R1: Write Training Coarse, upper nibbles
N4.C1.D0.R0.S06: Offset Found: RdPtrOffsetDqs = 007
N6.C0.D1.R1.S16: Total Delay in PI ticks: TxDQS = 967, TxDQ = 930
N0.C0.D1.R1.S10: Total Delay in PI ticks: TxDQS = 1002, TxDQ = 966
N2.C2.D1.R1.S09: Dq Delay estimate: 457
N4.C1.D0.R0.S07: Offset Found: RdPtrOffsetDqs = 007
N6.C0.D1.R1.S17: Total Delay in PI ticks: TxDQS = 938, TxDQ = 902
N0.C0.D1.R1.S11: Total Delay in PI ticks: TxDQS = 990, TxDQ = 956
N2.C2.D1.R1.S10: Dq Delay estimate: 446
N4.C1.D0.R0.S08: Offset Found: RdPtrOffsetDqs = 007
N6.C1.D0.R0: Write Training Coarse, lower nibbles / bytes
N0.C0.D1.R1.S12: Total Delay in PI ticks: TxDQS = 975, TxDQ = 940
N2.C2.D1.R1.S11: Dq Delay estimate: 434
N4.C1.D0.R0: Write Training Coarse, upper nibbles
N6.C1.D0.R0.S00: Dq Delay estimate: 469
N0.C0.D1.R1.S13: Total Delay in PI ticks: TxDQS = 942, TxDQ = 906
N2.C2.D1.R1.S12: Dq Delay estimate: 421
N4.C1.D0.R0.S09: Dq Delay estimate: 473
N6.C1.D0.R0.S01: Dq Delay estimate: 451
N0.C0.D1.R1.S14: Total Delay in PI ticks: TxDQS = 958, TxDQ = 924
N2.C2.D1.R1.S13: Dq Delay estimate: 380
N4.C1.D0.R0.S10: Dq Delay estimate: 455
N6.C1.D0.R0.S02: Dq Delay estimate: 442
N0.C0.D1.R1.S15: Total Delay in PI ticks: TxDQS = 961, TxDQ = 928
N2.C2.D1.R1.S14: Dq Delay estimate: 407
N4.C1.D0.R0.S11: Dq Delay estimate: 451
N6.C1.D0.R0.S03: Dq Delay estimate: 426
N0.C0.D1.R1.S16: Total Delay in PI ticks: TxDQS = 976, TxDQ = 942
N2.C2.D1.R1.S15: Dq Delay estimate: 402
N4.C1.D0.R0.S12: Dq Delay estimate: 430
N6.C1.D0.R0.S04: Dq Delay estimate: 392
N0.C0.D1.R1.S17: Total Delay in PI ticks: TxDQS = 945, TxDQ = 910
N2.C2.D1.R1.S16: Dq Delay estimate: 427
N4.C1.D0.R0.S13: Dq Delay estimate: 397
N6.C1.D0.R0.S05: Dq Delay estimate: 407
N0.C1.D0.R0: Write Training Coarse, lower nibbles / bytes
N2.C2.D1.R1.S17: Dq Delay estimate: 391
N4.C1.D0.R0.S14: Dq Delay estimate: 411
N6.C1.D0.R0.S06: Dq Delay estimate: 423
N0.C1.D0.R0.S00: Dq Delay estimate: 474
ACCM: F0 F0F0F0F0 F0F0F0F0
N4.C1.D0.R0.S15: Dq Delay estimate: 420
N6.C1.D0.R0.S07: Dq Delay estimate: 438
N0.C1.D0.R0.S01: Dq Delay estimate: 453
ACCM: F0 F0F0F0F0 F0F0F0F0
N4.C1.D0.R0.S16: Dq Delay estimate: 438
N6.C1.D0.R0.S08: Dq Delay estimate: 410
N0.C1.D0.R0.S02: Dq Delay estimate: 448
ACCM: F0 F0F0F0F0 F0F0F0F0
N4.C1.D0.R0.S17: Dq Delay estimate: 412
ACCM: 9F 0FBF9F9F 0F0F0F0F
N0.C1.D0.R0.S03: Dq Delay estimate: 430
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: 9F 0FBF9F9F 0F0F0F0F
N0.C1.D0.R0.S04: Dq Delay estimate: 396
N2.C2.D1.R1: CheckMCTest: result = 0x3FE00
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: 9F FFBF9F9F FFFFFFFF
N0.C1.D0.R0.S05: Dq Delay estimate: 410
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: 9F FFBF9F9F FFFFFFFF
N0.C1.D0.R0.S06: Dq Delay estimate: 427
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: F0 F0F0F0F0 F0F0F0F0
N6.C1.D0.R0: CheckMCTest: result = 0x3FFFF
N0.C1.D0.R0.S07: Dq Delay estimate: 443
ACCM: F0 F0F0F0F0 F0F0F0F0
N4.C1.D0.R0: CheckMCTest: result = 0x3FE00
ACCM: DF 0FFFDFDF 0F0F0F0F
N0.C1.D0.R0.S08: Dq Delay estimate: 411
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: DF 0FFFDFDF 0F0F0F0F
ACCM: FF 0F0FDF9F 0F0F0F0F
N2.C2.D1.R1: CheckMCTest: result = 0x3FE00
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: DF FFFFDFDF FFFFFFFF
ACCM: FF 0F0FDF9F 0F0F0F0F
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: DF FFFFDFDF FFFFFFFF
ACCM: FF FFFFFF9F FFFFFFFF
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: F0 F0F0F0F0 F0F0F0F0
N6.C1.D0.R0: CheckMCTest: result = 0x3FFFF
ACCM: FF FFFFFF9F FFFFFFFF
ACCM: 00 0000B0B0 00000000
N4.C1.D0.R0: CheckMCTest: result = 0x3FE00
ACCM: DF 0FFFDFDF 0F0F0F0F
N0.C1.D0.R0: CheckMCTest: result = 0x3FFFF
ACCM: 00 0000B0B0 00000000
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: DF 0FFFDFDF 0F0F0F0F
ACCM: FF 0F0FDFDF 0F0F0F0F
N2.C2.D1.R1: CheckMCTest: result = 0x3FE00
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: D0 FBFBDBDB FBF0FBFB
ACCM: FF 0F0FDFDF 0F0F0F0F
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: 00 0000B0B0 B0000000
ACCM: D0 FBFBDBDB FBF0FBFB
ACCM: FF FFFFFFDF FFFFFFFF
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: 00 0000B0B0 B0000000
N6.C1.D0.R0: CheckMCTest: result = 0x3FFFF
ACCM: FF FFFFFFDF FFFFFFFF
ACCM: 00 0000F0F0 D0000000
N4.C1.D0.R0: CheckMCTest: result = 0x3FE00
ACCM: DF 0FFFDFDF 0F0F0F0F
N0.C1.D0.R0: CheckMCTest: result = 0x3FFFF
ACCM: 00 0000F0F0 D0000000
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: DF 0FFFDFDF 0F0F0F0F
ACCM: FF 0F0FFFDF 0F0F0F0F
N2.C2.D1.R1: CheckMCTest: result = 0x3FE00
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: D0 FFFFDFDF FFF0FFFF
ACCM: FF 0F0FFFDF 0F0F0F0F
N2.C2.D1.R1: CheckMCTest: passed
ACCM: 00 0000F0F0 B0000000
ACCM: D0 FFFFDFDF FFF0FFFF
ACCM: F0 FBFBFBDB FBFBFBFB
N2.C2.D1.R1: CheckMCTest: passed
ACCM: 00 0000F0F0 B0000000
N6.C1.D0.R0: CheckMCTest: result = 0x3FFFF
ACCM: F0 FBFBFBDB FBFBFBFB
N2.C2.D1.R1.S09: Offset Found: RdPtrOffsetDqs = 007
N4.C1.D0.R0: CheckMCTest: result = 0x3FE00
ACCM: D0 00F0D0D0 00000000
N0.C1.D0.R0: CheckMCTest: result = 0x3FFFF
N2.C2.D1.R1.S10: Offset Found: RdPtrOffsetDqs = 007
N4.C1.D0.R0: CheckMCTest: passed
ACCM: D0 00F0D0D0 00000000
ACCM: FF 0F0FFFDF 0F0F0F0F
N2.C2.D1.R1.S11: Offset Found: RdPtrOffsetDqs = 007
N4.C1.D0.R0: CheckMCTest: passed
ACCM: D0 F0F0D0D0 F0F0F0F0
ACCM: FF 0F0FFFDF 0F0F0F0F
N2.C2.D1.R1.S12: Offset Found: RdPtrOffsetDqs = 007
N4.C1.D0.R0.S09: Offset Found: RdPtrOffsetDqs = 007
ACCM: D0 F0F0D0D0 F0F0F0F0
ACCM: FD FFFFFFDF FFFFFFFF
N2.C2.D1.R1.S13: Offset Found: RdPtrOffsetDqs = 006
N4.C1.D0.R0.S10: Offset Found: RdPtrOffsetDqs = 007
N6.C1.D0.R0: CheckMCTest: result = 0x3FE00
ACCM: FD FFFFFFDF FFFFFFFF
N2.C2.D1.R1.S14: Offset Found: RdPtrOffsetDqs = 006
N4.C1.D0.R0.S11: Offset Found: RdPtrOffsetDqs = 007
ACCM: D0 00F0D0D0 00000000
N0.C1.D0.R0: CheckMCTest: result = 0x3FFFF
N2.C2.D1.R1.S15: Offset Found: RdPtrOffsetDqs = 006
N4.C1.D0.R0.S12: Offset Found: RdPtrOffsetDqs = 007
ACCM: D0 00F0D0D0 00000000
ACCM: F0 0000F0D0 00000000
N2.C2.D1.R1.S16: Offset Found: RdPtrOffsetDqs = 007
N4.C1.D0.R0.S13: Offset Found: RdPtrOffsetDqs = 006
ACCM: D0 F0F0D0D0 F0F0F0F0
ACCM: F0 0000F0D0 00000000
N2.C2.D1.R1.S17: Offset Found: RdPtrOffsetDqs = 006
N4.C1.D0.R0.S14: Offset Found: RdPtrOffsetDqs = 006
ACCM: D0 F0F0D0D0 F0F0F0F0
ACCM: F0 F0F0F0D0 F0F0F0F0
N2.C2: Calculating Optimimum DQS Values
N4.C1.D0.R0.S15: Offset Found: RdPtrOffsetDqs = 007
N6.C1.D0.R0: CheckMCTest: result = 0x3FE00
ACCM: F0 F0F0F0D0 F0F0F0F0
N2.C2.D0.R0.S00: Total Delay in PI ticks: TxDQS = 1009, TxDQ = 976
N4.C1.D0.R0.S16: Offset Found: RdPtrOffsetDqs = 007
N6.C1.D0.R0.S00: Offset Found: RdPtrOffsetDqs = 007
N0.C1.D0.R0: CheckMCTest: result = 0x3FE00
N2.C2.D0.R0.S01: Total Delay in PI ticks: TxDQS = 994, TxDQ = 960
N4.C1.D0.R0.S17: Offset Found: RdPtrOffsetDqs = 007
N6.C1.D0.R0.S01: Offset Found: RdPtrOffsetDqs = 007
ACCM: F0 0000F0D0 00000000
N2.C2.D0.R0.S02: Total Delay in PI ticks: TxDQS = 984, TxDQ = 949
N4.C1.D0.R1: Write Training Coarse, lower nibbles / bytes
N6.C1.D0.R0.S02: Offset Found: RdPtrOffsetDqs = 007
ACCM: F0 0000F0D0 00000000
N2.C2.D0.R0.S03: Total Delay in PI ticks: TxDQS = 966, TxDQ = 932
N4.C1.D0.R1.S00: Dq Delay estimate: 462
N6.C1.D0.R0.S03: Offset Found: RdPtrOffsetDqs = 007
ACCM: F0 F0F0F0D0 F0F0F0F0
N2.C2.D0.R0.S04: Total Delay in PI ticks: TxDQS = 925, TxDQ = 892
N4.C1.D0.R1.S01: Dq Delay estimate: 448
N6.C1.D0.R0.S04: Offset Found: RdPtrOffsetDqs = 006
ACCM: F0 F0F0F0D0 F0F0F0F0
N2.C2.D0.R0.S05: Total Delay in PI ticks: TxDQS = 954, TxDQ = 918
N4.C1.D0.R1.S02: Dq Delay estimate: 438
N6.C1.D0.R0.S05: Offset Found: RdPtrOffsetDqs = 006
N0.C1.D0.R0: CheckMCTest: result = 0x3FE00
N2.C2.D0.R0.S06: Total Delay in PI ticks: TxDQS = 953, TxDQ = 919
N4.C1.D0.R1.S03: Dq Delay estimate: 424
N6.C1.D0.R0.S06: Offset Found: RdPtrOffsetDqs = 007
N0.C1.D0.R0.S00: Offset Found: RdPtrOffsetDqs = 007
N2.C2.D0.R0.S07: Total Delay in PI ticks: TxDQS = 975, TxDQ = 938
N4.C1.D0.R1.S04: Dq Delay estimate: 388
N6.C1.D0.R0.S07: Offset Found: RdPtrOffsetDqs = 007
N0.C1.D0.R0.S01: Offset Found: RdPtrOffsetDqs = 007
N2.C2.D0.R0.S08: Total Delay in PI ticks: TxDQS = 947, TxDQ = 912
N4.C1.D0.R1.S05: Dq Delay estimate: 404
N6.C1.D0.R0.S08: Offset Found: RdPtrOffsetDqs = 006
N0.C1.D0.R0.S02: Offset Found: RdPtrOffsetDqs = 007
N2.C2.D0.R0.S09: Total Delay in PI ticks: TxDQS = 1011, TxDQ = 976
N4.C1.D0.R1.S06: Dq Delay estimate: 412
N6.C1.D0.R0: Write Training Coarse, upper nibbles
N0.C1.D0.R0.S03: Offset Found: RdPtrOffsetDqs = 007
N2.C2.D0.R0.S10: Total Delay in PI ticks: TxDQS = 993, TxDQ = 960
N4.C1.D0.R1.S07: Dq Delay estimate: 433
N6.C1.D0.R0.S09: Dq Delay estimate: 466
N0.C1.D0.R0.S04: Offset Found: RdPtrOffsetDqs = 006
N2.C2.D0.R0.S11: Total Delay in PI ticks: TxDQS = 983, TxDQ = 947
N4.C1.D0.R1.S08: Dq Delay estimate: 403
N6.C1.D0.R0.S10: Dq Delay estimate: 451
N0.C1.D0.R0.S05: Offset Found: RdPtrOffsetDqs = 006
N2.C2.D0.R0.S12: Total Delay in PI ticks: TxDQS = 967, TxDQ = 932
ACCM: 0F 0F0F0F0F 0F0F0F0F
N6.C1.D0.R0.S11: Dq Delay estimate: 446
N0.C1.D0.R0.S06: Offset Found: RdPtrOffsetDqs = 007
N2.C2.D0.R0.S13: Total Delay in PI ticks: TxDQS = 926, TxDQ = 893
ACCM: 0F 0F0F0F0F 0F0F0F0F
N6.C1.D0.R0.S12: Dq Delay estimate: 427
N0.C1.D0.R0.S07: Offset Found: RdPtrOffsetDqs = 007
N2.C2.D0.R0.S14: Total Delay in PI ticks: TxDQS = 953, TxDQ = 917
ACCM: 0F 0F0F0F0F 0F0F0F0F
N6.C1.D0.R0.S13: Dq Delay estimate: 391
N0.C1.D0.R0.S08: Offset Found: RdPtrOffsetDqs = 006
N2.C2.D0.R0.S15: Total Delay in PI ticks: TxDQS = 952, TxDQ = 916
ACCM: 0F 0F0F0F0F 0F0F0F0F
N6.C1.D0.R0.S14: Dq Delay estimate: 404
N0.C1.D0.R0: Write Training Coarse, upper nibbles
N2.C2.D0.R0.S16: Total Delay in PI ticks: TxDQS = 976, TxDQ = 940
N4.C1.D0.R1: CheckMCTest: result = 0x1FF
N6.C1.D0.R0.S15: Dq Delay estimate: 422
N0.C1.D0.R0.S09: Dq Delay estimate: 473
N2.C2.D0.R0.S17: Total Delay in PI ticks: TxDQS = 946, TxDQ = 910
ACCM: 0F 0F0F0F0F 0F0F0F0F
N6.C1.D0.R0.S16: Dq Delay estimate: 435
N0.C1.D0.R0.S10: Dq Delay estimate: 454
N2.C2.D0.R1.S00: Total Delay in PI ticks: TxDQS = 1002, TxDQ = 969
ACCM: 0F 0F0F0F0F 0F0F0F0F
N6.C1.D0.R0.S17: Dq Delay estimate: 409
N0.C1.D0.R0.S11: Dq Delay estimate: 450
N2.C2.D0.R1.S01: Total Delay in PI ticks: TxDQS = 988, TxDQ = 954
ACCM: 0F 0F0F0F0F 0F0F0F0F
ACCM: F0 F0F0F0F0 F0F0F0F0
N0.C1.D0.R0.S12: Dq Delay estimate: 430
N2.C2.D0.R1.S02: Total Delay in PI ticks: TxDQS = 977, TxDQ = 942
ACCM: 0F 0F0F0F0F 0F0F0F0F
ACCM: F0 F0F0F0F0 F0F0F0F0
N0.C1.D0.R0.S13: Dq Delay estimate: 396
N2.C2.D0.R1.S03: Total Delay in PI ticks: TxDQS = 959, TxDQ = 925
N4.C1.D0.R1: CheckMCTest: result = 0x1FF
ACCM: F0 F0F0F0F0 F0F0F0F0
N0.C1.D0.R0.S14: Dq Delay estimate: 409
N2.C2.D0.R1.S04: Total Delay in PI ticks: TxDQS = 919, TxDQ = 886
ACCM: 0F 0F0F0F0F 0F0F0F0F
ACCM: F0 F0F0F0F0 F0F0F0F0
N0.C1.D0.R0.S15: Dq Delay estimate: 425
N2.C2.D0.R1.S05: Total Delay in PI ticks: TxDQS = 948, TxDQ = 912
ACCM: 0F 0F0F0F0F 0F0F0F0F
N6.C1.D0.R0: CheckMCTest: result = 0x3FE00
N0.C1.D0.R0.S16: Dq Delay estimate: 443
N2.C2.D0.R1.S06: Total Delay in PI ticks: TxDQS = 945, TxDQ = 912
ACCM: 0B 00000000 0B0B0B00
ACCM: F0 F0F0F0F0 F0F0F0F0
N0.C1.D0.R0.S17: Dq Delay estimate: 415
N2.C2.D0.R1.S07: Total Delay in PI ticks: TxDQS = 969, TxDQ = 932
ACCM: 0B 00000000 0B0B0B00
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: F0 F0F0F0F0 F0F0F0F0
N2.C2.D0.R1.S08: Total Delay in PI ticks: TxDQS = 937, TxDQ = 902
N4.C1.D0.R1: CheckMCTest: result = 0x1FF
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: F0 F0F0F0F0 F0F0F0F0
N2.C2.D0.R1.S09: Total Delay in PI ticks: TxDQS = 1001, TxDQ = 966
ACCM: 0F 0F0F0F0F 0F0F0F0F
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: F0 F0F0F0F0 F0F0F0F0
N2.C2.D0.R1.S10: Total Delay in PI ticks: TxDQS = 988, TxDQ = 953
ACCM: 0F 0F0F0F0F 0F0F0F0F
N6.C1.D0.R0: CheckMCTest: result = 0x3FE00
ACCM: F0 F0F0F0F0 F0F0F0F0
N2.C2.D0.R1.S11: Total Delay in PI ticks: TxDQS = 977, TxDQ = 941
ACCM: 0F 00000000 0F0F0F00
ACCM: F0 F0F0F0F0 F0F0F0F0
N0.C1.D0.R0: CheckMCTest: result = 0x3FE00
N2.C2.D0.R1.S12: Total Delay in PI ticks: TxDQS = 961, TxDQ = 926
ACCM: 0F 00000000 0F0F0F00
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: F0 F0F0F0F0 F0F0F0F0
N2.C2.D0.R1.S13: Total Delay in PI ticks: TxDQS = 919, TxDQ = 886
N4.C1.D0.R1: CheckMCTest: result = 0x1FF
ACCM: 00 B0B0B0B0 B000B0B0
ACCM: F0 F0F0F0F0 F0F0F0F0
N2.C2.D0.R1.S14: Total Delay in PI ticks: TxDQS = 948, TxDQ = 912
N4.C1.D0.R1: CheckMCTest: passed
ACCM: 00 B0B0B0B0 B000B0B0
ACCM: F0 F0F0F0F0 F0F0F0F0
N2.C2.D0.R1.S15: Total Delay in PI ticks: TxDQS = 946, TxDQ = 910
N4.C1.D0.R1: CheckMCTest: passed
N6.C1.D0.R0: CheckMCTest: result = 0x3FE00
ACCM: F0 F0F0F0F0 F0F0F0F0
N2.C2.D0.R1.S16: Total Delay in PI ticks: TxDQS = 970, TxDQ = 934
N4.C1.D0.R1.S00: Offset Found: RdPtrOffsetDqs = 007
ACCM: F0 F0F0F0F0 F0F0F0F0
N0.C1.D0.R0: CheckMCTest: result = 0x3FE00
N2.C2.D0.R1.S17: Total Delay in PI ticks: TxDQS = 937, TxDQ = 902
N4.C1.D0.R1.S01: Offset Found: RdPtrOffsetDqs = 007
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: F0 F0F0F0F0 F0F0F0F0
N2.C2.D1.R0.S00: Total Delay in PI ticks: TxDQS = 1010, TxDQ = 975
N4.C1.D0.R1.S02: Offset Found: RdPtrOffsetDqs = 007
ACCM: 00 F0F0F0F0 F000F0F0
ACCM: F0 F0F0F0F0 F0F0F0F0
N2.C2.D1.R0.S01: Total Delay in PI ticks: TxDQS = 998, TxDQ = 962
N4.C1.D0.R1.S03: Offset Found: RdPtrOffsetDqs = 007
ACCM: 00 F0F0F0F0 F000F0F0
ACCM: B0 00B000B0 0000B000
N2.C2.D1.R0.S02: Total Delay in PI ticks: TxDQS = 986, TxDQ = 949
N4.C1.D0.R1.S04: Offset Found: RdPtrOffsetDqs = 006
N6.C1.D0.R0: CheckMCTest: result = 0x3FE00
ACCM: B0 00B000B0 0000B000
N2.C2.D1.R0.S03: Total Delay in PI ticks: TxDQS = 973, TxDQ = 937
N4.C1.D0.R1.S05: Offset Found: RdPtrOffsetDqs = 006
N6.C1.D0.R0: CheckMCTest: passed
N0.C1.D0.R0: CheckMCTest: result = 0x3FE00
N2.C2.D1.R0.S04: Total Delay in PI ticks: TxDQS = 930, TxDQ = 894
N4.C1.D0.R1.S06: Offset Found: RdPtrOffsetDqs = 007
N6.C1.D0.R0: CheckMCTest: passed
ACCM: F0 F0F0F0F0 F0F0F0F0
N2.C2.D1.R0.S05: Total Delay in PI ticks: TxDQS = 960, TxDQ = 924
N4.C1.D0.R1.S07: Offset Found: RdPtrOffsetDqs = 007
N6.C1.D0.R0.S09: Offset Found: RdPtrOffsetDqs = 007
ACCM: F0 F0F0F0F0 F0F0F0F0
N2.C2.D1.R0.S06: Total Delay in PI ticks: TxDQS = 957, TxDQ = 922
N4.C1.D0.R1.S08: Offset Found: RdPtrOffsetDqs = 006
N6.C1.D0.R0.S10: Offset Found: RdPtrOffsetDqs = 007
ACCM: F0 00F000F0 00D0F0D0
N2.C2.D1.R0.S07: Total Delay in PI ticks: TxDQS = 979, TxDQ = 940
N4.C1.D0.R1: Write Training Coarse, upper nibbles
N6.C1.D0.R0.S11: Offset Found: RdPtrOffsetDqs = 007
ACCM: F0 00F000F0 00D0F0D0
N2.C2.D1.R0.S08: Total Delay in PI ticks: TxDQS = 945, TxDQ = 909
N4.C1.D0.R1.S09: Dq Delay estimate: 461
N6.C1.D0.R0.S12: Offset Found: RdPtrOffsetDqs = 007
N0.C1.D0.R0: CheckMCTest: result = 0x3FE00
N2.C2.D1.R0.S09: Total Delay in PI ticks: TxDQS = 1010, TxDQ = 973
N4.C1.D0.R1.S10: Dq Delay estimate: 451
N6.C1.D0.R0.S13: Offset Found: RdPtrOffsetDqs = 006
N0.C1.D0.R0: CheckMCTest: passed
N2.C2.D1.R0.S10: Total Delay in PI ticks: TxDQS = 998, TxDQ = 962
N4.C1.D0.R1.S11: Dq Delay estimate: 440
N6.C1.D0.R0.S14: Offset Found: RdPtrOffsetDqs = 006
N0.C1.D0.R0: CheckMCTest: passed
N2.C2.D1.R0.S11: Total Delay in PI ticks: TxDQS = 986, TxDQ = 949
N4.C1.D0.R1.S12: Dq Delay estimate: 426
N6.C1.D0.R0.S15: Offset Found: RdPtrOffsetDqs = 007
N0.C1.D0.R0.S09: Offset Found: RdPtrOffsetDqs = 007
N2.C2.D1.R0.S12: Total Delay in PI ticks: TxDQS = 972, TxDQ = 936
N4.C1.D0.R1.S13: Dq Delay estimate: 390
N6.C1.D0.R0.S16: Offset Found: RdPtrOffsetDqs = 007
N0.C1.D0.R0.S10: Offset Found: RdPtrOffsetDqs = 007
N2.C2.D1.R0.S13: Total Delay in PI ticks: TxDQS = 932, TxDQ = 898
N4.C1.D0.R1.S14: Dq Delay estimate: 408
N6.C1.D0.R0.S17: Offset Found: RdPtrOffsetDqs = 006
N0.C1.D0.R0.S11: Offset Found: RdPtrOffsetDqs = 007
N2.C2.D1.R0.S14: Total Delay in PI ticks: TxDQS = 959, TxDQ = 922
N4.C1.D0.R1.S15: Dq Delay estimate: 418
N6.C1.D0.R1: Write Training Coarse, lower nibbles / bytes
N0.C1.D0.R0.S12: Offset Found: RdPtrOffsetDqs = 007
N2.C2.D1.R0.S15: Total Delay in PI ticks: TxDQS = 957, TxDQ = 919
N4.C1.D0.R1.S16: Dq Delay estimate: 435
N6.C1.D0.R1.S00: Dq Delay estimate: 463
N0.C1.D0.R0.S13: Offset Found: RdPtrOffsetDqs = 006
N2.C2.D1.R0.S16: Total Delay in PI ticks: TxDQS = 979, TxDQ = 942
N4.C1.D0.R1.S17: Dq Delay estimate: 404
N6.C1.D0.R1.S01: Dq Delay estimate: 442
N0.C1.D0.R0.S14: Offset Found: RdPtrOffsetDqs = 006
N2.C2.D1.R0.S17: Total Delay in PI ticks: TxDQS = 946, TxDQ = 909
ACCM: F0 F0F0F0F0 F0F0F0F0
N6.C1.D0.R1.S02: Dq Delay estimate: 435
N0.C1.D0.R0.S15: Offset Found: RdPtrOffsetDqs = 007
N2.C2.D1.R1.S00: Total Delay in PI ticks: TxDQS = 1009, TxDQ = 974
ACCM: F0 F0F0F0F0 F0F0F0F0
N6.C1.D0.R1.S03: Dq Delay estimate: 419
N0.C1.D0.R0.S16: Offset Found: RdPtrOffsetDqs = 007
N2.C2.D1.R1.S01: Total Delay in PI ticks: TxDQS = 993, TxDQ = 957
ACCM: F0 F0F0F0F0 F0F0F0F0
N6.C1.D0.R1.S04: Dq Delay estimate: 388
N0.C1.D0.R0.S17: Offset Found: RdPtrOffsetDqs = 006
N2.C2.D1.R1.S02: Total Delay in PI ticks: TxDQS = 981, TxDQ = 944
ACCM: F0 F0F0F0F0 F0F0F0F0
N6.C1.D0.R1.S05: Dq Delay estimate: 400
N0.C1.D0.R1: Write Training Coarse, lower nibbles / bytes
N2.C2.D1.R1.S03: Total Delay in PI ticks: TxDQS = 969, TxDQ = 934
N4.C1.D0.R1: CheckMCTest: result = 0x3FE00
N6.C1.D0.R1.S06: Dq Delay estimate: 414
N0.C1.D0.R1.S00: Dq Delay estimate: 464
N2.C2.D1.R1.S04: Total Delay in PI ticks: TxDQS = 926, TxDQ = 890
ACCM: F0 F0F0F0F0 F0F0F0F0
N6.C1.D0.R1.S07: Dq Delay estimate: 431
N0.C1.D0.R1.S01: Dq Delay estimate: 446
N2.C2.D1.R1.S05: Total Delay in PI ticks: TxDQS = 957, TxDQ = 921
ACCM: F0 F0F0F0F0 F0F0F0F0
N6.C1.D0.R1.S08: Dq Delay estimate: 402
N0.C1.D0.R1.S02: Dq Delay estimate: 439
N2.C2.D1.R1.S06: Total Delay in PI ticks: TxDQS = 951, TxDQ = 916
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: 0F 0F0F0F0F 0F0F0F0F
N0.C1.D0.R1.S03: Dq Delay estimate: 424
N2.C2.D1.R1.S07: Total Delay in PI ticks: TxDQS = 977, TxDQ = 938
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: 0F 0F0F0F0F 0F0F0F0F
N0.C1.D0.R1.S04: Dq Delay estimate: 390
N2.C2.D1.R1.S08: Total Delay in PI ticks: TxDQS = 943, TxDQ = 907
N4.C1.D0.R1: CheckMCTest: result = 0x3FE00
ACCM: 0F 0F0F0F0F 0F0F0F0F
N0.C1.D0.R1.S05: Dq Delay estimate: 404
N2.C2.D1.R1.S09: Total Delay in PI ticks: TxDQS = 1006, TxDQ = 969
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: 0F 0F0F0F0F 0F0F0F0F
N0.C1.D0.R1.S06: Dq Delay estimate: 417
N2.C2.D1.R1.S10: Total Delay in PI ticks: TxDQS = 994, TxDQ = 958
ACCM: F0 F0F0F0F0 F0F0F0F0
N6.C1.D0.R1: CheckMCTest: result = 0x1FF
N0.C1.D0.R1.S07: Dq Delay estimate: 436
N2.C2.D1.R1.S11: Total Delay in PI ticks: TxDQS = 983, TxDQ = 946
ACCM: B0 00B0B0B0 00000000
ACCM: 0F 0F0F0F0F 0F0F0F0F
N0.C1.D0.R1.S08: Dq Delay estimate: 406
N2.C2.D1.R1.S12: Total Delay in PI ticks: TxDQS = 969, TxDQ = 933
ACCM: B0 00B0B0B0 00000000
ACCM: 0F 0F0F0F0F 0F0F0F0F
ACCM: 0F 0F0F0F0F 0F0F0F0F
N2.C2.D1.R1.S13: Total Delay in PI ticks: TxDQS = 927, TxDQ = 892
N4.C1.D0.R1: CheckMCTest: result = 0x3FE00
ACCM: 0F 0F0F0F0F 0F0F0F0F
ACCM: 0F 0F0F0F0F 0F0F0F0F
N2.C2.D1.R1.S14: Total Delay in PI ticks: TxDQS = 956, TxDQ = 919
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: 0F 0F0F0F0F 0F0F0F0F
ACCM: 0F 0F0F0F0F 0F0F0F0F
N2.C2.D1.R1.S15: Total Delay in PI ticks: TxDQS = 952, TxDQ = 914
ACCM: F0 F0F0F0F0 F0F0F0F0
N6.C1.D0.R1: CheckMCTest: result = 0x1FF
ACCM: 0F 0F0F0F0F 0F0F0F0F
N2.C2.D1.R1.S16: Total Delay in PI ticks: TxDQS = 976, TxDQ = 939
ACCM: F0 00F0F0F0 00000000
ACCM: 0F 0F0F0F0F 0F0F0F0F
N0.C1.D0.R1: CheckMCTest: result = 0x1FF
N2.C2.D1.R1.S17: Total Delay in PI ticks: TxDQS = 940, TxDQ = 903
ACCM: F0 00F0F0F0 00000000
ACCM: 0F 0F0F0F0F 0F0F0F0F
ACCM: 0F 0F0F0F0F 0F0F0F0F
N2.C3.D0.R0: Write Training Coarse, lower nibbles / bytes
N4.C1.D0.R1: CheckMCTest: result = 0x3FE00
ACCM: 00 0000000B 0B000000
ACCM: 0F 0F0F0F0F 0F0F0F0F
N2.C3.D0.R0.S00: Dq Delay estimate: 467
N4.C1.D0.R1: CheckMCTest: passed
ACCM: 00 0000000B 0B000000
ACCM: 0F 0F0F0F0F 0F0F0F0F
N2.C3.D0.R0.S01: Dq Delay estimate: 454
N4.C1.D0.R1: CheckMCTest: passed
N6.C1.D0.R1: CheckMCTest: result = 0x1FF
ACCM: 0F 0F0F0F0F 0F0F0F0F
N2.C3.D0.R0.S02: Dq Delay estimate: 443
N4.C1.D0.R1.S09: Offset Found: RdPtrOffsetDqs = 007
ACCM: 0F 0F0F0F0F 0F0F0F0F
N0.C1.D0.R1: CheckMCTest: result = 0x1FF
N2.C3.D0.R0.S03: Dq Delay estimate: 426
N4.C1.D0.R1.S10: Offset Found: RdPtrOffsetDqs = 007
ACCM: 0F 0F0F0F0F 0F0F0F0F
ACCM: 0F 0F0F0F0F 0F0F0F0F
N2.C3.D0.R0.S04: Dq Delay estimate: 393
N4.C1.D0.R1.S11: Offset Found: RdPtrOffsetDqs = 007
ACCM: 00 0000000F 0F000000
ACCM: 0F 0F0F0F0F 0F0F0F0F
N2.C3.D0.R0.S05: Dq Delay estimate: 404
N4.C1.D0.R1.S12: Offset Found: RdPtrOffsetDqs = 007
ACCM: 00 0000000F 0F000000
ACCM: 0B 0B0B000B 0B000B00
N2.C3.D0.R0.S06: Dq Delay estimate: 419
N4.C1.D0.R1.S13: Offset Found: RdPtrOffsetDqs = 006
N6.C1.D0.R1: CheckMCTest: result = 0x1FF
ACCM: 0B 0B0B000B 0B000B00
N2.C3.D0.R0.S07: Dq Delay estimate: 436
N4.C1.D0.R1.S14: Offset Found: RdPtrOffsetDqs = 006
N6.C1.D0.R1: CheckMCTest: passed
N0.C1.D0.R1: CheckMCTest: result = 0x1FF
N2.C3.D0.R0.S08: Dq Delay estimate: 412
N4.C1.D0.R1.S15: Offset Found: RdPtrOffsetDqs = 007
N6.C1.D0.R1: CheckMCTest: passed
ACCM: 0F 0F0F0F0F 0F0F0F0F
ACCM: 9F 0FDF9F9F 0F0F0F0F
N4.C1.D0.R1.S16: Offset Found: RdPtrOffsetDqs = 007
N6.C1.D0.R1.S00: Offset Found: RdPtrOffsetDqs = 007
ACCM: 0F 0F0F0F0F 0F0F0F0F
ACCM: 9F 0FDF9F9F 0F0F0F0F
N4.C1.D0.R1.S17: Offset Found: RdPtrOffsetDqs = 006
N6.C1.D0.R1.S01: Offset Found: RdPtrOffsetDqs = 007
ACCM: 0B 0F0F000F 0F000F00
ACCM: 9F FFFF9F9F FFFFFFFF
N4.C1.D1.R0: Write Training Coarse, lower nibbles / bytes
N6.C1.D0.R1.S02: Offset Found: RdPtrOffsetDqs = 007
ACCM: 0B 0F0F000F 0F000F00
ACCM: 9F FFFF9F9F FFFFFFFF
N4.C1.D1.R0.S00: Dq Delay estimate: 470
N6.C1.D0.R1.S03: Offset Found: RdPtrOffsetDqs = 007
N0.C1.D0.R1: CheckMCTest: result = 0x1FF
N2.C3.D0.R0: CheckMCTest: result = 0x3FFFF
N4.C1.D1.R0.S01: Dq Delay estimate: 454
N6.C1.D0.R1.S04: Offset Found: RdPtrOffsetDqs = 006
N0.C1.D0.R1: CheckMCTest: passed
ACCM: DF 0FDFDFDF 0F0F0F0F
N4.C1.D1.R0.S02: Dq Delay estimate: 443
N6.C1.D0.R1.S05: Offset Found: RdPtrOffsetDqs = 006
N0.C1.D0.R1: CheckMCTest: passed
ACCM: DF 0FDFDFDF 0F0F0F0F
N4.C1.D1.R0.S03: Dq Delay estimate: 427
N6.C1.D0.R1.S06: Offset Found: RdPtrOffsetDqs = 006
N0.C1.D0.R1.S00: Offset Found: RdPtrOffsetDqs = 007
ACCM: DF FFFFDFDF FFFFFFFF
N4.C1.D1.R0.S04: Dq Delay estimate: 392
N6.C1.D0.R1.S07: Offset Found: RdPtrOffsetDqs = 007
N0.C1.D0.R1.S01: Offset Found: RdPtrOffsetDqs = 007
ACCM: DF FFFFDFDF FFFFFFFF
N4.C1.D1.R0.S05: Dq Delay estimate: 407
N6.C1.D0.R1.S08: Offset Found: RdPtrOffsetDqs = 006
N0.C1.D0.R1.S02: Offset Found: RdPtrOffsetDqs = 007
N2.C3.D0.R0: CheckMCTest: result = 0x3FFFF
N4.C1.D1.R0.S06: Dq Delay estimate: 421
N6.C1.D0.R1: Write Training Coarse, upper nibbles
N0.C1.D0.R1.S03: Offset Found: RdPtrOffsetDqs = 007
ACCM: DF 0FDFDFDF 0F0F0F0F
N4.C1.D1.R0.S07: Dq Delay estimate: 435
N6.C1.D0.R1.S09: Dq Delay estimate: 458
N0.C1.D0.R1.S04: Offset Found: RdPtrOffsetDqs = 006
ACCM: DF 0FDFDFDF 0F0F0F0F
N4.C1.D1.R0.S08: Dq Delay estimate: 407
N6.C1.D0.R1.S10: Dq Delay estimate: 444
N0.C1.D0.R1.S05: Offset Found: RdPtrOffsetDqs = 006
ACCM: D0 FBFBDBDB FBF0FBF0
ACCM: 0F 0F0F0F0F 0F0F0F0F
N6.C1.D0.R1.S11: Dq Delay estimate: 439
N0.C1.D0.R1.S06: Offset Found: RdPtrOffsetDqs = 007
ACCM: D0 FBFBDBDB FBF0FBF0
ACCM: 0F 0F0F0F0F 0F0F0F0F
N6.C1.D0.R1.S12: Dq Delay estimate: 420
N0.C1.D0.R1.S07: Offset Found: RdPtrOffsetDqs = 007
N2.C3.D0.R0: CheckMCTest: result = 0x3FFFF
ACCM: 0F 0F0F0F0F 0F0F0F0F
N6.C1.D0.R1.S13: Dq Delay estimate: 385
N0.C1.D0.R1.S08: Offset Found: RdPtrOffsetDqs = 006
ACCM: DF 0FDFDFDF 0F0F0F0F
ACCM: 0F FFFF0F0F FFFF0F0F
N6.C1.D0.R1.S14: Dq Delay estimate: 398
N0.C1.D0.R1: Write Training Coarse, upper nibbles
ACCM: DF 0FDFDFDF 0F0F0F0F
N4.C1.D1.R0: CheckMCTest: result = 0x199FF
N6.C1.D0.R1.S15: Dq Delay estimate: 414
N0.C1.D0.R1.S09: Dq Delay estimate: 463
ACCM: DD FFFFDFDF FFF0FFF0
ACCM: 0F 0F0F0F0F 0F0F0F0F
N6.C1.D0.R1.S16: Dq Delay estimate: 431
N0.C1.D0.R1.S10: Dq Delay estimate: 447
ACCM: DD FFFFDFDF FFF0FFF0
ACCM: 0F 0F0F0F0F 0F0F0F0F
N6.C1.D0.R1.S17: Dq Delay estimate: 400
N0.C1.D0.R1.S11: Dq Delay estimate: 441
N2.C3.D0.R0: CheckMCTest: result = 0x3FFFF
ACCM: 0F 0F0F0F0F 0F0F0F0F
ACCM: F0 F0F0F0F0 F0F0F0F0
N0.C1.D0.R1.S12: Dq Delay estimate: 425
ACCM: D0 00D0D0D0 00000000
ACCM: 0F FFFF0F0F FFFF0F0F
ACCM: F0 F0F0F0F0 F0F0F0F0
N0.C1.D0.R1.S13: Dq Delay estimate: 392
ACCM: D0 00D0D0D0 00000000
N4.C1.D1.R0: CheckMCTest: result = 0x199FF
ACCM: F0 F0F0F0F0 F0F0F0F0
N0.C1.D0.R1.S14: Dq Delay estimate: 405
ACCM: D0 F0F0D0D0 F0F0F0F0
ACCM: 0F 0F0F0F0F 0F0F0F0F
ACCM: F0 F0F0F0F0 F0F0F0F0
N0.C1.D0.R1.S15: Dq Delay estimate: 417
ACCM: D0 F0F0D0D0 F0F0F0F0
ACCM: 0F 0F0F0F0F 0F0F0F0F
N6.C1.D0.R1: CheckMCTest: result = 0x3FE00
N0.C1.D0.R1.S16: Dq Delay estimate: 440
N2.C3.D0.R0: CheckMCTest: result = 0x3FE00
ACCM: 0B 000B0B0B 00000B0B
ACCM: F0 F0F0F0F0 F0F0F0F0
N0.C1.D0.R1.S17: Dq Delay estimate: 406
ACCM: D0 00F0D0D0 00000000
ACCM: 0B F0FB0B0B F0F00B0B
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: D0 00F0D0D0 00000000
N4.C1.D1.R0: CheckMCTest: result = 0x199FF
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: D0 F0F0D0D0 F0F0F0F0
ACCM: 0F 0F0F0F0F 0F0F0F0F
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: D0 F0F0D0D0 F0F0F0F0
ACCM: 0F 0F0F0F0F 0F0F0F0F
N6.C1.D0.R1: CheckMCTest: result = 0x3FE00
ACCM: F0 F0F0F0F0 F0F0F0F0
N2.C3.D0.R0: CheckMCTest: result = 0x3FE00
ACCM: 0F 000F0F0F 000C0F0F
ACCM: F0 F0F0F0F0 F0F0F0F0
N0.C1.D0.R1: CheckMCTest: result = 0x3FE00
N2.C3.D0.R0.S00: Offset Found: RdPtrOffsetDqs = 007
ACCM: 0F F0FF0F0F F0FC0F0F
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: F0 F0F0F0F0 F0F0F0F0
N2.C3.D0.R0.S01: Offset Found: RdPtrOffsetDqs = 007
N4.C1.D1.R0: CheckMCTest: result = 0x199FF
ACCM: 00 00000000 B0000000
ACCM: F0 F0F0F0F0 F0F0F0F0
N2.C3.D0.R0.S02: Offset Found: RdPtrOffsetDqs = 007
ACCM: 00 00000000 00000000
ACCM: 00 00000000 B0000000
ACCM: F0 F0F0F0F0 F0F0F0F0
N2.C3.D0.R0.S03: Offset Found: RdPtrOffsetDqs = 007
ACCM: 00 00000000 00000000
N6.C1.D0.R1: CheckMCTest: result = 0x3FE00
ACCM: F0 F0F0F0F0 F0F0F0F0
N2.C3.D0.R0.S04: Offset Found: RdPtrOffsetDqs = 006
ACCM: 00 00000000 00000000
ACCM: F0 F0F0F0F0 F0F0F0F0
N0.C1.D0.R1: CheckMCTest: result = 0x3FE00
N2.C3.D0.R0.S05: Offset Found: RdPtrOffsetDqs = 006
ACCM: 00 F0F00000 F0F00000
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: F0 F0F0F0F0 F0F0F0F0
N2.C3.D0.R0.S06: Offset Found: RdPtrOffsetDqs = 007
N4.C1.D1.R0: CheckMCTest: result = 0x19800
ACCM: 00 00000000 F0000000
ACCM: F0 F0F0F0F0 F0F0F0F0
N2.C3.D0.R0.S07: Offset Found: RdPtrOffsetDqs = 007
ACCM: 00 00000000 00000000
ACCM: 00 00000000 F0000000
ACCM: B0 0000B0B0 B0000000
N2.C3.D0.R0.S08: Offset Found: RdPtrOffsetDqs = 006
ACCM: 00 00000000 00000000
N6.C1.D0.R1: CheckMCTest: result = 0x3FE00
ACCM: B0 0000B0B0 B0000000
N2.C3.D0.R0: Write Training Coarse, upper nibbles
ACCM: 00 00000000 00000000
N6.C1.D0.R1: CheckMCTest: passed
N0.C1.D0.R1: CheckMCTest: result = 0x3FE00
N2.C3.D0.R0.S09: Dq Delay estimate: 468
ACCM: 00 F0F00000 F0F00000
N6.C1.D0.R1: CheckMCTest: passed
ACCM: F0 F0F0F0F0 F0F0F0F0
N2.C3.D0.R0.S10: Dq Delay estimate: 455
N4.C1.D1.R0: CheckMCTest: result = 0x19800
N6.C1.D0.R1.S09: Offset Found: RdPtrOffsetDqs = 007
ACCM: F0 F0F0F0F0 F0F0F0F0
N2.C3.D0.R0.S11: Dq Delay estimate: 444
N4.C1.D1.R0.S00: Offset Found: RdPtrOffsetDqs = 007
N6.C1.D0.R1.S10: Offset Found: RdPtrOffsetDqs = 007
ACCM: F0 0000F0F0 F0000000
N2.C3.D0.R0.S12: Dq Delay estimate: 428
N4.C1.D1.R0.S01: Offset Found: RdPtrOffsetDqs = 007
N6.C1.D0.R1.S11: Offset Found: RdPtrOffsetDqs = 007
ACCM: F0 0000F0F0 F0000000
N2.C3.D0.R0.S13: Dq Delay estimate: 393
N4.C1.D1.R0.S02: Offset Found: RdPtrOffsetDqs = 007
N6.C1.D0.R1.S12: Offset Found: RdPtrOffsetDqs = 007
N0.C1.D0.R1: CheckMCTest: result = 0x3FE00
N2.C3.D0.R0.S14: Dq Delay estimate: 405
N4.C1.D1.R0.S03: Offset Found: RdPtrOffsetDqs = 007
N6.C1.D0.R1.S13: Offset Found: RdPtrOffsetDqs = 006
N0.C1.D0.R1: CheckMCTest: passed
N2.C3.D0.R0.S15: Dq Delay estimate: 420
N4.C1.D1.R0.S04: Offset Found: RdPtrOffsetDqs = 006
N6.C1.D0.R1.S14: Offset Found: RdPtrOffsetDqs = 006
N0.C1.D0.R1: CheckMCTest: passed
N2.C3.D0.R0.S16: Dq Delay estimate: 432
N4.C1.D1.R0.S05: Offset Found: RdPtrOffsetDqs = 006
N6.C1.D0.R1.S15: Offset Found: RdPtrOffsetDqs = 006
N0.C1.D0.R1.S09: Offset Found: RdPtrOffsetDqs = 007
N2.C3.D0.R0.S17: Dq Delay estimate: 414
N4.C1.D1.R0.S06: Offset Found: RdPtrOffsetDqs = 007
N6.C1.D0.R1.S16: Offset Found: RdPtrOffsetDqs = 007
N0.C1.D0.R1.S10: Offset Found: RdPtrOffsetDqs = 007
ACCM: F0 F0F0F0F0 F0F0F0F0
N4.C1.D1.R0.S07: Offset Found: RdPtrOffsetDqs = 007
N6.C1.D0.R1.S17: Offset Found: RdPtrOffsetDqs = 006
N0.C1.D0.R1.S11: Offset Found: RdPtrOffsetDqs = 007
ACCM: F0 F0F0F0F0 F0F0F0F0
N4.C1.D1.R0.S08: Offset Found: RdPtrOffsetDqs = 006
N6.C1.D1.R0: Write Training Coarse, lower nibbles / bytes
N0.C1.D0.R1.S12: Offset Found: RdPtrOffsetDqs = 007
ACCM: F0 F0F0F0F0 F0F0F0F0
N4.C1.D1.R0: Write Training Coarse, upper nibbles
N6.C1.D1.R0.S00: Dq Delay estimate: 471
N0.C1.D0.R1.S13: Offset Found: RdPtrOffsetDqs = 006
ACCM: F0 F0F0F0F0 F0F0F0F0
N4.C1.D1.R0.S09: Dq Delay estimate: 469
N6.C1.D1.R0.S01: Dq Delay estimate: 454
N0.C1.D0.R1.S14: Offset Found: RdPtrOffsetDqs = 006
N2.C3.D0.R0: CheckMCTest: result = 0x3FE00
N4.C1.D1.R0.S10: Dq Delay estimate: 453
N6.C1.D1.R0.S02: Dq Delay estimate: 446
N0.C1.D0.R1.S15: Offset Found: RdPtrOffsetDqs = 007
ACCM: F0 F0F0F0F0 F0F0F0F0
N4.C1.D1.R0.S11: Dq Delay estimate: 446
N6.C1.D1.R0.S03: Dq Delay estimate: 429
N0.C1.D0.R1.S16: Offset Found: RdPtrOffsetDqs = 007
ACCM: F0 F0F0F0F0 F0F0F0F0
N4.C1.D1.R0.S12: Dq Delay estimate: 428
N6.C1.D1.R0.S04: Dq Delay estimate: 396
N0.C1.D0.R1.S17: Offset Found: RdPtrOffsetDqs = 006
ACCM: F0 F0F0F0F0 F0F0F0F0
N4.C1.D1.R0.S13: Dq Delay estimate: 392
N6.C1.D1.R0.S05: Dq Delay estimate: 410
N0.C1.D1.R0: Write Training Coarse, lower nibbles / bytes
ACCM: F0 F0F0F0F0 F0F0F0F0
N4.C1.D1.R0.S14: Dq Delay estimate: 410
N6.C1.D1.R0.S06: Dq Delay estimate: 422
N0.C1.D1.R0.S00: Dq Delay estimate: 471
N2.C3.D0.R0: CheckMCTest: result = 0x3FE00
N4.C1.D1.R0.S15: Dq Delay estimate: 419
N6.C1.D1.R0.S07: Dq Delay estimate: 441
N0.C1.D1.R0.S01: Dq Delay estimate: 453
ACCM: F0 F0F0F0F0 F0F0F0F0
N4.C1.D1.R0.S16: Dq Delay estimate: 441
N6.C1.D1.R0.S08: Dq Delay estimate: 411
N0.C1.D1.R0.S02: Dq Delay estimate: 445
ACCM: F0 F0F0F0F0 F0F0F0F0
N4.C1.D1.R0.S17: Dq Delay estimate: 404
ACCM: 0F 0F0F0F0F 0F0F0F0F
N0.C1.D1.R0.S03: Dq Delay estimate: 433
ACCM: 00 B0B0B0B0 0000B0B0
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: 0F 0F0F0F0F 0F0F0F0F
N0.C1.D1.R0.S04: Dq Delay estimate: 399
ACCM: 00 B0B0B0B0 0000B0B0
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: 0F 0F0F0F0F 0F0F0F0F
N0.C1.D1.R0.S05: Dq Delay estimate: 409
N2.C3.D0.R0: CheckMCTest: result = 0x3FE00
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: 0F FF0F0F0F FFFFFF0F
N0.C1.D1.R0.S06: Dq Delay estimate: 428
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: F0 F0F0F0F0 F0F0F0F0
N6.C1.D1.R0: CheckMCTest: result = 0x11DFF
N0.C1.D1.R0.S07: Dq Delay estimate: 443
ACCM: F0 F0F0F0F0 F0F0F0F0
N4.C1.D1.R0: CheckMCTest: result = 0x3FE00
ACCM: 0F 0F0F0F0F 0F0F0F0F
N0.C1.D1.R0.S08: Dq Delay estimate: 411
ACCM: 00 F0F0F0F0 0000F0F0
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: 0F 0F0F0F0F 0F0F0F0F
ACCM: 0F 0F0F0F0F 0F0F0F0F
ACCM: 00 F0F0F0F0 0000F0F0
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: 0F 0F0F0F0F 0F0F0F0F
ACCM: 0F 0F0F0F0F 0F0F0F0F
N2.C3.D0.R0: CheckMCTest: result = 0x3FE00
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: 0F FF0F0F0F FFFFFF0F
ACCM: 0F 0F0F0F0F 0F0F0F0F
N2.C3.D0.R0: CheckMCTest: passed
ACCM: F0 F0F0F0F0 F0F0F0F0
N6.C1.D1.R0: CheckMCTest: result = 0x11DFF
ACCM: 0F FFFF0F0F FFFFFF0F
N2.C3.D0.R0: CheckMCTest: passed
N4.C1.D1.R0: CheckMCTest: result = 0x3FE00
ACCM: 0F 0F0F0F0F 0F0F0F0F
N0.C1.D1.R0: CheckMCTest: result = 0x19DFF
N2.C3.D0.R0.S09: Offset Found: RdPtrOffsetDqs = 007
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: 0F 0F0F0F0F 0F0F0F0F
ACCM: 0F 0F0F0F0F 0F0F0F0F
N2.C3.D0.R0.S10: Offset Found: RdPtrOffsetDqs = 007
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: 00 0B0B0B0B 0B0B0B0B
ACCM: 0F 0F0F0F0F 0F0F0F0F
N2.C3.D0.R0.S11: Offset Found: RdPtrOffsetDqs = 007
ACCM: 00 B0000000 0000B000
ACCM: 00 FB0B0B0B FBFBFB0B
ACCM: 0F 0F0F0F0F 0F0F0F0F
N2.C3.D0.R0.S12: Offset Found: RdPtrOffsetDqs = 007
ACCM: 00 B0000000 0000B000
N6.C1.D1.R0: CheckMCTest: result = 0x11DFF
ACCM: 0F FFFF0F0F FFFFFF0F
N2.C3.D0.R0.S13: Offset Found: RdPtrOffsetDqs = 006
N4.C1.D1.R0: CheckMCTest: result = 0x3FE00
ACCM: 0F 0F0F0F0F 0F0F0F0F
N0.C1.D1.R0: CheckMCTest: result = 0x19DFF
N2.C3.D0.R0.S14: Offset Found: RdPtrOffsetDqs = 006
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: 0F 0F0F0F0F 0F0F0F0F
ACCM: 0F 0F0F0F0F 0F0F0F0F
N2.C3.D0.R0.S15: Offset Found: RdPtrOffsetDqs = 007
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: 00 0F0F0F0F 0F0F0F0F
ACCM: 0F 0F0F0F0F 0F0F0F0F
N2.C3.D0.R0.S16: Offset Found: RdPtrOffsetDqs = 007
ACCM: 00 F0000000 0000F000
ACCM: 00 FF0F0F0F FFFFFF0F
ACCM: 00 0B0B000B 0B000B00
N2.C3.D0.R0.S17: Offset Found: RdPtrOffsetDqs = 006
ACCM: 00 F0000000 0000F000
N6.C1.D1.R0: CheckMCTest: result = 0x11DFF
ACCM: 00 FBFB000B FBF0FB00
N2.C3.D0.R1: Write Training Coarse, lower nibbles / bytes
N4.C1.D1.R0: CheckMCTest: result = 0x3FE00
ACCM: 00 00000000 00000000
N0.C1.D1.R0: CheckMCTest: result = 0x19DFF
N2.C3.D0.R1.S00: Dq Delay estimate: 462
N4.C1.D1.R0: CheckMCTest: passed
ACCM: 00 00000000 00000000
ACCM: 0F 0F0F0F0F 0F0F0F0F
N2.C3.D0.R1.S01: Dq Delay estimate: 445
N4.C1.D1.R0: CheckMCTest: passed
ACCM: 00 00000000 00000000
ACCM: 0F 0F0F0F0F 0F0F0F0F
N2.C3.D0.R1.S02: Dq Delay estimate: 434
N4.C1.D1.R0.S09: Offset Found: RdPtrOffsetDqs = 007
ACCM: 00 F0000000 F0F0F000
ACCM: 00 0F0F000F 0F0D0F00
N2.C3.D0.R1.S03: Dq Delay estimate: 422
N4.C1.D1.R0.S10: Offset Found: RdPtrOffsetDqs = 007
N6.C1.D1.R0: CheckMCTest: result = 0x11C00
ACCM: 00 FFFF000F FFFDFF00
N2.C3.D0.R1.S04: Dq Delay estimate: 386
N4.C1.D1.R0.S11: Offset Found: RdPtrOffsetDqs = 007
ACCM: 00 00000000 00000000
N0.C1.D1.R0: CheckMCTest: result = 0x19DFF
N2.C3.D0.R1.S05: Dq Delay estimate: 398
N4.C1.D1.R0.S12: Offset Found: RdPtrOffsetDqs = 007
ACCM: 00 00000000 00000000
ACCM: 00 00000000 00000000
N2.C3.D0.R1.S06: Dq Delay estimate: 411
N4.C1.D1.R0.S13: Offset Found: RdPtrOffsetDqs = 006
ACCM: 00 00000000 00000000
ACCM: 00 00000000 00000000
N2.C3.D0.R1.S07: Dq Delay estimate: 429
N4.C1.D1.R0.S14: Offset Found: RdPtrOffsetDqs = 006
ACCM: 00 F0000000 F0F0F000
ACCM: 00 00000000 00000000
N2.C3.D0.R1.S08: Dq Delay estimate: 405
N4.C1.D1.R0.S15: Offset Found: RdPtrOffsetDqs = 007
N6.C1.D1.R0: CheckMCTest: result = 0x11C00
ACCM: 00 F0F00000 F0F0F000
ACCM: 0F 0F0F0F0F 0F0F0F0F
N4.C1.D1.R0.S16: Offset Found: RdPtrOffsetDqs = 007
N6.C1.D1.R0.S00: Offset Found: RdPtrOffsetDqs = 007
N0.C1.D1.R0: CheckMCTest: result = 0x19C00
ACCM: 0F 0F0F0F0F 0F0F0F0F
N4.C1.D1.R0.S17: Offset Found: RdPtrOffsetDqs = 006
N6.C1.D1.R0.S01: Offset Found: RdPtrOffsetDqs = 007
ACCM: 00 00000000 00000000
ACCM: 0F 0F0F0F0F 0F0F0F0F
N4.C1.D1.R1: Write Training Coarse, lower nibbles / bytes
N6.C1.D1.R0.S02: Offset Found: RdPtrOffsetDqs = 007
ACCM: 00 00000000 00000000
ACCM: 0F 0F0F0F0F 0F0F0F0F
N4.C1.D1.R1.S00: Dq Delay estimate: 467
N6.C1.D1.R0.S03: Offset Found: RdPtrOffsetDqs = 007
ACCM: 00 00000000 00000000
N2.C3.D0.R1: CheckMCTest: result = 0x1FF
N4.C1.D1.R1.S01: Dq Delay estimate: 451
N6.C1.D1.R0.S04: Offset Found: RdPtrOffsetDqs = 006
ACCM: 00 F0F00000 F0F0F000
ACCM: 0F 0F0F0F0F 0F0F0F0F
N4.C1.D1.R1.S02: Dq Delay estimate: 441
N6.C1.D1.R0.S05: Offset Found: RdPtrOffsetDqs = 006
N0.C1.D1.R0: CheckMCTest: result = 0x19C00
ACCM: 0F 0F0F0F0F 0F0F0F0F
N4.C1.D1.R1.S03: Dq Delay estimate: 427
N6.C1.D1.R0.S06: Offset Found: RdPtrOffsetDqs = 007
N0.C1.D1.R0.S00: Offset Found: RdPtrOffsetDqs = 007
ACCM: 0F 0F0F0F0F 0F0F0F0F
N4.C1.D1.R1.S04: Dq Delay estimate: 390
N6.C1.D1.R0.S07: Offset Found: RdPtrOffsetDqs = 007
N0.C1.D1.R0.S01: Offset Found: RdPtrOffsetDqs = 007
ACCM: 0F 0F0F0F0F 0F0F0F0F
N4.C1.D1.R1.S05: Dq Delay estimate: 406
N6.C1.D1.R0.S08: Offset Found: RdPtrOffsetDqs = 006
N0.C1.D1.R0.S02: Offset Found: RdPtrOffsetDqs = 007
N2.C3.D0.R1: CheckMCTest: result = 0x1FF
N4.C1.D1.R1.S06: Dq Delay estimate: 415
N6.C1.D1.R0: Write Training Coarse, upper nibbles
N0.C1.D1.R0.S03: Offset Found: RdPtrOffsetDqs = 007
ACCM: 0F 0F0F0F0F 0F0F0F0F
N4.C1.D1.R1.S07: Dq Delay estimate: 433
N6.C1.D1.R0.S09: Dq Delay estimate: 468
N0.C1.D1.R0.S04: Offset Found: RdPtrOffsetDqs = 006
ACCM: 0F 0F0F0F0F 0F0F0F0F
N4.C1.D1.R1.S08: Dq Delay estimate: 402
N6.C1.D1.R0.S10: Dq Delay estimate: 454
N0.C1.D1.R0.S05: Offset Found: RdPtrOffsetDqs = 006
ACCM: 00 00000000 0000000B
ACCM: 0F 0F0F0F0F 0F0F0F0F
N6.C1.D1.R0.S11: Dq Delay estimate: 448
N0.C1.D1.R0.S06: Offset Found: RdPtrOffsetDqs = 007
ACCM: 00 00000000 0000000B
ACCM: 0F 0F0F0F0F 0F0F0F0F
N6.C1.D1.R0.S12: Dq Delay estimate: 432
N0.C1.D1.R0.S07: Offset Found: RdPtrOffsetDqs = 007
N2.C3.D0.R1: CheckMCTest: result = 0x1FF
ACCM: 0F 0F0F0F0F 0F0F0F0F
N6.C1.D1.R0.S13: Dq Delay estimate: 398
N0.C1.D1.R0.S08: Offset Found: RdPtrOffsetDqs = 006
ACCM: 0F 0F0F0F0F 0F0F0F0F
ACCM: 0F 0F0F0F0F 0F0F0F0F
N6.C1.D1.R0.S14: Dq Delay estimate: 410
N0.C1.D1.R0: Write Training Coarse, upper nibbles
ACCM: 0F 0F0F0F0F 0F0F0F0F
N4.C1.D1.R1: CheckMCTest: result = 0x1FF
N6.C1.D1.R0.S15: Dq Delay estimate: 421
N0.C1.D1.R0.S09: Dq Delay estimate: 470
ACCM: 00 00000000 0000000F
ACCM: 0F 0F0F0F0F 0F0F0F0F
N6.C1.D1.R0.S16: Dq Delay estimate: 444
N0.C1.D1.R0.S10: Dq Delay estimate: 452
ACCM: 00 00000000 0000000F
ACCM: 0F 0F0F0F0F 0F0F0F0F
N6.C1.D1.R0.S17: Dq Delay estimate: 410
N0.C1.D1.R0.S11: Dq Delay estimate: 448
N2.C3.D0.R1: CheckMCTest: result = 0x1FF
ACCM: 0F 0F0F0F0F 0F0F0F0F
ACCM: F0 F0F0F0F0 F0F0F0F0
N0.C1.D1.R0.S12: Dq Delay estimate: 432
N2.C3.D0.R1: CheckMCTest: passed
ACCM: 0F 0F0F0F0F 0F0F0F0F
ACCM: F0 F0F0F0F0 F0F0F0F0
N0.C1.D1.R0.S13: Dq Delay estimate: 396
N2.C3.D0.R1: CheckMCTest: passed
N4.C1.D1.R1: CheckMCTest: result = 0x1FF
ACCM: F0 F0F0F0F0 F0F0F0F0
N0.C1.D1.R0.S14: Dq Delay estimate: 410
N2.C3.D0.R1.S00: Offset Found: RdPtrOffsetDqs = 007
ACCM: 0F 0F0F0F0F 0F0F0F0F
ACCM: F0 F0F0F0F0 F0F0F0F0
N0.C1.D1.R0.S15: Dq Delay estimate: 424
N2.C3.D0.R1.S01: Offset Found: RdPtrOffsetDqs = 007
ACCM: 0F 0F0F0F0F 0F0F0F0F
N6.C1.D1.R0: CheckMCTest: result = 0x3FE00
N0.C1.D1.R0.S16: Dq Delay estimate: 442
N2.C3.D0.R1.S02: Offset Found: RdPtrOffsetDqs = 007
ACCM: 00 00000B0B 0B00000B
ACCM: F0 F0F0F0F0 F0F0F0F0
N0.C1.D1.R0.S17: Dq Delay estimate: 411
N2.C3.D0.R1.S03: Offset Found: RdPtrOffsetDqs = 007
ACCM: 00 00000B0B 0B00000B
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: F0 F0F0F0F0 F0F0F0F0
N2.C3.D0.R1.S04: Offset Found: RdPtrOffsetDqs = 006
N4.C1.D1.R1: CheckMCTest: result = 0x1FF
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: F0 F0F0F0F0 F0F0F0F0
N2.C3.D0.R1.S05: Offset Found: RdPtrOffsetDqs = 006
ACCM: 0F 0F0F0F0F 0F0F0F0F
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: F0 F0F0F0F0 F0F0F0F0
N2.C3.D0.R1.S06: Offset Found: RdPtrOffsetDqs = 006
ACCM: 0F 0F0F0F0F 0F0F0F0F
N6.C1.D1.R0: CheckMCTest: result = 0x3FE00
ACCM: F0 F0F0F0F0 F0F0F0F0
N2.C3.D0.R1.S07: Offset Found: RdPtrOffsetDqs = 007
ACCM: 00 00000F0F 0F00000F
ACCM: F0 F0F0F0F0 F0F0F0F0
N0.C1.D1.R0: CheckMCTest: result = 0x3FE00
N2.C3.D0.R1.S08: Offset Found: RdPtrOffsetDqs = 006
ACCM: 00 00000F0F 0F00000F
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: F0 F0F0F0F0 F0F0F0F0
N2.C3.D0.R1: Write Training Coarse, upper nibbles
N4.C1.D1.R1: CheckMCTest: result = 0x1FF
ACCM: 00 B0B000B0 B00000B0
ACCM: F0 F0F0F0F0 F0F0F0F0
N2.C3.D0.R1.S09: Dq Delay estimate: 460
N4.C1.D1.R1: CheckMCTest: passed
ACCM: 00 B0B000B0 B00000B0
ACCM: F0 F0F0F0F0 F0F0F0F0
N2.C3.D0.R1.S10: Dq Delay estimate: 446
N4.C1.D1.R1: CheckMCTest: passed
N6.C1.D1.R0: CheckMCTest: result = 0x3FE00
ACCM: F0 F0F0F0F0 F0F0F0F0
N2.C3.D0.R1.S11: Dq Delay estimate: 437
N4.C1.D1.R1.S00: Offset Found: RdPtrOffsetDqs = 007
ACCM: F0 F0F0F0F0 F0F0F0F0
N0.C1.D1.R0: CheckMCTest: result = 0x3FE00
N2.C3.D0.R1.S12: Dq Delay estimate: 424
N4.C1.D1.R1.S01: Offset Found: RdPtrOffsetDqs = 007
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: F0 F0F0F0F0 F0F0F0F0
N2.C3.D0.R1.S13: Dq Delay estimate: 388
N4.C1.D1.R1.S02: Offset Found: RdPtrOffsetDqs = 007
ACCM: 00 F0F000F0 F00000F0
ACCM: F0 F0F0F0F0 F0F0F0F0
N2.C3.D0.R1.S14: Dq Delay estimate: 398
N4.C1.D1.R1.S03: Offset Found: RdPtrOffsetDqs = 007
ACCM: 00 F0F000F0 F00000F0
ACCM: B0 00B0B0B0 B0000000
N2.C3.D0.R1.S15: Dq Delay estimate: 413
N4.C1.D1.R1.S04: Offset Found: RdPtrOffsetDqs = 006
N6.C1.D1.R0: CheckMCTest: result = 0x3FE00
ACCM: B0 00B0B0B0 B0000000
N2.C3.D0.R1.S16: Dq Delay estimate: 429
N4.C1.D1.R1.S05: Offset Found: RdPtrOffsetDqs = 006
N6.C1.D1.R0: CheckMCTest: passed
N0.C1.D1.R0: CheckMCTest: result = 0x3FE00
N2.C3.D0.R1.S17: Dq Delay estimate: 405
N4.C1.D1.R1.S06: Offset Found: RdPtrOffsetDqs = 007
N6.C1.D1.R0: CheckMCTest: passed
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: F0 F0F0F0F0 F0F0F0F0
N4.C1.D1.R1.S07: Offset Found: RdPtrOffsetDqs = 007
N6.C1.D1.R0.S09: Offset Found: RdPtrOffsetDqs = 007
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: F0 F0F0F0F0 F0F0F0F0
N4.C1.D1.R1.S08: Offset Found: RdPtrOffsetDqs = 006
N6.C1.D1.R0.S10: Offset Found: RdPtrOffsetDqs = 007
ACCM: F0 00F0F0F0 F0000000
ACCM: F0 F0F0F0F0 F0F0F0F0
N4.C1.D1.R1: Write Training Coarse, upper nibbles
N6.C1.D1.R0.S11: Offset Found: RdPtrOffsetDqs = 007
ACCM: F0 00F0F0F0 F0000000
ACCM: F0 F0F0F0F0 F0F0F0F0
N4.C1.D1.R1.S09: Dq Delay estimate: 466
N6.C1.D1.R0.S12: Offset Found: RdPtrOffsetDqs = 007
N0.C1.D1.R0: CheckMCTest: result = 0x3FE00
N2.C3.D0.R1: CheckMCTest: result = 0x3FE00
N4.C1.D1.R1.S10: Dq Delay estimate: 451
N6.C1.D1.R0.S13: Offset Found: RdPtrOffsetDqs = 006
N0.C1.D1.R0: CheckMCTest: passed
ACCM: F0 F0F0F0F0 F0F0F0F0
N4.C1.D1.R1.S11: Dq Delay estimate: 443
N6.C1.D1.R0.S14: Offset Found: RdPtrOffsetDqs = 006
N0.C1.D1.R0: CheckMCTest: passed
ACCM: F0 F0F0F0F0 F0F0F0F0
N4.C1.D1.R1.S12: Dq Delay estimate: 427
N6.C1.D1.R0.S15: Offset Found: RdPtrOffsetDqs = 007
N0.C1.D1.R0.S09: Offset Found: RdPtrOffsetDqs = 007
ACCM: F0 F0F0F0F0 F0F0F0F0
N4.C1.D1.R1.S13: Dq Delay estimate: 391
N6.C1.D1.R0.S16: Offset Found: RdPtrOffsetDqs = 007
N0.C1.D1.R0.S10: Offset Found: RdPtrOffsetDqs = 007
ACCM: F0 F0F0F0F0 F0F0F0F0
N4.C1.D1.R1.S14: Dq Delay estimate: 407
N6.C1.D1.R0.S17: Offset Found: RdPtrOffsetDqs = 006
N0.C1.D1.R0.S11: Offset Found: RdPtrOffsetDqs = 007
N2.C3.D0.R1: CheckMCTest: result = 0x3FE00
N4.C1.D1.R1.S15: Dq Delay estimate: 416
N6.C1.D1.R1: Write Training Coarse, lower nibbles / bytes
N0.C1.D1.R0.S12: Offset Found: RdPtrOffsetDqs = 007
ACCM: F0 F0F0F0F0 F0F0F0F0
N4.C1.D1.R1.S16: Dq Delay estimate: 436
N6.C1.D1.R1.S00: Dq Delay estimate: 467
N0.C1.D1.R0.S13: Offset Found: RdPtrOffsetDqs = 006
ACCM: F0 F0F0F0F0 F0F0F0F0
N4.C1.D1.R1.S17: Dq Delay estimate: 401
N6.C1.D1.R1.S01: Dq Delay estimate: 448
N0.C1.D1.R0.S14: Offset Found: RdPtrOffsetDqs = 006
ACCM: B0 000000B0 0000B000
ACCM: F0 F0F0F0F0 F0F0F0F0
N6.C1.D1.R1.S02: Dq Delay estimate: 442
N0.C1.D1.R0.S15: Offset Found: RdPtrOffsetDqs = 007
ACCM: B0 000000B0 0000B000
ACCM: F0 F0F0F0F0 F0F0F0F0
N6.C1.D1.R1.S03: Dq Delay estimate: 425
N0.C1.D1.R0.S16: Offset Found: RdPtrOffsetDqs = 007
N2.C3.D0.R1: CheckMCTest: result = 0x3FE00
ACCM: F0 F0F0F0F0 F0F0F0F0
N6.C1.D1.R1.S04: Dq Delay estimate: 392
N0.C1.D1.R0.S17: Offset Found: RdPtrOffsetDqs = 006
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: F0 F0F0F0F0 F0F0F0F0
N6.C1.D1.R1.S05: Dq Delay estimate: 407
N0.C1.D1.R1: Write Training Coarse, lower nibbles / bytes
ACCM: F0 F0F0F0F0 F0F0F0F0
N4.C1.D1.R1: CheckMCTest: result = 0x3FE00
N6.C1.D1.R1.S06: Dq Delay estimate: 416
N0.C1.D1.R1.S00: Dq Delay estimate: 468
ACCM: F0 000000F0 0000F000
ACCM: F0 F0F0F0F0 F0F0F0F0
N6.C1.D1.R1.S07: Dq Delay estimate: 438
N0.C1.D1.R1.S01: Dq Delay estimate: 449
ACCM: F0 000000F0 0000F000
ACCM: F0 F0F0F0F0 F0F0F0F0
N6.C1.D1.R1.S08: Dq Delay estimate: 405
N0.C1.D1.R1.S02: Dq Delay estimate: 441
N2.C3.D0.R1: CheckMCTest: result = 0x3FE00
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: 0F 0F0F0F0F 0F0F0F0F
N0.C1.D1.R1.S03: Dq Delay estimate: 430
N2.C3.D0.R1: CheckMCTest: passed
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: 0F 0F0F0F0F 0F0F0F0F
N0.C1.D1.R1.S04: Dq Delay estimate: 395
N2.C3.D0.R1: CheckMCTest: passed
N4.C1.D1.R1: CheckMCTest: result = 0x3FE00
ACCM: 0F 0F0F0F0F 0F0F0F0F
N0.C1.D1.R1.S05: Dq Delay estimate: 408
N2.C3.D0.R1.S09: Offset Found: RdPtrOffsetDqs = 007
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: 0F 0F0F0F0F 0F0F0F0F
N0.C1.D1.R1.S06: Dq Delay estimate: 421
N2.C3.D0.R1.S10: Offset Found: RdPtrOffsetDqs = 007
ACCM: F0 F0F0F0F0 F0F0F0F0
N6.C1.D1.R1: CheckMCTest: result = 0x1FF
N0.C1.D1.R1.S07: Dq Delay estimate: 441
N2.C3.D0.R1.S11: Offset Found: RdPtrOffsetDqs = 007
ACCM: 00 00000000 00B00000
ACCM: 0F 0F0F0F0F 0F0F0F0F
N0.C1.D1.R1.S08: Dq Delay estimate: 407
N2.C3.D0.R1.S12: Offset Found: RdPtrOffsetDqs = 007
ACCM: 00 00000000 00B00000
ACCM: 0F 0F0F0F0F 0F0F0F0F
ACCM: 0F 0F0F0F0F 0F0F0F0F
N2.C3.D0.R1.S13: Offset Found: RdPtrOffsetDqs = 006
N4.C1.D1.R1: CheckMCTest: result = 0x3FE00
ACCM: 0F 0F0F0F0F 0F0F0F0F
ACCM: 0F 0F0F0F0F 0F0F0F0F
N2.C3.D0.R1.S14: Offset Found: RdPtrOffsetDqs = 006
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: 0F 0F0F0F0F 0F0F0F0F
ACCM: 0F 0F0F0F0F 0F0F0F0F
N2.C3.D0.R1.S15: Offset Found: RdPtrOffsetDqs = 007
ACCM: F0 F0F0F0F0 F0F0F0F0
N6.C1.D1.R1: CheckMCTest: result = 0x1FF
ACCM: 0F 0F0F0F0F 0F0F0F0F
N2.C3.D0.R1.S16: Offset Found: RdPtrOffsetDqs = 007
ACCM: 00 000000D0 C0F00000
ACCM: 0F 0F0F0F0F 0F0F0F0F
N0.C1.D1.R1: CheckMCTest: result = 0x1FF
N2.C3.D0.R1.S17: Offset Found: RdPtrOffsetDqs = 006
ACCM: 00 000000D0 C0F00000
ACCM: 0F 0F0F0F0F 0F0F0F0F
ACCM: 0F 0F0F0F0F 0F0F0F0F
N2.C3.D1.R0: Write Training Coarse, lower nibbles / bytes
N4.C1.D1.R1: CheckMCTest: result = 0x3FE00
ACCM: 00 00000000 0A0B0000
ACCM: 0F 0F0F0F0F 0F0F0F0F
N2.C3.D1.R0.S00: Dq Delay estimate: 470
N4.C1.D1.R1: CheckMCTest: passed
ACCM: 00 00000000 0A0B0000
ACCM: 0F 0F0F0F0F 0F0F0F0F
N2.C3.D1.R0.S01: Dq Delay estimate: 457
N4.C1.D1.R1: CheckMCTest: passed
N6.C1.D1.R1: CheckMCTest: result = 0x1FF
ACCM: 0F 0F0F0F0F 0F0F0F0F
N2.C3.D1.R0.S02: Dq Delay estimate: 447
N4.C1.D1.R1.S09: Offset Found: RdPtrOffsetDqs = 007
ACCM: 0F 0F0F0F0F 0F0F0F0F
N0.C1.D1.R1: CheckMCTest: result = 0x1FF
N2.C3.D1.R0.S03: Dq Delay estimate: 431
N4.C1.D1.R1.S10: Offset Found: RdPtrOffsetDqs = 007
ACCM: 0F 0F0F0F0F 0F0F0F0F
ACCM: 0F 0F0F0F0F 0F0F0F0F
N2.C3.D1.R0.S04: Dq Delay estimate: 394
N4.C1.D1.R1.S11: Offset Found: RdPtrOffsetDqs = 007
ACCM: 00 00000000 0E0B0000
ACCM: 0F 0F0F0F0F 0F0F0F0F
N2.C3.D1.R0.S05: Dq Delay estimate: 409
N4.C1.D1.R1.S12: Offset Found: RdPtrOffsetDqs = 007
ACCM: 00 00000000 0E0B0000
ACCM: 0B 0B0B000B 00000000
N2.C3.D1.R0.S06: Dq Delay estimate: 421
N4.C1.D1.R1.S13: Offset Found: RdPtrOffsetDqs = 006
N6.C1.D1.R1: CheckMCTest: result = 0x1FF
ACCM: 0B 0B0B000B 00000000
N2.C3.D1.R0.S07: Dq Delay estimate: 439
N4.C1.D1.R1.S14: Offset Found: RdPtrOffsetDqs = 006
N6.C1.D1.R1: CheckMCTest: passed
N0.C1.D1.R1: CheckMCTest: result = 0x1FF
N2.C3.D1.R0.S08: Dq Delay estimate: 413
N4.C1.D1.R1.S15: Offset Found: RdPtrOffsetDqs = 007
N6.C1.D1.R1: CheckMCTest: passed
ACCM: 0F 0F0F0F0F 0F0F0F0F
ACCM: 0F 0FFF0F0F 0F0F0F0F
N4.C1.D1.R1.S16: Offset Found: RdPtrOffsetDqs = 007
N6.C1.D1.R1.S00: Offset Found: RdPtrOffsetDqs = 007
ACCM: 0F 0F0F0F0F 0F0F0F0F
ACCM: 0F 0FFF0F0F 0F0F0F0F
N4.C1.D1.R1.S17: Offset Found: RdPtrOffsetDqs = 006
N6.C1.D1.R1.S01: Offset Found: RdPtrOffsetDqs = 007
ACCM: 0B 0F0F000F 00000000
ACCM: 0F 0FFF0F0F 0F0F0F0F
N4.C1: Calculating Optimimum DQS Values
N6.C1.D1.R1.S02: Offset Found: RdPtrOffsetDqs = 007
ACCM: 0B 0F0F000F 00000000
ACCM: 0F FFFF0F0F FFFFFF0F
N4.C1.D0.R0.S00: Total Delay in PI ticks: TxDQS = 1019, TxDQ = 982
N6.C1.D1.R1.S03: Offset Found: RdPtrOffsetDqs = 007
N0.C1.D1.R1: CheckMCTest: result = 0x1FF
N2.C3.D1.R0: CheckMCTest: result = 0x19DFF
N4.C1.D0.R0.S01: Total Delay in PI ticks: TxDQS = 1001, TxDQ = 964
N6.C1.D1.R1.S04: Offset Found: RdPtrOffsetDqs = 006
N0.C1.D1.R1: CheckMCTest: passed
ACCM: 0F 0FFF0F0F 0F0F0F0F
N4.C1.D0.R0.S02: Total Delay in PI ticks: TxDQS = 995, TxDQ = 958
N6.C1.D1.R1.S05: Offset Found: RdPtrOffsetDqs = 006
N0.C1.D1.R1: CheckMCTest: passed
ACCM: 0F 0FFF0F0F 0F0F0F0F
N4.C1.D0.R0.S03: Total Delay in PI ticks: TxDQS = 982, TxDQ = 945
N6.C1.D1.R1.S06: Offset Found: RdPtrOffsetDqs = 007
N0.C1.D1.R1.S00: Offset Found: RdPtrOffsetDqs = 007
ACCM: 0F 0FFF0F0F 0F0F0F0F
N4.C1.D0.R0.S04: Total Delay in PI ticks: TxDQS = 945, TxDQ = 907
N6.C1.D1.R1.S07: Offset Found: RdPtrOffsetDqs = 007
N0.C1.D1.R1.S01: Offset Found: RdPtrOffsetDqs = 007
ACCM: 0F FFFF0F0F FFFFFF0F
N4.C1.D0.R0.S05: Total Delay in PI ticks: TxDQS = 955, TxDQ = 918
N6.C1.D1.R1.S08: Offset Found: RdPtrOffsetDqs = 006
N0.C1.D1.R1.S02: Offset Found: RdPtrOffsetDqs = 007
N2.C3.D1.R0: CheckMCTest: result = 0x19DFF
N4.C1.D0.R0.S06: Total Delay in PI ticks: TxDQS = 975, TxDQ = 936
N6.C1.D1.R1: Write Training Coarse, upper nibbles
N0.C1.D1.R1.S03: Offset Found: RdPtrOffsetDqs = 007
ACCM: 0F 0FFF0F0F 0F0F0F0F
N4.C1.D0.R0.S07: Total Delay in PI ticks: TxDQS = 987, TxDQ = 948
N6.C1.D1.R1.S09: Dq Delay estimate: 463
N0.C1.D1.R1.S04: Offset Found: RdPtrOffsetDqs = 006
ACCM: 0F 0FFF0F0F 0F0F0F0F
N4.C1.D0.R0.S08: Total Delay in PI ticks: TxDQS = 960, TxDQ = 922
N6.C1.D1.R1.S10: Dq Delay estimate: 452
N0.C1.D1.R1.S05: Offset Found: RdPtrOffsetDqs = 006
ACCM: 00 0BFB000B 00000B0B
N4.C1.D0.R0.S09: Total Delay in PI ticks: TxDQS = 1021, TxDQ = 985
N6.C1.D1.R1.S11: Dq Delay estimate: 445
N0.C1.D1.R1.S06: Offset Found: RdPtrOffsetDqs = 007
ACCM: 00 FBFB000B F0F0FB0B
N4.C1.D0.R0.S10: Total Delay in PI ticks: TxDQS = 1003, TxDQ = 967
N6.C1.D1.R1.S12: Dq Delay estimate: 428
N0.C1.D1.R1.S07: Offset Found: RdPtrOffsetDqs = 007
N2.C3.D1.R0: CheckMCTest: result = 0x19DFF
N4.C1.D0.R0.S11: Total Delay in PI ticks: TxDQS = 997, TxDQ = 963
N6.C1.D1.R1.S13: Dq Delay estimate: 392
N0.C1.D1.R1.S08: Offset Found: RdPtrOffsetDqs = 006
ACCM: 0F 0FFF0F0F 0F0F0F0F
N4.C1.D0.R0.S12: Total Delay in PI ticks: TxDQS = 978, TxDQ = 942
N6.C1.D1.R1.S14: Dq Delay estimate: 407
N0.C1.D1.R1: Write Training Coarse, upper nibbles
ACCM: 0F 0FFF0F0F 0F0F0F0F
N4.C1.D0.R0.S13: Total Delay in PI ticks: TxDQS = 946, TxDQ = 909
N6.C1.D1.R1.S15: Dq Delay estimate: 416
N0.C1.D1.R1.S09: Dq Delay estimate: 467
ACCM: 00 0FFF000F 000D0F0F
N4.C1.D0.R0.S14: Total Delay in PI ticks: TxDQS = 959, TxDQ = 923
N6.C1.D1.R1.S16: Dq Delay estimate: 438
N0.C1.D1.R1.S10: Dq Delay estimate: 452
ACCM: 00 FFFF000F F0FDFF0F
N4.C1.D0.R0.S15: Total Delay in PI ticks: TxDQS = 971, TxDQ = 932
N6.C1.D1.R1.S17: Dq Delay estimate: 407
N0.C1.D1.R1.S11: Dq Delay estimate: 447
N2.C3.D1.R0: CheckMCTest: result = 0x19DFF
N4.C1.D0.R0.S16: Total Delay in PI ticks: TxDQS = 987, TxDQ = 950
ACCM: F0 F0F0F0F0 F0F0F0F0
N0.C1.D1.R1.S12: Dq Delay estimate: 430
ACCM: 00 00F00000 00000000
N4.C1.D0.R0.S17: Total Delay in PI ticks: TxDQS = 962, TxDQ = 924
ACCM: F0 F0F0F0F0 F0F0F0F0
N0.C1.D1.R1.S13: Dq Delay estimate: 396
ACCM: 00 00F00000 00000000
N4.C1.D0.R1.S00: Total Delay in PI ticks: TxDQS = 1011, TxDQ = 974
ACCM: F0 F0F0F0F0 F0F0F0F0
N0.C1.D1.R1.S14: Dq Delay estimate: 410
ACCM: 00 00F00000 00000000
N4.C1.D0.R1.S01: Total Delay in PI ticks: TxDQS = 997, TxDQ = 960
ACCM: F0 F0F0F0F0 F0F0F0F0
N0.C1.D1.R1.S15: Dq Delay estimate: 423
ACCM: 00 F0F00000 F0F0F000
N4.C1.D0.R1.S02: Total Delay in PI ticks: TxDQS = 987, TxDQ = 950
N6.C1.D1.R1: CheckMCTest: result = 0x3FE00
N0.C1.D1.R1.S16: Dq Delay estimate: 441
N2.C3.D1.R0: CheckMCTest: result = 0x19C00
N4.C1.D0.R1.S03: Total Delay in PI ticks: TxDQS = 973, TxDQ = 936
ACCM: F0 F0F0F0F0 F0F0F0F0
N0.C1.D1.R1.S17: Dq Delay estimate: 410
ACCM: 00 00F00000 00000000
N4.C1.D0.R1.S04: Total Delay in PI ticks: TxDQS = 938, TxDQ = 900
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: 00 00F00000 00000000
N4.C1.D0.R1.S05: Total Delay in PI ticks: TxDQS = 952, TxDQ = 916
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: 00 00F00000 00000000
N4.C1.D0.R1.S06: Total Delay in PI ticks: TxDQS = 963, TxDQ = 924
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: 00 F0F00000 F0F0F000
N4.C1.D0.R1.S07: Total Delay in PI ticks: TxDQS = 984, TxDQ = 945
N6.C1.D1.R1: CheckMCTest: result = 0x3FE00
ACCM: F0 F0F0F0F0 F0F0F0F0
N2.C3.D1.R0: CheckMCTest: result = 0x19C00
N4.C1.D0.R1.S08: Total Delay in PI ticks: TxDQS = 953, TxDQ = 915
ACCM: F0 F0F0F0F0 F0F0F0F0
N0.C1.D1.R1: CheckMCTest: result = 0x3FE00
N2.C3.D1.R0.S00: Offset Found: RdPtrOffsetDqs = 007
N4.C1.D0.R1.S09: Total Delay in PI ticks: TxDQS = 1010, TxDQ = 973
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: F0 F0F0F0F0 F0F0F0F0
N2.C3.D1.R0.S01: Offset Found: RdPtrOffsetDqs = 007
N4.C1.D0.R1.S10: Total Delay in PI ticks: TxDQS = 998, TxDQ = 963
ACCM: 00 000000B0 B000B000
ACCM: F0 F0F0F0F0 F0F0F0F0
N2.C3.D1.R0.S02: Offset Found: RdPtrOffsetDqs = 007
N4.C1.D0.R1.S11: Total Delay in PI ticks: TxDQS = 987, TxDQ = 952
ACCM: 00 000000B0 B000B000
ACCM: F0 F0F0F0F0 F0F0F0F0
N2.C3.D1.R0.S03: Offset Found: RdPtrOffsetDqs = 007
N4.C1.D0.R1.S12: Total Delay in PI ticks: TxDQS = 974, TxDQ = 938
N6.C1.D1.R1: CheckMCTest: result = 0x3FE00
ACCM: F0 F0F0F0F0 F0F0F0F0
N2.C3.D1.R0.S04: Offset Found: RdPtrOffsetDqs = 006
N4.C1.D0.R1.S13: Total Delay in PI ticks: TxDQS = 939, TxDQ = 902
ACCM: F0 F0F0F0F0 F0F0F0F0
N0.C1.D1.R1: CheckMCTest: result = 0x3FE00
N2.C3.D1.R0.S05: Offset Found: RdPtrOffsetDqs = 006
N4.C1.D0.R1.S14: Total Delay in PI ticks: TxDQS = 953, TxDQ = 920
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: F0 F0F0F0F0 F0F0F0F0
N2.C3.D1.R0.S06: Offset Found: RdPtrOffsetDqs = 007
N4.C1.D0.R1.S15: Total Delay in PI ticks: TxDQS = 968, TxDQ = 930
ACCM: 00 000000B0 F000F000
ACCM: F0 F0F0F0F0 F0F0F0F0
N2.C3.D1.R0.S07: Offset Found: RdPtrOffsetDqs = 007
N4.C1.D0.R1.S16: Total Delay in PI ticks: TxDQS = 983, TxDQ = 947
ACCM: 00 000000B0 F000F000
ACCM: 00 00B0B0B0 00000000
N2.C3.D1.R0.S08: Offset Found: RdPtrOffsetDqs = 007
N4.C1.D0.R1.S17: Total Delay in PI ticks: TxDQS = 953, TxDQ = 916
N6.C1.D1.R1: CheckMCTest: result = 0x3FE00
ACCM: 00 00B0B0B0 00000000
N2.C3.D1.R0: Write Training Coarse, upper nibbles
N4.C1.D1.R0.S00: Total Delay in PI ticks: TxDQS = 1021, TxDQ = 982
N6.C1.D1.R1: CheckMCTest: passed
N0.C1.D1.R1: CheckMCTest: result = 0x3FE00
N2.C3.D1.R0.S09: Dq Delay estimate: 470
N4.C1.D1.R0.S01: Total Delay in PI ticks: TxDQS = 1005, TxDQ = 966
N6.C1.D1.R1: CheckMCTest: passed
ACCM: F0 F0F0F0F0 F0F0F0F0
N2.C3.D1.R0.S10: Dq Delay estimate: 457
N4.C1.D1.R0.S02: Total Delay in PI ticks: TxDQS = 995, TxDQ = 955
N6.C1.D1.R1.S09: Offset Found: RdPtrOffsetDqs = 007
ACCM: F0 F0F0F0F0 F0F0F0F0
N2.C3.D1.R0.S11: Dq Delay estimate: 446
N4.C1.D1.R0.S03: Total Delay in PI ticks: TxDQS = 979, TxDQ = 939
N6.C1.D1.R1.S10: Offset Found: RdPtrOffsetDqs = 007
ACCM: 00 00F0F0F0 00000000
N2.C3.D1.R0.S12: Dq Delay estimate: 433
N4.C1.D1.R0.S04: Total Delay in PI ticks: TxDQS = 945, TxDQ = 904
N6.C1.D1.R1.S11: Offset Found: RdPtrOffsetDqs = 007
ACCM: 00 00F0F0F0 00000000
N2.C3.D1.R0.S13: Dq Delay estimate: 398
N4.C1.D1.R0.S05: Total Delay in PI ticks: TxDQS = 958, TxDQ = 919
N6.C1.D1.R1.S12: Offset Found: RdPtrOffsetDqs = 007
N0.C1.D1.R1: CheckMCTest: result = 0x3FE00
N2.C3.D1.R0.S14: Dq Delay estimate: 407
N4.C1.D1.R0.S06: Total Delay in PI ticks: TxDQS = 973, TxDQ = 933
N6.C1.D1.R1.S13: Offset Found: RdPtrOffsetDqs = 006
N0.C1.D1.R1: CheckMCTest: passed
N2.C3.D1.R0.S15: Dq Delay estimate: 422
N4.C1.D1.R0.S07: Total Delay in PI ticks: TxDQS = 988, TxDQ = 947
N6.C1.D1.R1.S14: Offset Found: RdPtrOffsetDqs = 006
N0.C1.D1.R1: CheckMCTest: passed
N2.C3.D1.R0.S16: Dq Delay estimate: 438
N4.C1.D1.R0.S08: Total Delay in PI ticks: TxDQS = 958, TxDQ = 919
N6.C1.D1.R1.S15: Offset Found: RdPtrOffsetDqs = 007
N0.C1.D1.R1.S09: Offset Found: RdPtrOffsetDqs = 007
N2.C3.D1.R0.S17: Dq Delay estimate: 413
N4.C1.D1.R0.S09: Total Delay in PI ticks: TxDQS = 1019, TxDQ = 981
N6.C1.D1.R1.S16: Offset Found: RdPtrOffsetDqs = 007
N0.C1.D1.R1.S10: Offset Found: RdPtrOffsetDqs = 007
ACCM: F0 F0F0F0F0 F0F0F0F0
N4.C1.D1.R0.S10: Total Delay in PI ticks: TxDQS = 1003, TxDQ = 965
N6.C1.D1.R1.S17: Offset Found: RdPtrOffsetDqs = 006
N0.C1.D1.R1.S11: Offset Found: RdPtrOffsetDqs = 007
ACCM: F0 F0F0F0F0 F0F0F0F0
N4.C1.D1.R0.S11: Total Delay in PI ticks: TxDQS = 994, TxDQ = 958
N6.C1: Calculating Optimimum DQS Values
N0.C1.D1.R1.S12: Offset Found: RdPtrOffsetDqs = 007
ACCM: F0 F0F0F0F0 F0F0F0F0
N4.C1.D1.R0.S12: Total Delay in PI ticks: TxDQS = 979, TxDQ = 940
N6.C1.D0.R0.S00: Total Delay in PI ticks: TxDQS = 1012, TxDQ = 981
N0.C1.D1.R1.S13: Offset Found: RdPtrOffsetDqs = 006
ACCM: F0 F0F0F0F0 F0F0F0F0
N4.C1.D1.R0.S13: Total Delay in PI ticks: TxDQS = 944, TxDQ = 904
N6.C1.D0.R0.S01: Total Delay in PI ticks: TxDQS = 997, TxDQ = 963
N0.C1.D1.R1.S14: Offset Found: RdPtrOffsetDqs = 006
N2.C3.D1.R0: CheckMCTest: result = 0x3FE00
N4.C1.D1.R0.S14: Total Delay in PI ticks: TxDQS = 958, TxDQ = 922
N6.C1.D0.R0.S02: Total Delay in PI ticks: TxDQS = 987, TxDQ = 954
N0.C1.D1.R1.S15: Offset Found: RdPtrOffsetDqs = 007
ACCM: F0 F0F0F0F0 F0F0F0F0
N4.C1.D1.R0.S15: Total Delay in PI ticks: TxDQS = 971, TxDQ = 931
N6.C1.D0.R0.S03: Total Delay in PI ticks: TxDQS = 971, TxDQ = 938
N0.C1.D1.R1.S16: Offset Found: RdPtrOffsetDqs = 007
ACCM: F0 F0F0F0F0 F0F0F0F0
N4.C1.D1.R0.S16: Total Delay in PI ticks: TxDQS = 992, TxDQ = 953
N6.C1.D0.R0.S04: Total Delay in PI ticks: TxDQS = 938, TxDQ = 904
N0.C1.D1.R1.S17: Offset Found: RdPtrOffsetDqs = 006
ACCM: F0 F0F0F0F0 F0F0F0F0
N4.C1.D1.R0.S17: Total Delay in PI ticks: TxDQS = 956, TxDQ = 916
N6.C1.D0.R0.S05: Total Delay in PI ticks: TxDQS = 953, TxDQ = 919
N0.C1: Calculating Optimimum DQS Values
ACCM: F0 F0F0F0F0 F0F0F0F0
N4.C1.D1.R1.S00: Total Delay in PI ticks: TxDQS = 1018, TxDQ = 979
N6.C1.D0.R0.S06: Total Delay in PI ticks: TxDQS = 968, TxDQ = 935
N0.C1.D0.R0.S00: Total Delay in PI ticks: TxDQS = 1018, TxDQ = 986
N2.C3.D1.R0: CheckMCTest: result = 0x3FE00
N4.C1.D1.R1.S01: Total Delay in PI ticks: TxDQS = 1002, TxDQ = 963
N6.C1.D0.R0.S07: Total Delay in PI ticks: TxDQS = 984, TxDQ = 950
N0.C1.D0.R0.S01: Total Delay in PI ticks: TxDQS = 999, TxDQ = 965
ACCM: F0 F0F0F0F0 F0F0F0F0
N4.C1.D1.R1.S02: Total Delay in PI ticks: TxDQS = 992, TxDQ = 953
N6.C1.D0.R0.S08: Total Delay in PI ticks: TxDQS = 955, TxDQ = 922
N0.C1.D0.R0.S02: Total Delay in PI ticks: TxDQS = 994, TxDQ = 960
ACCM: F0 F0F0F0F0 F0F0F0F0
N4.C1.D1.R1.S03: Total Delay in PI ticks: TxDQS = 978, TxDQ = 939
N6.C1.D0.R0.S09: Total Delay in PI ticks: TxDQS = 1013, TxDQ = 978
N0.C1.D0.R0.S03: Total Delay in PI ticks: TxDQS = 975, TxDQ = 942
ACCM: 00 B0B0B0B0 0000B0B0
N4.C1.D1.R1.S04: Total Delay in PI ticks: TxDQS = 943, TxDQ = 902
N6.C1.D0.R0.S10: Total Delay in PI ticks: TxDQS = 996, TxDQ = 963
N0.C1.D0.R0.S04: Total Delay in PI ticks: TxDQS = 940, TxDQ = 908
ACCM: 00 B0B0B0B0 0000B0B0
N4.C1.D1.R1.S05: Total Delay in PI ticks: TxDQS = 957, TxDQ = 918
N6.C1.D0.R0.S11: Total Delay in PI ticks: TxDQS = 989, TxDQ = 958
N0.C1.D0.R0.S05: Total Delay in PI ticks: TxDQS = 956, TxDQ = 922
N2.C3.D1.R0: CheckMCTest: result = 0x3FE00
N4.C1.D1.R1.S06: Total Delay in PI ticks: TxDQS = 968, TxDQ = 927
N6.C1.D0.R0.S12: Total Delay in PI ticks: TxDQS = 972, TxDQ = 939
N0.C1.D0.R0.S06: Total Delay in PI ticks: TxDQS = 973, TxDQ = 939
ACCM: F0 F0F0F0F0 F0F0F0F0
N4.C1.D1.R1.S07: Total Delay in PI ticks: TxDQS = 986, TxDQ = 945
N6.C1.D0.R0.S13: Total Delay in PI ticks: TxDQS = 937, TxDQ = 903
N0.C1.D0.R0.S07: Total Delay in PI ticks: TxDQS = 988, TxDQ = 955
ACCM: F0 F0F0F0F0 F0F0F0F0
N4.C1.D1.R1.S08: Total Delay in PI ticks: TxDQS = 954, TxDQ = 914
N6.C1.D0.R0.S14: Total Delay in PI ticks: TxDQS = 950, TxDQ = 916
N0.C1.D0.R0.S08: Total Delay in PI ticks: TxDQS = 955, TxDQ = 923
ACCM: 00 F0F0F0F0 0000F0F0
N4.C1.D1.R1.S09: Total Delay in PI ticks: TxDQS = 1016, TxDQ = 978
N6.C1.D0.R0.S15: Total Delay in PI ticks: TxDQS = 966, TxDQ = 934
N0.C1.D0.R0.S09: Total Delay in PI ticks: TxDQS = 1018, TxDQ = 985
ACCM: 00 F0F0F0F0 0000F0F0
N4.C1.D1.R1.S10: Total Delay in PI ticks: TxDQS = 1001, TxDQ = 963
N6.C1.D0.R0.S16: Total Delay in PI ticks: TxDQS = 982, TxDQ = 947
N0.C1.D0.R0.S10: Total Delay in PI ticks: TxDQS = 1000, TxDQ = 966
N2.C3.D1.R0: CheckMCTest: result = 0x3FE00
N4.C1.D1.R1.S11: Total Delay in PI ticks: TxDQS = 991, TxDQ = 955
N6.C1.D0.R0.S17: Total Delay in PI ticks: TxDQS = 954, TxDQ = 921
N0.C1.D0.R0.S11: Total Delay in PI ticks: TxDQS = 994, TxDQ = 962
N2.C3.D1.R0: CheckMCTest: passed
N4.C1.D1.R1.S12: Total Delay in PI ticks: TxDQS = 978, TxDQ = 939
N6.C1.D0.R1.S00: Total Delay in PI ticks: TxDQS = 1008, TxDQ = 975
N0.C1.D0.R0.S12: Total Delay in PI ticks: TxDQS = 975, TxDQ = 942
N2.C3.D1.R0: CheckMCTest: passed
N4.C1.D1.R1.S13: Total Delay in PI ticks: TxDQS = 943, TxDQ = 903
N6.C1.D0.R1.S01: Total Delay in PI ticks: TxDQS = 989, TxDQ = 954
N0.C1.D0.R0.S13: Total Delay in PI ticks: TxDQS = 941, TxDQ = 908
N2.C3.D1.R0.S09: Offset Found: RdPtrOffsetDqs = 007
N4.C1.D1.R1.S14: Total Delay in PI ticks: TxDQS = 956, TxDQ = 919
N6.C1.D0.R1.S02: Total Delay in PI ticks: TxDQS = 979, TxDQ = 947
N0.C1.D0.R0.S14: Total Delay in PI ticks: TxDQS = 955, TxDQ = 921
N2.C3.D1.R0.S10: Offset Found: RdPtrOffsetDqs = 007
N4.C1.D1.R1.S15: Total Delay in PI ticks: TxDQS = 968, TxDQ = 928
N6.C1.D0.R1.S03: Total Delay in PI ticks: TxDQS = 964, TxDQ = 931
N0.C1.D0.R0.S15: Total Delay in PI ticks: TxDQS = 970, TxDQ = 937
N2.C3.D1.R0.S11: Offset Found: RdPtrOffsetDqs = 007
N4.C1.D1.R1.S16: Total Delay in PI ticks: TxDQS = 986, TxDQ = 948
N6.C1.D0.R1.S04: Total Delay in PI ticks: TxDQS = 934, TxDQ = 900
N0.C1.D0.R0.S16: Total Delay in PI ticks: TxDQS = 988, TxDQ = 955
N2.C3.D1.R0.S12: Offset Found: RdPtrOffsetDqs = 007
N4.C1.D1.R1.S17: Total Delay in PI ticks: TxDQS = 953, TxDQ = 913
N6.C1.D0.R1.S05: Total Delay in PI ticks: TxDQS = 946, TxDQ = 912
N0.C1.D0.R0.S17: Total Delay in PI ticks: TxDQS = 958, TxDQ = 927
N2.C3.D1.R0.S13: Offset Found: RdPtrOffsetDqs = 006
N4.C2.D0.R0: Write Training Coarse, lower nibbles / bytes
N6.C1.D0.R1.S06: Total Delay in PI ticks: TxDQS = 959, TxDQ = 926
N0.C1.D0.R1.S00: Total Delay in PI ticks: TxDQS = 1009, TxDQ = 976
N2.C3.D1.R0.S14: Offset Found: RdPtrOffsetDqs = 006
N4.C2.D0.R0.S00: Dq Delay estimate: 463
N6.C1.D0.R1.S07: Total Delay in PI ticks: TxDQS = 977, TxDQ = 943
N0.C1.D0.R1.S01: Total Delay in PI ticks: TxDQS = 992, TxDQ = 958
N2.C3.D1.R0.S15: Offset Found: RdPtrOffsetDqs = 007
N4.C2.D0.R0.S01: Dq Delay estimate: 448
N6.C1.D0.R1.S08: Total Delay in PI ticks: TxDQS = 947, TxDQ = 914
N0.C1.D0.R1.S02: Total Delay in PI ticks: TxDQS = 985, TxDQ = 951
N2.C3.D1.R0.S16: Offset Found: RdPtrOffsetDqs = 007
N4.C2.D0.R0.S02: Dq Delay estimate: 439
N6.C1.D0.R1.S09: Total Delay in PI ticks: TxDQS = 1005, TxDQ = 970
N0.C1.D0.R1.S03: Total Delay in PI ticks: TxDQS = 969, TxDQ = 936
N2.C3.D1.R0.S17: Offset Found: RdPtrOffsetDqs = 007
N4.C2.D0.R0.S03: Dq Delay estimate: 422
N6.C1.D0.R1.S10: Total Delay in PI ticks: TxDQS = 989, TxDQ = 956
N0.C1.D0.R1.S04: Total Delay in PI ticks: TxDQS = 934, TxDQ = 902
N2.C3.D1.R1: Write Training Coarse, lower nibbles / bytes
N4.C2.D0.R0.S04: Dq Delay estimate: 378
N6.C1.D0.R1.S11: Total Delay in PI ticks: TxDQS = 981, TxDQ = 951
N0.C1.D0.R1.S05: Total Delay in PI ticks: TxDQS = 949, TxDQ = 916
N2.C3.D1.R1.S00: Dq Delay estimate: 467
N4.C2.D0.R0.S05: Dq Delay estimate: 407
N6.C1.D0.R1.S12: Total Delay in PI ticks: TxDQS = 965, TxDQ = 932
N0.C1.D0.R1.S06: Total Delay in PI ticks: TxDQS = 963, TxDQ = 929
N2.C3.D1.R1.S01: Dq Delay estimate: 452
N4.C2.D0.R0.S06: Dq Delay estimate: 408
N6.C1.D0.R1.S13: Total Delay in PI ticks: TxDQS = 931, TxDQ = 897
N0.C1.D0.R1.S07: Total Delay in PI ticks: TxDQS = 981, TxDQ = 948
N2.C3.D1.R1.S02: Dq Delay estimate: 441
N4.C2.D0.R0.S07: Dq Delay estimate: 427
N6.C1.D0.R1.S14: Total Delay in PI ticks: TxDQS = 944, TxDQ = 910
N0.C1.D0.R1.S08: Total Delay in PI ticks: TxDQS = 950, TxDQ = 918
N2.C3.D1.R1.S03: Dq Delay estimate: 428
N4.C2.D0.R0.S08: Dq Delay estimate: 400
N6.C1.D0.R1.S15: Total Delay in PI ticks: TxDQS = 959, TxDQ = 926
N0.C1.D0.R1.S09: Total Delay in PI ticks: TxDQS = 1008, TxDQ = 975
N2.C3.D1.R1.S04: Dq Delay estimate: 392
ACCM: 9F 0FFFDF9F 0F0F0F0F
N6.C1.D0.R1.S16: Total Delay in PI ticks: TxDQS = 978, TxDQ = 943
N0.C1.D0.R1.S10: Total Delay in PI ticks: TxDQS = 993, TxDQ = 959
N2.C3.D1.R1.S05: Dq Delay estimate: 405
ACCM: 9F 0FFFDF9F 0F0F0F0F
N6.C1.D0.R1.S17: Total Delay in PI ticks: TxDQS = 945, TxDQ = 912
N0.C1.D0.R1.S11: Total Delay in PI ticks: TxDQS = 985, TxDQ = 953
N2.C3.D1.R1.S06: Dq Delay estimate: 418
ACCM: 9F FFFFFF9F FFFFFFFF
N6.C1.D1.R0.S00: Total Delay in PI ticks: TxDQS = 1018, TxDQ = 983
N0.C1.D0.R1.S12: Total Delay in PI ticks: TxDQS = 970, TxDQ = 937
N2.C3.D1.R1.S07: Dq Delay estimate: 436
ACCM: 9F FFFFFF9F FFFFFFFF
N6.C1.D1.R0.S01: Total Delay in PI ticks: TxDQS = 1002, TxDQ = 966
N0.C1.D0.R1.S13: Total Delay in PI ticks: TxDQS = 936, TxDQ = 904
N2.C3.D1.R1.S08: Dq Delay estimate: 407
N4.C2.D0.R0: CheckMCTest: result = 0x3FFFF
N6.C1.D1.R0.S02: Total Delay in PI ticks: TxDQS = 992, TxDQ = 958
N0.C1.D0.R1.S14: Total Delay in PI ticks: TxDQS = 951, TxDQ = 917
ACCM: 0F 0F0F0F0F 0F0F0F0F
ACCM: DF 0FFFDFDF 0F0F0F0F
N6.C1.D1.R0.S03: Total Delay in PI ticks: TxDQS = 976, TxDQ = 941
N0.C1.D0.R1.S15: Total Delay in PI ticks: TxDQS = 962, TxDQ = 929
ACCM: 0F 0F0F0F0F 0F0F0F0F
ACCM: DF 0FFFDFDF 0F0F0F0F
N6.C1.D1.R0.S04: Total Delay in PI ticks: TxDQS = 944, TxDQ = 908
N0.C1.D0.R1.S16: Total Delay in PI ticks: TxDQS = 983, TxDQ = 952
ACCM: 0F 0F0F0F0F 0F0F0F0F
ACCM: DF FFFFFFDF FFFFFFFF
N6.C1.D1.R0.S05: Total Delay in PI ticks: TxDQS = 958, TxDQ = 922
N0.C1.D0.R1.S17: Total Delay in PI ticks: TxDQS = 949, TxDQ = 918
ACCM: 0F 0F0F0F0F 0F0F0F0F
ACCM: DF FFFFFFDF FFFFFFFF
N6.C1.D1.R0.S06: Total Delay in PI ticks: TxDQS = 970, TxDQ = 934
N0.C1.D1.R0.S00: Total Delay in PI ticks: TxDQS = 1017, TxDQ = 983
N2.C3.D1.R1: CheckMCTest: result = 0x1FF
N4.C2.D0.R0: CheckMCTest: result = 0x3FFFF
N6.C1.D1.R0.S07: Total Delay in PI ticks: TxDQS = 988, TxDQ = 953
N0.C1.D1.R0.S01: Total Delay in PI ticks: TxDQS = 1000, TxDQ = 965
ACCM: 0F 0F0F0F0F 0F0F0F0F
ACCM: DF 0FFFFFDF 0F0F0F0F
N6.C1.D1.R0.S08: Total Delay in PI ticks: TxDQS = 958, TxDQ = 923
N0.C1.D1.R0.S02: Total Delay in PI ticks: TxDQS = 993, TxDQ = 957
ACCM: 0F 0F0F0F0F 0F0F0F0F
ACCM: DF 0FFFFFDF 0F0F0F0F
N6.C1.D1.R0.S09: Total Delay in PI ticks: TxDQS = 1017, TxDQ = 980
N0.C1.D1.R0.S03: Total Delay in PI ticks: TxDQS = 979, TxDQ = 945
ACCM: 0F 0F0F0F0F 0F0F0F0F
ACCM: D0 FBFBFAD0 FBF0FBFB
N6.C1.D1.R0.S10: Total Delay in PI ticks: TxDQS = 1001, TxDQ = 966
N0.C1.D1.R0.S04: Total Delay in PI ticks: TxDQS = 945, TxDQ = 911
ACCM: 0F 0F0F0F0F 0F0F0F0F
ACCM: D0 FBFBFAD0 FBF0FBFB
N6.C1.D1.R0.S11: Total Delay in PI ticks: TxDQS = 993, TxDQ = 960
N0.C1.D1.R0.S05: Total Delay in PI ticks: TxDQS = 956, TxDQ = 921
N2.C3.D1.R1: CheckMCTest: result = 0x1FF
N4.C2.D0.R0: CheckMCTest: result = 0x3FFFF
N6.C1.D1.R0.S12: Total Delay in PI ticks: TxDQS = 978, TxDQ = 944
N0.C1.D1.R0.S06: Total Delay in PI ticks: TxDQS = 975, TxDQ = 940
ACCM: 0F 0F0F0F0F 0F0F0F0F
ACCM: DF 0FFFFFDF 0F0F0F0F
N6.C1.D1.R0.S13: Total Delay in PI ticks: TxDQS = 945, TxDQ = 910
N0.C1.D1.R0.S07: Total Delay in PI ticks: TxDQS = 990, TxDQ = 955
ACCM: 0F 0F0F0F0F 0F0F0F0F
ACCM: DF 0FFFFFDF 0F0F0F0F
N6.C1.D1.R0.S14: Total Delay in PI ticks: TxDQS = 958, TxDQ = 922
N0.C1.D1.R0.S08: Total Delay in PI ticks: TxDQS = 957, TxDQ = 923
ACCM: 00 000B000B 00000000
ACCM: D0 FFFFFFD0 FFF0FFFF
N6.C1.D1.R0.S15: Total Delay in PI ticks: TxDQS = 969, TxDQ = 933
N0.C1.D1.R0.S09: Total Delay in PI ticks: TxDQS = 1017, TxDQ = 982
ACCM: 00 000B000B 00000000
ACCM: D0 FFFFFFD0 FFF0FFFF
N6.C1.D1.R0.S16: Total Delay in PI ticks: TxDQS = 992, TxDQ = 956
N0.C1.D1.R0.S10: Total Delay in PI ticks: TxDQS = 1000, TxDQ = 964
N2.C3.D1.R1: CheckMCTest: result = 0x1FF
N4.C2.D0.R0: CheckMCTest: result = 0x3FFFF
N6.C1.D1.R0.S17: Total Delay in PI ticks: TxDQS = 957, TxDQ = 922
N0.C1.D1.R0.S11: Total Delay in PI ticks: TxDQS = 994, TxDQ = 960
ACCM: 0F 0F0F0F0F 0F0F0F0F
ACCM: D0 00F0D0D0 00000000
N6.C1.D1.R1.S00: Total Delay in PI ticks: TxDQS = 1014, TxDQ = 979
N0.C1.D1.R0.S12: Total Delay in PI ticks: TxDQS = 978, TxDQ = 944
ACCM: 0F 0F0F0F0F 0F0F0F0F
ACCM: D0 00F0D0D0 00000000
N6.C1.D1.R1.S01: Total Delay in PI ticks: TxDQS = 996, TxDQ = 960
N0.C1.D1.R0.S13: Total Delay in PI ticks: TxDQS = 943, TxDQ = 908
ACCM: 00 000B000F 00000000
ACCM: D0 F0F0F0D0 F0F0F0F0
N6.C1.D1.R1.S02: Total Delay in PI ticks: TxDQS = 988, TxDQ = 954
N0.C1.D1.R0.S14: Total Delay in PI ticks: TxDQS = 957, TxDQ = 922
ACCM: 00 000B000F 00000000
ACCM: D0 F0F0F0D0 F0F0F0F0
N6.C1.D1.R1.S03: Total Delay in PI ticks: TxDQS = 972, TxDQ = 937
N0.C1.D1.R0.S15: Total Delay in PI ticks: TxDQS = 970, TxDQ = 936
N2.C3.D1.R1: CheckMCTest: result = 0x1FF
N4.C2.D0.R0: CheckMCTest: result = 0x3FE00
N6.C1.D1.R1.S04: Total Delay in PI ticks: TxDQS = 939, TxDQ = 904
N0.C1.D1.R0.S16: Total Delay in PI ticks: TxDQS = 988, TxDQ = 954
N2.C3.D1.R1: CheckMCTest: passed
ACCM: D0 00F0D0D0 00000000
N6.C1.D1.R1.S05: Total Delay in PI ticks: TxDQS = 955, TxDQ = 919
N0.C1.D1.R0.S17: Total Delay in PI ticks: TxDQS = 956, TxDQ = 923
N2.C3.D1.R1: CheckMCTest: passed
ACCM: D0 00F0D0D0 00000000
N6.C1.D1.R1.S06: Total Delay in PI ticks: TxDQS = 964, TxDQ = 928
N0.C1.D1.R1.S00: Total Delay in PI ticks: TxDQS = 1014, TxDQ = 980
N2.C3.D1.R1.S00: Offset Found: RdPtrOffsetDqs = 007
ACCM: D0 F0F0F0D0 F0F0F0F0
N6.C1.D1.R1.S07: Total Delay in PI ticks: TxDQS = 986, TxDQ = 950
N0.C1.D1.R1.S01: Total Delay in PI ticks: TxDQS = 996, TxDQ = 961
N2.C3.D1.R1.S01: Offset Found: RdPtrOffsetDqs = 007
ACCM: D0 F0F0F0D0 F0F0F0F0
N6.C1.D1.R1.S08: Total Delay in PI ticks: TxDQS = 952, TxDQ = 917
N0.C1.D1.R1.S02: Total Delay in PI ticks: TxDQS = 988, TxDQ = 953
N2.C3.D1.R1.S02: Offset Found: RdPtrOffsetDqs = 007
N4.C2.D0.R0: CheckMCTest: result = 0x3FE00
N6.C1.D1.R1.S09: Total Delay in PI ticks: TxDQS = 1012, TxDQ = 975
N0.C1.D1.R1.S03: Total Delay in PI ticks: TxDQS = 976, TxDQ = 942
N2.C3.D1.R1.S03: Offset Found: RdPtrOffsetDqs = 007
N4.C2.D0.R0.S00: Offset Found: RdPtrOffsetDqs = 007
N6.C1.D1.R1.S10: Total Delay in PI ticks: TxDQS = 999, TxDQ = 964
N0.C1.D1.R1.S04: Total Delay in PI ticks: TxDQS = 941, TxDQ = 907
N2.C3.D1.R1.S04: Offset Found: RdPtrOffsetDqs = 006
N4.C2.D0.R0.S01: Offset Found: RdPtrOffsetDqs = 007
N6.C1.D1.R1.S11: Total Delay in PI ticks: TxDQS = 990, TxDQ = 957
N0.C1.D1.R1.S05: Total Delay in PI ticks: TxDQS = 955, TxDQ = 920
N2.C3.D1.R1.S05: Offset Found: RdPtrOffsetDqs = 006
N4.C2.D0.R0.S02: Offset Found: RdPtrOffsetDqs = 007
N6.C1.D1.R1.S12: Total Delay in PI ticks: TxDQS = 975, TxDQ = 940
N0.C1.D1.R1.S06: Total Delay in PI ticks: TxDQS = 968, TxDQ = 933
N2.C3.D1.R1.S06: Offset Found: RdPtrOffsetDqs = 007
N4.C2.D0.R0.S03: Offset Found: RdPtrOffsetDqs = 007
N6.C1.D1.R1.S13: Total Delay in PI ticks: TxDQS = 940, TxDQ = 904
N0.C1.D1.R1.S07: Total Delay in PI ticks: TxDQS = 987, TxDQ = 953
N2.C3.D1.R1.S07: Offset Found: RdPtrOffsetDqs = 007
N4.C2.D0.R0.S04: Offset Found: RdPtrOffsetDqs = 006
N6.C1.D1.R1.S14: Total Delay in PI ticks: TxDQS = 955, TxDQ = 919
N0.C1.D1.R1.S08: Total Delay in PI ticks: TxDQS = 953, TxDQ = 919
N2.C3.D1.R1.S08: Offset Found: RdPtrOffsetDqs = 006
N4.C2.D0.R0.S05: Offset Found: RdPtrOffsetDqs = 006
N6.C1.D1.R1.S15: Total Delay in PI ticks: TxDQS = 964, TxDQ = 928
N0.C1.D1.R1.S09: Total Delay in PI ticks: TxDQS = 1014, TxDQ = 979
N2.C3.D1.R1: Write Training Coarse, upper nibbles
N4.C2.D0.R0.S06: Offset Found: RdPtrOffsetDqs = 006
N6.C1.D1.R1.S16: Total Delay in PI ticks: TxDQS = 986, TxDQ = 950
N0.C1.D1.R1.S10: Total Delay in PI ticks: TxDQS = 1000, TxDQ = 964
N2.C3.D1.R1.S09: Dq Delay estimate: 468
N4.C2.D0.R0.S07: Offset Found: RdPtrOffsetDqs = 007
N6.C1.D1.R1.S17: Total Delay in PI ticks: TxDQS = 953, TxDQ = 919
N0.C1.D1.R1.S11: Total Delay in PI ticks: TxDQS = 992, TxDQ = 959
N2.C3.D1.R1.S10: Dq Delay estimate: 451
N4.C2.D0.R0.S08: Offset Found: RdPtrOffsetDqs = 006
N6.C2.D0.R0: Write Training Coarse, lower nibbles / bytes
N0.C1.D1.R1.S12: Total Delay in PI ticks: TxDQS = 976, TxDQ = 942
N2.C3.D1.R1.S11: Dq Delay estimate: 444
N4.C2.D0.R0: Write Training Coarse, upper nibbles
N6.C2.D0.R0.S00: Dq Delay estimate: 463
N0.C1.D1.R1.S13: Total Delay in PI ticks: TxDQS = 942, TxDQ = 908
N2.C3.D1.R1.S12: Dq Delay estimate: 428
N4.C2.D0.R0.S09: Dq Delay estimate: 466
N6.C2.D0.R0.S01: Dq Delay estimate: 447
N0.C1.D1.R1.S14: Total Delay in PI ticks: TxDQS = 956, TxDQ = 922
N2.C3.D1.R1.S13: Dq Delay estimate: 391
N4.C2.D0.R0.S10: Dq Delay estimate: 449
N6.C2.D0.R0.S02: Dq Delay estimate: 440
N0.C1.D1.R1.S15: Total Delay in PI ticks: TxDQS = 969, TxDQ = 935
N2.C3.D1.R1.S14: Dq Delay estimate: 403
N4.C2.D0.R0.S11: Dq Delay estimate: 442
N6.C2.D0.R0.S03: Dq Delay estimate: 418
N0.C1.D1.R1.S16: Total Delay in PI ticks: TxDQS = 987, TxDQ = 953
N2.C3.D1.R1.S15: Dq Delay estimate: 418
N4.C2.D0.R0.S12: Dq Delay estimate: 422
N6.C2.D0.R0.S04: Dq Delay estimate: 383
N0.C1.D1.R1.S17: Total Delay in PI ticks: TxDQS = 955, TxDQ = 922
N2.C3.D1.R1.S16: Dq Delay estimate: 435
N4.C2.D0.R0.S13: Dq Delay estimate: 385
N6.C2.D0.R0.S05: Dq Delay estimate: 406
N0.C2.D0.R0: Write Training Coarse, lower nibbles / bytes
N2.C3.D1.R1.S17: Dq Delay estimate: 408
N4.C2.D0.R0.S14: Dq Delay estimate: 408
N6.C2.D0.R0.S06: Dq Delay estimate: 407
N0.C2.D0.R0.S00: Dq Delay estimate: 468
ACCM: F0 F0F0F0F0 F0F0F0F0
N4.C2.D0.R0.S15: Dq Delay estimate: 409
N6.C2.D0.R0.S07: Dq Delay estimate: 427
N0.C2.D0.R0.S01: Dq Delay estimate: 451
ACCM: F0 F0F0F0F0 F0F0F0F0
N4.C2.D0.R0.S16: Dq Delay estimate: 429
N6.C2.D0.R0.S08: Dq Delay estimate: 396
N0.C2.D0.R0.S02: Dq Delay estimate: 441
ACCM: F0 F0F0F0F0 F0F0F0F0
N4.C2.D0.R0.S17: Dq Delay estimate: 398
ACCM: 0F 0F9F9F0F 0F0F0F0F
N0.C2.D0.R0.S03: Dq Delay estimate: 424
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: 0F 0F9F9F0F 0F0F0F0F
N0.C2.D0.R0.S04: Dq Delay estimate: 387
N2.C3.D1.R1: CheckMCTest: result = 0x3FE00
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: 0F FF9F9F0F FFFFFFFF
N0.C2.D0.R0.S05: Dq Delay estimate: 413
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: 0F FF9F9F0F FFFFFFFF
N0.C2.D0.R0.S06: Dq Delay estimate: 412
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: F0 F0F0F0F0 F0F0F0F0
N6.C2.D0.R0: CheckMCTest: result = 0x1DFFF
N0.C2.D0.R0.S07: Dq Delay estimate: 432
ACCM: F0 F0F0F0F0 F0F0F0F0
N4.C2.D0.R0: CheckMCTest: result = 0x3FE00
ACCM: 0F 0FDFDF0F 0F0F0F0F
N0.C2.D0.R0.S08: Dq Delay estimate: 407
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: 0F 0FDFDF0F 0F0F0F0F
ACCM: 9F 0F0FDF9F 0F0F0F0F
N2.C3.D1.R1: CheckMCTest: result = 0x3FE00
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: 0F FFDFDF0F FFFFFFFF
ACCM: 9F 0F0FDF9F 0F0F0F0F
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: 0F FFDFDF0F FFFFFFFF
ACCM: 9F FFFFFF9F FFFFFFFF
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: F0 F0F0F0F0 F0F0F0F0
N6.C2.D0.R0: CheckMCTest: result = 0x1DFFF
ACCM: 9F FFFFFF9F FFFFFFFF
ACCM: 00 000000B0 0000B000
N4.C2.D0.R0: CheckMCTest: result = 0x3FE00
ACCM: 0F 0FDFDF0F 0F0F0F0F
N0.C2.D0.R0: CheckMCTest: result = 0x3FFFF
ACCM: 00 000000B0 0000B000
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: 0F 0FDFDF0F 0F0F0F0F
ACCM: DF 0F0FDFDF 0F0F0F0F
N2.C3.D1.R1: CheckMCTest: result = 0x3FE00
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: 0B FBDBDB0B F0F0F0F0
ACCM: DF 0F0FDFDF 0F0F0F0F
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: 00 B0B000B0 B0B0B0B0
ACCM: 0B FBDBDB0B F0F0F0F0
ACCM: DF FFFFFFDF FFFFFFFF
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: 00 B0B000B0 B0B0B0B0
N6.C2.D0.R0: CheckMCTest: result = 0x1DFFF
ACCM: DF FFFFFFDF FFFFFFFF
ACCM: 00 0000D0F0 00D0F000
N4.C2.D0.R0: CheckMCTest: result = 0x3FE00
ACCM: 0F 0FDFDF0F 0F0F0F0F
N0.C2.D0.R0: CheckMCTest: result = 0x3FFFF
ACCM: 00 0000D0F0 00D0F000
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: 0F 0FDFDF0F 0F0F0F0F
ACCM: DF 0F0F0FDF 0F0F0F0F
N2.C3.D1.R1: CheckMCTest: result = 0x3FE00
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: 0B FFDFDF0F F0FDF0F0
ACCM: DF 0F0F0FDF 0F0F0F0F
N2.C3.D1.R1: CheckMCTest: passed
ACCM: 00 F0B000F0 F0F0F0F0
ACCM: 0B FFDFDF0F F0FDF0F0
ACCM: DB FBFBFBDB FBF0FBFB
N2.C3.D1.R1: CheckMCTest: passed
ACCM: 00 F0B000F0 F0F0F0F0
N6.C2.D0.R0: CheckMCTest: result = 0x1DFFF
ACCM: DB FBFBFBDB FBF0FBFB
N2.C3.D1.R1.S09: Offset Found: RdPtrOffsetDqs = 007
N4.C2.D0.R0: CheckMCTest: result = 0x3FE00
ACCM: 00 00D0D000 00000000
N0.C2.D0.R0: CheckMCTest: result = 0x3FFFF
N2.C3.D1.R1.S10: Offset Found: RdPtrOffsetDqs = 007
N4.C2.D0.R0: CheckMCTest: passed
ACCM: 00 00D0D000 00000000
ACCM: DF 0F0F0FDF 0F0F0F0F
N2.C3.D1.R1.S11: Offset Found: RdPtrOffsetDqs = 007
N4.C2.D0.R0: CheckMCTest: passed
ACCM: 00 F0D0D000 F0F0F0F0
ACCM: DF 0F0F0FDF 0F0F0F0F
N2.C3.D1.R1.S12: Offset Found: RdPtrOffsetDqs = 007
N4.C2.D0.R0.S09: Offset Found: RdPtrOffsetDqs = 007
ACCM: 00 F0D0D000 F0F0F0F0
ACCM: DB FFFFFFDF FFF0FFFF
N2.C3.D1.R1.S13: Offset Found: RdPtrOffsetDqs = 006
N4.C2.D0.R0.S10: Offset Found: RdPtrOffsetDqs = 007
N6.C2.D0.R0: CheckMCTest: result = 0x1DE00
ACCM: DB FFFFFFDF FFF0FFFF
N2.C3.D1.R1.S14: Offset Found: RdPtrOffsetDqs = 006
N4.C2.D0.R0.S11: Offset Found: RdPtrOffsetDqs = 007
ACCM: 00 00D0D000 00000000
N0.C2.D0.R0: CheckMCTest: result = 0x3FFFF
N2.C3.D1.R1.S15: Offset Found: RdPtrOffsetDqs = 007
N4.C2.D0.R0.S12: Offset Found: RdPtrOffsetDqs = 007
ACCM: 00 00D0D000 00000000
ACCM: D0 000000D0 00000000
N2.C3.D1.R1.S16: Offset Found: RdPtrOffsetDqs = 007
N4.C2.D0.R0.S13: Offset Found: RdPtrOffsetDqs = 006
ACCM: 00 F0D0D000 F0F0F0F0
ACCM: D0 000000D0 00000000
N2.C3.D1.R1.S17: Offset Found: RdPtrOffsetDqs = 006
N4.C2.D0.R0.S14: Offset Found: RdPtrOffsetDqs = 006
ACCM: 00 F0D0D000 F0F0F0F0
ACCM: D0 F0F0F0D0 F0F0F0F0
N2.C3: Calculating Optimimum DQS Values
N4.C2.D0.R0.S15: Offset Found: RdPtrOffsetDqs = 006
N6.C2.D0.R0: CheckMCTest: result = 0x1DE00
ACCM: D0 F0F0F0D0 F0F0F0F0
N2.C3.D0.R0.S00: Total Delay in PI ticks: TxDQS = 1015, TxDQ = 979
N4.C2.D0.R0.S16: Offset Found: RdPtrOffsetDqs = 007
N6.C2.D0.R0.S00: Offset Found: RdPtrOffsetDqs = 007
N0.C2.D0.R0: CheckMCTest: result = 0x3FE00
N2.C3.D0.R0.S01: Total Delay in PI ticks: TxDQS = 999, TxDQ = 966
N4.C2.D0.R0.S17: Offset Found: RdPtrOffsetDqs = 006
N6.C2.D0.R0.S01: Offset Found: RdPtrOffsetDqs = 007
ACCM: D0 000000D0 00000000
N2.C3.D0.R0.S02: Total Delay in PI ticks: TxDQS = 991, TxDQ = 955
N4.C2.D0.R1: Write Training Coarse, lower nibbles / bytes
N6.C2.D0.R0.S02: Offset Found: RdPtrOffsetDqs = 007
ACCM: D0 000000D0 00000000
N2.C3.D0.R0.S03: Total Delay in PI ticks: TxDQS = 972, TxDQ = 938
N4.C2.D0.R1.S00: Dq Delay estimate: 456
N6.C2.D0.R0.S03: Offset Found: RdPtrOffsetDqs = 007
ACCM: D0 F0F0F0D0 F0F0F0F0
N2.C3.D0.R0.S04: Total Delay in PI ticks: TxDQS = 939, TxDQ = 905
N4.C2.D0.R1.S01: Dq Delay estimate: 441
N6.C2.D0.R0.S04: Offset Found: RdPtrOffsetDqs = 006
ACCM: D0 F0F0F0D0 F0F0F0F0
N2.C3.D0.R0.S05: Total Delay in PI ticks: TxDQS = 951, TxDQ = 916
N4.C2.D0.R1.S02: Dq Delay estimate: 431
N6.C2.D0.R0.S05: Offset Found: RdPtrOffsetDqs = 006
N0.C2.D0.R0: CheckMCTest: result = 0x3FE00
N2.C3.D0.R0.S06: Total Delay in PI ticks: TxDQS = 967, TxDQ = 931
N4.C2.D0.R1.S03: Dq Delay estimate: 416
N6.C2.D0.R0.S06: Offset Found: RdPtrOffsetDqs = 006
N0.C2.D0.R0.S00: Offset Found: RdPtrOffsetDqs = 007
N2.C3.D0.R0.S07: Total Delay in PI ticks: TxDQS = 983, TxDQ = 948
N4.C2.D0.R1.S04: Dq Delay estimate: 372
N6.C2.D0.R0.S07: Offset Found: RdPtrOffsetDqs = 007
N0.C2.D0.R0.S01: Offset Found: RdPtrOffsetDqs = 007
N2.C3.D0.R0.S08: Total Delay in PI ticks: TxDQS = 957, TxDQ = 924
N4.C2.D0.R1.S05: Dq Delay estimate: 401
N6.C2.D0.R0.S08: Offset Found: RdPtrOffsetDqs = 006
N0.C2.D0.R0.S02: Offset Found: RdPtrOffsetDqs = 007
N2.C3.D0.R0.S09: Total Delay in PI ticks: TxDQS = 1016, TxDQ = 980
N4.C2.D0.R1.S06: Dq Delay estimate: 397
N6.C2.D0.R0: Write Training Coarse, upper nibbles
N0.C2.D0.R0.S03: Offset Found: RdPtrOffsetDqs = 007
N2.C3.D0.R0.S10: Total Delay in PI ticks: TxDQS = 1000, TxDQ = 967
N4.C2.D0.R1.S07: Dq Delay estimate: 422
N6.C2.D0.R0.S09: Dq Delay estimate: 463
N0.C2.D0.R0.S04: Offset Found: RdPtrOffsetDqs = 006
N2.C3.D0.R0.S11: Total Delay in PI ticks: TxDQS = 991, TxDQ = 956
N4.C2.D0.R1.S08: Dq Delay estimate: 392
N6.C2.D0.R0.S10: Dq Delay estimate: 449
N0.C2.D0.R0.S05: Offset Found: RdPtrOffsetDqs = 007
N2.C3.D0.R0.S12: Total Delay in PI ticks: TxDQS = 974, TxDQ = 940
ACCM: 0F 0F0F0F0F 0F0F0F0F
N6.C2.D0.R0.S11: Dq Delay estimate: 441
N0.C2.D0.R0.S06: Offset Found: RdPtrOffsetDqs = 006
N2.C3.D0.R0.S13: Total Delay in PI ticks: TxDQS = 938, TxDQ = 905
ACCM: 0F 0F0F0F0F 0F0F0F0F
N6.C2.D0.R0.S12: Dq Delay estimate: 419
N0.C2.D0.R0.S07: Offset Found: RdPtrOffsetDqs = 007
N2.C3.D0.R0.S14: Total Delay in PI ticks: TxDQS = 952, TxDQ = 917
ACCM: 0F 0F0F0F0F 0F0F0F0F
N6.C2.D0.R0.S13: Dq Delay estimate: 380
N0.C2.D0.R0.S08: Offset Found: RdPtrOffsetDqs = 006
N2.C3.D0.R0.S15: Total Delay in PI ticks: TxDQS = 966, TxDQ = 932
ACCM: 0F 0F0F0F0F 0F0F0F0F
N6.C2.D0.R0.S14: Dq Delay estimate: 406
N0.C2.D0.R0: Write Training Coarse, upper nibbles
N2.C3.D0.R0.S16: Total Delay in PI ticks: TxDQS = 980, TxDQ = 944
N4.C2.D0.R1: CheckMCTest: result = 0x1FF
N6.C2.D0.R0.S15: Dq Delay estimate: 408
N0.C2.D0.R0.S09: Dq Delay estimate: 472
N2.C3.D0.R0.S17: Total Delay in PI ticks: TxDQS = 957, TxDQ = 926
ACCM: 0F 0F0F0F0F 0F0F0F0F
N6.C2.D0.R0.S16: Dq Delay estimate: 428
N0.C2.D0.R0.S10: Dq Delay estimate: 456
N2.C3.D0.R1.S00: Total Delay in PI ticks: TxDQS = 1010, TxDQ = 974
ACCM: 0F 0F0F0F0F 0F0F0F0F
N6.C2.D0.R0.S17: Dq Delay estimate: 401
N0.C2.D0.R0.S11: Dq Delay estimate: 445
N2.C3.D0.R1.S01: Total Delay in PI ticks: TxDQS = 990, TxDQ = 957
ACCM: 0F 0F0F0F0F 0F0F0F0F
ACCM: F0 F0F0F0F0 F0F0F0F0
N0.C2.D0.R0.S12: Dq Delay estimate: 425
N2.C3.D0.R1.S02: Total Delay in PI ticks: TxDQS = 982, TxDQ = 946
ACCM: 0F 0F0F0F0F 0F0F0F0F
ACCM: F0 F0F0F0F0 F0F0F0F0
N0.C2.D0.R0.S13: Dq Delay estimate: 384
N2.C3.D0.R1.S03: Total Delay in PI ticks: TxDQS = 967, TxDQ = 934
N4.C2.D0.R1: CheckMCTest: result = 0x1FF
ACCM: F0 F0F0F0F0 F0F0F0F0
N0.C2.D0.R0.S14: Dq Delay estimate: 412
N2.C3.D0.R1.S04: Total Delay in PI ticks: TxDQS = 932, TxDQ = 898
ACCM: 0F 0F0F0F0F 0F0F0F0F
ACCM: F0 F0F0F0F0 F0F0F0F0
N0.C2.D0.R0.S15: Dq Delay estimate: 414
N2.C3.D0.R1.S05: Total Delay in PI ticks: TxDQS = 945, TxDQ = 910
ACCM: 0F 0F0F0F0F 0F0F0F0F
N6.C2.D0.R0: CheckMCTest: result = 0x3FE00
N0.C2.D0.R0.S16: Dq Delay estimate: 434
N2.C3.D0.R1.S06: Total Delay in PI ticks: TxDQS = 959, TxDQ = 923
ACCM: 00 0B0B0B00 00000000
ACCM: F0 F0F0F0F0 F0F0F0F0
N0.C2.D0.R0.S17: Dq Delay estimate: 404
N2.C3.D0.R1.S07: Total Delay in PI ticks: TxDQS = 976, TxDQ = 941
ACCM: 00 0B0B0B00 00000000
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: F0 F0F0F0F0 F0F0F0F0
N2.C3.D0.R1.S08: Total Delay in PI ticks: TxDQS = 950, TxDQ = 917
N4.C2.D0.R1: CheckMCTest: result = 0x1FF
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: F0 F0F0F0F0 F0F0F0F0
N2.C3.D0.R1.S09: Total Delay in PI ticks: TxDQS = 1007, TxDQ = 972
ACCM: 0F 0F0F0F0F 0F0F0F0F
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: F0 F0F0F0F0 F0F0F0F0
N2.C3.D0.R1.S10: Total Delay in PI ticks: TxDQS = 991, TxDQ = 958
ACCM: 0F 0F0F0F0F 0F0F0F0F
N6.C2.D0.R0: CheckMCTest: result = 0x3FE00
ACCM: F0 F0F0F0F0 F0F0F0F0
N2.C3.D0.R1.S11: Total Delay in PI ticks: TxDQS = 984, TxDQ = 949
ACCM: 00 0F0F0F00 00000000
ACCM: F0 F0F0F0F0 F0F0F0F0
N0.C2.D0.R0: CheckMCTest: result = 0x3FE00
N2.C3.D0.R1.S12: Total Delay in PI ticks: TxDQS = 969, TxDQ = 936
ACCM: 00 0F0F0F00 00000000
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: F0 F0F0F0F0 F0F0F0F0
N2.C3.D0.R1.S13: Total Delay in PI ticks: TxDQS = 933, TxDQ = 900
N4.C2.D0.R1: CheckMCTest: result = 0x1FF
ACCM: 00 B0B00000 00B00000
ACCM: F0 F0F0F0F0 F0F0F0F0
N2.C3.D0.R1.S14: Total Delay in PI ticks: TxDQS = 945, TxDQ = 910
N4.C2.D0.R1: CheckMCTest: passed
ACCM: 00 B0B00000 00B00000
ACCM: F0 F0F0F0F0 F0F0F0F0
N2.C3.D0.R1.S15: Total Delay in PI ticks: TxDQS = 960, TxDQ = 925
N4.C2.D0.R1: CheckMCTest: passed
N6.C2.D0.R0: CheckMCTest: result = 0x3FE00
ACCM: F0 F0F0F0F0 F0F0F0F0
N2.C3.D0.R1.S16: Total Delay in PI ticks: TxDQS = 977, TxDQ = 941
N4.C2.D0.R1.S00: Offset Found: RdPtrOffsetDqs = 007
ACCM: F0 F0F0F0F0 F0F0F0F0
N0.C2.D0.R0: CheckMCTest: result = 0x3FE00
N2.C3.D0.R1.S17: Total Delay in PI ticks: TxDQS = 949, TxDQ = 917
N4.C2.D0.R1.S01: Offset Found: RdPtrOffsetDqs = 007
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: F0 F0F0F0F0 F0F0F0F0
N2.C3.D1.R0.S00: Total Delay in PI ticks: TxDQS = 1020, TxDQ = 982
N4.C2.D0.R1.S02: Offset Found: RdPtrOffsetDqs = 007
ACCM: 00 F0F00000 00F00000
ACCM: F0 F0F0F0F0 F0F0F0F0
N2.C3.D1.R0.S01: Total Delay in PI ticks: TxDQS = 1004, TxDQ = 969
N4.C2.D0.R1.S03: Offset Found: RdPtrOffsetDqs = 007
ACCM: 00 F0F00000 00F00000
ACCM: 00 B00000B0 B000B0B0
N2.C3.D1.R0.S02: Total Delay in PI ticks: TxDQS = 996, TxDQ = 959
N4.C2.D0.R1.S04: Offset Found: RdPtrOffsetDqs = 006
N6.C2.D0.R0: CheckMCTest: result = 0x3FE00
ACCM: 00 B00000B0 B000B0B0
N2.C3.D1.R0.S03: Total Delay in PI ticks: TxDQS = 978, TxDQ = 943
N4.C2.D0.R1.S05: Offset Found: RdPtrOffsetDqs = 006
N6.C2.D0.R0: CheckMCTest: passed
N0.C2.D0.R0: CheckMCTest: result = 0x3FE00
N2.C3.D1.R0.S04: Total Delay in PI ticks: TxDQS = 943, TxDQ = 906
N4.C2.D0.R1.S06: Offset Found: RdPtrOffsetDqs = 006
N6.C2.D0.R0: CheckMCTest: passed
ACCM: F0 F0F0F0F0 F0F0F0F0
N2.C3.D1.R0.S05: Total Delay in PI ticks: TxDQS = 957, TxDQ = 921
N4.C2.D0.R1.S07: Offset Found: RdPtrOffsetDqs = 007
N6.C2.D0.R0.S09: Offset Found: RdPtrOffsetDqs = 007
ACCM: F0 F0F0F0F0 F0F0F0F0
N2.C3.D1.R0.S06: Total Delay in PI ticks: TxDQS = 970, TxDQ = 933
N4.C2.D0.R1.S08: Offset Found: RdPtrOffsetDqs = 006
N6.C2.D0.R0.S10: Offset Found: RdPtrOffsetDqs = 007
ACCM: 00 F00000F0 F000F0F0
N2.C3.D1.R0.S07: Total Delay in PI ticks: TxDQS = 988, TxDQ = 951
N4.C2.D0.R1: Write Training Coarse, upper nibbles
N6.C2.D0.R0.S11: Offset Found: RdPtrOffsetDqs = 007
ACCM: 00 F00000F0 F000F0F0
N2.C3.D1.R0.S08: Total Delay in PI ticks: TxDQS = 961, TxDQ = 925
N4.C2.D0.R1.S09: Dq Delay estimate: 456
N6.C2.D0.R0.S12: Offset Found: RdPtrOffsetDqs = 007
N0.C2.D0.R0: CheckMCTest: result = 0x3FE00
N2.C3.D1.R0.S09: Total Delay in PI ticks: TxDQS = 1019, TxDQ = 982
N4.C2.D0.R1.S10: Dq Delay estimate: 442
N6.C2.D0.R0.S13: Offset Found: RdPtrOffsetDqs = 006
N0.C2.D0.R0: CheckMCTest: passed
N2.C3.D1.R0.S10: Total Delay in PI ticks: TxDQS = 1004, TxDQ = 969
N4.C2.D0.R1.S11: Dq Delay estimate: 433
N6.C2.D0.R0.S14: Offset Found: RdPtrOffsetDqs = 006
N0.C2.D0.R0: CheckMCTest: passed
N2.C3.D1.R0.S11: Total Delay in PI ticks: TxDQS = 994, TxDQ = 958
N4.C2.D0.R1.S12: Dq Delay estimate: 418
N6.C2.D0.R0.S15: Offset Found: RdPtrOffsetDqs = 006
N0.C2.D0.R0.S09: Offset Found: RdPtrOffsetDqs = 007
N2.C3.D1.R0.S12: Total Delay in PI ticks: TxDQS = 980, TxDQ = 945
N4.C2.D0.R1.S13: Dq Delay estimate: 378
N6.C2.D0.R0.S16: Offset Found: RdPtrOffsetDqs = 007
N0.C2.D0.R0.S10: Offset Found: RdPtrOffsetDqs = 007
N2.C3.D1.R0.S13: Total Delay in PI ticks: TxDQS = 945, TxDQ = 910
N4.C2.D0.R1.S14: Dq Delay estimate: 401
N6.C2.D0.R0.S17: Offset Found: RdPtrOffsetDqs = 006
N0.C2.D0.R0.S11: Offset Found: RdPtrOffsetDqs = 007
N2.C3.D1.R0.S14: Total Delay in PI ticks: TxDQS = 955, TxDQ = 919
N4.C2.D0.R1.S15: Dq Delay estimate: 400
N6.C2.D0.R1: Write Training Coarse, lower nibbles / bytes
N0.C2.D0.R0.S12: Offset Found: RdPtrOffsetDqs = 007
N2.C3.D1.R0.S15: Total Delay in PI ticks: TxDQS = 970, TxDQ = 934
N4.C2.D0.R1.S16: Dq Delay estimate: 421
N6.C2.D0.R1.S00: Dq Delay estimate: 458
N0.C2.D0.R0.S13: Offset Found: RdPtrOffsetDqs = 006
N2.C3.D1.R0.S16: Total Delay in PI ticks: TxDQS = 987, TxDQ = 950
N4.C2.D0.R1.S17: Dq Delay estimate: 391
N6.C2.D0.R1.S01: Dq Delay estimate: 439
N0.C2.D0.R0.S14: Offset Found: RdPtrOffsetDqs = 006
N2.C3.D1.R0.S17: Total Delay in PI ticks: TxDQS = 960, TxDQ = 925
ACCM: F0 F0F0F0F0 F0F0F0F0
N6.C2.D0.R1.S02: Dq Delay estimate: 431
N0.C2.D0.R0.S15: Offset Found: RdPtrOffsetDqs = 007
N2.C3.D1.R1.S00: Total Delay in PI ticks: TxDQS = 1018, TxDQ = 979
ACCM: F0 F0F0F0F0 F0F0F0F0
N6.C2.D0.R1.S03: Dq Delay estimate: 411
N0.C2.D0.R0.S16: Offset Found: RdPtrOffsetDqs = 007
N2.C3.D1.R1.S01: Total Delay in PI ticks: TxDQS = 999, TxDQ = 964
ACCM: F0 F0F0F0F0 F0F0F0F0
N6.C2.D0.R1.S04: Dq Delay estimate: 375
N0.C2.D0.R0.S17: Offset Found: RdPtrOffsetDqs = 006
N2.C3.D1.R1.S02: Total Delay in PI ticks: TxDQS = 990, TxDQ = 953
ACCM: F0 F0F0F0F0 F0F0F0F0
N6.C2.D0.R1.S05: Dq Delay estimate: 401
N0.C2.D0.R1: Write Training Coarse, lower nibbles / bytes
N2.C3.D1.R1.S03: Total Delay in PI ticks: TxDQS = 975, TxDQ = 940
N4.C2.D0.R1: CheckMCTest: result = 0x3FE00
N6.C2.D0.R1.S06: Dq Delay estimate: 399
N0.C2.D0.R1.S00: Dq Delay estimate: 461
N2.C3.D1.R1.S04: Total Delay in PI ticks: TxDQS = 940, TxDQ = 904
ACCM: F0 F0F0F0F0 F0F0F0F0
N6.C2.D0.R1.S07: Dq Delay estimate: 422
N0.C2.D0.R1.S01: Dq Delay estimate: 446
N2.C3.D1.R1.S05: Total Delay in PI ticks: TxDQS = 953, TxDQ = 917
ACCM: F0 F0F0F0F0 F0F0F0F0
N6.C2.D0.R1.S08: Dq Delay estimate: 388
N0.C2.D0.R1.S02: Dq Delay estimate: 438
N2.C3.D1.R1.S06: Total Delay in PI ticks: TxDQS = 967, TxDQ = 930
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: 0F 0F0F0F0F 0F0F0F0F
N0.C2.D0.R1.S03: Dq Delay estimate: 420
N2.C3.D1.R1.S07: Total Delay in PI ticks: TxDQS = 985, TxDQ = 948
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: 0F 0F0F0F0F 0F0F0F0F
N0.C2.D0.R1.S04: Dq Delay estimate: 381
N2.C3.D1.R1.S08: Total Delay in PI ticks: TxDQS = 955, TxDQ = 919
N4.C2.D0.R1: CheckMCTest: result = 0x3FE00
ACCM: 0F 0F0F0F0F 0F0F0F0F
N0.C2.D0.R1.S05: Dq Delay estimate: 409
N2.C3.D1.R1.S09: Total Delay in PI ticks: TxDQS = 1017, TxDQ = 980
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: 0F 0F0F0F0F 0F0F0F0F
N0.C2.D0.R1.S06: Dq Delay estimate: 404
N2.C3.D1.R1.S10: Total Delay in PI ticks: TxDQS = 998, TxDQ = 963
ACCM: F0 F0F0F0F0 F0F0F0F0
N6.C2.D0.R1: CheckMCTest: result = 0x1FF
N0.C2.D0.R1.S07: Dq Delay estimate: 428
N2.C3.D1.R1.S11: Total Delay in PI ticks: TxDQS = 992, TxDQ = 956
ACCM: 00 000000B0 000000B0
ACCM: 0F 0F0F0F0F 0F0F0F0F
N0.C2.D0.R1.S08: Dq Delay estimate: 399
N2.C3.D1.R1.S12: Total Delay in PI ticks: TxDQS = 975, TxDQ = 940
ACCM: 00 000000B0 000000B0
ACCM: 0F 0F0F0F0F 0F0F0F0F
ACCM: 0F 0F0F0F0F 0F0F0F0F
N2.C3.D1.R1.S13: Total Delay in PI ticks: TxDQS = 939, TxDQ = 903
N4.C2.D0.R1: CheckMCTest: result = 0x3FE00
ACCM: 0F 0F0F0F0F 0F0F0F0F
ACCM: 0F 0F0F0F0F 0F0F0F0F
N2.C3.D1.R1.S14: Total Delay in PI ticks: TxDQS = 952, TxDQ = 915
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: 0F 0F0F0F0F 0F0F0F0F
ACCM: 0F 0F0F0F0F 0F0F0F0F
N2.C3.D1.R1.S15: Total Delay in PI ticks: TxDQS = 967, TxDQ = 930
ACCM: F0 F0F0F0F0 F0F0F0F0
N6.C2.D0.R1: CheckMCTest: result = 0x1FF
ACCM: 0F 0F0F0F0F 0F0F0F0F
N2.C3.D1.R1.S16: Total Delay in PI ticks: TxDQS = 984, TxDQ = 947
ACCM: 00 000000F0 000000F0
ACCM: 0F 0F0F0F0F 0F0F0F0F
N0.C2.D0.R1: CheckMCTest: result = 0x1FF
N2.C3.D1.R1.S17: Total Delay in PI ticks: TxDQS = 955, TxDQ = 920
ACCM: 00 000000F0 000000F0
ACCM: 0F 0F0F0F0F 0F0F0F0F
ACCM: 0F 0F0F0F0F 0F0F0F0F
N2: END WRITE LEVEL COARSE:
N4.C2.D0.R1: CheckMCTest: result = 0x3FE00
ACCM: 00 0000000B 0000000B
ACCM: 0F 0F0F0F0F 0F0F0F0F
N2: RunTrainStep: Final status = 0
N4.C2.D0.R1: CheckMCTest: passed
ACCM: 00 0000000B 0000000B
ACCM: 0F 0F0F0F0F 0F0F0F0F

END - Basic Write Level Training       Time         39412 ms
N4.C2.D0.R1: CheckMCTest: passed
N6.C2.D0.R1: CheckMCTest: result = 0x1FF
ACCM: 0F 0F0F0F0F 0F0F0F0F

START - Basic Write DQ/DQS Training
N4.C2.D0.R1.S09: Offset Found: RdPtrOffsetDqs = 007
ACCM: 0F 0F0F0F0F 0F0F0F0F
N0.C2.D0.R1: CheckMCTest: result = 0x1FF
N2.C0.D0.R0.S00: wrcmd2dqsstartlatency: 04
N4.C2.D0.R1.S10: Offset Found: RdPtrOffsetDqs = 007
ACCM: 0F 0F0F0F0F 0F0F0F0F
ACCM: 0F 0F0F0F0F 0F0F0F0F
N2.C0.D0.R0.S00: RdPtrOffsetTxDq: 06
N4.C2.D0.R1.S11: Offset Found: RdPtrOffsetDqs = 007
ACCM: 00 0000000F 0000000F
ACCM: 0F 0F0F0F0F 0F0F0F0F
N2.C0.D0.R0.S00: RdPtrOffsetTxDqs: 07
N4.C2.D0.R1.S12: Offset Found: RdPtrOffsetDqs = 007
ACCM: 00 0000000F 0000000F
ACCM: 0B 0B0B0B0B 0B000000
N2.C0.D0.R0.S00: PiTxDqs: 51
N4.C2.D0.R1.S13: Offset Found: RdPtrOffsetDqs = 006
N6.C2.D0.R1: CheckMCTest: result = 0x1FF
ACCM: 0B 0B0B0B0B 0B000000
N2.C0.D0.R0.S01: wrcmd2dqsstartlatency: 04
N4.C2.D0.R1.S14: Offset Found: RdPtrOffsetDqs = 006
N6.C2.D0.R1: CheckMCTest: passed
N0.C2.D0.R1: CheckMCTest: result = 0x1FF
N2.C0.D0.R0.S01: RdPtrOffsetTxDq: 05
N4.C2.D0.R1.S15: Offset Found: RdPtrOffsetDqs = 006
N6.C2.D0.R1: CheckMCTest: passed
ACCM: 0F 0F0F0F0F 0F0F0F0F
N2.C0.D0.R0.S01: RdPtrOffsetTxDqs: 07
N4.C2.D0.R1.S16: Offset Found: RdPtrOffsetDqs = 007
N6.C2.D0.R1.S00: Offset Found: RdPtrOffsetDqs = 007
ACCM: 0F 0F0F0F0F 0F0F0F0F
N2.C0.D0.R0.S01: PiTxDqs: 29
N4.C2.D0.R1.S17: Offset Found: RdPtrOffsetDqs = 006
N6.C2.D0.R1.S01: Offset Found: RdPtrOffsetDqs = 007
ACCM: 0F 0F0F0F0F 0B000000
N2.C0.D0.R0.S02: wrcmd2dqsstartlatency: 04
N4.C2.D1.R0: Write Training Coarse, lower nibbles / bytes
N6.C2.D0.R1.S02: Offset Found: RdPtrOffsetDqs = 007
ACCM: 0F 0F0F0F0F 0B000000
N2.C0.D0.R0.S02: RdPtrOffsetTxDq: 05
N4.C2.D1.R0.S00: Dq Delay estimate: 465
N6.C2.D0.R1.S03: Offset Found: RdPtrOffsetDqs = 006
N0.C2.D0.R1: CheckMCTest: result = 0x1FF
N2.C0.D0.R0.S02: RdPtrOffsetTxDqs: 07
N4.C2.D1.R0.S01: Dq Delay estimate: 450
N6.C2.D0.R1.S04: Offset Found: RdPtrOffsetDqs = 006
N0.C2.D0.R1: CheckMCTest: passed
N2.C0.D0.R0.S02: PiTxDqs: 21
N4.C2.D1.R0.S02: Dq Delay estimate: 442
N6.C2.D0.R1.S05: Offset Found: RdPtrOffsetDqs = 006
N0.C2.D0.R1: CheckMCTest: passed
N2.C0.D0.R0.S03: wrcmd2dqsstartlatency: 04
N4.C2.D1.R0.S03: Dq Delay estimate: 427
N6.C2.D0.R1.S06: Offset Found: RdPtrOffsetDqs = 006
N0.C2.D0.R1.S00: Offset Found: RdPtrOffsetDqs = 007
N2.C0.D0.R0.S03: RdPtrOffsetTxDq: 05
N4.C2.D1.R0.S04: Dq Delay estimate: 384
N6.C2.D0.R1.S07: Offset Found: RdPtrOffsetDqs = 007
N0.C2.D0.R1.S01: Offset Found: RdPtrOffsetDqs = 007
N2.C0.D0.R0.S03: RdPtrOffsetTxDqs: 07
N4.C2.D1.R0.S05: Dq Delay estimate: 411
N6.C2.D0.R1.S08: Offset Found: RdPtrOffsetDqs = 006
N0.C2.D0.R1.S02: Offset Found: RdPtrOffsetDqs = 007
N2.C0.D0.R0.S03: PiTxDqs: 03
N4.C2.D1.R0.S06: Dq Delay estimate: 409
N6.C2.D0.R1: Write Training Coarse, upper nibbles
N0.C2.D0.R1.S03: Offset Found: RdPtrOffsetDqs = 007
N2.C0.D0.R0.S04: wrcmd2dqsstartlatency: 04
N4.C2.D1.R0.S07: Dq Delay estimate: 430
N6.C2.D0.R1.S09: Dq Delay estimate: 454
N0.C2.D0.R1.S04: Offset Found: RdPtrOffsetDqs = 006
N2.C0.D0.R0.S04: RdPtrOffsetTxDq: 05
N4.C2.D1.R0.S08: Dq Delay estimate: 398
N6.C2.D0.R1.S10: Dq Delay estimate: 441
N0.C2.D0.R1.S05: Offset Found: RdPtrOffsetDqs = 006
N2.C0.D0.R0.S04: RdPtrOffsetTxDqs: 06
ACCM: 0F 0F0F0F0F 0F0F0F0F
N6.C2.D0.R1.S11: Dq Delay estimate: 433
N0.C2.D0.R1.S06: Offset Found: RdPtrOffsetDqs = 006
N2.C0.D0.R0.S04: PiTxDqs: 34
ACCM: 0F 0F0F0F0F 0F0F0F0F
N6.C2.D0.R1.S12: Dq Delay estimate: 415
N0.C2.D0.R1.S07: Offset Found: RdPtrOffsetDqs = 007
N2.C0.D0.R0.S05: wrcmd2dqsstartlatency: 04
ACCM: 0F 0F0F0F0F 0F0F0F0F
N6.C2.D0.R1.S13: Dq Delay estimate: 375
N0.C2.D0.R1.S08: Offset Found: RdPtrOffsetDqs = 006
N2.C0.D0.R0.S05: RdPtrOffsetTxDq: 05
ACCM: 0F FF0F0FFF FFFFFF0F
N6.C2.D0.R1.S14: Dq Delay estimate: 404
N0.C2.D0.R1: Write Training Coarse, upper nibbles
N2.C0.D0.R0.S05: RdPtrOffsetTxDqs: 06
N4.C2.D1.R0: CheckMCTest: result = 0x13DFF
N6.C2.D0.R1.S15: Dq Delay estimate: 403
N0.C2.D0.R1.S09: Dq Delay estimate: 465
N2.C0.D0.R0.S05: PiTxDqs: 51
ACCM: 0F 0F0F0F0F 0F0F0F0F
N6.C2.D0.R1.S16: Dq Delay estimate: 422
N0.C2.D0.R1.S10: Dq Delay estimate: 448
N2.C0.D0.R0.S06: wrcmd2dqsstartlatency: 04
ACCM: 0F 0F0F0F0F 0F0F0F0F
N6.C2.D0.R1.S17: Dq Delay estimate: 395
N0.C2.D0.R1.S11: Dq Delay estimate: 439
N2.C0.D0.R0.S06: RdPtrOffsetTxDq: 05
ACCM: 0F 0F0F0F0F 0F0F0F0F
ACCM: F0 F0F0F0F0 F0F0F0F0
N0.C2.D0.R1.S12: Dq Delay estimate: 421
N2.C0.D0.R0.S06: RdPtrOffsetTxDqs: 06
ACCM: 0F FF0F0FFF FFFFFF0F
ACCM: F0 F0F0F0F0 F0F0F0F0
N0.C2.D0.R1.S13: Dq Delay estimate: 381
N2.C0.D0.R0.S06: PiTxDqs: 58
N4.C2.D1.R0: CheckMCTest: result = 0x13DFF
ACCM: F0 F0F0F0F0 F0F0F0F0
N0.C2.D0.R1.S14: Dq Delay estimate: 408
N2.C0.D0.R0.S07: wrcmd2dqsstartlatency: 04
ACCM: 0F 0F0F0F0F 0F0F0F0F
ACCM: F0 F0F0F0F0 F0F0F0F0
N0.C2.D0.R1.S15: Dq Delay estimate: 405
N2.C0.D0.R0.S07: RdPtrOffsetTxDq: 05
ACCM: 0F 0F0F0F0F 0F0F0F0F
N6.C2.D0.R1: CheckMCTest: result = 0x3FE00
N0.C2.D0.R1.S16: Dq Delay estimate: 430
N2.C0.D0.R0.S07: RdPtrOffsetTxDqs: 07
ACCM: 00 0B0B000B 0A0B0000
ACCM: F0 F0F0F0F0 F0F0F0F0
N0.C2.D0.R1.S17: Dq Delay estimate: 396
N2.C0.D0.R0.S07: PiTxDqs: 05
ACCM: 00 FB0B00FB FAFBF000
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: F0 F0F0F0F0 F0F0F0F0
N2.C0.D0.R0.S08: wrcmd2dqsstartlatency: 04
N4.C2.D1.R0: CheckMCTest: result = 0x13DFF
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: F0 F0F0F0F0 F0F0F0F0
N2.C0.D0.R0.S08: RdPtrOffsetTxDq: 05
ACCM: 0F 0F0F0F0F 0F0F0F0F
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: F0 F0F0F0F0 F0F0F0F0
N2.C0.D0.R0.S08: RdPtrOffsetTxDqs: 06
ACCM: 0F 0F0F0F0F 0F0F0F0F
N6.C2.D0.R1: CheckMCTest: result = 0x3FE00
ACCM: F0 F0F0F0F0 F0F0F0F0
N2.C0.D0.R0.S08: PiTxDqs: 47
ACCM: 00 0F0F000F 0A0B0000
ACCM: F0 F0F0F0F0 F0F0F0F0
N0.C2.D0.R1: CheckMCTest: result = 0x3FE00
N2.C0.D0.R0.S09: wrcmd2dqsstartlatency: 04
ACCM: 00 FF0F00FF FAFBF000
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: F0 F0F0F0F0 F0F0F0F0
N2.C0.D0.R0.S09: RdPtrOffsetTxDq: 06
N4.C2.D1.R0: CheckMCTest: result = 0x13DFF
ACCM: 00 0000B000 00000000
ACCM: F0 F0F0F0F0 F0F0F0F0
N2.C0.D0.R0.S09: RdPtrOffsetTxDqs: 07
ACCM: 00 00000000 00000000
ACCM: 00 0000B000 00000000
ACCM: F0 F0F0F0F0 F0F0F0F0
N2.C0.D0.R0.S09: PiTxDqs: 55
ACCM: 00 00000000 00000000
N6.C2.D0.R1: CheckMCTest: result = 0x3FE00
ACCM: F0 F0F0F0F0 F0F0F0F0
N2.C0.D0.R0.S10: wrcmd2dqsstartlatency: 04
ACCM: 00 00000000 00000000
ACCM: F0 F0F0F0F0 F0F0F0F0
N0.C2.D0.R1: CheckMCTest: result = 0x3FE00
N2.C0.D0.R0.S10: RdPtrOffsetTxDq: 05
ACCM: 00 F00000F0 F0F0F000
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: F0 F0F0F0F0 F0F0F0F0
N2.C0.D0.R0.S10: RdPtrOffsetTxDqs: 07
N4.C2.D1.R0: CheckMCTest: result = 0x13C00
ACCM: 00 0000F000 00000000
ACCM: F0 F0F0F0F0 F0F0F0F0
N2.C0.D0.R0.S10: PiTxDqs: 30
ACCM: 00 00000000 00000000
ACCM: 00 0000F000 00000000
ACCM: 00 B000B000 000000B0
N2.C0.D0.R0.S11: wrcmd2dqsstartlatency: 04
ACCM: 00 00000000 00000000
N6.C2.D0.R1: CheckMCTest: result = 0x3FE00
ACCM: 00 B000B000 000000B0
N2.C0.D0.R0.S11: RdPtrOffsetTxDq: 05
ACCM: 00 00000000 00000000
N6.C2.D0.R1: CheckMCTest: passed
N0.C2.D0.R1: CheckMCTest: result = 0x3FE00
N2.C0.D0.R0.S11: RdPtrOffsetTxDqs: 07
ACCM: 00 F00000F0 F0F0F000
N6.C2.D0.R1: CheckMCTest: passed
ACCM: F0 F0F0F0F0 F0F0F0F0
N2.C0.D0.R0.S11: PiTxDqs: 21
N4.C2.D1.R0: CheckMCTest: result = 0x13C00
N6.C2.D0.R1.S09: Offset Found: RdPtrOffsetDqs = 007
ACCM: F0 F0F0F0F0 F0F0F0F0
N2.C0.D0.R0.S12: wrcmd2dqsstartlatency: 04
N4.C2.D1.R0.S00: Offset Found: RdPtrOffsetDqs = 007
N6.C2.D0.R1.S10: Offset Found: RdPtrOffsetDqs = 007
ACCM: 00 F000F000 000000B0
N2.C0.D0.R0.S12: RdPtrOffsetTxDq: 05
N4.C2.D1.R0.S01: Offset Found: RdPtrOffsetDqs = 007
N6.C2.D0.R1.S11: Offset Found: RdPtrOffsetDqs = 007
ACCM: 00 F000F000 000000B0
N2.C0.D0.R0.S12: RdPtrOffsetTxDqs: 07
N4.C2.D1.R0.S02: Offset Found: RdPtrOffsetDqs = 007
N6.C2.D0.R1.S12: Offset Found: RdPtrOffsetDqs = 007
N0.C2.D0.R1: CheckMCTest: result = 0x3FE00
N2.C0.D0.R0.S12: PiTxDqs: 04
N4.C2.D1.R0.S03: Offset Found: RdPtrOffsetDqs = 007
N6.C2.D0.R1.S13: Offset Found: RdPtrOffsetDqs = 006
N0.C2.D0.R1: CheckMCTest: passed
N2.C0.D0.R0.S13: wrcmd2dqsstartlatency: 04
N4.C2.D1.R0.S04: Offset Found: RdPtrOffsetDqs = 006
N6.C2.D0.R1.S14: Offset Found: RdPtrOffsetDqs = 006
N0.C2.D0.R1: CheckMCTest: passed
N2.C0.D0.R0.S13: RdPtrOffsetTxDq: 05
N4.C2.D1.R0.S05: Offset Found: RdPtrOffsetDqs = 007
N6.C2.D0.R1.S15: Offset Found: RdPtrOffsetDqs = 006
N0.C2.D0.R1.S09: Offset Found: RdPtrOffsetDqs = 007
N2.C0.D0.R0.S13: RdPtrOffsetTxDqs: 06
N4.C2.D1.R0.S06: Offset Found: RdPtrOffsetDqs = 007
N6.C2.D0.R1.S16: Offset Found: RdPtrOffsetDqs = 007
N0.C2.D0.R1.S10: Offset Found: RdPtrOffsetDqs = 007
N2.C0.D0.R0.S13: PiTxDqs: 36
N4.C2.D1.R0.S07: Offset Found: RdPtrOffsetDqs = 007
N6.C2.D0.R1.S17: Offset Found: RdPtrOffsetDqs = 006
N0.C2.D0.R1.S11: Offset Found: RdPtrOffsetDqs = 007
N2.C0.D0.R0.S14: wrcmd2dqsstartlatency: 04
N4.C2.D1.R0.S08: Offset Found: RdPtrOffsetDqs = 006
N6.C2.D1.R0: Write Training Coarse, lower nibbles / bytes
N0.C2.D0.R1.S12: Offset Found: RdPtrOffsetDqs = 007
N2.C0.D0.R0.S14: RdPtrOffsetTxDq: 05
N4.C2.D1.R0: Write Training Coarse, upper nibbles
N6.C2.D1.R0.S00: Dq Delay estimate: 470
N0.C2.D0.R1.S13: Offset Found: RdPtrOffsetDqs = 006
N2.C0.D0.R0.S14: RdPtrOffsetTxDqs: 06
N4.C2.D1.R0.S09: Dq Delay estimate: 467
N6.C2.D1.R0.S01: Dq Delay estimate: 452
N0.C2.D0.R1.S14: Offset Found: RdPtrOffsetDqs = 006
N2.C0.D0.R0.S14: PiTxDqs: 52
N4.C2.D1.R0.S10: Dq Delay estimate: 448
N6.C2.D1.R0.S02: Dq Delay estimate: 446
N0.C2.D0.R1.S15: Offset Found: RdPtrOffsetDqs = 006
N2.C0.D0.R0.S15: wrcmd2dqsstartlatency: 04
N4.C2.D1.R0.S11: Dq Delay estimate: 444
N6.C2.D1.R0.S03: Dq Delay estimate: 429
N0.C2.D0.R1.S16: Offset Found: RdPtrOffsetDqs = 007
N2.C0.D0.R0.S15: RdPtrOffsetTxDq: 05
N4.C2.D1.R0.S12: Dq Delay estimate: 426
N6.C2.D1.R0.S04: Dq Delay estimate: 388
N0.C2.D0.R1.S17: Offset Found: RdPtrOffsetDqs = 006
N2.C0.D0.R0.S15: RdPtrOffsetTxDqs: 06
N4.C2.D1.R0.S13: Dq Delay estimate: 386
N6.C2.D1.R0.S05: Dq Delay estimate: 415
N0.C2.D1.R0: Write Training Coarse, lower nibbles / bytes
N2.C0.D0.R0.S15: PiTxDqs: 55
N4.C2.D1.R0.S14: Dq Delay estimate: 408
N6.C2.D1.R0.S06: Dq Delay estimate: 412
N0.C2.D1.R0.S00: Dq Delay estimate: 468
N2.C0.D0.R0.S16: wrcmd2dqsstartlatency: 04
N4.C2.D1.R0.S15: Dq Delay estimate: 410
N6.C2.D1.R0.S07: Dq Delay estimate: 436
N0.C2.D1.R0.S01: Dq Delay estimate: 451
N2.C0.D0.R0.S16: RdPtrOffsetTxDq: 05
N4.C2.D1.R0.S16: Dq Delay estimate: 432
N6.C2.D1.R0.S08: Dq Delay estimate: 399
N0.C2.D1.R0.S02: Dq Delay estimate: 445
N2.C0.D0.R0.S16: RdPtrOffsetTxDqs: 07
N4.C2.D1.R0.S17: Dq Delay estimate: 399
ACCM: 0F 0F0F0F0F 0F0F0F0F
N0.C2.D1.R0.S03: Dq Delay estimate: 429
N2.C0.D0.R0.S16: PiTxDqs: 05
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: 0F 0F0F0F0F 0F0F0F0F
N0.C2.D1.R0.S04: Dq Delay estimate: 386
N2.C0.D0.R0.S17: wrcmd2dqsstartlatency: 04
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: 0F 0F0F0F0F 0F0F0F0F
N0.C2.D1.R0.S05: Dq Delay estimate: 416
N2.C0.D0.R0.S17: RdPtrOffsetTxDq: 05
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: 0F FF0F0FFF FFFFFF0F
N0.C2.D1.R0.S06: Dq Delay estimate: 411
N2.C0.D0.R0.S17: RdPtrOffsetTxDqs: 06
ACCM: F0 F0F0F0F0 F0F0F0F0
N6.C2.D1.R0: CheckMCTest: result = 0x13DFF
N0.C2.D1.R0.S07: Dq Delay estimate: 435
N2.C0.D0.R0.S17: PiTxDqs: 47
N4.C2.D1.R0: CheckMCTest: result = 0x3FE00
ACCM: 0F 0F0F0F0F 0F0F0F0F
N0.C2.D1.R0.S08: Dq Delay estimate: 403
N2.C0.D0.R0.S00: RdPtrOffsetTxDq: 07
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: 0F 0F0F0F0F 0F0F0F0F
ACCM: 0F 0F0F0F0F 0F0F0F0F
N2.C0.D0.R0.S01: RdPtrOffsetTxDq: 06
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: 0F 0F0F0F0F 0F0F0F0F
ACCM: 0F 0F0F0F0F 0F0F0F0F
N2.C0.D0.R0.S02: RdPtrOffsetTxDq: 06
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: 0F FF0F0FFF FFFFFF0F
ACCM: 0F 0F0F0F0F 0F0F0F0F
N2.C0.D0.R0.S03: RdPtrOffsetTxDq: 06
ACCM: F0 F0F0F0F0 F0F0F0F0
N6.C2.D1.R0: CheckMCTest: result = 0x13DFF
ACCM: 0F FF0F0FFF FFFF0F0F
N2.C0.D0.R0.S04: RdPtrOffsetTxDq: 06
N4.C2.D1.R0: CheckMCTest: result = 0x3FE00
ACCM: 0F 0F0F0F0F 0F0F0F0F
N0.C2.D1.R0: CheckMCTest: result = 0x139FF
N2.C0.D0.R0.S05: RdPtrOffsetTxDq: 06
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: 0F 0F0F0F0F 0F0F0F0F
ACCM: 0F 0F0F0F0F 0F0F0F0F
N2.C0.D0.R0.S06: RdPtrOffsetTxDq: 06
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: 00 0B0B000B 0B000000
ACCM: 0F 0F0F0F0F 0F0F0F0F
N2.C0.D0.R0.S07: RdPtrOffsetTxDq: 06
ACCM: B0 B0B000B0 B0B000B0
ACCM: 00 FB0B00FB FBF0F000
ACCM: 0F 0F0F0F0F 0F0F0F0F
N2.C0.D0.R0.S08: RdPtrOffsetTxDq: 06
ACCM: B0 B0B000B0 B0B000B0
N6.C2.D1.R0: CheckMCTest: result = 0x13DFF
ACCM: 0F FF0F0FFF FFFF0F0F
N2.C0.D0.R0.S09: RdPtrOffsetTxDq: 07
N4.C2.D1.R0: CheckMCTest: result = 0x3FE00
ACCM: 0F 0F0F0F0F 0F0F0F0F
N0.C2.D1.R0: CheckMCTest: result = 0x139FF
N2.C0.D0.R0.S10: RdPtrOffsetTxDq: 06
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: 0F 0F0F0F0F 0F0F0F0F
ACCM: 0F 0F0F0F0F 0F0F0F0F
N2.C0.D0.R0.S11: RdPtrOffsetTxDq: 06
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: 00 0F0F000F 0F000000
ACCM: 0F 0F0F0F0F 0F0F0F0F
N2.C0.D0.R0.S12: RdPtrOffsetTxDq: 06
ACCM: F0 F0B000F0 F0F000F0
ACCM: 00 FF0F00FF FFF0F000
ACCM: 0B 000B000B 0B0B0B0B
N2.C0.D0.R0.S13: RdPtrOffsetTxDq: 06
ACCM: F0 F0B000F0 F0F000F0
N6.C2.D1.R0: CheckMCTest: result = 0x13DFF
ACCM: 0B F00B00FB FBFB0B0B
N2.C0.D0.R0.S14: RdPtrOffsetTxDq: 06
N4.C2.D1.R0: CheckMCTest: result = 0x3FE00
ACCM: 00 00000000 00000000
N0.C2.D1.R0: CheckMCTest: result = 0x139FF
N2.C0.D0.R0.S15: RdPtrOffsetTxDq: 06
N4.C2.D1.R0: CheckMCTest: passed
ACCM: 00 00000000 00000000
ACCM: 0F 0F0F0F0F 0F0F0F0F
N2.C0.D0.R0.S16: RdPtrOffsetTxDq: 06
N4.C2.D1.R0: CheckMCTest: passed
ACCM: 00 00000000 00000000
ACCM: 0F 0F0F0F0F 0F0F0F0F
N2.C0.D0.R0.S17: RdPtrOffsetTxDq: 06
N4.C2.D1.R0.S09: Offset Found: RdPtrOffsetDqs = 007
ACCM: 00 F00000F0 F0F0F000
ACCM: 0F 000F000F 0F0F0F0F
N2.C0.D0.R0.S00: RdPtrOffsetTxDq: 08
N4.C2.D1.R0.S10: Offset Found: RdPtrOffsetDqs = 007
N6.C2.D1.R0: CheckMCTest: result = 0x13C00
ACCM: 0F F00F00FF FFFF0F0F
N2.C0.D0.R0.S01: RdPtrOffsetTxDq: 07
N4.C2.D1.R0.S11: Offset Found: RdPtrOffsetDqs = 007
ACCM: 00 00000000 00000000
N0.C2.D1.R0: CheckMCTest: result = 0x139FF
N2.C0.D0.R0.S02: RdPtrOffsetTxDq: 07
N4.C2.D1.R0.S12: Offset Found: RdPtrOffsetDqs = 007
ACCM: 00 00000000 00000000
ACCM: 00 00000000 00000000
N2.C0.D0.R0.S03: RdPtrOffsetTxDq: 07
N4.C2.D1.R0.S13: Offset Found: RdPtrOffsetDqs = 006
ACCM: 00 00000000 00000000
ACCM: 00 00000000 00000000
N2.C0.D0.R0.S04: RdPtrOffsetTxDq: 07
N4.C2.D1.R0.S14: Offset Found: RdPtrOffsetDqs = 007
ACCM: 00 F00000F0 F0F0F000
ACCM: 00 00000000 00000000
N2.C0.D0.R0.S05: RdPtrOffsetTxDq: 07
N4.C2.D1.R0.S15: Offset Found: RdPtrOffsetDqs = 007
N6.C2.D1.R0: CheckMCTest: result = 0x13C00
ACCM: 00 F00000F0 F0F00000
N2.C0.D0.R0.S06: RdPtrOffsetTxDq: 07
N4.C2.D1.R0.S16: Offset Found: RdPtrOffsetDqs = 007
N6.C2.D1.R0.S00: Offset Found: RdPtrOffsetDqs = 007
N0.C2.D1.R0: CheckMCTest: result = 0x13800
N2.C0.D0.R0.S07: RdPtrOffsetTxDq: 07
N4.C2.D1.R0.S17: Offset Found: RdPtrOffsetDqs = 006
N6.C2.D1.R0.S01: Offset Found: RdPtrOffsetDqs = 007
ACCM: 00 00000000 00000000
N2.C0.D0.R0.S08: RdPtrOffsetTxDq: 07
N4.C2.D1.R1: Write Training Coarse, lower nibbles / bytes
N6.C2.D1.R0.S02: Offset Found: RdPtrOffsetDqs = 007
ACCM: 00 00000000 00000000
N2.C0.D0.R0.S09: RdPtrOffsetTxDq: 08
N4.C2.D1.R1.S00: Dq Delay estimate: 462
N6.C2.D1.R0.S03: Offset Found: RdPtrOffsetDqs = 007
ACCM: 00 00000000 00000000
N2.C0.D0.R0.S10: RdPtrOffsetTxDq: 07
N4.C2.D1.R1.S01: Dq Delay estimate: 447
N6.C2.D1.R0.S04: Offset Found: RdPtrOffsetDqs = 006
ACCM: 00 F00000F0 F0F00000
N2.C0.D0.R0.S11: RdPtrOffsetTxDq: 07
N4.C2.D1.R1.S02: Dq Delay estimate: 438
N6.C2.D1.R0.S05: Offset Found: RdPtrOffsetDqs = 007
N0.C2.D1.R0: CheckMCTest: result = 0x13800
N2.C0.D0.R0.S12: RdPtrOffsetTxDq: 07
N4.C2.D1.R1.S03: Dq Delay estimate: 425
N6.C2.D1.R0.S06: Offset Found: RdPtrOffsetDqs = 007
N0.C2.D1.R0.S00: Offset Found: RdPtrOffsetDqs = 007
N2.C0.D0.R0.S13: RdPtrOffsetTxDq: 07
N4.C2.D1.R1.S04: Dq Delay estimate: 381
N6.C2.D1.R0.S07: Offset Found: RdPtrOffsetDqs = 007
N0.C2.D1.R0.S01: Offset Found: RdPtrOffsetDqs = 007
N2.C0.D0.R0.S14: RdPtrOffsetTxDq: 07
N4.C2.D1.R1.S05: Dq Delay estimate: 409
N6.C2.D1.R0.S08: Offset Found: RdPtrOffsetDqs = 006
N0.C2.D1.R0.S02: Offset Found: RdPtrOffsetDqs = 007
N2.C0.D0.R0.S15: RdPtrOffsetTxDq: 07
N4.C2.D1.R1.S06: Dq Delay estimate: 402
N6.C2.D1.R0: Write Training Coarse, upper nibbles
N0.C2.D1.R0.S03: Offset Found: RdPtrOffsetDqs = 007
N2.C0.D0.R0.S16: RdPtrOffsetTxDq: 07
N4.C2.D1.R1.S07: Dq Delay estimate: 427
N6.C2.D1.R0.S09: Dq Delay estimate: 467
N0.C2.D1.R0.S04: Offset Found: RdPtrOffsetDqs = 006
N2.C0.D0.R0.S17: RdPtrOffsetTxDq: 07
N4.C2.D1.R1.S08: Dq Delay estimate: 393
N6.C2.D1.R0.S10: Dq Delay estimate: 455
N0.C2.D1.R0.S05: Offset Found: RdPtrOffsetDqs = 007
N2.C0.D0.R0.S00: Total Delay in PI ticks: TxDQ = 981
ACCM: 0F 0F0F0F0F 0F0F0F0F
N6.C2.D1.R0.S11: Dq Delay estimate: 448
N0.C2.D1.R0.S06: Offset Found: RdPtrOffsetDqs = 007
N2.C0.D0.R0.S01: Total Delay in PI ticks: TxDQ = 957
ACCM: 0F 0F0F0F0F 0F0F0F0F
N6.C2.D1.R0.S12: Dq Delay estimate: 429
N0.C2.D1.R0.S07: Offset Found: RdPtrOffsetDqs = 007
N2.C0.D0.R0.S02: Total Delay in PI ticks: TxDQ = 947
ACCM: 0F 0F0F0F0F 0F0F0F0F
N6.C2.D1.R0.S13: Dq Delay estimate: 388
N0.C2.D1.R0.S08: Offset Found: RdPtrOffsetDqs = 006
N2.C0.D0.R0.S03: Total Delay in PI ticks: TxDQ = 931
ACCM: 0F 0F0F0F0F 0F0F0F0F
N6.C2.D1.R0.S14: Dq Delay estimate: 416
N0.C2.D1.R0: Write Training Coarse, upper nibbles
N2.C0.D0.R0.S04: Total Delay in PI ticks: TxDQ = 899
N4.C2.D1.R1: CheckMCTest: result = 0x1FF
N6.C2.D1.R0.S15: Dq Delay estimate: 414
N0.C2.D1.R0.S09: Dq Delay estimate: 467
N2.C0.D0.R0.S05: Total Delay in PI ticks: TxDQ = 915
ACCM: 0F 0F0F0F0F 0F0F0F0F
N6.C2.D1.R0.S16: Dq Delay estimate: 435
N0.C2.D1.R0.S10: Dq Delay estimate: 456
N2.C0.D0.R0.S06: Total Delay in PI ticks: TxDQ = 923
ACCM: 0F 0F0F0F0F 0F0F0F0F
N6.C2.D1.R0.S17: Dq Delay estimate: 405
N0.C2.D1.R0.S11: Dq Delay estimate: 446
N2.C0.D0.R0.S07: Total Delay in PI ticks: TxDQ = 932
ACCM: 0F 0F0F0F0F 0F0F0F0F
ACCM: F0 F0F0F0F0 F0F0F0F0
N0.C2.D1.R0.S12: Dq Delay estimate: 426
N2.C0.D0.R0.S08: Total Delay in PI ticks: TxDQ = 913
ACCM: 0F 0F0F0F0F 0F0F0F0F
ACCM: F0 F0F0F0F0 F0F0F0F0
N0.C2.D1.R0.S13: Dq Delay estimate: 388
N2.C0.D0.R0.S09: Total Delay in PI ticks: TxDQ = 981
N4.C2.D1.R1: CheckMCTest: result = 0x1FF
ACCM: F0 F0F0F0F0 F0F0F0F0
N0.C2.D1.R0.S14: Dq Delay estimate: 414
N2.C0.D0.R0.S10: Total Delay in PI ticks: TxDQ = 959
ACCM: 0F 0F0F0F0F 0F0F0F0F
ACCM: F0 F0F0F0F0 F0F0F0F0
N0.C2.D1.R0.S15: Dq Delay estimate: 415
N2.C0.D0.R0.S11: Total Delay in PI ticks: TxDQ = 948
ACCM: 0F 0F0F0F0F 0F0F0F0F
N6.C2.D1.R0: CheckMCTest: result = 0x3FE00
N0.C2.D1.R0.S16: Dq Delay estimate: 435
N2.C0.D0.R0.S12: Total Delay in PI ticks: TxDQ = 930
ACCM: 00 0000000B 0B000000
ACCM: F0 F0F0F0F0 F0F0F0F0
N0.C2.D1.R0.S17: Dq Delay estimate: 403
N2.C0.D0.R0.S13: Total Delay in PI ticks: TxDQ = 901
ACCM: 00 0000000B 0B000000
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: F0 F0F0F0F0 F0F0F0F0
N2.C0.D0.R0.S14: Total Delay in PI ticks: TxDQ = 916
N4.C2.D1.R1: CheckMCTest: result = 0x1FF
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: F0 F0F0F0F0 F0F0F0F0
N2.C0.D0.R0.S15: Total Delay in PI ticks: TxDQ = 919
ACCM: 0F 0F0F0F0F 0F0F0F0F
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: F0 F0F0F0F0 F0F0F0F0
N2.C0.D0.R0.S16: Total Delay in PI ticks: TxDQ = 933
ACCM: 0F 0F0F0F0F 0F0F0F0F
N6.C2.D1.R0: CheckMCTest: result = 0x3FE00
ACCM: F0 F0F0F0F0 F0F0F0F0
N2.C0.D0.R0.S17: Total Delay in PI ticks: TxDQ = 911
ACCM: 00 0000000F 0F000000
ACCM: F0 F0F0F0F0 F0F0F0F0
N0.C2.D1.R0: CheckMCTest: result = 0x3FE00
N2.C0.D0.R1.S00: wrcmd2dqsstartlatency: 04
ACCM: 00 0000000F 0F000000
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: F0 F0F0F0F0 F0F0F0F0
N2.C0.D0.R1.S00: RdPtrOffsetTxDq: 06
N4.C2.D1.R1: CheckMCTest: result = 0x1FF
ACCM: 00 B0B00000 000000B0
ACCM: F0 F0F0F0F0 F0F0F0F0
N2.C0.D0.R1.S00: RdPtrOffsetTxDqs: 07
N4.C2.D1.R1: CheckMCTest: passed
ACCM: 00 B0B00000 000000B0
ACCM: F0 F0F0F0F0 F0F0F0F0
N2.C0.D0.R1.S00: PiTxDqs: 47
N4.C2.D1.R1: CheckMCTest: passed
N6.C2.D1.R0: CheckMCTest: result = 0x3FE00
ACCM: F0 F0F0F0F0 F0F0F0F0
N2.C0.D0.R1.S01: wrcmd2dqsstartlatency: 04
N4.C2.D1.R1.S00: Offset Found: RdPtrOffsetDqs = 007
ACCM: F0 F0F0F0F0 F0F0F0F0
N0.C2.D1.R0: CheckMCTest: result = 0x3FE00
N2.C0.D0.R1.S01: RdPtrOffsetTxDq: 05
N4.C2.D1.R1.S01: Offset Found: RdPtrOffsetDqs = 007
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: F0 F0F0F0F0 F0F0F0F0
N2.C0.D0.R1.S01: RdPtrOffsetTxDqs: 07
N4.C2.D1.R1.S02: Offset Found: RdPtrOffsetDqs = 007
ACCM: 00 B0F00000 000000B0
ACCM: F0 F0F0F0F0 F0F0F0F0
N2.C0.D0.R1.S01: PiTxDqs: 27
N4.C2.D1.R1.S03: Offset Found: RdPtrOffsetDqs = 007
ACCM: 00 B0F00000 000000B0
ACCM: 00 00B000B0 B000B0B0
N2.C0.D0.R1.S02: wrcmd2dqsstartlatency: 04
N4.C2.D1.R1.S04: Offset Found: RdPtrOffsetDqs = 006
N6.C2.D1.R0: CheckMCTest: result = 0x3FE00
ACCM: 00 00B000B0 B000B0B0
N2.C0.D0.R1.S02: RdPtrOffsetTxDq: 05
N4.C2.D1.R1.S05: Offset Found: RdPtrOffsetDqs = 006
N6.C2.D1.R0: CheckMCTest: passed
N0.C2.D1.R0: CheckMCTest: result = 0x3FE00
N2.C0.D0.R1.S02: RdPtrOffsetTxDqs: 07
N4.C2.D1.R1.S06: Offset Found: RdPtrOffsetDqs = 006
N6.C2.D1.R0: CheckMCTest: passed
ACCM: F0 F0F0F0F0 F0F0F0F0
N2.C0.D0.R1.S02: PiTxDqs: 13
N4.C2.D1.R1.S07: Offset Found: RdPtrOffsetDqs = 007
N6.C2.D1.R0.S09: Offset Found: RdPtrOffsetDqs = 007
ACCM: F0 F0F0F0F0 F0F0F0F0
N2.C0.D0.R1.S03: wrcmd2dqsstartlatency: 04
N4.C2.D1.R1.S08: Offset Found: RdPtrOffsetDqs = 006
N6.C2.D1.R0.S10: Offset Found: RdPtrOffsetDqs = 007
ACCM: 00 00F000F0 F000F0F0
N2.C0.D0.R1.S03: RdPtrOffsetTxDq: 05
N4.C2.D1.R1: Write Training Coarse, upper nibbles
N6.C2.D1.R0.S11: Offset Found: RdPtrOffsetDqs = 007
ACCM: 00 00F000F0 F000F0F0
N2.C0.D0.R1.S03: RdPtrOffsetTxDqs: 06
N4.C2.D1.R1.S09: Dq Delay estimate: 461
N6.C2.D1.R0.S12: Offset Found: RdPtrOffsetDqs = 007
N0.C2.D1.R0: CheckMCTest: result = 0x3FE00
N2.C0.D0.R1.S03: PiTxDqs: 60
N4.C2.D1.R1.S10: Dq Delay estimate: 447
N6.C2.D1.R0.S13: Offset Found: RdPtrOffsetDqs = 006
N0.C2.D1.R0: CheckMCTest: passed
N2.C0.D0.R1.S04: wrcmd2dqsstartlatency: 04
N4.C2.D1.R1.S11: Dq Delay estimate: 439
N6.C2.D1.R0.S14: Offset Found: RdPtrOffsetDqs = 007
N0.C2.D1.R0: CheckMCTest: passed
N2.C0.D0.R1.S04: RdPtrOffsetTxDq: 04
N4.C2.D1.R1.S12: Dq Delay estimate: 424
N6.C2.D1.R0.S15: Offset Found: RdPtrOffsetDqs = 007
N0.C2.D1.R0.S09: Offset Found: RdPtrOffsetDqs = 007
N2.C0.D0.R1.S04: RdPtrOffsetTxDqs: 06
N4.C2.D1.R1.S13: Dq Delay estimate: 382
N6.C2.D1.R0.S16: Offset Found: RdPtrOffsetDqs = 007
N0.C2.D1.R0.S10: Offset Found: RdPtrOffsetDqs = 007
N2.C0.D0.R1.S04: PiTxDqs: 27
N4.C2.D1.R1.S14: Dq Delay estimate: 407
N6.C2.D1.R0.S17: Offset Found: RdPtrOffsetDqs = 006
N0.C2.D1.R0.S11: Offset Found: RdPtrOffsetDqs = 007
N2.C0.D0.R1.S05: wrcmd2dqsstartlatency: 04
N4.C2.D1.R1.S15: Dq Delay estimate: 408
N6.C2.D1.R1: Write Training Coarse, lower nibbles / bytes
N0.C2.D1.R0.S12: Offset Found: RdPtrOffsetDqs = 007
N2.C0.D0.R1.S05: RdPtrOffsetTxDq: 05
N4.C2.D1.R1.S16: Dq Delay estimate: 428
N6.C2.D1.R1.S00: Dq Delay estimate: 465
N0.C2.D1.R0.S13: Offset Found: RdPtrOffsetDqs = 006
N2.C0.D0.R1.S05: RdPtrOffsetTxDqs: 06
N4.C2.D1.R1.S17: Dq Delay estimate: 394
N6.C2.D1.R1.S01: Dq Delay estimate: 447
N0.C2.D1.R0.S14: Offset Found: RdPtrOffsetDqs = 007
N2.C0.D0.R1.S05: PiTxDqs: 44
ACCM: F0 F0F0F0F0 F0F0F0F0
N6.C2.D1.R1.S02: Dq Delay estimate: 440
N0.C2.D1.R0.S15: Offset Found: RdPtrOffsetDqs = 007
N2.C0.D0.R1.S06: wrcmd2dqsstartlatency: 04
ACCM: F0 F0F0F0F0 F0F0F0F0
N6.C2.D1.R1.S03: Dq Delay estimate: 422
N0.C2.D1.R0.S16: Offset Found: RdPtrOffsetDqs = 007
N2.C0.D0.R1.S06: RdPtrOffsetTxDq: 05
ACCM: F0 F0F0F0F0 F0F0F0F0
N6.C2.D1.R1.S04: Dq Delay estimate: 383
N0.C2.D1.R0.S17: Offset Found: RdPtrOffsetDqs = 006
N2.C0.D0.R1.S06: RdPtrOffsetTxDqs: 06
ACCM: F0 F0F0F0F0 F0F0F0F0
N6.C2.D1.R1.S05: Dq Delay estimate: 412
N0.C2.D1.R1: Write Training Coarse, lower nibbles / bytes
N2.C0.D0.R1.S06: PiTxDqs: 50
N4.C2.D1.R1: CheckMCTest: result = 0x3FE00
N6.C2.D1.R1.S06: Dq Delay estimate: 407
N0.C2.D1.R1.S00: Dq Delay estimate: 464
N2.C0.D0.R1.S07: wrcmd2dqsstartlatency: 04
ACCM: F0 F0F0F0F0 F0F0F0F0
N6.C2.D1.R1.S07: Dq Delay estimate: 432
N0.C2.D1.R1.S01: Dq Delay estimate: 449
N2.C0.D0.R1.S07: RdPtrOffsetTxDq: 05
ACCM: F0 F0F0F0F0 F0F0F0F0
N6.C2.D1.R1.S08: Dq Delay estimate: 395
N0.C2.D1.R1.S02: Dq Delay estimate: 440
N2.C0.D0.R1.S07: RdPtrOffsetTxDqs: 07
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: 0F 0F0F0F0F 0F0F0F0F
N0.C2.D1.R1.S03: Dq Delay estimate: 424
N2.C0.D0.R1.S07: PiTxDqs: 00
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: 0F 0F0F0F0F 0F0F0F0F
N0.C2.D1.R1.S04: Dq Delay estimate: 385
N2.C0.D0.R1.S08: wrcmd2dqsstartlatency: 04
N4.C2.D1.R1: CheckMCTest: result = 0x3FE00
ACCM: 0F 0F0F0F0F 0F0F0F0F
N0.C2.D1.R1.S05: Dq Delay estimate: 414
N2.C0.D0.R1.S08: RdPtrOffsetTxDq: 05
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: 0F 0F0F0F0F 0F0F0F0F
N0.C2.D1.R1.S06: Dq Delay estimate: 408
N2.C0.D0.R1.S08: RdPtrOffsetTxDqs: 06
ACCM: F0 F0F0F0F0 F0F0F0F0
N6.C2.D1.R1: CheckMCTest: result = 0x1FF
N0.C2.D1.R1.S07: Dq Delay estimate: 430
N2.C0.D0.R1.S08: PiTxDqs: 38
ACCM: 00 B0B0B000 00000000
ACCM: 0F 0F0F0F0F 0F0F0F0F
N0.C2.D1.R1.S08: Dq Delay estimate: 396
N2.C0.D0.R1.S09: wrcmd2dqsstartlatency: 04
ACCM: 00 B0B0B000 00000000
ACCM: 0F 0F0F0F0F 0F0F0F0F
ACCM: 0F 0F0F0F0F 0F0F0F0F
N2.C0.D0.R1.S09: RdPtrOffsetTxDq: 06
N4.C2.D1.R1: CheckMCTest: result = 0x3FE00
ACCM: 0F 0F0F0F0F 0F0F0F0F
ACCM: 0F 0F0F0F0F 0F0F0F0F
N2.C0.D0.R1.S09: RdPtrOffsetTxDqs: 07
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: 0F 0F0F0F0F 0F0F0F0F
ACCM: 0F 0F0F0F0F 0F0F0F0F
N2.C0.D0.R1.S09: PiTxDqs: 42
ACCM: F0 F0F0F0F0 F0F0F0F0
N6.C2.D1.R1: CheckMCTest: result = 0x1FF
ACCM: 0F 0F0F0F0F 0F0F0F0F
N2.C0.D0.R1.S10: wrcmd2dqsstartlatency: 04
ACCM: 00 F0F0F000 00000000
ACCM: 0F 0F0F0F0F 0F0F0F0F
N0.C2.D1.R1: CheckMCTest: result = 0x1FF
N2.C0.D0.R1.S10: RdPtrOffsetTxDq: 05
ACCM: 00 F0F0F000 00000000
ACCM: 0F 0F0F0F0F 0F0F0F0F
ACCM: 0F 0F0F0F0F 0F0F0F0F
N2.C0.D0.R1.S10: RdPtrOffsetTxDqs: 07
N4.C2.D1.R1: CheckMCTest: result = 0x3FE00
ACCM: 00 0B000B0B 0B0B000B
ACCM: 0F 0F0F0F0F 0F0F0F0F
N2.C0.D0.R1.S10: PiTxDqs: 25
N4.C2.D1.R1: CheckMCTest: passed
ACCM: 00 0B000B0B 0B0B000B
ACCM: 0F 0F0F0F0F 0F0F0F0F
N2.C0.D0.R1.S11: wrcmd2dqsstartlatency: 04
N4.C2.D1.R1: CheckMCTest: passed
N6.C2.D1.R1: CheckMCTest: result = 0x1FF
ACCM: 0F 0F0F0F0F 0F0F0F0F
N2.C0.D0.R1.S11: RdPtrOffsetTxDq: 05
N4.C2.D1.R1.S09: Offset Found: RdPtrOffsetDqs = 007
ACCM: 0F 0F0F0F0F 0F0F0F0F
N0.C2.D1.R1: CheckMCTest: result = 0x1FF
N2.C0.D0.R1.S11: RdPtrOffsetTxDqs: 07
N4.C2.D1.R1.S10: Offset Found: RdPtrOffsetDqs = 007
ACCM: 0F 0F0F0F0F 0F0F0F0F
ACCM: 0F 0F0F0F0F 0F0F0F0F
N2.C0.D0.R1.S11: PiTxDqs: 15
N4.C2.D1.R1.S11: Offset Found: RdPtrOffsetDqs = 007
ACCM: 00 0F000F0F 0F0F000B
ACCM: 0F 0F0F0F0F 0F0F0F0F
N2.C0.D0.R1.S12: wrcmd2dqsstartlatency: 04
N4.C2.D1.R1.S12: Offset Found: RdPtrOffsetDqs = 007
ACCM: 00 0F000F0F 0F0F000B
ACCM: 00 0B0B0B00 00000000
N2.C0.D0.R1.S12: RdPtrOffsetTxDq: 05
N4.C2.D1.R1.S13: Offset Found: RdPtrOffsetDqs = 006
N6.C2.D1.R1: CheckMCTest: result = 0x1FF
ACCM: 00 0B0B0B00 00000000
N2.C0.D0.R1.S12: RdPtrOffsetTxDqs: 07
N4.C2.D1.R1.S14: Offset Found: RdPtrOffsetDqs = 006
N6.C2.D1.R1: CheckMCTest: passed
N0.C2.D1.R1: CheckMCTest: result = 0x1FF
N2.C0.D0.R1.S12: PiTxDqs: 00
N4.C2.D1.R1.S15: Offset Found: RdPtrOffsetDqs = 006
N6.C2.D1.R1: CheckMCTest: passed
ACCM: 0F 0F0F0F0F 0F0F0F0F
N2.C0.D0.R1.S13: wrcmd2dqsstartlatency: 04
N4.C2.D1.R1.S16: Offset Found: RdPtrOffsetDqs = 007
N6.C2.D1.R1.S00: Offset Found: RdPtrOffsetDqs = 007
ACCM: 0F 0F0F0F0F 0F0F0F0F
N2.C0.D0.R1.S13: RdPtrOffsetTxDq: 04
N4.C2.D1.R1.S17: Offset Found: RdPtrOffsetDqs = 006
N6.C2.D1.R1.S01: Offset Found: RdPtrOffsetDqs = 007
ACCM: 00 0F0F0F00 00000000
N2.C0.D0.R1.S13: RdPtrOffsetTxDqs: 06
N4.C2: Calculating Optimimum DQS Values
N6.C2.D1.R1.S02: Offset Found: RdPtrOffsetDqs = 007
ACCM: 00 0F0F0F00 00000000
N2.C0.D0.R1.S13: PiTxDqs: 27
N4.C2.D0.R0.S00: Total Delay in PI ticks: TxDQS = 1011, TxDQ = 975
N6.C2.D1.R1.S03: Offset Found: RdPtrOffsetDqs = 007
N0.C2.D1.R1: CheckMCTest: result = 0x1FF
N2.C0.D0.R1.S14: wrcmd2dqsstartlatency: 04
N4.C2.D0.R0.S01: Total Delay in PI ticks: TxDQS = 997, TxDQ = 960
N6.C2.D1.R1.S04: Offset Found: RdPtrOffsetDqs = 006
N0.C2.D1.R1: CheckMCTest: passed
N2.C0.D0.R1.S14: RdPtrOffsetTxDq: 05
N4.C2.D0.R0.S02: Total Delay in PI ticks: TxDQS = 987, TxDQ = 951
N6.C2.D1.R1.S05: Offset Found: RdPtrOffsetDqs = 007
N0.C2.D1.R1: CheckMCTest: passed
N2.C0.D0.R1.S14: RdPtrOffsetTxDqs: 06
N4.C2.D0.R0.S03: Total Delay in PI ticks: TxDQS = 969, TxDQ = 934
N6.C2.D1.R1.S06: Offset Found: RdPtrOffsetDqs = 006
N0.C2.D1.R1.S00: Offset Found: RdPtrOffsetDqs = 007
N2.C0.D0.R1.S14: PiTxDqs: 45
N4.C2.D0.R0.S04: Total Delay in PI ticks: TxDQS = 926, TxDQ = 890
N6.C2.D1.R1.S07: Offset Found: RdPtrOffsetDqs = 007
N0.C2.D1.R1.S01: Offset Found: RdPtrOffsetDqs = 007
N2.C0.D0.R1.S15: wrcmd2dqsstartlatency: 04
N4.C2.D0.R0.S05: Total Delay in PI ticks: TxDQS = 956, TxDQ = 919
N6.C2.D1.R1.S08: Offset Found: RdPtrOffsetDqs = 006
N0.C2.D1.R1.S02: Offset Found: RdPtrOffsetDqs = 007
N2.C0.D0.R1.S15: RdPtrOffsetTxDq: 05
N4.C2.D0.R0.S06: Total Delay in PI ticks: TxDQS = 958, TxDQ = 920
N6.C2.D1.R1: Write Training Coarse, upper nibbles
N0.C2.D1.R1.S03: Offset Found: RdPtrOffsetDqs = 007
N2.C0.D0.R1.S15: RdPtrOffsetTxDqs: 06
N4.C2.D0.R0.S07: Total Delay in PI ticks: TxDQS = 976, TxDQ = 939
N6.C2.D1.R1.S09: Dq Delay estimate: 460
N0.C2.D1.R1.S04: Offset Found: RdPtrOffsetDqs = 006
N2.C0.D0.R1.S15: PiTxDqs: 50
N4.C2.D0.R0.S08: Total Delay in PI ticks: TxDQS = 949, TxDQ = 912
N6.C2.D1.R1.S10: Dq Delay estimate: 449
N0.C2.D1.R1.S05: Offset Found: RdPtrOffsetDqs = 007
N2.C0.D0.R1.S16: wrcmd2dqsstartlatency: 04
N4.C2.D0.R0.S09: Total Delay in PI ticks: TxDQS = 1014, TxDQ = 978
N6.C2.D1.R1.S11: Dq Delay estimate: 443
N0.C2.D1.R1.S06: Offset Found: RdPtrOffsetDqs = 006
N2.C0.D0.R1.S16: RdPtrOffsetTxDq: 05
N4.C2.D0.R0.S10: Total Delay in PI ticks: TxDQS = 1000, TxDQ = 961
N6.C2.D1.R1.S12: Dq Delay estimate: 428
N0.C2.D1.R1.S07: Offset Found: RdPtrOffsetDqs = 007
N2.C0.D0.R1.S16: RdPtrOffsetTxDqs: 07
N4.C2.D0.R0.S11: Total Delay in PI ticks: TxDQS = 988, TxDQ = 954
N6.C2.D1.R1.S13: Dq Delay estimate: 384
N0.C2.D1.R1.S08: Offset Found: RdPtrOffsetDqs = 006
N2.C0.D0.R1.S16: PiTxDqs: 01
N4.C2.D0.R0.S12: Total Delay in PI ticks: TxDQS = 970, TxDQ = 934
N6.C2.D1.R1.S14: Dq Delay estimate: 411
N0.C2.D1.R1: Write Training Coarse, upper nibbles
N2.C0.D0.R1.S17: wrcmd2dqsstartlatency: 04
N4.C2.D0.R0.S13: Total Delay in PI ticks: TxDQS = 929, TxDQ = 897
N6.C2.D1.R1.S15: Dq Delay estimate: 412
N0.C2.D1.R1.S09: Dq Delay estimate: 465
N2.C0.D0.R1.S17: RdPtrOffsetTxDq: 05
N4.C2.D0.R0.S14: Total Delay in PI ticks: TxDQS = 958, TxDQ = 920
N6.C2.D1.R1.S16: Dq Delay estimate: 433
N0.C2.D1.R1.S10: Dq Delay estimate: 452
N2.C0.D0.R1.S17: RdPtrOffsetTxDqs: 06
N4.C2.D0.R0.S15: Total Delay in PI ticks: TxDQS = 958, TxDQ = 921
N6.C2.D1.R1.S17: Dq Delay estimate: 398
N0.C2.D1.R1.S11: Dq Delay estimate: 445
N2.C0.D0.R1.S17: PiTxDqs: 39
N4.C2.D0.R0.S16: Total Delay in PI ticks: TxDQS = 977, TxDQ = 941
ACCM: F0 F0F0F0F0 F0F0F0F0
N0.C2.D1.R1.S12: Dq Delay estimate: 426
N2.C0.D0.R1.S00: RdPtrOffsetTxDq: 07
N4.C2.D0.R0.S17: Total Delay in PI ticks: TxDQS = 946, TxDQ = 910
ACCM: F0 F0F0F0F0 F0F0F0F0
N0.C2.D1.R1.S13: Dq Delay estimate: 387
N2.C0.D0.R1.S01: RdPtrOffsetTxDq: 06
N4.C2.D0.R1.S00: Total Delay in PI ticks: TxDQS = 1004, TxDQ = 968
ACCM: F0 F0F0F0F0 F0F0F0F0
N0.C2.D1.R1.S14: Dq Delay estimate: 413
N2.C0.D0.R1.S02: RdPtrOffsetTxDq: 06
N4.C2.D0.R1.S01: Total Delay in PI ticks: TxDQS = 990, TxDQ = 953
ACCM: F0 F0F0F0F0 F0F0F0F0
N0.C2.D1.R1.S15: Dq Delay estimate: 410
N2.C0.D0.R1.S03: RdPtrOffsetTxDq: 06
N4.C2.D0.R1.S02: Total Delay in PI ticks: TxDQS = 979, TxDQ = 943
N6.C2.D1.R1: CheckMCTest: result = 0x3FE00
N0.C2.D1.R1.S16: Dq Delay estimate: 435
N2.C0.D0.R1.S04: RdPtrOffsetTxDq: 05
N4.C2.D0.R1.S03: Total Delay in PI ticks: TxDQS = 964, TxDQ = 928
ACCM: F0 F0F0F0F0 F0F0F0F0
N0.C2.D1.R1.S17: Dq Delay estimate: 397
N2.C0.D0.R1.S05: RdPtrOffsetTxDq: 06
N4.C2.D0.R1.S04: Total Delay in PI ticks: TxDQS = 920, TxDQ = 884
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: F0 F0F0F0F0 F0F0F0F0
N2.C0.D0.R1.S06: RdPtrOffsetTxDq: 06
N4.C2.D0.R1.S05: Total Delay in PI ticks: TxDQS = 950, TxDQ = 913
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: F0 F0F0F0F0 F0F0F0F0
N2.C0.D0.R1.S07: RdPtrOffsetTxDq: 06
N4.C2.D0.R1.S06: Total Delay in PI ticks: TxDQS = 947, TxDQ = 909
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: F0 F0F0F0F0 F0F0F0F0
N2.C0.D0.R1.S08: RdPtrOffsetTxDq: 06
N4.C2.D0.R1.S07: Total Delay in PI ticks: TxDQS = 971, TxDQ = 934
N6.C2.D1.R1: CheckMCTest: result = 0x3FE00
ACCM: F0 F0F0F0F0 F0F0F0F0
N2.C0.D0.R1.S09: RdPtrOffsetTxDq: 07
N4.C2.D0.R1.S08: Total Delay in PI ticks: TxDQS = 942, TxDQ = 904
ACCM: F0 F0F0F0F0 F0F0F0F0
N0.C2.D1.R1: CheckMCTest: result = 0x3FE00
N2.C0.D0.R1.S10: RdPtrOffsetTxDq: 06
N4.C2.D0.R1.S09: Total Delay in PI ticks: TxDQS = 1004, TxDQ = 968
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: F0 F0F0F0F0 F0F0F0F0
N2.C0.D0.R1.S11: RdPtrOffsetTxDq: 06
N4.C2.D0.R1.S10: Total Delay in PI ticks: TxDQS = 992, TxDQ = 954
ACCM: 00 B0000000 B0B000B0
ACCM: F0 F0F0F0F0 F0F0F0F0
N2.C0.D0.R1.S12: RdPtrOffsetTxDq: 06
N4.C2.D0.R1.S11: Total Delay in PI ticks: TxDQS = 979, TxDQ = 945
ACCM: 00 B0000000 B0B000B0
ACCM: F0 F0F0F0F0 F0F0F0F0
N2.C0.D0.R1.S13: RdPtrOffsetTxDq: 05
N4.C2.D0.R1.S12: Total Delay in PI ticks: TxDQS = 966, TxDQ = 930
N6.C2.D1.R1: CheckMCTest: result = 0x3FE00
ACCM: F0 F0F0F0F0 F0F0F0F0
N2.C0.D0.R1.S14: RdPtrOffsetTxDq: 06
N4.C2.D0.R1.S13: Total Delay in PI ticks: TxDQS = 922, TxDQ = 890
ACCM: F0 F0F0F0F0 F0F0F0F0
N0.C2.D1.R1: CheckMCTest: result = 0x3FE00
N2.C0.D0.R1.S15: RdPtrOffsetTxDq: 06
N4.C2.D0.R1.S14: Total Delay in PI ticks: TxDQS = 951, TxDQ = 913
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: F0 F0F0F0F0 F0F0F0F0
N2.C0.D0.R1.S16: RdPtrOffsetTxDq: 06
N4.C2.D0.R1.S15: Total Delay in PI ticks: TxDQS = 949, TxDQ = 912
ACCM: 00 B0000000 F0F000F0
ACCM: F0 F0F0F0F0 F0F0F0F0
N2.C0.D0.R1.S17: RdPtrOffsetTxDq: 06
N4.C2.D0.R1.S16: Total Delay in PI ticks: TxDQS = 969, TxDQ = 933
ACCM: 00 B0000000 F0F000F0
ACCM: 00 B0B0B0B0 B00000B0
N2.C0.D0.R1.S00: RdPtrOffsetTxDq: 08
N4.C2.D0.R1.S17: Total Delay in PI ticks: TxDQS = 939, TxDQ = 903
N6.C2.D1.R1: CheckMCTest: result = 0x3FE00
ACCM: 00 B0B0B0B0 B00000B0
N2.C0.D0.R1.S01: RdPtrOffsetTxDq: 07
N4.C2.D1.R0.S00: Total Delay in PI ticks: TxDQS = 1015, TxDQ = 977
N6.C2.D1.R1: CheckMCTest: passed
N0.C2.D1.R1: CheckMCTest: result = 0x3FE00
N2.C0.D0.R1.S02: RdPtrOffsetTxDq: 07
N4.C2.D1.R0.S01: Total Delay in PI ticks: TxDQS = 1001, TxDQ = 962
N6.C2.D1.R1: CheckMCTest: passed
ACCM: F0 F0F0F0F0 F0F0F0F0
N2.C0.D0.R1.S03: RdPtrOffsetTxDq: 07
N4.C2.D1.R0.S02: Total Delay in PI ticks: TxDQS = 991, TxDQ = 954
N6.C2.D1.R1.S09: Offset Found: RdPtrOffsetDqs = 007
ACCM: F0 F0F0F0F0 F0F0F0F0
N2.C0.D0.R1.S04: RdPtrOffsetTxDq: 06
N4.C2.D1.R0.S03: Total Delay in PI ticks: TxDQS = 975, TxDQ = 939
N6.C2.D1.R1.S10: Offset Found: RdPtrOffsetDqs = 007
ACCM: 00 F0F0F0F0 F00000F0
N2.C0.D0.R1.S05: RdPtrOffsetTxDq: 07
N4.C2.D1.R0.S04: Total Delay in PI ticks: TxDQS = 933, TxDQ = 896
N6.C2.D1.R1.S11: Offset Found: RdPtrOffsetDqs = 007
ACCM: 00 F0F0F0F0 F00000F0
N2.C0.D0.R1.S06: RdPtrOffsetTxDq: 07
N4.C2.D1.R0.S05: Total Delay in PI ticks: TxDQS = 961, TxDQ = 923
N6.C2.D1.R1.S12: Offset Found: RdPtrOffsetDqs = 007
N0.C2.D1.R1: CheckMCTest: result = 0x3FE00
N2.C0.D0.R1.S07: RdPtrOffsetTxDq: 07
N4.C2.D1.R0.S06: Total Delay in PI ticks: TxDQS = 961, TxDQ = 921
N6.C2.D1.R1.S13: Offset Found: RdPtrOffsetDqs = 006
N0.C2.D1.R1: CheckMCTest: passed
N2.C0.D0.R1.S08: RdPtrOffsetTxDq: 07
N4.C2.D1.R0.S07: Total Delay in PI ticks: TxDQS = 981, TxDQ = 942
N6.C2.D1.R1.S14: Offset Found: RdPtrOffsetDqs = 006
N0.C2.D1.R1: CheckMCTest: passed
N2.C0.D0.R1.S09: RdPtrOffsetTxDq: 08
N4.C2.D1.R0.S08: Total Delay in PI ticks: TxDQS = 949, TxDQ = 910
N6.C2.D1.R1.S15: Offset Found: RdPtrOffsetDqs = 006
N0.C2.D1.R1.S09: Offset Found: RdPtrOffsetDqs = 007
N2.C0.D0.R1.S10: RdPtrOffsetTxDq: 07
N4.C2.D1.R0.S09: Total Delay in PI ticks: TxDQS = 1016, TxDQ = 979
N6.C2.D1.R1.S16: Offset Found: RdPtrOffsetDqs = 007
N0.C2.D1.R1.S10: Offset Found: RdPtrOffsetDqs = 007
N2.C0.D0.R1.S11: RdPtrOffsetTxDq: 07
N4.C2.D1.R0.S10: Total Delay in PI ticks: TxDQS = 1001, TxDQ = 960
N6.C2.D1.R1.S17: Offset Found: RdPtrOffsetDqs = 006
N0.C2.D1.R1.S11: Offset Found: RdPtrOffsetDqs = 007
N2.C0.D0.R1.S12: RdPtrOffsetTxDq: 07
N4.C2.D1.R0.S11: Total Delay in PI ticks: TxDQS = 992, TxDQ = 956
N6.C2: Calculating Optimimum DQS Values
N0.C2.D1.R1.S12: Offset Found: RdPtrOffsetDqs = 007
N2.C0.D0.R1.S13: RdPtrOffsetTxDq: 06
N4.C2.D1.R0.S12: Total Delay in PI ticks: TxDQS = 976, TxDQ = 938
N6.C2.D0.R0.S00: Total Delay in PI ticks: TxDQS = 1007, TxDQ = 975
N0.C2.D1.R1.S13: Offset Found: RdPtrOffsetDqs = 006
N2.C0.D0.R1.S14: RdPtrOffsetTxDq: 07
N4.C2.D1.R0.S13: Total Delay in PI ticks: TxDQS = 934, TxDQ = 898
N6.C2.D0.R0.S01: Total Delay in PI ticks: TxDQS = 993, TxDQ = 959
N0.C2.D1.R1.S14: Offset Found: RdPtrOffsetDqs = 007
N2.C0.D0.R1.S15: RdPtrOffsetTxDq: 07
N4.C2.D1.R0.S14: Total Delay in PI ticks: TxDQS = 960, TxDQ = 920
N6.C2.D0.R0.S02: Total Delay in PI ticks: TxDQS = 985, TxDQ = 952
N0.C2.D1.R1.S15: Offset Found: RdPtrOffsetDqs = 006
N2.C0.D0.R1.S16: RdPtrOffsetTxDq: 07
N4.C2.D1.R0.S15: Total Delay in PI ticks: TxDQS = 961, TxDQ = 922
N6.C2.D0.R0.S03: Total Delay in PI ticks: TxDQS = 963, TxDQ = 930
N0.C2.D1.R1.S16: Offset Found: RdPtrOffsetDqs = 007
N2.C0.D0.R1.S17: RdPtrOffsetTxDq: 07
N4.C2.D1.R0.S16: Total Delay in PI ticks: TxDQS = 981, TxDQ = 944
N6.C2.D0.R0.S04: Total Delay in PI ticks: TxDQS = 925, TxDQ = 895
N0.C2.D1.R1.S17: Offset Found: RdPtrOffsetDqs = 006
N2.C0.D0.R1.S00: Total Delay in PI ticks: TxDQ = 977
N4.C2.D1.R0.S17: Total Delay in PI ticks: TxDQS = 949, TxDQ = 911
N6.C2.D0.R0.S05: Total Delay in PI ticks: TxDQS = 953, TxDQ = 918
N0.C2: Calculating Optimimum DQS Values
N2.C0.D0.R1.S01: Total Delay in PI ticks: TxDQ = 953
N4.C2.D1.R1.S00: Total Delay in PI ticks: TxDQS = 1011, TxDQ = 974
N6.C2.D0.R0.S06: Total Delay in PI ticks: TxDQS = 953, TxDQ = 919
N0.C2.D0.R0.S00: Total Delay in PI ticks: TxDQS = 1013, TxDQ = 980
N2.C0.D0.R1.S02: Total Delay in PI ticks: TxDQ = 940
N4.C2.D1.R1.S01: Total Delay in PI ticks: TxDQS = 998, TxDQ = 959
N6.C2.D0.R0.S07: Total Delay in PI ticks: TxDQS = 975, TxDQ = 939
N0.C2.D0.R0.S01: Total Delay in PI ticks: TxDQS = 998, TxDQ = 963
N2.C0.D0.R1.S03: Total Delay in PI ticks: TxDQ = 924
N4.C2.D1.R1.S02: Total Delay in PI ticks: TxDQS = 987, TxDQ = 950
N6.C2.D0.R0.S08: Total Delay in PI ticks: TxDQS = 944, TxDQ = 908
N0.C2.D0.R0.S02: Total Delay in PI ticks: TxDQS = 987, TxDQ = 953
N2.C0.D0.R1.S04: Total Delay in PI ticks: TxDQ = 891
N4.C2.D1.R1.S03: Total Delay in PI ticks: TxDQS = 973, TxDQ = 937
N6.C2.D0.R0.S09: Total Delay in PI ticks: TxDQS = 1008, TxDQ = 975
N0.C2.D0.R0.S03: Total Delay in PI ticks: TxDQS = 971, TxDQ = 936
N2.C0.D0.R1.S05: Total Delay in PI ticks: TxDQ = 908
N4.C2.D1.R1.S04: Total Delay in PI ticks: TxDQS = 930, TxDQ = 893
N6.C2.D0.R0.S10: Total Delay in PI ticks: TxDQS = 993, TxDQ = 961
N0.C2.D0.R0.S04: Total Delay in PI ticks: TxDQS = 932, TxDQ = 899
N2.C0.D0.R1.S06: Total Delay in PI ticks: TxDQ = 915
N4.C2.D1.R1.S05: Total Delay in PI ticks: TxDQS = 959, TxDQ = 921
N6.C2.D0.R0.S11: Total Delay in PI ticks: TxDQS = 985, TxDQ = 953
N0.C2.D0.R0.S05: Total Delay in PI ticks: TxDQS = 960, TxDQ = 925
N2.C0.D0.R1.S07: Total Delay in PI ticks: TxDQ = 928
N4.C2.D1.R1.S06: Total Delay in PI ticks: TxDQS = 954, TxDQ = 914
N6.C2.D0.R0.S12: Total Delay in PI ticks: TxDQS = 964, TxDQ = 931
N0.C2.D0.R0.S06: Total Delay in PI ticks: TxDQS = 959, TxDQ = 924
N2.C0.D0.R1.S08: Total Delay in PI ticks: TxDQ = 904
N4.C2.D1.R1.S07: Total Delay in PI ticks: TxDQS = 978, TxDQ = 939
N6.C2.D0.R0.S13: Total Delay in PI ticks: TxDQS = 925, TxDQ = 892
N0.C2.D0.R0.S07: Total Delay in PI ticks: TxDQS = 978, TxDQ = 944
N2.C0.D0.R1.S09: Total Delay in PI ticks: TxDQ = 971
N4.C2.D1.R1.S08: Total Delay in PI ticks: TxDQS = 945, TxDQ = 905
N6.C2.D0.R0.S14: Total Delay in PI ticks: TxDQS = 952, TxDQ = 918
N0.C2.D0.R0.S08: Total Delay in PI ticks: TxDQS = 952, TxDQ = 919
N2.C0.D0.R1.S10: Total Delay in PI ticks: TxDQ = 952
N4.C2.D1.R1.S09: Total Delay in PI ticks: TxDQS = 1010, TxDQ = 973
N6.C2.D0.R0.S15: Total Delay in PI ticks: TxDQS = 953, TxDQ = 920
N0.C2.D0.R0.S09: Total Delay in PI ticks: TxDQS = 1015, TxDQ = 984
N2.C0.D0.R1.S11: Total Delay in PI ticks: TxDQ = 943
N4.C2.D1.R1.S10: Total Delay in PI ticks: TxDQS = 1000, TxDQ = 959
N6.C2.D0.R0.S16: Total Delay in PI ticks: TxDQS = 974, TxDQ = 940
N0.C2.D0.R0.S10: Total Delay in PI ticks: TxDQS = 1001, TxDQ = 968
N2.C0.D0.R1.S12: Total Delay in PI ticks: TxDQ = 928
N4.C2.D1.R1.S11: Total Delay in PI ticks: TxDQS = 987, TxDQ = 951
N6.C2.D0.R0.S17: Total Delay in PI ticks: TxDQS = 944, TxDQ = 913
N0.C2.D0.R0.S11: Total Delay in PI ticks: TxDQS = 990, TxDQ = 957
N2.C0.D0.R1.S13: Total Delay in PI ticks: TxDQ = 893
N4.C2.D1.R1.S12: Total Delay in PI ticks: TxDQS = 973, TxDQ = 936
N6.C2.D0.R1.S00: Total Delay in PI ticks: TxDQS = 1000, TxDQ = 970
N0.C2.D0.R0.S12: Total Delay in PI ticks: TxDQS = 970, TxDQ = 937
N2.C0.D0.R1.S14: Total Delay in PI ticks: TxDQ = 910
N4.C2.D1.R1.S13: Total Delay in PI ticks: TxDQS = 930, TxDQ = 894
N6.C2.D0.R1.S01: Total Delay in PI ticks: TxDQS = 985, TxDQ = 951
N0.C2.D0.R0.S13: Total Delay in PI ticks: TxDQS = 929, TxDQ = 896
N2.C0.D0.R1.S15: Total Delay in PI ticks: TxDQ = 913
N4.C2.D1.R1.S14: Total Delay in PI ticks: TxDQS = 959, TxDQ = 919
N6.C2.D0.R1.S02: Total Delay in PI ticks: TxDQS = 976, TxDQ = 943
N0.C2.D0.R0.S14: Total Delay in PI ticks: TxDQS = 958, TxDQ = 924
N2.C0.D0.R1.S16: Total Delay in PI ticks: TxDQ = 928
N4.C2.D1.R1.S15: Total Delay in PI ticks: TxDQS = 959, TxDQ = 920
N6.C2.D0.R1.S03: Total Delay in PI ticks: TxDQS = 957, TxDQ = 923
N0.C2.D0.R0.S15: Total Delay in PI ticks: TxDQS = 960, TxDQ = 926
N2.C0.D0.R1.S17: Total Delay in PI ticks: TxDQ = 903
N4.C2.D1.R1.S16: Total Delay in PI ticks: TxDQS = 977, TxDQ = 940
N6.C2.D0.R1.S04: Total Delay in PI ticks: TxDQS = 918, TxDQ = 887
N0.C2.D0.R0.S16: Total Delay in PI ticks: TxDQS = 979, TxDQ = 946
N2.C0.D1.R0.S00: wrcmd2dqsstartlatency: 04
N4.C2.D1.R1.S17: Total Delay in PI ticks: TxDQS = 943, TxDQ = 906
N6.C2.D0.R1.S05: Total Delay in PI ticks: TxDQS = 948, TxDQ = 913
N0.C2.D0.R0.S17: Total Delay in PI ticks: TxDQS = 951, TxDQ = 916
N2.C0.D1.R0.S00: RdPtrOffsetTxDq: 06
N4.C3.D0.R0: Write Training Coarse, lower nibbles / bytes
N6.C2.D0.R1.S06: Total Delay in PI ticks: TxDQS = 945, TxDQ = 911
N0.C2.D0.R1.S00: Total Delay in PI ticks: TxDQS = 1006, TxDQ = 973
N2.C0.D1.R0.S00: RdPtrOffsetTxDqs: 07
N4.C3.D0.R0.S00: Dq Delay estimate: 347
N6.C2.D0.R1.S07: Total Delay in PI ticks: TxDQS = 969, TxDQ = 934
N0.C2.D0.R1.S01: Total Delay in PI ticks: TxDQS = 993, TxDQ = 958
N2.C0.D1.R0.S00: PiTxDqs: 56
N4.C3.D0.R0.S01: Dq Delay estimate: 455
N6.C2.D0.R1.S08: Total Delay in PI ticks: TxDQS = 936, TxDQ = 900
N0.C2.D0.R1.S02: Total Delay in PI ticks: TxDQS = 983, TxDQ = 950
N2.C0.D1.R0.S01: wrcmd2dqsstartlatency: 04
N4.C3.D0.R0.S02: Dq Delay estimate: 451
N6.C2.D0.R1.S09: Total Delay in PI ticks: TxDQS = 999, TxDQ = 966
N0.C2.D0.R1.S03: Total Delay in PI ticks: TxDQS = 966, TxDQ = 932
N2.C0.D1.R0.S01: RdPtrOffsetTxDq: 06
N4.C3.D0.R0.S03: Dq Delay estimate: 433
N6.C2.D0.R1.S10: Total Delay in PI ticks: TxDQS = 986, TxDQ = 953
N0.C2.D0.R1.S04: Total Delay in PI ticks: TxDQS = 926, TxDQ = 893
N2.C0.D1.R0.S01: RdPtrOffsetTxDqs: 07
N4.C3.D0.R0.S04: Dq Delay estimate: 394
N6.C2.D0.R1.S11: Total Delay in PI ticks: TxDQS = 977, TxDQ = 945
N0.C2.D0.R1.S05: Total Delay in PI ticks: TxDQS = 956, TxDQ = 921
N2.C0.D1.R0.S01: PiTxDqs: 38
N4.C3.D0.R0.S05: Dq Delay estimate: 409
N6.C2.D0.R1.S12: Total Delay in PI ticks: TxDQS = 960, TxDQ = 927
N0.C2.D0.R1.S06: Total Delay in PI ticks: TxDQS = 951, TxDQ = 916
N2.C0.D1.R0.S02: wrcmd2dqsstartlatency: 04
N4.C3.D0.R0.S06: Dq Delay estimate: 422
N6.C2.D0.R1.S13: Total Delay in PI ticks: TxDQS = 918, TxDQ = 887
N0.C2.D0.R1.S07: Total Delay in PI ticks: TxDQS = 974, TxDQ = 940
N2.C0.D1.R0.S02: RdPtrOffsetTxDq: 05
N4.C3.D0.R0.S07: Dq Delay estimate: 442
N6.C2.D0.R1.S14: Total Delay in PI ticks: TxDQS = 949, TxDQ = 916
N0.C2.D0.R1.S08: Total Delay in PI ticks: TxDQS = 944, TxDQ = 911
N2.C0.D1.R0.S02: RdPtrOffsetTxDqs: 07
N4.C3.D0.R0.S08: Dq Delay estimate: 417
N6.C2.D0.R1.S15: Total Delay in PI ticks: TxDQS = 948, TxDQ = 915
N0.C2.D0.R1.S09: Total Delay in PI ticks: TxDQS = 1008, TxDQ = 977
N2.C0.D1.R0.S02: PiTxDqs: 26
ACCM: 0F 0F0F0F9F 0F0F0F0F
N6.C2.D0.R1.S16: Total Delay in PI ticks: TxDQS = 968, TxDQ = 934
N0.C2.D0.R1.S10: Total Delay in PI ticks: TxDQS = 993, TxDQ = 960
N2.C0.D1.R0.S03: wrcmd2dqsstartlatency: 04
ACCM: 0F 0F0F0F9F 0F0F0F0F
N6.C2.D0.R1.S17: Total Delay in PI ticks: TxDQS = 937, TxDQ = 907
N0.C2.D0.R1.S11: Total Delay in PI ticks: TxDQS = 984, TxDQ = 951
N2.C0.D1.R0.S03: RdPtrOffsetTxDq: 05
ACCM: FF FFFFFF9F FFFFFFF9
N6.C2.D1.R0.S00: Total Delay in PI ticks: TxDQS = 1015, TxDQ = 982
N0.C2.D0.R1.S12: Total Delay in PI ticks: TxDQS = 966, TxDQ = 933
N2.C0.D1.R0.S03: RdPtrOffsetTxDqs: 07
ACCM: FF FFFFFF9F FFFFFFF9
N6.C2.D1.R0.S01: Total Delay in PI ticks: TxDQS = 1000, TxDQ = 964
N0.C2.D0.R1.S13: Total Delay in PI ticks: TxDQS = 926, TxDQ = 893
N2.C0.D1.R0.S03: PiTxDqs: 10
N4.C3.D0.R0: CheckMCTest: result = 0x3FFFF
N6.C2.D1.R0.S02: Total Delay in PI ticks: TxDQS = 993, TxDQ = 958
N0.C2.D0.R1.S14: Total Delay in PI ticks: TxDQS = 953, TxDQ = 920
N2.C0.D1.R0.S04: wrcmd2dqsstartlatency: 04
ACCM: 0F 0F0F0FDF 0F0F0F0F
N6.C2.D1.R0.S03: Total Delay in PI ticks: TxDQS = 976, TxDQ = 941
N0.C2.D0.R1.S15: Total Delay in PI ticks: TxDQS = 951, TxDQ = 917
N2.C0.D1.R0.S04: RdPtrOffsetTxDq: 05
ACCM: 0F 0F0F0FDF 0F0F0F0F
N6.C2.D1.R0.S04: Total Delay in PI ticks: TxDQS = 934, TxDQ = 900
N0.C2.D0.R1.S16: Total Delay in PI ticks: TxDQS = 976, TxDQ = 942
N2.C0.D1.R0.S04: RdPtrOffsetTxDqs: 06
ACCM: FF FFFFFFDF FFFFFFFD
N6.C2.D1.R0.S05: Total Delay in PI ticks: TxDQS = 963, TxDQ = 927
N0.C2.D0.R1.S17: Total Delay in PI ticks: TxDQS = 942, TxDQ = 908
N2.C0.D1.R0.S04: PiTxDqs: 41
ACCM: FF FFFFFFDF FFFFFFFD
N6.C2.D1.R0.S06: Total Delay in PI ticks: TxDQS = 960, TxDQ = 924
N0.C2.D1.R0.S00: Total Delay in PI ticks: TxDQS = 1015, TxDQ = 980
N2.C0.D1.R0.S05: wrcmd2dqsstartlatency: 04
N4.C3.D0.R0: CheckMCTest: result = 0x3FFFF
N6.C2.D1.R0.S07: Total Delay in PI ticks: TxDQS = 985, TxDQ = 948
N0.C2.D1.R0.S01: Total Delay in PI ticks: TxDQS = 1000, TxDQ = 963
N2.C0.D1.R0.S05: RdPtrOffsetTxDq: 05
ACCM: 0F 0F0F0FDF 0F0F0F00
N6.C2.D1.R0.S08: Total Delay in PI ticks: TxDQS = 948, TxDQ = 911
N0.C2.D1.R0.S02: Total Delay in PI ticks: TxDQS = 993, TxDQ = 957
N2.C0.D1.R0.S05: RdPtrOffsetTxDqs: 06
ACCM: 0F 0F0F0FDF 0F0F0F00
N6.C2.D1.R0.S09: Total Delay in PI ticks: TxDQS = 1015, TxDQ = 979
N0.C2.D1.R0.S03: Total Delay in PI ticks: TxDQS = 977, TxDQ = 941
N2.C0.D1.R0.S05: PiTxDqs: 59
ACCM: FB FBF0FBD0 FBFBFBF0
N6.C2.D1.R0.S10: Total Delay in PI ticks: TxDQS = 1001, TxDQ = 967
N0.C2.D1.R0.S04: Total Delay in PI ticks: TxDQS = 934, TxDQ = 898
N2.C0.D1.R0.S06: wrcmd2dqsstartlatency: 04
ACCM: FB FBF0FBD0 FBFBFBF0
N6.C2.D1.R0.S11: Total Delay in PI ticks: TxDQS = 993, TxDQ = 960
N0.C2.D1.R0.S05: Total Delay in PI ticks: TxDQS = 964, TxDQ = 928
N2.C0.D1.R0.S06: RdPtrOffsetTxDq: 05
N4.C3.D0.R0: CheckMCTest: result = 0x3FFFE
N6.C2.D1.R0.S12: Total Delay in PI ticks: TxDQS = 976, TxDQ = 941
N0.C2.D1.R0.S06: Total Delay in PI ticks: TxDQS = 960, TxDQ = 923
N2.C0.D1.R0.S06: RdPtrOffsetTxDqs: 06
ACCM: 0F 0F0F0FDF 0F0F0F00
N6.C2.D1.R0.S13: Total Delay in PI ticks: TxDQS = 934, TxDQ = 900
N0.C2.D1.R0.S07: Total Delay in PI ticks: TxDQS = 982, TxDQ = 947
N2.C0.D1.R0.S06: PiTxDqs: 61
ACCM: 0F 0F0F0FDF 0F0F0F00
N6.C2.D1.R0.S14: Total Delay in PI ticks: TxDQS = 963, TxDQ = 928
N0.C2.D1.R0.S08: Total Delay in PI ticks: TxDQS = 951, TxDQ = 915
N2.C0.D1.R0.S07: wrcmd2dqsstartlatency: 04
ACCM: FF FFF0FFD0 FFFFFFF0
N6.C2.D1.R0.S15: Total Delay in PI ticks: TxDQS = 960, TxDQ = 926
N0.C2.D1.R0.S09: Total Delay in PI ticks: TxDQS = 1013, TxDQ = 979
N2.C0.D1.R0.S07: RdPtrOffsetTxDq: 05
ACCM: FF FFF0FFD0 FFFFFFF0
N6.C2.D1.R0.S16: Total Delay in PI ticks: TxDQS = 983, TxDQ = 947
N0.C2.D1.R0.S10: Total Delay in PI ticks: TxDQS = 1003, TxDQ = 968
N2.C0.D1.R0.S07: RdPtrOffsetTxDqs: 07
N4.C3.D0.R0: CheckMCTest: result = 0x3FFFE
N6.C2.D1.R0.S17: Total Delay in PI ticks: TxDQS = 951, TxDQ = 917
N0.C2.D1.R0.S11: Total Delay in PI ticks: TxDQS = 992, TxDQ = 958
N2.C0.D1.R0.S07: PiTxDqs: 14
N4.C3.D0.R0.S00: Offset Found: RdPtrOffsetDqs = 008
N6.C2.D1.R1.S00: Total Delay in PI ticks: TxDQS = 1010, TxDQ = 977
N0.C2.D1.R0.S12: Total Delay in PI ticks: TxDQS = 974, TxDQ = 938
N2.C0.D1.R0.S08: wrcmd2dqsstartlatency: 04
ACCM: 00 000000D0 00000000
N6.C2.D1.R1.S01: Total Delay in PI ticks: TxDQS = 995, TxDQ = 959
N0.C2.D1.R0.S13: Total Delay in PI ticks: TxDQS = 935, TxDQ = 900
N2.C0.D1.R0.S08: RdPtrOffsetTxDq: 05
ACCM: 00 000000D0 00000000
N6.C2.D1.R1.S02: Total Delay in PI ticks: TxDQS = 987, TxDQ = 952
N0.C2.D1.R0.S14: Total Delay in PI ticks: TxDQS = 961, TxDQ = 926
N2.C0.D1.R0.S08: RdPtrOffsetTxDqs: 06
ACCM: F0 F0F0F0D0 F0F0F0F0
N6.C2.D1.R1.S03: Total Delay in PI ticks: TxDQS = 970, TxDQ = 934
N0.C2.D1.R0.S15: Total Delay in PI ticks: TxDQS = 963, TxDQ = 927
N2.C0.D1.R0.S08: PiTxDqs: 48
ACCM: F0 F0F0F0D0 F0F0F0F0
N6.C2.D1.R1.S04: Total Delay in PI ticks: TxDQS = 929, TxDQ = 895
N0.C2.D1.R0.S16: Total Delay in PI ticks: TxDQS = 982, TxDQ = 947
N2.C0.D1.R0.S09: wrcmd2dqsstartlatency: 04
N4.C3.D0.R0: CheckMCTest: result = 0x3FE00
N6.C2.D1.R1.S05: Total Delay in PI ticks: TxDQS = 960, TxDQ = 924
N0.C2.D1.R0.S17: Total Delay in PI ticks: TxDQS = 951, TxDQ = 915
N2.C0.D1.R0.S09: RdPtrOffsetTxDq: 06
ACCM: 00 000000D0 00000000
N6.C2.D1.R1.S06: Total Delay in PI ticks: TxDQS = 955, TxDQ = 919
N0.C2.D1.R1.S00: Total Delay in PI ticks: TxDQS = 1011, TxDQ = 976
N2.C0.D1.R0.S09: RdPtrOffsetTxDqs: 07
ACCM: 00 000000D0 00000000
N6.C2.D1.R1.S07: Total Delay in PI ticks: TxDQS = 981, TxDQ = 944
N0.C2.D1.R1.S01: Total Delay in PI ticks: TxDQS = 998, TxDQ = 961
N2.C0.D1.R0.S09: PiTxDqs: 57
ACCM: F0 F0F0F0D0 F0F0F0F0
N6.C2.D1.R1.S08: Total Delay in PI ticks: TxDQS = 944, TxDQ = 907
N0.C2.D1.R1.S02: Total Delay in PI ticks: TxDQS = 988, TxDQ = 952
N2.C0.D1.R0.S10: wrcmd2dqsstartlatency: 04
ACCM: F0 F0F0F0D0 F0F0F0F0
N6.C2.D1.R1.S09: Total Delay in PI ticks: TxDQS = 1008, TxDQ = 972
N0.C2.D1.R1.S03: Total Delay in PI ticks: TxDQS = 972, TxDQ = 936
N2.C0.D1.R0.S10: RdPtrOffsetTxDq: 06
N4.C3.D0.R0: CheckMCTest: result = 0x3FE00
N6.C2.D1.R1.S10: Total Delay in PI ticks: TxDQS = 995, TxDQ = 961
N0.C2.D1.R1.S04: Total Delay in PI ticks: TxDQS = 933, TxDQ = 897
N2.C0.D1.R0.S10: RdPtrOffsetTxDqs: 07
N4.C3.D0.R0.S00: Offset Found: RdPtrOffsetDqs = 008
N6.C2.D1.R1.S11: Total Delay in PI ticks: TxDQS = 989, TxDQ = 955
N0.C2.D1.R1.S05: Total Delay in PI ticks: TxDQS = 961, TxDQ = 926
N2.C0.D1.R0.S10: PiTxDqs: 37
N4.C3.D0.R0.S01: Offset Found: RdPtrOffsetDqs = 007
N6.C2.D1.R1.S12: Total Delay in PI ticks: TxDQS = 975, TxDQ = 940
N0.C2.D1.R1.S06: Total Delay in PI ticks: TxDQS = 956, TxDQ = 920
N2.C0.D1.R0.S11: wrcmd2dqsstartlatency: 04
N4.C3.D0.R0.S02: Offset Found: RdPtrOffsetDqs = 007
N6.C2.D1.R1.S13: Total Delay in PI ticks: TxDQS = 930, TxDQ = 896
N0.C2.D1.R1.S07: Total Delay in PI ticks: TxDQS = 978, TxDQ = 942
N2.C0.D1.R0.S11: RdPtrOffsetTxDq: 05
N4.C3.D0.R0.S03: Offset Found: RdPtrOffsetDqs = 007
N6.C2.D1.R1.S14: Total Delay in PI ticks: TxDQS = 958, TxDQ = 923
N0.C2.D1.R1.S08: Total Delay in PI ticks: TxDQS = 944, TxDQ = 908
N2.C0.D1.R0.S11: RdPtrOffsetTxDqs: 07
N4.C3.D0.R0.S04: Offset Found: RdPtrOffsetDqs = 006
N6.C2.D1.R1.S15: Total Delay in PI ticks: TxDQS = 958, TxDQ = 924
N0.C2.D1.R1.S09: Total Delay in PI ticks: TxDQS = 1011, TxDQ = 977
N2.C0.D1.R0.S11: PiTxDqs: 29
N4.C3.D0.R0.S05: Offset Found: RdPtrOffsetDqs = 006
N6.C2.D1.R1.S16: Total Delay in PI ticks: TxDQS = 981, TxDQ = 945
N0.C2.D1.R1.S10: Total Delay in PI ticks: TxDQS = 1000, TxDQ = 964
N2.C0.D1.R0.S12: wrcmd2dqsstartlatency: 04
N4.C3.D0.R0.S06: Offset Found: RdPtrOffsetDqs = 007
N6.C2.D1.R1.S17: Total Delay in PI ticks: TxDQS = 944, TxDQ = 910
N0.C2.D1.R1.S11: Total Delay in PI ticks: TxDQS = 991, TxDQ = 957
N2.C0.D1.R0.S12: RdPtrOffsetTxDq: 05
N4.C3.D0.R0.S07: Offset Found: RdPtrOffsetDqs = 007
N6.C3.D0.R0: Write Training Coarse, lower nibbles / bytes
N0.C2.D1.R1.S12: Total Delay in PI ticks: TxDQS = 974, TxDQ = 938
N2.C0.D1.R0.S12: RdPtrOffsetTxDqs: 07
N4.C3.D0.R0.S08: Offset Found: RdPtrOffsetDqs = 007
N6.C3.D0.R0.S00: Dq Delay estimate: 475
N0.C2.D1.R1.S13: Total Delay in PI ticks: TxDQS = 934, TxDQ = 899
N2.C0.D1.R0.S12: PiTxDqs: 13
N4.C3.D0.R0: Write Training Coarse, upper nibbles
N6.C3.D0.R0.S01: Dq Delay estimate: 457
N0.C2.D1.R1.S14: Total Delay in PI ticks: TxDQS = 960, TxDQ = 925
N2.C0.D1.R0.S13: wrcmd2dqsstartlatency: 04
N4.C3.D0.R0.S09: Dq Delay estimate: 346
N6.C3.D0.R0.S02: Dq Delay estimate: 450
N0.C2.D1.R1.S15: Total Delay in PI ticks: TxDQS = 958, TxDQ = 922
N2.C0.D1.R0.S13: RdPtrOffsetTxDq: 05
N4.C3.D0.R0.S10: Dq Delay estimate: 457
N6.C3.D0.R0.S03: Dq Delay estimate: 434
N0.C2.D1.R1.S16: Total Delay in PI ticks: TxDQS = 983, TxDQ = 947
N2.C0.D1.R0.S13: RdPtrOffsetTxDqs: 06
N4.C3.D0.R0.S11: Dq Delay estimate: 449
N6.C3.D0.R0.S04: Dq Delay estimate: 393
N0.C2.D1.R1.S17: Total Delay in PI ticks: TxDQS = 945, TxDQ = 909
N2.C0.D1.R0.S13: PiTxDqs: 42
N4.C3.D0.R0.S12: Dq Delay estimate: 433
N6.C3.D0.R0.S05: Dq Delay estimate: 408
N0.C3.D0.R0: Write Training Coarse, lower nibbles / bytes
N2.C0.D1.R0.S14: wrcmd2dqsstartlatency: 04
N4.C3.D0.R0.S13: Dq Delay estimate: 397
N6.C3.D0.R0.S06: Dq Delay estimate: 425
N0.C3.D0.R0.S00: Dq Delay estimate: 352
N2.C0.D1.R0.S14: RdPtrOffsetTxDq: 05
N4.C3.D0.R0.S14: Dq Delay estimate: 408
N6.C3.D0.R0.S07: Dq Delay estimate: 439
N0.C3.D0.R0.S01: Dq Delay estimate: 463
N2.C0.D1.R0.S14: RdPtrOffsetTxDqs: 06
N4.C3.D0.R0.S15: Dq Delay estimate: 425
N6.C3.D0.R0.S08: Dq Delay estimate: 415
N0.C3.D0.R0.S02: Dq Delay estimate: 453
N2.C0.D1.R0.S14: PiTxDqs: 60
N4.C3.D0.R0.S16: Dq Delay estimate: 443
ACCM: 9F 0F0F9F9F 0F0F0F0F
N0.C3.D0.R0.S03: Dq Delay estimate: 433
N2.C0.D1.R0.S15: wrcmd2dqsstartlatency: 04
N4.C3.D0.R0.S17: Dq Delay estimate: 413
ACCM: 9F 0F0F9F9F 0F0F0F0F
N0.C3.D0.R0.S04: Dq Delay estimate: 401
N2.C0.D1.R0.S15: RdPtrOffsetTxDq: 05
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: 9F FFFF9F9F FFFFFFFF
N0.C3.D0.R0.S05: Dq Delay estimate: 415
N2.C0.D1.R0.S15: RdPtrOffsetTxDqs: 06
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: 9F FFFF9F9F FFFFFFFF
N0.C3.D0.R0.S06: Dq Delay estimate: 429
N2.C0.D1.R0.S15: PiTxDqs: 62
ACCM: F0 F0F0F0F0 F0F0F0B0
N6.C3.D0.R0: CheckMCTest: result = 0x3FFFF
N0.C3.D0.R0.S07: Dq Delay estimate: 449
N2.C0.D1.R0.S16: wrcmd2dqsstartlatency: 04
ACCM: F0 F0F0F0F0 F0F0F0B0
ACCM: DF 0F0FDFDF 0F0F0F0F
N0.C3.D0.R0.S08: Dq Delay estimate: 418
N2.C0.D1.R0.S16: RdPtrOffsetTxDq: 05
N4.C3.D0.R0: CheckMCTest: result = 0x3FE00
ACCM: DF 0F0FDFDF 0F0F0F0F
ACCM: 0F 0F0F0F9F 0F0F0F0F
N2.C0.D1.R0.S16: RdPtrOffsetTxDqs: 07
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: DF FFFFDFDF FFFFFFFF
ACCM: 0F 0F0F0F9F 0F0F0F0F
N2.C0.D1.R0.S16: PiTxDqs: 14
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: DF FFFFDFDF FFFFFFFF
ACCM: FF FFFFFF9F FFFFFFF9
N2.C0.D1.R0.S17: wrcmd2dqsstartlatency: 04
ACCM: F0 F0F0F0F0 F0F0F0F0
N6.C3.D0.R0: CheckMCTest: result = 0x3FFFF
ACCM: FF FFFFFF9F FFFFFFF9
N2.C0.D1.R0.S17: RdPtrOffsetTxDq: 05
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: DF 0F0FDFDF 0F0F0F0F
N0.C3.D0.R0: CheckMCTest: result = 0x3FFFF
N2.C0.D1.R0.S17: RdPtrOffsetTxDqs: 06
N4.C3.D0.R0: CheckMCTest: result = 0x3FE00
ACCM: DF 0F0FDFDF 0F0F0F0F
ACCM: 0F 0F0F0FDF 0F0F0F0F
N2.C0.D1.R0.S17: PiTxDqs: 50
ACCM: F0 F0F0F0F0 F0F0F000
ACCM: D0 FBFBDBDB FBFBFBFB
ACCM: 0F 0F0F0FDF 0F0F0F0F
N2.C0.D1.R0.S00: RdPtrOffsetTxDq: 07
ACCM: F0 F0F0F0F0 F0F0F000
ACCM: D0 FBFBDBDB FBFBFBFB
ACCM: FF FFFFFFDF FFFFFFFD
N2.C0.D1.R0.S01: RdPtrOffsetTxDq: 07
ACCM: B0 0000B0B0 B000B000
N6.C3.D0.R0: CheckMCTest: result = 0x3FFFF
ACCM: FF FFFFFFDF FFFFFFFD
N2.C0.D1.R0.S02: RdPtrOffsetTxDq: 06
ACCM: B0 0000B0B0 B000B000
ACCM: DF 0F0FDFDF 0F0F0F0F
N0.C3.D0.R0: CheckMCTest: result = 0x3FFFF
N2.C0.D1.R0.S03: RdPtrOffsetTxDq: 06
N4.C3.D0.R0: CheckMCTest: result = 0x3FC00
ACCM: DF 0F0FDFDF 0F0F0F0F
ACCM: 0F 0F0F0FDF 0F0F0F00
N2.C0.D1.R0.S04: RdPtrOffsetTxDq: 06
ACCM: F0 F0F0F0F0 F0F0F000
ACCM: D0 FFFFDFDF FFFFFFFF
ACCM: 0F 0F0F0FDF 0F0F0F00
N2.C0.D1.R0.S05: RdPtrOffsetTxDq: 06
ACCM: F0 F0F0F0F0 F0F0F000
ACCM: D0 FFFFDFDF FFFFFFFF
ACCM: F0 FBF0FBDB F0F0FBF0
N2.C0.D1.R0.S06: RdPtrOffsetTxDq: 06
ACCM: F0 0000F0F0 B000F000
N6.C3.D0.R0: CheckMCTest: result = 0x3FFFF
ACCM: F0 FBF0FBDB F0F0FBF0
N2.C0.D1.R0.S07: RdPtrOffsetTxDq: 06
ACCM: F0 0000F0F0 B000F000
ACCM: D0 0000D0D0 00000000
N0.C3.D0.R0: CheckMCTest: result = 0x3FFFE
N2.C0.D1.R0.S08: RdPtrOffsetTxDq: 06
N4.C3.D0.R0: CheckMCTest: result = 0x3FC00
ACCM: D0 0000D0D0 00000000
ACCM: 0F 0F0F0FDF 0F0F0F00
N2.C0.D1.R0.S09: RdPtrOffsetTxDq: 07
N4.C3.D0.R0.S09: Offset Found: RdPtrOffsetDqs = 008
ACCM: D0 F0F0D0D0 F0F0F0F0
ACCM: 0F 0F0F0FDF 0F0F0F00
N2.C0.D1.R0.S10: RdPtrOffsetTxDq: 07
N4.C3.D0.R0: CheckMCTest: passed
ACCM: D0 F0F0D0D0 F0F0F0F0
ACCM: F0 FFF0FFDF F0F0FFF0
N2.C0.D1.R0.S11: RdPtrOffsetTxDq: 06
N4.C3.D0.R0: CheckMCTest: passed
N6.C3.D0.R0: CheckMCTest: result = 0x3FE00
ACCM: F0 FFF0FFDF F0F0FFF0
N2.C0.D1.R0.S12: RdPtrOffsetTxDq: 06
N4.C3.D0.R0.S09: Offset Found: RdPtrOffsetDqs = 008
ACCM: D0 0000D0D0 00000000
N0.C3.D0.R0: CheckMCTest: result = 0x3FFFE
N2.C0.D1.R0.S13: RdPtrOffsetTxDq: 06
N4.C3.D0.R0.S10: Offset Found: RdPtrOffsetDqs = 007
ACCM: D0 0000D0D0 00000000
N0.C3.D0.R0.S00: Offset Found: RdPtrOffsetDqs = 008
N2.C0.D1.R0.S14: RdPtrOffsetTxDq: 06
N4.C3.D0.R0.S11: Offset Found: RdPtrOffsetDqs = 007
ACCM: D0 F0F0D0D0 F0F0F0F0
ACCM: 00 000000D0 00000000
N2.C0.D1.R0.S15: RdPtrOffsetTxDq: 06
N4.C3.D0.R0.S12: Offset Found: RdPtrOffsetDqs = 007
ACCM: D0 F0F0D0D0 F0F0F0F0
ACCM: 00 000000D0 00000000
N2.C0.D1.R0.S16: RdPtrOffsetTxDq: 06
N4.C3.D0.R0.S13: Offset Found: RdPtrOffsetDqs = 006
N6.C3.D0.R0: CheckMCTest: result = 0x3FE00
ACCM: F0 F0F0F0D0 F0F0F0F0
N2.C0.D1.R0.S17: RdPtrOffsetTxDq: 06
N4.C3.D0.R0.S14: Offset Found: RdPtrOffsetDqs = 006
N6.C3.D0.R0.S00: Offset Found: RdPtrOffsetDqs = 007
ACCM: F0 F0F0F0D0 F0F0F0F0
N2.C0.D1.R0.S00: RdPtrOffsetTxDq: 08
N4.C3.D0.R0.S15: Offset Found: RdPtrOffsetDqs = 007
N6.C3.D0.R0.S01: Offset Found: RdPtrOffsetDqs = 007
N0.C3.D0.R0: CheckMCTest: result = 0x3FE00
N2.C0.D1.R0.S01: RdPtrOffsetTxDq: 08
N4.C3.D0.R0.S16: Offset Found: RdPtrOffsetDqs = 007
N6.C3.D0.R0.S02: Offset Found: RdPtrOffsetDqs = 007
ACCM: 00 000000D0 00000000
N2.C0.D1.R0.S02: RdPtrOffsetTxDq: 07
N4.C3.D0.R0.S17: Offset Found: RdPtrOffsetDqs = 007
N6.C3.D0.R0.S03: Offset Found: RdPtrOffsetDqs = 007
ACCM: 00 000000D0 00000000
N2.C0.D1.R0.S03: RdPtrOffsetTxDq: 07
N4.C3.D0.R1: Write Training Coarse, lower nibbles / bytes
N6.C3.D0.R0.S04: Offset Found: RdPtrOffsetDqs = 006
ACCM: F0 F0F0F0D0 F0F0F0F0
N2.C0.D1.R0.S04: RdPtrOffsetTxDq: 07
N4.C3.D0.R1.S00: Dq Delay estimate: 468
N6.C3.D0.R0.S05: Offset Found: RdPtrOffsetDqs = 006
ACCM: F0 F0F0F0D0 F0F0F0F0
N2.C0.D1.R0.S05: RdPtrOffsetTxDq: 07
N4.C3.D0.R1.S01: Dq Delay estimate: 450
N6.C3.D0.R0.S06: Offset Found: RdPtrOffsetDqs = 007
N0.C3.D0.R0: CheckMCTest: result = 0x3FE00
N2.C0.D1.R0.S06: RdPtrOffsetTxDq: 07
N4.C3.D0.R1.S02: Dq Delay estimate: 440
N6.C3.D0.R0.S07: Offset Found: RdPtrOffsetDqs = 007
N0.C3.D0.R0.S00: Offset Found: RdPtrOffsetDqs = 008
N2.C0.D1.R0.S07: RdPtrOffsetTxDq: 07
N4.C3.D0.R1.S03: Dq Delay estimate: 429
N6.C3.D0.R0.S08: Offset Found: RdPtrOffsetDqs = 007
N0.C3.D0.R0.S01: Offset Found: RdPtrOffsetDqs = 007
N2.C0.D1.R0.S08: RdPtrOffsetTxDq: 07
N4.C3.D0.R1.S04: Dq Delay estimate: 387
N6.C3.D0.R0: Write Training Coarse, upper nibbles
N0.C3.D0.R0.S02: Offset Found: RdPtrOffsetDqs = 007
N2.C0.D1.R0.S09: RdPtrOffsetTxDq: 08
N4.C3.D0.R1.S05: Dq Delay estimate: 401
N6.C3.D0.R0.S09: Dq Delay estimate: 473
N0.C3.D0.R0.S03: Offset Found: RdPtrOffsetDqs = 007
N2.C0.D1.R0.S10: RdPtrOffsetTxDq: 08
N4.C3.D0.R1.S06: Dq Delay estimate: 415
N6.C3.D0.R0.S10: Dq Delay estimate: 459
N0.C3.D0.R0.S04: Offset Found: RdPtrOffsetDqs = 006
N2.C0.D1.R0.S11: RdPtrOffsetTxDq: 07
N4.C3.D0.R1.S07: Dq Delay estimate: 436
N6.C3.D0.R0.S11: Dq Delay estimate: 448
N0.C3.D0.R0.S05: Offset Found: RdPtrOffsetDqs = 007
N2.C0.D1.R0.S12: RdPtrOffsetTxDq: 07
N4.C3.D0.R1.S08: Dq Delay estimate: 407
N6.C3.D0.R0.S12: Dq Delay estimate: 430
N0.C3.D0.R0.S06: Offset Found: RdPtrOffsetDqs = 007
N2.C0.D1.R0.S13: RdPtrOffsetTxDq: 07
ACCM: 0F 0F0F0F0F 0F0F0F0F
N6.C3.D0.R0.S13: Dq Delay estimate: 395
N0.C3.D0.R0.S07: Offset Found: RdPtrOffsetDqs = 007
N2.C0.D1.R0.S14: RdPtrOffsetTxDq: 07
ACCM: 0F 0F0F0F0F 0F0F0F0F
N6.C3.D0.R0.S14: Dq Delay estimate: 413
N0.C3.D0.R0.S08: Offset Found: RdPtrOffsetDqs = 007
N2.C0.D1.R0.S15: RdPtrOffsetTxDq: 07
ACCM: 0F 0F0F0F0F 0F0F0F0F
N6.C3.D0.R0.S15: Dq Delay estimate: 426
N0.C3.D0.R0: Write Training Coarse, upper nibbles
N2.C0.D1.R0.S16: RdPtrOffsetTxDq: 07
ACCM: 0F 0F0F0F0F 0F0F0F0F
N6.C3.D0.R0.S16: Dq Delay estimate: 442
N0.C3.D0.R0.S09: Dq Delay estimate: 349
N2.C0.D1.R0.S17: RdPtrOffsetTxDq: 07
N4.C3.D0.R1: CheckMCTest: result = 0x1FF
N6.C3.D0.R0.S17: Dq Delay estimate: 413
N0.C3.D0.R0.S10: Dq Delay estimate: 464
N2.C0.D1.R0.S00: Total Delay in PI ticks: TxDQ = 986
ACCM: 0F 0F0F0F0F 0F0F0F0F
ACCM: F0 F0F0F0F0 F0F0F0F0
N0.C3.D0.R0.S11: Dq Delay estimate: 455
N2.C0.D1.R0.S01: Total Delay in PI ticks: TxDQ = 966
ACCM: 0F 0F0F0F0F 0F0F0F0F
ACCM: F0 F0F0F0F0 F0F0F0F0
N0.C3.D0.R0.S12: Dq Delay estimate: 438
N2.C0.D1.R0.S02: Total Delay in PI ticks: TxDQ = 953
ACCM: 0F 0F0F0F0F 0F0F0F0F
ACCM: F0 F0F0F0F0 F0F0F0F0
N0.C3.D0.R0.S13: Dq Delay estimate: 400
N2.C0.D1.R0.S03: Total Delay in PI ticks: TxDQ = 938
ACCM: 0F 0F0F0F0F 0F0F0F0F
ACCM: F0 F0F0F0F0 F0F0F0F0
N0.C3.D0.R0.S14: Dq Delay estimate: 415
N2.C0.D1.R0.S04: Total Delay in PI ticks: TxDQ = 904
N4.C3.D0.R1: CheckMCTest: result = 0x1FF
N6.C3.D0.R0: CheckMCTest: result = 0x3FE00
N0.C3.D0.R0.S15: Dq Delay estimate: 432
N2.C0.D1.R0.S05: Total Delay in PI ticks: TxDQ = 922
ACCM: 0F 0F0F0F0F 0F0F0F0F
ACCM: F0 F0F0F0F0 F0F0F0F0
N0.C3.D0.R0.S16: Dq Delay estimate: 444
N2.C0.D1.R0.S06: Total Delay in PI ticks: TxDQ = 926
ACCM: 0F 0F0F0F0F 0F0F0F0F
ACCM: F0 F0F0F0F0 F0F0F0F0
N0.C3.D0.R0.S17: Dq Delay estimate: 421
N2.C0.D1.R0.S07: Total Delay in PI ticks: TxDQ = 941
ACCM: 0B 0000000B 000B0B00
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: F0 F0F0F0F0 F0F0F0F0
N2.C0.D1.R0.S08: Total Delay in PI ticks: TxDQ = 914
ACCM: 0B 0000000B 000B0B00
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: F0 F0F0F0F0 F0F0F0F0
N2.C0.D1.R0.S09: Total Delay in PI ticks: TxDQ = 984
N4.C3.D0.R1: CheckMCTest: result = 0x1FF
N6.C3.D0.R0: CheckMCTest: result = 0x3FE00
ACCM: F0 F0F0F0F0 F0F0F0B0
N2.C0.D1.R0.S10: Total Delay in PI ticks: TxDQ = 966
ACCM: 0F 0F0F0F0F 0F0F0F0F
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: F0 F0F0F0F0 F0F0F0B0
N2.C0.D1.R0.S11: Total Delay in PI ticks: TxDQ = 955
ACCM: 0F 0F0F0F0F 0F0F0F0F
ACCM: F0 F0F0F0F0 F0F0F0F0
N0.C3.D0.R0: CheckMCTest: result = 0x3FE00
N2.C0.D1.R0.S12: Total Delay in PI ticks: TxDQ = 938
ACCM: 0F 0000000F 000F0F00
ACCM: 00 B0B0B0B0 B000B0B0
ACCM: F0 F0F0F0F0 F0F0F0F0
N2.C0.D1.R0.S13: Total Delay in PI ticks: TxDQ = 905
ACCM: 0F 0000000F 000F0F00
ACCM: 00 B0B0B0B0 B000B0B0
ACCM: F0 F0F0F0F0 F0F0F0F0
N2.C0.D1.R0.S14: Total Delay in PI ticks: TxDQ = 924
N4.C3.D0.R1: CheckMCTest: result = 0x1FF
N6.C3.D0.R0: CheckMCTest: result = 0x3FE00
ACCM: F0 F0F0F0F0 F0F0F0F0
N2.C0.D1.R0.S15: Total Delay in PI ticks: TxDQ = 924
N4.C3.D0.R1: CheckMCTest: passed
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: F0 F0F0F0F0 F0F0F0F0
N2.C0.D1.R0.S16: Total Delay in PI ticks: TxDQ = 941
N4.C3.D0.R1: CheckMCTest: passed
ACCM: F0 F0F0F0F0 F0F0F0F0
N0.C3.D0.R0: CheckMCTest: result = 0x3FE00
N2.C0.D1.R0.S17: Total Delay in PI ticks: TxDQ = 913
N4.C3.D0.R1.S00: Offset Found: RdPtrOffsetDqs = 007
ACCM: 00 F0F0F0F0 F000F0F0
ACCM: F0 F0F0F0F0 F0F0F000
N2.C0.D1.R1.S00: wrcmd2dqsstartlatency: 04
N4.C3.D0.R1.S01: Offset Found: RdPtrOffsetDqs = 007
ACCM: 00 F0F0F0F0 F000F0F0
ACCM: F0 F0F0F0F0 F0F0F000
N2.C0.D1.R1.S00: RdPtrOffsetTxDq: 06
N4.C3.D0.R1.S02: Offset Found: RdPtrOffsetDqs = 007
N6.C3.D0.R0: CheckMCTest: result = 0x3FE00
ACCM: B0 00B00000 0000B000
N2.C0.D1.R1.S00: RdPtrOffsetTxDqs: 07
N4.C3.D0.R1.S03: Offset Found: RdPtrOffsetDqs = 007
N6.C3.D0.R0: CheckMCTest: passed
ACCM: B0 00B00000 0000B000
N2.C0.D1.R1.S00: PiTxDqs: 51
N4.C3.D0.R1.S04: Offset Found: RdPtrOffsetDqs = 006
N6.C3.D0.R0: CheckMCTest: passed
N0.C3.D0.R0: CheckMCTest: result = 0x3FC00
N2.C0.D1.R1.S01: wrcmd2dqsstartlatency: 04
N4.C3.D0.R1.S05: Offset Found: RdPtrOffsetDqs = 006
N6.C3.D0.R0.S09: Offset Found: RdPtrOffsetDqs = 007
ACCM: F0 F0F0F0F0 F0F0F000
N2.C0.D1.R1.S01: RdPtrOffsetTxDq: 06
N4.C3.D0.R1.S06: Offset Found: RdPtrOffsetDqs = 007
N6.C3.D0.R0.S10: Offset Found: RdPtrOffsetDqs = 007
ACCM: F0 F0F0F0F0 F0F0F000
N2.C0.D1.R1.S01: RdPtrOffsetTxDqs: 07
N4.C3.D0.R1.S07: Offset Found: RdPtrOffsetDqs = 007
N6.C3.D0.R0.S11: Offset Found: RdPtrOffsetDqs = 007
ACCM: F0 00F00000 0000F000
N2.C0.D1.R1.S01: PiTxDqs: 36
N4.C3.D0.R1.S08: Offset Found: RdPtrOffsetDqs = 006
N6.C3.D0.R0.S12: Offset Found: RdPtrOffsetDqs = 007
ACCM: F0 00F00000 0000F000
N2.C0.D1.R1.S02: wrcmd2dqsstartlatency: 04
N4.C3.D0.R1: Write Training Coarse, upper nibbles
N6.C3.D0.R0.S13: Offset Found: RdPtrOffsetDqs = 006
N0.C3.D0.R0: CheckMCTest: result = 0x3FC00
N2.C0.D1.R1.S02: RdPtrOffsetTxDq: 05
N4.C3.D0.R1.S09: Dq Delay estimate: 466
N6.C3.D0.R0.S14: Offset Found: RdPtrOffsetDqs = 006
N0.C3.D0.R0.S09: Offset Found: RdPtrOffsetDqs = 008
N2.C0.D1.R1.S02: RdPtrOffsetTxDqs: 07
N4.C3.D0.R1.S10: Dq Delay estimate: 453
N6.C3.D0.R0.S15: Offset Found: RdPtrOffsetDqs = 007
N0.C3.D0.R0: CheckMCTest: passed
N2.C0.D1.R1.S02: PiTxDqs: 22
N4.C3.D0.R1.S11: Dq Delay estimate: 440
N6.C3.D0.R0.S16: Offset Found: RdPtrOffsetDqs = 007
N0.C3.D0.R0: CheckMCTest: passed
N2.C0.D1.R1.S03: wrcmd2dqsstartlatency: 04
N4.C3.D0.R1.S12: Dq Delay estimate: 430
N6.C3.D0.R0.S17: Offset Found: RdPtrOffsetDqs = 006
N0.C3.D0.R0.S09: Offset Found: RdPtrOffsetDqs = 008
N2.C0.D1.R1.S03: RdPtrOffsetTxDq: 05
N4.C3.D0.R1.S13: Dq Delay estimate: 389
N6.C3.D0.R1: Write Training Coarse, lower nibbles / bytes
N0.C3.D0.R0.S10: Offset Found: RdPtrOffsetDqs = 007
N2.C0.D1.R1.S03: RdPtrOffsetTxDqs: 07
N4.C3.D0.R1.S14: Dq Delay estimate: 404
N6.C3.D0.R1.S00: Dq Delay estimate: 468
N0.C3.D0.R0.S11: Offset Found: RdPtrOffsetDqs = 007
N2.C0.D1.R1.S03: PiTxDqs: 06
N4.C3.D0.R1.S15: Dq Delay estimate: 418
N6.C3.D0.R1.S01: Dq Delay estimate: 451
N0.C3.D0.R0.S12: Offset Found: RdPtrOffsetDqs = 007
N2.C0.D1.R1.S04: wrcmd2dqsstartlatency: 04
N4.C3.D0.R1.S16: Dq Delay estimate: 438
N6.C3.D0.R1.S02: Dq Delay estimate: 441
N0.C3.D0.R0.S13: Offset Found: RdPtrOffsetDqs = 006
N2.C0.D1.R1.S04: RdPtrOffsetTxDq: 05
N4.C3.D0.R1.S17: Dq Delay estimate: 405
N6.C3.D0.R1.S03: Dq Delay estimate: 425
N0.C3.D0.R0.S14: Offset Found: RdPtrOffsetDqs = 007
N2.C0.D1.R1.S04: RdPtrOffsetTxDqs: 06
ACCM: F0 F0F0F0F0 F0F0F0F0
N6.C3.D0.R1.S04: Dq Delay estimate: 385
N0.C3.D0.R0.S15: Offset Found: RdPtrOffsetDqs = 007
N2.C0.D1.R1.S04: PiTxDqs: 36
ACCM: F0 F0F0F0F0 F0F0F0F0
N6.C3.D0.R1.S05: Dq Delay estimate: 402
N0.C3.D0.R0.S16: Offset Found: RdPtrOffsetDqs = 007
N2.C0.D1.R1.S05: wrcmd2dqsstartlatency: 04
ACCM: F0 F0F0F0F0 F0F0F0F0
N6.C3.D0.R1.S06: Dq Delay estimate: 417
N0.C3.D0.R0.S17: Offset Found: RdPtrOffsetDqs = 007
N2.C0.D1.R1.S05: RdPtrOffsetTxDq: 05
ACCM: F0 F0F0F0F0 F0F0F0F0
N6.C3.D0.R1.S07: Dq Delay estimate: 433
N0.C3.D0.R1: Write Training Coarse, lower nibbles / bytes
N2.C0.D1.R1.S05: RdPtrOffsetTxDqs: 06
N4.C3.D0.R1: CheckMCTest: result = 0x3FE00
N6.C3.D0.R1.S08: Dq Delay estimate: 406
N0.C3.D0.R1.S00: Dq Delay estimate: 472
N2.C0.D1.R1.S05: PiTxDqs: 55
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: 0F 0F0F0F0F 0F0F0F0F
N0.C3.D0.R1.S01: Dq Delay estimate: 455
N2.C0.D1.R1.S06: wrcmd2dqsstartlatency: 04
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: 0F 0F0F0F0F 0F0F0F0F
N0.C3.D0.R1.S02: Dq Delay estimate: 446
N2.C0.D1.R1.S06: RdPtrOffsetTxDq: 05
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: 0F 0F0F0F0F 0F0F0F0F
N0.C3.D0.R1.S03: Dq Delay estimate: 431
N2.C0.D1.R1.S06: RdPtrOffsetTxDqs: 06
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: 0F 0F0F0F0F 0F0F0F0F
N0.C3.D0.R1.S04: Dq Delay estimate: 396
N2.C0.D1.R1.S06: PiTxDqs: 59
N4.C3.D0.R1: CheckMCTest: result = 0x3FE00
N6.C3.D0.R1: CheckMCTest: result = 0x1FF
N0.C3.D0.R1.S05: Dq Delay estimate: 408
N2.C0.D1.R1.S07: wrcmd2dqsstartlatency: 04
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: 0F 0F0F0F0F 0F0F0F0F
N0.C3.D0.R1.S06: Dq Delay estimate: 422
N2.C0.D1.R1.S07: RdPtrOffsetTxDq: 05
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: 0F 0F0F0F0F 0F0F0F0F
N0.C3.D0.R1.S07: Dq Delay estimate: 442
N2.C0.D1.R1.S07: RdPtrOffsetTxDqs: 07
ACCM: 00 00B0B000 B00000B0
ACCM: 0F 0F0F0F0F 0F0F0F0F
N0.C3.D0.R1.S08: Dq Delay estimate: 413
N2.C0.D1.R1.S07: PiTxDqs: 12
ACCM: 00 00B0B000 B00000B0
ACCM: 0F 0F0F0F0F 0F0F0F0F
ACCM: 0F 0F0F0F0F 0F0F0F0F
N2.C0.D1.R1.S08: wrcmd2dqsstartlatency: 04
N4.C3.D0.R1: CheckMCTest: result = 0x3FE00
N6.C3.D0.R1: CheckMCTest: result = 0x1FF
ACCM: 0F 0F0F0F0F 0F0F0F0F
N2.C0.D1.R1.S08: RdPtrOffsetTxDq: 05
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: 0F 0F0F0F0F 0F0F0F0F
ACCM: 0F 0F0F0F0F 0F0F0F0F
N2.C0.D1.R1.S08: RdPtrOffsetTxDqs: 06
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: 0F 0F0F0F0F 0F0F0F0F
ACCM: 0F 0F0F0F0F 0F0F0F0F
N2.C0.D1.R1.S08: PiTxDqs: 45
ACCM: 00 00F0F000 F00000F0
ACCM: 00 0000000B 0B0B000B
N0.C3.D0.R1: CheckMCTest: result = 0x1FF
N2.C0.D1.R1.S09: wrcmd2dqsstartlatency: 04
ACCM: 00 00F0F000 F00000F0
ACCM: 00 0000000B 0B0B000B
ACCM: 0F 0F0F0F0F 0F0F0F0F
N2.C0.D1.R1.S09: RdPtrOffsetTxDq: 06
N4.C3.D0.R1: CheckMCTest: result = 0x3FE00
N6.C3.D0.R1: CheckMCTest: result = 0x1FF
ACCM: 0F 0F0F0F0F 0F0F0F0F
N2.C0.D1.R1.S09: RdPtrOffsetTxDqs: 07
N4.C3.D0.R1: CheckMCTest: passed
ACCM: 0F 0F0F0F0F 0F0F0F0F
ACCM: 0F 0F0F0F0F 0F0F0F0F
N2.C0.D1.R1.S09: PiTxDqs: 51
N4.C3.D0.R1: CheckMCTest: passed
ACCM: 0F 0F0F0F0F 0F0F0F0F
ACCM: 0F 0F0F0F0F 0F0F0F0F
N2.C0.D1.R1.S10: wrcmd2dqsstartlatency: 04
N4.C3.D0.R1.S09: Offset Found: RdPtrOffsetDqs = 007
ACCM: 00 0000000F 0F0F000F
N0.C3.D0.R1: CheckMCTest: result = 0x1FF
N2.C0.D1.R1.S10: RdPtrOffsetTxDq: 06
N4.C3.D0.R1.S10: Offset Found: RdPtrOffsetDqs = 007
ACCM: 00 0000000F 0F0F000F
ACCM: 0F 0F0F0F0F 0F0F0F0F
N2.C0.D1.R1.S10: RdPtrOffsetTxDqs: 07
N4.C3.D0.R1.S11: Offset Found: RdPtrOffsetDqs = 007
N6.C3.D0.R1: CheckMCTest: result = 0x1FF
ACCM: 0F 0F0F0F0F 0F0F0F0F
N2.C0.D1.R1.S10: PiTxDqs: 36
N4.C3.D0.R1.S12: Offset Found: RdPtrOffsetDqs = 007
N6.C3.D0.R1: CheckMCTest: passed
ACCM: 0B 0B0B0B0B 0B00000B
N2.C0.D1.R1.S11: wrcmd2dqsstartlatency: 04
N4.C3.D0.R1.S13: Offset Found: RdPtrOffsetDqs = 006
N6.C3.D0.R1: CheckMCTest: passed
ACCM: 0B 0B0B0B0B 0B00000B
N2.C0.D1.R1.S11: RdPtrOffsetTxDq: 05
N4.C3.D0.R1.S14: Offset Found: RdPtrOffsetDqs = 006
N6.C3.D0.R1.S00: Offset Found: RdPtrOffsetDqs = 007
N0.C3.D0.R1: CheckMCTest: result = 0x1FF
N2.C0.D1.R1.S11: RdPtrOffsetTxDqs: 07
N4.C3.D0.R1.S15: Offset Found: RdPtrOffsetDqs = 007
N6.C3.D0.R1.S01: Offset Found: RdPtrOffsetDqs = 007
ACCM: 0F 0F0F0F0F 0F0F0F0F
N2.C0.D1.R1.S11: PiTxDqs: 24
N4.C3.D0.R1.S16: Offset Found: RdPtrOffsetDqs = 007
N6.C3.D0.R1.S02: Offset Found: RdPtrOffsetDqs = 007
ACCM: 0F 0F0F0F0F 0F0F0F0F
N2.C0.D1.R1.S12: wrcmd2dqsstartlatency: 04
N4.C3.D0.R1.S17: Offset Found: RdPtrOffsetDqs = 006
N6.C3.D0.R1.S03: Offset Found: RdPtrOffsetDqs = 007
ACCM: 0F 0F0F0F0F 0F00000F
N2.C0.D1.R1.S12: RdPtrOffsetTxDq: 05
N4.C3.D1.R0: Write Training Coarse, lower nibbles / bytes
N6.C3.D0.R1.S04: Offset Found: RdPtrOffsetDqs = 006
ACCM: 0F 0F0F0F0F 0F00000F
N2.C0.D1.R1.S12: RdPtrOffsetTxDqs: 07
N4.C3.D1.R0.S00: Dq Delay estimate: 348
N6.C3.D0.R1.S05: Offset Found: RdPtrOffsetDqs = 006
N0.C3.D0.R1: CheckMCTest: result = 0x1FF
N2.C0.D1.R1.S12: PiTxDqs: 11
N4.C3.D1.R0.S01: Dq Delay estimate: 461
N6.C3.D0.R1.S06: Offset Found: RdPtrOffsetDqs = 007
N0.C3.D0.R1: CheckMCTest: passed
N2.C0.D1.R1.S13: wrcmd2dqsstartlatency: 04
N4.C3.D1.R0.S02: Dq Delay estimate: 454
N6.C3.D0.R1.S07: Offset Found: RdPtrOffsetDqs = 007
N0.C3.D0.R1: CheckMCTest: passed
N2.C0.D1.R1.S13: RdPtrOffsetTxDq: 05
N4.C3.D1.R0.S03: Dq Delay estimate: 436
N6.C3.D0.R1.S08: Offset Found: RdPtrOffsetDqs = 006
N0.C3.D0.R1.S00: Offset Found: RdPtrOffsetDqs = 007
N2.C0.D1.R1.S13: RdPtrOffsetTxDqs: 06
N4.C3.D1.R0.S04: Dq Delay estimate: 400
N6.C3.D0.R1: Write Training Coarse, upper nibbles
N0.C3.D0.R1.S01: Offset Found: RdPtrOffsetDqs = 007
N2.C0.D1.R1.S13: PiTxDqs: 37
N4.C3.D1.R0.S05: Dq Delay estimate: 410
N6.C3.D0.R1.S09: Dq Delay estimate: 464
N0.C3.D0.R1.S02: Offset Found: RdPtrOffsetDqs = 007
N2.C0.D1.R1.S14: wrcmd2dqsstartlatency: 04
N4.C3.D1.R0.S06: Dq Delay estimate: 428
N6.C3.D0.R1.S10: Dq Delay estimate: 450
N0.C3.D0.R1.S03: Offset Found: RdPtrOffsetDqs = 007
N2.C0.D1.R1.S14: RdPtrOffsetTxDq: 05
N4.C3.D1.R0.S07: Dq Delay estimate: 447
N6.C3.D0.R1.S11: Dq Delay estimate: 440
N0.C3.D0.R1.S04: Offset Found: RdPtrOffsetDqs = 006
N2.C0.D1.R1.S14: RdPtrOffsetTxDqs: 06
N4.C3.D1.R0.S08: Dq Delay estimate: 419
N6.C3.D0.R1.S12: Dq Delay estimate: 424
N0.C3.D0.R1.S05: Offset Found: RdPtrOffsetDqs = 006
N2.C0.D1.R1.S14: PiTxDqs: 54
ACCM: 0F 0F0F0F0F 0F0F0F0F
N6.C3.D0.R1.S13: Dq Delay estimate: 387
N0.C3.D0.R1.S06: Offset Found: RdPtrOffsetDqs = 007
N2.C0.D1.R1.S15: wrcmd2dqsstartlatency: 04
ACCM: 0F 0F0F0F0F 0F0F0F0F
N6.C3.D0.R1.S14: Dq Delay estimate: 406
N0.C3.D0.R1.S07: Offset Found: RdPtrOffsetDqs = 007
N2.C0.D1.R1.S15: RdPtrOffsetTxDq: 05
ACCM: 0F 0F0F0F0F 0F0F0F00
N6.C3.D0.R1.S15: Dq Delay estimate: 418
N0.C3.D0.R1.S08: Offset Found: RdPtrOffsetDqs = 006
N2.C0.D1.R1.S15: RdPtrOffsetTxDqs: 06
ACCM: 0F FFFF0F0F FFFF0F00
N6.C3.D0.R1.S16: Dq Delay estimate: 438
N0.C3.D0.R1: Write Training Coarse, upper nibbles
N2.C0.D1.R1.S15: PiTxDqs: 59
N4.C3.D1.R0: CheckMCTest: result = 0x199FF
N6.C3.D0.R1.S17: Dq Delay estimate: 403
N0.C3.D0.R1.S09: Dq Delay estimate: 470
N2.C0.D1.R1.S16: wrcmd2dqsstartlatency: 04
ACCM: 0F 0F0F0F0F 0F0F0F0F
ACCM: F0 F0F0F0F0 F0F0F0F0
N0.C3.D0.R1.S10: Dq Delay estimate: 457
N2.C0.D1.R1.S16: RdPtrOffsetTxDq: 05
ACCM: 0F 0F0F0F0F 0F0F0F0F
ACCM: F0 F0F0F0F0 F0F0F0F0
N0.C3.D0.R1.S11: Dq Delay estimate: 446
N2.C0.D1.R1.S16: RdPtrOffsetTxDqs: 07
ACCM: 0F 0F0F0F0F 0F0F0F00
ACCM: F0 F0F0F0F0 F0F0F0F0
N0.C3.D0.R1.S12: Dq Delay estimate: 434
N2.C0.D1.R1.S16: PiTxDqs: 11
ACCM: 0F FFFF0F0F FFFF0F00
ACCM: F0 F0F0F0F0 F0F0F0F0
N0.C3.D0.R1.S13: Dq Delay estimate: 396
N2.C0.D1.R1.S17: wrcmd2dqsstartlatency: 04
N4.C3.D1.R0: CheckMCTest: result = 0x199FF
N6.C3.D0.R1: CheckMCTest: result = 0x3FE00
N0.C3.D0.R1.S14: Dq Delay estimate: 410
N2.C0.D1.R1.S17: RdPtrOffsetTxDq: 05
ACCM: 0F 0F0F0F0F 0F0F0F00
ACCM: F0 F0F0F0F0 F0F0F0F0
N0.C3.D0.R1.S15: Dq Delay estimate: 422
N2.C0.D1.R1.S17: RdPtrOffsetTxDqs: 06
ACCM: 0F 0F0F0F0F 0F0F0F00
ACCM: F0 F0F0F0F0 F0F0F0F0
N0.C3.D0.R1.S16: Dq Delay estimate: 442
N2.C0.D1.R1.S17: PiTxDqs: 45
ACCM: 0B 0B0B000B 00000000
ACCM: F0 F0F0F0F0 F0F0F0F0
N0.C3.D0.R1.S17: Dq Delay estimate: 412
N2.C0.D1.R1.S00: RdPtrOffsetTxDq: 07
ACCM: 0B FBFB000B F0F00000
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: F0 F0F0F0F0 F0F0F0F0
N2.C0.D1.R1.S01: RdPtrOffsetTxDq: 07
N4.C3.D1.R0: CheckMCTest: result = 0x199FE
N6.C3.D0.R1: CheckMCTest: result = 0x3FE00
ACCM: F0 F0F0F0F0 F0F0F0F0
N2.C0.D1.R1.S02: RdPtrOffsetTxDq: 06
ACCM: 0F 0F0F0F0F 0F0F0F00
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: F0 F0F0F0F0 F0F0F0F0
N2.C0.D1.R1.S03: RdPtrOffsetTxDq: 06
ACCM: 0F 0F0F0F0F 0F0F0F00
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: F0 F0F0F0F0 F0F0F0F0
N2.C0.D1.R1.S04: RdPtrOffsetTxDq: 06
ACCM: 0F 0F0F000F 00000000
ACCM: 00 B00000B0 B000B000
N0.C3.D0.R1: CheckMCTest: result = 0x3FE00
N2.C0.D1.R1.S05: RdPtrOffsetTxDq: 06
ACCM: 0F FFFF000F F0F00000
ACCM: 00 B00000B0 B000B000
ACCM: F0 F0F0F0F0 F0F0F0F0
N2.C0.D1.R1.S06: RdPtrOffsetTxDq: 06
N4.C3.D1.R0: CheckMCTest: result = 0x199FE
N6.C3.D0.R1: CheckMCTest: result = 0x3FE00
ACCM: F0 F0F0F0F0 F0F0F0F0
N2.C0.D1.R1.S07: RdPtrOffsetTxDq: 06
N4.C3.D1.R0.S00: Offset Found: RdPtrOffsetDqs = 008
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: F0 F0F0F0F0 F0F0F0F0
N2.C0.D1.R1.S08: RdPtrOffsetTxDq: 06
ACCM: 00 00000000 00000000
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: F0 F0F0F0F0 F0F0F0F0
N2.C0.D1.R1.S09: RdPtrOffsetTxDq: 07
ACCM: 00 00000000 00000000
ACCM: 00 F00000F0 F000F000
N0.C3.D0.R1: CheckMCTest: result = 0x3FE00
N2.C0.D1.R1.S10: RdPtrOffsetTxDq: 07
ACCM: 00 00000000 00000000
ACCM: 00 F00000F0 F000F000
ACCM: F0 F0F0F0F0 F0F0F0F0
N2.C0.D1.R1.S11: RdPtrOffsetTxDq: 06
ACCM: 00 F0F00000 F0F00000
N6.C3.D0.R1: CheckMCTest: result = 0x3FE00
ACCM: F0 F0F0F0F0 F0F0F0F0
N2.C0.D1.R1.S12: RdPtrOffsetTxDq: 06
N4.C3.D1.R0: CheckMCTest: result = 0x19800
N6.C3.D0.R1: CheckMCTest: passed
ACCM: 00 000000B0 00000000
N2.C0.D1.R1.S13: RdPtrOffsetTxDq: 06
ACCM: 00 00000000 00000000
N6.C3.D0.R1: CheckMCTest: passed
ACCM: 00 000000B0 00000000
N2.C0.D1.R1.S14: RdPtrOffsetTxDq: 06
ACCM: 00 00000000 00000000
N6.C3.D0.R1.S09: Offset Found: RdPtrOffsetDqs = 007
N0.C3.D0.R1: CheckMCTest: result = 0x3FE00
N2.C0.D1.R1.S15: RdPtrOffsetTxDq: 06
ACCM: 00 00000000 00000000
N6.C3.D0.R1.S10: Offset Found: RdPtrOffsetDqs = 007
ACCM: F0 F0F0F0F0 F0F0F0F0
N2.C0.D1.R1.S16: RdPtrOffsetTxDq: 06
ACCM: 00 F0F00000 F0F00000
N6.C3.D0.R1.S11: Offset Found: RdPtrOffsetDqs = 007
ACCM: F0 F0F0F0F0 F0F0F0F0
N2.C0.D1.R1.S17: RdPtrOffsetTxDq: 06
N4.C3.D1.R0: CheckMCTest: result = 0x19800
N6.C3.D0.R1.S12: Offset Found: RdPtrOffsetDqs = 007
ACCM: 00 000000F0 00D00000
N2.C0.D1.R1.S00: RdPtrOffsetTxDq: 08
N4.C3.D1.R0.S00: Offset Found: RdPtrOffsetDqs = 008
N6.C3.D0.R1.S13: Offset Found: RdPtrOffsetDqs = 006
ACCM: 00 000000F0 00D00000
N2.C0.D1.R1.S01: RdPtrOffsetTxDq: 08
N4.C3.D1.R0.S01: Offset Found: RdPtrOffsetDqs = 007
N6.C3.D0.R1.S14: Offset Found: RdPtrOffsetDqs = 006
N0.C3.D0.R1: CheckMCTest: result = 0x3FE00
N2.C0.D1.R1.S02: RdPtrOffsetTxDq: 07
N4.C3.D1.R0.S02: Offset Found: RdPtrOffsetDqs = 007
N6.C3.D0.R1.S15: Offset Found: RdPtrOffsetDqs = 007
N0.C3.D0.R1: CheckMCTest: passed
N2.C0.D1.R1.S03: RdPtrOffsetTxDq: 07
N4.C3.D1.R0.S03: Offset Found: RdPtrOffsetDqs = 007
N6.C3.D0.R1.S16: Offset Found: RdPtrOffsetDqs = 007
N0.C3.D0.R1: CheckMCTest: passed
N2.C0.D1.R1.S04: RdPtrOffsetTxDq: 07
N4.C3.D1.R0.S04: Offset Found: RdPtrOffsetDqs = 006
N6.C3.D0.R1.S17: Offset Found: RdPtrOffsetDqs = 006
N0.C3.D0.R1.S09: Offset Found: RdPtrOffsetDqs = 007
N2.C0.D1.R1.S05: RdPtrOffsetTxDq: 07
N4.C3.D1.R0.S05: Offset Found: RdPtrOffsetDqs = 007
N6.C3.D1.R0: Write Training Coarse, lower nibbles / bytes
N0.C3.D0.R1.S10: Offset Found: RdPtrOffsetDqs = 007
N2.C0.D1.R1.S06: RdPtrOffsetTxDq: 07
N4.C3.D1.R0.S06: Offset Found: RdPtrOffsetDqs = 007
N6.C3.D1.R0.S00: Dq Delay estimate: 352
N0.C3.D0.R1.S11: Offset Found: RdPtrOffsetDqs = 007
N2.C0.D1.R1.S07: RdPtrOffsetTxDq: 07
N4.C3.D1.R0.S07: Offset Found: RdPtrOffsetDqs = 007
N6.C3.D1.R0.S01: Dq Delay estimate: 462
N0.C3.D0.R1.S12: Offset Found: RdPtrOffsetDqs = 007
N2.C0.D1.R1.S08: RdPtrOffsetTxDq: 07
N4.C3.D1.R0.S08: Offset Found: RdPtrOffsetDqs = 007
N6.C3.D1.R0.S02: Dq Delay estimate: 450
N0.C3.D0.R1.S13: Offset Found: RdPtrOffsetDqs = 006
N2.C0.D1.R1.S09: RdPtrOffsetTxDq: 08
N4.C3.D1.R0: Write Training Coarse, upper nibbles
N6.C3.D1.R0.S03: Dq Delay estimate: 437
N0.C3.D0.R1.S14: Offset Found: RdPtrOffsetDqs = 006
N2.C0.D1.R1.S10: RdPtrOffsetTxDq: 08
N4.C3.D1.R0.S09: Dq Delay estimate: 348
N6.C3.D1.R0.S04: Dq Delay estimate: 397
N0.C3.D0.R1.S15: Offset Found: RdPtrOffsetDqs = 007
N2.C0.D1.R1.S11: RdPtrOffsetTxDq: 07
N4.C3.D1.R0.S10: Dq Delay estimate: 463
N6.C3.D1.R0.S05: Dq Delay estimate: 412
N0.C3.D0.R1.S16: Offset Found: RdPtrOffsetDqs = 007
N2.C0.D1.R1.S12: RdPtrOffsetTxDq: 07
N4.C3.D1.R0.S11: Dq Delay estimate: 454
N6.C3.D1.R0.S06: Dq Delay estimate: 427
N0.C3.D0.R1.S17: Offset Found: RdPtrOffsetDqs = 006
N2.C0.D1.R1.S13: RdPtrOffsetTxDq: 07
N4.C3.D1.R0.S12: Dq Delay estimate: 440
N6.C3.D1.R0.S07: Dq Delay estimate: 445
N0.C3.D1.R0: Write Training Coarse, lower nibbles / bytes
N2.C0.D1.R1.S14: RdPtrOffsetTxDq: 07
N4.C3.D1.R0.S13: Dq Delay estimate: 402
N6.C3.D1.R0.S08: Dq Delay estimate: 416
N0.C3.D1.R0.S00: Dq Delay estimate: 352
N2.C0.D1.R1.S15: RdPtrOffsetTxDq: 07
N4.C3.D1.R0.S14: Dq Delay estimate: 417
ACCM: 0F 0F0F0F0F 0F0F0F0F
N0.C3.D1.R0.S01: Dq Delay estimate: 462
N2.C0.D1.R1.S16: RdPtrOffsetTxDq: 07
N4.C3.D1.R0.S15: Dq Delay estimate: 427
ACCM: 0F 0F0F0F0F 0F0F0F0F
N0.C3.D1.R0.S02: Dq Delay estimate: 455
N2.C0.D1.R1.S17: RdPtrOffsetTxDq: 07
N4.C3.D1.R0.S16: Dq Delay estimate: 448
ACCM: 0F 0F0F0F0F 0F0F0F09
N0.C3.D1.R0.S03: Dq Delay estimate: 436
N2.C0.D1.R1.S00: Total Delay in PI ticks: TxDQ = 981
N4.C3.D1.R0.S17: Dq Delay estimate: 417
ACCM: 0F FFFF0F0F FFFF0F09
N0.C3.D1.R0.S04: Dq Delay estimate: 402
N2.C0.D1.R1.S01: Total Delay in PI ticks: TxDQ = 963
ACCM: F0 F0F0F0F0 F0F0F0F0
N6.C3.D1.R0: CheckMCTest: result = 0x199FF
N0.C3.D1.R0.S05: Dq Delay estimate: 415
N2.C0.D1.R1.S02: Total Delay in PI ticks: TxDQ = 948
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: 0F 0F0F0F0F 0F0F0F0F
N0.C3.D1.R0.S06: Dq Delay estimate: 429
N2.C0.D1.R1.S03: Total Delay in PI ticks: TxDQ = 935
ACCM: F0 F0F0F0F0 F0F0F000
ACCM: 0F 0F0F0F0F 0F0F0F0F
N0.C3.D1.R0.S07: Dq Delay estimate: 449
N2.C0.D1.R1.S04: Total Delay in PI ticks: TxDQ = 901
ACCM: F0 F0F0F0F0 F0F0F000
ACCM: 0F 0F0F0F0F 0F0F0F0D
N0.C3.D1.R0.S08: Dq Delay estimate: 418
N2.C0.D1.R1.S05: Total Delay in PI ticks: TxDQ = 919
N4.C3.D1.R0: CheckMCTest: result = 0x3FE00
ACCM: 0F FFFF0F0F FFFF0F0D
ACCM: 0F 0F0F0F0F 0F0F0F0F
N2.C0.D1.R1.S06: Total Delay in PI ticks: TxDQ = 923
ACCM: F0 F0F0F0F0 F0F0F0F0
N6.C3.D1.R0: CheckMCTest: result = 0x199FF
ACCM: 0F 0F0F0F0F 0F0F0F0F
N2.C0.D1.R1.S07: Total Delay in PI ticks: TxDQ = 938
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: 0F 0F0F0F0F 0F0F0F00
ACCM: 0F 0F0F0F0F 0F0F0F09
N2.C0.D1.R1.S08: Total Delay in PI ticks: TxDQ = 908
ACCM: F0 F0F0F0F0 F0F0F000
ACCM: 0F 0F0F0F0F 0F0F0F00
ACCM: 0F FFFF0F0F FFFF0F09
N2.C0.D1.R1.S09: Total Delay in PI ticks: TxDQ = 977
ACCM: F0 F0F0F0F0 F0F0F000
ACCM: 00 0B0B000B 0B000B00
N0.C3.D1.R0: CheckMCTest: result = 0x199FF
N2.C0.D1.R1.S10: Total Delay in PI ticks: TxDQ = 963
N4.C3.D1.R0: CheckMCTest: result = 0x3FE00
ACCM: 00 FBFB000B FBF00B00
ACCM: 0F 0F0F0F0F 0F0F0F0F
N2.C0.D1.R1.S11: Total Delay in PI ticks: TxDQ = 950
ACCM: F0 F0F0F0F0 F0F0F000
N6.C3.D1.R0: CheckMCTest: result = 0x199FE
ACCM: 0F 0F0F0F0F 0F0F0F0F
N2.C0.D1.R1.S12: Total Delay in PI ticks: TxDQ = 937
ACCM: F0 F0F0F0F0 F0F0F000
ACCM: 0F 0F0F0F0F 0F0F0F00
ACCM: 0F 0F0F0F0F 0F0F0F0D
N2.C0.D1.R1.S13: Total Delay in PI ticks: TxDQ = 901
ACCM: 00 0000B000 B000B000
ACCM: 0F 0F0F0F0F 0F0F0F00
ACCM: 0F FFFF0F0F FFFF0F0D
N2.C0.D1.R1.S14: Total Delay in PI ticks: TxDQ = 919
ACCM: 00 0000B000 B000B000
ACCM: 00 0F0F000F 0F0D0F00
N0.C3.D1.R0: CheckMCTest: result = 0x199FF
N2.C0.D1.R1.S15: Total Delay in PI ticks: TxDQ = 922
N4.C3.D1.R0: CheckMCTest: result = 0x3FC00
ACCM: 00 FFFF000F FFFD0F00
ACCM: 0F 0F0F0F0F 0F0F0F00
N2.C0.D1.R1.S16: Total Delay in PI ticks: TxDQ = 937
ACCM: F0 F0F0F0F0 F0F0F000
N6.C3.D1.R0: CheckMCTest: result = 0x199FE
ACCM: 0F 0F0F0F0F 0F0F0F00
N2.C0.D1.R1.S17: Total Delay in PI ticks: TxDQ = 907
ACCM: F0 F0F0F0F0 F0F0F000
N6.C3.D1.R0.S00: Offset Found: RdPtrOffsetDqs = 008
ACCM: 0B 0B0B0B00 00000B00
N2.C0: Calculating Optimimum DQ/DQS Values
ACCM: 00 0000F000 F000F000
ACCM: 00 00000000 00000000
ACCM: 0B FBFB0B00 F0F00B00
ACCM: 00 0000F000 F000F000
ACCM: 00 00000000 00000000
N0.C3.D1.R0: CheckMCTest: result = 0x199FE
N4.C3.D1.R0: CheckMCTest: result = 0x3FC00
ACCM: 00 00000000 00000000
ACCM: 0F 0F0F0F0F 0F0F0F00
START_DATA_TX_DQ
N4.C3.D1.R0.S09: Offset Found: RdPtrOffsetDqs = 008
ACCM: 00 F0F00000 F0F00000
ACCM: 0F 0F0F0F0F 0F0F0F00
N2.C0.S00: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 009, RdPtrOffsetTxDqs = 009
N4.C3.D1.R0: CheckMCTest: passed
N6.C3.D1.R0: CheckMCTest: result = 0x19800
ACCM: 0F 0F0B0B00 000D0F00
N2.C0.S00: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 009, RdPtrOffsetTxDqs = 009
N4.C3.D1.R0: CheckMCTest: passed
ACCM: 00 00000000 00000000
ACCM: 0F FFFB0B00 F0FD0F00
N2.C0.S01: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 009
N4.C3.D1.R0.S09: Offset Found: RdPtrOffsetDqs = 008
ACCM: 00 00000000 00000000
N0.C3.D1.R0: CheckMCTest: result = 0x199FE
N2.C0.S01: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 009
N4.C3.D1.R0.S10: Offset Found: RdPtrOffsetDqs = 007
ACCM: 00 00000000 00000000
N0.C3.D1.R0.S00: Offset Found: RdPtrOffsetDqs = 008
N2.C0.S02: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 009
N4.C3.D1.R0.S11: Offset Found: RdPtrOffsetDqs = 007
ACCM: 00 F0F00000 F0F00000
ACCM: 00 00000000 00000000
N2.C0.S02: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 009
N4.C3.D1.R0.S12: Offset Found: RdPtrOffsetDqs = 007
N6.C3.D1.R0: CheckMCTest: result = 0x19800
ACCM: 00 00000000 00000000
N2.C0.S03: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 008
N4.C3.D1.R0.S13: Offset Found: RdPtrOffsetDqs = 006
N6.C3.D1.R0.S00: Offset Found: RdPtrOffsetDqs = 008
ACCM: 00 00000000 00000000
N2.C0.S03: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 008
N4.C3.D1.R0.S14: Offset Found: RdPtrOffsetDqs = 007
N6.C3.D1.R0.S01: Offset Found: RdPtrOffsetDqs = 007
ACCM: 00 F0F00000 F0F00000
N2.C0.S04: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 007, RdPtrOffsetTxDqs = 008
N4.C3.D1.R0.S15: Offset Found: RdPtrOffsetDqs = 007
N6.C3.D1.R0.S02: Offset Found: RdPtrOffsetDqs = 007
N0.C3.D1.R0: CheckMCTest: result = 0x19800
N2.C0.S04: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 007, RdPtrOffsetTxDqs = 008
N4.C3.D1.R0.S16: Offset Found: RdPtrOffsetDqs = 007
N6.C3.D1.R0.S03: Offset Found: RdPtrOffsetDqs = 007
ACCM: 00 00000000 00000000
N2.C0.S05: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 008
N4.C3.D1.R0.S17: Offset Found: RdPtrOffsetDqs = 007
N6.C3.D1.R0.S04: Offset Found: RdPtrOffsetDqs = 006
ACCM: 00 00000000 00000000
N2.C0.S05: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 008
N4.C3.D1.R1: Write Training Coarse, lower nibbles / bytes
N6.C3.D1.R0.S05: Offset Found: RdPtrOffsetDqs = 007
ACCM: 00 00000000 00000000
N2.C0.S06: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 008
N4.C3.D1.R1.S00: Dq Delay estimate: 346
N6.C3.D1.R0.S06: Offset Found: RdPtrOffsetDqs = 007
ACCM: 00 F0F00000 F0F00000
N2.C0.S06: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 008
N4.C3.D1.R1.S01: Dq Delay estimate: 457
N6.C3.D1.R0.S07: Offset Found: RdPtrOffsetDqs = 007
N0.C3.D1.R0: CheckMCTest: result = 0x19800
N2.C0.S07: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 009
N4.C3.D1.R1.S02: Dq Delay estimate: 449
N6.C3.D1.R0.S08: Offset Found: RdPtrOffsetDqs = 007
N0.C3.D1.R0.S00: Offset Found: RdPtrOffsetDqs = 008
N2.C0.S07: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 009
N4.C3.D1.R1.S03: Dq Delay estimate: 435
N6.C3.D1.R0: Write Training Coarse, upper nibbles
N0.C3.D1.R0.S01: Offset Found: RdPtrOffsetDqs = 007
N2.C0.S08: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 008
N4.C3.D1.R1.S04: Dq Delay estimate: 395
N6.C3.D1.R0.S09: Dq Delay estimate: 350
N0.C3.D1.R0.S02: Offset Found: RdPtrOffsetDqs = 007
N2.C0.S08: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 008
N4.C3.D1.R1.S05: Dq Delay estimate: 410
N6.C3.D1.R0.S10: Dq Delay estimate: 460
N0.C3.D1.R0.S03: Offset Found: RdPtrOffsetDqs = 007
N2.C0.D0.R0.S00: TxDqs: plus1 = 1, minus1 = 0, PI = 49, DB = 1
N4.C3.D1.R1.S06: Dq Delay estimate: 423
N6.C3.D1.R0.S11: Dq Delay estimate: 451
N0.C3.D1.R0.S04: Offset Found: RdPtrOffsetDqs = 006
N2.C0.D0.R0.S00: TxDq : plus1 = 1, minus1 = 0, PI = 19, DB = 0
N4.C3.D1.R1.S07: Dq Delay estimate: 443
N6.C3.D1.R0.S12: Dq Delay estimate: 435
N0.C3.D1.R0.S05: Offset Found: RdPtrOffsetDqs = 007
N2.C0.D0.R0.S01: TxDqs: plus1 = 1, minus1 = 0, PI = 28, DB = 0
N4.C3.D1.R1.S08: Dq Delay estimate: 414
N6.C3.D1.R0.S13: Dq Delay estimate: 399
N0.C3.D1.R0.S06: Offset Found: RdPtrOffsetDqs = 007
N2.C0.D0.R0.S01: TxDq : plus1 = 1, minus1 = 0, PI = 59, DB = 1
ACCM: 0F 0F0F0F0F 0F0F0F0F
N6.C3.D1.R0.S14: Dq Delay estimate: 417
N0.C3.D1.R0.S07: Offset Found: RdPtrOffsetDqs = 007
N2.C0.D0.R0.S02: TxDqs: plus1 = 1, minus1 = 0, PI = 17, DB = 0
ACCM: 0F 0F0F0F0F 0F0F0F0F
N6.C3.D1.R0.S15: Dq Delay estimate: 429
N0.C3.D1.R0.S08: Offset Found: RdPtrOffsetDqs = 007
N2.C0.D0.R0.S02: TxDq : plus1 = 1, minus1 = 0, PI = 47, DB = 0
ACCM: 0F 0F0F0F0F 0F0F0F00
N6.C3.D1.R0.S16: Dq Delay estimate: 449
N0.C3.D1.R0: Write Training Coarse, upper nibbles
N2.C0.D0.R0.S03: TxDqs: plus1 = 1, minus1 = 0, PI = 63, DB = 1
ACCM: 0F 0F0F0F0F 0F0F0F00
N6.C3.D1.R0.S17: Dq Delay estimate: 415
N0.C3.D1.R0.S09: Dq Delay estimate: 351
N2.C0.D0.R0.S03: TxDq : plus1 = 1, minus1 = 0, PI = 31, DB = 0
N4.C3.D1.R1: CheckMCTest: result = 0x1FF
ACCM: F0 F0F0F0F0 F0F0F0F0
N0.C3.D1.R0.S10: Dq Delay estimate: 465
N2.C0.D0.R0.S04: TxDqs: plus1 = 1, minus1 = 0, PI = 30, DB = 0
ACCM: 0F 0F0F0F0F 0F0F0F0F
ACCM: F0 F0F0F0F0 F0F0F0F0
N0.C3.D1.R0.S11: Dq Delay estimate: 457
N2.C0.D0.R0.S04: TxDq : plus1 = 1, minus1 = 0, PI = 63, DB = 1
ACCM: 0F 0F0F0F0F 0F0F0F0F
ACCM: F0 F0F0F0F0 F0F0F0D0
N0.C3.D1.R0.S12: Dq Delay estimate: 439
N2.C0.D0.R0.S05: TxDqs: plus1 = 1, minus1 = 0, PI = 47, DB = 0
ACCM: 0F 0F0F0F0F 0F0F0F00
ACCM: F0 F0F0F0F0 F0F0F0D0
N0.C3.D1.R0.S13: Dq Delay estimate: 403
N2.C0.D0.R0.S05: TxDq : plus1 = 1, minus1 = 0, PI = 15, DB = 1
ACCM: 0F 0F0F0F0F 0F0F0F00
N6.C3.D1.R0: CheckMCTest: result = 0x3FE00
N0.C3.D1.R0.S14: Dq Delay estimate: 418
N2.C0.D0.R0.S06: TxDqs: plus1 = 1, minus1 = 0, PI = 54, DB = 1
N4.C3.D1.R1: CheckMCTest: result = 0x1FF
ACCM: F0 F0F0F0F0 F0F0F0F0
N0.C3.D1.R0.S15: Dq Delay estimate: 432
N2.C0.D0.R0.S06: TxDq : plus1 = 1, minus1 = 0, PI = 23, DB = 0
ACCM: 0F 0F0F0F0F 0F0F0F00
ACCM: F0 F0F0F0F0 F0F0F0F0
N0.C3.D1.R0.S16: Dq Delay estimate: 447
N2.C0.D0.R0.S07: TxDqs: plus1 = 1, minus1 = 0, PI = 02, DB = 1
ACCM: 0F 0F0F0F0F 0F0F0F00
ACCM: F0 F0F0F0F0 F0F0F0D0
N0.C3.D1.R0.S17: Dq Delay estimate: 415
N2.C0.D0.R0.S07: TxDq : plus1 = 1, minus1 = 0, PI = 34, DB = 0
ACCM: 00 000B0B00 0B0B0000
ACCM: F0 F0F0F0F0 F0F0F0D0
ACCM: F0 F0F0F0F0 F0F0F0F0
N2.C0.D0.R0.S08: TxDqs: plus1 = 1, minus1 = 0, PI = 42, DB = 0
ACCM: 00 000B0B00 0B0B0000
N6.C3.D1.R0: CheckMCTest: result = 0x3FE00
ACCM: F0 F0F0F0F0 F0F0F0F0
N2.C0.D0.R0.S08: TxDq : plus1 = 1, minus1 = 0, PI = 12, DB = 1
N4.C3.D1.R1: CheckMCTest: result = 0x1FE
ACCM: F0 F0F0F0F0 F0F0F000
ACCM: F0 F0F0F0F0 F0F0F0D0
N2.C0.D0.R0.S09: TxDqs: plus1 = 1, minus1 = 0, PI = 48, DB = 0
ACCM: 0F 0F0F0F0F 0F0F0F00
ACCM: F0 F0F0F0F0 F0F0F000
ACCM: F0 F0F0F0F0 F0F0F0D0
N2.C0.D0.R0.S09: TxDq : plus1 = 1, minus1 = 0, PI = 16, DB = 0
ACCM: 0F 0F0F0F0F 0F0F0F00
ACCM: 00 00B000B0 0000B000
N0.C3.D1.R0: CheckMCTest: result = 0x3FE00
N2.C0.D0.R0.S10: TxDqs: plus1 = 1, minus1 = 0, PI = 27, DB = 0
ACCM: 00 000F0F00 0F0F0000
ACCM: 00 00B000B0 0000B000
ACCM: F0 F0F0F0F0 F0F0F0F0
N2.C0.D0.R0.S10: TxDq : plus1 = 1, minus1 = 0, PI = 59, DB = 1
ACCM: 00 000F0F00 0F0F0000
N6.C3.D1.R0: CheckMCTest: result = 0x3FC00
ACCM: F0 F0F0F0F0 F0F0F0F0
N2.C0.D0.R0.S11: TxDqs: plus1 = 1, minus1 = 0, PI = 18, DB = 0
N4.C3.D1.R1: CheckMCTest: result = 0x1FE
ACCM: F0 F0F0F0F0 F0F0F000
ACCM: F0 F0F0F0F0 F0F0F0D0
N2.C0.D0.R0.S11: TxDq : plus1 = 1, minus1 = 0, PI = 49, DB = 1
N4.C3.D1.R1.S00: Offset Found: RdPtrOffsetDqs = 008
ACCM: F0 F0F0F0F0 F0F0F000
ACCM: F0 F0F0F0F0 F0F0F0D0
N2.C0.D0.R0.S12: TxDqs: plus1 = 0, minus1 = 1, PI = 02, DB = 1
N4.C3.D1.R1: CheckMCTest: passed
ACCM: 00 00F000F0 0000F000
N0.C3.D1.R0: CheckMCTest: result = 0x3FE00
N2.C0.D0.R0.S12: TxDq : plus1 = 1, minus1 = 0, PI = 33, DB = 0
N4.C3.D1.R1: CheckMCTest: passed
ACCM: 00 00F000F0 0000F000
ACCM: F0 F0F0F0F0 F0F0F000
N2.C0.D0.R0.S13: TxDqs: plus1 = 1, minus1 = 0, PI = 31, DB = 0
N4.C3.D1.R1.S00: Offset Found: RdPtrOffsetDqs = 008
N6.C3.D1.R0: CheckMCTest: result = 0x3FC00
ACCM: F0 F0F0F0F0 F0F0F000
N2.C0.D0.R0.S13: TxDq : plus1 = 0, minus1 = 1, PI = 01, DB = 1
N4.C3.D1.R1.S01: Offset Found: RdPtrOffsetDqs = 007
N6.C3.D1.R0.S09: Offset Found: RdPtrOffsetDqs = 008
ACCM: 00 B0B000B0 0000B000
N2.C0.D0.R0.S14: TxDqs: plus1 = 1, minus1 = 0, PI = 48, DB = 0
N4.C3.D1.R1.S02: Offset Found: RdPtrOffsetDqs = 007
N6.C3.D1.R0: CheckMCTest: passed
ACCM: 00 B0B000B0 0000B000
N2.C0.D0.R0.S14: TxDq : plus1 = 1, minus1 = 0, PI = 17, DB = 0
N4.C3.D1.R1.S03: Offset Found: RdPtrOffsetDqs = 007
N6.C3.D1.R0: CheckMCTest: passed
N0.C3.D1.R0: CheckMCTest: result = 0x3FC00
N2.C0.D0.R0.S15: TxDqs: plus1 = 1, minus1 = 0, PI = 52, DB = 1
N4.C3.D1.R1.S04: Offset Found: RdPtrOffsetDqs = 006
N6.C3.D1.R0.S09: Offset Found: RdPtrOffsetDqs = 008
ACCM: F0 F0F0F0F0 F0F0F000
N2.C0.D0.R0.S15: TxDq : plus1 = 1, minus1 = 0, PI = 20, DB = 0
N4.C3.D1.R1.S05: Offset Found: RdPtrOffsetDqs = 007
N6.C3.D1.R0.S10: Offset Found: RdPtrOffsetDqs = 007
ACCM: F0 F0F0F0F0 F0F0F000
N2.C0.D0.R0.S16: TxDqs: plus1 = 1, minus1 = 0, PI = 03, DB = 1
N4.C3.D1.R1.S06: Offset Found: RdPtrOffsetDqs = 007
N6.C3.D1.R0.S11: Offset Found: RdPtrOffsetDqs = 007
ACCM: 00 F0F000F0 0000F000
N2.C0.D0.R0.S16: TxDq : plus1 = 1, minus1 = 0, PI = 34, DB = 0
N4.C3.D1.R1.S07: Offset Found: RdPtrOffsetDqs = 007
N6.C3.D1.R0.S12: Offset Found: RdPtrOffsetDqs = 007
ACCM: 00 F0F000F0 0000F000
N2.C0.D0.R0.S17: TxDqs: plus1 = 1, minus1 = 0, PI = 43, DB = 0
N4.C3.D1.R1.S08: Offset Found: RdPtrOffsetDqs = 007
N6.C3.D1.R0.S13: Offset Found: RdPtrOffsetDqs = 006
N0.C3.D1.R0: CheckMCTest: result = 0x3FC00
N2.C0.D0.R0.S17: TxDq : plus1 = 1, minus1 = 0, PI = 11, DB = 1
N4.C3.D1.R1: Write Training Coarse, upper nibbles
N6.C3.D1.R0.S14: Offset Found: RdPtrOffsetDqs = 007
N0.C3.D1.R0.S09: Offset Found: RdPtrOffsetDqs = 008
N2.C0.D0.R1.S00: TxDqs: plus1 = 1, minus1 = 0, PI = 49, DB = 1
N4.C3.D1.R1.S09: Dq Delay estimate: 346
N6.C3.D1.R0.S15: Offset Found: RdPtrOffsetDqs = 007
N0.C3.D1.R0: CheckMCTest: passed
N2.C0.D0.R1.S00: TxDq : plus1 = 1, minus1 = 0, PI = 19, DB = 0
N4.C3.D1.R1.S10: Dq Delay estimate: 461
N6.C3.D1.R0.S16: Offset Found: RdPtrOffsetDqs = 007
N0.C3.D1.R0: CheckMCTest: passed
N2.C0.D0.R1.S01: TxDqs: plus1 = 1, minus1 = 0, PI = 28, DB = 0
N4.C3.D1.R1.S11: Dq Delay estimate: 451
N6.C3.D1.R0.S17: Offset Found: RdPtrOffsetDqs = 007
N0.C3.D1.R0.S09: Offset Found: RdPtrOffsetDqs = 008
N2.C0.D0.R1.S01: TxDq : plus1 = 1, minus1 = 0, PI = 59, DB = 1
N4.C3.D1.R1.S12: Dq Delay estimate: 437
N6.C3.D1.R1: Write Training Coarse, lower nibbles / bytes
N0.C3.D1.R0.S10: Offset Found: RdPtrOffsetDqs = 007
N2.C0.D0.R1.S02: TxDqs: plus1 = 1, minus1 = 0, PI = 17, DB = 0
N4.C3.D1.R1.S13: Dq Delay estimate: 402
N6.C3.D1.R1.S00: Dq Delay estimate: 476
N0.C3.D1.R0.S11: Offset Found: RdPtrOffsetDqs = 007
N2.C0.D0.R1.S02: TxDq : plus1 = 1, minus1 = 0, PI = 47, DB = 0
N4.C3.D1.R1.S14: Dq Delay estimate: 411
N6.C3.D1.R1.S01: Dq Delay estimate: 456
N0.C3.D1.R0.S12: Offset Found: RdPtrOffsetDqs = 007
N2.C0.D0.R1.S03: TxDqs: plus1 = 1, minus1 = 0, PI = 63, DB = 1
N4.C3.D1.R1.S15: Dq Delay estimate: 425
N6.C3.D1.R1.S02: Dq Delay estimate: 446
N0.C3.D1.R0.S13: Offset Found: RdPtrOffsetDqs = 006
N2.C0.D0.R1.S03: TxDq : plus1 = 1, minus1 = 0, PI = 31, DB = 0
N4.C3.D1.R1.S16: Dq Delay estimate: 447
N6.C3.D1.R1.S03: Dq Delay estimate: 434
N0.C3.D1.R0.S14: Offset Found: RdPtrOffsetDqs = 007
N2.C0.D0.R1.S04: TxDqs: plus1 = 1, minus1 = 0, PI = 30, DB = 0
N4.C3.D1.R1.S17: Dq Delay estimate: 412
N6.C3.D1.R1.S04: Dq Delay estimate: 394
N0.C3.D1.R0.S15: Offset Found: RdPtrOffsetDqs = 007
N2.C0.D0.R1.S04: TxDq : plus1 = 1, minus1 = 0, PI = 63, DB = 1
ACCM: F0 F0F0F0F0 F0F0F0F0
N6.C3.D1.R1.S05: Dq Delay estimate: 410
N0.C3.D1.R0.S16: Offset Found: RdPtrOffsetDqs = 007
N2.C0.D0.R1.S05: TxDqs: plus1 = 1, minus1 = 0, PI = 47, DB = 0
ACCM: F0 F0F0F0F0 F0F0F0F0
N6.C3.D1.R1.S06: Dq Delay estimate: 423
N0.C3.D1.R0.S17: Offset Found: RdPtrOffsetDqs = 007
N2.C0.D0.R1.S05: TxDq : plus1 = 1, minus1 = 0, PI = 15, DB = 1
ACCM: F0 F0F0F0F0 F0F0F0D0
N6.C3.D1.R1.S07: Dq Delay estimate: 440
N0.C3.D1.R1: Write Training Coarse, lower nibbles / bytes
N2.C0.D0.R1.S06: TxDqs: plus1 = 1, minus1 = 0, PI = 54, DB = 1
ACCM: F0 F0F0F0F0 F0F0F0D0
N6.C3.D1.R1.S08: Dq Delay estimate: 410
N0.C3.D1.R1.S00: Dq Delay estimate: 350
N2.C0.D0.R1.S06: TxDq : plus1 = 1, minus1 = 0, PI = 23, DB = 0
N4.C3.D1.R1: CheckMCTest: result = 0x3FE00
ACCM: 0F 0F0F0F0F 0F0F0F0F
N0.C3.D1.R1.S01: Dq Delay estimate: 461
N2.C0.D0.R1.S07: TxDqs: plus1 = 1, minus1 = 0, PI = 02, DB = 1
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: 0F 0F0F0F0F 0F0F0F0F
N0.C3.D1.R1.S02: Dq Delay estimate: 451
N2.C0.D0.R1.S07: TxDq : plus1 = 1, minus1 = 0, PI = 34, DB = 0
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: 0F 0F0F0F0F 0F0F0F0F
N0.C3.D1.R1.S03: Dq Delay estimate: 436
N2.C0.D0.R1.S08: TxDqs: plus1 = 1, minus1 = 0, PI = 42, DB = 0
ACCM: F0 F0F0F0F0 F0F0F0D0
ACCM: 0F 0F0F0F0F 0F0F0F0F
N0.C3.D1.R1.S04: Dq Delay estimate: 400
N2.C0.D0.R1.S08: TxDq : plus1 = 1, minus1 = 0, PI = 12, DB = 1
ACCM: F0 F0F0F0F0 F0F0F0D0
N6.C3.D1.R1: CheckMCTest: result = 0x1FF
N0.C3.D1.R1.S05: Dq Delay estimate: 413
N2.C0.D0.R1.S09: TxDqs: plus1 = 1, minus1 = 0, PI = 48, DB = 0
N4.C3.D1.R1: CheckMCTest: result = 0x3FE00
ACCM: 0F 0F0F0F0F 0F0F0F0F
N0.C3.D1.R1.S06: Dq Delay estimate: 426
N2.C0.D0.R1.S09: TxDq : plus1 = 1, minus1 = 0, PI = 16, DB = 0
ACCM: F0 F0F0F0F0 F0F0F000
ACCM: 0F 0F0F0F0F 0F0F0F0F
N0.C3.D1.R1.S07: Dq Delay estimate: 447
N2.C0.D0.R1.S10: TxDqs: plus1 = 1, minus1 = 0, PI = 27, DB = 0
ACCM: F0 F0F0F0F0 F0F0F000
ACCM: 0F 0F0F0F0F 0F0F0F0F
N0.C3.D1.R1.S08: Dq Delay estimate: 415
N2.C0.D0.R1.S10: TxDq : plus1 = 1, minus1 = 0, PI = 59, DB = 1
ACCM: 00 B00000B0 00000000
ACCM: 0F 0F0F0F0F 0F0F0F0F
ACCM: 0F 0F0F0F0F 0F0F0F0F
N2.C0.D0.R1.S11: TxDqs: plus1 = 1, minus1 = 0, PI = 18, DB = 0
ACCM: 00 B00000B0 00000000
N6.C3.D1.R1: CheckMCTest: result = 0x1FF
ACCM: 0F 0F0F0F0F 0F0F0F0F
N2.C0.D0.R1.S11: TxDq : plus1 = 1, minus1 = 0, PI = 49, DB = 1
N4.C3.D1.R1: CheckMCTest: result = 0x3FC00
ACCM: 0F 0F0F0F0F 0F0F0F0F
ACCM: 0F 0F0F0F0F 0F0F0F09
N2.C0.D0.R1.S12: TxDqs: plus1 = 0, minus1 = 1, PI = 02, DB = 1
ACCM: F0 F0F0F0F0 F0F0F000
ACCM: 0F 0F0F0F0F 0F0F0F0F
ACCM: 0F 0F0F0F0F 0F0F0F09
N2.C0.D0.R1.S12: TxDq : plus1 = 1, minus1 = 0, PI = 33, DB = 0
ACCM: F0 F0F0F0F0 F0F0F000
ACCM: 00 00000000 0B000000
N0.C3.D1.R1: CheckMCTest: result = 0x1FF
N2.C0.D0.R1.S13: TxDqs: plus1 = 1, minus1 = 0, PI = 31, DB = 0
ACCM: 00 F00000F0 0000D000
ACCM: 00 00000000 0B000000
ACCM: 0F 0F0F0F0F 0F0F0F0F
N2.C0.D0.R1.S13: TxDq : plus1 = 0, minus1 = 1, PI = 01, DB = 1
ACCM: 00 F00000F0 0000D000
N6.C3.D1.R1: CheckMCTest: result = 0x1FF
ACCM: 0F 0F0F0F0F 0F0F0F0F
N2.C0.D0.R1.S14: TxDqs: plus1 = 1, minus1 = 0, PI = 48, DB = 0
N4.C3.D1.R1: CheckMCTest: result = 0x3FC00
ACCM: 0F 0F0F0F0F 0F0F0F0F
ACCM: 0F 0F0F0F0F 0F0F0F0D
N2.C0.D0.R1.S14: TxDq : plus1 = 1, minus1 = 0, PI = 17, DB = 0
N4.C3.D1.R1.S09: Offset Found: RdPtrOffsetDqs = 008
ACCM: 0F 0F0F0F0F 0F0F0F0F
ACCM: 0F 0F0F0F0F 0F0F0F0D
N2.C0.D0.R1.S15: TxDqs: plus1 = 1, minus1 = 0, PI = 52, DB = 1
N4.C3.D1.R1: CheckMCTest: passed
ACCM: 00 00000000 0F000000
N0.C3.D1.R1: CheckMCTest: result = 0x1FF
N2.C0.D0.R1.S15: TxDq : plus1 = 1, minus1 = 0, PI = 20, DB = 0
N4.C3.D1.R1: CheckMCTest: passed
ACCM: 00 00000000 0F000000
ACCM: 0F 0F0F0F0F 0F0F0F00
N2.C0.D0.R1.S16: TxDqs: plus1 = 1, minus1 = 0, PI = 03, DB = 1
N4.C3.D1.R1.S09: Offset Found: RdPtrOffsetDqs = 008
N6.C3.D1.R1: CheckMCTest: result = 0x1FF
ACCM: 0F 0F0F0F0F 0F0F0F00
N2.C0.D0.R1.S16: TxDq : plus1 = 1, minus1 = 0, PI = 34, DB = 0
N4.C3.D1.R1.S10: Offset Found: RdPtrOffsetDqs = 007
N6.C3.D1.R1: CheckMCTest: passed
ACCM: 00 0B0B0B0B 0B000B00
N2.C0.D0.R1.S17: TxDqs: plus1 = 1, minus1 = 0, PI = 43, DB = 0
N4.C3.D1.R1.S11: Offset Found: RdPtrOffsetDqs = 007
N6.C3.D1.R1: CheckMCTest: passed
ACCM: 00 0B0B0B0B 0B000B00
N2.C0.D0.R1.S17: TxDq : plus1 = 1, minus1 = 0, PI = 11, DB = 1
N4.C3.D1.R1.S12: Offset Found: RdPtrOffsetDqs = 007
N6.C3.D1.R1.S00: Offset Found: RdPtrOffsetDqs = 007
N0.C3.D1.R1: CheckMCTest: result = 0x1FE
N2.C0.D1.R0.S00: TxDqs: plus1 = 1, minus1 = 0, PI = 53, DB = 1
N4.C3.D1.R1.S13: Offset Found: RdPtrOffsetDqs = 006
N6.C3.D1.R1.S01: Offset Found: RdPtrOffsetDqs = 007
ACCM: 0F 0F0F0F0F 0F0F0F00
N2.C0.D1.R0.S00: TxDq : plus1 = 1, minus1 = 0, PI = 23, DB = 0
N4.C3.D1.R1.S14: Offset Found: RdPtrOffsetDqs = 007
N6.C3.D1.R1.S02: Offset Found: RdPtrOffsetDqs = 007
ACCM: 0F 0F0F0F0F 0F0F0F00
N2.C0.D1.R0.S01: TxDqs: plus1 = 1, minus1 = 0, PI = 37, DB = 0
N4.C3.D1.R1.S15: Offset Found: RdPtrOffsetDqs = 007
N6.C3.D1.R1.S03: Offset Found: RdPtrOffsetDqs = 007
ACCM: 00 0F0F0F0F 0F000F00
N2.C0.D1.R0.S01: TxDq : plus1 = 0, minus1 = 1, PI = 04, DB = 1
N4.C3.D1.R1.S16: Offset Found: RdPtrOffsetDqs = 007
N6.C3.D1.R1.S04: Offset Found: RdPtrOffsetDqs = 006
ACCM: 00 0F0F0F0F 0F000F00
N2.C0.D1.R0.S02: TxDqs: plus1 = 1, minus1 = 0, PI = 24, DB = 0
N4.C3.D1.R1.S17: Offset Found: RdPtrOffsetDqs = 007
N6.C3.D1.R1.S05: Offset Found: RdPtrOffsetDqs = 006
N0.C3.D1.R1: CheckMCTest: result = 0x1FE
N2.C0.D1.R0.S02: TxDq : plus1 = 1, minus1 = 0, PI = 54, DB = 1
N4.C3: Calculating Optimimum DQS Values
N6.C3.D1.R1.S06: Offset Found: RdPtrOffsetDqs = 007
N0.C3.D1.R1.S00: Offset Found: RdPtrOffsetDqs = 008
N2.C0.D1.R0.S03: TxDqs: plus1 = 0, minus1 = 1, PI = 08, DB = 1
N4.C3.D0.R0.S00: Total Delay in PI ticks: TxDQS = 1025, TxDQ = 987
N6.C3.D1.R1.S07: Offset Found: RdPtrOffsetDqs = 007
N0.C3.D1.R1: CheckMCTest: passed
N2.C0.D1.R0.S03: TxDq : plus1 = 1, minus1 = 0, PI = 40, DB = 0
N4.C3.D0.R0.S01: Total Delay in PI ticks: TxDQS = 1006, TxDQ = 967
N6.C3.D1.R1.S08: Offset Found: RdPtrOffsetDqs = 006
N0.C3.D1.R1: CheckMCTest: passed
N2.C0.D1.R0.S04: TxDqs: plus1 = 1, minus1 = 0, PI = 38, DB = 0
N4.C3.D0.R0.S02: Total Delay in PI ticks: TxDQS = 999, TxDQ = 963
N6.C3.D1.R1: Write Training Coarse, upper nibbles
N0.C3.D1.R1.S00: Offset Found: RdPtrOffsetDqs = 008
N2.C0.D1.R0.S04: TxDq : plus1 = 0, minus1 = 1, PI = 06, DB = 1
N4.C3.D0.R0.S03: Total Delay in PI ticks: TxDQS = 981, TxDQ = 945
N6.C3.D1.R1.S09: Dq Delay estimate: 471
N0.C3.D1.R1.S01: Offset Found: RdPtrOffsetDqs = 007
N2.C0.D1.R0.S05: TxDqs: plus1 = 1, minus1 = 0, PI = 57, DB = 1
N4.C3.D0.R0.S04: Total Delay in PI ticks: TxDQS = 945, TxDQ = 906
N6.C3.D1.R1.S10: Dq Delay estimate: 456
N0.C3.D1.R1.S02: Offset Found: RdPtrOffsetDqs = 007
N2.C0.D1.R0.S05: TxDq : plus1 = 1, minus1 = 0, PI = 24, DB = 0
N4.C3.D0.R0.S05: Total Delay in PI ticks: TxDQS = 959, TxDQ = 921
N6.C3.D1.R1.S11: Dq Delay estimate: 448
N0.C3.D1.R1.S03: Offset Found: RdPtrOffsetDqs = 007
N2.C0.D1.R0.S06: TxDqs: plus1 = 1, minus1 = 0, PI = 60, DB = 1
N4.C3.D0.R0.S06: Total Delay in PI ticks: TxDQS = 973, TxDQ = 934
N6.C3.D1.R1.S12: Dq Delay estimate: 432
N0.C3.D1.R1.S04: Offset Found: RdPtrOffsetDqs = 006
N2.C0.D1.R0.S06: TxDq : plus1 = 1, minus1 = 0, PI = 28, DB = 0
N4.C3.D0.R0.S07: Total Delay in PI ticks: TxDQS = 991, TxDQ = 954
N6.C3.D1.R1.S13: Dq Delay estimate: 395
N0.C3.D1.R1.S05: Offset Found: RdPtrOffsetDqs = 007
N2.C0.D1.R0.S07: TxDqs: plus1 = 1, minus1 = 0, PI = 13, DB = 1
N4.C3.D0.R0.S08: Total Delay in PI ticks: TxDQS = 964, TxDQ = 929
N6.C3.D1.R1.S14: Dq Delay estimate: 414
N0.C3.D1.R1.S06: Offset Found: RdPtrOffsetDqs = 007
N2.C0.D1.R0.S07: TxDq : plus1 = 1, minus1 = 0, PI = 43, DB = 0
N4.C3.D0.R0.S09: Total Delay in PI ticks: TxDQS = 1024, TxDQ = 986
N6.C3.D1.R1.S15: Dq Delay estimate: 423
N0.C3.D1.R1.S07: Offset Found: RdPtrOffsetDqs = 007
N2.C0.D1.R0.S08: TxDqs: plus1 = 1, minus1 = 0, PI = 46, DB = 0
N4.C3.D0.R0.S10: Total Delay in PI ticks: TxDQS = 1005, TxDQ = 969
N6.C3.D1.R1.S16: Dq Delay estimate: 442
N0.C3.D1.R1.S08: Offset Found: RdPtrOffsetDqs = 007
N2.C0.D1.R0.S08: TxDq : plus1 = 1, minus1 = 0, PI = 15, DB = 1
N4.C3.D0.R0.S11: Total Delay in PI ticks: TxDQS = 997, TxDQ = 961
N6.C3.D1.R1.S17: Dq Delay estimate: 409
N0.C3.D1.R1: Write Training Coarse, upper nibbles
N2.C0.D1.R0.S09: TxDqs: plus1 = 1, minus1 = 0, PI = 54, DB = 1
N4.C3.D0.R0.S12: Total Delay in PI ticks: TxDQS = 982, TxDQ = 945
ACCM: F0 F0F0F0F0 F0F0F0F0
N0.C3.D1.R1.S09: Dq Delay estimate: 347
N2.C0.D1.R0.S09: TxDq : plus1 = 1, minus1 = 0, PI = 20, DB = 0
N4.C3.D0.R0.S13: Total Delay in PI ticks: TxDQS = 945, TxDQ = 909
ACCM: F0 F0F0F0F0 F0F0F0F0
N0.C3.D1.R1.S10: Dq Delay estimate: 463
N2.C0.D1.R0.S10: TxDqs: plus1 = 1, minus1 = 0, PI = 36, DB = 0
N4.C3.D0.R0.S14: Total Delay in PI ticks: TxDQS = 958, TxDQ = 920
ACCM: F0 F0F0F0F0 F0F0F0F0
N0.C3.D1.R1.S11: Dq Delay estimate: 452
N2.C0.D1.R0.S10: TxDq : plus1 = 0, minus1 = 1, PI = 04, DB = 1
N4.C3.D0.R0.S15: Total Delay in PI ticks: TxDQS = 975, TxDQ = 937
ACCM: F0 F0F0F0F0 F0F0F0F0
N0.C3.D1.R1.S12: Dq Delay estimate: 439
N2.C0.D1.R0.S11: TxDqs: plus1 = 1, minus1 = 0, PI = 26, DB = 0
N4.C3.D0.R0.S16: Total Delay in PI ticks: TxDQS = 990, TxDQ = 955
N6.C3.D1.R1: CheckMCTest: result = 0x3FE00
N0.C3.D1.R1.S13: Dq Delay estimate: 403
N2.C0.D1.R0.S11: TxDq : plus1 = 1, minus1 = 0, PI = 56, DB = 1
N4.C3.D0.R0.S17: Total Delay in PI ticks: TxDQS = 962, TxDQ = 925
ACCM: F0 F0F0F0F0 F0F0F0F0
N0.C3.D1.R1.S14: Dq Delay estimate: 416
N2.C0.D1.R0.S12: TxDqs: plus1 = 0, minus1 = 1, PI = 12, DB = 1
N4.C3.D0.R1.S00: Total Delay in PI ticks: TxDQS = 1017, TxDQ = 980
ACCM: F0 F0F0F0F0 F0F0F0F0
N0.C3.D1.R1.S15: Dq Delay estimate: 430
N2.C0.D1.R0.S12: TxDq : plus1 = 1, minus1 = 0, PI = 41, DB = 0
N4.C3.D0.R1.S01: Total Delay in PI ticks: TxDQS = 1001, TxDQ = 962
ACCM: F0 F0F0F0F0 F0F0F0F0
N0.C3.D1.R1.S16: Dq Delay estimate: 444
N2.C0.D1.R0.S13: TxDqs: plus1 = 1, minus1 = 0, PI = 39, DB = 0
N4.C3.D0.R1.S02: Total Delay in PI ticks: TxDQS = 988, TxDQ = 952
ACCM: F0 F0F0F0F0 F0F0F0F0
N0.C3.D1.R1.S17: Dq Delay estimate: 414
N2.C0.D1.R0.S13: TxDq : plus1 = 0, minus1 = 1, PI = 07, DB = 1
N4.C3.D0.R1.S03: Total Delay in PI ticks: TxDQS = 977, TxDQ = 941
N6.C3.D1.R1: CheckMCTest: result = 0x3FE00
ACCM: F0 F0F0F0F0 F0F0F0F0
N2.C0.D1.R0.S14: TxDqs: plus1 = 1, minus1 = 0, PI = 57, DB = 1
N4.C3.D0.R1.S04: Total Delay in PI ticks: TxDQS = 938, TxDQ = 899
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: F0 F0F0F0F0 F0F0F0F0
N2.C0.D1.R0.S14: TxDq : plus1 = 1, minus1 = 0, PI = 25, DB = 0
N4.C3.D0.R1.S05: Total Delay in PI ticks: TxDQS = 951, TxDQ = 913
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: F0 F0F0F0F0 F0F0F000
N2.C0.D1.R0.S15: TxDqs: plus1 = 1, minus1 = 0, PI = 60, DB = 1
N4.C3.D0.R1.S06: Total Delay in PI ticks: TxDQS = 966, TxDQ = 927
ACCM: 00 B00000B0 B00000B0
ACCM: F0 F0F0F0F0 F0F0F000
N2.C0.D1.R0.S15: TxDq : plus1 = 1, minus1 = 0, PI = 27, DB = 0
N4.C3.D0.R1.S07: Total Delay in PI ticks: TxDQS = 985, TxDQ = 948
ACCM: 00 B00000B0 B00000B0
N0.C3.D1.R1: CheckMCTest: result = 0x3FE00
N2.C0.D1.R0.S16: TxDqs: plus1 = 1, minus1 = 0, PI = 12, DB = 1
N4.C3.D0.R1.S08: Total Delay in PI ticks: TxDQS = 954, TxDQ = 919
N6.C3.D1.R1: CheckMCTest: result = 0x3FE00
ACCM: F0 F0F0F0F0 F0F0F0F0
N2.C0.D1.R0.S16: TxDq : plus1 = 1, minus1 = 0, PI = 43, DB = 0
N4.C3.D0.R1.S09: Total Delay in PI ticks: TxDQS = 1015, TxDQ = 978
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: F0 F0F0F0F0 F0F0F0F0
N2.C0.D1.R0.S17: TxDqs: plus1 = 1, minus1 = 0, PI = 47, DB = 0
N4.C3.D0.R1.S10: Total Delay in PI ticks: TxDQS = 1001, TxDQ = 965
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: F0 F0F0F0F0 F0F0F000
N2.C0.D1.R0.S17: TxDq : plus1 = 1, minus1 = 0, PI = 14, DB = 1
N4.C3.D0.R1.S11: Total Delay in PI ticks: TxDQS = 988, TxDQ = 952
ACCM: 00 F000D0F0 B00000F0
ACCM: F0 F0F0F0F0 F0F0F000
N2.C0.D1.R1.S00: TxDqs: plus1 = 1, minus1 = 0, PI = 53, DB = 1
N4.C3.D0.R1.S12: Total Delay in PI ticks: TxDQS = 979, TxDQ = 942
ACCM: 00 F000D0F0 B00000F0
N0.C3.D1.R1: CheckMCTest: result = 0x3FE00
N2.C0.D1.R1.S00: TxDq : plus1 = 1, minus1 = 0, PI = 23, DB = 0
N4.C3.D0.R1.S13: Total Delay in PI ticks: TxDQS = 937, TxDQ = 901
N6.C3.D1.R1: CheckMCTest: result = 0x3FE00
ACCM: F0 F0F0F0F0 F0F0F000
N2.C0.D1.R1.S01: TxDqs: plus1 = 1, minus1 = 0, PI = 37, DB = 0
N4.C3.D0.R1.S14: Total Delay in PI ticks: TxDQS = 953, TxDQ = 916
N6.C3.D1.R1: CheckMCTest: passed
ACCM: F0 F0F0F0F0 F0F0F000
N2.C0.D1.R1.S01: TxDq : plus1 = 0, minus1 = 1, PI = 04, DB = 1
N4.C3.D0.R1.S15: Total Delay in PI ticks: TxDQS = 968, TxDQ = 930
N6.C3.D1.R1: CheckMCTest: passed
ACCM: 00 000000B0 B000B000
N2.C0.D1.R1.S02: TxDqs: plus1 = 1, minus1 = 0, PI = 24, DB = 0
N4.C3.D0.R1.S16: Total Delay in PI ticks: TxDQS = 986, TxDQ = 950
N6.C3.D1.R1.S09: Offset Found: RdPtrOffsetDqs = 007
ACCM: 00 000000B0 B000B000
N2.C0.D1.R1.S02: TxDq : plus1 = 1, minus1 = 0, PI = 54, DB = 1
N4.C3.D0.R1.S17: Total Delay in PI ticks: TxDQS = 954, TxDQ = 917
N6.C3.D1.R1.S10: Offset Found: RdPtrOffsetDqs = 007
N0.C3.D1.R1: CheckMCTest: result = 0x3FC00
N2.C0.D1.R1.S03: TxDqs: plus1 = 0, minus1 = 1, PI = 08, DB = 1
N4.C3.D1.R0.S00: Total Delay in PI ticks: TxDQS = 1028, TxDQ = 988
N6.C3.D1.R1.S11: Offset Found: RdPtrOffsetDqs = 007
ACCM: F0 F0F0F0F0 F0F0F000
N2.C0.D1.R1.S03: TxDq : plus1 = 1, minus1 = 0, PI = 40, DB = 0
N4.C3.D1.R0.S01: Total Delay in PI ticks: TxDQS = 1014, TxDQ = 973
N6.C3.D1.R1.S12: Offset Found: RdPtrOffsetDqs = 007
ACCM: F0 F0F0F0F0 F0F0F000
N2.C0.D1.R1.S04: TxDqs: plus1 = 1, minus1 = 0, PI = 38, DB = 0
N4.C3.D1.R0.S02: Total Delay in PI ticks: TxDQS = 1003, TxDQ = 966
N6.C3.D1.R1.S13: Offset Found: RdPtrOffsetDqs = 006
ACCM: 00 0000D0F0 F000F000
N2.C0.D1.R1.S04: TxDq : plus1 = 0, minus1 = 1, PI = 06, DB = 1
N4.C3.D1.R0.S03: Total Delay in PI ticks: TxDQS = 987, TxDQ = 948
N6.C3.D1.R1.S14: Offset Found: RdPtrOffsetDqs = 006
ACCM: 00 0000D0F0 F000F000
N2.C0.D1.R1.S05: TxDqs: plus1 = 1, minus1 = 0, PI = 57, DB = 1
N4.C3.D1.R0.S04: Total Delay in PI ticks: TxDQS = 953, TxDQ = 912
N6.C3.D1.R1.S15: Offset Found: RdPtrOffsetDqs = 007
N0.C3.D1.R1: CheckMCTest: result = 0x3FC00
N2.C0.D1.R1.S05: TxDq : plus1 = 1, minus1 = 0, PI = 24, DB = 0
N4.C3.D1.R0.S05: Total Delay in PI ticks: TxDQS = 962, TxDQ = 922
N6.C3.D1.R1.S16: Offset Found: RdPtrOffsetDqs = 007
N0.C3.D1.R1.S09: Offset Found: RdPtrOffsetDqs = 008
N2.C0.D1.R1.S06: TxDqs: plus1 = 1, minus1 = 0, PI = 60, DB = 1
N4.C3.D1.R0.S06: Total Delay in PI ticks: TxDQS = 981, TxDQ = 940
N6.C3.D1.R1.S17: Offset Found: RdPtrOffsetDqs = 006
N0.C3.D1.R1: CheckMCTest: passed
N2.C0.D1.R1.S06: TxDq : plus1 = 1, minus1 = 0, PI = 28, DB = 0
N4.C3.D1.R0.S07: Total Delay in PI ticks: TxDQS = 997, TxDQ = 959
N6.C3: Calculating Optimimum DQS Values
N0.C3.D1.R1: CheckMCTest: passed
N2.C0.D1.R1.S07: TxDqs: plus1 = 1, minus1 = 0, PI = 13, DB = 1
N4.C3.D1.R0.S08: Total Delay in PI ticks: TxDQS = 967, TxDQ = 931
N6.C3.D0.R0.S00: Total Delay in PI ticks: TxDQS = 1018, TxDQ = 987
N0.C3.D1.R1.S09: Offset Found: RdPtrOffsetDqs = 008
N2.C0.D1.R1.S07: TxDq : plus1 = 1, minus1 = 0, PI = 43, DB = 0
N4.C3.D1.R0.S09: Total Delay in PI ticks: TxDQS = 1027, TxDQ = 988
N6.C3.D0.R0.S01: Total Delay in PI ticks: TxDQS = 1002, TxDQ = 969
N0.C3.D1.R1.S10: Offset Found: RdPtrOffsetDqs = 007
N2.C0.D1.R1.S08: TxDqs: plus1 = 1, minus1 = 0, PI = 46, DB = 0
N4.C3.D1.R0.S10: Total Delay in PI ticks: TxDQS = 1014, TxDQ = 975
N6.C3.D0.R0.S02: Total Delay in PI ticks: TxDQS = 995, TxDQ = 962
N0.C3.D1.R1.S11: Offset Found: RdPtrOffsetDqs = 007
N2.C0.D1.R1.S08: TxDq : plus1 = 1, minus1 = 0, PI = 15, DB = 1
N4.C3.D1.R0.S11: Total Delay in PI ticks: TxDQS = 1003, TxDQ = 966
N6.C3.D0.R0.S03: Total Delay in PI ticks: TxDQS = 978, TxDQ = 946
N0.C3.D1.R1.S12: Offset Found: RdPtrOffsetDqs = 007
N2.C0.D1.R1.S09: TxDqs: plus1 = 1, minus1 = 0, PI = 54, DB = 1
N4.C3.D1.R0.S12: Total Delay in PI ticks: TxDQS = 991, TxDQ = 952
N6.C3.D0.R0.S04: Total Delay in PI ticks: TxDQS = 941, TxDQ = 905
N0.C3.D1.R1.S13: Offset Found: RdPtrOffsetDqs = 006
N2.C0.D1.R1.S09: TxDq : plus1 = 1, minus1 = 0, PI = 20, DB = 0
N4.C3.D1.R0.S13: Total Delay in PI ticks: TxDQS = 951, TxDQ = 914
N6.C3.D0.R0.S05: Total Delay in PI ticks: TxDQS = 954, TxDQ = 920
N0.C3.D1.R1.S14: Offset Found: RdPtrOffsetDqs = 007
N2.C0.D1.R1.S10: TxDqs: plus1 = 1, minus1 = 0, PI = 36, DB = 0
N4.C3.D1.R0.S14: Total Delay in PI ticks: TxDQS = 968, TxDQ = 929
N6.C3.D0.R0.S06: Total Delay in PI ticks: TxDQS = 970, TxDQ = 937
N0.C3.D1.R1.S15: Offset Found: RdPtrOffsetDqs = 007
N2.C0.D1.R1.S10: TxDq : plus1 = 0, minus1 = 1, PI = 04, DB = 1
N4.C3.D1.R0.S15: Total Delay in PI ticks: TxDQS = 979, TxDQ = 939
N6.C3.D0.R0.S07: Total Delay in PI ticks: TxDQS = 986, TxDQ = 951
N0.C3.D1.R1.S16: Offset Found: RdPtrOffsetDqs = 007
N2.C0.D1.R1.S11: TxDqs: plus1 = 1, minus1 = 0, PI = 26, DB = 0
N4.C3.D1.R0.S16: Total Delay in PI ticks: TxDQS = 997, TxDQ = 960
N6.C3.D0.R0.S08: Total Delay in PI ticks: TxDQS = 960, TxDQ = 927
N0.C3.D1.R1.S17: Offset Found: RdPtrOffsetDqs = 007
N2.C0.D1.R1.S11: TxDq : plus1 = 1, minus1 = 0, PI = 56, DB = 1
N4.C3.D1.R0.S17: Total Delay in PI ticks: TxDQS = 968, TxDQ = 929
N6.C3.D0.R0.S09: Total Delay in PI ticks: TxDQS = 1019, TxDQ = 985
N0.C3: Calculating Optimimum DQS Values
N2.C0.D1.R1.S12: TxDqs: plus1 = 0, minus1 = 1, PI = 12, DB = 1
N4.C3.D1.R1.S00: Total Delay in PI ticks: TxDQS = 1026, TxDQ = 986
N6.C3.D0.R0.S10: Total Delay in PI ticks: TxDQS = 1002, TxDQ = 971
N0.C3.D0.R0.S00: Total Delay in PI ticks: TxDQS = 1026, TxDQ = 992
N2.C0.D1.R1.S12: TxDq : plus1 = 1, minus1 = 0, PI = 41, DB = 0
N4.C3.D1.R1.S01: Total Delay in PI ticks: TxDQS = 1010, TxDQ = 969
N6.C3.D0.R0.S11: Total Delay in PI ticks: TxDQS = 993, TxDQ = 960
N0.C3.D0.R0.S01: Total Delay in PI ticks: TxDQS = 1009, TxDQ = 975
N2.C0.D1.R1.S13: TxDqs: plus1 = 1, minus1 = 0, PI = 39, DB = 0
N4.C3.D1.R1.S02: Total Delay in PI ticks: TxDQS = 999, TxDQ = 961
N6.C3.D0.R0.S12: Total Delay in PI ticks: TxDQS = 976, TxDQ = 942
N0.C3.D0.R0.S02: Total Delay in PI ticks: TxDQS = 998, TxDQ = 965
N2.C0.D1.R1.S13: TxDq : plus1 = 0, minus1 = 1, PI = 07, DB = 1
N4.C3.D1.R1.S03: Total Delay in PI ticks: TxDQS = 986, TxDQ = 947
N6.C3.D0.R0.S13: Total Delay in PI ticks: TxDQS = 941, TxDQ = 907
N0.C3.D0.R0.S03: Total Delay in PI ticks: TxDQS = 979, TxDQ = 945
N2.C0.D1.R1.S14: TxDqs: plus1 = 1, minus1 = 0, PI = 57, DB = 1
N4.C3.D1.R1.S04: Total Delay in PI ticks: TxDQS = 948, TxDQ = 907
N6.C3.D0.R0.S14: Total Delay in PI ticks: TxDQS = 955, TxDQ = 925
N0.C3.D0.R0.S04: Total Delay in PI ticks: TxDQS = 948, TxDQ = 913
N2.C0.D1.R1.S14: TxDq : plus1 = 1, minus1 = 0, PI = 25, DB = 0
N4.C3.D1.R1.S05: Total Delay in PI ticks: TxDQS = 962, TxDQ = 922
N6.C3.D0.R0.S15: Total Delay in PI ticks: TxDQS = 969, TxDQ = 938
N0.C3.D0.R0.S05: Total Delay in PI ticks: TxDQS = 961, TxDQ = 927
N2.C0.D1.R1.S15: TxDqs: plus1 = 1, minus1 = 0, PI = 60, DB = 1
N4.C3.D1.R1.S06: Total Delay in PI ticks: TxDQS = 976, TxDQ = 935
N6.C3.D0.R0.S16: Total Delay in PI ticks: TxDQS = 987, TxDQ = 954
N0.C3.D0.R0.S06: Total Delay in PI ticks: TxDQS = 976, TxDQ = 941
N2.C0.D1.R1.S15: TxDq : plus1 = 1, minus1 = 0, PI = 27, DB = 0
N4.C3.D1.R1.S07: Total Delay in PI ticks: TxDQS = 994, TxDQ = 955
N6.C3.D0.R0.S17: Total Delay in PI ticks: TxDQS = 958, TxDQ = 925
N0.C3.D0.R0.S07: Total Delay in PI ticks: TxDQS = 994, TxDQ = 961
N2.C0.D1.R1.S16: TxDqs: plus1 = 1, minus1 = 0, PI = 12, DB = 1
N4.C3.D1.R1.S08: Total Delay in PI ticks: TxDQS = 963, TxDQ = 926
N6.C3.D0.R1.S00: Total Delay in PI ticks: TxDQS = 1011, TxDQ = 980
N0.C3.D0.R0.S08: Total Delay in PI ticks: TxDQS = 963, TxDQ = 930
N2.C0.D1.R1.S16: TxDq : plus1 = 1, minus1 = 0, PI = 43, DB = 0
N4.C3.D1.R1.S09: Total Delay in PI ticks: TxDQS = 1025, TxDQ = 986
N6.C3.D0.R1.S01: Total Delay in PI ticks: TxDQS = 996, TxDQ = 963
N0.C3.D0.R0.S09: Total Delay in PI ticks: TxDQS = 1025, TxDQ = 989
N2.C0.D1.R1.S17: TxDqs: plus1 = 1, minus1 = 0, PI = 47, DB = 0
N4.C3.D1.R1.S10: Total Delay in PI ticks: TxDQS = 1011, TxDQ = 973
N6.C3.D0.R1.S02: Total Delay in PI ticks: TxDQS = 986, TxDQ = 953
N0.C3.D0.R0.S10: Total Delay in PI ticks: TxDQS = 1009, TxDQ = 976
N2.C0.D1.R1.S17: TxDq : plus1 = 1, minus1 = 0, PI = 14, DB = 1
N4.C3.D1.R1.S11: Total Delay in PI ticks: TxDQS = 1000, TxDQ = 963
N6.C3.D0.R1.S03: Total Delay in PI ticks: TxDQS = 970, TxDQ = 937
N0.C3.D0.R0.S11: Total Delay in PI ticks: TxDQS = 999, TxDQ = 967
END_DATA_TX_DQ
N4.C3.D1.R1.S12: Total Delay in PI ticks: TxDQS = 988, TxDQ = 949
N6.C3.D0.R1.S04: Total Delay in PI ticks: TxDQS = 933, TxDQ = 897
N0.C3.D0.R0.S12: Total Delay in PI ticks: TxDQS = 984, TxDQ = 950
N2.C1.D0.R0.S00: wrcmd2dqsstartlatency: 04
N4.C3.D1.R1.S13: Total Delay in PI ticks: TxDQS = 951, TxDQ = 914
N6.C3.D0.R1.S05: Total Delay in PI ticks: TxDQS = 948, TxDQ = 914
N0.C3.D0.R0.S13: Total Delay in PI ticks: TxDQS = 947, TxDQ = 912
N2.C1.D0.R0.S00: RdPtrOffsetTxDq: 06
N4.C3.D1.R1.S14: Total Delay in PI ticks: TxDQS = 963, TxDQ = 923
N6.C3.D0.R1.S06: Total Delay in PI ticks: TxDQS = 962, TxDQ = 929
N0.C3.D0.R0.S14: Total Delay in PI ticks: TxDQS = 960, TxDQ = 927
N2.C1.D0.R0.S00: RdPtrOffsetTxDqs: 07
N4.C3.D1.R1.S15: Total Delay in PI ticks: TxDQS = 977, TxDQ = 937
N6.C3.D0.R1.S07: Total Delay in PI ticks: TxDQS = 979, TxDQ = 945
N0.C3.D0.R0.S15: Total Delay in PI ticks: TxDQS = 978, TxDQ = 944
N2.C1.D0.R0.S00: PiTxDqs: 50
N4.C3.D1.R1.S16: Total Delay in PI ticks: TxDQS = 996, TxDQ = 959
N6.C3.D0.R1.S08: Total Delay in PI ticks: TxDQS = 951, TxDQ = 918
N0.C3.D0.R0.S16: Total Delay in PI ticks: TxDQS = 989, TxDQ = 956
N2.C1.D0.R0.S01: wrcmd2dqsstartlatency: 04
N4.C3.D1.R1.S17: Total Delay in PI ticks: TxDQS = 963, TxDQ = 924
N6.C3.D0.R1.S09: Total Delay in PI ticks: TxDQS = 1010, TxDQ = 976
N0.C3.D0.R0.S17: Total Delay in PI ticks: TxDQS = 966, TxDQ = 933
N2.C1.D0.R0.S01: RdPtrOffsetTxDq: 05
N4: END WRITE LEVEL COARSE:
N6.C3.D0.R1.S10: Total Delay in PI ticks: TxDQS = 995, TxDQ = 962
N0.C3.D0.R1.S00: Total Delay in PI ticks: TxDQS = 1019, TxDQ = 984
N2.C1.D0.R0.S01: RdPtrOffsetTxDqs: 07
N4: RunTrainStep: Final status = 0
N6.C3.D0.R1.S11: Total Delay in PI ticks: TxDQS = 985, TxDQ = 952
N0.C3.D0.R1.S01: Total Delay in PI ticks: TxDQS = 1001, TxDQ = 967
N2.C1.D0.R0.S01: PiTxDqs: 32

END - Basic Write Level Training       Time         36942 ms
N6.C3.D0.R1.S12: Total Delay in PI ticks: TxDQS = 971, TxDQ = 936
N0.C3.D0.R1.S02: Total Delay in PI ticks: TxDQS = 991, TxDQ = 958
N2.C1.D0.R0.S02: wrcmd2dqsstartlatency: 04

START - Basic Write DQ/DQS Training
N6.C3.D0.R1.S13: Total Delay in PI ticks: TxDQS = 933, TxDQ = 899
N0.C3.D0.R1.S03: Total Delay in PI ticks: TxDQS = 977, TxDQ = 943
N2.C1.D0.R0.S02: RdPtrOffsetTxDq: 05
N4.C0.D0.R0.S00: wrcmd2dqsstartlatency: 04
N6.C3.D0.R1.S14: Total Delay in PI ticks: TxDQS = 947, TxDQ = 918
N0.C3.D0.R1.S04: Total Delay in PI ticks: TxDQS = 943, TxDQ = 908
N2.C1.D0.R0.S02: RdPtrOffsetTxDqs: 07
N4.C0.D0.R0.S00: RdPtrOffsetTxDq: 06
N6.C3.D0.R1.S15: Total Delay in PI ticks: TxDQS = 961, TxDQ = 930
N0.C3.D0.R1.S05: Total Delay in PI ticks: TxDQS = 954, TxDQ = 920
N2.C1.D0.R0.S02: PiTxDqs: 27
N4.C0.D0.R0.S00: RdPtrOffsetTxDqs: 07
N6.C3.D0.R1.S16: Total Delay in PI ticks: TxDQS = 980, TxDQ = 950
N0.C3.D0.R1.S06: Total Delay in PI ticks: TxDQS = 969, TxDQ = 934
N2.C1.D0.R0.S03: wrcmd2dqsstartlatency: 04
N4.C0.D0.R0.S00: PiTxDqs: 60
N6.C3.D0.R1.S17: Total Delay in PI ticks: TxDQS = 949, TxDQ = 915
N0.C3.D0.R1.S07: Total Delay in PI ticks: TxDQS = 987, TxDQ = 954
N2.C1.D0.R0.S03: RdPtrOffsetTxDq: 05
N4.C0.D0.R0.S01: wrcmd2dqsstartlatency: 04
N6.C3.D1.R0.S00: Total Delay in PI ticks: TxDQS = 1026, TxDQ = 992
N0.C3.D0.R1.S08: Total Delay in PI ticks: TxDQS = 957, TxDQ = 925
N2.C1.D0.R0.S03: RdPtrOffsetTxDqs: 07
N4.C0.D0.R0.S01: RdPtrOffsetTxDq: 06
N6.C3.D1.R0.S01: Total Delay in PI ticks: TxDQS = 1008, TxDQ = 974
N0.C3.D0.R1.S09: Total Delay in PI ticks: TxDQS = 1018, TxDQ = 982
N2.C1.D0.R0.S03: PiTxDqs: 08
N4.C0.D0.R0.S01: RdPtrOffsetTxDqs: 07
N6.C3.D1.R0.S02: Total Delay in PI ticks: TxDQS = 996, TxDQ = 962
N0.C3.D0.R1.S10: Total Delay in PI ticks: TxDQS = 1002, TxDQ = 969
N2.C1.D0.R0.S04: wrcmd2dqsstartlatency: 04
N4.C0.D0.R0.S01: PiTxDqs: 40
N6.C3.D1.R0.S03: Total Delay in PI ticks: TxDQS = 983, TxDQ = 949
N0.C3.D0.R1.S11: Total Delay in PI ticks: TxDQS = 991, TxDQ = 958
N2.C1.D0.R0.S04: RdPtrOffsetTxDq: 05
N4.C0.D0.R0.S02: wrcmd2dqsstartlatency: 04
N6.C3.D1.R0.S04: Total Delay in PI ticks: TxDQS = 947, TxDQ = 909
N0.C3.D0.R1.S12: Total Delay in PI ticks: TxDQS = 980, TxDQ = 946
N2.C1.D0.R0.S04: RdPtrOffsetTxDqs: 06
N4.C0.D0.R0.S02: RdPtrOffsetTxDq: 05
N6.C3.D1.R0.S05: Total Delay in PI ticks: TxDQS = 960, TxDQ = 924
N0.C3.D0.R1.S13: Total Delay in PI ticks: TxDQS = 943, TxDQ = 908
N2.C1.D0.R0.S04: PiTxDqs: 40
N4.C0.D0.R0.S02: RdPtrOffsetTxDqs: 07
N6.C3.D1.R0.S06: Total Delay in PI ticks: TxDQS = 975, TxDQ = 939
N0.C3.D0.R1.S14: Total Delay in PI ticks: TxDQS = 955, TxDQ = 922
N2.C1.D0.R0.S05: wrcmd2dqsstartlatency: 04
N4.C0.D0.R0.S02: PiTxDqs: 29
N6.C3.D1.R0.S07: Total Delay in PI ticks: TxDQS = 993, TxDQ = 957
N0.C3.D0.R1.S15: Total Delay in PI ticks: TxDQS = 968, TxDQ = 934
N2.C1.D0.R0.S05: RdPtrOffsetTxDq: 05
N4.C0.D0.R0.S03: wrcmd2dqsstartlatency: 04
N6.C3.D1.R0.S08: Total Delay in PI ticks: TxDQS = 963, TxDQ = 928
N0.C3.D0.R1.S16: Total Delay in PI ticks: TxDQS = 987, TxDQ = 954
N2.C1.D0.R0.S05: RdPtrOffsetTxDqs: 06
N4.C0.D0.R0.S03: RdPtrOffsetTxDq: 05
N6.C3.D1.R0.S09: Total Delay in PI ticks: TxDQS = 1026, TxDQ = 990
N0.C3.D0.R1.S17: Total Delay in PI ticks: TxDQS = 957, TxDQ = 924
N2.C1.D0.R0.S05: PiTxDqs: 55
N4.C0.D0.R0.S03: RdPtrOffsetTxDqs: 07
N6.C3.D1.R0.S10: Total Delay in PI ticks: TxDQS = 1007, TxDQ = 972
N0.C3.D1.R0.S00: Total Delay in PI ticks: TxDQS = 1028, TxDQ = 992
N2.C1.D0.R0.S06: wrcmd2dqsstartlatency: 04
N4.C0.D0.R0.S03: PiTxDqs: 09
N6.C3.D1.R0.S11: Total Delay in PI ticks: TxDQS = 997, TxDQ = 963
N0.C3.D1.R0.S01: Total Delay in PI ticks: TxDQS = 1010, TxDQ = 974
N2.C1.D0.R0.S06: RdPtrOffsetTxDq: 05
N4.C0.D0.R0.S04: wrcmd2dqsstartlatency: 04
N6.C3.D1.R0.S12: Total Delay in PI ticks: TxDQS = 983, TxDQ = 947
N0.C3.D1.R0.S02: Total Delay in PI ticks: TxDQS = 1003, TxDQ = 967
N2.C1.D0.R0.S06: RdPtrOffsetTxDqs: 07
N4.C0.D0.R0.S04: RdPtrOffsetTxDq: 05
N6.C3.D1.R0.S13: Total Delay in PI ticks: TxDQS = 947, TxDQ = 911
N0.C3.D1.R0.S03: Total Delay in PI ticks: TxDQS = 984, TxDQ = 948
N2.C1.D0.R0.S06: PiTxDqs: 03
N4.C0.D0.R0.S04: RdPtrOffsetTxDqs: 06
N6.C3.D1.R0.S14: Total Delay in PI ticks: TxDQS = 961, TxDQ = 929
N0.C3.D1.R0.S04: Total Delay in PI ticks: TxDQS = 950, TxDQ = 914
N2.C1.D0.R0.S07: wrcmd2dqsstartlatency: 04
N4.C0.D0.R0.S04: PiTxDqs: 45
N6.C3.D1.R0.S15: Total Delay in PI ticks: TxDQS = 975, TxDQ = 941
N0.C3.D1.R0.S05: Total Delay in PI ticks: TxDQS = 963, TxDQ = 927
N2.C1.D0.R0.S07: RdPtrOffsetTxDq: 05
N4.C0.D0.R0.S05: wrcmd2dqsstartlatency: 04
N6.C3.D1.R0.S16: Total Delay in PI ticks: TxDQS = 993, TxDQ = 961
N0.C3.D1.R0.S06: Total Delay in PI ticks: TxDQS = 977, TxDQ = 941
N2.C1.D0.R0.S07: RdPtrOffsetTxDqs: 07
N4.C0.D0.R0.S05: RdPtrOffsetTxDq: 05
N6.C3.D1.R0.S17: Total Delay in PI ticks: TxDQS = 963, TxDQ = 927
N0.C3.D1.R0.S07: Total Delay in PI ticks: TxDQS = 996, TxDQ = 961
N2.C1.D0.R0.S07: PiTxDqs: 19
N4.C0.D0.R0.S05: RdPtrOffsetTxDqs: 06
N6.C3.D1.R1.S00: Total Delay in PI ticks: TxDQS = 1020, TxDQ = 988
N0.C3.D1.R0.S08: Total Delay in PI ticks: TxDQS = 964, TxDQ = 930
N2.C1.D0.R0.S08: wrcmd2dqsstartlatency: 04
N4.C0.D0.R0.S05: PiTxDqs: 62
N6.C3.D1.R1.S01: Total Delay in PI ticks: TxDQS = 1003, TxDQ = 968
N0.C3.D1.R0.S09: Total Delay in PI ticks: TxDQS = 1029, TxDQ = 991
N2.C1.D0.R0.S08: RdPtrOffsetTxDq: 05
N4.C0.D0.R0.S06: wrcmd2dqsstartlatency: 04
N6.C3.D1.R1.S02: Total Delay in PI ticks: TxDQS = 992, TxDQ = 958
N0.C3.D1.R0.S10: Total Delay in PI ticks: TxDQS = 1012, TxDQ = 977
N2.C1.D0.R0.S08: RdPtrOffsetTxDqs: 06
N4.C0.D0.R0.S06: RdPtrOffsetTxDq: 05
N6.C3.D1.R1.S03: Total Delay in PI ticks: TxDQS = 980, TxDQ = 946
N0.C3.D1.R0.S11: Total Delay in PI ticks: TxDQS = 1002, TxDQ = 969
N2.C1.D0.R0.S08: PiTxDqs: 55
N4.C0.D0.R0.S06: RdPtrOffsetTxDqs: 06
N6.C3.D1.R1.S04: Total Delay in PI ticks: TxDQS = 944, TxDQ = 906
N0.C3.D1.R0.S12: Total Delay in PI ticks: TxDQS = 986, TxDQ = 951
N2.C1.D0.R0.S09: wrcmd2dqsstartlatency: 04
N4.C0.D0.R0.S06: PiTxDqs: 62
N6.C3.D1.R1.S05: Total Delay in PI ticks: TxDQS = 957, TxDQ = 922
N0.C3.D1.R0.S13: Total Delay in PI ticks: TxDQS = 951, TxDQ = 915
N2.C1.D0.R0.S09: RdPtrOffsetTxDq: 06
N4.C0.D0.R0.S07: wrcmd2dqsstartlatency: 04
N6.C3.D1.R1.S06: Total Delay in PI ticks: TxDQS = 971, TxDQ = 935
N0.C3.D1.R0.S14: Total Delay in PI ticks: TxDQS = 964, TxDQ = 930
N2.C1.D0.R0.S09: RdPtrOffsetTxDqs: 07
N4.C0.D0.R0.S07: RdPtrOffsetTxDq: 05
N6.C3.D1.R1.S07: Total Delay in PI ticks: TxDQS = 988, TxDQ = 952
N0.C3.D1.R0.S15: Total Delay in PI ticks: TxDQS = 979, TxDQ = 944
N2.C1.D0.R0.S09: PiTxDqs: 50
N4.C0.D0.R0.S07: RdPtrOffsetTxDqs: 07
N6.C3.D1.R1.S08: Total Delay in PI ticks: TxDQS = 957, TxDQ = 922
N0.C3.D1.R0.S16: Total Delay in PI ticks: TxDQS = 994, TxDQ = 959
N2.C1.D0.R0.S10: wrcmd2dqsstartlatency: 04
N4.C0.D0.R0.S07: PiTxDqs: 14
N6.C3.D1.R1.S09: Total Delay in PI ticks: TxDQS = 1019, TxDQ = 983
N0.C3.D1.R0.S17: Total Delay in PI ticks: TxDQS = 962, TxDQ = 927
N2.C1.D0.R0.S10: RdPtrOffsetTxDq: 06
N4.C0.D0.R0.S08: wrcmd2dqsstartlatency: 04
N6.C3.D1.R1.S10: Total Delay in PI ticks: TxDQS = 1003, TxDQ = 968
N0.C3.D1.R1.S00: Total Delay in PI ticks: TxDQS = 1026, TxDQ = 990
N2.C1.D0.R0.S10: RdPtrOffsetTxDqs: 07
N4.C0.D0.R0.S08: RdPtrOffsetTxDq: 05
N6.C3.D1.R1.S11: Total Delay in PI ticks: TxDQS = 995, TxDQ = 960
N0.C3.D1.R1.S01: Total Delay in PI ticks: TxDQS = 1009, TxDQ = 973
N2.C1.D0.R0.S10: PiTxDqs: 32
N4.C0.D0.R0.S08: RdPtrOffsetTxDqs: 06
N6.C3.D1.R1.S12: Total Delay in PI ticks: TxDQS = 980, TxDQ = 944
N0.C3.D1.R1.S02: Total Delay in PI ticks: TxDQS = 998, TxDQ = 963
N2.C1.D0.R0.S11: wrcmd2dqsstartlatency: 04
N4.C0.D0.R0.S08: PiTxDqs: 55
N6.C3.D1.R1.S13: Total Delay in PI ticks: TxDQS = 943, TxDQ = 907
N0.C3.D1.R1.S03: Total Delay in PI ticks: TxDQS = 984, TxDQ = 948
N2.C1.D0.R0.S11: RdPtrOffsetTxDq: 05
N4.C0.D0.R0.S09: wrcmd2dqsstartlatency: 04
N6.C3.D1.R1.S14: Total Delay in PI ticks: TxDQS = 957, TxDQ = 926
N0.C3.D1.R1.S04: Total Delay in PI ticks: TxDQS = 948, TxDQ = 912
N2.C1.D0.R0.S11: RdPtrOffsetTxDqs: 07
N4.C0.D0.R0.S09: RdPtrOffsetTxDq: 06
N6.C3.D1.R1.S15: Total Delay in PI ticks: TxDQS = 969, TxDQ = 935
N0.C3.D1.R1.S05: Total Delay in PI ticks: TxDQS = 961, TxDQ = 925
N2.C1.D0.R0.S11: PiTxDqs: 26
N4.C0.D0.R0.S09: RdPtrOffsetTxDqs: 07
N6.C3.D1.R1.S16: Total Delay in PI ticks: TxDQS = 987, TxDQ = 954
N0.C3.D1.R1.S06: Total Delay in PI ticks: TxDQS = 974, TxDQ = 938
N2.C1.D0.R0.S12: wrcmd2dqsstartlatency: 04
N4.C0.D0.R0.S09: PiTxDqs: 58
N6.C3.D1.R1.S17: Total Delay in PI ticks: TxDQS = 957, TxDQ = 921
N0.C3.D1.R1.S07: Total Delay in PI ticks: TxDQS = 994, TxDQ = 959
N2.C1.D0.R0.S12: RdPtrOffsetTxDq: 05
N4.C0.D0.R0.S10: wrcmd2dqsstartlatency: 04
N6: END WRITE LEVEL COARSE:
N0.C3.D1.R1.S08: Total Delay in PI ticks: TxDQS = 961, TxDQ = 927
N2.C1.D0.R0.S12: RdPtrOffsetTxDqs: 07
N4.C0.D0.R0.S10: RdPtrOffsetTxDq: 06
N6: RunTrainStep: Final status = 0
N0.C3.D1.R1.S09: Total Delay in PI ticks: TxDQS = 1025, TxDQ = 987
N2.C1.D0.R0.S12: PiTxDqs: 08
N4.C0.D0.R0.S10: RdPtrOffsetTxDqs: 07

END - Basic Write Level Training       Time         36630 ms
N0.C3.D1.R1.S10: Total Delay in PI ticks: TxDQS = 1010, TxDQ = 975
N2.C1.D0.R0.S13: wrcmd2dqsstartlatency: 04
N4.C0.D0.R0.S10: PiTxDqs: 38

START - Basic Write DQ/DQS Training
N0.C3.D1.R1.S11: Total Delay in PI ticks: TxDQS = 998, TxDQ = 964
N2.C1.D0.R0.S13: RdPtrOffsetTxDq: 05
N4.C0.D0.R0.S11: wrcmd2dqsstartlatency: 04
N6.C0.D0.R0.S00: wrcmd2dqsstartlatency: 04
N0.C3.D1.R1.S12: Total Delay in PI ticks: TxDQS = 985, TxDQ = 951
N2.C1.D0.R0.S13: RdPtrOffsetTxDqs: 06
N4.C0.D0.R0.S11: RdPtrOffsetTxDq: 05
N6.C0.D0.R0.S00: RdPtrOffsetTxDq: 06
N0.C3.D1.R1.S13: Total Delay in PI ticks: TxDQS = 951, TxDQ = 915
N2.C1.D0.R0.S13: PiTxDqs: 40
N4.C0.D0.R0.S11: RdPtrOffsetTxDqs: 07
N6.C0.D0.R0.S00: RdPtrOffsetTxDqs: 07
N0.C3.D1.R1.S14: Total Delay in PI ticks: TxDQS = 962, TxDQ = 928
N2.C1.D0.R0.S14: wrcmd2dqsstartlatency: 04
N4.C0.D0.R0.S11: PiTxDqs: 25
N6.C0.D0.R0.S00: PiTxDqs: 55
N0.C3.D1.R1.S15: Total Delay in PI ticks: TxDQS = 976, TxDQ = 942
N2.C1.D0.R0.S14: RdPtrOffsetTxDq: 05
N4.C0.D0.R0.S12: wrcmd2dqsstartlatency: 04
N6.C0.D0.R0.S01: wrcmd2dqsstartlatency: 04
N0.C3.D1.R1.S16: Total Delay in PI ticks: TxDQS = 990, TxDQ = 956
N2.C1.D0.R0.S14: RdPtrOffsetTxDqs: 06
N4.C0.D0.R0.S12: RdPtrOffsetTxDq: 05
N6.C0.D0.R0.S01: RdPtrOffsetTxDq: 06
N0.C3.D1.R1.S17: Total Delay in PI ticks: TxDQS = 961, TxDQ = 926
N2.C1.D0.R0.S14: PiTxDqs: 54
N4.C0.D0.R0.S12: RdPtrOffsetTxDqs: 07
N6.C0.D0.R0.S01: RdPtrOffsetTxDqs: 07
N0: END WRITE LEVEL COARSE:
N2.C1.D0.R0.S15: wrcmd2dqsstartlatency: 04
N4.C0.D0.R0.S12: PiTxDqs: 10
N6.C0.D0.R0.S01: PiTxDqs: 33
N0: RunTrainStep: Final status = 0
N2.C1.D0.R0.S15: RdPtrOffsetTxDq: 05
N4.C0.D0.R0.S13: wrcmd2dqsstartlatency: 04
N6.C0.D0.R0.S02: wrcmd2dqsstartlatency: 04

END - Basic Write Level Training       Time         36723 ms
N2.C1.D0.R0.S15: RdPtrOffsetTxDqs: 07
N4.C0.D0.R0.S13: RdPtrOffsetTxDq: 05
N6.C0.D0.R0.S02: RdPtrOffsetTxDq: 05

START - Basic Write DQ/DQS Training
N2.C1.D0.R0.S15: PiTxDqs: 03
N4.C0.D0.R0.S13: RdPtrOffsetTxDqs: 06
N6.C0.D0.R0.S02: RdPtrOffsetTxDqs: 07
Checkpoint Code: Socket 0, 0xB7, 0x05, 0x0000
N2.C1.D0.R0.S16: wrcmd2dqsstartlatency: 04
N4.C0.D0.R0.S13: PiTxDqs: 44
N6.C0.D0.R0.S02: PiTxDqs: 23
N0.C0.D0.R0.S00: wrcmd2dqsstartlatency: 04
N2.C1.D0.R0.S16: RdPtrOffsetTxDq: 05
N4.C0.D0.R0.S14: wrcmd2dqsstartlatency: 04
N6.C0.D0.R0.S03: wrcmd2dqsstartlatency: 04
N0.C0.D0.R0.S00: RdPtrOffsetTxDq: 06
N2.C1.D0.R0.S16: RdPtrOffsetTxDqs: 07
N4.C0.D0.R0.S14: RdPtrOffsetTxDq: 05
N6.C0.D0.R0.S03: RdPtrOffsetTxDq: 05
N0.C0.D0.R0.S00: RdPtrOffsetTxDqs: 07
N2.C1.D0.R0.S16: PiTxDqs: 22
N4.C0.D0.R0.S14: RdPtrOffsetTxDqs: 06
N6.C0.D0.R0.S03: RdPtrOffsetTxDqs: 07
N0.C0.D0.R0.S00: PiTxDqs: 55
N2.C1.D0.R0.S17: wrcmd2dqsstartlatency: 04
N4.C0.D0.R0.S14: PiTxDqs: 57
N6.C0.D0.R0.S03: PiTxDqs: 06
N0.C0.D0.R0.S01: wrcmd2dqsstartlatency: 04
N2.C1.D0.R0.S17: RdPtrOffsetTxDq: 05
N4.C0.D0.R0.S15: wrcmd2dqsstartlatency: 04
N6.C0.D0.R0.S04: wrcmd2dqsstartlatency: 04
N0.C0.D0.R0.S01: RdPtrOffsetTxDq: 06
N2.C1.D0.R0.S17: RdPtrOffsetTxDqs: 06
N4.C0.D0.R0.S15: RdPtrOffsetTxDq: 05
N6.C0.D0.R0.S04: RdPtrOffsetTxDq: 05
N0.C0.D0.R0.S01: RdPtrOffsetTxDqs: 07
N2.C1.D0.R0.S17: PiTxDqs: 54
N4.C0.D0.R0.S15: RdPtrOffsetTxDqs: 06
N6.C0.D0.R0.S04: RdPtrOffsetTxDqs: 06
N0.C0.D0.R0.S01: PiTxDqs: 37
N2.C1.D0.R0.S00: RdPtrOffsetTxDq: 07
N4.C0.D0.R0.S15: PiTxDqs: 61
N6.C0.D0.R0.S04: PiTxDqs: 36
N0.C0.D0.R0.S02: wrcmd2dqsstartlatency: 04
N2.C1.D0.R0.S01: RdPtrOffsetTxDq: 06
N4.C0.D0.R0.S16: wrcmd2dqsstartlatency: 04
N6.C0.D0.R0.S05: wrcmd2dqsstartlatency: 04
N0.C0.D0.R0.S02: RdPtrOffsetTxDq: 05
N2.C1.D0.R0.S02: RdPtrOffsetTxDq: 06
N4.C0.D0.R0.S16: RdPtrOffsetTxDq: 05
N6.C0.D0.R0.S05: RdPtrOffsetTxDq: 05
N0.C0.D0.R0.S02: RdPtrOffsetTxDqs: 07
N2.C1.D0.R0.S03: RdPtrOffsetTxDq: 06
N4.C0.D0.R0.S16: RdPtrOffsetTxDqs: 07
N6.C0.D0.R0.S05: RdPtrOffsetTxDqs: 06
N0.C0.D0.R0.S02: PiTxDqs: 28
N2.C1.D0.R0.S04: RdPtrOffsetTxDq: 06
N4.C0.D0.R0.S16: PiTxDqs: 14
N6.C0.D0.R0.S05: PiTxDqs: 56
N0.C0.D0.R0.S03: wrcmd2dqsstartlatency: 04
N2.C1.D0.R0.S05: RdPtrOffsetTxDq: 06
N4.C0.D0.R0.S17: wrcmd2dqsstartlatency: 04
N6.C0.D0.R0.S06: wrcmd2dqsstartlatency: 04
N0.C0.D0.R0.S03: RdPtrOffsetTxDq: 05
N2.C1.D0.R0.S06: RdPtrOffsetTxDq: 06
N4.C0.D0.R0.S17: RdPtrOffsetTxDq: 05
N6.C0.D0.R0.S06: RdPtrOffsetTxDq: 05
N0.C0.D0.R0.S03: RdPtrOffsetTxDqs: 07
N2.C1.D0.R0.S07: RdPtrOffsetTxDq: 06
N4.C0.D0.R0.S17: RdPtrOffsetTxDqs: 06
N6.C0.D0.R0.S06: RdPtrOffsetTxDqs: 06
N0.C0.D0.R0.S03: PiTxDqs: 09
N2.C1.D0.R0.S08: RdPtrOffsetTxDq: 06
N4.C0.D0.R0.S17: PiTxDqs: 55
N6.C0.D0.R0.S06: PiTxDqs: 60
N0.C0.D0.R0.S04: wrcmd2dqsstartlatency: 04
N2.C1.D0.R0.S09: RdPtrOffsetTxDq: 07
N4.C0.D0.R0.S00: RdPtrOffsetTxDq: 07
N6.C0.D0.R0.S07: wrcmd2dqsstartlatency: 04
N0.C0.D0.R0.S04: RdPtrOffsetTxDq: 05
N2.C1.D0.R0.S10: RdPtrOffsetTxDq: 07
N4.C0.D0.R0.S01: RdPtrOffsetTxDq: 07
N6.C0.D0.R0.S07: RdPtrOffsetTxDq: 05
N0.C0.D0.R0.S04: RdPtrOffsetTxDqs: 06
N2.C1.D0.R0.S11: RdPtrOffsetTxDq: 06
N4.C0.D0.R0.S02: RdPtrOffsetTxDq: 06
N6.C0.D0.R0.S07: RdPtrOffsetTxDqs: 07
N0.C0.D0.R0.S04: PiTxDqs: 41
N2.C1.D0.R0.S12: RdPtrOffsetTxDq: 06
N4.C0.D0.R0.S03: RdPtrOffsetTxDq: 06
N6.C0.D0.R0.S07: PiTxDqs: 13
N0.C0.D0.R0.S05: wrcmd2dqsstartlatency: 04
N2.C1.D0.R0.S13: RdPtrOffsetTxDq: 06
N4.C0.D0.R0.S04: RdPtrOffsetTxDq: 06
N6.C0.D0.R0.S08: wrcmd2dqsstartlatency: 04
N0.C0.D0.R0.S05: RdPtrOffsetTxDq: 05
N2.C1.D0.R0.S14: RdPtrOffsetTxDq: 06
N4.C0.D0.R0.S05: RdPtrOffsetTxDq: 06
N6.C0.D0.R0.S08: RdPtrOffsetTxDq: 05
N0.C0.D0.R0.S05: RdPtrOffsetTxDqs: 06
N2.C1.D0.R0.S15: RdPtrOffsetTxDq: 06
N4.C0.D0.R0.S06: RdPtrOffsetTxDq: 06
N6.C0.D0.R0.S08: RdPtrOffsetTxDqs: 06
N0.C0.D0.R0.S05: PiTxDqs: 57
N2.C1.D0.R0.S16: RdPtrOffsetTxDq: 06
N4.C0.D0.R0.S07: RdPtrOffsetTxDq: 06
N6.C0.D0.R0.S08: PiTxDqs: 50
N0.C0.D0.R0.S06: wrcmd2dqsstartlatency: 04
N2.C1.D0.R0.S17: RdPtrOffsetTxDq: 06
N4.C0.D0.R0.S08: RdPtrOffsetTxDq: 06
N6.C0.D0.R0.S09: wrcmd2dqsstartlatency: 04
N0.C0.D0.R0.S06: RdPtrOffsetTxDq: 05
N2.C1.D0.R0.S00: RdPtrOffsetTxDq: 08
N4.C0.D0.R0.S09: RdPtrOffsetTxDq: 07
N6.C0.D0.R0.S09: RdPtrOffsetTxDq: 06
N0.C0.D0.R0.S06: RdPtrOffsetTxDqs: 06
N2.C1.D0.R0.S01: RdPtrOffsetTxDq: 07
N4.C0.D0.R0.S10: RdPtrOffsetTxDq: 07
N6.C0.D0.R0.S09: RdPtrOffsetTxDqs: 07
N0.C0.D0.R0.S06: PiTxDqs: 61
N2.C1.D0.R0.S02: RdPtrOffsetTxDq: 07
N4.C0.D0.R0.S11: RdPtrOffsetTxDq: 06
N6.C0.D0.R0.S09: PiTxDqs: 56
N0.C0.D0.R0.S07: wrcmd2dqsstartlatency: 04
N2.C1.D0.R0.S03: RdPtrOffsetTxDq: 07
N4.C0.D0.R0.S12: RdPtrOffsetTxDq: 06
N6.C0.D0.R0.S10: wrcmd2dqsstartlatency: 04
N0.C0.D0.R0.S07: RdPtrOffsetTxDq: 05
N2.C1.D0.R0.S04: RdPtrOffsetTxDq: 07
N4.C0.D0.R0.S13: RdPtrOffsetTxDq: 06
N6.C0.D0.R0.S10: RdPtrOffsetTxDq: 06
N0.C0.D0.R0.S07: RdPtrOffsetTxDqs: 07
N2.C1.D0.R0.S05: RdPtrOffsetTxDq: 07
N4.C0.D0.R0.S14: RdPtrOffsetTxDq: 06
N6.C0.D0.R0.S10: RdPtrOffsetTxDqs: 07
N0.C0.D0.R0.S07: PiTxDqs: 14
N2.C1.D0.R0.S06: RdPtrOffsetTxDq: 07
N4.C0.D0.R0.S15: RdPtrOffsetTxDq: 06
N6.C0.D0.R0.S10: PiTxDqs: 33
N0.C0.D0.R0.S08: wrcmd2dqsstartlatency: 04
N2.C1.D0.R0.S07: RdPtrOffsetTxDq: 07
N4.C0.D0.R0.S16: RdPtrOffsetTxDq: 06
N6.C0.D0.R0.S11: wrcmd2dqsstartlatency: 04
N0.C0.D0.R0.S08: RdPtrOffsetTxDq: 05
N2.C1.D0.R0.S08: RdPtrOffsetTxDq: 07
N4.C0.D0.R0.S17: RdPtrOffsetTxDq: 06
N6.C0.D0.R0.S11: RdPtrOffsetTxDq: 05
N0.C0.D0.R0.S08: RdPtrOffsetTxDqs: 06
N2.C1.D0.R0.S09: RdPtrOffsetTxDq: 08
N4.C0.D0.R0.S00: RdPtrOffsetTxDq: 08
N6.C0.D0.R0.S11: RdPtrOffsetTxDqs: 07
N0.C0.D0.R0.S08: PiTxDqs: 52
N2.C1.D0.R0.S10: RdPtrOffsetTxDq: 08
N4.C0.D0.R0.S01: RdPtrOffsetTxDq: 08
N6.C0.D0.R0.S11: PiTxDqs: 23
N0.C0.D0.R0.S09: wrcmd2dqsstartlatency: 04
N2.C1.D0.R0.S11: RdPtrOffsetTxDq: 07
N4.C0.D0.R0.S02: RdPtrOffsetTxDq: 07
N6.C0.D0.R0.S12: wrcmd2dqsstartlatency: 04
N0.C0.D0.R0.S09: RdPtrOffsetTxDq: 06
N2.C1.D0.R0.S12: RdPtrOffsetTxDq: 07
N4.C0.D0.R0.S03: RdPtrOffsetTxDq: 07
N6.C0.D0.R0.S12: RdPtrOffsetTxDq: 05
N0.C0.D0.R0.S09: RdPtrOffsetTxDqs: 07
N2.C1.D0.R0.S13: RdPtrOffsetTxDq: 07
N4.C0.D0.R0.S04: RdPtrOffsetTxDq: 07
N6.C0.D0.R0.S12: RdPtrOffsetTxDqs: 07
N0.C0.D0.R0.S09: PiTxDqs: 57
N2.C1.D0.R0.S14: RdPtrOffsetTxDq: 07
N4.C0.D0.R0.S05: RdPtrOffsetTxDq: 07
N6.C0.D0.R0.S12: PiTxDqs: 07
N0.C0.D0.R0.S10: wrcmd2dqsstartlatency: 04
N2.C1.D0.R0.S15: RdPtrOffsetTxDq: 07
N4.C0.D0.R0.S06: RdPtrOffsetTxDq: 07
N6.C0.D0.R0.S13: wrcmd2dqsstartlatency: 04
N0.C0.D0.R0.S10: RdPtrOffsetTxDq: 06
N2.C1.D0.R0.S16: RdPtrOffsetTxDq: 07
N4.C0.D0.R0.S07: RdPtrOffsetTxDq: 07
N6.C0.D0.R0.S13: RdPtrOffsetTxDq: 05
N0.C0.D0.R0.S10: RdPtrOffsetTxDqs: 07
N2.C1.D0.R0.S17: RdPtrOffsetTxDq: 07
N4.C0.D0.R0.S08: RdPtrOffsetTxDq: 07
N6.C0.D0.R0.S13: RdPtrOffsetTxDqs: 06
N0.C0.D0.R0.S10: PiTxDqs: 37
N2.C1.D0.R0.S00: Total Delay in PI ticks: TxDQ = 980
N4.C0.D0.R0.S09: RdPtrOffsetTxDq: 08
N6.C0.D0.R0.S13: PiTxDqs: 37
N0.C0.D0.R0.S11: wrcmd2dqsstartlatency: 04
N2.C1.D0.R0.S01: Total Delay in PI ticks: TxDQ = 959
N4.C0.D0.R0.S10: RdPtrOffsetTxDq: 08
N6.C0.D0.R0.S14: wrcmd2dqsstartlatency: 04
N0.C0.D0.R0.S11: RdPtrOffsetTxDq: 05
N2.C1.D0.R0.S02: Total Delay in PI ticks: TxDQ = 955
N4.C0.D0.R0.S11: RdPtrOffsetTxDq: 07
N6.C0.D0.R0.S14: RdPtrOffsetTxDq: 05
N0.C0.D0.R0.S11: RdPtrOffsetTxDqs: 07
N2.C1.D0.R0.S03: Total Delay in PI ticks: TxDQ = 937
N4.C0.D0.R0.S12: RdPtrOffsetTxDq: 07
N6.C0.D0.R0.S14: RdPtrOffsetTxDqs: 06
N0.C0.D0.R0.S11: PiTxDqs: 28
N2.C1.D0.R0.S04: Total Delay in PI ticks: TxDQ = 905
N4.C0.D0.R0.S13: RdPtrOffsetTxDq: 07
N6.C0.D0.R0.S14: PiTxDqs: 56
N0.C0.D0.R0.S12: wrcmd2dqsstartlatency: 04
N2.C1.D0.R0.S05: Total Delay in PI ticks: TxDQ = 917
N4.C0.D0.R0.S14: RdPtrOffsetTxDq: 07
N6.C0.D0.R0.S15: wrcmd2dqsstartlatency: 04
N0.C0.D0.R0.S12: RdPtrOffsetTxDq: 05
N2.C1.D0.R0.S06: Total Delay in PI ticks: TxDQ = 933
N4.C0.D0.R0.S15: RdPtrOffsetTxDq: 07
N6.C0.D0.R0.S15: RdPtrOffsetTxDq: 05
N0.C0.D0.R0.S12: RdPtrOffsetTxDqs: 07
N2.C1.D0.R0.S07: Total Delay in PI ticks: TxDQ = 945
N4.C0.D0.R0.S16: RdPtrOffsetTxDq: 07
N6.C0.D0.R0.S15: RdPtrOffsetTxDqs: 06
N0.C0.D0.R0.S12: PiTxDqs: 12
N2.C1.D0.R0.S08: Total Delay in PI ticks: TxDQ = 919
N4.C0.D0.R0.S17: RdPtrOffsetTxDq: 07
N6.C0.D0.R0.S15: PiTxDqs: 59
N0.C0.D0.R0.S13: wrcmd2dqsstartlatency: 04
N2.C1.D0.R0.S09: Total Delay in PI ticks: TxDQ = 980
N4.C0.D0.R0.S00: Total Delay in PI ticks: TxDQ = 986
N6.C0.D0.R0.S16: wrcmd2dqsstartlatency: 04
N0.C0.D0.R0.S13: RdPtrOffsetTxDq: 05
N2.C1.D0.R0.S10: Total Delay in PI ticks: TxDQ = 960
N4.C0.D0.R0.S01: Total Delay in PI ticks: TxDQ = 966
N6.C0.D0.R0.S16: RdPtrOffsetTxDq: 05
N0.C0.D0.R0.S13: RdPtrOffsetTxDqs: 06
N2.C1.D0.R0.S11: Total Delay in PI ticks: TxDQ = 957
N4.C0.D0.R0.S02: Total Delay in PI ticks: TxDQ = 954
N6.C0.D0.R0.S16: RdPtrOffsetTxDqs: 07
N0.C0.D0.R0.S13: PiTxDqs: 42
N2.C1.D0.R0.S12: Total Delay in PI ticks: TxDQ = 937
N4.C0.D0.R0.S03: Total Delay in PI ticks: TxDQ = 935
N6.C0.D0.R0.S16: PiTxDqs: 11
N0.C0.D0.R0.S14: wrcmd2dqsstartlatency: 04
N2.C1.D0.R0.S13: Total Delay in PI ticks: TxDQ = 905
N4.C0.D0.R0.S04: Total Delay in PI ticks: TxDQ = 907
N6.C0.D0.R0.S17: wrcmd2dqsstartlatency: 04
N0.C0.D0.R0.S14: RdPtrOffsetTxDq: 05
N2.C1.D0.R0.S14: Total Delay in PI ticks: TxDQ = 917
N4.C0.D0.R0.S05: Total Delay in PI ticks: TxDQ = 923
N6.C0.D0.R0.S17: RdPtrOffsetTxDq: 05
N0.C0.D0.R0.S14: RdPtrOffsetTxDqs: 06
N2.C1.D0.R0.S15: Total Delay in PI ticks: TxDQ = 933
N4.C0.D0.R0.S06: Total Delay in PI ticks: TxDQ = 924
N6.C0.D0.R0.S17: RdPtrOffsetTxDqs: 06
N0.C0.D0.R0.S14: PiTxDqs: 57
N2.C1.D0.R0.S16: Total Delay in PI ticks: TxDQ = 949
N4.C0.D0.R0.S07: Total Delay in PI ticks: TxDQ = 941
N6.C0.D0.R0.S17: PiTxDqs: 52
N0.C0.D0.R0.S15: wrcmd2dqsstartlatency: 04
N2.C1.D0.R0.S17: Total Delay in PI ticks: TxDQ = 919
N4.C0.D0.R0.S08: Total Delay in PI ticks: TxDQ = 916
N6.C0.D0.R0.S00: RdPtrOffsetTxDq: 07
N0.C0.D0.R0.S15: RdPtrOffsetTxDq: 05
N2.C1.D0.R1.S00: wrcmd2dqsstartlatency: 04
N4.C0.D0.R0.S09: Total Delay in PI ticks: TxDQ = 986
N6.C0.D0.R0.S01: RdPtrOffsetTxDq: 07
N0.C0.D0.R0.S15: RdPtrOffsetTxDqs: 06
N2.C1.D0.R1.S00: RdPtrOffsetTxDq: 06
N4.C0.D0.R0.S10: Total Delay in PI ticks: TxDQ = 963
N6.C0.D0.R0.S02: RdPtrOffsetTxDq: 06
N0.C0.D0.R0.S15: PiTxDqs: 61
N2.C1.D0.R1.S00: RdPtrOffsetTxDqs: 07
N4.C0.D0.R0.S11: Total Delay in PI ticks: TxDQ = 952
N6.C0.D0.R0.S03: RdPtrOffsetTxDq: 06
N0.C0.D0.R0.S16: wrcmd2dqsstartlatency: 04
N2.C1.D0.R1.S00: PiTxDqs: 42
N4.C0.D0.R0.S12: Total Delay in PI ticks: TxDQ = 936
N6.C0.D0.R0.S04: RdPtrOffsetTxDq: 06
N0.C0.D0.R0.S16: RdPtrOffsetTxDq: 05
N2.C1.D0.R1.S01: wrcmd2dqsstartlatency: 04
N4.C0.D0.R0.S13: Total Delay in PI ticks: TxDQ = 906
N6.C0.D0.R0.S05: RdPtrOffsetTxDq: 06
N0.C0.D0.R0.S16: RdPtrOffsetTxDqs: 07
N2.C1.D0.R1.S01: RdPtrOffsetTxDq: 05
N4.C0.D0.R0.S14: Total Delay in PI ticks: TxDQ = 921
N6.C0.D0.R0.S06: RdPtrOffsetTxDq: 06
N0.C0.D0.R0.S16: PiTxDqs: 15
N2.C1.D0.R1.S01: RdPtrOffsetTxDqs: 07
N4.C0.D0.R0.S15: Total Delay in PI ticks: TxDQ = 925
N6.C0.D0.R0.S07: RdPtrOffsetTxDq: 06
N0.C0.D0.R0.S17: wrcmd2dqsstartlatency: 04
N2.C1.D0.R1.S01: PiTxDqs: 25
N4.C0.D0.R0.S16: Total Delay in PI ticks: TxDQ = 941
N6.C0.D0.R0.S08: RdPtrOffsetTxDq: 06
N0.C0.D0.R0.S17: RdPtrOffsetTxDq: 05
N2.C1.D0.R1.S02: wrcmd2dqsstartlatency: 04
N4.C0.D0.R0.S17: Total Delay in PI ticks: TxDQ = 917
N6.C0.D0.R0.S09: RdPtrOffsetTxDq: 07
N0.C0.D0.R0.S17: RdPtrOffsetTxDqs: 06
N2.C1.D0.R1.S02: RdPtrOffsetTxDq: 05
N4.C0.D0.R1.S00: wrcmd2dqsstartlatency: 04
N6.C0.D0.R0.S10: RdPtrOffsetTxDq: 07
N0.C0.D0.R0.S17: PiTxDqs: 50
N2.C1.D0.R1.S02: RdPtrOffsetTxDqs: 07
N4.C0.D0.R1.S00: RdPtrOffsetTxDq: 06
N6.C0.D0.R0.S11: RdPtrOffsetTxDq: 06
N0.C0.D0.R0.S00: RdPtrOffsetTxDq: 07
N2.C1.D0.R1.S02: PiTxDqs: 19
N4.C0.D0.R1.S00: RdPtrOffsetTxDqs: 07
N6.C0.D0.R0.S12: RdPtrOffsetTxDq: 06
N0.C0.D0.R0.S01: RdPtrOffsetTxDq: 07
N2.C1.D0.R1.S03: wrcmd2dqsstartlatency: 04
N4.C0.D0.R1.S00: PiTxDqs: 51
N6.C0.D0.R0.S13: RdPtrOffsetTxDq: 06
N0.C0.D0.R0.S02: RdPtrOffsetTxDq: 06
N2.C1.D0.R1.S03: RdPtrOffsetTxDq: 05
N4.C0.D0.R1.S01: wrcmd2dqsstartlatency: 04
N6.C0.D0.R0.S14: RdPtrOffsetTxDq: 06
N0.C0.D0.R0.S03: RdPtrOffsetTxDq: 06
N2.C1.D0.R1.S03: RdPtrOffsetTxDqs: 07
N4.C0.D0.R1.S01: RdPtrOffsetTxDq: 05
N6.C0.D0.R0.S15: RdPtrOffsetTxDq: 06
N0.C0.D0.R0.S04: RdPtrOffsetTxDq: 06
N2.C1.D0.R1.S03: PiTxDqs: 02
N4.C0.D0.R1.S01: RdPtrOffsetTxDqs: 07
N6.C0.D0.R0.S16: RdPtrOffsetTxDq: 06
N0.C0.D0.R0.S05: RdPtrOffsetTxDq: 06
N2.C1.D0.R1.S04: wrcmd2dqsstartlatency: 04
N4.C0.D0.R1.S01: PiTxDqs: 33
N6.C0.D0.R0.S17: RdPtrOffsetTxDq: 06
N0.C0.D0.R0.S06: RdPtrOffsetTxDq: 06
N2.C1.D0.R1.S04: RdPtrOffsetTxDq: 05
N4.C0.D0.R1.S02: wrcmd2dqsstartlatency: 04
N6.C0.D0.R0.S00: RdPtrOffsetTxDq: 08
N0.C0.D0.R0.S07: RdPtrOffsetTxDq: 06
N2.C1.D0.R1.S04: RdPtrOffsetTxDqs: 06
N4.C0.D0.R1.S02: RdPtrOffsetTxDq: 05
N6.C0.D0.R0.S01: RdPtrOffsetTxDq: 08
N0.C0.D0.R0.S08: RdPtrOffsetTxDq: 06
N2.C1.D0.R1.S04: PiTxDqs: 34
N4.C0.D0.R1.S02: RdPtrOffsetTxDqs: 07
N6.C0.D0.R0.S02: RdPtrOffsetTxDq: 07
N0.C0.D0.R0.S09: RdPtrOffsetTxDq: 07
N2.C1.D0.R1.S05: wrcmd2dqsstartlatency: 04
N4.C0.D0.R1.S02: PiTxDqs: 22
N6.C0.D0.R0.S03: RdPtrOffsetTxDq: 07
N0.C0.D0.R0.S10: RdPtrOffsetTxDq: 07
N2.C1.D0.R1.S05: RdPtrOffsetTxDq: 05
N4.C0.D0.R1.S03: wrcmd2dqsstartlatency: 04
N6.C0.D0.R0.S04: RdPtrOffsetTxDq: 07
N0.C0.D0.R0.S11: RdPtrOffsetTxDq: 06
N2.C1.D0.R1.S05: RdPtrOffsetTxDqs: 06
N4.C0.D0.R1.S03: RdPtrOffsetTxDq: 05
N6.C0.D0.R0.S05: RdPtrOffsetTxDq: 07
N0.C0.D0.R0.S12: RdPtrOffsetTxDq: 06
N2.C1.D0.R1.S05: PiTxDqs: 48
N4.C0.D0.R1.S03: RdPtrOffsetTxDqs: 07
N6.C0.D0.R0.S06: RdPtrOffsetTxDq: 07
N0.C0.D0.R0.S13: RdPtrOffsetTxDq: 06
N2.C1.D0.R1.S06: wrcmd2dqsstartlatency: 04
N4.C0.D0.R1.S03: PiTxDqs: 06
N6.C0.D0.R0.S07: RdPtrOffsetTxDq: 07
N0.C0.D0.R0.S14: RdPtrOffsetTxDq: 06
N2.C1.D0.R1.S06: RdPtrOffsetTxDq: 05
N4.C0.D0.R1.S04: wrcmd2dqsstartlatency: 04
N6.C0.D0.R0.S08: RdPtrOffsetTxDq: 07
N0.C0.D0.R0.S15: RdPtrOffsetTxDq: 06
N2.C1.D0.R1.S06: RdPtrOffsetTxDqs: 06
N4.C0.D0.R1.S04: RdPtrOffsetTxDq: 04
N6.C0.D0.R0.S09: RdPtrOffsetTxDq: 08
N0.C0.D0.R0.S16: RdPtrOffsetTxDq: 06
N2.C1.D0.R1.S06: PiTxDqs: 59
N4.C0.D0.R1.S04: RdPtrOffsetTxDqs: 06
N6.C0.D0.R0.S10: RdPtrOffsetTxDq: 08
N0.C0.D0.R0.S17: RdPtrOffsetTxDq: 06
N2.C1.D0.R1.S07: wrcmd2dqsstartlatency: 04
N4.C0.D0.R1.S04: PiTxDqs: 34
N6.C0.D0.R0.S11: RdPtrOffsetTxDq: 07
N0.C0.D0.R0.S00: RdPtrOffsetTxDq: 08
N2.C1.D0.R1.S07: RdPtrOffsetTxDq: 05
N4.C0.D0.R1.S05: wrcmd2dqsstartlatency: 04
N6.C0.D0.R0.S12: RdPtrOffsetTxDq: 07
N0.C0.D0.R0.S01: RdPtrOffsetTxDq: 08
N2.C1.D0.R1.S07: RdPtrOffsetTxDqs: 07
N4.C0.D0.R1.S05: RdPtrOffsetTxDq: 05
N6.C0.D0.R0.S13: RdPtrOffsetTxDq: 07
N0.C0.D0.R0.S02: RdPtrOffsetTxDq: 07
N2.C1.D0.R1.S07: PiTxDqs: 13
N4.C0.D0.R1.S05: RdPtrOffsetTxDqs: 06
N6.C0.D0.R0.S14: RdPtrOffsetTxDq: 07
N0.C0.D0.R0.S03: RdPtrOffsetTxDq: 07
N2.C1.D0.R1.S08: wrcmd2dqsstartlatency: 04
N4.C0.D0.R1.S05: PiTxDqs: 53
N6.C0.D0.R0.S15: RdPtrOffsetTxDq: 07
N0.C0.D0.R0.S04: RdPtrOffsetTxDq: 07
N2.C1.D0.R1.S08: RdPtrOffsetTxDq: 05
N4.C0.D0.R1.S06: wrcmd2dqsstartlatency: 04
N6.C0.D0.R0.S16: RdPtrOffsetTxDq: 07
N0.C0.D0.R0.S05: RdPtrOffsetTxDq: 07
N2.C1.D0.R1.S08: RdPtrOffsetTxDqs: 06
N4.C0.D0.R1.S06: RdPtrOffsetTxDq: 05
N6.C0.D0.R0.S17: RdPtrOffsetTxDq: 07
N0.C0.D0.R0.S06: RdPtrOffsetTxDq: 07
N2.C1.D0.R1.S08: PiTxDqs: 47
N4.C0.D0.R1.S06: RdPtrOffsetTxDqs: 06
N6.C0.D0.R0.S00: Total Delay in PI ticks: TxDQ = 986
N0.C0.D0.R0.S07: RdPtrOffsetTxDq: 07
N2.C1.D0.R1.S09: wrcmd2dqsstartlatency: 04
N4.C0.D0.R1.S06: PiTxDqs: 53
N6.C0.D0.R0.S01: Total Delay in PI ticks: TxDQ = 962
N0.C0.D0.R0.S08: RdPtrOffsetTxDq: 07
N2.C1.D0.R1.S09: RdPtrOffsetTxDq: 06
N4.C0.D0.R1.S07: wrcmd2dqsstartlatency: 04
N6.C0.D0.R0.S02: Total Delay in PI ticks: TxDQ = 950
N0.C0.D0.R0.S09: RdPtrOffsetTxDq: 08
N2.C1.D0.R1.S09: RdPtrOffsetTxDqs: 07
N4.C0.D0.R1.S07: RdPtrOffsetTxDq: 05
N6.C0.D0.R0.S03: Total Delay in PI ticks: TxDQ = 933
N0.C0.D0.R0.S10: RdPtrOffsetTxDq: 08
N2.C1.D0.R1.S09: PiTxDqs: 41
N4.C0.D0.R1.S07: RdPtrOffsetTxDqs: 07
N6.C0.D0.R0.S04: Total Delay in PI ticks: TxDQ = 901
N0.C0.D0.R0.S11: RdPtrOffsetTxDq: 07
N2.C1.D0.R1.S10: wrcmd2dqsstartlatency: 04
N4.C0.D0.R1.S07: PiTxDqs: 06
N6.C0.D0.R0.S05: Total Delay in PI ticks: TxDQ = 919
N0.C0.D0.R0.S12: RdPtrOffsetTxDq: 07
N2.C1.D0.R1.S10: RdPtrOffsetTxDq: 05
N4.C0.D0.R1.S08: wrcmd2dqsstartlatency: 04
N6.C0.D0.R0.S06: Total Delay in PI ticks: TxDQ = 925
N0.C0.D0.R0.S13: RdPtrOffsetTxDq: 07
N2.C1.D0.R1.S10: RdPtrOffsetTxDqs: 07
N4.C0.D0.R1.S08: RdPtrOffsetTxDq: 05
N6.C0.D0.R0.S07: Total Delay in PI ticks: TxDQ = 939
N0.C0.D0.R0.S14: RdPtrOffsetTxDq: 07
N2.C1.D0.R1.S10: PiTxDqs: 25
N4.C0.D0.R1.S08: RdPtrOffsetTxDqs: 06
N6.C0.D0.R0.S08: Total Delay in PI ticks: TxDQ = 916
N0.C0.D0.R0.S15: RdPtrOffsetTxDq: 07
N2.C1.D0.R1.S11: wrcmd2dqsstartlatency: 04
N4.C0.D0.R1.S08: PiTxDqs: 47
N6.C0.D0.R0.S09: Total Delay in PI ticks: TxDQ = 983
N0.C0.D0.R0.S16: RdPtrOffsetTxDq: 07
N2.C1.D0.R1.S11: RdPtrOffsetTxDq: 05
N4.C0.D0.R1.S09: wrcmd2dqsstartlatency: 04
N6.C0.D0.R0.S10: Total Delay in PI ticks: TxDQ = 961
N0.C0.D0.R0.S17: RdPtrOffsetTxDq: 07
N2.C1.D0.R1.S11: RdPtrOffsetTxDqs: 07
N4.C0.D0.R1.S09: RdPtrOffsetTxDq: 06
N6.C0.D0.R0.S11: Total Delay in PI ticks: TxDQ = 952
N0.C0.D0.R0.S00: Total Delay in PI ticks: TxDQ = 983
N2.C1.D0.R1.S11: PiTxDqs: 18
N4.C0.D0.R1.S09: RdPtrOffsetTxDqs: 07
N6.C0.D0.R0.S12: Total Delay in PI ticks: TxDQ = 933
N0.C0.D0.R0.S01: Total Delay in PI ticks: TxDQ = 964
N2.C1.D0.R1.S12: wrcmd2dqsstartlatency: 04
N4.C0.D0.R1.S09: PiTxDqs: 49
N6.C0.D0.R0.S13: Total Delay in PI ticks: TxDQ = 902
N0.C0.D0.R0.S02: Total Delay in PI ticks: TxDQ = 954
N2.C1.D0.R1.S12: RdPtrOffsetTxDq: 05
N4.C0.D0.R1.S10: wrcmd2dqsstartlatency: 04
N6.C0.D0.R0.S14: Total Delay in PI ticks: TxDQ = 920
N0.C0.D0.R0.S03: Total Delay in PI ticks: TxDQ = 936
N2.C1.D0.R1.S12: RdPtrOffsetTxDqs: 07
N4.C0.D0.R1.S10: RdPtrOffsetTxDq: 05
N6.C0.D0.R0.S15: Total Delay in PI ticks: TxDQ = 921
N0.C0.D0.R0.S04: Total Delay in PI ticks: TxDQ = 905
N2.C1.D0.R1.S12: PiTxDqs: 03
N4.C0.D0.R1.S10: RdPtrOffsetTxDqs: 07
N6.C0.D0.R0.S16: Total Delay in PI ticks: TxDQ = 938
N0.C0.D0.R0.S05: Total Delay in PI ticks: TxDQ = 920
N2.C1.D0.R1.S13: wrcmd2dqsstartlatency: 04
N4.C0.D0.R1.S10: PiTxDqs: 33
N6.C0.D0.R0.S17: Total Delay in PI ticks: TxDQ = 916
N0.C0.D0.R0.S06: Total Delay in PI ticks: TxDQ = 923
N2.C1.D0.R1.S13: RdPtrOffsetTxDq: 05
N4.C0.D0.R1.S11: wrcmd2dqsstartlatency: 04
N6.C0.D0.R1.S00: wrcmd2dqsstartlatency: 04
N0.C0.D0.R0.S07: Total Delay in PI ticks: TxDQ = 940
N2.C1.D0.R1.S13: RdPtrOffsetTxDqs: 06
N4.C0.D0.R1.S11: RdPtrOffsetTxDq: 05
N6.C0.D0.R1.S00: RdPtrOffsetTxDq: 06
N0.C0.D0.R0.S08: Total Delay in PI ticks: TxDQ = 915
N2.C1.D0.R1.S13: PiTxDqs: 33
N4.C0.D0.R1.S11: RdPtrOffsetTxDqs: 07
N6.C0.D0.R1.S00: RdPtrOffsetTxDqs: 07
N0.C0.D0.R0.S09: Total Delay in PI ticks: TxDQ = 986
N2.C1.D0.R1.S14: wrcmd2dqsstartlatency: 04
N4.C0.D0.R1.S11: PiTxDqs: 23
N6.C0.D0.R1.S00: PiTxDqs: 48
N0.C0.D0.R0.S10: Total Delay in PI ticks: TxDQ = 964
N2.C1.D0.R1.S14: RdPtrOffsetTxDq: 05
N4.C0.D0.R1.S12: wrcmd2dqsstartlatency: 04
N6.C0.D0.R1.S01: wrcmd2dqsstartlatency: 04
N0.C0.D0.R0.S11: Total Delay in PI ticks: TxDQ = 954
N2.C1.D0.R1.S14: RdPtrOffsetTxDqs: 06
N4.C0.D0.R1.S12: RdPtrOffsetTxDq: 05
N6.C0.D0.R1.S01: RdPtrOffsetTxDq: 05
N0.C0.D0.R0.S12: Total Delay in PI ticks: TxDQ = 938
N2.C1.D0.R1.S14: PiTxDqs: 48
N4.C0.D0.R1.S12: RdPtrOffsetTxDqs: 07
N6.C0.D0.R1.S01: RdPtrOffsetTxDqs: 07
N0.C0.D0.R0.S13: Total Delay in PI ticks: TxDQ = 907
N2.C1.D0.R1.S15: wrcmd2dqsstartlatency: 04
N4.C0.D0.R1.S12: PiTxDqs: 07
N6.C0.D0.R1.S01: PiTxDqs: 28
N0.C0.D0.R0.S14: Total Delay in PI ticks: TxDQ = 921
N2.C1.D0.R1.S15: RdPtrOffsetTxDq: 05
N4.C0.D0.R1.S13: wrcmd2dqsstartlatency: 04
N6.C0.D0.R1.S02: wrcmd2dqsstartlatency: 04
N0.C0.D0.R0.S15: Total Delay in PI ticks: TxDQ = 922
N2.C1.D0.R1.S15: RdPtrOffsetTxDqs: 06
N4.C0.D0.R1.S13: RdPtrOffsetTxDq: 05
N6.C0.D0.R1.S02: RdPtrOffsetTxDq: 05
N0.C0.D0.R0.S16: Total Delay in PI ticks: TxDQ = 941
N2.C1.D0.R1.S15: PiTxDqs: 60
N4.C0.D0.R1.S13: RdPtrOffsetTxDqs: 06
N6.C0.D0.R1.S02: RdPtrOffsetTxDqs: 07
N0.C0.D0.R0.S17: Total Delay in PI ticks: TxDQ = 912
N2.C1.D0.R1.S16: wrcmd2dqsstartlatency: 04
N4.C0.D0.R1.S13: PiTxDqs: 38
N6.C0.D0.R1.S02: PiTxDqs: 17
N0.C0.D0.R1.S00: wrcmd2dqsstartlatency: 04
N2.C1.D0.R1.S16: RdPtrOffsetTxDq: 05
N4.C0.D0.R1.S14: wrcmd2dqsstartlatency: 04
N6.C0.D0.R1.S03: wrcmd2dqsstartlatency: 04
N0.C0.D0.R1.S00: RdPtrOffsetTxDq: 06
N2.C1.D0.R1.S16: RdPtrOffsetTxDqs: 07
N4.C0.D0.R1.S14: RdPtrOffsetTxDq: 05
N6.C0.D0.R1.S03: RdPtrOffsetTxDq: 05
N0.C0.D0.R1.S00: RdPtrOffsetTxDqs: 07
N2.C1.D0.R1.S16: PiTxDqs: 15
N4.C0.D0.R1.S14: RdPtrOffsetTxDqs: 06
N6.C0.D0.R1.S03: RdPtrOffsetTxDqs: 07
N0.C0.D0.R1.S00: PiTxDqs: 50
N2.C1.D0.R1.S17: wrcmd2dqsstartlatency: 04
N4.C0.D0.R1.S14: PiTxDqs: 51
N6.C0.D0.R1.S03: PiTxDqs: 00
N0.C0.D0.R1.S01: wrcmd2dqsstartlatency: 04
N2.C1.D0.R1.S17: RdPtrOffsetTxDq: 05
N4.C0.D0.R1.S15: wrcmd2dqsstartlatency: 04
N6.C0.D0.R1.S04: wrcmd2dqsstartlatency: 04
N0.C0.D0.R1.S01: RdPtrOffsetTxDq: 05
N2.C1.D0.R1.S17: RdPtrOffsetTxDqs: 06
N4.C0.D0.R1.S15: RdPtrOffsetTxDq: 05
N6.C0.D0.R1.S04: RdPtrOffsetTxDq: 04
N0.C0.D0.R1.S01: RdPtrOffsetTxDqs: 07
N2.C1.D0.R1.S17: PiTxDqs: 48
N4.C0.D0.R1.S15: RdPtrOffsetTxDqs: 06
N6.C0.D0.R1.S04: RdPtrOffsetTxDqs: 06
N0.C0.D0.R1.S01: PiTxDqs: 32
N2.C1.D0.R1.S00: RdPtrOffsetTxDq: 07
N4.C0.D0.R1.S15: PiTxDqs: 55
N6.C0.D0.R1.S04: PiTxDqs: 30
N0.C0.D0.R1.S02: wrcmd2dqsstartlatency: 04
N2.C1.D0.R1.S01: RdPtrOffsetTxDq: 06
N4.C0.D0.R1.S16: wrcmd2dqsstartlatency: 04
N6.C0.D0.R1.S05: wrcmd2dqsstartlatency: 04
N0.C0.D0.R1.S02: RdPtrOffsetTxDq: 05
N2.C1.D0.R1.S02: RdPtrOffsetTxDq: 06
N4.C0.D0.R1.S16: RdPtrOffsetTxDq: 05
N6.C0.D0.R1.S05: RdPtrOffsetTxDq: 05
N0.C0.D0.R1.S02: RdPtrOffsetTxDqs: 07
N2.C1.D0.R1.S03: RdPtrOffsetTxDq: 06
N4.C0.D0.R1.S16: RdPtrOffsetTxDqs: 07
N6.C0.D0.R1.S05: RdPtrOffsetTxDqs: 06
N0.C0.D0.R1.S02: PiTxDqs: 19
N2.C1.D0.R1.S04: RdPtrOffsetTxDq: 06
N4.C0.D0.R1.S16: PiTxDqs: 07
N6.C0.D0.R1.S05: PiTxDqs: 50
N0.C0.D0.R1.S03: wrcmd2dqsstartlatency: 04
N2.C1.D0.R1.S05: RdPtrOffsetTxDq: 06
N4.C0.D0.R1.S17: wrcmd2dqsstartlatency: 04
N6.C0.D0.R1.S06: wrcmd2dqsstartlatency: 04
N0.C0.D0.R1.S03: RdPtrOffsetTxDq: 05
N2.C1.D0.R1.S06: RdPtrOffsetTxDq: 06
N4.C0.D0.R1.S17: RdPtrOffsetTxDq: 05
N6.C0.D0.R1.S06: RdPtrOffsetTxDq: 05
N0.C0.D0.R1.S03: RdPtrOffsetTxDqs: 07
N2.C1.D0.R1.S07: RdPtrOffsetTxDq: 06
N4.C0.D0.R1.S17: RdPtrOffsetTxDqs: 06
N6.C0.D0.R1.S06: RdPtrOffsetTxDqs: 06
N0.C0.D0.R1.S03: PiTxDqs: 03
N2.C1.D0.R1.S08: RdPtrOffsetTxDq: 06
N4.C0.D0.R1.S17: PiTxDqs: 44
N6.C0.D0.R1.S06: PiTxDqs: 52
N0.C0.D0.R1.S04: wrcmd2dqsstartlatency: 04
N2.C1.D0.R1.S09: RdPtrOffsetTxDq: 07
N4.C0.D0.R1.S00: RdPtrOffsetTxDq: 07
N6.C0.D0.R1.S07: wrcmd2dqsstartlatency: 04
N0.C0.D0.R1.S04: RdPtrOffsetTxDq: 05
N2.C1.D0.R1.S10: RdPtrOffsetTxDq: 06
N4.C0.D0.R1.S01: RdPtrOffsetTxDq: 06
N6.C0.D0.R1.S07: RdPtrOffsetTxDq: 05
N0.C0.D0.R1.S04: RdPtrOffsetTxDqs: 06
N2.C1.D0.R1.S11: RdPtrOffsetTxDq: 06
N4.C0.D0.R1.S02: RdPtrOffsetTxDq: 06
N6.C0.D0.R1.S07: RdPtrOffsetTxDqs: 07
N0.C0.D0.R1.S04: PiTxDqs: 35
N2.C1.D0.R1.S12: RdPtrOffsetTxDq: 06
N4.C0.D0.R1.S03: RdPtrOffsetTxDq: 06
N6.C0.D0.R1.S07: PiTxDqs: 06
N0.C0.D0.R1.S05: wrcmd2dqsstartlatency: 04
N2.C1.D0.R1.S13: RdPtrOffsetTxDq: 06
N4.C0.D0.R1.S04: RdPtrOffsetTxDq: 05
N6.C0.D0.R1.S08: wrcmd2dqsstartlatency: 04
N0.C0.D0.R1.S05: RdPtrOffsetTxDq: 05
N2.C1.D0.R1.S14: RdPtrOffsetTxDq: 06
N4.C0.D0.R1.S05: RdPtrOffsetTxDq: 06
N6.C0.D0.R1.S08: RdPtrOffsetTxDq: 05
N0.C0.D0.R1.S05: RdPtrOffsetTxDqs: 06
N2.C1.D0.R1.S15: RdPtrOffsetTxDq: 06
N4.C0.D0.R1.S06: RdPtrOffsetTxDq: 06
N6.C0.D0.R1.S08: RdPtrOffsetTxDqs: 06
N0.C0.D0.R1.S05: PiTxDqs: 51
N2.C1.D0.R1.S16: RdPtrOffsetTxDq: 06
N4.C0.D0.R1.S07: RdPtrOffsetTxDq: 06
N6.C0.D0.R1.S08: PiTxDqs: 42
N0.C0.D0.R1.S06: wrcmd2dqsstartlatency: 04
N2.C1.D0.R1.S17: RdPtrOffsetTxDq: 06
N4.C0.D0.R1.S08: RdPtrOffsetTxDq: 06
N6.C0.D0.R1.S09: wrcmd2dqsstartlatency: 04
N0.C0.D0.R1.S06: RdPtrOffsetTxDq: 05
N2.C1.D0.R1.S00: RdPtrOffsetTxDq: 08
N4.C0.D0.R1.S09: RdPtrOffsetTxDq: 07
N6.C0.D0.R1.S09: RdPtrOffsetTxDq: 06
N0.C0.D0.R1.S06: RdPtrOffsetTxDqs: 06
N2.C1.D0.R1.S01: RdPtrOffsetTxDq: 07
N4.C0.D0.R1.S10: RdPtrOffsetTxDq: 06
N6.C0.D0.R1.S09: RdPtrOffsetTxDqs: 07
N0.C0.D0.R1.S06: PiTxDqs: 54
N2.C1.D0.R1.S02: RdPtrOffsetTxDq: 07
N4.C0.D0.R1.S11: RdPtrOffsetTxDq: 06
N6.C0.D0.R1.S09: PiTxDqs: 46
N0.C0.D0.R1.S07: wrcmd2dqsstartlatency: 04
N2.C1.D0.R1.S03: RdPtrOffsetTxDq: 07
N4.C0.D0.R1.S12: RdPtrOffsetTxDq: 06
N6.C0.D0.R1.S10: wrcmd2dqsstartlatency: 04
N0.C0.D0.R1.S07: RdPtrOffsetTxDq: 05
N2.C1.D0.R1.S04: RdPtrOffsetTxDq: 07
N4.C0.D0.R1.S13: RdPtrOffsetTxDq: 06
N6.C0.D0.R1.S10: RdPtrOffsetTxDq: 05
N0.C0.D0.R1.S07: RdPtrOffsetTxDqs: 07
N2.C1.D0.R1.S05: RdPtrOffsetTxDq: 07
N4.C0.D0.R1.S14: RdPtrOffsetTxDq: 06
N6.C0.D0.R1.S10: RdPtrOffsetTxDqs: 07
N0.C0.D0.R1.S07: PiTxDqs: 06
N2.C1.D0.R1.S06: RdPtrOffsetTxDq: 07
N4.C0.D0.R1.S15: RdPtrOffsetTxDq: 06
N6.C0.D0.R1.S10: PiTxDqs: 29
N0.C0.D0.R1.S08: wrcmd2dqsstartlatency: 04
N2.C1.D0.R1.S07: RdPtrOffsetTxDq: 07
N4.C0.D0.R1.S16: RdPtrOffsetTxDq: 06
N6.C0.D0.R1.S11: wrcmd2dqsstartlatency: 04
N0.C0.D0.R1.S08: RdPtrOffsetTxDq: 05
N2.C1.D0.R1.S08: RdPtrOffsetTxDq: 07
N4.C0.D0.R1.S17: RdPtrOffsetTxDq: 06
N6.C0.D0.R1.S11: RdPtrOffsetTxDq: 05
N0.C0.D0.R1.S08: RdPtrOffsetTxDqs: 06
N2.C1.D0.R1.S09: RdPtrOffsetTxDq: 08
N4.C0.D0.R1.S00: RdPtrOffsetTxDq: 08
N6.C0.D0.R1.S11: RdPtrOffsetTxDqs: 07
N0.C0.D0.R1.S08: PiTxDqs: 43
N2.C1.D0.R1.S10: RdPtrOffsetTxDq: 07
N4.C0.D0.R1.S01: RdPtrOffsetTxDq: 07
N6.C0.D0.R1.S11: PiTxDqs: 16
N0.C0.D0.R1.S09: wrcmd2dqsstartlatency: 04
N2.C1.D0.R1.S11: RdPtrOffsetTxDq: 07
N4.C0.D0.R1.S02: RdPtrOffsetTxDq: 07
N6.C0.D0.R1.S12: wrcmd2dqsstartlatency: 04
N0.C0.D0.R1.S09: RdPtrOffsetTxDq: 06
N2.C1.D0.R1.S12: RdPtrOffsetTxDq: 07
N4.C0.D0.R1.S03: RdPtrOffsetTxDq: 07
N6.C0.D0.R1.S12: RdPtrOffsetTxDq: 05
N0.C0.D0.R1.S09: RdPtrOffsetTxDqs: 07
N2.C1.D0.R1.S13: RdPtrOffsetTxDq: 07
N4.C0.D0.R1.S04: RdPtrOffsetTxDq: 06
N6.C0.D0.R1.S12: RdPtrOffsetTxDqs: 07
N0.C0.D0.R1.S09: PiTxDqs: 47
N2.C1.D0.R1.S14: RdPtrOffsetTxDq: 07
N4.C0.D0.R1.S05: RdPtrOffsetTxDq: 07
N6.C0.D0.R1.S12: PiTxDqs: 05
N0.C0.D0.R1.S10: wrcmd2dqsstartlatency: 04
N2.C1.D0.R1.S15: RdPtrOffsetTxDq: 07
N4.C0.D0.R1.S06: RdPtrOffsetTxDq: 07
N6.C0.D0.R1.S13: wrcmd2dqsstartlatency: 04
N0.C0.D0.R1.S10: RdPtrOffsetTxDq: 05
N2.C1.D0.R1.S16: RdPtrOffsetTxDq: 07
N4.C0.D0.R1.S07: RdPtrOffsetTxDq: 07
N6.C0.D0.R1.S13: RdPtrOffsetTxDq: 04
N0.C0.D0.R1.S10: RdPtrOffsetTxDqs: 07
N2.C1.D0.R1.S17: RdPtrOffsetTxDq: 07
N4.C0.D0.R1.S08: RdPtrOffsetTxDq: 07
N6.C0.D0.R1.S13: RdPtrOffsetTxDqs: 06
N0.C0.D0.R1.S10: PiTxDqs: 33
N2.C1.D0.R1.S00: Total Delay in PI ticks: TxDQ = 973
N4.C0.D0.R1.S09: RdPtrOffsetTxDq: 08
N6.C0.D0.R1.S13: PiTxDqs: 31
N0.C0.D0.R1.S11: wrcmd2dqsstartlatency: 04
N2.C1.D0.R1.S01: Total Delay in PI ticks: TxDQ = 953
N4.C0.D0.R1.S10: RdPtrOffsetTxDq: 07
N6.C0.D0.R1.S14: wrcmd2dqsstartlatency: 04
N0.C0.D0.R1.S11: RdPtrOffsetTxDq: 05
N2.C1.D0.R1.S02: Total Delay in PI ticks: TxDQ = 947
N4.C0.D0.R1.S11: RdPtrOffsetTxDq: 07
N6.C0.D0.R1.S14: RdPtrOffsetTxDq: 05
N0.C0.D0.R1.S11: RdPtrOffsetTxDqs: 07
N2.C1.D0.R1.S03: Total Delay in PI ticks: TxDQ = 931
N4.C0.D0.R1.S12: RdPtrOffsetTxDq: 07
N6.C0.D0.R1.S14: RdPtrOffsetTxDqs: 06
N0.C0.D0.R1.S11: PiTxDqs: 21
N2.C1.D0.R1.S04: Total Delay in PI ticks: TxDQ = 898
N4.C0.D0.R1.S13: RdPtrOffsetTxDq: 07
N6.C0.D0.R1.S14: PiTxDqs: 49
N0.C0.D0.R1.S12: wrcmd2dqsstartlatency: 04
N2.C1.D0.R1.S05: Total Delay in PI ticks: TxDQ = 910
N4.C0.D0.R1.S14: RdPtrOffsetTxDq: 07
N6.C0.D0.R1.S15: wrcmd2dqsstartlatency: 04
N0.C0.D0.R1.S12: RdPtrOffsetTxDq: 05
N2.C1.D0.R1.S06: Total Delay in PI ticks: TxDQ = 924
N4.C0.D0.R1.S15: RdPtrOffsetTxDq: 07
N6.C0.D0.R1.S15: RdPtrOffsetTxDq: 05
N0.C0.D0.R1.S12: RdPtrOffsetTxDqs: 07
N2.C1.D0.R1.S07: Total Delay in PI ticks: TxDQ = 940
N4.C0.D0.R1.S16: RdPtrOffsetTxDq: 07
N6.C0.D0.R1.S15: RdPtrOffsetTxDqs: 06
N0.C0.D0.R1.S12: PiTxDqs: 06
N2.C1.D0.R1.S08: Total Delay in PI ticks: TxDQ = 910
N4.C0.D0.R1.S17: RdPtrOffsetTxDq: 07
N6.C0.D0.R1.S15: PiTxDqs: 52
N0.C0.D0.R1.S13: wrcmd2dqsstartlatency: 04
N2.C1.D0.R1.S09: Total Delay in PI ticks: TxDQ = 970
N4.C0.D0.R1.S00: Total Delay in PI ticks: TxDQ = 978
N6.C0.D0.R1.S16: wrcmd2dqsstartlatency: 04
N0.C0.D0.R1.S13: RdPtrOffsetTxDq: 05
N2.C1.D0.R1.S10: Total Delay in PI ticks: TxDQ = 954
N4.C0.D0.R1.S01: Total Delay in PI ticks: TxDQ = 960
N6.C0.D0.R1.S16: RdPtrOffsetTxDq: 05
N0.C0.D0.R1.S13: RdPtrOffsetTxDqs: 06
N2.C1.D0.R1.S11: Total Delay in PI ticks: TxDQ = 949
N4.C0.D0.R1.S02: Total Delay in PI ticks: TxDQ = 947
N6.C0.D0.R1.S16: RdPtrOffsetTxDqs: 07
N0.C0.D0.R1.S13: PiTxDqs: 35
N2.C1.D0.R1.S12: Total Delay in PI ticks: TxDQ = 932
N4.C0.D0.R1.S03: Total Delay in PI ticks: TxDQ = 931
N6.C0.D0.R1.S16: PiTxDqs: 06
N0.C0.D0.R1.S14: wrcmd2dqsstartlatency: 04
N2.C1.D0.R1.S13: Total Delay in PI ticks: TxDQ = 899
N4.C0.D0.R1.S04: Total Delay in PI ticks: TxDQ = 897
N6.C0.D0.R1.S17: wrcmd2dqsstartlatency: 04
N0.C0.D0.R1.S14: RdPtrOffsetTxDq: 05
N2.C1.D0.R1.S14: Total Delay in PI ticks: TxDQ = 912
N4.C0.D0.R1.S05: Total Delay in PI ticks: TxDQ = 914
N6.C0.D0.R1.S17: RdPtrOffsetTxDq: 05
N0.C0.D0.R1.S14: RdPtrOffsetTxDqs: 06
N2.C1.D0.R1.S15: Total Delay in PI ticks: TxDQ = 925
N4.C0.D0.R1.S06: Total Delay in PI ticks: TxDQ = 915
N6.C0.D0.R1.S17: RdPtrOffsetTxDqs: 06
N0.C0.D0.R1.S14: PiTxDqs: 53
N2.C1.D0.R1.S16: Total Delay in PI ticks: TxDQ = 942
N4.C0.D0.R1.S07: Total Delay in PI ticks: TxDQ = 933
N6.C0.D0.R1.S17: PiTxDqs: 42
N0.C0.D0.R1.S15: wrcmd2dqsstartlatency: 04
N2.C1.D0.R1.S17: Total Delay in PI ticks: TxDQ = 912
N4.C0.D0.R1.S08: Total Delay in PI ticks: TxDQ = 910
N6.C0.D0.R1.S00: RdPtrOffsetTxDq: 07
N0.C0.D0.R1.S15: RdPtrOffsetTxDq: 05
N2.C1.D1.R0.S00: wrcmd2dqsstartlatency: 04
N4.C0.D0.R1.S09: Total Delay in PI ticks: TxDQ = 976
N6.C0.D0.R1.S01: RdPtrOffsetTxDq: 06
N0.C0.D0.R1.S15: RdPtrOffsetTxDqs: 06
N2.C1.D1.R0.S00: RdPtrOffsetTxDq: 06
N4.C0.D0.R1.S10: Total Delay in PI ticks: TxDQ = 960
N6.C0.D0.R1.S02: RdPtrOffsetTxDq: 06
N0.C0.D0.R1.S15: PiTxDqs: 56
N2.C1.D1.R0.S00: RdPtrOffsetTxDqs: 07
N4.C0.D0.R1.S11: Total Delay in PI ticks: TxDQ = 949
N6.C0.D0.R1.S03: RdPtrOffsetTxDq: 06
N0.C0.D0.R1.S16: wrcmd2dqsstartlatency: 04
N2.C1.D1.R0.S00: PiTxDqs: 54
N4.C0.D0.R1.S12: Total Delay in PI ticks: TxDQ = 934
N6.C0.D0.R1.S04: RdPtrOffsetTxDq: 05
N0.C0.D0.R1.S16: RdPtrOffsetTxDq: 05
N2.C1.D1.R0.S01: wrcmd2dqsstartlatency: 04
N4.C0.D0.R1.S13: Total Delay in PI ticks: TxDQ = 900
N6.C0.D0.R1.S05: RdPtrOffsetTxDq: 06
N0.C0.D0.R1.S16: RdPtrOffsetTxDqs: 07
N2.C1.D1.R0.S01: RdPtrOffsetTxDq: 06
N4.C0.D0.R1.S14: Total Delay in PI ticks: TxDQ = 914
N6.C0.D0.R1.S06: RdPtrOffsetTxDq: 06
N0.C0.D0.R1.S16: PiTxDqs: 08
N2.C1.D1.R0.S01: RdPtrOffsetTxDqs: 07
N4.C0.D0.R1.S15: Total Delay in PI ticks: TxDQ = 918
N6.C0.D0.R1.S07: RdPtrOffsetTxDq: 06
N0.C0.D0.R1.S17: wrcmd2dqsstartlatency: 04
N2.C1.D1.R0.S01: PiTxDqs: 39
N4.C0.D0.R1.S16: Total Delay in PI ticks: TxDQ = 935
N6.C0.D0.R1.S08: RdPtrOffsetTxDq: 06
N0.C0.D0.R1.S17: RdPtrOffsetTxDq: 05
N2.C1.D1.R0.S02: wrcmd2dqsstartlatency: 04
N4.C0.D0.R1.S17: Total Delay in PI ticks: TxDQ = 906
N6.C0.D0.R1.S09: RdPtrOffsetTxDq: 07
N0.C0.D0.R1.S17: RdPtrOffsetTxDqs: 06
N2.C1.D1.R0.S02: RdPtrOffsetTxDq: 05
N4.C0.D1.R0.S00: wrcmd2dqsstartlatency: 04
N6.C0.D0.R1.S10: RdPtrOffsetTxDq: 06
N0.C0.D0.R1.S17: PiTxDqs: 42
N2.C1.D1.R0.S02: RdPtrOffsetTxDqs: 07
N4.C0.D1.R0.S00: RdPtrOffsetTxDq: 06
N6.C0.D0.R1.S11: RdPtrOffsetTxDq: 06
N0.C0.D0.R1.S00: RdPtrOffsetTxDq: 07
N2.C1.D1.R0.S02: PiTxDqs: 32
N4.C0.D1.R0.S00: RdPtrOffsetTxDqs: 07
N6.C0.D0.R1.S12: RdPtrOffsetTxDq: 06
N0.C0.D0.R1.S01: RdPtrOffsetTxDq: 06
N2.C1.D1.R0.S03: wrcmd2dqsstartlatency: 04
N4.C0.D1.R0.S00: PiTxDqs: 59
N6.C0.D0.R1.S13: RdPtrOffsetTxDq: 05
N0.C0.D0.R1.S02: RdPtrOffsetTxDq: 06
N2.C1.D1.R0.S03: RdPtrOffsetTxDq: 05
N4.C0.D1.R0.S01: wrcmd2dqsstartlatency: 04
N6.C0.D0.R1.S14: RdPtrOffsetTxDq: 06
N0.C0.D0.R1.S03: RdPtrOffsetTxDq: 06
N2.C1.D1.R0.S03: RdPtrOffsetTxDqs: 07
N4.C0.D1.R0.S01: RdPtrOffsetTxDq: 06
N6.C0.D0.R1.S15: RdPtrOffsetTxDq: 06
N0.C0.D0.R1.S04: RdPtrOffsetTxDq: 06
N2.C1.D1.R0.S03: PiTxDqs: 14
N4.C0.D1.R0.S01: RdPtrOffsetTxDqs: 07
N6.C0.D0.R1.S16: RdPtrOffsetTxDq: 06
N0.C0.D0.R1.S05: RdPtrOffsetTxDq: 06
N2.C1.D1.R0.S04: wrcmd2dqsstartlatency: 04
N4.C0.D1.R0.S01: PiTxDqs: 46
N6.C0.D0.R1.S17: RdPtrOffsetTxDq: 06
N0.C0.D0.R1.S06: RdPtrOffsetTxDq: 06
N2.C1.D1.R0.S04: RdPtrOffsetTxDq: 05
N4.C0.D1.R0.S02: wrcmd2dqsstartlatency: 04
N6.C0.D0.R1.S00: RdPtrOffsetTxDq: 08
N0.C0.D0.R1.S07: RdPtrOffsetTxDq: 06
N2.C1.D1.R0.S04: RdPtrOffsetTxDqs: 06
N4.C0.D1.R0.S02: RdPtrOffsetTxDq: 05
N6.C0.D0.R1.S01: RdPtrOffsetTxDq: 07
N0.C0.D0.R1.S08: RdPtrOffsetTxDq: 06
N2.C1.D1.R0.S04: PiTxDqs: 47
N4.C0.D1.R0.S02: RdPtrOffsetTxDqs: 07
N6.C0.D0.R1.S02: RdPtrOffsetTxDq: 07
N0.C0.D0.R1.S09: RdPtrOffsetTxDq: 07
N2.C1.D1.R0.S05: wrcmd2dqsstartlatency: 04
N4.C0.D1.R0.S02: PiTxDqs: 32
N6.C0.D0.R1.S03: RdPtrOffsetTxDq: 07
N0.C0.D0.R1.S10: RdPtrOffsetTxDq: 06
N2.C1.D1.R0.S05: RdPtrOffsetTxDq: 05
N4.C0.D1.R0.S03: wrcmd2dqsstartlatency: 04
N6.C0.D0.R1.S04: RdPtrOffsetTxDq: 06
N0.C0.D0.R1.S11: RdPtrOffsetTxDq: 06
N2.C1.D1.R0.S05: RdPtrOffsetTxDqs: 06
N4.C0.D1.R0.S03: RdPtrOffsetTxDq: 05
N6.C0.D0.R1.S05: RdPtrOffsetTxDq: 07
N0.C0.D0.R1.S12: RdPtrOffsetTxDq: 06
N2.C1.D1.R0.S05: PiTxDqs: 62
N4.C0.D1.R0.S03: RdPtrOffsetTxDqs: 07
N6.C0.D0.R1.S06: RdPtrOffsetTxDq: 07
N0.C0.D0.R1.S13: RdPtrOffsetTxDq: 06
N2.C1.D1.R0.S06: wrcmd2dqsstartlatency: 04
N4.C0.D1.R0.S03: PiTxDqs: 16
N6.C0.D0.R1.S07: RdPtrOffsetTxDq: 07
N0.C0.D0.R1.S14: RdPtrOffsetTxDq: 06
N2.C1.D1.R0.S06: RdPtrOffsetTxDq: 05
N4.C0.D1.R0.S04: wrcmd2dqsstartlatency: 04
N6.C0.D0.R1.S08: RdPtrOffsetTxDq: 07
N0.C0.D0.R1.S15: RdPtrOffsetTxDq: 06
N2.C1.D1.R0.S06: RdPtrOffsetTxDqs: 07
N4.C0.D1.R0.S04: RdPtrOffsetTxDq: 05
N6.C0.D0.R1.S09: RdPtrOffsetTxDq: 08
N0.C0.D0.R1.S16: RdPtrOffsetTxDq: 06
N2.C1.D1.R0.S06: PiTxDqs: 09
N4.C0.D1.R0.S04: RdPtrOffsetTxDqs: 06
N6.C0.D0.R1.S10: RdPtrOffsetTxDq: 07
N0.C0.D0.R1.S17: RdPtrOffsetTxDq: 06
N2.C1.D1.R0.S07: wrcmd2dqsstartlatency: 04
N4.C0.D1.R0.S04: PiTxDqs: 47
N6.C0.D0.R1.S11: RdPtrOffsetTxDq: 07
N0.C0.D0.R1.S00: RdPtrOffsetTxDq: 08
N2.C1.D1.R0.S07: RdPtrOffsetTxDq: 05
N4.C0.D1.R0.S05: wrcmd2dqsstartlatency: 04
N6.C0.D0.R1.S12: RdPtrOffsetTxDq: 07
N0.C0.D0.R1.S01: RdPtrOffsetTxDq: 07
N2.C1.D1.R0.S07: RdPtrOffsetTxDqs: 07
N4.C0.D1.R0.S05: RdPtrOffsetTxDq: 05
N6.C0.D0.R1.S13: RdPtrOffsetTxDq: 06
N0.C0.D0.R1.S02: RdPtrOffsetTxDq: 07
N2.C1.D1.R0.S07: PiTxDqs: 27
N4.C0.D1.R0.S05: RdPtrOffsetTxDqs: 07
N6.C0.D0.R1.S14: RdPtrOffsetTxDq: 07
N0.C0.D0.R1.S03: RdPtrOffsetTxDq: 07
N2.C1.D1.R0.S08: wrcmd2dqsstartlatency: 04
N4.C0.D1.R0.S05: PiTxDqs: 01
N6.C0.D0.R1.S15: RdPtrOffsetTxDq: 07
N0.C0.D0.R1.S04: RdPtrOffsetTxDq: 07
N2.C1.D1.R0.S08: RdPtrOffsetTxDq: 05
N4.C0.D1.R0.S06: wrcmd2dqsstartlatency: 04
N6.C0.D0.R1.S16: RdPtrOffsetTxDq: 07
N0.C0.D0.R1.S05: RdPtrOffsetTxDq: 07
N2.C1.D1.R0.S08: RdPtrOffsetTxDqs: 06
N4.C0.D1.R0.S06: RdPtrOffsetTxDq: 05
N6.C0.D0.R1.S17: RdPtrOffsetTxDq: 07
N0.C0.D0.R1.S06: RdPtrOffsetTxDq: 07
N2.C1.D1.R0.S08: PiTxDqs: 58
N4.C0.D1.R0.S06: RdPtrOffsetTxDqs: 07
N6.C0.D0.R1.S00: Total Delay in PI ticks: TxDQ = 979
N0.C0.D0.R1.S07: RdPtrOffsetTxDq: 07
N2.C1.D1.R0.S09: wrcmd2dqsstartlatency: 04
N4.C0.D1.R0.S06: PiTxDqs: 01
N6.C0.D0.R1.S01: Total Delay in PI ticks: TxDQ = 955
N0.C0.D0.R1.S08: RdPtrOffsetTxDq: 07
N2.C1.D1.R0.S09: RdPtrOffsetTxDq: 06
N4.C0.D1.R0.S07: wrcmd2dqsstartlatency: 04
N6.C0.D0.R1.S02: Total Delay in PI ticks: TxDQ = 945
N0.C0.D0.R1.S09: RdPtrOffsetTxDq: 08
N2.C1.D1.R0.S09: RdPtrOffsetTxDqs: 07
N4.C0.D1.R0.S07: RdPtrOffsetTxDq: 05
N6.C0.D0.R1.S03: Total Delay in PI ticks: TxDQ = 928
N0.C0.D0.R1.S10: RdPtrOffsetTxDq: 07
N2.C1.D1.R0.S09: PiTxDqs: 56
N4.C0.D1.R0.S07: RdPtrOffsetTxDqs: 07
N6.C0.D0.R1.S04: Total Delay in PI ticks: TxDQ = 895
N0.C0.D0.R1.S11: RdPtrOffsetTxDq: 07
N2.C1.D1.R0.S10: wrcmd2dqsstartlatency: 04
N4.C0.D1.R0.S07: PiTxDqs: 17
N6.C0.D0.R1.S05: Total Delay in PI ticks: TxDQ = 913
N0.C0.D0.R1.S12: RdPtrOffsetTxDq: 07
N2.C1.D1.R0.S10: RdPtrOffsetTxDq: 06
N4.C0.D1.R0.S08: wrcmd2dqsstartlatency: 04
N6.C0.D0.R1.S06: Total Delay in PI ticks: TxDQ = 919
N0.C0.D0.R1.S13: RdPtrOffsetTxDq: 07
N2.C1.D1.R0.S10: RdPtrOffsetTxDqs: 07
N4.C0.D1.R0.S08: RdPtrOffsetTxDq: 05
N6.C0.D0.R1.S07: Total Delay in PI ticks: TxDQ = 933
N0.C0.D0.R1.S14: RdPtrOffsetTxDq: 07
N2.C1.D1.R0.S10: PiTxDqs: 38
N4.C0.D1.R0.S08: RdPtrOffsetTxDqs: 06
N6.C0.D0.R1.S08: Total Delay in PI ticks: TxDQ = 907
N0.C0.D0.R1.S15: RdPtrOffsetTxDq: 07
N2.C1.D1.R0.S11: wrcmd2dqsstartlatency: 04
N4.C0.D1.R0.S08: PiTxDqs: 54
N6.C0.D0.R1.S09: Total Delay in PI ticks: TxDQ = 973
N0.C0.D0.R1.S16: RdPtrOffsetTxDq: 07
N2.C1.D1.R0.S11: RdPtrOffsetTxDq: 05
N4.C0.D1.R0.S09: wrcmd2dqsstartlatency: 04
N6.C0.D0.R1.S10: Total Delay in PI ticks: TxDQ = 956
N0.C0.D0.R1.S17: RdPtrOffsetTxDq: 07
N2.C1.D1.R0.S11: RdPtrOffsetTxDqs: 07
N4.C0.D1.R0.S09: RdPtrOffsetTxDq: 06
N6.C0.D0.R1.S11: Total Delay in PI ticks: TxDQ = 945
N0.C0.D0.R1.S00: Total Delay in PI ticks: TxDQ = 978
N2.C1.D1.R0.S11: PiTxDqs: 32
N4.C0.D1.R0.S09: RdPtrOffsetTxDqs: 07
N6.C0.D0.R1.S12: Total Delay in PI ticks: TxDQ = 932
N0.C0.D0.R1.S01: Total Delay in PI ticks: TxDQ = 960
N2.C1.D1.R0.S12: wrcmd2dqsstartlatency: 04
N4.C0.D1.R0.S09: PiTxDqs: 57
N6.C0.D0.R1.S13: Total Delay in PI ticks: TxDQ = 896
N0.C0.D0.R1.S02: Total Delay in PI ticks: TxDQ = 946
N2.C1.D1.R0.S12: RdPtrOffsetTxDq: 05
N4.C0.D1.R0.S10: wrcmd2dqsstartlatency: 04
N6.C0.D0.R1.S14: Total Delay in PI ticks: TxDQ = 913
N0.C0.D0.R1.S03: Total Delay in PI ticks: TxDQ = 930
N2.C1.D1.R0.S12: RdPtrOffsetTxDqs: 07
N4.C0.D1.R0.S10: RdPtrOffsetTxDq: 06
N6.C0.D0.R1.S15: Total Delay in PI ticks: TxDQ = 916
N0.C0.D0.R1.S04: Total Delay in PI ticks: TxDQ = 899
N2.C1.D1.R0.S12: PiTxDqs: 16
N4.C0.D1.R0.S10: RdPtrOffsetTxDqs: 07
N6.C0.D0.R1.S16: Total Delay in PI ticks: TxDQ = 932
N0.C0.D0.R1.S05: Total Delay in PI ticks: TxDQ = 913
N2.C1.D1.R0.S13: wrcmd2dqsstartlatency: 04
N4.C0.D1.R0.S10: PiTxDqs: 46
N6.C0.D0.R1.S17: Total Delay in PI ticks: TxDQ = 907
N0.C0.D0.R1.S06: Total Delay in PI ticks: TxDQ = 917
N2.C1.D1.R0.S13: RdPtrOffsetTxDq: 05
N4.C0.D1.R0.S11: wrcmd2dqsstartlatency: 04
N6.C0.D1.R0.S00: wrcmd2dqsstartlatency: 04
N0.C0.D0.R1.S07: Total Delay in PI ticks: TxDQ = 932
N2.C1.D1.R0.S13: RdPtrOffsetTxDqs: 06
N4.C0.D1.R0.S11: RdPtrOffsetTxDq: 05
N6.C0.D1.R0.S00: RdPtrOffsetTxDq: 06
N0.C0.D0.R1.S08: Total Delay in PI ticks: TxDQ = 907
N2.C1.D1.R0.S13: PiTxDqs: 46
N4.C0.D1.R0.S11: RdPtrOffsetTxDqs: 07
N6.C0.D1.R0.S00: RdPtrOffsetTxDqs: 07
N0.C0.D0.R1.S09: Total Delay in PI ticks: TxDQ = 974
N2.C1.D1.R0.S14: wrcmd2dqsstartlatency: 04
N4.C0.D1.R0.S11: PiTxDqs: 32
N6.C0.D1.R0.S00: PiTxDqs: 52
N0.C0.D0.R1.S10: Total Delay in PI ticks: TxDQ = 960
N2.C1.D1.R0.S14: RdPtrOffsetTxDq: 05
N4.C0.D1.R0.S12: wrcmd2dqsstartlatency: 04
N6.C0.D1.R0.S01: wrcmd2dqsstartlatency: 04
N0.C0.D0.R1.S11: Total Delay in PI ticks: TxDQ = 946
N2.C1.D1.R0.S14: RdPtrOffsetTxDqs: 06
N4.C0.D1.R0.S12: RdPtrOffsetTxDq: 05
N6.C0.D1.R0.S01: RdPtrOffsetTxDq: 05
N0.C0.D0.R1.S12: Total Delay in PI ticks: TxDQ = 932
N2.C1.D1.R0.S14: PiTxDqs: 61
N4.C0.D1.R0.S12: RdPtrOffsetTxDqs: 07
N6.C0.D1.R0.S01: RdPtrOffsetTxDqs: 07
N0.C0.D0.R1.S13: Total Delay in PI ticks: TxDQ = 899
N2.C1.D1.R0.S15: wrcmd2dqsstartlatency: 04
N4.C0.D1.R0.S12: PiTxDqs: 16
N6.C0.D1.R0.S01: PiTxDqs: 34
N0.C0.D0.R1.S14: Total Delay in PI ticks: TxDQ = 916
N2.C1.D1.R0.S15: RdPtrOffsetTxDq: 05
N4.C0.D1.R0.S13: wrcmd2dqsstartlatency: 04
N6.C0.D1.R0.S02: wrcmd2dqsstartlatency: 04
N0.C0.D0.R1.S15: Total Delay in PI ticks: TxDQ = 919
N2.C1.D1.R0.S15: RdPtrOffsetTxDqs: 07
N4.C0.D1.R0.S13: RdPtrOffsetTxDq: 05
N6.C0.D1.R0.S02: RdPtrOffsetTxDq: 05
N0.C0.D0.R1.S16: Total Delay in PI ticks: TxDQ = 935
N2.C1.D1.R0.S15: PiTxDqs: 09
N4.C0.D1.R0.S13: RdPtrOffsetTxDqs: 06
N6.C0.D1.R0.S02: RdPtrOffsetTxDqs: 07
N0.C0.D0.R1.S17: Total Delay in PI ticks: TxDQ = 904
N2.C1.D1.R0.S16: wrcmd2dqsstartlatency: 04
N4.C0.D1.R0.S13: PiTxDqs: 47
N6.C0.D1.R0.S02: PiTxDqs: 23
N0.C0.D1.R0.S00: wrcmd2dqsstartlatency: 04
N2.C1.D1.R0.S16: RdPtrOffsetTxDq: 05
N4.C0.D1.R0.S14: wrcmd2dqsstartlatency: 04
N6.C0.D1.R0.S03: wrcmd2dqsstartlatency: 04
N0.C0.D1.R0.S00: RdPtrOffsetTxDq: 06
N2.C1.D1.R0.S16: RdPtrOffsetTxDqs: 07
N4.C0.D1.R0.S14: RdPtrOffsetTxDq: 05
N6.C0.D1.R0.S03: RdPtrOffsetTxDq: 05
N0.C0.D1.R0.S00: RdPtrOffsetTxDqs: 07
N2.C1.D1.R0.S16: PiTxDqs: 26
N4.C0.D1.R0.S14: RdPtrOffsetTxDqs: 07
N6.C0.D1.R0.S03: RdPtrOffsetTxDqs: 07
N0.C0.D1.R0.S00: PiTxDqs: 62
N2.C1.D1.R0.S17: wrcmd2dqsstartlatency: 04
N4.C0.D1.R0.S14: PiTxDqs: 00
N6.C0.D1.R0.S03: PiTxDqs: 10
N0.C0.D1.R0.S01: wrcmd2dqsstartlatency: 04
N2.C1.D1.R0.S17: RdPtrOffsetTxDq: 05
N4.C0.D1.R0.S15: wrcmd2dqsstartlatency: 04
N6.C0.D1.R0.S04: wrcmd2dqsstartlatency: 04
N0.C0.D1.R0.S01: RdPtrOffsetTxDq: 06
N2.C1.D1.R0.S17: RdPtrOffsetTxDqs: 06
N4.C0.D1.R0.S15: RdPtrOffsetTxDq: 05
N6.C0.D1.R0.S04: RdPtrOffsetTxDq: 05
N0.C0.D1.R0.S01: RdPtrOffsetTxDqs: 07
N2.C1.D1.R0.S17: PiTxDqs: 58
N4.C0.D1.R0.S15: RdPtrOffsetTxDqs: 07
N6.C0.D1.R0.S04: RdPtrOffsetTxDqs: 06
N0.C0.D1.R0.S01: PiTxDqs: 44
N2.C1.D1.R0.S00: RdPtrOffsetTxDq: 07
N4.C0.D1.R0.S15: PiTxDqs: 00
N6.C0.D1.R0.S04: PiTxDqs: 37
N0.C0.D1.R0.S02: wrcmd2dqsstartlatency: 04
N2.C1.D1.R0.S01: RdPtrOffsetTxDq: 07
N4.C0.D1.R0.S16: wrcmd2dqsstartlatency: 04
N6.C0.D1.R0.S05: wrcmd2dqsstartlatency: 04
N0.C0.D1.R0.S02: RdPtrOffsetTxDq: 05
N2.C1.D1.R0.S02: RdPtrOffsetTxDq: 06
N4.C0.D1.R0.S16: RdPtrOffsetTxDq: 05
N6.C0.D1.R0.S05: RdPtrOffsetTxDq: 05
N0.C0.D1.R0.S02: RdPtrOffsetTxDqs: 07
N2.C1.D1.R0.S03: RdPtrOffsetTxDq: 06
N4.C0.D1.R0.S16: RdPtrOffsetTxDqs: 07
N6.C0.D1.R0.S05: RdPtrOffsetTxDqs: 06
N0.C0.D1.R0.S02: PiTxDqs: 32
N2.C1.D1.R0.S04: RdPtrOffsetTxDq: 06
N4.C0.D1.R0.S16: PiTxDqs: 17
N6.C0.D1.R0.S05: PiTxDqs: 56
N0.C0.D1.R0.S03: wrcmd2dqsstartlatency: 04
N2.C1.D1.R0.S05: RdPtrOffsetTxDq: 06
N4.C0.D1.R0.S17: wrcmd2dqsstartlatency: 04
N6.C0.D1.R0.S06: wrcmd2dqsstartlatency: 04
N0.C0.D1.R0.S03: RdPtrOffsetTxDq: 05
N2.C1.D1.R0.S06: RdPtrOffsetTxDq: 06
N4.C0.D1.R0.S17: RdPtrOffsetTxDq: 05
N6.C0.D1.R0.S06: RdPtrOffsetTxDq: 05
N0.C0.D1.R0.S03: RdPtrOffsetTxDqs: 07
N2.C1.D1.R0.S07: RdPtrOffsetTxDq: 06
N4.C0.D1.R0.S17: RdPtrOffsetTxDqs: 06
N6.C0.D1.R0.S06: RdPtrOffsetTxDqs: 06
N0.C0.D1.R0.S03: PiTxDqs: 15
N2.C1.D1.R0.S08: RdPtrOffsetTxDq: 06
N4.C0.D1.R0.S17: PiTxDqs: 54
N6.C0.D1.R0.S06: PiTxDqs: 60
N0.C0.D1.R0.S04: wrcmd2dqsstartlatency: 04
N2.C1.D1.R0.S09: RdPtrOffsetTxDq: 07
N4.C0.D1.R0.S00: RdPtrOffsetTxDq: 07
N6.C0.D1.R0.S07: wrcmd2dqsstartlatency: 04
N0.C0.D1.R0.S04: RdPtrOffsetTxDq: 05
N2.C1.D1.R0.S10: RdPtrOffsetTxDq: 07
N4.C0.D1.R0.S01: RdPtrOffsetTxDq: 07
N6.C0.D1.R0.S07: RdPtrOffsetTxDq: 05
N0.C0.D1.R0.S04: RdPtrOffsetTxDqs: 06
N2.C1.D1.R0.S11: RdPtrOffsetTxDq: 06
N4.C0.D1.R0.S02: RdPtrOffsetTxDq: 06
N6.C0.D1.R0.S07: RdPtrOffsetTxDqs: 07
N0.C0.D1.R0.S04: PiTxDqs: 46
N2.C1.D1.R0.S12: RdPtrOffsetTxDq: 06
N4.C0.D1.R0.S03: RdPtrOffsetTxDq: 06
N6.C0.D1.R0.S07: PiTxDqs: 13
N0.C0.D1.R0.S05: wrcmd2dqsstartlatency: 04
N2.C1.D1.R0.S13: RdPtrOffsetTxDq: 06
N4.C0.D1.R0.S04: RdPtrOffsetTxDq: 06
N6.C0.D1.R0.S08: wrcmd2dqsstartlatency: 04
N0.C0.D1.R0.S05: RdPtrOffsetTxDq: 05
N2.C1.D1.R0.S14: RdPtrOffsetTxDq: 06
N4.C0.D1.R0.S05: RdPtrOffsetTxDq: 06
N6.C0.D1.R0.S08: RdPtrOffsetTxDq: 05
N0.C0.D1.R0.S05: RdPtrOffsetTxDqs: 07
N2.C1.D1.R0.S15: RdPtrOffsetTxDq: 06
N4.C0.D1.R0.S06: RdPtrOffsetTxDq: 06
N6.C0.D1.R0.S08: RdPtrOffsetTxDqs: 06
N0.C0.D1.R0.S05: PiTxDqs: 00
N2.C1.D1.R0.S16: RdPtrOffsetTxDq: 06
N4.C0.D1.R0.S07: RdPtrOffsetTxDq: 06
N6.C0.D1.R0.S08: PiTxDqs: 47
N0.C0.D1.R0.S06: wrcmd2dqsstartlatency: 04
N2.C1.D1.R0.S17: RdPtrOffsetTxDq: 06
N4.C0.D1.R0.S08: RdPtrOffsetTxDq: 06
N6.C0.D1.R0.S09: wrcmd2dqsstartlatency: 04
N0.C0.D1.R0.S06: RdPtrOffsetTxDq: 05
N2.C1.D1.R0.S00: RdPtrOffsetTxDq: 08
N4.C0.D1.R0.S09: RdPtrOffsetTxDq: 07
N6.C0.D1.R0.S09: RdPtrOffsetTxDq: 06
N0.C0.D1.R0.S06: RdPtrOffsetTxDqs: 07
N2.C1.D1.R0.S01: RdPtrOffsetTxDq: 08
N4.C0.D1.R0.S10: RdPtrOffsetTxDq: 07
N6.C0.D1.R0.S09: RdPtrOffsetTxDqs: 07
N0.C0.D1.R0.S06: PiTxDqs: 00
N2.C1.D1.R0.S02: RdPtrOffsetTxDq: 07
N4.C0.D1.R0.S11: RdPtrOffsetTxDq: 06
N6.C0.D1.R0.S09: PiTxDqs: 55
N0.C0.D1.R0.S07: wrcmd2dqsstartlatency: 04
N2.C1.D1.R0.S03: RdPtrOffsetTxDq: 07
N4.C0.D1.R0.S12: RdPtrOffsetTxDq: 06
N6.C0.D1.R0.S10: wrcmd2dqsstartlatency: 04
N0.C0.D1.R0.S07: RdPtrOffsetTxDq: 05
N2.C1.D1.R0.S04: RdPtrOffsetTxDq: 07
N4.C0.D1.R0.S13: RdPtrOffsetTxDq: 06
N6.C0.D1.R0.S10: RdPtrOffsetTxDq: 06
N0.C0.D1.R0.S07: RdPtrOffsetTxDqs: 07
N2.C1.D1.R0.S05: RdPtrOffsetTxDq: 07
N4.C0.D1.R0.S14: RdPtrOffsetTxDq: 06
N6.C0.D1.R0.S10: RdPtrOffsetTxDqs: 07
N0.C0.D1.R0.S07: PiTxDqs: 20
N2.C1.D1.R0.S06: RdPtrOffsetTxDq: 07
N4.C0.D1.R0.S15: RdPtrOffsetTxDq: 06
N6.C0.D1.R0.S10: PiTxDqs: 37
N0.C0.D1.R0.S08: wrcmd2dqsstartlatency: 04
N2.C1.D1.R0.S07: RdPtrOffsetTxDq: 07
N4.C0.D1.R0.S16: RdPtrOffsetTxDq: 06
N6.C0.D1.R0.S11: wrcmd2dqsstartlatency: 04
N0.C0.D1.R0.S08: RdPtrOffsetTxDq: 05
N2.C1.D1.R0.S08: RdPtrOffsetTxDq: 07
N4.C0.D1.R0.S17: RdPtrOffsetTxDq: 06
N6.C0.D1.R0.S11: RdPtrOffsetTxDq: 05
N0.C0.D1.R0.S08: RdPtrOffsetTxDqs: 06
N2.C1.D1.R0.S09: RdPtrOffsetTxDq: 08
N4.C0.D1.R0.S00: RdPtrOffsetTxDq: 08
N6.C0.D1.R0.S11: RdPtrOffsetTxDqs: 07
N0.C0.D1.R0.S08: PiTxDqs: 54
N2.C1.D1.R0.S10: RdPtrOffsetTxDq: 08
N4.C0.D1.R0.S01: RdPtrOffsetTxDq: 08
N6.C0.D1.R0.S11: PiTxDqs: 22
N0.C0.D1.R0.S09: wrcmd2dqsstartlatency: 04
N2.C1.D1.R0.S11: RdPtrOffsetTxDq: 07
N4.C0.D1.R0.S02: RdPtrOffsetTxDq: 07
N6.C0.D1.R0.S12: wrcmd2dqsstartlatency: 04
N0.C0.D1.R0.S09: RdPtrOffsetTxDq: 06
N2.C1.D1.R0.S12: RdPtrOffsetTxDq: 07
N4.C0.D1.R0.S03: RdPtrOffsetTxDq: 07
N6.C0.D1.R0.S12: RdPtrOffsetTxDq: 05
N0.C0.D1.R0.S09: RdPtrOffsetTxDqs: 07
N2.C1.D1.R0.S13: RdPtrOffsetTxDq: 07
N4.C0.D1.R0.S04: RdPtrOffsetTxDq: 07
N6.C0.D1.R0.S12: RdPtrOffsetTxDqs: 07
N0.C0.D1.R0.S09: PiTxDqs: 59
N2.C1.D1.R0.S14: RdPtrOffsetTxDq: 07
N4.C0.D1.R0.S05: RdPtrOffsetTxDq: 07
N6.C0.D1.R0.S12: PiTxDqs: 10
N0.C0.D1.R0.S10: wrcmd2dqsstartlatency: 04
N2.C1.D1.R0.S15: RdPtrOffsetTxDq: 07
N4.C0.D1.R0.S06: RdPtrOffsetTxDq: 07
N6.C0.D1.R0.S13: wrcmd2dqsstartlatency: 04
N0.C0.D1.R0.S10: RdPtrOffsetTxDq: 06
N2.C1.D1.R0.S16: RdPtrOffsetTxDq: 07
N4.C0.D1.R0.S07: RdPtrOffsetTxDq: 07
N6.C0.D1.R0.S13: RdPtrOffsetTxDq: 05
N0.C0.D1.R0.S10: RdPtrOffsetTxDqs: 07
N2.C1.D1.R0.S17: RdPtrOffsetTxDq: 07
N4.C0.D1.R0.S08: RdPtrOffsetTxDq: 07
N6.C0.D1.R0.S13: RdPtrOffsetTxDqs: 06
N0.C0.D1.R0.S10: PiTxDqs: 44
N2.C1.D1.R0.S00: Total Delay in PI ticks: TxDQ = 983
N4.C0.D1.R0.S09: RdPtrOffsetTxDq: 08
N6.C0.D1.R0.S13: PiTxDqs: 38
N0.C0.D1.R0.S11: wrcmd2dqsstartlatency: 04
N2.C1.D1.R0.S01: Total Delay in PI ticks: TxDQ = 965
N4.C0.D1.R0.S10: RdPtrOffsetTxDq: 08
N6.C0.D1.R0.S14: wrcmd2dqsstartlatency: 04
N0.C0.D1.R0.S11: RdPtrOffsetTxDq: 05
N2.C1.D1.R0.S02: Total Delay in PI ticks: TxDQ = 958
N4.C0.D1.R0.S11: RdPtrOffsetTxDq: 07
N6.C0.D1.R0.S14: RdPtrOffsetTxDq: 05
N0.C0.D1.R0.S11: RdPtrOffsetTxDqs: 07
N2.C1.D1.R0.S03: Total Delay in PI ticks: TxDQ = 942
N4.C0.D1.R0.S12: RdPtrOffsetTxDq: 07
N6.C0.D1.R0.S14: RdPtrOffsetTxDqs: 06
N0.C0.D1.R0.S11: PiTxDqs: 31
N2.C1.D1.R0.S04: Total Delay in PI ticks: TxDQ = 910
N4.C0.D1.R0.S13: RdPtrOffsetTxDq: 07
N6.C0.D1.R0.S14: PiTxDqs: 57
N0.C0.D1.R0.S12: wrcmd2dqsstartlatency: 04
N2.C1.D1.R0.S05: Total Delay in PI ticks: TxDQ = 924
N4.C0.D1.R0.S14: RdPtrOffsetTxDq: 07
N6.C0.D1.R0.S15: wrcmd2dqsstartlatency: 04
N0.C0.D1.R0.S12: RdPtrOffsetTxDq: 05
N2.C1.D1.R0.S06: Total Delay in PI ticks: TxDQ = 937
N4.C0.D1.R0.S15: RdPtrOffsetTxDq: 07
N6.C0.D1.R0.S15: RdPtrOffsetTxDq: 05
N0.C0.D1.R0.S12: RdPtrOffsetTxDqs: 07
N2.C1.D1.R0.S07: Total Delay in PI ticks: TxDQ = 954
N4.C0.D1.R0.S16: RdPtrOffsetTxDq: 07
N6.C0.D1.R0.S15: RdPtrOffsetTxDqs: 06
N0.C0.D1.R0.S12: PiTxDqs: 18
N2.C1.D1.R0.S08: Total Delay in PI ticks: TxDQ = 921
N4.C0.D1.R0.S17: RdPtrOffsetTxDq: 07
N6.C0.D1.R0.S15: PiTxDqs: 61
N0.C0.D1.R0.S13: wrcmd2dqsstartlatency: 04
N2.C1.D1.R0.S09: Total Delay in PI ticks: TxDQ = 983
N4.C0.D1.R0.S00: Total Delay in PI ticks: TxDQ = 985
N6.C0.D1.R0.S16: wrcmd2dqsstartlatency: 04
N0.C0.D1.R0.S13: RdPtrOffsetTxDq: 05
N2.C1.D1.R0.S10: Total Delay in PI ticks: TxDQ = 964
N4.C0.D1.R0.S01: Total Delay in PI ticks: TxDQ = 969
N6.C0.D1.R0.S16: RdPtrOffsetTxDq: 05
N0.C0.D1.R0.S13: RdPtrOffsetTxDqs: 06
N2.C1.D1.R0.S11: Total Delay in PI ticks: TxDQ = 960
N4.C0.D1.R0.S02: Total Delay in PI ticks: TxDQ = 957
N6.C0.D1.R0.S16: RdPtrOffsetTxDqs: 07
N0.C0.D1.R0.S13: PiTxDqs: 47
N2.C1.D1.R0.S12: Total Delay in PI ticks: TxDQ = 943
N4.C0.D1.R0.S03: Total Delay in PI ticks: TxDQ = 941
N6.C0.D1.R0.S16: PiTxDqs: 14
N0.C0.D1.R0.S14: wrcmd2dqsstartlatency: 04
N2.C1.D1.R0.S13: Total Delay in PI ticks: TxDQ = 909
N4.C0.D1.R0.S04: Total Delay in PI ticks: TxDQ = 907
N6.C0.D1.R0.S17: wrcmd2dqsstartlatency: 04
N0.C0.D1.R0.S14: RdPtrOffsetTxDq: 05
N2.C1.D1.R0.S14: Total Delay in PI ticks: TxDQ = 924
N4.C0.D1.R0.S05: Total Delay in PI ticks: TxDQ = 926
N6.C0.D1.R0.S17: RdPtrOffsetTxDq: 05
N0.C0.D1.R0.S14: RdPtrOffsetTxDqs: 06
N2.C1.D1.R0.S15: Total Delay in PI ticks: TxDQ = 938
N4.C0.D1.R0.S06: Total Delay in PI ticks: TxDQ = 925
N6.C0.D1.R0.S17: RdPtrOffsetTxDqs: 06
N0.C0.D1.R0.S14: PiTxDqs: 63
N2.C1.D1.R0.S16: Total Delay in PI ticks: TxDQ = 954
N4.C0.D1.R0.S07: Total Delay in PI ticks: TxDQ = 943
N6.C0.D1.R0.S17: PiTxDqs: 48
N0.C0.D1.R0.S15: wrcmd2dqsstartlatency: 04
N2.C1.D1.R0.S17: Total Delay in PI ticks: TxDQ = 921
N4.C0.D1.R0.S08: Total Delay in PI ticks: TxDQ = 914
N6.C0.D1.R0.S00: RdPtrOffsetTxDq: 07
N0.C0.D1.R0.S15: RdPtrOffsetTxDq: 05
N2.C1.D1.R1.S00: wrcmd2dqsstartlatency: 04
N4.C0.D1.R0.S09: Total Delay in PI ticks: TxDQ = 984
N6.C0.D1.R0.S01: RdPtrOffsetTxDq: 06
N0.C0.D1.R0.S15: RdPtrOffsetTxDqs: 07
N2.C1.D1.R1.S00: RdPtrOffsetTxDq: 06
N4.C0.D1.R0.S10: Total Delay in PI ticks: TxDQ = 971
N6.C0.D1.R0.S02: RdPtrOffsetTxDq: 06
N0.C0.D1.R0.S15: PiTxDqs: 03
N2.C1.D1.R1.S00: RdPtrOffsetTxDqs: 07
N4.C0.D1.R0.S11: Total Delay in PI ticks: TxDQ = 955
N6.C0.D1.R0.S03: RdPtrOffsetTxDq: 06
N0.C0.D1.R0.S16: wrcmd2dqsstartlatency: 04
N2.C1.D1.R1.S00: PiTxDqs: 50
N4.C0.D1.R0.S12: Total Delay in PI ticks: TxDQ = 942
N6.C0.D1.R0.S04: RdPtrOffsetTxDq: 06
N0.C0.D1.R0.S16: RdPtrOffsetTxDq: 05
N2.C1.D1.R1.S01: wrcmd2dqsstartlatency: 04
N4.C0.D1.R0.S13: Total Delay in PI ticks: TxDQ = 907
N6.C0.D1.R0.S05: RdPtrOffsetTxDq: 06
N0.C0.D1.R0.S16: RdPtrOffsetTxDqs: 07
N2.C1.D1.R1.S01: RdPtrOffsetTxDq: 05
N4.C0.D1.R0.S14: Total Delay in PI ticks: TxDQ = 927
N6.C0.D1.R0.S06: RdPtrOffsetTxDq: 06
N0.C0.D1.R0.S16: PiTxDqs: 22
N2.C1.D1.R1.S01: RdPtrOffsetTxDqs: 07
N4.C0.D1.R0.S15: Total Delay in PI ticks: TxDQ = 927
N6.C0.D1.R0.S07: RdPtrOffsetTxDq: 06
N0.C0.D1.R0.S17: wrcmd2dqsstartlatency: 04
N2.C1.D1.R1.S01: PiTxDqs: 34
N4.C0.D1.R0.S16: Total Delay in PI ticks: TxDQ = 943
N6.C0.D1.R0.S08: RdPtrOffsetTxDq: 06
N0.C0.D1.R0.S17: RdPtrOffsetTxDq: 05
N2.C1.D1.R1.S02: wrcmd2dqsstartlatency: 04
N4.C0.D1.R0.S17: Total Delay in PI ticks: TxDQ = 914
N6.C0.D1.R0.S09: RdPtrOffsetTxDq: 07
N0.C0.D1.R0.S17: RdPtrOffsetTxDqs: 06
N2.C1.D1.R1.S02: RdPtrOffsetTxDq: 05
N4.C0.D1.R1.S00: wrcmd2dqsstartlatency: 04
N6.C0.D1.R0.S10: RdPtrOffsetTxDq: 07
N0.C0.D1.R0.S17: PiTxDqs: 55
N2.C1.D1.R1.S02: RdPtrOffsetTxDqs: 07
N4.C0.D1.R1.S00: RdPtrOffsetTxDq: 06
N6.C0.D1.R0.S11: RdPtrOffsetTxDq: 06
N0.C0.D1.R0.S00: RdPtrOffsetTxDq: 07
N2.C1.D1.R1.S02: PiTxDqs: 27
N4.C0.D1.R1.S00: RdPtrOffsetTxDqs: 07
N6.C0.D1.R0.S12: RdPtrOffsetTxDq: 06
N0.C0.D1.R0.S01: RdPtrOffsetTxDq: 07
N2.C1.D1.R1.S03: wrcmd2dqsstartlatency: 04
N4.C0.D1.R1.S00: PiTxDqs: 57
N6.C0.D1.R0.S13: RdPtrOffsetTxDq: 06
N0.C0.D1.R0.S02: RdPtrOffsetTxDq: 06
N2.C1.D1.R1.S03: RdPtrOffsetTxDq: 05
N4.C0.D1.R1.S01: wrcmd2dqsstartlatency: 04
N6.C0.D1.R0.S14: RdPtrOffsetTxDq: 06
N0.C0.D1.R0.S03: RdPtrOffsetTxDq: 06
N2.C1.D1.R1.S03: RdPtrOffsetTxDqs: 07
N4.C0.D1.R1.S01: RdPtrOffsetTxDq: 06
N6.C0.D1.R0.S15: RdPtrOffsetTxDq: 06
N0.C0.D1.R0.S04: RdPtrOffsetTxDq: 06
N2.C1.D1.R1.S03: PiTxDqs: 10
N4.C0.D1.R1.S01: RdPtrOffsetTxDqs: 07
N6.C0.D1.R0.S16: RdPtrOffsetTxDq: 06
N0.C0.D1.R0.S05: RdPtrOffsetTxDq: 06
N2.C1.D1.R1.S04: wrcmd2dqsstartlatency: 04
N4.C0.D1.R1.S01: PiTxDqs: 42
N6.C0.D1.R0.S17: RdPtrOffsetTxDq: 06
N0.C0.D1.R0.S06: RdPtrOffsetTxDq: 06
N2.C1.D1.R1.S04: RdPtrOffsetTxDq: 05
N4.C0.D1.R1.S02: wrcmd2dqsstartlatency: 04
N6.C0.D1.R0.S00: RdPtrOffsetTxDq: 08
N0.C0.D1.R0.S07: RdPtrOffsetTxDq: 06
N2.C1.D1.R1.S04: RdPtrOffsetTxDqs: 06
N4.C0.D1.R1.S02: RdPtrOffsetTxDq: 05
N6.C0.D1.R0.S01: RdPtrOffsetTxDq: 07
N0.C0.D1.R0.S08: RdPtrOffsetTxDq: 06
N2.C1.D1.R1.S04: PiTxDqs: 42
N4.C0.D1.R1.S02: RdPtrOffsetTxDqs: 07
N6.C0.D1.R0.S02: RdPtrOffsetTxDq: 07
N0.C0.D1.R0.S09: RdPtrOffsetTxDq: 07
N2.C1.D1.R1.S05: wrcmd2dqsstartlatency: 04
N4.C0.D1.R1.S02: PiTxDqs: 30
N6.C0.D1.R0.S03: RdPtrOffsetTxDq: 07
N0.C0.D1.R0.S10: RdPtrOffsetTxDq: 07
N2.C1.D1.R1.S05: RdPtrOffsetTxDq: 05
N4.C0.D1.R1.S03: wrcmd2dqsstartlatency: 04
N6.C0.D1.R0.S04: RdPtrOffsetTxDq: 07
N0.C0.D1.R0.S11: RdPtrOffsetTxDq: 06
N2.C1.D1.R1.S05: RdPtrOffsetTxDqs: 06
N4.C0.D1.R1.S03: RdPtrOffsetTxDq: 05
N6.C0.D1.R0.S05: RdPtrOffsetTxDq: 07
N0.C0.D1.R0.S12: RdPtrOffsetTxDq: 06
N2.C1.D1.R1.S05: PiTxDqs: 57
N4.C0.D1.R1.S03: RdPtrOffsetTxDqs: 07
N6.C0.D1.R0.S06: RdPtrOffsetTxDq: 07
N0.C0.D1.R0.S13: RdPtrOffsetTxDq: 06
N2.C1.D1.R1.S06: wrcmd2dqsstartlatency: 04
N4.C0.D1.R1.S03: PiTxDqs: 14
N6.C0.D1.R0.S07: RdPtrOffsetTxDq: 07
N0.C0.D1.R0.S14: RdPtrOffsetTxDq: 06
N2.C1.D1.R1.S06: RdPtrOffsetTxDq: 05
N4.C0.D1.R1.S04: wrcmd2dqsstartlatency: 04
N6.C0.D1.R0.S08: RdPtrOffsetTxDq: 07
N0.C0.D1.R0.S15: RdPtrOffsetTxDq: 06
N2.C1.D1.R1.S06: RdPtrOffsetTxDqs: 07
N4.C0.D1.R1.S04: RdPtrOffsetTxDq: 05
N6.C0.D1.R0.S09: RdPtrOffsetTxDq: 08
N0.C0.D1.R0.S16: RdPtrOffsetTxDq: 06
N2.C1.D1.R1.S06: PiTxDqs: 05
N4.C0.D1.R1.S04: RdPtrOffsetTxDqs: 06
N6.C0.D1.R0.S10: RdPtrOffsetTxDq: 08
N0.C0.D1.R0.S17: RdPtrOffsetTxDq: 06
N2.C1.D1.R1.S07: wrcmd2dqsstartlatency: 04
N4.C0.D1.R1.S04: PiTxDqs: 42
N6.C0.D1.R0.S11: RdPtrOffsetTxDq: 07
N0.C0.D1.R0.S00: RdPtrOffsetTxDq: 08
N2.C1.D1.R1.S07: RdPtrOffsetTxDq: 05
N4.C0.D1.R1.S05: wrcmd2dqsstartlatency: 04
N6.C0.D1.R0.S12: RdPtrOffsetTxDq: 07
N0.C0.D1.R0.S01: RdPtrOffsetTxDq: 08
N2.C1.D1.R1.S07: RdPtrOffsetTxDqs: 07
N4.C0.D1.R1.S05: RdPtrOffsetTxDq: 05
N6.C0.D1.R0.S13: RdPtrOffsetTxDq: 07
N0.C0.D1.R0.S02: RdPtrOffsetTxDq: 07
N2.C1.D1.R1.S07: PiTxDqs: 24
N4.C0.D1.R1.S05: RdPtrOffsetTxDqs: 06
N6.C0.D1.R0.S14: RdPtrOffsetTxDq: 07
N0.C0.D1.R0.S03: RdPtrOffsetTxDq: 07
N2.C1.D1.R1.S08: wrcmd2dqsstartlatency: 04
N4.C0.D1.R1.S05: PiTxDqs: 62
N6.C0.D1.R0.S15: RdPtrOffsetTxDq: 07
N0.C0.D1.R0.S04: RdPtrOffsetTxDq: 07
N2.C1.D1.R1.S08: RdPtrOffsetTxDq: 05
N4.C0.D1.R1.S06: wrcmd2dqsstartlatency: 04
N6.C0.D1.R0.S16: RdPtrOffsetTxDq: 07
N0.C0.D1.R0.S05: RdPtrOffsetTxDq: 07
N2.C1.D1.R1.S08: RdPtrOffsetTxDqs: 06
N4.C0.D1.R1.S06: RdPtrOffsetTxDq: 05
N6.C0.D1.R0.S17: RdPtrOffsetTxDq: 07
N0.C0.D1.R0.S06: RdPtrOffsetTxDq: 07
N2.C1.D1.R1.S08: PiTxDqs: 54
N4.C0.D1.R1.S06: RdPtrOffsetTxDqs: 06
N6.C0.D1.R0.S00: Total Delay in PI ticks: TxDQ = 983
N0.C0.D1.R0.S07: RdPtrOffsetTxDq: 07
N2.C1.D1.R1.S09: wrcmd2dqsstartlatency: 04
N4.C0.D1.R1.S06: PiTxDqs: 62
N6.C0.D1.R0.S01: Total Delay in PI ticks: TxDQ = 962
N0.C0.D1.R0.S08: RdPtrOffsetTxDq: 07
N2.C1.D1.R1.S09: RdPtrOffsetTxDq: 06
N4.C0.D1.R1.S07: wrcmd2dqsstartlatency: 04
N6.C0.D1.R0.S02: Total Delay in PI ticks: TxDQ = 950
N0.C0.D1.R0.S09: RdPtrOffsetTxDq: 08
N2.C1.D1.R1.S09: RdPtrOffsetTxDqs: 07
N4.C0.D1.R1.S07: RdPtrOffsetTxDq: 05
N6.C0.D1.R0.S03: Total Delay in PI ticks: TxDQ = 938
N0.C0.D1.R0.S10: RdPtrOffsetTxDq: 08
N2.C1.D1.R1.S09: PiTxDqs: 49
N4.C0.D1.R1.S07: RdPtrOffsetTxDqs: 07
N6.C0.D1.R0.S04: Total Delay in PI ticks: TxDQ = 901
N0.C0.D1.R0.S11: RdPtrOffsetTxDq: 07
N2.C1.D1.R1.S10: wrcmd2dqsstartlatency: 04
N4.C0.D1.R1.S07: PiTxDqs: 15
N6.C0.D1.R0.S05: Total Delay in PI ticks: TxDQ = 920
N0.C0.D1.R0.S12: RdPtrOffsetTxDq: 07
N2.C1.D1.R1.S10: RdPtrOffsetTxDq: 05
N4.C0.D1.R1.S08: wrcmd2dqsstartlatency: 04
N6.C0.D1.R0.S06: Total Delay in PI ticks: TxDQ = 924
N0.C0.D1.R0.S13: RdPtrOffsetTxDq: 07
N2.C1.D1.R1.S10: RdPtrOffsetTxDqs: 07
N4.C0.D1.R1.S08: RdPtrOffsetTxDq: 05
N6.C0.D1.R0.S07: Total Delay in PI ticks: TxDQ = 939
N0.C0.D1.R0.S14: RdPtrOffsetTxDq: 07
N2.C1.D1.R1.S10: PiTxDqs: 34
N4.C0.D1.R1.S08: RdPtrOffsetTxDqs: 06
N6.C0.D1.R0.S08: Total Delay in PI ticks: TxDQ = 911
N0.C0.D1.R0.S15: RdPtrOffsetTxDq: 07
N2.C1.D1.R1.S11: wrcmd2dqsstartlatency: 04
N4.C0.D1.R1.S08: PiTxDqs: 49
N6.C0.D1.R0.S09: Total Delay in PI ticks: TxDQ = 981
N0.C0.D1.R0.S16: RdPtrOffsetTxDq: 07
N2.C1.D1.R1.S11: RdPtrOffsetTxDq: 05
N4.C0.D1.R1.S09: wrcmd2dqsstartlatency: 04
N6.C0.D1.R0.S10: Total Delay in PI ticks: TxDQ = 963
N0.C0.D1.R0.S17: RdPtrOffsetTxDq: 07
N2.C1.D1.R1.S11: RdPtrOffsetTxDqs: 07
N4.C0.D1.R1.S09: RdPtrOffsetTxDq: 06
N6.C0.D1.R0.S11: Total Delay in PI ticks: TxDQ = 949
N0.C0.D1.R0.S00: Total Delay in PI ticks: TxDQ = 988
N2.C1.D1.R1.S11: PiTxDqs: 27
N4.C0.D1.R1.S09: RdPtrOffsetTxDqs: 07
N6.C0.D1.R0.S12: Total Delay in PI ticks: TxDQ = 937
N0.C0.D1.R0.S01: Total Delay in PI ticks: TxDQ = 970
N2.C1.D1.R1.S12: wrcmd2dqsstartlatency: 04
N4.C0.D1.R1.S09: PiTxDqs: 57
N6.C0.D1.R0.S13: Total Delay in PI ticks: TxDQ = 902
N0.C0.D1.R0.S02: Total Delay in PI ticks: TxDQ = 956
N2.C1.D1.R1.S12: RdPtrOffsetTxDq: 05
N4.C0.D1.R1.S10: wrcmd2dqsstartlatency: 04
N6.C0.D1.R0.S14: Total Delay in PI ticks: TxDQ = 921
N0.C0.D1.R0.S03: Total Delay in PI ticks: TxDQ = 941
N2.C1.D1.R1.S12: RdPtrOffsetTxDqs: 07
N4.C0.D1.R1.S10: RdPtrOffsetTxDq: 06
N6.C0.D1.R0.S15: Total Delay in PI ticks: TxDQ = 923
N0.C0.D1.R0.S04: Total Delay in PI ticks: TxDQ = 907
N2.C1.D1.R1.S12: PiTxDqs: 14
N4.C0.D1.R1.S10: RdPtrOffsetTxDqs: 07
N6.C0.D1.R0.S16: Total Delay in PI ticks: TxDQ = 940
N0.C0.D1.R0.S05: Total Delay in PI ticks: TxDQ = 925
N2.C1.D1.R1.S13: wrcmd2dqsstartlatency: 04
N4.C0.D1.R1.S10: PiTxDqs: 43
N6.C0.D1.R0.S17: Total Delay in PI ticks: TxDQ = 910
N0.C0.D1.R0.S06: Total Delay in PI ticks: TxDQ = 926
N2.C1.D1.R1.S13: RdPtrOffsetTxDq: 05
N4.C0.D1.R1.S11: wrcmd2dqsstartlatency: 04
N6.C0.D1.R1.S00: wrcmd2dqsstartlatency: 04
N0.C0.D1.R0.S07: Total Delay in PI ticks: TxDQ = 947
N2.C1.D1.R1.S13: RdPtrOffsetTxDqs: 06
N4.C0.D1.R1.S11: RdPtrOffsetTxDq: 05
N6.C0.D1.R1.S00: RdPtrOffsetTxDq: 06
N0.C0.D1.R0.S08: Total Delay in PI ticks: TxDQ = 916
N2.C1.D1.R1.S13: PiTxDqs: 41
N4.C0.D1.R1.S11: RdPtrOffsetTxDqs: 07
N6.C0.D1.R1.S00: RdPtrOffsetTxDqs: 07
N0.C0.D1.R0.S09: Total Delay in PI ticks: TxDQ = 985
N2.C1.D1.R1.S14: wrcmd2dqsstartlatency: 04
N4.C0.D1.R1.S11: PiTxDqs: 30
N6.C0.D1.R1.S00: PiTxDqs: 48
N0.C0.D1.R0.S10: Total Delay in PI ticks: TxDQ = 970
N2.C1.D1.R1.S14: RdPtrOffsetTxDq: 05
N4.C0.D1.R1.S12: wrcmd2dqsstartlatency: 04
N6.C0.D1.R1.S01: wrcmd2dqsstartlatency: 04
N0.C0.D1.R0.S11: Total Delay in PI ticks: TxDQ = 956
N2.C1.D1.R1.S14: RdPtrOffsetTxDqs: 06
N4.C0.D1.R1.S12: RdPtrOffsetTxDq: 05
N6.C0.D1.R1.S01: RdPtrOffsetTxDq: 05
N0.C0.D1.R0.S12: Total Delay in PI ticks: TxDQ = 944
N2.C1.D1.R1.S14: PiTxDqs: 56
N4.C0.D1.R1.S12: RdPtrOffsetTxDqs: 07
N6.C0.D1.R1.S01: RdPtrOffsetTxDqs: 07
N0.C0.D1.R0.S13: Total Delay in PI ticks: TxDQ = 909
N2.C1.D1.R1.S15: wrcmd2dqsstartlatency: 04
N4.C0.D1.R1.S12: PiTxDqs: 16
N6.C0.D1.R1.S01: PiTxDqs: 32
N0.C0.D1.R0.S14: Total Delay in PI ticks: TxDQ = 925
N2.C1.D1.R1.S15: RdPtrOffsetTxDq: 05
N4.C0.D1.R1.S13: wrcmd2dqsstartlatency: 04
N6.C0.D1.R1.S02: wrcmd2dqsstartlatency: 04
N0.C0.D1.R0.S15: Total Delay in PI ticks: TxDQ = 928
N2.C1.D1.R1.S15: RdPtrOffsetTxDqs: 07
N4.C0.D1.R1.S13: RdPtrOffsetTxDq: 05
N6.C0.D1.R1.S02: RdPtrOffsetTxDq: 05
N0.C0.D1.R0.S16: Total Delay in PI ticks: TxDQ = 947
N2.C1.D1.R1.S15: PiTxDqs: 03
N4.C0.D1.R1.S13: RdPtrOffsetTxDqs: 06
N6.C0.D1.R1.S02: RdPtrOffsetTxDqs: 07
N0.C0.D1.R0.S17: Total Delay in PI ticks: TxDQ = 916
N2.C1.D1.R1.S16: wrcmd2dqsstartlatency: 04
N4.C0.D1.R1.S13: PiTxDqs: 45
N6.C0.D1.R1.S02: PiTxDqs: 18
N0.C0.D1.R1.S00: wrcmd2dqsstartlatency: 04
N2.C1.D1.R1.S16: RdPtrOffsetTxDq: 05
N4.C0.D1.R1.S14: wrcmd2dqsstartlatency: 04
N6.C0.D1.R1.S03: wrcmd2dqsstartlatency: 04
N0.C0.D1.R1.S00: RdPtrOffsetTxDq: 06
N2.C1.D1.R1.S16: RdPtrOffsetTxDqs: 07
N4.C0.D1.R1.S14: RdPtrOffsetTxDq: 05
N6.C0.D1.R1.S03: RdPtrOffsetTxDq: 05
N0.C0.D1.R1.S00: RdPtrOffsetTxDqs: 07
N2.C1.D1.R1.S16: PiTxDqs: 24
N4.C0.D1.R1.S14: RdPtrOffsetTxDqs: 06
N6.C0.D1.R1.S03: RdPtrOffsetTxDqs: 07
N0.C0.D1.R1.S00: PiTxDqs: 57
N2.C1.D1.R1.S17: wrcmd2dqsstartlatency: 04
N4.C0.D1.R1.S14: PiTxDqs: 61
N6.C0.D1.R1.S03: PiTxDqs: 06
N0.C0.D1.R1.S01: wrcmd2dqsstartlatency: 04
N2.C1.D1.R1.S17: RdPtrOffsetTxDq: 05
N4.C0.D1.R1.S15: wrcmd2dqsstartlatency: 04
N6.C0.D1.R1.S04: wrcmd2dqsstartlatency: 04
N0.C0.D1.R1.S01: RdPtrOffsetTxDq: 06
N2.C1.D1.R1.S17: RdPtrOffsetTxDqs: 06
N4.C0.D1.R1.S15: RdPtrOffsetTxDq: 05
N6.C0.D1.R1.S04: RdPtrOffsetTxDq: 04
N0.C0.D1.R1.S01: RdPtrOffsetTxDqs: 07
N2.C1.D1.R1.S17: PiTxDqs: 53
N4.C0.D1.R1.S15: RdPtrOffsetTxDqs: 06
N6.C0.D1.R1.S04: RdPtrOffsetTxDqs: 06
N0.C0.D1.R1.S01: PiTxDqs: 41
N2.C1.D1.R1.S00: RdPtrOffsetTxDq: 07
N4.C0.D1.R1.S15: PiTxDqs: 63
N6.C0.D1.R1.S04: PiTxDqs: 34
N0.C0.D1.R1.S02: wrcmd2dqsstartlatency: 04
N2.C1.D1.R1.S01: RdPtrOffsetTxDq: 06
N4.C0.D1.R1.S16: wrcmd2dqsstartlatency: 04
N6.C0.D1.R1.S05: wrcmd2dqsstartlatency: 04
N0.C0.D1.R1.S02: RdPtrOffsetTxDq: 05
N2.C1.D1.R1.S02: RdPtrOffsetTxDq: 06
N4.C0.D1.R1.S16: RdPtrOffsetTxDq: 05
N6.C0.D1.R1.S05: RdPtrOffsetTxDq: 05
N0.C0.D1.R1.S02: RdPtrOffsetTxDqs: 07
N2.C1.D1.R1.S03: RdPtrOffsetTxDq: 06
N4.C0.D1.R1.S16: RdPtrOffsetTxDqs: 07
N6.C0.D1.R1.S05: RdPtrOffsetTxDqs: 06
N0.C0.D1.R1.S02: PiTxDqs: 30
N2.C1.D1.R1.S04: RdPtrOffsetTxDq: 06
N4.C0.D1.R1.S16: PiTxDqs: 15
N6.C0.D1.R1.S05: PiTxDqs: 54
N0.C0.D1.R1.S03: wrcmd2dqsstartlatency: 04
N2.C1.D1.R1.S05: RdPtrOffsetTxDq: 06
N4.C0.D1.R1.S17: wrcmd2dqsstartlatency: 04
N6.C0.D1.R1.S06: wrcmd2dqsstartlatency: 04
N0.C0.D1.R1.S03: RdPtrOffsetTxDq: 05
N2.C1.D1.R1.S06: RdPtrOffsetTxDq: 06
N4.C0.D1.R1.S17: RdPtrOffsetTxDq: 05
N6.C0.D1.R1.S06: RdPtrOffsetTxDq: 05
N0.C0.D1.R1.S03: RdPtrOffsetTxDqs: 07
N2.C1.D1.R1.S07: RdPtrOffsetTxDq: 06
N4.C0.D1.R1.S17: RdPtrOffsetTxDqs: 06
N6.C0.D1.R1.S06: RdPtrOffsetTxDqs: 06
N0.C0.D1.R1.S03: PiTxDqs: 14
N2.C1.D1.R1.S08: RdPtrOffsetTxDq: 06
N4.C0.D1.R1.S17: PiTxDqs: 48
N6.C0.D1.R1.S06: PiTxDqs: 56
N0.C0.D1.R1.S04: wrcmd2dqsstartlatency: 04
N2.C1.D1.R1.S09: RdPtrOffsetTxDq: 07
N4.C0.D1.R1.S00: RdPtrOffsetTxDq: 07
N6.C0.D1.R1.S07: wrcmd2dqsstartlatency: 04
N0.C0.D1.R1.S04: RdPtrOffsetTxDq: 05
N2.C1.D1.R1.S10: RdPtrOffsetTxDq: 06
N4.C0.D1.R1.S01: RdPtrOffsetTxDq: 07
N6.C0.D1.R1.S07: RdPtrOffsetTxDq: 05
N0.C0.D1.R1.S04: RdPtrOffsetTxDqs: 06
N2.C1.D1.R1.S11: RdPtrOffsetTxDq: 06
N4.C0.D1.R1.S02: RdPtrOffsetTxDq: 06
N6.C0.D1.R1.S07: RdPtrOffsetTxDqs: 07
N0.C0.D1.R1.S04: PiTxDqs: 44
N2.C1.D1.R1.S12: RdPtrOffsetTxDq: 06
N4.C0.D1.R1.S03: RdPtrOffsetTxDq: 06
N6.C0.D1.R1.S07: PiTxDqs: 08
N0.C0.D1.R1.S05: wrcmd2dqsstartlatency: 04
N2.C1.D1.R1.S13: RdPtrOffsetTxDq: 06
N4.C0.D1.R1.S04: RdPtrOffsetTxDq: 06
N6.C0.D1.R1.S08: wrcmd2dqsstartlatency: 04
N0.C0.D1.R1.S05: RdPtrOffsetTxDq: 05
N2.C1.D1.R1.S14: RdPtrOffsetTxDq: 06
N4.C0.D1.R1.S05: RdPtrOffsetTxDq: 06
N6.C0.D1.R1.S08: RdPtrOffsetTxDq: 05
N0.C0.D1.R1.S05: RdPtrOffsetTxDqs: 07
N2.C1.D1.R1.S15: RdPtrOffsetTxDq: 06
N4.C0.D1.R1.S06: RdPtrOffsetTxDq: 06
N6.C0.D1.R1.S08: RdPtrOffsetTxDqs: 06
N0.C0.D1.R1.S05: PiTxDqs: 00
N2.C1.D1.R1.S16: RdPtrOffsetTxDq: 06
N4.C0.D1.R1.S07: RdPtrOffsetTxDq: 06
N6.C0.D1.R1.S08: PiTxDqs: 42
N0.C0.D1.R1.S06: wrcmd2dqsstartlatency: 04
N2.C1.D1.R1.S17: RdPtrOffsetTxDq: 06
N4.C0.D1.R1.S08: RdPtrOffsetTxDq: 06
N6.C0.D1.R1.S09: wrcmd2dqsstartlatency: 04
N0.C0.D1.R1.S06: RdPtrOffsetTxDq: 05
N2.C1.D1.R1.S00: RdPtrOffsetTxDq: 08
N4.C0.D1.R1.S09: RdPtrOffsetTxDq: 07
N6.C0.D1.R1.S09: RdPtrOffsetTxDq: 06
N0.C0.D1.R1.S06: RdPtrOffsetTxDqs: 07
N2.C1.D1.R1.S01: RdPtrOffsetTxDq: 07
N4.C0.D1.R1.S10: RdPtrOffsetTxDq: 07
N6.C0.D1.R1.S09: RdPtrOffsetTxDqs: 07
N0.C0.D1.R1.S06: PiTxDqs: 00
N2.C1.D1.R1.S02: RdPtrOffsetTxDq: 07
N4.C0.D1.R1.S11: RdPtrOffsetTxDq: 06
N6.C0.D1.R1.S09: PiTxDqs: 49
N0.C0.D1.R1.S07: wrcmd2dqsstartlatency: 04
N2.C1.D1.R1.S03: RdPtrOffsetTxDq: 07
N4.C0.D1.R1.S12: RdPtrOffsetTxDq: 06
N6.C0.D1.R1.S10: wrcmd2dqsstartlatency: 04
N0.C0.D1.R1.S07: RdPtrOffsetTxDq: 05
N2.C1.D1.R1.S04: RdPtrOffsetTxDq: 07
N4.C0.D1.R1.S13: RdPtrOffsetTxDq: 06
N6.C0.D1.R1.S10: RdPtrOffsetTxDq: 06
N0.C0.D1.R1.S07: RdPtrOffsetTxDqs: 07
N2.C1.D1.R1.S05: RdPtrOffsetTxDq: 07
N4.C0.D1.R1.S14: RdPtrOffsetTxDq: 06
N6.C0.D1.R1.S10: RdPtrOffsetTxDqs: 07
N0.C0.D1.R1.S07: PiTxDqs: 16
N2.C1.D1.R1.S06: RdPtrOffsetTxDq: 07
N4.C0.D1.R1.S15: RdPtrOffsetTxDq: 06
N6.C0.D1.R1.S10: PiTxDqs: 33
N0.C0.D1.R1.S08: wrcmd2dqsstartlatency: 04
N2.C1.D1.R1.S07: RdPtrOffsetTxDq: 07
N4.C0.D1.R1.S16: RdPtrOffsetTxDq: 06
N6.C0.D1.R1.S11: wrcmd2dqsstartlatency: 04
N0.C0.D1.R1.S08: RdPtrOffsetTxDq: 05
N2.C1.D1.R1.S08: RdPtrOffsetTxDq: 07
N4.C0.D1.R1.S17: RdPtrOffsetTxDq: 06
N6.C0.D1.R1.S11: RdPtrOffsetTxDq: 05
N0.C0.D1.R1.S08: RdPtrOffsetTxDqs: 06
N2.C1.D1.R1.S09: RdPtrOffsetTxDq: 08
N4.C0.D1.R1.S00: RdPtrOffsetTxDq: 08
N6.C0.D1.R1.S11: RdPtrOffsetTxDqs: 07
N0.C0.D1.R1.S08: PiTxDqs: 48
N2.C1.D1.R1.S10: RdPtrOffsetTxDq: 07
N4.C0.D1.R1.S01: RdPtrOffsetTxDq: 08
N6.C0.D1.R1.S11: PiTxDqs: 22
N0.C0.D1.R1.S09: wrcmd2dqsstartlatency: 04
N2.C1.D1.R1.S11: RdPtrOffsetTxDq: 07
N4.C0.D1.R1.S02: RdPtrOffsetTxDq: 07
N6.C0.D1.R1.S12: wrcmd2dqsstartlatency: 04
N0.C0.D1.R1.S09: RdPtrOffsetTxDq: 06
N2.C1.D1.R1.S12: RdPtrOffsetTxDq: 07
N4.C0.D1.R1.S03: RdPtrOffsetTxDq: 07
N6.C0.D1.R1.S12: RdPtrOffsetTxDq: 05
N0.C0.D1.R1.S09: RdPtrOffsetTxDqs: 07
N2.C1.D1.R1.S13: RdPtrOffsetTxDq: 07
N4.C0.D1.R1.S04: RdPtrOffsetTxDq: 07
N6.C0.D1.R1.S12: RdPtrOffsetTxDqs: 07
N0.C0.D1.R1.S09: PiTxDqs: 57
N2.C1.D1.R1.S14: RdPtrOffsetTxDq: 07
N4.C0.D1.R1.S05: RdPtrOffsetTxDq: 07
N6.C0.D1.R1.S12: PiTxDqs: 06
N0.C0.D1.R1.S10: wrcmd2dqsstartlatency: 04
N2.C1.D1.R1.S15: RdPtrOffsetTxDq: 07
N4.C0.D1.R1.S06: RdPtrOffsetTxDq: 07
N6.C0.D1.R1.S13: wrcmd2dqsstartlatency: 04
N0.C0.D1.R1.S10: RdPtrOffsetTxDq: 06
N2.C1.D1.R1.S16: RdPtrOffsetTxDq: 07
N4.C0.D1.R1.S07: RdPtrOffsetTxDq: 07
N6.C0.D1.R1.S13: RdPtrOffsetTxDq: 04
N0.C0.D1.R1.S10: RdPtrOffsetTxDqs: 07
N2.C1.D1.R1.S17: RdPtrOffsetTxDq: 07
N4.C0.D1.R1.S08: RdPtrOffsetTxDq: 07
N6.C0.D1.R1.S13: RdPtrOffsetTxDqs: 06
N0.C0.D1.R1.S10: PiTxDqs: 42
N2.C1.D1.R1.S00: Total Delay in PI ticks: TxDQ = 980
N4.C0.D1.R1.S09: RdPtrOffsetTxDq: 08
N6.C0.D1.R1.S13: PiTxDqs: 34
N0.C0.D1.R1.S11: wrcmd2dqsstartlatency: 04
N2.C1.D1.R1.S01: Total Delay in PI ticks: TxDQ = 962
N4.C0.D1.R1.S10: RdPtrOffsetTxDq: 08
N6.C0.D1.R1.S14: wrcmd2dqsstartlatency: 04
N0.C0.D1.R1.S11: RdPtrOffsetTxDq: 05
N2.C1.D1.R1.S02: Total Delay in PI ticks: TxDQ = 954
N4.C0.D1.R1.S11: RdPtrOffsetTxDq: 07
N6.C0.D1.R1.S14: RdPtrOffsetTxDq: 05
N0.C0.D1.R1.S11: RdPtrOffsetTxDqs: 07
N2.C1.D1.R1.S03: Total Delay in PI ticks: TxDQ = 939
N4.C0.D1.R1.S12: RdPtrOffsetTxDq: 07
N6.C0.D1.R1.S14: RdPtrOffsetTxDqs: 06
N0.C0.D1.R1.S11: PiTxDqs: 30
N2.C1.D1.R1.S04: Total Delay in PI ticks: TxDQ = 906
N4.C0.D1.R1.S13: RdPtrOffsetTxDq: 07
N6.C0.D1.R1.S14: PiTxDqs: 53
N0.C0.D1.R1.S12: wrcmd2dqsstartlatency: 04
N2.C1.D1.R1.S05: Total Delay in PI ticks: TxDQ = 919
N4.C0.D1.R1.S14: RdPtrOffsetTxDq: 07
N6.C0.D1.R1.S15: wrcmd2dqsstartlatency: 04
N0.C0.D1.R1.S12: RdPtrOffsetTxDq: 05
N2.C1.D1.R1.S06: Total Delay in PI ticks: TxDQ = 933
N4.C0.D1.R1.S15: RdPtrOffsetTxDq: 07
N6.C0.D1.R1.S15: RdPtrOffsetTxDq: 05
N0.C0.D1.R1.S12: RdPtrOffsetTxDqs: 07
N2.C1.D1.R1.S07: Total Delay in PI ticks: TxDQ = 949
N4.C0.D1.R1.S16: RdPtrOffsetTxDq: 07
N6.C0.D1.R1.S15: RdPtrOffsetTxDqs: 06
N0.C0.D1.R1.S12: PiTxDqs: 15
N2.C1.D1.R1.S08: Total Delay in PI ticks: TxDQ = 917
N4.C0.D1.R1.S17: RdPtrOffsetTxDq: 07
N6.C0.D1.R1.S15: PiTxDqs: 56
N0.C0.D1.R1.S13: wrcmd2dqsstartlatency: 04
N2.C1.D1.R1.S09: Total Delay in PI ticks: TxDQ = 977
N4.C0.D1.R1.S00: Total Delay in PI ticks: TxDQ = 983
N6.C0.D1.R1.S16: wrcmd2dqsstartlatency: 04
N0.C0.D1.R1.S13: RdPtrOffsetTxDq: 05
N2.C1.D1.R1.S10: Total Delay in PI ticks: TxDQ = 962
N4.C0.D1.R1.S01: Total Delay in PI ticks: TxDQ = 968
N6.C0.D1.R1.S16: RdPtrOffsetTxDq: 05
N0.C0.D1.R1.S13: RdPtrOffsetTxDqs: 06
N2.C1.D1.R1.S11: Total Delay in PI ticks: TxDQ = 956
N4.C0.D1.R1.S02: Total Delay in PI ticks: TxDQ = 953
N6.C0.D1.R1.S16: RdPtrOffsetTxDqs: 07
N0.C0.D1.R1.S13: PiTxDqs: 46
N2.C1.D1.R1.S12: Total Delay in PI ticks: TxDQ = 942
N4.C0.D1.R1.S03: Total Delay in PI ticks: TxDQ = 936
N6.C0.D1.R1.S16: PiTxDqs: 07
N0.C0.D1.R1.S14: wrcmd2dqsstartlatency: 04
N2.C1.D1.R1.S13: Total Delay in PI ticks: TxDQ = 906
N4.C0.D1.R1.S04: Total Delay in PI ticks: TxDQ = 904
N6.C0.D1.R1.S17: wrcmd2dqsstartlatency: 04
N0.C0.D1.R1.S14: RdPtrOffsetTxDq: 05
N2.C1.D1.R1.S14: Total Delay in PI ticks: TxDQ = 920
N4.C0.D1.R1.S05: Total Delay in PI ticks: TxDQ = 922
N6.C0.D1.R1.S17: RdPtrOffsetTxDq: 05
N0.C0.D1.R1.S14: RdPtrOffsetTxDqs: 06
N2.C1.D1.R1.S15: Total Delay in PI ticks: TxDQ = 933
N4.C0.D1.R1.S06: Total Delay in PI ticks: TxDQ = 924
N6.C0.D1.R1.S17: RdPtrOffsetTxDqs: 06
N0.C0.D1.R1.S14: PiTxDqs: 62
N2.C1.D1.R1.S16: Total Delay in PI ticks: TxDQ = 951
N4.C0.D1.R1.S07: Total Delay in PI ticks: TxDQ = 940
N6.C0.D1.R1.S17: PiTxDqs: 42
N0.C0.D1.R1.S15: wrcmd2dqsstartlatency: 04
N2.C1.D1.R1.S17: Total Delay in PI ticks: TxDQ = 917
N4.C0.D1.R1.S08: Total Delay in PI ticks: TxDQ = 912
N6.C0.D1.R1.S00: RdPtrOffsetTxDq: 07
N0.C0.D1.R1.S15: RdPtrOffsetTxDq: 05
N2.C1: Calculating Optimimum DQ/DQS Values
N4.C0.D1.R1.S09: Total Delay in PI ticks: TxDQ = 984
N6.C0.D1.R1.S01: RdPtrOffsetTxDq: 06
N0.C0.D1.R1.S15: RdPtrOffsetTxDqs: 07
N4.C0.D1.R1.S10: Total Delay in PI ticks: TxDQ = 968
N6.C0.D1.R1.S02: RdPtrOffsetTxDq: 06
N0.C0.D1.R1.S15: PiTxDqs: 01
START_DATA_TX_DQ
N4.C0.D1.R1.S11: Total Delay in PI ticks: TxDQ = 952
N6.C0.D1.R1.S03: RdPtrOffsetTxDq: 06
N0.C0.D1.R1.S16: wrcmd2dqsstartlatency: 04
N2.C1.S00: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 009, RdPtrOffsetTxDqs = 009
N4.C0.D1.R1.S12: Total Delay in PI ticks: TxDQ = 941
N6.C0.D1.R1.S04: RdPtrOffsetTxDq: 05
N0.C0.D1.R1.S16: RdPtrOffsetTxDq: 05
N2.C1.S00: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 009, RdPtrOffsetTxDqs = 009
N4.C0.D1.R1.S13: Total Delay in PI ticks: TxDQ = 905
N6.C0.D1.R1.S05: RdPtrOffsetTxDq: 06
N0.C0.D1.R1.S16: RdPtrOffsetTxDqs: 07
N2.C1.S01: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 009
N4.C0.D1.R1.S14: Total Delay in PI ticks: TxDQ = 923
N6.C0.D1.R1.S06: RdPtrOffsetTxDq: 06
N0.C0.D1.R1.S16: PiTxDqs: 16
N2.C1.S01: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 009
N4.C0.D1.R1.S15: Total Delay in PI ticks: TxDQ = 925
N6.C0.D1.R1.S07: RdPtrOffsetTxDq: 06
N0.C0.D1.R1.S17: wrcmd2dqsstartlatency: 04
N2.C1.S02: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 009
N4.C0.D1.R1.S16: Total Delay in PI ticks: TxDQ = 941
N6.C0.D1.R1.S08: RdPtrOffsetTxDq: 06
N0.C0.D1.R1.S17: RdPtrOffsetTxDq: 05
N2.C1.S02: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 009
N4.C0.D1.R1.S17: Total Delay in PI ticks: TxDQ = 909
N6.C0.D1.R1.S09: RdPtrOffsetTxDq: 07
N0.C0.D1.R1.S17: RdPtrOffsetTxDqs: 06
N2.C1.S03: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 009
N4.C0: Calculating Optimimum DQ/DQS Values
N6.C0.D1.R1.S10: RdPtrOffsetTxDq: 07
N0.C0.D1.R1.S17: PiTxDqs: 49
N2.C1.S03: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 009
N6.C0.D1.R1.S11: RdPtrOffsetTxDq: 06
N0.C0.D1.R1.S00: RdPtrOffsetTxDq: 07
N2.C1.S04: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 008
START_DATA_TX_DQ
N6.C0.D1.R1.S12: RdPtrOffsetTxDq: 06
N0.C0.D1.R1.S01: RdPtrOffsetTxDq: 07
N2.C1.S04: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 008
N4.C0.S00: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 009, RdPtrOffsetTxDqs = 009
N6.C0.D1.R1.S13: RdPtrOffsetTxDq: 05
N0.C0.D1.R1.S02: RdPtrOffsetTxDq: 06
N2.C1.S05: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 008
N4.C0.S00: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 009, RdPtrOffsetTxDqs = 009
N6.C0.D1.R1.S14: RdPtrOffsetTxDq: 06
N0.C0.D1.R1.S03: RdPtrOffsetTxDq: 06
N2.C1.S05: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 008
N4.C0.S01: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 009, RdPtrOffsetTxDqs = 009
N6.C0.D1.R1.S15: RdPtrOffsetTxDq: 06
N0.C0.D1.R1.S04: RdPtrOffsetTxDq: 06
N2.C1.S06: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 008
N4.C0.S01: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 009, RdPtrOffsetTxDqs = 009
N6.C0.D1.R1.S16: RdPtrOffsetTxDq: 06
N0.C0.D1.R1.S05: RdPtrOffsetTxDq: 06
N2.C1.S06: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 008
N4.C0.S02: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 009
N6.C0.D1.R1.S17: RdPtrOffsetTxDq: 06
N0.C0.D1.R1.S06: RdPtrOffsetTxDq: 06
N2.C1.S07: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 009
N4.C0.S02: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 009
N6.C0.D1.R1.S00: RdPtrOffsetTxDq: 08
N0.C0.D1.R1.S07: RdPtrOffsetTxDq: 06
N2.C1.S07: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 009
N4.C0.S03: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 009
N6.C0.D1.R1.S01: RdPtrOffsetTxDq: 07
N0.C0.D1.R1.S08: RdPtrOffsetTxDq: 06
N2.C1.S08: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 008
N4.C0.S03: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 009
N6.C0.D1.R1.S02: RdPtrOffsetTxDq: 07
N0.C0.D1.R1.S09: RdPtrOffsetTxDq: 07
N2.C1.S08: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 008
N4.C0.S04: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 008
N6.C0.D1.R1.S03: RdPtrOffsetTxDq: 07
N0.C0.D1.R1.S10: RdPtrOffsetTxDq: 07
N2.C1.D0.R0.S00: TxDqs: plus1 = 1, minus1 = 0, PI = 46, DB = 0
N4.C0.S04: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 008
N6.C0.D1.R1.S04: RdPtrOffsetTxDq: 06
N0.C0.D1.R1.S11: RdPtrOffsetTxDq: 06
N2.C1.D0.R0.S00: TxDq : plus1 = 1, minus1 = 0, PI = 16, DB = 0
N4.C0.S05: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 008
N6.C0.D1.R1.S05: RdPtrOffsetTxDq: 07
N0.C0.D1.R1.S12: RdPtrOffsetTxDq: 06
N2.C1.D0.R0.S01: TxDqs: plus1 = 1, minus1 = 0, PI = 28, DB = 0
N4.C0.S05: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 008
N6.C0.D1.R1.S06: RdPtrOffsetTxDq: 07
N0.C0.D1.R1.S13: RdPtrOffsetTxDq: 06
N2.C1.D0.R0.S01: TxDq : plus1 = 1, minus1 = 0, PI = 60, DB = 1
N4.C0.S06: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 008
N6.C0.D1.R1.S07: RdPtrOffsetTxDq: 07
N0.C0.D1.R1.S14: RdPtrOffsetTxDq: 06
N2.C1.D0.R0.S02: TxDqs: plus1 = 1, minus1 = 0, PI = 23, DB = 0
N4.C0.S06: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 008
N6.C0.D1.R1.S08: RdPtrOffsetTxDq: 07
N0.C0.D1.R1.S15: RdPtrOffsetTxDq: 06
N2.C1.D0.R0.S02: TxDq : plus1 = 1, minus1 = 0, PI = 55, DB = 1
N4.C0.S07: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 009
N6.C0.D1.R1.S09: RdPtrOffsetTxDq: 08
N0.C0.D1.R1.S16: RdPtrOffsetTxDq: 06
N2.C1.D0.R0.S03: TxDqs: plus1 = 1, minus1 = 0, PI = 05, DB = 1
N4.C0.S07: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 009
N6.C0.D1.R1.S10: RdPtrOffsetTxDq: 08
N0.C0.D1.R1.S17: RdPtrOffsetTxDq: 06
N2.C1.D0.R0.S03: TxDq : plus1 = 1, minus1 = 0, PI = 38, DB = 0
N4.C0.S08: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 008
N6.C0.D1.R1.S11: RdPtrOffsetTxDq: 07
N0.C0.D1.R1.S00: RdPtrOffsetTxDq: 08
N2.C1.D0.R0.S04: TxDqs: plus1 = 1, minus1 = 0, PI = 37, DB = 0
N4.C0.S08: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 008
N6.C0.D1.R1.S12: RdPtrOffsetTxDq: 07
N0.C0.D1.R1.S01: RdPtrOffsetTxDq: 08
N2.C1.D0.R0.S04: TxDq : plus1 = 1, minus1 = 0, PI = 05, DB = 1
N4.C0.D0.R0.S00: TxDqs: plus1 = 1, minus1 = 0, PI = 55, DB = 1
N6.C0.D1.R1.S13: RdPtrOffsetTxDq: 06
N0.C0.D1.R1.S02: RdPtrOffsetTxDq: 07
N2.C1.D0.R0.S05: TxDqs: plus1 = 1, minus1 = 0, PI = 51, DB = 1
N4.C0.D0.R0.S00: TxDq : plus1 = 1, minus1 = 0, PI = 22, DB = 0
N6.C0.D1.R1.S14: RdPtrOffsetTxDq: 07
N0.C0.D1.R1.S03: RdPtrOffsetTxDq: 07
N2.C1.D0.R0.S05: TxDq : plus1 = 1, minus1 = 0, PI = 17, DB = 0
N4.C0.D0.R0.S01: TxDqs: plus1 = 1, minus1 = 0, PI = 36, DB = 0
N6.C0.D1.R1.S15: RdPtrOffsetTxDq: 07
N0.C0.D1.R1.S04: RdPtrOffsetTxDq: 07
N2.C1.D0.R0.S06: TxDqs: plus1 = 1, minus1 = 0, PI = 63, DB = 1
N4.C0.D0.R0.S01: TxDq : plus1 = 1, minus1 = 0, PI = 03, DB = 1
N6.C0.D1.R1.S16: RdPtrOffsetTxDq: 07
N0.C0.D1.R1.S05: RdPtrOffsetTxDq: 07
N2.C1.D0.R0.S06: TxDq : plus1 = 1, minus1 = 0, PI = 32, DB = 0
N4.C0.D0.R0.S02: TxDqs: plus1 = 1, minus1 = 0, PI = 25, DB = 0
N6.C0.D1.R1.S17: RdPtrOffsetTxDq: 07
N0.C0.D1.R1.S06: RdPtrOffsetTxDq: 07
N2.C1.D0.R0.S07: TxDqs: plus1 = 1, minus1 = 0, PI = 16, DB = 0
N4.C0.D0.R0.S02: TxDq : plus1 = 1, minus1 = 0, PI = 54, DB = 1
N6.C0.D1.R1.S00: Total Delay in PI ticks: TxDQ = 979
N0.C0.D1.R1.S07: RdPtrOffsetTxDq: 07
N2.C1.D0.R0.S07: TxDq : plus1 = 1, minus1 = 0, PI = 46, DB = 0
N4.C0.D0.R0.S03: TxDqs: plus1 = 1, minus1 = 0, PI = 07, DB = 1
N6.C0.D1.R1.S01: Total Delay in PI ticks: TxDQ = 961
N0.C0.D1.R1.S08: RdPtrOffsetTxDq: 07
N2.C1.D0.R0.S08: TxDqs: plus1 = 1, minus1 = 0, PI = 51, DB = 1
N4.C0.D0.R0.S03: TxDq : plus1 = 1, minus1 = 0, PI = 37, DB = 0
N6.C0.D1.R1.S02: Total Delay in PI ticks: TxDQ = 946
N0.C0.D1.R1.S09: RdPtrOffsetTxDq: 08
N2.C1.D0.R0.S08: TxDq : plus1 = 1, minus1 = 0, PI = 18, DB = 0
N4.C0.D0.R0.S04: TxDqs: plus1 = 1, minus1 = 0, PI = 39, DB = 0
N6.C0.D1.R1.S03: Total Delay in PI ticks: TxDQ = 933
N0.C0.D1.R1.S10: RdPtrOffsetTxDq: 08
N2.C1.D0.R0.S09: TxDqs: plus1 = 1, minus1 = 0, PI = 45, DB = 0
N4.C0.D0.R0.S04: TxDq : plus1 = 1, minus1 = 0, PI = 06, DB = 1
N6.C0.D1.R1.S04: Total Delay in PI ticks: TxDQ = 897
N0.C0.D1.R1.S11: RdPtrOffsetTxDq: 07
N2.C1.D0.R0.S09: TxDq : plus1 = 1, minus1 = 0, PI = 15, DB = 1
N4.C0.D0.R0.S05: TxDqs: plus1 = 1, minus1 = 0, PI = 57, DB = 1
N6.C0.D1.R1.S05: Total Delay in PI ticks: TxDQ = 917
N0.C0.D1.R1.S12: RdPtrOffsetTxDq: 07
N2.C1.D0.R0.S10: TxDqs: plus1 = 1, minus1 = 0, PI = 28, DB = 0
N4.C0.D0.R0.S05: TxDq : plus1 = 1, minus1 = 0, PI = 22, DB = 0
N6.C0.D1.R1.S06: Total Delay in PI ticks: TxDQ = 920
N0.C0.D1.R1.S13: RdPtrOffsetTxDq: 07
N2.C1.D0.R0.S10: TxDq : plus1 = 1, minus1 = 0, PI = 61, DB = 1
N4.C0.D0.R0.S06: TxDqs: plus1 = 1, minus1 = 0, PI = 57, DB = 1
N6.C0.D1.R1.S07: Total Delay in PI ticks: TxDQ = 936
N0.C0.D1.R1.S14: RdPtrOffsetTxDq: 07
N2.C1.D0.R0.S11: TxDqs: plus1 = 1, minus1 = 0, PI = 22, DB = 0
N4.C0.D0.R0.S06: TxDq : plus1 = 1, minus1 = 0, PI = 23, DB = 0
N6.C0.D1.R1.S08: Total Delay in PI ticks: TxDQ = 906
N0.C0.D1.R1.S15: RdPtrOffsetTxDq: 07
N2.C1.D0.R0.S11: TxDq : plus1 = 1, minus1 = 0, PI = 57, DB = 1
N4.C0.D0.R0.S07: TxDqs: plus1 = 1, minus1 = 0, PI = 10, DB = 1
N6.C0.D1.R1.S09: Total Delay in PI ticks: TxDQ = 977
N0.C0.D1.R1.S16: RdPtrOffsetTxDq: 07
N2.C1.D0.R0.S12: TxDqs: plus1 = 1, minus1 = 0, PI = 05, DB = 1
N4.C0.D0.R0.S07: TxDq : plus1 = 1, minus1 = 0, PI = 41, DB = 0
N6.C0.D1.R1.S10: Total Delay in PI ticks: TxDQ = 961
N0.C0.D1.R1.S17: RdPtrOffsetTxDq: 07
N2.C1.D0.R0.S12: TxDq : plus1 = 1, minus1 = 0, PI = 38, DB = 0
N4.C0.D0.R0.S08: TxDqs: plus1 = 1, minus1 = 0, PI = 51, DB = 1
N6.C0.D1.R1.S11: Total Delay in PI ticks: TxDQ = 948
N0.C0.D1.R1.S00: Total Delay in PI ticks: TxDQ = 985
N2.C1.D0.R0.S13: TxDqs: plus1 = 1, minus1 = 0, PI = 36, DB = 0
N4.C0.D0.R0.S08: TxDq : plus1 = 1, minus1 = 0, PI = 17, DB = 0
N6.C0.D1.R1.S12: Total Delay in PI ticks: TxDQ = 932
N0.C0.D1.R1.S01: Total Delay in PI ticks: TxDQ = 968
N2.C1.D0.R0.S13: TxDq : plus1 = 1, minus1 = 0, PI = 06, DB = 1
N4.C0.D0.R0.S09: TxDqs: plus1 = 1, minus1 = 0, PI = 53, DB = 1
N6.C0.D1.R1.S13: Total Delay in PI ticks: TxDQ = 896
N0.C0.D1.R1.S02: Total Delay in PI ticks: TxDQ = 954
N2.C1.D0.R0.S14: TxDqs: plus1 = 1, minus1 = 0, PI = 51, DB = 1
N4.C0.D0.R0.S09: TxDq : plus1 = 1, minus1 = 0, PI = 21, DB = 0
N6.C0.D1.R1.S14: Total Delay in PI ticks: TxDQ = 916
N0.C0.D1.R1.S03: Total Delay in PI ticks: TxDQ = 939
N2.C1.D0.R0.S14: TxDq : plus1 = 1, minus1 = 0, PI = 18, DB = 0
N4.C0.D0.R0.S10: TxDqs: plus1 = 1, minus1 = 0, PI = 35, DB = 0
N6.C0.D1.R1.S15: Total Delay in PI ticks: TxDQ = 919
N0.C0.D1.R1.S04: Total Delay in PI ticks: TxDQ = 907
N2.C1.D0.R0.S15: TxDqs: plus1 = 1, minus1 = 0, PI = 63, DB = 1
N4.C0.D0.R0.S10: TxDq : plus1 = 1, minus1 = 0, PI = 01, DB = 1
N6.C0.D1.R1.S16: Total Delay in PI ticks: TxDQ = 934
N0.C0.D1.R1.S05: Total Delay in PI ticks: TxDQ = 925
N2.C1.D0.R0.S15: TxDq : plus1 = 1, minus1 = 0, PI = 33, DB = 0
N4.C0.D0.R0.S11: TxDqs: plus1 = 1, minus1 = 0, PI = 24, DB = 0
N6.C0.D1.R1.S17: Total Delay in PI ticks: TxDQ = 905
N0.C0.D1.R1.S06: Total Delay in PI ticks: TxDQ = 927
N2.C1.D0.R0.S16: TxDqs: plus1 = 1, minus1 = 0, PI = 18, DB = 0
N4.C0.D0.R0.S11: TxDq : plus1 = 1, minus1 = 0, PI = 54, DB = 1
N6.C0: Calculating Optimimum DQ/DQS Values
N0.C0.D1.R1.S07: Total Delay in PI ticks: TxDQ = 941
N2.C1.D0.R0.S16: TxDq : plus1 = 1, minus1 = 0, PI = 49, DB = 1
N4.C0.D0.R0.S12: TxDqs: plus1 = 1, minus1 = 0, PI = 08, DB = 1
N0.C0.D1.R1.S08: Total Delay in PI ticks: TxDQ = 910
N2.C1.D0.R0.S17: TxDqs: plus1 = 1, minus1 = 0, PI = 51, DB = 1
N4.C0.D0.R0.S12: TxDq : plus1 = 1, minus1 = 0, PI = 39, DB = 0
START_DATA_TX_DQ
N0.C0.D1.R1.S09: Total Delay in PI ticks: TxDQ = 984
N2.C1.D0.R0.S17: TxDq : plus1 = 1, minus1 = 0, PI = 19, DB = 0
N4.C0.D0.R0.S13: TxDqs: plus1 = 1, minus1 = 0, PI = 41, DB = 0
N6.C0.S00: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 009, RdPtrOffsetTxDqs = 009
N0.C0.D1.R1.S10: Total Delay in PI ticks: TxDQ = 969
N2.C1.D0.R1.S00: TxDqs: plus1 = 1, minus1 = 0, PI = 46, DB = 0
N4.C0.D0.R0.S13: TxDq : plus1 = 1, minus1 = 0, PI = 07, DB = 1
N6.C0.S00: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 009, RdPtrOffsetTxDqs = 009
N0.C0.D1.R1.S11: Total Delay in PI ticks: TxDQ = 954
N2.C1.D0.R1.S00: TxDq : plus1 = 1, minus1 = 0, PI = 16, DB = 0
N4.C0.D0.R0.S14: TxDqs: plus1 = 1, minus1 = 0, PI = 54, DB = 1
N6.C0.S01: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 009
N0.C0.D1.R1.S12: Total Delay in PI ticks: TxDQ = 942
N2.C1.D0.R1.S01: TxDqs: plus1 = 1, minus1 = 0, PI = 28, DB = 0
N4.C0.D0.R0.S14: TxDq : plus1 = 1, minus1 = 0, PI = 21, DB = 0
N6.C0.S01: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 009
N0.C0.D1.R1.S13: Total Delay in PI ticks: TxDQ = 907
N2.C1.D0.R1.S01: TxDq : plus1 = 1, minus1 = 0, PI = 60, DB = 1
N4.C0.D0.R0.S15: TxDqs: plus1 = 1, minus1 = 0, PI = 58, DB = 1
N6.C0.S02: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 009
N0.C0.D1.R1.S14: Total Delay in PI ticks: TxDQ = 924
N2.C1.D0.R1.S02: TxDqs: plus1 = 1, minus1 = 0, PI = 23, DB = 0
N4.C0.D0.R0.S15: TxDq : plus1 = 1, minus1 = 0, PI = 25, DB = 0
N6.C0.S02: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 009
N0.C0.D1.R1.S15: Total Delay in PI ticks: TxDQ = 926
N2.C1.D0.R1.S02: TxDq : plus1 = 1, minus1 = 0, PI = 55, DB = 1
N4.C0.D0.R0.S16: TxDqs: plus1 = 1, minus1 = 0, PI = 10, DB = 1
N6.C0.S03: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 009
N0.C0.D1.R1.S16: Total Delay in PI ticks: TxDQ = 941
N2.C1.D0.R1.S03: TxDqs: plus1 = 1, minus1 = 0, PI = 05, DB = 1
N4.C0.D0.R0.S16: TxDq : plus1 = 1, minus1 = 0, PI = 42, DB = 0
N6.C0.S03: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 009
N0.C0.D1.R1.S17: Total Delay in PI ticks: TxDQ = 910
N2.C1.D0.R1.S03: TxDq : plus1 = 1, minus1 = 0, PI = 38, DB = 0
N4.C0.D0.R0.S17: TxDqs: plus1 = 1, minus1 = 0, PI = 49, DB = 1
N6.C0.S04: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 008
N0.C0: Calculating Optimimum DQ/DQS Values
N2.C1.D0.R1.S04: TxDqs: plus1 = 1, minus1 = 0, PI = 37, DB = 0
N4.C0.D0.R0.S17: TxDq : plus1 = 1, minus1 = 0, PI = 15, DB = 1
N6.C0.S04: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 008
START_DATA_TX_DQ
N2.C1.D0.R1.S04: TxDq : plus1 = 1, minus1 = 0, PI = 05, DB = 1
N4.C0.D0.R1.S00: TxDqs: plus1 = 1, minus1 = 0, PI = 55, DB = 1
N6.C0.S05: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 008
N0.C0.S00: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 009, RdPtrOffsetTxDqs = 009
N2.C1.D0.R1.S05: TxDqs: plus1 = 1, minus1 = 0, PI = 51, DB = 1
N4.C0.D0.R1.S00: TxDq : plus1 = 1, minus1 = 0, PI = 22, DB = 0
N6.C0.S05: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 008
N0.C0.S00: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 009, RdPtrOffsetTxDqs = 009
N2.C1.D0.R1.S05: TxDq : plus1 = 1, minus1 = 0, PI = 17, DB = 0
N4.C0.D0.R1.S01: TxDqs: plus1 = 1, minus1 = 0, PI = 36, DB = 0
N6.C0.S06: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 008
N0.C0.S01: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 009, RdPtrOffsetTxDqs = 009
N2.C1.D0.R1.S06: TxDqs: plus1 = 1, minus1 = 0, PI = 63, DB = 1
N4.C0.D0.R1.S01: TxDq : plus1 = 1, minus1 = 0, PI = 03, DB = 1
N6.C0.S06: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 008
N0.C0.S01: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 009, RdPtrOffsetTxDqs = 009
N2.C1.D0.R1.S06: TxDq : plus1 = 1, minus1 = 0, PI = 32, DB = 0
N4.C0.D0.R1.S02: TxDqs: plus1 = 1, minus1 = 0, PI = 25, DB = 0
N6.C0.S07: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 009
N0.C0.S02: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 009
N2.C1.D0.R1.S07: TxDqs: plus1 = 1, minus1 = 0, PI = 16, DB = 0
N4.C0.D0.R1.S02: TxDq : plus1 = 1, minus1 = 0, PI = 54, DB = 1
N6.C0.S07: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 009
N0.C0.S02: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 009
N2.C1.D0.R1.S07: TxDq : plus1 = 1, minus1 = 0, PI = 46, DB = 0
N4.C0.D0.R1.S03: TxDqs: plus1 = 1, minus1 = 0, PI = 07, DB = 1
N6.C0.S08: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 008
N0.C0.S03: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 009
N2.C1.D0.R1.S08: TxDqs: plus1 = 1, minus1 = 0, PI = 51, DB = 1
N4.C0.D0.R1.S03: TxDq : plus1 = 1, minus1 = 0, PI = 37, DB = 0
N6.C0.S08: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 008
N0.C0.S03: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 009
N2.C1.D0.R1.S08: TxDq : plus1 = 1, minus1 = 0, PI = 18, DB = 0
N4.C0.D0.R1.S04: TxDqs: plus1 = 1, minus1 = 0, PI = 39, DB = 0
N6.C0.D0.R0.S00: TxDqs: plus1 = 1, minus1 = 0, PI = 51, DB = 1
N0.C0.S04: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 008
N2.C1.D0.R1.S09: TxDqs: plus1 = 1, minus1 = 0, PI = 45, DB = 0
N4.C0.D0.R1.S04: TxDq : plus1 = 1, minus1 = 0, PI = 06, DB = 1
N6.C0.D0.R0.S00: TxDq : plus1 = 1, minus1 = 0, PI = 22, DB = 0
N0.C0.S04: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 008
N2.C1.D0.R1.S09: TxDq : plus1 = 1, minus1 = 0, PI = 15, DB = 1
N4.C0.D0.R1.S05: TxDqs: plus1 = 1, minus1 = 0, PI = 57, DB = 1
N6.C0.D0.R0.S01: TxDqs: plus1 = 1, minus1 = 0, PI = 30, DB = 0
N0.C0.S05: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 008
N2.C1.D0.R1.S10: TxDqs: plus1 = 1, minus1 = 0, PI = 28, DB = 0
N4.C0.D0.R1.S05: TxDq : plus1 = 1, minus1 = 0, PI = 22, DB = 0
N6.C0.D0.R0.S01: TxDq : plus1 = 1, minus1 = 0, PI = 62, DB = 1
N0.C0.S05: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 008
N2.C1.D0.R1.S10: TxDq : plus1 = 1, minus1 = 0, PI = 61, DB = 1
N4.C0.D0.R1.S06: TxDqs: plus1 = 1, minus1 = 0, PI = 57, DB = 1
N6.C0.D0.R0.S02: TxDqs: plus1 = 1, minus1 = 0, PI = 20, DB = 0
N0.C0.S06: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 008
N2.C1.D0.R1.S11: TxDqs: plus1 = 1, minus1 = 0, PI = 22, DB = 0
N4.C0.D0.R1.S06: TxDq : plus1 = 1, minus1 = 0, PI = 23, DB = 0
N6.C0.D0.R0.S02: TxDq : plus1 = 1, minus1 = 0, PI = 51, DB = 1
N0.C0.S06: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 008
N2.C1.D0.R1.S11: TxDq : plus1 = 1, minus1 = 0, PI = 57, DB = 1
N4.C0.D0.R1.S07: TxDqs: plus1 = 1, minus1 = 0, PI = 10, DB = 1
N6.C0.D0.R0.S03: TxDqs: plus1 = 1, minus1 = 0, PI = 03, DB = 1
N0.C0.S07: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 009
N2.C1.D0.R1.S12: TxDqs: plus1 = 1, minus1 = 0, PI = 05, DB = 1
N4.C0.D0.R1.S07: TxDq : plus1 = 1, minus1 = 0, PI = 41, DB = 0
N6.C0.D0.R0.S03: TxDq : plus1 = 1, minus1 = 0, PI = 34, DB = 0
N0.C0.S07: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 009
N2.C1.D0.R1.S12: TxDq : plus1 = 1, minus1 = 0, PI = 38, DB = 0
N4.C0.D0.R1.S08: TxDqs: plus1 = 1, minus1 = 0, PI = 51, DB = 1
N6.C0.D0.R0.S04: TxDqs: plus1 = 1, minus1 = 0, PI = 33, DB = 0
N0.C0.S08: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 008
N2.C1.D0.R1.S13: TxDqs: plus1 = 1, minus1 = 0, PI = 36, DB = 0
N4.C0.D0.R1.S08: TxDq : plus1 = 1, minus1 = 0, PI = 17, DB = 0
N6.C0.D0.R0.S04: TxDq : plus1 = 1, minus1 = 0, PI = 02, DB = 1
N0.C0.S08: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 008
N2.C1.D0.R1.S13: TxDq : plus1 = 1, minus1 = 0, PI = 06, DB = 1
N4.C0.D0.R1.S09: TxDqs: plus1 = 1, minus1 = 0, PI = 53, DB = 1
N6.C0.D0.R0.S05: TxDqs: plus1 = 1, minus1 = 0, PI = 53, DB = 1
N0.C0.D0.R0.S00: TxDqs: plus1 = 1, minus1 = 0, PI = 52, DB = 1
N2.C1.D0.R1.S14: TxDqs: plus1 = 1, minus1 = 0, PI = 51, DB = 1
N4.C0.D0.R1.S09: TxDq : plus1 = 1, minus1 = 0, PI = 21, DB = 0
N6.C0.D0.R0.S05: TxDq : plus1 = 1, minus1 = 0, PI = 20, DB = 0
N0.C0.D0.R0.S00: TxDq : plus1 = 1, minus1 = 0, PI = 20, DB = 0
N2.C1.D0.R1.S14: TxDq : plus1 = 1, minus1 = 0, PI = 18, DB = 0
N4.C0.D0.R1.S10: TxDqs: plus1 = 1, minus1 = 0, PI = 35, DB = 0
N6.C0.D0.R0.S06: TxDqs: plus1 = 1, minus1 = 0, PI = 56, DB = 1
N0.C0.D0.R0.S01: TxDqs: plus1 = 1, minus1 = 0, PI = 34, DB = 0
N2.C1.D0.R1.S15: TxDqs: plus1 = 1, minus1 = 0, PI = 63, DB = 1
N4.C0.D0.R1.S10: TxDq : plus1 = 1, minus1 = 0, PI = 01, DB = 1
N6.C0.D0.R0.S06: TxDq : plus1 = 1, minus1 = 0, PI = 26, DB = 0
N0.C0.D0.R0.S01: TxDq : plus1 = 1, minus1 = 0, PI = 02, DB = 1
N2.C1.D0.R1.S15: TxDq : plus1 = 1, minus1 = 0, PI = 33, DB = 0
N4.C0.D0.R1.S11: TxDqs: plus1 = 1, minus1 = 0, PI = 24, DB = 0
N6.C0.D0.R0.S07: TxDqs: plus1 = 1, minus1 = 0, PI = 09, DB = 1
N0.C0.D0.R0.S02: TxDqs: plus1 = 1, minus1 = 0, PI = 23, DB = 0
N2.C1.D0.R1.S16: TxDqs: plus1 = 1, minus1 = 0, PI = 18, DB = 0
N4.C0.D0.R1.S11: TxDq : plus1 = 1, minus1 = 0, PI = 54, DB = 1
N6.C0.D0.R0.S07: TxDq : plus1 = 1, minus1 = 0, PI = 40, DB = 0
N0.C0.D0.R0.S02: TxDq : plus1 = 1, minus1 = 0, PI = 54, DB = 1
N2.C1.D0.R1.S16: TxDq : plus1 = 1, minus1 = 0, PI = 49, DB = 1
N4.C0.D0.R1.S12: TxDqs: plus1 = 1, minus1 = 0, PI = 08, DB = 1
N6.C0.D0.R0.S08: TxDqs: plus1 = 1, minus1 = 0, PI = 46, DB = 0
N0.C0.D0.R0.S03: TxDqs: plus1 = 1, minus1 = 0, PI = 06, DB = 1
N2.C1.D0.R1.S17: TxDqs: plus1 = 1, minus1 = 0, PI = 51, DB = 1
N4.C0.D0.R1.S12: TxDq : plus1 = 1, minus1 = 0, PI = 39, DB = 0
N6.C0.D0.R0.S08: TxDq : plus1 = 1, minus1 = 0, PI = 15, DB = 1
N0.C0.D0.R0.S03: TxDq : plus1 = 1, minus1 = 0, PI = 37, DB = 0
N2.C1.D0.R1.S17: TxDq : plus1 = 1, minus1 = 0, PI = 19, DB = 0
N4.C0.D0.R1.S13: TxDqs: plus1 = 1, minus1 = 0, PI = 41, DB = 0
N6.C0.D0.R0.S09: TxDqs: plus1 = 1, minus1 = 0, PI = 51, DB = 1
N0.C0.D0.R0.S04: TxDqs: plus1 = 1, minus1 = 0, PI = 38, DB = 0
N2.C1.D1.R0.S00: TxDqs: plus1 = 1, minus1 = 0, PI = 52, DB = 1
N4.C0.D0.R1.S13: TxDq : plus1 = 1, minus1 = 0, PI = 07, DB = 1
N6.C0.D0.R0.S09: TxDq : plus1 = 1, minus1 = 0, PI = 18, DB = 0
N0.C0.D0.R0.S04: TxDq : plus1 = 1, minus1 = 0, PI = 06, DB = 1
N2.C1.D1.R0.S00: TxDq : plus1 = 1, minus1 = 0, PI = 21, DB = 0
N4.C0.D0.R1.S14: TxDqs: plus1 = 1, minus1 = 0, PI = 54, DB = 1
N6.C0.D0.R0.S10: TxDqs: plus1 = 1, minus1 = 0, PI = 31, DB = 0
N0.C0.D0.R0.S05: TxDqs: plus1 = 1, minus1 = 0, PI = 54, DB = 1
N2.C1.D1.R0.S01: TxDqs: plus1 = 1, minus1 = 0, PI = 36, DB = 0
N4.C0.D0.R1.S14: TxDq : plus1 = 1, minus1 = 0, PI = 21, DB = 0
N6.C0.D0.R0.S10: TxDq : plus1 = 1, minus1 = 0, PI = 62, DB = 1
N0.C0.D0.R0.S05: TxDq : plus1 = 1, minus1 = 0, PI = 20, DB = 0
N2.C1.D1.R0.S01: TxDq : plus1 = 0, minus1 = 1, PI = 03, DB = 1
N4.C0.D0.R1.S15: TxDqs: plus1 = 1, minus1 = 0, PI = 58, DB = 1
N6.C0.D0.R0.S11: TxDqs: plus1 = 1, minus1 = 0, PI = 19, DB = 0
N0.C0.D0.R0.S06: TxDqs: plus1 = 1, minus1 = 0, PI = 57, DB = 1
N2.C1.D1.R0.S02: TxDqs: plus1 = 1, minus1 = 0, PI = 29, DB = 0
N4.C0.D0.R1.S15: TxDq : plus1 = 1, minus1 = 0, PI = 25, DB = 0
N6.C0.D0.R0.S11: TxDq : plus1 = 1, minus1 = 0, PI = 52, DB = 1
N0.C0.D0.R0.S06: TxDq : plus1 = 1, minus1 = 0, PI = 24, DB = 0
N2.C1.D1.R0.S02: TxDq : plus1 = 1, minus1 = 0, PI = 60, DB = 1
N4.C0.D0.R1.S16: TxDqs: plus1 = 1, minus1 = 0, PI = 10, DB = 1
N6.C0.D0.R0.S12: TxDqs: plus1 = 1, minus1 = 0, PI = 06, DB = 1
N0.C0.D0.R0.S07: TxDqs: plus1 = 1, minus1 = 0, PI = 10, DB = 1
N2.C1.D1.R0.S03: TxDqs: plus1 = 1, minus1 = 0, PI = 12, DB = 1
N4.C0.D0.R1.S16: TxDq : plus1 = 1, minus1 = 0, PI = 42, DB = 0
N6.C0.D0.R0.S12: TxDq : plus1 = 1, minus1 = 0, PI = 36, DB = 0
N0.C0.D0.R0.S07: TxDq : plus1 = 1, minus1 = 0, PI = 40, DB = 0
N2.C1.D1.R0.S03: TxDq : plus1 = 1, minus1 = 0, PI = 44, DB = 0
N4.C0.D0.R1.S17: TxDqs: plus1 = 1, minus1 = 0, PI = 49, DB = 1
N6.C0.D0.R0.S13: TxDqs: plus1 = 1, minus1 = 0, PI = 34, DB = 0
N0.C0.D0.R0.S08: TxDqs: plus1 = 1, minus1 = 0, PI = 47, DB = 0
N2.C1.D1.R0.S04: TxDqs: plus1 = 1, minus1 = 0, PI = 44, DB = 0
N4.C0.D0.R1.S17: TxDq : plus1 = 1, minus1 = 0, PI = 15, DB = 1
N6.C0.D0.R0.S13: TxDq : plus1 = 1, minus1 = 0, PI = 03, DB = 1
N0.C0.D0.R0.S08: TxDq : plus1 = 1, minus1 = 0, PI = 15, DB = 1
N2.C1.D1.R0.S04: TxDq : plus1 = 1, minus1 = 0, PI = 12, DB = 1
N4.C0.D1.R0.S00: TxDqs: plus1 = 1, minus1 = 0, PI = 58, DB = 1
N6.C0.D0.R0.S14: TxDqs: plus1 = 1, minus1 = 0, PI = 52, DB = 1
N0.C0.D0.R0.S09: TxDqs: plus1 = 1, minus1 = 0, PI = 52, DB = 1
N2.C1.D1.R0.S05: TxDqs: plus1 = 1, minus1 = 0, PI = 59, DB = 1
N4.C0.D1.R0.S00: TxDq : plus1 = 1, minus1 = 0, PI = 24, DB = 0
N6.C0.D0.R0.S14: TxDq : plus1 = 1, minus1 = 0, PI = 20, DB = 0
N0.C0.D0.R0.S09: TxDq : plus1 = 1, minus1 = 0, PI = 20, DB = 0
N2.C1.D1.R0.S05: TxDq : plus1 = 1, minus1 = 0, PI = 25, DB = 0
N4.C0.D1.R0.S01: TxDqs: plus1 = 1, minus1 = 0, PI = 44, DB = 0
N6.C0.D0.R0.S15: TxDqs: plus1 = 1, minus1 = 0, PI = 55, DB = 1
N0.C0.D0.R0.S10: TxDqs: plus1 = 1, minus1 = 0, PI = 35, DB = 0
N2.C1.D1.R0.S06: TxDqs: plus1 = 0, minus1 = 1, PI = 07, DB = 1
N4.C0.D1.R0.S01: TxDq : plus1 = 1, minus1 = 0, PI = 08, DB = 1
N6.C0.D0.R0.S15: TxDq : plus1 = 1, minus1 = 0, PI = 22, DB = 0
N0.C0.D0.R0.S10: TxDq : plus1 = 1, minus1 = 0, PI = 02, DB = 1
N2.C1.D1.R0.S06: TxDq : plus1 = 1, minus1 = 0, PI = 39, DB = 0
N4.C0.D1.R0.S02: TxDqs: plus1 = 1, minus1 = 0, PI = 31, DB = 0
N6.C0.D0.R0.S16: TxDqs: plus1 = 1, minus1 = 0, PI = 08, DB = 1
N0.C0.D0.R0.S11: TxDqs: plus1 = 1, minus1 = 0, PI = 24, DB = 0
N2.C1.D1.R0.S07: TxDqs: plus1 = 1, minus1 = 0, PI = 25, DB = 0
N4.C0.D1.R0.S02: TxDq : plus1 = 1, minus1 = 0, PI = 59, DB = 1
N6.C0.D0.R0.S16: TxDq : plus1 = 1, minus1 = 0, PI = 39, DB = 0
N0.C0.D0.R0.S11: TxDq : plus1 = 1, minus1 = 0, PI = 54, DB = 1
N2.C1.D1.R0.S07: TxDq : plus1 = 1, minus1 = 0, PI = 55, DB = 1
N4.C0.D1.R0.S03: TxDqs: plus1 = 1, minus1 = 0, PI = 15, DB = 1
N6.C0.D0.R0.S17: TxDqs: plus1 = 1, minus1 = 0, PI = 47, DB = 0
N0.C0.D0.R0.S12: TxDqs: plus1 = 1, minus1 = 0, PI = 09, DB = 1
N2.C1.D1.R0.S08: TxDqs: plus1 = 1, minus1 = 0, PI = 56, DB = 1
N4.C0.D1.R0.S03: TxDq : plus1 = 1, minus1 = 0, PI = 42, DB = 0
N6.C0.D0.R0.S17: TxDq : plus1 = 1, minus1 = 0, PI = 15, DB = 1
N0.C0.D0.R0.S12: TxDq : plus1 = 1, minus1 = 0, PI = 39, DB = 0
N2.C1.D1.R0.S08: TxDq : plus1 = 1, minus1 = 0, PI = 23, DB = 0
N4.C0.D1.R0.S04: TxDqs: plus1 = 1, minus1 = 0, PI = 44, DB = 0
N6.C0.D0.R1.S00: TxDqs: plus1 = 1, minus1 = 0, PI = 51, DB = 1
N0.C0.D0.R0.S13: TxDqs: plus1 = 1, minus1 = 0, PI = 38, DB = 0
N2.C1.D1.R0.S09: TxDqs: plus1 = 1, minus1 = 0, PI = 52, DB = 1
N4.C0.D1.R0.S04: TxDq : plus1 = 1, minus1 = 0, PI = 09, DB = 1
N6.C0.D0.R1.S00: TxDq : plus1 = 1, minus1 = 0, PI = 22, DB = 0
N0.C0.D0.R0.S13: TxDq : plus1 = 1, minus1 = 0, PI = 07, DB = 1
N2.C1.D1.R0.S09: TxDq : plus1 = 1, minus1 = 0, PI = 20, DB = 0
N4.C0.D1.R0.S05: TxDqs: plus1 = 1, minus1 = 0, PI = 63, DB = 1
N6.C0.D0.R1.S01: TxDqs: plus1 = 1, minus1 = 0, PI = 30, DB = 0
N0.C0.D0.R0.S14: TxDqs: plus1 = 1, minus1 = 0, PI = 55, DB = 1
N2.C1.D1.R0.S10: TxDqs: plus1 = 1, minus1 = 0, PI = 36, DB = 0
N4.C0.D1.R0.S05: TxDq : plus1 = 1, minus1 = 0, PI = 28, DB = 0
N6.C0.D0.R1.S01: TxDq : plus1 = 1, minus1 = 0, PI = 62, DB = 1
N0.C0.D0.R0.S14: TxDq : plus1 = 1, minus1 = 0, PI = 22, DB = 0
N2.C1.D1.R0.S10: TxDq : plus1 = 0, minus1 = 1, PI = 03, DB = 1
N4.C0.D1.R0.S06: TxDqs: plus1 = 1, minus1 = 0, PI = 63, DB = 1
N6.C0.D0.R1.S02: TxDqs: plus1 = 1, minus1 = 0, PI = 20, DB = 0
N0.C0.D0.R0.S15: TxDqs: plus1 = 1, minus1 = 0, PI = 58, DB = 1
N2.C1.D1.R0.S11: TxDqs: plus1 = 1, minus1 = 0, PI = 29, DB = 0
N4.C0.D1.R0.S06: TxDq : plus1 = 1, minus1 = 0, PI = 28, DB = 0
N6.C0.D0.R1.S02: TxDq : plus1 = 1, minus1 = 0, PI = 51, DB = 1
N0.C0.D0.R0.S15: TxDq : plus1 = 1, minus1 = 0, PI = 24, DB = 0
N2.C1.D1.R0.S11: TxDq : plus1 = 1, minus1 = 0, PI = 62, DB = 1
N4.C0.D1.R0.S07: TxDqs: plus1 = 1, minus1 = 0, PI = 16, DB = 0
N6.C0.D0.R1.S03: TxDqs: plus1 = 1, minus1 = 0, PI = 03, DB = 1
N0.C0.D0.R0.S16: TxDqs: plus1 = 1, minus1 = 0, PI = 11, DB = 1
N2.C1.D1.R0.S12: TxDqs: plus1 = 1, minus1 = 0, PI = 15, DB = 1
N4.C0.D1.R0.S07: TxDq : plus1 = 1, minus1 = 0, PI = 45, DB = 0
N6.C0.D0.R1.S03: TxDq : plus1 = 1, minus1 = 0, PI = 34, DB = 0
N0.C0.D0.R0.S16: TxDq : plus1 = 1, minus1 = 0, PI = 42, DB = 0
N2.C1.D1.R0.S12: TxDq : plus1 = 1, minus1 = 0, PI = 46, DB = 0
N4.C0.D1.R0.S08: TxDqs: plus1 = 1, minus1 = 0, PI = 51, DB = 1
N6.C0.D0.R1.S04: TxDqs: plus1 = 1, minus1 = 0, PI = 33, DB = 0
N0.C0.D0.R0.S17: TxDqs: plus1 = 1, minus1 = 0, PI = 46, DB = 0
N2.C1.D1.R0.S13: TxDqs: plus1 = 1, minus1 = 0, PI = 43, DB = 0
N4.C0.D1.R0.S08: TxDq : plus1 = 1, minus1 = 0, PI = 17, DB = 0
N6.C0.D0.R1.S04: TxDq : plus1 = 1, minus1 = 0, PI = 02, DB = 1
N0.C0.D0.R0.S17: TxDq : plus1 = 1, minus1 = 0, PI = 12, DB = 1
N2.C1.D1.R0.S13: TxDq : plus1 = 1, minus1 = 0, PI = 11, DB = 1
N4.C0.D1.R0.S09: TxDqs: plus1 = 1, minus1 = 0, PI = 57, DB = 1
N6.C0.D0.R1.S05: TxDqs: plus1 = 1, minus1 = 0, PI = 53, DB = 1
N0.C0.D0.R1.S00: TxDqs: plus1 = 1, minus1 = 0, PI = 52, DB = 1
N2.C1.D1.R0.S14: TxDqs: plus1 = 1, minus1 = 0, PI = 58, DB = 1
N4.C0.D1.R0.S09: TxDq : plus1 = 1, minus1 = 0, PI = 24, DB = 0
N6.C0.D0.R1.S05: TxDq : plus1 = 1, minus1 = 0, PI = 20, DB = 0
N0.C0.D0.R1.S00: TxDq : plus1 = 1, minus1 = 0, PI = 20, DB = 0
N2.C1.D1.R0.S14: TxDq : plus1 = 1, minus1 = 0, PI = 26, DB = 0
N4.C0.D1.R0.S10: TxDqs: plus1 = 1, minus1 = 0, PI = 44, DB = 0
N6.C0.D0.R1.S06: TxDqs: plus1 = 1, minus1 = 0, PI = 56, DB = 1
N0.C0.D0.R1.S01: TxDqs: plus1 = 1, minus1 = 0, PI = 34, DB = 0
N2.C1.D1.R0.S15: TxDqs: plus1 = 0, minus1 = 1, PI = 06, DB = 1
N4.C0.D1.R0.S10: TxDq : plus1 = 1, minus1 = 0, PI = 09, DB = 1
N6.C0.D0.R1.S06: TxDq : plus1 = 1, minus1 = 0, PI = 26, DB = 0
N0.C0.D0.R1.S01: TxDq : plus1 = 1, minus1 = 0, PI = 02, DB = 1
N2.C1.D1.R0.S15: TxDq : plus1 = 1, minus1 = 0, PI = 39, DB = 0
N4.C0.D1.R0.S11: TxDqs: plus1 = 1, minus1 = 0, PI = 31, DB = 0
N6.C0.D0.R1.S07: TxDqs: plus1 = 1, minus1 = 0, PI = 09, DB = 1
N0.C0.D0.R1.S02: TxDqs: plus1 = 1, minus1 = 0, PI = 23, DB = 0
N2.C1.D1.R0.S16: TxDqs: plus1 = 1, minus1 = 0, PI = 25, DB = 0
N4.C0.D1.R0.S11: TxDq : plus1 = 1, minus1 = 0, PI = 57, DB = 1
N6.C0.D0.R1.S07: TxDq : plus1 = 1, minus1 = 0, PI = 40, DB = 0
N0.C0.D0.R1.S02: TxDq : plus1 = 1, minus1 = 0, PI = 54, DB = 1
N2.C1.D1.R0.S16: TxDq : plus1 = 1, minus1 = 0, PI = 56, DB = 1
N4.C0.D1.R0.S12: TxDqs: plus1 = 1, minus1 = 0, PI = 16, DB = 0
N6.C0.D0.R1.S08: TxDqs: plus1 = 1, minus1 = 0, PI = 46, DB = 0
N0.C0.D0.R1.S03: TxDqs: plus1 = 1, minus1 = 0, PI = 06, DB = 1
N2.C1.D1.R0.S17: TxDqs: plus1 = 1, minus1 = 0, PI = 55, DB = 1
N4.C0.D1.R0.S12: TxDq : plus1 = 1, minus1 = 0, PI = 45, DB = 0
N6.C0.D0.R1.S08: TxDq : plus1 = 1, minus1 = 0, PI = 15, DB = 1
N0.C0.D0.R1.S03: TxDq : plus1 = 1, minus1 = 0, PI = 37, DB = 0
N2.C1.D1.R0.S17: TxDq : plus1 = 1, minus1 = 0, PI = 23, DB = 0
N4.C0.D1.R0.S13: TxDqs: plus1 = 1, minus1 = 0, PI = 46, DB = 0
N6.C0.D0.R1.S09: TxDqs: plus1 = 1, minus1 = 0, PI = 51, DB = 1
N0.C0.D0.R1.S04: TxDqs: plus1 = 1, minus1 = 0, PI = 38, DB = 0
N2.C1.D1.R1.S00: TxDqs: plus1 = 1, minus1 = 0, PI = 52, DB = 1
N4.C0.D1.R0.S13: TxDq : plus1 = 1, minus1 = 0, PI = 10, DB = 1
N6.C0.D0.R1.S09: TxDq : plus1 = 1, minus1 = 0, PI = 18, DB = 0
N0.C0.D0.R1.S04: TxDq : plus1 = 1, minus1 = 0, PI = 06, DB = 1
N2.C1.D1.R1.S00: TxDq : plus1 = 1, minus1 = 0, PI = 21, DB = 0
N4.C0.D1.R0.S14: TxDqs: plus1 = 1, minus1 = 0, PI = 62, DB = 1
N6.C0.D0.R1.S10: TxDqs: plus1 = 1, minus1 = 0, PI = 31, DB = 0
N0.C0.D0.R1.S05: TxDqs: plus1 = 1, minus1 = 0, PI = 54, DB = 1
N2.C1.D1.R1.S01: TxDqs: plus1 = 1, minus1 = 0, PI = 36, DB = 0
N4.C0.D1.R0.S14: TxDq : plus1 = 1, minus1 = 0, PI = 29, DB = 0
N6.C0.D0.R1.S10: TxDq : plus1 = 1, minus1 = 0, PI = 62, DB = 1
N0.C0.D0.R1.S05: TxDq : plus1 = 1, minus1 = 0, PI = 20, DB = 0
N2.C1.D1.R1.S01: TxDq : plus1 = 0, minus1 = 1, PI = 03, DB = 1
N4.C0.D1.R0.S15: TxDqs: plus1 = 1, minus1 = 0, PI = 63, DB = 1
N6.C0.D0.R1.S11: TxDqs: plus1 = 1, minus1 = 0, PI = 19, DB = 0
N0.C0.D0.R1.S06: TxDqs: plus1 = 1, minus1 = 0, PI = 57, DB = 1
N2.C1.D1.R1.S02: TxDqs: plus1 = 1, minus1 = 0, PI = 29, DB = 0
N4.C0.D1.R0.S15: TxDq : plus1 = 1, minus1 = 0, PI = 30, DB = 0
N6.C0.D0.R1.S11: TxDq : plus1 = 1, minus1 = 0, PI = 52, DB = 1
N0.C0.D0.R1.S06: TxDq : plus1 = 1, minus1 = 0, PI = 24, DB = 0
N2.C1.D1.R1.S02: TxDq : plus1 = 1, minus1 = 0, PI = 60, DB = 1
N4.C0.D1.R0.S16: TxDqs: plus1 = 1, minus1 = 0, PI = 16, DB = 0
N6.C0.D0.R1.S12: TxDqs: plus1 = 1, minus1 = 0, PI = 06, DB = 1
N0.C0.D0.R1.S07: TxDqs: plus1 = 1, minus1 = 0, PI = 10, DB = 1
N2.C1.D1.R1.S03: TxDqs: plus1 = 1, minus1 = 0, PI = 12, DB = 1
N4.C0.D1.R0.S16: TxDq : plus1 = 1, minus1 = 0, PI = 46, DB = 0
N6.C0.D0.R1.S12: TxDq : plus1 = 1, minus1 = 0, PI = 36, DB = 0
N0.C0.D0.R1.S07: TxDq : plus1 = 1, minus1 = 0, PI = 40, DB = 0
N2.C1.D1.R1.S03: TxDq : plus1 = 1, minus1 = 0, PI = 44, DB = 0
N4.C0.D1.R0.S17: TxDqs: plus1 = 1, minus1 = 0, PI = 51, DB = 1
N6.C0.D0.R1.S13: TxDqs: plus1 = 1, minus1 = 0, PI = 34, DB = 0
N0.C0.D0.R1.S08: TxDqs: plus1 = 1, minus1 = 0, PI = 47, DB = 0
N2.C1.D1.R1.S04: TxDqs: plus1 = 1, minus1 = 0, PI = 44, DB = 0
N4.C0.D1.R0.S17: TxDq : plus1 = 1, minus1 = 0, PI = 15, DB = 1
N6.C0.D0.R1.S13: TxDq : plus1 = 1, minus1 = 0, PI = 03, DB = 1
N0.C0.D0.R1.S08: TxDq : plus1 = 1, minus1 = 0, PI = 15, DB = 1
N2.C1.D1.R1.S04: TxDq : plus1 = 1, minus1 = 0, PI = 12, DB = 1
N4.C0.D1.R1.S00: TxDqs: plus1 = 1, minus1 = 0, PI = 58, DB = 1
N6.C0.D0.R1.S14: TxDqs: plus1 = 1, minus1 = 0, PI = 52, DB = 1
N0.C0.D0.R1.S09: TxDqs: plus1 = 1, minus1 = 0, PI = 52, DB = 1
N2.C1.D1.R1.S05: TxDqs: plus1 = 1, minus1 = 0, PI = 59, DB = 1
N4.C0.D1.R1.S00: TxDq : plus1 = 1, minus1 = 0, PI = 24, DB = 0
N6.C0.D0.R1.S14: TxDq : plus1 = 1, minus1 = 0, PI = 20, DB = 0
N0.C0.D0.R1.S09: TxDq : plus1 = 1, minus1 = 0, PI = 20, DB = 0
N2.C1.D1.R1.S05: TxDq : plus1 = 1, minus1 = 0, PI = 25, DB = 0
N4.C0.D1.R1.S01: TxDqs: plus1 = 1, minus1 = 0, PI = 44, DB = 0
N6.C0.D0.R1.S15: TxDqs: plus1 = 1, minus1 = 0, PI = 55, DB = 1
N0.C0.D0.R1.S10: TxDqs: plus1 = 1, minus1 = 0, PI = 35, DB = 0
N2.C1.D1.R1.S06: TxDqs: plus1 = 0, minus1 = 1, PI = 07, DB = 1
N4.C0.D1.R1.S01: TxDq : plus1 = 1, minus1 = 0, PI = 08, DB = 1
N6.C0.D0.R1.S15: TxDq : plus1 = 1, minus1 = 0, PI = 22, DB = 0
N0.C0.D0.R1.S10: TxDq : plus1 = 1, minus1 = 0, PI = 02, DB = 1
N2.C1.D1.R1.S06: TxDq : plus1 = 1, minus1 = 0, PI = 39, DB = 0
N4.C0.D1.R1.S02: TxDqs: plus1 = 1, minus1 = 0, PI = 31, DB = 0
N6.C0.D0.R1.S16: TxDqs: plus1 = 1, minus1 = 0, PI = 08, DB = 1
N0.C0.D0.R1.S11: TxDqs: plus1 = 1, minus1 = 0, PI = 24, DB = 0
N2.C1.D1.R1.S07: TxDqs: plus1 = 1, minus1 = 0, PI = 25, DB = 0
N4.C0.D1.R1.S02: TxDq : plus1 = 1, minus1 = 0, PI = 59, DB = 1
N6.C0.D0.R1.S16: TxDq : plus1 = 1, minus1 = 0, PI = 39, DB = 0
N0.C0.D0.R1.S11: TxDq : plus1 = 1, minus1 = 0, PI = 54, DB = 1
N2.C1.D1.R1.S07: TxDq : plus1 = 1, minus1 = 0, PI = 55, DB = 1
N4.C0.D1.R1.S03: TxDqs: plus1 = 1, minus1 = 0, PI = 15, DB = 1
N6.C0.D0.R1.S17: TxDqs: plus1 = 1, minus1 = 0, PI = 47, DB = 0
N0.C0.D0.R1.S12: TxDqs: plus1 = 1, minus1 = 0, PI = 09, DB = 1
N2.C1.D1.R1.S08: TxDqs: plus1 = 1, minus1 = 0, PI = 56, DB = 1
N4.C0.D1.R1.S03: TxDq : plus1 = 1, minus1 = 0, PI = 42, DB = 0
N6.C0.D0.R1.S17: TxDq : plus1 = 1, minus1 = 0, PI = 15, DB = 1
N0.C0.D0.R1.S12: TxDq : plus1 = 1, minus1 = 0, PI = 39, DB = 0
N2.C1.D1.R1.S08: TxDq : plus1 = 1, minus1 = 0, PI = 23, DB = 0
N4.C0.D1.R1.S04: TxDqs: plus1 = 1, minus1 = 0, PI = 44, DB = 0
N6.C0.D1.R0.S00: TxDqs: plus1 = 1, minus1 = 0, PI = 50, DB = 1
N0.C0.D0.R1.S13: TxDqs: plus1 = 1, minus1 = 0, PI = 38, DB = 0
N2.C1.D1.R1.S09: TxDqs: plus1 = 1, minus1 = 0, PI = 52, DB = 1
N4.C0.D1.R1.S04: TxDq : plus1 = 1, minus1 = 0, PI = 09, DB = 1
N6.C0.D1.R0.S00: TxDq : plus1 = 1, minus1 = 0, PI = 21, DB = 0
N0.C0.D0.R1.S13: TxDq : plus1 = 1, minus1 = 0, PI = 07, DB = 1
N2.C1.D1.R1.S09: TxDq : plus1 = 1, minus1 = 0, PI = 20, DB = 0
N4.C0.D1.R1.S05: TxDqs: plus1 = 1, minus1 = 0, PI = 63, DB = 1
N6.C0.D1.R0.S01: TxDqs: plus1 = 1, minus1 = 0, PI = 33, DB = 0
N0.C0.D0.R1.S14: TxDqs: plus1 = 1, minus1 = 0, PI = 55, DB = 1
N2.C1.D1.R1.S10: TxDqs: plus1 = 1, minus1 = 0, PI = 36, DB = 0
N4.C0.D1.R1.S05: TxDq : plus1 = 1, minus1 = 0, PI = 28, DB = 0
N6.C0.D1.R0.S01: TxDq : plus1 = 0, minus1 = 1, PI = 01, DB = 1
N0.C0.D0.R1.S14: TxDq : plus1 = 1, minus1 = 0, PI = 22, DB = 0
N2.C1.D1.R1.S10: TxDq : plus1 = 0, minus1 = 1, PI = 03, DB = 1
N4.C0.D1.R1.S06: TxDqs: plus1 = 1, minus1 = 0, PI = 63, DB = 1
N6.C0.D1.R0.S02: TxDqs: plus1 = 1, minus1 = 0, PI = 20, DB = 0
N0.C0.D0.R1.S15: TxDqs: plus1 = 1, minus1 = 0, PI = 58, DB = 1
N2.C1.D1.R1.S11: TxDqs: plus1 = 1, minus1 = 0, PI = 29, DB = 0
N4.C0.D1.R1.S06: TxDq : plus1 = 1, minus1 = 0, PI = 28, DB = 0
N6.C0.D1.R0.S02: TxDq : plus1 = 1, minus1 = 0, PI = 52, DB = 1
N0.C0.D0.R1.S15: TxDq : plus1 = 1, minus1 = 0, PI = 24, DB = 0
N2.C1.D1.R1.S11: TxDq : plus1 = 1, minus1 = 0, PI = 62, DB = 1
N4.C0.D1.R1.S07: TxDqs: plus1 = 1, minus1 = 0, PI = 16, DB = 0
N6.C0.D1.R0.S03: TxDqs: plus1 = 1, minus1 = 0, PI = 08, DB = 1
N0.C0.D0.R1.S16: TxDqs: plus1 = 1, minus1 = 0, PI = 11, DB = 1
N2.C1.D1.R1.S12: TxDqs: plus1 = 1, minus1 = 0, PI = 15, DB = 1
N4.C0.D1.R1.S07: TxDq : plus1 = 1, minus1 = 0, PI = 45, DB = 0
N6.C0.D1.R0.S03: TxDq : plus1 = 1, minus1 = 0, PI = 39, DB = 0
N0.C0.D0.R1.S16: TxDq : plus1 = 1, minus1 = 0, PI = 42, DB = 0
N2.C1.D1.R1.S12: TxDq : plus1 = 1, minus1 = 0, PI = 46, DB = 0
N4.C0.D1.R1.S08: TxDqs: plus1 = 1, minus1 = 0, PI = 51, DB = 1
N6.C0.D1.R0.S04: TxDqs: plus1 = 1, minus1 = 0, PI = 35, DB = 0
N0.C0.D0.R1.S17: TxDqs: plus1 = 1, minus1 = 0, PI = 46, DB = 0
N2.C1.D1.R1.S13: TxDqs: plus1 = 1, minus1 = 0, PI = 43, DB = 0
N4.C0.D1.R1.S08: TxDq : plus1 = 1, minus1 = 0, PI = 17, DB = 0
N6.C0.D1.R0.S04: TxDq : plus1 = 1, minus1 = 0, PI = 03, DB = 1
N0.C0.D0.R1.S17: TxDq : plus1 = 1, minus1 = 0, PI = 12, DB = 1
N2.C1.D1.R1.S13: TxDq : plus1 = 1, minus1 = 0, PI = 11, DB = 1
N4.C0.D1.R1.S09: TxDqs: plus1 = 1, minus1 = 0, PI = 57, DB = 1
N6.C0.D1.R0.S05: TxDqs: plus1 = 1, minus1 = 0, PI = 55, DB = 1
N0.C0.D1.R0.S00: TxDqs: plus1 = 1, minus1 = 0, PI = 59, DB = 1
N2.C1.D1.R1.S14: TxDqs: plus1 = 1, minus1 = 0, PI = 58, DB = 1
N4.C0.D1.R1.S09: TxDq : plus1 = 1, minus1 = 0, PI = 24, DB = 0
N6.C0.D1.R0.S05: TxDq : plus1 = 1, minus1 = 0, PI = 22, DB = 0
N0.C0.D1.R0.S00: TxDq : plus1 = 1, minus1 = 0, PI = 26, DB = 0
N2.C1.D1.R1.S14: TxDq : plus1 = 1, minus1 = 0, PI = 26, DB = 0
N4.C0.D1.R1.S10: TxDqs: plus1 = 1, minus1 = 0, PI = 44, DB = 0
N6.C0.D1.R0.S06: TxDqs: plus1 = 1, minus1 = 0, PI = 58, DB = 1
N0.C0.D1.R0.S01: TxDqs: plus1 = 1, minus1 = 0, PI = 42, DB = 0
N2.C1.D1.R1.S15: TxDqs: plus1 = 0, minus1 = 1, PI = 06, DB = 1
N4.C0.D1.R1.S10: TxDq : plus1 = 1, minus1 = 0, PI = 09, DB = 1
N6.C0.D1.R0.S06: TxDq : plus1 = 1, minus1 = 0, PI = 26, DB = 0
N0.C0.D1.R0.S01: TxDq : plus1 = 1, minus1 = 0, PI = 09, DB = 1
N2.C1.D1.R1.S15: TxDq : plus1 = 1, minus1 = 0, PI = 39, DB = 0
N4.C0.D1.R1.S11: TxDqs: plus1 = 1, minus1 = 0, PI = 31, DB = 0
N6.C0.D1.R0.S07: TxDqs: plus1 = 1, minus1 = 0, PI = 10, DB = 1
N0.C0.D1.R0.S02: TxDqs: plus1 = 1, minus1 = 0, PI = 31, DB = 0
N2.C1.D1.R1.S16: TxDqs: plus1 = 1, minus1 = 0, PI = 25, DB = 0
N4.C0.D1.R1.S11: TxDq : plus1 = 1, minus1 = 0, PI = 57, DB = 1
N6.C0.D1.R0.S07: TxDq : plus1 = 1, minus1 = 0, PI = 41, DB = 0
N0.C0.D1.R0.S02: TxDq : plus1 = 1, minus1 = 0, PI = 59, DB = 1
N2.C1.D1.R1.S16: TxDq : plus1 = 1, minus1 = 0, PI = 56, DB = 1
N4.C0.D1.R1.S12: TxDqs: plus1 = 1, minus1 = 0, PI = 16, DB = 0
N6.C0.D1.R0.S08: TxDqs: plus1 = 1, minus1 = 0, PI = 44, DB = 0
N0.C0.D1.R0.S03: TxDqs: plus1 = 1, minus1 = 0, PI = 14, DB = 1
N2.C1.D1.R1.S17: TxDqs: plus1 = 1, minus1 = 0, PI = 55, DB = 1
N4.C0.D1.R1.S12: TxDq : plus1 = 1, minus1 = 0, PI = 45, DB = 0
N6.C0.D1.R0.S08: TxDq : plus1 = 1, minus1 = 0, PI = 12, DB = 1
N0.C0.D1.R0.S03: TxDq : plus1 = 1, minus1 = 0, PI = 44, DB = 0
N2.C1.D1.R1.S17: TxDq : plus1 = 1, minus1 = 0, PI = 23, DB = 0
N4.C0.D1.R1.S13: TxDqs: plus1 = 1, minus1 = 0, PI = 46, DB = 0
N6.C0.D1.R0.S09: TxDqs: plus1 = 1, minus1 = 0, PI = 52, DB = 1
N0.C0.D1.R0.S04: TxDqs: plus1 = 1, minus1 = 0, PI = 45, DB = 0
END_DATA_TX_DQ
N4.C0.D1.R1.S13: TxDq : plus1 = 1, minus1 = 0, PI = 10, DB = 1
N6.C0.D1.R0.S09: TxDq : plus1 = 1, minus1 = 0, PI = 19, DB = 0
N0.C0.D1.R0.S04: TxDq : plus1 = 1, minus1 = 0, PI = 11, DB = 1
N2.C2.D0.R0.S00: wrcmd2dqsstartlatency: 04
N4.C0.D1.R1.S14: TxDqs: plus1 = 1, minus1 = 0, PI = 62, DB = 1
N6.C0.D1.R0.S10: TxDqs: plus1 = 1, minus1 = 0, PI = 35, DB = 0
N0.C0.D1.R0.S05: TxDqs: plus1 = 0, minus1 = 1, PI = 00, DB = 1
N2.C2.D0.R0.S00: RdPtrOffsetTxDq: 06
N4.C0.D1.R1.S14: TxDq : plus1 = 1, minus1 = 0, PI = 29, DB = 0
N6.C0.D1.R0.S10: TxDq : plus1 = 0, minus1 = 1, PI = 02, DB = 1
N0.C0.D1.R0.S05: TxDq : plus1 = 1, minus1 = 0, PI = 29, DB = 0
N2.C2.D0.R0.S00: RdPtrOffsetTxDqs: 07
N4.C0.D1.R1.S15: TxDqs: plus1 = 1, minus1 = 0, PI = 63, DB = 1
N6.C0.D1.R0.S11: TxDqs: plus1 = 1, minus1 = 0, PI = 22, DB = 0
N0.C0.D1.R0.S06: TxDqs: plus1 = 0, minus1 = 1, PI = 00, DB = 1
N2.C2.D0.R0.S00: PiTxDqs: 49
N4.C0.D1.R1.S15: TxDq : plus1 = 1, minus1 = 0, PI = 30, DB = 0
N6.C0.D1.R0.S11: TxDq : plus1 = 1, minus1 = 0, PI = 52, DB = 1
N0.C0.D1.R0.S06: TxDq : plus1 = 1, minus1 = 0, PI = 30, DB = 0
N2.C2.D0.R0.S01: wrcmd2dqsstartlatency: 04
N4.C0.D1.R1.S16: TxDqs: plus1 = 1, minus1 = 0, PI = 16, DB = 0
N6.C0.D1.R0.S12: TxDqs: plus1 = 1, minus1 = 0, PI = 08, DB = 1
N0.C0.D1.R0.S07: TxDqs: plus1 = 1, minus1 = 0, PI = 18, DB = 0
N2.C2.D0.R0.S01: RdPtrOffsetTxDq: 06
N4.C0.D1.R1.S16: TxDq : plus1 = 1, minus1 = 0, PI = 46, DB = 0
N6.C0.D1.R0.S12: TxDq : plus1 = 1, minus1 = 0, PI = 38, DB = 0
N0.C0.D1.R0.S07: TxDq : plus1 = 1, minus1 = 0, PI = 48, DB = 0
N2.C2.D0.R0.S01: RdPtrOffsetTxDqs: 07
N4.C0.D1.R1.S17: TxDqs: plus1 = 1, minus1 = 0, PI = 51, DB = 1
N6.C0.D1.R0.S13: TxDqs: plus1 = 1, minus1 = 0, PI = 36, DB = 0
N0.C0.D1.R0.S08: TxDqs: plus1 = 1, minus1 = 0, PI = 51, DB = 1
N2.C2.D0.R0.S01: PiTxDqs: 34
N4.C0.D1.R1.S17: TxDq : plus1 = 1, minus1 = 0, PI = 15, DB = 1
N6.C0.D1.R0.S13: TxDq : plus1 = 1, minus1 = 0, PI = 03, DB = 1
N0.C0.D1.R0.S08: TxDq : plus1 = 1, minus1 = 0, PI = 17, DB = 0
N2.C2.D0.R0.S02: wrcmd2dqsstartlatency: 04
END_DATA_TX_DQ
N6.C0.D1.R0.S14: TxDqs: plus1 = 1, minus1 = 0, PI = 55, DB = 1
N0.C0.D1.R0.S09: TxDqs: plus1 = 1, minus1 = 0, PI = 58, DB = 1
N2.C2.D0.R0.S02: RdPtrOffsetTxDq: 05
N4.C1.D0.R0.S00: wrcmd2dqsstartlatency: 04
N6.C0.D1.R0.S14: TxDq : plus1 = 1, minus1 = 0, PI = 22, DB = 0
N0.C0.D1.R0.S09: TxDq : plus1 = 1, minus1 = 0, PI = 24, DB = 0
N2.C2.D0.R0.S02: RdPtrOffsetTxDqs: 07
N4.C1.D0.R0.S00: RdPtrOffsetTxDq: 06
N6.C0.D1.R0.S15: TxDqs: plus1 = 1, minus1 = 0, PI = 58, DB = 1
N0.C0.D1.R0.S10: TxDqs: plus1 = 1, minus1 = 0, PI = 43, DB = 0
N2.C2.D0.R0.S02: PiTxDqs: 24
N4.C1.D0.R0.S00: RdPtrOffsetTxDqs: 07
N6.C0.D1.R0.S15: TxDq : plus1 = 1, minus1 = 0, PI = 25, DB = 0
N0.C0.D1.R0.S10: TxDq : plus1 = 1, minus1 = 0, PI = 09, DB = 1
N2.C2.D0.R0.S03: wrcmd2dqsstartlatency: 04
N4.C1.D0.R0.S00: PiTxDqs: 59
N6.C0.D1.R0.S16: TxDqs: plus1 = 1, minus1 = 0, PI = 10, DB = 1
N0.C0.D1.R0.S11: TxDqs: plus1 = 1, minus1 = 0, PI = 30, DB = 0
N2.C2.D0.R0.S03: RdPtrOffsetTxDq: 05
N4.C1.D0.R0.S01: wrcmd2dqsstartlatency: 04
N6.C0.D1.R0.S16: TxDq : plus1 = 1, minus1 = 0, PI = 41, DB = 0
N0.C0.D1.R0.S11: TxDq : plus1 = 1, minus1 = 0, PI = 59, DB = 1
N2.C2.D0.R0.S03: RdPtrOffsetTxDqs: 07
N4.C1.D0.R0.S01: RdPtrOffsetTxDq: 06
N6.C0.D1.R0.S17: TxDqs: plus1 = 1, minus1 = 0, PI = 45, DB = 0
N0.C0.D1.R0.S12: TxDqs: plus1 = 1, minus1 = 0, PI = 16, DB = 0
N2.C2.D0.R0.S03: PiTxDqs: 06
N4.C1.D0.R0.S01: RdPtrOffsetTxDqs: 07
N6.C0.D1.R0.S17: TxDq : plus1 = 1, minus1 = 0, PI = 11, DB = 1
N0.C0.D1.R0.S12: TxDq : plus1 = 1, minus1 = 0, PI = 47, DB = 0
N2.C2.D0.R0.S04: wrcmd2dqsstartlatency: 04
N4.C1.D0.R0.S01: PiTxDqs: 41
N6.C0.D1.R1.S00: TxDqs: plus1 = 1, minus1 = 0, PI = 50, DB = 1
N0.C0.D1.R0.S13: TxDqs: plus1 = 1, minus1 = 0, PI = 46, DB = 0
N2.C2.D0.R0.S04: RdPtrOffsetTxDq: 04
N4.C1.D0.R0.S02: wrcmd2dqsstartlatency: 04
N6.C0.D1.R1.S00: TxDq : plus1 = 1, minus1 = 0, PI = 21, DB = 0
N0.C0.D1.R0.S13: TxDq : plus1 = 1, minus1 = 0, PI = 12, DB = 1
N2.C2.D0.R0.S04: RdPtrOffsetTxDqs: 06
N4.C1.D0.R0.S02: RdPtrOffsetTxDq: 05
N6.C0.D1.R1.S01: TxDqs: plus1 = 1, minus1 = 0, PI = 33, DB = 0
N0.C0.D1.R0.S14: TxDqs: plus1 = 1, minus1 = 0, PI = 62, DB = 1
N2.C2.D0.R0.S04: PiTxDqs: 29
N4.C1.D0.R0.S02: RdPtrOffsetTxDqs: 07
N6.C0.D1.R1.S01: TxDq : plus1 = 0, minus1 = 1, PI = 01, DB = 1
N0.C0.D1.R0.S14: TxDq : plus1 = 1, minus1 = 0, PI = 28, DB = 0
N2.C2.D0.R0.S05: wrcmd2dqsstartlatency: 04
N4.C1.D0.R0.S02: PiTxDqs: 35
N6.C0.D1.R1.S02: TxDqs: plus1 = 1, minus1 = 0, PI = 20, DB = 0
N0.C0.D1.R0.S15: TxDqs: plus1 = 0, minus1 = 1, PI = 02, DB = 1
N2.C2.D0.R0.S05: RdPtrOffsetTxDq: 05
N4.C1.D0.R0.S03: wrcmd2dqsstartlatency: 04
N6.C0.D1.R1.S02: TxDq : plus1 = 1, minus1 = 0, PI = 52, DB = 1
N0.C0.D1.R0.S15: TxDq : plus1 = 1, minus1 = 0, PI = 31, DB = 0
N2.C2.D0.R0.S05: RdPtrOffsetTxDqs: 06
N4.C1.D0.R0.S03: RdPtrOffsetTxDq: 05
N6.C0.D1.R1.S03: TxDqs: plus1 = 1, minus1 = 0, PI = 08, DB = 1
N0.C0.D1.R0.S16: TxDqs: plus1 = 1, minus1 = 0, PI = 19, DB = 0
N2.C2.D0.R0.S05: PiTxDqs: 58
N4.C1.D0.R0.S03: RdPtrOffsetTxDqs: 07
N6.C0.D1.R1.S03: TxDq : plus1 = 1, minus1 = 0, PI = 39, DB = 0
N0.C0.D1.R0.S16: TxDq : plus1 = 1, minus1 = 0, PI = 48, DB = 0
N2.C2.D0.R0.S06: wrcmd2dqsstartlatency: 04
N4.C1.D0.R0.S03: PiTxDqs: 22
N6.C0.D1.R1.S04: TxDqs: plus1 = 1, minus1 = 0, PI = 35, DB = 0
N0.C0.D1.R0.S17: TxDqs: plus1 = 1, minus1 = 0, PI = 52, DB = 1
N2.C2.D0.R0.S06: RdPtrOffsetTxDq: 05
N4.C1.D0.R0.S04: wrcmd2dqsstartlatency: 04
N6.C0.D1.R1.S04: TxDq : plus1 = 1, minus1 = 0, PI = 03, DB = 1
N0.C0.D1.R0.S17: TxDq : plus1 = 1, minus1 = 0, PI = 17, DB = 0
N2.C2.D0.R0.S06: RdPtrOffsetTxDqs: 06
N4.C1.D0.R0.S04: RdPtrOffsetTxDq: 05
N6.C0.D1.R1.S05: TxDqs: plus1 = 1, minus1 = 0, PI = 55, DB = 1
N0.C0.D1.R1.S00: TxDqs: plus1 = 1, minus1 = 0, PI = 59, DB = 1
N2.C2.D0.R0.S06: PiTxDqs: 57
N4.C1.D0.R0.S04: RdPtrOffsetTxDqs: 06
N6.C0.D1.R1.S05: TxDq : plus1 = 1, minus1 = 0, PI = 22, DB = 0
N0.C0.D1.R1.S00: TxDq : plus1 = 1, minus1 = 0, PI = 26, DB = 0
N2.C2.D0.R0.S07: wrcmd2dqsstartlatency: 04
N4.C1.D0.R0.S04: PiTxDqs: 49
N6.C0.D1.R1.S06: TxDqs: plus1 = 1, minus1 = 0, PI = 58, DB = 1
N0.C0.D1.R1.S01: TxDqs: plus1 = 1, minus1 = 0, PI = 42, DB = 0
N2.C2.D0.R0.S07: RdPtrOffsetTxDq: 05
N4.C1.D0.R0.S05: wrcmd2dqsstartlatency: 04
N6.C0.D1.R1.S06: TxDq : plus1 = 1, minus1 = 0, PI = 26, DB = 0
N0.C0.D1.R1.S01: TxDq : plus1 = 1, minus1 = 0, PI = 09, DB = 1
N2.C2.D0.R0.S07: RdPtrOffsetTxDqs: 07
N4.C1.D0.R0.S05: RdPtrOffsetTxDq: 05
N6.C0.D1.R1.S07: TxDqs: plus1 = 1, minus1 = 0, PI = 10, DB = 1
N0.C0.D1.R1.S02: TxDqs: plus1 = 1, minus1 = 0, PI = 31, DB = 0
N2.C2.D0.R0.S07: PiTxDqs: 15
N4.C1.D0.R0.S05: RdPtrOffsetTxDqs: 06
N6.C0.D1.R1.S07: TxDq : plus1 = 1, minus1 = 0, PI = 41, DB = 0
N0.C0.D1.R1.S02: TxDq : plus1 = 1, minus1 = 0, PI = 59, DB = 1
N2.C2.D0.R0.S08: wrcmd2dqsstartlatency: 04
N4.C1.D0.R0.S05: PiTxDqs: 59
N6.C0.D1.R1.S08: TxDqs: plus1 = 1, minus1 = 0, PI = 44, DB = 0
N0.C0.D1.R1.S03: TxDqs: plus1 = 1, minus1 = 0, PI = 14, DB = 1
N2.C2.D0.R0.S08: RdPtrOffsetTxDq: 05
N4.C1.D0.R0.S06: wrcmd2dqsstartlatency: 04
N6.C0.D1.R1.S08: TxDq : plus1 = 1, minus1 = 0, PI = 12, DB = 1
N0.C0.D1.R1.S03: TxDq : plus1 = 1, minus1 = 0, PI = 44, DB = 0
N2.C2.D0.R0.S08: RdPtrOffsetTxDqs: 06
N4.C1.D0.R0.S06: RdPtrOffsetTxDq: 05
N6.C0.D1.R1.S09: TxDqs: plus1 = 1, minus1 = 0, PI = 52, DB = 1
N0.C0.D1.R1.S04: TxDqs: plus1 = 1, minus1 = 0, PI = 45, DB = 0
N2.C2.D0.R0.S08: PiTxDqs: 51
N4.C1.D0.R0.S06: RdPtrOffsetTxDqs: 07
N6.C0.D1.R1.S09: TxDq : plus1 = 1, minus1 = 0, PI = 19, DB = 0
N0.C0.D1.R1.S04: TxDq : plus1 = 1, minus1 = 0, PI = 11, DB = 1
N2.C2.D0.R0.S09: wrcmd2dqsstartlatency: 04
N4.C1.D0.R0.S06: PiTxDqs: 15
N6.C0.D1.R1.S10: TxDqs: plus1 = 1, minus1 = 0, PI = 35, DB = 0
N0.C0.D1.R1.S05: TxDqs: plus1 = 0, minus1 = 1, PI = 00, DB = 1
N2.C2.D0.R0.S09: RdPtrOffsetTxDq: 06
N4.C1.D0.R0.S07: wrcmd2dqsstartlatency: 04
N6.C0.D1.R1.S10: TxDq : plus1 = 0, minus1 = 1, PI = 02, DB = 1
N0.C0.D1.R1.S05: TxDq : plus1 = 1, minus1 = 0, PI = 29, DB = 0
N2.C2.D0.R0.S09: RdPtrOffsetTxDqs: 07
N4.C1.D0.R0.S07: RdPtrOffsetTxDq: 05
N6.C0.D1.R1.S11: TxDqs: plus1 = 1, minus1 = 0, PI = 22, DB = 0
N0.C0.D1.R1.S06: TxDqs: plus1 = 0, minus1 = 1, PI = 00, DB = 1
N2.C2.D0.R0.S09: PiTxDqs: 51
N4.C1.D0.R0.S07: RdPtrOffsetTxDqs: 07
N6.C0.D1.R1.S11: TxDq : plus1 = 1, minus1 = 0, PI = 52, DB = 1
N0.C0.D1.R1.S06: TxDq : plus1 = 1, minus1 = 0, PI = 30, DB = 0
N2.C2.D0.R0.S10: wrcmd2dqsstartlatency: 04
N4.C1.D0.R0.S07: PiTxDqs: 27
N6.C0.D1.R1.S12: TxDqs: plus1 = 1, minus1 = 0, PI = 08, DB = 1
N0.C0.D1.R1.S07: TxDqs: plus1 = 1, minus1 = 0, PI = 18, DB = 0
N2.C2.D0.R0.S10: RdPtrOffsetTxDq: 06
N4.C1.D0.R0.S08: wrcmd2dqsstartlatency: 04
N6.C0.D1.R1.S12: TxDq : plus1 = 1, minus1 = 0, PI = 38, DB = 0
N0.C0.D1.R1.S07: TxDq : plus1 = 1, minus1 = 0, PI = 48, DB = 0
N2.C2.D0.R0.S10: RdPtrOffsetTxDqs: 07
N4.C1.D0.R0.S08: RdPtrOffsetTxDq: 05
N6.C0.D1.R1.S13: TxDqs: plus1 = 1, minus1 = 0, PI = 36, DB = 0
N0.C0.D1.R1.S08: TxDqs: plus1 = 1, minus1 = 0, PI = 51, DB = 1
N2.C2.D0.R0.S10: PiTxDqs: 33
N4.C1.D0.R0.S08: RdPtrOffsetTxDqs: 07
N6.C0.D1.R1.S13: TxDq : plus1 = 1, minus1 = 0, PI = 03, DB = 1
N0.C0.D1.R1.S08: TxDq : plus1 = 1, minus1 = 0, PI = 17, DB = 0
N2.C2.D0.R0.S11: wrcmd2dqsstartlatency: 04
N4.C1.D0.R0.S08: PiTxDqs: 00
N6.C0.D1.R1.S14: TxDqs: plus1 = 1, minus1 = 0, PI = 55, DB = 1
N0.C0.D1.R1.S09: TxDqs: plus1 = 1, minus1 = 0, PI = 58, DB = 1
N2.C2.D0.R0.S11: RdPtrOffsetTxDq: 05
N4.C1.D0.R0.S09: wrcmd2dqsstartlatency: 04
N6.C0.D1.R1.S14: TxDq : plus1 = 1, minus1 = 0, PI = 22, DB = 0
N0.C0.D1.R1.S09: TxDq : plus1 = 1, minus1 = 0, PI = 24, DB = 0
N2.C2.D0.R0.S11: RdPtrOffsetTxDqs: 07
N4.C1.D0.R0.S09: RdPtrOffsetTxDq: 06
N6.C0.D1.R1.S15: TxDqs: plus1 = 1, minus1 = 0, PI = 58, DB = 1
N0.C0.D1.R1.S10: TxDqs: plus1 = 1, minus1 = 0, PI = 43, DB = 0
N2.C2.D0.R0.S11: PiTxDqs: 23
N4.C1.D0.R0.S09: RdPtrOffsetTxDqs: 07
N6.C0.D1.R1.S15: TxDq : plus1 = 1, minus1 = 0, PI = 25, DB = 0
N0.C0.D1.R1.S10: TxDq : plus1 = 1, minus1 = 0, PI = 09, DB = 1
N2.C2.D0.R0.S12: wrcmd2dqsstartlatency: 04
N4.C1.D0.R0.S09: PiTxDqs: 61
N6.C0.D1.R1.S16: TxDqs: plus1 = 1, minus1 = 0, PI = 10, DB = 1
N0.C0.D1.R1.S11: TxDqs: plus1 = 1, minus1 = 0, PI = 30, DB = 0
N2.C2.D0.R0.S12: RdPtrOffsetTxDq: 05
N4.C1.D0.R0.S10: wrcmd2dqsstartlatency: 04
N6.C0.D1.R1.S16: TxDq : plus1 = 1, minus1 = 0, PI = 41, DB = 0
N0.C0.D1.R1.S11: TxDq : plus1 = 1, minus1 = 0, PI = 59, DB = 1
N2.C2.D0.R0.S12: RdPtrOffsetTxDqs: 07
N4.C1.D0.R0.S10: RdPtrOffsetTxDq: 06
N6.C0.D1.R1.S17: TxDqs: plus1 = 1, minus1 = 0, PI = 45, DB = 0
N0.C0.D1.R1.S12: TxDqs: plus1 = 1, minus1 = 0, PI = 16, DB = 0
N2.C2.D0.R0.S12: PiTxDqs: 07
N4.C1.D0.R0.S10: RdPtrOffsetTxDqs: 07
N6.C0.D1.R1.S17: TxDq : plus1 = 1, minus1 = 0, PI = 11, DB = 1
N0.C0.D1.R1.S12: TxDq : plus1 = 1, minus1 = 0, PI = 47, DB = 0
N2.C2.D0.R0.S13: wrcmd2dqsstartlatency: 04
N4.C1.D0.R0.S10: PiTxDqs: 43
END_DATA_TX_DQ
N0.C0.D1.R1.S13: TxDqs: plus1 = 1, minus1 = 0, PI = 46, DB = 0
N2.C2.D0.R0.S13: RdPtrOffsetTxDq: 04
N4.C1.D0.R0.S11: wrcmd2dqsstartlatency: 04
N6.C1.D0.R0.S00: wrcmd2dqsstartlatency: 04
N0.C0.D1.R1.S13: TxDq : plus1 = 1, minus1 = 0, PI = 12, DB = 1
N2.C2.D0.R0.S13: RdPtrOffsetTxDqs: 06
N4.C1.D0.R0.S11: RdPtrOffsetTxDq: 06
N6.C1.D0.R0.S00: RdPtrOffsetTxDq: 06
N0.C0.D1.R1.S14: TxDqs: plus1 = 1, minus1 = 0, PI = 62, DB = 1
N2.C2.D0.R0.S13: PiTxDqs: 30
N4.C1.D0.R0.S11: RdPtrOffsetTxDqs: 07
N6.C1.D0.R0.S00: RdPtrOffsetTxDqs: 07
N0.C0.D1.R1.S14: TxDq : plus1 = 1, minus1 = 0, PI = 28, DB = 0
N2.C2.D0.R0.S14: wrcmd2dqsstartlatency: 04
N4.C1.D0.R0.S11: PiTxDqs: 37
N6.C1.D0.R0.S00: PiTxDqs: 52
N0.C0.D1.R1.S15: TxDqs: plus1 = 0, minus1 = 1, PI = 02, DB = 1
N2.C2.D0.R0.S14: RdPtrOffsetTxDq: 05
N4.C1.D0.R0.S12: wrcmd2dqsstartlatency: 04
N6.C1.D0.R0.S01: wrcmd2dqsstartlatency: 04
N0.C0.D1.R1.S15: TxDq : plus1 = 1, minus1 = 0, PI = 31, DB = 0
N2.C2.D0.R0.S14: RdPtrOffsetTxDqs: 06
N4.C1.D0.R0.S12: RdPtrOffsetTxDq: 05
N6.C1.D0.R0.S01: RdPtrOffsetTxDq: 06
N0.C0.D1.R1.S16: TxDqs: plus1 = 1, minus1 = 0, PI = 19, DB = 0
N2.C2.D0.R0.S14: PiTxDqs: 57
N4.C1.D0.R0.S12: RdPtrOffsetTxDqs: 07
N6.C1.D0.R0.S01: RdPtrOffsetTxDqs: 07
N0.C0.D1.R1.S16: TxDq : plus1 = 1, minus1 = 0, PI = 48, DB = 0
N2.C2.D0.R0.S15: wrcmd2dqsstartlatency: 04
N4.C1.D0.R0.S12: PiTxDqs: 18
N6.C1.D0.R0.S01: PiTxDqs: 37
N0.C0.D1.R1.S17: TxDqs: plus1 = 1, minus1 = 0, PI = 52, DB = 1
N2.C2.D0.R0.S15: RdPtrOffsetTxDq: 05
N4.C1.D0.R0.S13: wrcmd2dqsstartlatency: 04
N6.C1.D0.R0.S02: wrcmd2dqsstartlatency: 04
N0.C0.D1.R1.S17: TxDq : plus1 = 1, minus1 = 0, PI = 17, DB = 0
N2.C2.D0.R0.S15: RdPtrOffsetTxDqs: 06
N4.C1.D0.R0.S13: RdPtrOffsetTxDq: 05
N6.C1.D0.R0.S02: RdPtrOffsetTxDq: 05
END_DATA_TX_DQ
N2.C2.D0.R0.S15: PiTxDqs: 56
N4.C1.D0.R0.S13: RdPtrOffsetTxDqs: 06
N6.C1.D0.R0.S02: RdPtrOffsetTxDqs: 07
N0.C1.D0.R0.S00: wrcmd2dqsstartlatency: 04
N2.C2.D0.R0.S16: wrcmd2dqsstartlatency: 04
N4.C1.D0.R0.S13: PiTxDqs: 50
N6.C1.D0.R0.S02: PiTxDqs: 27
N0.C1.D0.R0.S00: RdPtrOffsetTxDq: 06
N2.C2.D0.R0.S16: RdPtrOffsetTxDq: 05
N4.C1.D0.R0.S14: wrcmd2dqsstartlatency: 04
N6.C1.D0.R0.S03: wrcmd2dqsstartlatency: 04
N0.C1.D0.R0.S00: RdPtrOffsetTxDqs: 07
N2.C2.D0.R0.S16: RdPtrOffsetTxDqs: 07
N4.C1.D0.R0.S14: RdPtrOffsetTxDq: 05
N6.C1.D0.R0.S03: RdPtrOffsetTxDq: 05
N0.C1.D0.R0.S00: PiTxDqs: 58
N2.C2.D0.R0.S16: PiTxDqs: 16
N4.C1.D0.R0.S14: RdPtrOffsetTxDqs: 06
N6.C1.D0.R0.S03: RdPtrOffsetTxDqs: 07
N0.C1.D0.R0.S01: wrcmd2dqsstartlatency: 04
N2.C2.D0.R0.S17: wrcmd2dqsstartlatency: 04
N4.C1.D0.R0.S14: PiTxDqs: 63
N6.C1.D0.R0.S03: PiTxDqs: 11
N0.C1.D0.R0.S01: RdPtrOffsetTxDq: 06
N2.C2.D0.R0.S17: RdPtrOffsetTxDq: 05
N4.C1.D0.R0.S15: wrcmd2dqsstartlatency: 04
N6.C1.D0.R0.S04: wrcmd2dqsstartlatency: 04
N0.C1.D0.R0.S01: RdPtrOffsetTxDqs: 07
N2.C2.D0.R0.S17: RdPtrOffsetTxDqs: 06
N4.C1.D0.R0.S15: RdPtrOffsetTxDq: 05
N6.C1.D0.R0.S04: RdPtrOffsetTxDq: 05
N0.C1.D0.R0.S01: PiTxDqs: 39
N2.C2.D0.R0.S17: PiTxDqs: 50
N4.C1.D0.R0.S15: RdPtrOffsetTxDqs: 07
N6.C1.D0.R0.S04: RdPtrOffsetTxDqs: 06
N0.C1.D0.R0.S02: wrcmd2dqsstartlatency: 04
N2.C2.D0.R0.S00: RdPtrOffsetTxDq: 07
N4.C1.D0.R0.S15: PiTxDqs: 11
N6.C1.D0.R0.S04: PiTxDqs: 42
N0.C1.D0.R0.S02: RdPtrOffsetTxDq: 06
N2.C2.D0.R0.S01: RdPtrOffsetTxDq: 07
N4.C1.D0.R0.S16: wrcmd2dqsstartlatency: 04
N6.C1.D0.R0.S05: wrcmd2dqsstartlatency: 04
N0.C1.D0.R0.S02: RdPtrOffsetTxDqs: 07
N2.C2.D0.R0.S02: RdPtrOffsetTxDq: 06
N4.C1.D0.R0.S16: RdPtrOffsetTxDq: 05
N6.C1.D0.R0.S05: RdPtrOffsetTxDq: 05
N0.C1.D0.R0.S02: PiTxDqs: 34
N2.C2.D0.R0.S03: RdPtrOffsetTxDq: 06
N4.C1.D0.R0.S16: RdPtrOffsetTxDqs: 07
N6.C1.D0.R0.S05: RdPtrOffsetTxDqs: 06
N0.C1.D0.R0.S03: wrcmd2dqsstartlatency: 04
N2.C2.D0.R0.S04: RdPtrOffsetTxDq: 05
N4.C1.D0.R0.S16: PiTxDqs: 27
N6.C1.D0.R0.S05: PiTxDqs: 57
N0.C1.D0.R0.S03: RdPtrOffsetTxDq: 05
N2.C2.D0.R0.S05: RdPtrOffsetTxDq: 06
N4.C1.D0.R0.S17: wrcmd2dqsstartlatency: 04
N6.C1.D0.R0.S06: wrcmd2dqsstartlatency: 04
N0.C1.D0.R0.S03: RdPtrOffsetTxDqs: 07
N2.C2.D0.R0.S06: RdPtrOffsetTxDq: 06
N4.C1.D0.R0.S17: RdPtrOffsetTxDq: 05
N6.C1.D0.R0.S06: RdPtrOffsetTxDq: 05
N0.C1.D0.R0.S03: PiTxDqs: 15
N2.C2.D0.R0.S07: RdPtrOffsetTxDq: 06
N4.C1.D0.R0.S17: RdPtrOffsetTxDqs: 07
N6.C1.D0.R0.S06: RdPtrOffsetTxDqs: 07
N0.C1.D0.R0.S04: wrcmd2dqsstartlatency: 04
N2.C2.D0.R0.S08: RdPtrOffsetTxDq: 06
N4.C1.D0.R0.S17: PiTxDqs: 02
N6.C1.D0.R0.S06: PiTxDqs: 08
N0.C1.D0.R0.S04: RdPtrOffsetTxDq: 05
N2.C2.D0.R0.S09: RdPtrOffsetTxDq: 07
N4.C1.D0.R0.S00: RdPtrOffsetTxDq: 07
N6.C1.D0.R0.S07: wrcmd2dqsstartlatency: 04
N0.C1.D0.R0.S04: RdPtrOffsetTxDqs: 06
N2.C2.D0.R0.S10: RdPtrOffsetTxDq: 07
N4.C1.D0.R0.S01: RdPtrOffsetTxDq: 07
N6.C1.D0.R0.S07: RdPtrOffsetTxDq: 05
N0.C1.D0.R0.S04: PiTxDqs: 44
N2.C2.D0.R0.S11: RdPtrOffsetTxDq: 06
N4.C1.D0.R0.S02: RdPtrOffsetTxDq: 06
N6.C1.D0.R0.S07: RdPtrOffsetTxDqs: 07
N0.C1.D0.R0.S05: wrcmd2dqsstartlatency: 04
N2.C2.D0.R0.S12: RdPtrOffsetTxDq: 06
N4.C1.D0.R0.S03: RdPtrOffsetTxDq: 06
N6.C1.D0.R0.S07: PiTxDqs: 24
N0.C1.D0.R0.S05: RdPtrOffsetTxDq: 05
N2.C2.D0.R0.S13: RdPtrOffsetTxDq: 05
N4.C1.D0.R0.S04: RdPtrOffsetTxDq: 06
N6.C1.D0.R0.S08: wrcmd2dqsstartlatency: 04
N0.C1.D0.R0.S05: RdPtrOffsetTxDqs: 06
N2.C2.D0.R0.S14: RdPtrOffsetTxDq: 06
N4.C1.D0.R0.S05: RdPtrOffsetTxDq: 06
N6.C1.D0.R0.S08: RdPtrOffsetTxDq: 05
N0.C1.D0.R0.S05: PiTxDqs: 60
N2.C2.D0.R0.S15: RdPtrOffsetTxDq: 06
N4.C1.D0.R0.S06: RdPtrOffsetTxDq: 06
N6.C1.D0.R0.S08: RdPtrOffsetTxDqs: 06
N0.C1.D0.R0.S06: wrcmd2dqsstartlatency: 04
N2.C2.D0.R0.S16: RdPtrOffsetTxDq: 06
N4.C1.D0.R0.S07: RdPtrOffsetTxDq: 06
N6.C1.D0.R0.S08: PiTxDqs: 59
N0.C1.D0.R0.S06: RdPtrOffsetTxDq: 05
N2.C2.D0.R0.S17: RdPtrOffsetTxDq: 06
N4.C1.D0.R0.S08: RdPtrOffsetTxDq: 06
N6.C1.D0.R0.S09: wrcmd2dqsstartlatency: 04
N0.C1.D0.R0.S06: RdPtrOffsetTxDqs: 07
N2.C2.D0.R0.S00: RdPtrOffsetTxDq: 08
N4.C1.D0.R0.S09: RdPtrOffsetTxDq: 07
N6.C1.D0.R0.S09: RdPtrOffsetTxDq: 06
N0.C1.D0.R0.S06: PiTxDqs: 13
N2.C2.D0.R0.S01: RdPtrOffsetTxDq: 08
N4.C1.D0.R0.S10: RdPtrOffsetTxDq: 07
N6.C1.D0.R0.S09: RdPtrOffsetTxDqs: 07
N0.C1.D0.R0.S07: wrcmd2dqsstartlatency: 04
N2.C2.D0.R0.S02: RdPtrOffsetTxDq: 07
N4.C1.D0.R0.S11: RdPtrOffsetTxDq: 07
N6.C1.D0.R0.S09: PiTxDqs: 53
N0.C1.D0.R0.S07: RdPtrOffsetTxDq: 05
N2.C2.D0.R0.S03: RdPtrOffsetTxDq: 07
N4.C1.D0.R0.S12: RdPtrOffsetTxDq: 06
N6.C1.D0.R0.S10: wrcmd2dqsstartlatency: 04
N0.C1.D0.R0.S07: RdPtrOffsetTxDqs: 07
N2.C2.D0.R0.S04: RdPtrOffsetTxDq: 06
N4.C1.D0.R0.S13: RdPtrOffsetTxDq: 06
N6.C1.D0.R0.S10: RdPtrOffsetTxDq: 06
N0.C1.D0.R0.S07: PiTxDqs: 28
N2.C2.D0.R0.S05: RdPtrOffsetTxDq: 07
N4.C1.D0.R0.S14: RdPtrOffsetTxDq: 06
N6.C1.D0.R0.S10: RdPtrOffsetTxDqs: 07
N0.C1.D0.R0.S08: wrcmd2dqsstartlatency: 04
N2.C2.D0.R0.S06: RdPtrOffsetTxDq: 07
N4.C1.D0.R0.S15: RdPtrOffsetTxDq: 06
N6.C1.D0.R0.S10: PiTxDqs: 36
N0.C1.D0.R0.S08: RdPtrOffsetTxDq: 05
N2.C2.D0.R0.S07: RdPtrOffsetTxDq: 07
N4.C1.D0.R0.S16: RdPtrOffsetTxDq: 06
N6.C1.D0.R0.S11: wrcmd2dqsstartlatency: 04
N0.C1.D0.R0.S08: RdPtrOffsetTxDqs: 06
N2.C2.D0.R0.S08: RdPtrOffsetTxDq: 07
N4.C1.D0.R0.S17: RdPtrOffsetTxDq: 06
N6.C1.D0.R0.S11: RdPtrOffsetTxDq: 05
N0.C1.D0.R0.S08: PiTxDqs: 59
N2.C2.D0.R0.S09: RdPtrOffsetTxDq: 08
N4.C1.D0.R0.S00: RdPtrOffsetTxDq: 08
N6.C1.D0.R0.S11: RdPtrOffsetTxDqs: 07
N0.C1.D0.R0.S09: wrcmd2dqsstartlatency: 04
N2.C2.D0.R0.S10: RdPtrOffsetTxDq: 08
N4.C1.D0.R0.S01: RdPtrOffsetTxDq: 08
N6.C1.D0.R0.S11: PiTxDqs: 29
N0.C1.D0.R0.S09: RdPtrOffsetTxDq: 06
N2.C2.D0.R0.S11: RdPtrOffsetTxDq: 07
N4.C1.D0.R0.S02: RdPtrOffsetTxDq: 07
N6.C1.D0.R0.S12: wrcmd2dqsstartlatency: 04
N0.C1.D0.R0.S09: RdPtrOffsetTxDqs: 07
N2.C2.D0.R0.S12: RdPtrOffsetTxDq: 07
N4.C1.D0.R0.S03: RdPtrOffsetTxDq: 07
N6.C1.D0.R0.S12: RdPtrOffsetTxDq: 05
N0.C1.D0.R0.S09: PiTxDqs: 58
N2.C2.D0.R0.S13: RdPtrOffsetTxDq: 06
N4.C1.D0.R0.S04: RdPtrOffsetTxDq: 07
N6.C1.D0.R0.S12: RdPtrOffsetTxDqs: 07
N0.C1.D0.R0.S10: wrcmd2dqsstartlatency: 04
N2.C2.D0.R0.S14: RdPtrOffsetTxDq: 07
N4.C1.D0.R0.S05: RdPtrOffsetTxDq: 07
N6.C1.D0.R0.S12: PiTxDqs: 12
N0.C1.D0.R0.S10: RdPtrOffsetTxDq: 06
N2.C2.D0.R0.S15: RdPtrOffsetTxDq: 07
N4.C1.D0.R0.S06: RdPtrOffsetTxDq: 07
N6.C1.D0.R0.S13: wrcmd2dqsstartlatency: 04
N0.C1.D0.R0.S10: RdPtrOffsetTxDqs: 07
N2.C2.D0.R0.S16: RdPtrOffsetTxDq: 07
N4.C1.D0.R0.S07: RdPtrOffsetTxDq: 07
N6.C1.D0.R0.S13: RdPtrOffsetTxDq: 05
N0.C1.D0.R0.S10: PiTxDqs: 40
N2.C2.D0.R0.S17: RdPtrOffsetTxDq: 07
N4.C1.D0.R0.S08: RdPtrOffsetTxDq: 07
N6.C1.D0.R0.S13: RdPtrOffsetTxDqs: 06
N0.C1.D0.R0.S11: wrcmd2dqsstartlatency: 04
N2.C2.D0.R0.S00: Total Delay in PI ticks: TxDQ = 978
N4.C1.D0.R0.S09: RdPtrOffsetTxDq: 08
N6.C1.D0.R0.S13: PiTxDqs: 41
N0.C1.D0.R0.S11: RdPtrOffsetTxDq: 06
N2.C2.D0.R0.S01: Total Delay in PI ticks: TxDQ = 963
N4.C1.D0.R0.S10: RdPtrOffsetTxDq: 08
N6.C1.D0.R0.S14: wrcmd2dqsstartlatency: 04
N0.C1.D0.R0.S11: RdPtrOffsetTxDqs: 07
N2.C2.D0.R0.S02: Total Delay in PI ticks: TxDQ = 954
N4.C1.D0.R0.S11: RdPtrOffsetTxDq: 08
N6.C1.D0.R0.S14: RdPtrOffsetTxDq: 05
N0.C1.D0.R0.S11: PiTxDqs: 34
N2.C2.D0.R0.S03: Total Delay in PI ticks: TxDQ = 933
N4.C1.D0.R0.S12: RdPtrOffsetTxDq: 07
N6.C1.D0.R0.S14: RdPtrOffsetTxDqs: 06
N0.C1.D0.R0.S12: wrcmd2dqsstartlatency: 04
N2.C2.D0.R0.S04: Total Delay in PI ticks: TxDQ = 895
N4.C1.D0.R0.S13: RdPtrOffsetTxDq: 07
N6.C1.D0.R0.S14: PiTxDqs: 54
N0.C1.D0.R0.S12: RdPtrOffsetTxDq: 05
N2.C2.D0.R0.S05: Total Delay in PI ticks: TxDQ = 921
N4.C1.D0.R0.S14: RdPtrOffsetTxDq: 07
N6.C1.D0.R0.S15: wrcmd2dqsstartlatency: 04
N0.C1.D0.R0.S12: RdPtrOffsetTxDqs: 07
N2.C2.D0.R0.S06: Total Delay in PI ticks: TxDQ = 922
N4.C1.D0.R0.S15: RdPtrOffsetTxDq: 07
N6.C1.D0.R0.S15: RdPtrOffsetTxDq: 05
N0.C1.D0.R0.S12: PiTxDqs: 15
N2.C2.D0.R0.S07: Total Delay in PI ticks: TxDQ = 941
N4.C1.D0.R0.S16: RdPtrOffsetTxDq: 07
N6.C1.D0.R0.S15: RdPtrOffsetTxDqs: 07
N0.C1.D0.R0.S13: wrcmd2dqsstartlatency: 04
N2.C2.D0.R0.S08: Total Delay in PI ticks: TxDQ = 915
N4.C1.D0.R0.S17: RdPtrOffsetTxDq: 07
N6.C1.D0.R0.S15: PiTxDqs: 06
N0.C1.D0.R0.S13: RdPtrOffsetTxDq: 05
N2.C2.D0.R0.S09: Total Delay in PI ticks: TxDQ = 979
N4.C1.D0.R0.S00: Total Delay in PI ticks: TxDQ = 987
N6.C1.D0.R0.S16: wrcmd2dqsstartlatency: 04
N0.C1.D0.R0.S13: RdPtrOffsetTxDqs: 06
N2.C2.D0.R0.S10: Total Delay in PI ticks: TxDQ = 962
N4.C1.D0.R0.S01: Total Delay in PI ticks: TxDQ = 969
N6.C1.D0.R0.S16: RdPtrOffsetTxDq: 05
N0.C1.D0.R0.S13: PiTxDqs: 45
N2.C2.D0.R0.S11: Total Delay in PI ticks: TxDQ = 951
N4.C1.D0.R0.S02: Total Delay in PI ticks: TxDQ = 961
N6.C1.D0.R0.S16: RdPtrOffsetTxDqs: 07
N0.C1.D0.R0.S14: wrcmd2dqsstartlatency: 04
N2.C2.D0.R0.S12: Total Delay in PI ticks: TxDQ = 933
N4.C1.D0.R0.S03: Total Delay in PI ticks: TxDQ = 948
N6.C1.D0.R0.S16: PiTxDqs: 22
N0.C1.D0.R0.S14: RdPtrOffsetTxDq: 05
N2.C2.D0.R0.S13: Total Delay in PI ticks: TxDQ = 895
N4.C1.D0.R0.S04: Total Delay in PI ticks: TxDQ = 911
N6.C1.D0.R0.S17: wrcmd2dqsstartlatency: 04
N0.C1.D0.R0.S14: RdPtrOffsetTxDqs: 06
N2.C2.D0.R0.S14: Total Delay in PI ticks: TxDQ = 921
N4.C1.D0.R0.S05: Total Delay in PI ticks: TxDQ = 922
N6.C1.D0.R0.S17: RdPtrOffsetTxDq: 05
N0.C1.D0.R0.S14: PiTxDqs: 59
N2.C2.D0.R0.S15: Total Delay in PI ticks: TxDQ = 920
N4.C1.D0.R0.S06: Total Delay in PI ticks: TxDQ = 942
N6.C1.D0.R0.S17: RdPtrOffsetTxDqs: 06
N0.C1.D0.R0.S15: wrcmd2dqsstartlatency: 04
N2.C2.D0.R0.S16: Total Delay in PI ticks: TxDQ = 943
N4.C1.D0.R0.S07: Total Delay in PI ticks: TxDQ = 953
N6.C1.D0.R0.S17: PiTxDqs: 58
N0.C1.D0.R0.S15: RdPtrOffsetTxDq: 05
N2.C2.D0.R0.S17: Total Delay in PI ticks: TxDQ = 914
N4.C1.D0.R0.S08: Total Delay in PI ticks: TxDQ = 926
N6.C1.D0.R0.S00: RdPtrOffsetTxDq: 07
N0.C1.D0.R0.S15: RdPtrOffsetTxDqs: 07
N2.C2.D0.R1.S00: wrcmd2dqsstartlatency: 04
N4.C1.D0.R0.S09: Total Delay in PI ticks: TxDQ = 987
N6.C1.D0.R0.S01: RdPtrOffsetTxDq: 07
N0.C1.D0.R0.S15: PiTxDqs: 10
N2.C2.D0.R1.S00: RdPtrOffsetTxDq: 06
N4.C1.D0.R0.S10: Total Delay in PI ticks: TxDQ = 970
N6.C1.D0.R0.S02: RdPtrOffsetTxDq: 06
N0.C1.D0.R0.S16: wrcmd2dqsstartlatency: 04
N2.C2.D0.R1.S00: RdPtrOffsetTxDqs: 07
N4.C1.D0.R0.S11: Total Delay in PI ticks: TxDQ = 964
N6.C1.D0.R0.S03: RdPtrOffsetTxDq: 06
N0.C1.D0.R0.S16: RdPtrOffsetTxDq: 05
N2.C2.D0.R1.S00: PiTxDqs: 42
N4.C1.D0.R0.S12: Total Delay in PI ticks: TxDQ = 946
N6.C1.D0.R0.S04: RdPtrOffsetTxDq: 06
N0.C1.D0.R0.S16: RdPtrOffsetTxDqs: 07
N2.C2.D0.R1.S01: wrcmd2dqsstartlatency: 04
N4.C1.D0.R0.S13: Total Delay in PI ticks: TxDQ = 911
N6.C1.D0.R0.S05: RdPtrOffsetTxDq: 06
N0.C1.D0.R0.S16: PiTxDqs: 28
N2.C2.D0.R1.S01: RdPtrOffsetTxDq: 05
N4.C1.D0.R0.S14: Total Delay in PI ticks: TxDQ = 925
N6.C1.D0.R0.S06: RdPtrOffsetTxDq: 06
N0.C1.D0.R0.S17: wrcmd2dqsstartlatency: 04
N2.C2.D0.R1.S01: RdPtrOffsetTxDqs: 07
N4.C1.D0.R0.S15: Total Delay in PI ticks: TxDQ = 940
N6.C1.D0.R0.S07: RdPtrOffsetTxDq: 06
N0.C1.D0.R0.S17: RdPtrOffsetTxDq: 05
N2.C2.D0.R1.S01: PiTxDqs: 28
N4.C1.D0.R0.S16: Total Delay in PI ticks: TxDQ = 953
N6.C1.D0.R0.S08: RdPtrOffsetTxDq: 06
N0.C1.D0.R0.S17: RdPtrOffsetTxDqs: 06
N2.C2.D0.R1.S02: wrcmd2dqsstartlatency: 04
N4.C1.D0.R0.S17: Total Delay in PI ticks: TxDQ = 930
N6.C1.D0.R0.S09: RdPtrOffsetTxDq: 07
N0.C1.D0.R0.S17: PiTxDqs: 62
N2.C2.D0.R1.S02: RdPtrOffsetTxDq: 05
N4.C1.D0.R1.S00: wrcmd2dqsstartlatency: 04
N6.C1.D0.R0.S10: RdPtrOffsetTxDq: 07
N0.C1.D0.R0.S00: RdPtrOffsetTxDq: 07
N2.C2.D0.R1.S02: RdPtrOffsetTxDqs: 07
N4.C1.D0.R1.S00: RdPtrOffsetTxDq: 06
N6.C1.D0.R0.S11: RdPtrOffsetTxDq: 06
N0.C1.D0.R0.S01: RdPtrOffsetTxDq: 07
N2.C2.D0.R1.S02: PiTxDqs: 17
N4.C1.D0.R1.S00: RdPtrOffsetTxDqs: 07
N6.C1.D0.R0.S12: RdPtrOffsetTxDq: 06
N0.C1.D0.R0.S02: RdPtrOffsetTxDq: 07
N2.C2.D0.R1.S03: wrcmd2dqsstartlatency: 04
N4.C1.D0.R1.S00: PiTxDqs: 51
N6.C1.D0.R0.S13: RdPtrOffsetTxDq: 06
N0.C1.D0.R0.S03: RdPtrOffsetTxDq: 06
N2.C2.D0.R1.S03: RdPtrOffsetTxDq: 05
N4.C1.D0.R1.S01: wrcmd2dqsstartlatency: 04
N6.C1.D0.R0.S14: RdPtrOffsetTxDq: 06
N0.C1.D0.R0.S04: RdPtrOffsetTxDq: 06
N2.C2.D0.R1.S03: RdPtrOffsetTxDqs: 06
N4.C1.D0.R1.S01: RdPtrOffsetTxDq: 06
N6.C1.D0.R0.S15: RdPtrOffsetTxDq: 06
N0.C1.D0.R0.S05: RdPtrOffsetTxDq: 06
N2.C2.D0.R1.S03: PiTxDqs: 63
N4.C1.D0.R1.S01: RdPtrOffsetTxDqs: 07
N6.C1.D0.R0.S16: RdPtrOffsetTxDq: 06
N0.C1.D0.R0.S06: RdPtrOffsetTxDq: 06
N2.C2.D0.R1.S04: wrcmd2dqsstartlatency: 04
N4.C1.D0.R1.S01: PiTxDqs: 37
N6.C1.D0.R0.S17: RdPtrOffsetTxDq: 06
N0.C1.D0.R0.S07: RdPtrOffsetTxDq: 06
N2.C2.D0.R1.S04: RdPtrOffsetTxDq: 04
N4.C1.D0.R1.S02: wrcmd2dqsstartlatency: 04
N6.C1.D0.R0.S00: RdPtrOffsetTxDq: 08
N0.C1.D0.R0.S08: RdPtrOffsetTxDq: 06
N2.C2.D0.R1.S04: RdPtrOffsetTxDqs: 06
N4.C1.D0.R1.S02: RdPtrOffsetTxDq: 05
N6.C1.D0.R0.S01: RdPtrOffsetTxDq: 08
N0.C1.D0.R0.S09: RdPtrOffsetTxDq: 07
N2.C2.D0.R1.S04: PiTxDqs: 23
N4.C1.D0.R1.S02: RdPtrOffsetTxDqs: 07
N6.C1.D0.R0.S02: RdPtrOffsetTxDq: 07
N0.C1.D0.R0.S10: RdPtrOffsetTxDq: 07
N2.C2.D0.R1.S05: wrcmd2dqsstartlatency: 04
N4.C1.D0.R1.S02: PiTxDqs: 27
N6.C1.D0.R0.S03: RdPtrOffsetTxDq: 07
N0.C1.D0.R0.S11: RdPtrOffsetTxDq: 07
N2.C2.D0.R1.S05: RdPtrOffsetTxDq: 05
N4.C1.D0.R1.S03: wrcmd2dqsstartlatency: 04
N6.C1.D0.R0.S04: RdPtrOffsetTxDq: 07
N0.C1.D0.R0.S12: RdPtrOffsetTxDq: 06
N2.C2.D0.R1.S05: RdPtrOffsetTxDqs: 06
N4.C1.D0.R1.S03: RdPtrOffsetTxDq: 05
N6.C1.D0.R0.S05: RdPtrOffsetTxDq: 07
N0.C1.D0.R0.S13: RdPtrOffsetTxDq: 06
N2.C2.D0.R1.S05: PiTxDqs: 52
N4.C1.D0.R1.S03: RdPtrOffsetTxDqs: 07
N6.C1.D0.R0.S06: RdPtrOffsetTxDq: 07
N0.C1.D0.R0.S14: RdPtrOffsetTxDq: 06
N2.C2.D0.R1.S06: wrcmd2dqsstartlatency: 04
N4.C1.D0.R1.S03: PiTxDqs: 13
N6.C1.D0.R0.S07: RdPtrOffsetTxDq: 07
N0.C1.D0.R0.S15: RdPtrOffsetTxDq: 06
N2.C2.D0.R1.S06: RdPtrOffsetTxDq: 05
N4.C1.D0.R1.S04: wrcmd2dqsstartlatency: 04
N6.C1.D0.R0.S08: RdPtrOffsetTxDq: 07
N0.C1.D0.R0.S16: RdPtrOffsetTxDq: 06
N2.C2.D0.R1.S06: RdPtrOffsetTxDqs: 06
N4.C1.D0.R1.S04: RdPtrOffsetTxDq: 05
N6.C1.D0.R0.S09: RdPtrOffsetTxDq: 08
N0.C1.D0.R0.S17: RdPtrOffsetTxDq: 06
N2.C2.D0.R1.S06: PiTxDqs: 49
N4.C1.D0.R1.S04: RdPtrOffsetTxDqs: 06
N6.C1.D0.R0.S10: RdPtrOffsetTxDq: 08
N0.C1.D0.R0.S00: RdPtrOffsetTxDq: 08
N2.C2.D0.R1.S07: wrcmd2dqsstartlatency: 04
N4.C1.D0.R1.S04: PiTxDqs: 42
N6.C1.D0.R0.S11: RdPtrOffsetTxDq: 07
N0.C1.D0.R0.S01: RdPtrOffsetTxDq: 08
N2.C2.D0.R1.S07: RdPtrOffsetTxDq: 05
N4.C1.D0.R1.S05: wrcmd2dqsstartlatency: 04
N6.C1.D0.R0.S12: RdPtrOffsetTxDq: 07
N0.C1.D0.R0.S02: RdPtrOffsetTxDq: 08
N2.C2.D0.R1.S07: RdPtrOffsetTxDqs: 07
N4.C1.D0.R1.S05: RdPtrOffsetTxDq: 05
N6.C1.D0.R0.S13: RdPtrOffsetTxDq: 07
N0.C1.D0.R0.S03: RdPtrOffsetTxDq: 07
N2.C2.D0.R1.S07: PiTxDqs: 09
N4.C1.D0.R1.S05: RdPtrOffsetTxDqs: 06
N6.C1.D0.R0.S14: RdPtrOffsetTxDq: 07
N0.C1.D0.R0.S04: RdPtrOffsetTxDq: 07
N2.C2.D0.R1.S08: wrcmd2dqsstartlatency: 04
N4.C1.D0.R1.S05: PiTxDqs: 56
N6.C1.D0.R0.S15: RdPtrOffsetTxDq: 07
N0.C1.D0.R0.S05: RdPtrOffsetTxDq: 07
N2.C2.D0.R1.S08: RdPtrOffsetTxDq: 05
N4.C1.D0.R1.S06: wrcmd2dqsstartlatency: 04
N6.C1.D0.R0.S16: RdPtrOffsetTxDq: 07
N0.C1.D0.R0.S06: RdPtrOffsetTxDq: 07
N2.C2.D0.R1.S08: RdPtrOffsetTxDqs: 06
N4.C1.D0.R1.S06: RdPtrOffsetTxDq: 05
N6.C1.D0.R0.S17: RdPtrOffsetTxDq: 07
N0.C1.D0.R0.S07: RdPtrOffsetTxDq: 07
N2.C2.D0.R1.S08: PiTxDqs: 41
N4.C1.D0.R1.S06: RdPtrOffsetTxDqs: 07
N6.C1.D0.R0.S00: Total Delay in PI ticks: TxDQ = 981
N0.C1.D0.R0.S08: RdPtrOffsetTxDq: 07
N2.C2.D0.R1.S09: wrcmd2dqsstartlatency: 04
N4.C1.D0.R1.S06: PiTxDqs: 03
N6.C1.D0.R0.S01: Total Delay in PI ticks: TxDQ = 965
N0.C1.D0.R0.S09: RdPtrOffsetTxDq: 08
N2.C2.D0.R1.S09: RdPtrOffsetTxDq: 06
N4.C1.D0.R1.S07: wrcmd2dqsstartlatency: 04
N6.C1.D0.R0.S02: Total Delay in PI ticks: TxDQ = 956
N0.C1.D0.R0.S10: RdPtrOffsetTxDq: 08
N2.C2.D0.R1.S09: RdPtrOffsetTxDqs: 07
N4.C1.D0.R1.S07: RdPtrOffsetTxDq: 05
N6.C1.D0.R0.S03: Total Delay in PI ticks: TxDQ = 940
N0.C1.D0.R0.S11: RdPtrOffsetTxDq: 08
N2.C2.D0.R1.S09: PiTxDqs: 41
N4.C1.D0.R1.S07: RdPtrOffsetTxDqs: 07
N6.C1.D0.R0.S04: Total Delay in PI ticks: TxDQ = 907
N0.C1.D0.R0.S12: RdPtrOffsetTxDq: 07
N2.C2.D0.R1.S10: wrcmd2dqsstartlatency: 04
N4.C1.D0.R1.S07: PiTxDqs: 24
N6.C1.D0.R0.S05: Total Delay in PI ticks: TxDQ = 920
N0.C1.D0.R0.S13: RdPtrOffsetTxDq: 07
N2.C2.D0.R1.S10: RdPtrOffsetTxDq: 05
N4.C1.D0.R1.S08: wrcmd2dqsstartlatency: 04
N6.C1.D0.R0.S06: Total Delay in PI ticks: TxDQ = 938
N0.C1.D0.R0.S14: RdPtrOffsetTxDq: 07
N2.C2.D0.R1.S10: RdPtrOffsetTxDqs: 07
N4.C1.D0.R1.S08: RdPtrOffsetTxDq: 05
N6.C1.D0.R0.S07: Total Delay in PI ticks: TxDQ = 949
N0.C1.D0.R0.S15: RdPtrOffsetTxDq: 07
N2.C2.D0.R1.S10: PiTxDqs: 28
N4.C1.D0.R1.S08: RdPtrOffsetTxDqs: 06
N6.C1.D0.R0.S08: Total Delay in PI ticks: TxDQ = 925
N0.C1.D0.R0.S16: RdPtrOffsetTxDq: 07
N2.C2.D0.R1.S11: wrcmd2dqsstartlatency: 04
N4.C1.D0.R1.S08: PiTxDqs: 57
N6.C1.D0.R0.S09: Total Delay in PI ticks: TxDQ = 981
N0.C1.D0.R0.S17: RdPtrOffsetTxDq: 07
N2.C2.D0.R1.S11: RdPtrOffsetTxDq: 05
N4.C1.D0.R1.S09: wrcmd2dqsstartlatency: 04
N6.C1.D0.R0.S10: Total Delay in PI ticks: TxDQ = 965
N0.C1.D0.R0.S00: Total Delay in PI ticks: TxDQ = 986
N2.C2.D0.R1.S11: RdPtrOffsetTxDqs: 07
N4.C1.D0.R1.S09: RdPtrOffsetTxDq: 06
N6.C1.D0.R0.S11: Total Delay in PI ticks: TxDQ = 957
N0.C1.D0.R0.S01: Total Delay in PI ticks: TxDQ = 965
N2.C2.D0.R1.S11: PiTxDqs: 17
N4.C1.D0.R1.S09: RdPtrOffsetTxDqs: 07
N6.C1.D0.R0.S12: Total Delay in PI ticks: TxDQ = 941
N0.C1.D0.R0.S02: Total Delay in PI ticks: TxDQ = 961
N2.C2.D0.R1.S12: wrcmd2dqsstartlatency: 04
N4.C1.D0.R1.S09: PiTxDqs: 50
N6.C1.D0.R0.S13: Total Delay in PI ticks: TxDQ = 907
N0.C1.D0.R0.S03: Total Delay in PI ticks: TxDQ = 941
N2.C2.D0.R1.S12: RdPtrOffsetTxDq: 05
N4.C1.D0.R1.S10: wrcmd2dqsstartlatency: 04
N6.C1.D0.R0.S14: Total Delay in PI ticks: TxDQ = 918
N0.C1.D0.R0.S04: Total Delay in PI ticks: TxDQ = 907
N2.C2.D0.R1.S12: RdPtrOffsetTxDqs: 07
N4.C1.D0.R1.S10: RdPtrOffsetTxDq: 06
N6.C1.D0.R0.S15: Total Delay in PI ticks: TxDQ = 936
N0.C1.D0.R0.S05: Total Delay in PI ticks: TxDQ = 922
N2.C2.D0.R1.S12: PiTxDqs: 01
N4.C1.D0.R1.S10: RdPtrOffsetTxDqs: 07
N6.C1.D0.R0.S16: Total Delay in PI ticks: TxDQ = 950
N0.C1.D0.R0.S06: Total Delay in PI ticks: TxDQ = 940
N2.C2.D0.R1.S13: wrcmd2dqsstartlatency: 04
N4.C1.D0.R1.S10: PiTxDqs: 38
N6.C1.D0.R0.S17: Total Delay in PI ticks: TxDQ = 922
N0.C1.D0.R0.S07: Total Delay in PI ticks: TxDQ = 955
N2.C2.D0.R1.S13: RdPtrOffsetTxDq: 04
N4.C1.D0.R1.S11: wrcmd2dqsstartlatency: 04
N6.C1.D0.R1.S00: wrcmd2dqsstartlatency: 04
N0.C1.D0.R0.S08: Total Delay in PI ticks: TxDQ = 922
N2.C2.D0.R1.S13: RdPtrOffsetTxDqs: 06
N4.C1.D0.R1.S11: RdPtrOffsetTxDq: 05
N6.C1.D0.R1.S00: RdPtrOffsetTxDq: 06
N0.C1.D0.R0.S09: Total Delay in PI ticks: TxDQ = 985
N2.C2.D0.R1.S13: PiTxDqs: 23
N4.C1.D0.R1.S11: RdPtrOffsetTxDqs: 07
N6.C1.D0.R1.S00: RdPtrOffsetTxDqs: 07
N0.C1.D0.R0.S10: Total Delay in PI ticks: TxDQ = 966
N2.C2.D0.R1.S14: wrcmd2dqsstartlatency: 04
N4.C1.D0.R1.S11: PiTxDqs: 27
N6.C1.D0.R1.S00: PiTxDqs: 48
N0.C1.D0.R0.S11: Total Delay in PI ticks: TxDQ = 962
N2.C2.D0.R1.S14: RdPtrOffsetTxDq: 05
N4.C1.D0.R1.S12: wrcmd2dqsstartlatency: 04
N6.C1.D0.R1.S01: wrcmd2dqsstartlatency: 04
N0.C1.D0.R0.S12: Total Delay in PI ticks: TxDQ = 942
N2.C2.D0.R1.S14: RdPtrOffsetTxDqs: 06
N4.C1.D0.R1.S12: RdPtrOffsetTxDq: 05
N6.C1.D0.R1.S01: RdPtrOffsetTxDq: 05
N0.C1.D0.R0.S13: Total Delay in PI ticks: TxDQ = 908
N2.C2.D0.R1.S14: PiTxDqs: 52
N4.C1.D0.R1.S12: RdPtrOffsetTxDqs: 07
N6.C1.D0.R1.S01: RdPtrOffsetTxDqs: 07
N0.C1.D0.R0.S14: Total Delay in PI ticks: TxDQ = 922
N2.C2.D0.R1.S15: wrcmd2dqsstartlatency: 04
N4.C1.D0.R1.S12: PiTxDqs: 14
N6.C1.D0.R1.S01: PiTxDqs: 29
N0.C1.D0.R0.S15: Total Delay in PI ticks: TxDQ = 938
N2.C2.D0.R1.S15: RdPtrOffsetTxDq: 05
N4.C1.D0.R1.S13: wrcmd2dqsstartlatency: 04
N6.C1.D0.R1.S02: wrcmd2dqsstartlatency: 04
N0.C1.D0.R0.S16: Total Delay in PI ticks: TxDQ = 954
N2.C2.D0.R1.S15: RdPtrOffsetTxDqs: 06
N4.C1.D0.R1.S13: RdPtrOffsetTxDq: 05
N6.C1.D0.R1.S02: RdPtrOffsetTxDq: 05
N0.C1.D0.R0.S17: Total Delay in PI ticks: TxDQ = 926
N2.C2.D0.R1.S15: PiTxDqs: 50
N4.C1.D0.R1.S13: RdPtrOffsetTxDqs: 06
N6.C1.D0.R1.S02: RdPtrOffsetTxDqs: 07
N0.C1.D0.R1.S00: wrcmd2dqsstartlatency: 04
N2.C2.D0.R1.S16: wrcmd2dqsstartlatency: 04
N4.C1.D0.R1.S13: PiTxDqs: 43
N6.C1.D0.R1.S02: PiTxDqs: 19
N0.C1.D0.R1.S00: RdPtrOffsetTxDq: 06
N2.C2.D0.R1.S16: RdPtrOffsetTxDq: 05
N4.C1.D0.R1.S14: wrcmd2dqsstartlatency: 04
N6.C1.D0.R1.S03: wrcmd2dqsstartlatency: 04
N0.C1.D0.R1.S00: RdPtrOffsetTxDqs: 07
N2.C2.D0.R1.S16: RdPtrOffsetTxDqs: 07
N4.C1.D0.R1.S14: RdPtrOffsetTxDq: 05
N6.C1.D0.R1.S03: RdPtrOffsetTxDq: 05
N0.C1.D0.R1.S00: PiTxDqs: 49
N2.C2.D0.R1.S16: PiTxDqs: 10
N4.C1.D0.R1.S14: RdPtrOffsetTxDqs: 06
N6.C1.D0.R1.S03: RdPtrOffsetTxDqs: 07
N0.C1.D0.R1.S01: wrcmd2dqsstartlatency: 04
N2.C2.D0.R1.S17: wrcmd2dqsstartlatency: 04
N4.C1.D0.R1.S14: PiTxDqs: 57
N6.C1.D0.R1.S03: PiTxDqs: 04
N0.C1.D0.R1.S01: RdPtrOffsetTxDq: 05
N2.C2.D0.R1.S17: RdPtrOffsetTxDq: 05
N4.C1.D0.R1.S15: wrcmd2dqsstartlatency: 04
N6.C1.D0.R1.S04: wrcmd2dqsstartlatency: 04
N0.C1.D0.R1.S01: RdPtrOffsetTxDqs: 07
N2.C2.D0.R1.S17: RdPtrOffsetTxDqs: 06
N4.C1.D0.R1.S15: RdPtrOffsetTxDq: 05
N6.C1.D0.R1.S04: RdPtrOffsetTxDq: 05
N0.C1.D0.R1.S01: PiTxDqs: 32
N2.C2.D0.R1.S17: PiTxDqs: 41
N4.C1.D0.R1.S15: RdPtrOffsetTxDqs: 07
N6.C1.D0.R1.S04: RdPtrOffsetTxDqs: 06
N0.C1.D0.R1.S02: wrcmd2dqsstartlatency: 04
N2.C2.D0.R1.S00: RdPtrOffsetTxDq: 07
N4.C1.D0.R1.S15: PiTxDqs: 08
N6.C1.D0.R1.S04: PiTxDqs: 38
N0.C1.D0.R1.S02: RdPtrOffsetTxDq: 05
N2.C2.D0.R1.S01: RdPtrOffsetTxDq: 06
N4.C1.D0.R1.S16: wrcmd2dqsstartlatency: 04
N6.C1.D0.R1.S05: wrcmd2dqsstartlatency: 04
N0.C1.D0.R1.S02: RdPtrOffsetTxDqs: 07
N2.C2.D0.R1.S02: RdPtrOffsetTxDq: 06
N4.C1.D0.R1.S16: RdPtrOffsetTxDq: 05
N6.C1.D0.R1.S05: RdPtrOffsetTxDq: 05
N0.C1.D0.R1.S02: PiTxDqs: 25
N2.C2.D0.R1.S03: RdPtrOffsetTxDq: 06
N4.C1.D0.R1.S16: RdPtrOffsetTxDqs: 07
N6.C1.D0.R1.S05: RdPtrOffsetTxDqs: 06
N0.C1.D0.R1.S03: wrcmd2dqsstartlatency: 04
N2.C2.D0.R1.S04: RdPtrOffsetTxDq: 05
N4.C1.D0.R1.S16: PiTxDqs: 23
N6.C1.D0.R1.S05: PiTxDqs: 50
N0.C1.D0.R1.S03: RdPtrOffsetTxDq: 05
N2.C2.D0.R1.S05: RdPtrOffsetTxDq: 06
N4.C1.D0.R1.S17: wrcmd2dqsstartlatency: 04
N6.C1.D0.R1.S06: wrcmd2dqsstartlatency: 04
N0.C1.D0.R1.S03: RdPtrOffsetTxDqs: 07
N2.C2.D0.R1.S06: RdPtrOffsetTxDq: 06
N4.C1.D0.R1.S17: RdPtrOffsetTxDq: 05
N6.C1.D0.R1.S06: RdPtrOffsetTxDq: 05
N0.C1.D0.R1.S03: PiTxDqs: 09
N2.C2.D0.R1.S07: RdPtrOffsetTxDq: 06
N4.C1.D0.R1.S17: RdPtrOffsetTxDqs: 06
N6.C1.D0.R1.S06: RdPtrOffsetTxDqs: 06
N0.C1.D0.R1.S04: wrcmd2dqsstartlatency: 04
N2.C2.D0.R1.S08: RdPtrOffsetTxDq: 06
N4.C1.D0.R1.S17: PiTxDqs: 57
N6.C1.D0.R1.S06: PiTxDqs: 63
N0.C1.D0.R1.S04: RdPtrOffsetTxDq: 05
N2.C2.D0.R1.S09: RdPtrOffsetTxDq: 07
N4.C1.D0.R1.S00: RdPtrOffsetTxDq: 07
N6.C1.D0.R1.S07: wrcmd2dqsstartlatency: 04
N0.C1.D0.R1.S04: RdPtrOffsetTxDqs: 06
N2.C2.D0.R1.S10: RdPtrOffsetTxDq: 06
N4.C1.D0.R1.S01: RdPtrOffsetTxDq: 07
N6.C1.D0.R1.S07: RdPtrOffsetTxDq: 05
N0.C1.D0.R1.S04: PiTxDqs: 38
N2.C2.D0.R1.S11: RdPtrOffsetTxDq: 06
N4.C1.D0.R1.S02: RdPtrOffsetTxDq: 06
N6.C1.D0.R1.S07: RdPtrOffsetTxDqs: 07
N0.C1.D0.R1.S05: wrcmd2dqsstartlatency: 04
N2.C2.D0.R1.S12: RdPtrOffsetTxDq: 06
N4.C1.D0.R1.S03: RdPtrOffsetTxDq: 06
N6.C1.D0.R1.S07: PiTxDqs: 17
N0.C1.D0.R1.S05: RdPtrOffsetTxDq: 05
N2.C2.D0.R1.S13: RdPtrOffsetTxDq: 05
N4.C1.D0.R1.S04: RdPtrOffsetTxDq: 06
N6.C1.D0.R1.S08: wrcmd2dqsstartlatency: 04
N0.C1.D0.R1.S05: RdPtrOffsetTxDqs: 06
N2.C2.D0.R1.S14: RdPtrOffsetTxDq: 06
N4.C1.D0.R1.S05: RdPtrOffsetTxDq: 06
N6.C1.D0.R1.S08: RdPtrOffsetTxDq: 05
N0.C1.D0.R1.S05: PiTxDqs: 53
N2.C2.D0.R1.S15: RdPtrOffsetTxDq: 06
N4.C1.D0.R1.S06: RdPtrOffsetTxDq: 06
N6.C1.D0.R1.S08: RdPtrOffsetTxDqs: 06
N0.C1.D0.R1.S06: wrcmd2dqsstartlatency: 04
N2.C2.D0.R1.S16: RdPtrOffsetTxDq: 06
N4.C1.D0.R1.S07: RdPtrOffsetTxDq: 06
N6.C1.D0.R1.S08: PiTxDqs: 51
N0.C1.D0.R1.S06: RdPtrOffsetTxDq: 05
N2.C2.D0.R1.S17: RdPtrOffsetTxDq: 06
N4.C1.D0.R1.S08: RdPtrOffsetTxDq: 06
N6.C1.D0.R1.S09: wrcmd2dqsstartlatency: 04
N0.C1.D0.R1.S06: RdPtrOffsetTxDqs: 07
N2.C2.D0.R1.S00: RdPtrOffsetTxDq: 08
N4.C1.D0.R1.S09: RdPtrOffsetTxDq: 07
N6.C1.D0.R1.S09: RdPtrOffsetTxDq: 06
N0.C1.D0.R1.S06: PiTxDqs: 03
N2.C2.D0.R1.S01: RdPtrOffsetTxDq: 07
N4.C1.D0.R1.S10: RdPtrOffsetTxDq: 07
N6.C1.D0.R1.S09: RdPtrOffsetTxDqs: 07
N0.C1.D0.R1.S07: wrcmd2dqsstartlatency: 04
N2.C2.D0.R1.S02: RdPtrOffsetTxDq: 07
N4.C1.D0.R1.S11: RdPtrOffsetTxDq: 06
N6.C1.D0.R1.S09: PiTxDqs: 45
N0.C1.D0.R1.S07: RdPtrOffsetTxDq: 05
N2.C2.D0.R1.S03: RdPtrOffsetTxDq: 07
N4.C1.D0.R1.S12: RdPtrOffsetTxDq: 06
N6.C1.D0.R1.S10: wrcmd2dqsstartlatency: 04
N0.C1.D0.R1.S07: RdPtrOffsetTxDqs: 07
N2.C2.D0.R1.S04: RdPtrOffsetTxDq: 06
N4.C1.D0.R1.S13: RdPtrOffsetTxDq: 06
N6.C1.D0.R1.S10: RdPtrOffsetTxDq: 05
N0.C1.D0.R1.S07: PiTxDqs: 21
N2.C2.D0.R1.S05: RdPtrOffsetTxDq: 07
N4.C1.D0.R1.S14: RdPtrOffsetTxDq: 06
N6.C1.D0.R1.S10: RdPtrOffsetTxDqs: 07
N0.C1.D0.R1.S08: wrcmd2dqsstartlatency: 04
N2.C2.D0.R1.S06: RdPtrOffsetTxDq: 07
N4.C1.D0.R1.S15: RdPtrOffsetTxDq: 06
N6.C1.D0.R1.S10: PiTxDqs: 29
N0.C1.D0.R1.S08: RdPtrOffsetTxDq: 05
N2.C2.D0.R1.S07: RdPtrOffsetTxDq: 07
N4.C1.D0.R1.S16: RdPtrOffsetTxDq: 06
N6.C1.D0.R1.S11: wrcmd2dqsstartlatency: 04
N0.C1.D0.R1.S08: RdPtrOffsetTxDqs: 06
N2.C2.D0.R1.S08: RdPtrOffsetTxDq: 07
N4.C1.D0.R1.S17: RdPtrOffsetTxDq: 06
N6.C1.D0.R1.S11: RdPtrOffsetTxDq: 05
N0.C1.D0.R1.S08: PiTxDqs: 54
N2.C2.D0.R1.S09: RdPtrOffsetTxDq: 08
N4.C1.D0.R1.S00: RdPtrOffsetTxDq: 08
N6.C1.D0.R1.S11: RdPtrOffsetTxDqs: 07
N0.C1.D0.R1.S09: wrcmd2dqsstartlatency: 04
N2.C2.D0.R1.S10: RdPtrOffsetTxDq: 07
N4.C1.D0.R1.S01: RdPtrOffsetTxDq: 08
N6.C1.D0.R1.S11: PiTxDqs: 21
N0.C1.D0.R1.S09: RdPtrOffsetTxDq: 06
N2.C2.D0.R1.S11: RdPtrOffsetTxDq: 07
N4.C1.D0.R1.S02: RdPtrOffsetTxDq: 07
N6.C1.D0.R1.S12: wrcmd2dqsstartlatency: 04
N0.C1.D0.R1.S09: RdPtrOffsetTxDqs: 07
N2.C2.D0.R1.S12: RdPtrOffsetTxDq: 07
N4.C1.D0.R1.S03: RdPtrOffsetTxDq: 07
N6.C1.D0.R1.S12: RdPtrOffsetTxDq: 05
N0.C1.D0.R1.S09: PiTxDqs: 48
N2.C2.D0.R1.S13: RdPtrOffsetTxDq: 06
N4.C1.D0.R1.S04: RdPtrOffsetTxDq: 07
N6.C1.D0.R1.S12: RdPtrOffsetTxDqs: 07
N0.C1.D0.R1.S10: wrcmd2dqsstartlatency: 04
N2.C2.D0.R1.S14: RdPtrOffsetTxDq: 07
N4.C1.D0.R1.S05: RdPtrOffsetTxDq: 07
N6.C1.D0.R1.S12: PiTxDqs: 05
N0.C1.D0.R1.S10: RdPtrOffsetTxDq: 05
N2.C2.D0.R1.S15: RdPtrOffsetTxDq: 07
N4.C1.D0.R1.S06: RdPtrOffsetTxDq: 07
N6.C1.D0.R1.S13: wrcmd2dqsstartlatency: 04
N0.C1.D0.R1.S10: RdPtrOffsetTxDqs: 07
N2.C2.D0.R1.S16: RdPtrOffsetTxDq: 07
N4.C1.D0.R1.S07: RdPtrOffsetTxDq: 07
N6.C1.D0.R1.S13: RdPtrOffsetTxDq: 05
N0.C1.D0.R1.S10: PiTxDqs: 33
N2.C2.D0.R1.S17: RdPtrOffsetTxDq: 07
N4.C1.D0.R1.S08: RdPtrOffsetTxDq: 07
N6.C1.D0.R1.S13: RdPtrOffsetTxDqs: 06
N0.C1.D0.R1.S11: wrcmd2dqsstartlatency: 04
N2.C2.D0.R1.S00: Total Delay in PI ticks: TxDQ = 972
N4.C1.D0.R1.S09: RdPtrOffsetTxDq: 08
N6.C1.D0.R1.S13: PiTxDqs: 35
N0.C1.D0.R1.S11: RdPtrOffsetTxDq: 05
N2.C2.D0.R1.S01: Total Delay in PI ticks: TxDQ = 956
N4.C1.D0.R1.S10: RdPtrOffsetTxDq: 08
N6.C1.D0.R1.S14: wrcmd2dqsstartlatency: 04
N0.C1.D0.R1.S11: RdPtrOffsetTxDqs: 07
N2.C2.D0.R1.S02: Total Delay in PI ticks: TxDQ = 948
N4.C1.D0.R1.S11: RdPtrOffsetTxDq: 07
N6.C1.D0.R1.S14: RdPtrOffsetTxDq: 05
N0.C1.D0.R1.S11: PiTxDqs: 25
N2.C2.D0.R1.S03: Total Delay in PI ticks: TxDQ = 926
N4.C1.D0.R1.S12: RdPtrOffsetTxDq: 07
N6.C1.D0.R1.S14: RdPtrOffsetTxDqs: 06
N0.C1.D0.R1.S12: wrcmd2dqsstartlatency: 04
N2.C2.D0.R1.S04: Total Delay in PI ticks: TxDQ = 889
N4.C1.D0.R1.S13: RdPtrOffsetTxDq: 07
N6.C1.D0.R1.S14: PiTxDqs: 48
N0.C1.D0.R1.S12: RdPtrOffsetTxDq: 05
N2.C2.D0.R1.S05: Total Delay in PI ticks: TxDQ = 914
N4.C1.D0.R1.S14: RdPtrOffsetTxDq: 07
N6.C1.D0.R1.S15: wrcmd2dqsstartlatency: 04
N0.C1.D0.R1.S12: RdPtrOffsetTxDqs: 07
N2.C2.D0.R1.S06: Total Delay in PI ticks: TxDQ = 914
N4.C1.D0.R1.S15: RdPtrOffsetTxDq: 07
N6.C1.D0.R1.S15: RdPtrOffsetTxDq: 05
N0.C1.D0.R1.S12: PiTxDqs: 10
N2.C2.D0.R1.S07: Total Delay in PI ticks: TxDQ = 936
N4.C1.D0.R1.S16: RdPtrOffsetTxDq: 07
N6.C1.D0.R1.S15: RdPtrOffsetTxDqs: 06
N0.C1.D0.R1.S13: wrcmd2dqsstartlatency: 04
N2.C2.D0.R1.S08: Total Delay in PI ticks: TxDQ = 905
N4.C1.D0.R1.S17: RdPtrOffsetTxDq: 07
N6.C1.D0.R1.S15: PiTxDqs: 63
N0.C1.D0.R1.S13: RdPtrOffsetTxDq: 05
N2.C2.D0.R1.S09: Total Delay in PI ticks: TxDQ = 968
N4.C1.D0.R1.S00: Total Delay in PI ticks: TxDQ = 979
N6.C1.D0.R1.S16: wrcmd2dqsstartlatency: 04
N0.C1.D0.R1.S13: RdPtrOffsetTxDqs: 06
N2.C2.D0.R1.S10: Total Delay in PI ticks: TxDQ = 956
N4.C1.D0.R1.S01: Total Delay in PI ticks: TxDQ = 964
N6.C1.D0.R1.S16: RdPtrOffsetTxDq: 05
N0.C1.D0.R1.S13: PiTxDqs: 40
N2.C2.D0.R1.S11: Total Delay in PI ticks: TxDQ = 947
N4.C1.D0.R1.S02: Total Delay in PI ticks: TxDQ = 954
N6.C1.D0.R1.S16: RdPtrOffsetTxDqs: 07
N0.C1.D0.R1.S14: wrcmd2dqsstartlatency: 04
N2.C2.D0.R1.S12: Total Delay in PI ticks: TxDQ = 929
N4.C1.D0.R1.S03: Total Delay in PI ticks: TxDQ = 939
N6.C1.D0.R1.S16: PiTxDqs: 18
N0.C1.D0.R1.S14: RdPtrOffsetTxDq: 05
N2.C2.D0.R1.S13: Total Delay in PI ticks: TxDQ = 888
N4.C1.D0.R1.S04: Total Delay in PI ticks: TxDQ = 906
N6.C1.D0.R1.S17: wrcmd2dqsstartlatency: 04
N0.C1.D0.R1.S14: RdPtrOffsetTxDqs: 06
N2.C2.D0.R1.S14: Total Delay in PI ticks: TxDQ = 915
N4.C1.D0.R1.S05: Total Delay in PI ticks: TxDQ = 917
N6.C1.D0.R1.S17: RdPtrOffsetTxDq: 05
N0.C1.D0.R1.S14: PiTxDqs: 55
N2.C2.D0.R1.S15: Total Delay in PI ticks: TxDQ = 914
N4.C1.D0.R1.S06: Total Delay in PI ticks: TxDQ = 931
N6.C1.D0.R1.S17: RdPtrOffsetTxDqs: 06
N0.C1.D0.R1.S15: wrcmd2dqsstartlatency: 04
N2.C2.D0.R1.S16: Total Delay in PI ticks: TxDQ = 937
N4.C1.D0.R1.S07: Total Delay in PI ticks: TxDQ = 947
N6.C1.D0.R1.S17: PiTxDqs: 49
N0.C1.D0.R1.S15: RdPtrOffsetTxDq: 05
N2.C2.D0.R1.S17: Total Delay in PI ticks: TxDQ = 905
N4.C1.D0.R1.S08: Total Delay in PI ticks: TxDQ = 920
N6.C1.D0.R1.S00: RdPtrOffsetTxDq: 07
N0.C1.D0.R1.S15: RdPtrOffsetTxDqs: 07
N2.C2.D1.R0.S00: wrcmd2dqsstartlatency: 04
N4.C1.D0.R1.S09: Total Delay in PI ticks: TxDQ = 976
N6.C1.D0.R1.S01: RdPtrOffsetTxDq: 06
N0.C1.D0.R1.S15: PiTxDqs: 02
N2.C2.D1.R0.S00: RdPtrOffsetTxDq: 06
N4.C1.D0.R1.S10: Total Delay in PI ticks: TxDQ = 965
N6.C1.D0.R1.S02: RdPtrOffsetTxDq: 06
N0.C1.D0.R1.S16: wrcmd2dqsstartlatency: 04
N2.C2.D1.R0.S00: RdPtrOffsetTxDqs: 07
N4.C1.D0.R1.S11: Total Delay in PI ticks: TxDQ = 955
N6.C1.D0.R1.S03: RdPtrOffsetTxDq: 06
N0.C1.D0.R1.S16: RdPtrOffsetTxDq: 05
N2.C2.D1.R0.S00: PiTxDqs: 50
N4.C1.D0.R1.S12: Total Delay in PI ticks: TxDQ = 942
N6.C1.D0.R1.S04: RdPtrOffsetTxDq: 06
N0.C1.D0.R1.S16: RdPtrOffsetTxDqs: 07
N2.C2.D1.R0.S01: wrcmd2dqsstartlatency: 04
N4.C1.D0.R1.S13: Total Delay in PI ticks: TxDQ = 905
N6.C1.D0.R1.S05: RdPtrOffsetTxDq: 06
N0.C1.D0.R1.S16: PiTxDqs: 23
N2.C2.D1.R0.S01: RdPtrOffsetTxDq: 06
N4.C1.D0.R1.S14: Total Delay in PI ticks: TxDQ = 919
N6.C1.D0.R1.S06: RdPtrOffsetTxDq: 06
N0.C1.D0.R1.S17: wrcmd2dqsstartlatency: 04
N2.C2.D1.R0.S01: RdPtrOffsetTxDqs: 07
N4.C1.D0.R1.S15: Total Delay in PI ticks: TxDQ = 936
N6.C1.D0.R1.S07: RdPtrOffsetTxDq: 06
N0.C1.D0.R1.S17: RdPtrOffsetTxDq: 05
N2.C2.D1.R0.S01: PiTxDqs: 38
N4.C1.D0.R1.S16: Total Delay in PI ticks: TxDQ = 950
N6.C1.D0.R1.S08: RdPtrOffsetTxDq: 06
N0.C1.D0.R1.S17: RdPtrOffsetTxDqs: 06
N2.C2.D1.R0.S02: wrcmd2dqsstartlatency: 04
N4.C1.D0.R1.S17: Total Delay in PI ticks: TxDQ = 920
N6.C1.D0.R1.S09: RdPtrOffsetTxDq: 07
N0.C1.D0.R1.S17: PiTxDqs: 53
N2.C2.D1.R0.S02: RdPtrOffsetTxDq: 05
N4.C1.D1.R0.S00: wrcmd2dqsstartlatency: 04
N6.C1.D0.R1.S10: RdPtrOffsetTxDq: 06
N0.C1.D0.R1.S00: RdPtrOffsetTxDq: 07
N2.C2.D1.R0.S02: RdPtrOffsetTxDqs: 07
N4.C1.D1.R0.S00: RdPtrOffsetTxDq: 06
N6.C1.D0.R1.S11: RdPtrOffsetTxDq: 06
N0.C1.D0.R1.S01: RdPtrOffsetTxDq: 06
N2.C2.D1.R0.S02: PiTxDqs: 26
N4.C1.D1.R0.S00: RdPtrOffsetTxDqs: 07
N6.C1.D0.R1.S12: RdPtrOffsetTxDq: 06
N0.C1.D0.R1.S02: RdPtrOffsetTxDq: 06
N2.C2.D1.R0.S03: wrcmd2dqsstartlatency: 04
N4.C1.D1.R0.S00: PiTxDqs: 61
N6.C1.D0.R1.S13: RdPtrOffsetTxDq: 06
N0.C1.D0.R1.S03: RdPtrOffsetTxDq: 06
N2.C2.D1.R0.S03: RdPtrOffsetTxDq: 05
N4.C1.D1.R0.S01: wrcmd2dqsstartlatency: 04
N6.C1.D0.R1.S14: RdPtrOffsetTxDq: 06
N0.C1.D0.R1.S04: RdPtrOffsetTxDq: 06
N2.C2.D1.R0.S03: RdPtrOffsetTxDqs: 07
N4.C1.D1.R0.S01: RdPtrOffsetTxDq: 06
N6.C1.D0.R1.S15: RdPtrOffsetTxDq: 06
N0.C1.D0.R1.S05: RdPtrOffsetTxDq: 06
N2.C2.D1.R0.S03: PiTxDqs: 13
N4.C1.D1.R0.S01: RdPtrOffsetTxDqs: 07
N6.C1.D0.R1.S16: RdPtrOffsetTxDq: 06
N0.C1.D0.R1.S06: RdPtrOffsetTxDq: 06
N2.C2.D1.R0.S04: wrcmd2dqsstartlatency: 04
N4.C1.D1.R0.S01: PiTxDqs: 45
N6.C1.D0.R1.S17: RdPtrOffsetTxDq: 06
N0.C1.D0.R1.S07: RdPtrOffsetTxDq: 06
N2.C2.D1.R0.S04: RdPtrOffsetTxDq: 04
N4.C1.D1.R0.S02: wrcmd2dqsstartlatency: 04
N6.C1.D0.R1.S00: RdPtrOffsetTxDq: 08
N0.C1.D0.R1.S08: RdPtrOffsetTxDq: 06
N2.C2.D1.R0.S04: RdPtrOffsetTxDqs: 06
N4.C1.D1.R0.S02: RdPtrOffsetTxDq: 05
N6.C1.D0.R1.S01: RdPtrOffsetTxDq: 07
N0.C1.D0.R1.S09: RdPtrOffsetTxDq: 07
N2.C2.D1.R0.S04: PiTxDqs: 34
N4.C1.D1.R0.S02: RdPtrOffsetTxDqs: 07
N6.C1.D0.R1.S02: RdPtrOffsetTxDq: 07
N0.C1.D0.R1.S10: RdPtrOffsetTxDq: 06
N2.C2.D1.R0.S05: wrcmd2dqsstartlatency: 04
N4.C1.D1.R0.S02: PiTxDqs: 35
N6.C1.D0.R1.S03: RdPtrOffsetTxDq: 07
N0.C1.D0.R1.S11: RdPtrOffsetTxDq: 06
N2.C2.D1.R0.S05: RdPtrOffsetTxDq: 05
N4.C1.D1.R0.S03: wrcmd2dqsstartlatency: 04
N6.C1.D0.R1.S04: RdPtrOffsetTxDq: 07
N0.C1.D0.R1.S12: RdPtrOffsetTxDq: 06
N2.C2.D1.R0.S05: RdPtrOffsetTxDqs: 07
N4.C1.D1.R0.S03: RdPtrOffsetTxDq: 05
N6.C1.D0.R1.S05: RdPtrOffsetTxDq: 07
N0.C1.D0.R1.S13: RdPtrOffsetTxDq: 06
N2.C2.D1.R0.S05: PiTxDqs: 00
N4.C1.D1.R0.S03: RdPtrOffsetTxDqs: 07
N6.C1.D0.R1.S06: RdPtrOffsetTxDq: 07
N0.C1.D0.R1.S14: RdPtrOffsetTxDq: 06
N2.C2.D1.R0.S06: wrcmd2dqsstartlatency: 04
N4.C1.D1.R0.S03: PiTxDqs: 19
N6.C1.D0.R1.S07: RdPtrOffsetTxDq: 07
N0.C1.D0.R1.S15: RdPtrOffsetTxDq: 06
N2.C2.D1.R0.S06: RdPtrOffsetTxDq: 05
N4.C1.D1.R0.S04: wrcmd2dqsstartlatency: 04
N6.C1.D0.R1.S08: RdPtrOffsetTxDq: 07
N0.C1.D0.R1.S16: RdPtrOffsetTxDq: 06
N2.C2.D1.R0.S06: RdPtrOffsetTxDqs: 06
N4.C1.D1.R0.S04: RdPtrOffsetTxDq: 05
N6.C1.D0.R1.S09: RdPtrOffsetTxDq: 08
N0.C1.D0.R1.S17: RdPtrOffsetTxDq: 06
N2.C2.D1.R0.S06: PiTxDqs: 61
N4.C1.D1.R0.S04: RdPtrOffsetTxDqs: 06
N6.C1.D0.R1.S10: RdPtrOffsetTxDq: 07
N0.C1.D0.R1.S00: RdPtrOffsetTxDq: 08
N2.C2.D1.R0.S07: wrcmd2dqsstartlatency: 04
N4.C1.D1.R0.S04: PiTxDqs: 49
N6.C1.D0.R1.S11: RdPtrOffsetTxDq: 07
N0.C1.D0.R1.S01: RdPtrOffsetTxDq: 07
N2.C2.D1.R0.S07: RdPtrOffsetTxDq: 05
N4.C1.D1.R0.S05: wrcmd2dqsstartlatency: 04
N6.C1.D0.R1.S12: RdPtrOffsetTxDq: 07
N0.C1.D0.R1.S02: RdPtrOffsetTxDq: 07
N2.C2.D1.R0.S07: RdPtrOffsetTxDqs: 07
N4.C1.D1.R0.S05: RdPtrOffsetTxDq: 05
N6.C1.D0.R1.S13: RdPtrOffsetTxDq: 07
N0.C1.D0.R1.S03: RdPtrOffsetTxDq: 07
N2.C2.D1.R0.S07: PiTxDqs: 19
N4.C1.D1.R0.S05: RdPtrOffsetTxDqs: 06
N6.C1.D0.R1.S14: RdPtrOffsetTxDq: 07
N0.C1.D0.R1.S04: RdPtrOffsetTxDq: 07
N2.C2.D1.R0.S08: wrcmd2dqsstartlatency: 04
N4.C1.D1.R0.S05: PiTxDqs: 62
N6.C1.D0.R1.S15: RdPtrOffsetTxDq: 07
N0.C1.D0.R1.S05: RdPtrOffsetTxDq: 07
N2.C2.D1.R0.S08: RdPtrOffsetTxDq: 05
N4.C1.D1.R0.S06: wrcmd2dqsstartlatency: 04
N6.C1.D0.R1.S16: RdPtrOffsetTxDq: 07
N0.C1.D0.R1.S06: RdPtrOffsetTxDq: 07
N2.C2.D1.R0.S08: RdPtrOffsetTxDqs: 06
N4.C1.D1.R0.S06: RdPtrOffsetTxDq: 05
N6.C1.D0.R1.S17: RdPtrOffsetTxDq: 07
N0.C1.D0.R1.S07: RdPtrOffsetTxDq: 07
N2.C2.D1.R0.S08: PiTxDqs: 49
N4.C1.D1.R0.S06: RdPtrOffsetTxDqs: 07
N6.C1.D0.R1.S00: Total Delay in PI ticks: TxDQ = 975
N0.C1.D0.R1.S08: RdPtrOffsetTxDq: 07
N2.C2.D1.R0.S09: wrcmd2dqsstartlatency: 04
N4.C1.D1.R0.S06: PiTxDqs: 13
N6.C1.D0.R1.S01: Total Delay in PI ticks: TxDQ = 957
N0.C1.D0.R1.S09: RdPtrOffsetTxDq: 08
N2.C2.D1.R0.S09: RdPtrOffsetTxDq: 06
N4.C1.D1.R0.S07: wrcmd2dqsstartlatency: 04
N6.C1.D0.R1.S02: Total Delay in PI ticks: TxDQ = 948
N0.C1.D0.R1.S10: RdPtrOffsetTxDq: 07
N2.C2.D1.R0.S09: RdPtrOffsetTxDqs: 07
N4.C1.D1.R0.S07: RdPtrOffsetTxDq: 05
N6.C1.D0.R1.S03: Total Delay in PI ticks: TxDQ = 933
N0.C1.D0.R1.S11: RdPtrOffsetTxDq: 07
N2.C2.D1.R0.S09: PiTxDqs: 50
N4.C1.D1.R0.S07: RdPtrOffsetTxDqs: 07
N6.C1.D0.R1.S04: Total Delay in PI ticks: TxDQ = 902
N0.C1.D0.R1.S12: RdPtrOffsetTxDq: 07
N2.C2.D1.R0.S10: wrcmd2dqsstartlatency: 04
N4.C1.D1.R0.S07: PiTxDqs: 28
N6.C1.D0.R1.S05: Total Delay in PI ticks: TxDQ = 913
N0.C1.D0.R1.S13: RdPtrOffsetTxDq: 07
N2.C2.D1.R0.S10: RdPtrOffsetTxDq: 06
N4.C1.D1.R0.S08: wrcmd2dqsstartlatency: 04
N6.C1.D0.R1.S06: Total Delay in PI ticks: TxDQ = 929
N0.C1.D0.R1.S14: RdPtrOffsetTxDq: 07
N2.C2.D1.R0.S10: RdPtrOffsetTxDqs: 07
N4.C1.D1.R0.S08: RdPtrOffsetTxDq: 05
N6.C1.D0.R1.S07: Total Delay in PI ticks: TxDQ = 943
N0.C1.D0.R1.S15: RdPtrOffsetTxDq: 07
N2.C2.D1.R0.S10: PiTxDqs: 38
N4.C1.D1.R0.S08: RdPtrOffsetTxDqs: 06
N6.C1.D0.R1.S08: Total Delay in PI ticks: TxDQ = 915
N0.C1.D0.R1.S16: RdPtrOffsetTxDq: 07
N2.C2.D1.R0.S11: wrcmd2dqsstartlatency: 04
N4.C1.D1.R0.S08: PiTxDqs: 62
N6.C1.D0.R1.S09: Total Delay in PI ticks: TxDQ = 973
N0.C1.D0.R1.S17: RdPtrOffsetTxDq: 07
N2.C2.D1.R0.S11: RdPtrOffsetTxDq: 05
N4.C1.D1.R0.S09: wrcmd2dqsstartlatency: 04
N6.C1.D0.R1.S10: Total Delay in PI ticks: TxDQ = 958
N0.C1.D0.R1.S00: Total Delay in PI ticks: TxDQ = 978
N2.C2.D1.R0.S11: RdPtrOffsetTxDqs: 07
N4.C1.D1.R0.S09: RdPtrOffsetTxDq: 06
N6.C1.D0.R1.S11: Total Delay in PI ticks: TxDQ = 949
N0.C1.D0.R1.S01: Total Delay in PI ticks: TxDQ = 959
N2.C2.D1.R0.S11: PiTxDqs: 26
N4.C1.D1.R0.S09: RdPtrOffsetTxDqs: 07
N6.C1.D0.R1.S12: Total Delay in PI ticks: TxDQ = 934
N0.C1.D0.R1.S02: Total Delay in PI ticks: TxDQ = 950
N2.C2.D1.R0.S12: wrcmd2dqsstartlatency: 04
N4.C1.D1.R0.S09: PiTxDqs: 59
N6.C1.D0.R1.S13: Total Delay in PI ticks: TxDQ = 901
N0.C1.D0.R1.S03: Total Delay in PI ticks: TxDQ = 937
N2.C2.D1.R0.S12: RdPtrOffsetTxDq: 05
N4.C1.D1.R0.S10: wrcmd2dqsstartlatency: 04
N6.C1.D0.R1.S14: Total Delay in PI ticks: TxDQ = 912
N0.C1.D0.R1.S04: Total Delay in PI ticks: TxDQ = 902
N2.C2.D1.R0.S12: RdPtrOffsetTxDqs: 07
N4.C1.D1.R0.S10: RdPtrOffsetTxDq: 06
N6.C1.D0.R1.S15: Total Delay in PI ticks: TxDQ = 930
N0.C1.D0.R1.S05: Total Delay in PI ticks: TxDQ = 915
N2.C2.D1.R0.S12: PiTxDqs: 12
N4.C1.D1.R0.S10: RdPtrOffsetTxDqs: 07
N6.C1.D0.R1.S16: Total Delay in PI ticks: TxDQ = 946
N0.C1.D0.R1.S06: Total Delay in PI ticks: TxDQ = 930
N2.C2.D1.R0.S13: wrcmd2dqsstartlatency: 04
N4.C1.D1.R0.S10: PiTxDqs: 43
N6.C1.D0.R1.S17: Total Delay in PI ticks: TxDQ = 913
N0.C1.D0.R1.S07: Total Delay in PI ticks: TxDQ = 947
N2.C2.D1.R0.S13: RdPtrOffsetTxDq: 05
N4.C1.D1.R0.S11: wrcmd2dqsstartlatency: 04
N6.C1.D1.R0.S00: wrcmd2dqsstartlatency: 04
N0.C1.D0.R1.S08: Total Delay in PI ticks: TxDQ = 917
N2.C2.D1.R0.S13: RdPtrOffsetTxDqs: 06
N4.C1.D1.R0.S11: RdPtrOffsetTxDq: 05
N6.C1.D1.R0.S00: RdPtrOffsetTxDq: 06
N0.C1.D0.R1.S09: Total Delay in PI ticks: TxDQ = 974
N2.C2.D1.R0.S13: PiTxDqs: 36
N4.C1.D1.R0.S11: RdPtrOffsetTxDqs: 07
N6.C1.D1.R0.S00: RdPtrOffsetTxDqs: 07
N0.C1.D0.R1.S10: Total Delay in PI ticks: TxDQ = 960
N2.C2.D1.R0.S14: wrcmd2dqsstartlatency: 04
N4.C1.D1.R0.S11: PiTxDqs: 34
N6.C1.D1.R0.S00: PiTxDqs: 58
N0.C1.D0.R1.S11: Total Delay in PI ticks: TxDQ = 952
N2.C2.D1.R0.S14: RdPtrOffsetTxDq: 05
N4.C1.D1.R0.S12: wrcmd2dqsstartlatency: 04
N6.C1.D1.R0.S01: wrcmd2dqsstartlatency: 04
N0.C1.D0.R1.S12: Total Delay in PI ticks: TxDQ = 938
N2.C2.D1.R0.S14: RdPtrOffsetTxDqs: 06
N4.C1.D1.R0.S12: RdPtrOffsetTxDq: 05
N6.C1.D1.R0.S01: RdPtrOffsetTxDq: 06
N0.C1.D0.R1.S13: Total Delay in PI ticks: TxDQ = 902
N2.C2.D1.R0.S14: PiTxDqs: 63
N4.C1.D1.R0.S12: RdPtrOffsetTxDqs: 07
N6.C1.D1.R0.S01: RdPtrOffsetTxDqs: 07
N0.C1.D0.R1.S14: Total Delay in PI ticks: TxDQ = 917
N2.C2.D1.R0.S15: wrcmd2dqsstartlatency: 04
N4.C1.D1.R0.S12: PiTxDqs: 19
N6.C1.D1.R0.S01: PiTxDqs: 42
N0.C1.D0.R1.S15: Total Delay in PI ticks: TxDQ = 931
N2.C2.D1.R0.S15: RdPtrOffsetTxDq: 05
N4.C1.D1.R0.S13: wrcmd2dqsstartlatency: 04
N6.C1.D1.R0.S02: wrcmd2dqsstartlatency: 04
N0.C1.D0.R1.S16: Total Delay in PI ticks: TxDQ = 949
N2.C2.D1.R0.S15: RdPtrOffsetTxDqs: 06
N4.C1.D1.R0.S13: RdPtrOffsetTxDq: 05
N6.C1.D1.R0.S02: RdPtrOffsetTxDq: 05
N0.C1.D0.R1.S17: Total Delay in PI ticks: TxDQ = 918
N2.C2.D1.R0.S15: PiTxDqs: 61
N4.C1.D1.R0.S13: RdPtrOffsetTxDqs: 06
N6.C1.D1.R0.S02: RdPtrOffsetTxDqs: 07
N0.C1.D1.R0.S00: wrcmd2dqsstartlatency: 04
N2.C2.D1.R0.S16: wrcmd2dqsstartlatency: 04
N4.C1.D1.R0.S13: PiTxDqs: 48
N6.C1.D1.R0.S02: PiTxDqs: 32
N0.C1.D1.R0.S00: RdPtrOffsetTxDq: 06
N2.C2.D1.R0.S16: RdPtrOffsetTxDq: 05
N4.C1.D1.R0.S14: wrcmd2dqsstartlatency: 04
N6.C1.D1.R0.S03: wrcmd2dqsstartlatency: 04
N0.C1.D1.R0.S00: RdPtrOffsetTxDqs: 07
N2.C2.D1.R0.S16: RdPtrOffsetTxDqs: 07
N4.C1.D1.R0.S14: RdPtrOffsetTxDq: 05
N6.C1.D1.R0.S03: RdPtrOffsetTxDq: 05
N0.C1.D1.R0.S00: PiTxDqs: 57
N2.C2.D1.R0.S16: PiTxDqs: 19
N4.C1.D1.R0.S14: RdPtrOffsetTxDqs: 06
N6.C1.D1.R0.S03: RdPtrOffsetTxDqs: 07
N0.C1.D1.R0.S01: wrcmd2dqsstartlatency: 04
N2.C2.D1.R0.S17: wrcmd2dqsstartlatency: 04
N4.C1.D1.R0.S14: PiTxDqs: 62
N6.C1.D1.R0.S03: PiTxDqs: 16
N0.C1.D1.R0.S01: RdPtrOffsetTxDq: 06
N2.C2.D1.R0.S17: RdPtrOffsetTxDq: 05
N4.C1.D1.R0.S15: wrcmd2dqsstartlatency: 04
N6.C1.D1.R0.S04: wrcmd2dqsstartlatency: 04
N0.C1.D1.R0.S01: RdPtrOffsetTxDqs: 07
N2.C2.D1.R0.S17: RdPtrOffsetTxDqs: 06
N4.C1.D1.R0.S15: RdPtrOffsetTxDq: 05
N6.C1.D1.R0.S04: RdPtrOffsetTxDq: 05
N0.C1.D1.R0.S01: PiTxDqs: 40
N2.C2.D1.R0.S17: PiTxDqs: 50
N4.C1.D1.R0.S15: RdPtrOffsetTxDqs: 07
N6.C1.D1.R0.S04: RdPtrOffsetTxDqs: 06
N0.C1.D1.R0.S02: wrcmd2dqsstartlatency: 04
N2.C2.D1.R0.S00: RdPtrOffsetTxDq: 07
N4.C1.D1.R0.S15: PiTxDqs: 11
N6.C1.D1.R0.S04: PiTxDqs: 48
N0.C1.D1.R0.S02: RdPtrOffsetTxDq: 05
N2.C2.D1.R0.S01: RdPtrOffsetTxDq: 07
N4.C1.D1.R0.S16: wrcmd2dqsstartlatency: 04
N6.C1.D1.R0.S05: wrcmd2dqsstartlatency: 04
N0.C1.D1.R0.S02: RdPtrOffsetTxDqs: 07
N2.C2.D1.R0.S02: RdPtrOffsetTxDq: 06
N4.C1.D1.R0.S16: RdPtrOffsetTxDq: 05
N6.C1.D1.R0.S05: RdPtrOffsetTxDq: 05
N0.C1.D1.R0.S02: PiTxDqs: 33
N2.C2.D1.R0.S03: RdPtrOffsetTxDq: 06
N4.C1.D1.R0.S16: RdPtrOffsetTxDqs: 07
N6.C1.D1.R0.S05: RdPtrOffsetTxDqs: 06
N0.C1.D1.R0.S03: wrcmd2dqsstartlatency: 04
N2.C2.D1.R0.S04: RdPtrOffsetTxDq: 05
N4.C1.D1.R0.S16: PiTxDqs: 32
N6.C1.D1.R0.S05: PiTxDqs: 62
N0.C1.D1.R0.S03: RdPtrOffsetTxDq: 05
N2.C2.D1.R0.S05: RdPtrOffsetTxDq: 06
N4.C1.D1.R0.S17: wrcmd2dqsstartlatency: 04
N6.C1.D1.R0.S06: wrcmd2dqsstartlatency: 04
N0.C1.D1.R0.S03: RdPtrOffsetTxDqs: 07
N2.C2.D1.R0.S06: RdPtrOffsetTxDq: 06
N4.C1.D1.R0.S17: RdPtrOffsetTxDq: 05
N6.C1.D1.R0.S06: RdPtrOffsetTxDq: 05
N0.C1.D1.R0.S03: PiTxDqs: 19
N2.C2.D1.R0.S07: RdPtrOffsetTxDq: 06
N4.C1.D1.R0.S17: RdPtrOffsetTxDqs: 06
N6.C1.D1.R0.S06: RdPtrOffsetTxDqs: 07
N0.C1.D1.R0.S04: wrcmd2dqsstartlatency: 04
N2.C2.D1.R0.S08: RdPtrOffsetTxDq: 06
N4.C1.D1.R0.S17: PiTxDqs: 60
N6.C1.D1.R0.S06: PiTxDqs: 10
N0.C1.D1.R0.S04: RdPtrOffsetTxDq: 05
N2.C2.D1.R0.S09: RdPtrOffsetTxDq: 07
N4.C1.D1.R0.S00: RdPtrOffsetTxDq: 07
N6.C1.D1.R0.S07: wrcmd2dqsstartlatency: 04
N0.C1.D1.R0.S04: RdPtrOffsetTxDqs: 06
N2.C2.D1.R0.S10: RdPtrOffsetTxDq: 07
N4.C1.D1.R0.S01: RdPtrOffsetTxDq: 07
N6.C1.D1.R0.S07: RdPtrOffsetTxDq: 05
N0.C1.D1.R0.S04: PiTxDqs: 49
N2.C2.D1.R0.S11: RdPtrOffsetTxDq: 06
N4.C1.D1.R0.S02: RdPtrOffsetTxDq: 06
N6.C1.D1.R0.S07: RdPtrOffsetTxDqs: 07
N0.C1.D1.R0.S05: wrcmd2dqsstartlatency: 04
N2.C2.D1.R0.S12: RdPtrOffsetTxDq: 06
N4.C1.D1.R0.S03: RdPtrOffsetTxDq: 06
N6.C1.D1.R0.S07: PiTxDqs: 28
N0.C1.D1.R0.S05: RdPtrOffsetTxDq: 05
N2.C2.D1.R0.S13: RdPtrOffsetTxDq: 06
N4.C1.D1.R0.S04: RdPtrOffsetTxDq: 06
N6.C1.D1.R0.S08: wrcmd2dqsstartlatency: 04
N0.C1.D1.R0.S05: RdPtrOffsetTxDqs: 06
N2.C2.D1.R0.S14: RdPtrOffsetTxDq: 06
N4.C1.D1.R0.S05: RdPtrOffsetTxDq: 06
N6.C1.D1.R0.S08: RdPtrOffsetTxDq: 05
N0.C1.D1.R0.S05: PiTxDqs: 60
N2.C2.D1.R0.S15: RdPtrOffsetTxDq: 06
N4.C1.D1.R0.S06: RdPtrOffsetTxDq: 06
N6.C1.D1.R0.S08: RdPtrOffsetTxDqs: 06
N0.C1.D1.R0.S06: wrcmd2dqsstartlatency: 04
N2.C2.D1.R0.S16: RdPtrOffsetTxDq: 06
N4.C1.D1.R0.S07: RdPtrOffsetTxDq: 06
N6.C1.D1.R0.S08: PiTxDqs: 62
N0.C1.D1.R0.S06: RdPtrOffsetTxDq: 05
N2.C2.D1.R0.S17: RdPtrOffsetTxDq: 06
N4.C1.D1.R0.S08: RdPtrOffsetTxDq: 06
N6.C1.D1.R0.S09: wrcmd2dqsstartlatency: 04
N0.C1.D1.R0.S06: RdPtrOffsetTxDqs: 07
N2.C2.D1.R0.S00: RdPtrOffsetTxDq: 08
N4.C1.D1.R0.S09: RdPtrOffsetTxDq: 07
N6.C1.D1.R0.S09: RdPtrOffsetTxDq: 06
N0.C1.D1.R0.S06: PiTxDqs: 15
N2.C2.D1.R0.S01: RdPtrOffsetTxDq: 08
N4.C1.D1.R0.S10: RdPtrOffsetTxDq: 07
N6.C1.D1.R0.S09: RdPtrOffsetTxDqs: 07
N0.C1.D1.R0.S07: wrcmd2dqsstartlatency: 04
N2.C2.D1.R0.S02: RdPtrOffsetTxDq: 07
N4.C1.D1.R0.S11: RdPtrOffsetTxDq: 06
N6.C1.D1.R0.S09: PiTxDqs: 57
N0.C1.D1.R0.S07: RdPtrOffsetTxDq: 05
N2.C2.D1.R0.S03: RdPtrOffsetTxDq: 07
N4.C1.D1.R0.S12: RdPtrOffsetTxDq: 06
N6.C1.D1.R0.S10: wrcmd2dqsstartlatency: 04
N0.C1.D1.R0.S07: RdPtrOffsetTxDqs: 07
N2.C2.D1.R0.S04: RdPtrOffsetTxDq: 06
N4.C1.D1.R0.S13: RdPtrOffsetTxDq: 06
N6.C1.D1.R0.S10: RdPtrOffsetTxDq: 06
N0.C1.D1.R0.S07: PiTxDqs: 30
N2.C2.D1.R0.S05: RdPtrOffsetTxDq: 07
N4.C1.D1.R0.S14: RdPtrOffsetTxDq: 06
N6.C1.D1.R0.S10: RdPtrOffsetTxDqs: 07
N0.C1.D1.R0.S08: wrcmd2dqsstartlatency: 04
N2.C2.D1.R0.S06: RdPtrOffsetTxDq: 07
N4.C1.D1.R0.S15: RdPtrOffsetTxDq: 06
N6.C1.D1.R0.S10: PiTxDqs: 41
N0.C1.D1.R0.S08: RdPtrOffsetTxDq: 05
N2.C2.D1.R0.S07: RdPtrOffsetTxDq: 07
N4.C1.D1.R0.S16: RdPtrOffsetTxDq: 06
N6.C1.D1.R0.S11: wrcmd2dqsstartlatency: 04
N0.C1.D1.R0.S08: RdPtrOffsetTxDqs: 06
N2.C2.D1.R0.S08: RdPtrOffsetTxDq: 07
N4.C1.D1.R0.S17: RdPtrOffsetTxDq: 06
N6.C1.D1.R0.S11: RdPtrOffsetTxDq: 06
N0.C1.D1.R0.S08: PiTxDqs: 61
N2.C2.D1.R0.S09: RdPtrOffsetTxDq: 08
N4.C1.D1.R0.S00: RdPtrOffsetTxDq: 08
N6.C1.D1.R0.S11: RdPtrOffsetTxDqs: 07
N0.C1.D1.R0.S09: wrcmd2dqsstartlatency: 04
N2.C2.D1.R0.S10: RdPtrOffsetTxDq: 08
N4.C1.D1.R0.S01: RdPtrOffsetTxDq: 08
N6.C1.D1.R0.S11: PiTxDqs: 33
N0.C1.D1.R0.S09: RdPtrOffsetTxDq: 06
N2.C2.D1.R0.S11: RdPtrOffsetTxDq: 07
N4.C1.D1.R0.S02: RdPtrOffsetTxDq: 07
N6.C1.D1.R0.S12: wrcmd2dqsstartlatency: 04
N0.C1.D1.R0.S09: RdPtrOffsetTxDqs: 07
N2.C2.D1.R0.S12: RdPtrOffsetTxDq: 07
N4.C1.D1.R0.S03: RdPtrOffsetTxDq: 07
N6.C1.D1.R0.S12: RdPtrOffsetTxDq: 05
N0.C1.D1.R0.S09: PiTxDqs: 57
N2.C2.D1.R0.S13: RdPtrOffsetTxDq: 07
N4.C1.D1.R0.S04: RdPtrOffsetTxDq: 07
N6.C1.D1.R0.S12: RdPtrOffsetTxDqs: 07
N0.C1.D1.R0.S10: wrcmd2dqsstartlatency: 04
N2.C2.D1.R0.S14: RdPtrOffsetTxDq: 07
N4.C1.D1.R0.S05: RdPtrOffsetTxDq: 07
N6.C1.D1.R0.S12: PiTxDqs: 18
N0.C1.D1.R0.S10: RdPtrOffsetTxDq: 06
N2.C2.D1.R0.S15: RdPtrOffsetTxDq: 07
N4.C1.D1.R0.S06: RdPtrOffsetTxDq: 07
N6.C1.D1.R0.S13: wrcmd2dqsstartlatency: 04
N0.C1.D1.R0.S10: RdPtrOffsetTxDqs: 07
N2.C2.D1.R0.S16: RdPtrOffsetTxDq: 07
N4.C1.D1.R0.S07: RdPtrOffsetTxDq: 07
N6.C1.D1.R0.S13: RdPtrOffsetTxDq: 05
N0.C1.D1.R0.S10: PiTxDqs: 40
N2.C2.D1.R0.S17: RdPtrOffsetTxDq: 07
N4.C1.D1.R0.S08: RdPtrOffsetTxDq: 07
N6.C1.D1.R0.S13: RdPtrOffsetTxDqs: 06
N0.C1.D1.R0.S11: wrcmd2dqsstartlatency: 04
N2.C2.D1.R0.S00: Total Delay in PI ticks: TxDQ = 979
N4.C1.D1.R0.S09: RdPtrOffsetTxDq: 08
N6.C1.D1.R0.S13: PiTxDqs: 49
N0.C1.D1.R0.S11: RdPtrOffsetTxDq: 06
N2.C2.D1.R0.S01: Total Delay in PI ticks: TxDQ = 965
N4.C1.D1.R0.S10: RdPtrOffsetTxDq: 08
N6.C1.D1.R0.S14: wrcmd2dqsstartlatency: 04
N0.C1.D1.R0.S11: RdPtrOffsetTxDqs: 07
N2.C2.D1.R0.S02: Total Delay in PI ticks: TxDQ = 956
N4.C1.D1.R0.S11: RdPtrOffsetTxDq: 07
N6.C1.D1.R0.S14: RdPtrOffsetTxDq: 05
N0.C1.D1.R0.S11: PiTxDqs: 34
N2.C2.D1.R0.S03: Total Delay in PI ticks: TxDQ = 939
N4.C1.D1.R0.S12: RdPtrOffsetTxDq: 07
N6.C1.D1.R0.S14: RdPtrOffsetTxDqs: 06
N0.C1.D1.R0.S12: wrcmd2dqsstartlatency: 04
N2.C2.D1.R0.S04: Total Delay in PI ticks: TxDQ = 898
N4.C1.D1.R0.S13: RdPtrOffsetTxDq: 07
N6.C1.D1.R0.S14: PiTxDqs: 62
N0.C1.D1.R0.S12: RdPtrOffsetTxDq: 05
N2.C2.D1.R0.S05: Total Delay in PI ticks: TxDQ = 927
N4.C1.D1.R0.S14: RdPtrOffsetTxDq: 07
N6.C1.D1.R0.S15: wrcmd2dqsstartlatency: 04
N0.C1.D1.R0.S12: RdPtrOffsetTxDqs: 07
N2.C2.D1.R0.S06: Total Delay in PI ticks: TxDQ = 924
N4.C1.D1.R0.S15: RdPtrOffsetTxDq: 07
N6.C1.D1.R0.S15: RdPtrOffsetTxDq: 05
N0.C1.D1.R0.S12: PiTxDqs: 18
N2.C2.D1.R0.S07: Total Delay in PI ticks: TxDQ = 946
N4.C1.D1.R0.S16: RdPtrOffsetTxDq: 07
N6.C1.D1.R0.S15: RdPtrOffsetTxDqs: 07
N0.C1.D1.R0.S13: wrcmd2dqsstartlatency: 04
N2.C2.D1.R0.S08: Total Delay in PI ticks: TxDQ = 911
N4.C1.D1.R0.S17: RdPtrOffsetTxDq: 07
N6.C1.D1.R0.S15: PiTxDqs: 09
N0.C1.D1.R0.S13: RdPtrOffsetTxDq: 05
N2.C2.D1.R0.S09: Total Delay in PI ticks: TxDQ = 976
N4.C1.D1.R0.S00: Total Delay in PI ticks: TxDQ = 987
N6.C1.D1.R0.S16: wrcmd2dqsstartlatency: 04
N0.C1.D1.R0.S13: RdPtrOffsetTxDqs: 06
N2.C2.D1.R0.S10: Total Delay in PI ticks: TxDQ = 965
N4.C1.D1.R0.S01: Total Delay in PI ticks: TxDQ = 970
N6.C1.D1.R0.S16: RdPtrOffsetTxDq: 05
N0.C1.D1.R0.S13: PiTxDqs: 47
N2.C2.D1.R0.S11: Total Delay in PI ticks: TxDQ = 955
N4.C1.D1.R0.S02: Total Delay in PI ticks: TxDQ = 961
N6.C1.D1.R0.S16: RdPtrOffsetTxDqs: 07
N0.C1.D1.R0.S14: wrcmd2dqsstartlatency: 04
N2.C2.D1.R0.S12: Total Delay in PI ticks: TxDQ = 938
N4.C1.D1.R0.S03: Total Delay in PI ticks: TxDQ = 943
N6.C1.D1.R0.S16: PiTxDqs: 32
N0.C1.D1.R0.S14: RdPtrOffsetTxDq: 05
N2.C2.D1.R0.S13: Total Delay in PI ticks: TxDQ = 898
N4.C1.D1.R0.S04: Total Delay in PI ticks: TxDQ = 909
N6.C1.D1.R0.S17: wrcmd2dqsstartlatency: 04
N0.C1.D1.R0.S14: RdPtrOffsetTxDqs: 06
N2.C2.D1.R0.S14: Total Delay in PI ticks: TxDQ = 927
N4.C1.D1.R0.S05: Total Delay in PI ticks: TxDQ = 922
N6.C1.D1.R0.S17: RdPtrOffsetTxDq: 05
N0.C1.D1.R0.S14: PiTxDqs: 61
N2.C2.D1.R0.S15: Total Delay in PI ticks: TxDQ = 924
N4.C1.D1.R0.S06: Total Delay in PI ticks: TxDQ = 938
N6.C1.D1.R0.S17: RdPtrOffsetTxDqs: 06
N0.C1.D1.R0.S15: wrcmd2dqsstartlatency: 04
N2.C2.D1.R0.S16: Total Delay in PI ticks: TxDQ = 947
N4.C1.D1.R0.S07: Total Delay in PI ticks: TxDQ = 953
N6.C1.D1.R0.S17: PiTxDqs: 61
N0.C1.D1.R0.S15: RdPtrOffsetTxDq: 05
N2.C2.D1.R0.S17: Total Delay in PI ticks: TxDQ = 912
N4.C1.D1.R0.S08: Total Delay in PI ticks: TxDQ = 924
N6.C1.D1.R0.S00: RdPtrOffsetTxDq: 07
N0.C1.D1.R0.S15: RdPtrOffsetTxDqs: 07
N2.C2.D1.R1.S00: wrcmd2dqsstartlatency: 04
N4.C1.D1.R0.S09: Total Delay in PI ticks: TxDQ = 984
N6.C1.D1.R0.S01: RdPtrOffsetTxDq: 07
N0.C1.D1.R0.S15: PiTxDqs: 10
N2.C2.D1.R1.S00: RdPtrOffsetTxDq: 06
N4.C1.D1.R0.S10: Total Delay in PI ticks: TxDQ = 969
N6.C1.D1.R0.S02: RdPtrOffsetTxDq: 06
N0.C1.D1.R0.S16: wrcmd2dqsstartlatency: 04
N2.C2.D1.R1.S00: RdPtrOffsetTxDqs: 07
N4.C1.D1.R0.S11: Total Delay in PI ticks: TxDQ = 959
N6.C1.D1.R0.S03: RdPtrOffsetTxDq: 06
N0.C1.D1.R0.S16: RdPtrOffsetTxDq: 05
N2.C2.D1.R1.S00: PiTxDqs: 49
N4.C1.D1.R0.S12: Total Delay in PI ticks: TxDQ = 946
N6.C1.D1.R0.S04: RdPtrOffsetTxDq: 06
N0.C1.D1.R0.S16: RdPtrOffsetTxDqs: 07
N2.C2.D1.R1.S01: wrcmd2dqsstartlatency: 04
N4.C1.D1.R0.S13: Total Delay in PI ticks: TxDQ = 908
N6.C1.D1.R0.S05: RdPtrOffsetTxDq: 06
N0.C1.D1.R0.S16: PiTxDqs: 28
N2.C2.D1.R1.S01: RdPtrOffsetTxDq: 05
N4.C1.D1.R0.S14: Total Delay in PI ticks: TxDQ = 922
N6.C1.D1.R0.S06: RdPtrOffsetTxDq: 06
N0.C1.D1.R0.S17: wrcmd2dqsstartlatency: 04
N2.C2.D1.R1.S01: RdPtrOffsetTxDqs: 07
N4.C1.D1.R0.S15: Total Delay in PI ticks: TxDQ = 938
N6.C1.D1.R0.S07: RdPtrOffsetTxDq: 06
N0.C1.D1.R0.S17: RdPtrOffsetTxDq: 05
N2.C2.D1.R1.S01: PiTxDqs: 33
N4.C1.D1.R0.S16: Total Delay in PI ticks: TxDQ = 955
N6.C1.D1.R0.S08: RdPtrOffsetTxDq: 06
N0.C1.D1.R0.S17: RdPtrOffsetTxDqs: 06
N2.C2.D1.R1.S02: wrcmd2dqsstartlatency: 04
N4.C1.D1.R0.S17: Total Delay in PI ticks: TxDQ = 922
N6.C1.D1.R0.S09: RdPtrOffsetTxDq: 07
N0.C1.D1.R0.S17: PiTxDqs: 60
N2.C2.D1.R1.S02: RdPtrOffsetTxDq: 05
N4.C1.D1.R1.S00: wrcmd2dqsstartlatency: 04
N6.C1.D1.R0.S10: RdPtrOffsetTxDq: 07
N0.C1.D1.R0.S00: RdPtrOffsetTxDq: 07
N2.C2.D1.R1.S02: RdPtrOffsetTxDqs: 07
N4.C1.D1.R1.S00: RdPtrOffsetTxDq: 06
N6.C1.D1.R0.S11: RdPtrOffsetTxDq: 07
N0.C1.D1.R0.S01: RdPtrOffsetTxDq: 07
N2.C2.D1.R1.S02: PiTxDqs: 21
N4.C1.D1.R1.S00: RdPtrOffsetTxDqs: 07
N6.C1.D1.R0.S12: RdPtrOffsetTxDq: 06
N0.C1.D1.R0.S02: RdPtrOffsetTxDq: 06
N2.C2.D1.R1.S03: wrcmd2dqsstartlatency: 04
N4.C1.D1.R1.S00: PiTxDqs: 58
N6.C1.D1.R0.S13: RdPtrOffsetTxDq: 06
N0.C1.D1.R0.S03: RdPtrOffsetTxDq: 06
N2.C2.D1.R1.S03: RdPtrOffsetTxDq: 05
N4.C1.D1.R1.S01: wrcmd2dqsstartlatency: 04
N6.C1.D1.R0.S14: RdPtrOffsetTxDq: 06
N0.C1.D1.R0.S04: RdPtrOffsetTxDq: 06
N2.C2.D1.R1.S03: RdPtrOffsetTxDqs: 07
N4.C1.D1.R1.S01: RdPtrOffsetTxDq: 06
N6.C1.D1.R0.S15: RdPtrOffsetTxDq: 06
N0.C1.D1.R0.S05: RdPtrOffsetTxDq: 06
N2.C2.D1.R1.S03: PiTxDqs: 09
N4.C1.D1.R1.S01: RdPtrOffsetTxDqs: 07
N6.C1.D1.R0.S16: RdPtrOffsetTxDq: 06
N0.C1.D1.R0.S06: RdPtrOffsetTxDq: 06
N2.C2.D1.R1.S04: wrcmd2dqsstartlatency: 04
N4.C1.D1.R1.S01: PiTxDqs: 42
N6.C1.D1.R0.S17: RdPtrOffsetTxDq: 06
N0.C1.D1.R0.S07: RdPtrOffsetTxDq: 06
N2.C2.D1.R1.S04: RdPtrOffsetTxDq: 04
N4.C1.D1.R1.S02: wrcmd2dqsstartlatency: 04
N6.C1.D1.R0.S00: RdPtrOffsetTxDq: 08
N0.C1.D1.R0.S08: RdPtrOffsetTxDq: 06
N2.C2.D1.R1.S04: RdPtrOffsetTxDqs: 06
N4.C1.D1.R1.S02: RdPtrOffsetTxDq: 05
N6.C1.D1.R0.S01: RdPtrOffsetTxDq: 08
N0.C1.D1.R0.S09: RdPtrOffsetTxDq: 07
N2.C2.D1.R1.S04: PiTxDqs: 30
N4.C1.D1.R1.S02: RdPtrOffsetTxDqs: 07
N6.C1.D1.R0.S02: RdPtrOffsetTxDq: 07
N0.C1.D1.R0.S10: RdPtrOffsetTxDq: 07
N2.C2.D1.R1.S05: wrcmd2dqsstartlatency: 04
N4.C1.D1.R1.S02: PiTxDqs: 32
N6.C1.D1.R0.S03: RdPtrOffsetTxDq: 07
N0.C1.D1.R0.S11: RdPtrOffsetTxDq: 07
N2.C2.D1.R1.S05: RdPtrOffsetTxDq: 05
N4.C1.D1.R1.S03: wrcmd2dqsstartlatency: 04
N6.C1.D1.R0.S04: RdPtrOffsetTxDq: 07
N0.C1.D1.R0.S12: RdPtrOffsetTxDq: 06
N2.C2.D1.R1.S05: RdPtrOffsetTxDqs: 06
N4.C1.D1.R1.S03: RdPtrOffsetTxDq: 05
N6.C1.D1.R0.S05: RdPtrOffsetTxDq: 07
N0.C1.D1.R0.S13: RdPtrOffsetTxDq: 06
N2.C2.D1.R1.S05: PiTxDqs: 61
N4.C1.D1.R1.S03: RdPtrOffsetTxDqs: 07
N6.C1.D1.R0.S06: RdPtrOffsetTxDq: 07
N0.C1.D1.R0.S14: RdPtrOffsetTxDq: 06
N2.C2.D1.R1.S06: wrcmd2dqsstartlatency: 04
N4.C1.D1.R1.S03: PiTxDqs: 18
N6.C1.D1.R0.S07: RdPtrOffsetTxDq: 07
N0.C1.D1.R0.S15: RdPtrOffsetTxDq: 06
N2.C2.D1.R1.S06: RdPtrOffsetTxDq: 05
N4.C1.D1.R1.S04: wrcmd2dqsstartlatency: 04
N6.C1.D1.R0.S08: RdPtrOffsetTxDq: 07
N0.C1.D1.R0.S16: RdPtrOffsetTxDq: 06
N2.C2.D1.R1.S06: RdPtrOffsetTxDqs: 06
N4.C1.D1.R1.S04: RdPtrOffsetTxDq: 05
N6.C1.D1.R0.S09: RdPtrOffsetTxDq: 08
N0.C1.D1.R0.S17: RdPtrOffsetTxDq: 06
N2.C2.D1.R1.S06: PiTxDqs: 55
N4.C1.D1.R1.S04: RdPtrOffsetTxDqs: 06
N6.C1.D1.R0.S10: RdPtrOffsetTxDq: 08
N0.C1.D1.R0.S00: RdPtrOffsetTxDq: 08
N2.C2.D1.R1.S07: wrcmd2dqsstartlatency: 04
N4.C1.D1.R1.S04: PiTxDqs: 47
N6.C1.D1.R0.S11: RdPtrOffsetTxDq: 08
N0.C1.D1.R0.S01: RdPtrOffsetTxDq: 08
N2.C2.D1.R1.S07: RdPtrOffsetTxDq: 05
N4.C1.D1.R1.S05: wrcmd2dqsstartlatency: 04
N6.C1.D1.R0.S12: RdPtrOffsetTxDq: 07
N0.C1.D1.R0.S02: RdPtrOffsetTxDq: 07
N2.C2.D1.R1.S07: RdPtrOffsetTxDqs: 07
N4.C1.D1.R1.S05: RdPtrOffsetTxDq: 05
N6.C1.D1.R0.S13: RdPtrOffsetTxDq: 07
N0.C1.D1.R0.S03: RdPtrOffsetTxDq: 07
N2.C2.D1.R1.S07: PiTxDqs: 17
N4.C1.D1.R1.S05: RdPtrOffsetTxDqs: 06
N6.C1.D1.R0.S14: RdPtrOffsetTxDq: 07
N0.C1.D1.R0.S04: RdPtrOffsetTxDq: 07
N2.C2.D1.R1.S08: wrcmd2dqsstartlatency: 04
N4.C1.D1.R1.S05: PiTxDqs: 61
N6.C1.D1.R0.S15: RdPtrOffsetTxDq: 07
N0.C1.D1.R0.S05: RdPtrOffsetTxDq: 07
N2.C2.D1.R1.S08: RdPtrOffsetTxDq: 05
N4.C1.D1.R1.S06: wrcmd2dqsstartlatency: 04
N6.C1.D1.R0.S16: RdPtrOffsetTxDq: 07
N0.C1.D1.R0.S06: RdPtrOffsetTxDq: 07
N2.C2.D1.R1.S08: RdPtrOffsetTxDqs: 06
N4.C1.D1.R1.S06: RdPtrOffsetTxDq: 05
N6.C1.D1.R0.S17: RdPtrOffsetTxDq: 07
N0.C1.D1.R0.S07: RdPtrOffsetTxDq: 07
N2.C2.D1.R1.S08: PiTxDqs: 47
N4.C1.D1.R1.S06: RdPtrOffsetTxDqs: 07
N6.C1.D1.R0.S00: Total Delay in PI ticks: TxDQ = 986
N0.C1.D1.R0.S08: RdPtrOffsetTxDq: 07
N2.C2.D1.R1.S09: wrcmd2dqsstartlatency: 04
N4.C1.D1.R1.S06: PiTxDqs: 08
N6.C1.D1.R0.S01: Total Delay in PI ticks: TxDQ = 969
N0.C1.D1.R0.S09: RdPtrOffsetTxDq: 08
N2.C2.D1.R1.S09: RdPtrOffsetTxDq: 06
N4.C1.D1.R1.S07: wrcmd2dqsstartlatency: 04
N6.C1.D1.R0.S02: Total Delay in PI ticks: TxDQ = 958
N0.C1.D1.R0.S10: RdPtrOffsetTxDq: 08
N2.C2.D1.R1.S09: RdPtrOffsetTxDqs: 07
N4.C1.D1.R1.S07: RdPtrOffsetTxDq: 05
N6.C1.D1.R0.S03: Total Delay in PI ticks: TxDQ = 943
N0.C1.D1.R0.S11: RdPtrOffsetTxDq: 08
N2.C2.D1.R1.S09: PiTxDqs: 46
N4.C1.D1.R1.S07: RdPtrOffsetTxDqs: 07
N6.C1.D1.R0.S04: Total Delay in PI ticks: TxDQ = 910
N0.C1.D1.R0.S12: RdPtrOffsetTxDq: 07
N2.C2.D1.R1.S10: wrcmd2dqsstartlatency: 04
N4.C1.D1.R1.S07: PiTxDqs: 26
N6.C1.D1.R0.S05: Total Delay in PI ticks: TxDQ = 924
N0.C1.D1.R0.S13: RdPtrOffsetTxDq: 07
N2.C2.D1.R1.S10: RdPtrOffsetTxDq: 05
N4.C1.D1.R1.S08: wrcmd2dqsstartlatency: 04
N6.C1.D1.R0.S06: Total Delay in PI ticks: TxDQ = 939
N0.C1.D1.R0.S14: RdPtrOffsetTxDq: 07
N2.C2.D1.R1.S10: RdPtrOffsetTxDqs: 07
N4.C1.D1.R1.S08: RdPtrOffsetTxDq: 05
N6.C1.D1.R0.S07: Total Delay in PI ticks: TxDQ = 956
N0.C1.D1.R0.S15: RdPtrOffsetTxDq: 07
N2.C2.D1.R1.S10: PiTxDqs: 34
N4.C1.D1.R1.S08: RdPtrOffsetTxDqs: 06
N6.C1.D1.R0.S08: Total Delay in PI ticks: TxDQ = 926
N0.C1.D1.R0.S16: RdPtrOffsetTxDq: 07
N2.C2.D1.R1.S11: wrcmd2dqsstartlatency: 04
N4.C1.D1.R1.S08: PiTxDqs: 58
N6.C1.D1.R0.S09: Total Delay in PI ticks: TxDQ = 983
N0.C1.D1.R0.S17: RdPtrOffsetTxDq: 07
N2.C2.D1.R1.S11: RdPtrOffsetTxDq: 05
N4.C1.D1.R1.S09: wrcmd2dqsstartlatency: 04
N6.C1.D1.R0.S10: Total Delay in PI ticks: TxDQ = 968
N0.C1.D1.R0.S00: Total Delay in PI ticks: TxDQ = 984
N2.C2.D1.R1.S11: RdPtrOffsetTxDqs: 07
N4.C1.D1.R1.S09: RdPtrOffsetTxDq: 06
N6.C1.D1.R0.S11: Total Delay in PI ticks: TxDQ = 960
N0.C1.D1.R0.S01: Total Delay in PI ticks: TxDQ = 966
N2.C2.D1.R1.S11: PiTxDqs: 23
N4.C1.D1.R1.S09: RdPtrOffsetTxDqs: 07
N6.C1.D1.R0.S12: Total Delay in PI ticks: TxDQ = 945
N0.C1.D1.R0.S02: Total Delay in PI ticks: TxDQ = 958
N2.C2.D1.R1.S12: wrcmd2dqsstartlatency: 04
N4.C1.D1.R1.S09: PiTxDqs: 56
N6.C1.D1.R0.S13: Total Delay in PI ticks: TxDQ = 913
N0.C1.D1.R0.S03: Total Delay in PI ticks: TxDQ = 945
N2.C2.D1.R1.S12: RdPtrOffsetTxDq: 05
N4.C1.D1.R1.S10: wrcmd2dqsstartlatency: 04
N6.C1.D1.R0.S14: Total Delay in PI ticks: TxDQ = 925
N0.C1.D1.R0.S04: Total Delay in PI ticks: TxDQ = 911
N2.C2.D1.R1.S12: RdPtrOffsetTxDqs: 07
N4.C1.D1.R1.S10: RdPtrOffsetTxDq: 06
N6.C1.D1.R0.S15: Total Delay in PI ticks: TxDQ = 938
N0.C1.D1.R0.S05: Total Delay in PI ticks: TxDQ = 922
N2.C2.D1.R1.S12: PiTxDqs: 09
N4.C1.D1.R1.S10: RdPtrOffsetTxDqs: 07
N6.C1.D1.R0.S16: Total Delay in PI ticks: TxDQ = 959
N0.C1.D1.R0.S06: Total Delay in PI ticks: TxDQ = 940
N2.C2.D1.R1.S13: wrcmd2dqsstartlatency: 04
N4.C1.D1.R1.S10: PiTxDqs: 41
N6.C1.D1.R0.S17: Total Delay in PI ticks: TxDQ = 924
N0.C1.D1.R0.S07: Total Delay in PI ticks: TxDQ = 956
N2.C2.D1.R1.S13: RdPtrOffsetTxDq: 04
N4.C1.D1.R1.S11: wrcmd2dqsstartlatency: 04
N6.C1.D1.R1.S00: wrcmd2dqsstartlatency: 04
N0.C1.D1.R0.S08: Total Delay in PI ticks: TxDQ = 924
N2.C2.D1.R1.S13: RdPtrOffsetTxDqs: 06
N4.C1.D1.R1.S11: RdPtrOffsetTxDq: 05
N6.C1.D1.R1.S00: RdPtrOffsetTxDq: 06
N0.C1.D1.R0.S09: Total Delay in PI ticks: TxDQ = 982
N2.C2.D1.R1.S13: PiTxDqs: 31
N4.C1.D1.R1.S11: RdPtrOffsetTxDqs: 07
N6.C1.D1.R1.S00: RdPtrOffsetTxDqs: 07
N0.C1.D1.R0.S10: Total Delay in PI ticks: TxDQ = 966
N2.C2.D1.R1.S14: wrcmd2dqsstartlatency: 04
N4.C1.D1.R1.S11: PiTxDqs: 31
N6.C1.D1.R1.S00: PiTxDqs: 54
N0.C1.D1.R0.S11: Total Delay in PI ticks: TxDQ = 960
N2.C2.D1.R1.S14: RdPtrOffsetTxDq: 05
N4.C1.D1.R1.S12: wrcmd2dqsstartlatency: 04
N6.C1.D1.R1.S01: wrcmd2dqsstartlatency: 04
N0.C1.D1.R0.S12: Total Delay in PI ticks: TxDQ = 946
N2.C2.D1.R1.S14: RdPtrOffsetTxDqs: 06
N4.C1.D1.R1.S12: RdPtrOffsetTxDq: 05
N6.C1.D1.R1.S01: RdPtrOffsetTxDq: 06
N0.C1.D1.R0.S13: Total Delay in PI ticks: TxDQ = 909
N2.C2.D1.R1.S14: PiTxDqs: 60
N4.C1.D1.R1.S12: RdPtrOffsetTxDqs: 07
N6.C1.D1.R1.S01: RdPtrOffsetTxDqs: 07
N0.C1.D1.R0.S14: Total Delay in PI ticks: TxDQ = 924
N2.C2.D1.R1.S15: wrcmd2dqsstartlatency: 04
N4.C1.D1.R1.S12: PiTxDqs: 18
N6.C1.D1.R1.S01: PiTxDqs: 36
N0.C1.D1.R0.S15: Total Delay in PI ticks: TxDQ = 938
N2.C2.D1.R1.S15: RdPtrOffsetTxDq: 05
N4.C1.D1.R1.S13: wrcmd2dqsstartlatency: 04
N6.C1.D1.R1.S02: wrcmd2dqsstartlatency: 04
N0.C1.D1.R0.S16: Total Delay in PI ticks: TxDQ = 955
N2.C2.D1.R1.S15: RdPtrOffsetTxDqs: 06
N4.C1.D1.R1.S13: RdPtrOffsetTxDq: 05
N6.C1.D1.R1.S02: RdPtrOffsetTxDq: 05
N0.C1.D1.R0.S17: Total Delay in PI ticks: TxDQ = 923
N2.C2.D1.R1.S15: PiTxDqs: 56
N4.C1.D1.R1.S13: RdPtrOffsetTxDqs: 06
N6.C1.D1.R1.S02: RdPtrOffsetTxDqs: 07
N0.C1.D1.R1.S00: wrcmd2dqsstartlatency: 04
N2.C2.D1.R1.S16: wrcmd2dqsstartlatency: 04
N4.C1.D1.R1.S13: PiTxDqs: 47
N6.C1.D1.R1.S02: PiTxDqs: 28
N0.C1.D1.R1.S00: RdPtrOffsetTxDq: 06
N2.C2.D1.R1.S16: RdPtrOffsetTxDq: 05
N4.C1.D1.R1.S14: wrcmd2dqsstartlatency: 04
N6.C1.D1.R1.S03: wrcmd2dqsstartlatency: 04
N0.C1.D1.R1.S00: RdPtrOffsetTxDqs: 07
N2.C2.D1.R1.S16: RdPtrOffsetTxDqs: 07
N4.C1.D1.R1.S14: RdPtrOffsetTxDq: 05
N6.C1.D1.R1.S03: RdPtrOffsetTxDq: 05
N0.C1.D1.R1.S00: PiTxDqs: 54
N2.C2.D1.R1.S16: PiTxDqs: 16
N4.C1.D1.R1.S14: RdPtrOffsetTxDqs: 06
N6.C1.D1.R1.S03: RdPtrOffsetTxDqs: 07
N0.C1.D1.R1.S01: wrcmd2dqsstartlatency: 04
N2.C2.D1.R1.S17: wrcmd2dqsstartlatency: 04
N4.C1.D1.R1.S14: PiTxDqs: 60
N6.C1.D1.R1.S03: PiTxDqs: 12
N0.C1.D1.R1.S01: RdPtrOffsetTxDq: 06
N2.C2.D1.R1.S17: RdPtrOffsetTxDq: 05
N4.C1.D1.R1.S15: wrcmd2dqsstartlatency: 04
N6.C1.D1.R1.S04: wrcmd2dqsstartlatency: 04
N0.C1.D1.R1.S01: RdPtrOffsetTxDqs: 07
N2.C2.D1.R1.S17: RdPtrOffsetTxDqs: 06
N4.C1.D1.R1.S15: RdPtrOffsetTxDq: 05
N6.C1.D1.R1.S04: RdPtrOffsetTxDq: 05
N0.C1.D1.R1.S01: PiTxDqs: 36
N2.C2.D1.R1.S17: PiTxDqs: 44
N4.C1.D1.R1.S15: RdPtrOffsetTxDqs: 07
N6.C1.D1.R1.S04: RdPtrOffsetTxDqs: 06
N0.C1.D1.R1.S02: wrcmd2dqsstartlatency: 04
N2.C2.D1.R1.S00: RdPtrOffsetTxDq: 07
N4.C1.D1.R1.S15: PiTxDqs: 08
N6.C1.D1.R1.S04: PiTxDqs: 43
N0.C1.D1.R1.S02: RdPtrOffsetTxDq: 05
N2.C2.D1.R1.S01: RdPtrOffsetTxDq: 06
N4.C1.D1.R1.S16: wrcmd2dqsstartlatency: 04
N6.C1.D1.R1.S05: wrcmd2dqsstartlatency: 04
N0.C1.D1.R1.S02: RdPtrOffsetTxDqs: 07
N2.C2.D1.R1.S02: RdPtrOffsetTxDq: 06
N4.C1.D1.R1.S16: RdPtrOffsetTxDq: 05
N6.C1.D1.R1.S05: RdPtrOffsetTxDq: 05
N0.C1.D1.R1.S02: PiTxDqs: 28
N2.C2.D1.R1.S03: RdPtrOffsetTxDq: 06
N4.C1.D1.R1.S16: RdPtrOffsetTxDqs: 07
N6.C1.D1.R1.S05: RdPtrOffsetTxDqs: 06
N0.C1.D1.R1.S03: wrcmd2dqsstartlatency: 04
N2.C2.D1.R1.S04: RdPtrOffsetTxDq: 05
N4.C1.D1.R1.S16: PiTxDqs: 26
N6.C1.D1.R1.S05: PiTxDqs: 59
N0.C1.D1.R1.S03: RdPtrOffsetTxDq: 05
N2.C2.D1.R1.S05: RdPtrOffsetTxDq: 06
N4.C1.D1.R1.S17: wrcmd2dqsstartlatency: 04
N6.C1.D1.R1.S06: wrcmd2dqsstartlatency: 04
N0.C1.D1.R1.S03: RdPtrOffsetTxDqs: 07
N2.C2.D1.R1.S06: RdPtrOffsetTxDq: 06
N4.C1.D1.R1.S17: RdPtrOffsetTxDq: 05
N6.C1.D1.R1.S06: RdPtrOffsetTxDq: 05
N0.C1.D1.R1.S03: PiTxDqs: 16
N2.C2.D1.R1.S07: RdPtrOffsetTxDq: 06
N4.C1.D1.R1.S17: RdPtrOffsetTxDqs: 06
N6.C1.D1.R1.S06: RdPtrOffsetTxDqs: 07
N0.C1.D1.R1.S04: wrcmd2dqsstartlatency: 04
N2.C2.D1.R1.S08: RdPtrOffsetTxDq: 06
N4.C1.D1.R1.S17: PiTxDqs: 57
N6.C1.D1.R1.S06: PiTxDqs: 04
N0.C1.D1.R1.S04: RdPtrOffsetTxDq: 05
N2.C2.D1.R1.S09: RdPtrOffsetTxDq: 07
N4.C1.D1.R1.S00: RdPtrOffsetTxDq: 07
N6.C1.D1.R1.S07: wrcmd2dqsstartlatency: 04
N0.C1.D1.R1.S04: RdPtrOffsetTxDqs: 06
N2.C2.D1.R1.S10: RdPtrOffsetTxDq: 06
N4.C1.D1.R1.S01: RdPtrOffsetTxDq: 07
N6.C1.D1.R1.S07: RdPtrOffsetTxDq: 05
N0.C1.D1.R1.S04: PiTxDqs: 45
N2.C2.D1.R1.S11: RdPtrOffsetTxDq: 06
N4.C1.D1.R1.S02: RdPtrOffsetTxDq: 06
N6.C1.D1.R1.S07: RdPtrOffsetTxDqs: 07
N0.C1.D1.R1.S05: wrcmd2dqsstartlatency: 04
N2.C2.D1.R1.S12: RdPtrOffsetTxDq: 06
N4.C1.D1.R1.S03: RdPtrOffsetTxDq: 06
N6.C1.D1.R1.S07: PiTxDqs: 26
N0.C1.D1.R1.S05: RdPtrOffsetTxDq: 05
N2.C2.D1.R1.S13: RdPtrOffsetTxDq: 05
N4.C1.D1.R1.S04: RdPtrOffsetTxDq: 06
N6.C1.D1.R1.S08: wrcmd2dqsstartlatency: 04
N0.C1.D1.R1.S05: RdPtrOffsetTxDqs: 06
N2.C2.D1.R1.S14: RdPtrOffsetTxDq: 06
N4.C1.D1.R1.S05: RdPtrOffsetTxDq: 06
N6.C1.D1.R1.S08: RdPtrOffsetTxDq: 05
N0.C1.D1.R1.S05: PiTxDqs: 59
N2.C2.D1.R1.S15: RdPtrOffsetTxDq: 06
N4.C1.D1.R1.S06: RdPtrOffsetTxDq: 06
N6.C1.D1.R1.S08: RdPtrOffsetTxDqs: 06
N0.C1.D1.R1.S06: wrcmd2dqsstartlatency: 04
N2.C2.D1.R1.S16: RdPtrOffsetTxDq: 06
N4.C1.D1.R1.S07: RdPtrOffsetTxDq: 06
N6.C1.D1.R1.S08: PiTxDqs: 56
N0.C1.D1.R1.S06: RdPtrOffsetTxDq: 05
N2.C2.D1.R1.S17: RdPtrOffsetTxDq: 06
N4.C1.D1.R1.S08: RdPtrOffsetTxDq: 06
N6.C1.D1.R1.S09: wrcmd2dqsstartlatency: 04
N0.C1.D1.R1.S06: RdPtrOffsetTxDqs: 07
N2.C2.D1.R1.S00: RdPtrOffsetTxDq: 08
N4.C1.D1.R1.S09: RdPtrOffsetTxDq: 07
N6.C1.D1.R1.S09: RdPtrOffsetTxDq: 06
N0.C1.D1.R1.S06: PiTxDqs: 08
N2.C2.D1.R1.S01: RdPtrOffsetTxDq: 07
N4.C1.D1.R1.S10: RdPtrOffsetTxDq: 07
N6.C1.D1.R1.S09: RdPtrOffsetTxDqs: 07
N0.C1.D1.R1.S07: wrcmd2dqsstartlatency: 04
N2.C2.D1.R1.S02: RdPtrOffsetTxDq: 07
N4.C1.D1.R1.S11: RdPtrOffsetTxDq: 06
N6.C1.D1.R1.S09: PiTxDqs: 52
N0.C1.D1.R1.S07: RdPtrOffsetTxDq: 05
N2.C2.D1.R1.S03: RdPtrOffsetTxDq: 07
N4.C1.D1.R1.S12: RdPtrOffsetTxDq: 06
N6.C1.D1.R1.S10: wrcmd2dqsstartlatency: 04
N0.C1.D1.R1.S07: RdPtrOffsetTxDqs: 07
N2.C2.D1.R1.S04: RdPtrOffsetTxDq: 06
N4.C1.D1.R1.S13: RdPtrOffsetTxDq: 06
N6.C1.D1.R1.S10: RdPtrOffsetTxDq: 06
N0.C1.D1.R1.S07: PiTxDqs: 27
N2.C2.D1.R1.S05: RdPtrOffsetTxDq: 07
N4.C1.D1.R1.S14: RdPtrOffsetTxDq: 06
N6.C1.D1.R1.S10: RdPtrOffsetTxDqs: 07
N0.C1.D1.R1.S08: wrcmd2dqsstartlatency: 04
N2.C2.D1.R1.S06: RdPtrOffsetTxDq: 07
N4.C1.D1.R1.S15: RdPtrOffsetTxDq: 06
N6.C1.D1.R1.S10: PiTxDqs: 39
N0.C1.D1.R1.S08: RdPtrOffsetTxDq: 05
N2.C2.D1.R1.S07: RdPtrOffsetTxDq: 07
N4.C1.D1.R1.S16: RdPtrOffsetTxDq: 06
N6.C1.D1.R1.S11: wrcmd2dqsstartlatency: 04
N0.C1.D1.R1.S08: RdPtrOffsetTxDqs: 06
N2.C2.D1.R1.S08: RdPtrOffsetTxDq: 07
N4.C1.D1.R1.S17: RdPtrOffsetTxDq: 06
N6.C1.D1.R1.S11: RdPtrOffsetTxDq: 05
N0.C1.D1.R1.S08: PiTxDqs: 57
N2.C2.D1.R1.S09: RdPtrOffsetTxDq: 08
N4.C1.D1.R1.S00: RdPtrOffsetTxDq: 08
N6.C1.D1.R1.S11: RdPtrOffsetTxDqs: 07
N0.C1.D1.R1.S09: wrcmd2dqsstartlatency: 04
N2.C2.D1.R1.S10: RdPtrOffsetTxDq: 07
N4.C1.D1.R1.S01: RdPtrOffsetTxDq: 08
N6.C1.D1.R1.S11: PiTxDqs: 30
N0.C1.D1.R1.S09: RdPtrOffsetTxDq: 06
N2.C2.D1.R1.S11: RdPtrOffsetTxDq: 07
N4.C1.D1.R1.S02: RdPtrOffsetTxDq: 07
N6.C1.D1.R1.S12: wrcmd2dqsstartlatency: 04
N0.C1.D1.R1.S09: RdPtrOffsetTxDqs: 07
N2.C2.D1.R1.S12: RdPtrOffsetTxDq: 07
N4.C1.D1.R1.S03: RdPtrOffsetTxDq: 07
N6.C1.D1.R1.S12: RdPtrOffsetTxDq: 05
N0.C1.D1.R1.S09: PiTxDqs: 54
N2.C2.D1.R1.S13: RdPtrOffsetTxDq: 06
N4.C1.D1.R1.S04: RdPtrOffsetTxDq: 07
N6.C1.D1.R1.S12: RdPtrOffsetTxDqs: 07
N0.C1.D1.R1.S10: wrcmd2dqsstartlatency: 04
N2.C2.D1.R1.S14: RdPtrOffsetTxDq: 07
N4.C1.D1.R1.S05: RdPtrOffsetTxDq: 07
N6.C1.D1.R1.S12: PiTxDqs: 15
N0.C1.D1.R1.S10: RdPtrOffsetTxDq: 06
N2.C2.D1.R1.S15: RdPtrOffsetTxDq: 07
N4.C1.D1.R1.S06: RdPtrOffsetTxDq: 07
N6.C1.D1.R1.S13: wrcmd2dqsstartlatency: 04
N0.C1.D1.R1.S10: RdPtrOffsetTxDqs: 07
N2.C2.D1.R1.S16: RdPtrOffsetTxDq: 07
N4.C1.D1.R1.S07: RdPtrOffsetTxDq: 07
N6.C1.D1.R1.S13: RdPtrOffsetTxDq: 05
N0.C1.D1.R1.S10: PiTxDqs: 40
N2.C2.D1.R1.S17: RdPtrOffsetTxDq: 07
N4.C1.D1.R1.S08: RdPtrOffsetTxDq: 07
N6.C1.D1.R1.S13: RdPtrOffsetTxDqs: 06
N0.C1.D1.R1.S11: wrcmd2dqsstartlatency: 04
N2.C2.D1.R1.S00: Total Delay in PI ticks: TxDQ = 977
N4.C1.D1.R1.S09: RdPtrOffsetTxDq: 08
N6.C1.D1.R1.S13: PiTxDqs: 44
N0.C1.D1.R1.S11: RdPtrOffsetTxDq: 05
N2.C2.D1.R1.S01: Total Delay in PI ticks: TxDQ = 961
N4.C1.D1.R1.S10: RdPtrOffsetTxDq: 08
N6.C1.D1.R1.S14: wrcmd2dqsstartlatency: 04
N0.C1.D1.R1.S11: RdPtrOffsetTxDqs: 07
N2.C2.D1.R1.S02: Total Delay in PI ticks: TxDQ = 950
N4.C1.D1.R1.S11: RdPtrOffsetTxDq: 07
N6.C1.D1.R1.S14: RdPtrOffsetTxDq: 05
N0.C1.D1.R1.S11: PiTxDqs: 32
N2.C2.D1.R1.S03: Total Delay in PI ticks: TxDQ = 937
N4.C1.D1.R1.S12: RdPtrOffsetTxDq: 07
N6.C1.D1.R1.S14: RdPtrOffsetTxDqs: 06
N0.C1.D1.R1.S12: wrcmd2dqsstartlatency: 04
N2.C2.D1.R1.S04: Total Delay in PI ticks: TxDQ = 896
N4.C1.D1.R1.S13: RdPtrOffsetTxDq: 07
N6.C1.D1.R1.S14: PiTxDqs: 59
N0.C1.D1.R1.S12: RdPtrOffsetTxDq: 05
N2.C2.D1.R1.S05: Total Delay in PI ticks: TxDQ = 925
N4.C1.D1.R1.S14: RdPtrOffsetTxDq: 07
N6.C1.D1.R1.S15: wrcmd2dqsstartlatency: 04
N0.C1.D1.R1.S12: RdPtrOffsetTxDqs: 07
N2.C2.D1.R1.S06: Total Delay in PI ticks: TxDQ = 919
N4.C1.D1.R1.S15: RdPtrOffsetTxDq: 07
N6.C1.D1.R1.S15: RdPtrOffsetTxDq: 05
N0.C1.D1.R1.S12: PiTxDqs: 16
N2.C2.D1.R1.S07: Total Delay in PI ticks: TxDQ = 944
N4.C1.D1.R1.S16: RdPtrOffsetTxDq: 07
N6.C1.D1.R1.S15: RdPtrOffsetTxDqs: 07
N0.C1.D1.R1.S13: wrcmd2dqsstartlatency: 04
N2.C2.D1.R1.S08: Total Delay in PI ticks: TxDQ = 908
N4.C1.D1.R1.S17: RdPtrOffsetTxDq: 07
N6.C1.D1.R1.S15: PiTxDqs: 04
N0.C1.D1.R1.S13: RdPtrOffsetTxDq: 05
N2.C2.D1.R1.S09: Total Delay in PI ticks: TxDQ = 971
N4.C1.D1.R1.S00: Total Delay in PI ticks: TxDQ = 984
N6.C1.D1.R1.S16: wrcmd2dqsstartlatency: 04
N0.C1.D1.R1.S13: RdPtrOffsetTxDqs: 06
N2.C2.D1.R1.S10: Total Delay in PI ticks: TxDQ = 962
N4.C1.D1.R1.S01: Total Delay in PI ticks: TxDQ = 966
N6.C1.D1.R1.S16: RdPtrOffsetTxDq: 05
N0.C1.D1.R1.S13: PiTxDqs: 46
N2.C2.D1.R1.S11: Total Delay in PI ticks: TxDQ = 951
N4.C1.D1.R1.S02: Total Delay in PI ticks: TxDQ = 955
N6.C1.D1.R1.S16: RdPtrOffsetTxDqs: 07
N0.C1.D1.R1.S14: wrcmd2dqsstartlatency: 04
N2.C2.D1.R1.S12: Total Delay in PI ticks: TxDQ = 936
N4.C1.D1.R1.S03: Total Delay in PI ticks: TxDQ = 940
N6.C1.D1.R1.S16: PiTxDqs: 26
N0.C1.D1.R1.S14: RdPtrOffsetTxDq: 05
N2.C2.D1.R1.S13: Total Delay in PI ticks: TxDQ = 896
N4.C1.D1.R1.S04: Total Delay in PI ticks: TxDQ = 906
N6.C1.D1.R1.S17: wrcmd2dqsstartlatency: 04
N0.C1.D1.R1.S14: RdPtrOffsetTxDqs: 06
N2.C2.D1.R1.S14: Total Delay in PI ticks: TxDQ = 923
N4.C1.D1.R1.S05: Total Delay in PI ticks: TxDQ = 922
N6.C1.D1.R1.S17: RdPtrOffsetTxDq: 05
N0.C1.D1.R1.S14: PiTxDqs: 60
N2.C2.D1.R1.S15: Total Delay in PI ticks: TxDQ = 920
N4.C1.D1.R1.S06: Total Delay in PI ticks: TxDQ = 933
N6.C1.D1.R1.S17: RdPtrOffsetTxDqs: 06
N0.C1.D1.R1.S15: wrcmd2dqsstartlatency: 04
N2.C2.D1.R1.S16: Total Delay in PI ticks: TxDQ = 941
N4.C1.D1.R1.S07: Total Delay in PI ticks: TxDQ = 949
N6.C1.D1.R1.S17: PiTxDqs: 57
N0.C1.D1.R1.S15: RdPtrOffsetTxDq: 05
N2.C2.D1.R1.S17: Total Delay in PI ticks: TxDQ = 907
N4.C1.D1.R1.S08: Total Delay in PI ticks: TxDQ = 919
N6.C1.D1.R1.S00: RdPtrOffsetTxDq: 07
N0.C1.D1.R1.S15: RdPtrOffsetTxDqs: 07
N2.C2: Calculating Optimimum DQ/DQS Values
N4.C1.D1.R1.S09: Total Delay in PI ticks: TxDQ = 979
N6.C1.D1.R1.S01: RdPtrOffsetTxDq: 07
N0.C1.D1.R1.S15: PiTxDqs: 09
N4.C1.D1.R1.S10: Total Delay in PI ticks: TxDQ = 966
N6.C1.D1.R1.S02: RdPtrOffsetTxDq: 06
N0.C1.D1.R1.S16: wrcmd2dqsstartlatency: 04
START_DATA_TX_DQ
N4.C1.D1.R1.S11: Total Delay in PI ticks: TxDQ = 956
N6.C1.D1.R1.S03: RdPtrOffsetTxDq: 06
N0.C1.D1.R1.S16: RdPtrOffsetTxDq: 05
N2.C2.S00: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 009, RdPtrOffsetTxDqs = 009
N4.C1.D1.R1.S12: Total Delay in PI ticks: TxDQ = 945
N6.C1.D1.R1.S04: RdPtrOffsetTxDq: 06
N0.C1.D1.R1.S16: RdPtrOffsetTxDqs: 07
N2.C2.S00: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 009, RdPtrOffsetTxDqs = 009
N4.C1.D1.R1.S13: Total Delay in PI ticks: TxDQ = 906
N6.C1.D1.R1.S05: RdPtrOffsetTxDq: 06
N0.C1.D1.R1.S16: PiTxDqs: 27
N2.C2.S01: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 009
N4.C1.D1.R1.S14: Total Delay in PI ticks: TxDQ = 921
N6.C1.D1.R1.S06: RdPtrOffsetTxDq: 06
N0.C1.D1.R1.S17: wrcmd2dqsstartlatency: 04
N2.C2.S01: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 009
N4.C1.D1.R1.S15: Total Delay in PI ticks: TxDQ = 933
N6.C1.D1.R1.S07: RdPtrOffsetTxDq: 06
N0.C1.D1.R1.S17: RdPtrOffsetTxDq: 05
N2.C2.S02: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 009
N4.C1.D1.R1.S16: Total Delay in PI ticks: TxDQ = 950
N6.C1.D1.R1.S08: RdPtrOffsetTxDq: 06
N0.C1.D1.R1.S17: RdPtrOffsetTxDqs: 06
N2.C2.S02: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 009
N4.C1.D1.R1.S17: Total Delay in PI ticks: TxDQ = 917
N6.C1.D1.R1.S09: RdPtrOffsetTxDq: 07
N0.C1.D1.R1.S17: PiTxDqs: 59
N2.C2.S03: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 009
N4.C1: Calculating Optimimum DQ/DQS Values
N6.C1.D1.R1.S10: RdPtrOffsetTxDq: 07
N0.C1.D1.R1.S00: RdPtrOffsetTxDq: 07
N2.C2.S03: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 009
N6.C1.D1.R1.S11: RdPtrOffsetTxDq: 06
N0.C1.D1.R1.S01: RdPtrOffsetTxDq: 07
N2.C2.S04: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 007, RdPtrOffsetTxDqs = 008
START_DATA_TX_DQ
N6.C1.D1.R1.S12: RdPtrOffsetTxDq: 06
N0.C1.D1.R1.S02: RdPtrOffsetTxDq: 06
N2.C2.S04: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 007, RdPtrOffsetTxDqs = 008
N4.C1.S00: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 009, RdPtrOffsetTxDqs = 009
N6.C1.D1.R1.S13: RdPtrOffsetTxDq: 06
N0.C1.D1.R1.S03: RdPtrOffsetTxDq: 06
N2.C2.S05: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 008
N4.C1.S00: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 009, RdPtrOffsetTxDqs = 009
N6.C1.D1.R1.S14: RdPtrOffsetTxDq: 06
N0.C1.D1.R1.S04: RdPtrOffsetTxDq: 06
N2.C2.S05: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 008
N4.C1.S01: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 009, RdPtrOffsetTxDqs = 009
N6.C1.D1.R1.S15: RdPtrOffsetTxDq: 06
N0.C1.D1.R1.S05: RdPtrOffsetTxDq: 06
N2.C2.S06: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 008
N4.C1.S01: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 009, RdPtrOffsetTxDqs = 009
N6.C1.D1.R1.S16: RdPtrOffsetTxDq: 06
N0.C1.D1.R1.S06: RdPtrOffsetTxDq: 06
N2.C2.S06: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 008
N4.C1.S02: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 009
N6.C1.D1.R1.S17: RdPtrOffsetTxDq: 06
N0.C1.D1.R1.S07: RdPtrOffsetTxDq: 06
N2.C2.S07: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 009
N4.C1.S02: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 009
N6.C1.D1.R1.S00: RdPtrOffsetTxDq: 08
N0.C1.D1.R1.S08: RdPtrOffsetTxDq: 06
N2.C2.S07: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 009
N4.C1.S03: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 009
N6.C1.D1.R1.S01: RdPtrOffsetTxDq: 08
N0.C1.D1.R1.S09: RdPtrOffsetTxDq: 07
N2.C2.S08: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 008
N4.C1.S03: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 009
N6.C1.D1.R1.S02: RdPtrOffsetTxDq: 07
N0.C1.D1.R1.S10: RdPtrOffsetTxDq: 07
N2.C2.S08: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 008
N4.C1.S04: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 008
N6.C1.D1.R1.S03: RdPtrOffsetTxDq: 07
N0.C1.D1.R1.S11: RdPtrOffsetTxDq: 06
N2.C2.D0.R0.S00: TxDqs: plus1 = 1, minus1 = 0, PI = 45, DB = 0
N4.C1.S04: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 008
N6.C1.D1.R1.S04: RdPtrOffsetTxDq: 07
N0.C1.D1.R1.S12: RdPtrOffsetTxDq: 06
N2.C2.D0.R0.S00: TxDq : plus1 = 1, minus1 = 0, PI = 15, DB = 1
N4.C1.S05: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 008
N6.C1.D1.R1.S05: RdPtrOffsetTxDq: 07
N0.C1.D1.R1.S13: RdPtrOffsetTxDq: 06
N2.C2.D0.R0.S01: TxDqs: plus1 = 1, minus1 = 0, PI = 31, DB = 0
N4.C1.S05: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 008
N6.C1.D1.R1.S06: RdPtrOffsetTxDq: 07
N0.C1.D1.R1.S14: RdPtrOffsetTxDq: 06
N2.C2.D0.R0.S01: TxDq : plus1 = 1, minus1 = 0, PI = 63, DB = 1
N4.C1.S06: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 009
N6.C1.D1.R1.S07: RdPtrOffsetTxDq: 07
N0.C1.D1.R1.S15: RdPtrOffsetTxDq: 06
N2.C2.D0.R0.S02: TxDqs: plus1 = 1, minus1 = 0, PI = 20, DB = 0
N4.C1.S06: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 009
N6.C1.D1.R1.S08: RdPtrOffsetTxDq: 07
N0.C1.D1.R1.S16: RdPtrOffsetTxDq: 06
N2.C2.D0.R0.S02: TxDq : plus1 = 1, minus1 = 0, PI = 55, DB = 1
N4.C1.S07: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 009
N6.C1.D1.R1.S09: RdPtrOffsetTxDq: 08
N0.C1.D1.R1.S17: RdPtrOffsetTxDq: 06
N2.C2.D0.R0.S03: TxDqs: plus1 = 1, minus1 = 0, PI = 02, DB = 1
N4.C1.S07: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 009
N6.C1.D1.R1.S10: RdPtrOffsetTxDq: 08
N0.C1.D1.R1.S00: RdPtrOffsetTxDq: 08
N2.C2.D0.R0.S03: TxDq : plus1 = 1, minus1 = 0, PI = 33, DB = 0
N4.C1.S08: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 008
N6.C1.D1.R1.S11: RdPtrOffsetTxDq: 07
N0.C1.D1.R1.S01: RdPtrOffsetTxDq: 08
N2.C2.D0.R0.S04: TxDqs: plus1 = 1, minus1 = 0, PI = 26, DB = 0
N4.C1.S08: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 008
N6.C1.D1.R1.S12: RdPtrOffsetTxDq: 07
N0.C1.D1.R1.S02: RdPtrOffsetTxDq: 07
N2.C2.D0.R0.S04: TxDq : plus1 = 1, minus1 = 0, PI = 60, DB = 1
N4.C1.D0.R0.S00: TxDqs: plus1 = 1, minus1 = 0, PI = 55, DB = 1
N6.C1.D1.R1.S13: RdPtrOffsetTxDq: 07
N0.C1.D1.R1.S03: RdPtrOffsetTxDq: 07
N2.C2.D0.R0.S05: TxDqs: plus1 = 1, minus1 = 0, PI = 55, DB = 1
N4.C1.D0.R0.S00: TxDq : plus1 = 1, minus1 = 0, PI = 23, DB = 0
N6.C1.D1.R1.S14: RdPtrOffsetTxDq: 07
N0.C1.D1.R1.S04: RdPtrOffsetTxDq: 07
N2.C2.D0.R0.S05: TxDq : plus1 = 1, minus1 = 0, PI = 21, DB = 0
N4.C1.D0.R0.S01: TxDqs: plus1 = 1, minus1 = 0, PI = 39, DB = 0
N6.C1.D1.R1.S15: RdPtrOffsetTxDq: 07
N0.C1.D1.R1.S05: RdPtrOffsetTxDq: 07
N2.C2.D0.R0.S06: TxDqs: plus1 = 1, minus1 = 0, PI = 53, DB = 1
N4.C1.D0.R0.S01: TxDq : plus1 = 1, minus1 = 0, PI = 06, DB = 1
N6.C1.D1.R1.S16: RdPtrOffsetTxDq: 07
N0.C1.D1.R1.S06: RdPtrOffsetTxDq: 07
N2.C2.D0.R0.S06: TxDq : plus1 = 1, minus1 = 0, PI = 22, DB = 0
N4.C1.D0.R0.S02: TxDqs: plus1 = 1, minus1 = 0, PI = 31, DB = 0
N6.C1.D1.R1.S17: RdPtrOffsetTxDq: 07
N0.C1.D1.R1.S07: RdPtrOffsetTxDq: 07
N2.C2.D0.R0.S07: TxDqs: plus1 = 1, minus1 = 0, PI = 12, DB = 1
N4.C1.D0.R0.S02: TxDq : plus1 = 1, minus1 = 0, PI = 61, DB = 1
N6.C1.D1.R1.S00: Total Delay in PI ticks: TxDQ = 983
N0.C1.D1.R1.S08: RdPtrOffsetTxDq: 07
N2.C2.D0.R0.S07: TxDq : plus1 = 1, minus1 = 0, PI = 42, DB = 0
N4.C1.D0.R0.S03: TxDqs: plus1 = 1, minus1 = 0, PI = 17, DB = 0
N6.C1.D1.R1.S01: Total Delay in PI ticks: TxDQ = 964
N0.C1.D1.R1.S09: RdPtrOffsetTxDq: 08
N2.C2.D0.R0.S08: TxDqs: plus1 = 1, minus1 = 0, PI = 46, DB = 0
N4.C1.D0.R0.S03: TxDq : plus1 = 1, minus1 = 0, PI = 47, DB = 0
N6.C1.D1.R1.S02: Total Delay in PI ticks: TxDQ = 956
N0.C1.D1.R1.S10: RdPtrOffsetTxDq: 08
N2.C2.D0.R0.S08: TxDq : plus1 = 1, minus1 = 0, PI = 14, DB = 1
N4.C1.D0.R0.S04: TxDqs: plus1 = 1, minus1 = 0, PI = 45, DB = 0
N6.C1.D1.R1.S03: Total Delay in PI ticks: TxDQ = 940
N0.C1.D1.R1.S11: RdPtrOffsetTxDq: 07
N2.C2.D0.R0.S09: TxDqs: plus1 = 1, minus1 = 0, PI = 46, DB = 0
N4.C1.D0.R0.S04: TxDq : plus1 = 1, minus1 = 0, PI = 12, DB = 1
N6.C1.D1.R1.S04: Total Delay in PI ticks: TxDQ = 907
N0.C1.D1.R1.S12: RdPtrOffsetTxDq: 07
N2.C2.D0.R0.S09: TxDq : plus1 = 1, minus1 = 0, PI = 13, DB = 1
N4.C1.D0.R0.S05: TxDqs: plus1 = 1, minus1 = 0, PI = 57, DB = 1
N6.C1.D1.R1.S05: Total Delay in PI ticks: TxDQ = 922
N0.C1.D1.R1.S13: RdPtrOffsetTxDq: 07
N2.C2.D0.R0.S10: TxDqs: plus1 = 1, minus1 = 0, PI = 30, DB = 0
N4.C1.D0.R0.S05: TxDq : plus1 = 1, minus1 = 0, PI = 23, DB = 0
N6.C1.D1.R1.S06: Total Delay in PI ticks: TxDQ = 933
N0.C1.D1.R1.S14: RdPtrOffsetTxDq: 07
N2.C2.D0.R0.S10: TxDq : plus1 = 1, minus1 = 0, PI = 63, DB = 1
N4.C1.D0.R0.S06: TxDqs: plus1 = 1, minus1 = 0, PI = 09, DB = 1
N6.C1.D1.R1.S07: Total Delay in PI ticks: TxDQ = 952
N0.C1.D1.R1.S15: RdPtrOffsetTxDq: 07
N2.C2.D0.R0.S11: TxDqs: plus1 = 1, minus1 = 0, PI = 20, DB = 0
N4.C1.D0.R0.S06: TxDq : plus1 = 1, minus1 = 0, PI = 40, DB = 0
N6.C1.D1.R1.S08: Total Delay in PI ticks: TxDQ = 919
N0.C1.D1.R1.S16: RdPtrOffsetTxDq: 07
N2.C2.D0.R0.S11: TxDq : plus1 = 1, minus1 = 0, PI = 53, DB = 1
N4.C1.D0.R0.S07: TxDqs: plus1 = 1, minus1 = 0, PI = 25, DB = 0
N6.C1.D1.R1.S09: Total Delay in PI ticks: TxDQ = 979
N0.C1.D1.R1.S17: RdPtrOffsetTxDq: 07
N2.C2.D0.R0.S12: TxDqs: plus1 = 1, minus1 = 0, PI = 04, DB = 1
N4.C1.D0.R0.S07: TxDq : plus1 = 1, minus1 = 0, PI = 54, DB = 1
N6.C1.D1.R1.S10: Total Delay in PI ticks: TxDQ = 967
N0.C1.D1.R1.S00: Total Delay in PI ticks: TxDQ = 981
N2.C2.D0.R0.S12: TxDq : plus1 = 1, minus1 = 0, PI = 35, DB = 0
N4.C1.D0.R0.S08: TxDqs: plus1 = 1, minus1 = 0, PI = 60, DB = 1
N6.C1.D1.R1.S11: Total Delay in PI ticks: TxDQ = 957
N0.C1.D1.R1.S01: Total Delay in PI ticks: TxDQ = 963
N2.C2.D0.R0.S13: TxDqs: plus1 = 1, minus1 = 0, PI = 26, DB = 0
N4.C1.D0.R0.S08: TxDq : plus1 = 1, minus1 = 0, PI = 27, DB = 0
N6.C1.D1.R1.S12: Total Delay in PI ticks: TxDQ = 943
N0.C1.D1.R1.S02: Total Delay in PI ticks: TxDQ = 954
N2.C2.D0.R0.S13: TxDq : plus1 = 1, minus1 = 0, PI = 59, DB = 1
N4.C1.D0.R0.S09: TxDqs: plus1 = 1, minus1 = 0, PI = 55, DB = 1
N6.C1.D1.R1.S13: Total Delay in PI ticks: TxDQ = 909
N0.C1.D1.R1.S03: Total Delay in PI ticks: TxDQ = 941
N2.C2.D0.R0.S14: TxDqs: plus1 = 1, minus1 = 0, PI = 54, DB = 1
N4.C1.D0.R0.S09: TxDq : plus1 = 1, minus1 = 0, PI = 21, DB = 0
N6.C1.D1.R1.S14: Total Delay in PI ticks: TxDQ = 924
N0.C1.D1.R1.S04: Total Delay in PI ticks: TxDQ = 908
N2.C2.D0.R0.S14: TxDq : plus1 = 1, minus1 = 0, PI = 22, DB = 0
N4.C1.D0.R0.S10: TxDqs: plus1 = 1, minus1 = 0, PI = 40, DB = 0
N6.C1.D1.R1.S15: Total Delay in PI ticks: TxDQ = 933
N0.C1.D1.R1.S05: Total Delay in PI ticks: TxDQ = 921
N2.C2.D0.R0.S15: TxDqs: plus1 = 1, minus1 = 0, PI = 53, DB = 1
N4.C1.D0.R0.S10: TxDq : plus1 = 1, minus1 = 0, PI = 07, DB = 1
N6.C1.D1.R1.S16: Total Delay in PI ticks: TxDQ = 953
N0.C1.D1.R1.S06: Total Delay in PI ticks: TxDQ = 933
N2.C2.D0.R0.S15: TxDq : plus1 = 1, minus1 = 0, PI = 21, DB = 0
N4.C1.D0.R0.S11: TxDqs: plus1 = 1, minus1 = 0, PI = 32, DB = 0
N6.C1.D1.R1.S17: Total Delay in PI ticks: TxDQ = 919
N0.C1.D1.R1.S07: Total Delay in PI ticks: TxDQ = 953
N2.C2.D0.R0.S16: TxDqs: plus1 = 1, minus1 = 0, PI = 13, DB = 1
N4.C1.D0.R0.S11: TxDq : plus1 = 1, minus1 = 0, PI = 63, DB = 1
N6.C1: Calculating Optimimum DQ/DQS Values
N0.C1.D1.R1.S08: Total Delay in PI ticks: TxDQ = 918
N2.C2.D0.R0.S16: TxDq : plus1 = 1, minus1 = 0, PI = 44, DB = 0
N4.C1.D0.R0.S12: TxDqs: plus1 = 1, minus1 = 0, PI = 16, DB = 0
N0.C1.D1.R1.S09: Total Delay in PI ticks: TxDQ = 978
N2.C2.D0.R0.S17: TxDqs: plus1 = 1, minus1 = 0, PI = 45, DB = 0
N4.C1.D0.R0.S12: TxDq : plus1 = 1, minus1 = 0, PI = 48, DB = 0
START_DATA_TX_DQ
N0.C1.D1.R1.S10: Total Delay in PI ticks: TxDQ = 965
N2.C2.D0.R0.S17: TxDq : plus1 = 1, minus1 = 0, PI = 13, DB = 1
N4.C1.D0.R0.S13: TxDqs: plus1 = 1, minus1 = 0, PI = 46, DB = 0
N6.C1.S00: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 009, RdPtrOffsetTxDqs = 009
N0.C1.D1.R1.S11: Total Delay in PI ticks: TxDQ = 958
N2.C2.D0.R1.S00: TxDqs: plus1 = 1, minus1 = 0, PI = 45, DB = 0
N4.C1.D0.R0.S13: TxDq : plus1 = 1, minus1 = 0, PI = 12, DB = 1
N6.C1.S00: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 009, RdPtrOffsetTxDqs = 009
N0.C1.D1.R1.S12: Total Delay in PI ticks: TxDQ = 943
N2.C2.D0.R1.S00: TxDq : plus1 = 1, minus1 = 0, PI = 15, DB = 1
N4.C1.D0.R0.S14: TxDqs: plus1 = 1, minus1 = 0, PI = 60, DB = 1
N6.C1.S01: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 009, RdPtrOffsetTxDqs = 009
N0.C1.D1.R1.S13: Total Delay in PI ticks: TxDQ = 909
N2.C2.D0.R1.S01: TxDqs: plus1 = 1, minus1 = 0, PI = 31, DB = 0
N4.C1.D0.R0.S14: TxDq : plus1 = 1, minus1 = 0, PI = 26, DB = 0
N6.C1.S01: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 009, RdPtrOffsetTxDqs = 009
N0.C1.D1.R1.S14: Total Delay in PI ticks: TxDQ = 923
N2.C2.D0.R1.S01: TxDq : plus1 = 1, minus1 = 0, PI = 63, DB = 1
N4.C1.D0.R0.S15: TxDqs: plus1 = 1, minus1 = 0, PI = 09, DB = 1
N6.C1.S02: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 009
N0.C1.D1.R1.S15: Total Delay in PI ticks: TxDQ = 937
N2.C2.D0.R1.S02: TxDqs: plus1 = 1, minus1 = 0, PI = 20, DB = 0
N4.C1.D0.R0.S15: TxDq : plus1 = 1, minus1 = 0, PI = 42, DB = 0
N6.C1.S02: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 009
N0.C1.D1.R1.S16: Total Delay in PI ticks: TxDQ = 953
N2.C2.D0.R1.S02: TxDq : plus1 = 1, minus1 = 0, PI = 55, DB = 1
N4.C1.D0.R0.S16: TxDqs: plus1 = 1, minus1 = 0, PI = 25, DB = 0
N6.C1.S03: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 009
N0.C1.D1.R1.S17: Total Delay in PI ticks: TxDQ = 920
N2.C2.D0.R1.S03: TxDqs: plus1 = 1, minus1 = 0, PI = 02, DB = 1
N4.C1.D0.R0.S16: TxDq : plus1 = 1, minus1 = 0, PI = 55, DB = 1
N6.C1.S03: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 009
N0.C1: Calculating Optimimum DQ/DQS Values
N2.C2.D0.R1.S03: TxDq : plus1 = 1, minus1 = 0, PI = 33, DB = 0
N4.C1.D0.R0.S17: TxDqs: plus1 = 1, minus1 = 0, PI = 61, DB = 1
N6.C1.S04: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 008
START_DATA_TX_DQ
N2.C2.D0.R1.S04: TxDqs: plus1 = 1, minus1 = 0, PI = 26, DB = 0
N4.C1.D0.R0.S17: TxDq : plus1 = 1, minus1 = 0, PI = 29, DB = 0
N6.C1.S04: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 008
N0.C1.S00: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 009, RdPtrOffsetTxDqs = 009
N2.C2.D0.R1.S04: TxDq : plus1 = 1, minus1 = 0, PI = 60, DB = 1
N4.C1.D0.R1.S00: TxDqs: plus1 = 1, minus1 = 0, PI = 55, DB = 1
N6.C1.S05: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 008
N0.C1.S00: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 009, RdPtrOffsetTxDqs = 009
N2.C2.D0.R1.S05: TxDqs: plus1 = 1, minus1 = 0, PI = 55, DB = 1
N4.C1.D0.R1.S00: TxDq : plus1 = 1, minus1 = 0, PI = 23, DB = 0
N6.C1.S05: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 008
N0.C1.S01: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 009, RdPtrOffsetTxDqs = 009
N2.C2.D0.R1.S05: TxDq : plus1 = 1, minus1 = 0, PI = 21, DB = 0
N4.C1.D0.R1.S01: TxDqs: plus1 = 1, minus1 = 0, PI = 39, DB = 0
N6.C1.S06: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 009
N0.C1.S01: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 009, RdPtrOffsetTxDqs = 009
N2.C2.D0.R1.S06: TxDqs: plus1 = 1, minus1 = 0, PI = 53, DB = 1
N4.C1.D0.R1.S01: TxDq : plus1 = 1, minus1 = 0, PI = 06, DB = 1
N6.C1.S06: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 009
N0.C1.S02: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 009
N2.C2.D0.R1.S06: TxDq : plus1 = 1, minus1 = 0, PI = 22, DB = 0
N4.C1.D0.R1.S02: TxDqs: plus1 = 1, minus1 = 0, PI = 31, DB = 0
N6.C1.S07: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 009
N0.C1.S02: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 009
N2.C2.D0.R1.S07: TxDqs: plus1 = 1, minus1 = 0, PI = 12, DB = 1
N4.C1.D0.R1.S02: TxDq : plus1 = 1, minus1 = 0, PI = 61, DB = 1
N6.C1.S07: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 009
N0.C1.S03: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 009
N2.C2.D0.R1.S07: TxDq : plus1 = 1, minus1 = 0, PI = 42, DB = 0
N4.C1.D0.R1.S03: TxDqs: plus1 = 1, minus1 = 0, PI = 17, DB = 0
N6.C1.S08: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 008
N0.C1.S03: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 009
N2.C2.D0.R1.S08: TxDqs: plus1 = 1, minus1 = 0, PI = 46, DB = 0
N4.C1.D0.R1.S03: TxDq : plus1 = 1, minus1 = 0, PI = 47, DB = 0
N6.C1.S08: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 008
N0.C1.S04: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 008
N2.C2.D0.R1.S08: TxDq : plus1 = 1, minus1 = 0, PI = 14, DB = 1
N4.C1.D0.R1.S04: TxDqs: plus1 = 1, minus1 = 0, PI = 45, DB = 0
N6.C1.D0.R0.S00: TxDqs: plus1 = 1, minus1 = 0, PI = 50, DB = 1
N0.C1.S04: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 008
N2.C2.D0.R1.S09: TxDqs: plus1 = 1, minus1 = 0, PI = 46, DB = 0
N4.C1.D0.R1.S04: TxDq : plus1 = 1, minus1 = 0, PI = 12, DB = 1
N6.C1.D0.R0.S00: TxDq : plus1 = 1, minus1 = 0, PI = 18, DB = 0
N0.C1.S05: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 008
N2.C2.D0.R1.S09: TxDq : plus1 = 1, minus1 = 0, PI = 13, DB = 1
N4.C1.D0.R1.S05: TxDqs: plus1 = 1, minus1 = 0, PI = 57, DB = 1
N6.C1.D0.R0.S01: TxDqs: plus1 = 1, minus1 = 0, PI = 33, DB = 0
N0.C1.S05: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 008
N2.C2.D0.R1.S10: TxDqs: plus1 = 1, minus1 = 0, PI = 30, DB = 0
N4.C1.D0.R1.S05: TxDq : plus1 = 1, minus1 = 0, PI = 23, DB = 0
N6.C1.D0.R0.S01: TxDq : plus1 = 1, minus1 = 0, PI = 01, DB = 1
N0.C1.S06: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 009
N2.C2.D0.R1.S10: TxDq : plus1 = 1, minus1 = 0, PI = 63, DB = 1
N4.C1.D0.R1.S06: TxDqs: plus1 = 1, minus1 = 0, PI = 09, DB = 1
N6.C1.D0.R0.S02: TxDqs: plus1 = 1, minus1 = 0, PI = 23, DB = 0
N0.C1.S06: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 009
N2.C2.D0.R1.S11: TxDqs: plus1 = 1, minus1 = 0, PI = 20, DB = 0
N4.C1.D0.R1.S06: TxDq : plus1 = 1, minus1 = 0, PI = 40, DB = 0
N6.C1.D0.R0.S02: TxDq : plus1 = 1, minus1 = 0, PI = 56, DB = 1
N0.C1.S07: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 009
N2.C2.D0.R1.S11: TxDq : plus1 = 1, minus1 = 0, PI = 53, DB = 1
N4.C1.D0.R1.S07: TxDqs: plus1 = 1, minus1 = 0, PI = 25, DB = 0
N6.C1.D0.R0.S03: TxDqs: plus1 = 1, minus1 = 0, PI = 07, DB = 1
N0.C1.S07: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 009
N2.C2.D0.R1.S12: TxDqs: plus1 = 1, minus1 = 0, PI = 04, DB = 1
N4.C1.D0.R1.S07: TxDq : plus1 = 1, minus1 = 0, PI = 54, DB = 1
N6.C1.D0.R0.S03: TxDq : plus1 = 1, minus1 = 0, PI = 40, DB = 0
N0.C1.S08: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 008
N2.C2.D0.R1.S12: TxDq : plus1 = 1, minus1 = 0, PI = 35, DB = 0
N4.C1.D0.R1.S08: TxDqs: plus1 = 1, minus1 = 0, PI = 60, DB = 1
N6.C1.D0.R0.S04: TxDqs: plus1 = 1, minus1 = 0, PI = 40, DB = 0
N0.C1.S08: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 008
N2.C2.D0.R1.S13: TxDqs: plus1 = 1, minus1 = 0, PI = 26, DB = 0
N4.C1.D0.R1.S08: TxDq : plus1 = 1, minus1 = 0, PI = 27, DB = 0
N6.C1.D0.R0.S04: TxDq : plus1 = 1, minus1 = 0, PI = 08, DB = 1
N0.C1.D0.R0.S00: TxDqs: plus1 = 1, minus1 = 0, PI = 53, DB = 1
N2.C2.D0.R1.S13: TxDq : plus1 = 1, minus1 = 0, PI = 59, DB = 1
N4.C1.D0.R1.S09: TxDqs: plus1 = 1, minus1 = 0, PI = 55, DB = 1
N6.C1.D0.R0.S05: TxDqs: plus1 = 1, minus1 = 0, PI = 53, DB = 1
N0.C1.D0.R0.S00: TxDq : plus1 = 1, minus1 = 0, PI = 22, DB = 0
N2.C2.D0.R1.S14: TxDqs: plus1 = 1, minus1 = 0, PI = 54, DB = 1
N4.C1.D0.R1.S09: TxDq : plus1 = 1, minus1 = 0, PI = 21, DB = 0
N6.C1.D0.R0.S05: TxDq : plus1 = 1, minus1 = 0, PI = 20, DB = 0
N0.C1.D0.R0.S01: TxDqs: plus1 = 1, minus1 = 0, PI = 35, DB = 0
N2.C2.D0.R1.S14: TxDq : plus1 = 1, minus1 = 0, PI = 22, DB = 0
N4.C1.D0.R1.S10: TxDqs: plus1 = 1, minus1 = 0, PI = 40, DB = 0
N6.C1.D0.R0.S06: TxDqs: plus1 = 1, minus1 = 0, PI = 03, DB = 1
N0.C1.D0.R0.S01: TxDq : plus1 = 1, minus1 = 0, PI = 02, DB = 1
N2.C2.D0.R1.S15: TxDqs: plus1 = 1, minus1 = 0, PI = 53, DB = 1
N4.C1.D0.R1.S10: TxDq : plus1 = 1, minus1 = 0, PI = 07, DB = 1
N6.C1.D0.R0.S06: TxDq : plus1 = 1, minus1 = 0, PI = 37, DB = 0
N0.C1.D0.R0.S02: TxDqs: plus1 = 1, minus1 = 0, PI = 29, DB = 0
N2.C2.D0.R1.S15: TxDq : plus1 = 1, minus1 = 0, PI = 21, DB = 0
N4.C1.D0.R1.S11: TxDqs: plus1 = 1, minus1 = 0, PI = 32, DB = 0
N6.C1.D0.R0.S07: TxDqs: plus1 = 1, minus1 = 0, PI = 20, DB = 0
N0.C1.D0.R0.S02: TxDq : plus1 = 1, minus1 = 0, PI = 59, DB = 1
N2.C2.D0.R1.S16: TxDqs: plus1 = 1, minus1 = 0, PI = 13, DB = 1
N4.C1.D0.R1.S11: TxDq : plus1 = 1, minus1 = 0, PI = 63, DB = 1
N6.C1.D0.R0.S07: TxDq : plus1 = 1, minus1 = 0, PI = 50, DB = 1
N0.C1.D0.R0.S03: TxDqs: plus1 = 1, minus1 = 0, PI = 12, DB = 1
N2.C2.D0.R1.S16: TxDq : plus1 = 1, minus1 = 0, PI = 44, DB = 0
N4.C1.D0.R1.S12: TxDqs: plus1 = 1, minus1 = 0, PI = 16, DB = 0
N6.C1.D0.R0.S08: TxDqs: plus1 = 1, minus1 = 0, PI = 55, DB = 1
N0.C1.D0.R0.S03: TxDq : plus1 = 1, minus1 = 0, PI = 43, DB = 0
N2.C2.D0.R1.S17: TxDqs: plus1 = 1, minus1 = 0, PI = 45, DB = 0
N4.C1.D0.R1.S12: TxDq : plus1 = 1, minus1 = 0, PI = 48, DB = 0
N6.C1.D0.R0.S08: TxDq : plus1 = 1, minus1 = 0, PI = 24, DB = 0
N0.C1.D0.R0.S04: TxDqs: plus1 = 1, minus1 = 0, PI = 41, DB = 0
N2.C2.D0.R1.S17: TxDq : plus1 = 1, minus1 = 0, PI = 13, DB = 1
N4.C1.D0.R1.S13: TxDqs: plus1 = 1, minus1 = 0, PI = 46, DB = 0
N6.C1.D0.R0.S09: TxDqs: plus1 = 1, minus1 = 0, PI = 49, DB = 1
N0.C1.D0.R0.S04: TxDq : plus1 = 1, minus1 = 0, PI = 08, DB = 1
N2.C2.D1.R0.S00: TxDqs: plus1 = 1, minus1 = 0, PI = 49, DB = 1
N4.C1.D0.R1.S13: TxDq : plus1 = 1, minus1 = 0, PI = 12, DB = 1
N6.C1.D0.R0.S09: TxDq : plus1 = 1, minus1 = 0, PI = 17, DB = 0
N0.C1.D0.R0.S05: TxDqs: plus1 = 1, minus1 = 0, PI = 56, DB = 1
N2.C2.D1.R0.S00: TxDq : plus1 = 1, minus1 = 0, PI = 18, DB = 0
N4.C1.D0.R1.S14: TxDqs: plus1 = 1, minus1 = 0, PI = 60, DB = 1
N6.C1.D0.R0.S10: TxDqs: plus1 = 1, minus1 = 0, PI = 32, DB = 0
N0.C1.D0.R0.S05: TxDq : plus1 = 1, minus1 = 0, PI = 22, DB = 0
N2.C2.D1.R0.S01: TxDqs: plus1 = 1, minus1 = 0, PI = 35, DB = 0
N4.C1.D0.R1.S14: TxDq : plus1 = 1, minus1 = 0, PI = 26, DB = 0
N6.C1.D0.R0.S10: TxDq : plus1 = 1, minus1 = 0, PI = 01, DB = 1
N0.C1.D0.R0.S06: TxDqs: plus1 = 1, minus1 = 0, PI = 08, DB = 1
N2.C2.D1.R0.S01: TxDq : plus1 = 0, minus1 = 1, PI = 03, DB = 1
N4.C1.D0.R1.S15: TxDqs: plus1 = 1, minus1 = 0, PI = 09, DB = 1
N6.C1.D0.R0.S11: TxDqs: plus1 = 1, minus1 = 0, PI = 25, DB = 0
N0.C1.D0.R0.S06: TxDq : plus1 = 1, minus1 = 0, PI = 39, DB = 0
N2.C2.D1.R0.S02: TxDqs: plus1 = 1, minus1 = 0, PI = 23, DB = 0
N4.C1.D0.R1.S15: TxDq : plus1 = 1, minus1 = 0, PI = 42, DB = 0
N6.C1.D0.R0.S11: TxDq : plus1 = 1, minus1 = 0, PI = 57, DB = 1
N0.C1.D0.R0.S07: TxDqs: plus1 = 1, minus1 = 0, PI = 24, DB = 0
N2.C2.D1.R0.S02: TxDq : plus1 = 1, minus1 = 0, PI = 57, DB = 1
N4.C1.D0.R1.S16: TxDqs: plus1 = 1, minus1 = 0, PI = 25, DB = 0
N6.C1.D0.R0.S12: TxDqs: plus1 = 1, minus1 = 0, PI = 08, DB = 1
N0.C1.D0.R0.S07: TxDq : plus1 = 1, minus1 = 0, PI = 55, DB = 1
N2.C2.D1.R0.S03: TxDqs: plus1 = 1, minus1 = 0, PI = 11, DB = 1
N4.C1.D0.R1.S16: TxDq : plus1 = 1, minus1 = 0, PI = 55, DB = 1
N6.C1.D0.R0.S12: TxDq : plus1 = 1, minus1 = 0, PI = 41, DB = 0
N0.C1.D0.R0.S08: TxDqs: plus1 = 1, minus1 = 0, PI = 56, DB = 1
N2.C2.D1.R0.S03: TxDq : plus1 = 1, minus1 = 0, PI = 42, DB = 0
N4.C1.D0.R1.S17: TxDqs: plus1 = 1, minus1 = 0, PI = 61, DB = 1
N6.C1.D0.R0.S13: TxDqs: plus1 = 1, minus1 = 0, PI = 38, DB = 0
N0.C1.D0.R0.S08: TxDq : plus1 = 1, minus1 = 0, PI = 23, DB = 0
N2.C2.D1.R0.S04: TxDqs: plus1 = 1, minus1 = 0, PI = 32, DB = 0
N4.C1.D0.R1.S17: TxDq : plus1 = 1, minus1 = 0, PI = 29, DB = 0
N6.C1.D0.R0.S13: TxDq : plus1 = 1, minus1 = 0, PI = 08, DB = 1
N0.C1.D0.R0.S09: TxDqs: plus1 = 1, minus1 = 0, PI = 53, DB = 1
N2.C2.D1.R0.S04: TxDq : plus1 = 0, minus1 = 1, PI = 01, DB = 1
N4.C1.D1.R0.S00: TxDqs: plus1 = 1, minus1 = 0, PI = 59, DB = 1
N6.C1.D0.R0.S14: TxDqs: plus1 = 1, minus1 = 0, PI = 51, DB = 1
N0.C1.D0.R0.S09: TxDq : plus1 = 1, minus1 = 0, PI = 19, DB = 0
N2.C2.D1.R0.S05: TxDqs: plus1 = 1, minus1 = 0, PI = 62, DB = 1
N4.C1.D1.R0.S00: TxDq : plus1 = 1, minus1 = 0, PI = 25, DB = 0
N6.C1.D0.R0.S14: TxDq : plus1 = 1, minus1 = 0, PI = 19, DB = 0
N0.C1.D0.R0.S10: TxDqs: plus1 = 1, minus1 = 0, PI = 36, DB = 0
N2.C2.D1.R0.S05: TxDq : plus1 = 1, minus1 = 0, PI = 30, DB = 0
N4.C1.D1.R0.S01: TxDqs: plus1 = 1, minus1 = 0, PI = 43, DB = 0
N6.C1.D0.R0.S15: TxDqs: plus1 = 1, minus1 = 0, PI = 02, DB = 1
N0.C1.D0.R0.S10: TxDq : plus1 = 1, minus1 = 0, PI = 03, DB = 1
N2.C2.D1.R0.S06: TxDqs: plus1 = 1, minus1 = 0, PI = 58, DB = 1
N4.C1.D1.R0.S01: TxDq : plus1 = 1, minus1 = 0, PI = 08, DB = 1
N6.C1.D0.R0.S15: TxDq : plus1 = 1, minus1 = 0, PI = 37, DB = 0
N0.C1.D0.R0.S11: TxDqs: plus1 = 1, minus1 = 0, PI = 29, DB = 0
N2.C2.D1.R0.S06: TxDq : plus1 = 1, minus1 = 0, PI = 25, DB = 0
N4.C1.D1.R0.S02: TxDqs: plus1 = 1, minus1 = 0, PI = 33, DB = 0
N6.C1.D0.R0.S16: TxDqs: plus1 = 1, minus1 = 0, PI = 20, DB = 0
N0.C1.D0.R0.S11: TxDq : plus1 = 1, minus1 = 0, PI = 61, DB = 1
N2.C2.D1.R0.S07: TxDqs: plus1 = 1, minus1 = 0, PI = 18, DB = 0
N4.C1.D1.R0.S02: TxDq : plus1 = 1, minus1 = 0, PI = 62, DB = 1
N6.C1.D0.R0.S16: TxDq : plus1 = 1, minus1 = 0, PI = 52, DB = 1
N0.C1.D0.R0.S12: TxDqs: plus1 = 1, minus1 = 0, PI = 12, DB = 1
N2.C2.D1.R0.S07: TxDq : plus1 = 1, minus1 = 0, PI = 49, DB = 1
N4.C1.D1.R0.S03: TxDqs: plus1 = 1, minus1 = 0, PI = 18, DB = 0
N6.C1.D0.R0.S17: TxDqs: plus1 = 1, minus1 = 0, PI = 53, DB = 1
N0.C1.D0.R0.S12: TxDq : plus1 = 1, minus1 = 0, PI = 44, DB = 0
N2.C2.D1.R0.S08: TxDqs: plus1 = 1, minus1 = 0, PI = 48, DB = 0
N4.C1.D1.R0.S03: TxDq : plus1 = 1, minus1 = 0, PI = 45, DB = 0
N6.C1.D0.R0.S17: TxDq : plus1 = 1, minus1 = 0, PI = 21, DB = 0
N0.C1.D0.R0.S13: TxDqs: plus1 = 1, minus1 = 0, PI = 42, DB = 0
N2.C2.D1.R0.S08: TxDq : plus1 = 1, minus1 = 0, PI = 13, DB = 1
N4.C1.D1.R0.S04: TxDqs: plus1 = 1, minus1 = 0, PI = 48, DB = 0
N6.C1.D0.R1.S00: TxDqs: plus1 = 1, minus1 = 0, PI = 50, DB = 1
N0.C1.D0.R0.S13: TxDq : plus1 = 1, minus1 = 0, PI = 09, DB = 1
N2.C2.D1.R0.S09: TxDqs: plus1 = 1, minus1 = 0, PI = 48, DB = 0
N4.C1.D1.R0.S04: TxDq : plus1 = 1, minus1 = 0, PI = 11, DB = 1
N6.C1.D0.R1.S00: TxDq : plus1 = 1, minus1 = 0, PI = 18, DB = 0
N0.C1.D0.R0.S14: TxDqs: plus1 = 1, minus1 = 0, PI = 57, DB = 1
N2.C2.D1.R0.S09: TxDq : plus1 = 1, minus1 = 0, PI = 13, DB = 1
N4.C1.D1.R0.S05: TxDqs: plus1 = 1, minus1 = 0, PI = 61, DB = 1
N6.C1.D0.R1.S01: TxDqs: plus1 = 1, minus1 = 0, PI = 33, DB = 0
N0.C1.D0.R0.S14: TxDq : plus1 = 1, minus1 = 0, PI = 23, DB = 0
N2.C2.D1.R0.S10: TxDqs: plus1 = 1, minus1 = 0, PI = 36, DB = 0
N4.C1.D1.R0.S05: TxDq : plus1 = 1, minus1 = 0, PI = 26, DB = 0
N6.C1.D0.R1.S01: TxDq : plus1 = 1, minus1 = 0, PI = 01, DB = 1
N0.C1.D0.R0.S15: TxDqs: plus1 = 1, minus1 = 0, PI = 06, DB = 1
N2.C2.D1.R0.S10: TxDq : plus1 = 0, minus1 = 1, PI = 03, DB = 1
N4.C1.D1.R0.S06: TxDqs: plus1 = 1, minus1 = 0, PI = 10, DB = 1
N6.C1.D0.R1.S02: TxDqs: plus1 = 1, minus1 = 0, PI = 23, DB = 0
N0.C1.D0.R0.S15: TxDq : plus1 = 1, minus1 = 0, PI = 38, DB = 0
N2.C2.D1.R0.S11: TxDqs: plus1 = 1, minus1 = 0, PI = 24, DB = 0
N4.C1.D1.R0.S06: TxDq : plus1 = 1, minus1 = 0, PI = 39, DB = 0
N6.C1.D0.R1.S02: TxDq : plus1 = 1, minus1 = 0, PI = 56, DB = 1
N0.C1.D0.R0.S16: TxDqs: plus1 = 1, minus1 = 0, PI = 25, DB = 0
N2.C2.D1.R0.S11: TxDq : plus1 = 1, minus1 = 0, PI = 57, DB = 1
N4.C1.D1.R0.S07: TxDqs: plus1 = 1, minus1 = 0, PI = 27, DB = 0
N6.C1.D0.R1.S03: TxDqs: plus1 = 1, minus1 = 0, PI = 07, DB = 1
N0.C1.D0.R0.S16: TxDq : plus1 = 1, minus1 = 0, PI = 55, DB = 1
N2.C2.D1.R0.S12: TxDqs: plus1 = 1, minus1 = 0, PI = 10, DB = 1
N4.C1.D1.R0.S07: TxDq : plus1 = 1, minus1 = 0, PI = 55, DB = 1
N6.C1.D0.R1.S03: TxDq : plus1 = 1, minus1 = 0, PI = 40, DB = 0
N0.C1.D0.R0.S17: TxDqs: plus1 = 1, minus1 = 0, PI = 57, DB = 1
N2.C2.D1.R0.S12: TxDq : plus1 = 1, minus1 = 0, PI = 41, DB = 0
N4.C1.D1.R0.S08: TxDqs: plus1 = 1, minus1 = 0, PI = 60, DB = 1
N6.C1.D0.R1.S04: TxDqs: plus1 = 1, minus1 = 0, PI = 40, DB = 0
N0.C1.D0.R0.S17: TxDq : plus1 = 1, minus1 = 0, PI = 26, DB = 0
N2.C2.D1.R0.S13: TxDqs: plus1 = 1, minus1 = 0, PI = 33, DB = 0
N4.C1.D1.R0.S08: TxDq : plus1 = 1, minus1 = 0, PI = 25, DB = 0
N6.C1.D0.R1.S04: TxDq : plus1 = 1, minus1 = 0, PI = 08, DB = 1
N0.C1.D0.R1.S00: TxDqs: plus1 = 1, minus1 = 0, PI = 53, DB = 1
N2.C2.D1.R0.S13: TxDq : plus1 = 0, minus1 = 1, PI = 01, DB = 1
N4.C1.D1.R0.S09: TxDqs: plus1 = 1, minus1 = 0, PI = 57, DB = 1
N6.C1.D0.R1.S05: TxDqs: plus1 = 1, minus1 = 0, PI = 53, DB = 1
N0.C1.D0.R1.S00: TxDq : plus1 = 1, minus1 = 0, PI = 22, DB = 0
N2.C2.D1.R0.S14: TxDqs: plus1 = 1, minus1 = 0, PI = 61, DB = 1
N4.C1.D1.R0.S09: TxDq : plus1 = 1, minus1 = 0, PI = 21, DB = 0
N6.C1.D0.R1.S05: TxDq : plus1 = 1, minus1 = 0, PI = 20, DB = 0
N0.C1.D0.R1.S01: TxDqs: plus1 = 1, minus1 = 0, PI = 35, DB = 0
N2.C2.D1.R0.S14: TxDq : plus1 = 1, minus1 = 0, PI = 29, DB = 0
N4.C1.D1.R0.S10: TxDqs: plus1 = 1, minus1 = 0, PI = 42, DB = 0
N6.C1.D0.R1.S06: TxDqs: plus1 = 1, minus1 = 0, PI = 03, DB = 1
N0.C1.D0.R1.S01: TxDq : plus1 = 1, minus1 = 0, PI = 02, DB = 1
N2.C2.D1.R0.S15: TxDqs: plus1 = 1, minus1 = 0, PI = 58, DB = 1
N4.C1.D1.R0.S10: TxDq : plus1 = 1, minus1 = 0, PI = 07, DB = 1
N6.C1.D0.R1.S06: TxDq : plus1 = 1, minus1 = 0, PI = 37, DB = 0
N0.C1.D0.R1.S02: TxDqs: plus1 = 1, minus1 = 0, PI = 29, DB = 0
N2.C2.D1.R0.S15: TxDq : plus1 = 1, minus1 = 0, PI = 26, DB = 0
N4.C1.D1.R0.S11: TxDqs: plus1 = 1, minus1 = 0, PI = 32, DB = 0
N6.C1.D0.R1.S07: TxDqs: plus1 = 1, minus1 = 0, PI = 20, DB = 0
N0.C1.D0.R1.S02: TxDq : plus1 = 1, minus1 = 0, PI = 59, DB = 1
N2.C2.D1.R0.S16: TxDqs: plus1 = 1, minus1 = 0, PI = 17, DB = 0
N4.C1.D1.R0.S11: TxDq : plus1 = 1, minus1 = 0, PI = 61, DB = 1
N6.C1.D0.R1.S07: TxDq : plus1 = 1, minus1 = 0, PI = 50, DB = 1
N0.C1.D0.R1.S03: TxDqs: plus1 = 1, minus1 = 0, PI = 12, DB = 1
N2.C2.D1.R0.S16: TxDq : plus1 = 1, minus1 = 0, PI = 48, DB = 0
N4.C1.D1.R0.S12: TxDqs: plus1 = 1, minus1 = 0, PI = 18, DB = 0
N6.C1.D0.R1.S08: TxDqs: plus1 = 1, minus1 = 0, PI = 55, DB = 1
N0.C1.D0.R1.S03: TxDq : plus1 = 1, minus1 = 0, PI = 43, DB = 0
N2.C2.D1.R0.S17: TxDqs: plus1 = 1, minus1 = 0, PI = 47, DB = 0
N4.C1.D1.R0.S12: TxDq : plus1 = 1, minus1 = 0, PI = 49, DB = 1
N6.C1.D0.R1.S08: TxDq : plus1 = 1, minus1 = 0, PI = 24, DB = 0
N0.C1.D0.R1.S04: TxDqs: plus1 = 1, minus1 = 0, PI = 41, DB = 0
N2.C2.D1.R0.S17: TxDq : plus1 = 1, minus1 = 0, PI = 13, DB = 1
N4.C1.D1.R0.S13: TxDqs: plus1 = 1, minus1 = 0, PI = 47, DB = 0
N6.C1.D0.R1.S09: TxDqs: plus1 = 1, minus1 = 0, PI = 49, DB = 1
N0.C1.D0.R1.S04: TxDq : plus1 = 1, minus1 = 0, PI = 08, DB = 1
N2.C2.D1.R1.S00: TxDqs: plus1 = 1, minus1 = 0, PI = 49, DB = 1
N4.C1.D1.R0.S13: TxDq : plus1 = 1, minus1 = 0, PI = 11, DB = 1
N6.C1.D0.R1.S09: TxDq : plus1 = 1, minus1 = 0, PI = 17, DB = 0
N0.C1.D0.R1.S05: TxDqs: plus1 = 1, minus1 = 0, PI = 56, DB = 1
N2.C2.D1.R1.S00: TxDq : plus1 = 1, minus1 = 0, PI = 18, DB = 0
N4.C1.D1.R0.S14: TxDqs: plus1 = 1, minus1 = 0, PI = 61, DB = 1
N6.C1.D0.R1.S10: TxDqs: plus1 = 1, minus1 = 0, PI = 32, DB = 0
N0.C1.D0.R1.S05: TxDq : plus1 = 1, minus1 = 0, PI = 22, DB = 0
N2.C2.D1.R1.S01: TxDqs: plus1 = 1, minus1 = 0, PI = 35, DB = 0
N4.C1.D1.R0.S14: TxDq : plus1 = 1, minus1 = 0, PI = 25, DB = 0
N6.C1.D0.R1.S10: TxDq : plus1 = 1, minus1 = 0, PI = 01, DB = 1
N0.C1.D0.R1.S06: TxDqs: plus1 = 1, minus1 = 0, PI = 08, DB = 1
N2.C2.D1.R1.S01: TxDq : plus1 = 0, minus1 = 1, PI = 03, DB = 1
N4.C1.D1.R0.S15: TxDqs: plus1 = 1, minus1 = 0, PI = 09, DB = 1
N6.C1.D0.R1.S11: TxDqs: plus1 = 1, minus1 = 0, PI = 25, DB = 0
N0.C1.D0.R1.S06: TxDq : plus1 = 1, minus1 = 0, PI = 39, DB = 0
N2.C2.D1.R1.S02: TxDqs: plus1 = 1, minus1 = 0, PI = 23, DB = 0
N4.C1.D1.R0.S15: TxDq : plus1 = 1, minus1 = 0, PI = 39, DB = 0
N6.C1.D0.R1.S11: TxDq : plus1 = 1, minus1 = 0, PI = 57, DB = 1
N0.C1.D0.R1.S07: TxDqs: plus1 = 1, minus1 = 0, PI = 24, DB = 0
N2.C2.D1.R1.S02: TxDq : plus1 = 1, minus1 = 0, PI = 57, DB = 1
N4.C1.D1.R0.S16: TxDqs: plus1 = 1, minus1 = 0, PI = 29, DB = 0
N6.C1.D0.R1.S12: TxDqs: plus1 = 1, minus1 = 0, PI = 08, DB = 1
N0.C1.D0.R1.S07: TxDq : plus1 = 1, minus1 = 0, PI = 55, DB = 1
N2.C2.D1.R1.S03: TxDqs: plus1 = 1, minus1 = 0, PI = 11, DB = 1
N4.C1.D1.R0.S16: TxDq : plus1 = 1, minus1 = 0, PI = 56, DB = 1
N6.C1.D0.R1.S12: TxDq : plus1 = 1, minus1 = 0, PI = 41, DB = 0
N0.C1.D0.R1.S08: TxDqs: plus1 = 1, minus1 = 0, PI = 56, DB = 1
N2.C2.D1.R1.S03: TxDq : plus1 = 1, minus1 = 0, PI = 42, DB = 0
N4.C1.D1.R0.S17: TxDqs: plus1 = 1, minus1 = 0, PI = 58, DB = 1
N6.C1.D0.R1.S13: TxDqs: plus1 = 1, minus1 = 0, PI = 38, DB = 0
N0.C1.D0.R1.S08: TxDq : plus1 = 1, minus1 = 0, PI = 23, DB = 0
N2.C2.D1.R1.S04: TxDqs: plus1 = 1, minus1 = 0, PI = 32, DB = 0
N4.C1.D1.R0.S17: TxDq : plus1 = 1, minus1 = 0, PI = 23, DB = 0
N6.C1.D0.R1.S13: TxDq : plus1 = 1, minus1 = 0, PI = 08, DB = 1
N0.C1.D0.R1.S09: TxDqs: plus1 = 1, minus1 = 0, PI = 53, DB = 1
N2.C2.D1.R1.S04: TxDq : plus1 = 0, minus1 = 1, PI = 01, DB = 1
N4.C1.D1.R1.S00: TxDqs: plus1 = 1, minus1 = 0, PI = 59, DB = 1
N6.C1.D0.R1.S14: TxDqs: plus1 = 1, minus1 = 0, PI = 51, DB = 1
N0.C1.D0.R1.S09: TxDq : plus1 = 1, minus1 = 0, PI = 19, DB = 0
N2.C2.D1.R1.S05: TxDqs: plus1 = 1, minus1 = 0, PI = 62, DB = 1
N4.C1.D1.R1.S00: TxDq : plus1 = 1, minus1 = 0, PI = 25, DB = 0
N6.C1.D0.R1.S14: TxDq : plus1 = 1, minus1 = 0, PI = 19, DB = 0
N0.C1.D0.R1.S10: TxDqs: plus1 = 1, minus1 = 0, PI = 36, DB = 0
N2.C2.D1.R1.S05: TxDq : plus1 = 1, minus1 = 0, PI = 30, DB = 0
N4.C1.D1.R1.S01: TxDqs: plus1 = 1, minus1 = 0, PI = 43, DB = 0
N6.C1.D0.R1.S15: TxDqs: plus1 = 1, minus1 = 0, PI = 02, DB = 1
N0.C1.D0.R1.S10: TxDq : plus1 = 1, minus1 = 0, PI = 03, DB = 1
N2.C2.D1.R1.S06: TxDqs: plus1 = 1, minus1 = 0, PI = 58, DB = 1
N4.C1.D1.R1.S01: TxDq : plus1 = 1, minus1 = 0, PI = 08, DB = 1
N6.C1.D0.R1.S15: TxDq : plus1 = 1, minus1 = 0, PI = 37, DB = 0
N0.C1.D0.R1.S11: TxDqs: plus1 = 1, minus1 = 0, PI = 29, DB = 0
N2.C2.D1.R1.S06: TxDq : plus1 = 1, minus1 = 0, PI = 25, DB = 0
N4.C1.D1.R1.S02: TxDqs: plus1 = 1, minus1 = 0, PI = 33, DB = 0
N6.C1.D0.R1.S16: TxDqs: plus1 = 1, minus1 = 0, PI = 20, DB = 0
N0.C1.D0.R1.S11: TxDq : plus1 = 1, minus1 = 0, PI = 61, DB = 1
N2.C2.D1.R1.S07: TxDqs: plus1 = 1, minus1 = 0, PI = 18, DB = 0
N4.C1.D1.R1.S02: TxDq : plus1 = 1, minus1 = 0, PI = 62, DB = 1
N6.C1.D0.R1.S16: TxDq : plus1 = 1, minus1 = 0, PI = 52, DB = 1
N0.C1.D0.R1.S12: TxDqs: plus1 = 1, minus1 = 0, PI = 12, DB = 1
N2.C2.D1.R1.S07: TxDq : plus1 = 1, minus1 = 0, PI = 49, DB = 1
N4.C1.D1.R1.S03: TxDqs: plus1 = 1, minus1 = 0, PI = 18, DB = 0
N6.C1.D0.R1.S17: TxDqs: plus1 = 1, minus1 = 0, PI = 53, DB = 1
N0.C1.D0.R1.S12: TxDq : plus1 = 1, minus1 = 0, PI = 44, DB = 0
N2.C2.D1.R1.S08: TxDqs: plus1 = 1, minus1 = 0, PI = 48, DB = 0
N4.C1.D1.R1.S03: TxDq : plus1 = 1, minus1 = 0, PI = 45, DB = 0
N6.C1.D0.R1.S17: TxDq : plus1 = 1, minus1 = 0, PI = 21, DB = 0
N0.C1.D0.R1.S13: TxDqs: plus1 = 1, minus1 = 0, PI = 42, DB = 0
N2.C2.D1.R1.S08: TxDq : plus1 = 1, minus1 = 0, PI = 13, DB = 1
N4.C1.D1.R1.S04: TxDqs: plus1 = 1, minus1 = 0, PI = 48, DB = 0
N6.C1.D1.R0.S00: TxDqs: plus1 = 1, minus1 = 0, PI = 56, DB = 1
N0.C1.D0.R1.S13: TxDq : plus1 = 1, minus1 = 0, PI = 09, DB = 1
N2.C2.D1.R1.S09: TxDqs: plus1 = 1, minus1 = 0, PI = 48, DB = 0
N4.C1.D1.R1.S04: TxDq : plus1 = 1, minus1 = 0, PI = 11, DB = 1
N6.C1.D1.R0.S00: TxDq : plus1 = 1, minus1 = 0, PI = 24, DB = 0
N0.C1.D0.R1.S14: TxDqs: plus1 = 1, minus1 = 0, PI = 57, DB = 1
N2.C2.D1.R1.S09: TxDq : plus1 = 1, minus1 = 0, PI = 13, DB = 1
N4.C1.D1.R1.S05: TxDqs: plus1 = 1, minus1 = 0, PI = 61, DB = 1
N6.C1.D1.R0.S01: TxDqs: plus1 = 1, minus1 = 0, PI = 39, DB = 0
N0.C1.D0.R1.S14: TxDq : plus1 = 1, minus1 = 0, PI = 23, DB = 0
N2.C2.D1.R1.S10: TxDqs: plus1 = 1, minus1 = 0, PI = 36, DB = 0
N4.C1.D1.R1.S05: TxDq : plus1 = 1, minus1 = 0, PI = 26, DB = 0
N6.C1.D1.R0.S01: TxDq : plus1 = 1, minus1 = 0, PI = 06, DB = 1
N0.C1.D0.R1.S15: TxDqs: plus1 = 1, minus1 = 0, PI = 06, DB = 1
N2.C2.D1.R1.S10: TxDq : plus1 = 0, minus1 = 1, PI = 03, DB = 1
N4.C1.D1.R1.S06: TxDqs: plus1 = 1, minus1 = 0, PI = 10, DB = 1
N6.C1.D1.R0.S02: TxDqs: plus1 = 1, minus1 = 0, PI = 30, DB = 0
N0.C1.D0.R1.S15: TxDq : plus1 = 1, minus1 = 0, PI = 38, DB = 0
N2.C2.D1.R1.S11: TxDqs: plus1 = 1, minus1 = 0, PI = 24, DB = 0
N4.C1.D1.R1.S06: TxDq : plus1 = 1, minus1 = 0, PI = 39, DB = 0
N6.C1.D1.R0.S02: TxDq : plus1 = 1, minus1 = 0, PI = 61, DB = 1
N0.C1.D0.R1.S16: TxDqs: plus1 = 1, minus1 = 0, PI = 25, DB = 0
N2.C2.D1.R1.S11: TxDq : plus1 = 1, minus1 = 0, PI = 57, DB = 1
N4.C1.D1.R1.S07: TxDqs: plus1 = 1, minus1 = 0, PI = 27, DB = 0
N6.C1.D1.R0.S03: TxDqs: plus1 = 1, minus1 = 0, PI = 14, DB = 1
N0.C1.D0.R1.S16: TxDq : plus1 = 1, minus1 = 0, PI = 55, DB = 1
N2.C2.D1.R1.S12: TxDqs: plus1 = 1, minus1 = 0, PI = 10, DB = 1
N4.C1.D1.R1.S07: TxDq : plus1 = 1, minus1 = 0, PI = 55, DB = 1
N6.C1.D1.R0.S03: TxDq : plus1 = 1, minus1 = 0, PI = 45, DB = 0
N0.C1.D0.R1.S17: TxDqs: plus1 = 1, minus1 = 0, PI = 57, DB = 1
N2.C2.D1.R1.S12: TxDq : plus1 = 1, minus1 = 0, PI = 41, DB = 0
N4.C1.D1.R1.S08: TxDqs: plus1 = 1, minus1 = 0, PI = 60, DB = 1
N6.C1.D1.R0.S04: TxDqs: plus1 = 1, minus1 = 0, PI = 45, DB = 0
N0.C1.D0.R1.S17: TxDq : plus1 = 1, minus1 = 0, PI = 26, DB = 0
N2.C2.D1.R1.S13: TxDqs: plus1 = 1, minus1 = 0, PI = 33, DB = 0
N4.C1.D1.R1.S08: TxDq : plus1 = 1, minus1 = 0, PI = 25, DB = 0
N6.C1.D1.R0.S04: TxDq : plus1 = 1, minus1 = 0, PI = 12, DB = 1
N0.C1.D1.R0.S00: TxDqs: plus1 = 1, minus1 = 0, PI = 55, DB = 1
N2.C2.D1.R1.S13: TxDq : plus1 = 0, minus1 = 1, PI = 01, DB = 1
N4.C1.D1.R1.S09: TxDqs: plus1 = 1, minus1 = 0, PI = 57, DB = 1
N6.C1.D1.R0.S05: TxDqs: plus1 = 1, minus1 = 0, PI = 60, DB = 1
N0.C1.D1.R0.S00: TxDq : plus1 = 1, minus1 = 0, PI = 22, DB = 0
N2.C2.D1.R1.S14: TxDqs: plus1 = 1, minus1 = 0, PI = 61, DB = 1
N4.C1.D1.R1.S09: TxDq : plus1 = 1, minus1 = 0, PI = 21, DB = 0
N6.C1.D1.R0.S05: TxDq : plus1 = 1, minus1 = 0, PI = 27, DB = 0
N0.C1.D1.R0.S01: TxDqs: plus1 = 1, minus1 = 0, PI = 38, DB = 0
N2.C2.D1.R1.S14: TxDq : plus1 = 1, minus1 = 0, PI = 29, DB = 0
N4.C1.D1.R1.S10: TxDqs: plus1 = 1, minus1 = 0, PI = 42, DB = 0
N6.C1.D1.R0.S06: TxDqs: plus1 = 1, minus1 = 0, PI = 07, DB = 1
N0.C1.D1.R0.S01: TxDq : plus1 = 1, minus1 = 0, PI = 04, DB = 1
N2.C2.D1.R1.S15: TxDqs: plus1 = 1, minus1 = 0, PI = 58, DB = 1
N4.C1.D1.R1.S10: TxDq : plus1 = 1, minus1 = 0, PI = 07, DB = 1
N6.C1.D1.R0.S06: TxDq : plus1 = 1, minus1 = 0, PI = 40, DB = 0
N0.C1.D1.R0.S02: TxDqs: plus1 = 1, minus1 = 0, PI = 30, DB = 0
N2.C2.D1.R1.S15: TxDq : plus1 = 1, minus1 = 0, PI = 26, DB = 0
N4.C1.D1.R1.S11: TxDqs: plus1 = 1, minus1 = 0, PI = 32, DB = 0
N6.C1.D1.R0.S07: TxDqs: plus1 = 1, minus1 = 0, PI = 27, DB = 0
N0.C1.D1.R0.S02: TxDq : plus1 = 1, minus1 = 0, PI = 60, DB = 1
N2.C2.D1.R1.S16: TxDqs: plus1 = 1, minus1 = 0, PI = 17, DB = 0
N4.C1.D1.R1.S11: TxDq : plus1 = 1, minus1 = 0, PI = 61, DB = 1
N6.C1.D1.R0.S07: TxDq : plus1 = 1, minus1 = 0, PI = 58, DB = 1
N0.C1.D1.R0.S03: TxDqs: plus1 = 1, minus1 = 0, PI = 17, DB = 0
N2.C2.D1.R1.S16: TxDq : plus1 = 1, minus1 = 0, PI = 48, DB = 0
N4.C1.D1.R1.S12: TxDqs: plus1 = 1, minus1 = 0, PI = 18, DB = 0
N6.C1.D1.R0.S08: TxDqs: plus1 = 1, minus1 = 0, PI = 59, DB = 1
N0.C1.D1.R0.S03: TxDq : plus1 = 1, minus1 = 0, PI = 47, DB = 0
N2.C2.D1.R1.S17: TxDqs: plus1 = 1, minus1 = 0, PI = 47, DB = 0
N4.C1.D1.R1.S12: TxDq : plus1 = 1, minus1 = 0, PI = 49, DB = 1
N6.C1.D1.R0.S08: TxDq : plus1 = 1, minus1 = 0, PI = 26, DB = 0
N0.C1.D1.R0.S04: TxDqs: plus1 = 1, minus1 = 0, PI = 47, DB = 0
N2.C2.D1.R1.S17: TxDq : plus1 = 1, minus1 = 0, PI = 13, DB = 1
N4.C1.D1.R1.S13: TxDqs: plus1 = 1, minus1 = 0, PI = 47, DB = 0
N6.C1.D1.R0.S09: TxDqs: plus1 = 1, minus1 = 0, PI = 54, DB = 1
N0.C1.D1.R0.S04: TxDq : plus1 = 1, minus1 = 0, PI = 13, DB = 1
END_DATA_TX_DQ
N4.C1.D1.R1.S13: TxDq : plus1 = 1, minus1 = 0, PI = 11, DB = 1
N6.C1.D1.R0.S09: TxDq : plus1 = 1, minus1 = 0, PI = 21, DB = 0
N0.C1.D1.R0.S05: TxDqs: plus1 = 1, minus1 = 0, PI = 59, DB = 1
N2.C3.D0.R0.S00: wrcmd2dqsstartlatency: 04
N4.C1.D1.R1.S14: TxDqs: plus1 = 1, minus1 = 0, PI = 61, DB = 1
N6.C1.D1.R0.S10: TxDqs: plus1 = 1, minus1 = 0, PI = 40, DB = 0
N0.C1.D1.R0.S05: TxDq : plus1 = 1, minus1 = 0, PI = 25, DB = 0
N2.C3.D0.R0.S00: RdPtrOffsetTxDq: 06
N4.C1.D1.R1.S14: TxDq : plus1 = 1, minus1 = 0, PI = 25, DB = 0
N6.C1.D1.R0.S10: TxDq : plus1 = 1, minus1 = 0, PI = 07, DB = 1
N0.C1.D1.R0.S06: TxDqs: plus1 = 1, minus1 = 0, PI = 11, DB = 1
N2.C3.D0.R0.S00: RdPtrOffsetTxDqs: 07
N4.C1.D1.R1.S15: TxDqs: plus1 = 1, minus1 = 0, PI = 09, DB = 1
N6.C1.D1.R0.S11: TxDqs: plus1 = 1, minus1 = 0, PI = 31, DB = 0
N0.C1.D1.R0.S06: TxDq : plus1 = 1, minus1 = 0, PI = 40, DB = 0
N2.C3.D0.R0.S00: PiTxDqs: 55
N4.C1.D1.R1.S15: TxDq : plus1 = 1, minus1 = 0, PI = 39, DB = 0
N6.C1.D1.R0.S11: TxDq : plus1 = 1, minus1 = 0, PI = 62, DB = 1
N0.C1.D1.R0.S07: TxDqs: plus1 = 1, minus1 = 0, PI = 28, DB = 0
N2.C3.D0.R0.S01: wrcmd2dqsstartlatency: 04
N4.C1.D1.R1.S16: TxDqs: plus1 = 1, minus1 = 0, PI = 29, DB = 0
N6.C1.D1.R0.S12: TxDqs: plus1 = 1, minus1 = 0, PI = 16, DB = 0
N0.C1.D1.R0.S07: TxDq : plus1 = 1, minus1 = 0, PI = 58, DB = 1
N2.C3.D0.R0.S01: RdPtrOffsetTxDq: 06
N4.C1.D1.R1.S16: TxDq : plus1 = 1, minus1 = 0, PI = 56, DB = 1
N6.C1.D1.R0.S12: TxDq : plus1 = 1, minus1 = 0, PI = 48, DB = 0
N0.C1.D1.R0.S08: TxDqs: plus1 = 1, minus1 = 0, PI = 59, DB = 1
N2.C3.D0.R0.S01: RdPtrOffsetTxDqs: 07
N4.C1.D1.R1.S17: TxDqs: plus1 = 1, minus1 = 0, PI = 58, DB = 1
N6.C1.D1.R0.S13: TxDqs: plus1 = 1, minus1 = 0, PI = 46, DB = 0
N0.C1.D1.R0.S08: TxDq : plus1 = 1, minus1 = 0, PI = 25, DB = 0
N2.C3.D0.R0.S01: PiTxDqs: 39
N4.C1.D1.R1.S17: TxDq : plus1 = 1, minus1 = 0, PI = 23, DB = 0
N6.C1.D1.R0.S13: TxDq : plus1 = 1, minus1 = 0, PI = 15, DB = 1
N0.C1.D1.R0.S09: TxDqs: plus1 = 1, minus1 = 0, PI = 55, DB = 1
N2.C3.D0.R0.S02: wrcmd2dqsstartlatency: 04
END_DATA_TX_DQ
N6.C1.D1.R0.S14: TxDqs: plus1 = 1, minus1 = 0, PI = 60, DB = 1
N0.C1.D1.R0.S09: TxDq : plus1 = 1, minus1 = 0, PI = 20, DB = 0
N2.C3.D0.R0.S02: RdPtrOffsetTxDq: 05
N4.C2.D0.R0.S00: wrcmd2dqsstartlatency: 04
N6.C1.D1.R0.S14: TxDq : plus1 = 1, minus1 = 0, PI = 28, DB = 0
N0.C1.D1.R0.S10: TxDqs: plus1 = 1, minus1 = 0, PI = 40, DB = 0
N2.C3.D0.R0.S02: RdPtrOffsetTxDqs: 07
N4.C2.D0.R0.S00: RdPtrOffsetTxDq: 06
N6.C1.D1.R0.S15: TxDqs: plus1 = 1, minus1 = 0, PI = 06, DB = 1
N0.C1.D1.R0.S10: TxDq : plus1 = 1, minus1 = 0, PI = 05, DB = 1
N2.C3.D0.R0.S02: PiTxDqs: 31
N4.C2.D0.R0.S00: RdPtrOffsetTxDqs: 07
N6.C1.D1.R0.S15: TxDq : plus1 = 1, minus1 = 0, PI = 39, DB = 0
N0.C1.D1.R0.S11: TxDqs: plus1 = 1, minus1 = 0, PI = 33, DB = 0
N2.C3.D0.R0.S03: wrcmd2dqsstartlatency: 04
N4.C2.D0.R0.S00: PiTxDqs: 51
N6.C1.D1.R0.S16: TxDqs: plus1 = 1, minus1 = 0, PI = 29, DB = 0
N0.C1.D1.R0.S11: TxDq : plus1 = 1, minus1 = 0, PI = 63, DB = 1
N2.C3.D0.R0.S03: RdPtrOffsetTxDq: 05
N4.C2.D0.R0.S01: wrcmd2dqsstartlatency: 04
N6.C1.D1.R0.S16: TxDq : plus1 = 1, minus1 = 0, PI = 60, DB = 1
N0.C1.D1.R0.S12: TxDqs: plus1 = 1, minus1 = 0, PI = 17, DB = 0
N2.C3.D0.R0.S03: RdPtrOffsetTxDqs: 07
N4.C2.D0.R0.S01: RdPtrOffsetTxDq: 06
N6.C1.D1.R0.S17: TxDqs: plus1 = 1, minus1 = 0, PI = 59, DB = 1
N0.C1.D1.R0.S12: TxDq : plus1 = 1, minus1 = 0, PI = 48, DB = 0
N2.C3.D0.R0.S03: PiTxDqs: 12
N4.C2.D0.R0.S01: RdPtrOffsetTxDqs: 07
N6.C1.D1.R0.S17: TxDq : plus1 = 1, minus1 = 0, PI = 25, DB = 0
N0.C1.D1.R0.S13: TxDqs: plus1 = 1, minus1 = 0, PI = 46, DB = 0
N2.C3.D0.R0.S04: wrcmd2dqsstartlatency: 04
N4.C2.D0.R0.S01: PiTxDqs: 37
N6.C1.D1.R1.S00: TxDqs: plus1 = 1, minus1 = 0, PI = 56, DB = 1
N0.C1.D1.R0.S13: TxDq : plus1 = 1, minus1 = 0, PI = 13, DB = 1
N2.C3.D0.R0.S04: RdPtrOffsetTxDq: 05
N4.C2.D0.R0.S02: wrcmd2dqsstartlatency: 04
N6.C1.D1.R1.S00: TxDq : plus1 = 1, minus1 = 0, PI = 24, DB = 0
N0.C1.D1.R0.S14: TxDqs: plus1 = 1, minus1 = 0, PI = 60, DB = 1
N2.C3.D0.R0.S04: RdPtrOffsetTxDqs: 06
N4.C2.D0.R0.S02: RdPtrOffsetTxDq: 05
N6.C1.D1.R1.S01: TxDqs: plus1 = 1, minus1 = 0, PI = 39, DB = 0
N0.C1.D1.R0.S14: TxDq : plus1 = 1, minus1 = 0, PI = 27, DB = 0
N2.C3.D0.R0.S04: PiTxDqs: 43
N4.C2.D0.R0.S02: RdPtrOffsetTxDqs: 07
N6.C1.D1.R1.S01: TxDq : plus1 = 1, minus1 = 0, PI = 06, DB = 1
N0.C1.D1.R0.S15: TxDqs: plus1 = 1, minus1 = 0, PI = 09, DB = 1
N2.C3.D0.R0.S05: wrcmd2dqsstartlatency: 04
N4.C2.D0.R0.S02: PiTxDqs: 27
N6.C1.D1.R1.S02: TxDqs: plus1 = 1, minus1 = 0, PI = 30, DB = 0
N0.C1.D1.R0.S15: TxDq : plus1 = 1, minus1 = 0, PI = 41, DB = 0
N2.C3.D0.R0.S05: RdPtrOffsetTxDq: 05
N4.C2.D0.R0.S03: wrcmd2dqsstartlatency: 04
N6.C1.D1.R1.S02: TxDq : plus1 = 1, minus1 = 0, PI = 61, DB = 1
N0.C1.D1.R0.S16: TxDqs: plus1 = 1, minus1 = 0, PI = 27, DB = 0
N2.C3.D0.R0.S05: RdPtrOffsetTxDqs: 06
N4.C2.D0.R0.S03: RdPtrOffsetTxDq: 05
N6.C1.D1.R1.S03: TxDqs: plus1 = 1, minus1 = 0, PI = 14, DB = 1
N0.C1.D1.R0.S16: TxDq : plus1 = 1, minus1 = 0, PI = 58, DB = 1
N2.C3.D0.R0.S05: PiTxDqs: 55
N4.C2.D0.R0.S03: RdPtrOffsetTxDqs: 07
N6.C1.D1.R1.S03: TxDq : plus1 = 1, minus1 = 0, PI = 45, DB = 0
N0.C1.D1.R0.S17: TxDqs: plus1 = 1, minus1 = 0, PI = 59, DB = 1
N2.C3.D0.R0.S06: wrcmd2dqsstartlatency: 04
N4.C2.D0.R0.S03: PiTxDqs: 09
N6.C1.D1.R1.S04: TxDqs: plus1 = 1, minus1 = 0, PI = 45, DB = 0
N0.C1.D1.R0.S17: TxDq : plus1 = 1, minus1 = 0, PI = 25, DB = 0
N2.C3.D0.R0.S06: RdPtrOffsetTxDq: 05
N4.C2.D0.R0.S04: wrcmd2dqsstartlatency: 04
N6.C1.D1.R1.S04: TxDq : plus1 = 1, minus1 = 0, PI = 12, DB = 1
N0.C1.D1.R1.S00: TxDqs: plus1 = 1, minus1 = 0, PI = 55, DB = 1
N2.C3.D0.R0.S06: RdPtrOffsetTxDqs: 07
N4.C2.D0.R0.S04: RdPtrOffsetTxDq: 04
N6.C1.D1.R1.S05: TxDqs: plus1 = 1, minus1 = 0, PI = 60, DB = 1
N0.C1.D1.R1.S00: TxDq : plus1 = 1, minus1 = 0, PI = 22, DB = 0
N2.C3.D0.R0.S06: PiTxDqs: 07
N4.C2.D0.R0.S04: RdPtrOffsetTxDqs: 06
N6.C1.D1.R1.S05: TxDq : plus1 = 1, minus1 = 0, PI = 27, DB = 0
N0.C1.D1.R1.S01: TxDqs: plus1 = 1, minus1 = 0, PI = 38, DB = 0
N2.C3.D0.R0.S07: wrcmd2dqsstartlatency: 04
N4.C2.D0.R0.S04: PiTxDqs: 30
N6.C1.D1.R1.S06: TxDqs: plus1 = 1, minus1 = 0, PI = 07, DB = 1
N0.C1.D1.R1.S01: TxDq : plus1 = 1, minus1 = 0, PI = 04, DB = 1
N2.C3.D0.R0.S07: RdPtrOffsetTxDq: 05
N4.C2.D0.R0.S05: wrcmd2dqsstartlatency: 04
N6.C1.D1.R1.S06: TxDq : plus1 = 1, minus1 = 0, PI = 40, DB = 0
N0.C1.D1.R1.S02: TxDqs: plus1 = 1, minus1 = 0, PI = 30, DB = 0
N2.C3.D0.R0.S07: RdPtrOffsetTxDqs: 07
N4.C2.D0.R0.S05: RdPtrOffsetTxDq: 05
N6.C1.D1.R1.S07: TxDqs: plus1 = 1, minus1 = 0, PI = 27, DB = 0
N0.C1.D1.R1.S02: TxDq : plus1 = 1, minus1 = 0, PI = 60, DB = 1
N2.C3.D0.R0.S07: PiTxDqs: 23
N4.C2.D0.R0.S05: RdPtrOffsetTxDqs: 06
N6.C1.D1.R1.S07: TxDq : plus1 = 1, minus1 = 0, PI = 58, DB = 1
N0.C1.D1.R1.S03: TxDqs: plus1 = 1, minus1 = 0, PI = 17, DB = 0
N2.C3.D0.R0.S08: wrcmd2dqsstartlatency: 04
N4.C2.D0.R0.S05: PiTxDqs: 60
N6.C1.D1.R1.S08: TxDqs: plus1 = 1, minus1 = 0, PI = 59, DB = 1
N0.C1.D1.R1.S03: TxDq : plus1 = 1, minus1 = 0, PI = 47, DB = 0
N2.C3.D0.R0.S08: RdPtrOffsetTxDq: 05
N4.C2.D0.R0.S06: wrcmd2dqsstartlatency: 04
N6.C1.D1.R1.S08: TxDq : plus1 = 1, minus1 = 0, PI = 26, DB = 0
N0.C1.D1.R1.S04: TxDqs: plus1 = 1, minus1 = 0, PI = 47, DB = 0
N2.C3.D0.R0.S08: RdPtrOffsetTxDqs: 06
N4.C2.D0.R0.S06: RdPtrOffsetTxDq: 05
N6.C1.D1.R1.S09: TxDqs: plus1 = 1, minus1 = 0, PI = 54, DB = 1
N0.C1.D1.R1.S04: TxDq : plus1 = 1, minus1 = 0, PI = 13, DB = 1
N2.C3.D0.R0.S08: PiTxDqs: 61
N4.C2.D0.R0.S06: RdPtrOffsetTxDqs: 06
N6.C1.D1.R1.S09: TxDq : plus1 = 1, minus1 = 0, PI = 21, DB = 0
N0.C1.D1.R1.S05: TxDqs: plus1 = 1, minus1 = 0, PI = 59, DB = 1
N2.C3.D0.R0.S09: wrcmd2dqsstartlatency: 04
N4.C2.D0.R0.S06: PiTxDqs: 62
N6.C1.D1.R1.S10: TxDqs: plus1 = 1, minus1 = 0, PI = 40, DB = 0
N0.C1.D1.R1.S05: TxDq : plus1 = 1, minus1 = 0, PI = 25, DB = 0
N2.C3.D0.R0.S09: RdPtrOffsetTxDq: 06
N4.C2.D0.R0.S07: wrcmd2dqsstartlatency: 04
N6.C1.D1.R1.S10: TxDq : plus1 = 1, minus1 = 0, PI = 07, DB = 1
N0.C1.D1.R1.S06: TxDqs: plus1 = 1, minus1 = 0, PI = 11, DB = 1
N2.C3.D0.R0.S09: RdPtrOffsetTxDqs: 07
N4.C2.D0.R0.S07: RdPtrOffsetTxDq: 05
N6.C1.D1.R1.S11: TxDqs: plus1 = 1, minus1 = 0, PI = 31, DB = 0
N0.C1.D1.R1.S06: TxDq : plus1 = 1, minus1 = 0, PI = 40, DB = 0
N2.C3.D0.R0.S09: PiTxDqs: 56
N4.C2.D0.R0.S07: RdPtrOffsetTxDqs: 07
N6.C1.D1.R1.S11: TxDq : plus1 = 1, minus1 = 0, PI = 62, DB = 1
N0.C1.D1.R1.S07: TxDqs: plus1 = 1, minus1 = 0, PI = 28, DB = 0
N2.C3.D0.R0.S10: wrcmd2dqsstartlatency: 04
N4.C2.D0.R0.S07: PiTxDqs: 16
N6.C1.D1.R1.S12: TxDqs: plus1 = 1, minus1 = 0, PI = 16, DB = 0
N0.C1.D1.R1.S07: TxDq : plus1 = 1, minus1 = 0, PI = 58, DB = 1
N2.C3.D0.R0.S10: RdPtrOffsetTxDq: 06
N4.C2.D0.R0.S08: wrcmd2dqsstartlatency: 04
N6.C1.D1.R1.S12: TxDq : plus1 = 1, minus1 = 0, PI = 48, DB = 0
N0.C1.D1.R1.S08: TxDqs: plus1 = 1, minus1 = 0, PI = 59, DB = 1
N2.C3.D0.R0.S10: RdPtrOffsetTxDqs: 07
N4.C2.D0.R0.S08: RdPtrOffsetTxDq: 05
N6.C1.D1.R1.S13: TxDqs: plus1 = 1, minus1 = 0, PI = 46, DB = 0
N0.C1.D1.R1.S08: TxDq : plus1 = 1, minus1 = 0, PI = 25, DB = 0
N2.C3.D0.R0.S10: PiTxDqs: 40
N4.C2.D0.R0.S08: RdPtrOffsetTxDqs: 06
N6.C1.D1.R1.S13: TxDq : plus1 = 1, minus1 = 0, PI = 15, DB = 1
N0.C1.D1.R1.S09: TxDqs: plus1 = 1, minus1 = 0, PI = 55, DB = 1
N2.C3.D0.R0.S11: wrcmd2dqsstartlatency: 04
N4.C2.D0.R0.S08: PiTxDqs: 53
N6.C1.D1.R1.S14: TxDqs: plus1 = 1, minus1 = 0, PI = 60, DB = 1
N0.C1.D1.R1.S09: TxDq : plus1 = 1, minus1 = 0, PI = 20, DB = 0
N2.C3.D0.R0.S11: RdPtrOffsetTxDq: 05
N4.C2.D0.R0.S09: wrcmd2dqsstartlatency: 04
N6.C1.D1.R1.S14: TxDq : plus1 = 1, minus1 = 0, PI = 28, DB = 0
N0.C1.D1.R1.S10: TxDqs: plus1 = 1, minus1 = 0, PI = 40, DB = 0
N2.C3.D0.R0.S11: RdPtrOffsetTxDqs: 07
N4.C2.D0.R0.S09: RdPtrOffsetTxDq: 06
N6.C1.D1.R1.S15: TxDqs: plus1 = 1, minus1 = 0, PI = 06, DB = 1
N0.C1.D1.R1.S10: TxDq : plus1 = 1, minus1 = 0, PI = 05, DB = 1
N2.C3.D0.R0.S11: PiTxDqs: 31
N4.C2.D0.R0.S09: RdPtrOffsetTxDqs: 07
N6.C1.D1.R1.S15: TxDq : plus1 = 1, minus1 = 0, PI = 39, DB = 0
N0.C1.D1.R1.S11: TxDqs: plus1 = 1, minus1 = 0, PI = 33, DB = 0
N2.C3.D0.R0.S12: wrcmd2dqsstartlatency: 04
N4.C2.D0.R0.S09: PiTxDqs: 54
N6.C1.D1.R1.S16: TxDqs: plus1 = 1, minus1 = 0, PI = 29, DB = 0
N0.C1.D1.R1.S11: TxDq : plus1 = 1, minus1 = 0, PI = 63, DB = 1
N2.C3.D0.R0.S12: RdPtrOffsetTxDq: 05
N4.C2.D0.R0.S10: wrcmd2dqsstartlatency: 04
N6.C1.D1.R1.S16: TxDq : plus1 = 1, minus1 = 0, PI = 60, DB = 1
N0.C1.D1.R1.S12: TxDqs: plus1 = 1, minus1 = 0, PI = 17, DB = 0
N2.C3.D0.R0.S12: RdPtrOffsetTxDqs: 07
N4.C2.D0.R0.S10: RdPtrOffsetTxDq: 06
N6.C1.D1.R1.S17: TxDqs: plus1 = 1, minus1 = 0, PI = 59, DB = 1
N0.C1.D1.R1.S12: TxDq : plus1 = 1, minus1 = 0, PI = 48, DB = 0
N2.C3.D0.R0.S12: PiTxDqs: 14
N4.C2.D0.R0.S10: RdPtrOffsetTxDqs: 07
N6.C1.D1.R1.S17: TxDq : plus1 = 1, minus1 = 0, PI = 25, DB = 0
N0.C1.D1.R1.S13: TxDqs: plus1 = 1, minus1 = 0, PI = 46, DB = 0
N2.C3.D0.R0.S13: wrcmd2dqsstartlatency: 04
N4.C2.D0.R0.S10: PiTxDqs: 40
END_DATA_TX_DQ
N0.C1.D1.R1.S13: TxDq : plus1 = 1, minus1 = 0, PI = 13, DB = 1
N2.C3.D0.R0.S13: RdPtrOffsetTxDq: 05
N4.C2.D0.R0.S11: wrcmd2dqsstartlatency: 04
N6.C2.D0.R0.S00: wrcmd2dqsstartlatency: 04
N0.C1.D1.R1.S14: TxDqs: plus1 = 1, minus1 = 0, PI = 60, DB = 1
N2.C3.D0.R0.S13: RdPtrOffsetTxDqs: 06
N4.C2.D0.R0.S11: RdPtrOffsetTxDq: 05
N6.C2.D0.R0.S00: RdPtrOffsetTxDq: 06
N0.C1.D1.R1.S14: TxDq : plus1 = 1, minus1 = 0, PI = 27, DB = 0
N2.C3.D0.R0.S13: PiTxDqs: 42
N4.C2.D0.R0.S11: RdPtrOffsetTxDqs: 07
N6.C2.D0.R0.S00: RdPtrOffsetTxDqs: 07
N0.C1.D1.R1.S15: TxDqs: plus1 = 1, minus1 = 0, PI = 09, DB = 1
N2.C3.D0.R0.S14: wrcmd2dqsstartlatency: 04
N4.C2.D0.R0.S11: PiTxDqs: 28
N6.C2.D0.R0.S00: PiTxDqs: 47
N0.C1.D1.R1.S15: TxDq : plus1 = 1, minus1 = 0, PI = 41, DB = 0
N2.C3.D0.R0.S14: RdPtrOffsetTxDq: 05
N4.C2.D0.R0.S12: wrcmd2dqsstartlatency: 04
N6.C2.D0.R0.S01: wrcmd2dqsstartlatency: 04
N0.C1.D1.R1.S16: TxDqs: plus1 = 1, minus1 = 0, PI = 27, DB = 0
N2.C3.D0.R0.S14: RdPtrOffsetTxDqs: 06
N4.C2.D0.R0.S12: RdPtrOffsetTxDq: 05
N6.C2.D0.R0.S01: RdPtrOffsetTxDq: 05
N0.C1.D1.R1.S16: TxDq : plus1 = 1, minus1 = 0, PI = 58, DB = 1
N2.C3.D0.R0.S14: PiTxDqs: 56
N4.C2.D0.R0.S12: RdPtrOffsetTxDqs: 07
N6.C2.D0.R0.S01: RdPtrOffsetTxDqs: 07
N0.C1.D1.R1.S17: TxDqs: plus1 = 1, minus1 = 0, PI = 59, DB = 1
N2.C3.D0.R0.S15: wrcmd2dqsstartlatency: 04
N4.C2.D0.R0.S12: PiTxDqs: 10
N6.C2.D0.R0.S01: PiTxDqs: 33
N0.C1.D1.R1.S17: TxDq : plus1 = 1, minus1 = 0, PI = 25, DB = 0
N2.C3.D0.R0.S15: RdPtrOffsetTxDq: 05
N4.C2.D0.R0.S13: wrcmd2dqsstartlatency: 04
N6.C2.D0.R0.S02: wrcmd2dqsstartlatency: 04
END_DATA_TX_DQ
N2.C3.D0.R0.S15: RdPtrOffsetTxDqs: 07
N4.C2.D0.R0.S13: RdPtrOffsetTxDq: 05
N6.C2.D0.R0.S02: RdPtrOffsetTxDq: 05
N0.C2.D0.R0.S00: wrcmd2dqsstartlatency: 04
N2.C3.D0.R0.S15: PiTxDqs: 06
N4.C2.D0.R0.S13: RdPtrOffsetTxDqs: 06
N6.C2.D0.R0.S02: RdPtrOffsetTxDqs: 07
N0.C2.D0.R0.S00: RdPtrOffsetTxDq: 06
N2.C3.D0.R0.S16: wrcmd2dqsstartlatency: 04
N4.C2.D0.R0.S13: PiTxDqs: 33
N6.C2.D0.R0.S02: PiTxDqs: 25
N0.C2.D0.R0.S00: RdPtrOffsetTxDqs: 07
N2.C3.D0.R0.S16: RdPtrOffsetTxDq: 05
N4.C2.D0.R0.S14: wrcmd2dqsstartlatency: 04
N6.C2.D0.R0.S03: wrcmd2dqsstartlatency: 04
N0.C2.D0.R0.S00: PiTxDqs: 53
N2.C3.D0.R0.S16: RdPtrOffsetTxDqs: 07
N4.C2.D0.R0.S14: RdPtrOffsetTxDq: 05
N6.C2.D0.R0.S03: RdPtrOffsetTxDq: 05
N0.C2.D0.R0.S01: wrcmd2dqsstartlatency: 04
N2.C3.D0.R0.S16: PiTxDqs: 20
N4.C2.D0.R0.S14: RdPtrOffsetTxDqs: 06
N6.C2.D0.R0.S03: RdPtrOffsetTxDqs: 07
N0.C2.D0.R0.S01: RdPtrOffsetTxDq: 06
N2.C3.D0.R0.S17: wrcmd2dqsstartlatency: 04
N4.C2.D0.R0.S14: PiTxDqs: 62
N6.C2.D0.R0.S03: PiTxDqs: 03
N0.C2.D0.R0.S01: RdPtrOffsetTxDqs: 07
N2.C3.D0.R0.S17: RdPtrOffsetTxDq: 05
N4.C2.D0.R0.S15: wrcmd2dqsstartlatency: 04
N6.C2.D0.R0.S04: wrcmd2dqsstartlatency: 04
N0.C2.D0.R0.S01: PiTxDqs: 38
N2.C3.D0.R0.S17: RdPtrOffsetTxDqs: 06
N4.C2.D0.R0.S15: RdPtrOffsetTxDq: 05
N6.C2.D0.R0.S04: RdPtrOffsetTxDq: 04
N0.C2.D0.R0.S02: wrcmd2dqsstartlatency: 04
N2.C3.D0.R0.S17: PiTxDqs: 61
N4.C2.D0.R0.S15: RdPtrOffsetTxDqs: 06
N6.C2.D0.R0.S04: RdPtrOffsetTxDqs: 06
N0.C2.D0.R0.S02: RdPtrOffsetTxDq: 05
N2.C3.D0.R0.S00: RdPtrOffsetTxDq: 07
N4.C2.D0.R0.S15: PiTxDqs: 62
N6.C2.D0.R0.S04: PiTxDqs: 29
N0.C2.D0.R0.S02: RdPtrOffsetTxDqs: 07
N2.C3.D0.R0.S01: RdPtrOffsetTxDq: 07
N4.C2.D0.R0.S16: wrcmd2dqsstartlatency: 04
N6.C2.D0.R0.S05: wrcmd2dqsstartlatency: 04
N0.C2.D0.R0.S02: PiTxDqs: 27
N2.C3.D0.R0.S02: RdPtrOffsetTxDq: 06
N4.C2.D0.R0.S16: RdPtrOffsetTxDq: 05
N6.C2.D0.R0.S05: RdPtrOffsetTxDq: 05
N0.C2.D0.R0.S03: wrcmd2dqsstartlatency: 04
N2.C3.D0.R0.S03: RdPtrOffsetTxDq: 06
N4.C2.D0.R0.S16: RdPtrOffsetTxDqs: 07
N6.C2.D0.R0.S05: RdPtrOffsetTxDqs: 06
N0.C2.D0.R0.S03: RdPtrOffsetTxDq: 05
N2.C3.D0.R0.S04: RdPtrOffsetTxDq: 06
N4.C2.D0.R0.S16: PiTxDqs: 17
N6.C2.D0.R0.S05: PiTxDqs: 57
N0.C2.D0.R0.S03: RdPtrOffsetTxDqs: 07
N2.C3.D0.R0.S05: RdPtrOffsetTxDq: 06
N4.C2.D0.R0.S17: wrcmd2dqsstartlatency: 04
N6.C2.D0.R0.S06: wrcmd2dqsstartlatency: 04
N0.C2.D0.R0.S03: PiTxDqs: 11
N2.C3.D0.R0.S06: RdPtrOffsetTxDq: 06
N4.C2.D0.R0.S17: RdPtrOffsetTxDq: 05
N6.C2.D0.R0.S06: RdPtrOffsetTxDq: 05
N0.C2.D0.R0.S04: wrcmd2dqsstartlatency: 04
N2.C3.D0.R0.S07: RdPtrOffsetTxDq: 06
N4.C2.D0.R0.S17: RdPtrOffsetTxDqs: 06
N6.C2.D0.R0.S06: RdPtrOffsetTxDqs: 06
N0.C2.D0.R0.S04: RdPtrOffsetTxDq: 05
N2.C3.D0.R0.S08: RdPtrOffsetTxDq: 06
N4.C2.D0.R0.S17: PiTxDqs: 50
N6.C2.D0.R0.S06: PiTxDqs: 57
N0.C2.D0.R0.S04: RdPtrOffsetTxDqs: 06
N2.C3.D0.R0.S09: RdPtrOffsetTxDq: 07
N4.C2.D0.R0.S00: RdPtrOffsetTxDq: 07
N6.C2.D0.R0.S07: wrcmd2dqsstartlatency: 04
N0.C2.D0.R0.S04: PiTxDqs: 36
N2.C3.D0.R0.S10: RdPtrOffsetTxDq: 07
N4.C2.D0.R0.S01: RdPtrOffsetTxDq: 07
N6.C2.D0.R0.S07: RdPtrOffsetTxDq: 05
N0.C2.D0.R0.S05: wrcmd2dqsstartlatency: 04
N2.C3.D0.R0.S11: RdPtrOffsetTxDq: 06
N4.C2.D0.R0.S02: RdPtrOffsetTxDq: 06
N6.C2.D0.R0.S07: RdPtrOffsetTxDqs: 07
N0.C2.D0.R0.S05: RdPtrOffsetTxDq: 05
N2.C3.D0.R0.S12: RdPtrOffsetTxDq: 06
N4.C2.D0.R0.S03: RdPtrOffsetTxDq: 06
N6.C2.D0.R0.S07: PiTxDqs: 15
N0.C2.D0.R0.S05: RdPtrOffsetTxDqs: 07
N2.C3.D0.R0.S13: RdPtrOffsetTxDq: 06
N4.C2.D0.R0.S04: RdPtrOffsetTxDq: 05
N6.C2.D0.R0.S08: wrcmd2dqsstartlatency: 04
N0.C2.D0.R0.S05: PiTxDqs: 00
N2.C3.D0.R0.S14: RdPtrOffsetTxDq: 06
N4.C2.D0.R0.S05: RdPtrOffsetTxDq: 06
N6.C2.D0.R0.S08: RdPtrOffsetTxDq: 05
N0.C2.D0.R0.S06: wrcmd2dqsstartlatency: 04
N2.C3.D0.R0.S15: RdPtrOffsetTxDq: 06
N4.C2.D0.R0.S06: RdPtrOffsetTxDq: 06
N6.C2.D0.R0.S08: RdPtrOffsetTxDqs: 06
N0.C2.D0.R0.S06: RdPtrOffsetTxDq: 05
N2.C3.D0.R0.S16: RdPtrOffsetTxDq: 06
N4.C2.D0.R0.S07: RdPtrOffsetTxDq: 06
N6.C2.D0.R0.S08: PiTxDqs: 48
N0.C2.D0.R0.S06: RdPtrOffsetTxDqs: 06
N2.C3.D0.R0.S17: RdPtrOffsetTxDq: 06
N4.C2.D0.R0.S08: RdPtrOffsetTxDq: 06
N6.C2.D0.R0.S09: wrcmd2dqsstartlatency: 04
N0.C2.D0.R0.S06: PiTxDqs: 63
N2.C3.D0.R0.S00: RdPtrOffsetTxDq: 08
N4.C2.D0.R0.S09: RdPtrOffsetTxDq: 07
N6.C2.D0.R0.S09: RdPtrOffsetTxDq: 06
N0.C2.D0.R0.S07: wrcmd2dqsstartlatency: 04
N2.C3.D0.R0.S01: RdPtrOffsetTxDq: 08
N4.C2.D0.R0.S10: RdPtrOffsetTxDq: 07
N6.C2.D0.R0.S09: RdPtrOffsetTxDqs: 07
N0.C2.D0.R0.S07: RdPtrOffsetTxDq: 05
N2.C3.D0.R0.S02: RdPtrOffsetTxDq: 07
N4.C2.D0.R0.S11: RdPtrOffsetTxDq: 06
N6.C2.D0.R0.S09: PiTxDqs: 48
N0.C2.D0.R0.S07: RdPtrOffsetTxDqs: 07
N2.C3.D0.R0.S03: RdPtrOffsetTxDq: 07
N4.C2.D0.R0.S12: RdPtrOffsetTxDq: 06
N6.C2.D0.R0.S10: wrcmd2dqsstartlatency: 04
N0.C2.D0.R0.S07: PiTxDqs: 18
N2.C3.D0.R0.S04: RdPtrOffsetTxDq: 07
N4.C2.D0.R0.S13: RdPtrOffsetTxDq: 06
N6.C2.D0.R0.S10: RdPtrOffsetTxDq: 06
N0.C2.D0.R0.S08: wrcmd2dqsstartlatency: 04
N2.C3.D0.R0.S05: RdPtrOffsetTxDq: 07
N4.C2.D0.R0.S14: RdPtrOffsetTxDq: 06
N6.C2.D0.R0.S10: RdPtrOffsetTxDqs: 07
N0.C2.D0.R0.S08: RdPtrOffsetTxDq: 05
N2.C3.D0.R0.S06: RdPtrOffsetTxDq: 07
N4.C2.D0.R0.S15: RdPtrOffsetTxDq: 06
N6.C2.D0.R0.S10: PiTxDqs: 33
N0.C2.D0.R0.S08: RdPtrOffsetTxDqs: 06
N2.C3.D0.R0.S07: RdPtrOffsetTxDq: 07
N4.C2.D0.R0.S16: RdPtrOffsetTxDq: 06
N6.C2.D0.R0.S11: wrcmd2dqsstartlatency: 04
N0.C2.D0.R0.S08: PiTxDqs: 56
N2.C3.D0.R0.S08: RdPtrOffsetTxDq: 07
N4.C2.D0.R0.S17: RdPtrOffsetTxDq: 06
N6.C2.D0.R0.S11: RdPtrOffsetTxDq: 05
N0.C2.D0.R0.S09: wrcmd2dqsstartlatency: 04
N2.C3.D0.R0.S09: RdPtrOffsetTxDq: 08
N4.C2.D0.R0.S00: RdPtrOffsetTxDq: 08
N6.C2.D0.R0.S11: RdPtrOffsetTxDqs: 07
N0.C2.D0.R0.S09: RdPtrOffsetTxDq: 06
N2.C3.D0.R0.S10: RdPtrOffsetTxDq: 08
N4.C2.D0.R0.S01: RdPtrOffsetTxDq: 08
N6.C2.D0.R0.S11: PiTxDqs: 25
N0.C2.D0.R0.S09: RdPtrOffsetTxDqs: 07
N2.C3.D0.R0.S11: RdPtrOffsetTxDq: 07
N4.C2.D0.R0.S02: RdPtrOffsetTxDq: 07
N6.C2.D0.R0.S12: wrcmd2dqsstartlatency: 04
N0.C2.D0.R0.S09: PiTxDqs: 55
N2.C3.D0.R0.S12: RdPtrOffsetTxDq: 07
N4.C2.D0.R0.S03: RdPtrOffsetTxDq: 07
N6.C2.D0.R0.S12: RdPtrOffsetTxDq: 05
N0.C2.D0.R0.S10: wrcmd2dqsstartlatency: 04
N2.C3.D0.R0.S13: RdPtrOffsetTxDq: 07
N4.C2.D0.R0.S04: RdPtrOffsetTxDq: 06
N6.C2.D0.R0.S12: RdPtrOffsetTxDqs: 07
N0.C2.D0.R0.S10: RdPtrOffsetTxDq: 06
N2.C3.D0.R0.S14: RdPtrOffsetTxDq: 07
N4.C2.D0.R0.S05: RdPtrOffsetTxDq: 07
N6.C2.D0.R0.S12: PiTxDqs: 04
N0.C2.D0.R0.S10: RdPtrOffsetTxDqs: 07
N2.C3.D0.R0.S15: RdPtrOffsetTxDq: 07
N4.C2.D0.R0.S06: RdPtrOffsetTxDq: 07
N6.C2.D0.R0.S13: wrcmd2dqsstartlatency: 04
N0.C2.D0.R0.S10: PiTxDqs: 41
N2.C3.D0.R0.S16: RdPtrOffsetTxDq: 07
N4.C2.D0.R0.S07: RdPtrOffsetTxDq: 07
N6.C2.D0.R0.S13: RdPtrOffsetTxDq: 04
N0.C2.D0.R0.S11: wrcmd2dqsstartlatency: 04
N2.C3.D0.R0.S17: RdPtrOffsetTxDq: 07
N4.C2.D0.R0.S08: RdPtrOffsetTxDq: 07
N6.C2.D0.R0.S13: RdPtrOffsetTxDqs: 06
N0.C2.D0.R0.S11: RdPtrOffsetTxDq: 05
N2.C3.D0.R0.S00: Total Delay in PI ticks: TxDQ = 982
N4.C2.D0.R0.S09: RdPtrOffsetTxDq: 08
N6.C2.D0.R0.S13: PiTxDqs: 29
N0.C2.D0.R0.S11: RdPtrOffsetTxDqs: 07
N2.C3.D0.R0.S01: Total Delay in PI ticks: TxDQ = 966
N4.C2.D0.R0.S10: RdPtrOffsetTxDq: 08
N6.C2.D0.R0.S14: wrcmd2dqsstartlatency: 04
N0.C2.D0.R0.S11: PiTxDqs: 30
N2.C3.D0.R0.S02: Total Delay in PI ticks: TxDQ = 958
N4.C2.D0.R0.S11: RdPtrOffsetTxDq: 07
N6.C2.D0.R0.S14: RdPtrOffsetTxDq: 05
N0.C2.D0.R0.S12: wrcmd2dqsstartlatency: 04
N2.C3.D0.R0.S03: Total Delay in PI ticks: TxDQ = 940
N4.C2.D0.R0.S12: RdPtrOffsetTxDq: 07
N6.C2.D0.R0.S14: RdPtrOffsetTxDqs: 06
N0.C2.D0.R0.S12: RdPtrOffsetTxDq: 05
N2.C3.D0.R0.S04: Total Delay in PI ticks: TxDQ = 906
N4.C2.D0.R0.S13: RdPtrOffsetTxDq: 07
N6.C2.D0.R0.S14: PiTxDqs: 56
N0.C2.D0.R0.S12: RdPtrOffsetTxDqs: 07
N2.C3.D0.R0.S05: Total Delay in PI ticks: TxDQ = 918
N4.C2.D0.R0.S14: RdPtrOffsetTxDq: 07
N6.C2.D0.R0.S15: wrcmd2dqsstartlatency: 04
N0.C2.D0.R0.S12: PiTxDqs: 10
N2.C3.D0.R0.S06: Total Delay in PI ticks: TxDQ = 934
N4.C2.D0.R0.S15: RdPtrOffsetTxDq: 07
N6.C2.D0.R0.S15: RdPtrOffsetTxDq: 05
N0.C2.D0.R0.S13: wrcmd2dqsstartlatency: 04
N2.C3.D0.R0.S07: Total Delay in PI ticks: TxDQ = 950
N4.C2.D0.R0.S16: RdPtrOffsetTxDq: 07
N6.C2.D0.R0.S15: RdPtrOffsetTxDqs: 06
N0.C2.D0.R0.S13: RdPtrOffsetTxDq: 05
N2.C3.D0.R0.S08: Total Delay in PI ticks: TxDQ = 925
N4.C2.D0.R0.S17: RdPtrOffsetTxDq: 07
N6.C2.D0.R0.S15: PiTxDqs: 57
N0.C2.D0.R0.S13: RdPtrOffsetTxDqs: 06
N2.C3.D0.R0.S09: Total Delay in PI ticks: TxDQ = 982
N4.C2.D0.R0.S00: Total Delay in PI ticks: TxDQ = 977
N6.C2.D0.R0.S16: wrcmd2dqsstartlatency: 04
N0.C2.D0.R0.S13: PiTxDqs: 33
N2.C3.D0.R0.S10: Total Delay in PI ticks: TxDQ = 967
N4.C2.D0.R0.S01: Total Delay in PI ticks: TxDQ = 963
N6.C2.D0.R0.S16: RdPtrOffsetTxDq: 05
N0.C2.D0.R0.S14: wrcmd2dqsstartlatency: 04
N2.C3.D0.R0.S11: Total Delay in PI ticks: TxDQ = 959
N4.C2.D0.R0.S02: Total Delay in PI ticks: TxDQ = 953
N6.C2.D0.R0.S16: RdPtrOffsetTxDqs: 07
N0.C2.D0.R0.S14: RdPtrOffsetTxDq: 05
N2.C3.D0.R0.S12: Total Delay in PI ticks: TxDQ = 941
N4.C2.D0.R0.S03: Total Delay in PI ticks: TxDQ = 935
N6.C2.D0.R0.S16: PiTxDqs: 14
N0.C2.D0.R0.S14: RdPtrOffsetTxDqs: 06
N2.C3.D0.R0.S13: Total Delay in PI ticks: TxDQ = 907
N4.C2.D0.R0.S04: Total Delay in PI ticks: TxDQ = 895
N6.C2.D0.R0.S17: wrcmd2dqsstartlatency: 04
N0.C2.D0.R0.S14: PiTxDqs: 62
N2.C3.D0.R0.S14: Total Delay in PI ticks: TxDQ = 920
N4.C2.D0.R0.S05: Total Delay in PI ticks: TxDQ = 922
N6.C2.D0.R0.S17: RdPtrOffsetTxDq: 05
N0.C2.D0.R0.S15: wrcmd2dqsstartlatency: 04
N2.C3.D0.R0.S15: Total Delay in PI ticks: TxDQ = 934
N4.C2.D0.R0.S06: Total Delay in PI ticks: TxDQ = 924
N6.C2.D0.R0.S17: RdPtrOffsetTxDqs: 06
N0.C2.D0.R0.S15: RdPtrOffsetTxDq: 05
N2.C3.D0.R0.S16: Total Delay in PI ticks: TxDQ = 948
N4.C2.D0.R0.S07: Total Delay in PI ticks: TxDQ = 943
N6.C2.D0.R0.S17: PiTxDqs: 48
N0.C2.D0.R0.S15: RdPtrOffsetTxDqs: 07
N2.C3.D0.R0.S17: Total Delay in PI ticks: TxDQ = 926
N4.C2.D0.R0.S08: Total Delay in PI ticks: TxDQ = 914
N6.C2.D0.R0.S00: RdPtrOffsetTxDq: 07
N0.C2.D0.R0.S15: PiTxDqs: 00
N2.C3.D0.R1.S00: wrcmd2dqsstartlatency: 04
N4.C2.D0.R0.S09: Total Delay in PI ticks: TxDQ = 981
N6.C2.D0.R0.S01: RdPtrOffsetTxDq: 06
N0.C2.D0.R0.S16: wrcmd2dqsstartlatency: 04
N2.C3.D0.R1.S00: RdPtrOffsetTxDq: 06
N4.C2.D0.R0.S10: Total Delay in PI ticks: TxDQ = 965
N6.C2.D0.R0.S02: RdPtrOffsetTxDq: 06
N0.C2.D0.R0.S16: RdPtrOffsetTxDq: 05
N2.C3.D0.R1.S00: RdPtrOffsetTxDqs: 07
N4.C2.D0.R0.S11: Total Delay in PI ticks: TxDQ = 954
N6.C2.D0.R0.S03: RdPtrOffsetTxDq: 06
N0.C2.D0.R0.S16: RdPtrOffsetTxDqs: 07
N2.C3.D0.R1.S00: PiTxDqs: 50
N4.C2.D0.R0.S12: Total Delay in PI ticks: TxDQ = 937
N6.C2.D0.R0.S04: RdPtrOffsetTxDq: 05
N0.C2.D0.R0.S16: PiTxDqs: 19
N2.C3.D0.R1.S01: wrcmd2dqsstartlatency: 04
N4.C2.D0.R0.S13: Total Delay in PI ticks: TxDQ = 896
N6.C2.D0.R0.S05: RdPtrOffsetTxDq: 06
N0.C2.D0.R0.S17: wrcmd2dqsstartlatency: 04
N2.C3.D0.R1.S01: RdPtrOffsetTxDq: 05
N4.C2.D0.R0.S14: Total Delay in PI ticks: TxDQ = 926
N6.C2.D0.R0.S06: RdPtrOffsetTxDq: 06
N0.C2.D0.R0.S17: RdPtrOffsetTxDq: 05
N2.C3.D0.R1.S01: RdPtrOffsetTxDqs: 07
N4.C2.D0.R0.S15: Total Delay in PI ticks: TxDQ = 926
N6.C2.D0.R0.S07: RdPtrOffsetTxDq: 06
N0.C2.D0.R0.S17: RdPtrOffsetTxDqs: 06
N2.C3.D0.R1.S01: PiTxDqs: 30
N4.C2.D0.R0.S16: Total Delay in PI ticks: TxDQ = 944
N6.C2.D0.R0.S08: RdPtrOffsetTxDq: 06
N0.C2.D0.R0.S17: PiTxDqs: 55
N2.C3.D0.R1.S02: wrcmd2dqsstartlatency: 04
N4.C2.D0.R0.S17: Total Delay in PI ticks: TxDQ = 913
N6.C2.D0.R0.S09: RdPtrOffsetTxDq: 07
N0.C2.D0.R0.S00: RdPtrOffsetTxDq: 07
N2.C3.D0.R1.S02: RdPtrOffsetTxDq: 05
N4.C2.D0.R1.S00: wrcmd2dqsstartlatency: 04
N6.C2.D0.R0.S10: RdPtrOffsetTxDq: 07
N0.C2.D0.R0.S01: RdPtrOffsetTxDq: 07
N2.C3.D0.R1.S02: RdPtrOffsetTxDqs: 07
N4.C2.D0.R1.S00: RdPtrOffsetTxDq: 06
N6.C2.D0.R0.S11: RdPtrOffsetTxDq: 06
N0.C2.D0.R0.S02: RdPtrOffsetTxDq: 06
N2.C3.D0.R1.S02: PiTxDqs: 22
N4.C2.D0.R1.S00: RdPtrOffsetTxDqs: 07
N6.C2.D0.R0.S12: RdPtrOffsetTxDq: 06
N0.C2.D0.R0.S03: RdPtrOffsetTxDq: 06
N2.C3.D0.R1.S03: wrcmd2dqsstartlatency: 04
N4.C2.D0.R1.S00: PiTxDqs: 44
N6.C2.D0.R0.S13: RdPtrOffsetTxDq: 05
N0.C2.D0.R0.S04: RdPtrOffsetTxDq: 06
N2.C3.D0.R1.S03: RdPtrOffsetTxDq: 05
N4.C2.D0.R1.S01: wrcmd2dqsstartlatency: 04
N6.C2.D0.R0.S14: RdPtrOffsetTxDq: 06
N0.C2.D0.R0.S05: RdPtrOffsetTxDq: 06
N2.C3.D0.R1.S03: RdPtrOffsetTxDqs: 07
N4.C2.D0.R1.S01: RdPtrOffsetTxDq: 05
N6.C2.D0.R0.S15: RdPtrOffsetTxDq: 06
N0.C2.D0.R0.S06: RdPtrOffsetTxDq: 06
N2.C3.D0.R1.S03: PiTxDqs: 07
N4.C2.D0.R1.S01: RdPtrOffsetTxDqs: 07
N6.C2.D0.R0.S16: RdPtrOffsetTxDq: 06
N0.C2.D0.R0.S07: RdPtrOffsetTxDq: 06
N2.C3.D0.R1.S04: wrcmd2dqsstartlatency: 04
N4.C2.D0.R1.S01: PiTxDqs: 30
N6.C2.D0.R0.S17: RdPtrOffsetTxDq: 06
N0.C2.D0.R0.S08: RdPtrOffsetTxDq: 06
N2.C3.D0.R1.S04: RdPtrOffsetTxDq: 05
N4.C2.D0.R1.S02: wrcmd2dqsstartlatency: 04
N6.C2.D0.R0.S00: RdPtrOffsetTxDq: 08
N0.C2.D0.R0.S09: RdPtrOffsetTxDq: 07
N2.C3.D0.R1.S04: RdPtrOffsetTxDqs: 06
N4.C2.D0.R1.S02: RdPtrOffsetTxDq: 05
N6.C2.D0.R0.S01: RdPtrOffsetTxDq: 07
N0.C2.D0.R0.S10: RdPtrOffsetTxDq: 07
N2.C3.D0.R1.S04: PiTxDqs: 36
N4.C2.D0.R1.S02: RdPtrOffsetTxDqs: 07
N6.C2.D0.R0.S02: RdPtrOffsetTxDq: 07
N0.C2.D0.R0.S11: RdPtrOffsetTxDq: 06
N2.C3.D0.R1.S05: wrcmd2dqsstartlatency: 04
N4.C2.D0.R1.S02: PiTxDqs: 19
N6.C2.D0.R0.S03: RdPtrOffsetTxDq: 07
N0.C2.D0.R0.S12: RdPtrOffsetTxDq: 06
N2.C3.D0.R1.S05: RdPtrOffsetTxDq: 05
N4.C2.D0.R1.S03: wrcmd2dqsstartlatency: 04
N6.C2.D0.R0.S04: RdPtrOffsetTxDq: 06
N0.C2.D0.R0.S13: RdPtrOffsetTxDq: 06
N2.C3.D0.R1.S05: RdPtrOffsetTxDqs: 06
N4.C2.D0.R1.S03: RdPtrOffsetTxDq: 05
N6.C2.D0.R0.S05: RdPtrOffsetTxDq: 07
N0.C2.D0.R0.S14: RdPtrOffsetTxDq: 06
N2.C3.D0.R1.S05: PiTxDqs: 49
N4.C2.D0.R1.S03: RdPtrOffsetTxDqs: 07
N6.C2.D0.R0.S06: RdPtrOffsetTxDq: 07
N0.C2.D0.R0.S15: RdPtrOffsetTxDq: 06
N2.C3.D0.R1.S06: wrcmd2dqsstartlatency: 04
N4.C2.D0.R1.S03: PiTxDqs: 04
N6.C2.D0.R0.S07: RdPtrOffsetTxDq: 07
N0.C2.D0.R0.S16: RdPtrOffsetTxDq: 06
N2.C3.D0.R1.S06: RdPtrOffsetTxDq: 05
N4.C2.D0.R1.S04: wrcmd2dqsstartlatency: 04
N6.C2.D0.R0.S08: RdPtrOffsetTxDq: 07
N0.C2.D0.R0.S17: RdPtrOffsetTxDq: 06
N2.C3.D0.R1.S06: RdPtrOffsetTxDqs: 06
N4.C2.D0.R1.S04: RdPtrOffsetTxDq: 04
N6.C2.D0.R0.S09: RdPtrOffsetTxDq: 08
N0.C2.D0.R0.S00: RdPtrOffsetTxDq: 08
N2.C3.D0.R1.S06: PiTxDqs: 63
N4.C2.D0.R1.S04: RdPtrOffsetTxDqs: 06
N6.C2.D0.R0.S10: RdPtrOffsetTxDq: 08
N0.C2.D0.R0.S01: RdPtrOffsetTxDq: 08
N2.C3.D0.R1.S07: wrcmd2dqsstartlatency: 04
N4.C2.D0.R1.S04: PiTxDqs: 24
N6.C2.D0.R0.S11: RdPtrOffsetTxDq: 07
N0.C2.D0.R0.S02: RdPtrOffsetTxDq: 07
N2.C3.D0.R1.S07: RdPtrOffsetTxDq: 05
N4.C2.D0.R1.S05: wrcmd2dqsstartlatency: 04
N6.C2.D0.R0.S12: RdPtrOffsetTxDq: 07
N0.C2.D0.R0.S03: RdPtrOffsetTxDq: 07
N2.C3.D0.R1.S07: RdPtrOffsetTxDqs: 07
N4.C2.D0.R1.S05: RdPtrOffsetTxDq: 05
N6.C2.D0.R0.S13: RdPtrOffsetTxDq: 06
N0.C2.D0.R0.S04: RdPtrOffsetTxDq: 07
N2.C3.D0.R1.S07: PiTxDqs: 16
N4.C2.D0.R1.S05: RdPtrOffsetTxDqs: 06
N6.C2.D0.R0.S14: RdPtrOffsetTxDq: 07
N0.C2.D0.R0.S05: RdPtrOffsetTxDq: 07
N2.C3.D0.R1.S08: wrcmd2dqsstartlatency: 04
N4.C2.D0.R1.S05: PiTxDqs: 54
N6.C2.D0.R0.S15: RdPtrOffsetTxDq: 07
N0.C2.D0.R0.S06: RdPtrOffsetTxDq: 07
N2.C3.D0.R1.S08: RdPtrOffsetTxDq: 05
N4.C2.D0.R1.S06: wrcmd2dqsstartlatency: 04
N6.C2.D0.R0.S16: RdPtrOffsetTxDq: 07
N0.C2.D0.R0.S07: RdPtrOffsetTxDq: 07
N2.C3.D0.R1.S08: RdPtrOffsetTxDqs: 06
N4.C2.D0.R1.S06: RdPtrOffsetTxDq: 05
N6.C2.D0.R0.S17: RdPtrOffsetTxDq: 07
N0.C2.D0.R0.S08: RdPtrOffsetTxDq: 07
N2.C3.D0.R1.S08: PiTxDqs: 54
N4.C2.D0.R1.S06: RdPtrOffsetTxDqs: 06
N6.C2.D0.R0.S00: Total Delay in PI ticks: TxDQ = 974
N0.C2.D0.R0.S09: RdPtrOffsetTxDq: 08
N2.C3.D0.R1.S09: wrcmd2dqsstartlatency: 04
N4.C2.D0.R1.S06: PiTxDqs: 51
N6.C2.D0.R0.S01: Total Delay in PI ticks: TxDQ = 961
N0.C2.D0.R0.S10: RdPtrOffsetTxDq: 08
N2.C3.D0.R1.S09: RdPtrOffsetTxDq: 06
N4.C2.D0.R1.S07: wrcmd2dqsstartlatency: 04
N6.C2.D0.R0.S02: Total Delay in PI ticks: TxDQ = 955
N0.C2.D0.R0.S11: RdPtrOffsetTxDq: 07
N2.C3.D0.R1.S09: RdPtrOffsetTxDqs: 07
N4.C2.D0.R1.S07: RdPtrOffsetTxDq: 05
N6.C2.D0.R0.S03: Total Delay in PI ticks: TxDQ = 932
N0.C2.D0.R0.S12: RdPtrOffsetTxDq: 07
N2.C3.D0.R1.S09: PiTxDqs: 47
N4.C2.D0.R1.S07: RdPtrOffsetTxDqs: 07
N6.C2.D0.R0.S04: Total Delay in PI ticks: TxDQ = 893
N0.C2.D0.R0.S13: RdPtrOffsetTxDq: 07
N2.C3.D0.R1.S10: wrcmd2dqsstartlatency: 04
N4.C2.D0.R1.S07: PiTxDqs: 11
N6.C2.D0.R0.S05: Total Delay in PI ticks: TxDQ = 921
N0.C2.D0.R0.S14: RdPtrOffsetTxDq: 07
N2.C3.D0.R1.S10: RdPtrOffsetTxDq: 05
N4.C2.D0.R1.S08: wrcmd2dqsstartlatency: 04
N6.C2.D0.R0.S06: Total Delay in PI ticks: TxDQ = 923
N0.C2.D0.R0.S15: RdPtrOffsetTxDq: 07
N2.C3.D0.R1.S10: RdPtrOffsetTxDqs: 07
N4.C2.D0.R1.S08: RdPtrOffsetTxDq: 05
N6.C2.D0.R0.S07: Total Delay in PI ticks: TxDQ = 940
N0.C2.D0.R0.S16: RdPtrOffsetTxDq: 07
N2.C3.D0.R1.S10: PiTxDqs: 31
N4.C2.D0.R1.S08: RdPtrOffsetTxDqs: 06
N6.C2.D0.R0.S08: Total Delay in PI ticks: TxDQ = 911
N0.C2.D0.R0.S17: RdPtrOffsetTxDq: 07
N2.C3.D0.R1.S11: wrcmd2dqsstartlatency: 04
N4.C2.D0.R1.S08: PiTxDqs: 46
N6.C2.D0.R0.S09: Total Delay in PI ticks: TxDQ = 974
N0.C2.D0.R0.S00: Total Delay in PI ticks: TxDQ = 981
N2.C3.D0.R1.S11: RdPtrOffsetTxDq: 05
N4.C2.D0.R1.S09: wrcmd2dqsstartlatency: 04
N6.C2.D0.R0.S10: Total Delay in PI ticks: TxDQ = 960
N0.C2.D0.R0.S01: Total Delay in PI ticks: TxDQ = 964
N2.C3.D0.R1.S11: RdPtrOffsetTxDqs: 07
N4.C2.D0.R1.S09: RdPtrOffsetTxDq: 06
N6.C2.D0.R0.S11: Total Delay in PI ticks: TxDQ = 954
N0.C2.D0.R0.S02: Total Delay in PI ticks: TxDQ = 956
N2.C3.D0.R1.S11: PiTxDqs: 24
N4.C2.D0.R1.S09: RdPtrOffsetTxDqs: 07
N6.C2.D0.R0.S12: Total Delay in PI ticks: TxDQ = 931
N0.C2.D0.R0.S03: Total Delay in PI ticks: TxDQ = 936
N2.C3.D0.R1.S12: wrcmd2dqsstartlatency: 04
N4.C2.D0.R1.S09: PiTxDqs: 44
N6.C2.D0.R0.S13: Total Delay in PI ticks: TxDQ = 893
N0.C2.D0.R0.S04: Total Delay in PI ticks: TxDQ = 900
N2.C3.D0.R1.S12: RdPtrOffsetTxDq: 05
N4.C2.D0.R1.S10: wrcmd2dqsstartlatency: 04
N6.C2.D0.R0.S14: Total Delay in PI ticks: TxDQ = 921
N0.C2.D0.R0.S05: Total Delay in PI ticks: TxDQ = 925
N2.C3.D0.R1.S12: RdPtrOffsetTxDqs: 07
N4.C2.D0.R1.S10: RdPtrOffsetTxDq: 05
N6.C2.D0.R0.S15: Total Delay in PI ticks: TxDQ = 923
N0.C2.D0.R0.S06: Total Delay in PI ticks: TxDQ = 926
N2.C3.D0.R1.S12: PiTxDqs: 09
N4.C2.D0.R1.S10: RdPtrOffsetTxDqs: 07
N6.C2.D0.R0.S16: Total Delay in PI ticks: TxDQ = 941
N0.C2.D0.R0.S07: Total Delay in PI ticks: TxDQ = 944
N2.C3.D0.R1.S13: wrcmd2dqsstartlatency: 04
N4.C2.D0.R1.S10: PiTxDqs: 32
N6.C2.D0.R0.S17: Total Delay in PI ticks: TxDQ = 909
N0.C2.D0.R0.S08: Total Delay in PI ticks: TxDQ = 918
N2.C3.D0.R1.S13: RdPtrOffsetTxDq: 05
N4.C2.D0.R1.S11: wrcmd2dqsstartlatency: 04
N6.C2.D0.R1.S00: wrcmd2dqsstartlatency: 04
N0.C2.D0.R0.S09: Total Delay in PI ticks: TxDQ = 982
N2.C3.D0.R1.S13: RdPtrOffsetTxDqs: 06
N4.C2.D0.R1.S11: RdPtrOffsetTxDq: 05
N6.C2.D0.R1.S00: RdPtrOffsetTxDq: 06
N0.C2.D0.R0.S10: Total Delay in PI ticks: TxDQ = 965
N2.C3.D0.R1.S13: PiTxDqs: 37
N4.C2.D0.R1.S11: RdPtrOffsetTxDqs: 07
N6.C2.D0.R1.S00: RdPtrOffsetTxDqs: 07
N0.C2.D0.R0.S11: Total Delay in PI ticks: TxDQ = 957
N2.C3.D0.R1.S14: wrcmd2dqsstartlatency: 04
N4.C2.D0.R1.S11: PiTxDqs: 19
N6.C2.D0.R1.S00: PiTxDqs: 40
N0.C2.D0.R0.S12: Total Delay in PI ticks: TxDQ = 936
N2.C3.D0.R1.S14: RdPtrOffsetTxDq: 05
N4.C2.D0.R1.S12: wrcmd2dqsstartlatency: 04
N6.C2.D0.R1.S01: wrcmd2dqsstartlatency: 04
N0.C2.D0.R0.S13: Total Delay in PI ticks: TxDQ = 897
N2.C3.D0.R1.S14: RdPtrOffsetTxDqs: 06
N4.C2.D0.R1.S12: RdPtrOffsetTxDq: 05
N6.C2.D0.R1.S01: RdPtrOffsetTxDq: 05
N0.C2.D0.R0.S14: Total Delay in PI ticks: TxDQ = 926
N2.C3.D0.R1.S14: PiTxDqs: 49
N4.C2.D0.R1.S12: RdPtrOffsetTxDqs: 07
N6.C2.D0.R1.S01: RdPtrOffsetTxDqs: 07
N0.C2.D0.R0.S15: Total Delay in PI ticks: TxDQ = 927
N2.C3.D0.R1.S15: wrcmd2dqsstartlatency: 04
N4.C2.D0.R1.S12: PiTxDqs: 06
N6.C2.D0.R1.S01: PiTxDqs: 25
N0.C2.D0.R0.S16: Total Delay in PI ticks: TxDQ = 944
N2.C3.D0.R1.S15: RdPtrOffsetTxDq: 05
N4.C2.D0.R1.S13: wrcmd2dqsstartlatency: 04
N6.C2.D0.R1.S02: wrcmd2dqsstartlatency: 04
N0.C2.D0.R0.S17: Total Delay in PI ticks: TxDQ = 917
N2.C3.D0.R1.S15: RdPtrOffsetTxDqs: 07
N4.C2.D0.R1.S13: RdPtrOffsetTxDq: 04
N6.C2.D0.R1.S02: RdPtrOffsetTxDq: 05
N0.C2.D0.R1.S00: wrcmd2dqsstartlatency: 04
N2.C3.D0.R1.S15: PiTxDqs: 00
N4.C2.D0.R1.S13: RdPtrOffsetTxDqs: 06
N6.C2.D0.R1.S02: RdPtrOffsetTxDqs: 07
N0.C2.D0.R1.S00: RdPtrOffsetTxDq: 06
N2.C3.D0.R1.S16: wrcmd2dqsstartlatency: 04
N4.C2.D0.R1.S13: PiTxDqs: 26
N6.C2.D0.R1.S02: PiTxDqs: 16
N0.C2.D0.R1.S00: RdPtrOffsetTxDqs: 07
N2.C3.D0.R1.S16: RdPtrOffsetTxDq: 05
N4.C2.D0.R1.S14: wrcmd2dqsstartlatency: 04
N6.C2.D0.R1.S03: wrcmd2dqsstartlatency: 04
N0.C2.D0.R1.S00: PiTxDqs: 46
N2.C3.D0.R1.S16: RdPtrOffsetTxDqs: 07
N4.C2.D0.R1.S14: RdPtrOffsetTxDq: 05
N6.C2.D0.R1.S03: RdPtrOffsetTxDq: 05
N0.C2.D0.R1.S01: wrcmd2dqsstartlatency: 04
N2.C3.D0.R1.S16: PiTxDqs: 17
N4.C2.D0.R1.S14: RdPtrOffsetTxDqs: 06
N6.C2.D0.R1.S03: RdPtrOffsetTxDqs: 06
N0.C2.D0.R1.S01: RdPtrOffsetTxDq: 05
N2.C3.D0.R1.S17: wrcmd2dqsstartlatency: 04
N4.C2.D0.R1.S14: PiTxDqs: 55
N6.C2.D0.R1.S03: PiTxDqs: 61
N0.C2.D0.R1.S01: RdPtrOffsetTxDqs: 07
N2.C3.D0.R1.S17: RdPtrOffsetTxDq: 05
N4.C2.D0.R1.S15: wrcmd2dqsstartlatency: 04
N6.C2.D0.R1.S04: wrcmd2dqsstartlatency: 04
N0.C2.D0.R1.S01: PiTxDqs: 33
N2.C3.D0.R1.S17: RdPtrOffsetTxDqs: 06
N4.C2.D0.R1.S15: RdPtrOffsetTxDq: 05
N6.C2.D0.R1.S04: RdPtrOffsetTxDq: 04
N0.C2.D0.R1.S02: wrcmd2dqsstartlatency: 04
N2.C3.D0.R1.S17: PiTxDqs: 53
N4.C2.D0.R1.S15: RdPtrOffsetTxDqs: 06
N6.C2.D0.R1.S04: RdPtrOffsetTxDqs: 06
N0.C2.D0.R1.S02: RdPtrOffsetTxDq: 05
N2.C3.D0.R1.S00: RdPtrOffsetTxDq: 07
N4.C2.D0.R1.S15: PiTxDqs: 53
N6.C2.D0.R1.S04: PiTxDqs: 22
N0.C2.D0.R1.S02: RdPtrOffsetTxDqs: 07
N2.C3.D0.R1.S01: RdPtrOffsetTxDq: 06
N4.C2.D0.R1.S16: wrcmd2dqsstartlatency: 04
N6.C2.D0.R1.S05: wrcmd2dqsstartlatency: 04
N0.C2.D0.R1.S02: PiTxDqs: 23
N2.C3.D0.R1.S02: RdPtrOffsetTxDq: 06
N4.C2.D0.R1.S16: RdPtrOffsetTxDq: 05
N6.C2.D0.R1.S05: RdPtrOffsetTxDq: 05
N0.C2.D0.R1.S03: wrcmd2dqsstartlatency: 04
N2.C3.D0.R1.S03: RdPtrOffsetTxDq: 06
N4.C2.D0.R1.S16: RdPtrOffsetTxDqs: 07
N6.C2.D0.R1.S05: RdPtrOffsetTxDqs: 06
N0.C2.D0.R1.S03: RdPtrOffsetTxDq: 05
N2.C3.D0.R1.S04: RdPtrOffsetTxDq: 06
N4.C2.D0.R1.S16: PiTxDqs: 09
N6.C2.D0.R1.S05: PiTxDqs: 52
N0.C2.D0.R1.S03: RdPtrOffsetTxDqs: 07
N2.C3.D0.R1.S05: RdPtrOffsetTxDq: 06
N4.C2.D0.R1.S17: wrcmd2dqsstartlatency: 04
N6.C2.D0.R1.S06: wrcmd2dqsstartlatency: 04
N0.C2.D0.R1.S03: PiTxDqs: 06
N2.C3.D0.R1.S06: RdPtrOffsetTxDq: 06
N4.C2.D0.R1.S17: RdPtrOffsetTxDq: 05
N6.C2.D0.R1.S06: RdPtrOffsetTxDq: 05
N0.C2.D0.R1.S04: wrcmd2dqsstartlatency: 04
N2.C3.D0.R1.S07: RdPtrOffsetTxDq: 06
N4.C2.D0.R1.S17: RdPtrOffsetTxDqs: 06
N6.C2.D0.R1.S06: RdPtrOffsetTxDqs: 06
N0.C2.D0.R1.S04: RdPtrOffsetTxDq: 04
N2.C3.D0.R1.S08: RdPtrOffsetTxDq: 06
N4.C2.D0.R1.S17: PiTxDqs: 43
N6.C2.D0.R1.S06: PiTxDqs: 49
N0.C2.D0.R1.S04: RdPtrOffsetTxDqs: 06
N2.C3.D0.R1.S09: RdPtrOffsetTxDq: 07
N4.C2.D0.R1.S00: RdPtrOffsetTxDq: 07
N6.C2.D0.R1.S07: wrcmd2dqsstartlatency: 04
N0.C2.D0.R1.S04: PiTxDqs: 30
N2.C3.D0.R1.S10: RdPtrOffsetTxDq: 06
N4.C2.D0.R1.S01: RdPtrOffsetTxDq: 06
N6.C2.D0.R1.S07: RdPtrOffsetTxDq: 05
N0.C2.D0.R1.S05: wrcmd2dqsstartlatency: 04
N2.C3.D0.R1.S11: RdPtrOffsetTxDq: 06
N4.C2.D0.R1.S02: RdPtrOffsetTxDq: 06
N6.C2.D0.R1.S07: RdPtrOffsetTxDqs: 07
N0.C2.D0.R1.S05: RdPtrOffsetTxDq: 05
N2.C3.D0.R1.S12: RdPtrOffsetTxDq: 06
N4.C2.D0.R1.S03: RdPtrOffsetTxDq: 06
N6.C2.D0.R1.S07: PiTxDqs: 09
N0.C2.D0.R1.S05: RdPtrOffsetTxDqs: 06
N2.C3.D0.R1.S13: RdPtrOffsetTxDq: 06
N4.C2.D0.R1.S04: RdPtrOffsetTxDq: 05
N6.C2.D0.R1.S08: wrcmd2dqsstartlatency: 04
N0.C2.D0.R1.S05: PiTxDqs: 60
N2.C3.D0.R1.S14: RdPtrOffsetTxDq: 06
N4.C2.D0.R1.S05: RdPtrOffsetTxDq: 06
N6.C2.D0.R1.S08: RdPtrOffsetTxDq: 05
N0.C2.D0.R1.S06: wrcmd2dqsstartlatency: 04
N2.C3.D0.R1.S15: RdPtrOffsetTxDq: 06
N4.C2.D0.R1.S06: RdPtrOffsetTxDq: 06
N6.C2.D0.R1.S08: RdPtrOffsetTxDqs: 06
N0.C2.D0.R1.S06: RdPtrOffsetTxDq: 05
N2.C3.D0.R1.S16: RdPtrOffsetTxDq: 06
N4.C2.D0.R1.S07: RdPtrOffsetTxDq: 06
N6.C2.D0.R1.S08: PiTxDqs: 40
N0.C2.D0.R1.S06: RdPtrOffsetTxDqs: 06
N2.C3.D0.R1.S17: RdPtrOffsetTxDq: 06
N4.C2.D0.R1.S08: RdPtrOffsetTxDq: 06
N6.C2.D0.R1.S09: wrcmd2dqsstartlatency: 04
N0.C2.D0.R1.S06: PiTxDqs: 55
N2.C3.D0.R1.S00: RdPtrOffsetTxDq: 08
N4.C2.D0.R1.S09: RdPtrOffsetTxDq: 07
N6.C2.D0.R1.S09: RdPtrOffsetTxDq: 06
N0.C2.D0.R1.S07: wrcmd2dqsstartlatency: 04
N2.C3.D0.R1.S01: RdPtrOffsetTxDq: 07
N4.C2.D0.R1.S10: RdPtrOffsetTxDq: 06
N6.C2.D0.R1.S09: RdPtrOffsetTxDqs: 07
N0.C2.D0.R1.S07: RdPtrOffsetTxDq: 05
N2.C3.D0.R1.S02: RdPtrOffsetTxDq: 07
N4.C2.D0.R1.S11: RdPtrOffsetTxDq: 06
N6.C2.D0.R1.S09: PiTxDqs: 39
N0.C2.D0.R1.S07: RdPtrOffsetTxDqs: 07
N2.C3.D0.R1.S03: RdPtrOffsetTxDq: 07
N4.C2.D0.R1.S12: RdPtrOffsetTxDq: 06
N6.C2.D0.R1.S10: wrcmd2dqsstartlatency: 04
N0.C2.D0.R1.S07: PiTxDqs: 14
N2.C3.D0.R1.S04: RdPtrOffsetTxDq: 07
N4.C2.D0.R1.S13: RdPtrOffsetTxDq: 05
N6.C2.D0.R1.S10: RdPtrOffsetTxDq: 05
N0.C2.D0.R1.S08: wrcmd2dqsstartlatency: 04
N2.C3.D0.R1.S05: RdPtrOffsetTxDq: 07
N4.C2.D0.R1.S14: RdPtrOffsetTxDq: 06
N6.C2.D0.R1.S10: RdPtrOffsetTxDqs: 07
N0.C2.D0.R1.S08: RdPtrOffsetTxDq: 05
N2.C3.D0.R1.S06: RdPtrOffsetTxDq: 07
N4.C2.D0.R1.S15: RdPtrOffsetTxDq: 06
N6.C2.D0.R1.S10: PiTxDqs: 26
N0.C2.D0.R1.S08: RdPtrOffsetTxDqs: 06
N2.C3.D0.R1.S07: RdPtrOffsetTxDq: 07
N4.C2.D0.R1.S16: RdPtrOffsetTxDq: 06
N6.C2.D0.R1.S11: wrcmd2dqsstartlatency: 04
N0.C2.D0.R1.S08: PiTxDqs: 48
N2.C3.D0.R1.S08: RdPtrOffsetTxDq: 07
N4.C2.D0.R1.S17: RdPtrOffsetTxDq: 06
N6.C2.D0.R1.S11: RdPtrOffsetTxDq: 05
N0.C2.D0.R1.S09: wrcmd2dqsstartlatency: 04
N2.C3.D0.R1.S09: RdPtrOffsetTxDq: 08
N4.C2.D0.R1.S00: RdPtrOffsetTxDq: 08
N6.C2.D0.R1.S11: RdPtrOffsetTxDqs: 07
N0.C2.D0.R1.S09: RdPtrOffsetTxDq: 06
N2.C3.D0.R1.S10: RdPtrOffsetTxDq: 07
N4.C2.D0.R1.S01: RdPtrOffsetTxDq: 07
N6.C2.D0.R1.S11: PiTxDqs: 17
N0.C2.D0.R1.S09: RdPtrOffsetTxDqs: 07
N2.C3.D0.R1.S11: RdPtrOffsetTxDq: 07
N4.C2.D0.R1.S02: RdPtrOffsetTxDq: 07
N6.C2.D0.R1.S12: wrcmd2dqsstartlatency: 04
N0.C2.D0.R1.S09: PiTxDqs: 48
N2.C3.D0.R1.S12: RdPtrOffsetTxDq: 07
N4.C2.D0.R1.S03: RdPtrOffsetTxDq: 07
N6.C2.D0.R1.S12: RdPtrOffsetTxDq: 05
N0.C2.D0.R1.S10: wrcmd2dqsstartlatency: 04
N2.C3.D0.R1.S13: RdPtrOffsetTxDq: 07
N4.C2.D0.R1.S04: RdPtrOffsetTxDq: 06
N6.C2.D0.R1.S12: RdPtrOffsetTxDqs: 07
N0.C2.D0.R1.S10: RdPtrOffsetTxDq: 06
N2.C3.D0.R1.S14: RdPtrOffsetTxDq: 07
N4.C2.D0.R1.S05: RdPtrOffsetTxDq: 07
N6.C2.D0.R1.S12: PiTxDqs: 00
N0.C2.D0.R1.S10: RdPtrOffsetTxDqs: 07
N2.C3.D0.R1.S15: RdPtrOffsetTxDq: 07
N4.C2.D0.R1.S06: RdPtrOffsetTxDq: 07
N6.C2.D0.R1.S13: wrcmd2dqsstartlatency: 04
N0.C2.D0.R1.S10: PiTxDqs: 33
N2.C3.D0.R1.S16: RdPtrOffsetTxDq: 07
N4.C2.D0.R1.S07: RdPtrOffsetTxDq: 07
N6.C2.D0.R1.S13: RdPtrOffsetTxDq: 04
N0.C2.D0.R1.S11: wrcmd2dqsstartlatency: 04
N2.C3.D0.R1.S17: RdPtrOffsetTxDq: 07
N4.C2.D0.R1.S08: RdPtrOffsetTxDq: 07
N6.C2.D0.R1.S13: RdPtrOffsetTxDqs: 06
N0.C2.D0.R1.S11: RdPtrOffsetTxDq: 05
N2.C3.D0.R1.S00: Total Delay in PI ticks: TxDQ = 977
N4.C2.D0.R1.S09: RdPtrOffsetTxDq: 08
N6.C2.D0.R1.S13: PiTxDqs: 22
N0.C2.D0.R1.S11: RdPtrOffsetTxDqs: 07
N2.C3.D0.R1.S01: Total Delay in PI ticks: TxDQ = 958
N4.C2.D0.R1.S10: RdPtrOffsetTxDq: 07
N6.C2.D0.R1.S14: wrcmd2dqsstartlatency: 04
N0.C2.D0.R1.S11: PiTxDqs: 24
N2.C3.D0.R1.S02: Total Delay in PI ticks: TxDQ = 950
N4.C2.D0.R1.S11: RdPtrOffsetTxDq: 07
N6.C2.D0.R1.S14: RdPtrOffsetTxDq: 05
N0.C2.D0.R1.S12: wrcmd2dqsstartlatency: 04
N2.C3.D0.R1.S03: Total Delay in PI ticks: TxDQ = 934
N4.C2.D0.R1.S12: RdPtrOffsetTxDq: 07
N6.C2.D0.R1.S14: RdPtrOffsetTxDqs: 06
N0.C2.D0.R1.S12: RdPtrOffsetTxDq: 05
N2.C3.D0.R1.S04: Total Delay in PI ticks: TxDQ = 900
N4.C2.D0.R1.S13: RdPtrOffsetTxDq: 06
N6.C2.D0.R1.S14: PiTxDqs: 53
N0.C2.D0.R1.S12: RdPtrOffsetTxDqs: 07
N2.C3.D0.R1.S05: Total Delay in PI ticks: TxDQ = 914
N4.C2.D0.R1.S14: RdPtrOffsetTxDq: 07
N6.C2.D0.R1.S15: wrcmd2dqsstartlatency: 04
N0.C2.D0.R1.S12: PiTxDqs: 06
N2.C3.D0.R1.S06: Total Delay in PI ticks: TxDQ = 927
N4.C2.D0.R1.S15: RdPtrOffsetTxDq: 07
N6.C2.D0.R1.S15: RdPtrOffsetTxDq: 05
N0.C2.D0.R1.S13: wrcmd2dqsstartlatency: 04
N2.C3.D0.R1.S07: Total Delay in PI ticks: TxDQ = 943
N4.C2.D0.R1.S16: RdPtrOffsetTxDq: 07
N6.C2.D0.R1.S15: RdPtrOffsetTxDqs: 06
N0.C2.D0.R1.S13: RdPtrOffsetTxDq: 04
N2.C3.D0.R1.S08: Total Delay in PI ticks: TxDQ = 918
N4.C2.D0.R1.S17: RdPtrOffsetTxDq: 07
N6.C2.D0.R1.S15: PiTxDqs: 52
N0.C2.D0.R1.S13: RdPtrOffsetTxDqs: 06
N2.C3.D0.R1.S09: Total Delay in PI ticks: TxDQ = 974
N4.C2.D0.R1.S00: Total Delay in PI ticks: TxDQ = 970
N6.C2.D0.R1.S16: wrcmd2dqsstartlatency: 04
N0.C2.D0.R1.S13: PiTxDqs: 30
N2.C3.D0.R1.S10: Total Delay in PI ticks: TxDQ = 959
N4.C2.D0.R1.S01: Total Delay in PI ticks: TxDQ = 956
N6.C2.D0.R1.S16: RdPtrOffsetTxDq: 05
N0.C2.D0.R1.S14: wrcmd2dqsstartlatency: 04
N2.C3.D0.R1.S11: Total Delay in PI ticks: TxDQ = 952
N4.C2.D0.R1.S02: Total Delay in PI ticks: TxDQ = 947
N6.C2.D0.R1.S16: RdPtrOffsetTxDqs: 07
N0.C2.D0.R1.S14: RdPtrOffsetTxDq: 05
N2.C3.D0.R1.S12: Total Delay in PI ticks: TxDQ = 936
N4.C2.D0.R1.S03: Total Delay in PI ticks: TxDQ = 930
N6.C2.D0.R1.S16: PiTxDqs: 08
N0.C2.D0.R1.S14: RdPtrOffsetTxDqs: 06
N2.C3.D0.R1.S13: Total Delay in PI ticks: TxDQ = 900
N4.C2.D0.R1.S04: Total Delay in PI ticks: TxDQ = 889
N6.C2.D0.R1.S17: wrcmd2dqsstartlatency: 04
N0.C2.D0.R1.S14: PiTxDqs: 57
N2.C3.D0.R1.S14: Total Delay in PI ticks: TxDQ = 914
N4.C2.D0.R1.S05: Total Delay in PI ticks: TxDQ = 917
N6.C2.D0.R1.S17: RdPtrOffsetTxDq: 05
N0.C2.D0.R1.S15: wrcmd2dqsstartlatency: 04
N2.C3.D0.R1.S15: Total Delay in PI ticks: TxDQ = 929
N4.C2.D0.R1.S06: Total Delay in PI ticks: TxDQ = 913
N6.C2.D0.R1.S17: RdPtrOffsetTxDqs: 06
N0.C2.D0.R1.S15: RdPtrOffsetTxDq: 05
N2.C3.D0.R1.S16: Total Delay in PI ticks: TxDQ = 944
N4.C2.D0.R1.S07: Total Delay in PI ticks: TxDQ = 937
N6.C2.D0.R1.S17: PiTxDqs: 41
N0.C2.D0.R1.S15: RdPtrOffsetTxDqs: 06
N2.C3.D0.R1.S17: Total Delay in PI ticks: TxDQ = 917
N4.C2.D0.R1.S08: Total Delay in PI ticks: TxDQ = 907
N6.C2.D0.R1.S00: RdPtrOffsetTxDq: 07
N0.C2.D0.R1.S15: PiTxDqs: 55
N2.C3.D1.R0.S00: wrcmd2dqsstartlatency: 04
N4.C2.D0.R1.S09: Total Delay in PI ticks: TxDQ = 968
N6.C2.D0.R1.S01: RdPtrOffsetTxDq: 06
N0.C2.D0.R1.S16: wrcmd2dqsstartlatency: 04
N2.C3.D1.R0.S00: RdPtrOffsetTxDq: 06
N4.C2.D0.R1.S10: Total Delay in PI ticks: TxDQ = 957
N6.C2.D0.R1.S02: RdPtrOffsetTxDq: 06
N0.C2.D0.R1.S16: RdPtrOffsetTxDq: 05
N2.C3.D1.R0.S00: RdPtrOffsetTxDqs: 07
N4.C2.D0.R1.S11: Total Delay in PI ticks: TxDQ = 946
N6.C2.D0.R1.S03: RdPtrOffsetTxDq: 06
N0.C2.D0.R1.S16: RdPtrOffsetTxDqs: 07
N2.C3.D1.R0.S00: PiTxDqs: 60
N4.C2.D0.R1.S12: Total Delay in PI ticks: TxDQ = 933
N6.C2.D0.R1.S04: RdPtrOffsetTxDq: 05
N0.C2.D0.R1.S16: PiTxDqs: 16
N2.C3.D1.R0.S01: wrcmd2dqsstartlatency: 04
N4.C2.D0.R1.S13: Total Delay in PI ticks: TxDQ = 888
N6.C2.D0.R1.S05: RdPtrOffsetTxDq: 06
N0.C2.D0.R1.S17: wrcmd2dqsstartlatency: 04
N2.C3.D1.R0.S01: RdPtrOffsetTxDq: 06
N4.C2.D0.R1.S14: Total Delay in PI ticks: TxDQ = 919
N6.C2.D0.R1.S06: RdPtrOffsetTxDq: 06
N0.C2.D0.R1.S17: RdPtrOffsetTxDq: 05
N2.C3.D1.R0.S01: RdPtrOffsetTxDqs: 07
N4.C2.D0.R1.S15: Total Delay in PI ticks: TxDQ = 917
N6.C2.D0.R1.S07: RdPtrOffsetTxDq: 06
N0.C2.D0.R1.S17: RdPtrOffsetTxDqs: 06
N2.C3.D1.R0.S01: PiTxDqs: 44
N4.C2.D0.R1.S16: Total Delay in PI ticks: TxDQ = 936
N6.C2.D0.R1.S08: RdPtrOffsetTxDq: 06
N0.C2.D0.R1.S17: PiTxDqs: 46
N2.C3.D1.R0.S02: wrcmd2dqsstartlatency: 04
N4.C2.D0.R1.S17: Total Delay in PI ticks: TxDQ = 905
N6.C2.D0.R1.S09: RdPtrOffsetTxDq: 07
N0.C2.D0.R1.S00: RdPtrOffsetTxDq: 07
N2.C3.D1.R0.S02: RdPtrOffsetTxDq: 05
N4.C2.D1.R0.S00: wrcmd2dqsstartlatency: 04
N6.C2.D0.R1.S10: RdPtrOffsetTxDq: 06
N0.C2.D0.R1.S01: RdPtrOffsetTxDq: 06
N2.C3.D1.R0.S02: RdPtrOffsetTxDqs: 07
N4.C2.D1.R0.S00: RdPtrOffsetTxDq: 06
N6.C2.D0.R1.S11: RdPtrOffsetTxDq: 06
N0.C2.D0.R1.S02: RdPtrOffsetTxDq: 06
N2.C3.D1.R0.S02: PiTxDqs: 36
N4.C2.D1.R0.S00: RdPtrOffsetTxDqs: 07
N6.C2.D0.R1.S12: RdPtrOffsetTxDq: 06
N0.C2.D0.R1.S03: RdPtrOffsetTxDq: 06
N2.C3.D1.R0.S03: wrcmd2dqsstartlatency: 04
N4.C2.D1.R0.S00: PiTxDqs: 55
N6.C2.D0.R1.S13: RdPtrOffsetTxDq: 05
N0.C2.D0.R1.S04: RdPtrOffsetTxDq: 05
N2.C3.D1.R0.S03: RdPtrOffsetTxDq: 05
N4.C2.D1.R0.S01: wrcmd2dqsstartlatency: 04
N6.C2.D0.R1.S14: RdPtrOffsetTxDq: 06
N0.C2.D0.R1.S05: RdPtrOffsetTxDq: 06
N2.C3.D1.R0.S03: RdPtrOffsetTxDqs: 07
N4.C2.D1.R0.S01: RdPtrOffsetTxDq: 06
N6.C2.D0.R1.S15: RdPtrOffsetTxDq: 06
N0.C2.D0.R1.S06: RdPtrOffsetTxDq: 06
N2.C3.D1.R0.S03: PiTxDqs: 18
N4.C2.D1.R0.S01: RdPtrOffsetTxDqs: 07
N6.C2.D0.R1.S16: RdPtrOffsetTxDq: 06
N0.C2.D0.R1.S07: RdPtrOffsetTxDq: 06
N2.C3.D1.R0.S04: wrcmd2dqsstartlatency: 04
N4.C2.D1.R0.S01: PiTxDqs: 41
N6.C2.D0.R1.S17: RdPtrOffsetTxDq: 06
N0.C2.D0.R1.S08: RdPtrOffsetTxDq: 06
N2.C3.D1.R0.S04: RdPtrOffsetTxDq: 05
N4.C2.D1.R0.S02: wrcmd2dqsstartlatency: 04
N6.C2.D0.R1.S00: RdPtrOffsetTxDq: 08
N0.C2.D0.R1.S09: RdPtrOffsetTxDq: 07
N2.C3.D1.R0.S04: RdPtrOffsetTxDqs: 06
N4.C2.D1.R0.S02: RdPtrOffsetTxDq: 05
N6.C2.D0.R1.S01: RdPtrOffsetTxDq: 07
N0.C2.D0.R1.S10: RdPtrOffsetTxDq: 07
N2.C3.D1.R0.S04: PiTxDqs: 47
N4.C2.D1.R0.S02: RdPtrOffsetTxDqs: 07
N6.C2.D0.R1.S02: RdPtrOffsetTxDq: 07
N0.C2.D0.R1.S11: RdPtrOffsetTxDq: 06
N2.C3.D1.R0.S05: wrcmd2dqsstartlatency: 04
N4.C2.D1.R0.S02: PiTxDqs: 31
N6.C2.D0.R1.S03: RdPtrOffsetTxDq: 07
N0.C2.D0.R1.S12: RdPtrOffsetTxDq: 06
N2.C3.D1.R0.S05: RdPtrOffsetTxDq: 05
N4.C2.D1.R0.S03: wrcmd2dqsstartlatency: 04
N6.C2.D0.R1.S04: RdPtrOffsetTxDq: 06
N0.C2.D0.R1.S13: RdPtrOffsetTxDq: 05
N2.C3.D1.R0.S05: RdPtrOffsetTxDqs: 06
N4.C2.D1.R0.S03: RdPtrOffsetTxDq: 05
N6.C2.D0.R1.S05: RdPtrOffsetTxDq: 07
N0.C2.D0.R1.S14: RdPtrOffsetTxDq: 06
N2.C3.D1.R0.S05: PiTxDqs: 61
N4.C2.D1.R0.S03: RdPtrOffsetTxDqs: 07
N6.C2.D0.R1.S06: RdPtrOffsetTxDq: 07
N0.C2.D0.R1.S15: RdPtrOffsetTxDq: 06
N2.C3.D1.R0.S06: wrcmd2dqsstartlatency: 04
N4.C2.D1.R0.S03: PiTxDqs: 15
N6.C2.D0.R1.S07: RdPtrOffsetTxDq: 07
N0.C2.D0.R1.S16: RdPtrOffsetTxDq: 06
N2.C3.D1.R0.S06: RdPtrOffsetTxDq: 05
N4.C2.D1.R0.S04: wrcmd2dqsstartlatency: 04
N6.C2.D0.R1.S08: RdPtrOffsetTxDq: 07
N0.C2.D0.R1.S17: RdPtrOffsetTxDq: 06
N2.C3.D1.R0.S06: RdPtrOffsetTxDqs: 07
N4.C2.D1.R0.S04: RdPtrOffsetTxDq: 05
N6.C2.D0.R1.S09: RdPtrOffsetTxDq: 08
N0.C2.D0.R1.S00: RdPtrOffsetTxDq: 08
N2.C3.D1.R0.S06: PiTxDqs: 10
N4.C2.D1.R0.S04: RdPtrOffsetTxDqs: 06
N6.C2.D0.R1.S10: RdPtrOffsetTxDq: 07
N0.C2.D0.R1.S01: RdPtrOffsetTxDq: 07
N2.C3.D1.R0.S07: wrcmd2dqsstartlatency: 04
N4.C2.D1.R0.S04: PiTxDqs: 37
N6.C2.D0.R1.S11: RdPtrOffsetTxDq: 07
N0.C2.D0.R1.S02: RdPtrOffsetTxDq: 07
N2.C3.D1.R0.S07: RdPtrOffsetTxDq: 05
N4.C2.D1.R0.S05: wrcmd2dqsstartlatency: 04
N6.C2.D0.R1.S12: RdPtrOffsetTxDq: 07
N0.C2.D0.R1.S03: RdPtrOffsetTxDq: 07
N2.C3.D1.R0.S07: RdPtrOffsetTxDqs: 07
N4.C2.D1.R0.S05: RdPtrOffsetTxDq: 05
N6.C2.D0.R1.S13: RdPtrOffsetTxDq: 06
N0.C2.D0.R1.S04: RdPtrOffsetTxDq: 06
N2.C3.D1.R0.S07: PiTxDqs: 28
N4.C2.D1.R0.S05: RdPtrOffsetTxDqs: 07
N6.C2.D0.R1.S14: RdPtrOffsetTxDq: 07
N0.C2.D0.R1.S05: RdPtrOffsetTxDq: 07
N2.C3.D1.R0.S08: wrcmd2dqsstartlatency: 04
N4.C2.D1.R0.S05: PiTxDqs: 01
N6.C2.D0.R1.S15: RdPtrOffsetTxDq: 07
N0.C2.D0.R1.S06: RdPtrOffsetTxDq: 07
N2.C3.D1.R0.S08: RdPtrOffsetTxDq: 05
N4.C2.D1.R0.S06: wrcmd2dqsstartlatency: 04
N6.C2.D0.R1.S16: RdPtrOffsetTxDq: 07
N0.C2.D0.R1.S07: RdPtrOffsetTxDq: 07
N2.C3.D1.R0.S08: RdPtrOffsetTxDqs: 07
N4.C2.D1.R0.S06: RdPtrOffsetTxDq: 05
N6.C2.D0.R1.S17: RdPtrOffsetTxDq: 07
N0.C2.D0.R1.S08: RdPtrOffsetTxDq: 07
N2.C3.D1.R0.S08: PiTxDqs: 01
N4.C2.D1.R0.S06: RdPtrOffsetTxDqs: 07
N6.C2.D0.R1.S00: Total Delay in PI ticks: TxDQ = 968
N0.C2.D0.R1.S09: RdPtrOffsetTxDq: 08
N2.C3.D1.R0.S09: wrcmd2dqsstartlatency: 04
N4.C2.D1.R0.S06: PiTxDqs: 01
N6.C2.D0.R1.S01: Total Delay in PI ticks: TxDQ = 952
N0.C2.D0.R1.S10: RdPtrOffsetTxDq: 08
N2.C3.D1.R0.S09: RdPtrOffsetTxDq: 06
N4.C2.D1.R0.S07: wrcmd2dqsstartlatency: 04
N6.C2.D0.R1.S02: Total Delay in PI ticks: TxDQ = 944
N0.C2.D0.R1.S11: RdPtrOffsetTxDq: 07
N2.C3.D1.R0.S09: RdPtrOffsetTxDqs: 07
N4.C2.D1.R0.S07: RdPtrOffsetTxDq: 05
N6.C2.D0.R1.S03: Total Delay in PI ticks: TxDQ = 924
N0.C2.D0.R1.S12: RdPtrOffsetTxDq: 07
N2.C3.D1.R0.S09: PiTxDqs: 59
N4.C2.D1.R0.S07: RdPtrOffsetTxDqs: 07
N6.C2.D0.R1.S04: Total Delay in PI ticks: TxDQ = 888
N0.C2.D0.R1.S13: RdPtrOffsetTxDq: 06
N2.C3.D1.R0.S10: wrcmd2dqsstartlatency: 04
N4.C2.D1.R0.S07: PiTxDqs: 21
N6.C2.D0.R1.S05: Total Delay in PI ticks: TxDQ = 915
N0.C2.D0.R1.S14: RdPtrOffsetTxDq: 07
N2.C3.D1.R0.S10: RdPtrOffsetTxDq: 06
N4.C2.D1.R0.S08: wrcmd2dqsstartlatency: 04
N6.C2.D0.R1.S06: Total Delay in PI ticks: TxDQ = 915
N0.C2.D0.R1.S15: RdPtrOffsetTxDq: 07
N2.C3.D1.R0.S10: RdPtrOffsetTxDqs: 07
N4.C2.D1.R0.S08: RdPtrOffsetTxDq: 05
N6.C2.D0.R1.S07: Total Delay in PI ticks: TxDQ = 935
N0.C2.D0.R1.S16: RdPtrOffsetTxDq: 07
N2.C3.D1.R0.S10: PiTxDqs: 44
N4.C2.D1.R0.S08: RdPtrOffsetTxDqs: 06
N6.C2.D0.R1.S08: Total Delay in PI ticks: TxDQ = 904
N0.C2.D0.R1.S17: RdPtrOffsetTxDq: 07
N2.C3.D1.R0.S11: wrcmd2dqsstartlatency: 04
N4.C2.D1.R0.S08: PiTxDqs: 53
N6.C2.D0.R1.S09: Total Delay in PI ticks: TxDQ = 966
N0.C2.D0.R1.S00: Total Delay in PI ticks: TxDQ = 974
N2.C3.D1.R0.S11: RdPtrOffsetTxDq: 05
N4.C2.D1.R0.S09: wrcmd2dqsstartlatency: 04
N6.C2.D0.R1.S10: Total Delay in PI ticks: TxDQ = 955
N0.C2.D0.R1.S01: Total Delay in PI ticks: TxDQ = 960
N2.C3.D1.R0.S11: RdPtrOffsetTxDqs: 07
N4.C2.D1.R0.S09: RdPtrOffsetTxDq: 06
N6.C2.D0.R1.S11: Total Delay in PI ticks: TxDQ = 946
N0.C2.D0.R1.S02: Total Delay in PI ticks: TxDQ = 950
N2.C3.D1.R0.S11: PiTxDqs: 34
N4.C2.D1.R0.S09: RdPtrOffsetTxDqs: 07
N6.C2.D0.R1.S12: Total Delay in PI ticks: TxDQ = 927
N0.C2.D0.R1.S03: Total Delay in PI ticks: TxDQ = 932
N2.C3.D1.R0.S12: wrcmd2dqsstartlatency: 04
N4.C2.D1.R0.S09: PiTxDqs: 56
N6.C2.D0.R1.S13: Total Delay in PI ticks: TxDQ = 887
N0.C2.D0.R1.S04: Total Delay in PI ticks: TxDQ = 894
N2.C3.D1.R0.S12: RdPtrOffsetTxDq: 05
N4.C2.D1.R0.S10: wrcmd2dqsstartlatency: 04
N6.C2.D0.R1.S14: Total Delay in PI ticks: TxDQ = 916
N0.C2.D0.R1.S05: Total Delay in PI ticks: TxDQ = 921
N2.C3.D1.R0.S12: RdPtrOffsetTxDqs: 07
N4.C2.D1.R0.S10: RdPtrOffsetTxDq: 06
N6.C2.D0.R1.S15: Total Delay in PI ticks: TxDQ = 916
N0.C2.D0.R1.S06: Total Delay in PI ticks: TxDQ = 920
N2.C3.D1.R0.S12: PiTxDqs: 20
N4.C2.D1.R0.S10: RdPtrOffsetTxDqs: 07
N6.C2.D0.R1.S16: Total Delay in PI ticks: TxDQ = 935
N0.C2.D0.R1.S07: Total Delay in PI ticks: TxDQ = 939
N2.C3.D1.R0.S13: wrcmd2dqsstartlatency: 04
N4.C2.D1.R0.S10: PiTxDqs: 41
N6.C2.D0.R1.S17: Total Delay in PI ticks: TxDQ = 904
N0.C2.D0.R1.S08: Total Delay in PI ticks: TxDQ = 910
N2.C3.D1.R0.S13: RdPtrOffsetTxDq: 05
N4.C2.D1.R0.S11: wrcmd2dqsstartlatency: 04
N6.C2.D1.R0.S00: wrcmd2dqsstartlatency: 04
N0.C2.D0.R1.S09: Total Delay in PI ticks: TxDQ = 975
N2.C3.D1.R0.S13: RdPtrOffsetTxDqs: 06
N4.C2.D1.R0.S11: RdPtrOffsetTxDq: 05
N6.C2.D1.R0.S00: RdPtrOffsetTxDq: 06
N0.C2.D0.R1.S10: Total Delay in PI ticks: TxDQ = 957
N2.C3.D1.R0.S13: PiTxDqs: 49
N4.C2.D1.R0.S11: RdPtrOffsetTxDqs: 07
N6.C2.D1.R0.S00: RdPtrOffsetTxDqs: 07
N0.C2.D0.R1.S11: Total Delay in PI ticks: TxDQ = 951
N2.C3.D1.R0.S14: wrcmd2dqsstartlatency: 04
N4.C2.D1.R0.S11: PiTxDqs: 32
N6.C2.D1.R0.S00: PiTxDqs: 55
N0.C2.D0.R1.S12: Total Delay in PI ticks: TxDQ = 932
N2.C3.D1.R0.S14: RdPtrOffsetTxDq: 05
N4.C2.D1.R0.S12: wrcmd2dqsstartlatency: 04
N6.C2.D1.R0.S01: wrcmd2dqsstartlatency: 04
N0.C2.D0.R1.S13: Total Delay in PI ticks: TxDQ = 893
N2.C3.D1.R0.S14: RdPtrOffsetTxDqs: 06
N4.C2.D1.R0.S12: RdPtrOffsetTxDq: 05
N6.C2.D1.R0.S01: RdPtrOffsetTxDq: 06
N0.C2.D0.R1.S14: Total Delay in PI ticks: TxDQ = 923
N2.C3.D1.R0.S14: PiTxDqs: 59
N4.C2.D1.R0.S12: RdPtrOffsetTxDqs: 07
N6.C2.D1.R0.S01: RdPtrOffsetTxDqs: 07
N0.C2.D0.R1.S15: Total Delay in PI ticks: TxDQ = 918
N2.C3.D1.R0.S15: wrcmd2dqsstartlatency: 04
N4.C2.D1.R0.S12: PiTxDqs: 16
N6.C2.D1.R0.S01: PiTxDqs: 40
N0.C2.D0.R1.S16: Total Delay in PI ticks: TxDQ = 940
N2.C3.D1.R0.S15: RdPtrOffsetTxDq: 05
N4.C2.D1.R0.S13: wrcmd2dqsstartlatency: 04
N6.C2.D1.R0.S02: wrcmd2dqsstartlatency: 04
N0.C2.D0.R1.S17: Total Delay in PI ticks: TxDQ = 907
N2.C3.D1.R0.S15: RdPtrOffsetTxDqs: 07
N4.C2.D1.R0.S13: RdPtrOffsetTxDq: 05
N6.C2.D1.R0.S02: RdPtrOffsetTxDq: 05
N0.C2.D1.R0.S00: wrcmd2dqsstartlatency: 04
N2.C3.D1.R0.S15: PiTxDqs: 10
N4.C2.D1.R0.S13: RdPtrOffsetTxDqs: 06
N6.C2.D1.R0.S02: RdPtrOffsetTxDqs: 07
N0.C2.D1.R0.S00: RdPtrOffsetTxDq: 06
N2.C3.D1.R0.S16: wrcmd2dqsstartlatency: 04
N4.C2.D1.R0.S13: PiTxDqs: 38
N6.C2.D1.R0.S02: PiTxDqs: 33
N0.C2.D1.R0.S00: RdPtrOffsetTxDqs: 07
N2.C3.D1.R0.S16: RdPtrOffsetTxDq: 05
N4.C2.D1.R0.S14: wrcmd2dqsstartlatency: 04
N6.C2.D1.R0.S03: wrcmd2dqsstartlatency: 04
N0.C2.D1.R0.S00: PiTxDqs: 55
N2.C3.D1.R0.S16: RdPtrOffsetTxDqs: 07
N4.C2.D1.R0.S14: RdPtrOffsetTxDq: 05
N6.C2.D1.R0.S03: RdPtrOffsetTxDq: 05
N0.C2.D1.R0.S01: wrcmd2dqsstartlatency: 04
N2.C3.D1.R0.S16: PiTxDqs: 27
N4.C2.D1.R0.S14: RdPtrOffsetTxDqs: 07
N6.C2.D1.R0.S03: RdPtrOffsetTxDqs: 07
N0.C2.D1.R0.S01: RdPtrOffsetTxDq: 06
N2.C3.D1.R0.S17: wrcmd2dqsstartlatency: 04
N4.C2.D1.R0.S14: PiTxDqs: 00
N6.C2.D1.R0.S03: PiTxDqs: 16
N0.C2.D1.R0.S01: RdPtrOffsetTxDqs: 07
N2.C3.D1.R0.S17: RdPtrOffsetTxDq: 05
N4.C2.D1.R0.S15: wrcmd2dqsstartlatency: 04
N6.C2.D1.R0.S04: wrcmd2dqsstartlatency: 04
N0.C2.D1.R0.S01: PiTxDqs: 40
N2.C3.D1.R0.S17: RdPtrOffsetTxDqs: 07
N4.C2.D1.R0.S15: RdPtrOffsetTxDq: 05
N6.C2.D1.R0.S04: RdPtrOffsetTxDq: 05
N0.C2.D1.R0.S02: wrcmd2dqsstartlatency: 04
N2.C3.D1.R0.S17: PiTxDqs: 00
N4.C2.D1.R0.S15: RdPtrOffsetTxDqs: 07
N6.C2.D1.R0.S04: RdPtrOffsetTxDqs: 06
N0.C2.D1.R0.S02: RdPtrOffsetTxDq: 05
N2.C3.D1.R0.S00: RdPtrOffsetTxDq: 07
N4.C2.D1.R0.S15: PiTxDqs: 01
N6.C2.D1.R0.S04: PiTxDqs: 38
N0.C2.D1.R0.S02: RdPtrOffsetTxDqs: 07
N2.C3.D1.R0.S01: RdPtrOffsetTxDq: 07
N4.C2.D1.R0.S16: wrcmd2dqsstartlatency: 04
N6.C2.D1.R0.S05: wrcmd2dqsstartlatency: 04
N0.C2.D1.R0.S02: PiTxDqs: 33
N2.C3.D1.R0.S02: RdPtrOffsetTxDq: 06
N4.C2.D1.R0.S16: RdPtrOffsetTxDq: 05
N6.C2.D1.R0.S05: RdPtrOffsetTxDq: 05
N0.C2.D1.R0.S03: wrcmd2dqsstartlatency: 04
N2.C3.D1.R0.S03: RdPtrOffsetTxDq: 06
N4.C2.D1.R0.S16: RdPtrOffsetTxDqs: 07
N6.C2.D1.R0.S05: RdPtrOffsetTxDqs: 07
N0.C2.D1.R0.S03: RdPtrOffsetTxDq: 05
N2.C3.D1.R0.S04: RdPtrOffsetTxDq: 06
N4.C2.D1.R0.S16: PiTxDqs: 21
N6.C2.D1.R0.S05: PiTxDqs: 03
N0.C2.D1.R0.S03: RdPtrOffsetTxDqs: 07
N2.C3.D1.R0.S05: RdPtrOffsetTxDq: 06
N4.C2.D1.R0.S17: wrcmd2dqsstartlatency: 04
N6.C2.D1.R0.S06: wrcmd2dqsstartlatency: 04
N0.C2.D1.R0.S03: PiTxDqs: 17
N2.C3.D1.R0.S06: RdPtrOffsetTxDq: 06
N4.C2.D1.R0.S17: RdPtrOffsetTxDq: 05
N6.C2.D1.R0.S06: RdPtrOffsetTxDq: 05
N0.C2.D1.R0.S04: wrcmd2dqsstartlatency: 04
N2.C3.D1.R0.S07: RdPtrOffsetTxDq: 06
N4.C2.D1.R0.S17: RdPtrOffsetTxDqs: 06
N6.C2.D1.R0.S06: RdPtrOffsetTxDqs: 07
N0.C2.D1.R0.S04: RdPtrOffsetTxDq: 05
N2.C3.D1.R0.S08: RdPtrOffsetTxDq: 06
N4.C2.D1.R0.S17: PiTxDqs: 53
N6.C2.D1.R0.S06: PiTxDqs: 00
N0.C2.D1.R0.S04: RdPtrOffsetTxDqs: 06
N2.C3.D1.R0.S09: RdPtrOffsetTxDq: 07
N4.C2.D1.R0.S00: RdPtrOffsetTxDq: 07
N6.C2.D1.R0.S07: wrcmd2dqsstartlatency: 04
N0.C2.D1.R0.S04: PiTxDqs: 38
N2.C3.D1.R0.S10: RdPtrOffsetTxDq: 07
N4.C2.D1.R0.S01: RdPtrOffsetTxDq: 07
N6.C2.D1.R0.S07: RdPtrOffsetTxDq: 05
N0.C2.D1.R0.S05: wrcmd2dqsstartlatency: 04
N2.C3.D1.R0.S11: RdPtrOffsetTxDq: 06
N4.C2.D1.R0.S02: RdPtrOffsetTxDq: 06
N6.C2.D1.R0.S07: RdPtrOffsetTxDqs: 07
N0.C2.D1.R0.S05: RdPtrOffsetTxDq: 05
N2.C3.D1.R0.S12: RdPtrOffsetTxDq: 06
N4.C2.D1.R0.S03: RdPtrOffsetTxDq: 06
N6.C2.D1.R0.S07: PiTxDqs: 25
N0.C2.D1.R0.S05: RdPtrOffsetTxDqs: 07
N2.C3.D1.R0.S13: RdPtrOffsetTxDq: 06
N4.C2.D1.R0.S04: RdPtrOffsetTxDq: 06
N6.C2.D1.R0.S08: wrcmd2dqsstartlatency: 04
N0.C2.D1.R0.S05: PiTxDqs: 04
N2.C3.D1.R0.S14: RdPtrOffsetTxDq: 06
N4.C2.D1.R0.S05: RdPtrOffsetTxDq: 06
N6.C2.D1.R0.S08: RdPtrOffsetTxDq: 05
N0.C2.D1.R0.S06: wrcmd2dqsstartlatency: 04
N2.C3.D1.R0.S15: RdPtrOffsetTxDq: 06
N4.C2.D1.R0.S06: RdPtrOffsetTxDq: 06
N6.C2.D1.R0.S08: RdPtrOffsetTxDqs: 06
N0.C2.D1.R0.S06: RdPtrOffsetTxDq: 05
N2.C3.D1.R0.S16: RdPtrOffsetTxDq: 06
N4.C2.D1.R0.S07: RdPtrOffsetTxDq: 06
N6.C2.D1.R0.S08: PiTxDqs: 52
N0.C2.D1.R0.S06: RdPtrOffsetTxDqs: 07
N2.C3.D1.R0.S17: RdPtrOffsetTxDq: 06
N4.C2.D1.R0.S08: RdPtrOffsetTxDq: 06
N6.C2.D1.R0.S09: wrcmd2dqsstartlatency: 04
N0.C2.D1.R0.S06: PiTxDqs: 00
N2.C3.D1.R0.S00: RdPtrOffsetTxDq: 08
N4.C2.D1.R0.S09: RdPtrOffsetTxDq: 07
N6.C2.D1.R0.S09: RdPtrOffsetTxDq: 06
N0.C2.D1.R0.S07: wrcmd2dqsstartlatency: 04
N2.C3.D1.R0.S01: RdPtrOffsetTxDq: 08
N4.C2.D1.R0.S10: RdPtrOffsetTxDq: 07
N6.C2.D1.R0.S09: RdPtrOffsetTxDqs: 07
N0.C2.D1.R0.S07: RdPtrOffsetTxDq: 05
N2.C3.D1.R0.S02: RdPtrOffsetTxDq: 07
N4.C2.D1.R0.S11: RdPtrOffsetTxDq: 06
N6.C2.D1.R0.S09: PiTxDqs: 55
N0.C2.D1.R0.S07: RdPtrOffsetTxDqs: 07
N2.C3.D1.R0.S03: RdPtrOffsetTxDq: 07
N4.C2.D1.R0.S12: RdPtrOffsetTxDq: 06
N6.C2.D1.R0.S10: wrcmd2dqsstartlatency: 04
N0.C2.D1.R0.S07: PiTxDqs: 22
N2.C3.D1.R0.S04: RdPtrOffsetTxDq: 07
N4.C2.D1.R0.S13: RdPtrOffsetTxDq: 06
N6.C2.D1.R0.S10: RdPtrOffsetTxDq: 06
N0.C2.D1.R0.S08: wrcmd2dqsstartlatency: 04
N2.C3.D1.R0.S05: RdPtrOffsetTxDq: 07
N4.C2.D1.R0.S14: RdPtrOffsetTxDq: 06
N6.C2.D1.R0.S10: RdPtrOffsetTxDqs: 07
N0.C2.D1.R0.S08: RdPtrOffsetTxDq: 05
N2.C3.D1.R0.S06: RdPtrOffsetTxDq: 07
N4.C2.D1.R0.S15: RdPtrOffsetTxDq: 06
N6.C2.D1.R0.S10: PiTxDqs: 41
N0.C2.D1.R0.S08: RdPtrOffsetTxDqs: 06
N2.C3.D1.R0.S07: RdPtrOffsetTxDq: 07
N4.C2.D1.R0.S16: RdPtrOffsetTxDq: 06
N6.C2.D1.R0.S11: wrcmd2dqsstartlatency: 04
N0.C2.D1.R0.S08: PiTxDqs: 55
N2.C3.D1.R0.S08: RdPtrOffsetTxDq: 07
N4.C2.D1.R0.S17: RdPtrOffsetTxDq: 06
N6.C2.D1.R0.S11: RdPtrOffsetTxDq: 06
N0.C2.D1.R0.S09: wrcmd2dqsstartlatency: 04
N2.C3.D1.R0.S09: RdPtrOffsetTxDq: 08
N4.C2.D1.R0.S00: RdPtrOffsetTxDq: 08
N6.C2.D1.R0.S11: RdPtrOffsetTxDqs: 07
N0.C2.D1.R0.S09: RdPtrOffsetTxDq: 06
N2.C3.D1.R0.S10: RdPtrOffsetTxDq: 08
N4.C2.D1.R0.S01: RdPtrOffsetTxDq: 08
N6.C2.D1.R0.S11: PiTxDqs: 33
N0.C2.D1.R0.S09: RdPtrOffsetTxDqs: 07
N2.C3.D1.R0.S11: RdPtrOffsetTxDq: 07
N4.C2.D1.R0.S02: RdPtrOffsetTxDq: 07
N6.C2.D1.R0.S12: wrcmd2dqsstartlatency: 04
N0.C2.D1.R0.S09: PiTxDqs: 53
N2.C3.D1.R0.S12: RdPtrOffsetTxDq: 07
N4.C2.D1.R0.S03: RdPtrOffsetTxDq: 07
N6.C2.D1.R0.S12: RdPtrOffsetTxDq: 05
N0.C2.D1.R0.S10: wrcmd2dqsstartlatency: 04
N2.C3.D1.R0.S13: RdPtrOffsetTxDq: 07
N4.C2.D1.R0.S04: RdPtrOffsetTxDq: 07
N6.C2.D1.R0.S12: RdPtrOffsetTxDqs: 07
N0.C2.D1.R0.S10: RdPtrOffsetTxDq: 06
N2.C3.D1.R0.S14: RdPtrOffsetTxDq: 07
N4.C2.D1.R0.S05: RdPtrOffsetTxDq: 07
N6.C2.D1.R0.S12: PiTxDqs: 16
N0.C2.D1.R0.S10: RdPtrOffsetTxDqs: 07
N2.C3.D1.R0.S15: RdPtrOffsetTxDq: 07
N4.C2.D1.R0.S06: RdPtrOffsetTxDq: 07
N6.C2.D1.R0.S13: wrcmd2dqsstartlatency: 04
N0.C2.D1.R0.S10: PiTxDqs: 43
N2.C3.D1.R0.S16: RdPtrOffsetTxDq: 07
N4.C2.D1.R0.S07: RdPtrOffsetTxDq: 07
N6.C2.D1.R0.S13: RdPtrOffsetTxDq: 05
N0.C2.D1.R0.S11: wrcmd2dqsstartlatency: 04
N2.C3.D1.R0.S17: RdPtrOffsetTxDq: 07
N4.C2.D1.R0.S08: RdPtrOffsetTxDq: 07
N6.C2.D1.R0.S13: RdPtrOffsetTxDqs: 06
N0.C2.D1.R0.S11: RdPtrOffsetTxDq: 05
N2.C3.D1.R0.S00: Total Delay in PI ticks: TxDQ = 987
N4.C2.D1.R0.S09: RdPtrOffsetTxDq: 08
N6.C2.D1.R0.S13: PiTxDqs: 38
N0.C2.D1.R0.S11: RdPtrOffsetTxDqs: 07
N2.C3.D1.R0.S01: Total Delay in PI ticks: TxDQ = 972
N4.C2.D1.R0.S10: RdPtrOffsetTxDq: 08
N6.C2.D1.R0.S14: wrcmd2dqsstartlatency: 04
N0.C2.D1.R0.S11: PiTxDqs: 32
N2.C3.D1.R0.S02: Total Delay in PI ticks: TxDQ = 963
N4.C2.D1.R0.S11: RdPtrOffsetTxDq: 07
N6.C2.D1.R0.S14: RdPtrOffsetTxDq: 05
N0.C2.D1.R0.S12: wrcmd2dqsstartlatency: 04
N2.C3.D1.R0.S03: Total Delay in PI ticks: TxDQ = 944
N4.C2.D1.R0.S12: RdPtrOffsetTxDq: 07
N6.C2.D1.R0.S14: RdPtrOffsetTxDqs: 07
N0.C2.D1.R0.S12: RdPtrOffsetTxDq: 05
N2.C3.D1.R0.S04: Total Delay in PI ticks: TxDQ = 910
N4.C2.D1.R0.S13: RdPtrOffsetTxDq: 07
N6.C2.D1.R0.S14: PiTxDqs: 03
N0.C2.D1.R0.S12: RdPtrOffsetTxDqs: 07
N2.C3.D1.R0.S05: Total Delay in PI ticks: TxDQ = 925
N4.C2.D1.R0.S14: RdPtrOffsetTxDq: 07
N6.C2.D1.R0.S15: wrcmd2dqsstartlatency: 04
N0.C2.D1.R0.S12: PiTxDqs: 14
N2.C3.D1.R0.S06: Total Delay in PI ticks: TxDQ = 937
N4.C2.D1.R0.S15: RdPtrOffsetTxDq: 07
N6.C2.D1.R0.S15: RdPtrOffsetTxDq: 05
N0.C2.D1.R0.S13: wrcmd2dqsstartlatency: 04
N2.C3.D1.R0.S07: Total Delay in PI ticks: TxDQ = 955
N4.C2.D1.R0.S16: RdPtrOffsetTxDq: 07
N6.C2.D1.R0.S15: RdPtrOffsetTxDqs: 07
N0.C2.D1.R0.S13: RdPtrOffsetTxDq: 05
N2.C3.D1.R0.S08: Total Delay in PI ticks: TxDQ = 927
N4.C2.D1.R0.S17: RdPtrOffsetTxDq: 07
N6.C2.D1.R0.S15: PiTxDqs: 00
N0.C2.D1.R0.S13: RdPtrOffsetTxDqs: 06
N2.C3.D1.R0.S09: Total Delay in PI ticks: TxDQ = 984
N4.C2.D1.R0.S00: Total Delay in PI ticks: TxDQ = 980
N6.C2.D1.R0.S16: wrcmd2dqsstartlatency: 04
N0.C2.D1.R0.S13: PiTxDqs: 39
N2.C3.D1.R0.S10: Total Delay in PI ticks: TxDQ = 971
N4.C2.D1.R0.S01: Total Delay in PI ticks: TxDQ = 967
N6.C2.D1.R0.S16: RdPtrOffsetTxDq: 05
N0.C2.D1.R0.S14: wrcmd2dqsstartlatency: 04
N2.C3.D1.R0.S11: Total Delay in PI ticks: TxDQ = 962
N4.C2.D1.R0.S02: Total Delay in PI ticks: TxDQ = 956
N6.C2.D1.R0.S16: RdPtrOffsetTxDqs: 07
N0.C2.D1.R0.S14: RdPtrOffsetTxDq: 05
N2.C3.D1.R0.S12: Total Delay in PI ticks: TxDQ = 946
N4.C2.D1.R0.S03: Total Delay in PI ticks: TxDQ = 939
N6.C2.D1.R0.S16: PiTxDqs: 23
N0.C2.D1.R0.S14: RdPtrOffsetTxDqs: 07
N2.C3.D1.R0.S13: Total Delay in PI ticks: TxDQ = 911
N4.C2.D1.R0.S04: Total Delay in PI ticks: TxDQ = 902
N6.C2.D1.R0.S17: wrcmd2dqsstartlatency: 04
N0.C2.D1.R0.S14: PiTxDqs: 01
N2.C3.D1.R0.S14: Total Delay in PI ticks: TxDQ = 924
N4.C2.D1.R0.S05: Total Delay in PI ticks: TxDQ = 928
N6.C2.D1.R0.S17: RdPtrOffsetTxDq: 05
N0.C2.D1.R0.S15: wrcmd2dqsstartlatency: 04
N2.C3.D1.R0.S15: Total Delay in PI ticks: TxDQ = 938
N4.C2.D1.R0.S06: Total Delay in PI ticks: TxDQ = 927
N6.C2.D1.R0.S17: RdPtrOffsetTxDqs: 06
N0.C2.D1.R0.S15: RdPtrOffsetTxDq: 05
N2.C3.D1.R0.S16: Total Delay in PI ticks: TxDQ = 954
N4.C2.D1.R0.S07: Total Delay in PI ticks: TxDQ = 945
N6.C2.D1.R0.S17: PiTxDqs: 55
N0.C2.D1.R0.S15: RdPtrOffsetTxDqs: 07
N2.C3.D1.R0.S17: Total Delay in PI ticks: TxDQ = 926
N4.C2.D1.R0.S08: Total Delay in PI ticks: TxDQ = 913
N6.C2.D1.R0.S00: RdPtrOffsetTxDq: 07
N0.C2.D1.R0.S15: PiTxDqs: 03
N2.C3.D1.R1.S00: wrcmd2dqsstartlatency: 04
N4.C2.D1.R0.S09: Total Delay in PI ticks: TxDQ = 981
N6.C2.D1.R0.S01: RdPtrOffsetTxDq: 07
N0.C2.D1.R0.S16: wrcmd2dqsstartlatency: 04
N2.C3.D1.R1.S00: RdPtrOffsetTxDq: 06
N4.C2.D1.R0.S10: Total Delay in PI ticks: TxDQ = 964
N6.C2.D1.R0.S02: RdPtrOffsetTxDq: 06
N0.C2.D1.R0.S16: RdPtrOffsetTxDq: 05
N2.C3.D1.R1.S00: RdPtrOffsetTxDqs: 07
N4.C2.D1.R0.S11: Total Delay in PI ticks: TxDQ = 958
N6.C2.D1.R0.S03: RdPtrOffsetTxDq: 06
N0.C2.D1.R0.S16: RdPtrOffsetTxDqs: 07
N2.C3.D1.R1.S00: PiTxDqs: 58
N4.C2.D1.R0.S12: Total Delay in PI ticks: TxDQ = 942
N6.C2.D1.R0.S04: RdPtrOffsetTxDq: 06
N0.C2.D1.R0.S16: PiTxDqs: 22
N2.C3.D1.R1.S01: wrcmd2dqsstartlatency: 04
N4.C2.D1.R0.S13: Total Delay in PI ticks: TxDQ = 900
N6.C2.D1.R0.S05: RdPtrOffsetTxDq: 06
N0.C2.D1.R0.S17: wrcmd2dqsstartlatency: 04
N2.C3.D1.R1.S01: RdPtrOffsetTxDq: 06
N4.C2.D1.R0.S14: Total Delay in PI ticks: TxDQ = 927
N6.C2.D1.R0.S06: RdPtrOffsetTxDq: 06
N0.C2.D1.R0.S17: RdPtrOffsetTxDq: 05
N2.C3.D1.R1.S01: RdPtrOffsetTxDqs: 07
N4.C2.D1.R0.S15: Total Delay in PI ticks: TxDQ = 927
N6.C2.D1.R0.S07: RdPtrOffsetTxDq: 06
N0.C2.D1.R0.S17: RdPtrOffsetTxDqs: 06
N2.C3.D1.R1.S01: PiTxDqs: 39
N4.C2.D1.R0.S16: Total Delay in PI ticks: TxDQ = 945
N6.C2.D1.R0.S08: RdPtrOffsetTxDq: 06
N0.C2.D1.R0.S17: PiTxDqs: 55
N2.C3.D1.R1.S02: wrcmd2dqsstartlatency: 04
N4.C2.D1.R0.S17: Total Delay in PI ticks: TxDQ = 914
N6.C2.D1.R0.S09: RdPtrOffsetTxDq: 07
N0.C2.D1.R0.S00: RdPtrOffsetTxDq: 07
N2.C3.D1.R1.S02: RdPtrOffsetTxDq: 05
N4.C2.D1.R1.S00: wrcmd2dqsstartlatency: 04
N6.C2.D1.R0.S10: RdPtrOffsetTxDq: 07
N0.C2.D1.R0.S01: RdPtrOffsetTxDq: 07
N2.C3.D1.R1.S02: RdPtrOffsetTxDqs: 07
N4.C2.D1.R1.S00: RdPtrOffsetTxDq: 06
N6.C2.D1.R0.S11: RdPtrOffsetTxDq: 07
N0.C2.D1.R0.S02: RdPtrOffsetTxDq: 06
N2.C3.D1.R1.S02: PiTxDqs: 30
N4.C2.D1.R1.S00: RdPtrOffsetTxDqs: 07
N6.C2.D1.R0.S12: RdPtrOffsetTxDq: 06
N0.C2.D1.R0.S03: RdPtrOffsetTxDq: 06
N2.C3.D1.R1.S03: wrcmd2dqsstartlatency: 04
N4.C2.D1.R1.S00: PiTxDqs: 51
N6.C2.D1.R0.S13: RdPtrOffsetTxDq: 06
N0.C2.D1.R0.S04: RdPtrOffsetTxDq: 06
N2.C3.D1.R1.S03: RdPtrOffsetTxDq: 05
N4.C2.D1.R1.S01: wrcmd2dqsstartlatency: 04
N6.C2.D1.R0.S14: RdPtrOffsetTxDq: 06
N0.C2.D1.R0.S05: RdPtrOffsetTxDq: 06
N2.C3.D1.R1.S03: RdPtrOffsetTxDqs: 07
N4.C2.D1.R1.S01: RdPtrOffsetTxDq: 05
N6.C2.D1.R0.S15: RdPtrOffsetTxDq: 06
N0.C2.D1.R0.S06: RdPtrOffsetTxDq: 06
N2.C3.D1.R1.S03: PiTxDqs: 15
N4.C2.D1.R1.S01: RdPtrOffsetTxDqs: 07
N6.C2.D1.R0.S16: RdPtrOffsetTxDq: 06
N0.C2.D1.R0.S07: RdPtrOffsetTxDq: 06
N2.C3.D1.R1.S04: wrcmd2dqsstartlatency: 04
N4.C2.D1.R1.S01: PiTxDqs: 38
N6.C2.D1.R0.S17: RdPtrOffsetTxDq: 06
N0.C2.D1.R0.S08: RdPtrOffsetTxDq: 06
N2.C3.D1.R1.S04: RdPtrOffsetTxDq: 05
N4.C2.D1.R1.S02: wrcmd2dqsstartlatency: 04
N6.C2.D1.R0.S00: RdPtrOffsetTxDq: 08
N0.C2.D1.R0.S09: RdPtrOffsetTxDq: 07
N2.C3.D1.R1.S04: RdPtrOffsetTxDqs: 06
N4.C2.D1.R1.S02: RdPtrOffsetTxDq: 05
N6.C2.D1.R0.S01: RdPtrOffsetTxDq: 08
N0.C2.D1.R0.S10: RdPtrOffsetTxDq: 07
N2.C3.D1.R1.S04: PiTxDqs: 44
N4.C2.D1.R1.S02: RdPtrOffsetTxDqs: 07
N6.C2.D1.R0.S02: RdPtrOffsetTxDq: 07
N0.C2.D1.R0.S11: RdPtrOffsetTxDq: 06
N2.C3.D1.R1.S05: wrcmd2dqsstartlatency: 04
N4.C2.D1.R1.S02: PiTxDqs: 27
N6.C2.D1.R0.S03: RdPtrOffsetTxDq: 07
N0.C2.D1.R0.S12: RdPtrOffsetTxDq: 06
N2.C3.D1.R1.S05: RdPtrOffsetTxDq: 05
N4.C2.D1.R1.S03: wrcmd2dqsstartlatency: 04
N6.C2.D1.R0.S04: RdPtrOffsetTxDq: 07
N0.C2.D1.R0.S13: RdPtrOffsetTxDq: 06
N2.C3.D1.R1.S05: RdPtrOffsetTxDqs: 06
N4.C2.D1.R1.S03: RdPtrOffsetTxDq: 05
N6.C2.D1.R0.S05: RdPtrOffsetTxDq: 07
N0.C2.D1.R0.S14: RdPtrOffsetTxDq: 06
N2.C3.D1.R1.S05: PiTxDqs: 57
N4.C2.D1.R1.S03: RdPtrOffsetTxDqs: 07
N6.C2.D1.R0.S06: RdPtrOffsetTxDq: 07
N0.C2.D1.R0.S15: RdPtrOffsetTxDq: 06
N2.C3.D1.R1.S06: wrcmd2dqsstartlatency: 04
N4.C2.D1.R1.S03: PiTxDqs: 13
N6.C2.D1.R0.S07: RdPtrOffsetTxDq: 07
N0.C2.D1.R0.S16: RdPtrOffsetTxDq: 06
N2.C3.D1.R1.S06: RdPtrOffsetTxDq: 05
N4.C2.D1.R1.S04: wrcmd2dqsstartlatency: 04
N6.C2.D1.R0.S08: RdPtrOffsetTxDq: 07
N0.C2.D1.R0.S17: RdPtrOffsetTxDq: 06
N2.C3.D1.R1.S06: RdPtrOffsetTxDqs: 07
N4.C2.D1.R1.S04: RdPtrOffsetTxDq: 04
N6.C2.D1.R0.S09: RdPtrOffsetTxDq: 08
N0.C2.D1.R0.S00: RdPtrOffsetTxDq: 08
N2.C3.D1.R1.S06: PiTxDqs: 07
N4.C2.D1.R1.S04: RdPtrOffsetTxDqs: 06
N6.C2.D1.R0.S10: RdPtrOffsetTxDq: 08
N0.C2.D1.R0.S01: RdPtrOffsetTxDq: 08
N2.C3.D1.R1.S07: wrcmd2dqsstartlatency: 04
N4.C2.D1.R1.S04: PiTxDqs: 34
N6.C2.D1.R0.S11: RdPtrOffsetTxDq: 08
N0.C2.D1.R0.S02: RdPtrOffsetTxDq: 07
N2.C3.D1.R1.S07: RdPtrOffsetTxDq: 05
N4.C2.D1.R1.S05: wrcmd2dqsstartlatency: 04
N6.C2.D1.R0.S12: RdPtrOffsetTxDq: 07
N0.C2.D1.R0.S03: RdPtrOffsetTxDq: 07
N2.C3.D1.R1.S07: RdPtrOffsetTxDqs: 07
N4.C2.D1.R1.S05: RdPtrOffsetTxDq: 05
N6.C2.D1.R0.S13: RdPtrOffsetTxDq: 07
N0.C2.D1.R0.S04: RdPtrOffsetTxDq: 07
N2.C3.D1.R1.S07: PiTxDqs: 25
N4.C2.D1.R1.S05: RdPtrOffsetTxDqs: 06
N6.C2.D1.R0.S14: RdPtrOffsetTxDq: 07
N0.C2.D1.R0.S05: RdPtrOffsetTxDq: 07
N2.C3.D1.R1.S08: wrcmd2dqsstartlatency: 04
N4.C2.D1.R1.S05: PiTxDqs: 63
N6.C2.D1.R0.S15: RdPtrOffsetTxDq: 07
N0.C2.D1.R0.S06: RdPtrOffsetTxDq: 07
N2.C3.D1.R1.S08: RdPtrOffsetTxDq: 05
N4.C2.D1.R1.S06: wrcmd2dqsstartlatency: 04
N6.C2.D1.R0.S16: RdPtrOffsetTxDq: 07
N0.C2.D1.R0.S07: RdPtrOffsetTxDq: 07
N2.C3.D1.R1.S08: RdPtrOffsetTxDqs: 06
N4.C2.D1.R1.S06: RdPtrOffsetTxDq: 05
N6.C2.D1.R0.S17: RdPtrOffsetTxDq: 07
N0.C2.D1.R0.S08: RdPtrOffsetTxDq: 07
N2.C3.D1.R1.S08: PiTxDqs: 59
N4.C2.D1.R1.S06: RdPtrOffsetTxDqs: 06
N6.C2.D1.R0.S00: Total Delay in PI ticks: TxDQ = 983
N0.C2.D1.R0.S09: RdPtrOffsetTxDq: 08
N2.C3.D1.R1.S09: wrcmd2dqsstartlatency: 04
N4.C2.D1.R1.S06: PiTxDqs: 58
N6.C2.D1.R0.S01: Total Delay in PI ticks: TxDQ = 966
N0.C2.D1.R0.S10: RdPtrOffsetTxDq: 08
N2.C3.D1.R1.S09: RdPtrOffsetTxDq: 06
N4.C2.D1.R1.S07: wrcmd2dqsstartlatency: 04
N6.C2.D1.R0.S02: Total Delay in PI ticks: TxDQ = 962
N0.C2.D1.R0.S11: RdPtrOffsetTxDq: 07
N2.C3.D1.R1.S09: RdPtrOffsetTxDqs: 07
N4.C2.D1.R1.S07: RdPtrOffsetTxDq: 05
N6.C2.D1.R0.S03: Total Delay in PI ticks: TxDQ = 942
N0.C2.D1.R0.S12: RdPtrOffsetTxDq: 07
N2.C3.D1.R1.S09: PiTxDqs: 57
N4.C2.D1.R1.S07: RdPtrOffsetTxDqs: 07
N6.C2.D1.R0.S04: Total Delay in PI ticks: TxDQ = 902
N0.C2.D1.R0.S13: RdPtrOffsetTxDq: 07
N2.C3.D1.R1.S10: wrcmd2dqsstartlatency: 04
N4.C2.D1.R1.S07: PiTxDqs: 18
N6.C2.D1.R0.S05: Total Delay in PI ticks: TxDQ = 931
N0.C2.D1.R0.S14: RdPtrOffsetTxDq: 07
N2.C3.D1.R1.S10: RdPtrOffsetTxDq: 06
N4.C2.D1.R1.S08: wrcmd2dqsstartlatency: 04
N6.C2.D1.R0.S06: Total Delay in PI ticks: TxDQ = 929
N0.C2.D1.R0.S15: RdPtrOffsetTxDq: 07
N2.C3.D1.R1.S10: RdPtrOffsetTxDqs: 07
N4.C2.D1.R1.S08: RdPtrOffsetTxDq: 05
N6.C2.D1.R0.S07: Total Delay in PI ticks: TxDQ = 951
N0.C2.D1.R0.S16: RdPtrOffsetTxDq: 07
N2.C3.D1.R1.S10: PiTxDqs: 38
N4.C2.D1.R1.S08: RdPtrOffsetTxDqs: 06
N6.C2.D1.R0.S08: Total Delay in PI ticks: TxDQ = 916
N0.C2.D1.R0.S17: RdPtrOffsetTxDq: 07
N2.C3.D1.R1.S11: wrcmd2dqsstartlatency: 04
N4.C2.D1.R1.S08: PiTxDqs: 49
N6.C2.D1.R0.S09: Total Delay in PI ticks: TxDQ = 980
N0.C2.D1.R0.S00: Total Delay in PI ticks: TxDQ = 983
N2.C3.D1.R1.S11: RdPtrOffsetTxDq: 05
N4.C2.D1.R1.S09: wrcmd2dqsstartlatency: 04
N6.C2.D1.R0.S10: Total Delay in PI ticks: TxDQ = 967
N0.C2.D1.R0.S01: Total Delay in PI ticks: TxDQ = 965
N2.C3.D1.R1.S11: RdPtrOffsetTxDqs: 07
N4.C2.D1.R1.S09: RdPtrOffsetTxDq: 06
N6.C2.D1.R0.S11: Total Delay in PI ticks: TxDQ = 961
N0.C2.D1.R0.S02: Total Delay in PI ticks: TxDQ = 960
N2.C3.D1.R1.S11: PiTxDqs: 32
N4.C2.D1.R1.S09: RdPtrOffsetTxDqs: 07
N6.C2.D1.R0.S12: Total Delay in PI ticks: TxDQ = 941
N0.C2.D1.R0.S03: Total Delay in PI ticks: TxDQ = 943
N2.C3.D1.R1.S12: wrcmd2dqsstartlatency: 04
N4.C2.D1.R1.S09: PiTxDqs: 50
N6.C2.D1.R0.S13: Total Delay in PI ticks: TxDQ = 901
N0.C2.D1.R0.S04: Total Delay in PI ticks: TxDQ = 902
N2.C3.D1.R1.S12: RdPtrOffsetTxDq: 05
N4.C2.D1.R1.S10: wrcmd2dqsstartlatency: 04
N6.C2.D1.R0.S14: Total Delay in PI ticks: TxDQ = 929
N0.C2.D1.R0.S05: Total Delay in PI ticks: TxDQ = 930
N2.C3.D1.R1.S12: RdPtrOffsetTxDqs: 07
N4.C2.D1.R1.S10: RdPtrOffsetTxDq: 05
N6.C2.D1.R0.S15: Total Delay in PI ticks: TxDQ = 928
N0.C2.D1.R0.S06: Total Delay in PI ticks: TxDQ = 927
N2.C3.D1.R1.S12: PiTxDqs: 15
N4.C2.D1.R1.S10: RdPtrOffsetTxDqs: 07
N6.C2.D1.R0.S16: Total Delay in PI ticks: TxDQ = 949
N0.C2.D1.R0.S07: Total Delay in PI ticks: TxDQ = 947
N2.C3.D1.R1.S13: wrcmd2dqsstartlatency: 04
N4.C2.D1.R1.S10: PiTxDqs: 40
N6.C2.D1.R0.S17: Total Delay in PI ticks: TxDQ = 916
N0.C2.D1.R0.S08: Total Delay in PI ticks: TxDQ = 917
N2.C3.D1.R1.S13: RdPtrOffsetTxDq: 05
N4.C2.D1.R1.S11: wrcmd2dqsstartlatency: 04
N6.C2.D1.R1.S00: wrcmd2dqsstartlatency: 04
N0.C2.D1.R0.S09: Total Delay in PI ticks: TxDQ = 978
N2.C3.D1.R1.S13: RdPtrOffsetTxDqs: 06
N4.C2.D1.R1.S11: RdPtrOffsetTxDq: 05
N6.C2.D1.R1.S00: RdPtrOffsetTxDq: 06
N0.C2.D1.R0.S10: Total Delay in PI ticks: TxDQ = 966
N2.C3.D1.R1.S13: PiTxDqs: 43
N4.C2.D1.R1.S11: RdPtrOffsetTxDqs: 07
N6.C2.D1.R1.S00: RdPtrOffsetTxDqs: 07
N0.C2.D1.R0.S11: Total Delay in PI ticks: TxDQ = 958
N2.C3.D1.R1.S14: wrcmd2dqsstartlatency: 04
N4.C2.D1.R1.S11: PiTxDqs: 27
N6.C2.D1.R1.S00: PiTxDqs: 50
N0.C2.D1.R0.S12: Total Delay in PI ticks: TxDQ = 939
N2.C3.D1.R1.S14: RdPtrOffsetTxDq: 05
N4.C2.D1.R1.S12: wrcmd2dqsstartlatency: 04
N6.C2.D1.R1.S01: wrcmd2dqsstartlatency: 04
N0.C2.D1.R0.S13: Total Delay in PI ticks: TxDQ = 902
N2.C3.D1.R1.S14: RdPtrOffsetTxDqs: 06
N4.C2.D1.R1.S12: RdPtrOffsetTxDq: 05
N6.C2.D1.R1.S01: RdPtrOffsetTxDq: 05
N0.C2.D1.R0.S14: Total Delay in PI ticks: TxDQ = 929
N2.C3.D1.R1.S14: PiTxDqs: 56
N4.C2.D1.R1.S12: RdPtrOffsetTxDqs: 07
N6.C2.D1.R1.S01: RdPtrOffsetTxDqs: 07
N0.C2.D1.R0.S15: Total Delay in PI ticks: TxDQ = 929
N2.C3.D1.R1.S15: wrcmd2dqsstartlatency: 04
N4.C2.D1.R1.S12: PiTxDqs: 13
N6.C2.D1.R1.S01: PiTxDqs: 35
N0.C2.D1.R0.S16: Total Delay in PI ticks: TxDQ = 945
N2.C3.D1.R1.S15: RdPtrOffsetTxDq: 05
N4.C2.D1.R1.S13: wrcmd2dqsstartlatency: 04
N6.C2.D1.R1.S02: wrcmd2dqsstartlatency: 04
N0.C2.D1.R0.S17: Total Delay in PI ticks: TxDQ = 916
N2.C3.D1.R1.S15: RdPtrOffsetTxDqs: 07
N4.C2.D1.R1.S13: RdPtrOffsetTxDq: 04
N6.C2.D1.R1.S02: RdPtrOffsetTxDq: 05
N0.C2.D1.R1.S00: wrcmd2dqsstartlatency: 04
N2.C3.D1.R1.S15: PiTxDqs: 07
N4.C2.D1.R1.S13: RdPtrOffsetTxDqs: 06
N6.C2.D1.R1.S02: RdPtrOffsetTxDqs: 07
N0.C2.D1.R1.S00: RdPtrOffsetTxDq: 06
N2.C3.D1.R1.S16: wrcmd2dqsstartlatency: 04
N4.C2.D1.R1.S13: PiTxDqs: 34
N6.C2.D1.R1.S02: PiTxDqs: 27
N0.C2.D1.R1.S00: RdPtrOffsetTxDqs: 07
N2.C3.D1.R1.S16: RdPtrOffsetTxDq: 05
N4.C2.D1.R1.S14: wrcmd2dqsstartlatency: 04
N6.C2.D1.R1.S03: wrcmd2dqsstartlatency: 04
N0.C2.D1.R1.S00: PiTxDqs: 51
N2.C3.D1.R1.S16: RdPtrOffsetTxDqs: 07
N4.C2.D1.R1.S14: RdPtrOffsetTxDq: 05
N6.C2.D1.R1.S03: RdPtrOffsetTxDq: 05
N0.C2.D1.R1.S01: wrcmd2dqsstartlatency: 04
N2.C3.D1.R1.S16: PiTxDqs: 24
N4.C2.D1.R1.S14: RdPtrOffsetTxDqs: 06
N6.C2.D1.R1.S03: RdPtrOffsetTxDqs: 07
N0.C2.D1.R1.S01: RdPtrOffsetTxDq: 06
N2.C3.D1.R1.S17: wrcmd2dqsstartlatency: 04
N4.C2.D1.R1.S14: PiTxDqs: 63
N6.C2.D1.R1.S03: PiTxDqs: 10
N0.C2.D1.R1.S01: RdPtrOffsetTxDqs: 07
N2.C3.D1.R1.S17: RdPtrOffsetTxDq: 05
N4.C2.D1.R1.S15: wrcmd2dqsstartlatency: 04
N6.C2.D1.R1.S04: wrcmd2dqsstartlatency: 04
N0.C2.D1.R1.S01: PiTxDqs: 38
N2.C3.D1.R1.S17: RdPtrOffsetTxDqs: 06
N4.C2.D1.R1.S15: RdPtrOffsetTxDq: 05
N6.C2.D1.R1.S04: RdPtrOffsetTxDq: 04
N0.C2.D1.R1.S02: wrcmd2dqsstartlatency: 04
N2.C3.D1.R1.S17: PiTxDqs: 59
N4.C2.D1.R1.S15: RdPtrOffsetTxDqs: 06
N6.C2.D1.R1.S04: RdPtrOffsetTxDqs: 06
N0.C2.D1.R1.S02: RdPtrOffsetTxDq: 05
N2.C3.D1.R1.S00: RdPtrOffsetTxDq: 07
N4.C2.D1.R1.S15: PiTxDqs: 63
N6.C2.D1.R1.S04: PiTxDqs: 33
N0.C2.D1.R1.S02: RdPtrOffsetTxDqs: 07
N2.C3.D1.R1.S01: RdPtrOffsetTxDq: 07
N4.C2.D1.R1.S16: wrcmd2dqsstartlatency: 04
N6.C2.D1.R1.S05: wrcmd2dqsstartlatency: 04
N0.C2.D1.R1.S02: PiTxDqs: 28
N2.C3.D1.R1.S02: RdPtrOffsetTxDq: 06
N4.C2.D1.R1.S16: RdPtrOffsetTxDq: 05
N6.C2.D1.R1.S05: RdPtrOffsetTxDq: 05
N0.C2.D1.R1.S03: wrcmd2dqsstartlatency: 04
N2.C3.D1.R1.S03: RdPtrOffsetTxDq: 06
N4.C2.D1.R1.S16: RdPtrOffsetTxDqs: 07
N6.C2.D1.R1.S05: RdPtrOffsetTxDqs: 07
N0.C2.D1.R1.S03: RdPtrOffsetTxDq: 05
N2.C3.D1.R1.S04: RdPtrOffsetTxDq: 06
N4.C2.D1.R1.S16: PiTxDqs: 17
N6.C2.D1.R1.S05: PiTxDqs: 00
N0.C2.D1.R1.S03: RdPtrOffsetTxDqs: 07
N2.C3.D1.R1.S05: RdPtrOffsetTxDq: 06
N4.C2.D1.R1.S17: wrcmd2dqsstartlatency: 04
N6.C2.D1.R1.S06: wrcmd2dqsstartlatency: 04
N0.C2.D1.R1.S03: PiTxDqs: 12
N2.C3.D1.R1.S06: RdPtrOffsetTxDq: 06
N4.C2.D1.R1.S17: RdPtrOffsetTxDq: 05
N6.C2.D1.R1.S06: RdPtrOffsetTxDq: 05
N0.C2.D1.R1.S04: wrcmd2dqsstartlatency: 04
N2.C3.D1.R1.S07: RdPtrOffsetTxDq: 06
N4.C2.D1.R1.S17: RdPtrOffsetTxDqs: 06
N6.C2.D1.R1.S06: RdPtrOffsetTxDqs: 06
N0.C2.D1.R1.S04: RdPtrOffsetTxDq: 05
N2.C3.D1.R1.S08: RdPtrOffsetTxDq: 06
N4.C2.D1.R1.S17: PiTxDqs: 47
N6.C2.D1.R1.S06: PiTxDqs: 59
N0.C2.D1.R1.S04: RdPtrOffsetTxDqs: 06
N2.C3.D1.R1.S09: RdPtrOffsetTxDq: 07
N4.C2.D1.R1.S00: RdPtrOffsetTxDq: 07
N6.C2.D1.R1.S07: wrcmd2dqsstartlatency: 04
N0.C2.D1.R1.S04: PiTxDqs: 37
N2.C3.D1.R1.S10: RdPtrOffsetTxDq: 07
N4.C2.D1.R1.S01: RdPtrOffsetTxDq: 06
N6.C2.D1.R1.S07: RdPtrOffsetTxDq: 05
N0.C2.D1.R1.S05: wrcmd2dqsstartlatency: 04
N2.C3.D1.R1.S11: RdPtrOffsetTxDq: 06
N4.C2.D1.R1.S02: RdPtrOffsetTxDq: 06
N6.C2.D1.R1.S07: RdPtrOffsetTxDqs: 07
N0.C2.D1.R1.S05: RdPtrOffsetTxDq: 05
N2.C3.D1.R1.S12: RdPtrOffsetTxDq: 06
N4.C2.D1.R1.S03: RdPtrOffsetTxDq: 06
N6.C2.D1.R1.S07: PiTxDqs: 21
N0.C2.D1.R1.S05: RdPtrOffsetTxDqs: 07
N2.C3.D1.R1.S13: RdPtrOffsetTxDq: 06
N4.C2.D1.R1.S04: RdPtrOffsetTxDq: 05
N6.C2.D1.R1.S08: wrcmd2dqsstartlatency: 04
N0.C2.D1.R1.S05: PiTxDqs: 01
N2.C3.D1.R1.S14: RdPtrOffsetTxDq: 06
N4.C2.D1.R1.S05: RdPtrOffsetTxDq: 06
N6.C2.D1.R1.S08: RdPtrOffsetTxDq: 05
N0.C2.D1.R1.S06: wrcmd2dqsstartlatency: 04
N2.C3.D1.R1.S15: RdPtrOffsetTxDq: 06
N4.C2.D1.R1.S06: RdPtrOffsetTxDq: 06
N6.C2.D1.R1.S08: RdPtrOffsetTxDqs: 06
N0.C2.D1.R1.S06: RdPtrOffsetTxDq: 05
N2.C3.D1.R1.S16: RdPtrOffsetTxDq: 06
N4.C2.D1.R1.S07: RdPtrOffsetTxDq: 06
N6.C2.D1.R1.S08: PiTxDqs: 48
N0.C2.D1.R1.S06: RdPtrOffsetTxDqs: 06
N2.C3.D1.R1.S17: RdPtrOffsetTxDq: 06
N4.C2.D1.R1.S08: RdPtrOffsetTxDq: 06
N6.C2.D1.R1.S09: wrcmd2dqsstartlatency: 04
N0.C2.D1.R1.S06: PiTxDqs: 60
N2.C3.D1.R1.S00: RdPtrOffsetTxDq: 08
N4.C2.D1.R1.S09: RdPtrOffsetTxDq: 07
N6.C2.D1.R1.S09: RdPtrOffsetTxDq: 06
N0.C2.D1.R1.S07: wrcmd2dqsstartlatency: 04
N2.C3.D1.R1.S01: RdPtrOffsetTxDq: 08
N4.C2.D1.R1.S10: RdPtrOffsetTxDq: 06
N6.C2.D1.R1.S09: RdPtrOffsetTxDqs: 07
N0.C2.D1.R1.S07: RdPtrOffsetTxDq: 05
N2.C3.D1.R1.S02: RdPtrOffsetTxDq: 07
N4.C2.D1.R1.S11: RdPtrOffsetTxDq: 06
N6.C2.D1.R1.S09: PiTxDqs: 48
N0.C2.D1.R1.S07: RdPtrOffsetTxDqs: 07
N2.C3.D1.R1.S03: RdPtrOffsetTxDq: 07
N4.C2.D1.R1.S12: RdPtrOffsetTxDq: 06
N6.C2.D1.R1.S10: wrcmd2dqsstartlatency: 04
N0.C2.D1.R1.S07: PiTxDqs: 18
N2.C3.D1.R1.S04: RdPtrOffsetTxDq: 07
N4.C2.D1.R1.S13: RdPtrOffsetTxDq: 05
N6.C2.D1.R1.S10: RdPtrOffsetTxDq: 06
N0.C2.D1.R1.S08: wrcmd2dqsstartlatency: 04
N2.C3.D1.R1.S05: RdPtrOffsetTxDq: 07
N4.C2.D1.R1.S14: RdPtrOffsetTxDq: 06
N6.C2.D1.R1.S10: RdPtrOffsetTxDqs: 07
N0.C2.D1.R1.S08: RdPtrOffsetTxDq: 05
N2.C3.D1.R1.S06: RdPtrOffsetTxDq: 07
N4.C2.D1.R1.S15: RdPtrOffsetTxDq: 06
N6.C2.D1.R1.S10: PiTxDqs: 35
N0.C2.D1.R1.S08: RdPtrOffsetTxDqs: 06
N2.C3.D1.R1.S07: RdPtrOffsetTxDq: 07
N4.C2.D1.R1.S16: RdPtrOffsetTxDq: 06
N6.C2.D1.R1.S11: wrcmd2dqsstartlatency: 04
N0.C2.D1.R1.S08: PiTxDqs: 48
N2.C3.D1.R1.S08: RdPtrOffsetTxDq: 07
N4.C2.D1.R1.S17: RdPtrOffsetTxDq: 06
N6.C2.D1.R1.S11: RdPtrOffsetTxDq: 05
N0.C2.D1.R1.S09: wrcmd2dqsstartlatency: 04
N2.C3.D1.R1.S09: RdPtrOffsetTxDq: 08
N4.C2.D1.R1.S00: RdPtrOffsetTxDq: 08
N6.C2.D1.R1.S11: RdPtrOffsetTxDqs: 07
N0.C2.D1.R1.S09: RdPtrOffsetTxDq: 06
N2.C3.D1.R1.S10: RdPtrOffsetTxDq: 08
N4.C2.D1.R1.S01: RdPtrOffsetTxDq: 07
N6.C2.D1.R1.S11: PiTxDqs: 29
N0.C2.D1.R1.S09: RdPtrOffsetTxDqs: 07
N2.C3.D1.R1.S11: RdPtrOffsetTxDq: 07
N4.C2.D1.R1.S02: RdPtrOffsetTxDq: 07
N6.C2.D1.R1.S12: wrcmd2dqsstartlatency: 04
N0.C2.D1.R1.S09: PiTxDqs: 51
N2.C3.D1.R1.S12: RdPtrOffsetTxDq: 07
N4.C2.D1.R1.S03: RdPtrOffsetTxDq: 07
N6.C2.D1.R1.S12: RdPtrOffsetTxDq: 05
N0.C2.D1.R1.S10: wrcmd2dqsstartlatency: 04
N2.C3.D1.R1.S13: RdPtrOffsetTxDq: 07
N4.C2.D1.R1.S04: RdPtrOffsetTxDq: 06
N6.C2.D1.R1.S12: RdPtrOffsetTxDqs: 07
N0.C2.D1.R1.S10: RdPtrOffsetTxDq: 06
N2.C3.D1.R1.S14: RdPtrOffsetTxDq: 07
N4.C2.D1.R1.S05: RdPtrOffsetTxDq: 07
N6.C2.D1.R1.S12: PiTxDqs: 15
N0.C2.D1.R1.S10: RdPtrOffsetTxDqs: 07
N2.C3.D1.R1.S15: RdPtrOffsetTxDq: 07
N4.C2.D1.R1.S06: RdPtrOffsetTxDq: 07
N6.C2.D1.R1.S13: wrcmd2dqsstartlatency: 04
N0.C2.D1.R1.S10: PiTxDqs: 40
N2.C3.D1.R1.S16: RdPtrOffsetTxDq: 07
N4.C2.D1.R1.S07: RdPtrOffsetTxDq: 07
N6.C2.D1.R1.S13: RdPtrOffsetTxDq: 05
N0.C2.D1.R1.S11: wrcmd2dqsstartlatency: 04
N2.C3.D1.R1.S17: RdPtrOffsetTxDq: 07
N4.C2.D1.R1.S08: RdPtrOffsetTxDq: 07
N6.C2.D1.R1.S13: RdPtrOffsetTxDqs: 06
N0.C2.D1.R1.S11: RdPtrOffsetTxDq: 05
N2.C3.D1.R1.S00: Total Delay in PI ticks: TxDQ = 985
N4.C2.D1.R1.S09: RdPtrOffsetTxDq: 08
N6.C2.D1.R1.S13: PiTxDqs: 34
N0.C2.D1.R1.S11: RdPtrOffsetTxDqs: 07
N2.C3.D1.R1.S01: Total Delay in PI ticks: TxDQ = 966
N4.C2.D1.R1.S10: RdPtrOffsetTxDq: 07
N6.C2.D1.R1.S14: wrcmd2dqsstartlatency: 04
N0.C2.D1.R1.S11: PiTxDqs: 31
N2.C3.D1.R1.S02: Total Delay in PI ticks: TxDQ = 957
N4.C2.D1.R1.S11: RdPtrOffsetTxDq: 07
N6.C2.D1.R1.S14: RdPtrOffsetTxDq: 05
N0.C2.D1.R1.S12: wrcmd2dqsstartlatency: 04
N2.C3.D1.R1.S03: Total Delay in PI ticks: TxDQ = 942
N4.C2.D1.R1.S12: RdPtrOffsetTxDq: 07
N6.C2.D1.R1.S14: RdPtrOffsetTxDqs: 06
N0.C2.D1.R1.S12: RdPtrOffsetTxDq: 05
N2.C3.D1.R1.S04: Total Delay in PI ticks: TxDQ = 907
N4.C2.D1.R1.S13: RdPtrOffsetTxDq: 06
N6.C2.D1.R1.S14: PiTxDqs: 62
N0.C2.D1.R1.S12: RdPtrOffsetTxDqs: 07
N2.C3.D1.R1.S05: Total Delay in PI ticks: TxDQ = 921
N4.C2.D1.R1.S14: RdPtrOffsetTxDq: 07
N6.C2.D1.R1.S15: wrcmd2dqsstartlatency: 04
N0.C2.D1.R1.S12: PiTxDqs: 14
N2.C3.D1.R1.S06: Total Delay in PI ticks: TxDQ = 933
N4.C2.D1.R1.S15: RdPtrOffsetTxDq: 07
N6.C2.D1.R1.S15: RdPtrOffsetTxDq: 05
N0.C2.D1.R1.S13: wrcmd2dqsstartlatency: 04
N2.C3.D1.R1.S07: Total Delay in PI ticks: TxDQ = 952
N4.C2.D1.R1.S16: RdPtrOffsetTxDq: 07
N6.C2.D1.R1.S15: RdPtrOffsetTxDqs: 06
N0.C2.D1.R1.S13: RdPtrOffsetTxDq: 05
N2.C3.D1.R1.S08: Total Delay in PI ticks: TxDQ = 921
N4.C2.D1.R1.S17: RdPtrOffsetTxDq: 07
N6.C2.D1.R1.S15: PiTxDqs: 62
N0.C2.D1.R1.S13: RdPtrOffsetTxDqs: 06
N2.C3.D1.R1.S09: Total Delay in PI ticks: TxDQ = 983
N4.C2.D1.R1.S00: Total Delay in PI ticks: TxDQ = 977
N6.C2.D1.R1.S16: wrcmd2dqsstartlatency: 04
N0.C2.D1.R1.S13: PiTxDqs: 38
N2.C3.D1.R1.S10: Total Delay in PI ticks: TxDQ = 965
N4.C2.D1.R1.S01: Total Delay in PI ticks: TxDQ = 961
N6.C2.D1.R1.S16: RdPtrOffsetTxDq: 05
N0.C2.D1.R1.S14: wrcmd2dqsstartlatency: 04
N2.C3.D1.R1.S11: Total Delay in PI ticks: TxDQ = 959
N4.C2.D1.R1.S02: Total Delay in PI ticks: TxDQ = 952
N6.C2.D1.R1.S16: RdPtrOffsetTxDqs: 07
N0.C2.D1.R1.S14: RdPtrOffsetTxDq: 05
N2.C3.D1.R1.S12: Total Delay in PI ticks: TxDQ = 942
N4.C2.D1.R1.S03: Total Delay in PI ticks: TxDQ = 936
N6.C2.D1.R1.S16: PiTxDqs: 21
N0.C2.D1.R1.S14: RdPtrOffsetTxDqs: 07
N2.C3.D1.R1.S13: Total Delay in PI ticks: TxDQ = 907
N4.C2.D1.R1.S04: Total Delay in PI ticks: TxDQ = 898
N6.C2.D1.R1.S17: wrcmd2dqsstartlatency: 04
N0.C2.D1.R1.S14: PiTxDqs: 00
N2.C3.D1.R1.S14: Total Delay in PI ticks: TxDQ = 919
N4.C2.D1.R1.S05: Total Delay in PI ticks: TxDQ = 926
N6.C2.D1.R1.S17: RdPtrOffsetTxDq: 05
N0.C2.D1.R1.S15: wrcmd2dqsstartlatency: 04
N2.C3.D1.R1.S15: Total Delay in PI ticks: TxDQ = 935
N4.C2.D1.R1.S06: Total Delay in PI ticks: TxDQ = 920
N6.C2.D1.R1.S17: RdPtrOffsetTxDqs: 06
N0.C2.D1.R1.S15: RdPtrOffsetTxDq: 05
N2.C3.D1.R1.S16: Total Delay in PI ticks: TxDQ = 951
N4.C2.D1.R1.S07: Total Delay in PI ticks: TxDQ = 943
N6.C2.D1.R1.S17: PiTxDqs: 48
N0.C2.D1.R1.S15: RdPtrOffsetTxDqs: 06
N2.C3.D1.R1.S17: Total Delay in PI ticks: TxDQ = 921
N4.C2.D1.R1.S08: Total Delay in PI ticks: TxDQ = 911
N6.C2.D1.R1.S00: RdPtrOffsetTxDq: 07
N0.C2.D1.R1.S15: PiTxDqs: 62
N2.C3: Calculating Optimimum DQ/DQS Values
N4.C2.D1.R1.S09: Total Delay in PI ticks: TxDQ = 975
N6.C2.D1.R1.S01: RdPtrOffsetTxDq: 06
N0.C2.D1.R1.S16: wrcmd2dqsstartlatency: 04
N4.C2.D1.R1.S10: Total Delay in PI ticks: TxDQ = 962
N6.C2.D1.R1.S02: RdPtrOffsetTxDq: 06
N0.C2.D1.R1.S16: RdPtrOffsetTxDq: 05
START_DATA_TX_DQ
N4.C2.D1.R1.S11: Total Delay in PI ticks: TxDQ = 952
N6.C2.D1.R1.S03: RdPtrOffsetTxDq: 06
N0.C2.D1.R1.S16: RdPtrOffsetTxDqs: 07
N2.C3.S00: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 009, RdPtrOffsetTxDqs = 009
N4.C2.D1.R1.S12: Total Delay in PI ticks: TxDQ = 937
N6.C2.D1.R1.S04: RdPtrOffsetTxDq: 05
N0.C2.D1.R1.S16: PiTxDqs: 23
N2.C3.S00: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 009, RdPtrOffsetTxDqs = 009
N4.C2.D1.R1.S13: Total Delay in PI ticks: TxDQ = 897
N6.C2.D1.R1.S05: RdPtrOffsetTxDq: 06
N0.C2.D1.R1.S17: wrcmd2dqsstartlatency: 04
N2.C3.S01: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 009, RdPtrOffsetTxDqs = 009
N4.C2.D1.R1.S14: Total Delay in PI ticks: TxDQ = 926
N6.C2.D1.R1.S06: RdPtrOffsetTxDq: 06
N0.C2.D1.R1.S17: RdPtrOffsetTxDq: 05
N2.C3.S01: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 009, RdPtrOffsetTxDqs = 009
N4.C2.D1.R1.S15: Total Delay in PI ticks: TxDQ = 925
N6.C2.D1.R1.S07: RdPtrOffsetTxDq: 06
N0.C2.D1.R1.S17: RdPtrOffsetTxDqs: 06
N2.C3.S02: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 009
N4.C2.D1.R1.S16: Total Delay in PI ticks: TxDQ = 943
N6.C2.D1.R1.S08: RdPtrOffsetTxDq: 06
N0.C2.D1.R1.S17: PiTxDqs: 49
N2.C3.S02: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 009
N4.C2.D1.R1.S17: Total Delay in PI ticks: TxDQ = 909
N6.C2.D1.R1.S09: RdPtrOffsetTxDq: 07
N0.C2.D1.R1.S00: RdPtrOffsetTxDq: 07
N2.C3.S03: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 009
N4.C2: Calculating Optimimum DQ/DQS Values
N6.C2.D1.R1.S10: RdPtrOffsetTxDq: 07
N0.C2.D1.R1.S01: RdPtrOffsetTxDq: 07
N2.C3.S03: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 009
N6.C2.D1.R1.S11: RdPtrOffsetTxDq: 06
N0.C2.D1.R1.S02: RdPtrOffsetTxDq: 06
N2.C3.S04: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 008
START_DATA_TX_DQ
N6.C2.D1.R1.S12: RdPtrOffsetTxDq: 06
N0.C2.D1.R1.S03: RdPtrOffsetTxDq: 06
N2.C3.S04: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 008
N4.C2.S00: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 009, RdPtrOffsetTxDqs = 009
N6.C2.D1.R1.S13: RdPtrOffsetTxDq: 06
N0.C2.D1.R1.S04: RdPtrOffsetTxDq: 06
N2.C3.S05: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 008
N4.C2.S00: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 009, RdPtrOffsetTxDqs = 009
N6.C2.D1.R1.S14: RdPtrOffsetTxDq: 06
N0.C2.D1.R1.S05: RdPtrOffsetTxDq: 06
N2.C3.S05: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 008
N4.C2.S01: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 009
N6.C2.D1.R1.S15: RdPtrOffsetTxDq: 06
N0.C2.D1.R1.S06: RdPtrOffsetTxDq: 06
N2.C3.S06: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 009
N4.C2.S01: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 009
N6.C2.D1.R1.S16: RdPtrOffsetTxDq: 06
N0.C2.D1.R1.S07: RdPtrOffsetTxDq: 06
N2.C3.S06: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 009
N4.C2.S02: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 009
N6.C2.D1.R1.S17: RdPtrOffsetTxDq: 06
N0.C2.D1.R1.S08: RdPtrOffsetTxDq: 06
N2.C3.S07: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 009
N4.C2.S02: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 009
N6.C2.D1.R1.S00: RdPtrOffsetTxDq: 08
N0.C2.D1.R1.S09: RdPtrOffsetTxDq: 07
N2.C3.S07: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 009
N4.C2.S03: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 009
N6.C2.D1.R1.S01: RdPtrOffsetTxDq: 07
N0.C2.D1.R1.S10: RdPtrOffsetTxDq: 07
N2.C3.S08: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 008
N4.C2.S03: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 009
N6.C2.D1.R1.S02: RdPtrOffsetTxDq: 07
N0.C2.D1.R1.S11: RdPtrOffsetTxDq: 06
N2.C3.S08: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 008
N4.C2.S04: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 007, RdPtrOffsetTxDqs = 008
N6.C2.D1.R1.S03: RdPtrOffsetTxDq: 07
N0.C2.D1.R1.S12: RdPtrOffsetTxDq: 06
N2.C3.D0.R0.S00: TxDqs: plus1 = 1, minus1 = 0, PI = 52, DB = 1
N4.C2.S04: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 007, RdPtrOffsetTxDqs = 008
N6.C2.D1.R1.S04: RdPtrOffsetTxDq: 06
N0.C2.D1.R1.S13: RdPtrOffsetTxDq: 06
N2.C3.D0.R0.S00: TxDq : plus1 = 1, minus1 = 0, PI = 19, DB = 0
N4.C2.S05: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 008
N6.C2.D1.R1.S05: RdPtrOffsetTxDq: 07
N0.C2.D1.R1.S14: RdPtrOffsetTxDq: 06
N2.C3.D0.R0.S01: TxDqs: plus1 = 1, minus1 = 0, PI = 34, DB = 0
N4.C2.S05: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 008
N6.C2.D1.R1.S06: RdPtrOffsetTxDq: 07
N0.C2.D1.R1.S15: RdPtrOffsetTxDq: 06
N2.C3.D0.R0.S01: TxDq : plus1 = 1, minus1 = 0, PI = 02, DB = 1
N4.C2.S06: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 008
N6.C2.D1.R1.S07: RdPtrOffsetTxDq: 07
N0.C2.D1.R1.S16: RdPtrOffsetTxDq: 06
N2.C3.D0.R0.S02: TxDqs: plus1 = 1, minus1 = 0, PI = 26, DB = 0
N4.C2.S06: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 008
N6.C2.D1.R1.S08: RdPtrOffsetTxDq: 07
N0.C2.D1.R1.S17: RdPtrOffsetTxDq: 06
N2.C3.D0.R0.S02: TxDq : plus1 = 1, minus1 = 0, PI = 58, DB = 1
N4.C2.S07: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 009
N6.C2.D1.R1.S09: RdPtrOffsetTxDq: 08
N0.C2.D1.R1.S00: RdPtrOffsetTxDq: 08
N2.C3.D0.R0.S03: TxDqs: plus1 = 1, minus1 = 0, PI = 09, DB = 1
N4.C2.S07: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 009
N6.C2.D1.R1.S10: RdPtrOffsetTxDq: 08
N0.C2.D1.R1.S01: RdPtrOffsetTxDq: 08
N2.C3.D0.R0.S03: TxDq : plus1 = 1, minus1 = 0, PI = 41, DB = 0
N4.C2.S08: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 008
N6.C2.D1.R1.S11: RdPtrOffsetTxDq: 07
N0.C2.D1.R1.S02: RdPtrOffsetTxDq: 07
N2.C3.D0.R0.S04: TxDqs: plus1 = 1, minus1 = 0, PI = 39, DB = 0
N4.C2.S08: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 008
N6.C2.D1.R1.S12: RdPtrOffsetTxDq: 07
N0.C2.D1.R1.S03: RdPtrOffsetTxDq: 07
N2.C3.D0.R0.S04: TxDq : plus1 = 1, minus1 = 0, PI = 07, DB = 1
N4.C2.D0.R0.S00: TxDqs: plus1 = 1, minus1 = 0, PI = 47, DB = 0
N6.C2.D1.R1.S13: RdPtrOffsetTxDq: 07
N0.C2.D1.R1.S04: RdPtrOffsetTxDq: 07
N2.C3.D0.R0.S05: TxDqs: plus1 = 1, minus1 = 0, PI = 52, DB = 1
N4.C2.D0.R0.S00: TxDq : plus1 = 1, minus1 = 0, PI = 13, DB = 1
N6.C2.D1.R1.S14: RdPtrOffsetTxDq: 07
N0.C2.D1.R1.S05: RdPtrOffsetTxDq: 07
N2.C3.D0.R0.S05: TxDq : plus1 = 1, minus1 = 0, PI = 20, DB = 0
N4.C2.D0.R0.S01: TxDqs: plus1 = 1, minus1 = 0, PI = 33, DB = 0
N6.C2.D1.R1.S15: RdPtrOffsetTxDq: 07
N0.C2.D1.R1.S06: RdPtrOffsetTxDq: 07
N2.C3.D0.R0.S06: TxDqs: plus1 = 1, minus1 = 0, PI = 03, DB = 1
N4.C2.D0.R0.S01: TxDq : plus1 = 1, minus1 = 0, PI = 63, DB = 1
N6.C2.D1.R1.S16: RdPtrOffsetTxDq: 07
N0.C2.D1.R1.S07: RdPtrOffsetTxDq: 07
N2.C3.D0.R0.S06: TxDq : plus1 = 1, minus1 = 0, PI = 34, DB = 0
N4.C2.D0.R0.S02: TxDqs: plus1 = 1, minus1 = 0, PI = 23, DB = 0
N6.C2.D1.R1.S17: RdPtrOffsetTxDq: 07
N0.C2.D1.R1.S08: RdPtrOffsetTxDq: 07
N2.C3.D0.R0.S07: TxDqs: plus1 = 1, minus1 = 0, PI = 19, DB = 0
N4.C2.D0.R0.S02: TxDq : plus1 = 1, minus1 = 0, PI = 54, DB = 1
N6.C2.D1.R1.S00: Total Delay in PI ticks: TxDQ = 978
N0.C2.D1.R1.S09: RdPtrOffsetTxDq: 08
N2.C3.D0.R0.S07: TxDq : plus1 = 1, minus1 = 0, PI = 50, DB = 1
N4.C2.D0.R0.S03: TxDqs: plus1 = 1, minus1 = 0, PI = 06, DB = 1
N6.C2.D1.R1.S01: Total Delay in PI ticks: TxDQ = 963
N0.C2.D1.R1.S10: RdPtrOffsetTxDq: 08
N2.C3.D0.R0.S08: TxDqs: plus1 = 1, minus1 = 0, PI = 57, DB = 1
N4.C2.D0.R0.S03: TxDq : plus1 = 1, minus1 = 0, PI = 36, DB = 0
N6.C2.D1.R1.S02: Total Delay in PI ticks: TxDQ = 956
N0.C2.D1.R1.S11: RdPtrOffsetTxDq: 07
N2.C3.D0.R0.S08: TxDq : plus1 = 1, minus1 = 0, PI = 25, DB = 0
N4.C2.D0.R0.S04: TxDqs: plus1 = 1, minus1 = 0, PI = 27, DB = 0
N6.C2.D1.R1.S03: Total Delay in PI ticks: TxDQ = 939
N0.C2.D1.R1.S12: RdPtrOffsetTxDq: 07
N2.C3.D0.R0.S09: TxDqs: plus1 = 1, minus1 = 0, PI = 51, DB = 1
N4.C2.D0.R0.S04: TxDq : plus1 = 1, minus1 = 0, PI = 60, DB = 1
N6.C2.D1.R1.S04: Total Delay in PI ticks: TxDQ = 897
N0.C2.D1.R1.S13: RdPtrOffsetTxDq: 07
N2.C3.D0.R0.S09: TxDq : plus1 = 1, minus1 = 0, PI = 18, DB = 0
N4.C2.D0.R0.S05: TxDqs: plus1 = 1, minus1 = 0, PI = 57, DB = 1
N6.C2.D1.R1.S05: Total Delay in PI ticks: TxDQ = 929
N0.C2.D1.R1.S14: RdPtrOffsetTxDq: 07
N2.C3.D0.R0.S10: TxDqs: plus1 = 1, minus1 = 0, PI = 35, DB = 0
N4.C2.D0.R0.S05: TxDq : plus1 = 1, minus1 = 0, PI = 23, DB = 0
N6.C2.D1.R1.S06: Total Delay in PI ticks: TxDQ = 923
N0.C2.D1.R1.S15: RdPtrOffsetTxDq: 07
N2.C3.D0.R0.S10: TxDq : plus1 = 1, minus1 = 0, PI = 03, DB = 1
N4.C2.D0.R0.S06: TxDqs: plus1 = 1, minus1 = 0, PI = 56, DB = 1
N6.C2.D1.R1.S07: Total Delay in PI ticks: TxDQ = 947
N0.C2.D1.R1.S16: RdPtrOffsetTxDq: 07
N2.C3.D0.R0.S11: TxDqs: plus1 = 1, minus1 = 0, PI = 27, DB = 0
N4.C2.D0.R0.S06: TxDq : plus1 = 1, minus1 = 0, PI = 22, DB = 0
N6.C2.D1.R1.S08: Total Delay in PI ticks: TxDQ = 911
N0.C2.D1.R1.S17: RdPtrOffsetTxDq: 07
N2.C3.D0.R0.S11: TxDq : plus1 = 1, minus1 = 0, PI = 59, DB = 1
N4.C2.D0.R0.S07: TxDqs: plus1 = 1, minus1 = 0, PI = 13, DB = 1
N6.C2.D1.R1.S09: Total Delay in PI ticks: TxDQ = 974
N0.C2.D1.R1.S00: Total Delay in PI ticks: TxDQ = 979
N2.C3.D0.R0.S12: TxDqs: plus1 = 1, minus1 = 0, PI = 11, DB = 1
N4.C2.D0.R0.S07: TxDq : plus1 = 1, minus1 = 0, PI = 44, DB = 0
N6.C2.D1.R1.S10: Total Delay in PI ticks: TxDQ = 962
N0.C2.D1.R1.S01: Total Delay in PI ticks: TxDQ = 964
N2.C3.D0.R0.S12: TxDq : plus1 = 1, minus1 = 0, PI = 42, DB = 0
N4.C2.D0.R0.S08: TxDqs: plus1 = 1, minus1 = 0, PI = 49, DB = 1
N6.C2.D1.R1.S11: Total Delay in PI ticks: TxDQ = 957
N0.C2.D1.R1.S02: Total Delay in PI ticks: TxDQ = 955
N2.C3.D0.R0.S13: TxDqs: plus1 = 1, minus1 = 0, PI = 39, DB = 0
N4.C2.D0.R0.S08: TxDq : plus1 = 1, minus1 = 0, PI = 14, DB = 1
N6.C2.D1.R1.S12: Total Delay in PI ticks: TxDQ = 941
N0.C2.D1.R1.S03: Total Delay in PI ticks: TxDQ = 937
N2.C3.D0.R0.S13: TxDq : plus1 = 1, minus1 = 0, PI = 07, DB = 1
N4.C2.D0.R0.S09: TxDqs: plus1 = 1, minus1 = 0, PI = 49, DB = 1
N6.C2.D1.R1.S13: Total Delay in PI ticks: TxDQ = 897
N0.C2.D1.R1.S04: Total Delay in PI ticks: TxDQ = 900
N2.C3.D0.R0.S14: TxDqs: plus1 = 1, minus1 = 0, PI = 52, DB = 1
N4.C2.D0.R0.S09: TxDq : plus1 = 1, minus1 = 0, PI = 14, DB = 1
N6.C2.D1.R1.S14: Total Delay in PI ticks: TxDQ = 926
N0.C2.D1.R1.S05: Total Delay in PI ticks: TxDQ = 927
N2.C3.D0.R0.S14: TxDq : plus1 = 1, minus1 = 0, PI = 21, DB = 0
N4.C2.D0.R0.S10: TxDqs: plus1 = 1, minus1 = 0, PI = 36, DB = 0
N6.C2.D1.R1.S15: Total Delay in PI ticks: TxDQ = 925
N0.C2.D1.R1.S06: Total Delay in PI ticks: TxDQ = 922
N2.C3.D0.R0.S15: TxDqs: plus1 = 1, minus1 = 0, PI = 03, DB = 1
N4.C2.D0.R0.S10: TxDq : plus1 = 0, minus1 = 1, PI = 01, DB = 1
N6.C2.D1.R1.S16: Total Delay in PI ticks: TxDQ = 948
N0.C2.D1.R1.S07: Total Delay in PI ticks: TxDQ = 943
N2.C3.D0.R0.S15: TxDq : plus1 = 1, minus1 = 0, PI = 35, DB = 0
N4.C2.D0.R0.S11: TxDqs: plus1 = 1, minus1 = 0, PI = 23, DB = 0
N6.C2.D1.R1.S17: Total Delay in PI ticks: TxDQ = 909
N0.C2.D1.R1.S08: Total Delay in PI ticks: TxDQ = 910
N2.C3.D0.R0.S16: TxDqs: plus1 = 1, minus1 = 0, PI = 18, DB = 0
N4.C2.D0.R0.S11: TxDq : plus1 = 1, minus1 = 0, PI = 54, DB = 1
N6.C2: Calculating Optimimum DQ/DQS Values
N0.C2.D1.R1.S09: Total Delay in PI ticks: TxDQ = 978
N2.C3.D0.R0.S16: TxDq : plus1 = 1, minus1 = 0, PI = 50, DB = 1
N4.C2.D0.R0.S12: TxDqs: plus1 = 1, minus1 = 0, PI = 08, DB = 1
N0.C2.D1.R1.S10: Total Delay in PI ticks: TxDQ = 964
N2.C3.D0.R0.S17: TxDqs: plus1 = 1, minus1 = 0, PI = 57, DB = 1
N4.C2.D0.R0.S12: TxDq : plus1 = 1, minus1 = 0, PI = 39, DB = 0
START_DATA_TX_DQ
N0.C2.D1.R1.S11: Total Delay in PI ticks: TxDQ = 957
N2.C3.D0.R0.S17: TxDq : plus1 = 1, minus1 = 0, PI = 25, DB = 0
N4.C2.D0.R0.S13: TxDqs: plus1 = 1, minus1 = 0, PI = 29, DB = 0
N6.C2.S00: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 009, RdPtrOffsetTxDqs = 009
N0.C2.D1.R1.S12: Total Delay in PI ticks: TxDQ = 939
N2.C3.D0.R1.S00: TxDqs: plus1 = 1, minus1 = 0, PI = 52, DB = 1
N4.C2.D0.R0.S13: TxDq : plus1 = 1, minus1 = 0, PI = 60, DB = 1
N6.C2.S00: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 009, RdPtrOffsetTxDqs = 009
N0.C2.D1.R1.S13: Total Delay in PI ticks: TxDQ = 900
N2.C3.D0.R1.S00: TxDq : plus1 = 1, minus1 = 0, PI = 19, DB = 0
N4.C2.D0.R0.S14: TxDqs: plus1 = 1, minus1 = 0, PI = 58, DB = 1
N6.C2.S01: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 009
N0.C2.D1.R1.S14: Total Delay in PI ticks: TxDQ = 928
N2.C3.D0.R1.S01: TxDqs: plus1 = 1, minus1 = 0, PI = 34, DB = 0
N4.C2.D0.R0.S14: TxDq : plus1 = 1, minus1 = 0, PI = 26, DB = 0
N6.C2.S01: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 009
N0.C2.D1.R1.S15: Total Delay in PI ticks: TxDQ = 924
N2.C3.D0.R1.S01: TxDq : plus1 = 1, minus1 = 0, PI = 02, DB = 1
N4.C2.D0.R0.S15: TxDqs: plus1 = 1, minus1 = 0, PI = 57, DB = 1
N6.C2.S02: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 009
N0.C2.D1.R1.S16: Total Delay in PI ticks: TxDQ = 946
N2.C3.D0.R1.S02: TxDqs: plus1 = 1, minus1 = 0, PI = 26, DB = 0
N4.C2.D0.R0.S15: TxDq : plus1 = 1, minus1 = 0, PI = 25, DB = 0
N6.C2.S02: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 009
N0.C2.D1.R1.S17: Total Delay in PI ticks: TxDQ = 910
N2.C3.D0.R1.S02: TxDq : plus1 = 1, minus1 = 0, PI = 58, DB = 1
N4.C2.D0.R0.S16: TxDqs: plus1 = 1, minus1 = 0, PI = 13, DB = 1
N6.C2.S03: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 009
N0.C2: Calculating Optimimum DQ/DQS Values
N2.C3.D0.R1.S03: TxDqs: plus1 = 1, minus1 = 0, PI = 09, DB = 1
N4.C2.D0.R0.S16: TxDq : plus1 = 1, minus1 = 0, PI = 44, DB = 0
N6.C2.S03: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 009
START_DATA_TX_DQ
N2.C3.D0.R1.S03: TxDq : plus1 = 1, minus1 = 0, PI = 41, DB = 0
N4.C2.D0.R0.S17: TxDqs: plus1 = 1, minus1 = 0, PI = 46, DB = 0
N6.C2.S04: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 007, RdPtrOffsetTxDqs = 008
N0.C2.S00: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 009, RdPtrOffsetTxDqs = 009
N2.C3.D0.R1.S04: TxDqs: plus1 = 1, minus1 = 0, PI = 39, DB = 0
N4.C2.D0.R0.S17: TxDq : plus1 = 1, minus1 = 0, PI = 13, DB = 1
N6.C2.S04: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 007, RdPtrOffsetTxDqs = 008
N0.C2.S00: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 009, RdPtrOffsetTxDqs = 009
N2.C3.D0.R1.S04: TxDq : plus1 = 1, minus1 = 0, PI = 07, DB = 1
N4.C2.D0.R1.S00: TxDqs: plus1 = 1, minus1 = 0, PI = 47, DB = 0
N6.C2.S05: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 008
N0.C2.S01: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 009, RdPtrOffsetTxDqs = 009
N2.C3.D0.R1.S05: TxDqs: plus1 = 1, minus1 = 0, PI = 52, DB = 1
N4.C2.D0.R1.S00: TxDq : plus1 = 1, minus1 = 0, PI = 13, DB = 1
N6.C2.S05: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 008
N0.C2.S01: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 009, RdPtrOffsetTxDqs = 009
N2.C3.D0.R1.S05: TxDq : plus1 = 1, minus1 = 0, PI = 20, DB = 0
N4.C2.D0.R1.S01: TxDqs: plus1 = 1, minus1 = 0, PI = 33, DB = 0
N6.C2.S06: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 008
N0.C2.S02: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 009
N2.C3.D0.R1.S06: TxDqs: plus1 = 1, minus1 = 0, PI = 03, DB = 1
N4.C2.D0.R1.S01: TxDq : plus1 = 1, minus1 = 0, PI = 63, DB = 1
N6.C2.S06: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 008
N0.C2.S02: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 009
N2.C3.D0.R1.S06: TxDq : plus1 = 1, minus1 = 0, PI = 34, DB = 0
N4.C2.D0.R1.S02: TxDqs: plus1 = 1, minus1 = 0, PI = 23, DB = 0
N6.C2.S07: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 009
N0.C2.S03: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 009
N2.C3.D0.R1.S07: TxDqs: plus1 = 1, minus1 = 0, PI = 19, DB = 0
N4.C2.D0.R1.S02: TxDq : plus1 = 1, minus1 = 0, PI = 54, DB = 1
N6.C2.S07: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 009
N0.C2.S03: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 009
N2.C3.D0.R1.S07: TxDq : plus1 = 1, minus1 = 0, PI = 50, DB = 1
N4.C2.D0.R1.S03: TxDqs: plus1 = 1, minus1 = 0, PI = 06, DB = 1
N6.C2.S08: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 008
N0.C2.S04: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 007, RdPtrOffsetTxDqs = 008
N2.C3.D0.R1.S08: TxDqs: plus1 = 1, minus1 = 0, PI = 57, DB = 1
N4.C2.D0.R1.S03: TxDq : plus1 = 1, minus1 = 0, PI = 36, DB = 0
N6.C2.S08: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 008
N0.C2.S04: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 007, RdPtrOffsetTxDqs = 008
N2.C3.D0.R1.S08: TxDq : plus1 = 1, minus1 = 0, PI = 25, DB = 0
N4.C2.D0.R1.S04: TxDqs: plus1 = 1, minus1 = 0, PI = 27, DB = 0
N6.C2.D0.R0.S00: TxDqs: plus1 = 1, minus1 = 0, PI = 43, DB = 0
N0.C2.S05: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 008
N2.C3.D0.R1.S09: TxDqs: plus1 = 1, minus1 = 0, PI = 51, DB = 1
N4.C2.D0.R1.S04: TxDq : plus1 = 1, minus1 = 0, PI = 60, DB = 1
N6.C2.D0.R0.S00: TxDq : plus1 = 1, minus1 = 0, PI = 11, DB = 1
N0.C2.S05: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 008
N2.C3.D0.R1.S09: TxDq : plus1 = 1, minus1 = 0, PI = 18, DB = 0
N4.C2.D0.R1.S05: TxDqs: plus1 = 1, minus1 = 0, PI = 57, DB = 1
N6.C2.D0.R0.S01: TxDqs: plus1 = 1, minus1 = 0, PI = 29, DB = 0
N0.C2.S06: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 008
N2.C3.D0.R1.S10: TxDqs: plus1 = 1, minus1 = 0, PI = 35, DB = 0
N4.C2.D0.R1.S05: TxDq : plus1 = 1, minus1 = 0, PI = 23, DB = 0
N6.C2.D0.R0.S01: TxDq : plus1 = 1, minus1 = 0, PI = 60, DB = 1
N0.C2.S06: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 008
N2.C3.D0.R1.S10: TxDq : plus1 = 1, minus1 = 0, PI = 03, DB = 1
N4.C2.D0.R1.S06: TxDqs: plus1 = 1, minus1 = 0, PI = 56, DB = 1
N6.C2.D0.R0.S02: TxDqs: plus1 = 1, minus1 = 0, PI = 20, DB = 0
N0.C2.S07: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 009
N2.C3.D0.R1.S11: TxDqs: plus1 = 1, minus1 = 0, PI = 27, DB = 0
N4.C2.D0.R1.S06: TxDq : plus1 = 1, minus1 = 0, PI = 22, DB = 0
N6.C2.D0.R0.S02: TxDq : plus1 = 1, minus1 = 0, PI = 53, DB = 1
N0.C2.S07: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 009
N2.C3.D0.R1.S11: TxDq : plus1 = 1, minus1 = 0, PI = 59, DB = 1
N4.C2.D0.R1.S07: TxDqs: plus1 = 1, minus1 = 0, PI = 13, DB = 1
N6.C2.D0.R0.S03: TxDqs: plus1 = 1, minus1 = 0, PI = 00, DB = 1
N0.C2.S08: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 008
N2.C3.D0.R1.S12: TxDqs: plus1 = 1, minus1 = 0, PI = 11, DB = 1
N4.C2.D0.R1.S07: TxDq : plus1 = 1, minus1 = 0, PI = 44, DB = 0
N6.C2.D0.R0.S03: TxDq : plus1 = 1, minus1 = 0, PI = 32, DB = 0
N0.C2.S08: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 008
N2.C3.D0.R1.S12: TxDq : plus1 = 1, minus1 = 0, PI = 42, DB = 0
N4.C2.D0.R1.S08: TxDqs: plus1 = 1, minus1 = 0, PI = 49, DB = 1
N6.C2.D0.R0.S04: TxDqs: plus1 = 1, minus1 = 0, PI = 25, DB = 0
N0.C2.D0.R0.S00: TxDqs: plus1 = 1, minus1 = 0, PI = 49, DB = 1
N2.C3.D0.R1.S13: TxDqs: plus1 = 1, minus1 = 0, PI = 39, DB = 0
N4.C2.D0.R1.S08: TxDq : plus1 = 1, minus1 = 0, PI = 14, DB = 1
N6.C2.D0.R0.S04: TxDq : plus1 = 1, minus1 = 0, PI = 58, DB = 1
N0.C2.D0.R0.S00: TxDq : plus1 = 1, minus1 = 0, PI = 17, DB = 0
N2.C3.D0.R1.S13: TxDq : plus1 = 1, minus1 = 0, PI = 07, DB = 1
N4.C2.D0.R1.S09: TxDqs: plus1 = 1, minus1 = 0, PI = 49, DB = 1
N6.C2.D0.R0.S05: TxDqs: plus1 = 1, minus1 = 0, PI = 54, DB = 1
N0.C2.D0.R0.S01: TxDqs: plus1 = 1, minus1 = 0, PI = 35, DB = 0
N2.C3.D0.R1.S14: TxDqs: plus1 = 1, minus1 = 0, PI = 52, DB = 1
N4.C2.D0.R1.S09: TxDq : plus1 = 1, minus1 = 0, PI = 14, DB = 1
N6.C2.D0.R0.S05: TxDq : plus1 = 1, minus1 = 0, PI = 22, DB = 0
N0.C2.D0.R0.S01: TxDq : plus1 = 1, minus1 = 0, PI = 02, DB = 1
N2.C3.D0.R1.S14: TxDq : plus1 = 1, minus1 = 0, PI = 21, DB = 0
N4.C2.D0.R1.S10: TxDqs: plus1 = 1, minus1 = 0, PI = 36, DB = 0
N6.C2.D0.R0.S06: TxDqs: plus1 = 1, minus1 = 0, PI = 53, DB = 1
N0.C2.D0.R0.S02: TxDqs: plus1 = 1, minus1 = 0, PI = 25, DB = 0
N2.C3.D0.R1.S15: TxDqs: plus1 = 1, minus1 = 0, PI = 03, DB = 1
N4.C2.D0.R1.S10: TxDq : plus1 = 0, minus1 = 1, PI = 01, DB = 1
N6.C2.D0.R0.S06: TxDq : plus1 = 1, minus1 = 0, PI = 23, DB = 0
N0.C2.D0.R0.S02: TxDq : plus1 = 1, minus1 = 0, PI = 57, DB = 1
N2.C3.D0.R1.S15: TxDq : plus1 = 1, minus1 = 0, PI = 35, DB = 0
N4.C2.D0.R1.S11: TxDqs: plus1 = 1, minus1 = 0, PI = 23, DB = 0
N6.C2.D0.R0.S07: TxDqs: plus1 = 1, minus1 = 0, PI = 12, DB = 1
N0.C2.D0.R0.S03: TxDqs: plus1 = 1, minus1 = 0, PI = 08, DB = 1
N2.C3.D0.R1.S16: TxDqs: plus1 = 1, minus1 = 0, PI = 18, DB = 0
N4.C2.D0.R1.S11: TxDq : plus1 = 1, minus1 = 0, PI = 54, DB = 1
N6.C2.D0.R0.S07: TxDq : plus1 = 1, minus1 = 0, PI = 41, DB = 0
N0.C2.D0.R0.S03: TxDq : plus1 = 1, minus1 = 0, PI = 38, DB = 0
N2.C3.D0.R1.S16: TxDq : plus1 = 1, minus1 = 0, PI = 50, DB = 1
N4.C2.D0.R1.S12: TxDqs: plus1 = 1, minus1 = 0, PI = 08, DB = 1
N6.C2.D0.R0.S08: TxDqs: plus1 = 1, minus1 = 0, PI = 44, DB = 0
N0.C2.D0.R0.S04: TxDqs: plus1 = 1, minus1 = 0, PI = 33, DB = 0
N2.C3.D0.R1.S17: TxDqs: plus1 = 1, minus1 = 0, PI = 57, DB = 1
N4.C2.D0.R1.S12: TxDq : plus1 = 1, minus1 = 0, PI = 39, DB = 0
N6.C2.D0.R0.S08: TxDq : plus1 = 1, minus1 = 0, PI = 11, DB = 1
N0.C2.D0.R0.S04: TxDq : plus1 = 0, minus1 = 1, PI = 01, DB = 1
N2.C3.D0.R1.S17: TxDq : plus1 = 1, minus1 = 0, PI = 25, DB = 0
N4.C2.D0.R1.S13: TxDqs: plus1 = 1, minus1 = 0, PI = 29, DB = 0
N6.C2.D0.R0.S09: TxDqs: plus1 = 1, minus1 = 0, PI = 43, DB = 0
N0.C2.D0.R0.S05: TxDqs: plus1 = 1, minus1 = 0, PI = 62, DB = 1
N2.C3.D1.R0.S00: TxDqs: plus1 = 1, minus1 = 0, PI = 59, DB = 1
N4.C2.D0.R1.S13: TxDq : plus1 = 1, minus1 = 0, PI = 60, DB = 1
N6.C2.D0.R0.S09: TxDq : plus1 = 1, minus1 = 0, PI = 10, DB = 1
N0.C2.D0.R0.S05: TxDq : plus1 = 1, minus1 = 0, PI = 27, DB = 0
N2.C3.D1.R0.S00: TxDq : plus1 = 1, minus1 = 0, PI = 26, DB = 0
N4.C2.D0.R1.S14: TxDqs: plus1 = 1, minus1 = 0, PI = 58, DB = 1
N6.C2.D0.R0.S10: TxDqs: plus1 = 1, minus1 = 0, PI = 29, DB = 0
N0.C2.D0.R0.S06: TxDqs: plus1 = 1, minus1 = 0, PI = 59, DB = 1
N2.C3.D1.R0.S01: TxDqs: plus1 = 1, minus1 = 0, PI = 41, DB = 0
N4.C2.D0.R1.S14: TxDq : plus1 = 1, minus1 = 0, PI = 26, DB = 0
N6.C2.D0.R0.S10: TxDq : plus1 = 1, minus1 = 0, PI = 61, DB = 1
N0.C2.D0.R0.S06: TxDq : plus1 = 1, minus1 = 0, PI = 27, DB = 0
N2.C3.D1.R0.S01: TxDq : plus1 = 1, minus1 = 0, PI = 09, DB = 1
N4.C2.D0.R1.S15: TxDqs: plus1 = 1, minus1 = 0, PI = 57, DB = 1
N6.C2.D0.R0.S11: TxDqs: plus1 = 1, minus1 = 0, PI = 21, DB = 0
N0.C2.D0.R0.S07: TxDqs: plus1 = 1, minus1 = 0, PI = 16, DB = 0
N2.C3.D1.R0.S02: TxDqs: plus1 = 1, minus1 = 0, PI = 33, DB = 0
N4.C2.D0.R1.S15: TxDq : plus1 = 1, minus1 = 0, PI = 25, DB = 0
N6.C2.D0.R0.S11: TxDq : plus1 = 1, minus1 = 0, PI = 54, DB = 1
N0.C2.D0.R0.S07: TxDq : plus1 = 1, minus1 = 0, PI = 45, DB = 0
N2.C3.D1.R0.S02: TxDq : plus1 = 0, minus1 = 1, PI = 00, DB = 1
N4.C2.D0.R1.S16: TxDqs: plus1 = 1, minus1 = 0, PI = 13, DB = 1
N6.C2.D0.R0.S12: TxDqs: plus1 = 1, minus1 = 0, PI = 02, DB = 1
N0.C2.D0.R0.S08: TxDqs: plus1 = 1, minus1 = 0, PI = 52, DB = 1
N2.C3.D1.R0.S03: TxDqs: plus1 = 1, minus1 = 0, PI = 16, DB = 0
N4.C2.D0.R1.S16: TxDq : plus1 = 1, minus1 = 0, PI = 44, DB = 0
N6.C2.D0.R0.S12: TxDq : plus1 = 1, minus1 = 0, PI = 33, DB = 0
N0.C2.D0.R0.S08: TxDq : plus1 = 1, minus1 = 0, PI = 18, DB = 0
N2.C3.D1.R0.S03: TxDq : plus1 = 1, minus1 = 0, PI = 47, DB = 0
N4.C2.D0.R1.S17: TxDqs: plus1 = 1, minus1 = 0, PI = 46, DB = 0
N6.C2.D0.R0.S13: TxDqs: plus1 = 1, minus1 = 0, PI = 25, DB = 0
N0.C2.D0.R0.S09: TxDqs: plus1 = 1, minus1 = 0, PI = 51, DB = 1
N2.C3.D1.R0.S04: TxDqs: plus1 = 1, minus1 = 0, PI = 45, DB = 0
N4.C2.D0.R1.S17: TxDq : plus1 = 1, minus1 = 0, PI = 13, DB = 1
N6.C2.D0.R0.S13: TxDq : plus1 = 1, minus1 = 0, PI = 58, DB = 1
N0.C2.D0.R0.S09: TxDq : plus1 = 1, minus1 = 0, PI = 18, DB = 0
N2.C3.D1.R0.S04: TxDq : plus1 = 1, minus1 = 0, PI = 12, DB = 1
N4.C2.D1.R0.S00: TxDqs: plus1 = 1, minus1 = 0, PI = 53, DB = 1
N6.C2.D0.R0.S14: TxDqs: plus1 = 1, minus1 = 0, PI = 54, DB = 1
N0.C2.D0.R0.S10: TxDqs: plus1 = 1, minus1 = 0, PI = 37, DB = 0
N2.C3.D1.R0.S05: TxDqs: plus1 = 1, minus1 = 0, PI = 59, DB = 1
N4.C2.D1.R0.S00: TxDq : plus1 = 1, minus1 = 0, PI = 18, DB = 0
N6.C2.D0.R0.S14: TxDq : plus1 = 1, minus1 = 0, PI = 22, DB = 0
N0.C2.D0.R0.S10: TxDq : plus1 = 1, minus1 = 0, PI = 01, DB = 1
N2.C3.D1.R0.S05: TxDq : plus1 = 1, minus1 = 0, PI = 27, DB = 0
N4.C2.D1.R0.S01: TxDqs: plus1 = 1, minus1 = 0, PI = 39, DB = 0
N6.C2.D0.R0.S15: TxDqs: plus1 = 1, minus1 = 0, PI = 54, DB = 1
N0.C2.D0.R0.S11: TxDqs: plus1 = 1, minus1 = 0, PI = 27, DB = 0
N2.C3.D1.R0.S06: TxDqs: plus1 = 1, minus1 = 0, PI = 08, DB = 1
N4.C2.D1.R0.S01: TxDq : plus1 = 0, minus1 = 1, PI = 04, DB = 1
N6.C2.D0.R0.S15: TxDq : plus1 = 1, minus1 = 0, PI = 23, DB = 0
N0.C2.D0.R0.S11: TxDq : plus1 = 1, minus1 = 0, PI = 58, DB = 1
N2.C3.D1.R0.S06: TxDq : plus1 = 1, minus1 = 0, PI = 39, DB = 0
N4.C2.D1.R0.S02: TxDqs: plus1 = 1, minus1 = 0, PI = 29, DB = 0
N6.C2.D0.R0.S16: TxDqs: plus1 = 1, minus1 = 0, PI = 11, DB = 1
N0.C2.D0.R0.S12: TxDqs: plus1 = 1, minus1 = 0, PI = 08, DB = 1
N2.C3.D1.R0.S07: TxDqs: plus1 = 1, minus1 = 0, PI = 26, DB = 0
N4.C2.D1.R0.S02: TxDq : plus1 = 1, minus1 = 0, PI = 58, DB = 1
N6.C2.D0.R0.S16: TxDq : plus1 = 1, minus1 = 0, PI = 42, DB = 0
N0.C2.D0.R0.S12: TxDq : plus1 = 1, minus1 = 0, PI = 38, DB = 0
N2.C3.D1.R0.S07: TxDq : plus1 = 1, minus1 = 0, PI = 57, DB = 1
N4.C2.D1.R0.S03: TxDqs: plus1 = 1, minus1 = 0, PI = 14, DB = 1
N6.C2.D0.R0.S17: TxDqs: plus1 = 1, minus1 = 0, PI = 44, DB = 0
N0.C2.D0.R0.S13: TxDqs: plus1 = 1, minus1 = 0, PI = 31, DB = 0
N2.C3.D1.R0.S08: TxDqs: plus1 = 1, minus1 = 0, PI = 62, DB = 1
N4.C2.D1.R0.S03: TxDq : plus1 = 1, minus1 = 0, PI = 41, DB = 0
N6.C2.D0.R0.S17: TxDq : plus1 = 1, minus1 = 0, PI = 10, DB = 1
N0.C2.D0.R0.S13: TxDq : plus1 = 1, minus1 = 0, PI = 63, DB = 1
N2.C3.D1.R0.S08: TxDq : plus1 = 1, minus1 = 0, PI = 28, DB = 0
N4.C2.D1.R0.S04: TxDqs: plus1 = 1, minus1 = 0, PI = 35, DB = 0
N6.C2.D0.R1.S00: TxDqs: plus1 = 1, minus1 = 0, PI = 43, DB = 0
N0.C2.D0.R0.S14: TxDqs: plus1 = 1, minus1 = 0, PI = 59, DB = 1
N2.C3.D1.R0.S09: TxDqs: plus1 = 1, minus1 = 0, PI = 58, DB = 1
N4.C2.D1.R0.S04: TxDq : plus1 = 0, minus1 = 1, PI = 04, DB = 1
N6.C2.D0.R1.S00: TxDq : plus1 = 1, minus1 = 0, PI = 11, DB = 1
N0.C2.D0.R0.S14: TxDq : plus1 = 1, minus1 = 0, PI = 28, DB = 0
N2.C3.D1.R0.S09: TxDq : plus1 = 1, minus1 = 0, PI = 23, DB = 0
N4.C2.D1.R0.S05: TxDqs: plus1 = 0, minus1 = 1, PI = 00, DB = 1
N6.C2.D0.R1.S01: TxDqs: plus1 = 1, minus1 = 0, PI = 29, DB = 0
N0.C2.D0.R0.S15: TxDqs: plus1 = 1, minus1 = 0, PI = 59, DB = 1
N2.C3.D1.R0.S10: TxDqs: plus1 = 1, minus1 = 0, PI = 41, DB = 0
N4.C2.D1.R0.S05: TxDq : plus1 = 1, minus1 = 0, PI = 31, DB = 0
N6.C2.D0.R1.S01: TxDq : plus1 = 1, minus1 = 0, PI = 60, DB = 1
N0.C2.D0.R0.S15: TxDq : plus1 = 1, minus1 = 0, PI = 26, DB = 0
N2.C3.D1.R0.S10: TxDq : plus1 = 1, minus1 = 0, PI = 08, DB = 1
N4.C2.D1.R0.S06: TxDqs: plus1 = 1, minus1 = 0, PI = 61, DB = 1
N6.C2.D0.R1.S02: TxDqs: plus1 = 1, minus1 = 0, PI = 20, DB = 0
N0.C2.D0.R0.S16: TxDqs: plus1 = 1, minus1 = 0, PI = 17, DB = 0
N2.C3.D1.R0.S11: TxDqs: plus1 = 1, minus1 = 0, PI = 33, DB = 0
N4.C2.D1.R0.S06: TxDq : plus1 = 1, minus1 = 0, PI = 27, DB = 0
N6.C2.D0.R1.S02: TxDq : plus1 = 1, minus1 = 0, PI = 53, DB = 1
N0.C2.D0.R0.S16: TxDq : plus1 = 1, minus1 = 0, PI = 46, DB = 0
N2.C3.D1.R0.S11: TxDq : plus1 = 0, minus1 = 1, PI = 00, DB = 1
N4.C2.D1.R0.S07: TxDqs: plus1 = 1, minus1 = 0, PI = 19, DB = 0
N6.C2.D0.R1.S03: TxDqs: plus1 = 1, minus1 = 0, PI = 00, DB = 1
N0.C2.D0.R0.S17: TxDqs: plus1 = 1, minus1 = 0, PI = 50, DB = 1
N2.C3.D1.R0.S12: TxDqs: plus1 = 1, minus1 = 0, PI = 17, DB = 0
N4.C2.D1.R0.S07: TxDq : plus1 = 1, minus1 = 0, PI = 48, DB = 0
N6.C2.D0.R1.S03: TxDq : plus1 = 1, minus1 = 0, PI = 32, DB = 0
N0.C2.D0.R0.S17: TxDq : plus1 = 1, minus1 = 0, PI = 16, DB = 0
N2.C3.D1.R0.S12: TxDq : plus1 = 1, minus1 = 0, PI = 48, DB = 0
N4.C2.D1.R0.S08: TxDqs: plus1 = 1, minus1 = 0, PI = 51, DB = 1
N6.C2.D0.R1.S04: TxDqs: plus1 = 1, minus1 = 0, PI = 25, DB = 0
N0.C2.D0.R1.S00: TxDqs: plus1 = 1, minus1 = 0, PI = 49, DB = 1
N2.C3.D1.R0.S13: TxDqs: plus1 = 1, minus1 = 0, PI = 46, DB = 0
N4.C2.D1.R0.S08: TxDq : plus1 = 1, minus1 = 0, PI = 16, DB = 0
N6.C2.D0.R1.S04: TxDq : plus1 = 1, minus1 = 0, PI = 58, DB = 1
N0.C2.D0.R1.S00: TxDq : plus1 = 1, minus1 = 0, PI = 17, DB = 0
N2.C3.D1.R0.S13: TxDq : plus1 = 1, minus1 = 0, PI = 13, DB = 1
N4.C2.D1.R0.S09: TxDqs: plus1 = 1, minus1 = 0, PI = 53, DB = 1
N6.C2.D0.R1.S05: TxDqs: plus1 = 1, minus1 = 0, PI = 54, DB = 1
N0.C2.D0.R1.S01: TxDqs: plus1 = 1, minus1 = 0, PI = 35, DB = 0
N2.C3.D1.R0.S14: TxDqs: plus1 = 1, minus1 = 0, PI = 57, DB = 1
N4.C2.D1.R0.S09: TxDq : plus1 = 1, minus1 = 0, PI = 18, DB = 0
N6.C2.D0.R1.S05: TxDq : plus1 = 1, minus1 = 0, PI = 22, DB = 0
N0.C2.D0.R1.S01: TxDq : plus1 = 1, minus1 = 0, PI = 02, DB = 1
N2.C3.D1.R0.S14: TxDq : plus1 = 1, minus1 = 0, PI = 25, DB = 0
N4.C2.D1.R0.S10: TxDqs: plus1 = 1, minus1 = 0, PI = 40, DB = 0
N6.C2.D0.R1.S06: TxDqs: plus1 = 1, minus1 = 0, PI = 53, DB = 1
N0.C2.D0.R1.S02: TxDqs: plus1 = 1, minus1 = 0, PI = 25, DB = 0
N2.C3.D1.R0.S15: TxDqs: plus1 = 1, minus1 = 0, PI = 08, DB = 1
N4.C2.D1.R0.S10: TxDq : plus1 = 0, minus1 = 1, PI = 03, DB = 1
N6.C2.D0.R1.S06: TxDq : plus1 = 1, minus1 = 0, PI = 23, DB = 0
N0.C2.D0.R1.S02: TxDq : plus1 = 1, minus1 = 0, PI = 57, DB = 1
N2.C3.D1.R0.S15: TxDq : plus1 = 1, minus1 = 0, PI = 40, DB = 0
N4.C2.D1.R0.S11: TxDqs: plus1 = 1, minus1 = 0, PI = 29, DB = 0
N6.C2.D0.R1.S07: TxDqs: plus1 = 1, minus1 = 0, PI = 12, DB = 1
N0.C2.D0.R1.S03: TxDqs: plus1 = 1, minus1 = 0, PI = 08, DB = 1
N2.C3.D1.R0.S16: TxDqs: plus1 = 1, minus1 = 0, PI = 25, DB = 0
N4.C2.D1.R0.S11: TxDq : plus1 = 1, minus1 = 0, PI = 59, DB = 1
N6.C2.D0.R1.S07: TxDq : plus1 = 1, minus1 = 0, PI = 41, DB = 0
N0.C2.D0.R1.S03: TxDq : plus1 = 1, minus1 = 0, PI = 38, DB = 0
N2.C3.D1.R0.S16: TxDq : plus1 = 1, minus1 = 0, PI = 56, DB = 1
N4.C2.D1.R0.S12: TxDqs: plus1 = 1, minus1 = 0, PI = 14, DB = 1
N6.C2.D0.R1.S08: TxDqs: plus1 = 1, minus1 = 0, PI = 44, DB = 0
N0.C2.D0.R1.S04: TxDqs: plus1 = 1, minus1 = 0, PI = 33, DB = 0
N2.C3.D1.R0.S17: TxDqs: plus1 = 1, minus1 = 0, PI = 61, DB = 1
N4.C2.D1.R0.S12: TxDq : plus1 = 1, minus1 = 0, PI = 43, DB = 0
N6.C2.D0.R1.S08: TxDq : plus1 = 1, minus1 = 0, PI = 11, DB = 1
N0.C2.D0.R1.S04: TxDq : plus1 = 0, minus1 = 1, PI = 01, DB = 1
N2.C3.D1.R0.S17: TxDq : plus1 = 1, minus1 = 0, PI = 27, DB = 0
N4.C2.D1.R0.S13: TxDqs: plus1 = 1, minus1 = 0, PI = 36, DB = 0
N6.C2.D0.R1.S09: TxDqs: plus1 = 1, minus1 = 0, PI = 43, DB = 0
N0.C2.D0.R1.S05: TxDqs: plus1 = 1, minus1 = 0, PI = 62, DB = 1
N2.C3.D1.R1.S00: TxDqs: plus1 = 1, minus1 = 0, PI = 59, DB = 1
N4.C2.D1.R0.S13: TxDq : plus1 = 0, minus1 = 1, PI = 02, DB = 1
N6.C2.D0.R1.S09: TxDq : plus1 = 1, minus1 = 0, PI = 10, DB = 1
N0.C2.D0.R1.S05: TxDq : plus1 = 1, minus1 = 0, PI = 27, DB = 0
N2.C3.D1.R1.S00: TxDq : plus1 = 1, minus1 = 0, PI = 26, DB = 0
N4.C2.D1.R0.S14: TxDqs: plus1 = 1, minus1 = 0, PI = 63, DB = 1
N6.C2.D0.R1.S10: TxDqs: plus1 = 1, minus1 = 0, PI = 29, DB = 0
N0.C2.D0.R1.S06: TxDqs: plus1 = 1, minus1 = 0, PI = 59, DB = 1
N2.C3.D1.R1.S01: TxDqs: plus1 = 1, minus1 = 0, PI = 41, DB = 0
N4.C2.D1.R0.S14: TxDq : plus1 = 1, minus1 = 0, PI = 30, DB = 0
N6.C2.D0.R1.S10: TxDq : plus1 = 1, minus1 = 0, PI = 61, DB = 1
N0.C2.D0.R1.S06: TxDq : plus1 = 1, minus1 = 0, PI = 27, DB = 0
N2.C3.D1.R1.S01: TxDq : plus1 = 1, minus1 = 0, PI = 09, DB = 1
N4.C2.D1.R0.S15: TxDqs: plus1 = 0, minus1 = 1, PI = 00, DB = 1
N6.C2.D0.R1.S11: TxDqs: plus1 = 1, minus1 = 0, PI = 21, DB = 0
N0.C2.D0.R1.S07: TxDqs: plus1 = 1, minus1 = 0, PI = 16, DB = 0
N2.C3.D1.R1.S02: TxDqs: plus1 = 1, minus1 = 0, PI = 33, DB = 0
N4.C2.D1.R0.S15: TxDq : plus1 = 1, minus1 = 0, PI = 30, DB = 0
N6.C2.D0.R1.S11: TxDq : plus1 = 1, minus1 = 0, PI = 54, DB = 1
N0.C2.D0.R1.S07: TxDq : plus1 = 1, minus1 = 0, PI = 45, DB = 0
N2.C3.D1.R1.S02: TxDq : plus1 = 0, minus1 = 1, PI = 00, DB = 1
N4.C2.D1.R0.S16: TxDqs: plus1 = 1, minus1 = 0, PI = 19, DB = 0
N6.C2.D0.R1.S12: TxDqs: plus1 = 1, minus1 = 0, PI = 02, DB = 1
N0.C2.D0.R1.S08: TxDqs: plus1 = 1, minus1 = 0, PI = 52, DB = 1
N2.C3.D1.R1.S03: TxDqs: plus1 = 1, minus1 = 0, PI = 16, DB = 0
N4.C2.D1.R0.S16: TxDq : plus1 = 1, minus1 = 0, PI = 48, DB = 0
N6.C2.D0.R1.S12: TxDq : plus1 = 1, minus1 = 0, PI = 33, DB = 0
N0.C2.D0.R1.S08: TxDq : plus1 = 1, minus1 = 0, PI = 18, DB = 0
N2.C3.D1.R1.S03: TxDq : plus1 = 1, minus1 = 0, PI = 47, DB = 0
N4.C2.D1.R0.S17: TxDqs: plus1 = 1, minus1 = 0, PI = 50, DB = 1
N6.C2.D0.R1.S13: TxDqs: plus1 = 1, minus1 = 0, PI = 25, DB = 0
N0.C2.D0.R1.S09: TxDqs: plus1 = 1, minus1 = 0, PI = 51, DB = 1
N2.C3.D1.R1.S04: TxDqs: plus1 = 1, minus1 = 0, PI = 45, DB = 0
N4.C2.D1.R0.S17: TxDq : plus1 = 1, minus1 = 0, PI = 15, DB = 1
N6.C2.D0.R1.S13: TxDq : plus1 = 1, minus1 = 0, PI = 58, DB = 1
N0.C2.D0.R1.S09: TxDq : plus1 = 1, minus1 = 0, PI = 18, DB = 0
N2.C3.D1.R1.S04: TxDq : plus1 = 1, minus1 = 0, PI = 12, DB = 1
N4.C2.D1.R1.S00: TxDqs: plus1 = 1, minus1 = 0, PI = 53, DB = 1
N6.C2.D0.R1.S14: TxDqs: plus1 = 1, minus1 = 0, PI = 54, DB = 1
N0.C2.D0.R1.S10: TxDqs: plus1 = 1, minus1 = 0, PI = 37, DB = 0
N2.C3.D1.R1.S05: TxDqs: plus1 = 1, minus1 = 0, PI = 59, DB = 1
N4.C2.D1.R1.S00: TxDq : plus1 = 1, minus1 = 0, PI = 18, DB = 0
N6.C2.D0.R1.S14: TxDq : plus1 = 1, minus1 = 0, PI = 22, DB = 0
N0.C2.D0.R1.S10: TxDq : plus1 = 1, minus1 = 0, PI = 01, DB = 1
N2.C3.D1.R1.S05: TxDq : plus1 = 1, minus1 = 0, PI = 27, DB = 0
N4.C2.D1.R1.S01: TxDqs: plus1 = 1, minus1 = 0, PI = 39, DB = 0
N6.C2.D0.R1.S15: TxDqs: plus1 = 1, minus1 = 0, PI = 54, DB = 1
N0.C2.D0.R1.S11: TxDqs: plus1 = 1, minus1 = 0, PI = 27, DB = 0
N2.C3.D1.R1.S06: TxDqs: plus1 = 1, minus1 = 0, PI = 08, DB = 1
N4.C2.D1.R1.S01: TxDq : plus1 = 0, minus1 = 1, PI = 04, DB = 1
N6.C2.D0.R1.S15: TxDq : plus1 = 1, minus1 = 0, PI = 23, DB = 0
N0.C2.D0.R1.S11: TxDq : plus1 = 1, minus1 = 0, PI = 58, DB = 1
N2.C3.D1.R1.S06: TxDq : plus1 = 1, minus1 = 0, PI = 39, DB = 0
N4.C2.D1.R1.S02: TxDqs: plus1 = 1, minus1 = 0, PI = 29, DB = 0
N6.C2.D0.R1.S16: TxDqs: plus1 = 1, minus1 = 0, PI = 11, DB = 1
N0.C2.D0.R1.S12: TxDqs: plus1 = 1, minus1 = 0, PI = 08, DB = 1
N2.C3.D1.R1.S07: TxDqs: plus1 = 1, minus1 = 0, PI = 26, DB = 0
N4.C2.D1.R1.S02: TxDq : plus1 = 1, minus1 = 0, PI = 58, DB = 1
N6.C2.D0.R1.S16: TxDq : plus1 = 1, minus1 = 0, PI = 42, DB = 0
N0.C2.D0.R1.S12: TxDq : plus1 = 1, minus1 = 0, PI = 38, DB = 0
N2.C3.D1.R1.S07: TxDq : plus1 = 1, minus1 = 0, PI = 57, DB = 1
N4.C2.D1.R1.S03: TxDqs: plus1 = 1, minus1 = 0, PI = 14, DB = 1
N6.C2.D0.R1.S17: TxDqs: plus1 = 1, minus1 = 0, PI = 44, DB = 0
N0.C2.D0.R1.S13: TxDqs: plus1 = 1, minus1 = 0, PI = 31, DB = 0
N2.C3.D1.R1.S08: TxDqs: plus1 = 1, minus1 = 0, PI = 62, DB = 1
N4.C2.D1.R1.S03: TxDq : plus1 = 1, minus1 = 0, PI = 41, DB = 0
N6.C2.D0.R1.S17: TxDq : plus1 = 1, minus1 = 0, PI = 10, DB = 1
N0.C2.D0.R1.S13: TxDq : plus1 = 1, minus1 = 0, PI = 63, DB = 1
N2.C3.D1.R1.S08: TxDq : plus1 = 1, minus1 = 0, PI = 28, DB = 0
N4.C2.D1.R1.S04: TxDqs: plus1 = 1, minus1 = 0, PI = 35, DB = 0
N6.C2.D1.R0.S00: TxDqs: plus1 = 1, minus1 = 0, PI = 52, DB = 1
N0.C2.D0.R1.S14: TxDqs: plus1 = 1, minus1 = 0, PI = 59, DB = 1
N2.C3.D1.R1.S09: TxDqs: plus1 = 1, minus1 = 0, PI = 58, DB = 1
N4.C2.D1.R1.S04: TxDq : plus1 = 0, minus1 = 1, PI = 04, DB = 1
N6.C2.D1.R0.S00: TxDq : plus1 = 1, minus1 = 0, PI = 20, DB = 0
N0.C2.D0.R1.S14: TxDq : plus1 = 1, minus1 = 0, PI = 28, DB = 0
N2.C3.D1.R1.S09: TxDq : plus1 = 1, minus1 = 0, PI = 23, DB = 0
N4.C2.D1.R1.S05: TxDqs: plus1 = 0, minus1 = 1, PI = 00, DB = 1
N6.C2.D1.R0.S01: TxDqs: plus1 = 1, minus1 = 0, PI = 37, DB = 0
N0.C2.D0.R1.S15: TxDqs: plus1 = 1, minus1 = 0, PI = 59, DB = 1
N2.C3.D1.R1.S10: TxDqs: plus1 = 1, minus1 = 0, PI = 41, DB = 0
N4.C2.D1.R1.S05: TxDq : plus1 = 1, minus1 = 0, PI = 31, DB = 0
N6.C2.D1.R0.S01: TxDq : plus1 = 0, minus1 = 1, PI = 04, DB = 1
N0.C2.D0.R1.S15: TxDq : plus1 = 1, minus1 = 0, PI = 26, DB = 0
N2.C3.D1.R1.S10: TxDq : plus1 = 1, minus1 = 0, PI = 08, DB = 1
N4.C2.D1.R1.S06: TxDqs: plus1 = 1, minus1 = 0, PI = 61, DB = 1
N6.C2.D1.R0.S02: TxDqs: plus1 = 1, minus1 = 0, PI = 30, DB = 0
N0.C2.D0.R1.S16: TxDqs: plus1 = 1, minus1 = 0, PI = 17, DB = 0
N2.C3.D1.R1.S11: TxDqs: plus1 = 1, minus1 = 0, PI = 33, DB = 0
N4.C2.D1.R1.S06: TxDq : plus1 = 1, minus1 = 0, PI = 27, DB = 0
N6.C2.D1.R0.S02: TxDq : plus1 = 1, minus1 = 0, PI = 63, DB = 1
N0.C2.D0.R1.S16: TxDq : plus1 = 1, minus1 = 0, PI = 46, DB = 0
N2.C3.D1.R1.S11: TxDq : plus1 = 0, minus1 = 1, PI = 00, DB = 1
N4.C2.D1.R1.S07: TxDqs: plus1 = 1, minus1 = 0, PI = 19, DB = 0
N6.C2.D1.R0.S03: TxDqs: plus1 = 1, minus1 = 0, PI = 13, DB = 1
N0.C2.D0.R1.S17: TxDqs: plus1 = 1, minus1 = 0, PI = 50, DB = 1
N2.C3.D1.R1.S12: TxDqs: plus1 = 1, minus1 = 0, PI = 17, DB = 0
N4.C2.D1.R1.S07: TxDq : plus1 = 1, minus1 = 0, PI = 48, DB = 0
N6.C2.D1.R0.S03: TxDq : plus1 = 1, minus1 = 0, PI = 44, DB = 0
N0.C2.D0.R1.S17: TxDq : plus1 = 1, minus1 = 0, PI = 16, DB = 0
N2.C3.D1.R1.S12: TxDq : plus1 = 1, minus1 = 0, PI = 48, DB = 0
N4.C2.D1.R1.S08: TxDqs: plus1 = 1, minus1 = 0, PI = 51, DB = 1
N6.C2.D1.R0.S04: TxDqs: plus1 = 1, minus1 = 0, PI = 35, DB = 0
N0.C2.D1.R0.S00: TxDqs: plus1 = 1, minus1 = 0, PI = 53, DB = 1
N2.C3.D1.R1.S13: TxDqs: plus1 = 1, minus1 = 0, PI = 46, DB = 0
N4.C2.D1.R1.S08: TxDq : plus1 = 1, minus1 = 0, PI = 16, DB = 0
N6.C2.D1.R0.S04: TxDq : plus1 = 0, minus1 = 1, PI = 03, DB = 1
N0.C2.D1.R0.S00: TxDq : plus1 = 1, minus1 = 0, PI = 21, DB = 0
N2.C3.D1.R1.S13: TxDq : plus1 = 1, minus1 = 0, PI = 13, DB = 1
N4.C2.D1.R1.S09: TxDqs: plus1 = 1, minus1 = 0, PI = 53, DB = 1
N6.C2.D1.R0.S05: TxDqs: plus1 = 0, minus1 = 1, PI = 01, DB = 1
N0.C2.D1.R0.S01: TxDqs: plus1 = 1, minus1 = 0, PI = 39, DB = 0
N2.C3.D1.R1.S14: TxDqs: plus1 = 1, minus1 = 0, PI = 57, DB = 1
N4.C2.D1.R1.S09: TxDq : plus1 = 1, minus1 = 0, PI = 18, DB = 0
N6.C2.D1.R0.S05: TxDq : plus1 = 1, minus1 = 0, PI = 34, DB = 0
N0.C2.D1.R0.S01: TxDq : plus1 = 1, minus1 = 0, PI = 04, DB = 1
N2.C3.D1.R1.S14: TxDq : plus1 = 1, minus1 = 0, PI = 25, DB = 0
N4.C2.D1.R1.S10: TxDqs: plus1 = 1, minus1 = 0, PI = 40, DB = 0
N6.C2.D1.R0.S06: TxDqs: plus1 = 1, minus1 = 0, PI = 61, DB = 1
N0.C2.D1.R0.S02: TxDqs: plus1 = 1, minus1 = 0, PI = 30, DB = 0
N2.C3.D1.R1.S15: TxDqs: plus1 = 1, minus1 = 0, PI = 08, DB = 1
N4.C2.D1.R1.S10: TxDq : plus1 = 0, minus1 = 1, PI = 03, DB = 1
N6.C2.D1.R0.S06: TxDq : plus1 = 1, minus1 = 0, PI = 30, DB = 0
N0.C2.D1.R0.S02: TxDq : plus1 = 1, minus1 = 0, PI = 61, DB = 1
N2.C3.D1.R1.S15: TxDq : plus1 = 1, minus1 = 0, PI = 40, DB = 0
N4.C2.D1.R1.S11: TxDqs: plus1 = 1, minus1 = 0, PI = 29, DB = 0
N6.C2.D1.R0.S07: TxDqs: plus1 = 1, minus1 = 0, PI = 23, DB = 0
N0.C2.D1.R0.S03: TxDqs: plus1 = 1, minus1 = 0, PI = 14, DB = 1
N2.C3.D1.R1.S16: TxDqs: plus1 = 1, minus1 = 0, PI = 25, DB = 0
N4.C2.D1.R1.S11: TxDq : plus1 = 1, minus1 = 0, PI = 59, DB = 1
N6.C2.D1.R0.S07: TxDq : plus1 = 1, minus1 = 0, PI = 53, DB = 1
N0.C2.D1.R0.S03: TxDq : plus1 = 1, minus1 = 0, PI = 44, DB = 0
N2.C3.D1.R1.S16: TxDq : plus1 = 1, minus1 = 0, PI = 56, DB = 1
N4.C2.D1.R1.S12: TxDqs: plus1 = 1, minus1 = 0, PI = 14, DB = 1
N6.C2.D1.R0.S08: TxDqs: plus1 = 1, minus1 = 0, PI = 50, DB = 1
N0.C2.D1.R0.S04: TxDqs: plus1 = 1, minus1 = 0, PI = 37, DB = 0
N2.C3.D1.R1.S17: TxDqs: plus1 = 1, minus1 = 0, PI = 61, DB = 1
N4.C2.D1.R1.S12: TxDq : plus1 = 1, minus1 = 0, PI = 43, DB = 0
N6.C2.D1.R0.S08: TxDq : plus1 = 1, minus1 = 0, PI = 17, DB = 0
N0.C2.D1.R0.S04: TxDq : plus1 = 0, minus1 = 1, PI = 05, DB = 1
N2.C3.D1.R1.S17: TxDq : plus1 = 1, minus1 = 0, PI = 27, DB = 0
N4.C2.D1.R1.S13: TxDqs: plus1 = 1, minus1 = 0, PI = 36, DB = 0
N6.C2.D1.R0.S09: TxDqs: plus1 = 1, minus1 = 0, PI = 51, DB = 1
N0.C2.D1.R0.S05: TxDqs: plus1 = 0, minus1 = 1, PI = 02, DB = 1
END_DATA_TX_DQ
N4.C2.D1.R1.S13: TxDq : plus1 = 0, minus1 = 1, PI = 02, DB = 1
N6.C2.D1.R0.S09: TxDq : plus1 = 1, minus1 = 0, PI = 17, DB = 0
N0.C2.D1.R0.S05: TxDq : plus1 = 1, minus1 = 0, PI = 32, DB = 0
N2: RunTrainStep: Final status = 0
N4.C2.D1.R1.S14: TxDqs: plus1 = 1, minus1 = 0, PI = 63, DB = 1
N6.C2.D1.R0.S10: TxDqs: plus1 = 1, minus1 = 0, PI = 38, DB = 0
N0.C2.D1.R0.S06: TxDqs: plus1 = 1, minus1 = 0, PI = 62, DB = 1

END - Basic Write DQ/DQS Training      Time         51820 ms
N4.C2.D1.R1.S14: TxDq : plus1 = 1, minus1 = 0, PI = 30, DB = 0
N6.C2.D1.R0.S10: TxDq : plus1 = 0, minus1 = 1, PI = 04, DB = 1
N0.C2.D1.R0.S06: TxDq : plus1 = 1, minus1 = 0, PI = 28, DB = 0
N2.C0: JCK cmd timing = 1N
N4.C2.D1.R1.S15: TxDqs: plus1 = 0, minus1 = 1, PI = 00, DB = 1
N6.C2.D1.R0.S11: TxDqs: plus1 = 1, minus1 = 0, PI = 31, DB = 0
N0.C2.D1.R0.S07: TxDqs: plus1 = 1, minus1 = 0, PI = 20, DB = 0
N2.C0: RdCmd2DataValidLatency = 21, (dlyFrmS = 15, clEff = 10, earlyCas = 0, selNTiming = 0)
N4.C2.D1.R1.S15: TxDq : plus1 = 1, minus1 = 0, PI = 30, DB = 0
N6.C2.D1.R0.S11: TxDq : plus1 = 1, minus1 = 0, PI = 63, DB = 1
N0.C2.D1.R0.S07: TxDq : plus1 = 1, minus1 = 0, PI = 49, DB = 1
N2.C1: RdCmd2DataValidLatency = 21, (dlyFrmS = 15, clEff = 10, earlyCas = 0, selNTiming = 0)
N4.C2.D1.R1.S16: TxDqs: plus1 = 1, minus1 = 0, PI = 19, DB = 0
N6.C2.D1.R0.S12: TxDqs: plus1 = 1, minus1 = 0, PI = 15, DB = 1
N0.C2.D1.R0.S08: TxDqs: plus1 = 1, minus1 = 0, PI = 51, DB = 1
N2.C2: JCK cmd timing = 1N
N4.C2.D1.R1.S16: TxDq : plus1 = 1, minus1 = 0, PI = 48, DB = 0
N6.C2.D1.R0.S12: TxDq : plus1 = 1, minus1 = 0, PI = 45, DB = 0
N0.C2.D1.R0.S08: TxDq : plus1 = 1, minus1 = 0, PI = 17, DB = 0
N2.C2: RdCmd2DataValidLatency = 21, (dlyFrmS = 15, clEff = 10, earlyCas = 0, selNTiming = 0)
N4.C2.D1.R1.S17: TxDqs: plus1 = 1, minus1 = 0, PI = 50, DB = 1
N6.C2.D1.R0.S13: TxDqs: plus1 = 1, minus1 = 0, PI = 36, DB = 0
N0.C2.D1.R0.S09: TxDqs: plus1 = 1, minus1 = 0, PI = 52, DB = 1
N2.C3: RdCmd2DataValidLatency = 21, (dlyFrmS = 15, clEff = 10, earlyCas = 0, selNTiming = 0)
N4.C2.D1.R1.S17: TxDq : plus1 = 1, minus1 = 0, PI = 15, DB = 1
N6.C2.D1.R0.S13: TxDq : plus1 = 0, minus1 = 1, PI = 03, DB = 1
N0.C2.D1.R0.S09: TxDq : plus1 = 1, minus1 = 0, PI = 18, DB = 0
N2: JckSetOdtDynTiming[2] BL8:
END_DATA_TX_DQ
N6.C2.D1.R0.S14: TxDqs: plus1 = 0, minus1 = 1, PI = 00, DB = 1
N0.C2.D1.R0.S10: TxDqs: plus1 = 1, minus1 = 0, PI = 41, DB = 0
N4.C3.D0.R0.S00: wrcmd2dqsstartlatency: 04
N6.C2.D1.R0.S14: TxDq : plus1 = 1, minus1 = 0, PI = 31, DB = 0
N0.C2.D1.R0.S10: TxDq : plus1 = 1, minus1 = 0, PI = 05, DB = 1
N2.C0: minRcvEnDelay = 208 maxRcvEnDelay = 304 ==> rdwidth = 6 rddly = 2 wrwidth = 6 wrdly = 0
N4.C3.D0.R0.S00: RdPtrOffsetTxDq: 06
N6.C2.D1.R0.S15: TxDqs: plus1 = 1, minus1 = 0, PI = 63, DB = 1
N0.C2.D1.R0.S11: TxDqs: plus1 = 1, minus1 = 0, PI = 31, DB = 0
N2.C1: minRcvEnDelay = 200 maxRcvEnDelay = 332 ==> rdwidth = 6 rddly = 2 wrwidth = 6 wrdly = 0
N4.C3.D0.R0.S00: RdPtrOffsetTxDqs: 08
N6.C2.D1.R0.S15: TxDq : plus1 = 1, minus1 = 0, PI = 30, DB = 0
N0.C2.D1.R0.S11: TxDq : plus1 = 1, minus1 = 0, PI = 61, DB = 1
N2.C2: minRcvEnDelay = 203 maxRcvEnDelay = 306 ==> rdwidth = 6 rddly = 2 wrwidth = 6 wrdly = 0
N4.C3.D0.R0.S00: PiTxDqs: 01
N6.C2.D1.R0.S16: TxDqs: plus1 = 1, minus1 = 0, PI = 22, DB = 0
N0.C2.D1.R0.S12: TxDqs: plus1 = 1, minus1 = 0, PI = 14, DB = 1
N2.C3: minRcvEnDelay = 202 maxRcvEnDelay = 328 ==> rdwidth = 6 rddly = 2 wrwidth = 6 wrdly = 0
N4.C3.D0.R0.S01: wrcmd2dqsstartlatency: 04
N6.C2.D1.R0.S16: TxDq : plus1 = 1, minus1 = 0, PI = 52, DB = 1
N0.C2.D1.R0.S12: TxDq : plus1 = 1, minus1 = 0, PI = 43, DB = 0
N2.C0: Memory Electrical TurnAround timings:
N4.C3.D0.R0.S01: RdPtrOffsetTxDq: 06
N6.C2.D1.R0.S17: TxDqs: plus1 = 1, minus1 = 0, PI = 51, DB = 1
N0.C2.D1.R0.S13: TxDqs: plus1 = 1, minus1 = 0, PI = 38, DB = 0
N2.C0:      tCCD  =  0, tWWDR =  3, tRRDD =  2, tWWDD =  3, tWRDR =  1, tWRDR_UPPER =  0, tRRDR =  0
N4.C3.D0.R0.S01: RdPtrOffsetTxDqs: 07
N6.C2.D1.R0.S17: TxDq : plus1 = 1, minus1 = 0, PI = 16, DB = 0
N0.C2.D1.R0.S13: TxDq : plus1 = 0, minus1 = 1, PI = 05, DB = 1
N2.C0:      tRWDD =  2, tRWDR =  2, tWRDD =  1, tRWSR =  2
N4.C3.D0.R0.S01: PiTxDqs: 46
N6.C2.D1.R1.S00: TxDqs: plus1 = 1, minus1 = 0, PI = 52, DB = 1
N0.C2.D1.R0.S14: TxDqs: plus1 = 0, minus1 = 1, PI = 00, DB = 1
N2.C0: TCOTHP: T_RWSR = 0x2, T_RWDD = 0x2
N4.C3.D0.R0.S02: wrcmd2dqsstartlatency: 04
N6.C2.D1.R1.S00: TxDq : plus1 = 1, minus1 = 0, PI = 20, DB = 0
N0.C2.D1.R0.S14: TxDq : plus1 = 1, minus1 = 0, PI = 32, DB = 0
N2.C0:      tCCD_WR =  0, tWRDS =  2, tRWDS =  2, tWWDS =  3, tRRDS =  1
N4.C3.D0.R0.S02: RdPtrOffsetTxDq: 06
N6.C2.D1.R1.S01: TxDqs: plus1 = 1, minus1 = 0, PI = 37, DB = 0
N0.C2.D1.R0.S15: TxDqs: plus1 = 0, minus1 = 1, PI = 00, DB = 1
N2.C1: Memory Electrical TurnAround timings:
N4.C3.D0.R0.S02: RdPtrOffsetTxDqs: 07
N6.C2.D1.R1.S01: TxDq : plus1 = 0, minus1 = 1, PI = 04, DB = 1
N0.C2.D1.R0.S15: TxDq : plus1 = 1, minus1 = 0, PI = 30, DB = 0
N2.C1:      tCCD  =  0, tWWDR =  3, tRRDD =  2, tWWDD =  3, tWRDR =  1, tWRDR_UPPER =  0, tRRDR =  0
N4.C3.D0.R0.S02: PiTxDqs: 39
N6.C2.D1.R1.S02: TxDqs: plus1 = 1, minus1 = 0, PI = 30, DB = 0
N0.C2.D1.R0.S16: TxDqs: plus1 = 1, minus1 = 0, PI = 22, DB = 0
N2.C1:      tRWDD =  2, tRWDR =  2, tWRDD =  1, tRWSR =  2
N4.C3.D0.R0.S03: wrcmd2dqsstartlatency: 04
N6.C2.D1.R1.S02: TxDq : plus1 = 1, minus1 = 0, PI = 63, DB = 1
N0.C2.D1.R0.S16: TxDq : plus1 = 1, minus1 = 0, PI = 49, DB = 1
N2.C1: TCOTHP: T_RWSR = 0x2, T_RWDD = 0x2
N4.C3.D0.R0.S03: RdPtrOffsetTxDq: 05
N6.C2.D1.R1.S03: TxDqs: plus1 = 1, minus1 = 0, PI = 13, DB = 1
N0.C2.D1.R0.S17: TxDqs: plus1 = 1, minus1 = 0, PI = 52, DB = 1
N2.C1:      tCCD_WR =  0, tWRDS =  2, tRWDS =  2, tWWDS =  3, tRRDS =  1
N4.C3.D0.R0.S03: RdPtrOffsetTxDqs: 07
N6.C2.D1.R1.S03: TxDq : plus1 = 1, minus1 = 0, PI = 44, DB = 0
N0.C2.D1.R0.S17: TxDq : plus1 = 1, minus1 = 0, PI = 17, DB = 0
N2.C2: Memory Electrical TurnAround timings:
N4.C3.D0.R0.S03: PiTxDqs: 21
N6.C2.D1.R1.S04: TxDqs: plus1 = 1, minus1 = 0, PI = 35, DB = 0
N0.C2.D1.R1.S00: TxDqs: plus1 = 1, minus1 = 0, PI = 53, DB = 1
N2.C2:      tCCD  =  0, tWWDR =  3, tRRDD =  2, tWWDD =  3, tWRDR =  1, tWRDR_UPPER =  0, tRRDR =  0
N4.C3.D0.R0.S04: wrcmd2dqsstartlatency: 04
N6.C2.D1.R1.S04: TxDq : plus1 = 0, minus1 = 1, PI = 03, DB = 1
N0.C2.D1.R1.S00: TxDq : plus1 = 1, minus1 = 0, PI = 21, DB = 0
N2.C2:      tRWDD =  2, tRWDR =  2, tWRDD =  1, tRWSR =  2
N4.C3.D0.R0.S04: RdPtrOffsetTxDq: 05
N6.C2.D1.R1.S05: TxDqs: plus1 = 0, minus1 = 1, PI = 01, DB = 1
N0.C2.D1.R1.S01: TxDqs: plus1 = 1, minus1 = 0, PI = 39, DB = 0
N2.C2: TCOTHP: T_RWSR = 0x2, T_RWDD = 0x2
N4.C3.D0.R0.S04: RdPtrOffsetTxDqs: 06
N6.C2.D1.R1.S05: TxDq : plus1 = 1, minus1 = 0, PI = 34, DB = 0
N0.C2.D1.R1.S01: TxDq : plus1 = 1, minus1 = 0, PI = 04, DB = 1
N2.C2:      tCCD_WR =  0, tWRDS =  2, tRWDS =  2, tWWDS =  3, tRRDS =  1
N4.C3.D0.R0.S04: PiTxDqs: 49
N6.C2.D1.R1.S06: TxDqs: plus1 = 1, minus1 = 0, PI = 61, DB = 1
N0.C2.D1.R1.S02: TxDqs: plus1 = 1, minus1 = 0, PI = 30, DB = 0
N2.C3: Memory Electrical TurnAround timings:
N4.C3.D0.R0.S05: wrcmd2dqsstartlatency: 04
N6.C2.D1.R1.S06: TxDq : plus1 = 1, minus1 = 0, PI = 30, DB = 0
N0.C2.D1.R1.S02: TxDq : plus1 = 1, minus1 = 0, PI = 61, DB = 1
N2.C3:      tCCD  =  0, tWWDR =  3, tRRDD =  2, tWWDD =  3, tWRDR =  1, tWRDR_UPPER =  0, tRRDR =  0
N4.C3.D0.R0.S05: RdPtrOffsetTxDq: 05
N6.C2.D1.R1.S07: TxDqs: plus1 = 1, minus1 = 0, PI = 23, DB = 0
N0.C2.D1.R1.S03: TxDqs: plus1 = 1, minus1 = 0, PI = 14, DB = 1
N2.C3:      tRWDD =  2, tRWDR =  2, tWRDD =  1, tRWSR =  2
N4.C3.D0.R0.S05: RdPtrOffsetTxDqs: 06
N6.C2.D1.R1.S07: TxDq : plus1 = 1, minus1 = 0, PI = 53, DB = 1
N0.C2.D1.R1.S03: TxDq : plus1 = 1, minus1 = 0, PI = 44, DB = 0
N2.C3: TCOTHP: T_RWSR = 0x2, T_RWDD = 0x2
N4.C3.D0.R0.S05: PiTxDqs: 63
N6.C2.D1.R1.S08: TxDqs: plus1 = 1, minus1 = 0, PI = 50, DB = 1
N0.C2.D1.R1.S04: TxDqs: plus1 = 1, minus1 = 0, PI = 37, DB = 0
N2.C3:      tCCD_WR =  0, tWRDS =  2, tRWDS =  2, tWWDS =  3, tRRDS =  1
N4.C3.D0.R0.S06: wrcmd2dqsstartlatency: 04
N6.C2.D1.R1.S08: TxDq : plus1 = 1, minus1 = 0, PI = 17, DB = 0
N0.C2.D1.R1.S04: TxDq : plus1 = 0, minus1 = 1, PI = 05, DB = 1

START - Rd Timing Centering 2D Training
N4.C3.D0.R0.S06: RdPtrOffsetTxDq: 05
N6.C2.D1.R1.S09: TxDqs: plus1 = 1, minus1 = 0, PI = 51, DB = 1
N0.C2.D1.R1.S05: TxDqs: plus1 = 0, minus1 = 1, PI = 02, DB = 1
N2: 

Adv Strobe Centering(MARGIN_RX_DQ): GetMultiVref: patternLength = 13, stepSize = 1, numPoints = 1
N4.C3.D0.R0.S06: RdPtrOffsetTxDqs: 07
N6.C2.D1.R1.S09: TxDq : plus1 = 1, minus1 = 0, PI = 17, DB = 0
N0.C2.D1.R1.S05: TxDq : plus1 = 1, minus1 = 0, PI = 32, DB = 0
N2: GetMargins: Level = 1, group = 11, mode = 0, scope = 4
N4.C3.D0.R0.S06: PiTxDqs: 13
N6.C2.D1.R1.S10: TxDqs: plus1 = 1, minus1 = 0, PI = 38, DB = 0
N0.C2.D1.R1.S06: TxDqs: plus1 = 1, minus1 = 0, PI = 62, DB = 1
N4.C3.D0.R0.S07: wrcmd2dqsstartlatency: 04
N6.C2.D1.R1.S10: TxDq : plus1 = 0, minus1 = 1, PI = 04, DB = 1
N0.C2.D1.R1.S06: TxDq : plus1 = 1, minus1 = 0, PI = 28, DB = 0
N4.C3.D0.R0.S07: RdPtrOffsetTxDq: 05
N6.C2.D1.R1.S11: TxDqs: plus1 = 1, minus1 = 0, PI = 31, DB = 0
N0.C2.D1.R1.S07: TxDqs: plus1 = 1, minus1 = 0, PI = 20, DB = 0
N4.C3.D0.R0.S07: RdPtrOffsetTxDqs: 07
N6.C2.D1.R1.S11: TxDq : plus1 = 1, minus1 = 0, PI = 63, DB = 1
N0.C2.D1.R1.S07: TxDq : plus1 = 1, minus1 = 0, PI = 49, DB = 1
N4.C3.D0.R0.S07: PiTxDqs: 31
N6.C2.D1.R1.S12: TxDqs: plus1 = 1, minus1 = 0, PI = 15, DB = 1
N0.C2.D1.R1.S08: TxDqs: plus1 = 1, minus1 = 0, PI = 51, DB = 1
N4.C3.D0.R0.S08: wrcmd2dqsstartlatency: 04
N6.C2.D1.R1.S12: TxDq : plus1 = 1, minus1 = 0, PI = 45, DB = 0
N0.C2.D1.R1.S08: TxDq : plus1 = 1, minus1 = 0, PI = 17, DB = 0
N4.C3.D0.R0.S08: RdPtrOffsetTxDq: 05
N6.C2.D1.R1.S13: TxDqs: plus1 = 1, minus1 = 0, PI = 36, DB = 0
N0.C2.D1.R1.S09: TxDqs: plus1 = 1, minus1 = 0, PI = 52, DB = 1
N4.C3.D0.R0.S08: RdPtrOffsetTxDqs: 07
N6.C2.D1.R1.S13: TxDq : plus1 = 0, minus1 = 1, PI = 03, DB = 1
N0.C2.D1.R1.S09: TxDq : plus1 = 1, minus1 = 0, PI = 18, DB = 0
N4.C3.D0.R0.S08: PiTxDqs: 04
N6.C2.D1.R1.S14: TxDqs: plus1 = 0, minus1 = 1, PI = 00, DB = 1
N0.C2.D1.R1.S10: TxDqs: plus1 = 1, minus1 = 0, PI = 41, DB = 0
N4.C3.D0.R0.S09: wrcmd2dqsstartlatency: 04
N6.C2.D1.R1.S14: TxDq : plus1 = 1, minus1 = 0, PI = 31, DB = 0
N0.C2.D1.R1.S10: TxDq : plus1 = 1, minus1 = 0, PI = 05, DB = 1
N4.C3.D0.R0.S09: RdPtrOffsetTxDq: 06
N6.C2.D1.R1.S15: TxDqs: plus1 = 1, minus1 = 0, PI = 63, DB = 1
N0.C2.D1.R1.S11: TxDqs: plus1 = 1, minus1 = 0, PI = 31, DB = 0
N4.C3.D0.R0.S09: RdPtrOffsetTxDqs: 08
N6.C2.D1.R1.S15: TxDq : plus1 = 1, minus1 = 0, PI = 30, DB = 0
N0.C2.D1.R1.S11: TxDq : plus1 = 1, minus1 = 0, PI = 61, DB = 1
N4.C3.D0.R0.S09: PiTxDqs: 00
N6.C2.D1.R1.S16: TxDqs: plus1 = 1, minus1 = 0, PI = 22, DB = 0
N0.C2.D1.R1.S12: TxDqs: plus1 = 1, minus1 = 0, PI = 14, DB = 1
N4.C3.D0.R0.S10: wrcmd2dqsstartlatency: 04
N6.C2.D1.R1.S16: TxDq : plus1 = 1, minus1 = 0, PI = 52, DB = 1
N0.C2.D1.R1.S12: TxDq : plus1 = 1, minus1 = 0, PI = 43, DB = 0
N4.C3.D0.R0.S10: RdPtrOffsetTxDq: 06
N6.C2.D1.R1.S17: TxDqs: plus1 = 1, minus1 = 0, PI = 51, DB = 1
N0.C2.D1.R1.S13: TxDqs: plus1 = 1, minus1 = 0, PI = 38, DB = 0
N4.C3.D0.R0.S10: RdPtrOffsetTxDqs: 07
N6.C2.D1.R1.S17: TxDq : plus1 = 1, minus1 = 0, PI = 16, DB = 0
N0.C2.D1.R1.S13: TxDq : plus1 = 0, minus1 = 1, PI = 05, DB = 1
N4.C3.D0.R0.S10: PiTxDqs: 45
END_DATA_TX_DQ
N0.C2.D1.R1.S14: TxDqs: plus1 = 0, minus1 = 1, PI = 00, DB = 1
N4.C3.D0.R0.S11: wrcmd2dqsstartlatency: 04
N6.C3.D0.R0.S00: wrcmd2dqsstartlatency: 04
N0.C2.D1.R1.S14: TxDq : plus1 = 1, minus1 = 0, PI = 32, DB = 0
N4.C3.D0.R0.S11: RdPtrOffsetTxDq: 06
N6.C3.D0.R0.S00: RdPtrOffsetTxDq: 06
N0.C2.D1.R1.S15: TxDqs: plus1 = 0, minus1 = 1, PI = 00, DB = 1
N4.C3.D0.R0.S11: RdPtrOffsetTxDqs: 07
N6.C3.D0.R0.S00: RdPtrOffsetTxDqs: 07
N0.C2.D1.R1.S15: TxDq : plus1 = 1, minus1 = 0, PI = 30, DB = 0
N4.C3.D0.R0.S11: PiTxDqs: 37
N6.C3.D0.R0.S00: PiTxDqs: 58
N0.C2.D1.R1.S16: TxDqs: plus1 = 1, minus1 = 0, PI = 22, DB = 0
N4.C3.D0.R0.S12: wrcmd2dqsstartlatency: 04
N6.C3.D0.R0.S01: wrcmd2dqsstartlatency: 04
N0.C2.D1.R1.S16: TxDq : plus1 = 1, minus1 = 0, PI = 49, DB = 1
N4.C3.D0.R0.S12: RdPtrOffsetTxDq: 05
N6.C3.D0.R0.S01: RdPtrOffsetTxDq: 06
N0.C2.D1.R1.S17: TxDqs: plus1 = 1, minus1 = 0, PI = 52, DB = 1
N4.C3.D0.R0.S12: RdPtrOffsetTxDqs: 07
N6.C3.D0.R0.S01: RdPtrOffsetTxDqs: 07
N0.C2.D1.R1.S17: TxDq : plus1 = 1, minus1 = 0, PI = 17, DB = 0
N4.C3.D0.R0.S12: PiTxDqs: 22
N6.C3.D0.R0.S01: PiTxDqs: 42
END_DATA_TX_DQ
N4.C3.D0.R0.S13: wrcmd2dqsstartlatency: 04
N6.C3.D0.R0.S02: wrcmd2dqsstartlatency: 04
N0.C3.D0.R0.S00: wrcmd2dqsstartlatency: 04
N4.C3.D0.R0.S13: RdPtrOffsetTxDq: 05
N6.C3.D0.R0.S02: RdPtrOffsetTxDq: 06
N0.C3.D0.R0.S00: RdPtrOffsetTxDq: 06
N4.C3.D0.R0.S13: RdPtrOffsetTxDqs: 06
N6.C3.D0.R0.S02: RdPtrOffsetTxDqs: 07
N0.C3.D0.R0.S00: RdPtrOffsetTxDqs: 08
N4.C3.D0.R0.S13: PiTxDqs: 49
N6.C3.D0.R0.S02: PiTxDqs: 35
N0.C3.D0.R0.S00: PiTxDqs: 02
N4.C3.D0.R0.S14: wrcmd2dqsstartlatency: 04
N6.C3.D0.R0.S03: wrcmd2dqsstartlatency: 04
N0.C3.D0.R0.S01: wrcmd2dqsstartlatency: 04
N4.C3.D0.R0.S14: RdPtrOffsetTxDq: 05
N6.C3.D0.R0.S03: RdPtrOffsetTxDq: 05
N0.C3.D0.R0.S01: RdPtrOffsetTxDq: 06
N4.C3.D0.R0.S14: RdPtrOffsetTxDqs: 06
N6.C3.D0.R0.S03: RdPtrOffsetTxDqs: 07
N0.C3.D0.R0.S01: RdPtrOffsetTxDqs: 07
N4.C3.D0.R0.S14: PiTxDqs: 62
N6.C3.D0.R0.S03: PiTxDqs: 18
N0.C3.D0.R0.S01: PiTxDqs: 49
N4.C3.D0.R0.S15: wrcmd2dqsstartlatency: 04
N6.C3.D0.R0.S04: wrcmd2dqsstartlatency: 04
N0.C3.D0.R0.S02: wrcmd2dqsstartlatency: 04
N4.C3.D0.R0.S15: RdPtrOffsetTxDq: 05
N6.C3.D0.R0.S04: RdPtrOffsetTxDq: 05
N0.C3.D0.R0.S02: RdPtrOffsetTxDq: 06
N4.C3.D0.R0.S15: RdPtrOffsetTxDqs: 07
N6.C3.D0.R0.S04: RdPtrOffsetTxDqs: 06
N0.C3.D0.R0.S02: RdPtrOffsetTxDqs: 07
N4.C3.D0.R0.S15: PiTxDqs: 15
N6.C3.D0.R0.S04: PiTxDqs: 45
N0.C3.D0.R0.S02: PiTxDqs: 38
N4.C3.D0.R0.S16: wrcmd2dqsstartlatency: 04
N6.C3.D0.R0.S05: wrcmd2dqsstartlatency: 04
N0.C3.D0.R0.S03: wrcmd2dqsstartlatency: 04
N4.C3.D0.R0.S16: RdPtrOffsetTxDq: 05
N6.C3.D0.R0.S05: RdPtrOffsetTxDq: 05
N0.C3.D0.R0.S03: RdPtrOffsetTxDq: 05
N4.C3.D0.R0.S16: RdPtrOffsetTxDqs: 07
N6.C3.D0.R0.S05: RdPtrOffsetTxDqs: 06
N0.C3.D0.R0.S03: RdPtrOffsetTxDqs: 07
N4.C3.D0.R0.S16: PiTxDqs: 30
N6.C3.D0.R0.S05: PiTxDqs: 58
N0.C3.D0.R0.S03: PiTxDqs: 19
N4.C3.D0.R0.S17: wrcmd2dqsstartlatency: 04
N6.C3.D0.R0.S06: wrcmd2dqsstartlatency: 04
N0.C3.D0.R0.S04: wrcmd2dqsstartlatency: 04
N4.C3.D0.R0.S17: RdPtrOffsetTxDq: 05
N6.C3.D0.R0.S06: RdPtrOffsetTxDq: 05
N0.C3.D0.R0.S04: RdPtrOffsetTxDq: 05
N4.C3.D0.R0.S17: RdPtrOffsetTxDqs: 07
N6.C3.D0.R0.S06: RdPtrOffsetTxDqs: 07
N0.C3.D0.R0.S04: RdPtrOffsetTxDqs: 06
N4.C3.D0.R0.S17: PiTxDqs: 02
N6.C3.D0.R0.S06: PiTxDqs: 10
N0.C3.D0.R0.S04: PiTxDqs: 52
N4.C3.D0.R0.S00: RdPtrOffsetTxDq: 07
N6.C3.D0.R0.S07: wrcmd2dqsstartlatency: 04
N0.C3.D0.R0.S05: wrcmd2dqsstartlatency: 04
N4.C3.D0.R0.S01: RdPtrOffsetTxDq: 07
N6.C3.D0.R0.S07: RdPtrOffsetTxDq: 05
N0.C3.D0.R0.S05: RdPtrOffsetTxDq: 05
N4.C3.D0.R0.S02: RdPtrOffsetTxDq: 07
N6.C3.D0.R0.S07: RdPtrOffsetTxDqs: 07
N0.C3.D0.R0.S05: RdPtrOffsetTxDqs: 07
N4.C3.D0.R0.S03: RdPtrOffsetTxDq: 06
N6.C3.D0.R0.S07: PiTxDqs: 26
N0.C3.D0.R0.S05: PiTxDqs: 01
N4.C3.D0.R0.S04: RdPtrOffsetTxDq: 06
N6.C3.D0.R0.S08: wrcmd2dqsstartlatency: 04
N0.C3.D0.R0.S06: wrcmd2dqsstartlatency: 04
N4.C3.D0.R0.S05: RdPtrOffsetTxDq: 06
N6.C3.D0.R0.S08: RdPtrOffsetTxDq: 05
N0.C3.D0.R0.S06: RdPtrOffsetTxDq: 05
N4.C3.D0.R0.S06: RdPtrOffsetTxDq: 06
N6.C3.D0.R0.S08: RdPtrOffsetTxDqs: 07
N0.C3.D0.R0.S06: RdPtrOffsetTxDqs: 07
N4.C3.D0.R0.S07: RdPtrOffsetTxDq: 06
N6.C3.D0.R0.S08: PiTxDqs: 00
N0.C3.D0.R0.S06: PiTxDqs: 16
N4.C3.D0.R0.S08: RdPtrOffsetTxDq: 06
N6.C3.D0.R0.S09: wrcmd2dqsstartlatency: 04
N0.C3.D0.R0.S07: wrcmd2dqsstartlatency: 04
N4.C3.D0.R0.S09: RdPtrOffsetTxDq: 07
N6.C3.D0.R0.S09: RdPtrOffsetTxDq: 06
N0.C3.D0.R0.S07: RdPtrOffsetTxDq: 06
N4.C3.D0.R0.S10: RdPtrOffsetTxDq: 07
N6.C3.D0.R0.S09: RdPtrOffsetTxDqs: 07
N0.C3.D0.R0.S07: RdPtrOffsetTxDqs: 07
N4.C3.D0.R0.S11: RdPtrOffsetTxDq: 07
N6.C3.D0.R0.S09: PiTxDqs: 59
N0.C3.D0.R0.S07: PiTxDqs: 34
N4.C3.D0.R0.S12: RdPtrOffsetTxDq: 06
N6.C3.D0.R0.S10: wrcmd2dqsstartlatency: 04
N0.C3.D0.R0.S08: wrcmd2dqsstartlatency: 04
N4.C3.D0.R0.S13: RdPtrOffsetTxDq: 06
N6.C3.D0.R0.S10: RdPtrOffsetTxDq: 06
N0.C3.D0.R0.S08: RdPtrOffsetTxDq: 05
N4.C3.D0.R0.S14: RdPtrOffsetTxDq: 06
N6.C3.D0.R0.S10: RdPtrOffsetTxDqs: 07
N0.C3.D0.R0.S08: RdPtrOffsetTxDqs: 07
N4.C3.D0.R0.S15: RdPtrOffsetTxDq: 06
N6.C3.D0.R0.S10: PiTxDqs: 42
N0.C3.D0.R0.S08: PiTxDqs: 03
N4.C3.D0.R0.S16: RdPtrOffsetTxDq: 06
N6.C3.D0.R0.S11: wrcmd2dqsstartlatency: 04
N0.C3.D0.R0.S09: wrcmd2dqsstartlatency: 04
N4.C3.D0.R0.S17: RdPtrOffsetTxDq: 06
N6.C3.D0.R0.S11: RdPtrOffsetTxDq: 06
N0.C3.D0.R0.S09: RdPtrOffsetTxDq: 06
N4.C3.D0.R0.S00: RdPtrOffsetTxDq: 08
N6.C3.D0.R0.S11: RdPtrOffsetTxDqs: 07
N0.C3.D0.R0.S09: RdPtrOffsetTxDqs: 08
N4.C3.D0.R0.S01: RdPtrOffsetTxDq: 08
N6.C3.D0.R0.S11: PiTxDqs: 33
N0.C3.D0.R0.S09: PiTxDqs: 01
N4.C3.D0.R0.S02: RdPtrOffsetTxDq: 08
N6.C3.D0.R0.S12: wrcmd2dqsstartlatency: 04
N0.C3.D0.R0.S10: wrcmd2dqsstartlatency: 04
N4.C3.D0.R0.S03: RdPtrOffsetTxDq: 07
N6.C3.D0.R0.S12: RdPtrOffsetTxDq: 05
N0.C3.D0.R0.S10: RdPtrOffsetTxDq: 06
N4.C3.D0.R0.S04: RdPtrOffsetTxDq: 07
N6.C3.D0.R0.S12: RdPtrOffsetTxDqs: 07
N0.C3.D0.R0.S10: RdPtrOffsetTxDqs: 07
START_DATA_RX_DQS_ADV
Results for N2.C0.D0.R0: 
           0   1   2   3   4   5   6   7   8   9  10  11  12  13  14  15  16  17
-------------------------------------------------------------------------------
Vref offset: 0
Left:    -24 -24 -24 -26 -25 -26 -18 -23 -26 -23 -22 -22 -26 -25 -26 -22 -25 -24
Right:    18  21  25  23  23  25  31  23  22  24  20  21  22  23  22  27  23  20
-------------------------------------------------------------------------------
Prev Pi:  33  33  33  34  34  34  34  34  36  32  33  33  34  33  33  33  34  34
New Pi:   30  32  33  33  33  34  40  34  34  32  32  33  32  32  31  35  33  32
Diff:     -3  -1   0  -1  -1   0   6   0  -2   0  -1   0  -2  -1  -2   2  -1  -2

Results for N2.C0.D0.R1: 
           0   1   2   3   4   5   6   7   8   9  10  11  12  13  14  15  16  17
-------------------------------------------------------------------------------
Vref offset: 0
Left:    -24 -25 -24 -26 -25 -26 -17 -24 -24 -23 -21 -23 -26 -24 -25 -22 -25 -25
Right:    18  23  25  23  25  25  31  24  19  24  18  24  22  25  21  24  22  20
-------------------------------------------------------------------------------
Prev Pi:  33  33  33  34  34  34  34  34  36  32  33  33  34  33  33  33  34  34
New Pi:   30  32  33  33  34  34  41  34  34  32  32  33  32  33  31  34  33  32
Diff:     -3  -1   0  -1   0   0   7   0  -2   0  -1   0  -2   0  -2   1  -1  -2

Results for N2.C0.D1.R0: 
           0   1   2   3   4   5   6   7   8   9  10  11  12  13  14  15  16  17
-------------------------------------------------------------------------------
Vref offset: 0
Left:    -24 -25 -23 -27 -25 -26 -17 -23 -23 -24 -24 -20 -25 -25 -25 -21 -24 -25
Right:    17  20  23  22  23  27  30  23  21  18  15  23  22  22  21  26  24  16
-------------------------------------------------------------------------------
Prev Pi:  35  35  35  36  36  35  36  36  37  35  36  35  35  35  34  35  35  36
New Pi:   32  33  35  34  35  35  42  36  36  32  32  36  34  34  32  37  35  32
Diff:     -3  -2   0  -2  -1   0   6   0  -1  -3  -4   1  -1  -1  -2   2   0  -4

Results for N2.C0.D1.R1: 
           0   1   2   3   4   5   6   7   8   9  10  11  12  13  14  15  16  17
-------------------------------------------------------------------------------
Vref offset: 0
Left:    -24 -25 -24 -27 -25 -26 -17 -23 -23 -24 -23 -20 -25 -25 -25 -21 -24 -25
Right:    17  20  23  22  22  25  29  21  21  19  17  22  21  22  21  26  21  18
-------------------------------------------------------------------------------
Prev Pi:  35  35  35  36  36  35  36  36  37  35  36  35  35  35  34  35  35  36
New Pi:   32  33  35  34  35  35  42  35  36  33  33  36  33  34  32  37  34  33
Diff:     -3  -2   0  -2  -1   0   6  -1  -1  -2  -3   1  -2  -1  -2   2  -1  -3

Results for N2.C1.D0.R0: 
           0   1   2   3   4   5   6   7   8   9  10  11  12  13  14  15  16  17
-------------------------------------------------------------------------------
Vref offset: 0
Left:    -24 -26 -26 -25 -26 -23 -23 -26 -25 -23 -22 -25 -24 -21 -23 -23 -26 -18
Right:    24  24  24  24  26  27  25  27  22  21  24  25  22  21  22  23  22  24
-------------------------------------------------------------------------------
Prev Pi:  32  34  33  34  34  33  32  34  30  31  31  31  31  31  34  34  34  27
New Pi:   32  33  32  34  34  35  33  34  29  30  32  31  30  31  34  34  32  30
Diff:      0  -1  -1   0   0   2   1   0  -1  -1   1   0  -1   0   0   0  -2   3

Results for N2.C1.D0.R1: 
           0   1   2   3   4   5   6   7   8   9  10  11  12  13  14  15  16  17
-------------------------------------------------------------------------------
Vref offset: 0
Left:    -24 -27 -26 -25 -26 -24 -23 -26 -25 -23 -22 -27 -24 -21 -23 -22 -25 -19
Right:    22  24  25  24  25  25  23  27  23  22  23  23  22  26  20  21  23  23
-------------------------------------------------------------------------------
Prev Pi:  32  34  33  34  34  33  32  34  30  31  31  31  31  31  34  34  34  27
New Pi:   31  33  33  34  34  33  32  34  29  31  31  29  30  33  33  34  33  29
Diff:     -1  -1   0   0   0   0   0   0  -1   0   0  -2  -1   2  -1   0  -1   2

Results for N2.C1.D1.R0: 
           0   1   2   3   4   5   6   7   8   9  10  11  12  13  14  15  16  17
-------------------------------------------------------------------------------
Vref offset: 0
Left:    -26 -27 -26 -25 -25 -22 -22 -25 -26 -25 -24 -26 -26 -23 -21 -22 -25 -20
Right:    20  22  22  21  25  24  21  23  19  18  20  22  19  23  18  22  22  20
-------------------------------------------------------------------------------
Prev Pi:  35  36  35  36  36  35  34  35  34  35  35  34  35  35  36  36  35  31
New Pi:   32  34  33  34  36  36  34  34  31  32  33  32  32  35  35  36  34  31
Diff:     -3  -2  -2  -2   0   1   0  -1  -3  -3  -2  -2  -3   0  -1   0  -1   0

Results for N2.C1.D1.R1: 
           0   1   2   3   4   5   6   7   8   9  10  11  12  13  14  15  16  17
-------------------------------------------------------------------------------
Vref offset: 0
Left:    -26 -27 -25 -25 -26 -22 -23 -25 -26 -25 -23 -26 -26 -22 -20 -20 -24 -21
Right:    20  20  24  23  26  22  24  24  19  20  20  21  18  22  17  18  19  20
-------------------------------------------------------------------------------
Prev Pi:  35  36  35  36  36  35  34  35  34  35  35  34  35  35  36  36  35  31
New Pi:   32  33  35  35  36  35  34  35  31  33  34  32  31  35  35  35  33  31
Diff:     -3  -3   0  -1   0   0   0   0  -3  -2  -1  -2  -4   0  -1  -1  -2   0

Results for N2.C2.D0.R0: 
           0   1   2   3   4   5   6   7   8   9  10  11  12  13  14  15  16  17
-------------------------------------------------------------------------------
Vref offset: 0
Left:    -23 -24 -27 -25 -25 -20 -24 -24 -25 -23 -25 -26 -27 -28 -24 -26 -26 -25
Right:    30  27  24  27  25  27  28  28  22  23  20  26  25  26  29  22  25  25
-------------------------------------------------------------------------------
Prev Pi:  33  34  35  34  33  36  33  37  35  35  34  36  35  33  36  36  36  35
New Pi:   36  35  34  35  33  39  35  39  34  35  32  36  34  32  38  34  36  35
Diff:      3   1  -1   1   0   3   2   2  -1   0  -2   0  -1  -1   2  -2   0   0

Results for N2.C2.D0.R1: 
           0   1   2   3   4   5   6   7   8   9  10  11  12  13  14  15  16  17
-------------------------------------------------------------------------------
Vref offset: 0
Left:    -23 -24 -26 -25 -25 -20 -24 -25 -25 -22 -24 -26 -26 -27 -24 -27 -26 -25
Right:    31  25  24  27  24  25  27  27  25  23  25  26  28  26  27  23  24  26
-------------------------------------------------------------------------------
Prev Pi:  33  34  35  34  33  36  33  37  35  35  34  36  35  33  36  36  36  35
New Pi:   37  34  34  35  33  38  34  38  35  35  34  36  36  33  37  34  35  35
Diff:      4   0  -1   1   0   2   1   1   0   0   0   0   1   0   1  -2  -1   0

Results for N2.C2.D1.R0: 
           0   1   2   3   4   5   6   7   8   9  10  11  12  13  14  15  16  17
-------------------------------------------------------------------------------
Vref offset: 0
Left:    -22 -23 -25 -25 -24 -19 -24 -22 -22 -20 -22 -23 -26 -25 -23 -23 -23 -23
Right:    29  22  24  25  23  26  26  23  25  21  20  25  25  25  26  22  22  23
-------------------------------------------------------------------------------
Prev Pi:  35  36  37  35  36  36  35  39  36  37  36  37  36  34  37  38  37  37
New Pi:   38  36  37  35  36  39  36  39  37  37  35  38  36  34  38  38  37  37
Diff:      3   0   0   0   0   3   1   0   1   0  -1   1   0   0   1   0   0   0

Results for N2.C2.D1.R1: 
           0   1   2   3   4   5   6   7   8   9  10  11  12  13  14  15  16  17
-------------------------------------------------------------------------------
Vref offset: 0
Left:    -22 -23 -26 -25 -25 -20 -23 -22 -21 -21 -22 -23 -26 -25 -22 -24 -23 -24
Right:    31  23  23  25  22  27  24  24  25  24  19  25  26  25  26  21  23  24
-------------------------------------------------------------------------------
Prev Pi:  35  36  37  35  36  36  35  39  36  37  36  37  36  34  37  38  37  37
New Pi:   39  36  36  35  35  39  35  40  38  38  35  38  36  34  39  37  37  37
Diff:      4   0  -1   0  -1   3   0   1   2   1  -1   1   0   0   2  -1   0   0

Results for N2.C3.D0.R0: 
           0   1   2   3   4   5   6   7   8   9  10  11  12  13  14  15  16  17
-------------------------------------------------------------------------------
Vref offset: 0
Left:    -25 -26 -27 -25 -25 -25 -21 -23 -24 -20 -25 -26 -25 -23 -24 -26 -26 -22
Right:    30  25  24  26  27  31  26  26  23  24  24  21  26  29  31  27  24  24
-------------------------------------------------------------------------------
Prev Pi:  36  33  36  33  34  35  36  35  33  35  33  35  33  33  35  34  36  31
New Pi:   38  33  35  33  35  38  38  36  33  37  33  33  33  36  38  34  35  32
Diff:      2   0  -1   0   1   3   2   1   0   2   0  -2   0   3   3   0  -1   1

Results for N2.C3.D0.R1: 
           0   1   2   3   4   5   6   7   8   9  10  11  12  13  14  15  16  17
-------------------------------------------------------------------------------
Vref offset: 0
Left:    -24 -26 -26 -25 -25 -25 -22 -24 -24 -21 -25 -27 -25 -23 -25 -26 -26 -22
Right:    27  27  24  28  28  27  23  28  26  30  24  22  25  27  27  26  24  26
-------------------------------------------------------------------------------
Prev Pi:  36  33  36  33  34  35  36  35  33  35  33  35  33  33  35  34  36  31
New Pi:   37  33  35  34  35  36  36  37  34  39  33  33  33  35  36  34  35  33
Diff:      1   0  -1   1   1   1   0   2   1   4   0  -2   0   2   1   0  -1   2

Results for N2.C3.D1.R0: 
           0   1   2   3   4   5   6   7   8   9  10  11  12  13  14  15  16  17
-------------------------------------------------------------------------------
Vref offset: 0
Left:    -23 -26 -25 -25 -24 -23 -21 -20 -25 -19 -24 -25 -25 -23 -23 -25 -24 -22
Right:    27  27  23  27  25  31  23  24  21  25  25  17  19  25  30  25  22  23
-------------------------------------------------------------------------------
Prev Pi:  38  35  37  35  36  36  37  37  36  37  35  36  35  35  36  36  37  35
New Pi:   40  35  36  36  36  40  38  39  34  40  35  32  32  36  39  36  36  35
Diff:      2   0  -1   1   0   4   1   2  -2   3   0  -4  -3   1   3   0  -1   0

Results for N2.C3.D1.R1: 
           0   1   2   3   4   5   6   7   8   9  10  11  12  13  14  15  16  17
-------------------------------------------------------------------------------
Vref offset: 0
Left:    -22 -25 -24 -25 -25 -23 -21 -21 -25 -19 -25 -25 -25 -22 -23 -25 -25 -24
Right:    28  26  23  27  25  30  22  25  22  28  24  21  21  24  30  26  21  21
-------------------------------------------------------------------------------
Prev Pi:  38  35  37  35  36  36  37  37  36  37  35  36  35  35  36  36  37  35
New Pi:   41  35  37  36  36  39  37  39  35  41  35  34  33  36  39  36  35  34
Diff:      3   0   0   1   0   3   0   2  -1   4   0  -2  -2   1   3   0  -2  -1

STOP_DATA_RX_DQS_ADV
N4.C3.D0.R0.S05: RdPtrOffsetTxDq: 07
N6.C3.D0.R0.S12: PiTxDqs: 16
N0.C3.D0.R0.S10: PiTxDqs: 49
N2: RunTrainStep: Final status = 0
N4.C3.D0.R0.S06: RdPtrOffsetTxDq: 07
N6.C3.D0.R0.S13: wrcmd2dqsstartlatency: 04
N0.C3.D0.R0.S11: wrcmd2dqsstartlatency: 04

END - Rd Timing Centering 2D Training  Time         2366 ms
N4.C3.D0.R0.S07: RdPtrOffsetTxDq: 07
N6.C3.D0.R0.S13: RdPtrOffsetTxDq: 05
N0.C3.D0.R0.S11: RdPtrOffsetTxDq: 06

START - Wr Timing Centering 2D Training
N4.C3.D0.R0.S08: RdPtrOffsetTxDq: 07
N6.C3.D0.R0.S13: RdPtrOffsetTxDqs: 06
N0.C3.D0.R0.S11: RdPtrOffsetTxDqs: 07
N2: 

Adv Strobe Centering(MARGIN_TX_DQ): GetMultiVref: patternLength = 13, stepSize = 1, numPoints = 1
N4.C3.D0.R0.S09: RdPtrOffsetTxDq: 08
N6.C3.D0.R0.S13: PiTxDqs: 45
N0.C3.D0.R0.S11: PiTxDqs: 39
N4.C3.D0.R0.S10: RdPtrOffsetTxDq: 08
N6.C3.D0.R0.S14: wrcmd2dqsstartlatency: 04
N0.C3.D0.R0.S12: wrcmd2dqsstartlatency: 04
N2: GetMargins: Level = 1, group = 12, mode = 0, scope = 4
N4.C3.D0.R0.S11: RdPtrOffsetTxDq: 08
N6.C3.D0.R0.S14: RdPtrOffsetTxDq: 05
N0.C3.D0.R0.S12: RdPtrOffsetTxDq: 05
N4.C3.D0.R0.S12: RdPtrOffsetTxDq: 07
N6.C3.D0.R0.S14: RdPtrOffsetTxDqs: 06
N0.C3.D0.R0.S12: RdPtrOffsetTxDqs: 07
N4.C3.D0.R0.S13: RdPtrOffsetTxDq: 07
N6.C3.D0.R0.S14: PiTxDqs: 59
N0.C3.D0.R0.S12: PiTxDqs: 24
N4.C3.D0.R0.S14: RdPtrOffsetTxDq: 07
N6.C3.D0.R0.S15: wrcmd2dqsstartlatency: 04
N0.C3.D0.R0.S13: wrcmd2dqsstartlatency: 04
N4.C3.D0.R0.S15: RdPtrOffsetTxDq: 07
N6.C3.D0.R0.S15: RdPtrOffsetTxDq: 05
N0.C3.D0.R0.S13: RdPtrOffsetTxDq: 05
N4.C3.D0.R0.S16: RdPtrOffsetTxDq: 07
N6.C3.D0.R0.S15: RdPtrOffsetTxDqs: 07
N0.C3.D0.R0.S13: RdPtrOffsetTxDqs: 06
N4.C3.D0.R0.S17: RdPtrOffsetTxDq: 07
N6.C3.D0.R0.S15: PiTxDqs: 09
N0.C3.D0.R0.S13: PiTxDqs: 51
N4.C3.D0.R0.S00: Total Delay in PI ticks: TxDQ = 990
N6.C3.D0.R0.S16: wrcmd2dqsstartlatency: 04
N0.C3.D0.R0.S14: wrcmd2dqsstartlatency: 04
N4.C3.D0.R0.S01: Total Delay in PI ticks: TxDQ = 972
N6.C3.D0.R0.S16: RdPtrOffsetTxDq: 05
N0.C3.D0.R0.S14: RdPtrOffsetTxDq: 05
N4.C3.D0.R0.S02: Total Delay in PI ticks: TxDQ = 965
N6.C3.D0.R0.S16: RdPtrOffsetTxDqs: 07
N0.C3.D0.R0.S14: RdPtrOffsetTxDqs: 07
N4.C3.D0.R0.S03: Total Delay in PI ticks: TxDQ = 947
N6.C3.D0.R0.S16: PiTxDqs: 27
N0.C3.D0.R0.S14: PiTxDqs: 00
N4.C3.D0.R0.S04: Total Delay in PI ticks: TxDQ = 910
N6.C3.D0.R0.S17: wrcmd2dqsstartlatency: 04
N0.C3.D0.R0.S15: wrcmd2dqsstartlatency: 04
N4.C3.D0.R0.S05: Total Delay in PI ticks: TxDQ = 925
N6.C3.D0.R0.S17: RdPtrOffsetTxDq: 05
N0.C3.D0.R0.S15: RdPtrOffsetTxDq: 05
N4.C3.D0.R0.S06: Total Delay in PI ticks: TxDQ = 939
N6.C3.D0.R0.S17: RdPtrOffsetTxDqs: 06
N0.C3.D0.R0.S15: RdPtrOffsetTxDqs: 07
N4.C3.D0.R0.S07: Total Delay in PI ticks: TxDQ = 958
N6.C3.D0.R0.S17: PiTxDqs: 62
N0.C3.D0.R0.S15: PiTxDqs: 18
N4.C3.D0.R0.S08: Total Delay in PI ticks: TxDQ = 931
N6.C3.D0.R0.S00: RdPtrOffsetTxDq: 07
N0.C3.D0.R0.S16: wrcmd2dqsstartlatency: 04
N4.C3.D0.R0.S09: Total Delay in PI ticks: TxDQ = 988
N6.C3.D0.R0.S01: RdPtrOffsetTxDq: 07
N0.C3.D0.R0.S16: RdPtrOffsetTxDq: 05
N4.C3.D0.R0.S10: Total Delay in PI ticks: TxDQ = 972
N6.C3.D0.R0.S02: RdPtrOffsetTxDq: 07
N0.C3.D0.R0.S16: RdPtrOffsetTxDqs: 07
N4.C3.D0.R0.S11: Total Delay in PI ticks: TxDQ = 964
N6.C3.D0.R0.S03: RdPtrOffsetTxDq: 06
N0.C3.D0.R0.S16: PiTxDqs: 29
N4.C3.D0.R0.S12: Total Delay in PI ticks: TxDQ = 947
N6.C3.D0.R0.S04: RdPtrOffsetTxDq: 06
N0.C3.D0.R0.S17: wrcmd2dqsstartlatency: 04
N4.C3.D0.R0.S13: Total Delay in PI ticks: TxDQ = 912
N6.C3.D0.R0.S05: RdPtrOffsetTxDq: 06
N0.C3.D0.R0.S17: RdPtrOffsetTxDq: 05
N4.C3.D0.R0.S14: Total Delay in PI ticks: TxDQ = 924
N6.C3.D0.R0.S06: RdPtrOffsetTxDq: 06
N0.C3.D0.R0.S17: RdPtrOffsetTxDqs: 07
N4.C3.D0.R0.S15: Total Delay in PI ticks: TxDQ = 944
N6.C3.D0.R0.S07: RdPtrOffsetTxDq: 06
N0.C3.D0.R0.S17: PiTxDqs: 06
N4.C3.D0.R0.S16: Total Delay in PI ticks: TxDQ = 955
N6.C3.D0.R0.S08: RdPtrOffsetTxDq: 06
N0.C3.D0.R0.S00: RdPtrOffsetTxDq: 07
N4.C3.D0.R0.S17: Total Delay in PI ticks: TxDQ = 929
N6.C3.D0.R0.S09: RdPtrOffsetTxDq: 07
N0.C3.D0.R0.S01: RdPtrOffsetTxDq: 07
N4.C3.D0.R1.S00: wrcmd2dqsstartlatency: 04
N6.C3.D0.R0.S10: RdPtrOffsetTxDq: 07
N0.C3.D0.R0.S02: RdPtrOffsetTxDq: 07
N4.C3.D0.R1.S00: RdPtrOffsetTxDq: 06
N6.C3.D0.R0.S11: RdPtrOffsetTxDq: 07
N0.C3.D0.R0.S03: RdPtrOffsetTxDq: 06
N4.C3.D0.R1.S00: RdPtrOffsetTxDqs: 07
N6.C3.D0.R0.S12: RdPtrOffsetTxDq: 06
N0.C3.D0.R0.S04: RdPtrOffsetTxDq: 06
N4.C3.D0.R1.S00: PiTxDqs: 57
N6.C3.D0.R0.S13: RdPtrOffsetTxDq: 06
N0.C3.D0.R0.S05: RdPtrOffsetTxDq: 06
N4.C3.D0.R1.S01: wrcmd2dqsstartlatency: 04
N6.C3.D0.R0.S14: RdPtrOffsetTxDq: 06
N0.C3.D0.R0.S06: RdPtrOffsetTxDq: 06
N4.C3.D0.R1.S01: RdPtrOffsetTxDq: 06
N6.C3.D0.R0.S15: RdPtrOffsetTxDq: 06
N0.C3.D0.R0.S07: RdPtrOffsetTxDq: 07
N4.C3.D0.R1.S01: RdPtrOffsetTxDqs: 07
N6.C3.D0.R0.S16: RdPtrOffsetTxDq: 06
N0.C3.D0.R0.S08: RdPtrOffsetTxDq: 06
N4.C3.D0.R1.S01: PiTxDqs: 41
N6.C3.D0.R0.S17: RdPtrOffsetTxDq: 06
N0.C3.D0.R0.S09: RdPtrOffsetTxDq: 07
N4.C3.D0.R1.S02: wrcmd2dqsstartlatency: 04
N6.C3.D0.R0.S00: RdPtrOffsetTxDq: 08
N0.C3.D0.R0.S10: RdPtrOffsetTxDq: 07
N4.C3.D0.R1.S02: RdPtrOffsetTxDq: 05
N6.C3.D0.R0.S01: RdPtrOffsetTxDq: 08
N0.C3.D0.R0.S11: RdPtrOffsetTxDq: 07
N4.C3.D0.R1.S02: RdPtrOffsetTxDqs: 07
N6.C3.D0.R0.S02: RdPtrOffsetTxDq: 08
N0.C3.D0.R0.S12: RdPtrOffsetTxDq: 06
N4.C3.D0.R1.S02: PiTxDqs: 28
N6.C3.D0.R0.S03: RdPtrOffsetTxDq: 07
N0.C3.D0.R0.S13: RdPtrOffsetTxDq: 06
N4.C3.D0.R1.S03: wrcmd2dqsstartlatency: 04
N6.C3.D0.R0.S04: RdPtrOffsetTxDq: 07
N0.C3.D0.R0.S14: RdPtrOffsetTxDq: 06
N4.C3.D0.R1.S03: RdPtrOffsetTxDq: 05
N6.C3.D0.R0.S05: RdPtrOffsetTxDq: 07
N0.C3.D0.R0.S15: RdPtrOffsetTxDq: 06
N4.C3.D0.R1.S03: RdPtrOffsetTxDqs: 07
N6.C3.D0.R0.S06: RdPtrOffsetTxDq: 07
N0.C3.D0.R0.S16: RdPtrOffsetTxDq: 06
N4.C3.D0.R1.S03: PiTxDqs: 17
N6.C3.D0.R0.S07: RdPtrOffsetTxDq: 07
N0.C3.D0.R0.S17: RdPtrOffsetTxDq: 06
N4.C3.D0.R1.S04: wrcmd2dqsstartlatency: 04
N6.C3.D0.R0.S08: RdPtrOffsetTxDq: 07
N0.C3.D0.R0.S00: RdPtrOffsetTxDq: 08
N4.C3.D0.R1.S04: RdPtrOffsetTxDq: 05
N6.C3.D0.R0.S09: RdPtrOffsetTxDq: 08
N0.C3.D0.R0.S01: RdPtrOffsetTxDq: 08
N4.C3.D0.R1.S04: RdPtrOffsetTxDqs: 06
N6.C3.D0.R0.S10: RdPtrOffsetTxDq: 08
N0.C3.D0.R0.S02: RdPtrOffsetTxDq: 08
N4.C3.D0.R1.S04: PiTxDqs: 42
N6.C3.D0.R0.S11: RdPtrOffsetTxDq: 08
N0.C3.D0.R0.S03: RdPtrOffsetTxDq: 07
N4.C3.D0.R1.S05: wrcmd2dqsstartlatency: 04
N6.C3.D0.R0.S12: RdPtrOffsetTxDq: 07
N0.C3.D0.R0.S04: RdPtrOffsetTxDq: 07
N4.C3.D0.R1.S05: RdPtrOffsetTxDq: 05
N6.C3.D0.R0.S13: RdPtrOffsetTxDq: 07
N0.C3.D0.R0.S05: RdPtrOffsetTxDq: 07
N4.C3.D0.R1.S05: RdPtrOffsetTxDqs: 06
N6.C3.D0.R0.S14: RdPtrOffsetTxDq: 07
N0.C3.D0.R0.S06: RdPtrOffsetTxDq: 07
N4.C3.D0.R1.S05: PiTxDqs: 55
N6.C3.D0.R0.S15: RdPtrOffsetTxDq: 07
N0.C3.D0.R0.S07: RdPtrOffsetTxDq: 08
N4.C3.D0.R1.S06: wrcmd2dqsstartlatency: 04
N6.C3.D0.R0.S16: RdPtrOffsetTxDq: 07
N0.C3.D0.R0.S08: RdPtrOffsetTxDq: 07
N4.C3.D0.R1.S06: RdPtrOffsetTxDq: 05
N6.C3.D0.R0.S17: RdPtrOffsetTxDq: 07
N0.C3.D0.R0.S09: RdPtrOffsetTxDq: 08
N4.C3.D0.R1.S06: RdPtrOffsetTxDqs: 07
N6.C3.D0.R0.S00: Total Delay in PI ticks: TxDQ = 986
N0.C3.D0.R0.S10: RdPtrOffsetTxDq: 08
N4.C3.D0.R1.S06: PiTxDqs: 06
N6.C3.D0.R0.S01: Total Delay in PI ticks: TxDQ = 970
N0.C3.D0.R0.S11: RdPtrOffsetTxDq: 08
N4.C3.D0.R1.S07: wrcmd2dqsstartlatency: 04
N6.C3.D0.R0.S02: Total Delay in PI ticks: TxDQ = 963
N0.C3.D0.R0.S12: RdPtrOffsetTxDq: 07
N4.C3.D0.R1.S07: RdPtrOffsetTxDq: 05
N6.C3.D0.R0.S03: Total Delay in PI ticks: TxDQ = 944
N0.C3.D0.R0.S13: RdPtrOffsetTxDq: 07
N4.C3.D0.R1.S07: RdPtrOffsetTxDqs: 07
N6.C3.D0.R0.S04: Total Delay in PI ticks: TxDQ = 908
N0.C3.D0.R0.S14: RdPtrOffsetTxDq: 07
N4.C3.D0.R1.S07: PiTxDqs: 25
N6.C3.D0.R0.S05: Total Delay in PI ticks: TxDQ = 921
N0.C3.D0.R0.S15: RdPtrOffsetTxDq: 07
N4.C3.D0.R1.S08: wrcmd2dqsstartlatency: 04
N6.C3.D0.R0.S06: Total Delay in PI ticks: TxDQ = 939
N0.C3.D0.R0.S16: RdPtrOffsetTxDq: 07
N4.C3.D0.R1.S08: RdPtrOffsetTxDq: 05
N6.C3.D0.R0.S07: Total Delay in PI ticks: TxDQ = 953
N0.C3.D0.R0.S17: RdPtrOffsetTxDq: 07
N4.C3.D0.R1.S08: RdPtrOffsetTxDqs: 06
N6.C3.D0.R0.S08: Total Delay in PI ticks: TxDQ = 927
N0.C3.D0.R0.S00: Total Delay in PI ticks: TxDQ = 990
N4.C3.D0.R1.S08: PiTxDqs: 58
N6.C3.D0.R0.S09: Total Delay in PI ticks: TxDQ = 985
N0.C3.D0.R0.S01: Total Delay in PI ticks: TxDQ = 975
N4.C3.D0.R1.S09: wrcmd2dqsstartlatency: 04
N6.C3.D0.R0.S10: Total Delay in PI ticks: TxDQ = 970
N0.C3.D0.R0.S02: Total Delay in PI ticks: TxDQ = 966
N4.C3.D0.R1.S09: RdPtrOffsetTxDq: 06
N6.C3.D0.R0.S11: Total Delay in PI ticks: TxDQ = 961
N0.C3.D0.R0.S03: Total Delay in PI ticks: TxDQ = 945
N4.C3.D0.R1.S09: RdPtrOffsetTxDqs: 07
N6.C3.D0.R0.S12: Total Delay in PI ticks: TxDQ = 943
N0.C3.D0.R0.S04: Total Delay in PI ticks: TxDQ = 914
N4.C3.D0.R1.S09: PiTxDqs: 55
N6.C3.D0.R0.S13: Total Delay in PI ticks: TxDQ = 908
N0.C3.D0.R0.S05: Total Delay in PI ticks: TxDQ = 927
N4.C3.D0.R1.S10: wrcmd2dqsstartlatency: 04
N6.C3.D0.R0.S14: Total Delay in PI ticks: TxDQ = 925
N0.C3.D0.R0.S06: Total Delay in PI ticks: TxDQ = 941
N4.C3.D0.R1.S10: RdPtrOffsetTxDq: 06
N6.C3.D0.R0.S15: Total Delay in PI ticks: TxDQ = 938
N0.C3.D0.R0.S07: Total Delay in PI ticks: TxDQ = 960
N4.C3.D0.R1.S10: RdPtrOffsetTxDqs: 07
N6.C3.D0.R0.S16: Total Delay in PI ticks: TxDQ = 956
N0.C3.D0.R0.S08: Total Delay in PI ticks: TxDQ = 930
N4.C3.D0.R1.S10: PiTxDqs: 41
N6.C3.D0.R0.S17: Total Delay in PI ticks: TxDQ = 926
N0.C3.D0.R0.S09: Total Delay in PI ticks: TxDQ = 988
N4.C3.D0.R1.S11: wrcmd2dqsstartlatency: 04
N6.C3.D0.R1.S00: wrcmd2dqsstartlatency: 04
N0.C3.D0.R0.S10: Total Delay in PI ticks: TxDQ = 975
N4.C3.D0.R1.S11: RdPtrOffsetTxDq: 05
N6.C3.D0.R1.S00: RdPtrOffsetTxDq: 06
N0.C3.D0.R0.S11: Total Delay in PI ticks: TxDQ = 966
N4.C3.D0.R1.S11: RdPtrOffsetTxDqs: 07
N6.C3.D0.R1.S00: RdPtrOffsetTxDqs: 07
N0.C3.D0.R0.S12: Total Delay in PI ticks: TxDQ = 949
N4.C3.D0.R1.S11: PiTxDqs: 28
N6.C3.D0.R1.S00: PiTxDqs: 51
N0.C3.D0.R0.S13: Total Delay in PI ticks: TxDQ = 915
N4.C3.D0.R1.S12: wrcmd2dqsstartlatency: 04
N6.C3.D0.R1.S01: wrcmd2dqsstartlatency: 04
N0.C3.D0.R0.S14: Total Delay in PI ticks: TxDQ = 926
N4.C3.D0.R1.S12: RdPtrOffsetTxDq: 05
N6.C3.D0.R1.S01: RdPtrOffsetTxDq: 06
N0.C3.D0.R0.S15: Total Delay in PI ticks: TxDQ = 944
N4.C3.D0.R1.S12: RdPtrOffsetTxDqs: 07
N6.C3.D0.R1.S01: RdPtrOffsetTxDqs: 07
N0.C3.D0.R0.S16: Total Delay in PI ticks: TxDQ = 956
N4.C3.D0.R1.S12: PiTxDqs: 19
N6.C3.D0.R1.S01: PiTxDqs: 36
N0.C3.D0.R0.S17: Total Delay in PI ticks: TxDQ = 934
N4.C3.D0.R1.S13: wrcmd2dqsstartlatency: 04
N6.C3.D0.R1.S02: wrcmd2dqsstartlatency: 04
N0.C3.D0.R1.S00: wrcmd2dqsstartlatency: 04
N4.C3.D0.R1.S13: RdPtrOffsetTxDq: 05
N6.C3.D0.R1.S02: RdPtrOffsetTxDq: 05
N0.C3.D0.R1.S00: RdPtrOffsetTxDq: 06
N4.C3.D0.R1.S13: RdPtrOffsetTxDqs: 06
N6.C3.D0.R1.S02: RdPtrOffsetTxDqs: 07
N0.C3.D0.R1.S00: RdPtrOffsetTxDqs: 07
N4.C3.D0.R1.S13: PiTxDqs: 41
N6.C3.D0.R1.S02: PiTxDqs: 26
N0.C3.D0.R1.S00: PiTxDqs: 59
N4.C3.D0.R1.S14: wrcmd2dqsstartlatency: 04
N6.C3.D0.R1.S03: wrcmd2dqsstartlatency: 04
N0.C3.D0.R1.S01: wrcmd2dqsstartlatency: 04
N4.C3.D0.R1.S14: RdPtrOffsetTxDq: 05
N6.C3.D0.R1.S03: RdPtrOffsetTxDq: 05
N0.C3.D0.R1.S01: RdPtrOffsetTxDq: 06
N4.C3.D0.R1.S14: RdPtrOffsetTxDqs: 06
N6.C3.D0.R1.S03: RdPtrOffsetTxDqs: 07
N0.C3.D0.R1.S01: RdPtrOffsetTxDqs: 07
N4.C3.D0.R1.S14: PiTxDqs: 57
N6.C3.D0.R1.S03: PiTxDqs: 10
N0.C3.D0.R1.S01: PiTxDqs: 41
N4.C3.D0.R1.S15: wrcmd2dqsstartlatency: 04
N6.C3.D0.R1.S04: wrcmd2dqsstartlatency: 04
N0.C3.D0.R1.S02: wrcmd2dqsstartlatency: 04
N4.C3.D0.R1.S15: RdPtrOffsetTxDq: 05
N6.C3.D0.R1.S04: RdPtrOffsetTxDq: 05
N0.C3.D0.R1.S02: RdPtrOffsetTxDq: 05
N4.C3.D0.R1.S15: RdPtrOffsetTxDqs: 07
N6.C3.D0.R1.S04: RdPtrOffsetTxDqs: 06
N0.C3.D0.R1.S02: RdPtrOffsetTxDqs: 07
N4.C3.D0.R1.S15: PiTxDqs: 08
N6.C3.D0.R1.S04: PiTxDqs: 37
N0.C3.D0.R1.S02: PiTxDqs: 31
N4.C3.D0.R1.S16: wrcmd2dqsstartlatency: 04
N6.C3.D0.R1.S05: wrcmd2dqsstartlatency: 04
N0.C3.D0.R1.S03: wrcmd2dqsstartlatency: 04
N4.C3.D0.R1.S16: RdPtrOffsetTxDq: 05
N6.C3.D0.R1.S05: RdPtrOffsetTxDq: 05
N0.C3.D0.R1.S03: RdPtrOffsetTxDq: 05
N4.C3.D0.R1.S16: RdPtrOffsetTxDqs: 07
N6.C3.D0.R1.S05: RdPtrOffsetTxDqs: 06
N0.C3.D0.R1.S03: RdPtrOffsetTxDqs: 07
N4.C3.D0.R1.S16: PiTxDqs: 26
N6.C3.D0.R1.S05: PiTxDqs: 52
N0.C3.D0.R1.S03: PiTxDqs: 17
N4.C3.D0.R1.S17: wrcmd2dqsstartlatency: 04
N6.C3.D0.R1.S06: wrcmd2dqsstartlatency: 04
N0.C3.D0.R1.S04: wrcmd2dqsstartlatency: 04
N4.C3.D0.R1.S17: RdPtrOffsetTxDq: 05
N6.C3.D0.R1.S06: RdPtrOffsetTxDq: 05
N0.C3.D0.R1.S04: RdPtrOffsetTxDq: 05
N4.C3.D0.R1.S17: RdPtrOffsetTxDqs: 06
N6.C3.D0.R1.S06: RdPtrOffsetTxDqs: 07
N0.C3.D0.R1.S04: RdPtrOffsetTxDqs: 06
N4.C3.D0.R1.S17: PiTxDqs: 58
N6.C3.D0.R1.S06: PiTxDqs: 02
N0.C3.D0.R1.S04: PiTxDqs: 47
N4.C3.D0.R1.S00: RdPtrOffsetTxDq: 07
N6.C3.D0.R1.S07: wrcmd2dqsstartlatency: 04
N0.C3.D0.R1.S05: wrcmd2dqsstartlatency: 04
N4.C3.D0.R1.S01: RdPtrOffsetTxDq: 07
N6.C3.D0.R1.S07: RdPtrOffsetTxDq: 05
N0.C3.D0.R1.S05: RdPtrOffsetTxDq: 05
N4.C3.D0.R1.S02: RdPtrOffsetTxDq: 06
N6.C3.D0.R1.S07: RdPtrOffsetTxDqs: 07
N0.C3.D0.R1.S05: RdPtrOffsetTxDqs: 06
N4.C3.D0.R1.S03: RdPtrOffsetTxDq: 06
N6.C3.D0.R1.S07: PiTxDqs: 19
N0.C3.D0.R1.S05: PiTxDqs: 58
N4.C3.D0.R1.S04: RdPtrOffsetTxDq: 06
N6.C3.D0.R1.S08: wrcmd2dqsstartlatency: 04
N0.C3.D0.R1.S06: wrcmd2dqsstartlatency: 04
N4.C3.D0.R1.S05: RdPtrOffsetTxDq: 06
N6.C3.D0.R1.S08: RdPtrOffsetTxDq: 05
N0.C3.D0.R1.S06: RdPtrOffsetTxDq: 05
N4.C3.D0.R1.S06: RdPtrOffsetTxDq: 06
N6.C3.D0.R1.S08: RdPtrOffsetTxDqs: 06
N0.C3.D0.R1.S06: RdPtrOffsetTxDqs: 07
N4.C3.D0.R1.S07: RdPtrOffsetTxDq: 06
N6.C3.D0.R1.S08: PiTxDqs: 55
N0.C3.D0.R1.S06: PiTxDqs: 09
N4.C3.D0.R1.S08: RdPtrOffsetTxDq: 06
N6.C3.D0.R1.S09: wrcmd2dqsstartlatency: 04
N0.C3.D0.R1.S07: wrcmd2dqsstartlatency: 04
N4.C3.D0.R1.S09: RdPtrOffsetTxDq: 07
N6.C3.D0.R1.S09: RdPtrOffsetTxDq: 06
N0.C3.D0.R1.S07: RdPtrOffsetTxDq: 05
N4.C3.D0.R1.S10: RdPtrOffsetTxDq: 07
N6.C3.D0.R1.S09: RdPtrOffsetTxDqs: 07
N0.C3.D0.R1.S07: RdPtrOffsetTxDqs: 07
N4.C3.D0.R1.S11: RdPtrOffsetTxDq: 06
N6.C3.D0.R1.S09: PiTxDqs: 50
N0.C3.D0.R1.S07: PiTxDqs: 27
N4.C3.D0.R1.S12: RdPtrOffsetTxDq: 06
N6.C3.D0.R1.S10: wrcmd2dqsstartlatency: 04
N0.C3.D0.R1.S08: wrcmd2dqsstartlatency: 04
N4.C3.D0.R1.S13: RdPtrOffsetTxDq: 06
N6.C3.D0.R1.S10: RdPtrOffsetTxDq: 06
N0.C3.D0.R1.S08: RdPtrOffsetTxDq: 05
N4.C3.D0.R1.S14: RdPtrOffsetTxDq: 06
N6.C3.D0.R1.S10: RdPtrOffsetTxDqs: 07
N0.C3.D0.R1.S08: RdPtrOffsetTxDqs: 06
N4.C3.D0.R1.S15: RdPtrOffsetTxDq: 06
N6.C3.D0.R1.S10: PiTxDqs: 35
N0.C3.D0.R1.S08: PiTxDqs: 61
N4.C3.D0.R1.S16: RdPtrOffsetTxDq: 06
N6.C3.D0.R1.S11: wrcmd2dqsstartlatency: 04
N0.C3.D0.R1.S09: wrcmd2dqsstartlatency: 04
N4.C3.D0.R1.S17: RdPtrOffsetTxDq: 06
N6.C3.D0.R1.S11: RdPtrOffsetTxDq: 05
N0.C3.D0.R1.S09: RdPtrOffsetTxDq: 06
N4.C3.D0.R1.S00: RdPtrOffsetTxDq: 08
N6.C3.D0.R1.S11: RdPtrOffsetTxDqs: 07
N0.C3.D0.R1.S09: RdPtrOffsetTxDqs: 07
N4.C3.D0.R1.S01: RdPtrOffsetTxDq: 08
N6.C3.D0.R1.S11: PiTxDqs: 25
N0.C3.D0.R1.S09: PiTxDqs: 58
N4.C3.D0.R1.S02: RdPtrOffsetTxDq: 07
N6.C3.D0.R1.S12: wrcmd2dqsstartlatency: 04
N0.C3.D0.R1.S10: wrcmd2dqsstartlatency: 04
N4.C3.D0.R1.S03: RdPtrOffsetTxDq: 07
N6.C3.D0.R1.S12: RdPtrOffsetTxDq: 05
N0.C3.D0.R1.S10: RdPtrOffsetTxDq: 06
N4.C3.D0.R1.S04: RdPtrOffsetTxDq: 07
N6.C3.D0.R1.S12: RdPtrOffsetTxDqs: 07
N0.C3.D0.R1.S10: RdPtrOffsetTxDqs: 07
N4.C3.D0.R1.S05: RdPtrOffsetTxDq: 07
N6.C3.D0.R1.S12: PiTxDqs: 11
N0.C3.D0.R1.S10: PiTxDqs: 42
N4.C3.D0.R1.S06: RdPtrOffsetTxDq: 07
N6.C3.D0.R1.S13: wrcmd2dqsstartlatency: 04
N0.C3.D0.R1.S11: wrcmd2dqsstartlatency: 04
N4.C3.D0.R1.S07: RdPtrOffsetTxDq: 07
N6.C3.D0.R1.S13: RdPtrOffsetTxDq: 05
N0.C3.D0.R1.S11: RdPtrOffsetTxDq: 05
N4.C3.D0.R1.S08: RdPtrOffsetTxDq: 07
N6.C3.D0.R1.S13: RdPtrOffsetTxDqs: 06
N0.C3.D0.R1.S11: RdPtrOffsetTxDqs: 07
N4.C3.D0.R1.S09: RdPtrOffsetTxDq: 08
N6.C3.D0.R1.S13: PiTxDqs: 37
N0.C3.D0.R1.S11: PiTxDqs: 31
N4.C3.D0.R1.S10: RdPtrOffsetTxDq: 08
N6.C3.D0.R1.S14: wrcmd2dqsstartlatency: 04
N0.C3.D0.R1.S12: wrcmd2dqsstartlatency: 04
N4.C3.D0.R1.S11: RdPtrOffsetTxDq: 07
N6.C3.D0.R1.S14: RdPtrOffsetTxDq: 05
N0.C3.D0.R1.S12: RdPtrOffsetTxDq: 05
N4.C3.D0.R1.S12: RdPtrOffsetTxDq: 07
N6.C3.D0.R1.S14: RdPtrOffsetTxDqs: 06
N0.C3.D0.R1.S12: RdPtrOffsetTxDqs: 07
N4.C3.D0.R1.S13: RdPtrOffsetTxDq: 07
N6.C3.D0.R1.S14: PiTxDqs: 51
N0.C3.D0.R1.S12: PiTxDqs: 20
N4.C3.D0.R1.S14: RdPtrOffsetTxDq: 07
N6.C3.D0.R1.S15: wrcmd2dqsstartlatency: 04
N0.C3.D0.R1.S13: wrcmd2dqsstartlatency: 04
N4.C3.D0.R1.S15: RdPtrOffsetTxDq: 07
N6.C3.D0.R1.S15: RdPtrOffsetTxDq: 05
N0.C3.D0.R1.S13: RdPtrOffsetTxDq: 05
N4.C3.D0.R1.S16: RdPtrOffsetTxDq: 07
N6.C3.D0.R1.S15: RdPtrOffsetTxDqs: 07
N0.C3.D0.R1.S13: RdPtrOffsetTxDqs: 06
N4.C3.D0.R1.S17: RdPtrOffsetTxDq: 07
N6.C3.D0.R1.S15: PiTxDqs: 01
N0.C3.D0.R1.S13: PiTxDqs: 47
N4.C3.D0.R1.S00: Total Delay in PI ticks: TxDQ = 984
N6.C3.D0.R1.S16: wrcmd2dqsstartlatency: 04
N0.C3.D0.R1.S14: wrcmd2dqsstartlatency: 04
N4.C3.D0.R1.S01: Total Delay in PI ticks: TxDQ = 967
N6.C3.D0.R1.S16: RdPtrOffsetTxDq: 05
N0.C3.D0.R1.S14: RdPtrOffsetTxDq: 05
N4.C3.D0.R1.S02: Total Delay in PI ticks: TxDQ = 954
N6.C3.D0.R1.S16: RdPtrOffsetTxDqs: 07
N0.C3.D0.R1.S14: RdPtrOffsetTxDqs: 06
N4.C3.D0.R1.S03: Total Delay in PI ticks: TxDQ = 943
N6.C3.D0.R1.S16: PiTxDqs: 20
N0.C3.D0.R1.S14: PiTxDqs: 59
N4.C3.D0.R1.S04: Total Delay in PI ticks: TxDQ = 904
N6.C3.D0.R1.S17: wrcmd2dqsstartlatency: 04
N0.C3.D0.R1.S15: wrcmd2dqsstartlatency: 04
N4.C3.D0.R1.S05: Total Delay in PI ticks: TxDQ = 916
N6.C3.D0.R1.S17: RdPtrOffsetTxDq: 05
N0.C3.D0.R1.S15: RdPtrOffsetTxDq: 05
N4.C3.D0.R1.S06: Total Delay in PI ticks: TxDQ = 932
N6.C3.D0.R1.S17: RdPtrOffsetTxDqs: 06
N0.C3.D0.R1.S15: RdPtrOffsetTxDqs: 07
N4.C3.D0.R1.S07: Total Delay in PI ticks: TxDQ = 949
N6.C3.D0.R1.S17: PiTxDqs: 53
N0.C3.D0.R1.S15: PiTxDqs: 08
N4.C3.D0.R1.S08: Total Delay in PI ticks: TxDQ = 921
N6.C3.D0.R1.S00: RdPtrOffsetTxDq: 07
N0.C3.D0.R1.S16: wrcmd2dqsstartlatency: 04
N4.C3.D0.R1.S09: Total Delay in PI ticks: TxDQ = 980
N6.C3.D0.R1.S01: RdPtrOffsetTxDq: 07
N0.C3.D0.R1.S16: RdPtrOffsetTxDq: 05
N4.C3.D0.R1.S10: Total Delay in PI ticks: TxDQ = 968
N6.C3.D0.R1.S02: RdPtrOffsetTxDq: 06
N0.C3.D0.R1.S16: RdPtrOffsetTxDqs: 07
N4.C3.D0.R1.S11: Total Delay in PI ticks: TxDQ = 954
N6.C3.D0.R1.S03: RdPtrOffsetTxDq: 06
N0.C3.D0.R1.S16: PiTxDqs: 27
N4.C3.D0.R1.S12: Total Delay in PI ticks: TxDQ = 945
N6.C3.D0.R1.S04: RdPtrOffsetTxDq: 06
N0.C3.D0.R1.S17: wrcmd2dqsstartlatency: 04
N4.C3.D0.R1.S13: Total Delay in PI ticks: TxDQ = 905
N6.C3.D0.R1.S05: RdPtrOffsetTxDq: 06
N0.C3.D0.R1.S17: RdPtrOffsetTxDq: 05
N4.C3.D0.R1.S14: Total Delay in PI ticks: TxDQ = 920
N6.C3.D0.R1.S06: RdPtrOffsetTxDq: 06
N0.C3.D0.R1.S17: RdPtrOffsetTxDqs: 06
N4.C3.D0.R1.S15: Total Delay in PI ticks: TxDQ = 935
N6.C3.D0.R1.S07: RdPtrOffsetTxDq: 06
N0.C3.D0.R1.S17: PiTxDqs: 61
N4.C3.D0.R1.S16: Total Delay in PI ticks: TxDQ = 952
N6.C3.D0.R1.S08: RdPtrOffsetTxDq: 06
N0.C3.D0.R1.S00: RdPtrOffsetTxDq: 07
N4.C3.D0.R1.S17: Total Delay in PI ticks: TxDQ = 921
N6.C3.D0.R1.S09: RdPtrOffsetTxDq: 07
N0.C3.D0.R1.S01: RdPtrOffsetTxDq: 07
N4.C3.D1.R0.S00: wrcmd2dqsstartlatency: 04
N6.C3.D0.R1.S10: RdPtrOffsetTxDq: 07
N0.C3.D0.R1.S02: RdPtrOffsetTxDq: 06
N4.C3.D1.R0.S00: RdPtrOffsetTxDq: 06
N6.C3.D0.R1.S11: RdPtrOffsetTxDq: 06
N0.C3.D0.R1.S03: RdPtrOffsetTxDq: 06
N4.C3.D1.R0.S00: RdPtrOffsetTxDqs: 08
N6.C3.D0.R1.S12: RdPtrOffsetTxDq: 06
N0.C3.D0.R1.S04: RdPtrOffsetTxDq: 06
N4.C3.D1.R0.S00: PiTxDqs: 04
N6.C3.D0.R1.S13: RdPtrOffsetTxDq: 06
N0.C3.D0.R1.S05: RdPtrOffsetTxDq: 06
N4.C3.D1.R0.S01: wrcmd2dqsstartlatency: 04
N6.C3.D0.R1.S14: RdPtrOffsetTxDq: 06
N0.C3.D0.R1.S06: RdPtrOffsetTxDq: 06
N4.C3.D1.R0.S01: RdPtrOffsetTxDq: 06
N6.C3.D0.R1.S15: RdPtrOffsetTxDq: 06
N0.C3.D0.R1.S07: RdPtrOffsetTxDq: 06
N4.C3.D1.R0.S01: RdPtrOffsetTxDqs: 07
N6.C3.D0.R1.S16: RdPtrOffsetTxDq: 06
N0.C3.D0.R1.S08: RdPtrOffsetTxDq: 06
N4.C3.D1.R0.S01: PiTxDqs: 54
N6.C3.D0.R1.S17: RdPtrOffsetTxDq: 06
N0.C3.D0.R1.S09: RdPtrOffsetTxDq: 07
N4.C3.D1.R0.S02: wrcmd2dqsstartlatency: 04
N6.C3.D0.R1.S00: RdPtrOffsetTxDq: 08
N0.C3.D0.R1.S10: RdPtrOffsetTxDq: 07
N4.C3.D1.R0.S02: RdPtrOffsetTxDq: 06
N6.C3.D0.R1.S01: RdPtrOffsetTxDq: 08
N0.C3.D0.R1.S11: RdPtrOffsetTxDq: 06
N4.C3.D1.R0.S02: RdPtrOffsetTxDqs: 07
N6.C3.D0.R1.S02: RdPtrOffsetTxDq: 07
N0.C3.D0.R1.S12: RdPtrOffsetTxDq: 06
N4.C3.D1.R0.S02: PiTxDqs: 43
N6.C3.D0.R1.S03: RdPtrOffsetTxDq: 07
N0.C3.D0.R1.S13: RdPtrOffsetTxDq: 06
N4.C3.D1.R0.S03: wrcmd2dqsstartlatency: 04
N6.C3.D0.R1.S04: RdPtrOffsetTxDq: 07
N0.C3.D0.R1.S14: RdPtrOffsetTxDq: 06
N4.C3.D1.R0.S03: RdPtrOffsetTxDq: 05
N6.C3.D0.R1.S05: RdPtrOffsetTxDq: 07
N0.C3.D0.R1.S15: RdPtrOffsetTxDq: 06
N4.C3.D1.R0.S03: RdPtrOffsetTxDqs: 07
N6.C3.D0.R1.S06: RdPtrOffsetTxDq: 07
N0.C3.D0.R1.S16: RdPtrOffsetTxDq: 06
N4.C3.D1.R0.S03: PiTxDqs: 27
N6.C3.D0.R1.S07: RdPtrOffsetTxDq: 07
N0.C3.D0.R1.S17: RdPtrOffsetTxDq: 06
N4.C3.D1.R0.S04: wrcmd2dqsstartlatency: 04
N6.C3.D0.R1.S08: RdPtrOffsetTxDq: 07
N0.C3.D0.R1.S00: RdPtrOffsetTxDq: 08
N4.C3.D1.R0.S04: RdPtrOffsetTxDq: 05
N6.C3.D0.R1.S09: RdPtrOffsetTxDq: 08
N0.C3.D0.R1.S01: RdPtrOffsetTxDq: 08
N4.C3.D1.R0.S04: RdPtrOffsetTxDqs: 06
N6.C3.D0.R1.S10: RdPtrOffsetTxDq: 08
N0.C3.D0.R1.S02: RdPtrOffsetTxDq: 07
N4.C3.D1.R0.S04: PiTxDqs: 57
N6.C3.D0.R1.S11: RdPtrOffsetTxDq: 07
N0.C3.D0.R1.S03: RdPtrOffsetTxDq: 07
N4.C3.D1.R0.S05: wrcmd2dqsstartlatency: 04
N6.C3.D0.R1.S12: RdPtrOffsetTxDq: 07
N0.C3.D0.R1.S04: RdPtrOffsetTxDq: 07
N4.C3.D1.R0.S05: RdPtrOffsetTxDq: 05
N6.C3.D0.R1.S13: RdPtrOffsetTxDq: 07
N0.C3.D0.R1.S05: RdPtrOffsetTxDq: 07
N4.C3.D1.R0.S05: RdPtrOffsetTxDqs: 07
N6.C3.D0.R1.S14: RdPtrOffsetTxDq: 07
N0.C3.D0.R1.S06: RdPtrOffsetTxDq: 07
N4.C3.D1.R0.S05: PiTxDqs: 02
N6.C3.D0.R1.S15: RdPtrOffsetTxDq: 07
N0.C3.D0.R1.S07: RdPtrOffsetTxDq: 07
N4.C3.D1.R0.S06: wrcmd2dqsstartlatency: 04
N6.C3.D0.R1.S16: RdPtrOffsetTxDq: 07
N0.C3.D0.R1.S08: RdPtrOffsetTxDq: 07
N4.C3.D1.R0.S06: RdPtrOffsetTxDq: 05
N6.C3.D0.R1.S17: RdPtrOffsetTxDq: 07
N0.C3.D0.R1.S09: RdPtrOffsetTxDq: 08
N4.C3.D1.R0.S06: RdPtrOffsetTxDqs: 07
N6.C3.D0.R1.S00: Total Delay in PI ticks: TxDQ = 980
N0.C3.D0.R1.S10: RdPtrOffsetTxDq: 08
N4.C3.D1.R0.S06: PiTxDqs: 21
N6.C3.D0.R1.S01: Total Delay in PI ticks: TxDQ = 963
N0.C3.D0.R1.S11: RdPtrOffsetTxDq: 07
N4.C3.D1.R0.S07: wrcmd2dqsstartlatency: 04
N6.C3.D0.R1.S02: Total Delay in PI ticks: TxDQ = 953
N0.C3.D0.R1.S12: RdPtrOffsetTxDq: 07
N4.C3.D1.R0.S07: RdPtrOffsetTxDq: 05
N6.C3.D0.R1.S03: Total Delay in PI ticks: TxDQ = 936
N0.C3.D0.R1.S13: RdPtrOffsetTxDq: 07
N4.C3.D1.R0.S07: RdPtrOffsetTxDqs: 07
N6.C3.D0.R1.S04: Total Delay in PI ticks: TxDQ = 899
N0.C3.D0.R1.S14: RdPtrOffsetTxDq: 07
N4.C3.D1.R0.S07: PiTxDqs: 37
N6.C3.D0.R1.S05: Total Delay in PI ticks: TxDQ = 917
N0.C3.D0.R1.S15: RdPtrOffsetTxDq: 07
N4.C3.D1.R0.S08: wrcmd2dqsstartlatency: 04
N6.C3.D0.R1.S06: Total Delay in PI ticks: TxDQ = 931
N0.C3.D0.R1.S16: RdPtrOffsetTxDq: 07
N4.C3.D1.R0.S08: RdPtrOffsetTxDq: 05
N6.C3.D0.R1.S07: Total Delay in PI ticks: TxDQ = 946
N0.C3.D0.R1.S17: RdPtrOffsetTxDq: 07
N4.C3.D1.R0.S08: RdPtrOffsetTxDqs: 07
N6.C3.D0.R1.S08: Total Delay in PI ticks: TxDQ = 918
N0.C3.D0.R1.S00: Total Delay in PI ticks: TxDQ = 984
N4.C3.D1.R0.S08: PiTxDqs: 07
N6.C3.D0.R1.S09: Total Delay in PI ticks: TxDQ = 976
N0.C3.D0.R1.S01: Total Delay in PI ticks: TxDQ = 967
N4.C3.D1.R0.S09: wrcmd2dqsstartlatency: 04
N6.C3.D0.R1.S10: Total Delay in PI ticks: TxDQ = 964
N0.C3.D0.R1.S02: Total Delay in PI ticks: TxDQ = 958
N4.C3.D1.R0.S09: RdPtrOffsetTxDq: 06
N6.C3.D0.R1.S11: Total Delay in PI ticks: TxDQ = 953
N0.C3.D0.R1.S03: Total Delay in PI ticks: TxDQ = 942
N4.C3.D1.R0.S09: RdPtrOffsetTxDqs: 08
N6.C3.D0.R1.S12: Total Delay in PI ticks: TxDQ = 939
N0.C3.D0.R1.S04: Total Delay in PI ticks: TxDQ = 909
N4.C3.D1.R0.S09: PiTxDqs: 03
N6.C3.D0.R1.S13: Total Delay in PI ticks: TxDQ = 901
N0.C3.D0.R1.S05: Total Delay in PI ticks: TxDQ = 921
N4.C3.D1.R0.S10: wrcmd2dqsstartlatency: 04
N6.C3.D0.R1.S14: Total Delay in PI ticks: TxDQ = 916
N0.C3.D0.R1.S06: Total Delay in PI ticks: TxDQ = 935
N4.C3.D1.R0.S10: RdPtrOffsetTxDq: 06
N6.C3.D0.R1.S15: Total Delay in PI ticks: TxDQ = 931
N0.C3.D0.R1.S07: Total Delay in PI ticks: TxDQ = 953
N4.C3.D1.R0.S10: RdPtrOffsetTxDqs: 07
N6.C3.D0.R1.S16: Total Delay in PI ticks: TxDQ = 948
N0.C3.D0.R1.S08: Total Delay in PI ticks: TxDQ = 924
N4.C3.D1.R0.S10: PiTxDqs: 54
N6.C3.D0.R1.S17: Total Delay in PI ticks: TxDQ = 917
N0.C3.D0.R1.S09: Total Delay in PI ticks: TxDQ = 983
N4.C3.D1.R0.S11: wrcmd2dqsstartlatency: 04
N6.C3.D1.R0.S00: wrcmd2dqsstartlatency: 04
N0.C3.D0.R1.S10: Total Delay in PI ticks: TxDQ = 968
N4.C3.D1.R0.S11: RdPtrOffsetTxDq: 06
N6.C3.D1.R0.S00: RdPtrOffsetTxDq: 06
N0.C3.D0.R1.S11: Total Delay in PI ticks: TxDQ = 958
N4.C3.D1.R0.S11: RdPtrOffsetTxDqs: 07
N6.C3.D1.R0.S00: RdPtrOffsetTxDqs: 08
N0.C3.D0.R1.S12: Total Delay in PI ticks: TxDQ = 945
N4.C3.D1.R0.S11: PiTxDqs: 43
N6.C3.D1.R0.S00: PiTxDqs: 02
N0.C3.D0.R1.S13: Total Delay in PI ticks: TxDQ = 908
N4.C3.D1.R0.S12: wrcmd2dqsstartlatency: 04
N6.C3.D1.R0.S01: wrcmd2dqsstartlatency: 04
N0.C3.D0.R1.S14: Total Delay in PI ticks: TxDQ = 922
N4.C3.D1.R0.S12: RdPtrOffsetTxDq: 05
N6.C3.D1.R0.S01: RdPtrOffsetTxDq: 06
N0.C3.D0.R1.S15: Total Delay in PI ticks: TxDQ = 934
N4.C3.D1.R0.S12: RdPtrOffsetTxDqs: 07
N6.C3.D1.R0.S01: RdPtrOffsetTxDqs: 07
N0.C3.D0.R1.S16: Total Delay in PI ticks: TxDQ = 954
N4.C3.D1.R0.S12: PiTxDqs: 31
N6.C3.D1.R0.S01: PiTxDqs: 48
N0.C3.D0.R1.S17: Total Delay in PI ticks: TxDQ = 925
N4.C3.D1.R0.S13: wrcmd2dqsstartlatency: 04
N6.C3.D1.R0.S02: wrcmd2dqsstartlatency: 04
N0.C3.D1.R0.S00: wrcmd2dqsstartlatency: 04
N4.C3.D1.R0.S13: RdPtrOffsetTxDq: 05
N6.C3.D1.R0.S02: RdPtrOffsetTxDq: 06
N0.C3.D1.R0.S00: RdPtrOffsetTxDq: 06
N4.C3.D1.R0.S13: RdPtrOffsetTxDqs: 06
N6.C3.D1.R0.S02: RdPtrOffsetTxDqs: 07
N0.C3.D1.R0.S00: RdPtrOffsetTxDqs: 08
N4.C3.D1.R0.S13: PiTxDqs: 55
N6.C3.D1.R0.S02: PiTxDqs: 36
N0.C3.D1.R0.S00: PiTxDqs: 04
N4.C3.D1.R0.S14: wrcmd2dqsstartlatency: 04
N6.C3.D1.R0.S03: wrcmd2dqsstartlatency: 04
N0.C3.D1.R0.S01: wrcmd2dqsstartlatency: 04
N4.C3.D1.R0.S14: RdPtrOffsetTxDq: 05
N6.C3.D1.R0.S03: RdPtrOffsetTxDq: 05
N0.C3.D1.R0.S01: RdPtrOffsetTxDq: 06
N4.C3.D1.R0.S14: RdPtrOffsetTxDqs: 07
N6.C3.D1.R0.S03: RdPtrOffsetTxDqs: 07
N0.C3.D1.R0.S01: RdPtrOffsetTxDqs: 07
N4.C3.D1.R0.S14: PiTxDqs: 08
N6.C3.D1.R0.S03: PiTxDqs: 23
N0.C3.D1.R0.S01: PiTxDqs: 50
N4.C3.D1.R0.S15: wrcmd2dqsstartlatency: 04
N6.C3.D1.R0.S04: wrcmd2dqsstartlatency: 04
N0.C3.D1.R0.S02: wrcmd2dqsstartlatency: 04
N4.C3.D1.R0.S15: RdPtrOffsetTxDq: 05
N6.C3.D1.R0.S04: RdPtrOffsetTxDq: 05
N0.C3.D1.R0.S02: RdPtrOffsetTxDq: 06
N4.C3.D1.R0.S15: RdPtrOffsetTxDqs: 07
N6.C3.D1.R0.S04: RdPtrOffsetTxDqs: 06
N0.C3.D1.R0.S02: RdPtrOffsetTxDqs: 07
N4.C3.D1.R0.S15: PiTxDqs: 19
N6.C3.D1.R0.S04: PiTxDqs: 51
N0.C3.D1.R0.S02: PiTxDqs: 43
N4.C3.D1.R0.S16: wrcmd2dqsstartlatency: 04
N6.C3.D1.R0.S05: wrcmd2dqsstartlatency: 04
N0.C3.D1.R0.S03: wrcmd2dqsstartlatency: 04
N4.C3.D1.R0.S16: RdPtrOffsetTxDq: 06
N6.C3.D1.R0.S05: RdPtrOffsetTxDq: 05
N0.C3.D1.R0.S03: RdPtrOffsetTxDq: 05
N4.C3.D1.R0.S16: RdPtrOffsetTxDqs: 07
N6.C3.D1.R0.S05: RdPtrOffsetTxDqs: 07
N0.C3.D1.R0.S03: RdPtrOffsetTxDqs: 07
N4.C3.D1.R0.S16: PiTxDqs: 37
N6.C3.D1.R0.S05: PiTxDqs: 00
N0.C3.D1.R0.S03: PiTxDqs: 24
N4.C3.D1.R0.S17: wrcmd2dqsstartlatency: 04
N6.C3.D1.R0.S06: wrcmd2dqsstartlatency: 04
N0.C3.D1.R0.S04: wrcmd2dqsstartlatency: 04
N4.C3.D1.R0.S17: RdPtrOffsetTxDq: 05
N6.C3.D1.R0.S06: RdPtrOffsetTxDq: 05
N0.C3.D1.R0.S04: RdPtrOffsetTxDq: 05
N4.C3.D1.R0.S17: RdPtrOffsetTxDqs: 07
N6.C3.D1.R0.S06: RdPtrOffsetTxDqs: 07
N0.C3.D1.R0.S04: RdPtrOffsetTxDqs: 06
N4.C3.D1.R0.S17: PiTxDqs: 08
N6.C3.D1.R0.S06: PiTxDqs: 15
N0.C3.D1.R0.S04: PiTxDqs: 54
N4.C3.D1.R0.S00: RdPtrOffsetTxDq: 07
N6.C3.D1.R0.S07: wrcmd2dqsstartlatency: 04
N0.C3.D1.R0.S05: wrcmd2dqsstartlatency: 04
N4.C3.D1.R0.S01: RdPtrOffsetTxDq: 07
N6.C3.D1.R0.S07: RdPtrOffsetTxDq: 05
N0.C3.D1.R0.S05: RdPtrOffsetTxDq: 05
N4.C3.D1.R0.S02: RdPtrOffsetTxDq: 07
N6.C3.D1.R0.S07: RdPtrOffsetTxDqs: 07
N0.C3.D1.R0.S05: RdPtrOffsetTxDqs: 07
N4.C3.D1.R0.S03: RdPtrOffsetTxDq: 06
N6.C3.D1.R0.S07: PiTxDqs: 33
N0.C3.D1.R0.S05: PiTxDqs: 03
N4.C3.D1.R0.S04: RdPtrOffsetTxDq: 06
N6.C3.D1.R0.S08: wrcmd2dqsstartlatency: 04
N0.C3.D1.R0.S06: wrcmd2dqsstartlatency: 04
N4.C3.D1.R0.S05: RdPtrOffsetTxDq: 06
N6.C3.D1.R0.S08: RdPtrOffsetTxDq: 05
N0.C3.D1.R0.S06: RdPtrOffsetTxDq: 05
N4.C3.D1.R0.S06: RdPtrOffsetTxDq: 06
N6.C3.D1.R0.S08: RdPtrOffsetTxDqs: 07
N0.C3.D1.R0.S06: RdPtrOffsetTxDqs: 07
N4.C3.D1.R0.S07: RdPtrOffsetTxDq: 06
N6.C3.D1.R0.S08: PiTxDqs: 03
N0.C3.D1.R0.S06: PiTxDqs: 17
N4.C3.D1.R0.S08: RdPtrOffsetTxDq: 06
N6.C3.D1.R0.S09: wrcmd2dqsstartlatency: 04
N0.C3.D1.R0.S07: wrcmd2dqsstartlatency: 04
N4.C3.D1.R0.S09: RdPtrOffsetTxDq: 07
N6.C3.D1.R0.S09: RdPtrOffsetTxDq: 06
N0.C3.D1.R0.S07: RdPtrOffsetTxDq: 06
N4.C3.D1.R0.S10: RdPtrOffsetTxDq: 07
N6.C3.D1.R0.S09: RdPtrOffsetTxDqs: 08
N0.C3.D1.R0.S07: RdPtrOffsetTxDqs: 07
N4.C3.D1.R0.S11: RdPtrOffsetTxDq: 07
N6.C3.D1.R0.S09: PiTxDqs: 02
N0.C3.D1.R0.S07: PiTxDqs: 36
N4.C3.D1.R0.S12: RdPtrOffsetTxDq: 06
N6.C3.D1.R0.S10: wrcmd2dqsstartlatency: 04
N0.C3.D1.R0.S08: wrcmd2dqsstartlatency: 04
N4.C3.D1.R0.S13: RdPtrOffsetTxDq: 06
N6.C3.D1.R0.S10: RdPtrOffsetTxDq: 06
N0.C3.D1.R0.S08: RdPtrOffsetTxDq: 05
N4.C3.D1.R0.S14: RdPtrOffsetTxDq: 06
N6.C3.D1.R0.S10: RdPtrOffsetTxDqs: 07
N0.C3.D1.R0.S08: RdPtrOffsetTxDqs: 07
N4.C3.D1.R0.S15: RdPtrOffsetTxDq: 06
N6.C3.D1.R0.S10: PiTxDqs: 47
N0.C3.D1.R0.S08: PiTxDqs: 04
N4.C3.D1.R0.S16: RdPtrOffsetTxDq: 07
N6.C3.D1.R0.S11: wrcmd2dqsstartlatency: 04
N0.C3.D1.R0.S09: wrcmd2dqsstartlatency: 04
N4.C3.D1.R0.S17: RdPtrOffsetTxDq: 06
N6.C3.D1.R0.S11: RdPtrOffsetTxDq: 06
N0.C3.D1.R0.S09: RdPtrOffsetTxDq: 06
N4.C3.D1.R0.S00: RdPtrOffsetTxDq: 08
N6.C3.D1.R0.S11: RdPtrOffsetTxDqs: 07
N0.C3.D1.R0.S09: RdPtrOffsetTxDqs: 08
START_DATA_TX_DQ_ADV
Results for N2.C0.D0.R0: 
           0   1   2   3   4   5   6   7   8   9  10  11  12  13  14  15  16  17
-------------------------------------------------------------------------------
Vref offset: 0
Left:    -24 -26 -22 -24 -26 -23 -24 -23 -24 -25 -26 -23 -25 -27 -23 -25 -23 -24
Right:    25  27  29  27  24  28  26  26  23  24  26  28  25  23  26  27  27  22
-------------------------------------------------------------------------------
Prev Pi: 467 443 431 415 383 399 407 418 396 464 443 433 417 385 401 404 418 395
New Pi:  467 443 434 416 382 401 408 419 396 464 443 435 417 383 402 405 420 394
Diff:      0   0   3   1  -1   2   1   1   0   0   0   2   0  -2   1   1   2  -1

Results for N2.C0.D0.R1: 
           0   1   2   3   4   5   6   7   8   9  10  11  12  13  14  15  16  17
-------------------------------------------------------------------------------
Vref offset: 0
Left:    -25 -24 -22 -22 -25 -23 -22 -24 -23 -25 -26 -23 -26 -26 -23 -25 -22 -26
Right:    27  25  28  27  23  28  26  25  23  24  25  28  26  24  26  27  26  24
-------------------------------------------------------------------------------
Prev Pi: 467 443 431 415 383 399 407 418 396 464 443 433 417 385 401 404 418 395
New Pi:  468 443 434 417 382 401 409 418 396 464 443 435 417 384 402 405 420 394
Diff:      1   0   3   2  -1   2   2   0   0   0   0   2   0  -1   1   1   2  -1

Results for N2.C0.D1.R0: 
           0   1   2   3   4   5   6   7   8   9  10  11  12  13  14  15  16  17
-------------------------------------------------------------------------------
Vref offset: 0
Left:    -25 -24 -24 -24 -25 -24 -22 -20 -24 -23 -25 -23 -22 -27 -23 -23 -22 -24
Right:    24  25  24  24  21  24  23  25  22  25  23  24  23  22  23  25  25  23
-------------------------------------------------------------------------------
Prev Pi: 471 452 438 424 390 408 412 427 399 468 452 440 425 391 409 411 427 398
New Pi:  471 452 438 424 388 408 412 429 398 469 451 440 425 389 409 412 428 398
Diff:      0   0   0   0  -2   0   0   2  -1   1  -1   0   0  -2   0   1   1   0

Results for N2.C0.D1.R1: 
           0   1   2   3   4   5   6   7   8   9  10  11  12  13  14  15  16  17
-------------------------------------------------------------------------------
Vref offset: 0
Left:    -27 -22 -23 -21 -22 -22 -21 -20 -24 -24 -25 -24 -22 -27 -24 -22 -22 -24
Right:    24  24  23  24  21  23  23  24  19  25  24  24  25  23  25  26  25  24
-------------------------------------------------------------------------------
Prev Pi: 471 452 438 424 390 408 412 427 399 468 452 440 425 391 409 411 427 398
New Pi:  470 453 438 425 390 408 413 429 397 468 452 440 426 389 409 413 428 398
Diff:     -1   1   0   1   0   0   1   2  -2   0   0   0   1  -2   0   2   1   0

Results for N2.C1.D0.R0: 
           0   1   2   3   4   5   6   7   8   9  10  11  12  13  14  15  16  17
-------------------------------------------------------------------------------
Vref offset: 0
Left:    -23 -24 -23 -24 -24 -21 -23 -21 -23 -23 -25 -24 -23 -26 -20 -23 -21 -23
Right:    25  25  25  26  26  27  24  27  26  23  25  25  26  25  26  24  26  27
-------------------------------------------------------------------------------
Prev Pi: 464 444 439 422 389 401 416 430 402 463 445 441 422 390 402 417 433 403
New Pi:  465 444 440 423 390 404 416 433 403 463 445 441 423 390 405 417 435 405
Diff:      1   0   1   1   1   3   0   3   1   0   0   0   1   0   3   0   2   2

Results for N2.C1.D0.R1: 
           0   1   2   3   4   5   6   7   8   9  10  11  12  13  14  15  16  17
-------------------------------------------------------------------------------
Vref offset: 0
Left:    -23 -22 -24 -23 -23 -19 -23 -21 -23 -24 -25 -25 -23 -26 -20 -24 -19 -23
Right:    25  25  25  26  25  28  23  26  26  23  23  25  26  26  29  24  25  27
-------------------------------------------------------------------------------
Prev Pi: 464 444 439 422 389 401 416 430 402 463 445 441 422 390 402 417 433 403
New Pi:  465 445 439 423 390 405 416 432 403 463 444 441 423 390 406 417 436 405
Diff:      1   1   0   1   1   4   0   2   1   0  -1   0   1   0   4   0   3   2

Results for N2.C1.D1.R0: 
           0   1   2   3   4   5   6   7   8   9  10  11  12  13  14  15  16  17
-------------------------------------------------------------------------------
Vref offset: 0
Left:    -20 -22 -23 -23 -22 -18 -22 -19 -22 -20 -21 -21 -21 -21 -19 -22 -18 -23
Right:    23  23  22  23  21  24  20  24  22  22  23  24  22  24  22  23  24  25
-------------------------------------------------------------------------------
Prev Pi: 469 451 444 428 396 409 423 439 407 468 451 446 430 395 410 423 440 407
New Pi:  470 451 444 428 396 412 422 441 407 469 452 447 430 396 411 423 443 408
Diff:      1   0   0   0   0   3  -1   2   0   1   1   1   0   1   1   0   3   1

Results for N2.C1.D1.R1: 
           0   1   2   3   4   5   6   7   8   9  10  11  12  13  14  15  16  17
-------------------------------------------------------------------------------
Vref offset: 0
Left:    -21 -20 -22 -20 -20 -20 -21 -19 -22 -20 -21 -23 -21 -22 -19 -22 -18 -23
Right:    23  23  21  22  23  25  20  23  20  22  24  22  24  25  23  23  24  24
-------------------------------------------------------------------------------
Prev Pi: 469 451 444 428 396 409 423 439 407 468 451 446 430 395 410 423 440 407
New Pi:  470 452 444 429 397 411 423 441 406 469 452 446 431 396 412 423 443 407
Diff:      1   1   0   1   1   2   0   2  -1   1   1   0   1   1   2   0   3   0

Results for N2.C2.D0.R0: 
           0   1   2   3   4   5   6   7   8   9  10  11  12  13  14  15  16  17
-------------------------------------------------------------------------------
Vref offset: 0
Left:    -25 -23 -24 -25 -25 -24 -25 -22 -25 -25 -26 -23 -26 -24 -25 -24 -24 -23
Right:    26  25  24  28  26  25  24  27  21  25  24  26  25  26  24  26  26  22
-------------------------------------------------------------------------------
Prev Pi: 463 447 439 417 380 405 406 426 398 461 447 437 419 379 406 405 428 397
New Pi:  463 448 439 418 380 405 406 428 396 461 446 438 419 380 406 406 429 397
Diff:      0   1   0   1   0   0   0   2  -2   0  -1   1   0   1   0   1   1   0

Results for N2.C2.D0.R1: 
           0   1   2   3   4   5   6   7   8   9  10  11  12  13  14  15  16  17
-------------------------------------------------------------------------------
Vref offset: 0
Left:    -26 -23 -23 -23 -23 -23 -24 -23 -26 -25 -26 -23 -26 -24 -25 -24 -23 -24
Right:    26  26  24  25  25  25  24  25  21  26  24  27  27  27  25  25  24  23
-------------------------------------------------------------------------------
Prev Pi: 463 447 439 417 380 405 406 426 398 461 447 437 419 379 406 405 428 397
New Pi:  463 448 439 418 381 406 406 427 396 461 446 439 419 380 406 405 428 397
Diff:      0   1   0   1   1   1   0   1  -2   0  -1   2   0   1   0   0   0   0

Results for N2.C2.D1.R0: 
           0   1   2   3   4   5   6   7   8   9  10  11  12  13  14  15  16  17
-------------------------------------------------------------------------------
Vref offset: 0
Left:    -24 -22 -24 -24 -22 -25 -22 -21 -22 -22 -22 -22 -25 -23 -25 -22 -21 -22
Right:    24  24  20  22  22  21  22  23  22  23  22  22  21  24  20  22  25  22
-------------------------------------------------------------------------------
Prev Pi: 466 451 441 426 385 414 409 433 397 461 451 441 425 385 413 410 432 397
New Pi:  466 452 439 425 385 412 409 434 397 461 451 441 423 385 411 410 434 397
Diff:      0   1  -2  -1   0  -2   0   1   0   0   0   0  -2   0  -2   0   2   0

Results for N2.C2.D1.R1: 
           0   1   2   3   4   5   6   7   8   9  10  11  12  13  14  15  16  17
-------------------------------------------------------------------------------
Vref offset: 0
Left:    -24 -21 -23 -22 -21 -24 -21 -22 -22 -23 -22 -25 -25 -23 -25 -23 -22 -24
Right:    24  23  18  22  23  20  23  22  21  24  22  22  21  25  20  23  23  23
-------------------------------------------------------------------------------
Prev Pi: 466 451 441 426 385 414 409 433 397 461 451 441 425 385 413 410 432 397
New Pi:  466 452 439 426 386 412 410 433 397 461 451 440 423 386 411 410 432 397
Diff:      0   1  -2   0   1  -2   1   0   0   0   0  -1  -2   1  -2   0   0   0

Results for N2.C3.D0.R0: 
           0   1   2   3   4   5   6   7   8   9  10  11  12  13  14  15  16  17
-------------------------------------------------------------------------------
Vref offset: 0
Left:    -24 -23 -25 -24 -24 -22 -21 -21 -25 -23 -21 -21 -24 -25 -22 -21 -23 -25
Right:    27  27  25  25  25  27  24  26  25  25  27  27  26  25  25  26  26  26
-------------------------------------------------------------------------------
Prev Pi: 467 450 442 425 391 404 418 434 409 466 451 443 426 391 405 419 434 409
New Pi:  468 452 442 425 391 406 419 436 409 467 454 446 427 391 406 421 435 409
Diff:      1   2   0   0   0   2   1   2   0   1   3   3   1   0   1   2   1   0

Results for N2.C3.D0.R1: 
           0   1   2   3   4   5   6   7   8   9  10  11  12  13  14  15  16  17
-------------------------------------------------------------------------------
Vref offset: 0
Left:    -23 -20 -23 -25 -24 -21 -20 -22 -24 -24 -22 -22 -24 -25 -22 -21 -23 -26
Right:    25  27  23  26  25  27  24  26  24  26  26  26  27  25  27  26  25  26
-------------------------------------------------------------------------------
Prev Pi: 467 450 442 425 391 404 418 434 409 466 451 443 426 391 405 419 434 409
New Pi:  468 453 442 425 391 407 420 436 409 467 453 445 427 391 407 421 435 409
Diff:      1   3   0   0   0   3   2   2   0   1   2   2   1   0   2   2   1   0

Results for N2.C3.D1.R0: 
           0   1   2   3   4   5   6   7   8   9  10  11  12  13  14  15  16  17
-------------------------------------------------------------------------------
Vref offset: 0
Left:    -22 -22 -23 -24 -24 -20 -22 -18 -21 -21 -20 -21 -23 -22 -19 -21 -19 -23
Right:    24  24  21  23  24  23  20  24  23  23  23  24  23  22  24  23  24  25
-------------------------------------------------------------------------------
Prev Pi: 474 457 448 431 396 411 423 441 412 471 456 448 432 397 409 424 440 411
New Pi:  475 458 447 431 396 412 422 444 413 472 457 449 432 397 411 425 442 412
Diff:      1   1  -1   0   0   1  -1   3   1   1   1   1   0   0   2   1   2   1

Results for N2.C3.D1.R1: 
           0   1   2   3   4   5   6   7   8   9  10  11  12  13  14  15  16  17
-------------------------------------------------------------------------------
Vref offset: 0
Left:    -22 -19 -22 -22 -21 -19 -22 -20 -20 -20 -20 -22 -23 -23 -19 -22 -20 -23
Right:    24  24  20  24  23  23  21  24  23  24  25  24  24  24  24  24  24  26
-------------------------------------------------------------------------------
Prev Pi: 474 457 448 431 396 411 423 441 412 471 456 448 432 397 409 424 440 411
New Pi:  475 459 447 432 397 413 423 443 413 473 458 449 432 397 411 425 442 412
Diff:      1   2  -1   1   1   2   0   2   1   2   2   1   0   0   2   1   2   1

STOP_DATA_TX_DQ_ADV
N4.C3.D1.R0.S01: RdPtrOffsetTxDq: 08
N6.C3.D1.R0.S11: PiTxDqs: 37
N0.C3.D1.R0.S09: PiTxDqs: 05
N2: RunTrainStep: Final status = 0
N4.C3.D1.R0.S02: RdPtrOffsetTxDq: 08
N6.C3.D1.R0.S12: wrcmd2dqsstartlatency: 04
N0.C3.D1.R0.S10: wrcmd2dqsstartlatency: 04

END - Wr Timing Centering 2D Training  Time         5906 ms
N4.C3.D1.R0.S03: RdPtrOffsetTxDq: 07
N6.C3.D1.R0.S12: RdPtrOffsetTxDq: 05
N0.C3.D1.R0.S10: RdPtrOffsetTxDq: 06

START - Rd Voltage Training
N4.C3.D1.R0.S04: RdPtrOffsetTxDq: 07
N6.C3.D1.R0.S12: RdPtrOffsetTxDqs: 07
N0.C3.D1.R0.S10: RdPtrOffsetTxDqs: 07
N2: RX Vref Training...
N4.C3.D1.R0.S05: RdPtrOffsetTxDq: 07
N6.C3.D1.R0.S12: PiTxDqs: 23
N0.C3.D1.R0.S10: PiTxDqs: 52
N2: GetMargins: Level = 1, group = 13, mode = 2, scope = 4
N4.C3.D1.R0.S06: RdPtrOffsetTxDq: 07
N6.C3.D1.R0.S13: wrcmd2dqsstartlatency: 04
N0.C3.D1.R0.S11: wrcmd2dqsstartlatency: 04
N4.C3.D1.R0.S07: RdPtrOffsetTxDq: 07
N6.C3.D1.R0.S13: RdPtrOffsetTxDq: 05
N0.C3.D1.R0.S11: RdPtrOffsetTxDq: 06
N4.C3.D1.R0.S08: RdPtrOffsetTxDq: 07
N6.C3.D1.R0.S13: RdPtrOffsetTxDqs: 06
N0.C3.D1.R0.S11: RdPtrOffsetTxDqs: 07
N4.C3.D1.R0.S09: RdPtrOffsetTxDq: 08
N6.C3.D1.R0.S13: PiTxDqs: 51
N0.C3.D1.R0.S11: PiTxDqs: 42
N4.C3.D1.R0.S10: RdPtrOffsetTxDq: 08
N6.C3.D1.R0.S14: wrcmd2dqsstartlatency: 04
N0.C3.D1.R0.S12: wrcmd2dqsstartlatency: 04
N4.C3.D1.R0.S11: RdPtrOffsetTxDq: 08
N6.C3.D1.R0.S14: RdPtrOffsetTxDq: 05
N0.C3.D1.R0.S12: RdPtrOffsetTxDq: 05
N4.C3.D1.R0.S12: RdPtrOffsetTxDq: 07
N6.C3.D1.R0.S14: RdPtrOffsetTxDqs: 07
N0.C3.D1.R0.S12: RdPtrOffsetTxDqs: 07
N4.C3.D1.R0.S13: RdPtrOffsetTxDq: 07
N6.C3.D1.R0.S14: PiTxDqs: 01
N0.C3.D1.R0.S12: PiTxDqs: 26
N4.C3.D1.R0.S14: RdPtrOffsetTxDq: 07
N6.C3.D1.R0.S15: wrcmd2dqsstartlatency: 04
N0.C3.D1.R0.S13: wrcmd2dqsstartlatency: 04
N4.C3.D1.R0.S15: RdPtrOffsetTxDq: 07
N6.C3.D1.R0.S15: RdPtrOffsetTxDq: 05
N0.C3.D1.R0.S13: RdPtrOffsetTxDq: 05
N4.C3.D1.R0.S16: RdPtrOffsetTxDq: 08
N6.C3.D1.R0.S15: RdPtrOffsetTxDqs: 07
N0.C3.D1.R0.S13: RdPtrOffsetTxDqs: 06
N4.C3.D1.R0.S17: RdPtrOffsetTxDq: 07
N6.C3.D1.R0.S15: PiTxDqs: 15
N0.C3.D1.R0.S13: PiTxDqs: 55
N4.C3.D1.R0.S00: Total Delay in PI ticks: TxDQ = 993
N6.C3.D1.R0.S16: wrcmd2dqsstartlatency: 04
N0.C3.D1.R0.S14: wrcmd2dqsstartlatency: 04
N4.C3.D1.R0.S01: Total Delay in PI ticks: TxDQ = 978
N6.C3.D1.R0.S16: RdPtrOffsetTxDq: 06
N0.C3.D1.R0.S14: RdPtrOffsetTxDq: 05
N4.C3.D1.R0.S02: Total Delay in PI ticks: TxDQ = 968
N6.C3.D1.R0.S16: RdPtrOffsetTxDqs: 07
N0.C3.D1.R0.S14: RdPtrOffsetTxDqs: 07
N4.C3.D1.R0.S03: Total Delay in PI ticks: TxDQ = 952
N6.C3.D1.R0.S16: PiTxDqs: 33
N0.C3.D1.R0.S14: PiTxDqs: 04
N4.C3.D1.R0.S04: Total Delay in PI ticks: TxDQ = 915
N6.C3.D1.R0.S17: wrcmd2dqsstartlatency: 04
N0.C3.D1.R0.S15: wrcmd2dqsstartlatency: 04
N4.C3.D1.R0.S05: Total Delay in PI ticks: TxDQ = 928
N6.C3.D1.R0.S17: RdPtrOffsetTxDq: 05
N0.C3.D1.R0.S15: RdPtrOffsetTxDq: 05
N4.C3.D1.R0.S06: Total Delay in PI ticks: TxDQ = 945
N6.C3.D1.R0.S17: RdPtrOffsetTxDqs: 07
N0.C3.D1.R0.S15: RdPtrOffsetTxDqs: 07
N4.C3.D1.R0.S07: Total Delay in PI ticks: TxDQ = 962
N6.C3.D1.R0.S17: PiTxDqs: 03
N0.C3.D1.R0.S15: PiTxDqs: 19
N4.C3.D1.R0.S08: Total Delay in PI ticks: TxDQ = 931
N6.C3.D1.R0.S00: RdPtrOffsetTxDq: 07
N0.C3.D1.R0.S16: wrcmd2dqsstartlatency: 04
N4.C3.D1.R0.S09: Total Delay in PI ticks: TxDQ = 990
N6.C3.D1.R0.S01: RdPtrOffsetTxDq: 07
N0.C3.D1.R0.S16: RdPtrOffsetTxDq: 05
N4.C3.D1.R0.S10: Total Delay in PI ticks: TxDQ = 978
N6.C3.D1.R0.S02: RdPtrOffsetTxDq: 07
N0.C3.D1.R0.S16: RdPtrOffsetTxDqs: 07
N4.C3.D1.R0.S11: Total Delay in PI ticks: TxDQ = 966
N6.C3.D1.R0.S03: RdPtrOffsetTxDq: 06
N0.C3.D1.R0.S16: PiTxDqs: 34
N4.C3.D1.R0.S12: Total Delay in PI ticks: TxDQ = 955
N6.C3.D1.R0.S04: RdPtrOffsetTxDq: 06
N0.C3.D1.R0.S17: wrcmd2dqsstartlatency: 04
N4.C3.D1.R0.S13: Total Delay in PI ticks: TxDQ = 915
N6.C3.D1.R0.S05: RdPtrOffsetTxDq: 06
N0.C3.D1.R0.S17: RdPtrOffsetTxDq: 05
N4.C3.D1.R0.S14: Total Delay in PI ticks: TxDQ = 932
N6.C3.D1.R0.S06: RdPtrOffsetTxDq: 06
N0.C3.D1.R0.S17: RdPtrOffsetTxDqs: 07
N4.C3.D1.R0.S15: Total Delay in PI ticks: TxDQ = 946
N6.C3.D1.R0.S07: RdPtrOffsetTxDq: 06
N0.C3.D1.R0.S17: PiTxDqs: 02
N4.C3.D1.R0.S16: Total Delay in PI ticks: TxDQ = 962
N6.C3.D1.R0.S08: RdPtrOffsetTxDq: 06
N0.C3.D1.R0.S00: RdPtrOffsetTxDq: 07
N4.C3.D1.R0.S17: Total Delay in PI ticks: TxDQ = 932
N6.C3.D1.R0.S09: RdPtrOffsetTxDq: 07
N0.C3.D1.R0.S01: RdPtrOffsetTxDq: 07
N4.C3.D1.R1.S00: wrcmd2dqsstartlatency: 04
N6.C3.D1.R0.S10: RdPtrOffsetTxDq: 07
N0.C3.D1.R0.S02: RdPtrOffsetTxDq: 07
N4.C3.D1.R1.S00: RdPtrOffsetTxDq: 06
N6.C3.D1.R0.S11: RdPtrOffsetTxDq: 07
N0.C3.D1.R0.S03: RdPtrOffsetTxDq: 06
N4.C3.D1.R1.S00: RdPtrOffsetTxDqs: 08
N6.C3.D1.R0.S12: RdPtrOffsetTxDq: 06
N0.C3.D1.R0.S04: RdPtrOffsetTxDq: 06
N4.C3.D1.R1.S00: PiTxDqs: 02
N6.C3.D1.R0.S13: RdPtrOffsetTxDq: 06
N0.C3.D1.R0.S05: RdPtrOffsetTxDq: 06
N4.C3.D1.R1.S01: wrcmd2dqsstartlatency: 04
N6.C3.D1.R0.S14: RdPtrOffsetTxDq: 06
N0.C3.D1.R0.S06: RdPtrOffsetTxDq: 06
N4.C3.D1.R1.S01: RdPtrOffsetTxDq: 06
N6.C3.D1.R0.S15: RdPtrOffsetTxDq: 06
N0.C3.D1.R0.S07: RdPtrOffsetTxDq: 07
N4.C3.D1.R1.S01: RdPtrOffsetTxDqs: 07
N6.C3.D1.R0.S16: RdPtrOffsetTxDq: 07
N0.C3.D1.R0.S08: RdPtrOffsetTxDq: 06
N4.C3.D1.R1.S01: PiTxDqs: 50
N6.C3.D1.R0.S17: RdPtrOffsetTxDq: 06
N0.C3.D1.R0.S09: RdPtrOffsetTxDq: 07
N4.C3.D1.R1.S02: wrcmd2dqsstartlatency: 04
N6.C3.D1.R0.S00: RdPtrOffsetTxDq: 08
N0.C3.D1.R0.S10: RdPtrOffsetTxDq: 07
N4.C3.D1.R1.S02: RdPtrOffsetTxDq: 06
N6.C3.D1.R0.S01: RdPtrOffsetTxDq: 08
N0.C3.D1.R0.S11: RdPtrOffsetTxDq: 07
N4.C3.D1.R1.S02: RdPtrOffsetTxDqs: 07
N6.C3.D1.R0.S02: RdPtrOffsetTxDq: 08
N0.C3.D1.R0.S12: RdPtrOffsetTxDq: 06
N4.C3.D1.R1.S02: PiTxDqs: 39
N6.C3.D1.R0.S03: RdPtrOffsetTxDq: 07
N0.C3.D1.R0.S13: RdPtrOffsetTxDq: 06
N4.C3.D1.R1.S03: wrcmd2dqsstartlatency: 04
N6.C3.D1.R0.S04: RdPtrOffsetTxDq: 07
N0.C3.D1.R0.S14: RdPtrOffsetTxDq: 06
N4.C3.D1.R1.S03: RdPtrOffsetTxDq: 05
N6.C3.D1.R0.S05: RdPtrOffsetTxDq: 07
N0.C3.D1.R0.S15: RdPtrOffsetTxDq: 06
N4.C3.D1.R1.S03: RdPtrOffsetTxDqs: 07
N6.C3.D1.R0.S06: RdPtrOffsetTxDq: 07
N0.C3.D1.R0.S16: RdPtrOffsetTxDq: 06
N4.C3.D1.R1.S03: PiTxDqs: 26
N6.C3.D1.R0.S07: RdPtrOffsetTxDq: 07
N0.C3.D1.R0.S17: RdPtrOffsetTxDq: 06
N4.C3.D1.R1.S04: wrcmd2dqsstartlatency: 04
N6.C3.D1.R0.S08: RdPtrOffsetTxDq: 07
N0.C3.D1.R0.S00: RdPtrOffsetTxDq: 08
N4.C3.D1.R1.S04: RdPtrOffsetTxDq: 05
N6.C3.D1.R0.S09: RdPtrOffsetTxDq: 08
N0.C3.D1.R0.S01: RdPtrOffsetTxDq: 08
N4.C3.D1.R1.S04: RdPtrOffsetTxDqs: 06
N6.C3.D1.R0.S10: RdPtrOffsetTxDq: 08
N0.C3.D1.R0.S02: RdPtrOffsetTxDq: 08
N4.C3.D1.R1.S04: PiTxDqs: 52
N6.C3.D1.R0.S11: RdPtrOffsetTxDq: 08
N0.C3.D1.R0.S03: RdPtrOffsetTxDq: 07
N4.C3.D1.R1.S05: wrcmd2dqsstartlatency: 04
N6.C3.D1.R0.S12: RdPtrOffsetTxDq: 07
N0.C3.D1.R0.S04: RdPtrOffsetTxDq: 07
N4.C3.D1.R1.S05: RdPtrOffsetTxDq: 05
N6.C3.D1.R0.S13: RdPtrOffsetTxDq: 07
N0.C3.D1.R0.S05: RdPtrOffsetTxDq: 07
N4.C3.D1.R1.S05: RdPtrOffsetTxDqs: 07
N6.C3.D1.R0.S14: RdPtrOffsetTxDq: 07
N0.C3.D1.R0.S06: RdPtrOffsetTxDq: 07
N4.C3.D1.R1.S05: PiTxDqs: 02
N6.C3.D1.R0.S15: RdPtrOffsetTxDq: 07
N0.C3.D1.R0.S07: RdPtrOffsetTxDq: 08
N4.C3.D1.R1.S06: wrcmd2dqsstartlatency: 04
N6.C3.D1.R0.S16: RdPtrOffsetTxDq: 08
N0.C3.D1.R0.S08: RdPtrOffsetTxDq: 07
N4.C3.D1.R1.S06: RdPtrOffsetTxDq: 05
N6.C3.D1.R0.S17: RdPtrOffsetTxDq: 07
N0.C3.D1.R0.S09: RdPtrOffsetTxDq: 08
N4.C3.D1.R1.S06: RdPtrOffsetTxDqs: 07
N6.C3.D1.R0.S00: Total Delay in PI ticks: TxDQ = 993
N0.C3.D1.R0.S10: RdPtrOffsetTxDq: 08
N4.C3.D1.R1.S06: PiTxDqs: 16
N6.C3.D1.R0.S01: Total Delay in PI ticks: TxDQ = 975
N0.C3.D1.R0.S11: RdPtrOffsetTxDq: 08
N4.C3.D1.R1.S07: wrcmd2dqsstartlatency: 04
N6.C3.D1.R0.S02: Total Delay in PI ticks: TxDQ = 964
N0.C3.D1.R0.S12: RdPtrOffsetTxDq: 07
N4.C3.D1.R1.S07: RdPtrOffsetTxDq: 05
N6.C3.D1.R0.S03: Total Delay in PI ticks: TxDQ = 949
N0.C3.D1.R0.S13: RdPtrOffsetTxDq: 07
N4.C3.D1.R1.S07: RdPtrOffsetTxDqs: 07
N6.C3.D1.R0.S04: Total Delay in PI ticks: TxDQ = 914
N0.C3.D1.R0.S14: RdPtrOffsetTxDq: 07
N4.C3.D1.R1.S07: PiTxDqs: 34
N6.C3.D1.R0.S05: Total Delay in PI ticks: TxDQ = 927
N0.C3.D1.R0.S15: RdPtrOffsetTxDq: 07
N4.C3.D1.R1.S08: wrcmd2dqsstartlatency: 04
N6.C3.D1.R0.S06: Total Delay in PI ticks: TxDQ = 942
N0.C3.D1.R0.S16: RdPtrOffsetTxDq: 07
N4.C3.D1.R1.S08: RdPtrOffsetTxDq: 05
N6.C3.D1.R0.S07: Total Delay in PI ticks: TxDQ = 959
N0.C3.D1.R0.S17: RdPtrOffsetTxDq: 07
N4.C3.D1.R1.S08: RdPtrOffsetTxDqs: 07
N6.C3.D1.R0.S08: Total Delay in PI ticks: TxDQ = 930
N0.C3.D1.R0.S00: Total Delay in PI ticks: TxDQ = 992
N4.C3.D1.R1.S08: PiTxDqs: 03
N6.C3.D1.R0.S09: Total Delay in PI ticks: TxDQ = 990
N0.C3.D1.R0.S01: Total Delay in PI ticks: TxDQ = 975
N4.C3.D1.R1.S09: wrcmd2dqsstartlatency: 04
N6.C3.D1.R0.S10: Total Delay in PI ticks: TxDQ = 974
N0.C3.D1.R0.S02: Total Delay in PI ticks: TxDQ = 968
N4.C3.D1.R1.S09: RdPtrOffsetTxDq: 06
N6.C3.D1.R0.S11: Total Delay in PI ticks: TxDQ = 966
N0.C3.D1.R0.S03: Total Delay in PI ticks: TxDQ = 949
N4.C3.D1.R1.S09: RdPtrOffsetTxDqs: 08
N6.C3.D1.R0.S12: Total Delay in PI ticks: TxDQ = 950
N0.C3.D1.R0.S04: Total Delay in PI ticks: TxDQ = 915
N4.C3.D1.R1.S09: PiTxDqs: 01
N6.C3.D1.R0.S13: Total Delay in PI ticks: TxDQ = 914
N0.C3.D1.R0.S05: Total Delay in PI ticks: TxDQ = 929
N4.C3.D1.R1.S10: wrcmd2dqsstartlatency: 04
N6.C3.D1.R0.S14: Total Delay in PI ticks: TxDQ = 930
N0.C3.D1.R0.S06: Total Delay in PI ticks: TxDQ = 941
N4.C3.D1.R1.S10: RdPtrOffsetTxDq: 06
N6.C3.D1.R0.S15: Total Delay in PI ticks: TxDQ = 942
N0.C3.D1.R0.S07: Total Delay in PI ticks: TxDQ = 961
N4.C3.D1.R1.S10: RdPtrOffsetTxDqs: 07
N6.C3.D1.R0.S16: Total Delay in PI ticks: TxDQ = 961
N0.C3.D1.R0.S08: Total Delay in PI ticks: TxDQ = 930
N4.C3.D1.R1.S10: PiTxDqs: 51
N6.C3.D1.R0.S17: Total Delay in PI ticks: TxDQ = 929
N0.C3.D1.R0.S09: Total Delay in PI ticks: TxDQ = 992
N4.C3.D1.R1.S11: wrcmd2dqsstartlatency: 04
N6.C3.D1.R1.S00: wrcmd2dqsstartlatency: 04
N0.C3.D1.R0.S10: Total Delay in PI ticks: TxDQ = 978
N4.C3.D1.R1.S11: RdPtrOffsetTxDq: 06
N6.C3.D1.R1.S00: RdPtrOffsetTxDq: 06
N0.C3.D1.R0.S11: Total Delay in PI ticks: TxDQ = 967
N4.C3.D1.R1.S11: RdPtrOffsetTxDqs: 07
N6.C3.D1.R1.S00: RdPtrOffsetTxDqs: 07
N0.C3.D1.R0.S12: Total Delay in PI ticks: TxDQ = 950
N4.C3.D1.R1.S11: PiTxDqs: 40
N6.C3.D1.R1.S00: PiTxDqs: 60
N0.C3.D1.R0.S13: Total Delay in PI ticks: TxDQ = 916
N4.C3.D1.R1.S12: wrcmd2dqsstartlatency: 04
N6.C3.D1.R1.S01: wrcmd2dqsstartlatency: 04
N0.C3.D1.R0.S14: Total Delay in PI ticks: TxDQ = 931
N4.C3.D1.R1.S12: RdPtrOffsetTxDq: 05
N6.C3.D1.R1.S01: RdPtrOffsetTxDq: 06
N0.C3.D1.R0.S15: Total Delay in PI ticks: TxDQ = 943
N4.C3.D1.R1.S12: RdPtrOffsetTxDqs: 07
N6.C3.D1.R1.S01: RdPtrOffsetTxDqs: 07
N0.C3.D1.R0.S16: Total Delay in PI ticks: TxDQ = 960
N4.C3.D1.R1.S12: PiTxDqs: 28
N6.C3.D1.R1.S01: PiTxDqs: 43
N0.C3.D1.R0.S17: Total Delay in PI ticks: TxDQ = 929
N4.C3.D1.R1.S13: wrcmd2dqsstartlatency: 04
N6.C3.D1.R1.S02: wrcmd2dqsstartlatency: 04
N0.C3.D1.R1.S00: wrcmd2dqsstartlatency: 04
N4.C3.D1.R1.S13: RdPtrOffsetTxDq: 05
N6.C3.D1.R1.S02: RdPtrOffsetTxDq: 05
N0.C3.D1.R1.S00: RdPtrOffsetTxDq: 06
N4.C3.D1.R1.S13: RdPtrOffsetTxDqs: 06
N6.C3.D1.R1.S02: RdPtrOffsetTxDqs: 07
N0.C3.D1.R1.S00: RdPtrOffsetTxDqs: 08
N4.C3.D1.R1.S13: PiTxDqs: 55
N6.C3.D1.R1.S02: PiTxDqs: 32
N0.C3.D1.R1.S00: PiTxDqs: 02
N4.C3.D1.R1.S14: wrcmd2dqsstartlatency: 04
N6.C3.D1.R1.S03: wrcmd2dqsstartlatency: 04
N0.C3.D1.R1.S01: wrcmd2dqsstartlatency: 04
N4.C3.D1.R1.S14: RdPtrOffsetTxDq: 05
N6.C3.D1.R1.S03: RdPtrOffsetTxDq: 05
N0.C3.D1.R1.S01: RdPtrOffsetTxDq: 06
N4.C3.D1.R1.S14: RdPtrOffsetTxDqs: 07
N6.C3.D1.R1.S03: RdPtrOffsetTxDqs: 07
N0.C3.D1.R1.S01: RdPtrOffsetTxDqs: 07
N4.C3.D1.R1.S14: PiTxDqs: 03
N6.C3.D1.R1.S03: PiTxDqs: 20
N0.C3.D1.R1.S01: PiTxDqs: 49
N4.C3.D1.R1.S15: wrcmd2dqsstartlatency: 04
N6.C3.D1.R1.S04: wrcmd2dqsstartlatency: 04
N0.C3.D1.R1.S02: wrcmd2dqsstartlatency: 04
N4.C3.D1.R1.S15: RdPtrOffsetTxDq: 05
N6.C3.D1.R1.S04: RdPtrOffsetTxDq: 05
N0.C3.D1.R1.S02: RdPtrOffsetTxDq: 06
N4.C3.D1.R1.S15: RdPtrOffsetTxDqs: 07
N6.C3.D1.R1.S04: RdPtrOffsetTxDqs: 06
N0.C3.D1.R1.S02: RdPtrOffsetTxDqs: 07
N4.C3.D1.R1.S15: PiTxDqs: 17
N6.C3.D1.R1.S04: PiTxDqs: 48
N0.C3.D1.R1.S02: PiTxDqs: 38
N4.C3.D1.R1.S16: wrcmd2dqsstartlatency: 04
N6.C3.D1.R1.S05: wrcmd2dqsstartlatency: 04
N0.C3.D1.R1.S03: wrcmd2dqsstartlatency: 04
N4.C3.D1.R1.S16: RdPtrOffsetTxDq: 05
N6.C3.D1.R1.S05: RdPtrOffsetTxDq: 05
N0.C3.D1.R1.S03: RdPtrOffsetTxDq: 05
N4.C3.D1.R1.S16: RdPtrOffsetTxDqs: 07
N6.C3.D1.R1.S05: RdPtrOffsetTxDqs: 06
N0.C3.D1.R1.S03: RdPtrOffsetTxDqs: 07
N4.C3.D1.R1.S16: PiTxDqs: 36
N6.C3.D1.R1.S05: PiTxDqs: 61
N0.C3.D1.R1.S03: PiTxDqs: 24
N4.C3.D1.R1.S17: wrcmd2dqsstartlatency: 04
N6.C3.D1.R1.S06: wrcmd2dqsstartlatency: 04
N0.C3.D1.R1.S04: wrcmd2dqsstartlatency: 04
N4.C3.D1.R1.S17: RdPtrOffsetTxDq: 05
N6.C3.D1.R1.S06: RdPtrOffsetTxDq: 05
N0.C3.D1.R1.S04: RdPtrOffsetTxDq: 05
N4.C3.D1.R1.S17: RdPtrOffsetTxDqs: 07
N6.C3.D1.R1.S06: RdPtrOffsetTxDqs: 07
N0.C3.D1.R1.S04: RdPtrOffsetTxDqs: 06
N4.C3.D1.R1.S17: PiTxDqs: 03
N6.C3.D1.R1.S06: PiTxDqs: 11
N0.C3.D1.R1.S04: PiTxDqs: 52
N4.C3.D1.R1.S00: RdPtrOffsetTxDq: 07
N6.C3.D1.R1.S07: wrcmd2dqsstartlatency: 04
N0.C3.D1.R1.S05: wrcmd2dqsstartlatency: 04
N4.C3.D1.R1.S01: RdPtrOffsetTxDq: 07
N6.C3.D1.R1.S07: RdPtrOffsetTxDq: 05
N0.C3.D1.R1.S05: RdPtrOffsetTxDq: 05
N4.C3.D1.R1.S02: RdPtrOffsetTxDq: 07
N6.C3.D1.R1.S07: RdPtrOffsetTxDqs: 07
N0.C3.D1.R1.S05: RdPtrOffsetTxDqs: 07
N4.C3.D1.R1.S03: RdPtrOffsetTxDq: 06
N6.C3.D1.R1.S07: PiTxDqs: 28
N0.C3.D1.R1.S05: PiTxDqs: 01
N4.C3.D1.R1.S04: RdPtrOffsetTxDq: 06
N6.C3.D1.R1.S08: wrcmd2dqsstartlatency: 04
N0.C3.D1.R1.S06: wrcmd2dqsstartlatency: 04
N4.C3.D1.R1.S05: RdPtrOffsetTxDq: 06
N6.C3.D1.R1.S08: RdPtrOffsetTxDq: 05
N0.C3.D1.R1.S06: RdPtrOffsetTxDq: 05
N4.C3.D1.R1.S06: RdPtrOffsetTxDq: 06
N6.C3.D1.R1.S08: RdPtrOffsetTxDqs: 06
N0.C3.D1.R1.S06: RdPtrOffsetTxDqs: 07
N4.C3.D1.R1.S07: RdPtrOffsetTxDq: 06
N6.C3.D1.R1.S08: PiTxDqs: 61
N0.C3.D1.R1.S06: PiTxDqs: 14
N4.C3.D1.R1.S08: RdPtrOffsetTxDq: 06
N6.C3.D1.R1.S09: wrcmd2dqsstartlatency: 04
N0.C3.D1.R1.S07: wrcmd2dqsstartlatency: 04
N4.C3.D1.R1.S09: RdPtrOffsetTxDq: 07
N6.C3.D1.R1.S09: RdPtrOffsetTxDq: 06
N0.C3.D1.R1.S07: RdPtrOffsetTxDq: 05
N4.C3.D1.R1.S10: RdPtrOffsetTxDq: 07
N6.C3.D1.R1.S09: RdPtrOffsetTxDqs: 07
N0.C3.D1.R1.S07: RdPtrOffsetTxDqs: 07
N4.C3.D1.R1.S11: RdPtrOffsetTxDq: 07
N6.C3.D1.R1.S09: PiTxDqs: 59
N0.C3.D1.R1.S07: PiTxDqs: 34
N4.C3.D1.R1.S12: RdPtrOffsetTxDq: 06
N6.C3.D1.R1.S10: wrcmd2dqsstartlatency: 04
N0.C3.D1.R1.S08: wrcmd2dqsstartlatency: 04
N4.C3.D1.R1.S13: RdPtrOffsetTxDq: 06
N6.C3.D1.R1.S10: RdPtrOffsetTxDq: 06
N0.C3.D1.R1.S08: RdPtrOffsetTxDq: 05
N4.C3.D1.R1.S14: RdPtrOffsetTxDq: 06
N6.C3.D1.R1.S10: RdPtrOffsetTxDqs: 07
N0.C3.D1.R1.S08: RdPtrOffsetTxDqs: 07
N4.C3.D1.R1.S15: RdPtrOffsetTxDq: 06
N6.C3.D1.R1.S10: PiTxDqs: 43
N0.C3.D1.R1.S08: PiTxDqs: 01
N4.C3.D1.R1.S16: RdPtrOffsetTxDq: 06
N6.C3.D1.R1.S11: wrcmd2dqsstartlatency: 04
N0.C3.D1.R1.S09: wrcmd2dqsstartlatency: 04
N4.C3.D1.R1.S17: RdPtrOffsetTxDq: 06
N6.C3.D1.R1.S11: RdPtrOffsetTxDq: 06
N0.C3.D1.R1.S09: RdPtrOffsetTxDq: 06
N4.C3.D1.R1.S00: RdPtrOffsetTxDq: 08
N6.C3.D1.R1.S11: RdPtrOffsetTxDqs: 07
N0.C3.D1.R1.S09: RdPtrOffsetTxDqs: 08
N4.C3.D1.R1.S01: RdPtrOffsetTxDq: 08
N6.C3.D1.R1.S11: PiTxDqs: 35
N0.C3.D1.R1.S09: PiTxDqs: 01
N4.C3.D1.R1.S02: RdPtrOffsetTxDq: 08
N6.C3.D1.R1.S12: wrcmd2dqsstartlatency: 04
N0.C3.D1.R1.S10: wrcmd2dqsstartlatency: 04
N4.C3.D1.R1.S03: RdPtrOffsetTxDq: 07
N6.C3.D1.R1.S12: RdPtrOffsetTxDq: 05
N0.C3.D1.R1.S10: RdPtrOffsetTxDq: 06
N4.C3.D1.R1.S04: RdPtrOffsetTxDq: 07
N6.C3.D1.R1.S12: RdPtrOffsetTxDqs: 07
N0.C3.D1.R1.S10: RdPtrOffsetTxDqs: 07
N4.C3.D1.R1.S05: RdPtrOffsetTxDq: 07
N6.C3.D1.R1.S12: PiTxDqs: 20
N0.C3.D1.R1.S10: PiTxDqs: 50
N4.C3.D1.R1.S06: RdPtrOffsetTxDq: 07
N6.C3.D1.R1.S13: wrcmd2dqsstartlatency: 04
N0.C3.D1.R1.S11: wrcmd2dqsstartlatency: 04
N4.C3.D1.R1.S07: RdPtrOffsetTxDq: 07
N6.C3.D1.R1.S13: RdPtrOffsetTxDq: 05
N0.C3.D1.R1.S11: RdPtrOffsetTxDq: 06
N4.C3.D1.R1.S08: RdPtrOffsetTxDq: 07
N6.C3.D1.R1.S13: RdPtrOffsetTxDqs: 06
N0.C3.D1.R1.S11: RdPtrOffsetTxDqs: 07
N4.C3.D1.R1.S09: RdPtrOffsetTxDq: 08
N6.C3.D1.R1.S13: PiTxDqs: 47
N0.C3.D1.R1.S11: PiTxDqs: 38
N4.C3.D1.R1.S10: RdPtrOffsetTxDq: 08
N6.C3.D1.R1.S14: wrcmd2dqsstartlatency: 04
N0.C3.D1.R1.S12: wrcmd2dqsstartlatency: 04
N4.C3.D1.R1.S11: RdPtrOffsetTxDq: 08
N6.C3.D1.R1.S14: RdPtrOffsetTxDq: 05
N0.C3.D1.R1.S12: RdPtrOffsetTxDq: 05
N4.C3.D1.R1.S12: RdPtrOffsetTxDq: 07
N6.C3.D1.R1.S14: RdPtrOffsetTxDqs: 06
N0.C3.D1.R1.S12: RdPtrOffsetTxDqs: 07
N4.C3.D1.R1.S13: RdPtrOffsetTxDq: 07
N6.C3.D1.R1.S14: PiTxDqs: 61
N0.C3.D1.R1.S12: PiTxDqs: 25
N4.C3.D1.R1.S14: RdPtrOffsetTxDq: 07
N6.C3.D1.R1.S15: wrcmd2dqsstartlatency: 04
N0.C3.D1.R1.S13: wrcmd2dqsstartlatency: 04
N4.C3.D1.R1.S15: RdPtrOffsetTxDq: 07
N6.C3.D1.R1.S15: RdPtrOffsetTxDq: 05
N0.C3.D1.R1.S13: RdPtrOffsetTxDq: 05
N4.C3.D1.R1.S16: RdPtrOffsetTxDq: 07
N6.C3.D1.R1.S15: RdPtrOffsetTxDqs: 07
N0.C3.D1.R1.S13: RdPtrOffsetTxDqs: 06
N4.C3.D1.R1.S17: RdPtrOffsetTxDq: 07
N6.C3.D1.R1.S15: PiTxDqs: 09
N0.C3.D1.R1.S13: PiTxDqs: 55
N4.C3.D1.R1.S00: Total Delay in PI ticks: TxDQ = 991
N6.C3.D1.R1.S16: wrcmd2dqsstartlatency: 04
N0.C3.D1.R1.S14: wrcmd2dqsstartlatency: 04
N4.C3.D1.R1.S01: Total Delay in PI ticks: TxDQ = 976
N6.C3.D1.R1.S16: RdPtrOffsetTxDq: 05
N0.C3.D1.R1.S14: RdPtrOffsetTxDq: 05
N4.C3.D1.R1.S02: Total Delay in PI ticks: TxDQ = 964
N6.C3.D1.R1.S16: RdPtrOffsetTxDqs: 07
N0.C3.D1.R1.S14: RdPtrOffsetTxDqs: 07
N4.C3.D1.R1.S03: Total Delay in PI ticks: TxDQ = 949
N6.C3.D1.R1.S16: PiTxDqs: 27
N0.C3.D1.R1.S14: PiTxDqs: 02
N4.C3.D1.R1.S04: Total Delay in PI ticks: TxDQ = 911
N6.C3.D1.R1.S17: wrcmd2dqsstartlatency: 04
N0.C3.D1.R1.S15: wrcmd2dqsstartlatency: 04
N4.C3.D1.R1.S05: Total Delay in PI ticks: TxDQ = 929
N6.C3.D1.R1.S17: RdPtrOffsetTxDq: 05
N0.C3.D1.R1.S15: RdPtrOffsetTxDq: 05
N4.C3.D1.R1.S06: Total Delay in PI ticks: TxDQ = 940
N6.C3.D1.R1.S17: RdPtrOffsetTxDqs: 06
N0.C3.D1.R1.S15: RdPtrOffsetTxDqs: 07
N4.C3.D1.R1.S07: Total Delay in PI ticks: TxDQ = 958
N6.C3.D1.R1.S17: PiTxDqs: 61
N0.C3.D1.R1.S15: PiTxDqs: 16
N4.C3.D1.R1.S08: Total Delay in PI ticks: TxDQ = 927
N6.C3.D1.R1.S00: RdPtrOffsetTxDq: 07
N0.C3.D1.R1.S16: wrcmd2dqsstartlatency: 04
N4.C3.D1.R1.S09: Total Delay in PI ticks: TxDQ = 987
N6.C3.D1.R1.S01: RdPtrOffsetTxDq: 07
N0.C3.D1.R1.S16: RdPtrOffsetTxDq: 05
N4.C3.D1.R1.S10: Total Delay in PI ticks: TxDQ = 976
N6.C3.D1.R1.S02: RdPtrOffsetTxDq: 06
N0.C3.D1.R1.S16: RdPtrOffsetTxDqs: 07
N4.C3.D1.R1.S11: Total Delay in PI ticks: TxDQ = 962
N6.C3.D1.R1.S03: RdPtrOffsetTxDq: 06
N0.C3.D1.R1.S16: PiTxDqs: 30
N4.C3.D1.R1.S12: Total Delay in PI ticks: TxDQ = 952
N6.C3.D1.R1.S04: RdPtrOffsetTxDq: 06
N0.C3.D1.R1.S17: wrcmd2dqsstartlatency: 04
N4.C3.D1.R1.S13: Total Delay in PI ticks: TxDQ = 914
N6.C3.D1.R1.S05: RdPtrOffsetTxDq: 06
N0.C3.D1.R1.S17: RdPtrOffsetTxDq: 05
N4.C3.D1.R1.S14: Total Delay in PI ticks: TxDQ = 929
N6.C3.D1.R1.S06: RdPtrOffsetTxDq: 06
N0.C3.D1.R1.S17: RdPtrOffsetTxDqs: 07
N4.C3.D1.R1.S15: Total Delay in PI ticks: TxDQ = 942
N6.C3.D1.R1.S07: RdPtrOffsetTxDq: 06
N0.C3.D1.R1.S17: PiTxDqs: 01
N4.C3.D1.R1.S16: Total Delay in PI ticks: TxDQ = 961
N6.C3.D1.R1.S08: RdPtrOffsetTxDq: 06
N0.C3.D1.R1.S00: RdPtrOffsetTxDq: 07
N4.C3.D1.R1.S17: Total Delay in PI ticks: TxDQ = 927
N6.C3.D1.R1.S09: RdPtrOffsetTxDq: 07
N0.C3.D1.R1.S01: RdPtrOffsetTxDq: 07
N4.C3: Calculating Optimimum DQ/DQS Values
N6.C3.D1.R1.S10: RdPtrOffsetTxDq: 07
N0.C3.D1.R1.S02: RdPtrOffsetTxDq: 07
N6.C3.D1.R1.S11: RdPtrOffsetTxDq: 07
N0.C3.D1.R1.S03: RdPtrOffsetTxDq: 06
N6.C3.D1.R1.S12: RdPtrOffsetTxDq: 06
N0.C3.D1.R1.S04: RdPtrOffsetTxDq: 06
N6.C3.D1.R1.S13: RdPtrOffsetTxDq: 06
N0.C3.D1.R1.S05: RdPtrOffsetTxDq: 06
START_DATA_TX_DQ
N6.C3.D1.R1.S14: RdPtrOffsetTxDq: 06
N0.C3.D1.R1.S06: RdPtrOffsetTxDq: 06
N4.C3.S00: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 009, RdPtrOffsetTxDqs = 009
N6.C3.D1.R1.S15: RdPtrOffsetTxDq: 06
N0.C3.D1.R1.S07: RdPtrOffsetTxDq: 06
N4.C3.S00: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 009, RdPtrOffsetTxDqs = 009
N6.C3.D1.R1.S16: RdPtrOffsetTxDq: 06
N0.C3.D1.R1.S08: RdPtrOffsetTxDq: 06
N4.C3.S01: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 009, RdPtrOffsetTxDqs = 009
N6.C3.D1.R1.S17: RdPtrOffsetTxDq: 06
N0.C3.D1.R1.S09: RdPtrOffsetTxDq: 07
N4.C3.S01: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 009, RdPtrOffsetTxDqs = 009
N6.C3.D1.R1.S00: RdPtrOffsetTxDq: 08
N0.C3.D1.R1.S10: RdPtrOffsetTxDq: 07
N4.C3.S02: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 009
N6.C3.D1.R1.S01: RdPtrOffsetTxDq: 08
N0.C3.D1.R1.S11: RdPtrOffsetTxDq: 07
N4.C3.S02: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 009
N6.C3.D1.R1.S02: RdPtrOffsetTxDq: 07
N0.C3.D1.R1.S12: RdPtrOffsetTxDq: 06
N4.C3.S03: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 009
N6.C3.D1.R1.S03: RdPtrOffsetTxDq: 07
N0.C3.D1.R1.S13: RdPtrOffsetTxDq: 06
N4.C3.S03: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 009
N6.C3.D1.R1.S04: RdPtrOffsetTxDq: 07
N0.C3.D1.R1.S14: RdPtrOffsetTxDq: 06
N4.C3.S04: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 008
N6.C3.D1.R1.S05: RdPtrOffsetTxDq: 07
N0.C3.D1.R1.S15: RdPtrOffsetTxDq: 06
N4.C3.S04: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 008
N6.C3.D1.R1.S06: RdPtrOffsetTxDq: 07
N0.C3.D1.R1.S16: RdPtrOffsetTxDq: 06
N4.C3.S05: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 008
N6.C3.D1.R1.S07: RdPtrOffsetTxDq: 07
N0.C3.D1.R1.S17: RdPtrOffsetTxDq: 06
N4.C3.S05: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 008
N6.C3.D1.R1.S08: RdPtrOffsetTxDq: 07
N0.C3.D1.R1.S00: RdPtrOffsetTxDq: 08
N4.C3.S06: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 009
N6.C3.D1.R1.S09: RdPtrOffsetTxDq: 08
N0.C3.D1.R1.S01: RdPtrOffsetTxDq: 08
N4.C3.S06: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 009
N6.C3.D1.R1.S10: RdPtrOffsetTxDq: 08
N0.C3.D1.R1.S02: RdPtrOffsetTxDq: 08
N4.C3.S07: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 009
N6.C3.D1.R1.S11: RdPtrOffsetTxDq: 08
N0.C3.D1.R1.S03: RdPtrOffsetTxDq: 07
N4.C3.S07: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 009
N6.C3.D1.R1.S12: RdPtrOffsetTxDq: 07
N0.C3.D1.R1.S04: RdPtrOffsetTxDq: 07
N4.C3.S08: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 008
N6.C3.D1.R1.S13: RdPtrOffsetTxDq: 07
N0.C3.D1.R1.S05: RdPtrOffsetTxDq: 07
N4.C3.S08: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 008
N6.C3.D1.R1.S14: RdPtrOffsetTxDq: 07
N0.C3.D1.R1.S06: RdPtrOffsetTxDq: 07
N4.C3.D0.R0.S00: TxDqs: plus1 = 1, minus1 = 0, PI = 61, DB = 1
N6.C3.D1.R1.S15: RdPtrOffsetTxDq: 07
N0.C3.D1.R1.S07: RdPtrOffsetTxDq: 07
N4.C3.D0.R0.S00: TxDq : plus1 = 1, minus1 = 0, PI = 27, DB = 0
N6.C3.D1.R1.S16: RdPtrOffsetTxDq: 07
N0.C3.D1.R1.S08: RdPtrOffsetTxDq: 07
N4.C3.D0.R0.S01: TxDqs: plus1 = 1, minus1 = 0, PI = 43, DB = 0
N6.C3.D1.R1.S17: RdPtrOffsetTxDq: 07
N0.C3.D1.R1.S09: RdPtrOffsetTxDq: 08
N4.C3.D0.R0.S01: TxDq : plus1 = 1, minus1 = 0, PI = 09, DB = 1
N6.C3.D1.R1.S00: Total Delay in PI ticks: TxDQ = 989
N0.C3.D1.R1.S10: RdPtrOffsetTxDq: 08
N4.C3.D0.R0.S02: TxDqs: plus1 = 1, minus1 = 0, PI = 33, DB = 0
N6.C3.D1.R1.S01: Total Delay in PI ticks: TxDQ = 971
N0.C3.D1.R1.S11: RdPtrOffsetTxDq: 08
N4.C3.D0.R0.S02: TxDq : plus1 = 1, minus1 = 0, PI = 63, DB = 1
N6.C3.D1.R1.S02: Total Delay in PI ticks: TxDQ = 959
N0.C3.D1.R1.S12: RdPtrOffsetTxDq: 07
N4.C3.D0.R0.S03: TxDqs: plus1 = 1, minus1 = 0, PI = 19, DB = 0
N6.C3.D1.R1.S03: Total Delay in PI ticks: TxDQ = 947
N0.C3.D1.R1.S13: RdPtrOffsetTxDq: 07
N4.C3.D0.R0.S03: TxDq : plus1 = 1, minus1 = 0, PI = 49, DB = 1
N6.C3.D1.R1.S04: Total Delay in PI ticks: TxDQ = 909
N0.C3.D1.R1.S14: RdPtrOffsetTxDq: 07
N4.C3.D0.R0.S04: TxDqs: plus1 = 1, minus1 = 0, PI = 45, DB = 0
N6.C3.D1.R1.S05: Total Delay in PI ticks: TxDQ = 924
N0.C3.D1.R1.S15: RdPtrOffsetTxDq: 07
N4.C3.D0.R0.S04: TxDq : plus1 = 1, minus1 = 0, PI = 11, DB = 1
N6.C3.D1.R1.S06: Total Delay in PI ticks: TxDQ = 939
N0.C3.D1.R1.S16: RdPtrOffsetTxDq: 07
N4.C3.D0.R0.S05: TxDqs: plus1 = 1, minus1 = 0, PI = 59, DB = 1
N6.C3.D1.R1.S07: Total Delay in PI ticks: TxDQ = 954
N0.C3.D1.R1.S17: RdPtrOffsetTxDq: 07
N4.C3.D0.R0.S05: TxDq : plus1 = 1, minus1 = 0, PI = 24, DB = 0
N6.C3.D1.R1.S08: Total Delay in PI ticks: TxDQ = 925
N0.C3.D1.R1.S00: Total Delay in PI ticks: TxDQ = 990
N4.C3.D0.R0.S06: TxDqs: plus1 = 1, minus1 = 0, PI = 09, DB = 1
N6.C3.D1.R1.S09: Total Delay in PI ticks: TxDQ = 985
N0.C3.D1.R1.S01: Total Delay in PI ticks: TxDQ = 974
N4.C3.D0.R0.S06: TxDq : plus1 = 1, minus1 = 0, PI = 39, DB = 0
N6.C3.D1.R1.S10: Total Delay in PI ticks: TxDQ = 971
N0.C3.D1.R1.S02: Total Delay in PI ticks: TxDQ = 962
N4.C3.D0.R0.S07: TxDqs: plus1 = 1, minus1 = 0, PI = 28, DB = 0
N6.C3.D1.R1.S11: Total Delay in PI ticks: TxDQ = 962
N0.C3.D1.R1.S03: Total Delay in PI ticks: TxDQ = 949
N4.C3.D0.R0.S07: TxDq : plus1 = 1, minus1 = 0, PI = 57, DB = 1
N6.C3.D1.R1.S12: Total Delay in PI ticks: TxDQ = 949
N0.C3.D1.R1.S04: Total Delay in PI ticks: TxDQ = 915
N4.C3.D0.R0.S08: TxDqs: plus1 = 1, minus1 = 0, PI = 63, DB = 1
N6.C3.D1.R1.S13: Total Delay in PI ticks: TxDQ = 909
N0.C3.D1.R1.S05: Total Delay in PI ticks: TxDQ = 927
N4.C3.D0.R0.S08: TxDq : plus1 = 1, minus1 = 0, PI = 30, DB = 0
N6.C3.D1.R1.S14: Total Delay in PI ticks: TxDQ = 926
N0.C3.D1.R1.S06: Total Delay in PI ticks: TxDQ = 937
N4.C3.D0.R0.S09: TxDqs: plus1 = 1, minus1 = 0, PI = 59, DB = 1
N6.C3.D1.R1.S15: Total Delay in PI ticks: TxDQ = 937
N0.C3.D1.R1.S07: Total Delay in PI ticks: TxDQ = 959
N4.C3.D0.R0.S09: TxDq : plus1 = 1, minus1 = 0, PI = 24, DB = 0
N6.C3.D1.R1.S16: Total Delay in PI ticks: TxDQ = 955
N0.C3.D1.R1.S08: Total Delay in PI ticks: TxDQ = 925
N4.C3.D0.R0.S10: TxDqs: plus1 = 1, minus1 = 0, PI = 43, DB = 0
N6.C3.D1.R1.S17: Total Delay in PI ticks: TxDQ = 924
N0.C3.D1.R1.S09: Total Delay in PI ticks: TxDQ = 988
N4.C3.D0.R0.S10: TxDq : plus1 = 1, minus1 = 0, PI = 10, DB = 1
N6.C3: Calculating Optimimum DQ/DQS Values
N0.C3.D1.R1.S10: Total Delay in PI ticks: TxDQ = 975
N4.C3.D0.R0.S11: TxDqs: plus1 = 1, minus1 = 0, PI = 32, DB = 0
N0.C3.D1.R1.S11: Total Delay in PI ticks: TxDQ = 963
N4.C3.D0.R0.S11: TxDq : plus1 = 1, minus1 = 0, PI = 63, DB = 1
START_DATA_TX_DQ
N0.C3.D1.R1.S12: Total Delay in PI ticks: TxDQ = 949
N4.C3.D0.R0.S12: TxDqs: plus1 = 1, minus1 = 0, PI = 20, DB = 0
N6.C3.S00: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 009, RdPtrOffsetTxDqs = 009
N0.C3.D1.R1.S13: Total Delay in PI ticks: TxDQ = 916
N4.C3.D0.R0.S12: TxDq : plus1 = 1, minus1 = 0, PI = 50, DB = 1
N6.C3.S00: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 009, RdPtrOffsetTxDqs = 009
N0.C3.D1.R1.S14: Total Delay in PI ticks: TxDQ = 927
N4.C3.D0.R0.S13: TxDqs: plus1 = 1, minus1 = 0, PI = 45, DB = 0
N6.C3.S01: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 009, RdPtrOffsetTxDqs = 009
N0.C3.D1.R1.S15: Total Delay in PI ticks: TxDQ = 940
N4.C3.D0.R0.S13: TxDq : plus1 = 1, minus1 = 0, PI = 12, DB = 1
N6.C3.S01: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 009, RdPtrOffsetTxDqs = 009
N0.C3.D1.R1.S16: Total Delay in PI ticks: TxDQ = 957
N4.C3.D0.R0.S14: TxDqs: plus1 = 1, minus1 = 0, PI = 59, DB = 1
N6.C3.S02: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 009
N0.C3.D1.R1.S17: Total Delay in PI ticks: TxDQ = 927
N4.C3.D0.R0.S14: TxDq : plus1 = 1, minus1 = 0, PI = 26, DB = 0
N6.C3.S02: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 009
N0.C3: Calculating Optimimum DQ/DQS Values
N4.C3.D0.R0.S15: TxDqs: plus1 = 1, minus1 = 0, PI = 11, DB = 1
N6.C3.S03: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 009
N4.C3.D0.R0.S15: TxDq : plus1 = 1, minus1 = 0, PI = 43, DB = 0
N6.C3.S03: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 009
START_DATA_TX_DQ
N4.C3.D0.R0.S16: TxDqs: plus1 = 1, minus1 = 0, PI = 28, DB = 0
N6.C3.S04: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 008
N0.C3.S00: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 009, RdPtrOffsetTxDqs = 009
N2.C0: Read Vref - Strobe:0 Worst Left Edge:-29, Worst Right Edge:31, Center:1
N4.C3.D0.R0.S16: TxDq : plus1 = 1, minus1 = 0, PI = 57, DB = 1
N6.C3.S04: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 008
N0.C3.S00: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 009, RdPtrOffsetTxDqs = 009
N2.C0: Read Vref - Strobe:1 Worst Left Edge:-29, Worst Right Edge:31, Center:1
N4.C3.D0.R0.S17: TxDqs: plus1 = 1, minus1 = 0, PI = 62, DB = 1
N6.C3.S05: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 008
N0.C3.S01: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 009, RdPtrOffsetTxDqs = 009
N2.C0: Read Vref - Strobe:2 Worst Left Edge:-31, Worst Right Edge:31, Center:0
N4.C3.D0.R0.S17: TxDq : plus1 = 1, minus1 = 0, PI = 29, DB = 0
N6.C3.S05: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 008
N0.C3.S01: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 009, RdPtrOffsetTxDqs = 009
N2.C0: Read Vref - Strobe:3 Worst Left Edge:-29, Worst Right Edge:31, Center:1
N4.C3.D0.R1.S00: TxDqs: plus1 = 1, minus1 = 0, PI = 61, DB = 1
N6.C3.S06: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 009
N0.C3.S02: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 009, RdPtrOffsetTxDqs = 009
N2.C0: Read Vref - Strobe:4 Worst Left Edge:-25, Worst Right Edge:31, Center:3
N4.C3.D0.R1.S00: TxDq : plus1 = 1, minus1 = 0, PI = 27, DB = 0
N6.C3.S06: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 009
N0.C3.S02: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 009, RdPtrOffsetTxDqs = 009
N2.C0: Read Vref - Strobe:5 Worst Left Edge:-31, Worst Right Edge:31, Center:0
N4.C3.D0.R1.S01: TxDqs: plus1 = 1, minus1 = 0, PI = 43, DB = 0
N6.C3.S07: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 009
N0.C3.S03: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 009
N2.C0: Read Vref - Strobe:6 Worst Left Edge:-30, Worst Right Edge:31, Center:0
N4.C3.D0.R1.S01: TxDq : plus1 = 1, minus1 = 0, PI = 09, DB = 1
N6.C3.S07: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 009
N0.C3.S03: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 009
N2.C0: Read Vref - Strobe:7 Worst Left Edge:-24, Worst Right Edge:31, Center:3
N4.C3.D0.R1.S02: TxDqs: plus1 = 1, minus1 = 0, PI = 33, DB = 0
N6.C3.S08: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 008
N0.C3.S04: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 008
N2.C0: Read Vref - Strobe:8 Worst Left Edge:-25, Worst Right Edge:31, Center:3
N4.C3.D0.R1.S02: TxDq : plus1 = 1, minus1 = 0, PI = 63, DB = 1
N6.C3.S08: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 008
N0.C3.S04: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 008
N2.C0: Read Vref - Strobe:9 Worst Left Edge:-30, Worst Right Edge:31, Center:0
N4.C3.D0.R1.S03: TxDqs: plus1 = 1, minus1 = 0, PI = 19, DB = 0
N6.C3.D0.R0.S00: TxDqs: plus1 = 1, minus1 = 0, PI = 54, DB = 1
N0.C3.S05: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 008
N2.C0: Read Vref - Strobe:10 Worst Left Edge:-31, Worst Right Edge:31, Center:0
N4.C3.D0.R1.S03: TxDq : plus1 = 1, minus1 = 0, PI = 49, DB = 1
N6.C3.D0.R0.S00: TxDq : plus1 = 1, minus1 = 0, PI = 23, DB = 0
N0.C3.S05: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 008
N2.C0: Read Vref - Strobe:11 Worst Left Edge:-27, Worst Right Edge:31, Center:2
N4.C3.D0.R1.S04: TxDqs: plus1 = 1, minus1 = 0, PI = 45, DB = 0
N6.C3.D0.R0.S01: TxDqs: plus1 = 1, minus1 = 0, PI = 39, DB = 0
N0.C3.S06: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 009
N2.C0: Read Vref - Strobe:12 Worst Left Edge:-31, Worst Right Edge:31, Center:0
N4.C3.D0.R1.S04: TxDq : plus1 = 1, minus1 = 0, PI = 11, DB = 1
N6.C3.D0.R0.S01: TxDq : plus1 = 1, minus1 = 0, PI = 06, DB = 1
N0.C3.S06: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 009
N2.C0: Read Vref - Strobe:13 Worst Left Edge:-30, Worst Right Edge:31, Center:0
N4.C3.D0.R1.S05: TxDqs: plus1 = 1, minus1 = 0, PI = 59, DB = 1
N6.C3.D0.R0.S02: TxDqs: plus1 = 1, minus1 = 0, PI = 30, DB = 0
N0.C3.S07: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 009
N2.C0: Read Vref - Strobe:14 Worst Left Edge:-22, Worst Right Edge:31, Center:4
N4.C3.D0.R1.S05: TxDq : plus1 = 1, minus1 = 0, PI = 24, DB = 0
N6.C3.D0.R0.S02: TxDq : plus1 = 1, minus1 = 0, PI = 62, DB = 1
N0.C3.S07: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 009
N2.C0: Read Vref - Strobe:15 Worst Left Edge:-29, Worst Right Edge:31, Center:1
N4.C3.D0.R1.S06: TxDqs: plus1 = 1, minus1 = 0, PI = 09, DB = 1
N6.C3.D0.R0.S03: TxDqs: plus1 = 1, minus1 = 0, PI = 14, DB = 1
N0.C3.S08: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 009
N2.C0: Read Vref - Strobe:16 Worst Left Edge:-28, Worst Right Edge:31, Center:1
N4.C3.D0.R1.S06: TxDq : plus1 = 1, minus1 = 0, PI = 39, DB = 0
N6.C3.D0.R0.S03: TxDq : plus1 = 1, minus1 = 0, PI = 44, DB = 0
N0.C3.S08: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 009
N2.C0: Read Vref - Strobe:17 Worst Left Edge:-29, Worst Right Edge:31, Center:1
N4.C3.D0.R1.S07: TxDqs: plus1 = 1, minus1 = 0, PI = 28, DB = 0
N6.C3.D0.R0.S04: TxDqs: plus1 = 1, minus1 = 0, PI = 41, DB = 0
N0.C3.D0.R0.S00: TxDqs: plus1 = 1, minus1 = 0, PI = 62, DB = 1
N2.C1: Read Vref - Strobe:0 Worst Left Edge:-30, Worst Right Edge:31, Center:0
N4.C3.D0.R1.S07: TxDq : plus1 = 1, minus1 = 0, PI = 57, DB = 1
N6.C3.D0.R0.S04: TxDq : plus1 = 1, minus1 = 0, PI = 07, DB = 1
N0.C3.D0.R0.S00: TxDq : plus1 = 1, minus1 = 0, PI = 27, DB = 0
N2.C1: Read Vref - Strobe:1 Worst Left Edge:-27, Worst Right Edge:31, Center:2
N4.C3.D0.R1.S08: TxDqs: plus1 = 1, minus1 = 0, PI = 63, DB = 1
N6.C3.D0.R0.S05: TxDqs: plus1 = 1, minus1 = 0, PI = 55, DB = 1
N0.C3.D0.R0.S01: TxDqs: plus1 = 1, minus1 = 0, PI = 45, DB = 0
N2.C1: Read Vref - Strobe:2 Worst Left Edge:-25, Worst Right Edge:31, Center:3
N4.C3.D0.R1.S08: TxDq : plus1 = 1, minus1 = 0, PI = 30, DB = 0
N6.C3.D0.R0.S05: TxDq : plus1 = 1, minus1 = 0, PI = 23, DB = 0
N0.C3.D0.R0.S01: TxDq : plus1 = 1, minus1 = 0, PI = 11, DB = 1
N2.C1: Read Vref - Strobe:3 Worst Left Edge:-31, Worst Right Edge:31, Center:0
N4.C3.D0.R1.S09: TxDqs: plus1 = 1, minus1 = 0, PI = 59, DB = 1
N6.C3.D0.R0.S06: TxDqs: plus1 = 1, minus1 = 0, PI = 06, DB = 1
N0.C3.D0.R0.S02: TxDqs: plus1 = 1, minus1 = 0, PI = 34, DB = 0
N2.C1: Read Vref - Strobe:4 Worst Left Edge:-27, Worst Right Edge:31, Center:2
N4.C3.D0.R1.S09: TxDq : plus1 = 1, minus1 = 0, PI = 24, DB = 0
N6.C3.D0.R0.S06: TxDq : plus1 = 1, minus1 = 0, PI = 39, DB = 0
N0.C3.D0.R0.S02: TxDq : plus1 = 1, minus1 = 0, PI = 02, DB = 1
N2.C1: Read Vref - Strobe:5 Worst Left Edge:-27, Worst Right Edge:31, Center:2
N4.C3.D0.R1.S10: TxDqs: plus1 = 1, minus1 = 0, PI = 43, DB = 0
N6.C3.D0.R0.S07: TxDqs: plus1 = 1, minus1 = 0, PI = 22, DB = 0
N0.C3.D0.R0.S03: TxDqs: plus1 = 1, minus1 = 0, PI = 18, DB = 0
N2.C1: Read Vref - Strobe:6 Worst Left Edge:-24, Worst Right Edge:31, Center:3
N4.C3.D0.R1.S10: TxDq : plus1 = 1, minus1 = 0, PI = 10, DB = 1
N6.C3.D0.R0.S07: TxDq : plus1 = 1, minus1 = 0, PI = 53, DB = 1
N0.C3.D0.R0.S03: TxDq : plus1 = 1, minus1 = 0, PI = 47, DB = 0
N2.C1: Read Vref - Strobe:7 Worst Left Edge:-27, Worst Right Edge:31, Center:2
N4.C3.D0.R1.S11: TxDqs: plus1 = 1, minus1 = 0, PI = 32, DB = 0
N6.C3.D0.R0.S08: TxDqs: plus1 = 1, minus1 = 0, PI = 59, DB = 1
N0.C3.D0.R0.S04: TxDqs: plus1 = 1, minus1 = 0, PI = 49, DB = 1
N2.C1: Read Vref - Strobe:8 Worst Left Edge:-28, Worst Right Edge:31, Center:1
N4.C3.D0.R1.S11: TxDq : plus1 = 1, minus1 = 0, PI = 63, DB = 1
N6.C3.D0.R0.S08: TxDq : plus1 = 1, minus1 = 0, PI = 26, DB = 0
N0.C3.D0.R0.S04: TxDq : plus1 = 1, minus1 = 0, PI = 15, DB = 1
N2.C1: Read Vref - Strobe:9 Worst Left Edge:-26, Worst Right Edge:31, Center:2
N4.C3.D0.R1.S12: TxDqs: plus1 = 1, minus1 = 0, PI = 20, DB = 0
N6.C3.D0.R0.S09: TxDqs: plus1 = 1, minus1 = 0, PI = 54, DB = 1
N0.C3.D0.R0.S05: TxDqs: plus1 = 1, minus1 = 0, PI = 61, DB = 1
N2.C1: Read Vref - Strobe:10 Worst Left Edge:-26, Worst Right Edge:31, Center:2
N4.C3.D0.R1.S12: TxDq : plus1 = 1, minus1 = 0, PI = 50, DB = 1
N6.C3.D0.R0.S09: TxDq : plus1 = 1, minus1 = 0, PI = 20, DB = 0
N0.C3.D0.R0.S05: TxDq : plus1 = 1, minus1 = 0, PI = 28, DB = 0
N2.C1: Read Vref - Strobe:11 Worst Left Edge:-29, Worst Right Edge:31, Center:1
N4.C3.D0.R1.S13: TxDqs: plus1 = 1, minus1 = 0, PI = 45, DB = 0
N6.C3.D0.R0.S10: TxDqs: plus1 = 1, minus1 = 0, PI = 38, DB = 0
N0.C3.D0.R0.S06: TxDqs: plus1 = 1, minus1 = 0, PI = 12, DB = 1
N2.C1: Read Vref - Strobe:12 Worst Left Edge:-23, Worst Right Edge:31, Center:4
N4.C3.D0.R1.S13: TxDq : plus1 = 1, minus1 = 0, PI = 12, DB = 1
N6.C3.D0.R0.S10: TxDq : plus1 = 1, minus1 = 0, PI = 07, DB = 1
N0.C3.D0.R0.S06: TxDq : plus1 = 1, minus1 = 0, PI = 42, DB = 0
N2.C1: Read Vref - Strobe:13 Worst Left Edge:-23, Worst Right Edge:31, Center:4
N4.C3.D0.R1.S14: TxDqs: plus1 = 1, minus1 = 0, PI = 59, DB = 1
N6.C3.D0.R0.S11: TxDqs: plus1 = 1, minus1 = 0, PI = 29, DB = 0
N0.C3.D0.R0.S07: TxDqs: plus1 = 1, minus1 = 0, PI = 30, DB = 0
N2.C1: Read Vref - Strobe:14 Worst Left Edge:-22, Worst Right Edge:31, Center:4
N4.C3.D0.R1.S14: TxDq : plus1 = 1, minus1 = 0, PI = 26, DB = 0
N6.C3.D0.R0.S11: TxDq : plus1 = 1, minus1 = 0, PI = 61, DB = 1
N0.C3.D0.R0.S07: TxDq : plus1 = 1, minus1 = 0, PI = 60, DB = 1
N2.C1: Read Vref - Strobe:15 Worst Left Edge:-31, Worst Right Edge:31, Center:0
N4.C3.D0.R1.S15: TxDqs: plus1 = 1, minus1 = 0, PI = 11, DB = 1
N6.C3.D0.R0.S12: TxDqs: plus1 = 1, minus1 = 0, PI = 13, DB = 1
N0.C3.D0.R0.S08: TxDqs: plus1 = 1, minus1 = 0, PI = 00, DB = 1
N2.C1: Read Vref - Strobe:16 Worst Left Edge:-26, Worst Right Edge:31, Center:2
N4.C3.D0.R1.S15: TxDq : plus1 = 1, minus1 = 0, PI = 43, DB = 0
N6.C3.D0.R0.S12: TxDq : plus1 = 1, minus1 = 0, PI = 45, DB = 0
N0.C3.D0.R0.S08: TxDq : plus1 = 1, minus1 = 0, PI = 31, DB = 0
N2.C1: Read Vref - Strobe:17 Worst Left Edge:-24, Worst Right Edge:31, Center:3
N4.C3.D0.R1.S16: TxDqs: plus1 = 1, minus1 = 0, PI = 28, DB = 0
N6.C3.D0.R0.S13: TxDqs: plus1 = 1, minus1 = 0, PI = 41, DB = 0
N0.C3.D0.R0.S09: TxDqs: plus1 = 1, minus1 = 0, PI = 61, DB = 1
N2.C2: Read Vref - Strobe:0 Worst Left Edge:-29, Worst Right Edge:31, Center:1
N4.C3.D0.R1.S16: TxDq : plus1 = 1, minus1 = 0, PI = 57, DB = 1
N6.C3.D0.R0.S13: TxDq : plus1 = 1, minus1 = 0, PI = 08, DB = 1
N0.C3.D0.R0.S09: TxDq : plus1 = 1, minus1 = 0, PI = 25, DB = 0
N2.C2: Read Vref - Strobe:1 Worst Left Edge:-24, Worst Right Edge:31, Center:3
N4.C3.D0.R1.S17: TxDqs: plus1 = 1, minus1 = 0, PI = 62, DB = 1
N6.C3.D0.R0.S14: TxDqs: plus1 = 1, minus1 = 0, PI = 55, DB = 1
N0.C3.D0.R0.S10: TxDqs: plus1 = 1, minus1 = 0, PI = 45, DB = 0
N2.C2: Read Vref - Strobe:2 Worst Left Edge:-28, Worst Right Edge:31, Center:1
N4.C3.D0.R1.S17: TxDq : plus1 = 1, minus1 = 0, PI = 29, DB = 0
N6.C3.D0.R0.S14: TxDq : plus1 = 1, minus1 = 0, PI = 24, DB = 0
N0.C3.D0.R0.S10: TxDq : plus1 = 1, minus1 = 0, PI = 11, DB = 1
N2.C2: Read Vref - Strobe:3 Worst Left Edge:-27, Worst Right Edge:31, Center:2
N4.C3.D1.R0.S00: TxDqs: plus1 = 0, minus1 = 1, PI = 03, DB = 1
N6.C3.D0.R0.S15: TxDqs: plus1 = 1, minus1 = 0, PI = 05, DB = 1
N0.C3.D0.R0.S11: TxDqs: plus1 = 1, minus1 = 0, PI = 35, DB = 0
N2.C2: Read Vref - Strobe:4 Worst Left Edge:-24, Worst Right Edge:31, Center:3
N4.C3.D1.R0.S00: TxDq : plus1 = 1, minus1 = 0, PI = 32, DB = 0
N6.C3.D0.R0.S15: TxDq : plus1 = 1, minus1 = 0, PI = 38, DB = 0
N0.C3.D0.R0.S11: TxDq : plus1 = 1, minus1 = 0, PI = 02, DB = 1
N2.C2: Read Vref - Strobe:5 Worst Left Edge:-23, Worst Right Edge:31, Center:4
N4.C3.D1.R0.S01: TxDqs: plus1 = 1, minus1 = 0, PI = 52, DB = 1
N6.C3.D0.R0.S16: TxDqs: plus1 = 1, minus1 = 0, PI = 23, DB = 0
N0.C3.D0.R0.S12: TxDqs: plus1 = 1, minus1 = 0, PI = 22, DB = 0
N2.C2: Read Vref - Strobe:6 Worst Left Edge:-25, Worst Right Edge:31, Center:3
N4.C3.D1.R0.S01: TxDq : plus1 = 1, minus1 = 0, PI = 17, DB = 0
N6.C3.D0.R0.S16: TxDq : plus1 = 1, minus1 = 0, PI = 56, DB = 1
N0.C3.D0.R0.S12: TxDq : plus1 = 1, minus1 = 0, PI = 51, DB = 1
N2.C2: Read Vref - Strobe:7 Worst Left Edge:-22, Worst Right Edge:31, Center:4
N4.C3.D1.R0.S02: TxDqs: plus1 = 1, minus1 = 0, PI = 41, DB = 0
N6.C3.D0.R0.S17: TxDqs: plus1 = 1, minus1 = 0, PI = 57, DB = 1
N0.C3.D0.R0.S13: TxDqs: plus1 = 1, minus1 = 0, PI = 49, DB = 1
N2.C2: Read Vref - Strobe:8 Worst Left Edge:-31, Worst Right Edge:31, Center:0
N4.C3.D1.R0.S02: TxDq : plus1 = 0, minus1 = 1, PI = 06, DB = 1
N6.C3.D0.R0.S17: TxDq : plus1 = 1, minus1 = 0, PI = 25, DB = 0
N0.C3.D0.R0.S13: TxDq : plus1 = 1, minus1 = 0, PI = 15, DB = 1
N2.C2: Read Vref - Strobe:9 Worst Left Edge:-24, Worst Right Edge:31, Center:3
N4.C3.D1.R0.S03: TxDqs: plus1 = 1, minus1 = 0, PI = 26, DB = 0
N6.C3.D0.R1.S00: TxDqs: plus1 = 1, minus1 = 0, PI = 54, DB = 1
N0.C3.D0.R0.S14: TxDqs: plus1 = 1, minus1 = 0, PI = 61, DB = 1
N2.C2: Read Vref - Strobe:10 Worst Left Edge:-22, Worst Right Edge:31, Center:4
N4.C3.D1.R0.S03: TxDq : plus1 = 1, minus1 = 0, PI = 54, DB = 1
N6.C3.D0.R1.S00: TxDq : plus1 = 1, minus1 = 0, PI = 23, DB = 0
N0.C3.D0.R0.S14: TxDq : plus1 = 1, minus1 = 0, PI = 28, DB = 0
N2.C2: Read Vref - Strobe:11 Worst Left Edge:-29, Worst Right Edge:31, Center:1
N4.C3.D1.R0.S04: TxDqs: plus1 = 1, minus1 = 0, PI = 54, DB = 1
N6.C3.D0.R1.S01: TxDqs: plus1 = 1, minus1 = 0, PI = 39, DB = 0
N0.C3.D0.R0.S15: TxDqs: plus1 = 1, minus1 = 0, PI = 13, DB = 1
N2.C2: Read Vref - Strobe:12 Worst Left Edge:-30, Worst Right Edge:31, Center:0
N4.C3.D1.R0.S04: TxDq : plus1 = 1, minus1 = 0, PI = 17, DB = 0
N6.C3.D0.R1.S01: TxDq : plus1 = 1, minus1 = 0, PI = 06, DB = 1
N0.C3.D0.R0.S15: TxDq : plus1 = 1, minus1 = 0, PI = 43, DB = 0
N2.C2: Read Vref - Strobe:13 Worst Left Edge:-27, Worst Right Edge:31, Center:2
N4.C3.D1.R0.S05: TxDqs: plus1 = 0, minus1 = 1, PI = 02, DB = 1
N6.C3.D0.R1.S02: TxDqs: plus1 = 1, minus1 = 0, PI = 30, DB = 0
N0.C3.D0.R0.S16: TxDqs: plus1 = 1, minus1 = 0, PI = 28, DB = 0
N2.C2: Read Vref - Strobe:14 Worst Left Edge:-31, Worst Right Edge:31, Center:0
N4.C3.D1.R0.S05: TxDq : plus1 = 1, minus1 = 0, PI = 32, DB = 0
N6.C3.D0.R1.S02: TxDq : plus1 = 1, minus1 = 0, PI = 62, DB = 1
N0.C3.D0.R0.S16: TxDq : plus1 = 1, minus1 = 0, PI = 59, DB = 1
N2.C2: Read Vref - Strobe:15 Worst Left Edge:-21, Worst Right Edge:31, Center:5
N4.C3.D1.R0.S06: TxDqs: plus1 = 1, minus1 = 0, PI = 18, DB = 0
N6.C3.D0.R1.S03: TxDqs: plus1 = 1, minus1 = 0, PI = 14, DB = 1
N0.C3.D0.R0.S17: TxDqs: plus1 = 1, minus1 = 0, PI = 01, DB = 1
N2.C2: Read Vref - Strobe:16 Worst Left Edge:-25, Worst Right Edge:31, Center:3
N4.C3.D1.R0.S06: TxDq : plus1 = 1, minus1 = 0, PI = 46, DB = 0
N6.C3.D0.R1.S03: TxDq : plus1 = 1, minus1 = 0, PI = 44, DB = 0
N0.C3.D0.R0.S17: TxDq : plus1 = 1, minus1 = 0, PI = 33, DB = 0
N2.C2: Read Vref - Strobe:17 Worst Left Edge:-30, Worst Right Edge:31, Center:0
N4.C3.D1.R0.S07: TxDqs: plus1 = 1, minus1 = 0, PI = 35, DB = 0
N6.C3.D0.R1.S04: TxDqs: plus1 = 1, minus1 = 0, PI = 41, DB = 0
N0.C3.D0.R1.S00: TxDqs: plus1 = 1, minus1 = 0, PI = 62, DB = 1
N2.C3: Read Vref - Strobe:0 Worst Left Edge:-25, Worst Right Edge:31, Center:3
N4.C3.D1.R0.S07: TxDq : plus1 = 0, minus1 = 1, PI = 00, DB = 1
N6.C3.D0.R1.S04: TxDq : plus1 = 1, minus1 = 0, PI = 07, DB = 1
N0.C3.D0.R1.S00: TxDq : plus1 = 1, minus1 = 0, PI = 27, DB = 0
N2.C3: Read Vref - Strobe:1 Worst Left Edge:-28, Worst Right Edge:31, Center:1
N4.C3.D1.R0.S08: TxDqs: plus1 = 0, minus1 = 1, PI = 05, DB = 1
N6.C3.D0.R1.S05: TxDqs: plus1 = 1, minus1 = 0, PI = 55, DB = 1
N0.C3.D0.R1.S01: TxDqs: plus1 = 1, minus1 = 0, PI = 45, DB = 0
N2.C3: Read Vref - Strobe:2 Worst Left Edge:-29, Worst Right Edge:31, Center:1
N4.C3.D1.R0.S08: TxDq : plus1 = 1, minus1 = 0, PI = 33, DB = 0
N6.C3.D0.R1.S05: TxDq : plus1 = 1, minus1 = 0, PI = 23, DB = 0
N0.C3.D0.R1.S01: TxDq : plus1 = 1, minus1 = 0, PI = 11, DB = 1
N2.C3: Read Vref - Strobe:3 Worst Left Edge:-31, Worst Right Edge:31, Center:0
N4.C3.D1.R0.S09: TxDqs: plus1 = 0, minus1 = 1, PI = 02, DB = 1
N6.C3.D0.R1.S06: TxDqs: plus1 = 1, minus1 = 0, PI = 06, DB = 1
N0.C3.D0.R1.S02: TxDqs: plus1 = 1, minus1 = 0, PI = 34, DB = 0
N2.C3: Read Vref - Strobe:4 Worst Left Edge:-24, Worst Right Edge:31, Center:3
N4.C3.D1.R0.S09: TxDq : plus1 = 1, minus1 = 0, PI = 28, DB = 0
N6.C3.D0.R1.S06: TxDq : plus1 = 1, minus1 = 0, PI = 39, DB = 0
N0.C3.D0.R1.S02: TxDq : plus1 = 1, minus1 = 0, PI = 02, DB = 1
N2.C3: Read Vref - Strobe:5 Worst Left Edge:-31, Worst Right Edge:31, Center:0
N4.C3.D1.R0.S10: TxDqs: plus1 = 1, minus1 = 0, PI = 52, DB = 1
N6.C3.D0.R1.S07: TxDqs: plus1 = 1, minus1 = 0, PI = 22, DB = 0
N0.C3.D0.R1.S03: TxDqs: plus1 = 1, minus1 = 0, PI = 18, DB = 0
N2.C3: Read Vref - Strobe:6 Worst Left Edge:-26, Worst Right Edge:31, Center:2
N4.C3.D1.R0.S10: TxDq : plus1 = 1, minus1 = 0, PI = 17, DB = 0
N6.C3.D0.R1.S07: TxDq : plus1 = 1, minus1 = 0, PI = 53, DB = 1
N0.C3.D0.R1.S03: TxDq : plus1 = 1, minus1 = 0, PI = 47, DB = 0
N2.C3: Read Vref - Strobe:7 Worst Left Edge:-26, Worst Right Edge:31, Center:2
N4.C3.D1.R0.S11: TxDqs: plus1 = 1, minus1 = 0, PI = 41, DB = 0
N6.C3.D0.R1.S08: TxDqs: plus1 = 1, minus1 = 0, PI = 59, DB = 1
N0.C3.D0.R1.S04: TxDqs: plus1 = 1, minus1 = 0, PI = 49, DB = 1
N2.C3: Read Vref - Strobe:8 Worst Left Edge:-31, Worst Right Edge:31, Center:0
N4.C3.D1.R0.S11: TxDq : plus1 = 0, minus1 = 1, PI = 04, DB = 1
N6.C3.D0.R1.S08: TxDq : plus1 = 1, minus1 = 0, PI = 26, DB = 0
N0.C3.D0.R1.S04: TxDq : plus1 = 1, minus1 = 0, PI = 15, DB = 1
N2.C3: Read Vref - Strobe:9 Worst Left Edge:-28, Worst Right Edge:31, Center:1
N4.C3.D1.R0.S12: TxDqs: plus1 = 1, minus1 = 0, PI = 29, DB = 0
N6.C3.D0.R1.S09: TxDqs: plus1 = 1, minus1 = 0, PI = 54, DB = 1
N0.C3.D0.R1.S05: TxDqs: plus1 = 1, minus1 = 0, PI = 61, DB = 1
N2.C3: Read Vref - Strobe:10 Worst Left Edge:-29, Worst Right Edge:31, Center:1
N4.C3.D1.R0.S12: TxDq : plus1 = 1, minus1 = 0, PI = 57, DB = 1
N6.C3.D0.R1.S09: TxDq : plus1 = 1, minus1 = 0, PI = 20, DB = 0
N0.C3.D0.R1.S05: TxDq : plus1 = 1, minus1 = 0, PI = 28, DB = 0
N2.C3: Read Vref - Strobe:11 Worst Left Edge:-21, Worst Right Edge:31, Center:5
N4.C3.D1.R0.S13: TxDqs: plus1 = 1, minus1 = 0, PI = 55, DB = 1
N6.C3.D0.R1.S10: TxDqs: plus1 = 1, minus1 = 0, PI = 38, DB = 0
N0.C3.D0.R1.S06: TxDqs: plus1 = 1, minus1 = 0, PI = 12, DB = 1
N2.C3: Read Vref - Strobe:12 Worst Left Edge:-28, Worst Right Edge:31, Center:1
N4.C3.D1.R0.S13: TxDq : plus1 = 1, minus1 = 0, PI = 18, DB = 0
N6.C3.D0.R1.S10: TxDq : plus1 = 1, minus1 = 0, PI = 07, DB = 1
N0.C3.D0.R1.S06: TxDq : plus1 = 1, minus1 = 0, PI = 42, DB = 0
N2.C3: Read Vref - Strobe:13 Worst Left Edge:-29, Worst Right Edge:31, Center:1
N4.C3.D1.R0.S14: TxDqs: plus1 = 0, minus1 = 1, PI = 05, DB = 1
N6.C3.D0.R1.S11: TxDqs: plus1 = 1, minus1 = 0, PI = 29, DB = 0
N0.C3.D0.R1.S07: TxDqs: plus1 = 1, minus1 = 0, PI = 30, DB = 0
N2.C3: Read Vref - Strobe:14 Worst Left Edge:-30, Worst Right Edge:31, Center:0
N4.C3.D1.R0.S14: TxDq : plus1 = 1, minus1 = 0, PI = 34, DB = 0
N6.C3.D0.R1.S11: TxDq : plus1 = 1, minus1 = 0, PI = 61, DB = 1
N0.C3.D0.R1.S07: TxDq : plus1 = 1, minus1 = 0, PI = 60, DB = 1
N2.C3: Read Vref - Strobe:15 Worst Left Edge:-28, Worst Right Edge:31, Center:1
N4.C3.D1.R0.S15: TxDqs: plus1 = 1, minus1 = 0, PI = 18, DB = 0
N6.C3.D0.R1.S12: TxDqs: plus1 = 1, minus1 = 0, PI = 13, DB = 1
N0.C3.D0.R1.S08: TxDqs: plus1 = 1, minus1 = 0, PI = 00, DB = 1
N2.C3: Read Vref - Strobe:16 Worst Left Edge:-27, Worst Right Edge:31, Center:2
N4.C3.D1.R0.S15: TxDq : plus1 = 1, minus1 = 0, PI = 48, DB = 0
N6.C3.D0.R1.S12: TxDq : plus1 = 1, minus1 = 0, PI = 45, DB = 0
N0.C3.D0.R1.S08: TxDq : plus1 = 1, minus1 = 0, PI = 31, DB = 0
N2.C3: Read Vref - Strobe:17 Worst Left Edge:-26, Worst Right Edge:31, Center:2
N4.C3.D1.R0.S16: TxDqs: plus1 = 1, minus1 = 0, PI = 36, DB = 0
N6.C3.D0.R1.S13: TxDqs: plus1 = 1, minus1 = 0, PI = 41, DB = 0
N0.C3.D0.R1.S09: TxDqs: plus1 = 1, minus1 = 0, PI = 61, DB = 1
N2: RunTrainStep: Final status = 0
N4.C3.D1.R0.S16: TxDq : plus1 = 0, minus1 = 1, PI = 01, DB = 1
N6.C3.D0.R1.S13: TxDq : plus1 = 1, minus1 = 0, PI = 08, DB = 1
N0.C3.D0.R1.S09: TxDq : plus1 = 1, minus1 = 0, PI = 25, DB = 0

END - Rd Voltage Training              Time         5097 ms
N4.C3.D1.R0.S17: TxDqs: plus1 = 0, minus1 = 1, PI = 05, DB = 1
N6.C3.D0.R1.S14: TxDqs: plus1 = 1, minus1 = 0, PI = 55, DB = 1
N0.C3.D0.R1.S10: TxDqs: plus1 = 1, minus1 = 0, PI = 45, DB = 0
N2.C0.D0.R0.S00: StoreJckWorstRank: worst rank = 0, greatestDelay = 1327
N4.C3.D1.R0.S17: TxDq : plus1 = 1, minus1 = 0, PI = 33, DB = 0
N6.C3.D0.R1.S14: TxDq : plus1 = 1, minus1 = 0, PI = 24, DB = 0
N0.C3.D0.R1.S10: TxDq : plus1 = 1, minus1 = 0, PI = 11, DB = 1
N2.C0.D0.R0.S07: StoreJckWorstRank: worst rank = 0, greatestDelay = 1328
N4.C3.D1.R1.S00: TxDqs: plus1 = 0, minus1 = 1, PI = 03, DB = 1
N6.C3.D0.R1.S15: TxDqs: plus1 = 1, minus1 = 0, PI = 05, DB = 1
N0.C3.D0.R1.S11: TxDqs: plus1 = 1, minus1 = 0, PI = 35, DB = 0
N2.C1.D0.R0.S00: StoreJckWorstRank: worst rank = 0, greatestDelay = 1373
N4.C3.D1.R1.S00: TxDq : plus1 = 1, minus1 = 0, PI = 32, DB = 0
N6.C3.D0.R1.S15: TxDq : plus1 = 1, minus1 = 0, PI = 38, DB = 0
N0.C3.D0.R1.S11: TxDq : plus1 = 1, minus1 = 0, PI = 02, DB = 1
N2.C1.D0.R0.S09: StoreJckWorstRank: worst rank = 0, greatestDelay = 1374
N4.C3.D1.R1.S01: TxDqs: plus1 = 1, minus1 = 0, PI = 52, DB = 1
N6.C3.D0.R1.S16: TxDqs: plus1 = 1, minus1 = 0, PI = 23, DB = 0
N0.C3.D0.R1.S12: TxDqs: plus1 = 1, minus1 = 0, PI = 22, DB = 0
N2.C1.D0.R1.S00: StoreJckWorstRank: worst rank = 1, greatestDelay = 1375
N4.C3.D1.R1.S01: TxDq : plus1 = 1, minus1 = 0, PI = 17, DB = 0
N6.C3.D0.R1.S16: TxDq : plus1 = 1, minus1 = 0, PI = 56, DB = 1
N0.C3.D0.R1.S12: TxDq : plus1 = 1, minus1 = 0, PI = 51, DB = 1
N2.C0: StoreJckWorstRank: final value: worst rank = 1
N4.C3.D1.R1.S02: TxDqs: plus1 = 1, minus1 = 0, PI = 41, DB = 0
N6.C3.D0.R1.S17: TxDqs: plus1 = 1, minus1 = 0, PI = 57, DB = 1
N0.C3.D0.R1.S13: TxDqs: plus1 = 1, minus1 = 0, PI = 49, DB = 1
N2.C2.D0.R0.S00: StoreJckWorstRank: worst rank = 0, greatestDelay = 1329
N4.C3.D1.R1.S02: TxDq : plus1 = 0, minus1 = 1, PI = 06, DB = 1
N6.C3.D0.R1.S17: TxDq : plus1 = 1, minus1 = 0, PI = 25, DB = 0
N0.C3.D0.R1.S13: TxDq : plus1 = 1, minus1 = 0, PI = 15, DB = 1
N2.C2.D0.R0.S09: StoreJckWorstRank: worst rank = 0, greatestDelay = 1331
N4.C3.D1.R1.S03: TxDqs: plus1 = 1, minus1 = 0, PI = 26, DB = 0
N6.C3.D1.R0.S00: TxDqs: plus1 = 1, minus1 = 0, PI = 63, DB = 1
N0.C3.D0.R1.S14: TxDqs: plus1 = 1, minus1 = 0, PI = 61, DB = 1
N2.C3.D0.R0.S00: StoreJckWorstRank: worst rank = 0, greatestDelay = 1375
N4.C3.D1.R1.S03: TxDq : plus1 = 1, minus1 = 0, PI = 54, DB = 1
N6.C3.D1.R0.S00: TxDq : plus1 = 1, minus1 = 0, PI = 31, DB = 0
N0.C3.D0.R1.S14: TxDq : plus1 = 1, minus1 = 0, PI = 28, DB = 0
N2.C1: StoreJckWorstRank: final value: worst rank = 0
N4.C3.D1.R1.S04: TxDqs: plus1 = 1, minus1 = 0, PI = 54, DB = 1
N6.C3.D1.R0.S01: TxDqs: plus1 = 1, minus1 = 0, PI = 45, DB = 0
N0.C3.D0.R1.S15: TxDqs: plus1 = 1, minus1 = 0, PI = 13, DB = 1
GetAllRankMargins
N4.C3.D1.R1.S04: TxDq : plus1 = 1, minus1 = 0, PI = 17, DB = 0
N6.C3.D1.R0.S01: TxDq : plus1 = 1, minus1 = 0, PI = 13, DB = 1
N0.C3.D0.R1.S15: TxDq : plus1 = 1, minus1 = 0, PI = 43, DB = 0
N2: Checking margins for all ranks...
N4.C3.D1.R1.S05: TxDqs: plus1 = 0, minus1 = 1, PI = 02, DB = 1
N6.C3.D1.R0.S02: TxDqs: plus1 = 1, minus1 = 0, PI = 34, DB = 0
N0.C3.D0.R1.S16: TxDqs: plus1 = 1, minus1 = 0, PI = 28, DB = 0
N2: 
Get Rx Dqs margins...
N4.C3.D1.R1.S05: TxDq : plus1 = 1, minus1 = 0, PI = 32, DB = 0
N6.C3.D1.R0.S02: TxDq : plus1 = 0, minus1 = 1, PI = 01, DB = 1
N0.C3.D0.R1.S16: TxDq : plus1 = 1, minus1 = 0, PI = 59, DB = 1
N2: GetMargins: Level = 1, group = 11, mode = 0, scope = 3
N4.C3.D1.R1.S06: TxDqs: plus1 = 1, minus1 = 0, PI = 18, DB = 0
N6.C3.D1.R0.S03: TxDqs: plus1 = 1, minus1 = 0, PI = 21, DB = 0
N0.C3.D0.R1.S17: TxDqs: plus1 = 1, minus1 = 0, PI = 01, DB = 1
N4.C3.D1.R1.S06: TxDq : plus1 = 1, minus1 = 0, PI = 46, DB = 0
N6.C3.D1.R0.S03: TxDq : plus1 = 1, minus1 = 0, PI = 52, DB = 1
N0.C3.D0.R1.S17: TxDq : plus1 = 1, minus1 = 0, PI = 33, DB = 0
N4.C3.D1.R1.S07: TxDqs: plus1 = 1, minus1 = 0, PI = 35, DB = 0
N6.C3.D1.R0.S04: TxDqs: plus1 = 1, minus1 = 0, PI = 49, DB = 1
N0.C3.D1.R0.S00: TxDqs: plus1 = 0, minus1 = 1, PI = 03, DB = 1
N4.C3.D1.R1.S07: TxDq : plus1 = 0, minus1 = 1, PI = 00, DB = 1
N6.C3.D1.R0.S04: TxDq : plus1 = 1, minus1 = 0, PI = 15, DB = 1
N0.C3.D1.R0.S00: TxDq : plus1 = 1, minus1 = 0, PI = 31, DB = 0
N4.C3.D1.R1.S08: TxDqs: plus1 = 0, minus1 = 1, PI = 05, DB = 1
N6.C3.D1.R0.S05: TxDqs: plus1 = 1, minus1 = 0, PI = 62, DB = 1
N0.C3.D1.R0.S01: TxDqs: plus1 = 1, minus1 = 0, PI = 49, DB = 1
N4.C3.D1.R1.S08: TxDq : plus1 = 1, minus1 = 0, PI = 33, DB = 0
N6.C3.D1.R0.S05: TxDq : plus1 = 1, minus1 = 0, PI = 29, DB = 0
N0.C3.D1.R0.S01: TxDq : plus1 = 1, minus1 = 0, PI = 14, DB = 1
N4.C3.D1.R1.S09: TxDqs: plus1 = 0, minus1 = 1, PI = 02, DB = 1
N6.C3.D1.R0.S06: TxDqs: plus1 = 1, minus1 = 0, PI = 13, DB = 1
N0.C3.D1.R0.S02: TxDqs: plus1 = 1, minus1 = 0, PI = 40, DB = 0
N4.C3.D1.R1.S09: TxDq : plus1 = 1, minus1 = 0, PI = 28, DB = 0
N6.C3.D1.R0.S06: TxDq : plus1 = 1, minus1 = 0, PI = 44, DB = 0
N0.C3.D1.R0.S02: TxDq : plus1 = 1, minus1 = 0, PI = 05, DB = 1
N4.C3.D1.R1.S10: TxDqs: plus1 = 1, minus1 = 0, PI = 52, DB = 1
N6.C3.D1.R0.S07: TxDqs: plus1 = 1, minus1 = 0, PI = 30, DB = 0
N0.C3.D1.R0.S03: TxDqs: plus1 = 1, minus1 = 0, PI = 24, DB = 0
N4.C3.D1.R1.S10: TxDq : plus1 = 1, minus1 = 0, PI = 17, DB = 0
N6.C3.D1.R0.S07: TxDq : plus1 = 1, minus1 = 0, PI = 60, DB = 1
N0.C3.D1.R0.S03: TxDq : plus1 = 1, minus1 = 0, PI = 53, DB = 1
N4.C3.D1.R1.S11: TxDqs: plus1 = 1, minus1 = 0, PI = 41, DB = 0
N6.C3.D1.R0.S08: TxDqs: plus1 = 0, minus1 = 1, PI = 00, DB = 1
N0.C3.D1.R0.S04: TxDqs: plus1 = 1, minus1 = 0, PI = 53, DB = 1
N4.C3.D1.R1.S11: TxDq : plus1 = 0, minus1 = 1, PI = 04, DB = 1
N6.C3.D1.R0.S08: TxDq : plus1 = 1, minus1 = 0, PI = 31, DB = 0
N0.C3.D1.R0.S04: TxDq : plus1 = 1, minus1 = 0, PI = 19, DB = 0
N4.C3.D1.R1.S12: TxDqs: plus1 = 1, minus1 = 0, PI = 29, DB = 0
N6.C3.D1.R0.S09: TxDqs: plus1 = 1, minus1 = 0, PI = 62, DB = 1
N0.C3.D1.R0.S05: TxDqs: plus1 = 0, minus1 = 1, PI = 02, DB = 1
N4.C3.D1.R1.S12: TxDq : plus1 = 1, minus1 = 0, PI = 57, DB = 1
N6.C3.D1.R0.S09: TxDq : plus1 = 1, minus1 = 0, PI = 27, DB = 0
N0.C3.D1.R0.S05: TxDq : plus1 = 1, minus1 = 0, PI = 32, DB = 0
N4.C3.D1.R1.S13: TxDqs: plus1 = 1, minus1 = 0, PI = 55, DB = 1
N6.C3.D1.R0.S10: TxDqs: plus1 = 1, minus1 = 0, PI = 45, DB = 0
N0.C3.D1.R0.S06: TxDqs: plus1 = 1, minus1 = 0, PI = 15, DB = 1
N4.C3.D1.R1.S13: TxDq : plus1 = 1, minus1 = 0, PI = 18, DB = 0
N6.C3.D1.R0.S10: TxDq : plus1 = 1, minus1 = 0, PI = 12, DB = 1
N0.C3.D1.R0.S06: TxDq : plus1 = 1, minus1 = 0, PI = 43, DB = 0
N4.C3.D1.R1.S14: TxDqs: plus1 = 0, minus1 = 1, PI = 05, DB = 1
N6.C3.D1.R0.S11: TxDqs: plus1 = 1, minus1 = 0, PI = 36, DB = 0
N0.C3.D1.R0.S07: TxDqs: plus1 = 1, minus1 = 0, PI = 35, DB = 0
N4.C3.D1.R1.S14: TxDq : plus1 = 1, minus1 = 0, PI = 34, DB = 0
N6.C3.D1.R0.S11: TxDq : plus1 = 0, minus1 = 1, PI = 04, DB = 1
N0.C3.D1.R0.S07: TxDq : plus1 = 0, minus1 = 1, PI = 00, DB = 1
N4.C3.D1.R1.S15: TxDqs: plus1 = 1, minus1 = 0, PI = 18, DB = 0
N6.C3.D1.R0.S12: TxDqs: plus1 = 1, minus1 = 0, PI = 21, DB = 0
N0.C3.D1.R0.S08: TxDqs: plus1 = 1, minus1 = 0, PI = 02, DB = 1
N4.C3.D1.R1.S15: TxDq : plus1 = 1, minus1 = 0, PI = 48, DB = 0
N6.C3.D1.R0.S12: TxDq : plus1 = 1, minus1 = 0, PI = 53, DB = 1
N0.C3.D1.R0.S08: TxDq : plus1 = 1, minus1 = 0, PI = 31, DB = 0
N4.C3.D1.R1.S16: TxDqs: plus1 = 1, minus1 = 0, PI = 36, DB = 0
N6.C3.D1.R0.S13: TxDqs: plus1 = 1, minus1 = 0, PI = 49, DB = 1
N0.C3.D1.R0.S09: TxDqs: plus1 = 0, minus1 = 1, PI = 03, DB = 1
N4.C3.D1.R1.S16: TxDq : plus1 = 0, minus1 = 1, PI = 01, DB = 1
N6.C3.D1.R0.S13: TxDq : plus1 = 1, minus1 = 0, PI = 15, DB = 1
N0.C3.D1.R0.S09: TxDq : plus1 = 1, minus1 = 0, PI = 30, DB = 0
N4.C3.D1.R1.S17: TxDqs: plus1 = 0, minus1 = 1, PI = 05, DB = 1
N6.C3.D1.R0.S14: TxDqs: plus1 = 1, minus1 = 0, PI = 63, DB = 1
N0.C3.D1.R0.S10: TxDqs: plus1 = 1, minus1 = 0, PI = 51, DB = 1
N4.C3.D1.R1.S17: TxDq : plus1 = 1, minus1 = 0, PI = 33, DB = 0
N6.C3.D1.R0.S14: TxDq : plus1 = 1, minus1 = 0, PI = 32, DB = 0
N0.C3.D1.R0.S10: TxDq : plus1 = 1, minus1 = 0, PI = 16, DB = 0
END_DATA_TX_DQ
N6.C3.D1.R0.S15: TxDqs: plus1 = 1, minus1 = 0, PI = 12, DB = 1
N0.C3.D1.R0.S11: TxDqs: plus1 = 1, minus1 = 0, PI = 40, DB = 0
N4: RunTrainStep: Final status = 0
N6.C3.D1.R0.S15: TxDq : plus1 = 1, minus1 = 0, PI = 43, DB = 0
N0.C3.D1.R0.S11: TxDq : plus1 = 1, minus1 = 0, PI = 05, DB = 1

END - Basic Write DQ/DQS Training      Time         54358 ms
N6.C3.D1.R0.S16: TxDqs: plus1 = 1, minus1 = 0, PI = 30, DB = 0
N0.C3.D1.R0.S12: TxDqs: plus1 = 1, minus1 = 0, PI = 25, DB = 0
N4.C0: JCK cmd timing = 1N
N6.C3.D1.R0.S16: TxDq : plus1 = 1, minus1 = 0, PI = 62, DB = 1
N0.C3.D1.R0.S12: TxDq : plus1 = 1, minus1 = 0, PI = 53, DB = 1
N4.C0: RdCmd2DataValidLatency = 21, (dlyFrmS = 15, clEff = 10, earlyCas = 0, selNTiming = 0)
N6.C3.D1.R0.S17: TxDqs: plus1 = 0, minus1 = 1, PI = 00, DB = 1
N0.C3.D1.R0.S13: TxDqs: plus1 = 1, minus1 = 0, PI = 55, DB = 1
N4.C1: RdCmd2DataValidLatency = 21, (dlyFrmS = 15, clEff = 10, earlyCas = 0, selNTiming = 0)
N6.C3.D1.R0.S17: TxDq : plus1 = 1, minus1 = 0, PI = 30, DB = 0
N0.C3.D1.R0.S13: TxDq : plus1 = 1, minus1 = 0, PI = 20, DB = 0
N4.C2: JCK cmd timing = 1N
N6.C3.D1.R1.S00: TxDqs: plus1 = 1, minus1 = 0, PI = 63, DB = 1
N0.C3.D1.R0.S14: TxDqs: plus1 = 0, minus1 = 1, PI = 03, DB = 1
N4.C2: RdCmd2DataValidLatency = 21, (dlyFrmS = 15, clEff = 10, earlyCas = 0, selNTiming = 0)
N6.C3.D1.R1.S00: TxDq : plus1 = 1, minus1 = 0, PI = 31, DB = 0
N0.C3.D1.R0.S14: TxDq : plus1 = 1, minus1 = 0, PI = 33, DB = 0
N4.C3: RdCmd2DataValidLatency = 21, (dlyFrmS = 15, clEff = 10, earlyCas = 0, selNTiming = 0)
N6.C3.D1.R1.S01: TxDqs: plus1 = 1, minus1 = 0, PI = 45, DB = 0
N0.C3.D1.R0.S15: TxDqs: plus1 = 1, minus1 = 0, PI = 17, DB = 0
N4: JckSetOdtDynTiming[2] BL8:
N6.C3.D1.R1.S01: TxDq : plus1 = 1, minus1 = 0, PI = 13, DB = 1
N0.C3.D1.R0.S15: TxDq : plus1 = 1, minus1 = 0, PI = 45, DB = 0
N2: 
Get Tx Dq margins...
N6.C3.D1.R1.S02: TxDqs: plus1 = 1, minus1 = 0, PI = 34, DB = 0
N0.C3.D1.R0.S16: TxDqs: plus1 = 1, minus1 = 0, PI = 32, DB = 0
N2: GetMargins: Level = 1, group = 12, mode = 0, scope = 3
N4.C0: minRcvEnDelay = 200 maxRcvEnDelay = 300 ==> rdwidth = 6 rddly = 2 wrwidth = 6 wrdly = 0
N6.C3.D1.R1.S02: TxDq : plus1 = 0, minus1 = 1, PI = 01, DB = 1
N0.C3.D1.R0.S16: TxDq : plus1 = 1, minus1 = 0, PI = 62, DB = 1
N4.C1: minRcvEnDelay = 193 maxRcvEnDelay = 331 ==> rdwidth = 6 rddly = 2 wrwidth = 6 wrdly = 0
N6.C3.D1.R1.S03: TxDqs: plus1 = 1, minus1 = 0, PI = 21, DB = 0
N0.C3.D1.R0.S17: TxDqs: plus1 = 1, minus1 = 0, PI = 01, DB = 1
N4.C2: minRcvEnDelay = 196 maxRcvEnDelay = 302 ==> rdwidth = 6 rddly = 2 wrwidth = 6 wrdly = 0
N6.C3.D1.R1.S03: TxDq : plus1 = 1, minus1 = 0, PI = 52, DB = 1
N0.C3.D1.R0.S17: TxDq : plus1 = 1, minus1 = 0, PI = 32, DB = 0
N4.C3: minRcvEnDelay = 203 maxRcvEnDelay = 329 ==> rdwidth = 6 rddly = 2 wrwidth = 6 wrdly = 0
N6.C3.D1.R1.S04: TxDqs: plus1 = 1, minus1 = 0, PI = 49, DB = 1
N0.C3.D1.R1.S00: TxDqs: plus1 = 0, minus1 = 1, PI = 03, DB = 1
N4.C0: Memory Electrical TurnAround timings:
N6.C3.D1.R1.S04: TxDq : plus1 = 1, minus1 = 0, PI = 15, DB = 1
N0.C3.D1.R1.S00: TxDq : plus1 = 1, minus1 = 0, PI = 31, DB = 0
N4.C0:      tCCD  =  0, tWWDR =  3, tRRDD =  2, tWWDD =  3, tWRDR =  1, tWRDR_UPPER =  0, tRRDR =  0
N6.C3.D1.R1.S05: TxDqs: plus1 = 1, minus1 = 0, PI = 62, DB = 1
N0.C3.D1.R1.S01: TxDqs: plus1 = 1, minus1 = 0, PI = 49, DB = 1
N4.C0:      tRWDD =  2, tRWDR =  2, tWRDD =  1, tRWSR =  2
N6.C3.D1.R1.S05: TxDq : plus1 = 1, minus1 = 0, PI = 29, DB = 0
N0.C3.D1.R1.S01: TxDq : plus1 = 1, minus1 = 0, PI = 14, DB = 1
N4.C0: TCOTHP: T_RWSR = 0x2, T_RWDD = 0x2
N6.C3.D1.R1.S06: TxDqs: plus1 = 1, minus1 = 0, PI = 13, DB = 1
N0.C3.D1.R1.S02: TxDqs: plus1 = 1, minus1 = 0, PI = 40, DB = 0
N4.C0:      tCCD_WR =  0, tWRDS =  2, tRWDS =  2, tWWDS =  3, tRRDS =  1
N6.C3.D1.R1.S06: TxDq : plus1 = 1, minus1 = 0, PI = 44, DB = 0
N0.C3.D1.R1.S02: TxDq : plus1 = 1, minus1 = 0, PI = 05, DB = 1
N4.C1: Memory Electrical TurnAround timings:
N6.C3.D1.R1.S07: TxDqs: plus1 = 1, minus1 = 0, PI = 30, DB = 0
N0.C3.D1.R1.S03: TxDqs: plus1 = 1, minus1 = 0, PI = 24, DB = 0
N4.C1:      tCCD  =  0, tWWDR =  3, tRRDD =  2, tWWDD =  3, tWRDR =  1, tWRDR_UPPER =  0, tRRDR =  0
N6.C3.D1.R1.S07: TxDq : plus1 = 1, minus1 = 0, PI = 60, DB = 1
N0.C3.D1.R1.S03: TxDq : plus1 = 1, minus1 = 0, PI = 53, DB = 1
N4.C1:      tRWDD =  2, tRWDR =  2, tWRDD =  1, tRWSR =  2
N6.C3.D1.R1.S08: TxDqs: plus1 = 0, minus1 = 1, PI = 00, DB = 1
N0.C3.D1.R1.S04: TxDqs: plus1 = 1, minus1 = 0, PI = 53, DB = 1
N4.C1: TCOTHP: T_RWSR = 0x2, T_RWDD = 0x2
N6.C3.D1.R1.S08: TxDq : plus1 = 1, minus1 = 0, PI = 31, DB = 0
N0.C3.D1.R1.S04: TxDq : plus1 = 1, minus1 = 0, PI = 19, DB = 0
N4.C1:      tCCD_WR =  0, tWRDS =  2, tRWDS =  2, tWWDS =  3, tRRDS =  1
N6.C3.D1.R1.S09: TxDqs: plus1 = 1, minus1 = 0, PI = 62, DB = 1
N0.C3.D1.R1.S05: TxDqs: plus1 = 0, minus1 = 1, PI = 02, DB = 1
N4.C2: Memory Electrical TurnAround timings:
N6.C3.D1.R1.S09: TxDq : plus1 = 1, minus1 = 0, PI = 27, DB = 0
N0.C3.D1.R1.S05: TxDq : plus1 = 1, minus1 = 0, PI = 32, DB = 0
N4.C2:      tCCD  =  0, tWWDR =  3, tRRDD =  2, tWWDD =  3, tWRDR =  1, tWRDR_UPPER =  0, tRRDR =  0
N6.C3.D1.R1.S10: TxDqs: plus1 = 1, minus1 = 0, PI = 45, DB = 0
N0.C3.D1.R1.S06: TxDqs: plus1 = 1, minus1 = 0, PI = 15, DB = 1
N4.C2:      tRWDD =  2, tRWDR =  2, tWRDD =  1, tRWSR =  2
N6.C3.D1.R1.S10: TxDq : plus1 = 1, minus1 = 0, PI = 12, DB = 1
N0.C3.D1.R1.S06: TxDq : plus1 = 1, minus1 = 0, PI = 43, DB = 0
N4.C2: TCOTHP: T_RWSR = 0x2, T_RWDD = 0x2
N6.C3.D1.R1.S11: TxDqs: plus1 = 1, minus1 = 0, PI = 36, DB = 0
N0.C3.D1.R1.S07: TxDqs: plus1 = 1, minus1 = 0, PI = 35, DB = 0
N4.C2:      tCCD_WR =  0, tWRDS =  2, tRWDS =  2, tWWDS =  3, tRRDS =  1
N6.C3.D1.R1.S11: TxDq : plus1 = 0, minus1 = 1, PI = 04, DB = 1
N0.C3.D1.R1.S07: TxDq : plus1 = 0, minus1 = 1, PI = 00, DB = 1
N4.C3: Memory Electrical TurnAround timings:
N6.C3.D1.R1.S12: TxDqs: plus1 = 1, minus1 = 0, PI = 21, DB = 0
N0.C3.D1.R1.S08: TxDqs: plus1 = 1, minus1 = 0, PI = 02, DB = 1
N4.C3:      tCCD  =  0, tWWDR =  3, tRRDD =  2, tWWDD =  3, tWRDR =  1, tWRDR_UPPER =  0, tRRDR =  0
N6.C3.D1.R1.S12: TxDq : plus1 = 1, minus1 = 0, PI = 53, DB = 1
N0.C3.D1.R1.S08: TxDq : plus1 = 1, minus1 = 0, PI = 31, DB = 0
N4.C3:      tRWDD =  2, tRWDR =  2, tWRDD =  1, tRWSR =  2
N6.C3.D1.R1.S13: TxDqs: plus1 = 1, minus1 = 0, PI = 49, DB = 1
N0.C3.D1.R1.S09: TxDqs: plus1 = 0, minus1 = 1, PI = 03, DB = 1
N4.C3: TCOTHP: T_RWSR = 0x2, T_RWDD = 0x2
N6.C3.D1.R1.S13: TxDq : plus1 = 1, minus1 = 0, PI = 15, DB = 1
N0.C3.D1.R1.S09: TxDq : plus1 = 1, minus1 = 0, PI = 30, DB = 0
N4.C3:      tCCD_WR =  0, tWRDS =  2, tRWDS =  2, tWWDS =  3, tRRDS =  1
N6.C3.D1.R1.S14: TxDqs: plus1 = 1, minus1 = 0, PI = 63, DB = 1
N0.C3.D1.R1.S10: TxDqs: plus1 = 1, minus1 = 0, PI = 51, DB = 1

START - Rd Timing Centering 2D Training
N6.C3.D1.R1.S14: TxDq : plus1 = 1, minus1 = 0, PI = 32, DB = 0
N0.C3.D1.R1.S10: TxDq : plus1 = 1, minus1 = 0, PI = 16, DB = 0
N4: 

Adv Strobe Centering(MARGIN_RX_DQ): GetMultiVref: patternLength = 13, stepSize = 1, numPoints = 1
N6.C3.D1.R1.S15: TxDqs: plus1 = 1, minus1 = 0, PI = 12, DB = 1
N0.C3.D1.R1.S11: TxDqs: plus1 = 1, minus1 = 0, PI = 40, DB = 0
N4: GetMargins: Level = 1, group = 11, mode = 0, scope = 4
N6.C3.D1.R1.S15: TxDq : plus1 = 1, minus1 = 0, PI = 43, DB = 0
N0.C3.D1.R1.S11: TxDq : plus1 = 1, minus1 = 0, PI = 05, DB = 1
N6.C3.D1.R1.S16: TxDqs: plus1 = 1, minus1 = 0, PI = 30, DB = 0
N0.C3.D1.R1.S12: TxDqs: plus1 = 1, minus1 = 0, PI = 25, DB = 0
N6.C3.D1.R1.S16: TxDq : plus1 = 1, minus1 = 0, PI = 62, DB = 1
N0.C3.D1.R1.S12: TxDq : plus1 = 1, minus1 = 0, PI = 53, DB = 1
N6.C3.D1.R1.S17: TxDqs: plus1 = 0, minus1 = 1, PI = 00, DB = 1
N0.C3.D1.R1.S13: TxDqs: plus1 = 1, minus1 = 0, PI = 55, DB = 1
N6.C3.D1.R1.S17: TxDq : plus1 = 1, minus1 = 0, PI = 30, DB = 0
N0.C3.D1.R1.S13: TxDq : plus1 = 1, minus1 = 0, PI = 20, DB = 0
END_DATA_TX_DQ
N0.C3.D1.R1.S14: TxDqs: plus1 = 0, minus1 = 1, PI = 03, DB = 1
N6: RunTrainStep: Final status = 0
N0.C3.D1.R1.S14: TxDq : plus1 = 1, minus1 = 0, PI = 33, DB = 0

END - Basic Write DQ/DQS Training      Time         54218 ms
N0.C3.D1.R1.S15: TxDqs: plus1 = 1, minus1 = 0, PI = 17, DB = 0
N6.C0: JCK cmd timing = 1N
N0.C3.D1.R1.S15: TxDq : plus1 = 1, minus1 = 0, PI = 45, DB = 0
N6.C0: RdCmd2DataValidLatency = 21, (dlyFrmS = 15, clEff = 10, earlyCas = 0, selNTiming = 0)
N0.C3.D1.R1.S16: TxDqs: plus1 = 1, minus1 = 0, PI = 32, DB = 0
N6.C1: RdCmd2DataValidLatency = 21, (dlyFrmS = 15, clEff = 10, earlyCas = 0, selNTiming = 0)
N0.C3.D1.R1.S16: TxDq : plus1 = 1, minus1 = 0, PI = 62, DB = 1
N6.C2: JCK cmd timing = 1N
N0.C3.D1.R1.S17: TxDqs: plus1 = 1, minus1 = 0, PI = 01, DB = 1
N6.C2: RdCmd2DataValidLatency = 21, (dlyFrmS = 15, clEff = 10, earlyCas = 0, selNTiming = 0)
N0.C3.D1.R1.S17: TxDq : plus1 = 1, minus1 = 0, PI = 32, DB = 0
N6.C3: RdCmd2DataValidLatency = 21, (dlyFrmS = 15, clEff = 10, earlyCas = 0, selNTiming = 0)
END_DATA_TX_DQ
N6: JckSetOdtDynTiming[2] BL8:
N0: RunTrainStep: Final status = 0

END - Basic Write DQ/DQS Training      Time         54139 ms
Checkpoint Code: Socket 0, 0xB7, 0x11, 0x0000
N0.C0: JCK cmd timing = 1N
N0.C0: RdCmd2DataValidLatency = 21, (dlyFrmS = 15, clEff = 10, earlyCas = 0, selNTiming = 0)
N0.C1: RdCmd2DataValidLatency = 21, (dlyFrmS = 15, clEff = 10, earlyCas = 0, selNTiming = 0)
N6.C0: minRcvEnDelay = 205 maxRcvEnDelay = 309 ==> rdwidth = 6 rddly = 2 wrwidth = 6 wrdly = 0
N0.C2: JCK cmd timing = 1N
N6.C1: minRcvEnDelay = 202 maxRcvEnDelay = 335 ==> rdwidth = 6 rddly = 2 wrwidth = 6 wrdly = 0
N0.C2: RdCmd2DataValidLatency = 21, (dlyFrmS = 15, clEff = 10, earlyCas = 0, selNTiming = 0)
N6.C2: minRcvEnDelay = 211 maxRcvEnDelay = 308 ==> rdwidth = 6 rddly = 2 wrwidth = 6 wrdly = 0
N0.C3: RdCmd2DataValidLatency = 21, (dlyFrmS = 15, clEff = 10, earlyCas = 0, selNTiming = 0)
N6.C3: minRcvEnDelay = 192 maxRcvEnDelay = 329 ==> rdwidth = 6 rddly = 2 wrwidth = 6 wrdly = 0
N0: JckSetOdtDynTiming[2] BL8:
N6.C0: Memory Electrical TurnAround timings:
N6.C0:      tCCD  =  0, tWWDR =  3, tRRDD =  2, tWWDD =  3, tWRDR =  1, tWRDR_UPPER =  0, tRRDR =  0
N6.C0:      tRWDD =  2, tRWDR =  2, tWRDD =  1, tRWSR =  2
N6.C0: TCOTHP: T_RWSR = 0x2, T_RWDD = 0x2
N6.C0:      tCCD_WR =  0, tWRDS =  2, tRWDS =  2, tWWDS =  3, tRRDS =  1
N0.C0: minRcvEnDelay = 198 maxRcvEnDelay = 301 ==> rdwidth = 6 rddly = 2 wrwidth = 6 wrdly = 0
N6.C1: Memory Electrical TurnAround timings:
N0.C1: minRcvEnDelay = 192 maxRcvEnDelay = 329 ==> rdwidth = 6 rddly = 2 wrwidth = 6 wrdly = 0
N6.C1:      tCCD  =  0, tWWDR =  3, tRRDD =  2, tWWDD =  3, tWRDR =  1, tWRDR_UPPER =  0, tRRDR =  0
N0.C2: minRcvEnDelay = 198 maxRcvEnDelay = 305 ==> rdwidth = 6 rddly = 2 wrwidth = 6 wrdly = 0
N6.C1:      tRWDD =  2, tRWDR =  2, tWRDD =  1, tRWSR =  2
N0.C3: minRcvEnDelay = 201 maxRcvEnDelay = 332 ==> rdwidth = 6 rddly = 2 wrwidth = 6 wrdly = 0
N6.C1: TCOTHP: T_RWSR = 0x2, T_RWDD = 0x2
N0.C0: Memory Electrical TurnAround timings:
N6.C1:      tCCD_WR =  0, tWRDS =  2, tRWDS =  2, tWWDS =  3, tRRDS =  1
N0.C0:      tCCD  =  0, tWWDR =  3, tRRDD =  2, tWWDD =  3, tWRDR =  1, tWRDR_UPPER =  0, tRRDR =  0
N6.C2: Memory Electrical TurnAround timings:
N0.C0:      tRWDD =  2, tRWDR =  2, tWRDD =  1, tRWSR =  2
N6.C2:      tCCD  =  0, tWWDR =  3, tRRDD =  2, tWWDD =  3, tWRDR =  1, tWRDR_UPPER =  0, tRRDR =  0
N0.C0: TCOTHP: T_RWSR = 0x2, T_RWDD = 0x2
N6.C2:      tRWDD =  2, tRWDR =  2, tWRDD =  1, tRWSR =  2
N0.C0:      tCCD_WR =  0, tWRDS =  2, tRWDS =  2, tWWDS =  3, tRRDS =  1
N6.C2: TCOTHP: T_RWSR = 0x2, T_RWDD = 0x2
N0.C1: Memory Electrical TurnAround timings:
N6.C2:      tCCD_WR =  0, tWRDS =  2, tRWDS =  2, tWWDS =  3, tRRDS =  1
N0.C1:      tCCD  =  0, tWWDR =  3, tRRDD =  2, tWWDD =  3, tWRDR =  1, tWRDR_UPPER =  0, tRRDR =  0
N6.C3: Memory Electrical TurnAround timings:
N0.C1:      tRWDD =  2, tRWDR =  2, tWRDD =  1, tRWSR =  2
N6.C3:      tCCD  =  0, tWWDR =  3, tRRDD =  2, tWWDD =  3, tWRDR =  1, tWRDR_UPPER =  0, tRRDR =  0
N0.C1: TCOTHP: T_RWSR = 0x2, T_RWDD = 0x2
N6.C3:      tRWDD =  2, tRWDR =  2, tWRDD =  1, tRWSR =  2
N0.C1:      tCCD_WR =  0, tWRDS =  2, tRWDS =  2, tWWDS =  3, tRRDS =  1
N6.C3: TCOTHP: T_RWSR = 0x2, T_RWDD = 0x2
N0.C2: Memory Electrical TurnAround timings:
N6.C3:      tCCD_WR =  0, tWRDS =  2, tRWDS =  2, tWWDS =  3, tRRDS =  1
N0.C2:      tCCD  =  0, tWWDR =  3, tRRDD =  2, tWWDD =  3, tWRDR =  1, tWRDR_UPPER =  0, tRRDR =  0

START - Rd Timing Centering 2D Training
N0.C2:      tRWDD =  2, tRWDR =  2, tWRDD =  1, tRWSR =  2
N6: 

Adv Strobe Centering(MARGIN_RX_DQ): GetMultiVref: patternLength = 13, stepSize = 1, numPoints = 1
N0.C2: TCOTHP: T_RWSR = 0x2, T_RWDD = 0x2
N0.C2:      tCCD_WR =  0, tWRDS =  2, tRWDS =  2, tWWDS =  3, tRRDS =  1
N6: GetMargins: Level = 1, group = 11, mode = 0, scope = 4
N0.C3: Memory Electrical TurnAround timings:
N0.C3:      tCCD  =  0, tWWDR =  3, tRRDD =  2, tWWDD =  3, tWRDR =  1, tWRDR_UPPER =  0, tRRDR =  0
N0.C3:      tRWDD =  2, tRWDR =  2, tWRDD =  1, tRWSR =  2
N0.C3: TCOTHP: T_RWSR = 0x2, T_RWDD = 0x2
N0.C3:      tCCD_WR =  0, tWRDS =  2, tRWDS =  2, tWWDS =  3, tRRDS =  1

START - Rd Timing Centering 2D Training
Checkpoint Code: Socket 0, 0xB7, 0x08, 0x0000
N0: 

Adv Strobe Centering(MARGIN_RX_DQ): GetMultiVref: patternLength = 13, stepSize = 1, numPoints = 1
N0: GetMargins: Level = 1, group = 11, mode = 0, scope = 4
START_DATA_RX_DQS_ADV
Results for N4.C0.D0.R0: 
           0   1   2   3   4   5   6   7   8   9  10  11  12  13  14  15  16  17
-------------------------------------------------------------------------------
Vref offset: 0
Left:    -22 -17 -21 -18 -20 -21 -20 -19 -14 -20 -20 -19 -21 -20 -24 -20 -19 -17
Right:    21  18  15  17  14  15  15  19  22  17  16  20  20  16  14  16  22  22
-------------------------------------------------------------------------------
Prev Pi:  36  36  38  37  37  37  38  38  37  38  36  37  37  36  37  36  36  36
New Pi:   36  36  35  37  34  34  36  38  41  37  34  37  37  34  32  34  37  38
Diff:      0   0  -3   0  -3  -3  -2   0   4  -1  -2   0   0  -2  -5  -2   1   2

Results for N4.C0.D0.R1: 
           0   1   2   3   4   5   6   7   8   9  10  11  12  13  14  15  16  17
-------------------------------------------------------------------------------
Vref offset: 0
Left:    -22 -16 -21 -19 -20 -22 -19 -20 -15 -20 -20 -19 -22 -19 -23 -21 -18 -18
Right:    18  21  15  19  14  13  13  21  24  17  18  20  22  16  12  17  22  25
-------------------------------------------------------------------------------
Prev Pi:  36  36  38  37  37  37  38  38  37  38  36  37  37  36  37  36  36  36
New Pi:   34  38  35  37  34  33  35  38  41  37  35  37  37  35  32  34  38  39
Diff:     -2   2  -3   0  -3  -4  -3   0   4  -1  -1   0   0  -1  -5  -2   2   3

Results for N4.C0.D1.R0: 
           0   1   2   3   4   5   6   7   8   9  10  11  12  13  14  15  16  17
-------------------------------------------------------------------------------
Vref offset: 0
Left:    -21 -15 -20 -16 -19 -21 -19 -17 -15 -18 -18 -18 -21 -21 -21 -16 -17 -15
Right:    17  15  13  17  12  12  15  18  20  12  17  16  15  15  13  16  20  23
-------------------------------------------------------------------------------
Prev Pi:  37  38  39  37  38  38  39  40  40  40  37  38  39  38  38  37  38  38
New Pi:   35  38  36  37  35  34  37  40  42  37  37  37  36  35  34  37  39  42
Diff:     -2   0  -3   0  -3  -4  -2   0   2  -3   0  -1  -3  -3  -4   0   1   4

Results for N4.C0.D1.R1: 
           0   1   2   3   4   5   6   7   8   9  10  11  12  13  14  15  16  17
-------------------------------------------------------------------------------
Vref offset: 0
Left:    -21 -15 -20 -17 -20 -20 -18 -16 -15 -19 -19 -17 -22 -21 -21 -15 -16 -16
Right:    15  16  13  19  13  12  12  16  21  12  15  19  17  15  12  16  19  25
-------------------------------------------------------------------------------
Prev Pi:  37  38  39  37  38  38  39  40  40  40  37  38  39  38  38  37  38  38
New Pi:   34  38  36  38  35  34  36  40  43  37  35  39  37  35  34  37  39  42
Diff:     -3   0  -3   1  -3  -4  -3   0   3  -3  -2   1  -2  -3  -4   0   1   4

Results for N4.C1.D0.R0: 
           0   1   2   3   4   5   6   7   8   9  10  11  12  13  14  15  16  17
-------------------------------------------------------------------------------
Vref offset: 0
Left:    -20 -21 -18 -18 -21 -21 -19 -21 -20 -19 -22 -19 -22 -19 -20 -20 -17 -12
Right:    14  23  16  14  14  16  19  19  18  16  19  19  15  16  14   9  23  17
-------------------------------------------------------------------------------
Prev Pi:  37  37  37  37  38  36  39  39  38  36  35  34  36  37  34  38  36  37
New Pi:   34  38  36  35  35  34  39  38  37  35  34  34  33  36  31  33  39  39
Diff:     -3   1  -1  -2  -3  -2   0  -1  -1  -1  -1   0  -3  -1  -3  -5   3   2

Results for N4.C1.D0.R1: 
           0   1   2   3   4   5   6   7   8   9  10  11  12  13  14  15  16  17
-------------------------------------------------------------------------------
Vref offset: 0
Left:    -20 -22 -18 -18 -21 -21 -20 -21 -19 -19 -22 -19 -21 -19 -20 -20 -17 -13
Right:    15  22  13  14  13  16  18  20  20  16  20  20  14  15  14  11  23  19
-------------------------------------------------------------------------------
Prev Pi:  37  37  37  37  38  36  39  39  38  36  35  34  36  37  34  38  36  37
New Pi:   35  37  35  35  34  34  38  39  38  35  34  34  33  35  31  34  39  40
Diff:     -2   0  -2  -2  -4  -2  -1   0   0  -1  -1   0  -3  -2  -3  -4   3   3

Results for N4.C1.D1.R0: 
           0   1   2   3   4   5   6   7   8   9  10  11  12  13  14  15  16  17
-------------------------------------------------------------------------------
Vref offset: 0
Left:    -19 -20 -16 -12 -19 -20 -16 -17 -14 -17 -18 -15 -20 -17 -14 -14 -12  -9
Right:    13  20  14  11  11  11  18  16  19  14  17  18  11  12  13  11  21  17
-------------------------------------------------------------------------------
Prev Pi:  39  39  39  39  41  39  40  41  39  38  38  36  39  40  36  40  38  40
New Pi:   36  39  38  39  37  35  41  41  41  37  38  37  35  38  36  39  42  44
Diff:     -3   0  -1   0  -4  -4   1   0   2  -1   0   1  -4  -2   0  -1   4   4

Results for N4.C1.D1.R1: 
           0   1   2   3   4   5   6   7   8   9  10  11  12  13  14  15  16  17
-------------------------------------------------------------------------------
Vref offset: 0
Left:    -19 -21 -17 -13 -18 -20 -16 -17 -14 -18 -19 -16 -19 -17 -14 -14 -12  -8
Right:    11  20  13  13  10  13  17  12  16  14  18  18  11  12  12   9  20  18
-------------------------------------------------------------------------------
Prev Pi:  39  39  39  39  41  39  40  41  39  38  38  36  39  40  36  40  38  40
New Pi:   35  39  37  39  37  36  40  39  40  36  38  37  35  38  35  38  42  45
Diff:     -4   0  -2   0  -4  -3   0  -2   1  -2   0   1  -4  -2  -1  -2   4   5

Results for N4.C2.D0.R0: 
           0   1   2   3   4   5   6   7   8   9  10  11  12  13  14  15  16  17
-------------------------------------------------------------------------------
Vref offset: 0
Left:    -21 -20 -20 -21 -17 -15 -20 -20 -19 -18 -14 -16 -18 -17 -19 -21 -20 -18
Right:    21  24  14  25  16  22  17  20  22  22  16  22  26  20  20  19  23  24
-------------------------------------------------------------------------------
Prev Pi:  36  37  36  35  36  37  38  37  37  36  38  34  36  32  38  37  36  36
New Pi:   36  39  33  37  36  40  37  37  38  38  39  37  40  33  38  36  37  39
Diff:      0   2  -3   2   0   3  -1   0   1   2   1   3   4   1   0  -1   1   3

Results for N4.C2.D0.R1: 
           0   1   2   3   4   5   6   7   8   9  10  11  12  13  14  15  16  17
-------------------------------------------------------------------------------
Vref offset: 0
Left:    -20 -20 -20 -22 -18 -13 -20 -20 -20 -19 -14 -15 -19 -18 -18 -21 -20 -19
Right:    21  27  15  26  15  23  14  20  21  20  20  23  25  18  18  19  21  25
-------------------------------------------------------------------------------
Prev Pi:  36  37  36  35  36  37  38  37  37  36  38  34  36  32  38  37  36  36
New Pi:   36  40  34  37  35  42  35  37  37  36  41  38  39  32  38  36  36  39
Diff:      0   3  -2   2  -1   5  -3   0   0   0   3   4   3   0   0  -1   0   3

Results for N4.C2.D1.R0: 
           0   1   2   3   4   5   6   7   8   9  10  11  12  13  14  15  16  17
-------------------------------------------------------------------------------
Vref offset: 0
Left:    -19 -19 -18 -18 -14  -9 -15 -14 -19 -15 -11 -10 -14 -16 -17 -20 -15 -15
Right:    18  21  16  23  14  22  15  17  19  21  16  21  24  14  16  14  20  21
-------------------------------------------------------------------------------
Prev Pi:  37  39  37  36  37  38  40  39  39  37  41  36  37  36  40  39  37  37
New Pi:   37  40  36  38  37  44  40  40  39  40  43  41  42  35  40  36  39  40
Diff:      0   1  -1   2   0   6   0   1   0   3   2   5   5  -1   0  -3   2   3

Results for N4.C2.D1.R1: 
           0   1   2   3   4   5   6   7   8   9  10  11  12  13  14  15  16  17
-------------------------------------------------------------------------------
Vref offset: 0
Left:    -20 -19 -18 -18 -14  -9 -15 -15 -18 -14 -13 -11 -15 -17 -16 -19 -16 -16
Right:    19  23  13  25  14  22  11  19  19  20  12  21  25  14  16  16  19  23
-------------------------------------------------------------------------------
Prev Pi:  37  39  37  36  37  38  40  39  39  37  41  36  37  36  40  39  37  37
New Pi:   37  41  35  39  37  44  38  41  39  40  41  41  42  35  40  38  38  40
Diff:      0   2  -2   3   0   6  -2   2   0   3   0   5   5  -1   0  -1   1   3

Results for N4.C3.D0.R0: 
           0   1   2   3   4   5   6   7   8   9  10  11  12  13  14  15  16  17
-------------------------------------------------------------------------------
Vref offset: 0
Left:    -19 -20 -16 -19 -19 -20 -20 -16 -19 -20 -22 -21 -22 -24 -19 -20 -21 -21
Right:    21  19  22  23  19  21  18  15  24  17  20  22  20  24  26  17  23  20
-------------------------------------------------------------------------------
Prev Pi:  37  39  36  36  39  38  39  37  35  37  36  36  37  36  37  38  35  37
New Pi:   38  39  39  38  39  38  38  37  37  36  35  36  36  36  40  37  36  37
Diff:      1   0   3   2   0   0  -1   0   2  -1  -1   0  -1   0   3  -1   1   0

Results for N4.C3.D0.R1: 
           0   1   2   3   4   5   6   7   8   9  10  11  12  13  14  15  16  17
-------------------------------------------------------------------------------
Vref offset: 0
Left:    -19 -20 -17 -19 -20 -20 -20 -17 -17 -21 -23 -21 -21 -23 -18 -21 -19 -22
Right:    22  18  22  24  18  20  17  19  22  21  20  22  21  23  27  16  22  20
-------------------------------------------------------------------------------
Prev Pi:  37  39  36  36  39  38  39  37  35  37  36  36  37  36  37  38  35  37
New Pi:   38  38  38  38  38  38  38  38  37  37  35  36  37  36  41  36  36  36
Diff:      1  -1   2   2  -1   0  -1   1   2   0  -1   0   0   0   4  -2   1  -1

Results for N4.C3.D1.R0: 
           0   1   2   3   4   5   6   7   8   9  10  11  12  13  14  15  16  17
-------------------------------------------------------------------------------
Vref offset: 0
Left:    -16 -17 -14 -16 -13 -15 -18 -11 -12 -18 -20 -19 -19 -19 -15 -17 -19 -20
Right:    18  17  22  19  15  17  16  16  21  16  20  19  18  20  23  12  21  17
-------------------------------------------------------------------------------
Prev Pi:  40  41  37  39  41  40  41  38  36  39  38  37  39  37  39  40  37  39
New Pi:   41  41  41  40  42  41  40  40  40  38  38  37  39  37  43  38  38  38
Diff:      1   0   4   1   1   1  -1   2   4  -1   0   0   0   0   4  -2   1  -1

Results for N4.C3.D1.R1: 
           0   1   2   3   4   5   6   7   8   9  10  11  12  13  14  15  16  17
-------------------------------------------------------------------------------
Vref offset: 0
Left:    -16 -17 -14 -16 -14 -16 -17 -11 -11 -18 -20 -20 -19 -19 -14 -16 -18 -19
Right:    18  18  18  20  16  17  16  14  21  18  21  20  16  21  24  13  19  19
-------------------------------------------------------------------------------
Prev Pi:  40  41  37  39  41  40  41  38  36  39  38  37  39  37  39  40  37  39
New Pi:   41  41  39  41  42  40  41  39  41  39  38  37  38  38  44  39  37  39
Diff:      1   0   2   2   1   0   0   1   5   0   0   0  -1   1   5  -1   0   0

STOP_DATA_RX_DQS_ADV
START_DATA_RX_DQS_ADV
Results for N6.C0.D0.R0: 
           0   1   2   3   4   5   6   7   8   9  10  11  12  13  14  15  16  17
-------------------------------------------------------------------------------
Vref offset: 0
Left:    -22 -24 -24 -23 -18 -24 -24 -24 -24 -25 -21 -23 -23 -25 -26 -27 -25 -24
Right:    22  23  22  24  26  25  25  24  21  24  21  23  30  26  25  25  24  23
-------------------------------------------------------------------------------
Prev Pi:  31  33  33  33  33  34  33  34  34  33  31  33  33  33  34  34  35  34
New Pi:   31  33  32  33  37  34  33  34  33  33  31  33  36  33  34  33  35  34
Diff:      0   0  -1   0   4   0   0   0  -1   0   0   0   3   0   0  -1   0   0

Results for N6.C0.D0.R1: 
           0   1   2   3   4   5   6   7   8   9  10  11  12  13  14  15  16  17
-------------------------------------------------------------------------------
Vref offset: 0
Left:    -22 -25 -24 -22 -20 -24 -24 -24 -24 -24 -21 -23 -22 -25 -26 -26 -25 -24
Right:    22  26  24  25  24  24  26  27  24  23  25  20  27  24  23  25  23  25
-------------------------------------------------------------------------------
Prev Pi:  31  33  33  33  33  34  33  34  34  33  31  33  33  33  34  34  35  34
New Pi:   31  33  33  34  35  34  34  35  34  33  33  32  35  33  33  34  34  34
Diff:      0   0   0   1   2   0   1   1   0   0   2  -1   2   0  -1   0  -1   0

Results for N6.C0.D1.R0: 
           0   1   2   3   4   5   6   7   8   9  10  11  12  13  14  15  16  17
-------------------------------------------------------------------------------
Vref offset: 0
Left:    -23 -25 -25 -21 -17 -23 -24 -24 -24 -25 -21 -23 -23 -26 -26 -25 -25 -24
Right:    18  24  20  22  25  23  24  23  20  21  19  19  25  24  22  22  23  21
-------------------------------------------------------------------------------
Prev Pi:  34  35  36  34  34  35  35  36  36  35  34  35  35  35  36  36  37  36
New Pi:   32  35  34  34  38  35  35  36  34  33  33  33  36  34  34  35  36  35
Diff:     -2   0  -2   0   4   0   0   0  -2  -2  -1  -2   1  -1  -2  -1  -1  -1

Results for N6.C0.D1.R1: 
           0   1   2   3   4   5   6   7   8   9  10  11  12  13  14  15  16  17
-------------------------------------------------------------------------------
Vref offset: 0
Left:    -23 -25 -25 -22 -18 -23 -24 -24 -23 -25 -22 -23 -21 -25 -25 -25 -25 -25
Right:    23  23  19  26  25  23  23  23  18  21  20  20  28  25  21  23  22  22
-------------------------------------------------------------------------------
Prev Pi:  34  35  36  34  34  35  35  36  36  35  34  35  35  35  36  36  37  36
New Pi:   34  34  33  36  37  35  35  36  34  33  33  34  38  35  34  35  36  35
Diff:      0  -1  -3   2   3   0   0   0  -2  -2  -1  -1   3   0  -2  -1  -1  -1

Results for N6.C1.D0.R0: 
           0   1   2   3   4   5   6   7   8   9  10  11  12  13  14  15  16  17
-------------------------------------------------------------------------------
Vref offset: 0
Left:    -22 -24 -22 -24 -25 -25 -23 -20 -27 -26 -25 -21 -24 -22 -25 -24 -26 -25
Right:    19  23  24  31  29  27  23  27  24  22  26  25  24  26  27  20  26  25
-------------------------------------------------------------------------------
Prev Pi:  32  34  32  33  34  34  33  34  33  35  33  30  33  34  34  32  35  33
New Pi:   31  34  33  36  36  35  33  37  32  33  33  32  33  36  35  30  35  33
Diff:     -1   0   1   3   2   1   0   3  -1  -2   0   2   0   2   1  -2   0   0

Results for N6.C1.D0.R1: 
           0   1   2   3   4   5   6   7   8   9  10  11  12  13  14  15  16  17
-------------------------------------------------------------------------------
Vref offset: 0
Left:    -22 -24 -22 -24 -25 -25 -24 -21 -26 -25 -25 -21 -24 -23 -25 -24 -26 -25
Right:    24  23  21  30  28  30  25  28  25  21  26  26  26  28  24  23  24  24
-------------------------------------------------------------------------------
Prev Pi:  32  34  32  33  34  34  33  34  33  35  33  30  33  34  34  32  35  33
New Pi:   33  34  32  36  35  36  33  37  33  33  33  32  34  36  34  32  34  33
Diff:      1   0   0   3   1   2   0   3   0  -2   0   2   1   2   0   0  -1   0

Results for N6.C1.D1.R0: 
           0   1   2   3   4   5   6   7   8   9  10  11  12  13  14  15  16  17
-------------------------------------------------------------------------------
Vref offset: 0
Left:    -22 -22 -22 -24 -24 -25 -24 -18 -26 -24 -24 -21 -23 -20 -25 -26 -26 -22
Right:    20  21  23  29  28  27  22  28  22  21  24  23  23  25  23  18  24  22
-------------------------------------------------------------------------------
Prev Pi:  35  36  34  35  35  36  36  35  35  37  35  33  34  35  36  36  36  34
New Pi:   34  36  34  37  37  37  35  40  33  36  35  34  34  37  35  32  35  34
Diff:     -1   0   0   2   2   1  -1   5  -2  -1   0   1   0   2  -1  -4  -1   0

Results for N6.C1.D1.R1: 
           0   1   2   3   4   5   6   7   8   9  10  11  12  13  14  15  16  17
-------------------------------------------------------------------------------
Vref offset: 0
Left:    -21 -23 -22 -24 -24 -24 -23 -18 -26 -24 -23 -22 -23 -20 -25 -26 -26 -23
Right:    18  21  23  30  25  24  23  27  23  21  24  21  23  24  22  18  23  24
-------------------------------------------------------------------------------
Prev Pi:  35  36  34  35  35  36  36  35  35  37  35  33  34  35  36  36  36  34
New Pi:   34  35  34  38  35  36  36  39  34  36  35  33  34  37  35  32  35  34
Diff:     -1  -1   0   3   0   0   0   4  -1  -1   0   0   0   2  -1  -4  -1   0

Results for N6.C2.D0.R0: 
           0   1   2   3   4   5   6   7   8   9  10  11  12  13  14  15  16  17
-------------------------------------------------------------------------------
Vref offset: 0
Left:    -25 -24 -24 -23 -24 -27 -25 -26 -26 -26 -25 -24 -25 -29 -24 -27 -26 -22
Right:    21  27  26  25  22  22  25  24  25  26  24  26  28  25  23  25  24  25
-------------------------------------------------------------------------------
Prev Pi:  31  34  33  33  30  35  34  35  36  33  32  32  33  32  33  33  34  30
New Pi:   29  35  34  34  29  33  34  34  36  33  32  33  34  30  33  32  33  31
Diff:     -2   1   1   1  -1  -2   0  -1   0   0   0   1   1  -2   0  -1  -1   1

Results for N6.C2.D0.R1: 
           0   1   2   3   4   5   6   7   8   9  10  11  12  13  14  15  16  17
-------------------------------------------------------------------------------
Vref offset: 0
Left:    -25 -24 -24 -23 -25 -26 -25 -27 -27 -26 -25 -26 -25 -28 -24 -27 -26 -22
Right:    21  24  25  24  26  23  24  25  28  26  24  27  29  24  23  24  21  22
-------------------------------------------------------------------------------
Prev Pi:  31  34  33  33  30  35  34  35  36  33  32  32  33  32  33  33  34  30
New Pi:   29  34  33  33  30  34  34  34  36  33  32  32  35  30  33  32  32  30
Diff:     -2   0   0   0   0  -1   0  -1   0   0   0   0   2  -2   0  -1  -2   0

Results for N6.C2.D1.R0: 
           0   1   2   3   4   5   6   7   8   9  10  11  12  13  14  15  16  17
-------------------------------------------------------------------------------
Vref offset: 0
Left:    -24 -23 -24 -23 -25 -27 -25 -26 -25 -26 -25 -24 -24 -27 -25 -25 -26 -24
Right:    20  26  25  23  23  22  22  21  24  22  19  27  25  24  19  23  22  19
-------------------------------------------------------------------------------
Prev Pi:  33  36  35  35  34  36  36  37  37  36  34  33  35  34  35  34  36  34
New Pi:   31  37  35  35  33  34  35  35  37  34  31  34  35  33  32  33  34  32
Diff:     -2   1   0   0  -1  -2  -1  -2   0  -2  -3   1   0  -1  -3  -1  -2  -2

Results for N6.C2.D1.R1: 
           0   1   2   3   4   5   6   7   8   9  10  11  12  13  14  15  16  17
-------------------------------------------------------------------------------
Vref offset: 0
Left:    -25 -22 -24 -23 -26 -26 -25 -26 -25 -26 -24 -24 -23 -27 -25 -25 -26 -24
Right:    19  23  24  24  20  21  23  20  25  23  23  26  25  21  21  24  21  21
-------------------------------------------------------------------------------
Prev Pi:  33  36  35  35  34  36  36  37  37  36  34  33  35  34  35  34  36  34
New Pi:   30  36  35  35  31  34  35  34  37  35  34  34  36  31  33  34  34  33
Diff:     -3   0   0   0  -3  -2  -1  -3   0  -1   0   1   1  -3  -2   0  -2  -1

Results for N6.C3.D0.R0: 
           0   1   2   3   4   5   6   7   8   9  10  11  12  13  14  15  16  17
-------------------------------------------------------------------------------
Vref offset: 0
Left:    -22 -25 -24 -25 -26 -27 -22 -22 -25 -23 -23 -26 -22 -25 -21 -23 -22 -27
Right:    22  26  25  26  27  24  26  30  24  22  23  25  26  25  21  24  25  24
-------------------------------------------------------------------------------
Prev Pi:  31  33  33  32  36  34  33  34  33  34  32  33  34  34  29  31  31  33
New Pi:   31  33  33  32  36  33  35  38  33  34  32  33  36  34  29  31  32  32
Diff:      0   0   0   0   0  -1   2   4   0   0   0   0   2   0   0   0   1  -1

Results for N6.C3.D0.R1: 
           0   1   2   3   4   5   6   7   8   9  10  11  12  13  14  15  16  17
-------------------------------------------------------------------------------
Vref offset: 0
Left:    -22 -25 -24 -24 -27 -26 -22 -23 -25 -23 -23 -27 -23 -25 -22 -23 -20 -27
Right:    22  25  22  27  26  26  25  26  24  23  25  26  25  24  22  20  24  24
-------------------------------------------------------------------------------
Prev Pi:  31  33  33  32  36  34  33  34  33  34  32  33  34  34  29  31  31  33
New Pi:   31  33  32  33  36  34  34  35  33  34  33  33  35  34  29  30  33  32
Diff:      0   0  -1   1   0   0   1   1   0   0   1   0   1   0   0  -1   2  -1

Results for N6.C3.D1.R0: 
           0   1   2   3   4   5   6   7   8   9  10  11  12  13  14  15  16  17
-------------------------------------------------------------------------------
Vref offset: 0
Left:    -22 -24 -23 -24 -24 -25 -21 -22 -25 -22 -23 -25 -21 -24 -22 -24 -19 -27
Right:    20  25  22  24  25  25  23  26  23  21  22  24  26  18  19  19  23  22
-------------------------------------------------------------------------------
Prev Pi:  33  34  34  34  38  35  36  36  35  36  35  34  36  36  31  34  32  36
New Pi:   32  34  34  34  38  35  37  38  34  36  35  34  38  33  30  32  34  34
Diff:     -1   0   0   0   0   0   1   2  -1   0   0   0   2  -3  -1  -2   2  -2

Results for N6.C3.D1.R1: 
           0   1   2   3   4   5   6   7   8   9  10  11  12  13  14  15  16  17
-------------------------------------------------------------------------------
Vref offset: 0
Left:    -22 -24 -24 -25 -24 -25 -21 -22 -25 -22 -23 -25 -23 -25 -21 -23 -19 -27
Right:    18  25  24  25  25  25  24  25  22  22  23  26  24  21  20  19  23  22
-------------------------------------------------------------------------------
Prev Pi:  33  34  34  34  38  35  36  36  35  36  35  34  36  36  31  34  32  36
New Pi:   31  34  34  34  38  35  37  37  34  36  35  34  36  34  31  32  34  34
Diff:     -2   0   0   0   0   0   1   1  -1   0   0   0   0  -2   0  -2   2  -2

STOP_DATA_RX_DQS_ADV
START_DATA_RX_DQS_ADV
Results for N0.C0.D0.R0: 
           0   1   2   3   4   5   6   7   8   9  10  11  12  13  14  15  16  17
-------------------------------------------------------------------------------
Vref offset: 0
Left:    -22 -24 -23 -23 -23 -25 -24 -19 -24 -24 -24 -24 -24 -22 -24 -23 -23 -25
Right:    20  29  31  25  27  30  28  24  26  25  27  26  31  31  31  29  25  23
-------------------------------------------------------------------------------
Prev Pi:  32  33  33  33  34  34  33  34  33  33  33  33  33  34  33  32  32  34
New Pi:   31  35  37  34  36  36  35  36  34  33  34  34  36  38  36  35  33  33
Diff:     -1   2   4   1   2   2   2   2   1   0   1   1   3   4   3   3   1  -1

Results for N0.C0.D0.R1: 
           0   1   2   3   4   5   6   7   8   9  10  11  12  13  14  15  16  17
-------------------------------------------------------------------------------
Vref offset: 0
Left:    -23 -25 -21 -24 -24 -23 -24 -19 -24 -24 -22 -25 -24 -21 -24 -23 -23 -27
Right:    26  28  31  27  28  31  28  25  24  26  29  28  31  26  31  28  25  22
-------------------------------------------------------------------------------
Prev Pi:  32  33  33  33  34  34  33  34  33  33  33  33  33  34  33  32  32  34
New Pi:   33  34  38  34  36  38  35  37  33  34  36  34  36  36  36  34  33  32
Diff:      1   1   5   1   2   4   2   3   0   1   3   1   3   2   3   2   1  -2

Results for N0.C0.D1.R0: 
           0   1   2   3   4   5   6   7   8   9  10  11  12  13  14  15  16  17
-------------------------------------------------------------------------------
Vref offset: 0
Left:    -22 -24 -21 -22 -22 -22 -26 -19 -23 -24 -23 -21 -24 -22 -22 -21 -22 -25
Right:    19  24  31  25  28  30  27  23  19  21  29  27  31  30  31  30  22  21
-------------------------------------------------------------------------------
Prev Pi:  35  35  35  34  35  36  36  36  34  36  35  34  35  36  34  33  34  35
New Pi:   34  35  40  35  38  40  36  38  32  35  38  37  38  40  38  37  34  33
Diff:     -1   0   5   1   3   4   0   2  -2  -1   3   3   3   4   4   4   0  -2

Results for N0.C0.D1.R1: 
           0   1   2   3   4   5   6   7   8   9  10  11  12  13  14  15  16  17
-------------------------------------------------------------------------------
Vref offset: 0
Left:    -22 -25 -21 -24 -22 -21 -24 -18 -22 -25 -22 -22 -23 -20 -22 -21 -21 -26
Right:    22  26  31  30  29  29  28  22  22  21  29  28  31  27  31  31  21  21
-------------------------------------------------------------------------------
Prev Pi:  35  35  35  34  35  36  36  36  34  36  35  34  35  36  34  33  34  35
New Pi:   35  35  40  37  38  40  38  38  34  34  38  37  39  39  38  38  34  33
Diff:      0   0   5   3   3   4   2   2   0  -2   3   3   4   3   4   5   0  -2

Results for N0.C1.D0.R0: 
           0   1   2   3   4   5   6   7   8   9  10  11  12  13  14  15  16  17
-------------------------------------------------------------------------------
Vref offset: 0
Left:    -22 -25 -23 -24 -24 -24 -25 -22 -24 -23 -26 -23 -24 -20 -25 -21 -22 -23
Right:    26  31  30  31  31  31  25  24  24  26  31  28  31  26  27  26  28  28
-------------------------------------------------------------------------------
Prev Pi:  32  34  34  33  32  33  34  33  32  33  34  32  33  32  34  33  32  31
New Pi:   34  37  37  36  35  36  34  34  32  34  36  34  36  35  35  35  35  33
Diff:      2   3   3   3   3   3   0   1   0   1   2   2   3   3   1   2   3   2

Results for N0.C1.D0.R1: 
           0   1   2   3   4   5   6   7   8   9  10  11  12  13  14  15  16  17
-------------------------------------------------------------------------------
Vref offset: 0
Left:    -23 -25 -23 -25 -25 -23 -26 -23 -23 -24 -25 -24 -23 -20 -24 -21 -23 -24
Right:    25  31  26  31  27  28  26  27  26  27  28  29  31  26  28  27  25  26
-------------------------------------------------------------------------------
Prev Pi:  32  34  34  33  32  33  34  33  32  33  34  32  33  32  34  33  32  31
New Pi:   33  37  35  36  33  35  34  35  33  34  35  34  37  35  36  36  33  32
Diff:      1   3   1   3   1   2   0   2   1   1   1   2   4   3   2   3   1   1

Results for N0.C1.D1.R0: 
           0   1   2   3   4   5   6   7   8   9  10  11  12  13  14  15  16  17
-------------------------------------------------------------------------------
Vref offset: 0
Left:    -21 -24 -20 -24 -22 -22 -24 -18 -23 -19 -25 -21 -21 -18 -23 -19 -22 -22
Right:    20  30  26  30  29  26  26  22  22  24  29  28  31  24  28  27  24  25
-------------------------------------------------------------------------------
Prev Pi:  34  35  35  34  34  35  35  34  34  35  36  33  34  34  34  34  34  33
New Pi:   34  38  38  37  37  37  36  36  34  37  38  36  39  37  36  38  35  34
Diff:      0   3   3   3   3   2   1   2   0   2   2   3   5   3   2   4   1   1

Results for N0.C1.D1.R1: 
           0   1   2   3   4   5   6   7   8   9  10  11  12  13  14  15  16  17
-------------------------------------------------------------------------------
Vref offset: 0
Left:    -21 -24 -20 -23 -23 -23 -24 -18 -23 -20 -25 -22 -21 -18 -23 -19 -22 -24
Right:    23  31  26  31  27  25  27  22  24  22  29  27  31  24  30  26  24  26
-------------------------------------------------------------------------------
Prev Pi:  34  35  35  34  34  35  35  34  34  35  36  33  34  34  34  34  34  33
New Pi:   35  38  38  38  36  36  36  36  34  36  38  35  39  37  37  37  35  34
Diff:      1   3   3   4   2   1   1   2   0   1   2   2   5   3   3   3   1   1

Results for N0.C2.D0.R0: 
           0   1   2   3   4   5   6   7   8   9  10  11  12  13  14  15  16  17
-------------------------------------------------------------------------------
Vref offset: 0
Left:    -23 -23 -25 -25 -25 -23 -25 -22 -22 -21 -23 -23 -24 -27 -23 -26 -25 -22
Right:    30  30  28  30  26  27  30  25  31  26  31  26  29  28  30  25  27  31
-------------------------------------------------------------------------------
Prev Pi:  33  35  33  34  33  35  35  34  33  31  33  33  33  33  33  34  33  34
New Pi:   36  38  34  36  33  37  37  35  37  33  37  34  35  33  36  34  34  38
Diff:      3   3   1   2   0   2   2   1   4   2   4   1   2   0   3   0   1   4

Results for N0.C2.D0.R1: 
           0   1   2   3   4   5   6   7   8   9  10  11  12  13  14  15  16  17
-------------------------------------------------------------------------------
Vref offset: 0
Left:    -23 -25 -24 -25 -25 -22 -24 -23 -23 -21 -23 -24 -25 -25 -22 -26 -26 -23
Right:    28  29  25  31  27  25  29  24  31  24  31  25  31  27  27  26  27  31
-------------------------------------------------------------------------------
Prev Pi:  33  35  33  34  33  35  35  34  33  31  33  33  33  33  33  34  33  34
New Pi:   35  37  33  37  34  36  37  34  37  32  37  33  36  34  35  34  33  38
Diff:      2   2   0   3   1   1   2   0   4   1   4   0   3   1   2   0   0   4

Results for N0.C2.D1.R0: 
           0   1   2   3   4   5   6   7   8   9  10  11  12  13  14  15  16  17
-------------------------------------------------------------------------------
Vref offset: 0
Left:    -23 -23 -26 -25 -26 -20 -22 -17 -21 -22 -23 -20 -24 -26 -22 -26 -25 -21
Right:    26  24  22  31  27  26  28  23  30  19  30  24  29  24  25  24  26  29
-------------------------------------------------------------------------------
Prev Pi:  35  37  36  36  36  35  36  35  36  34  35  34  36  35  35  36  35  36
New Pi:   36  37  34  39  36  38  39  38  40  33  38  36  38  34  36  35  35  40
Diff:      1   0  -2   3   0   3   3   3   4  -1   3   2   2  -1   1  -1   0   4

Results for N0.C2.D1.R1: 
           0   1   2   3   4   5   6   7   8   9  10  11  12  13  14  15  16  17
-------------------------------------------------------------------------------
Vref offset: 0
Left:    -22 -24 -25 -26 -26 -19 -22 -18 -22 -22 -22 -21 -24 -25 -21 -26 -26 -22
Right:    26  28  22  30  26  25  27  23  28  24  29  26  29  25  24  23  24  30
-------------------------------------------------------------------------------
Prev Pi:  35  37  36  36  36  35  36  35  36  34  35  34  36  35  35  36  35  36
New Pi:   37  39  35  38  36  38  38  37  39  35  38  36  38  35  36  35  34  40
Diff:      2   2  -1   2   0   3   2   2   3   1   3   2   2   0   1  -1  -1   4

Results for N0.C3.D0.R0: 
           0   1   2   3   4   5   6   7   8   9  10  11  12  13  14  15  16  17
-------------------------------------------------------------------------------
Vref offset: 0
Left:    -22 -23 -25 -24 -24 -25 -25 -22 -23 -26 -22 -22 -26 -23 -23 -25 -25 -23
Right:    21  26  24  27  25  30  27  26  27  26  31  28  28  23  26  24  26  31
-------------------------------------------------------------------------------
Prev Pi:  34  34  33  34  35  34  35  33  32  36  33  32  34  35  33  34  33  33
New Pi:   34  35  33  35  35  36  36  35  34  36  37  35  35  35  34  34  33  37
Diff:      0   1   0   1   0   2   1   2   2   0   4   3   1   0   1   0   0   4

Results for N0.C3.D0.R1: 
           0   1   2   3   4   5   6   7   8   9  10  11  12  13  14  15  16  17
-------------------------------------------------------------------------------
Vref offset: 0
Left:    -24 -22 -26 -24 -25 -25 -24 -23 -22 -26 -21 -22 -25 -23 -23 -24 -25 -24
Right:    26  29  25  29  28  29  26  25  26  23  31  27  30  26  28  23  25  31
-------------------------------------------------------------------------------
Prev Pi:  34  34  33  34  35  34  35  33  32  36  33  32  34  35  33  34  33  33
New Pi:   35  37  33  36  36  36  36  34  34  35  38  34  36  36  35  34  33  36
Diff:      1   3   0   2   1   2   1   1   2  -1   5   2   2   1   2   0   0   3

Results for N0.C3.D1.R0: 
           0   1   2   3   4   5   6   7   8   9  10  11  12  13  14  15  16  17
-------------------------------------------------------------------------------
Vref offset: 0
Left:    -21 -20 -25 -20 -23 -24 -24 -21 -23 -23 -19 -22 -21 -20 -22 -22 -23 -22
Right:    25  30  23  29  27  27  24  24  26  27  31  28  30  25  25  24  26  30
-------------------------------------------------------------------------------
Prev Pi:  36  36  35  36  36  36  36  35  34  38  35  33  34  36  34  34  34  35
New Pi:   38  41  34  40  38  37  36  36  35  40  41  36  38  38  35  35  35  39
Diff:      2   5  -1   4   2   1   0   1   1   2   6   3   4   2   1   1   1   4

Results for N0.C3.D1.R1: 
           0   1   2   3   4   5   6   7   8   9  10  11  12  13  14  15  16  17
-------------------------------------------------------------------------------
Vref offset: 0
Left:    -20 -21 -25 -22 -23 -25 -22 -21 -22 -23 -19 -22 -22 -22 -21 -23 -24 -23
Right:    24  29  23  30  29  29  23  24  26  26  31  30  31  29  26  23  24  30
-------------------------------------------------------------------------------
Prev Pi:  36  36  35  36  36  36  36  35  34  38  35  33  34  36  34  34  34  35
New Pi:   38  40  34  40  39  38  36  36  36  39  41  37  38  39  36  34  34  38
Diff:      2   4  -1   4   3   2   0   1   2   1   6   4   4   3   2   0   0   3

STOP_DATA_RX_DQS_ADV
N2: 
Get Rx Vref margins...
N4: RunTrainStep: Final status = 0
N6: RunTrainStep: Final status = 0
N0: RunTrainStep: Final status = 0
N2: GetMargins: Level = 1, group = 13, mode = 0, scope = 3

END - Rd Timing Centering 2D Training  Time         4984 ms

END - Rd Timing Centering 2D Training  Time         4385 ms

END - Rd Timing Centering 2D Training  Time         4313 ms

START - Wr Timing Centering 2D Training

START - Wr Timing Centering 2D Training

START - Wr Timing Centering 2D Training
N4: 

Adv Strobe Centering(MARGIN_TX_DQ): GetMultiVref: patternLength = 13, stepSize = 1, numPoints = 1
N6: 

Adv Strobe Centering(MARGIN_TX_DQ): GetMultiVref: patternLength = 13, stepSize = 1, numPoints = 1
Checkpoint Code: Socket 0, 0xB7, 0x07, 0x0000
N4: GetMargins: Level = 1, group = 12, mode = 0, scope = 4
N6: GetMargins: Level = 1, group = 12, mode = 0, scope = 4
N0: 

Adv Strobe Centering(MARGIN_TX_DQ): GetMultiVref: patternLength = 13, stepSize = 1, numPoints = 1
N0: GetMargins: Level = 1, group = 12, mode = 0, scope = 4
N2: 
Get Tx Vref margins...
N2: GetMargins: Level = 1, group = 14, mode = 0, scope = 3
START_DATA_TX_DQ_ADV
Results for N4.C0.D0.R0: 
           0   1   2   3   4   5   6   7   8   9  10  11  12  13  14  15  16  17
-------------------------------------------------------------------------------
Vref offset: 0
Left:    -20 -22 -21 -21 -22 -21 -19 -19 -20 -21 -21 -21 -21 -21 -21 -20 -21 -20
Right:    17  16  19  19  17  19  19  16  18  17  18  19  19  20  20  20  20  18
-------------------------------------------------------------------------------
Prev Pi: 470 451 438 421 390 406 407 425 401 469 449 438 423 391 405 409 426 399
New Pi:  469 448 437 420 388 405 407 424 400 467 448 437 422 391 405 409 426 398
Diff:     -1  -3  -1  -1  -2  -1   0  -1  -1  -2  -1  -1  -1   0   0   0   0  -1

Results for N4.C0.D0.R1: 
           0   1   2   3   4   5   6   7   8   9  10  11  12  13  14  15  16  17
-------------------------------------------------------------------------------
Vref offset: 0
Left:    -22 -22 -21 -22 -22 -20 -20 -19 -18 -22 -22 -22 -22 -21 -22 -21 -20 -21
Right:    18  17  19  19  17  19  20  17  18  15  20  19  19  19  19  20  20  18
-------------------------------------------------------------------------------
Prev Pi: 470 451 438 421 390 406 407 425 401 469 449 438 423 391 405 409 426 399
New Pi:  468 449 437 420 388 406 407 424 401 466 448 437 422 390 404 409 426 398
Diff:     -2  -2  -1  -1  -2   0   0  -1   0  -3  -1  -1  -1  -1  -1   0   0  -1

Results for N4.C0.D1.R0: 
           0   1   2   3   4   5   6   7   8   9  10  11  12  13  14  15  16  17
-------------------------------------------------------------------------------
Vref offset: 0
Left:    -19 -18 -20 -19 -21 -21 -18 -16 -20 -21 -19 -19 -20 -20 -20 -19 -18 -17
Right:    17  17  18  16  14  14  18  16  16  16  18  18  18  19  15  18  18  17
-------------------------------------------------------------------------------
Prev Pi: 472 456 443 426 393 412 412 429 401 472 457 441 429 394 413 414 430 399
New Pi:  471 456 442 425 390 409 412 429 399 470 457 441 428 394 411 414 430 399
Diff:     -1   0  -1  -1  -3  -3   0   0  -2  -2   0   0  -1   0  -2   0   0   0

Results for N4.C0.D1.R1: 
           0   1   2   3   4   5   6   7   8   9  10  11  12  13  14  15  16  17
-------------------------------------------------------------------------------
Vref offset: 0
Left:    -21 -20 -20 -19 -20 -20 -17 -16 -19 -22 -21 -19 -22 -19 -21 -19 -17 -18
Right:    16  16  18  19  15  13  17  16  16  16  18  19  17  19  13  18  18  18
-------------------------------------------------------------------------------
Prev Pi: 472 456 443 426 393 412 412 429 401 472 457 441 429 394 413 414 430 399
New Pi:  470 454 442 426 391 409 412 429 400 469 456 441 427 394 409 414 430 399
Diff:     -2  -2  -1   0  -2  -3   0   0  -1  -3  -1   0  -2   0  -4   0   0   0

Results for N4.C1.D0.R0: 
           0   1   2   3   4   5   6   7   8   9  10  11  12  13  14  15  16  17
-------------------------------------------------------------------------------
Vref offset: 0
Left:    -20 -20 -19 -21 -21 -19 -18 -17 -19 -20 -20 -20 -21 -22 -17 -18 -19 -19
Right:    17  18  15  19  17  19  17  18  19  15  19  19  18  19  21  16  19  16
-------------------------------------------------------------------------------
Prev Pi: 471 454 445 431 396 407 424 438 411 469 455 447 432 396 410 426 439 413
New Pi:  470 453 443 430 394 407 424 438 411 467 455 447 431 395 412 425 439 412
Diff:     -1  -1  -2  -1  -2   0   0   0   0  -2   0   0  -1  -1   2  -1   0  -1

Results for N4.C1.D0.R1: 
           0   1   2   3   4   5   6   7   8   9  10  11  12  13  14  15  16  17
-------------------------------------------------------------------------------
Vref offset: 0
Left:    -21 -19 -18 -21 -21 -18 -17 -18 -18 -19 -20 -21 -21 -21 -17 -19 -17 -20
Right:    18  19  18  18  18  19  17  17  18  15  18  18  18  18  19  17  20  18
-------------------------------------------------------------------------------
Prev Pi: 471 454 445 431 396 407 424 438 411 469 455 447 432 396 410 426 439 413
New Pi:  470 454 445 430 395 407 424 438 411 467 454 446 431 395 411 425 440 412
Diff:     -1   0   0  -1  -1   0   0   0   0  -2  -1  -1  -1  -1   1  -1   1  -1

Results for N4.C1.D1.R0: 
           0   1   2   3   4   5   6   7   8   9  10  11  12  13  14  15  16  17
-------------------------------------------------------------------------------
Vref offset: 0
Left:    -17 -16 -19 -18 -18 -17 -16 -16 -17 -19 -18 -19 -22 -20 -16 -15 -15 -20
Right:    16  15  13  14  15  16  15  15  16  13  18  15  14  15  16  16  19  15
-------------------------------------------------------------------------------
Prev Pi: 473 456 446 429 395 410 423 439 409 469 455 445 433 395 409 423 440 407
New Pi:  473 456 443 427 394 410 423 439 409 466 455 443 429 393 409 423 442 405
Diff:      0   0  -3  -2  -1   0   0   0   0  -3   0  -2  -4  -2   0   0   2  -2

Results for N4.C1.D1.R1: 
           0   1   2   3   4   5   6   7   8   9  10  11  12  13  14  15  16  17
-------------------------------------------------------------------------------
Vref offset: 0
Left:    -18 -17 -19 -19 -19 -16 -16 -16 -18 -19 -18 -19 -21 -21 -16 -17 -16 -20
Right:    16  16  13  15  16  16  14  15  16  13  18  16  15  15  17  17  17  15
-------------------------------------------------------------------------------
Prev Pi: 473 456 446 429 395 410 423 439 409 469 455 445 433 395 409 423 440 407
New Pi:  472 456 443 427 394 410 422 439 408 466 455 444 430 392 409 423 440 405
Diff:     -1   0  -3  -2  -1   0  -1   0  -1  -3   0  -1  -3  -3   0   0   0  -2

Results for N4.C2.D0.R0: 
           0   1   2   3   4   5   6   7   8   9  10  11  12  13  14  15  16  17
-------------------------------------------------------------------------------
Vref offset: 0
Left:    -21 -18 -19 -22 -22 -20 -19 -21 -18 -17 -20 -21 -22 -21 -20 -20 -22 -22
Right:    18  19  17  18  18  18  19  18  17  20  17  19  19  19  20  22  19  17
-------------------------------------------------------------------------------
Prev Pi: 461 447 438 420 380 407 406 428 398 462 449 438 423 380 410 409 428 397
New Pi:  460 447 437 418 378 406 406 427 398 463 448 437 422 379 410 410 427 395
Diff:     -1   0  -1  -2  -2  -1   0  -1   0   1  -1  -1  -1  -1   0   1  -1  -2

Results for N4.C2.D0.R1: 
           0   1   2   3   4   5   6   7   8   9  10  11  12  13  14  15  16  17
-------------------------------------------------------------------------------
Vref offset: 0
Left:    -21 -18 -19 -22 -22 -19 -18 -21 -19 -20 -20 -20 -22 -22 -20 -20 -20 -22
Right:    19  18  17  18  18  18  21  18  16  19  18  18  19  19  20  21  19  16
-------------------------------------------------------------------------------
Prev Pi: 461 447 438 420 380 407 406 428 398 462 449 438 423 380 410 409 428 397
New Pi:  460 447 437 418 378 407 407 427 397 462 448 437 422 379 410 409 428 394
Diff:     -1   0  -1  -2  -2   0   1  -1  -1   0  -1  -1  -1  -1   0   0   0  -3

Results for N4.C2.D1.R0: 
           0   1   2   3   4   5   6   7   8   9  10  11  12  13  14  15  16  17
-------------------------------------------------------------------------------
Vref offset: 0
Left:    -19 -19 -20 -19 -21 -19 -21 -18 -20 -21 -19 -21 -19 -20 -21 -17 -18 -17
Right:    15  15  14  17  12  15  14  16  15  13  15  13  18  17  15  19  17  16
-------------------------------------------------------------------------------
Prev Pi: 466 452 442 425 388 415 411 432 400 466 451 443 427 386 414 414 432 399
New Pi:  464 450 439 424 384 413 408 431 398 462 449 439 427 385 411 415 432 399
Diff:     -2  -2  -3  -1  -4  -2  -3  -1  -2  -4  -2  -4   0  -1  -3   1   0   0

Results for N4.C2.D1.R1: 
           0   1   2   3   4   5   6   7   8   9  10  11  12  13  14  15  16  17
-------------------------------------------------------------------------------
Vref offset: 0
Left:    -21 -20 -19 -19 -21 -18 -20 -18 -19 -20 -19 -21 -20 -19 -21 -18 -18 -19
Right:    16  15  14  17  13  16  14  16  14  14  15  13  17  18  16  20  17  15
-------------------------------------------------------------------------------
Prev Pi: 466 452 442 425 388 415 411 432 400 466 451 443 427 386 414 414 432 399
New Pi:  464 450 440 424 384 414 408 431 398 463 449 439 426 386 412 415 432 397
Diff:     -2  -2  -2  -1  -4  -1  -3  -1  -2  -3  -2  -4  -1   0  -2   1   0  -2

Results for N4.C3.D0.R0: 
           0   1   2   3   4   5   6   7   8   9  10  11  12  13  14  15  16  17
-------------------------------------------------------------------------------
Vref offset: 0
Left:    -20 -20 -20 -22 -21 -16 -19 -16 -21 -19 -20 -21 -20 -21 -19 -19 -18 -22
Right:    21  21  19  20  17  21  17  20  18  19  19  18  19  19  20  17  20  18
-------------------------------------------------------------------------------
Prev Pi: 475 457 447 433 395 408 423 441 414 472 458 447 434 396 410 427 441 413
New Pi:  475 457 447 432 393 410 422 443 413 472 458 446 434 395 410 426 442 411
Diff:      0   0   0  -1  -2   2  -1   2  -1   0   0  -1   0  -1   0  -1   1  -2

Results for N4.C3.D0.R1: 
           0   1   2   3   4   5   6   7   8   9  10  11  12  13  14  15  16  17
-------------------------------------------------------------------------------
Vref offset: 0
Left:    -20 -19 -19 -21 -21 -16 -18 -17 -21 -20 -20 -21 -21 -20 -17 -19 -17 -23
Right:    19  21  18  19  17  21  18  19  19  20  20  16  19  19  19  18  22  18
-------------------------------------------------------------------------------
Prev Pi: 475 457 447 433 395 408 423 441 414 472 458 447 434 396 410 427 441 413
New Pi:  475 458 447 432 393 410 423 442 413 472 458 445 433 396 411 427 443 411
Diff:      0   1   0  -1  -2   2   0   1  -1   0   0  -2  -1   0   1   0   2  -2

Results for N4.C3.D1.R0: 
           0   1   2   3   4   5   6   7   8   9  10  11  12  13  14  15  16  17
-------------------------------------------------------------------------------
Vref offset: 0
Left:    -17 -20 -20 -19 -19 -17 -16 -16 -17 -18 -18 -19 -18 -18 -17 -16 -18 -19
Right:    16  17  15  17  14  16  15  15  16  16  17  16  16  18  16  16  17  16
-------------------------------------------------------------------------------
Prev Pi: 480 465 454 438 401 416 430 448 417 476 465 452 441 402 418 432 449 417
New Pi:  480 464 452 437 399 416 430 448 417 475 465 451 440 402 418 432 449 416
Diff:      0  -1  -2  -1  -2   0   0   0   0  -1   0  -1  -1   0   0   0   0  -1

Results for N4.C3.D1.R1: 
           0   1   2   3   4   5   6   7   8   9  10  11  12  13  14  15  16  17
-------------------------------------------------------------------------------
Vref offset: 0
Left:    -20 -19 -19 -19 -19 -16 -16 -17 -18 -17 -20 -20 -19 -19 -17 -17 -17 -19
Right:    17  17  16  17  15  17  14  17  15  17  17  15  15  17  16  17  18  16
-------------------------------------------------------------------------------
Prev Pi: 480 465 454 438 401 416 430 448 417 476 465 452 441 402 418 432 449 417
New Pi:  479 464 453 437 399 416 429 448 416 476 464 450 439 401 418 432 449 416
Diff:     -1  -1  -1  -1  -2   0  -1   0  -1   0  -1  -2  -2  -1   0   0   0  -1

STOP_DATA_TX_DQ_ADV
START_DATA_TX_DQ_ADV
Results for N6.C0.D0.R0: 
           0   1   2   3   4   5   6   7   8   9  10  11  12  13  14  15  16  17
-------------------------------------------------------------------------------
Vref offset: 0
Left:    -25 -26 -22 -25 -26 -24 -25 -21 -25 -23 -25 -24 -25 -26 -24 -23 -23 -24
Right:    26  26  27  27  25  25  24  27  24  25  26  26  27  24  24  28  27  24
-------------------------------------------------------------------------------
Prev Pi: 470 446 435 418 386 404 410 424 399 466 446 436 420 387 404 406 423 399
New Pi:  470 446 437 419 386 404 410 427 399 467 446 437 421 386 404 408 425 399
Diff:      0   0   2   1   0   0   0   3   0   1   0   1   1  -1   0   2   2   0

Results for N6.C0.D0.R1: 
           0   1   2   3   4   5   6   7   8   9  10  11  12  13  14  15  16  17
-------------------------------------------------------------------------------
Vref offset: 0
Left:    -25 -25 -23 -23 -25 -24 -23 -22 -25 -25 -25 -23 -24 -26 -25 -24 -21 -25
Right:    26  26  26  26  23  26  23  27  24  25  26  26  26  24  24  28  26  25
-------------------------------------------------------------------------------
Prev Pi: 470 446 435 418 386 404 410 424 399 466 446 436 420 387 404 406 423 399
New Pi:  470 446 436 419 385 405 410 426 399 466 446 437 421 386 404 408 425 399
Diff:      0   0   1   1  -1   1   0   2   0   0   0   1   1  -1   0   2   2   0

Results for N6.C0.D1.R0: 
           0   1   2   3   4   5   6   7   8   9  10  11  12  13  14  15  16  17
-------------------------------------------------------------------------------
Vref offset: 0
Left:    -24 -26 -24 -23 -24 -23 -23 -21 -22 -22 -25 -21 -24 -25 -23 -22 -20 -23
Right:    25  26  20  25  20  23  23  24  23  24  23  26  24  24  23  23  24  24
-------------------------------------------------------------------------------
Prev Pi: 469 449 436 423 387 406 410 425 396 467 450 436 422 387 406 409 425 395
New Pi:  469 449 434 424 385 406 410 426 396 468 449 438 422 387 406 409 427 395
Diff:      0   0  -2   1  -2   0   0   1   0   1  -1   2   0   0   0   0   2   0

Results for N6.C0.D1.R1: 
           0   1   2   3   4   5   6   7   8   9  10  11  12  13  14  15  16  17
-------------------------------------------------------------------------------
Vref offset: 0
Left:    -25 -24 -24 -23 -24 -23 -23 -21 -23 -24 -25 -23 -24 -24 -24 -24 -20 -23
Right:    25  25  20  25  21  22  22  22  21  24  25  26  24  25  23  25  23  25
-------------------------------------------------------------------------------
Prev Pi: 469 449 436 423 387 406 410 425 396 467 450 436 422 387 406 409 425 395
New Pi:  469 449 434 424 386 406 410 425 395 467 450 437 422 387 406 409 426 396
Diff:      0   0  -2   1  -1   0   0   0  -1   0   0   1   0   0   0   0   1   1

Results for N6.C1.D0.R0: 
           0   1   2   3   4   5   6   7   8   9  10  11  12  13  14  15  16  17
-------------------------------------------------------------------------------
Vref offset: 0
Left:    -23 -24 -24 -25 -24 -24 -23 -21 -24 -24 -24 -23 -24 -24 -21 -22 -21 -23
Right:    25  26  24  25  26  23  20  27  25  24  25  26  25  26  28  25  26  28
-------------------------------------------------------------------------------
Prev Pi: 466 449 440 424 392 404 421 434 408 465 449 441 425 392 403 421 436 405
New Pi:  467 450 440 424 393 404 420 437 408 465 449 442 425 393 406 422 438 407
Diff:      1   1   0   0   1   0  -1   3   0   0   0   1   0   1   3   1   2   2

Results for N6.C1.D0.R1: 
           0   1   2   3   4   5   6   7   8   9  10  11  12  13  14  15  16  17
-------------------------------------------------------------------------------
Vref offset: 0
Left:    -23 -23 -24 -24 -24 -22 -22 -22 -25 -24 -25 -23 -24 -25 -23 -23 -21 -24
Right:    24  25  23  24  26  27  21  25  25  23  25  26  25  27  28  25  24  29
-------------------------------------------------------------------------------
Prev Pi: 466 449 440 424 392 404 421 434 408 465 449 441 425 392 403 421 436 405
New Pi:  466 450 440 424 393 406 421 435 408 465 449 442 425 393 405 422 437 407
Diff:      0   1   0   0   1   2   0   1   0   0   0   1   0   1   2   1   1   2

Results for N6.C1.D1.R0: 
           0   1   2   3   4   5   6   7   8   9  10  11  12  13  14  15  16  17
-------------------------------------------------------------------------------
Vref offset: 0
Left:    -22 -22 -22 -22 -23 -20 -20 -19 -21 -21 -21 -22 -22 -24 -20 -20 -19 -22
Right:    23  24  22  22  24  23  19  23  25  22  25  22  21  24  23  24  23  25
-------------------------------------------------------------------------------
Prev Pi: 472 454 445 429 396 411 424 442 410 469 455 446 432 399 412 423 444 409
New Pi:  472 455 445 429 396 412 424 444 412 469 457 446 432 399 413 425 446 410
Diff:      0   1   0   0   0   1   0   2   2   0   2   0   0   0   1   2   2   1

Results for N6.C1.D1.R1: 
           0   1   2   3   4   5   6   7   8   9  10  11  12  13  14  15  16  17
-------------------------------------------------------------------------------
Vref offset: 0
Left:    -22 -21 -21 -20 -21 -20 -19 -21 -22 -22 -21 -23 -22 -24 -20 -21 -20 -23
Right:    23  23  20  22  24  24  20  22  24  22  26  22  23  24  23  24  24  25
-------------------------------------------------------------------------------
Prev Pi: 472 454 445 429 396 411 424 442 410 469 455 446 432 399 412 423 444 409
New Pi:  472 455 445 430 397 413 424 442 411 469 457 446 432 399 413 424 446 410
Diff:      0   1   0   1   1   2   0   0   1   0   2   0   0   0   1   1   2   1

Results for N6.C2.D0.R0: 
           0   1   2   3   4   5   6   7   8   9  10  11  12  13  14  15  16  17
-------------------------------------------------------------------------------
Vref offset: 0
Left:    -24 -25 -21 -25 -26 -25 -25 -21 -23 -23 -27 -23 -25 -26 -25 -24 -20 -24
Right:    28  24  27  25  28  24  23  27  24  26  24  25  25  27  24  25  29  23
-------------------------------------------------------------------------------
Prev Pi: 459 444 437 416 378 406 407 425 395 458 445 438 417 378 406 407 426 394
New Pi:  461 444 440 416 379 406 406 428 395 459 444 439 417 378 406 407 430 394
Diff:      2   0   3   0   1   0  -1   3   0   1  -1   1   0   0   0   0   4   0

Results for N6.C2.D0.R1: 
           0   1   2   3   4   5   6   7   8   9  10  11  12  13  14  15  16  17
-------------------------------------------------------------------------------
Vref offset: 0
Left:    -23 -23 -22 -25 -24 -24 -25 -23 -23 -23 -27 -23 -25 -25 -25 -25 -20 -25
Right:    28  25  27  25  26  24  23  26  23  27  25  26  26  28  24  25  29  24
-------------------------------------------------------------------------------
Prev Pi: 459 444 437 416 378 406 407 425 395 458 445 438 417 378 406 407 426 394
New Pi:  461 445 439 416 379 406 406 426 395 460 444 439 417 379 406 407 430 394
Diff:      2   1   2   0   1   0  -1   1   0   2  -1   1   0   1   0   0   4   0

Results for N6.C2.D1.R0: 
           0   1   2   3   4   5   6   7   8   9  10  11  12  13  14  15  16  17
-------------------------------------------------------------------------------
Vref offset: 0
Left:    -25 -22 -24 -25 -23 -24 -23 -21 -23 -24 -24 -24 -23 -23 -24 -20 -20 -23
Right:    24  22  19  23  23  20  21  24  23  24  21  19  21  25  21  25  25  24
-------------------------------------------------------------------------------
Prev Pi: 468 452 447 428 387 418 414 437 401 465 452 447 429 387 415 414 436 400
New Pi:  468 452 445 427 387 416 413 438 401 465 451 445 428 388 414 416 438 400
Diff:      0   0  -2  -1   0  -2  -1   1   0   0  -1  -2  -1   1  -1   2   2   0

Results for N6.C2.D1.R1: 
           0   1   2   3   4   5   6   7   8   9  10  11  12  13  14  15  16  17
-------------------------------------------------------------------------------
Vref offset: 0
Left:    -25 -21 -24 -21 -21 -24 -23 -22 -22 -24 -23 -24 -23 -24 -24 -22 -21 -24
Right:    23  22  18  22  23  20  20  22  23  24  22  18  20  26  22  26  25  25
-------------------------------------------------------------------------------
Prev Pi: 468 452 447 428 387 418 414 437 401 465 452 447 429 387 415 414 436 400
New Pi:  467 452 444 428 388 416 413 437 401 465 452 444 428 388 414 416 438 400
Diff:     -1   0  -3   0   1  -2  -1   0   0   0   0  -3  -1   1  -1   2   2   0

Results for N6.C3.D0.R0: 
           0   1   2   3   4   5   6   7   8   9  10  11  12  13  14  15  16  17
-------------------------------------------------------------------------------
Vref offset: 0
Left:    -25 -24 -22 -23 -23 -23 -24 -21 -23 -23 -23 -22 -24 -23 -22 -21 -24 -24
Right:    26  28  25  27  26  25  22  25  26  28  26  26  26  26  26  25  24  26
-------------------------------------------------------------------------------
Prev Pi: 471 454 446 428 391 407 423 437 410 468 455 445 429 392 408 422 440 409
New Pi:  471 456 447 430 392 408 422 439 411 470 456 447 430 393 410 424 440 410
Diff:      0   2   1   2   1   1  -1   2   1   2   1   2   1   1   2   2   0   1

Results for N6.C3.D0.R1: 
           0   1   2   3   4   5   6   7   8   9  10  11  12  13  14  15  16  17
-------------------------------------------------------------------------------
Vref offset: 0
Left:    -24 -23 -21 -23 -22 -23 -23 -24 -23 -24 -24 -23 -23 -24 -23 -23 -24 -25
Right:    26  27  24  28  27  26  22  26  25  27  26  27  26  26  26  25  24  25
-------------------------------------------------------------------------------
Prev Pi: 471 454 446 428 391 407 423 437 410 468 455 445 429 392 408 422 440 409
New Pi:  472 456 447 430 393 408 423 438 411 469 456 447 430 393 409 423 440 409
Diff:      1   2   1   2   2   1   0   1   1   1   1   2   1   1   1   1   0   0

Results for N6.C3.D1.R0: 
           0   1   2   3   4   5   6   7   8   9  10  11  12  13  14  15  16  17
-------------------------------------------------------------------------------
Vref offset: 0
Left:    -21 -23 -23 -24 -23 -21 -21 -20 -23 -20 -20 -22 -23 -21 -20 -19 -22 -23
Right:    23  24  22  22  23  24  21  24  22  25  25  23  22  24  24  25  24  25
-------------------------------------------------------------------------------
Prev Pi: 479 461 449 436 399 413 428 444 415 475 460 452 437 399 416 427 446 414
New Pi:  480 461 449 435 399 414 428 446 415 477 462 452 437 400 418 430 447 415
Diff:      1   0   0  -1   0   1   0   2   0   2   2   0   0   1   2   3   1   1

Results for N6.C3.D1.R1: 
           0   1   2   3   4   5   6   7   8   9  10  11  12  13  14  15  16  17
-------------------------------------------------------------------------------
Vref offset: 0
Left:    -22 -21 -22 -22 -21 -20 -19 -21 -22 -20 -22 -23 -22 -23 -21 -20 -22 -23
Right:    23  24  22  23  24  24  20  23  20  24  26  23  22  25  24  26  25  26
-------------------------------------------------------------------------------
Prev Pi: 479 461 449 436 399 413 428 444 415 475 460 452 437 399 416 427 446 414
New Pi:  479 462 449 436 400 415 428 445 414 477 462 452 437 400 417 430 447 415
Diff:      0   1   0   0   1   2   0   1  -1   2   2   0   0   1   1   3   1   1

STOP_DATA_TX_DQ_ADV
START_DATA_TX_DQ_ADV
Results for N0.C0.D0.R0: 
           0   1   2   3   4   5   6   7   8   9  10  11  12  13  14  15  16  17
-------------------------------------------------------------------------------
Vref offset: 0
Left:    -24 -27 -25 -26 -28 -26 -24 -22 -27 -25 -26 -25 -25 -28 -24 -24 -24 -27
Right:    22  22  24  24  24  23  25  25  22  22  25  26  25  23  26  24  27  21
-------------------------------------------------------------------------------
Prev Pi: 468 450 438 421 390 404 408 424 399 468 450 438 423 391 406 408 426 396
New Pi:  467 448 438 420 388 403 408 425 397 467 450 438 423 389 407 408 427 393
Diff:     -1  -2   0  -1  -2  -1   0   1  -2  -1   0   0   0  -2   1   0   1  -3

Results for N0.C0.D0.R1: 
           0   1   2   3   4   5   6   7   8   9  10  11  12  13  14  15  16  17
-------------------------------------------------------------------------------
Vref offset: 0
Left:    -27 -27 -25 -26 -26 -25 -24 -22 -26 -26 -28 -25 -26 -28 -24 -25 -23 -27
Right:    21  23  24  24  23  22  25  25  21  21  27  25  25  24  26  26  27  22
-------------------------------------------------------------------------------
Prev Pi: 468 450 438 421 390 404 408 424 399 468 450 438 423 391 406 408 426 396
New Pi:  465 448 438 420 389 403 408 425 397 466 450 438 423 389 407 408 428 394
Diff:     -3  -2   0  -1  -1  -1   0   1  -2  -2   0   0   0  -2   1   0   2  -2

Results for N0.C0.D1.R0: 
           0   1   2   3   4   5   6   7   8   9  10  11  12  13  14  15  16  17
-------------------------------------------------------------------------------
Vref offset: 0
Left:    -26 -26 -26 -27 -28 -24 -23 -22 -25 -24 -27 -27 -27 -27 -23 -23 -23 -26
Right:    21  21  20  20  19  19  24  21  22  22  22  21  22  22  21  24  24  22
-------------------------------------------------------------------------------
Prev Pi: 474 457 443 428 395 413 414 432 401 472 457 443 431 396 412 415 432 401
New Pi:  472 455 440 425 391 411 414 432 400 471 455 440 429 394 411 415 432 399
Diff:     -2  -2  -3  -3  -4  -2   0   0  -1  -1  -2  -3  -2  -2  -1   0   0  -2

Results for N0.C0.D1.R1: 
           0   1   2   3   4   5   6   7   8   9  10  11  12  13  14  15  16  17
-------------------------------------------------------------------------------
Vref offset: 0
Left:    -27 -26 -25 -26 -28 -25 -23 -23 -24 -26 -26 -28 -26 -27 -26 -24 -23 -26
Right:    21  21  21  22  20  20  24  20  21  23  22  21  22  21  22  25  24  22
-------------------------------------------------------------------------------
Prev Pi: 474 457 443 428 395 413 414 432 401 472 457 443 431 396 412 415 432 401
New Pi:  471 455 441 426 391 411 414 431 400 471 455 440 429 393 410 415 432 399
Diff:     -3  -2  -2  -2  -4  -2   0  -1  -1  -1  -2  -3  -2  -3  -2   0   0  -2

Results for N0.C1.D0.R0: 
           0   1   2   3   4   5   6   7   8   9  10  11  12  13  14  15  16  17
-------------------------------------------------------------------------------
Vref offset: 0
Left:    -24 -25 -25 -26 -26 -24 -23 -25 -25 -23 -26 -26 -24 -25 -23 -24 -24 -28
Right:    24  25  25  24  25  25  25  22  25  24  27  26  25  26  26  24  26  23
-------------------------------------------------------------------------------
Prev Pi: 470 450 443 427 392 406 423 439 407 467 451 445 428 393 407 422 439 410
New Pi:  470 450 443 426 392 406 424 438 407 467 451 445 428 393 408 422 440 408
Diff:      0   0   0  -1   0   0   1  -1   0   0   0   0   0   0   1   0   1  -2

Results for N0.C1.D0.R1: 
           0   1   2   3   4   5   6   7   8   9  10  11  12  13  14  15  16  17
-------------------------------------------------------------------------------
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Results for N0.C1.D1.R0: 
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-------------------------------------------------------------------------------
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Results for N0.C1.D1.R1: 
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-------------------------------------------------------------------------------
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Results for N0.C2.D0.R0: 
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Results for N0.C2.D0.R1: 
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Results for N0.C2.D1.R0: 
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Results for N0.C2.D1.R1: 
           0   1   2   3   4   5   6   7   8   9  10  11  12  13  14  15  16  17
-------------------------------------------------------------------------------
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Diff:     -2   0  -3  -2  -3  -3   1  -1  -1  -1   0  -3  -1  -1  -2   1  -1  -2

Results for N0.C3.D0.R0: 
           0   1   2   3   4   5   6   7   8   9  10  11  12  13  14  15  16  17
-------------------------------------------------------------------------------
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Left:    -24 -24 -26 -23 -25 -24 -24 -23 -27 -24 -24 -24 -26 -23 -24 -24 -24 -25
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Results for N0.C3.D0.R1: 
           0   1   2   3   4   5   6   7   8   9  10  11  12  13  14  15  16  17
-------------------------------------------------------------------------------
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Left:    -25 -25 -26 -24 -25 -24 -22 -24 -26 -24 -24 -26 -26 -24 -25 -23 -24 -26
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Results for N0.C3.D1.R0: 
           0   1   2   3   4   5   6   7   8   9  10  11  12  13  14  15  16  17
-------------------------------------------------------------------------------
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Results for N0.C3.D1.R1: 
           0   1   2   3   4   5   6   7   8   9  10  11  12  13  14  15  16  17
-------------------------------------------------------------------------------
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Left:    -25 -24 -25 -26 -25 -22 -24 -23 -25 -22 -24 -26 -26 -26 -23 -21 -24 -26
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Diff:     -2   0  -2  -2  -2   0  -1  -1  -1  -1   0  -2  -3  -1   0   0   0  -2

STOP_DATA_TX_DQ_ADV
N2: 
 Time to do RMT patterns 15  is 8 seconds 
N4: RunTrainStep: Final status = 0
N6: RunTrainStep: Final status = 0
N0: RunTrainStep: Final status = 0

            RxDqLeft RxDqRight RxVLow RxVHigh TxDqLeft TxDqRight TxVLow TxVHigh
--------------------------------------------------------------------------------
N2.C0.D0.R0:   -21       20       -25       30      -22     22      -30      31
N2.C0.D0.R1:   -20       18       -25       30      -22     22      -28      31
N2.C0.D1.R0:   -20       19       -26       31      -22     22      -30      31
N2.C0.D1.R1:   -19       19       -27       31      -20     21      -29      31
N2.C1.D0.R0:   -20       20       -27       48      -22     24      -28      31
N2.C1.D0.R1:   -21       20       -27       48      -21     23      -27      31
N2.C1.D1.R0:   -20       19       -26       32      -20     21      -29      31
N2.C1.D1.R1:   -19       19       -26       32      -20     20      -28      31
N2.C2.D0.R0:   -23       23       -25       48      -23     23      -30      31
N2.C2.D0.R1:   -23       22       -25       48      -23     23      -30      31
N2.C2.D1.R0:   -21       21       -25       48      -20     21      -28      31
N2.C2.D1.R1:   -21       22       -25       48      -20     21      -28      31
N2.C3.D0.R0:   -22       21       -25       48      -22     23      -28      31
N2.C3.D0.R1:   -23       22       -25       48      -21     23      -28      31
N2.C3.D1.R0:   -21       21       -26       31      -19     21      -28      31
N2.C3.D1.R1:   -21       22       -26       40      -20     21      -27      31
STOP_RMT_N2

END - Wr Timing Centering 2D Training  Time         10296 ms

END - Wr Timing Centering 2D Training  Time         10295 ms

END - Wr Timing Centering 2D Training  Time         10294 ms
N2: GetAllRankMargins time            16718 ms

START - Rd Voltage Training

START - Rd Voltage Training

START - Rd Voltage Training
N2: 
Total DDR trainings latency = 200297 ms
N4: RX Vref Training...
N6: RX Vref Training...
Checkpoint Code: Socket 0, 0xB7, 0x0A, 0x0000
N3: PostVmseTraining
N4: GetMargins: Level = 1, group = 13, mode = 2, scope = 4
N6: GetMargins: Level = 1, group = 13, mode = 2, scope = 4
N0: RX Vref Training...
N3.C0: PostVmseTraining
N0: GetMargins: Level = 1, group = 13, mode = 2, scope = 4
N3.C0: PostVMSE Training VMSE Health Check Passed
N3.C1: PostVmseTraining
N3.C2: PostVMSE Training VMSE Health Check Passed
N3: PreDdrTraining
N3: PreDdrTraining[QCRM=OFF]
N3.C0.D0: CheckRankPopLocal: dimmPresent: 1, numRanks = 2
N3.C0.D0.R0: CheckRankPopLocal: mapOut: 0, enabled = 1
N3.C0.D0.R1: CheckRankPopLocal: mapOut: 0, enabled = 1
N3.C0.D1: CheckRankPopLocal: dimmPresent: 0, numRanks = 0
N3.C0.D2: CheckRankPopLocal: dimmPresent: 0, numRanks = 0
N3.C0.D0: CheckRankPopLocal: amap: 0x00000000
N3.C0.D1: CheckRankPopLocal: amap: 0x00000000
N3.C0.D2: CheckRankPopLocal: amap: 0x00000000
N3.C1.D0: CheckRankPopLocal: dimmPresent: 1, numRanks = 2
N3.C1.D0.R0: CheckRankPopLocal: mapOut: 0, enabled = 1
N3.C1.D0.R1: CheckRankPopLocal: mapOut: 0, enabled = 1
N3.C1.D1: CheckRankPopLocal: dimmPresent: 0, numRanks = 0
N3.C1.D2: CheckRankPopLocal: dimmPresent: 0, numRanks = 0
N3.C1.D0: CheckRankPopLocal: amap: 0x00000000
N3.C1.D1: CheckRankPopLocal: amap: 0x00000000
N3.C1.D2: CheckRankPopLocal: amap: 0x00000000
N3.C2.D0: CheckRankPopLocal: dimmPresent: 1, numRanks = 2
N3.C2.D0.R0: CheckRankPopLocal: mapOut: 0, enabled = 1
N3.C2.D0.R1: CheckRankPopLocal: mapOut: 0, enabled = 1
N3.C2.D1: CheckRankPopLocal: dimmPresent: 0, numRanks = 0
N3.C2.D2: CheckRankPopLocal: dimmPresent: 0, numRanks = 0
N3.C2.D0: CheckRankPopLocal: amap: 0x00000000
N3.C2.D1: CheckRankPopLocal: amap: 0x00000000
N3.C2.D2: CheckRankPopLocal: amap: 0x00000000
N3.C3.D0: CheckRankPopLocal: dimmPresent: 1, numRanks = 2
N3.C3.D0.R0: CheckRankPopLocal: mapOut: 0, enabled = 1
N3.C3.D0.R1: CheckRankPopLocal: mapOut: 0, enabled = 1
N3.C3.D1: CheckRankPopLocal: dimmPresent: 0, numRanks = 0
N3.C3.D2: CheckRankPopLocal: dimmPresent: 0, numRanks = 0
N3.C3.D0: CheckRankPopLocal: amap: 0x00000000
N3.C3.D1: CheckRankPopLocal: amap: 0x00000000
N3.C3.D2: CheckRankPopLocal: amap: 0x00000000
N3.C0: JCK cmd timing = 3N
N3.C0: RdCmd2DataValidLatency = 20, (dlyFrmS = 15, clEff = 10, earlyCas = 0, selNTiming = 2)
N3.C0: CLK0_CFG: 0x000FFF10
N3.C0: DDR_RANKCTL: 0x000FEE40
N3.C0: MCODT = 0 ( 50 ohms)
N3.C0.D0.R0: Rtt_wr = 0, Rtt_nom = 60
N3.C0.D0.R1: Rtt_wr = 0, Rtt_nom = 60
N3.C0: ODTRDCTL00 = 0x00000000
N3.C0: ODTRDCTL01 = 0x00000000
N3.C0: ODTWRCTL00 = 0x00000081
N3.C0: ODTWRCTL01 = 0x00000000
N3.C1: RdCmd2DataValidLatency = 20, (dlyFrmS = 15, clEff = 10, earlyCas = 0, selNTiming = 2)
N3.C1: CLK0_CFG: 0x000FF110
N3.C1: DDR_RANKCTL: 0x000FEE40
N3.C1: MCODT = 0 ( 50 ohms)
N3.C1.D0.R0: Rtt_wr = 0, Rtt_nom = 60
N3.C1.D0.R1: Rtt_wr = 0, Rtt_nom = 60
N3.C1: ODTRDCTL00 = 0x00000000
N3.C1: ODTRDCTL01 = 0x00000000
N3.C1: ODTWRCTL00 = 0x00000081
N3.C1: ODTWRCTL01 = 0x00000000
N3.C2: JCK cmd timing = 3N
N3.C2: RdCmd2DataValidLatency = 20, (dlyFrmS = 15, clEff = 10, earlyCas = 0, selNTiming = 2)
N3.C2: CLK0_CFG: 0x000FFF10
N3.C2: DDR_RANKCTL: 0x000FEE40
N3.C2: MCODT = 0 ( 50 ohms)
N3.C2.D0.R0: Rtt_wr = 0, Rtt_nom = 60
N3.C2.D0.R1: Rtt_wr = 0, Rtt_nom = 60
N3.C2: ODTRDCTL00 = 0x00000000
N3.C2: ODTRDCTL01 = 0x00000000
N3.C2: ODTWRCTL00 = 0x00000081
N3.C2: ODTWRCTL01 = 0x00000000
N3.C3: RdCmd2DataValidLatency = 20, (dlyFrmS = 15, clEff = 10, earlyCas = 0, selNTiming = 2)
N3.C3: CLK0_CFG: 0x000FF110
N3.C3: DDR_RANKCTL: 0x000FEE40
N3.C3: MCODT = 0 ( 50 ohms)
N3.C3.D0.R0: Rtt_wr = 0, Rtt_nom = 60
N3.C3.D0.R1: Rtt_wr = 0, Rtt_nom = 60
N3.C3: ODTRDCTL00 = 0x00000000
N3.C3: ODTRDCTL01 = 0x00000000
N3.C3: ODTWRCTL00 = 0x00000081
N3.C3: ODTWRCTL01 = 0x00000000
N3.C0.D0: PreDdrTraining: Program dimmmtr 0xC5051
N3.C1.D0: PreDdrTraining: Program dimmmtr 0xC5051
N3.C2.D0: PreDdrTraining: Program dimmmtr 0xC5051
N3.C3.D0: PreDdrTraining: Program dimmmtr 0xC5051
N3: InitializeDdrioForUse
N3: SetupJckForBL: setting BL to 8
N3.C0: ODTTIMCTL (INIT RELAX) rdwidth = 10 rddly = 0 wrwidth = 8 wrdly = 0
N3.C1: ODTTIMCTL (INIT RELAX) rdwidth = 10 rddly = 0 wrwidth = 8 wrdly = 0
N3.C2: ODTTIMCTL (INIT RELAX) rdwidth = 10 rddly = 0 wrwidth = 8 wrdly = 0
N3.C3: ODTTIMCTL (INIT RELAX) rdwidth = 10 rddly = 0 wrwidth = 8 wrdly = 0
N3: JckDdrTraining
N3: InitializeDdrioForTraining: QCRM Disabled
N3.C0: InitializeDdrioForTraining: cleff = 10
N3.C0: InitializeDdrioForTraining: cwleff = 8
N3.C0: InitializeDdrioForTraining: initial ddrInitIndexRx = 4 ddrInitIndexTx = 2
N3.C0: InitializeDdrioForTraining: initial RdCmd2RcvEnLatency = 5
N3.C0: InitializeDdrioForTraining: initial RdPtrOffsetRcvEn = 4
N3.C0: InitializeDdrioForTraining: initial rkrdptroffsetrcvenb = 6
N3.C0: InitializeDdrioForTraining: initial rkrdptroffsetdrvenrcvenb = 5
N3.C0: InitializeDdrioForTraining: initial WrCmd2DqsStartLatency = 4
N3.C0: InitializeDdrioForTraining: initial RdPtrOffsetDqs = 10
N3.C0: InitializeDdrioForTraining: initial RdCmd2RcvEnLatency = 5
N3.C0: InitializeDdrioForTraining: initial WrCmd2DqsStartLatency = 4
N3.C0: InitializeDdrioForTraining: initial RdPtrOffsetRcvEn = 4
N3.C0: InitializeDdrioForTraining: initial RdPtrOffsetDqs = 6
N3.C0: InitializeDdrioForTraining: initial RdPtrOffsetDq = 5
N3.C1: InitializeDdrioForTraining: cleff = 10
N3.C1: InitializeDdrioForTraining: cwleff = 8
N3.C1: InitializeDdrioForTraining: initial ddrInitIndexRx = 4 ddrInitIndexTx = 2
N3.C1: InitializeDdrioForTraining: initial RdCmd2RcvEnLatency = 5
N3.C1: InitializeDdrioForTraining: initial RdPtrOffsetRcvEn = 4
N3.C1: InitializeDdrioForTraining: initial rkrdptroffsetrcvenb = 6
N3.C1: InitializeDdrioForTraining: initial rkrdptroffsetdrvenrcvenb = 5
N3.C1: InitializeDdrioForTraining: initial WrCmd2DqsStartLatency = 4
N3.C1: InitializeDdrioForTraining: initial RdPtrOffsetDqs = 10
N3.C1: InitializeDdrioForTraining: initial RdCmd2RcvEnLatency = 5
N3.C1: InitializeDdrioForTraining: initial WrCmd2DqsStartLatency = 4
N3.C1: InitializeDdrioForTraining: initial RdPtrOffsetRcvEn = 4
N3.C1: InitializeDdrioForTraining: initial RdPtrOffsetDqs = 6
N3.C1: InitializeDdrioForTraining: initial RdPtrOffsetDq = 5
N3.C2: InitializeDdrioForTraining: cleff = 10
N3.C2: InitializeDdrioForTraining: cwleff = 8
N3.C2: InitializeDdrioForTraining: initial ddrInitIndexRx = 4 ddrInitIndexTx = 2
N3.C2: InitializeDdrioForTraining: initial RdCmd2RcvEnLatency = 5
N3.C2: InitializeDdrioForTraining: initial RdPtrOffsetRcvEn = 4
N3.C2: InitializeDdrioForTraining: initial rkrdptroffsetrcvenb = 6
N3.C2: InitializeDdrioForTraining: initial rkrdptroffsetdrvenrcvenb = 5
N3.C2: InitializeDdrioForTraining: initial WrCmd2DqsStartLatency = 4
N3.C2: InitializeDdrioForTraining: initial RdPtrOffsetDqs = 10
N3.C2: InitializeDdrioForTraining: initial RdCmd2RcvEnLatency = 5
N3.C2: InitializeDdrioForTraining: initial WrCmd2DqsStartLatency = 4
N3.C2: InitializeDdrioForTraining: initial RdPtrOffsetRcvEn = 4
N3.C2: InitializeDdrioForTraining: initial RdPtrOffsetDqs = 6
N3.C2: InitializeDdrioForTraining: initial RdPtrOffsetDq = 5
N3.C3: InitializeDdrioForTraining: cleff = 10
N3.C3: InitializeDdrioForTraining: cwleff = 8
N3.C3: InitializeDdrioForTraining: initial ddrInitIndexRx = 4 ddrInitIndexTx = 2
N3.C3: InitializeDdrioForTraining: initial RdCmd2RcvEnLatency = 5
N3.C3: InitializeDdrioForTraining: initial RdPtrOffsetRcvEn = 4
N3.C3: InitializeDdrioForTraining: initial rkrdptroffsetrcvenb = 6
N3.C3: InitializeDdrioForTraining: initial rkrdptroffsetdrvenrcvenb = 5
N3.C3: InitializeDdrioForTraining: initial WrCmd2DqsStartLatency = 4
N3.C3: InitializeDdrioForTraining: initial RdPtrOffsetDqs = 10
N3.C3: InitializeDdrioForTraining: initial RdCmd2RcvEnLatency = 5
N3.C3: InitializeDdrioForTraining: initial WrCmd2DqsStartLatency = 4
N3.C3: InitializeDdrioForTraining: initial RdPtrOffsetRcvEn = 4
N3.C3: InitializeDdrioForTraining: initial RdPtrOffsetDqs = 6
N3.C3: InitializeDdrioForTraining: initial RdPtrOffsetDq = 5
N3: DdrClockStopWa
N3: JckSetOdtRelaxTiming:
N3.C0: ODTTIMCTL (INIT RELAX) rdwidth = 10 rddly = 0 wrwidth = 8 wrdly = 0
N3.C0.S00: DDRIOHSIODATA0_LATCTL1 = 08040804
N3.C0.S01: DDRIOHSIODATA0_LATCTL1 = 08040804
N3.C0.S02: DDRIOHSIODATA0_LATCTL1 = 08040804
N3.C0.S03: DDRIOHSIODATA0_LATCTL1 = 08040804
N3.C0.S04: DDRIOHSIODATA0_LATCTL1 = 08040804
N3.C0.S05: DDRIOHSIODATA0_LATCTL1 = 08040804
N3.C0.S06: DDRIOHSIODATA0_LATCTL1 = 08040804
N3.C0.S07: DDRIOHSIODATA0_LATCTL1 = 08040804
N3.C0.S08: DDRIOHSIODATA0_LATCTL1 = 08040804
N3.C1: ODTTIMCTL (INIT RELAX) rdwidth = 10 rddly = 0 wrwidth = 8 wrdly = 0
N3.C1.S00: DDRIOHSIODATA0_LATCTL1 = 08040804
N3.C1.S01: DDRIOHSIODATA0_LATCTL1 = 08040804
N3.C1.S02: DDRIOHSIODATA0_LATCTL1 = 08040804
N3.C1.S03: DDRIOHSIODATA0_LATCTL1 = 08040804
N3.C1.S04: DDRIOHSIODATA0_LATCTL1 = 08040804
N3.C1.S05: DDRIOHSIODATA0_LATCTL1 = 08040804
N3.C1.S06: DDRIOHSIODATA0_LATCTL1 = 08040804
N3.C1.S07: DDRIOHSIODATA0_LATCTL1 = 08040804
N3.C1.S08: DDRIOHSIODATA0_LATCTL1 = 08040804
N3.C2: ODTTIMCTL (INIT RELAX) rdwidth = 10 rddly = 0 wrwidth = 8 wrdly = 0
N3.C2.S00: DDRIOHSIODATA0_LATCTL1 = 08040804
N3.C2.S01: DDRIOHSIODATA0_LATCTL1 = 08040804
N3.C2.S02: DDRIOHSIODATA0_LATCTL1 = 08040804
N3.C2.S03: DDRIOHSIODATA0_LATCTL1 = 08040804
N3.C2.S04: DDRIOHSIODATA0_LATCTL1 = 08040804
N3.C2.S05: DDRIOHSIODATA0_LATCTL1 = 08040804
N3.C2.S06: DDRIOHSIODATA0_LATCTL1 = 08040804
N3.C2.S07: DDRIOHSIODATA0_LATCTL1 = 08040804
N3.C2.S08: DDRIOHSIODATA0_LATCTL1 = 08040804
N3.C3: ODTTIMCTL (INIT RELAX) rdwidth = 10 rddly = 0 wrwidth = 8 wrdly = 0
N3.C3.S00: DDRIOHSIODATA0_LATCTL1 = 08040804
N3.C3.S01: DDRIOHSIODATA0_LATCTL1 = 08040804
N3.C3.S02: DDRIOHSIODATA0_LATCTL1 = 08040804
N3.C3.S03: DDRIOHSIODATA0_LATCTL1 = 08040804
N3.C3.S04: DDRIOHSIODATA0_LATCTL1 = 08040804
N3.C3.S05: DDRIOHSIODATA0_LATCTL1 = 08040804
N3.C3.S06: DDRIOHSIODATA0_LATCTL1 = 08040804
N3.C3.S07: DDRIOHSIODATA0_LATCTL1 = 08040804
N3.C3.S08: DDRIOHSIODATA0_LATCTL1 = 08040804

START - Early Command Training
N3.C0: DDRIOHSIODATA0_LATCTL1 = 08040804
N3.C0: RdCmd2DataValidLatency = 20, (dlyFrmS = 15, clEff = 10, earlyCas = 0, selNTiming = 2)
N3.C0: SettingForTrainingStep: RdCmd2RcvEnLatency = 5
N3.C0: SettingForTrainingStep: Programming 7 tick initial value to CTL signals
N3.C1: DDRIOHSIODATA0_LATCTL1 = 08040804
N3.C1: RdCmd2DataValidLatency = 20, (dlyFrmS = 15, clEff = 10, earlyCas = 0, selNTiming = 2)
N3.C1: SettingForTrainingStep: RdCmd2RcvEnLatency = 5
N3.C1: SettingForTrainingStep: Programming 10 tick initial value to CTL signals
N3.C2: DDRIOHSIODATA0_LATCTL1 = 08040804
N3.C2: RdCmd2DataValidLatency = 20, (dlyFrmS = 15, clEff = 10, earlyCas = 0, selNTiming = 2)
N3.C2: SettingForTrainingStep: RdCmd2RcvEnLatency = 5
N3.C2: SettingForTrainingStep: Programming 7 tick initial value to CTL signals
N3.C3: DDRIOHSIODATA0_LATCTL1 = 08040804
N3.C3: RdCmd2DataValidLatency = 20, (dlyFrmS = 15, clEff = 10, earlyCas = 0, selNTiming = 2)
N3.C3: SettingForTrainingStep: RdCmd2RcvEnLatency = 5
N3.C3: SettingForTrainingStep: Programming 10 tick initial value to CTL signals
N3: FSM Basic Clock Training
N3.C0: JCK cmd timing = 1N
N3.C0: RdCmd2DataValidLatency = 21, (dlyFrmS = 15, clEff = 10, earlyCas = 0, selNTiming = 0)
N3.C1: RdCmd2DataValidLatency = 21, (dlyFrmS = 15, clEff = 10, earlyCas = 0, selNTiming = 0)
N3.C2: JCK cmd timing = 1N
N3.C2: RdCmd2DataValidLatency = 21, (dlyFrmS = 15, clEff = 10, earlyCas = 0, selNTiming = 0)
N3.C3: RdCmd2DataValidLatency = 21, (dlyFrmS = 15, clEff = 10, earlyCas = 0, selNTiming = 0)
N4.C0: Read Vref - Strobe:0 Worst Left Edge:-31, Worst Right Edge:16, Center:-7
N4.C0: Read Vref - Strobe:1 Worst Left Edge:-31, Worst Right Edge:14, Center:-8
N4.C0: Read Vref - Strobe:2 Worst Left Edge:-31, Worst Right Edge:12, Center:-9
N4.C0: Read Vref - Strobe:3 Worst Left Edge:-31, Worst Right Edge:14, Center:-8
N4.C0: Read Vref - Strobe:4 Worst Left Edge:-31, Worst Right Edge:13, Center:-9
N4.C0: Read Vref - Strobe:5 Worst Left Edge:-31, Worst Right Edge:17, Center:-7
N4.C0: Read Vref - Strobe:6 Worst Left Edge:-31, Worst Right Edge:14, Center:-8
N4.C0: Read Vref - Strobe:7 Worst Left Edge:-31, Worst Right Edge:16, Center:-7
N4.C0: Read Vref - Strobe:8 Worst Left Edge:-31, Worst Right Edge:15, Center:-8
N4.C0: Read Vref - Strobe:9 Worst Left Edge:-31, Worst Right Edge:12, Center:-9
N4.C0: Read Vref - Strobe:10 Worst Left Edge:-31, Worst Right Edge:13, Center:-9
N4.C0: Read Vref - Strobe:11 Worst Left Edge:-31, Worst Right Edge:14, Center:-8
N4.C0: Read Vref - Strobe:12 Worst Left Edge:-31, Worst Right Edge:17, Center:-7
N4.C0: Read Vref - Strobe:13 Worst Left Edge:-31, Worst Right Edge:19, Center:-6
N4.C0: Read Vref - Strobe:14 Worst Left Edge:-31, Worst Right Edge:13, Center:-9
N4.C0: Read Vref - Strobe:15 Worst Left Edge:-31, Worst Right Edge:12, Center:-9
N4.C0: Read Vref - Strobe:16 Worst Left Edge:-31, Worst Right Edge:11, Center:-10
N4.C0: Read Vref - Strobe:17 Worst Left Edge:-31, Worst Right Edge:12, Center:-9
N4.C1: Read Vref - Strobe:0 Worst Left Edge:-31, Worst Right Edge:14, Center:-8
N4.C1: Read Vref - Strobe:1 Worst Left Edge:-31, Worst Right Edge:18, Center:-6
N4.C1: Read Vref - Strobe:2 Worst Left Edge:-31, Worst Right Edge:17, Center:-7
N4.C1: Read Vref - Strobe:3 Worst Left Edge:-31, Worst Right Edge:11, Center:-10
N4.C1: Read Vref - Strobe:4 Worst Left Edge:-31, Worst Right Edge:15, Center:-8
N4.C1: Read Vref - Strobe:5 Worst Left Edge:-31, Worst Right Edge:17, Center:-7
N4.C1: Read Vref - Strobe:6 Worst Left Edge:-31, Worst Right Edge:15, Center:-8
N4.C1: Read Vref - Strobe:7 Worst Left Edge:-31, Worst Right Edge:14, Center:-8
N4.C1: Read Vref - Strobe:8 Worst Left Edge:-31, Worst Right Edge:12, Center:-9
N4.C1: Read Vref - Strobe:9 Worst Left Edge:-31, Worst Right Edge:16, Center:-7
N4.C1: Read Vref - Strobe:10 Worst Left Edge:-31, Worst Right Edge:17, Center:-7
N4.C1: Read Vref - Strobe:11 Worst Left Edge:-31, Worst Right Edge:13, Center:-9
N4.C1: Read Vref - Strobe:12 Worst Left Edge:-31, Worst Right Edge:14, Center:-8
N4.C1: Read Vref - Strobe:13 Worst Left Edge:-31, Worst Right Edge:13, Center:-9
N4.C1: Read Vref - Strobe:14 Worst Left Edge:-31, Worst Right Edge:11, Center:-10
N4.C1: Read Vref - Strobe:15 Worst Left Edge:-31, Worst Right Edge:12, Center:-9
N4.C1: Read Vref - Strobe:16 Worst Left Edge:-31, Worst Right Edge:14, Center:-8
N4.C1: Read Vref - Strobe:17 Worst Left Edge:-31, Worst Right Edge:11, Center:-10
N4.C2: Read Vref - Strobe:0 Worst Left Edge:-31, Worst Right Edge:17, Center:-7
N4.C2: Read Vref - Strobe:1 Worst Left Edge:-31, Worst Right Edge:18, Center:-6
N4.C2: Read Vref - Strobe:2 Worst Left Edge:-31, Worst Right Edge:15, Center:-8
N4.C2: Read Vref - Strobe:3 Worst Left Edge:-31, Worst Right Edge:16, Center:-7
N4.C2: Read Vref - Strobe:4 Worst Left Edge:-31, Worst Right Edge:14, Center:-8
N4.C2: Read Vref - Strobe:5 Worst Left Edge:-31, Worst Right Edge:12, Center:-9
N4.C2: Read Vref - Strobe:6 Worst Left Edge:-31, Worst Right Edge:11, Center:-10
N4.C2: Read Vref - Strobe:7 Worst Left Edge:-31, Worst Right Edge:14, Center:-8
N4.C2: Read Vref - Strobe:8 Worst Left Edge:-31, Worst Right Edge:13, Center:-9
N4.C2: Read Vref - Strobe:9 Worst Left Edge:-31, Worst Right Edge:13, Center:-9
N4.C2: Read Vref - Strobe:10 Worst Left Edge:-31, Worst Right Edge:14, Center:-8
N4.C2: Read Vref - Strobe:11 Worst Left Edge:-31, Worst Right Edge:15, Center:-8
N4.C2: Read Vref - Strobe:12 Worst Left Edge:-31, Worst Right Edge:15, Center:-8
N4.C2: Read Vref - Strobe:13 Worst Left Edge:-31, Worst Right Edge:13, Center:-9
N4.C2: Read Vref - Strobe:14 Worst Left Edge:-31, Worst Right Edge:11, Center:-10
N4.C2: Read Vref - Strobe:15 Worst Left Edge:-31, Worst Right Edge:15, Center:-8
N4.C2: Read Vref - Strobe:16 Worst Left Edge:-31, Worst Right Edge:17, Center:-7
N4.C2: Read Vref - Strobe:17 Worst Left Edge:-31, Worst Right Edge:17, Center:-7
N4.C3: Read Vref - Strobe:0 Worst Left Edge:-31, Worst Right Edge:16, Center:-7
N4.C3: Read Vref - Strobe:1 Worst Left Edge:-31, Worst Right Edge:13, Center:-9
N4.C3: Read Vref - Strobe:2 Worst Left Edge:-31, Worst Right Edge:13, Center:-9
N4.C3: Read Vref - Strobe:3 Worst Left Edge:-31, Worst Right Edge:15, Center:-8
N4.C3: Read Vref - Strobe:4 Worst Left Edge:-31, Worst Right Edge:12, Center:-9
N4.C3: Read Vref - Strobe:5 Worst Left Edge:-31, Worst Right Edge:11, Center:-10
N4.C3: Read Vref - Strobe:6 Worst Left Edge:-31, Worst Right Edge:17, Center:-7
N4.C3: Read Vref - Strobe:7 Worst Left Edge:-31, Worst Right Edge:12, Center:-9
N4.C3: Read Vref - Strobe:8 Worst Left Edge:-31, Worst Right Edge:15, Center:-8
N4.C3: Read Vref - Strobe:9 Worst Left Edge:-31, Worst Right Edge:14, Center:-8
N4.C3: Read Vref - Strobe:10 Worst Left Edge:-31, Worst Right Edge:19, Center:-6
N4.C3: Read Vref - Strobe:11 Worst Left Edge:-31, Worst Right Edge:19, Center:-6
N4.C3: Read Vref - Strobe:12 Worst Left Edge:-31, Worst Right Edge:17, Center:-7
N4.C3: Read Vref - Strobe:13 Worst Left Edge:-31, Worst Right Edge:18, Center:-6
N4.C3: Read Vref - Strobe:14 Worst Left Edge:-31, Worst Right Edge:14, Center:-8
N4.C3: Read Vref - Strobe:15 Worst Left Edge:-31, Worst Right Edge:12, Center:-9
N4.C3: Read Vref - Strobe:16 Worst Left Edge:-31, Worst Right Edge:19, Center:-6
N4.C3: Read Vref - Strobe:17 Worst Left Edge:-31, Worst Right Edge:13, Center:-9
N4: RunTrainStep: Final status = 0

END - Rd Voltage Training              Time         2543 ms
N4.C0.D0.R0.S00: StoreJckWorstRank: worst rank = 0, greatestDelay = 1323
N4.C0.D0.R0.S07: StoreJckWorstRank: worst rank = 0, greatestDelay = 1324
N4.C0.D0.R1.S07: StoreJckWorstRank: worst rank = 1, greatestDelay = 1325
N4.C1.D0.R0.S00: StoreJckWorstRank: worst rank = 0, greatestDelay = 1374
N4.C0: StoreJckWorstRank: final value: worst rank = 0
N4.C2.D0.R0.S00: StoreJckWorstRank: worst rank = 0, greatestDelay = 1327
N4.C3.D0.R0.S00: StoreJckWorstRank: worst rank = 0, greatestDelay = 1373
N4.C1: StoreJckWorstRank: final value: worst rank = 0
GetAllRankMargins
N4: Checking margins for all ranks...
N4: 
Get Rx Dqs margins...
N4: GetMargins: Level = 1, group = 11, mode = 0, scope = 3
N3.C0.D0: CalcFinalClock(90,122) = 23
N3.C1.D0: CalcFinalClock(93,120) = 25
N3.C2.D0: CalcFinalClock(93,120) = 25
N3.C3.D0: CalcFinalClock(96,112) = 24
N3.C0: JCK cmd timing = 3N
N3.C0: RdCmd2DataValidLatency = 20, (dlyFrmS = 15, clEff = 10, earlyCas = 0, selNTiming = 2)
N3.C1: RdCmd2DataValidLatency = 20, (dlyFrmS = 15, clEff = 10, earlyCas = 0, selNTiming = 2)
N3.C2: JCK cmd timing = 3N
N3.C2: RdCmd2DataValidLatency = 20, (dlyFrmS = 15, clEff = 10, earlyCas = 0, selNTiming = 2)
N3.C3: RdCmd2DataValidLatency = 20, (dlyFrmS = 15, clEff = 10, earlyCas = 0, selNTiming = 2)
N3: RunTrainStep: Final status = 0

END - Early Command Training           Time         1736 ms

START - Basic Read DQ/DQS Training
N3.C0: RdCmd2DataValidLatency = 20, (dlyFrmS = 15, clEff = 10, earlyCas = 0, selNTiming = 2)
N3.C0: SettingForTrainingStep: RdCmd2RcvEnLatency = 5
N3.C1: RdCmd2DataValidLatency = 20, (dlyFrmS = 15, clEff = 10, earlyCas = 0, selNTiming = 2)
N3.C1: SettingForTrainingStep: RdCmd2RcvEnLatency = 5
N3.C2: RdCmd2DataValidLatency = 20, (dlyFrmS = 15, clEff = 10, earlyCas = 0, selNTiming = 2)
N3.C2: SettingForTrainingStep: RdCmd2RcvEnLatency = 5
N3.C3: RdCmd2DataValidLatency = 20, (dlyFrmS = 15, clEff = 10, earlyCas = 0, selNTiming = 2)
N3.C3: SettingForTrainingStep: RdCmd2RcvEnLatency = 5
N3.C0.D0.R0.S00: RdDqDqs FSM results: Left = 02, Right = 58, center = 30
N6.C0: Read Vref - Strobe:0 Worst Left Edge:-28, Worst Right Edge:31, Center:1
N3.C0.D0.R0.S00: RxDqsDelay = 030
N6.C0: Read Vref - Strobe:1 Worst Left Edge:-26, Worst Right Edge:31, Center:2
N0.C0: Read Vref - Strobe:0 Worst Left Edge:-31, Worst Right Edge:31, Center:0
N3.C0.D0.R0.S01: RdDqDqs FSM results: Left = 06, Right = 63, center = 34
N6.C0: Read Vref - Strobe:2 Worst Left Edge:-27, Worst Right Edge:31, Center:2
N0.C0: Read Vref - Strobe:1 Worst Left Edge:-23, Worst Right Edge:31, Center:4
N3.C0.D0.R0.S01: RxDqsDelay = 034
N6.C0: Read Vref - Strobe:3 Worst Left Edge:-29, Worst Right Edge:31, Center:1
N0.C0: Read Vref - Strobe:2 Worst Left Edge:-24, Worst Right Edge:31, Center:3
N3.C0.D0.R0.S02: RdDqDqs FSM results: Left = 06, Right = 63, center = 34
N6.C0: Read Vref - Strobe:4 Worst Left Edge:-27, Worst Right Edge:31, Center:2
N0.C0: Read Vref - Strobe:3 Worst Left Edge:-27, Worst Right Edge:31, Center:2
N3.C0.D0.R0.S02: RxDqsDelay = 034
N6.C0: Read Vref - Strobe:5 Worst Left Edge:-24, Worst Right Edge:31, Center:3
N0.C0: Read Vref - Strobe:4 Worst Left Edge:-30, Worst Right Edge:31, Center:0
N3.C0.D0.R0.S03: RdDqDqs FSM results: Left = 10, Right = 63, center = 36
N6.C0: Read Vref - Strobe:6 Worst Left Edge:-26, Worst Right Edge:31, Center:2
N0.C0: Read Vref - Strobe:5 Worst Left Edge:-25, Worst Right Edge:31, Center:3
N3.C0.D0.R0.S03: RxDqsDelay = 036
N6.C0: Read Vref - Strobe:7 Worst Left Edge:-29, Worst Right Edge:31, Center:1
N0.C0: Read Vref - Strobe:6 Worst Left Edge:-28, Worst Right Edge:30, Center:1
N3.C0.D0.R0.S04: RdDqDqs FSM results: Left = 06, Right = 63, center = 34
N6.C0: Read Vref - Strobe:8 Worst Left Edge:-21, Worst Right Edge:31, Center:5
N0.C0: Read Vref - Strobe:7 Worst Left Edge:-29, Worst Right Edge:31, Center:1
N3.C0.D0.R0.S04: RxDqsDelay = 034
N6.C0: Read Vref - Strobe:9 Worst Left Edge:-29, Worst Right Edge:31, Center:1
N0.C0: Read Vref - Strobe:8 Worst Left Edge:-28, Worst Right Edge:31, Center:1
N3.C0.D0.R0.S05: RdDqDqs FSM results: Left = 10, Right = 63, center = 36
N6.C0: Read Vref - Strobe:10 Worst Left Edge:-21, Worst Right Edge:31, Center:5
N0.C0: Read Vref - Strobe:9 Worst Left Edge:-29, Worst Right Edge:31, Center:1
N3.C0.D0.R0.S05: RxDqsDelay = 036
N6.C0: Read Vref - Strobe:11 Worst Left Edge:-25, Worst Right Edge:31, Center:3
N0.C0: Read Vref - Strobe:10 Worst Left Edge:-22, Worst Right Edge:31, Center:4
N3.C0.D0.R0.S06: RdDqDqs FSM results: Left = 04, Right = 63, center = 33
N6.C0: Read Vref - Strobe:12 Worst Left Edge:-27, Worst Right Edge:31, Center:2
N0.C0: Read Vref - Strobe:11 Worst Left Edge:-29, Worst Right Edge:31, Center:1
N3.C0.D0.R0.S06: RxDqsDelay = 033
N6.C0: Read Vref - Strobe:13 Worst Left Edge:-25, Worst Right Edge:31, Center:3
N0.C0: Read Vref - Strobe:12 Worst Left Edge:-31, Worst Right Edge:31, Center:0
N3.C0.D0.R0.S07: RdDqDqs FSM results: Left = 07, Right = 63, center = 35
N6.C0: Read Vref - Strobe:14 Worst Left Edge:-25, Worst Right Edge:31, Center:3
N0.C0: Read Vref - Strobe:13 Worst Left Edge:-27, Worst Right Edge:31, Center:2
N3.C0.D0.R0.S07: RxDqsDelay = 035
N6.C0: Read Vref - Strobe:15 Worst Left Edge:-25, Worst Right Edge:31, Center:3
N0.C0: Read Vref - Strobe:14 Worst Left Edge:-28, Worst Right Edge:31, Center:1
N3.C0.D0.R0.S08: RdDqDqs FSM results: Left = 08, Right = 63, center = 35
N6.C0: Read Vref - Strobe:16 Worst Left Edge:-26, Worst Right Edge:31, Center:2
N0.C0: Read Vref - Strobe:15 Worst Left Edge:-25, Worst Right Edge:31, Center:3
N3.C0.D0.R0.S08: RxDqsDelay = 035
N6.C0: Read Vref - Strobe:17 Worst Left Edge:-29, Worst Right Edge:31, Center:1
N0.C0: Read Vref - Strobe:16 Worst Left Edge:-30, Worst Right Edge:31, Center:0
N3.C0.D0.R0.S09: RdDqDqs FSM results: Left = 04, Right = 63, center = 33
N6.C1: Read Vref - Strobe:0 Worst Left Edge:-31, Worst Right Edge:31, Center:0
N0.C0: Read Vref - Strobe:17 Worst Left Edge:-30, Worst Right Edge:31, Center:0
N3.C0.D0.R0.S09: RxDqsDelay = 033
N6.C1: Read Vref - Strobe:1 Worst Left Edge:-30, Worst Right Edge:31, Center:0
N0.C1: Read Vref - Strobe:0 Worst Left Edge:-22, Worst Right Edge:31, Center:4
N3.C0.D0.R0.S10: RdDqDqs FSM results: Left = 08, Right = 63, center = 35
N6.C1: Read Vref - Strobe:2 Worst Left Edge:-23, Worst Right Edge:31, Center:4
N0.C1: Read Vref - Strobe:1 Worst Left Edge:-28, Worst Right Edge:31, Center:1
N3.C0.D0.R0.S10: RxDqsDelay = 035
N6.C1: Read Vref - Strobe:3 Worst Left Edge:-29, Worst Right Edge:31, Center:1
N0.C1: Read Vref - Strobe:2 Worst Left Edge:-24, Worst Right Edge:31, Center:3
N3.C0.D0.R0.S11: RdDqDqs FSM results: Left = 03, Right = 60, center = 31
N6.C1: Read Vref - Strobe:4 Worst Left Edge:-28, Worst Right Edge:31, Center:1
N0.C1: Read Vref - Strobe:3 Worst Left Edge:-28, Worst Right Edge:31, Center:1
N3.C0.D0.R0.S11: RxDqsDelay = 031
N6.C1: Read Vref - Strobe:5 Worst Left Edge:-24, Worst Right Edge:31, Center:3
N0.C1: Read Vref - Strobe:4 Worst Left Edge:-26, Worst Right Edge:31, Center:2
N3.C0.D0.R0.S12: RdDqDqs FSM results: Left = 08, Right = 63, center = 35
N6.C1: Read Vref - Strobe:6 Worst Left Edge:-27, Worst Right Edge:31, Center:2
N0.C1: Read Vref - Strobe:5 Worst Left Edge:-25, Worst Right Edge:30, Center:2
N3.C0.D0.R0.S12: RxDqsDelay = 035
N6.C1: Read Vref - Strobe:7 Worst Left Edge:-28, Worst Right Edge:31, Center:1
N0.C1: Read Vref - Strobe:6 Worst Left Edge:-26, Worst Right Edge:31, Center:2
N3.C0.D0.R0.S13: RdDqDqs FSM results: Left = 06, Right = 63, center = 34
N6.C1: Read Vref - Strobe:8 Worst Left Edge:-28, Worst Right Edge:31, Center:1
N0.C1: Read Vref - Strobe:7 Worst Left Edge:-23, Worst Right Edge:31, Center:4
N3.C0.D0.R0.S13: RxDqsDelay = 034
N6.C1: Read Vref - Strobe:9 Worst Left Edge:-23, Worst Right Edge:31, Center:4
N0.C1: Read Vref - Strobe:8 Worst Left Edge:-27, Worst Right Edge:31, Center:2
N3.C0.D0.R0.S14: RdDqDqs FSM results: Left = 08, Right = 63, center = 35
N6.C1: Read Vref - Strobe:10 Worst Left Edge:-23, Worst Right Edge:31, Center:4
N0.C1: Read Vref - Strobe:9 Worst Left Edge:-24, Worst Right Edge:31, Center:3
N3.C0.D0.R0.S14: RxDqsDelay = 035
N6.C1: Read Vref - Strobe:11 Worst Left Edge:-27, Worst Right Edge:31, Center:2
N0.C1: Read Vref - Strobe:10 Worst Left Edge:-28, Worst Right Edge:31, Center:1
N3.C0.D0.R0.S15: RdDqDqs FSM results: Left = 04, Right = 58, center = 31
N6.C1: Read Vref - Strobe:12 Worst Left Edge:-23, Worst Right Edge:31, Center:4
N0.C1: Read Vref - Strobe:11 Worst Left Edge:-26, Worst Right Edge:31, Center:2
N3.C0.D0.R0.S15: RxDqsDelay = 031
N6.C1: Read Vref - Strobe:13 Worst Left Edge:-25, Worst Right Edge:31, Center:3
N0.C1: Read Vref - Strobe:12 Worst Left Edge:-28, Worst Right Edge:31, Center:1
N3.C0.D0.R0.S16: RdDqDqs FSM results: Left = 03, Right = 58, center = 30
N6.C1: Read Vref - Strobe:14 Worst Left Edge:-24, Worst Right Edge:31, Center:3
N0.C1: Read Vref - Strobe:13 Worst Left Edge:-26, Worst Right Edge:29, Center:1
N3.C0.D0.R0.S16: RxDqsDelay = 030
N6.C1: Read Vref - Strobe:15 Worst Left Edge:-26, Worst Right Edge:31, Center:2
N0.C1: Read Vref - Strobe:14 Worst Left Edge:-28, Worst Right Edge:31, Center:1
N3.C0.D0.R0.S17: RdDqDqs FSM results: Left = 06, Right = 63, center = 34
N4: 
Get Tx Dq margins...
N6.C1: Read Vref - Strobe:16 Worst Left Edge:-27, Worst Right Edge:31, Center:2
N0.C1: Read Vref - Strobe:15 Worst Left Edge:-30, Worst Right Edge:31, Center:0
N3.C0.D0.R0.S17: RxDqsDelay = 034
N4: GetMargins: Level = 1, group = 12, mode = 0, scope = 3
N6.C1: Read Vref - Strobe:17 Worst Left Edge:-29, Worst Right Edge:31, Center:1
N0.C1: Read Vref - Strobe:16 Worst Left Edge:-27, Worst Right Edge:31, Center:2
N3.C0.D0.R1.S00: RdDqDqs FSM results: Left = 02, Right = 56, center = 29
N6.C2: Read Vref - Strobe:0 Worst Left Edge:-31, Worst Right Edge:31, Center:0
N0.C1: Read Vref - Strobe:17 Worst Left Edge:-29, Worst Right Edge:31, Center:1
N3.C0.D0.R1.S00: RxDqsDelay = 029
N6.C2: Read Vref - Strobe:1 Worst Left Edge:-31, Worst Right Edge:31, Center:0
N0.C2: Read Vref - Strobe:0 Worst Left Edge:-28, Worst Right Edge:31, Center:1
N3.C0.D0.R1.S01: RdDqDqs FSM results: Left = 06, Right = 63, center = 34
N6.C2: Read Vref - Strobe:2 Worst Left Edge:-27, Worst Right Edge:31, Center:2
N0.C2: Read Vref - Strobe:1 Worst Left Edge:-31, Worst Right Edge:31, Center:0
N3.C0.D0.R1.S01: RxDqsDelay = 034
N6.C2: Read Vref - Strobe:3 Worst Left Edge:-31, Worst Right Edge:31, Center:0
N0.C2: Read Vref - Strobe:2 Worst Left Edge:-29, Worst Right Edge:31, Center:1
N3.C0.D0.R1.S02: RdDqDqs FSM results: Left = 06, Right = 63, center = 34
N6.C2: Read Vref - Strobe:4 Worst Left Edge:-27, Worst Right Edge:31, Center:2
N0.C2: Read Vref - Strobe:3 Worst Left Edge:-27, Worst Right Edge:31, Center:2
N3.C0.D0.R1.S02: RxDqsDelay = 034
N6.C2: Read Vref - Strobe:5 Worst Left Edge:-26, Worst Right Edge:31, Center:2
N0.C2: Read Vref - Strobe:4 Worst Left Edge:-30, Worst Right Edge:31, Center:0
N3.C0.D0.R1.S03: RdDqDqs FSM results: Left = 10, Right = 63, center = 36
N6.C2: Read Vref - Strobe:6 Worst Left Edge:-24, Worst Right Edge:31, Center:3
N0.C2: Read Vref - Strobe:5 Worst Left Edge:-26, Worst Right Edge:31, Center:2
N3.C0.D0.R1.S03: RxDqsDelay = 036
N6.C2: Read Vref - Strobe:7 Worst Left Edge:-25, Worst Right Edge:31, Center:3
N0.C2: Read Vref - Strobe:6 Worst Left Edge:-28, Worst Right Edge:31, Center:1
N3.C0.D0.R1.S04: RdDqDqs FSM results: Left = 06, Right = 63, center = 34
N6.C2: Read Vref - Strobe:8 Worst Left Edge:-29, Worst Right Edge:31, Center:1
N0.C2: Read Vref - Strobe:7 Worst Left Edge:-25, Worst Right Edge:31, Center:3
N3.C0.D0.R1.S04: RxDqsDelay = 034
N6.C2: Read Vref - Strobe:9 Worst Left Edge:-30, Worst Right Edge:31, Center:0
N0.C2: Read Vref - Strobe:8 Worst Left Edge:-31, Worst Right Edge:31, Center:0
N3.C0.D0.R1.S05: RdDqDqs FSM results: Left = 09, Right = 63, center = 36
N6.C2: Read Vref - Strobe:10 Worst Left Edge:-29, Worst Right Edge:31, Center:1
N0.C2: Read Vref - Strobe:9 Worst Left Edge:-28, Worst Right Edge:31, Center:1
N3.C0.D0.R1.S05: RxDqsDelay = 036
N6.C2: Read Vref - Strobe:11 Worst Left Edge:-31, Worst Right Edge:31, Center:0
N0.C2: Read Vref - Strobe:10 Worst Left Edge:-25, Worst Right Edge:31, Center:3
N3.C0.D0.R1.S06: RdDqDqs FSM results: Left = 05, Right = 63, center = 34
N6.C2: Read Vref - Strobe:12 Worst Left Edge:-26, Worst Right Edge:31, Center:2
N0.C2: Read Vref - Strobe:11 Worst Left Edge:-30, Worst Right Edge:31, Center:0
N3.C0.D0.R1.S06: RxDqsDelay = 034
N6.C2: Read Vref - Strobe:13 Worst Left Edge:-29, Worst Right Edge:31, Center:1
N0.C2: Read Vref - Strobe:12 Worst Left Edge:-30, Worst Right Edge:31, Center:0
N3.C0.D0.R1.S07: RdDqDqs FSM results: Left = 06, Right = 59, center = 32
N6.C2: Read Vref - Strobe:14 Worst Left Edge:-29, Worst Right Edge:31, Center:1
N0.C2: Read Vref - Strobe:13 Worst Left Edge:-29, Worst Right Edge:31, Center:1
N3.C0.D0.R1.S07: RxDqsDelay = 032
N6.C2: Read Vref - Strobe:15 Worst Left Edge:-30, Worst Right Edge:31, Center:0
N0.C2: Read Vref - Strobe:14 Worst Left Edge:-30, Worst Right Edge:30, Center:0
N3.C0.D0.R1.S08: RdDqDqs FSM results: Left = 06, Right = 63, center = 34
N6.C2: Read Vref - Strobe:16 Worst Left Edge:-27, Worst Right Edge:31, Center:2
N0.C2: Read Vref - Strobe:15 Worst Left Edge:-29, Worst Right Edge:31, Center:1
N3.C0.D0.R1.S08: RxDqsDelay = 034
N6.C2: Read Vref - Strobe:17 Worst Left Edge:-26, Worst Right Edge:31, Center:2
N0.C2: Read Vref - Strobe:16 Worst Left Edge:-25, Worst Right Edge:31, Center:3
N3.C0.D0.R1.S09: RdDqDqs FSM results: Left = 04, Right = 63, center = 33
N6.C3: Read Vref - Strobe:0 Worst Left Edge:-25, Worst Right Edge:31, Center:3
N0.C2: Read Vref - Strobe:17 Worst Left Edge:-31, Worst Right Edge:31, Center:0
N3.C0.D0.R1.S09: RxDqsDelay = 033
N6.C3: Read Vref - Strobe:1 Worst Left Edge:-31, Worst Right Edge:31, Center:0
N0.C3: Read Vref - Strobe:0 Worst Left Edge:-22, Worst Right Edge:31, Center:4
N3.C0.D0.R1.S10: RdDqDqs FSM results: Left = 06, Right = 63, center = 34
N6.C3: Read Vref - Strobe:2 Worst Left Edge:-26, Worst Right Edge:31, Center:2
N0.C3: Read Vref - Strobe:1 Worst Left Edge:-23, Worst Right Edge:30, Center:3
N3.C0.D0.R1.S10: RxDqsDelay = 034
N6.C3: Read Vref - Strobe:3 Worst Left Edge:-24, Worst Right Edge:31, Center:3
N0.C3: Read Vref - Strobe:2 Worst Left Edge:-28, Worst Right Edge:31, Center:1
N3.C0.D0.R1.S11: RdDqDqs FSM results: Left = 04, Right = 60, center = 32
N6.C3: Read Vref - Strobe:4 Worst Left Edge:-29, Worst Right Edge:31, Center:1
N0.C3: Read Vref - Strobe:3 Worst Left Edge:-28, Worst Right Edge:31, Center:1
N3.C0.D0.R1.S11: RxDqsDelay = 032
N6.C3: Read Vref - Strobe:5 Worst Left Edge:-29, Worst Right Edge:31, Center:1
N0.C3: Read Vref - Strobe:4 Worst Left Edge:-25, Worst Right Edge:31, Center:3
N3.C0.D0.R1.S12: RdDqDqs FSM results: Left = 09, Right = 63, center = 36
N6.C3: Read Vref - Strobe:6 Worst Left Edge:-27, Worst Right Edge:31, Center:2
N0.C3: Read Vref - Strobe:5 Worst Left Edge:-27, Worst Right Edge:31, Center:2
N3.C0.D0.R1.S12: RxDqsDelay = 036
N6.C3: Read Vref - Strobe:7 Worst Left Edge:-31, Worst Right Edge:31, Center:0
N0.C3: Read Vref - Strobe:6 Worst Left Edge:-24, Worst Right Edge:31, Center:3
N3.C0.D0.R1.S13: RdDqDqs FSM results: Left = 06, Right = 63, center = 34
N6.C3: Read Vref - Strobe:8 Worst Left Edge:-31, Worst Right Edge:31, Center:0
N0.C3: Read Vref - Strobe:7 Worst Left Edge:-30, Worst Right Edge:31, Center:0
N3.C0.D0.R1.S13: RxDqsDelay = 034
N6.C3: Read Vref - Strobe:9 Worst Left Edge:-30, Worst Right Edge:31, Center:0
N0.C3: Read Vref - Strobe:8 Worst Left Edge:-31, Worst Right Edge:31, Center:0
N3.C0.D0.R1.S14: RdDqDqs FSM results: Left = 07, Right = 63, center = 35
N6.C3: Read Vref - Strobe:10 Worst Left Edge:-31, Worst Right Edge:31, Center:0
N0.C3: Read Vref - Strobe:9 Worst Left Edge:-26, Worst Right Edge:31, Center:2
N3.C0.D0.R1.S14: RxDqsDelay = 035
N6.C3: Read Vref - Strobe:11 Worst Left Edge:-31, Worst Right Edge:31, Center:0
N0.C3: Read Vref - Strobe:10 Worst Left Edge:-29, Worst Right Edge:31, Center:1
N3.C0.D0.R1.S15: RdDqDqs FSM results: Left = 04, Right = 57, center = 30
N6.C3: Read Vref - Strobe:12 Worst Left Edge:-28, Worst Right Edge:31, Center:1
N0.C3: Read Vref - Strobe:11 Worst Left Edge:-31, Worst Right Edge:31, Center:0
N3.C0.D0.R1.S15: RxDqsDelay = 030
N6.C3: Read Vref - Strobe:13 Worst Left Edge:-24, Worst Right Edge:31, Center:3
N0.C3: Read Vref - Strobe:12 Worst Left Edge:-28, Worst Right Edge:31, Center:1
N3.C0.D0.R1.S16: RdDqDqs FSM results: Left = 03, Right = 57, center = 30
N6.C3: Read Vref - Strobe:14 Worst Left Edge:-29, Worst Right Edge:31, Center:1
N0.C3: Read Vref - Strobe:13 Worst Left Edge:-31, Worst Right Edge:31, Center:0
N3.C0.D0.R1.S16: RxDqsDelay = 030
N6.C3: Read Vref - Strobe:15 Worst Left Edge:-26, Worst Right Edge:31, Center:2
N0.C3: Read Vref - Strobe:14 Worst Left Edge:-28, Worst Right Edge:31, Center:1
N3.C0.D0.R1.S17: RdDqDqs FSM results: Left = 06, Right = 63, center = 34
N6.C3: Read Vref - Strobe:16 Worst Left Edge:-28, Worst Right Edge:31, Center:1
N0.C3: Read Vref - Strobe:15 Worst Left Edge:-30, Worst Right Edge:31, Center:0
N3.C0.D0.R1.S17: RxDqsDelay = 034
N6.C3: Read Vref - Strobe:17 Worst Left Edge:-22, Worst Right Edge:31, Center:4
N0.C3: Read Vref - Strobe:16 Worst Left Edge:-27, Worst Right Edge:31, Center:2
START_DATA_RX_DQS
N6: RunTrainStep: Final status = 0
N0.C3: Read Vref - Strobe:17 Worst Left Edge:-29, Worst Right Edge:31, Center:1
N3.C0.R0.S00: PI = 29

END - Rd Voltage Training              Time         4550 ms
N0: RunTrainStep: Final status = 0
N3.C0.R0.S01: PI = 34
N6.C0.D0.R0.S00: StoreJckWorstRank: worst rank = 0, greatestDelay = 1334

END - Rd Voltage Training              Time         4568 ms
N3.C0.R0.S02: PI = 34
N6.C1.D0.R0.S00: StoreJckWorstRank: worst rank = 0, greatestDelay = 1378
N0.C0.D0.R0.S00: StoreJckWorstRank: worst rank = 0, greatestDelay = 1320
N3.C0.R0.S03: PI = 36
N6.C1.D0.R1.S00: StoreJckWorstRank: worst rank = 1, greatestDelay = 1380
N0.C0.D0.R0.S07: StoreJckWorstRank: worst rank = 0, greatestDelay = 1326
N3.C0.R0.S04: PI = 34
N6.C0: StoreJckWorstRank: final value: worst rank = 1
N0.C1.D0.R0.S00: StoreJckWorstRank: worst rank = 0, greatestDelay = 1374
N3.C0.R0.S05: PI = 36
N6.C2.D0.R0.S00: StoreJckWorstRank: worst rank = 0, greatestDelay = 1333
N0.C1.D0.R1.S00: StoreJckWorstRank: worst rank = 1, greatestDelay = 1376
N3.C0.R0.S06: PI = 33
N6.C3.D0.R0.S00: StoreJckWorstRank: worst rank = 0, greatestDelay = 1379
N0.C0: StoreJckWorstRank: final value: worst rank = 1
N3.C0.R0.S07: PI = 33
N6.C3.D0.R1.S00: StoreJckWorstRank: worst rank = 1, greatestDelay = 1381
N0.C2.D0.R0.S00: StoreJckWorstRank: worst rank = 0, greatestDelay = 1329
N3.C0.R0.S08: PI = 34
N6.C1: StoreJckWorstRank: final value: worst rank = 1
N0.C2.D0.R0.S09: StoreJckWorstRank: worst rank = 0, greatestDelay = 1330
N3.C0.R0.S09: PI = 33
GetAllRankMargins
N0.C3.D0.R0.S00: StoreJckWorstRank: worst rank = 0, greatestDelay = 1373
N3.C0.R0.S10: PI = 34
N6: Checking margins for all ranks...
N0.C3.D0.R0.S09: StoreJckWorstRank: worst rank = 0, greatestDelay = 1375
N3.C0.R0.S11: PI = 31
N6: 
Get Rx Dqs margins...
N0.C1: StoreJckWorstRank: final value: worst rank = 0
N3.C0.R0.S12: PI = 35
N6: GetMargins: Level = 1, group = 11, mode = 0, scope = 3
GetAllRankMargins
N3.C0.R0.S13: PI = 34
N0: Checking margins for all ranks...
N3.C0.R0.S14: PI = 35
Checkpoint Code: Socket 0, 0xB7, 0x17, 0x0000
N3.C0.R0.S15: PI = 30
N0: 
Get Rx Dqs margins...
N3.C0.R0.S16: PI = 30
N0: GetMargins: Level = 1, group = 11, mode = 0, scope = 3
N3.C0.R0.S17: PI = 34
N3.C0.R0.S00: PI = 29
N3.C0.R0.S01: PI = 34
N3.C0.R0.S02: PI = 34
N3.C0.R0.S03: PI = 36
N3.C0.R0.S04: PI = 34
N3.C0.R0.S05: PI = 36
N3.C0.R0.S06: PI = 33
N3.C0.R0.S07: PI = 33
N3.C0.R0.S08: PI = 34
N3.C0.R0.S09: PI = 33
N3.C0.R0.S10: PI = 34
N3.C0.R0.S11: PI = 31
N3.C0.R0.S12: PI = 35
N3.C0.R0.S13: PI = 34
N3.C0.R0.S14: PI = 35
N3.C0.R0.S15: PI = 30
N3.C0.R0.S16: PI = 30
N3.C0.R0.S17: PI = 34
STOP_DATA_RX_DQS
N3.C1.D0.R0.S00: RdDqDqs FSM results: Left = 04, Right = 55, center = 29
N3.C1.D0.R0.S00: RxDqsDelay = 029
N3.C1.D0.R0.S01: RdDqDqs FSM results: Left = 06, Right = 63, center = 34
N3.C1.D0.R0.S01: RxDqsDelay = 034
N3.C1.D0.R0.S02: RdDqDqs FSM results: Left = 05, Right = 59, center = 32
N3.C1.D0.R0.S02: RxDqsDelay = 032
N3.C1.D0.R0.S03: RdDqDqs FSM results: Left = 08, Right = 63, center = 35
N3.C1.D0.R0.S03: RxDqsDelay = 035
N3.C1.D0.R0.S04: RdDqDqs FSM results: Left = 06, Right = 63, center = 34
N3.C1.D0.R0.S04: RxDqsDelay = 034
N3.C1.D0.R0.S05: RdDqDqs FSM results: Left = 09, Right = 63, center = 36
N3.C1.D0.R0.S05: RxDqsDelay = 036
N3.C1.D0.R0.S06: RdDqDqs FSM results: Left = 04, Right = 63, center = 33
N3.C1.D0.R0.S06: RxDqsDelay = 033
N3.C1.D0.R0.S07: RdDqDqs FSM results: Left = 06, Right = 63, center = 34
N3.C1.D0.R0.S07: RxDqsDelay = 034
N3.C1.D0.R0.S08: RdDqDqs FSM results: Left = 05, Right = 63, center = 34
N3.C1.D0.R0.S08: RxDqsDelay = 034
N3.C1.D0.R0.S09: RdDqDqs FSM results: Left = 07, Right = 63, center = 35
N3.C1.D0.R0.S09: RxDqsDelay = 035
N3.C1.D0.R0.S10: RdDqDqs FSM results: Left = 05, Right = 63, center = 34
N3.C1.D0.R0.S10: RxDqsDelay = 034
N3.C1.D0.R0.S11: RdDqDqs FSM results: Left = 03, Right = 61, center = 32
N3.C1.D0.R0.S11: RxDqsDelay = 032
N3.C1.D0.R0.S12: RdDqDqs FSM results: Left = 06, Right = 63, center = 34
N3.C1.D0.R0.S12: RxDqsDelay = 034
N3.C1.D0.R0.S13: RdDqDqs FSM results: Left = 02, Right = 59, center = 30
N3.C1.D0.R0.S13: RxDqsDelay = 030
N3.C1.D0.R0.S14: RdDqDqs FSM results: Left = 07, Right = 60, center = 33
N3.C1.D0.R0.S14: RxDqsDelay = 033
N3.C1.D0.R0.S15: RdDqDqs FSM results: Left = 06, Right = 63, center = 34
N3.C1.D0.R0.S15: RxDqsDelay = 034
N3.C1.D0.R0.S16: RdDqDqs FSM results: Left = 06, Right = 59, center = 32
N3.C1.D0.R0.S16: RxDqsDelay = 032
N3.C1.D0.R0.S17: RdDqDqs FSM results: Left = 05, Right = 63, center = 34
N3.C1.D0.R0.S17: RxDqsDelay = 034
N3.C1.D0.R1.S00: RdDqDqs FSM results: Left = 04, Right = 53, center = 28
N3.C1.D0.R1.S00: RxDqsDelay = 028
N3.C1.D0.R1.S01: RdDqDqs FSM results: Left = 06, Right = 63, center = 34
N3.C1.D0.R1.S01: RxDqsDelay = 034
N4: 
Get Rx Vref margins...
N3.C1.D0.R1.S02: RdDqDqs FSM results: Left = 05, Right = 59, center = 32
N4: GetMargins: Level = 1, group = 13, mode = 0, scope = 3
N3.C1.D0.R1.S02: RxDqsDelay = 032
N3.C1.D0.R1.S03: RdDqDqs FSM results: Left = 09, Right = 63, center = 36
N3.C1.D0.R1.S03: RxDqsDelay = 036
N3.C1.D0.R1.S04: RdDqDqs FSM results: Left = 07, Right = 63, center = 35
N3.C1.D0.R1.S04: RxDqsDelay = 035
N3.C1.D0.R1.S05: RdDqDqs FSM results: Left = 09, Right = 63, center = 36
N3.C1.D0.R1.S05: RxDqsDelay = 036
N3.C1.D0.R1.S06: RdDqDqs FSM results: Left = 04, Right = 63, center = 33
N3.C1.D0.R1.S06: RxDqsDelay = 033
N3.C1.D0.R1.S07: RdDqDqs FSM results: Left = 06, Right = 63, center = 34
N3.C1.D0.R1.S07: RxDqsDelay = 034
N3.C1.D0.R1.S08: RdDqDqs FSM results: Left = 05, Right = 63, center = 34
N3.C1.D0.R1.S08: RxDqsDelay = 034
N3.C1.D0.R1.S09: RdDqDqs FSM results: Left = 07, Right = 61, center = 34
N3.C1.D0.R1.S09: RxDqsDelay = 034
N3.C1.D0.R1.S10: RdDqDqs FSM results: Left = 06, Right = 63, center = 34
N3.C1.D0.R1.S10: RxDqsDelay = 034
N3.C1.D0.R1.S11: RdDqDqs FSM results: Left = 03, Right = 63, center = 33
N3.C1.D0.R1.S11: RxDqsDelay = 033
N3.C1.D0.R1.S12: RdDqDqs FSM results: Left = 06, Right = 63, center = 34
N3.C1.D0.R1.S12: RxDqsDelay = 034
N3.C1.D0.R1.S13: RdDqDqs FSM results: Left = 02, Right = 59, center = 30
N3.C1.D0.R1.S13: RxDqsDelay = 030
N3.C1.D0.R1.S14: RdDqDqs FSM results: Left = 06, Right = 58, center = 32
N3.C1.D0.R1.S14: RxDqsDelay = 032
N3.C1.D0.R1.S15: RdDqDqs FSM results: Left = 05, Right = 63, center = 34
N3.C1.D0.R1.S15: RxDqsDelay = 034
N3.C1.D0.R1.S16: RdDqDqs FSM results: Left = 05, Right = 60, center = 32
N3.C1.D0.R1.S16: RxDqsDelay = 032
N3.C1.D0.R1.S17: RdDqDqs FSM results: Left = 06, Right = 63, center = 34
N3.C1.D0.R1.S17: RxDqsDelay = 034
START_DATA_RX_DQS
N3.C1.R0.S00: PI = 28
N3.C1.R0.S01: PI = 34
N3.C1.R0.S02: PI = 32
N3.C1.R0.S03: PI = 35
N3.C1.R0.S04: PI = 34
N3.C1.R0.S05: PI = 36
N3.C1.R0.S06: PI = 33
N3.C1.R0.S07: PI = 34
N3.C1.R0.S08: PI = 34
N3.C1.R0.S09: PI = 34
N3.C1.R0.S10: PI = 34
N3.C1.R0.S11: PI = 32
N3.C1.R0.S12: PI = 34
N3.C1.R0.S13: PI = 30
N3.C1.R0.S14: PI = 32
N3.C1.R0.S15: PI = 34
N3.C1.R0.S16: PI = 32
N3.C1.R0.S17: PI = 34
N3.C1.R0.S00: PI = 28
N3.C1.R0.S01: PI = 34
N3.C1.R0.S02: PI = 32
N3.C1.R0.S03: PI = 35
N3.C1.R0.S04: PI = 34
N3.C1.R0.S05: PI = 36
N3.C1.R0.S06: PI = 33
N3.C1.R0.S07: PI = 34
N3.C1.R0.S08: PI = 34
N3.C1.R0.S09: PI = 34
N3.C1.R0.S10: PI = 34
N3.C1.R0.S11: PI = 32
N3.C1.R0.S12: PI = 34
N3.C1.R0.S13: PI = 30
N3.C1.R0.S14: PI = 32
N3.C1.R0.S15: PI = 34
N3.C1.R0.S16: PI = 32
N3.C1.R0.S17: PI = 34
N0: 
Get Tx Dq margins...
STOP_DATA_RX_DQS
N0: GetMargins: Level = 1, group = 12, mode = 0, scope = 3
N3.C2.D0.R0.S00: RdDqDqs FSM results: Left = 03, Right = 63, center = 33
N3.C2.D0.R0.S00: RxDqsDelay = 033
N3.C2.D0.R0.S01: RdDqDqs FSM results: Left = 05, Right = 63, center = 34
N3.C2.D0.R0.S01: RxDqsDelay = 034
N3.C2.D0.R0.S02: RdDqDqs FSM results: Left = 05, Right = 63, center = 34
N3.C2.D0.R0.S02: RxDqsDelay = 034
N3.C2.D0.R0.S03: RdDqDqs FSM results: Left = 08, Right = 63, center = 35
N6: 
Get Tx Dq margins...
N3.C2.D0.R0.S03: RxDqsDelay = 035
N6: GetMargins: Level = 1, group = 12, mode = 0, scope = 3
N3.C2.D0.R0.S04: RdDqDqs FSM results: Left = 02, Right = 63, center = 32
N3.C2.D0.R0.S04: RxDqsDelay = 032
N3.C2.D0.R0.S05: RdDqDqs FSM results: Left = 07, Right = 63, center = 35
N3.C2.D0.R0.S05: RxDqsDelay = 035
N3.C2.D0.R0.S06: RdDqDqs FSM results: Left = 07, Right = 63, center = 35
N3.C2.D0.R0.S06: RxDqsDelay = 035
N3.C2.D0.R0.S07: RdDqDqs FSM results: Left = 05, Right = 61, center = 33
N3.C2.D0.R0.S07: RxDqsDelay = 033
N3.C2.D0.R0.S08: RdDqDqs FSM results: Left = 10, Right = 63, center = 36
N3.C2.D0.R0.S08: RxDqsDelay = 036
N3.C2.D0.R0.S09: RdDqDqs FSM results: Left = 04, Right = 63, center = 33
N3.C2.D0.R0.S09: RxDqsDelay = 033
N3.C2.D0.R0.S10: RdDqDqs FSM results: Left = 07, Right = 63, center = 35
N3.C2.D0.R0.S10: RxDqsDelay = 035
N3.C2.D0.R0.S11: RdDqDqs FSM results: Left = 03, Right = 63, center = 33
N3.C2.D0.R0.S11: RxDqsDelay = 033
N3.C2.D0.R0.S12: RdDqDqs FSM results: Left = 05, Right = 63, center = 34
N3.C2.D0.R0.S12: RxDqsDelay = 034
N3.C2.D0.R0.S13: RdDqDqs FSM results: Left = 04, Right = 63, center = 33
N3.C2.D0.R0.S13: RxDqsDelay = 033
N3.C2.D0.R0.S14: RdDqDqs FSM results: Left = 09, Right = 63, center = 36
N3.C2.D0.R0.S14: RxDqsDelay = 036
N3.C2.D0.R0.S15: RdDqDqs FSM results: Left = 06, Right = 63, center = 34
N3.C2.D0.R0.S15: RxDqsDelay = 034
N3.C2.D0.R0.S16: RdDqDqs FSM results: Left = 04, Right = 59, center = 31
N3.C2.D0.R0.S16: RxDqsDelay = 031
N3.C2.D0.R0.S17: RdDqDqs FSM results: Left = 06, Right = 63, center = 34
N3.C2.D0.R0.S17: RxDqsDelay = 034
N3.C2.D0.R1.S00: RdDqDqs FSM results: Left = 03, Right = 63, center = 33
N3.C2.D0.R1.S00: RxDqsDelay = 033
N3.C2.D0.R1.S01: RdDqDqs FSM results: Left = 05, Right = 63, center = 34
N3.C2.D0.R1.S01: RxDqsDelay = 034
N3.C2.D0.R1.S02: RdDqDqs FSM results: Left = 05, Right = 63, center = 34
N3.C2.D0.R1.S02: RxDqsDelay = 034
N3.C2.D0.R1.S03: RdDqDqs FSM results: Left = 08, Right = 63, center = 35
N3.C2.D0.R1.S03: RxDqsDelay = 035
N3.C2.D0.R1.S04: RdDqDqs FSM results: Left = 02, Right = 63, center = 32
N3.C2.D0.R1.S04: RxDqsDelay = 032
N3.C2.D0.R1.S05: RdDqDqs FSM results: Left = 07, Right = 63, center = 35
N3.C2.D0.R1.S05: RxDqsDelay = 035
N3.C2.D0.R1.S06: RdDqDqs FSM results: Left = 07, Right = 63, center = 35
N3.C2.D0.R1.S06: RxDqsDelay = 035
N3.C2.D0.R1.S07: RdDqDqs FSM results: Left = 04, Right = 63, center = 33
N3.C2.D0.R1.S07: RxDqsDelay = 033
N3.C2.D0.R1.S08: RdDqDqs FSM results: Left = 09, Right = 63, center = 36
N3.C2.D0.R1.S08: RxDqsDelay = 036
N3.C2.D0.R1.S09: RdDqDqs FSM results: Left = 04, Right = 63, center = 33
N3.C2.D0.R1.S09: RxDqsDelay = 033
N3.C2.D0.R1.S10: RdDqDqs FSM results: Left = 07, Right = 63, center = 35
N3.C2.D0.R1.S10: RxDqsDelay = 035
N3.C2.D0.R1.S11: RdDqDqs FSM results: Left = 04, Right = 63, center = 33
N3.C2.D0.R1.S11: RxDqsDelay = 033
N3.C2.D0.R1.S12: RdDqDqs FSM results: Left = 06, Right = 63, center = 34
N3.C2.D0.R1.S12: RxDqsDelay = 034
N3.C2.D0.R1.S13: RdDqDqs FSM results: Left = 04, Right = 63, center = 33
N3.C2.D0.R1.S13: RxDqsDelay = 033
N3.C2.D0.R1.S14: RdDqDqs FSM results: Left = 08, Right = 63, center = 35
N3.C2.D0.R1.S14: RxDqsDelay = 035
N3.C2.D0.R1.S15: RdDqDqs FSM results: Left = 05, Right = 63, center = 34
N4: 
Get Tx Vref margins...
N3.C2.D0.R1.S15: RxDqsDelay = 034
N4: GetMargins: Level = 1, group = 14, mode = 0, scope = 3
N3.C2.D0.R1.S16: RdDqDqs FSM results: Left = 03, Right = 59, center = 31
N3.C2.D0.R1.S16: RxDqsDelay = 031
N3.C2.D0.R1.S17: RdDqDqs FSM results: Left = 07, Right = 63, center = 35
N3.C2.D0.R1.S17: RxDqsDelay = 035
START_DATA_RX_DQS
N3.C2.R0.S00: PI = 33
N3.C2.R0.S01: PI = 34
N3.C2.R0.S02: PI = 34
N3.C2.R0.S03: PI = 35
N3.C2.R0.S04: PI = 32
N3.C2.R0.S05: PI = 35
N3.C2.R0.S06: PI = 35
N3.C2.R0.S07: PI = 33
N3.C2.R0.S08: PI = 36
N3.C2.R0.S09: PI = 33
N3.C2.R0.S10: PI = 35
N3.C2.R0.S11: PI = 33
N3.C2.R0.S12: PI = 34
N3.C2.R0.S13: PI = 33
N3.C2.R0.S14: PI = 35
N3.C2.R0.S15: PI = 34
N3.C2.R0.S16: PI = 31
N3.C2.R0.S17: PI = 34
N3.C2.R0.S00: PI = 33
N3.C2.R0.S01: PI = 34
N3.C2.R0.S02: PI = 34
N3.C2.R0.S03: PI = 35
N3.C2.R0.S04: PI = 32
N3.C2.R0.S05: PI = 35
N3.C2.R0.S06: PI = 35
N3.C2.R0.S07: PI = 33
N3.C2.R0.S08: PI = 36
N3.C2.R0.S09: PI = 33
N3.C2.R0.S10: PI = 35
N3.C2.R0.S11: PI = 33
N3.C2.R0.S12: PI = 34
N3.C2.R0.S13: PI = 33
N3.C2.R0.S14: PI = 35
N3.C2.R0.S15: PI = 34
N3.C2.R0.S16: PI = 31
N3.C2.R0.S17: PI = 34
STOP_DATA_RX_DQS
N3.C3.D0.R0.S00: RdDqDqs FSM results: Left = 08, Right = 63, center = 35
N3.C3.D0.R0.S00: RxDqsDelay = 035
N3.C3.D0.R0.S01: RdDqDqs FSM results: Left = 05, Right = 61, center = 33
N3.C3.D0.R0.S01: RxDqsDelay = 033
N3.C3.D0.R0.S02: RdDqDqs FSM results: Left = 05, Right = 63, center = 34
N3.C3.D0.R0.S02: RxDqsDelay = 034
N3.C3.D0.R0.S03: RdDqDqs FSM results: Left = 06, Right = 63, center = 34
N3.C3.D0.R0.S03: RxDqsDelay = 034
N3.C3.D0.R0.S04: RdDqDqs FSM results: Left = 07, Right = 63, center = 35
N3.C3.D0.R0.S04: RxDqsDelay = 035
N3.C3.D0.R0.S05: RdDqDqs FSM results: Left = 05, Right = 63, center = 34
N3.C3.D0.R0.S05: RxDqsDelay = 034
N3.C3.D0.R0.S06: RdDqDqs FSM results: Left = 09, Right = 63, center = 36
N3.C3.D0.R0.S06: RxDqsDelay = 036
N3.C3.D0.R0.S07: RdDqDqs FSM results: Left = 06, Right = 63, center = 34
N3.C3.D0.R0.S07: RxDqsDelay = 034
N3.C3.D0.R0.S08: RdDqDqs FSM results: Left = 03, Right = 63, center = 33
N3.C3.D0.R0.S08: RxDqsDelay = 033
N3.C3.D0.R0.S09: RdDqDqs FSM results: Left = 07, Right = 63, center = 35
N3.C3.D0.R0.S09: RxDqsDelay = 035
N3.C3.D0.R0.S10: RdDqDqs FSM results: Left = 08, Right = 63, center = 35
N3.C3.D0.R0.S10: RxDqsDelay = 035
N3.C3.D0.R0.S11: RdDqDqs FSM results: Left = 04, Right = 63, center = 33
N3.C3.D0.R0.S11: RxDqsDelay = 033
N3.C3.D0.R0.S12: RdDqDqs FSM results: Left = 10, Right = 63, center = 36
N3.C3.D0.R0.S12: RxDqsDelay = 036
N3.C3.D0.R0.S13: RdDqDqs FSM results: Left = 06, Right = 63, center = 34
N3.C3.D0.R0.S13: RxDqsDelay = 034
N3.C3.D0.R0.S14: RdDqDqs FSM results: Left = 04, Right = 63, center = 33
N3.C3.D0.R0.S14: RxDqsDelay = 033
N3.C3.D0.R0.S15: RdDqDqs FSM results: Left = 08, Right = 63, center = 35
N3.C3.D0.R0.S15: RxDqsDelay = 035
N3.C3.D0.R0.S16: RdDqDqs FSM results: Left = 03, Right = 59, center = 31
N3.C3.D0.R0.S16: RxDqsDelay = 031
N3.C3.D0.R0.S17: RdDqDqs FSM results: Left = 03, Right = 63, center = 33
N3.C3.D0.R0.S17: RxDqsDelay = 033
N3.C3.D0.R1.S00: RdDqDqs FSM results: Left = 08, Right = 63, center = 35
N3.C3.D0.R1.S00: RxDqsDelay = 035
N3.C3.D0.R1.S01: RdDqDqs FSM results: Left = 05, Right = 63, center = 34
N3.C3.D0.R1.S01: RxDqsDelay = 034
N3.C3.D0.R1.S02: RdDqDqs FSM results: Left = 04, Right = 63, center = 33
N3.C3.D0.R1.S02: RxDqsDelay = 033
N3.C3.D0.R1.S03: RdDqDqs FSM results: Left = 08, Right = 63, center = 35
N3.C3.D0.R1.S03: RxDqsDelay = 035
N3.C3.D0.R1.S04: RdDqDqs FSM results: Left = 09, Right = 63, center = 36
N3.C3.D0.R1.S04: RxDqsDelay = 036
N3.C3.D0.R1.S05: RdDqDqs FSM results: Left = 05, Right = 63, center = 34
N3.C3.D0.R1.S05: RxDqsDelay = 034
N3.C3.D0.R1.S06: RdDqDqs FSM results: Left = 09, Right = 63, center = 36
N3.C3.D0.R1.S06: RxDqsDelay = 036
N3.C3.D0.R1.S07: RdDqDqs FSM results: Left = 05, Right = 63, center = 34
N3.C3.D0.R1.S07: RxDqsDelay = 034
N3.C3.D0.R1.S08: RdDqDqs FSM results: Left = 03, Right = 63, center = 33
N3.C3.D0.R1.S08: RxDqsDelay = 033
N3.C3.D0.R1.S09: RdDqDqs FSM results: Left = 07, Right = 63, center = 35
N3.C3.D0.R1.S09: RxDqsDelay = 035
N3.C3.D0.R1.S10: RdDqDqs FSM results: Left = 09, Right = 63, center = 36
N3.C3.D0.R1.S10: RxDqsDelay = 036
N3.C3.D0.R1.S11: RdDqDqs FSM results: Left = 04, Right = 63, center = 33
N3.C3.D0.R1.S11: RxDqsDelay = 033
N3.C3.D0.R1.S12: RdDqDqs FSM results: Left = 09, Right = 63, center = 36
N3.C3.D0.R1.S12: RxDqsDelay = 036
N3.C3.D0.R1.S13: RdDqDqs FSM results: Left = 06, Right = 63, center = 34
N3.C3.D0.R1.S13: RxDqsDelay = 034
N3.C3.D0.R1.S14: RdDqDqs FSM results: Left = 04, Right = 63, center = 33
N3.C3.D0.R1.S14: RxDqsDelay = 033
N3.C3.D0.R1.S15: RdDqDqs FSM results: Left = 07, Right = 63, center = 35
N3.C3.D0.R1.S15: RxDqsDelay = 035
N3.C3.D0.R1.S16: RdDqDqs FSM results: Left = 03, Right = 59, center = 31
N3.C3.D0.R1.S16: RxDqsDelay = 031
N3.C3.D0.R1.S17: RdDqDqs FSM results: Left = 03, Right = 63, center = 33
N3.C3.D0.R1.S17: RxDqsDelay = 033
START_DATA_RX_DQS
N3.C3.R0.S00: PI = 35
N3.C3.R0.S01: PI = 33
N3.C3.R0.S02: PI = 33
N3.C3.R0.S03: PI = 34
N3.C3.R0.S04: PI = 35
N3.C3.R0.S05: PI = 34
N3.C3.R0.S06: PI = 36
N3.C3.R0.S07: PI = 34
N3.C3.R0.S08: PI = 33
N3.C3.R0.S09: PI = 35
N3.C3.R0.S10: PI = 35
N3.C3.R0.S11: PI = 33
N3.C3.R0.S12: PI = 36
N3.C3.R0.S13: PI = 34
N3.C3.R0.S14: PI = 33
N3.C3.R0.S15: PI = 35
N3.C3.R0.S16: PI = 31
N3.C3.R0.S17: PI = 33
N3.C3.R0.S00: PI = 35
N3.C3.R0.S01: PI = 33
N3.C3.R0.S02: PI = 33
N3.C3.R0.S03: PI = 34
N3.C3.R0.S04: PI = 35
N3.C3.R0.S05: PI = 34
N3.C3.R0.S06: PI = 36
N3.C3.R0.S07: PI = 34
N3.C3.R0.S08: PI = 33
N3.C3.R0.S09: PI = 35
N3.C3.R0.S10: PI = 35
N3.C3.R0.S11: PI = 33
N3.C3.R0.S12: PI = 36
N3.C3.R0.S13: PI = 34
N3.C3.R0.S14: PI = 33
N3.C3.R0.S15: PI = 35
N3.C3.R0.S16: PI = 31
N3.C3.R0.S17: PI = 33
STOP_DATA_RX_DQS
N3: RunTrainStep: Final status = 0

END - Basic Read DQ/DQS Training       Time         3558 ms

START - Basic Receive Enable Training
N3.C0: QCRM debug: extraRcvEnLatency = 0
N3.C0: SettingForTrainingStep: RdCmd2RcvEnLatency = 10, RdPtrOffsetRcvEn = 4
N3.C1: QCRM debug: extraRcvEnLatency = 0
N3.C1: SettingForTrainingStep: RdCmd2RcvEnLatency = 10, RdPtrOffsetRcvEn = 4
N3.C2: QCRM debug: extraRcvEnLatency = 0
N3.C2: SettingForTrainingStep: RdCmd2RcvEnLatency = 10, RdPtrOffsetRcvEn = 4
N3.C3: QCRM debug: extraRcvEnLatency = 0
N3.C3: SettingForTrainingStep: RdCmd2RcvEnLatency = 10, RdPtrOffsetRcvEn = 4
N3.C0.D0.R0: RcvEnFine: Initial RdCmd2RcvEnLatency = 10, Initial RdPtrOffsetRcvEn = 4
N3.C0.D0.R0.S00: Rcv En Fine Value = 257
N3.C0.D0.R0.S01: Rcv En Fine Value = 363
N3.C0.D0.R0.S02: Rcv En Fine Value = 328
N3.C0.D0.R0.S03: Rcv En Fine Value = 312
N3.C0.D0.R0.S04: Rcv En Fine Value = 308
N3.C0.D0.R0.S05: Rcv En Fine Value = 327
N3.C0.D0.R0.S06: Rcv En Fine Value = 363
N3.C0.D0.R0.S07: Rcv En Fine Value = 261
N3.C0.D0.R0.S08: Rcv En Fine Value = 300
N3.C0.D0.R0.S09: Rcv En Fine Value = 381
N3.C0.D0.R0.S10: Rcv En Fine Value = 358
N3.C0.D0.R0.S11: Rcv En Fine Value = 333
N3.C0.D0.R0.S12: Rcv En Fine Value = 310
N3.C0.D0.R0.S13: Rcv En Fine Value = 306
N3.C0.D0.R0.S14: Rcv En Fine Value = 328
N3.C0.D0.R0.S15: Rcv En Fine Value = 362
N3.C0.D0.R0.S16: Rcv En Fine Value = 260
N3.C0.D0.R0.S17: Rcv En Fine Value = 297
N3.C0.D0.R0: Starting preamble search lower nibbles
N3.C0.D0.R0.S00: PI = 001, PtrOffset = 004
N3.C0.D0.R0.S01: PI = 043, PtrOffset = 005
N3.C0.D0.R0.S02: PI = 008, PtrOffset = 005
N3.C0.D0.R0.S03: PI = 056, PtrOffset = 004
N3.C0.D0.R0.S04: PI = 052, PtrOffset = 004
N3.C0.D0.R0.S05: PI = 007, PtrOffset = 005
N3.C0.D0.R0.S06: PI = 043, PtrOffset = 005
N3.C0.D0.R0.S07: PI = 005, PtrOffset = 004
N3.C0.D0.R0.S08: PI = 044, PtrOffset = 004
N3.C0.D0.R0.S00: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N3.C0.D0.R0.S01: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N3.C0.D0.R0.S02: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N3.C0.D0.R0.S03: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N3.C0.D0.R0.S04: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N3.C0.D0.R0.S05: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N3.C0.D0.R0.S06: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N3.C0.D0.R0.S07: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N3.C0.D0.R0.S08: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N3.C0.D0.R0.S00: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N3.C0.D0.R0.S01: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N3.C0.D0.R0.S02: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N3.C0.D0.R0.S03: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N3.C0.D0.R0.S04: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N3.C0.D0.R0.S05: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N3.C0.D0.R0.S06: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N3.C0.D0.R0.S07: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N3.C0.D0.R0.S08: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N3.C0.D0.R0.S00: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N0: 
Get Rx Vref margins...
N3.C0.D0.R0.S01: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N0: GetMargins: Level = 1, group = 13, mode = 0, scope = 3
N3.C0.D0.R0.S02: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N3.C0.D0.R0.S03: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N3.C0.D0.R0.S04: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N3.C0.D0.R0.S05: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N3.C0.D0.R0.S06: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N3.C0.D0.R0.S07: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N3.C0.D0.R0.S08: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N3.C0.D0.R0.S00: Preamble found at Latency = 008
N3.C0.D0.R0.S07: Preamble found at Latency = 008
N3.C0.D0.R0.S00: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N3.C0.D0.R0.S01: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N3.C0.D0.R0.S02: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N6: 
Get Rx Vref margins...
N3.C0.D0.R0.S03: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N6: GetMargins: Level = 1, group = 13, mode = 0, scope = 3
N3.C0.D0.R0.S04: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N3.C0.D0.R0.S05: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N3.C0.D0.R0.S06: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N3.C0.D0.R0.S07: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N3.C0.D0.R0.S08: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N3.C0.D0.R0.S01: Preamble found at Latency = 007
N3.C0.D0.R0.S02: Preamble found at Latency = 007
N3.C0.D0.R0.S03: Preamble found at Latency = 007
N3.C0.D0.R0.S04: Preamble found at Latency = 007
N3.C0.D0.R0.S05: Preamble found at Latency = 007
N3.C0.D0.R0.S06: Preamble found at Latency = 007
N3.C0.D0.R0.S08: Preamble found at Latency = 007
N3.C0.D0.R0.S00: Total Receive Enable Delay = 1313
N3.C0.D0.R0.S01: Total Receive Enable Delay = 1291
N3.C0.D0.R0.S02: Total Receive Enable Delay = 1256
N3.C0.D0.R0.S03: Total Receive Enable Delay = 1240
N3.C0.D0.R0.S04: Total Receive Enable Delay = 1236
N3.C0.D0.R0.S05: Total Receive Enable Delay = 1255
N3.C0.D0.R0.S06: Total Receive Enable Delay = 1291
N3.C0.D0.R0.S07: Total Receive Enable Delay = 1317
N3.C0.D0.R0.S08: Total Receive Enable Delay = 1228
N3.C0.D0.R0: Starting preamble search upper nibbles
N3.C0.D0.R0.S09: PI = 061, PtrOffset = 005
N3.C0.D0.R0.S10: PI = 038, PtrOffset = 005
N3.C0.D0.R0.S11: PI = 013, PtrOffset = 005
N3.C0.D0.R0.S12: PI = 054, PtrOffset = 004
N3.C0.D0.R0.S13: PI = 050, PtrOffset = 004
N3.C0.D0.R0.S14: PI = 008, PtrOffset = 005
N3.C0.D0.R0.S15: PI = 042, PtrOffset = 005
N3.C0.D0.R0.S16: PI = 004, PtrOffset = 004
N3.C0.D0.R0.S17: PI = 041, PtrOffset = 004
N3.C0.D0.R0.S09: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N3.C0.D0.R0.S10: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N4: 
 Time to do RMT patterns 15  is 4 seconds 
N3.C0.D0.R0.S11: RcvEnCoarse: Latency = 010, RdPtr Offset = 5

            RxDqLeft RxDqRight RxVLow RxVHigh TxDqLeft TxDqRight TxVLow TxVHigh
--------------------------------------------------------------------------------
N4.C0.D0.R0:   -20       19       -46       19      -18     17      -13      31
N4.C0.D0.R1:   -19       18       -46       19      -17     18      -12      31
N4.C0.D1.R0:   -19       17       -46       21      -16     16      -14      31
N4.C0.D1.R1:   -18       18       -46       21      -16     15      -14      31
N4.C1.D0.R0:   -18       17       -46       19      -17     16      -13      31
N4.C1.D0.R1:   -18       17       -46       19      -16     17      -12      31
N4.C1.D1.R0:   -17       15       -46       20      -15     14      -12      31
N4.C1.D1.R1:   -17       13       -46       20      -15     15      -14      31
N4.C2.D0.R0:   -18       17       -46       18      -17     18      -13      31
N4.C2.D0.R1:   -18       20       -46       19      -18     17      -13      31
N4.C2.D1.R0:   -17       17       -46       19      -16     16      -15      31
N4.C2.D1.R1:   -17       15       -46       19      -16     16      -15      31
N4.C3.D0.R0:   -19       18       -46       20      -17     17      -12      31
N4.C3.D0.R1:   -20       20       -46       21      -17     18      -12      31
N4.C3.D1.R0:   -16       17       -46       20      -15     15      -13      31
N4.C3.D1.R1:   -16       17       -46       21      -15     15      -12      31
STOP_RMT_N4
N3.C0.D0.R0.S12: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N4: GetAllRankMargins time            4577 ms
N3.C0.D0.R0.S13: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N4: 
Total DDR trainings latency = 203189 ms
N3.C0.D0.R0.S14: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N5: PostVmseTraining
N3.C0.D0.R0.S15: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N5.C0: PostVmseTraining
N3.C0.D0.R0.S16: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N5.C0: PostVMSE Training VMSE Health Check Passed
N3.C0.D0.R0.S17: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N5.C1: PostVmseTraining
N3.C0.D0.R0.S09: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N5.C2: PostVMSE Training VMSE Health Check Passed
N3.C0.D0.R0.S10: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N5: PreDdrTraining
N3.C0.D0.R0.S11: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N5: PreDdrTraining[QCRM=OFF]
N3.C0.D0.R0.S12: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N5.C0.D0: CheckRankPopLocal: dimmPresent: 1, numRanks = 2
N3.C0.D0.R0.S13: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N5.C0.D0.R0: CheckRankPopLocal: mapOut: 0, enabled = 1
N3.C0.D0.R0.S14: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N5.C0.D0.R1: CheckRankPopLocal: mapOut: 0, enabled = 1
N3.C0.D0.R0.S15: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N5.C0.D1: CheckRankPopLocal: dimmPresent: 0, numRanks = 0
N3.C0.D0.R0.S16: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N5.C0.D2: CheckRankPopLocal: dimmPresent: 0, numRanks = 0
N3.C0.D0.R0.S17: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N5.C0.D0: CheckRankPopLocal: amap: 0x00000000
N3.C0.D0.R0.S09: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N5.C0.D1: CheckRankPopLocal: amap: 0x00000000
N3.C0.D0.R0.S10: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N5.C0.D2: CheckRankPopLocal: amap: 0x00000000
N3.C0.D0.R0.S11: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N5.C1.D0: CheckRankPopLocal: dimmPresent: 1, numRanks = 2
N3.C0.D0.R0.S12: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N5.C1.D0.R0: CheckRankPopLocal: mapOut: 0, enabled = 1
N3.C0.D0.R0.S13: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N5.C1.D0.R1: CheckRankPopLocal: mapOut: 0, enabled = 1
N3.C0.D0.R0.S14: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N5.C1.D1: CheckRankPopLocal: dimmPresent: 0, numRanks = 0
N3.C0.D0.R0.S15: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N5.C1.D2: CheckRankPopLocal: dimmPresent: 0, numRanks = 0
N3.C0.D0.R0.S16: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N5.C1.D0: CheckRankPopLocal: amap: 0x00000000
N3.C0.D0.R0.S17: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N5.C1.D1: CheckRankPopLocal: amap: 0x00000000
N3.C0.D0.R0.S16: Preamble found at Latency = 008
N5.C1.D2: CheckRankPopLocal: amap: 0x00000000
N3.C0.D0.R0.S09: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N5.C2.D0: CheckRankPopLocal: dimmPresent: 1, numRanks = 2
N3.C0.D0.R0.S10: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N5.C2.D0.R0: CheckRankPopLocal: mapOut: 0, enabled = 1
N3.C0.D0.R0.S11: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N5.C2.D0.R1: CheckRankPopLocal: mapOut: 0, enabled = 1
N3.C0.D0.R0.S12: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N5.C2.D1: CheckRankPopLocal: dimmPresent: 0, numRanks = 0
N3.C0.D0.R0.S13: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N5.C2.D2: CheckRankPopLocal: dimmPresent: 0, numRanks = 0
N3.C0.D0.R0.S14: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N5.C2.D0: CheckRankPopLocal: amap: 0x00000000
N3.C0.D0.R0.S15: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N5.C2.D1: CheckRankPopLocal: amap: 0x00000000
N3.C0.D0.R0.S16: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N5.C2.D2: CheckRankPopLocal: amap: 0x00000000
N3.C0.D0.R0.S17: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N5.C3.D0: CheckRankPopLocal: dimmPresent: 1, numRanks = 2
N3.C0.D0.R0.S09: Preamble found at Latency = 007
N5.C3.D0.R0: CheckRankPopLocal: mapOut: 0, enabled = 1
N3.C0.D0.R0.S10: Preamble found at Latency = 007
N5.C3.D0.R1: CheckRankPopLocal: mapOut: 0, enabled = 1
N3.C0.D0.R0.S11: Preamble found at Latency = 007
N5.C3.D1: CheckRankPopLocal: dimmPresent: 0, numRanks = 0
N3.C0.D0.R0.S12: Preamble found at Latency = 007
N5.C3.D2: CheckRankPopLocal: dimmPresent: 0, numRanks = 0
N3.C0.D0.R0.S13: Preamble found at Latency = 007
N5.C3.D0: CheckRankPopLocal: amap: 0x00000000
N3.C0.D0.R0.S14: Preamble found at Latency = 007
N5.C3.D1: CheckRankPopLocal: amap: 0x00000000
N3.C0.D0.R0.S15: Preamble found at Latency = 007
N5.C3.D2: CheckRankPopLocal: amap: 0x00000000
N3.C0.D0.R0.S17: Preamble found at Latency = 007
N5.C0: JCK cmd timing = 3N
N0: 
Get Tx Vref margins...
N3.C0.D0.R0: Preamble found for all upper nibbles, adjusting Pi, Offset to center into preamble
N5.C0: RdCmd2DataValidLatency = 20, (dlyFrmS = 15, clEff = 10, earlyCas = 0, selNTiming = 2)
N0: GetMargins: Level = 1, group = 14, mode = 0, scope = 3
N3.C0.D0.R0.S09: Total Receive Enable Delay = 1309
N5.C0: CLK0_CFG: 0x000FFF10
N3.C0.D0.R0.S10: Total Receive Enable Delay = 1286
N5.C0: DDR_RANKCTL: 0x000FEE40
N3.C0.D0.R0.S11: Total Receive Enable Delay = 1261
N5.C0: MCODT = 0 ( 50 ohms)
N3.C0.D0.R0.S12: Total Receive Enable Delay = 1238
N5.C0.D0.R0: Rtt_wr = 0, Rtt_nom = 60
N3.C0.D0.R0.S13: Total Receive Enable Delay = 1234
N5.C0.D0.R1: Rtt_wr = 0, Rtt_nom = 60
N3.C0.D0.R0.S14: Total Receive Enable Delay = 1256
N5.C0: ODTRDCTL00 = 0x00000000
N3.C0.D0.R0.S15: Total Receive Enable Delay = 1290
N5.C0: ODTRDCTL01 = 0x00000000
N3.C0.D0.R0.S16: Total Receive Enable Delay = 1316
N5.C0: ODTWRCTL00 = 0x00000081
N3.C0.D0.R0.S17: Total Receive Enable Delay = 1225
N5.C0: ODTWRCTL01 = 0x00000000
N6: 
Get Tx Vref margins...
N3.C0.D0.R1: RcvEnFine: Initial RdCmd2RcvEnLatency = 10, Initial RdPtrOffsetRcvEn = 4
N5.C1: RdCmd2DataValidLatency = 20, (dlyFrmS = 15, clEff = 10, earlyCas = 0, selNTiming = 2)
N6: GetMargins: Level = 1, group = 14, mode = 0, scope = 3
N3.C0.D0.R1.S00: Rcv En Fine Value = 256
N5.C1: CLK0_CFG: 0x000FF110
N3.C0.D0.R1.S01: Rcv En Fine Value = 360
N5.C1: DDR_RANKCTL: 0x000FEE40
N3.C0.D0.R1.S02: Rcv En Fine Value = 330
N5.C1: MCODT = 0 ( 50 ohms)
N3.C0.D0.R1.S03: Rcv En Fine Value = 311
N5.C1.D0.R0: Rtt_wr = 0, Rtt_nom = 60
N3.C0.D0.R1.S04: Rcv En Fine Value = 307
N5.C1.D0.R1: Rtt_wr = 0, Rtt_nom = 60
N3.C0.D0.R1.S05: Rcv En Fine Value = 329
N5.C1: ODTRDCTL00 = 0x00000000
N3.C0.D0.R1.S06: Rcv En Fine Value = 362
N5.C1: ODTRDCTL01 = 0x00000000
N3.C0.D0.R1.S07: Rcv En Fine Value = 261
N5.C1: ODTWRCTL00 = 0x00000081
N3.C0.D0.R1.S08: Rcv En Fine Value = 300
N5.C1: ODTWRCTL01 = 0x00000000
N3.C0.D0.R1.S09: Rcv En Fine Value = 380
N5.C2: JCK cmd timing = 3N
N3.C0.D0.R1.S10: Rcv En Fine Value = 360
N5.C2: RdCmd2DataValidLatency = 20, (dlyFrmS = 15, clEff = 10, earlyCas = 0, selNTiming = 2)
N3.C0.D0.R1.S11: Rcv En Fine Value = 329
N5.C2: CLK0_CFG: 0x000FFF10
N3.C0.D0.R1.S12: Rcv En Fine Value = 310
N5.C2: DDR_RANKCTL: 0x000FEE40
N3.C0.D0.R1.S13: Rcv En Fine Value = 307
N5.C2: MCODT = 0 ( 50 ohms)
N3.C0.D0.R1.S14: Rcv En Fine Value = 328
N5.C2.D0.R0: Rtt_wr = 0, Rtt_nom = 60
N3.C0.D0.R1.S15: Rcv En Fine Value = 363
N5.C2.D0.R1: Rtt_wr = 0, Rtt_nom = 60
N3.C0.D0.R1.S16: Rcv En Fine Value = 262
N5.C2: ODTRDCTL00 = 0x00000000
N3.C0.D0.R1.S17: Rcv En Fine Value = 297
N5.C2: ODTRDCTL01 = 0x00000000
N3.C0.D0.R1: Starting preamble search lower nibbles
N5.C2: ODTWRCTL00 = 0x00000081
N3.C0.D0.R1.S00: PI = 000, PtrOffset = 004
N5.C2: ODTWRCTL01 = 0x00000000
N3.C0.D0.R1.S01: PI = 040, PtrOffset = 005
N5.C3: RdCmd2DataValidLatency = 20, (dlyFrmS = 15, clEff = 10, earlyCas = 0, selNTiming = 2)
N3.C0.D0.R1.S02: PI = 010, PtrOffset = 005
N5.C3: CLK0_CFG: 0x000FF110
N3.C0.D0.R1.S03: PI = 055, PtrOffset = 004
N5.C3: DDR_RANKCTL: 0x000FEE40
N3.C0.D0.R1.S04: PI = 051, PtrOffset = 004
N5.C3: MCODT = 0 ( 50 ohms)
N3.C0.D0.R1.S05: PI = 009, PtrOffset = 005
N5.C3.D0.R0: Rtt_wr = 0, Rtt_nom = 60
N3.C0.D0.R1.S06: PI = 042, PtrOffset = 005
N5.C3.D0.R1: Rtt_wr = 0, Rtt_nom = 60
N3.C0.D0.R1.S07: PI = 005, PtrOffset = 004
N5.C3: ODTRDCTL00 = 0x00000000
N3.C0.D0.R1.S08: PI = 044, PtrOffset = 004
N5.C3: ODTRDCTL01 = 0x00000000
N3.C0.D0.R1.S00: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N5.C3: ODTWRCTL00 = 0x00000081
N3.C0.D0.R1.S01: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N5.C3: ODTWRCTL01 = 0x00000000
N3.C0.D0.R1.S02: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N5.C0.D0: PreDdrTraining: Program dimmmtr 0xC5051
N3.C0.D0.R1.S03: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N5.C1.D0: PreDdrTraining: Program dimmmtr 0xC5051
N3.C0.D0.R1.S04: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N5.C2.D0: PreDdrTraining: Program dimmmtr 0xC5051
N3.C0.D0.R1.S05: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N5.C3.D0: PreDdrTraining: Program dimmmtr 0xC5051
N3.C0.D0.R1.S06: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N5: InitializeDdrioForUse
N3.C0.D0.R1.S07: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N5: SetupJckForBL: setting BL to 8
N3.C0.D0.R1.S08: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N5.C0: ODTTIMCTL (INIT RELAX) rdwidth = 10 rddly = 0 wrwidth = 8 wrdly = 0
N3.C0.D0.R1.S00: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N5.C1: ODTTIMCTL (INIT RELAX) rdwidth = 10 rddly = 0 wrwidth = 8 wrdly = 0
N3.C0.D0.R1.S01: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N5.C2: ODTTIMCTL (INIT RELAX) rdwidth = 10 rddly = 0 wrwidth = 8 wrdly = 0
N3.C0.D0.R1.S02: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N5.C3: ODTTIMCTL (INIT RELAX) rdwidth = 10 rddly = 0 wrwidth = 8 wrdly = 0
N3.C0.D0.R1.S03: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N5: JckDdrTraining
N3.C0.D0.R1.S04: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N5: InitializeDdrioForTraining: QCRM Disabled
N3.C0.D0.R1.S05: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N5.C0: InitializeDdrioForTraining: cleff = 10
N3.C0.D0.R1.S06: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N5.C0: InitializeDdrioForTraining: cwleff = 8
N3.C0.D0.R1.S07: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N5.C0: InitializeDdrioForTraining: initial ddrInitIndexRx = 4 ddrInitIndexTx = 2
N3.C0.D0.R1.S08: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N5.C0: InitializeDdrioForTraining: initial RdCmd2RcvEnLatency = 5
N3.C0.D0.R1.S00: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N5.C0: InitializeDdrioForTraining: initial RdPtrOffsetRcvEn = 4
N3.C0.D0.R1.S01: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N5.C0: InitializeDdrioForTraining: initial rkrdptroffsetrcvenb = 6
N3.C0.D0.R1.S02: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N5.C0: InitializeDdrioForTraining: initial rkrdptroffsetdrvenrcvenb = 5
N3.C0.D0.R1.S03: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N5.C0: InitializeDdrioForTraining: initial WrCmd2DqsStartLatency = 4
N3.C0.D0.R1.S04: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N5.C0: InitializeDdrioForTraining: initial RdPtrOffsetDqs = 10
N3.C0.D0.R1.S05: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N5.C0: InitializeDdrioForTraining: initial RdCmd2RcvEnLatency = 5
N3.C0.D0.R1.S06: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N5.C0: InitializeDdrioForTraining: initial WrCmd2DqsStartLatency = 4
N3.C0.D0.R1.S07: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N5.C0: InitializeDdrioForTraining: initial RdPtrOffsetRcvEn = 4
N3.C0.D0.R1.S08: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N5.C0: InitializeDdrioForTraining: initial RdPtrOffsetDqs = 6
N3.C0.D0.R1.S00: Preamble found at Latency = 008
N5.C0: InitializeDdrioForTraining: initial RdPtrOffsetDq = 5
N3.C0.D0.R1.S07: Preamble found at Latency = 008
N5.C1: InitializeDdrioForTraining: cleff = 10
N3.C0.D0.R1.S00: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N5.C1: InitializeDdrioForTraining: cwleff = 8
N3.C0.D0.R1.S01: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N5.C1: InitializeDdrioForTraining: initial ddrInitIndexRx = 4 ddrInitIndexTx = 2
N3.C0.D0.R1.S02: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N5.C1: InitializeDdrioForTraining: initial RdCmd2RcvEnLatency = 5
N3.C0.D0.R1.S03: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N5.C1: InitializeDdrioForTraining: initial RdPtrOffsetRcvEn = 4
N3.C0.D0.R1.S04: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N5.C1: InitializeDdrioForTraining: initial rkrdptroffsetrcvenb = 6
N3.C0.D0.R1.S05: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N5.C1: InitializeDdrioForTraining: initial rkrdptroffsetdrvenrcvenb = 5
N3.C0.D0.R1.S06: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N5.C1: InitializeDdrioForTraining: initial WrCmd2DqsStartLatency = 4
N3.C0.D0.R1.S07: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N5.C1: InitializeDdrioForTraining: initial RdPtrOffsetDqs = 10
N3.C0.D0.R1.S08: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N5.C1: InitializeDdrioForTraining: initial RdCmd2RcvEnLatency = 5
N3.C0.D0.R1.S01: Preamble found at Latency = 007
N5.C1: InitializeDdrioForTraining: initial WrCmd2DqsStartLatency = 4
N3.C0.D0.R1.S02: Preamble found at Latency = 007
N5.C1: InitializeDdrioForTraining: initial RdPtrOffsetRcvEn = 4
N3.C0.D0.R1.S03: Preamble found at Latency = 007
N5.C1: InitializeDdrioForTraining: initial RdPtrOffsetDqs = 6
N3.C0.D0.R1.S04: Preamble found at Latency = 007
N5.C1: InitializeDdrioForTraining: initial RdPtrOffsetDq = 5
N3.C0.D0.R1.S05: Preamble found at Latency = 007
N5.C2: InitializeDdrioForTraining: cleff = 10
N3.C0.D0.R1.S06: Preamble found at Latency = 007
N5.C2: InitializeDdrioForTraining: cwleff = 8
N3.C0.D0.R1.S08: Preamble found at Latency = 007
N5.C2: InitializeDdrioForTraining: initial ddrInitIndexRx = 4 ddrInitIndexTx = 2
N3.C0.D0.R1.S00: Total Receive Enable Delay = 1312
N5.C2: InitializeDdrioForTraining: initial RdCmd2RcvEnLatency = 5
N3.C0.D0.R1.S01: Total Receive Enable Delay = 1288
N5.C2: InitializeDdrioForTraining: initial RdPtrOffsetRcvEn = 4
N3.C0.D0.R1.S02: Total Receive Enable Delay = 1258
N5.C2: InitializeDdrioForTraining: initial rkrdptroffsetrcvenb = 6
N3.C0.D0.R1.S03: Total Receive Enable Delay = 1239
N5.C2: InitializeDdrioForTraining: initial rkrdptroffsetdrvenrcvenb = 5
N3.C0.D0.R1.S04: Total Receive Enable Delay = 1235
N5.C2: InitializeDdrioForTraining: initial WrCmd2DqsStartLatency = 4
N3.C0.D0.R1.S05: Total Receive Enable Delay = 1257
N5.C2: InitializeDdrioForTraining: initial RdPtrOffsetDqs = 10
N3.C0.D0.R1.S06: Total Receive Enable Delay = 1290
N5.C2: InitializeDdrioForTraining: initial RdCmd2RcvEnLatency = 5
N3.C0.D0.R1.S07: Total Receive Enable Delay = 1317
N5.C2: InitializeDdrioForTraining: initial WrCmd2DqsStartLatency = 4
N3.C0.D0.R1.S08: Total Receive Enable Delay = 1228
N5.C2: InitializeDdrioForTraining: initial RdPtrOffsetRcvEn = 4
N3.C0.D0.R1: Starting preamble search upper nibbles
N5.C2: InitializeDdrioForTraining: initial RdPtrOffsetDqs = 6
N3.C0.D0.R1.S09: PI = 060, PtrOffset = 005
N5.C2: InitializeDdrioForTraining: initial RdPtrOffsetDq = 5
N3.C0.D0.R1.S10: PI = 040, PtrOffset = 005
N5.C3: InitializeDdrioForTraining: cleff = 10
N3.C0.D0.R1.S11: PI = 009, PtrOffset = 005
N5.C3: InitializeDdrioForTraining: cwleff = 8
N3.C0.D0.R1.S12: PI = 054, PtrOffset = 004
N5.C3: InitializeDdrioForTraining: initial ddrInitIndexRx = 4 ddrInitIndexTx = 2
N3.C0.D0.R1.S13: PI = 051, PtrOffset = 004
N5.C3: InitializeDdrioForTraining: initial RdCmd2RcvEnLatency = 5
N3.C0.D0.R1.S14: PI = 008, PtrOffset = 005
N5.C3: InitializeDdrioForTraining: initial RdPtrOffsetRcvEn = 4
N3.C0.D0.R1.S15: PI = 043, PtrOffset = 005
N5.C3: InitializeDdrioForTraining: initial rkrdptroffsetrcvenb = 6
N3.C0.D0.R1.S16: PI = 006, PtrOffset = 004
N5.C3: InitializeDdrioForTraining: initial rkrdptroffsetdrvenrcvenb = 5
N3.C0.D0.R1.S17: PI = 041, PtrOffset = 004
N5.C3: InitializeDdrioForTraining: initial WrCmd2DqsStartLatency = 4
N3.C0.D0.R1.S09: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N5.C3: InitializeDdrioForTraining: initial RdPtrOffsetDqs = 10
N3.C0.D0.R1.S10: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N5.C3: InitializeDdrioForTraining: initial RdCmd2RcvEnLatency = 5
N3.C0.D0.R1.S11: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N5.C3: InitializeDdrioForTraining: initial WrCmd2DqsStartLatency = 4
N3.C0.D0.R1.S12: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N5.C3: InitializeDdrioForTraining: initial RdPtrOffsetRcvEn = 4
N3.C0.D0.R1.S13: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N5.C3: InitializeDdrioForTraining: initial RdPtrOffsetDqs = 6
N3.C0.D0.R1.S14: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N5.C3: InitializeDdrioForTraining: initial RdPtrOffsetDq = 5
N3.C0.D0.R1.S15: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N5: DdrClockStopWa
N3.C0.D0.R1.S16: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N5: JckSetOdtRelaxTiming:
N3.C0.D0.R1.S17: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N5.C0: ODTTIMCTL (INIT RELAX) rdwidth = 10 rddly = 0 wrwidth = 8 wrdly = 0
N3.C0.D0.R1.S09: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N5.C0.S00: DDRIOHSIODATA0_LATCTL1 = 08040804
N3.C0.D0.R1.S10: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N5.C0.S01: DDRIOHSIODATA0_LATCTL1 = 08040804
N3.C0.D0.R1.S11: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N5.C0.S02: DDRIOHSIODATA0_LATCTL1 = 08040804
N3.C0.D0.R1.S12: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N5.C0.S03: DDRIOHSIODATA0_LATCTL1 = 08040804
N3.C0.D0.R1.S13: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N5.C0.S04: DDRIOHSIODATA0_LATCTL1 = 08040804
N3.C0.D0.R1.S14: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N5.C0.S05: DDRIOHSIODATA0_LATCTL1 = 08040804
N3.C0.D0.R1.S15: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N5.C0.S06: DDRIOHSIODATA0_LATCTL1 = 08040804
N3.C0.D0.R1.S16: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N5.C0.S07: DDRIOHSIODATA0_LATCTL1 = 08040804
N3.C0.D0.R1.S17: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N5.C0.S08: DDRIOHSIODATA0_LATCTL1 = 08040804
N3.C0.D0.R1.S09: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N5.C1: ODTTIMCTL (INIT RELAX) rdwidth = 10 rddly = 0 wrwidth = 8 wrdly = 0
N3.C0.D0.R1.S10: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N5.C1.S00: DDRIOHSIODATA0_LATCTL1 = 08040804
N3.C0.D0.R1.S11: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N5.C1.S01: DDRIOHSIODATA0_LATCTL1 = 08040804
N3.C0.D0.R1.S12: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N5.C1.S02: DDRIOHSIODATA0_LATCTL1 = 08040804
N3.C0.D0.R1.S13: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N5.C1.S03: DDRIOHSIODATA0_LATCTL1 = 08040804
N3.C0.D0.R1.S14: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N5.C1.S04: DDRIOHSIODATA0_LATCTL1 = 08040804
N3.C0.D0.R1.S15: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N5.C1.S05: DDRIOHSIODATA0_LATCTL1 = 08040804
N3.C0.D0.R1.S16: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N5.C1.S06: DDRIOHSIODATA0_LATCTL1 = 08040804
N3.C0.D0.R1.S17: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N5.C1.S07: DDRIOHSIODATA0_LATCTL1 = 08040804
N3.C0.D0.R1.S16: Preamble found at Latency = 008
N5.C1.S08: DDRIOHSIODATA0_LATCTL1 = 08040804
N3.C0.D0.R1.S09: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N5.C2: ODTTIMCTL (INIT RELAX) rdwidth = 10 rddly = 0 wrwidth = 8 wrdly = 0
N3.C0.D0.R1.S10: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N5.C2.S00: DDRIOHSIODATA0_LATCTL1 = 08040804
N3.C0.D0.R1.S11: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N5.C2.S01: DDRIOHSIODATA0_LATCTL1 = 08040804
N3.C0.D0.R1.S12: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N5.C2.S02: DDRIOHSIODATA0_LATCTL1 = 08040804
N3.C0.D0.R1.S13: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N5.C2.S03: DDRIOHSIODATA0_LATCTL1 = 08040804
N3.C0.D0.R1.S14: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N5.C2.S04: DDRIOHSIODATA0_LATCTL1 = 08040804
N3.C0.D0.R1.S15: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N5.C2.S05: DDRIOHSIODATA0_LATCTL1 = 08040804
N3.C0.D0.R1.S16: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N5.C2.S06: DDRIOHSIODATA0_LATCTL1 = 08040804
N3.C0.D0.R1.S17: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N5.C2.S07: DDRIOHSIODATA0_LATCTL1 = 08040804
N3.C0.D0.R1.S09: Preamble found at Latency = 007
N5.C2.S08: DDRIOHSIODATA0_LATCTL1 = 08040804
N3.C0.D0.R1.S10: Preamble found at Latency = 007
N5.C3: ODTTIMCTL (INIT RELAX) rdwidth = 10 rddly = 0 wrwidth = 8 wrdly = 0
N3.C0.D0.R1.S11: Preamble found at Latency = 007
N5.C3.S00: DDRIOHSIODATA0_LATCTL1 = 08040804
N3.C0.D0.R1.S12: Preamble found at Latency = 007
N5.C3.S01: DDRIOHSIODATA0_LATCTL1 = 08040804
N3.C0.D0.R1.S13: Preamble found at Latency = 007
N5.C3.S02: DDRIOHSIODATA0_LATCTL1 = 08040804
N3.C0.D0.R1.S14: Preamble found at Latency = 007
N5.C3.S03: DDRIOHSIODATA0_LATCTL1 = 08040804
N3.C0.D0.R1.S15: Preamble found at Latency = 007
N5.C3.S04: DDRIOHSIODATA0_LATCTL1 = 08040804
N3.C0.D0.R1.S17: Preamble found at Latency = 007
N5.C3.S05: DDRIOHSIODATA0_LATCTL1 = 08040804
N3.C0.D0.R1: Preamble found for all upper nibbles, adjusting Pi, Offset to center into preamble
N5.C3.S06: DDRIOHSIODATA0_LATCTL1 = 08040804
N3.C0.D0.R1.S09: Total Receive Enable Delay = 1308
N5.C3.S07: DDRIOHSIODATA0_LATCTL1 = 08040804
N3.C0.D0.R1.S10: Total Receive Enable Delay = 1288
N5.C3.S08: DDRIOHSIODATA0_LATCTL1 = 08040804
N3.C0.D0.R1.S11: Total Receive Enable Delay = 1257

START - Early Command Training
N3.C0.D0.R1.S12: Total Receive Enable Delay = 1238
N5.C0: DDRIOHSIODATA0_LATCTL1 = 08040804
N3.C0.D0.R1.S13: Total Receive Enable Delay = 1235
N5.C0: RdCmd2DataValidLatency = 20, (dlyFrmS = 15, clEff = 10, earlyCas = 0, selNTiming = 2)
N3.C0.D0.R1.S14: Total Receive Enable Delay = 1256
N5.C0: SettingForTrainingStep: RdCmd2RcvEnLatency = 5
N3.C0.D0.R1.S15: Total Receive Enable Delay = 1291
N5.C0: SettingForTrainingStep: Programming 7 tick initial value to CTL signals
N3.C0.D0.R1.S16: Total Receive Enable Delay = 1318
N5.C1: DDRIOHSIODATA0_LATCTL1 = 08040804
N3.C0.D0.R1.S17: Total Receive Enable Delay = 1225
N5.C1: RdCmd2DataValidLatency = 20, (dlyFrmS = 15, clEff = 10, earlyCas = 0, selNTiming = 2)
START_DATA_REC_EN
N5.C1: SettingForTrainingStep: RdCmd2RcvEnLatency = 5
N3.C0.S00: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N5.C1: SettingForTrainingStep: Programming 10 tick initial value to CTL signals
N3.C0.S01: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N5.C2: DDRIOHSIODATA0_LATCTL1 = 08040804
N3.C0.S02: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 5
N5.C2: RdCmd2DataValidLatency = 20, (dlyFrmS = 15, clEff = 10, earlyCas = 0, selNTiming = 2)
N3.C0.S03: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 5
N5.C2: SettingForTrainingStep: RdCmd2RcvEnLatency = 5
N3.C0.S04: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 5
N5.C2: SettingForTrainingStep: Programming 7 tick initial value to CTL signals
N3.C0.S05: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 5
N5.C3: DDRIOHSIODATA0_LATCTL1 = 08040804
N3.C0.S06: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N5.C3: RdCmd2DataValidLatency = 20, (dlyFrmS = 15, clEff = 10, earlyCas = 0, selNTiming = 2)
N3.C0.S07: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N5.C3: SettingForTrainingStep: RdCmd2RcvEnLatency = 5
N3.C0.S08: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 5
N5.C3: SettingForTrainingStep: Programming 10 tick initial value to CTL signals
N0: 
 Time to do RMT patterns 15  is 4 seconds 
N3.C0.S09: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N5: FSM Basic Clock Training

            RxDqLeft RxDqRight RxVLow RxVHigh TxDqLeft TxDqRight TxVLow TxVHigh
--------------------------------------------------------------------------------
N0.C0.D0.R0:   -22       20       -28       48      -22     24      -30      27
N0.C0.D0.R1:   -22       23       -26       29      -23     23      -29      28
N0.C0.D1.R0:   -21       20       -27       30      -21     21      -31      29
N0.C0.D1.R1:   -20       19       -26       29      -21     21      -31      29
N0.C1.D0.R0:   -22       23       -26       30      -23     23      -28      27
N0.C1.D0.R1:   -22       23       -27       29      -23     23      -28      26
N0.C1.D1.R0:   -20       18       -27       27      -21     21      -28      27
N0.C1.D1.R1:   -20       21       -26       28      -21     21      -30      28
N0.C2.D0.R0:   -21       24       -27       33      -23     24      -30      28
N0.C2.D0.R1:   -21       22       -28       33      -23     24      -30      28
N0.C2.D1.R0:   -20       18       -28       30      -21     21      -29      28
N0.C2.D1.R1:   -20       20       -28       29      -21     21      -29      27
N0.C3.D0.R0:   -23       20       -29       32      -23     23      -26      28
N0.C3.D0.R1:   -23       23       -28       34      -22     23      -26      28
N0.C3.D1.R0:   -22       23       -25       29      -20     21      -28      29
N0.C3.D1.R1:   -22       21       -26       27      -21     21      -28      28
STOP_RMT_N0
N3.C0.S10: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N5.C0: JCK cmd timing = 1N
N6: 
 Time to do RMT patterns 15  is 5 seconds 
N0: GetAllRankMargins time            5017 ms
N3.C0.S11: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 5
N5.C0: RdCmd2DataValidLatency = 21, (dlyFrmS = 15, clEff = 10, earlyCas = 0, selNTiming = 0)

            RxDqLeft RxDqRight RxVLow RxVHigh TxDqLeft TxDqRight TxVLow TxVHigh
--------------------------------------------------------------------------------
N6.C0.D0.R0:   -21       21       -24       30      -22     23      -30      31
N6.C0.D0.R1:   -21       21       -24       30      -22     23      -28      31
N6.C0.D1.R0:   -20       18       -25       29      -20     22      -28      31
N6.C0.D1.R1:   -20       21       -25       30      -21     21      -29      31
N6.C1.D0.R0:   -22       18       -27       31      -22     21      -27      31
N6.C1.D0.R1:   -22       21       -26       31      -21     22      -26      31
N6.C1.D1.R0:   -21       21       -25       29      -20     19      -29      31
N6.C1.D1.R1:   -20       19       -25       29      -19     20      -29      31
N6.C2.D0.R0:   -22       22       -27       48      -22     23      -30      31
N6.C2.D0.R1:   -22       22       -27       48      -22     23      -29      31
N6.C2.D1.R0:   -21       21       -27       32      -21     22      -29      31
N6.C2.D1.R1:   -22       22       -27       32      -20     21      -29      31
N6.C3.D0.R0:   -21       21       -26       48      -21     23      -28      31
N6.C3.D0.R1:   -21       21       -25       48      -22     23      -28      31
N6.C3.D1.R0:   -19       20       -25       29      -21     20      -29      31
N6.C3.D1.R1:   -20       21       -26       30      -19     20      -28      31
STOP_RMT_N6
N0: 
Total DDR trainings latency = 204903 ms
N3.C0.S12: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 5
N5.C1: RdCmd2DataValidLatency = 21, (dlyFrmS = 15, clEff = 10, earlyCas = 0, selNTiming = 0)
N6: GetAllRankMargins time            5243 ms
N1: PostVmseTraining
N3.C0.S13: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 5
N5.C2: JCK cmd timing = 1N
N6: 
Total DDR trainings latency = 205261 ms
Checkpoint Code: Socket 0, 0xB6, 0x5C, 0x0000
N3.C0.S14: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 5
N5.C2: RdCmd2DataValidLatency = 21, (dlyFrmS = 15, clEff = 10, earlyCas = 0, selNTiming = 0)
N7: PostVmseTraining
N1.C0: PostVmseTraining
N3.C0.S15: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N5.C3: RdCmd2DataValidLatency = 21, (dlyFrmS = 15, clEff = 10, earlyCas = 0, selNTiming = 0)
N7.C0: PostVmseTraining
N1.C0: PostVMSE Training VMSE Health Check Passed
N3.C0.S16: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N7.C0: PostVMSE Training VMSE Health Check Passed
N1.C1: PostVmseTraining
N3.C0.S17: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 5
N7.C1: PostVmseTraining
N1.C2: PostVMSE Training VMSE Health Check Passed
N3.C0.D0.R0.S00: RcvEn: plus1 = 1, minus1 = 0, PI = 32, DB = 0
N7.C2: PostVMSE Training VMSE Health Check Passed
N1: PreDdrTraining
N3.C0.D0.R0.S01: RcvEn: plus1 = 1, minus1 = 0, PI = 09, DB = 1
N7: PreDdrTraining
N1: PreDdrTraining[QCRM=OFF]
N3.C0.D0.R0.S02: RcvEn: plus1 = 1, minus1 = 0, PI = 41, DB = 0
N7: PreDdrTraining[QCRM=OFF]
N1.C0.D0: CheckRankPopLocal: dimmPresent: 1, numRanks = 2
N3.C0.D0.R0.S03: RcvEn: plus1 = 1, minus1 = 0, PI = 23, DB = 0
N7.C0.D0: CheckRankPopLocal: dimmPresent: 1, numRanks = 2
N1.C0.D0.R0: CheckRankPopLocal: mapOut: 0, enabled = 1
N3.C0.D0.R0.S04: RcvEn: plus1 = 1, minus1 = 0, PI = 19, DB = 0
N7.C0.D0.R0: CheckRankPopLocal: mapOut: 0, enabled = 1
N1.C0.D0.R1: CheckRankPopLocal: mapOut: 0, enabled = 1
N3.C0.D0.R0.S05: RcvEn: plus1 = 1, minus1 = 0, PI = 40, DB = 0
N7.C0.D0.R1: CheckRankPopLocal: mapOut: 0, enabled = 1
N1.C0.D1: CheckRankPopLocal: dimmPresent: 0, numRanks = 0
N3.C0.D0.R0.S06: RcvEn: plus1 = 1, minus1 = 0, PI = 10, DB = 1
N7.C0.D1: CheckRankPopLocal: dimmPresent: 0, numRanks = 0
N1.C0.D2: CheckRankPopLocal: dimmPresent: 0, numRanks = 0
N3.C0.D0.R0.S07: RcvEn: plus1 = 1, minus1 = 0, PI = 37, DB = 0
N7.C0.D2: CheckRankPopLocal: dimmPresent: 0, numRanks = 0
N1.C0.D0: CheckRankPopLocal: amap: 0x00000000
N3.C0.D0.R0.S08: RcvEn: plus1 = 1, minus1 = 0, PI = 12, DB = 1
N7.C0.D0: CheckRankPopLocal: amap: 0x00000000
N1.C0.D1: CheckRankPopLocal: amap: 0x00000000
N3.C0.D0.R0.S09: RcvEn: plus1 = 1, minus1 = 0, PI = 28, DB = 0
N7.C0.D1: CheckRankPopLocal: amap: 0x00000000
N1.C0.D2: CheckRankPopLocal: amap: 0x00000000
N3.C0.D0.R0.S10: RcvEn: plus1 = 1, minus1 = 0, PI = 07, DB = 1
N7.C0.D2: CheckRankPopLocal: amap: 0x00000000
N1.C1.D0: CheckRankPopLocal: dimmPresent: 1, numRanks = 2
N3.C0.D0.R0.S11: RcvEn: plus1 = 1, minus1 = 0, PI = 43, DB = 0
N7.C1.D0: CheckRankPopLocal: dimmPresent: 1, numRanks = 2
N1.C1.D0.R0: CheckRankPopLocal: mapOut: 0, enabled = 1
N3.C0.D0.R0.S12: RcvEn: plus1 = 1, minus1 = 0, PI = 22, DB = 0
N7.C1.D0.R0: CheckRankPopLocal: mapOut: 0, enabled = 1
N1.C1.D0.R1: CheckRankPopLocal: mapOut: 0, enabled = 1
N3.C0.D0.R0.S13: RcvEn: plus1 = 1, minus1 = 0, PI = 18, DB = 0
N7.C1.D0.R1: CheckRankPopLocal: mapOut: 0, enabled = 1
N1.C1.D1: CheckRankPopLocal: dimmPresent: 0, numRanks = 0
N3.C0.D0.R0.S14: RcvEn: plus1 = 1, minus1 = 0, PI = 40, DB = 0
N7.C1.D1: CheckRankPopLocal: dimmPresent: 0, numRanks = 0
N1.C1.D2: CheckRankPopLocal: dimmPresent: 0, numRanks = 0
N3.C0.D0.R0.S15: RcvEn: plus1 = 1, minus1 = 0, PI = 10, DB = 1
N7.C1.D2: CheckRankPopLocal: dimmPresent: 0, numRanks = 0
N1.C1.D0: CheckRankPopLocal: amap: 0x00000000
N3.C0.D0.R0.S16: RcvEn: plus1 = 1, minus1 = 0, PI = 37, DB = 0
N7.C1.D0: CheckRankPopLocal: amap: 0x00000000
N1.C1.D1: CheckRankPopLocal: amap: 0x00000000
N3.C0.D0.R0.S17: RcvEn: plus1 = 1, minus1 = 0, PI = 09, DB = 1
N7.C1.D1: CheckRankPopLocal: amap: 0x00000000
N1.C1.D2: CheckRankPopLocal: amap: 0x00000000
N3.C0.D0.R1.S00: RcvEn: plus1 = 1, minus1 = 0, PI = 32, DB = 0
N7.C1.D2: CheckRankPopLocal: amap: 0x00000000
N1.C2.D0: CheckRankPopLocal: dimmPresent: 1, numRanks = 2
N3.C0.D0.R1.S01: RcvEn: plus1 = 1, minus1 = 0, PI = 09, DB = 1
N7.C2.D0: CheckRankPopLocal: dimmPresent: 1, numRanks = 2
N1.C2.D0.R0: CheckRankPopLocal: mapOut: 0, enabled = 1
N3.C0.D0.R1.S02: RcvEn: plus1 = 1, minus1 = 0, PI = 41, DB = 0
N7.C2.D0.R0: CheckRankPopLocal: mapOut: 0, enabled = 1
N1.C2.D0.R1: CheckRankPopLocal: mapOut: 0, enabled = 1
N3.C0.D0.R1.S03: RcvEn: plus1 = 1, minus1 = 0, PI = 23, DB = 0
N7.C2.D0.R1: CheckRankPopLocal: mapOut: 0, enabled = 1
N1.C2.D1: CheckRankPopLocal: dimmPresent: 0, numRanks = 0
N3.C0.D0.R1.S04: RcvEn: plus1 = 1, minus1 = 0, PI = 19, DB = 0
N7.C2.D1: CheckRankPopLocal: dimmPresent: 0, numRanks = 0
N1.C2.D2: CheckRankPopLocal: dimmPresent: 0, numRanks = 0
N3.C0.D0.R1.S05: RcvEn: plus1 = 1, minus1 = 0, PI = 40, DB = 0
N7.C2.D2: CheckRankPopLocal: dimmPresent: 0, numRanks = 0
N1.C2.D0: CheckRankPopLocal: amap: 0x00000000
N3.C0.D0.R1.S06: RcvEn: plus1 = 1, minus1 = 0, PI = 10, DB = 1
N7.C2.D0: CheckRankPopLocal: amap: 0x00000000
N1.C2.D1: CheckRankPopLocal: amap: 0x00000000
N3.C0.D0.R1.S07: RcvEn: plus1 = 1, minus1 = 0, PI = 37, DB = 0
N7.C2.D1: CheckRankPopLocal: amap: 0x00000000
N1.C2.D2: CheckRankPopLocal: amap: 0x00000000
N3.C0.D0.R1.S08: RcvEn: plus1 = 1, minus1 = 0, PI = 12, DB = 1
N7.C2.D2: CheckRankPopLocal: amap: 0x00000000
N1.C3.D0: CheckRankPopLocal: dimmPresent: 1, numRanks = 2
N3.C0.D0.R1.S09: RcvEn: plus1 = 1, minus1 = 0, PI = 28, DB = 0
N7.C3.D0: CheckRankPopLocal: dimmPresent: 1, numRanks = 2
N1.C3.D0.R0: CheckRankPopLocal: mapOut: 0, enabled = 1
N3.C0.D0.R1.S10: RcvEn: plus1 = 1, minus1 = 0, PI = 07, DB = 1
N7.C3.D0.R0: CheckRankPopLocal: mapOut: 0, enabled = 1
N1.C3.D0.R1: CheckRankPopLocal: mapOut: 0, enabled = 1
N3.C0.D0.R1.S11: RcvEn: plus1 = 1, minus1 = 0, PI = 43, DB = 0
N7.C3.D0.R1: CheckRankPopLocal: mapOut: 0, enabled = 1
N1.C3.D1: CheckRankPopLocal: dimmPresent: 0, numRanks = 0
N3.C0.D0.R1.S12: RcvEn: plus1 = 1, minus1 = 0, PI = 22, DB = 0
N7.C3.D1: CheckRankPopLocal: dimmPresent: 0, numRanks = 0
N1.C3.D2: CheckRankPopLocal: dimmPresent: 0, numRanks = 0
N3.C0.D0.R1.S13: RcvEn: plus1 = 1, minus1 = 0, PI = 18, DB = 0
N7.C3.D2: CheckRankPopLocal: dimmPresent: 0, numRanks = 0
N1.C3.D0: CheckRankPopLocal: amap: 0x00000000
N3.C0.D0.R1.S14: RcvEn: plus1 = 1, minus1 = 0, PI = 40, DB = 0
N7.C3.D0: CheckRankPopLocal: amap: 0x00000000
N1.C3.D1: CheckRankPopLocal: amap: 0x00000000
N3.C0.D0.R1.S15: RcvEn: plus1 = 1, minus1 = 0, PI = 10, DB = 1
N7.C3.D1: CheckRankPopLocal: amap: 0x00000000
N1.C3.D2: CheckRankPopLocal: amap: 0x00000000
N3.C0.D0.R1.S16: RcvEn: plus1 = 1, minus1 = 0, PI = 37, DB = 0
N7.C3.D2: CheckRankPopLocal: amap: 0x00000000
N1.C0: JCK cmd timing = 3N
N3.C0.D0.R1.S17: RcvEn: plus1 = 1, minus1 = 0, PI = 09, DB = 1
N7.C0: JCK cmd timing = 3N
N1.C0: RdCmd2DataValidLatency = 20, (dlyFrmS = 15, clEff = 10, earlyCas = 0, selNTiming = 2)
STOP_DATA_REC_EN
N7.C0: RdCmd2DataValidLatency = 20, (dlyFrmS = 15, clEff = 10, earlyCas = 0, selNTiming = 2)
N1.C0: CLK0_CFG: 0x000FFF10
N3.C1.D0.R0: RcvEnFine: Initial RdCmd2RcvEnLatency = 10, Initial RdPtrOffsetRcvEn = 4
N7.C0: CLK0_CFG: 0x000FFF10
N1.C0: DDR_RANKCTL: 0x000FEE40
N7.C0: DDR_RANKCTL: 0x000FEE40
N1.C0: MCODT = 0 ( 50 ohms)
N3.C1.D0.R0.S00: Rcv En Fine Value = 300
N7.C0: MCODT = 0 ( 50 ohms)
N1.C0.D0.R0: Rtt_wr = 0, Rtt_nom = 60
N3.C1.D0.R0.S01: Rcv En Fine Value = 281
N7.C0.D0.R0: Rtt_wr = 0, Rtt_nom = 60
N1.C0.D0.R1: Rtt_wr = 0, Rtt_nom = 60
N3.C1.D0.R0.S02: Rcv En Fine Value = 381
N7.C0.D0.R1: Rtt_wr = 0, Rtt_nom = 60
N1.C0: ODTRDCTL00 = 0x00000000
N3.C1.D0.R0.S03: Rcv En Fine Value = 357
N7.C0: ODTRDCTL00 = 0x00000000
N1.C0: ODTRDCTL01 = 0x00000000
N3.C1.D0.R0.S04: Rcv En Fine Value = 351
N7.C0: ODTRDCTL01 = 0x00000000
N1.C0: ODTWRCTL00 = 0x00000081
N3.C1.D0.R0.S05: Rcv En Fine Value = 374
N7.C0: ODTWRCTL00 = 0x00000081
N1.C0: ODTWRCTL01 = 0x00000000
N3.C1.D0.R0.S06: Rcv En Fine Value = 272
N7.C0: ODTWRCTL01 = 0x00000000
N1.C1: RdCmd2DataValidLatency = 20, (dlyFrmS = 15, clEff = 10, earlyCas = 0, selNTiming = 2)
N3.C1.D0.R0.S07: Rcv En Fine Value = 292
N7.C1: RdCmd2DataValidLatency = 20, (dlyFrmS = 15, clEff = 10, earlyCas = 0, selNTiming = 2)
N1.C1: CLK0_CFG: 0x000FF110
N3.C1.D0.R0.S08: Rcv En Fine Value = 341
N7.C1: CLK0_CFG: 0x000FF110
N1.C1: DDR_RANKCTL: 0x000FEE40
N3.C1.D0.R0.S09: Rcv En Fine Value = 300
N7.C1: DDR_RANKCTL: 0x000FEE40
N1.C1: MCODT = 0 ( 50 ohms)
N3.C1.D0.R0.S10: Rcv En Fine Value = 284
N7.C1: MCODT = 0 ( 50 ohms)
N1.C1.D0.R0: Rtt_wr = 0, Rtt_nom = 60
N3.C1.D0.R0.S11: Rcv En Fine Value = 378
N7.C1.D0.R0: Rtt_wr = 0, Rtt_nom = 60
N1.C1.D0.R1: Rtt_wr = 0, Rtt_nom = 60
N3.C1.D0.R0.S12: Rcv En Fine Value = 359
N7.C1.D0.R1: Rtt_wr = 0, Rtt_nom = 60
N1.C1: ODTRDCTL00 = 0x00000000
N3.C1.D0.R0.S13: Rcv En Fine Value = 353
N7.C1: ODTRDCTL00 = 0x00000000
N1.C1: ODTRDCTL01 = 0x00000000
N3.C1.D0.R0.S14: Rcv En Fine Value = 376
N7.C1: ODTRDCTL01 = 0x00000000
N1.C1: ODTWRCTL00 = 0x00000081
N3.C1.D0.R0.S15: Rcv En Fine Value = 273
N7.C1: ODTWRCTL00 = 0x00000081
N1.C1: ODTWRCTL01 = 0x00000000
N3.C1.D0.R0.S16: Rcv En Fine Value = 296
N7.C1: ODTWRCTL01 = 0x00000000
N1.C2: JCK cmd timing = 3N
N3.C1.D0.R0.S17: Rcv En Fine Value = 340
N7.C2: JCK cmd timing = 3N
N1.C2: RdCmd2DataValidLatency = 20, (dlyFrmS = 15, clEff = 10, earlyCas = 0, selNTiming = 2)
N3.C1.D0.R0: Starting preamble search lower nibbles
N7.C2: RdCmd2DataValidLatency = 20, (dlyFrmS = 15, clEff = 10, earlyCas = 0, selNTiming = 2)
N1.C2: CLK0_CFG: 0x000FFF10
N3.C1.D0.R0.S00: PI = 044, PtrOffset = 004
N7.C2: CLK0_CFG: 0x000FFF10
N1.C2: DDR_RANKCTL: 0x000FEE40
N3.C1.D0.R0.S01: PI = 025, PtrOffset = 004
N7.C2: DDR_RANKCTL: 0x000FEE40
N1.C2: MCODT = 0 ( 50 ohms)
N3.C1.D0.R0.S02: PI = 061, PtrOffset = 005
N7.C2: MCODT = 0 ( 50 ohms)
N1.C2.D0.R0: Rtt_wr = 0, Rtt_nom = 60
N3.C1.D0.R0.S03: PI = 037, PtrOffset = 005
N7.C2.D0.R0: Rtt_wr = 0, Rtt_nom = 60
N1.C2.D0.R1: Rtt_wr = 0, Rtt_nom = 60
N3.C1.D0.R0.S04: PI = 031, PtrOffset = 005
N7.C2.D0.R1: Rtt_wr = 0, Rtt_nom = 60
N1.C2: ODTRDCTL00 = 0x00000000
N3.C1.D0.R0.S05: PI = 054, PtrOffset = 005
N7.C2: ODTRDCTL00 = 0x00000000
N1.C2: ODTRDCTL01 = 0x00000000
N3.C1.D0.R0.S06: PI = 016, PtrOffset = 004
N7.C2: ODTRDCTL01 = 0x00000000
N1.C2: ODTWRCTL00 = 0x00000081
N3.C1.D0.R0.S07: PI = 036, PtrOffset = 004
N7.C2: ODTWRCTL00 = 0x00000081
N1.C2: ODTWRCTL01 = 0x00000000
N3.C1.D0.R0.S08: PI = 021, PtrOffset = 005
N7.C2: ODTWRCTL01 = 0x00000000
N1.C3: RdCmd2DataValidLatency = 20, (dlyFrmS = 15, clEff = 10, earlyCas = 0, selNTiming = 2)
N3.C1.D0.R0.S00: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N7.C3: RdCmd2DataValidLatency = 20, (dlyFrmS = 15, clEff = 10, earlyCas = 0, selNTiming = 2)
N1.C3: CLK0_CFG: 0x000FF110
N3.C1.D0.R0.S01: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N7.C3: CLK0_CFG: 0x000FF110
N1.C3: DDR_RANKCTL: 0x000FEE40
N3.C1.D0.R0.S02: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N7.C3: DDR_RANKCTL: 0x000FEE40
N1.C3: MCODT = 0 ( 50 ohms)
N3.C1.D0.R0.S03: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N7.C3: MCODT = 0 ( 50 ohms)
N1.C3.D0.R0: Rtt_wr = 0, Rtt_nom = 60
N3.C1.D0.R0.S04: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N7.C3.D0.R0: Rtt_wr = 0, Rtt_nom = 60
N1.C3.D0.R1: Rtt_wr = 0, Rtt_nom = 60
N3.C1.D0.R0.S05: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N7.C3.D0.R1: Rtt_wr = 0, Rtt_nom = 60
N1.C3: ODTRDCTL00 = 0x00000000
N3.C1.D0.R0.S06: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N7.C3: ODTRDCTL00 = 0x00000000
N1.C3: ODTRDCTL01 = 0x00000000
N3.C1.D0.R0.S07: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N7.C3: ODTRDCTL01 = 0x00000000
N1.C3: ODTWRCTL00 = 0x00000081
N3.C1.D0.R0.S08: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N7.C3: ODTWRCTL00 = 0x00000081
N1.C3: ODTWRCTL01 = 0x00000000
N3.C1.D0.R0.S00: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N7.C3: ODTWRCTL01 = 0x00000000
N1.C0.D0: PreDdrTraining: Program dimmmtr 0xC5051
N3.C1.D0.R0.S01: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N7.C0.D0: PreDdrTraining: Program dimmmtr 0xC5051
N1.C1.D0: PreDdrTraining: Program dimmmtr 0xC5051
N3.C1.D0.R0.S02: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N7.C1.D0: PreDdrTraining: Program dimmmtr 0xC5051
N1.C2.D0: PreDdrTraining: Program dimmmtr 0xC5051
N3.C1.D0.R0.S03: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N7.C2.D0: PreDdrTraining: Program dimmmtr 0xC5051
N1.C3.D0: PreDdrTraining: Program dimmmtr 0xC5051
N3.C1.D0.R0.S04: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N7.C3.D0: PreDdrTraining: Program dimmmtr 0xC5051
N1: InitializeDdrioForUse
N3.C1.D0.R0.S05: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N7: InitializeDdrioForUse
N1: SetupJckForBL: setting BL to 8
N3.C1.D0.R0.S06: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N7: SetupJckForBL: setting BL to 8
N1.C0: ODTTIMCTL (INIT RELAX) rdwidth = 10 rddly = 0 wrwidth = 8 wrdly = 0
N3.C1.D0.R0.S07: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N7.C0: ODTTIMCTL (INIT RELAX) rdwidth = 10 rddly = 0 wrwidth = 8 wrdly = 0
N1.C1: ODTTIMCTL (INIT RELAX) rdwidth = 10 rddly = 0 wrwidth = 8 wrdly = 0
N3.C1.D0.R0.S08: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N7.C1: ODTTIMCTL (INIT RELAX) rdwidth = 10 rddly = 0 wrwidth = 8 wrdly = 0
N1.C2: ODTTIMCTL (INIT RELAX) rdwidth = 10 rddly = 0 wrwidth = 8 wrdly = 0
N3.C1.D0.R0.S00: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N7.C2: ODTTIMCTL (INIT RELAX) rdwidth = 10 rddly = 0 wrwidth = 8 wrdly = 0
N1.C3: ODTTIMCTL (INIT RELAX) rdwidth = 10 rddly = 0 wrwidth = 8 wrdly = 0
N3.C1.D0.R0.S01: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N7.C3: ODTTIMCTL (INIT RELAX) rdwidth = 10 rddly = 0 wrwidth = 8 wrdly = 0
N1: JckDdrTraining
N3.C1.D0.R0.S02: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N7: JckDdrTraining
N1: InitializeDdrioForTraining: QCRM Disabled
N3.C1.D0.R0.S03: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N7: InitializeDdrioForTraining: QCRM Disabled
N1.C0: InitializeDdrioForTraining: cleff = 10
N3.C1.D0.R0.S04: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N7.C0: InitializeDdrioForTraining: cleff = 10
N1.C0: InitializeDdrioForTraining: cwleff = 8
N3.C1.D0.R0.S05: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N7.C0: InitializeDdrioForTraining: cwleff = 8
N1.C0: InitializeDdrioForTraining: initial ddrInitIndexRx = 4 ddrInitIndexTx = 2
N3.C1.D0.R0.S06: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N7.C0: InitializeDdrioForTraining: initial ddrInitIndexRx = 4 ddrInitIndexTx = 2
N1.C0: InitializeDdrioForTraining: initial RdCmd2RcvEnLatency = 5
N3.C1.D0.R0.S07: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N7.C0: InitializeDdrioForTraining: initial RdCmd2RcvEnLatency = 5
N1.C0: InitializeDdrioForTraining: initial RdPtrOffsetRcvEn = 4
N3.C1.D0.R0.S08: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N7.C0: InitializeDdrioForTraining: initial RdPtrOffsetRcvEn = 4
N1.C0: InitializeDdrioForTraining: initial rkrdptroffsetrcvenb = 6
N3.C1.D0.R0.S00: Preamble found at Latency = 008
N7.C0: InitializeDdrioForTraining: initial rkrdptroffsetrcvenb = 6
N1.C0: InitializeDdrioForTraining: initial rkrdptroffsetdrvenrcvenb = 5
N3.C1.D0.R0.S01: Preamble found at Latency = 008
N7.C0: InitializeDdrioForTraining: initial rkrdptroffsetdrvenrcvenb = 5
N1.C0: InitializeDdrioForTraining: initial WrCmd2DqsStartLatency = 4
N3.C1.D0.R0.S06: Preamble found at Latency = 008
N7.C0: InitializeDdrioForTraining: initial WrCmd2DqsStartLatency = 4
N1.C0: InitializeDdrioForTraining: initial RdPtrOffsetDqs = 10
N3.C1.D0.R0.S07: Preamble found at Latency = 008
N7.C0: InitializeDdrioForTraining: initial RdPtrOffsetDqs = 10
N1.C0: InitializeDdrioForTraining: initial RdCmd2RcvEnLatency = 5
N3.C1.D0.R0.S00: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N7.C0: InitializeDdrioForTraining: initial RdCmd2RcvEnLatency = 5
N1.C0: InitializeDdrioForTraining: initial WrCmd2DqsStartLatency = 4
N3.C1.D0.R0.S01: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N7.C0: InitializeDdrioForTraining: initial WrCmd2DqsStartLatency = 4
N1.C0: InitializeDdrioForTraining: initial RdPtrOffsetRcvEn = 4
N3.C1.D0.R0.S02: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N7.C0: InitializeDdrioForTraining: initial RdPtrOffsetRcvEn = 4
N1.C0: InitializeDdrioForTraining: initial RdPtrOffsetDqs = 6
N3.C1.D0.R0.S03: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N7.C0: InitializeDdrioForTraining: initial RdPtrOffsetDqs = 6
N1.C0: InitializeDdrioForTraining: initial RdPtrOffsetDq = 5
N3.C1.D0.R0.S04: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N5.C0.D0: CalcFinalClock(94,120) = 26
N7.C0: InitializeDdrioForTraining: initial RdPtrOffsetDq = 5
N1.C1: InitializeDdrioForTraining: cleff = 10
N3.C1.D0.R0.S05: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N5.C1.D0: CalcFinalClock(96,118) = 27
N7.C1: InitializeDdrioForTraining: cleff = 10
N1.C1: InitializeDdrioForTraining: cwleff = 8
N3.C1.D0.R0.S06: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N5.C2.D0: CalcFinalClock(87,124) = 21
N7.C1: InitializeDdrioForTraining: cwleff = 8
N1.C1: InitializeDdrioForTraining: initial ddrInitIndexRx = 4 ddrInitIndexTx = 2
N3.C1.D0.R0.S07: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N5.C3.D0: CalcFinalClock(93,115) = 22
N7.C1: InitializeDdrioForTraining: initial ddrInitIndexRx = 4 ddrInitIndexTx = 2
N1.C1: InitializeDdrioForTraining: initial RdCmd2RcvEnLatency = 5
N3.C1.D0.R0.S08: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N5.C0: JCK cmd timing = 3N
N7.C1: InitializeDdrioForTraining: initial RdCmd2RcvEnLatency = 5
N1.C1: InitializeDdrioForTraining: initial RdPtrOffsetRcvEn = 4
N3.C1.D0.R0.S02: Preamble found at Latency = 007
N5.C0: RdCmd2DataValidLatency = 20, (dlyFrmS = 15, clEff = 10, earlyCas = 0, selNTiming = 2)
N7.C1: InitializeDdrioForTraining: initial RdPtrOffsetRcvEn = 4
N1.C1: InitializeDdrioForTraining: initial rkrdptroffsetrcvenb = 6
N3.C1.D0.R0.S03: Preamble found at Latency = 007
N5.C1: RdCmd2DataValidLatency = 20, (dlyFrmS = 15, clEff = 10, earlyCas = 0, selNTiming = 2)
N7.C1: InitializeDdrioForTraining: initial rkrdptroffsetrcvenb = 6
N1.C1: InitializeDdrioForTraining: initial rkrdptroffsetdrvenrcvenb = 5
N3.C1.D0.R0.S04: Preamble found at Latency = 007
N5.C2: JCK cmd timing = 3N
N7.C1: InitializeDdrioForTraining: initial rkrdptroffsetdrvenrcvenb = 5
N1.C1: InitializeDdrioForTraining: initial WrCmd2DqsStartLatency = 4
N3.C1.D0.R0.S05: Preamble found at Latency = 007
N5.C2: RdCmd2DataValidLatency = 20, (dlyFrmS = 15, clEff = 10, earlyCas = 0, selNTiming = 2)
N7.C1: InitializeDdrioForTraining: initial WrCmd2DqsStartLatency = 4
N1.C1: InitializeDdrioForTraining: initial RdPtrOffsetDqs = 10
N3.C1.D0.R0.S08: Preamble found at Latency = 007
N5.C3: RdCmd2DataValidLatency = 20, (dlyFrmS = 15, clEff = 10, earlyCas = 0, selNTiming = 2)
N7.C1: InitializeDdrioForTraining: initial RdPtrOffsetDqs = 10
N1.C1: InitializeDdrioForTraining: initial RdCmd2RcvEnLatency = 5
N3.C1.D0.R0.S00: Total Receive Enable Delay = 1356
N5: RunTrainStep: Final status = 0
N7.C1: InitializeDdrioForTraining: initial RdCmd2RcvEnLatency = 5
N1.C1: InitializeDdrioForTraining: initial WrCmd2DqsStartLatency = 4
N3.C1.D0.R0.S01: Total Receive Enable Delay = 1337

END - Early Command Training           Time         2596 ms
N7.C1: InitializeDdrioForTraining: initial WrCmd2DqsStartLatency = 4
N1.C1: InitializeDdrioForTraining: initial RdPtrOffsetRcvEn = 4
N3.C1.D0.R0.S02: Total Receive Enable Delay = 1309

START - Basic Read DQ/DQS Training
N7.C1: InitializeDdrioForTraining: initial RdPtrOffsetRcvEn = 4
N1.C1: InitializeDdrioForTraining: initial RdPtrOffsetDqs = 6
N3.C1.D0.R0.S03: Total Receive Enable Delay = 1285
N5.C0: RdCmd2DataValidLatency = 20, (dlyFrmS = 15, clEff = 10, earlyCas = 0, selNTiming = 2)
N7.C1: InitializeDdrioForTraining: initial RdPtrOffsetDqs = 6
N1.C1: InitializeDdrioForTraining: initial RdPtrOffsetDq = 5
N3.C1.D0.R0.S04: Total Receive Enable Delay = 1279
N5.C0: SettingForTrainingStep: RdCmd2RcvEnLatency = 5
N7.C1: InitializeDdrioForTraining: initial RdPtrOffsetDq = 5
N1.C2: InitializeDdrioForTraining: cleff = 10
N3.C1.D0.R0.S05: Total Receive Enable Delay = 1302
N5.C1: RdCmd2DataValidLatency = 20, (dlyFrmS = 15, clEff = 10, earlyCas = 0, selNTiming = 2)
N7.C2: InitializeDdrioForTraining: cleff = 10
N1.C2: InitializeDdrioForTraining: cwleff = 8
N3.C1.D0.R0.S06: Total Receive Enable Delay = 1328
N5.C1: SettingForTrainingStep: RdCmd2RcvEnLatency = 5
N7.C2: InitializeDdrioForTraining: cwleff = 8
N1.C2: InitializeDdrioForTraining: initial ddrInitIndexRx = 4 ddrInitIndexTx = 2
N3.C1.D0.R0.S07: Total Receive Enable Delay = 1348
N5.C2: RdCmd2DataValidLatency = 20, (dlyFrmS = 15, clEff = 10, earlyCas = 0, selNTiming = 2)
N7.C2: InitializeDdrioForTraining: initial ddrInitIndexRx = 4 ddrInitIndexTx = 2
N1.C2: InitializeDdrioForTraining: initial RdCmd2RcvEnLatency = 5
N3.C1.D0.R0.S08: Total Receive Enable Delay = 1269
N5.C2: SettingForTrainingStep: RdCmd2RcvEnLatency = 5
N7.C2: InitializeDdrioForTraining: initial RdCmd2RcvEnLatency = 5
N1.C2: InitializeDdrioForTraining: initial RdPtrOffsetRcvEn = 4
N3.C1.D0.R0: Starting preamble search upper nibbles
N5.C3: RdCmd2DataValidLatency = 20, (dlyFrmS = 15, clEff = 10, earlyCas = 0, selNTiming = 2)
N7.C2: InitializeDdrioForTraining: initial RdPtrOffsetRcvEn = 4
N1.C2: InitializeDdrioForTraining: initial rkrdptroffsetrcvenb = 6
N3.C1.D0.R0.S09: PI = 044, PtrOffset = 004
N5.C3: SettingForTrainingStep: RdCmd2RcvEnLatency = 5
N7.C2: InitializeDdrioForTraining: initial rkrdptroffsetrcvenb = 6
N1.C2: InitializeDdrioForTraining: initial rkrdptroffsetdrvenrcvenb = 5
N3.C1.D0.R0.S10: PI = 028, PtrOffset = 004
N5.C0.D0.R0.S00: RdDqDqs FSM results: Left = 05, Right = 63, center = 34
N7.C2: InitializeDdrioForTraining: initial rkrdptroffsetdrvenrcvenb = 5
N1.C2: InitializeDdrioForTraining: initial WrCmd2DqsStartLatency = 4
N3.C1.D0.R0.S11: PI = 058, PtrOffset = 005
N5.C0.D0.R0.S00: RxDqsDelay = 034
N7.C2: InitializeDdrioForTraining: initial WrCmd2DqsStartLatency = 4
N1.C2: InitializeDdrioForTraining: initial RdPtrOffsetDqs = 10
N3.C1.D0.R0.S12: PI = 039, PtrOffset = 005
N5.C0.D0.R0.S01: RdDqDqs FSM results: Left = 05, Right = 63, center = 34
N7.C2: InitializeDdrioForTraining: initial RdPtrOffsetDqs = 10
N1.C2: InitializeDdrioForTraining: initial RdCmd2RcvEnLatency = 5
N3.C1.D0.R0.S13: PI = 033, PtrOffset = 005
N5.C0.D0.R0.S01: RxDqsDelay = 034
N7.C2: InitializeDdrioForTraining: initial RdCmd2RcvEnLatency = 5
N1.C2: InitializeDdrioForTraining: initial WrCmd2DqsStartLatency = 4
N3.C1.D0.R0.S14: PI = 056, PtrOffset = 005
N5.C0.D0.R0.S02: RdDqDqs FSM results: Left = 10, Right = 63, center = 36
N7.C2: InitializeDdrioForTraining: initial WrCmd2DqsStartLatency = 4
N1.C2: InitializeDdrioForTraining: initial RdPtrOffsetRcvEn = 4
N3.C1.D0.R0.S15: PI = 017, PtrOffset = 004
N5.C0.D0.R0.S02: RxDqsDelay = 036
N7.C2: InitializeDdrioForTraining: initial RdPtrOffsetRcvEn = 4
N1.C2: InitializeDdrioForTraining: initial RdPtrOffsetDqs = 6
N3.C1.D0.R0.S16: PI = 040, PtrOffset = 004
N5.C0.D0.R0.S03: RdDqDqs FSM results: Left = 06, Right = 63, center = 34
N7.C2: InitializeDdrioForTraining: initial RdPtrOffsetDqs = 6
N1.C2: InitializeDdrioForTraining: initial RdPtrOffsetDq = 5
N3.C1.D0.R0.S17: PI = 020, PtrOffset = 005
N5.C0.D0.R0.S03: RxDqsDelay = 034
N7.C2: InitializeDdrioForTraining: initial RdPtrOffsetDq = 5
N1.C3: InitializeDdrioForTraining: cleff = 10
N3.C1.D0.R0.S09: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N5.C0.D0.R0.S04: RdDqDqs FSM results: Left = 03, Right = 54, center = 28
N7.C3: InitializeDdrioForTraining: cleff = 10
N1.C3: InitializeDdrioForTraining: cwleff = 8
N3.C1.D0.R0.S10: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N5.C0.D0.R0.S04: RxDqsDelay = 028
N7.C3: InitializeDdrioForTraining: cwleff = 8
N1.C3: InitializeDdrioForTraining: initial ddrInitIndexRx = 4 ddrInitIndexTx = 2
N3.C1.D0.R0.S11: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N5.C0.D0.R0.S05: RdDqDqs FSM results: Left = 07, Right = 57, center = 32
N7.C3: InitializeDdrioForTraining: initial ddrInitIndexRx = 4 ddrInitIndexTx = 2
N1.C3: InitializeDdrioForTraining: initial RdCmd2RcvEnLatency = 5
N3.C1.D0.R0.S12: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N5.C0.D0.R0.S05: RxDqsDelay = 032
N7.C3: InitializeDdrioForTraining: initial RdCmd2RcvEnLatency = 5
N1.C3: InitializeDdrioForTraining: initial RdPtrOffsetRcvEn = 4
N3.C1.D0.R0.S13: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N5.C0.D0.R0.S06: RdDqDqs FSM results: Left = 03, Right = 60, center = 31
N7.C3: InitializeDdrioForTraining: initial RdPtrOffsetRcvEn = 4
N1.C3: InitializeDdrioForTraining: initial rkrdptroffsetrcvenb = 6
N3.C1.D0.R0.S14: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N5.C0.D0.R0.S06: RxDqsDelay = 031
N7.C3: InitializeDdrioForTraining: initial rkrdptroffsetrcvenb = 6
N1.C3: InitializeDdrioForTraining: initial rkrdptroffsetdrvenrcvenb = 5
N3.C1.D0.R0.S15: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N5.C0.D0.R0.S07: RdDqDqs FSM results: Left = 03, Right = 57, center = 30
N7.C3: InitializeDdrioForTraining: initial rkrdptroffsetdrvenrcvenb = 5
N1.C3: InitializeDdrioForTraining: initial WrCmd2DqsStartLatency = 4
N3.C1.D0.R0.S16: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N5.C0.D0.R0.S07: RxDqsDelay = 030
N7.C3: InitializeDdrioForTraining: initial WrCmd2DqsStartLatency = 4
N1.C3: InitializeDdrioForTraining: initial RdPtrOffsetDqs = 10
N3.C1.D0.R0.S17: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N5.C0.D0.R0.S08: RdDqDqs FSM results: Left = 06, Right = 59, center = 32
N7.C3: InitializeDdrioForTraining: initial RdPtrOffsetDqs = 10
N1.C3: InitializeDdrioForTraining: initial RdCmd2RcvEnLatency = 5
N3.C1.D0.R0.S09: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N5.C0.D0.R0.S08: RxDqsDelay = 032
N7.C3: InitializeDdrioForTraining: initial RdCmd2RcvEnLatency = 5
N1.C3: InitializeDdrioForTraining: initial WrCmd2DqsStartLatency = 4
N3.C1.D0.R0.S10: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N5.C0.D0.R0.S09: RdDqDqs FSM results: Left = 08, Right = 63, center = 35
N7.C3: InitializeDdrioForTraining: initial WrCmd2DqsStartLatency = 4
N1.C3: InitializeDdrioForTraining: initial RdPtrOffsetRcvEn = 4
N3.C1.D0.R0.S11: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N5.C0.D0.R0.S09: RxDqsDelay = 035
N7.C3: InitializeDdrioForTraining: initial RdPtrOffsetRcvEn = 4
N1.C3: InitializeDdrioForTraining: initial RdPtrOffsetDqs = 6
N3.C1.D0.R0.S12: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N5.C0.D0.R0.S10: RdDqDqs FSM results: Left = 07, Right = 61, center = 34
N7.C3: InitializeDdrioForTraining: initial RdPtrOffsetDqs = 6
N1.C3: InitializeDdrioForTraining: initial RdPtrOffsetDq = 5
N3.C1.D0.R0.S13: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N5.C0.D0.R0.S10: RxDqsDelay = 034
N7.C3: InitializeDdrioForTraining: initial RdPtrOffsetDq = 5
N1: DdrClockStopWa
N3.C1.D0.R0.S14: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N5.C0.D0.R0.S11: RdDqDqs FSM results: Left = 04, Right = 60, center = 32
N7: DdrClockStopWa
N1: JckSetOdtRelaxTiming:
N3.C1.D0.R0.S15: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N5.C0.D0.R0.S11: RxDqsDelay = 032
N7: JckSetOdtRelaxTiming:
N1.C0: ODTTIMCTL (INIT RELAX) rdwidth = 10 rddly = 0 wrwidth = 8 wrdly = 0
N3.C1.D0.R0.S16: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N5.C0.D0.R0.S12: RdDqDqs FSM results: Left = 06, Right = 61, center = 33
N7.C0: ODTTIMCTL (INIT RELAX) rdwidth = 10 rddly = 0 wrwidth = 8 wrdly = 0
N1.C0.S00: DDRIOHSIODATA0_LATCTL1 = 08040804
N3.C1.D0.R0.S17: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N5.C0.D0.R0.S12: RxDqsDelay = 033
N7.C0.S00: DDRIOHSIODATA0_LATCTL1 = 08040804
N1.C0.S01: DDRIOHSIODATA0_LATCTL1 = 08040804
N3.C1.D0.R0.S09: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N5.C0.D0.R0.S13: RdDqDqs FSM results: Left = 04, Right = 54, center = 29
N7.C0.S01: DDRIOHSIODATA0_LATCTL1 = 08040804
N1.C0.S02: DDRIOHSIODATA0_LATCTL1 = 08040804
N3.C1.D0.R0.S10: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N5.C0.D0.R0.S13: RxDqsDelay = 029
N7.C0.S02: DDRIOHSIODATA0_LATCTL1 = 08040804
N1.C0.S03: DDRIOHSIODATA0_LATCTL1 = 08040804
N3.C1.D0.R0.S11: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N5.C0.D0.R0.S14: RdDqDqs FSM results: Left = 07, Right = 54, center = 30
N7.C0.S03: DDRIOHSIODATA0_LATCTL1 = 08040804
N1.C0.S04: DDRIOHSIODATA0_LATCTL1 = 08040804
N3.C1.D0.R0.S12: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N5.C0.D0.R0.S14: RxDqsDelay = 030
N7.C0.S04: DDRIOHSIODATA0_LATCTL1 = 08040804
N1.C0.S05: DDRIOHSIODATA0_LATCTL1 = 08040804
N3.C1.D0.R0.S13: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N5.C0.D0.R0.S15: RdDqDqs FSM results: Left = 04, Right = 57, center = 30
N7.C0.S05: DDRIOHSIODATA0_LATCTL1 = 08040804
N1.C0.S06: DDRIOHSIODATA0_LATCTL1 = 08040804
N3.C1.D0.R0.S14: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N5.C0.D0.R0.S15: RxDqsDelay = 030
N7.C0.S06: DDRIOHSIODATA0_LATCTL1 = 08040804
N1.C0.S07: DDRIOHSIODATA0_LATCTL1 = 08040804
N3.C1.D0.R0.S15: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N5.C0.D0.R0.S16: RdDqDqs FSM results: Left = 04, Right = 58, center = 31
N7.C0.S07: DDRIOHSIODATA0_LATCTL1 = 08040804
N1.C0.S08: DDRIOHSIODATA0_LATCTL1 = 08040804
N3.C1.D0.R0.S16: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N5.C0.D0.R0.S16: RxDqsDelay = 031
N7.C0.S08: DDRIOHSIODATA0_LATCTL1 = 08040804
N1.C1: ODTTIMCTL (INIT RELAX) rdwidth = 10 rddly = 0 wrwidth = 8 wrdly = 0
N3.C1.D0.R0.S17: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N5.C0.D0.R0.S17: RdDqDqs FSM results: Left = 10, Right = 56, center = 33
N7.C1: ODTTIMCTL (INIT RELAX) rdwidth = 10 rddly = 0 wrwidth = 8 wrdly = 0
N1.C1.S00: DDRIOHSIODATA0_LATCTL1 = 08040804
N3.C1.D0.R0.S09: Preamble found at Latency = 008
N5.C0.D0.R0.S17: RxDqsDelay = 033
N7.C1.S00: DDRIOHSIODATA0_LATCTL1 = 08040804
N1.C1.S01: DDRIOHSIODATA0_LATCTL1 = 08040804
N3.C1.D0.R0.S10: Preamble found at Latency = 008
N5.C0.D0.R1.S00: RdDqDqs FSM results: Left = 04, Right = 63, center = 33
N7.C1.S01: DDRIOHSIODATA0_LATCTL1 = 08040804
N1.C1.S02: DDRIOHSIODATA0_LATCTL1 = 08040804
N3.C1.D0.R0.S15: Preamble found at Latency = 008
N5.C0.D0.R1.S00: RxDqsDelay = 033
N7.C1.S02: DDRIOHSIODATA0_LATCTL1 = 08040804
N1.C1.S03: DDRIOHSIODATA0_LATCTL1 = 08040804
N3.C1.D0.R0.S16: Preamble found at Latency = 008
N5.C0.D0.R1.S01: RdDqDqs FSM results: Left = 05, Right = 63, center = 34
N7.C1.S03: DDRIOHSIODATA0_LATCTL1 = 08040804
N1.C1.S04: DDRIOHSIODATA0_LATCTL1 = 08040804
N3.C1.D0.R0.S09: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N5.C0.D0.R1.S01: RxDqsDelay = 034
N7.C1.S04: DDRIOHSIODATA0_LATCTL1 = 08040804
N1.C1.S05: DDRIOHSIODATA0_LATCTL1 = 08040804
N3.C1.D0.R0.S10: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N5.C0.D0.R1.S02: RdDqDqs FSM results: Left = 10, Right = 63, center = 36
N7.C1.S05: DDRIOHSIODATA0_LATCTL1 = 08040804
N1.C1.S06: DDRIOHSIODATA0_LATCTL1 = 08040804
N3.C1.D0.R0.S11: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N5.C0.D0.R1.S02: RxDqsDelay = 036
N7.C1.S06: DDRIOHSIODATA0_LATCTL1 = 08040804
N1.C1.S07: DDRIOHSIODATA0_LATCTL1 = 08040804
N3.C1.D0.R0.S12: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N5.C0.D0.R1.S03: RdDqDqs FSM results: Left = 06, Right = 63, center = 34
N7.C1.S07: DDRIOHSIODATA0_LATCTL1 = 08040804
N1.C1.S08: DDRIOHSIODATA0_LATCTL1 = 08040804
N3.C1.D0.R0.S13: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N5.C0.D0.R1.S03: RxDqsDelay = 034
N7.C1.S08: DDRIOHSIODATA0_LATCTL1 = 08040804
N1.C2: ODTTIMCTL (INIT RELAX) rdwidth = 10 rddly = 0 wrwidth = 8 wrdly = 0
N3.C1.D0.R0.S14: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N5.C0.D0.R1.S04: RdDqDqs FSM results: Left = 03, Right = 54, center = 28
N7.C2: ODTTIMCTL (INIT RELAX) rdwidth = 10 rddly = 0 wrwidth = 8 wrdly = 0
N1.C2.S00: DDRIOHSIODATA0_LATCTL1 = 08040804
N3.C1.D0.R0.S15: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N5.C0.D0.R1.S04: RxDqsDelay = 028
N7.C2.S00: DDRIOHSIODATA0_LATCTL1 = 08040804
N1.C2.S01: DDRIOHSIODATA0_LATCTL1 = 08040804
N3.C1.D0.R0.S16: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N5.C0.D0.R1.S05: RdDqDqs FSM results: Left = 08, Right = 57, center = 32
N7.C2.S01: DDRIOHSIODATA0_LATCTL1 = 08040804
N1.C2.S02: DDRIOHSIODATA0_LATCTL1 = 08040804
N3.C1.D0.R0.S17: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N5.C0.D0.R1.S05: RxDqsDelay = 032
N7.C2.S02: DDRIOHSIODATA0_LATCTL1 = 08040804
N1.C2.S03: DDRIOHSIODATA0_LATCTL1 = 08040804
N3.C1.D0.R0.S11: Preamble found at Latency = 007
N5.C0.D0.R1.S06: RdDqDqs FSM results: Left = 04, Right = 59, center = 31
N7.C2.S03: DDRIOHSIODATA0_LATCTL1 = 08040804
N1.C2.S04: DDRIOHSIODATA0_LATCTL1 = 08040804
N3.C1.D0.R0.S12: Preamble found at Latency = 007
N5.C0.D0.R1.S06: RxDqsDelay = 031
N7.C2.S04: DDRIOHSIODATA0_LATCTL1 = 08040804
N1.C2.S05: DDRIOHSIODATA0_LATCTL1 = 08040804
N3.C1.D0.R0.S13: Preamble found at Latency = 007
N5.C0.D0.R1.S07: RdDqDqs FSM results: Left = 02, Right = 58, center = 30
N7.C2.S05: DDRIOHSIODATA0_LATCTL1 = 08040804
N1.C2.S06: DDRIOHSIODATA0_LATCTL1 = 08040804
N3.C1.D0.R0.S14: Preamble found at Latency = 007
N5.C0.D0.R1.S07: RxDqsDelay = 030
N7.C2.S06: DDRIOHSIODATA0_LATCTL1 = 08040804
N1.C2.S07: DDRIOHSIODATA0_LATCTL1 = 08040804
N3.C1.D0.R0.S17: Preamble found at Latency = 007
N5.C0.D0.R1.S08: RdDqDqs FSM results: Left = 07, Right = 63, center = 35
N7.C2.S07: DDRIOHSIODATA0_LATCTL1 = 08040804
N1.C2.S08: DDRIOHSIODATA0_LATCTL1 = 08040804
N3.C1.D0.R0: Preamble found for all upper nibbles, adjusting Pi, Offset to center into preamble
N5.C0.D0.R1.S08: RxDqsDelay = 035
N7.C2.S08: DDRIOHSIODATA0_LATCTL1 = 08040804
N1.C3: ODTTIMCTL (INIT RELAX) rdwidth = 10 rddly = 0 wrwidth = 8 wrdly = 0
N3.C1.D0.R0.S09: Total Receive Enable Delay = 1356
N5.C0.D0.R1.S09: RdDqDqs FSM results: Left = 07, Right = 63, center = 35
N7.C3: ODTTIMCTL (INIT RELAX) rdwidth = 10 rddly = 0 wrwidth = 8 wrdly = 0
N1.C3.S00: DDRIOHSIODATA0_LATCTL1 = 08040804
N3.C1.D0.R0.S10: Total Receive Enable Delay = 1340
N5.C0.D0.R1.S09: RxDqsDelay = 035
N7.C3.S00: DDRIOHSIODATA0_LATCTL1 = 08040804
N1.C3.S01: DDRIOHSIODATA0_LATCTL1 = 08040804
N3.C1.D0.R0.S11: Total Receive Enable Delay = 1306
N5.C0.D0.R1.S10: RdDqDqs FSM results: Left = 06, Right = 60, center = 33
N7.C3.S01: DDRIOHSIODATA0_LATCTL1 = 08040804
N1.C3.S02: DDRIOHSIODATA0_LATCTL1 = 08040804
N3.C1.D0.R0.S12: Total Receive Enable Delay = 1287
N5.C0.D0.R1.S10: RxDqsDelay = 033
N7.C3.S02: DDRIOHSIODATA0_LATCTL1 = 08040804
N1.C3.S03: DDRIOHSIODATA0_LATCTL1 = 08040804
N3.C1.D0.R0.S13: Total Receive Enable Delay = 1281
N5.C0.D0.R1.S11: RdDqDqs FSM results: Left = 05, Right = 63, center = 34
N7.C3.S03: DDRIOHSIODATA0_LATCTL1 = 08040804
N1.C3.S04: DDRIOHSIODATA0_LATCTL1 = 08040804
N3.C1.D0.R0.S14: Total Receive Enable Delay = 1304
N5.C0.D0.R1.S11: RxDqsDelay = 034
N7.C3.S04: DDRIOHSIODATA0_LATCTL1 = 08040804
N1.C3.S05: DDRIOHSIODATA0_LATCTL1 = 08040804
N3.C1.D0.R0.S15: Total Receive Enable Delay = 1329
N5.C0.D0.R1.S12: RdDqDqs FSM results: Left = 06, Right = 63, center = 34
N7.C3.S05: DDRIOHSIODATA0_LATCTL1 = 08040804
N1.C3.S06: DDRIOHSIODATA0_LATCTL1 = 08040804
N3.C1.D0.R0.S16: Total Receive Enable Delay = 1352
N5.C0.D0.R1.S12: RxDqsDelay = 034
N7.C3.S06: DDRIOHSIODATA0_LATCTL1 = 08040804
N1.C3.S07: DDRIOHSIODATA0_LATCTL1 = 08040804
N3.C1.D0.R0.S17: Total Receive Enable Delay = 1268
N5.C0.D0.R1.S13: RdDqDqs FSM results: Left = 04, Right = 52, center = 28
N7.C3.S07: DDRIOHSIODATA0_LATCTL1 = 08040804
N1.C3.S08: DDRIOHSIODATA0_LATCTL1 = 08040804
N3.C1.D0.R1: RcvEnFine: Initial RdCmd2RcvEnLatency = 10, Initial RdPtrOffsetRcvEn = 4
N5.C0.D0.R1.S13: RxDqsDelay = 028
N7.C3.S08: DDRIOHSIODATA0_LATCTL1 = 08040804

START - Early Command Training
N3.C1.D0.R1.S00: Rcv En Fine Value = 300
N5.C0.D0.R1.S14: RdDqDqs FSM results: Left = 08, Right = 55, center = 31

START - Early Command Training
Checkpoint Code: Socket 0, 0xB7, 0x00, 0x0000
N3.C1.D0.R1.S01: Rcv En Fine Value = 281
N5.C0.D0.R1.S14: RxDqsDelay = 031
N7.C0: DDRIOHSIODATA0_LATCTL1 = 08040804
N1.C0: DDRIOHSIODATA0_LATCTL1 = 08040804
N3.C1.D0.R1.S02: Rcv En Fine Value = 378
N5.C0.D0.R1.S15: RdDqDqs FSM results: Left = 04, Right = 56, center = 30
N7.C0: RdCmd2DataValidLatency = 20, (dlyFrmS = 15, clEff = 10, earlyCas = 0, selNTiming = 2)
N1.C0: RdCmd2DataValidLatency = 20, (dlyFrmS = 15, clEff = 10, earlyCas = 0, selNTiming = 2)
N3.C1.D0.R1.S03: Rcv En Fine Value = 357
N5.C0.D0.R1.S15: RxDqsDelay = 030
N7.C0: SettingForTrainingStep: RdCmd2RcvEnLatency = 5
N1.C0: SettingForTrainingStep: RdCmd2RcvEnLatency = 5
N3.C1.D0.R1.S04: Rcv En Fine Value = 352
N5.C0.D0.R1.S16: RdDqDqs FSM results: Left = 04, Right = 60, center = 32
N7.C0: SettingForTrainingStep: Programming 7 tick initial value to CTL signals
N1.C0: SettingForTrainingStep: Programming 7 tick initial value to CTL signals
N3.C1.D0.R1.S05: Rcv En Fine Value = 374
N5.C0.D0.R1.S16: RxDqsDelay = 032
N7.C1: DDRIOHSIODATA0_LATCTL1 = 08040804
N1.C1: DDRIOHSIODATA0_LATCTL1 = 08040804
N3.C1.D0.R1.S06: Rcv En Fine Value = 270
N5.C0.D0.R1.S17: RdDqDqs FSM results: Left = 09, Right = 59, center = 34
N7.C1: RdCmd2DataValidLatency = 20, (dlyFrmS = 15, clEff = 10, earlyCas = 0, selNTiming = 2)
N1.C1: RdCmd2DataValidLatency = 20, (dlyFrmS = 15, clEff = 10, earlyCas = 0, selNTiming = 2)
N3.C1.D0.R1.S07: Rcv En Fine Value = 293
N5.C0.D0.R1.S17: RxDqsDelay = 034
N7.C1: SettingForTrainingStep: RdCmd2RcvEnLatency = 5
N1.C1: SettingForTrainingStep: RdCmd2RcvEnLatency = 5
N3.C1.D0.R1.S08: Rcv En Fine Value = 341
START_DATA_RX_DQS
N7.C1: SettingForTrainingStep: Programming 10 tick initial value to CTL signals
N1.C1: SettingForTrainingStep: Programming 10 tick initial value to CTL signals
N3.C1.D0.R1.S09: Rcv En Fine Value = 300
N5.C0.R0.S00: PI = 33
N7.C2: DDRIOHSIODATA0_LATCTL1 = 08040804
N1.C2: DDRIOHSIODATA0_LATCTL1 = 08040804
N3.C1.D0.R1.S10: Rcv En Fine Value = 284
N5.C0.R0.S01: PI = 34
N7.C2: RdCmd2DataValidLatency = 20, (dlyFrmS = 15, clEff = 10, earlyCas = 0, selNTiming = 2)
N1.C2: RdCmd2DataValidLatency = 20, (dlyFrmS = 15, clEff = 10, earlyCas = 0, selNTiming = 2)
N3.C1.D0.R1.S11: Rcv En Fine Value = 380
N5.C0.R0.S02: PI = 36
N7.C2: SettingForTrainingStep: RdCmd2RcvEnLatency = 5
N1.C2: SettingForTrainingStep: RdCmd2RcvEnLatency = 5
N3.C1.D0.R1.S12: Rcv En Fine Value = 358
N5.C0.R0.S03: PI = 34
N7.C2: SettingForTrainingStep: Programming 7 tick initial value to CTL signals
N1.C2: SettingForTrainingStep: Programming 7 tick initial value to CTL signals
N3.C1.D0.R1.S13: Rcv En Fine Value = 351
N5.C0.R0.S04: PI = 28
N7.C3: DDRIOHSIODATA0_LATCTL1 = 08040804
N1.C3: DDRIOHSIODATA0_LATCTL1 = 08040804
N3.C1.D0.R1.S14: Rcv En Fine Value = 374
N5.C0.R0.S05: PI = 32
N7.C3: RdCmd2DataValidLatency = 20, (dlyFrmS = 15, clEff = 10, earlyCas = 0, selNTiming = 2)
N1.C3: RdCmd2DataValidLatency = 20, (dlyFrmS = 15, clEff = 10, earlyCas = 0, selNTiming = 2)
N3.C1.D0.R1.S15: Rcv En Fine Value = 272
N5.C0.R0.S06: PI = 31
N7.C3: SettingForTrainingStep: RdCmd2RcvEnLatency = 5
N1.C3: SettingForTrainingStep: RdCmd2RcvEnLatency = 5
N3.C1.D0.R1.S16: Rcv En Fine Value = 293
N5.C0.R0.S07: PI = 30
N7.C3: SettingForTrainingStep: Programming 10 tick initial value to CTL signals
N1.C3: SettingForTrainingStep: Programming 10 tick initial value to CTL signals
N3.C1.D0.R1.S17: Rcv En Fine Value = 341
N5.C0.R0.S08: PI = 33
N7: FSM Basic Clock Training
N1: FSM Basic Clock Training
N3.C1.D0.R1: Starting preamble search lower nibbles
N5.C0.R0.S09: PI = 35
N7.C0: JCK cmd timing = 1N
N1.C0: JCK cmd timing = 1N
N3.C1.D0.R1.S00: PI = 044, PtrOffset = 004
N5.C0.R0.S10: PI = 33
N7.C0: RdCmd2DataValidLatency = 21, (dlyFrmS = 15, clEff = 10, earlyCas = 0, selNTiming = 0)
N1.C0: RdCmd2DataValidLatency = 21, (dlyFrmS = 15, clEff = 10, earlyCas = 0, selNTiming = 0)
N3.C1.D0.R1.S01: PI = 025, PtrOffset = 004
N5.C0.R0.S11: PI = 33
N7.C1: RdCmd2DataValidLatency = 21, (dlyFrmS = 15, clEff = 10, earlyCas = 0, selNTiming = 0)
N1.C1: RdCmd2DataValidLatency = 21, (dlyFrmS = 15, clEff = 10, earlyCas = 0, selNTiming = 0)
N3.C1.D0.R1.S02: PI = 058, PtrOffset = 005
N5.C0.R0.S12: PI = 33
N7.C2: JCK cmd timing = 1N
N1.C2: JCK cmd timing = 1N
N3.C1.D0.R1.S03: PI = 037, PtrOffset = 005
N5.C0.R0.S13: PI = 28
N7.C2: RdCmd2DataValidLatency = 21, (dlyFrmS = 15, clEff = 10, earlyCas = 0, selNTiming = 0)
N1.C2: RdCmd2DataValidLatency = 21, (dlyFrmS = 15, clEff = 10, earlyCas = 0, selNTiming = 0)
N3.C1.D0.R1.S04: PI = 032, PtrOffset = 005
N5.C0.R0.S14: PI = 30
N7.C3: RdCmd2DataValidLatency = 21, (dlyFrmS = 15, clEff = 10, earlyCas = 0, selNTiming = 0)
N1.C3: RdCmd2DataValidLatency = 21, (dlyFrmS = 15, clEff = 10, earlyCas = 0, selNTiming = 0)
N3.C1.D0.R1.S05: PI = 054, PtrOffset = 005
N5.C0.R0.S15: PI = 30
N3.C1.D0.R1.S06: PI = 014, PtrOffset = 004
N5.C0.R0.S16: PI = 31
N3.C1.D0.R1.S07: PI = 037, PtrOffset = 004
N5.C0.R0.S17: PI = 33
N3.C1.D0.R1.S08: PI = 021, PtrOffset = 005
N5.C0.R0.S00: PI = 33
N3.C1.D0.R1.S00: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N5.C0.R0.S01: PI = 34
N3.C1.D0.R1.S01: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N5.C0.R0.S02: PI = 36
N3.C1.D0.R1.S02: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N5.C0.R0.S03: PI = 34
N3.C1.D0.R1.S03: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N5.C0.R0.S04: PI = 28
N3.C1.D0.R1.S04: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N5.C0.R0.S05: PI = 32
N3.C1.D0.R1.S05: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N5.C0.R0.S06: PI = 31
N3.C1.D0.R1.S06: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N5.C0.R0.S07: PI = 30
N3.C1.D0.R1.S07: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N5.C0.R0.S08: PI = 33
N3.C1.D0.R1.S08: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N5.C0.R0.S09: PI = 35
N3.C1.D0.R1.S00: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N5.C0.R0.S10: PI = 33
N3.C1.D0.R1.S01: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N5.C0.R0.S11: PI = 33
N3.C1.D0.R1.S02: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N5.C0.R0.S12: PI = 33
N3.C1.D0.R1.S03: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N5.C0.R0.S13: PI = 28
N3.C1.D0.R1.S04: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N5.C0.R0.S14: PI = 30
N3.C1.D0.R1.S05: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N5.C0.R0.S15: PI = 30
N3.C1.D0.R1.S06: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N5.C0.R0.S16: PI = 31
N3.C1.D0.R1.S07: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N5.C0.R0.S17: PI = 33
N3.C1.D0.R1.S08: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
STOP_DATA_RX_DQS
N3.C1.D0.R1.S00: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N5.C1.D0.R0.S00: RdDqDqs FSM results: Left = 05, Right = 58, center = 31
N3.C1.D0.R1.S01: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N5.C1.D0.R0.S00: RxDqsDelay = 031
N3.C1.D0.R1.S02: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N5.C1.D0.R0.S01: RdDqDqs FSM results: Left = 05, Right = 63, center = 34
N3.C1.D0.R1.S03: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N5.C1.D0.R0.S01: RxDqsDelay = 034
N3.C1.D0.R1.S04: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N5.C1.D0.R0.S02: RdDqDqs FSM results: Left = 05, Right = 59, center = 32
N3.C1.D0.R1.S05: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N5.C1.D0.R0.S02: RxDqsDelay = 032
N3.C1.D0.R1.S06: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N5.C1.D0.R0.S03: RdDqDqs FSM results: Left = 02, Right = 58, center = 30
N3.C1.D0.R1.S07: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N5.C1.D0.R0.S03: RxDqsDelay = 030
N3.C1.D0.R1.S08: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N5.C1.D0.R0.S04: RdDqDqs FSM results: Left = 07, Right = 59, center = 33
N3.C1.D0.R1.S00: Preamble found at Latency = 008
N5.C1.D0.R0.S04: RxDqsDelay = 033
N3.C1.D0.R1.S01: Preamble found at Latency = 008
N5.C1.D0.R0.S05: RdDqDqs FSM results: Left = 04, Right = 59, center = 31
N3.C1.D0.R1.S06: Preamble found at Latency = 008
N5.C1.D0.R0.S05: RxDqsDelay = 031
N3.C1.D0.R1.S07: Preamble found at Latency = 008
N5.C1.D0.R0.S06: RdDqDqs FSM results: Left = 03, Right = 59, center = 31
N3.C1.D0.R1.S00: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N5.C1.D0.R0.S06: RxDqsDelay = 031
N3.C1.D0.R1.S01: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N5.C1.D0.R0.S07: RdDqDqs FSM results: Left = 04, Right = 58, center = 31
N3.C1.D0.R1.S02: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N5.C1.D0.R0.S07: RxDqsDelay = 031
N3.C1.D0.R1.S03: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N5.C1.D0.R0.S08: RdDqDqs FSM results: Left = 05, Right = 58, center = 31
N3.C1.D0.R1.S04: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N5.C1.D0.R0.S08: RxDqsDelay = 031
N3.C1.D0.R1.S05: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N5.C1.D0.R0.S09: RdDqDqs FSM results: Left = 08, Right = 61, center = 34
N3.C1.D0.R1.S06: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N5.C1.D0.R0.S09: RxDqsDelay = 034
N3.C1.D0.R1.S07: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N5.C1.D0.R0.S10: RdDqDqs FSM results: Left = 04, Right = 60, center = 32
N3.C1.D0.R1.S08: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N5.C1.D0.R0.S10: RxDqsDelay = 032
N3.C1.D0.R1.S02: Preamble found at Latency = 007
N5.C1.D0.R0.S11: RdDqDqs FSM results: Left = 03, Right = 59, center = 31
N3.C1.D0.R1.S03: Preamble found at Latency = 007
N5.C1.D0.R0.S11: RxDqsDelay = 031
N3.C1.D0.R1.S04: Preamble found at Latency = 007
N5.C1.D0.R0.S12: RdDqDqs FSM results: Left = 03, Right = 59, center = 31
N3.C1.D0.R1.S05: Preamble found at Latency = 007
N5.C1.D0.R0.S12: RxDqsDelay = 031
N3.C1.D0.R1.S08: Preamble found at Latency = 007
N5.C1.D0.R0.S13: RdDqDqs FSM results: Left = 05, Right = 58, center = 31
N3.C1.D0.R1.S00: Total Receive Enable Delay = 1356
N5.C1.D0.R0.S13: RxDqsDelay = 031
N3.C1.D0.R1.S01: Total Receive Enable Delay = 1337
N5.C1.D0.R0.S14: RdDqDqs FSM results: Left = 10, Right = 54, center = 32
N3.C1.D0.R1.S02: Total Receive Enable Delay = 1306
N5.C1.D0.R0.S14: RxDqsDelay = 032
N3.C1.D0.R1.S03: Total Receive Enable Delay = 1285
N5.C1.D0.R0.S15: RdDqDqs FSM results: Left = 07, Right = 61, center = 34
N3.C1.D0.R1.S04: Total Receive Enable Delay = 1280
N5.C1.D0.R0.S15: RxDqsDelay = 034
N3.C1.D0.R1.S05: Total Receive Enable Delay = 1302
N5.C1.D0.R0.S16: RdDqDqs FSM results: Left = 05, Right = 60, center = 32
N3.C1.D0.R1.S06: Total Receive Enable Delay = 1326
N5.C1.D0.R0.S16: RxDqsDelay = 032
N3.C1.D0.R1.S07: Total Receive Enable Delay = 1349
N5.C1.D0.R0.S17: RdDqDqs FSM results: Left = 04, Right = 53, center = 28
N3.C1.D0.R1.S08: Total Receive Enable Delay = 1269
N5.C1.D0.R0.S17: RxDqsDelay = 028
N3.C1.D0.R1: Starting preamble search upper nibbles
N5.C1.D0.R1.S00: RdDqDqs FSM results: Left = 05, Right = 60, center = 32
N3.C1.D0.R1.S09: PI = 044, PtrOffset = 004
N5.C1.D0.R1.S00: RxDqsDelay = 032
N3.C1.D0.R1.S10: PI = 028, PtrOffset = 004
N5.C1.D0.R1.S01: RdDqDqs FSM results: Left = 05, Right = 63, center = 34
N3.C1.D0.R1.S11: PI = 060, PtrOffset = 005
N5.C1.D0.R1.S01: RxDqsDelay = 034
N3.C1.D0.R1.S12: PI = 038, PtrOffset = 005
N5.C1.D0.R1.S02: RdDqDqs FSM results: Left = 05, Right = 60, center = 32
N3.C1.D0.R1.S13: PI = 031, PtrOffset = 005
N5.C1.D0.R1.S02: RxDqsDelay = 032
N3.C1.D0.R1.S14: PI = 054, PtrOffset = 005
N5.C1.D0.R1.S03: RdDqDqs FSM results: Left = 02, Right = 59, center = 30
N3.C1.D0.R1.S15: PI = 016, PtrOffset = 004
N5.C1.D0.R1.S03: RxDqsDelay = 030
N3.C1.D0.R1.S16: PI = 037, PtrOffset = 004
N5.C1.D0.R1.S04: RdDqDqs FSM results: Left = 07, Right = 58, center = 32
N3.C1.D0.R1.S17: PI = 021, PtrOffset = 005
N5.C1.D0.R1.S04: RxDqsDelay = 032
N3.C1.D0.R1.S09: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N5.C1.D0.R1.S05: RdDqDqs FSM results: Left = 04, Right = 60, center = 32
N3.C1.D0.R1.S10: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N5.C1.D0.R1.S05: RxDqsDelay = 032
N3.C1.D0.R1.S11: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N5.C1.D0.R1.S06: RdDqDqs FSM results: Left = 03, Right = 58, center = 30
N3.C1.D0.R1.S12: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N5.C1.D0.R1.S06: RxDqsDelay = 030
N3.C1.D0.R1.S13: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N5.C1.D0.R1.S07: RdDqDqs FSM results: Left = 04, Right = 59, center = 31
N3.C1.D0.R1.S14: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N5.C1.D0.R1.S07: RxDqsDelay = 031
N3.C1.D0.R1.S15: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N5.C1.D0.R1.S08: RdDqDqs FSM results: Left = 06, Right = 58, center = 32
N3.C1.D0.R1.S16: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N5.C1.D0.R1.S08: RxDqsDelay = 032
N3.C1.D0.R1.S17: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N5.C1.D0.R1.S09: RdDqDqs FSM results: Left = 08, Right = 63, center = 35
N3.C1.D0.R1.S09: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N5.C1.D0.R1.S09: RxDqsDelay = 035
N3.C1.D0.R1.S10: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N5.C1.D0.R1.S10: RdDqDqs FSM results: Left = 03, Right = 59, center = 31
N3.C1.D0.R1.S11: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N5.C1.D0.R1.S10: RxDqsDelay = 031
N3.C1.D0.R1.S12: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N5.C1.D0.R1.S11: RdDqDqs FSM results: Left = 03, Right = 61, center = 32
N3.C1.D0.R1.S13: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N5.C1.D0.R1.S11: RxDqsDelay = 032
N3.C1.D0.R1.S14: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N5.C1.D0.R1.S12: RdDqDqs FSM results: Left = 03, Right = 59, center = 31
N3.C1.D0.R1.S15: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N5.C1.D0.R1.S12: RxDqsDelay = 031
N3.C1.D0.R1.S16: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N5.C1.D0.R1.S13: RdDqDqs FSM results: Left = 05, Right = 59, center = 32
N3.C1.D0.R1.S17: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N5.C1.D0.R1.S13: RxDqsDelay = 032
N3.C1.D0.R1.S09: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N5.C1.D0.R1.S14: RdDqDqs FSM results: Left = 09, Right = 52, center = 30
N3.C1.D0.R1.S10: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N5.C1.D0.R1.S14: RxDqsDelay = 030
N3.C1.D0.R1.S11: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N5.C1.D0.R1.S15: RdDqDqs FSM results: Left = 06, Right = 60, center = 33
N3.C1.D0.R1.S12: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N5.C1.D0.R1.S15: RxDqsDelay = 033
N3.C1.D0.R1.S13: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N5.C1.D0.R1.S16: RdDqDqs FSM results: Left = 04, Right = 60, center = 32
N3.C1.D0.R1.S14: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N5.C1.D0.R1.S16: RxDqsDelay = 032
N3.C1.D0.R1.S15: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N5.C1.D0.R1.S17: RdDqDqs FSM results: Left = 04, Right = 52, center = 28
N3.C1.D0.R1.S16: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N5.C1.D0.R1.S17: RxDqsDelay = 028
N3.C1.D0.R1.S17: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
START_DATA_RX_DQS
N3.C1.D0.R1.S09: Preamble found at Latency = 008
N5.C1.R0.S00: PI = 31
N3.C1.D0.R1.S10: Preamble found at Latency = 008
N5.C1.R0.S01: PI = 34
N3.C1.D0.R1.S15: Preamble found at Latency = 008
N5.C1.R0.S02: PI = 32
N3.C1.D0.R1.S16: Preamble found at Latency = 008
N5.C1.R0.S03: PI = 30
N3.C1.D0.R1.S09: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N5.C1.R0.S04: PI = 32
N3.C1.D0.R1.S10: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N5.C1.R0.S05: PI = 31
N3.C1.D0.R1.S11: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N5.C1.R0.S06: PI = 30
N3.C1.D0.R1.S12: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N5.C1.R0.S07: PI = 31
N3.C1.D0.R1.S13: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N5.C1.R0.S08: PI = 31
N3.C1.D0.R1.S14: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N5.C1.R0.S09: PI = 34
N3.C1.D0.R1.S15: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N5.C1.R0.S10: PI = 31
N3.C1.D0.R1.S16: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N5.C1.R0.S11: PI = 31
N3.C1.D0.R1.S17: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N5.C1.R0.S12: PI = 31
N3.C1.D0.R1.S11: Preamble found at Latency = 007
N5.C1.R0.S13: PI = 31
N3.C1.D0.R1.S12: Preamble found at Latency = 007
N5.C1.R0.S14: PI = 31
N3.C1.D0.R1.S13: Preamble found at Latency = 007
N5.C1.R0.S15: PI = 33
N3.C1.D0.R1.S14: Preamble found at Latency = 007
N5.C1.R0.S16: PI = 32
N3.C1.D0.R1.S17: Preamble found at Latency = 007
N5.C1.R0.S17: PI = 28
N3.C1.D0.R1: Preamble found for all upper nibbles, adjusting Pi, Offset to center into preamble
N5.C1.R0.S00: PI = 31
N3.C1.D0.R1.S09: Total Receive Enable Delay = 1356
N5.C1.R0.S01: PI = 34
N3.C1.D0.R1.S10: Total Receive Enable Delay = 1340
N5.C1.R0.S02: PI = 32
N3.C1.D0.R1.S11: Total Receive Enable Delay = 1308
N5.C1.R0.S03: PI = 30
N3.C1.D0.R1.S12: Total Receive Enable Delay = 1286
N5.C1.R0.S04: PI = 32
N3.C1.D0.R1.S13: Total Receive Enable Delay = 1279
N5.C1.R0.S05: PI = 31
N3.C1.D0.R1.S14: Total Receive Enable Delay = 1302
N5.C1.R0.S06: PI = 30
N3.C1.D0.R1.S15: Total Receive Enable Delay = 1328
N5.C1.R0.S07: PI = 31
N3.C1.D0.R1.S16: Total Receive Enable Delay = 1349
N5.C1.R0.S08: PI = 31
N3.C1.D0.R1.S17: Total Receive Enable Delay = 1269
N5.C1.R0.S09: PI = 34
N5.C1.R0.S10: PI = 31
N5.C1.R0.S11: PI = 31
N5.C1.R0.S12: PI = 31
START_DATA_REC_EN
N5.C1.R0.S13: PI = 31
N3.C1.S00: RdCmd2RcvEnLatency = 9, RdPtrOffsetRcvEn = 5
N5.C1.R0.S14: PI = 31
N3.C1.S01: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N5.C1.R0.S15: PI = 33
N3.C1.S02: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N5.C1.R0.S16: PI = 32
N3.C1.S03: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N5.C1.R0.S17: PI = 28
N3.C1.S04: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 5
STOP_DATA_RX_DQS
N3.C1.S05: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N5.C2.D0.R0.S00: RdDqDqs FSM results: Left = 04, Right = 63, center = 33
N3.C1.S06: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N5.C2.D0.R0.S00: RxDqsDelay = 033
N3.C1.S07: RdCmd2RcvEnLatency = 9, RdPtrOffsetRcvEn = 5
N5.C2.D0.R0.S01: RdDqDqs FSM results: Left = 05, Right = 63, center = 34
N3.C1.S08: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 5
N5.C2.D0.R0.S01: RxDqsDelay = 034
N3.C1.S09: RdCmd2RcvEnLatency = 9, RdPtrOffsetRcvEn = 5
N5.C2.D0.R0.S02: RdDqDqs FSM results: Left = 05, Right = 63, center = 34
N3.C1.S10: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N5.C2.D0.R0.S02: RxDqsDelay = 034
N3.C1.S11: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N5.C2.D0.R0.S03: RdDqDqs FSM results: Left = 06, Right = 63, center = 34
N3.C1.S12: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N5.C2.D0.R0.S03: RxDqsDelay = 034
N3.C1.S13: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 5
N5.C2.D0.R0.S04: RdDqDqs FSM results: Left = 05, Right = 63, center = 34
N3.C1.S14: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N5.C2.D0.R0.S04: RxDqsDelay = 034
N3.C1.S15: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N5.C2.D0.R0.S05: RdDqDqs FSM results: Left = 11, Right = 63, center = 37
N3.C1.S16: RdCmd2RcvEnLatency = 9, RdPtrOffsetRcvEn = 5
N5.C2.D0.R0.S05: RxDqsDelay = 037
N3.C1.S17: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 5
N5.C2.D0.R0.S06: RdDqDqs FSM results: Left = 03, Right = 63, center = 33
N3.C1.D0.R0.S00: RcvEn: plus1 = 1, minus1 = 0, PI = 12, DB = 1
N5.C2.D0.R0.S06: RxDqsDelay = 033
N3.C1.D0.R0.S01: RcvEn: plus1 = 1, minus1 = 0, PI = 57, DB = 1
N5.C2.D0.R0.S07: RdDqDqs FSM results: Left = 06, Right = 63, center = 34
N3.C1.D0.R0.S02: RcvEn: plus1 = 1, minus1 = 0, PI = 27, DB = 0
N5.C2.D0.R0.S07: RxDqsDelay = 034
N3.C1.D0.R0.S03: RcvEn: plus1 = 1, minus1 = 0, PI = 05, DB = 1
N5.C2.D0.R0.S08: RdDqDqs FSM results: Left = 05, Right = 63, center = 34
N3.C1.D0.R0.S04: RcvEn: plus1 = 1, minus1 = 0, PI = 63, DB = 1
N5.C2.D0.R0.S08: RxDqsDelay = 034
N3.C1.D0.R0.S05: RcvEn: plus1 = 1, minus1 = 0, PI = 22, DB = 0
N5.C2.D0.R0.S09: RdDqDqs FSM results: Left = 07, Right = 63, center = 35
N3.C1.D0.R0.S06: RcvEn: plus1 = 1, minus1 = 0, PI = 47, DB = 0
N5.C2.D0.R0.S09: RxDqsDelay = 035
N3.C1.D0.R0.S07: RcvEn: plus1 = 1, minus1 = 0, PI = 04, DB = 1
N5.C2.D0.R0.S10: RdDqDqs FSM results: Left = 02, Right = 63, center = 32
N3.C1.D0.R0.S08: RcvEn: plus1 = 1, minus1 = 0, PI = 53, DB = 1
N5.C2.D0.R0.S10: RxDqsDelay = 032
N3.C1.D0.R0.S09: RcvEn: plus1 = 1, minus1 = 0, PI = 12, DB = 1
N5.C2.D0.R0.S11: RdDqDqs FSM results: Left = 07, Right = 63, center = 35
N3.C1.D0.R0.S10: RcvEn: plus1 = 1, minus1 = 0, PI = 60, DB = 1
N5.C2.D0.R0.S11: RxDqsDelay = 035
N3.C1.D0.R0.S11: RcvEn: plus1 = 1, minus1 = 0, PI = 27, DB = 0
N5.C2.D0.R0.S12: RdDqDqs FSM results: Left = 10, Right = 63, center = 36
N3.C1.D0.R0.S12: RcvEn: plus1 = 1, minus1 = 0, PI = 06, DB = 1
N5.C2.D0.R0.S12: RxDqsDelay = 036
N3.C1.D0.R0.S13: RcvEn: plus1 = 0, minus1 = 1, PI = 00, DB = 1
N5.C2.D0.R0.S13: RdDqDqs FSM results: Left = 03, Right = 63, center = 33
N3.C1.D0.R0.S14: RcvEn: plus1 = 1, minus1 = 0, PI = 23, DB = 0
N5.C2.D0.R0.S13: RxDqsDelay = 033
N3.C1.D0.R0.S15: RcvEn: plus1 = 1, minus1 = 0, PI = 48, DB = 0
N5.C2.D0.R0.S14: RdDqDqs FSM results: Left = 06, Right = 63, center = 34
N3.C1.D0.R0.S16: RcvEn: plus1 = 1, minus1 = 0, PI = 06, DB = 1
N5.C2.D0.R0.S14: RxDqsDelay = 034
N3.C1.D0.R0.S17: RcvEn: plus1 = 1, minus1 = 0, PI = 52, DB = 1
N5.C2.D0.R0.S15: RdDqDqs FSM results: Left = 06, Right = 63, center = 34
N3.C1.D0.R1.S00: RcvEn: plus1 = 1, minus1 = 0, PI = 12, DB = 1
N5.C2.D0.R0.S15: RxDqsDelay = 034
N3.C1.D0.R1.S01: RcvEn: plus1 = 1, minus1 = 0, PI = 57, DB = 1
N5.C2.D0.R0.S16: RdDqDqs FSM results: Left = 04, Right = 63, center = 33
N3.C1.D0.R1.S02: RcvEn: plus1 = 1, minus1 = 0, PI = 27, DB = 0
N5.C2.D0.R0.S16: RxDqsDelay = 033
N3.C1.D0.R1.S03: RcvEn: plus1 = 1, minus1 = 0, PI = 05, DB = 1
N5.C2.D0.R0.S17: RdDqDqs FSM results: Left = 06, Right = 63, center = 34
N3.C1.D0.R1.S04: RcvEn: plus1 = 1, minus1 = 0, PI = 63, DB = 1
N5.C2.D0.R0.S17: RxDqsDelay = 034
N1.C0.D0: CalcFinalClock(89,119) = 20
N3.C1.D0.R1.S05: RcvEn: plus1 = 1, minus1 = 0, PI = 22, DB = 0
N5.C2.D0.R1.S00: RdDqDqs FSM results: Left = 04, Right = 63, center = 33
N1.C1.D0: CalcFinalClock(94,115) = 23
N3.C1.D0.R1.S06: RcvEn: plus1 = 1, minus1 = 0, PI = 47, DB = 0
N5.C2.D0.R1.S00: RxDqsDelay = 033
N1.C2.D0: CalcFinalClock(88,121) = 20
N3.C1.D0.R1.S07: RcvEn: plus1 = 1, minus1 = 0, PI = 04, DB = 1
N5.C2.D0.R1.S01: RdDqDqs FSM results: Left = 05, Right = 63, center = 34
N1.C3.D0: CalcFinalClock(94,112) = 22
N3.C1.D0.R1.S08: RcvEn: plus1 = 1, minus1 = 0, PI = 53, DB = 1
N5.C2.D0.R1.S01: RxDqsDelay = 034
N1.C0: JCK cmd timing = 3N
N3.C1.D0.R1.S09: RcvEn: plus1 = 1, minus1 = 0, PI = 12, DB = 1
N5.C2.D0.R1.S02: RdDqDqs FSM results: Left = 04, Right = 63, center = 33
N7.C0.D0: CalcFinalClock(91,120) = 23
N1.C0: RdCmd2DataValidLatency = 20, (dlyFrmS = 15, clEff = 10, earlyCas = 0, selNTiming = 2)
N3.C1.D0.R1.S10: RcvEn: plus1 = 1, minus1 = 0, PI = 60, DB = 1
N5.C2.D0.R1.S02: RxDqsDelay = 033
N7.C1.D0: CalcFinalClock(95,116) = 25
N1.C1: RdCmd2DataValidLatency = 20, (dlyFrmS = 15, clEff = 10, earlyCas = 0, selNTiming = 2)
N3.C1.D0.R1.S11: RcvEn: plus1 = 1, minus1 = 0, PI = 27, DB = 0
N5.C2.D0.R1.S03: RdDqDqs FSM results: Left = 06, Right = 63, center = 34
N7.C2.D0: CalcFinalClock(88,122) = 21
N1.C2: JCK cmd timing = 3N
N3.C1.D0.R1.S12: RcvEn: plus1 = 1, minus1 = 0, PI = 06, DB = 1
N5.C2.D0.R1.S03: RxDqsDelay = 034
N7.C3.D0: CalcFinalClock(89,118) = 20
N1.C2: RdCmd2DataValidLatency = 20, (dlyFrmS = 15, clEff = 10, earlyCas = 0, selNTiming = 2)
N3.C1.D0.R1.S13: RcvEn: plus1 = 0, minus1 = 1, PI = 00, DB = 1
N5.C2.D0.R1.S04: RdDqDqs FSM results: Left = 06, Right = 63, center = 34
N7.C0: JCK cmd timing = 3N
N1.C3: RdCmd2DataValidLatency = 20, (dlyFrmS = 15, clEff = 10, earlyCas = 0, selNTiming = 2)
N3.C1.D0.R1.S14: RcvEn: plus1 = 1, minus1 = 0, PI = 23, DB = 0
N5.C2.D0.R1.S04: RxDqsDelay = 034
N7.C0: RdCmd2DataValidLatency = 20, (dlyFrmS = 15, clEff = 10, earlyCas = 0, selNTiming = 2)
N1: RunTrainStep: Final status = 0
N3.C1.D0.R1.S15: RcvEn: plus1 = 1, minus1 = 0, PI = 48, DB = 0
N5.C2.D0.R1.S05: RdDqDqs FSM results: Left = 11, Right = 63, center = 37
N7.C1: RdCmd2DataValidLatency = 20, (dlyFrmS = 15, clEff = 10, earlyCas = 0, selNTiming = 2)

END - Early Command Training           Time         2524 ms
N3.C1.D0.R1.S16: RcvEn: plus1 = 1, minus1 = 0, PI = 06, DB = 1
N5.C2.D0.R1.S05: RxDqsDelay = 037
N7.C2: JCK cmd timing = 3N

START - Basic Read DQ/DQS Training
N3.C1.D0.R1.S17: RcvEn: plus1 = 1, minus1 = 0, PI = 52, DB = 1
N5.C2.D0.R1.S06: RdDqDqs FSM results: Left = 03, Right = 63, center = 33
N7.C2: RdCmd2DataValidLatency = 20, (dlyFrmS = 15, clEff = 10, earlyCas = 0, selNTiming = 2)
Checkpoint Code: Socket 0, 0xB7, 0x01, 0x0000
STOP_DATA_REC_EN
N5.C2.D0.R1.S06: RxDqsDelay = 033
N7.C3: RdCmd2DataValidLatency = 20, (dlyFrmS = 15, clEff = 10, earlyCas = 0, selNTiming = 2)
N1.C0: RdCmd2DataValidLatency = 20, (dlyFrmS = 15, clEff = 10, earlyCas = 0, selNTiming = 2)
N3.C2.D0.R0: RcvEnFine: Initial RdCmd2RcvEnLatency = 10, Initial RdPtrOffsetRcvEn = 4
N5.C2.D0.R1.S07: RdDqDqs FSM results: Left = 05, Right = 63, center = 34
N7: RunTrainStep: Final status = 0
N1.C0: SettingForTrainingStep: RdCmd2RcvEnLatency = 5
N3.C2.D0.R0.S00: Rcv En Fine Value = 378
N5.C2.D0.R1.S07: RxDqsDelay = 034

END - Early Command Training           Time         2632 ms
N1.C1: RdCmd2DataValidLatency = 20, (dlyFrmS = 15, clEff = 10, earlyCas = 0, selNTiming = 2)
N3.C2.D0.R0.S01: Rcv En Fine Value = 356
N5.C2.D0.R1.S08: RdDqDqs FSM results: Left = 05, Right = 63, center = 34

START - Basic Read DQ/DQS Training
N1.C1: SettingForTrainingStep: RdCmd2RcvEnLatency = 5
N3.C2.D0.R0.S02: Rcv En Fine Value = 323
N5.C2.D0.R1.S08: RxDqsDelay = 034
N7.C0: RdCmd2DataValidLatency = 20, (dlyFrmS = 15, clEff = 10, earlyCas = 0, selNTiming = 2)
N1.C2: RdCmd2DataValidLatency = 20, (dlyFrmS = 15, clEff = 10, earlyCas = 0, selNTiming = 2)
N3.C2.D0.R0.S03: Rcv En Fine Value = 307
N5.C2.D0.R1.S09: RdDqDqs FSM results: Left = 07, Right = 63, center = 35
N7.C0: SettingForTrainingStep: RdCmd2RcvEnLatency = 5
N1.C2: SettingForTrainingStep: RdCmd2RcvEnLatency = 5
N3.C2.D0.R0.S04: Rcv En Fine Value = 308
N5.C2.D0.R1.S09: RxDqsDelay = 035
N7.C1: RdCmd2DataValidLatency = 20, (dlyFrmS = 15, clEff = 10, earlyCas = 0, selNTiming = 2)
N1.C3: RdCmd2DataValidLatency = 20, (dlyFrmS = 15, clEff = 10, earlyCas = 0, selNTiming = 2)
N3.C2.D0.R0.S05: Rcv En Fine Value = 319
N5.C2.D0.R1.S10: RdDqDqs FSM results: Left = 02, Right = 63, center = 32
N7.C1: SettingForTrainingStep: RdCmd2RcvEnLatency = 5
N1.C3: SettingForTrainingStep: RdCmd2RcvEnLatency = 5
N3.C2.D0.R0.S06: Rcv En Fine Value = 358
N5.C2.D0.R1.S10: RxDqsDelay = 032
N7.C2: RdCmd2DataValidLatency = 20, (dlyFrmS = 15, clEff = 10, earlyCas = 0, selNTiming = 2)
N1.C0.D0.R0.S00: RdDqDqs FSM results: Left = 05, Right = 63, center = 34
N3.C2.D0.R0.S07: Rcv En Fine Value = 375
N5.C2.D0.R1.S11: RdDqDqs FSM results: Left = 08, Right = 63, center = 35
N7.C2: SettingForTrainingStep: RdCmd2RcvEnLatency = 5
N1.C0.D0.R0.S00: RxDqsDelay = 034
N3.C2.D0.R0.S08: Rcv En Fine Value = 295
N5.C2.D0.R1.S11: RxDqsDelay = 035
N7.C3: RdCmd2DataValidLatency = 20, (dlyFrmS = 15, clEff = 10, earlyCas = 0, selNTiming = 2)
N1.C0.D0.R0.S01: RdDqDqs FSM results: Left = 05, Right = 61, center = 33
N3.C2.D0.R0.S09: Rcv En Fine Value = 380
N5.C2.D0.R1.S12: RdDqDqs FSM results: Left = 10, Right = 63, center = 36
N7.C3: SettingForTrainingStep: RdCmd2RcvEnLatency = 5
N1.C0.D0.R0.S01: RxDqsDelay = 033
N3.C2.D0.R0.S10: Rcv En Fine Value = 355
N5.C2.D0.R1.S12: RxDqsDelay = 036
N7.C0.D0.R0.S00: RdDqDqs FSM results: Left = 07, Right = 63, center = 35
N1.C0.D0.R0.S02: RdDqDqs FSM results: Left = 08, Right = 63, center = 35
N3.C2.D0.R0.S11: Rcv En Fine Value = 324
N5.C2.D0.R1.S13: RdDqDqs FSM results: Left = 04, Right = 63, center = 33
N7.C0.D0.R0.S00: RxDqsDelay = 035
N1.C0.D0.R0.S02: RxDqsDelay = 035
N3.C2.D0.R0.S12: Rcv En Fine Value = 305
N5.C2.D0.R1.S13: RxDqsDelay = 033
N7.C0.D0.R0.S01: RdDqDqs FSM results: Left = 06, Right = 63, center = 34
N1.C0.D0.R0.S03: RdDqDqs FSM results: Left = 09, Right = 63, center = 36
N3.C2.D0.R0.S13: Rcv En Fine Value = 308
N5.C2.D0.R1.S14: RdDqDqs FSM results: Left = 05, Right = 63, center = 34
N7.C0.D0.R0.S01: RxDqsDelay = 034
N1.C0.D0.R0.S03: RxDqsDelay = 036
N3.C2.D0.R0.S14: Rcv En Fine Value = 319
N5.C2.D0.R1.S14: RxDqsDelay = 034
N7.C0.D0.R0.S02: RdDqDqs FSM results: Left = 04, Right = 63, center = 33
N1.C0.D0.R0.S04: RdDqDqs FSM results: Left = 05, Right = 63, center = 34
N3.C2.D0.R0.S15: Rcv En Fine Value = 357
N5.C2.D0.R1.S15: RdDqDqs FSM results: Left = 06, Right = 63, center = 34
N7.C0.D0.R0.S02: RxDqsDelay = 033
N1.C0.D0.R0.S04: RxDqsDelay = 034
N3.C2.D0.R0.S16: Rcv En Fine Value = 376
N5.C2.D0.R1.S15: RxDqsDelay = 034
N7.C0.D0.R0.S03: RdDqDqs FSM results: Left = 07, Right = 63, center = 35
N1.C0.D0.R0.S05: RdDqDqs FSM results: Left = 08, Right = 63, center = 35
N3.C2.D0.R0.S17: Rcv En Fine Value = 292
N5.C2.D0.R1.S16: RdDqDqs FSM results: Left = 04, Right = 63, center = 33
N7.C0.D0.R0.S03: RxDqsDelay = 035
N1.C0.D0.R0.S05: RxDqsDelay = 035
N3.C2.D0.R0: Starting preamble search lower nibbles
N5.C2.D0.R1.S16: RxDqsDelay = 033
N7.C0.D0.R0.S04: RdDqDqs FSM results: Left = 05, Right = 63, center = 34
N1.C0.D0.R0.S06: RdDqDqs FSM results: Left = 06, Right = 63, center = 34
N3.C2.D0.R0.S00: PI = 058, PtrOffset = 005
N5.C2.D0.R1.S17: RdDqDqs FSM results: Left = 07, Right = 63, center = 35
N7.C0.D0.R0.S04: RxDqsDelay = 034
N1.C0.D0.R0.S06: RxDqsDelay = 034
N3.C2.D0.R0.S01: PI = 036, PtrOffset = 005
N5.C2.D0.R1.S17: RxDqsDelay = 035
N7.C0.D0.R0.S05: RdDqDqs FSM results: Left = 09, Right = 63, center = 36
N1.C0.D0.R0.S07: RdDqDqs FSM results: Left = 06, Right = 63, center = 34
N3.C2.D0.R0.S02: PI = 003, PtrOffset = 005
START_DATA_RX_DQS
N7.C0.D0.R0.S05: RxDqsDelay = 036
N1.C0.D0.R0.S07: RxDqsDelay = 034
N3.C2.D0.R0.S03: PI = 051, PtrOffset = 004
N5.C2.R0.S00: PI = 33
N7.C0.D0.R0.S06: RdDqDqs FSM results: Left = 02, Right = 60, center = 31
N1.C0.D0.R0.S08: RdDqDqs FSM results: Left = 04, Right = 63, center = 33
N3.C2.D0.R0.S04: PI = 052, PtrOffset = 004
N5.C2.R0.S01: PI = 34
N7.C0.D0.R0.S06: RxDqsDelay = 031
N1.C0.D0.R0.S08: RxDqsDelay = 033
N3.C2.D0.R0.S05: PI = 063, PtrOffset = 004
N5.C2.R0.S02: PI = 33
N7.C0.D0.R0.S07: RdDqDqs FSM results: Left = 09, Right = 63, center = 36
N1.C0.D0.R0.S09: RdDqDqs FSM results: Left = 07, Right = 63, center = 35
N3.C2.D0.R0.S06: PI = 038, PtrOffset = 005
N5.C2.R0.S03: PI = 34
N7.C0.D0.R0.S07: RxDqsDelay = 036
N1.C0.D0.R0.S09: RxDqsDelay = 035
N3.C2.D0.R0.S07: PI = 055, PtrOffset = 005
N5.C2.R0.S04: PI = 34
N7.C0.D0.R0.S08: RdDqDqs FSM results: Left = 06, Right = 63, center = 34
N1.C0.D0.R0.S10: RdDqDqs FSM results: Left = 04, Right = 55, center = 29
N3.C2.D0.R0.S08: PI = 039, PtrOffset = 004
N5.C2.R0.S05: PI = 37
N7.C0.D0.R0.S08: RxDqsDelay = 034
N1.C0.D0.R0.S10: RxDqsDelay = 029
N3.C2.D0.R0.S00: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N5.C2.R0.S06: PI = 33
N7.C0.D0.R0.S09: RdDqDqs FSM results: Left = 05, Right = 63, center = 34
N1.C0.D0.R0.S11: RdDqDqs FSM results: Left = 05, Right = 63, center = 34
N3.C2.D0.R0.S01: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N5.C2.R0.S07: PI = 34
N7.C0.D0.R0.S09: RxDqsDelay = 034
N1.C0.D0.R0.S11: RxDqsDelay = 034
N3.C2.D0.R0.S02: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N5.C2.R0.S08: PI = 34
N7.C0.D0.R0.S10: RdDqDqs FSM results: Left = 08, Right = 63, center = 35
N1.C0.D0.R0.S12: RdDqDqs FSM results: Left = 05, Right = 63, center = 34
N3.C2.D0.R0.S03: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N5.C2.R0.S09: PI = 35
N7.C0.D0.R0.S10: RxDqsDelay = 035
N1.C0.D0.R0.S12: RxDqsDelay = 034
N3.C2.D0.R0.S04: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N5.C2.R0.S10: PI = 32
N7.C0.D0.R0.S11: RdDqDqs FSM results: Left = 06, Right = 63, center = 34
N1.C0.D0.R0.S13: RdDqDqs FSM results: Left = 07, Right = 63, center = 35
N3.C2.D0.R0.S05: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N5.C2.R0.S11: PI = 35
N7.C0.D0.R0.S11: RxDqsDelay = 034
N1.C0.D0.R0.S13: RxDqsDelay = 035
N3.C2.D0.R0.S06: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N5.C2.R0.S12: PI = 36
N7.C0.D0.R0.S12: RdDqDqs FSM results: Left = 06, Right = 63, center = 34
N1.C0.D0.R0.S14: RdDqDqs FSM results: Left = 06, Right = 63, center = 34
N3.C2.D0.R0.S07: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N5.C2.R0.S13: PI = 33
N7.C0.D0.R0.S12: RxDqsDelay = 034
N1.C0.D0.R0.S14: RxDqsDelay = 034
N3.C2.D0.R0.S08: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N5.C2.R0.S14: PI = 34
N7.C0.D0.R0.S13: RdDqDqs FSM results: Left = 09, Right = 63, center = 36
N1.C0.D0.R0.S15: RdDqDqs FSM results: Left = 05, Right = 63, center = 34
N3.C2.D0.R0.S00: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N5.C2.R0.S15: PI = 34
N7.C0.D0.R0.S13: RxDqsDelay = 036
N1.C0.D0.R0.S15: RxDqsDelay = 034
N3.C2.D0.R0.S01: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N5.C2.R0.S16: PI = 33
N7.C0.D0.R0.S14: RdDqDqs FSM results: Left = 04, Right = 63, center = 33
N1.C0.D0.R0.S16: RdDqDqs FSM results: Left = 04, Right = 63, center = 33
N3.C2.D0.R0.S02: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N5.C2.R0.S17: PI = 34
N7.C0.D0.R0.S14: RxDqsDelay = 033
N1.C0.D0.R0.S16: RxDqsDelay = 033
N3.C2.D0.R0.S03: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N5.C2.R0.S00: PI = 33
N7.C0.D0.R0.S15: RdDqDqs FSM results: Left = 04, Right = 63, center = 33
N1.C0.D0.R0.S17: RdDqDqs FSM results: Left = 09, Right = 63, center = 36
N3.C2.D0.R0.S04: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N5.C2.R0.S01: PI = 34
N7.C0.D0.R0.S15: RxDqsDelay = 033
N1.C0.D0.R0.S17: RxDqsDelay = 036
N3.C2.D0.R0.S05: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N5.C2.R0.S02: PI = 33
N7.C0.D0.R0.S16: RdDqDqs FSM results: Left = 05, Right = 63, center = 34
N1.C0.D0.R1.S00: RdDqDqs FSM results: Left = 06, Right = 63, center = 34
N3.C2.D0.R0.S06: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N5.C2.R0.S03: PI = 34
N7.C0.D0.R0.S16: RxDqsDelay = 034
N1.C0.D0.R1.S00: RxDqsDelay = 034
N3.C2.D0.R0.S07: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N5.C2.R0.S04: PI = 34
N7.C0.D0.R0.S17: RdDqDqs FSM results: Left = 09, Right = 63, center = 36
N1.C0.D0.R1.S01: RdDqDqs FSM results: Left = 05, Right = 61, center = 33
N3.C2.D0.R0.S08: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N5.C2.R0.S05: PI = 37
N7.C0.D0.R0.S17: RxDqsDelay = 036
N1.C0.D0.R1.S01: RxDqsDelay = 033
N3.C2.D0.R0.S00: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N5.C2.R0.S06: PI = 33
N7.C0.D0.R1.S00: RdDqDqs FSM results: Left = 08, Right = 63, center = 35
N1.C0.D0.R1.S02: RdDqDqs FSM results: Left = 08, Right = 63, center = 35
N3.C2.D0.R0.S01: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N5.C2.R0.S07: PI = 34
N7.C0.D0.R1.S00: RxDqsDelay = 035
N1.C0.D0.R1.S02: RxDqsDelay = 035
N3.C2.D0.R0.S02: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N5.C2.R0.S08: PI = 34
N7.C0.D0.R1.S01: RdDqDqs FSM results: Left = 07, Right = 63, center = 35
N1.C0.D0.R1.S03: RdDqDqs FSM results: Left = 09, Right = 63, center = 36
N3.C2.D0.R0.S03: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N5.C2.R0.S09: PI = 35
N7.C0.D0.R1.S01: RxDqsDelay = 035
N1.C0.D0.R1.S03: RxDqsDelay = 036
N3.C2.D0.R0.S04: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N5.C2.R0.S10: PI = 32
N7.C0.D0.R1.S02: RdDqDqs FSM results: Left = 05, Right = 63, center = 34
N1.C0.D0.R1.S04: RdDqDqs FSM results: Left = 05, Right = 63, center = 34
N3.C2.D0.R0.S05: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N5.C2.R0.S11: PI = 35
N7.C0.D0.R1.S02: RxDqsDelay = 034
N1.C0.D0.R1.S04: RxDqsDelay = 034
N3.C2.D0.R0.S06: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N5.C2.R0.S12: PI = 36
N7.C0.D0.R1.S03: RdDqDqs FSM results: Left = 07, Right = 63, center = 35
N1.C0.D0.R1.S05: RdDqDqs FSM results: Left = 08, Right = 63, center = 35
N3.C2.D0.R0.S07: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N5.C2.R0.S13: PI = 33
N7.C0.D0.R1.S03: RxDqsDelay = 035
N1.C0.D0.R1.S05: RxDqsDelay = 035
N3.C2.D0.R0.S08: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N5.C2.R0.S14: PI = 34
N7.C0.D0.R1.S04: RdDqDqs FSM results: Left = 05, Right = 63, center = 34
N1.C0.D0.R1.S06: RdDqDqs FSM results: Left = 05, Right = 63, center = 34
N3.C2.D0.R0.S00: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N5.C2.R0.S15: PI = 34
N7.C0.D0.R1.S04: RxDqsDelay = 034
N1.C0.D0.R1.S06: RxDqsDelay = 034
N3.C2.D0.R0.S01: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N5.C2.R0.S16: PI = 33
N7.C0.D0.R1.S05: RdDqDqs FSM results: Left = 08, Right = 63, center = 35
N1.C0.D0.R1.S07: RdDqDqs FSM results: Left = 05, Right = 63, center = 34
N3.C2.D0.R0.S02: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N5.C2.R0.S17: PI = 34
N7.C0.D0.R1.S05: RxDqsDelay = 035
N1.C0.D0.R1.S07: RxDqsDelay = 034
N3.C2.D0.R0.S03: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
STOP_DATA_RX_DQS
N7.C0.D0.R1.S06: RdDqDqs FSM results: Left = 03, Right = 63, center = 33
N1.C0.D0.R1.S08: RdDqDqs FSM results: Left = 05, Right = 63, center = 34
N3.C2.D0.R0.S04: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N5.C3.D0.R0.S00: RdDqDqs FSM results: Left = 08, Right = 63, center = 35
N7.C0.D0.R1.S06: RxDqsDelay = 033
N1.C0.D0.R1.S08: RxDqsDelay = 034
N3.C2.D0.R0.S05: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N5.C3.D0.R0.S00: RxDqsDelay = 035
N7.C0.D0.R1.S07: RdDqDqs FSM results: Left = 08, Right = 63, center = 35
N1.C0.D0.R1.S09: RdDqDqs FSM results: Left = 07, Right = 63, center = 35
N3.C2.D0.R0.S06: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N5.C3.D0.R0.S01: RdDqDqs FSM results: Left = 04, Right = 63, center = 33
N7.C0.D0.R1.S07: RxDqsDelay = 035
N1.C0.D0.R1.S09: RxDqsDelay = 035
N3.C2.D0.R0.S07: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N5.C3.D0.R0.S01: RxDqsDelay = 033
N7.C0.D0.R1.S08: RdDqDqs FSM results: Left = 05, Right = 63, center = 34
N1.C0.D0.R1.S10: RdDqDqs FSM results: Left = 04, Right = 56, center = 30
N3.C2.D0.R0.S08: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N5.C3.D0.R0.S02: RdDqDqs FSM results: Left = 07, Right = 63, center = 35
N7.C0.D0.R1.S08: RxDqsDelay = 034
N1.C0.D0.R1.S10: RxDqsDelay = 030
N3.C2.D0.R0.S00: Preamble found at Latency = 007
N5.C3.D0.R0.S02: RxDqsDelay = 035
N7.C0.D0.R1.S09: RdDqDqs FSM results: Left = 05, Right = 63, center = 34
N1.C0.D0.R1.S11: RdDqDqs FSM results: Left = 06, Right = 63, center = 34
N3.C2.D0.R0.S01: Preamble found at Latency = 007
N5.C3.D0.R0.S03: RdDqDqs FSM results: Left = 05, Right = 63, center = 34
N7.C0.D0.R1.S09: RxDqsDelay = 034
N1.C0.D0.R1.S11: RxDqsDelay = 034
N3.C2.D0.R0.S02: Preamble found at Latency = 007
N5.C3.D0.R0.S03: RxDqsDelay = 034
N7.C0.D0.R1.S10: RdDqDqs FSM results: Left = 08, Right = 63, center = 35
N1.C0.D0.R1.S12: RdDqDqs FSM results: Left = 05, Right = 63, center = 34
N3.C2.D0.R0.S03: Preamble found at Latency = 007
N5.C3.D0.R0.S04: RdDqDqs FSM results: Left = 08, Right = 63, center = 35
N7.C0.D0.R1.S10: RxDqsDelay = 035
N1.C0.D0.R1.S12: RxDqsDelay = 034
N3.C2.D0.R0.S04: Preamble found at Latency = 007
N5.C3.D0.R0.S04: RxDqsDelay = 035
N7.C0.D0.R1.S11: RdDqDqs FSM results: Left = 06, Right = 63, center = 34
N1.C0.D0.R1.S13: RdDqDqs FSM results: Left = 08, Right = 63, center = 35
N3.C2.D0.R0.S05: Preamble found at Latency = 007
N5.C3.D0.R0.S05: RdDqDqs FSM results: Left = 06, Right = 63, center = 34
N7.C0.D0.R1.S11: RxDqsDelay = 034
N1.C0.D0.R1.S13: RxDqsDelay = 035
N3.C2.D0.R0.S06: Preamble found at Latency = 007
N5.C3.D0.R0.S05: RxDqsDelay = 034
N7.C0.D0.R1.S12: RdDqDqs FSM results: Left = 07, Right = 63, center = 35
N1.C0.D0.R1.S14: RdDqDqs FSM results: Left = 06, Right = 63, center = 34
N3.C2.D0.R0.S07: Preamble found at Latency = 007
N5.C3.D0.R0.S06: RdDqDqs FSM results: Left = 05, Right = 63, center = 34
N7.C0.D0.R1.S12: RxDqsDelay = 035
N1.C0.D0.R1.S14: RxDqsDelay = 034
N3.C2.D0.R0.S08: Preamble found at Latency = 007
N5.C3.D0.R0.S06: RxDqsDelay = 034
N7.C0.D0.R1.S13: RdDqDqs FSM results: Left = 09, Right = 63, center = 36
N1.C0.D0.R1.S15: RdDqDqs FSM results: Left = 04, Right = 63, center = 33
N3.C2.D0.R0.S00: Total Receive Enable Delay = 1306
N5.C3.D0.R0.S07: RdDqDqs FSM results: Left = 08, Right = 63, center = 35
N7.C0.D0.R1.S13: RxDqsDelay = 036
N1.C0.D0.R1.S15: RxDqsDelay = 033
N3.C2.D0.R0.S01: Total Receive Enable Delay = 1284
N5.C3.D0.R0.S07: RxDqsDelay = 035
N7.C0.D0.R1.S14: RdDqDqs FSM results: Left = 04, Right = 63, center = 33
N1.C0.D0.R1.S16: RdDqDqs FSM results: Left = 05, Right = 59, center = 32
N3.C2.D0.R0.S02: Total Receive Enable Delay = 1251
N5.C3.D0.R0.S08: RdDqDqs FSM results: Left = 06, Right = 63, center = 34
N7.C0.D0.R1.S14: RxDqsDelay = 033
N1.C0.D0.R1.S16: RxDqsDelay = 032
N3.C2.D0.R0.S03: Total Receive Enable Delay = 1235
N5.C3.D0.R0.S08: RxDqsDelay = 034
N7.C0.D0.R1.S15: RdDqDqs FSM results: Left = 04, Right = 63, center = 33
N1.C0.D0.R1.S17: RdDqDqs FSM results: Left = 07, Right = 63, center = 35
N3.C2.D0.R0.S04: Total Receive Enable Delay = 1236
N5.C3.D0.R0.S09: RdDqDqs FSM results: Left = 10, Right = 63, center = 36
N7.C0.D0.R1.S15: RxDqsDelay = 033
N1.C0.D0.R1.S17: RxDqsDelay = 035
N3.C2.D0.R0.S05: Total Receive Enable Delay = 1247
N5.C3.D0.R0.S09: RxDqsDelay = 036
N7.C0.D0.R1.S16: RdDqDqs FSM results: Left = 05, Right = 63, center = 34
START_DATA_RX_DQS
N3.C2.D0.R0.S06: Total Receive Enable Delay = 1286
N5.C3.D0.R0.S10: RdDqDqs FSM results: Left = 03, Right = 63, center = 33
N7.C0.D0.R1.S16: RxDqsDelay = 034
N1.C0.R0.S00: PI = 34
N3.C2.D0.R0.S07: Total Receive Enable Delay = 1303
N5.C3.D0.R0.S10: RxDqsDelay = 033
N7.C0.D0.R1.S17: RdDqDqs FSM results: Left = 09, Right = 63, center = 36
N1.C0.R0.S01: PI = 33
N3.C2.D0.R0.S08: Total Receive Enable Delay = 1223
N5.C3.D0.R0.S11: RdDqDqs FSM results: Left = 04, Right = 63, center = 33
N7.C0.D0.R1.S17: RxDqsDelay = 036
N1.C0.R0.S02: PI = 35
N3.C2.D0.R0: Starting preamble search upper nibbles
N5.C3.D0.R0.S11: RxDqsDelay = 033
START_DATA_RX_DQS
N1.C0.R0.S03: PI = 36
N3.C2.D0.R0.S09: PI = 060, PtrOffset = 005
N5.C3.D0.R0.S12: RdDqDqs FSM results: Left = 05, Right = 63, center = 34
N7.C0.R0.S00: PI = 35
N1.C0.R0.S04: PI = 34
N3.C2.D0.R0.S10: PI = 035, PtrOffset = 005
N5.C3.D0.R0.S12: RxDqsDelay = 034
N7.C0.R0.S01: PI = 34
N1.C0.R0.S05: PI = 35
N3.C2.D0.R0.S11: PI = 004, PtrOffset = 005
N5.C3.D0.R0.S13: RdDqDqs FSM results: Left = 06, Right = 63, center = 34
N7.C0.R0.S02: PI = 33
N1.C0.R0.S06: PI = 34
N3.C2.D0.R0.S12: PI = 049, PtrOffset = 004
N5.C3.D0.R0.S13: RxDqsDelay = 034
N7.C0.R0.S03: PI = 35
N1.C0.R0.S07: PI = 34
N3.C2.D0.R0.S13: PI = 052, PtrOffset = 004
N5.C3.D0.R0.S14: RdDqDqs FSM results: Left = 03, Right = 63, center = 33
N7.C0.R0.S04: PI = 34
N1.C0.R0.S08: PI = 33
N3.C2.D0.R0.S14: PI = 063, PtrOffset = 004
N5.C3.D0.R0.S14: RxDqsDelay = 033
N7.C0.R0.S05: PI = 35
N1.C0.R0.S09: PI = 35
N3.C2.D0.R0.S15: PI = 037, PtrOffset = 005
N5.C3.D0.R0.S15: RdDqDqs FSM results: Left = 06, Right = 63, center = 34
N7.C0.R0.S06: PI = 32
N1.C0.R0.S10: PI = 29
N3.C2.D0.R0.S16: PI = 056, PtrOffset = 005
N5.C3.D0.R0.S15: RxDqsDelay = 034
N7.C0.R0.S07: PI = 35
N1.C0.R0.S11: PI = 34
N3.C2.D0.R0.S17: PI = 036, PtrOffset = 004
N5.C3.D0.R0.S16: RdDqDqs FSM results: Left = 04, Right = 63, center = 33
N7.C0.R0.S08: PI = 34
N1.C0.R0.S12: PI = 34
N3.C2.D0.R0.S09: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N5.C3.D0.R0.S16: RxDqsDelay = 033
N7.C0.R0.S09: PI = 34
N1.C0.R0.S13: PI = 35
N3.C2.D0.R0.S10: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N5.C3.D0.R0.S17: RdDqDqs FSM results: Left = 07, Right = 63, center = 35
N7.C0.R0.S10: PI = 35
N1.C0.R0.S14: PI = 34
N3.C2.D0.R0.S11: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N5.C3.D0.R0.S17: RxDqsDelay = 035
N7.C0.R0.S11: PI = 34
N1.C0.R0.S15: PI = 33
N3.C2.D0.R0.S12: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N5.C3.D0.R1.S00: RdDqDqs FSM results: Left = 07, Right = 63, center = 35
N7.C0.R0.S12: PI = 34
N1.C0.R0.S16: PI = 32
N3.C2.D0.R0.S13: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N5.C3.D0.R1.S00: RxDqsDelay = 035
N7.C0.R0.S13: PI = 36
N1.C0.R0.S17: PI = 35
N3.C2.D0.R0.S14: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N5.C3.D0.R1.S01: RdDqDqs FSM results: Left = 05, Right = 63, center = 34
N7.C0.R0.S14: PI = 33
N1.C0.R0.S00: PI = 34
N3.C2.D0.R0.S15: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N5.C3.D0.R1.S01: RxDqsDelay = 034
N7.C0.R0.S15: PI = 33
N1.C0.R0.S01: PI = 33
N3.C2.D0.R0.S16: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N5.C3.D0.R1.S02: RdDqDqs FSM results: Left = 06, Right = 63, center = 34
N7.C0.R0.S16: PI = 34
N1.C0.R0.S02: PI = 35
N3.C2.D0.R0.S17: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N5.C3.D0.R1.S02: RxDqsDelay = 034
N7.C0.R0.S17: PI = 36
N1.C0.R0.S03: PI = 36
N3.C2.D0.R0.S09: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N5.C3.D0.R1.S03: RdDqDqs FSM results: Left = 07, Right = 63, center = 35
N7.C0.R0.S00: PI = 35
N1.C0.R0.S04: PI = 34
N3.C2.D0.R0.S10: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N5.C3.D0.R1.S03: RxDqsDelay = 035
N7.C0.R0.S01: PI = 34
N1.C0.R0.S05: PI = 35
N3.C2.D0.R0.S11: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N5.C3.D0.R1.S04: RdDqDqs FSM results: Left = 07, Right = 63, center = 35
N7.C0.R0.S02: PI = 33
N1.C0.R0.S06: PI = 34
N3.C2.D0.R0.S12: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N5.C3.D0.R1.S04: RxDqsDelay = 035
N7.C0.R0.S03: PI = 35
N1.C0.R0.S07: PI = 34
N3.C2.D0.R0.S13: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N5.C3.D0.R1.S05: RdDqDqs FSM results: Left = 07, Right = 63, center = 35
N7.C0.R0.S04: PI = 34
N1.C0.R0.S08: PI = 33
N3.C2.D0.R0.S14: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N5.C3.D0.R1.S05: RxDqsDelay = 035
N7.C0.R0.S05: PI = 35
N1.C0.R0.S09: PI = 35
N3.C2.D0.R0.S15: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N5.C3.D0.R1.S06: RdDqDqs FSM results: Left = 05, Right = 63, center = 34
N7.C0.R0.S06: PI = 32
N1.C0.R0.S10: PI = 29
N3.C2.D0.R0.S16: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N5.C3.D0.R1.S06: RxDqsDelay = 034
N7.C0.R0.S07: PI = 35
N1.C0.R0.S11: PI = 34
N3.C2.D0.R0.S17: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N5.C3.D0.R1.S07: RdDqDqs FSM results: Left = 07, Right = 63, center = 35
N7.C0.R0.S08: PI = 34
N1.C0.R0.S12: PI = 34
N3.C2.D0.R0.S09: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N5.C3.D0.R1.S07: RxDqsDelay = 035
N7.C0.R0.S09: PI = 34
N1.C0.R0.S13: PI = 35
N3.C2.D0.R0.S10: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N5.C3.D0.R1.S08: RdDqDqs FSM results: Left = 06, Right = 63, center = 34
N7.C0.R0.S10: PI = 35
N1.C0.R0.S14: PI = 34
N3.C2.D0.R0.S11: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N5.C3.D0.R1.S08: RxDqsDelay = 034
N7.C0.R0.S11: PI = 34
N1.C0.R0.S15: PI = 33
N3.C2.D0.R0.S12: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N5.C3.D0.R1.S09: RdDqDqs FSM results: Left = 09, Right = 63, center = 36
N7.C0.R0.S12: PI = 34
N1.C0.R0.S16: PI = 32
N3.C2.D0.R0.S13: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N5.C3.D0.R1.S09: RxDqsDelay = 036
N7.C0.R0.S13: PI = 36
N1.C0.R0.S17: PI = 35
N3.C2.D0.R0.S14: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N5.C3.D0.R1.S10: RdDqDqs FSM results: Left = 03, Right = 63, center = 33
N7.C0.R0.S14: PI = 33
STOP_DATA_RX_DQS
N3.C2.D0.R0.S15: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N5.C3.D0.R1.S10: RxDqsDelay = 033
N7.C0.R0.S15: PI = 33
N1.C1.D0.R0.S00: RdDqDqs FSM results: Left = 06, Right = 63, center = 34
N3.C2.D0.R0.S16: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N5.C3.D0.R1.S11: RdDqDqs FSM results: Left = 04, Right = 63, center = 33
N7.C0.R0.S16: PI = 34
N1.C1.D0.R0.S00: RxDqsDelay = 034
N3.C2.D0.R0.S17: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N5.C3.D0.R1.S11: RxDqsDelay = 033
N7.C0.R0.S17: PI = 36
N1.C1.D0.R0.S01: RdDqDqs FSM results: Left = 06, Right = 61, center = 33
N3.C2.D0.R0.S09: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N5.C3.D0.R1.S12: RdDqDqs FSM results: Left = 05, Right = 63, center = 34
STOP_DATA_RX_DQS
N1.C1.D0.R0.S01: RxDqsDelay = 033
N3.C2.D0.R0.S10: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N5.C3.D0.R1.S12: RxDqsDelay = 034
N7.C1.D0.R0.S00: RdDqDqs FSM results: Left = 04, Right = 63, center = 33
N1.C1.D0.R0.S02: RdDqDqs FSM results: Left = 03, Right = 63, center = 33
N3.C2.D0.R0.S11: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N5.C3.D0.R1.S13: RdDqDqs FSM results: Left = 07, Right = 63, center = 35
N7.C1.D0.R0.S00: RxDqsDelay = 033
N1.C1.D0.R0.S02: RxDqsDelay = 033
N3.C2.D0.R0.S12: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N5.C3.D0.R1.S13: RxDqsDelay = 035
N7.C1.D0.R0.S01: RdDqDqs FSM results: Left = 08, Right = 63, center = 35
N1.C1.D0.R0.S03: RdDqDqs FSM results: Left = 04, Right = 63, center = 33
N3.C2.D0.R0.S13: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N5.C3.D0.R1.S14: RdDqDqs FSM results: Left = 03, Right = 63, center = 33
N7.C1.D0.R0.S01: RxDqsDelay = 035
N1.C1.D0.R0.S03: RxDqsDelay = 033
N3.C2.D0.R0.S14: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N5.C3.D0.R1.S14: RxDqsDelay = 033
N7.C1.D0.R0.S02: RdDqDqs FSM results: Left = 04, Right = 63, center = 33
N1.C1.D0.R0.S04: RdDqDqs FSM results: Left = 05, Right = 63, center = 34
N3.C2.D0.R0.S15: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N5.C3.D0.R1.S15: RdDqDqs FSM results: Left = 05, Right = 63, center = 34
N7.C1.D0.R0.S02: RxDqsDelay = 033
N1.C1.D0.R0.S04: RxDqsDelay = 034
N3.C2.D0.R0.S16: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N5.C3.D0.R1.S15: RxDqsDelay = 034
N7.C1.D0.R0.S03: RdDqDqs FSM results: Left = 05, Right = 63, center = 34
N1.C1.D0.R0.S05: RdDqDqs FSM results: Left = 06, Right = 63, center = 34
N3.C2.D0.R0.S17: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N5.C3.D0.R1.S16: RdDqDqs FSM results: Left = 05, Right = 63, center = 34
N7.C1.D0.R0.S03: RxDqsDelay = 034
N1.C1.D0.R0.S05: RxDqsDelay = 034
N3.C2.D0.R0.S09: Preamble found at Latency = 007
N5.C3.D0.R1.S16: RxDqsDelay = 034
N7.C1.D0.R0.S04: RdDqDqs FSM results: Left = 03, Right = 63, center = 33
N1.C1.D0.R0.S06: RdDqDqs FSM results: Left = 03, Right = 63, center = 33
N3.C2.D0.R0.S10: Preamble found at Latency = 007
N5.C3.D0.R1.S17: RdDqDqs FSM results: Left = 07, Right = 63, center = 35
N7.C1.D0.R0.S04: RxDqsDelay = 033
N1.C1.D0.R0.S06: RxDqsDelay = 033
N3.C2.D0.R0.S11: Preamble found at Latency = 007
N5.C3.D0.R1.S17: RxDqsDelay = 035
N7.C1.D0.R0.S05: RdDqDqs FSM results: Left = 04, Right = 63, center = 33
N1.C1.D0.R0.S07: RdDqDqs FSM results: Left = 05, Right = 63, center = 34
N3.C2.D0.R0.S12: Preamble found at Latency = 007
START_DATA_RX_DQS
N7.C1.D0.R0.S05: RxDqsDelay = 033
N1.C1.D0.R0.S07: RxDqsDelay = 034
N3.C2.D0.R0.S13: Preamble found at Latency = 007
N5.C3.R0.S00: PI = 35
N7.C1.D0.R0.S06: RdDqDqs FSM results: Left = 06, Right = 63, center = 34
N1.C1.D0.R0.S08: RdDqDqs FSM results: Left = 05, Right = 63, center = 34
N3.C2.D0.R0.S14: Preamble found at Latency = 007
N5.C3.R0.S01: PI = 33
N7.C1.D0.R0.S06: RxDqsDelay = 034
N1.C1.D0.R0.S08: RxDqsDelay = 034
N3.C2.D0.R0.S15: Preamble found at Latency = 007
N5.C3.R0.S02: PI = 34
N7.C1.D0.R0.S07: RdDqDqs FSM results: Left = 04, Right = 63, center = 33
N1.C1.D0.R0.S09: RdDqDqs FSM results: Left = 09, Right = 63, center = 36
N3.C2.D0.R0.S16: Preamble found at Latency = 007
N5.C3.R0.S03: PI = 34
N7.C1.D0.R0.S07: RxDqsDelay = 033
N1.C1.D0.R0.S09: RxDqsDelay = 036
N3.C2.D0.R0.S17: Preamble found at Latency = 007
N5.C3.R0.S04: PI = 35
N7.C1.D0.R0.S08: RdDqDqs FSM results: Left = 04, Right = 63, center = 33
N1.C1.D0.R0.S10: RdDqDqs FSM results: Left = 06, Right = 60, center = 33
N3.C2.D0.R0: Preamble found for all upper nibbles, adjusting Pi, Offset to center into preamble
N5.C3.R0.S05: PI = 34
N7.C1.D0.R0.S08: RxDqsDelay = 033
N1.C1.D0.R0.S10: RxDqsDelay = 033
N3.C2.D0.R0.S09: Total Receive Enable Delay = 1308
N5.C3.R0.S06: PI = 34
N7.C1.D0.R0.S09: RdDqDqs FSM results: Left = 05, Right = 63, center = 34
N1.C1.D0.R0.S11: RdDqDqs FSM results: Left = 05, Right = 63, center = 34
N3.C2.D0.R0.S10: Total Receive Enable Delay = 1283
N5.C3.R0.S07: PI = 35
N7.C1.D0.R0.S09: RxDqsDelay = 034
N1.C1.D0.R0.S11: RxDqsDelay = 034
N3.C2.D0.R0.S11: Total Receive Enable Delay = 1252
N5.C3.R0.S08: PI = 34
N7.C1.D0.R0.S10: RdDqDqs FSM results: Left = 07, Right = 63, center = 35
N1.C1.D0.R0.S12: RdDqDqs FSM results: Left = 03, Right = 63, center = 33
N3.C2.D0.R0.S12: Total Receive Enable Delay = 1233
N5.C3.R0.S09: PI = 36
N7.C1.D0.R0.S10: RxDqsDelay = 035
N1.C1.D0.R0.S12: RxDqsDelay = 033
N3.C2.D0.R0.S13: Total Receive Enable Delay = 1236
N5.C3.R0.S10: PI = 33
N7.C1.D0.R0.S11: RdDqDqs FSM results: Left = 03, Right = 60, center = 31
N1.C1.D0.R0.S13: RdDqDqs FSM results: Left = 04, Right = 57, center = 30
N3.C2.D0.R0.S14: Total Receive Enable Delay = 1247
N5.C3.R0.S11: PI = 33
N7.C1.D0.R0.S11: RxDqsDelay = 031
N1.C1.D0.R0.S13: RxDqsDelay = 030
N3.C2.D0.R0.S15: Total Receive Enable Delay = 1285
N5.C3.R0.S12: PI = 34
N7.C1.D0.R0.S12: RdDqDqs FSM results: Left = 04, Right = 60, center = 32
N1.C1.D0.R0.S14: RdDqDqs FSM results: Left = 07, Right = 63, center = 35
N3.C2.D0.R0.S16: Total Receive Enable Delay = 1304
N5.C3.R0.S13: PI = 34
N7.C1.D0.R0.S12: RxDqsDelay = 032
N1.C1.D0.R0.S14: RxDqsDelay = 035
N3.C2.D0.R0.S17: Total Receive Enable Delay = 1220
N5.C3.R0.S14: PI = 33
N7.C1.D0.R0.S13: RdDqDqs FSM results: Left = 05, Right = 63, center = 34
N1.C1.D0.R0.S15: RdDqDqs FSM results: Left = 04, Right = 63, center = 33
N3.C2.D0.R1: RcvEnFine: Initial RdCmd2RcvEnLatency = 10, Initial RdPtrOffsetRcvEn = 4
N5.C3.R0.S15: PI = 34
N7.C1.D0.R0.S13: RxDqsDelay = 034
N1.C1.D0.R0.S15: RxDqsDelay = 033
N3.C2.D0.R1.S00: Rcv En Fine Value = 380
N5.C3.R0.S16: PI = 33
N7.C1.D0.R0.S14: RdDqDqs FSM results: Left = 04, Right = 63, center = 33
N1.C1.D0.R0.S16: RdDqDqs FSM results: Left = 08, Right = 63, center = 35
N3.C2.D0.R1.S01: Rcv En Fine Value = 355
N5.C3.R0.S17: PI = 35
N7.C1.D0.R0.S14: RxDqsDelay = 033
N1.C1.D0.R0.S16: RxDqsDelay = 035
N3.C2.D0.R1.S02: Rcv En Fine Value = 324
N5.C3.R0.S00: PI = 35
N7.C1.D0.R0.S15: RdDqDqs FSM results: Left = 05, Right = 63, center = 34
N1.C1.D0.R0.S17: RdDqDqs FSM results: Left = 03, Right = 60, center = 31
N3.C2.D0.R1.S03: Rcv En Fine Value = 307
N5.C3.R0.S01: PI = 33
N7.C1.D0.R0.S15: RxDqsDelay = 034
N1.C1.D0.R0.S17: RxDqsDelay = 031
N3.C2.D0.R1.S04: Rcv En Fine Value = 307
N5.C3.R0.S02: PI = 34
N7.C1.D0.R0.S16: RdDqDqs FSM results: Left = 06, Right = 63, center = 34
N1.C1.D0.R1.S00: RdDqDqs FSM results: Left = 07, Right = 63, center = 35
N3.C2.D0.R1.S05: Rcv En Fine Value = 318
N5.C3.R0.S03: PI = 34
N7.C1.D0.R0.S16: RxDqsDelay = 034
N1.C1.D0.R1.S00: RxDqsDelay = 035
N3.C2.D0.R1.S06: Rcv En Fine Value = 356
N5.C3.R0.S04: PI = 35
N7.C1.D0.R0.S17: RdDqDqs FSM results: Left = 04, Right = 60, center = 32
N1.C1.D0.R1.S01: RdDqDqs FSM results: Left = 06, Right = 63, center = 34
N3.C2.D0.R1.S07: Rcv En Fine Value = 376
N5.C3.R0.S05: PI = 34
N7.C1.D0.R0.S17: RxDqsDelay = 032
N1.C1.D0.R1.S01: RxDqsDelay = 034
N3.C2.D0.R1.S08: Rcv En Fine Value = 291
N5.C3.R0.S06: PI = 34
N7.C1.D0.R1.S00: RdDqDqs FSM results: Left = 04, Right = 63, center = 33
N1.C1.D0.R1.S02: RdDqDqs FSM results: Left = 03, Right = 63, center = 33
N3.C2.D0.R1.S09: Rcv En Fine Value = 381
N5.C3.R0.S07: PI = 35
N7.C1.D0.R1.S00: RxDqsDelay = 033
N1.C1.D0.R1.S02: RxDqsDelay = 033
N3.C2.D0.R1.S10: Rcv En Fine Value = 355
N5.C3.R0.S08: PI = 34
N7.C1.D0.R1.S01: RdDqDqs FSM results: Left = 08, Right = 63, center = 35
N1.C1.D0.R1.S03: RdDqDqs FSM results: Left = 06, Right = 63, center = 34
N3.C2.D0.R1.S11: Rcv En Fine Value = 324
N5.C3.R0.S09: PI = 36
N7.C1.D0.R1.S01: RxDqsDelay = 035
N1.C1.D0.R1.S03: RxDqsDelay = 034
N3.C2.D0.R1.S12: Rcv En Fine Value = 306
N5.C3.R0.S10: PI = 33
N7.C1.D0.R1.S02: RdDqDqs FSM results: Left = 04, Right = 63, center = 33
N1.C1.D0.R1.S04: RdDqDqs FSM results: Left = 04, Right = 63, center = 33
N3.C2.D0.R1.S13: Rcv En Fine Value = 307
N5.C3.R0.S11: PI = 33
N7.C1.D0.R1.S02: RxDqsDelay = 033
N1.C1.D0.R1.S04: RxDqsDelay = 033
N3.C2.D0.R1.S14: Rcv En Fine Value = 320
N5.C3.R0.S12: PI = 34
N7.C1.D0.R1.S03: RdDqDqs FSM results: Left = 06, Right = 63, center = 34
N1.C1.D0.R1.S05: RdDqDqs FSM results: Left = 05, Right = 63, center = 34
N3.C2.D0.R1.S15: Rcv En Fine Value = 359
N5.C3.R0.S13: PI = 34
N7.C1.D0.R1.S03: RxDqsDelay = 034
N1.C1.D0.R1.S05: RxDqsDelay = 034
N3.C2.D0.R1.S16: Rcv En Fine Value = 374
N5.C3.R0.S14: PI = 33
N7.C1.D0.R1.S04: RdDqDqs FSM results: Left = 03, Right = 63, center = 33
N1.C1.D0.R1.S06: RdDqDqs FSM results: Left = 04, Right = 63, center = 33
N3.C2.D0.R1.S17: Rcv En Fine Value = 291
N5.C3.R0.S15: PI = 34
N7.C1.D0.R1.S04: RxDqsDelay = 033
N1.C1.D0.R1.S06: RxDqsDelay = 033
N3.C2.D0.R1: Starting preamble search lower nibbles
N5.C3.R0.S16: PI = 33
N7.C1.D0.R1.S05: RdDqDqs FSM results: Left = 04, Right = 63, center = 33
N1.C1.D0.R1.S07: RdDqDqs FSM results: Left = 05, Right = 63, center = 34
N3.C2.D0.R1.S00: PI = 060, PtrOffset = 005
N5.C3.R0.S17: PI = 35
N7.C1.D0.R1.S05: RxDqsDelay = 033
N1.C1.D0.R1.S07: RxDqsDelay = 034
N3.C2.D0.R1.S01: PI = 035, PtrOffset = 005
STOP_DATA_RX_DQS
N7.C1.D0.R1.S06: RdDqDqs FSM results: Left = 06, Right = 63, center = 34
N1.C1.D0.R1.S08: RdDqDqs FSM results: Left = 05, Right = 59, center = 32
N3.C2.D0.R1.S02: PI = 004, PtrOffset = 005
N5: RunTrainStep: Final status = 0
N7.C1.D0.R1.S06: RxDqsDelay = 034
N1.C1.D0.R1.S08: RxDqsDelay = 032
N3.C2.D0.R1.S03: PI = 051, PtrOffset = 004

END - Basic Read DQ/DQS Training       Time         7765 ms
N7.C1.D0.R1.S07: RdDqDqs FSM results: Left = 04, Right = 63, center = 33
N1.C1.D0.R1.S09: RdDqDqs FSM results: Left = 09, Right = 63, center = 36
N3.C2.D0.R1.S04: PI = 051, PtrOffset = 004

START - Basic Receive Enable Training
N7.C1.D0.R1.S07: RxDqsDelay = 033
N1.C1.D0.R1.S09: RxDqsDelay = 036
N3.C2.D0.R1.S05: PI = 062, PtrOffset = 004
N5.C0: QCRM debug: extraRcvEnLatency = 0
N7.C1.D0.R1.S08: RdDqDqs FSM results: Left = 03, Right = 61, center = 32
N1.C1.D0.R1.S10: RdDqDqs FSM results: Left = 06, Right = 63, center = 34
N3.C2.D0.R1.S06: PI = 036, PtrOffset = 005
N5.C0: SettingForTrainingStep: RdCmd2RcvEnLatency = 10, RdPtrOffsetRcvEn = 4
N7.C1.D0.R1.S08: RxDqsDelay = 032
N1.C1.D0.R1.S10: RxDqsDelay = 034
N3.C2.D0.R1.S07: PI = 056, PtrOffset = 005
N5.C1: QCRM debug: extraRcvEnLatency = 0
N7.C1.D0.R1.S09: RdDqDqs FSM results: Left = 06, Right = 63, center = 34
N1.C1.D0.R1.S11: RdDqDqs FSM results: Left = 05, Right = 63, center = 34
N3.C2.D0.R1.S08: PI = 035, PtrOffset = 004
N5.C1: SettingForTrainingStep: RdCmd2RcvEnLatency = 10, RdPtrOffsetRcvEn = 4
N7.C1.D0.R1.S09: RxDqsDelay = 034
N1.C1.D0.R1.S11: RxDqsDelay = 034
N3.C2.D0.R1.S00: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N5.C2: QCRM debug: extraRcvEnLatency = 0
N7.C1.D0.R1.S10: RdDqDqs FSM results: Left = 07, Right = 63, center = 35
N1.C1.D0.R1.S12: RdDqDqs FSM results: Left = 03, Right = 63, center = 33
N3.C2.D0.R1.S01: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N5.C2: SettingForTrainingStep: RdCmd2RcvEnLatency = 10, RdPtrOffsetRcvEn = 4
N7.C1.D0.R1.S10: RxDqsDelay = 035
N1.C1.D0.R1.S12: RxDqsDelay = 033
N3.C2.D0.R1.S02: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N5.C3: QCRM debug: extraRcvEnLatency = 0
N7.C1.D0.R1.S11: RdDqDqs FSM results: Left = 03, Right = 63, center = 33
N1.C1.D0.R1.S13: RdDqDqs FSM results: Left = 04, Right = 59, center = 31
N3.C2.D0.R1.S03: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N5.C3: SettingForTrainingStep: RdCmd2RcvEnLatency = 10, RdPtrOffsetRcvEn = 4
N7.C1.D0.R1.S11: RxDqsDelay = 033
N1.C1.D0.R1.S13: RxDqsDelay = 031
N3.C2.D0.R1.S04: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N5.C0.D0.R0: RcvEnFine: Initial RdCmd2RcvEnLatency = 10, Initial RdPtrOffsetRcvEn = 4
N7.C1.D0.R1.S12: RdDqDqs FSM results: Left = 05, Right = 63, center = 34
N1.C1.D0.R1.S14: RdDqDqs FSM results: Left = 06, Right = 63, center = 34
N3.C2.D0.R1.S05: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N5.C0.D0.R0.S00: Rcv En Fine Value = 376
N7.C1.D0.R1.S12: RxDqsDelay = 034
N1.C1.D0.R1.S14: RxDqsDelay = 034
N3.C2.D0.R1.S06: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N5.C0.D0.R0.S01: Rcv En Fine Value = 357
N7.C1.D0.R1.S13: RdDqDqs FSM results: Left = 05, Right = 63, center = 34
N1.C1.D0.R1.S15: RdDqDqs FSM results: Left = 04, Right = 63, center = 33
N3.C2.D0.R1.S07: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N5.C0.D0.R0.S02: Rcv En Fine Value = 327
N7.C1.D0.R1.S13: RxDqsDelay = 034
N1.C1.D0.R1.S15: RxDqsDelay = 033
N3.C2.D0.R1.S08: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N5.C0.D0.R0.S03: Rcv En Fine Value = 308
N7.C1.D0.R1.S14: RdDqDqs FSM results: Left = 04, Right = 63, center = 33
N1.C1.D0.R1.S16: RdDqDqs FSM results: Left = 07, Right = 63, center = 35
N3.C2.D0.R1.S00: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N5.C0.D0.R0.S04: Rcv En Fine Value = 304
N7.C1.D0.R1.S14: RxDqsDelay = 033
N1.C1.D0.R1.S16: RxDqsDelay = 035
N3.C2.D0.R1.S01: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N5.C0.D0.R0.S05: Rcv En Fine Value = 326
N7.C1.D0.R1.S15: RdDqDqs FSM results: Left = 05, Right = 63, center = 34
N1.C1.D0.R1.S17: RdDqDqs FSM results: Left = 03, Right = 61, center = 32
N3.C2.D0.R1.S02: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N5.C0.D0.R0.S06: Rcv En Fine Value = 360
N7.C1.D0.R1.S15: RxDqsDelay = 034
N1.C1.D0.R1.S17: RxDqsDelay = 032
N3.C2.D0.R1.S03: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N5.C0.D0.R0.S07: Rcv En Fine Value = 382
N7.C1.D0.R1.S16: RdDqDqs FSM results: Left = 05, Right = 63, center = 34
START_DATA_RX_DQS
N3.C2.D0.R1.S04: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N5.C0.D0.R0.S08: Rcv En Fine Value = 295
N7.C1.D0.R1.S16: RxDqsDelay = 034
N1.C1.R0.S00: PI = 34
N3.C2.D0.R1.S05: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N5.C0.D0.R0.S09: Rcv En Fine Value = 376
N7.C1.D0.R1.S17: RdDqDqs FSM results: Left = 03, Right = 61, center = 32
N1.C1.R0.S01: PI = 33
N3.C2.D0.R1.S06: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N5.C0.D0.R0.S10: Rcv En Fine Value = 357
N7.C1.D0.R1.S17: RxDqsDelay = 032
N1.C1.R0.S02: PI = 33
N3.C2.D0.R1.S07: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N5.C0.D0.R0.S11: Rcv En Fine Value = 328
START_DATA_RX_DQS
N1.C1.R0.S03: PI = 33
N3.C2.D0.R1.S08: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N5.C0.D0.R0.S12: Rcv En Fine Value = 307
N7.C1.R0.S00: PI = 33
N1.C1.R0.S04: PI = 33
N3.C2.D0.R1.S00: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N5.C0.D0.R0.S13: Rcv En Fine Value = 303
N7.C1.R0.S01: PI = 35
N1.C1.R0.S05: PI = 34
N3.C2.D0.R1.S01: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N5.C0.D0.R0.S14: Rcv En Fine Value = 325
N7.C1.R0.S02: PI = 33
N1.C1.R0.S06: PI = 33
N3.C2.D0.R1.S02: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N5.C0.D0.R0.S15: Rcv En Fine Value = 359
N7.C1.R0.S03: PI = 34
N1.C1.R0.S07: PI = 34
N3.C2.D0.R1.S03: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N5.C0.D0.R0.S16: Rcv En Fine Value = 379
N7.C1.R0.S04: PI = 33
N1.C1.R0.S08: PI = 33
N3.C2.D0.R1.S04: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N5.C0.D0.R0.S17: Rcv En Fine Value = 296
N7.C1.R0.S05: PI = 33
N1.C1.R0.S09: PI = 36
N3.C2.D0.R1.S05: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N5.C0.D0.R0: Starting preamble search lower nibbles
N7.C1.R0.S06: PI = 34
N1.C1.R0.S10: PI = 33
N3.C2.D0.R1.S06: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N5.C0.D0.R0.S00: PI = 056, PtrOffset = 005
N7.C1.R0.S07: PI = 33
N1.C1.R0.S11: PI = 34
N3.C2.D0.R1.S07: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N5.C0.D0.R0.S01: PI = 037, PtrOffset = 005
N7.C1.R0.S08: PI = 32
N1.C1.R0.S12: PI = 33
N3.C2.D0.R1.S08: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N5.C0.D0.R0.S02: PI = 007, PtrOffset = 005
N7.C1.R0.S09: PI = 34
N1.C1.R0.S13: PI = 30
N3.C2.D0.R1.S00: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N5.C0.D0.R0.S03: PI = 052, PtrOffset = 004
N7.C1.R0.S10: PI = 35
N1.C1.R0.S14: PI = 34
N3.C2.D0.R1.S01: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N5.C0.D0.R0.S04: PI = 048, PtrOffset = 004
N7.C1.R0.S11: PI = 32
N1.C1.R0.S15: PI = 33
N3.C2.D0.R1.S02: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N5.C0.D0.R0.S05: PI = 006, PtrOffset = 005
N7.C1.R0.S12: PI = 33
N1.C1.R0.S16: PI = 35
N3.C2.D0.R1.S03: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N5.C0.D0.R0.S06: PI = 040, PtrOffset = 005
N7.C1.R0.S13: PI = 34
N1.C1.R0.S17: PI = 31
N3.C2.D0.R1.S04: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N5.C0.D0.R0.S07: PI = 062, PtrOffset = 005
N7.C1.R0.S14: PI = 33
N1.C1.R0.S00: PI = 34
N3.C2.D0.R1.S05: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N5.C0.D0.R0.S08: PI = 039, PtrOffset = 004
N7.C1.R0.S15: PI = 34
N1.C1.R0.S01: PI = 33
N3.C2.D0.R1.S06: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N5.C0.D0.R0.S00: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N7.C1.R0.S16: PI = 34
N1.C1.R0.S02: PI = 33
N3.C2.D0.R1.S07: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N5.C0.D0.R0.S01: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N7.C1.R0.S17: PI = 32
N1.C1.R0.S03: PI = 33
N3.C2.D0.R1.S08: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N5.C0.D0.R0.S02: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N7.C1.R0.S00: PI = 33
N1.C1.R0.S04: PI = 33
N3.C2.D0.R1.S00: Preamble found at Latency = 007
N5.C0.D0.R0.S03: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N7.C1.R0.S01: PI = 35
N1.C1.R0.S05: PI = 34
N3.C2.D0.R1.S01: Preamble found at Latency = 007
N5.C0.D0.R0.S04: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N7.C1.R0.S02: PI = 33
N1.C1.R0.S06: PI = 33
N3.C2.D0.R1.S02: Preamble found at Latency = 007
N5.C0.D0.R0.S05: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N7.C1.R0.S03: PI = 34
N1.C1.R0.S07: PI = 34
N3.C2.D0.R1.S03: Preamble found at Latency = 007
N5.C0.D0.R0.S06: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N7.C1.R0.S04: PI = 33
N1.C1.R0.S08: PI = 33
N3.C2.D0.R1.S04: Preamble found at Latency = 007
N5.C0.D0.R0.S07: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N7.C1.R0.S05: PI = 33
N1.C1.R0.S09: PI = 36
N3.C2.D0.R1.S05: Preamble found at Latency = 007
N5.C0.D0.R0.S08: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N7.C1.R0.S06: PI = 34
N1.C1.R0.S10: PI = 33
N3.C2.D0.R1.S06: Preamble found at Latency = 007
N5.C0.D0.R0.S00: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N7.C1.R0.S07: PI = 33
N1.C1.R0.S11: PI = 34
N3.C2.D0.R1.S07: Preamble found at Latency = 007
N5.C0.D0.R0.S01: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N7.C1.R0.S08: PI = 32
N1.C1.R0.S12: PI = 33
N3.C2.D0.R1.S08: Preamble found at Latency = 007
N5.C0.D0.R0.S02: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N7.C1.R0.S09: PI = 34
N1.C1.R0.S13: PI = 30
N3.C2.D0.R1.S00: Total Receive Enable Delay = 1308
N5.C0.D0.R0.S03: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N7.C1.R0.S10: PI = 35
N1.C1.R0.S14: PI = 34
N3.C2.D0.R1.S01: Total Receive Enable Delay = 1283
N5.C0.D0.R0.S04: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N7.C1.R0.S11: PI = 32
N1.C1.R0.S15: PI = 33
N3.C2.D0.R1.S02: Total Receive Enable Delay = 1252
N5.C0.D0.R0.S05: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N7.C1.R0.S12: PI = 33
N1.C1.R0.S16: PI = 35
N3.C2.D0.R1.S03: Total Receive Enable Delay = 1235
N5.C0.D0.R0.S06: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N7.C1.R0.S13: PI = 34
N1.C1.R0.S17: PI = 31
N3.C2.D0.R1.S04: Total Receive Enable Delay = 1235
N5.C0.D0.R0.S07: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N7.C1.R0.S14: PI = 33
STOP_DATA_RX_DQS
N3.C2.D0.R1.S05: Total Receive Enable Delay = 1246
N5.C0.D0.R0.S08: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N7.C1.R0.S15: PI = 34
N1.C2.D0.R0.S00: RdDqDqs FSM results: Left = 04, Right = 63, center = 33
N3.C2.D0.R1.S06: Total Receive Enable Delay = 1284
N5.C0.D0.R0.S00: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N7.C1.R0.S16: PI = 34
N1.C2.D0.R0.S00: RxDqsDelay = 033
N3.C2.D0.R1.S07: Total Receive Enable Delay = 1304
N5.C0.D0.R0.S01: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N7.C1.R0.S17: PI = 32
N1.C2.D0.R0.S01: RdDqDqs FSM results: Left = 07, Right = 63, center = 35
N3.C2.D0.R1.S08: Total Receive Enable Delay = 1219
N5.C0.D0.R0.S02: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
STOP_DATA_RX_DQS
N1.C2.D0.R0.S01: RxDqsDelay = 035
N3.C2.D0.R1: Starting preamble search upper nibbles
N5.C0.D0.R0.S03: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N7.C2.D0.R0.S00: RdDqDqs FSM results: Left = 04, Right = 63, center = 33
N1.C2.D0.R0.S02: RdDqDqs FSM results: Left = 07, Right = 63, center = 35
N3.C2.D0.R1.S09: PI = 061, PtrOffset = 005
N5.C0.D0.R0.S04: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N7.C2.D0.R0.S00: RxDqsDelay = 033
N1.C2.D0.R0.S02: RxDqsDelay = 035
N3.C2.D0.R1.S10: PI = 035, PtrOffset = 005
N5.C0.D0.R0.S05: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N7.C2.D0.R0.S01: RdDqDqs FSM results: Left = 07, Right = 63, center = 35
N1.C2.D0.R0.S03: RdDqDqs FSM results: Left = 05, Right = 63, center = 34
N3.C2.D0.R1.S11: PI = 004, PtrOffset = 005
N5.C0.D0.R0.S06: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N7.C2.D0.R0.S01: RxDqsDelay = 035
N1.C2.D0.R0.S03: RxDqsDelay = 034
N3.C2.D0.R1.S12: PI = 050, PtrOffset = 004
N5.C0.D0.R0.S07: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N7.C2.D0.R0.S02: RdDqDqs FSM results: Left = 05, Right = 63, center = 34
N1.C2.D0.R0.S04: RdDqDqs FSM results: Left = 04, Right = 63, center = 33
N3.C2.D0.R1.S13: PI = 051, PtrOffset = 004
N5.C0.D0.R0.S08: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N7.C2.D0.R0.S02: RxDqsDelay = 034
N1.C2.D0.R0.S04: RxDqsDelay = 033
N3.C2.D0.R1.S14: PI = 000, PtrOffset = 005
N5.C0.D0.R0.S00: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N7.C2.D0.R0.S03: RdDqDqs FSM results: Left = 05, Right = 63, center = 34
N1.C2.D0.R0.S05: RdDqDqs FSM results: Left = 09, Right = 63, center = 36
N3.C2.D0.R1.S15: PI = 039, PtrOffset = 005
N5.C0.D0.R0.S01: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N7.C2.D0.R0.S03: RxDqsDelay = 034
N1.C2.D0.R0.S05: RxDqsDelay = 036
N3.C2.D0.R1.S16: PI = 054, PtrOffset = 005
N5.C0.D0.R0.S02: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N7.C2.D0.R0.S04: RdDqDqs FSM results: Left = 05, Right = 63, center = 34
N1.C2.D0.R0.S06: RdDqDqs FSM results: Left = 08, Right = 63, center = 35
N3.C2.D0.R1.S17: PI = 035, PtrOffset = 004
N5.C0.D0.R0.S03: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N7.C2.D0.R0.S04: RxDqsDelay = 034
N1.C2.D0.R0.S06: RxDqsDelay = 035
N3.C2.D0.R1.S09: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N5.C0.D0.R0.S04: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N7.C2.D0.R0.S05: RdDqDqs FSM results: Left = 09, Right = 63, center = 36
N1.C2.D0.R0.S07: RdDqDqs FSM results: Left = 08, Right = 63, center = 35
N3.C2.D0.R1.S10: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N5.C0.D0.R0.S05: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N7.C2.D0.R0.S05: RxDqsDelay = 036
N1.C2.D0.R0.S07: RxDqsDelay = 035
N3.C2.D0.R1.S11: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N5.C0.D0.R0.S06: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N7.C2.D0.R0.S06: RdDqDqs FSM results: Left = 07, Right = 63, center = 35
N1.C2.D0.R0.S08: RdDqDqs FSM results: Left = 06, Right = 63, center = 34
N3.C2.D0.R1.S12: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N5.C0.D0.R0.S07: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N7.C2.D0.R0.S06: RxDqsDelay = 035
N1.C2.D0.R0.S08: RxDqsDelay = 034
N3.C2.D0.R1.S13: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N5.C0.D0.R0.S08: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N7.C2.D0.R0.S07: RdDqDqs FSM results: Left = 04, Right = 59, center = 31
N1.C2.D0.R0.S09: RdDqDqs FSM results: Left = 07, Right = 63, center = 35
N3.C2.D0.R1.S14: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N5.C0.D0.R0.S00: Preamble found at Latency = 007
N7.C2.D0.R0.S07: RxDqsDelay = 031
N1.C2.D0.R0.S09: RxDqsDelay = 035
N3.C2.D0.R1.S15: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N5.C0.D0.R0.S01: Preamble found at Latency = 007
N7.C2.D0.R0.S08: RdDqDqs FSM results: Left = 07, Right = 63, center = 35
N1.C2.D0.R0.S10: RdDqDqs FSM results: Left = 04, Right = 63, center = 33
N3.C2.D0.R1.S16: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N5.C0.D0.R0.S02: Preamble found at Latency = 007
N7.C2.D0.R0.S08: RxDqsDelay = 035
N1.C2.D0.R0.S10: RxDqsDelay = 033
N3.C2.D0.R1.S17: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N5.C0.D0.R0.S03: Preamble found at Latency = 007
N7.C2.D0.R0.S09: RdDqDqs FSM results: Left = 04, Right = 61, center = 32
N1.C2.D0.R0.S11: RdDqDqs FSM results: Left = 07, Right = 63, center = 35
N3.C2.D0.R1.S09: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N5.C0.D0.R0.S04: Preamble found at Latency = 007
N7.C2.D0.R0.S09: RxDqsDelay = 032
N1.C2.D0.R0.S11: RxDqsDelay = 035
N3.C2.D0.R1.S10: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N5.C0.D0.R0.S05: Preamble found at Latency = 007
N7.C2.D0.R0.S10: RdDqDqs FSM results: Left = 07, Right = 63, center = 35
N1.C2.D0.R0.S12: RdDqDqs FSM results: Left = 07, Right = 63, center = 35
N3.C2.D0.R1.S11: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N5.C0.D0.R0.S06: Preamble found at Latency = 007
N7.C2.D0.R0.S10: RxDqsDelay = 035
N1.C2.D0.R0.S12: RxDqsDelay = 035
N3.C2.D0.R1.S12: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N5.C0.D0.R0.S07: Preamble found at Latency = 007
N7.C2.D0.R0.S11: RdDqDqs FSM results: Left = 03, Right = 63, center = 33
N1.C2.D0.R0.S13: RdDqDqs FSM results: Left = 03, Right = 63, center = 33
N3.C2.D0.R1.S13: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N5.C0.D0.R0.S08: Preamble found at Latency = 007
N7.C2.D0.R0.S11: RxDqsDelay = 033
N1.C2.D0.R0.S13: RxDqsDelay = 033
N3.C2.D0.R1.S14: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N5.C0.D0.R0.S00: Total Receive Enable Delay = 1304
N7.C2.D0.R0.S12: RdDqDqs FSM results: Left = 09, Right = 63, center = 36
N1.C2.D0.R0.S14: RdDqDqs FSM results: Left = 09, Right = 63, center = 36
N3.C2.D0.R1.S15: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N5.C0.D0.R0.S01: Total Receive Enable Delay = 1285
N7.C2.D0.R0.S12: RxDqsDelay = 036
N1.C2.D0.R0.S14: RxDqsDelay = 036
N3.C2.D0.R1.S16: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N5.C0.D0.R0.S02: Total Receive Enable Delay = 1255
N7.C2.D0.R0.S13: RdDqDqs FSM results: Left = 02, Right = 63, center = 32
N1.C2.D0.R0.S15: RdDqDqs FSM results: Left = 08, Right = 63, center = 35
N3.C2.D0.R1.S17: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N5.C0.D0.R0.S03: Total Receive Enable Delay = 1236
N7.C2.D0.R0.S13: RxDqsDelay = 032
N1.C2.D0.R0.S15: RxDqsDelay = 035
N3.C2.D0.R1.S09: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N5.C0.D0.R0.S04: Total Receive Enable Delay = 1232
N7.C2.D0.R0.S14: RdDqDqs FSM results: Left = 06, Right = 63, center = 34
N1.C2.D0.R0.S16: RdDqDqs FSM results: Left = 05, Right = 63, center = 34
N3.C2.D0.R1.S10: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N5.C0.D0.R0.S05: Total Receive Enable Delay = 1254
N7.C2.D0.R0.S14: RxDqsDelay = 034
N1.C2.D0.R0.S16: RxDqsDelay = 034
N3.C2.D0.R1.S11: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N5.C0.D0.R0.S06: Total Receive Enable Delay = 1288
N7.C2.D0.R0.S15: RdDqDqs FSM results: Left = 02, Right = 56, center = 29
N1.C2.D0.R0.S17: RdDqDqs FSM results: Left = 08, Right = 63, center = 35
N3.C2.D0.R1.S12: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N5.C0.D0.R0.S07: Total Receive Enable Delay = 1310
N7.C2.D0.R0.S15: RxDqsDelay = 029
N1.C2.D0.R0.S17: RxDqsDelay = 035
N3.C2.D0.R1.S13: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N5.C0.D0.R0.S08: Total Receive Enable Delay = 1223
N7.C2.D0.R0.S16: RdDqDqs FSM results: Left = 02, Right = 56, center = 29
N1.C2.D0.R1.S00: RdDqDqs FSM results: Left = 04, Right = 60, center = 32
N3.C2.D0.R1.S14: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N5.C0.D0.R0: Starting preamble search upper nibbles
N7.C2.D0.R0.S16: RxDqsDelay = 029
N1.C2.D0.R1.S00: RxDqsDelay = 032
N3.C2.D0.R1.S15: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N5.C0.D0.R0.S09: PI = 056, PtrOffset = 005
N7.C2.D0.R0.S17: RdDqDqs FSM results: Left = 11, Right = 63, center = 37
N1.C2.D0.R1.S01: RdDqDqs FSM results: Left = 07, Right = 63, center = 35
N3.C2.D0.R1.S16: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N5.C0.D0.R0.S10: PI = 037, PtrOffset = 005
N7.C2.D0.R0.S17: RxDqsDelay = 037
N1.C2.D0.R1.S01: RxDqsDelay = 035
N3.C2.D0.R1.S17: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N5.C0.D0.R0.S11: PI = 008, PtrOffset = 005
N7.C2.D0.R1.S00: RdDqDqs FSM results: Left = 04, Right = 61, center = 32
N1.C2.D0.R1.S02: RdDqDqs FSM results: Left = 07, Right = 63, center = 35
N3.C2.D0.R1.S09: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N5.C0.D0.R0.S12: PI = 051, PtrOffset = 004
N7.C2.D0.R1.S00: RxDqsDelay = 032
N1.C2.D0.R1.S02: RxDqsDelay = 035
N3.C2.D0.R1.S10: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N5.C0.D0.R0.S13: PI = 047, PtrOffset = 004
N7.C2.D0.R1.S01: RdDqDqs FSM results: Left = 06, Right = 63, center = 34
N1.C2.D0.R1.S03: RdDqDqs FSM results: Left = 06, Right = 63, center = 34
N3.C2.D0.R1.S11: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N5.C0.D0.R0.S14: PI = 005, PtrOffset = 005
N7.C2.D0.R1.S01: RxDqsDelay = 034
N1.C2.D0.R1.S03: RxDqsDelay = 034
N3.C2.D0.R1.S12: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N5.C0.D0.R0.S15: PI = 039, PtrOffset = 005
N7.C2.D0.R1.S02: RdDqDqs FSM results: Left = 04, Right = 63, center = 33
N1.C2.D0.R1.S04: RdDqDqs FSM results: Left = 05, Right = 63, center = 34
N3.C2.D0.R1.S13: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N5.C0.D0.R0.S16: PI = 059, PtrOffset = 005
N7.C2.D0.R1.S02: RxDqsDelay = 033
N1.C2.D0.R1.S04: RxDqsDelay = 034
N3.C2.D0.R1.S14: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N5.C0.D0.R0.S17: PI = 040, PtrOffset = 004
N7.C2.D0.R1.S03: RdDqDqs FSM results: Left = 06, Right = 63, center = 34
N1.C2.D0.R1.S05: RdDqDqs FSM results: Left = 09, Right = 63, center = 36
N3.C2.D0.R1.S15: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N5.C0.D0.R0.S09: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N7.C2.D0.R1.S03: RxDqsDelay = 034
N1.C2.D0.R1.S05: RxDqsDelay = 036
N3.C2.D0.R1.S16: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N5.C0.D0.R0.S10: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N7.C2.D0.R1.S04: RdDqDqs FSM results: Left = 05, Right = 63, center = 34
N1.C2.D0.R1.S06: RdDqDqs FSM results: Left = 07, Right = 63, center = 35
N3.C2.D0.R1.S17: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N5.C0.D0.R0.S11: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N7.C2.D0.R1.S04: RxDqsDelay = 034
N1.C2.D0.R1.S06: RxDqsDelay = 035
N3.C2.D0.R1.S09: Preamble found at Latency = 007
N5.C0.D0.R0.S12: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N7.C2.D0.R1.S05: RdDqDqs FSM results: Left = 08, Right = 63, center = 35
N1.C2.D0.R1.S07: RdDqDqs FSM results: Left = 06, Right = 63, center = 34
N3.C2.D0.R1.S10: Preamble found at Latency = 007
N5.C0.D0.R0.S13: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N7.C2.D0.R1.S05: RxDqsDelay = 035
N1.C2.D0.R1.S07: RxDqsDelay = 034
N3.C2.D0.R1.S11: Preamble found at Latency = 007
N5.C0.D0.R0.S14: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N7.C2.D0.R1.S06: RdDqDqs FSM results: Left = 07, Right = 63, center = 35
N1.C2.D0.R1.S08: RdDqDqs FSM results: Left = 05, Right = 63, center = 34
N3.C2.D0.R1.S12: Preamble found at Latency = 007
N5.C0.D0.R0.S15: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N7.C2.D0.R1.S06: RxDqsDelay = 035
N1.C2.D0.R1.S08: RxDqsDelay = 034
N3.C2.D0.R1.S13: Preamble found at Latency = 007
N5.C0.D0.R0.S16: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N7.C2.D0.R1.S07: RdDqDqs FSM results: Left = 04, Right = 59, center = 31
N1.C2.D0.R1.S09: RdDqDqs FSM results: Left = 07, Right = 63, center = 35
N3.C2.D0.R1.S14: Preamble found at Latency = 007
N5.C0.D0.R0.S17: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N7.C2.D0.R1.S07: RxDqsDelay = 031
N1.C2.D0.R1.S09: RxDqsDelay = 035
N3.C2.D0.R1.S15: Preamble found at Latency = 007
N5.C0.D0.R0.S09: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N7.C2.D0.R1.S08: RdDqDqs FSM results: Left = 06, Right = 63, center = 34
N1.C2.D0.R1.S10: RdDqDqs FSM results: Left = 04, Right = 63, center = 33
N3.C2.D0.R1.S16: Preamble found at Latency = 007
N5.C0.D0.R0.S10: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N7.C2.D0.R1.S08: RxDqsDelay = 034
N1.C2.D0.R1.S10: RxDqsDelay = 033
N3.C2.D0.R1.S17: Preamble found at Latency = 007
N5.C0.D0.R0.S11: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N7.C2.D0.R1.S09: RdDqDqs FSM results: Left = 04, Right = 60, center = 32
N1.C2.D0.R1.S11: RdDqDqs FSM results: Left = 06, Right = 63, center = 34
N3.C2.D0.R1: Preamble found for all upper nibbles, adjusting Pi, Offset to center into preamble
N5.C0.D0.R0.S12: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N7.C2.D0.R1.S09: RxDqsDelay = 032
N1.C2.D0.R1.S11: RxDqsDelay = 034
N3.C2.D0.R1.S09: Total Receive Enable Delay = 1309
N5.C0.D0.R0.S13: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N7.C2.D0.R1.S10: RdDqDqs FSM results: Left = 07, Right = 63, center = 35
N1.C2.D0.R1.S12: RdDqDqs FSM results: Left = 07, Right = 63, center = 35
N3.C2.D0.R1.S10: Total Receive Enable Delay = 1283
N5.C0.D0.R0.S14: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N7.C2.D0.R1.S10: RxDqsDelay = 035
N1.C2.D0.R1.S12: RxDqsDelay = 035
N3.C2.D0.R1.S11: Total Receive Enable Delay = 1252
N5.C0.D0.R0.S15: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N7.C2.D0.R1.S11: RdDqDqs FSM results: Left = 03, Right = 61, center = 32
N1.C2.D0.R1.S13: RdDqDqs FSM results: Left = 03, Right = 63, center = 33
N3.C2.D0.R1.S12: Total Receive Enable Delay = 1234
N5.C0.D0.R0.S16: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N7.C2.D0.R1.S11: RxDqsDelay = 032
N1.C2.D0.R1.S13: RxDqsDelay = 033
N3.C2.D0.R1.S13: Total Receive Enable Delay = 1235
N5.C0.D0.R0.S17: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N7.C2.D0.R1.S12: RdDqDqs FSM results: Left = 10, Right = 63, center = 36
N1.C2.D0.R1.S14: RdDqDqs FSM results: Left = 09, Right = 63, center = 36
N3.C2.D0.R1.S14: Total Receive Enable Delay = 1248
N5.C0.D0.R0.S09: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N7.C2.D0.R1.S12: RxDqsDelay = 036
N1.C2.D0.R1.S14: RxDqsDelay = 036
N3.C2.D0.R1.S15: Total Receive Enable Delay = 1287
N5.C0.D0.R0.S10: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N7.C2.D0.R1.S13: RdDqDqs FSM results: Left = 02, Right = 63, center = 32
N1.C2.D0.R1.S15: RdDqDqs FSM results: Left = 07, Right = 63, center = 35
N3.C2.D0.R1.S16: Total Receive Enable Delay = 1302
N5.C0.D0.R0.S11: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N7.C2.D0.R1.S13: RxDqsDelay = 032
N1.C2.D0.R1.S15: RxDqsDelay = 035
N3.C2.D0.R1.S17: Total Receive Enable Delay = 1219
N5.C0.D0.R0.S12: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N7.C2.D0.R1.S14: RdDqDqs FSM results: Left = 07, Right = 63, center = 35
N1.C2.D0.R1.S16: RdDqDqs FSM results: Left = 05, Right = 59, center = 32
START_DATA_REC_EN
N5.C0.D0.R0.S13: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N7.C2.D0.R1.S14: RxDqsDelay = 035
N1.C2.D0.R1.S16: RxDqsDelay = 032
N3.C2.S00: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N5.C0.D0.R0.S14: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N7.C2.D0.R1.S15: RdDqDqs FSM results: Left = 02, Right = 57, center = 29
N1.C2.D0.R1.S17: RdDqDqs FSM results: Left = 08, Right = 63, center = 35
N3.C2.S01: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N5.C0.D0.R0.S15: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N7.C2.D0.R1.S15: RxDqsDelay = 029
N1.C2.D0.R1.S17: RxDqsDelay = 035
N3.C2.S02: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 5
N5.C0.D0.R0.S16: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N7.C2.D0.R1.S16: RdDqDqs FSM results: Left = 02, Right = 52, center = 27
START_DATA_RX_DQS
N3.C2.S03: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 5
N5.C0.D0.R0.S17: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N7.C2.D0.R1.S16: RxDqsDelay = 027
N1.C2.R0.S00: PI = 32
N3.C2.S04: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 5
N5.C0.D0.R0.S09: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N7.C2.D0.R1.S17: RdDqDqs FSM results: Left = 11, Right = 63, center = 37
N1.C2.R0.S01: PI = 35
N3.C2.S05: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 5
N5.C0.D0.R0.S10: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N7.C2.D0.R1.S17: RxDqsDelay = 037
N1.C2.R0.S02: PI = 35
N3.C2.S06: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N5.C0.D0.R0.S11: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
START_DATA_RX_DQS
N1.C2.R0.S03: PI = 34
N3.C2.S07: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N5.C0.D0.R0.S12: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N7.C2.R0.S00: PI = 32
N1.C2.R0.S04: PI = 33
N3.C2.S08: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 5
N5.C0.D0.R0.S13: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N7.C2.R0.S01: PI = 34
N1.C2.R0.S05: PI = 36
N3.C2.S09: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N5.C0.D0.R0.S14: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N7.C2.R0.S02: PI = 33
N1.C2.R0.S06: PI = 35
N3.C2.S10: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N5.C0.D0.R0.S15: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N7.C2.R0.S03: PI = 34
N1.C2.R0.S07: PI = 34
N3.C2.S11: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 5
N5.C0.D0.R0.S16: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N7.C2.R0.S04: PI = 34
N1.C2.R0.S08: PI = 34
N3.C2.S12: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 5
N5.C0.D0.R0.S17: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N7.C2.R0.S05: PI = 35
N1.C2.R0.S09: PI = 35
N3.C2.S13: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 5
N5.C0.D0.R0.S09: Preamble found at Latency = 007
N7.C2.R0.S06: PI = 35
N1.C2.R0.S10: PI = 33
N3.C2.S14: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 5
N5.C0.D0.R0.S10: Preamble found at Latency = 007
N7.C2.R0.S07: PI = 31
N1.C2.R0.S11: PI = 34
N3.C2.S15: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N5.C0.D0.R0.S11: Preamble found at Latency = 007
N7.C2.R0.S08: PI = 34
N1.C2.R0.S12: PI = 35
N3.C2.S16: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N5.C0.D0.R0.S12: Preamble found at Latency = 007
N7.C2.R0.S09: PI = 32
N1.C2.R0.S13: PI = 33
N3.C2.S17: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 5
N5.C0.D0.R0.S13: Preamble found at Latency = 007
N7.C2.R0.S10: PI = 35
N1.C2.R0.S14: PI = 36
N3.C2.D0.R0.S00: RcvEn: plus1 = 1, minus1 = 0, PI = 27, DB = 0
N5.C0.D0.R0.S14: Preamble found at Latency = 007
N7.C2.R0.S11: PI = 32
N1.C2.R0.S15: PI = 35
N3.C2.D0.R0.S01: RcvEn: plus1 = 1, minus1 = 0, PI = 03, DB = 1
N5.C0.D0.R0.S15: Preamble found at Latency = 007
N7.C2.R0.S12: PI = 36
N1.C2.R0.S16: PI = 33
N3.C2.D0.R0.S02: RcvEn: plus1 = 1, minus1 = 0, PI = 35, DB = 0
N5.C0.D0.R0.S16: Preamble found at Latency = 007
N7.C2.R0.S13: PI = 32
N1.C2.R0.S17: PI = 35
N3.C2.D0.R0.S03: RcvEn: plus1 = 1, minus1 = 0, PI = 19, DB = 0
N5.C0.D0.R0.S17: Preamble found at Latency = 007
N7.C2.R0.S14: PI = 34
N1.C2.R0.S00: PI = 32
N3.C2.D0.R0.S04: RcvEn: plus1 = 1, minus1 = 0, PI = 19, DB = 0
N5.C0.D0.R0: Preamble found for all upper nibbles, adjusting Pi, Offset to center into preamble
N7.C2.R0.S15: PI = 29
N1.C2.R0.S01: PI = 35
N3.C2.D0.R0.S05: RcvEn: plus1 = 1, minus1 = 0, PI = 30, DB = 0
N5.C0.D0.R0.S09: Total Receive Enable Delay = 1304
N7.C2.R0.S16: PI = 28
N1.C2.R0.S02: PI = 35
N3.C2.D0.R0.S06: RcvEn: plus1 = 1, minus1 = 0, PI = 05, DB = 1
N5.C0.D0.R0.S10: Total Receive Enable Delay = 1285
N7.C2.R0.S17: PI = 37
N1.C2.R0.S03: PI = 34
N3.C2.D0.R0.S07: RcvEn: plus1 = 1, minus1 = 0, PI = 23, DB = 0
N5.C0.D0.R0.S11: Total Receive Enable Delay = 1256
N7.C2.R0.S00: PI = 32
N1.C2.R0.S04: PI = 33
N3.C2.D0.R0.S08: RcvEn: plus1 = 1, minus1 = 0, PI = 05, DB = 1
N5.C0.D0.R0.S12: Total Receive Enable Delay = 1235
N7.C2.R0.S01: PI = 34
N1.C2.R0.S05: PI = 36
N3.C2.D0.R0.S09: RcvEn: plus1 = 1, minus1 = 0, PI = 28, DB = 0
N5.C0.D0.R0.S13: Total Receive Enable Delay = 1231
N7.C2.R0.S02: PI = 33
N1.C2.R0.S06: PI = 35
N3.C2.D0.R0.S10: RcvEn: plus1 = 1, minus1 = 0, PI = 03, DB = 1
N5.C0.D0.R0.S14: Total Receive Enable Delay = 1253
N7.C2.R0.S03: PI = 34
N1.C2.R0.S07: PI = 34
N3.C2.D0.R0.S11: RcvEn: plus1 = 1, minus1 = 0, PI = 36, DB = 0
N5.C0.D0.R0.S15: Total Receive Enable Delay = 1287
N7.C2.R0.S04: PI = 34
N1.C2.R0.S08: PI = 34
N3.C2.D0.R0.S12: RcvEn: plus1 = 1, minus1 = 0, PI = 17, DB = 0
N5.C0.D0.R0.S16: Total Receive Enable Delay = 1307
N7.C2.R0.S05: PI = 35
N1.C2.R0.S09: PI = 35
N3.C2.D0.R0.S13: RcvEn: plus1 = 1, minus1 = 0, PI = 19, DB = 0
N5.C0.D0.R0.S17: Total Receive Enable Delay = 1224
N7.C2.R0.S06: PI = 35
N1.C2.R0.S10: PI = 33
N3.C2.D0.R0.S14: RcvEn: plus1 = 1, minus1 = 0, PI = 31, DB = 0
N5.C0.D0.R1: RcvEnFine: Initial RdCmd2RcvEnLatency = 10, Initial RdPtrOffsetRcvEn = 4
N7.C2.R0.S07: PI = 31
N1.C2.R0.S11: PI = 34
N3.C2.D0.R0.S15: RcvEn: plus1 = 1, minus1 = 0, PI = 06, DB = 1
N5.C0.D0.R1.S00: Rcv En Fine Value = 378
N7.C2.R0.S08: PI = 34
N1.C2.R0.S12: PI = 35
N3.C2.D0.R0.S16: RcvEn: plus1 = 1, minus1 = 0, PI = 23, DB = 0
N5.C0.D0.R1.S01: Rcv En Fine Value = 359
N7.C2.R0.S09: PI = 32
N1.C2.R0.S13: PI = 33
N3.C2.D0.R0.S17: RcvEn: plus1 = 1, minus1 = 0, PI = 03, DB = 1
N5.C0.D0.R1.S02: Rcv En Fine Value = 327
N7.C2.R0.S10: PI = 35
N1.C2.R0.S14: PI = 36
N3.C2.D0.R1.S00: RcvEn: plus1 = 1, minus1 = 0, PI = 27, DB = 0
N5.C0.D0.R1.S03: Rcv En Fine Value = 309
N7.C2.R0.S11: PI = 32
N1.C2.R0.S15: PI = 35
N3.C2.D0.R1.S01: RcvEn: plus1 = 1, minus1 = 0, PI = 03, DB = 1
N5.C0.D0.R1.S04: Rcv En Fine Value = 305
N7.C2.R0.S12: PI = 36
N1.C2.R0.S16: PI = 33
N3.C2.D0.R1.S02: RcvEn: plus1 = 1, minus1 = 0, PI = 35, DB = 0
N5.C0.D0.R1.S05: Rcv En Fine Value = 324
N7.C2.R0.S13: PI = 32
N1.C2.R0.S17: PI = 35
N3.C2.D0.R1.S03: RcvEn: plus1 = 1, minus1 = 0, PI = 19, DB = 0
N5.C0.D0.R1.S06: Rcv En Fine Value = 359
N7.C2.R0.S14: PI = 34
STOP_DATA_RX_DQS
N3.C2.D0.R1.S04: RcvEn: plus1 = 1, minus1 = 0, PI = 19, DB = 0
N5.C0.D0.R1.S07: Rcv En Fine Value = 379
N7.C2.R0.S15: PI = 29
N1.C3.D0.R0.S00: RdDqDqs FSM results: Left = 08, Right = 63, center = 35
N3.C2.D0.R1.S05: RcvEn: plus1 = 1, minus1 = 0, PI = 30, DB = 0
N5.C0.D0.R1.S08: Rcv En Fine Value = 296
N7.C2.R0.S16: PI = 28
N1.C3.D0.R0.S00: RxDqsDelay = 035
N3.C2.D0.R1.S06: RcvEn: plus1 = 1, minus1 = 0, PI = 05, DB = 1
N5.C0.D0.R1.S09: Rcv En Fine Value = 375
N7.C2.R0.S17: PI = 37
N1.C3.D0.R0.S01: RdDqDqs FSM results: Left = 05, Right = 60, center = 32
N3.C2.D0.R1.S07: RcvEn: plus1 = 1, minus1 = 0, PI = 23, DB = 0
N5.C0.D0.R1.S10: Rcv En Fine Value = 356
STOP_DATA_RX_DQS
N1.C3.D0.R0.S01: RxDqsDelay = 032
N3.C2.D0.R1.S08: RcvEn: plus1 = 1, minus1 = 0, PI = 05, DB = 1
N5.C0.D0.R1.S11: Rcv En Fine Value = 329
N7.C3.D0.R0.S00: RdDqDqs FSM results: Left = 04, Right = 59, center = 31
N1.C3.D0.R0.S02: RdDqDqs FSM results: Left = 04, Right = 63, center = 33
N3.C2.D0.R1.S09: RcvEn: plus1 = 1, minus1 = 0, PI = 28, DB = 0
N5.C0.D0.R1.S12: Rcv En Fine Value = 308
N7.C3.D0.R0.S00: RxDqsDelay = 031
N1.C3.D0.R0.S02: RxDqsDelay = 033
N3.C2.D0.R1.S10: RcvEn: plus1 = 1, minus1 = 0, PI = 03, DB = 1
N5.C0.D0.R1.S13: Rcv En Fine Value = 304
N7.C3.D0.R0.S01: RdDqDqs FSM results: Left = 04, Right = 59, center = 31
N1.C3.D0.R0.S03: RdDqDqs FSM results: Left = 07, Right = 63, center = 35
N3.C2.D0.R1.S11: RcvEn: plus1 = 1, minus1 = 0, PI = 36, DB = 0
N5.C0.D0.R1.S14: Rcv En Fine Value = 326
N7.C3.D0.R0.S01: RxDqsDelay = 031
N1.C3.D0.R0.S03: RxDqsDelay = 035
N3.C2.D0.R1.S12: RcvEn: plus1 = 1, minus1 = 0, PI = 17, DB = 0
N5.C0.D0.R1.S15: Rcv En Fine Value = 359
N7.C3.D0.R0.S02: RdDqDqs FSM results: Left = 07, Right = 63, center = 35
N1.C3.D0.R0.S04: RdDqDqs FSM results: Left = 05, Right = 63, center = 34
N3.C2.D0.R1.S13: RcvEn: plus1 = 1, minus1 = 0, PI = 19, DB = 0
N5.C0.D0.R1.S16: Rcv En Fine Value = 380
N7.C3.D0.R0.S02: RxDqsDelay = 035
N1.C3.D0.R0.S04: RxDqsDelay = 034
N3.C2.D0.R1.S14: RcvEn: plus1 = 1, minus1 = 0, PI = 31, DB = 0
N5.C0.D0.R1.S17: Rcv En Fine Value = 296
N7.C3.D0.R0.S03: RdDqDqs FSM results: Left = 05, Right = 63, center = 34
N1.C3.D0.R0.S05: RdDqDqs FSM results: Left = 07, Right = 63, center = 35
N3.C2.D0.R1.S15: RcvEn: plus1 = 1, minus1 = 0, PI = 06, DB = 1
N5.C0.D0.R1: Starting preamble search lower nibbles
N7.C3.D0.R0.S03: RxDqsDelay = 034
N1.C3.D0.R0.S05: RxDqsDelay = 035
N3.C2.D0.R1.S16: RcvEn: plus1 = 1, minus1 = 0, PI = 23, DB = 0
N5.C0.D0.R1.S00: PI = 058, PtrOffset = 005
N7.C3.D0.R0.S04: RdDqDqs FSM results: Left = 09, Right = 63, center = 36
N1.C3.D0.R0.S06: RdDqDqs FSM results: Left = 08, Right = 63, center = 35
N3.C2.D0.R1.S17: RcvEn: plus1 = 1, minus1 = 0, PI = 03, DB = 1
N5.C0.D0.R1.S01: PI = 039, PtrOffset = 005
N7.C3.D0.R0.S04: RxDqsDelay = 036
N1.C3.D0.R0.S06: RxDqsDelay = 035
STOP_DATA_REC_EN
N5.C0.D0.R1.S02: PI = 007, PtrOffset = 005
N7.C3.D0.R0.S05: RdDqDqs FSM results: Left = 05, Right = 63, center = 34
N1.C3.D0.R0.S07: RdDqDqs FSM results: Left = 05, Right = 60, center = 32
N3.C3.D0.R0: RcvEnFine: Initial RdCmd2RcvEnLatency = 10, Initial RdPtrOffsetRcvEn = 4
N5.C0.D0.R1.S03: PI = 053, PtrOffset = 004
N7.C3.D0.R0.S05: RxDqsDelay = 034
N1.C3.D0.R0.S07: RxDqsDelay = 032
N3.C3.D0.R0.S00: Rcv En Fine Value = 297
N5.C0.D0.R1.S04: PI = 049, PtrOffset = 004
N7.C3.D0.R0.S06: RdDqDqs FSM results: Left = 07, Right = 63, center = 35
N1.C3.D0.R0.S08: RdDqDqs FSM results: Left = 06, Right = 63, center = 34
N3.C3.D0.R0.S01: Rcv En Fine Value = 275
N5.C0.D0.R1.S05: PI = 004, PtrOffset = 005
N7.C3.D0.R0.S06: RxDqsDelay = 035
N1.C3.D0.R0.S08: RxDqsDelay = 034
N3.C3.D0.R0.S02: Rcv En Fine Value = 378
N5.C0.D0.R1.S06: PI = 039, PtrOffset = 005
N7.C3.D0.R0.S07: RdDqDqs FSM results: Left = 05, Right = 60, center = 32
N1.C3.D0.R0.S09: RdDqDqs FSM results: Left = 08, Right = 63, center = 35
N3.C3.D0.R0.S03: Rcv En Fine Value = 354
N5.C0.D0.R1.S07: PI = 059, PtrOffset = 005
N7.C3.D0.R0.S07: RxDqsDelay = 032
N1.C3.D0.R0.S09: RxDqsDelay = 035
N3.C3.D0.R0.S04: Rcv En Fine Value = 349
N5.C0.D0.R1.S08: PI = 040, PtrOffset = 004
N7.C3.D0.R0.S08: RdDqDqs FSM results: Left = 04, Right = 63, center = 33
N1.C3.D0.R0.S10: RdDqDqs FSM results: Left = 06, Right = 63, center = 34
N3.C3.D0.R0.S05: Rcv En Fine Value = 374
N5.C0.D0.R1.S00: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N7.C3.D0.R0.S08: RxDqsDelay = 033
N1.C3.D0.R0.S10: RxDqsDelay = 034
N3.C3.D0.R0.S06: Rcv En Fine Value = 268
N5.C0.D0.R1.S01: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N7.C3.D0.R0.S09: RdDqDqs FSM results: Left = 07, Right = 63, center = 35
N1.C3.D0.R0.S11: RdDqDqs FSM results: Left = 04, Right = 63, center = 33
N3.C3.D0.R0.S07: Rcv En Fine Value = 293
N5.C0.D0.R1.S02: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N7.C3.D0.R0.S09: RxDqsDelay = 035
N1.C3.D0.R0.S11: RxDqsDelay = 033
N3.C3.D0.R0.S08: Rcv En Fine Value = 334
N5.C0.D0.R1.S03: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N7.C3.D0.R0.S10: RdDqDqs FSM results: Left = 05, Right = 63, center = 34
N1.C3.D0.R0.S12: RdDqDqs FSM results: Left = 03, Right = 63, center = 33
N3.C3.D0.R0.S09: Rcv En Fine Value = 300
N5.C0.D0.R1.S04: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N7.C3.D0.R0.S10: RxDqsDelay = 034
N1.C3.D0.R0.S12: RxDqsDelay = 033
N3.C3.D0.R0.S10: Rcv En Fine Value = 278
N5.C0.D0.R1.S05: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N7.C3.D0.R0.S11: RdDqDqs FSM results: Left = 03, Right = 63, center = 33
N1.C3.D0.R0.S13: RdDqDqs FSM results: Left = 09, Right = 63, center = 36
N3.C3.D0.R0.S11: Rcv En Fine Value = 375
N5.C0.D0.R1.S06: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N7.C3.D0.R0.S11: RxDqsDelay = 033
N1.C3.D0.R0.S13: RxDqsDelay = 036
N3.C3.D0.R0.S12: Rcv En Fine Value = 354
N5.C0.D0.R1.S07: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N7.C3.D0.R0.S12: RdDqDqs FSM results: Left = 03, Right = 63, center = 33
N1.C3.D0.R0.S14: RdDqDqs FSM results: Left = 07, Right = 63, center = 35
N3.C3.D0.R0.S13: Rcv En Fine Value = 350
N5.C0.D0.R1.S08: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N7.C3.D0.R0.S12: RxDqsDelay = 033
N1.C3.D0.R0.S14: RxDqsDelay = 035
N3.C3.D0.R0.S14: Rcv En Fine Value = 374
N5.C0.D0.R1.S00: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N7.C3.D0.R0.S13: RdDqDqs FSM results: Left = 08, Right = 63, center = 35
N1.C3.D0.R0.S15: RdDqDqs FSM results: Left = 07, Right = 63, center = 35
N3.C3.D0.R0.S15: Rcv En Fine Value = 268
N5.C0.D0.R1.S01: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N7.C3.D0.R0.S13: RxDqsDelay = 035
N1.C3.D0.R0.S15: RxDqsDelay = 035
N3.C3.D0.R0.S16: Rcv En Fine Value = 293
N5.C0.D0.R1.S02: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N7.C3.D0.R0.S14: RdDqDqs FSM results: Left = 05, Right = 63, center = 34
N1.C3.D0.R0.S16: RdDqDqs FSM results: Left = 05, Right = 60, center = 32
N3.C3.D0.R0.S17: Rcv En Fine Value = 335
N5.C0.D0.R1.S03: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N7.C3.D0.R0.S14: RxDqsDelay = 034
N1.C3.D0.R0.S16: RxDqsDelay = 032
N3.C3.D0.R0: Starting preamble search lower nibbles
N5.C0.D0.R1.S04: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N7.C3.D0.R0.S15: RdDqDqs FSM results: Left = 06, Right = 63, center = 34
N1.C3.D0.R0.S17: RdDqDqs FSM results: Left = 05, Right = 63, center = 34
N3.C3.D0.R0.S00: PI = 041, PtrOffset = 004
N5.C0.D0.R1.S05: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N7.C3.D0.R0.S15: RxDqsDelay = 034
N1.C3.D0.R0.S17: RxDqsDelay = 034
N3.C3.D0.R0.S01: PI = 019, PtrOffset = 004
N5.C0.D0.R1.S06: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N7.C3.D0.R0.S16: RdDqDqs FSM results: Left = 02, Right = 58, center = 30
N1.C3.D0.R1.S00: RdDqDqs FSM results: Left = 09, Right = 63, center = 36
N3.C3.D0.R0.S02: PI = 058, PtrOffset = 005
N5.C0.D0.R1.S07: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N7.C3.D0.R0.S16: RxDqsDelay = 030
N1.C3.D0.R1.S00: RxDqsDelay = 036
N3.C3.D0.R0.S03: PI = 034, PtrOffset = 005
N5.C0.D0.R1.S08: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N7.C3.D0.R0.S17: RdDqDqs FSM results: Left = 05, Right = 63, center = 34
N1.C3.D0.R1.S01: RdDqDqs FSM results: Left = 06, Right = 63, center = 34
N3.C3.D0.R0.S04: PI = 029, PtrOffset = 005
N5.C0.D0.R1.S00: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N7.C3.D0.R0.S17: RxDqsDelay = 034
N1.C3.D0.R1.S01: RxDqsDelay = 034
N3.C3.D0.R0.S05: PI = 054, PtrOffset = 005
N5.C0.D0.R1.S01: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N7.C3.D0.R1.S00: RdDqDqs FSM results: Left = 04, Right = 60, center = 32
N1.C3.D0.R1.S02: RdDqDqs FSM results: Left = 04, Right = 63, center = 33
N3.C3.D0.R0.S06: PI = 012, PtrOffset = 004
N5.C0.D0.R1.S02: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N7.C3.D0.R1.S00: RxDqsDelay = 032
N1.C3.D0.R1.S02: RxDqsDelay = 033
N3.C3.D0.R0.S07: PI = 037, PtrOffset = 004
N5.C0.D0.R1.S03: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N7.C3.D0.R1.S01: RdDqDqs FSM results: Left = 05, Right = 59, center = 32
N1.C3.D0.R1.S03: RdDqDqs FSM results: Left = 09, Right = 63, center = 36
N3.C3.D0.R0.S08: PI = 014, PtrOffset = 005
N5.C0.D0.R1.S04: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N7.C3.D0.R1.S01: RxDqsDelay = 032
N1.C3.D0.R1.S03: RxDqsDelay = 036
N3.C3.D0.R0.S00: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N5.C0.D0.R1.S05: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N7.C3.D0.R1.S02: RdDqDqs FSM results: Left = 08, Right = 63, center = 35
N1.C3.D0.R1.S04: RdDqDqs FSM results: Left = 06, Right = 59, center = 32
N3.C3.D0.R0.S01: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N5.C0.D0.R1.S06: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N7.C3.D0.R1.S02: RxDqsDelay = 035
N1.C3.D0.R1.S04: RxDqsDelay = 032
N3.C3.D0.R0.S02: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N5.C0.D0.R1.S07: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N7.C3.D0.R1.S03: RdDqDqs FSM results: Left = 05, Right = 63, center = 34
N1.C3.D0.R1.S05: RdDqDqs FSM results: Left = 07, Right = 63, center = 35
N3.C3.D0.R0.S03: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N5.C0.D0.R1.S08: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N7.C3.D0.R1.S03: RxDqsDelay = 034
N1.C3.D0.R1.S05: RxDqsDelay = 035
N3.C3.D0.R0.S04: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N5.C0.D0.R1.S00: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N7.C3.D0.R1.S04: RdDqDqs FSM results: Left = 10, Right = 63, center = 36
N1.C3.D0.R1.S06: RdDqDqs FSM results: Left = 06, Right = 63, center = 34
N3.C3.D0.R0.S05: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N5.C0.D0.R1.S01: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N7.C3.D0.R1.S04: RxDqsDelay = 036
N1.C3.D0.R1.S06: RxDqsDelay = 034
N3.C3.D0.R0.S06: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N5.C0.D0.R1.S02: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N7.C3.D0.R1.S05: RdDqDqs FSM results: Left = 05, Right = 63, center = 34
N1.C3.D0.R1.S07: RdDqDqs FSM results: Left = 05, Right = 58, center = 31
N3.C3.D0.R0.S07: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N5.C0.D0.R1.S03: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N7.C3.D0.R1.S05: RxDqsDelay = 034
N1.C3.D0.R1.S07: RxDqsDelay = 031
N3.C3.D0.R0.S08: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N5.C0.D0.R1.S04: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N7.C3.D0.R1.S06: RdDqDqs FSM results: Left = 07, Right = 63, center = 35
N1.C3.D0.R1.S08: RdDqDqs FSM results: Left = 05, Right = 63, center = 34
N3.C3.D0.R0.S00: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N5.C0.D0.R1.S05: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N7.C3.D0.R1.S06: RxDqsDelay = 035
N1.C3.D0.R1.S08: RxDqsDelay = 034
N3.C3.D0.R0.S01: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N5.C0.D0.R1.S06: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N7.C3.D0.R1.S07: RdDqDqs FSM results: Left = 04, Right = 58, center = 31
N1.C3.D0.R1.S09: RdDqDqs FSM results: Left = 08, Right = 63, center = 35
N3.C3.D0.R0.S02: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N5.C0.D0.R1.S07: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N7.C3.D0.R1.S07: RxDqsDelay = 031
N1.C3.D0.R1.S09: RxDqsDelay = 035
N3.C3.D0.R0.S03: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N5.C0.D0.R1.S08: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N7.C3.D0.R1.S08: RdDqDqs FSM results: Left = 03, Right = 63, center = 33
N1.C3.D0.R1.S10: RdDqDqs FSM results: Left = 06, Right = 63, center = 34
N3.C3.D0.R0.S04: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N5.C0.D0.R1.S00: Preamble found at Latency = 007
N7.C3.D0.R1.S08: RxDqsDelay = 033
N1.C3.D0.R1.S10: RxDqsDelay = 034
N3.C3.D0.R0.S05: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N5.C0.D0.R1.S01: Preamble found at Latency = 007
N7.C3.D0.R1.S09: RdDqDqs FSM results: Left = 07, Right = 63, center = 35
N1.C3.D0.R1.S11: RdDqDqs FSM results: Left = 03, Right = 63, center = 33
N3.C3.D0.R0.S06: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N5.C0.D0.R1.S02: Preamble found at Latency = 007
N7.C3.D0.R1.S09: RxDqsDelay = 035
N1.C3.D0.R1.S11: RxDqsDelay = 033
N3.C3.D0.R0.S07: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N5.C0.D0.R1.S03: Preamble found at Latency = 007
N7.C3.D0.R1.S10: RdDqDqs FSM results: Left = 05, Right = 63, center = 34
N1.C3.D0.R1.S12: RdDqDqs FSM results: Left = 04, Right = 63, center = 33
N3.C3.D0.R0.S08: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N5.C0.D0.R1.S04: Preamble found at Latency = 007
N7.C3.D0.R1.S10: RxDqsDelay = 034
N1.C3.D0.R1.S12: RxDqsDelay = 033
N3.C3.D0.R0.S00: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N5.C0.D0.R1.S05: Preamble found at Latency = 007
N7.C3.D0.R1.S11: RdDqDqs FSM results: Left = 03, Right = 63, center = 33
N1.C3.D0.R1.S13: RdDqDqs FSM results: Left = 09, Right = 63, center = 36
N3.C3.D0.R0.S01: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N5.C0.D0.R1.S06: Preamble found at Latency = 007
N7.C3.D0.R1.S11: RxDqsDelay = 033
N1.C3.D0.R1.S13: RxDqsDelay = 036
N3.C3.D0.R0.S02: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N5.C0.D0.R1.S07: Preamble found at Latency = 007
N7.C3.D0.R1.S12: RdDqDqs FSM results: Left = 03, Right = 63, center = 33
N1.C3.D0.R1.S14: RdDqDqs FSM results: Left = 07, Right = 63, center = 35
N3.C3.D0.R0.S03: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N5.C0.D0.R1.S08: Preamble found at Latency = 007
N7.C3.D0.R1.S12: RxDqsDelay = 033
N1.C3.D0.R1.S14: RxDqsDelay = 035
N3.C3.D0.R0.S04: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N5.C0.D0.R1.S00: Total Receive Enable Delay = 1306
N7.C3.D0.R1.S13: RdDqDqs FSM results: Left = 08, Right = 63, center = 35
N1.C3.D0.R1.S15: RdDqDqs FSM results: Left = 06, Right = 63, center = 34
N3.C3.D0.R0.S05: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N5.C0.D0.R1.S01: Total Receive Enable Delay = 1287
N7.C3.D0.R1.S13: RxDqsDelay = 035
N1.C3.D0.R1.S15: RxDqsDelay = 034
N3.C3.D0.R0.S06: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N5.C0.D0.R1.S02: Total Receive Enable Delay = 1255
N7.C3.D0.R1.S14: RdDqDqs FSM results: Left = 05, Right = 63, center = 34
N1.C3.D0.R1.S16: RdDqDqs FSM results: Left = 05, Right = 58, center = 31
N3.C3.D0.R0.S07: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N5.C0.D0.R1.S03: Total Receive Enable Delay = 1237
N7.C3.D0.R1.S14: RxDqsDelay = 034
N1.C3.D0.R1.S16: RxDqsDelay = 031
N3.C3.D0.R0.S08: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N5.C0.D0.R1.S04: Total Receive Enable Delay = 1233
N7.C3.D0.R1.S15: RdDqDqs FSM results: Left = 06, Right = 63, center = 34
N1.C3.D0.R1.S17: RdDqDqs FSM results: Left = 06, Right = 63, center = 34
N3.C3.D0.R0.S00: Preamble found at Latency = 008
N5.C0.D0.R1.S05: Total Receive Enable Delay = 1252
N7.C3.D0.R1.S15: RxDqsDelay = 034
N1.C3.D0.R1.S17: RxDqsDelay = 034
N3.C3.D0.R0.S01: Preamble found at Latency = 008
N5.C0.D0.R1.S06: Total Receive Enable Delay = 1287
N7.C3.D0.R1.S16: RdDqDqs FSM results: Left = 02, Right = 57, center = 29
START_DATA_RX_DQS
N3.C3.D0.R0.S06: Preamble found at Latency = 008
N5.C0.D0.R1.S07: Total Receive Enable Delay = 1307
N7.C3.D0.R1.S16: RxDqsDelay = 029
N1.C3.R0.S00: PI = 35
N3.C3.D0.R0.S07: Preamble found at Latency = 008
N5.C0.D0.R1.S08: Total Receive Enable Delay = 1224
N7.C3.D0.R1.S17: RdDqDqs FSM results: Left = 05, Right = 63, center = 34
N1.C3.R0.S01: PI = 33
N3.C3.D0.R0.S00: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N5.C0.D0.R1: Starting preamble search upper nibbles
N7.C3.D0.R1.S17: RxDqsDelay = 034
N1.C3.R0.S02: PI = 33
N3.C3.D0.R0.S01: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N5.C0.D0.R1.S09: PI = 055, PtrOffset = 005
START_DATA_RX_DQS
N1.C3.R0.S03: PI = 35
N3.C3.D0.R0.S02: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N5.C0.D0.R1.S10: PI = 036, PtrOffset = 005
N7.C3.R0.S00: PI = 31
N1.C3.R0.S04: PI = 33
N3.C3.D0.R0.S03: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N5.C0.D0.R1.S11: PI = 009, PtrOffset = 005
N7.C3.R0.S01: PI = 31
N1.C3.R0.S05: PI = 35
N3.C3.D0.R0.S04: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N5.C0.D0.R1.S12: PI = 052, PtrOffset = 004
N7.C3.R0.S02: PI = 35
N1.C3.R0.S06: PI = 34
N3.C3.D0.R0.S05: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N5.C0.D0.R1.S13: PI = 048, PtrOffset = 004
N7.C3.R0.S03: PI = 34
N1.C3.R0.S07: PI = 31
N3.C3.D0.R0.S06: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N5.C0.D0.R1.S14: PI = 006, PtrOffset = 005
N7.C3.R0.S04: PI = 36
N1.C3.R0.S08: PI = 34
N3.C3.D0.R0.S07: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N5.C0.D0.R1.S15: PI = 039, PtrOffset = 005
N7.C3.R0.S05: PI = 34
N1.C3.R0.S09: PI = 35
N3.C3.D0.R0.S08: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N5.C0.D0.R1.S16: PI = 060, PtrOffset = 005
N7.C3.R0.S06: PI = 35
N1.C3.R0.S10: PI = 34
N3.C3.D0.R0.S02: Preamble found at Latency = 007
N5.C0.D0.R1.S17: PI = 040, PtrOffset = 004
N7.C3.R0.S07: PI = 31
N1.C3.R0.S11: PI = 33
N3.C3.D0.R0.S03: Preamble found at Latency = 007
N5.C0.D0.R1.S09: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N7.C3.R0.S08: PI = 33
N1.C3.R0.S12: PI = 33
N3.C3.D0.R0.S04: Preamble found at Latency = 007
N5.C0.D0.R1.S10: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N7.C3.R0.S09: PI = 35
N1.C3.R0.S13: PI = 36
N3.C3.D0.R0.S05: Preamble found at Latency = 007
N5.C0.D0.R1.S11: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N7.C3.R0.S10: PI = 34
N1.C3.R0.S14: PI = 35
N3.C3.D0.R0.S08: Preamble found at Latency = 007
N5.C0.D0.R1.S12: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N7.C3.R0.S11: PI = 33
N1.C3.R0.S15: PI = 34
N3.C3.D0.R0.S00: Total Receive Enable Delay = 1353
N5.C0.D0.R1.S13: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N7.C3.R0.S12: PI = 33
N1.C3.R0.S16: PI = 31
N3.C3.D0.R0.S01: Total Receive Enable Delay = 1331
N5.C0.D0.R1.S14: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N7.C3.R0.S13: PI = 35
N1.C3.R0.S17: PI = 34
N3.C3.D0.R0.S02: Total Receive Enable Delay = 1306
N5.C0.D0.R1.S15: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N7.C3.R0.S14: PI = 34
N1.C3.R0.S00: PI = 35
N3.C3.D0.R0.S03: Total Receive Enable Delay = 1282
N5.C0.D0.R1.S16: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N7.C3.R0.S15: PI = 34
N1.C3.R0.S01: PI = 33
N3.C3.D0.R0.S04: Total Receive Enable Delay = 1277
N5.C0.D0.R1.S17: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N7.C3.R0.S16: PI = 29
N1.C3.R0.S02: PI = 33
N3.C3.D0.R0.S05: Total Receive Enable Delay = 1302
N5.C0.D0.R1.S09: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N7.C3.R0.S17: PI = 34
N1.C3.R0.S03: PI = 35
N3.C3.D0.R0.S06: Total Receive Enable Delay = 1324
N5.C0.D0.R1.S10: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N7.C3.R0.S00: PI = 31
N1.C3.R0.S04: PI = 33
N3.C3.D0.R0.S07: Total Receive Enable Delay = 1349
N5.C0.D0.R1.S11: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N7.C3.R0.S01: PI = 31
N1.C3.R0.S05: PI = 35
N3.C3.D0.R0.S08: Total Receive Enable Delay = 1262
N5.C0.D0.R1.S12: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N7.C3.R0.S02: PI = 35
N1.C3.R0.S06: PI = 34
N3.C3.D0.R0: Starting preamble search upper nibbles
N5.C0.D0.R1.S13: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N7.C3.R0.S03: PI = 34
N1.C3.R0.S07: PI = 31
N3.C3.D0.R0.S09: PI = 044, PtrOffset = 004
N5.C0.D0.R1.S14: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N7.C3.R0.S04: PI = 36
N1.C3.R0.S08: PI = 34
N3.C3.D0.R0.S10: PI = 022, PtrOffset = 004
N5.C0.D0.R1.S15: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N7.C3.R0.S05: PI = 34
N1.C3.R0.S09: PI = 35
N3.C3.D0.R0.S11: PI = 055, PtrOffset = 005
N5.C0.D0.R1.S16: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N7.C3.R0.S06: PI = 35
N1.C3.R0.S10: PI = 34
N3.C3.D0.R0.S12: PI = 034, PtrOffset = 005
N5.C0.D0.R1.S17: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N7.C3.R0.S07: PI = 31
N1.C3.R0.S11: PI = 33
N3.C3.D0.R0.S13: PI = 030, PtrOffset = 005
N5.C0.D0.R1.S09: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N7.C3.R0.S08: PI = 33
N1.C3.R0.S12: PI = 33
N3.C3.D0.R0.S14: PI = 054, PtrOffset = 005
N5.C0.D0.R1.S10: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N7.C3.R0.S09: PI = 35
N1.C3.R0.S13: PI = 36
N3.C3.D0.R0.S15: PI = 012, PtrOffset = 004
N5.C0.D0.R1.S11: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N7.C3.R0.S10: PI = 34
N1.C3.R0.S14: PI = 35
N3.C3.D0.R0.S16: PI = 037, PtrOffset = 004
N5.C0.D0.R1.S12: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N7.C3.R0.S11: PI = 33
N1.C3.R0.S15: PI = 34
N3.C3.D0.R0.S17: PI = 015, PtrOffset = 005
N5.C0.D0.R1.S13: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N7.C3.R0.S12: PI = 33
N1.C3.R0.S16: PI = 31
N3.C3.D0.R0.S09: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N5.C0.D0.R1.S14: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N7.C3.R0.S13: PI = 35
N1.C3.R0.S17: PI = 34
N3.C3.D0.R0.S10: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N5.C0.D0.R1.S15: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N7.C3.R0.S14: PI = 34
STOP_DATA_RX_DQS
N3.C3.D0.R0.S11: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N5.C0.D0.R1.S16: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N7.C3.R0.S15: PI = 34
N1: RunTrainStep: Final status = 0
N3.C3.D0.R0.S12: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N5.C0.D0.R1.S17: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N7.C3.R0.S16: PI = 29

END - Basic Read DQ/DQS Training       Time         9187 ms
N3.C3.D0.R0.S13: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N5.C0.D0.R1.S09: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N7.C3.R0.S17: PI = 34

START - Basic Receive Enable Training
N3.C3.D0.R0.S14: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N5.C0.D0.R1.S10: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
STOP_DATA_RX_DQS
Checkpoint Code: Socket 0, 0xB7, 0x02, 0x0000
N3.C3.D0.R0.S15: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N5.C0.D0.R1.S11: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N7: RunTrainStep: Final status = 0
N1.C0: QCRM debug: extraRcvEnLatency = 0
N3.C3.D0.R0.S16: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N5.C0.D0.R1.S12: RcvEnCoarse: Latency = 007, RdPtr Offset = 4

END - Basic Read DQ/DQS Training       Time         9144 ms
N1.C0: SettingForTrainingStep: RdCmd2RcvEnLatency = 10, RdPtrOffsetRcvEn = 4
N3.C3.D0.R0.S17: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N5.C0.D0.R1.S13: RcvEnCoarse: Latency = 007, RdPtr Offset = 4

START - Basic Receive Enable Training
N1.C1: QCRM debug: extraRcvEnLatency = 0
N3.C3.D0.R0.S09: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N5.C0.D0.R1.S14: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N7.C0: QCRM debug: extraRcvEnLatency = 0
N1.C1: SettingForTrainingStep: RdCmd2RcvEnLatency = 10, RdPtrOffsetRcvEn = 4
N3.C3.D0.R0.S10: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N5.C0.D0.R1.S15: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N7.C0: SettingForTrainingStep: RdCmd2RcvEnLatency = 10, RdPtrOffsetRcvEn = 4
N1.C2: QCRM debug: extraRcvEnLatency = 0
N3.C3.D0.R0.S11: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N5.C0.D0.R1.S16: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N7.C1: QCRM debug: extraRcvEnLatency = 0
N1.C2: SettingForTrainingStep: RdCmd2RcvEnLatency = 10, RdPtrOffsetRcvEn = 4
N3.C3.D0.R0.S12: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N5.C0.D0.R1.S17: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N7.C1: SettingForTrainingStep: RdCmd2RcvEnLatency = 10, RdPtrOffsetRcvEn = 4
N1.C3: QCRM debug: extraRcvEnLatency = 0
N3.C3.D0.R0.S13: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N5.C0.D0.R1.S09: Preamble found at Latency = 007
N7.C2: QCRM debug: extraRcvEnLatency = 0
N1.C3: SettingForTrainingStep: RdCmd2RcvEnLatency = 10, RdPtrOffsetRcvEn = 4
N3.C3.D0.R0.S14: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N5.C0.D0.R1.S10: Preamble found at Latency = 007
N7.C2: SettingForTrainingStep: RdCmd2RcvEnLatency = 10, RdPtrOffsetRcvEn = 4
N1.C0.D0.R0: RcvEnFine: Initial RdCmd2RcvEnLatency = 10, Initial RdPtrOffsetRcvEn = 4
N3.C3.D0.R0.S15: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N5.C0.D0.R1.S11: Preamble found at Latency = 007
N7.C3: QCRM debug: extraRcvEnLatency = 0
N1.C0.D0.R0.S00: Rcv En Fine Value = 376
N3.C3.D0.R0.S16: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N5.C0.D0.R1.S12: Preamble found at Latency = 007
N7.C3: SettingForTrainingStep: RdCmd2RcvEnLatency = 10, RdPtrOffsetRcvEn = 4
N1.C0.D0.R0.S01: Rcv En Fine Value = 355
N3.C3.D0.R0.S17: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N5.C0.D0.R1.S13: Preamble found at Latency = 007
N7.C0.D0.R0: RcvEnFine: Initial RdCmd2RcvEnLatency = 10, Initial RdPtrOffsetRcvEn = 4
N1.C0.D0.R0.S02: Rcv En Fine Value = 324
N3.C3.D0.R0.S09: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N5.C0.D0.R1.S14: Preamble found at Latency = 007
N7.C0.D0.R0.S00: Rcv En Fine Value = 374
N1.C0.D0.R0.S03: Rcv En Fine Value = 306
N3.C3.D0.R0.S10: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N5.C0.D0.R1.S15: Preamble found at Latency = 007
N7.C0.D0.R0.S01: Rcv En Fine Value = 355
N1.C0.D0.R0.S04: Rcv En Fine Value = 298
N3.C3.D0.R0.S11: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N5.C0.D0.R1.S16: Preamble found at Latency = 007
N7.C0.D0.R0.S02: Rcv En Fine Value = 324
N1.C0.D0.R0.S05: Rcv En Fine Value = 321
N3.C3.D0.R0.S12: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N5.C0.D0.R1.S17: Preamble found at Latency = 007
N7.C0.D0.R0.S03: Rcv En Fine Value = 304
N1.C0.D0.R0.S06: Rcv En Fine Value = 355
N3.C3.D0.R0.S13: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N5.C0.D0.R1: Preamble found for all upper nibbles, adjusting Pi, Offset to center into preamble
N7.C0.D0.R0.S04: Rcv En Fine Value = 299
N1.C0.D0.R0.S07: Rcv En Fine Value = 379
N3.C3.D0.R0.S14: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N5.C0.D0.R1.S09: Total Receive Enable Delay = 1303
N7.C0.D0.R0.S05: Rcv En Fine Value = 323
N1.C0.D0.R0.S08: Rcv En Fine Value = 294
N3.C3.D0.R0.S15: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N5.C0.D0.R1.S10: Total Receive Enable Delay = 1284
N7.C0.D0.R0.S06: Rcv En Fine Value = 356
N1.C0.D0.R0.S09: Rcv En Fine Value = 372
N3.C3.D0.R0.S16: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N5.C0.D0.R1.S11: Total Receive Enable Delay = 1257
N7.C0.D0.R0.S07: Rcv En Fine Value = 380
N1.C0.D0.R0.S10: Rcv En Fine Value = 354
N3.C3.D0.R0.S17: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N5.C0.D0.R1.S12: Total Receive Enable Delay = 1236
N7.C0.D0.R0.S08: Rcv En Fine Value = 296
N1.C0.D0.R0.S11: Rcv En Fine Value = 323
N3.C3.D0.R0.S09: Preamble found at Latency = 008
N5.C0.D0.R1.S13: Total Receive Enable Delay = 1232
N7.C0.D0.R0.S09: Rcv En Fine Value = 372
N1.C0.D0.R0.S12: Rcv En Fine Value = 303
N3.C3.D0.R0.S10: Preamble found at Latency = 008
N5.C0.D0.R1.S14: Total Receive Enable Delay = 1254
N7.C0.D0.R0.S10: Rcv En Fine Value = 353
N1.C0.D0.R0.S13: Rcv En Fine Value = 297
N3.C3.D0.R0.S15: Preamble found at Latency = 008
N5.C0.D0.R1.S15: Total Receive Enable Delay = 1287
N7.C0.D0.R0.S11: Rcv En Fine Value = 322
N1.C0.D0.R0.S14: Rcv En Fine Value = 320
N3.C3.D0.R0.S16: Preamble found at Latency = 008
N5.C0.D0.R1.S16: Total Receive Enable Delay = 1308
N7.C0.D0.R0.S12: Rcv En Fine Value = 303
N1.C0.D0.R0.S15: Rcv En Fine Value = 353
N3.C3.D0.R0.S09: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N5.C0.D0.R1.S17: Total Receive Enable Delay = 1224
N7.C0.D0.R0.S13: Rcv En Fine Value = 297
N1.C0.D0.R0.S16: Rcv En Fine Value = 378
N3.C3.D0.R0.S10: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
START_DATA_REC_EN
N7.C0.D0.R0.S14: Rcv En Fine Value = 321
N1.C0.D0.R0.S17: Rcv En Fine Value = 290
N3.C3.D0.R0.S11: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N5.C0.S00: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N7.C0.D0.R0.S15: Rcv En Fine Value = 355
N1.C0.D0.R0: Starting preamble search lower nibbles
N3.C3.D0.R0.S12: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N5.C0.S01: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N7.C0.D0.R0.S16: Rcv En Fine Value = 380
N1.C0.D0.R0.S00: PI = 056, PtrOffset = 005
N3.C3.D0.R0.S13: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N5.C0.S02: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 5
N7.C0.D0.R0.S17: Rcv En Fine Value = 292
N1.C0.D0.R0.S01: PI = 035, PtrOffset = 005
N3.C3.D0.R0.S14: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N5.C0.S03: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 5
N7.C0.D0.R0: Starting preamble search lower nibbles
N1.C0.D0.R0.S02: PI = 004, PtrOffset = 005
N3.C3.D0.R0.S15: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N5.C0.S04: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 5
N7.C0.D0.R0.S00: PI = 054, PtrOffset = 005
N1.C0.D0.R0.S03: PI = 050, PtrOffset = 004
N3.C3.D0.R0.S16: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N5.C0.S05: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 5
N7.C0.D0.R0.S01: PI = 035, PtrOffset = 005
N1.C0.D0.R0.S04: PI = 042, PtrOffset = 004
N3.C3.D0.R0.S17: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N5.C0.S06: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N7.C0.D0.R0.S02: PI = 004, PtrOffset = 005
N1.C0.D0.R0.S05: PI = 001, PtrOffset = 005
N3.C3.D0.R0.S11: Preamble found at Latency = 007
N5.C0.S07: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N7.C0.D0.R0.S03: PI = 048, PtrOffset = 004
N1.C0.D0.R0.S06: PI = 035, PtrOffset = 005
N3.C3.D0.R0.S12: Preamble found at Latency = 007
N5.C0.S08: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 5
N7.C0.D0.R0.S04: PI = 043, PtrOffset = 004
N1.C0.D0.R0.S07: PI = 059, PtrOffset = 005
N3.C3.D0.R0.S13: Preamble found at Latency = 007
N5.C0.S09: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N7.C0.D0.R0.S05: PI = 003, PtrOffset = 005
N1.C0.D0.R0.S08: PI = 038, PtrOffset = 004
N3.C3.D0.R0.S14: Preamble found at Latency = 007
N5.C0.S10: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N7.C0.D0.R0.S06: PI = 036, PtrOffset = 005
N1.C0.D0.R0.S00: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N3.C3.D0.R0.S17: Preamble found at Latency = 007
N5.C0.S11: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 5
N7.C0.D0.R0.S07: PI = 060, PtrOffset = 005
N1.C0.D0.R0.S01: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N3.C3.D0.R0: Preamble found for all upper nibbles, adjusting Pi, Offset to center into preamble
N5.C0.S12: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 5
N7.C0.D0.R0.S08: PI = 040, PtrOffset = 004
N1.C0.D0.R0.S02: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N3.C3.D0.R0.S09: Total Receive Enable Delay = 1356
N5.C0.S13: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 5
N7.C0.D0.R0.S00: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N1.C0.D0.R0.S03: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N3.C3.D0.R0.S10: Total Receive Enable Delay = 1334
N5.C0.S14: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 5
N7.C0.D0.R0.S01: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N1.C0.D0.R0.S04: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N3.C3.D0.R0.S11: Total Receive Enable Delay = 1303
N5.C0.S15: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N7.C0.D0.R0.S02: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N1.C0.D0.R0.S05: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N3.C3.D0.R0.S12: Total Receive Enable Delay = 1282
N5.C0.S16: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N7.C0.D0.R0.S03: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N1.C0.D0.R0.S06: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N3.C3.D0.R0.S13: Total Receive Enable Delay = 1278
N5.C0.S17: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 5
N7.C0.D0.R0.S04: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N1.C0.D0.R0.S07: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N3.C3.D0.R0.S14: Total Receive Enable Delay = 1302
N5.C0.D0.R0.S00: RcvEn: plus1 = 1, minus1 = 0, PI = 25, DB = 0
N7.C0.D0.R0.S05: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N1.C0.D0.R0.S08: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N3.C3.D0.R0.S15: Total Receive Enable Delay = 1324
N5.C0.D0.R0.S01: RcvEn: plus1 = 1, minus1 = 0, PI = 06, DB = 1
N7.C0.D0.R0.S06: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N1.C0.D0.R0.S00: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N3.C3.D0.R0.S16: Total Receive Enable Delay = 1349
N5.C0.D0.R0.S02: RcvEn: plus1 = 1, minus1 = 0, PI = 39, DB = 0
N7.C0.D0.R0.S07: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N1.C0.D0.R0.S01: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N3.C3.D0.R0.S17: Total Receive Enable Delay = 1263
N5.C0.D0.R0.S03: RcvEn: plus1 = 1, minus1 = 0, PI = 20, DB = 0
N7.C0.D0.R0.S08: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N1.C0.D0.R0.S02: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N3.C3.D0.R1: RcvEnFine: Initial RdCmd2RcvEnLatency = 10, Initial RdPtrOffsetRcvEn = 4
N5.C0.D0.R0.S04: RcvEn: plus1 = 1, minus1 = 0, PI = 16, DB = 0
N7.C0.D0.R0.S00: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N1.C0.D0.R0.S03: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N3.C3.D0.R1.S00: Rcv En Fine Value = 297
N5.C0.D0.R0.S05: RcvEn: plus1 = 1, minus1 = 0, PI = 37, DB = 0
N7.C0.D0.R0.S01: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N1.C0.D0.R0.S04: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N3.C3.D0.R1.S01: Rcv En Fine Value = 278
N5.C0.D0.R0.S06: RcvEn: plus1 = 1, minus1 = 0, PI = 07, DB = 1
N7.C0.D0.R0.S02: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N1.C0.D0.R0.S05: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N3.C3.D0.R1.S02: Rcv En Fine Value = 376
N5.C0.D0.R0.S07: RcvEn: plus1 = 1, minus1 = 0, PI = 28, DB = 0
N7.C0.D0.R0.S03: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N1.C0.D0.R0.S06: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N3.C3.D0.R1.S03: Rcv En Fine Value = 351
N5.C0.D0.R0.S08: RcvEn: plus1 = 1, minus1 = 0, PI = 07, DB = 1
N7.C0.D0.R0.S04: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N1.C0.D0.R0.S07: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N3.C3.D0.R1.S04: Rcv En Fine Value = 347
N5.C0.D0.R0.S09: RcvEn: plus1 = 1, minus1 = 0, PI = 23, DB = 0
N7.C0.D0.R0.S05: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N1.C0.D0.R0.S08: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N3.C3.D0.R1.S05: Rcv En Fine Value = 373
N5.C0.D0.R0.S10: RcvEn: plus1 = 1, minus1 = 0, PI = 04, DB = 1
N7.C0.D0.R0.S06: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N1.C0.D0.R0.S00: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N3.C3.D0.R1.S06: Rcv En Fine Value = 267
N5.C0.D0.R0.S11: RcvEn: plus1 = 1, minus1 = 0, PI = 40, DB = 0
N7.C0.D0.R0.S07: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N1.C0.D0.R0.S01: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N3.C3.D0.R1.S07: Rcv En Fine Value = 291
N5.C0.D0.R0.S12: RcvEn: plus1 = 1, minus1 = 0, PI = 19, DB = 0
N7.C0.D0.R0.S08: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N1.C0.D0.R0.S02: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N3.C3.D0.R1.S08: Rcv En Fine Value = 334
N5.C0.D0.R0.S13: RcvEn: plus1 = 1, minus1 = 0, PI = 15, DB = 1
N7.C0.D0.R0.S00: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N1.C0.D0.R0.S03: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N3.C3.D0.R1.S09: Rcv En Fine Value = 298
N5.C0.D0.R0.S14: RcvEn: plus1 = 1, minus1 = 0, PI = 37, DB = 0
N7.C0.D0.R0.S01: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N1.C0.D0.R0.S04: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N3.C3.D0.R1.S10: Rcv En Fine Value = 277
N5.C0.D0.R0.S15: RcvEn: plus1 = 1, minus1 = 0, PI = 07, DB = 1
N7.C0.D0.R0.S02: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N1.C0.D0.R0.S05: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N3.C3.D0.R1.S11: Rcv En Fine Value = 374
N5.C0.D0.R0.S16: RcvEn: plus1 = 1, minus1 = 0, PI = 27, DB = 0
N7.C0.D0.R0.S03: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N1.C0.D0.R0.S06: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N3.C3.D0.R1.S12: Rcv En Fine Value = 355
N5.C0.D0.R0.S17: RcvEn: plus1 = 1, minus1 = 0, PI = 08, DB = 1
N7.C0.D0.R0.S04: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N1.C0.D0.R0.S07: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N3.C3.D0.R1.S13: Rcv En Fine Value = 348
N5.C0.D0.R1.S00: RcvEn: plus1 = 1, minus1 = 0, PI = 25, DB = 0
N7.C0.D0.R0.S05: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N1.C0.D0.R0.S08: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N3.C3.D0.R1.S14: Rcv En Fine Value = 374
N5.C0.D0.R1.S01: RcvEn: plus1 = 1, minus1 = 0, PI = 06, DB = 1
N7.C0.D0.R0.S06: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N1.C0.D0.R0.S00: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N3.C3.D0.R1.S15: Rcv En Fine Value = 267
N5.C0.D0.R1.S02: RcvEn: plus1 = 1, minus1 = 0, PI = 39, DB = 0
N7.C0.D0.R0.S07: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N1.C0.D0.R0.S01: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N3.C3.D0.R1.S16: Rcv En Fine Value = 292
N5.C0.D0.R1.S03: RcvEn: plus1 = 1, minus1 = 0, PI = 20, DB = 0
N7.C0.D0.R0.S08: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N1.C0.D0.R0.S02: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N3.C3.D0.R1.S17: Rcv En Fine Value = 335
N5.C0.D0.R1.S04: RcvEn: plus1 = 1, minus1 = 0, PI = 16, DB = 0
N7.C0.D0.R0.S00: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N1.C0.D0.R0.S03: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N3.C3.D0.R1: Starting preamble search lower nibbles
N5.C0.D0.R1.S05: RcvEn: plus1 = 1, minus1 = 0, PI = 37, DB = 0
N7.C0.D0.R0.S01: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N1.C0.D0.R0.S04: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N3.C3.D0.R1.S00: PI = 041, PtrOffset = 004
N5.C0.D0.R1.S06: RcvEn: plus1 = 1, minus1 = 0, PI = 07, DB = 1
N7.C0.D0.R0.S02: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N1.C0.D0.R0.S05: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N3.C3.D0.R1.S01: PI = 022, PtrOffset = 004
N5.C0.D0.R1.S07: RcvEn: plus1 = 1, minus1 = 0, PI = 28, DB = 0
N7.C0.D0.R0.S03: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N1.C0.D0.R0.S06: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N3.C3.D0.R1.S02: PI = 056, PtrOffset = 005
N5.C0.D0.R1.S08: RcvEn: plus1 = 1, minus1 = 0, PI = 07, DB = 1
N7.C0.D0.R0.S04: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N1.C0.D0.R0.S07: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N3.C3.D0.R1.S03: PI = 031, PtrOffset = 005
N5.C0.D0.R1.S09: RcvEn: plus1 = 1, minus1 = 0, PI = 23, DB = 0
N7.C0.D0.R0.S05: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N1.C0.D0.R0.S08: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N3.C3.D0.R1.S04: PI = 027, PtrOffset = 005
N5.C0.D0.R1.S10: RcvEn: plus1 = 1, minus1 = 0, PI = 04, DB = 1
N7.C0.D0.R0.S06: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N1.C0.D0.R0.S00: Preamble found at Latency = 007
N3.C3.D0.R1.S05: PI = 053, PtrOffset = 005
N5.C0.D0.R1.S11: RcvEn: plus1 = 1, minus1 = 0, PI = 40, DB = 0
N7.C0.D0.R0.S07: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N1.C0.D0.R0.S01: Preamble found at Latency = 007
N3.C3.D0.R1.S06: PI = 011, PtrOffset = 004
N5.C0.D0.R1.S12: RcvEn: plus1 = 1, minus1 = 0, PI = 19, DB = 0
N7.C0.D0.R0.S08: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N1.C0.D0.R0.S02: Preamble found at Latency = 007
N3.C3.D0.R1.S07: PI = 035, PtrOffset = 004
N5.C0.D0.R1.S13: RcvEn: plus1 = 1, minus1 = 0, PI = 15, DB = 1
N7.C0.D0.R0.S00: Preamble found at Latency = 007
N1.C0.D0.R0.S03: Preamble found at Latency = 007
N3.C3.D0.R1.S08: PI = 014, PtrOffset = 005
N5.C0.D0.R1.S14: RcvEn: plus1 = 1, minus1 = 0, PI = 37, DB = 0
N7.C0.D0.R0.S01: Preamble found at Latency = 007
N1.C0.D0.R0.S04: Preamble found at Latency = 007
N3.C3.D0.R1.S00: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N5.C0.D0.R1.S15: RcvEn: plus1 = 1, minus1 = 0, PI = 07, DB = 1
N7.C0.D0.R0.S02: Preamble found at Latency = 007
N1.C0.D0.R0.S05: Preamble found at Latency = 007
N3.C3.D0.R1.S01: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N5.C0.D0.R1.S16: RcvEn: plus1 = 1, minus1 = 0, PI = 27, DB = 0
N7.C0.D0.R0.S03: Preamble found at Latency = 007
N1.C0.D0.R0.S06: Preamble found at Latency = 007
N3.C3.D0.R1.S02: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N5.C0.D0.R1.S17: RcvEn: plus1 = 1, minus1 = 0, PI = 08, DB = 1
N7.C0.D0.R0.S04: Preamble found at Latency = 007
N1.C0.D0.R0.S07: Preamble found at Latency = 007
N3.C3.D0.R1.S03: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
STOP_DATA_REC_EN
N7.C0.D0.R0.S05: Preamble found at Latency = 007
N1.C0.D0.R0.S08: Preamble found at Latency = 007
N3.C3.D0.R1.S04: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N5.C1.D0.R0: RcvEnFine: Initial RdCmd2RcvEnLatency = 10, Initial RdPtrOffsetRcvEn = 4
N7.C0.D0.R0.S06: Preamble found at Latency = 007
N1.C0.D0.R0.S00: Total Receive Enable Delay = 1304
N3.C3.D0.R1.S05: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N5.C1.D0.R0.S00: Rcv En Fine Value = 302
N7.C0.D0.R0.S07: Preamble found at Latency = 007
N1.C0.D0.R0.S01: Total Receive Enable Delay = 1283
N3.C3.D0.R1.S06: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N5.C1.D0.R0.S01: Rcv En Fine Value = 284
N7.C0.D0.R0.S08: Preamble found at Latency = 007
N1.C0.D0.R0.S02: Total Receive Enable Delay = 1252
N3.C3.D0.R1.S07: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N5.C1.D0.R0.S02: Rcv En Fine Value = 378
N7.C0.D0.R0.S00: Total Receive Enable Delay = 1302
N1.C0.D0.R0.S03: Total Receive Enable Delay = 1234
N3.C3.D0.R1.S08: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N5.C1.D0.R0.S03: Rcv En Fine Value = 360
N7.C0.D0.R0.S01: Total Receive Enable Delay = 1283
N1.C0.D0.R0.S04: Total Receive Enable Delay = 1226
N3.C3.D0.R1.S00: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N5.C1.D0.R0.S04: Rcv En Fine Value = 352
N7.C0.D0.R0.S02: Total Receive Enable Delay = 1252
N1.C0.D0.R0.S05: Total Receive Enable Delay = 1249
N3.C3.D0.R1.S01: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N5.C1.D0.R0.S05: Rcv En Fine Value = 378
N7.C0.D0.R0.S03: Total Receive Enable Delay = 1232
N1.C0.D0.R0.S06: Total Receive Enable Delay = 1283
N3.C3.D0.R1.S02: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N5.C1.D0.R0.S06: Rcv En Fine Value = 278
N7.C0.D0.R0.S04: Total Receive Enable Delay = 1227
N1.C0.D0.R0.S07: Total Receive Enable Delay = 1307
N3.C3.D0.R1.S03: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N5.C1.D0.R0.S07: Rcv En Fine Value = 295
N7.C0.D0.R0.S05: Total Receive Enable Delay = 1251
N1.C0.D0.R0.S08: Total Receive Enable Delay = 1222
N3.C3.D0.R1.S04: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N5.C1.D0.R0.S08: Rcv En Fine Value = 336
N7.C0.D0.R0.S06: Total Receive Enable Delay = 1284
N1.C0.D0.R0: Starting preamble search upper nibbles
N3.C3.D0.R1.S05: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N5.C1.D0.R0.S09: Rcv En Fine Value = 298
N7.C0.D0.R0.S07: Total Receive Enable Delay = 1308
N1.C0.D0.R0.S09: PI = 052, PtrOffset = 005
N3.C3.D0.R1.S06: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N5.C1.D0.R0.S10: Rcv En Fine Value = 281
N7.C0.D0.R0.S08: Total Receive Enable Delay = 1224
N1.C0.D0.R0.S10: PI = 034, PtrOffset = 005
N3.C3.D0.R1.S07: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N5.C1.D0.R0.S11: Rcv En Fine Value = 379
N7.C0.D0.R0: Starting preamble search upper nibbles
N1.C0.D0.R0.S11: PI = 003, PtrOffset = 005
N3.C3.D0.R1.S08: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N5.C1.D0.R0.S12: Rcv En Fine Value = 356
N7.C0.D0.R0.S09: PI = 052, PtrOffset = 005
N1.C0.D0.R0.S12: PI = 047, PtrOffset = 004
N3.C3.D0.R1.S00: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N5.C1.D0.R0.S13: Rcv En Fine Value = 350
N7.C0.D0.R0.S10: PI = 033, PtrOffset = 005
N1.C0.D0.R0.S13: PI = 041, PtrOffset = 004
N3.C3.D0.R1.S01: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N5.C1.D0.R0.S14: Rcv En Fine Value = 377
N7.C0.D0.R0.S11: PI = 002, PtrOffset = 005
N1.C0.D0.R0.S14: PI = 000, PtrOffset = 005
N3.C3.D0.R1.S02: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N5.C1.D0.R0.S15: Rcv En Fine Value = 273
N7.C0.D0.R0.S12: PI = 047, PtrOffset = 004
N1.C0.D0.R0.S15: PI = 033, PtrOffset = 005
N3.C3.D0.R1.S03: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N5.C1.D0.R0.S16: Rcv En Fine Value = 295
N7.C0.D0.R0.S13: PI = 041, PtrOffset = 004
N1.C0.D0.R0.S16: PI = 058, PtrOffset = 005
N3.C3.D0.R1.S04: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N5.C1.D0.R0.S17: Rcv En Fine Value = 342
N7.C0.D0.R0.S14: PI = 001, PtrOffset = 005
N1.C0.D0.R0.S17: PI = 034, PtrOffset = 004
N3.C3.D0.R1.S05: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N5.C1.D0.R0: Starting preamble search lower nibbles
N7.C0.D0.R0.S15: PI = 035, PtrOffset = 005
N1.C0.D0.R0.S09: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N3.C3.D0.R1.S06: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N5.C1.D0.R0.S00: PI = 046, PtrOffset = 004
N7.C0.D0.R0.S16: PI = 060, PtrOffset = 005
N1.C0.D0.R0.S10: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N3.C3.D0.R1.S07: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N5.C1.D0.R0.S01: PI = 028, PtrOffset = 004
N7.C0.D0.R0.S17: PI = 036, PtrOffset = 004
N1.C0.D0.R0.S11: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N3.C3.D0.R1.S08: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N5.C1.D0.R0.S02: PI = 058, PtrOffset = 005
N7.C0.D0.R0.S09: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N1.C0.D0.R0.S12: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N3.C3.D0.R1.S00: Preamble found at Latency = 008
N5.C1.D0.R0.S03: PI = 040, PtrOffset = 005
N7.C0.D0.R0.S10: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N1.C0.D0.R0.S13: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N3.C3.D0.R1.S01: Preamble found at Latency = 008
N5.C1.D0.R0.S04: PI = 032, PtrOffset = 005
N7.C0.D0.R0.S11: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N1.C0.D0.R0.S14: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N3.C3.D0.R1.S06: Preamble found at Latency = 008
N5.C1.D0.R0.S05: PI = 058, PtrOffset = 005
N7.C0.D0.R0.S12: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N1.C0.D0.R0.S15: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N3.C3.D0.R1.S07: Preamble found at Latency = 008
N5.C1.D0.R0.S06: PI = 022, PtrOffset = 004
N7.C0.D0.R0.S13: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N1.C0.D0.R0.S16: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N3.C3.D0.R1.S00: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N5.C1.D0.R0.S07: PI = 039, PtrOffset = 004
N7.C0.D0.R0.S14: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N1.C0.D0.R0.S17: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N3.C3.D0.R1.S01: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N5.C1.D0.R0.S08: PI = 016, PtrOffset = 005
N7.C0.D0.R0.S15: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N1.C0.D0.R0.S09: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N3.C3.D0.R1.S02: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N5.C1.D0.R0.S00: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N7.C0.D0.R0.S16: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N1.C0.D0.R0.S10: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N3.C3.D0.R1.S03: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N5.C1.D0.R0.S01: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N7.C0.D0.R0.S17: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N1.C0.D0.R0.S11: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N3.C3.D0.R1.S04: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N5.C1.D0.R0.S02: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N7.C0.D0.R0.S09: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N1.C0.D0.R0.S12: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N3.C3.D0.R1.S05: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N5.C1.D0.R0.S03: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N7.C0.D0.R0.S10: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N1.C0.D0.R0.S13: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N3.C3.D0.R1.S06: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N5.C1.D0.R0.S04: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N7.C0.D0.R0.S11: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N1.C0.D0.R0.S14: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N3.C3.D0.R1.S07: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N5.C1.D0.R0.S05: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N7.C0.D0.R0.S12: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N1.C0.D0.R0.S15: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N3.C3.D0.R1.S08: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N5.C1.D0.R0.S06: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N7.C0.D0.R0.S13: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N1.C0.D0.R0.S16: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N3.C3.D0.R1.S02: Preamble found at Latency = 007
N5.C1.D0.R0.S07: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N7.C0.D0.R0.S14: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N1.C0.D0.R0.S17: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N3.C3.D0.R1.S03: Preamble found at Latency = 007
N5.C1.D0.R0.S08: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N7.C0.D0.R0.S15: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N1.C0.D0.R0.S09: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N3.C3.D0.R1.S04: Preamble found at Latency = 007
N5.C1.D0.R0.S00: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N7.C0.D0.R0.S16: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N1.C0.D0.R0.S10: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N3.C3.D0.R1.S05: Preamble found at Latency = 007
N5.C1.D0.R0.S01: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N7.C0.D0.R0.S17: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N1.C0.D0.R0.S11: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N3.C3.D0.R1.S08: Preamble found at Latency = 007
N5.C1.D0.R0.S02: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N7.C0.D0.R0.S09: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N1.C0.D0.R0.S12: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N3.C3.D0.R1.S00: Total Receive Enable Delay = 1353
N5.C1.D0.R0.S03: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N7.C0.D0.R0.S10: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N1.C0.D0.R0.S13: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N3.C3.D0.R1.S01: Total Receive Enable Delay = 1334
N5.C1.D0.R0.S04: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N7.C0.D0.R0.S11: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N1.C0.D0.R0.S14: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N3.C3.D0.R1.S02: Total Receive Enable Delay = 1304
N5.C1.D0.R0.S05: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N7.C0.D0.R0.S12: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N1.C0.D0.R0.S15: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N3.C3.D0.R1.S03: Total Receive Enable Delay = 1279
N5.C1.D0.R0.S06: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N7.C0.D0.R0.S13: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N1.C0.D0.R0.S16: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N3.C3.D0.R1.S04: Total Receive Enable Delay = 1275
N5.C1.D0.R0.S07: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N7.C0.D0.R0.S14: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N1.C0.D0.R0.S17: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N3.C3.D0.R1.S05: Total Receive Enable Delay = 1301
N5.C1.D0.R0.S08: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N7.C0.D0.R0.S15: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N1.C0.D0.R0.S09: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N3.C3.D0.R1.S06: Total Receive Enable Delay = 1323
N5.C1.D0.R0.S00: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N7.C0.D0.R0.S16: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N1.C0.D0.R0.S10: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N3.C3.D0.R1.S07: Total Receive Enable Delay = 1347
N5.C1.D0.R0.S01: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N7.C0.D0.R0.S17: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N1.C0.D0.R0.S11: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N3.C3.D0.R1.S08: Total Receive Enable Delay = 1262
N5.C1.D0.R0.S02: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N7.C0.D0.R0.S09: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N1.C0.D0.R0.S12: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N3.C3.D0.R1: Starting preamble search upper nibbles
N5.C1.D0.R0.S03: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N7.C0.D0.R0.S10: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N1.C0.D0.R0.S13: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N3.C3.D0.R1.S09: PI = 042, PtrOffset = 004
N5.C1.D0.R0.S04: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N7.C0.D0.R0.S11: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N1.C0.D0.R0.S14: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N3.C3.D0.R1.S10: PI = 021, PtrOffset = 004
N5.C1.D0.R0.S05: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N7.C0.D0.R0.S12: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N1.C0.D0.R0.S15: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N3.C3.D0.R1.S11: PI = 054, PtrOffset = 005
N5.C1.D0.R0.S06: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N7.C0.D0.R0.S13: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N1.C0.D0.R0.S16: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N3.C3.D0.R1.S12: PI = 035, PtrOffset = 005
N5.C1.D0.R0.S07: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N7.C0.D0.R0.S14: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N1.C0.D0.R0.S17: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N3.C3.D0.R1.S13: PI = 028, PtrOffset = 005
N5.C1.D0.R0.S08: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N7.C0.D0.R0.S15: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N1.C0.D0.R0.S09: Preamble found at Latency = 007
N3.C3.D0.R1.S14: PI = 054, PtrOffset = 005
N5.C1.D0.R0.S00: Preamble found at Latency = 008
N7.C0.D0.R0.S16: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N1.C0.D0.R0.S10: Preamble found at Latency = 007
N3.C3.D0.R1.S15: PI = 011, PtrOffset = 004
N5.C1.D0.R0.S01: Preamble found at Latency = 008
N7.C0.D0.R0.S17: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N1.C0.D0.R0.S11: Preamble found at Latency = 007
N3.C3.D0.R1.S16: PI = 036, PtrOffset = 004
N5.C1.D0.R0.S06: Preamble found at Latency = 008
N7.C0.D0.R0.S09: Preamble found at Latency = 007
N1.C0.D0.R0.S12: Preamble found at Latency = 007
N3.C3.D0.R1.S17: PI = 015, PtrOffset = 005
N5.C1.D0.R0.S07: Preamble found at Latency = 008
N7.C0.D0.R0.S10: Preamble found at Latency = 007
N1.C0.D0.R0.S13: Preamble found at Latency = 007
N3.C3.D0.R1.S09: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N5.C1.D0.R0.S00: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N7.C0.D0.R0.S11: Preamble found at Latency = 007
N1.C0.D0.R0.S14: Preamble found at Latency = 007
N3.C3.D0.R1.S10: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N5.C1.D0.R0.S01: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N7.C0.D0.R0.S12: Preamble found at Latency = 007
N1.C0.D0.R0.S15: Preamble found at Latency = 007
N3.C3.D0.R1.S11: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N5.C1.D0.R0.S02: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N7.C0.D0.R0.S13: Preamble found at Latency = 007
N1.C0.D0.R0.S16: Preamble found at Latency = 007
N3.C3.D0.R1.S12: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N5.C1.D0.R0.S03: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N7.C0.D0.R0.S14: Preamble found at Latency = 007
N1.C0.D0.R0.S17: Preamble found at Latency = 007
N3.C3.D0.R1.S13: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N5.C1.D0.R0.S04: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N7.C0.D0.R0.S15: Preamble found at Latency = 007
N1.C0.D0.R0: Preamble found for all upper nibbles, adjusting Pi, Offset to center into preamble
N3.C3.D0.R1.S14: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N5.C1.D0.R0.S05: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N7.C0.D0.R0.S16: Preamble found at Latency = 007
N1.C0.D0.R0.S09: Total Receive Enable Delay = 1300
N3.C3.D0.R1.S15: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N5.C1.D0.R0.S06: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N7.C0.D0.R0.S17: Preamble found at Latency = 007
N1.C0.D0.R0.S10: Total Receive Enable Delay = 1282
N3.C3.D0.R1.S16: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N5.C1.D0.R0.S07: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N7.C0.D0.R0: Preamble found for all upper nibbles, adjusting Pi, Offset to center into preamble
N1.C0.D0.R0.S11: Total Receive Enable Delay = 1251
N3.C3.D0.R1.S17: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N5.C1.D0.R0.S08: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N7.C0.D0.R0.S09: Total Receive Enable Delay = 1300
N1.C0.D0.R0.S12: Total Receive Enable Delay = 1231
N3.C3.D0.R1.S09: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N5.C1.D0.R0.S02: Preamble found at Latency = 007
N7.C0.D0.R0.S10: Total Receive Enable Delay = 1281
N1.C0.D0.R0.S13: Total Receive Enable Delay = 1225
N3.C3.D0.R1.S10: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N5.C1.D0.R0.S03: Preamble found at Latency = 007
N7.C0.D0.R0.S11: Total Receive Enable Delay = 1250
N1.C0.D0.R0.S14: Total Receive Enable Delay = 1248
N3.C3.D0.R1.S11: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N5.C1.D0.R0.S04: Preamble found at Latency = 007
N7.C0.D0.R0.S12: Total Receive Enable Delay = 1231
N1.C0.D0.R0.S15: Total Receive Enable Delay = 1281
N3.C3.D0.R1.S12: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N5.C1.D0.R0.S05: Preamble found at Latency = 007
N7.C0.D0.R0.S13: Total Receive Enable Delay = 1225
N1.C0.D0.R0.S16: Total Receive Enable Delay = 1306
N3.C3.D0.R1.S13: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N5.C1.D0.R0.S08: Preamble found at Latency = 007
N7.C0.D0.R0.S14: Total Receive Enable Delay = 1249
N1.C0.D0.R0.S17: Total Receive Enable Delay = 1218
N3.C3.D0.R1.S14: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N5.C1.D0.R0.S00: Total Receive Enable Delay = 1358
N7.C0.D0.R0.S15: Total Receive Enable Delay = 1283
N1.C0.D0.R1: RcvEnFine: Initial RdCmd2RcvEnLatency = 10, Initial RdPtrOffsetRcvEn = 4
N3.C3.D0.R1.S15: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N5.C1.D0.R0.S01: Total Receive Enable Delay = 1340
N7.C0.D0.R0.S16: Total Receive Enable Delay = 1308
N1.C0.D0.R1.S00: Rcv En Fine Value = 378
N3.C3.D0.R1.S16: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N5.C1.D0.R0.S02: Total Receive Enable Delay = 1306
N7.C0.D0.R0.S17: Total Receive Enable Delay = 1220
N1.C0.D0.R1.S01: Rcv En Fine Value = 355
N3.C3.D0.R1.S17: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N5.C1.D0.R0.S03: Total Receive Enable Delay = 1288
N7.C0.D0.R1: RcvEnFine: Initial RdCmd2RcvEnLatency = 10, Initial RdPtrOffsetRcvEn = 4
N1.C0.D0.R1.S02: Rcv En Fine Value = 325
N3.C3.D0.R1.S09: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N5.C1.D0.R0.S04: Total Receive Enable Delay = 1280
N7.C0.D0.R1.S00: Rcv En Fine Value = 374
N1.C0.D0.R1.S03: Rcv En Fine Value = 304
N3.C3.D0.R1.S10: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N5.C1.D0.R0.S05: Total Receive Enable Delay = 1306
N7.C0.D0.R1.S01: Rcv En Fine Value = 352
N1.C0.D0.R1.S04: Rcv En Fine Value = 298
N3.C3.D0.R1.S11: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N5.C1.D0.R0.S06: Total Receive Enable Delay = 1334
N7.C0.D0.R1.S02: Rcv En Fine Value = 324
N1.C0.D0.R1.S05: Rcv En Fine Value = 322
N3.C3.D0.R1.S12: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N5.C1.D0.R0.S07: Total Receive Enable Delay = 1351
N7.C0.D0.R1.S03: Rcv En Fine Value = 305
N1.C0.D0.R1.S06: Rcv En Fine Value = 354
N3.C3.D0.R1.S13: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N5.C1.D0.R0.S08: Total Receive Enable Delay = 1264
N7.C0.D0.R1.S04: Rcv En Fine Value = 297
N1.C0.D0.R1.S07: Rcv En Fine Value = 378
N3.C3.D0.R1.S14: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N5.C1.D0.R0: Starting preamble search upper nibbles
N7.C0.D0.R1.S05: Rcv En Fine Value = 324
N1.C0.D0.R1.S08: Rcv En Fine Value = 293
N3.C3.D0.R1.S15: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N5.C1.D0.R0.S09: PI = 042, PtrOffset = 004
N7.C0.D0.R1.S06: Rcv En Fine Value = 356
N1.C0.D0.R1.S09: Rcv En Fine Value = 374
N3.C3.D0.R1.S16: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N5.C1.D0.R0.S10: PI = 025, PtrOffset = 004
N7.C0.D0.R1.S07: Rcv En Fine Value = 379
N1.C0.D0.R1.S10: Rcv En Fine Value = 353
N3.C3.D0.R1.S17: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N5.C1.D0.R0.S11: PI = 059, PtrOffset = 005
N7.C0.D0.R1.S08: Rcv En Fine Value = 293
N1.C0.D0.R1.S11: Rcv En Fine Value = 323
N3.C3.D0.R1.S09: Preamble found at Latency = 008
N5.C1.D0.R0.S12: PI = 036, PtrOffset = 005
N7.C0.D0.R1.S09: Rcv En Fine Value = 371
N1.C0.D0.R1.S12: Rcv En Fine Value = 305
N3.C3.D0.R1.S10: Preamble found at Latency = 008
N5.C1.D0.R0.S13: PI = 030, PtrOffset = 005
N7.C0.D0.R1.S10: Rcv En Fine Value = 353
N1.C0.D0.R1.S13: Rcv En Fine Value = 296
N3.C3.D0.R1.S15: Preamble found at Latency = 008
N5.C1.D0.R0.S14: PI = 057, PtrOffset = 005
N7.C0.D0.R1.S11: Rcv En Fine Value = 322
N1.C0.D0.R1.S14: Rcv En Fine Value = 322
N3.C3.D0.R1.S16: Preamble found at Latency = 008
N5.C1.D0.R0.S15: PI = 017, PtrOffset = 004
N7.C0.D0.R1.S12: Rcv En Fine Value = 303
N1.C0.D0.R1.S15: Rcv En Fine Value = 355
N3.C3.D0.R1.S09: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N5.C1.D0.R0.S16: PI = 039, PtrOffset = 004
N7.C0.D0.R1.S13: Rcv En Fine Value = 298
N1.C0.D0.R1.S16: Rcv En Fine Value = 375
N3.C3.D0.R1.S10: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N5.C1.D0.R0.S17: PI = 022, PtrOffset = 005
N7.C0.D0.R1.S14: Rcv En Fine Value = 320
N1.C0.D0.R1.S17: Rcv En Fine Value = 292
N3.C3.D0.R1.S11: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N5.C1.D0.R0.S09: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N7.C0.D0.R1.S15: Rcv En Fine Value = 354
N1.C0.D0.R1: Starting preamble search lower nibbles
N3.C3.D0.R1.S12: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N5.C1.D0.R0.S10: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N7.C0.D0.R1.S16: Rcv En Fine Value = 379
N1.C0.D0.R1.S00: PI = 058, PtrOffset = 005
N3.C3.D0.R1.S13: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N5.C1.D0.R0.S11: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N7.C0.D0.R1.S17: Rcv En Fine Value = 292
N1.C0.D0.R1.S01: PI = 035, PtrOffset = 005
N3.C3.D0.R1.S14: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N5.C1.D0.R0.S12: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N7.C0.D0.R1: Starting preamble search lower nibbles
N1.C0.D0.R1.S02: PI = 005, PtrOffset = 005
N3.C3.D0.R1.S15: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N5.C1.D0.R0.S13: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N7.C0.D0.R1.S00: PI = 054, PtrOffset = 005
N1.C0.D0.R1.S03: PI = 048, PtrOffset = 004
N3.C3.D0.R1.S16: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N5.C1.D0.R0.S14: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N7.C0.D0.R1.S01: PI = 032, PtrOffset = 005
N1.C0.D0.R1.S04: PI = 042, PtrOffset = 004
N3.C3.D0.R1.S17: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N5.C1.D0.R0.S15: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N7.C0.D0.R1.S02: PI = 004, PtrOffset = 005
N1.C0.D0.R1.S05: PI = 002, PtrOffset = 005
N3.C3.D0.R1.S11: Preamble found at Latency = 007
N5.C1.D0.R0.S16: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N7.C0.D0.R1.S03: PI = 049, PtrOffset = 004
N1.C0.D0.R1.S06: PI = 034, PtrOffset = 005
N3.C3.D0.R1.S12: Preamble found at Latency = 007
N5.C1.D0.R0.S17: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N7.C0.D0.R1.S04: PI = 041, PtrOffset = 004
N1.C0.D0.R1.S07: PI = 058, PtrOffset = 005
N3.C3.D0.R1.S13: Preamble found at Latency = 007
N5.C1.D0.R0.S09: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N7.C0.D0.R1.S05: PI = 004, PtrOffset = 005
N1.C0.D0.R1.S08: PI = 037, PtrOffset = 004
N3.C3.D0.R1.S14: Preamble found at Latency = 007
N5.C1.D0.R0.S10: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N7.C0.D0.R1.S06: PI = 036, PtrOffset = 005
N1.C0.D0.R1.S00: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N3.C3.D0.R1.S17: Preamble found at Latency = 007
N5.C1.D0.R0.S11: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N7.C0.D0.R1.S07: PI = 059, PtrOffset = 005
N1.C0.D0.R1.S01: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N3.C3.D0.R1: Preamble found for all upper nibbles, adjusting Pi, Offset to center into preamble
N5.C1.D0.R0.S12: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N7.C0.D0.R1.S08: PI = 037, PtrOffset = 004
N1.C0.D0.R1.S02: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N3.C3.D0.R1.S09: Total Receive Enable Delay = 1354
N5.C1.D0.R0.S13: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N7.C0.D0.R1.S00: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N1.C0.D0.R1.S03: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N3.C3.D0.R1.S10: Total Receive Enable Delay = 1333
N5.C1.D0.R0.S14: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N7.C0.D0.R1.S01: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N1.C0.D0.R1.S04: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N3.C3.D0.R1.S11: Total Receive Enable Delay = 1302
N5.C1.D0.R0.S15: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N7.C0.D0.R1.S02: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N1.C0.D0.R1.S05: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N3.C3.D0.R1.S12: Total Receive Enable Delay = 1283
N5.C1.D0.R0.S16: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N7.C0.D0.R1.S03: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N1.C0.D0.R1.S06: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N3.C3.D0.R1.S13: Total Receive Enable Delay = 1276
N5.C1.D0.R0.S17: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N7.C0.D0.R1.S04: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N1.C0.D0.R1.S07: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N3.C3.D0.R1.S14: Total Receive Enable Delay = 1302
N5.C1.D0.R0.S09: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N7.C0.D0.R1.S05: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N1.C0.D0.R1.S08: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N3.C3.D0.R1.S15: Total Receive Enable Delay = 1323
N5.C1.D0.R0.S10: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N7.C0.D0.R1.S06: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N1.C0.D0.R1.S00: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N3.C3.D0.R1.S16: Total Receive Enable Delay = 1348
N5.C1.D0.R0.S11: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N7.C0.D0.R1.S07: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N1.C0.D0.R1.S01: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N3.C3.D0.R1.S17: Total Receive Enable Delay = 1263
N5.C1.D0.R0.S12: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N7.C0.D0.R1.S08: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N1.C0.D0.R1.S02: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
START_DATA_REC_EN
N5.C1.D0.R0.S13: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N7.C0.D0.R1.S00: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N1.C0.D0.R1.S03: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N3.C3.S00: RdCmd2RcvEnLatency = 9, RdPtrOffsetRcvEn = 5
N5.C1.D0.R0.S14: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N7.C0.D0.R1.S01: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N1.C0.D0.R1.S04: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N3.C3.S01: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N5.C1.D0.R0.S15: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N7.C0.D0.R1.S02: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N1.C0.D0.R1.S05: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N3.C3.S02: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N5.C1.D0.R0.S16: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N7.C0.D0.R1.S03: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N1.C0.D0.R1.S06: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N3.C3.S03: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N5.C1.D0.R0.S17: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N7.C0.D0.R1.S04: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N1.C0.D0.R1.S07: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N3.C3.S04: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 5
N5.C1.D0.R0.S09: Preamble found at Latency = 008
N7.C0.D0.R1.S05: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N1.C0.D0.R1.S08: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N3.C3.S05: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N5.C1.D0.R0.S10: Preamble found at Latency = 008
N7.C0.D0.R1.S06: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N1.C0.D0.R1.S00: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N3.C3.S06: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N5.C1.D0.R0.S15: Preamble found at Latency = 008
N7.C0.D0.R1.S07: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N1.C0.D0.R1.S01: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N3.C3.S07: RdCmd2RcvEnLatency = 9, RdPtrOffsetRcvEn = 5
N5.C1.D0.R0.S16: Preamble found at Latency = 008
N7.C0.D0.R1.S08: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N1.C0.D0.R1.S02: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N3.C3.S08: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 5
N5.C1.D0.R0.S09: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N7.C0.D0.R1.S00: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N1.C0.D0.R1.S03: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N3.C3.S09: RdCmd2RcvEnLatency = 9, RdPtrOffsetRcvEn = 5
N5.C1.D0.R0.S10: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N7.C0.D0.R1.S01: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N1.C0.D0.R1.S04: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N3.C3.S10: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N5.C1.D0.R0.S11: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N7.C0.D0.R1.S02: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N1.C0.D0.R1.S05: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N3.C3.S11: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N5.C1.D0.R0.S12: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N7.C0.D0.R1.S03: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N1.C0.D0.R1.S06: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N3.C3.S12: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N5.C1.D0.R0.S13: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N7.C0.D0.R1.S04: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N1.C0.D0.R1.S07: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N3.C3.S13: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 5
N5.C1.D0.R0.S14: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N7.C0.D0.R1.S05: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N1.C0.D0.R1.S08: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N3.C3.S14: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N5.C1.D0.R0.S15: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N7.C0.D0.R1.S06: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N1.C0.D0.R1.S00: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N3.C3.S15: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N5.C1.D0.R0.S16: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N7.C0.D0.R1.S07: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N1.C0.D0.R1.S01: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N3.C3.S16: RdCmd2RcvEnLatency = 9, RdPtrOffsetRcvEn = 5
N5.C1.D0.R0.S17: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N7.C0.D0.R1.S08: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N1.C0.D0.R1.S02: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N3.C3.S17: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 5
N5.C1.D0.R0.S11: Preamble found at Latency = 007
N7.C0.D0.R1.S00: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N1.C0.D0.R1.S03: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N3.C3.D0.R0.S00: RcvEn: plus1 = 1, minus1 = 0, PI = 09, DB = 1
N5.C1.D0.R0.S12: Preamble found at Latency = 007
N7.C0.D0.R1.S01: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N1.C0.D0.R1.S04: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N3.C3.D0.R0.S01: RcvEn: plus1 = 1, minus1 = 0, PI = 52, DB = 1
N5.C1.D0.R0.S13: Preamble found at Latency = 007
N7.C0.D0.R1.S02: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N1.C0.D0.R1.S05: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N3.C3.D0.R0.S02: RcvEn: plus1 = 1, minus1 = 0, PI = 25, DB = 0
N5.C1.D0.R0.S14: Preamble found at Latency = 007
N7.C0.D0.R1.S03: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N1.C0.D0.R1.S06: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N3.C3.D0.R0.S03: RcvEn: plus1 = 1, minus1 = 0, PI = 00, DB = 1
N5.C1.D0.R0.S17: Preamble found at Latency = 007
N7.C0.D0.R1.S04: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N1.C0.D0.R1.S07: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N3.C3.D0.R0.S04: RcvEn: plus1 = 1, minus1 = 0, PI = 60, DB = 1
N5.C1.D0.R0: Preamble found for all upper nibbles, adjusting Pi, Offset to center into preamble
N7.C0.D0.R1.S05: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N1.C0.D0.R1.S08: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N3.C3.D0.R0.S05: RcvEn: plus1 = 1, minus1 = 0, PI = 21, DB = 0
N5.C1.D0.R0.S09: Total Receive Enable Delay = 1354
N7.C0.D0.R1.S06: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N1.C0.D0.R1.S00: Preamble found at Latency = 007
N3.C3.D0.R0.S06: RcvEn: plus1 = 1, minus1 = 0, PI = 43, DB = 0
N5.C1.D0.R0.S10: Total Receive Enable Delay = 1337
N7.C0.D0.R1.S07: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N1.C0.D0.R1.S01: Preamble found at Latency = 007
N3.C3.D0.R0.S07: RcvEn: plus1 = 1, minus1 = 0, PI = 04, DB = 1
N5.C1.D0.R0.S11: Total Receive Enable Delay = 1307
N7.C0.D0.R1.S08: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N1.C0.D0.R1.S02: Preamble found at Latency = 007
N3.C3.D0.R0.S08: RcvEn: plus1 = 1, minus1 = 0, PI = 46, DB = 0
N5.C1.D0.R0.S12: Total Receive Enable Delay = 1284
N7.C0.D0.R1.S00: Preamble found at Latency = 007
N1.C0.D0.R1.S03: Preamble found at Latency = 007
N3.C3.D0.R0.S09: RcvEn: plus1 = 1, minus1 = 0, PI = 11, DB = 1
N5.C1.D0.R0.S13: Total Receive Enable Delay = 1278
N7.C0.D0.R1.S01: Preamble found at Latency = 007
N1.C0.D0.R1.S04: Preamble found at Latency = 007
N3.C3.D0.R0.S10: RcvEn: plus1 = 1, minus1 = 0, PI = 53, DB = 1
N5.C1.D0.R0.S14: Total Receive Enable Delay = 1305
N7.C0.D0.R1.S02: Preamble found at Latency = 007
N1.C0.D0.R1.S05: Preamble found at Latency = 007
N3.C3.D0.R0.S11: RcvEn: plus1 = 1, minus1 = 0, PI = 22, DB = 0
N5.C1.D0.R0.S15: Total Receive Enable Delay = 1329
N7.C0.D0.R1.S03: Preamble found at Latency = 007
N1.C0.D0.R1.S06: Preamble found at Latency = 007
N3.C3.D0.R0.S12: RcvEn: plus1 = 1, minus1 = 0, PI = 02, DB = 1
N5.C1.D0.R0.S16: Total Receive Enable Delay = 1351
N7.C0.D0.R1.S04: Preamble found at Latency = 007
N1.C0.D0.R1.S07: Preamble found at Latency = 007
N3.C3.D0.R0.S13: RcvEn: plus1 = 1, minus1 = 0, PI = 61, DB = 1
N5.C1.D0.R0.S17: Total Receive Enable Delay = 1270
N7.C0.D0.R1.S05: Preamble found at Latency = 007
N1.C0.D0.R1.S08: Preamble found at Latency = 007
N3.C3.D0.R0.S14: RcvEn: plus1 = 1, minus1 = 0, PI = 22, DB = 0
N5.C1.D0.R1: RcvEnFine: Initial RdCmd2RcvEnLatency = 10, Initial RdPtrOffsetRcvEn = 4
N7.C0.D0.R1.S06: Preamble found at Latency = 007
N1.C0.D0.R1.S00: Total Receive Enable Delay = 1306
N3.C3.D0.R0.S15: RcvEn: plus1 = 1, minus1 = 0, PI = 43, DB = 0
N5.C1.D0.R1.S00: Rcv En Fine Value = 302
N7.C0.D0.R1.S07: Preamble found at Latency = 007
N1.C0.D0.R1.S01: Total Receive Enable Delay = 1283
N3.C3.D0.R0.S16: RcvEn: plus1 = 1, minus1 = 0, PI = 04, DB = 1
N5.C1.D0.R1.S01: Rcv En Fine Value = 282
N7.C0.D0.R1.S08: Preamble found at Latency = 007
N1.C0.D0.R1.S02: Total Receive Enable Delay = 1253
N3.C3.D0.R0.S17: RcvEn: plus1 = 1, minus1 = 0, PI = 47, DB = 0
N5.C1.D0.R1.S02: Rcv En Fine Value = 378
N7.C0.D0.R1.S00: Total Receive Enable Delay = 1302
N1.C0.D0.R1.S03: Total Receive Enable Delay = 1232
N3.C3.D0.R1.S00: RcvEn: plus1 = 1, minus1 = 0, PI = 09, DB = 1
N5.C1.D0.R1.S03: Rcv En Fine Value = 357
N7.C0.D0.R1.S01: Total Receive Enable Delay = 1280
N1.C0.D0.R1.S04: Total Receive Enable Delay = 1226
N3.C3.D0.R1.S01: RcvEn: plus1 = 1, minus1 = 0, PI = 52, DB = 1
N5.C1.D0.R1.S04: Rcv En Fine Value = 350
N7.C0.D0.R1.S02: Total Receive Enable Delay = 1252
N1.C0.D0.R1.S05: Total Receive Enable Delay = 1250
N3.C3.D0.R1.S02: RcvEn: plus1 = 1, minus1 = 0, PI = 25, DB = 0
N5.C1.D0.R1.S05: Rcv En Fine Value = 377
N7.C0.D0.R1.S03: Total Receive Enable Delay = 1233
N1.C0.D0.R1.S06: Total Receive Enable Delay = 1282
N3.C3.D0.R1.S03: RcvEn: plus1 = 1, minus1 = 0, PI = 00, DB = 1
N5.C1.D0.R1.S06: Rcv En Fine Value = 272
N7.C0.D0.R1.S04: Total Receive Enable Delay = 1225
N1.C0.D0.R1.S07: Total Receive Enable Delay = 1306
N3.C3.D0.R1.S04: RcvEn: plus1 = 1, minus1 = 0, PI = 60, DB = 1
N5.C1.D0.R1.S07: Rcv En Fine Value = 291
N7.C0.D0.R1.S05: Total Receive Enable Delay = 1252
N1.C0.D0.R1.S08: Total Receive Enable Delay = 1221
N3.C3.D0.R1.S05: RcvEn: plus1 = 1, minus1 = 0, PI = 21, DB = 0
N5.C1.D0.R1.S08: Rcv En Fine Value = 339
N7.C0.D0.R1.S06: Total Receive Enable Delay = 1284
N1.C0.D0.R1: Starting preamble search upper nibbles
N3.C3.D0.R1.S06: RcvEn: plus1 = 1, minus1 = 0, PI = 43, DB = 0
N5.C1.D0.R1.S09: Rcv En Fine Value = 301
N7.C0.D0.R1.S07: Total Receive Enable Delay = 1307
N1.C0.D0.R1.S09: PI = 054, PtrOffset = 005
N3.C3.D0.R1.S07: RcvEn: plus1 = 1, minus1 = 0, PI = 04, DB = 1
N5.C1.D0.R1.S10: Rcv En Fine Value = 283
N7.C0.D0.R1.S08: Total Receive Enable Delay = 1221
N1.C0.D0.R1.S10: PI = 033, PtrOffset = 005
N3.C3.D0.R1.S08: RcvEn: plus1 = 1, minus1 = 0, PI = 46, DB = 0
N5.C1.D0.R1.S11: Rcv En Fine Value = 379
N7.C0.D0.R1: Starting preamble search upper nibbles
N1.C0.D0.R1.S11: PI = 003, PtrOffset = 005
N3.C3.D0.R1.S09: RcvEn: plus1 = 1, minus1 = 0, PI = 11, DB = 1
N5.C1.D0.R1.S12: Rcv En Fine Value = 358
N7.C0.D0.R1.S09: PI = 051, PtrOffset = 005
N1.C0.D0.R1.S12: PI = 049, PtrOffset = 004
N3.C3.D0.R1.S10: RcvEn: plus1 = 1, minus1 = 0, PI = 53, DB = 1
N5.C1.D0.R1.S13: Rcv En Fine Value = 353
N7.C0.D0.R1.S10: PI = 033, PtrOffset = 005
N1.C0.D0.R1.S13: PI = 040, PtrOffset = 004
N3.C3.D0.R1.S11: RcvEn: plus1 = 1, minus1 = 0, PI = 22, DB = 0
N5.C1.D0.R1.S14: Rcv En Fine Value = 373
N7.C0.D0.R1.S11: PI = 002, PtrOffset = 005
N1.C0.D0.R1.S14: PI = 002, PtrOffset = 005
N3.C3.D0.R1.S12: RcvEn: plus1 = 1, minus1 = 0, PI = 02, DB = 1
N5.C1.D0.R1.S15: Rcv En Fine Value = 274
N7.C0.D0.R1.S12: PI = 047, PtrOffset = 004
N1.C0.D0.R1.S15: PI = 035, PtrOffset = 005
N3.C3.D0.R1.S13: RcvEn: plus1 = 1, minus1 = 0, PI = 61, DB = 1
N5.C1.D0.R1.S16: Rcv En Fine Value = 292
N7.C0.D0.R1.S13: PI = 042, PtrOffset = 004
N1.C0.D0.R1.S16: PI = 055, PtrOffset = 005
N3.C3.D0.R1.S14: RcvEn: plus1 = 1, minus1 = 0, PI = 22, DB = 0
N5.C1.D0.R1.S17: Rcv En Fine Value = 341
N7.C0.D0.R1.S14: PI = 000, PtrOffset = 005
N1.C0.D0.R1.S17: PI = 036, PtrOffset = 004
N3.C3.D0.R1.S15: RcvEn: plus1 = 1, minus1 = 0, PI = 43, DB = 0
N5.C1.D0.R1: Starting preamble search lower nibbles
N7.C0.D0.R1.S15: PI = 034, PtrOffset = 005
N1.C0.D0.R1.S09: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N3.C3.D0.R1.S16: RcvEn: plus1 = 1, minus1 = 0, PI = 04, DB = 1
N5.C1.D0.R1.S00: PI = 046, PtrOffset = 004
N7.C0.D0.R1.S16: PI = 059, PtrOffset = 005
N1.C0.D0.R1.S10: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N3.C3.D0.R1.S17: RcvEn: plus1 = 1, minus1 = 0, PI = 47, DB = 0
N5.C1.D0.R1.S01: PI = 026, PtrOffset = 004
N7.C0.D0.R1.S17: PI = 036, PtrOffset = 004
N1.C0.D0.R1.S11: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
STOP_DATA_REC_EN
N5.C1.D0.R1.S02: PI = 058, PtrOffset = 005
N7.C0.D0.R1.S09: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N1.C0.D0.R1.S12: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N3.C0.D0.R0.S00: StoreJckWorstRank: worst rank = 0, greatestDelay = 1313
N5.C1.D0.R1.S03: PI = 037, PtrOffset = 005
N7.C0.D0.R1.S10: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N1.C0.D0.R1.S13: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N3.C0.D0.R0.S07: StoreJckWorstRank: worst rank = 0, greatestDelay = 1317
N5.C1.D0.R1.S04: PI = 030, PtrOffset = 005
N7.C0.D0.R1.S11: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N1.C0.D0.R1.S14: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N3.C0.D0.R1.S16: StoreJckWorstRank: worst rank = 1, greatestDelay = 1318
N5.C1.D0.R1.S05: PI = 057, PtrOffset = 005
N7.C0.D0.R1.S12: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N1.C0.D0.R1.S15: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N3.C1.D0.R0.S00: StoreJckWorstRank: worst rank = 0, greatestDelay = 1356
N5.C1.D0.R1.S06: PI = 016, PtrOffset = 004
N7.C0.D0.R1.S13: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N1.C0.D0.R1.S16: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N3.C0: StoreJckWorstRank: final value: worst rank = 0
N5.C1.D0.R1.S07: PI = 035, PtrOffset = 004
N7.C0.D0.R1.S14: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N1.C0.D0.R1.S17: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N3.C2.D0.R0.S00: StoreJckWorstRank: worst rank = 0, greatestDelay = 1306
N5.C1.D0.R1.S08: PI = 019, PtrOffset = 005
N7.C0.D0.R1.S15: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N1.C0.D0.R1.S09: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N3.C2.D0.R0.S09: StoreJckWorstRank: worst rank = 0, greatestDelay = 1308
N5.C1.D0.R1.S00: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N7.C0.D0.R1.S16: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N1.C0.D0.R1.S10: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N3.C2.D0.R1.S09: StoreJckWorstRank: worst rank = 1, greatestDelay = 1309
N5.C1.D0.R1.S01: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N7.C0.D0.R1.S17: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N1.C0.D0.R1.S11: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N3.C3.D0.R0.S00: StoreJckWorstRank: worst rank = 0, greatestDelay = 1353
N5.C1.D0.R1.S02: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N7.C0.D0.R1.S09: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N1.C0.D0.R1.S12: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N3.C3.D0.R0.S09: StoreJckWorstRank: worst rank = 0, greatestDelay = 1356
N5.C1.D0.R1.S03: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N7.C0.D0.R1.S10: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N1.C0.D0.R1.S13: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N3.C1: StoreJckWorstRank: final value: worst rank = 0
N5.C1.D0.R1.S04: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N7.C0.D0.R1.S11: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N1.C0.D0.R1.S14: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N3: RunTrainStep: Final status = 0
N5.C1.D0.R1.S05: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N7.C0.D0.R1.S12: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N1.C0.D0.R1.S15: RcvEnCoarse: Latency = 009, RdPtr Offset = 5

END - Basic Receive Enable Training    Time         25402 ms
N5.C1.D0.R1.S06: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N7.C0.D0.R1.S13: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N1.C0.D0.R1.S16: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N3.C0.S00: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  6
N5.C1.D0.R1.S07: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N7.C0.D0.R1.S14: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N1.C0.D0.R1.S17: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N3.C0.S01: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  6
N5.C1.D0.R1.S08: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N7.C0.D0.R1.S15: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N1.C0.D0.R1.S09: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N3.C0.S02: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  5
N5.C1.D0.R1.S00: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N7.C0.D0.R1.S16: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N1.C0.D0.R1.S10: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N3.C0.S03: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  5
N5.C1.D0.R1.S01: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N7.C0.D0.R1.S17: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N1.C0.D0.R1.S11: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N3.C0.S04: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  5
N5.C1.D0.R1.S02: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N7.C0.D0.R1.S09: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N1.C0.D0.R1.S12: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N3.C0.S05: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  5
N5.C1.D0.R1.S03: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N7.C0.D0.R1.S10: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N1.C0.D0.R1.S13: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N3.C0.S06: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  6
N5.C1.D0.R1.S04: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N7.C0.D0.R1.S11: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N1.C0.D0.R1.S14: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N3.C0.S07: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  6
N5.C1.D0.R1.S05: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N7.C0.D0.R1.S12: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N1.C0.D0.R1.S15: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N3.C0.S08: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  5
N5.C1.D0.R1.S06: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N7.C0.D0.R1.S13: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N1.C0.D0.R1.S16: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N3.C1.S00: SuppressionWindowAdjustmentRd: latency =  9, rdptroffset =  5
N5.C1.D0.R1.S07: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N7.C0.D0.R1.S14: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N1.C0.D0.R1.S17: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N3.C1.S01: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  6
N5.C1.D0.R1.S08: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N7.C0.D0.R1.S15: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N1.C0.D0.R1.S09: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N3.C1.S02: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  6
N5.C1.D0.R1.S00: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N7.C0.D0.R1.S16: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N1.C0.D0.R1.S10: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N3.C1.S03: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  6
N5.C1.D0.R1.S01: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N7.C0.D0.R1.S17: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N1.C0.D0.R1.S11: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N3.C1.S04: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  5
N5.C1.D0.R1.S02: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N7.C0.D0.R1.S09: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N1.C0.D0.R1.S12: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N3.C1.S05: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  6
N5.C1.D0.R1.S03: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N7.C0.D0.R1.S10: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N1.C0.D0.R1.S13: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N3.C1.S06: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  6
N5.C1.D0.R1.S04: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N7.C0.D0.R1.S11: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N1.C0.D0.R1.S14: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N3.C1.S07: SuppressionWindowAdjustmentRd: latency =  9, rdptroffset =  5
N5.C1.D0.R1.S05: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N7.C0.D0.R1.S12: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N1.C0.D0.R1.S15: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N3.C1.S08: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  5
N5.C1.D0.R1.S06: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N7.C0.D0.R1.S13: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N1.C0.D0.R1.S16: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N3.C2.S00: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  6
N5.C1.D0.R1.S07: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N7.C0.D0.R1.S14: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N1.C0.D0.R1.S17: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N3.C2.S01: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  6
N5.C1.D0.R1.S08: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N7.C0.D0.R1.S15: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N1.C0.D0.R1.S09: Preamble found at Latency = 007
N3.C2.S02: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  5
N5.C1.D0.R1.S00: Preamble found at Latency = 008
N7.C0.D0.R1.S16: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N1.C0.D0.R1.S10: Preamble found at Latency = 007
N3.C2.S03: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  5
N5.C1.D0.R1.S01: Preamble found at Latency = 008
N7.C0.D0.R1.S17: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N1.C0.D0.R1.S11: Preamble found at Latency = 007
N3.C2.S04: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  5
N5.C1.D0.R1.S06: Preamble found at Latency = 008
N7.C0.D0.R1.S09: Preamble found at Latency = 007
N1.C0.D0.R1.S12: Preamble found at Latency = 007
N3.C2.S05: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  5
N5.C1.D0.R1.S07: Preamble found at Latency = 008
N7.C0.D0.R1.S10: Preamble found at Latency = 007
N1.C0.D0.R1.S13: Preamble found at Latency = 007
N3.C2.S06: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  6
N5.C1.D0.R1.S00: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N7.C0.D0.R1.S11: Preamble found at Latency = 007
N1.C0.D0.R1.S14: Preamble found at Latency = 007
N3.C2.S07: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  6
N5.C1.D0.R1.S01: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N7.C0.D0.R1.S12: Preamble found at Latency = 007
N1.C0.D0.R1.S15: Preamble found at Latency = 007
N3.C2.S08: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  5
N5.C1.D0.R1.S02: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N7.C0.D0.R1.S13: Preamble found at Latency = 007
N1.C0.D0.R1.S16: Preamble found at Latency = 007
N3.C3.S00: SuppressionWindowAdjustmentRd: latency =  9, rdptroffset =  5
N5.C1.D0.R1.S03: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N7.C0.D0.R1.S14: Preamble found at Latency = 007
N1.C0.D0.R1.S17: Preamble found at Latency = 007
N3.C3.S01: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  6
N5.C1.D0.R1.S04: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N7.C0.D0.R1.S15: Preamble found at Latency = 007
N1.C0.D0.R1: Preamble found for all upper nibbles, adjusting Pi, Offset to center into preamble
N3.C3.S02: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  6
N5.C1.D0.R1.S05: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N7.C0.D0.R1.S16: Preamble found at Latency = 007
N1.C0.D0.R1.S09: Total Receive Enable Delay = 1302
N3.C3.S03: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  6
N5.C1.D0.R1.S06: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N7.C0.D0.R1.S17: Preamble found at Latency = 007
N1.C0.D0.R1.S10: Total Receive Enable Delay = 1281
N3.C3.S04: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  5
N5.C1.D0.R1.S07: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N7.C0.D0.R1: Preamble found for all upper nibbles, adjusting Pi, Offset to center into preamble
N1.C0.D0.R1.S11: Total Receive Enable Delay = 1251
N3.C3.S05: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  6
N5.C1.D0.R1.S08: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N7.C0.D0.R1.S09: Total Receive Enable Delay = 1299
N1.C0.D0.R1.S12: Total Receive Enable Delay = 1233
N3.C3.S06: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  6
N5.C1.D0.R1.S02: Preamble found at Latency = 007
N7.C0.D0.R1.S10: Total Receive Enable Delay = 1281
N1.C0.D0.R1.S13: Total Receive Enable Delay = 1224
N3.C3.S07: SuppressionWindowAdjustmentRd: latency =  9, rdptroffset =  5
N5.C1.D0.R1.S03: Preamble found at Latency = 007
N7.C0.D0.R1.S11: Total Receive Enable Delay = 1250
N1.C0.D0.R1.S14: Total Receive Enable Delay = 1250
N3.C3.S08: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  5
N5.C1.D0.R1.S04: Preamble found at Latency = 007
N7.C0.D0.R1.S12: Total Receive Enable Delay = 1231
N1.C0.D0.R1.S15: Total Receive Enable Delay = 1283

START - Basic Write Level Training
N5.C1.D0.R1.S05: Preamble found at Latency = 007
N7.C0.D0.R1.S13: Total Receive Enable Delay = 1226
N1.C0.D0.R1.S16: Total Receive Enable Delay = 1303
N3: START WRITE LEVEL:
N5.C1.D0.R1.S08: Preamble found at Latency = 007
N7.C0.D0.R1.S14: Total Receive Enable Delay = 1248
N1.C0.D0.R1.S17: Total Receive Enable Delay = 1220
N3.C0.D0.R0: ODT Override: 0x1
N5.C1.D0.R1.S00: Total Receive Enable Delay = 1358
N7.C0.D0.R1.S15: Total Receive Enable Delay = 1282
START_DATA_REC_EN
N3.C0.D0.R0.S00: Write Level Fine Value = 484
N5.C1.D0.R1.S01: Total Receive Enable Delay = 1338
N7.C0.D0.R1.S16: Total Receive Enable Delay = 1307
N1.C0.S00: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N3.C0.D0.R0.S01: Write Level Fine Value = 466
N5.C1.D0.R1.S02: Total Receive Enable Delay = 1306
N7.C0.D0.R1.S17: Total Receive Enable Delay = 1220
N1.C0.S01: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N3.C0.D0.R0.S02: Write Level Fine Value = 455
N5.C1.D0.R1.S03: Total Receive Enable Delay = 1285
START_DATA_REC_EN
N1.C0.S02: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 5
N3.C0.D0.R0.S03: Write Level Fine Value = 440
N5.C1.D0.R1.S04: Total Receive Enable Delay = 1278
N7.C0.S00: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N1.C0.S03: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 5
N3.C0.D0.R0.S04: Write Level Fine Value = 405
N5.C1.D0.R1.S05: Total Receive Enable Delay = 1305
N7.C0.S01: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N1.C0.S04: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 5
N3.C0.D0.R0.S05: Write Level Fine Value = 423
N5.C1.D0.R1.S06: Total Receive Enable Delay = 1328
N7.C0.S02: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 5
N1.C0.S05: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 5
N3.C0.D0.R0.S06: Write Level Fine Value = 426
N5.C1.D0.R1.S07: Total Receive Enable Delay = 1347
N7.C0.S03: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 5
N1.C0.S06: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N3.C0.D0.R0.S07: Write Level Fine Value = 444
N5.C1.D0.R1.S08: Total Receive Enable Delay = 1267
N7.C0.S04: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 5
N1.C0.S07: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N3.C0.D0.R0.S08: Write Level Fine Value = 414
N5.C1.D0.R1: Starting preamble search upper nibbles
N7.C0.S05: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 5
N1.C0.S08: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 5
N3.C0.D0.R0.S09: Write Level Fine Value = 484
N5.C1.D0.R1.S09: PI = 045, PtrOffset = 004
N7.C0.S06: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N1.C0.S09: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N3.C0.D0.R0.S10: Write Level Fine Value = 466
N5.C1.D0.R1.S10: PI = 027, PtrOffset = 004
N7.C0.S07: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N1.C0.S10: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N3.C0.D0.R0.S11: Write Level Fine Value = 455
N5.C1.D0.R1.S11: PI = 059, PtrOffset = 005
N7.C0.S08: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 5
N1.C0.S11: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 5
N3.C0.D0.R0.S12: Write Level Fine Value = 440
N5.C1.D0.R1.S12: PI = 038, PtrOffset = 005
N7.C0.S09: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N1.C0.S12: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 5
N3.C0.D0.R0.S13: Write Level Fine Value = 406
N5.C1.D0.R1.S13: PI = 033, PtrOffset = 005
N7.C0.S10: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N1.C0.S13: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 5
N3.C0.D0.R0.S14: Write Level Fine Value = 422
N5.C1.D0.R1.S14: PI = 053, PtrOffset = 005
N7.C0.S11: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 5
N1.C0.S14: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 5
N3.C0.D0.R0.S15: Write Level Fine Value = 426
N5.C1.D0.R1.S15: PI = 018, PtrOffset = 004
N7.C0.S12: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 5
N1.C0.S15: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N3.C0.D0.R0.S16: Write Level Fine Value = 444
N5.C1.D0.R1.S16: PI = 036, PtrOffset = 004
N7.C0.S13: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 5
N1.C0.S16: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N3.C0.D0.R0.S17: Write Level Fine Value = 414
N5.C1.D0.R1.S17: PI = 021, PtrOffset = 005
N7.C0.S14: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 5
N1.C0.S17: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 5
N3.C0.D0.R1: ODT Override: 0x2
N5.C1.D0.R1.S09: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N7.C0.S15: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N1.C0.D0.R0.S00: RcvEn: plus1 = 1, minus1 = 0, PI = 25, DB = 0
N3.C0.D0.R1.S00: Write Level Fine Value = 485
N5.C1.D0.R1.S10: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N7.C0.S16: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N1.C0.D0.R0.S01: RcvEn: plus1 = 1, minus1 = 0, PI = 03, DB = 1
N3.C0.D0.R1.S01: Write Level Fine Value = 467
N5.C1.D0.R1.S11: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N7.C0.S17: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 5
N1.C0.D0.R0.S02: RcvEn: plus1 = 1, minus1 = 0, PI = 36, DB = 0
N3.C0.D0.R1.S02: Write Level Fine Value = 454
N5.C1.D0.R1.S12: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N7.C0.D0.R0.S00: RcvEn: plus1 = 1, minus1 = 0, PI = 22, DB = 0
N1.C0.D0.R0.S03: RcvEn: plus1 = 1, minus1 = 0, PI = 17, DB = 0
N3.C0.D0.R1.S03: Write Level Fine Value = 439
N5.C1.D0.R1.S13: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N7.C0.D0.R0.S01: RcvEn: plus1 = 1, minus1 = 0, PI = 01, DB = 1
N1.C0.D0.R0.S04: RcvEn: plus1 = 1, minus1 = 0, PI = 10, DB = 1
N3.C0.D0.R1.S04: Write Level Fine Value = 405
N5.C1.D0.R1.S14: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N7.C0.D0.R0.S02: RcvEn: plus1 = 1, minus1 = 0, PI = 36, DB = 0
N1.C0.D0.R0.S05: RcvEn: plus1 = 1, minus1 = 0, PI = 33, DB = 0
N3.C0.D0.R1.S05: Write Level Fine Value = 422
N5.C1.D0.R1.S15: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N7.C0.D0.R0.S03: RcvEn: plus1 = 1, minus1 = 0, PI = 16, DB = 0
N1.C0.D0.R0.S06: RcvEn: plus1 = 1, minus1 = 0, PI = 02, DB = 1
N3.C0.D0.R1.S06: Write Level Fine Value = 425
N5.C1.D0.R1.S16: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N7.C0.D0.R0.S04: RcvEn: plus1 = 1, minus1 = 0, PI = 10, DB = 1
N1.C0.D0.R0.S07: RcvEn: plus1 = 1, minus1 = 0, PI = 26, DB = 0
N3.C0.D0.R1.S07: Write Level Fine Value = 444
N5.C1.D0.R1.S17: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N7.C0.D0.R0.S05: RcvEn: plus1 = 1, minus1 = 0, PI = 35, DB = 0
N1.C0.D0.R0.S08: RcvEn: plus1 = 1, minus1 = 0, PI = 05, DB = 1
N3.C0.D0.R1.S08: Write Level Fine Value = 411
N5.C1.D0.R1.S09: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N7.C0.D0.R0.S06: RcvEn: plus1 = 1, minus1 = 0, PI = 04, DB = 1
N1.C0.D0.R0.S09: RcvEn: plus1 = 1, minus1 = 0, PI = 21, DB = 0
N3.C0.D0.R1.S09: Write Level Fine Value = 483
N5.C1.D0.R1.S10: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N7.C0.D0.R0.S07: RcvEn: plus1 = 1, minus1 = 0, PI = 27, DB = 0
N1.C0.D0.R0.S10: RcvEn: plus1 = 1, minus1 = 0, PI = 01, DB = 1
N3.C0.D0.R1.S10: Write Level Fine Value = 467
N5.C1.D0.R1.S11: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N7.C0.D0.R0.S08: RcvEn: plus1 = 1, minus1 = 0, PI = 06, DB = 1
N1.C0.D0.R0.S11: RcvEn: plus1 = 1, minus1 = 0, PI = 35, DB = 0
N3.C0.D0.R1.S11: Write Level Fine Value = 456
N5.C1.D0.R1.S12: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N7.C0.D0.R0.S09: RcvEn: plus1 = 1, minus1 = 0, PI = 19, DB = 0
N1.C0.D0.R0.S12: RcvEn: plus1 = 1, minus1 = 0, PI = 16, DB = 0
N3.C0.D0.R1.S12: Write Level Fine Value = 439
N5.C1.D0.R1.S13: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N7.C0.D0.R0.S10: RcvEn: plus1 = 1, minus1 = 0, PI = 01, DB = 1
N1.C0.D0.R0.S13: RcvEn: plus1 = 1, minus1 = 0, PI = 08, DB = 1
N3.C0.D0.R1.S13: Write Level Fine Value = 405
N5.C1.D0.R1.S14: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N7.C0.D0.R0.S11: RcvEn: plus1 = 1, minus1 = 0, PI = 34, DB = 0
N1.C0.D0.R0.S14: RcvEn: plus1 = 1, minus1 = 0, PI = 33, DB = 0
N3.C0.D0.R1.S14: Write Level Fine Value = 421
N5.C1.D0.R1.S15: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N7.C0.D0.R0.S12: RcvEn: plus1 = 1, minus1 = 0, PI = 15, DB = 1
N1.C0.D0.R0.S15: RcvEn: plus1 = 1, minus1 = 0, PI = 02, DB = 1
N3.C0.D0.R1.S15: Write Level Fine Value = 426
N5.C1.D0.R1.S16: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N7.C0.D0.R0.S13: RcvEn: plus1 = 1, minus1 = 0, PI = 09, DB = 1
N1.C0.D0.R0.S16: RcvEn: plus1 = 1, minus1 = 0, PI = 24, DB = 0
N3.C0.D0.R1.S16: Write Level Fine Value = 444
N5.C1.D0.R1.S17: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N7.C0.D0.R0.S14: RcvEn: plus1 = 1, minus1 = 0, PI = 32, DB = 0
N1.C0.D0.R0.S17: RcvEn: plus1 = 1, minus1 = 0, PI = 03, DB = 1
N3.C0.D0.R1.S17: Write Level Fine Value = 413
N5.C1.D0.R1.S09: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N7.C0.D0.R0.S15: RcvEn: plus1 = 1, minus1 = 0, PI = 02, DB = 1
N1.C0.D0.R1.S00: RcvEn: plus1 = 1, minus1 = 0, PI = 25, DB = 0
N3.C1.D0.R0: ODT Override: 0x1
N5.C1.D0.R1.S10: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N7.C0.D0.R0.S16: RcvEn: plus1 = 1, minus1 = 0, PI = 27, DB = 0
N1.C0.D0.R1.S01: RcvEn: plus1 = 1, minus1 = 0, PI = 03, DB = 1
N3.C1.D0.R0.S00: Write Level Fine Value = 484
N5.C1.D0.R1.S11: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N7.C0.D0.R0.S17: RcvEn: plus1 = 1, minus1 = 0, PI = 04, DB = 1
N1.C0.D0.R1.S02: RcvEn: plus1 = 1, minus1 = 0, PI = 36, DB = 0
N3.C1.D0.R0.S01: Write Level Fine Value = 468
N5.C1.D0.R1.S12: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N7.C0.D0.R1.S00: RcvEn: plus1 = 1, minus1 = 0, PI = 22, DB = 0
N1.C0.D0.R1.S03: RcvEn: plus1 = 1, minus1 = 0, PI = 17, DB = 0
N3.C1.D0.R0.S02: Write Level Fine Value = 461
N5.C1.D0.R1.S13: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N7.C0.D0.R1.S01: RcvEn: plus1 = 1, minus1 = 0, PI = 01, DB = 1
N1.C0.D0.R1.S04: RcvEn: plus1 = 1, minus1 = 0, PI = 10, DB = 1
N3.C1.D0.R0.S03: Write Level Fine Value = 442
N5.C1.D0.R1.S14: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N7.C0.D0.R1.S02: RcvEn: plus1 = 1, minus1 = 0, PI = 36, DB = 0
N1.C0.D0.R1.S05: RcvEn: plus1 = 1, minus1 = 0, PI = 33, DB = 0
N3.C1.D0.R0.S04: Write Level Fine Value = 410
N5.C1.D0.R1.S15: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N7.C0.D0.R1.S03: RcvEn: plus1 = 1, minus1 = 0, PI = 16, DB = 0
N1.C0.D0.R1.S06: RcvEn: plus1 = 1, minus1 = 0, PI = 02, DB = 1
N3.C1.D0.R0.S05: Write Level Fine Value = 424
N5.C1.D0.R1.S16: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N7.C0.D0.R1.S04: RcvEn: plus1 = 1, minus1 = 0, PI = 10, DB = 1
N1.C0.D0.R1.S07: RcvEn: plus1 = 1, minus1 = 0, PI = 26, DB = 0
N3.C1.D0.R0.S06: Write Level Fine Value = 436
N5.C1.D0.R1.S17: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N7.C0.D0.R1.S05: RcvEn: plus1 = 1, minus1 = 0, PI = 35, DB = 0
N1.C0.D0.R1.S08: RcvEn: plus1 = 1, minus1 = 0, PI = 05, DB = 1
N3.C1.D0.R0.S07: Write Level Fine Value = 456
N5.C1.D0.R1.S09: Preamble found at Latency = 008
N7.C0.D0.R1.S06: RcvEn: plus1 = 1, minus1 = 0, PI = 04, DB = 1
N1.C0.D0.R1.S09: RcvEn: plus1 = 1, minus1 = 0, PI = 21, DB = 0
N3.C1.D0.R0.S08: Write Level Fine Value = 422
N5.C1.D0.R1.S10: Preamble found at Latency = 008
N7.C0.D0.R1.S07: RcvEn: plus1 = 1, minus1 = 0, PI = 27, DB = 0
N1.C0.D0.R1.S10: RcvEn: plus1 = 1, minus1 = 0, PI = 01, DB = 1
N3.C1.D0.R0.S09: Write Level Fine Value = 483
N5.C1.D0.R1.S15: Preamble found at Latency = 008
N7.C0.D0.R1.S08: RcvEn: plus1 = 1, minus1 = 0, PI = 06, DB = 1
N1.C0.D0.R1.S11: RcvEn: plus1 = 1, minus1 = 0, PI = 35, DB = 0
N3.C1.D0.R0.S10: Write Level Fine Value = 469
N5.C1.D0.R1.S16: Preamble found at Latency = 008
N7.C0.D0.R1.S09: RcvEn: plus1 = 1, minus1 = 0, PI = 19, DB = 0
N1.C0.D0.R1.S12: RcvEn: plus1 = 1, minus1 = 0, PI = 16, DB = 0
N3.C1.D0.R0.S11: Write Level Fine Value = 461
N5.C1.D0.R1.S09: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N7.C0.D0.R1.S10: RcvEn: plus1 = 1, minus1 = 0, PI = 01, DB = 1
N1.C0.D0.R1.S13: RcvEn: plus1 = 1, minus1 = 0, PI = 08, DB = 1
N3.C1.D0.R0.S12: Write Level Fine Value = 442
N5.C1.D0.R1.S10: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N7.C0.D0.R1.S11: RcvEn: plus1 = 1, minus1 = 0, PI = 34, DB = 0
N1.C0.D0.R1.S14: RcvEn: plus1 = 1, minus1 = 0, PI = 33, DB = 0
N3.C1.D0.R0.S13: Write Level Fine Value = 410
N5.C1.D0.R1.S11: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N7.C0.D0.R1.S12: RcvEn: plus1 = 1, minus1 = 0, PI = 15, DB = 1
N1.C0.D0.R1.S15: RcvEn: plus1 = 1, minus1 = 0, PI = 02, DB = 1
N3.C1.D0.R0.S14: Write Level Fine Value = 422
N5.C1.D0.R1.S12: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N7.C0.D0.R1.S13: RcvEn: plus1 = 1, minus1 = 0, PI = 09, DB = 1
N1.C0.D0.R1.S16: RcvEn: plus1 = 1, minus1 = 0, PI = 24, DB = 0
N3.C1.D0.R0.S15: Write Level Fine Value = 435
N5.C1.D0.R1.S13: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N7.C0.D0.R1.S14: RcvEn: plus1 = 1, minus1 = 0, PI = 32, DB = 0
N1.C0.D0.R1.S17: RcvEn: plus1 = 1, minus1 = 0, PI = 03, DB = 1
N3.C1.D0.R0.S16: Write Level Fine Value = 455
N5.C1.D0.R1.S14: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N7.C0.D0.R1.S15: RcvEn: plus1 = 1, minus1 = 0, PI = 02, DB = 1
STOP_DATA_REC_EN
N3.C1.D0.R0.S17: Write Level Fine Value = 420
N5.C1.D0.R1.S15: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N7.C0.D0.R1.S16: RcvEn: plus1 = 1, minus1 = 0, PI = 27, DB = 0
N1.C1.D0.R0: RcvEnFine: Initial RdCmd2RcvEnLatency = 10, Initial RdPtrOffsetRcvEn = 4
N3.C1.D0.R1: ODT Override: 0x2
N5.C1.D0.R1.S16: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N7.C0.D0.R1.S17: RcvEn: plus1 = 1, minus1 = 0, PI = 04, DB = 1
N1.C1.D0.R0.S00: Rcv En Fine Value = 299
N3.C1.D0.R1.S00: Write Level Fine Value = 483
N5.C1.D0.R1.S17: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
STOP_DATA_REC_EN
N1.C1.D0.R0.S01: Rcv En Fine Value = 280
N3.C1.D0.R1.S01: Write Level Fine Value = 467
N5.C1.D0.R1.S11: Preamble found at Latency = 007
N7.C1.D0.R0: RcvEnFine: Initial RdCmd2RcvEnLatency = 10, Initial RdPtrOffsetRcvEn = 4
N1.C1.D0.R0.S02: Rcv En Fine Value = 374
N3.C1.D0.R1.S02: Write Level Fine Value = 460
N5.C1.D0.R1.S12: Preamble found at Latency = 007
N7.C1.D0.R0.S00: Rcv En Fine Value = 307
N1.C1.D0.R0.S03: Rcv En Fine Value = 359
N3.C1.D0.R1.S03: Write Level Fine Value = 440
N5.C1.D0.R1.S13: Preamble found at Latency = 007
N7.C1.D0.R0.S01: Rcv En Fine Value = 287
N1.C1.D0.R0.S04: Rcv En Fine Value = 349
N3.C1.D0.R1.S04: Write Level Fine Value = 411
N5.C1.D0.R1.S14: Preamble found at Latency = 007
N7.C1.D0.R0.S02: Rcv En Fine Value = 257
N1.C1.D0.R0.S05: Rcv En Fine Value = 375
N3.C1.D0.R1.S05: Write Level Fine Value = 424
N5.C1.D0.R1.S17: Preamble found at Latency = 007
N7.C1.D0.R0.S03: Rcv En Fine Value = 363
N1.C1.D0.R0.S06: Rcv En Fine Value = 270
N3.C1.D0.R1.S06: Write Level Fine Value = 436
N5.C1.D0.R1: Preamble found for all upper nibbles, adjusting Pi, Offset to center into preamble
N7.C1.D0.R0.S04: Rcv En Fine Value = 358
N1.C1.D0.R0.S07: Rcv En Fine Value = 292
N3.C1.D0.R1.S07: Write Level Fine Value = 454
N5.C1.D0.R1.S09: Total Receive Enable Delay = 1357
N7.C1.D0.R0.S05: Rcv En Fine Value = 379
N1.C1.D0.R0.S08: Rcv En Fine Value = 334
N3.C1.D0.R1.S08: Write Level Fine Value = 420
N5.C1.D0.R1.S10: Total Receive Enable Delay = 1339
N7.C1.D0.R0.S06: Rcv En Fine Value = 277
N1.C1.D0.R0.S09: Rcv En Fine Value = 299
N3.C1.D0.R1.S09: Write Level Fine Value = 482
N5.C1.D0.R1.S11: Total Receive Enable Delay = 1307
N7.C1.D0.R0.S07: Rcv En Fine Value = 298
N1.C1.D0.R0.S10: Rcv En Fine Value = 278
N3.C1.D0.R1.S10: Write Level Fine Value = 469
N5.C1.D0.R1.S12: Total Receive Enable Delay = 1286
N7.C1.D0.R0.S08: Rcv En Fine Value = 344
N1.C1.D0.R0.S11: Rcv En Fine Value = 377
N3.C1.D0.R1.S11: Write Level Fine Value = 460
N5.C1.D0.R1.S13: Total Receive Enable Delay = 1281
N7.C1.D0.R0.S09: Rcv En Fine Value = 308
N1.C1.D0.R0.S12: Rcv En Fine Value = 359
N3.C1.D0.R1.S12: Write Level Fine Value = 442
N5.C1.D0.R1.S14: Total Receive Enable Delay = 1301
N7.C1.D0.R0.S10: Rcv En Fine Value = 287
N1.C1.D0.R0.S13: Rcv En Fine Value = 352
N3.C1.D0.R1.S13: Write Level Fine Value = 409
N5.C1.D0.R1.S15: Total Receive Enable Delay = 1330
N7.C1.D0.R0.S11: Rcv En Fine Value = 257
N1.C1.D0.R0.S14: Rcv En Fine Value = 374
N3.C1.D0.R1.S14: Write Level Fine Value = 423
N5.C1.D0.R1.S16: Total Receive Enable Delay = 1348
N7.C1.D0.R0.S12: Rcv En Fine Value = 363
N1.C1.D0.R0.S15: Rcv En Fine Value = 269
N3.C1.D0.R1.S15: Write Level Fine Value = 436
N5.C1.D0.R1.S17: Total Receive Enable Delay = 1269
N7.C1.D0.R0.S13: Rcv En Fine Value = 355
N1.C1.D0.R0.S16: Rcv En Fine Value = 294
N3.C1.D0.R1.S16: Write Level Fine Value = 454
START_DATA_REC_EN
N7.C1.D0.R0.S14: Rcv En Fine Value = 381
N1.C1.D0.R0.S17: Rcv En Fine Value = 338
N3.C1.D0.R1.S17: Write Level Fine Value = 421
N5.C1.S00: RdCmd2RcvEnLatency = 9, RdPtrOffsetRcvEn = 5
N7.C1.D0.R0.S15: Rcv En Fine Value = 277
N1.C1.D0.R0: Starting preamble search lower nibbles
N3.C2.D0.R0: ODT Override: 0x1
N5.C1.S01: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N7.C1.D0.R0.S16: Rcv En Fine Value = 298
N1.C1.D0.R0.S00: PI = 043, PtrOffset = 004
N3.C2.D0.R0.S00: Write Level Fine Value = 477
N5.C1.S02: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N7.C1.D0.R0.S17: Rcv En Fine Value = 345
N1.C1.D0.R0.S01: PI = 024, PtrOffset = 004
N3.C2.D0.R0.S01: Write Level Fine Value = 460
N5.C1.S03: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N7.C1.D0.R0: Starting preamble search lower nibbles
N1.C1.D0.R0.S02: PI = 054, PtrOffset = 005
N3.C2.D0.R0.S02: Write Level Fine Value = 449
N5.C1.S04: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 5
N7.C1.D0.R0.S00: PI = 051, PtrOffset = 004
N1.C1.D0.R0.S03: PI = 039, PtrOffset = 005
N3.C2.D0.R0.S03: Write Level Fine Value = 431
N5.C1.S05: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N7.C1.D0.R0.S01: PI = 031, PtrOffset = 004
N1.C1.D0.R0.S04: PI = 029, PtrOffset = 005
N3.C2.D0.R0.S04: Write Level Fine Value = 393
N5.C1.S06: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N7.C1.D0.R0.S02: PI = 001, PtrOffset = 004
N1.C1.D0.R0.S05: PI = 055, PtrOffset = 005
N3.C2.D0.R0.S05: Write Level Fine Value = 421
N5.C1.S07: RdCmd2RcvEnLatency = 9, RdPtrOffsetRcvEn = 5
N7.C1.D0.R0.S03: PI = 043, PtrOffset = 005
N1.C1.D0.R0.S06: PI = 014, PtrOffset = 004
N3.C2.D0.R0.S06: Write Level Fine Value = 422
N5.C1.S08: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 5
N7.C1.D0.R0.S04: PI = 038, PtrOffset = 005
N1.C1.D0.R0.S07: PI = 036, PtrOffset = 004
N3.C2.D0.R0.S07: Write Level Fine Value = 442
N5.C1.S09: RdCmd2RcvEnLatency = 9, RdPtrOffsetRcvEn = 5
N7.C1.D0.R0.S05: PI = 059, PtrOffset = 005
N1.C1.D0.R0.S08: PI = 014, PtrOffset = 005
N3.C2.D0.R0.S08: Write Level Fine Value = 408
N5.C1.S10: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N7.C1.D0.R0.S06: PI = 021, PtrOffset = 004
N1.C1.D0.R0.S00: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N3.C2.D0.R0.S09: Write Level Fine Value = 474
N5.C1.S11: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N7.C1.D0.R0.S07: PI = 042, PtrOffset = 004
N1.C1.D0.R0.S01: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N3.C2.D0.R0.S10: Write Level Fine Value = 462
N5.C1.S12: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N7.C1.D0.R0.S08: PI = 024, PtrOffset = 005
N1.C1.D0.R0.S02: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N3.C2.D0.R0.S11: Write Level Fine Value = 453
N5.C1.S13: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 5
N7.C1.D0.R0.S00: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N1.C1.D0.R0.S03: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N3.C2.D0.R0.S12: Write Level Fine Value = 433
N5.C1.S14: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N7.C1.D0.R0.S01: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N1.C1.D0.R0.S04: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N3.C2.D0.R0.S13: Write Level Fine Value = 392
N5.C1.S15: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N7.C1.D0.R0.S02: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N1.C1.D0.R0.S05: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N3.C2.D0.R0.S14: Write Level Fine Value = 421
N5.C1.S16: RdCmd2RcvEnLatency = 9, RdPtrOffsetRcvEn = 5
N7.C1.D0.R0.S03: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N1.C1.D0.R0.S06: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N3.C2.D0.R0.S15: Write Level Fine Value = 422
N5.C1.S17: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 5
N7.C1.D0.R0.S04: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N1.C1.D0.R0.S07: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N3.C2.D0.R0.S16: Write Level Fine Value = 444
N5.C1.D0.R0.S00: RcvEn: plus1 = 1, minus1 = 0, PI = 14, DB = 1
N7.C1.D0.R0.S05: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N1.C1.D0.R0.S08: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N3.C2.D0.R0.S17: Write Level Fine Value = 408
N5.C1.D0.R0.S01: RcvEn: plus1 = 1, minus1 = 0, PI = 59, DB = 1
N7.C1.D0.R0.S06: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N1.C1.D0.R0.S00: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N3.C2.D0.R1: ODT Override: 0x2
N5.C1.D0.R0.S02: RcvEn: plus1 = 1, minus1 = 0, PI = 26, DB = 0
N7.C1.D0.R0.S07: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N1.C1.D0.R0.S01: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N3.C2.D0.R1.S00: Write Level Fine Value = 477
N5.C1.D0.R0.S03: RcvEn: plus1 = 1, minus1 = 0, PI = 06, DB = 1
N7.C1.D0.R0.S08: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N1.C1.D0.R0.S02: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N3.C2.D0.R1.S01: Write Level Fine Value = 458
N5.C1.D0.R0.S04: RcvEn: plus1 = 1, minus1 = 0, PI = 63, DB = 1
N7.C1.D0.R0.S00: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N1.C1.D0.R0.S03: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N3.C2.D0.R1.S02: Write Level Fine Value = 449
N5.C1.D0.R0.S05: RcvEn: plus1 = 1, minus1 = 0, PI = 25, DB = 0
N7.C1.D0.R0.S01: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N1.C1.D0.R0.S04: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N3.C2.D0.R1.S03: Write Level Fine Value = 432
N5.C1.D0.R0.S06: RcvEn: plus1 = 1, minus1 = 0, PI = 51, DB = 1
N7.C1.D0.R0.S02: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N1.C1.D0.R0.S05: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N3.C2.D0.R1.S04: Write Level Fine Value = 391
N5.C1.D0.R0.S07: RcvEn: plus1 = 1, minus1 = 0, PI = 05, DB = 1
N7.C1.D0.R0.S03: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N1.C1.D0.R0.S06: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N3.C2.D0.R1.S05: Write Level Fine Value = 423
N5.C1.D0.R0.S08: RcvEn: plus1 = 1, minus1 = 0, PI = 49, DB = 1
N7.C1.D0.R0.S04: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N1.C1.D0.R0.S07: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N3.C2.D0.R1.S06: Write Level Fine Value = 423
N5.C1.D0.R0.S09: RcvEn: plus1 = 1, minus1 = 0, PI = 11, DB = 1
N7.C1.D0.R0.S05: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N1.C1.D0.R0.S08: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N3.C2.D0.R1.S07: Write Level Fine Value = 442
N5.C1.D0.R0.S10: RcvEn: plus1 = 1, minus1 = 0, PI = 58, DB = 1
N7.C1.D0.R0.S06: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N1.C1.D0.R0.S00: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N3.C2.D0.R1.S08: Write Level Fine Value = 408
N5.C1.D0.R0.S11: RcvEn: plus1 = 1, minus1 = 0, PI = 27, DB = 0
N7.C1.D0.R0.S07: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N1.C1.D0.R0.S01: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N3.C2.D0.R1.S09: Write Level Fine Value = 474
N5.C1.D0.R0.S12: RcvEn: plus1 = 1, minus1 = 0, PI = 05, DB = 1
N7.C1.D0.R0.S08: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N1.C1.D0.R0.S02: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N3.C2.D0.R1.S10: Write Level Fine Value = 462
N5.C1.D0.R0.S13: RcvEn: plus1 = 1, minus1 = 0, PI = 63, DB = 1
N7.C1.D0.R0.S00: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N1.C1.D0.R0.S03: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N3.C2.D0.R1.S11: Write Level Fine Value = 450
N5.C1.D0.R0.S14: RcvEn: plus1 = 1, minus1 = 0, PI = 23, DB = 0
N7.C1.D0.R0.S01: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N1.C1.D0.R0.S04: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N3.C2.D0.R1.S12: Write Level Fine Value = 433
N5.C1.D0.R0.S15: RcvEn: plus1 = 1, minus1 = 0, PI = 49, DB = 1
N7.C1.D0.R0.S02: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N1.C1.D0.R0.S05: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N3.C2.D0.R1.S13: Write Level Fine Value = 392
N5.C1.D0.R0.S16: RcvEn: plus1 = 1, minus1 = 0, PI = 05, DB = 1
N7.C1.D0.R0.S03: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N1.C1.D0.R0.S06: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N3.C2.D0.R1.S14: Write Level Fine Value = 420
N5.C1.D0.R0.S17: RcvEn: plus1 = 1, minus1 = 0, PI = 53, DB = 1
N7.C1.D0.R0.S04: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N1.C1.D0.R0.S07: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N3.C2.D0.R1.S15: Write Level Fine Value = 423
N5.C1.D0.R1.S00: RcvEn: plus1 = 1, minus1 = 0, PI = 14, DB = 1
N7.C1.D0.R0.S05: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N1.C1.D0.R0.S08: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N3.C2.D0.R1.S16: Write Level Fine Value = 446
N5.C1.D0.R1.S01: RcvEn: plus1 = 1, minus1 = 0, PI = 59, DB = 1
N7.C1.D0.R0.S06: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N1.C1.D0.R0.S00: Preamble found at Latency = 008
N3.C2.D0.R1.S17: Write Level Fine Value = 408
N5.C1.D0.R1.S02: RcvEn: plus1 = 1, minus1 = 0, PI = 26, DB = 0
N7.C1.D0.R0.S07: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N1.C1.D0.R0.S01: Preamble found at Latency = 008
N3.C3.D0.R0: ODT Override: 0x1
N5.C1.D0.R1.S03: RcvEn: plus1 = 1, minus1 = 0, PI = 06, DB = 1
N7.C1.D0.R0.S08: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N1.C1.D0.R0.S06: Preamble found at Latency = 008
N3.C3.D0.R0.S00: Write Level Fine Value = 487
N5.C1.D0.R1.S04: RcvEn: plus1 = 1, minus1 = 0, PI = 63, DB = 1
N7.C1.D0.R0.S00: Preamble found at Latency = 008
N1.C1.D0.R0.S07: Preamble found at Latency = 008
N3.C3.D0.R0.S01: Write Level Fine Value = 468
N5.C1.D0.R1.S05: RcvEn: plus1 = 1, minus1 = 0, PI = 25, DB = 0
N7.C1.D0.R0.S01: Preamble found at Latency = 008
N1.C1.D0.R0.S00: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N3.C3.D0.R0.S02: Write Level Fine Value = 459
N5.C1.D0.R1.S06: RcvEn: plus1 = 1, minus1 = 0, PI = 51, DB = 1
N7.C1.D0.R0.S02: Preamble found at Latency = 008
N1.C1.D0.R0.S01: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N3.C3.D0.R0.S03: Write Level Fine Value = 443
N5.C1.D0.R1.S07: RcvEn: plus1 = 1, minus1 = 0, PI = 05, DB = 1
N7.C1.D0.R0.S06: Preamble found at Latency = 008
N1.C1.D0.R0.S02: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N3.C3.D0.R0.S04: Write Level Fine Value = 408
N5.C1.D0.R1.S08: RcvEn: plus1 = 1, minus1 = 0, PI = 49, DB = 1
N7.C1.D0.R0.S07: Preamble found at Latency = 008
N1.C1.D0.R0.S03: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N3.C3.D0.R0.S05: Write Level Fine Value = 421
N5.C1.D0.R1.S09: RcvEn: plus1 = 1, minus1 = 0, PI = 11, DB = 1
N7.C1.D0.R0.S00: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N1.C1.D0.R0.S04: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N3.C3.D0.R0.S06: Write Level Fine Value = 436
N5.C1.D0.R1.S10: RcvEn: plus1 = 1, minus1 = 0, PI = 58, DB = 1
N7.C1.D0.R0.S01: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N1.C1.D0.R0.S05: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N3.C3.D0.R0.S07: Write Level Fine Value = 454
N5.C1.D0.R1.S11: RcvEn: plus1 = 1, minus1 = 0, PI = 27, DB = 0
N7.C1.D0.R0.S02: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N1.C1.D0.R0.S06: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N3.C3.D0.R0.S08: Write Level Fine Value = 421
N5.C1.D0.R1.S12: RcvEn: plus1 = 1, minus1 = 0, PI = 05, DB = 1
N7.C1.D0.R0.S03: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N1.C1.D0.R0.S07: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N3.C3.D0.R0.S09: Write Level Fine Value = 485
N5.C1.D0.R1.S13: RcvEn: plus1 = 1, minus1 = 0, PI = 63, DB = 1
N7.C1.D0.R0.S04: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N1.C1.D0.R0.S08: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N3.C3.D0.R0.S10: Write Level Fine Value = 470
N5.C1.D0.R1.S14: RcvEn: plus1 = 1, minus1 = 0, PI = 23, DB = 0
N7.C1.D0.R0.S05: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N1.C1.D0.R0.S02: Preamble found at Latency = 007
N3.C3.D0.R0.S11: Write Level Fine Value = 459
N5.C1.D0.R1.S15: RcvEn: plus1 = 1, minus1 = 0, PI = 49, DB = 1
N7.C1.D0.R0.S06: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N1.C1.D0.R0.S03: Preamble found at Latency = 007
N3.C3.D0.R0.S12: Write Level Fine Value = 443
N5.C1.D0.R1.S16: RcvEn: plus1 = 1, minus1 = 0, PI = 05, DB = 1
N7.C1.D0.R0.S07: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N1.C1.D0.R0.S04: Preamble found at Latency = 007
N3.C3.D0.R0.S13: Write Level Fine Value = 408
N5.C1.D0.R1.S17: RcvEn: plus1 = 1, minus1 = 0, PI = 53, DB = 1
N7.C1.D0.R0.S08: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N1.C1.D0.R0.S05: Preamble found at Latency = 007
N3.C3.D0.R0.S14: Write Level Fine Value = 419
STOP_DATA_REC_EN
N7.C1.D0.R0.S03: Preamble found at Latency = 007
N1.C1.D0.R0.S08: Preamble found at Latency = 007
N3.C3.D0.R0.S15: Write Level Fine Value = 436
N5.C2.D0.R0: RcvEnFine: Initial RdCmd2RcvEnLatency = 10, Initial RdPtrOffsetRcvEn = 4
N7.C1.D0.R0.S04: Preamble found at Latency = 007
N1.C1.D0.R0.S00: Total Receive Enable Delay = 1355
N3.C3.D0.R0.S16: Write Level Fine Value = 454
N5.C2.D0.R0.S00: Rcv En Fine Value = 261
N7.C1.D0.R0.S05: Preamble found at Latency = 007
N1.C1.D0.R0.S01: Total Receive Enable Delay = 1336
N3.C3.D0.R0.S17: Write Level Fine Value = 421
N5.C2.D0.R0.S01: Rcv En Fine Value = 367
N7.C1.D0.R0.S08: Preamble found at Latency = 007
N1.C1.D0.R0.S02: Total Receive Enable Delay = 1302
N3.C3.D0.R1: ODT Override: 0x2
N5.C2.D0.R0.S02: Rcv En Fine Value = 335
N7.C1.D0.R0.S00: Total Receive Enable Delay = 1363
N1.C1.D0.R0.S03: Total Receive Enable Delay = 1287
N3.C3.D0.R1.S00: Write Level Fine Value = 488
N5.C2.D0.R0.S03: Rcv En Fine Value = 314
N7.C1.D0.R0.S01: Total Receive Enable Delay = 1343
N1.C1.D0.R0.S04: Total Receive Enable Delay = 1277
N3.C3.D0.R1.S01: Write Level Fine Value = 468
N5.C2.D0.R0.S04: Rcv En Fine Value = 311
N7.C1.D0.R0.S02: Total Receive Enable Delay = 1313
N1.C1.D0.R0.S05: Total Receive Enable Delay = 1303
N3.C3.D0.R1.S02: Write Level Fine Value = 458
N5.C2.D0.R0.S05: Rcv En Fine Value = 325
N7.C1.D0.R0.S03: Total Receive Enable Delay = 1291
N1.C1.D0.R0.S06: Total Receive Enable Delay = 1326
N3.C3.D0.R1.S03: Write Level Fine Value = 441
N5.C2.D0.R0.S06: Rcv En Fine Value = 365
N7.C1.D0.R0.S04: Total Receive Enable Delay = 1286
N1.C1.D0.R0.S07: Total Receive Enable Delay = 1348
N3.C3.D0.R1.S04: Write Level Fine Value = 407
N5.C2.D0.R0.S07: Rcv En Fine Value = 382
N7.C1.D0.R0.S05: Total Receive Enable Delay = 1307
N1.C1.D0.R0.S08: Total Receive Enable Delay = 1262
N3.C3.D0.R1.S05: Write Level Fine Value = 421
N5.C2.D0.R0.S08: Rcv En Fine Value = 303
N7.C1.D0.R0.S06: Total Receive Enable Delay = 1333
N1.C1.D0.R0: Starting preamble search upper nibbles
N3.C3.D0.R1.S06: Write Level Fine Value = 435
N5.C2.D0.R0.S09: Rcv En Fine Value = 262
N7.C1.D0.R0.S07: Total Receive Enable Delay = 1354
N1.C1.D0.R0.S09: PI = 043, PtrOffset = 004
N3.C3.D0.R1.S07: Write Level Fine Value = 455
N5.C2.D0.R0.S10: Rcv En Fine Value = 364
N7.C1.D0.R0.S08: Total Receive Enable Delay = 1272
N1.C1.D0.R0.S10: PI = 022, PtrOffset = 004
N3.C3.D0.R1.S08: Write Level Fine Value = 422
N5.C2.D0.R0.S11: Rcv En Fine Value = 333
N7.C1.D0.R0: Starting preamble search upper nibbles
N1.C1.D0.R0.S11: PI = 057, PtrOffset = 005
N3.C3.D0.R1.S09: Write Level Fine Value = 484
N5.C2.D0.R0.S12: Rcv En Fine Value = 314
N7.C1.D0.R0.S09: PI = 052, PtrOffset = 004
N1.C1.D0.R0.S12: PI = 039, PtrOffset = 005
N3.C3.D0.R1.S10: Write Level Fine Value = 470
N5.C2.D0.R0.S13: Rcv En Fine Value = 313
N7.C1.D0.R0.S10: PI = 031, PtrOffset = 004
N1.C1.D0.R0.S13: PI = 032, PtrOffset = 005
N3.C3.D0.R1.S11: Write Level Fine Value = 458
N5.C2.D0.R0.S14: Rcv En Fine Value = 326
N7.C1.D0.R0.S11: PI = 001, PtrOffset = 004
N1.C1.D0.R0.S14: PI = 054, PtrOffset = 005
N3.C3.D0.R1.S12: Write Level Fine Value = 441
N5.C2.D0.R0.S15: Rcv En Fine Value = 363
N7.C1.D0.R0.S12: PI = 043, PtrOffset = 005
N1.C1.D0.R0.S15: PI = 013, PtrOffset = 004
N3.C3.D0.R1.S13: Write Level Fine Value = 407
N5.C2.D0.R0.S16: Rcv En Fine Value = 381
N7.C1.D0.R0.S13: PI = 035, PtrOffset = 005
N1.C1.D0.R0.S16: PI = 038, PtrOffset = 004
N3.C3.D0.R1.S14: Write Level Fine Value = 421
N5.C2.D0.R0.S17: Rcv En Fine Value = 298
N7.C1.D0.R0.S14: PI = 061, PtrOffset = 005
N1.C1.D0.R0.S17: PI = 018, PtrOffset = 005
N3.C3.D0.R1.S15: Write Level Fine Value = 437
N5.C2.D0.R0: Starting preamble search lower nibbles
N7.C1.D0.R0.S15: PI = 021, PtrOffset = 004
N1.C1.D0.R0.S09: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N3.C3.D0.R1.S16: Write Level Fine Value = 455
N5.C2.D0.R0.S00: PI = 005, PtrOffset = 004
N7.C1.D0.R0.S16: PI = 042, PtrOffset = 004
N1.C1.D0.R0.S10: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N3.C3.D0.R1.S17: Write Level Fine Value = 421
N5.C2.D0.R0.S01: PI = 047, PtrOffset = 005
N7.C1.D0.R0.S17: PI = 025, PtrOffset = 005
N1.C1.D0.R0.S11: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N3: END WRITE LEVEL:
N5.C2.D0.R0.S02: PI = 015, PtrOffset = 005
N7.C1.D0.R0.S09: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N1.C1.D0.R0.S12: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N3: START WRITE LEVEL COARSE:
N5.C2.D0.R0.S03: PI = 058, PtrOffset = 004
N7.C1.D0.R0.S10: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N1.C1.D0.R0.S13: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N5.C2.D0.R0.S04: PI = 055, PtrOffset = 004
N7.C1.D0.R0.S11: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N1.C1.D0.R0.S14: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N3.C0.D0.R0: Write Training Coarse, lower nibbles / bytes
N5.C2.D0.R0.S05: PI = 005, PtrOffset = 005
N7.C1.D0.R0.S12: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N1.C1.D0.R0.S15: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N3.C0.D0.R0.S00: Dq Delay estimate: 454
N5.C2.D0.R0.S06: PI = 045, PtrOffset = 005
N7.C1.D0.R0.S13: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N1.C1.D0.R0.S16: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N3.C0.D0.R0.S01: Dq Delay estimate: 432
N5.C2.D0.R0.S07: PI = 062, PtrOffset = 005
N7.C1.D0.R0.S14: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N1.C1.D0.R0.S17: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N3.C0.D0.R0.S02: Dq Delay estimate: 421
N5.C2.D0.R0.S08: PI = 047, PtrOffset = 004
N7.C1.D0.R0.S15: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N1.C1.D0.R0.S09: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N3.C0.D0.R0.S03: Dq Delay estimate: 404
N5.C2.D0.R0.S00: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N7.C1.D0.R0.S16: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N1.C1.D0.R0.S10: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N3.C0.D0.R0.S04: Dq Delay estimate: 371
N5.C2.D0.R0.S01: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N7.C1.D0.R0.S17: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N1.C1.D0.R0.S11: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N3.C0.D0.R0.S05: Dq Delay estimate: 387
N5.C2.D0.R0.S02: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N7.C1.D0.R0.S09: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N1.C1.D0.R0.S12: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N3.C0.D0.R0.S06: Dq Delay estimate: 393
N5.C2.D0.R0.S03: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N7.C1.D0.R0.S10: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N1.C1.D0.R0.S13: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N3.C0.D0.R0.S07: Dq Delay estimate: 409
N5.C2.D0.R0.S04: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N7.C1.D0.R0.S11: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N1.C1.D0.R0.S14: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N3.C0.D0.R0.S08: Dq Delay estimate: 379
N5.C2.D0.R0.S05: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N7.C1.D0.R0.S12: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N1.C1.D0.R0.S15: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
ACCM: 0F 9F9F0F0F 9F0F0F0F
N5.C2.D0.R0.S06: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N7.C1.D0.R0.S13: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N1.C1.D0.R0.S16: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
ACCM: 0F 9F9F0F0F 9F0F0F0F
N5.C2.D0.R0.S07: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N7.C1.D0.R0.S14: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N1.C1.D0.R0.S17: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
ACCM: 0F 9F9F0F0F 9FFFFFFF
N5.C2.D0.R0.S08: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N7.C1.D0.R0.S15: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N1.C1.D0.R0.S09: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
ACCM: 0F 9F9F0F0F 9FFFFFFF
N5.C2.D0.R0.S00: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N7.C1.D0.R0.S16: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N1.C1.D0.R0.S10: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N3.C0.D0.R0: CheckMCTest: result = 0x19FFF
N5.C2.D0.R0.S01: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N7.C1.D0.R0.S17: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N1.C1.D0.R0.S11: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
ACCM: 0F DF9F0F0F DF0F0F0F
N5.C2.D0.R0.S02: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N7.C1.D0.R0.S09: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N1.C1.D0.R0.S12: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
ACCM: 0F DF9F0F0F DF0F0F0F
N5.C2.D0.R0.S03: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N7.C1.D0.R0.S10: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N1.C1.D0.R0.S13: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
ACCM: 0F DF9F0F0F DFFFFFFF
N5.C2.D0.R0.S04: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N7.C1.D0.R0.S11: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N1.C1.D0.R0.S14: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
ACCM: 0F DF9F0F0F DFFFFFFF
N5.C2.D0.R0.S05: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N7.C1.D0.R0.S12: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N1.C1.D0.R0.S15: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N3.C0.D0.R0: CheckMCTest: result = 0x19FFF
N5.C2.D0.R0.S06: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N7.C1.D0.R0.S13: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N1.C1.D0.R0.S16: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
ACCM: 0F DFDF0F0F DF0F0F0F
N5.C2.D0.R0.S07: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N7.C1.D0.R0.S14: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N1.C1.D0.R0.S17: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
ACCM: 0F DFDF0F0F DF0F0F0F
N5.C2.D0.R0.S08: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N7.C1.D0.R0.S15: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N1.C1.D0.R0.S09: Preamble found at Latency = 008
ACCM: 00 D0D00000 D0F0F0F0
N5.C2.D0.R0.S00: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N7.C1.D0.R0.S16: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N1.C1.D0.R0.S10: Preamble found at Latency = 008
ACCM: 00 D0D00000 D0F0F0F0
N5.C2.D0.R0.S01: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N7.C1.D0.R0.S17: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N1.C1.D0.R0.S15: Preamble found at Latency = 008
N3.C0.D0.R0: CheckMCTest: result = 0x19FFF
N5.C2.D0.R0.S02: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N7.C1.D0.R0.S09: Preamble found at Latency = 008
N1.C1.D0.R0.S16: Preamble found at Latency = 008
ACCM: 0F DFDF0F0F DF0F0F0F
N5.C2.D0.R0.S03: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N7.C1.D0.R0.S10: Preamble found at Latency = 008
N1.C1.D0.R0.S09: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
ACCM: 0F DFDF0F0F DF0F0F0F
N5.C2.D0.R0.S04: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N7.C1.D0.R0.S11: Preamble found at Latency = 008
N1.C1.D0.R0.S10: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
ACCM: 00 D0D00000 D0F0F0F0
N5.C2.D0.R0.S05: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N7.C1.D0.R0.S15: Preamble found at Latency = 008
N1.C1.D0.R0.S11: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
ACCM: 00 D0D00000 D0F0F0F0
N5.C2.D0.R0.S06: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N7.C1.D0.R0.S16: Preamble found at Latency = 008
N1.C1.D0.R0.S12: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N3.C0.D0.R0: CheckMCTest: result = 0x19FFF
N5.C2.D0.R0.S07: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N7.C1.D0.R0.S09: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N1.C1.D0.R0.S13: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
ACCM: 00 D0D00000 D0000000
N5.C2.D0.R0.S08: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N7.C1.D0.R0.S10: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N1.C1.D0.R0.S14: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
ACCM: 00 D0D00000 D0000000
N5.C2.D0.R0.S00: Preamble found at Latency = 008
N7.C1.D0.R0.S11: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N1.C1.D0.R0.S15: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
ACCM: 00 D0D00000 D0F0F0F0
N5.C2.D0.R0.S00: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N7.C1.D0.R0.S12: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N1.C1.D0.R0.S16: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
ACCM: 00 D0D00000 D0F0F0F0
N5.C2.D0.R0.S01: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N7.C1.D0.R0.S13: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N1.C1.D0.R0.S17: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N3.C0.D0.R0: CheckMCTest: result = 0x19E00
N5.C2.D0.R0.S02: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N7.C1.D0.R0.S14: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N1.C1.D0.R0.S11: Preamble found at Latency = 007
ACCM: 00 D0D00000 D0000000
N5.C2.D0.R0.S03: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N7.C1.D0.R0.S15: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N1.C1.D0.R0.S12: Preamble found at Latency = 007
ACCM: 00 D0D00000 D0000000
N5.C2.D0.R0.S04: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N7.C1.D0.R0.S16: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N1.C1.D0.R0.S13: Preamble found at Latency = 007
ACCM: 00 D0D00000 D0F0F0F0
N5.C2.D0.R0.S05: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N7.C1.D0.R0.S17: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N1.C1.D0.R0.S14: Preamble found at Latency = 007
ACCM: 00 D0D00000 D0F0F0F0
N5.C2.D0.R0.S06: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N7.C1.D0.R0.S12: Preamble found at Latency = 007
N1.C1.D0.R0.S17: Preamble found at Latency = 007
N3.C0.D0.R0: CheckMCTest: result = 0x19E00
N5.C2.D0.R0.S07: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N7.C1.D0.R0.S13: Preamble found at Latency = 007
N1.C1.D0.R0: Preamble found for all upper nibbles, adjusting Pi, Offset to center into preamble
N3.C0.D0.R0.S00: Offset Found: RdPtrOffsetDqs = 007
N5.C2.D0.R0.S08: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N7.C1.D0.R0.S14: Preamble found at Latency = 007
N1.C1.D0.R0.S09: Total Receive Enable Delay = 1355
N3.C0.D0.R0.S01: Offset Found: RdPtrOffsetDqs = 007
N5.C2.D0.R0.S01: Preamble found at Latency = 007
N7.C1.D0.R0.S17: Preamble found at Latency = 007
N1.C1.D0.R0.S10: Total Receive Enable Delay = 1334
N3.C0.D0.R0.S02: Offset Found: RdPtrOffsetDqs = 007
N5.C2.D0.R0.S02: Preamble found at Latency = 007
N7.C1.D0.R0: Preamble found for all upper nibbles, adjusting Pi, Offset to center into preamble
N1.C1.D0.R0.S11: Total Receive Enable Delay = 1305
N3.C0.D0.R0.S03: Offset Found: RdPtrOffsetDqs = 006
N5.C2.D0.R0.S03: Preamble found at Latency = 007
N7.C1.D0.R0.S09: Total Receive Enable Delay = 1364
N1.C1.D0.R0.S12: Total Receive Enable Delay = 1287
N3.C0.D0.R0.S04: Offset Found: RdPtrOffsetDqs = 006
N5.C2.D0.R0.S04: Preamble found at Latency = 007
N7.C1.D0.R0.S10: Total Receive Enable Delay = 1343
N1.C1.D0.R0.S13: Total Receive Enable Delay = 1280
N3.C0.D0.R0.S05: Offset Found: RdPtrOffsetDqs = 006
N5.C2.D0.R0.S05: Preamble found at Latency = 007
N7.C1.D0.R0.S11: Total Receive Enable Delay = 1313
N1.C1.D0.R0.S14: Total Receive Enable Delay = 1302
N3.C0.D0.R0.S06: Offset Found: RdPtrOffsetDqs = 006
N5.C2.D0.R0.S06: Preamble found at Latency = 007
N7.C1.D0.R0.S12: Total Receive Enable Delay = 1291
N1.C1.D0.R0.S15: Total Receive Enable Delay = 1325
N3.C0.D0.R0.S07: Offset Found: RdPtrOffsetDqs = 006
N5.C2.D0.R0.S07: Preamble found at Latency = 007
N7.C1.D0.R0.S13: Total Receive Enable Delay = 1283
N1.C1.D0.R0.S16: Total Receive Enable Delay = 1350
N3.C0.D0.R0.S08: Offset Found: RdPtrOffsetDqs = 006
N5.C2.D0.R0.S08: Preamble found at Latency = 007
N7.C1.D0.R0.S14: Total Receive Enable Delay = 1309
N1.C1.D0.R0.S17: Total Receive Enable Delay = 1266
N3.C0.D0.R0: Write Training Coarse, upper nibbles
N5.C2.D0.R0.S00: Total Receive Enable Delay = 1317
N7.C1.D0.R0.S15: Total Receive Enable Delay = 1333
N1.C1.D0.R1: RcvEnFine: Initial RdCmd2RcvEnLatency = 10, Initial RdPtrOffsetRcvEn = 4
N3.C0.D0.R0.S09: Dq Delay estimate: 451
N5.C2.D0.R0.S01: Total Receive Enable Delay = 1295
N7.C1.D0.R0.S16: Total Receive Enable Delay = 1354
N1.C1.D0.R1.S00: Rcv En Fine Value = 299
N3.C0.D0.R0.S10: Dq Delay estimate: 431
N5.C2.D0.R0.S02: Total Receive Enable Delay = 1263
N7.C1.D0.R0.S17: Total Receive Enable Delay = 1273
N1.C1.D0.R1.S01: Rcv En Fine Value = 278
N3.C0.D0.R0.S11: Dq Delay estimate: 424
N5.C2.D0.R0.S03: Total Receive Enable Delay = 1242
N7.C1.D0.R1: RcvEnFine: Initial RdCmd2RcvEnLatency = 10, Initial RdPtrOffsetRcvEn = 4
N1.C1.D0.R1.S02: Rcv En Fine Value = 374
N3.C0.D0.R0.S12: Dq Delay estimate: 405
N5.C2.D0.R0.S04: Total Receive Enable Delay = 1239
N7.C1.D0.R1.S00: Rcv En Fine Value = 304
N1.C1.D0.R1.S03: Rcv En Fine Value = 356
N3.C0.D0.R0.S13: Dq Delay estimate: 372
N5.C2.D0.R0.S05: Total Receive Enable Delay = 1253
N7.C1.D0.R1.S01: Rcv En Fine Value = 286
N1.C1.D0.R1.S04: Rcv En Fine Value = 349
N3.C0.D0.R0.S14: Dq Delay estimate: 387
N5.C2.D0.R0.S06: Total Receive Enable Delay = 1293
N7.C1.D0.R1.S02: Rcv En Fine Value = 382
N1.C1.D0.R1.S05: Rcv En Fine Value = 373
N3.C0.D0.R0.S15: Dq Delay estimate: 395
N5.C2.D0.R0.S07: Total Receive Enable Delay = 1310
N7.C1.D0.R1.S03: Rcv En Fine Value = 359
N1.C1.D0.R1.S06: Rcv En Fine Value = 269
N3.C0.D0.R0.S16: Dq Delay estimate: 414
N5.C2.D0.R0.S08: Total Receive Enable Delay = 1231
N7.C1.D0.R1.S04: Rcv En Fine Value = 358
N1.C1.D0.R1.S07: Rcv En Fine Value = 291
N3.C0.D0.R0.S17: Dq Delay estimate: 380
N5.C2.D0.R0: Starting preamble search upper nibbles
N7.C1.D0.R1.S05: Rcv En Fine Value = 382
N1.C1.D0.R1.S08: Rcv En Fine Value = 336
ACCM: F0 F0F0F0F0 F0F0F0F0
N5.C2.D0.R0.S09: PI = 006, PtrOffset = 004
N7.C1.D0.R1.S06: Rcv En Fine Value = 277
N1.C1.D0.R1.S09: Rcv En Fine Value = 296
ACCM: F0 F0F0F0F0 F0F0F0F0
N5.C2.D0.R0.S10: PI = 044, PtrOffset = 005
N7.C1.D0.R1.S07: Rcv En Fine Value = 298
N1.C1.D0.R1.S10: Rcv En Fine Value = 280
ACCM: F0 F0F0F0F0 F0F0F0F0
N5.C2.D0.R0.S11: PI = 013, PtrOffset = 005
N7.C1.D0.R1.S08: Rcv En Fine Value = 342
N1.C1.D0.R1.S11: Rcv En Fine Value = 377
ACCM: F0 F0F0F0F0 F0F0F0F0
N5.C2.D0.R0.S12: PI = 058, PtrOffset = 004
N7.C1.D0.R1.S09: Rcv En Fine Value = 309
N1.C1.D0.R1.S12: Rcv En Fine Value = 356
N3.C0.D0.R0: CheckMCTest: result = 0x3FE00
N5.C2.D0.R0.S13: PI = 057, PtrOffset = 004
N7.C1.D0.R1.S10: Rcv En Fine Value = 287
N1.C1.D0.R1.S13: Rcv En Fine Value = 349
ACCM: F0 F0F0F0F0 F0F0F0F0
N5.C2.D0.R0.S14: PI = 006, PtrOffset = 005
N7.C1.D0.R1.S11: Rcv En Fine Value = 256
N1.C1.D0.R1.S14: Rcv En Fine Value = 374
ACCM: F0 F0F0F0F0 F0F0F0F0
N5.C2.D0.R0.S15: PI = 043, PtrOffset = 005
N7.C1.D0.R1.S12: Rcv En Fine Value = 363
N1.C1.D0.R1.S15: Rcv En Fine Value = 267
ACCM: F0 F0F0F0F0 F0F0F0F0
N5.C2.D0.R0.S16: PI = 061, PtrOffset = 005
N7.C1.D0.R1.S13: Rcv En Fine Value = 357
N1.C1.D0.R1.S16: Rcv En Fine Value = 294
ACCM: F0 F0F0F0F0 F0F0F0F0
N5.C2.D0.R0.S17: PI = 042, PtrOffset = 004
N7.C1.D0.R1.S14: Rcv En Fine Value = 379
N1.C1.D0.R1.S17: Rcv En Fine Value = 337
N3.C0.D0.R0: CheckMCTest: result = 0x3FE00
N5.C2.D0.R0.S09: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N7.C1.D0.R1.S15: Rcv En Fine Value = 277
N1.C1.D0.R1: Starting preamble search lower nibbles
ACCM: F0 F0F0F0F0 F0F0F0F0
N5.C2.D0.R0.S10: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N7.C1.D0.R1.S16: Rcv En Fine Value = 300
N1.C1.D0.R1.S00: PI = 043, PtrOffset = 004
ACCM: F0 F0F0F0F0 F0F0F0F0
N5.C2.D0.R0.S11: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N7.C1.D0.R1.S17: Rcv En Fine Value = 343
N1.C1.D0.R1.S01: PI = 022, PtrOffset = 004
ACCM: 00 00000000 00000000
N5.C2.D0.R0.S12: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N7.C1.D0.R1: Starting preamble search lower nibbles
N1.C1.D0.R1.S02: PI = 054, PtrOffset = 005
ACCM: 00 00000000 00000000
N5.C2.D0.R0.S13: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N7.C1.D0.R1.S00: PI = 048, PtrOffset = 004
N1.C1.D0.R1.S03: PI = 036, PtrOffset = 005
N3.C0.D0.R0: CheckMCTest: result = 0x3FE00
N5.C2.D0.R0.S14: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N7.C1.D0.R1.S01: PI = 030, PtrOffset = 004
N1.C1.D0.R1.S04: PI = 029, PtrOffset = 005
ACCM: F0 F0F0F0F0 F0F0F0F0
N5.C2.D0.R0.S15: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N7.C1.D0.R1.S02: PI = 062, PtrOffset = 005
N1.C1.D0.R1.S05: PI = 053, PtrOffset = 005
ACCM: F0 F0F0F0F0 F0F0F0F0
N5.C2.D0.R0.S16: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N7.C1.D0.R1.S03: PI = 039, PtrOffset = 005
N1.C1.D0.R1.S06: PI = 013, PtrOffset = 004
ACCM: 00 00000000 00000000
N5.C2.D0.R0.S17: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N7.C1.D0.R1.S04: PI = 038, PtrOffset = 005
N1.C1.D0.R1.S07: PI = 035, PtrOffset = 004
ACCM: 00 00000000 00000000
N5.C2.D0.R0.S09: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N7.C1.D0.R1.S05: PI = 062, PtrOffset = 005
N1.C1.D0.R1.S08: PI = 016, PtrOffset = 005
N3.C0.D0.R0: CheckMCTest: result = 0x3FE00
N5.C2.D0.R0.S10: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N7.C1.D0.R1.S06: PI = 021, PtrOffset = 004
N1.C1.D0.R1.S00: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N3.C0.D0.R0: CheckMCTest: passed
N5.C2.D0.R0.S11: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N7.C1.D0.R1.S07: PI = 042, PtrOffset = 004
N1.C1.D0.R1.S01: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N3.C0.D0.R0: CheckMCTest: passed
N5.C2.D0.R0.S12: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N7.C1.D0.R1.S08: PI = 022, PtrOffset = 005
N1.C1.D0.R1.S02: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N3.C0.D0.R0.S09: Offset Found: RdPtrOffsetDqs = 007
N5.C2.D0.R0.S13: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N7.C1.D0.R1.S00: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N1.C1.D0.R1.S03: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N3.C0.D0.R0.S10: Offset Found: RdPtrOffsetDqs = 007
N5.C2.D0.R0.S14: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N7.C1.D0.R1.S01: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N1.C1.D0.R1.S04: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N3.C0.D0.R0.S11: Offset Found: RdPtrOffsetDqs = 007
N5.C2.D0.R0.S15: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N7.C1.D0.R1.S02: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N1.C1.D0.R1.S05: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N3.C0.D0.R0.S12: Offset Found: RdPtrOffsetDqs = 006
N5.C2.D0.R0.S16: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N7.C1.D0.R1.S03: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N1.C1.D0.R1.S06: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N3.C0.D0.R0.S13: Offset Found: RdPtrOffsetDqs = 006
N5.C2.D0.R0.S17: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N7.C1.D0.R1.S04: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N1.C1.D0.R1.S07: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N3.C0.D0.R0.S14: Offset Found: RdPtrOffsetDqs = 006
N5.C2.D0.R0.S09: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N7.C1.D0.R1.S05: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N1.C1.D0.R1.S08: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N3.C0.D0.R0.S15: Offset Found: RdPtrOffsetDqs = 006
N5.C2.D0.R0.S10: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N7.C1.D0.R1.S06: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N1.C1.D0.R1.S00: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N3.C0.D0.R0.S16: Offset Found: RdPtrOffsetDqs = 006
N5.C2.D0.R0.S11: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N7.C1.D0.R1.S07: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N1.C1.D0.R1.S01: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N3.C0.D0.R0.S17: Offset Found: RdPtrOffsetDqs = 006
N5.C2.D0.R0.S12: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N7.C1.D0.R1.S08: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N1.C1.D0.R1.S02: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N3.C0.D0.R1: Write Training Coarse, lower nibbles / bytes
N5.C2.D0.R0.S13: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N7.C1.D0.R1.S00: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N1.C1.D0.R1.S03: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N3.C0.D0.R1.S00: Dq Delay estimate: 456
N5.C2.D0.R0.S14: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N7.C1.D0.R1.S01: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N1.C1.D0.R1.S04: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N3.C0.D0.R1.S01: Dq Delay estimate: 433
N5.C2.D0.R0.S15: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N7.C1.D0.R1.S02: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N1.C1.D0.R1.S05: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N3.C0.D0.R1.S02: Dq Delay estimate: 420
N5.C2.D0.R0.S16: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N7.C1.D0.R1.S03: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N1.C1.D0.R1.S06: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N3.C0.D0.R1.S03: Dq Delay estimate: 403
N5.C2.D0.R0.S17: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N7.C1.D0.R1.S04: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N1.C1.D0.R1.S07: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N3.C0.D0.R1.S04: Dq Delay estimate: 371
N5.C2.D0.R0.S09: Preamble found at Latency = 008
N7.C1.D0.R1.S05: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N1.C1.D0.R1.S08: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N3.C0.D0.R1.S05: Dq Delay estimate: 386
N5.C2.D0.R0.S09: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N7.C1.D0.R1.S06: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N1.C1.D0.R1.S00: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N3.C0.D0.R1.S06: Dq Delay estimate: 391
N5.C2.D0.R0.S10: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N7.C1.D0.R1.S07: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N1.C1.D0.R1.S01: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N3.C0.D0.R1.S07: Dq Delay estimate: 412
N5.C2.D0.R0.S11: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N7.C1.D0.R1.S08: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N1.C1.D0.R1.S02: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N3.C0.D0.R1.S08: Dq Delay estimate: 377
N5.C2.D0.R0.S12: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N7.C1.D0.R1.S00: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N1.C1.D0.R1.S03: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
ACCM: 0F 0F0F0F0F 0F0F0F0F
N5.C2.D0.R0.S13: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N7.C1.D0.R1.S01: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N1.C1.D0.R1.S04: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
ACCM: 0F 0F0F0F0F 0F0F0F0F
N5.C2.D0.R0.S14: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N7.C1.D0.R1.S02: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N1.C1.D0.R1.S05: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
ACCM: 0F 0F0F0F0F 0F0F0F0F
N5.C2.D0.R0.S15: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N7.C1.D0.R1.S03: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N1.C1.D0.R1.S06: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
ACCM: 0F 0F0F0F0F 0F0F0F0F
N5.C2.D0.R0.S16: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N7.C1.D0.R1.S04: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N1.C1.D0.R1.S07: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N3.C0.D0.R1: CheckMCTest: result = 0x1FF
N5.C2.D0.R0.S17: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N7.C1.D0.R1.S05: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N1.C1.D0.R1.S08: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
ACCM: 0F 0F0F0F0F 0F0F0F0F
N5.C2.D0.R0.S10: Preamble found at Latency = 007
N7.C1.D0.R1.S06: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N1.C1.D0.R1.S00: Preamble found at Latency = 008
ACCM: 0F 0F0F0F0F 0F0F0F0F
N5.C2.D0.R0.S11: Preamble found at Latency = 007
N7.C1.D0.R1.S07: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N1.C1.D0.R1.S01: Preamble found at Latency = 008
ACCM: 0F 0F0F0F0F 0F0F0F0F
N5.C2.D0.R0.S12: Preamble found at Latency = 007
N7.C1.D0.R1.S08: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N1.C1.D0.R1.S06: Preamble found at Latency = 008
ACCM: 0F 0F0F0F0F 0F0F0F0F
N5.C2.D0.R0.S13: Preamble found at Latency = 007
N7.C1.D0.R1.S00: Preamble found at Latency = 008
N1.C1.D0.R1.S07: Preamble found at Latency = 008
N3.C0.D0.R1: CheckMCTest: result = 0x1FF
N5.C2.D0.R0.S14: Preamble found at Latency = 007
N7.C1.D0.R1.S01: Preamble found at Latency = 008
N1.C1.D0.R1.S00: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
ACCM: 0F 0F0F0F0F 0F0F0F0F
N5.C2.D0.R0.S15: Preamble found at Latency = 007
N7.C1.D0.R1.S06: Preamble found at Latency = 008
N1.C1.D0.R1.S01: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
ACCM: 0F 0F0F0F0F 0F0F0F0F
N5.C2.D0.R0.S16: Preamble found at Latency = 007
N7.C1.D0.R1.S07: Preamble found at Latency = 008
N1.C1.D0.R1.S02: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
ACCM: 00 00000000 0B000000
N5.C2.D0.R0.S17: Preamble found at Latency = 007
N7.C1.D0.R1.S00: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N1.C1.D0.R1.S03: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
ACCM: 00 00000000 0B000000
N5.C2.D0.R0: Preamble found for all upper nibbles, adjusting Pi, Offset to center into preamble
N7.C1.D0.R1.S01: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N1.C1.D0.R1.S04: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N3.C0.D0.R1: CheckMCTest: result = 0x1FF
N5.C2.D0.R0.S09: Total Receive Enable Delay = 1318
N7.C1.D0.R1.S02: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N1.C1.D0.R1.S05: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
ACCM: 0F 0F0F0F0F 0F0F0F0F
N5.C2.D0.R0.S10: Total Receive Enable Delay = 1292
N7.C1.D0.R1.S03: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N1.C1.D0.R1.S06: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
ACCM: 0F 0F0F0F0F 0F0F0F0F
N5.C2.D0.R0.S11: Total Receive Enable Delay = 1261
N7.C1.D0.R1.S04: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N1.C1.D0.R1.S07: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
ACCM: 00 00000000 0B000000
N5.C2.D0.R0.S12: Total Receive Enable Delay = 1242
N7.C1.D0.R1.S05: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N1.C1.D0.R1.S08: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
ACCM: 00 00000000 0B000000
N5.C2.D0.R0.S13: Total Receive Enable Delay = 1241
N7.C1.D0.R1.S06: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N1.C1.D0.R1.S02: Preamble found at Latency = 007
N3.C0.D0.R1: CheckMCTest: result = 0x1FF
N5.C2.D0.R0.S14: Total Receive Enable Delay = 1254
N7.C1.D0.R1.S07: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N1.C1.D0.R1.S03: Preamble found at Latency = 007
N3.C0.D0.R1: CheckMCTest: passed
N5.C2.D0.R0.S15: Total Receive Enable Delay = 1291
N7.C1.D0.R1.S08: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N1.C1.D0.R1.S04: Preamble found at Latency = 007
N3.C0.D0.R1: CheckMCTest: passed
N5.C2.D0.R0.S16: Total Receive Enable Delay = 1309
N7.C1.D0.R1.S02: Preamble found at Latency = 007
N1.C1.D0.R1.S05: Preamble found at Latency = 007
N3.C0.D0.R1.S00: Offset Found: RdPtrOffsetDqs = 007
N5.C2.D0.R0.S17: Total Receive Enable Delay = 1226
N7.C1.D0.R1.S03: Preamble found at Latency = 007
N1.C1.D0.R1.S08: Preamble found at Latency = 007
N3.C0.D0.R1.S01: Offset Found: RdPtrOffsetDqs = 007
N5.C2.D0.R1: RcvEnFine: Initial RdCmd2RcvEnLatency = 10, Initial RdPtrOffsetRcvEn = 4
N7.C1.D0.R1.S04: Preamble found at Latency = 007
N1.C1.D0.R1.S00: Total Receive Enable Delay = 1355
N3.C0.D0.R1.S02: Offset Found: RdPtrOffsetDqs = 007
N5.C2.D0.R1.S00: Rcv En Fine Value = 261
N7.C1.D0.R1.S05: Preamble found at Latency = 007
N1.C1.D0.R1.S01: Total Receive Enable Delay = 1334
N3.C0.D0.R1.S03: Offset Found: RdPtrOffsetDqs = 006
N5.C2.D0.R1.S01: Rcv En Fine Value = 364
N7.C1.D0.R1.S08: Preamble found at Latency = 007
N1.C1.D0.R1.S02: Total Receive Enable Delay = 1302
N3.C0.D0.R1.S04: Offset Found: RdPtrOffsetDqs = 006
N5.C2.D0.R1.S02: Rcv En Fine Value = 334
N7.C1.D0.R1.S00: Total Receive Enable Delay = 1360
N1.C1.D0.R1.S03: Total Receive Enable Delay = 1284
N3.C0.D0.R1.S05: Offset Found: RdPtrOffsetDqs = 006
N5.C2.D0.R1.S03: Rcv En Fine Value = 314
N7.C1.D0.R1.S01: Total Receive Enable Delay = 1342
N1.C1.D0.R1.S04: Total Receive Enable Delay = 1277
N3.C0.D0.R1.S06: Offset Found: RdPtrOffsetDqs = 006
N5.C2.D0.R1.S04: Rcv En Fine Value = 312
N7.C1.D0.R1.S02: Total Receive Enable Delay = 1310
N1.C1.D0.R1.S05: Total Receive Enable Delay = 1301
N3.C0.D0.R1.S07: Offset Found: RdPtrOffsetDqs = 006
N5.C2.D0.R1.S05: Rcv En Fine Value = 325
N7.C1.D0.R1.S03: Total Receive Enable Delay = 1287
N1.C1.D0.R1.S06: Total Receive Enable Delay = 1325
N3.C0.D0.R1.S08: Offset Found: RdPtrOffsetDqs = 006
N5.C2.D0.R1.S06: Rcv En Fine Value = 363
N7.C1.D0.R1.S04: Total Receive Enable Delay = 1286
N1.C1.D0.R1.S07: Total Receive Enable Delay = 1347
N3.C0.D0.R1: Write Training Coarse, upper nibbles
N5.C2.D0.R1.S07: Rcv En Fine Value = 382
N7.C1.D0.R1.S05: Total Receive Enable Delay = 1310
N1.C1.D0.R1.S08: Total Receive Enable Delay = 1264
N3.C0.D0.R1.S09: Dq Delay estimate: 450
N5.C2.D0.R1.S08: Rcv En Fine Value = 300
N7.C1.D0.R1.S06: Total Receive Enable Delay = 1333
N1.C1.D0.R1: Starting preamble search upper nibbles
N3.C0.D0.R1.S10: Dq Delay estimate: 433
N5.C2.D0.R1.S09: Rcv En Fine Value = 258
N7.C1.D0.R1.S07: Total Receive Enable Delay = 1354
N1.C1.D0.R1.S09: PI = 040, PtrOffset = 004
N3.C0.D0.R1.S11: Dq Delay estimate: 424
N5.C2.D0.R1.S10: Rcv En Fine Value = 365
N7.C1.D0.R1.S08: Total Receive Enable Delay = 1270
N1.C1.D0.R1.S10: PI = 024, PtrOffset = 004
N3.C0.D0.R1.S12: Dq Delay estimate: 403
N5.C2.D0.R1.S11: Rcv En Fine Value = 335
N7.C1.D0.R1: Starting preamble search upper nibbles
N1.C1.D0.R1.S11: PI = 057, PtrOffset = 005
N3.C0.D0.R1.S13: Dq Delay estimate: 371
N5.C2.D0.R1.S12: Rcv En Fine Value = 317
N7.C1.D0.R1.S09: PI = 053, PtrOffset = 004
N1.C1.D0.R1.S12: PI = 036, PtrOffset = 005
N3.C0.D0.R1.S14: Dq Delay estimate: 386
N5.C2.D0.R1.S13: Rcv En Fine Value = 312
N7.C1.D0.R1.S10: PI = 031, PtrOffset = 004
N1.C1.D0.R1.S13: PI = 029, PtrOffset = 005
N3.C0.D0.R1.S15: Dq Delay estimate: 396
N5.C2.D0.R1.S14: Rcv En Fine Value = 324
N7.C1.D0.R1.S11: PI = 000, PtrOffset = 004
N1.C1.D0.R1.S14: PI = 054, PtrOffset = 005
N3.C0.D0.R1.S16: Dq Delay estimate: 414
N5.C2.D0.R1.S15: Rcv En Fine Value = 364
N7.C1.D0.R1.S12: PI = 043, PtrOffset = 005
N1.C1.D0.R1.S15: PI = 011, PtrOffset = 004
N3.C0.D0.R1.S17: Dq Delay estimate: 379
N5.C2.D0.R1.S16: Rcv En Fine Value = 381
N7.C1.D0.R1.S13: PI = 037, PtrOffset = 005
N1.C1.D0.R1.S16: PI = 038, PtrOffset = 004
ACCM: F0 F0F0F0F0 F0F0F0F0
N5.C2.D0.R1.S17: Rcv En Fine Value = 301
N7.C1.D0.R1.S14: PI = 059, PtrOffset = 005
N1.C1.D0.R1.S17: PI = 017, PtrOffset = 005
ACCM: F0 F0F0F0F0 F0F0F0F0
N5.C2.D0.R1: Starting preamble search lower nibbles
N7.C1.D0.R1.S15: PI = 021, PtrOffset = 004
N1.C1.D0.R1.S09: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
ACCM: F0 F0F0F0F0 F0F0F0F0
N5.C2.D0.R1.S00: PI = 005, PtrOffset = 004
N7.C1.D0.R1.S16: PI = 044, PtrOffset = 004
N1.C1.D0.R1.S10: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
ACCM: F0 F0F0F0F0 F0F0F0F0
N5.C2.D0.R1.S01: PI = 044, PtrOffset = 005
N7.C1.D0.R1.S17: PI = 023, PtrOffset = 005
N1.C1.D0.R1.S11: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N3.C0.D0.R1: CheckMCTest: result = 0x3FE00
N5.C2.D0.R1.S02: PI = 014, PtrOffset = 005
N7.C1.D0.R1.S09: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N1.C1.D0.R1.S12: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
ACCM: F0 F0F0F0F0 F0F0F0F0
N5.C2.D0.R1.S03: PI = 058, PtrOffset = 004
N7.C1.D0.R1.S10: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N1.C1.D0.R1.S13: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
ACCM: F0 F0F0F0F0 F0F0F0F0
N5.C2.D0.R1.S04: PI = 056, PtrOffset = 004
N7.C1.D0.R1.S11: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N1.C1.D0.R1.S14: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
ACCM: F0 F0F0F0F0 F0F0F0F0
N5.C2.D0.R1.S05: PI = 005, PtrOffset = 005
N7.C1.D0.R1.S12: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N1.C1.D0.R1.S15: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
ACCM: F0 F0F0F0F0 F0F0F0F0
N5.C2.D0.R1.S06: PI = 043, PtrOffset = 005
N7.C1.D0.R1.S13: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N1.C1.D0.R1.S16: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N3.C0.D0.R1: CheckMCTest: result = 0x3FE00
N5.C2.D0.R1.S07: PI = 062, PtrOffset = 005
N7.C1.D0.R1.S14: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N1.C1.D0.R1.S17: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
ACCM: F0 F0F0F0F0 F0F0F0F0
N5.C2.D0.R1.S08: PI = 044, PtrOffset = 004
N7.C1.D0.R1.S15: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N1.C1.D0.R1.S09: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
ACCM: F0 F0F0F0F0 F0F0F0F0
N5.C2.D0.R1.S00: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N7.C1.D0.R1.S16: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N1.C1.D0.R1.S10: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
ACCM: 00 00000000 00000000
N5.C2.D0.R1.S01: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N7.C1.D0.R1.S17: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N1.C1.D0.R1.S11: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
ACCM: 00 00000000 00000000
N5.C2.D0.R1.S02: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N7.C1.D0.R1.S09: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N1.C1.D0.R1.S12: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N3.C0.D0.R1: CheckMCTest: result = 0x3FE00
N5.C2.D0.R1.S03: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N7.C1.D0.R1.S10: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N1.C1.D0.R1.S13: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
ACCM: F0 F0F0F0F0 F0F0F0F0
N5.C2.D0.R1.S04: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N7.C1.D0.R1.S11: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N1.C1.D0.R1.S14: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
ACCM: F0 F0F0F0F0 F0F0F0F0
N5.C2.D0.R1.S05: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N7.C1.D0.R1.S12: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N1.C1.D0.R1.S15: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
ACCM: 00 00000000 00000000
N5.C2.D0.R1.S06: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N7.C1.D0.R1.S13: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N1.C1.D0.R1.S16: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
ACCM: 00 00000000 00000000
N5.C2.D0.R1.S07: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N7.C1.D0.R1.S14: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N1.C1.D0.R1.S17: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N3.C0.D0.R1: CheckMCTest: result = 0x3FE00
N5.C2.D0.R1.S08: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N7.C1.D0.R1.S15: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N1.C1.D0.R1.S09: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N3.C0.D0.R1: CheckMCTest: passed
N5.C2.D0.R1.S00: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N7.C1.D0.R1.S16: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N1.C1.D0.R1.S10: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N3.C0.D0.R1: CheckMCTest: passed
N5.C2.D0.R1.S01: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N7.C1.D0.R1.S17: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N1.C1.D0.R1.S11: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N3.C0.D0.R1.S09: Offset Found: RdPtrOffsetDqs = 007
N5.C2.D0.R1.S02: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N7.C1.D0.R1.S09: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N1.C1.D0.R1.S12: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N3.C0.D0.R1.S10: Offset Found: RdPtrOffsetDqs = 007
N5.C2.D0.R1.S03: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N7.C1.D0.R1.S10: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N1.C1.D0.R1.S13: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N3.C0.D0.R1.S11: Offset Found: RdPtrOffsetDqs = 007
N5.C2.D0.R1.S04: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N7.C1.D0.R1.S11: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N1.C1.D0.R1.S14: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N3.C0.D0.R1.S12: Offset Found: RdPtrOffsetDqs = 006
N5.C2.D0.R1.S05: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N7.C1.D0.R1.S12: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N1.C1.D0.R1.S15: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N3.C0.D0.R1.S13: Offset Found: RdPtrOffsetDqs = 006
N5.C2.D0.R1.S06: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N7.C1.D0.R1.S13: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N1.C1.D0.R1.S16: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N3.C0.D0.R1.S14: Offset Found: RdPtrOffsetDqs = 006
N5.C2.D0.R1.S07: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N7.C1.D0.R1.S14: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N1.C1.D0.R1.S17: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N3.C0.D0.R1.S15: Offset Found: RdPtrOffsetDqs = 006
N5.C2.D0.R1.S08: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N7.C1.D0.R1.S15: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N1.C1.D0.R1.S09: Preamble found at Latency = 008
N3.C0.D0.R1.S16: Offset Found: RdPtrOffsetDqs = 006
N5.C2.D0.R1.S00: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N7.C1.D0.R1.S16: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N1.C1.D0.R1.S10: Preamble found at Latency = 008
N3.C0.D0.R1.S17: Offset Found: RdPtrOffsetDqs = 006
N5.C2.D0.R1.S01: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N7.C1.D0.R1.S17: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N1.C1.D0.R1.S15: Preamble found at Latency = 008
N3.C0: Calculating Optimimum DQS Values
N5.C2.D0.R1.S02: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N7.C1.D0.R1.S09: Preamble found at Latency = 008
N1.C1.D0.R1.S16: Preamble found at Latency = 008
N3.C0.D0.R0.S00: Total Delay in PI ticks: TxDQS = 996, TxDQ = 966
N5.C2.D0.R1.S03: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N7.C1.D0.R1.S10: Preamble found at Latency = 008
N1.C1.D0.R1.S09: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N3.C0.D0.R0.S01: Total Delay in PI ticks: TxDQS = 978, TxDQ = 944
N5.C2.D0.R1.S04: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N7.C1.D0.R1.S11: Preamble found at Latency = 008
N1.C1.D0.R1.S10: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N3.C0.D0.R0.S02: Total Delay in PI ticks: TxDQS = 967, TxDQ = 933
N5.C2.D0.R1.S05: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N7.C1.D0.R1.S15: Preamble found at Latency = 008
N1.C1.D0.R1.S11: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N3.C0.D0.R0.S03: Total Delay in PI ticks: TxDQS = 952, TxDQ = 916
N5.C2.D0.R1.S06: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N7.C1.D0.R1.S16: Preamble found at Latency = 008
N1.C1.D0.R1.S12: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N3.C0.D0.R0.S04: Total Delay in PI ticks: TxDQS = 917, TxDQ = 883
N5.C2.D0.R1.S07: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N7.C1.D0.R1.S09: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N1.C1.D0.R1.S13: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N3.C0.D0.R0.S05: Total Delay in PI ticks: TxDQS = 935, TxDQ = 899
N5.C2.D0.R1.S08: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N7.C1.D0.R1.S10: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N1.C1.D0.R1.S14: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N3.C0.D0.R0.S06: Total Delay in PI ticks: TxDQS = 938, TxDQ = 905
N5.C2.D0.R1.S00: Preamble found at Latency = 008
N7.C1.D0.R1.S11: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N1.C1.D0.R1.S15: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N3.C0.D0.R0.S07: Total Delay in PI ticks: TxDQS = 956, TxDQ = 921
N5.C2.D0.R1.S00: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N7.C1.D0.R1.S12: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N1.C1.D0.R1.S16: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N3.C0.D0.R0.S08: Total Delay in PI ticks: TxDQS = 926, TxDQ = 891
N5.C2.D0.R1.S01: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N7.C1.D0.R1.S13: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N1.C1.D0.R1.S17: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N3.C0.D0.R0.S09: Total Delay in PI ticks: TxDQS = 996, TxDQ = 963
N5.C2.D0.R1.S02: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N7.C1.D0.R1.S14: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N1.C1.D0.R1.S11: Preamble found at Latency = 007
N3.C0.D0.R0.S10: Total Delay in PI ticks: TxDQS = 978, TxDQ = 943
N5.C2.D0.R1.S03: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N7.C1.D0.R1.S15: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N1.C1.D0.R1.S12: Preamble found at Latency = 007
N3.C0.D0.R0.S11: Total Delay in PI ticks: TxDQS = 967, TxDQ = 936
N5.C2.D0.R1.S04: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N7.C1.D0.R1.S16: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N1.C1.D0.R1.S13: Preamble found at Latency = 007
N3.C0.D0.R0.S12: Total Delay in PI ticks: TxDQS = 952, TxDQ = 917
N5.C2.D0.R1.S05: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N7.C1.D0.R1.S17: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N1.C1.D0.R1.S14: Preamble found at Latency = 007
N3.C0.D0.R0.S13: Total Delay in PI ticks: TxDQS = 918, TxDQ = 884
N5.C2.D0.R1.S06: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N7.C1.D0.R1.S12: Preamble found at Latency = 007
N1.C1.D0.R1.S17: Preamble found at Latency = 007
N3.C0.D0.R0.S14: Total Delay in PI ticks: TxDQS = 934, TxDQ = 899
N5.C2.D0.R1.S07: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N7.C1.D0.R1.S13: Preamble found at Latency = 007
N1.C1.D0.R1: Preamble found for all upper nibbles, adjusting Pi, Offset to center into preamble
N3.C0.D0.R0.S15: Total Delay in PI ticks: TxDQS = 938, TxDQ = 907
N5.C2.D0.R1.S08: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N7.C1.D0.R1.S14: Preamble found at Latency = 007
N1.C1.D0.R1.S09: Total Receive Enable Delay = 1352
N3.C0.D0.R0.S16: Total Delay in PI ticks: TxDQS = 956, TxDQ = 926
N5.C2.D0.R1.S01: Preamble found at Latency = 007
N7.C1.D0.R1.S17: Preamble found at Latency = 007
N1.C1.D0.R1.S10: Total Receive Enable Delay = 1336
N3.C0.D0.R0.S17: Total Delay in PI ticks: TxDQS = 926, TxDQ = 892
N5.C2.D0.R1.S02: Preamble found at Latency = 007
N7.C1.D0.R1: Preamble found for all upper nibbles, adjusting Pi, Offset to center into preamble
N1.C1.D0.R1.S11: Total Receive Enable Delay = 1305
N3.C0.D0.R1.S00: Total Delay in PI ticks: TxDQS = 997, TxDQ = 968
N5.C2.D0.R1.S03: Preamble found at Latency = 007
N7.C1.D0.R1.S09: Total Receive Enable Delay = 1365
N1.C1.D0.R1.S12: Total Receive Enable Delay = 1284
N3.C0.D0.R1.S01: Total Delay in PI ticks: TxDQS = 979, TxDQ = 945
N5.C2.D0.R1.S04: Preamble found at Latency = 007
N7.C1.D0.R1.S10: Total Receive Enable Delay = 1343
N1.C1.D0.R1.S13: Total Receive Enable Delay = 1277
N3.C0.D0.R1.S02: Total Delay in PI ticks: TxDQS = 966, TxDQ = 932
N5.C2.D0.R1.S05: Preamble found at Latency = 007
N7.C1.D0.R1.S11: Total Receive Enable Delay = 1312
N1.C1.D0.R1.S14: Total Receive Enable Delay = 1302
N3.C0.D0.R1.S03: Total Delay in PI ticks: TxDQS = 951, TxDQ = 915
N5.C2.D0.R1.S06: Preamble found at Latency = 007
N7.C1.D0.R1.S12: Total Receive Enable Delay = 1291
N1.C1.D0.R1.S15: Total Receive Enable Delay = 1323
N3.C0.D0.R1.S04: Total Delay in PI ticks: TxDQS = 917, TxDQ = 883
N5.C2.D0.R1.S07: Preamble found at Latency = 007
N7.C1.D0.R1.S13: Total Receive Enable Delay = 1285
N1.C1.D0.R1.S16: Total Receive Enable Delay = 1350
N3.C0.D0.R1.S05: Total Delay in PI ticks: TxDQS = 934, TxDQ = 898
N5.C2.D0.R1.S08: Preamble found at Latency = 007
N7.C1.D0.R1.S14: Total Receive Enable Delay = 1307
N1.C1.D0.R1.S17: Total Receive Enable Delay = 1265
N3.C0.D0.R1.S06: Total Delay in PI ticks: TxDQS = 937, TxDQ = 903
N5.C2.D0.R1.S00: Total Receive Enable Delay = 1317
N7.C1.D0.R1.S15: Total Receive Enable Delay = 1333
START_DATA_REC_EN
N3.C0.D0.R1.S07: Total Delay in PI ticks: TxDQS = 956, TxDQ = 924
N5.C2.D0.R1.S01: Total Receive Enable Delay = 1292
N7.C1.D0.R1.S16: Total Receive Enable Delay = 1356
N1.C1.S00: RdCmd2RcvEnLatency = 9, RdPtrOffsetRcvEn = 5
N3.C0.D0.R1.S08: Total Delay in PI ticks: TxDQS = 923, TxDQ = 889
N5.C2.D0.R1.S02: Total Receive Enable Delay = 1262
N7.C1.D0.R1.S17: Total Receive Enable Delay = 1271
N1.C1.S01: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N3.C0.D0.R1.S09: Total Delay in PI ticks: TxDQS = 995, TxDQ = 962
N5.C2.D0.R1.S03: Total Receive Enable Delay = 1242
START_DATA_REC_EN
N1.C1.S02: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N3.C0.D0.R1.S10: Total Delay in PI ticks: TxDQS = 979, TxDQ = 945
N5.C2.D0.R1.S04: Total Receive Enable Delay = 1240
N7.C1.S00: RdCmd2RcvEnLatency = 9, RdPtrOffsetRcvEn = 5
N1.C1.S03: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N3.C0.D0.R1.S11: Total Delay in PI ticks: TxDQS = 968, TxDQ = 936
N5.C2.D0.R1.S05: Total Receive Enable Delay = 1253
N7.C1.S01: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N1.C1.S04: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 5
N3.C0.D0.R1.S12: Total Delay in PI ticks: TxDQS = 951, TxDQ = 915
N5.C2.D0.R1.S06: Total Receive Enable Delay = 1291
N7.C1.S02: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N1.C1.S05: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N3.C0.D0.R1.S13: Total Delay in PI ticks: TxDQS = 917, TxDQ = 883
N5.C2.D0.R1.S07: Total Receive Enable Delay = 1310
N7.C1.S03: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N1.C1.S06: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N3.C0.D0.R1.S14: Total Delay in PI ticks: TxDQS = 933, TxDQ = 898
N5.C2.D0.R1.S08: Total Receive Enable Delay = 1228
N7.C1.S04: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N1.C1.S07: RdCmd2RcvEnLatency = 9, RdPtrOffsetRcvEn = 5
N3.C0.D0.R1.S15: Total Delay in PI ticks: TxDQS = 938, TxDQ = 908
N5.C2.D0.R1: Starting preamble search upper nibbles
N7.C1.S05: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N1.C1.S08: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 5
N3.C0.D0.R1.S16: Total Delay in PI ticks: TxDQS = 956, TxDQ = 926
N5.C2.D0.R1.S09: PI = 002, PtrOffset = 004
N7.C1.S06: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N1.C1.S09: RdCmd2RcvEnLatency = 9, RdPtrOffsetRcvEn = 5
N3.C0.D0.R1.S17: Total Delay in PI ticks: TxDQS = 925, TxDQ = 891
N5.C2.D0.R1.S10: PI = 045, PtrOffset = 005
N7.C1.S07: RdCmd2RcvEnLatency = 9, RdPtrOffsetRcvEn = 5
N1.C1.S10: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N3.C1.D0.R0: Write Training Coarse, lower nibbles / bytes
N5.C2.D0.R1.S11: PI = 015, PtrOffset = 005
N7.C1.S08: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 5
N1.C1.S11: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N3.C1.D0.R0.S00: Dq Delay estimate: 455
N5.C2.D0.R1.S12: PI = 061, PtrOffset = 004
N7.C1.S09: RdCmd2RcvEnLatency = 9, RdPtrOffsetRcvEn = 5
N1.C1.S12: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N3.C1.D0.R0.S01: Dq Delay estimate: 434
N5.C2.D0.R1.S13: PI = 056, PtrOffset = 004
N7.C1.S10: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N1.C1.S13: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 5
N3.C1.D0.R0.S02: Dq Delay estimate: 429
N5.C2.D0.R1.S14: PI = 004, PtrOffset = 005
N7.C1.S11: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N1.C1.S14: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N3.C1.D0.R0.S03: Dq Delay estimate: 407
N5.C2.D0.R1.S15: PI = 044, PtrOffset = 005
N7.C1.S12: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N1.C1.S15: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N3.C1.D0.R0.S04: Dq Delay estimate: 376
N5.C2.D0.R1.S16: PI = 061, PtrOffset = 005
N7.C1.S13: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N1.C1.S16: RdCmd2RcvEnLatency = 9, RdPtrOffsetRcvEn = 5
N3.C1.D0.R0.S05: Dq Delay estimate: 388
N5.C2.D0.R1.S17: PI = 045, PtrOffset = 004
N7.C1.S14: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N1.C1.S17: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 5
N3.C1.D0.R0.S06: Dq Delay estimate: 403
N5.C2.D0.R1.S09: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N7.C1.S15: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N1.C1.D0.R0.S00: RcvEn: plus1 = 1, minus1 = 0, PI = 11, DB = 1
N3.C1.D0.R0.S07: Dq Delay estimate: 422
N5.C2.D0.R1.S10: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N7.C1.S16: RdCmd2RcvEnLatency = 9, RdPtrOffsetRcvEn = 5
N1.C1.D0.R0.S01: RcvEn: plus1 = 1, minus1 = 0, PI = 55, DB = 1
N3.C1.D0.R0.S08: Dq Delay estimate: 388
N5.C2.D0.R1.S11: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N7.C1.S17: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 5
N1.C1.D0.R0.S02: RcvEn: plus1 = 1, minus1 = 0, PI = 22, DB = 0
ACCM: 9F 0F9F0F0F 9F0F0F0F
N5.C2.D0.R1.S12: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N7.C1.D0.R0.S00: RcvEn: plus1 = 1, minus1 = 0, PI = 17, DB = 0
N1.C1.D0.R0.S03: RcvEn: plus1 = 1, minus1 = 0, PI = 05, DB = 1
ACCM: 9F 0F9F0F0F 9F0F0F0F
N5.C2.D0.R1.S13: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N7.C1.D0.R0.S01: RcvEn: plus1 = 1, minus1 = 0, PI = 62, DB = 1
N1.C1.D0.R0.S04: RcvEn: plus1 = 1, minus1 = 0, PI = 61, DB = 1
ACCM: 9F FF9F0F0F 9FFFFFFF
N5.C2.D0.R1.S14: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N7.C1.D0.R0.S02: RcvEn: plus1 = 1, minus1 = 0, PI = 31, DB = 0
N1.C1.D0.R0.S05: RcvEn: plus1 = 1, minus1 = 0, PI = 22, DB = 0
ACCM: 9F FF9F0F0F 9FFFFFFF
N5.C2.D0.R1.S15: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N7.C1.D0.R0.S03: RcvEn: plus1 = 1, minus1 = 0, PI = 09, DB = 1
N1.C1.D0.R0.S06: RcvEn: plus1 = 1, minus1 = 0, PI = 45, DB = 0
N3.C1.D0.R0: CheckMCTest: result = 0x39FFF
N5.C2.D0.R1.S16: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N7.C1.D0.R0.S04: RcvEn: plus1 = 1, minus1 = 0, PI = 06, DB = 1
N1.C1.D0.R0.S07: RcvEn: plus1 = 1, minus1 = 0, PI = 03, DB = 1
ACCM: DF 0FDF0FDF DF0F0F0F
N5.C2.D0.R1.S17: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N7.C1.D0.R0.S05: RcvEn: plus1 = 1, minus1 = 0, PI = 28, DB = 0
N1.C1.D0.R0.S08: RcvEn: plus1 = 1, minus1 = 0, PI = 47, DB = 0
ACCM: DF 0FDF0FDF DF0F0F0F
N5.C2.D0.R1.S09: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N7.C1.D0.R0.S06: RcvEn: plus1 = 1, minus1 = 0, PI = 53, DB = 1
N1.C1.D0.R0.S09: RcvEn: plus1 = 1, minus1 = 0, PI = 09, DB = 1
ACCM: DF FFDF0FDF DFFFFFFF
N5.C2.D0.R1.S10: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N7.C1.D0.R0.S07: RcvEn: plus1 = 1, minus1 = 0, PI = 10, DB = 1
N1.C1.D0.R0.S10: RcvEn: plus1 = 1, minus1 = 0, PI = 55, DB = 1
ACCM: DF FFDF0FDF DFFFFFFF
N5.C2.D0.R1.S11: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N7.C1.D0.R0.S08: RcvEn: plus1 = 1, minus1 = 0, PI = 55, DB = 1
N1.C1.D0.R0.S11: RcvEn: plus1 = 1, minus1 = 0, PI = 25, DB = 0
N3.C1.D0.R0: CheckMCTest: result = 0x3BFFF
N5.C2.D0.R1.S12: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N7.C1.D0.R0.S09: RcvEn: plus1 = 1, minus1 = 0, PI = 20, DB = 0
N1.C1.D0.R0.S12: RcvEn: plus1 = 1, minus1 = 0, PI = 05, DB = 1
ACCM: DF 0FDF0F0F DF0F0F0F
N5.C2.D0.R1.S13: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N7.C1.D0.R0.S10: RcvEn: plus1 = 1, minus1 = 0, PI = 63, DB = 1
N1.C1.D0.R0.S13: RcvEn: plus1 = 1, minus1 = 0, PI = 62, DB = 1
ACCM: DF 0FDF0F0F DF0F0F0F
N5.C2.D0.R1.S14: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N7.C1.D0.R0.S11: RcvEn: plus1 = 1, minus1 = 0, PI = 32, DB = 0
N1.C1.D0.R0.S14: RcvEn: plus1 = 1, minus1 = 0, PI = 22, DB = 0
ACCM: D0 F0D00000 D0F0F0F0
N5.C2.D0.R1.S15: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N7.C1.D0.R0.S12: RcvEn: plus1 = 1, minus1 = 0, PI = 11, DB = 1
N1.C1.D0.R0.S15: RcvEn: plus1 = 1, minus1 = 0, PI = 44, DB = 0
ACCM: D0 F0D00000 D0F0F0F0
N5.C2.D0.R1.S16: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N7.C1.D0.R0.S13: RcvEn: plus1 = 1, minus1 = 0, PI = 04, DB = 1
N1.C1.D0.R0.S16: RcvEn: plus1 = 1, minus1 = 0, PI = 06, DB = 1
N3.C1.D0.R0: CheckMCTest: result = 0x39FFF
N5.C2.D0.R1.S17: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N7.C1.D0.R0.S14: RcvEn: plus1 = 1, minus1 = 0, PI = 28, DB = 0
N1.C1.D0.R0.S17: RcvEn: plus1 = 1, minus1 = 0, PI = 49, DB = 1
ACCM: DF 0FDF0FDF DF0F0F0F
N5.C2.D0.R1.S09: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N7.C1.D0.R0.S15: RcvEn: plus1 = 1, minus1 = 0, PI = 53, DB = 1
N1.C1.D0.R1.S00: RcvEn: plus1 = 1, minus1 = 0, PI = 11, DB = 1
ACCM: DF 0FDF0FDF DF0F0F0F
N5.C2.D0.R1.S10: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N7.C1.D0.R0.S16: RcvEn: plus1 = 1, minus1 = 0, PI = 11, DB = 1
N1.C1.D0.R1.S01: RcvEn: plus1 = 1, minus1 = 0, PI = 55, DB = 1
ACCM: D0 F0D000D0 D0F0F0F0
N5.C2.D0.R1.S11: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N7.C1.D0.R0.S17: RcvEn: plus1 = 1, minus1 = 0, PI = 56, DB = 1
N1.C1.D0.R1.S02: RcvEn: plus1 = 1, minus1 = 0, PI = 22, DB = 0
ACCM: D0 F0D000D0 D0F0F0F0
N5.C2.D0.R1.S12: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N7.C1.D0.R1.S00: RcvEn: plus1 = 1, minus1 = 0, PI = 17, DB = 0
N1.C1.D0.R1.S03: RcvEn: plus1 = 1, minus1 = 0, PI = 05, DB = 1
N3.C1.D0.R0: CheckMCTest: result = 0x3BFFF
N5.C2.D0.R1.S13: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N7.C1.D0.R1.S01: RcvEn: plus1 = 1, minus1 = 0, PI = 62, DB = 1
N1.C1.D0.R1.S04: RcvEn: plus1 = 1, minus1 = 0, PI = 61, DB = 1
ACCM: 00 00D000D0 D0000000
N5.C2.D0.R1.S14: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N7.C1.D0.R1.S02: RcvEn: plus1 = 1, minus1 = 0, PI = 31, DB = 0
N1.C1.D0.R1.S05: RcvEn: plus1 = 1, minus1 = 0, PI = 22, DB = 0
ACCM: 00 00D000D0 D0000000
N5.C2.D0.R1.S15: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N7.C1.D0.R1.S03: RcvEn: plus1 = 1, minus1 = 0, PI = 09, DB = 1
N1.C1.D0.R1.S06: RcvEn: plus1 = 1, minus1 = 0, PI = 45, DB = 0
ACCM: 00 F0D000D0 D0F0F0F0
N5.C2.D0.R1.S16: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N7.C1.D0.R1.S04: RcvEn: plus1 = 1, minus1 = 0, PI = 06, DB = 1
N1.C1.D0.R1.S07: RcvEn: plus1 = 1, minus1 = 0, PI = 03, DB = 1
ACCM: 00 F0D000D0 D0F0F0F0
N5.C2.D0.R1.S17: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N7.C1.D0.R1.S05: RcvEn: plus1 = 1, minus1 = 0, PI = 28, DB = 0
N1.C1.D0.R1.S08: RcvEn: plus1 = 1, minus1 = 0, PI = 47, DB = 0
N3.C1.D0.R0: CheckMCTest: result = 0x1BE00
N5.C2.D0.R1.S09: Preamble found at Latency = 008
N7.C1.D0.R1.S06: RcvEn: plus1 = 1, minus1 = 0, PI = 53, DB = 1
N1.C1.D0.R1.S09: RcvEn: plus1 = 1, minus1 = 0, PI = 09, DB = 1
ACCM: D0 00D000D0 D0000000
N5.C2.D0.R1.S09: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N7.C1.D0.R1.S07: RcvEn: plus1 = 1, minus1 = 0, PI = 10, DB = 1
N1.C1.D0.R1.S10: RcvEn: plus1 = 1, minus1 = 0, PI = 55, DB = 1
ACCM: D0 00D000D0 D0000000
N5.C2.D0.R1.S10: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N7.C1.D0.R1.S08: RcvEn: plus1 = 1, minus1 = 0, PI = 55, DB = 1
N1.C1.D0.R1.S11: RcvEn: plus1 = 1, minus1 = 0, PI = 25, DB = 0
ACCM: D0 F0D000D0 D0F0F0F0
N5.C2.D0.R1.S11: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N7.C1.D0.R1.S09: RcvEn: plus1 = 1, minus1 = 0, PI = 20, DB = 0
N1.C1.D0.R1.S12: RcvEn: plus1 = 1, minus1 = 0, PI = 05, DB = 1
ACCM: D0 F0D000D0 D0F0F0F0
N5.C2.D0.R1.S12: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N7.C1.D0.R1.S10: RcvEn: plus1 = 1, minus1 = 0, PI = 63, DB = 1
N1.C1.D0.R1.S13: RcvEn: plus1 = 1, minus1 = 0, PI = 62, DB = 1
N3.C1.D0.R0: CheckMCTest: result = 0x3BE00
N5.C2.D0.R1.S13: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N7.C1.D0.R1.S11: RcvEn: plus1 = 1, minus1 = 0, PI = 32, DB = 0
N1.C1.D0.R1.S14: RcvEn: plus1 = 1, minus1 = 0, PI = 22, DB = 0
N3.C1.D0.R0.S00: Offset Found: RdPtrOffsetDqs = 007
N5.C2.D0.R1.S14: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N7.C1.D0.R1.S12: RcvEn: plus1 = 1, minus1 = 0, PI = 11, DB = 1
N1.C1.D0.R1.S15: RcvEn: plus1 = 1, minus1 = 0, PI = 44, DB = 0
N3.C1.D0.R0.S01: Offset Found: RdPtrOffsetDqs = 007
N5.C2.D0.R1.S15: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N7.C1.D0.R1.S13: RcvEn: plus1 = 1, minus1 = 0, PI = 04, DB = 1
N1.C1.D0.R1.S16: RcvEn: plus1 = 1, minus1 = 0, PI = 06, DB = 1
N3.C1.D0.R0.S02: Offset Found: RdPtrOffsetDqs = 007
N5.C2.D0.R1.S16: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N7.C1.D0.R1.S14: RcvEn: plus1 = 1, minus1 = 0, PI = 28, DB = 0
N1.C1.D0.R1.S17: RcvEn: plus1 = 1, minus1 = 0, PI = 49, DB = 1
N3.C1.D0.R0.S03: Offset Found: RdPtrOffsetDqs = 006
N5.C2.D0.R1.S17: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N7.C1.D0.R1.S15: RcvEn: plus1 = 1, minus1 = 0, PI = 53, DB = 1
STOP_DATA_REC_EN
N3.C1.D0.R0.S04: Offset Found: RdPtrOffsetDqs = 006
N5.C2.D0.R1.S10: Preamble found at Latency = 007
N7.C1.D0.R1.S16: RcvEn: plus1 = 1, minus1 = 0, PI = 11, DB = 1
N1.C2.D0.R0: RcvEnFine: Initial RdCmd2RcvEnLatency = 10, Initial RdPtrOffsetRcvEn = 4
N3.C1.D0.R0.S05: Offset Found: RdPtrOffsetDqs = 006
N5.C2.D0.R1.S11: Preamble found at Latency = 007
N7.C1.D0.R1.S17: RcvEn: plus1 = 1, minus1 = 0, PI = 56, DB = 1
N1.C2.D0.R0.S00: Rcv En Fine Value = 258
N3.C1.D0.R0.S06: Offset Found: RdPtrOffsetDqs = 006
N5.C2.D0.R1.S12: Preamble found at Latency = 007
STOP_DATA_REC_EN
N1.C2.D0.R0.S01: Rcv En Fine Value = 359
N3.C1.D0.R0.S07: Offset Found: RdPtrOffsetDqs = 007
N5.C2.D0.R1.S13: Preamble found at Latency = 007
N7.C2.D0.R0: RcvEnFine: Initial RdCmd2RcvEnLatency = 10, Initial RdPtrOffsetRcvEn = 4
N1.C2.D0.R0.S02: Rcv En Fine Value = 327
N3.C1.D0.R0.S08: Offset Found: RdPtrOffsetDqs = 006
N5.C2.D0.R1.S14: Preamble found at Latency = 007
N7.C2.D0.R0.S00: Rcv En Fine Value = 381
N1.C2.D0.R0.S03: Rcv En Fine Value = 307
N3.C1.D0.R0: Write Training Coarse, upper nibbles
N5.C2.D0.R1.S15: Preamble found at Latency = 007
N7.C2.D0.R0.S01: Rcv En Fine Value = 359
N1.C2.D0.R0.S04: Rcv En Fine Value = 316
N3.C1.D0.R0.S09: Dq Delay estimate: 448
N5.C2.D0.R1.S16: Preamble found at Latency = 007
N7.C2.D0.R0.S02: Rcv En Fine Value = 326
N1.C2.D0.R0.S05: Rcv En Fine Value = 322
N3.C1.D0.R0.S10: Dq Delay estimate: 435
N5.C2.D0.R1.S17: Preamble found at Latency = 007
N7.C2.D0.R0.S03: Rcv En Fine Value = 304
N1.C2.D0.R0.S06: Rcv En Fine Value = 361
N3.C1.D0.R0.S11: Dq Delay estimate: 429
N5.C2.D0.R1: Preamble found for all upper nibbles, adjusting Pi, Offset to center into preamble
N7.C2.D0.R0.S04: Rcv En Fine Value = 307
N1.C2.D0.R0.S07: Rcv En Fine Value = 377
N3.C1.D0.R0.S12: Dq Delay estimate: 408
N5.C2.D0.R1.S09: Total Receive Enable Delay = 1314
N7.C2.D0.R0.S05: Rcv En Fine Value = 321
N1.C2.D0.R0.S08: Rcv En Fine Value = 296
N3.C1.D0.R0.S13: Dq Delay estimate: 380
N5.C2.D0.R1.S10: Total Receive Enable Delay = 1293
N7.C2.D0.R0.S06: Rcv En Fine Value = 358
N1.C2.D0.R0.S09: Rcv En Fine Value = 382
N3.C1.D0.R0.S14: Dq Delay estimate: 389
N5.C2.D0.R1.S11: Total Receive Enable Delay = 1263
N7.C2.D0.R0.S07: Rcv En Fine Value = 377
N1.C2.D0.R0.S10: Rcv En Fine Value = 361
N3.C1.D0.R0.S15: Dq Delay estimate: 401
N5.C2.D0.R1.S12: Total Receive Enable Delay = 1245
N7.C2.D0.R0.S08: Rcv En Fine Value = 296
N1.C2.D0.R0.S11: Rcv En Fine Value = 326
N3.C1.D0.R0.S16: Dq Delay estimate: 423
N5.C2.D0.R1.S13: Total Receive Enable Delay = 1240
N7.C2.D0.R0.S09: Rcv En Fine Value = 379
N1.C2.D0.R0.S12: Rcv En Fine Value = 307
N3.C1.D0.R0.S17: Dq Delay estimate: 386
N5.C2.D0.R1.S14: Total Receive Enable Delay = 1252
N7.C2.D0.R0.S10: Rcv En Fine Value = 357
N1.C2.D0.R0.S13: Rcv En Fine Value = 311
ACCM: F0 F0F0F0F0 F0F0F0F0
N5.C2.D0.R1.S15: Total Receive Enable Delay = 1292
N7.C2.D0.R0.S11: Rcv En Fine Value = 326
N1.C2.D0.R0.S14: Rcv En Fine Value = 319
ACCM: F0 F0F0F0F0 F0F0F0F0
N5.C2.D0.R1.S16: Total Receive Enable Delay = 1309
N7.C2.D0.R0.S12: Rcv En Fine Value = 305
N1.C2.D0.R0.S15: Rcv En Fine Value = 361
ACCM: F0 F0F0F0F0 F0F0F0F0
N5.C2.D0.R1.S17: Total Receive Enable Delay = 1229
N7.C2.D0.R0.S13: Rcv En Fine Value = 311
N1.C2.D0.R0.S16: Rcv En Fine Value = 378
ACCM: F0 F0F0F0F0 F0F0F0F0
START_DATA_REC_EN
N7.C2.D0.R0.S14: Rcv En Fine Value = 322
N1.C2.D0.R0.S17: Rcv En Fine Value = 294
N3.C1.D0.R0: CheckMCTest: result = 0x3FE00
N5.C2.S00: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N7.C2.D0.R0.S15: Rcv En Fine Value = 358
N1.C2.D0.R0: Starting preamble search lower nibbles
ACCM: F0 F0F0F0F0 F0F0F0F0
N5.C2.S01: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N7.C2.D0.R0.S16: Rcv En Fine Value = 379
N1.C2.D0.R0.S00: PI = 002, PtrOffset = 004
ACCM: F0 F0F0F0F0 F0F0F0F0
N5.C2.S02: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 5
N7.C2.D0.R0.S17: Rcv En Fine Value = 295
N1.C2.D0.R0.S01: PI = 039, PtrOffset = 005
ACCM: F0 F0F0F0F0 F0F0F0F0
N5.C2.S03: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 5
N7.C2.D0.R0: Starting preamble search lower nibbles
N1.C2.D0.R0.S02: PI = 007, PtrOffset = 005
ACCM: F0 F0F0F0F0 F0F0F0F0
N5.C2.S04: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 5
N7.C2.D0.R0.S00: PI = 061, PtrOffset = 005
N1.C2.D0.R0.S03: PI = 051, PtrOffset = 004
N3.C1.D0.R0: CheckMCTest: result = 0x3FE00
N5.C2.S05: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 5
N7.C2.D0.R0.S01: PI = 039, PtrOffset = 005
N1.C2.D0.R0.S04: PI = 060, PtrOffset = 004
ACCM: F0 F0F0F0F0 F0F0F0F0
N5.C2.S06: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N7.C2.D0.R0.S02: PI = 006, PtrOffset = 005
N1.C2.D0.R0.S05: PI = 002, PtrOffset = 005
ACCM: F0 F0F0F0F0 F0F0F0F0
N5.C2.S07: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N7.C2.D0.R0.S03: PI = 048, PtrOffset = 004
N1.C2.D0.R0.S06: PI = 041, PtrOffset = 005
ACCM: 00 000000B0 00000000
N5.C2.S08: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 5
N7.C2.D0.R0.S04: PI = 051, PtrOffset = 004
N1.C2.D0.R0.S07: PI = 057, PtrOffset = 005
ACCM: 00 000000B0 00000000
N5.C2.S09: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N7.C2.D0.R0.S05: PI = 001, PtrOffset = 005
N1.C2.D0.R0.S08: PI = 040, PtrOffset = 004
N3.C1.D0.R0: CheckMCTest: result = 0x3FE00
N5.C2.S10: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N7.C2.D0.R0.S06: PI = 038, PtrOffset = 005
N1.C2.D0.R0.S00: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
ACCM: F0 F0F0F0F0 F0F0F0F0
N5.C2.S11: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 5
N7.C2.D0.R0.S07: PI = 057, PtrOffset = 005
N1.C2.D0.R0.S01: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
ACCM: F0 F0F0F0F0 F0F0F0F0
N5.C2.S12: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 5
N7.C2.D0.R0.S08: PI = 040, PtrOffset = 004
N1.C2.D0.R0.S02: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
ACCM: 00 000000B0 00000000
N5.C2.S13: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 5
N7.C2.D0.R0.S00: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N1.C2.D0.R0.S03: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
ACCM: 00 000000B0 00000000
N5.C2.S14: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 5
N7.C2.D0.R0.S01: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N1.C2.D0.R0.S04: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N3.C1.D0.R0: CheckMCTest: result = 0x3FE00
N5.C2.S15: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N7.C2.D0.R0.S02: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N1.C2.D0.R0.S05: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N3.C1.D0.R0: CheckMCTest: passed
N5.C2.S16: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N7.C2.D0.R0.S03: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N1.C2.D0.R0.S06: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N3.C1.D0.R0: CheckMCTest: passed
N5.C2.S17: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 5
N7.C2.D0.R0.S04: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N1.C2.D0.R0.S07: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N3.C1.D0.R0.S09: Offset Found: RdPtrOffsetDqs = 007
N5.C2.D0.R0.S00: RcvEn: plus1 = 1, minus1 = 0, PI = 37, DB = 0
N7.C2.D0.R0.S05: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N1.C2.D0.R0.S08: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N3.C1.D0.R0.S10: Offset Found: RdPtrOffsetDqs = 007
N5.C2.D0.R0.S01: RcvEn: plus1 = 1, minus1 = 0, PI = 13, DB = 1
N7.C2.D0.R0.S06: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N1.C2.D0.R0.S00: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N3.C1.D0.R0.S11: Offset Found: RdPtrOffsetDqs = 007
N5.C2.D0.R0.S02: RcvEn: plus1 = 1, minus1 = 0, PI = 46, DB = 0
N7.C2.D0.R0.S07: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N1.C2.D0.R0.S01: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N3.C1.D0.R0.S12: Offset Found: RdPtrOffsetDqs = 006
N5.C2.D0.R0.S03: RcvEn: plus1 = 1, minus1 = 0, PI = 26, DB = 0
N7.C2.D0.R0.S08: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N1.C2.D0.R0.S02: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N3.C1.D0.R0.S13: Offset Found: RdPtrOffsetDqs = 006
N5.C2.D0.R0.S04: RcvEn: plus1 = 1, minus1 = 0, PI = 23, DB = 0
N7.C2.D0.R0.S00: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N1.C2.D0.R0.S03: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N3.C1.D0.R0.S14: Offset Found: RdPtrOffsetDqs = 006
N5.C2.D0.R0.S05: RcvEn: plus1 = 1, minus1 = 0, PI = 37, DB = 0
N7.C2.D0.R0.S01: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N1.C2.D0.R0.S04: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N3.C1.D0.R0.S15: Offset Found: RdPtrOffsetDqs = 006
N5.C2.D0.R0.S06: RcvEn: plus1 = 1, minus1 = 0, PI = 12, DB = 1
N7.C2.D0.R0.S02: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N1.C2.D0.R0.S05: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N3.C1.D0.R0.S16: Offset Found: RdPtrOffsetDqs = 007
N5.C2.D0.R0.S07: RcvEn: plus1 = 1, minus1 = 0, PI = 30, DB = 0
N7.C2.D0.R0.S03: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N1.C2.D0.R0.S06: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N3.C1.D0.R0.S17: Offset Found: RdPtrOffsetDqs = 006
N5.C2.D0.R0.S08: RcvEn: plus1 = 1, minus1 = 0, PI = 13, DB = 1
N7.C2.D0.R0.S04: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N1.C2.D0.R0.S07: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N3.C1.D0.R1: Write Training Coarse, lower nibbles / bytes
N5.C2.D0.R0.S09: RcvEn: plus1 = 1, minus1 = 0, PI = 36, DB = 0
N7.C2.D0.R0.S05: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N1.C2.D0.R0.S08: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N3.C1.D0.R1.S00: Dq Delay estimate: 455
N5.C2.D0.R0.S10: RcvEn: plus1 = 1, minus1 = 0, PI = 12, DB = 1
N7.C2.D0.R0.S06: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N1.C2.D0.R0.S00: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N3.C1.D0.R1.S01: Dq Delay estimate: 433
N5.C2.D0.R0.S11: RcvEn: plus1 = 1, minus1 = 0, PI = 46, DB = 0
N7.C2.D0.R0.S07: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N1.C2.D0.R0.S01: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N3.C1.D0.R1.S02: Dq Delay estimate: 428
N5.C2.D0.R0.S12: RcvEn: plus1 = 1, minus1 = 0, PI = 27, DB = 0
N7.C2.D0.R0.S08: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N1.C2.D0.R0.S02: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N3.C1.D0.R1.S03: Dq Delay estimate: 404
N5.C2.D0.R0.S13: RcvEn: plus1 = 1, minus1 = 0, PI = 24, DB = 0
N7.C2.D0.R0.S00: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N1.C2.D0.R0.S03: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N3.C1.D0.R1.S04: Dq Delay estimate: 376
N5.C2.D0.R0.S14: RcvEn: plus1 = 1, minus1 = 0, PI = 37, DB = 0
N7.C2.D0.R0.S01: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N1.C2.D0.R0.S04: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N3.C1.D0.R1.S05: Dq Delay estimate: 388
N5.C2.D0.R0.S15: RcvEn: plus1 = 1, minus1 = 0, PI = 11, DB = 1
N7.C2.D0.R0.S02: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N1.C2.D0.R0.S05: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N3.C1.D0.R1.S06: Dq Delay estimate: 403
N5.C2.D0.R0.S16: RcvEn: plus1 = 1, minus1 = 0, PI = 29, DB = 0
N7.C2.D0.R0.S03: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N1.C2.D0.R0.S06: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N3.C1.D0.R1.S07: Dq Delay estimate: 420
N5.C2.D0.R0.S17: RcvEn: plus1 = 1, minus1 = 0, PI = 11, DB = 1
N7.C2.D0.R0.S04: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N1.C2.D0.R0.S07: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N3.C1.D0.R1.S08: Dq Delay estimate: 386
N5.C2.D0.R1.S00: RcvEn: plus1 = 1, minus1 = 0, PI = 37, DB = 0
N7.C2.D0.R0.S05: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N1.C2.D0.R0.S08: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
ACCM: 0F 0F0F0F0F 0F0F0F0F
N5.C2.D0.R1.S01: RcvEn: plus1 = 1, minus1 = 0, PI = 13, DB = 1
N7.C2.D0.R0.S06: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N1.C2.D0.R0.S00: Preamble found at Latency = 008
ACCM: 0F 0F0F0F0F 0F0F0F0F
N5.C2.D0.R1.S02: RcvEn: plus1 = 1, minus1 = 0, PI = 46, DB = 0
N7.C2.D0.R0.S07: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N1.C2.D0.R0.S00: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
ACCM: 0F 0F0F0F0F 0F0F0F0F
N5.C2.D0.R1.S03: RcvEn: plus1 = 1, minus1 = 0, PI = 26, DB = 0
N7.C2.D0.R0.S08: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N1.C2.D0.R0.S01: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
ACCM: 0F 0F0F0F0F 0F0F0F0F
N5.C2.D0.R1.S04: RcvEn: plus1 = 1, minus1 = 0, PI = 23, DB = 0
N7.C2.D0.R0.S00: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N1.C2.D0.R0.S02: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N3.C1.D0.R1: CheckMCTest: result = 0x1FF
N5.C2.D0.R1.S05: RcvEn: plus1 = 1, minus1 = 0, PI = 37, DB = 0
N7.C2.D0.R0.S01: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N1.C2.D0.R0.S03: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
ACCM: 0F 0F0F0F0F 0F0F0F0F
N5.C2.D0.R1.S06: RcvEn: plus1 = 1, minus1 = 0, PI = 12, DB = 1
N7.C2.D0.R0.S02: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N1.C2.D0.R0.S04: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
ACCM: 0F 0F0F0F0F 0F0F0F0F
N5.C2.D0.R1.S07: RcvEn: plus1 = 1, minus1 = 0, PI = 30, DB = 0
N7.C2.D0.R0.S03: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N1.C2.D0.R0.S05: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
ACCM: 0F 0F0F0F0F 0F0F0F0F
N5.C2.D0.R1.S08: RcvEn: plus1 = 1, minus1 = 0, PI = 13, DB = 1
N7.C2.D0.R0.S04: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N1.C2.D0.R0.S06: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
ACCM: 0F 0F0F0F0F 0F0F0F0F
N5.C2.D0.R1.S09: RcvEn: plus1 = 1, minus1 = 0, PI = 36, DB = 0
N7.C2.D0.R0.S05: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N1.C2.D0.R0.S07: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N3.C1.D0.R1: CheckMCTest: result = 0x1FF
N5.C2.D0.R1.S10: RcvEn: plus1 = 1, minus1 = 0, PI = 12, DB = 1
N7.C2.D0.R0.S06: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N1.C2.D0.R0.S08: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
ACCM: 0F 0F0F0F0F 0F0F0F0F
N5.C2.D0.R1.S11: RcvEn: plus1 = 1, minus1 = 0, PI = 46, DB = 0
N7.C2.D0.R0.S07: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N1.C2.D0.R0.S01: Preamble found at Latency = 007
ACCM: 0F 0F0F0F0F 0F0F0F0F
N5.C2.D0.R1.S12: RcvEn: plus1 = 1, minus1 = 0, PI = 27, DB = 0
N7.C2.D0.R0.S08: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N1.C2.D0.R0.S02: Preamble found at Latency = 007
ACCM: 00 00000000 00000000
N5.C2.D0.R1.S13: RcvEn: plus1 = 1, minus1 = 0, PI = 24, DB = 0
N7.C2.D0.R0.S00: Preamble found at Latency = 007
N1.C2.D0.R0.S03: Preamble found at Latency = 007
ACCM: 00 00000000 00000000
N5.C2.D0.R1.S14: RcvEn: plus1 = 1, minus1 = 0, PI = 37, DB = 0
N7.C2.D0.R0.S01: Preamble found at Latency = 007
N1.C2.D0.R0.S04: Preamble found at Latency = 007
N3.C1.D0.R1: CheckMCTest: result = 0x1FF
N5.C2.D0.R1.S15: RcvEn: plus1 = 1, minus1 = 0, PI = 11, DB = 1
N7.C2.D0.R0.S02: Preamble found at Latency = 007
N1.C2.D0.R0.S05: Preamble found at Latency = 007
ACCM: 0F 0F0F0F0F 0F0F0F0F
N5.C2.D0.R1.S16: RcvEn: plus1 = 1, minus1 = 0, PI = 29, DB = 0
N7.C2.D0.R0.S03: Preamble found at Latency = 007
N1.C2.D0.R0.S06: Preamble found at Latency = 007
ACCM: 0F 0F0F0F0F 0F0F0F0F
N5.C2.D0.R1.S17: RcvEn: plus1 = 1, minus1 = 0, PI = 11, DB = 1
N7.C2.D0.R0.S04: Preamble found at Latency = 007
N1.C2.D0.R0.S07: Preamble found at Latency = 007
ACCM: 00 00000000 00000000
STOP_DATA_REC_EN
N7.C2.D0.R0.S05: Preamble found at Latency = 007
N1.C2.D0.R0.S08: Preamble found at Latency = 007
ACCM: 00 00000000 00000000
N5.C3.D0.R0: RcvEnFine: Initial RdCmd2RcvEnLatency = 10, Initial RdPtrOffsetRcvEn = 4
N7.C2.D0.R0.S06: Preamble found at Latency = 007
N1.C2.D0.R0.S00: Total Receive Enable Delay = 1314
N3.C1.D0.R1: CheckMCTest: result = 0x1FF
N5.C3.D0.R0.S00: Rcv En Fine Value = 299
N7.C2.D0.R0.S07: Preamble found at Latency = 007
N1.C2.D0.R0.S01: Total Receive Enable Delay = 1287
N3.C1.D0.R1: CheckMCTest: passed
N5.C3.D0.R0.S01: Rcv En Fine Value = 279
N7.C2.D0.R0.S08: Preamble found at Latency = 007
N1.C2.D0.R0.S02: Total Receive Enable Delay = 1255
N3.C1.D0.R1: CheckMCTest: passed
N5.C3.D0.R0.S02: Rcv En Fine Value = 377
N7.C2.D0.R0.S00: Total Receive Enable Delay = 1309
N1.C2.D0.R0.S03: Total Receive Enable Delay = 1235
N3.C1.D0.R1.S00: Offset Found: RdPtrOffsetDqs = 007
N5.C3.D0.R0.S03: Rcv En Fine Value = 354
N7.C2.D0.R0.S01: Total Receive Enable Delay = 1287
N1.C2.D0.R0.S04: Total Receive Enable Delay = 1244
N3.C1.D0.R1.S01: Offset Found: RdPtrOffsetDqs = 007
N5.C3.D0.R0.S04: Rcv En Fine Value = 351
N7.C2.D0.R0.S02: Total Receive Enable Delay = 1254
N1.C2.D0.R0.S05: Total Receive Enable Delay = 1250
N3.C1.D0.R1.S02: Offset Found: RdPtrOffsetDqs = 007
N5.C3.D0.R0.S05: Rcv En Fine Value = 377
N7.C2.D0.R0.S03: Total Receive Enable Delay = 1232
N1.C2.D0.R0.S06: Total Receive Enable Delay = 1289
N3.C1.D0.R1.S03: Offset Found: RdPtrOffsetDqs = 006
N5.C3.D0.R0.S06: Rcv En Fine Value = 272
N7.C2.D0.R0.S04: Total Receive Enable Delay = 1235
N1.C2.D0.R0.S07: Total Receive Enable Delay = 1305
N3.C1.D0.R1.S04: Offset Found: RdPtrOffsetDqs = 006
N5.C3.D0.R0.S07: Rcv En Fine Value = 292
N7.C2.D0.R0.S05: Total Receive Enable Delay = 1249
N1.C2.D0.R0.S08: Total Receive Enable Delay = 1224
N3.C1.D0.R1.S05: Offset Found: RdPtrOffsetDqs = 006
N5.C3.D0.R0.S08: Rcv En Fine Value = 335
N7.C2.D0.R0.S06: Total Receive Enable Delay = 1286
N1.C2.D0.R0: Starting preamble search upper nibbles
N3.C1.D0.R1.S06: Offset Found: RdPtrOffsetDqs = 006
N5.C3.D0.R0.S09: Rcv En Fine Value = 298
N7.C2.D0.R0.S07: Total Receive Enable Delay = 1305
N1.C2.D0.R0.S09: PI = 062, PtrOffset = 005
N3.C1.D0.R1.S07: Offset Found: RdPtrOffsetDqs = 007
N5.C3.D0.R0.S10: Rcv En Fine Value = 278
N7.C2.D0.R0.S08: Total Receive Enable Delay = 1224
N1.C2.D0.R0.S10: PI = 041, PtrOffset = 005
N3.C1.D0.R1.S08: Offset Found: RdPtrOffsetDqs = 006
N5.C3.D0.R0.S11: Rcv En Fine Value = 380
N7.C2.D0.R0: Starting preamble search upper nibbles
N1.C2.D0.R0.S11: PI = 006, PtrOffset = 005
N3.C1.D0.R1: Write Training Coarse, upper nibbles
N5.C3.D0.R0.S12: Rcv En Fine Value = 355
N7.C2.D0.R0.S09: PI = 059, PtrOffset = 005
N1.C2.D0.R0.S12: PI = 051, PtrOffset = 004
N3.C1.D0.R1.S09: Dq Delay estimate: 448
N5.C3.D0.R0.S13: Rcv En Fine Value = 350
N7.C2.D0.R0.S10: PI = 037, PtrOffset = 005
N1.C2.D0.R0.S13: PI = 055, PtrOffset = 004
N3.C1.D0.R1.S10: Dq Delay estimate: 435
N5.C3.D0.R0.S14: Rcv En Fine Value = 377
N7.C2.D0.R0.S11: PI = 006, PtrOffset = 005
N1.C2.D0.R0.S14: PI = 063, PtrOffset = 004
N3.C1.D0.R1.S11: Dq Delay estimate: 427
N5.C3.D0.R0.S15: Rcv En Fine Value = 274
N7.C2.D0.R0.S12: PI = 049, PtrOffset = 004
N1.C2.D0.R0.S15: PI = 041, PtrOffset = 005
N3.C1.D0.R1.S12: Dq Delay estimate: 408
N5.C3.D0.R0.S16: Rcv En Fine Value = 296
N7.C2.D0.R0.S13: PI = 055, PtrOffset = 004
N1.C2.D0.R0.S16: PI = 058, PtrOffset = 005
N3.C1.D0.R1.S13: Dq Delay estimate: 379
N5.C3.D0.R0.S17: Rcv En Fine Value = 337
N7.C2.D0.R0.S14: PI = 002, PtrOffset = 005
N1.C2.D0.R0.S17: PI = 038, PtrOffset = 004
N3.C1.D0.R1.S14: Dq Delay estimate: 391
N5.C3.D0.R0: Starting preamble search lower nibbles
N7.C2.D0.R0.S15: PI = 038, PtrOffset = 005
N1.C2.D0.R0.S09: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N3.C1.D0.R1.S15: Dq Delay estimate: 402
N5.C3.D0.R0.S00: PI = 043, PtrOffset = 004
N7.C2.D0.R0.S16: PI = 059, PtrOffset = 005
N1.C2.D0.R0.S10: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N3.C1.D0.R1.S16: Dq Delay estimate: 422
N5.C3.D0.R0.S01: PI = 023, PtrOffset = 004
N7.C2.D0.R0.S17: PI = 039, PtrOffset = 004
N1.C2.D0.R0.S11: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N3.C1.D0.R1.S17: Dq Delay estimate: 387
N5.C3.D0.R0.S02: PI = 057, PtrOffset = 005
N7.C2.D0.R0.S09: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N1.C2.D0.R0.S12: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
ACCM: F0 F0F0F0F0 F0F0F0F0
N5.C3.D0.R0.S03: PI = 034, PtrOffset = 005
N7.C2.D0.R0.S10: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N1.C2.D0.R0.S13: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
ACCM: F0 F0F0F0F0 F0F0F0F0
N5.C3.D0.R0.S04: PI = 031, PtrOffset = 005
N7.C2.D0.R0.S11: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N1.C2.D0.R0.S14: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
ACCM: F0 F0F0F0F0 F0F0F0F0
N5.C3.D0.R0.S05: PI = 057, PtrOffset = 005
N7.C2.D0.R0.S12: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N1.C2.D0.R0.S15: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
ACCM: F0 F0F0F0F0 F0F0F0F0
N5.C3.D0.R0.S06: PI = 016, PtrOffset = 004
N7.C2.D0.R0.S13: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N1.C2.D0.R0.S16: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N3.C1.D0.R1: CheckMCTest: result = 0x3FE00
N5.C3.D0.R0.S07: PI = 036, PtrOffset = 004
N7.C2.D0.R0.S14: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N1.C2.D0.R0.S17: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
ACCM: F0 F0F0F0F0 F0F0F0F0
N5.C3.D0.R0.S08: PI = 015, PtrOffset = 005
N7.C2.D0.R0.S15: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N1.C2.D0.R0.S09: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
ACCM: F0 F0F0F0F0 F0F0F0F0
N5.C3.D0.R0.S00: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N7.C2.D0.R0.S16: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N1.C2.D0.R0.S10: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
ACCM: F0 F0F0F0F0 F0F0F0F0
N5.C3.D0.R0.S01: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N7.C2.D0.R0.S17: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N1.C2.D0.R0.S11: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
ACCM: F0 F0F0F0F0 F0F0F0F0
N5.C3.D0.R0.S02: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N7.C2.D0.R0.S09: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N1.C2.D0.R0.S12: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N3.C1.D0.R1: CheckMCTest: result = 0x3FE00
N5.C3.D0.R0.S03: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N7.C2.D0.R0.S10: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N1.C2.D0.R0.S13: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
ACCM: F0 F0F0F0F0 F0F0F0F0
N5.C3.D0.R0.S04: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N7.C2.D0.R0.S11: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N1.C2.D0.R0.S14: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
ACCM: F0 F0F0F0F0 F0F0F0F0
N5.C3.D0.R0.S05: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N7.C2.D0.R0.S12: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N1.C2.D0.R0.S15: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
ACCM: 00 00000000 00000000
N5.C3.D0.R0.S06: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N7.C2.D0.R0.S13: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N1.C2.D0.R0.S16: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
ACCM: 00 00000000 00000000
N5.C3.D0.R0.S07: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N7.C2.D0.R0.S14: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N1.C2.D0.R0.S17: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N3.C1.D0.R1: CheckMCTest: result = 0x3FE00
N5.C3.D0.R0.S08: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N7.C2.D0.R0.S15: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N1.C2.D0.R0.S09: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
ACCM: F0 F0F0F0F0 F0F0F0F0
N5.C3.D0.R0.S00: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N7.C2.D0.R0.S16: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N1.C2.D0.R0.S10: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
ACCM: F0 F0F0F0F0 F0F0F0F0
N5.C3.D0.R0.S01: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N7.C2.D0.R0.S17: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N1.C2.D0.R0.S11: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
ACCM: 00 00000000 00000000
N5.C3.D0.R0.S02: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N7.C2.D0.R0.S09: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N1.C2.D0.R0.S12: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
ACCM: 00 00000000 00000000
N5.C3.D0.R0.S03: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N7.C2.D0.R0.S10: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N1.C2.D0.R0.S13: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N3.C1.D0.R1: CheckMCTest: result = 0x3FE00
N5.C3.D0.R0.S04: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N7.C2.D0.R0.S11: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N1.C2.D0.R0.S14: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N3.C1.D0.R1: CheckMCTest: passed
N5.C3.D0.R0.S05: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N7.C2.D0.R0.S12: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N1.C2.D0.R0.S15: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N3.C1.D0.R1: CheckMCTest: passed
N5.C3.D0.R0.S06: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N7.C2.D0.R0.S13: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N1.C2.D0.R0.S16: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N3.C1.D0.R1.S09: Offset Found: RdPtrOffsetDqs = 007
N5.C3.D0.R0.S07: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N7.C2.D0.R0.S14: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N1.C2.D0.R0.S17: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N3.C1.D0.R1.S10: Offset Found: RdPtrOffsetDqs = 007
N5.C3.D0.R0.S08: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N7.C2.D0.R0.S15: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N1.C2.D0.R0.S09: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N3.C1.D0.R1.S11: Offset Found: RdPtrOffsetDqs = 007
N5.C3.D0.R0.S00: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N7.C2.D0.R0.S16: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N1.C2.D0.R0.S10: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N3.C1.D0.R1.S12: Offset Found: RdPtrOffsetDqs = 006
N5.C3.D0.R0.S01: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N7.C2.D0.R0.S17: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N1.C2.D0.R0.S11: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N3.C1.D0.R1.S13: Offset Found: RdPtrOffsetDqs = 006
N5.C3.D0.R0.S02: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N7.C2.D0.R0.S09: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N1.C2.D0.R0.S12: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N3.C1.D0.R1.S14: Offset Found: RdPtrOffsetDqs = 006
N5.C3.D0.R0.S03: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N7.C2.D0.R0.S10: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N1.C2.D0.R0.S13: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N3.C1.D0.R1.S15: Offset Found: RdPtrOffsetDqs = 006
N5.C3.D0.R0.S04: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N7.C2.D0.R0.S11: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N1.C2.D0.R0.S14: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N3.C1.D0.R1.S16: Offset Found: RdPtrOffsetDqs = 007
N5.C3.D0.R0.S05: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N7.C2.D0.R0.S12: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N1.C2.D0.R0.S15: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N3.C1.D0.R1.S17: Offset Found: RdPtrOffsetDqs = 006
N5.C3.D0.R0.S06: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N7.C2.D0.R0.S13: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N1.C2.D0.R0.S16: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N3.C1: Calculating Optimimum DQS Values
N5.C3.D0.R0.S07: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N7.C2.D0.R0.S14: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N1.C2.D0.R0.S17: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N3.C1.D0.R0.S00: Total Delay in PI ticks: TxDQS = 996, TxDQ = 967
N5.C3.D0.R0.S08: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N7.C2.D0.R0.S15: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N1.C2.D0.R0.S09: Preamble found at Latency = 007
N3.C1.D0.R0.S01: Total Delay in PI ticks: TxDQS = 980, TxDQ = 946
N5.C3.D0.R0.S00: Preamble found at Latency = 008
N7.C2.D0.R0.S16: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N1.C2.D0.R0.S10: Preamble found at Latency = 007
N3.C1.D0.R0.S02: Total Delay in PI ticks: TxDQS = 973, TxDQ = 941
N5.C3.D0.R0.S01: Preamble found at Latency = 008
N7.C2.D0.R0.S17: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N1.C2.D0.R0.S11: Preamble found at Latency = 007
N3.C1.D0.R0.S03: Total Delay in PI ticks: TxDQS = 954, TxDQ = 919
N5.C3.D0.R0.S06: Preamble found at Latency = 008
N7.C2.D0.R0.S09: Preamble found at Latency = 007
N1.C2.D0.R0.S12: Preamble found at Latency = 007
N3.C1.D0.R0.S04: Total Delay in PI ticks: TxDQS = 922, TxDQ = 888
N5.C3.D0.R0.S07: Preamble found at Latency = 008
N7.C2.D0.R0.S10: Preamble found at Latency = 007
N1.C2.D0.R0.S13: Preamble found at Latency = 007
N3.C1.D0.R0.S05: Total Delay in PI ticks: TxDQS = 936, TxDQ = 900
N5.C3.D0.R0.S00: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N7.C2.D0.R0.S11: Preamble found at Latency = 007
N1.C2.D0.R0.S14: Preamble found at Latency = 007
N3.C1.D0.R0.S06: Total Delay in PI ticks: TxDQS = 948, TxDQ = 915
N5.C3.D0.R0.S01: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N7.C2.D0.R0.S12: Preamble found at Latency = 007
N1.C2.D0.R0.S15: Preamble found at Latency = 007
N3.C1.D0.R0.S07: Total Delay in PI ticks: TxDQS = 968, TxDQ = 934
N5.C3.D0.R0.S02: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N7.C2.D0.R0.S13: Preamble found at Latency = 007
N1.C2.D0.R0.S16: Preamble found at Latency = 007
N3.C1.D0.R0.S08: Total Delay in PI ticks: TxDQS = 934, TxDQ = 900
N5.C3.D0.R0.S03: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N7.C2.D0.R0.S14: Preamble found at Latency = 007
N1.C2.D0.R0.S17: Preamble found at Latency = 007
N3.C1.D0.R0.S09: Total Delay in PI ticks: TxDQS = 995, TxDQ = 960
N5.C3.D0.R0.S04: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N7.C2.D0.R0.S15: Preamble found at Latency = 007
N1.C2.D0.R0: Preamble found for all upper nibbles, adjusting Pi, Offset to center into preamble
N3.C1.D0.R0.S10: Total Delay in PI ticks: TxDQS = 981, TxDQ = 947
N5.C3.D0.R0.S05: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N7.C2.D0.R0.S16: Preamble found at Latency = 007
N1.C2.D0.R0.S09: Total Receive Enable Delay = 1310
N3.C1.D0.R0.S11: Total Delay in PI ticks: TxDQS = 973, TxDQ = 941
N5.C3.D0.R0.S06: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N7.C2.D0.R0.S17: Preamble found at Latency = 007
N1.C2.D0.R0.S10: Total Receive Enable Delay = 1289
N3.C1.D0.R0.S12: Total Delay in PI ticks: TxDQS = 954, TxDQ = 920
N5.C3.D0.R0.S07: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N7.C2.D0.R0: Preamble found for all upper nibbles, adjusting Pi, Offset to center into preamble
N1.C2.D0.R0.S11: Total Receive Enable Delay = 1254
N3.C1.D0.R0.S13: Total Delay in PI ticks: TxDQS = 922, TxDQ = 892
N5.C3.D0.R0.S08: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N7.C2.D0.R0.S09: Total Receive Enable Delay = 1307
N1.C2.D0.R0.S12: Total Receive Enable Delay = 1235
N3.C1.D0.R0.S14: Total Delay in PI ticks: TxDQS = 934, TxDQ = 901
N5.C3.D0.R0.S02: Preamble found at Latency = 007
N7.C2.D0.R0.S10: Total Receive Enable Delay = 1285
N1.C2.D0.R0.S13: Total Receive Enable Delay = 1239
N3.C1.D0.R0.S15: Total Delay in PI ticks: TxDQS = 947, TxDQ = 913
N5.C3.D0.R0.S03: Preamble found at Latency = 007
N7.C2.D0.R0.S11: Total Receive Enable Delay = 1254
N1.C2.D0.R0.S14: Total Receive Enable Delay = 1247
N3.C1.D0.R0.S16: Total Delay in PI ticks: TxDQS = 967, TxDQ = 935
N5.C3.D0.R0.S04: Preamble found at Latency = 007
N7.C2.D0.R0.S12: Total Receive Enable Delay = 1233
N1.C2.D0.R0.S15: Total Receive Enable Delay = 1289
N3.C1.D0.R0.S17: Total Delay in PI ticks: TxDQS = 932, TxDQ = 898
N5.C3.D0.R0.S05: Preamble found at Latency = 007
N7.C2.D0.R0.S13: Total Receive Enable Delay = 1239
N1.C2.D0.R0.S16: Total Receive Enable Delay = 1306
N3.C1.D0.R1.S00: Total Delay in PI ticks: TxDQS = 995, TxDQ = 967
N5.C3.D0.R0.S08: Preamble found at Latency = 007
N7.C2.D0.R0.S14: Total Receive Enable Delay = 1250
N1.C2.D0.R0.S17: Total Receive Enable Delay = 1222
N3.C1.D0.R1.S01: Total Delay in PI ticks: TxDQS = 979, TxDQ = 945
N5.C3.D0.R0.S00: Total Receive Enable Delay = 1355
N7.C2.D0.R0.S15: Total Receive Enable Delay = 1286
N1.C2.D0.R1: RcvEnFine: Initial RdCmd2RcvEnLatency = 10, Initial RdPtrOffsetRcvEn = 4
N3.C1.D0.R1.S02: Total Delay in PI ticks: TxDQS = 972, TxDQ = 940
N5.C3.D0.R0.S01: Total Receive Enable Delay = 1335
N7.C2.D0.R0.S16: Total Receive Enable Delay = 1307
N1.C2.D0.R1.S00: Rcv En Fine Value = 383
N3.C1.D0.R1.S03: Total Delay in PI ticks: TxDQS = 952, TxDQ = 916
N5.C3.D0.R0.S02: Total Receive Enable Delay = 1305
N7.C2.D0.R0.S17: Total Receive Enable Delay = 1223
N1.C2.D0.R1.S01: Rcv En Fine Value = 358
N3.C1.D0.R1.S04: Total Delay in PI ticks: TxDQS = 923, TxDQ = 888
N5.C3.D0.R0.S03: Total Receive Enable Delay = 1282
N7.C2.D0.R1: RcvEnFine: Initial RdCmd2RcvEnLatency = 10, Initial RdPtrOffsetRcvEn = 4
N1.C2.D0.R1.S02: Rcv En Fine Value = 325
N3.C1.D0.R1.S05: Total Delay in PI ticks: TxDQS = 936, TxDQ = 900
N5.C3.D0.R0.S04: Total Receive Enable Delay = 1279
N7.C2.D0.R1.S00: Rcv En Fine Value = 380
N1.C2.D0.R1.S03: Rcv En Fine Value = 307
N3.C1.D0.R1.S06: Total Delay in PI ticks: TxDQS = 948, TxDQ = 915
N5.C3.D0.R0.S05: Total Receive Enable Delay = 1305
N7.C2.D0.R1.S01: Rcv En Fine Value = 360
N1.C2.D0.R1.S04: Rcv En Fine Value = 312
N3.C1.D0.R1.S07: Total Delay in PI ticks: TxDQS = 966, TxDQ = 932
N5.C3.D0.R0.S06: Total Receive Enable Delay = 1328
N7.C2.D0.R1.S02: Rcv En Fine Value = 324
N1.C2.D0.R1.S05: Rcv En Fine Value = 322
N3.C1.D0.R1.S08: Total Delay in PI ticks: TxDQS = 932, TxDQ = 898
N5.C3.D0.R0.S07: Total Receive Enable Delay = 1348
N7.C2.D0.R1.S03: Rcv En Fine Value = 305
N1.C2.D0.R1.S06: Rcv En Fine Value = 357
N3.C1.D0.R1.S09: Total Delay in PI ticks: TxDQS = 994, TxDQ = 960
N5.C3.D0.R0.S08: Total Receive Enable Delay = 1263
N7.C2.D0.R1.S04: Rcv En Fine Value = 310
N1.C2.D0.R1.S07: Rcv En Fine Value = 378
N3.C1.D0.R1.S10: Total Delay in PI ticks: TxDQS = 981, TxDQ = 947
N5.C3.D0.R0: Starting preamble search upper nibbles
N7.C2.D0.R1.S05: Rcv En Fine Value = 318
N1.C2.D0.R1.S08: Rcv En Fine Value = 296
N3.C1.D0.R1.S11: Total Delay in PI ticks: TxDQS = 972, TxDQ = 939
N5.C3.D0.R0.S09: PI = 042, PtrOffset = 004
N7.C2.D0.R1.S06: Rcv En Fine Value = 359
N1.C2.D0.R1.S09: Rcv En Fine Value = 381
N3.C1.D0.R1.S12: Total Delay in PI ticks: TxDQS = 954, TxDQ = 920
N5.C3.D0.R0.S10: PI = 022, PtrOffset = 004
N7.C2.D0.R1.S07: Rcv En Fine Value = 375
N1.C2.D0.R1.S10: Rcv En Fine Value = 358
N3.C1.D0.R1.S13: Total Delay in PI ticks: TxDQS = 921, TxDQ = 891
N5.C3.D0.R0.S11: PI = 060, PtrOffset = 005
N7.C2.D0.R1.S08: Rcv En Fine Value = 296
N1.C2.D0.R1.S11: Rcv En Fine Value = 322
N3.C1.D0.R1.S14: Total Delay in PI ticks: TxDQS = 935, TxDQ = 903
N5.C3.D0.R0.S12: PI = 035, PtrOffset = 005
N7.C2.D0.R1.S09: Rcv En Fine Value = 377
N1.C2.D0.R1.S12: Rcv En Fine Value = 309
N3.C1.D0.R1.S15: Total Delay in PI ticks: TxDQS = 948, TxDQ = 914
N5.C3.D0.R0.S13: PI = 030, PtrOffset = 005
N7.C2.D0.R1.S10: Rcv En Fine Value = 354
N1.C2.D0.R1.S13: Rcv En Fine Value = 311
N3.C1.D0.R1.S16: Total Delay in PI ticks: TxDQS = 966, TxDQ = 934
N5.C3.D0.R0.S14: PI = 057, PtrOffset = 005
N7.C2.D0.R1.S11: Rcv En Fine Value = 328
N1.C2.D0.R1.S14: Rcv En Fine Value = 319
N3.C1.D0.R1.S17: Total Delay in PI ticks: TxDQS = 933, TxDQ = 899
N5.C3.D0.R0.S15: PI = 018, PtrOffset = 004
N7.C2.D0.R1.S12: Rcv En Fine Value = 305
N1.C2.D0.R1.S15: Rcv En Fine Value = 360
N3.C2.D0.R0: Write Training Coarse, lower nibbles / bytes
N5.C3.D0.R0.S16: PI = 040, PtrOffset = 004
N7.C2.D0.R1.S13: Rcv En Fine Value = 310
N1.C2.D0.R1.S16: Rcv En Fine Value = 381
N3.C2.D0.R0.S00: Dq Delay estimate: 444
N5.C3.D0.R0.S17: PI = 017, PtrOffset = 005
N7.C2.D0.R1.S14: Rcv En Fine Value = 319
N1.C2.D0.R1.S17: Rcv En Fine Value = 292
N3.C2.D0.R0.S01: Dq Delay estimate: 426
N5.C3.D0.R0.S09: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N7.C2.D0.R1.S15: Rcv En Fine Value = 363
N1.C2.D0.R1: Starting preamble search lower nibbles
N3.C2.D0.R0.S02: Dq Delay estimate: 415
N5.C3.D0.R0.S10: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N7.C2.D0.R1.S16: Rcv En Fine Value = 379
N1.C2.D0.R1.S00: PI = 063, PtrOffset = 005
N3.C2.D0.R0.S03: Dq Delay estimate: 396
N5.C3.D0.R0.S11: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N7.C2.D0.R1.S17: Rcv En Fine Value = 294
N1.C2.D0.R1.S01: PI = 038, PtrOffset = 005
N3.C2.D0.R0.S04: Dq Delay estimate: 361
N5.C3.D0.R0.S12: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N7.C2.D0.R1: Starting preamble search lower nibbles
N1.C2.D0.R1.S02: PI = 005, PtrOffset = 005
N3.C2.D0.R0.S05: Dq Delay estimate: 386
N5.C3.D0.R0.S13: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N7.C2.D0.R1.S00: PI = 060, PtrOffset = 005
N1.C2.D0.R1.S03: PI = 051, PtrOffset = 004
N3.C2.D0.R0.S06: Dq Delay estimate: 387
N5.C3.D0.R0.S14: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N7.C2.D0.R1.S01: PI = 040, PtrOffset = 005
N1.C2.D0.R1.S04: PI = 056, PtrOffset = 004
N3.C2.D0.R0.S07: Dq Delay estimate: 409
N5.C3.D0.R0.S15: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N7.C2.D0.R1.S02: PI = 004, PtrOffset = 005
N1.C2.D0.R1.S05: PI = 002, PtrOffset = 005
N3.C2.D0.R0.S08: Dq Delay estimate: 372
N5.C3.D0.R0.S16: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N7.C2.D0.R1.S03: PI = 049, PtrOffset = 004
N1.C2.D0.R1.S06: PI = 037, PtrOffset = 005
ACCM: 0F BF0F9F0F 9F0F0F0F
N5.C3.D0.R0.S17: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N7.C2.D0.R1.S04: PI = 054, PtrOffset = 004
N1.C2.D0.R1.S07: PI = 058, PtrOffset = 005
ACCM: 0F BF0F9F0F 9F0F0F0F
N5.C3.D0.R0.S09: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N7.C2.D0.R1.S05: PI = 062, PtrOffset = 004
N1.C2.D0.R1.S08: PI = 040, PtrOffset = 004
ACCM: 0F BF0F9F0F 9FFFFFFF
N5.C3.D0.R0.S10: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N7.C2.D0.R1.S06: PI = 039, PtrOffset = 005
N1.C2.D0.R1.S00: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
ACCM: 0F BF0F9F0F 9FFFFFFF
N5.C3.D0.R0.S11: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N7.C2.D0.R1.S07: PI = 055, PtrOffset = 005
N1.C2.D0.R1.S01: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N3.C2.D0.R0: CheckMCTest: result = 0x15FFF
N5.C3.D0.R0.S12: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N7.C2.D0.R1.S08: PI = 040, PtrOffset = 004
N1.C2.D0.R1.S02: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
ACCM: 0F FF0FDF0F DF0F0F0F
N5.C3.D0.R0.S13: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N7.C2.D0.R1.S00: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N1.C2.D0.R1.S03: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
ACCM: 0F FF0FDF0F DF0F0F0F
N5.C3.D0.R0.S14: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N7.C2.D0.R1.S01: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N1.C2.D0.R1.S04: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
ACCM: 0F FF0FDF0F DFFFFFFF
N5.C3.D0.R0.S15: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N7.C2.D0.R1.S02: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N1.C2.D0.R1.S05: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
ACCM: 0F FF0FDF0F DFFFFFFF
N5.C3.D0.R0.S16: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N7.C2.D0.R1.S03: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N1.C2.D0.R1.S06: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N3.C2.D0.R0: CheckMCTest: result = 0x15FFF
N5.C3.D0.R0.S17: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N7.C2.D0.R1.S04: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N1.C2.D0.R1.S07: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
ACCM: 0F DF0FDF0F DF0F0F0F
N5.C3.D0.R0.S09: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N7.C2.D0.R1.S05: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N1.C2.D0.R1.S08: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
ACCM: 0F DF0FDF0F DF0F0F0F
N5.C3.D0.R0.S10: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N7.C2.D0.R1.S06: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N1.C2.D0.R1.S00: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
ACCM: 00 D000D000 D0F0F0F0
N5.C3.D0.R0.S11: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N7.C2.D0.R1.S07: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N1.C2.D0.R1.S01: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
ACCM: 00 D000D000 D0F0F0F0
N5.C3.D0.R0.S12: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N7.C2.D0.R1.S08: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N1.C2.D0.R1.S02: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N3.C2.D0.R0: CheckMCTest: result = 0x15FFF
N5.C3.D0.R0.S13: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N7.C2.D0.R1.S00: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N1.C2.D0.R1.S03: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
ACCM: 0F DF0FDF0F DF0F0F0F
N5.C3.D0.R0.S14: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N7.C2.D0.R1.S01: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N1.C2.D0.R1.S04: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
ACCM: 0F DF0FDF0F DF0F0F0F
N5.C3.D0.R0.S15: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N7.C2.D0.R1.S02: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N1.C2.D0.R1.S05: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
ACCM: 00 D000D000 D0F0F0F0
N5.C3.D0.R0.S16: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N7.C2.D0.R1.S03: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N1.C2.D0.R1.S06: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
ACCM: 00 D000D000 D0F0F0F0
N5.C3.D0.R0.S17: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N7.C2.D0.R1.S04: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N1.C2.D0.R1.S07: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N3.C2.D0.R0: CheckMCTest: result = 0x15FFF
N5.C3.D0.R0.S09: Preamble found at Latency = 008
N7.C2.D0.R1.S05: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N1.C2.D0.R1.S08: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
ACCM: 00 F000D000 D0000000
N5.C3.D0.R0.S10: Preamble found at Latency = 008
N7.C2.D0.R1.S06: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N1.C2.D0.R1.S00: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
ACCM: 00 F000D000 D0000000
N5.C3.D0.R0.S15: Preamble found at Latency = 008
N7.C2.D0.R1.S07: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N1.C2.D0.R1.S01: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
ACCM: 00 F000D000 D0F0F0F0
N5.C3.D0.R0.S16: Preamble found at Latency = 008
N7.C2.D0.R1.S08: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N1.C2.D0.R1.S02: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
ACCM: 00 F000D000 D0F0F0F0
N5.C3.D0.R0.S09: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N7.C2.D0.R1.S00: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N1.C2.D0.R1.S03: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N3.C2.D0.R0: CheckMCTest: result = 0x15E00
N5.C3.D0.R0.S10: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N7.C2.D0.R1.S01: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N1.C2.D0.R1.S04: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
ACCM: 00 F000D000 D0000000
N5.C3.D0.R0.S11: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N7.C2.D0.R1.S02: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N1.C2.D0.R1.S05: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
ACCM: 00 F000D000 D0000000
N5.C3.D0.R0.S12: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N7.C2.D0.R1.S03: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N1.C2.D0.R1.S06: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
ACCM: 00 F000D000 D0F0F0F0
N5.C3.D0.R0.S13: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N7.C2.D0.R1.S04: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N1.C2.D0.R1.S07: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
ACCM: 00 F000D000 D0F0F0F0
N5.C3.D0.R0.S14: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N7.C2.D0.R1.S05: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N1.C2.D0.R1.S08: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N3.C2.D0.R0: CheckMCTest: result = 0x15E00
N5.C3.D0.R0.S15: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N7.C2.D0.R1.S06: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N1.C2.D0.R1.S00: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N3.C2.D0.R0.S00: Offset Found: RdPtrOffsetDqs = 007
N5.C3.D0.R0.S16: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N7.C2.D0.R1.S07: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N1.C2.D0.R1.S01: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N3.C2.D0.R0.S01: Offset Found: RdPtrOffsetDqs = 007
N5.C3.D0.R0.S17: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N7.C2.D0.R1.S08: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N1.C2.D0.R1.S02: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N3.C2.D0.R0.S02: Offset Found: RdPtrOffsetDqs = 007
N5.C3.D0.R0.S11: Preamble found at Latency = 007
N7.C2.D0.R1.S00: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N1.C2.D0.R1.S03: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N3.C2.D0.R0.S03: Offset Found: RdPtrOffsetDqs = 006
N5.C3.D0.R0.S12: Preamble found at Latency = 007
N7.C2.D0.R1.S01: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N1.C2.D0.R1.S04: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N3.C2.D0.R0.S04: Offset Found: RdPtrOffsetDqs = 006
N5.C3.D0.R0.S13: Preamble found at Latency = 007
N7.C2.D0.R1.S02: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N1.C2.D0.R1.S05: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N3.C2.D0.R0.S05: Offset Found: RdPtrOffsetDqs = 006
N5.C3.D0.R0.S14: Preamble found at Latency = 007
N7.C2.D0.R1.S03: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N1.C2.D0.R1.S06: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N3.C2.D0.R0.S06: Offset Found: RdPtrOffsetDqs = 006
N5.C3.D0.R0.S17: Preamble found at Latency = 007
N7.C2.D0.R1.S04: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N1.C2.D0.R1.S07: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N3.C2.D0.R0.S07: Offset Found: RdPtrOffsetDqs = 006
N5.C3.D0.R0: Preamble found for all upper nibbles, adjusting Pi, Offset to center into preamble
N7.C2.D0.R1.S05: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N1.C2.D0.R1.S08: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N3.C2.D0.R0.S08: Offset Found: RdPtrOffsetDqs = 006
N5.C3.D0.R0.S09: Total Receive Enable Delay = 1354
N7.C2.D0.R1.S06: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N1.C2.D0.R1.S00: Preamble found at Latency = 007
N3.C2.D0.R0: Write Training Coarse, upper nibbles
N5.C3.D0.R0.S10: Total Receive Enable Delay = 1334
N7.C2.D0.R1.S07: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N1.C2.D0.R1.S01: Preamble found at Latency = 007
N3.C2.D0.R0.S09: Dq Delay estimate: 441
N5.C3.D0.R0.S11: Total Receive Enable Delay = 1308
N7.C2.D0.R1.S08: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N1.C2.D0.R1.S02: Preamble found at Latency = 007
N3.C2.D0.R0.S10: Dq Delay estimate: 427
N5.C3.D0.R0.S12: Total Receive Enable Delay = 1283
N7.C2.D0.R1.S00: Preamble found at Latency = 007
N1.C2.D0.R1.S03: Preamble found at Latency = 007
N3.C2.D0.R0.S11: Dq Delay estimate: 420
N5.C3.D0.R0.S13: Total Receive Enable Delay = 1278
N7.C2.D0.R1.S01: Preamble found at Latency = 007
N1.C2.D0.R1.S04: Preamble found at Latency = 007
N3.C2.D0.R0.S12: Dq Delay estimate: 399
N5.C3.D0.R0.S14: Total Receive Enable Delay = 1305
N7.C2.D0.R1.S02: Preamble found at Latency = 007
N1.C2.D0.R1.S05: Preamble found at Latency = 007
N3.C2.D0.R0.S13: Dq Delay estimate: 359
N5.C3.D0.R0.S15: Total Receive Enable Delay = 1330
N7.C2.D0.R1.S03: Preamble found at Latency = 007
N1.C2.D0.R1.S06: Preamble found at Latency = 007
N3.C2.D0.R0.S14: Dq Delay estimate: 385
N5.C3.D0.R0.S16: Total Receive Enable Delay = 1352
N7.C2.D0.R1.S04: Preamble found at Latency = 007
N1.C2.D0.R1.S07: Preamble found at Latency = 007
N3.C2.D0.R0.S15: Dq Delay estimate: 388
N5.C3.D0.R0.S17: Total Receive Enable Delay = 1265
N7.C2.D0.R1.S05: Preamble found at Latency = 007
N1.C2.D0.R1.S08: Preamble found at Latency = 007
N3.C2.D0.R0.S16: Dq Delay estimate: 413
N5.C3.D0.R1: RcvEnFine: Initial RdCmd2RcvEnLatency = 10, Initial RdPtrOffsetRcvEn = 4
N7.C2.D0.R1.S06: Preamble found at Latency = 007
N1.C2.D0.R1.S00: Total Receive Enable Delay = 1311
N3.C2.D0.R0.S17: Dq Delay estimate: 374
N5.C3.D0.R1.S00: Rcv En Fine Value = 300
N7.C2.D0.R1.S07: Preamble found at Latency = 007
N1.C2.D0.R1.S01: Total Receive Enable Delay = 1286
ACCM: F0 F0F0F0F0 F0F0F0F0
N5.C3.D0.R1.S01: Rcv En Fine Value = 278
N7.C2.D0.R1.S08: Preamble found at Latency = 007
N1.C2.D0.R1.S02: Total Receive Enable Delay = 1253
ACCM: F0 F0F0F0F0 F0F0F0F0
N5.C3.D0.R1.S02: Rcv En Fine Value = 377
N7.C2.D0.R1.S00: Total Receive Enable Delay = 1308
N1.C2.D0.R1.S03: Total Receive Enable Delay = 1235
ACCM: F0 F0F0F0F0 F0F0F0F0
N5.C3.D0.R1.S03: Rcv En Fine Value = 355
N7.C2.D0.R1.S01: Total Receive Enable Delay = 1288
N1.C2.D0.R1.S04: Total Receive Enable Delay = 1240
ACCM: F0 F0F0F0F0 F0F0F0F0
N5.C3.D0.R1.S04: Rcv En Fine Value = 352
N7.C2.D0.R1.S02: Total Receive Enable Delay = 1252
N1.C2.D0.R1.S05: Total Receive Enable Delay = 1250
N3.C2.D0.R0: CheckMCTest: result = 0x3FE00
N5.C3.D0.R1.S05: Rcv En Fine Value = 378
N7.C2.D0.R1.S03: Total Receive Enable Delay = 1233
N1.C2.D0.R1.S06: Total Receive Enable Delay = 1285
ACCM: F0 F0F0F0F0 F0F0F0F0
N5.C3.D0.R1.S06: Rcv En Fine Value = 270
N7.C2.D0.R1.S04: Total Receive Enable Delay = 1238
N1.C2.D0.R1.S07: Total Receive Enable Delay = 1306
ACCM: F0 F0F0F0F0 F0F0F0F0
N5.C3.D0.R1.S07: Rcv En Fine Value = 292
N7.C2.D0.R1.S05: Total Receive Enable Delay = 1246
N1.C2.D0.R1.S08: Total Receive Enable Delay = 1224
ACCM: F0 F0F0F0F0 F0F0F0F0
N5.C3.D0.R1.S08: Rcv En Fine Value = 336
N7.C2.D0.R1.S06: Total Receive Enable Delay = 1287
N1.C2.D0.R1: Starting preamble search upper nibbles
ACCM: F0 F0F0F0F0 F0F0F0F0
N5.C3.D0.R1.S09: Rcv En Fine Value = 297
N7.C2.D0.R1.S07: Total Receive Enable Delay = 1303
N1.C2.D0.R1.S09: PI = 061, PtrOffset = 005
N3.C2.D0.R0: CheckMCTest: result = 0x3FE00
N5.C3.D0.R1.S10: Rcv En Fine Value = 281
N7.C2.D0.R1.S08: Total Receive Enable Delay = 1224
N1.C2.D0.R1.S10: PI = 038, PtrOffset = 005
ACCM: F0 F0F0F0F0 F0F0F0F0
N5.C3.D0.R1.S11: Rcv En Fine Value = 379
N7.C2.D0.R1: Starting preamble search upper nibbles
N1.C2.D0.R1.S11: PI = 002, PtrOffset = 005
ACCM: F0 F0F0F0F0 F0F0F0F0
N5.C3.D0.R1.S12: Rcv En Fine Value = 356
N7.C2.D0.R1.S09: PI = 057, PtrOffset = 005
N1.C2.D0.R1.S12: PI = 053, PtrOffset = 004
ACCM: 00 00000000 00000000
N5.C3.D0.R1.S13: Rcv En Fine Value = 353
N7.C2.D0.R1.S10: PI = 034, PtrOffset = 005
N1.C2.D0.R1.S13: PI = 055, PtrOffset = 004
ACCM: 00 00000000 00000000
N5.C3.D0.R1.S14: Rcv En Fine Value = 378
N7.C2.D0.R1.S11: PI = 008, PtrOffset = 005
N1.C2.D0.R1.S14: PI = 063, PtrOffset = 004
N3.C2.D0.R0: CheckMCTest: result = 0x3FE00
N5.C3.D0.R1.S15: Rcv En Fine Value = 271
N7.C2.D0.R1.S12: PI = 049, PtrOffset = 004
N1.C2.D0.R1.S15: PI = 040, PtrOffset = 005
ACCM: F0 F0F0F0F0 F0F0F0F0
N5.C3.D0.R1.S16: Rcv En Fine Value = 294
N7.C2.D0.R1.S13: PI = 054, PtrOffset = 004
N1.C2.D0.R1.S16: PI = 061, PtrOffset = 005
ACCM: F0 F0F0F0F0 F0F0F0F0
N5.C3.D0.R1.S17: Rcv En Fine Value = 338
N7.C2.D0.R1.S14: PI = 063, PtrOffset = 004
N1.C2.D0.R1.S17: PI = 036, PtrOffset = 004
ACCM: 00 00000000 00000000
N5.C3.D0.R1: Starting preamble search lower nibbles
N7.C2.D0.R1.S15: PI = 043, PtrOffset = 005
N1.C2.D0.R1.S09: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
ACCM: 00 00000000 00000000
N5.C3.D0.R1.S00: PI = 044, PtrOffset = 004
N7.C2.D0.R1.S16: PI = 059, PtrOffset = 005
N1.C2.D0.R1.S10: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N3.C2.D0.R0: CheckMCTest: result = 0x3FE00
N5.C3.D0.R1.S01: PI = 022, PtrOffset = 004
N7.C2.D0.R1.S17: PI = 038, PtrOffset = 004
N1.C2.D0.R1.S11: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N3.C2.D0.R0: CheckMCTest: passed
N5.C3.D0.R1.S02: PI = 057, PtrOffset = 005
N7.C2.D0.R1.S09: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N1.C2.D0.R1.S12: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N3.C2.D0.R0: CheckMCTest: passed
N5.C3.D0.R1.S03: PI = 035, PtrOffset = 005
N7.C2.D0.R1.S10: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N1.C2.D0.R1.S13: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N3.C2.D0.R0.S09: Offset Found: RdPtrOffsetDqs = 007
N5.C3.D0.R1.S04: PI = 032, PtrOffset = 005
N7.C2.D0.R1.S11: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N1.C2.D0.R1.S14: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N3.C2.D0.R0.S10: Offset Found: RdPtrOffsetDqs = 007
N5.C3.D0.R1.S05: PI = 058, PtrOffset = 005
N7.C2.D0.R1.S12: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N1.C2.D0.R1.S15: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N3.C2.D0.R0.S11: Offset Found: RdPtrOffsetDqs = 007
N5.C3.D0.R1.S06: PI = 014, PtrOffset = 004
N7.C2.D0.R1.S13: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N1.C2.D0.R1.S16: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N3.C2.D0.R0.S12: Offset Found: RdPtrOffsetDqs = 006
N5.C3.D0.R1.S07: PI = 036, PtrOffset = 004
N7.C2.D0.R1.S14: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N1.C2.D0.R1.S17: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N3.C2.D0.R0.S13: Offset Found: RdPtrOffsetDqs = 006
N5.C3.D0.R1.S08: PI = 016, PtrOffset = 005
N7.C2.D0.R1.S15: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N1.C2.D0.R1.S09: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N3.C2.D0.R0.S14: Offset Found: RdPtrOffsetDqs = 006
N5.C3.D0.R1.S00: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N7.C2.D0.R1.S16: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N1.C2.D0.R1.S10: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N3.C2.D0.R0.S15: Offset Found: RdPtrOffsetDqs = 006
N5.C3.D0.R1.S01: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N7.C2.D0.R1.S17: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N1.C2.D0.R1.S11: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N3.C2.D0.R0.S16: Offset Found: RdPtrOffsetDqs = 006
N5.C3.D0.R1.S02: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N7.C2.D0.R1.S09: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N1.C2.D0.R1.S12: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N3.C2.D0.R0.S17: Offset Found: RdPtrOffsetDqs = 006
N5.C3.D0.R1.S03: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N7.C2.D0.R1.S10: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N1.C2.D0.R1.S13: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N3.C2.D0.R1: Write Training Coarse, lower nibbles / bytes
N5.C3.D0.R1.S04: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N7.C2.D0.R1.S11: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N1.C2.D0.R1.S14: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N3.C2.D0.R1.S00: Dq Delay estimate: 444
N5.C3.D0.R1.S05: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N7.C2.D0.R1.S12: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N1.C2.D0.R1.S15: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N3.C2.D0.R1.S01: Dq Delay estimate: 424
N5.C3.D0.R1.S06: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N7.C2.D0.R1.S13: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N1.C2.D0.R1.S16: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N3.C2.D0.R1.S02: Dq Delay estimate: 415
N5.C3.D0.R1.S07: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N7.C2.D0.R1.S14: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N1.C2.D0.R1.S17: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N3.C2.D0.R1.S03: Dq Delay estimate: 397
N5.C3.D0.R1.S08: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N7.C2.D0.R1.S15: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N1.C2.D0.R1.S09: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N3.C2.D0.R1.S04: Dq Delay estimate: 359
N5.C3.D0.R1.S00: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N7.C2.D0.R1.S16: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N1.C2.D0.R1.S10: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N3.C2.D0.R1.S05: Dq Delay estimate: 388
N5.C3.D0.R1.S01: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N7.C2.D0.R1.S17: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N1.C2.D0.R1.S11: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N3.C2.D0.R1.S06: Dq Delay estimate: 388
N5.C3.D0.R1.S02: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N7.C2.D0.R1.S09: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N1.C2.D0.R1.S12: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N3.C2.D0.R1.S07: Dq Delay estimate: 409
N5.C3.D0.R1.S03: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N7.C2.D0.R1.S10: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N1.C2.D0.R1.S13: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N3.C2.D0.R1.S08: Dq Delay estimate: 372
N5.C3.D0.R1.S04: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N7.C2.D0.R1.S11: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N1.C2.D0.R1.S14: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
ACCM: 0F 0F0F0F0F 0F0F0F0F
N5.C3.D0.R1.S05: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N7.C2.D0.R1.S12: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N1.C2.D0.R1.S15: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
ACCM: 0F 0F0F0F0F 0F0F0F0F
N5.C3.D0.R1.S06: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N7.C2.D0.R1.S13: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N1.C2.D0.R1.S16: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
ACCM: 0F 0F0F0F0F 0F0F0F0F
N5.C3.D0.R1.S07: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N7.C2.D0.R1.S14: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N1.C2.D0.R1.S17: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
ACCM: 0F 0F0F0F0F 0F0F0F0F
N5.C3.D0.R1.S08: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N7.C2.D0.R1.S15: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N1.C2.D0.R1.S09: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N3.C2.D0.R1: CheckMCTest: result = 0x1FF
N5.C3.D0.R1.S00: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N7.C2.D0.R1.S16: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N1.C2.D0.R1.S10: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
ACCM: 0F 0F0F0F0F 0F0F0F0F
N5.C3.D0.R1.S01: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N7.C2.D0.R1.S17: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N1.C2.D0.R1.S11: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
ACCM: 0F 0F0F0F0F 0F0F0F0F
N5.C3.D0.R1.S02: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N7.C2.D0.R1.S09: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N1.C2.D0.R1.S12: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
ACCM: 0F 0F0F0F0F 0F0F0F0F
N5.C3.D0.R1.S03: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N7.C2.D0.R1.S10: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N1.C2.D0.R1.S13: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
ACCM: 0F 0F0F0F0F 0F0F0F0F
N5.C3.D0.R1.S04: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N7.C2.D0.R1.S11: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N1.C2.D0.R1.S14: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N3.C2.D0.R1: CheckMCTest: result = 0x1FF
N5.C3.D0.R1.S05: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N7.C2.D0.R1.S12: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N1.C2.D0.R1.S15: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
ACCM: 0F 0F0F0F0F 0F0F0F0F
N5.C3.D0.R1.S06: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N7.C2.D0.R1.S13: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N1.C2.D0.R1.S16: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
ACCM: 0F 0F0F0F0F 0F0F0F0F
N5.C3.D0.R1.S07: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N7.C2.D0.R1.S14: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N1.C2.D0.R1.S17: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
ACCM: 00 00000000 00000000
N5.C3.D0.R1.S08: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N7.C2.D0.R1.S15: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N1.C2.D0.R1.S09: Preamble found at Latency = 007
ACCM: 00 00000000 00000000
N5.C3.D0.R1.S00: Preamble found at Latency = 008
N7.C2.D0.R1.S16: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N1.C2.D0.R1.S10: Preamble found at Latency = 007
N3.C2.D0.R1: CheckMCTest: result = 0x1FF
N5.C3.D0.R1.S01: Preamble found at Latency = 008
N7.C2.D0.R1.S17: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N1.C2.D0.R1.S11: Preamble found at Latency = 007
ACCM: 0F 0F0F0F0F 0F0F0F0F
N5.C3.D0.R1.S06: Preamble found at Latency = 008
N7.C2.D0.R1.S09: Preamble found at Latency = 007
N1.C2.D0.R1.S12: Preamble found at Latency = 007
ACCM: 0F 0F0F0F0F 0F0F0F0F
N5.C3.D0.R1.S07: Preamble found at Latency = 008
N7.C2.D0.R1.S10: Preamble found at Latency = 007
N1.C2.D0.R1.S13: Preamble found at Latency = 007
ACCM: 00 00000000 00000000
N5.C3.D0.R1.S00: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N7.C2.D0.R1.S11: Preamble found at Latency = 007
N1.C2.D0.R1.S14: Preamble found at Latency = 007
ACCM: 00 00000000 00000000
N5.C3.D0.R1.S01: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N7.C2.D0.R1.S12: Preamble found at Latency = 007
N1.C2.D0.R1.S15: Preamble found at Latency = 007
N3.C2.D0.R1: CheckMCTest: result = 0x1FF
N5.C3.D0.R1.S02: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N7.C2.D0.R1.S13: Preamble found at Latency = 007
N1.C2.D0.R1.S16: Preamble found at Latency = 007
N3.C2.D0.R1: CheckMCTest: passed
N5.C3.D0.R1.S03: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N7.C2.D0.R1.S14: Preamble found at Latency = 007
N1.C2.D0.R1.S17: Preamble found at Latency = 007
N3.C2.D0.R1: CheckMCTest: passed
N5.C3.D0.R1.S04: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N7.C2.D0.R1.S15: Preamble found at Latency = 007
N1.C2.D0.R1: Preamble found for all upper nibbles, adjusting Pi, Offset to center into preamble
N3.C2.D0.R1.S00: Offset Found: RdPtrOffsetDqs = 007
N5.C3.D0.R1.S05: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N7.C2.D0.R1.S16: Preamble found at Latency = 007
N1.C2.D0.R1.S09: Total Receive Enable Delay = 1309
N3.C2.D0.R1.S01: Offset Found: RdPtrOffsetDqs = 007
N5.C3.D0.R1.S06: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N7.C2.D0.R1.S17: Preamble found at Latency = 007
N1.C2.D0.R1.S10: Total Receive Enable Delay = 1286
N3.C2.D0.R1.S02: Offset Found: RdPtrOffsetDqs = 007
N5.C3.D0.R1.S07: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N7.C2.D0.R1: Preamble found for all upper nibbles, adjusting Pi, Offset to center into preamble
N1.C2.D0.R1.S11: Total Receive Enable Delay = 1250
N3.C2.D0.R1.S03: Offset Found: RdPtrOffsetDqs = 006
N5.C3.D0.R1.S08: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N7.C2.D0.R1.S09: Total Receive Enable Delay = 1305
N1.C2.D0.R1.S12: Total Receive Enable Delay = 1237
N3.C2.D0.R1.S04: Offset Found: RdPtrOffsetDqs = 006
N5.C3.D0.R1.S02: Preamble found at Latency = 007
N7.C2.D0.R1.S10: Total Receive Enable Delay = 1282
N1.C2.D0.R1.S13: Total Receive Enable Delay = 1239
N3.C2.D0.R1.S05: Offset Found: RdPtrOffsetDqs = 006
N5.C3.D0.R1.S03: Preamble found at Latency = 007
N7.C2.D0.R1.S11: Total Receive Enable Delay = 1256
N1.C2.D0.R1.S14: Total Receive Enable Delay = 1247
N3.C2.D0.R1.S06: Offset Found: RdPtrOffsetDqs = 006
N5.C3.D0.R1.S04: Preamble found at Latency = 007
N7.C2.D0.R1.S12: Total Receive Enable Delay = 1233
N1.C2.D0.R1.S15: Total Receive Enable Delay = 1288
N3.C2.D0.R1.S07: Offset Found: RdPtrOffsetDqs = 006
N5.C3.D0.R1.S05: Preamble found at Latency = 007
N7.C2.D0.R1.S13: Total Receive Enable Delay = 1238
N1.C2.D0.R1.S16: Total Receive Enable Delay = 1309
N3.C2.D0.R1.S08: Offset Found: RdPtrOffsetDqs = 006
N5.C3.D0.R1.S08: Preamble found at Latency = 007
N7.C2.D0.R1.S14: Total Receive Enable Delay = 1247
N1.C2.D0.R1.S17: Total Receive Enable Delay = 1220
N3.C2.D0.R1: Write Training Coarse, upper nibbles
N5.C3.D0.R1.S00: Total Receive Enable Delay = 1356
N7.C2.D0.R1.S15: Total Receive Enable Delay = 1291
START_DATA_REC_EN
N3.C2.D0.R1.S09: Dq Delay estimate: 441
N5.C3.D0.R1.S01: Total Receive Enable Delay = 1334
N7.C2.D0.R1.S16: Total Receive Enable Delay = 1307
N1.C2.S00: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N3.C2.D0.R1.S10: Dq Delay estimate: 427
N5.C3.D0.R1.S02: Total Receive Enable Delay = 1305
N7.C2.D0.R1.S17: Total Receive Enable Delay = 1222
N1.C2.S01: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N3.C2.D0.R1.S11: Dq Delay estimate: 417
N5.C3.D0.R1.S03: Total Receive Enable Delay = 1283
START_DATA_REC_EN
N1.C2.S02: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 5
N3.C2.D0.R1.S12: Dq Delay estimate: 399
N5.C3.D0.R1.S04: Total Receive Enable Delay = 1280
N7.C2.S00: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N1.C2.S03: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 5
N3.C2.D0.R1.S13: Dq Delay estimate: 359
N5.C3.D0.R1.S05: Total Receive Enable Delay = 1306
N7.C2.S01: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N1.C2.S04: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 5
N3.C2.D0.R1.S14: Dq Delay estimate: 385
N5.C3.D0.R1.S06: Total Receive Enable Delay = 1326
N7.C2.S02: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 5
N1.C2.S05: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 5
N3.C2.D0.R1.S15: Dq Delay estimate: 389
N5.C3.D0.R1.S07: Total Receive Enable Delay = 1348
N7.C2.S03: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 5
N1.C2.S06: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N3.C2.D0.R1.S16: Dq Delay estimate: 415
N5.C3.D0.R1.S08: Total Receive Enable Delay = 1264
N7.C2.S04: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 5
N1.C2.S07: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N3.C2.D0.R1.S17: Dq Delay estimate: 373
N5.C3.D0.R1: Starting preamble search upper nibbles
N7.C2.S05: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 5
N1.C2.S08: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 5
ACCM: F0 F0F0F0F0 F0F0F0F0
N5.C3.D0.R1.S09: PI = 041, PtrOffset = 004
N7.C2.S06: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N1.C2.S09: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
ACCM: F0 F0F0F0F0 F0F0F0F0
N5.C3.D0.R1.S10: PI = 025, PtrOffset = 004
N7.C2.S07: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N1.C2.S10: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
ACCM: F0 F0F0F0F0 F0F0F0F0
N5.C3.D0.R1.S11: PI = 059, PtrOffset = 005
N7.C2.S08: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 5
N1.C2.S11: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 5
ACCM: F0 F0F0F0F0 F0F0F0F0
N5.C3.D0.R1.S12: PI = 036, PtrOffset = 005
N7.C2.S09: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N1.C2.S12: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 5
N3.C2.D0.R1: CheckMCTest: result = 0x3FE00
N5.C3.D0.R1.S13: PI = 033, PtrOffset = 005
N7.C2.S10: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N1.C2.S13: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 5
ACCM: F0 F0F0F0F0 F0F0F0F0
N5.C3.D0.R1.S14: PI = 058, PtrOffset = 005
N7.C2.S11: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 5
N1.C2.S14: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 5
ACCM: F0 F0F0F0F0 F0F0F0F0
N5.C3.D0.R1.S15: PI = 015, PtrOffset = 004
N7.C2.S12: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 5
N1.C2.S15: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
ACCM: F0 F0F0F0F0 F0F0F0F0
N5.C3.D0.R1.S16: PI = 038, PtrOffset = 004
N7.C2.S13: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 5
N1.C2.S16: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
ACCM: F0 F0F0F0F0 F0F0F0F0
N5.C3.D0.R1.S17: PI = 018, PtrOffset = 005
N7.C2.S14: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 5
N1.C2.S17: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 5
N3.C2.D0.R1: CheckMCTest: result = 0x3FE00
N5.C3.D0.R1.S09: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N7.C2.S15: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N1.C2.D0.R0.S00: RcvEn: plus1 = 1, minus1 = 0, PI = 32, DB = 0
ACCM: F0 F0F0F0F0 F0F0F0F0
N5.C3.D0.R1.S10: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N7.C2.S16: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N1.C2.D0.R0.S01: RcvEn: plus1 = 1, minus1 = 0, PI = 06, DB = 1
ACCM: F0 F0F0F0F0 F0F0F0F0
N5.C3.D0.R1.S11: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N7.C2.S17: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 5
N1.C2.D0.R0.S02: RcvEn: plus1 = 1, minus1 = 0, PI = 38, DB = 0
ACCM: 00 B0000000 00000000
N5.C3.D0.R1.S12: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N7.C2.D0.R0.S00: RcvEn: plus1 = 1, minus1 = 0, PI = 28, DB = 0
N1.C2.D0.R0.S03: RcvEn: plus1 = 1, minus1 = 0, PI = 19, DB = 0
ACCM: 00 B0000000 00000000
N5.C3.D0.R1.S13: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N7.C2.D0.R0.S01: RcvEn: plus1 = 1, minus1 = 0, PI = 07, DB = 1
N1.C2.D0.R0.S04: RcvEn: plus1 = 1, minus1 = 0, PI = 26, DB = 0
N3.C2.D0.R1: CheckMCTest: result = 0x3FE00
N5.C3.D0.R1.S14: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N7.C2.D0.R0.S02: RcvEn: plus1 = 1, minus1 = 0, PI = 37, DB = 0
N1.C2.D0.R0.S05: RcvEn: plus1 = 1, minus1 = 0, PI = 34, DB = 0
ACCM: F0 F0F0F0F0 F0F0F0F0
N5.C3.D0.R1.S15: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N7.C2.D0.R0.S03: RcvEn: plus1 = 1, minus1 = 0, PI = 16, DB = 0
N1.C2.D0.R0.S06: RcvEn: plus1 = 1, minus1 = 0, PI = 07, DB = 1
ACCM: F0 F0F0F0F0 F0F0F0F0
N5.C3.D0.R1.S16: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N7.C2.D0.R0.S04: RcvEn: plus1 = 1, minus1 = 0, PI = 20, DB = 0
N1.C2.D0.R0.S07: RcvEn: plus1 = 1, minus1 = 0, PI = 25, DB = 0
ACCM: 00 F0000000 00000000
N5.C3.D0.R1.S17: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N7.C2.D0.R0.S05: RcvEn: plus1 = 1, minus1 = 0, PI = 31, DB = 0
N1.C2.D0.R0.S08: RcvEn: plus1 = 1, minus1 = 0, PI = 08, DB = 1
ACCM: 00 F0000000 00000000
N5.C3.D0.R1.S09: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N7.C2.D0.R0.S06: RcvEn: plus1 = 1, minus1 = 0, PI = 06, DB = 1
N1.C2.D0.R0.S09: RcvEn: plus1 = 1, minus1 = 0, PI = 29, DB = 0
N3.C2.D0.R1: CheckMCTest: result = 0x3FE00
N5.C3.D0.R1.S10: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N7.C2.D0.R0.S07: RcvEn: plus1 = 1, minus1 = 0, PI = 24, DB = 0
N1.C2.D0.R0.S10: RcvEn: plus1 = 1, minus1 = 0, PI = 07, DB = 1
N3.C2.D0.R1: CheckMCTest: passed
N5.C3.D0.R1.S11: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N7.C2.D0.R0.S08: RcvEn: plus1 = 1, minus1 = 0, PI = 08, DB = 1
N1.C2.D0.R0.S11: RcvEn: plus1 = 1, minus1 = 0, PI = 36, DB = 0
N3.C2.D0.R1: CheckMCTest: passed
N5.C3.D0.R1.S12: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N7.C2.D0.R0.S09: RcvEn: plus1 = 1, minus1 = 0, PI = 26, DB = 0
N1.C2.D0.R0.S12: RcvEn: plus1 = 1, minus1 = 0, PI = 20, DB = 0
N3.C2.D0.R1.S09: Offset Found: RdPtrOffsetDqs = 007
N5.C3.D0.R1.S13: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N7.C2.D0.R0.S10: RcvEn: plus1 = 1, minus1 = 0, PI = 03, DB = 1
N1.C2.D0.R0.S13: RcvEn: plus1 = 1, minus1 = 0, PI = 23, DB = 0
N3.C2.D0.R1.S10: Offset Found: RdPtrOffsetDqs = 007
N5.C3.D0.R1.S14: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N7.C2.D0.R0.S11: RcvEn: plus1 = 1, minus1 = 0, PI = 39, DB = 0
N1.C2.D0.R0.S14: RcvEn: plus1 = 1, minus1 = 0, PI = 31, DB = 0
N3.C2.D0.R1.S11: Offset Found: RdPtrOffsetDqs = 007
N5.C3.D0.R1.S15: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N7.C2.D0.R0.S12: RcvEn: plus1 = 1, minus1 = 0, PI = 17, DB = 0
N1.C2.D0.R0.S15: RcvEn: plus1 = 1, minus1 = 0, PI = 08, DB = 1
N3.C2.D0.R1.S12: Offset Found: RdPtrOffsetDqs = 006
N5.C3.D0.R1.S16: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N7.C2.D0.R0.S13: RcvEn: plus1 = 1, minus1 = 0, PI = 22, DB = 0
N1.C2.D0.R0.S16: RcvEn: plus1 = 1, minus1 = 0, PI = 27, DB = 0
N3.C2.D0.R1.S13: Offset Found: RdPtrOffsetDqs = 006
N5.C3.D0.R1.S17: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N7.C2.D0.R0.S14: RcvEn: plus1 = 1, minus1 = 0, PI = 32, DB = 0
N1.C2.D0.R0.S17: RcvEn: plus1 = 1, minus1 = 0, PI = 05, DB = 1
N3.C2.D0.R1.S14: Offset Found: RdPtrOffsetDqs = 006
N5.C3.D0.R1.S09: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N7.C2.D0.R0.S15: RcvEn: plus1 = 1, minus1 = 0, PI = 08, DB = 1
N1.C2.D0.R1.S00: RcvEn: plus1 = 1, minus1 = 0, PI = 32, DB = 0
N3.C2.D0.R1.S15: Offset Found: RdPtrOffsetDqs = 006
N5.C3.D0.R1.S10: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N7.C2.D0.R0.S16: RcvEn: plus1 = 1, minus1 = 0, PI = 27, DB = 0
N1.C2.D0.R1.S01: RcvEn: plus1 = 1, minus1 = 0, PI = 06, DB = 1
N3.C2.D0.R1.S16: Offset Found: RdPtrOffsetDqs = 006
N5.C3.D0.R1.S11: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N7.C2.D0.R0.S17: RcvEn: plus1 = 1, minus1 = 0, PI = 06, DB = 1
N1.C2.D0.R1.S02: RcvEn: plus1 = 1, minus1 = 0, PI = 38, DB = 0
N3.C2.D0.R1.S17: Offset Found: RdPtrOffsetDqs = 006
N5.C3.D0.R1.S12: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N7.C2.D0.R1.S00: RcvEn: plus1 = 1, minus1 = 0, PI = 28, DB = 0
N1.C2.D0.R1.S03: RcvEn: plus1 = 1, minus1 = 0, PI = 19, DB = 0
N3.C2: Calculating Optimimum DQS Values
N5.C3.D0.R1.S13: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N7.C2.D0.R1.S01: RcvEn: plus1 = 1, minus1 = 0, PI = 07, DB = 1
N1.C2.D0.R1.S04: RcvEn: plus1 = 1, minus1 = 0, PI = 26, DB = 0
N3.C2.D0.R0.S00: Total Delay in PI ticks: TxDQS = 989, TxDQ = 956
N5.C3.D0.R1.S14: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N7.C2.D0.R1.S02: RcvEn: plus1 = 1, minus1 = 0, PI = 37, DB = 0
N1.C2.D0.R1.S05: RcvEn: plus1 = 1, minus1 = 0, PI = 34, DB = 0
N3.C2.D0.R0.S01: Total Delay in PI ticks: TxDQS = 972, TxDQ = 938
N5.C3.D0.R1.S15: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N7.C2.D0.R1.S03: RcvEn: plus1 = 1, minus1 = 0, PI = 16, DB = 0
N1.C2.D0.R1.S06: RcvEn: plus1 = 1, minus1 = 0, PI = 07, DB = 1
N3.C2.D0.R0.S02: Total Delay in PI ticks: TxDQS = 961, TxDQ = 927
N5.C3.D0.R1.S16: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N7.C2.D0.R1.S04: RcvEn: plus1 = 1, minus1 = 0, PI = 20, DB = 0
N1.C2.D0.R1.S07: RcvEn: plus1 = 1, minus1 = 0, PI = 25, DB = 0
N3.C2.D0.R0.S03: Total Delay in PI ticks: TxDQS = 943, TxDQ = 908
N5.C3.D0.R1.S17: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N7.C2.D0.R1.S05: RcvEn: plus1 = 1, minus1 = 0, PI = 31, DB = 0
N1.C2.D0.R1.S08: RcvEn: plus1 = 1, minus1 = 0, PI = 08, DB = 1
N3.C2.D0.R0.S04: Total Delay in PI ticks: TxDQS = 905, TxDQ = 873
N5.C3.D0.R1.S09: Preamble found at Latency = 008
N7.C2.D0.R1.S06: RcvEn: plus1 = 1, minus1 = 0, PI = 06, DB = 1
N1.C2.D0.R1.S09: RcvEn: plus1 = 1, minus1 = 0, PI = 29, DB = 0
N3.C2.D0.R0.S05: Total Delay in PI ticks: TxDQS = 933, TxDQ = 898
N5.C3.D0.R1.S10: Preamble found at Latency = 008
N7.C2.D0.R1.S07: RcvEn: plus1 = 1, minus1 = 0, PI = 24, DB = 0
N1.C2.D0.R1.S10: RcvEn: plus1 = 1, minus1 = 0, PI = 07, DB = 1
N3.C2.D0.R0.S06: Total Delay in PI ticks: TxDQS = 934, TxDQ = 899
N5.C3.D0.R1.S15: Preamble found at Latency = 008
N7.C2.D0.R1.S08: RcvEn: plus1 = 1, minus1 = 0, PI = 08, DB = 1
N1.C2.D0.R1.S11: RcvEn: plus1 = 1, minus1 = 0, PI = 36, DB = 0
N3.C2.D0.R0.S07: Total Delay in PI ticks: TxDQS = 954, TxDQ = 921
N5.C3.D0.R1.S16: Preamble found at Latency = 008
N7.C2.D0.R1.S09: RcvEn: plus1 = 1, minus1 = 0, PI = 26, DB = 0
N1.C2.D0.R1.S12: RcvEn: plus1 = 1, minus1 = 0, PI = 20, DB = 0
N3.C2.D0.R0.S08: Total Delay in PI ticks: TxDQS = 920, TxDQ = 884
N5.C3.D0.R1.S09: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N7.C2.D0.R1.S10: RcvEn: plus1 = 1, minus1 = 0, PI = 03, DB = 1
N1.C2.D0.R1.S13: RcvEn: plus1 = 1, minus1 = 0, PI = 23, DB = 0
N3.C2.D0.R0.S09: Total Delay in PI ticks: TxDQS = 986, TxDQ = 953
N5.C3.D0.R1.S10: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N7.C2.D0.R1.S11: RcvEn: plus1 = 1, minus1 = 0, PI = 39, DB = 0
N1.C2.D0.R1.S14: RcvEn: plus1 = 1, minus1 = 0, PI = 31, DB = 0
N3.C2.D0.R0.S10: Total Delay in PI ticks: TxDQS = 974, TxDQ = 939
N5.C3.D0.R1.S11: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N7.C2.D0.R1.S12: RcvEn: plus1 = 1, minus1 = 0, PI = 17, DB = 0
N1.C2.D0.R1.S15: RcvEn: plus1 = 1, minus1 = 0, PI = 08, DB = 1
N3.C2.D0.R0.S11: Total Delay in PI ticks: TxDQS = 965, TxDQ = 932
N5.C3.D0.R1.S12: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N7.C2.D0.R1.S13: RcvEn: plus1 = 1, minus1 = 0, PI = 22, DB = 0
N1.C2.D0.R1.S16: RcvEn: plus1 = 1, minus1 = 0, PI = 27, DB = 0
N3.C2.D0.R0.S12: Total Delay in PI ticks: TxDQS = 945, TxDQ = 911
N5.C3.D0.R1.S13: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N7.C2.D0.R1.S14: RcvEn: plus1 = 1, minus1 = 0, PI = 32, DB = 0
N1.C2.D0.R1.S17: RcvEn: plus1 = 1, minus1 = 0, PI = 05, DB = 1
N3.C2.D0.R0.S13: Total Delay in PI ticks: TxDQS = 904, TxDQ = 871
N5.C3.D0.R1.S14: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N7.C2.D0.R1.S15: RcvEn: plus1 = 1, minus1 = 0, PI = 08, DB = 1
STOP_DATA_REC_EN
N3.C2.D0.R0.S14: Total Delay in PI ticks: TxDQS = 933, TxDQ = 897
N5.C3.D0.R1.S15: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N7.C2.D0.R1.S16: RcvEn: plus1 = 1, minus1 = 0, PI = 27, DB = 0
N1.C3.D0.R0: RcvEnFine: Initial RdCmd2RcvEnLatency = 10, Initial RdPtrOffsetRcvEn = 4
N3.C2.D0.R0.S15: Total Delay in PI ticks: TxDQS = 934, TxDQ = 900
N5.C3.D0.R1.S16: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N7.C2.D0.R1.S17: RcvEn: plus1 = 1, minus1 = 0, PI = 06, DB = 1
N1.C3.D0.R0.S00: Rcv En Fine Value = 295
N3.C2.D0.R0.S16: Total Delay in PI ticks: TxDQS = 956, TxDQ = 925
N5.C3.D0.R1.S17: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
STOP_DATA_REC_EN
N1.C3.D0.R0.S01: Rcv En Fine Value = 276
N3.C2.D0.R0.S17: Total Delay in PI ticks: TxDQS = 920, TxDQ = 886
N5.C3.D0.R1.S11: Preamble found at Latency = 007
N7.C3.D0.R0: RcvEnFine: Initial RdCmd2RcvEnLatency = 10, Initial RdPtrOffsetRcvEn = 4
N1.C3.D0.R0.S02: Rcv En Fine Value = 373
N3.C2.D0.R1.S00: Total Delay in PI ticks: TxDQS = 989, TxDQ = 956
N5.C3.D0.R1.S12: Preamble found at Latency = 007
N7.C3.D0.R0.S00: Rcv En Fine Value = 306
N1.C3.D0.R0.S03: Rcv En Fine Value = 350
N3.C2.D0.R1.S01: Total Delay in PI ticks: TxDQS = 970, TxDQ = 936
N5.C3.D0.R1.S13: Preamble found at Latency = 007
N7.C3.D0.R0.S01: Rcv En Fine Value = 286
N1.C3.D0.R0.S04: Rcv En Fine Value = 350
N3.C2.D0.R1.S02: Total Delay in PI ticks: TxDQS = 961, TxDQ = 927
N5.C3.D0.R1.S14: Preamble found at Latency = 007
N7.C3.D0.R0.S02: Rcv En Fine Value = 256
N1.C3.D0.R0.S05: Rcv En Fine Value = 372
N3.C2.D0.R1.S03: Total Delay in PI ticks: TxDQS = 944, TxDQ = 909
N5.C3.D0.R1.S17: Preamble found at Latency = 007
N7.C3.D0.R0.S03: Rcv En Fine Value = 365
N1.C3.D0.R0.S06: Rcv En Fine Value = 267
N3.C2.D0.R1.S04: Total Delay in PI ticks: TxDQS = 903, TxDQ = 871
N5.C3.D0.R1: Preamble found for all upper nibbles, adjusting Pi, Offset to center into preamble
N7.C3.D0.R0.S04: Rcv En Fine Value = 358
N1.C3.D0.R0.S07: Rcv En Fine Value = 289
N3.C2.D0.R1.S05: Total Delay in PI ticks: TxDQS = 935, TxDQ = 900
N5.C3.D0.R1.S09: Total Receive Enable Delay = 1353
N7.C3.D0.R0.S05: Rcv En Fine Value = 256
N1.C3.D0.R0.S08: Rcv En Fine Value = 331
N3.C2.D0.R1.S06: Total Delay in PI ticks: TxDQS = 935, TxDQ = 900
N5.C3.D0.R1.S10: Total Receive Enable Delay = 1337
N7.C3.D0.R0.S06: Rcv En Fine Value = 278
N1.C3.D0.R0.S09: Rcv En Fine Value = 298
N3.C2.D0.R1.S07: Total Delay in PI ticks: TxDQS = 954, TxDQ = 921
N5.C3.D0.R1.S11: Total Receive Enable Delay = 1307
N7.C3.D0.R0.S07: Rcv En Fine Value = 300
N1.C3.D0.R0.S10: Rcv En Fine Value = 277
N3.C2.D0.R1.S08: Total Delay in PI ticks: TxDQS = 920, TxDQ = 884
N5.C3.D0.R1.S12: Total Receive Enable Delay = 1284
N7.C3.D0.R0.S08: Rcv En Fine Value = 343
N1.C3.D0.R0.S11: Rcv En Fine Value = 374
N3.C2.D0.R1.S09: Total Delay in PI ticks: TxDQS = 986, TxDQ = 953
N5.C3.D0.R1.S13: Total Receive Enable Delay = 1281
N7.C3.D0.R0.S09: Rcv En Fine Value = 308
N1.C3.D0.R0.S12: Rcv En Fine Value = 359
N3.C2.D0.R1.S10: Total Delay in PI ticks: TxDQS = 974, TxDQ = 939
N5.C3.D0.R1.S14: Total Receive Enable Delay = 1306
N7.C3.D0.R0.S10: Rcv En Fine Value = 288
N1.C3.D0.R0.S13: Rcv En Fine Value = 347
N3.C2.D0.R1.S11: Total Delay in PI ticks: TxDQS = 962, TxDQ = 929
N5.C3.D0.R1.S15: Total Receive Enable Delay = 1327
N7.C3.D0.R0.S11: Rcv En Fine Value = 257
N1.C3.D0.R0.S14: Rcv En Fine Value = 371
N3.C2.D0.R1.S12: Total Delay in PI ticks: TxDQS = 945, TxDQ = 911
N5.C3.D0.R1.S16: Total Receive Enable Delay = 1350
N7.C3.D0.R0.S12: Rcv En Fine Value = 368
N1.C3.D0.R0.S15: Rcv En Fine Value = 266
N3.C2.D0.R1.S13: Total Delay in PI ticks: TxDQS = 904, TxDQ = 871
N5.C3.D0.R1.S17: Total Receive Enable Delay = 1266
N7.C3.D0.R0.S13: Rcv En Fine Value = 358
N1.C3.D0.R0.S16: Rcv En Fine Value = 293
N3.C2.D0.R1.S14: Total Delay in PI ticks: TxDQS = 932, TxDQ = 897
START_DATA_REC_EN
N7.C3.D0.R0.S14: Rcv En Fine Value = 257
N1.C3.D0.R0.S17: Rcv En Fine Value = 335
N3.C2.D0.R1.S15: Total Delay in PI ticks: TxDQS = 935, TxDQ = 901
N5.C3.S00: RdCmd2RcvEnLatency = 9, RdPtrOffsetRcvEn = 5
N7.C3.D0.R0.S15: Rcv En Fine Value = 276
N1.C3.D0.R0: Starting preamble search lower nibbles
N3.C2.D0.R1.S16: Total Delay in PI ticks: TxDQS = 958, TxDQ = 927
N5.C3.S01: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N7.C3.D0.R0.S16: Rcv En Fine Value = 300
N1.C3.D0.R0.S00: PI = 039, PtrOffset = 004
N3.C2.D0.R1.S17: Total Delay in PI ticks: TxDQS = 920, TxDQ = 885
N5.C3.S02: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N7.C3.D0.R0.S17: Rcv En Fine Value = 345
N1.C3.D0.R0.S01: PI = 020, PtrOffset = 004
N3.C3.D0.R0: Write Training Coarse, lower nibbles / bytes
N5.C3.S03: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N7.C3.D0.R0: Starting preamble search lower nibbles
N1.C3.D0.R0.S02: PI = 053, PtrOffset = 005
N3.C3.D0.R0.S00: Dq Delay estimate: 452
N5.C3.S04: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 5
N7.C3.D0.R0.S00: PI = 050, PtrOffset = 004
N1.C3.D0.R0.S03: PI = 030, PtrOffset = 005
N3.C3.D0.R0.S01: Dq Delay estimate: 435
N5.C3.S05: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N7.C3.D0.R0.S01: PI = 030, PtrOffset = 004
N1.C3.D0.R0.S04: PI = 030, PtrOffset = 005
N3.C3.D0.R0.S02: Dq Delay estimate: 425
N5.C3.S06: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N7.C3.D0.R0.S02: PI = 000, PtrOffset = 004
N1.C3.D0.R0.S05: PI = 052, PtrOffset = 005
N3.C3.D0.R0.S03: Dq Delay estimate: 409
N5.C3.S07: RdCmd2RcvEnLatency = 9, RdPtrOffsetRcvEn = 5
N7.C3.D0.R0.S03: PI = 045, PtrOffset = 005
N1.C3.D0.R0.S06: PI = 011, PtrOffset = 004
N3.C3.D0.R0.S04: Dq Delay estimate: 373
N5.C3.S08: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 5
N7.C3.D0.R0.S04: PI = 038, PtrOffset = 005
N1.C3.D0.R0.S07: PI = 033, PtrOffset = 004
N3.C3.D0.R0.S05: Dq Delay estimate: 387
N5.C3.S09: RdCmd2RcvEnLatency = 9, RdPtrOffsetRcvEn = 5
N7.C3.D0.R0.S05: PI = 000, PtrOffset = 004
N1.C3.D0.R0.S08: PI = 011, PtrOffset = 005
N3.C3.D0.R0.S06: Dq Delay estimate: 400
N5.C3.S10: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N7.C3.D0.R0.S06: PI = 022, PtrOffset = 004
N1.C3.D0.R0.S00: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N3.C3.D0.R0.S07: Dq Delay estimate: 420
N5.C3.S11: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N7.C3.D0.R0.S07: PI = 044, PtrOffset = 004
N1.C3.D0.R0.S01: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N3.C3.D0.R0.S08: Dq Delay estimate: 388
N5.C3.S12: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N7.C3.D0.R0.S08: PI = 023, PtrOffset = 005
N1.C3.D0.R0.S02: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
ACCM: 9F 0F9F0F0F 9F0F0F0F
N5.C3.S13: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 5
N7.C3.D0.R0.S00: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N1.C3.D0.R0.S03: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
ACCM: 9F 0F9F0F0F 9F0F0F0F
N5.C3.S14: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N7.C3.D0.R0.S01: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N1.C3.D0.R0.S04: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
ACCM: 9F FF9F0F0F 9FFFFFFF
N5.C3.S15: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N7.C3.D0.R0.S02: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N1.C3.D0.R0.S05: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
ACCM: 9F FF9F0F0F 9FFFFFFF
N5.C3.S16: RdCmd2RcvEnLatency = 9, RdPtrOffsetRcvEn = 5
N7.C3.D0.R0.S03: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N1.C3.D0.R0.S06: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N3.C3.D0.R0: CheckMCTest: result = 0x39FFF
N5.C3.S17: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 5
N7.C3.D0.R0.S04: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N1.C3.D0.R0.S07: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
ACCM: DF 0FDF0F0F DF0F0F0F
N5.C3.D0.R0.S00: RcvEn: plus1 = 1, minus1 = 0, PI = 11, DB = 1
N7.C3.D0.R0.S05: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N1.C3.D0.R0.S08: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
ACCM: DF 0FDF0F0F DF0F0F0F
N5.C3.D0.R0.S01: RcvEn: plus1 = 1, minus1 = 0, PI = 54, DB = 1
N7.C3.D0.R0.S06: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N1.C3.D0.R0.S00: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
ACCM: DF FFDF0F0F DFFFFFFF
N5.C3.D0.R0.S02: RcvEn: plus1 = 1, minus1 = 0, PI = 25, DB = 0
N7.C3.D0.R0.S07: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N1.C3.D0.R0.S01: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
ACCM: DF FFDF0F0F DFFFFFFF
N5.C3.D0.R0.S03: RcvEn: plus1 = 1, minus1 = 0, PI = 02, DB = 1
N7.C3.D0.R0.S08: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N1.C3.D0.R0.S02: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N3.C3.D0.R0: CheckMCTest: result = 0x39FFF
N5.C3.D0.R0.S04: RcvEn: plus1 = 1, minus1 = 0, PI = 63, DB = 1
N7.C3.D0.R0.S00: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N1.C3.D0.R0.S03: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
ACCM: DF 0FDF0F0F FF0F0F0F
N5.C3.D0.R0.S05: RcvEn: plus1 = 1, minus1 = 0, PI = 25, DB = 0
N7.C3.D0.R0.S01: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N1.C3.D0.R0.S04: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
ACCM: DF 0FDF0F0F FF0F0F0F
N5.C3.D0.R0.S06: RcvEn: plus1 = 1, minus1 = 0, PI = 47, DB = 0
N7.C3.D0.R0.S02: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N1.C3.D0.R0.S05: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
ACCM: D0 F0D00000 F0F0FBF0
N5.C3.D0.R0.S07: RcvEn: plus1 = 1, minus1 = 0, PI = 04, DB = 1
N7.C3.D0.R0.S03: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N1.C3.D0.R0.S06: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
ACCM: D0 F0D00000 F0F0FBF0
N5.C3.D0.R0.S08: RcvEn: plus1 = 1, minus1 = 0, PI = 47, DB = 0
N7.C3.D0.R0.S04: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N1.C3.D0.R0.S07: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N3.C3.D0.R0: CheckMCTest: result = 0x39FFF
N5.C3.D0.R0.S09: RcvEn: plus1 = 1, minus1 = 0, PI = 09, DB = 1
N7.C3.D0.R0.S05: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N1.C3.D0.R0.S08: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
ACCM: DF 0FDF0F0F FF0F0F0F
N5.C3.D0.R0.S10: RcvEn: plus1 = 1, minus1 = 0, PI = 55, DB = 1
N7.C3.D0.R0.S06: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N1.C3.D0.R0.S00: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
ACCM: DF 0FDF0F0F FF0F0F0F
N5.C3.D0.R0.S11: RcvEn: plus1 = 1, minus1 = 0, PI = 27, DB = 0
N7.C3.D0.R0.S07: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N1.C3.D0.R0.S01: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
ACCM: D0 F0D00000 F0F0FFF0
N5.C3.D0.R0.S12: RcvEn: plus1 = 1, minus1 = 0, PI = 03, DB = 1
N7.C3.D0.R0.S08: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N1.C3.D0.R0.S02: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
ACCM: D0 F0D00000 F0F0FFF0
N5.C3.D0.R0.S13: RcvEn: plus1 = 1, minus1 = 0, PI = 63, DB = 1
N7.C3.D0.R0.S00: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N1.C3.D0.R0.S03: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N3.C3.D0.R0: CheckMCTest: result = 0x39FFF
N5.C3.D0.R0.S14: RcvEn: plus1 = 1, minus1 = 0, PI = 25, DB = 0
N7.C3.D0.R0.S01: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N1.C3.D0.R0.S04: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
ACCM: 00 00D00000 F0000000
N5.C3.D0.R0.S15: RcvEn: plus1 = 1, minus1 = 0, PI = 48, DB = 0
N7.C3.D0.R0.S02: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N1.C3.D0.R0.S05: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
ACCM: 00 00D00000 F0000000
N5.C3.D0.R0.S16: RcvEn: plus1 = 1, minus1 = 0, PI = 07, DB = 1
N7.C3.D0.R0.S03: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N1.C3.D0.R0.S06: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
ACCM: 00 F0D00000 F0F0F0F0
N5.C3.D0.R0.S17: RcvEn: plus1 = 1, minus1 = 0, PI = 49, DB = 1
N7.C3.D0.R0.S04: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N1.C3.D0.R0.S07: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
ACCM: 00 F0D00000 F0F0F0F0
N5.C3.D0.R1.S00: RcvEn: plus1 = 1, minus1 = 0, PI = 11, DB = 1
N7.C3.D0.R0.S05: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N1.C3.D0.R0.S08: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N3.C3.D0.R0: CheckMCTest: result = 0x19E00
N5.C3.D0.R1.S01: RcvEn: plus1 = 1, minus1 = 0, PI = 54, DB = 1
N7.C3.D0.R0.S06: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N1.C3.D0.R0.S00: Preamble found at Latency = 008
ACCM: D0 00D00000 F0000000
N5.C3.D0.R1.S02: RcvEn: plus1 = 1, minus1 = 0, PI = 25, DB = 0
N7.C3.D0.R0.S07: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N1.C3.D0.R0.S01: Preamble found at Latency = 008
ACCM: D0 00D00000 F0000000
N5.C3.D0.R1.S03: RcvEn: plus1 = 1, minus1 = 0, PI = 02, DB = 1
N7.C3.D0.R0.S08: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N1.C3.D0.R0.S06: Preamble found at Latency = 008
ACCM: D0 F0D00000 F0F0F0F0
N5.C3.D0.R1.S04: RcvEn: plus1 = 1, minus1 = 0, PI = 63, DB = 1
N7.C3.D0.R0.S00: Preamble found at Latency = 008
N1.C3.D0.R0.S07: Preamble found at Latency = 008
ACCM: D0 F0D00000 F0F0F0F0
N5.C3.D0.R1.S05: RcvEn: plus1 = 1, minus1 = 0, PI = 25, DB = 0
N7.C3.D0.R0.S01: Preamble found at Latency = 008
N1.C3.D0.R0.S00: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N3.C3.D0.R0: CheckMCTest: result = 0x39E00
N5.C3.D0.R1.S06: RcvEn: plus1 = 1, minus1 = 0, PI = 47, DB = 0
N7.C3.D0.R0.S02: Preamble found at Latency = 008
N1.C3.D0.R0.S01: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N3.C3.D0.R0.S00: Offset Found: RdPtrOffsetDqs = 007
N5.C3.D0.R1.S07: RcvEn: plus1 = 1, minus1 = 0, PI = 04, DB = 1
N7.C3.D0.R0.S05: Preamble found at Latency = 008
N1.C3.D0.R0.S02: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N3.C3.D0.R0.S01: Offset Found: RdPtrOffsetDqs = 007
N5.C3.D0.R1.S08: RcvEn: plus1 = 1, minus1 = 0, PI = 47, DB = 0
N7.C3.D0.R0.S06: Preamble found at Latency = 008
N1.C3.D0.R0.S03: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N3.C3.D0.R0.S02: Offset Found: RdPtrOffsetDqs = 007
N5.C3.D0.R1.S09: RcvEn: plus1 = 1, minus1 = 0, PI = 09, DB = 1
N7.C3.D0.R0.S07: Preamble found at Latency = 008
N1.C3.D0.R0.S04: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N3.C3.D0.R0.S03: Offset Found: RdPtrOffsetDqs = 006
N5.C3.D0.R1.S10: RcvEn: plus1 = 1, minus1 = 0, PI = 55, DB = 1
N7.C3.D0.R0.S00: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N1.C3.D0.R0.S05: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N3.C3.D0.R0.S04: Offset Found: RdPtrOffsetDqs = 006
N5.C3.D0.R1.S11: RcvEn: plus1 = 1, minus1 = 0, PI = 27, DB = 0
N7.C3.D0.R0.S01: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N1.C3.D0.R0.S06: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N3.C3.D0.R0.S05: Offset Found: RdPtrOffsetDqs = 006
N5.C3.D0.R1.S12: RcvEn: plus1 = 1, minus1 = 0, PI = 03, DB = 1
N7.C3.D0.R0.S02: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N1.C3.D0.R0.S07: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N3.C3.D0.R0.S06: Offset Found: RdPtrOffsetDqs = 006
N5.C3.D0.R1.S13: RcvEn: plus1 = 1, minus1 = 0, PI = 63, DB = 1
N7.C3.D0.R0.S03: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N1.C3.D0.R0.S08: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N3.C3.D0.R0.S07: Offset Found: RdPtrOffsetDqs = 007
N5.C3.D0.R1.S14: RcvEn: plus1 = 1, minus1 = 0, PI = 25, DB = 0
N7.C3.D0.R0.S04: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N1.C3.D0.R0.S02: Preamble found at Latency = 007
N3.C3.D0.R0.S08: Offset Found: RdPtrOffsetDqs = 006
N5.C3.D0.R1.S15: RcvEn: plus1 = 1, minus1 = 0, PI = 48, DB = 0
N7.C3.D0.R0.S05: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N1.C3.D0.R0.S03: Preamble found at Latency = 007
N3.C3.D0.R0: Write Training Coarse, upper nibbles
N5.C3.D0.R1.S16: RcvEn: plus1 = 1, minus1 = 0, PI = 07, DB = 1
N7.C3.D0.R0.S06: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N1.C3.D0.R0.S04: Preamble found at Latency = 007
N3.C3.D0.R0.S09: Dq Delay estimate: 450
N5.C3.D0.R1.S17: RcvEn: plus1 = 1, minus1 = 0, PI = 49, DB = 1
N7.C3.D0.R0.S07: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N1.C3.D0.R0.S05: Preamble found at Latency = 007
N3.C3.D0.R0.S10: Dq Delay estimate: 435
STOP_DATA_REC_EN
N7.C3.D0.R0.S08: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N1.C3.D0.R0.S08: Preamble found at Latency = 007
N3.C3.D0.R0.S11: Dq Delay estimate: 426
N5.C0.D0.R0.S00: StoreJckWorstRank: worst rank = 0, greatestDelay = 1304
N7.C3.D0.R0.S03: Preamble found at Latency = 007
N1.C3.D0.R0.S00: Total Receive Enable Delay = 1351
N3.C3.D0.R0.S12: Dq Delay estimate: 407
N5.C0.D0.R0.S07: StoreJckWorstRank: worst rank = 0, greatestDelay = 1310
N7.C3.D0.R0.S04: Preamble found at Latency = 007
N1.C3.D0.R0.S01: Total Receive Enable Delay = 1332
N3.C3.D0.R0.S13: Dq Delay estimate: 374
N5.C1.D0.R0.S00: StoreJckWorstRank: worst rank = 0, greatestDelay = 1358
N7.C3.D0.R0.S08: Preamble found at Latency = 007
N1.C3.D0.R0.S02: Total Receive Enable Delay = 1301
N3.C3.D0.R0.S14: Dq Delay estimate: 386
N5.C0: StoreJckWorstRank: final value: worst rank = 0
N7.C3.D0.R0.S00: Total Receive Enable Delay = 1362
N1.C3.D0.R0.S03: Total Receive Enable Delay = 1278
N3.C3.D0.R0.S15: Dq Delay estimate: 401
N5.C2.D0.R0.S00: StoreJckWorstRank: worst rank = 0, greatestDelay = 1317
N7.C3.D0.R0.S01: Total Receive Enable Delay = 1342
N1.C3.D0.R0.S04: Total Receive Enable Delay = 1278
N3.C3.D0.R0.S16: Dq Delay estimate: 423
N5.C2.D0.R0.S09: StoreJckWorstRank: worst rank = 0, greatestDelay = 1318
N7.C3.D0.R0.S02: Total Receive Enable Delay = 1312
N1.C3.D0.R0.S05: Total Receive Enable Delay = 1300
N3.C3.D0.R0.S17: Dq Delay estimate: 388
N5.C3.D0.R0.S00: StoreJckWorstRank: worst rank = 0, greatestDelay = 1355
N7.C3.D0.R0.S03: Total Receive Enable Delay = 1293
N1.C3.D0.R0.S06: Total Receive Enable Delay = 1323
ACCM: F0 F0F0F0F0 F0F0F0F0
N5.C3.D0.R1.S00: StoreJckWorstRank: worst rank = 1, greatestDelay = 1356
N7.C3.D0.R0.S04: Total Receive Enable Delay = 1286
N1.C3.D0.R0.S07: Total Receive Enable Delay = 1345
ACCM: F0 F0F0F0F0 F0F0F0F0
N5.C1: StoreJckWorstRank: final value: worst rank = 1
N7.C3.D0.R0.S05: Total Receive Enable Delay = 1312
N1.C3.D0.R0.S08: Total Receive Enable Delay = 1259
ACCM: F0 F0F0F0F0 F0F0F0F0
N5: RunTrainStep: Final status = 0
N7.C3.D0.R0.S06: Total Receive Enable Delay = 1334
N1.C3.D0.R0: Starting preamble search upper nibbles
ACCM: F0 F0F0F0F0 F0F0F0F0

END - Basic Receive Enable Training    Time         31872 ms
N7.C3.D0.R0.S07: Total Receive Enable Delay = 1356
N1.C3.D0.R0.S09: PI = 042, PtrOffset = 004
N3.C3.D0.R0: CheckMCTest: result = 0x3FE00
N5.C0.S00: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  6
N7.C3.D0.R0.S08: Total Receive Enable Delay = 1271
N1.C3.D0.R0.S10: PI = 021, PtrOffset = 004
ACCM: F0 F0F0F0F0 F0F0F0F0
N5.C0.S01: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  6
N7.C3.D0.R0: Starting preamble search upper nibbles
N1.C3.D0.R0.S11: PI = 054, PtrOffset = 005
ACCM: F0 F0F0F0F0 F0F0F0F0
N5.C0.S02: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  5
N7.C3.D0.R0.S09: PI = 052, PtrOffset = 004
N1.C3.D0.R0.S12: PI = 039, PtrOffset = 005
ACCM: F0 F0F0F0F0 F0F0F0F0
N5.C0.S03: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  5
N7.C3.D0.R0.S10: PI = 032, PtrOffset = 004
N1.C3.D0.R0.S13: PI = 027, PtrOffset = 005
ACCM: F0 F0F0F0F0 F0F0F0F0
N5.C0.S04: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  5
N7.C3.D0.R0.S11: PI = 001, PtrOffset = 004
N1.C3.D0.R0.S14: PI = 051, PtrOffset = 005
N3.C3.D0.R0: CheckMCTest: result = 0x3FE00
N5.C0.S05: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  5
N7.C3.D0.R0.S12: PI = 048, PtrOffset = 005
N1.C3.D0.R0.S15: PI = 010, PtrOffset = 004
ACCM: F0 F0F0F0F0 F0F0F0F0
N5.C0.S06: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  6
N7.C3.D0.R0.S13: PI = 038, PtrOffset = 005
N1.C3.D0.R0.S16: PI = 037, PtrOffset = 004
ACCM: F0 F0F0F0F0 F0F0F0F0
N5.C0.S07: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  6
N7.C3.D0.R0.S14: PI = 001, PtrOffset = 004
N1.C3.D0.R0.S17: PI = 015, PtrOffset = 005
ACCM: 00 00000000 00000000
N5.C0.S08: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  5
N7.C3.D0.R0.S15: PI = 020, PtrOffset = 004
N1.C3.D0.R0.S09: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
ACCM: 00 00000000 00000000
N5.C1.S00: SuppressionWindowAdjustmentRd: latency =  9, rdptroffset =  5
N7.C3.D0.R0.S16: PI = 044, PtrOffset = 004
N1.C3.D0.R0.S10: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N3.C3.D0.R0: CheckMCTest: result = 0x3FE00
N5.C1.S01: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  6
N7.C3.D0.R0.S17: PI = 025, PtrOffset = 005
N1.C3.D0.R0.S11: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
ACCM: F0 F0F0F0F0 F0F0F0F0
N5.C1.S02: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  6
N7.C3.D0.R0.S09: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N1.C3.D0.R0.S12: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
ACCM: F0 F0F0F0F0 F0F0F0F0
N5.C1.S03: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  6
N7.C3.D0.R0.S10: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N1.C3.D0.R0.S13: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
ACCM: 00 00000000 00000000
N5.C1.S04: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  5
N7.C3.D0.R0.S11: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N1.C3.D0.R0.S14: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
ACCM: 00 00000000 00000000
N5.C1.S05: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  6
N7.C3.D0.R0.S12: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N1.C3.D0.R0.S15: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N3.C3.D0.R0: CheckMCTest: result = 0x3FE00
N5.C1.S06: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  6
N7.C3.D0.R0.S13: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N1.C3.D0.R0.S16: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N3.C3.D0.R0: CheckMCTest: passed
N5.C1.S07: SuppressionWindowAdjustmentRd: latency =  9, rdptroffset =  5
N7.C3.D0.R0.S14: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N1.C3.D0.R0.S17: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N3.C3.D0.R0: CheckMCTest: passed
N5.C1.S08: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  5
N7.C3.D0.R0.S15: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N1.C3.D0.R0.S09: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N3.C3.D0.R0.S09: Offset Found: RdPtrOffsetDqs = 007
N5.C2.S00: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  6
N7.C3.D0.R0.S16: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N1.C3.D0.R0.S10: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N3.C3.D0.R0.S10: Offset Found: RdPtrOffsetDqs = 007
N5.C2.S01: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  6
N7.C3.D0.R0.S17: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N1.C3.D0.R0.S11: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N3.C3.D0.R0.S11: Offset Found: RdPtrOffsetDqs = 007
N5.C2.S02: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  5
N7.C3.D0.R0.S09: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N1.C3.D0.R0.S12: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N3.C3.D0.R0.S12: Offset Found: RdPtrOffsetDqs = 006
N5.C2.S03: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  5
N7.C3.D0.R0.S10: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N1.C3.D0.R0.S13: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N3.C3.D0.R0.S13: Offset Found: RdPtrOffsetDqs = 006
N5.C2.S04: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  5
N7.C3.D0.R0.S11: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N1.C3.D0.R0.S14: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N3.C3.D0.R0.S14: Offset Found: RdPtrOffsetDqs = 006
N5.C2.S05: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  5
N7.C3.D0.R0.S12: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N1.C3.D0.R0.S15: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N3.C3.D0.R0.S15: Offset Found: RdPtrOffsetDqs = 006
N5.C2.S06: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  6
N7.C3.D0.R0.S13: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N1.C3.D0.R0.S16: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N3.C3.D0.R0.S16: Offset Found: RdPtrOffsetDqs = 007
N5.C2.S07: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  6
N7.C3.D0.R0.S14: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N1.C3.D0.R0.S17: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N3.C3.D0.R0.S17: Offset Found: RdPtrOffsetDqs = 006
N5.C2.S08: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  5
N7.C3.D0.R0.S15: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N1.C3.D0.R0.S09: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N3.C3.D0.R1: Write Training Coarse, lower nibbles / bytes
N5.C3.S00: SuppressionWindowAdjustmentRd: latency =  9, rdptroffset =  5
N7.C3.D0.R0.S16: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N1.C3.D0.R0.S10: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N3.C3.D0.R1.S00: Dq Delay estimate: 453
N5.C3.S01: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  6
N7.C3.D0.R0.S17: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N1.C3.D0.R0.S11: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N3.C3.D0.R1.S01: Dq Delay estimate: 434
N5.C3.S02: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  6
N7.C3.D0.R0.S09: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N1.C3.D0.R0.S12: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N3.C3.D0.R1.S02: Dq Delay estimate: 425
N5.C3.S03: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  6
N7.C3.D0.R0.S10: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N1.C3.D0.R0.S13: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N3.C3.D0.R1.S03: Dq Delay estimate: 406
N5.C3.S04: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  5
N7.C3.D0.R0.S11: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N1.C3.D0.R0.S14: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N3.C3.D0.R1.S04: Dq Delay estimate: 371
N5.C3.S05: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  6
N7.C3.D0.R0.S12: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N1.C3.D0.R0.S15: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N3.C3.D0.R1.S05: Dq Delay estimate: 387
N5.C3.S06: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  6
N7.C3.D0.R0.S13: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N1.C3.D0.R0.S16: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N3.C3.D0.R1.S06: Dq Delay estimate: 399
N5.C3.S07: SuppressionWindowAdjustmentRd: latency =  9, rdptroffset =  5
N7.C3.D0.R0.S14: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N1.C3.D0.R0.S17: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N3.C3.D0.R1.S07: Dq Delay estimate: 421
N5.C3.S08: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  5
N7.C3.D0.R0.S15: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N1.C3.D0.R0.S09: Preamble found at Latency = 008
N3.C3.D0.R1.S08: Dq Delay estimate: 389

START - Basic Write Level Training
N7.C3.D0.R0.S16: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N1.C3.D0.R0.S10: Preamble found at Latency = 008
ACCM: 0F 0F0F0F0F 0F0F0F0F
N5: START WRITE LEVEL:
N7.C3.D0.R0.S17: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N1.C3.D0.R0.S15: Preamble found at Latency = 008
ACCM: 0F 0F0F0F0F 0F0F0F0F
N5.C0.D0.R0: ODT Override: 0x1
N7.C3.D0.R0.S09: Preamble found at Latency = 008
N1.C3.D0.R0.S16: Preamble found at Latency = 008
ACCM: 0F 0F0F0F0F 0F0F0F0F
N5.C0.D0.R0.S00: Write Level Fine Value = 481
N7.C3.D0.R0.S10: Preamble found at Latency = 008
N1.C3.D0.R0.S09: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
ACCM: 0F 0F0F0F0F 0F0F0F0F
N5.C0.D0.R0.S01: Write Level Fine Value = 466
N7.C3.D0.R0.S11: Preamble found at Latency = 008
N1.C3.D0.R0.S10: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N3.C3.D0.R1: CheckMCTest: result = 0x1FF
N5.C0.D0.R0.S02: Write Level Fine Value = 452
N7.C3.D0.R0.S14: Preamble found at Latency = 008
N1.C3.D0.R0.S11: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
ACCM: 0F 0F0F0F0F 0F0F0F0F
N5.C0.D0.R0.S03: Write Level Fine Value = 437
N7.C3.D0.R0.S15: Preamble found at Latency = 008
N1.C3.D0.R0.S12: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
ACCM: 0F 0F0F0F0F 0F0F0F0F
N5.C0.D0.R0.S04: Write Level Fine Value = 403
N7.C3.D0.R0.S16: Preamble found at Latency = 008
N1.C3.D0.R0.S13: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
ACCM: 0F 0F0F0F0F 0F0F0F0F
N5.C0.D0.R0.S05: Write Level Fine Value = 420
N7.C3.D0.R0.S09: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N1.C3.D0.R0.S14: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
ACCM: 0F 0F0F0F0F 0F0F0F0F
N5.C0.D0.R0.S06: Write Level Fine Value = 426
N7.C3.D0.R0.S10: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N1.C3.D0.R0.S15: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N3.C3.D0.R1: CheckMCTest: result = 0x1FF
N5.C0.D0.R0.S07: Write Level Fine Value = 442
N7.C3.D0.R0.S11: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N1.C3.D0.R0.S16: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
ACCM: 0F 0F0F0F0F 0F0F0F0F
N5.C0.D0.R0.S08: Write Level Fine Value = 409
N7.C3.D0.R0.S12: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N1.C3.D0.R0.S17: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
ACCM: 0F 0F0F0F0F 0F0F0F0F
N5.C0.D0.R0.S09: Write Level Fine Value = 481
N7.C3.D0.R0.S13: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N1.C3.D0.R0.S11: Preamble found at Latency = 007
ACCM: 00 00000000 0000000B
N5.C0.D0.R0.S10: Write Level Fine Value = 466
N7.C3.D0.R0.S14: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N1.C3.D0.R0.S12: Preamble found at Latency = 007
ACCM: 00 00000000 0000000B
N5.C0.D0.R0.S11: Write Level Fine Value = 455
N7.C3.D0.R0.S15: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N1.C3.D0.R0.S13: Preamble found at Latency = 007
N3.C3.D0.R1: CheckMCTest: result = 0x1FF
N5.C0.D0.R0.S12: Write Level Fine Value = 437
N7.C3.D0.R0.S16: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N1.C3.D0.R0.S14: Preamble found at Latency = 007
ACCM: 0F 0F0F0F0F 0F0F0F0F
N5.C0.D0.R0.S13: Write Level Fine Value = 403
N7.C3.D0.R0.S17: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N1.C3.D0.R0.S17: Preamble found at Latency = 007
ACCM: 0F 0F0F0F0F 0F0F0F0F
N5.C0.D0.R0.S14: Write Level Fine Value = 419
N7.C3.D0.R0.S12: Preamble found at Latency = 007
N1.C3.D0.R0: Preamble found for all upper nibbles, adjusting Pi, Offset to center into preamble
ACCM: 00 00000000 0000000F
N5.C0.D0.R0.S15: Write Level Fine Value = 426
N7.C3.D0.R0.S13: Preamble found at Latency = 007
N1.C3.D0.R0.S09: Total Receive Enable Delay = 1354
ACCM: 00 00000000 0000000F
N5.C0.D0.R0.S16: Write Level Fine Value = 442
N7.C3.D0.R0.S17: Preamble found at Latency = 007
N1.C3.D0.R0.S10: Total Receive Enable Delay = 1333
N3.C3.D0.R1: CheckMCTest: result = 0x1FF
N5.C0.D0.R0.S17: Write Level Fine Value = 410
N7.C3.D0.R0: Preamble found for all upper nibbles, adjusting Pi, Offset to center into preamble
N1.C3.D0.R0.S11: Total Receive Enable Delay = 1302
N3.C3.D0.R1: CheckMCTest: passed
N5.C0.D0.R1: ODT Override: 0x2
N7.C3.D0.R0.S09: Total Receive Enable Delay = 1364
N1.C3.D0.R0.S12: Total Receive Enable Delay = 1287
N3.C3.D0.R1: CheckMCTest: passed
N5.C0.D0.R1.S00: Write Level Fine Value = 481
N7.C3.D0.R0.S10: Total Receive Enable Delay = 1344
N1.C3.D0.R0.S13: Total Receive Enable Delay = 1275
N3.C3.D0.R1.S00: Offset Found: RdPtrOffsetDqs = 007
N5.C0.D0.R1.S01: Write Level Fine Value = 466
N7.C3.D0.R0.S11: Total Receive Enable Delay = 1313
N1.C3.D0.R0.S14: Total Receive Enable Delay = 1299
N3.C3.D0.R1.S01: Offset Found: RdPtrOffsetDqs = 007
N5.C0.D0.R1.S02: Write Level Fine Value = 450
N7.C3.D0.R0.S12: Total Receive Enable Delay = 1296
N1.C3.D0.R0.S15: Total Receive Enable Delay = 1322
N3.C3.D0.R1.S02: Offset Found: RdPtrOffsetDqs = 007
N5.C0.D0.R1.S03: Write Level Fine Value = 437
N7.C3.D0.R0.S13: Total Receive Enable Delay = 1286
N1.C3.D0.R0.S16: Total Receive Enable Delay = 1349
N3.C3.D0.R1.S03: Offset Found: RdPtrOffsetDqs = 006
N5.C0.D0.R1.S04: Write Level Fine Value = 401
N7.C3.D0.R0.S14: Total Receive Enable Delay = 1313
N1.C3.D0.R0.S17: Total Receive Enable Delay = 1263
N3.C3.D0.R1.S04: Offset Found: RdPtrOffsetDqs = 006
N5.C0.D0.R1.S05: Write Level Fine Value = 419
N7.C3.D0.R0.S15: Total Receive Enable Delay = 1332
N1.C3.D0.R1: RcvEnFine: Initial RdCmd2RcvEnLatency = 10, Initial RdPtrOffsetRcvEn = 4
N3.C3.D0.R1.S05: Offset Found: RdPtrOffsetDqs = 006
N5.C0.D0.R1.S06: Write Level Fine Value = 426
N7.C3.D0.R0.S16: Total Receive Enable Delay = 1356
N1.C3.D0.R1.S00: Rcv En Fine Value = 296
N3.C3.D0.R1.S06: Offset Found: RdPtrOffsetDqs = 006
N5.C0.D0.R1.S07: Write Level Fine Value = 441
N7.C3.D0.R0.S17: Total Receive Enable Delay = 1273
N1.C3.D0.R1.S01: Rcv En Fine Value = 275
N3.C3.D0.R1.S07: Offset Found: RdPtrOffsetDqs = 007
N5.C0.D0.R1.S08: Write Level Fine Value = 410
N7.C3.D0.R1: RcvEnFine: Initial RdCmd2RcvEnLatency = 10, Initial RdPtrOffsetRcvEn = 4
N1.C3.D0.R1.S02: Rcv En Fine Value = 371
N3.C3.D0.R1.S08: Offset Found: RdPtrOffsetDqs = 006
N5.C0.D0.R1.S09: Write Level Fine Value = 481
N7.C3.D0.R1.S00: Rcv En Fine Value = 305
N1.C3.D0.R1.S03: Rcv En Fine Value = 350
N3.C3.D0.R1: Write Training Coarse, upper nibbles
N5.C0.D0.R1.S10: Write Level Fine Value = 464
N7.C3.D0.R1.S01: Rcv En Fine Value = 288
N1.C3.D0.R1.S04: Rcv En Fine Value = 350
N3.C3.D0.R1.S09: Dq Delay estimate: 449
N5.C0.D0.R1.S11: Write Level Fine Value = 454
N7.C3.D0.R1.S02: Rcv En Fine Value = 257
N1.C3.D0.R1.S05: Rcv En Fine Value = 372
N3.C3.D0.R1.S10: Dq Delay estimate: 434
N5.C0.D0.R1.S12: Write Level Fine Value = 433
N7.C3.D0.R1.S03: Rcv En Fine Value = 364
N1.C3.D0.R1.S06: Rcv En Fine Value = 264
N3.C3.D0.R1.S11: Dq Delay estimate: 425
N5.C0.D0.R1.S13: Write Level Fine Value = 403
N7.C3.D0.R1.S04: Rcv En Fine Value = 357
N1.C3.D0.R1.S07: Rcv En Fine Value = 288
N3.C3.D0.R1.S12: Dq Delay estimate: 405
N5.C0.D0.R1.S14: Write Level Fine Value = 418
N7.C3.D0.R1.S05: Rcv En Fine Value = 257
N1.C3.D0.R1.S08: Rcv En Fine Value = 332
N3.C3.D0.R1.S13: Dq Delay estimate: 373
N5.C0.D0.R1.S15: Write Level Fine Value = 426
N7.C3.D0.R1.S06: Rcv En Fine Value = 279
N1.C3.D0.R1.S09: Rcv En Fine Value = 296
N3.C3.D0.R1.S14: Dq Delay estimate: 388
N5.C0.D0.R1.S16: Write Level Fine Value = 443
N7.C3.D0.R1.S07: Rcv En Fine Value = 301
N1.C3.D0.R1.S10: Rcv En Fine Value = 275
N3.C3.D0.R1.S15: Dq Delay estimate: 402
N5.C0.D0.R1.S17: Write Level Fine Value = 410
N7.C3.D0.R1.S08: Rcv En Fine Value = 342
N1.C3.D0.R1.S11: Rcv En Fine Value = 376
N3.C3.D0.R1.S16: Dq Delay estimate: 424
N5.C1.D0.R0: ODT Override: 0x1
N7.C3.D0.R1.S09: Rcv En Fine Value = 308
N1.C3.D0.R1.S12: Rcv En Fine Value = 355
N3.C3.D0.R1.S17: Dq Delay estimate: 388
N5.C1.D0.R0.S00: Write Level Fine Value = 490
N7.C3.D0.R1.S10: Rcv En Fine Value = 291
N1.C3.D0.R1.S13: Rcv En Fine Value = 349
ACCM: F0 F0F0F0F0 F0F0F0F0
N5.C1.D0.R0.S01: Write Level Fine Value = 473
N7.C3.D0.R1.S11: Rcv En Fine Value = 261
N1.C3.D0.R1.S14: Rcv En Fine Value = 370
ACCM: F0 F0F0F0F0 F0F0F0F0
N5.C1.D0.R0.S02: Write Level Fine Value = 461
N7.C3.D0.R1.S12: Rcv En Fine Value = 368
N1.C3.D0.R1.S15: Rcv En Fine Value = 269
ACCM: F0 F0F0F0F0 F0F0F0F0
N5.C1.D0.R0.S03: Write Level Fine Value = 446
N7.C3.D0.R1.S13: Rcv En Fine Value = 357
N1.C3.D0.R1.S16: Rcv En Fine Value = 291
ACCM: F0 F0F0F0F0 F0F0F0F0
N5.C1.D0.R0.S04: Write Level Fine Value = 412
N7.C3.D0.R1.S14: Rcv En Fine Value = 257
N1.C3.D0.R1.S17: Rcv En Fine Value = 332
N3.C3.D0.R1: CheckMCTest: result = 0x3FE00
N5.C1.D0.R0.S05: Write Level Fine Value = 427
N7.C3.D0.R1.S15: Rcv En Fine Value = 275
N1.C3.D0.R1: Starting preamble search lower nibbles
ACCM: F0 F0F0F0F0 F0F0F0F0
N5.C1.D0.R0.S06: Write Level Fine Value = 442
N7.C3.D0.R1.S16: Rcv En Fine Value = 300
N1.C3.D0.R1.S00: PI = 040, PtrOffset = 004
ACCM: F0 F0F0F0F0 F0F0F0F0
N5.C1.D0.R0.S07: Write Level Fine Value = 459
N7.C3.D0.R1.S17: Rcv En Fine Value = 342
N1.C3.D0.R1.S01: PI = 019, PtrOffset = 004
ACCM: F0 F0F0F0F0 F0F0F0F0
N5.C1.D0.R0.S08: Write Level Fine Value = 424
N7.C3.D0.R1: Starting preamble search lower nibbles
N1.C3.D0.R1.S02: PI = 051, PtrOffset = 005
ACCM: F0 F0F0F0F0 F0F0F0F0
N5.C1.D0.R0.S09: Write Level Fine Value = 489
N7.C3.D0.R1.S00: PI = 049, PtrOffset = 004
N1.C3.D0.R1.S03: PI = 030, PtrOffset = 005
N3.C3.D0.R1: CheckMCTest: result = 0x3FE00
N5.C1.D0.R0.S10: Write Level Fine Value = 473
N7.C3.D0.R1.S01: PI = 032, PtrOffset = 004
N1.C3.D0.R1.S04: PI = 030, PtrOffset = 005
ACCM: F0 F0F0F0F0 F0F0F0F0
N5.C1.D0.R0.S11: Write Level Fine Value = 462
N7.C3.D0.R1.S02: PI = 001, PtrOffset = 004
N1.C3.D0.R1.S05: PI = 052, PtrOffset = 005
ACCM: F0 F0F0F0F0 F0F0F0F0
N5.C1.D0.R0.S12: Write Level Fine Value = 445
N7.C3.D0.R1.S03: PI = 044, PtrOffset = 005
N1.C3.D0.R1.S06: PI = 008, PtrOffset = 004
ACCM: 00 000000B0 00000000
N5.C1.D0.R0.S13: Write Level Fine Value = 414
N7.C3.D0.R1.S04: PI = 037, PtrOffset = 005
N1.C3.D0.R1.S07: PI = 032, PtrOffset = 004
ACCM: 00 000000B0 00000000
N5.C1.D0.R0.S14: Write Level Fine Value = 427
N7.C3.D0.R1.S05: PI = 001, PtrOffset = 004
N1.C3.D0.R1.S08: PI = 012, PtrOffset = 005
N3.C3.D0.R1: CheckMCTest: result = 0x3FE00
N5.C1.D0.R0.S15: Write Level Fine Value = 440
N7.C3.D0.R1.S06: PI = 023, PtrOffset = 004
N1.C3.D0.R1.S00: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
ACCM: F0 F0F0F0F0 F0F0F0F0
N5.C1.D0.R0.S16: Write Level Fine Value = 459
N7.C3.D0.R1.S07: PI = 045, PtrOffset = 004
N1.C3.D0.R1.S01: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
ACCM: F0 F0F0F0F0 F0F0F0F0
N5.C1.D0.R0.S17: Write Level Fine Value = 426
N7.C3.D0.R1.S08: PI = 022, PtrOffset = 005
N1.C3.D0.R1.S02: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
ACCM: 00 000000F0 00000000
N5.C1.D0.R1: ODT Override: 0x2
N7.C3.D0.R1.S00: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N1.C3.D0.R1.S03: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
ACCM: 00 000000F0 00000000
N5.C1.D0.R1.S00: Write Level Fine Value = 489
N7.C3.D0.R1.S01: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N1.C3.D0.R1.S04: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N3.C3.D0.R1: CheckMCTest: result = 0x3FE00
N5.C1.D0.R1.S01: Write Level Fine Value = 472
N7.C3.D0.R1.S02: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N1.C3.D0.R1.S05: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N3.C3.D0.R1: CheckMCTest: passed
N5.C1.D0.R1.S02: Write Level Fine Value = 461
N7.C3.D0.R1.S03: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N1.C3.D0.R1.S06: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N3.C3.D0.R1: CheckMCTest: passed
N5.C1.D0.R1.S03: Write Level Fine Value = 443
N7.C3.D0.R1.S04: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N1.C3.D0.R1.S07: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N3.C3.D0.R1.S09: Offset Found: RdPtrOffsetDqs = 007
N5.C1.D0.R1.S04: Write Level Fine Value = 411
N7.C3.D0.R1.S05: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N1.C3.D0.R1.S08: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N3.C3.D0.R1.S10: Offset Found: RdPtrOffsetDqs = 007
N5.C1.D0.R1.S05: Write Level Fine Value = 427
N7.C3.D0.R1.S06: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N1.C3.D0.R1.S00: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N3.C3.D0.R1.S11: Offset Found: RdPtrOffsetDqs = 007
N5.C1.D0.R1.S06: Write Level Fine Value = 439
N7.C3.D0.R1.S07: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N1.C3.D0.R1.S01: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N3.C3.D0.R1.S12: Offset Found: RdPtrOffsetDqs = 006
N5.C1.D0.R1.S07: Write Level Fine Value = 459
N7.C3.D0.R1.S08: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N1.C3.D0.R1.S02: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N3.C3.D0.R1.S13: Offset Found: RdPtrOffsetDqs = 006
N5.C1.D0.R1.S08: Write Level Fine Value = 424
N7.C3.D0.R1.S00: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N1.C3.D0.R1.S03: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N3.C3.D0.R1.S14: Offset Found: RdPtrOffsetDqs = 006
N5.C1.D0.R1.S09: Write Level Fine Value = 487
N7.C3.D0.R1.S01: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N1.C3.D0.R1.S04: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N3.C3.D0.R1.S15: Offset Found: RdPtrOffsetDqs = 006
N5.C1.D0.R1.S10: Write Level Fine Value = 473
N7.C3.D0.R1.S02: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N1.C3.D0.R1.S05: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N3.C3.D0.R1.S16: Offset Found: RdPtrOffsetDqs = 007
N5.C1.D0.R1.S11: Write Level Fine Value = 461
N7.C3.D0.R1.S03: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N1.C3.D0.R1.S06: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N3.C3.D0.R1.S17: Offset Found: RdPtrOffsetDqs = 006
N5.C1.D0.R1.S12: Write Level Fine Value = 446
N7.C3.D0.R1.S04: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N1.C3.D0.R1.S07: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N3.C3: Calculating Optimimum DQS Values
N5.C1.D0.R1.S13: Write Level Fine Value = 415
N7.C3.D0.R1.S05: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N1.C3.D0.R1.S08: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N3.C3.D0.R0.S00: Total Delay in PI ticks: TxDQS = 999, TxDQ = 964
N5.C1.D0.R1.S14: Write Level Fine Value = 426
N7.C3.D0.R1.S06: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N1.C3.D0.R1.S00: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N3.C3.D0.R0.S01: Total Delay in PI ticks: TxDQS = 980, TxDQ = 947
N5.C1.D0.R1.S15: Write Level Fine Value = 442
N7.C3.D0.R1.S07: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N1.C3.D0.R1.S01: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N3.C3.D0.R0.S02: Total Delay in PI ticks: TxDQS = 971, TxDQ = 937
N5.C1.D0.R1.S16: Write Level Fine Value = 458
N7.C3.D0.R1.S08: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N1.C3.D0.R1.S02: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N3.C3.D0.R0.S03: Total Delay in PI ticks: TxDQS = 955, TxDQ = 921
N5.C1.D0.R1.S17: Write Level Fine Value = 425
N7.C3.D0.R1.S00: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N1.C3.D0.R1.S03: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N3.C3.D0.R0.S04: Total Delay in PI ticks: TxDQS = 920, TxDQ = 885
N5.C2.D0.R0: ODT Override: 0x1
N7.C3.D0.R1.S01: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N1.C3.D0.R1.S04: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N3.C3.D0.R0.S05: Total Delay in PI ticks: TxDQS = 933, TxDQ = 899
N5.C2.D0.R0.S00: Write Level Fine Value = 485
N7.C3.D0.R1.S02: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N1.C3.D0.R1.S05: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N3.C3.D0.R0.S06: Total Delay in PI ticks: TxDQS = 948, TxDQ = 912
N5.C2.D0.R0.S01: Write Level Fine Value = 472
N7.C3.D0.R1.S03: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N1.C3.D0.R1.S06: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N3.C3.D0.R0.S07: Total Delay in PI ticks: TxDQS = 966, TxDQ = 932
N5.C2.D0.R0.S02: Write Level Fine Value = 460
N7.C3.D0.R1.S04: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N1.C3.D0.R1.S07: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N3.C3.D0.R0.S08: Total Delay in PI ticks: TxDQS = 933, TxDQ = 900
N5.C2.D0.R0.S03: Write Level Fine Value = 443
N7.C3.D0.R1.S05: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N1.C3.D0.R1.S08: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N3.C3.D0.R0.S09: Total Delay in PI ticks: TxDQS = 997, TxDQ = 962
N5.C2.D0.R0.S04: Write Level Fine Value = 400
N7.C3.D0.R1.S06: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N1.C3.D0.R1.S00: Preamble found at Latency = 008
N3.C3.D0.R0.S10: Total Delay in PI ticks: TxDQS = 982, TxDQ = 947
N5.C2.D0.R0.S05: Write Level Fine Value = 431
N7.C3.D0.R1.S07: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N1.C3.D0.R1.S01: Preamble found at Latency = 008
N3.C3.D0.R0.S11: Total Delay in PI ticks: TxDQS = 971, TxDQ = 938
N5.C2.D0.R0.S06: Write Level Fine Value = 431
N7.C3.D0.R1.S08: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N1.C3.D0.R1.S06: Preamble found at Latency = 008
N3.C3.D0.R0.S12: Total Delay in PI ticks: TxDQS = 955, TxDQ = 919
N5.C2.D0.R0.S07: Write Level Fine Value = 454
N7.C3.D0.R1.S00: Preamble found at Latency = 008
N1.C3.D0.R1.S07: Preamble found at Latency = 008
N3.C3.D0.R0.S13: Total Delay in PI ticks: TxDQS = 920, TxDQ = 886
N5.C2.D0.R0.S08: Write Level Fine Value = 417
N7.C3.D0.R1.S01: Preamble found at Latency = 008
N1.C3.D0.R1.S00: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N3.C3.D0.R0.S14: Total Delay in PI ticks: TxDQS = 931, TxDQ = 898
N5.C2.D0.R0.S09: Write Level Fine Value = 483
N7.C3.D0.R1.S02: Preamble found at Latency = 008
N1.C3.D0.R1.S01: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N3.C3.D0.R0.S15: Total Delay in PI ticks: TxDQS = 948, TxDQ = 913
N5.C2.D0.R0.S10: Write Level Fine Value = 472
N7.C3.D0.R1.S05: Preamble found at Latency = 008
N1.C3.D0.R1.S02: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N3.C3.D0.R0.S16: Total Delay in PI ticks: TxDQS = 966, TxDQ = 935
N5.C2.D0.R0.S11: Write Level Fine Value = 461
N7.C3.D0.R1.S06: Preamble found at Latency = 008
N1.C3.D0.R1.S03: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N3.C3.D0.R0.S17: Total Delay in PI ticks: TxDQS = 933, TxDQ = 900
N5.C2.D0.R0.S12: Write Level Fine Value = 443
N7.C3.D0.R1.S07: Preamble found at Latency = 008
N1.C3.D0.R1.S04: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N3.C3.D0.R1.S00: Total Delay in PI ticks: TxDQS = 1000, TxDQ = 965
N5.C2.D0.R0.S13: Write Level Fine Value = 400
N7.C3.D0.R1.S00: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N1.C3.D0.R1.S05: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N3.C3.D0.R1.S01: Total Delay in PI ticks: TxDQS = 980, TxDQ = 946
N5.C2.D0.R0.S14: Write Level Fine Value = 431
N7.C3.D0.R1.S01: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N1.C3.D0.R1.S06: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N3.C3.D0.R1.S02: Total Delay in PI ticks: TxDQS = 970, TxDQ = 937
N5.C2.D0.R0.S15: Write Level Fine Value = 431
N7.C3.D0.R1.S02: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N1.C3.D0.R1.S07: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N3.C3.D0.R1.S03: Total Delay in PI ticks: TxDQS = 953, TxDQ = 918
N5.C2.D0.R0.S16: Write Level Fine Value = 451
N7.C3.D0.R1.S03: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N1.C3.D0.R1.S08: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N3.C3.D0.R1.S04: Total Delay in PI ticks: TxDQS = 919, TxDQ = 883
N5.C2.D0.R0.S17: Write Level Fine Value = 417
N7.C3.D0.R1.S04: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N1.C3.D0.R1.S02: Preamble found at Latency = 007
N3.C3.D0.R1.S05: Total Delay in PI ticks: TxDQS = 933, TxDQ = 899
N5.C2.D0.R1: ODT Override: 0x2
N7.C3.D0.R1.S05: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N1.C3.D0.R1.S03: Preamble found at Latency = 007
N3.C3.D0.R1.S06: Total Delay in PI ticks: TxDQS = 947, TxDQ = 911
N5.C2.D0.R1.S00: Write Level Fine Value = 483
N7.C3.D0.R1.S06: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N1.C3.D0.R1.S04: Preamble found at Latency = 007
N3.C3.D0.R1.S07: Total Delay in PI ticks: TxDQS = 967, TxDQ = 933
N5.C2.D0.R1.S01: Write Level Fine Value = 471
N7.C3.D0.R1.S07: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N1.C3.D0.R1.S05: Preamble found at Latency = 007
N3.C3.D0.R1.S08: Total Delay in PI ticks: TxDQS = 934, TxDQ = 901
N5.C2.D0.R1.S02: Write Level Fine Value = 459
N7.C3.D0.R1.S08: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N1.C3.D0.R1.S08: Preamble found at Latency = 007
N3.C3.D0.R1.S09: Total Delay in PI ticks: TxDQS = 996, TxDQ = 961
N5.C2.D0.R1.S03: Write Level Fine Value = 442
N7.C3.D0.R1.S03: Preamble found at Latency = 007
N1.C3.D0.R1.S00: Total Receive Enable Delay = 1352
N3.C3.D0.R1.S10: Total Delay in PI ticks: TxDQS = 982, TxDQ = 946
N5.C2.D0.R1.S04: Write Level Fine Value = 400
N7.C3.D0.R1.S04: Preamble found at Latency = 007
N1.C3.D0.R1.S01: Total Receive Enable Delay = 1331
N3.C3.D0.R1.S11: Total Delay in PI ticks: TxDQS = 970, TxDQ = 937
N5.C2.D0.R1.S05: Write Level Fine Value = 431
N7.C3.D0.R1.S08: Preamble found at Latency = 007
N1.C3.D0.R1.S02: Total Receive Enable Delay = 1299
N3.C3.D0.R1.S12: Total Delay in PI ticks: TxDQS = 953, TxDQ = 917
N5.C2.D0.R1.S06: Write Level Fine Value = 430
N7.C3.D0.R1.S00: Total Receive Enable Delay = 1361
N1.C3.D0.R1.S03: Total Receive Enable Delay = 1278
N3.C3.D0.R1.S13: Total Delay in PI ticks: TxDQS = 919, TxDQ = 885
N5.C2.D0.R1.S07: Write Level Fine Value = 452
N7.C3.D0.R1.S01: Total Receive Enable Delay = 1344
N1.C3.D0.R1.S04: Total Receive Enable Delay = 1278
N3.C3.D0.R1.S14: Total Delay in PI ticks: TxDQS = 933, TxDQ = 900
N5.C2.D0.R1.S08: Write Level Fine Value = 417
N7.C3.D0.R1.S02: Total Receive Enable Delay = 1313
N1.C3.D0.R1.S05: Total Receive Enable Delay = 1300
N3.C3.D0.R1.S15: Total Delay in PI ticks: TxDQS = 949, TxDQ = 914
N5.C2.D0.R1.S09: Write Level Fine Value = 483
N7.C3.D0.R1.S03: Total Receive Enable Delay = 1292
N1.C3.D0.R1.S06: Total Receive Enable Delay = 1320
N3.C3.D0.R1.S16: Total Delay in PI ticks: TxDQS = 967, TxDQ = 936
N5.C2.D0.R1.S10: Write Level Fine Value = 471
N7.C3.D0.R1.S04: Total Receive Enable Delay = 1285
N1.C3.D0.R1.S07: Total Receive Enable Delay = 1344
N3.C3.D0.R1.S17: Total Delay in PI ticks: TxDQS = 933, TxDQ = 900
N5.C2.D0.R1.S11: Write Level Fine Value = 462
N7.C3.D0.R1.S05: Total Receive Enable Delay = 1313
N1.C3.D0.R1.S08: Total Receive Enable Delay = 1260
N3: END WRITE LEVEL COARSE:
N5.C2.D0.R1.S12: Write Level Fine Value = 445
N7.C3.D0.R1.S06: Total Receive Enable Delay = 1335
N1.C3.D0.R1: Starting preamble search upper nibbles
N3: RunTrainStep: Final status = 0
N5.C2.D0.R1.S13: Write Level Fine Value = 400
N7.C3.D0.R1.S07: Total Receive Enable Delay = 1357
N1.C3.D0.R1.S09: PI = 040, PtrOffset = 004

END - Basic Write Level Training       Time         22202 ms
N5.C2.D0.R1.S14: Write Level Fine Value = 431
N7.C3.D0.R1.S08: Total Receive Enable Delay = 1270
N1.C3.D0.R1.S10: PI = 019, PtrOffset = 004

START - Basic Write DQ/DQS Training
N5.C2.D0.R1.S15: Write Level Fine Value = 431
N7.C3.D0.R1: Starting preamble search upper nibbles
N1.C3.D0.R1.S11: PI = 056, PtrOffset = 005
N3.C0.D0.R0.S00: wrcmd2dqsstartlatency: 04
N5.C2.D0.R1.S16: Write Level Fine Value = 454
N7.C3.D0.R1.S09: PI = 052, PtrOffset = 004
N1.C3.D0.R1.S12: PI = 035, PtrOffset = 005
N3.C0.D0.R0.S00: RdPtrOffsetTxDq: 06
N5.C2.D0.R1.S17: Write Level Fine Value = 417
N7.C3.D0.R1.S10: PI = 035, PtrOffset = 004
N1.C3.D0.R1.S13: PI = 029, PtrOffset = 005
N3.C0.D0.R0.S00: RdPtrOffsetTxDqs: 07
N5.C3.D0.R0: ODT Override: 0x1
N7.C3.D0.R1.S11: PI = 005, PtrOffset = 004
N1.C3.D0.R1.S14: PI = 050, PtrOffset = 005
N3.C0.D0.R0.S00: PiTxDqs: 36
N5.C3.D0.R0.S00: Write Level Fine Value = 491
N7.C3.D0.R1.S12: PI = 048, PtrOffset = 005
N1.C3.D0.R1.S15: PI = 013, PtrOffset = 004
N3.C0.D0.R0.S01: wrcmd2dqsstartlatency: 04
N5.C3.D0.R0.S01: Write Level Fine Value = 475
N7.C3.D0.R1.S13: PI = 037, PtrOffset = 005
N1.C3.D0.R1.S16: PI = 035, PtrOffset = 004
N3.C0.D0.R0.S01: RdPtrOffsetTxDq: 05
N5.C3.D0.R0.S02: Write Level Fine Value = 462
N7.C3.D0.R1.S14: PI = 001, PtrOffset = 004
N1.C3.D0.R1.S17: PI = 012, PtrOffset = 005
N3.C0.D0.R0.S01: RdPtrOffsetTxDqs: 07
N5.C3.D0.R0.S03: Write Level Fine Value = 447
N7.C3.D0.R1.S15: PI = 019, PtrOffset = 004
N1.C3.D0.R1.S09: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N3.C0.D0.R0.S01: PiTxDqs: 18
N5.C3.D0.R0.S04: Write Level Fine Value = 410
N7.C3.D0.R1.S16: PI = 044, PtrOffset = 004
N1.C3.D0.R1.S10: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N3.C0.D0.R0.S02: wrcmd2dqsstartlatency: 04
N5.C3.D0.R0.S05: Write Level Fine Value = 426
N7.C3.D0.R1.S17: PI = 022, PtrOffset = 005
N1.C3.D0.R1.S11: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N3.C0.D0.R0.S02: RdPtrOffsetTxDq: 05
N5.C3.D0.R0.S06: Write Level Fine Value = 440
N7.C3.D0.R1.S09: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N1.C3.D0.R1.S12: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N3.C0.D0.R0.S02: RdPtrOffsetTxDqs: 07
N5.C3.D0.R0.S07: Write Level Fine Value = 457
N7.C3.D0.R1.S10: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N1.C3.D0.R1.S13: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N3.C0.D0.R0.S02: PiTxDqs: 07
N5.C3.D0.R0.S08: Write Level Fine Value = 428
N7.C3.D0.R1.S11: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N1.C3.D0.R1.S14: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N3.C0.D0.R0.S03: wrcmd2dqsstartlatency: 04
N5.C3.D0.R0.S09: Write Level Fine Value = 491
N7.C3.D0.R1.S12: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N1.C3.D0.R1.S15: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N3.C0.D0.R0.S03: RdPtrOffsetTxDq: 05
N5.C3.D0.R0.S10: Write Level Fine Value = 477
N7.C3.D0.R1.S13: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N1.C3.D0.R1.S16: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N3.C0.D0.R0.S03: RdPtrOffsetTxDqs: 06
N5.C3.D0.R0.S11: Write Level Fine Value = 463
N7.C3.D0.R1.S14: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N1.C3.D0.R1.S17: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N3.C0.D0.R0.S03: PiTxDqs: 56
N5.C3.D0.R0.S12: Write Level Fine Value = 447
N7.C3.D0.R1.S15: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N1.C3.D0.R1.S09: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N3.C0.D0.R0.S04: wrcmd2dqsstartlatency: 04
N5.C3.D0.R0.S13: Write Level Fine Value = 412
N7.C3.D0.R1.S16: RcvEnCoarse: Latency = 010, RdPtr Offset = 4
N1.C3.D0.R1.S10: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N3.C0.D0.R0.S04: RdPtrOffsetTxDq: 04
N5.C3.D0.R0.S14: Write Level Fine Value = 426
N7.C3.D0.R1.S17: RcvEnCoarse: Latency = 010, RdPtr Offset = 5
N1.C3.D0.R1.S11: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N3.C0.D0.R0.S04: RdPtrOffsetTxDqs: 06
N5.C3.D0.R0.S15: Write Level Fine Value = 441
N7.C3.D0.R1.S09: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N1.C3.D0.R1.S12: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N3.C0.D0.R0.S04: PiTxDqs: 21
N5.C3.D0.R0.S16: Write Level Fine Value = 457
N7.C3.D0.R1.S10: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N1.C3.D0.R1.S13: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N3.C0.D0.R0.S05: wrcmd2dqsstartlatency: 04
N5.C3.D0.R0.S17: Write Level Fine Value = 428
N7.C3.D0.R1.S11: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N1.C3.D0.R1.S14: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N3.C0.D0.R0.S05: RdPtrOffsetTxDq: 05
N5.C3.D0.R1: ODT Override: 0x2
N7.C3.D0.R1.S12: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N1.C3.D0.R1.S15: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N3.C0.D0.R0.S05: RdPtrOffsetTxDqs: 06
N5.C3.D0.R1.S00: Write Level Fine Value = 492
N7.C3.D0.R1.S13: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N1.C3.D0.R1.S16: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N3.C0.D0.R0.S05: PiTxDqs: 39
N5.C3.D0.R1.S01: Write Level Fine Value = 475
N7.C3.D0.R1.S14: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N1.C3.D0.R1.S17: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N3.C0.D0.R0.S06: wrcmd2dqsstartlatency: 04
N5.C3.D0.R1.S02: Write Level Fine Value = 463
N7.C3.D0.R1.S15: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N1.C3.D0.R1.S09: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N3.C0.D0.R0.S06: RdPtrOffsetTxDq: 05
N5.C3.D0.R1.S03: Write Level Fine Value = 446
N7.C3.D0.R1.S16: RcvEnCoarse: Latency = 009, RdPtr Offset = 4
N1.C3.D0.R1.S10: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N3.C0.D0.R0.S06: RdPtrOffsetTxDqs: 06
N5.C3.D0.R1.S04: Write Level Fine Value = 411
N7.C3.D0.R1.S17: RcvEnCoarse: Latency = 009, RdPtr Offset = 5
N1.C3.D0.R1.S11: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N3.C0.D0.R0.S06: PiTxDqs: 42
N5.C3.D0.R1.S05: Write Level Fine Value = 427
N7.C3.D0.R1.S09: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N1.C3.D0.R1.S12: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N3.C0.D0.R0.S07: wrcmd2dqsstartlatency: 04
N5.C3.D0.R1.S06: Write Level Fine Value = 440
N7.C3.D0.R1.S10: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N1.C3.D0.R1.S13: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N3.C0.D0.R0.S07: RdPtrOffsetTxDq: 05
N5.C3.D0.R1.S07: Write Level Fine Value = 457
N7.C3.D0.R1.S11: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N1.C3.D0.R1.S14: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N3.C0.D0.R0.S07: RdPtrOffsetTxDqs: 06
N5.C3.D0.R1.S08: Write Level Fine Value = 428
N7.C3.D0.R1.S12: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N1.C3.D0.R1.S15: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N3.C0.D0.R0.S07: PiTxDqs: 60
N5.C3.D0.R1.S09: Write Level Fine Value = 490
N7.C3.D0.R1.S13: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N1.C3.D0.R1.S16: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N3.C0.D0.R0.S08: wrcmd2dqsstartlatency: 04
N5.C3.D0.R1.S10: Write Level Fine Value = 475
N7.C3.D0.R1.S14: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N1.C3.D0.R1.S17: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N3.C0.D0.R0.S08: RdPtrOffsetTxDq: 04
N5.C3.D0.R1.S11: Write Level Fine Value = 464
N7.C3.D0.R1.S15: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N1.C3.D0.R1.S09: Preamble found at Latency = 008
N3.C0.D0.R0.S08: RdPtrOffsetTxDqs: 06
N5.C3.D0.R1.S12: Write Level Fine Value = 448
N7.C3.D0.R1.S16: RcvEnCoarse: Latency = 008, RdPtr Offset = 4
N1.C3.D0.R1.S10: Preamble found at Latency = 008
N3.C0.D0.R0.S08: PiTxDqs: 30
N5.C3.D0.R1.S13: Write Level Fine Value = 411
N7.C3.D0.R1.S17: RcvEnCoarse: Latency = 008, RdPtr Offset = 5
N1.C3.D0.R1.S15: Preamble found at Latency = 008
N3.C0.D0.R0.S09: wrcmd2dqsstartlatency: 04
N5.C3.D0.R1.S14: Write Level Fine Value = 426
N7.C3.D0.R1.S09: Preamble found at Latency = 008
N1.C3.D0.R1.S16: Preamble found at Latency = 008
N3.C0.D0.R0.S09: RdPtrOffsetTxDq: 06
N5.C3.D0.R1.S15: Write Level Fine Value = 440
N7.C3.D0.R1.S10: Preamble found at Latency = 008
N1.C3.D0.R1.S09: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N3.C0.D0.R0.S09: RdPtrOffsetTxDqs: 07
N5.C3.D0.R1.S16: Write Level Fine Value = 458
N7.C3.D0.R1.S11: Preamble found at Latency = 008
N1.C3.D0.R1.S10: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N3.C0.D0.R0.S09: PiTxDqs: 36
N5.C3.D0.R1.S17: Write Level Fine Value = 427
N7.C3.D0.R1.S14: Preamble found at Latency = 008
N1.C3.D0.R1.S11: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N3.C0.D0.R0.S10: wrcmd2dqsstartlatency: 04
N5: END WRITE LEVEL:
N7.C3.D0.R1.S15: Preamble found at Latency = 008
N1.C3.D0.R1.S12: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N3.C0.D0.R0.S10: RdPtrOffsetTxDq: 05
N5: START WRITE LEVEL COARSE:
N7.C3.D0.R1.S16: Preamble found at Latency = 008
N1.C3.D0.R1.S13: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N3.C0.D0.R0.S10: RdPtrOffsetTxDqs: 07
N7.C3.D0.R1.S09: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N1.C3.D0.R1.S14: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N3.C0.D0.R0.S10: PiTxDqs: 18
N5.C0.D0.R0: Write Training Coarse, lower nibbles / bytes
N7.C3.D0.R1.S10: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N1.C3.D0.R1.S15: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N3.C0.D0.R0.S11: wrcmd2dqsstartlatency: 04
N5.C0.D0.R0.S00: Dq Delay estimate: 447
N7.C3.D0.R1.S11: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N1.C3.D0.R1.S16: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N3.C0.D0.R0.S11: RdPtrOffsetTxDq: 05
N5.C0.D0.R0.S01: Dq Delay estimate: 432
N7.C3.D0.R1.S12: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N1.C3.D0.R1.S17: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N3.C0.D0.R0.S11: RdPtrOffsetTxDqs: 07
N5.C0.D0.R0.S02: Dq Delay estimate: 416
N7.C3.D0.R1.S13: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N1.C3.D0.R1.S11: Preamble found at Latency = 007
N3.C0.D0.R0.S11: PiTxDqs: 07
N5.C0.D0.R0.S03: Dq Delay estimate: 403
N7.C3.D0.R1.S14: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N1.C3.D0.R1.S12: Preamble found at Latency = 007
N3.C0.D0.R0.S12: wrcmd2dqsstartlatency: 04
N5.C0.D0.R0.S04: Dq Delay estimate: 375
N7.C3.D0.R1.S15: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N1.C3.D0.R1.S13: Preamble found at Latency = 007
N3.C0.D0.R0.S12: RdPtrOffsetTxDq: 05
N5.C0.D0.R0.S05: Dq Delay estimate: 388
N7.C3.D0.R1.S16: RcvEnCoarse: Latency = 007, RdPtr Offset = 4
N1.C3.D0.R1.S14: Preamble found at Latency = 007
N3.C0.D0.R0.S12: RdPtrOffsetTxDqs: 06
N5.C0.D0.R0.S06: Dq Delay estimate: 395
N7.C3.D0.R1.S17: RcvEnCoarse: Latency = 007, RdPtr Offset = 5
N1.C3.D0.R1.S17: Preamble found at Latency = 007
N3.C0.D0.R0.S12: PiTxDqs: 56
N5.C0.D0.R0.S07: Dq Delay estimate: 412
N7.C3.D0.R1.S12: Preamble found at Latency = 007
N1.C3.D0.R1: Preamble found for all upper nibbles, adjusting Pi, Offset to center into preamble
N3.C0.D0.R0.S13: wrcmd2dqsstartlatency: 04
N5.C0.D0.R0.S08: Dq Delay estimate: 377
N7.C3.D0.R1.S13: Preamble found at Latency = 007
N1.C3.D0.R1.S09: Total Receive Enable Delay = 1352
N3.C0.D0.R0.S13: RdPtrOffsetTxDq: 04
ACCM: 0F 9F9F9F0F 9F0F0F0F
N7.C3.D0.R1.S17: Preamble found at Latency = 007
N1.C3.D0.R1.S10: Total Receive Enable Delay = 1331
N3.C0.D0.R0.S13: RdPtrOffsetTxDqs: 06
ACCM: 0F 9F9F9F0F 9F0F0F0F
N7.C3.D0.R1: Preamble found for all upper nibbles, adjusting Pi, Offset to center into preamble
N1.C3.D0.R1.S11: Total Receive Enable Delay = 1304
N3.C0.D0.R0.S13: PiTxDqs: 22
ACCM: 0F 9F9F9F0F 9FFFFFFF
N7.C3.D0.R1.S09: Total Receive Enable Delay = 1364
N1.C3.D0.R1.S12: Total Receive Enable Delay = 1283
N3.C0.D0.R0.S14: wrcmd2dqsstartlatency: 04
ACCM: 0F 9F9F9F0F 9FFFFFFF
N7.C3.D0.R1.S10: Total Receive Enable Delay = 1347
N1.C3.D0.R1.S13: Total Receive Enable Delay = 1277
N3.C0.D0.R0.S14: RdPtrOffsetTxDq: 05
N5.C0.D0.R0: CheckMCTest: result = 0x1DFFF
N7.C3.D0.R1.S11: Total Receive Enable Delay = 1317
N1.C3.D0.R1.S14: Total Receive Enable Delay = 1298
N3.C0.D0.R0.S14: RdPtrOffsetTxDqs: 06
ACCM: 0F FF9FDF0F DF0F0F0F
N7.C3.D0.R1.S12: Total Receive Enable Delay = 1296
N1.C3.D0.R1.S15: Total Receive Enable Delay = 1325
N3.C0.D0.R0.S14: PiTxDqs: 38
ACCM: 0F FF9FDF0F DF0F0F0F
N7.C3.D0.R1.S13: Total Receive Enable Delay = 1285
N1.C3.D0.R1.S16: Total Receive Enable Delay = 1347
N3.C0.D0.R0.S15: wrcmd2dqsstartlatency: 04
ACCM: 0F FF9FDF0F DFFFFFFF
N7.C3.D0.R1.S14: Total Receive Enable Delay = 1313
N1.C3.D0.R1.S17: Total Receive Enable Delay = 1260
N3.C0.D0.R0.S15: RdPtrOffsetTxDq: 05
ACCM: 0F FF9FDF0F DFFFFFFF
N7.C3.D0.R1.S15: Total Receive Enable Delay = 1331
START_DATA_REC_EN
N3.C0.D0.R0.S15: RdPtrOffsetTxDqs: 06
N5.C0.D0.R0: CheckMCTest: result = 0x1DFFF
N7.C3.D0.R1.S16: Total Receive Enable Delay = 1356
N1.C3.S00: RdCmd2RcvEnLatency = 9, RdPtrOffsetRcvEn = 5
N3.C0.D0.R0.S15: PiTxDqs: 42
ACCM: 0F DFDFDF0F DF0F0F0F
N7.C3.D0.R1.S17: Total Receive Enable Delay = 1270
N1.C3.S01: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N3.C0.D0.R0.S16: wrcmd2dqsstartlatency: 04
ACCM: 0F DFDFDF0F DF0F0F0F
START_DATA_REC_EN
N1.C3.S02: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N3.C0.D0.R0.S16: RdPtrOffsetTxDq: 05
ACCM: 00 D0D0D000 D0F0F0FB
N7.C3.S00: RdCmd2RcvEnLatency = 9, RdPtrOffsetRcvEn = 5
N1.C3.S03: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 5
N3.C0.D0.R0.S16: RdPtrOffsetTxDqs: 06
ACCM: 00 D0D0D000 D0F0F0FB
N7.C3.S01: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N1.C3.S04: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 5
N3.C0.D0.R0.S16: PiTxDqs: 60
N5.C0.D0.R0: CheckMCTest: result = 0x1DFFF
N7.C3.S02: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N1.C3.S05: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N3.C0.D0.R0.S17: wrcmd2dqsstartlatency: 04
ACCM: 0F DFDFDF0F DF0F0F0F
N7.C3.S03: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N1.C3.S06: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N3.C0.D0.R0.S17: RdPtrOffsetTxDq: 04
ACCM: 0F DFDFDF0F DF0F0F0F
N7.C3.S04: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N1.C3.S07: RdCmd2RcvEnLatency = 9, RdPtrOffsetRcvEn = 5
N3.C0.D0.R0.S17: RdPtrOffsetTxDqs: 06
ACCM: 00 D0D0D000 D0F0F0FF
N7.C3.S05: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N1.C3.S08: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 5
N3.C0.D0.R0.S17: PiTxDqs: 30
ACCM: 00 D0D0D000 D0F0F0FF
N7.C3.S06: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N1.C3.S09: RdCmd2RcvEnLatency = 9, RdPtrOffsetRcvEn = 5
N3.C0.D0.R0.S00: RdPtrOffsetTxDq: 07
N5.C0.D0.R0: CheckMCTest: result = 0x1DFFF
N7.C3.S07: RdCmd2RcvEnLatency = 9, RdPtrOffsetRcvEn = 5
N1.C3.S10: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N3.C0.D0.R0.S01: RdPtrOffsetTxDq: 06
ACCM: 00 D0D0D000 D0000000
N7.C3.S08: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 5
N1.C3.S11: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N3.C0.D0.R0.S02: RdPtrOffsetTxDq: 06
ACCM: 00 D0D0D000 D0000000
N7.C3.S09: RdCmd2RcvEnLatency = 9, RdPtrOffsetRcvEn = 5
N1.C3.S12: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 5
N3.C0.D0.R0.S03: RdPtrOffsetTxDq: 06
ACCM: 00 D0D0D000 D0F0F0F0
N7.C3.S10: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N1.C3.S13: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 5
N3.C0.D0.R0.S04: RdPtrOffsetTxDq: 05
ACCM: 00 D0D0D000 D0F0F0F0
N7.C3.S11: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N1.C3.S14: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N3.C0.D0.R0.S05: RdPtrOffsetTxDq: 06
N5.C0.D0.R0: CheckMCTest: result = 0x1DE00
N7.C3.S12: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N1.C3.S15: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N3.C0.D0.R0.S06: RdPtrOffsetTxDq: 06
ACCM: 00 F0D0D000 D0000000
N7.C3.S13: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N1.C3.S16: RdCmd2RcvEnLatency = 9, RdPtrOffsetRcvEn = 5
N3.C0.D0.R0.S07: RdPtrOffsetTxDq: 06
ACCM: 00 F0D0D000 D0000000
N7.C3.S14: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N1.C3.S17: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 5
N3.C0.D0.R0.S08: RdPtrOffsetTxDq: 05
ACCM: 00 F0D0D000 D0F0F0F0
N7.C3.S15: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 6
N1.C3.D0.R0.S00: RcvEn: plus1 = 1, minus1 = 0, PI = 07, DB = 1
N3.C0.D0.R0.S09: RdPtrOffsetTxDq: 07
ACCM: 00 F0D0D000 D0F0F0F0
N7.C3.S16: RdCmd2RcvEnLatency = 9, RdPtrOffsetRcvEn = 5
N1.C3.D0.R0.S01: RcvEn: plus1 = 1, minus1 = 0, PI = 51, DB = 1
N3.C0.D0.R0.S10: RdPtrOffsetTxDq: 06
N5.C0.D0.R0: CheckMCTest: result = 0x1DE00
N7.C3.S17: RdCmd2RcvEnLatency = 8, RdPtrOffsetRcvEn = 5
N1.C3.D0.R0.S02: RcvEn: plus1 = 1, minus1 = 0, PI = 20, DB = 0
N3.C0.D0.R0.S11: RdPtrOffsetTxDq: 06
N5.C0.D0.R0.S00: Offset Found: RdPtrOffsetDqs = 007
N7.C3.D0.R0.S00: RcvEn: plus1 = 1, minus1 = 0, PI = 17, DB = 0
N1.C3.D0.R0.S03: RcvEn: plus1 = 1, minus1 = 0, PI = 62, DB = 1
N3.C0.D0.R0.S12: RdPtrOffsetTxDq: 06
N5.C0.D0.R0.S01: Offset Found: RdPtrOffsetDqs = 007
N7.C3.D0.R0.S01: RcvEn: plus1 = 1, minus1 = 0, PI = 63, DB = 1
N1.C3.D0.R0.S04: RcvEn: plus1 = 1, minus1 = 0, PI = 62, DB = 1
N3.C0.D0.R0.S13: RdPtrOffsetTxDq: 05
N5.C0.D0.R0.S02: Offset Found: RdPtrOffsetDqs = 007
N7.C3.D0.R0.S02: RcvEn: plus1 = 1, minus1 = 0, PI = 32, DB = 0
N1.C3.D0.R0.S05: RcvEn: plus1 = 1, minus1 = 0, PI = 20, DB = 0
N3.C0.D0.R0.S14: RdPtrOffsetTxDq: 06
N5.C0.D0.R0.S03: Offset Found: RdPtrOffsetDqs = 006
N7.C3.D0.R0.S03: RcvEn: plus1 = 1, minus1 = 0, PI = 12, DB = 1
N1.C3.D0.R0.S06: RcvEn: plus1 = 1, minus1 = 0, PI = 41, DB = 0
N3.C0.D0.R0.S15: RdPtrOffsetTxDq: 06
N5.C0.D0.R0.S04: Offset Found: RdPtrOffsetDqs = 006
N7.C3.D0.R0.S04: RcvEn: plus1 = 1, minus1 = 0, PI = 05, DB = 1
N1.C3.D0.R0.S07: RcvEn: plus1 = 1, minus1 = 0, PI = 00, DB = 1
N3.C0.D0.R0.S16: RdPtrOffsetTxDq: 06
N5.C0.D0.R0.S05: Offset Found: RdPtrOffsetDqs = 006
N7.C3.D0.R0.S05: RcvEn: plus1 = 1, minus1 = 0, PI = 32, DB = 0
N1.C3.D0.R0.S08: RcvEn: plus1 = 1, minus1 = 0, PI = 43, DB = 0
N3.C0.D0.R0.S17: RdPtrOffsetTxDq: 05
N5.C0.D0.R0.S06: Offset Found: RdPtrOffsetDqs = 006
N7.C3.D0.R0.S06: RcvEn: plus1 = 1, minus1 = 0, PI = 54, DB = 1
N1.C3.D0.R0.S09: RcvEn: plus1 = 1, minus1 = 0, PI = 09, DB = 1
N3.C0.D0.R0.S00: RdPtrOffsetTxDq: 08
N5.C0.D0.R0.S07: Offset Found: RdPtrOffsetDqs = 006
N7.C3.D0.R0.S07: RcvEn: plus1 = 1, minus1 = 0, PI = 12, DB = 1
N1.C3.D0.R0.S10: RcvEn: plus1 = 1, minus1 = 0, PI = 52, DB = 1
N3.C0.D0.R0.S01: RdPtrOffsetTxDq: 07
N5.C0.D0.R0.S08: Offset Found: RdPtrOffsetDqs = 006
N7.C3.D0.R0.S08: RcvEn: plus1 = 1, minus1 = 0, PI = 54, DB = 1
N1.C3.D0.R0.S11: RcvEn: plus1 = 1, minus1 = 0, PI = 23, DB = 0
N3.C0.D0.R0.S02: RdPtrOffsetTxDq: 07
N5.C0.D0.R0: Write Training Coarse, upper nibbles
N7.C3.D0.R0.S09: RcvEn: plus1 = 1, minus1 = 0, PI = 20, DB = 0
N1.C3.D0.R0.S12: RcvEn: plus1 = 0, minus1 = 1, PI = 05, DB = 1
N3.C0.D0.R0.S03: RdPtrOffsetTxDq: 07
N5.C0.D0.R0.S09: Dq Delay estimate: 446
N7.C3.D0.R0.S10: RcvEn: plus1 = 0, minus1 = 1, PI = 01, DB = 1
N1.C3.D0.R0.S13: RcvEn: plus1 = 1, minus1 = 0, PI = 60, DB = 1
N3.C0.D0.R0.S04: RdPtrOffsetTxDq: 06
N5.C0.D0.R0.S10: Dq Delay estimate: 432
N7.C3.D0.R0.S11: RcvEn: plus1 = 1, minus1 = 0, PI = 35, DB = 0
N1.C3.D0.R0.S14: RcvEn: plus1 = 1, minus1 = 0, PI = 18, DB = 0
N3.C0.D0.R0.S05: RdPtrOffsetTxDq: 07
N5.C0.D0.R0.S11: Dq Delay estimate: 423
N7.C3.D0.R0.S12: RcvEn: plus1 = 1, minus1 = 0, PI = 16, DB = 0
N1.C3.D0.R0.S15: RcvEn: plus1 = 1, minus1 = 0, PI = 43, DB = 0
N3.C0.D0.R0.S06: RdPtrOffsetTxDq: 07
N5.C0.D0.R0.S12: Dq Delay estimate: 404
N7.C3.D0.R0.S13: RcvEn: plus1 = 1, minus1 = 0, PI = 05, DB = 1
N1.C3.D0.R0.S16: RcvEn: plus1 = 1, minus1 = 0, PI = 04, DB = 1
N3.C0.D0.R0.S07: RdPtrOffsetTxDq: 07
N5.C0.D0.R0.S13: Dq Delay estimate: 374
N7.C3.D0.R0.S14: RcvEn: plus1 = 1, minus1 = 0, PI = 33, DB = 0
N1.C3.D0.R0.S17: RcvEn: plus1 = 1, minus1 = 0, PI = 45, DB = 0
N3.C0.D0.R0.S08: RdPtrOffsetTxDq: 06
N5.C0.D0.R0.S14: Dq Delay estimate: 389
N7.C3.D0.R0.S15: RcvEn: plus1 = 1, minus1 = 0, PI = 51, DB = 1
N1.C3.D0.R1.S00: RcvEn: plus1 = 1, minus1 = 0, PI = 07, DB = 1
N3.C0.D0.R0.S09: RdPtrOffsetTxDq: 08
N5.C0.D0.R0.S15: Dq Delay estimate: 396
N7.C3.D0.R0.S16: RcvEn: plus1 = 1, minus1 = 0, PI = 12, DB = 1
N1.C3.D0.R1.S01: RcvEn: plus1 = 1, minus1 = 0, PI = 51, DB = 1
N3.C0.D0.R0.S10: RdPtrOffsetTxDq: 07
N5.C0.D0.R0.S16: Dq Delay estimate: 411
N7.C3.D0.R0.S17: RcvEn: plus1 = 1, minus1 = 0, PI = 55, DB = 1
N1.C3.D0.R1.S02: RcvEn: plus1 = 1, minus1 = 0, PI = 20, DB = 0
N3.C0.D0.R0.S11: RdPtrOffsetTxDq: 07
N5.C0.D0.R0.S17: Dq Delay estimate: 377
N7.C3.D0.R1.S00: RcvEn: plus1 = 1, minus1 = 0, PI = 17, DB = 0
N1.C3.D0.R1.S03: RcvEn: plus1 = 1, minus1 = 0, PI = 62, DB = 1
N3.C0.D0.R0.S12: RdPtrOffsetTxDq: 07
ACCM: F0 F0F0F0F0 F0F0F0F0
N7.C3.D0.R1.S01: RcvEn: plus1 = 1, minus1 = 0, PI = 63, DB = 1
N1.C3.D0.R1.S04: RcvEn: plus1 = 1, minus1 = 0, PI = 62, DB = 1
N3.C0.D0.R0.S13: RdPtrOffsetTxDq: 06
ACCM: F0 F0F0F0F0 F0F0F0F0
N7.C3.D0.R1.S02: RcvEn: plus1 = 1, minus1 = 0, PI = 32, DB = 0
N1.C3.D0.R1.S05: RcvEn: plus1 = 1, minus1 = 0, PI = 20, DB = 0
N3.C0.D0.R0.S14: RdPtrOffsetTxDq: 07
ACCM: F0 F0F0F0F0 F0F0F0F0
N7.C3.D0.R1.S03: RcvEn: plus1 = 1, minus1 = 0, PI = 12, DB = 1
N1.C3.D0.R1.S06: RcvEn: plus1 = 1, minus1 = 0, PI = 41, DB = 0
N3.C0.D0.R0.S15: RdPtrOffsetTxDq: 07
ACCM: F0 F0F0F0F0 F0F0F0F0
N7.C3.D0.R1.S04: RcvEn: plus1 = 1, minus1 = 0, PI = 05, DB = 1
N1.C3.D0.R1.S07: RcvEn: plus1 = 1, minus1 = 0, PI = 00, DB = 1
N3.C0.D0.R0.S16: RdPtrOffsetTxDq: 07
N5.C0.D0.R0: CheckMCTest: result = 0x3FE00
N7.C3.D0.R1.S05: RcvEn: plus1 = 1, minus1 = 0, PI = 32, DB = 0
N1.C3.D0.R1.S08: RcvEn: plus1 = 1, minus1 = 0, PI = 43, DB = 0
N3.C0.D0.R0.S17: RdPtrOffsetTxDq: 06
ACCM: F0 F0F0F0F0 F0F0F0F0
N7.C3.D0.R1.S06: RcvEn: plus1 = 1, minus1 = 0, PI = 54, DB = 1
N1.C3.D0.R1.S09: RcvEn: plus1 = 1, minus1 = 0, PI = 09, DB = 1
N3.C0.D0.R0.S00: Total Delay in PI ticks: TxDQ = 963
ACCM: F0 F0F0F0F0 F0F0F0F0
N7.C3.D0.R1.S07: RcvEn: plus1 = 1, minus1 = 0, PI = 12, DB = 1
N1.C3.D0.R1.S10: RcvEn: plus1 = 1, minus1 = 0, PI = 52, DB = 1
N3.C0.D0.R0.S01: Total Delay in PI ticks: TxDQ = 945
ACCM: F0 F0F0F0F0 F0F0F0F0
N7.C3.D0.R1.S08: RcvEn: plus1 = 1, minus1 = 0, PI = 54, DB = 1
N1.C3.D0.R1.S11: RcvEn: plus1 = 1, minus1 = 0, PI = 23, DB = 0
N3.C0.D0.R0.S02: Total Delay in PI ticks: TxDQ = 932
ACCM: F0 F0F0F0F0 F0F0F0F0
N7.C3.D0.R1.S09: RcvEn: plus1 = 1, minus1 = 0, PI = 20, DB = 0
N1.C3.D0.R1.S12: RcvEn: plus1 = 0, minus1 = 1, PI = 05, DB = 1
N3.C0.D0.R0.S03: Total Delay in PI ticks: TxDQ = 917
N5.C0.D0.R0: CheckMCTest: result = 0x3FE00
N7.C3.D0.R1.S10: RcvEn: plus1 = 0, minus1 = 1, PI = 01, DB = 1
N1.C3.D0.R1.S13: RcvEn: plus1 = 1, minus1 = 0, PI = 60, DB = 1
N3.C0.D0.R0.S04: Total Delay in PI ticks: TxDQ = 884
ACCM: F0 F0F0F0F0 F0F0F0F0
N7.C3.D0.R1.S11: RcvEn: plus1 = 1, minus1 = 0, PI = 35, DB = 0
N1.C3.D0.R1.S14: RcvEn: plus1 = 1, minus1 = 0, PI = 18, DB = 0
N3.C0.D0.R0.S05: Total Delay in PI ticks: TxDQ = 901
ACCM: F0 F0F0F0F0 F0F0F0F0
N7.C3.D0.R1.S12: RcvEn: plus1 = 1, minus1 = 0, PI = 16, DB = 0
N1.C3.D0.R1.S15: RcvEn: plus1 = 1, minus1 = 0, PI = 43, DB = 0
N3.C0.D0.R0.S06: Total Delay in PI ticks: TxDQ = 905
ACCM: 00 0000B000 00B00000
N7.C3.D0.R1.S13: RcvEn: plus1 = 1, minus1 = 0, PI = 05, DB = 1
N1.C3.D0.R1.S16: RcvEn: plus1 = 1, minus1 = 0, PI = 04, DB = 1
N3.C0.D0.R0.S07: Total Delay in PI ticks: TxDQ = 924
ACCM: 00 0000B000 00B00000
N7.C3.D0.R1.S14: RcvEn: plus1 = 1, minus1 = 0, PI = 33, DB = 0
N1.C3.D0.R1.S17: RcvEn: plus1 = 1, minus1 = 0, PI = 45, DB = 0
N3.C0.D0.R0.S08: Total Delay in PI ticks: TxDQ = 891
N5.C0.D0.R0: CheckMCTest: result = 0x3FE00
N7.C3.D0.R1.S15: RcvEn: plus1 = 1, minus1 = 0, PI = 51, DB = 1
STOP_DATA_REC_EN
N3.C0.D0.R0.S09: Total Delay in PI ticks: TxDQ = 963
ACCM: F0 F0F0F0F0 F0F0F0F0
N7.C3.D0.R1.S16: RcvEn: plus1 = 1, minus1 = 0, PI = 12, DB = 1
N1.C0.D0.R0.S00: StoreJckWorstRank: worst rank = 0, greatestDelay = 1304
N3.C0.D0.R0.S10: Total Delay in PI ticks: TxDQ = 945
ACCM: F0 F0F0F0F0 F0F0F0F0
N7.C3.D0.R1.S17: RcvEn: plus1 = 1, minus1 = 0, PI = 55, DB = 1
N1.C0.D0.R0.S07: StoreJckWorstRank: worst rank = 0, greatestDelay = 1307
N3.C0.D0.R0.S11: Total Delay in PI ticks: TxDQ = 933
ACCM: 00 0000F000 00F00000
STOP_DATA_REC_EN
N1.C1.D0.R0.S00: StoreJckWorstRank: worst rank = 0, greatestDelay = 1355
N3.C0.D0.R0.S12: Total Delay in PI ticks: TxDQ = 918
ACCM: 00 0000F000 00F00000
N7.C0.D0.R0.S00: StoreJckWorstRank: worst rank = 0, greatestDelay = 1302
N1.C0: StoreJckWorstRank: final value: worst rank = 0
N3.C0.D0.R0.S13: Total Delay in PI ticks: TxDQ = 883
N5.C0.D0.R0: CheckMCTest: result = 0x3FE00
N7.C0.D0.R0.S07: StoreJckWorstRank: worst rank = 0, greatestDelay = 1308
N1.C2.D0.R0.S00: StoreJckWorstRank: worst rank = 0, greatestDelay = 1314
N3.C0.D0.R0.S14: Total Delay in PI ticks: TxDQ = 900
N5.C0.D0.R0: CheckMCTest: passed
N7.C1.D0.R0.S00: StoreJckWorstRank: worst rank = 0, greatestDelay = 1363
N1.C3.D0.R0.S00: StoreJckWorstRank: worst rank = 0, greatestDelay = 1351
N3.C0.D0.R0.S15: Total Delay in PI ticks: TxDQ = 904
N5.C0.D0.R0: CheckMCTest: passed
N7.C1.D0.R0.S09: StoreJckWorstRank: worst rank = 0, greatestDelay = 1364
N1.C3.D0.R0.S09: StoreJckWorstRank: worst rank = 0, greatestDelay = 1354
N3.C0.D0.R0.S16: Total Delay in PI ticks: TxDQ = 924
N5.C0.D0.R0.S09: Offset Found: RdPtrOffsetDqs = 007
N7.C1.D0.R1.S09: StoreJckWorstRank: worst rank = 1, greatestDelay = 1365
N1.C1: StoreJckWorstRank: final value: worst rank = 0
N3.C0.D0.R0.S17: Total Delay in PI ticks: TxDQ = 891
N5.C0.D0.R0.S10: Offset Found: RdPtrOffsetDqs = 007
N7.C0: StoreJckWorstRank: final value: worst rank = 1
N1: RunTrainStep: Final status = 0
N3.C0.D0.R1.S00: wrcmd2dqsstartlatency: 04
N5.C0.D0.R0.S11: Offset Found: RdPtrOffsetDqs = 007
N7.C2.D0.R0.S00: StoreJckWorstRank: worst rank = 0, greatestDelay = 1309

END - Basic Receive Enable Training    Time         32139 ms
N3.C0.D0.R1.S00: RdPtrOffsetTxDq: 06
N5.C0.D0.R0.S12: Offset Found: RdPtrOffsetDqs = 006
N7.C3.D0.R0.S00: StoreJckWorstRank: worst rank = 0, greatestDelay = 1362
N1.C0.S00: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  6
N3.C0.D0.R1.S00: RdPtrOffsetTxDqs: 07
N5.C0.D0.R0.S13: Offset Found: RdPtrOffsetDqs = 006
N7.C3.D0.R0.S09: StoreJckWorstRank: worst rank = 0, greatestDelay = 1364
N1.C0.S01: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  6
N3.C0.D0.R1.S00: PiTxDqs: 37
N5.C0.D0.R0.S14: Offset Found: RdPtrOffsetDqs = 006
N7.C1: StoreJckWorstRank: final value: worst rank = 0
N1.C0.S02: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  5
N3.C0.D0.R1.S01: wrcmd2dqsstartlatency: 04
N5.C0.D0.R0.S15: Offset Found: RdPtrOffsetDqs = 006
N7: RunTrainStep: Final status = 0
N1.C0.S03: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  5
N3.C0.D0.R1.S01: RdPtrOffsetTxDq: 05
N5.C0.D0.R0.S16: Offset Found: RdPtrOffsetDqs = 006

END - Basic Receive Enable Training    Time         32163 ms
N1.C0.S04: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  5
N3.C0.D0.R1.S01: RdPtrOffsetTxDqs: 07
N5.C0.D0.R0.S17: Offset Found: RdPtrOffsetDqs = 006
N7.C0.S00: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  6
N1.C0.S05: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  5
N3.C0.D0.R1.S01: PiTxDqs: 19
N5.C0.D0.R1: Write Training Coarse, lower nibbles / bytes
N7.C0.S01: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  6
N1.C0.S06: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  6
N3.C0.D0.R1.S02: wrcmd2dqsstartlatency: 04
N5.C0.D0.R1.S00: Dq Delay estimate: 448
N7.C0.S02: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  5
N1.C0.S07: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  6
N3.C0.D0.R1.S02: RdPtrOffsetTxDq: 05
N5.C0.D0.R1.S01: Dq Delay estimate: 432
N7.C0.S03: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  5
N1.C0.S08: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  5
N3.C0.D0.R1.S02: RdPtrOffsetTxDqs: 07
N5.C0.D0.R1.S02: Dq Delay estimate: 414
N7.C0.S04: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  5
N1.C1.S00: SuppressionWindowAdjustmentRd: latency =  9, rdptroffset =  5
N3.C0.D0.R1.S02: PiTxDqs: 06
N5.C0.D0.R1.S03: Dq Delay estimate: 403
N7.C0.S05: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  5
N1.C1.S01: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  6
N3.C0.D0.R1.S03: wrcmd2dqsstartlatency: 04
N5.C0.D0.R1.S04: Dq Delay estimate: 373
N7.C0.S06: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  6
N1.C1.S02: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  6
N3.C0.D0.R1.S03: RdPtrOffsetTxDq: 05
N5.C0.D0.R1.S05: Dq Delay estimate: 387
N7.C0.S07: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  6
N1.C1.S03: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  6
N3.C0.D0.R1.S03: RdPtrOffsetTxDqs: 06
N5.C0.D0.R1.S06: Dq Delay estimate: 395
N7.C0.S08: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  5
N1.C1.S04: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  5
N3.C0.D0.R1.S03: PiTxDqs: 55
N5.C0.D0.R1.S07: Dq Delay estimate: 411
N7.C1.S00: SuppressionWindowAdjustmentRd: latency =  9, rdptroffset =  5
N1.C1.S05: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  6
N3.C0.D0.R1.S04: wrcmd2dqsstartlatency: 04
N5.C0.D0.R1.S08: Dq Delay estimate: 375
N7.C1.S01: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  6
N1.C1.S06: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  6
N3.C0.D0.R1.S04: RdPtrOffsetTxDq: 04
ACCM: 0F 0F0F0F0F 0F0F0F0F
N7.C1.S02: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  6
N1.C1.S07: SuppressionWindowAdjustmentRd: latency =  9, rdptroffset =  5
N3.C0.D0.R1.S04: RdPtrOffsetTxDqs: 06
ACCM: 0F 0F0F0F0F 0F0F0F0F
N7.C1.S03: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  6
N1.C1.S08: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  5
N3.C0.D0.R1.S04: PiTxDqs: 21
ACCM: 0F 0F0F0F0F 0F0F0F0F
N7.C1.S04: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  6
N1.C2.S00: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  6
N3.C0.D0.R1.S05: wrcmd2dqsstartlatency: 04
ACCM: 0F 0F0F0F0F 0F0F0F0F
N7.C1.S05: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  6
N1.C2.S01: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  6
N3.C0.D0.R1.S05: RdPtrOffsetTxDq: 05
N5.C0.D0.R1: CheckMCTest: result = 0x1FF
N7.C1.S06: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  6
N1.C2.S02: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  5
N3.C0.D0.R1.S05: RdPtrOffsetTxDqs: 06
ACCM: 0F 0F0F0F0F 0F0F0F0F
N7.C1.S07: SuppressionWindowAdjustmentRd: latency =  9, rdptroffset =  5
N1.C2.S03: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  5
N3.C0.D0.R1.S05: PiTxDqs: 38
ACCM: 0F 0F0F0F0F 0F0F0F0F
N7.C1.S08: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  5
N1.C2.S04: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  5
N3.C0.D0.R1.S06: wrcmd2dqsstartlatency: 04
ACCM: 0F 0F0F0F0F 0F0F0F0F
N7.C2.S00: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  6
N1.C2.S05: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  5
N3.C0.D0.R1.S06: RdPtrOffsetTxDq: 05
ACCM: 0F 0F0F0F0F 0F0F0F0F
N7.C2.S01: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  6
N1.C2.S06: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  6
N3.C0.D0.R1.S06: RdPtrOffsetTxDqs: 06
N5.C0.D0.R1: CheckMCTest: result = 0x1FF
N7.C2.S02: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  5
N1.C2.S07: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  6
N3.C0.D0.R1.S06: PiTxDqs: 41
ACCM: 0F 0F0F0F0F 0F0F0F0F
N7.C2.S03: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  5
N1.C2.S08: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  5
N3.C0.D0.R1.S07: wrcmd2dqsstartlatency: 04
ACCM: 0F 0F0F0F0F 0F0F0F0F
N7.C2.S04: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  5
N1.C3.S00: SuppressionWindowAdjustmentRd: latency =  9, rdptroffset =  5
N3.C0.D0.R1.S07: RdPtrOffsetTxDq: 05
ACCM: 00 00000000 000B0000
N7.C2.S05: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  5
N1.C3.S01: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  6
N3.C0.D0.R1.S07: RdPtrOffsetTxDqs: 06
ACCM: 00 00000000 000B0000
N7.C2.S06: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  6
N1.C3.S02: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  6
N3.C0.D0.R1.S07: PiTxDqs: 60
N5.C0.D0.R1: CheckMCTest: result = 0x1FF
N7.C2.S07: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  6
N1.C3.S03: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  5
N3.C0.D0.R1.S08: wrcmd2dqsstartlatency: 04
ACCM: 0F 0F0F0F0F 0F0F0F0F
N7.C2.S08: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  5
N1.C3.S04: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  5
N3.C0.D0.R1.S08: RdPtrOffsetTxDq: 04
ACCM: 0F 0F0F0F0F 0F0F0F0F
N7.C3.S00: SuppressionWindowAdjustmentRd: latency =  9, rdptroffset =  5
N1.C3.S05: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  6
N3.C0.D0.R1.S08: RdPtrOffsetTxDqs: 06
ACCM: 00 00000000 000B0000
N7.C3.S01: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  6
N1.C3.S06: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  6
N3.C0.D0.R1.S08: PiTxDqs: 27
ACCM: 00 00000000 000B0000
N7.C3.S02: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  6
N1.C3.S07: SuppressionWindowAdjustmentRd: latency =  9, rdptroffset =  5
N3.C0.D0.R1.S09: wrcmd2dqsstartlatency: 04
N5.C0.D0.R1: CheckMCTest: result = 0x1FF
N7.C3.S03: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  6
N1.C3.S08: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  5
N3.C0.D0.R1.S09: RdPtrOffsetTxDq: 06
N5.C0.D0.R1: CheckMCTest: passed
N7.C3.S04: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  6

START - Basic Write Level Training
N3.C0.D0.R1.S09: RdPtrOffsetTxDqs: 07
N5.C0.D0.R1: CheckMCTest: passed
N7.C3.S05: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  6
Checkpoint Code: Socket 0, 0xB7, 0x03, 0x0000
N3.C0.D0.R1.S09: PiTxDqs: 35
N5.C0.D0.R1.S00: Offset Found: RdPtrOffsetDqs = 007
N7.C3.S06: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  6
N1: START WRITE LEVEL:
N3.C0.D0.R1.S10: wrcmd2dqsstartlatency: 04
N5.C0.D0.R1.S01: Offset Found: RdPtrOffsetDqs = 007
N7.C3.S07: SuppressionWindowAdjustmentRd: latency =  9, rdptroffset =  5
N1.C0.D0.R0: ODT Override: 0x1
N3.C0.D0.R1.S10: RdPtrOffsetTxDq: 05
N5.C0.D0.R1.S02: Offset Found: RdPtrOffsetDqs = 007
N7.C3.S08: SuppressionWindowAdjustmentRd: latency =  8, rdptroffset =  5
N1.C0.D0.R0.S00: Write Level Fine Value = 481
N3.C0.D0.R1.S10: RdPtrOffsetTxDqs: 07
N5.C0.D0.R1.S03: Offset Found: RdPtrOffsetDqs = 006

START - Basic Write Level Training
N1.C0.D0.R0.S01: Write Level Fine Value = 464
N3.C0.D0.R1.S10: PiTxDqs: 19
N5.C0.D0.R1.S04: Offset Found: RdPtrOffsetDqs = 006
N7: START WRITE LEVEL:
N1.C0.D0.R0.S02: Write Level Fine Value = 452
N3.C0.D0.R1.S11: wrcmd2dqsstartlatency: 04
N5.C0.D0.R1.S05: Offset Found: RdPtrOffsetDqs = 006
N7.C0.D0.R0: ODT Override: 0x1
N1.C0.D0.R0.S03: Write Level Fine Value = 436
N3.C0.D0.R1.S11: RdPtrOffsetTxDq: 05
N5.C0.D0.R1.S06: Offset Found: RdPtrOffsetDqs = 006
N7.C0.D0.R0.S00: Write Level Fine Value = 481
N1.C0.D0.R0.S04: Write Level Fine Value = 400
N3.C0.D0.R1.S11: RdPtrOffsetTxDqs: 07
N5.C0.D0.R1.S07: Offset Found: RdPtrOffsetDqs = 006
N7.C0.D0.R0.S01: Write Level Fine Value = 460
N1.C0.D0.R0.S05: Write Level Fine Value = 418
N3.C0.D0.R1.S11: PiTxDqs: 08
N5.C0.D0.R1.S08: Offset Found: RdPtrOffsetDqs = 006
N7.C0.D0.R0.S02: Write Level Fine Value = 448
N1.C0.D0.R0.S06: Write Level Fine Value = 424
N3.C0.D0.R1.S12: wrcmd2dqsstartlatency: 04
N5.C0.D0.R1: Write Training Coarse, upper nibbles
N7.C0.D0.R0.S03: Write Level Fine Value = 432
N1.C0.D0.R0.S07: Write Level Fine Value = 442
N3.C0.D0.R1.S12: RdPtrOffsetTxDq: 05
N5.C0.D0.R1.S09: Dq Delay estimate: 446
N7.C0.D0.R0.S04: Write Level Fine Value = 398
N1.C0.D0.R0.S08: Write Level Fine Value = 409
N3.C0.D0.R1.S12: RdPtrOffsetTxDqs: 06
N5.C0.D0.R1.S10: Dq Delay estimate: 431
N7.C0.D0.R0.S05: Write Level Fine Value = 417
N1.C0.D0.R0.S09: Write Level Fine Value = 481
N3.C0.D0.R1.S12: PiTxDqs: 55
N5.C0.D0.R1.S11: Dq Delay estimate: 420
N7.C0.D0.R0.S06: Write Level Fine Value = 419
N1.C0.D0.R0.S10: Write Level Fine Value = 464
N3.C0.D0.R1.S13: wrcmd2dqsstartlatency: 04
N5.C0.D0.R1.S12: Dq Delay estimate: 399
N7.C0.D0.R0.S07: Write Level Fine Value = 440
N1.C0.D0.R0.S11: Write Level Fine Value = 451
N3.C0.D0.R1.S13: RdPtrOffsetTxDq: 04
N5.C0.D0.R1.S13: Dq Delay estimate: 375
N7.C0.D0.R0.S08: Write Level Fine Value = 407
N1.C0.D0.R0.S12: Write Level Fine Value = 437
N3.C0.D0.R1.S13: RdPtrOffsetTxDqs: 06
N5.C0.D0.R1.S14: Dq Delay estimate: 387
N7.C0.D0.R0.S09: Write Level Fine Value = 479
N1.C0.D0.R0.S13: Write Level Fine Value = 400
N3.C0.D0.R1.S13: PiTxDqs: 21
N5.C0.D0.R1.S15: Dq Delay estimate: 396
N7.C0.D0.R0.S10: Write Level Fine Value = 460
N1.C0.D0.R0.S14: Write Level Fine Value = 416
N3.C0.D0.R1.S14: wrcmd2dqsstartlatency: 04
N5.C0.D0.R1.S16: Dq Delay estimate: 411
N7.C0.D0.R0.S11: Write Level Fine Value = 447
N1.C0.D0.R0.S15: Write Level Fine Value = 424
N3.C0.D0.R1.S14: RdPtrOffsetTxDq: 05
N5.C0.D0.R1.S17: Dq Delay estimate: 376
N7.C0.D0.R0.S12: Write Level Fine Value = 432
N1.C0.D0.R0.S16: Write Level Fine Value = 440
N3.C0.D0.R1.S14: RdPtrOffsetTxDqs: 06
ACCM: F0 F0F0F0F0 F0F0F0F0
N7.C0.D0.R0.S13: Write Level Fine Value = 398
N1.C0.D0.R0.S17: Write Level Fine Value = 409
N3.C0.D0.R1.S14: PiTxDqs: 37
ACCM: F0 F0F0F0F0 F0F0F0F0
N7.C0.D0.R0.S14: Write Level Fine Value = 417
N1.C0.D0.R1: ODT Override: 0x2
N3.C0.D0.R1.S15: wrcmd2dqsstartlatency: 04
ACCM: F0 F0F0F0F0 F0F0F0F0
N7.C0.D0.R0.S15: Write Level Fine Value = 420
N1.C0.D0.R1.S00: Write Level Fine Value = 482
N3.C0.D0.R1.S15: RdPtrOffsetTxDq: 05
ACCM: F0 F0F0F0F0 F0F0F0F0
N7.C0.D0.R0.S16: Write Level Fine Value = 439
N1.C0.D0.R1.S01: Write Level Fine Value = 463
N3.C0.D0.R1.S15: RdPtrOffsetTxDqs: 06
N5.C0.D0.R1: CheckMCTest: result = 0x3FE00
N7.C0.D0.R0.S17: Write Level Fine Value = 408
N1.C0.D0.R1.S02: Write Level Fine Value = 451
N3.C0.D0.R1.S15: PiTxDqs: 42
ACCM: F0 F0F0F0F0 F0F0F0F0
N7.C0.D0.R1: ODT Override: 0x2
N1.C0.D0.R1.S03: Write Level Fine Value = 433
N3.C0.D0.R1.S16: wrcmd2dqsstartlatency: 04
ACCM: F0 F0F0F0F0 F0F0F0F0
N7.C0.D0.R1.S00: Write Level Fine Value = 479
N1.C0.D0.R1.S04: Write Level Fine Value = 400
N3.C0.D0.R1.S16: RdPtrOffsetTxDq: 05
ACCM: F0 F0F0F0F0 F0F0F0F0
N7.C0.D0.R1.S01: Write Level Fine Value = 459
N1.C0.D0.R1.S05: Write Level Fine Value = 418
N3.C0.D0.R1.S16: RdPtrOffsetTxDqs: 06
ACCM: F0 F0F0F0F0 F0F0F0F0
N7.C0.D0.R1.S02: Write Level Fine Value = 447
N1.C0.D0.R1.S06: Write Level Fine Value = 423
N3.C0.D0.R1.S16: PiTxDqs: 60
N5.C0.D0.R1: CheckMCTest: result = 0x3FE00
N7.C0.D0.R1.S03: Write Level Fine Value = 431
N1.C0.D0.R1.S07: Write Level Fine Value = 441
N3.C0.D0.R1.S17: wrcmd2dqsstartlatency: 04
ACCM: F0 F0F0F0F0 F0F0F0F0
N7.C0.D0.R1.S04: Write Level Fine Value = 398
N1.C0.D0.R1.S08: Write Level Fine Value = 407
N3.C0.D0.R1.S17: RdPtrOffsetTxDq: 04
ACCM: F0 F0F0F0F0 F0F0F0F0
N7.C0.D0.R1.S05: Write Level Fine Value = 417
N1.C0.D0.R1.S09: Write Level Fine Value = 481
N3.C0.D0.R1.S17: RdPtrOffsetTxDqs: 06
ACCM: 00 00000000 00000000
N7.C0.D0.R1.S06: Write Level Fine Value = 420
N1.C0.D0.R1.S10: Write Level Fine Value = 463
N3.C0.D0.R1.S17: PiTxDqs: 29
ACCM: 00 00000000 00000000
N7.C0.D0.R1.S07: Write Level Fine Value = 440
N1.C0.D0.R1.S11: Write Level Fine Value = 451
N3.C0.D0.R1.S00: RdPtrOffsetTxDq: 07
N5.C0.D0.R1: CheckMCTest: result = 0x3FE00
N7.C0.D0.R1.S08: Write Level Fine Value = 406
N1.C0.D0.R1.S12: Write Level Fine Value = 437
N3.C0.D0.R1.S01: RdPtrOffsetTxDq: 06
ACCM: F0 F0F0F0F0 F0F0F0F0
N7.C0.D0.R1.S09: Write Level Fine Value = 479
N1.C0.D0.R1.S13: Write Level Fine Value = 401
N3.C0.D0.R1.S02: RdPtrOffsetTxDq: 06
ACCM: F0 F0F0F0F0 F0F0F0F0
N7.C0.D0.R1.S10: Write Level Fine Value = 459
N1.C0.D0.R1.S14: Write Level Fine Value = 417
N3.C0.D0.R1.S03: RdPtrOffsetTxDq: 06
ACCM: 00 00000000 00000000
N7.C0.D0.R1.S11: Write Level Fine Value = 447
N1.C0.D0.R1.S15: Write Level Fine Value = 423
N3.C0.D0.R1.S04: RdPtrOffsetTxDq: 05
ACCM: 00 00000000 00000000
N7.C0.D0.R1.S12: Write Level Fine Value = 430
N1.C0.D0.R1.S16: Write Level Fine Value = 440
N3.C0.D0.R1.S05: RdPtrOffsetTxDq: 06
N5.C0.D0.R1: CheckMCTest: result = 0x3FE00
N7.C0.D0.R1.S13: Write Level Fine Value = 398
N1.C0.D0.R1.S17: Write Level Fine Value = 408
N3.C0.D0.R1.S06: RdPtrOffsetTxDq: 06
N5.C0.D0.R1: CheckMCTest: passed
N7.C0.D0.R1.S14: Write Level Fine Value = 416
N1.C1.D0.R0: ODT Override: 0x1
N3.C0.D0.R1.S07: RdPtrOffsetTxDq: 06
N5.C0.D0.R1: CheckMCTest: passed
N7.C0.D0.R1.S15: Write Level Fine Value = 420
N1.C1.D0.R0.S00: Write Level Fine Value = 487
N3.C0.D0.R1.S08: RdPtrOffsetTxDq: 05
N5.C0.D0.R1.S09: Offset Found: RdPtrOffsetDqs = 007
N7.C0.D0.R1.S16: Write Level Fine Value = 440
N1.C1.D0.R0.S01: Write Level Fine Value = 471
N3.C0.D0.R1.S09: RdPtrOffsetTxDq: 07
N5.C0.D0.R1.S10: Offset Found: RdPtrOffsetDqs = 007
N7.C0.D0.R1.S17: Write Level Fine Value = 407
N1.C1.D0.R0.S02: Write Level Fine Value = 460
N3.C0.D0.R1.S10: RdPtrOffsetTxDq: 06
N5.C0.D0.R1.S11: Offset Found: RdPtrOffsetDqs = 007
N7.C1.D0.R0: ODT Override: 0x1
N1.C1.D0.R0.S03: Write Level Fine Value = 444
N3.C0.D0.R1.S11: RdPtrOffsetTxDq: 06
N5.C0.D0.R1.S12: Offset Found: RdPtrOffsetDqs = 006
N7.C1.D0.R0.S00: Write Level Fine Value = 492
N1.C1.D0.R0.S04: Write Level Fine Value = 411
N3.C0.D0.R1.S12: RdPtrOffsetTxDq: 06
N5.C0.D0.R1.S13: Offset Found: RdPtrOffsetDqs = 006
N7.C1.D0.R0.S01: Write Level Fine Value = 475
N1.C1.D0.R0.S05: Write Level Fine Value = 424
N3.C0.D0.R1.S13: RdPtrOffsetTxDq: 05
N5.C0.D0.R1.S14: Offset Found: RdPtrOffsetDqs = 006
N7.C1.D0.R0.S02: Write Level Fine Value = 467
N1.C1.D0.R0.S06: Write Level Fine Value = 437
N3.C0.D0.R1.S14: RdPtrOffsetTxDq: 06
N5.C0.D0.R1.S15: Offset Found: RdPtrOffsetDqs = 006
N7.C1.D0.R0.S03: Write Level Fine Value = 449
N1.C1.D0.R0.S07: Write Level Fine Value = 453
N3.C0.D0.R1.S15: RdPtrOffsetTxDq: 06
N5.C0.D0.R1.S16: Offset Found: RdPtrOffsetDqs = 006
N7.C1.D0.R0.S04: Write Level Fine Value = 416
N1.C1.D0.R0.S08: Write Level Fine Value = 422
N3.C0.D0.R1.S16: RdPtrOffsetTxDq: 06
N5.C0.D0.R1.S17: Offset Found: RdPtrOffsetDqs = 006
N7.C1.D0.R0.S05: Write Level Fine Value = 430
N1.C1.D0.R0.S09: Write Level Fine Value = 489
N3.C0.D0.R1.S17: RdPtrOffsetTxDq: 05
N5.C0: Calculating Optimimum DQS Values
N7.C1.D0.R0.S06: Write Level Fine Value = 443
N1.C1.D0.R0.S10: Write Level Fine Value = 471
N3.C0.D0.R1.S00: RdPtrOffsetTxDq: 08
N5.C0.D0.R0.S00: Total Delay in PI ticks: TxDQS = 993, TxDQ = 959
N7.C1.D0.R0.S07: Write Level Fine Value = 463
N1.C1.D0.R0.S11: Write Level Fine Value = 460
N3.C0.D0.R1.S01: RdPtrOffsetTxDq: 07
N5.C0.D0.R0.S01: Total Delay in PI ticks: TxDQS = 978, TxDQ = 944
N7.C1.D0.R0.S08: Write Level Fine Value = 429
N1.C1.D0.R0.S12: Write Level Fine Value = 445
N3.C0.D0.R1.S02: RdPtrOffsetTxDq: 07
N5.C0.D0.R0.S02: Total Delay in PI ticks: TxDQS = 964, TxDQ = 928
N7.C1.D0.R0.S09: Write Level Fine Value = 490
N1.C1.D0.R0.S13: Write Level Fine Value = 411
N3.C0.D0.R1.S03: RdPtrOffsetTxDq: 07
N5.C0.D0.R0.S03: Total Delay in PI ticks: TxDQS = 949, TxDQ = 915
N7.C1.D0.R0.S10: Write Level Fine Value = 477
N1.C1.D0.R0.S14: Write Level Fine Value = 424
N3.C0.D0.R1.S04: RdPtrOffsetTxDq: 06
N5.C0.D0.R0.S04: Total Delay in PI ticks: TxDQS = 915, TxDQ = 887
N7.C1.D0.R0.S11: Write Level Fine Value = 466
N1.C1.D0.R0.S15: Write Level Fine Value = 437
N3.C0.D0.R1.S05: RdPtrOffsetTxDq: 07
N5.C0.D0.R0.S05: Total Delay in PI ticks: TxDQS = 932, TxDQ = 900
N7.C1.D0.R0.S12: Write Level Fine Value = 448
N1.C1.D0.R0.S16: Write Level Fine Value = 455
N3.C0.D0.R1.S06: RdPtrOffsetTxDq: 07
N5.C0.D0.R0.S06: Total Delay in PI ticks: TxDQS = 938, TxDQ = 907
N7.C1.D0.R0.S13: Write Level Fine Value = 415
N1.C1.D0.R0.S17: Write Level Fine Value = 423
N3.C0.D0.R1.S07: RdPtrOffsetTxDq: 07
N5.C0.D0.R0.S07: Total Delay in PI ticks: TxDQS = 954, TxDQ = 924
N7.C1.D0.R0.S14: Write Level Fine Value = 430
N1.C1.D0.R1: ODT Override: 0x2
N3.C0.D0.R1.S08: RdPtrOffsetTxDq: 06
N5.C0.D0.R0.S08: Total Delay in PI ticks: TxDQS = 921, TxDQ = 889
N7.C1.D0.R0.S15: Write Level Fine Value = 442
N1.C1.D0.R1.S00: Write Level Fine Value = 488
N3.C0.D0.R1.S09: RdPtrOffsetTxDq: 08
N5.C0.D0.R0.S09: Total Delay in PI ticks: TxDQS = 993, TxDQ = 958
N7.C1.D0.R0.S16: Write Level Fine Value = 461
N1.C1.D0.R1.S01: Write Level Fine Value = 469
N3.C0.D0.R1.S10: RdPtrOffsetTxDq: 07
N5.C0.D0.R0.S10: Total Delay in PI ticks: TxDQS = 978, TxDQ = 944
N7.C1.D0.R0.S17: Write Level Fine Value = 427
N1.C1.D0.R1.S02: Write Level Fine Value = 459
N3.C0.D0.R1.S11: RdPtrOffsetTxDq: 07
N5.C0.D0.R0.S11: Total Delay in PI ticks: TxDQS = 967, TxDQ = 935
N7.C1.D0.R1: ODT Override: 0x2
N1.C1.D0.R1.S03: Write Level Fine Value = 443
N3.C0.D0.R1.S12: RdPtrOffsetTxDq: 07
N5.C0.D0.R0.S12: Total Delay in PI ticks: TxDQS = 949, TxDQ = 916
N7.C1.D0.R1.S00: Write Level Fine Value = 493
N1.C1.D0.R1.S04: Write Level Fine Value = 411
N3.C0.D0.R1.S13: RdPtrOffsetTxDq: 06
N5.C0.D0.R0.S13: Total Delay in PI ticks: TxDQS = 915, TxDQ = 886
N7.C1.D0.R1.S01: Write Level Fine Value = 474
N1.C1.D0.R1.S05: Write Level Fine Value = 424
N3.C0.D0.R1.S14: RdPtrOffsetTxDq: 07
N5.C0.D0.R0.S14: Total Delay in PI ticks: TxDQS = 931, TxDQ = 901
N7.C1.D0.R1.S02: Write Level Fine Value = 465
N1.C1.D0.R1.S06: Write Level Fine Value = 436
N3.C0.D0.R1.S15: RdPtrOffsetTxDq: 07
N5.C0.D0.R0.S15: Total Delay in PI ticks: TxDQS = 938, TxDQ = 908
N7.C1.D0.R1.S03: Write Level Fine Value = 448
N1.C1.D0.R1.S07: Write Level Fine Value = 454
N3.C0.D0.R1.S16: RdPtrOffsetTxDq: 07
N5.C0.D0.R0.S16: Total Delay in PI ticks: TxDQS = 954, TxDQ = 923
N7.C1.D0.R1.S04: Write Level Fine Value = 417
N1.C1.D0.R1.S08: Write Level Fine Value = 420
N3.C0.D0.R1.S17: RdPtrOffsetTxDq: 06
N5.C0.D0.R0.S17: Total Delay in PI ticks: TxDQS = 922, TxDQ = 889
N7.C1.D0.R1.S05: Write Level Fine Value = 429
N1.C1.D0.R1.S09: Write Level Fine Value = 485
N3.C0.D0.R1.S00: Total Delay in PI ticks: TxDQ = 964
N5.C0.D0.R1.S00: Total Delay in PI ticks: TxDQS = 993, TxDQ = 960
N7.C1.D0.R1.S06: Write Level Fine Value = 443
N1.C1.D0.R1.S10: Write Level Fine Value = 469
N3.C0.D0.R1.S01: Total Delay in PI ticks: TxDQ = 946
N5.C0.D0.R1.S01: Total Delay in PI ticks: TxDQS = 978, TxDQ = 944
N7.C1.D0.R1.S07: Write Level Fine Value = 460
N1.C1.D0.R1.S11: Write Level Fine Value = 459
N3.C0.D0.R1.S02: Total Delay in PI ticks: TxDQ = 931
N5.C0.D0.R1.S02: Total Delay in PI ticks: TxDQS = 962, TxDQ = 926
N7.C1.D0.R1.S08: Write Level Fine Value = 429
N1.C1.D0.R1.S12: Write Level Fine Value = 442
N3.C0.D0.R1.S03: Total Delay in PI ticks: TxDQ = 916
N5.C0.D0.R1.S03: Total Delay in PI ticks: TxDQS = 949, TxDQ = 915
N7.C1.D0.R1.S09: Write Level Fine Value = 489
N1.C1.D0.R1.S13: Write Level Fine Value = 412
N3.C0.D0.R1.S04: Total Delay in PI ticks: TxDQ = 884
N5.C0.D0.R1.S04: Total Delay in PI ticks: TxDQS = 913, TxDQ = 885
N7.C1.D0.R1.S10: Write Level Fine Value = 476
N1.C1.D0.R1.S14: Write Level Fine Value = 424
N3.C0.D0.R1.S05: Total Delay in PI ticks: TxDQ = 899
N5.C0.D0.R1.S05: Total Delay in PI ticks: TxDQS = 931, TxDQ = 899
N7.C1.D0.R1.S11: Write Level Fine Value = 466
N1.C1.D0.R1.S15: Write Level Fine Value = 436
N3.C0.D0.R1.S06: Total Delay in PI ticks: TxDQ = 903
N5.C0.D0.R1.S06: Total Delay in PI ticks: TxDQS = 938, TxDQ = 907
N7.C1.D0.R1.S12: Write Level Fine Value = 448
N1.C1.D0.R1.S16: Write Level Fine Value = 456
N3.C0.D0.R1.S07: Total Delay in PI ticks: TxDQ = 923
N5.C0.D0.R1.S07: Total Delay in PI ticks: TxDQS = 953, TxDQ = 923
N7.C1.D0.R1.S13: Write Level Fine Value = 416
N1.C1.D0.R1.S17: Write Level Fine Value = 421
N3.C0.D0.R1.S08: Total Delay in PI ticks: TxDQ = 889
N5.C0.D0.R1.S08: Total Delay in PI ticks: TxDQS = 922, TxDQ = 887
N7.C1.D0.R1.S14: Write Level Fine Value = 430
N1.C2.D0.R0: ODT Override: 0x1
N3.C0.D0.R1.S09: Total Delay in PI ticks: TxDQ = 962
N5.C0.D0.R1.S09: Total Delay in PI ticks: TxDQS = 993, TxDQ = 958
N7.C1.D0.R1.S15: Write Level Fine Value = 442
N1.C2.D0.R0.S00: Write Level Fine Value = 481
N3.C0.D0.R1.S10: Total Delay in PI ticks: TxDQ = 946
N5.C0.D0.R1.S10: Total Delay in PI ticks: TxDQS = 976, TxDQ = 943
N7.C1.D0.R1.S16: Write Level Fine Value = 460
N1.C2.D0.R0.S01: Write Level Fine Value = 466
N3.C0.D0.R1.S11: Total Delay in PI ticks: TxDQ = 933
N5.C0.D0.R1.S11: Total Delay in PI ticks: TxDQS = 966, TxDQ = 932
N7.C1.D0.R1.S17: Write Level Fine Value = 427
N1.C2.D0.R0.S02: Write Level Fine Value = 453
N3.C0.D0.R1.S12: Total Delay in PI ticks: TxDQ = 916
N5.C0.D0.R1.S12: Total Delay in PI ticks: TxDQS = 945, TxDQ = 911
N7.C2.D0.R0: ODT Override: 0x1
N1.C2.D0.R0.S03: Write Level Fine Value = 438
N3.C0.D0.R1.S13: Total Delay in PI ticks: TxDQ = 883
N5.C0.D0.R1.S13: Total Delay in PI ticks: TxDQS = 915, TxDQ = 887
N7.C2.D0.R0.S00: Write Level Fine Value = 477
N1.C2.D0.R0.S04: Write Level Fine Value = 399
N3.C0.D0.R1.S14: Total Delay in PI ticks: TxDQ = 900
N5.C0.D0.R1.S14: Total Delay in PI ticks: TxDQS = 930, TxDQ = 899
N7.C2.D0.R0.S01: Write Level Fine Value = 463
N1.C2.D0.R0.S05: Write Level Fine Value = 427
N3.C0.D0.R1.S15: Total Delay in PI ticks: TxDQ = 903
N5.C0.D0.R1.S15: Total Delay in PI ticks: TxDQS = 938, TxDQ = 908
N7.C2.D0.R0.S02: Write Level Fine Value = 452
N1.C2.D0.R0.S06: Write Level Fine Value = 423
N3.C0.D0.R1.S16: Total Delay in PI ticks: TxDQ = 923
N5.C0.D0.R1.S16: Total Delay in PI ticks: TxDQS = 955, TxDQ = 923
N7.C2.D0.R0.S03: Write Level Fine Value = 435
N1.C2.D0.R0.S07: Write Level Fine Value = 447
N3.C0.D0.R1.S17: Total Delay in PI ticks: TxDQ = 890
N5.C0.D0.R1.S17: Total Delay in PI ticks: TxDQS = 922, TxDQ = 888
N7.C2.D0.R0.S04: Write Level Fine Value = 392
N1.C2.D0.R0.S08: Write Level Fine Value = 413
N3.C0: Calculating Optimimum DQ/DQS Values
N5.C1.D0.R0: Write Training Coarse, lower nibbles / bytes
N7.C2.D0.R0.S05: Write Level Fine Value = 423
N1.C2.D0.R0.S09: Write Level Fine Value = 481
START_DATA_TX_DQ
N5.C1.D0.R0.S00: Dq Delay estimate: 459
N7.C2.D0.R0.S06: Write Level Fine Value = 422
N1.C2.D0.R0.S10: Write Level Fine Value = 468
N3.C0.S00: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 009, RdPtrOffsetTxDqs = 009
N5.C1.D0.R0.S01: Dq Delay estimate: 439
N7.C2.D0.R0.S07: Write Level Fine Value = 444
N1.C2.D0.R0.S11: Write Level Fine Value = 453
N3.C0.S00: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 009, RdPtrOffsetTxDqs = 009
N5.C1.D0.R0.S02: Dq Delay estimate: 429
N7.C2.D0.R0.S08: Write Level Fine Value = 408
N1.C2.D0.R0.S12: Write Level Fine Value = 438
N3.C0.S01: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 009
N5.C1.D0.R0.S03: Dq Delay estimate: 416
N7.C2.D0.R0.S09: Write Level Fine Value = 478
N1.C2.D0.R0.S13: Write Level Fine Value = 398
N3.C0.S01: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 009
N5.C1.D0.R0.S04: Dq Delay estimate: 379
N7.C2.D0.R0.S10: Write Level Fine Value = 463
N1.C2.D0.R0.S14: Write Level Fine Value = 425
N3.C0.S02: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 009
N5.C1.D0.R0.S05: Dq Delay estimate: 396
N7.C2.D0.R0.S11: Write Level Fine Value = 454
N1.C2.D0.R0.S15: Write Level Fine Value = 425
N3.C0.S02: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 009
N5.C1.D0.R0.S06: Dq Delay estimate: 411
N7.C2.D0.R0.S12: Write Level Fine Value = 435
N1.C2.D0.R0.S16: Write Level Fine Value = 447
N3.C0.S03: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 008
N5.C1.D0.R0.S07: Dq Delay estimate: 428
N7.C2.D0.R0.S13: Write Level Fine Value = 392
N1.C2.D0.R0.S17: Write Level Fine Value = 414
N3.C0.S03: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 008
N5.C1.D0.R0.S08: Dq Delay estimate: 393
N7.C2.D0.R0.S14: Write Level Fine Value = 421
N1.C2.D0.R1: ODT Override: 0x2
N3.C0.S04: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 007, RdPtrOffsetTxDqs = 008
ACCM: 0F 0F9F0F9F 9F0F0F0F
N7.C2.D0.R0.S15: Write Level Fine Value = 422
N1.C2.D0.R1.S00: Write Level Fine Value = 480
N3.C0.S04: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 007, RdPtrOffsetTxDqs = 008
ACCM: 0F 0F9F0F9F 9F0F0F0F
N7.C2.D0.R0.S16: Write Level Fine Value = 442
N1.C2.D0.R1.S01: Write Level Fine Value = 465
N3.C0.S05: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 008
ACCM: 0F FF9F0F9F 9FFFFFFF
N7.C2.D0.R0.S17: Write Level Fine Value = 408
N1.C2.D0.R1.S02: Write Level Fine Value = 452
N3.C0.S05: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 008
ACCM: 0F FF9F0F9F 9FFFFFFF
N7.C2.D0.R1: ODT Override: 0x2
N1.C2.D0.R1.S03: Write Level Fine Value = 437
N3.C0.S06: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 008
N5.C1.D0.R0: CheckMCTest: result = 0x1BFFF
N7.C2.D0.R1.S00: Write Level Fine Value = 479
N1.C2.D0.R1.S04: Write Level Fine Value = 398
N3.C0.S06: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 008
ACCM: 0F 0FDF0FDF FF0F0F0F
N7.C2.D0.R1.S01: Write Level Fine Value = 462
N1.C2.D0.R1.S05: Write Level Fine Value = 427
N3.C0.S07: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 008
ACCM: 0F 0FDF0FDF FF0F0F0F
N7.C2.D0.R1.S02: Write Level Fine Value = 450
N1.C2.D0.R1.S06: Write Level Fine Value = 424
N3.C0.S07: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 008
ACCM: 0F FFDF0FDF FFFFFFFF
N7.C2.D0.R1.S03: Write Level Fine Value = 433
N1.C2.D0.R1.S07: Write Level Fine Value = 447
N3.C0.S08: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 007, RdPtrOffsetTxDqs = 008
ACCM: 0F FFDF0FDF FFFFFFFF
N7.C2.D0.R1.S04: Write Level Fine Value = 393
N1.C2.D0.R1.S08: Write Level Fine Value = 409
N3.C0.S08: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 007, RdPtrOffsetTxDqs = 008
N5.C1.D0.R0: CheckMCTest: result = 0x1BFFF
N7.C2.D0.R1.S05: Write Level Fine Value = 422
N1.C2.D0.R1.S09: Write Level Fine Value = 479
N3.C0.D0.R0.S00: TxDqs: plus1 = 1, minus1 = 0, PI = 36, DB = 0
ACCM: 0F 0FDF0FDF FF0F0F0F
N7.C2.D0.R1.S06: Write Level Fine Value = 420
N1.C2.D0.R1.S10: Write Level Fine Value = 466
N3.C0.D0.R0.S00: TxDq : plus1 = 1, minus1 = 0, PI = 03, DB = 1
ACCM: 0F 0FDF0FDF FF0F0F0F
N7.C2.D0.R1.S07: Write Level Fine Value = 443
N1.C2.D0.R1.S11: Write Level Fine Value = 454
N3.C0.D0.R0.S01: TxDqs: plus1 = 1, minus1 = 0, PI = 18, DB = 0
ACCM: 00 FBD000D0 FBF0F0F0
N7.C2.D0.R1.S08: Write Level Fine Value = 408
N1.C2.D0.R1.S12: Write Level Fine Value = 438
N3.C0.D0.R0.S01: TxDq : plus1 = 1, minus1 = 0, PI = 49, DB = 1
ACCM: 00 FBD000D0 FBF0F0F0
N7.C2.D0.R1.S09: Write Level Fine Value = 475
N1.C2.D0.R1.S13: Write Level Fine Value = 399
N3.C0.D0.R0.S02: TxDqs: plus1 = 1, minus1 = 0, PI = 06, DB = 1
N5.C1.D0.R0: CheckMCTest: result = 0x1BFFF
N7.C2.D0.R1.S10: Write Level Fine Value = 464
N1.C2.D0.R1.S14: Write Level Fine Value = 426
N3.C0.D0.R0.S02: TxDq : plus1 = 1, minus1 = 0, PI = 35, DB = 0
ACCM: 0F 0FDF0FDF FF0F0F0F
N7.C2.D0.R1.S11: Write Level Fine Value = 453
N1.C2.D0.R1.S15: Write Level Fine Value = 426
N3.C0.D0.R0.S03: TxDqs: plus1 = 1, minus1 = 0, PI = 55, DB = 1
ACCM: 0F 0FDF0FDF FF0F0F0F
N7.C2.D0.R1.S12: Write Level Fine Value = 435
N1.C2.D0.R1.S16: Write Level Fine Value = 448
N3.C0.D0.R0.S03: TxDq : plus1 = 1, minus1 = 0, PI = 20, DB = 0
ACCM: 00 FFDD00D0 FFFDF0F0
N7.C2.D0.R1.S13: Write Level Fine Value = 392
N1.C2.D0.R1.S17: Write Level Fine Value = 411
N3.C0.D0.R0.S04: TxDqs: plus1 = 1, minus1 = 0, PI = 21, DB = 0
ACCM: 00 FFDD00D0 FFFDF0F0
N7.C2.D0.R1.S14: Write Level Fine Value = 421
N1.C3.D0.R0: ODT Override: 0x1
N3.C0.D0.R0.S04: TxDq : plus1 = 1, minus1 = 0, PI = 52, DB = 1
N5.C1.D0.R0: CheckMCTest: result = 0x1BFFF
N7.C2.D0.R1.S15: Write Level Fine Value = 423
N1.C3.D0.R0.S00: Write Level Fine Value = 488
N3.C0.D0.R0.S05: TxDqs: plus1 = 1, minus1 = 0, PI = 38, DB = 0
ACCM: 00 00D000D0 D0000000
N7.C2.D0.R1.S16: Write Level Fine Value = 443
N1.C3.D0.R0.S01: Write Level Fine Value = 468
N3.C0.D0.R0.S05: TxDq : plus1 = 1, minus1 = 0, PI = 04, DB = 1
ACCM: 00 00D000D0 D0000000
N7.C2.D0.R1.S17: Write Level Fine Value = 408
N1.C3.D0.R0.S02: Write Level Fine Value = 458
N3.C0.D0.R0.S06: TxDqs: plus1 = 1, minus1 = 0, PI = 41, DB = 0
ACCM: 00 F0D000D0 F0F0F0F0
N7.C3.D0.R0: ODT Override: 0x1
N1.C3.D0.R0.S03: Write Level Fine Value = 442
N3.C0.D0.R0.S06: TxDq : plus1 = 1, minus1 = 0, PI = 08, DB = 1
ACCM: 00 F0D000D0 F0F0F0F0
N7.C3.D0.R0.S00: Write Level Fine Value = 495
N1.C3.D0.R0.S04: Write Level Fine Value = 408
N3.C0.D0.R0.S07: TxDqs: plus1 = 1, minus1 = 0, PI = 60, DB = 1
N5.C1.D0.R0: CheckMCTest: result = 0x1BE00
N7.C3.D0.R0.S01: Write Level Fine Value = 480
N1.C3.D0.R0.S05: Write Level Fine Value = 421
N3.C0.D0.R0.S07: TxDq : plus1 = 1, minus1 = 0, PI = 27, DB = 0
ACCM: 00 00D000D0 F0000000
N7.C3.D0.R0.S02: Write Level Fine Value = 466
N1.C3.D0.R0.S06: Write Level Fine Value = 435
N3.C0.D0.R0.S08: TxDqs: plus1 = 1, minus1 = 0, PI = 28, DB = 0
ACCM: 00 00D000D0 F0000000
N7.C3.D0.R0.S03: Write Level Fine Value = 453
N1.C3.D0.R0.S07: Write Level Fine Value = 453
N3.C0.D0.R0.S08: TxDq : plus1 = 1, minus1 = 0, PI = 58, DB = 1
ACCM: 00 F0D000D0 F0F0F0F0
N7.C3.D0.R0.S04: Write Level Fine Value = 416
N1.C3.D0.R0.S08: Write Level Fine Value = 423
N3.C0.D0.R0.S09: TxDqs: plus1 = 1, minus1 = 0, PI = 35, DB = 0
ACCM: 00 F0D000D0 F0F0F0F0
N7.C3.D0.R0.S05: Write Level Fine Value = 430
N1.C3.D0.R0.S09: Write Level Fine Value = 487
N3.C0.D0.R0.S09: TxDq : plus1 = 1, minus1 = 0, PI = 02, DB = 1
N5.C1.D0.R0: CheckMCTest: result = 0x1BE00
N7.C3.D0.R0.S06: Write Level Fine Value = 446
N1.C3.D0.R0.S10: Write Level Fine Value = 470
N3.C0.D0.R0.S10: TxDqs: plus1 = 1, minus1 = 0, PI = 18, DB = 0
N5.C1.D0.R0.S00: Offset Found: RdPtrOffsetDqs = 007
N7.C3.D0.R0.S07: Write Level Fine Value = 462
N1.C3.D0.R0.S11: Write Level Fine Value = 458
N3.C0.D0.R0.S10: TxDq : plus1 = 1, minus1 = 0, PI = 49, DB = 1
N5.C1.D0.R0.S01: Offset Found: RdPtrOffsetDqs = 007
N7.C3.D0.R0.S08: Write Level Fine Value = 432
N1.C3.D0.R0.S12: Write Level Fine Value = 443
N3.C0.D0.R0.S11: TxDqs: plus1 = 1, minus1 = 0, PI = 07, DB = 1
N5.C1.D0.R0.S02: Offset Found: RdPtrOffsetDqs = 007
N7.C3.D0.R0.S09: Write Level Fine Value = 495
N1.C3.D0.R0.S13: Write Level Fine Value = 408
N3.C0.D0.R0.S11: TxDq : plus1 = 1, minus1 = 0, PI = 37, DB = 0
N5.C1.D0.R0.S03: Offset Found: RdPtrOffsetDqs = 006
N7.C3.D0.R0.S10: Write Level Fine Value = 481
N1.C3.D0.R0.S14: Write Level Fine Value = 420
N3.C0.D0.R0.S12: TxDqs: plus1 = 1, minus1 = 0, PI = 55, DB = 1
N5.C1.D0.R0.S04: Offset Found: RdPtrOffsetDqs = 006
N7.C3.D0.R0.S11: Write Level Fine Value = 469
N1.C3.D0.R0.S15: Write Level Fine Value = 435
N3.C0.D0.R0.S12: TxDq : plus1 = 1, minus1 = 0, PI = 21, DB = 0
N5.C1.D0.R0.S05: Offset Found: RdPtrOffsetDqs = 006
N7.C3.D0.R0.S12: Write Level Fine Value = 454
N1.C3.D0.R0.S16: Write Level Fine Value = 453
N3.C0.D0.R0.S13: TxDqs: plus1 = 1, minus1 = 0, PI = 21, DB = 0
N5.C1.D0.R0.S06: Offset Found: RdPtrOffsetDqs = 006
N7.C3.D0.R0.S13: Write Level Fine Value = 417
N1.C3.D0.R0.S17: Write Level Fine Value = 419
N3.C0.D0.R0.S13: TxDq : plus1 = 1, minus1 = 0, PI = 51, DB = 1
N5.C1.D0.R0.S07: Offset Found: RdPtrOffsetDqs = 007
N7.C3.D0.R0.S14: Write Level Fine Value = 432
N1.C3.D0.R1: ODT Override: 0x2
N3.C0.D0.R0.S14: TxDqs: plus1 = 1, minus1 = 0, PI = 37, DB = 0
N5.C1.D0.R0.S08: Offset Found: RdPtrOffsetDqs = 006
N7.C3.D0.R0.S15: Write Level Fine Value = 446
N1.C3.D0.R1.S00: Write Level Fine Value = 488
N3.C0.D0.R0.S14: TxDq : plus1 = 1, minus1 = 0, PI = 04, DB = 1
N5.C1.D0.R0: Write Training Coarse, upper nibbles
N7.C3.D0.R0.S16: Write Level Fine Value = 461
N1.C3.D0.R1.S01: Write Level Fine Value = 467
N3.C0.D0.R0.S15: TxDqs: plus1 = 1, minus1 = 0, PI = 42, DB = 0
N5.C1.D0.R0.S09: Dq Delay estimate: 455
N7.C3.D0.R0.S17: Write Level Fine Value = 431
N1.C3.D0.R1.S02: Write Level Fine Value = 456
N3.C0.D0.R0.S15: TxDq : plus1 = 1, minus1 = 0, PI = 07, DB = 1
N5.C1.D0.R0.S10: Dq Delay estimate: 441
N7.C3.D0.R1: ODT Override: 0x2
N1.C3.D0.R1.S03: Write Level Fine Value = 442
N3.C0.D0.R0.S16: TxDqs: plus1 = 1, minus1 = 0, PI = 60, DB = 1
N5.C1.D0.R0.S11: Dq Delay estimate: 431
N7.C3.D0.R1.S00: Write Level Fine Value = 495
N1.C3.D0.R1.S04: Write Level Fine Value = 407
N3.C0.D0.R0.S16: TxDq : plus1 = 1, minus1 = 0, PI = 27, DB = 0
N5.C1.D0.R0.S12: Dq Delay estimate: 414
N7.C3.D0.R1.S01: Write Level Fine Value = 478
N1.C3.D0.R1.S05: Write Level Fine Value = 419
N3.C0.D0.R0.S17: TxDqs: plus1 = 1, minus1 = 0, PI = 29, DB = 0
N5.C1.D0.R0.S13: Dq Delay estimate: 383
N7.C3.D0.R1.S02: Write Level Fine Value = 466
N1.C3.D0.R1.S06: Write Level Fine Value = 435
N3.C0.D0.R0.S17: TxDq : plus1 = 1, minus1 = 0, PI = 58, DB = 1
N5.C1.D0.R0.S14: Dq Delay estimate: 395
N7.C3.D0.R1.S03: Write Level Fine Value = 453
N1.C3.D0.R1.S07: Write Level Fine Value = 451
N3.C0.D0.R1.S00: TxDqs: plus1 = 1, minus1 = 0, PI = 36, DB = 0
N5.C1.D0.R0.S15: Dq Delay estimate: 406
N7.C3.D0.R1.S04: Write Level Fine Value = 417
N1.C3.D0.R1.S08: Write Level Fine Value = 419
N3.C0.D0.R1.S00: TxDq : plus1 = 1, minus1 = 0, PI = 03, DB = 1
N5.C1.D0.R0.S16: Dq Delay estimate: 427
N7.C3.D0.R1.S05: Write Level Fine Value = 431
N1.C3.D0.R1.S09: Write Level Fine Value = 486
N3.C0.D0.R1.S01: TxDqs: plus1 = 1, minus1 = 0, PI = 18, DB = 0
N5.C1.D0.R0.S17: Dq Delay estimate: 398
N7.C3.D0.R1.S06: Write Level Fine Value = 445
N1.C3.D0.R1.S10: Write Level Fine Value = 469
N3.C0.D0.R1.S01: TxDq : plus1 = 1, minus1 = 0, PI = 49, DB = 1
ACCM: F0 F0F0F0F0 F0F0F0F0
N7.C3.D0.R1.S07: Write Level Fine Value = 462
N1.C3.D0.R1.S11: Write Level Fine Value = 458
N3.C0.D0.R1.S02: TxDqs: plus1 = 1, minus1 = 0, PI = 06, DB = 1
ACCM: F0 F0F0F0F0 F0F0F0F0
N7.C3.D0.R1.S08: Write Level Fine Value = 431
N1.C3.D0.R1.S12: Write Level Fine Value = 442
N3.C0.D0.R1.S02: TxDq : plus1 = 1, minus1 = 0, PI = 35, DB = 0
ACCM: F0 F0F0F0F0 F0F0F0F0
N7.C3.D0.R1.S09: Write Level Fine Value = 493
N1.C3.D0.R1.S13: Write Level Fine Value = 409
N3.C0.D0.R1.S03: TxDqs: plus1 = 1, minus1 = 0, PI = 55, DB = 1
ACCM: F0 F0F0F0F0 F0F0F0F0
N7.C3.D0.R1.S10: Write Level Fine Value = 479
N1.C3.D0.R1.S14: Write Level Fine Value = 419
N3.C0.D0.R1.S03: TxDq : plus1 = 1, minus1 = 0, PI = 20, DB = 0
N5.C1.D0.R0: CheckMCTest: result = 0x3FE00
N7.C3.D0.R1.S11: Write Level Fine Value = 468
N1.C3.D0.R1.S15: Write Level Fine Value = 437
N3.C0.D0.R1.S04: TxDqs: plus1 = 1, minus1 = 0, PI = 21, DB = 0
ACCM: F0 F0F0F0F0 F0F0F0F0
N7.C3.D0.R1.S12: Write Level Fine Value = 453
N1.C3.D0.R1.S16: Write Level Fine Value = 451
N3.C0.D0.R1.S04: TxDq : plus1 = 1, minus1 = 0, PI = 52, DB = 1
ACCM: F0 F0F0F0F0 F0F0F0F0
N7.C3.D0.R1.S13: Write Level Fine Value = 418
N1.C3.D0.R1.S17: Write Level Fine Value = 421
N3.C0.D0.R1.S05: TxDqs: plus1 = 1, minus1 = 0, PI = 38, DB = 0
ACCM: F0 F0F0F0F0 F0F0F0F0
N7.C3.D0.R1.S14: Write Level Fine Value = 431
N1: END WRITE LEVEL:
N3.C0.D0.R1.S05: TxDq : plus1 = 1, minus1 = 0, PI = 04, DB = 1
ACCM: F0 F0F0F0F0 F0F0F0F0
N7.C3.D0.R1.S15: Write Level Fine Value = 445
Checkpoint Code: Socket 0, 0xB7, 0x04, 0x0000
N3.C0.D0.R1.S06: TxDqs: plus1 = 1, minus1 = 0, PI = 41, DB = 0
N5.C1.D0.R0: CheckMCTest: result = 0x3FE00
N7.C3.D0.R1.S16: Write Level Fine Value = 461
N1: START WRITE LEVEL COARSE:
N3.C0.D0.R1.S06: TxDq : plus1 = 1, minus1 = 0, PI = 08, DB = 1
ACCM: F0 F0F0F0F0 F0F0F0F0
N7.C3.D0.R1.S17: Write Level Fine Value = 431
N3.C0.D0.R1.S07: TxDqs: plus1 = 1, minus1 = 0, PI = 60, DB = 1
ACCM: F0 F0F0F0F0 F0F0F0F0
N7: END WRITE LEVEL:
N1.C0.D0.R0: Write Training Coarse, lower nibbles / bytes
N3.C0.D0.R1.S07: TxDq : plus1 = 1, minus1 = 0, PI = 27, DB = 0
ACCM: 00 000000B0 00000000
N7: START WRITE LEVEL COARSE:
N1.C0.D0.R0.S00: Dq Delay estimate: 447
N3.C0.D0.R1.S08: TxDqs: plus1 = 1, minus1 = 0, PI = 28, DB = 0
ACCM: 00 000000B0 00000000
N1.C0.D0.R0.S01: Dq Delay estimate: 431
N3.C0.D0.R1.S08: TxDq : plus1 = 1, minus1 = 0, PI = 58, DB = 1
N5.C1.D0.R0: CheckMCTest: result = 0x3FE00
N7.C0.D0.R0: Write Training Coarse, lower nibbles / bytes
N1.C0.D0.R0.S02: Dq Delay estimate: 417
N3.C0.D0.R1.S09: TxDqs: plus1 = 1, minus1 = 0, PI = 35, DB = 0
ACCM: F0 F0F0F0F0 F0F0F0F0
N7.C0.D0.R0.S00: Dq Delay estimate: 446
N1.C0.D0.R0.S03: Dq Delay estimate: 400
N3.C0.D0.R1.S09: TxDq : plus1 = 1, minus1 = 0, PI = 02, DB = 1
ACCM: F0 F0F0F0F0 F0F0F0F0
N7.C0.D0.R0.S01: Dq Delay estimate: 426
N1.C0.D0.R0.S04: Dq Delay estimate: 366
N3.C0.D0.R1.S10: TxDqs: plus1 = 1, minus1 = 0, PI = 18, DB = 0
ACCM: 00 000000F0 00000000
N7.C0.D0.R0.S02: Dq Delay estimate: 415
N1.C0.D0.R0.S05: Dq Delay estimate: 383
N3.C0.D0.R1.S10: TxDq : plus1 = 1, minus1 = 0, PI = 49, DB = 1
ACCM: 00 000000F0 00000000
N7.C0.D0.R0.S03: Dq Delay estimate: 397
N1.C0.D0.R0.S06: Dq Delay estimate: 390
N3.C0.D0.R1.S11: TxDqs: plus1 = 1, minus1 = 0, PI = 07, DB = 1
N5.C1.D0.R0: CheckMCTest: result = 0x3FE00
N7.C0.D0.R0.S04: Dq Delay estimate: 364
N1.C0.D0.R0.S07: Dq Delay estimate: 408
N3.C0.D0.R1.S11: TxDq : plus1 = 1, minus1 = 0, PI = 37, DB = 0
N5.C1.D0.R0: CheckMCTest: passed
N7.C0.D0.R0.S05: Dq Delay estimate: 381
N1.C0.D0.R0.S08: Dq Delay estimate: 376
N3.C0.D0.R1.S12: TxDqs: plus1 = 1, minus1 = 0, PI = 55, DB = 1
N5.C1.D0.R0: CheckMCTest: passed
N7.C0.D0.R0.S06: Dq Delay estimate: 388
ACCM: 0F 9F0F0F0F 9F0F0F0F
N3.C0.D0.R1.S12: TxDq : plus1 = 1, minus1 = 0, PI = 21, DB = 0
N5.C1.D0.R0.S09: Offset Found: RdPtrOffsetDqs = 007
N7.C0.D0.R0.S07: Dq Delay estimate: 404
ACCM: 0F 9F0F0F0F 9F0F0F0F
N3.C0.D0.R1.S13: TxDqs: plus1 = 1, minus1 = 0, PI = 21, DB = 0
N5.C1.D0.R0.S10: Offset Found: RdPtrOffsetDqs = 007
N7.C0.D0.R0.S08: Dq Delay estimate: 373
ACCM: 0F 9F0F0F0F 9FFFFFFF
N3.C0.D0.R1.S13: TxDq : plus1 = 1, minus1 = 0, PI = 51, DB = 1
N5.C1.D0.R0.S11: Offset Found: RdPtrOffsetDqs = 007
ACCM: 0F 9F0F0F9F 9F0F0F0F
ACCM: 0F 9F0F0F0F 9FFFFFFF
N3.C0.D0.R1.S14: TxDqs: plus1 = 1, minus1 = 0, PI = 37, DB = 0
N5.C1.D0.R0.S12: Offset Found: RdPtrOffsetDqs = 006
ACCM: 0F 9F0F0F9F 9F0F0F0F
N1.C0.D0.R0: CheckMCTest: result = 0x11FFF
N3.C0.D0.R1.S14: TxDq : plus1 = 1, minus1 = 0, PI = 04, DB = 1
N5.C1.D0.R0.S13: Offset Found: RdPtrOffsetDqs = 006
ACCM: 0F 9F0F0F9F 9FFFFFFF
ACCM: 0F DF0F0F0F DF0F0F0F
N3.C0.D0.R1.S15: TxDqs: plus1 = 1, minus1 = 0, PI = 42, DB = 0
N5.C1.D0.R0.S14: Offset Found: RdPtrOffsetDqs = 006
ACCM: 0F 9F0F0F9F 9FFFFFFF
ACCM: 0F DF0F0F0F DF0F0F0F
N3.C0.D0.R1.S15: TxDq : plus1 = 1, minus1 = 0, PI = 07, DB = 1
N5.C1.D0.R0.S15: Offset Found: RdPtrOffsetDqs = 006
N7.C0.D0.R0: CheckMCTest: result = 0x13FFF
ACCM: 0F DF0F0F0F DFFFFFFF
N3.C0.D0.R1.S16: TxDqs: plus1 = 1, minus1 = 0, PI = 60, DB = 1
N5.C1.D0.R0.S16: Offset Found: RdPtrOffsetDqs = 007
ACCM: 0F DF0F0FDF DF0F0F0F
ACCM: 0F DF0F0F0F DFFFFFFF
N3.C0.D0.R1.S16: TxDq : plus1 = 1, minus1 = 0, PI = 27, DB = 0
N5.C1.D0.R0.S17: Offset Found: RdPtrOffsetDqs = 006
ACCM: 0F DF0F0FDF DF0F0F0F
N1.C0.D0.R0: CheckMCTest: result = 0x11FFF
N3.C0.D0.R1.S17: TxDqs: plus1 = 1, minus1 = 0, PI = 29, DB = 0
N5.C1.D0.R1: Write Training Coarse, lower nibbles / bytes
ACCM: 0F DF0F0FDF DFFFFFFF
ACCM: 0F DF0F0F0F DF0F0F0F
N3.C0.D0.R1.S17: TxDq : plus1 = 1, minus1 = 0, PI = 58, DB = 1
N5.C1.D0.R1.S00: Dq Delay estimate: 457
ACCM: 0F DF0F0FDF DFFFFFFF
ACCM: 0F DF0F0F0F DF0F0F0F
END_DATA_TX_DQ
N5.C1.D0.R1.S01: Dq Delay estimate: 438
N7.C0.D0.R0: CheckMCTest: result = 0x13FFF
ACCM: 0B DB000000 D0F0F0F0
N3.C1.D0.R0.S00: wrcmd2dqsstartlatency: 04
N5.C1.D0.R1.S02: Dq Delay estimate: 429
ACCM: 0F DF0F0FDF DF0F0F0F
ACCM: 0B DB000000 D0F0F0F0
N3.C1.D0.R0.S00: RdPtrOffsetTxDq: 06
N5.C1.D0.R1.S03: Dq Delay estimate: 413
ACCM: 0F DF0F0FDF DF0F0F0F
N1.C0.D0.R0: CheckMCTest: result = 0x11FFF
N3.C1.D0.R0.S00: RdPtrOffsetTxDqs: 07
N5.C1.D0.R1.S04: Dq Delay estimate: 379
ACCM: 00 DB000BD0 D0F0F0F0
ACCM: 0F DF0F0F0F DF0F0F0F
N3.C1.D0.R0.S00: PiTxDqs: 36
N5.C1.D0.R1.S05: Dq Delay estimate: 395
ACCM: 00 DB000BD0 D0F0F0F0
ACCM: 0F DF0F0F0F DF0F0F0F
N3.C1.D0.R0.S01: wrcmd2dqsstartlatency: 04
N5.C1.D0.R1.S06: Dq Delay estimate: 409
N7.C0.D0.R0: CheckMCTest: result = 0x13FFF
ACCM: 0F DF000000 D0F0F0F0
N3.C1.D0.R0.S01: RdPtrOffsetTxDq: 05
N5.C1.D0.R1.S07: Dq Delay estimate: 428
ACCM: 0F DF0F0FDF DF0F0F0F
ACCM: 0F DF000000 D0F0F0F0
N3.C1.D0.R0.S01: RdPtrOffsetTxDqs: 07
N5.C1.D0.R1.S08: Dq Delay estimate: 392
ACCM: 0F DF0F0FDF DF0F0F0F
N1.C0.D0.R0: CheckMCTest: result = 0x11FFF
N3.C1.D0.R0.S01: PiTxDqs: 20
ACCM: 0F 0F0F0F0F 0F0F0F0F
ACCM: 00 DB000FD0 D0F0F0F0
ACCM: 00 D0000000 D0000000
N3.C1.D0.R0.S02: wrcmd2dqsstartlatency: 04
ACCM: 0F 0F0F0F0F 0F0F0F0F
ACCM: 00 DB000FD0 D0F0F0F0
ACCM: 00 D0000000 D0000000
N3.C1.D0.R0.S02: RdPtrOffsetTxDq: 05
ACCM: 0F 0F0F0F0F 0F0F0F0F
N7.C0.D0.R0: CheckMCTest: result = 0x13FFF
ACCM: 00 D0000000 D0F0F0F0
N3.C1.D0.R0.S02: RdPtrOffsetTxDqs: 07
ACCM: 0F 0F0F0F0F 0F0F0F0F
ACCM: 00 D0000000 D0000000
ACCM: 00 D0000000 D0F0F0F0
N3.C1.D0.R0.S02: PiTxDqs: 13
N5.C1.D0.R1: CheckMCTest: result = 0x1FF
ACCM: 00 D0000000 D0000000
N1.C0.D0.R0: CheckMCTest: result = 0x11E00
N3.C1.D0.R0.S03: wrcmd2dqsstartlatency: 04
ACCM: 0F 0F0F0F0F 0F0F0F0F
ACCM: 00 D0000000 D0F0F0F0
ACCM: 00 D0000000 D0000000
N3.C1.D0.R0.S03: RdPtrOffsetTxDq: 05
ACCM: 0F 0F0F0F0F 0F0F0F0F
ACCM: 00 D0000000 D0F0F0F0
ACCM: 00 D0000000 D0000000
N3.C1.D0.R0.S03: RdPtrOffsetTxDqs: 06
ACCM: 0F 0F0F0F0F 0F0F0F0F
N7.C0.D0.R0: CheckMCTest: result = 0x11E00
ACCM: 00 D0000000 D0F0F0F0
N3.C1.D0.R0.S03: PiTxDqs: 58
ACCM: 0F 0F0F0F0F 0F0F0F0F
ACCM: 00 D0000000 D0000000
ACCM: 00 D0000000 D0F0F0F0
N3.C1.D0.R0.S04: wrcmd2dqsstartlatency: 04
N5.C1.D0.R1: CheckMCTest: result = 0x1FF
ACCM: 00 D0000000 D0000000
N1.C0.D0.R0: CheckMCTest: result = 0x11E00
N3.C1.D0.R0.S04: RdPtrOffsetTxDq: 04
ACCM: 0F 0F0F0F0F 0F0F0F0F
ACCM: 00 D0000000 D0F0F0F0
N1.C0.D0.R0.S00: Offset Found: RdPtrOffsetDqs = 007
N3.C1.D0.R0.S04: RdPtrOffsetTxDqs: 06
ACCM: 0F 0F0F0F0F 0F0F0F0F
ACCM: 00 D0000000 D0F0F0F0
N1.C0.D0.R0.S01: Offset Found: RdPtrOffsetDqs = 007
N3.C1.D0.R0.S04: PiTxDqs: 26
ACCM: 00 00000000 00000000
N7.C0.D0.R0: CheckMCTest: result = 0x11E00
N1.C0.D0.R0.S02: Offset Found: RdPtrOffsetDqs = 007
N3.C1.D0.R0.S05: wrcmd2dqsstartlatency: 04
ACCM: 00 00000000 00000000
N7.C0.D0.R0.S00: Offset Found: RdPtrOffsetDqs = 007
N1.C0.D0.R0.S03: Offset Found: RdPtrOffsetDqs = 006
N3.C1.D0.R0.S05: RdPtrOffsetTxDq: 05
N5.C1.D0.R1: CheckMCTest: result = 0x1FF
N7.C0.D0.R0.S01: Offset Found: RdPtrOffsetDqs = 007
N1.C0.D0.R0.S04: Offset Found: RdPtrOffsetDqs = 006
N3.C1.D0.R0.S05: RdPtrOffsetTxDqs: 06
ACCM: 0F 0F0F0F0F 0F0F0F0F
N7.C0.D0.R0.S02: Offset Found: RdPtrOffsetDqs = 007
N1.C0.D0.R0.S05: Offset Found: RdPtrOffsetDqs = 006
N3.C1.D0.R0.S05: PiTxDqs: 40
ACCM: 0F 0F0F0F0F 0F0F0F0F
N7.C0.D0.R0.S03: Offset Found: RdPtrOffsetDqs = 006
N1.C0.D0.R0.S06: Offset Found: RdPtrOffsetDqs = 006
N3.C1.D0.R0.S06: wrcmd2dqsstartlatency: 04
ACCM: 00 00000000 00000000
N7.C0.D0.R0.S04: Offset Found: RdPtrOffsetDqs = 006
N1.C0.D0.R0.S07: Offset Found: RdPtrOffsetDqs = 006
N3.C1.D0.R0.S06: RdPtrOffsetTxDq: 05
ACCM: 00 00000000 00000000
N7.C0.D0.R0.S05: Offset Found: RdPtrOffsetDqs = 006
N1.C0.D0.R0.S08: Offset Found: RdPtrOffsetDqs = 006
N3.C1.D0.R0.S06: RdPtrOffsetTxDqs: 06
N5.C1.D0.R1: CheckMCTest: result = 0x1FF
N7.C0.D0.R0.S06: Offset Found: RdPtrOffsetDqs = 006
N1.C0.D0.R0: Write Training Coarse, upper nibbles
N3.C1.D0.R0.S06: PiTxDqs: 52
N5.C1.D0.R1: CheckMCTest: passed
N7.C0.D0.R0.S07: Offset Found: RdPtrOffsetDqs = 006
N1.C0.D0.R0.S09: Dq Delay estimate: 446
N3.C1.D0.R0.S07: wrcmd2dqsstartlatency: 04
N5.C1.D0.R1: CheckMCTest: passed
N7.C0.D0.R0.S08: Offset Found: RdPtrOffsetDqs = 006
N1.C0.D0.R0.S10: Dq Delay estimate: 435
N3.C1.D0.R0.S07: RdPtrOffsetTxDq: 05
N5.C1.D0.R1.S00: Offset Found: RdPtrOffsetDqs = 007
N7.C0.D0.R0: Write Training Coarse, upper nibbles
N1.C0.D0.R0.S11: Dq Delay estimate: 417
N3.C1.D0.R0.S07: RdPtrOffsetTxDqs: 07
N5.C1.D0.R1.S01: Offset Found: RdPtrOffsetDqs = 007
N7.C0.D0.R0.S09: Dq Delay estimate: 445
N1.C0.D0.R0.S12: Dq Delay estimate: 403
N3.C1.D0.R0.S07: PiTxDqs: 08
N5.C1.D0.R1.S02: Offset Found: RdPtrOffsetDqs = 007
N7.C0.D0.R0.S10: Dq Delay estimate: 425
N1.C0.D0.R0.S13: Dq Delay estimate: 365
N3.C1.D0.R0.S08: wrcmd2dqsstartlatency: 04
N5.C1.D0.R1.S03: Offset Found: RdPtrOffsetDqs = 006
N7.C0.D0.R0.S11: Dq Delay estimate: 413
N1.C0.D0.R0.S14: Dq Delay estimate: 382
N3.C1.D0.R0.S08: RdPtrOffsetTxDq: 05
N5.C1.D0.R1.S04: Offset Found: RdPtrOffsetDqs = 006
N7.C0.D0.R0.S12: Dq Delay estimate: 398
N1.C0.D0.R0.S15: Dq Delay estimate: 390
N3.C1.D0.R0.S08: RdPtrOffsetTxDqs: 06
N5.C1.D0.R1.S05: Offset Found: RdPtrOffsetDqs = 006
N7.C0.D0.R0.S13: Dq Delay estimate: 362
N1.C0.D0.R0.S16: Dq Delay estimate: 407
N3.C1.D0.R0.S08: PiTxDqs: 38
N5.C1.D0.R1.S06: Offset Found: RdPtrOffsetDqs = 006
N7.C0.D0.R0.S14: Dq Delay estimate: 384
N1.C0.D0.R0.S17: Dq Delay estimate: 373
N3.C1.D0.R0.S09: wrcmd2dqsstartlatency: 04
N5.C1.D0.R1.S07: Offset Found: RdPtrOffsetDqs = 007
N7.C0.D0.R0.S15: Dq Delay estimate: 387
ACCM: F0 F0F0F0F0 F0F0F0F0
N3.C1.D0.R0.S09: RdPtrOffsetTxDq: 06
N5.C1.D0.R1.S08: Offset Found: RdPtrOffsetDqs = 006
N7.C0.D0.R0.S16: Dq Delay estimate: 405
ACCM: F0 F0F0F0F0 F0F0F0F0
N3.C1.D0.R0.S09: RdPtrOffsetTxDqs: 07
N5.C1.D0.R1: Write Training Coarse, upper nibbles
N7.C0.D0.R0.S17: Dq Delay estimate: 372
ACCM: F0 F0F0F0F0 F0F0F0F0
N3.C1.D0.R0.S09: PiTxDqs: 35
N5.C1.D0.R1.S09: Dq Delay estimate: 452
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: F0 F0F0F0F0 F0F0F0F0
N3.C1.D0.R0.S10: wrcmd2dqsstartlatency: 04
N5.C1.D0.R1.S10: Dq Delay estimate: 442
ACCM: F0 F0F0F0F0 F0F0F0F0
N1.C0.D0.R0: CheckMCTest: result = 0x3FE00
N3.C1.D0.R0.S10: RdPtrOffsetTxDq: 05
N5.C1.D0.R1.S11: Dq Delay estimate: 429
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: F0 F0F0F0F0 F0F0F0F0
N3.C1.D0.R0.S10: RdPtrOffsetTxDqs: 07
N5.C1.D0.R1.S12: Dq Delay estimate: 415
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: F0 F0F0F0F0 F0F0F0F0
N3.C1.D0.R0.S10: PiTxDqs: 21
N5.C1.D0.R1.S13: Dq Delay estimate: 383
N7.C0.D0.R0: CheckMCTest: result = 0x3FE00
ACCM: F0 F0F0F0F0 F0F0F0F0
N3.C1.D0.R0.S11: wrcmd2dqsstartlatency: 04
N5.C1.D0.R1.S14: Dq Delay estimate: 396
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: F0 F0F0F0F0 F0F0F0F0
N3.C1.D0.R0.S11: RdPtrOffsetTxDq: 05
N5.C1.D0.R1.S15: Dq Delay estimate: 409
ACCM: F0 F0F0F0F0 F0F0F0F0
N1.C0.D0.R0: CheckMCTest: result = 0x3FE00
N3.C1.D0.R0.S11: RdPtrOffsetTxDqs: 07
N5.C1.D0.R1.S16: Dq Delay estimate: 426
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: F0 F0F0F0F0 F0F0F0F0
N3.C1.D0.R0.S11: PiTxDqs: 13
N5.C1.D0.R1.S17: Dq Delay estimate: 397
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: F0 F0F0F0F0 F0F0F0F0
N3.C1.D0.R0.S12: wrcmd2dqsstartlatency: 04
ACCM: F0 F0F0F0F0 F0F0F0F0
N7.C0.D0.R0: CheckMCTest: result = 0x3FE00
ACCM: 00 00000000 00000000
N3.C1.D0.R0.S12: RdPtrOffsetTxDq: 05
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: 00 00000000 00000000
N3.C1.D0.R0.S12: RdPtrOffsetTxDqs: 06
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: F0 F0F0F0F0 F0F0F0F0
N1.C0.D0.R0: CheckMCTest: result = 0x3FE00
N3.C1.D0.R0.S12: PiTxDqs: 58
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: 00 00000000 00000000
ACCM: F0 F0F0F0F0 F0F0F0F0
N3.C1.D0.R0.S13: wrcmd2dqsstartlatency: 04
N5.C1.D0.R1: CheckMCTest: result = 0x3FE00
ACCM: 00 00000000 00000000
ACCM: F0 F0F0F0F0 F0F0F0F0
N3.C1.D0.R0.S13: RdPtrOffsetTxDq: 04
ACCM: F0 F0F0F0F0 F0F0F0F0
N7.C0.D0.R0: CheckMCTest: result = 0x3FE00
ACCM: 00 00000000 00000000
N3.C1.D0.R0.S13: RdPtrOffsetTxDqs: 06
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: 00 00000000 00000000
N3.C1.D0.R0.S13: PiTxDqs: 26
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: F0 F0F0F0F0 F0F0F0F0
N1.C0.D0.R0: CheckMCTest: result = 0x3FE00
N3.C1.D0.R0.S14: wrcmd2dqsstartlatency: 04
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: 00 00000000 00000000
N1.C0.D0.R0: CheckMCTest: passed
N3.C1.D0.R0.S14: RdPtrOffsetTxDq: 05
N5.C1.D0.R1: CheckMCTest: result = 0x3FE00
ACCM: 00 00000000 00000000
N1.C0.D0.R0: CheckMCTest: passed
N3.C1.D0.R0.S14: RdPtrOffsetTxDqs: 06
ACCM: F0 F0F0F0F0 F0F0F0F0
N7.C0.D0.R0: CheckMCTest: result = 0x3FE00
N1.C0.D0.R0.S09: Offset Found: RdPtrOffsetDqs = 007
N3.C1.D0.R0.S14: PiTxDqs: 38
ACCM: F0 F0F0F0F0 F0F0F0F0
N7.C0.D0.R0: CheckMCTest: passed
N1.C0.D0.R0.S10: Offset Found: RdPtrOffsetDqs = 007
N3.C1.D0.R0.S15: wrcmd2dqsstartlatency: 04
ACCM: 00 00000000 00000000
N7.C0.D0.R0: CheckMCTest: passed
N1.C0.D0.R0.S11: Offset Found: RdPtrOffsetDqs = 007
N3.C1.D0.R0.S15: RdPtrOffsetTxDq: 05
ACCM: 00 00000000 00000000
N7.C0.D0.R0.S09: Offset Found: RdPtrOffsetDqs = 007
N1.C0.D0.R0.S12: Offset Found: RdPtrOffsetDqs = 006
N3.C1.D0.R0.S15: RdPtrOffsetTxDqs: 06
N5.C1.D0.R1: CheckMCTest: result = 0x3FE00
N7.C0.D0.R0.S10: Offset Found: RdPtrOffsetDqs = 007
N1.C0.D0.R0.S13: Offset Found: RdPtrOffsetDqs = 006
N3.C1.D0.R0.S15: PiTxDqs: 51
ACCM: F0 F0F0F0F0 F0F0F0F0
N7.C0.D0.R0.S11: Offset Found: RdPtrOffsetDqs = 006
N1.C0.D0.R0.S14: Offset Found: RdPtrOffsetDqs = 006
N3.C1.D0.R0.S16: wrcmd2dqsstartlatency: 04
ACCM: F0 F0F0F0F0 F0F0F0F0
N7.C0.D0.R0.S12: Offset Found: RdPtrOffsetDqs = 006
N1.C0.D0.R0.S15: Offset Found: RdPtrOffsetDqs = 006
N3.C1.D0.R0.S16: RdPtrOffsetTxDq: 05
ACCM: 00 00000000 00000000
N7.C0.D0.R0.S13: Offset Found: RdPtrOffsetDqs = 006
N1.C0.D0.R0.S16: Offset Found: RdPtrOffsetDqs = 006
N3.C1.D0.R0.S16: RdPtrOffsetTxDqs: 07
ACCM: 00 00000000 00000000
N7.C0.D0.R0.S14: Offset Found: RdPtrOffsetDqs = 006
N1.C0.D0.R0.S17: Offset Found: RdPtrOffsetDqs = 006
N3.C1.D0.R0.S16: PiTxDqs: 07
N5.C1.D0.R1: CheckMCTest: result = 0x3FE00
N7.C0.D0.R0.S15: Offset Found: RdPtrOffsetDqs = 006
N1.C0.D0.R1: Write Training Coarse, lower nibbles / bytes
N3.C1.D0.R0.S17: wrcmd2dqsstartlatency: 04
N5.C1.D0.R1: CheckMCTest: passed
N7.C0.D0.R0.S16: Offset Found: RdPtrOffsetDqs = 006
N1.C0.D0.R1.S00: Dq Delay estimate: 448
N3.C1.D0.R0.S17: RdPtrOffsetTxDq: 05
N5.C1.D0.R1: CheckMCTest: passed
N7.C0.D0.R0.S17: Offset Found: RdPtrOffsetDqs = 006
N1.C0.D0.R1.S01: Dq Delay estimate: 430
N3.C1.D0.R0.S17: RdPtrOffsetTxDqs: 06
N5.C1.D0.R1.S09: Offset Found: RdPtrOffsetDqs = 007
N7.C0.D0.R1: Write Training Coarse, lower nibbles / bytes
N1.C0.D0.R1.S02: Dq Delay estimate: 416
N3.C1.D0.R0.S17: PiTxDqs: 36
N5.C1.D0.R1.S10: Offset Found: RdPtrOffsetDqs = 007
N7.C0.D0.R1.S00: Dq Delay estimate: 444
N1.C0.D0.R1.S03: Dq Delay estimate: 397
N3.C1.D0.R0.S00: RdPtrOffsetTxDq: 07
N5.C1.D0.R1.S11: Offset Found: RdPtrOffsetDqs = 007
N7.C0.D0.R1.S01: Dq Delay estimate: 424
N1.C0.D0.R1.S04: Dq Delay estimate: 366
N3.C1.D0.R0.S01: RdPtrOffsetTxDq: 06
N5.C1.D0.R1.S12: Offset Found: RdPtrOffsetDqs = 006
N7.C0.D0.R1.S02: Dq Delay estimate: 413
N1.C0.D0.R1.S05: Dq Delay estimate: 383
N3.C1.D0.R0.S02: RdPtrOffsetTxDq: 06
N5.C1.D0.R1.S13: Offset Found: RdPtrOffsetDqs = 006
N7.C0.D0.R1.S03: Dq Delay estimate: 396
N1.C0.D0.R1.S06: Dq Delay estimate: 389
N3.C1.D0.R0.S03: RdPtrOffsetTxDq: 06
N5.C1.D0.R1.S14: Offset Found: RdPtrOffsetDqs = 006
N7.C0.D0.R1.S04: Dq Delay estimate: 364
N1.C0.D0.R1.S07: Dq Delay estimate: 407
N3.C1.D0.R0.S04: RdPtrOffsetTxDq: 05
N5.C1.D0.R1.S15: Offset Found: RdPtrOffsetDqs = 006
N7.C0.D0.R1.S05: Dq Delay estimate: 382
N1.C0.D0.R1.S08: Dq Delay estimate: 373
N3.C1.D0.R0.S05: RdPtrOffsetTxDq: 06
N5.C1.D0.R1.S16: Offset Found: RdPtrOffsetDqs = 007
N7.C0.D0.R1.S06: Dq Delay estimate: 387
ACCM: 0F 0F0F0F0F 0F0F0F0F
N3.C1.D0.R0.S06: RdPtrOffsetTxDq: 06
N5.C1.D0.R1.S17: Offset Found: RdPtrOffsetDqs = 006
N7.C0.D0.R1.S07: Dq Delay estimate: 405
ACCM: 0F 0F0F0F0F 0F0F0F0F
N3.C1.D0.R0.S07: RdPtrOffsetTxDq: 06
N5.C1: Calculating Optimimum DQS Values
N7.C0.D0.R1.S08: Dq Delay estimate: 372
ACCM: 0F 0F0F0F0F 0F0F0F0F
N3.C1.D0.R0.S08: RdPtrOffsetTxDq: 06
N5.C1.D0.R0.S00: Total Delay in PI ticks: TxDQS = 1002, TxDQ = 971
ACCM: 0F 0F0F0F0F 0F0F0F0F
ACCM: 0F 0F0F0F0F 0F0F0F0F
N3.C1.D0.R0.S09: RdPtrOffsetTxDq: 07
N5.C1.D0.R0.S01: Total Delay in PI ticks: TxDQS = 985, TxDQ = 951
ACCM: 0F 0F0F0F0F 0F0F0F0F
N1.C0.D0.R1: CheckMCTest: result = 0x1FF
N3.C1.D0.R0.S10: RdPtrOffsetTxDq: 06
N5.C1.D0.R0.S02: Total Delay in PI ticks: TxDQS = 973, TxDQ = 941
ACCM: 0F 0F0F0F0F 0F0F0F0F
ACCM: 0F 0F0F0F0F 0F0F0F0F
N3.C1.D0.R0.S11: RdPtrOffsetTxDq: 06
N5.C1.D0.R0.S03: Total Delay in PI ticks: TxDQS = 958, TxDQ = 928
ACCM: 0F 0F0F0F0F 0F0F0F0F
ACCM: 0F 0F0F0F0F 0F0F0F0F
N3.C1.D0.R0.S12: RdPtrOffsetTxDq: 06
N5.C1.D0.R0.S04: Total Delay in PI ticks: TxDQS = 924, TxDQ = 891
N7.C0.D0.R1: CheckMCTest: result = 0x1FF
ACCM: 0F 0F0F0F0F 0F0F0F0F
N3.C1.D0.R0.S13: RdPtrOffsetTxDq: 05
N5.C1.D0.R0.S05: Total Delay in PI ticks: TxDQS = 939, TxDQ = 908
ACCM: 0F 0F0F0F0F 0F0F0F0F
ACCM: 0F 0F0F0F0F 0F0F0F0F
N3.C1.D0.R0.S14: RdPtrOffsetTxDq: 06
N5.C1.D0.R0.S06: Total Delay in PI ticks: TxDQS = 954, TxDQ = 923
ACCM: 0F 0F0F0F0F 0F0F0F0F
N1.C0.D0.R1: CheckMCTest: result = 0x1FF
N3.C1.D0.R0.S15: RdPtrOffsetTxDq: 06
N5.C1.D0.R0.S07: Total Delay in PI ticks: TxDQS = 971, TxDQ = 940
ACCM: 0F 0F0F0F0F 0F0F0F0F
ACCM: 0F 0F0F0F0F 0F0F0F0F
N3.C1.D0.R0.S16: RdPtrOffsetTxDq: 06
N5.C1.D0.R0.S08: Total Delay in PI ticks: TxDQS = 936, TxDQ = 905
ACCM: 0F 0F0F0F0F 0F0F0F0F
ACCM: 0F 0F0F0F0F 0F0F0F0F
N3.C1.D0.R0.S17: RdPtrOffsetTxDq: 06
N5.C1.D0.R0.S09: Total Delay in PI ticks: TxDQS = 1001, TxDQ = 967
N7.C0.D0.R1: CheckMCTest: result = 0x1FF
ACCM: 00 00000000 00000000
N3.C1.D0.R0.S00: RdPtrOffsetTxDq: 08
N5.C1.D0.R0.S10: Total Delay in PI ticks: TxDQS = 985, TxDQ = 953
ACCM: 0F 0F0F0F0F 0F0F0F0F
ACCM: 00 00000000 00000000
N3.C1.D0.R0.S01: RdPtrOffsetTxDq: 07
N5.C1.D0.R0.S11: Total Delay in PI ticks: TxDQS = 974, TxDQ = 943
ACCM: 0F 0F0F0F0F 0F0F0F0F
N1.C0.D0.R1: CheckMCTest: result = 0x1FF
N3.C1.D0.R0.S02: RdPtrOffsetTxDq: 07
N5.C1.D0.R0.S12: Total Delay in PI ticks: TxDQS = 957, TxDQ = 926
ACCM: 00 00000000 00000000
ACCM: 0F 0F0F0F0F 0F0F0F0F
N3.C1.D0.R0.S03: RdPtrOffsetTxDq: 07
N5.C1.D0.R0.S13: Total Delay in PI ticks: TxDQS = 926, TxDQ = 895
ACCM: 00 00000000 00000000
ACCM: 0F 0F0F0F0F 0F0F0F0F
N3.C1.D0.R0.S04: RdPtrOffsetTxDq: 06
N5.C1.D0.R0.S14: Total Delay in PI ticks: TxDQS = 939, TxDQ = 907
N7.C0.D0.R1: CheckMCTest: result = 0x1FF
ACCM: 00 00000000 00000000
N3.C1.D0.R0.S05: RdPtrOffsetTxDq: 07
N5.C1.D0.R0.S15: Total Delay in PI ticks: TxDQS = 952, TxDQ = 918
ACCM: 0F 0F0F0F0F 0F0F0F0F
ACCM: 00 00000000 00000000
N3.C1.D0.R0.S06: RdPtrOffsetTxDq: 07
N5.C1.D0.R0.S16: Total Delay in PI ticks: TxDQS = 971, TxDQ = 939
ACCM: 0F 0F0F0F0F 0F0F0F0F
N1.C0.D0.R1: CheckMCTest: result = 0x1FF
N3.C1.D0.R0.S07: RdPtrOffsetTxDq: 07
N5.C1.D0.R0.S17: Total Delay in PI ticks: TxDQS = 938, TxDQ = 910
ACCM: 00 00000000 00000000
N1.C0.D0.R1: CheckMCTest: passed
N3.C1.D0.R0.S08: RdPtrOffsetTxDq: 07
N5.C1.D0.R1.S00: Total Delay in PI ticks: TxDQS = 1001, TxDQ = 969
ACCM: 00 00000000 00000000
N1.C0.D0.R1: CheckMCTest: passed
N3.C1.D0.R0.S09: RdPtrOffsetTxDq: 08
N5.C1.D0.R1.S01: Total Delay in PI ticks: TxDQS = 984, TxDQ = 950
N7.C0.D0.R1: CheckMCTest: result = 0x1FF
N1.C0.D0.R1.S00: Offset Found: RdPtrOffsetDqs = 007
N3.C1.D0.R0.S10: RdPtrOffsetTxDq: 07
N5.C1.D0.R1.S02: Total Delay in PI ticks: TxDQS = 973, TxDQ = 941
N7.C0.D0.R1: CheckMCTest: passed
N1.C0.D0.R1.S01: Offset Found: RdPtrOffsetDqs = 007
N3.C1.D0.R0.S11: RdPtrOffsetTxDq: 07
N5.C1.D0.R1.S03: Total Delay in PI ticks: TxDQS = 955, TxDQ = 925
N7.C0.D0.R1: CheckMCTest: passed
N1.C0.D0.R1.S02: Offset Found: RdPtrOffsetDqs = 007
N3.C1.D0.R0.S12: RdPtrOffsetTxDq: 07
N5.C1.D0.R1.S04: Total Delay in PI ticks: TxDQS = 923, TxDQ = 891
N7.C0.D0.R1.S00: Offset Found: RdPtrOffsetDqs = 007
N1.C0.D0.R1.S03: Offset Found: RdPtrOffsetDqs = 006
N3.C1.D0.R0.S13: RdPtrOffsetTxDq: 06
N5.C1.D0.R1.S05: Total Delay in PI ticks: TxDQS = 939, TxDQ = 907
N7.C0.D0.R1.S01: Offset Found: RdPtrOffsetDqs = 007
N1.C0.D0.R1.S04: Offset Found: RdPtrOffsetDqs = 006
N3.C1.D0.R0.S14: RdPtrOffsetTxDq: 07
N5.C1.D0.R1.S06: Total Delay in PI ticks: TxDQS = 951, TxDQ = 921
N7.C0.D0.R1.S02: Offset Found: RdPtrOffsetDqs = 006
N1.C0.D0.R1.S05: Offset Found: RdPtrOffsetDqs = 006
N3.C1.D0.R0.S15: RdPtrOffsetTxDq: 07
N5.C1.D0.R1.S07: Total Delay in PI ticks: TxDQS = 971, TxDQ = 940
N7.C0.D0.R1.S03: Offset Found: RdPtrOffsetDqs = 006
N1.C0.D0.R1.S06: Offset Found: RdPtrOffsetDqs = 006
N3.C1.D0.R0.S16: RdPtrOffsetTxDq: 07
N5.C1.D0.R1.S08: Total Delay in PI ticks: TxDQS = 936, TxDQ = 904
N7.C0.D0.R1.S04: Offset Found: RdPtrOffsetDqs = 006
N1.C0.D0.R1.S07: Offset Found: RdPtrOffsetDqs = 006
N3.C1.D0.R0.S17: RdPtrOffsetTxDq: 07
N5.C1.D0.R1.S09: Total Delay in PI ticks: TxDQS = 999, TxDQ = 964
N7.C0.D0.R1.S05: Offset Found: RdPtrOffsetDqs = 006
N1.C0.D0.R1.S08: Offset Found: RdPtrOffsetDqs = 006
N3.C1.D0.R0.S00: Total Delay in PI ticks: TxDQ = 964
N5.C1.D0.R1.S10: Total Delay in PI ticks: TxDQS = 985, TxDQ = 954
N7.C0.D0.R1.S06: Offset Found: RdPtrOffsetDqs = 006
N1.C0.D0.R1: Write Training Coarse, upper nibbles
N3.C1.D0.R0.S01: Total Delay in PI ticks: TxDQ = 948
N5.C1.D0.R1.S11: Total Delay in PI ticks: TxDQS = 973, TxDQ = 941
N7.C0.D0.R1.S07: Offset Found: RdPtrOffsetDqs = 006
N1.C0.D0.R1.S09: Dq Delay estimate: 446
N3.C1.D0.R0.S02: Total Delay in PI ticks: TxDQ = 939
N5.C1.D0.R1.S12: Total Delay in PI ticks: TxDQS = 958, TxDQ = 927
N7.C0.D0.R1.S08: Offset Found: RdPtrOffsetDqs = 006
N1.C0.D0.R1.S10: Dq Delay estimate: 433
N3.C1.D0.R0.S03: Total Delay in PI ticks: TxDQ = 921
N5.C1.D0.R1.S13: Total Delay in PI ticks: TxDQS = 927, TxDQ = 895
N7.C0.D0.R1: Write Training Coarse, upper nibbles
N1.C0.D0.R1.S11: Dq Delay estimate: 417
N3.C1.D0.R0.S04: Total Delay in PI ticks: TxDQ = 887
N5.C1.D0.R1.S14: Total Delay in PI ticks: TxDQS = 938, TxDQ = 908
N7.C0.D0.R1.S09: Dq Delay estimate: 445
N1.C0.D0.R1.S12: Dq Delay estimate: 403
N3.C1.D0.R0.S05: Total Delay in PI ticks: TxDQ = 901
N5.C1.D0.R1.S15: Total Delay in PI ticks: TxDQS = 954, TxDQ = 921
N7.C0.D0.R1.S10: Dq Delay estimate: 424
N1.C0.D0.R1.S13: Dq Delay estimate: 366
N3.C1.D0.R0.S06: Total Delay in PI ticks: TxDQ = 915
N5.C1.D0.R1.S16: Total Delay in PI ticks: TxDQS = 970, TxDQ = 938
N7.C0.D0.R1.S11: Dq Delay estimate: 413
N1.C0.D0.R1.S14: Dq Delay estimate: 383
N3.C1.D0.R0.S07: Total Delay in PI ticks: TxDQ = 933
N5.C1.D0.R1.S17: Total Delay in PI ticks: TxDQS = 937, TxDQ = 909
N7.C0.D0.R1.S12: Dq Delay estimate: 395
N1.C0.D0.R1.S15: Dq Delay estimate: 390
N3.C1.D0.R0.S08: Total Delay in PI ticks: TxDQ = 901
N5.C2.D0.R0: Write Training Coarse, lower nibbles / bytes
N7.C0.D0.R1.S13: Dq Delay estimate: 362
N1.C0.D0.R1.S16: Dq Delay estimate: 408
N3.C1.D0.R0.S09: Total Delay in PI ticks: TxDQ = 963
N5.C2.D0.R0.S00: Dq Delay estimate: 452
N7.C0.D0.R1.S14: Dq Delay estimate: 383
N1.C0.D0.R1.S17: Dq Delay estimate: 373
N3.C1.D0.R0.S10: Total Delay in PI ticks: TxDQ = 949
N5.C2.D0.R0.S01: Dq Delay estimate: 438
N7.C0.D0.R1.S15: Dq Delay estimate: 387
ACCM: F0 F0F0F0F0 F0F0F0F0
N3.C1.D0.R0.S11: Total Delay in PI ticks: TxDQ = 942
N5.C2.D0.R0.S02: Dq Delay estimate: 426
N7.C0.D0.R1.S16: Dq Delay estimate: 406
ACCM: F0 F0F0F0F0 F0F0F0F0
N3.C1.D0.R0.S12: Total Delay in PI ticks: TxDQ = 919
N5.C2.D0.R0.S03: Dq Delay estimate: 409
N7.C0.D0.R1.S17: Dq Delay estimate: 371
ACCM: F0 F0F0F0F0 F0F0F0F0
N3.C1.D0.R0.S13: Total Delay in PI ticks: TxDQ = 888
N5.C2.D0.R0.S04: Dq Delay estimate: 366
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: F0 F0F0F0F0 F0F0F0F0
N3.C1.D0.R0.S14: Total Delay in PI ticks: TxDQ = 900
N5.C2.D0.R0.S05: Dq Delay estimate: 394
ACCM: F0 F0F0F0F0 F0F0F0F0
N1.C0.D0.R1: CheckMCTest: result = 0x3FE00
N3.C1.D0.R0.S15: Total Delay in PI ticks: TxDQ = 914
N5.C2.D0.R0.S06: Dq Delay estimate: 398
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: F0 F0F0F0F0 F0F0F0F0
N3.C1.D0.R0.S16: Total Delay in PI ticks: TxDQ = 932
N5.C2.D0.R0.S07: Dq Delay estimate: 420
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: F0 F0F0F0F0 F0F0F0F0
N3.C1.D0.R0.S17: Total Delay in PI ticks: TxDQ = 901
N5.C2.D0.R0.S08: Dq Delay estimate: 383
N7.C0.D0.R1: CheckMCTest: result = 0x3FE00
ACCM: F0 F0F0F0F0 F0F0F0F0
N3.C1.D0.R1.S00: wrcmd2dqsstartlatency: 04
ACCM: 0F 0F9F9F0F 9F0F0F0F
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: F0 F0F0F0F0 F0F0F0F0
N3.C1.D0.R1.S00: RdPtrOffsetTxDq: 06
ACCM: 0F 0F9F9F0F 9F0F0F0F
ACCM: F0 F0F0F0F0 F0F0F0F0
N1.C0.D0.R1: CheckMCTest: result = 0x3FE00
N3.C1.D0.R1.S00: RdPtrOffsetTxDqs: 07
ACCM: 0F FF9F9F0F 9FFFFFFF
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: F0 F0F0F0F0 F0F0F0F0
N3.C1.D0.R1.S00: PiTxDqs: 35
ACCM: 0F FF9F9F0F 9FFFFFFF
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: F0 F0F0F0F0 F0F0F0F0
N3.C1.D0.R1.S01: wrcmd2dqsstartlatency: 04
N5.C2.D0.R0: CheckMCTest: result = 0x1DFFF
N7.C0.D0.R1: CheckMCTest: result = 0x3FE00
ACCM: 00 00000000 00000000
N3.C1.D0.R1.S01: RdPtrOffsetTxDq: 05
ACCM: 0F 0FDFDF0F DF0F0F0F
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: 00 00000000 00000000
N3.C1.D0.R1.S01: RdPtrOffsetTxDqs: 07
ACCM: 0F 0FDFDF0F DF0F0F0F
ACCM: F0 F0F0F0F0 F0F0F0F0
N1.C0.D0.R1: CheckMCTest: result = 0x3FE00
N3.C1.D0.R1.S01: PiTxDqs: 19
ACCM: 0F FFDFDF0F DFFFFFFF
ACCM: 00 00000000 00000000
ACCM: F0 F0F0F0F0 F0F0F0F0
N3.C1.D0.R1.S02: wrcmd2dqsstartlatency: 04
ACCM: 0F FFDFDF0F DFFFFFFF
ACCM: 00 00000000 00000000
ACCM: F0 F0F0F0F0 F0F0F0F0
N3.C1.D0.R1.S02: RdPtrOffsetTxDq: 05
N5.C2.D0.R0: CheckMCTest: result = 0x1DFFF
N7.C0.D0.R1: CheckMCTest: result = 0x3FE00
ACCM: 00 00000000 00000000
N3.C1.D0.R1.S02: RdPtrOffsetTxDqs: 07
ACCM: 0F 0FDFDF0F DF0F0F0F
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: 00 00000000 00000000
N3.C1.D0.R1.S02: PiTxDqs: 12
ACCM: 0F 0FDFDF0F DF0F0F0F
ACCM: F0 F0F0F0F0 F0F0F0F0
N1.C0.D0.R1: CheckMCTest: result = 0x3FE00
N3.C1.D0.R1.S03: wrcmd2dqsstartlatency: 04
ACCM: 00 FBD0D000 D0F0F0F0
ACCM: 00 00000000 00000000
N1.C0.D0.R1: CheckMCTest: passed
N3.C1.D0.R1.S03: RdPtrOffsetTxDq: 05
ACCM: 00 FBD0D000 D0F0F0F0
ACCM: 00 00000000 00000000
N1.C0.D0.R1: CheckMCTest: passed
N3.C1.D0.R1.S03: RdPtrOffsetTxDqs: 06
N5.C2.D0.R0: CheckMCTest: result = 0x1DFFF
N7.C0.D0.R1: CheckMCTest: result = 0x3FE00
N1.C0.D0.R1.S09: Offset Found: RdPtrOffsetDqs = 007
N3.C1.D0.R1.S03: PiTxDqs: 56
ACCM: 0F 0FDFDF0F DF0F0F0F
N7.C0.D0.R1: CheckMCTest: passed
N1.C0.D0.R1.S10: Offset Found: RdPtrOffsetDqs = 007
N3.C1.D0.R1.S04: wrcmd2dqsstartlatency: 04
ACCM: 0F 0FDFDF0F DF0F0F0F
N7.C0.D0.R1: CheckMCTest: passed
N1.C0.D0.R1.S11: Offset Found: RdPtrOffsetDqs = 007
N3.C1.D0.R1.S04: RdPtrOffsetTxDq: 04
ACCM: 00 FFD0D000 D0F0F0F0
N7.C0.D0.R1.S09: Offset Found: RdPtrOffsetDqs = 007
N1.C0.D0.R1.S12: Offset Found: RdPtrOffsetDqs = 006
N3.C1.D0.R1.S04: RdPtrOffsetTxDqs: 06
ACCM: 00 FFD0D000 D0F0F0F0
N7.C0.D0.R1.S10: Offset Found: RdPtrOffsetDqs = 007
N1.C0.D0.R1.S13: Offset Found: RdPtrOffsetDqs = 006
N3.C1.D0.R1.S04: PiTxDqs: 27
N5.C2.D0.R0: CheckMCTest: result = 0x1DFFF
N7.C0.D0.R1.S11: Offset Found: RdPtrOffsetDqs = 006
N1.C0.D0.R1.S14: Offset Found: RdPtrOffsetDqs = 006
N3.C1.D0.R1.S05: wrcmd2dqsstartlatency: 04
ACCM: 00 00D0D000 D0000000
N7.C0.D0.R1.S12: Offset Found: RdPtrOffsetDqs = 006
N1.C0.D0.R1.S15: Offset Found: RdPtrOffsetDqs = 006
N3.C1.D0.R1.S05: RdPtrOffsetTxDq: 05
ACCM: 00 00D0D000 D0000000
N7.C0.D0.R1.S13: Offset Found: RdPtrOffsetDqs = 006
N1.C0.D0.R1.S16: Offset Found: RdPtrOffsetDqs = 006
N3.C1.D0.R1.S05: RdPtrOffsetTxDqs: 06
ACCM: 00 F0D0D000 D0F0F0F0
N7.C0.D0.R1.S14: Offset Found: RdPtrOffsetDqs = 006
N1.C0.D0.R1.S17: Offset Found: RdPtrOffsetDqs = 006
N3.C1.D0.R1.S05: PiTxDqs: 40
ACCM: 00 F0D0D000 D0F0F0F0
N7.C0.D0.R1.S15: Offset Found: RdPtrOffsetDqs = 006
N1.C0: Calculating Optimimum DQS Values
N3.C1.D0.R1.S06: wrcmd2dqsstartlatency: 04
N5.C2.D0.R0: CheckMCTest: result = 0x1DE00
N7.C0.D0.R1.S16: Offset Found: RdPtrOffsetDqs = 006
N1.C0.D0.R0.S00: Total Delay in PI ticks: TxDQS = 993, TxDQ = 959
N3.C1.D0.R1.S06: RdPtrOffsetTxDq: 05
ACCM: 00 00D0D000 D0000000
N7.C0.D0.R1.S17: Offset Found: RdPtrOffsetDqs = 006
N1.C0.D0.R0.S01: Total Delay in PI ticks: TxDQS = 976, TxDQ = 943
N3.C1.D0.R1.S06: RdPtrOffsetTxDqs: 06
ACCM: 00 00D0D000 D0000000
N7.C0: Calculating Optimimum DQS Values
N1.C0.D0.R0.S02: Total Delay in PI ticks: TxDQS = 964, TxDQ = 929
N3.C1.D0.R1.S06: PiTxDqs: 52
ACCM: 00 F0D0D000 D0F0F0F0
N7.C0.D0.R0.S00: Total Delay in PI ticks: TxDQS = 993, TxDQ = 958
N1.C0.D0.R0.S03: Total Delay in PI ticks: TxDQS = 948, TxDQ = 912
N3.C1.D0.R1.S07: wrcmd2dqsstartlatency: 04
ACCM: 00 F0D0D000 D0F0F0F0
N7.C0.D0.R0.S01: Total Delay in PI ticks: TxDQS = 972, TxDQ = 938
N1.C0.D0.R0.S04: Total Delay in PI ticks: TxDQS = 912, TxDQ = 878
N3.C1.D0.R1.S07: RdPtrOffsetTxDq: 05
N5.C2.D0.R0: CheckMCTest: result = 0x1DE00
N7.C0.D0.R0.S02: Total Delay in PI ticks: TxDQS = 960, TxDQ = 927
N1.C0.D0.R0.S05: Total Delay in PI ticks: TxDQS = 930, TxDQ = 895
N3.C1.D0.R1.S07: RdPtrOffsetTxDqs: 07
N5.C2.D0.R0.S00: Offset Found: RdPtrOffsetDqs = 007
N7.C0.D0.R0.S03: Total Delay in PI ticks: TxDQS = 944, TxDQ = 909
N1.C0.D0.R0.S06: Total Delay in PI ticks: TxDQS = 936, TxDQ = 902
N3.C1.D0.R1.S07: PiTxDqs: 06
N5.C2.D0.R0.S01: Offset Found: RdPtrOffsetDqs = 007
N7.C0.D0.R0.S04: Total Delay in PI ticks: TxDQS = 910, TxDQ = 876
N1.C0.D0.R0.S07: Total Delay in PI ticks: TxDQS = 954, TxDQ = 920
N3.C1.D0.R1.S08: wrcmd2dqsstartlatency: 04
N5.C2.D0.R0.S02: Offset Found: RdPtrOffsetDqs = 007
N7.C0.D0.R0.S05: Total Delay in PI ticks: TxDQS = 929, TxDQ = 893
N1.C0.D0.R0.S08: Total Delay in PI ticks: TxDQS = 921, TxDQ = 888
N3.C1.D0.R1.S08: RdPtrOffsetTxDq: 05
N5.C2.D0.R0.S03: Offset Found: RdPtrOffsetDqs = 006
N7.C0.D0.R0.S06: Total Delay in PI ticks: TxDQS = 931, TxDQ = 900
N1.C0.D0.R0.S09: Total Delay in PI ticks: TxDQS = 993, TxDQ = 958
N3.C1.D0.R1.S08: RdPtrOffsetTxDqs: 06
N5.C2.D0.R0.S04: Offset Found: RdPtrOffsetDqs = 006
N7.C0.D0.R0.S07: Total Delay in PI ticks: TxDQS = 952, TxDQ = 916
N1.C0.D0.R0.S10: Total Delay in PI ticks: TxDQS = 976, TxDQ = 947
N3.C1.D0.R1.S08: PiTxDqs: 36
N5.C2.D0.R0.S05: Offset Found: RdPtrOffsetDqs = 006
N7.C0.D0.R0.S08: Total Delay in PI ticks: TxDQS = 919, TxDQ = 885
N1.C0.D0.R0.S11: Total Delay in PI ticks: TxDQS = 963, TxDQ = 929
N3.C1.D0.R1.S09: wrcmd2dqsstartlatency: 04
N5.C2.D0.R0.S06: Offset Found: RdPtrOffsetDqs = 006
N7.C0.D0.R0.S09: Total Delay in PI ticks: TxDQS = 991, TxDQ = 957
N1.C0.D0.R0.S12: Total Delay in PI ticks: TxDQS = 949, TxDQ = 915
N3.C1.D0.R1.S09: RdPtrOffsetTxDq: 06
N5.C2.D0.R0.S07: Offset Found: RdPtrOffsetDqs = 007
N7.C0.D0.R0.S10: Total Delay in PI ticks: TxDQS = 972, TxDQ = 937
N1.C0.D0.R0.S13: Total Delay in PI ticks: TxDQS = 912, TxDQ = 877
N3.C1.D0.R1.S09: RdPtrOffsetTxDqs: 07
N5.C2.D0.R0.S08: Offset Found: RdPtrOffsetDqs = 006
N7.C0.D0.R0.S11: Total Delay in PI ticks: TxDQS = 959, TxDQ = 925
N1.C0.D0.R0.S14: Total Delay in PI ticks: TxDQS = 928, TxDQ = 894
N3.C1.D0.R1.S09: PiTxDqs: 34
N5.C2.D0.R0: Write Training Coarse, upper nibbles
N7.C0.D0.R0.S12: Total Delay in PI ticks: TxDQS = 944, TxDQ = 910
N1.C0.D0.R0.S15: Total Delay in PI ticks: TxDQS = 936, TxDQ = 902
N3.C1.D0.R1.S10: wrcmd2dqsstartlatency: 04
N5.C2.D0.R0.S09: Dq Delay estimate: 448
N7.C0.D0.R0.S13: Total Delay in PI ticks: TxDQS = 910, TxDQ = 874
N1.C0.D0.R0.S16: Total Delay in PI ticks: TxDQS = 952, TxDQ = 919
N3.C1.D0.R1.S10: RdPtrOffsetTxDq: 05
N5.C2.D0.R0.S10: Dq Delay estimate: 440
N7.C0.D0.R0.S14: Total Delay in PI ticks: TxDQS = 929, TxDQ = 896
N1.C0.D0.R0.S17: Total Delay in PI ticks: TxDQS = 921, TxDQ = 885
N3.C1.D0.R1.S10: RdPtrOffsetTxDqs: 07
N5.C2.D0.R0.S11: Dq Delay estimate: 426
N7.C0.D0.R0.S15: Total Delay in PI ticks: TxDQS = 932, TxDQ = 899
N1.C0.D0.R1.S00: Total Delay in PI ticks: TxDQS = 994, TxDQ = 960
N3.C1.D0.R1.S10: PiTxDqs: 21
N5.C2.D0.R0.S12: Dq Delay estimate: 407
N7.C0.D0.R0.S16: Total Delay in PI ticks: TxDQS = 951, TxDQ = 917
N1.C0.D0.R1.S01: Total Delay in PI ticks: TxDQS = 975, TxDQ = 942
N3.C1.D0.R1.S11: wrcmd2dqsstartlatency: 04
N5.C2.D0.R0.S13: Dq Delay estimate: 367
N7.C0.D0.R0.S17: Total Delay in PI ticks: TxDQS = 920, TxDQ = 884
N1.C0.D0.R1.S02: Total Delay in PI ticks: TxDQS = 963, TxDQ = 928
N3.C1.D0.R1.S11: RdPtrOffsetTxDq: 05
N5.C2.D0.R0.S14: Dq Delay estimate: 397
N7.C0.D0.R1.S00: Total Delay in PI ticks: TxDQS = 991, TxDQ = 956
N1.C0.D0.R1.S03: Total Delay in PI ticks: TxDQS = 945, TxDQ = 909
N3.C1.D0.R1.S11: RdPtrOffsetTxDqs: 07
N5.C2.D0.R0.S15: Dq Delay estimate: 397
N7.C0.D0.R1.S01: Total Delay in PI ticks: TxDQS = 971, TxDQ = 936
N1.C0.D0.R1.S04: Total Delay in PI ticks: TxDQS = 912, TxDQ = 878
N3.C1.D0.R1.S11: PiTxDqs: 12
N5.C2.D0.R0.S16: Dq Delay estimate: 418
N7.C0.D0.R1.S02: Total Delay in PI ticks: TxDQS = 959, TxDQ = 925
N1.C0.D0.R1.S05: Total Delay in PI ticks: TxDQS = 930, TxDQ = 895
N3.C1.D0.R1.S12: wrcmd2dqsstartlatency: 04
N5.C2.D0.R0.S17: Dq Delay estimate: 383
N7.C0.D0.R1.S03: Total Delay in PI ticks: TxDQS = 943, TxDQ = 908
N1.C0.D0.R1.S06: Total Delay in PI ticks: TxDQS = 935, TxDQ = 901
N3.C1.D0.R1.S12: RdPtrOffsetTxDq: 05
ACCM: F0 F0F0F0F0 F0F0F0F0
N7.C0.D0.R1.S04: Total Delay in PI ticks: TxDQS = 910, TxDQ = 876
N1.C0.D0.R1.S07: Total Delay in PI ticks: TxDQS = 953, TxDQ = 919
N3.C1.D0.R1.S12: RdPtrOffsetTxDqs: 06
ACCM: F0 F0F0F0F0 F0F0F0F0
N7.C0.D0.R1.S05: Total Delay in PI ticks: TxDQS = 929, TxDQ = 894
N1.C0.D0.R1.S08: Total Delay in PI ticks: TxDQS = 919, TxDQ = 885
N3.C1.D0.R1.S12: PiTxDqs: 58
ACCM: F0 F0F0F0F0 F0F0F0F0
N7.C0.D0.R1.S06: Total Delay in PI ticks: TxDQS = 932, TxDQ = 899
N1.C0.D0.R1.S09: Total Delay in PI ticks: TxDQS = 993, TxDQ = 958
N3.C1.D0.R1.S13: wrcmd2dqsstartlatency: 04
ACCM: F0 F0F0F0F0 F0F0F0F0
N7.C0.D0.R1.S07: Total Delay in PI ticks: TxDQS = 952, TxDQ = 917
N1.C0.D0.R1.S10: Total Delay in PI ticks: TxDQS = 975, TxDQ = 945
N3.C1.D0.R1.S13: RdPtrOffsetTxDq: 04
N5.C2.D0.R0: CheckMCTest: result = 0x3FE00
N7.C0.D0.R1.S08: Total Delay in PI ticks: TxDQS = 918, TxDQ = 884
N1.C0.D0.R1.S11: Total Delay in PI ticks: TxDQS = 963, TxDQ = 929
N3.C1.D0.R1.S13: RdPtrOffsetTxDqs: 06
ACCM: F0 F0F0F0F0 F0F0F0F0
N7.C0.D0.R1.S09: Total Delay in PI ticks: TxDQS = 991, TxDQ = 957
N1.C0.D0.R1.S12: Total Delay in PI ticks: TxDQS = 949, TxDQ = 915
N3.C1.D0.R1.S13: PiTxDqs: 25
ACCM: F0 F0F0F0F0 F0F0F0F0
N7.C0.D0.R1.S10: Total Delay in PI ticks: TxDQS = 971, TxDQ = 936
N1.C0.D0.R1.S13: Total Delay in PI ticks: TxDQS = 913, TxDQ = 878
N3.C1.D0.R1.S14: wrcmd2dqsstartlatency: 04
ACCM: F0 F0F0F0F0 F0F0F0F0
N7.C0.D0.R1.S11: Total Delay in PI ticks: TxDQS = 959, TxDQ = 925
N1.C0.D0.R1.S14: Total Delay in PI ticks: TxDQS = 929, TxDQ = 895
N3.C1.D0.R1.S14: RdPtrOffsetTxDq: 05
ACCM: F0 F0F0F0F0 F0F0F0F0
N7.C0.D0.R1.S12: Total Delay in PI ticks: TxDQS = 942, TxDQ = 907
N1.C0.D0.R1.S15: Total Delay in PI ticks: TxDQS = 935, TxDQ = 902
N3.C1.D0.R1.S14: RdPtrOffsetTxDqs: 06
N5.C2.D0.R0: CheckMCTest: result = 0x3FE00
N7.C0.D0.R1.S13: Total Delay in PI ticks: TxDQS = 910, TxDQ = 874
N1.C0.D0.R1.S16: Total Delay in PI ticks: TxDQS = 952, TxDQ = 920
N3.C1.D0.R1.S14: PiTxDqs: 39
ACCM: F0 F0F0F0F0 F0F0F0F0
N7.C0.D0.R1.S14: Total Delay in PI ticks: TxDQS = 928, TxDQ = 895
N1.C0.D0.R1.S17: Total Delay in PI ticks: TxDQS = 920, TxDQ = 885
N3.C1.D0.R1.S15: wrcmd2dqsstartlatency: 04
ACCM: F0 F0F0F0F0 F0F0F0F0
N7.C0.D0.R1.S15: Total Delay in PI ticks: TxDQS = 932, TxDQ = 899
N1.C1.D0.R0: Write Training Coarse, lower nibbles / bytes
N3.C1.D0.R1.S15: RdPtrOffsetTxDq: 05
ACCM: 00 00000000 00000000
N7.C0.D0.R1.S16: Total Delay in PI ticks: TxDQS = 952, TxDQ = 918
N1.C1.D0.R0.S00: Dq Delay estimate: 453
N3.C1.D0.R1.S15: RdPtrOffsetTxDqs: 06
ACCM: 00 00000000 00000000
N7.C0.D0.R1.S17: Total Delay in PI ticks: TxDQS = 919, TxDQ = 883
N1.C1.D0.R0.S01: Dq Delay estimate: 438
N3.C1.D0.R1.S15: PiTxDqs: 52
N5.C2.D0.R0: CheckMCTest: result = 0x3FE00
N7.C1.D0.R0: Write Training Coarse, lower nibbles / bytes
N1.C1.D0.R0.S02: Dq Delay estimate: 427
N3.C1.D0.R1.S16: wrcmd2dqsstartlatency: 04
ACCM: F0 F0F0F0F0 F0F0F0F0
N7.C1.D0.R0.S00: Dq Delay estimate: 459
N1.C1.D0.R0.S03: Dq Delay estimate: 411
N3.C1.D0.R1.S16: RdPtrOffsetTxDq: 05
ACCM: F0 F0F0F0F0 F0F0F0F0
N7.C1.D0.R0.S01: Dq Delay estimate: 440
N1.C1.D0.R0.S04: Dq Delay estimate: 377
N3.C1.D0.R1.S16: RdPtrOffsetTxDqs: 07
ACCM: 00 00000000 00000000
N7.C1.D0.R0.S02: Dq Delay estimate: 434
N1.C1.D0.R0.S05: Dq Delay estimate: 390
N3.C1.D0.R1.S16: PiTxDqs: 06
ACCM: 00 00000000 00000000
N7.C1.D0.R0.S03: Dq Delay estimate: 415
N1.C1.D0.R0.S06: Dq Delay estimate: 404
N3.C1.D0.R1.S17: wrcmd2dqsstartlatency: 04
N5.C2.D0.R0: CheckMCTest: result = 0x3FE00
N7.C1.D0.R0.S04: Dq Delay estimate: 383
N1.C1.D0.R0.S07: Dq Delay estimate: 419
N3.C1.D0.R1.S17: RdPtrOffsetTxDq: 05
N5.C2.D0.R0: CheckMCTest: passed
N7.C1.D0.R0.S05: Dq Delay estimate: 397
N1.C1.D0.R0.S08: Dq Delay estimate: 388
N3.C1.D0.R1.S17: RdPtrOffsetTxDqs: 06
N5.C2.D0.R0: CheckMCTest: passed
N7.C1.D0.R0.S06: Dq Delay estimate: 409
ACCM: 0F 0F9F0F0F DF0F0F0F
N3.C1.D0.R1.S17: PiTxDqs: 37
N5.C2.D0.R0.S09: Offset Found: RdPtrOffsetDqs = 007
N7.C1.D0.R0.S07: Dq Delay estimate: 430
ACCM: 0F 0F9F0F0F DF0F0F0F
N3.C1.D0.R1.S00: RdPtrOffsetTxDq: 07
N5.C2.D0.R0.S10: Offset Found: RdPtrOffsetDqs = 007
N7.C1.D0.R0.S08: Dq Delay estimate: 396
ACCM: 0F FF9F0F0F FFFFFFFF
N3.C1.D0.R1.S01: RdPtrOffsetTxDq: 06
N5.C2.D0.R0.S11: Offset Found: RdPtrOffsetDqs = 007
ACCM: 9F 0F9F9F0F 0F0F0F0F
ACCM: 0F FF9F0F0F FFFFFFFF
N3.C1.D0.R1.S02: RdPtrOffsetTxDq: 06
N5.C2.D0.R0.S12: Offset Found: RdPtrOffsetDqs = 006
ACCM: 9F 0F9F9F0F 0F0F0F0F
N1.C1.D0.R0: CheckMCTest: result = 0x19FFF
N3.C1.D0.R1.S03: RdPtrOffsetTxDq: 06
N5.C2.D0.R0.S13: Offset Found: RdPtrOffsetDqs = 006
ACCM: 9F FF9F9F0F FFFFFFFF
ACCM: 0F 0FDF0F0F DF0F0F0F
N3.C1.D0.R1.S04: RdPtrOffsetTxDq: 05
N5.C2.D0.R0.S14: Offset Found: RdPtrOffsetDqs = 006
ACCM: 9F FF9F9F0F FFFFFFFF
ACCM: 0F 0FDF0F0F DF0F0F0F
N3.C1.D0.R1.S05: RdPtrOffsetTxDq: 06
N5.C2.D0.R0.S15: Offset Found: RdPtrOffsetDqs = 006
N7.C1.D0.R0: CheckMCTest: result = 0x3DFFF
ACCM: 0F FFDF0F0F FFFFFFFF
N3.C1.D0.R1.S06: RdPtrOffsetTxDq: 06
N5.C2.D0.R0.S16: Offset Found: RdPtrOffsetDqs = 007
ACCM: DF 0FDFDF0F 0F0F0F0F
ACCM: 0F FFDF0F0F FFFFFFFF
N3.C1.D0.R1.S07: RdPtrOffsetTxDq: 06
N5.C2.D0.R0.S17: Offset Found: RdPtrOffsetDqs = 006
ACCM: DF 0FDFDF0F 0F0F0F0F
N1.C1.D0.R0: CheckMCTest: result = 0x19FFF
N3.C1.D0.R1.S08: RdPtrOffsetTxDq: 06
N5.C2.D0.R1: Write Training Coarse, lower nibbles / bytes
ACCM: DF FFDFDF0F FFFFFFFF
ACCM: 0F 0FDF0F0F DF0F0F0F
N3.C1.D0.R1.S09: RdPtrOffsetTxDq: 07
N5.C2.D0.R1.S00: Dq Delay estimate: 450
ACCM: DF FFDFDF0F FFFFFFFF
ACCM: 0F 0FDF0F0F DF0F0F0F
N3.C1.D0.R1.S10: RdPtrOffsetTxDq: 06
N5.C2.D0.R1.S01: Dq Delay estimate: 437
N7.C1.D0.R0: CheckMCTest: result = 0x3DFFF
ACCM: 00 F0D00000 FBF0F0F0
N3.C1.D0.R1.S11: RdPtrOffsetTxDq: 06
N5.C2.D0.R1.S02: Dq Delay estimate: 426
ACCM: DF 0FDFDF0F 0F0F0F0F
ACCM: 00 F0D00000 FBF0F0F0
N3.C1.D0.R1.S12: RdPtrOffsetTxDq: 06
N5.C2.D0.R1.S03: Dq Delay estimate: 408
ACCM: DF 0FDFDF0F 0F0F0F0F
N1.C1.D0.R0: CheckMCTest: result = 0x19FFF
N3.C1.D0.R1.S13: RdPtrOffsetTxDq: 05
N5.C2.D0.R1.S04: Dq Delay estimate: 366
ACCM: D0 F0D0D000 F0F0F0F0
ACCM: 0F 0FDF0F0F DF0F0F0F
N3.C1.D0.R1.S14: RdPtrOffsetTxDq: 06
N5.C2.D0.R1.S05: Dq Delay estimate: 394
ACCM: D0 F0D0D000 F0F0F0F0
ACCM: 0F 0FDF0F0F DF0F0F0F
N3.C1.D0.R1.S15: RdPtrOffsetTxDq: 06
N5.C2.D0.R1.S06: Dq Delay estimate: 397
N7.C1.D0.R0: CheckMCTest: result = 0x3DFFF
ACCM: 00 F0DD0000 FFF0F0F0
N3.C1.D0.R1.S16: RdPtrOffsetTxDq: 06
N5.C2.D0.R1.S07: Dq Delay estimate: 418
ACCM: DF 0FDFDF0F 0F0F0F0F
ACCM: 00 F0DD0000 FFF0F0F0
N3.C1.D0.R1.S17: RdPtrOffsetTxDq: 06
N5.C2.D0.R1.S08: Dq Delay estimate: 383
ACCM: DF 0FDFDF0F 0F0F0F0F
N1.C1.D0.R0: CheckMCTest: result = 0x19FFF
N3.C1.D0.R1.S00: RdPtrOffsetTxDq: 08
ACCM: 0F 0F0F0F0F 0F0F0F0F
ACCM: D0 F0D0D000 F0F0F0F0
ACCM: 00 00D00000 D0000000
N3.C1.D0.R1.S01: RdPtrOffsetTxDq: 07
ACCM: 0F 0F0F0F0F 0F0F0F0F
ACCM: D0 F0D0D000 F0F0F0F0
ACCM: 00 00D00000 D0000000
N3.C1.D0.R1.S02: RdPtrOffsetTxDq: 07
ACCM: 0F 0F0F0F0F 0F0F0F0F
N7.C1.D0.R0: CheckMCTest: result = 0x3DFFF
ACCM: 00 F0D00000 F0F0F0F0
N3.C1.D0.R1.S03: RdPtrOffsetTxDq: 07
ACCM: 0F 0F0F0F0F 0F0F0F0F
ACCM: 00 00D0D000 00000000
ACCM: 00 F0D00000 F0F0F0F0
N3.C1.D0.R1.S04: RdPtrOffsetTxDq: 06
N5.C2.D0.R1: CheckMCTest: result = 0x1FF
ACCM: 00 00D0D000 00000000
N1.C1.D0.R0: CheckMCTest: result = 0x19E00
N3.C1.D0.R1.S05: RdPtrOffsetTxDq: 07
ACCM: 0F 0F0F0F0F 0F0F0F0F
ACCM: 00 F0D0D000 F0F0F0F0
ACCM: 00 00D00000 D0000000
N3.C1.D0.R1.S06: RdPtrOffsetTxDq: 07
ACCM: 0F 0F0F0F0F 0F0F0F0F
ACCM: 00 F0D0D000 F0F0F0F0
ACCM: 00 00D00000 D0000000
N3.C1.D0.R1.S07: RdPtrOffsetTxDq: 07
ACCM: 0F 0F0F0F0F 0F0F0F0F
N7.C1.D0.R0: CheckMCTest: result = 0x1DE00
ACCM: 00 F0D00000 F0F0F0F0
N3.C1.D0.R1.S08: RdPtrOffsetTxDq: 07
ACCM: 0F 0F0F0F0F 0F0F0F0F
ACCM: 00 00D0D000 00000000
ACCM: 00 F0D00000 F0F0F0F0
N3.C1.D0.R1.S09: RdPtrOffsetTxDq: 08
N5.C2.D0.R1: CheckMCTest: result = 0x1FF
ACCM: 00 00D0D000 00000000
N1.C1.D0.R0: CheckMCTest: result = 0x19E00
N3.C1.D0.R1.S10: RdPtrOffsetTxDq: 07
ACCM: 0F 0F0F0F0F 0F0F0F0F
ACCM: 00 F0D0D000 F0F0F0F0
N1.C1.D0.R0.S00: Offset Found: RdPtrOffsetDqs = 007
N3.C1.D0.R1.S11: RdPtrOffsetTxDq: 07
ACCM: 0F 0F0F0F0F 0F0F0F0F
ACCM: 00 F0D0D000 F0F0F0F0
N1.C1.D0.R0.S01: Offset Found: RdPtrOffsetDqs = 007
N3.C1.D0.R1.S12: RdPtrOffsetTxDq: 07
ACCM: 00 00000000 0000000B
N7.C1.D0.R0: CheckMCTest: result = 0x1DE00
N1.C1.D0.R0.S02: Offset Found: RdPtrOffsetDqs = 007
N3.C1.D0.R1.S13: RdPtrOffsetTxDq: 06
ACCM: 00 00000000 0000000B
N7.C1.D0.R0.S00: Offset Found: RdPtrOffsetDqs = 007
N1.C1.D0.R0.S03: Offset Found: RdPtrOffsetDqs = 006
N3.C1.D0.R1.S14: RdPtrOffsetTxDq: 07
N5.C2.D0.R1: CheckMCTest: result = 0x1FF
N7.C1.D0.R0.S01: Offset Found: RdPtrOffsetDqs = 007
N1.C1.D0.R0.S04: Offset Found: RdPtrOffsetDqs = 006
N3.C1.D0.R1.S15: RdPtrOffsetTxDq: 07
ACCM: 0F 0F0F0F0F 0F0F0F0F
N7.C1.D0.R0.S02: Offset Found: RdPtrOffsetDqs = 007
N1.C1.D0.R0.S05: Offset Found: RdPtrOffsetDqs = 006
N3.C1.D0.R1.S16: RdPtrOffsetTxDq: 07
ACCM: 0F 0F0F0F0F 0F0F0F0F
N7.C1.D0.R0.S03: Offset Found: RdPtrOffsetDqs = 007
N1.C1.D0.R0.S06: Offset Found: RdPtrOffsetDqs = 006
N3.C1.D0.R1.S17: RdPtrOffsetTxDq: 07
ACCM: 00 00000000 0000000F
N7.C1.D0.R0.S04: Offset Found: RdPtrOffsetDqs = 006
N1.C1.D0.R0.S07: Offset Found: RdPtrOffsetDqs = 007
N3.C1.D0.R1.S00: Total Delay in PI ticks: TxDQ = 964
ACCM: 00 00000000 0000000F
N7.C1.D0.R0.S05: Offset Found: RdPtrOffsetDqs = 006
N1.C1.D0.R0.S08: Offset Found: RdPtrOffsetDqs = 006
N3.C1.D0.R1.S01: Total Delay in PI ticks: TxDQ = 946
N5.C2.D0.R1: CheckMCTest: result = 0x1FF
N7.C1.D0.R0.S06: Offset Found: RdPtrOffsetDqs = 006
N1.C1.D0.R0: Write Training Coarse, upper nibbles
N3.C1.D0.R1.S02: Total Delay in PI ticks: TxDQ = 937
N5.C2.D0.R1: CheckMCTest: passed
N7.C1.D0.R0.S07: Offset Found: RdPtrOffsetDqs = 007
N1.C1.D0.R0.S09: Dq Delay estimate: 453
N3.C1.D0.R1.S03: Total Delay in PI ticks: TxDQ = 919
N5.C2.D0.R1: CheckMCTest: passed
N7.C1.D0.R0.S08: Offset Found: RdPtrOffsetDqs = 006
N1.C1.D0.R0.S10: Dq Delay estimate: 438
N3.C1.D0.R1.S04: Total Delay in PI ticks: TxDQ = 889
N5.C2.D0.R1.S00: Offset Found: RdPtrOffsetDqs = 007
N7.C1.D0.R0: Write Training Coarse, upper nibbles
N1.C1.D0.R0.S11: Dq Delay estimate: 426
N3.C1.D0.R1.S05: Total Delay in PI ticks: TxDQ = 901
N5.C2.D0.R1.S01: Offset Found: RdPtrOffsetDqs = 007
N7.C1.D0.R0.S09: Dq Delay estimate: 456
N1.C1.D0.R0.S12: Dq Delay estimate: 412
N3.C1.D0.R1.S06: Total Delay in PI ticks: TxDQ = 914
N5.C2.D0.R1.S02: Offset Found: RdPtrOffsetDqs = 007
N7.C1.D0.R0.S10: Dq Delay estimate: 442
N1.C1.D0.R0.S13: Dq Delay estimate: 381
N3.C1.D0.R1.S07: Total Delay in PI ticks: TxDQ = 933
N5.C2.D0.R1.S03: Offset Found: RdPtrOffsetDqs = 006
N7.C1.D0.R0.S11: Dq Delay estimate: 435
N1.C1.D0.R0.S14: Dq Delay estimate: 389
N3.C1.D0.R1.S08: Total Delay in PI ticks: TxDQ = 898
N5.C2.D0.R1.S04: Offset Found: RdPtrOffsetDqs = 006
N7.C1.D0.R0.S12: Dq Delay estimate: 416
N1.C1.D0.R0.S15: Dq Delay estimate: 404
N3.C1.D0.R1.S09: Total Delay in PI ticks: TxDQ = 961
N5.C2.D0.R1.S05: Offset Found: RdPtrOffsetDqs = 006
N7.C1.D0.R0.S13: Dq Delay estimate: 381
N1.C1.D0.R0.S16: Dq Delay estimate: 420
N3.C1.D0.R1.S10: Total Delay in PI ticks: TxDQ = 948
N5.C2.D0.R1.S06: Offset Found: RdPtrOffsetDqs = 006
N7.C1.D0.R0.S14: Dq Delay estimate: 397
N1.C1.D0.R0.S17: Dq Delay estimate: 392
N3.C1.D0.R1.S11: Total Delay in PI ticks: TxDQ = 939
N5.C2.D0.R1.S07: Offset Found: RdPtrOffsetDqs = 007
N7.C1.D0.R0.S15: Dq Delay estimate: 408
ACCM: F0 F0F0F0F0 F0F0F0F0
N3.C1.D0.R1.S12: Total Delay in PI ticks: TxDQ = 920
N5.C2.D0.R1.S08: Offset Found: RdPtrOffsetDqs = 006
N7.C1.D0.R0.S16: Dq Delay estimate: 427
ACCM: F0 F0F0F0F0 F0F0F0F0
N3.C1.D0.R1.S13: Total Delay in PI ticks: TxDQ = 887
N5.C2.D0.R1: Write Training Coarse, upper nibbles
N7.C1.D0.R0.S17: Dq Delay estimate: 395
ACCM: F0 F0F0F0F0 F0F0F0F0
N3.C1.D0.R1.S14: Total Delay in PI ticks: TxDQ = 901
N5.C2.D0.R1.S09: Dq Delay estimate: 448
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: F0 F0F0F0F0 F0F0F0F0
N3.C1.D0.R1.S15: Total Delay in PI ticks: TxDQ = 916
N5.C2.D0.R1.S10: Dq Delay estimate: 439
ACCM: F0 F0F0F0F0 F0F0F0F0
N1.C1.D0.R0: CheckMCTest: result = 0x3FE00
N3.C1.D0.R1.S16: Total Delay in PI ticks: TxDQ = 931
N5.C2.D0.R1.S11: Dq Delay estimate: 427
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: F0 F0F0F0F0 F0F0F0F0
N3.C1.D0.R1.S17: Total Delay in PI ticks: TxDQ = 901
N5.C2.D0.R1.S12: Dq Delay estimate: 409
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: F0 F0F0F0F0 F0F0F0F0
N3.C1: Calculating Optimimum DQ/DQS Values
N5.C2.D0.R1.S13: Dq Delay estimate: 367
N7.C1.D0.R0: CheckMCTest: result = 0x3FE00
ACCM: F0 F0F0F0F0 F0F0F0F0
N5.C2.D0.R1.S14: Dq Delay estimate: 397
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: F0 F0F0F0F0 F0F0F0F0
START_DATA_TX_DQ
N5.C2.D0.R1.S15: Dq Delay estimate: 397
ACCM: F0 F0F0F0F0 F0F0F0F0
N1.C1.D0.R0: CheckMCTest: result = 0x3FE00
N3.C1.S00: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 009, RdPtrOffsetTxDqs = 009
N5.C2.D0.R1.S16: Dq Delay estimate: 421
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: F0 F0F0F0F0 F0F0F0F0
N3.C1.S00: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 009, RdPtrOffsetTxDqs = 009
N5.C2.D0.R1.S17: Dq Delay estimate: 382
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: F0 F0F0F0F0 F0F0F0F0
N3.C1.S01: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 009
ACCM: F0 F0F0F0F0 F0F0F0F0
N7.C1.D0.R0: CheckMCTest: result = 0x3FE00
ACCM: 00 00000000 00000000
N3.C1.S01: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 009
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: 00 00000000 00000000
N3.C1.S02: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 009
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: F0 F0F0F0F0 F0F0F0F0
N1.C1.D0.R0: CheckMCTest: result = 0x3FE00
N3.C1.S02: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 009
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: 00 00000000 00000000
ACCM: F0 F0F0F0F0 F0F0F0F0
N3.C1.S03: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 008
N5.C2.D0.R1: CheckMCTest: result = 0x3FE00
ACCM: 00 00000000 00000000
ACCM: F0 F0F0F0F0 F0F0F0F0
N3.C1.S03: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 008
ACCM: F0 F0F0F0F0 F0F0F0F0
N7.C1.D0.R0: CheckMCTest: result = 0x3FE00
ACCM: 00 00000000 00000000
N3.C1.S04: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 007, RdPtrOffsetTxDqs = 008
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: 00 00000000 00000000
N3.C1.S04: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 007, RdPtrOffsetTxDqs = 008
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: F0 F0F0F0F0 F0F0F0F0
N1.C1.D0.R0: CheckMCTest: result = 0x3FE00
N3.C1.S05: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 008
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: 00 00000000 00000000
N1.C1.D0.R0: CheckMCTest: passed
N3.C1.S05: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 008
N5.C2.D0.R1: CheckMCTest: result = 0x3FE00
ACCM: 00 00000000 00000000
N1.C1.D0.R0: CheckMCTest: passed
N3.C1.S06: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 008
ACCM: F0 F0F0F0F0 F0F0F0F0
N7.C1.D0.R0: CheckMCTest: result = 0x3FE00
N1.C1.D0.R0.S09: Offset Found: RdPtrOffsetDqs = 007
N3.C1.S06: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 008
ACCM: F0 F0F0F0F0 F0F0F0F0
N7.C1.D0.R0: CheckMCTest: passed
N1.C1.D0.R0.S10: Offset Found: RdPtrOffsetDqs = 007
N3.C1.S07: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 009
ACCM: 00 000000B0 00000000
N7.C1.D0.R0: CheckMCTest: passed
N1.C1.D0.R0.S11: Offset Found: RdPtrOffsetDqs = 007
N3.C1.S07: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 009
ACCM: 00 000000B0 00000000
N7.C1.D0.R0.S09: Offset Found: RdPtrOffsetDqs = 007
N1.C1.D0.R0.S12: Offset Found: RdPtrOffsetDqs = 006
N3.C1.S08: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 008
N5.C2.D0.R1: CheckMCTest: result = 0x3FE00
N7.C1.D0.R0.S10: Offset Found: RdPtrOffsetDqs = 007
N1.C1.D0.R0.S13: Offset Found: RdPtrOffsetDqs = 006
N3.C1.S08: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 008
ACCM: F0 F0F0F0F0 F0F0F0F0
N7.C1.D0.R0.S11: Offset Found: RdPtrOffsetDqs = 007
N1.C1.D0.R0.S14: Offset Found: RdPtrOffsetDqs = 006
N3.C1.D0.R0.S00: TxDqs: plus1 = 1, minus1 = 0, PI = 35, DB = 0
ACCM: F0 F0F0F0F0 F0F0F0F0
N7.C1.D0.R0.S12: Offset Found: RdPtrOffsetDqs = 007
N1.C1.D0.R0.S15: Offset Found: RdPtrOffsetDqs = 006
N3.C1.D0.R0.S00: TxDq : plus1 = 1, minus1 = 0, PI = 04, DB = 1
ACCM: 00 000000F0 00000000
N7.C1.D0.R0.S13: Offset Found: RdPtrOffsetDqs = 006
N1.C1.D0.R0.S16: Offset Found: RdPtrOffsetDqs = 007
N3.C1.D0.R0.S01: TxDqs: plus1 = 1, minus1 = 0, PI = 19, DB = 0
ACCM: 00 000000F0 00000000
N7.C1.D0.R0.S14: Offset Found: RdPtrOffsetDqs = 006
N1.C1.D0.R0.S17: Offset Found: RdPtrOffsetDqs = 006
N3.C1.D0.R0.S01: TxDq : plus1 = 1, minus1 = 0, PI = 51, DB = 1
N5.C2.D0.R1: CheckMCTest: result = 0x3FE00
N7.C1.D0.R0.S15: Offset Found: RdPtrOffsetDqs = 006
N1.C1.D0.R1: Write Training Coarse, lower nibbles / bytes
N3.C1.D0.R0.S02: TxDqs: plus1 = 1, minus1 = 0, PI = 12, DB = 1
N5.C2.D0.R1: CheckMCTest: passed
N7.C1.D0.R0.S16: Offset Found: RdPtrOffsetDqs = 007
N1.C1.D0.R1.S00: Dq Delay estimate: 453
N3.C1.D0.R0.S02: TxDq : plus1 = 1, minus1 = 0, PI = 42, DB = 0
N5.C2.D0.R1: CheckMCTest: passed
N7.C1.D0.R0.S17: Offset Found: RdPtrOffsetDqs = 006
N1.C1.D0.R1.S01: Dq Delay estimate: 435
N3.C1.D0.R0.S03: TxDqs: plus1 = 1, minus1 = 0, PI = 57, DB = 1
N5.C2.D0.R1.S09: Offset Found: RdPtrOffsetDqs = 007
N7.C1.D0.R1: Write Training Coarse, lower nibbles / bytes
N1.C1.D0.R1.S02: Dq Delay estimate: 426
N3.C1.D0.R0.S03: TxDq : plus1 = 1, minus1 = 0, PI = 24, DB = 0
N5.C2.D0.R1.S10: Offset Found: RdPtrOffsetDqs = 007
N7.C1.D0.R1.S00: Dq Delay estimate: 460
N1.C1.D0.R1.S03: Dq Delay estimate: 409
N3.C1.D0.R0.S04: TxDqs: plus1 = 1, minus1 = 0, PI = 26, DB = 0
N5.C2.D0.R1.S11: Offset Found: RdPtrOffsetDqs = 007
N7.C1.D0.R1.S01: Dq Delay estimate: 439
N1.C1.D0.R1.S04: Dq Delay estimate: 378
N3.C1.D0.R0.S04: TxDq : plus1 = 1, minus1 = 0, PI = 56, DB = 1
N5.C2.D0.R1.S12: Offset Found: RdPtrOffsetDqs = 006
N7.C1.D0.R1.S02: Dq Delay estimate: 432
N1.C1.D0.R1.S05: Dq Delay estimate: 390
N3.C1.D0.R0.S05: TxDqs: plus1 = 1, minus1 = 0, PI = 40, DB = 0
N5.C2.D0.R1.S13: Offset Found: RdPtrOffsetDqs = 006
N7.C1.D0.R1.S03: Dq Delay estimate: 414
N1.C1.D0.R1.S06: Dq Delay estimate: 403
N3.C1.D0.R0.S05: TxDq : plus1 = 1, minus1 = 0, PI = 05, DB = 1
N5.C2.D0.R1.S14: Offset Found: RdPtrOffsetDqs = 006
N7.C1.D0.R1.S04: Dq Delay estimate: 384
N1.C1.D0.R1.S07: Dq Delay estimate: 420
N3.C1.D0.R0.S06: TxDqs: plus1 = 1, minus1 = 0, PI = 52, DB = 1
N5.C2.D0.R1.S15: Offset Found: RdPtrOffsetDqs = 006
N7.C1.D0.R1.S05: Dq Delay estimate: 396
N1.C1.D0.R1.S08: Dq Delay estimate: 388
N3.C1.D0.R0.S06: TxDq : plus1 = 1, minus1 = 0, PI = 18, DB = 0
N5.C2.D0.R1.S16: Offset Found: RdPtrOffsetDqs = 007
N7.C1.D0.R1.S06: Dq Delay estimate: 409
ACCM: 0F 0F0F0F0F 0F0F0F0F
N3.C1.D0.R0.S07: TxDqs: plus1 = 1, minus1 = 0, PI = 07, DB = 1
N5.C2.D0.R1.S17: Offset Found: RdPtrOffsetDqs = 006
N7.C1.D0.R1.S07: Dq Delay estimate: 427
ACCM: 0F 0F0F0F0F 0F0F0F0F
N3.C1.D0.R0.S07: TxDq : plus1 = 1, minus1 = 0, PI = 37, DB = 0
N5.C2: Calculating Optimimum DQS Values
N7.C1.D0.R1.S08: Dq Delay estimate: 397
ACCM: 0F 0F0F0F0F 0F0F0F0F
N3.C1.D0.R0.S08: TxDqs: plus1 = 1, minus1 = 0, PI = 37, DB = 0
N5.C2.D0.R0.S00: Total Delay in PI ticks: TxDQS = 997, TxDQ = 964
ACCM: 0F 0F0F0F0F 0F0F0F0F
ACCM: 0F 0F0F0F0F 0F0F0F0F
N3.C1.D0.R0.S08: TxDq : plus1 = 1, minus1 = 0, PI = 03, DB = 1
N5.C2.D0.R0.S01: Total Delay in PI ticks: TxDQS = 984, TxDQ = 950
ACCM: 0F 0F0F0F0F 0F0F0F0F
N1.C1.D0.R1: CheckMCTest: result = 0x1FF
N3.C1.D0.R0.S09: TxDqs: plus1 = 1, minus1 = 0, PI = 34, DB = 0
N5.C2.D0.R0.S02: Total Delay in PI ticks: TxDQS = 972, TxDQ = 938
ACCM: 0F 0F0F0F0F 0F0F0F0F
ACCM: 0F 0F0F0F0F 0F0F0F0F
N3.C1.D0.R0.S09: TxDq : plus1 = 1, minus1 = 0, PI = 02, DB = 1
N5.C2.D0.R0.S03: Total Delay in PI ticks: TxDQS = 955, TxDQ = 921
ACCM: 0F 0F0F0F0F 0F0F0F0F
ACCM: 0F 0F0F0F0F 0F0F0F0F
N3.C1.D0.R0.S10: TxDqs: plus1 = 1, minus1 = 0, PI = 21, DB = 0
N5.C2.D0.R0.S04: Total Delay in PI ticks: TxDQS = 912, TxDQ = 878
N7.C1.D0.R1: CheckMCTest: result = 0x1FF
ACCM: 0F 0F0F0F0F 0F0F0F0F
N3.C1.D0.R0.S10: TxDq : plus1 = 1, minus1 = 0, PI = 52, DB = 1
N5.C2.D0.R0.S05: Total Delay in PI ticks: TxDQS = 943, TxDQ = 906
ACCM: 0F 0F0F0F0F 0F0F0F0F
ACCM: 0F 0F0F0F0F 0F0F0F0F
N3.C1.D0.R0.S11: TxDqs: plus1 = 1, minus1 = 0, PI = 12, DB = 1
N5.C2.D0.R0.S06: Total Delay in PI ticks: TxDQS = 943, TxDQ = 910
ACCM: 0F 0F0F0F0F 0F0F0F0F
N1.C1.D0.R1: CheckMCTest: result = 0x1FF
N3.C1.D0.R0.S11: TxDq : plus1 = 1, minus1 = 0, PI = 44, DB = 0
N5.C2.D0.R0.S07: Total Delay in PI ticks: TxDQS = 966, TxDQ = 932
ACCM: 0F 0F0F0F0F 0F0F0F0F
ACCM: 0F 0F0F0F0F 0F0F0F0F
N3.C1.D0.R0.S12: TxDqs: plus1 = 1, minus1 = 0, PI = 58, DB = 1
N5.C2.D0.R0.S08: Total Delay in PI ticks: TxDQS = 929, TxDQ = 895
ACCM: 0F 0F0F0F0F 0F0F0F0F
ACCM: 0F 0F0F0F0F 0F0F0F0F
N3.C1.D0.R0.S12: TxDq : plus1 = 1, minus1 = 0, PI = 23, DB = 0
N5.C2.D0.R0.S09: Total Delay in PI ticks: TxDQS = 995, TxDQ = 960
N7.C1.D0.R1: CheckMCTest: result = 0x1FF
ACCM: 00 00000000 00000000
N3.C1.D0.R0.S13: TxDqs: plus1 = 1, minus1 = 0, PI = 25, DB = 0
N5.C2.D0.R0.S10: Total Delay in PI ticks: TxDQS = 984, TxDQ = 952
ACCM: 0F 0F0F0F0F 0F0F0F0F
ACCM: 00 00000000 00000000
N3.C1.D0.R0.S13: TxDq : plus1 = 1, minus1 = 0, PI = 55, DB = 1
N5.C2.D0.R0.S11: Total Delay in PI ticks: TxDQS = 973, TxDQ = 938
ACCM: 0F 0F0F0F0F 0F0F0F0F
N1.C1.D0.R1: CheckMCTest: result = 0x1FF
N3.C1.D0.R0.S14: TxDqs: plus1 = 1, minus1 = 0, PI = 38, DB = 0
N5.C2.D0.R0.S12: Total Delay in PI ticks: TxDQS = 955, TxDQ = 919
ACCM: 00 00000000 00000000
ACCM: 0F 0F0F0F0F 0F0F0F0F
N3.C1.D0.R0.S14: TxDq : plus1 = 1, minus1 = 0, PI = 04, DB = 1
N5.C2.D0.R0.S13: Total Delay in PI ticks: TxDQS = 912, TxDQ = 879
ACCM: 00 00000000 00000000
ACCM: 0F 0F0F0F0F 0F0F0F0F
N3.C1.D0.R0.S15: TxDqs: plus1 = 1, minus1 = 0, PI = 51, DB = 1
N5.C2.D0.R0.S14: Total Delay in PI ticks: TxDQS = 943, TxDQ = 909
N7.C1.D0.R1: CheckMCTest: result = 0x1FF
ACCM: 00 00000000 00000000
N3.C1.D0.R0.S15: TxDq : plus1 = 1, minus1 = 0, PI = 19, DB = 0
N5.C2.D0.R0.S15: Total Delay in PI ticks: TxDQS = 943, TxDQ = 909
ACCM: 0F 0F0F0F0F 0F0F0F0F
ACCM: 00 00000000 00000000
N3.C1.D0.R0.S16: TxDqs: plus1 = 1, minus1 = 0, PI = 06, DB = 1
N5.C2.D0.R0.S16: Total Delay in PI ticks: TxDQS = 963, TxDQ = 930
ACCM: 0F 0F0F0F0F 0F0F0F0F
N1.C1.D0.R1: CheckMCTest: result = 0x1FF
N3.C1.D0.R0.S16: TxDq : plus1 = 1, minus1 = 0, PI = 35, DB = 0
N5.C2.D0.R0.S17: Total Delay in PI ticks: TxDQS = 929, TxDQ = 895
ACCM: 00 00000000 00000000
N1.C1.D0.R1: CheckMCTest: passed
N3.C1.D0.R0.S17: TxDqs: plus1 = 1, minus1 = 0, PI = 36, DB = 0
N5.C2.D0.R1.S00: Total Delay in PI ticks: TxDQS = 995, TxDQ = 962
ACCM: 00 00000000 00000000
N1.C1.D0.R1: CheckMCTest: passed
N3.C1.D0.R0.S17: TxDq : plus1 = 1, minus1 = 0, PI = 05, DB = 1
N5.C2.D0.R1.S01: Total Delay in PI ticks: TxDQS = 983, TxDQ = 949
N7.C1.D0.R1: CheckMCTest: result = 0x1FF
N1.C1.D0.R1.S00: Offset Found: RdPtrOffsetDqs = 007
N3.C1.D0.R1.S00: TxDqs: plus1 = 1, minus1 = 0, PI = 35, DB = 0
N5.C2.D0.R1.S02: Total Delay in PI ticks: TxDQS = 971, TxDQ = 938
N7.C1.D0.R1: CheckMCTest: passed
N1.C1.D0.R1.S01: Offset Found: RdPtrOffsetDqs = 007
N3.C1.D0.R1.S00: TxDq : plus1 = 1, minus1 = 0, PI = 04, DB = 1
N5.C2.D0.R1.S03: Total Delay in PI ticks: TxDQS = 954, TxDQ = 920
N7.C1.D0.R1: CheckMCTest: passed
N1.C1.D0.R1.S02: Offset Found: RdPtrOffsetDqs = 007
N3.C1.D0.R1.S01: TxDqs: plus1 = 1, minus1 = 0, PI = 19, DB = 0
N5.C2.D0.R1.S04: Total Delay in PI ticks: TxDQS = 912, TxDQ = 878
N7.C1.D0.R1.S00: Offset Found: RdPtrOffsetDqs = 007
N1.C1.D0.R1.S03: Offset Found: RdPtrOffsetDqs = 006
N3.C1.D0.R1.S01: TxDq : plus1 = 1, minus1 = 0, PI = 51, DB = 1
N5.C2.D0.R1.S05: Total Delay in PI ticks: TxDQS = 943, TxDQ = 906
N7.C1.D0.R1.S01: Offset Found: RdPtrOffsetDqs = 007
N1.C1.D0.R1.S04: Offset Found: RdPtrOffsetDqs = 006
N3.C1.D0.R1.S02: TxDqs: plus1 = 1, minus1 = 0, PI = 12, DB = 1
N5.C2.D0.R1.S06: Total Delay in PI ticks: TxDQS = 942, TxDQ = 909
N7.C1.D0.R1.S02: Offset Found: RdPtrOffsetDqs = 007
N1.C1.D0.R1.S05: Offset Found: RdPtrOffsetDqs = 006
N3.C1.D0.R1.S02: TxDq : plus1 = 1, minus1 = 0, PI = 42, DB = 0
N5.C2.D0.R1.S07: Total Delay in PI ticks: TxDQS = 964, TxDQ = 930
N7.C1.D0.R1.S03: Offset Found: RdPtrOffsetDqs = 007
N1.C1.D0.R1.S06: Offset Found: RdPtrOffsetDqs = 006
N3.C1.D0.R1.S03: TxDqs: plus1 = 1, minus1 = 0, PI = 57, DB = 1
N5.C2.D0.R1.S08: Total Delay in PI ticks: TxDQS = 929, TxDQ = 895
N7.C1.D0.R1.S04: Offset Found: RdPtrOffsetDqs = 006
N1.C1.D0.R1.S07: Offset Found: RdPtrOffsetDqs = 007
N3.C1.D0.R1.S03: TxDq : plus1 = 1, minus1 = 0, PI = 24, DB = 0
N5.C2.D0.R1.S09: Total Delay in PI ticks: TxDQS = 995, TxDQ = 960
N7.C1.D0.R1.S05: Offset Found: RdPtrOffsetDqs = 006
N1.C1.D0.R1.S08: Offset Found: RdPtrOffsetDqs = 006
N3.C1.D0.R1.S04: TxDqs: plus1 = 1, minus1 = 0, PI = 26, DB = 0
N5.C2.D0.R1.S10: Total Delay in PI ticks: TxDQS = 983, TxDQ = 951
N7.C1.D0.R1.S06: Offset Found: RdPtrOffsetDqs = 006
N1.C1.D0.R1: Write Training Coarse, upper nibbles
N3.C1.D0.R1.S04: TxDq : plus1 = 1, minus1 = 0, PI = 56, DB = 1
N5.C2.D0.R1.S11: Total Delay in PI ticks: TxDQS = 974, TxDQ = 939
N7.C1.D0.R1.S07: Offset Found: RdPtrOffsetDqs = 007
N1.C1.D0.R1.S09: Dq Delay estimate: 449
N3.C1.D0.R1.S05: TxDqs: plus1 = 1, minus1 = 0, PI = 40, DB = 0
N5.C2.D0.R1.S12: Total Delay in PI ticks: TxDQS = 957, TxDQ = 921
N7.C1.D0.R1.S08: Offset Found: RdPtrOffsetDqs = 006
N1.C1.D0.R1.S10: Dq Delay estimate: 435
N3.C1.D0.R1.S05: TxDq : plus1 = 1, minus1 = 0, PI = 05, DB = 1
N5.C2.D0.R1.S13: Total Delay in PI ticks: TxDQS = 912, TxDQ = 879
N7.C1.D0.R1: Write Training Coarse, upper nibbles
N1.C1.D0.R1.S11: Dq Delay estimate: 425
N3.C1.D0.R1.S06: TxDqs: plus1 = 1, minus1 = 0, PI = 52, DB = 1
N5.C2.D0.R1.S14: Total Delay in PI ticks: TxDQS = 943, TxDQ = 909
N7.C1.D0.R1.S09: Dq Delay estimate: 455
N1.C1.D0.R1.S12: Dq Delay estimate: 409
N3.C1.D0.R1.S06: TxDq : plus1 = 1, minus1 = 0, PI = 18, DB = 0
N5.C2.D0.R1.S15: Total Delay in PI ticks: TxDQS = 943, TxDQ = 909
N7.C1.D0.R1.S10: Dq Delay estimate: 441
N1.C1.D0.R1.S13: Dq Delay estimate: 381
N3.C1.D0.R1.S07: TxDqs: plus1 = 1, minus1 = 0, PI = 07, DB = 1
N5.C2.D0.R1.S16: Total Delay in PI ticks: TxDQS = 966, TxDQ = 933
N7.C1.D0.R1.S11: Dq Delay estimate: 433
N1.C1.D0.R1.S14: Dq Delay estimate: 390
N3.C1.D0.R1.S07: TxDq : plus1 = 1, minus1 = 0, PI = 37, DB = 0
N5.C2.D0.R1.S17: Total Delay in PI ticks: TxDQS = 929, TxDQ = 894
N7.C1.D0.R1.S12: Dq Delay estimate: 414
N1.C1.D0.R1.S15: Dq Delay estimate: 403
N3.C1.D0.R1.S08: TxDqs: plus1 = 1, minus1 = 0, PI = 37, DB = 0
N5.C3.D0.R0: Write Training Coarse, lower nibbles / bytes
N7.C1.D0.R1.S13: Dq Delay estimate: 382
N1.C1.D0.R1.S16: Dq Delay estimate: 421
N3.C1.D0.R1.S08: TxDq : plus1 = 1, minus1 = 0, PI = 03, DB = 1
N5.C3.D0.R0.S00: Dq Delay estimate: 456
N7.C1.D0.R1.S14: Dq Delay estimate: 397
N1.C1.D0.R1.S17: Dq Delay estimate: 389
N3.C1.D0.R1.S09: TxDqs: plus1 = 1, minus1 = 0, PI = 34, DB = 0
N5.C3.D0.R0.S01: Dq Delay estimate: 442
N7.C1.D0.R1.S15: Dq Delay estimate: 408
ACCM: F0 F0F0F0F0 F0F0F0F0
N3.C1.D0.R1.S09: TxDq : plus1 = 1, minus1 = 0, PI = 02, DB = 1
N5.C3.D0.R0.S02: Dq Delay estimate: 427
N7.C1.D0.R1.S16: Dq Delay estimate: 426
ACCM: F0 F0F0F0F0 F0F0F0F0
N3.C1.D0.R1.S10: TxDqs: plus1 = 1, minus1 = 0, PI = 21, DB = 0
N5.C3.D0.R0.S03: Dq Delay estimate: 413
N7.C1.D0.R1.S17: Dq Delay estimate: 395
ACCM: F0 F0F0F0F0 F0F0F0F0
N3.C1.D0.R1.S10: TxDq : plus1 = 1, minus1 = 0, PI = 52, DB = 1
N5.C3.D0.R0.S04: Dq Delay estimate: 375
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: F0 F0F0F0F0 F0F0F0F0
N3.C1.D0.R1.S11: TxDqs: plus1 = 1, minus1 = 0, PI = 12, DB = 1
N5.C3.D0.R0.S05: Dq Delay estimate: 392
ACCM: F0 F0F0F0F0 F0F0F0F0
N1.C1.D0.R1: CheckMCTest: result = 0x3FE00
N3.C1.D0.R1.S11: TxDq : plus1 = 1, minus1 = 0, PI = 44, DB = 0
N5.C3.D0.R0.S06: Dq Delay estimate: 406
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: F0 F0F0F0F0 F0F0F0F0
N3.C1.D0.R1.S12: TxDqs: plus1 = 1, minus1 = 0, PI = 58, DB = 1
N5.C3.D0.R0.S07: Dq Delay estimate: 422
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: F0 F0F0F0F0 F0F0F0F0
N3.C1.D0.R1.S12: TxDq : plus1 = 1, minus1 = 0, PI = 23, DB = 0
N5.C3.D0.R0.S08: Dq Delay estimate: 394
N7.C1.D0.R1: CheckMCTest: result = 0x3FE00
ACCM: F0 F0F0F0F0 F0F0F0F0
N3.C1.D0.R1.S13: TxDqs: plus1 = 1, minus1 = 0, PI = 25, DB = 0
ACCM: 0F 0F9F9F0F DF0F0F0F
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: F0 F0F0F0F0 F0F0F0F0
N3.C1.D0.R1.S13: TxDq : plus1 = 1, minus1 = 0, PI = 55, DB = 1
ACCM: 0F 0F9F9F0F DF0F0F0F
ACCM: F0 F0F0F0F0 F0F0F0F0
N1.C1.D0.R1: CheckMCTest: result = 0x3FE00
N3.C1.D0.R1.S14: TxDqs: plus1 = 1, minus1 = 0, PI = 38, DB = 0
ACCM: 0F FF9F9F0F FFFFFFFF
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: F0 F0F0F0F0 F0F0F0F0
N3.C1.D0.R1.S14: TxDq : plus1 = 1, minus1 = 0, PI = 04, DB = 1
ACCM: 0F FF9F9F0F FFFFFFFF
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: F0 F0F0F0F0 F0F0F0F0
N3.C1.D0.R1.S15: TxDqs: plus1 = 1, minus1 = 0, PI = 51, DB = 1
N5.C3.D0.R0: CheckMCTest: result = 0x1DFFF
N7.C1.D0.R1: CheckMCTest: result = 0x3FE00
ACCM: B0 00000000 00000000
N3.C1.D0.R1.S15: TxDq : plus1 = 1, minus1 = 0, PI = 19, DB = 0
ACCM: 0F 0FDFDF0F DF0F0F0F
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: B0 00000000 00000000
N3.C1.D0.R1.S16: TxDqs: plus1 = 1, minus1 = 0, PI = 06, DB = 1
ACCM: 0F 0FDFDF0F DF0F0F0F
ACCM: F0 F0F0F0F0 F0F0F0F0
N1.C1.D0.R1: CheckMCTest: result = 0x3FE00
N3.C1.D0.R1.S16: TxDq : plus1 = 1, minus1 = 0, PI = 35, DB = 0
ACCM: 0F FFDFDF0F FFFFFFFF
ACCM: 00 00000000 00000000
ACCM: F0 F0F0F0F0 F0F0F0F0
N3.C1.D0.R1.S17: TxDqs: plus1 = 1, minus1 = 0, PI = 36, DB = 0
ACCM: 0F FFDFDF0F FFFFFFFF
ACCM: 00 00000000 00000000
ACCM: F0 F0F0F0F0 F0F0F0F0
N3.C1.D0.R1.S17: TxDq : plus1 = 1, minus1 = 0, PI = 05, DB = 1
N5.C3.D0.R0: CheckMCTest: result = 0x1DFFF
N7.C1.D0.R1: CheckMCTest: result = 0x3FE00
ACCM: F0 00000000 00000000
END_DATA_TX_DQ
ACCM: 0F 0FDFDF0F 0F0F0F0F
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: F0 00000000 00000000
N3.C2.D0.R0.S00: wrcmd2dqsstartlatency: 04
ACCM: 0F 0FDFDF0F 0F0F0F0F
ACCM: F0 F0F0F0F0 F0F0F0F0
N1.C1.D0.R1: CheckMCTest: result = 0x3FE00
N3.C2.D0.R0.S00: RdPtrOffsetTxDq: 05
ACCM: 00 F0D0D000 F0F0F0F0
ACCM: 00 00000000 00000000
N1.C1.D0.R1: CheckMCTest: passed
N3.C2.D0.R0.S00: RdPtrOffsetTxDqs: 07
ACCM: 00 F0D0D000 F0F0F0F0
ACCM: 00 00000000 00000000
N1.C1.D0.R1: CheckMCTest: passed
N3.C2.D0.R0.S00: PiTxDqs: 29
N5.C3.D0.R0: CheckMCTest: result = 0x1DFFF
N7.C1.D0.R1: CheckMCTest: result = 0x3FE00
N1.C1.D0.R1.S09: Offset Found: RdPtrOffsetDqs = 007
N3.C2.D0.R0.S01: wrcmd2dqsstartlatency: 04
ACCM: 0F 0FDFDF0F 0F0F0F0F
N7.C1.D0.R1: CheckMCTest: passed
N1.C1.D0.R1.S10: Offset Found: RdPtrOffsetDqs = 007
N3.C2.D0.R0.S01: RdPtrOffsetTxDq: 05
ACCM: 0F 0FDFDF0F 0F0F0F0F
N7.C1.D0.R1: CheckMCTest: passed
N1.C1.D0.R1.S11: Offset Found: RdPtrOffsetDqs = 007
N3.C2.D0.R0.S01: RdPtrOffsetTxDqs: 07
ACCM: 00 F0D0D000 F0F0F0F0
N7.C1.D0.R1.S09: Offset Found: RdPtrOffsetDqs = 007
N1.C1.D0.R1.S12: Offset Found: RdPtrOffsetDqs = 006
N3.C2.D0.R0.S01: PiTxDqs: 12
ACCM: 00 F0D0D000 F0F0F0F0
N7.C1.D0.R1.S10: Offset Found: RdPtrOffsetDqs = 007
N1.C1.D0.R1.S13: Offset Found: RdPtrOffsetDqs = 006
N3.C2.D0.R0.S02: wrcmd2dqsstartlatency: 04
N5.C3.D0.R0: CheckMCTest: result = 0x1DFFF
N7.C1.D0.R1.S11: Offset Found: RdPtrOffsetDqs = 007
N1.C1.D0.R1.S14: Offset Found: RdPtrOffsetDqs = 006
N3.C2.D0.R0.S02: RdPtrOffsetTxDq: 05
ACCM: 00 00D0D000 00000000
N7.C1.D0.R1.S12: Offset Found: RdPtrOffsetDqs = 007
N1.C1.D0.R1.S15: Offset Found: RdPtrOffsetDqs = 006
N3.C2.D0.R0.S02: RdPtrOffsetTxDqs: 07
ACCM: 00 00D0D000 00000000
N7.C1.D0.R1.S13: Offset Found: RdPtrOffsetDqs = 006
N1.C1.D0.R1.S16: Offset Found: RdPtrOffsetDqs = 007
N3.C2.D0.R0.S02: PiTxDqs: 01
ACCM: 00 F0D0D000 F0F0F0F0
N7.C1.D0.R1.S14: Offset Found: RdPtrOffsetDqs = 006
N1.C1.D0.R1.S17: Offset Found: RdPtrOffsetDqs = 006
N3.C2.D0.R0.S03: wrcmd2dqsstartlatency: 04
ACCM: 00 F0D0D000 F0F0F0F0
N7.C1.D0.R1.S15: Offset Found: RdPtrOffsetDqs = 006
N1.C1: Calculating Optimimum DQS Values
N3.C2.D0.R0.S03: RdPtrOffsetTxDq: 05
N5.C3.D0.R0: CheckMCTest: result = 0x1DE00
N7.C1.D0.R1.S16: Offset Found: RdPtrOffsetDqs = 007
N1.C1.D0.R0.S00: Total Delay in PI ticks: TxDQS = 999, TxDQ = 965
N3.C2.D0.R0.S03: RdPtrOffsetTxDqs: 06
ACCM: 00 00D0D000 D0000000
N7.C1.D0.R1.S17: Offset Found: RdPtrOffsetDqs = 006
N1.C1.D0.R0.S01: Total Delay in PI ticks: TxDQS = 983, TxDQ = 950
N3.C2.D0.R0.S03: PiTxDqs: 47
ACCM: 00 00D0D000 D0000000
N7.C1: Calculating Optimimum DQS Values
N1.C1.D0.R0.S02: Total Delay in PI ticks: TxDQS = 972, TxDQ = 939
N3.C2.D0.R0.S04: wrcmd2dqsstartlatency: 04
ACCM: 00 F0D0D000 F0F0F0F0
N7.C1.D0.R0.S00: Total Delay in PI ticks: TxDQS = 1004, TxDQ = 971
N1.C1.D0.R0.S03: Total Delay in PI ticks: TxDQS = 956, TxDQ = 923
N3.C2.D0.R0.S04: RdPtrOffsetTxDq: 04
ACCM: 00 F0D0D000 F0F0F0F0
N7.C1.D0.R0.S01: Total Delay in PI ticks: TxDQS = 987, TxDQ = 952
N1.C1.D0.R0.S04: Total Delay in PI ticks: TxDQS = 923, TxDQ = 889
N3.C2.D0.R0.S04: RdPtrOffsetTxDqs: 06
N5.C3.D0.R0: CheckMCTest: result = 0x1DE00
N7.C1.D0.R0.S02: Total Delay in PI ticks: TxDQS = 979, TxDQ = 946
N1.C1.D0.R0.S05: Total Delay in PI ticks: TxDQS = 936, TxDQ = 902
N3.C2.D0.R0.S04: PiTxDqs: 09
N5.C3.D0.R0.S00: Offset Found: RdPtrOffsetDqs = 007
N7.C1.D0.R0.S03: Total Delay in PI ticks: TxDQS = 961, TxDQ = 927
N1.C1.D0.R0.S06: Total Delay in PI ticks: TxDQS = 949, TxDQ = 916
N3.C2.D0.R0.S05: wrcmd2dqsstartlatency: 04
N5.C3.D0.R0.S01: Offset Found: RdPtrOffsetDqs = 007
N7.C1.D0.R0.S04: Total Delay in PI ticks: TxDQS = 928, TxDQ = 895
N1.C1.D0.R0.S07: Total Delay in PI ticks: TxDQS = 965, TxDQ = 931
N3.C2.D0.R0.S05: RdPtrOffsetTxDq: 05
N5.C3.D0.R0.S02: Offset Found: RdPtrOffsetDqs = 007
N7.C1.D0.R0.S05: Total Delay in PI ticks: TxDQS = 942, TxDQ = 909
N1.C1.D0.R0.S08: Total Delay in PI ticks: TxDQS = 934, TxDQ = 900
N3.C2.D0.R0.S05: RdPtrOffsetTxDqs: 06
N5.C3.D0.R0.S03: Offset Found: RdPtrOffsetDqs = 006
N7.C1.D0.R0.S06: Total Delay in PI ticks: TxDQS = 955, TxDQ = 921
N1.C1.D0.R0.S09: Total Delay in PI ticks: TxDQS = 1001, TxDQ = 965
N3.C2.D0.R0.S05: PiTxDqs: 37
N5.C3.D0.R0.S04: Offset Found: RdPtrOffsetDqs = 006
N7.C1.D0.R0.S07: Total Delay in PI ticks: TxDQS = 975, TxDQ = 942
N1.C1.D0.R0.S10: Total Delay in PI ticks: TxDQS = 983, TxDQ = 950
N3.C2.D0.R0.S06: wrcmd2dqsstartlatency: 04
N5.C3.D0.R0.S05: Offset Found: RdPtrOffsetDqs = 006
N7.C1.D0.R0.S08: Total Delay in PI ticks: TxDQS = 941, TxDQ = 908
N1.C1.D0.R0.S11: Total Delay in PI ticks: TxDQS = 972, TxDQ = 938
N3.C2.D0.R0.S06: RdPtrOffsetTxDq: 05
N5.C3.D0.R0.S06: Offset Found: RdPtrOffsetDqs = 006
N7.C1.D0.R0.S09: Total Delay in PI ticks: TxDQS = 1002, TxDQ = 968
N1.C1.D0.R0.S12: Total Delay in PI ticks: TxDQS = 957, TxDQ = 924
N3.C2.D0.R0.S06: RdPtrOffsetTxDqs: 06
N5.C3.D0.R0.S07: Offset Found: RdPtrOffsetDqs = 007
N7.C1.D0.R0.S10: Total Delay in PI ticks: TxDQS = 989, TxDQ = 954
N1.C1.D0.R0.S13: Total Delay in PI ticks: TxDQS = 923, TxDQ = 893
N3.C2.D0.R0.S06: PiTxDqs: 38
N5.C3.D0.R0.S08: Offset Found: RdPtrOffsetDqs = 006
N7.C1.D0.R0.S11: Total Delay in PI ticks: TxDQS = 978, TxDQ = 947
N1.C1.D0.R0.S14: Total Delay in PI ticks: TxDQS = 936, TxDQ = 901
N3.C2.D0.R0.S07: wrcmd2dqsstartlatency: 04
N5.C3.D0.R0: Write Training Coarse, upper nibbles
N7.C1.D0.R0.S12: Total Delay in PI ticks: TxDQS = 960, TxDQ = 928
N1.C1.D0.R0.S15: Total Delay in PI ticks: TxDQS = 949, TxDQ = 916
N3.C2.D0.R0.S07: RdPtrOffsetTxDq: 05
N5.C3.D0.R0.S09: Dq Delay estimate: 455
N7.C1.D0.R0.S13: Total Delay in PI ticks: TxDQS = 927, TxDQ = 893
N1.C1.D0.R0.S16: Total Delay in PI ticks: TxDQS = 967, TxDQ = 932
N3.C2.D0.R0.S07: RdPtrOffsetTxDqs: 06
N5.C3.D0.R0.S10: Dq Delay estimate: 444
N7.C1.D0.R0.S14: Total Delay in PI ticks: TxDQS = 942, TxDQ = 909
N1.C1.D0.R0.S17: Total Delay in PI ticks: TxDQS = 935, TxDQ = 904
N3.C2.D0.R0.S07: PiTxDqs: 58
N5.C3.D0.R0.S11: Dq Delay estimate: 430
N7.C1.D0.R0.S15: Total Delay in PI ticks: TxDQS = 954, TxDQ = 920
N1.C1.D0.R1.S00: Total Delay in PI ticks: TxDQS = 1000, TxDQ = 965
N3.C2.D0.R0.S08: wrcmd2dqsstartlatency: 04
N5.C3.D0.R0.S12: Dq Delay estimate: 413
N7.C1.D0.R0.S16: Total Delay in PI ticks: TxDQS = 973, TxDQ = 939
N1.C1.D0.R1.S01: Total Delay in PI ticks: TxDQS = 981, TxDQ = 947
N3.C2.D0.R0.S08: RdPtrOffsetTxDq: 04
N5.C3.D0.R0.S13: Dq Delay estimate: 378
N7.C1.D0.R0.S17: Total Delay in PI ticks: TxDQS = 939, TxDQ = 907
N1.C1.D0.R1.S02: Total Delay in PI ticks: TxDQS = 971, TxDQ = 938
N3.C2.D0.R0.S08: RdPtrOffsetTxDqs: 06
N5.C3.D0.R0.S14: Dq Delay estimate: 393
N7.C1.D0.R1.S00: Total Delay in PI ticks: TxDQS = 1005, TxDQ = 972
N1.C1.D0.R1.S03: Total Delay in PI ticks: TxDQS = 955, TxDQ = 921
N3.C2.D0.R0.S08: PiTxDqs: 24
N5.C3.D0.R0.S15: Dq Delay estimate: 407
N7.C1.D0.R1.S01: Total Delay in PI ticks: TxDQS = 986, TxDQ = 951
N1.C1.D0.R1.S04: Total Delay in PI ticks: TxDQS = 923, TxDQ = 890
N3.C2.D0.R0.S09: wrcmd2dqsstartlatency: 04
N5.C3.D0.R0.S16: Dq Delay estimate: 424
N7.C1.D0.R1.S02: Total Delay in PI ticks: TxDQS = 977, TxDQ = 944
N1.C1.D0.R1.S05: Total Delay in PI ticks: TxDQS = 936, TxDQ = 902
N3.C2.D0.R0.S09: RdPtrOffsetTxDq: 05
N5.C3.D0.R0.S17: Dq Delay estimate: 393
N7.C1.D0.R1.S03: Total Delay in PI ticks: TxDQS = 960, TxDQ = 926
N1.C1.D0.R1.S06: Total Delay in PI ticks: TxDQS = 948, TxDQ = 915
N3.C2.D0.R0.S09: RdPtrOffsetTxDqs: 07
ACCM: F0 F0F0F0F0 F0F0F0F0
N7.C1.D0.R1.S04: Total Delay in PI ticks: TxDQS = 929, TxDQ = 896
N1.C1.D0.R1.S07: Total Delay in PI ticks: TxDQS = 966, TxDQ = 932
N3.C2.D0.R0.S09: PiTxDqs: 26
ACCM: F0 F0F0F0F0 F0F0F0F0
N7.C1.D0.R1.S05: Total Delay in PI ticks: TxDQS = 941, TxDQ = 908
N1.C1.D0.R1.S08: Total Delay in PI ticks: TxDQS = 932, TxDQ = 900
N3.C2.D0.R0.S10: wrcmd2dqsstartlatency: 04
ACCM: F0 F0F0F0F0 F0F0F0F0
N7.C1.D0.R1.S06: Total Delay in PI ticks: TxDQS = 955, TxDQ = 921
N1.C1.D0.R1.S09: Total Delay in PI ticks: TxDQS = 997, TxDQ = 961
N3.C2.D0.R0.S10: RdPtrOffsetTxDq: 05
ACCM: F0 F0F0F0F0 F0F0F0F0
N7.C1.D0.R1.S07: Total Delay in PI ticks: TxDQS = 972, TxDQ = 939
N1.C1.D0.R1.S10: Total Delay in PI ticks: TxDQS = 981, TxDQ = 947
N3.C2.D0.R0.S10: RdPtrOffsetTxDqs: 07
N5.C3.D0.R0: CheckMCTest: result = 0x3FE00
N7.C1.D0.R1.S08: Total Delay in PI ticks: TxDQS = 941, TxDQ = 909
N1.C1.D0.R1.S11: Total Delay in PI ticks: TxDQS = 971, TxDQ = 937
N3.C2.D0.R0.S10: PiTxDqs: 14
ACCM: F0 F0F0F0F0 F0F0F0F0
N7.C1.D0.R1.S09: Total Delay in PI ticks: TxDQS = 1001, TxDQ = 967
N1.C1.D0.R1.S12: Total Delay in PI ticks: TxDQS = 954, TxDQ = 921
N3.C2.D0.R0.S11: wrcmd2dqsstartlatency: 04
ACCM: F0 F0F0F0F0 F0F0F0F0
N7.C1.D0.R1.S10: Total Delay in PI ticks: TxDQS = 988, TxDQ = 953
N1.C1.D0.R1.S13: Total Delay in PI ticks: TxDQS = 924, TxDQ = 893
N3.C2.D0.R0.S11: RdPtrOffsetTxDq: 05
ACCM: F0 F0F0F0F0 F0F0F0F0
N7.C1.D0.R1.S11: Total Delay in PI ticks: TxDQS = 978, TxDQ = 945
N1.C1.D0.R1.S14: Total Delay in PI ticks: TxDQS = 936, TxDQ = 902
N3.C2.D0.R0.S11: RdPtrOffsetTxDqs: 07
ACCM: F0 F0F0F0F0 F0F0F0F0
N7.C1.D0.R1.S12: Total Delay in PI ticks: TxDQS = 960, TxDQ = 926
N1.C1.D0.R1.S15: Total Delay in PI ticks: TxDQS = 948, TxDQ = 915
N3.C2.D0.R0.S11: PiTxDqs: 05
N5.C3.D0.R0: CheckMCTest: result = 0x3FE00
N7.C1.D0.R1.S13: Total Delay in PI ticks: TxDQS = 928, TxDQ = 894
N1.C1.D0.R1.S16: Total Delay in PI ticks: TxDQS = 968, TxDQ = 933
N3.C2.D0.R0.S12: wrcmd2dqsstartlatency: 04
ACCM: F0 F0F0F0F0 F0F0F0F0
N7.C1.D0.R1.S14: Total Delay in PI ticks: TxDQS = 942, TxDQ = 909
N1.C1.D0.R1.S17: Total Delay in PI ticks: TxDQS = 933, TxDQ = 901
N3.C2.D0.R0.S12: RdPtrOffsetTxDq: 05
ACCM: F0 F0F0F0F0 F0F0F0F0
N7.C1.D0.R1.S15: Total Delay in PI ticks: TxDQS = 954, TxDQ = 920
N1.C2.D0.R0: Write Training Coarse, lower nibbles / bytes
N3.C2.D0.R0.S12: RdPtrOffsetTxDqs: 06
ACCM: 00 00000000 00000000
N7.C1.D0.R1.S16: Total Delay in PI ticks: TxDQS = 972, TxDQ = 938
N1.C2.D0.R0.S00: Dq Delay estimate: 448
N3.C2.D0.R0.S12: PiTxDqs: 49
ACCM: 00 00000000 00000000
N7.C1.D0.R1.S17: Total Delay in PI ticks: TxDQS = 939, TxDQ = 907
N1.C2.D0.R0.S01: Dq Delay estimate: 431
N3.C2.D0.R0.S13: wrcmd2dqsstartlatency: 04
N5.C3.D0.R0: CheckMCTest: result = 0x3FE00
N7.C2.D0.R0: Write Training Coarse, lower nibbles / bytes
N1.C2.D0.R0.S02: Dq Delay estimate: 418
N3.C2.D0.R0.S13: RdPtrOffsetTxDq: 04
ACCM: F0 F0F0F0F0 F0F0F0F0
N7.C2.D0.R0.S00: Dq Delay estimate: 444
N1.C2.D0.R0.S03: Dq Delay estimate: 404
N3.C2.D0.R0.S13: RdPtrOffsetTxDqs: 06
ACCM: F0 F0F0F0F0 F0F0F0F0
N7.C2.D0.R0.S01: Dq Delay estimate: 428
N1.C2.D0.R0.S04: Dq Delay estimate: 366
N3.C2.D0.R0.S13: PiTxDqs: 08
ACCM: 00 00000000 00000000
N7.C2.D0.R0.S02: Dq Delay estimate: 418
N1.C2.D0.R0.S05: Dq Delay estimate: 391
N3.C2.D0.R0.S14: wrcmd2dqsstartlatency: 04
ACCM: 00 00000000 00000000
N7.C2.D0.R0.S03: Dq Delay estimate: 401
N1.C2.D0.R0.S06: Dq Delay estimate: 388
N3.C2.D0.R0.S14: RdPtrOffsetTxDq: 05
N5.C3.D0.R0: CheckMCTest: result = 0x3FE00
N7.C2.D0.R0.S04: Dq Delay estimate: 358
N1.C2.D0.R0.S07: Dq Delay estimate: 412
N3.C2.D0.R0.S14: RdPtrOffsetTxDqs: 06
N5.C3.D0.R0: CheckMCTest: passed
N7.C2.D0.R0.S05: Dq Delay estimate: 387
N1.C2.D0.R0.S08: Dq Delay estimate: 379
N3.C2.D0.R0.S14: PiTxDqs: 37
N5.C3.D0.R0: CheckMCTest: passed
N7.C2.D0.R0.S06: Dq Delay estimate: 387
ACCM: 9F 0F9F0F0F 9F0F0F0F
N3.C2.D0.R0.S15: wrcmd2dqsstartlatency: 04
N5.C3.D0.R0.S09: Offset Found: RdPtrOffsetDqs = 007
N7.C2.D0.R0.S07: Dq Delay estimate: 413
ACCM: 9F 0F9F0F0F 9F0F0F0F
N3.C2.D0.R0.S15: RdPtrOffsetTxDq: 05
N5.C3.D0.R0.S10: Offset Found: RdPtrOffsetDqs = 007
N7.C2.D0.R0.S08: Dq Delay estimate: 373
ACCM: 9F FF9F0F0F 9FFFFFFF
N3.C2.D0.R0.S15: RdPtrOffsetTxDqs: 06
N5.C3.D0.R0.S11: Offset Found: RdPtrOffsetDqs = 007
ACCM: 0F 9F0F0F0F 9F0F0F0F
ACCM: 9F FF9F0F0F 9FFFFFFF
N3.C2.D0.R0.S15: PiTxDqs: 38
N5.C3.D0.R0.S12: Offset Found: RdPtrOffsetDqs = 006
ACCM: 0F 9F0F0F0F 9F0F0F0F
N1.C2.D0.R0: CheckMCTest: result = 0x39FFF
N3.C2.D0.R0.S16: wrcmd2dqsstartlatency: 04
N5.C3.D0.R0.S13: Offset Found: RdPtrOffsetDqs = 006
ACCM: 0F 9F0F0F0F 9FFFFFFF
ACCM: DF 0FDF0F0F DF0F0F0F
N3.C2.D0.R0.S16: RdPtrOffsetTxDq: 05
N5.C3.D0.R0.S14: Offset Found: RdPtrOffsetDqs = 006
ACCM: 0F 9F0F0F0F 9FFFFFFF
ACCM: DF 0FDF0F0F DF0F0F0F
N3.C2.D0.R0.S16: RdPtrOffsetTxDqs: 06
N5.C3.D0.R0.S15: Offset Found: RdPtrOffsetDqs = 006
N7.C2.D0.R0: CheckMCTest: result = 0x11FFF
ACCM: DF FFDF0F0F DFFFFFFF
N3.C2.D0.R0.S16: PiTxDqs: 60
N5.C3.D0.R0.S16: Offset Found: RdPtrOffsetDqs = 007
ACCM: 0F FF0F0F0F DF0F0F0F
ACCM: DF FFDF0F0F DFFFFFFF
N3.C2.D0.R0.S17: wrcmd2dqsstartlatency: 04
N5.C3.D0.R0.S17: Offset Found: RdPtrOffsetDqs = 006
ACCM: 0F FF0F0F0F DF0F0F0F
N1.C2.D0.R0: CheckMCTest: result = 0x39FFF
N3.C2.D0.R0.S17: RdPtrOffsetTxDq: 04
N5.C3.D0.R1: Write Training Coarse, lower nibbles / bytes
ACCM: 0F FF0F0F0F DFFFFFFF
ACCM: DF 0FDF0F0F DF0F0F0F
N3.C2.D0.R0.S17: RdPtrOffsetTxDqs: 06
N5.C3.D0.R1.S00: Dq Delay estimate: 457
ACCM: 0F FF0F0F0F DFFFFFFF
ACCM: DF 0FDF0F0F DF0F0F0F
N3.C2.D0.R0.S17: PiTxDqs: 24
N5.C3.D0.R1.S01: Dq Delay estimate: 441
N7.C2.D0.R0: CheckMCTest: result = 0x11FFF
ACCM: D0 F0D00000 D0F0F0FB
N3.C2.D0.R0.S00: RdPtrOffsetTxDq: 06
N5.C3.D0.R1.S02: Dq Delay estimate: 429
ACCM: 0F DF0F0F0F DF0F0F0F
ACCM: D0 F0D00000 D0F0F0FB
N3.C2.D0.R0.S01: RdPtrOffsetTxDq: 06
N5.C3.D0.R1.S03: Dq Delay estimate: 411
ACCM: 0F DF0F0F0F DF0F0F0F
N1.C2.D0.R0: CheckMCTest: result = 0x39FFF
N3.C2.D0.R0.S02: RdPtrOffsetTxDq: 06
N5.C3.D0.R1.S04: Dq Delay estimate: 376
ACCM: 00 D0000000 D0F0F0F0
ACCM: DF 0FDF0F0F DF0F0F0F
N3.C2.D0.R0.S03: RdPtrOffsetTxDq: 06
N5.C3.D0.R1.S05: Dq Delay estimate: 392
ACCM: 00 D0000000 D0F0F0F0
ACCM: DF 0FDF0F0F DF0F0F0F
N3.C2.D0.R0.S04: RdPtrOffsetTxDq: 05
N5.C3.D0.R1.S06: Dq Delay estimate: 406
N7.C2.D0.R0: CheckMCTest: result = 0x11FFF
ACCM: D0 F0D00000 D0F0F0FF
N3.C2.D0.R0.S05: RdPtrOffsetTxDq: 06
N5.C3.D0.R1.S07: Dq Delay estimate: 422
ACCM: 0F FF0F0F0F DF0F0F0F
ACCM: D0 F0D00000 D0F0F0FF
N3.C2.D0.R0.S06: RdPtrOffsetTxDq: 06
N5.C3.D0.R1.S08: Dq Delay estimate: 394
ACCM: 0F FF0F0F0F DF0F0F0F
N1.C2.D0.R0: CheckMCTest: result = 0x39FFF
N3.C2.D0.R0.S07: RdPtrOffsetTxDq: 06
ACCM: 0F 0F0F0F0F 0F0F0F0F
ACCM: 00 F0000000 D0F0F0F0
ACCM: 00 00D00000 D0000000
N3.C2.D0.R0.S08: RdPtrOffsetTxDq: 05
ACCM: 0F 0F0F0F0F 0F0F0F0F
ACCM: 00 F0000000 D0F0F0F0
ACCM: 00 00D00000 D0000000
N3.C2.D0.R0.S09: RdPtrOffsetTxDq: 06
ACCM: 0F 0F0F0F0F 0F0F0F0F
N7.C2.D0.R0: CheckMCTest: result = 0x11FFF
ACCM: 00 F0D00000 D0F0F0F0
N3.C2.D0.R0.S10: RdPtrOffsetTxDq: 06
ACCM: 0F 0F0F0F0F 0F0F0F0F
ACCM: 00 F0000000 D0000000
ACCM: 00 F0D00000 D0F0F0F0
N3.C2.D0.R0.S11: RdPtrOffsetTxDq: 06
N5.C3.D0.R1: CheckMCTest: result = 0x1FF
ACCM: 00 F0000000 D0000000
N1.C2.D0.R0: CheckMCTest: result = 0x19E00
N3.C2.D0.R0.S12: RdPtrOffsetTxDq: 06
ACCM: 0F 0F0F0F0F 0F0F0F0F
ACCM: 00 F0000000 D0F0F0F0
ACCM: 00 00D00000 D0000000
N3.C2.D0.R0.S13: RdPtrOffsetTxDq: 05
ACCM: 0F 0F0F0F0F 0F0F0F0F
ACCM: 00 F0000000 D0F0F0F0
ACCM: 00 00D00000 D0000000
N3.C2.D0.R0.S14: RdPtrOffsetTxDq: 06
ACCM: 0F 0F0F0F0F 0F0F0F0F
N7.C2.D0.R0: CheckMCTest: result = 0x11E00
ACCM: 00 F0D00000 D0F0F0F0
N3.C2.D0.R0.S15: RdPtrOffsetTxDq: 06
ACCM: 0F 0F0F0F0F 0F0F0F0F
ACCM: 00 F0000000 D0000000
ACCM: 00 F0D00000 D0F0F0F0
N3.C2.D0.R0.S16: RdPtrOffsetTxDq: 06
N5.C3.D0.R1: CheckMCTest: result = 0x1FF
ACCM: 00 F0000000 D0000000
N1.C2.D0.R0: CheckMCTest: result = 0x19E00
N3.C2.D0.R0.S17: RdPtrOffsetTxDq: 05
ACCM: 0F 0F0F0F0F 0F0F0F0F
ACCM: 00 F0000000 D0F0F0F0
N1.C2.D0.R0.S00: Offset Found: RdPtrOffsetDqs = 007
N3.C2.D0.R0.S00: RdPtrOffsetTxDq: 07
ACCM: 0F 0F0F0F0F 0F0F0F0F
ACCM: 00 F0000000 D0F0F0F0
N1.C2.D0.R0.S01: Offset Found: RdPtrOffsetDqs = 007
N3.C2.D0.R0.S01: RdPtrOffsetTxDq: 07
ACCM: 00 00000000 00000000
N7.C2.D0.R0: CheckMCTest: result = 0x11E00
N1.C2.D0.R0.S02: Offset Found: RdPtrOffsetDqs = 007
N3.C2.D0.R0.S02: RdPtrOffsetTxDq: 07
ACCM: 00 00000000 00000000
N7.C2.D0.R0.S00: Offset Found: RdPtrOffsetDqs = 007
N1.C2.D0.R0.S03: Offset Found: RdPtrOffsetDqs = 006
N3.C2.D0.R0.S03: RdPtrOffsetTxDq: 07
N5.C3.D0.R1: CheckMCTest: result = 0x1FF
N7.C2.D0.R0.S01: Offset Found: RdPtrOffsetDqs = 007
N1.C2.D0.R0.S04: Offset Found: RdPtrOffsetDqs = 006
N3.C2.D0.R0.S04: RdPtrOffsetTxDq: 06
ACCM: 0F 0F0F0F0F 0F0F0F0F
N7.C2.D0.R0.S02: Offset Found: RdPtrOffsetDqs = 007
N1.C2.D0.R0.S05: Offset Found: RdPtrOffsetDqs = 006
N3.C2.D0.R0.S05: RdPtrOffsetTxDq: 07
ACCM: 0F 0F0F0F0F 0F0F0F0F
N7.C2.D0.R0.S03: Offset Found: RdPtrOffsetDqs = 006
N1.C2.D0.R0.S06: Offset Found: RdPtrOffsetDqs = 006
N3.C2.D0.R0.S06: RdPtrOffsetTxDq: 07
ACCM: 00 00000000 00000000
N7.C2.D0.R0.S04: Offset Found: RdPtrOffsetDqs = 006
N1.C2.D0.R0.S07: Offset Found: RdPtrOffsetDqs = 006
N3.C2.D0.R0.S07: RdPtrOffsetTxDq: 07
ACCM: 00 00000000 00000000
N7.C2.D0.R0.S05: Offset Found: RdPtrOffsetDqs = 006
N1.C2.D0.R0.S08: Offset Found: RdPtrOffsetDqs = 006
N3.C2.D0.R0.S08: RdPtrOffsetTxDq: 06
N5.C3.D0.R1: CheckMCTest: result = 0x1FF
N7.C2.D0.R0.S06: Offset Found: RdPtrOffsetDqs = 006
N1.C2.D0.R0: Write Training Coarse, upper nibbles
N3.C2.D0.R0.S09: RdPtrOffsetTxDq: 07
N5.C3.D0.R1: CheckMCTest: passed
N7.C2.D0.R0.S07: Offset Found: RdPtrOffsetDqs = 006
N1.C2.D0.R0.S09: Dq Delay estimate: 446
N3.C2.D0.R0.S10: RdPtrOffsetTxDq: 07
N5.C3.D0.R1: CheckMCTest: passed
N7.C2.D0.R0.S08: Offset Found: RdPtrOffsetDqs = 006
N1.C2.D0.R0.S10: Dq Delay estimate: 435
N3.C2.D0.R0.S11: RdPtrOffsetTxDq: 07
N5.C3.D0.R1.S00: Offset Found: RdPtrOffsetDqs = 007
N7.C2.D0.R0: Write Training Coarse, upper nibbles
N1.C2.D0.R0.S11: Dq Delay estimate: 418
N3.C2.D0.R0.S12: RdPtrOffsetTxDq: 07
N5.C3.D0.R1.S01: Offset Found: RdPtrOffsetDqs = 007
N7.C2.D0.R0.S09: Dq Delay estimate: 446
N1.C2.D0.R0.S12: Dq Delay estimate: 403
N3.C2.D0.R0.S13: RdPtrOffsetTxDq: 06
N5.C3.D0.R1.S02: Offset Found: RdPtrOffsetDqs = 007
N7.C2.D0.R0.S10: Dq Delay estimate: 428
N1.C2.D0.R0.S13: Dq Delay estimate: 365
N3.C2.D0.R0.S14: RdPtrOffsetTxDq: 07
N5.C3.D0.R1.S03: Offset Found: RdPtrOffsetDqs = 006
N7.C2.D0.R0.S11: Dq Delay estimate: 421
N1.C2.D0.R0.S14: Dq Delay estimate: 389
N3.C2.D0.R0.S15: RdPtrOffsetTxDq: 07
N5.C3.D0.R1.S04: Offset Found: RdPtrOffsetDqs = 006
N7.C2.D0.R0.S12: Dq Delay estimate: 399
N1.C2.D0.R0.S15: Dq Delay estimate: 390
N3.C2.D0.R0.S16: RdPtrOffsetTxDq: 07
N5.C3.D0.R1.S05: Offset Found: RdPtrOffsetDqs = 006
N7.C2.D0.R0.S13: Dq Delay estimate: 360
N1.C2.D0.R0.S16: Dq Delay estimate: 413
N3.C2.D0.R0.S17: RdPtrOffsetTxDq: 06
N5.C3.D0.R1.S06: Offset Found: RdPtrOffsetDqs = 006
N7.C2.D0.R0.S14: Dq Delay estimate: 387
N1.C2.D0.R0.S17: Dq Delay estimate: 379
N3.C2.D0.R0.S00: Total Delay in PI ticks: TxDQ = 957
N5.C3.D0.R1.S07: Offset Found: RdPtrOffsetDqs = 007
N7.C2.D0.R0.S15: Dq Delay estimate: 393
ACCM: F0 F0F0F0F0 F0F0F0F0
N3.C2.D0.R0.S01: Total Delay in PI ticks: TxDQ = 938
N5.C3.D0.R1.S08: Offset Found: RdPtrOffsetDqs = 006
N7.C2.D0.R0.S16: Dq Delay estimate: 413
ACCM: F0 F0F0F0F0 F0F0F0F0
N3.C2.D0.R0.S02: Total Delay in PI ticks: TxDQ = 929
N5.C3.D0.R1: Write Training Coarse, upper nibbles
N7.C2.D0.R0.S17: Dq Delay estimate: 371
ACCM: F0 F0F0F0F0 F0F0F0F0
N3.C2.D0.R0.S03: Total Delay in PI ticks: TxDQ = 909
N5.C3.D0.R1.S09: Dq Delay estimate: 454
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: F0 F0F0F0F0 F0F0F0F0
N3.C2.D0.R0.S04: Total Delay in PI ticks: TxDQ = 874
N5.C3.D0.R1.S10: Dq Delay estimate: 442
ACCM: F0 F0F0F0F0 F0F0F0F0
N1.C2.D0.R0: CheckMCTest: result = 0x3FE00
N3.C2.D0.R0.S05: Total Delay in PI ticks: TxDQ = 899
N5.C3.D0.R1.S11: Dq Delay estimate: 431
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: F0 F0F0F0F0 F0F0F0F0
N3.C2.D0.R0.S06: Total Delay in PI ticks: TxDQ = 900
N5.C3.D0.R1.S12: Dq Delay estimate: 414
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: F0 F0F0F0F0 F0F0F0F0
N3.C2.D0.R0.S07: Total Delay in PI ticks: TxDQ = 920
N5.C3.D0.R1.S13: Dq Delay estimate: 376
N7.C2.D0.R0: CheckMCTest: result = 0x3FE00
ACCM: F0 F0F0F0F0 F0F0F0F0
N3.C2.D0.R0.S08: Total Delay in PI ticks: TxDQ = 884
N5.C3.D0.R1.S14: Dq Delay estimate: 393
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: F0 F0F0F0F0 F0F0F0F0
N3.C2.D0.R0.S09: Total Delay in PI ticks: TxDQ = 953
N5.C3.D0.R1.S15: Dq Delay estimate: 406
ACCM: F0 F0F0F0F0 F0F0F0F0
N1.C2.D0.R0: CheckMCTest: result = 0x3FE00
N3.C2.D0.R0.S10: Total Delay in PI ticks: TxDQ = 939
N5.C3.D0.R1.S16: Dq Delay estimate: 424
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: F0 F0F0F0F0 F0F0F0F0
N3.C2.D0.R0.S11: Total Delay in PI ticks: TxDQ = 931
N5.C3.D0.R1.S17: Dq Delay estimate: 392
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: F0 F0F0F0F0 F0F0F0F0
N3.C2.D0.R0.S12: Total Delay in PI ticks: TxDQ = 909
ACCM: F0 F0F0F0F0 F0F0F0F0
N7.C2.D0.R0: CheckMCTest: result = 0x3FE00
ACCM: 00 00000000 00000000
N3.C2.D0.R0.S13: Total Delay in PI ticks: TxDQ = 873
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: 00 00000000 00000000
N3.C2.D0.R0.S14: Total Delay in PI ticks: TxDQ = 899
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: F0 F0F0F0F0 F0F0F0F0
N1.C2.D0.R0: CheckMCTest: result = 0x3FE00
N3.C2.D0.R0.S15: Total Delay in PI ticks: TxDQ = 900
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: 00 00000000 00000000
ACCM: F0 F0F0F0F0 F0F0F0F0
N3.C2.D0.R0.S16: Total Delay in PI ticks: TxDQ = 921
N5.C3.D0.R1: CheckMCTest: result = 0x3FE00
ACCM: 00 00000000 00000000
ACCM: F0 F0F0F0F0 F0F0F0F0
N3.C2.D0.R0.S17: Total Delay in PI ticks: TxDQ = 885
ACCM: F0 F0F0F0F0 F0F0F0F0
N7.C2.D0.R0: CheckMCTest: result = 0x3FE00
ACCM: 00 00000000 00000000
N3.C2.D0.R1.S00: wrcmd2dqsstartlatency: 04
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: 00 00000000 00000000
N3.C2.D0.R1.S00: RdPtrOffsetTxDq: 05
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: F0 F0F0F0F0 F0F0F0F0
N1.C2.D0.R0: CheckMCTest: result = 0x3FE00
N3.C2.D0.R1.S00: RdPtrOffsetTxDqs: 07
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: 00 00000000 00000000
N1.C2.D0.R0: CheckMCTest: passed
N3.C2.D0.R1.S00: PiTxDqs: 29
N5.C3.D0.R1: CheckMCTest: result = 0x3FE00
ACCM: 00 00000000 00000000
N1.C2.D0.R0: CheckMCTest: passed
N3.C2.D0.R1.S01: wrcmd2dqsstartlatency: 04
ACCM: F0 F0F0F0F0 F0F0F0F0
N7.C2.D0.R0: CheckMCTest: result = 0x3FE00
N1.C2.D0.R0.S09: Offset Found: RdPtrOffsetDqs = 007
N3.C2.D0.R1.S01: RdPtrOffsetTxDq: 05
ACCM: F0 F0F0F0F0 F0F0F0F0
N7.C2.D0.R0: CheckMCTest: passed
N1.C2.D0.R0.S10: Offset Found: RdPtrOffsetDqs = 007
N3.C2.D0.R1.S01: RdPtrOffsetTxDqs: 07
ACCM: 00 00000000 00000000
N7.C2.D0.R0: CheckMCTest: passed
N1.C2.D0.R0.S11: Offset Found: RdPtrOffsetDqs = 007
N3.C2.D0.R1.S01: PiTxDqs: 10
ACCM: 00 00000000 00000000
N7.C2.D0.R0.S09: Offset Found: RdPtrOffsetDqs = 007
N1.C2.D0.R0.S12: Offset Found: RdPtrOffsetDqs = 006
N3.C2.D0.R1.S02: wrcmd2dqsstartlatency: 04
N5.C3.D0.R1: CheckMCTest: result = 0x3FE00
N7.C2.D0.R0.S10: Offset Found: RdPtrOffsetDqs = 007
N1.C2.D0.R0.S13: Offset Found: RdPtrOffsetDqs = 006
N3.C2.D0.R1.S02: RdPtrOffsetTxDq: 05
ACCM: F0 F0F0F0F0 F0F0F0F0
N7.C2.D0.R0.S11: Offset Found: RdPtrOffsetDqs = 007
N1.C2.D0.R0.S14: Offset Found: RdPtrOffsetDqs = 006
N3.C2.D0.R1.S02: RdPtrOffsetTxDqs: 07
ACCM: F0 F0F0F0F0 F0F0F0F0
N7.C2.D0.R0.S12: Offset Found: RdPtrOffsetDqs = 006
N1.C2.D0.R0.S15: Offset Found: RdPtrOffsetDqs = 006
N3.C2.D0.R1.S02: PiTxDqs: 01
ACCM: 00 00000000 00000000
N7.C2.D0.R0.S13: Offset Found: RdPtrOffsetDqs = 006
N1.C2.D0.R0.S16: Offset Found: RdPtrOffsetDqs = 006
N3.C2.D0.R1.S03: wrcmd2dqsstartlatency: 04
ACCM: 00 00000000 00000000
N7.C2.D0.R0.S14: Offset Found: RdPtrOffsetDqs = 006
N1.C2.D0.R0.S17: Offset Found: RdPtrOffsetDqs = 006
N3.C2.D0.R1.S03: RdPtrOffsetTxDq: 05
N5.C3.D0.R1: CheckMCTest: result = 0x3FE00
N7.C2.D0.R0.S15: Offset Found: RdPtrOffsetDqs = 006
N1.C2.D0.R1: Write Training Coarse, lower nibbles / bytes
N3.C2.D0.R1.S03: RdPtrOffsetTxDqs: 06
N5.C3.D0.R1: CheckMCTest: passed
N7.C2.D0.R0.S16: Offset Found: RdPtrOffsetDqs = 006
N1.C2.D0.R1.S00: Dq Delay estimate: 448
N3.C2.D0.R1.S03: PiTxDqs: 48
N5.C3.D0.R1: CheckMCTest: passed
N7.C2.D0.R0.S17: Offset Found: RdPtrOffsetDqs = 006
N1.C2.D0.R1.S01: Dq Delay estimate: 430
N3.C2.D0.R1.S04: wrcmd2dqsstartlatency: 04
N5.C3.D0.R1.S09: Offset Found: RdPtrOffsetDqs = 007
N7.C2.D0.R1: Write Training Coarse, lower nibbles / bytes
N1.C2.D0.R1.S02: Dq Delay estimate: 417
N3.C2.D0.R1.S04: RdPtrOffsetTxDq: 04
N5.C3.D0.R1.S10: Offset Found: RdPtrOffsetDqs = 007
N7.C2.D0.R1.S00: Dq Delay estimate: 447
N1.C2.D0.R1.S03: Dq Delay estimate: 403
N3.C2.D0.R1.S04: RdPtrOffsetTxDqs: 06
N5.C3.D0.R1.S11: Offset Found: RdPtrOffsetDqs = 007
N7.C2.D0.R1.S01: Dq Delay estimate: 428
N1.C2.D0.R1.S04: Dq Delay estimate: 364
N3.C2.D0.R1.S04: PiTxDqs: 07
N5.C3.D0.R1.S12: Offset Found: RdPtrOffsetDqs = 007
N7.C2.D0.R1.S02: Dq Delay estimate: 417
N1.C2.D0.R1.S05: Dq Delay estimate: 391
N3.C2.D0.R1.S05: wrcmd2dqsstartlatency: 04
N5.C3.D0.R1.S13: Offset Found: RdPtrOffsetDqs = 006
N7.C2.D0.R1.S03: Dq Delay estimate: 399
N1.C2.D0.R1.S06: Dq Delay estimate: 389
N3.C2.D0.R1.S05: RdPtrOffsetTxDq: 05
N5.C3.D0.R1.S14: Offset Found: RdPtrOffsetDqs = 006
N7.C2.D0.R1.S04: Dq Delay estimate: 359
N1.C2.D0.R1.S07: Dq Delay estimate: 413
N3.C2.D0.R1.S05: RdPtrOffsetTxDqs: 06
N5.C3.D0.R1.S15: Offset Found: RdPtrOffsetDqs = 006
N7.C2.D0.R1.S05: Dq Delay estimate: 387
N1.C2.D0.R1.S08: Dq Delay estimate: 375
N3.C2.D0.R1.S05: PiTxDqs: 39
N5.C3.D0.R1.S16: Offset Found: RdPtrOffsetDqs = 007
N7.C2.D0.R1.S06: Dq Delay estimate: 385
ACCM: 0F 0F0F0F0F 0F0F0F0F
N3.C2.D0.R1.S06: wrcmd2dqsstartlatency: 04
N5.C3.D0.R1.S17: Offset Found: RdPtrOffsetDqs = 006
N7.C2.D0.R1.S07: Dq Delay estimate: 412
ACCM: 0F 0F0F0F0F 0F0F0F0F
N3.C2.D0.R1.S06: RdPtrOffsetTxDq: 05
N5.C3: Calculating Optimimum DQS Values
N7.C2.D0.R1.S08: Dq Delay estimate: 374
ACCM: 0F 0F0F0F0F 0F0F0F0F
N3.C2.D0.R1.S06: RdPtrOffsetTxDqs: 06
N5.C3.D0.R0.S00: Total Delay in PI ticks: TxDQS = 1003, TxDQ = 968
ACCM: 0F 0F0F0F0F 0F0F0F0F
ACCM: 0F 0F0F0F0F 0F0F0F0F
N3.C2.D0.R1.S06: PiTxDqs: 39
N5.C3.D0.R0.S01: Total Delay in PI ticks: TxDQS = 987, TxDQ = 954
ACCM: 0F 0F0F0F0F 0F0F0F0F
N1.C2.D0.R1: CheckMCTest: result = 0x1FF
N3.C2.D0.R1.S07: wrcmd2dqsstartlatency: 04
N5.C3.D0.R0.S02: Total Delay in PI ticks: TxDQS = 974, TxDQ = 939
ACCM: 0F 0F0F0F0F 0F0F0F0F
ACCM: 0F 0F0F0F0F 0F0F0F0F
N3.C2.D0.R1.S07: RdPtrOffsetTxDq: 05
N5.C3.D0.R0.S03: Total Delay in PI ticks: TxDQS = 959, TxDQ = 925
ACCM: 0F 0F0F0F0F 0F0F0F0F
ACCM: 0F 0F0F0F0F 0F0F0F0F
N3.C2.D0.R1.S07: RdPtrOffsetTxDqs: 06
N5.C3.D0.R0.S04: Total Delay in PI ticks: TxDQS = 922, TxDQ = 887
N7.C2.D0.R1: CheckMCTest: result = 0x1FF
ACCM: 0F 0F0F0F0F 0F0F0F0F
N3.C2.D0.R1.S07: PiTxDqs: 58
N5.C3.D0.R0.S05: Total Delay in PI ticks: TxDQS = 938, TxDQ = 904
ACCM: 0F 0F0F0F0F 0F0F0F0F
ACCM: 0F 0F0F0F0F 0F0F0F0F
N3.C2.D0.R1.S08: wrcmd2dqsstartlatency: 04
N5.C3.D0.R0.S06: Total Delay in PI ticks: TxDQS = 952, TxDQ = 918
ACCM: 0F 0F0F0F0F 0F0F0F0F
N1.C2.D0.R1: CheckMCTest: result = 0x1FF
N3.C2.D0.R1.S08: RdPtrOffsetTxDq: 04
N5.C3.D0.R0.S07: Total Delay in PI ticks: TxDQS = 969, TxDQ = 934
ACCM: 0F 0F0F0F0F 0F0F0F0F
ACCM: 0F 0F0F0F0F 0F0F0F0F
N3.C2.D0.R1.S08: RdPtrOffsetTxDqs: 06
N5.C3.D0.R0.S08: Total Delay in PI ticks: TxDQS = 940, TxDQ = 906
ACCM: 0F 0F0F0F0F 0F0F0F0F
ACCM: 0F 0F0F0F0F 0F0F0F0F
N3.C2.D0.R1.S08: PiTxDqs: 24
N5.C3.D0.R0.S09: Total Delay in PI ticks: TxDQS = 1003, TxDQ = 967
N7.C2.D0.R1: CheckMCTest: result = 0x1FF
ACCM: 00 00000000 00000000
N3.C2.D0.R1.S09: wrcmd2dqsstartlatency: 04
N5.C3.D0.R0.S10: Total Delay in PI ticks: TxDQS = 989, TxDQ = 956
ACCM: 0F 0F0F0F0F 0F0F0F0F
ACCM: 00 00000000 00000000
N3.C2.D0.R1.S09: RdPtrOffsetTxDq: 05
N5.C3.D0.R0.S11: Total Delay in PI ticks: TxDQS = 975, TxDQ = 942
ACCM: 0F 0F0F0F0F 0F0F0F0F
N1.C2.D0.R1: CheckMCTest: result = 0x1FF
N3.C2.D0.R1.S09: RdPtrOffsetTxDqs: 07
N5.C3.D0.R0.S12: Total Delay in PI ticks: TxDQS = 959, TxDQ = 925
ACCM: 00 00000000 00000000
ACCM: 0F 0F0F0F0F 0F0F0F0F
N3.C2.D0.R1.S09: PiTxDqs: 26
N5.C3.D0.R0.S13: Total Delay in PI ticks: TxDQS = 924, TxDQ = 890
ACCM: 00 00000000 00000000
ACCM: 0F 0F0F0F0F 0F0F0F0F
N3.C2.D0.R1.S10: wrcmd2dqsstartlatency: 04
N5.C3.D0.R0.S14: Total Delay in PI ticks: TxDQS = 938, TxDQ = 905
N7.C2.D0.R1: CheckMCTest: result = 0x1FF
ACCM: 00 00000000 00000000
N3.C2.D0.R1.S10: RdPtrOffsetTxDq: 05
N5.C3.D0.R0.S15: Total Delay in PI ticks: TxDQS = 953, TxDQ = 919
ACCM: 0F 0F0F0F0F 0F0F0F0F
ACCM: 00 00000000 00000000
N3.C2.D0.R1.S10: RdPtrOffsetTxDqs: 07
N5.C3.D0.R0.S16: Total Delay in PI ticks: TxDQS = 969, TxDQ = 936
ACCM: 0F 0F0F0F0F 0F0F0F0F
N1.C2.D0.R1: CheckMCTest: result = 0x1FF
N3.C2.D0.R1.S10: PiTxDqs: 14
N5.C3.D0.R0.S17: Total Delay in PI ticks: TxDQS = 940, TxDQ = 905
ACCM: 00 00000000 00000000
N1.C2.D0.R1: CheckMCTest: passed
N3.C2.D0.R1.S11: wrcmd2dqsstartlatency: 04
N5.C3.D0.R1.S00: Total Delay in PI ticks: TxDQS = 1004, TxDQ = 969
ACCM: 00 00000000 00000000
N1.C2.D0.R1: CheckMCTest: passed
N3.C2.D0.R1.S11: RdPtrOffsetTxDq: 05
N5.C3.D0.R1.S01: Total Delay in PI ticks: TxDQS = 987, TxDQ = 953
N7.C2.D0.R1: CheckMCTest: result = 0x1FF
N1.C2.D0.R1.S00: Offset Found: RdPtrOffsetDqs = 007
N3.C2.D0.R1.S11: RdPtrOffsetTxDqs: 07
N5.C3.D0.R1.S02: Total Delay in PI ticks: TxDQS = 975, TxDQ = 941
N7.C2.D0.R1: CheckMCTest: passed
N1.C2.D0.R1.S01: Offset Found: RdPtrOffsetDqs = 007
N3.C2.D0.R1.S11: PiTxDqs: 02
N5.C3.D0.R1.S03: Total Delay in PI ticks: TxDQS = 958, TxDQ = 923
N7.C2.D0.R1: CheckMCTest: passed
N1.C2.D0.R1.S02: Offset Found: RdPtrOffsetDqs = 007
N3.C2.D0.R1.S12: wrcmd2dqsstartlatency: 04
N5.C3.D0.R1.S04: Total Delay in PI ticks: TxDQS = 923, TxDQ = 888
N7.C2.D0.R1.S00: Offset Found: RdPtrOffsetDqs = 007
N1.C2.D0.R1.S03: Offset Found: RdPtrOffsetDqs = 006
N3.C2.D0.R1.S12: RdPtrOffsetTxDq: 05
N5.C3.D0.R1.S05: Total Delay in PI ticks: TxDQS = 939, TxDQ = 904
N7.C2.D0.R1.S01: Offset Found: RdPtrOffsetDqs = 007
N1.C2.D0.R1.S04: Offset Found: RdPtrOffsetDqs = 006
N3.C2.D0.R1.S12: RdPtrOffsetTxDqs: 06
N5.C3.D0.R1.S06: Total Delay in PI ticks: TxDQS = 952, TxDQ = 918
N7.C2.D0.R1.S02: Offset Found: RdPtrOffsetDqs = 007
N1.C2.D0.R1.S05: Offset Found: RdPtrOffsetDqs = 006
N3.C2.D0.R1.S12: PiTxDqs: 49
N5.C3.D0.R1.S07: Total Delay in PI ticks: TxDQS = 969, TxDQ = 934
N7.C2.D0.R1.S03: Offset Found: RdPtrOffsetDqs = 006
N1.C2.D0.R1.S06: Offset Found: RdPtrOffsetDqs = 006
N3.C2.D0.R1.S13: wrcmd2dqsstartlatency: 04
N5.C3.D0.R1.S08: Total Delay in PI ticks: TxDQS = 940, TxDQ = 906
N7.C2.D0.R1.S04: Offset Found: RdPtrOffsetDqs = 006
N1.C2.D0.R1.S07: Offset Found: RdPtrOffsetDqs = 006
N3.C2.D0.R1.S13: RdPtrOffsetTxDq: 04
N5.C3.D0.R1.S09: Total Delay in PI ticks: TxDQS = 1002, TxDQ = 966
N7.C2.D0.R1.S05: Offset Found: RdPtrOffsetDqs = 006
N1.C2.D0.R1.S08: Offset Found: RdPtrOffsetDqs = 006
N3.C2.D0.R1.S13: RdPtrOffsetTxDqs: 06
N5.C3.D0.R1.S10: Total Delay in PI ticks: TxDQS = 987, TxDQ = 954
N7.C2.D0.R1.S06: Offset Found: RdPtrOffsetDqs = 006
N1.C2.D0.R1: Write Training Coarse, upper nibbles
N3.C2.D0.R1.S13: PiTxDqs: 08
N5.C3.D0.R1.S11: Total Delay in PI ticks: TxDQS = 976, TxDQ = 943
N7.C2.D0.R1.S07: Offset Found: RdPtrOffsetDqs = 006
N1.C2.D0.R1.S09: Dq Delay estimate: 444
N3.C2.D0.R1.S14: wrcmd2dqsstartlatency: 04
N5.C3.D0.R1.S12: Total Delay in PI ticks: TxDQS = 960, TxDQ = 926
N7.C2.D0.R1.S08: Offset Found: RdPtrOffsetDqs = 006
N1.C2.D0.R1.S10: Dq Delay estimate: 433
N3.C2.D0.R1.S14: RdPtrOffsetTxDq: 05
N5.C3.D0.R1.S13: Total Delay in PI ticks: TxDQS = 923, TxDQ = 888
N7.C2.D0.R1: Write Training Coarse, upper nibbles
N1.C2.D0.R1.S11: Dq Delay estimate: 420
N3.C2.D0.R1.S14: RdPtrOffsetTxDqs: 06
N5.C3.D0.R1.S14: Total Delay in PI ticks: TxDQS = 938, TxDQ = 905
N7.C2.D0.R1.S09: Dq Delay estimate: 443
N1.C2.D0.R1.S12: Dq Delay estimate: 403
N3.C2.D0.R1.S14: PiTxDqs: 36
N5.C3.D0.R1.S15: Total Delay in PI ticks: TxDQS = 952, TxDQ = 918
N7.C2.D0.R1.S10: Dq Delay estimate: 429
N1.C2.D0.R1.S13: Dq Delay estimate: 366
N3.C2.D0.R1.S15: wrcmd2dqsstartlatency: 04
N5.C3.D0.R1.S16: Total Delay in PI ticks: TxDQS = 970, TxDQ = 936
N7.C2.D0.R1.S11: Dq Delay estimate: 421
N1.C2.D0.R1.S14: Dq Delay estimate: 390
N3.C2.D0.R1.S15: RdPtrOffsetTxDq: 05
N5.C3.D0.R1.S17: Total Delay in PI ticks: TxDQS = 939, TxDQ = 904
N7.C2.D0.R1.S12: Dq Delay estimate: 399
N1.C2.D0.R1.S15: Dq Delay estimate: 391
N3.C2.D0.R1.S15: RdPtrOffsetTxDqs: 06
N5: END WRITE LEVEL COARSE:
N7.C2.D0.R1.S13: Dq Delay estimate: 360
N1.C2.D0.R1.S16: Dq Delay estimate: 416
N3.C2.D0.R1.S15: PiTxDqs: 39
N5: RunTrainStep: Final status = 0
N7.C2.D0.R1.S14: Dq Delay estimate: 386
N1.C2.D0.R1.S17: Dq Delay estimate: 376
N3.C2.D0.R1.S16: wrcmd2dqsstartlatency: 04

END - Basic Write Level Training       Time         19332 ms
N7.C2.D0.R1.S15: Dq Delay estimate: 394
ACCM: F0 F0F0F0F0 F0F0F0F0
N3.C2.D0.R1.S16: RdPtrOffsetTxDq: 05

START - Basic Write DQ/DQS Training
N7.C2.D0.R1.S16: Dq Delay estimate: 416
ACCM: F0 F0F0F0F0 F0F0F0F0
N3.C2.D0.R1.S16: RdPtrOffsetTxDqs: 06
N5.C0.D0.R0.S00: wrcmd2dqsstartlatency: 04
N7.C2.D0.R1.S17: Dq Delay estimate: 371
ACCM: F0 F0F0F0F0 F0F0F0F0
N3.C2.D0.R1.S16: PiTxDqs: 62
N5.C0.D0.R0.S00: RdPtrOffsetTxDq: 05
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: F0 F0F0F0F0 F0F0F0F0
N3.C2.D0.R1.S17: wrcmd2dqsstartlatency: 04
N5.C0.D0.R0.S00: RdPtrOffsetTxDqs: 07
ACCM: F0 F0F0F0F0 F0F0F0F0
N1.C2.D0.R1: CheckMCTest: result = 0x3FE00
N3.C2.D0.R1.S17: RdPtrOffsetTxDq: 04
N5.C0.D0.R0.S00: PiTxDqs: 33
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: F0 F0F0F0F0 F0F0F0F0
N3.C2.D0.R1.S17: RdPtrOffsetTxDqs: 06
N5.C0.D0.R0.S01: wrcmd2dqsstartlatency: 04
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: F0 F0F0F0F0 F0F0F0F0
N3.C2.D0.R1.S17: PiTxDqs: 24
N5.C0.D0.R0.S01: RdPtrOffsetTxDq: 05
N7.C2.D0.R1: CheckMCTest: result = 0x3FE00
ACCM: F0 F0F0F0F0 F0F0F0F0
N3.C2.D0.R1.S00: RdPtrOffsetTxDq: 06
N5.C0.D0.R0.S01: RdPtrOffsetTxDqs: 07
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: F0 F0F0F0F0 F0F0F0F0
N3.C2.D0.R1.S01: RdPtrOffsetTxDq: 06
N5.C0.D0.R0.S01: PiTxDqs: 18
ACCM: F0 F0F0F0F0 F0F0F0F0
N1.C2.D0.R1: CheckMCTest: result = 0x3FE00
N3.C2.D0.R1.S02: RdPtrOffsetTxDq: 06
N5.C0.D0.R0.S02: wrcmd2dqsstartlatency: 04
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: F0 F0F0F0F0 F0F0F0F0
N3.C2.D0.R1.S03: RdPtrOffsetTxDq: 06
N5.C0.D0.R0.S02: RdPtrOffsetTxDq: 05
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: F0 F0F0F0F0 F0F0F0F0
N3.C2.D0.R1.S04: RdPtrOffsetTxDq: 05
N5.C0.D0.R0.S02: RdPtrOffsetTxDqs: 07
N7.C2.D0.R1: CheckMCTest: result = 0x3FE00
ACCM: 00 00000000 00000000
N3.C2.D0.R1.S05: RdPtrOffsetTxDq: 06
N5.C0.D0.R0.S02: PiTxDqs: 04
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: 00 00000000 00000000
N3.C2.D0.R1.S06: RdPtrOffsetTxDq: 06
N5.C0.D0.R0.S03: wrcmd2dqsstartlatency: 04
ACCM: F0 F0F0F0F0 F0F0F0F0
N1.C2.D0.R1: CheckMCTest: result = 0x3FE00
N3.C2.D0.R1.S07: RdPtrOffsetTxDq: 06
N5.C0.D0.R0.S03: RdPtrOffsetTxDq: 05
ACCM: 00 00000000 00000000
ACCM: F0 F0F0F0F0 F0F0F0F0
N3.C2.D0.R1.S08: RdPtrOffsetTxDq: 05
N5.C0.D0.R0.S03: RdPtrOffsetTxDqs: 06
ACCM: 00 00000000 00000000
ACCM: F0 F0F0F0F0 F0F0F0F0
N3.C2.D0.R1.S09: RdPtrOffsetTxDq: 06
N5.C0.D0.R0.S03: PiTxDqs: 53
N7.C2.D0.R1: CheckMCTest: result = 0x3FE00
ACCM: 00 00000000 00000000
N3.C2.D0.R1.S10: RdPtrOffsetTxDq: 06
N5.C0.D0.R0.S04: wrcmd2dqsstartlatency: 04
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: 00 00000000 00000000
N3.C2.D0.R1.S11: RdPtrOffsetTxDq: 06
N5.C0.D0.R0.S04: RdPtrOffsetTxDq: 04
ACCM: F0 F0F0F0F0 F0F0F0F0
N1.C2.D0.R1: CheckMCTest: result = 0x3FE00
N3.C2.D0.R1.S12: RdPtrOffsetTxDq: 06
N5.C0.D0.R0.S04: RdPtrOffsetTxDqs: 06
ACCM: 00 00000000 00000000
N1.C2.D0.R1: CheckMCTest: passed
N3.C2.D0.R1.S13: RdPtrOffsetTxDq: 05
N5.C0.D0.R0.S04: PiTxDqs: 19
ACCM: 00 00000000 00000000
N1.C2.D0.R1: CheckMCTest: passed
N3.C2.D0.R1.S14: RdPtrOffsetTxDq: 06
N5.C0.D0.R0.S05: wrcmd2dqsstartlatency: 04
N7.C2.D0.R1: CheckMCTest: result = 0x3FE00
N1.C2.D0.R1.S09: Offset Found: RdPtrOffsetDqs = 007
N3.C2.D0.R1.S15: RdPtrOffsetTxDq: 06
N5.C0.D0.R0.S05: RdPtrOffsetTxDq: 05
N7.C2.D0.R1: CheckMCTest: passed
N1.C2.D0.R1.S10: Offset Found: RdPtrOffsetDqs = 007
N3.C2.D0.R1.S16: RdPtrOffsetTxDq: 06
N5.C0.D0.R0.S05: RdPtrOffsetTxDqs: 06
N7.C2.D0.R1: CheckMCTest: passed
N1.C2.D0.R1.S11: Offset Found: RdPtrOffsetDqs = 007
N3.C2.D0.R1.S17: RdPtrOffsetTxDq: 05
N5.C0.D0.R0.S05: PiTxDqs: 36
N7.C2.D0.R1.S09: Offset Found: RdPtrOffsetDqs = 007
N1.C2.D0.R1.S12: Offset Found: RdPtrOffsetDqs = 006
N3.C2.D0.R1.S00: RdPtrOffsetTxDq: 07
N5.C0.D0.R0.S06: wrcmd2dqsstartlatency: 04
N7.C2.D0.R1.S10: Offset Found: RdPtrOffsetDqs = 007
N1.C2.D0.R1.S13: Offset Found: RdPtrOffsetDqs = 006
N3.C2.D0.R1.S01: RdPtrOffsetTxDq: 07
N5.C0.D0.R0.S06: RdPtrOffsetTxDq: 05
N7.C2.D0.R1.S11: Offset Found: RdPtrOffsetDqs = 007
N1.C2.D0.R1.S14: Offset Found: RdPtrOffsetDqs = 006
N3.C2.D0.R1.S02: RdPtrOffsetTxDq: 07
N5.C0.D0.R0.S06: RdPtrOffsetTxDqs: 06
N7.C2.D0.R1.S12: Offset Found: RdPtrOffsetDqs = 006
N1.C2.D0.R1.S15: Offset Found: RdPtrOffsetDqs = 006
N3.C2.D0.R1.S03: RdPtrOffsetTxDq: 07
N5.C0.D0.R0.S06: PiTxDqs: 42
N7.C2.D0.R1.S13: Offset Found: RdPtrOffsetDqs = 006
N1.C2.D0.R1.S16: Offset Found: RdPtrOffsetDqs = 007
N3.C2.D0.R1.S04: RdPtrOffsetTxDq: 06
N5.C0.D0.R0.S07: wrcmd2dqsstartlatency: 04
N7.C2.D0.R1.S14: Offset Found: RdPtrOffsetDqs = 006
N1.C2.D0.R1.S17: Offset Found: RdPtrOffsetDqs = 006
N3.C2.D0.R1.S05: RdPtrOffsetTxDq: 07
N5.C0.D0.R0.S07: RdPtrOffsetTxDq: 05
N7.C2.D0.R1.S15: Offset Found: RdPtrOffsetDqs = 006
N1.C2: Calculating Optimimum DQS Values
N3.C2.D0.R1.S06: RdPtrOffsetTxDq: 07
N5.C0.D0.R0.S07: RdPtrOffsetTxDqs: 06
N7.C2.D0.R1.S16: Offset Found: RdPtrOffsetDqs = 006
N1.C2.D0.R0.S00: Total Delay in PI ticks: TxDQS = 993, TxDQ = 960
N3.C2.D0.R1.S07: RdPtrOffsetTxDq: 07
N5.C0.D0.R0.S07: PiTxDqs: 58
N7.C2.D0.R1.S17: Offset Found: RdPtrOffsetDqs = 006
N1.C2.D0.R0.S01: Total Delay in PI ticks: TxDQS = 978, TxDQ = 943
N3.C2.D0.R1.S08: RdPtrOffsetTxDq: 06
N5.C0.D0.R0.S08: wrcmd2dqsstartlatency: 04
N7.C2: Calculating Optimimum DQS Values
N1.C2.D0.R0.S02: Total Delay in PI ticks: TxDQS = 965, TxDQ = 930
N3.C2.D0.R1.S09: RdPtrOffsetTxDq: 07
N5.C0.D0.R0.S08: RdPtrOffsetTxDq: 04
N7.C2.D0.R0.S00: Total Delay in PI ticks: TxDQS = 989, TxDQ = 956
N1.C2.D0.R0.S03: Total Delay in PI ticks: TxDQS = 950, TxDQ = 916
N3.C2.D0.R1.S10: RdPtrOffsetTxDq: 07
N5.C0.D0.R0.S08: RdPtrOffsetTxDqs: 06
N7.C2.D0.R0.S01: Total Delay in PI ticks: TxDQS = 975, TxDQ = 940
N1.C2.D0.R0.S04: Total Delay in PI ticks: TxDQS = 911, TxDQ = 878
N3.C2.D0.R1.S11: RdPtrOffsetTxDq: 07
N5.C0.D0.R0.S08: PiTxDqs: 25
N7.C2.D0.R0.S02: Total Delay in PI ticks: TxDQS = 964, TxDQ = 930
N1.C2.D0.R0.S05: Total Delay in PI ticks: TxDQS = 939, TxDQ = 903
N3.C2.D0.R1.S12: RdPtrOffsetTxDq: 07
N5.C0.D0.R0.S09: wrcmd2dqsstartlatency: 04
N7.C2.D0.R0.S03: Total Delay in PI ticks: TxDQS = 947, TxDQ = 913
N1.C2.D0.R0.S06: Total Delay in PI ticks: TxDQS = 935, TxDQ = 900
N3.C2.D0.R1.S13: RdPtrOffsetTxDq: 06
N5.C0.D0.R0.S09: RdPtrOffsetTxDq: 05
N7.C2.D0.R0.S04: Total Delay in PI ticks: TxDQS = 904, TxDQ = 870
N1.C2.D0.R0.S07: Total Delay in PI ticks: TxDQS = 959, TxDQ = 924
N3.C2.D0.R1.S14: RdPtrOffsetTxDq: 07
N5.C0.D0.R0.S09: RdPtrOffsetTxDqs: 07
N7.C2.D0.R0.S05: Total Delay in PI ticks: TxDQS = 935, TxDQ = 899
N1.C2.D0.R0.S08: Total Delay in PI ticks: TxDQS = 925, TxDQ = 891
N3.C2.D0.R1.S15: RdPtrOffsetTxDq: 07
N5.C0.D0.R0.S09: PiTxDqs: 33
N7.C2.D0.R0.S06: Total Delay in PI ticks: TxDQS = 934, TxDQ = 899
N1.C2.D0.R0.S09: Total Delay in PI ticks: TxDQS = 993, TxDQ = 958
N3.C2.D0.R1.S16: RdPtrOffsetTxDq: 07
N5.C0.D0.R0.S10: wrcmd2dqsstartlatency: 04
N7.C2.D0.R0.S07: Total Delay in PI ticks: TxDQS = 956, TxDQ = 925
N1.C2.D0.R0.S10: Total Delay in PI ticks: TxDQS = 980, TxDQ = 947
N3.C2.D0.R1.S17: RdPtrOffsetTxDq: 06
N5.C0.D0.R0.S10: RdPtrOffsetTxDq: 05
N7.C2.D0.R0.S08: Total Delay in PI ticks: TxDQS = 920, TxDQ = 885
N1.C2.D0.R0.S11: Total Delay in PI ticks: TxDQS = 965, TxDQ = 930
N3.C2.D0.R1.S00: Total Delay in PI ticks: TxDQ = 956
N5.C0.D0.R0.S10: RdPtrOffsetTxDqs: 07
N7.C2.D0.R0.S09: Total Delay in PI ticks: TxDQS = 990, TxDQ = 958
N1.C2.D0.R0.S12: Total Delay in PI ticks: TxDQS = 950, TxDQ = 915
N3.C2.D0.R1.S01: Total Delay in PI ticks: TxDQ = 937
N5.C0.D0.R0.S10: PiTxDqs: 18
N7.C2.D0.R0.S10: Total Delay in PI ticks: TxDQS = 975, TxDQ = 940
N1.C2.D0.R0.S13: Total Delay in PI ticks: TxDQS = 910, TxDQ = 877
N3.C2.D0.R1.S02: Total Delay in PI ticks: TxDQ = 930
N5.C0.D0.R0.S11: wrcmd2dqsstartlatency: 04
N7.C2.D0.R0.S11: Total Delay in PI ticks: TxDQS = 966, TxDQ = 933
N1.C2.D0.R0.S14: Total Delay in PI ticks: TxDQS = 937, TxDQ = 901
N3.C2.D0.R1.S03: Total Delay in PI ticks: TxDQ = 910
N5.C0.D0.R0.S11: RdPtrOffsetTxDq: 05
N7.C2.D0.R0.S12: Total Delay in PI ticks: TxDQS = 947, TxDQ = 911
N1.C2.D0.R0.S15: Total Delay in PI ticks: TxDQS = 937, TxDQ = 902
N3.C2.D0.R1.S04: Total Delay in PI ticks: TxDQ = 872
N5.C0.D0.R0.S11: RdPtrOffsetTxDqs: 07
N7.C2.D0.R0.S13: Total Delay in PI ticks: TxDQS = 904, TxDQ = 872
N1.C2.D0.R0.S16: Total Delay in PI ticks: TxDQS = 959, TxDQ = 925
N3.C2.D0.R1.S05: Total Delay in PI ticks: TxDQ = 901
N5.C0.D0.R0.S11: PiTxDqs: 07
N7.C2.D0.R0.S14: Total Delay in PI ticks: TxDQS = 933, TxDQ = 899
N1.C2.D0.R0.S17: Total Delay in PI ticks: TxDQS = 926, TxDQ = 891
N3.C2.D0.R1.S06: Total Delay in PI ticks: TxDQ = 901
N5.C0.D0.R0.S12: wrcmd2dqsstartlatency: 04
N7.C2.D0.R0.S15: Total Delay in PI ticks: TxDQS = 934, TxDQ = 905
N1.C2.D0.R1.S00: Total Delay in PI ticks: TxDQS = 992, TxDQ = 960
N3.C2.D0.R1.S07: Total Delay in PI ticks: TxDQ = 921
N5.C0.D0.R0.S12: RdPtrOffsetTxDq: 05
N7.C2.D0.R0.S16: Total Delay in PI ticks: TxDQS = 954, TxDQ = 925
N1.C2.D0.R1.S01: Total Delay in PI ticks: TxDQS = 977, TxDQ = 942
N3.C2.D0.R1.S08: Total Delay in PI ticks: TxDQ = 884
N5.C0.D0.R0.S12: RdPtrOffsetTxDqs: 06
N7.C2.D0.R0.S17: Total Delay in PI ticks: TxDQS = 920, TxDQ = 883
N1.C2.D0.R1.S02: Total Delay in PI ticks: TxDQS = 964, TxDQ = 929
N3.C2.D0.R1.S09: Total Delay in PI ticks: TxDQ = 954
N5.C0.D0.R0.S12: PiTxDqs: 53
N7.C2.D0.R1.S00: Total Delay in PI ticks: TxDQS = 991, TxDQ = 959
N1.C2.D0.R1.S03: Total Delay in PI ticks: TxDQS = 949, TxDQ = 915
N3.C2.D0.R1.S10: Total Delay in PI ticks: TxDQ = 938
N5.C0.D0.R0.S13: wrcmd2dqsstartlatency: 04
N7.C2.D0.R1.S01: Total Delay in PI ticks: TxDQS = 974, TxDQ = 940
N1.C2.D0.R1.S04: Total Delay in PI ticks: TxDQS = 910, TxDQ = 876
N3.C2.D0.R1.S11: Total Delay in PI ticks: TxDQ = 929
N5.C0.D0.R0.S13: RdPtrOffsetTxDq: 04
N7.C2.D0.R1.S02: Total Delay in PI ticks: TxDQS = 962, TxDQ = 929
N1.C2.D0.R1.S05: Total Delay in PI ticks: TxDQS = 939, TxDQ = 903
N3.C2.D0.R1.S12: Total Delay in PI ticks: TxDQ = 910
N5.C0.D0.R0.S13: RdPtrOffsetTxDqs: 06
N7.C2.D0.R1.S03: Total Delay in PI ticks: TxDQS = 945, TxDQ = 911
N1.C2.D0.R1.S06: Total Delay in PI ticks: TxDQS = 936, TxDQ = 901
N3.C2.D0.R1.S13: Total Delay in PI ticks: TxDQ = 872
N5.C0.D0.R0.S13: PiTxDqs: 19
N7.C2.D0.R1.S04: Total Delay in PI ticks: TxDQS = 905, TxDQ = 871
N1.C2.D0.R1.S07: Total Delay in PI ticks: TxDQS = 959, TxDQ = 925
N3.C2.D0.R1.S14: Total Delay in PI ticks: TxDQ = 899
N5.C0.D0.R0.S14: wrcmd2dqsstartlatency: 04
N7.C2.D0.R1.S05: Total Delay in PI ticks: TxDQS = 934, TxDQ = 899
N1.C2.D0.R1.S08: Total Delay in PI ticks: TxDQS = 921, TxDQ = 887
N3.C2.D0.R1.S15: Total Delay in PI ticks: TxDQ = 902
N5.C0.D0.R0.S14: RdPtrOffsetTxDq: 05
N7.C2.D0.R1.S06: Total Delay in PI ticks: TxDQS = 932, TxDQ = 897
N1.C2.D0.R1.S09: Total Delay in PI ticks: TxDQS = 991, TxDQ = 956
N3.C2.D0.R1.S16: Total Delay in PI ticks: TxDQ = 923
N5.C0.D0.R0.S14: RdPtrOffsetTxDqs: 06
N7.C2.D0.R1.S07: Total Delay in PI ticks: TxDQS = 955, TxDQ = 924
N1.C2.D0.R1.S10: Total Delay in PI ticks: TxDQS = 978, TxDQ = 945
N3.C2.D0.R1.S17: Total Delay in PI ticks: TxDQ = 885
N5.C0.D0.R0.S14: PiTxDqs: 35
N7.C2.D0.R1.S08: Total Delay in PI ticks: TxDQS = 920, TxDQ = 886
N1.C2.D0.R1.S11: Total Delay in PI ticks: TxDQS = 966, TxDQ = 932
N3.C2: Calculating Optimimum DQ/DQS Values
N5.C0.D0.R0.S15: wrcmd2dqsstartlatency: 04
N7.C2.D0.R1.S09: Total Delay in PI ticks: TxDQS = 987, TxDQ = 955
N1.C2.D0.R1.S12: Total Delay in PI ticks: TxDQS = 950, TxDQ = 915
START_DATA_TX_DQ
N5.C0.D0.R0.S15: RdPtrOffsetTxDq: 05
N7.C2.D0.R1.S10: Total Delay in PI ticks: TxDQS = 976, TxDQ = 941
N1.C2.D0.R1.S13: Total Delay in PI ticks: TxDQS = 911, TxDQ = 878
N3.C2.S00: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 009
N5.C0.D0.R0.S15: RdPtrOffsetTxDqs: 06
N7.C2.D0.R1.S11: Total Delay in PI ticks: TxDQS = 965, TxDQ = 933
N1.C2.D0.R1.S14: Total Delay in PI ticks: TxDQS = 938, TxDQ = 902
N3.C2.S00: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 009
N5.C0.D0.R0.S15: PiTxDqs: 42
N7.C2.D0.R1.S12: Total Delay in PI ticks: TxDQS = 947, TxDQ = 911
N1.C2.D0.R1.S15: Total Delay in PI ticks: TxDQS = 938, TxDQ = 903
N3.C2.S01: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 009
N5.C0.D0.R0.S16: wrcmd2dqsstartlatency: 04
N7.C2.D0.R1.S13: Total Delay in PI ticks: TxDQS = 904, TxDQ = 872
N1.C2.D0.R1.S16: Total Delay in PI ticks: TxDQS = 960, TxDQ = 928
N3.C2.S01: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 009
N5.C0.D0.R0.S16: RdPtrOffsetTxDq: 05
N7.C2.D0.R1.S14: Total Delay in PI ticks: TxDQS = 933, TxDQ = 898
N1.C2.D0.R1.S17: Total Delay in PI ticks: TxDQS = 923, TxDQ = 888
N3.C2.S02: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 009
N5.C0.D0.R0.S16: RdPtrOffsetTxDqs: 06
N7.C2.D0.R1.S15: Total Delay in PI ticks: TxDQS = 935, TxDQ = 906
N1.C3.D0.R0: Write Training Coarse, lower nibbles / bytes
N3.C2.S02: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 009
N5.C0.D0.R0.S16: PiTxDqs: 58
N7.C2.D0.R1.S16: Total Delay in PI ticks: TxDQS = 955, TxDQ = 928
N1.C3.D0.R0.S00: Dq Delay estimate: 453
N3.C2.S03: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 008
N5.C0.D0.R0.S17: wrcmd2dqsstartlatency: 04
N7.C2.D0.R1.S17: Total Delay in PI ticks: TxDQS = 920, TxDQ = 883
N1.C3.D0.R0.S01: Dq Delay estimate: 436
N3.C2.S03: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 008
N5.C0.D0.R0.S17: RdPtrOffsetTxDq: 04
N7.C3.D0.R0: Write Training Coarse, lower nibbles / bytes
N1.C3.D0.R0.S02: Dq Delay estimate: 425
N3.C2.S04: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 007, RdPtrOffsetTxDqs = 008
N5.C0.D0.R0.S17: RdPtrOffsetTxDqs: 06
N7.C3.D0.R0.S00: Dq Delay estimate: 464
N1.C3.D0.R0.S03: Dq Delay estimate: 407
N3.C2.S04: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 007, RdPtrOffsetTxDqs = 008
N5.C0.D0.R0.S17: PiTxDqs: 26
N7.C3.D0.R0.S01: Dq Delay estimate: 449
N1.C3.D0.R0.S04: Dq Delay estimate: 374
N3.C2.S05: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 008
N5.C0.D0.R0.S00: RdPtrOffsetTxDq: 06
N7.C3.D0.R0.S02: Dq Delay estimate: 431
N1.C3.D0.R0.S05: Dq Delay estimate: 386
N3.C2.S05: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 008
N5.C0.D0.R0.S01: RdPtrOffsetTxDq: 06
N7.C3.D0.R0.S03: Dq Delay estimate: 419
N1.C3.D0.R0.S06: Dq Delay estimate: 400
N3.C2.S06: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 008
N5.C0.D0.R0.S02: RdPtrOffsetTxDq: 06
N7.C3.D0.R0.S04: Dq Delay estimate: 380
N1.C3.D0.R0.S07: Dq Delay estimate: 421
N3.C2.S06: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 008
N5.C0.D0.R0.S03: RdPtrOffsetTxDq: 06
N7.C3.D0.R0.S05: Dq Delay estimate: 396
N1.C3.D0.R0.S08: Dq Delay estimate: 389
N3.C2.S07: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 008
N5.C0.D0.R0.S04: RdPtrOffsetTxDq: 05
N7.C3.D0.R0.S06: Dq Delay estimate: 411
ACCM: 0F 0F9F9F0F FF0F0F0F
N3.C2.S07: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 008
N5.C0.D0.R0.S05: RdPtrOffsetTxDq: 06
N7.C3.D0.R0.S07: Dq Delay estimate: 430
ACCM: 0F 0F9F9F0F FF0F0F0F
N3.C2.S08: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 007, RdPtrOffsetTxDqs = 008
N5.C0.D0.R0.S06: RdPtrOffsetTxDq: 06
N7.C3.D0.R0.S08: Dq Delay estimate: 399
ACCM: 0F FF9F9F0F FFFFFFFF
N3.C2.S08: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 007, RdPtrOffsetTxDqs = 008
N5.C0.D0.R0.S07: RdPtrOffsetTxDq: 06
ACCM: 9F 0F0F9F0F 0F0F0F0F
ACCM: 0F FF9F9F0F FFFFFFFF
N3.C2.D0.R0.S00: TxDqs: plus1 = 1, minus1 = 0, PI = 29, DB = 0
N5.C0.D0.R0.S08: RdPtrOffsetTxDq: 05
ACCM: 9F 0F0F9F0F 0F0F0F0F
N1.C3.D0.R0: CheckMCTest: result = 0x1DFFF
N3.C2.D0.R0.S00: TxDq : plus1 = 1, minus1 = 0, PI = 60, DB = 1
N5.C0.D0.R0.S09: RdPtrOffsetTxDq: 06
ACCM: 9F FFFF9F0F FFFFFFFF
ACCM: 0F 0FDF9F0F FF0F0F0F
N3.C2.D0.R0.S01: TxDqs: plus1 = 1, minus1 = 0, PI = 11, DB = 1
N5.C0.D0.R0.S10: RdPtrOffsetTxDq: 06
ACCM: 9F FFFF9F0F FFFFFFFF
ACCM: 0F 0FDF9F0F FF0F0F0F
N3.C2.D0.R0.S01: TxDq : plus1 = 1, minus1 = 0, PI = 41, DB = 0
N5.C0.D0.R0.S11: RdPtrOffsetTxDq: 06
N7.C3.D0.R0: CheckMCTest: result = 0x3DFFF
ACCM: 0F FFDF9F0F FFFFFFFF
N3.C2.D0.R0.S02: TxDqs: plus1 = 1, minus1 = 0, PI = 01, DB = 1
N5.C0.D0.R0.S12: RdPtrOffsetTxDq: 06
ACCM: DF 0F0FDF0F 0F0F0F0F
ACCM: 0F FFDF9F0F FFFFFFFF
N3.C2.D0.R0.S02: TxDq : plus1 = 1, minus1 = 0, PI = 33, DB = 0
N5.C0.D0.R0.S13: RdPtrOffsetTxDq: 05
ACCM: DF 0F0FDF0F 0F0F0F0F
N1.C3.D0.R0: CheckMCTest: result = 0x1DFFF
N3.C2.D0.R0.S03: TxDqs: plus1 = 1, minus1 = 0, PI = 47, DB = 0
N5.C0.D0.R0.S14: RdPtrOffsetTxDq: 06
ACCM: DF FFFFDF0F FFFFFFFF
ACCM: 0F 0FDFDF0F DF0F0F0F
N3.C2.D0.R0.S03: TxDq : plus1 = 1, minus1 = 0, PI = 13, DB = 1
N5.C0.D0.R0.S15: RdPtrOffsetTxDq: 06
ACCM: DF FFFFDF0F FFFFFFFF
ACCM: 0F 0FDFDF0F DF0F0F0F
N3.C2.D0.R0.S04: TxDqs: plus1 = 1, minus1 = 0, PI = 08, DB = 1
N5.C0.D0.R0.S16: RdPtrOffsetTxDq: 06
N7.C3.D0.R0: CheckMCTest: result = 0x3DFFF
ACCM: 0B F0D0DB0B F0FBF0F0
N3.C2.D0.R0.S04: TxDq : plus1 = 1, minus1 = 0, PI = 41, DB = 0
N5.C0.D0.R0.S17: RdPtrOffsetTxDq: 05
ACCM: DF 0F0FDF0F 0F0F0F0F
ACCM: 0B F0D0DB0B F0FBF0F0
N3.C2.D0.R0.S05: TxDqs: plus1 = 1, minus1 = 0, PI = 38, DB = 0
N5.C0.D0.R0.S00: RdPtrOffsetTxDq: 07
ACCM: DF 0F0FDF0F 0F0F0F0F
N1.C3.D0.R0: CheckMCTest: result = 0x1DFFF
N3.C2.D0.R0.S05: TxDq : plus1 = 1, minus1 = 0, PI = 04, DB = 1
N5.C0.D0.R0.S01: RdPtrOffsetTxDq: 07
ACCM: D0 F0FBDB00 F0F0F0F0
ACCM: 0F 0FDFDF0F DF0F0F0F
N3.C2.D0.R0.S06: TxDqs: plus1 = 1, minus1 = 0, PI = 38, DB = 0
N5.C0.D0.R0.S02: RdPtrOffsetTxDq: 07
ACCM: D0 F0FBDB00 F0F0F0F0
ACCM: 0F 0FDFDF0F DF0F0F0F
N3.C2.D0.R0.S06: TxDq : plus1 = 1, minus1 = 0, PI = 04, DB = 1
N5.C0.D0.R0.S03: RdPtrOffsetTxDq: 07
N7.C3.D0.R0: CheckMCTest: result = 0x3DFFF
ACCM: 0F F0D0DF0F F0FFF0F0
N3.C2.D0.R0.S07: TxDqs: plus1 = 1, minus1 = 0, PI = 58, DB = 1
N5.C0.D0.R0.S04: RdPtrOffsetTxDq: 06
ACCM: DF 0FDFDF0F 0F0F0F0F
ACCM: 0F F0D0DF0F F0FFF0F0
N3.C2.D0.R0.S07: TxDq : plus1 = 1, minus1 = 0, PI = 24, DB = 0
N5.C0.D0.R0.S05: RdPtrOffsetTxDq: 07
ACCM: DF 0FDFDF0F 0F0F0F0F
N1.C3.D0.R0: CheckMCTest: result = 0x1DFFF
N3.C2.D0.R0.S08: TxDqs: plus1 = 1, minus1 = 0, PI = 24, DB = 0
N5.C0.D0.R0.S06: RdPtrOffsetTxDq: 07
ACCM: D0 F0FFDF00 F0F0F0F0
ACCM: 00 00D0D000 D0000000
N3.C2.D0.R0.S08: TxDq : plus1 = 1, minus1 = 0, PI = 52, DB = 1
N5.C0.D0.R0.S07: RdPtrOffsetTxDq: 07
ACCM: D0 F0FFDF00 F0F0F0F0
ACCM: 00 00D0D000 D0000000
N3.C2.D0.R0.S09: TxDqs: plus1 = 1, minus1 = 0, PI = 26, DB = 0
N5.C0.D0.R0.S08: RdPtrOffsetTxDq: 06
N7.C3.D0.R0: CheckMCTest: result = 0x3DFFF
ACCM: 00 F0D0D000 F0F0F0F0
N3.C2.D0.R0.S09: TxDq : plus1 = 1, minus1 = 0, PI = 57, DB = 1
N5.C0.D0.R0.S09: RdPtrOffsetTxDq: 07
ACCM: D0 00D0D000 00000000
ACCM: 00 F0D0D000 F0F0F0F0
N3.C2.D0.R0.S10: TxDqs: plus1 = 1, minus1 = 0, PI = 14, DB = 1
N5.C0.D0.R0.S10: RdPtrOffsetTxDq: 07
ACCM: D0 00D0D000 00000000
N1.C3.D0.R0: CheckMCTest: result = 0x1DE00
N3.C2.D0.R0.S10: TxDq : plus1 = 1, minus1 = 0, PI = 42, DB = 0
N5.C0.D0.R0.S11: RdPtrOffsetTxDq: 07
ACCM: D0 F0F0D000 F0F0F0F0
ACCM: 00 00D0D000 D0000000
N3.C2.D0.R0.S11: TxDqs: plus1 = 1, minus1 = 0, PI = 03, DB = 1
N5.C0.D0.R0.S12: RdPtrOffsetTxDq: 07
ACCM: D0 F0F0D000 F0F0F0F0
ACCM: 00 00D0D000 D0000000
N3.C2.D0.R0.S11: TxDq : plus1 = 1, minus1 = 0, PI = 34, DB = 0
N5.C0.D0.R0.S13: RdPtrOffsetTxDq: 06
N7.C3.D0.R0: CheckMCTest: result = 0x3DE00
ACCM: 00 F0D0D000 F0F0F0F0
N3.C2.D0.R0.S12: TxDqs: plus1 = 1, minus1 = 0, PI = 49, DB = 1
N5.C0.D0.R0.S14: RdPtrOffsetTxDq: 07
ACCM: D0 00D0D000 00000000
ACCM: 00 F0D0D000 F0F0F0F0
N3.C2.D0.R0.S12: TxDq : plus1 = 1, minus1 = 0, PI = 13, DB = 1
N5.C0.D0.R0.S15: RdPtrOffsetTxDq: 07
ACCM: D0 00D0D000 00000000
N1.C3.D0.R0: CheckMCTest: result = 0x1DE00
N3.C2.D0.R0.S13: TxDqs: plus1 = 1, minus1 = 0, PI = 08, DB = 1
N5.C0.D0.R0.S16: RdPtrOffsetTxDq: 07
ACCM: D0 F0F0D000 F0F0F0F0
N1.C3.D0.R0.S00: Offset Found: RdPtrOffsetDqs = 007
N3.C2.D0.R0.S13: TxDq : plus1 = 1, minus1 = 0, PI = 40, DB = 0
N5.C0.D0.R0.S17: RdPtrOffsetTxDq: 06
ACCM: D0 F0F0D000 F0F0F0F0
N1.C3.D0.R0.S01: Offset Found: RdPtrOffsetDqs = 007
N3.C2.D0.R0.S14: TxDqs: plus1 = 1, minus1 = 0, PI = 36, DB = 0
N5.C0.D0.R0.S00: Total Delay in PI ticks: TxDQ = 959
N7.C3.D0.R0: CheckMCTest: result = 0x3DE00
N1.C3.D0.R0.S02: Offset Found: RdPtrOffsetDqs = 007
N3.C2.D0.R0.S14: TxDq : plus1 = 1, minus1 = 0, PI = 03, DB = 1
N5.C0.D0.R0.S01: Total Delay in PI ticks: TxDQ = 945
N7.C3.D0.R0.S00: Offset Found: RdPtrOffsetDqs = 007
N1.C3.D0.R0.S03: Offset Found: RdPtrOffsetDqs = 006
N3.C2.D0.R0.S15: TxDqs: plus1 = 1, minus1 = 0, PI = 38, DB = 0
N5.C0.D0.R0.S02: Total Delay in PI ticks: TxDQ = 931
N7.C3.D0.R0.S01: Offset Found: RdPtrOffsetDqs = 007
N1.C3.D0.R0.S04: Offset Found: RdPtrOffsetDqs = 006
N3.C2.D0.R0.S15: TxDq : plus1 = 1, minus1 = 0, PI = 05, DB = 1
N5.C0.D0.R0.S03: Total Delay in PI ticks: TxDQ = 913
N7.C3.D0.R0.S02: Offset Found: RdPtrOffsetDqs = 007
N1.C3.D0.R0.S05: Offset Found: RdPtrOffsetDqs = 006
N3.C2.D0.R0.S16: TxDqs: plus1 = 1, minus1 = 0, PI = 61, DB = 1
N5.C0.D0.R0.S04: Total Delay in PI ticks: TxDQ = 883
N7.C3.D0.R0.S03: Offset Found: RdPtrOffsetDqs = 007
N1.C3.D0.R0.S06: Offset Found: RdPtrOffsetDqs = 006
N3.C2.D0.R0.S16: TxDq : plus1 = 1, minus1 = 0, PI = 26, DB = 0
N5.C0.D0.R0.S05: Total Delay in PI ticks: TxDQ = 898
N7.C3.D0.R0.S04: Offset Found: RdPtrOffsetDqs = 006
N1.C3.D0.R0.S07: Offset Found: RdPtrOffsetDqs = 007
N3.C2.D0.R0.S17: TxDqs: plus1 = 1, minus1 = 0, PI = 24, DB = 0
N5.C0.D0.R0.S06: Total Delay in PI ticks: TxDQ = 903
N7.C3.D0.R0.S05: Offset Found: RdPtrOffsetDqs = 006
N1.C3.D0.R0.S08: Offset Found: RdPtrOffsetDqs = 006
N3.C2.D0.R0.S17: TxDq : plus1 = 1, minus1 = 0, PI = 53, DB = 1
N5.C0.D0.R0.S07: Total Delay in PI ticks: TxDQ = 922
N7.C3.D0.R0.S06: Offset Found: RdPtrOffsetDqs = 006
N1.C3.D0.R0: Write Training Coarse, upper nibbles
N3.C2.D0.R1.S00: TxDqs: plus1 = 1, minus1 = 0, PI = 29, DB = 0
N5.C0.D0.R0.S08: Total Delay in PI ticks: TxDQ = 886
N7.C3.D0.R0.S07: Offset Found: RdPtrOffsetDqs = 007
N1.C3.D0.R0.S09: Dq Delay estimate: 452
N3.C2.D0.R1.S00: TxDq : plus1 = 1, minus1 = 0, PI = 60, DB = 1
N5.C0.D0.R0.S09: Total Delay in PI ticks: TxDQ = 960
N7.C3.D0.R0.S08: Offset Found: RdPtrOffsetDqs = 006
N1.C3.D0.R0.S10: Dq Delay estimate: 436
N3.C2.D0.R1.S01: TxDqs: plus1 = 1, minus1 = 0, PI = 11, DB = 1
N5.C0.D0.R0.S10: Total Delay in PI ticks: TxDQ = 945
N7.C3.D0.R0: Write Training Coarse, upper nibbles
N1.C3.D0.R0.S11: Dq Delay estimate: 425
N3.C2.D0.R1.S01: TxDq : plus1 = 1, minus1 = 0, PI = 41, DB = 0
N5.C0.D0.R0.S11: Total Delay in PI ticks: TxDQ = 933
N7.C3.D0.R0.S09: Dq Delay estimate: 460
N1.C3.D0.R0.S12: Dq Delay estimate: 410
N3.C2.D0.R1.S02: TxDqs: plus1 = 1, minus1 = 0, PI = 01, DB = 1
N5.C0.D0.R0.S12: Total Delay in PI ticks: TxDQ = 914
N7.C3.D0.R0.S10: Dq Delay estimate: 447
N1.C3.D0.R0.S13: Dq Delay estimate: 372
N3.C2.D0.R1.S02: TxDq : plus1 = 1, minus1 = 0, PI = 33, DB = 0
N5.C0.D0.R0.S13: Total Delay in PI ticks: TxDQ = 882
N7.C3.D0.R0.S11: Dq Delay estimate: 436
N1.C3.D0.R0.S14: Dq Delay estimate: 385
N3.C2.D0.R1.S03: TxDqs: plus1 = 1, minus1 = 0, PI = 47, DB = 0
N5.C0.D0.R0.S14: Total Delay in PI ticks: TxDQ = 900
N7.C3.D0.R0.S12: Dq Delay estimate: 421
N1.C3.D0.R0.S15: Dq Delay estimate: 400
N3.C2.D0.R1.S03: TxDq : plus1 = 1, minus1 = 0, PI = 13, DB = 1
N5.C0.D0.R0.S15: Total Delay in PI ticks: TxDQ = 904
N7.C3.D0.R0.S13: Dq Delay estimate: 382
N1.C3.D0.R0.S16: Dq Delay estimate: 421
N3.C2.D0.R1.S04: TxDqs: plus1 = 1, minus1 = 0, PI = 08, DB = 1
N5.C0.D0.R0.S16: Total Delay in PI ticks: TxDQ = 921
N7.C3.D0.R0.S14: Dq Delay estimate: 398
N1.C3.D0.R0.S17: Dq Delay estimate: 385
N3.C2.D0.R1.S04: TxDq : plus1 = 1, minus1 = 0, PI = 41, DB = 0
N5.C0.D0.R0.S17: Total Delay in PI ticks: TxDQ = 887
N7.C3.D0.R0.S15: Dq Delay estimate: 412
ACCM: F0 F0F0F0F0 F0F0F0F0
N3.C2.D0.R1.S05: TxDqs: plus1 = 1, minus1 = 0, PI = 38, DB = 0
N5.C0.D0.R1.S00: wrcmd2dqsstartlatency: 04
N7.C3.D0.R0.S16: Dq Delay estimate: 431
ACCM: F0 F0F0F0F0 F0F0F0F0
N3.C2.D0.R1.S05: TxDq : plus1 = 1, minus1 = 0, PI = 04, DB = 1
N5.C0.D0.R1.S00: RdPtrOffsetTxDq: 06
N7.C3.D0.R0.S17: Dq Delay estimate: 397
ACCM: F0 F0F0F0F0 F0F0F0F0
N3.C2.D0.R1.S06: TxDqs: plus1 = 1, minus1 = 0, PI = 38, DB = 0
N5.C0.D0.R1.S00: RdPtrOffsetTxDqs: 07
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: F0 F0F0F0F0 F0F0F0F0
N3.C2.D0.R1.S06: TxDq : plus1 = 1, minus1 = 0, PI = 04, DB = 1
N5.C0.D0.R1.S00: PiTxDqs: 33
ACCM: F0 F0F0F0F0 F0F0F0F0
N1.C3.D0.R0: CheckMCTest: result = 0x3FE00
N3.C2.D0.R1.S07: TxDqs: plus1 = 1, minus1 = 0, PI = 58, DB = 1
N5.C0.D0.R1.S01: wrcmd2dqsstartlatency: 04
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: F0 F0F0F0F0 F0F0F0F0
N3.C2.D0.R1.S07: TxDq : plus1 = 1, minus1 = 0, PI = 24, DB = 0
N5.C0.D0.R1.S01: RdPtrOffsetTxDq: 05
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: F0 F0F0F0F0 F0F0F0F0
N3.C2.D0.R1.S08: TxDqs: plus1 = 1, minus1 = 0, PI = 24, DB = 0
N5.C0.D0.R1.S01: RdPtrOffsetTxDqs: 07
N7.C3.D0.R0: CheckMCTest: result = 0x3FE00
ACCM: F0 F0F0F0F0 F0F0F0F0
N3.C2.D0.R1.S08: TxDq : plus1 = 1, minus1 = 0, PI = 52, DB = 1
N5.C0.D0.R1.S01: PiTxDqs: 18
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: F0 F0F0F0F0 F0F0F0F0
N3.C2.D0.R1.S09: TxDqs: plus1 = 1, minus1 = 0, PI = 26, DB = 0
N5.C0.D0.R1.S02: wrcmd2dqsstartlatency: 04
ACCM: F0 F0F0F0F0 F0F0F0F0
N1.C3.D0.R0: CheckMCTest: result = 0x3FE00
N3.C2.D0.R1.S09: TxDq : plus1 = 1, minus1 = 0, PI = 57, DB = 1
N5.C0.D0.R1.S02: RdPtrOffsetTxDq: 05
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: F0 F0F0F0F0 F0F0F0F0
N3.C2.D0.R1.S10: TxDqs: plus1 = 1, minus1 = 0, PI = 14, DB = 1
N5.C0.D0.R1.S02: RdPtrOffsetTxDqs: 07
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: F0 F0F0F0F0 F0F0F0F0
N3.C2.D0.R1.S10: TxDq : plus1 = 1, minus1 = 0, PI = 42, DB = 0
N5.C0.D0.R1.S02: PiTxDqs: 02
N7.C3.D0.R0: CheckMCTest: result = 0x3FE00
ACCM: 00 00000000 00000000
N3.C2.D0.R1.S11: TxDqs: plus1 = 1, minus1 = 0, PI = 03, DB = 1
N5.C0.D0.R1.S03: wrcmd2dqsstartlatency: 04
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: 00 00000000 00000000
N3.C2.D0.R1.S11: TxDq : plus1 = 1, minus1 = 0, PI = 34, DB = 0
N5.C0.D0.R1.S03: RdPtrOffsetTxDq: 05
ACCM: F0 F0F0F0F0 F0F0F0F0
N1.C3.D0.R0: CheckMCTest: result = 0x3FE00
N3.C2.D0.R1.S12: TxDqs: plus1 = 1, minus1 = 0, PI = 49, DB = 1
N5.C0.D0.R1.S03: RdPtrOffsetTxDqs: 06
ACCM: 00 00000000 00000000
ACCM: F0 F0F0F0F0 F0F0F0F0
N3.C2.D0.R1.S12: TxDq : plus1 = 1, minus1 = 0, PI = 13, DB = 1
N5.C0.D0.R1.S03: PiTxDqs: 53
ACCM: 00 00000000 00000000
ACCM: F0 F0F0F0F0 F0F0F0F0
N3.C2.D0.R1.S13: TxDqs: plus1 = 1, minus1 = 0, PI = 08, DB = 1
N5.C0.D0.R1.S04: wrcmd2dqsstartlatency: 04
N7.C3.D0.R0: CheckMCTest: result = 0x3FE00
ACCM: 00 00000000 00000000
N3.C2.D0.R1.S13: TxDq : plus1 = 1, minus1 = 0, PI = 40, DB = 0
N5.C0.D0.R1.S04: RdPtrOffsetTxDq: 04
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: 00 00000000 00000000
N3.C2.D0.R1.S14: TxDqs: plus1 = 1, minus1 = 0, PI = 36, DB = 0
N5.C0.D0.R1.S04: RdPtrOffsetTxDqs: 06
ACCM: F0 F0F0F0F0 F0F0F0F0
N1.C3.D0.R0: CheckMCTest: result = 0x3FE00
N3.C2.D0.R1.S14: TxDq : plus1 = 1, minus1 = 0, PI = 03, DB = 1
N5.C0.D0.R1.S04: PiTxDqs: 17
ACCM: 00 00000000 00000000
N1.C3.D0.R0: CheckMCTest: passed
N3.C2.D0.R1.S15: TxDqs: plus1 = 1, minus1 = 0, PI = 38, DB = 0
N5.C0.D0.R1.S05: wrcmd2dqsstartlatency: 04
ACCM: 00 00000000 00000000
N1.C3.D0.R0: CheckMCTest: passed
N3.C2.D0.R1.S15: TxDq : plus1 = 1, minus1 = 0, PI = 05, DB = 1
N5.C0.D0.R1.S05: RdPtrOffsetTxDq: 05
N7.C3.D0.R0: CheckMCTest: result = 0x3FE00
N1.C3.D0.R0.S09: Offset Found: RdPtrOffsetDqs = 007
N3.C2.D0.R1.S16: TxDqs: plus1 = 1, minus1 = 0, PI = 61, DB = 1
N5.C0.D0.R1.S05: RdPtrOffsetTxDqs: 06
N7.C3.D0.R0: CheckMCTest: passed
N1.C3.D0.R0.S10: Offset Found: RdPtrOffsetDqs = 007
N3.C2.D0.R1.S16: TxDq : plus1 = 1, minus1 = 0, PI = 26, DB = 0
N5.C0.D0.R1.S05: PiTxDqs: 35
N7.C3.D0.R0: CheckMCTest: passed
N1.C3.D0.R0.S11: Offset Found: RdPtrOffsetDqs = 007
N3.C2.D0.R1.S17: TxDqs: plus1 = 1, minus1 = 0, PI = 24, DB = 0
N5.C0.D0.R1.S06: wrcmd2dqsstartlatency: 04
N7.C3.D0.R0.S09: Offset Found: RdPtrOffsetDqs = 007
N1.C3.D0.R0.S12: Offset Found: RdPtrOffsetDqs = 006
N3.C2.D0.R1.S17: TxDq : plus1 = 1, minus1 = 0, PI = 53, DB = 1
N5.C0.D0.R1.S06: RdPtrOffsetTxDq: 05
N7.C3.D0.R0.S10: Offset Found: RdPtrOffsetDqs = 007
N1.C3.D0.R0.S13: Offset Found: RdPtrOffsetDqs = 006
END_DATA_TX_DQ
N5.C0.D0.R1.S06: RdPtrOffsetTxDqs: 06
N7.C3.D0.R0.S11: Offset Found: RdPtrOffsetDqs = 007
N1.C3.D0.R0.S14: Offset Found: RdPtrOffsetDqs = 006
N3.C3.D0.R0.S00: wrcmd2dqsstartlatency: 04
N5.C0.D0.R1.S06: PiTxDqs: 42
N7.C3.D0.R0.S12: Offset Found: RdPtrOffsetDqs = 007
N1.C3.D0.R0.S15: Offset Found: RdPtrOffsetDqs = 006
N3.C3.D0.R0.S00: RdPtrOffsetTxDq: 06
N5.C0.D0.R1.S07: wrcmd2dqsstartlatency: 04
N7.C3.D0.R0.S13: Offset Found: RdPtrOffsetDqs = 006
N1.C3.D0.R0.S16: Offset Found: RdPtrOffsetDqs = 007
N3.C3.D0.R0.S00: RdPtrOffsetTxDqs: 07
N5.C0.D0.R1.S07: RdPtrOffsetTxDq: 05
N7.C3.D0.R0.S14: Offset Found: RdPtrOffsetDqs = 006
N1.C3.D0.R0.S17: Offset Found: RdPtrOffsetDqs = 006
N3.C3.D0.R0.S00: PiTxDqs: 39
N5.C0.D0.R1.S07: RdPtrOffsetTxDqs: 06
N7.C3.D0.R0.S15: Offset Found: RdPtrOffsetDqs = 006
N1.C3.D0.R1: Write Training Coarse, lower nibbles / bytes
N3.C3.D0.R0.S01: wrcmd2dqsstartlatency: 04
N5.C0.D0.R1.S07: PiTxDqs: 57
N7.C3.D0.R0.S16: Offset Found: RdPtrOffsetDqs = 007
N1.C3.D0.R1.S00: Dq Delay estimate: 452
N3.C3.D0.R0.S01: RdPtrOffsetTxDq: 05
N5.C0.D0.R1.S08: wrcmd2dqsstartlatency: 04
N7.C3.D0.R0.S17: Offset Found: RdPtrOffsetDqs = 006
N1.C3.D0.R1.S01: Dq Delay estimate: 433
N3.C3.D0.R0.S01: RdPtrOffsetTxDqs: 07
N5.C0.D0.R1.S08: RdPtrOffsetTxDq: 04
N7.C3.D0.R1: Write Training Coarse, lower nibbles / bytes
N1.C3.D0.R1.S02: Dq Delay estimate: 423
N3.C3.D0.R0.S01: PiTxDqs: 20
N5.C0.D0.R1.S08: RdPtrOffsetTxDqs: 06
N7.C3.D0.R1.S00: Dq Delay estimate: 463
N1.C3.D0.R1.S03: Dq Delay estimate: 406
N3.C3.D0.R0.S02: wrcmd2dqsstartlatency: 04
N5.C0.D0.R1.S08: PiTxDqs: 26
N7.C3.D0.R1.S01: Dq Delay estimate: 446
N1.C3.D0.R1.S04: Dq Delay estimate: 375
N3.C3.D0.R0.S02: RdPtrOffsetTxDq: 05
N5.C0.D0.R1.S09: wrcmd2dqsstartlatency: 04
N7.C3.D0.R1.S02: Dq Delay estimate: 431
N1.C3.D0.R1.S05: Dq Delay estimate: 384
N3.C3.D0.R0.S02: RdPtrOffsetTxDqs: 07
N5.C0.D0.R1.S09: RdPtrOffsetTxDq: 05
N7.C3.D0.R1.S03: Dq Delay estimate: 419
N1.C3.D0.R1.S06: Dq Delay estimate: 401
N3.C3.D0.R0.S02: PiTxDqs: 11
N5.C0.D0.R1.S09: RdPtrOffsetTxDqs: 07
N7.C3.D0.R1.S04: Dq Delay estimate: 381
N1.C3.D0.R1.S07: Dq Delay estimate: 420
N3.C3.D0.R0.S03: wrcmd2dqsstartlatency: 04
N5.C0.D0.R1.S09: PiTxDqs: 33
N7.C3.D0.R1.S05: Dq Delay estimate: 397
N1.C3.D0.R1.S08: Dq Delay estimate: 385
N3.C3.D0.R0.S03: RdPtrOffsetTxDq: 05
N5.C0.D0.R1.S10: wrcmd2dqsstartlatency: 04
N7.C3.D0.R1.S06: Dq Delay estimate: 410
ACCM: 0F 0F0F0F0F 0F0F0F0F
N3.C3.D0.R0.S03: RdPtrOffsetTxDqs: 06
N5.C0.D0.R1.S10: RdPtrOffsetTxDq: 05
N7.C3.D0.R1.S07: Dq Delay estimate: 431
ACCM: 0F 0F0F0F0F 0F0F0F0F
N3.C3.D0.R0.S03: PiTxDqs: 59
N5.C0.D0.R1.S10: RdPtrOffsetTxDqs: 07
N7.C3.D0.R1.S08: Dq Delay estimate: 398
ACCM: 0F 0F0F0F0F 0F0F0F0F
N3.C3.D0.R0.S04: wrcmd2dqsstartlatency: 04
N5.C0.D0.R1.S10: PiTxDqs: 16
ACCM: 0F 0F0F0F0F 0F0F0F0F
ACCM: 0F 0F0F0F0F 0F0F0F0F
N3.C3.D0.R0.S04: RdPtrOffsetTxDq: 04
N5.C0.D0.R1.S11: wrcmd2dqsstartlatency: 04
ACCM: 0F 0F0F0F0F 0F0F0F0F
N1.C3.D0.R1: CheckMCTest: result = 0x1FF
N3.C3.D0.R0.S04: RdPtrOffsetTxDqs: 06
N5.C0.D0.R1.S11: RdPtrOffsetTxDq: 05
ACCM: 0F 0F0F0F0F 0F0F0F0F
ACCM: 0F 0F0F0F0F 0F0F0F0F
N3.C3.D0.R0.S04: PiTxDqs: 24
N5.C0.D0.R1.S11: RdPtrOffsetTxDqs: 07
ACCM: 0F 0F0F0F0F 0F0F0F0F
ACCM: 0F 0F0F0F0F 0F0F0F0F
N3.C3.D0.R0.S05: wrcmd2dqsstartlatency: 04
N5.C0.D0.R1.S11: PiTxDqs: 06
N7.C3.D0.R1: CheckMCTest: result = 0x1FF
ACCM: 0F 0F0F0F0F 0F0F0F0F
N3.C3.D0.R0.S05: RdPtrOffsetTxDq: 05
N5.C0.D0.R1.S12: wrcmd2dqsstartlatency: 04
ACCM: 0F 0F0F0F0F 0F0F0F0F
ACCM: 0F 0F0F0F0F 0F0F0F0F
N3.C3.D0.R0.S05: RdPtrOffsetTxDqs: 06
N5.C0.D0.R1.S12: RdPtrOffsetTxDq: 05
ACCM: 0F 0F0F0F0F 0F0F0F0F
N1.C3.D0.R1: CheckMCTest: result = 0x1FF
N3.C3.D0.R0.S05: PiTxDqs: 37
N5.C0.D0.R1.S12: RdPtrOffsetTxDqs: 06
ACCM: 0F 0F0F0F0F 0F0F0F0F
ACCM: 0F 0F0F0F0F 0F0F0F0F
N3.C3.D0.R0.S06: wrcmd2dqsstartlatency: 04
N5.C0.D0.R1.S12: PiTxDqs: 49
ACCM: 0F 0F0F0F0F 0F0F0F0F
ACCM: 0F 0F0F0F0F 0F0F0F0F
N3.C3.D0.R0.S06: RdPtrOffsetTxDq: 05
N5.C0.D0.R1.S13: wrcmd2dqsstartlatency: 04
N7.C3.D0.R1: CheckMCTest: result = 0x1FF
ACCM: 00 00000000 00000000
N3.C3.D0.R0.S06: RdPtrOffsetTxDqs: 06
N5.C0.D0.R1.S13: RdPtrOffsetTxDq: 04
ACCM: 0F 0F0F0F0F 0F0F0F0F
ACCM: 00 00000000 00000000
N3.C3.D0.R0.S06: PiTxDqs: 52
N5.C0.D0.R1.S13: RdPtrOffsetTxDqs: 06
ACCM: 0F 0F0F0F0F 0F0F0F0F
N1.C3.D0.R1: CheckMCTest: result = 0x1FF
N3.C3.D0.R0.S07: wrcmd2dqsstartlatency: 04
N5.C0.D0.R1.S13: PiTxDqs: 19
ACCM: 00 00000000 00000000
ACCM: 0F 0F0F0F0F 0F0F0F0F
N3.C3.D0.R0.S07: RdPtrOffsetTxDq: 05
N5.C0.D0.R1.S14: wrcmd2dqsstartlatency: 04
ACCM: 00 00000000 00000000
ACCM: 0F 0F0F0F0F 0F0F0F0F
N3.C3.D0.R0.S07: RdPtrOffsetTxDqs: 07
N5.C0.D0.R1.S14: RdPtrOffsetTxDq: 05
N7.C3.D0.R1: CheckMCTest: result = 0x1FF
ACCM: 00 00000000 00000000
N3.C3.D0.R0.S07: PiTxDqs: 06
N5.C0.D0.R1.S14: RdPtrOffsetTxDqs: 06
ACCM: 0F 0F0F0F0F 0F0F0F0F
ACCM: 00 00000000 00000000
N3.C3.D0.R0.S08: wrcmd2dqsstartlatency: 04
N5.C0.D0.R1.S14: PiTxDqs: 34
ACCM: 0F 0F0F0F0F 0F0F0F0F
N1.C3.D0.R1: CheckMCTest: result = 0x1FF
N3.C3.D0.R0.S08: RdPtrOffsetTxDq: 05
N5.C0.D0.R1.S15: wrcmd2dqsstartlatency: 04
ACCM: 00 00000000 00000000
N1.C3.D0.R1: CheckMCTest: passed
N3.C3.D0.R0.S08: RdPtrOffsetTxDqs: 06
N5.C0.D0.R1.S15: RdPtrOffsetTxDq: 05
ACCM: 00 00000000 00000000
N1.C3.D0.R1: CheckMCTest: passed
N3.C3.D0.R0.S08: PiTxDqs: 37
N5.C0.D0.R1.S15: RdPtrOffsetTxDqs: 06
N7.C3.D0.R1: CheckMCTest: result = 0x1FF
N1.C3.D0.R1.S00: Offset Found: RdPtrOffsetDqs = 007
N3.C3.D0.R0.S09: wrcmd2dqsstartlatency: 04
N5.C0.D0.R1.S15: PiTxDqs: 42
N7.C3.D0.R1: CheckMCTest: passed
N1.C3.D0.R1.S01: Offset Found: RdPtrOffsetDqs = 007
N3.C3.D0.R0.S09: RdPtrOffsetTxDq: 06
N5.C0.D0.R1.S16: wrcmd2dqsstartlatency: 04
N7.C3.D0.R1: CheckMCTest: passed
N1.C3.D0.R1.S02: Offset Found: RdPtrOffsetDqs = 007
N3.C3.D0.R0.S09: RdPtrOffsetTxDqs: 07
N5.C0.D0.R1.S16: RdPtrOffsetTxDq: 05
N7.C3.D0.R1.S00: Offset Found: RdPtrOffsetDqs = 007
N1.C3.D0.R1.S03: Offset Found: RdPtrOffsetDqs = 006
N3.C3.D0.R0.S09: PiTxDqs: 37
N5.C0.D0.R1.S16: RdPtrOffsetTxDqs: 06
N7.C3.D0.R1.S01: Offset Found: RdPtrOffsetDqs = 007
N1.C3.D0.R1.S04: Offset Found: RdPtrOffsetDqs = 006
N3.C3.D0.R0.S10: wrcmd2dqsstartlatency: 04
N5.C0.D0.R1.S16: PiTxDqs: 59
N7.C3.D0.R1.S02: Offset Found: RdPtrOffsetDqs = 007
N1.C3.D0.R1.S05: Offset Found: RdPtrOffsetDqs = 006
N3.C3.D0.R0.S10: RdPtrOffsetTxDq: 05
N5.C0.D0.R1.S17: wrcmd2dqsstartlatency: 04
N7.C3.D0.R1.S03: Offset Found: RdPtrOffsetDqs = 007
N1.C3.D0.R1.S06: Offset Found: RdPtrOffsetDqs = 006
N3.C3.D0.R0.S10: RdPtrOffsetTxDqs: 07
N5.C0.D0.R1.S17: RdPtrOffsetTxDq: 04
N7.C3.D0.R1.S04: Offset Found: RdPtrOffsetDqs = 006
N1.C3.D0.R1.S07: Offset Found: RdPtrOffsetDqs = 007
N3.C3.D0.R0.S10: PiTxDqs: 22
N5.C0.D0.R1.S17: RdPtrOffsetTxDqs: 06
N7.C3.D0.R1.S05: Offset Found: RdPtrOffsetDqs = 006
N1.C3.D0.R1.S08: Offset Found: RdPtrOffsetDqs = 006
N3.C3.D0.R0.S11: wrcmd2dqsstartlatency: 04
N5.C0.D0.R1.S17: PiTxDqs: 26
N7.C3.D0.R1.S06: Offset Found: RdPtrOffsetDqs = 006
N1.C3.D0.R1: Write Training Coarse, upper nibbles
N3.C3.D0.R0.S11: RdPtrOffsetTxDq: 05
N5.C0.D0.R1.S00: RdPtrOffsetTxDq: 07
N7.C3.D0.R1.S07: Offset Found: RdPtrOffsetDqs = 007
N1.C3.D0.R1.S09: Dq Delay estimate: 451
N3.C3.D0.R0.S11: RdPtrOffsetTxDqs: 07
N5.C0.D0.R1.S01: RdPtrOffsetTxDq: 06
N7.C3.D0.R1.S08: Offset Found: RdPtrOffsetDqs = 006
N1.C3.D0.R1.S10: Dq Delay estimate: 435
N3.C3.D0.R0.S11: PiTxDqs: 11
N5.C0.D0.R1.S02: RdPtrOffsetTxDq: 06
N7.C3.D0.R1: Write Training Coarse, upper nibbles
N1.C3.D0.R1.S11: Dq Delay estimate: 425
N3.C3.D0.R0.S12: wrcmd2dqsstartlatency: 04
N5.C0.D0.R1.S03: RdPtrOffsetTxDq: 06
N7.C3.D0.R1.S09: Dq Delay estimate: 458
N1.C3.D0.R1.S12: Dq Delay estimate: 409
N3.C3.D0.R0.S12: RdPtrOffsetTxDq: 05
N5.C0.D0.R1.S04: RdPtrOffsetTxDq: 05
N7.C3.D0.R1.S10: Dq Delay estimate: 445
N1.C3.D0.R1.S13: Dq Delay estimate: 373
N3.C3.D0.R0.S12: RdPtrOffsetTxDqs: 06
N5.C0.D0.R1.S05: RdPtrOffsetTxDq: 06
N7.C3.D0.R1.S11: Dq Delay estimate: 435
N1.C3.D0.R1.S14: Dq Delay estimate: 384
N3.C3.D0.R0.S12: PiTxDqs: 59
N5.C0.D0.R1.S06: RdPtrOffsetTxDq: 06
N7.C3.D0.R1.S12: Dq Delay estimate: 420
N1.C3.D0.R1.S15: Dq Delay estimate: 403
N3.C3.D0.R0.S13: wrcmd2dqsstartlatency: 04
N5.C0.D0.R1.S07: RdPtrOffsetTxDq: 06
N7.C3.D0.R1.S13: Dq Delay estimate: 383
N1.C3.D0.R1.S16: Dq Delay estimate: 420
N3.C3.D0.R0.S13: RdPtrOffsetTxDq: 04
N5.C0.D0.R1.S08: RdPtrOffsetTxDq: 05
N7.C3.D0.R1.S14: Dq Delay estimate: 397
N1.C3.D0.R1.S17: Dq Delay estimate: 387
N3.C3.D0.R0.S13: RdPtrOffsetTxDqs: 06
N5.C0.D0.R1.S09: RdPtrOffsetTxDq: 06
N7.C3.D0.R1.S15: Dq Delay estimate: 411
ACCM: F0 F0F0F0F0 F0F0F0F0
N3.C3.D0.R0.S13: PiTxDqs: 24
N5.C0.D0.R1.S10: RdPtrOffsetTxDq: 06
N7.C3.D0.R1.S16: Dq Delay estimate: 432
ACCM: F0 F0F0F0F0 F0F0F0F0
N3.C3.D0.R0.S14: wrcmd2dqsstartlatency: 04
N5.C0.D0.R1.S11: RdPtrOffsetTxDq: 06
N7.C3.D0.R1.S17: Dq Delay estimate: 397
ACCM: F0 F0F0F0F0 F0F0F0F0
N3.C3.D0.R0.S14: RdPtrOffsetTxDq: 05
N5.C0.D0.R1.S12: RdPtrOffsetTxDq: 06
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: F0 F0F0F0F0 F0F0F0F0
N3.C3.D0.R0.S14: RdPtrOffsetTxDqs: 06
N5.C0.D0.R1.S13: RdPtrOffsetTxDq: 05
ACCM: F0 F0F0F0F0 F0F0F0F0
N1.C3.D0.R1: CheckMCTest: result = 0x3FE00
N3.C3.D0.R0.S14: PiTxDqs: 35
N5.C0.D0.R1.S14: RdPtrOffsetTxDq: 06
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: F0 F0F0F0F0 F0F0F0F0
N3.C3.D0.R0.S15: wrcmd2dqsstartlatency: 04
N5.C0.D0.R1.S15: RdPtrOffsetTxDq: 06
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: F0 F0F0F0F0 F0F0F0F0
N3.C3.D0.R0.S15: RdPtrOffsetTxDq: 05
N5.C0.D0.R1.S16: RdPtrOffsetTxDq: 06
N7.C3.D0.R1: CheckMCTest: result = 0x3FE00
ACCM: F0 F0F0F0F0 F0F0F0F0
N3.C3.D0.R0.S15: RdPtrOffsetTxDqs: 06
N5.C0.D0.R1.S17: RdPtrOffsetTxDq: 05
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: F0 F0F0F0F0 F0F0F0F0
N3.C3.D0.R0.S15: PiTxDqs: 52
N5.C0.D0.R1.S00: RdPtrOffsetTxDq: 08
ACCM: F0 F0F0F0F0 F0F0F0F0
N1.C3.D0.R1: CheckMCTest: result = 0x3FE00
N3.C3.D0.R0.S16: wrcmd2dqsstartlatency: 04
N5.C0.D0.R1.S01: RdPtrOffsetTxDq: 07
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: F0 F0F0F0F0 F0F0F0F0
N3.C3.D0.R0.S16: RdPtrOffsetTxDq: 05
N5.C0.D0.R1.S02: RdPtrOffsetTxDq: 07
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: F0 F0F0F0F0 F0F0F0F0
N3.C3.D0.R0.S16: RdPtrOffsetTxDqs: 07
N5.C0.D0.R1.S03: RdPtrOffsetTxDq: 07
N7.C3.D0.R1: CheckMCTest: result = 0x3FE00
ACCM: 00 000000B0 00000000
N3.C3.D0.R0.S16: PiTxDqs: 06
N5.C0.D0.R1.S04: RdPtrOffsetTxDq: 06
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: 00 000000B0 00000000
N3.C3.D0.R0.S17: wrcmd2dqsstartlatency: 04
N5.C0.D0.R1.S05: RdPtrOffsetTxDq: 07
ACCM: F0 F0F0F0F0 F0F0F0F0
N1.C3.D0.R1: CheckMCTest: result = 0x3FE00
N3.C3.D0.R0.S17: RdPtrOffsetTxDq: 05
N5.C0.D0.R1.S06: RdPtrOffsetTxDq: 07
ACCM: 00 00000000 00000000
ACCM: F0 F0F0F0F0 F0F0F0F0
N3.C3.D0.R0.S17: RdPtrOffsetTxDqs: 06
N5.C0.D0.R1.S07: RdPtrOffsetTxDq: 07
ACCM: 00 00000000 00000000
ACCM: F0 F0F0F0F0 F0F0F0F0
N3.C3.D0.R0.S17: PiTxDqs: 37
N5.C0.D0.R1.S08: RdPtrOffsetTxDq: 06
N7.C3.D0.R1: CheckMCTest: result = 0x3FE00
ACCM: 00 000000F0 00000000
N3.C3.D0.R0.S00: RdPtrOffsetTxDq: 07
N5.C0.D0.R1.S09: RdPtrOffsetTxDq: 07
ACCM: F0 F0F0F0F0 F0F0F0F0
ACCM: 00 000000F0 00000000
N3.C3.D0.R0.S01: RdPtrOffsetTxDq: 06
N5.C0.D0.R1.S10: RdPtrOffsetTxDq: 07
ACCM: F0 F0F0F0F0 F0F0F0F0
N1.C3.D0.R1: CheckMCTest: result = 0x3FE00
N3.C3.D0.R0.S02: RdPtrOffsetTxDq: 06
N5.C0.D0.R1.S11: RdPtrOffsetTxDq: 07
ACCM: 00 00000000 00000000
N1.C3.D0.R1: CheckMCTest: passed
N3.C3.D0.R0.S03: RdPtrOffsetTxDq: 06
N5.C0.D0.R1.S12: RdPtrOffsetTxDq: 07
ACCM: 00 00000000 00000000
N1.C3.D0.R1: CheckMCTest: passed
N3.C3.D0.R0.S04: RdPtrOffsetTxDq: 05
N5.C0.D0.R1.S13: RdPtrOffsetTxDq: 06
N7.C3.D0.R1: CheckMCTest: result = 0x3FE00
N1.C3.D0.R1.S09: Offset Found: RdPtrOffsetDqs = 007
N3.C3.D0.R0.S05: RdPtrOffsetTxDq: 06
N5.C0.D0.R1.S14: RdPtrOffsetTxDq: 07
N7.C3.D0.R1: CheckMCTest: passed
N1.C3.D0.R1.S10: Offset Found: RdPtrOffsetDqs = 007
N3.C3.D0.R0.S06: RdPtrOffsetTxDq: 06
N5.C0.D0.R1.S15: RdPtrOffsetTxDq: 07
N7.C3.D0.R1: CheckMCTest: passed
N1.C3.D0.R1.S11: Offset Found: RdPtrOffsetDqs = 007
N3.C3.D0.R0.S07: RdPtrOffsetTxDq: 06
N5.C0.D0.R1.S16: RdPtrOffsetTxDq: 07
N7.C3.D0.R1.S09: Offset Found: RdPtrOffsetDqs = 007
N1.C3.D0.R1.S12: Offset Found: RdPtrOffsetDqs = 006
N3.C3.D0.R0.S08: RdPtrOffsetTxDq: 06
N5.C0.D0.R1.S17: RdPtrOffsetTxDq: 06
N7.C3.D0.R1.S10: Offset Found: RdPtrOffsetDqs = 007
N1.C3.D0.R1.S13: Offset Found: RdPtrOffsetDqs = 006
N3.C3.D0.R0.S09: RdPtrOffsetTxDq: 07
N5.C0.D0.R1.S00: Total Delay in PI ticks: TxDQ = 960
N7.C3.D0.R1.S11: Offset Found: RdPtrOffsetDqs = 007
N1.C3.D0.R1.S14: Offset Found: RdPtrOffsetDqs = 006
N3.C3.D0.R0.S10: RdPtrOffsetTxDq: 06
N5.C0.D0.R1.S01: Total Delay in PI ticks: TxDQ = 943
N7.C3.D0.R1.S12: Offset Found: RdPtrOffsetDqs = 007
N1.C3.D0.R1.S15: Offset Found: RdPtrOffsetDqs = 006
N3.C3.D0.R0.S11: RdPtrOffsetTxDq: 06
N5.C0.D0.R1.S02: Total Delay in PI ticks: TxDQ = 928
N7.C3.D0.R1.S13: Offset Found: RdPtrOffsetDqs = 006
N1.C3.D0.R1.S16: Offset Found: RdPtrOffsetDqs = 007
N3.C3.D0.R0.S12: RdPtrOffsetTxDq: 06
N5.C0.D0.R1.S03: Total Delay in PI ticks: TxDQ = 914
N7.C3.D0.R1.S14: Offset Found: RdPtrOffsetDqs = 006
N1.C3.D0.R1.S17: Offset Found: RdPtrOffsetDqs = 006
N3.C3.D0.R0.S13: RdPtrOffsetTxDq: 05
N5.C0.D0.R1.S04: Total Delay in PI ticks: TxDQ = 880
N7.C3.D0.R1.S15: Offset Found: RdPtrOffsetDqs = 006
N1.C3: Calculating Optimimum DQS Values
N3.C3.D0.R0.S14: RdPtrOffsetTxDq: 06
N5.C0.D0.R1.S05: Total Delay in PI ticks: TxDQ = 898
N7.C3.D0.R1.S16: Offset Found: RdPtrOffsetDqs = 007
N1.C3.D0.R0.S00: Total Delay in PI ticks: TxDQS = 1000, TxDQ = 965
N3.C3.D0.R0.S15: RdPtrOffsetTxDq: 06
N5.C0.D0.R1.S06: Total Delay in PI ticks: TxDQ = 902
N7.C3.D0.R1.S17: Offset Found: RdPtrOffsetDqs = 006
N1.C3.D0.R0.S01: Total Delay in PI ticks: TxDQS = 980, TxDQ = 948
N3.C3.D0.R0.S16: RdPtrOffsetTxDq: 06
N5.C0.D0.R1.S07: Total Delay in PI ticks: TxDQ = 921
N7.C3: Calculating Optimimum DQS Values
N1.C3.D0.R0.S02: Total Delay in PI ticks: TxDQS = 970, TxDQ = 937
N3.C3.D0.R0.S17: RdPtrOffsetTxDq: 06
N5.C0.D0.R1.S08: Total Delay in PI ticks: TxDQ = 888
N7.C3.D0.R0.S00: Total Delay in PI ticks: TxDQS = 1007, TxDQ = 976
N1.C3.D0.R0.S03: Total Delay in PI ticks: TxDQS = 954, TxDQ = 919
N3.C3.D0.R0.S00: RdPtrOffsetTxDq: 08
N5.C0.D0.R1.S09: Total Delay in PI ticks: TxDQ = 959
N7.C3.D0.R0.S01: Total Delay in PI ticks: TxDQS = 992, TxDQ = 961
N1.C3.D0.R0.S04: Total Delay in PI ticks: TxDQS = 920, TxDQ = 886
N3.C3.D0.R0.S01: RdPtrOffsetTxDq: 07
N5.C0.D0.R1.S10: Total Delay in PI ticks: TxDQ = 942
N7.C3.D0.R0.S02: Total Delay in PI ticks: TxDQS = 978, TxDQ = 943
N1.C3.D0.R0.S05: Total Delay in PI ticks: TxDQS = 933, TxDQ = 898
N3.C3.D0.R0.S02: RdPtrOffsetTxDq: 07
N5.C0.D0.R1.S11: Total Delay in PI ticks: TxDQ = 931
N7.C3.D0.R0.S03: Total Delay in PI ticks: TxDQS = 965, TxDQ = 931
N1.C3.D0.R0.S06: Total Delay in PI ticks: TxDQS = 947, TxDQ = 912
N3.C3.D0.R0.S03: RdPtrOffsetTxDq: 07
N5.C0.D0.R1.S12: Total Delay in PI ticks: TxDQ = 910
N7.C3.D0.R0.S04: Total Delay in PI ticks: TxDQS = 928, TxDQ = 892
N1.C3.D0.R0.S07: Total Delay in PI ticks: TxDQS = 965, TxDQ = 933
N3.C3.D0.R0.S04: RdPtrOffsetTxDq: 06
N5.C0.D0.R1.S13: Total Delay in PI ticks: TxDQ = 882
N7.C3.D0.R0.S05: Total Delay in PI ticks: TxDQS = 942, TxDQ = 908
N1.C3.D0.R0.S08: Total Delay in PI ticks: TxDQS = 935, TxDQ = 901
N3.C3.D0.R0.S05: RdPtrOffsetTxDq: 07
N5.C0.D0.R1.S14: Total Delay in PI ticks: TxDQ = 899
N7.C3.D0.R0.S06: Total Delay in PI ticks: TxDQS = 958, TxDQ = 923
N1.C3.D0.R0.S09: Total Delay in PI ticks: TxDQS = 999, TxDQ = 964
N3.C3.D0.R0.S06: RdPtrOffsetTxDq: 07
N5.C0.D0.R1.S15: Total Delay in PI ticks: TxDQ = 905
N7.C3.D0.R0.S07: Total Delay in PI ticks: TxDQS = 974, TxDQ = 942
N1.C3.D0.R0.S10: Total Delay in PI ticks: TxDQS = 982, TxDQ = 948
N3.C3.D0.R0.S07: RdPtrOffsetTxDq: 07
N5.C0.D0.R1.S16: Total Delay in PI ticks: TxDQ = 922
N7.C3.D0.R0.S08: Total Delay in PI ticks: TxDQS = 944, TxDQ = 911
N1.C3.D0.R0.S11: Total Delay in PI ticks: TxDQS = 970, TxDQ = 937
N3.C3.D0.R0.S08: RdPtrOffsetTxDq: 07
N5.C0.D0.R1.S17: Total Delay in PI ticks: TxDQ = 887
N7.C3.D0.R0.S09: Total Delay in PI ticks: TxDQS = 1007, TxDQ = 972
N1.C3.D0.R0.S12: Total Delay in PI ticks: TxDQS = 955, TxDQ = 922
N3.C3.D0.R0.S09: RdPtrOffsetTxDq: 08
N5.C0: Calculating Optimimum DQ/DQS Values
N7.C3.D0.R0.S10: Total Delay in PI ticks: TxDQS = 993, TxDQ = 959
N1.C3.D0.R0.S13: Total Delay in PI ticks: TxDQS = 920, TxDQ = 884
N3.C3.D0.R0.S10: RdPtrOffsetTxDq: 07
START_DATA_TX_DQ
N7.C3.D0.R0.S11: Total Delay in PI ticks: TxDQS = 981, TxDQ = 948
N1.C3.D0.R0.S14: Total Delay in PI ticks: TxDQS = 932, TxDQ = 897
N3.C3.D0.R0.S11: RdPtrOffsetTxDq: 07
N5.C0.S00: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 009
N7.C3.D0.R0.S12: Total Delay in PI ticks: TxDQS = 966, TxDQ = 933
N1.C3.D0.R0.S15: Total Delay in PI ticks: TxDQS = 947, TxDQ = 912
N3.C3.D0.R0.S12: RdPtrOffsetTxDq: 07
N5.C0.S00: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 009
N7.C3.D0.R0.S13: Total Delay in PI ticks: TxDQS = 929, TxDQ = 894
N1.C3.D0.R0.S16: Total Delay in PI ticks: TxDQS = 965, TxDQ = 933
N3.C3.D0.R0.S13: RdPtrOffsetTxDq: 06
N5.C0.S01: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 009
N7.C3.D0.R0.S14: Total Delay in PI ticks: TxDQS = 944, TxDQ = 910
N1.C3.D0.R0.S17: Total Delay in PI ticks: TxDQS = 931, TxDQ = 897
N3.C3.D0.R0.S14: RdPtrOffsetTxDq: 07
N5.C0.S01: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 009
N7.C3.D0.R0.S15: Total Delay in PI ticks: TxDQS = 958, TxDQ = 924
N1.C3.D0.R1.S00: Total Delay in PI ticks: TxDQS = 1000, TxDQ = 964
N3.C3.D0.R0.S15: RdPtrOffsetTxDq: 07
N5.C0.S02: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 009
N7.C3.D0.R0.S16: Total Delay in PI ticks: TxDQS = 973, TxDQ = 943
N1.C3.D0.R1.S01: Total Delay in PI ticks: TxDQS = 979, TxDQ = 945
N3.C3.D0.R0.S16: RdPtrOffsetTxDq: 07
N5.C0.S02: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 009
N7.C3.D0.R0.S17: Total Delay in PI ticks: TxDQS = 943, TxDQ = 909
N1.C3.D0.R1.S02: Total Delay in PI ticks: TxDQS = 968, TxDQ = 935
N3.C3.D0.R0.S17: RdPtrOffsetTxDq: 07
N5.C0.S03: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 008
N7.C3.D0.R1.S00: Total Delay in PI ticks: TxDQS = 1007, TxDQ = 975
N1.C3.D0.R1.S03: Total Delay in PI ticks: TxDQS = 954, TxDQ = 918
N3.C3.D0.R0.S00: Total Delay in PI ticks: TxDQ = 966
N5.C0.S03: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 008
N7.C3.D0.R1.S01: Total Delay in PI ticks: TxDQS = 990, TxDQ = 958
N1.C3.D0.R1.S04: Total Delay in PI ticks: TxDQS = 919, TxDQ = 887
N3.C3.D0.R0.S01: Total Delay in PI ticks: TxDQ = 946
N5.C0.S04: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 007, RdPtrOffsetTxDqs = 008
N7.C3.D0.R1.S02: Total Delay in PI ticks: TxDQS = 978, TxDQ = 943
N1.C3.D0.R1.S05: Total Delay in PI ticks: TxDQS = 931, TxDQ = 896
N3.C3.D0.R0.S02: Total Delay in PI ticks: TxDQ = 937
N5.C0.S04: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 007, RdPtrOffsetTxDqs = 008
N7.C3.D0.R1.S03: Total Delay in PI ticks: TxDQS = 965, TxDQ = 931
N1.C3.D0.R1.S06: Total Delay in PI ticks: TxDQS = 947, TxDQ = 913
N3.C3.D0.R0.S03: Total Delay in PI ticks: TxDQ = 920
N5.C0.S05: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 008
N7.C3.D0.R1.S04: Total Delay in PI ticks: TxDQS = 929, TxDQ = 893
N1.C3.D0.R1.S07: Total Delay in PI ticks: TxDQS = 963, TxDQ = 932
N3.C3.D0.R0.S04: Total Delay in PI ticks: TxDQ = 885
N5.C0.S05: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 008
N7.C3.D0.R1.S05: Total Delay in PI ticks: TxDQS = 943, TxDQ = 909
N1.C3.D0.R1.S08: Total Delay in PI ticks: TxDQS = 931, TxDQ = 897
N3.C3.D0.R0.S05: Total Delay in PI ticks: TxDQ = 901
N5.C0.S06: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 008
N7.C3.D0.R1.S06: Total Delay in PI ticks: TxDQS = 957, TxDQ = 922
N1.C3.D0.R1.S09: Total Delay in PI ticks: TxDQS = 998, TxDQ = 963
N3.C3.D0.R0.S06: Total Delay in PI ticks: TxDQ = 915
N5.C0.S06: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 008
N7.C3.D0.R1.S07: Total Delay in PI ticks: TxDQS = 974, TxDQ = 943
N1.C3.D0.R1.S10: Total Delay in PI ticks: TxDQS = 981, TxDQ = 947
N3.C3.D0.R0.S07: Total Delay in PI ticks: TxDQ = 931
N5.C0.S07: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 008
N7.C3.D0.R1.S08: Total Delay in PI ticks: TxDQS = 943, TxDQ = 910
N1.C3.D0.R1.S11: Total Delay in PI ticks: TxDQS = 970, TxDQ = 937
N3.C3.D0.R0.S08: Total Delay in PI ticks: TxDQ = 900
N5.C0.S07: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 008
N7.C3.D0.R1.S09: Total Delay in PI ticks: TxDQS = 1005, TxDQ = 970
N1.C3.D0.R1.S12: Total Delay in PI ticks: TxDQS = 954, TxDQ = 921
N3.C3.D0.R0.S09: Total Delay in PI ticks: TxDQ = 963
N5.C0.S08: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 007, RdPtrOffsetTxDqs = 008
N7.C3.D0.R1.S10: Total Delay in PI ticks: TxDQS = 991, TxDQ = 957
N1.C3.D0.R1.S13: Total Delay in PI ticks: TxDQS = 921, TxDQ = 885
N3.C3.D0.R0.S10: Total Delay in PI ticks: TxDQ = 948
N5.C0.S08: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 007, RdPtrOffsetTxDqs = 008
N7.C3.D0.R1.S11: Total Delay in PI ticks: TxDQS = 980, TxDQ = 947
N1.C3.D0.R1.S14: Total Delay in PI ticks: TxDQS = 931, TxDQ = 896
N3.C3.D0.R0.S11: Total Delay in PI ticks: TxDQ = 939
N5.C0.D0.R0.S00: TxDqs: plus1 = 1, minus1 = 0, PI = 33, DB = 0
N7.C3.D0.R1.S12: Total Delay in PI ticks: TxDQS = 965, TxDQ = 932
N1.C3.D0.R1.S15: Total Delay in PI ticks: TxDQS = 949, TxDQ = 915
N3.C3.D0.R0.S12: Total Delay in PI ticks: TxDQ = 922
N5.C0.D0.R0.S00: TxDq : plus1 = 1, minus1 = 0, PI = 63, DB = 1
N7.C3.D0.R1.S13: Total Delay in PI ticks: TxDQS = 930, TxDQ = 895
N1.C3.D0.R1.S16: Total Delay in PI ticks: TxDQS = 963, TxDQ = 932
N3.C3.D0.R0.S13: Total Delay in PI ticks: TxDQ = 886
N5.C0.D0.R0.S01: TxDqs: plus1 = 1, minus1 = 0, PI = 18, DB = 0
N7.C3.D0.R1.S14: Total Delay in PI ticks: TxDQS = 943, TxDQ = 909
N1.C3.D0.R1.S17: Total Delay in PI ticks: TxDQS = 933, TxDQ = 899
N3.C3.D0.R0.S14: Total Delay in PI ticks: TxDQ = 898
N5.C0.D0.R0.S01: TxDq : plus1 = 1, minus1 = 0, PI = 48, DB = 0
N7.C3.D0.R1.S15: Total Delay in PI ticks: TxDQS = 957, TxDQ = 923
N1: END WRITE LEVEL COARSE:
N3.C3.D0.R0.S15: Total Delay in PI ticks: TxDQ = 914
N5.C0.D0.R0.S02: TxDqs: plus1 = 1, minus1 = 0, PI = 03, DB = 1
N7.C3.D0.R1.S16: Total Delay in PI ticks: TxDQS = 973, TxDQ = 944
N1: RunTrainStep: Final status = 0
N3.C3.D0.R0.S16: Total Delay in PI ticks: TxDQ = 933
N5.C0.D0.R0.S02: TxDq : plus1 = 1, minus1 = 0, PI = 33, DB = 0
N7.C3.D0.R1.S17: Total Delay in PI ticks: TxDQS = 943, TxDQ = 909

END - Basic Write Level Training       Time         18825 ms
N3.C3.D0.R0.S17: Total Delay in PI ticks: TxDQ = 902
N5.C0.D0.R0.S03: TxDqs: plus1 = 1, minus1 = 0, PI = 53, DB = 1
N7: END WRITE LEVEL COARSE:

START - Basic Write DQ/DQS Training
N3.C3.D0.R1.S00: wrcmd2dqsstartlatency: 04
N5.C0.D0.R0.S03: TxDq : plus1 = 1, minus1 = 0, PI = 17, DB = 0
N7: RunTrainStep: Final status = 0
Checkpoint Code: Socket 0, 0xB7, 0x05, 0x0000
N3.C3.D0.R1.S00: RdPtrOffsetTxDq: 06
N5.C0.D0.R0.S04: TxDqs: plus1 = 1, minus1 = 0, PI = 18, DB = 0

END - Basic Write Level Training       Time         18789 ms
N1.C0.D0.R0.S00: wrcmd2dqsstartlatency: 04
N3.C3.D0.R1.S00: RdPtrOffsetTxDqs: 07
N5.C0.D0.R0.S04: TxDq : plus1 = 1, minus1 = 0, PI = 49, DB = 1

START - Basic Write DQ/DQS Training
N1.C0.D0.R0.S00: RdPtrOffsetTxDq: 05
N3.C3.D0.R1.S00: PiTxDqs: 40
N5.C0.D0.R0.S05: TxDqs: plus1 = 1, minus1 = 0, PI = 35, DB = 0
N7.C0.D0.R0.S00: wrcmd2dqsstartlatency: 04
N1.C0.D0.R0.S00: RdPtrOffsetTxDqs: 07
N3.C3.D0.R1.S01: wrcmd2dqsstartlatency: 04
N5.C0.D0.R0.S05: TxDq : plus1 = 1, minus1 = 0, PI = 02, DB = 1
N7.C0.D0.R0.S00: RdPtrOffsetTxDq: 05
N1.C0.D0.R0.S00: PiTxDqs: 33
N3.C3.D0.R1.S01: RdPtrOffsetTxDq: 05
N5.C0.D0.R0.S06: TxDqs: plus1 = 1, minus1 = 0, PI = 42, DB = 0
N7.C0.D0.R0.S00: RdPtrOffsetTxDqs: 07
N1.C0.D0.R0.S01: wrcmd2dqsstartlatency: 04
N3.C3.D0.R1.S01: RdPtrOffsetTxDqs: 07
N5.C0.D0.R0.S06: TxDq : plus1 = 1, minus1 = 0, PI = 06, DB = 1
N7.C0.D0.R0.S00: PiTxDqs: 33
N1.C0.D0.R0.S01: RdPtrOffsetTxDq: 05
N3.C3.D0.R1.S01: PiTxDqs: 20
N5.C0.D0.R0.S07: TxDqs: plus1 = 1, minus1 = 0, PI = 57, DB = 1
N7.C0.D0.R0.S01: wrcmd2dqsstartlatency: 04
N1.C0.D0.R0.S01: RdPtrOffsetTxDqs: 07
N3.C3.D0.R1.S02: wrcmd2dqsstartlatency: 04
N5.C0.D0.R0.S07: TxDq : plus1 = 1, minus1 = 0, PI = 25, DB = 0
N7.C0.D0.R0.S01: RdPtrOffsetTxDq: 05
N1.C0.D0.R0.S01: PiTxDqs: 16
N3.C3.D0.R1.S02: RdPtrOffsetTxDq: 05
N5.C0.D0.R0.S08: TxDqs: plus1 = 1, minus1 = 0, PI = 25, DB = 0
N7.C0.D0.R0.S01: RdPtrOffsetTxDqs: 07
N1.C0.D0.R0.S02: wrcmd2dqsstartlatency: 04
N3.C3.D0.R1.S02: RdPtrOffsetTxDqs: 07
N5.C0.D0.R0.S08: TxDq : plus1 = 1, minus1 = 0, PI = 55, DB = 1
N7.C0.D0.R0.S01: PiTxDqs: 12
N1.C0.D0.R0.S02: RdPtrOffsetTxDq: 05
N3.C3.D0.R1.S02: PiTxDqs: 10
N5.C0.D0.R0.S09: TxDqs: plus1 = 1, minus1 = 0, PI = 33, DB = 0
N7.C0.D0.R0.S02: wrcmd2dqsstartlatency: 04
N1.C0.D0.R0.S02: RdPtrOffsetTxDqs: 07
N3.C3.D0.R1.S03: wrcmd2dqsstartlatency: 04
N5.C0.D0.R0.S09: TxDq : plus1 = 1, minus1 = 0, PI = 63, DB = 1
N7.C0.D0.R0.S02: RdPtrOffsetTxDq: 05
N1.C0.D0.R0.S02: PiTxDqs: 04
N3.C3.D0.R1.S03: RdPtrOffsetTxDq: 05
N5.C0.D0.R0.S10: TxDqs: plus1 = 1, minus1 = 0, PI = 17, DB = 0
N7.C0.D0.R0.S02: RdPtrOffsetTxDqs: 07
N1.C0.D0.R0.S03: wrcmd2dqsstartlatency: 04
N3.C3.D0.R1.S03: RdPtrOffsetTxDqs: 06
N5.C0.D0.R0.S10: TxDq : plus1 = 1, minus1 = 0, PI = 47, DB = 0
N7.C0.D0.R0.S02: PiTxDqs: 00
N1.C0.D0.R0.S03: RdPtrOffsetTxDq: 05
N3.C3.D0.R1.S03: PiTxDqs: 57
N5.C0.D0.R0.S11: TxDqs: plus1 = 1, minus1 = 0, PI = 06, DB = 1
N7.C0.D0.R0.S03: wrcmd2dqsstartlatency: 04
N1.C0.D0.R0.S03: RdPtrOffsetTxDqs: 06
N3.C3.D0.R1.S04: wrcmd2dqsstartlatency: 04
N5.C0.D0.R0.S11: TxDq : plus1 = 1, minus1 = 0, PI = 36, DB = 0
N7.C0.D0.R0.S03: RdPtrOffsetTxDq: 05
N1.C0.D0.R0.S03: PiTxDqs: 52
N3.C3.D0.R1.S04: RdPtrOffsetTxDq: 04
N5.C0.D0.R0.S12: TxDqs: plus1 = 1, minus1 = 0, PI = 51, DB = 1
N7.C0.D0.R0.S03: RdPtrOffsetTxDqs: 06
N1.C0.D0.R0.S04: wrcmd2dqsstartlatency: 04
N3.C3.D0.R1.S04: RdPtrOffsetTxDqs: 06
N5.C0.D0.R0.S12: TxDq : plus1 = 1, minus1 = 0, PI = 16, DB = 0
N7.C0.D0.R0.S03: PiTxDqs: 48
N1.C0.D0.R0.S04: RdPtrOffsetTxDq: 04
N3.C3.D0.R1.S04: PiTxDqs: 23
N5.C0.D0.R0.S13: TxDqs: plus1 = 1, minus1 = 0, PI = 19, DB = 0
N7.C0.D0.R0.S04: wrcmd2dqsstartlatency: 04
N1.C0.D0.R0.S04: RdPtrOffsetTxDqs: 06
N3.C3.D0.R1.S05: wrcmd2dqsstartlatency: 04
N5.C0.D0.R0.S13: TxDq : plus1 = 1, minus1 = 0, PI = 50, DB = 1
N7.C0.D0.R0.S04: RdPtrOffsetTxDq: 04
N1.C0.D0.R0.S04: PiTxDqs: 16
N3.C3.D0.R1.S05: RdPtrOffsetTxDq: 05
N5.C0.D0.R0.S14: TxDqs: plus1 = 1, minus1 = 0, PI = 34, DB = 0
N7.C0.D0.R0.S04: RdPtrOffsetTxDqs: 06
N1.C0.D0.R0.S05: wrcmd2dqsstartlatency: 04
N3.C3.D0.R1.S05: RdPtrOffsetTxDqs: 06
N5.C0.D0.R0.S14: TxDq : plus1 = 1, minus1 = 0, PI = 03, DB = 1
N7.C0.D0.R0.S04: PiTxDqs: 14
N1.C0.D0.R0.S05: RdPtrOffsetTxDq: 04
N3.C3.D0.R1.S05: PiTxDqs: 37
N5.C0.D0.R0.S15: TxDqs: plus1 = 1, minus1 = 0, PI = 42, DB = 0
N7.C0.D0.R0.S05: wrcmd2dqsstartlatency: 04
N1.C0.D0.R0.S05: RdPtrOffsetTxDqs: 06
N3.C3.D0.R1.S06: wrcmd2dqsstartlatency: 04
N5.C0.D0.R0.S15: TxDq : plus1 = 1, minus1 = 0, PI = 08, DB = 1
N7.C0.D0.R0.S05: RdPtrOffsetTxDq: 04
N1.C0.D0.R0.S05: PiTxDqs: 34
N3.C3.D0.R1.S06: RdPtrOffsetTxDq: 05
N5.C0.D0.R0.S16: TxDqs: plus1 = 1, minus1 = 0, PI = 58, DB = 1
N7.C0.D0.R0.S05: RdPtrOffsetTxDqs: 06
N1.C0.D0.R0.S06: wrcmd2dqsstartlatency: 04
N3.C3.D0.R1.S06: RdPtrOffsetTxDqs: 06
N5.C0.D0.R0.S16: TxDq : plus1 = 1, minus1 = 0, PI = 25, DB = 0
N7.C0.D0.R0.S05: PiTxDqs: 33
N1.C0.D0.R0.S06: RdPtrOffsetTxDq: 05
N3.C3.D0.R1.S06: PiTxDqs: 51
N5.C0.D0.R0.S17: TxDqs: plus1 = 1, minus1 = 0, PI = 26, DB = 0
N7.C0.D0.R0.S06: wrcmd2dqsstartlatency: 04
N1.C0.D0.R0.S06: RdPtrOffsetTxDqs: 06
N3.C3.D0.R1.S07: wrcmd2dqsstartlatency: 04
N5.C0.D0.R0.S17: TxDq : plus1 = 1, minus1 = 0, PI = 55, DB = 1
N7.C0.D0.R0.S06: RdPtrOffsetTxDq: 05
N1.C0.D0.R0.S06: PiTxDqs: 40
N3.C3.D0.R1.S07: RdPtrOffsetTxDq: 05
N5.C0.D0.R1.S00: TxDqs: plus1 = 1, minus1 = 0, PI = 33, DB = 0
N7.C0.D0.R0.S06: RdPtrOffsetTxDqs: 06
N1.C0.D0.R0.S07: wrcmd2dqsstartlatency: 04
N3.C3.D0.R1.S07: RdPtrOffsetTxDqs: 07
N5.C0.D0.R1.S00: TxDq : plus1 = 1, minus1 = 0, PI = 63, DB = 1
N7.C0.D0.R0.S06: PiTxDqs: 35
N1.C0.D0.R0.S07: RdPtrOffsetTxDq: 05
N3.C3.D0.R1.S07: PiTxDqs: 07
N5.C0.D0.R1.S01: TxDqs: plus1 = 1, minus1 = 0, PI = 18, DB = 0
N7.C0.D0.R0.S07: wrcmd2dqsstartlatency: 04
N1.C0.D0.R0.S07: RdPtrOffsetTxDqs: 06
N3.C3.D0.R1.S08: wrcmd2dqsstartlatency: 04
N5.C0.D0.R1.S01: TxDq : plus1 = 1, minus1 = 0, PI = 48, DB = 0
N7.C0.D0.R0.S07: RdPtrOffsetTxDq: 05
N1.C0.D0.R0.S07: PiTxDqs: 58
N3.C3.D0.R1.S08: RdPtrOffsetTxDq: 05
N5.C0.D0.R1.S02: TxDqs: plus1 = 1, minus1 = 0, PI = 03, DB = 1
N7.C0.D0.R0.S07: RdPtrOffsetTxDqs: 06
N1.C0.D0.R0.S08: wrcmd2dqsstartlatency: 04
N3.C3.D0.R1.S08: RdPtrOffsetTxDqs: 06
N5.C0.D0.R1.S02: TxDq : plus1 = 1, minus1 = 0, PI = 33, DB = 0
N7.C0.D0.R0.S07: PiTxDqs: 56
N1.C0.D0.R0.S08: RdPtrOffsetTxDq: 04
N3.C3.D0.R1.S08: PiTxDqs: 38
N5.C0.D0.R1.S03: TxDqs: plus1 = 1, minus1 = 0, PI = 53, DB = 1
N7.C0.D0.R0.S08: wrcmd2dqsstartlatency: 04
N1.C0.D0.R0.S08: RdPtrOffsetTxDqs: 06
N3.C3.D0.R1.S09: wrcmd2dqsstartlatency: 04
N5.C0.D0.R1.S03: TxDq : plus1 = 1, minus1 = 0, PI = 17, DB = 0
N7.C0.D0.R0.S08: RdPtrOffsetTxDq: 04
N1.C0.D0.R0.S08: PiTxDqs: 25
N3.C3.D0.R1.S09: RdPtrOffsetTxDq: 06
N5.C0.D0.R1.S04: TxDqs: plus1 = 1, minus1 = 0, PI = 18, DB = 0
N7.C0.D0.R0.S08: RdPtrOffsetTxDqs: 06
N1.C0.D0.R0.S09: wrcmd2dqsstartlatency: 04
N3.C3.D0.R1.S09: RdPtrOffsetTxDqs: 07
N5.C0.D0.R1.S04: TxDq : plus1 = 1, minus1 = 0, PI = 49, DB = 1
N7.C0.D0.R0.S08: PiTxDqs: 23
N1.C0.D0.R0.S09: RdPtrOffsetTxDq: 05
N3.C3.D0.R1.S09: PiTxDqs: 36
N5.C0.D0.R1.S05: TxDqs: plus1 = 1, minus1 = 0, PI = 35, DB = 0
N7.C0.D0.R0.S09: wrcmd2dqsstartlatency: 04
N1.C0.D0.R0.S09: RdPtrOffsetTxDqs: 07
N3.C3.D0.R1.S10: wrcmd2dqsstartlatency: 04
N5.C0.D0.R1.S05: TxDq : plus1 = 1, minus1 = 0, PI = 02, DB = 1
N7.C0.D0.R0.S09: RdPtrOffsetTxDq: 05
N1.C0.D0.R0.S09: PiTxDqs: 33
N3.C3.D0.R1.S10: RdPtrOffsetTxDq: 05
N5.C0.D0.R1.S06: TxDqs: plus1 = 1, minus1 = 0, PI = 42, DB = 0
N7.C0.D0.R0.S09: RdPtrOffsetTxDqs: 07
N1.C0.D0.R0.S10: wrcmd2dqsstartlatency: 04
N3.C3.D0.R1.S10: RdPtrOffsetTxDqs: 07
N5.C0.D0.R1.S06: TxDq : plus1 = 1, minus1 = 0, PI = 06, DB = 1
N7.C0.D0.R0.S09: PiTxDqs: 31
N1.C0.D0.R0.S10: RdPtrOffsetTxDq: 05
N3.C3.D0.R1.S10: PiTxDqs: 22
N5.C0.D0.R1.S07: TxDqs: plus1 = 1, minus1 = 0, PI = 57, DB = 1
N7.C0.D0.R0.S10: wrcmd2dqsstartlatency: 04
N1.C0.D0.R0.S10: RdPtrOffsetTxDqs: 07
N3.C3.D0.R1.S11: wrcmd2dqsstartlatency: 04
N5.C0.D0.R1.S07: TxDq : plus1 = 1, minus1 = 0, PI = 25, DB = 0
N7.C0.D0.R0.S10: RdPtrOffsetTxDq: 05
N1.C0.D0.R0.S10: PiTxDqs: 16
N3.C3.D0.R1.S11: RdPtrOffsetTxDq: 05
N5.C0.D0.R1.S08: TxDqs: plus1 = 1, minus1 = 0, PI = 25, DB = 0
N7.C0.D0.R0.S10: RdPtrOffsetTxDqs: 07
N1.C0.D0.R0.S11: wrcmd2dqsstartlatency: 04
N3.C3.D0.R1.S11: RdPtrOffsetTxDqs: 07
N5.C0.D0.R1.S08: TxDq : plus1 = 1, minus1 = 0, PI = 55, DB = 1
N7.C0.D0.R0.S10: PiTxDqs: 12
N1.C0.D0.R0.S11: RdPtrOffsetTxDq: 05
N3.C3.D0.R1.S11: PiTxDqs: 10
N5.C0.D0.R1.S09: TxDqs: plus1 = 1, minus1 = 0, PI = 33, DB = 0
N7.C0.D0.R0.S11: wrcmd2dqsstartlatency: 04
N1.C0.D0.R0.S11: RdPtrOffsetTxDqs: 07
N3.C3.D0.R1.S12: wrcmd2dqsstartlatency: 04
N5.C0.D0.R1.S09: TxDq : plus1 = 1, minus1 = 0, PI = 63, DB = 1
N7.C0.D0.R0.S11: RdPtrOffsetTxDq: 05
N1.C0.D0.R0.S11: PiTxDqs: 03
N3.C3.D0.R1.S12: RdPtrOffsetTxDq: 05
N5.C0.D0.R1.S10: TxDqs: plus1 = 1, minus1 = 0, PI = 17, DB = 0
N7.C0.D0.R0.S11: RdPtrOffsetTxDqs: 06
N1.C0.D0.R0.S12: wrcmd2dqsstartlatency: 04
N3.C3.D0.R1.S12: RdPtrOffsetTxDqs: 06
N5.C0.D0.R1.S10: TxDq : plus1 = 1, minus1 = 0, PI = 47, DB = 0
N7.C0.D0.R0.S11: PiTxDqs: 63
N1.C0.D0.R0.S12: RdPtrOffsetTxDq: 05
N3.C3.D0.R1.S12: PiTxDqs: 57
N5.C0.D0.R1.S11: TxDqs: plus1 = 1, minus1 = 0, PI = 06, DB = 1
N7.C0.D0.R0.S12: wrcmd2dqsstartlatency: 04
N1.C0.D0.R0.S12: RdPtrOffsetTxDqs: 06
N3.C3.D0.R1.S13: wrcmd2dqsstartlatency: 04
N5.C0.D0.R1.S11: TxDq : plus1 = 1, minus1 = 0, PI = 36, DB = 0
N7.C0.D0.R0.S12: RdPtrOffsetTxDq: 05
N1.C0.D0.R0.S12: PiTxDqs: 53
N3.C3.D0.R1.S13: RdPtrOffsetTxDq: 04
N5.C0.D0.R1.S12: TxDqs: plus1 = 1, minus1 = 0, PI = 51, DB = 1
N7.C0.D0.R0.S12: RdPtrOffsetTxDqs: 06
N1.C0.D0.R0.S13: wrcmd2dqsstartlatency: 04
N3.C3.D0.R1.S13: RdPtrOffsetTxDqs: 06
N5.C0.D0.R1.S12: TxDq : plus1 = 1, minus1 = 0, PI = 16, DB = 0
N7.C0.D0.R0.S12: PiTxDqs: 48
N1.C0.D0.R0.S13: RdPtrOffsetTxDq: 04
N3.C3.D0.R1.S13: PiTxDqs: 23
N5.C0.D0.R1.S13: TxDqs: plus1 = 1, minus1 = 0, PI = 19, DB = 0
N7.C0.D0.R0.S13: wrcmd2dqsstartlatency: 04
N1.C0.D0.R0.S13: RdPtrOffsetTxDqs: 06
N3.C3.D0.R1.S14: wrcmd2dqsstartlatency: 04
N5.C0.D0.R1.S13: TxDq : plus1 = 1, minus1 = 0, PI = 50, DB = 1
N7.C0.D0.R0.S13: RdPtrOffsetTxDq: 04
N1.C0.D0.R0.S13: PiTxDqs: 16
N3.C3.D0.R1.S14: RdPtrOffsetTxDq: 05
N5.C0.D0.R1.S14: TxDqs: plus1 = 1, minus1 = 0, PI = 34, DB = 0
N7.C0.D0.R0.S13: RdPtrOffsetTxDqs: 06
N1.C0.D0.R0.S14: wrcmd2dqsstartlatency: 04
N3.C3.D0.R1.S14: RdPtrOffsetTxDqs: 06
N5.C0.D0.R1.S14: TxDq : plus1 = 1, minus1 = 0, PI = 03, DB = 1
N7.C0.D0.R0.S13: PiTxDqs: 14
N1.C0.D0.R0.S14: RdPtrOffsetTxDq: 04
N3.C3.D0.R1.S14: PiTxDqs: 37
N5.C0.D0.R1.S15: TxDqs: plus1 = 1, minus1 = 0, PI = 42, DB = 0
N7.C0.D0.R0.S14: wrcmd2dqsstartlatency: 04
N1.C0.D0.R0.S14: RdPtrOffsetTxDqs: 06
N3.C3.D0.R1.S15: wrcmd2dqsstartlatency: 04
N5.C0.D0.R1.S15: TxDq : plus1 = 1, minus1 = 0, PI = 08, DB = 1
N7.C0.D0.R0.S14: RdPtrOffsetTxDq: 05
N1.C0.D0.R0.S14: PiTxDqs: 32
N3.C3.D0.R1.S15: RdPtrOffsetTxDq: 05
N5.C0.D0.R1.S16: TxDqs: plus1 = 1, minus1 = 0, PI = 58, DB = 1
N7.C0.D0.R0.S14: RdPtrOffsetTxDqs: 06
N1.C0.D0.R0.S15: wrcmd2dqsstartlatency: 04
N3.C3.D0.R1.S15: RdPtrOffsetTxDqs: 06
N5.C0.D0.R1.S16: TxDq : plus1 = 1, minus1 = 0, PI = 25, DB = 0
N7.C0.D0.R0.S14: PiTxDqs: 33
N1.C0.D0.R0.S15: RdPtrOffsetTxDq: 05
N3.C3.D0.R1.S15: PiTxDqs: 53
N5.C0.D0.R1.S17: TxDqs: plus1 = 1, minus1 = 0, PI = 26, DB = 0
N7.C0.D0.R0.S15: wrcmd2dqsstartlatency: 04
N1.C0.D0.R0.S15: RdPtrOffsetTxDqs: 06
N3.C3.D0.R1.S16: wrcmd2dqsstartlatency: 04
N5.C0.D0.R1.S17: TxDq : plus1 = 1, minus1 = 0, PI = 55, DB = 1
N7.C0.D0.R0.S15: RdPtrOffsetTxDq: 05
N1.C0.D0.R0.S15: PiTxDqs: 40
N3.C3.D0.R1.S16: RdPtrOffsetTxDq: 05
END_DATA_TX_DQ
N7.C0.D0.R0.S15: RdPtrOffsetTxDqs: 06
N1.C0.D0.R0.S16: wrcmd2dqsstartlatency: 04
N3.C3.D0.R1.S16: RdPtrOffsetTxDqs: 07
N5.C1.D0.R0.S00: wrcmd2dqsstartlatency: 04
N7.C0.D0.R0.S15: PiTxDqs: 36
N1.C0.D0.R0.S16: RdPtrOffsetTxDq: 05
N3.C3.D0.R1.S16: PiTxDqs: 07
N5.C1.D0.R0.S00: RdPtrOffsetTxDq: 06
N7.C0.D0.R0.S16: wrcmd2dqsstartlatency: 04
N1.C0.D0.R0.S16: RdPtrOffsetTxDqs: 06
N3.C3.D0.R1.S17: wrcmd2dqsstartlatency: 04
N5.C1.D0.R0.S00: RdPtrOffsetTxDqs: 07
N7.C0.D0.R0.S16: RdPtrOffsetTxDq: 05
N1.C0.D0.R0.S16: PiTxDqs: 56
N3.C3.D0.R1.S17: RdPtrOffsetTxDq: 05
N5.C1.D0.R0.S00: PiTxDqs: 42
N7.C0.D0.R0.S16: RdPtrOffsetTxDqs: 06
N1.C0.D0.R0.S17: wrcmd2dqsstartlatency: 04
N3.C3.D0.R1.S17: RdPtrOffsetTxDqs: 06
N5.C1.D0.R0.S01: wrcmd2dqsstartlatency: 04
N7.C0.D0.R0.S16: PiTxDqs: 55
N1.C0.D0.R0.S17: RdPtrOffsetTxDq: 04
N3.C3.D0.R1.S17: PiTxDqs: 37
N5.C1.D0.R0.S01: RdPtrOffsetTxDq: 05
N7.C0.D0.R0.S17: wrcmd2dqsstartlatency: 04
N1.C0.D0.R0.S17: RdPtrOffsetTxDqs: 06
N3.C3.D0.R1.S00: RdPtrOffsetTxDq: 07
N5.C1.D0.R0.S01: RdPtrOffsetTxDqs: 07
N7.C0.D0.R0.S17: RdPtrOffsetTxDq: 04
N1.C0.D0.R0.S17: PiTxDqs: 25
N3.C3.D0.R1.S01: RdPtrOffsetTxDq: 06
N5.C1.D0.R0.S01: PiTxDqs: 25
N7.C0.D0.R0.S17: RdPtrOffsetTxDqs: 06
N1.C0.D0.R0.S00: RdPtrOffsetTxDq: 06
N3.C3.D0.R1.S02: RdPtrOffsetTxDq: 06
N5.C1.D0.R0.S02: wrcmd2dqsstartlatency: 04
N7.C0.D0.R0.S17: PiTxDqs: 24
N1.C0.D0.R0.S01: RdPtrOffsetTxDq: 06
N3.C3.D0.R1.S03: RdPtrOffsetTxDq: 06
N5.C1.D0.R0.S02: RdPtrOffsetTxDq: 05
N7.C0.D0.R0.S00: RdPtrOffsetTxDq: 06
N1.C0.D0.R0.S02: RdPtrOffsetTxDq: 06
N3.C3.D0.R1.S04: RdPtrOffsetTxDq: 05
N5.C1.D0.R0.S02: RdPtrOffsetTxDqs: 07
N7.C0.D0.R0.S01: RdPtrOffsetTxDq: 06
N1.C0.D0.R0.S03: RdPtrOffsetTxDq: 06
N3.C3.D0.R1.S05: RdPtrOffsetTxDq: 06
N5.C1.D0.R0.S02: PiTxDqs: 13
N7.C0.D0.R0.S02: RdPtrOffsetTxDq: 06
N1.C0.D0.R0.S04: RdPtrOffsetTxDq: 05
N3.C3.D0.R1.S06: RdPtrOffsetTxDq: 06
N5.C1.D0.R0.S03: wrcmd2dqsstartlatency: 04
N7.C0.D0.R0.S03: RdPtrOffsetTxDq: 06
N1.C0.D0.R0.S05: RdPtrOffsetTxDq: 05
N3.C3.D0.R1.S07: RdPtrOffsetTxDq: 06
N5.C1.D0.R0.S03: RdPtrOffsetTxDq: 05
N7.C0.D0.R0.S04: RdPtrOffsetTxDq: 05
N1.C0.D0.R0.S06: RdPtrOffsetTxDq: 06
N3.C3.D0.R1.S08: RdPtrOffsetTxDq: 06
N5.C1.D0.R0.S03: RdPtrOffsetTxDqs: 06
N7.C0.D0.R0.S05: RdPtrOffsetTxDq: 05
N1.C0.D0.R0.S07: RdPtrOffsetTxDq: 06
N3.C3.D0.R1.S09: RdPtrOffsetTxDq: 07
N5.C1.D0.R0.S03: PiTxDqs: 62
N7.C0.D0.R0.S06: RdPtrOffsetTxDq: 06
N1.C0.D0.R0.S08: RdPtrOffsetTxDq: 05
N3.C3.D0.R1.S10: RdPtrOffsetTxDq: 06
N5.C1.D0.R0.S04: wrcmd2dqsstartlatency: 04
N7.C0.D0.R0.S07: RdPtrOffsetTxDq: 06
N1.C0.D0.R0.S09: RdPtrOffsetTxDq: 06
N3.C3.D0.R1.S11: RdPtrOffsetTxDq: 06
N5.C1.D0.R0.S04: RdPtrOffsetTxDq: 04
N7.C0.D0.R0.S08: RdPtrOffsetTxDq: 05
N1.C0.D0.R0.S10: RdPtrOffsetTxDq: 06
N3.C3.D0.R1.S12: RdPtrOffsetTxDq: 06
N5.C1.D0.R0.S04: RdPtrOffsetTxDqs: 06
N7.C0.D0.R0.S09: RdPtrOffsetTxDq: 06
N1.C0.D0.R0.S11: RdPtrOffsetTxDq: 06
N3.C3.D0.R1.S13: RdPtrOffsetTxDq: 05
N5.C1.D0.R0.S04: PiTxDqs: 28
N7.C0.D0.R0.S10: RdPtrOffsetTxDq: 06
N1.C0.D0.R0.S12: RdPtrOffsetTxDq: 06
N3.C3.D0.R1.S14: RdPtrOffsetTxDq: 06
N5.C1.D0.R0.S05: wrcmd2dqsstartlatency: 04
N7.C0.D0.R0.S11: RdPtrOffsetTxDq: 06
N1.C0.D0.R0.S13: RdPtrOffsetTxDq: 05
N3.C3.D0.R1.S15: RdPtrOffsetTxDq: 06
N5.C1.D0.R0.S05: RdPtrOffsetTxDq: 05
N7.C0.D0.R0.S12: RdPtrOffsetTxDq: 06
N1.C0.D0.R0.S14: RdPtrOffsetTxDq: 05
N3.C3.D0.R1.S16: RdPtrOffsetTxDq: 06
N5.C1.D0.R0.S05: RdPtrOffsetTxDqs: 06
N7.C0.D0.R0.S13: RdPtrOffsetTxDq: 05
N1.C0.D0.R0.S15: RdPtrOffsetTxDq: 06
N3.C3.D0.R1.S17: RdPtrOffsetTxDq: 06
N5.C1.D0.R0.S05: PiTxDqs: 43
N7.C0.D0.R0.S14: RdPtrOffsetTxDq: 06
N1.C0.D0.R0.S16: RdPtrOffsetTxDq: 06
N3.C3.D0.R1.S00: RdPtrOffsetTxDq: 08
N5.C1.D0.R0.S06: wrcmd2dqsstartlatency: 04
N7.C0.D0.R0.S15: RdPtrOffsetTxDq: 06
N1.C0.D0.R0.S17: RdPtrOffsetTxDq: 05
N3.C3.D0.R1.S01: RdPtrOffsetTxDq: 07
N5.C1.D0.R0.S06: RdPtrOffsetTxDq: 05
N7.C0.D0.R0.S16: RdPtrOffsetTxDq: 06
N1.C0.D0.R0.S00: RdPtrOffsetTxDq: 07
N3.C3.D0.R1.S02: RdPtrOffsetTxDq: 07
N5.C1.D0.R0.S06: RdPtrOffsetTxDqs: 06
N7.C0.D0.R0.S17: RdPtrOffsetTxDq: 05
N1.C0.D0.R0.S01: RdPtrOffsetTxDq: 07
N3.C3.D0.R1.S03: RdPtrOffsetTxDq: 07
N5.C1.D0.R0.S06: PiTxDqs: 58
N7.C0.D0.R0.S00: RdPtrOffsetTxDq: 07
N1.C0.D0.R0.S02: RdPtrOffsetTxDq: 07
N3.C3.D0.R1.S04: RdPtrOffsetTxDq: 06
N5.C1.D0.R0.S07: wrcmd2dqsstartlatency: 04
N7.C0.D0.R0.S01: RdPtrOffsetTxDq: 07
N1.C0.D0.R0.S03: RdPtrOffsetTxDq: 07
N3.C3.D0.R1.S05: RdPtrOffsetTxDq: 07
N5.C1.D0.R0.S07: RdPtrOffsetTxDq: 05
N7.C0.D0.R0.S02: RdPtrOffsetTxDq: 07
N1.C0.D0.R0.S04: RdPtrOffsetTxDq: 06
N3.C3.D0.R1.S06: RdPtrOffsetTxDq: 07
N5.C1.D0.R0.S07: RdPtrOffsetTxDqs: 07
N7.C0.D0.R0.S03: RdPtrOffsetTxDq: 07
N1.C0.D0.R0.S05: RdPtrOffsetTxDq: 06
N3.C3.D0.R1.S07: RdPtrOffsetTxDq: 07
N5.C1.D0.R0.S07: PiTxDqs: 11
N7.C0.D0.R0.S04: RdPtrOffsetTxDq: 06
N1.C0.D0.R0.S06: RdPtrOffsetTxDq: 07
N3.C3.D0.R1.S08: RdPtrOffsetTxDq: 07
N5.C1.D0.R0.S08: wrcmd2dqsstartlatency: 04
N7.C0.D0.R0.S05: RdPtrOffsetTxDq: 06
N1.C0.D0.R0.S07: RdPtrOffsetTxDq: 07
N3.C3.D0.R1.S09: RdPtrOffsetTxDq: 08
N5.C1.D0.R0.S08: RdPtrOffsetTxDq: 05
N7.C0.D0.R0.S06: RdPtrOffsetTxDq: 07
N1.C0.D0.R0.S08: RdPtrOffsetTxDq: 06
N3.C3.D0.R1.S10: RdPtrOffsetTxDq: 07
N5.C1.D0.R0.S08: RdPtrOffsetTxDqs: 06
N7.C0.D0.R0.S07: RdPtrOffsetTxDq: 07
N1.C0.D0.R0.S09: RdPtrOffsetTxDq: 07
N3.C3.D0.R1.S11: RdPtrOffsetTxDq: 07
N5.C1.D0.R0.S08: PiTxDqs: 40
N7.C0.D0.R0.S08: RdPtrOffsetTxDq: 06
N1.C0.D0.R0.S10: RdPtrOffsetTxDq: 07
N3.C3.D0.R1.S12: RdPtrOffsetTxDq: 07
N5.C1.D0.R0.S09: wrcmd2dqsstartlatency: 04
N7.C0.D0.R0.S09: RdPtrOffsetTxDq: 07
N1.C0.D0.R0.S11: RdPtrOffsetTxDq: 07
N3.C3.D0.R1.S13: RdPtrOffsetTxDq: 06
N5.C1.D0.R0.S09: RdPtrOffsetTxDq: 06
N7.C0.D0.R0.S10: RdPtrOffsetTxDq: 07
N1.C0.D0.R0.S12: RdPtrOffsetTxDq: 07
N3.C3.D0.R1.S14: RdPtrOffsetTxDq: 07
N5.C1.D0.R0.S09: RdPtrOffsetTxDqs: 07
N7.C0.D0.R0.S11: RdPtrOffsetTxDq: 07
N1.C0.D0.R0.S13: RdPtrOffsetTxDq: 06
N3.C3.D0.R1.S15: RdPtrOffsetTxDq: 07
N5.C1.D0.R0.S09: PiTxDqs: 41
N7.C0.D0.R0.S12: RdPtrOffsetTxDq: 07
N1.C0.D0.R0.S14: RdPtrOffsetTxDq: 06
N3.C3.D0.R1.S16: RdPtrOffsetTxDq: 07
N5.C1.D0.R0.S10: wrcmd2dqsstartlatency: 04
N7.C0.D0.R0.S13: RdPtrOffsetTxDq: 06
N1.C0.D0.R0.S15: RdPtrOffsetTxDq: 07
N3.C3.D0.R1.S17: RdPtrOffsetTxDq: 07
N5.C1.D0.R0.S10: RdPtrOffsetTxDq: 05
N7.C0.D0.R0.S14: RdPtrOffsetTxDq: 07
N1.C0.D0.R0.S16: RdPtrOffsetTxDq: 07
N3.C3.D0.R1.S00: Total Delay in PI ticks: TxDQ = 966
N5.C1.D0.R0.S10: RdPtrOffsetTxDqs: 07
N7.C0.D0.R0.S15: RdPtrOffsetTxDq: 07
N1.C0.D0.R0.S17: RdPtrOffsetTxDq: 06
N3.C3.D0.R1.S01: Total Delay in PI ticks: TxDQ = 947
N5.C1.D0.R0.S10: PiTxDqs: 25
N7.C0.D0.R0.S16: RdPtrOffsetTxDq: 07
N1.C0.D0.R0.S00: Total Delay in PI ticks: TxDQ = 962
N3.C3.D0.R1.S02: Total Delay in PI ticks: TxDQ = 936
N5.C1.D0.R0.S11: wrcmd2dqsstartlatency: 04
N7.C0.D0.R0.S17: RdPtrOffsetTxDq: 06
N1.C0.D0.R0.S01: Total Delay in PI ticks: TxDQ = 943
N3.C3.D0.R1.S03: Total Delay in PI ticks: TxDQ = 919
N5.C1.D0.R0.S11: RdPtrOffsetTxDq: 05
N7.C0.D0.R0.S00: Total Delay in PI ticks: TxDQ = 960
N1.C0.D0.R0.S02: Total Delay in PI ticks: TxDQ = 930
N3.C3.D0.R1.S04: Total Delay in PI ticks: TxDQ = 884
N5.C1.D0.R0.S11: RdPtrOffsetTxDqs: 07
N7.C0.D0.R0.S01: Total Delay in PI ticks: TxDQ = 937
N1.C0.D0.R0.S03: Total Delay in PI ticks: TxDQ = 913
N3.C3.D0.R1.S05: Total Delay in PI ticks: TxDQ = 900
N5.C1.D0.R0.S11: PiTxDqs: 14
N7.C0.D0.R0.S02: Total Delay in PI ticks: TxDQ = 927
N1.C0.D0.R0.S04: Total Delay in PI ticks: TxDQ = 878
N3.C3.D0.R1.S06: Total Delay in PI ticks: TxDQ = 913
N5.C1.D0.R0.S12: wrcmd2dqsstartlatency: 04
N7.C0.D0.R0.S03: Total Delay in PI ticks: TxDQ = 908
N1.C0.D0.R0.S05: Total Delay in PI ticks: TxDQ = 898
N3.C3.D0.R1.S07: Total Delay in PI ticks: TxDQ = 932
N5.C1.D0.R0.S12: RdPtrOffsetTxDq: 05
N7.C0.D0.R0.S04: Total Delay in PI ticks: TxDQ = 876
N1.C0.D0.R0.S06: Total Delay in PI ticks: TxDQ = 902
N3.C3.D0.R1.S08: Total Delay in PI ticks: TxDQ = 900
N5.C1.D0.R0.S12: RdPtrOffsetTxDqs: 06
N7.C0.D0.R0.S05: Total Delay in PI ticks: TxDQ = 896
N1.C0.D0.R0.S07: Total Delay in PI ticks: TxDQ = 920
N3.C3.D0.R1.S09: Total Delay in PI ticks: TxDQ = 963
N5.C1.D0.R0.S12: PiTxDqs: 61
N7.C0.D0.R0.S06: Total Delay in PI ticks: TxDQ = 897
N1.C0.D0.R0.S08: Total Delay in PI ticks: TxDQ = 886
N3.C3.D0.R1.S10: Total Delay in PI ticks: TxDQ = 948
N5.C1.D0.R0.S13: wrcmd2dqsstartlatency: 04
N7.C0.D0.R0.S07: Total Delay in PI ticks: TxDQ = 918
N1.C0.D0.R0.S09: Total Delay in PI ticks: TxDQ = 960
N3.C3.D0.R1.S11: Total Delay in PI ticks: TxDQ = 936
N5.C1.D0.R0.S13: RdPtrOffsetTxDq: 04
N7.C0.D0.R0.S08: Total Delay in PI ticks: TxDQ = 885
N1.C0.D0.R0.S10: Total Delay in PI ticks: TxDQ = 943
N3.C3.D0.R1.S12: Total Delay in PI ticks: TxDQ = 919
N5.C1.D0.R0.S13: RdPtrOffsetTxDqs: 06
N7.C0.D0.R0.S09: Total Delay in PI ticks: TxDQ = 957
N1.C0.D0.R0.S11: Total Delay in PI ticks: TxDQ = 928
N3.C3.D0.R1.S13: Total Delay in PI ticks: TxDQ = 884
N5.C1.D0.R0.S13: PiTxDqs: 30
N7.C0.D0.R0.S10: Total Delay in PI ticks: TxDQ = 937
N1.C0.D0.R0.S12: Total Delay in PI ticks: TxDQ = 915
N3.C3.D0.R1.S14: Total Delay in PI ticks: TxDQ = 900
N5.C1.D0.R0.S14: wrcmd2dqsstartlatency: 04
N7.C0.D0.R0.S11: Total Delay in PI ticks: TxDQ = 924
N1.C0.D0.R0.S13: Total Delay in PI ticks: TxDQ = 879
N3.C3.D0.R1.S15: Total Delay in PI ticks: TxDQ = 915
N5.C1.D0.R0.S14: RdPtrOffsetTxDq: 05
N7.C0.D0.R0.S12: Total Delay in PI ticks: TxDQ = 909
N1.C0.D0.R0.S14: Total Delay in PI ticks: TxDQ = 896
N3.C3.D0.R1.S16: Total Delay in PI ticks: TxDQ = 933
N5.C1.D0.R0.S14: RdPtrOffsetTxDqs: 06
N7.C0.D0.R0.S13: Total Delay in PI ticks: TxDQ = 878
N1.C0.D0.R0.S15: Total Delay in PI ticks: TxDQ = 904
N3.C3.D0.R1.S17: Total Delay in PI ticks: TxDQ = 901
N5.C1.D0.R0.S14: PiTxDqs: 43
N7.C0.D0.R0.S14: Total Delay in PI ticks: TxDQ = 897
N1.C0.D0.R0.S16: Total Delay in PI ticks: TxDQ = 918
N3.C3: Calculating Optimimum DQ/DQS Values
N5.C1.D0.R0.S15: wrcmd2dqsstartlatency: 04
N7.C0.D0.R0.S15: Total Delay in PI ticks: TxDQ = 899
N1.C0.D0.R0.S17: Total Delay in PI ticks: TxDQ = 886
START_DATA_TX_DQ
N5.C1.D0.R0.S15: RdPtrOffsetTxDq: 05
N7.C0.D0.R0.S16: Total Delay in PI ticks: TxDQ = 917
N1.C0.D0.R1.S00: wrcmd2dqsstartlatency: 04
N3.C3.S00: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 009, RdPtrOffsetTxDqs = 009
N5.C1.D0.R0.S15: RdPtrOffsetTxDqs: 06
N7.C0.D0.R0.S17: Total Delay in PI ticks: TxDQ = 886
N1.C0.D0.R1.S00: RdPtrOffsetTxDq: 06
N3.C3.S00: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 009, RdPtrOffsetTxDqs = 009
N5.C1.D0.R0.S15: PiTxDqs: 56
N7.C0.D0.R1.S00: wrcmd2dqsstartlatency: 04
N1.C0.D0.R1.S00: RdPtrOffsetTxDqs: 07
N3.C3.S01: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 009
N5.C1.D0.R0.S16: wrcmd2dqsstartlatency: 04
N7.C0.D0.R1.S00: RdPtrOffsetTxDq: 05
N1.C0.D0.R1.S00: PiTxDqs: 34
N3.C3.S01: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 009
N5.C1.D0.R0.S16: RdPtrOffsetTxDq: 05
N7.C0.D0.R1.S00: RdPtrOffsetTxDqs: 07
N1.C0.D0.R1.S01: wrcmd2dqsstartlatency: 04
N3.C3.S02: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 009
N5.C1.D0.R0.S16: RdPtrOffsetTxDqs: 07
N7.C0.D0.R1.S00: PiTxDqs: 31
N1.C0.D0.R1.S01: RdPtrOffsetTxDq: 05
N3.C3.S02: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 009
N5.C1.D0.R0.S16: PiTxDqs: 11
N7.C0.D0.R1.S01: wrcmd2dqsstartlatency: 04
N1.C0.D0.R1.S01: RdPtrOffsetTxDqs: 07
N3.C3.S03: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 008
N5.C1.D0.R0.S17: wrcmd2dqsstartlatency: 04
N7.C0.D0.R1.S01: RdPtrOffsetTxDq: 05
N1.C0.D0.R1.S01: PiTxDqs: 15
N3.C3.S03: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 008
N5.C1.D0.R0.S17: RdPtrOffsetTxDq: 05
N7.C0.D0.R1.S01: RdPtrOffsetTxDqs: 07
N1.C0.D0.R1.S02: wrcmd2dqsstartlatency: 04
N3.C3.S04: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 007, RdPtrOffsetTxDqs = 008
N5.C1.D0.R0.S17: RdPtrOffsetTxDqs: 06
N7.C0.D0.R1.S01: PiTxDqs: 11
N1.C0.D0.R1.S02: RdPtrOffsetTxDq: 05
N3.C3.S04: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 007, RdPtrOffsetTxDqs = 008
N5.C1.D0.R0.S17: PiTxDqs: 42
N7.C0.D0.R1.S02: wrcmd2dqsstartlatency: 04
N1.C0.D0.R1.S02: RdPtrOffsetTxDqs: 07
N3.C3.S05: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 008
N5.C1.D0.R0.S00: RdPtrOffsetTxDq: 07
N7.C0.D0.R1.S02: RdPtrOffsetTxDq: 05
N1.C0.D0.R1.S02: PiTxDqs: 03
N3.C3.S05: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 008
N5.C1.D0.R0.S01: RdPtrOffsetTxDq: 06
N7.C0.D0.R1.S02: RdPtrOffsetTxDqs: 06
N1.C0.D0.R1.S03: wrcmd2dqsstartlatency: 04
N3.C3.S06: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 008
N5.C1.D0.R0.S02: RdPtrOffsetTxDq: 06
N7.C0.D0.R1.S02: PiTxDqs: 63
N1.C0.D0.R1.S03: RdPtrOffsetTxDq: 05
N3.C3.S06: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 008
N5.C1.D0.R0.S03: RdPtrOffsetTxDq: 06
N7.C0.D0.R1.S03: wrcmd2dqsstartlatency: 04
N1.C0.D0.R1.S03: RdPtrOffsetTxDqs: 06
N3.C3.S07: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 009
N5.C1.D0.R0.S04: RdPtrOffsetTxDq: 05
N7.C0.D0.R1.S03: RdPtrOffsetTxDq: 05
N1.C0.D0.R1.S03: PiTxDqs: 49
N3.C3.S07: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 009
N5.C1.D0.R0.S05: RdPtrOffsetTxDq: 06
N7.C0.D0.R1.S03: RdPtrOffsetTxDqs: 06
N1.C0.D0.R1.S04: wrcmd2dqsstartlatency: 04
N3.C3.S08: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 008
N5.C1.D0.R0.S06: RdPtrOffsetTxDq: 06
N7.C0.D0.R1.S03: PiTxDqs: 47
N1.C0.D0.R1.S04: RdPtrOffsetTxDq: 04
N3.C3.S08: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 008
N5.C1.D0.R0.S07: RdPtrOffsetTxDq: 06
N7.C0.D0.R1.S04: wrcmd2dqsstartlatency: 04
N1.C0.D0.R1.S04: RdPtrOffsetTxDqs: 06
N3.C3.D0.R0.S00: TxDqs: plus1 = 1, minus1 = 0, PI = 39, DB = 0
N5.C1.D0.R0.S08: RdPtrOffsetTxDq: 06
N7.C0.D0.R1.S04: RdPtrOffsetTxDq: 04
N1.C0.D0.R1.S04: PiTxDqs: 16
N3.C3.D0.R0.S00: TxDq : plus1 = 1, minus1 = 0, PI = 06, DB = 1
N5.C1.D0.R0.S09: RdPtrOffsetTxDq: 07
N7.C0.D0.R1.S04: RdPtrOffsetTxDqs: 06
N1.C0.D0.R1.S05: wrcmd2dqsstartlatency: 04
N3.C3.D0.R0.S01: TxDqs: plus1 = 1, minus1 = 0, PI = 20, DB = 0
N5.C1.D0.R0.S10: RdPtrOffsetTxDq: 06
N7.C0.D0.R1.S04: PiTxDqs: 14
N1.C0.D0.R1.S05: RdPtrOffsetTxDq: 04
N3.C3.D0.R0.S01: TxDq : plus1 = 1, minus1 = 0, PI = 50, DB = 1
N5.C1.D0.R0.S11: RdPtrOffsetTxDq: 06
N7.C0.D0.R1.S05: wrcmd2dqsstartlatency: 04
N1.C0.D0.R1.S05: RdPtrOffsetTxDqs: 06
N3.C3.D0.R0.S02: TxDqs: plus1 = 1, minus1 = 0, PI = 10, DB = 1
N5.C1.D0.R0.S12: RdPtrOffsetTxDq: 06
N7.C0.D0.R1.S05: RdPtrOffsetTxDq: 04
N1.C0.D0.R1.S05: PiTxDqs: 34
N3.C3.D0.R0.S02: TxDq : plus1 = 1, minus1 = 0, PI = 40, DB = 0
N5.C1.D0.R0.S13: RdPtrOffsetTxDq: 05
N7.C0.D0.R1.S05: RdPtrOffsetTxDqs: 06
N1.C0.D0.R1.S06: wrcmd2dqsstartlatency: 04
N3.C3.D0.R0.S03: TxDqs: plus1 = 1, minus1 = 0, PI = 58, DB = 1
N5.C1.D0.R0.S14: RdPtrOffsetTxDq: 06
N7.C0.D0.R1.S05: PiTxDqs: 33
N1.C0.D0.R1.S06: RdPtrOffsetTxDq: 05
N3.C3.D0.R0.S03: TxDq : plus1 = 1, minus1 = 0, PI = 23, DB = 0
N5.C1.D0.R0.S15: RdPtrOffsetTxDq: 06
N7.C0.D0.R1.S06: wrcmd2dqsstartlatency: 04
N1.C0.D0.R1.S06: RdPtrOffsetTxDqs: 06
N3.C3.D0.R0.S04: TxDqs: plus1 = 1, minus1 = 0, PI = 23, DB = 0
N5.C1.D0.R0.S16: RdPtrOffsetTxDq: 06
N7.C0.D0.R1.S06: RdPtrOffsetTxDq: 05
N1.C0.D0.R1.S06: PiTxDqs: 39
N3.C3.D0.R0.S04: TxDq : plus1 = 1, minus1 = 0, PI = 52, DB = 1
N5.C1.D0.R0.S17: RdPtrOffsetTxDq: 06
N7.C0.D0.R1.S06: RdPtrOffsetTxDqs: 06
N1.C0.D0.R1.S07: wrcmd2dqsstartlatency: 04
N3.C3.D0.R0.S05: TxDqs: plus1 = 1, minus1 = 0, PI = 37, DB = 0
N5.C1.D0.R0.S00: RdPtrOffsetTxDq: 08
N7.C0.D0.R1.S06: PiTxDqs: 36
N1.C0.D0.R1.S07: RdPtrOffsetTxDq: 05
N3.C3.D0.R0.S05: TxDq : plus1 = 1, minus1 = 0, PI = 04, DB = 1
N5.C1.D0.R0.S01: RdPtrOffsetTxDq: 07
N7.C0.D0.R1.S07: wrcmd2dqsstartlatency: 04
N1.C0.D0.R1.S07: RdPtrOffsetTxDqs: 06
N3.C3.D0.R0.S06: TxDqs: plus1 = 1, minus1 = 0, PI = 51, DB = 1
N5.C1.D0.R0.S02: RdPtrOffsetTxDq: 07
N7.C0.D0.R1.S07: RdPtrOffsetTxDq: 05
N1.C0.D0.R1.S07: PiTxDqs: 57
N3.C3.D0.R0.S06: TxDq : plus1 = 1, minus1 = 0, PI = 18, DB = 0
N5.C1.D0.R0.S03: RdPtrOffsetTxDq: 07
N7.C0.D0.R1.S07: RdPtrOffsetTxDqs: 06
N1.C0.D0.R1.S08: wrcmd2dqsstartlatency: 04
N3.C3.D0.R0.S07: TxDqs: plus1 = 1, minus1 = 0, PI = 06, DB = 1
N5.C1.D0.R0.S04: RdPtrOffsetTxDq: 06
N7.C0.D0.R1.S07: PiTxDqs: 56
N1.C0.D0.R1.S08: RdPtrOffsetTxDq: 04
N3.C3.D0.R0.S07: TxDq : plus1 = 1, minus1 = 0, PI = 35, DB = 0
N5.C1.D0.R0.S05: RdPtrOffsetTxDq: 07
N7.C0.D0.R1.S08: wrcmd2dqsstartlatency: 04
N1.C0.D0.R1.S08: RdPtrOffsetTxDqs: 06
N3.C3.D0.R0.S08: TxDqs: plus1 = 1, minus1 = 0, PI = 37, DB = 0
N5.C1.D0.R0.S06: RdPtrOffsetTxDq: 07
N7.C0.D0.R1.S08: RdPtrOffsetTxDq: 04
N1.C0.D0.R1.S08: PiTxDqs: 23
N3.C3.D0.R0.S08: TxDq : plus1 = 1, minus1 = 0, PI = 04, DB = 1
N5.C1.D0.R0.S07: RdPtrOffsetTxDq: 07
N7.C0.D0.R1.S08: RdPtrOffsetTxDqs: 06
N1.C0.D0.R1.S09: wrcmd2dqsstartlatency: 04
N3.C3.D0.R0.S09: TxDqs: plus1 = 1, minus1 = 0, PI = 36, DB = 0
N5.C1.D0.R0.S08: RdPtrOffsetTxDq: 07
N7.C0.D0.R1.S08: PiTxDqs: 22
N1.C0.D0.R1.S09: RdPtrOffsetTxDq: 05
N3.C3.D0.R0.S09: TxDq : plus1 = 1, minus1 = 0, PI = 03, DB = 1
N5.C1.D0.R0.S09: RdPtrOffsetTxDq: 08
N7.C0.D0.R1.S09: wrcmd2dqsstartlatency: 04
N1.C0.D0.R1.S09: RdPtrOffsetTxDqs: 07
N3.C3.D0.R0.S10: TxDqs: plus1 = 1, minus1 = 0, PI = 22, DB = 0
N5.C1.D0.R0.S10: RdPtrOffsetTxDq: 07
N7.C0.D0.R1.S09: RdPtrOffsetTxDq: 05
N1.C0.D0.R1.S09: PiTxDqs: 33
N3.C3.D0.R0.S10: TxDq : plus1 = 1, minus1 = 0, PI = 52, DB = 1
N5.C1.D0.R0.S11: RdPtrOffsetTxDq: 07
N7.C0.D0.R1.S09: RdPtrOffsetTxDqs: 07
N1.C0.D0.R1.S10: wrcmd2dqsstartlatency: 04
N3.C3.D0.R0.S11: TxDqs: plus1 = 1, minus1 = 0, PI = 10, DB = 1
N5.C1.D0.R0.S12: RdPtrOffsetTxDq: 07
N7.C0.D0.R1.S09: PiTxDqs: 31
N1.C0.D0.R1.S10: RdPtrOffsetTxDq: 05
N3.C3.D0.R0.S11: TxDq : plus1 = 1, minus1 = 0, PI = 41, DB = 0
N5.C1.D0.R0.S13: RdPtrOffsetTxDq: 06
N7.C0.D0.R1.S10: wrcmd2dqsstartlatency: 04
N1.C0.D0.R1.S10: RdPtrOffsetTxDqs: 07
N3.C3.D0.R0.S12: TxDqs: plus1 = 1, minus1 = 0, PI = 58, DB = 1
N5.C1.D0.R0.S14: RdPtrOffsetTxDq: 07
N7.C0.D0.R1.S10: RdPtrOffsetTxDq: 05
N1.C0.D0.R1.S10: PiTxDqs: 15
N3.C3.D0.R0.S12: TxDq : plus1 = 1, minus1 = 0, PI = 24, DB = 0
N5.C1.D0.R0.S15: RdPtrOffsetTxDq: 07
N7.C0.D0.R1.S10: RdPtrOffsetTxDqs: 07
N1.C0.D0.R1.S11: wrcmd2dqsstartlatency: 04
N3.C3.D0.R0.S13: TxDqs: plus1 = 1, minus1 = 0, PI = 23, DB = 0
N5.C1.D0.R0.S16: RdPtrOffsetTxDq: 07
N7.C0.D0.R1.S10: PiTxDqs: 11
N1.C0.D0.R1.S11: RdPtrOffsetTxDq: 05
N3.C3.D0.R0.S13: TxDq : plus1 = 1, minus1 = 0, PI = 53, DB = 1
N5.C1.D0.R0.S17: RdPtrOffsetTxDq: 07
N7.C0.D0.R1.S11: wrcmd2dqsstartlatency: 04
N1.C0.D0.R1.S11: RdPtrOffsetTxDqs: 07
N3.C3.D0.R0.S14: TxDqs: plus1 = 1, minus1 = 0, PI = 36, DB = 0
N5.C1.D0.R0.S00: Total Delay in PI ticks: TxDQ = 968
N7.C0.D0.R1.S11: RdPtrOffsetTxDq: 05
N1.C0.D0.R1.S11: PiTxDqs: 03
N3.C3.D0.R0.S14: TxDq : plus1 = 1, minus1 = 0, PI = 03, DB = 1
N5.C1.D0.R0.S01: Total Delay in PI ticks: TxDQ = 950
N7.C0.D0.R1.S11: RdPtrOffsetTxDqs: 06
N1.C0.D0.R1.S12: wrcmd2dqsstartlatency: 04
N3.C3.D0.R0.S15: TxDqs: plus1 = 1, minus1 = 0, PI = 52, DB = 1
N5.C1.D0.R0.S02: Total Delay in PI ticks: TxDQ = 940
N7.C0.D0.R1.S11: PiTxDqs: 63
N1.C0.D0.R1.S12: RdPtrOffsetTxDq: 05
N3.C3.D0.R0.S15: TxDq : plus1 = 1, minus1 = 0, PI = 18, DB = 0
N5.C1.D0.R0.S03: Total Delay in PI ticks: TxDQ = 924
N7.C0.D0.R1.S12: wrcmd2dqsstartlatency: 04
N1.C0.D0.R1.S12: RdPtrOffsetTxDqs: 06
N3.C3.D0.R0.S16: TxDqs: plus1 = 1, minus1 = 0, PI = 06, DB = 1
N5.C1.D0.R0.S04: Total Delay in PI ticks: TxDQ = 890
N7.C0.D0.R1.S12: RdPtrOffsetTxDq: 05
N1.C0.D0.R1.S12: PiTxDqs: 53
N3.C3.D0.R0.S16: TxDq : plus1 = 1, minus1 = 0, PI = 37, DB = 0
N5.C1.D0.R0.S05: Total Delay in PI ticks: TxDQ = 905
N7.C0.D0.R1.S12: RdPtrOffsetTxDqs: 06
N1.C0.D0.R1.S13: wrcmd2dqsstartlatency: 04
N3.C3.D0.R0.S17: TxDqs: plus1 = 1, minus1 = 0, PI = 37, DB = 0
N5.C1.D0.R0.S06: Total Delay in PI ticks: TxDQ = 920
N7.C0.D0.R1.S12: PiTxDqs: 46
N1.C0.D0.R1.S13: RdPtrOffsetTxDq: 04
N3.C3.D0.R0.S17: TxDq : plus1 = 1, minus1 = 0, PI = 05, DB = 1
N5.C1.D0.R0.S07: Total Delay in PI ticks: TxDQ = 937
N7.C0.D0.R1.S13: wrcmd2dqsstartlatency: 04
N1.C0.D0.R1.S13: RdPtrOffsetTxDqs: 06
N3.C3.D0.R1.S00: TxDqs: plus1 = 1, minus1 = 0, PI = 39, DB = 0
N5.C1.D0.R0.S08: Total Delay in PI ticks: TxDQ = 903
N7.C0.D0.R1.S13: RdPtrOffsetTxDq: 04
N1.C0.D0.R1.S13: PiTxDqs: 17
N3.C3.D0.R1.S00: TxDq : plus1 = 1, minus1 = 0, PI = 06, DB = 1
N5.C1.D0.R0.S09: Total Delay in PI ticks: TxDQ = 968
N7.C0.D0.R1.S13: RdPtrOffsetTxDqs: 06
N1.C0.D0.R1.S14: wrcmd2dqsstartlatency: 04
N3.C3.D0.R1.S01: TxDqs: plus1 = 1, minus1 = 0, PI = 20, DB = 0
N5.C1.D0.R0.S10: Total Delay in PI ticks: TxDQ = 950
N7.C0.D0.R1.S13: PiTxDqs: 14
N1.C0.D0.R1.S14: RdPtrOffsetTxDq: 04
N3.C3.D0.R1.S01: TxDq : plus1 = 1, minus1 = 0, PI = 50, DB = 1
N5.C1.D0.R0.S11: Total Delay in PI ticks: TxDQ = 942
N7.C0.D0.R1.S14: wrcmd2dqsstartlatency: 04
N1.C0.D0.R1.S14: RdPtrOffsetTxDqs: 06
N3.C3.D0.R1.S02: TxDqs: plus1 = 1, minus1 = 0, PI = 10, DB = 1
N5.C1.D0.R0.S12: Total Delay in PI ticks: TxDQ = 924
N7.C0.D0.R1.S14: RdPtrOffsetTxDq: 04
N1.C0.D0.R1.S14: PiTxDqs: 33
N3.C3.D0.R1.S02: TxDq : plus1 = 1, minus1 = 0, PI = 40, DB = 0
N5.C1.D0.R0.S13: Total Delay in PI ticks: TxDQ = 893
N7.C0.D0.R1.S14: RdPtrOffsetTxDqs: 06
N1.C0.D0.R1.S15: wrcmd2dqsstartlatency: 04
N3.C3.D0.R1.S03: TxDqs: plus1 = 1, minus1 = 0, PI = 58, DB = 1
N5.C1.D0.R0.S14: Total Delay in PI ticks: TxDQ = 905
N7.C0.D0.R1.S14: PiTxDqs: 32
N1.C0.D0.R1.S15: RdPtrOffsetTxDq: 05
N3.C3.D0.R1.S03: TxDq : plus1 = 1, minus1 = 0, PI = 23, DB = 0
N5.C1.D0.R0.S15: Total Delay in PI ticks: TxDQ = 918
N7.C0.D0.R1.S15: wrcmd2dqsstartlatency: 04
N1.C0.D0.R1.S15: RdPtrOffsetTxDqs: 06
N3.C3.D0.R1.S04: TxDqs: plus1 = 1, minus1 = 0, PI = 23, DB = 0
N5.C1.D0.R0.S16: Total Delay in PI ticks: TxDQ = 936
N7.C0.D0.R1.S15: RdPtrOffsetTxDq: 05
N1.C0.D0.R1.S15: PiTxDqs: 39
N3.C3.D0.R1.S04: TxDq : plus1 = 1, minus1 = 0, PI = 52, DB = 1
N5.C1.D0.R0.S17: Total Delay in PI ticks: TxDQ = 905
N7.C0.D0.R1.S15: RdPtrOffsetTxDqs: 06
N1.C0.D0.R1.S16: wrcmd2dqsstartlatency: 04
N3.C3.D0.R1.S05: TxDqs: plus1 = 1, minus1 = 0, PI = 37, DB = 0
N5.C1.D0.R1.S00: wrcmd2dqsstartlatency: 04
N7.C0.D0.R1.S15: PiTxDqs: 36
N1.C0.D0.R1.S16: RdPtrOffsetTxDq: 05
N3.C3.D0.R1.S05: TxDq : plus1 = 1, minus1 = 0, PI = 04, DB = 1
N5.C1.D0.R1.S00: RdPtrOffsetTxDq: 06
N7.C0.D0.R1.S16: wrcmd2dqsstartlatency: 04
N1.C0.D0.R1.S16: RdPtrOffsetTxDqs: 06
N3.C3.D0.R1.S06: TxDqs: plus1 = 1, minus1 = 0, PI = 51, DB = 1
N5.C1.D0.R1.S00: RdPtrOffsetTxDqs: 07
N7.C0.D0.R1.S16: RdPtrOffsetTxDq: 05
N1.C0.D0.R1.S16: PiTxDqs: 56
N3.C3.D0.R1.S06: TxDq : plus1 = 1, minus1 = 0, PI = 18, DB = 0
N5.C1.D0.R1.S00: PiTxDqs: 41
N7.C0.D0.R1.S16: RdPtrOffsetTxDqs: 06
N1.C0.D0.R1.S17: wrcmd2dqsstartlatency: 04
N3.C3.D0.R1.S07: TxDqs: plus1 = 1, minus1 = 0, PI = 06, DB = 1
N5.C1.D0.R1.S01: wrcmd2dqsstartlatency: 04
N7.C0.D0.R1.S16: PiTxDqs: 56
N1.C0.D0.R1.S17: RdPtrOffsetTxDq: 04
N3.C3.D0.R1.S07: TxDq : plus1 = 1, minus1 = 0, PI = 35, DB = 0
N5.C1.D0.R1.S01: RdPtrOffsetTxDq: 05
N7.C0.D0.R1.S17: wrcmd2dqsstartlatency: 04
N1.C0.D0.R1.S17: RdPtrOffsetTxDqs: 06
N3.C3.D0.R1.S08: TxDqs: plus1 = 1, minus1 = 0, PI = 37, DB = 0
N5.C1.D0.R1.S01: RdPtrOffsetTxDqs: 07
N7.C0.D0.R1.S17: RdPtrOffsetTxDq: 04
N1.C0.D0.R1.S17: PiTxDqs: 24
N3.C3.D0.R1.S08: TxDq : plus1 = 1, minus1 = 0, PI = 04, DB = 1
N5.C1.D0.R1.S01: PiTxDqs: 24
N7.C0.D0.R1.S17: RdPtrOffsetTxDqs: 06
N1.C0.D0.R1.S00: RdPtrOffsetTxDq: 07
N3.C3.D0.R1.S09: TxDqs: plus1 = 1, minus1 = 0, PI = 36, DB = 0
N5.C1.D0.R1.S02: wrcmd2dqsstartlatency: 04
N7.C0.D0.R1.S17: PiTxDqs: 23
N1.C0.D0.R1.S01: RdPtrOffsetTxDq: 06
N3.C3.D0.R1.S09: TxDq : plus1 = 1, minus1 = 0, PI = 03, DB = 1
N5.C1.D0.R1.S02: RdPtrOffsetTxDq: 05
N7.C0.D0.R1.S00: RdPtrOffsetTxDq: 06
N1.C0.D0.R1.S02: RdPtrOffsetTxDq: 06
N3.C3.D0.R1.S10: TxDqs: plus1 = 1, minus1 = 0, PI = 22, DB = 0
N5.C1.D0.R1.S02: RdPtrOffsetTxDqs: 07
N7.C0.D0.R1.S01: RdPtrOffsetTxDq: 06
N1.C0.D0.R1.S03: RdPtrOffsetTxDq: 06
N3.C3.D0.R1.S10: TxDq : plus1 = 1, minus1 = 0, PI = 52, DB = 1
N5.C1.D0.R1.S02: PiTxDqs: 13
N7.C0.D0.R1.S02: RdPtrOffsetTxDq: 06
N1.C0.D0.R1.S04: RdPtrOffsetTxDq: 05
N3.C3.D0.R1.S11: TxDqs: plus1 = 1, minus1 = 0, PI = 10, DB = 1
N5.C1.D0.R1.S03: wrcmd2dqsstartlatency: 04
N7.C0.D0.R1.S03: RdPtrOffsetTxDq: 06
N1.C0.D0.R1.S05: RdPtrOffsetTxDq: 05
N3.C3.D0.R1.S11: TxDq : plus1 = 1, minus1 = 0, PI = 41, DB = 0
N5.C1.D0.R1.S03: RdPtrOffsetTxDq: 05
N7.C0.D0.R1.S04: RdPtrOffsetTxDq: 05
N1.C0.D0.R1.S06: RdPtrOffsetTxDq: 06
N3.C3.D0.R1.S12: TxDqs: plus1 = 1, minus1 = 0, PI = 58, DB = 1
N5.C1.D0.R1.S03: RdPtrOffsetTxDqs: 06
N7.C0.D0.R1.S05: RdPtrOffsetTxDq: 05
N1.C0.D0.R1.S07: RdPtrOffsetTxDq: 06
N3.C3.D0.R1.S12: TxDq : plus1 = 1, minus1 = 0, PI = 24, DB = 0
N5.C1.D0.R1.S03: PiTxDqs: 59
N7.C0.D0.R1.S06: RdPtrOffsetTxDq: 06
N1.C0.D0.R1.S08: RdPtrOffsetTxDq: 05
N3.C3.D0.R1.S13: TxDqs: plus1 = 1, minus1 = 0, PI = 23, DB = 0
N5.C1.D0.R1.S04: wrcmd2dqsstartlatency: 04
N7.C0.D0.R1.S07: RdPtrOffsetTxDq: 06
N1.C0.D0.R1.S09: RdPtrOffsetTxDq: 06
N3.C3.D0.R1.S13: TxDq : plus1 = 1, minus1 = 0, PI = 53, DB = 1
N5.C1.D0.R1.S04: RdPtrOffsetTxDq: 04
N7.C0.D0.R1.S08: RdPtrOffsetTxDq: 05
N1.C0.D0.R1.S10: RdPtrOffsetTxDq: 06
N3.C3.D0.R1.S14: TxDqs: plus1 = 1, minus1 = 0, PI = 36, DB = 0
N5.C1.D0.R1.S04: RdPtrOffsetTxDqs: 06
N7.C0.D0.R1.S09: RdPtrOffsetTxDq: 06
N1.C0.D0.R1.S11: RdPtrOffsetTxDq: 06
N3.C3.D0.R1.S14: TxDq : plus1 = 1, minus1 = 0, PI = 03, DB = 1
N5.C1.D0.R1.S04: PiTxDqs: 27
N7.C0.D0.R1.S10: RdPtrOffsetTxDq: 06
N1.C0.D0.R1.S12: RdPtrOffsetTxDq: 06
N3.C3.D0.R1.S15: TxDqs: plus1 = 1, minus1 = 0, PI = 52, DB = 1
N5.C1.D0.R1.S05: wrcmd2dqsstartlatency: 04
N7.C0.D0.R1.S11: RdPtrOffsetTxDq: 06
N1.C0.D0.R1.S13: RdPtrOffsetTxDq: 05
N3.C3.D0.R1.S15: TxDq : plus1 = 1, minus1 = 0, PI = 18, DB = 0
N5.C1.D0.R1.S05: RdPtrOffsetTxDq: 05
N7.C0.D0.R1.S12: RdPtrOffsetTxDq: 06
N1.C0.D0.R1.S14: RdPtrOffsetTxDq: 05
N3.C3.D0.R1.S16: TxDqs: plus1 = 1, minus1 = 0, PI = 06, DB = 1
N5.C1.D0.R1.S05: RdPtrOffsetTxDqs: 06
N7.C0.D0.R1.S13: RdPtrOffsetTxDq: 05
N1.C0.D0.R1.S15: RdPtrOffsetTxDq: 06
N3.C3.D0.R1.S16: TxDq : plus1 = 1, minus1 = 0, PI = 37, DB = 0
N5.C1.D0.R1.S05: PiTxDqs: 43
N7.C0.D0.R1.S14: RdPtrOffsetTxDq: 05
N1.C0.D0.R1.S16: RdPtrOffsetTxDq: 06
N3.C3.D0.R1.S17: TxDqs: plus1 = 1, minus1 = 0, PI = 37, DB = 0
N5.C1.D0.R1.S06: wrcmd2dqsstartlatency: 04
N7.C0.D0.R1.S15: RdPtrOffsetTxDq: 06
N1.C0.D0.R1.S17: RdPtrOffsetTxDq: 05
N3.C3.D0.R1.S17: TxDq : plus1 = 1, minus1 = 0, PI = 05, DB = 1
N5.C1.D0.R1.S06: RdPtrOffsetTxDq: 05
N7.C0.D0.R1.S16: RdPtrOffsetTxDq: 06
N1.C0.D0.R1.S00: RdPtrOffsetTxDq: 08
END_DATA_TX_DQ
N5.C1.D0.R1.S06: RdPtrOffsetTxDqs: 06
N7.C0.D0.R1.S17: RdPtrOffsetTxDq: 05
N1.C0.D0.R1.S01: RdPtrOffsetTxDq: 07
N3: RunTrainStep: Final status = 0
N5.C1.D0.R1.S06: PiTxDqs: 55
N7.C0.D0.R1.S00: RdPtrOffsetTxDq: 07
N1.C0.D0.R1.S02: RdPtrOffsetTxDq: 07

END - Basic Write DQ/DQS Training      Time         26492 ms
N5.C1.D0.R1.S07: wrcmd2dqsstartlatency: 04
N7.C0.D0.R1.S01: RdPtrOffsetTxDq: 07
N1.C0.D0.R1.S03: RdPtrOffsetTxDq: 07
N3.C0: JCK cmd timing = 1N
N5.C1.D0.R1.S07: RdPtrOffsetTxDq: 05
N7.C0.D0.R1.S02: RdPtrOffsetTxDq: 07
N1.C0.D0.R1.S04: RdPtrOffsetTxDq: 06
N3.C0: RdCmd2DataValidLatency = 21, (dlyFrmS = 15, clEff = 10, earlyCas = 0, selNTiming = 0)
N5.C1.D0.R1.S07: RdPtrOffsetTxDqs: 07
N7.C0.D0.R1.S03: RdPtrOffsetTxDq: 07
N1.C0.D0.R1.S05: RdPtrOffsetTxDq: 06
N3.C1: RdCmd2DataValidLatency = 21, (dlyFrmS = 15, clEff = 10, earlyCas = 0, selNTiming = 0)
N5.C1.D0.R1.S07: PiTxDqs: 11
N7.C0.D0.R1.S04: RdPtrOffsetTxDq: 06
N1.C0.D0.R1.S06: RdPtrOffsetTxDq: 07
N3.C2: JCK cmd timing = 1N
N5.C1.D0.R1.S08: wrcmd2dqsstartlatency: 04
N7.C0.D0.R1.S05: RdPtrOffsetTxDq: 06
N1.C0.D0.R1.S07: RdPtrOffsetTxDq: 07
N3.C2: RdCmd2DataValidLatency = 21, (dlyFrmS = 15, clEff = 10, earlyCas = 0, selNTiming = 0)
N5.C1.D0.R1.S08: RdPtrOffsetTxDq: 05
N7.C0.D0.R1.S06: RdPtrOffsetTxDq: 07
N1.C0.D0.R1.S08: RdPtrOffsetTxDq: 06
N3.C3: RdCmd2DataValidLatency = 21, (dlyFrmS = 15, clEff = 10, earlyCas = 0, selNTiming = 0)
N5.C1.D0.R1.S08: RdPtrOffsetTxDqs: 06
N7.C0.D0.R1.S07: RdPtrOffsetTxDq: 07
N1.C0.D0.R1.S09: RdPtrOffsetTxDq: 07
N3: JckSetOdtDynTiming[2] BL8:
N5.C1.D0.R1.S08: PiTxDqs: 40
N7.C0.D0.R1.S08: RdPtrOffsetTxDq: 06
N1.C0.D0.R1.S10: RdPtrOffsetTxDq: 07
N5.C1.D0.R1.S09: wrcmd2dqsstartlatency: 04
N7.C0.D0.R1.S09: RdPtrOffsetTxDq: 07
N1.C0.D0.R1.S11: RdPtrOffsetTxDq: 07
N3.C0: minRcvEnDelay = 201 maxRcvEnDelay = 293 ==> rdwidth = 6 rddly = 2 wrwidth = 6 wrdly = 0
N5.C1.D0.R1.S09: RdPtrOffsetTxDq: 06
N7.C0.D0.R1.S10: RdPtrOffsetTxDq: 07
N1.C0.D0.R1.S12: RdPtrOffsetTxDq: 07
N3.C1: minRcvEnDelay = 196 maxRcvEnDelay = 316 ==> rdwidth = 6 rddly = 2 wrwidth = 6 wrdly = 0
N5.C1.D0.R1.S09: RdPtrOffsetTxDqs: 07
N7.C0.D0.R1.S11: RdPtrOffsetTxDq: 07
N1.C0.D0.R1.S13: RdPtrOffsetTxDq: 06
N3.C2: minRcvEnDelay = 195 maxRcvEnDelay = 284 ==> rdwidth = 6 rddly = 2 wrwidth = 6 wrdly = 0
N5.C1.D0.R1.S09: PiTxDqs: 39
N7.C0.D0.R1.S12: RdPtrOffsetTxDq: 07
N1.C0.D0.R1.S14: RdPtrOffsetTxDq: 06
N3.C3: minRcvEnDelay = 196 maxRcvEnDelay = 309 ==> rdwidth = 6 rddly = 2 wrwidth = 6 wrdly = 0
N5.C1.D0.R1.S10: wrcmd2dqsstartlatency: 04
N7.C0.D0.R1.S13: RdPtrOffsetTxDq: 06
N1.C0.D0.R1.S15: RdPtrOffsetTxDq: 07
N3.C0: Memory Electrical TurnAround timings:
N5.C1.D0.R1.S10: RdPtrOffsetTxDq: 05
N7.C0.D0.R1.S14: RdPtrOffsetTxDq: 06
N1.C0.D0.R1.S16: RdPtrOffsetTxDq: 07
N3.C0:      tCCD  =  0, tWWDR =  3, tRRDD =  2, tWWDD =  3, tWRDR =  1, tWRDR_UPPER =  0, tRRDR =  0
N5.C1.D0.R1.S10: RdPtrOffsetTxDqs: 07
N7.C0.D0.R1.S15: RdPtrOffsetTxDq: 07
N1.C0.D0.R1.S17: RdPtrOffsetTxDq: 06
N3.C0:      tRWDD =  2, tRWDR =  2, tWRDD =  1, tRWSR =  2
N5.C1.D0.R1.S10: PiTxDqs: 25
N7.C0.D0.R1.S16: RdPtrOffsetTxDq: 07
N1.C0.D0.R1.S00: Total Delay in PI ticks: TxDQ = 963
N3.C0: TCOTHP: T_RWSR = 0x2, T_RWDD = 0x2
N5.C1.D0.R1.S11: wrcmd2dqsstartlatency: 04
N7.C0.D0.R1.S17: RdPtrOffsetTxDq: 06
N1.C0.D0.R1.S01: Total Delay in PI ticks: TxDQ = 942
N3.C0:      tCCD_WR =  0, tWRDS =  2, tRWDS =  2, tWWDS =  3, tRRDS =  1
N5.C1.D0.R1.S11: RdPtrOffsetTxDq: 05
N7.C0.D0.R1.S00: Total Delay in PI ticks: TxDQ = 956
N1.C0.D0.R1.S02: Total Delay in PI ticks: TxDQ = 929
N3.C1: Memory Electrical TurnAround timings:
N5.C1.D0.R1.S11: RdPtrOffsetTxDqs: 07
N7.C0.D0.R1.S01: Total Delay in PI ticks: TxDQ = 936
N1.C0.D0.R1.S03: Total Delay in PI ticks: TxDQ = 910
N3.C1:      tCCD  =  0, tWWDR =  3, tRRDD =  2, tWWDD =  3, tWRDR =  1, tWRDR_UPPER =  0, tRRDR =  0
N5.C1.D0.R1.S11: PiTxDqs: 13
N7.C0.D0.R1.S02: Total Delay in PI ticks: TxDQ = 924
N1.C0.D0.R1.S04: Total Delay in PI ticks: TxDQ = 879
N3.C1:      tRWDD =  2, tRWDR =  2, tWRDD =  1, tRWSR =  2
N5.C1.D0.R1.S12: wrcmd2dqsstartlatency: 04
N7.C0.D0.R1.S03: Total Delay in PI ticks: TxDQ = 908
N1.C0.D0.R1.S05: Total Delay in PI ticks: TxDQ = 897
N3.C1: TCOTHP: T_RWSR = 0x2, T_RWDD = 0x2
N5.C1.D0.R1.S12: RdPtrOffsetTxDq: 05
N7.C0.D0.R1.S04: Total Delay in PI ticks: TxDQ = 877
N1.C0.D0.R1.S06: Total Delay in PI ticks: TxDQ = 901
N3.C1:      tCCD_WR =  0, tWRDS =  2, tRWDS =  2, tWWDS =  3, tRRDS =  1
N5.C1.D0.R1.S12: RdPtrOffsetTxDqs: 06
N7.C0.D0.R1.S05: Total Delay in PI ticks: TxDQ = 895
N1.C0.D0.R1.S07: Total Delay in PI ticks: TxDQ = 918
N3.C2: Memory Electrical TurnAround timings:
N5.C1.D0.R1.S12: PiTxDqs: 62
N7.C0.D0.R1.S06: Total Delay in PI ticks: TxDQ = 898
N1.C0.D0.R1.S08: Total Delay in PI ticks: TxDQ = 884
N3.C2:      tCCD  =  0, tWWDR =  3, tRRDD =  2, tWWDD =  3, tWRDR =  1, tWRDR_UPPER =  0, tRRDR =  0
N5.C1.D0.R1.S13: wrcmd2dqsstartlatency: 04
N7.C0.D0.R1.S07: Total Delay in PI ticks: TxDQ = 917
N1.C0.D0.R1.S09: Total Delay in PI ticks: TxDQ = 959
N3.C2:      tRWDD =  2, tRWDR =  2, tWRDD =  1, tRWSR =  2
N5.C1.D0.R1.S13: RdPtrOffsetTxDq: 04
N7.C0.D0.R1.S08: Total Delay in PI ticks: TxDQ = 884
N1.C0.D0.R1.S10: Total Delay in PI ticks: TxDQ = 942
N3.C2: TCOTHP: T_RWSR = 0x2, T_RWDD = 0x2
N5.C1.D0.R1.S13: RdPtrOffsetTxDqs: 06
N7.C0.D0.R1.S09: Total Delay in PI ticks: TxDQ = 957
N1.C0.D0.R1.S11: Total Delay in PI ticks: TxDQ = 927
N3.C2:      tCCD_WR =  0, tWRDS =  2, tRWDS =  2, tWWDS =  3, tRRDS =  1
N5.C1.D0.R1.S13: PiTxDqs: 31
N7.C0.D0.R1.S10: Total Delay in PI ticks: TxDQ = 936
N1.C0.D0.R1.S12: Total Delay in PI ticks: TxDQ = 914
N3.C3: Memory Electrical TurnAround timings:
N5.C1.D0.R1.S14: wrcmd2dqsstartlatency: 04
N7.C0.D0.R1.S11: Total Delay in PI ticks: TxDQ = 924
N1.C0.D0.R1.S13: Total Delay in PI ticks: TxDQ = 879
N3.C3:      tCCD  =  0, tWWDR =  3, tRRDD =  2, tWWDD =  3, tWRDR =  1, tWRDR_UPPER =  0, tRRDR =  0
N5.C1.D0.R1.S14: RdPtrOffsetTxDq: 05
N7.C0.D0.R1.S12: Total Delay in PI ticks: TxDQ = 907
N1.C0.D0.R1.S14: Total Delay in PI ticks: TxDQ = 897
N3.C3:      tRWDD =  2, tRWDR =  2, tWRDD =  1, tRWSR =  2
N5.C1.D0.R1.S14: RdPtrOffsetTxDqs: 06
N7.C0.D0.R1.S13: Total Delay in PI ticks: TxDQ = 877
N1.C0.D0.R1.S15: Total Delay in PI ticks: TxDQ = 903
N3.C3: TCOTHP: T_RWSR = 0x2, T_RWDD = 0x2
N5.C1.D0.R1.S14: PiTxDqs: 42
N7.C0.D0.R1.S14: Total Delay in PI ticks: TxDQ = 895
N1.C0.D0.R1.S16: Total Delay in PI ticks: TxDQ = 918
N3.C3:      tCCD_WR =  0, tWRDS =  2, tRWDS =  2, tWWDS =  3, tRRDS =  1
N5.C1.D0.R1.S15: wrcmd2dqsstartlatency: 04
N7.C0.D0.R1.S15: Total Delay in PI ticks: TxDQ = 899
N1.C0.D0.R1.S17: Total Delay in PI ticks: TxDQ = 885

START - Rd Timing Centering 2D Training
N5.C1.D0.R1.S15: RdPtrOffsetTxDq: 05
N7.C0.D0.R1.S16: Total Delay in PI ticks: TxDQ = 917
N1.C0: Calculating Optimimum DQ/DQS Values
N3: 

Adv Strobe Centering(MARGIN_RX_DQ): GetMultiVref: patternLength = 13, stepSize = 1, numPoints = 1
N5.C1.D0.R1.S15: RdPtrOffsetTxDqs: 06
N7.C0.D0.R1.S17: Total Delay in PI ticks: TxDQ = 884
START_DATA_TX_DQ
N3: GetMargins: Level = 1, group = 11, mode = 0, scope = 4
N5.C1.D0.R1.S15: PiTxDqs: 58
N7.C0: Calculating Optimimum DQ/DQS Values
N1.C0.S00: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 009
N5.C1.D0.R1.S16: wrcmd2dqsstartlatency: 04
N1.C0.S00: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 009
N5.C1.D0.R1.S16: RdPtrOffsetTxDq: 05
START_DATA_TX_DQ
N1.C0.S01: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 009
N5.C1.D0.R1.S16: RdPtrOffsetTxDqs: 07
N7.C0.S00: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 009
N1.C0.S01: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 009
N5.C1.D0.R1.S16: PiTxDqs: 10
N7.C0.S00: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 009
N1.C0.S02: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 009
N5.C1.D0.R1.S17: wrcmd2dqsstartlatency: 04
N7.C0.S01: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 009
N1.C0.S02: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 009
N5.C1.D0.R1.S17: RdPtrOffsetTxDq: 05
N7.C0.S01: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 009
N1.C0.S03: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 008
N5.C1.D0.R1.S17: RdPtrOffsetTxDqs: 06
N7.C0.S02: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 008
N1.C0.S03: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 008
N5.C1.D0.R1.S17: PiTxDqs: 41
N7.C0.S02: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 008
N1.C0.S04: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 007, RdPtrOffsetTxDqs = 008
N5.C1.D0.R1.S00: RdPtrOffsetTxDq: 07
N7.C0.S03: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 008
N1.C0.S04: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 007, RdPtrOffsetTxDqs = 008
N5.C1.D0.R1.S01: RdPtrOffsetTxDq: 06
N7.C0.S03: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 008
N1.C0.S05: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 008
N5.C1.D0.R1.S02: RdPtrOffsetTxDq: 06
N7.C0.S04: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 007, RdPtrOffsetTxDqs = 008
N1.C0.S05: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 008
N5.C1.D0.R1.S03: RdPtrOffsetTxDq: 06
N7.C0.S04: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 007, RdPtrOffsetTxDqs = 008
N1.C0.S06: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 008
N5.C1.D0.R1.S04: RdPtrOffsetTxDq: 05
N7.C0.S05: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 007, RdPtrOffsetTxDqs = 008
N1.C0.S06: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 008
N5.C1.D0.R1.S05: RdPtrOffsetTxDq: 06
N7.C0.S05: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 007, RdPtrOffsetTxDqs = 008
N1.C0.S07: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 008
N5.C1.D0.R1.S06: RdPtrOffsetTxDq: 06
N7.C0.S06: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 008
N1.C0.S07: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 008
N5.C1.D0.R1.S07: RdPtrOffsetTxDq: 06
N7.C0.S06: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 008
N1.C0.S08: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 007, RdPtrOffsetTxDqs = 008
N5.C1.D0.R1.S08: RdPtrOffsetTxDq: 06
N7.C0.S07: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 008
N1.C0.S08: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 007, RdPtrOffsetTxDqs = 008
N5.C1.D0.R1.S09: RdPtrOffsetTxDq: 07
N7.C0.S07: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 008
N1.C0.D0.R0.S00: TxDqs: plus1 = 1, minus1 = 0, PI = 33, DB = 0
N5.C1.D0.R1.S10: RdPtrOffsetTxDq: 06
N7.C0.S08: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 007, RdPtrOffsetTxDqs = 008
N1.C0.D0.R0.S00: TxDq : plus1 = 0, minus1 = 1, PI = 02, DB = 1
N5.C1.D0.R1.S11: RdPtrOffsetTxDq: 06
N7.C0.S08: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 007, RdPtrOffsetTxDqs = 008
N1.C0.D0.R0.S01: TxDqs: plus1 = 1, minus1 = 0, PI = 15, DB = 1
N5.C1.D0.R1.S12: RdPtrOffsetTxDq: 06
N7.C0.D0.R0.S00: TxDqs: plus1 = 1, minus1 = 0, PI = 32, DB = 0
N1.C0.D0.R0.S01: TxDq : plus1 = 1, minus1 = 0, PI = 46, DB = 0
START_DATA_RX_DQS_ADV
Results for N3.C0.D0.R0: 
           0   1   2   3   4   5   6   7   8   9  10  11  12  13  14  15  16  17
-------------------------------------------------------------------------------
Vref offset: 0
Left:    -22 -24 -22 -18 -23 -24 -24 -23 -23 -25 -22 -22 -19 -24 -22 -20 -22 -19
Right:    23  27  25  31  23  22  26  18  24  23  27  25  31  21  22  26  23  23
-------------------------------------------------------------------------------
Prev Pi:  29  34  34  36  34  36  33  33  34  33  34  31  35  34  35  30  30  34
New Pi:   29  35  35  42  34  35  34  31  34  32  36  32  41  33  35  33  30  36
Diff:      0   1   1   6   0  -1   1  -2   0  -1   2   1   6  -1   0   3   0   2

Results for N3.C0.D0.R1: 
           0   1   2   3   4   5   6   7   8   9  10  11  12  13  14  15  16  17
-------------------------------------------------------------------------------
Vref offset: 0
Left:    -22 -24 -22 -18 -23 -23 -23 -23 -23 -25 -22 -22 -19 -24 -22 -19 -21 -19
Right:    22  25  26  31  23  19  27  18  25  23  27  26  28  20  20  23  21  24
-------------------------------------------------------------------------------
Prev Pi:  29  34  34  36  34  36  33  33  34  33  34  31  35  34  35  30  30  34
New Pi:   29  34  36  42  34  34  35  31  35  32  36  33  39  32  34  32  30  36
Diff:      0   0   2   6   0  -2   2  -2   1  -1   2   2   4  -2  -1   2   0   2

Results for N3.C1.D0.R0: 
           0   1   2   3   4   5   6   7   8   9  10  11  12  13  14  15  16  17
-------------------------------------------------------------------------------
Vref offset: 0
Left:    -18 -21 -17 -25 -24 -23 -23 -21 -23 -25 -25 -24 -24 -22 -21 -24 -21 -23
Right:    19  26  18  24  24  18  25  22  23  18  26  23  27  23  22  24  22  24
-------------------------------------------------------------------------------
Prev Pi:  28  34  32  35  34  36  33  34  34  34  34  32  34  30  32  34  32  34
New Pi:   28  36  32  35  34  34  34  34  34  31  34  32  35  30  32  34  32  34
Diff:      0   2   0   0   0  -2   1   0   0  -3   0   0   1   0   0   0   0   0

Results for N3.C1.D0.R1: 
           0   1   2   3   4   5   6   7   8   9  10  11  12  13  14  15  16  17
-------------------------------------------------------------------------------
Vref offset: 0
Left:    -18 -22 -17 -25 -24 -22 -23 -21 -22 -25 -25 -24 -23 -22 -20 -24 -21 -23
Right:    19  29  18  25  21  20  24  23  18  19  26  24  26  24  20  23  22  24
-------------------------------------------------------------------------------
Prev Pi:  28  34  32  35  34  36  33  34  34  34  34  32  34  30  32  34  32  34
New Pi:   28  37  32  35  33  35  33  35  32  31  34  32  35  31  32  34  32  34
Diff:      0   3   0   0  -1  -1   0   1  -2  -3   0   0   1   1   0   0   0   0

Results for N3.C2.D0.R0: 
           0   1   2   3   4   5   6   7   8   9  10  11  12  13  14  15  16  17
-------------------------------------------------------------------------------
Vref offset: 0
Left:    -22 -22 -24 -24 -22 -23 -25 -24 -22 -23 -26 -21 -21 -24 -21 -21 -22 -21
Right:    26  28  25  31  31  24  24  23  28  26  26  27  31  25  25  24  23  26
-------------------------------------------------------------------------------
Prev Pi:  33  34  34  35  32  35  35  33  36  33  35  33  34  33  35  34  31  34
New Pi:   35  37  34  38  36  35  35  33  39  34  35  36  39  33  37  35  31  36
Diff:      2   3   0   3   4   0   0   0   3   1   0   3   5   0   2   1   0   2

Results for N3.C2.D0.R1: 
           0   1   2   3   4   5   6   7   8   9  10  11  12  13  14  15  16  17
-------------------------------------------------------------------------------
Vref offset: 0
Left:    -21 -22 -24 -24 -22 -23 -25 -24 -22 -24 -26 -22 -21 -24 -20 -21 -22 -21
Right:    25  28  28  31  30  22  24  24  28  27  27  28  31  27  25  25  21  29
-------------------------------------------------------------------------------
Prev Pi:  33  34  34  35  32  35  35  33  36  33  35  33  34  33  35  34  31  34
New Pi:   35  37  36  38  36  35  35  33  39  34  35  36  39  34  37  36  31  38
Diff:      2   3   2   3   4   0   0   0   3   1   0   3   5   1   2   2   0   4

Results for N3.C3.D0.R0: 
           0   1   2   3   4   5   6   7   8   9  10  11  12  13  14  15  16  17
-------------------------------------------------------------------------------
Vref offset: 0
Left:    -21 -21 -20 -17 -25 -24 -22 -21 -21 -20 -26 -21 -21 -22 -25 -23 -23 -22
Right:    25  24  28  31  31  24  26  24  27  25  28  27  31  27  25  28  23  22
-------------------------------------------------------------------------------
Prev Pi:  35  33  33  34  35  34  36  34  33  35  35  33  36  34  33  35  31  33
New Pi:   37  34  37  41  38  34  38  35  36  37  36  36  41  36  33  37  31  33
Diff:      2   1   4   7   3   0   2   1   3   2   1   3   5   2   0   2   0   0

Results for N3.C3.D0.R1: 
           0   1   2   3   4   5   6   7   8   9  10  11  12  13  14  15  16  17
-------------------------------------------------------------------------------
Vref offset: 0
Left:    -21 -21 -21 -17 -25 -24 -22 -22 -21 -21 -26 -21 -21 -22 -24 -22 -23 -23
Right:    24  26  29  31  31  23  25  23  28  25  26  26  31  29  24  28  21  21
-------------------------------------------------------------------------------
Prev Pi:  35  33  33  34  35  34  36  34  33  35  35  33  36  34  33  35  31  33
New Pi:   36  35  37  41  38  34  37  34  36  37  35  35  41  37  33  38  30  32
Diff:      1   2   4   7   3   0   1   0   3   2   0   2   5   3   0   3  -1  -1

STOP_DATA_RX_DQS_ADV
N5.C1.D0.R1.S13: RdPtrOffsetTxDq: 05
N7.C0.D0.R0.S00: TxDq : plus1 = 1, minus1 = 0, PI = 62, DB = 1
N1.C0.D0.R0.S02: TxDqs: plus1 = 1, minus1 = 0, PI = 03, DB = 1
N3: RunTrainStep: Final status = 0
N5.C1.D0.R1.S14: RdPtrOffsetTxDq: 06
N7.C0.D0.R0.S01: TxDqs: plus1 = 1, minus1 = 0, PI = 11, DB = 1
N1.C0.D0.R0.S02: TxDq : plus1 = 1, minus1 = 0, PI = 33, DB = 0

END - Rd Timing Centering 2D Training  Time         1221 ms
N5.C1.D0.R1.S15: RdPtrOffsetTxDq: 06
N7.C0.D0.R0.S01: TxDq : plus1 = 1, minus1 = 0, PI = 40, DB = 0
N1.C0.D0.R0.S03: TxDqs: plus1 = 1, minus1 = 0, PI = 50, DB = 1

START - Wr Timing Centering 2D Training
N5.C1.D0.R1.S16: RdPtrOffsetTxDq: 06
N7.C0.D0.R0.S02: TxDqs: plus1 = 1, minus1 = 0, PI = 63, DB = 1
N1.C0.D0.R0.S03: TxDq : plus1 = 1, minus1 = 0, PI = 15, DB = 1
N3: 

Adv Strobe Centering(MARGIN_TX_DQ): GetMultiVref: patternLength = 13, stepSize = 1, numPoints = 1
N5.C1.D0.R1.S17: RdPtrOffsetTxDq: 06
N7.C0.D0.R0.S02: TxDq : plus1 = 1, minus1 = 0, PI = 29, DB = 0
N1.C0.D0.R0.S04: TxDqs: plus1 = 1, minus1 = 0, PI = 16, DB = 0
N3: GetMargins: Level = 1, group = 12, mode = 0, scope = 4
N5.C1.D0.R1.S00: RdPtrOffsetTxDq: 08
N7.C0.D0.R0.S03: TxDqs: plus1 = 1, minus1 = 0, PI = 47, DB = 0
N1.C0.D0.R0.S04: TxDq : plus1 = 1, minus1 = 0, PI = 46, DB = 0
N5.C1.D0.R1.S01: RdPtrOffsetTxDq: 07
N7.C0.D0.R0.S03: TxDq : plus1 = 1, minus1 = 0, PI = 12, DB = 1
N1.C0.D0.R0.S05: TxDqs: plus1 = 1, minus1 = 0, PI = 34, DB = 0
N5.C1.D0.R1.S02: RdPtrOffsetTxDq: 07
N7.C0.D0.R0.S04: TxDqs: plus1 = 1, minus1 = 0, PI = 14, DB = 1
N1.C0.D0.R0.S05: TxDq : plus1 = 1, minus1 = 0, PI = 01, DB = 1
N5.C1.D0.R1.S03: RdPtrOffsetTxDq: 07
N7.C0.D0.R0.S04: TxDq : plus1 = 1, minus1 = 0, PI = 44, DB = 0
N1.C0.D0.R0.S06: TxDqs: plus1 = 1, minus1 = 0, PI = 39, DB = 0
N5.C1.D0.R1.S04: RdPtrOffsetTxDq: 06
N7.C0.D0.R0.S05: TxDqs: plus1 = 1, minus1 = 0, PI = 33, DB = 0
N1.C0.D0.R0.S06: TxDq : plus1 = 1, minus1 = 0, PI = 05, DB = 1
N5.C1.D0.R1.S05: RdPtrOffsetTxDq: 07
N7.C0.D0.R0.S05: TxDq : plus1 = 1, minus1 = 0, PI = 63, DB = 1
N1.C0.D0.R0.S07: TxDqs: plus1 = 1, minus1 = 0, PI = 57, DB = 1
N5.C1.D0.R1.S06: RdPtrOffsetTxDq: 07
N7.C0.D0.R0.S06: TxDqs: plus1 = 1, minus1 = 0, PI = 35, DB = 0
N1.C0.D0.R0.S07: TxDq : plus1 = 1, minus1 = 0, PI = 23, DB = 0
N5.C1.D0.R1.S07: RdPtrOffsetTxDq: 07
N7.C0.D0.R0.S06: TxDq : plus1 = 1, minus1 = 0, PI = 01, DB = 1
N1.C0.D0.R0.S08: TxDqs: plus1 = 1, minus1 = 0, PI = 24, DB = 0
N5.C1.D0.R1.S08: RdPtrOffsetTxDq: 07
N7.C0.D0.R0.S07: TxDqs: plus1 = 1, minus1 = 0, PI = 56, DB = 1
N1.C0.D0.R0.S08: TxDq : plus1 = 1, minus1 = 0, PI = 53, DB = 1
N5.C1.D0.R1.S09: RdPtrOffsetTxDq: 08
N7.C0.D0.R0.S07: TxDq : plus1 = 1, minus1 = 0, PI = 21, DB = 0
N1.C0.D0.R0.S09: TxDqs: plus1 = 1, minus1 = 0, PI = 33, DB = 0
N5.C1.D0.R1.S10: RdPtrOffsetTxDq: 07
N7.C0.D0.R0.S08: TxDqs: plus1 = 1, minus1 = 0, PI = 22, DB = 0
N1.C0.D0.R0.S09: TxDq : plus1 = 1, minus1 = 0, PI = 63, DB = 1
N5.C1.D0.R1.S11: RdPtrOffsetTxDq: 07
N7.C0.D0.R0.S08: TxDq : plus1 = 1, minus1 = 0, PI = 52, DB = 1
N1.C0.D0.R0.S10: TxDqs: plus1 = 1, minus1 = 0, PI = 15, DB = 1
N5.C1.D0.R1.S12: RdPtrOffsetTxDq: 07
N7.C0.D0.R0.S09: TxDqs: plus1 = 1, minus1 = 0, PI = 31, DB = 0
N1.C0.D0.R0.S10: TxDq : plus1 = 1, minus1 = 0, PI = 46, DB = 0
N5.C1.D0.R1.S13: RdPtrOffsetTxDq: 06
N7.C0.D0.R0.S09: TxDq : plus1 = 1, minus1 = 0, PI = 61, DB = 1
N1.C0.D0.R0.S11: TxDqs: plus1 = 1, minus1 = 0, PI = 03, DB = 1
N5.C1.D0.R1.S14: RdPtrOffsetTxDq: 07
N7.C0.D0.R0.S10: TxDqs: plus1 = 1, minus1 = 0, PI = 11, DB = 1
N1.C0.D0.R0.S11: TxDq : plus1 = 1, minus1 = 0, PI = 31, DB = 0
N5.C1.D0.R1.S15: RdPtrOffsetTxDq: 07
N7.C0.D0.R0.S10: TxDq : plus1 = 1, minus1 = 0, PI = 40, DB = 0
N1.C0.D0.R0.S12: TxDqs: plus1 = 1, minus1 = 0, PI = 53, DB = 1
N5.C1.D0.R1.S16: RdPtrOffsetTxDq: 07
N7.C0.D0.R0.S11: TxDqs: plus1 = 1, minus1 = 0, PI = 63, DB = 1
N1.C0.D0.R0.S12: TxDq : plus1 = 1, minus1 = 0, PI = 18, DB = 0
N5.C1.D0.R1.S17: RdPtrOffsetTxDq: 07
N7.C0.D0.R0.S11: TxDq : plus1 = 1, minus1 = 0, PI = 28, DB = 0
N1.C0.D0.R0.S13: TxDqs: plus1 = 1, minus1 = 0, PI = 16, DB = 0
N5.C1.D0.R1.S00: Total Delay in PI ticks: TxDQ = 968
N7.C0.D0.R0.S12: TxDqs: plus1 = 1, minus1 = 0, PI = 47, DB = 0
N1.C0.D0.R0.S13: TxDq : plus1 = 1, minus1 = 0, PI = 47, DB = 0
N5.C1.D0.R1.S01: Total Delay in PI ticks: TxDQ = 950
N7.C0.D0.R0.S12: TxDq : plus1 = 1, minus1 = 0, PI = 12, DB = 1
N1.C0.D0.R0.S14: TxDqs: plus1 = 1, minus1 = 0, PI = 32, DB = 0
N5.C1.D0.R1.S02: Total Delay in PI ticks: TxDQ = 940
N7.C0.D0.R0.S13: TxDqs: plus1 = 1, minus1 = 0, PI = 14, DB = 1
N1.C0.D0.R0.S14: TxDq : plus1 = 1, minus1 = 0, PI = 00, DB = 1
N5.C1.D0.R1.S03: Total Delay in PI ticks: TxDQ = 921
N7.C0.D0.R0.S13: TxDq : plus1 = 1, minus1 = 0, PI = 45, DB = 0
N1.C0.D0.R0.S15: TxDqs: plus1 = 1, minus1 = 0, PI = 39, DB = 0
N5.C1.D0.R1.S04: Total Delay in PI ticks: TxDQ = 890
N7.C0.D0.R0.S14: TxDqs: plus1 = 1, minus1 = 0, PI = 32, DB = 0
N1.C0.D0.R0.S15: TxDq : plus1 = 1, minus1 = 0, PI = 07, DB = 1
N5.C1.D0.R1.S05: Total Delay in PI ticks: TxDQ = 905
N7.C0.D0.R0.S14: TxDq : plus1 = 0, minus1 = 1, PI = 00, DB = 1
N1.C0.D0.R0.S16: TxDqs: plus1 = 1, minus1 = 0, PI = 56, DB = 1
N5.C1.D0.R1.S06: Total Delay in PI ticks: TxDQ = 918
N7.C0.D0.R0.S15: TxDqs: plus1 = 1, minus1 = 0, PI = 36, DB = 0
N1.C0.D0.R0.S16: TxDq : plus1 = 1, minus1 = 0, PI = 22, DB = 0
N5.C1.D0.R1.S07: Total Delay in PI ticks: TxDQ = 937
N7.C0.D0.R0.S15: TxDq : plus1 = 1, minus1 = 0, PI = 03, DB = 1
N1.C0.D0.R0.S17: TxDqs: plus1 = 1, minus1 = 0, PI = 24, DB = 0
N5.C1.D0.R1.S08: Total Delay in PI ticks: TxDQ = 903
N7.C0.D0.R0.S16: TxDqs: plus1 = 1, minus1 = 0, PI = 55, DB = 1
N1.C0.D0.R0.S17: TxDq : plus1 = 1, minus1 = 0, PI = 53, DB = 1
N5.C1.D0.R1.S09: Total Delay in PI ticks: TxDQ = 966
N7.C0.D0.R0.S16: TxDq : plus1 = 1, minus1 = 0, PI = 21, DB = 0
N1.C0.D0.R1.S00: TxDqs: plus1 = 1, minus1 = 0, PI = 33, DB = 0
N5.C1.D0.R1.S10: Total Delay in PI ticks: TxDQ = 951
N7.C0.D0.R0.S17: TxDqs: plus1 = 1, minus1 = 0, PI = 23, DB = 0
N1.C0.D0.R1.S00: TxDq : plus1 = 0, minus1 = 1, PI = 02, DB = 1
N5.C1.D0.R1.S11: Total Delay in PI ticks: TxDQ = 941
N7.C0.D0.R0.S17: TxDq : plus1 = 1, minus1 = 0, PI = 53, DB = 1
N1.C0.D0.R1.S01: TxDqs: plus1 = 1, minus1 = 0, PI = 15, DB = 1
N5.C1.D0.R1.S12: Total Delay in PI ticks: TxDQ = 925
N7.C0.D0.R1.S00: TxDqs: plus1 = 1, minus1 = 0, PI = 32, DB = 0
N1.C0.D0.R1.S01: TxDq : plus1 = 1, minus1 = 0, PI = 46, DB = 0
N5.C1.D0.R1.S13: Total Delay in PI ticks: TxDQ = 893
N7.C0.D0.R1.S00: TxDq : plus1 = 1, minus1 = 0, PI = 62, DB = 1
N1.C0.D0.R1.S02: TxDqs: plus1 = 1, minus1 = 0, PI = 03, DB = 1
N5.C1.D0.R1.S14: Total Delay in PI ticks: TxDQ = 903
N7.C0.D0.R1.S01: TxDqs: plus1 = 1, minus1 = 0, PI = 11, DB = 1
N1.C0.D0.R1.S02: TxDq : plus1 = 1, minus1 = 0, PI = 33, DB = 0
N5.C1.D0.R1.S15: Total Delay in PI ticks: TxDQ = 921
N7.C0.D0.R1.S01: TxDq : plus1 = 1, minus1 = 0, PI = 40, DB = 0
N1.C0.D0.R1.S03: TxDqs: plus1 = 1, minus1 = 0, PI = 50, DB = 1
N5.C1.D0.R1.S16: Total Delay in PI ticks: TxDQ = 936
N7.C0.D0.R1.S02: TxDqs: plus1 = 1, minus1 = 0, PI = 63, DB = 1
N1.C0.D0.R1.S03: TxDq : plus1 = 1, minus1 = 0, PI = 15, DB = 1
N5.C1.D0.R1.S17: Total Delay in PI ticks: TxDQ = 904
N7.C0.D0.R1.S02: TxDq : plus1 = 1, minus1 = 0, PI = 29, DB = 0
N1.C0.D0.R1.S04: TxDqs: plus1 = 1, minus1 = 0, PI = 16, DB = 0
N5.C1: Calculating Optimimum DQ/DQS Values
N7.C0.D0.R1.S03: TxDqs: plus1 = 1, minus1 = 0, PI = 47, DB = 0
N1.C0.D0.R1.S04: TxDq : plus1 = 1, minus1 = 0, PI = 46, DB = 0
N7.C0.D0.R1.S03: TxDq : plus1 = 1, minus1 = 0, PI = 12, DB = 1
N1.C0.D0.R1.S05: TxDqs: plus1 = 1, minus1 = 0, PI = 34, DB = 0
START_DATA_TX_DQ
N7.C0.D0.R1.S04: TxDqs: plus1 = 1, minus1 = 0, PI = 14, DB = 1
N1.C0.D0.R1.S05: TxDq : plus1 = 1, minus1 = 0, PI = 01, DB = 1
N5.C1.S00: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 009, RdPtrOffsetTxDqs = 009
N7.C0.D0.R1.S04: TxDq : plus1 = 1, minus1 = 0, PI = 44, DB = 0
N1.C0.D0.R1.S06: TxDqs: plus1 = 1, minus1 = 0, PI = 39, DB = 0
N5.C1.S00: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 009, RdPtrOffsetTxDqs = 009
N7.C0.D0.R1.S05: TxDqs: plus1 = 1, minus1 = 0, PI = 33, DB = 0
N1.C0.D0.R1.S06: TxDq : plus1 = 1, minus1 = 0, PI = 05, DB = 1
N5.C1.S01: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 009
N7.C0.D0.R1.S05: TxDq : plus1 = 1, minus1 = 0, PI = 63, DB = 1
N1.C0.D0.R1.S07: TxDqs: plus1 = 1, minus1 = 0, PI = 57, DB = 1
N5.C1.S01: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 009
N7.C0.D0.R1.S06: TxDqs: plus1 = 1, minus1 = 0, PI = 35, DB = 0
N1.C0.D0.R1.S07: TxDq : plus1 = 1, minus1 = 0, PI = 23, DB = 0
N5.C1.S02: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 009
N7.C0.D0.R1.S06: TxDq : plus1 = 1, minus1 = 0, PI = 01, DB = 1
N1.C0.D0.R1.S08: TxDqs: plus1 = 1, minus1 = 0, PI = 24, DB = 0
N5.C1.S02: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 009
N7.C0.D0.R1.S07: TxDqs: plus1 = 1, minus1 = 0, PI = 56, DB = 1
N1.C0.D0.R1.S08: TxDq : plus1 = 1, minus1 = 0, PI = 53, DB = 1
N5.C1.S03: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 008
N7.C0.D0.R1.S07: TxDq : plus1 = 1, minus1 = 0, PI = 21, DB = 0
N1.C0.D0.R1.S09: TxDqs: plus1 = 1, minus1 = 0, PI = 33, DB = 0
N5.C1.S03: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 008
N7.C0.D0.R1.S08: TxDqs: plus1 = 1, minus1 = 0, PI = 22, DB = 0
N1.C0.D0.R1.S09: TxDq : plus1 = 1, minus1 = 0, PI = 63, DB = 1
N5.C1.S04: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 007, RdPtrOffsetTxDqs = 008
N7.C0.D0.R1.S08: TxDq : plus1 = 1, minus1 = 0, PI = 52, DB = 1
N1.C0.D0.R1.S10: TxDqs: plus1 = 1, minus1 = 0, PI = 15, DB = 1
N5.C1.S04: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 007, RdPtrOffsetTxDqs = 008
N7.C0.D0.R1.S09: TxDqs: plus1 = 1, minus1 = 0, PI = 31, DB = 0
N1.C0.D0.R1.S10: TxDq : plus1 = 1, minus1 = 0, PI = 46, DB = 0
N5.C1.S05: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 008
N7.C0.D0.R1.S09: TxDq : plus1 = 1, minus1 = 0, PI = 61, DB = 1
N1.C0.D0.R1.S11: TxDqs: plus1 = 1, minus1 = 0, PI = 03, DB = 1
N5.C1.S05: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 008
N7.C0.D0.R1.S10: TxDqs: plus1 = 1, minus1 = 0, PI = 11, DB = 1
N1.C0.D0.R1.S11: TxDq : plus1 = 1, minus1 = 0, PI = 31, DB = 0
N5.C1.S06: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 008
N7.C0.D0.R1.S10: TxDq : plus1 = 1, minus1 = 0, PI = 40, DB = 0
N1.C0.D0.R1.S12: TxDqs: plus1 = 1, minus1 = 0, PI = 53, DB = 1
N5.C1.S06: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 008
N7.C0.D0.R1.S11: TxDqs: plus1 = 1, minus1 = 0, PI = 63, DB = 1
N1.C0.D0.R1.S12: TxDq : plus1 = 1, minus1 = 0, PI = 18, DB = 0
N5.C1.S07: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 009
N7.C0.D0.R1.S11: TxDq : plus1 = 1, minus1 = 0, PI = 28, DB = 0
N1.C0.D0.R1.S13: TxDqs: plus1 = 1, minus1 = 0, PI = 16, DB = 0
N5.C1.S07: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 009
N7.C0.D0.R1.S12: TxDqs: plus1 = 1, minus1 = 0, PI = 47, DB = 0
N1.C0.D0.R1.S13: TxDq : plus1 = 1, minus1 = 0, PI = 47, DB = 0
N5.C1.S08: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 008
N7.C0.D0.R1.S12: TxDq : plus1 = 1, minus1 = 0, PI = 12, DB = 1
N1.C0.D0.R1.S14: TxDqs: plus1 = 1, minus1 = 0, PI = 32, DB = 0
N5.C1.S08: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 008
N7.C0.D0.R1.S13: TxDqs: plus1 = 1, minus1 = 0, PI = 14, DB = 1
N1.C0.D0.R1.S14: TxDq : plus1 = 1, minus1 = 0, PI = 00, DB = 1
N5.C1.D0.R0.S00: TxDqs: plus1 = 1, minus1 = 0, PI = 41, DB = 0
N7.C0.D0.R1.S13: TxDq : plus1 = 1, minus1 = 0, PI = 45, DB = 0
N1.C0.D0.R1.S15: TxDqs: plus1 = 1, minus1 = 0, PI = 39, DB = 0
N5.C1.D0.R0.S00: TxDq : plus1 = 1, minus1 = 0, PI = 08, DB = 1
N7.C0.D0.R1.S14: TxDqs: plus1 = 1, minus1 = 0, PI = 32, DB = 0
N1.C0.D0.R1.S15: TxDq : plus1 = 1, minus1 = 0, PI = 07, DB = 1
N5.C1.D0.R0.S01: TxDqs: plus1 = 1, minus1 = 0, PI = 24, DB = 0
N7.C0.D0.R1.S14: TxDq : plus1 = 0, minus1 = 1, PI = 00, DB = 1
N1.C0.D0.R1.S16: TxDqs: plus1 = 1, minus1 = 0, PI = 56, DB = 1
N5.C1.D0.R0.S01: TxDq : plus1 = 1, minus1 = 0, PI = 54, DB = 1
N7.C0.D0.R1.S15: TxDqs: plus1 = 1, minus1 = 0, PI = 36, DB = 0
N1.C0.D0.R1.S16: TxDq : plus1 = 1, minus1 = 0, PI = 22, DB = 0
N5.C1.D0.R0.S02: TxDqs: plus1 = 1, minus1 = 0, PI = 13, DB = 1
N7.C0.D0.R1.S15: TxDq : plus1 = 1, minus1 = 0, PI = 03, DB = 1
N1.C0.D0.R1.S17: TxDqs: plus1 = 1, minus1 = 0, PI = 24, DB = 0
N5.C1.D0.R0.S02: TxDq : plus1 = 1, minus1 = 0, PI = 44, DB = 0
N7.C0.D0.R1.S16: TxDqs: plus1 = 1, minus1 = 0, PI = 55, DB = 1
N1.C0.D0.R1.S17: TxDq : plus1 = 1, minus1 = 0, PI = 53, DB = 1
N5.C1.D0.R0.S03: TxDqs: plus1 = 1, minus1 = 0, PI = 60, DB = 1
N7.C0.D0.R1.S16: TxDq : plus1 = 1, minus1 = 0, PI = 21, DB = 0
END_DATA_TX_DQ
N5.C1.D0.R0.S03: TxDq : plus1 = 1, minus1 = 0, PI = 26, DB = 0
N7.C0.D0.R1.S17: TxDqs: plus1 = 1, minus1 = 0, PI = 23, DB = 0
N1.C1.D0.R0.S00: wrcmd2dqsstartlatency: 04
N5.C1.D0.R0.S04: TxDqs: plus1 = 1, minus1 = 0, PI = 27, DB = 0
N7.C0.D0.R1.S17: TxDq : plus1 = 1, minus1 = 0, PI = 53, DB = 1
N1.C1.D0.R0.S00: RdPtrOffsetTxDq: 06
N5.C1.D0.R0.S04: TxDq : plus1 = 1, minus1 = 0, PI = 58, DB = 1
END_DATA_TX_DQ
N1.C1.D0.R0.S00: RdPtrOffsetTxDqs: 07
N5.C1.D0.R0.S05: TxDqs: plus1 = 1, minus1 = 0, PI = 43, DB = 0
N7.C1.D0.R0.S00: wrcmd2dqsstartlatency: 04
N1.C1.D0.R0.S00: PiTxDqs: 39
N5.C1.D0.R0.S05: TxDq : plus1 = 1, minus1 = 0, PI = 09, DB = 1
N7.C1.D0.R0.S00: RdPtrOffsetTxDq: 06
N1.C1.D0.R0.S01: wrcmd2dqsstartlatency: 04
N5.C1.D0.R0.S06: TxDqs: plus1 = 1, minus1 = 0, PI = 56, DB = 1
N7.C1.D0.R0.S00: RdPtrOffsetTxDqs: 07
N1.C1.D0.R0.S01: RdPtrOffsetTxDq: 05
N5.C1.D0.R0.S06: TxDq : plus1 = 1, minus1 = 0, PI = 23, DB = 0
N7.C1.D0.R0.S00: PiTxDqs: 44
N1.C1.D0.R0.S01: RdPtrOffsetTxDqs: 07
N5.C1.D0.R0.S07: TxDqs: plus1 = 1, minus1 = 0, PI = 11, DB = 1
N7.C1.D0.R0.S01: wrcmd2dqsstartlatency: 04
N1.C1.D0.R0.S01: PiTxDqs: 23
N5.C1.D0.R0.S07: TxDq : plus1 = 1, minus1 = 0, PI = 41, DB = 0
N7.C1.D0.R0.S01: RdPtrOffsetTxDq: 05
N1.C1.D0.R0.S02: wrcmd2dqsstartlatency: 04
N5.C1.D0.R0.S08: TxDqs: plus1 = 1, minus1 = 0, PI = 40, DB = 0
N7.C1.D0.R0.S01: RdPtrOffsetTxDqs: 07
N1.C1.D0.R0.S02: RdPtrOffsetTxDq: 05
N5.C1.D0.R0.S08: TxDq : plus1 = 1, minus1 = 0, PI = 07, DB = 1
N7.C1.D0.R0.S01: PiTxDqs: 27
N1.C1.D0.R0.S02: RdPtrOffsetTxDqs: 07
N5.C1.D0.R0.S09: TxDqs: plus1 = 1, minus1 = 0, PI = 40, DB = 0
N7.C1.D0.R0.S02: wrcmd2dqsstartlatency: 04
N1.C1.D0.R0.S02: PiTxDqs: 12
N5.C1.D0.R0.S09: TxDq : plus1 = 1, minus1 = 0, PI = 07, DB = 1
N7.C1.D0.R0.S02: RdPtrOffsetTxDq: 05
N1.C1.D0.R0.S03: wrcmd2dqsstartlatency: 04
N5.C1.D0.R0.S10: TxDqs: plus1 = 1, minus1 = 0, PI = 25, DB = 0
N7.C1.D0.R0.S02: RdPtrOffsetTxDqs: 07
N1.C1.D0.R0.S03: RdPtrOffsetTxDq: 05
N5.C1.D0.R0.S10: TxDq : plus1 = 1, minus1 = 0, PI = 54, DB = 1
N7.C1.D0.R0.S02: PiTxDqs: 19
N1.C1.D0.R0.S03: RdPtrOffsetTxDqs: 06
N5.C1.D0.R0.S11: TxDqs: plus1 = 1, minus1 = 0, PI = 13, DB = 1
N7.C1.D0.R0.S03: wrcmd2dqsstartlatency: 04
N1.C1.D0.R0.S03: PiTxDqs: 60
N5.C1.D0.R0.S11: TxDq : plus1 = 1, minus1 = 0, PI = 45, DB = 0
N7.C1.D0.R0.S03: RdPtrOffsetTxDq: 05
N1.C1.D0.R0.S04: wrcmd2dqsstartlatency: 04
N5.C1.D0.R0.S12: TxDqs: plus1 = 1, minus1 = 0, PI = 61, DB = 1
N7.C1.D0.R0.S03: RdPtrOffsetTxDqs: 07
N1.C1.D0.R0.S04: RdPtrOffsetTxDq: 04
N5.C1.D0.R0.S12: TxDq : plus1 = 1, minus1 = 0, PI = 28, DB = 0
N7.C1.D0.R0.S03: PiTxDqs: 01
N1.C1.D0.R0.S04: RdPtrOffsetTxDqs: 06
N5.C1.D0.R0.S13: TxDqs: plus1 = 1, minus1 = 0, PI = 30, DB = 0
N7.C1.D0.R0.S04: wrcmd2dqsstartlatency: 04
N1.C1.D0.R0.S04: PiTxDqs: 27
N5.C1.D0.R0.S13: TxDq : plus1 = 1, minus1 = 0, PI = 61, DB = 1
N7.C1.D0.R0.S04: RdPtrOffsetTxDq: 04
N1.C1.D0.R0.S05: wrcmd2dqsstartlatency: 04
N5.C1.D0.R0.S14: TxDqs: plus1 = 1, minus1 = 0, PI = 42, DB = 0
N7.C1.D0.R0.S04: RdPtrOffsetTxDqs: 06
N1.C1.D0.R0.S05: RdPtrOffsetTxDq: 05
N5.C1.D0.R0.S14: TxDq : plus1 = 1, minus1 = 0, PI = 08, DB = 1
N7.C1.D0.R0.S04: PiTxDqs: 32
N1.C1.D0.R0.S05: RdPtrOffsetTxDqs: 06
START_DATA_TX_DQ_ADV
Results for N3.C0.D0.R0: 
           0   1   2   3   4   5   6   7   8   9  10  11  12  13  14  15  16  17
-------------------------------------------------------------------------------
Vref offset: 0
Left:    -27 -27 -27 -28 -27 -27 -26 -27 -28 -27 -28 -26 -28 -28 -29 -26 -26 -26
Right:    22  23  23  25  21  21  23  21  21  22  23  24  25  22  21  24  22  22
-------------------------------------------------------------------------------
Prev Pi: 451 433 419 404 372 388 392 411 378 450 433 421 405 371 388 391 411 378
New Pi:  449 431 417 403 369 385 391 408 375 448 431 420 404 368 384 390 409 376
Diff:     -2  -2  -2  -1  -3  -3  -1  -3  -3  -2  -2  -1  -1  -3  -4  -1  -2  -2

Results for N3.C0.D0.R1: 
           0   1   2   3   4   5   6   7   8   9  10  11  12  13  14  15  16  17
-------------------------------------------------------------------------------
Vref offset: 0
Left:    -28 -26 -27 -26 -27 -27 -27 -27 -27 -27 -27 -27 -28 -27 -27 -25 -27 -26
Right:    22  23  22  25  21  20  22  22  21  23  23  23  23  22  22  24  23  22
-------------------------------------------------------------------------------
Prev Pi: 451 433 419 404 372 388 392 411 378 450 433 421 405 371 388 391 411 378
New Pi:  448 432 417 404 369 385 390 409 375 448 431 419 403 369 386 391 409 376
Diff:     -3  -1  -2   0  -3  -3  -2  -2  -3  -2  -2  -2  -2  -2  -2   0  -2  -2

Results for N3.C1.D0.R0: 
           0   1   2   3   4   5   6   7   8   9  10  11  12  13  14  15  16  17
-------------------------------------------------------------------------------
Vref offset: 0
Left:    -27 -28 -27 -27 -28 -25 -25 -26 -25 -26 -27 -26 -26 -27 -27 -27 -26 -27
Right:    21  22  20  24  20  23  23  21  24  20  23  22  25  22  22  22  23  23
-------------------------------------------------------------------------------
Prev Pi: 452 435 426 408 376 389 402 421 387 450 436 428 407 375 388 403 419 389
New Pi:  449 432 423 407 372 388 401 419 387 447 434 426 407 373 386 401 418 387
Diff:     -3  -3  -3  -1  -4  -1  -1  -2   0  -3  -2  -2   0  -2  -2  -2  -1  -2

Results for N3.C1.D0.R1: 
           0   1   2   3   4   5   6   7   8   9  10  11  12  13  14  15  16  17
-------------------------------------------------------------------------------
Vref offset: 0
Left:    -28 -29 -26 -27 -28 -26 -25 -26 -26 -27 -27 -27 -26 -27 -27 -27 -25 -28
Right:    21  22  21  24  21  22  24  23  24  19  22  22  25  22  22  22  23  23
-------------------------------------------------------------------------------
Prev Pi: 452 435 426 408 376 389 402 421 387 450 436 428 407 375 388 403 419 389
New Pi:  449 432 424 407 373 387 402 420 386 446 434 426 407 373 386 401 418 387
Diff:     -3  -3  -2  -1  -3  -2   0  -1  -1  -4  -2  -2   0  -2  -2  -2  -1  -2

Results for N3.C2.D0.R0: 
           0   1   2   3   4   5   6   7   8   9  10  11  12  13  14  15  16  17
-------------------------------------------------------------------------------
Vref offset: 0
Left:    -27 -27 -26 -24 -28 -28 -27 -26 -25 -27 -27 -27 -24 -26 -27 -27 -28 -25
Right:    22  24  22  25  22  19  22  23  21  22  23  23  25  24  21  21  23  23
-------------------------------------------------------------------------------
Prev Pi: 444 425 417 397 361 388 388 408 372 441 426 418 397 360 387 389 410 373
New Pi:  442 424 415 397 358 384 386 407 370 439 424 416 397 359 384 386 408 372
Diff:     -2  -1  -2   0  -3  -4  -2  -1  -2  -2  -2  -2   0  -1  -3  -3  -2  -1

Results for N3.C2.D0.R1: 
           0   1   2   3   4   5   6   7   8   9  10  11  12  13  14  15  16  17
-------------------------------------------------------------------------------
Vref offset: 0
Left:    -28 -27 -26 -25 -27 -27 -26 -26 -26 -26 -28 -27 -25 -27 -28 -27 -27 -25
Right:    23  24  23  25  21  21  21  24  22  23  23  23  25  24  21  22  24  23
-------------------------------------------------------------------------------
Prev Pi: 444 425 417 397 361 388 388 408 372 441 426 418 397 360 387 389 410 373
New Pi:  442 424 416 397 358 385 386 407 370 440 424 416 397 359 384 387 409 372
Diff:     -2  -1  -1   0  -3  -3  -2  -1  -2  -1  -2  -2   0  -1  -3  -2  -1  -1

Results for N3.C3.D0.R0: 
           0   1   2   3   4   5   6   7   8   9  10  11  12  13  14  15  16  17
-------------------------------------------------------------------------------
Vref offset: 0
Left:    -28 -27 -25 -27 -28 -26 -26 -23 -27 -27 -27 -25 -25 -27 -25 -26 -26 -26
Right:    21  22  21  22  20  22  22  22  21  18  21  23  21  21  21  21  22  23
-------------------------------------------------------------------------------
Prev Pi: 454 434 424 407 372 388 402 419 388 451 436 425 408 373 387 402 421 389
New Pi:  451 432 422 405 368 386 400 419 385 447 433 424 406 370 385 400 419 388
Diff:     -3  -2  -2  -2  -4  -2  -2   0  -3  -4  -3  -1  -2  -3  -2  -2  -2  -1

Results for N3.C3.D0.R1: 
           0   1   2   3   4   5   6   7   8   9  10  11  12  13  14  15  16  17
-------------------------------------------------------------------------------
Vref offset: 0
Left:    -28 -27 -26 -24 -27 -26 -26 -25 -27 -27 -27 -27 -25 -28 -26 -26 -26 -27
Right:    20  22  22  23  21  21  22  22  21  19  21  21  21  20  22  22  23  21
-------------------------------------------------------------------------------
Prev Pi: 454 434 424 407 372 388 402 419 388 451 436 425 408 373 387 402 421 389
New Pi:  450 432 422 407 369 386 400 418 385 447 433 422 406 369 385 400 420 386
Diff:     -4  -2  -2   0  -3  -2  -2  -1  -3  -4  -3  -3  -2  -4  -2  -2  -1  -3

STOP_DATA_TX_DQ_ADV
N5.C1.D0.R0.S15: TxDqs: plus1 = 1, minus1 = 0, PI = 57, DB = 1
N7.C1.D0.R0.S05: wrcmd2dqsstartlatency: 04
N1.C1.D0.R0.S05: PiTxDqs: 40
N3: RunTrainStep: Final status = 0
N5.C1.D0.R0.S15: TxDq : plus1 = 1, minus1 = 0, PI = 23, DB = 0
N7.C1.D0.R0.S05: RdPtrOffsetTxDq: 05
N1.C1.D0.R0.S06: wrcmd2dqsstartlatency: 04

END - Wr Timing Centering 2D Training  Time         3107 ms
N5.C1.D0.R0.S16: TxDqs: plus1 = 1, minus1 = 0, PI = 10, DB = 1
N7.C1.D0.R0.S05: RdPtrOffsetTxDqs: 06
N1.C1.D0.R0.S06: RdPtrOffsetTxDq: 05

START - Rd Voltage Training
N5.C1.D0.R0.S16: TxDq : plus1 = 1, minus1 = 0, PI = 40, DB = 0
N7.C1.D0.R0.S05: PiTxDqs: 46
N1.C1.D0.R0.S06: RdPtrOffsetTxDqs: 06
N3: RX Vref Training...
N5.C1.D0.R0.S17: TxDqs: plus1 = 1, minus1 = 0, PI = 41, DB = 0
N7.C1.D0.R0.S06: wrcmd2dqsstartlatency: 04
N1.C1.D0.R0.S06: PiTxDqs: 53
N3: GetMargins: Level = 1, group = 13, mode = 2, scope = 4
N5.C1.D0.R0.S17: TxDq : plus1 = 1, minus1 = 0, PI = 08, DB = 1
N7.C1.D0.R0.S06: RdPtrOffsetTxDq: 05
N1.C1.D0.R0.S07: wrcmd2dqsstartlatency: 04
N5.C1.D0.R1.S00: TxDqs: plus1 = 1, minus1 = 0, PI = 41, DB = 0
N7.C1.D0.R0.S06: RdPtrOffsetTxDqs: 06
N1.C1.D0.R0.S07: RdPtrOffsetTxDq: 05
N5.C1.D0.R1.S00: TxDq : plus1 = 1, minus1 = 0, PI = 08, DB = 1
N7.C1.D0.R0.S06: PiTxDqs: 59
N1.C1.D0.R0.S07: RdPtrOffsetTxDqs: 07
N5.C1.D0.R1.S01: TxDqs: plus1 = 1, minus1 = 0, PI = 24, DB = 0
N7.C1.D0.R0.S07: wrcmd2dqsstartlatency: 04
N1.C1.D0.R0.S07: PiTxDqs: 05
N5.C1.D0.R1.S01: TxDq : plus1 = 1, minus1 = 0, PI = 54, DB = 1
N7.C1.D0.R0.S07: RdPtrOffsetTxDq: 05
N1.C1.D0.R0.S08: wrcmd2dqsstartlatency: 04
N5.C1.D0.R1.S02: TxDqs: plus1 = 1, minus1 = 0, PI = 13, DB = 1
N7.C1.D0.R0.S07: RdPtrOffsetTxDqs: 07
N1.C1.D0.R0.S08: RdPtrOffsetTxDq: 05
N5.C1.D0.R1.S02: TxDq : plus1 = 1, minus1 = 0, PI = 44, DB = 0
N7.C1.D0.R0.S07: PiTxDqs: 15
N1.C1.D0.R0.S08: RdPtrOffsetTxDqs: 06
N5.C1.D0.R1.S03: TxDqs: plus1 = 1, minus1 = 0, PI = 60, DB = 1
N7.C1.D0.R0.S08: wrcmd2dqsstartlatency: 04
N1.C1.D0.R0.S08: PiTxDqs: 38
N5.C1.D0.R1.S03: TxDq : plus1 = 1, minus1 = 0, PI = 26, DB = 0
N7.C1.D0.R0.S08: RdPtrOffsetTxDq: 05
N1.C1.D0.R0.S09: wrcmd2dqsstartlatency: 04
N5.C1.D0.R1.S04: TxDqs: plus1 = 1, minus1 = 0, PI = 27, DB = 0
N7.C1.D0.R0.S08: RdPtrOffsetTxDqs: 06
N1.C1.D0.R0.S09: RdPtrOffsetTxDq: 06
N5.C1.D0.R1.S04: TxDq : plus1 = 1, minus1 = 0, PI = 58, DB = 1
N7.C1.D0.R0.S08: PiTxDqs: 45
N1.C1.D0.R0.S09: RdPtrOffsetTxDqs: 07
N5.C1.D0.R1.S05: TxDqs: plus1 = 1, minus1 = 0, PI = 43, DB = 0
N7.C1.D0.R0.S09: wrcmd2dqsstartlatency: 04
N1.C1.D0.R0.S09: PiTxDqs: 41
N5.C1.D0.R1.S05: TxDq : plus1 = 1, minus1 = 0, PI = 09, DB = 1
N7.C1.D0.R0.S09: RdPtrOffsetTxDq: 06
N1.C1.D0.R0.S10: wrcmd2dqsstartlatency: 04
N5.C1.D0.R1.S06: TxDqs: plus1 = 1, minus1 = 0, PI = 56, DB = 1
N7.C1.D0.R0.S09: RdPtrOffsetTxDqs: 07
N1.C1.D0.R0.S10: RdPtrOffsetTxDq: 05
N5.C1.D0.R1.S06: TxDq : plus1 = 1, minus1 = 0, PI = 23, DB = 0
N7.C1.D0.R0.S09: PiTxDqs: 42
N1.C1.D0.R0.S10: RdPtrOffsetTxDqs: 07
N5.C1.D0.R1.S07: TxDqs: plus1 = 1, minus1 = 0, PI = 11, DB = 1
N7.C1.D0.R0.S10: wrcmd2dqsstartlatency: 04
N1.C1.D0.R0.S10: PiTxDqs: 23
N5.C1.D0.R1.S07: TxDq : plus1 = 1, minus1 = 0, PI = 41, DB = 0
N7.C1.D0.R0.S10: RdPtrOffsetTxDq: 05
N1.C1.D0.R0.S11: wrcmd2dqsstartlatency: 04
N5.C1.D0.R1.S08: TxDqs: plus1 = 1, minus1 = 0, PI = 40, DB = 0
N7.C1.D0.R0.S10: RdPtrOffsetTxDqs: 07
N1.C1.D0.R0.S11: RdPtrOffsetTxDq: 05
N5.C1.D0.R1.S08: TxDq : plus1 = 1, minus1 = 0, PI = 07, DB = 1
N7.C1.D0.R0.S10: PiTxDqs: 29
N1.C1.D0.R0.S11: RdPtrOffsetTxDqs: 07
N5.C1.D0.R1.S09: TxDqs: plus1 = 1, minus1 = 0, PI = 40, DB = 0
N7.C1.D0.R0.S11: wrcmd2dqsstartlatency: 04
N1.C1.D0.R0.S11: PiTxDqs: 12
N5.C1.D0.R1.S09: TxDq : plus1 = 1, minus1 = 0, PI = 07, DB = 1
N7.C1.D0.R0.S11: RdPtrOffsetTxDq: 05
N1.C1.D0.R0.S12: wrcmd2dqsstartlatency: 04
N5.C1.D0.R1.S10: TxDqs: plus1 = 1, minus1 = 0, PI = 25, DB = 0
N7.C1.D0.R0.S11: RdPtrOffsetTxDqs: 07
N1.C1.D0.R0.S12: RdPtrOffsetTxDq: 05
N5.C1.D0.R1.S10: TxDq : plus1 = 1, minus1 = 0, PI = 54, DB = 1
N7.C1.D0.R0.S11: PiTxDqs: 18
N1.C1.D0.R0.S12: RdPtrOffsetTxDqs: 06
N5.C1.D0.R1.S11: TxDqs: plus1 = 1, minus1 = 0, PI = 13, DB = 1
N7.C1.D0.R0.S12: wrcmd2dqsstartlatency: 04
N1.C1.D0.R0.S12: PiTxDqs: 61
N5.C1.D0.R1.S11: TxDq : plus1 = 1, minus1 = 0, PI = 45, DB = 0
N7.C1.D0.R0.S12: RdPtrOffsetTxDq: 05
N1.C1.D0.R0.S13: wrcmd2dqsstartlatency: 04
N5.C1.D0.R1.S12: TxDqs: plus1 = 1, minus1 = 0, PI = 61, DB = 1
N7.C1.D0.R0.S12: RdPtrOffsetTxDqs: 07
N1.C1.D0.R0.S13: RdPtrOffsetTxDq: 04
N5.C1.D0.R1.S12: TxDq : plus1 = 1, minus1 = 0, PI = 28, DB = 0
N7.C1.D0.R0.S12: PiTxDqs: 00
N1.C1.D0.R0.S13: RdPtrOffsetTxDqs: 06
N5.C1.D0.R1.S13: TxDqs: plus1 = 1, minus1 = 0, PI = 30, DB = 0
N7.C1.D0.R0.S13: wrcmd2dqsstartlatency: 04
N1.C1.D0.R0.S13: PiTxDqs: 27
N5.C1.D0.R1.S13: TxDq : plus1 = 1, minus1 = 0, PI = 61, DB = 1
N7.C1.D0.R0.S13: RdPtrOffsetTxDq: 04
N1.C1.D0.R0.S14: wrcmd2dqsstartlatency: 04
N5.C1.D0.R1.S14: TxDqs: plus1 = 1, minus1 = 0, PI = 42, DB = 0
N7.C1.D0.R0.S13: RdPtrOffsetTxDqs: 06
N1.C1.D0.R0.S14: RdPtrOffsetTxDq: 05
N5.C1.D0.R1.S14: TxDq : plus1 = 1, minus1 = 0, PI = 08, DB = 1
N7.C1.D0.R0.S13: PiTxDqs: 31
N1.C1.D0.R0.S14: RdPtrOffsetTxDqs: 06
N5.C1.D0.R1.S15: TxDqs: plus1 = 1, minus1 = 0, PI = 57, DB = 1
N7.C1.D0.R0.S14: wrcmd2dqsstartlatency: 04
N1.C1.D0.R0.S14: PiTxDqs: 40
N5.C1.D0.R1.S15: TxDq : plus1 = 1, minus1 = 0, PI = 23, DB = 0
N7.C1.D0.R0.S14: RdPtrOffsetTxDq: 05
N1.C1.D0.R0.S15: wrcmd2dqsstartlatency: 04
N5.C1.D0.R1.S16: TxDqs: plus1 = 1, minus1 = 0, PI = 10, DB = 1
N7.C1.D0.R0.S14: RdPtrOffsetTxDqs: 06
N1.C1.D0.R0.S15: RdPtrOffsetTxDq: 05
N5.C1.D0.R1.S16: TxDq : plus1 = 1, minus1 = 0, PI = 40, DB = 0
N7.C1.D0.R0.S14: PiTxDqs: 46
N1.C1.D0.R0.S15: RdPtrOffsetTxDqs: 06
N5.C1.D0.R1.S17: TxDqs: plus1 = 1, minus1 = 0, PI = 41, DB = 0
N7.C1.D0.R0.S15: wrcmd2dqsstartlatency: 04
N1.C1.D0.R0.S15: PiTxDqs: 53
N5.C1.D0.R1.S17: TxDq : plus1 = 1, minus1 = 0, PI = 08, DB = 1
N7.C1.D0.R0.S15: RdPtrOffsetTxDq: 05
N1.C1.D0.R0.S16: wrcmd2dqsstartlatency: 04
END_DATA_TX_DQ
N7.C1.D0.R0.S15: RdPtrOffsetTxDqs: 06
N1.C1.D0.R0.S16: RdPtrOffsetTxDq: 05
N5.C2.D0.R0.S00: wrcmd2dqsstartlatency: 04
N7.C1.D0.R0.S15: PiTxDqs: 58
N1.C1.D0.R0.S16: RdPtrOffsetTxDqs: 07
N5.C2.D0.R0.S00: RdPtrOffsetTxDq: 06
N7.C1.D0.R0.S16: wrcmd2dqsstartlatency: 04
N1.C1.D0.R0.S16: PiTxDqs: 07
N5.C2.D0.R0.S00: RdPtrOffsetTxDqs: 07
N7.C1.D0.R0.S16: RdPtrOffsetTxDq: 05
N1.C1.D0.R0.S17: wrcmd2dqsstartlatency: 04
N5.C2.D0.R0.S00: PiTxDqs: 37
N7.C1.D0.R0.S16: RdPtrOffsetTxDqs: 07
N1.C1.D0.R0.S17: RdPtrOffsetTxDq: 05
N5.C2.D0.R0.S01: wrcmd2dqsstartlatency: 04
N7.C1.D0.R0.S16: PiTxDqs: 13
N1.C1.D0.R0.S17: RdPtrOffsetTxDqs: 06
N5.C2.D0.R0.S01: RdPtrOffsetTxDq: 05
N7.C1.D0.R0.S17: wrcmd2dqsstartlatency: 04
N1.C1.D0.R0.S17: PiTxDqs: 39
N5.C2.D0.R0.S01: RdPtrOffsetTxDqs: 07
N7.C1.D0.R0.S17: RdPtrOffsetTxDq: 05
N1.C1.D0.R0.S00: RdPtrOffsetTxDq: 07
N5.C2.D0.R0.S01: PiTxDqs: 24
N7.C1.D0.R0.S17: RdPtrOffsetTxDqs: 06
N1.C1.D0.R0.S01: RdPtrOffsetTxDq: 06
N5.C2.D0.R0.S02: wrcmd2dqsstartlatency: 04
N7.C1.D0.R0.S17: PiTxDqs: 43
N1.C1.D0.R0.S02: RdPtrOffsetTxDq: 06
N5.C2.D0.R0.S02: RdPtrOffsetTxDq: 05
N7.C1.D0.R0.S00: RdPtrOffsetTxDq: 07
N1.C1.D0.R0.S03: RdPtrOffsetTxDq: 06
N5.C2.D0.R0.S02: RdPtrOffsetTxDqs: 07
N7.C1.D0.R0.S01: RdPtrOffsetTxDq: 06
N1.C1.D0.R0.S04: RdPtrOffsetTxDq: 05
N5.C2.D0.R0.S02: PiTxDqs: 12
N7.C1.D0.R0.S02: RdPtrOffsetTxDq: 06
N1.C1.D0.R0.S05: RdPtrOffsetTxDq: 06
N5.C2.D0.R0.S03: wrcmd2dqsstartlatency: 04
N7.C1.D0.R0.S03: RdPtrOffsetTxDq: 06
N1.C1.D0.R0.S06: RdPtrOffsetTxDq: 06
N5.C2.D0.R0.S03: RdPtrOffsetTxDq: 05
N7.C1.D0.R0.S04: RdPtrOffsetTxDq: 05
N1.C1.D0.R0.S07: RdPtrOffsetTxDq: 06
N5.C2.D0.R0.S03: RdPtrOffsetTxDqs: 06
N7.C1.D0.R0.S05: RdPtrOffsetTxDq: 06
N1.C1.D0.R0.S08: RdPtrOffsetTxDq: 06
N5.C2.D0.R0.S03: PiTxDqs: 59
N7.C1.D0.R0.S06: RdPtrOffsetTxDq: 06
N1.C1.D0.R0.S09: RdPtrOffsetTxDq: 07
N5.C2.D0.R0.S04: wrcmd2dqsstartlatency: 04
N7.C1.D0.R0.S07: RdPtrOffsetTxDq: 06
N1.C1.D0.R0.S10: RdPtrOffsetTxDq: 06
N5.C2.D0.R0.S04: RdPtrOffsetTxDq: 04
N7.C1.D0.R0.S08: RdPtrOffsetTxDq: 06
N1.C1.D0.R0.S11: RdPtrOffsetTxDq: 06
N5.C2.D0.R0.S04: RdPtrOffsetTxDqs: 06
N7.C1.D0.R0.S09: RdPtrOffsetTxDq: 07
N1.C1.D0.R0.S12: RdPtrOffsetTxDq: 06
N5.C2.D0.R0.S04: PiTxDqs: 16
N7.C1.D0.R0.S10: RdPtrOffsetTxDq: 06
N1.C1.D0.R0.S13: RdPtrOffsetTxDq: 05
N5.C2.D0.R0.S05: wrcmd2dqsstartlatency: 04
N7.C1.D0.R0.S11: RdPtrOffsetTxDq: 06
N1.C1.D0.R0.S14: RdPtrOffsetTxDq: 06
N5.C2.D0.R0.S05: RdPtrOffsetTxDq: 05
N7.C1.D0.R0.S12: RdPtrOffsetTxDq: 06
N1.C1.D0.R0.S15: RdPtrOffsetTxDq: 06
N5.C2.D0.R0.S05: RdPtrOffsetTxDqs: 06
N7.C1.D0.R0.S13: RdPtrOffsetTxDq: 05
N1.C1.D0.R0.S16: RdPtrOffsetTxDq: 06
N5.C2.D0.R0.S05: PiTxDqs: 47
N7.C1.D0.R0.S14: RdPtrOffsetTxDq: 06
N1.C1.D0.R0.S17: RdPtrOffsetTxDq: 06
N5.C2.D0.R0.S06: wrcmd2dqsstartlatency: 04
N7.C1.D0.R0.S15: RdPtrOffsetTxDq: 06
N1.C1.D0.R0.S00: RdPtrOffsetTxDq: 08
N5.C2.D0.R0.S06: RdPtrOffsetTxDq: 05
N7.C1.D0.R0.S16: RdPtrOffsetTxDq: 06
N1.C1.D0.R0.S01: RdPtrOffsetTxDq: 07
N5.C2.D0.R0.S06: RdPtrOffsetTxDqs: 06
N7.C1.D0.R0.S17: RdPtrOffsetTxDq: 06
N1.C1.D0.R0.S02: RdPtrOffsetTxDq: 07
N5.C2.D0.R0.S06: PiTxDqs: 47
N7.C1.D0.R0.S00: RdPtrOffsetTxDq: 08
N1.C1.D0.R0.S03: RdPtrOffsetTxDq: 07
N5.C2.D0.R0.S07: wrcmd2dqsstartlatency: 04
N7.C1.D0.R0.S01: RdPtrOffsetTxDq: 07
N1.C1.D0.R0.S04: RdPtrOffsetTxDq: 06
N5.C2.D0.R0.S07: RdPtrOffsetTxDq: 05
N7.C1.D0.R0.S02: RdPtrOffsetTxDq: 07
N1.C1.D0.R0.S05: RdPtrOffsetTxDq: 07
N5.C2.D0.R0.S07: RdPtrOffsetTxDqs: 07
N7.C1.D0.R0.S03: RdPtrOffsetTxDq: 07
N1.C1.D0.R0.S06: RdPtrOffsetTxDq: 07
N5.C2.D0.R0.S07: PiTxDqs: 06
N7.C1.D0.R0.S04: RdPtrOffsetTxDq: 06
N1.C1.D0.R0.S07: RdPtrOffsetTxDq: 07
N5.C2.D0.R0.S08: wrcmd2dqsstartlatency: 04
N7.C1.D0.R0.S05: RdPtrOffsetTxDq: 07
N1.C1.D0.R0.S08: RdPtrOffsetTxDq: 07
N5.C2.D0.R0.S08: RdPtrOffsetTxDq: 04
N7.C1.D0.R0.S06: RdPtrOffsetTxDq: 07
N1.C1.D0.R0.S09: RdPtrOffsetTxDq: 08
N5.C2.D0.R0.S08: RdPtrOffsetTxDqs: 06
N7.C1.D0.R0.S07: RdPtrOffsetTxDq: 07
N1.C1.D0.R0.S10: RdPtrOffsetTxDq: 07
N5.C2.D0.R0.S08: PiTxDqs: 33
N7.C1.D0.R0.S08: RdPtrOffsetTxDq: 07
N1.C1.D0.R0.S11: RdPtrOffsetTxDq: 07
N5.C2.D0.R0.S09: wrcmd2dqsstartlatency: 04
N7.C1.D0.R0.S09: RdPtrOffsetTxDq: 08
N1.C1.D0.R0.S12: RdPtrOffsetTxDq: 07
N5.C2.D0.R0.S09: RdPtrOffsetTxDq: 06
N7.C1.D0.R0.S10: RdPtrOffsetTxDq: 07
N1.C1.D0.R0.S13: RdPtrOffsetTxDq: 06
N5.C2.D0.R0.S09: RdPtrOffsetTxDqs: 07
N7.C1.D0.R0.S11: RdPtrOffsetTxDq: 07
N1.C1.D0.R0.S14: RdPtrOffsetTxDq: 07
N5.C2.D0.R0.S09: PiTxDqs: 35
N7.C1.D0.R0.S12: RdPtrOffsetTxDq: 07
N1.C1.D0.R0.S15: RdPtrOffsetTxDq: 07
N5.C2.D0.R0.S10: wrcmd2dqsstartlatency: 04
N7.C1.D0.R0.S13: RdPtrOffsetTxDq: 06
N1.C1.D0.R0.S16: RdPtrOffsetTxDq: 07
N5.C2.D0.R0.S10: RdPtrOffsetTxDq: 05
N7.C1.D0.R0.S14: RdPtrOffsetTxDq: 07
N1.C1.D0.R0.S17: RdPtrOffsetTxDq: 07
N5.C2.D0.R0.S10: RdPtrOffsetTxDqs: 07
N7.C1.D0.R0.S15: RdPtrOffsetTxDq: 07
N1.C1.D0.R0.S00: Total Delay in PI ticks: TxDQ = 965
N5.C2.D0.R0.S10: PiTxDqs: 24
N7.C1.D0.R0.S16: RdPtrOffsetTxDq: 07
N1.C1.D0.R0.S01: Total Delay in PI ticks: TxDQ = 949
N5.C2.D0.R0.S11: wrcmd2dqsstartlatency: 04
N7.C1.D0.R0.S17: RdPtrOffsetTxDq: 07
N1.C1.D0.R0.S02: Total Delay in PI ticks: TxDQ = 940
N5.C2.D0.R0.S11: RdPtrOffsetTxDq: 05
N7.C1.D0.R0.S00: Total Delay in PI ticks: TxDQ = 971
N1.C1.D0.R0.S03: Total Delay in PI ticks: TxDQ = 924
N5.C2.D0.R0.S11: RdPtrOffsetTxDqs: 07
N7.C1.D0.R0.S01: Total Delay in PI ticks: TxDQ = 954
N1.C1.D0.R0.S04: Total Delay in PI ticks: TxDQ = 889
N5.C2.D0.R0.S11: PiTxDqs: 13
N7.C1.D0.R0.S02: Total Delay in PI ticks: TxDQ = 947
N1.C1.D0.R0.S05: Total Delay in PI ticks: TxDQ = 901
N5.C2.D0.R0.S12: wrcmd2dqsstartlatency: 04
N7.C1.D0.R0.S03: Total Delay in PI ticks: TxDQ = 928
N1.C1.D0.R0.S06: Total Delay in PI ticks: TxDQ = 917
N5.C2.D0.R0.S12: RdPtrOffsetTxDq: 05
N7.C1.D0.R0.S04: Total Delay in PI ticks: TxDQ = 894
N1.C1.D0.R0.S07: Total Delay in PI ticks: TxDQ = 934
N5.C2.D0.R0.S12: RdPtrOffsetTxDqs: 06
N7.C1.D0.R0.S05: Total Delay in PI ticks: TxDQ = 910
N1.C1.D0.R0.S08: Total Delay in PI ticks: TxDQ = 902
N5.C2.D0.R0.S12: PiTxDqs: 59
N7.C1.D0.R0.S06: Total Delay in PI ticks: TxDQ = 923
N1.C1.D0.R0.S09: Total Delay in PI ticks: TxDQ = 967
N5.C2.D0.R0.S13: wrcmd2dqsstartlatency: 04
N7.C1.D0.R0.S07: Total Delay in PI ticks: TxDQ = 940
N1.C1.D0.R0.S10: Total Delay in PI ticks: TxDQ = 948
N5.C2.D0.R0.S13: RdPtrOffsetTxDq: 04
N7.C1.D0.R0.S08: Total Delay in PI ticks: TxDQ = 907
N1.C1.D0.R0.S11: Total Delay in PI ticks: TxDQ = 940
N5.C2.D0.R0.S13: RdPtrOffsetTxDqs: 06
N7.C1.D0.R0.S09: Total Delay in PI ticks: TxDQ = 971
N1.C1.D0.R0.S12: Total Delay in PI ticks: TxDQ = 925
N5.C2.D0.R0.S13: PiTxDqs: 16
N7.C1.D0.R0.S10: Total Delay in PI ticks: TxDQ = 954
N1.C1.D0.R0.S13: Total Delay in PI ticks: TxDQ = 889
N5.C2.D0.R0.S14: wrcmd2dqsstartlatency: 04
N7.C1.D0.R0.S11: Total Delay in PI ticks: TxDQ = 946
N1.C1.D0.R0.S14: Total Delay in PI ticks: TxDQ = 901
N5.C2.D0.R0.S14: RdPtrOffsetTxDq: 05
N7.C1.D0.R0.S12: Total Delay in PI ticks: TxDQ = 928
N1.C1.D0.R0.S15: Total Delay in PI ticks: TxDQ = 918
N5.C2.D0.R0.S14: RdPtrOffsetTxDqs: 06
N7.C1.D0.R0.S13: Total Delay in PI ticks: TxDQ = 895
N1.C1.D0.R0.S16: Total Delay in PI ticks: TxDQ = 933
N5.C2.D0.R0.S14: PiTxDqs: 47
N7.C1.D0.R0.S14: Total Delay in PI ticks: TxDQ = 907
N1.C1.D0.R0.S17: Total Delay in PI ticks: TxDQ = 901
N5.C2.D0.R0.S15: wrcmd2dqsstartlatency: 04
N7.C1.D0.R0.S15: Total Delay in PI ticks: TxDQ = 922
N1.C1.D0.R1.S00: wrcmd2dqsstartlatency: 04
N5.C2.D0.R0.S15: RdPtrOffsetTxDq: 05
N7.C1.D0.R0.S16: Total Delay in PI ticks: TxDQ = 940
N1.C1.D0.R1.S00: RdPtrOffsetTxDq: 06
N5.C2.D0.R0.S15: RdPtrOffsetTxDqs: 06
N7.C1.D0.R0.S17: Total Delay in PI ticks: TxDQ = 907
N1.C1.D0.R1.S00: RdPtrOffsetTxDqs: 07
N5.C2.D0.R0.S15: PiTxDqs: 47
N7.C1.D0.R1.S00: wrcmd2dqsstartlatency: 04
N1.C1.D0.R1.S00: PiTxDqs: 40
N5.C2.D0.R0.S16: wrcmd2dqsstartlatency: 04
N7.C1.D0.R1.S00: RdPtrOffsetTxDq: 06
N1.C1.D0.R1.S01: wrcmd2dqsstartlatency: 04
N5.C2.D0.R0.S16: RdPtrOffsetTxDq: 05
N7.C1.D0.R1.S00: RdPtrOffsetTxDqs: 07
N1.C1.D0.R1.S01: RdPtrOffsetTxDq: 05
N5.C2.D0.R0.S16: RdPtrOffsetTxDqs: 07
N7.C1.D0.R1.S00: PiTxDqs: 45
N1.C1.D0.R1.S01: RdPtrOffsetTxDqs: 07
N5.C2.D0.R0.S16: PiTxDqs: 03
N7.C1.D0.R1.S01: wrcmd2dqsstartlatency: 04
N1.C1.D0.R1.S01: PiTxDqs: 21
N5.C2.D0.R0.S17: wrcmd2dqsstartlatency: 04
N7.C1.D0.R1.S01: RdPtrOffsetTxDq: 05
N1.C1.D0.R1.S02: wrcmd2dqsstartlatency: 04
N5.C2.D0.R0.S17: RdPtrOffsetTxDq: 04
N7.C1.D0.R1.S01: RdPtrOffsetTxDqs: 07
N1.C1.D0.R1.S02: RdPtrOffsetTxDq: 05
N5.C2.D0.R0.S17: RdPtrOffsetTxDqs: 06
N7.C1.D0.R1.S01: PiTxDqs: 26
N1.C1.D0.R1.S02: RdPtrOffsetTxDqs: 07
N5.C2.D0.R0.S17: PiTxDqs: 33
N7.C1.D0.R1.S02: wrcmd2dqsstartlatency: 04
N1.C1.D0.R1.S02: PiTxDqs: 11
N5.C2.D0.R0.S00: RdPtrOffsetTxDq: 07
N7.C1.D0.R1.S02: RdPtrOffsetTxDq: 05
N1.C1.D0.R1.S03: wrcmd2dqsstartlatency: 04
N3.C0: Read Vref - Strobe:0 Worst Left Edge:-31, Worst Right Edge:31, Center:0
N5.C2.D0.R0.S01: RdPtrOffsetTxDq: 06
N7.C1.D0.R1.S02: RdPtrOffsetTxDqs: 07
N1.C1.D0.R1.S03: RdPtrOffsetTxDq: 05
N3.C0: Read Vref - Strobe:1 Worst Left Edge:-31, Worst Right Edge:31, Center:0
N5.C2.D0.R0.S02: RdPtrOffsetTxDq: 06
N7.C1.D0.R1.S02: PiTxDqs: 17
N1.C1.D0.R1.S03: RdPtrOffsetTxDqs: 06
N3.C0: Read Vref - Strobe:2 Worst Left Edge:-31, Worst Right Edge:31, Center:0
N5.C2.D0.R0.S03: RdPtrOffsetTxDq: 06
N7.C1.D0.R1.S03: wrcmd2dqsstartlatency: 04
N1.C1.D0.R1.S03: PiTxDqs: 59
N3.C0: Read Vref - Strobe:3 Worst Left Edge:-31, Worst Right Edge:31, Center:0
N5.C2.D0.R0.S04: RdPtrOffsetTxDq: 05
N7.C1.D0.R1.S03: RdPtrOffsetTxDq: 05
N1.C1.D0.R1.S04: wrcmd2dqsstartlatency: 04
N3.C0: Read Vref - Strobe:4 Worst Left Edge:-31, Worst Right Edge:31, Center:0
N5.C2.D0.R0.S05: RdPtrOffsetTxDq: 06
N7.C1.D0.R1.S03: RdPtrOffsetTxDqs: 07
N1.C1.D0.R1.S04: RdPtrOffsetTxDq: 04
N3.C0: Read Vref - Strobe:5 Worst Left Edge:-31, Worst Right Edge:31, Center:0
N5.C2.D0.R0.S06: RdPtrOffsetTxDq: 06
N7.C1.D0.R1.S03: PiTxDqs: 00
N1.C1.D0.R1.S04: RdPtrOffsetTxDqs: 06
N3.C0: Read Vref - Strobe:6 Worst Left Edge:-31, Worst Right Edge:31, Center:0
N5.C2.D0.R0.S07: RdPtrOffsetTxDq: 06
N7.C1.D0.R1.S04: wrcmd2dqsstartlatency: 04
N1.C1.D0.R1.S04: PiTxDqs: 27
N3.C0: Read Vref - Strobe:7 Worst Left Edge:-31, Worst Right Edge:31, Center:0
N5.C2.D0.R0.S08: RdPtrOffsetTxDq: 05
N7.C1.D0.R1.S04: RdPtrOffsetTxDq: 05
N1.C1.D0.R1.S05: wrcmd2dqsstartlatency: 04
N3.C0: Read Vref - Strobe:8 Worst Left Edge:-31, Worst Right Edge:31, Center:0
N5.C2.D0.R0.S09: RdPtrOffsetTxDq: 07
N7.C1.D0.R1.S04: RdPtrOffsetTxDqs: 06
N1.C1.D0.R1.S05: RdPtrOffsetTxDq: 05
N3.C0: Read Vref - Strobe:9 Worst Left Edge:-31, Worst Right Edge:31, Center:0
N5.C2.D0.R0.S10: RdPtrOffsetTxDq: 06
N7.C1.D0.R1.S04: PiTxDqs: 33
N1.C1.D0.R1.S05: RdPtrOffsetTxDqs: 06
N3.C0: Read Vref - Strobe:10 Worst Left Edge:-31, Worst Right Edge:31, Center:0
N5.C2.D0.R0.S11: RdPtrOffsetTxDq: 06
N7.C1.D0.R1.S05: wrcmd2dqsstartlatency: 04
N1.C1.D0.R1.S05: PiTxDqs: 40
N3.C0: Read Vref - Strobe:11 Worst Left Edge:-31, Worst Right Edge:31, Center:0
N5.C2.D0.R0.S12: RdPtrOffsetTxDq: 06
N7.C1.D0.R1.S05: RdPtrOffsetTxDq: 05
N1.C1.D0.R1.S06: wrcmd2dqsstartlatency: 04
N3.C0: Read Vref - Strobe:12 Worst Left Edge:-31, Worst Right Edge:31, Center:0
N5.C2.D0.R0.S13: RdPtrOffsetTxDq: 05
N7.C1.D0.R1.S05: RdPtrOffsetTxDqs: 06
N1.C1.D0.R1.S06: RdPtrOffsetTxDq: 05
N3.C0: Read Vref - Strobe:13 Worst Left Edge:-31, Worst Right Edge:31, Center:0
N5.C2.D0.R0.S14: RdPtrOffsetTxDq: 06
N7.C1.D0.R1.S05: PiTxDqs: 45
N1.C1.D0.R1.S06: RdPtrOffsetTxDqs: 06
N3.C0: Read Vref - Strobe:14 Worst Left Edge:-31, Worst Right Edge:31, Center:0
N5.C2.D0.R0.S15: RdPtrOffsetTxDq: 06
N7.C1.D0.R1.S06: wrcmd2dqsstartlatency: 04
N1.C1.D0.R1.S06: PiTxDqs: 52
N3.C0: Read Vref - Strobe:15 Worst Left Edge:-31, Worst Right Edge:31, Center:0
N5.C2.D0.R0.S16: RdPtrOffsetTxDq: 06
N7.C1.D0.R1.S06: RdPtrOffsetTxDq: 05
N1.C1.D0.R1.S07: wrcmd2dqsstartlatency: 04
N3.C0: Read Vref - Strobe:16 Worst Left Edge:-31, Worst Right Edge:31, Center:0
N5.C2.D0.R0.S17: RdPtrOffsetTxDq: 05
N7.C1.D0.R1.S06: RdPtrOffsetTxDqs: 06
N1.C1.D0.R1.S07: RdPtrOffsetTxDq: 05
N3.C0: Read Vref - Strobe:17 Worst Left Edge:-31, Worst Right Edge:31, Center:0
N5.C2.D0.R0.S00: RdPtrOffsetTxDq: 08
N7.C1.D0.R1.S06: PiTxDqs: 59
N1.C1.D0.R1.S07: RdPtrOffsetTxDqs: 07
N3.C1: Read Vref - Strobe:0 Worst Left Edge:-31, Worst Right Edge:31, Center:0
N5.C2.D0.R0.S01: RdPtrOffsetTxDq: 07
N7.C1.D0.R1.S07: wrcmd2dqsstartlatency: 04
N1.C1.D0.R1.S07: PiTxDqs: 06
N3.C1: Read Vref - Strobe:1 Worst Left Edge:-30, Worst Right Edge:31, Center:0
N5.C2.D0.R0.S02: RdPtrOffsetTxDq: 07
N7.C1.D0.R1.S07: RdPtrOffsetTxDq: 05
N1.C1.D0.R1.S08: wrcmd2dqsstartlatency: 04
N3.C1: Read Vref - Strobe:2 Worst Left Edge:-31, Worst Right Edge:31, Center:0
N5.C2.D0.R0.S03: RdPtrOffsetTxDq: 07
N7.C1.D0.R1.S07: RdPtrOffsetTxDqs: 07
N1.C1.D0.R1.S08: RdPtrOffsetTxDq: 05
N3.C1: Read Vref - Strobe:3 Worst Left Edge:-31, Worst Right Edge:31, Center:0
N5.C2.D0.R0.S04: RdPtrOffsetTxDq: 06
N7.C1.D0.R1.S07: PiTxDqs: 12
N1.C1.D0.R1.S08: RdPtrOffsetTxDqs: 06
N3.C1: Read Vref - Strobe:4 Worst Left Edge:-31, Worst Right Edge:31, Center:0
N5.C2.D0.R0.S05: RdPtrOffsetTxDq: 07
N7.C1.D0.R1.S08: wrcmd2dqsstartlatency: 04
N1.C1.D0.R1.S08: PiTxDqs: 36
N3.C1: Read Vref - Strobe:5 Worst Left Edge:-31, Worst Right Edge:31, Center:0
N5.C2.D0.R0.S06: RdPtrOffsetTxDq: 07
N7.C1.D0.R1.S08: RdPtrOffsetTxDq: 05
N1.C1.D0.R1.S09: wrcmd2dqsstartlatency: 04
N3.C1: Read Vref - Strobe:6 Worst Left Edge:-31, Worst Right Edge:31, Center:0
N5.C2.D0.R0.S07: RdPtrOffsetTxDq: 07
N7.C1.D0.R1.S08: RdPtrOffsetTxDqs: 06
N1.C1.D0.R1.S09: RdPtrOffsetTxDq: 06
N3.C1: Read Vref - Strobe:7 Worst Left Edge:-31, Worst Right Edge:31, Center:0
N5.C2.D0.R0.S08: RdPtrOffsetTxDq: 06
N7.C1.D0.R1.S08: PiTxDqs: 45
N1.C1.D0.R1.S09: RdPtrOffsetTxDqs: 07
N3.C1: Read Vref - Strobe:8 Worst Left Edge:-31, Worst Right Edge:31, Center:0
N5.C2.D0.R0.S09: RdPtrOffsetTxDq: 08
N7.C1.D0.R1.S09: wrcmd2dqsstartlatency: 04
N1.C1.D0.R1.S09: PiTxDqs: 37
N3.C1: Read Vref - Strobe:9 Worst Left Edge:-31, Worst Right Edge:31, Center:0
N5.C2.D0.R0.S10: RdPtrOffsetTxDq: 07
N7.C1.D0.R1.S09: RdPtrOffsetTxDq: 06
N1.C1.D0.R1.S10: wrcmd2dqsstartlatency: 04
N3.C1: Read Vref - Strobe:10 Worst Left Edge:-31, Worst Right Edge:31, Center:0
N5.C2.D0.R0.S11: RdPtrOffsetTxDq: 07
N7.C1.D0.R1.S09: RdPtrOffsetTxDqs: 07
N1.C1.D0.R1.S10: RdPtrOffsetTxDq: 05
N3.C1: Read Vref - Strobe:11 Worst Left Edge:-31, Worst Right Edge:31, Center:0
N5.C2.D0.R0.S12: RdPtrOffsetTxDq: 07
N7.C1.D0.R1.S09: PiTxDqs: 41
N1.C1.D0.R1.S10: RdPtrOffsetTxDqs: 07
N3.C1: Read Vref - Strobe:12 Worst Left Edge:-30, Worst Right Edge:31, Center:0
N5.C2.D0.R0.S13: RdPtrOffsetTxDq: 06
N7.C1.D0.R1.S10: wrcmd2dqsstartlatency: 04
N1.C1.D0.R1.S10: PiTxDqs: 21
N3.C1: Read Vref - Strobe:13 Worst Left Edge:-31, Worst Right Edge:31, Center:0
N5.C2.D0.R0.S14: RdPtrOffsetTxDq: 07
N7.C1.D0.R1.S10: RdPtrOffsetTxDq: 05
N1.C1.D0.R1.S11: wrcmd2dqsstartlatency: 04
N3.C1: Read Vref - Strobe:14 Worst Left Edge:-31, Worst Right Edge:31, Center:0
N5.C2.D0.R0.S15: RdPtrOffsetTxDq: 07
N7.C1.D0.R1.S10: RdPtrOffsetTxDqs: 07
N1.C1.D0.R1.S11: RdPtrOffsetTxDq: 05
N3.C1: Read Vref - Strobe:15 Worst Left Edge:-31, Worst Right Edge:31, Center:0
N5.C2.D0.R0.S16: RdPtrOffsetTxDq: 07
N7.C1.D0.R1.S10: PiTxDqs: 28
N1.C1.D0.R1.S11: RdPtrOffsetTxDqs: 07
N3.C1: Read Vref - Strobe:16 Worst Left Edge:-30, Worst Right Edge:31, Center:0
N5.C2.D0.R0.S17: RdPtrOffsetTxDq: 06
N7.C1.D0.R1.S11: wrcmd2dqsstartlatency: 04
N1.C1.D0.R1.S11: PiTxDqs: 11
N3.C1: Read Vref - Strobe:17 Worst Left Edge:-31, Worst Right Edge:31, Center:0
N5.C2.D0.R0.S00: Total Delay in PI ticks: TxDQ = 964
N7.C1.D0.R1.S11: RdPtrOffsetTxDq: 05
N1.C1.D0.R1.S12: wrcmd2dqsstartlatency: 04
N3.C2: Read Vref - Strobe:0 Worst Left Edge:-31, Worst Right Edge:31, Center:0
N5.C2.D0.R0.S01: Total Delay in PI ticks: TxDQ = 949
N7.C1.D0.R1.S11: RdPtrOffsetTxDqs: 07
N1.C1.D0.R1.S12: RdPtrOffsetTxDq: 05
N3.C2: Read Vref - Strobe:1 Worst Left Edge:-31, Worst Right Edge:31, Center:0
N5.C2.D0.R0.S02: Total Delay in PI ticks: TxDQ = 941
N7.C1.D0.R1.S11: PiTxDqs: 18
N1.C1.D0.R1.S12: RdPtrOffsetTxDqs: 06
N3.C2: Read Vref - Strobe:2 Worst Left Edge:-31, Worst Right Edge:31, Center:0
N5.C2.D0.R0.S03: Total Delay in PI ticks: TxDQ = 923
N7.C1.D0.R1.S12: wrcmd2dqsstartlatency: 04
N1.C1.D0.R1.S12: PiTxDqs: 58
N3.C2: Read Vref - Strobe:3 Worst Left Edge:-31, Worst Right Edge:31, Center:0
N5.C2.D0.R0.S04: Total Delay in PI ticks: TxDQ = 880
N7.C1.D0.R1.S12: RdPtrOffsetTxDq: 05
N1.C1.D0.R1.S13: wrcmd2dqsstartlatency: 04
N3.C2: Read Vref - Strobe:4 Worst Left Edge:-31, Worst Right Edge:31, Center:0
N5.C2.D0.R0.S05: Total Delay in PI ticks: TxDQ = 908
N7.C1.D0.R1.S12: RdPtrOffsetTxDqs: 07
N1.C1.D0.R1.S13: RdPtrOffsetTxDq: 04
N3.C2: Read Vref - Strobe:5 Worst Left Edge:-31, Worst Right Edge:31, Center:0
N5.C2.D0.R0.S06: Total Delay in PI ticks: TxDQ = 909
N7.C1.D0.R1.S12: PiTxDqs: 00
N1.C1.D0.R1.S13: RdPtrOffsetTxDqs: 06
N3.C2: Read Vref - Strobe:6 Worst Left Edge:-31, Worst Right Edge:31, Center:0
N5.C2.D0.R0.S07: Total Delay in PI ticks: TxDQ = 932
N7.C1.D0.R1.S13: wrcmd2dqsstartlatency: 04
N1.C1.D0.R1.S13: PiTxDqs: 28
N3.C2: Read Vref - Strobe:7 Worst Left Edge:-31, Worst Right Edge:31, Center:0
N5.C2.D0.R0.S08: Total Delay in PI ticks: TxDQ = 894
N7.C1.D0.R1.S13: RdPtrOffsetTxDq: 04
N1.C1.D0.R1.S14: wrcmd2dqsstartlatency: 04
N3.C2: Read Vref - Strobe:8 Worst Left Edge:-31, Worst Right Edge:31, Center:0
N5.C2.D0.R0.S09: Total Delay in PI ticks: TxDQ = 962
N7.C1.D0.R1.S13: RdPtrOffsetTxDqs: 06
N1.C1.D0.R1.S14: RdPtrOffsetTxDq: 05
N3.C2: Read Vref - Strobe:9 Worst Left Edge:-31, Worst Right Edge:31, Center:0
N5.C2.D0.R0.S10: Total Delay in PI ticks: TxDQ = 949
N7.C1.D0.R1.S13: PiTxDqs: 32
N1.C1.D0.R1.S14: RdPtrOffsetTxDqs: 06
N3.C2: Read Vref - Strobe:10 Worst Left Edge:-31, Worst Right Edge:31, Center:0
N5.C2.D0.R0.S11: Total Delay in PI ticks: TxDQ = 940
N7.C1.D0.R1.S14: wrcmd2dqsstartlatency: 04
N1.C1.D0.R1.S14: PiTxDqs: 40
N3.C2: Read Vref - Strobe:11 Worst Left Edge:-31, Worst Right Edge:31, Center:0
N5.C2.D0.R0.S12: Total Delay in PI ticks: TxDQ = 922
N7.C1.D0.R1.S14: RdPtrOffsetTxDq: 05
N1.C1.D0.R1.S15: wrcmd2dqsstartlatency: 04
N3.C2: Read Vref - Strobe:12 Worst Left Edge:-31, Worst Right Edge:31, Center:0
N5.C2.D0.R0.S13: Total Delay in PI ticks: TxDQ = 880
N7.C1.D0.R1.S14: RdPtrOffsetTxDqs: 06
N1.C1.D0.R1.S15: RdPtrOffsetTxDq: 05
N3.C2: Read Vref - Strobe:13 Worst Left Edge:-31, Worst Right Edge:31, Center:0
N5.C2.D0.R0.S14: Total Delay in PI ticks: TxDQ = 908
N7.C1.D0.R1.S14: PiTxDqs: 46
N1.C1.D0.R1.S15: RdPtrOffsetTxDqs: 06
N3.C2: Read Vref - Strobe:14 Worst Left Edge:-31, Worst Right Edge:31, Center:0
N5.C2.D0.R0.S15: Total Delay in PI ticks: TxDQ = 909
N7.C1.D0.R1.S15: wrcmd2dqsstartlatency: 04
N1.C1.D0.R1.S15: PiTxDqs: 52
N3.C2: Read Vref - Strobe:15 Worst Left Edge:-31, Worst Right Edge:31, Center:0
N5.C2.D0.R0.S16: Total Delay in PI ticks: TxDQ = 929
N7.C1.D0.R1.S15: RdPtrOffsetTxDq: 05
N1.C1.D0.R1.S16: wrcmd2dqsstartlatency: 04
N3.C2: Read Vref - Strobe:16 Worst Left Edge:-31, Worst Right Edge:31, Center:0
N5.C2.D0.R0.S17: Total Delay in PI ticks: TxDQ = 894
N7.C1.D0.R1.S15: RdPtrOffsetTxDqs: 06
N1.C1.D0.R1.S16: RdPtrOffsetTxDq: 05
N3.C2: Read Vref - Strobe:17 Worst Left Edge:-31, Worst Right Edge:31, Center:0
N5.C2.D0.R1.S00: wrcmd2dqsstartlatency: 04
N7.C1.D0.R1.S15: PiTxDqs: 58
N1.C1.D0.R1.S16: RdPtrOffsetTxDqs: 07
N3.C3: Read Vref - Strobe:0 Worst Left Edge:-31, Worst Right Edge:31, Center:0
N5.C2.D0.R1.S00: RdPtrOffsetTxDq: 06
N7.C1.D0.R1.S16: wrcmd2dqsstartlatency: 04
N1.C1.D0.R1.S16: PiTxDqs: 08
N3.C3: Read Vref - Strobe:1 Worst Left Edge:-31, Worst Right Edge:31, Center:0
N5.C2.D0.R1.S00: RdPtrOffsetTxDqs: 07
N7.C1.D0.R1.S16: RdPtrOffsetTxDq: 05
N1.C1.D0.R1.S17: wrcmd2dqsstartlatency: 04
N3.C3: Read Vref - Strobe:2 Worst Left Edge:-31, Worst Right Edge:31, Center:0
N5.C2.D0.R1.S00: PiTxDqs: 35
N7.C1.D0.R1.S16: RdPtrOffsetTxDqs: 07
N1.C1.D0.R1.S17: RdPtrOffsetTxDq: 05
N3.C3: Read Vref - Strobe:3 Worst Left Edge:-31, Worst Right Edge:31, Center:0
N5.C2.D0.R1.S01: wrcmd2dqsstartlatency: 04
N7.C1.D0.R1.S16: PiTxDqs: 12
N1.C1.D0.R1.S17: RdPtrOffsetTxDqs: 06
N3.C3: Read Vref - Strobe:4 Worst Left Edge:-31, Worst Right Edge:31, Center:0
N5.C2.D0.R1.S01: RdPtrOffsetTxDq: 05
N7.C1.D0.R1.S17: wrcmd2dqsstartlatency: 04
N1.C1.D0.R1.S17: PiTxDqs: 37
N3.C3: Read Vref - Strobe:5 Worst Left Edge:-31, Worst Right Edge:31, Center:0
N5.C2.D0.R1.S01: RdPtrOffsetTxDqs: 07
N7.C1.D0.R1.S17: RdPtrOffsetTxDq: 05
N1.C1.D0.R1.S00: RdPtrOffsetTxDq: 07
N3.C3: Read Vref - Strobe:6 Worst Left Edge:-31, Worst Right Edge:31, Center:0
N5.C2.D0.R1.S01: PiTxDqs: 23
N7.C1.D0.R1.S17: RdPtrOffsetTxDqs: 06
N1.C1.D0.R1.S01: RdPtrOffsetTxDq: 06
N3.C3: Read Vref - Strobe:7 Worst Left Edge:-31, Worst Right Edge:31, Center:0
N5.C2.D0.R1.S02: wrcmd2dqsstartlatency: 04
N7.C1.D0.R1.S17: PiTxDqs: 43
N1.C1.D0.R1.S02: RdPtrOffsetTxDq: 06
N3.C3: Read Vref - Strobe:8 Worst Left Edge:-31, Worst Right Edge:31, Center:0
N5.C2.D0.R1.S02: RdPtrOffsetTxDq: 05
N7.C1.D0.R1.S00: RdPtrOffsetTxDq: 07
N1.C1.D0.R1.S03: RdPtrOffsetTxDq: 06
N3.C3: Read Vref - Strobe:9 Worst Left Edge:-30, Worst Right Edge:31, Center:0
N5.C2.D0.R1.S02: RdPtrOffsetTxDqs: 07
N7.C1.D0.R1.S01: RdPtrOffsetTxDq: 06
N1.C1.D0.R1.S04: RdPtrOffsetTxDq: 05
N3.C3: Read Vref - Strobe:10 Worst Left Edge:-31, Worst Right Edge:31, Center:0
N5.C2.D0.R1.S02: PiTxDqs: 11
N7.C1.D0.R1.S02: RdPtrOffsetTxDq: 06
N1.C1.D0.R1.S05: RdPtrOffsetTxDq: 06
N3.C3: Read Vref - Strobe:11 Worst Left Edge:-31, Worst Right Edge:31, Center:0
N5.C2.D0.R1.S03: wrcmd2dqsstartlatency: 04
N7.C1.D0.R1.S03: RdPtrOffsetTxDq: 06
N1.C1.D0.R1.S06: RdPtrOffsetTxDq: 06
N3.C3: Read Vref - Strobe:12 Worst Left Edge:-31, Worst Right Edge:31, Center:0
N5.C2.D0.R1.S03: RdPtrOffsetTxDq: 05
N7.C1.D0.R1.S04: RdPtrOffsetTxDq: 06
N1.C1.D0.R1.S07: RdPtrOffsetTxDq: 06
N3.C3: Read Vref - Strobe:13 Worst Left Edge:-31, Worst Right Edge:31, Center:0
N5.C2.D0.R1.S03: RdPtrOffsetTxDqs: 06
N7.C1.D0.R1.S05: RdPtrOffsetTxDq: 06
N1.C1.D0.R1.S08: RdPtrOffsetTxDq: 06
N3.C3: Read Vref - Strobe:14 Worst Left Edge:-31, Worst Right Edge:31, Center:0
N5.C2.D0.R1.S03: PiTxDqs: 58
N7.C1.D0.R1.S06: RdPtrOffsetTxDq: 06
N1.C1.D0.R1.S09: RdPtrOffsetTxDq: 07
N3.C3: Read Vref - Strobe:15 Worst Left Edge:-31, Worst Right Edge:31, Center:0
N5.C2.D0.R1.S04: wrcmd2dqsstartlatency: 04
N7.C1.D0.R1.S07: RdPtrOffsetTxDq: 06
N1.C1.D0.R1.S10: RdPtrOffsetTxDq: 06
N3.C3: Read Vref - Strobe:16 Worst Left Edge:-31, Worst Right Edge:31, Center:0
N5.C2.D0.R1.S04: RdPtrOffsetTxDq: 04
N7.C1.D0.R1.S08: RdPtrOffsetTxDq: 06
N1.C1.D0.R1.S11: RdPtrOffsetTxDq: 06
N3.C3: Read Vref - Strobe:17 Worst Left Edge:-31, Worst Right Edge:31, Center:0
N5.C2.D0.R1.S04: RdPtrOffsetTxDqs: 06
N7.C1.D0.R1.S09: RdPtrOffsetTxDq: 07
N1.C1.D0.R1.S12: RdPtrOffsetTxDq: 06
N3: RunTrainStep: Final status = 0
N5.C2.D0.R1.S04: PiTxDqs: 16
N7.C1.D0.R1.S10: RdPtrOffsetTxDq: 06
N1.C1.D0.R1.S13: RdPtrOffsetTxDq: 05

END - Rd Voltage Training              Time         3031 ms
N5.C2.D0.R1.S05: wrcmd2dqsstartlatency: 04
N7.C1.D0.R1.S11: RdPtrOffsetTxDq: 06
N1.C1.D0.R1.S14: RdPtrOffsetTxDq: 06
N3.C0.D0.R0.S00: StoreJckWorstRank: worst rank = 0, greatestDelay = 1313
N5.C2.D0.R1.S05: RdPtrOffsetTxDq: 05
N7.C1.D0.R1.S12: RdPtrOffsetTxDq: 06
N1.C1.D0.R1.S15: RdPtrOffsetTxDq: 06
N3.C0.D0.R0.S07: StoreJckWorstRank: worst rank = 0, greatestDelay = 1317
N5.C2.D0.R1.S05: RdPtrOffsetTxDqs: 06
N7.C1.D0.R1.S13: RdPtrOffsetTxDq: 05
N1.C1.D0.R1.S16: RdPtrOffsetTxDq: 06
N3.C0.D0.R1.S16: StoreJckWorstRank: worst rank = 1, greatestDelay = 1318
N5.C2.D0.R1.S05: PiTxDqs: 47
N7.C1.D0.R1.S14: RdPtrOffsetTxDq: 06
N1.C1.D0.R1.S17: RdPtrOffsetTxDq: 06
N3.C1.D0.R0.S00: StoreJckWorstRank: worst rank = 0, greatestDelay = 1356
N5.C2.D0.R1.S06: wrcmd2dqsstartlatency: 04
N7.C1.D0.R1.S15: RdPtrOffsetTxDq: 06
N1.C1.D0.R1.S00: RdPtrOffsetTxDq: 08
N3.C0: StoreJckWorstRank: final value: worst rank = 0
N5.C2.D0.R1.S06: RdPtrOffsetTxDq: 05
N7.C1.D0.R1.S16: RdPtrOffsetTxDq: 06
N1.C1.D0.R1.S01: RdPtrOffsetTxDq: 07
N3.C2.D0.R0.S00: StoreJckWorstRank: worst rank = 0, greatestDelay = 1306
N5.C2.D0.R1.S06: RdPtrOffsetTxDqs: 06
N7.C1.D0.R1.S17: RdPtrOffsetTxDq: 06
N1.C1.D0.R1.S02: RdPtrOffsetTxDq: 07
N3.C2.D0.R0.S09: StoreJckWorstRank: worst rank = 0, greatestDelay = 1308
N5.C2.D0.R1.S06: PiTxDqs: 46
N7.C1.D0.R1.S00: RdPtrOffsetTxDq: 08
N1.C1.D0.R1.S03: RdPtrOffsetTxDq: 07
N3.C2.D0.R1.S09: StoreJckWorstRank: worst rank = 1, greatestDelay = 1309
N5.C2.D0.R1.S07: wrcmd2dqsstartlatency: 04
N7.C1.D0.R1.S01: RdPtrOffsetTxDq: 07
N1.C1.D0.R1.S04: RdPtrOffsetTxDq: 06
N3.C3.D0.R0.S00: StoreJckWorstRank: worst rank = 0, greatestDelay = 1353
N5.C2.D0.R1.S07: RdPtrOffsetTxDq: 05
N7.C1.D0.R1.S02: RdPtrOffsetTxDq: 07
N1.C1.D0.R1.S05: RdPtrOffsetTxDq: 07
N3.C3.D0.R0.S09: StoreJckWorstRank: worst rank = 0, greatestDelay = 1356
N5.C2.D0.R1.S07: RdPtrOffsetTxDqs: 07
N7.C1.D0.R1.S03: RdPtrOffsetTxDq: 07
N1.C1.D0.R1.S06: RdPtrOffsetTxDq: 07
N3.C1: StoreJckWorstRank: final value: worst rank = 0
N5.C2.D0.R1.S07: PiTxDqs: 04
N7.C1.D0.R1.S04: RdPtrOffsetTxDq: 07
N1.C1.D0.R1.S07: RdPtrOffsetTxDq: 07
GetAllRankMargins
N5.C2.D0.R1.S08: wrcmd2dqsstartlatency: 04
N7.C1.D0.R1.S05: RdPtrOffsetTxDq: 07
N1.C1.D0.R1.S08: RdPtrOffsetTxDq: 07
N3: Checking margins for all ranks...
N5.C2.D0.R1.S08: RdPtrOffsetTxDq: 04
N7.C1.D0.R1.S06: RdPtrOffsetTxDq: 07
N1.C1.D0.R1.S09: RdPtrOffsetTxDq: 08
N3: 
Get Rx Dqs margins...
N5.C2.D0.R1.S08: RdPtrOffsetTxDqs: 06
N7.C1.D0.R1.S07: RdPtrOffsetTxDq: 07
N1.C1.D0.R1.S10: RdPtrOffsetTxDq: 07
N3: GetMargins: Level = 1, group = 11, mode = 0, scope = 3
N5.C2.D0.R1.S08: PiTxDqs: 33
N7.C1.D0.R1.S08: RdPtrOffsetTxDq: 07
N1.C1.D0.R1.S11: RdPtrOffsetTxDq: 07
N5.C2.D0.R1.S09: wrcmd2dqsstartlatency: 04
N7.C1.D0.R1.S09: RdPtrOffsetTxDq: 08
N1.C1.D0.R1.S12: RdPtrOffsetTxDq: 07
N5.C2.D0.R1.S09: RdPtrOffsetTxDq: 06
N7.C1.D0.R1.S10: RdPtrOffsetTxDq: 07
N1.C1.D0.R1.S13: RdPtrOffsetTxDq: 06
N5.C2.D0.R1.S09: RdPtrOffsetTxDqs: 07
N7.C1.D0.R1.S11: RdPtrOffsetTxDq: 07
N1.C1.D0.R1.S14: RdPtrOffsetTxDq: 07
N5.C2.D0.R1.S09: PiTxDqs: 35
N7.C1.D0.R1.S12: RdPtrOffsetTxDq: 07
N1.C1.D0.R1.S15: RdPtrOffsetTxDq: 07
N5.C2.D0.R1.S10: wrcmd2dqsstartlatency: 04
N7.C1.D0.R1.S13: RdPtrOffsetTxDq: 06
N1.C1.D0.R1.S16: RdPtrOffsetTxDq: 07
N5.C2.D0.R1.S10: RdPtrOffsetTxDq: 05
N7.C1.D0.R1.S14: RdPtrOffsetTxDq: 07
N1.C1.D0.R1.S17: RdPtrOffsetTxDq: 07
N5.C2.D0.R1.S10: RdPtrOffsetTxDqs: 07
N7.C1.D0.R1.S15: RdPtrOffsetTxDq: 07
N1.C1.D0.R1.S00: Total Delay in PI ticks: TxDQ = 967
N5.C2.D0.R1.S10: PiTxDqs: 23
N7.C1.D0.R1.S16: RdPtrOffsetTxDq: 07
N1.C1.D0.R1.S01: Total Delay in PI ticks: TxDQ = 948
N5.C2.D0.R1.S11: wrcmd2dqsstartlatency: 04
N7.C1.D0.R1.S17: RdPtrOffsetTxDq: 07
N1.C1.D0.R1.S02: Total Delay in PI ticks: TxDQ = 938
N5.C2.D0.R1.S11: RdPtrOffsetTxDq: 05
N7.C1.D0.R1.S00: Total Delay in PI ticks: TxDQ = 972
N1.C1.D0.R1.S03: Total Delay in PI ticks: TxDQ = 923
N5.C2.D0.R1.S11: RdPtrOffsetTxDqs: 07
N7.C1.D0.R1.S01: Total Delay in PI ticks: TxDQ = 953
N1.C1.D0.R1.S04: Total Delay in PI ticks: TxDQ = 890
N5.C2.D0.R1.S11: PiTxDqs: 14
N7.C1.D0.R1.S02: Total Delay in PI ticks: TxDQ = 944
N1.C1.D0.R1.S05: Total Delay in PI ticks: TxDQ = 902
N5.C2.D0.R1.S12: wrcmd2dqsstartlatency: 04
N7.C1.D0.R1.S03: Total Delay in PI ticks: TxDQ = 925
N1.C1.D0.R1.S06: Total Delay in PI ticks: TxDQ = 916
N5.C2.D0.R1.S12: RdPtrOffsetTxDq: 05
N7.C1.D0.R1.S04: Total Delay in PI ticks: TxDQ = 896
N1.C1.D0.R1.S07: Total Delay in PI ticks: TxDQ = 933
N5.C2.D0.R1.S12: RdPtrOffsetTxDqs: 06
N7.C1.D0.R1.S05: Total Delay in PI ticks: TxDQ = 908
N1.C1.D0.R1.S08: Total Delay in PI ticks: TxDQ = 900
N5.C2.D0.R1.S12: PiTxDqs: 61
N7.C1.D0.R1.S06: Total Delay in PI ticks: TxDQ = 923
N1.C1.D0.R1.S09: Total Delay in PI ticks: TxDQ = 964
N5.C2.D0.R1.S13: wrcmd2dqsstartlatency: 04
N7.C1.D0.R1.S07: Total Delay in PI ticks: TxDQ = 936
N1.C1.D0.R1.S10: Total Delay in PI ticks: TxDQ = 947
N5.C2.D0.R1.S13: RdPtrOffsetTxDq: 04
N7.C1.D0.R1.S08: Total Delay in PI ticks: TxDQ = 906
N1.C1.D0.R1.S11: Total Delay in PI ticks: TxDQ = 940
N5.C2.D0.R1.S13: RdPtrOffsetTxDqs: 06
N7.C1.D0.R1.S09: Total Delay in PI ticks: TxDQ = 969
N1.C1.D0.R1.S12: Total Delay in PI ticks: TxDQ = 922
N5.C2.D0.R1.S13: PiTxDqs: 16
N7.C1.D0.R1.S10: Total Delay in PI ticks: TxDQ = 953
N1.C1.D0.R1.S13: Total Delay in PI ticks: TxDQ = 891
N5.C2.D0.R1.S14: wrcmd2dqsstartlatency: 04
N7.C1.D0.R1.S11: Total Delay in PI ticks: TxDQ = 947
N1.C1.D0.R1.S14: Total Delay in PI ticks: TxDQ = 901
N5.C2.D0.R1.S14: RdPtrOffsetTxDq: 05
N7.C1.D0.R1.S12: Total Delay in PI ticks: TxDQ = 927
N1.C1.D0.R1.S15: Total Delay in PI ticks: TxDQ = 917
N5.C2.D0.R1.S14: RdPtrOffsetTxDqs: 06
N7.C1.D0.R1.S13: Total Delay in PI ticks: TxDQ = 894
N1.C1.D0.R1.S16: Total Delay in PI ticks: TxDQ = 934
N3: 
Get Tx Dq margins...
N5.C2.D0.R1.S14: PiTxDqs: 47
N7.C1.D0.R1.S14: Total Delay in PI ticks: TxDQ = 908
N1.C1.D0.R1.S17: Total Delay in PI ticks: TxDQ = 900
N3: GetMargins: Level = 1, group = 12, mode = 0, scope = 3
N5.C2.D0.R1.S15: wrcmd2dqsstartlatency: 04
N7.C1.D0.R1.S15: Total Delay in PI ticks: TxDQ = 922
N1.C1: Calculating Optimimum DQ/DQS Values
N5.C2.D0.R1.S15: RdPtrOffsetTxDq: 05
N7.C1.D0.R1.S16: Total Delay in PI ticks: TxDQ = 939
N5.C2.D0.R1.S15: RdPtrOffsetTxDqs: 06
N7.C1.D0.R1.S17: Total Delay in PI ticks: TxDQ = 906
START_DATA_TX_DQ
N5.C2.D0.R1.S15: PiTxDqs: 47
N7.C1: Calculating Optimimum DQ/DQS Values
N1.C1.S00: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 009, RdPtrOffsetTxDqs = 009
N5.C2.D0.R1.S16: wrcmd2dqsstartlatency: 04
START_DATA_TX_DQ
N1.C1.S00: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 009, RdPtrOffsetTxDqs = 009
N5.C2.D0.R1.S16: RdPtrOffsetTxDq: 05
N7.C1.S00: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 009, RdPtrOffsetTxDqs = 009
N1.C1.S01: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 009
N5.C2.D0.R1.S16: RdPtrOffsetTxDqs: 07
N7.C1.S00: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 009, RdPtrOffsetTxDqs = 009
N1.C1.S01: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 009
N5.C2.D0.R1.S16: PiTxDqs: 06
N7.C1.S01: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 009
N1.C1.S02: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 009
N5.C2.D0.R1.S17: wrcmd2dqsstartlatency: 04
N7.C1.S01: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 009
N1.C1.S02: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 009
N5.C2.D0.R1.S17: RdPtrOffsetTxDq: 04
N7.C1.S02: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 009
N1.C1.S03: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 008
N5.C2.D0.R1.S17: RdPtrOffsetTxDqs: 06
N7.C1.S02: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 009
N1.C1.S03: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 008
N5.C2.D0.R1.S17: PiTxDqs: 33
N7.C1.S03: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 009
N1.C1.S04: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 007, RdPtrOffsetTxDqs = 008
N5.C2.D0.R1.S00: RdPtrOffsetTxDq: 07
N7.C1.S03: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 009
N1.C1.S04: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 007, RdPtrOffsetTxDqs = 008
N5.C2.D0.R1.S01: RdPtrOffsetTxDq: 06
N7.C1.S04: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 007, RdPtrOffsetTxDqs = 008
N1.C1.S05: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 008
N5.C2.D0.R1.S02: RdPtrOffsetTxDq: 06
N7.C1.S04: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 007, RdPtrOffsetTxDqs = 008
N1.C1.S05: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 008
N5.C2.D0.R1.S03: RdPtrOffsetTxDq: 06
N7.C1.S05: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 008
N1.C1.S06: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 008
N5.C2.D0.R1.S04: RdPtrOffsetTxDq: 05
N7.C1.S05: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 008
N1.C1.S06: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 008
N5.C2.D0.R1.S05: RdPtrOffsetTxDq: 06
N7.C1.S06: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 008
N1.C1.S07: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 009
N5.C2.D0.R1.S06: RdPtrOffsetTxDq: 06
N7.C1.S06: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 008
N1.C1.S07: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 009
N5.C2.D0.R1.S07: RdPtrOffsetTxDq: 06
N7.C1.S07: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 009
N1.C1.S08: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 008
N5.C2.D0.R1.S08: RdPtrOffsetTxDq: 05
N7.C1.S07: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 009
N1.C1.S08: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 008
N5.C2.D0.R1.S09: RdPtrOffsetTxDq: 07
N7.C1.S08: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 008
N1.C1.D0.R0.S00: TxDqs: plus1 = 1, minus1 = 0, PI = 39, DB = 0
N5.C2.D0.R1.S10: RdPtrOffsetTxDq: 06
N7.C1.S08: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 008
N1.C1.D0.R0.S00: TxDq : plus1 = 1, minus1 = 0, PI = 06, DB = 1
N5.C2.D0.R1.S11: RdPtrOffsetTxDq: 06
N7.C1.D0.R0.S00: TxDqs: plus1 = 1, minus1 = 0, PI = 44, DB = 0
N1.C1.D0.R0.S01: TxDqs: plus1 = 1, minus1 = 0, PI = 22, DB = 0
N5.C2.D0.R1.S12: RdPtrOffsetTxDq: 06
N7.C1.D0.R0.S00: TxDq : plus1 = 1, minus1 = 0, PI = 11, DB = 1
N1.C1.D0.R0.S01: TxDq : plus1 = 1, minus1 = 0, PI = 52, DB = 1
N5.C2.D0.R1.S13: RdPtrOffsetTxDq: 05
N7.C1.D0.R0.S01: TxDqs: plus1 = 1, minus1 = 0, PI = 26, DB = 0
N1.C1.D0.R0.S02: TxDqs: plus1 = 1, minus1 = 0, PI = 11, DB = 1
N5.C2.D0.R1.S14: RdPtrOffsetTxDq: 06
N7.C1.D0.R0.S01: TxDq : plus1 = 1, minus1 = 0, PI = 57, DB = 1
N1.C1.D0.R0.S02: TxDq : plus1 = 1, minus1 = 0, PI = 43, DB = 0
N5.C2.D0.R1.S15: RdPtrOffsetTxDq: 06
N7.C1.D0.R0.S02: TxDqs: plus1 = 1, minus1 = 0, PI = 18, DB = 0
N1.C1.D0.R0.S03: TxDqs: plus1 = 1, minus1 = 0, PI = 59, DB = 1
N5.C2.D0.R1.S16: RdPtrOffsetTxDq: 06
N7.C1.D0.R0.S02: TxDq : plus1 = 1, minus1 = 0, PI = 49, DB = 1
N1.C1.D0.R0.S03: TxDq : plus1 = 1, minus1 = 0, PI = 27, DB = 0
N5.C2.D0.R1.S17: RdPtrOffsetTxDq: 05
N7.C1.D0.R0.S03: TxDqs: plus1 = 1, minus1 = 0, PI = 00, DB = 1
N1.C1.D0.R0.S04: TxDqs: plus1 = 1, minus1 = 0, PI = 27, DB = 0
N5.C2.D0.R1.S00: RdPtrOffsetTxDq: 08
N7.C1.D0.R0.S03: TxDq : plus1 = 1, minus1 = 0, PI = 30, DB = 0
N1.C1.D0.R0.S04: TxDq : plus1 = 1, minus1 = 0, PI = 57, DB = 1
N5.C2.D0.R1.S01: RdPtrOffsetTxDq: 07
N7.C1.D0.R0.S04: TxDqs: plus1 = 1, minus1 = 0, PI = 32, DB = 0
N1.C1.D0.R0.S05: TxDqs: plus1 = 1, minus1 = 0, PI = 40, DB = 0
N5.C2.D0.R1.S02: RdPtrOffsetTxDq: 07
N7.C1.D0.R0.S04: TxDq : plus1 = 1, minus1 = 0, PI = 63, DB = 1
N1.C1.D0.R0.S05: TxDq : plus1 = 1, minus1 = 0, PI = 05, DB = 1
N5.C2.D0.R1.S03: RdPtrOffsetTxDq: 07
N7.C1.D0.R0.S05: TxDqs: plus1 = 1, minus1 = 0, PI = 45, DB = 0
N1.C1.D0.R0.S06: TxDqs: plus1 = 1, minus1 = 0, PI = 52, DB = 1
N5.C2.D0.R1.S04: RdPtrOffsetTxDq: 06
N7.C1.D0.R0.S05: TxDq : plus1 = 1, minus1 = 0, PI = 13, DB = 1
N1.C1.D0.R0.S06: TxDq : plus1 = 1, minus1 = 0, PI = 20, DB = 0
N5.C2.D0.R1.S05: RdPtrOffsetTxDq: 07
N7.C1.D0.R0.S06: TxDqs: plus1 = 1, minus1 = 0, PI = 59, DB = 1
N1.C1.D0.R0.S07: TxDqs: plus1 = 1, minus1 = 0, PI = 05, DB = 1
N5.C2.D0.R1.S06: RdPtrOffsetTxDq: 07
N7.C1.D0.R0.S06: TxDq : plus1 = 1, minus1 = 0, PI = 27, DB = 0
N1.C1.D0.R0.S07: TxDq : plus1 = 1, minus1 = 0, PI = 37, DB = 0
N5.C2.D0.R1.S07: RdPtrOffsetTxDq: 07
N7.C1.D0.R0.S07: TxDqs: plus1 = 1, minus1 = 0, PI = 13, DB = 1
N1.C1.D0.R0.S08: TxDqs: plus1 = 1, minus1 = 0, PI = 37, DB = 0
N3: 
Get Rx Vref margins...
N5.C2.D0.R1.S08: RdPtrOffsetTxDq: 06
N7.C1.D0.R0.S07: TxDq : plus1 = 1, minus1 = 0, PI = 42, DB = 0
N1.C1.D0.R0.S08: TxDq : plus1 = 1, minus1 = 0, PI = 05, DB = 1
N3: GetMargins: Level = 1, group = 13, mode = 0, scope = 3
N5.C2.D0.R1.S09: RdPtrOffsetTxDq: 08
N7.C1.D0.R0.S08: TxDqs: plus1 = 1, minus1 = 0, PI = 45, DB = 0
N1.C1.D0.R0.S09: TxDqs: plus1 = 1, minus1 = 0, PI = 39, DB = 0
N5.C2.D0.R1.S10: RdPtrOffsetTxDq: 07
N7.C1.D0.R0.S08: TxDq : plus1 = 1, minus1 = 0, PI = 10, DB = 1
N1.C1.D0.R0.S09: TxDq : plus1 = 1, minus1 = 0, PI = 05, DB = 1
N5.C2.D0.R1.S11: RdPtrOffsetTxDq: 07
N7.C1.D0.R0.S09: TxDqs: plus1 = 1, minus1 = 0, PI = 41, DB = 0
N1.C1.D0.R0.S10: TxDqs: plus1 = 1, minus1 = 0, PI = 22, DB = 0
N5.C2.D0.R1.S12: RdPtrOffsetTxDq: 07
N7.C1.D0.R0.S09: TxDq : plus1 = 1, minus1 = 0, PI = 10, DB = 1
N1.C1.D0.R0.S10: TxDq : plus1 = 1, minus1 = 0, PI = 51, DB = 1
N5.C2.D0.R1.S13: RdPtrOffsetTxDq: 06
N7.C1.D0.R0.S10: TxDqs: plus1 = 1, minus1 = 0, PI = 28, DB = 0
N1.C1.D0.R0.S11: TxDqs: plus1 = 1, minus1 = 0, PI = 11, DB = 1
N5.C2.D0.R1.S14: RdPtrOffsetTxDq: 07
N7.C1.D0.R0.S10: TxDq : plus1 = 1, minus1 = 0, PI = 57, DB = 1
N1.C1.D0.R0.S11: TxDq : plus1 = 1, minus1 = 0, PI = 44, DB = 0
N5.C2.D0.R1.S15: RdPtrOffsetTxDq: 07
N7.C1.D0.R0.S11: TxDqs: plus1 = 1, minus1 = 0, PI = 18, DB = 0
N1.C1.D0.R0.S12: TxDqs: plus1 = 1, minus1 = 0, PI = 59, DB = 1
N5.C2.D0.R1.S16: RdPtrOffsetTxDq: 07
N7.C1.D0.R0.S11: TxDq : plus1 = 1, minus1 = 0, PI = 50, DB = 1
N1.C1.D0.R0.S12: TxDq : plus1 = 1, minus1 = 0, PI = 27, DB = 0
N5.C2.D0.R1.S17: RdPtrOffsetTxDq: 06
N7.C1.D0.R0.S12: TxDqs: plus1 = 1, minus1 = 0, PI = 00, DB = 1
N1.C1.D0.R0.S13: TxDqs: plus1 = 1, minus1 = 0, PI = 27, DB = 0
N5.C2.D0.R1.S00: Total Delay in PI ticks: TxDQ = 963
N7.C1.D0.R0.S12: TxDq : plus1 = 1, minus1 = 0, PI = 31, DB = 0
N1.C1.D0.R0.S13: TxDq : plus1 = 1, minus1 = 0, PI = 58, DB = 1
N5.C2.D0.R1.S01: Total Delay in PI ticks: TxDQ = 948
N7.C1.D0.R0.S13: TxDqs: plus1 = 1, minus1 = 0, PI = 31, DB = 0
N1.C1.D0.R0.S14: TxDqs: plus1 = 1, minus1 = 0, PI = 40, DB = 0
N5.C2.D0.R1.S02: Total Delay in PI ticks: TxDQ = 939
N7.C1.D0.R0.S13: TxDq : plus1 = 1, minus1 = 0, PI = 62, DB = 1
N1.C1.D0.R0.S14: TxDq : plus1 = 1, minus1 = 0, PI = 05, DB = 1
N5.C2.D0.R1.S03: Total Delay in PI ticks: TxDQ = 922
N7.C1.D0.R0.S14: TxDqs: plus1 = 1, minus1 = 0, PI = 46, DB = 0
N1.C1.D0.R0.S15: TxDqs: plus1 = 1, minus1 = 0, PI = 52, DB = 1
N5.C2.D0.R1.S04: Total Delay in PI ticks: TxDQ = 880
N7.C1.D0.R0.S14: TxDq : plus1 = 1, minus1 = 0, PI = 11, DB = 1
N1.C1.D0.R0.S15: TxDq : plus1 = 1, minus1 = 0, PI = 21, DB = 0
N5.C2.D0.R1.S05: Total Delay in PI ticks: TxDQ = 908
N7.C1.D0.R0.S15: TxDqs: plus1 = 1, minus1 = 0, PI = 58, DB = 1
N1.C1.D0.R0.S16: TxDqs: plus1 = 1, minus1 = 0, PI = 07, DB = 1
N5.C2.D0.R1.S06: Total Delay in PI ticks: TxDQ = 908
N7.C1.D0.R0.S15: TxDq : plus1 = 1, minus1 = 0, PI = 26, DB = 0
N1.C1.D0.R0.S16: TxDq : plus1 = 1, minus1 = 0, PI = 37, DB = 0
N5.C2.D0.R1.S07: Total Delay in PI ticks: TxDQ = 930
N7.C1.D0.R0.S16: TxDqs: plus1 = 1, minus1 = 0, PI = 12, DB = 1
N1.C1.D0.R0.S17: TxDqs: plus1 = 1, minus1 = 0, PI = 38, DB = 0
N5.C2.D0.R1.S08: Total Delay in PI ticks: TxDQ = 894
N7.C1.D0.R0.S16: TxDq : plus1 = 1, minus1 = 0, PI = 43, DB = 0
N1.C1.D0.R0.S17: TxDq : plus1 = 1, minus1 = 0, PI = 04, DB = 1
N5.C2.D0.R1.S09: Total Delay in PI ticks: TxDQ = 962
N7.C1.D0.R0.S17: TxDqs: plus1 = 1, minus1 = 0, PI = 43, DB = 0
N1.C1.D0.R1.S00: TxDqs: plus1 = 1, minus1 = 0, PI = 39, DB = 0
N5.C2.D0.R1.S10: Total Delay in PI ticks: TxDQ = 947
N7.C1.D0.R0.S17: TxDq : plus1 = 1, minus1 = 0, PI = 10, DB = 1
N1.C1.D0.R1.S00: TxDq : plus1 = 1, minus1 = 0, PI = 06, DB = 1
N5.C2.D0.R1.S11: Total Delay in PI ticks: TxDQ = 940
N7.C1.D0.R1.S00: TxDqs: plus1 = 1, minus1 = 0, PI = 44, DB = 0
N1.C1.D0.R1.S01: TxDqs: plus1 = 1, minus1 = 0, PI = 22, DB = 0
N5.C2.D0.R1.S12: Total Delay in PI ticks: TxDQ = 924
N7.C1.D0.R1.S00: TxDq : plus1 = 1, minus1 = 0, PI = 11, DB = 1
N1.C1.D0.R1.S01: TxDq : plus1 = 1, minus1 = 0, PI = 52, DB = 1
N5.C2.D0.R1.S13: Total Delay in PI ticks: TxDQ = 880
N7.C1.D0.R1.S01: TxDqs: plus1 = 1, minus1 = 0, PI = 26, DB = 0
N1.C1.D0.R1.S02: TxDqs: plus1 = 1, minus1 = 0, PI = 11, DB = 1
N5.C2.D0.R1.S14: Total Delay in PI ticks: TxDQ = 907
N7.C1.D0.R1.S01: TxDq : plus1 = 1, minus1 = 0, PI = 57, DB = 1
N1.C1.D0.R1.S02: TxDq : plus1 = 1, minus1 = 0, PI = 43, DB = 0
N5.C2.D0.R1.S15: Total Delay in PI ticks: TxDQ = 909
N7.C1.D0.R1.S02: TxDqs: plus1 = 1, minus1 = 0, PI = 18, DB = 0
N1.C1.D0.R1.S03: TxDqs: plus1 = 1, minus1 = 0, PI = 59, DB = 1
N5.C2.D0.R1.S16: Total Delay in PI ticks: TxDQ = 931
N7.C1.D0.R1.S02: TxDq : plus1 = 1, minus1 = 0, PI = 49, DB = 1
N1.C1.D0.R1.S03: TxDq : plus1 = 1, minus1 = 0, PI = 27, DB = 0
N3: 
Get Tx Vref margins...
N5.C2.D0.R1.S17: Total Delay in PI ticks: TxDQ = 894
N7.C1.D0.R1.S03: TxDqs: plus1 = 1, minus1 = 0, PI = 00, DB = 1
N1.C1.D0.R1.S04: TxDqs: plus1 = 1, minus1 = 0, PI = 27, DB = 0
N3: GetMargins: Level = 1, group = 14, mode = 0, scope = 3
N5.C2: Calculating Optimimum DQ/DQS Values
N7.C1.D0.R1.S03: TxDq : plus1 = 1, minus1 = 0, PI = 30, DB = 0
N1.C1.D0.R1.S04: TxDq : plus1 = 1, minus1 = 0, PI = 57, DB = 1
START_DATA_TX_DQ
N7.C1.D0.R1.S04: TxDqs: plus1 = 1, minus1 = 0, PI = 32, DB = 0
N1.C1.D0.R1.S05: TxDqs: plus1 = 1, minus1 = 0, PI = 40, DB = 0
N5.C2.S00: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 009, RdPtrOffsetTxDqs = 009
N7.C1.D0.R1.S04: TxDq : plus1 = 1, minus1 = 0, PI = 63, DB = 1
N1.C1.D0.R1.S05: TxDq : plus1 = 1, minus1 = 0, PI = 05, DB = 1
N5.C2.S00: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 009, RdPtrOffsetTxDqs = 009
N7.C1.D0.R1.S05: TxDqs: plus1 = 1, minus1 = 0, PI = 45, DB = 0
N1.C1.D0.R1.S06: TxDqs: plus1 = 1, minus1 = 0, PI = 52, DB = 1
N5.C2.S01: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 009
N7.C1.D0.R1.S05: TxDq : plus1 = 1, minus1 = 0, PI = 13, DB = 1
N1.C1.D0.R1.S06: TxDq : plus1 = 1, minus1 = 0, PI = 20, DB = 0
N5.C2.S01: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 009
N7.C1.D0.R1.S06: TxDqs: plus1 = 1, minus1 = 0, PI = 59, DB = 1
N1.C1.D0.R1.S07: TxDqs: plus1 = 1, minus1 = 0, PI = 05, DB = 1
N5.C2.S02: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 009
N7.C1.D0.R1.S06: TxDq : plus1 = 1, minus1 = 0, PI = 27, DB = 0
N1.C1.D0.R1.S07: TxDq : plus1 = 1, minus1 = 0, PI = 37, DB = 0
N5.C2.S02: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 009
N7.C1.D0.R1.S07: TxDqs: plus1 = 1, minus1 = 0, PI = 13, DB = 1
N1.C1.D0.R1.S08: TxDqs: plus1 = 1, minus1 = 0, PI = 37, DB = 0
N5.C2.S03: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 008
N7.C1.D0.R1.S07: TxDq : plus1 = 1, minus1 = 0, PI = 42, DB = 0
N1.C1.D0.R1.S08: TxDq : plus1 = 1, minus1 = 0, PI = 05, DB = 1
N5.C2.S03: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 008
N7.C1.D0.R1.S08: TxDqs: plus1 = 1, minus1 = 0, PI = 45, DB = 0
N1.C1.D0.R1.S09: TxDqs: plus1 = 1, minus1 = 0, PI = 39, DB = 0
N5.C2.S04: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 007, RdPtrOffsetTxDqs = 008
N7.C1.D0.R1.S08: TxDq : plus1 = 1, minus1 = 0, PI = 10, DB = 1
N1.C1.D0.R1.S09: TxDq : plus1 = 1, minus1 = 0, PI = 05, DB = 1
N5.C2.S04: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 007, RdPtrOffsetTxDqs = 008
N7.C1.D0.R1.S09: TxDqs: plus1 = 1, minus1 = 0, PI = 41, DB = 0
N1.C1.D0.R1.S10: TxDqs: plus1 = 1, minus1 = 0, PI = 22, DB = 0
N5.C2.S05: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 008
N7.C1.D0.R1.S09: TxDq : plus1 = 1, minus1 = 0, PI = 10, DB = 1
N1.C1.D0.R1.S10: TxDq : plus1 = 1, minus1 = 0, PI = 51, DB = 1
N5.C2.S05: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 008
N7.C1.D0.R1.S10: TxDqs: plus1 = 1, minus1 = 0, PI = 28, DB = 0
N1.C1.D0.R1.S11: TxDqs: plus1 = 1, minus1 = 0, PI = 11, DB = 1
N5.C2.S06: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 008
N7.C1.D0.R1.S10: TxDq : plus1 = 1, minus1 = 0, PI = 57, DB = 1
N1.C1.D0.R1.S11: TxDq : plus1 = 1, minus1 = 0, PI = 44, DB = 0
N5.C2.S06: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 008
N7.C1.D0.R1.S11: TxDqs: plus1 = 1, minus1 = 0, PI = 18, DB = 0
N1.C1.D0.R1.S12: TxDqs: plus1 = 1, minus1 = 0, PI = 59, DB = 1
N5.C2.S07: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 009
N7.C1.D0.R1.S11: TxDq : plus1 = 1, minus1 = 0, PI = 50, DB = 1
N1.C1.D0.R1.S12: TxDq : plus1 = 1, minus1 = 0, PI = 27, DB = 0
N5.C2.S07: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 009
N7.C1.D0.R1.S12: TxDqs: plus1 = 1, minus1 = 0, PI = 00, DB = 1
N1.C1.D0.R1.S13: TxDqs: plus1 = 1, minus1 = 0, PI = 27, DB = 0
N5.C2.S08: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 007, RdPtrOffsetTxDqs = 008
N7.C1.D0.R1.S12: TxDq : plus1 = 1, minus1 = 0, PI = 31, DB = 0
N1.C1.D0.R1.S13: TxDq : plus1 = 1, minus1 = 0, PI = 58, DB = 1
N5.C2.S08: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 007, RdPtrOffsetTxDqs = 008
N7.C1.D0.R1.S13: TxDqs: plus1 = 1, minus1 = 0, PI = 31, DB = 0
N1.C1.D0.R1.S14: TxDqs: plus1 = 1, minus1 = 0, PI = 40, DB = 0
N5.C2.D0.R0.S00: TxDqs: plus1 = 1, minus1 = 0, PI = 36, DB = 0
N7.C1.D0.R1.S13: TxDq : plus1 = 1, minus1 = 0, PI = 62, DB = 1
N1.C1.D0.R1.S14: TxDq : plus1 = 1, minus1 = 0, PI = 05, DB = 1
N5.C2.D0.R0.S00: TxDq : plus1 = 1, minus1 = 0, PI = 03, DB = 1
N7.C1.D0.R1.S14: TxDqs: plus1 = 1, minus1 = 0, PI = 46, DB = 0
N1.C1.D0.R1.S15: TxDqs: plus1 = 1, minus1 = 0, PI = 52, DB = 1
N5.C2.D0.R0.S01: TxDqs: plus1 = 1, minus1 = 0, PI = 23, DB = 0
N7.C1.D0.R1.S14: TxDq : plus1 = 1, minus1 = 0, PI = 11, DB = 1
N1.C1.D0.R1.S15: TxDq : plus1 = 1, minus1 = 0, PI = 21, DB = 0
N5.C2.D0.R0.S01: TxDq : plus1 = 1, minus1 = 0, PI = 52, DB = 1
N7.C1.D0.R1.S15: TxDqs: plus1 = 1, minus1 = 0, PI = 58, DB = 1
N1.C1.D0.R1.S16: TxDqs: plus1 = 1, minus1 = 0, PI = 07, DB = 1
N5.C2.D0.R0.S02: TxDqs: plus1 = 1, minus1 = 0, PI = 11, DB = 1
N7.C1.D0.R1.S15: TxDq : plus1 = 1, minus1 = 0, PI = 26, DB = 0
N1.C1.D0.R1.S16: TxDq : plus1 = 1, minus1 = 0, PI = 37, DB = 0
N5.C2.D0.R0.S02: TxDq : plus1 = 1, minus1 = 0, PI = 44, DB = 0
N7.C1.D0.R1.S16: TxDqs: plus1 = 1, minus1 = 0, PI = 12, DB = 1
N1.C1.D0.R1.S17: TxDqs: plus1 = 1, minus1 = 0, PI = 38, DB = 0
N5.C2.D0.R0.S03: TxDqs: plus1 = 1, minus1 = 0, PI = 58, DB = 1
N7.C1.D0.R1.S16: TxDq : plus1 = 1, minus1 = 0, PI = 43, DB = 0
N1.C1.D0.R1.S17: TxDq : plus1 = 1, minus1 = 0, PI = 04, DB = 1
N5.C2.D0.R0.S03: TxDq : plus1 = 1, minus1 = 0, PI = 26, DB = 0
N7.C1.D0.R1.S17: TxDqs: plus1 = 1, minus1 = 0, PI = 43, DB = 0
END_DATA_TX_DQ
N5.C2.D0.R0.S04: TxDqs: plus1 = 1, minus1 = 0, PI = 16, DB = 0
N7.C1.D0.R1.S17: TxDq : plus1 = 1, minus1 = 0, PI = 10, DB = 1
N1.C2.D0.R0.S00: wrcmd2dqsstartlatency: 04
N5.C2.D0.R0.S04: TxDq : plus1 = 1, minus1 = 0, PI = 48, DB = 0
END_DATA_TX_DQ
N1.C2.D0.R0.S00: RdPtrOffsetTxDq: 06
N5.C2.D0.R0.S05: TxDqs: plus1 = 1, minus1 = 0, PI = 47, DB = 0
N7.C2.D0.R0.S00: wrcmd2dqsstartlatency: 04
N1.C2.D0.R0.S00: RdPtrOffsetTxDqs: 07
N5.C2.D0.R0.S05: TxDq : plus1 = 1, minus1 = 0, PI = 12, DB = 1
N7.C2.D0.R0.S00: RdPtrOffsetTxDq: 05
N1.C2.D0.R0.S00: PiTxDqs: 33
N5.C2.D0.R0.S06: TxDqs: plus1 = 1, minus1 = 0, PI = 46, DB = 0
N7.C2.D0.R0.S00: RdPtrOffsetTxDqs: 07
N1.C2.D0.R0.S01: wrcmd2dqsstartlatency: 04
N5.C2.D0.R0.S06: TxDq : plus1 = 1, minus1 = 0, PI = 12, DB = 1
N7.C2.D0.R0.S00: PiTxDqs: 29
N1.C2.D0.R0.S01: RdPtrOffsetTxDq: 05
N5.C2.D0.R0.S07: TxDqs: plus1 = 1, minus1 = 0, PI = 05, DB = 1
N7.C2.D0.R0.S01: wrcmd2dqsstartlatency: 04
N1.C2.D0.R0.S01: RdPtrOffsetTxDqs: 07
N5.C2.D0.R0.S07: TxDq : plus1 = 1, minus1 = 0, PI = 35, DB = 0
N7.C2.D0.R0.S01: RdPtrOffsetTxDq: 05
N1.C2.D0.R0.S01: PiTxDqs: 18
N5.C2.D0.R0.S08: TxDqs: plus1 = 1, minus1 = 0, PI = 33, DB = 0
N7.C2.D0.R0.S01: RdPtrOffsetTxDqs: 07
N1.C2.D0.R0.S02: wrcmd2dqsstartlatency: 04
N5.C2.D0.R0.S08: TxDq : plus1 = 1, minus1 = 0, PI = 62, DB = 1
N7.C2.D0.R0.S01: PiTxDqs: 15
N1.C2.D0.R0.S02: RdPtrOffsetTxDq: 05
N5.C2.D0.R0.S09: TxDqs: plus1 = 1, minus1 = 0, PI = 35, DB = 0
N7.C2.D0.R0.S02: wrcmd2dqsstartlatency: 04
N1.C2.D0.R0.S02: RdPtrOffsetTxDqs: 07
N5.C2.D0.R0.S09: TxDq : plus1 = 1, minus1 = 0, PI = 02, DB = 1
N7.C2.D0.R0.S02: RdPtrOffsetTxDq: 05
N1.C2.D0.R0.S02: PiTxDqs: 05
N5.C2.D0.R0.S10: TxDqs: plus1 = 1, minus1 = 0, PI = 23, DB = 0
N7.C2.D0.R0.S02: RdPtrOffsetTxDqs: 07
N1.C2.D0.R0.S03: wrcmd2dqsstartlatency: 04
N5.C2.D0.R0.S10: TxDq : plus1 = 1, minus1 = 0, PI = 52, DB = 1
N7.C2.D0.R0.S02: PiTxDqs: 04
N1.C2.D0.R0.S03: RdPtrOffsetTxDq: 05
N5.C2.D0.R0.S11: TxDqs: plus1 = 1, minus1 = 0, PI = 13, DB = 1
N7.C2.D0.R0.S03: wrcmd2dqsstartlatency: 04
N1.C2.D0.R0.S03: RdPtrOffsetTxDqs: 06
N5.C2.D0.R0.S11: TxDq : plus1 = 1, minus1 = 0, PI = 44, DB = 0
N7.C2.D0.R0.S03: RdPtrOffsetTxDq: 05
N1.C2.D0.R0.S03: PiTxDqs: 54
N5.C2.D0.R0.S12: TxDqs: plus1 = 1, minus1 = 0, PI = 60, DB = 1
N7.C2.D0.R0.S03: RdPtrOffsetTxDqs: 06
N1.C2.D0.R0.S04: wrcmd2dqsstartlatency: 04
N5.C2.D0.R0.S12: TxDq : plus1 = 1, minus1 = 0, PI = 27, DB = 0
N7.C2.D0.R0.S03: PiTxDqs: 51
N1.C2.D0.R0.S04: RdPtrOffsetTxDq: 04
N5.C2.D0.R0.S13: TxDqs: plus1 = 1, minus1 = 0, PI = 16, DB = 0
N7.C2.D0.R0.S04: wrcmd2dqsstartlatency: 04
N1.C2.D0.R0.S04: RdPtrOffsetTxDqs: 06
N5.C2.D0.R0.S13: TxDq : plus1 = 1, minus1 = 0, PI = 48, DB = 0
N7.C2.D0.R0.S04: RdPtrOffsetTxDq: 04
N1.C2.D0.R0.S04: PiTxDqs: 15
N5.C2.D0.R0.S14: TxDqs: plus1 = 1, minus1 = 0, PI = 47, DB = 0
N7.C2.D0.R0.S04: RdPtrOffsetTxDqs: 06
N1.C2.D0.R0.S05: wrcmd2dqsstartlatency: 04
N5.C2.D0.R0.S14: TxDq : plus1 = 1, minus1 = 0, PI = 11, DB = 1
N7.C2.D0.R0.S04: PiTxDqs: 08
N1.C2.D0.R0.S05: RdPtrOffsetTxDq: 05
N5.C2.D0.R0.S15: TxDqs: plus1 = 1, minus1 = 0, PI = 47, DB = 0
N7.C2.D0.R0.S05: wrcmd2dqsstartlatency: 04
N1.C2.D0.R0.S05: RdPtrOffsetTxDqs: 06
N5.C2.D0.R0.S15: TxDq : plus1 = 1, minus1 = 0, PI = 13, DB = 1
N7.C2.D0.R0.S05: RdPtrOffsetTxDq: 05
N1.C2.D0.R0.S05: PiTxDqs: 43
N5.C2.D0.R0.S16: TxDqs: plus1 = 1, minus1 = 0, PI = 04, DB = 1
N7.C2.D0.R0.S05: RdPtrOffsetTxDqs: 06
N1.C2.D0.R0.S06: wrcmd2dqsstartlatency: 04
N3: 
 Time to do RMT patterns 15  is 2 seconds 
N5.C2.D0.R0.S16: TxDq : plus1 = 1, minus1 = 0, PI = 34, DB = 0
N7.C2.D0.R0.S05: PiTxDqs: 39
N1.C2.D0.R0.S06: RdPtrOffsetTxDq: 05

            RxDqLeft RxDqRight RxVLow RxVHigh TxDqLeft TxDqRight TxVLow TxVHigh
--------------------------------------------------------------------------------
N3.C0.D0.R0:   -21       20       -48       48      -24     23      -29      27
N3.C0.D0.R1:   -20       20       -48       48      -24     23      -30      29
N3.C1.D0.R0:   -17       18       -30       48      -22     22      -26      26
N3.C1.D0.R1:   -17       17       -29       48      -23     23      -27      26
N3.C2.D0.R0:   -21       22       -48       48      -24     23      -28      27
N3.C2.D0.R1:   -21       21       -48       48      -23     23      -27      28
N3.C3.D0.R0:   -21       22       -29       48      -22     22      -23      25
N3.C3.D0.R1:   -21       22       -29       48      -23     23      -26      26
STOP_RMT_N3
N5.C2.D0.R0.S17: TxDqs: plus1 = 1, minus1 = 0, PI = 33, DB = 0
N7.C2.D0.R0.S06: wrcmd2dqsstartlatency: 04
N1.C2.D0.R0.S06: RdPtrOffsetTxDqs: 06
N3: GetAllRankMargins time            2722 ms
N5.C2.D0.R0.S17: TxDq : plus1 = 1, minus1 = 0, PI = 62, DB = 1
N7.C2.D0.R0.S06: RdPtrOffsetTxDq: 05
N1.C2.D0.R0.S06: PiTxDqs: 39
N3: 
Total DDR trainings latency = 92244 ms
N5.C2.D0.R1.S00: TxDqs: plus1 = 1, minus1 = 0, PI = 36, DB = 0
N7.C2.D0.R0.S06: RdPtrOffsetTxDqs: 06
N1.C2.D0.R0.S07: wrcmd2dqsstartlatency: 04
N2: PostDdrTraining
N5.C2.D0.R1.S00: TxDq : plus1 = 1, minus1 = 0, PI = 03, DB = 1
N7.C2.D0.R0.S06: PiTxDqs: 38
N1.C2.D0.R0.S07: RdPtrOffsetTxDq: 05
N3: PostDdrTraining
N5.C2.D0.R1.S01: TxDqs: plus1 = 1, minus1 = 0, PI = 23, DB = 0
N7.C2.D0.R0.S07: wrcmd2dqsstartlatency: 04
N1.C2.D0.R0.S07: RdPtrOffsetTxDqs: 06
N2.C0.D0: CheckRankPopLocal: dimmPresent: 1, numRanks = 2
N5.C2.D0.R1.S01: TxDq : plus1 = 1, minus1 = 0, PI = 52, DB = 1
N7.C2.D0.R0.S07: RdPtrOffsetTxDq: 05
N1.C2.D0.R0.S07: PiTxDqs: 63
N2.C0.D0.R0: CheckRankPopLocal: mapOut: 0, enabled = 1
N5.C2.D0.R1.S02: TxDqs: plus1 = 1, minus1 = 0, PI = 11, DB = 1
N7.C2.D0.R0.S07: RdPtrOffsetTxDqs: 06
N1.C2.D0.R0.S08: wrcmd2dqsstartlatency: 04
N2.C0.D0.R1: CheckRankPopLocal: mapOut: 0, enabled = 1
N5.C2.D0.R1.S02: TxDq : plus1 = 1, minus1 = 0, PI = 44, DB = 0
N7.C2.D0.R0.S07: PiTxDqs: 60
N1.C2.D0.R0.S08: RdPtrOffsetTxDq: 04
N2.C0.D1: CheckRankPopLocal: dimmPresent: 1, numRanks = 2
N5.C2.D0.R1.S03: TxDqs: plus1 = 1, minus1 = 0, PI = 58, DB = 1
N7.C2.D0.R0.S08: wrcmd2dqsstartlatency: 04
N1.C2.D0.R0.S08: RdPtrOffsetTxDqs: 06
N2.C0.D1.R0: CheckRankPopLocal: mapOut: 0, enabled = 1
N5.C2.D0.R1.S03: TxDq : plus1 = 1, minus1 = 0, PI = 26, DB = 0
N7.C2.D0.R0.S08: RdPtrOffsetTxDq: 04
N1.C2.D0.R0.S08: PiTxDqs: 29
N2.C0.D1.R1: CheckRankPopLocal: mapOut: 0, enabled = 1
N5.C2.D0.R1.S04: TxDqs: plus1 = 1, minus1 = 0, PI = 16, DB = 0
N7.C2.D0.R0.S08: RdPtrOffsetTxDqs: 06
N1.C2.D0.R0.S09: wrcmd2dqsstartlatency: 04
N2.C0.D2: CheckRankPopLocal: dimmPresent: 0, numRanks = 0
N5.C2.D0.R1.S04: TxDq : plus1 = 1, minus1 = 0, PI = 48, DB = 0
N7.C2.D0.R0.S08: PiTxDqs: 24
N1.C2.D0.R0.S09: RdPtrOffsetTxDq: 05
N2.C0.D0: CheckRankPopLocal: amap: 0x00000000
N5.C2.D0.R1.S05: TxDqs: plus1 = 1, minus1 = 0, PI = 47, DB = 0
N7.C2.D0.R0.S09: wrcmd2dqsstartlatency: 04
N1.C2.D0.R0.S09: RdPtrOffsetTxDqs: 07
N2.C0.D1: CheckRankPopLocal: amap: 0x00000000
N5.C2.D0.R1.S05: TxDq : plus1 = 1, minus1 = 0, PI = 12, DB = 1
N7.C2.D0.R0.S09: RdPtrOffsetTxDq: 05
N1.C2.D0.R0.S09: PiTxDqs: 33
N2.C0.D2: CheckRankPopLocal: amap: 0x00000000
N5.C2.D0.R1.S06: TxDqs: plus1 = 1, minus1 = 0, PI = 46, DB = 0
N7.C2.D0.R0.S09: RdPtrOffsetTxDqs: 07
N1.C2.D0.R0.S10: wrcmd2dqsstartlatency: 04
N2.C1.D0: CheckRankPopLocal: dimmPresent: 1, numRanks = 2
N5.C2.D0.R1.S06: TxDq : plus1 = 1, minus1 = 0, PI = 12, DB = 1
N7.C2.D0.R0.S09: PiTxDqs: 30
N1.C2.D0.R0.S10: RdPtrOffsetTxDq: 05
N2.C1.D0.R0: CheckRankPopLocal: mapOut: 0, enabled = 1
N5.C2.D0.R1.S07: TxDqs: plus1 = 1, minus1 = 0, PI = 05, DB = 1
N7.C2.D0.R0.S10: wrcmd2dqsstartlatency: 04
N1.C2.D0.R0.S10: RdPtrOffsetTxDqs: 07
N2.C1.D0.R1: CheckRankPopLocal: mapOut: 0, enabled = 1
N5.C2.D0.R1.S07: TxDq : plus1 = 1, minus1 = 0, PI = 35, DB = 0
N7.C2.D0.R0.S10: RdPtrOffsetTxDq: 05
N1.C2.D0.R0.S10: PiTxDqs: 20
N2.C1.D1: CheckRankPopLocal: dimmPresent: 1, numRanks = 2
N5.C2.D0.R1.S08: TxDqs: plus1 = 1, minus1 = 0, PI = 33, DB = 0
N7.C2.D0.R0.S10: RdPtrOffsetTxDqs: 07
N1.C2.D0.R0.S11: wrcmd2dqsstartlatency: 04
N2.C1.D1.R0: CheckRankPopLocal: mapOut: 0, enabled = 1
N5.C2.D0.R1.S08: TxDq : plus1 = 1, minus1 = 0, PI = 62, DB = 1
N7.C2.D0.R0.S10: PiTxDqs: 15
N1.C2.D0.R0.S11: RdPtrOffsetTxDq: 05
N2.C1.D1.R1: CheckRankPopLocal: mapOut: 0, enabled = 1
N5.C2.D0.R1.S09: TxDqs: plus1 = 1, minus1 = 0, PI = 35, DB = 0
N7.C2.D0.R0.S11: wrcmd2dqsstartlatency: 04
N1.C2.D0.R0.S11: RdPtrOffsetTxDqs: 07
N2.C1.D2: CheckRankPopLocal: dimmPresent: 0, numRanks = 0
N5.C2.D0.R1.S09: TxDq : plus1 = 1, minus1 = 0, PI = 02, DB = 1
N7.C2.D0.R0.S11: RdPtrOffsetTxDq: 05
N1.C2.D0.R0.S11: PiTxDqs: 05
N2.C1.D0: CheckRankPopLocal: amap: 0x00000000
N5.C2.D0.R1.S10: TxDqs: plus1 = 1, minus1 = 0, PI = 23, DB = 0
N7.C2.D0.R0.S11: RdPtrOffsetTxDqs: 07
N1.C2.D0.R0.S12: wrcmd2dqsstartlatency: 04
N2.C1.D1: CheckRankPopLocal: amap: 0x00000000
N5.C2.D0.R1.S10: TxDq : plus1 = 1, minus1 = 0, PI = 52, DB = 1
N7.C2.D0.R0.S11: PiTxDqs: 06
N1.C2.D0.R0.S12: RdPtrOffsetTxDq: 05
N2.C1.D2: CheckRankPopLocal: amap: 0x00000000
N5.C2.D0.R1.S11: TxDqs: plus1 = 1, minus1 = 0, PI = 13, DB = 1
N7.C2.D0.R0.S12: wrcmd2dqsstartlatency: 04
N1.C2.D0.R0.S12: RdPtrOffsetTxDqs: 06
N2.C2.D0: CheckRankPopLocal: dimmPresent: 1, numRanks = 2
N5.C2.D0.R1.S11: TxDq : plus1 = 1, minus1 = 0, PI = 44, DB = 0
N7.C2.D0.R0.S12: RdPtrOffsetTxDq: 05
N1.C2.D0.R0.S12: PiTxDqs: 54
N2.C2.D0.R0: CheckRankPopLocal: mapOut: 0, enabled = 1
N5.C2.D0.R1.S12: TxDqs: plus1 = 1, minus1 = 0, PI = 60, DB = 1
N7.C2.D0.R0.S12: RdPtrOffsetTxDqs: 06
N1.C2.D0.R0.S13: wrcmd2dqsstartlatency: 04
N2.C2.D0.R1: CheckRankPopLocal: mapOut: 0, enabled = 1
N5.C2.D0.R1.S12: TxDq : plus1 = 1, minus1 = 0, PI = 27, DB = 0
N7.C2.D0.R0.S12: PiTxDqs: 51
N1.C2.D0.R0.S13: RdPtrOffsetTxDq: 04
N2.C2.D1: CheckRankPopLocal: dimmPresent: 1, numRanks = 2
N5.C2.D0.R1.S13: TxDqs: plus1 = 1, minus1 = 0, PI = 16, DB = 0
N7.C2.D0.R0.S13: wrcmd2dqsstartlatency: 04
N1.C2.D0.R0.S13: RdPtrOffsetTxDqs: 06
N2.C2.D1.R0: CheckRankPopLocal: mapOut: 0, enabled = 1
N5.C2.D0.R1.S13: TxDq : plus1 = 1, minus1 = 0, PI = 48, DB = 0
N7.C2.D0.R0.S13: RdPtrOffsetTxDq: 04
N1.C2.D0.R0.S13: PiTxDqs: 14
N2.C2.D1.R1: CheckRankPopLocal: mapOut: 0, enabled = 1
N5.C2.D0.R1.S14: TxDqs: plus1 = 1, minus1 = 0, PI = 47, DB = 0
N7.C2.D0.R0.S13: RdPtrOffsetTxDqs: 06
N1.C2.D0.R0.S14: wrcmd2dqsstartlatency: 04
N2.C2.D2: CheckRankPopLocal: dimmPresent: 0, numRanks = 0
N5.C2.D0.R1.S14: TxDq : plus1 = 1, minus1 = 0, PI = 11, DB = 1
N7.C2.D0.R0.S13: PiTxDqs: 08
N1.C2.D0.R0.S14: RdPtrOffsetTxDq: 05
N2.C2.D0: CheckRankPopLocal: amap: 0x00000000
N5.C2.D0.R1.S15: TxDqs: plus1 = 1, minus1 = 0, PI = 47, DB = 0
N7.C2.D0.R0.S14: wrcmd2dqsstartlatency: 04
N1.C2.D0.R0.S14: RdPtrOffsetTxDqs: 06
N2.C2.D1: CheckRankPopLocal: amap: 0x00000000
N5.C2.D0.R1.S15: TxDq : plus1 = 1, minus1 = 0, PI = 13, DB = 1
N7.C2.D0.R0.S14: RdPtrOffsetTxDq: 05
N1.C2.D0.R0.S14: PiTxDqs: 41
N2.C2.D2: CheckRankPopLocal: amap: 0x00000000
N5.C2.D0.R1.S16: TxDqs: plus1 = 1, minus1 = 0, PI = 04, DB = 1
N7.C2.D0.R0.S14: RdPtrOffsetTxDqs: 06
N1.C2.D0.R0.S15: wrcmd2dqsstartlatency: 04
N2.C3.D0: CheckRankPopLocal: dimmPresent: 1, numRanks = 2
N5.C2.D0.R1.S16: TxDq : plus1 = 1, minus1 = 0, PI = 34, DB = 0
N7.C2.D0.R0.S14: PiTxDqs: 37
N1.C2.D0.R0.S15: RdPtrOffsetTxDq: 05
N2.C3.D0.R0: CheckRankPopLocal: mapOut: 0, enabled = 1
N5.C2.D0.R1.S17: TxDqs: plus1 = 1, minus1 = 0, PI = 33, DB = 0
N7.C2.D0.R0.S15: wrcmd2dqsstartlatency: 04
N1.C2.D0.R0.S15: RdPtrOffsetTxDqs: 06
N2.C3.D0.R1: CheckRankPopLocal: mapOut: 0, enabled = 1
N5.C2.D0.R1.S17: TxDq : plus1 = 1, minus1 = 0, PI = 62, DB = 1
N7.C2.D0.R0.S15: RdPtrOffsetTxDq: 05
N1.C2.D0.R0.S15: PiTxDqs: 41
N2.C3.D1: CheckRankPopLocal: dimmPresent: 1, numRanks = 2
END_DATA_TX_DQ
N7.C2.D0.R0.S15: RdPtrOffsetTxDqs: 06
N1.C2.D0.R0.S16: wrcmd2dqsstartlatency: 04
N2.C3.D1.R0: CheckRankPopLocal: mapOut: 0, enabled = 1
N5.C3.D0.R0.S00: wrcmd2dqsstartlatency: 04
N7.C2.D0.R0.S15: PiTxDqs: 38
N1.C2.D0.R0.S16: RdPtrOffsetTxDq: 05
N2.C3.D1.R1: CheckRankPopLocal: mapOut: 0, enabled = 1
N5.C3.D0.R0.S00: RdPtrOffsetTxDq: 06
N7.C2.D0.R0.S16: wrcmd2dqsstartlatency: 04
N1.C2.D0.R0.S16: RdPtrOffsetTxDqs: 06
N2.C3.D2: CheckRankPopLocal: dimmPresent: 0, numRanks = 0
N5.C3.D0.R0.S00: RdPtrOffsetTxDqs: 07
N7.C2.D0.R0.S16: RdPtrOffsetTxDq: 05
N1.C2.D0.R0.S16: PiTxDqs: 63
N2.C3.D0: CheckRankPopLocal: amap: 0x00000000
N5.C3.D0.R0.S00: PiTxDqs: 43
N7.C2.D0.R0.S16: RdPtrOffsetTxDqs: 06
N1.C2.D0.R0.S17: wrcmd2dqsstartlatency: 04
N2.C3.D1: CheckRankPopLocal: amap: 0x00000000
N5.C3.D0.R0.S01: wrcmd2dqsstartlatency: 04
N7.C2.D0.R0.S16: PiTxDqs: 58
N1.C2.D0.R0.S17: RdPtrOffsetTxDq: 04
N2.C3.D2: CheckRankPopLocal: amap: 0x00000000
N5.C3.D0.R0.S01: RdPtrOffsetTxDq: 05
N7.C2.D0.R0.S17: wrcmd2dqsstartlatency: 04
N1.C2.D0.R0.S17: RdPtrOffsetTxDqs: 06
N2.C0: AdjustTotalRoundTripTime
N5.C3.D0.R0.S01: RdPtrOffsetTxDqs: 07
N7.C2.D0.R0.S17: RdPtrOffsetTxDq: 04
N1.C2.D0.R0.S17: PiTxDqs: 30
N2.C0: AdjustTotalRoundTripTime: worstRank = 1
N5.C3.D0.R0.S01: PiTxDqs: 27
N7.C2.D0.R0.S17: RdPtrOffsetTxDqs: 06
N1.C2.D0.R0.S00: RdPtrOffsetTxDq: 07
N2.C0: AdjustTotalRoundTripTime: worstRank dimm = 0, rank = 1
N5.C3.D0.R0.S02: wrcmd2dqsstartlatency: 04
N7.C2.D0.R0.S17: PiTxDqs: 24
N1.C2.D0.R0.S01: RdPtrOffsetTxDq: 06
N2.C1: AdjustTotalRoundTripTime: worstRank dimm = 0, rank = 1
N5.C3.D0.R0.S02: RdPtrOffsetTxDq: 05
N7.C2.D0.R0.S00: RdPtrOffsetTxDq: 06
N1.C2.D0.R0.S02: RdPtrOffsetTxDq: 06
N2.C0: AdjustTotalRoundTripTime: ddrChMask = 0x3
N5.C3.D0.R0.S02: RdPtrOffsetTxDqs: 07
N7.C2.D0.R0.S01: RdPtrOffsetTxDq: 06
N1.C2.D0.R0.S03: RdPtrOffsetTxDq: 06
N5.C3.D0.R0.S02: PiTxDqs: 14
N7.C2.D0.R0.S02: RdPtrOffsetTxDq: 06
N1.C2.D0.R0.S04: RdPtrOffsetTxDq: 05
N2.C0: RdCmd2DataValidLatency = 20, (dlyFrmS = 14, clEff = 10, earlyCas = 0, selNTiming = 0)
N5.C3.D0.R0.S03: wrcmd2dqsstartlatency: 04
N7.C2.D0.R0.S03: RdPtrOffsetTxDq: 06
N1.C2.D0.R0.S05: RdPtrOffsetTxDq: 06
N5.C3.D0.R0.S03: RdPtrOffsetTxDq: 05
N7.C2.D0.R0.S04: RdPtrOffsetTxDq: 05
N1.C2.D0.R0.S06: RdPtrOffsetTxDq: 06
N5.C3.D0.R0.S03: RdPtrOffsetTxDqs: 06
N7.C2.D0.R0.S05: RdPtrOffsetTxDq: 06
N1.C2.D0.R0.S07: RdPtrOffsetTxDq: 06
N5.C3.D0.R0.S03: PiTxDqs: 63
N7.C2.D0.R0.S06: RdPtrOffsetTxDq: 06
N1.C2.D0.R0.S08: RdPtrOffsetTxDq: 05
N5.C3.D0.R0.S04: wrcmd2dqsstartlatency: 04
N7.C2.D0.R0.S07: RdPtrOffsetTxDq: 06
N1.C2.D0.R0.S09: RdPtrOffsetTxDq: 06
N5.C3.D0.R0.S04: RdPtrOffsetTxDq: 04
N7.C2.D0.R0.S08: RdPtrOffsetTxDq: 05
N1.C2.D0.R0.S10: RdPtrOffsetTxDq: 06
N5.C3.D0.R0.S04: RdPtrOffsetTxDqs: 06
N7.C2.D0.R0.S09: RdPtrOffsetTxDq: 06
N1.C2.D0.R0.S11: RdPtrOffsetTxDq: 06
N5.C3.D0.R0.S04: PiTxDqs: 26
N7.C2.D0.R0.S10: RdPtrOffsetTxDq: 06
N1.C2.D0.R0.S12: RdPtrOffsetTxDq: 06
N5.C3.D0.R0.S05: wrcmd2dqsstartlatency: 04
N7.C2.D0.R0.S11: RdPtrOffsetTxDq: 06
N1.C2.D0.R0.S13: RdPtrOffsetTxDq: 05
N5.C3.D0.R0.S05: RdPtrOffsetTxDq: 05
N7.C2.D0.R0.S12: RdPtrOffsetTxDq: 06
N1.C2.D0.R0.S14: RdPtrOffsetTxDq: 06
N5.C3.D0.R0.S05: RdPtrOffsetTxDqs: 06
N7.C2.D0.R0.S13: RdPtrOffsetTxDq: 05
N1.C2.D0.R0.S15: RdPtrOffsetTxDq: 06
N5.C3.D0.R0.S05: PiTxDqs: 42
N7.C2.D0.R0.S14: RdPtrOffsetTxDq: 06
N1.C2.D0.R0.S16: RdPtrOffsetTxDq: 06
N5.C3.D0.R0.S06: wrcmd2dqsstartlatency: 04
N7.C2.D0.R0.S15: RdPtrOffsetTxDq: 06
N1.C2.D0.R0.S17: RdPtrOffsetTxDq: 05
N5.C3.D0.R0.S06: RdPtrOffsetTxDq: 05
N7.C2.D0.R0.S16: RdPtrOffsetTxDq: 06
N1.C2.D0.R0.S00: RdPtrOffsetTxDq: 08
N2.C1: RdCmd2DataValidLatency = 20, (dlyFrmS = 14, clEff = 10, earlyCas = 0, selNTiming = 0)
N5.C3.D0.R0.S06: RdPtrOffsetTxDqs: 06
N7.C2.D0.R0.S17: RdPtrOffsetTxDq: 05
N1.C2.D0.R0.S01: RdPtrOffsetTxDq: 07
N5.C3.D0.R0.S06: PiTxDqs: 56
N7.C2.D0.R0.S00: RdPtrOffsetTxDq: 07
N1.C2.D0.R0.S02: RdPtrOffsetTxDq: 07
N5.C3.D0.R0.S07: wrcmd2dqsstartlatency: 04
N7.C2.D0.R0.S01: RdPtrOffsetTxDq: 07
N1.C2.D0.R0.S03: RdPtrOffsetTxDq: 07
N5.C3.D0.R0.S07: RdPtrOffsetTxDq: 05
N7.C2.D0.R0.S02: RdPtrOffsetTxDq: 07
N1.C2.D0.R0.S04: RdPtrOffsetTxDq: 06
N5.C3.D0.R0.S07: RdPtrOffsetTxDqs: 07
N7.C2.D0.R0.S03: RdPtrOffsetTxDq: 07
N1.C2.D0.R0.S05: RdPtrOffsetTxDq: 07
N5.C3.D0.R0.S07: PiTxDqs: 09
N7.C2.D0.R0.S04: RdPtrOffsetTxDq: 06
N1.C2.D0.R0.S06: RdPtrOffsetTxDq: 07
N5.C3.D0.R0.S08: wrcmd2dqsstartlatency: 04
N7.C2.D0.R0.S05: RdPtrOffsetTxDq: 07
N1.C2.D0.R0.S07: RdPtrOffsetTxDq: 07
N5.C3.D0.R0.S08: RdPtrOffsetTxDq: 05
N7.C2.D0.R0.S06: RdPtrOffsetTxDq: 07
N1.C2.D0.R0.S08: RdPtrOffsetTxDq: 06
N5.C3.D0.R0.S08: RdPtrOffsetTxDqs: 06
N7.C2.D0.R0.S07: RdPtrOffsetTxDq: 07
N1.C2.D0.R0.S09: RdPtrOffsetTxDq: 07
N5.C3.D0.R0.S08: PiTxDqs: 44
N7.C2.D0.R0.S08: RdPtrOffsetTxDq: 06
N1.C2.D0.R0.S10: RdPtrOffsetTxDq: 07
N5.C3.D0.R0.S09: wrcmd2dqsstartlatency: 04
N7.C2.D0.R0.S09: RdPtrOffsetTxDq: 07
N1.C2.D0.R0.S11: RdPtrOffsetTxDq: 07
N5.C3.D0.R0.S09: RdPtrOffsetTxDq: 06
N7.C2.D0.R0.S10: RdPtrOffsetTxDq: 07
N1.C2.D0.R0.S12: RdPtrOffsetTxDq: 07
N5.C3.D0.R0.S09: RdPtrOffsetTxDqs: 07
N7.C2.D0.R0.S11: RdPtrOffsetTxDq: 07
N1.C2.D0.R0.S13: RdPtrOffsetTxDq: 06
N5.C3.D0.R0.S09: PiTxDqs: 43
N7.C2.D0.R0.S12: RdPtrOffsetTxDq: 07
N1.C2.D0.R0.S14: RdPtrOffsetTxDq: 07
N5.C3.D0.R0.S10: wrcmd2dqsstartlatency: 04
N7.C2.D0.R0.S13: RdPtrOffsetTxDq: 06
N1.C2.D0.R0.S15: RdPtrOffsetTxDq: 07
N5.C3.D0.R0.S10: RdPtrOffsetTxDq: 05
N7.C2.D0.R0.S14: RdPtrOffsetTxDq: 07
N1.C2.D0.R0.S16: RdPtrOffsetTxDq: 07
N5.C3.D0.R0.S10: RdPtrOffsetTxDqs: 07
N7.C2.D0.R0.S15: RdPtrOffsetTxDq: 07
N1.C2.D0.R0.S17: RdPtrOffsetTxDq: 06
N2.C0: RdCmd2DataValidLatency = 19, (dlyFrmS = 13, clEff = 10, earlyCas = 0, selNTiming = 0)
N5.C3.D0.R0.S10: PiTxDqs: 29
N7.C2.D0.R0.S16: RdPtrOffsetTxDq: 07
N1.C2.D0.R0.S00: Total Delay in PI ticks: TxDQ = 960
N5.C3.D0.R0.S11: wrcmd2dqsstartlatency: 04
N7.C2.D0.R0.S17: RdPtrOffsetTxDq: 06
N1.C2.D0.R0.S01: Total Delay in PI ticks: TxDQ = 943
N5.C3.D0.R0.S11: RdPtrOffsetTxDq: 05
N7.C2.D0.R0.S00: Total Delay in PI ticks: TxDQ = 956
N1.C2.D0.R0.S02: Total Delay in PI ticks: TxDQ = 932
N5.C3.D0.R0.S11: RdPtrOffsetTxDqs: 07
N7.C2.D0.R0.S01: Total Delay in PI ticks: TxDQ = 941
N1.C2.D0.R0.S03: Total Delay in PI ticks: TxDQ = 915
N5.C3.D0.R0.S11: PiTxDqs: 15
N7.C2.D0.R0.S02: Total Delay in PI ticks: TxDQ = 930
N1.C2.D0.R0.S04: Total Delay in PI ticks: TxDQ = 880
N5.C3.D0.R0.S12: wrcmd2dqsstartlatency: 04
N7.C2.D0.R0.S03: Total Delay in PI ticks: TxDQ = 912
N1.C2.D0.R0.S05: Total Delay in PI ticks: TxDQ = 904
N5.C3.D0.R0.S12: RdPtrOffsetTxDq: 05
N7.C2.D0.R0.S04: Total Delay in PI ticks: TxDQ = 872
N1.C2.D0.R0.S06: Total Delay in PI ticks: TxDQ = 904
N5.C3.D0.R0.S12: RdPtrOffsetTxDqs: 06
N7.C2.D0.R0.S05: Total Delay in PI ticks: TxDQ = 900
N1.C2.D0.R0.S07: Total Delay in PI ticks: TxDQ = 925
N5.C3.D0.R0.S12: PiTxDqs: 63
N7.C2.D0.R0.S06: Total Delay in PI ticks: TxDQ = 901
N1.C2.D0.R0.S08: Total Delay in PI ticks: TxDQ = 889
N5.C3.D0.R0.S13: wrcmd2dqsstartlatency: 04
N7.C2.D0.R0.S07: Total Delay in PI ticks: TxDQ = 923
N1.C2.D0.R0.S09: Total Delay in PI ticks: TxDQ = 958
N5.C3.D0.R0.S13: RdPtrOffsetTxDq: 04
N7.C2.D0.R0.S08: Total Delay in PI ticks: TxDQ = 886
N1.C2.D0.R0.S10: Total Delay in PI ticks: TxDQ = 946
N2.C1: RdCmd2DataValidLatency = 19, (dlyFrmS = 13, clEff = 10, earlyCas = 0, selNTiming = 0)
N5.C3.D0.R0.S13: RdPtrOffsetTxDqs: 06
N7.C2.D0.R0.S09: Total Delay in PI ticks: TxDQ = 955
N1.C2.D0.R0.S11: Total Delay in PI ticks: TxDQ = 931
N5.C3.D0.R0.S13: PiTxDqs: 28
N7.C2.D0.R0.S10: Total Delay in PI ticks: TxDQ = 940
N1.C2.D0.R0.S12: Total Delay in PI ticks: TxDQ = 917
N5.C3.D0.R0.S14: wrcmd2dqsstartlatency: 04
N7.C2.D0.R0.S11: Total Delay in PI ticks: TxDQ = 932
N1.C2.D0.R0.S13: Total Delay in PI ticks: TxDQ = 877
N5.C3.D0.R0.S14: RdPtrOffsetTxDq: 05
N7.C2.D0.R0.S12: Total Delay in PI ticks: TxDQ = 912
N1.C2.D0.R0.S14: Total Delay in PI ticks: TxDQ = 904
N5.C3.D0.R0.S14: RdPtrOffsetTxDqs: 06
N7.C2.D0.R0.S13: Total Delay in PI ticks: TxDQ = 872
N1.C2.D0.R0.S15: Total Delay in PI ticks: TxDQ = 905
N5.C3.D0.R0.S14: PiTxDqs: 42
N7.C2.D0.R0.S14: Total Delay in PI ticks: TxDQ = 900
N1.C2.D0.R0.S16: Total Delay in PI ticks: TxDQ = 925
N5.C3.D0.R0.S15: wrcmd2dqsstartlatency: 04
N7.C2.D0.R0.S15: Total Delay in PI ticks: TxDQ = 901
N1.C2.D0.R0.S17: Total Delay in PI ticks: TxDQ = 892
N5.C3.D0.R0.S15: RdPtrOffsetTxDq: 05
N7.C2.D0.R0.S16: Total Delay in PI ticks: TxDQ = 921
N1.C2.D0.R1.S00: wrcmd2dqsstartlatency: 04
N5.C3.D0.R0.S15: RdPtrOffsetTxDqs: 06
N7.C2.D0.R0.S17: Total Delay in PI ticks: TxDQ = 885
N1.C2.D0.R1.S00: RdPtrOffsetTxDq: 06
N5.C3.D0.R0.S15: PiTxDqs: 57
N7.C2.D0.R1.S00: wrcmd2dqsstartlatency: 04
N1.C2.D0.R1.S00: RdPtrOffsetTxDqs: 07
N5.C3.D0.R0.S16: wrcmd2dqsstartlatency: 04
N7.C2.D0.R1.S00: RdPtrOffsetTxDq: 05
N1.C2.D0.R1.S00: PiTxDqs: 32
N5.C3.D0.R0.S16: RdPtrOffsetTxDq: 05
N7.C2.D0.R1.S00: RdPtrOffsetTxDqs: 07
N1.C2.D0.R1.S01: wrcmd2dqsstartlatency: 04
N5.C3.D0.R0.S16: RdPtrOffsetTxDqs: 07
N7.C2.D0.R1.S00: PiTxDqs: 31
N1.C2.D0.R1.S01: RdPtrOffsetTxDq: 05
N5.C3.D0.R0.S16: PiTxDqs: 09
N7.C2.D0.R1.S01: wrcmd2dqsstartlatency: 04
N1.C2.D0.R1.S01: RdPtrOffsetTxDqs: 07
N2.C0: RdCmd2DataValidLatency = 18, (dlyFrmS = 12, clEff = 10, earlyCas = 0, selNTiming = 0)
N5.C3.D0.R0.S17: wrcmd2dqsstartlatency: 04
N7.C2.D0.R1.S01: RdPtrOffsetTxDq: 05
N1.C2.D0.R1.S01: PiTxDqs: 17
N5.C3.D0.R0.S17: RdPtrOffsetTxDq: 05
N7.C2.D0.R1.S01: RdPtrOffsetTxDqs: 07
N1.C2.D0.R1.S02: wrcmd2dqsstartlatency: 04
N5.C3.D0.R0.S17: RdPtrOffsetTxDqs: 06
N7.C2.D0.R1.S01: PiTxDqs: 14
N1.C2.D0.R1.S02: RdPtrOffsetTxDq: 05
N5.C3.D0.R0.S17: PiTxDqs: 44
N7.C2.D0.R1.S02: wrcmd2dqsstartlatency: 04
N1.C2.D0.R1.S02: RdPtrOffsetTxDqs: 07
N5.C3.D0.R0.S00: RdPtrOffsetTxDq: 07
N7.C2.D0.R1.S02: RdPtrOffsetTxDq: 05
N1.C2.D0.R1.S02: PiTxDqs: 04
N5.C3.D0.R0.S01: RdPtrOffsetTxDq: 06
N7.C2.D0.R1.S02: RdPtrOffsetTxDqs: 07
N1.C2.D0.R1.S03: wrcmd2dqsstartlatency: 04
N5.C3.D0.R0.S02: RdPtrOffsetTxDq: 06
N7.C2.D0.R1.S02: PiTxDqs: 02
N1.C2.D0.R1.S03: RdPtrOffsetTxDq: 05
N5.C3.D0.R0.S03: RdPtrOffsetTxDq: 06
N7.C2.D0.R1.S03: wrcmd2dqsstartlatency: 04
N1.C2.D0.R1.S03: RdPtrOffsetTxDqs: 06
N5.C3.D0.R0.S04: RdPtrOffsetTxDq: 05
N7.C2.D0.R1.S03: RdPtrOffsetTxDq: 05
N1.C2.D0.R1.S03: PiTxDqs: 53
N5.C3.D0.R0.S05: RdPtrOffsetTxDq: 06
N7.C2.D0.R1.S03: RdPtrOffsetTxDqs: 06
N1.C2.D0.R1.S04: wrcmd2dqsstartlatency: 04
N5.C3.D0.R0.S06: RdPtrOffsetTxDq: 06
N7.C2.D0.R1.S03: PiTxDqs: 49
N1.C2.D0.R1.S04: RdPtrOffsetTxDq: 04
N5.C3.D0.R0.S07: RdPtrOffsetTxDq: 06
N7.C2.D0.R1.S04: wrcmd2dqsstartlatency: 04
N1.C2.D0.R1.S04: RdPtrOffsetTxDqs: 06
N5.C3.D0.R0.S08: RdPtrOffsetTxDq: 06
N7.C2.D0.R1.S04: RdPtrOffsetTxDq: 04
N1.C2.D0.R1.S04: PiTxDqs: 14
N5.C3.D0.R0.S09: RdPtrOffsetTxDq: 07
N7.C2.D0.R1.S04: RdPtrOffsetTxDqs: 06
N1.C2.D0.R1.S05: wrcmd2dqsstartlatency: 04
N2.C1: RdCmd2DataValidLatency = 18, (dlyFrmS = 12, clEff = 10, earlyCas = 0, selNTiming = 0)
N5.C3.D0.R0.S10: RdPtrOffsetTxDq: 06
N7.C2.D0.R1.S04: PiTxDqs: 09
N1.C2.D0.R1.S05: RdPtrOffsetTxDq: 05
N5.C3.D0.R0.S11: RdPtrOffsetTxDq: 06
N7.C2.D0.R1.S05: wrcmd2dqsstartlatency: 04
N1.C2.D0.R1.S05: RdPtrOffsetTxDqs: 06
N5.C3.D0.R0.S12: RdPtrOffsetTxDq: 06
N7.C2.D0.R1.S05: RdPtrOffsetTxDq: 05
N1.C2.D0.R1.S05: PiTxDqs: 43
N5.C3.D0.R0.S13: RdPtrOffsetTxDq: 05
N7.C2.D0.R1.S05: RdPtrOffsetTxDqs: 06
N1.C2.D0.R1.S06: wrcmd2dqsstartlatency: 04
N5.C3.D0.R0.S14: RdPtrOffsetTxDq: 06
N7.C2.D0.R1.S05: PiTxDqs: 38
N1.C2.D0.R1.S06: RdPtrOffsetTxDq: 05
N5.C3.D0.R0.S15: RdPtrOffsetTxDq: 06
N7.C2.D0.R1.S06: wrcmd2dqsstartlatency: 04
N1.C2.D0.R1.S06: RdPtrOffsetTxDqs: 06
N5.C3.D0.R0.S16: RdPtrOffsetTxDq: 06
N7.C2.D0.R1.S06: RdPtrOffsetTxDq: 05
N1.C2.D0.R1.S06: PiTxDqs: 40
N5.C3.D0.R0.S17: RdPtrOffsetTxDq: 06
N7.C2.D0.R1.S06: RdPtrOffsetTxDqs: 06
N1.C2.D0.R1.S07: wrcmd2dqsstartlatency: 04
N5.C3.D0.R0.S00: RdPtrOffsetTxDq: 08
N7.C2.D0.R1.S06: PiTxDqs: 36
N1.C2.D0.R1.S07: RdPtrOffsetTxDq: 05
N5.C3.D0.R0.S01: RdPtrOffsetTxDq: 07
N7.C2.D0.R1.S07: wrcmd2dqsstartlatency: 04
N1.C2.D0.R1.S07: RdPtrOffsetTxDqs: 06
N5.C3.D0.R0.S02: RdPtrOffsetTxDq: 07
N7.C2.D0.R1.S07: RdPtrOffsetTxDq: 05
N1.C2.D0.R1.S07: PiTxDqs: 63
N5.C3.D0.R0.S03: RdPtrOffsetTxDq: 07
N7.C2.D0.R1.S07: RdPtrOffsetTxDqs: 06
N1.C2.D0.R1.S08: wrcmd2dqsstartlatency: 04
N5.C3.D0.R0.S04: RdPtrOffsetTxDq: 06
N7.C2.D0.R1.S07: PiTxDqs: 59
N1.C2.D0.R1.S08: RdPtrOffsetTxDq: 04
N5.C3.D0.R0.S05: RdPtrOffsetTxDq: 07
N7.C2.D0.R1.S08: wrcmd2dqsstartlatency: 04
N1.C2.D0.R1.S08: RdPtrOffsetTxDqs: 06
N5.C3.D0.R0.S06: RdPtrOffsetTxDq: 07
N7.C2.D0.R1.S08: RdPtrOffsetTxDq: 04
N1.C2.D0.R1.S08: PiTxDqs: 25
N5.C3.D0.R0.S07: RdPtrOffsetTxDq: 07
N7.C2.D0.R1.S08: RdPtrOffsetTxDqs: 06
N1.C2.D0.R1.S09: wrcmd2dqsstartlatency: 04
N5.C3.D0.R0.S08: RdPtrOffsetTxDq: 07
N7.C2.D0.R1.S08: PiTxDqs: 24
N1.C2.D0.R1.S09: RdPtrOffsetTxDq: 05
N2.C0: RdCmd2DataValidLatency = 17, (dlyFrmS = 11, clEff = 10, earlyCas = 0, selNTiming = 0)
N5.C3.D0.R0.S09: RdPtrOffsetTxDq: 08
N7.C2.D0.R1.S09: wrcmd2dqsstartlatency: 04
N1.C2.D0.R1.S09: RdPtrOffsetTxDqs: 07
N5.C3.D0.R0.S10: RdPtrOffsetTxDq: 07
N7.C2.D0.R1.S09: RdPtrOffsetTxDq: 05
N1.C2.D0.R1.S09: PiTxDqs: 31
N5.C3.D0.R0.S11: RdPtrOffsetTxDq: 07
N7.C2.D0.R1.S09: RdPtrOffsetTxDqs: 07
N1.C2.D0.R1.S10: wrcmd2dqsstartlatency: 04
N5.C3.D0.R0.S12: RdPtrOffsetTxDq: 07
N7.C2.D0.R1.S09: PiTxDqs: 27
N1.C2.D0.R1.S10: RdPtrOffsetTxDq: 05
N5.C3.D0.R0.S13: RdPtrOffsetTxDq: 06
N7.C2.D0.R1.S10: wrcmd2dqsstartlatency: 04
N1.C2.D0.R1.S10: RdPtrOffsetTxDqs: 07
N5.C3.D0.R0.S14: RdPtrOffsetTxDq: 07
N7.C2.D0.R1.S10: RdPtrOffsetTxDq: 05
N1.C2.D0.R1.S10: PiTxDqs: 18
N5.C3.D0.R0.S15: RdPtrOffsetTxDq: 07
N7.C2.D0.R1.S10: RdPtrOffsetTxDqs: 07
N1.C2.D0.R1.S11: wrcmd2dqsstartlatency: 04
N5.C3.D0.R0.S16: RdPtrOffsetTxDq: 07
N7.C2.D0.R1.S10: PiTxDqs: 16
N1.C2.D0.R1.S11: RdPtrOffsetTxDq: 05
N5.C3.D0.R0.S17: RdPtrOffsetTxDq: 07
N7.C2.D0.R1.S11: wrcmd2dqsstartlatency: 04
N1.C2.D0.R1.S11: RdPtrOffsetTxDqs: 07
N5.C3.D0.R0.S00: Total Delay in PI ticks: TxDQ = 968
N7.C2.D0.R1.S11: RdPtrOffsetTxDq: 05
N1.C2.D0.R1.S11: PiTxDqs: 06
N5.C3.D0.R0.S01: Total Delay in PI ticks: TxDQ = 953
N7.C2.D0.R1.S11: RdPtrOffsetTxDqs: 07
N1.C2.D0.R1.S12: wrcmd2dqsstartlatency: 04
N5.C3.D0.R0.S02: Total Delay in PI ticks: TxDQ = 940
N7.C2.D0.R1.S11: PiTxDqs: 05
N1.C2.D0.R1.S12: RdPtrOffsetTxDq: 05
N5.C3.D0.R0.S03: Total Delay in PI ticks: TxDQ = 925
N7.C2.D0.R1.S12: wrcmd2dqsstartlatency: 04
N1.C2.D0.R1.S12: RdPtrOffsetTxDqs: 06
N5.C3.D0.R0.S04: Total Delay in PI ticks: TxDQ = 886
N7.C2.D0.R1.S12: RdPtrOffsetTxDq: 05
N1.C2.D0.R1.S12: PiTxDqs: 54
N2.C1: RdCmd2DataValidLatency = 17, (dlyFrmS = 11, clEff = 10, earlyCas = 0, selNTiming = 0)
N5.C3.D0.R0.S05: Total Delay in PI ticks: TxDQ = 905
N7.C2.D0.R1.S12: RdPtrOffsetTxDqs: 06
N1.C2.D0.R1.S13: wrcmd2dqsstartlatency: 04
N5.C3.D0.R0.S06: Total Delay in PI ticks: TxDQ = 917
N7.C2.D0.R1.S12: PiTxDqs: 51
N1.C2.D0.R1.S13: RdPtrOffsetTxDq: 04
N5.C3.D0.R0.S07: Total Delay in PI ticks: TxDQ = 935
N7.C2.D0.R1.S13: wrcmd2dqsstartlatency: 04
N1.C2.D0.R1.S13: RdPtrOffsetTxDqs: 06
N5.C3.D0.R0.S08: Total Delay in PI ticks: TxDQ = 906
N7.C2.D0.R1.S13: RdPtrOffsetTxDq: 04
N1.C2.D0.R1.S13: PiTxDqs: 15
N5.C3.D0.R0.S09: Total Delay in PI ticks: TxDQ = 968
N7.C2.D0.R1.S13: RdPtrOffsetTxDqs: 06
N1.C2.D0.R1.S14: wrcmd2dqsstartlatency: 04
N5.C3.D0.R0.S10: Total Delay in PI ticks: TxDQ = 956
N7.C2.D0.R1.S13: PiTxDqs: 08
N1.C2.D0.R1.S14: RdPtrOffsetTxDq: 05
N5.C3.D0.R0.S11: Total Delay in PI ticks: TxDQ = 943
N7.C2.D0.R1.S14: wrcmd2dqsstartlatency: 04
N1.C2.D0.R1.S14: RdPtrOffsetTxDqs: 06
N5.C3.D0.R0.S12: Total Delay in PI ticks: TxDQ = 924
N7.C2.D0.R1.S14: RdPtrOffsetTxDq: 05
N1.C2.D0.R1.S14: PiTxDqs: 42
N5.C3.D0.R0.S13: Total Delay in PI ticks: TxDQ = 889
N7.C2.D0.R1.S14: RdPtrOffsetTxDqs: 06
N1.C2.D0.R1.S15: wrcmd2dqsstartlatency: 04
N5.C3.D0.R0.S14: Total Delay in PI ticks: TxDQ = 903
N7.C2.D0.R1.S14: PiTxDqs: 37
N1.C2.D0.R1.S15: RdPtrOffsetTxDq: 05
N5.C3.D0.R0.S15: Total Delay in PI ticks: TxDQ = 918
N7.C2.D0.R1.S15: wrcmd2dqsstartlatency: 04
N1.C2.D0.R1.S15: RdPtrOffsetTxDqs: 06
N5.C3.D0.R0.S16: Total Delay in PI ticks: TxDQ = 935
N7.C2.D0.R1.S15: RdPtrOffsetTxDq: 05
N1.C2.D0.R1.S15: PiTxDqs: 42
N5.C3.D0.R0.S17: Total Delay in PI ticks: TxDQ = 908
N7.C2.D0.R1.S15: RdPtrOffsetTxDqs: 06
N1.C2.D0.R1.S16: wrcmd2dqsstartlatency: 04
N5.C3.D0.R1.S00: wrcmd2dqsstartlatency: 04
N7.C2.D0.R1.S15: PiTxDqs: 39
N1.C2.D0.R1.S16: RdPtrOffsetTxDq: 05
N5.C3.D0.R1.S00: RdPtrOffsetTxDq: 06
N7.C2.D0.R1.S16: wrcmd2dqsstartlatency: 04
N1.C2.D0.R1.S16: RdPtrOffsetTxDqs: 07
N2.C0: RdCmd2DataValidLatency = 16, (dlyFrmS = 10, clEff = 10, earlyCas = 0, selNTiming = 0)
N5.C3.D0.R1.S00: RdPtrOffsetTxDqs: 07
N7.C2.D0.R1.S16: RdPtrOffsetTxDq: 05
N1.C2.D0.R1.S16: PiTxDqs: 00
N5.C3.D0.R1.S00: PiTxDqs: 44
N7.C2.D0.R1.S16: RdPtrOffsetTxDqs: 06
N1.C2.D0.R1.S17: wrcmd2dqsstartlatency: 04
N5.C3.D0.R1.S01: wrcmd2dqsstartlatency: 04
N7.C2.D0.R1.S16: PiTxDqs: 59
N1.C2.D0.R1.S17: RdPtrOffsetTxDq: 04
N5.C3.D0.R1.S01: RdPtrOffsetTxDq: 05
N7.C2.D0.R1.S17: wrcmd2dqsstartlatency: 04
N1.C2.D0.R1.S17: RdPtrOffsetTxDqs: 06
N5.C3.D0.R1.S01: RdPtrOffsetTxDqs: 07
N7.C2.D0.R1.S17: RdPtrOffsetTxDq: 04
N1.C2.D0.R1.S17: PiTxDqs: 27
N5.C3.D0.R1.S01: PiTxDqs: 27
N7.C2.D0.R1.S17: RdPtrOffsetTxDqs: 06
N1.C2.D0.R1.S00: RdPtrOffsetTxDq: 07
N5.C3.D0.R1.S02: wrcmd2dqsstartlatency: 04
N7.C2.D0.R1.S17: PiTxDqs: 24
N1.C2.D0.R1.S01: RdPtrOffsetTxDq: 06
N5.C3.D0.R1.S02: RdPtrOffsetTxDq: 05
N7.C2.D0.R1.S00: RdPtrOffsetTxDq: 06
N1.C2.D0.R1.S02: RdPtrOffsetTxDq: 06
N5.C3.D0.R1.S02: RdPtrOffsetTxDqs: 07
N7.C2.D0.R1.S01: RdPtrOffsetTxDq: 06
N1.C2.D0.R1.S03: RdPtrOffsetTxDq: 06
N5.C3.D0.R1.S02: PiTxDqs: 15
N7.C2.D0.R1.S02: RdPtrOffsetTxDq: 06
N1.C2.D0.R1.S04: RdPtrOffsetTxDq: 05
N5.C3.D0.R1.S03: wrcmd2dqsstartlatency: 04
N7.C2.D0.R1.S03: RdPtrOffsetTxDq: 06
N1.C2.D0.R1.S05: RdPtrOffsetTxDq: 06
N5.C3.D0.R1.S03: RdPtrOffsetTxDq: 05
N7.C2.D0.R1.S04: RdPtrOffsetTxDq: 05
N1.C2.D0.R1.S06: RdPtrOffsetTxDq: 06
N5.C3.D0.R1.S03: RdPtrOffsetTxDqs: 06
N7.C2.D0.R1.S05: RdPtrOffsetTxDq: 06
N1.C2.D0.R1.S07: RdPtrOffsetTxDq: 06
N5.C3.D0.R1.S03: PiTxDqs: 62
N7.C2.D0.R1.S06: RdPtrOffsetTxDq: 06
N1.C2.D0.R1.S08: RdPtrOffsetTxDq: 05
N2.C1: RdCmd2DataValidLatency = 16, (dlyFrmS = 10, clEff = 10, earlyCas = 0, selNTiming = 0)
N5.C3.D0.R1.S04: wrcmd2dqsstartlatency: 04
N7.C2.D0.R1.S07: RdPtrOffsetTxDq: 06
N1.C2.D0.R1.S09: RdPtrOffsetTxDq: 06
N5.C3.D0.R1.S04: RdPtrOffsetTxDq: 04
N7.C2.D0.R1.S08: RdPtrOffsetTxDq: 05
N1.C2.D0.R1.S10: RdPtrOffsetTxDq: 06
N5.C3.D0.R1.S04: RdPtrOffsetTxDqs: 06
N7.C2.D0.R1.S09: RdPtrOffsetTxDq: 06
N1.C2.D0.R1.S11: RdPtrOffsetTxDq: 06
N5.C3.D0.R1.S04: PiTxDqs: 27
N7.C2.D0.R1.S10: RdPtrOffsetTxDq: 06
N1.C2.D0.R1.S12: RdPtrOffsetTxDq: 06
N5.C3.D0.R1.S05: wrcmd2dqsstartlatency: 04
N7.C2.D0.R1.S11: RdPtrOffsetTxDq: 06
N1.C2.D0.R1.S13: RdPtrOffsetTxDq: 05
N5.C3.D0.R1.S05: RdPtrOffsetTxDq: 05
N7.C2.D0.R1.S12: RdPtrOffsetTxDq: 06
N1.C2.D0.R1.S14: RdPtrOffsetTxDq: 06
N5.C3.D0.R1.S05: RdPtrOffsetTxDqs: 06
N7.C2.D0.R1.S13: RdPtrOffsetTxDq: 05
N1.C2.D0.R1.S15: RdPtrOffsetTxDq: 06
N5.C3.D0.R1.S05: PiTxDqs: 43
N7.C2.D0.R1.S14: RdPtrOffsetTxDq: 06
N1.C2.D0.R1.S16: RdPtrOffsetTxDq: 06
N5.C3.D0.R1.S06: wrcmd2dqsstartlatency: 04
N7.C2.D0.R1.S15: RdPtrOffsetTxDq: 06
N1.C2.D0.R1.S17: RdPtrOffsetTxDq: 05
N5.C3.D0.R1.S06: RdPtrOffsetTxDq: 05
N7.C2.D0.R1.S16: RdPtrOffsetTxDq: 06
N1.C2.D0.R1.S00: RdPtrOffsetTxDq: 08
N5.C3.D0.R1.S06: RdPtrOffsetTxDqs: 06
N7.C2.D0.R1.S17: RdPtrOffsetTxDq: 05
N1.C2.D0.R1.S01: RdPtrOffsetTxDq: 07
N5.C3.D0.R1.S06: PiTxDqs: 56
N7.C2.D0.R1.S00: RdPtrOffsetTxDq: 07
N1.C2.D0.R1.S02: RdPtrOffsetTxDq: 07
N5.C3.D0.R1.S07: wrcmd2dqsstartlatency: 04
N7.C2.D0.R1.S01: RdPtrOffsetTxDq: 07
N1.C2.D0.R1.S03: RdPtrOffsetTxDq: 07
N5.C3.D0.R1.S07: RdPtrOffsetTxDq: 05
N7.C2.D0.R1.S02: RdPtrOffsetTxDq: 07
N1.C2.D0.R1.S04: RdPtrOffsetTxDq: 06
N5.C3.D0.R1.S07: RdPtrOffsetTxDqs: 07
N7.C2.D0.R1.S03: RdPtrOffsetTxDq: 07
N1.C2.D0.R1.S05: RdPtrOffsetTxDq: 07
N5.C3.D0.R1.S07: PiTxDqs: 09
N7.C2.D0.R1.S04: RdPtrOffsetTxDq: 06
N1.C2.D0.R1.S06: RdPtrOffsetTxDq: 07
N5.C3.D0.R1.S08: wrcmd2dqsstartlatency: 04
N7.C2.D0.R1.S05: RdPtrOffsetTxDq: 07
N1.C2.D0.R1.S07: RdPtrOffsetTxDq: 07
N2.C0: RdCmd2DataValidLatency = 15, (dlyFrmS = 9, clEff = 10, earlyCas = 0, selNTiming = 0)
N5.C3.D0.R1.S08: RdPtrOffsetTxDq: 05
N7.C2.D0.R1.S06: RdPtrOffsetTxDq: 07
N1.C2.D0.R1.S08: RdPtrOffsetTxDq: 06
N5.C3.D0.R1.S08: RdPtrOffsetTxDqs: 06
N7.C2.D0.R1.S07: RdPtrOffsetTxDq: 07
N1.C2.D0.R1.S09: RdPtrOffsetTxDq: 07
N5.C3.D0.R1.S08: PiTxDqs: 44
N7.C2.D0.R1.S08: RdPtrOffsetTxDq: 06
N1.C2.D0.R1.S10: RdPtrOffsetTxDq: 07
N5.C3.D0.R1.S09: wrcmd2dqsstartlatency: 04
N7.C2.D0.R1.S09: RdPtrOffsetTxDq: 07
N1.C2.D0.R1.S11: RdPtrOffsetTxDq: 07
N5.C3.D0.R1.S09: RdPtrOffsetTxDq: 06
N7.C2.D0.R1.S10: RdPtrOffsetTxDq: 07
N1.C2.D0.R1.S12: RdPtrOffsetTxDq: 07
N5.C3.D0.R1.S09: RdPtrOffsetTxDqs: 07
N7.C2.D0.R1.S11: RdPtrOffsetTxDq: 07
N1.C2.D0.R1.S13: RdPtrOffsetTxDq: 06
N5.C3.D0.R1.S09: PiTxDqs: 42
N7.C2.D0.R1.S12: RdPtrOffsetTxDq: 07
N1.C2.D0.R1.S14: RdPtrOffsetTxDq: 07
N5.C3.D0.R1.S10: wrcmd2dqsstartlatency: 04
N7.C2.D0.R1.S13: RdPtrOffsetTxDq: 06
N1.C2.D0.R1.S15: RdPtrOffsetTxDq: 07
N5.C3.D0.R1.S10: RdPtrOffsetTxDq: 05
N7.C2.D0.R1.S14: RdPtrOffsetTxDq: 07
N1.C2.D0.R1.S16: RdPtrOffsetTxDq: 07
N5.C3.D0.R1.S10: RdPtrOffsetTxDqs: 07
N7.C2.D0.R1.S15: RdPtrOffsetTxDq: 07
N1.C2.D0.R1.S17: RdPtrOffsetTxDq: 06
N5.C3.D0.R1.S10: PiTxDqs: 27
N7.C2.D0.R1.S16: RdPtrOffsetTxDq: 07
N1.C2.D0.R1.S00: Total Delay in PI ticks: TxDQ = 959
N5.C3.D0.R1.S11: wrcmd2dqsstartlatency: 04
N7.C2.D0.R1.S17: RdPtrOffsetTxDq: 06
N1.C2.D0.R1.S01: Total Delay in PI ticks: TxDQ = 942
N5.C3.D0.R1.S11: RdPtrOffsetTxDq: 05
N7.C2.D0.R1.S00: Total Delay in PI ticks: TxDQ = 957
N1.C2.D0.R1.S02: Total Delay in PI ticks: TxDQ = 929
N5.C3.D0.R1.S11: RdPtrOffsetTxDqs: 07
N7.C2.D0.R1.S01: Total Delay in PI ticks: TxDQ = 940
N1.C2.D0.R1.S03: Total Delay in PI ticks: TxDQ = 914
N2.C1: RdCmd2DataValidLatency = 15, (dlyFrmS = 9, clEff = 10, earlyCas = 0, selNTiming = 0)
N5.C3.D0.R1.S11: PiTxDqs: 16
N7.C2.D0.R1.S02: Total Delay in PI ticks: TxDQ = 930
N1.C2.D0.R1.S04: Total Delay in PI ticks: TxDQ = 877
N5.C3.D0.R1.S12: wrcmd2dqsstartlatency: 04
N7.C2.D0.R1.S03: Total Delay in PI ticks: TxDQ = 910
N1.C2.D0.R1.S05: Total Delay in PI ticks: TxDQ = 904
N5.C3.D0.R1.S12: RdPtrOffsetTxDq: 05
N7.C2.D0.R1.S04: Total Delay in PI ticks: TxDQ = 873
N1.C2.D0.R1.S06: Total Delay in PI ticks: TxDQ = 903
N5.C3.D0.R1.S12: RdPtrOffsetTxDqs: 07
N7.C2.D0.R1.S05: Total Delay in PI ticks: TxDQ = 899
N1.C2.D0.R1.S07: Total Delay in PI ticks: TxDQ = 924
N5.C3.D0.R1.S12: PiTxDqs: 00
N7.C2.D0.R1.S06: Total Delay in PI ticks: TxDQ = 899
N1.C2.D0.R1.S08: Total Delay in PI ticks: TxDQ = 888
N5.C3.D0.R1.S13: wrcmd2dqsstartlatency: 04
N7.C2.D0.R1.S07: Total Delay in PI ticks: TxDQ = 922
N1.C2.D0.R1.S09: Total Delay in PI ticks: TxDQ = 957
N5.C3.D0.R1.S13: RdPtrOffsetTxDq: 04
N7.C2.D0.R1.S08: Total Delay in PI ticks: TxDQ = 885
N1.C2.D0.R1.S10: Total Delay in PI ticks: TxDQ = 945
N5.C3.D0.R1.S13: RdPtrOffsetTxDqs: 06
N7.C2.D0.R1.S09: Total Delay in PI ticks: TxDQ = 954
N1.C2.D0.R1.S11: Total Delay in PI ticks: TxDQ = 932
N5.C3.D0.R1.S13: PiTxDqs: 27
N7.C2.D0.R1.S10: Total Delay in PI ticks: TxDQ = 942
N1.C2.D0.R1.S12: Total Delay in PI ticks: TxDQ = 916
N5.C3.D0.R1.S14: wrcmd2dqsstartlatency: 04
N7.C2.D0.R1.S11: Total Delay in PI ticks: TxDQ = 930
N1.C2.D0.R1.S13: Total Delay in PI ticks: TxDQ = 879
N5.C3.D0.R1.S14: RdPtrOffsetTxDq: 05
N7.C2.D0.R1.S12: Total Delay in PI ticks: TxDQ = 912
N1.C2.D0.R1.S14: Total Delay in PI ticks: TxDQ = 904
N5.C3.D0.R1.S14: RdPtrOffsetTxDqs: 06
N7.C2.D0.R1.S13: Total Delay in PI ticks: TxDQ = 872
N1.C2.D0.R1.S15: Total Delay in PI ticks: TxDQ = 905
N5.C3.D0.R1.S14: PiTxDqs: 42
N7.C2.D0.R1.S14: Total Delay in PI ticks: TxDQ = 899
N1.C2.D0.R1.S16: Total Delay in PI ticks: TxDQ = 927
N2.C0: RdCmd2DataValidLatency = 14, (dlyFrmS = 8, clEff = 10, earlyCas = 0, selNTiming = 0)
N5.C3.D0.R1.S15: wrcmd2dqsstartlatency: 04
N7.C2.D0.R1.S15: Total Delay in PI ticks: TxDQ = 901
N1.C2.D0.R1.S17: Total Delay in PI ticks: TxDQ = 889
N5.C3.D0.R1.S15: RdPtrOffsetTxDq: 05
N7.C2.D0.R1.S16: Total Delay in PI ticks: TxDQ = 922
N1.C2: Calculating Optimimum DQ/DQS Values
N5.C3.D0.R1.S15: RdPtrOffsetTxDqs: 06
N7.C2.D0.R1.S17: Total Delay in PI ticks: TxDQ = 884
N5.C3.D0.R1.S15: PiTxDqs: 56
N7.C2: Calculating Optimimum DQ/DQS Values
START_DATA_TX_DQ
N5.C3.D0.R1.S16: wrcmd2dqsstartlatency: 04
N1.C2.S00: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 009
N5.C3.D0.R1.S16: RdPtrOffsetTxDq: 05
START_DATA_TX_DQ
N1.C2.S00: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 009
N5.C3.D0.R1.S16: RdPtrOffsetTxDqs: 07
N7.C2.S00: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 009
N1.C2.S01: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 009
N5.C3.D0.R1.S16: PiTxDqs: 10
N7.C2.S00: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 009
N1.C2.S01: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 009
N5.C3.D0.R1.S17: wrcmd2dqsstartlatency: 04
N7.C2.S01: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 009
N1.C2.S02: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 009
N5.C3.D0.R1.S17: RdPtrOffsetTxDq: 05
N7.C2.S01: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 009
N1.C2.S02: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 009
N2.C1: RdCmd2DataValidLatency = 14, (dlyFrmS = 8, clEff = 10, earlyCas = 0, selNTiming = 0)
N5.C3.D0.R1.S17: RdPtrOffsetTxDqs: 06
N7.C2.S02: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 009
N1.C2.S03: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 008
N5.C3.D0.R1.S17: PiTxDqs: 43
N7.C2.S02: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 009
N1.C2.S03: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 008
N5.C3.D0.R1.S00: RdPtrOffsetTxDq: 07
N7.C2.S03: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 008
N1.C2.S04: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 007, RdPtrOffsetTxDqs = 008
N5.C3.D0.R1.S01: RdPtrOffsetTxDq: 06
N7.C2.S03: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 008
N1.C2.S04: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 007, RdPtrOffsetTxDqs = 008
N5.C3.D0.R1.S02: RdPtrOffsetTxDq: 06
N7.C2.S04: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 007, RdPtrOffsetTxDqs = 008
N1.C2.S05: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 008
N5.C3.D0.R1.S03: RdPtrOffsetTxDq: 06
N7.C2.S04: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 007, RdPtrOffsetTxDqs = 008
N1.C2.S05: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 008
N5.C3.D0.R1.S04: RdPtrOffsetTxDq: 05
N7.C2.S05: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 008
N1.C2.S06: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 008
N5.C3.D0.R1.S05: RdPtrOffsetTxDq: 06
N7.C2.S05: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 008
N1.C2.S06: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 008
N5.C3.D0.R1.S06: RdPtrOffsetTxDq: 06
N7.C2.S06: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 008
N1.C2.S07: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 008
N2.C0: RdCmd2DataValidLatency = 16, (dlyFrmS = 10, clEff = 10, earlyCas = 0, selNTiming = 0)
N5.C3.D0.R1.S07: RdPtrOffsetTxDq: 06
N7.C2.S06: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 008
N1.C2.S07: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 008
N5.C3.D0.R1.S08: RdPtrOffsetTxDq: 06
N7.C2.S07: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 008
N1.C2.S08: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 007, RdPtrOffsetTxDqs = 008
N5.C3.D0.R1.S09: RdPtrOffsetTxDq: 07
N7.C2.S07: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 008
N1.C2.S08: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 007, RdPtrOffsetTxDqs = 008
N5.C3.D0.R1.S10: RdPtrOffsetTxDq: 06
N7.C2.S08: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 007, RdPtrOffsetTxDqs = 008
N1.C2.D0.R0.S00: TxDqs: plus1 = 1, minus1 = 0, PI = 32, DB = 0
N5.C3.D0.R1.S11: RdPtrOffsetTxDq: 06
N7.C2.S08: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 007, RdPtrOffsetTxDqs = 008
N1.C2.D0.R0.S00: TxDq : plus1 = 1, minus1 = 0, PI = 63, DB = 1
N5.C3.D0.R1.S12: RdPtrOffsetTxDq: 06
N7.C2.D0.R0.S00: TxDqs: plus1 = 1, minus1 = 0, PI = 30, DB = 0
N1.C2.D0.R0.S01: TxDqs: plus1 = 1, minus1 = 0, PI = 17, DB = 0
N5.C3.D0.R1.S13: RdPtrOffsetTxDq: 05
N7.C2.D0.R0.S00: TxDq : plus1 = 1, minus1 = 0, PI = 60, DB = 1
N1.C2.D0.R0.S01: TxDq : plus1 = 1, minus1 = 0, PI = 46, DB = 0
N5.C3.D0.R1.S14: RdPtrOffsetTxDq: 06
N7.C2.D0.R0.S01: TxDqs: plus1 = 1, minus1 = 0, PI = 14, DB = 1
N1.C2.D0.R0.S02: TxDqs: plus1 = 1, minus1 = 0, PI = 04, DB = 1
N5.C3.D0.R1.S15: RdPtrOffsetTxDq: 06
N7.C2.D0.R0.S01: TxDq : plus1 = 1, minus1 = 0, PI = 44, DB = 0
N1.C2.D0.R0.S02: TxDq : plus1 = 1, minus1 = 0, PI = 34, DB = 0
N2.C1: RdCmd2DataValidLatency = 16, (dlyFrmS = 10, clEff = 10, earlyCas = 0, selNTiming = 0)
N5.C3.D0.R1.S16: RdPtrOffsetTxDq: 06
N7.C2.D0.R0.S02: TxDqs: plus1 = 1, minus1 = 0, PI = 03, DB = 1
N1.C2.D0.R0.S03: TxDqs: plus1 = 1, minus1 = 0, PI = 53, DB = 1
N5.C3.D0.R1.S17: RdPtrOffsetTxDq: 06
N7.C2.D0.R0.S02: TxDq : plus1 = 1, minus1 = 0, PI = 34, DB = 0
N1.C2.D0.R0.S03: TxDq : plus1 = 1, minus1 = 0, PI = 18, DB = 0
N5.C3.D0.R1.S00: RdPtrOffsetTxDq: 08
N7.C2.D0.R0.S03: TxDqs: plus1 = 1, minus1 = 0, PI = 50, DB = 1
N1.C2.D0.R0.S04: TxDqs: plus1 = 1, minus1 = 0, PI = 14, DB = 1
N5.C3.D0.R1.S01: RdPtrOffsetTxDq: 07
N7.C2.D0.R0.S03: TxDq : plus1 = 1, minus1 = 0, PI = 15, DB = 1
N1.C2.D0.R0.S04: TxDq : plus1 = 1, minus1 = 0, PI = 46, DB = 0
N5.C3.D0.R1.S02: RdPtrOffsetTxDq: 07
N7.C2.D0.R0.S04: TxDqs: plus1 = 1, minus1 = 0, PI = 08, DB = 1
N1.C2.D0.R0.S05: TxDqs: plus1 = 1, minus1 = 0, PI = 43, DB = 0
N5.C3.D0.R1.S03: RdPtrOffsetTxDq: 07
N7.C2.D0.R0.S04: TxDq : plus1 = 1, minus1 = 0, PI = 40, DB = 0
N1.C2.D0.R0.S05: TxDq : plus1 = 1, minus1 = 0, PI = 08, DB = 1
N5.C3.D0.R1.S04: RdPtrOffsetTxDq: 06
N7.C2.D0.R0.S05: TxDqs: plus1 = 1, minus1 = 0, PI = 38, DB = 0
N1.C2.D0.R0.S06: TxDqs: plus1 = 1, minus1 = 0, PI = 39, DB = 0
N5.C3.D0.R1.S05: RdPtrOffsetTxDq: 07
N7.C2.D0.R0.S05: TxDq : plus1 = 1, minus1 = 0, PI = 03, DB = 1
N1.C2.D0.R0.S06: TxDq : plus1 = 1, minus1 = 0, PI = 07, DB = 1
N5.C3.D0.R1.S06: RdPtrOffsetTxDq: 07
N7.C2.D0.R0.S06: TxDqs: plus1 = 1, minus1 = 0, PI = 37, DB = 0
N1.C2.D0.R0.S07: TxDqs: plus1 = 1, minus1 = 0, PI = 63, DB = 1
N5.C3.D0.R1.S07: RdPtrOffsetTxDq: 07
N7.C2.D0.R0.S06: TxDq : plus1 = 1, minus1 = 0, PI = 04, DB = 1
N1.C2.D0.R0.S07: TxDq : plus1 = 1, minus1 = 0, PI = 28, DB = 0
N2.C0: AdjustTotalRoundTripTime: SUCCESS - worst rank = 1, host round trip = 73, MXB cmd2dat = 10
N5.C3.D0.R1.S08: RdPtrOffsetTxDq: 07
N7.C2.D0.R0.S07: TxDqs: plus1 = 1, minus1 = 0, PI = 59, DB = 1
N1.C2.D0.R0.S08: TxDqs: plus1 = 1, minus1 = 0, PI = 27, DB = 0
N2.C2: AdjustTotalRoundTripTime
N5.C3.D0.R1.S09: RdPtrOffsetTxDq: 08
N7.C2.D0.R0.S07: TxDq : plus1 = 1, minus1 = 0, PI = 26, DB = 0
N1.C2.D0.R0.S08: TxDq : plus1 = 1, minus1 = 0, PI = 56, DB = 1
N2.C1: AdjustTotalRoundTripTime: worstRank = 0
N5.C3.D0.R1.S10: RdPtrOffsetTxDq: 07
N7.C2.D0.R0.S08: TxDqs: plus1 = 1, minus1 = 0, PI = 24, DB = 0
N1.C2.D0.R0.S09: TxDqs: plus1 = 1, minus1 = 0, PI = 32, DB = 0
N2.C2: AdjustTotalRoundTripTime: worstRank dimm = 0, rank = 0
N5.C3.D0.R1.S11: RdPtrOffsetTxDq: 07
N7.C2.D0.R0.S08: TxDq : plus1 = 1, minus1 = 0, PI = 53, DB = 1
N1.C2.D0.R0.S09: TxDq : plus1 = 1, minus1 = 0, PI = 61, DB = 1
N2.C3: AdjustTotalRoundTripTime: worstRank dimm = 0, rank = 0
N5.C3.D0.R1.S12: RdPtrOffsetTxDq: 07
N7.C2.D0.R0.S09: TxDqs: plus1 = 1, minus1 = 0, PI = 28, DB = 0
N1.C2.D0.R0.S10: TxDqs: plus1 = 1, minus1 = 0, PI = 19, DB = 0
N2.C1: AdjustTotalRoundTripTime: ddrChMask = 0xC
N5.C3.D0.R1.S13: RdPtrOffsetTxDq: 06
N7.C2.D0.R0.S09: TxDq : plus1 = 1, minus1 = 0, PI = 58, DB = 1
N1.C2.D0.R0.S10: TxDq : plus1 = 1, minus1 = 0, PI = 49, DB = 1
N5.C3.D0.R1.S14: RdPtrOffsetTxDq: 07
N7.C2.D0.R0.S10: TxDqs: plus1 = 1, minus1 = 0, PI = 15, DB = 1
N1.C2.D0.R0.S11: TxDqs: plus1 = 1, minus1 = 0, PI = 05, DB = 1
N2.C2: RdCmd2DataValidLatency = 20, (dlyFrmS = 14, clEff = 10, earlyCas = 0, selNTiming = 0)
N5.C3.D0.R1.S15: RdPtrOffsetTxDq: 07
N7.C2.D0.R0.S10: TxDq : plus1 = 1, minus1 = 0, PI = 45, DB = 0
N1.C2.D0.R0.S11: TxDq : plus1 = 1, minus1 = 0, PI = 35, DB = 0
N5.C3.D0.R1.S16: RdPtrOffsetTxDq: 07
N7.C2.D0.R0.S11: TxDqs: plus1 = 1, minus1 = 0, PI = 05, DB = 1
N1.C2.D0.R0.S12: TxDqs: plus1 = 1, minus1 = 0, PI = 54, DB = 1
N5.C3.D0.R1.S17: RdPtrOffsetTxDq: 07
N7.C2.D0.R0.S11: TxDq : plus1 = 1, minus1 = 0, PI = 35, DB = 0
N1.C2.D0.R0.S12: TxDq : plus1 = 1, minus1 = 0, PI = 20, DB = 0
N5.C3.D0.R1.S00: Total Delay in PI ticks: TxDQ = 969
N7.C2.D0.R0.S12: TxDqs: plus1 = 1, minus1 = 0, PI = 51, DB = 1
N1.C2.D0.R0.S13: TxDqs: plus1 = 1, minus1 = 0, PI = 14, DB = 1
N5.C3.D0.R1.S01: Total Delay in PI ticks: TxDQ = 953
N7.C2.D0.R0.S12: TxDq : plus1 = 1, minus1 = 0, PI = 16, DB = 0
N1.C2.D0.R0.S13: TxDq : plus1 = 1, minus1 = 0, PI = 46, DB = 0
N5.C3.D0.R1.S02: Total Delay in PI ticks: TxDQ = 941
N7.C2.D0.R0.S13: TxDqs: plus1 = 1, minus1 = 0, PI = 08, DB = 1
N1.C2.D0.R0.S14: TxDqs: plus1 = 1, minus1 = 0, PI = 41, DB = 0
N5.C3.D0.R1.S03: Total Delay in PI ticks: TxDQ = 925
N7.C2.D0.R0.S13: TxDq : plus1 = 1, minus1 = 0, PI = 40, DB = 0
N1.C2.D0.R0.S14: TxDq : plus1 = 1, minus1 = 0, PI = 08, DB = 1
N5.C3.D0.R1.S04: Total Delay in PI ticks: TxDQ = 889
N7.C2.D0.R0.S14: TxDqs: plus1 = 1, minus1 = 0, PI = 37, DB = 0
N1.C2.D0.R0.S15: TxDqs: plus1 = 1, minus1 = 0, PI = 41, DB = 0
N5.C3.D0.R1.S05: Total Delay in PI ticks: TxDQ = 907
N7.C2.D0.R0.S14: TxDq : plus1 = 1, minus1 = 0, PI = 03, DB = 1
N1.C2.D0.R0.S15: TxDq : plus1 = 1, minus1 = 0, PI = 09, DB = 1
N2.C3: RdCmd2DataValidLatency = 20, (dlyFrmS = 14, clEff = 10, earlyCas = 0, selNTiming = 0)
N5.C3.D0.R1.S06: Total Delay in PI ticks: TxDQ = 917
N7.C2.D0.R0.S15: TxDqs: plus1 = 1, minus1 = 0, PI = 38, DB = 0
N1.C2.D0.R0.S16: TxDqs: plus1 = 1, minus1 = 0, PI = 63, DB = 1
N5.C3.D0.R1.S07: Total Delay in PI ticks: TxDQ = 934
N7.C2.D0.R0.S15: TxDq : plus1 = 1, minus1 = 0, PI = 05, DB = 1
N1.C2.D0.R0.S16: TxDq : plus1 = 1, minus1 = 0, PI = 30, DB = 0
N5.C3.D0.R1.S08: Total Delay in PI ticks: TxDQ = 906
N7.C2.D0.R0.S16: TxDqs: plus1 = 1, minus1 = 0, PI = 58, DB = 1
N1.C2.D0.R0.S17: TxDqs: plus1 = 1, minus1 = 0, PI = 28, DB = 0
N5.C3.D0.R1.S09: Total Delay in PI ticks: TxDQ = 966
N7.C2.D0.R0.S16: TxDq : plus1 = 1, minus1 = 0, PI = 25, DB = 0
N1.C2.D0.R0.S17: TxDq : plus1 = 1, minus1 = 0, PI = 58, DB = 1
N5.C3.D0.R1.S10: Total Delay in PI ticks: TxDQ = 953
N7.C2.D0.R0.S17: TxDqs: plus1 = 1, minus1 = 0, PI = 24, DB = 0
N1.C2.D0.R1.S00: TxDqs: plus1 = 1, minus1 = 0, PI = 32, DB = 0
N5.C3.D0.R1.S11: Total Delay in PI ticks: TxDQ = 944
N7.C2.D0.R0.S17: TxDq : plus1 = 1, minus1 = 0, PI = 52, DB = 1
N1.C2.D0.R1.S00: TxDq : plus1 = 1, minus1 = 0, PI = 63, DB = 1
N5.C3.D0.R1.S12: Total Delay in PI ticks: TxDQ = 926
N7.C2.D0.R1.S00: TxDqs: plus1 = 1, minus1 = 0, PI = 30, DB = 0
N1.C2.D0.R1.S01: TxDqs: plus1 = 1, minus1 = 0, PI = 17, DB = 0
N5.C3.D0.R1.S13: Total Delay in PI ticks: TxDQ = 888
N7.C2.D0.R1.S00: TxDq : plus1 = 1, minus1 = 0, PI = 60, DB = 1
N1.C2.D0.R1.S01: TxDq : plus1 = 1, minus1 = 0, PI = 46, DB = 0
N5.C3.D0.R1.S14: Total Delay in PI ticks: TxDQ = 904
N7.C2.D0.R1.S01: TxDqs: plus1 = 1, minus1 = 0, PI = 14, DB = 1
N1.C2.D0.R1.S02: TxDqs: plus1 = 1, minus1 = 0, PI = 04, DB = 1
N5.C3.D0.R1.S15: Total Delay in PI ticks: TxDQ = 918
N7.C2.D0.R1.S01: TxDq : plus1 = 1, minus1 = 0, PI = 44, DB = 0
N1.C2.D0.R1.S02: TxDq : plus1 = 1, minus1 = 0, PI = 34, DB = 0
N5.C3.D0.R1.S16: Total Delay in PI ticks: TxDQ = 935
N7.C2.D0.R1.S02: TxDqs: plus1 = 1, minus1 = 0, PI = 03, DB = 1
N1.C2.D0.R1.S03: TxDqs: plus1 = 1, minus1 = 0, PI = 53, DB = 1
N2.C2: RdCmd2DataValidLatency = 19, (dlyFrmS = 13, clEff = 10, earlyCas = 0, selNTiming = 0)
N5.C3.D0.R1.S17: Total Delay in PI ticks: TxDQ = 906
N7.C2.D0.R1.S02: TxDq : plus1 = 1, minus1 = 0, PI = 34, DB = 0
N1.C2.D0.R1.S03: TxDq : plus1 = 1, minus1 = 0, PI = 18, DB = 0
N5.C3: Calculating Optimimum DQ/DQS Values
N7.C2.D0.R1.S03: TxDqs: plus1 = 1, minus1 = 0, PI = 50, DB = 1
N1.C2.D0.R1.S04: TxDqs: plus1 = 1, minus1 = 0, PI = 14, DB = 1
N7.C2.D0.R1.S03: TxDq : plus1 = 1, minus1 = 0, PI = 15, DB = 1
N1.C2.D0.R1.S04: TxDq : plus1 = 1, minus1 = 0, PI = 46, DB = 0
START_DATA_TX_DQ
N7.C2.D0.R1.S04: TxDqs: plus1 = 1, minus1 = 0, PI = 08, DB = 1
N1.C2.D0.R1.S05: TxDqs: plus1 = 1, minus1 = 0, PI = 43, DB = 0
N5.C3.S00: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 009, RdPtrOffsetTxDqs = 009
N7.C2.D0.R1.S04: TxDq : plus1 = 1, minus1 = 0, PI = 40, DB = 0
N1.C2.D0.R1.S05: TxDq : plus1 = 1, minus1 = 0, PI = 08, DB = 1
N5.C3.S00: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 009, RdPtrOffsetTxDqs = 009
N7.C2.D0.R1.S05: TxDqs: plus1 = 1, minus1 = 0, PI = 38, DB = 0
N1.C2.D0.R1.S06: TxDqs: plus1 = 1, minus1 = 0, PI = 39, DB = 0
N5.C3.S01: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 009
N7.C2.D0.R1.S05: TxDq : plus1 = 1, minus1 = 0, PI = 03, DB = 1
N1.C2.D0.R1.S06: TxDq : plus1 = 1, minus1 = 0, PI = 07, DB = 1
N5.C3.S01: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 009
N7.C2.D0.R1.S06: TxDqs: plus1 = 1, minus1 = 0, PI = 37, DB = 0
N1.C2.D0.R1.S07: TxDqs: plus1 = 1, minus1 = 0, PI = 63, DB = 1
N5.C3.S02: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 009
N7.C2.D0.R1.S06: TxDq : plus1 = 1, minus1 = 0, PI = 04, DB = 1
N1.C2.D0.R1.S07: TxDq : plus1 = 1, minus1 = 0, PI = 28, DB = 0
N2.C3: RdCmd2DataValidLatency = 19, (dlyFrmS = 13, clEff = 10, earlyCas = 0, selNTiming = 0)
N5.C3.S02: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 009
N7.C2.D0.R1.S07: TxDqs: plus1 = 1, minus1 = 0, PI = 59, DB = 1
N1.C2.D0.R1.S08: TxDqs: plus1 = 1, minus1 = 0, PI = 27, DB = 0
N5.C3.S03: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 008
N7.C2.D0.R1.S07: TxDq : plus1 = 1, minus1 = 0, PI = 26, DB = 0
N1.C2.D0.R1.S08: TxDq : plus1 = 1, minus1 = 0, PI = 56, DB = 1
N5.C3.S03: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 008
N7.C2.D0.R1.S08: TxDqs: plus1 = 1, minus1 = 0, PI = 24, DB = 0
N1.C2.D0.R1.S09: TxDqs: plus1 = 1, minus1 = 0, PI = 32, DB = 0
N5.C3.S04: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 007, RdPtrOffsetTxDqs = 008
N7.C2.D0.R1.S08: TxDq : plus1 = 1, minus1 = 0, PI = 53, DB = 1
N1.C2.D0.R1.S09: TxDq : plus1 = 1, minus1 = 0, PI = 61, DB = 1
N5.C3.S04: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 007, RdPtrOffsetTxDqs = 008
N7.C2.D0.R1.S09: TxDqs: plus1 = 1, minus1 = 0, PI = 28, DB = 0
N1.C2.D0.R1.S10: TxDqs: plus1 = 1, minus1 = 0, PI = 19, DB = 0
N5.C3.S05: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 008
N7.C2.D0.R1.S09: TxDq : plus1 = 1, minus1 = 0, PI = 58, DB = 1
N1.C2.D0.R1.S10: TxDq : plus1 = 1, minus1 = 0, PI = 49, DB = 1
N5.C3.S05: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 008
N7.C2.D0.R1.S10: TxDqs: plus1 = 1, minus1 = 0, PI = 15, DB = 1
N1.C2.D0.R1.S11: TxDqs: plus1 = 1, minus1 = 0, PI = 05, DB = 1
N5.C3.S06: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 008
N7.C2.D0.R1.S10: TxDq : plus1 = 1, minus1 = 0, PI = 45, DB = 0
N1.C2.D0.R1.S11: TxDq : plus1 = 1, minus1 = 0, PI = 35, DB = 0
N5.C3.S06: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 008
N7.C2.D0.R1.S11: TxDqs: plus1 = 1, minus1 = 0, PI = 05, DB = 1
N1.C2.D0.R1.S12: TxDqs: plus1 = 1, minus1 = 0, PI = 54, DB = 1
N2.C2: RdCmd2DataValidLatency = 18, (dlyFrmS = 12, clEff = 10, earlyCas = 0, selNTiming = 0)
N5.C3.S07: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 009
N7.C2.D0.R1.S11: TxDq : plus1 = 1, minus1 = 0, PI = 35, DB = 0
N1.C2.D0.R1.S12: TxDq : plus1 = 1, minus1 = 0, PI = 20, DB = 0
N5.C3.S07: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 009
N7.C2.D0.R1.S12: TxDqs: plus1 = 1, minus1 = 0, PI = 51, DB = 1
N1.C2.D0.R1.S13: TxDqs: plus1 = 1, minus1 = 0, PI = 14, DB = 1
N5.C3.S08: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 008
N7.C2.D0.R1.S12: TxDq : plus1 = 1, minus1 = 0, PI = 16, DB = 0
N1.C2.D0.R1.S13: TxDq : plus1 = 1, minus1 = 0, PI = 46, DB = 0
N5.C3.S08: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 008
N7.C2.D0.R1.S13: TxDqs: plus1 = 1, minus1 = 0, PI = 08, DB = 1
N1.C2.D0.R1.S14: TxDqs: plus1 = 1, minus1 = 0, PI = 41, DB = 0
N5.C3.D0.R0.S00: TxDqs: plus1 = 1, minus1 = 0, PI = 43, DB = 0
N7.C2.D0.R1.S13: TxDq : plus1 = 1, minus1 = 0, PI = 40, DB = 0
N1.C2.D0.R1.S14: TxDq : plus1 = 1, minus1 = 0, PI = 08, DB = 1
N5.C3.D0.R0.S00: TxDq : plus1 = 1, minus1 = 0, PI = 08, DB = 1
N7.C2.D0.R1.S14: TxDqs: plus1 = 1, minus1 = 0, PI = 37, DB = 0
N1.C2.D0.R1.S15: TxDqs: plus1 = 1, minus1 = 0, PI = 41, DB = 0
N5.C3.D0.R0.S01: TxDqs: plus1 = 1, minus1 = 0, PI = 27, DB = 0
N7.C2.D0.R1.S14: TxDq : plus1 = 1, minus1 = 0, PI = 03, DB = 1
N1.C2.D0.R1.S15: TxDq : plus1 = 1, minus1 = 0, PI = 09, DB = 1
N5.C3.D0.R0.S01: TxDq : plus1 = 1, minus1 = 0, PI = 57, DB = 1
N7.C2.D0.R1.S15: TxDqs: plus1 = 1, minus1 = 0, PI = 38, DB = 0
N1.C2.D0.R1.S16: TxDqs: plus1 = 1, minus1 = 0, PI = 63, DB = 1
N2.C3: RdCmd2DataValidLatency = 18, (dlyFrmS = 12, clEff = 10, earlyCas = 0, selNTiming = 0)
N5.C3.D0.R0.S02: TxDqs: plus1 = 1, minus1 = 0, PI = 14, DB = 1
N7.C2.D0.R1.S15: TxDq : plus1 = 1, minus1 = 0, PI = 05, DB = 1
N1.C2.D0.R1.S16: TxDq : plus1 = 1, minus1 = 0, PI = 30, DB = 0
N5.C3.D0.R0.S02: TxDq : plus1 = 1, minus1 = 0, PI = 44, DB = 0
N7.C2.D0.R1.S16: TxDqs: plus1 = 1, minus1 = 0, PI = 58, DB = 1
N1.C2.D0.R1.S17: TxDqs: plus1 = 1, minus1 = 0, PI = 28, DB = 0
N5.C3.D0.R0.S03: TxDqs: plus1 = 1, minus1 = 0, PI = 62, DB = 1
N7.C2.D0.R1.S16: TxDq : plus1 = 1, minus1 = 0, PI = 25, DB = 0
N1.C2.D0.R1.S17: TxDq : plus1 = 1, minus1 = 0, PI = 58, DB = 1
N5.C3.D0.R0.S03: TxDq : plus1 = 1, minus1 = 0, PI = 29, DB = 0
N7.C2.D0.R1.S17: TxDqs: plus1 = 1, minus1 = 0, PI = 24, DB = 0
END_DATA_TX_DQ
N5.C3.D0.R0.S04: TxDqs: plus1 = 1, minus1 = 0, PI = 26, DB = 0
N7.C2.D0.R1.S17: TxDq : plus1 = 1, minus1 = 0, PI = 52, DB = 1
N1.C3.D0.R0.S00: wrcmd2dqsstartlatency: 04
N5.C3.D0.R0.S04: TxDq : plus1 = 1, minus1 = 0, PI = 55, DB = 1
END_DATA_TX_DQ
N1.C3.D0.R0.S00: RdPtrOffsetTxDq: 06
N5.C3.D0.R0.S05: TxDqs: plus1 = 1, minus1 = 0, PI = 42, DB = 0
N7.C3.D0.R0.S00: wrcmd2dqsstartlatency: 04
N1.C3.D0.R0.S00: RdPtrOffsetTxDqs: 07
N5.C3.D0.R0.S05: TxDq : plus1 = 1, minus1 = 0, PI = 10, DB = 1
N7.C3.D0.R0.S00: RdPtrOffsetTxDq: 06
N1.C3.D0.R0.S00: PiTxDqs: 40
N5.C3.D0.R0.S06: TxDqs: plus1 = 1, minus1 = 0, PI = 56, DB = 1
N7.C3.D0.R0.S00: RdPtrOffsetTxDqs: 07
N1.C3.D0.R0.S01: wrcmd2dqsstartlatency: 04
N5.C3.D0.R0.S06: TxDq : plus1 = 1, minus1 = 0, PI = 21, DB = 0
N7.C3.D0.R0.S00: PiTxDqs: 47
N1.C3.D0.R0.S01: RdPtrOffsetTxDq: 05
N5.C3.D0.R0.S07: TxDqs: plus1 = 1, minus1 = 0, PI = 09, DB = 1
N7.C3.D0.R0.S01: wrcmd2dqsstartlatency: 04
N1.C3.D0.R0.S01: RdPtrOffsetTxDqs: 07
N5.C3.D0.R0.S07: TxDq : plus1 = 1, minus1 = 0, PI = 38, DB = 0
N7.C3.D0.R0.S01: RdPtrOffsetTxDq: 06
N1.C3.D0.R0.S01: PiTxDqs: 20
N2.C2: RdCmd2DataValidLatency = 17, (dlyFrmS = 11, clEff = 10, earlyCas = 0, selNTiming = 0)
N5.C3.D0.R0.S08: TxDqs: plus1 = 1, minus1 = 0, PI = 44, DB = 0
N7.C3.D0.R0.S01: RdPtrOffsetTxDqs: 07
N1.C3.D0.R0.S02: wrcmd2dqsstartlatency: 04
N5.C3.D0.R0.S08: TxDq : plus1 = 1, minus1 = 0, PI = 10, DB = 1
N7.C3.D0.R0.S01: PiTxDqs: 32
N1.C3.D0.R0.S02: RdPtrOffsetTxDq: 05
N5.C3.D0.R0.S09: TxDqs: plus1 = 1, minus1 = 0, PI = 42, DB = 0
N7.C3.D0.R0.S02: wrcmd2dqsstartlatency: 04
N1.C3.D0.R0.S02: RdPtrOffsetTxDqs: 07
N5.C3.D0.R0.S09: TxDq : plus1 = 1, minus1 = 0, PI = 07, DB = 1
N7.C3.D0.R0.S02: RdPtrOffsetTxDq: 05
N1.C3.D0.R0.S02: PiTxDqs: 10
N5.C3.D0.R0.S10: TxDqs: plus1 = 1, minus1 = 0, PI = 28, DB = 0
N7.C3.D0.R0.S02: RdPtrOffsetTxDqs: 07
N1.C3.D0.R0.S03: wrcmd2dqsstartlatency: 04
N5.C3.D0.R0.S10: TxDq : plus1 = 1, minus1 = 0, PI = 58, DB = 1
N7.C3.D0.R0.S02: PiTxDqs: 18
N1.C3.D0.R0.S03: RdPtrOffsetTxDq: 05
N5.C3.D0.R0.S11: TxDqs: plus1 = 1, minus1 = 0, PI = 15, DB = 1
N7.C3.D0.R0.S03: wrcmd2dqsstartlatency: 04
N1.C3.D0.R0.S03: RdPtrOffsetTxDqs: 06
N5.C3.D0.R0.S11: TxDq : plus1 = 1, minus1 = 0, PI = 47, DB = 0
N7.C3.D0.R0.S03: RdPtrOffsetTxDq: 05
N1.C3.D0.R0.S03: PiTxDqs: 58
N5.C3.D0.R0.S12: TxDqs: plus1 = 1, minus1 = 0, PI = 63, DB = 1
N7.C3.D0.R0.S03: RdPtrOffsetTxDqs: 07
N1.C3.D0.R0.S04: wrcmd2dqsstartlatency: 04
N5.C3.D0.R0.S12: TxDq : plus1 = 1, minus1 = 0, PI = 29, DB = 0
N7.C3.D0.R0.S03: PiTxDqs: 05
N1.C3.D0.R0.S04: RdPtrOffsetTxDq: 04
N5.C3.D0.R0.S13: TxDqs: plus1 = 1, minus1 = 0, PI = 27, DB = 0
N7.C3.D0.R0.S04: wrcmd2dqsstartlatency: 04
N1.C3.D0.R0.S04: RdPtrOffsetTxDqs: 06
N5.C3.D0.R0.S13: TxDq : plus1 = 1, minus1 = 0, PI = 56, DB = 1
N7.C3.D0.R0.S04: RdPtrOffsetTxDq: 04
N1.C3.D0.R0.S04: PiTxDqs: 24
N2.C3: RdCmd2DataValidLatency = 17, (dlyFrmS = 11, clEff = 10, earlyCas = 0, selNTiming = 0)
N5.C3.D0.R0.S14: TxDqs: plus1 = 1, minus1 = 0, PI = 42, DB = 0
N7.C3.D0.R0.S04: RdPtrOffsetTxDqs: 06
N1.C3.D0.R0.S05: wrcmd2dqsstartlatency: 04
N5.C3.D0.R0.S14: TxDq : plus1 = 1, minus1 = 0, PI = 07, DB = 1
N7.C3.D0.R0.S04: PiTxDqs: 32
N1.C3.D0.R0.S05: RdPtrOffsetTxDq: 05
N5.C3.D0.R0.S15: TxDqs: plus1 = 1, minus1 = 0, PI = 56, DB = 1
N7.C3.D0.R0.S05: wrcmd2dqsstartlatency: 04
N1.C3.D0.R0.S05: RdPtrOffsetTxDqs: 06
N5.C3.D0.R0.S15: TxDq : plus1 = 1, minus1 = 0, PI = 22, DB = 0
N7.C3.D0.R0.S05: RdPtrOffsetTxDq: 05
N1.C3.D0.R0.S05: PiTxDqs: 37
N5.C3.D0.R0.S16: TxDqs: plus1 = 1, minus1 = 0, PI = 09, DB = 1
N7.C3.D0.R0.S05: RdPtrOffsetTxDqs: 06
N1.C3.D0.R0.S06: wrcmd2dqsstartlatency: 04
N5.C3.D0.R0.S16: TxDq : plus1 = 1, minus1 = 0, PI = 39, DB = 0
N7.C3.D0.R0.S05: PiTxDqs: 46
N1.C3.D0.R0.S06: RdPtrOffsetTxDq: 05
N5.C3.D0.R0.S17: TxDqs: plus1 = 1, minus1 = 0, PI = 43, DB = 0
N7.C3.D0.R0.S06: wrcmd2dqsstartlatency: 04
N1.C3.D0.R0.S06: RdPtrOffsetTxDqs: 06
N5.C3.D0.R0.S17: TxDq : plus1 = 1, minus1 = 0, PI = 11, DB = 1
N7.C3.D0.R0.S06: RdPtrOffsetTxDq: 05
N1.C3.D0.R0.S06: PiTxDqs: 51
N5.C3.D0.R1.S00: TxDqs: plus1 = 1, minus1 = 0, PI = 43, DB = 0
N7.C3.D0.R0.S06: RdPtrOffsetTxDqs: 06
N1.C3.D0.R0.S07: wrcmd2dqsstartlatency: 04
N5.C3.D0.R1.S00: TxDq : plus1 = 1, minus1 = 0, PI = 08, DB = 1
N7.C3.D0.R0.S06: PiTxDqs: 62
N1.C3.D0.R0.S07: RdPtrOffsetTxDq: 05
N5.C3.D0.R1.S01: TxDqs: plus1 = 1, minus1 = 0, PI = 27, DB = 0
N7.C3.D0.R0.S07: wrcmd2dqsstartlatency: 04
N1.C3.D0.R0.S07: RdPtrOffsetTxDqs: 07
N5.C3.D0.R1.S01: TxDq : plus1 = 1, minus1 = 0, PI = 57, DB = 1
N7.C3.D0.R0.S07: RdPtrOffsetTxDq: 05
N1.C3.D0.R0.S07: PiTxDqs: 05
N5.C3.D0.R1.S02: TxDqs: plus1 = 1, minus1 = 0, PI = 14, DB = 1
N7.C3.D0.R0.S07: RdPtrOffsetTxDqs: 07
N1.C3.D0.R0.S08: wrcmd2dqsstartlatency: 04
N5.C3.D0.R1.S02: TxDq : plus1 = 1, minus1 = 0, PI = 44, DB = 0
N7.C3.D0.R0.S07: PiTxDqs: 14
N1.C3.D0.R0.S08: RdPtrOffsetTxDq: 05
N2.C2: RdCmd2DataValidLatency = 16, (dlyFrmS = 10, clEff = 10, earlyCas = 0, selNTiming = 0)
N5.C3.D0.R1.S03: TxDqs: plus1 = 1, minus1 = 0, PI = 62, DB = 1
N7.C3.D0.R0.S08: wrcmd2dqsstartlatency: 04
N1.C3.D0.R0.S08: RdPtrOffsetTxDqs: 06
N5.C3.D0.R1.S03: TxDq : plus1 = 1, minus1 = 0, PI = 29, DB = 0
N7.C3.D0.R0.S08: RdPtrOffsetTxDq: 05
N1.C3.D0.R0.S08: PiTxDqs: 39
N5.C3.D0.R1.S04: TxDqs: plus1 = 1, minus1 = 0, PI = 26, DB = 0
N7.C3.D0.R0.S08: RdPtrOffsetTxDqs: 06
N1.C3.D0.R0.S09: wrcmd2dqsstartlatency: 04
N5.C3.D0.R1.S04: TxDq : plus1 = 1, minus1 = 0, PI = 55, DB = 1
N7.C3.D0.R0.S08: PiTxDqs: 48
N1.C3.D0.R0.S09: RdPtrOffsetTxDq: 06
N5.C3.D0.R1.S05: TxDqs: plus1 = 1, minus1 = 0, PI = 42, DB = 0
N7.C3.D0.R0.S09: wrcmd2dqsstartlatency: 04
N1.C3.D0.R0.S09: RdPtrOffsetTxDqs: 07
N5.C3.D0.R1.S05: TxDq : plus1 = 1, minus1 = 0, PI = 10, DB = 1
N7.C3.D0.R0.S09: RdPtrOffsetTxDq: 06
N1.C3.D0.R0.S09: PiTxDqs: 39
N5.C3.D0.R1.S06: TxDqs: plus1 = 1, minus1 = 0, PI = 56, DB = 1
N7.C3.D0.R0.S09: RdPtrOffsetTxDqs: 07
N1.C3.D0.R0.S10: wrcmd2dqsstartlatency: 04
N5.C3.D0.R1.S06: TxDq : plus1 = 1, minus1 = 0, PI = 21, DB = 0
N7.C3.D0.R0.S09: PiTxDqs: 47
N1.C3.D0.R0.S10: RdPtrOffsetTxDq: 05
N5.C3.D0.R1.S07: TxDqs: plus1 = 1, minus1 = 0, PI = 09, DB = 1
N7.C3.D0.R0.S10: wrcmd2dqsstartlatency: 04
N1.C3.D0.R0.S10: RdPtrOffsetTxDqs: 07
N5.C3.D0.R1.S07: TxDq : plus1 = 1, minus1 = 0, PI = 38, DB = 0
N7.C3.D0.R0.S10: RdPtrOffsetTxDq: 05
N1.C3.D0.R0.S10: PiTxDqs: 22
N5.C3.D0.R1.S08: TxDqs: plus1 = 1, minus1 = 0, PI = 44, DB = 0
N7.C3.D0.R0.S10: RdPtrOffsetTxDqs: 07
N1.C3.D0.R0.S11: wrcmd2dqsstartlatency: 04
N5.C3.D0.R1.S08: TxDq : plus1 = 1, minus1 = 0, PI = 10, DB = 1
N7.C3.D0.R0.S10: PiTxDqs: 33
N1.C3.D0.R0.S11: RdPtrOffsetTxDq: 05
N2.C3: RdCmd2DataValidLatency = 16, (dlyFrmS = 10, clEff = 10, earlyCas = 0, selNTiming = 0)
N5.C3.D0.R1.S09: TxDqs: plus1 = 1, minus1 = 0, PI = 42, DB = 0
N7.C3.D0.R0.S11: wrcmd2dqsstartlatency: 04
N1.C3.D0.R0.S11: RdPtrOffsetTxDqs: 07
N5.C3.D0.R1.S09: TxDq : plus1 = 1, minus1 = 0, PI = 07, DB = 1
N7.C3.D0.R0.S11: RdPtrOffsetTxDq: 05
N1.C3.D0.R0.S11: PiTxDqs: 10
N5.C3.D0.R1.S10: TxDqs: plus1 = 1, minus1 = 0, PI = 28, DB = 0
N7.C3.D0.R0.S11: RdPtrOffsetTxDqs: 07
N1.C3.D0.R0.S12: wrcmd2dqsstartlatency: 04
N5.C3.D0.R1.S10: TxDq : plus1 = 1, minus1 = 0, PI = 58, DB = 1
N7.C3.D0.R0.S11: PiTxDqs: 21
N1.C3.D0.R0.S12: RdPtrOffsetTxDq: 05
N5.C3.D0.R1.S11: TxDqs: plus1 = 1, minus1 = 0, PI = 15, DB = 1
N7.C3.D0.R0.S12: wrcmd2dqsstartlatency: 04
N1.C3.D0.R0.S12: RdPtrOffsetTxDqs: 06
N5.C3.D0.R1.S11: TxDq : plus1 = 1, minus1 = 0, PI = 47, DB = 0
N7.C3.D0.R0.S12: RdPtrOffsetTxDq: 05
N1.C3.D0.R0.S12: PiTxDqs: 59
N5.C3.D0.R1.S12: TxDqs: plus1 = 1, minus1 = 0, PI = 63, DB = 1
N7.C3.D0.R0.S12: RdPtrOffsetTxDqs: 07
N1.C3.D0.R0.S13: wrcmd2dqsstartlatency: 04
N5.C3.D0.R1.S12: TxDq : plus1 = 1, minus1 = 0, PI = 29, DB = 0
N7.C3.D0.R0.S12: PiTxDqs: 06
N1.C3.D0.R0.S13: RdPtrOffsetTxDq: 04
N5.C3.D0.R1.S13: TxDqs: plus1 = 1, minus1 = 0, PI = 27, DB = 0
N7.C3.D0.R0.S13: wrcmd2dqsstartlatency: 04
N1.C3.D0.R0.S13: RdPtrOffsetTxDqs: 06
N5.C3.D0.R1.S13: TxDq : plus1 = 1, minus1 = 0, PI = 56, DB = 1
N7.C3.D0.R0.S13: RdPtrOffsetTxDq: 04
N1.C3.D0.R0.S13: PiTxDqs: 24
N5.C3.D0.R1.S14: TxDqs: plus1 = 1, minus1 = 0, PI = 42, DB = 0
N7.C3.D0.R0.S13: RdPtrOffsetTxDqs: 06
N1.C3.D0.R0.S14: wrcmd2dqsstartlatency: 04
N5.C3.D0.R1.S14: TxDq : plus1 = 1, minus1 = 0, PI = 07, DB = 1
N7.C3.D0.R0.S13: PiTxDqs: 33
N1.C3.D0.R0.S14: RdPtrOffsetTxDq: 05
N5.C3.D0.R1.S15: TxDqs: plus1 = 1, minus1 = 0, PI = 56, DB = 1
N7.C3.D0.R0.S14: wrcmd2dqsstartlatency: 04
N1.C3.D0.R0.S14: RdPtrOffsetTxDqs: 06
N5.C3.D0.R1.S15: TxDq : plus1 = 1, minus1 = 0, PI = 22, DB = 0
N7.C3.D0.R0.S14: RdPtrOffsetTxDq: 05
N1.C3.D0.R0.S14: PiTxDqs: 36
N2.C2: RdCmd2DataValidLatency = 15, (dlyFrmS = 9, clEff = 10, earlyCas = 0, selNTiming = 0)
N5.C3.D0.R1.S16: TxDqs: plus1 = 1, minus1 = 0, PI = 09, DB = 1
N7.C3.D0.R0.S14: RdPtrOffsetTxDqs: 06
N1.C3.D0.R0.S15: wrcmd2dqsstartlatency: 04
N5.C3.D0.R1.S16: TxDq : plus1 = 1, minus1 = 0, PI = 39, DB = 0
N7.C3.D0.R0.S14: PiTxDqs: 48
N1.C3.D0.R0.S15: RdPtrOffsetTxDq: 05
N5.C3.D0.R1.S17: TxDqs: plus1 = 1, minus1 = 0, PI = 43, DB = 0
N7.C3.D0.R0.S15: wrcmd2dqsstartlatency: 04
N1.C3.D0.R0.S15: RdPtrOffsetTxDqs: 06
N5.C3.D0.R1.S17: TxDq : plus1 = 1, minus1 = 0, PI = 11, DB = 1
N7.C3.D0.R0.S15: RdPtrOffsetTxDq: 05
N1.C3.D0.R0.S15: PiTxDqs: 51
END_DATA_TX_DQ
N7.C3.D0.R0.S15: RdPtrOffsetTxDqs: 06
N1.C3.D0.R0.S16: wrcmd2dqsstartlatency: 04
N5: RunTrainStep: Final status = 0
N7.C3.D0.R0.S15: PiTxDqs: 62
N1.C3.D0.R0.S16: RdPtrOffsetTxDq: 05

END - Basic Write DQ/DQS Training      Time         27003 ms
N7.C3.D0.R0.S16: wrcmd2dqsstartlatency: 04
N1.C3.D0.R0.S16: RdPtrOffsetTxDqs: 07
N5.C0: JCK cmd timing = 1N
N7.C3.D0.R0.S16: RdPtrOffsetTxDq: 05
N1.C3.D0.R0.S16: PiTxDqs: 05
N5.C0: RdCmd2DataValidLatency = 21, (dlyFrmS = 15, clEff = 10, earlyCas = 0, selNTiming = 0)
N7.C3.D0.R0.S16: RdPtrOffsetTxDqs: 07
N1.C3.D0.R0.S17: wrcmd2dqsstartlatency: 04
N5.C1: RdCmd2DataValidLatency = 21, (dlyFrmS = 15, clEff = 10, earlyCas = 0, selNTiming = 0)
N7.C3.D0.R0.S16: PiTxDqs: 13
N1.C3.D0.R0.S17: RdPtrOffsetTxDq: 05
N5.C2: JCK cmd timing = 1N
N7.C3.D0.R0.S17: wrcmd2dqsstartlatency: 04
N1.C3.D0.R0.S17: RdPtrOffsetTxDqs: 06
N5.C2: RdCmd2DataValidLatency = 21, (dlyFrmS = 15, clEff = 10, earlyCas = 0, selNTiming = 0)
N7.C3.D0.R0.S17: RdPtrOffsetTxDq: 05
N1.C3.D0.R0.S17: PiTxDqs: 35
N2.C3: RdCmd2DataValidLatency = 15, (dlyFrmS = 9, clEff = 10, earlyCas = 0, selNTiming = 0)
N5.C3: RdCmd2DataValidLatency = 21, (dlyFrmS = 15, clEff = 10, earlyCas = 0, selNTiming = 0)
N7.C3.D0.R0.S17: RdPtrOffsetTxDqs: 06
N1.C3.D0.R0.S00: RdPtrOffsetTxDq: 07
N5: JckSetOdtDynTiming[2] BL8:
N7.C3.D0.R0.S17: PiTxDqs: 47
N1.C3.D0.R0.S01: RdPtrOffsetTxDq: 06
N7.C3.D0.R0.S00: RdPtrOffsetTxDq: 07
N1.C3.D0.R0.S02: RdPtrOffsetTxDq: 06
N7.C3.D0.R0.S01: RdPtrOffsetTxDq: 07
N1.C3.D0.R0.S03: RdPtrOffsetTxDq: 06
N5.C0: minRcvEnDelay = 199 maxRcvEnDelay = 284 ==> rdwidth = 6 rddly = 2 wrwidth = 6 wrdly = 0
N7.C3.D0.R0.S02: RdPtrOffsetTxDq: 06
N1.C3.D0.R0.S04: RdPtrOffsetTxDq: 05
N5.C1: minRcvEnDelay = 197 maxRcvEnDelay = 315 ==> rdwidth = 6 rddly = 2 wrwidth = 6 wrdly = 0
N7.C3.D0.R0.S03: RdPtrOffsetTxDq: 06
N1.C3.D0.R0.S05: RdPtrOffsetTxDq: 06
N5.C2: minRcvEnDelay = 203 maxRcvEnDelay = 293 ==> rdwidth = 6 rddly = 2 wrwidth = 6 wrdly = 0
N7.C3.D0.R0.S04: RdPtrOffsetTxDq: 05
N1.C3.D0.R0.S06: RdPtrOffsetTxDq: 06
N5.C3: minRcvEnDelay = 196 maxRcvEnDelay = 311 ==> rdwidth = 6 rddly = 2 wrwidth = 6 wrdly = 0
N7.C3.D0.R0.S05: RdPtrOffsetTxDq: 06
N1.C3.D0.R0.S07: RdPtrOffsetTxDq: 06
N5.C0: Memory Electrical TurnAround timings:
N7.C3.D0.R0.S06: RdPtrOffsetTxDq: 06
N1.C3.D0.R0.S08: RdPtrOffsetTxDq: 06
N5.C0:      tCCD  =  0, tWWDR =  3, tRRDD =  2, tWWDD =  3, tWRDR =  1, tWRDR_UPPER =  0, tRRDR =  0
N7.C3.D0.R0.S07: RdPtrOffsetTxDq: 06
N1.C3.D0.R0.S09: RdPtrOffsetTxDq: 07
N5.C0:      tRWDD =  2, tRWDR =  2, tWRDD =  1, tRWSR =  2
N7.C3.D0.R0.S08: RdPtrOffsetTxDq: 06
N1.C3.D0.R0.S10: RdPtrOffsetTxDq: 06
N5.C0: TCOTHP: T_RWSR = 0x2, T_RWDD = 0x2
N7.C3.D0.R0.S09: RdPtrOffsetTxDq: 07
N1.C3.D0.R0.S11: RdPtrOffsetTxDq: 06
N5.C0:      tCCD_WR =  0, tWRDS =  2, tRWDS =  2, tWWDS =  3, tRRDS =  1
N7.C3.D0.R0.S10: RdPtrOffsetTxDq: 06
N1.C3.D0.R0.S12: RdPtrOffsetTxDq: 06
N5.C1: Memory Electrical TurnAround timings:
N7.C3.D0.R0.S11: RdPtrOffsetTxDq: 06
N1.C3.D0.R0.S13: RdPtrOffsetTxDq: 05
N2.C2: RdCmd2DataValidLatency = 14, (dlyFrmS = 8, clEff = 10, earlyCas = 0, selNTiming = 0)
N5.C1:      tCCD  =  0, tWWDR =  3, tRRDD =  2, tWWDD =  3, tWRDR =  1, tWRDR_UPPER =  0, tRRDR =  0
N7.C3.D0.R0.S12: RdPtrOffsetTxDq: 06
N1.C3.D0.R0.S14: RdPtrOffsetTxDq: 06
N5.C1:      tRWDD =  2, tRWDR =  2, tWRDD =  1, tRWSR =  2
N7.C3.D0.R0.S13: RdPtrOffsetTxDq: 05
N1.C3.D0.R0.S15: RdPtrOffsetTxDq: 06
N5.C1: TCOTHP: T_RWSR = 0x2, T_RWDD = 0x2
N7.C3.D0.R0.S14: RdPtrOffsetTxDq: 06
N1.C3.D0.R0.S16: RdPtrOffsetTxDq: 06
N5.C1:      tCCD_WR =  0, tWRDS =  2, tRWDS =  2, tWWDS =  3, tRRDS =  1
N7.C3.D0.R0.S15: RdPtrOffsetTxDq: 06
N1.C3.D0.R0.S17: RdPtrOffsetTxDq: 06
N5.C2: Memory Electrical TurnAround timings:
N7.C3.D0.R0.S16: RdPtrOffsetTxDq: 06
N1.C3.D0.R0.S00: RdPtrOffsetTxDq: 08
N5.C2:      tCCD  =  0, tWWDR =  3, tRRDD =  2, tWWDD =  3, tWRDR =  1, tWRDR_UPPER =  0, tRRDR =  0
N7.C3.D0.R0.S17: RdPtrOffsetTxDq: 06
N1.C3.D0.R0.S01: RdPtrOffsetTxDq: 07
N5.C2:      tRWDD =  2, tRWDR =  2, tWRDD =  1, tRWSR =  2
N7.C3.D0.R0.S00: RdPtrOffsetTxDq: 08
N1.C3.D0.R0.S02: RdPtrOffsetTxDq: 07
N5.C2: TCOTHP: T_RWSR = 0x2, T_RWDD = 0x2
N7.C3.D0.R0.S01: RdPtrOffsetTxDq: 08
N1.C3.D0.R0.S03: RdPtrOffsetTxDq: 07
N5.C2:      tCCD_WR =  0, tWRDS =  2, tRWDS =  2, tWWDS =  3, tRRDS =  1
N7.C3.D0.R0.S02: RdPtrOffsetTxDq: 07
N1.C3.D0.R0.S04: RdPtrOffsetTxDq: 06
N5.C3: Memory Electrical TurnAround timings:
N7.C3.D0.R0.S03: RdPtrOffsetTxDq: 07
N1.C3.D0.R0.S05: RdPtrOffsetTxDq: 07
N5.C3:      tCCD  =  0, tWWDR =  3, tRRDD =  2, tWWDD =  3, tWRDR =  1, tWRDR_UPPER =  0, tRRDR =  0
N7.C3.D0.R0.S04: RdPtrOffsetTxDq: 06
N1.C3.D0.R0.S06: RdPtrOffsetTxDq: 07
N2.C3: RdCmd2DataValidLatency = 14, (dlyFrmS = 8, clEff = 10, earlyCas = 0, selNTiming = 0)
N5.C3:      tRWDD =  2, tRWDR =  2, tWRDD =  1, tRWSR =  2
N7.C3.D0.R0.S05: RdPtrOffsetTxDq: 07
N1.C3.D0.R0.S07: RdPtrOffsetTxDq: 07
N5.C3: TCOTHP: T_RWSR = 0x2, T_RWDD = 0x2
N7.C3.D0.R0.S06: RdPtrOffsetTxDq: 07
N1.C3.D0.R0.S08: RdPtrOffsetTxDq: 07
N5.C3:      tCCD_WR =  0, tWRDS =  2, tRWDS =  2, tWWDS =  3, tRRDS =  1
N7.C3.D0.R0.S07: RdPtrOffsetTxDq: 07
N1.C3.D0.R0.S09: RdPtrOffsetTxDq: 08

START - Rd Timing Centering 2D Training
N7.C3.D0.R0.S08: RdPtrOffsetTxDq: 07
N1.C3.D0.R0.S10: RdPtrOffsetTxDq: 07
N5: 

Adv Strobe Centering(MARGIN_RX_DQ): GetMultiVref: patternLength = 13, stepSize = 1, numPoints = 1
N7.C3.D0.R0.S09: RdPtrOffsetTxDq: 08
N1.C3.D0.R0.S11: RdPtrOffsetTxDq: 07
N5: GetMargins: Level = 1, group = 11, mode = 0, scope = 4
N7.C3.D0.R0.S10: RdPtrOffsetTxDq: 07
N1.C3.D0.R0.S12: RdPtrOffsetTxDq: 07
N7.C3.D0.R0.S11: RdPtrOffsetTxDq: 07
N1.C3.D0.R0.S13: RdPtrOffsetTxDq: 06
N7.C3.D0.R0.S12: RdPtrOffsetTxDq: 07
N1.C3.D0.R0.S14: RdPtrOffsetTxDq: 07
N7.C3.D0.R0.S13: RdPtrOffsetTxDq: 06
N1.C3.D0.R0.S15: RdPtrOffsetTxDq: 07
N7.C3.D0.R0.S14: RdPtrOffsetTxDq: 07
N1.C3.D0.R0.S16: RdPtrOffsetTxDq: 07
N7.C3.D0.R0.S15: RdPtrOffsetTxDq: 07
N1.C3.D0.R0.S17: RdPtrOffsetTxDq: 07
N7.C3.D0.R0.S16: RdPtrOffsetTxDq: 07
N1.C3.D0.R0.S00: Total Delay in PI ticks: TxDQ = 965
N7.C3.D0.R0.S17: RdPtrOffsetTxDq: 07
N1.C3.D0.R0.S01: Total Delay in PI ticks: TxDQ = 948
N7.C3.D0.R0.S00: Total Delay in PI ticks: TxDQ = 973
N1.C3.D0.R0.S02: Total Delay in PI ticks: TxDQ = 937
N7.C3.D0.R0.S01: Total Delay in PI ticks: TxDQ = 957
N1.C3.D0.R0.S03: Total Delay in PI ticks: TxDQ = 919
N7.C3.D0.R0.S02: Total Delay in PI ticks: TxDQ = 945
N1.C3.D0.R0.S04: Total Delay in PI ticks: TxDQ = 886
N7.C3.D0.R0.S03: Total Delay in PI ticks: TxDQ = 931
N1.C3.D0.R0.S05: Total Delay in PI ticks: TxDQ = 899
N2.C2: RdCmd2DataValidLatency = 16, (dlyFrmS = 10, clEff = 10, earlyCas = 0, selNTiming = 0)
N7.C3.D0.R0.S04: Total Delay in PI ticks: TxDQ = 893
N1.C3.D0.R0.S06: Total Delay in PI ticks: TxDQ = 912
N7.C3.D0.R0.S05: Total Delay in PI ticks: TxDQ = 909
N1.C3.D0.R0.S07: Total Delay in PI ticks: TxDQ = 930
N7.C3.D0.R0.S06: Total Delay in PI ticks: TxDQ = 922
N1.C3.D0.R0.S08: Total Delay in PI ticks: TxDQ = 901
N7.C3.D0.R0.S07: Total Delay in PI ticks: TxDQ = 938
N1.C3.D0.R0.S09: Total Delay in PI ticks: TxDQ = 963
N7.C3.D0.R0.S08: Total Delay in PI ticks: TxDQ = 910
N1.C3.D0.R0.S10: Total Delay in PI ticks: TxDQ = 948
N7.C3.D0.R0.S09: Total Delay in PI ticks: TxDQ = 973
N1.C3.D0.R0.S11: Total Delay in PI ticks: TxDQ = 937
N7.C3.D0.R0.S10: Total Delay in PI ticks: TxDQ = 958
N1.C3.D0.R0.S12: Total Delay in PI ticks: TxDQ = 921
N7.C3.D0.R0.S11: Total Delay in PI ticks: TxDQ = 948
N1.C3.D0.R0.S13: Total Delay in PI ticks: TxDQ = 885
N7.C3.D0.R0.S12: Total Delay in PI ticks: TxDQ = 931
N1.C3.D0.R0.S14: Total Delay in PI ticks: TxDQ = 898
N7.C3.D0.R0.S13: Total Delay in PI ticks: TxDQ = 894
N1.C3.D0.R0.S15: Total Delay in PI ticks: TxDQ = 914
N7.C3.D0.R0.S14: Total Delay in PI ticks: TxDQ = 910
N1.C3.D0.R0.S16: Total Delay in PI ticks: TxDQ = 932
N7.C3.D0.R0.S15: Total Delay in PI ticks: TxDQ = 925
N1.C3.D0.R0.S17: Total Delay in PI ticks: TxDQ = 897
N7.C3.D0.R0.S16: Total Delay in PI ticks: TxDQ = 939
N1.C3.D0.R1.S00: wrcmd2dqsstartlatency: 04
N7.C3.D0.R0.S17: Total Delay in PI ticks: TxDQ = 910
N1.C3.D0.R1.S00: RdPtrOffsetTxDq: 06
N7.C3.D0.R1.S00: wrcmd2dqsstartlatency: 04
N1.C3.D0.R1.S00: RdPtrOffsetTxDqs: 07
N2.C3: RdCmd2DataValidLatency = 16, (dlyFrmS = 10, clEff = 10, earlyCas = 0, selNTiming = 0)
N7.C3.D0.R1.S00: RdPtrOffsetTxDq: 06
N1.C3.D0.R1.S00: PiTxDqs: 40
N7.C3.D0.R1.S00: RdPtrOffsetTxDqs: 07
N1.C3.D0.R1.S01: wrcmd2dqsstartlatency: 04
N7.C3.D0.R1.S00: PiTxDqs: 47
N1.C3.D0.R1.S01: RdPtrOffsetTxDq: 05
N7.C3.D0.R1.S01: wrcmd2dqsstartlatency: 04
N1.C3.D0.R1.S01: RdPtrOffsetTxDqs: 07
N7.C3.D0.R1.S01: RdPtrOffsetTxDq: 05
N1.C3.D0.R1.S01: PiTxDqs: 19
N7.C3.D0.R1.S01: RdPtrOffsetTxDqs: 07
N1.C3.D0.R1.S02: wrcmd2dqsstartlatency: 04
N7.C3.D0.R1.S01: PiTxDqs: 30
N1.C3.D0.R1.S02: RdPtrOffsetTxDq: 05
N7.C3.D0.R1.S02: wrcmd2dqsstartlatency: 04
N1.C3.D0.R1.S02: RdPtrOffsetTxDqs: 07
N7.C3.D0.R1.S02: RdPtrOffsetTxDq: 05
N1.C3.D0.R1.S02: PiTxDqs: 08
N7.C3.D0.R1.S02: RdPtrOffsetTxDqs: 07
N1.C3.D0.R1.S03: wrcmd2dqsstartlatency: 04
N7.C3.D0.R1.S02: PiTxDqs: 18
N1.C3.D0.R1.S03: RdPtrOffsetTxDq: 05
N7.C3.D0.R1.S03: wrcmd2dqsstartlatency: 04
N1.C3.D0.R1.S03: RdPtrOffsetTxDqs: 06
N7.C3.D0.R1.S03: RdPtrOffsetTxDq: 05
N1.C3.D0.R1.S03: PiTxDqs: 58
N7.C3.D0.R1.S03: RdPtrOffsetTxDqs: 07
N1.C3.D0.R1.S04: wrcmd2dqsstartlatency: 04
N7.C3.D0.R1.S03: PiTxDqs: 05
N1.C3.D0.R1.S04: RdPtrOffsetTxDq: 04
N7.C3.D0.R1.S04: wrcmd2dqsstartlatency: 04
N1.C3.D0.R1.S04: RdPtrOffsetTxDqs: 06
N7.C3.D0.R1.S04: RdPtrOffsetTxDq: 04
N1.C3.D0.R1.S04: PiTxDqs: 23
N7.C3.D0.R1.S04: RdPtrOffsetTxDqs: 06
N1.C3.D0.R1.S05: wrcmd2dqsstartlatency: 04
N7.C3.D0.R1.S04: PiTxDqs: 33
N1.C3.D0.R1.S05: RdPtrOffsetTxDq: 05
N7.C3.D0.R1.S05: wrcmd2dqsstartlatency: 04
N1.C3.D0.R1.S05: RdPtrOffsetTxDqs: 06
N7.C3.D0.R1.S05: RdPtrOffsetTxDq: 05
N1.C3.D0.R1.S05: PiTxDqs: 35
N7.C3.D0.R1.S05: RdPtrOffsetTxDqs: 06
N1.C3.D0.R1.S06: wrcmd2dqsstartlatency: 04
N2.C2: AdjustTotalRoundTripTime: SUCCESS - worst rank = 0, host round trip = 73, MXB cmd2dat = 10
START_DATA_RX_DQS_ADV
Results for N5.C0.D0.R0: 
           0   1   2   3   4   5   6   7   8   9  10  11  12  13  14  15  16  17
-------------------------------------------------------------------------------
Vref offset: 0
Left:    -24 -23 -25 -25 -20 -22 -24 -21 -23 -25 -20 -24 -23 -20 -21 -22 -22 -23
Right:    24  24  24  28  22  19  24  22  21  20  23  23  23  21  20  23  22  17
-------------------------------------------------------------------------------
Prev Pi:  33  34  36  34  28  32  31  30  33  35  33  33  33  28  30  30  31  33
New Pi:   33  34  36  35  29  31  31  30  32  33  34  33  33  28  30  30  31  30
Diff:      0   0   0   1   1  -1   0   0  -1  -2   1   0   0   0   0   0   0  -3

Results for N5.C0.D0.R1: 
           0   1   2   3   4   5   6   7   8   9  10  11  12  13  14  15  16  17
-------------------------------------------------------------------------------
Vref offset: 0
Left:    -24 -24 -25 -25 -21 -21 -24 -21 -23 -26 -20 -24 -23 -20 -21 -22 -22 -24
Right:    24  25  24  25  22  19  23  23  24  21  23  24  27  21  20  22  24  19
-------------------------------------------------------------------------------
Prev Pi:  33  34  36  34  28  32  31  30  33  35  33  33  33  28  30  30  31  33
New Pi:   33  34  36  34  28  31  31  31  33  33  34  33  35  28  30  30  32  31
Diff:      0   0   0   0   0  -1   0   1   0  -2   1   0   2   0   0   0   1  -2

Results for N5.C1.D0.R0: 
           0   1   2   3   4   5   6   7   8   9  10  11  12  13  14  15  16  17
-------------------------------------------------------------------------------
Vref offset: 0
Left:    -24 -24 -24 -23 -24 -22 -21 -20 -20 -24 -23 -23 -24 -22 -19 -23 -22 -17
Right:    21  22  21  23  23  25  23  22  23  21  25  22  22  21  20  24  23  22
-------------------------------------------------------------------------------
Prev Pi:  31  34  32  30  32  31  30  31  31  34  31  31  31  31  31  33  32  28
New Pi:   30  33  31  30  32  32  31  32  32  33  32  31  30  31  31  33  32  30
Diff:     -1  -1  -1   0   0   1   1   1   1  -1   1   0  -1   0   0   0   0   2

Results for N5.C1.D0.R1: 
           0   1   2   3   4   5   6   7   8   9  10  11  12  13  14  15  16  17
-------------------------------------------------------------------------------
Vref offset: 0
Left:    -24 -24 -24 -23 -24 -21 -21 -20 -20 -24 -23 -22 -23 -22 -18 -24 -22 -17
Right:    22  23  24  25  21  25  20  24  21  23  24  24  21  21  19  24  23  20
-------------------------------------------------------------------------------
Prev Pi:  31  34  32  30  32  31  30  31  31  34  31  31  31  31  31  33  32  28
New Pi:   30  34  32  31  31  33  30  33  31  34  31  32  30  31  31  33  32  29
Diff:     -1   0   0   1  -1   2   0   2   0   0   0   1  -1   0   0   0   0   1

Results for N5.C2.D0.R0: 
           0   1   2   3   4   5   6   7   8   9  10  11  12  13  14  15  16  17
-------------------------------------------------------------------------------
Vref offset: 0
Left:    -23 -21 -24 -21 -25 -25 -23 -21 -25 -26 -20 -23 -26 -26 -23 -22 -21 -22
Right:    26  29  24  30  27  28  26  31  28  31  26  27  30  30  27  27  27  24
-------------------------------------------------------------------------------
Prev Pi:  33  34  33  34  34  37  33  34  34  35  32  35  36  33  34  34  33  34
New Pi:   34  38  33  38  35  38  34  39  35  37  35  37  38  35  36  36  36  35
Diff:      1   4   0   4   1   1   1   5   1   2   3   2   2   2   2   2   3   1

Results for N5.C2.D0.R1: 
           0   1   2   3   4   5   6   7   8   9  10  11  12  13  14  15  16  17
-------------------------------------------------------------------------------
Vref offset: 0
Left:    -23 -22 -23 -22 -25 -25 -23 -22 -25 -26 -20 -24 -27 -25 -23 -22 -21 -23
Right:    25  30  24  30  30  29  27  31  26  31  29  25  30  30  25  29  26  26
-------------------------------------------------------------------------------
Prev Pi:  33  34  33  34  34  37  33  34  34  35  32  35  36  33  34  34  33  34
New Pi:   34  38  33  38  36  39  35  38  34  37  36  35  37  35  35  37  35  35
Diff:      1   4   0   4   2   2   2   4   0   2   4   0   1   2   1   3   2   1

Results for N5.C3.D0.R0: 
           0   1   2   3   4   5   6   7   8   9  10  11  12  13  14  15  16  17
-------------------------------------------------------------------------------
Vref offset: 0
Left:    -26 -23 -21 -23 -24 -23 -20 -24 -24 -23 -24 -24 -24 -21 -24 -24 -23 -25
Right:    30  29  31  31  31  27  25  25  28  28  30  25  31  30  25  29  28  27
-------------------------------------------------------------------------------
Prev Pi:  35  33  34  34  35  34  34  35  34  36  33  33  34  34  33  34  33  35
New Pi:   37  36  39  38  38  36  36  35  36  38  36  33  37  38  33  36  35  36
Diff:      2   3   5   4   3   2   2   0   2   2   3   0   3   4   0   2   2   1

Results for N5.C3.D0.R1: 
           0   1   2   3   4   5   6   7   8   9  10  11  12  13  14  15  16  17
-------------------------------------------------------------------------------
Vref offset: 0
Left:    -26 -23 -20 -22 -24 -24 -20 -25 -24 -23 -24 -24 -23 -21 -24 -24 -21 -26
Right:    31  28  31  31  31  26  25  28  29  29  28  29  31  30  26  27  25  26
-------------------------------------------------------------------------------
Prev Pi:  35  33  34  34  35  34  34  35  34  36  33  33  34  34  33  34  33  35
New Pi:   37  35  39  38  38  35  36  36  36  39  35  35  38  38  34  35  35  35
Diff:      2   2   5   4   3   1   2   1   2   3   2   2   4   4   1   1   2   0

STOP_DATA_RX_DQS_ADV
N7.C3.D0.R1.S05: PiTxDqs: 47
N1.C3.D0.R1.S06: RdPtrOffsetTxDq: 05
N3.C0.D0: CheckRankPopLocal: dimmPresent: 1, numRanks = 2
N5: RunTrainStep: Final status = 0
N7.C3.D0.R1.S06: wrcmd2dqsstartlatency: 04
N1.C3.D0.R1.S06: RdPtrOffsetTxDqs: 06
N3.C0.D0.R0: CheckRankPopLocal: mapOut: 0, enabled = 1

END - Rd Timing Centering 2D Training  Time         1230 ms
N7.C3.D0.R1.S06: RdPtrOffsetTxDq: 05
N1.C3.D0.R1.S06: PiTxDqs: 51
N3.C0.D0.R1: CheckRankPopLocal: mapOut: 0, enabled = 1

START - Wr Timing Centering 2D Training
N7.C3.D0.R1.S06: RdPtrOffsetTxDqs: 06
N1.C3.D0.R1.S07: wrcmd2dqsstartlatency: 04
N3.C0.D1: CheckRankPopLocal: dimmPresent: 0, numRanks = 0
N5: 

Adv Strobe Centering(MARGIN_TX_DQ): GetMultiVref: patternLength = 13, stepSize = 1, numPoints = 1
N7.C3.D0.R1.S06: PiTxDqs: 61
N1.C3.D0.R1.S07: RdPtrOffsetTxDq: 05
N3.C0.D2: CheckRankPopLocal: dimmPresent: 0, numRanks = 0
N5: GetMargins: Level = 1, group = 12, mode = 0, scope = 4
N7.C3.D0.R1.S07: wrcmd2dqsstartlatency: 04
N1.C3.D0.R1.S07: RdPtrOffsetTxDqs: 07
N3.C0.D0: CheckRankPopLocal: amap: 0x00000000
N7.C3.D0.R1.S07: RdPtrOffsetTxDq: 05
N1.C3.D0.R1.S07: PiTxDqs: 03
N3.C0.D1: CheckRankPopLocal: amap: 0x00000000
N7.C3.D0.R1.S07: RdPtrOffsetTxDqs: 07
N1.C3.D0.R1.S08: wrcmd2dqsstartlatency: 04
N3.C0.D2: CheckRankPopLocal: amap: 0x00000000
N7.C3.D0.R1.S07: PiTxDqs: 14
N1.C3.D0.R1.S08: RdPtrOffsetTxDq: 05
N3.C1.D0: CheckRankPopLocal: dimmPresent: 1, numRanks = 2
N7.C3.D0.R1.S08: wrcmd2dqsstartlatency: 04
N1.C3.D0.R1.S08: RdPtrOffsetTxDqs: 06
N3.C1.D0.R0: CheckRankPopLocal: mapOut: 0, enabled = 1
N7.C3.D0.R1.S08: RdPtrOffsetTxDq: 05
N1.C3.D0.R1.S08: PiTxDqs: 35
N3.C1.D0.R1: CheckRankPopLocal: mapOut: 0, enabled = 1
N7.C3.D0.R1.S08: RdPtrOffsetTxDqs: 06
N1.C3.D0.R1.S09: wrcmd2dqsstartlatency: 04
N3.C1.D1: CheckRankPopLocal: dimmPresent: 0, numRanks = 0
N7.C3.D0.R1.S08: PiTxDqs: 47
N1.C3.D0.R1.S09: RdPtrOffsetTxDq: 06
N3.C1.D2: CheckRankPopLocal: dimmPresent: 0, numRanks = 0
N7.C3.D0.R1.S09: wrcmd2dqsstartlatency: 04
N1.C3.D0.R1.S09: RdPtrOffsetTxDqs: 07
N3.C1.D0: CheckRankPopLocal: amap: 0x00000000
N7.C3.D0.R1.S09: RdPtrOffsetTxDq: 06
N1.C3.D0.R1.S09: PiTxDqs: 38
N3.C1.D1: CheckRankPopLocal: amap: 0x00000000
N7.C3.D0.R1.S09: RdPtrOffsetTxDqs: 07
N1.C3.D0.R1.S10: wrcmd2dqsstartlatency: 04
N3.C1.D2: CheckRankPopLocal: amap: 0x00000000
N7.C3.D0.R1.S09: PiTxDqs: 45
N1.C3.D0.R1.S10: RdPtrOffsetTxDq: 05
N3.C2.D0: CheckRankPopLocal: dimmPresent: 1, numRanks = 2
N7.C3.D0.R1.S10: wrcmd2dqsstartlatency: 04
N1.C3.D0.R1.S10: RdPtrOffsetTxDqs: 07
N3.C2.D0.R0: CheckRankPopLocal: mapOut: 0, enabled = 1
N7.C3.D0.R1.S10: RdPtrOffsetTxDq: 05
N1.C3.D0.R1.S10: PiTxDqs: 21
N3.C2.D0.R1: CheckRankPopLocal: mapOut: 0, enabled = 1
N7.C3.D0.R1.S10: RdPtrOffsetTxDqs: 07
N1.C3.D0.R1.S11: wrcmd2dqsstartlatency: 04
N3.C2.D1: CheckRankPopLocal: dimmPresent: 0, numRanks = 0
N7.C3.D0.R1.S10: PiTxDqs: 31
N1.C3.D0.R1.S11: RdPtrOffsetTxDq: 05
N3.C2.D2: CheckRankPopLocal: dimmPresent: 0, numRanks = 0
N7.C3.D0.R1.S11: wrcmd2dqsstartlatency: 04
N1.C3.D0.R1.S11: RdPtrOffsetTxDqs: 07
N3.C2.D0: CheckRankPopLocal: amap: 0x00000000
N7.C3.D0.R1.S11: RdPtrOffsetTxDq: 05
N1.C3.D0.R1.S11: PiTxDqs: 10
N3.C2.D1: CheckRankPopLocal: amap: 0x00000000
N7.C3.D0.R1.S11: RdPtrOffsetTxDqs: 07
N1.C3.D0.R1.S12: wrcmd2dqsstartlatency: 04
N3.C2.D2: CheckRankPopLocal: amap: 0x00000000
N7.C3.D0.R1.S11: PiTxDqs: 20
N1.C3.D0.R1.S12: RdPtrOffsetTxDq: 05
N3.C3.D0: CheckRankPopLocal: dimmPresent: 1, numRanks = 2
N7.C3.D0.R1.S12: wrcmd2dqsstartlatency: 04
N1.C3.D0.R1.S12: RdPtrOffsetTxDqs: 06
N3.C3.D0.R0: CheckRankPopLocal: mapOut: 0, enabled = 1
N7.C3.D0.R1.S12: RdPtrOffsetTxDq: 05
N1.C3.D0.R1.S12: PiTxDqs: 58
N3.C3.D0.R1: CheckRankPopLocal: mapOut: 0, enabled = 1
N7.C3.D0.R1.S12: RdPtrOffsetTxDqs: 07
N1.C3.D0.R1.S13: wrcmd2dqsstartlatency: 04
N3.C3.D1: CheckRankPopLocal: dimmPresent: 0, numRanks = 0
N7.C3.D0.R1.S12: PiTxDqs: 05
N1.C3.D0.R1.S13: RdPtrOffsetTxDq: 04
N3.C3.D2: CheckRankPopLocal: dimmPresent: 0, numRanks = 0
N7.C3.D0.R1.S13: wrcmd2dqsstartlatency: 04
N1.C3.D0.R1.S13: RdPtrOffsetTxDqs: 06
N3.C3.D0: CheckRankPopLocal: amap: 0x00000000
N7.C3.D0.R1.S13: RdPtrOffsetTxDq: 04
N1.C3.D0.R1.S13: PiTxDqs: 25
N3.C3.D1: CheckRankPopLocal: amap: 0x00000000
N7.C3.D0.R1.S13: RdPtrOffsetTxDqs: 06
N1.C3.D0.R1.S14: wrcmd2dqsstartlatency: 04
N3.C3.D2: CheckRankPopLocal: amap: 0x00000000
N7.C3.D0.R1.S13: PiTxDqs: 34
N1.C3.D0.R1.S14: RdPtrOffsetTxDq: 05
N3.C0: AdjustTotalRoundTripTime
N7.C3.D0.R1.S14: wrcmd2dqsstartlatency: 04
N1.C3.D0.R1.S14: RdPtrOffsetTxDqs: 06
N3.C0: AdjustTotalRoundTripTime: worstRank = 0
N7.C3.D0.R1.S14: RdPtrOffsetTxDq: 05
N1.C3.D0.R1.S14: PiTxDqs: 35
N3.C0: AdjustTotalRoundTripTime: worstRank dimm = 0, rank = 0
N7.C3.D0.R1.S14: RdPtrOffsetTxDqs: 06
N1.C3.D0.R1.S15: wrcmd2dqsstartlatency: 04
N3.C1: AdjustTotalRoundTripTime: worstRank dimm = 0, rank = 0
N7.C3.D0.R1.S14: PiTxDqs: 47
N1.C3.D0.R1.S15: RdPtrOffsetTxDq: 05
N3.C0: AdjustTotalRoundTripTime: ddrChMask = 0x3
N7.C3.D0.R1.S15: wrcmd2dqsstartlatency: 04
N1.C3.D0.R1.S15: RdPtrOffsetTxDqs: 06
N7.C3.D0.R1.S15: RdPtrOffsetTxDq: 05
N1.C3.D0.R1.S15: PiTxDqs: 53
N7.C3.D0.R1.S15: RdPtrOffsetTxDqs: 06
N1.C3.D0.R1.S16: wrcmd2dqsstartlatency: 04
N3.C0: RdCmd2DataValidLatency = 20, (dlyFrmS = 14, clEff = 10, earlyCas = 0, selNTiming = 0)
N7.C3.D0.R1.S15: PiTxDqs: 61
N1.C3.D0.R1.S16: RdPtrOffsetTxDq: 05
N7.C3.D0.R1.S16: wrcmd2dqsstartlatency: 04
N1.C3.D0.R1.S16: RdPtrOffsetTxDqs: 07
N7.C3.D0.R1.S16: RdPtrOffsetTxDq: 05
N1.C3.D0.R1.S16: PiTxDqs: 03
N7.C3.D0.R1.S16: RdPtrOffsetTxDqs: 07
N1.C3.D0.R1.S17: wrcmd2dqsstartlatency: 04
N7.C3.D0.R1.S16: PiTxDqs: 13
N1.C3.D0.R1.S17: RdPtrOffsetTxDq: 05
N7.C3.D0.R1.S17: wrcmd2dqsstartlatency: 04
N1.C3.D0.R1.S17: RdPtrOffsetTxDqs: 06
N7.C3.D0.R1.S17: RdPtrOffsetTxDq: 05
N1.C3.D0.R1.S17: PiTxDqs: 37
N7.C3.D0.R1.S17: RdPtrOffsetTxDqs: 06
N1.C3.D0.R1.S00: RdPtrOffsetTxDq: 07
N7.C3.D0.R1.S17: PiTxDqs: 47
N1.C3.D0.R1.S01: RdPtrOffsetTxDq: 06
N7.C3.D0.R1.S00: RdPtrOffsetTxDq: 07
N1.C3.D0.R1.S02: RdPtrOffsetTxDq: 06
N7.C3.D0.R1.S01: RdPtrOffsetTxDq: 06
N1.C3.D0.R1.S03: RdPtrOffsetTxDq: 06
N7.C3.D0.R1.S02: RdPtrOffsetTxDq: 06
N1.C3.D0.R1.S04: RdPtrOffsetTxDq: 05
N7.C3.D0.R1.S03: RdPtrOffsetTxDq: 06
N1.C3.D0.R1.S05: RdPtrOffsetTxDq: 06
N7.C3.D0.R1.S04: RdPtrOffsetTxDq: 05
N1.C3.D0.R1.S06: RdPtrOffsetTxDq: 06
N7.C3.D0.R1.S05: RdPtrOffsetTxDq: 06
N1.C3.D0.R1.S07: RdPtrOffsetTxDq: 06
N7.C3.D0.R1.S06: RdPtrOffsetTxDq: 06
N1.C3.D0.R1.S08: RdPtrOffsetTxDq: 06
N7.C3.D0.R1.S07: RdPtrOffsetTxDq: 06
N1.C3.D0.R1.S09: RdPtrOffsetTxDq: 07
N7.C3.D0.R1.S08: RdPtrOffsetTxDq: 06
N1.C3.D0.R1.S10: RdPtrOffsetTxDq: 06
N7.C3.D0.R1.S09: RdPtrOffsetTxDq: 07
N1.C3.D0.R1.S11: RdPtrOffsetTxDq: 06
N7.C3.D0.R1.S10: RdPtrOffsetTxDq: 06
N1.C3.D0.R1.S12: RdPtrOffsetTxDq: 06
N7.C3.D0.R1.S11: RdPtrOffsetTxDq: 06
N1.C3.D0.R1.S13: RdPtrOffsetTxDq: 05
N3.C1: RdCmd2DataValidLatency = 20, (dlyFrmS = 14, clEff = 10, earlyCas = 0, selNTiming = 0)
N7.C3.D0.R1.S12: RdPtrOffsetTxDq: 06
N1.C3.D0.R1.S14: RdPtrOffsetTxDq: 06
N7.C3.D0.R1.S13: RdPtrOffsetTxDq: 05
N1.C3.D0.R1.S15: RdPtrOffsetTxDq: 06
N7.C3.D0.R1.S14: RdPtrOffsetTxDq: 06
N1.C3.D0.R1.S16: RdPtrOffsetTxDq: 06
N7.C3.D0.R1.S15: RdPtrOffsetTxDq: 06
N1.C3.D0.R1.S17: RdPtrOffsetTxDq: 06
N7.C3.D0.R1.S16: RdPtrOffsetTxDq: 06
N1.C3.D0.R1.S00: RdPtrOffsetTxDq: 08
N7.C3.D0.R1.S17: RdPtrOffsetTxDq: 06
N1.C3.D0.R1.S01: RdPtrOffsetTxDq: 07
N7.C3.D0.R1.S00: RdPtrOffsetTxDq: 08
N1.C3.D0.R1.S02: RdPtrOffsetTxDq: 07
N7.C3.D0.R1.S01: RdPtrOffsetTxDq: 07
N1.C3.D0.R1.S03: RdPtrOffsetTxDq: 07
N7.C3.D0.R1.S02: RdPtrOffsetTxDq: 07
N1.C3.D0.R1.S04: RdPtrOffsetTxDq: 06
N7.C3.D0.R1.S03: RdPtrOffsetTxDq: 07
N1.C3.D0.R1.S05: RdPtrOffsetTxDq: 07
N7.C3.D0.R1.S04: RdPtrOffsetTxDq: 06
N1.C3.D0.R1.S06: RdPtrOffsetTxDq: 07
N7.C3.D0.R1.S05: RdPtrOffsetTxDq: 07
N1.C3.D0.R1.S07: RdPtrOffsetTxDq: 07
N7.C3.D0.R1.S06: RdPtrOffsetTxDq: 07
N1.C3.D0.R1.S08: RdPtrOffsetTxDq: 07
N7.C3.D0.R1.S07: RdPtrOffsetTxDq: 07
N1.C3.D0.R1.S09: RdPtrOffsetTxDq: 08
N7.C3.D0.R1.S08: RdPtrOffsetTxDq: 07
N1.C3.D0.R1.S10: RdPtrOffsetTxDq: 07
N7.C3.D0.R1.S09: RdPtrOffsetTxDq: 08
N1.C3.D0.R1.S11: RdPtrOffsetTxDq: 07
N7.C3.D0.R1.S10: RdPtrOffsetTxDq: 07
N1.C3.D0.R1.S12: RdPtrOffsetTxDq: 07
N7.C3.D0.R1.S11: RdPtrOffsetTxDq: 07
N1.C3.D0.R1.S13: RdPtrOffsetTxDq: 06
N7.C3.D0.R1.S12: RdPtrOffsetTxDq: 07
N1.C3.D0.R1.S14: RdPtrOffsetTxDq: 07
N7.C3.D0.R1.S13: RdPtrOffsetTxDq: 06
N1.C3.D0.R1.S15: RdPtrOffsetTxDq: 07
N7.C3.D0.R1.S14: RdPtrOffsetTxDq: 07
N1.C3.D0.R1.S16: RdPtrOffsetTxDq: 07
N7.C3.D0.R1.S15: RdPtrOffsetTxDq: 07
N1.C3.D0.R1.S17: RdPtrOffsetTxDq: 07
N7.C3.D0.R1.S16: RdPtrOffsetTxDq: 07
N1.C3.D0.R1.S00: Total Delay in PI ticks: TxDQ = 965
N7.C3.D0.R1.S17: RdPtrOffsetTxDq: 07
N1.C3.D0.R1.S01: Total Delay in PI ticks: TxDQ = 947
N3.C0: RdCmd2DataValidLatency = 19, (dlyFrmS = 13, clEff = 10, earlyCas = 0, selNTiming = 0)
N7.C3.D0.R1.S00: Total Delay in PI ticks: TxDQ = 974
N1.C3.D0.R1.S02: Total Delay in PI ticks: TxDQ = 934
N7.C3.D0.R1.S01: Total Delay in PI ticks: TxDQ = 956
N1.C3.D0.R1.S03: Total Delay in PI ticks: TxDQ = 920
N7.C3.D0.R1.S02: Total Delay in PI ticks: TxDQ = 945
N1.C3.D0.R1.S04: Total Delay in PI ticks: TxDQ = 885
N7.C3.D0.R1.S03: Total Delay in PI ticks: TxDQ = 931
N1.C3.D0.R1.S05: Total Delay in PI ticks: TxDQ = 898
N7.C3.D0.R1.S04: Total Delay in PI ticks: TxDQ = 895
N1.C3.D0.R1.S06: Total Delay in PI ticks: TxDQ = 913
N7.C3.D0.R1.S05: Total Delay in PI ticks: TxDQ = 909
N1.C3.D0.R1.S07: Total Delay in PI ticks: TxDQ = 927
N7.C3.D0.R1.S06: Total Delay in PI ticks: TxDQ = 922
N1.C3.D0.R1.S08: Total Delay in PI ticks: TxDQ = 899
N7.C3.D0.R1.S07: Total Delay in PI ticks: TxDQ = 937
N1.C3.D0.R1.S09: Total Delay in PI ticks: TxDQ = 963
N7.C3.D0.R1.S08: Total Delay in PI ticks: TxDQ = 909
N1.C3.D0.R1.S10: Total Delay in PI ticks: TxDQ = 946
N7.C3.D0.R1.S09: Total Delay in PI ticks: TxDQ = 971
N1.C3.D0.R1.S11: Total Delay in PI ticks: TxDQ = 937
N7.C3.D0.R1.S10: Total Delay in PI ticks: TxDQ = 956
N1.C3.D0.R1.S12: Total Delay in PI ticks: TxDQ = 919
N7.C3.D0.R1.S11: Total Delay in PI ticks: TxDQ = 946
N1.C3.D0.R1.S13: Total Delay in PI ticks: TxDQ = 886
N7.C3.D0.R1.S12: Total Delay in PI ticks: TxDQ = 931
N1.C3.D0.R1.S14: Total Delay in PI ticks: TxDQ = 898
N7.C3.D0.R1.S13: Total Delay in PI ticks: TxDQ = 895
N1.C3.D0.R1.S15: Total Delay in PI ticks: TxDQ = 915
N7.C3.D0.R1.S14: Total Delay in PI ticks: TxDQ = 909
N1.C3.D0.R1.S16: Total Delay in PI ticks: TxDQ = 930
N3.C1: RdCmd2DataValidLatency = 19, (dlyFrmS = 13, clEff = 10, earlyCas = 0, selNTiming = 0)
N7.C3.D0.R1.S15: Total Delay in PI ticks: TxDQ = 924
N1.C3.D0.R1.S17: Total Delay in PI ticks: TxDQ = 899
N7.C3.D0.R1.S16: Total Delay in PI ticks: TxDQ = 940
N1.C3: Calculating Optimimum DQ/DQS Values
N7.C3.D0.R1.S17: Total Delay in PI ticks: TxDQ = 909
N7.C3: Calculating Optimimum DQ/DQS Values
START_DATA_TX_DQ
N1.C3.S00: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 009, RdPtrOffsetTxDqs = 009
N1.C3.S00: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 009, RdPtrOffsetTxDqs = 009
START_DATA_TX_DQ
N1.C3.S01: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 009
N7.C3.S00: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 009, RdPtrOffsetTxDqs = 009
N1.C3.S01: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 009
N7.C3.S00: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 009, RdPtrOffsetTxDqs = 009
N1.C3.S02: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 009
N7.C3.S01: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 009
N1.C3.S02: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 009
N7.C3.S01: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 009
N1.C3.S03: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 008
N7.C3.S02: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 009
N1.C3.S03: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 008
N7.C3.S02: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 009
N1.C3.S04: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 007, RdPtrOffsetTxDqs = 008
N7.C3.S03: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 009
N1.C3.S04: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 007, RdPtrOffsetTxDqs = 008
N3.C0: RdCmd2DataValidLatency = 18, (dlyFrmS = 12, clEff = 10, earlyCas = 0, selNTiming = 0)
N7.C3.S03: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 009
N1.C3.S05: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 008
N7.C3.S04: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 007, RdPtrOffsetTxDqs = 008
N1.C3.S05: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 008
N7.C3.S04: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 007, RdPtrOffsetTxDqs = 008
N1.C3.S06: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 008
N7.C3.S05: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 008
N1.C3.S06: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 008
N7.C3.S05: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 008
N1.C3.S07: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 009
N7.C3.S06: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 008
N1.C3.S07: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 009
N7.C3.S06: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 008
N1.C3.S08: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 008
N7.C3.S07: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 009
N1.C3.S08: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 008
N7.C3.S07: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 009
N1.C3.D0.R0.S00: TxDqs: plus1 = 1, minus1 = 0, PI = 40, DB = 0
N7.C3.S08: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 008
N1.C3.D0.R0.S00: TxDq : plus1 = 1, minus1 = 0, PI = 05, DB = 1
N3.C1: RdCmd2DataValidLatency = 18, (dlyFrmS = 12, clEff = 10, earlyCas = 0, selNTiming = 0)
N7.C3.S08: WrCmd2DqsStartLatency = 004, RdPtrOffsetTxDq = 008, RdPtrOffsetTxDqs = 008
N1.C3.D0.R0.S01: TxDqs: plus1 = 1, minus1 = 0, PI = 19, DB = 0
N7.C3.D0.R0.S00: TxDqs: plus1 = 1, minus1 = 0, PI = 47, DB = 0
N1.C3.D0.R0.S01: TxDq : plus1 = 1, minus1 = 0, PI = 51, DB = 1
N7.C3.D0.R0.S00: TxDq : plus1 = 1, minus1 = 0, PI = 13, DB = 1
N1.C3.D0.R0.S02: TxDqs: plus1 = 1, minus1 = 0, PI = 09, DB = 1
N7.C3.D0.R0.S01: TxDqs: plus1 = 1, minus1 = 0, PI = 31, DB = 0
N1.C3.D0.R0.S02: TxDq : plus1 = 1, minus1 = 0, PI = 39, DB = 0
N7.C3.D0.R0.S01: TxDq : plus1 = 1, minus1 = 0, PI = 60, DB = 1
N1.C3.D0.R0.S03: TxDqs: plus1 = 1, minus1 = 0, PI = 58, DB = 1
N7.C3.D0.R0.S02: TxDqs: plus1 = 1, minus1 = 0, PI = 18, DB = 0
N1.C3.D0.R0.S03: TxDq : plus1 = 1, minus1 = 0, PI = 23, DB = 0
N7.C3.D0.R0.S02: TxDq : plus1 = 1, minus1 = 0, PI = 49, DB = 1
N1.C3.D0.R0.S04: TxDqs: plus1 = 1, minus1 = 0, PI = 23, DB = 0
N7.C3.D0.R0.S03: TxDqs: plus1 = 1, minus1 = 0, PI = 05, DB = 1
N1.C3.D0.R0.S04: TxDq : plus1 = 1, minus1 = 0, PI = 53, DB = 1
N7.C3.D0.R0.S03: TxDq : plus1 = 1, minus1 = 0, PI = 35, DB = 0
N1.C3.D0.R0.S05: TxDqs: plus1 = 1, minus1 = 0, PI = 36, DB = 0
N7.C3.D0.R0.S04: TxDqs: plus1 = 1, minus1 = 0, PI = 32, DB = 0
N1.C3.D0.R0.S05: TxDq : plus1 = 1, minus1 = 0, PI = 02, DB = 1
N7.C3.D0.R0.S04: TxDq : plus1 = 1, minus1 = 0, PI = 62, DB = 1
N1.C3.D0.R0.S06: TxDqs: plus1 = 1, minus1 = 0, PI = 51, DB = 1
N7.C3.D0.R0.S05: TxDqs: plus1 = 1, minus1 = 0, PI = 46, DB = 0
N1.C3.D0.R0.S06: TxDq : plus1 = 1, minus1 = 0, PI = 16, DB = 0
N7.C3.D0.R0.S05: TxDq : plus1 = 1, minus1 = 0, PI = 13, DB = 1
N1.C3.D0.R0.S07: TxDqs: plus1 = 1, minus1 = 0, PI = 04, DB = 1
N7.C3.D0.R0.S06: TxDqs: plus1 = 1, minus1 = 0, PI = 61, DB = 1
N1.C3.D0.R0.S07: TxDq : plus1 = 1, minus1 = 0, PI = 32, DB = 0
N7.C3.D0.R0.S06: TxDq : plus1 = 1, minus1 = 0, PI = 26, DB = 0
N1.C3.D0.R0.S08: TxDqs: plus1 = 1, minus1 = 0, PI = 37, DB = 0
N3.C0: RdCmd2DataValidLatency = 17, (dlyFrmS = 11, clEff = 10, earlyCas = 0, selNTiming = 0)
N7.C3.D0.R0.S07: TxDqs: plus1 = 1, minus1 = 0, PI = 14, DB = 1
N1.C3.D0.R0.S08: TxDq : plus1 = 1, minus1 = 0, PI = 04, DB = 1
START_DATA_TX_DQ_ADV
Results for N5.C0.D0.R0: 
           0   1   2   3   4   5   6   7   8   9  10  11  12  13  14  15  16  17
-------------------------------------------------------------------------------
Vref offset: 0
Left:    -26 -26 -26 -26 -26 -29 -26 -27 -26 -25 -25 -28 -26 -28 -27 -27 -27 -24
Right:    24  24  24  23  22  18  24  22  21  24  24  26  23  22  21  24  23  24
-------------------------------------------------------------------------------
Prev Pi: 447 432 417 401 369 386 390 409 375 447 431 420 400 370 387 392 409 375
New Pi:  446 431 416 400 367 381 389 407 373 447 431 419 399 367 384 391 407 375
Diff:     -1  -1  -1  -1  -2  -5  -1  -2  -2   0   0  -1  -1  -3  -3  -1  -2   0

Results for N5.C0.D0.R1: 
           0   1   2   3   4   5   6   7   8   9  10  11  12  13  14  15  16  17
-------------------------------------------------------------------------------
Vref offset: 0
Left:    -28 -28 -26 -26 -26 -27 -27 -27 -27 -25 -25 -28 -27 -27 -27 -24 -27 -26
Right:    24  23  24  23  22  20  23  22  21  25  25  22  23  23  22  24  23  21
-------------------------------------------------------------------------------
Prev Pi: 447 432 417 401 369 386 390 409 375 447 431 420 400 370 387 392 409 375
New Pi:  445 430 416 400 367 383 388 407 372 447 431 417 398 368 385 392 407 373
Diff:     -2  -2  -1  -1  -2  -3  -2  -2  -3   0   0  -3  -2  -2  -2   0  -2  -2

Results for N5.C1.D0.R0: 
           0   1   2   3   4   5   6   7   8   9  10  11  12  13  14  15  16  17
-------------------------------------------------------------------------------
Vref offset: 0
Left:    -27 -28 -26 -27 -28 -27 -28 -24 -26 -27 -27 -27 -27 -27 -27 -25 -24 -27
Right:    20  20  21  22  20  21  21  23  21  19  22  22  23  22  22  23  24  23
-------------------------------------------------------------------------------
Prev Pi: 456 438 428 410 378 393 407 425 391 455 438 429 412 381 392 407 424 392
New Pi:  453 434 426 408 374 390 404 425 389 451 436 427 410 379 390 406 424 390
Diff:     -3  -4  -2  -2  -4  -3  -3   0  -2  -4  -2  -2  -2  -2  -2  -1   0  -2

Results for N5.C1.D0.R1: 
           0   1   2   3   4   5   6   7   8   9  10  11  12  13  14  15  16  17
-------------------------------------------------------------------------------
Vref offset: 0
Left:    -27 -27 -26 -27 -27 -26 -26 -24 -27 -28 -25 -27 -27 -28 -27 -25 -23 -26
Right:    20  21  21  23  22  22  22  24  22  19  22  21  23  21  23  24  26  22
-------------------------------------------------------------------------------
Prev Pi: 456 438 428 410 378 393 407 425 391 455 438 429 412 381 392 407 424 392
New Pi:  453 435 426 408 376 391 405 425 389 451 437 426 410 378 390 407 425 390
Diff:     -3  -3  -2  -2  -2  -2  -2   0  -2  -4  -1  -3  -2  -3  -2   0   1  -2

Results for N5.C2.D0.R0: 
           0   1   2   3   4   5   6   7   8   9  10  11  12  13  14  15  16  17
-------------------------------------------------------------------------------
Vref offset: 0
Left:    -26 -28 -25 -27 -26 -27 -25 -27 -26 -27 -27 -26 -27 -26 -26 -27 -28 -24
Right:    23  22  21  22  22  20  21  20  21  22  21  22  23  23  21  24  22  20
-------------------------------------------------------------------------------
Prev Pi: 451 436 428 410 368 396 396 419 382 450 436 428 411 368 395 397 418 382
New Pi:  450 433 426 408 366 393 394 416 380 448 433 426 409 367 393 396 415 380
Diff:     -1  -3  -2  -2  -2  -3  -2  -3  -2  -2  -3  -2  -2  -1  -2  -1  -3  -2

Results for N5.C2.D0.R1: 
           0   1   2   3   4   5   6   7   8   9  10  11  12  13  14  15  16  17
-------------------------------------------------------------------------------
Vref offset: 0
Left:    -26 -25 -26 -27 -26 -26 -25 -28 -26 -27 -28 -27 -28 -26 -27 -27 -28 -25
Right:    23  22  22  23  23  21  21  20  20  22  22  22  22  23  21  22  22  21
-------------------------------------------------------------------------------
Prev Pi: 451 436 428 410 368 396 396 419 382 450 436 428 411 368 395 397 418 382
New Pi:  450 435 426 408 367 394 394 415 379 448 433 426 408 367 392 395 415 380
Diff:     -1  -1  -2  -2  -1  -2  -2  -4  -3  -2  -3  -2  -3  -1  -3  -2  -3  -2

Results for N5.C3.D0.R0: 
           0   1   2   3   4   5   6   7   8   9  10  11  12  13  14  15  16  17
-------------------------------------------------------------------------------
Vref offset: 0
Left:    -24 -26 -25 -28 -27 -26 -25 -21 -25 -27 -24 -27 -28 -26 -24 -26 -26 -28
Right:    20  21  23  22  21  20  22  23  22  19  22  22  21  23  20  23  21  23
-------------------------------------------------------------------------------
Prev Pi: 456 441 428 413 375 394 405 422 394 455 442 431 413 376 391 406 423 395
New Pi:  454 439 427 410 372 391 404 423 393 451 441 429 410 375 389 405 421 393
Diff:     -2  -2  -1  -3  -3  -3  -1   1  -1  -4  -1  -2  -3  -1  -2  -1  -2  -2

Results for N5.C3.D0.R1: 
           0   1   2   3   4   5   6   7   8   9  10  11  12  13  14  15  16  17
-------------------------------------------------------------------------------
Vref offset: 0
Left:    -27 -25 -24 -28 -25 -26 -25 -24 -25 -28 -25 -26 -28 -27 -26 -25 -26 -28
Right:    21  22  22  22  22  22  22  23  22  19  22  21  21  22  23  23  22  22
-------------------------------------------------------------------------------
Prev Pi: 456 441 428 413 375 394 405 422 394 455 442 431 413 376 391 406 423 395
New Pi:  453 440 427 410 374 392 404 422 393 451 441 429 410 374 390 405 421 392
Diff:     -3  -1  -1  -3  -1  -2  -1   0  -1  -4  -1  -2  -3  -2  -1  -1  -2  -3

STOP_DATA_TX_DQ_ADV
N7.C3.D0.R0.S07: TxDq : plus1 = 1, minus1 = 0, PI = 41, DB = 0
N1.C3.D0.R0.S09: TxDqs: plus1 = 1, minus1 = 0, PI = 38, DB = 0
N3.C1: RdCmd2DataValidLatency = 17, (dlyFrmS = 11, clEff = 10, earlyCas = 0, selNTiming = 0)
N5: RunTrainStep: Final status = 0
N7.C3.D0.R0.S08: TxDqs: plus1 = 1, minus1 = 0, PI = 47, DB = 0
N1.C3.D0.R0.S09: TxDq : plus1 = 1, minus1 = 0, PI = 03, DB = 1

END - Wr Timing Centering 2D Training  Time         3144 ms
N7.C3.D0.R0.S08: TxDq : plus1 = 1, minus1 = 0, PI = 13, DB = 1
N1.C3.D0.R0.S10: TxDqs: plus1 = 1, minus1 = 0, PI = 21, DB = 0

START - Rd Voltage Training
N7.C3.D0.R0.S09: TxDqs: plus1 = 1, minus1 = 0, PI = 46, DB = 0
N1.C3.D0.R0.S10: TxDq : plus1 = 1, minus1 = 0, PI = 51, DB = 1
N5: RX Vref Training...
N7.C3.D0.R0.S09: TxDq : plus1 = 1, minus1 = 0, PI = 12, DB = 1
N1.C3.D0.R0.S11: TxDqs: plus1 = 1, minus1 = 0, PI = 10, DB = 1
N5: GetMargins: Level = 1, group = 13, mode = 2, scope = 4
N7.C3.D0.R0.S10: TxDqs: plus1 = 1, minus1 = 0, PI = 32, DB = 0
N1.C3.D0.R0.S11: TxDq : plus1 = 1, minus1 = 0, PI = 41, DB = 0
N7.C3.D0.R0.S10: TxDq : plus1 = 1, minus1 = 0, PI = 61, DB = 1
N1.C3.D0.R0.S12: TxDqs: plus1 = 1, minus1 = 0, PI = 58, DB = 1
N7.C3.D0.R0.S11: TxDqs: plus1 = 1, minus1 = 0, PI = 20, DB = 0
N1.C3.D0.R0.S12: TxDq : plus1 = 1, minus1 = 0, PI = 24, DB = 0
N7.C3.D0.R0.S11: TxDq : plus1 = 1, minus1 = 0, PI = 51, DB = 1
N1.C3.D0.R0.S13: TxDqs: plus1 = 1, minus1 = 0, PI = 24, DB = 0
N7.C3.D0.R0.S12: TxDqs: plus1 = 1, minus1 = 0, PI = 05, DB = 1
N1.C3.D0.R0.S13: TxDq : plus1 = 1, minus1 = 0, PI = 53, DB = 1
N7.C3.D0.R0.S12: TxDq : plus1 = 1, minus1 = 0, PI = 35, DB = 0
N1.C3.D0.R0.S14: TxDqs: plus1 = 1, minus1 = 0, PI = 35, DB = 0
N7.C3.D0.R0.S13: TxDqs: plus1 = 1, minus1 = 0, PI = 33, DB = 0
N1.C3.D0.R0.S14: TxDq : plus1 = 1, minus1 = 0, PI = 02, DB = 1
N7.C3.D0.R0.S13: TxDq : plus1 = 1, minus1 = 0, PI = 62, DB = 1
N1.C3.D0.R0.S15: TxDqs: plus1 = 1, minus1 = 0, PI = 52, DB = 1
N7.C3.D0.R0.S14: TxDqs: plus1 = 1, minus1 = 0, PI = 47, DB = 0
N1.C3.D0.R0.S15: TxDq : plus1 = 1, minus1 = 0, PI = 18, DB = 0
N3.C0: RdCmd2DataValidLatency = 16, (dlyFrmS = 10, clEff = 10, earlyCas = 0, selNTiming = 0)
N7.C3.D0.R0.S14: TxDq : plus1 = 1, minus1 = 0, PI = 13, DB = 1
N1.C3.D0.R0.S16: TxDqs: plus1 = 1, minus1 = 0, PI = 04, DB = 1
N7.C3.D0.R0.S15: TxDqs: plus1 = 1, minus1 = 0, PI = 61, DB = 1
N1.C3.D0.R0.S16: TxDq : plus1 = 1, minus1 = 0, PI = 35, DB = 0
N7.C3.D0.R0.S15: TxDq : plus1 = 1, minus1 = 0, PI = 28, DB = 0
N1.C3.D0.R0.S17: TxDqs: plus1 = 1, minus1 = 0, PI = 36, DB = 0
N7.C3.D0.R0.S16: TxDqs: plus1 = 1, minus1 = 0, PI = 13, DB = 1
N1.C3.D0.R0.S17: TxDq : plus1 = 1, minus1 = 0, PI = 02, DB = 1
N7.C3.D0.R0.S16: TxDq : plus1 = 1, minus1 = 0, PI = 43, DB = 0
N1.C3.D0.R1.S00: TxDqs: plus1 = 1, minus1 = 0, PI = 40, DB = 0
N7.C3.D0.R0.S17: TxDqs: plus1 = 1, minus1 = 0, PI = 47, DB = 0
N1.C3.D0.R1.S00: TxDq : plus1 = 1, minus1 = 0, PI = 05, DB = 1
N7.C3.D0.R0.S17: TxDq : plus1 = 1, minus1 = 0, PI = 13, DB = 1
N1.C3.D0.R1.S01: TxDqs: plus1 = 1, minus1 = 0, PI = 19, DB = 0
N7.C3.D0.R1.S00: TxDqs: plus1 = 1, minus1 = 0, PI = 47, DB = 0
N1.C3.D0.R1.S01: TxDq : plus1 = 1, minus1 = 0, PI = 51, DB = 1
N7.C3.D0.R1.S00: TxDq : plus1 = 1, minus1 = 0, PI = 13, DB = 1
N1.C3.D0.R1.S02: TxDqs: plus1 = 1, minus1 = 0, PI = 09, DB = 1
N7.C3.D0.R1.S01: TxDqs: plus1 = 1, minus1 = 0, PI = 31, DB = 0
N1.C3.D0.R1.S02: TxDq : plus1 = 1, minus1 = 0, PI = 39, DB = 0
N7.C3.D0.R1.S01: TxDq : plus1 = 1, minus1 = 0, PI = 60, DB = 1
N1.C3.D0.R1.S03: TxDqs: plus1 = 1, minus1 = 0, PI = 58, DB = 1
N7.C3.D0.R1.S02: TxDqs: plus1 = 1, minus1 = 0, PI = 18, DB = 0
N1.C3.D0.R1.S03: TxDq : plus1 = 1, minus1 = 0, PI = 23, DB = 0
N7.C3.D0.R1.S02: TxDq : plus1 = 1, minus1 = 0, PI = 49, DB = 1
N1.C3.D0.R1.S04: TxDqs: plus1 = 1, minus1 = 0, PI = 23, DB = 0
N3.C1: RdCmd2DataValidLatency = 16, (dlyFrmS = 10, clEff = 10, earlyCas = 0, selNTiming = 0)
N7.C3.D0.R1.S03: TxDqs: plus1 = 1, minus1 = 0, PI = 05, DB = 1
N1.C3.D0.R1.S04: TxDq : plus1 = 1, minus1 = 0, PI = 53, DB = 1
N7.C3.D0.R1.S03: TxDq : plus1 = 1, minus1 = 0, PI = 35, DB = 0
N1.C3.D0.R1.S05: TxDqs: plus1 = 1, minus1 = 0, PI = 36, DB = 0
N7.C3.D0.R1.S04: TxDqs: plus1 = 1, minus1 = 0, PI = 32, DB = 0
N1.C3.D0.R1.S05: TxDq : plus1 = 1, minus1 = 0, PI = 02, DB = 1
N7.C3.D0.R1.S04: TxDq : plus1 = 1, minus1 = 0, PI = 62, DB = 1
N1.C3.D0.R1.S06: TxDqs: plus1 = 1, minus1 = 0, PI = 51, DB = 1
N7.C3.D0.R1.S05: TxDqs: plus1 = 1, minus1 = 0, PI = 46, DB = 0
N1.C3.D0.R1.S06: TxDq : plus1 = 1, minus1 = 0, PI = 16, DB = 0
N7.C3.D0.R1.S05: TxDq : plus1 = 1, minus1 = 0, PI = 13, DB = 1
N1.C3.D0.R1.S07: TxDqs: plus1 = 1, minus1 = 0, PI = 04, DB = 1
N7.C3.D0.R1.S06: TxDqs: plus1 = 1, minus1 = 0, PI = 61, DB = 1
N1.C3.D0.R1.S07: TxDq : plus1 = 1, minus1 = 0, PI = 32, DB = 0
N7.C3.D0.R1.S06: TxDq : plus1 = 1, minus1 = 0, PI = 26, DB = 0
N1.C3.D0.R1.S08: TxDqs: plus1 = 1, minus1 = 0, PI = 37, DB = 0
N7.C3.D0.R1.S07: TxDqs: plus1 = 1, minus1 = 0, PI = 14, DB = 1
N1.C3.D0.R1.S08: TxDq : plus1 = 1, minus1 = 0, PI = 04, DB = 1
N7.C3.D0.R1.S07: TxDq : plus1 = 1, minus1 = 0, PI = 41, DB = 0
N1.C3.D0.R1.S09: TxDqs: plus1 = 1, minus1 = 0, PI = 38, DB = 0
N7.C3.D0.R1.S08: TxDqs: plus1 = 1, minus1 = 0, PI = 47, DB = 0
N1.C3.D0.R1.S09: TxDq : plus1 = 1, minus1 = 0, PI = 03, DB = 1
N7.C3.D0.R1.S08: TxDq : plus1 = 1, minus1 = 0, PI = 13, DB = 1
N1.C3.D0.R1.S10: TxDqs: plus1 = 1, minus1 = 0, PI = 21, DB = 0
N7.C3.D0.R1.S09: TxDqs: plus1 = 1, minus1 = 0, PI = 46, DB = 0
N1.C3.D0.R1.S10: TxDq : plus1 = 1, minus1 = 0, PI = 51, DB = 1
N7.C3.D0.R1.S09: TxDq : plus1 = 1, minus1 = 0, PI = 12, DB = 1
N1.C3.D0.R1.S11: TxDqs: plus1 = 1, minus1 = 0, PI = 10, DB = 1
N7.C3.D0.R1.S10: TxDqs: plus1 = 1, minus1 = 0, PI = 32, DB = 0
N1.C3.D0.R1.S11: TxDq : plus1 = 1, minus1 = 0, PI = 41, DB = 0
N3.C0: RdCmd2DataValidLatency = 15, (dlyFrmS = 9, clEff = 10, earlyCas = 0, selNTiming = 0)
N7.C3.D0.R1.S10: TxDq : plus1 = 1, minus1 = 0, PI = 61, DB = 1
N1.C3.D0.R1.S12: TxDqs: plus1 = 1, minus1 = 0, PI = 58, DB = 1
N7.C3.D0.R1.S11: TxDqs: plus1 = 1, minus1 = 0, PI = 20, DB = 0
N1.C3.D0.R1.S12: TxDq : plus1 = 1, minus1 = 0, PI = 24, DB = 0
N7.C3.D0.R1.S11: TxDq : plus1 = 1, minus1 = 0, PI = 51, DB = 1
N1.C3.D0.R1.S13: TxDqs: plus1 = 1, minus1 = 0, PI = 24, DB = 0
N7.C3.D0.R1.S12: TxDqs: plus1 = 1, minus1 = 0, PI = 05, DB = 1
N1.C3.D0.R1.S13: TxDq : plus1 = 1, minus1 = 0, PI = 53, DB = 1
N7.C3.D0.R1.S12: TxDq : plus1 = 1, minus1 = 0, PI = 35, DB = 0
N1.C3.D0.R1.S14: TxDqs: plus1 = 1, minus1 = 0, PI = 35, DB = 0
N7.C3.D0.R1.S13: TxDqs: plus1 = 1, minus1 = 0, PI = 33, DB = 0
N1.C3.D0.R1.S14: TxDq : plus1 = 1, minus1 = 0, PI = 02, DB = 1
N7.C3.D0.R1.S13: TxDq : plus1 = 1, minus1 = 0, PI = 62, DB = 1
N1.C3.D0.R1.S15: TxDqs: plus1 = 1, minus1 = 0, PI = 52, DB = 1
N7.C3.D0.R1.S14: TxDqs: plus1 = 1, minus1 = 0, PI = 47, DB = 0
N1.C3.D0.R1.S15: TxDq : plus1 = 1, minus1 = 0, PI = 18, DB = 0
N7.C3.D0.R1.S14: TxDq : plus1 = 1, minus1 = 0, PI = 13, DB = 1
N1.C3.D0.R1.S16: TxDqs: plus1 = 1, minus1 = 0, PI = 04, DB = 1
N7.C3.D0.R1.S15: TxDqs: plus1 = 1, minus1 = 0, PI = 61, DB = 1
N1.C3.D0.R1.S16: TxDq : plus1 = 1, minus1 = 0, PI = 35, DB = 0
N7.C3.D0.R1.S15: TxDq : plus1 = 1, minus1 = 0, PI = 28, DB = 0
N1.C3.D0.R1.S17: TxDqs: plus1 = 1, minus1 = 0, PI = 36, DB = 0
N7.C3.D0.R1.S16: TxDqs: plus1 = 1, minus1 = 0, PI = 13, DB = 1
N1.C3.D0.R1.S17: TxDq : plus1 = 1, minus1 = 0, PI = 02, DB = 1
N7.C3.D0.R1.S16: TxDq : plus1 = 1, minus1 = 0, PI = 43, DB = 0
END_DATA_TX_DQ
N3.C1: RdCmd2DataValidLatency = 15, (dlyFrmS = 9, clEff = 10, earlyCas = 0, selNTiming = 0)
N7.C3.D0.R1.S17: TxDqs: plus1 = 1, minus1 = 0, PI = 47, DB = 0
N1: RunTrainStep: Final status = 0
N7.C3.D0.R1.S17: TxDq : plus1 = 1, minus1 = 0, PI = 13, DB = 1

END - Basic Write DQ/DQS Training      Time         27309 ms
END_DATA_TX_DQ
Checkpoint Code: Socket 0, 0xB7, 0x11, 0x0000
N7: RunTrainStep: Final status = 0
N1.C0: JCK cmd timing = 1N

END - Basic Write DQ/DQS Training      Time         27275 ms
N1.C0: RdCmd2DataValidLatency = 21, (dlyFrmS = 15, clEff = 10, earlyCas = 0, selNTiming = 0)
N7.C0: JCK cmd timing = 1N
N1.C1: RdCmd2DataValidLatency = 21, (dlyFrmS = 15, clEff = 10, earlyCas = 0, selNTiming = 0)
N7.C0: RdCmd2DataValidLatency = 21, (dlyFrmS = 15, clEff = 10, earlyCas = 0, selNTiming = 0)
N1.C2: JCK cmd timing = 1N
N7.C1: RdCmd2DataValidLatency = 21, (dlyFrmS = 15, clEff = 10, earlyCas = 0, selNTiming = 0)
N1.C2: RdCmd2DataValidLatency = 21, (dlyFrmS = 15, clEff = 10, earlyCas = 0, selNTiming = 0)
N7.C2: JCK cmd timing = 1N
N1.C3: RdCmd2DataValidLatency = 21, (dlyFrmS = 15, clEff = 10, earlyCas = 0, selNTiming = 0)
N7.C2: RdCmd2DataValidLatency = 21, (dlyFrmS = 15, clEff = 10, earlyCas = 0, selNTiming = 0)
N1: JckSetOdtDynTiming[2] BL8:
N7.C3: RdCmd2DataValidLatency = 21, (dlyFrmS = 15, clEff = 10, earlyCas = 0, selNTiming = 0)
N7: JckSetOdtDynTiming[2] BL8:
N1.C0: minRcvEnDelay = 195 maxRcvEnDelay = 282 ==> rdwidth = 6 rddly = 2 wrwidth = 6 wrdly = 0
N1.C1: minRcvEnDelay = 195 maxRcvEnDelay = 311 ==> rdwidth = 6 rddly = 2 wrwidth = 6 wrdly = 0
N7.C0: minRcvEnDelay = 196 maxRcvEnDelay = 283 ==> rdwidth = 6 rddly = 2 wrwidth = 6 wrdly = 0
N1.C2: minRcvEnDelay = 197 maxRcvEnDelay = 288 ==> rdwidth = 6 rddly = 2 wrwidth = 6 wrdly = 0
N7.C1: minRcvEnDelay = 202 maxRcvEnDelay = 319 ==> rdwidth = 6 rddly = 2 wrwidth = 6 wrdly = 0
N1.C3: minRcvEnDelay = 192 maxRcvEnDelay = 308 ==> rdwidth = 6 rddly = 2 wrwidth = 6 wrdly = 0
N3.C0: RdCmd2DataValidLatency = 14, (dlyFrmS = 8, clEff = 10, earlyCas = 0, selNTiming = 0)
N7.C2: minRcvEnDelay = 198 maxRcvEnDelay = 284 ==> rdwidth = 6 rddly = 2 wrwidth = 6 wrdly = 0
N1.C0: Memory Electrical TurnAround timings:
N7.C3: minRcvEnDelay = 204 maxRcvEnDelay = 321 ==> rdwidth = 6 rddly = 2 wrwidth = 6 wrdly = 0
N1.C0:      tCCD  =  0, tWWDR =  3, tRRDD =  2, tWWDD =  3, tWRDR =  1, tWRDR_UPPER =  0, tRRDR =  0
N7.C0: Memory Electrical TurnAround timings:
N1.C0:      tRWDD =  2, tRWDR =  2, tWRDD =  1, tRWSR =  2
N7.C0:      tCCD  =  0, tWWDR =  3, tRRDD =  2, tWWDD =  3, tWRDR =  1, tWRDR_UPPER =  0, tRRDR =  0
N1.C0: TCOTHP: T_RWSR = 0x2, T_RWDD = 0x2
N7.C0:      tRWDD =  2, tRWDR =  2, tWRDD =  1, tRWSR =  2
N1.C0:      tCCD_WR =  0, tWRDS =  2, tRWDS =  2, tWWDS =  3, tRRDS =  1
N7.C0: TCOTHP: T_RWSR = 0x2, T_RWDD = 0x2
N1.C1: Memory Electrical TurnAround timings:
N7.C0:      tCCD_WR =  0, tWRDS =  2, tRWDS =  2, tWWDS =  3, tRRDS =  1
N1.C1:      tCCD  =  0, tWWDR =  3, tRRDD =  2, tWWDD =  3, tWRDR =  1, tWRDR_UPPER =  0, tRRDR =  0
N7.C1: Memory Electrical TurnAround timings:
N1.C1:      tRWDD =  2, tRWDR =  2, tWRDD =  1, tRWSR =  2
N7.C1:      tCCD  =  0, tWWDR =  3, tRRDD =  2, tWWDD =  3, tWRDR =  1, tWRDR_UPPER =  0, tRRDR =  0
N1.C1: TCOTHP: T_RWSR = 0x2, T_RWDD = 0x2
N7.C1:      tRWDD =  2, tRWDR =  2, tWRDD =  1, tRWSR =  2
N1.C1:      tCCD_WR =  0, tWRDS =  2, tRWDS =  2, tWWDS =  3, tRRDS =  1
N7.C1: TCOTHP: T_RWSR = 0x2, T_RWDD = 0x2
N1.C2: Memory Electrical TurnAround timings:
N7.C1:      tCCD_WR =  0, tWRDS =  2, tRWDS =  2, tWWDS =  3, tRRDS =  1
N1.C2:      tCCD  =  0, tWWDR =  3, tRRDD =  2, tWWDD =  3, tWRDR =  1, tWRDR_UPPER =  0, tRRDR =  0
N3.C1: RdCmd2DataValidLatency = 14, (dlyFrmS = 8, clEff = 10, earlyCas = 0, selNTiming = 0)
N7.C2: Memory Electrical TurnAround timings:
N1.C2:      tRWDD =  2, tRWDR =  2, tWRDD =  1, tRWSR =  2
N7.C2:      tCCD  =  0, tWWDR =  3, tRRDD =  2, tWWDD =  3, tWRDR =  1, tWRDR_UPPER =  0, tRRDR =  0
N1.C2: TCOTHP: T_RWSR = 0x2, T_RWDD = 0x2
N7.C2:      tRWDD =  2, tRWDR =  2, tWRDD =  1, tRWSR =  2
N1.C2:      tCCD_WR =  0, tWRDS =  2, tRWDS =  2, tWWDS =  3, tRRDS =  1
N7.C2: TCOTHP: T_RWSR = 0x2, T_RWDD = 0x2
N1.C3: Memory Electrical TurnAround timings:
N7.C2:      tCCD_WR =  0, tWRDS =  2, tRWDS =  2, tWWDS =  3, tRRDS =  1
N1.C3:      tCCD  =  0, tWWDR =  3, tRRDD =  2, tWWDD =  3, tWRDR =  1, tWRDR_UPPER =  0, tRRDR =  0
N7.C3: Memory Electrical TurnAround timings:
N1.C3:      tRWDD =  2, tRWDR =  2, tWRDD =  1, tRWSR =  2
N7.C3:      tCCD  =  0, tWWDR =  3, tRRDD =  2, tWWDD =  3, tWRDR =  1, tWRDR_UPPER =  0, tRRDR =  0
N1.C3: TCOTHP: T_RWSR = 0x2, T_RWDD = 0x2
N7.C3:      tRWDD =  2, tRWDR =  2, tWRDD =  1, tRWSR =  2
N1.C3:      tCCD_WR =  0, tWRDS =  2, tRWDS =  2, tWWDS =  3, tRRDS =  1
N7.C3: TCOTHP: T_RWSR = 0x2, T_RWDD = 0x2

START - Rd Timing Centering 2D Training
N7.C3:      tCCD_WR =  0, tWRDS =  2, tRWDS =  2, tWWDS =  3, tRRDS =  1
Checkpoint Code: Socket 0, 0xB7, 0x08, 0x0000

START - Rd Timing Centering 2D Training
N1: 

Adv Strobe Centering(MARGIN_RX_DQ): GetMultiVref: patternLength = 13, stepSize = 1, numPoints = 1
N7: 

Adv Strobe Centering(MARGIN_RX_DQ): GetMultiVref: patternLength = 13, stepSize = 1, numPoints = 1
N1: GetMargins: Level = 1, group = 11, mode = 0, scope = 4
N7: GetMargins: Level = 1, group = 11, mode = 0, scope = 4
N3.C0: RdCmd2DataValidLatency = 16, (dlyFrmS = 10, clEff = 10, earlyCas = 0, selNTiming = 0)
N3.C1: RdCmd2DataValidLatency = 16, (dlyFrmS = 10, clEff = 10, earlyCas = 0, selNTiming = 0)
N5.C0: Read Vref - Strobe:0 Worst Left Edge:-31, Worst Right Edge:31, Center:0
N5.C0: Read Vref - Strobe:1 Worst Left Edge:-31, Worst Right Edge:31, Center:0
N5.C0: Read Vref - Strobe:2 Worst Left Edge:-31, Worst Right Edge:31, Center:0
N5.C0: Read Vref - Strobe:3 Worst Left Edge:-31, Worst Right Edge:31, Center:0
N5.C0: Read Vref - Strobe:4 Worst Left Edge:-31, Worst Right Edge:31, Center:0
N5.C0: Read Vref - Strobe:5 Worst Left Edge:-31, Worst Right Edge:31, Center:0
N5.C0: Read Vref - Strobe:6 Worst Left Edge:-31, Worst Right Edge:31, Center:0
N5.C0: Read Vref - Strobe:7 Worst Left Edge:-31, Worst Right Edge:31, Center:0
N5.C0: Read Vref - Strobe:8 Worst Left Edge:-31, Worst Right Edge:31, Center:0
N5.C0: Read Vref - Strobe:9 Worst Left Edge:-31, Worst Right Edge:31, Center:0
N5.C0: Read Vref - Strobe:10 Worst Left Edge:-31, Worst Right Edge:31, Center:0
N5.C0: Read Vref - Strobe:11 Worst Left Edge:-31, Worst Right Edge:31, Center:0
N5.C0: Read Vref - Strobe:12 Worst Left Edge:-31, Worst Right Edge:31, Center:0
N5.C0: Read Vref - Strobe:13 Worst Left Edge:-31, Worst Right Edge:31, Center:0
N5.C0: Read Vref - Strobe:14 Worst Left Edge:-31, Worst Right Edge:31, Center:0
N5.C0: Read Vref - Strobe:15 Worst Left Edge:-31, Worst Right Edge:31, Center:0
N5.C0: Read Vref - Strobe:16 Worst Left Edge:-31, Worst Right Edge:31, Center:0
N5.C0: Read Vref - Strobe:17 Worst Left Edge:-31, Worst Right Edge:31, Center:0
N5.C1: Read Vref - Strobe:0 Worst Left Edge:-31, Worst Right Edge:31, Center:0
N5.C1: Read Vref - Strobe:1 Worst Left Edge:-31, Worst Right Edge:31, Center:0
N3.C0: AdjustTotalRoundTripTime: SUCCESS - worst rank = 0, host round trip = 73, MXB cmd2dat = 10
N5.C1: Read Vref - Strobe:2 Worst Left Edge:-31, Worst Right Edge:31, Center:0
N3.C2: AdjustTotalRoundTripTime
N5.C1: Read Vref - Strobe:3 Worst Left Edge:-31, Worst Right Edge:31, Center:0
N3.C1: AdjustTotalRoundTripTime: worstRank = 0
N5.C1: Read Vref - Strobe:4 Worst Left Edge:-31, Worst Right Edge:31, Center:0
N3.C2: AdjustTotalRoundTripTime: worstRank dimm = 0, rank = 0
N5.C1: Read Vref - Strobe:5 Worst Left Edge:-31, Worst Right Edge:31, Center:0
N3.C3: AdjustTotalRoundTripTime: worstRank dimm = 0, rank = 0
N5.C1: Read Vref - Strobe:6 Worst Left Edge:-31, Worst Right Edge:31, Center:0
START_DATA_RX_DQS_ADV
Results for N7.C0.D0.R0: 
           0   1   2   3   4   5   6   7   8   9  10  11  12  13  14  15  16  17
-------------------------------------------------------------------------------
Vref offset: 0
Left:    -25 -24 -24 -25 -23 -24 -23 -24 -23 -26 -22 -23 -24 -24 -24 -26 -24 -20
Right:    26  28  29  31  26  25  24  23  26  22  31  28  31  26  25  26  27  24
-------------------------------------------------------------------------------
Prev Pi:  35  34  33  35  34  35  32  35  34  34  35  34  34  36  33  33  34  36
New Pi:   35  36  35  38  35  35  32  35  35  32  39  36  37  37  33  33  35  38
Diff:      0   2   2   3   1   0   0   0   1  -2   4   2   3   1   0   0   1   2

Results for N7.C0.D0.R1: 
           0   1   2   3   4   5   6   7   8   9  10  11  12  13  14  15  16  17
-------------------------------------------------------------------------------
Vref offset: 0
Left:    -25 -24 -24 -25 -23 -23 -23 -24 -23 -26 -24 -24 -24 -24 -24 -26 -24 -20
Right:    23  27  29  31  26  25  25  25  24  23  30  31  26  24  23  26  28  24
-------------------------------------------------------------------------------
Prev Pi:  35  34  33  35  34  35  32  35  34  34  35  34  34  36  33  33  34  36
New Pi:   34  35  35  38  35  36  33  35  34  33  38  37  35  36  33  33  36  38
Diff:     -1   1   2   3   1   1   1   0   0  -1   3   3   1   0   0   0   2   2

Results for N7.C1.D0.R0: 
           0   1   2   3   4   5   6   7   8   9  10  11  12  13  14  15  16  17
-------------------------------------------------------------------------------
Vref offset: 0
Left:    -24 -25 -23 -25 -25 -22 -22 -19 -18 -24 -24 -21 -23 -25 -23 -24 -22 -24
Right:    24  30  25  27  28  25  23  27  26  19  26  25  21  22  25  23  27  23
-------------------------------------------------------------------------------
Prev Pi:  33  35  33  34  33  33  34  33  32  34  35  32  33  34  33  34  34  32
New Pi:   33  37  34  35  34  34  34  37  36  32  36  34  32  33  34  34  36  32
Diff:      0   2   1   1   1   1   0   4   4  -2   1   2  -1  -1   1   0   2   0

Results for N7.C1.D0.R1: 
           0   1   2   3   4   5   6   7   8   9  10  11  12  13  14  15  16  17
-------------------------------------------------------------------------------
Vref offset: 0
Left:    -24 -25 -24 -24 -25 -22 -22 -20 -17 -24 -24 -22 -23 -25 -23 -24 -22 -24
Right:    24  29  26  26  31  24  22  26  24  21  24  25  21  23  25  21  27  23
-------------------------------------------------------------------------------
Prev Pi:  33  35  33  34  33  33  34  33  32  34  35  32  33  34  33  34  34  32
New Pi:   33  37  34  35  36  34  34  36  35  33  35  33  32  33  34  33  36  32
Diff:      0   2   1   1   3   1   0   3   3  -1   0   1  -1  -1   1  -1   2   0

Results for N7.C2.D0.R0: 
           0   1   2   3   4   5   6   7   8   9  10  11  12  13  14  15  16  17
-------------------------------------------------------------------------------
Vref offset: 0
Left:    -23 -22 -22 -24 -21 -23 -24 -21 -22 -20 -20 -22 -25 -21 -22 -20 -20 -21
Right:    23  24  27  29  26  26  16  18  29  25  25  25  28  25  18  23  23  26
-------------------------------------------------------------------------------
Prev Pi:  32  34  33  34  34  35  35  31  34  32  35  32  36  32  34  29  28  37
New Pi:   32  35  35  36  36  36  31  30  37  34  37  33  37  34  32  30  29  39
Diff:      0   1   2   2   2   1  -4  -1   3   2   2   1   1   2  -2   1   1   2

Results for N7.C2.D0.R1: 
           0   1   2   3   4   5   6   7   8   9  10  11  12  13  14  15  16  17
-------------------------------------------------------------------------------
Vref offset: 0
Left:    -22 -23 -23 -24 -21 -22 -24 -21 -23 -20 -21 -22 -25 -20 -22 -21 -19 -22
Right:    21  25  25  28  26  23  16  20  27  23  25  25  29  25  18  23  21  25
-------------------------------------------------------------------------------
Prev Pi:  32  34  33  34  34  35  35  31  34  32  35  32  36  32  34  29  28  37
New Pi:   32  35  34  36  36  35  31  31  36  33  37  33  38  34  32  30  29  38
Diff:      0   1   1   2   2   0  -4   0   2   1   2   1   2   2  -2   1   1   1

Results for N7.C3.D0.R0: 
           0   1   2   3   4   5   6   7   8   9  10  11  12  13  14  15  16  17
-------------------------------------------------------------------------------
Vref offset: 0
Left:    -19 -21 -21 -21 -20 -26 -20 -23 -20 -24 -23 -24 -22 -23 -22 -25 -19 -21
Right:    23  22  22  24  22  24  25  20  25  22  24  26  26  22  25  24  25  24
-------------------------------------------------------------------------------
Prev Pi:  31  31  35  34  36  34  35  31  33  35  34  33  33  35  34  34  29  34
New Pi:   33  31  35  35  37  33  37  30  35  34  34  34  35  35  35  34  32  35
Diff:      2   0   0   1   1  -1   2  -1   2  -1   0   1   2   0   1   0   3   1

Results for N7.C3.D0.R1: 
           0   1   2   3   4   5   6   7   8   9  10  11  12  13  14  15  16  17
-------------------------------------------------------------------------------
Vref offset: 0
Left:    -19 -21 -20 -21 -21 -25 -20 -23 -20 -25 -23 -24 -22 -23 -22 -25 -19 -22
Right:    23  21  21  23  25  19  25  20  22  22  25  29  27  22  24  24  24  26
-------------------------------------------------------------------------------
Prev Pi:  31  31  35  34  36  34  35  31  33  35  34  33  33  35  34  34  29  34
New Pi:   33  31  35  35  38  31  37  30  34  34  35  35  35  35  35  34  31  36
Diff:      2   0   0   1   2  -3   2  -1   1  -1   1   2   2   0   1   0   2   2

STOP_DATA_RX_DQS_ADV
START_DATA_RX_DQS_ADV
Results for N1.C0.D0.R0: 
           0   1   2   3   4   5   6   7   8   9  10  11  12  13  14  15  16  17
-------------------------------------------------------------------------------
Vref offset: 0
Left:    -26 -25 -19 -24 -22 -20 -23 -23 -23 -26 -20 -22 -23 -24 -23 -17 -23 -25
Right:    24  21  23  24  23  30  26  25  25  24  22  26  26  25  28  31  26  25
-------------------------------------------------------------------------------
Prev Pi:  34  33  35  36  34  35  34  34  33  35  29  34  34  35  34  33  32  35
New Pi:   33  31  37  36  34  40  35  35  34  34  30  36  35  35  36  40  33  35
Diff:     -1  -2   2   0   0   5   1   1   1  -1   1   2   1   0   2   7   1   0

Results for N1.C0.D0.R1: 
           0   1   2   3   4   5   6   7   8   9  10  11  12  13  14  15  16  17
-------------------------------------------------------------------------------
Vref offset: 0
Left:    -25 -25 -20 -24 -22 -19 -23 -24 -23 -26 -20 -22 -24 -23 -23 -17 -22 -25
Right:    24  23  25  25  24  25  27  25  25  25  21  26  24  24  28  30  24  27
-------------------------------------------------------------------------------
Prev Pi:  34  33  35  36  34  35  34  34  33  35  29  34  34  35  34  33  32  35
New Pi:   34  32  37  36  35  38  36  34  34  35  29  36  34  35  36  39  33  36
Diff:      0  -1   2   0   1   3   2   0   1   0   0   2   0   0   2   6   1   1

Results for N1.C1.D0.R0: 
           0   1   2   3   4   5   6   7   8   9  10  11  12  13  14  15  16  17
-------------------------------------------------------------------------------
Vref offset: 0
Left:    -23 -23 -21 -23 -24 -25 -22 -25 -22 -23 -24 -25 -25 -21 -24 -23 -24 -21
Right:    25  24  24  30  25  27  30  25  26  28  24  24  25  23  31  28  23  25
-------------------------------------------------------------------------------
Prev Pi:  34  33  33  33  33  34  33  34  33  36  33  34  33  30  34  33  35  31
New Pi:   35  33  34  36  33  35  37  34  35  38  33  34  33  31  37  35  35  33
Diff:      1   0   1   3   0   1   4   0   2   2   0   0   0   1   3   2   0   2

Results for N1.C1.D0.R1: 
           0   1   2   3   4   5   6   7   8   9  10  11  12  13  14  15  16  17
-------------------------------------------------------------------------------
Vref offset: 0
Left:    -22 -23 -21 -22 -24 -24 -22 -25 -21 -23 -24 -25 -25 -21 -24 -23 -24 -22
Right:    26  26  24  28  25  26  26  25  21  28  24  24  26  25  30  26  22  24
-------------------------------------------------------------------------------
Prev Pi:  34  33  33  33  33  34  33  34  33  36  33  34  33  30  34  33  35  31
New Pi:   36  34  34  36  33  35  35  34  33  38  33  34  33  32  37  34  34  32
Diff:      2   1   1   3   0   1   2   0   0   2   0   0   0   2   3   1  -1   1

Results for N1.C2.D0.R0: 
           0   1   2   3   4   5   6   7   8   9  10  11  12  13  14  15  16  17
-------------------------------------------------------------------------------
Vref offset: 0
Left:    -23 -22 -27 -21 -24 -20 -21 -22 -22 -24 -22 -23 -22 -25 -21 -17 -25 -24
Right:    27  23  27  29  28  31  28  24  31  22  26  26  26  25  31  25  24  29
-------------------------------------------------------------------------------
Prev Pi:  32  35  35  34  33  36  35  34  34  35  33  34  35  33  36  35  33  35
New Pi:   34  35  35  38  35  41  38  35  38  34  35  35  37  33  41  39  33  37
Diff:      2   0   0   4   2   5   3   1   4  -1   2   1   2   0   5   4   0   2

Results for N1.C2.D0.R1: 
           0   1   2   3   4   5   6   7   8   9  10  11  12  13  14  15  16  17
-------------------------------------------------------------------------------
Vref offset: 0
Left:    -23 -22 -26 -20 -24 -20 -22 -22 -21 -24 -22 -24 -21 -25 -21 -18 -25 -25
Right:    23  24  27  31  25  31  26  23  25  23  21  26  24  24  31  26  23  27
-------------------------------------------------------------------------------
Prev Pi:  32  35  35  34  33  36  35  34  34  35  33  34  35  33  36  35  33  35
New Pi:   32  36  35  39  33  41  37  34  36  35  33  35  36  33  41  39  32  36
Diff:      0   1   0   5   0   5   2   0   2   0   0   1   1   0   5   4  -1   1

Results for N1.C3.D0.R0: 
           0   1   2   3   4   5   6   7   8   9  10  11  12  13  14  15  16  17
-------------------------------------------------------------------------------
Vref offset: 0
Left:    -22 -23 -19 -20 -23 -21 -19 -16 -19 -22 -23 -24 -26 -24 -24 -21 -22 -19
Right:    24  20  25  30  25  28  31  22  31  26  24  27  30  19  31  24  25  26
-------------------------------------------------------------------------------
Prev Pi:  35  33  33  35  33  35  34  31  34  35  34  33  33  36  35  34  31  34
New Pi:   36  32  36  40  34  38  40  34  40  37  34  34  35  34  38  35  32  37
Diff:      1  -1   3   5   1   3   6   3   6   2   0   1   2  -2   3   1   1   3

Results for N1.C3.D0.R1: 
           0   1   2   3   4   5   6   7   8   9  10  11  12  13  14  15  16  17
-------------------------------------------------------------------------------
Vref offset: 0
Left:    -22 -24 -19 -20 -23 -20 -19 -16 -19 -22 -23 -25 -25 -24 -23 -21 -22 -20
Right:    24  23  25  31  20  30  24  21  28  27  24  27  29  19  31  22  24  28
-------------------------------------------------------------------------------
Prev Pi:  35  33  33  35  33  35  34  31  34  35  34  33  33  36  35  34  31  34
New Pi:   36  33  36  40  32  40  36  33  38  37  34  34  35  34  39  34  32  38
Diff:      1   0   3   5  -1   5   2   2   4   2   0   1   2  -2   4   0   1   4

STOP_DATA_RX_DQS_ADV
N3.C1: AdjustTotalRoundTripTime: ddrChMask = 0xC
N5.C1: Read Vref - Strobe:7 Worst Left Edge:-31, Worst Right Edge:31, Center:0
N7: RunTrainStep: Final status = 0
N1: RunTrainStep: Final status = 0
N5.C1: Read Vref - Strobe:8 Worst Left Edge:-31, Worst Right Edge:31, Center:0

END - Rd Timing Centering 2D Training  Time         1902 ms

END - Rd Timing Centering 2D Training  Time         1923 ms
N3.C2: RdCmd2DataValidLatency = 20, (dlyFrmS = 14, clEff = 10, earlyCas = 0, selNTiming = 0)
N5.C1: Read Vref - Strobe:9 Worst Left Edge:-31, Worst Right Edge:31, Center:0

START - Wr Timing Centering 2D Training

START - Wr Timing Centering 2D Training
N5.C1: Read Vref - Strobe:10 Worst Left Edge:-30, Worst Right Edge:31, Center:0
N7: 

Adv Strobe Centering(MARGIN_TX_DQ): GetMultiVref: patternLength = 13, stepSize = 1, numPoints = 1
Checkpoint Code: Socket 0, 0xB7, 0x07, 0x0000
N5.C1: Read Vref - Strobe:11 Worst Left Edge:-31, Worst Right Edge:31, Center:0
N7: GetMargins: Level = 1, group = 12, mode = 0, scope = 4
N1: 

Adv Strobe Centering(MARGIN_TX_DQ): GetMultiVref: patternLength = 13, stepSize = 1, numPoints = 1
N5.C1: Read Vref - Strobe:12 Worst Left Edge:-31, Worst Right Edge:31, Center:0
N1: GetMargins: Level = 1, group = 12, mode = 0, scope = 4
N5.C1: Read Vref - Strobe:13 Worst Left Edge:-31, Worst Right Edge:31, Center:0
N5.C1: Read Vref - Strobe:14 Worst Left Edge:-31, Worst Right Edge:31, Center:0
N5.C1: Read Vref - Strobe:15 Worst Left Edge:-30, Worst Right Edge:31, Center:0
N5.C1: Read Vref - Strobe:16 Worst Left Edge:-31, Worst Right Edge:31, Center:0
N5.C1: Read Vref - Strobe:17 Worst Left Edge:-31, Worst Right Edge:31, Center:0
N5.C2: Read Vref - Strobe:0 Worst Left Edge:-31, Worst Right Edge:31, Center:0
N5.C2: Read Vref - Strobe:1 Worst Left Edge:-31, Worst Right Edge:31, Center:0
N5.C2: Read Vref - Strobe:2 Worst Left Edge:-31, Worst Right Edge:31, Center:0
N5.C2: Read Vref - Strobe:3 Worst Left Edge:-31, Worst Right Edge:31, Center:0
N5.C2: Read Vref - Strobe:4 Worst Left Edge:-31, Worst Right Edge:31, Center:0
N3.C3: RdCmd2DataValidLatency = 20, (dlyFrmS = 14, clEff = 10, earlyCas = 0, selNTiming = 0)
N5.C2: Read Vref - Strobe:5 Worst Left Edge:-31, Worst Right Edge:31, Center:0
N5.C2: Read Vref - Strobe:6 Worst Left Edge:-31, Worst Right Edge:31, Center:0
N5.C2: Read Vref - Strobe:7 Worst Left Edge:-31, Worst Right Edge:31, Center:0
N5.C2: Read Vref - Strobe:8 Worst Left Edge:-31, Worst Right Edge:31, Center:0
N5.C2: Read Vref - Strobe:9 Worst Left Edge:-31, Worst Right Edge:31, Center:0
N5.C2: Read Vref - Strobe:10 Worst Left Edge:-31, Worst Right Edge:31, Center:0
N5.C2: Read Vref - Strobe:11 Worst Left Edge:-31, Worst Right Edge:31, Center:0
N5.C2: Read Vref - Strobe:12 Worst Left Edge:-31, Worst Right Edge:31, Center:0
N5.C2: Read Vref - Strobe:13 Worst Left Edge:-31, Worst Right Edge:31, Center:0
N5.C2: Read Vref - Strobe:14 Worst Left Edge:-31, Worst Right Edge:31, Center:0
N5.C2: Read Vref - Strobe:15 Worst Left Edge:-31, Worst Right Edge:31, Center:0
N5.C2: Read Vref - Strobe:16 Worst Left Edge:-28, Worst Right Edge:31, Center:1
N5.C2: Read Vref - Strobe:17 Worst Left Edge:-31, Worst Right Edge:31, Center:0
N5.C3: Read Vref - Strobe:0 Worst Left Edge:-31, Worst Right Edge:31, Center:0
N5.C3: Read Vref - Strobe:1 Worst Left Edge:-31, Worst Right Edge:31, Center:0
N5.C3: Read Vref - Strobe:2 Worst Left Edge:-31, Worst Right Edge:31, Center:0
N5.C3: Read Vref - Strobe:3 Worst Left Edge:-31, Worst Right Edge:31, Center:0
N5.C3: Read Vref - Strobe:4 Worst Left Edge:-31, Worst Right Edge:31, Center:0
N5.C3: Read Vref - Strobe:5 Worst Left Edge:-26, Worst Right Edge:31, Center:2
N5.C3: Read Vref - Strobe:6 Worst Left Edge:-31, Worst Right Edge:31, Center:0
N5.C3: Read Vref - Strobe:7 Worst Left Edge:-31, Worst Right Edge:31, Center:0
N5.C3: Read Vref - Strobe:8 Worst Left Edge:-31, Worst Right Edge:31, Center:0
N5.C3: Read Vref - Strobe:9 Worst Left Edge:-31, Worst Right Edge:31, Center:0
N3.C2: RdCmd2DataValidLatency = 19, (dlyFrmS = 13, clEff = 10, earlyCas = 0, selNTiming = 0)
N5.C3: Read Vref - Strobe:10 Worst Left Edge:-31, Worst Right Edge:31, Center:0
N5.C3: Read Vref - Strobe:11 Worst Left Edge:-31, Worst Right Edge:31, Center:0
N5.C3: Read Vref - Strobe:12 Worst Left Edge:-31, Worst Right Edge:31, Center:0
N5.C3: Read Vref - Strobe:13 Worst Left Edge:-31, Worst Right Edge:31, Center:0
N5.C3: Read Vref - Strobe:14 Worst Left Edge:-31, Worst Right Edge:31, Center:0
N5.C3: Read Vref - Strobe:15 Worst Left Edge:-30, Worst Right Edge:31, Center:0
N5.C3: Read Vref - Strobe:16 Worst Left Edge:-31, Worst Right Edge:31, Center:0
N5.C3: Read Vref - Strobe:17 Worst Left Edge:-31, Worst Right Edge:31, Center:0
N5: RunTrainStep: Final status = 0

END - Rd Voltage Training              Time         3666 ms
N5.C0.D0.R0.S00: StoreJckWorstRank: worst rank = 0, greatestDelay = 1304
N5.C0.D0.R0.S07: StoreJckWorstRank: worst rank = 0, greatestDelay = 1310
N5.C1.D0.R0.S00: StoreJckWorstRank: worst rank = 0, greatestDelay = 1358
N5.C0: StoreJckWorstRank: final value: worst rank = 0
N5.C2.D0.R0.S00: StoreJckWorstRank: worst rank = 0, greatestDelay = 1317
N5.C2.D0.R0.S09: StoreJckWorstRank: worst rank = 0, greatestDelay = 1318
N5.C3.D0.R0.S00: StoreJckWorstRank: worst rank = 0, greatestDelay = 1355
N5.C3.D0.R1.S00: StoreJckWorstRank: worst rank = 1, greatestDelay = 1356
N5.C1: StoreJckWorstRank: final value: worst rank = 1
GetAllRankMargins
N5: Checking margins for all ranks...
N5: 
Get Rx Dqs margins...
N5: GetMargins: Level = 1, group = 11, mode = 0, scope = 3
N3.C3: RdCmd2DataValidLatency = 19, (dlyFrmS = 13, clEff = 10, earlyCas = 0, selNTiming = 0)
N3.C2: RdCmd2DataValidLatency = 18, (dlyFrmS = 12, clEff = 10, earlyCas = 0, selNTiming = 0)
N5: 
Get Tx Dq margins...
N5: GetMargins: Level = 1, group = 12, mode = 0, scope = 3
N3.C3: RdCmd2DataValidLatency = 18, (dlyFrmS = 12, clEff = 10, earlyCas = 0, selNTiming = 0)
N3.C2: RdCmd2DataValidLatency = 17, (dlyFrmS = 11, clEff = 10, earlyCas = 0, selNTiming = 0)
N3.C3: RdCmd2DataValidLatency = 17, (dlyFrmS = 11, clEff = 10, earlyCas = 0, selNTiming = 0)
N5: 
Get Rx Vref margins...
N5: GetMargins: Level = 1, group = 13, mode = 0, scope = 3
N3.C2: RdCmd2DataValidLatency = 16, (dlyFrmS = 10, clEff = 10, earlyCas = 0, selNTiming = 0)
START_DATA_TX_DQ_ADV
Results for N7.C0.D0.R0: 
           0   1   2   3   4   5   6   7   8   9  10  11  12  13  14  15  16  17
-------------------------------------------------------------------------------
Vref offset: 0
Left:    -26 -28 -25 -26 -24 -25 -27 -26 -26 -24 -26 -25 -25 -24 -26 -27 -27 -25
Right:    22  22  23  25  21  21  21  21  20  22  22  24  25  25  20  22  21  21
-------------------------------------------------------------------------------
Prev Pi: 446 424 413 396 364 383 385 405 372 445 424 412 396 365 384 387 405 373
New Pi:  444 421 412 396 363 381 382 403 369 444 422 412 396 365 381 385 402 371
Diff:     -2  -3  -1   0  -1  -2  -3  -2  -3  -1  -2   0   0   0  -3  -2  -3  -2

Results for N7.C0.D0.R1: 
           0   1   2   3   4   5   6   7   8   9  10  11  12  13  14  15  16  17
-------------------------------------------------------------------------------
Vref offset: 0
Left:    -26 -27 -26 -25 -24 -25 -26 -26 -26 -25 -27 -25 -24 -25 -27 -27 -27 -26
Right:    23  21  22  25  22  22  21  21  21  21  22  25  24  24  22  22  21  20
-------------------------------------------------------------------------------
Prev Pi: 446 424 413 396 364 383 385 405 372 445 424 412 396 365 384 387 405 373
New Pi:  445 421 411 396 363 382 383 403 370 443 422 412 396 365 382 385 402 370
Diff:     -1  -3  -2   0  -1  -1  -2  -2  -2  -2  -2   0   0   0  -2  -2  -3  -3

Results for N7.C1.D0.R0: 
           0   1   2   3   4   5   6   7   8   9  10  11  12  13  14  15  16  17
-------------------------------------------------------------------------------
Vref offset: 0
Left:    -26 -27 -25 -27 -27 -26 -26 -25 -24 -26 -26 -26 -25 -26 -25 -27 -24 -25
Right:    20  21  21  21  19  21  21  21  22  19  22  21  23  22  22  21  22  23
-------------------------------------------------------------------------------
Prev Pi: 459 441 433 414 383 397 411 426 394 458 441 434 415 382 395 410 427 394
New Pi:  456 438 431 411 379 395 409 424 393 455 439 432 414 380 394 407 426 393
Diff:     -3  -3  -2  -3  -4  -2  -2  -2  -1  -3  -2  -2  -1  -2  -1  -3  -1  -1

Results for N7.C1.D0.R1: 
           0   1   2   3   4   5   6   7   8   9  10  11  12  13  14  15  16  17
-------------------------------------------------------------------------------
Vref offset: 0
Left:    -27 -28 -25 -27 -27 -27 -26 -25 -26 -26 -26 -26 -26 -27 -25 -27 -25 -25
Right:    20  20  21  21  21  21  22  22  23  17  22  22  23  21  23  21  23  22
-------------------------------------------------------------------------------
Prev Pi: 459 441 433 414 383 397 411 426 394 458 441 434 415 382 395 410 427 394
New Pi:  456 437 431 411 380 394 409 425 393 454 439 432 414 379 394 407 426 393
Diff:     -3  -4  -2  -3  -3  -3  -2  -1  -1  -4  -2  -2  -1  -3  -1  -3  -1  -1

Results for N7.C2.D0.R0: 
           0   1   2   3   4   5   6   7   8   9  10  11  12  13  14  15  16  17
-------------------------------------------------------------------------------
Vref offset: 0
Left:    -27 -28 -27 -27 -26 -27 -27 -27 -24 -27 -28 -27 -27 -26 -26 -26 -27 -24
Right:    23  23  22  23  23  19  21  22  24  22  23  24  24  24  21  21  23  22
-------------------------------------------------------------------------------
Prev Pi: 444 428 418 399 360 387 388 410 373 442 429 419 400 360 387 389 409 372
New Pi:  442 426 416 397 359 383 385 408 373 440 427 418 399 359 385 387 407 371
Diff:     -2  -2  -2  -2  -1  -4  -3  -2   0  -2  -2  -1  -1  -1  -2  -2  -2  -1

Results for N7.C2.D0.R1: 
           0   1   2   3   4   5   6   7   8   9  10  11  12  13  14  15  16  17
-------------------------------------------------------------------------------
Vref offset: 0
Left:    -28 -27 -25 -27 -26 -26 -28 -27 -24 -27 -28 -28 -25 -26 -27 -27 -27 -24
Right:    23  22  23  24  23  20  20  22  22  23  24  22  24  24  21  22  24  24
-------------------------------------------------------------------------------
Prev Pi: 444 428 418 399 360 387 388 410 373 442 429 419 400 360 387 389 409 372
New Pi:  442 426 417 398 359 384 384 408 372 440 427 416 400 359 384 387 408 372
Diff:     -2  -2  -1  -1  -1  -3  -4  -2  -1  -2  -2  -3   0  -1  -3  -2  -1   0

Results for N7.C3.D0.R0: 
           0   1   2   3   4   5   6   7   8   9  10  11  12  13  14  15  16  17
-------------------------------------------------------------------------------
Vref offset: 0
Left:    -28 -27 -25 -27 -28 -27 -25 -23 -27 -27 -27 -26 -27 -28 -26 -26 -25 -25
Right:    20  22  21  22  20  21  22  23  21  19  23  22  22  21  22  22  23  24
-------------------------------------------------------------------------------
Prev Pi: 461 444 433 419 382 397 410 425 397 460 445 435 419 382 397 412 427 397
New Pi:  457 442 431 417 378 394 409 425 394 456 443 433 417 379 395 410 426 397
Diff:     -4  -2  -2  -2  -4  -3  -1   0  -3  -4  -2  -2  -2  -3  -2  -2  -1   0

Results for N7.C3.D0.R1: 
           0   1   2   3   4   5   6   7   8   9  10  11  12  13  14  15  16  17
-------------------------------------------------------------------------------
Vref offset: 0
Left:    -28 -27 -25 -28 -26 -27 -25 -23 -27 -27 -27 -27 -27 -28 -26 -26 -24 -24
Right:    20  21  20  22  21  20  22  24  22  18  21  20  21  21  23  22  24  22
-------------------------------------------------------------------------------
Prev Pi: 461 444 433 419 382 397 410 425 397 460 445 435 419 382 397 412 427 397
New Pi:  457 441 431 416 380 394 409 425 395 456 442 432 416 379 396 410 427 396
Diff:     -4  -3  -2  -3  -2  -3  -1   0  -2  -4  -3  -3  -3  -3  -1  -2   0  -1

STOP_DATA_TX_DQ_ADV
START_DATA_TX_DQ_ADV
Results for N1.C0.D0.R0: 
           0   1   2   3   4   5   6   7   8   9  10  11  12  13  14  15  16  17
-------------------------------------------------------------------------------
Vref offset: 0
Left:    -27 -26 -27 -26 -25 -26 -26 -25 -23 -26 -26 -25 -26 -28 -27 -28 -24 -27
Right:    22  22  23  24  21  21  21  19  21  24  23  25  24  22  21  22  22  23
-------------------------------------------------------------------------------
Prev Pi: 450 430 417 399 366 385 389 407 373 447 430 415 402 367 384 391 406 373
New Pi:  448 428 415 398 364 383 387 404 372 446 429 415 401 364 381 388 405 371
Diff:     -2  -2  -2  -1  -2  -2  -2  -3  -1  -1  -1   0  -1  -3  -3  -3  -1  -2

Results for N1.C0.D0.R1: 
           0   1   2   3   4   5   6   7   8   9  10  11  12  13  14  15  16  17
-------------------------------------------------------------------------------
Vref offset: 0
Left:    -27 -26 -27 -26 -24 -27 -26 -26 -25 -25 -27 -26 -27 -28 -26 -27 -24 -27
Right:    21  23  23  24  22  22  22  19  23  24  24  25  24  22  21  23  22  22
-------------------------------------------------------------------------------
Prev Pi: 450 430 417 399 366 385 389 407 373 447 430 415 402 367 384 391 406 373
New Pi:  447 429 415 398 365 383 387 404 372 447 429 415 401 364 382 389 405 371
Diff:     -3  -1  -2  -1  -1  -2  -2  -3  -1   0  -1   0  -1  -3  -2  -2  -1  -2

Results for N1.C1.D0.R0: 
           0   1   2   3   4   5   6   7   8   9  10  11  12  13  14  15  16  17
-------------------------------------------------------------------------------
Vref offset: 0
Left:    -27 -27 -26 -27 -26 -26 -26 -25 -26 -26 -27 -27 -26 -29 -26 -26 -25 -26
Right:    19  21  20  22  22  22  23  22  21  19  22  22  23  21  22  22  23  23
-------------------------------------------------------------------------------
Prev Pi: 454 436 427 411 377 389 404 421 389 453 435 428 411 378 389 405 421 388
New Pi:  450 433 424 409 375 387 403 420 387 450 433 426 410 374 387 403 420 387
Diff:     -4  -3  -3  -2  -2  -2  -1  -1  -2  -3  -2  -2  -1  -4  -2  -2  -1  -1

Results for N1.C1.D0.R1: 
           0   1   2   3   4   5   6   7   8   9  10  11  12  13  14  15  16  17
-------------------------------------------------------------------------------
Vref offset: 0
Left:    -26 -27 -27 -26 -27 -22 -25 -26 -27 -25 -26 -27 -27 -29 -27 -26 -25 -27
Right:    18  21  21  22  23  23  22  22  21  19  21  22  23  21  22  21  23  22
-------------------------------------------------------------------------------
Prev Pi: 454 436 427 411 377 389 404 421 389 453 435 428 411 378 389 405 421 388
New Pi:  450 433 424 409 375 389 403 419 386 450 433 426 409 374 387 403 420 386
Diff:     -4  -3  -3  -2  -2   0  -1  -2  -3  -3  -2  -2  -2  -4  -2  -2  -1  -2

Results for N1.C2.D0.R0: 
           0   1   2   3   4   5   6   7   8   9  10  11  12  13  14  15  16  17
-------------------------------------------------------------------------------
Vref offset: 0
Left:    -26 -26 -25 -26 -28 -26 -27 -25 -26 -25 -28 -26 -25 -27 -27 -28 -29 -27
Right:    23  23  23  24  24  20  21  24  22  24  21  24  26  23  21  21  23  22
-------------------------------------------------------------------------------
Prev Pi: 447 430 418 402 366 392 391 412 376 445 433 419 404 366 392 393 414 378
New Pi:  446 429 417 401 364 389 388 412 374 445 430 418 404 364 389 390 411 376
Diff:     -1  -1  -1  -1  -2  -3  -3   0  -2   0  -3  -1   0  -2  -3  -3  -3  -2

Results for N1.C2.D0.R1: 
           0   1   2   3   4   5   6   7   8   9  10  11  12  13  14  15  16  17
-------------------------------------------------------------------------------
Vref offset: 0
Left:    -27 -27 -25 -26 -26 -27 -27 -27 -26 -25 -27 -26 -25 -28 -27 -28 -28 -27
Right:    24  23  24  24  22  21  21  23  22  25  22  25  25  24  21  21  23  21
-------------------------------------------------------------------------------
Prev Pi: 447 430 418 402 366 392 391 412 376 445 433 419 404 366 392 393 414 378
New Pi:  446 428 418 401 364 389 388 410 374 445 431 419 404 364 389 390 412 375
Diff:     -1  -2   0  -1  -2  -3  -3  -2  -2   0  -2   0   0  -2  -3  -3  -2  -3

Results for N1.C3.D0.R0: 
           0   1   2   3   4   5   6   7   8   9  10  11  12  13  14  15  16  17
-------------------------------------------------------------------------------
Vref offset: 0
Left:    -27 -28 -24 -26 -28 -26 -24 -23 -28 -27 -28 -27 -26 -28 -27 -26 -25 -27
Right:    21  21  20  24  20  22  23  24  21  19  22  23  23  21  22  23  22  22
-------------------------------------------------------------------------------
Prev Pi: 453 435 423 407 373 386 400 416 388 451 435 425 408 373 386 402 419 386
New Pi:  450 432 421 406 369 384 400 416 385 447 432 423 407 370 384 401 418 384
Diff:     -3  -3  -2  -1  -4  -2   0   0  -3  -4  -3  -2  -1  -3  -2  -1  -1  -2

Results for N1.C3.D0.R1: 
           0   1   2   3   4   5   6   7   8   9  10  11  12  13  14  15  16  17
-------------------------------------------------------------------------------
Vref offset: 0
Left:    -27 -28 -24 -26 -28 -26 -23 -23 -27 -27 -28 -26 -27 -28 -27 -27 -25 -26
Right:    22  21  22  25  20  23  23  24  21  20  21  22  23  22  22  23  23  23
-------------------------------------------------------------------------------
Prev Pi: 453 435 423 407 373 386 400 416 388 451 435 425 408 373 386 402 419 386
New Pi:  451 432 422 407 369 385 400 416 385 448 432 423 406 370 384 400 418 385
Diff:     -2  -3  -1   0  -4  -1   0   0  -3  -3  -3  -2  -2  -3  -2  -2  -1  -1

STOP_DATA_TX_DQ_ADV
N3.C3: RdCmd2DataValidLatency = 16, (dlyFrmS = 10, clEff = 10, earlyCas = 0, selNTiming = 0)
N5: 
Get Tx Vref margins...
N7: RunTrainStep: Final status = 0
N1: RunTrainStep: Final status = 0
N5: GetMargins: Level = 1, group = 14, mode = 0, scope = 3

END - Wr Timing Centering 2D Training  Time         4384 ms

END - Wr Timing Centering 2D Training  Time         4384 ms

START - Rd Voltage Training

START - Rd Voltage Training
N7: RX Vref Training...
Checkpoint Code: Socket 0, 0xB7, 0x0A, 0x0000
N7: GetMargins: Level = 1, group = 13, mode = 2, scope = 4
N1: RX Vref Training...
N1: GetMargins: Level = 1, group = 13, mode = 2, scope = 4
N3.C2: RdCmd2DataValidLatency = 15, (dlyFrmS = 9, clEff = 10, earlyCas = 0, selNTiming = 0)
N3.C3: RdCmd2DataValidLatency = 15, (dlyFrmS = 9, clEff = 10, earlyCas = 0, selNTiming = 0)
N3.C2: RdCmd2DataValidLatency = 14, (dlyFrmS = 8, clEff = 10, earlyCas = 0, selNTiming = 0)
N3.C3: RdCmd2DataValidLatency = 14, (dlyFrmS = 8, clEff = 10, earlyCas = 0, selNTiming = 0)
N3.C2: RdCmd2DataValidLatency = 16, (dlyFrmS = 10, clEff = 10, earlyCas = 0, selNTiming = 0)
N5: 
 Time to do RMT patterns 15  is 4 seconds 

            RxDqLeft RxDqRight RxVLow RxVHigh TxDqLeft TxDqRight TxVLow TxVHigh
--------------------------------------------------------------------------------
N5.C0.D0.R0:   -20       20       -48       48      -23     23      -29      28
N5.C0.D0.R1:   -20       20       -48       48      -23     23      -29      29
N5.C1.D0.R0:   -18       20       -30       48      -23     22      -26      26
N5.C1.D0.R1:   -18       18       -30       48      -23     22      -25      25
N5.C2.D0.R0:   -23       23       -28       48      -23     22      -29      27
N5.C2.D0.R1:   -23       23       -29       48      -23     23      -29      28
N5.C3.D0.R0:   -22       23       -27       48      -21     22      -24      26
N5.C3.D0.R1:   -22       23       -28       48      -23     22      -25      24
STOP_RMT_N5
N5: GetAllRankMargins time            4907 ms
N5: 
Total DDR trainings latency = 104481 ms
N4: PostDdrTraining
N5: PostDdrTraining
N4.C0.D0: CheckRankPopLocal: dimmPresent: 1, numRanks = 2
N4.C0.D0.R0: CheckRankPopLocal: mapOut: 0, enabled = 1
N4.C0.D0.R1: CheckRankPopLocal: mapOut: 0, enabled = 1
N4.C0.D1: CheckRankPopLocal: dimmPresent: 1, numRanks = 2
N4.C0.D1.R0: CheckRankPopLocal: mapOut: 0, enabled = 1
N4.C0.D1.R1: CheckRankPopLocal: mapOut: 0, enabled = 1
N4.C0.D2: CheckRankPopLocal: dimmPresent: 0, numRanks = 0
N4.C0.D0: CheckRankPopLocal: amap: 0x00000000
N4.C0.D1: CheckRankPopLocal: amap: 0x00000000
N3.C3: RdCmd2DataValidLatency = 16, (dlyFrmS = 10, clEff = 10, earlyCas = 0, selNTiming = 0)
N4.C0.D2: CheckRankPopLocal: amap: 0x00000000
N4.C1.D0: CheckRankPopLocal: dimmPresent: 1, numRanks = 2
N4.C1.D0.R0: CheckRankPopLocal: mapOut: 0, enabled = 1
N4.C1.D0.R1: CheckRankPopLocal: mapOut: 0, enabled = 1
N4.C1.D1: CheckRankPopLocal: dimmPresent: 1, numRanks = 2
N4.C1.D1.R0: CheckRankPopLocal: mapOut: 0, enabled = 1
N4.C1.D1.R1: CheckRankPopLocal: mapOut: 0, enabled = 1
N4.C1.D2: CheckRankPopLocal: dimmPresent: 0, numRanks = 0
N4.C1.D0: CheckRankPopLocal: amap: 0x00000000
N4.C1.D1: CheckRankPopLocal: amap: 0x00000000
N4.C1.D2: CheckRankPopLocal: amap: 0x00000000
N4.C2.D0: CheckRankPopLocal: dimmPresent: 1, numRanks = 2
N4.C2.D0.R0: CheckRankPopLocal: mapOut: 0, enabled = 1
N4.C2.D0.R1: CheckRankPopLocal: mapOut: 0, enabled = 1
N4.C2.D1: CheckRankPopLocal: dimmPresent: 1, numRanks = 2
N4.C2.D1.R0: CheckRankPopLocal: mapOut: 0, enabled = 1
N4.C2.D1.R1: CheckRankPopLocal: mapOut: 0, enabled = 1
N4.C2.D2: CheckRankPopLocal: dimmPresent: 0, numRanks = 0
N4.C2.D0: CheckRankPopLocal: amap: 0x00000000
N4.C2.D1: CheckRankPopLocal: amap: 0x00000000
N4.C2.D2: CheckRankPopLocal: amap: 0x00000000
N4.C3.D0: CheckRankPopLocal: dimmPresent: 1, numRanks = 2
N4.C3.D0.R0: CheckRankPopLocal: mapOut: 0, enabled = 1
N4.C3.D0.R1: CheckRankPopLocal: mapOut: 0, enabled = 1
N4.C3.D1: CheckRankPopLocal: dimmPresent: 1, numRanks = 2
N4.C3.D1.R0: CheckRankPopLocal: mapOut: 0, enabled = 1
N4.C3.D1.R1: CheckRankPopLocal: mapOut: 0, enabled = 1
N4.C3.D2: CheckRankPopLocal: dimmPresent: 0, numRanks = 0
N4.C3.D0: CheckRankPopLocal: amap: 0x00000000
N4.C3.D1: CheckRankPopLocal: amap: 0x00000000
N4.C3.D2: CheckRankPopLocal: amap: 0x00000000
N3.C2: AdjustTotalRoundTripTime: SUCCESS - worst rank = 0, host round trip = 75, MXB cmd2dat = 10
N4.C0: AdjustTotalRoundTripTime
N2: DDR Channel Late Configuration
N4.C0: AdjustTotalRoundTripTime: worstRank = 0
N2: Parity Checking Enable
N4.C0: AdjustTotalRoundTripTime: worstRank dimm = 0, rank = 0
N2: Enabling C/A Parity
N4.C1: AdjustTotalRoundTripTime: worstRank dimm = 0, rank = 0
N2.C0: VmseSetupscrambling: Host push_to_data_delay = 7, host scr_to_data_delay = 7, JCK wpsyncdata = 10, JCK scrsyndata = 10, JCK wpsyncrcven = 5, JCK scrsyncrcven = 5
N4.C0: AdjustTotalRoundTripTime: ddrChMask = 0x3
N2.C0: VmseStartScramblers: Start VMSE scramblers, cmdbit = 0x10, datbit = 0x20, command = 0x60003A, 
N2.C1: VmseSetupscrambling: Host push_to_data_delay = 7, host scr_to_data_delay = 7, JCK wpsyncdata = 10, JCK scrsyndata = 10, JCK wpsyncrcven = 5, JCK scrsyncrcven = 5
N4.C0: RdCmd2DataValidLatency = 20, (dlyFrmS = 14, clEff = 10, earlyCas = 0, selNTiming = 0)
N2.C2: VmseStartScramblers: Start VMSE scramblers, cmdbit = 0x10, datbit = 0x20, command = 0x60003A, 
N2: DRAM Maintenance
N2: DRAM Maintenance : Auto Mode
N2: DRAM Maintenance : TRR Mode detected : 0
N2: DRAM Maintenance : TRR Mode detected : 0
N2: DRAM Maintenance : TRR Mode detected : 0
N2: DRAM Maintenance : TRR Mode detected : 0
PTRR Mode Enabled 
N3: DDR Channel Late Configuration
N3: Parity Checking Enable
N3: Enabling C/A Parity
N3.C0: VmseSetupscrambling: Host push_to_data_delay = 7, host scr_to_data_delay = 7, JCK wpsyncdata = 10, JCK scrsyndata = 10, JCK wpsyncrcven = 5, JCK scrsyncrcven = 5
N3.C0: VmseStartScramblers: Start VMSE scramblers, cmdbit = 0x10, datbit = 0x20, command = 0x60003A, 
N3.C1: VmseSetupscrambling: Host push_to_data_delay = 8, host scr_to_data_delay = 8, JCK wpsyncdata = 10, JCK scrsyndata = 10, JCK wpsyncrcven = 5, JCK scrsyncrcven = 5
N7.C0: Read Vref - Strobe:0 Worst Left Edge:-31, Worst Right Edge:31, Center:0
N1.C0: Read Vref - Strobe:0 Worst Left Edge:-31, Worst Right Edge:31, Center:0
N3.C2: VmseStartScramblers: Start VMSE scramblers, cmdbit = 0x10, datbit = 0x20, command = 0x60003A, 
N7.C0: Read Vref - Strobe:1 Worst Left Edge:-31, Worst Right Edge:31, Center:0
N1.C0: Read Vref - Strobe:1 Worst Left Edge:-31, Worst Right Edge:31, Center:0
N3: DRAM Maintenance
N7.C0: Read Vref - Strobe:2 Worst Left Edge:-31, Worst Right Edge:31, Center:0
N1.C0: Read Vref - Strobe:2 Worst Left Edge:-31, Worst Right Edge:31, Center:0
N3: DRAM Maintenance : Auto Mode
N7.C0: Read Vref - Strobe:3 Worst Left Edge:-31, Worst Right Edge:31, Center:0
N1.C0: Read Vref - Strobe:3 Worst Left Edge:-31, Worst Right Edge:31, Center:0
N3: DRAM Maintenance : TRR Mode detected : 0
N4.C1: RdCmd2DataValidLatency = 20, (dlyFrmS = 14, clEff = 10, earlyCas = 0, selNTiming = 0)
N7.C0: Read Vref - Strobe:4 Worst Left Edge:-31, Worst Right Edge:31, Center:0
N1.C0: Read Vref - Strobe:4 Worst Left Edge:-31, Worst Right Edge:31, Center:0
N3: DRAM Maintenance : TRR Mode detected : 0
N7.C0: Read Vref - Strobe:5 Worst Left Edge:-31, Worst Right Edge:31, Center:0
N1.C0: Read Vref - Strobe:5 Worst Left Edge:-31, Worst Right Edge:31, Center:0
N3: DRAM Maintenance : TRR Mode detected : 0
N7.C0: Read Vref - Strobe:6 Worst Left Edge:-31, Worst Right Edge:31, Center:0
N1.C0: Read Vref - Strobe:6 Worst Left Edge:-31, Worst Right Edge:31, Center:0
N3: DRAM Maintenance : TRR Mode detected : 0
N7.C0: Read Vref - Strobe:7 Worst Left Edge:-31, Worst Right Edge:31, Center:0
N1.C0: Read Vref - Strobe:7 Worst Left Edge:-31, Worst Right Edge:31, Center:0
PTRR Mode Enabled 
N7.C0: Read Vref - Strobe:8 Worst Left Edge:-31, Worst Right Edge:31, Center:0
N1.C0: Read Vref - Strobe:8 Worst Left Edge:-31, Worst Right Edge:31, Center:0
DramMemoryEccInit: rankNodeChEnMap = 0xFE1B8BA0
N7.C0: Read Vref - Strobe:9 Worst Left Edge:-31, Worst Right Edge:31, Center:0
N1.C0: Read Vref - Strobe:9 Worst Left Edge:-31, Worst Right Edge:31, Center:0
N3: EnableHostRefresh Start Write Time diff[3]=7849 ns
N7.C0: Read Vref - Strobe:10 Worst Left Edge:-31, Worst Right Edge:31, Center:0
N1.C0: Read Vref - Strobe:10 Worst Left Edge:-31, Worst Right Edge:31, Center:0
N3: EnableHostRefresh End Write Time diff[3]=7835 ns
N7.C0: Read Vref - Strobe:11 Worst Left Edge:-31, Worst Right Edge:31, Center:0
N1.C0: Read Vref - Strobe:11 Worst Left Edge:-31, Worst Right Edge:31, Center:0
N2.C0.R0: CpgcMemTestRankSetup: colAddressBits = 11, rowAddressBits = 15, bankAddressBits = 3
N7.C0: Read Vref - Strobe:12 Worst Left Edge:-31, Worst Right Edge:31, Center:0
N1.C0: Read Vref - Strobe:12 Worst Left Edge:-31, Worst Right Edge:31, Center:0
N2.C1.R0: CpgcMemTestRankSetup: colAddressBits = 11, rowAddressBits = 15, bankAddressBits = 3
N4.C0: RdCmd2DataValidLatency = 19, (dlyFrmS = 13, clEff = 10, earlyCas = 0, selNTiming = 0)
N7.C0: Read Vref - Strobe:13 Worst Left Edge:-31, Worst Right Edge:31, Center:0
N1.C0: Read Vref - Strobe:13 Worst Left Edge:-31, Worst Right Edge:31, Center:0
N2.C2.R0: CpgcMemTestRankSetup: colAddressBits = 11, rowAddressBits = 15, bankAddressBits = 3
N7.C0: Read Vref - Strobe:14 Worst Left Edge:-31, Worst Right Edge:31, Center:0
N1.C0: Read Vref - Strobe:14 Worst Left Edge:-31, Worst Right Edge:31, Center:0
N2.C3.R0: CpgcMemTestRankSetup: colAddressBits = 11, rowAddressBits = 15, bankAddressBits = 3
N7.C0: Read Vref - Strobe:15 Worst Left Edge:-31, Worst Right Edge:31, Center:0
N1.C0: Read Vref - Strobe:15 Worst Left Edge:-31, Worst Right Edge:31, Center:0
N3.C0.R0: CpgcMemTestRankSetup: colAddressBits = 11, rowAddressBits = 16, bankAddressBits = 3
N7.C0: Read Vref - Strobe:16 Worst Left Edge:-31, Worst Right Edge:31, Center:0
N1.C0: Read Vref - Strobe:16 Worst Left Edge:-31, Worst Right Edge:31, Center:0
N3.C1.R0: CpgcMemTestRankSetup: colAddressBits = 11, rowAddressBits = 16, bankAddressBits = 3
N7.C0: Read Vref - Strobe:17 Worst Left Edge:-31, Worst Right Edge:31, Center:0
N1.C0: Read Vref - Strobe:17 Worst Left Edge:-31, Worst Right Edge:31, Center:0
N3.C2.R0: CpgcMemTestRankSetup: colAddressBits = 11, rowAddressBits = 16, bankAddressBits = 3
N7.C1: Read Vref - Strobe:0 Worst Left Edge:-31, Worst Right Edge:31, Center:0
N1.C1: Read Vref - Strobe:0 Worst Left Edge:-30, Worst Right Edge:31, Center:0
N3.C3.R0: CpgcMemTestRankSetup: colAddressBits = 11, rowAddressBits = 16, bankAddressBits = 3
N7.C1: Read Vref - Strobe:1 Worst Left Edge:-31, Worst Right Edge:31, Center:0
N1.C1: Read Vref - Strobe:1 Worst Left Edge:-31, Worst Right Edge:31, Center:0
N4.C1: RdCmd2DataValidLatency = 19, (dlyFrmS = 13, clEff = 10, earlyCas = 0, selNTiming = 0)
N7.C1: Read Vref - Strobe:2 Worst Left Edge:-31, Worst Right Edge:31, Center:0
N1.C1: Read Vref - Strobe:2 Worst Left Edge:-31, Worst Right Edge:31, Center:0
N7.C1: Read Vref - Strobe:3 Worst Left Edge:-31, Worst Right Edge:31, Center:0
N1.C1: Read Vref - Strobe:3 Worst Left Edge:-31, Worst Right Edge:31, Center:0
N7.C1: Read Vref - Strobe:4 Worst Left Edge:-31, Worst Right Edge:31, Center:0
N1.C1: Read Vref - Strobe:4 Worst Left Edge:-31, Worst Right Edge:31, Center:0
N7.C1: Read Vref - Strobe:5 Worst Left Edge:-28, Worst Right Edge:31, Center:1
N1.C1: Read Vref - Strobe:5 Worst Left Edge:-31, Worst Right Edge:31, Center:0
N7.C1: Read Vref - Strobe:6 Worst Left Edge:-31, Worst Right Edge:31, Center:0
N1.C1: Read Vref - Strobe:6 Worst Left Edge:-31, Worst Right Edge:31, Center:0
N7.C1: Read Vref - Strobe:7 Worst Left Edge:-31, Worst Right Edge:31, Center:0
N1.C1: Read Vref - Strobe:7 Worst Left Edge:-31, Worst Right Edge:31, Center:0
N7.C1: Read Vref - Strobe:8 Worst Left Edge:-31, Worst Right Edge:31, Center:0
N1.C1: Read Vref - Strobe:8 Worst Left Edge:-31, Worst Right Edge:31, Center:0
N7.C1: Read Vref - Strobe:9 Worst Left Edge:-31, Worst Right Edge:31, Center:0
N1.C1: Read Vref - Strobe:9 Worst Left Edge:-31, Worst Right Edge:31, Center:0
N7.C1: Read Vref - Strobe:10 Worst Left Edge:-31, Worst Right Edge:31, Center:0
N1.C1: Read Vref - Strobe:10 Worst Left Edge:-31, Worst Right Edge:31, Center:0
N7.C1: Read Vref - Strobe:11 Worst Left Edge:-31, Worst Right Edge:31, Center:0
N1.C1: Read Vref - Strobe:11 Worst Left Edge:-31, Worst Right Edge:31, Center:0
N7.C1: Read Vref - Strobe:12 Worst Left Edge:-29, Worst Right Edge:31, Center:1
N1.C1: Read Vref - Strobe:12 Worst Left Edge:-31, Worst Right Edge:31, Center:0
N7.C1: Read Vref - Strobe:13 Worst Left Edge:-31, Worst Right Edge:31, Center:0
N1.C1: Read Vref - Strobe:13 Worst Left Edge:-30, Worst Right Edge:31, Center:0
N4.C0: RdCmd2DataValidLatency = 18, (dlyFrmS = 12, clEff = 10, earlyCas = 0, selNTiming = 0)
N7.C1: Read Vref - Strobe:14 Worst Left Edge:-31, Worst Right Edge:31, Center:0
N1.C1: Read Vref - Strobe:14 Worst Left Edge:-31, Worst Right Edge:31, Center:0
N7.C1: Read Vref - Strobe:15 Worst Left Edge:-31, Worst Right Edge:31, Center:0
N1.C1: Read Vref - Strobe:15 Worst Left Edge:-31, Worst Right Edge:31, Center:0
N7.C1: Read Vref - Strobe:16 Worst Left Edge:-31, Worst Right Edge:31, Center:0
N1.C1: Read Vref - Strobe:16 Worst Left Edge:-31, Worst Right Edge:31, Center:0
N7.C1: Read Vref - Strobe:17 Worst Left Edge:-31, Worst Right Edge:31, Center:0
N1.C1: Read Vref - Strobe:17 Worst Left Edge:-31, Worst Right Edge:31, Center:0
N7.C2: Read Vref - Strobe:0 Worst Left Edge:-31, Worst Right Edge:31, Center:0
N1.C2: Read Vref - Strobe:0 Worst Left Edge:-31, Worst Right Edge:31, Center:0
N7.C2: Read Vref - Strobe:1 Worst Left Edge:-31, Worst Right Edge:31, Center:0
N1.C2: Read Vref - Strobe:1 Worst Left Edge:-31, Worst Right Edge:31, Center:0
N7.C2: Read Vref - Strobe:2 Worst Left Edge:-31, Worst Right Edge:31, Center:0
N1.C2: Read Vref - Strobe:2 Worst Left Edge:-31, Worst Right Edge:31, Center:0
N7.C2: Read Vref - Strobe:3 Worst Left Edge:-31, Worst Right Edge:31, Center:0
N1.C2: Read Vref - Strobe:3 Worst Left Edge:-31, Worst Right Edge:31, Center:0
N7.C2: Read Vref - Strobe:4 Worst Left Edge:-31, Worst Right Edge:31, Center:0
N1.C2: Read Vref - Strobe:4 Worst Left Edge:-31, Worst Right Edge:31, Center:0
N7.C2: Read Vref - Strobe:5 Worst Left Edge:-31, Worst Right Edge:31, Center:0
N1.C2: Read Vref - Strobe:5 Worst Left Edge:-31, Worst Right Edge:31, Center:0
N4.C1: RdCmd2DataValidLatency = 18, (dlyFrmS = 12, clEff = 10, earlyCas = 0, selNTiming = 0)
N7.C2: Read Vref - Strobe:6 Worst Left Edge:-31, Worst Right Edge:31, Center:0
N1.C2: Read Vref - Strobe:6 Worst Left Edge:-31, Worst Right Edge:31, Center:0
N7.C2: Read Vref - Strobe:7 Worst Left Edge:-31, Worst Right Edge:31, Center:0
N1.C2: Read Vref - Strobe:7 Worst Left Edge:-31, Worst Right Edge:31, Center:0
N7.C2: Read Vref - Strobe:8 Worst Left Edge:-31, Worst Right Edge:31, Center:0
N1.C2: Read Vref - Strobe:8 Worst Left Edge:-31, Worst Right Edge:31, Center:0
N7.C2: Read Vref - Strobe:9 Worst Left Edge:-31, Worst Right Edge:31, Center:0
N1.C2: Read Vref - Strobe:9 Worst Left Edge:-31, Worst Right Edge:31, Center:0
N7.C2: Read Vref - Strobe:10 Worst Left Edge:-31, Worst Right Edge:31, Center:0
N1.C2: Read Vref - Strobe:10 Worst Left Edge:-31, Worst Right Edge:31, Center:0
N7.C2: Read Vref - Strobe:11 Worst Left Edge:-31, Worst Right Edge:31, Center:0
N1.C2: Read Vref - Strobe:11 Worst Left Edge:-31, Worst Right Edge:31, Center:0
N7.C2: Read Vref - Strobe:12 Worst Left Edge:-31, Worst Right Edge:31, Center:0
N1.C2: Read Vref - Strobe:12 Worst Left Edge:-31, Worst Right Edge:31, Center:0
N7.C2: Read Vref - Strobe:13 Worst Left Edge:-31, Worst Right Edge:31, Center:0
N1.C2: Read Vref - Strobe:13 Worst Left Edge:-31, Worst Right Edge:31, Center:0
N7.C2: Read Vref - Strobe:14 Worst Left Edge:-31, Worst Right Edge:31, Center:0
N1.C2: Read Vref - Strobe:14 Worst Left Edge:-31, Worst Right Edge:31, Center:0
N7.C2: Read Vref - Strobe:15 Worst Left Edge:-31, Worst Right Edge:31, Center:0
N1.C2: Read Vref - Strobe:15 Worst Left Edge:-31, Worst Right Edge:31, Center:0
N7.C2: Read Vref - Strobe:16 Worst Left Edge:-31, Worst Right Edge:31, Center:0
N1.C2: Read Vref - Strobe:16 Worst Left Edge:-31, Worst Right Edge:31, Center:0
N7.C2: Read Vref - Strobe:17 Worst Left Edge:-31, Worst Right Edge:31, Center:0
N1.C2: Read Vref - Strobe:17 Worst Left Edge:-31, Worst Right Edge:31, Center:0
N4.C0: RdCmd2DataValidLatency = 17, (dlyFrmS = 11, clEff = 10, earlyCas = 0, selNTiming = 0)
N7.C3: Read Vref - Strobe:0 Worst Left Edge:-31, Worst Right Edge:31, Center:0
N1.C3: Read Vref - Strobe:0 Worst Left Edge:-31, Worst Right Edge:31, Center:0
N7.C3: Read Vref - Strobe:1 Worst Left Edge:-31, Worst Right Edge:31, Center:0
N1.C3: Read Vref - Strobe:1 Worst Left Edge:-30, Worst Right Edge:31, Center:0
N7.C3: Read Vref - Strobe:2 Worst Left Edge:-31, Worst Right Edge:31, Center:0
N1.C3: Read Vref - Strobe:2 Worst Left Edge:-31, Worst Right Edge:31, Center:0
N7.C3: Read Vref - Strobe:3 Worst Left Edge:-31, Worst Right Edge:31, Center:0
N1.C3: Read Vref - Strobe:3 Worst Left Edge:-31, Worst Right Edge:31, Center:0
N7.C3: Read Vref - Strobe:4 Worst Left Edge:-31, Worst Right Edge:31, Center:0
N1.C3: Read Vref - Strobe:4 Worst Left Edge:-29, Worst Right Edge:31, Center:1
N7.C3: Read Vref - Strobe:5 Worst Left Edge:-31, Worst Right Edge:31, Center:0
N1.C3: Read Vref - Strobe:5 Worst Left Edge:-31, Worst Right Edge:31, Center:0
N7.C3: Read Vref - Strobe:6 Worst Left Edge:-31, Worst Right Edge:31, Center:0
N1.C3: Read Vref - Strobe:6 Worst Left Edge:-31, Worst Right Edge:31, Center:0
N7.C3: Read Vref - Strobe:7 Worst Left Edge:-31, Worst Right Edge:31, Center:0
N1.C3: Read Vref - Strobe:7 Worst Left Edge:-31, Worst Right Edge:31, Center:0
N7.C3: Read Vref - Strobe:8 Worst Left Edge:-31, Worst Right Edge:31, Center:0
N1.C3: Read Vref - Strobe:8 Worst Left Edge:-31, Worst Right Edge:31, Center:0
N7.C3: Read Vref - Strobe:9 Worst Left Edge:-31, Worst Right Edge:31, Center:0
N1.C3: Read Vref - Strobe:9 Worst Left Edge:-31, Worst Right Edge:31, Center:0
N4.C1: RdCmd2DataValidLatency = 17, (dlyFrmS = 11, clEff = 10, earlyCas = 0, selNTiming = 0)
N7.C3: Read Vref - Strobe:10 Worst Left Edge:-31, Worst Right Edge:31, Center:0
N1.C3: Read Vref - Strobe:10 Worst Left Edge:-31, Worst Right Edge:31, Center:0
N7.C3: Read Vref - Strobe:11 Worst Left Edge:-31, Worst Right Edge:31, Center:0
N1.C3: Read Vref - Strobe:11 Worst Left Edge:-31, Worst Right Edge:31, Center:0
N7.C3: Read Vref - Strobe:12 Worst Left Edge:-31, Worst Right Edge:31, Center:0
N1.C3: Read Vref - Strobe:12 Worst Left Edge:-31, Worst Right Edge:31, Center:0
N7.C3: Read Vref - Strobe:13 Worst Left Edge:-31, Worst Right Edge:31, Center:0
N1.C3: Read Vref - Strobe:13 Worst Left Edge:-31, Worst Right Edge:31, Center:0
N2.C0.R1: CpgcMemTestRankSetup: colAddressBits = 11, rowAddressBits = 15, bankAddressBits = 3
N7.C3: Read Vref - Strobe:14 Worst Left Edge:-31, Worst Right Edge:31, Center:0
N1.C3: Read Vref - Strobe:14 Worst Left Edge:-31, Worst Right Edge:31, Center:0
N2.C1.R1: CpgcMemTestRankSetup: colAddressBits = 11, rowAddressBits = 15, bankAddressBits = 3
N7.C3: Read Vref - Strobe:15 Worst Left Edge:-31, Worst Right Edge:31, Center:0
N1.C3: Read Vref - Strobe:15 Worst Left Edge:-31, Worst Right Edge:31, Center:0
N2.C2.R1: CpgcMemTestRankSetup: colAddressBits = 11, rowAddressBits = 15, bankAddressBits = 3
N7.C3: Read Vref - Strobe:16 Worst Left Edge:-31, Worst Right Edge:31, Center:0
N1.C3: Read Vref - Strobe:16 Worst Left Edge:-31, Worst Right Edge:31, Center:0
N2.C3.R1: CpgcMemTestRankSetup: colAddressBits = 11, rowAddressBits = 15, bankAddressBits = 3
N7.C3: Read Vref - Strobe:17 Worst Left Edge:-31, Worst Right Edge:31, Center:0
N1.C3: Read Vref - Strobe:17 Worst Left Edge:-31, Worst Right Edge:31, Center:0
N3.C0.R1: CpgcMemTestRankSetup: colAddressBits = 11, rowAddressBits = 16, bankAddressBits = 3
N7: RunTrainStep: Final status = 0
N1: RunTrainStep: Final status = 0
N3.C1.R1: CpgcMemTestRankSetup: colAddressBits = 11, rowAddressBits = 16, bankAddressBits = 3
N4.C0: RdCmd2DataValidLatency = 16, (dlyFrmS = 10, clEff = 10, earlyCas = 0, selNTiming = 0)

END - Rd Voltage Training              Time         2948 ms

END - Rd Voltage Training              Time         2949 ms
N3.C2.R1: CpgcMemTestRankSetup: colAddressBits = 11, rowAddressBits = 16, bankAddressBits = 3
N7.C0.D0.R0.S00: StoreJckWorstRank: worst rank = 0, greatestDelay = 1302
N1.C0.D0.R0.S00: StoreJckWorstRank: worst rank = 0, greatestDelay = 1304
N3.C3.R1: CpgcMemTestRankSetup: colAddressBits = 11, rowAddressBits = 16, bankAddressBits = 3
N7.C0.D0.R0.S07: StoreJckWorstRank: worst rank = 0, greatestDelay = 1308
N1.C0.D0.R0.S07: StoreJckWorstRank: worst rank = 0, greatestDelay = 1307
N7.C1.D0.R0.S00: StoreJckWorstRank: worst rank = 0, greatestDelay = 1363
N1.C1.D0.R0.S00: StoreJckWorstRank: worst rank = 0, greatestDelay = 1355
N7.C1.D0.R0.S09: StoreJckWorstRank: worst rank = 0, greatestDelay = 1364
N1.C0: StoreJckWorstRank: final value: worst rank = 0
N7.C1.D0.R1.S09: StoreJckWorstRank: worst rank = 1, greatestDelay = 1365
N1.C2.D0.R0.S00: StoreJckWorstRank: worst rank = 0, greatestDelay = 1314
N7.C0: StoreJckWorstRank: final value: worst rank = 1
N1.C3.D0.R0.S00: StoreJckWorstRank: worst rank = 0, greatestDelay = 1351
N7.C2.D0.R0.S00: StoreJckWorstRank: worst rank = 0, greatestDelay = 1309
N1.C3.D0.R0.S09: StoreJckWorstRank: worst rank = 0, greatestDelay = 1354
N7.C3.D0.R0.S00: StoreJckWorstRank: worst rank = 0, greatestDelay = 1362
N1.C1: StoreJckWorstRank: final value: worst rank = 0
N7.C3.D0.R0.S09: StoreJckWorstRank: worst rank = 0, greatestDelay = 1364
GetAllRankMargins
N7.C1: StoreJckWorstRank: final value: worst rank = 0
N1: Checking margins for all ranks...
N4.C1: RdCmd2DataValidLatency = 16, (dlyFrmS = 10, clEff = 10, earlyCas = 0, selNTiming = 0)
GetAllRankMargins
Checkpoint Code: Socket 0, 0xB7, 0x17, 0x0000
N7: Checking margins for all ranks...
N1: 
Get Rx Dqs margins...
N7: 
Get Rx Dqs margins...
N1: GetMargins: Level = 1, group = 11, mode = 0, scope = 3
N7: GetMargins: Level = 1, group = 11, mode = 0, scope = 3
N4.C0: RdCmd2DataValidLatency = 15, (dlyFrmS = 9, clEff = 10, earlyCas = 0, selNTiming = 0)
N1: 
Get Tx Dq margins...
N1: GetMargins: Level = 1, group = 12, mode = 0, scope = 3
N4.C1: RdCmd2DataValidLatency = 15, (dlyFrmS = 9, clEff = 10, earlyCas = 0, selNTiming = 0)
N7: 
Get Tx Dq margins...
N7: GetMargins: Level = 1, group = 12, mode = 0, scope = 3
N4.C0: RdCmd2DataValidLatency = 14, (dlyFrmS = 8, clEff = 10, earlyCas = 0, selNTiming = 0)
N2.C0.R4: CpgcMemTestRankSetup: colAddressBits = 11, rowAddressBits = 15, bankAddressBits = 3
N4.C1: RdCmd2DataValidLatency = 14, (dlyFrmS = 8, clEff = 10, earlyCas = 0, selNTiming = 0)
N2.C1.R4: CpgcMemTestRankSetup: colAddressBits = 11, rowAddressBits = 15, bankAddressBits = 3
N2.C2.R4: CpgcMemTestRankSetup: colAddressBits = 11, rowAddressBits = 15, bankAddressBits = 3
N2.C3.R4: CpgcMemTestRankSetup: colAddressBits = 11, rowAddressBits = 15, bankAddressBits = 3
N1: 
Get Rx Vref margins...
N1: GetMargins: Level = 1, group = 13, mode = 0, scope = 3
N4.C0: RdCmd2DataValidLatency = 16, (dlyFrmS = 10, clEff = 10, earlyCas = 0, selNTiming = 0)
N7: 
Get Rx Vref margins...
N7: GetMargins: Level = 1, group = 13, mode = 0, scope = 3
N4.C1: RdCmd2DataValidLatency = 16, (dlyFrmS = 10, clEff = 10, earlyCas = 0, selNTiming = 0)
N2.C0.R5: CpgcMemTestRankSetup: colAddressBits = 11, rowAddressBits = 15, bankAddressBits = 3
N2.C1.R5: CpgcMemTestRankSetup: colAddressBits = 11, rowAddressBits = 15, bankAddressBits = 3
N2.C2.R5: CpgcMemTestRankSetup: colAddressBits = 11, rowAddressBits = 15, bankAddressBits = 3
N2.C3.R5: CpgcMemTestRankSetup: colAddressBits = 11, rowAddressBits = 15, bankAddressBits = 3
N4.C0: AdjustTotalRoundTripTime: SUCCESS - worst rank = 0, host round trip = 75, MXB cmd2dat = 10
N4.C2: AdjustTotalRoundTripTime
N4.C1: AdjustTotalRoundTripTime: worstRank = 0
N4.C2: AdjustTotalRoundTripTime: worstRank dimm = 0, rank = 0
N4.C3: AdjustTotalRoundTripTime: worstRank dimm = 0, rank = 0
N4.C1: AdjustTotalRoundTripTime: ddrChMask = 0xC
N4.C2: RdCmd2DataValidLatency = 20, (dlyFrmS = 14, clEff = 10, earlyCas = 0, selNTiming = 0)
N1: 
Get Tx Vref margins...
N1: GetMargins: Level = 1, group = 14, mode = 0, scope = 3
N7: 
Get Tx Vref margins...
N7: GetMargins: Level = 1, group = 14, mode = 0, scope = 3
N4.C3: RdCmd2DataValidLatency = 20, (dlyFrmS = 14, clEff = 10, earlyCas = 0, selNTiming = 0)

ECC init time = 3184 ms
N4.C2: RdCmd2DataValidLatency = 19, (dlyFrmS = 13, clEff = 10, earlyCas = 0, selNTiming = 0)
N2: PcodeRcompEnable
N2: PCU RD CMD Success: MboxStatus = 0x0 Default PCUData Value = 0x9840000
N2: PCU WR CMD Success: MBoxStatus = 0x0 PCU_MISC_CONFIG = 0x8840000
N2: Set rst_cpl2 to enable RCOMP
N2: InitThrottling
N2: Init Throttling

N2: 
::MPM:: 2> dimmInWTTable = 0, WTcurrentDimm.WTLvAndDramDensity = 3,   ddrVoltage = 0

N2: 
::MEM DDR3:: DDR3 Memory detected. Look at DDR3 Power table now...
N2.C0.D0: Init DRAM RAPL

N2.C0.D0: MTS mfgid = 0x4A10
N2.C0.D0: MTS did_rid = 0x3
N2.C0.D0: MTS Capabilities = 0x6F00
N2.C0.D0: MTS Current Ambient Temp = 0x10C2
N2.C0.D0: TCRIT  = 0x690
N2: 
::MPM:: 2> dimmInWTTable = 0, WTcurrentDimm.WTLvAndDramDensity = 3,   ddrVoltage = 0

N2: 
::MEM DDR3:: DDR3 Memory detected. Look at DDR3 Power table now...
N2.C0.D1: Init DRAM RAPL

N2.C0.D1: MTS mfgid = 0x4A10
N2.C0.D1: MTS did_rid = 0x3
N2.C0.D1: MTS Capabilities = 0x6F00
N2.C0.D1: MTS Current Ambient Temp = 0xF4C1
N2.C0.D1: TCRIT  = 0x690
N2: 
::MPM:: 2> dimmInWTTable = 0, WTcurrentDimm.WTLvAndDramDensity = 3,   ddrVoltage = 0

N2: 
::MEM DDR3:: DDR3 Memory detected. Look at DDR3 Power table now...
N2.C1.D0: Init DRAM RAPL

N2.C1.D0: MTS mfgid = 0x4A10
N2.C1.D0: MTS did_rid = 0x3
N2.C1.D0: MTS Capabilities = 0x6F00
N2.C1.D0: MTS Current Ambient Temp = 0x18C2
N2.C1.D0: TCRIT  = 0x690
N2: 
::MPM:: 2> dimmInWTTable = 0, WTcurrentDimm.WTLvAndDramDensity = 3,   ddrVoltage = 0

N2: 
::MEM DDR3:: DDR3 Memory detected. Look at DDR3 Power table now...
N2.C1.D1: Init DRAM RAPL

N2.C1.D1: MTS mfgid = 0x4A10
N2.C1.D1: MTS did_rid = 0x3
N2.C1.D1: MTS Capabilities = 0x6F00
N2.C1.D1: MTS Current Ambient Temp = 0x10C2
N2.C1.D1: TCRIT  = 0x690
N2: SMBCNTL_0 = 0x38000033
N2: 
::MPM:: 2> dimmInWTTable = 0, WTcurrentDimm.WTLvAndDramDensity = 3,   ddrVoltage = 0

N2: 
::MEM DDR3:: DDR3 Memory detected. Look at DDR3 Power table now...
N2.C2.D0: Init DRAM RAPL

N2.C2.D0: MTS mfgid = 0x4A10
N2.C2.D0: MTS did_rid = 0x3
N2.C2.D0: MTS Capabilities = 0x6F00
N2.C2.D0: MTS Current Ambient Temp = 0xDCC1
N2.C2.D0: TCRIT  = 0x690
N2: 
::MPM:: 2> dimmInWTTable = 0, WTcurrentDimm.WTLvAndDramDensity = 3,   ddrVoltage = 0

N2: 
::MEM DDR3:: DDR3 Memory detected. Look at DDR3 Power table now...
N2.C2.D1: Init DRAM RAPL

N2.C2.D1: MTS mfgid = 0x4A10
N2.C2.D1: MTS did_rid = 0x3
N2.C2.D1: MTS Capabilities = 0x6F00
N2.C2.D1: MTS Current Ambient Temp = 0xC8C1
N2.C2.D1: TCRIT  = 0x690
N2: 
::MPM:: 2> dimmInWTTable = 0, WTcurrentDimm.WTLvAndDramDensity = 3,   ddrVoltage = 0

N2: 
::MEM DDR3:: DDR3 Memory detected. Look at DDR3 Power table now...
N2.C3.D0: Init DRAM RAPL

N2.C3.D0: MTS mfgid = 0x4A10
N2.C3.D0: MTS did_rid = 0x3
N2.C3.D0: MTS Capabilities = 0x6F00
N2.C3.D0: MTS Current Ambient Temp = 0xB4C1
N2.C3.D0: TCRIT  = 0x690
N2: 
::MPM:: 2> dimmInWTTable = 0, WTcurrentDimm.WTLvAndDramDensity = 3,   ddrVoltage = 0

N2: 
::MEM DDR3:: DDR3 Memory detected. Look at DDR3 Power table now...
N2.C3.D1: Init DRAM RAPL

N2.C3.D1: MTS mfgid = 0x4A10
N2.C3.D1: MTS did_rid = 0x3
N2.C3.D1: MTS Capabilities = 0x6F00
N2.C3.D1: MTS Current Ambient Temp = 0xC4C1
N2.C3.D1: TCRIT  = 0x690
N2: SMBCNTL_1 = 0x38000033
N2: 
Init DRAM Phase Shedding
N2: Memory current estimate value 20
N2: Setting Node 0x2 - VR0 Active PSI = PS0
N2: Memory current estimate value 20
N2: Setting Node 0x2 - VR1 Active PSI = PS0
N4.C3: RdCmd2DataValidLatency = 19, (dlyFrmS = 13, clEff = 10, earlyCas = 0, selNTiming = 0)
N2: SwitchToNormalMode
N2: SetupMiscFeatures
N2: Clear Errors
N3: PcodeRcompEnable
N3: PCU RD CMD Success: MboxStatus = 0x0 Default PCUData Value = 0x8840000
N3: PCU WR CMD Success: MBoxStatus = 0x0 PCU_MISC_CONFIG = 0x8840000
N3: InitThrottling
N3: Init Throttling

N3: 
::MPM:: 2> dimmInWTTable = 0, WTcurrentDimm.WTLvAndDramDensity = 4,   ddrVoltage = 0

N3: 
::MEM DDR3:: DDR3 Memory detected. Look at DDR3 Power table now...
N3.C0.D0: Init DRAM RAPL

N3.C0.D0: MTS mfgid = 0x4A10
N3.C0.D0: MTS did_rid = 0x3
N3.C0.D0: MTS Capabilities = 0x6F00
N3.C0.D0: MTS Current Ambient Temp = 0xC0C1
N3.C0.D0: TCRIT  = 0x690
N3: 
::MPM:: 2> dimmInWTTable = 0, WTcurrentDimm.WTLvAndDramDensity = 4,   ddrVoltage = 0

N3: 
::MEM DDR3:: DDR3 Memory detected. Look at DDR3 Power table now...
N3.C1.D0: Init DRAM RAPL

N3.C1.D0: MTS mfgid = 0x4A10
N3.C1.D0: MTS did_rid = 0x3
N3.C1.D0: MTS Capabilities = 0x6F00
N3.C1.D0: MTS Current Ambient Temp = 0xD0C1
N3.C1.D0: TCRIT  = 0x690
N3: SMBCNTL_0 = 0x38000011
N3: 
::MPM:: 2> dimmInWTTable = 0, WTcurrentDimm.WTLvAndDramDensity = 4,   ddrVoltage = 0

N3: 
::MEM DDR3:: DDR3 Memory detected. Look at DDR3 Power table now...
N3.C2.D0: Init DRAM RAPL

N3.C2.D0: MTS mfgid = 0x4A10
N3.C2.D0: MTS did_rid = 0x3
N3.C2.D0: MTS Capabilities = 0x6F00
N3.C2.D0: MTS Current Ambient Temp = 0xA4C1
N3.C2.D0: TCRIT  = 0x690
N3: 
::MPM:: 2> dimmInWTTable = 0, WTcurrentDimm.WTLvAndDramDensity = 4,   ddrVoltage = 0

N3: 
::MEM DDR3:: DDR3 Memory detected. Look at DDR3 Power table now...
N3.C3.D0: Init DRAM RAPL

N3.C3.D0: MTS mfgid = 0x4A10
N3.C3.D0: MTS did_rid = 0x3
N3.C3.D0: MTS Capabilities = 0x6F00
N3.C3.D0: MTS Current Ambient Temp = 0xB0C1
N3.C3.D0: TCRIT  = 0x690
N3: SMBCNTL_1 = 0x38000011
N3: 
Init DRAM Phase Shedding
N3: Memory current estimate value E
N3: Setting Node 0x3 - VR2 Active PSI = PS1
N3: Memory current estimate value E
N3: Setting Node 0x3 - VR3 Active PSI = PS1
N4.C2: RdCmd2DataValidLatency = 18, (dlyFrmS = 12, clEff = 10, earlyCas = 0, selNTiming = 0)
N1: 
 Time to do RMT patterns 15  is 2 seconds 
N3: SwitchToNormalMode
N7: 
 Time to do RMT patterns 15  is 2 seconds 

            RxDqLeft RxDqRight RxVLow RxVHigh TxDqLeft TxDqRight TxVLow TxVHigh
--------------------------------------------------------------------------------
N1.C0.D0.R0:   -20       21       -48       48      -22     22      -27      28
N1.C0.D0.R1:   -20       21       -48       48      -22     22      -28      27
N1.C1.D0.R0:   -22       22       -30       48      -23     22      -26      25
N1.C1.D0.R1:   -22       20       -29       48      -21     21      -26      23
N1.C2.D0.R0:   -21       21       -48       48      -24     23      -28      28
N1.C2.D0.R1:   -22       21       -48       48      -24     23      -29      29
N1.C3.D0.R0:   -17       20       -30       48      -22     22      -25      25
N1.C3.D0.R1:   -18       19       -30       48      -22     23      -25      24
STOP_RMT_N1
N3: SetupMiscFeatures

            RxDqLeft RxDqRight RxVLow RxVHigh TxDqLeft TxDqRight TxVLow TxVHigh
--------------------------------------------------------------------------------
N7.C0.D0.R0:   -21       22       -48       48      -22     23      -29      27
N7.C0.D0.R1:   -22       22       -48       48      -23     23      -30      28
N7.C1.D0.R0:   -21       21       -29       48      -22     22      -26      26
N7.C1.D0.R1:   -21       20       -29       48      -22     21      -26      27
N7.C2.D0.R0:   -20       20       -48       48      -22     23      -29      28
N7.C2.D0.R1:   -20       19       -48       48      -22     23      -29      29
N7.C3.D0.R0:   -21       20       -48       48      -23     22      -26      25
N7.C3.D0.R1:   -20       20       -48       48      -22     21      -25      26
STOP_RMT_N7
N1: GetAllRankMargins time            2483 ms
N3: Clear Errors
N4.C3: RdCmd2DataValidLatency = 18, (dlyFrmS = 12, clEff = 10, earlyCas = 0, selNTiming = 0)
N7: GetAllRankMargins time            2569 ms
N1: 
Total DDR trainings latency = 105951 ms
N7: 
Total DDR trainings latency = 105959 ms
N0: PostDdrTraining
N6: PostDdrTraining
N1: PostDdrTraining
N7: PostDdrTraining
Checkpoint Code: Socket 0, 0xB7, 0x10, 0x0000
N6.C0.D0: CheckRankPopLocal: dimmPresent: 1, numRanks = 2
Checkpoint Code: Socket 0, 0xB9, 0x00, 0x0000
N6.C0.D0.R0: CheckRankPopLocal: mapOut: 0, enabled = 1
N0.C0.D0: CheckRankPopLocal: dimmPresent: 1, numRanks = 2
N6.C0.D0.R1: CheckRankPopLocal: mapOut: 0, enabled = 1
N0.C0.D0.R0: CheckRankPopLocal: mapOut: 0, enabled = 1
N6.C0.D1: CheckRankPopLocal: dimmPresent: 1, numRanks = 2
N0.C0.D0.R1: CheckRankPopLocal: mapOut: 0, enabled = 1
N6.C0.D1.R0: CheckRankPopLocal: mapOut: 0, enabled = 1
N0.C0.D1: CheckRankPopLocal: dimmPresent: 1, numRanks = 2
N6.C0.D1.R1: CheckRankPopLocal: mapOut: 0, enabled = 1
N0.C0.D1.R0: CheckRankPopLocal: mapOut: 0, enabled = 1
N6.C0.D2: CheckRankPopLocal: dimmPresent: 0, numRanks = 0
N0.C0.D1.R1: CheckRankPopLocal: mapOut: 0, enabled = 1
N6.C0.D0: CheckRankPopLocal: amap: 0x00000000
N0.C0.D2: CheckRankPopLocal: dimmPresent: 0, numRanks = 0
N6.C0.D1: CheckRankPopLocal: amap: 0x00000000
N0.C0.D0: CheckRankPopLocal: amap: 0x00000000
N6.C0.D2: CheckRankPopLocal: amap: 0x00000000
N0.C0.D1: CheckRankPopLocal: amap: 0x00000000
N6.C1.D0: CheckRankPopLocal: dimmPresent: 1, numRanks = 2
N0.C0.D2: CheckRankPopLocal: amap: 0x00000000
N6.C1.D0.R0: CheckRankPopLocal: mapOut: 0, enabled = 1
N0.C1.D0: CheckRankPopLocal: dimmPresent: 1, numRanks = 2
N6.C1.D0.R1: CheckRankPopLocal: mapOut: 0, enabled = 1
N0.C1.D0.R0: CheckRankPopLocal: mapOut: 0, enabled = 1
N6.C1.D1: CheckRankPopLocal: dimmPresent: 1, numRanks = 2
N0.C1.D0.R1: CheckRankPopLocal: mapOut: 0, enabled = 1
N6.C1.D1.R0: CheckRankPopLocal: mapOut: 0, enabled = 1
N0.C1.D1: CheckRankPopLocal: dimmPresent: 1, numRanks = 2
N4.C2: RdCmd2DataValidLatency = 17, (dlyFrmS = 11, clEff = 10, earlyCas = 0, selNTiming = 0)
N6.C1.D1.R1: CheckRankPopLocal: mapOut: 0, enabled = 1
N0.C1.D1.R0: CheckRankPopLocal: mapOut: 0, enabled = 1
N6.C1.D2: CheckRankPopLocal: dimmPresent: 0, numRanks = 0
N0.C1.D1.R1: CheckRankPopLocal: mapOut: 0, enabled = 1
N6.C1.D0: CheckRankPopLocal: amap: 0x00000000
N0.C1.D2: CheckRankPopLocal: dimmPresent: 0, numRanks = 0
N6.C1.D1: CheckRankPopLocal: amap: 0x00000000
N0.C1.D0: CheckRankPopLocal: amap: 0x00000000
N6.C1.D2: CheckRankPopLocal: amap: 0x00000000
N0.C1.D1: CheckRankPopLocal: amap: 0x00000000
N6.C2.D0: CheckRankPopLocal: dimmPresent: 1, numRanks = 2
N0.C1.D2: CheckRankPopLocal: amap: 0x00000000
N6.C2.D0.R0: CheckRankPopLocal: mapOut: 0, enabled = 1
N0.C2.D0: CheckRankPopLocal: dimmPresent: 1, numRanks = 2
N6.C2.D0.R1: CheckRankPopLocal: mapOut: 0, enabled = 1
N0.C2.D0.R0: CheckRankPopLocal: mapOut: 0, enabled = 1
N6.C2.D1: CheckRankPopLocal: dimmPresent: 1, numRanks = 2
N0.C2.D0.R1: CheckRankPopLocal: mapOut: 0, enabled = 1
N6.C2.D1.R0: CheckRankPopLocal: mapOut: 0, enabled = 1
N0.C2.D1: CheckRankPopLocal: dimmPresent: 1, numRanks = 2
N6.C2.D1.R1: CheckRankPopLocal: mapOut: 0, enabled = 1
N0.C2.D1.R0: CheckRankPopLocal: mapOut: 0, enabled = 1
N6.C2.D2: CheckRankPopLocal: dimmPresent: 0, numRanks = 0
N0.C2.D1.R1: CheckRankPopLocal: mapOut: 0, enabled = 1
N6.C2.D0: CheckRankPopLocal: amap: 0x00000000
N0.C2.D2: CheckRankPopLocal: dimmPresent: 0, numRanks = 0
N6.C2.D1: CheckRankPopLocal: amap: 0x00000000
N0.C2.D0: CheckRankPopLocal: amap: 0x00000000
N6.C2.D2: CheckRankPopLocal: amap: 0x00000000
N0.C2.D1: CheckRankPopLocal: amap: 0x00000000
N4.C3: RdCmd2DataValidLatency = 17, (dlyFrmS = 11, clEff = 10, earlyCas = 0, selNTiming = 0)
N6.C3.D0: CheckRankPopLocal: dimmPresent: 1, numRanks = 2
N0.C2.D2: CheckRankPopLocal: amap: 0x00000000
N6.C3.D0.R0: CheckRankPopLocal: mapOut: 0, enabled = 1
N0.C3.D0: CheckRankPopLocal: dimmPresent: 1, numRanks = 2
N6.C3.D0.R1: CheckRankPopLocal: mapOut: 0, enabled = 1
N0.C3.D0.R0: CheckRankPopLocal: mapOut: 0, enabled = 1
N6.C3.D1: CheckRankPopLocal: dimmPresent: 1, numRanks = 2
N0.C3.D0.R1: CheckRankPopLocal: mapOut: 0, enabled = 1
N6.C3.D1.R0: CheckRankPopLocal: mapOut: 0, enabled = 1
N0.C3.D1: CheckRankPopLocal: dimmPresent: 1, numRanks = 2
N6.C3.D1.R1: CheckRankPopLocal: mapOut: 0, enabled = 1
N0.C3.D1.R0: CheckRankPopLocal: mapOut: 0, enabled = 1
N6.C3.D2: CheckRankPopLocal: dimmPresent: 0, numRanks = 0
N0.C3.D1.R1: CheckRankPopLocal: mapOut: 0, enabled = 1
N6.C3.D0: CheckRankPopLocal: amap: 0x00000000
N0.C3.D2: CheckRankPopLocal: dimmPresent: 0, numRanks = 0
N6.C3.D1: CheckRankPopLocal: amap: 0x00000000
N0.C3.D0: CheckRankPopLocal: amap: 0x00000000
N6.C3.D2: CheckRankPopLocal: amap: 0x00000000
N0.C3.D1: CheckRankPopLocal: amap: 0x00000000
N6.C0: AdjustTotalRoundTripTime
N0.C3.D2: CheckRankPopLocal: amap: 0x00000000
N6.C0: AdjustTotalRoundTripTime: worstRank = 1
N0.C0: AdjustTotalRoundTripTime
N6.C0: AdjustTotalRoundTripTime: worstRank dimm = 0, rank = 1
N0.C0: AdjustTotalRoundTripTime: worstRank = 1
N6.C1: AdjustTotalRoundTripTime: worstRank dimm = 0, rank = 1
N0.C0: AdjustTotalRoundTripTime: worstRank dimm = 0, rank = 1
N6.C0: AdjustTotalRoundTripTime: ddrChMask = 0x3
N0.C1: AdjustTotalRoundTripTime: worstRank dimm = 0, rank = 1
N0.C0: AdjustTotalRoundTripTime: ddrChMask = 0x3
N6.C0: RdCmd2DataValidLatency = 20, (dlyFrmS = 14, clEff = 10, earlyCas = 0, selNTiming = 0)
N4.C2: RdCmd2DataValidLatency = 16, (dlyFrmS = 10, clEff = 10, earlyCas = 0, selNTiming = 0)
N0.C0: RdCmd2DataValidLatency = 20, (dlyFrmS = 14, clEff = 10, earlyCas = 0, selNTiming = 0)
N6.C1: RdCmd2DataValidLatency = 20, (dlyFrmS = 14, clEff = 10, earlyCas = 0, selNTiming = 0)
N4.C3: RdCmd2DataValidLatency = 16, (dlyFrmS = 10, clEff = 10, earlyCas = 0, selNTiming = 0)
N0.C1: RdCmd2DataValidLatency = 20, (dlyFrmS = 14, clEff = 10, earlyCas = 0, selNTiming = 0)
N6.C0: RdCmd2DataValidLatency = 19, (dlyFrmS = 13, clEff = 10, earlyCas = 0, selNTiming = 0)
N4.C2: RdCmd2DataValidLatency = 15, (dlyFrmS = 9, clEff = 10, earlyCas = 0, selNTiming = 0)
N0.C0: RdCmd2DataValidLatency = 19, (dlyFrmS = 13, clEff = 10, earlyCas = 0, selNTiming = 0)
N6.C1: RdCmd2DataValidLatency = 19, (dlyFrmS = 13, clEff = 10, earlyCas = 0, selNTiming = 0)
N4.C3: RdCmd2DataValidLatency = 15, (dlyFrmS = 9, clEff = 10, earlyCas = 0, selNTiming = 0)
N0.C1: RdCmd2DataValidLatency = 19, (dlyFrmS = 13, clEff = 10, earlyCas = 0, selNTiming = 0)
N6.C0: RdCmd2DataValidLatency = 18, (dlyFrmS = 12, clEff = 10, earlyCas = 0, selNTiming = 0)
N4.C2: RdCmd2DataValidLatency = 14, (dlyFrmS = 8, clEff = 10, earlyCas = 0, selNTiming = 0)
N0.C0: RdCmd2DataValidLatency = 18, (dlyFrmS = 12, clEff = 10, earlyCas = 0, selNTiming = 0)
N6.C1: RdCmd2DataValidLatency = 18, (dlyFrmS = 12, clEff = 10, earlyCas = 0, selNTiming = 0)
N4.C3: RdCmd2DataValidLatency = 14, (dlyFrmS = 8, clEff = 10, earlyCas = 0, selNTiming = 0)
N0.C1: RdCmd2DataValidLatency = 18, (dlyFrmS = 12, clEff = 10, earlyCas = 0, selNTiming = 0)
N6.C0: RdCmd2DataValidLatency = 17, (dlyFrmS = 11, clEff = 10, earlyCas = 0, selNTiming = 0)
N4.C2: RdCmd2DataValidLatency = 16, (dlyFrmS = 10, clEff = 10, earlyCas = 0, selNTiming = 0)
N0.C0: RdCmd2DataValidLatency = 17, (dlyFrmS = 11, clEff = 10, earlyCas = 0, selNTiming = 0)
N6.C1: RdCmd2DataValidLatency = 17, (dlyFrmS = 11, clEff = 10, earlyCas = 0, selNTiming = 0)
N4.C3: RdCmd2DataValidLatency = 16, (dlyFrmS = 10, clEff = 10, earlyCas = 0, selNTiming = 0)
N0.C1: RdCmd2DataValidLatency = 17, (dlyFrmS = 11, clEff = 10, earlyCas = 0, selNTiming = 0)
N4.C2: AdjustTotalRoundTripTime: SUCCESS - worst rank = 0, host round trip = 73, MXB cmd2dat = 10
N5.C0.D0: CheckRankPopLocal: dimmPresent: 1, numRanks = 2
N6.C0: RdCmd2DataValidLatency = 16, (dlyFrmS = 10, clEff = 10, earlyCas = 0, selNTiming = 0)
N5.C0.D0.R0: CheckRankPopLocal: mapOut: 0, enabled = 1
N0.C0: RdCmd2DataValidLatency = 16, (dlyFrmS = 10, clEff = 10, earlyCas = 0, selNTiming = 0)
N5.C0.D0.R1: CheckRankPopLocal: mapOut: 0, enabled = 1
N5.C0.D1: CheckRankPopLocal: dimmPresent: 0, numRanks = 0
N5.C0.D2: CheckRankPopLocal: dimmPresent: 0, numRanks = 0
N5.C0.D0: CheckRankPopLocal: amap: 0x00000000
N5.C0.D1: CheckRankPopLocal: amap: 0x00000000
N5.C0.D2: CheckRankPopLocal: amap: 0x00000000
N5.C1.D0: CheckRankPopLocal: dimmPresent: 1, numRanks = 2
N5.C1.D0.R0: CheckRankPopLocal: mapOut: 0, enabled = 1
N5.C1.D0.R1: CheckRankPopLocal: mapOut: 0, enabled = 1
N5.C1.D1: CheckRankPopLocal: dimmPresent: 0, numRanks = 0
N5.C1.D2: CheckRankPopLocal: dimmPresent: 0, numRanks = 0
N5.C1.D0: CheckRankPopLocal: amap: 0x00000000
N5.C1.D1: CheckRankPopLocal: amap: 0x00000000
N5.C1.D2: CheckRankPopLocal: amap: 0x00000000
N5.C2.D0: CheckRankPopLocal: dimmPresent: 1, numRanks = 2
N5.C2.D0.R0: CheckRankPopLocal: mapOut: 0, enabled = 1
N5.C2.D0.R1: CheckRankPopLocal: mapOut: 0, enabled = 1
N5.C2.D1: CheckRankPopLocal: dimmPresent: 0, numRanks = 0
N5.C2.D2: CheckRankPopLocal: dimmPresent: 0, numRanks = 0
N5.C2.D0: CheckRankPopLocal: amap: 0x00000000
N5.C2.D1: CheckRankPopLocal: amap: 0x00000000
N5.C2.D2: CheckRankPopLocal: amap: 0x00000000
N5.C3.D0: CheckRankPopLocal: dimmPresent: 1, numRanks = 2
N5.C3.D0.R0: CheckRankPopLocal: mapOut: 0, enabled = 1
N5.C3.D0.R1: CheckRankPopLocal: mapOut: 0, enabled = 1
N5.C3.D1: CheckRankPopLocal: dimmPresent: 0, numRanks = 0
N5.C3.D2: CheckRankPopLocal: dimmPresent: 0, numRanks = 0
N6.C1: RdCmd2DataValidLatency = 16, (dlyFrmS = 10, clEff = 10, earlyCas = 0, selNTiming = 0)
N5.C3.D0: CheckRankPopLocal: amap: 0x00000000
N0.C1: RdCmd2DataValidLatency = 16, (dlyFrmS = 10, clEff = 10, earlyCas = 0, selNTiming = 0)
N5.C3.D1: CheckRankPopLocal: amap: 0x00000000
N5.C3.D2: CheckRankPopLocal: amap: 0x00000000
N5.C0: AdjustTotalRoundTripTime
N5.C0: AdjustTotalRoundTripTime: worstRank = 0
N5.C0: AdjustTotalRoundTripTime: worstRank dimm = 0, rank = 0
N5.C1: AdjustTotalRoundTripTime: worstRank dimm = 0, rank = 0
N5.C0: AdjustTotalRoundTripTime: ddrChMask = 0x3
N5.C0: RdCmd2DataValidLatency = 20, (dlyFrmS = 14, clEff = 10, earlyCas = 0, selNTiming = 0)
N6.C0: RdCmd2DataValidLatency = 15, (dlyFrmS = 9, clEff = 10, earlyCas = 0, selNTiming = 0)
N0.C0: RdCmd2DataValidLatency = 15, (dlyFrmS = 9, clEff = 10, earlyCas = 0, selNTiming = 0)
N5.C1: RdCmd2DataValidLatency = 20, (dlyFrmS = 14, clEff = 10, earlyCas = 0, selNTiming = 0)
N6.C1: RdCmd2DataValidLatency = 15, (dlyFrmS = 9, clEff = 10, earlyCas = 0, selNTiming = 0)
N0.C1: RdCmd2DataValidLatency = 15, (dlyFrmS = 9, clEff = 10, earlyCas = 0, selNTiming = 0)
N5.C0: RdCmd2DataValidLatency = 19, (dlyFrmS = 13, clEff = 10, earlyCas = 0, selNTiming = 0)
N6.C0: RdCmd2DataValidLatency = 14, (dlyFrmS = 8, clEff = 10, earlyCas = 0, selNTiming = 0)
N0.C0: RdCmd2DataValidLatency = 14, (dlyFrmS = 8, clEff = 10, earlyCas = 0, selNTiming = 0)
N5.C1: RdCmd2DataValidLatency = 19, (dlyFrmS = 13, clEff = 10, earlyCas = 0, selNTiming = 0)
N6.C1: RdCmd2DataValidLatency = 14, (dlyFrmS = 8, clEff = 10, earlyCas = 0, selNTiming = 0)
N0.C1: RdCmd2DataValidLatency = 14, (dlyFrmS = 8, clEff = 10, earlyCas = 0, selNTiming = 0)
N5.C0: RdCmd2DataValidLatency = 18, (dlyFrmS = 12, clEff = 10, earlyCas = 0, selNTiming = 0)
N6.C0: RdCmd2DataValidLatency = 16, (dlyFrmS = 10, clEff = 10, earlyCas = 0, selNTiming = 0)
N0.C0: RdCmd2DataValidLatency = 16, (dlyFrmS = 10, clEff = 10, earlyCas = 0, selNTiming = 0)
N5.C1: RdCmd2DataValidLatency = 18, (dlyFrmS = 12, clEff = 10, earlyCas = 0, selNTiming = 0)
N6.C1: RdCmd2DataValidLatency = 16, (dlyFrmS = 10, clEff = 10, earlyCas = 0, selNTiming = 0)
N0.C1: RdCmd2DataValidLatency = 16, (dlyFrmS = 10, clEff = 10, earlyCas = 0, selNTiming = 0)
N5.C0: RdCmd2DataValidLatency = 17, (dlyFrmS = 11, clEff = 10, earlyCas = 0, selNTiming = 0)
N6.C0: AdjustTotalRoundTripTime: SUCCESS - worst rank = 1, host round trip = 75, MXB cmd2dat = 10
N6.C2: AdjustTotalRoundTripTime
N6.C1: AdjustTotalRoundTripTime: worstRank = 1
N0.C0: AdjustTotalRoundTripTime: SUCCESS - worst rank = 1, host round trip = 73, MXB cmd2dat = 10
N6.C2: AdjustTotalRoundTripTime: worstRank dimm = 0, rank = 1
N0.C2: AdjustTotalRoundTripTime
N6.C3: AdjustTotalRoundTripTime: worstRank dimm = 0, rank = 1
N0.C1: AdjustTotalRoundTripTime: worstRank = 0
N6.C1: AdjustTotalRoundTripTime: ddrChMask = 0xC
N0.C2: AdjustTotalRoundTripTime: worstRank dimm = 0, rank = 0
N0.C3: AdjustTotalRoundTripTime: worstRank dimm = 0, rank = 0
N0.C1: AdjustTotalRoundTripTime: ddrChMask = 0xC
N6.C2: RdCmd2DataValidLatency = 20, (dlyFrmS = 14, clEff = 10, earlyCas = 0, selNTiming = 0)
N5.C1: RdCmd2DataValidLatency = 17, (dlyFrmS = 11, clEff = 10, earlyCas = 0, selNTiming = 0)
N0.C2: RdCmd2DataValidLatency = 20, (dlyFrmS = 14, clEff = 10, earlyCas = 0, selNTiming = 0)
N6.C3: RdCmd2DataValidLatency = 20, (dlyFrmS = 14, clEff = 10, earlyCas = 0, selNTiming = 0)
N0.C3: RdCmd2DataValidLatency = 20, (dlyFrmS = 14, clEff = 10, earlyCas = 0, selNTiming = 0)
N5.C0: RdCmd2DataValidLatency = 16, (dlyFrmS = 10, clEff = 10, earlyCas = 0, selNTiming = 0)
N6.C2: RdCmd2DataValidLatency = 19, (dlyFrmS = 13, clEff = 10, earlyCas = 0, selNTiming = 0)
N5.C1: RdCmd2DataValidLatency = 16, (dlyFrmS = 10, clEff = 10, earlyCas = 0, selNTiming = 0)
N0.C2: RdCmd2DataValidLatency = 19, (dlyFrmS = 13, clEff = 10, earlyCas = 0, selNTiming = 0)
N6.C3: RdCmd2DataValidLatency = 19, (dlyFrmS = 13, clEff = 10, earlyCas = 0, selNTiming = 0)
N0.C3: RdCmd2DataValidLatency = 19, (dlyFrmS = 13, clEff = 10, earlyCas = 0, selNTiming = 0)
N5.C0: RdCmd2DataValidLatency = 15, (dlyFrmS = 9, clEff = 10, earlyCas = 0, selNTiming = 0)
N6.C2: RdCmd2DataValidLatency = 18, (dlyFrmS = 12, clEff = 10, earlyCas = 0, selNTiming = 0)
N5.C1: RdCmd2DataValidLatency = 15, (dlyFrmS = 9, clEff = 10, earlyCas = 0, selNTiming = 0)
N0.C2: RdCmd2DataValidLatency = 18, (dlyFrmS = 12, clEff = 10, earlyCas = 0, selNTiming = 0)
N6.C3: RdCmd2DataValidLatency = 18, (dlyFrmS = 12, clEff = 10, earlyCas = 0, selNTiming = 0)
N0.C3: RdCmd2DataValidLatency = 18, (dlyFrmS = 12, clEff = 10, earlyCas = 0, selNTiming = 0)
N5.C0: RdCmd2DataValidLatency = 14, (dlyFrmS = 8, clEff = 10, earlyCas = 0, selNTiming = 0)
N6.C2: RdCmd2DataValidLatency = 17, (dlyFrmS = 11, clEff = 10, earlyCas = 0, selNTiming = 0)
N5.C1: RdCmd2DataValidLatency = 14, (dlyFrmS = 8, clEff = 10, earlyCas = 0, selNTiming = 0)
N0.C2: RdCmd2DataValidLatency = 17, (dlyFrmS = 11, clEff = 10, earlyCas = 0, selNTiming = 0)
N6.C3: RdCmd2DataValidLatency = 17, (dlyFrmS = 11, clEff = 10, earlyCas = 0, selNTiming = 0)
N0.C3: RdCmd2DataValidLatency = 17, (dlyFrmS = 11, clEff = 10, earlyCas = 0, selNTiming = 0)
N5.C0: RdCmd2DataValidLatency = 16, (dlyFrmS = 10, clEff = 10, earlyCas = 0, selNTiming = 0)
N6.C2: RdCmd2DataValidLatency = 16, (dlyFrmS = 10, clEff = 10, earlyCas = 0, selNTiming = 0)
N5.C1: RdCmd2DataValidLatency = 16, (dlyFrmS = 10, clEff = 10, earlyCas = 0, selNTiming = 0)
N0.C2: RdCmd2DataValidLatency = 16, (dlyFrmS = 10, clEff = 10, earlyCas = 0, selNTiming = 0)
N6.C3: RdCmd2DataValidLatency = 16, (dlyFrmS = 10, clEff = 10, earlyCas = 0, selNTiming = 0)
N5.C0: AdjustTotalRoundTripTime: SUCCESS - worst rank = 0, host round trip = 73, MXB cmd2dat = 10
N0.C3: RdCmd2DataValidLatency = 16, (dlyFrmS = 10, clEff = 10, earlyCas = 0, selNTiming = 0)
N5.C2: AdjustTotalRoundTripTime
N5.C1: AdjustTotalRoundTripTime: worstRank = 1
N5.C2: AdjustTotalRoundTripTime: worstRank dimm = 0, rank = 1
N5.C3: AdjustTotalRoundTripTime: worstRank dimm = 0, rank = 1
N5.C1: AdjustTotalRoundTripTime: ddrChMask = 0xC
N5.C2: RdCmd2DataValidLatency = 20, (dlyFrmS = 14, clEff = 10, earlyCas = 0, selNTiming = 0)
N6.C2: RdCmd2DataValidLatency = 15, (dlyFrmS = 9, clEff = 10, earlyCas = 0, selNTiming = 0)
N0.C2: RdCmd2DataValidLatency = 15, (dlyFrmS = 9, clEff = 10, earlyCas = 0, selNTiming = 0)
N5.C3: RdCmd2DataValidLatency = 20, (dlyFrmS = 14, clEff = 10, earlyCas = 0, selNTiming = 0)
N6.C3: RdCmd2DataValidLatency = 15, (dlyFrmS = 9, clEff = 10, earlyCas = 0, selNTiming = 0)
N0.C3: RdCmd2DataValidLatency = 15, (dlyFrmS = 9, clEff = 10, earlyCas = 0, selNTiming = 0)
N5.C2: RdCmd2DataValidLatency = 19, (dlyFrmS = 13, clEff = 10, earlyCas = 0, selNTiming = 0)
N6.C2: RdCmd2DataValidLatency = 14, (dlyFrmS = 8, clEff = 10, earlyCas = 0, selNTiming = 0)
N0.C2: RdCmd2DataValidLatency = 14, (dlyFrmS = 8, clEff = 10, earlyCas = 0, selNTiming = 0)
N5.C3: RdCmd2DataValidLatency = 19, (dlyFrmS = 13, clEff = 10, earlyCas = 0, selNTiming = 0)
N6.C3: RdCmd2DataValidLatency = 14, (dlyFrmS = 8, clEff = 10, earlyCas = 0, selNTiming = 0)
N0.C3: RdCmd2DataValidLatency = 14, (dlyFrmS = 8, clEff = 10, earlyCas = 0, selNTiming = 0)
N5.C2: RdCmd2DataValidLatency = 18, (dlyFrmS = 12, clEff = 10, earlyCas = 0, selNTiming = 0)
N6.C2: RdCmd2DataValidLatency = 16, (dlyFrmS = 10, clEff = 10, earlyCas = 0, selNTiming = 0)
N0.C2: RdCmd2DataValidLatency = 16, (dlyFrmS = 10, clEff = 10, earlyCas = 0, selNTiming = 0)
N5.C3: RdCmd2DataValidLatency = 18, (dlyFrmS = 12, clEff = 10, earlyCas = 0, selNTiming = 0)
N6.C3: RdCmd2DataValidLatency = 16, (dlyFrmS = 10, clEff = 10, earlyCas = 0, selNTiming = 0)
N0.C3: RdCmd2DataValidLatency = 16, (dlyFrmS = 10, clEff = 10, earlyCas = 0, selNTiming = 0)
N5.C2: RdCmd2DataValidLatency = 17, (dlyFrmS = 11, clEff = 10, earlyCas = 0, selNTiming = 0)
N6.C2: AdjustTotalRoundTripTime: SUCCESS - worst rank = 1, host round trip = 73, MXB cmd2dat = 10
N7.C0.D0: CheckRankPopLocal: dimmPresent: 1, numRanks = 2
N7.C0.D0.R0: CheckRankPopLocal: mapOut: 0, enabled = 1
N7.C0.D0.R1: CheckRankPopLocal: mapOut: 0, enabled = 1
N0.C2: AdjustTotalRoundTripTime: SUCCESS - worst rank = 0, host round trip = 73, MXB cmd2dat = 10
N7.C0.D1: CheckRankPopLocal: dimmPresent: 0, numRanks = 0
Checkpoint Code: Socket 0, 0xB9, 0x00, 0x0000
N7.C0.D2: CheckRankPopLocal: dimmPresent: 0, numRanks = 0
N1.C0.D0: CheckRankPopLocal: dimmPresent: 1, numRanks = 2
N7.C0.D0: CheckRankPopLocal: amap: 0x00000000
N1.C0.D0.R0: CheckRankPopLocal: mapOut: 0, enabled = 1
N7.C0.D1: CheckRankPopLocal: amap: 0x00000000
N1.C0.D0.R1: CheckRankPopLocal: mapOut: 0, enabled = 1
N5.C3: RdCmd2DataValidLatency = 17, (dlyFrmS = 11, clEff = 10, earlyCas = 0, selNTiming = 0)
N7.C0.D2: CheckRankPopLocal: amap: 0x00000000
N1.C0.D1: CheckRankPopLocal: dimmPresent: 0, numRanks = 0
N7.C1.D0: CheckRankPopLocal: dimmPresent: 1, numRanks = 2
N1.C0.D2: CheckRankPopLocal: dimmPresent: 0, numRanks = 0
N7.C1.D0.R0: CheckRankPopLocal: mapOut: 0, enabled = 1
N1.C0.D0: CheckRankPopLocal: amap: 0x00000000
N7.C1.D0.R1: CheckRankPopLocal: mapOut: 0, enabled = 1
N1.C0.D1: CheckRankPopLocal: amap: 0x00000000
N7.C1.D1: CheckRankPopLocal: dimmPresent: 0, numRanks = 0
N1.C0.D2: CheckRankPopLocal: amap: 0x00000000
N7.C1.D2: CheckRankPopLocal: dimmPresent: 0, numRanks = 0
N1.C1.D0: CheckRankPopLocal: dimmPresent: 1, numRanks = 2
N7.C1.D0: CheckRankPopLocal: amap: 0x00000000
N1.C1.D0.R0: CheckRankPopLocal: mapOut: 0, enabled = 1
N7.C1.D1: CheckRankPopLocal: amap: 0x00000000
N1.C1.D0.R1: CheckRankPopLocal: mapOut: 0, enabled = 1
N7.C1.D2: CheckRankPopLocal: amap: 0x00000000
N1.C1.D1: CheckRankPopLocal: dimmPresent: 0, numRanks = 0
N7.C2.D0: CheckRankPopLocal: dimmPresent: 1, numRanks = 2
N1.C1.D2: CheckRankPopLocal: dimmPresent: 0, numRanks = 0
N7.C2.D0.R0: CheckRankPopLocal: mapOut: 0, enabled = 1
N1.C1.D0: CheckRankPopLocal: amap: 0x00000000
N7.C2.D0.R1: CheckRankPopLocal: mapOut: 0, enabled = 1
N1.C1.D1: CheckRankPopLocal: amap: 0x00000000
N7.C2.D1: CheckRankPopLocal: dimmPresent: 0, numRanks = 0
N1.C1.D2: CheckRankPopLocal: amap: 0x00000000
N7.C2.D2: CheckRankPopLocal: dimmPresent: 0, numRanks = 0
N1.C2.D0: CheckRankPopLocal: dimmPresent: 1, numRanks = 2
N7.C2.D0: CheckRankPopLocal: amap: 0x00000000
N1.C2.D0.R0: CheckRankPopLocal: mapOut: 0, enabled = 1
N7.C2.D1: CheckRankPopLocal: amap: 0x00000000
N1.C2.D0.R1: CheckRankPopLocal: mapOut: 0, enabled = 1
N7.C2.D2: CheckRankPopLocal: amap: 0x00000000
N1.C2.D1: CheckRankPopLocal: dimmPresent: 0, numRanks = 0
N7.C3.D0: CheckRankPopLocal: dimmPresent: 1, numRanks = 2
N1.C2.D2: CheckRankPopLocal: dimmPresent: 0, numRanks = 0
N5.C2: RdCmd2DataValidLatency = 16, (dlyFrmS = 10, clEff = 10, earlyCas = 0, selNTiming = 0)
N7.C3.D0.R0: CheckRankPopLocal: mapOut: 0, enabled = 1
N1.C2.D0: CheckRankPopLocal: amap: 0x00000000
N7.C3.D0.R1: CheckRankPopLocal: mapOut: 0, enabled = 1
N1.C2.D1: CheckRankPopLocal: amap: 0x00000000
N7.C3.D1: CheckRankPopLocal: dimmPresent: 0, numRanks = 0
N1.C2.D2: CheckRankPopLocal: amap: 0x00000000
N7.C3.D2: CheckRankPopLocal: dimmPresent: 0, numRanks = 0
N1.C3.D0: CheckRankPopLocal: dimmPresent: 1, numRanks = 2
N7.C3.D0: CheckRankPopLocal: amap: 0x00000000
N1.C3.D0.R0: CheckRankPopLocal: mapOut: 0, enabled = 1
N7.C3.D1: CheckRankPopLocal: amap: 0x00000000
N1.C3.D0.R1: CheckRankPopLocal: mapOut: 0, enabled = 1
N7.C3.D2: CheckRankPopLocal: amap: 0x00000000
N1.C3.D1: CheckRankPopLocal: dimmPresent: 0, numRanks = 0
N7.C0: AdjustTotalRoundTripTime
N1.C3.D2: CheckRankPopLocal: dimmPresent: 0, numRanks = 0
N7.C0: AdjustTotalRoundTripTime: worstRank = 1
N1.C3.D0: CheckRankPopLocal: amap: 0x00000000
N7.C0: AdjustTotalRoundTripTime: worstRank dimm = 0, rank = 1
N1.C3.D1: CheckRankPopLocal: amap: 0x00000000
N7.C1: AdjustTotalRoundTripTime: worstRank dimm = 0, rank = 1
N1.C3.D2: CheckRankPopLocal: amap: 0x00000000
N7.C0: AdjustTotalRoundTripTime: ddrChMask = 0x3
N1.C0: AdjustTotalRoundTripTime
N1.C0: AdjustTotalRoundTripTime: worstRank = 0
N1.C0: AdjustTotalRoundTripTime: worstRank dimm = 0, rank = 0
N1.C1: AdjustTotalRoundTripTime: worstRank dimm = 0, rank = 0
N7.C0: RdCmd2DataValidLatency = 20, (dlyFrmS = 14, clEff = 10, earlyCas = 0, selNTiming = 0)
N1.C0: AdjustTotalRoundTripTime: ddrChMask = 0x3
N5.C3: RdCmd2DataValidLatency = 16, (dlyFrmS = 10, clEff = 10, earlyCas = 0, selNTiming = 0)
N1.C0: RdCmd2DataValidLatency = 20, (dlyFrmS = 14, clEff = 10, earlyCas = 0, selNTiming = 0)
N7.C1: RdCmd2DataValidLatency = 20, (dlyFrmS = 14, clEff = 10, earlyCas = 0, selNTiming = 0)
N1.C1: RdCmd2DataValidLatency = 20, (dlyFrmS = 14, clEff = 10, earlyCas = 0, selNTiming = 0)
N5.C2: RdCmd2DataValidLatency = 15, (dlyFrmS = 9, clEff = 10, earlyCas = 0, selNTiming = 0)
N7.C0: RdCmd2DataValidLatency = 19, (dlyFrmS = 13, clEff = 10, earlyCas = 0, selNTiming = 0)
N5.C3: RdCmd2DataValidLatency = 15, (dlyFrmS = 9, clEff = 10, earlyCas = 0, selNTiming = 0)
N1.C0: RdCmd2DataValidLatency = 19, (dlyFrmS = 13, clEff = 10, earlyCas = 0, selNTiming = 0)
N7.C1: RdCmd2DataValidLatency = 19, (dlyFrmS = 13, clEff = 10, earlyCas = 0, selNTiming = 0)
N1.C1: RdCmd2DataValidLatency = 19, (dlyFrmS = 13, clEff = 10, earlyCas = 0, selNTiming = 0)
N5.C2: RdCmd2DataValidLatency = 14, (dlyFrmS = 8, clEff = 10, earlyCas = 0, selNTiming = 0)
N7.C0: RdCmd2DataValidLatency = 18, (dlyFrmS = 12, clEff = 10, earlyCas = 0, selNTiming = 0)
N5.C3: RdCmd2DataValidLatency = 14, (dlyFrmS = 8, clEff = 10, earlyCas = 0, selNTiming = 0)
N1.C0: RdCmd2DataValidLatency = 18, (dlyFrmS = 12, clEff = 10, earlyCas = 0, selNTiming = 0)
N7.C1: RdCmd2DataValidLatency = 18, (dlyFrmS = 12, clEff = 10, earlyCas = 0, selNTiming = 0)
N1.C1: RdCmd2DataValidLatency = 18, (dlyFrmS = 12, clEff = 10, earlyCas = 0, selNTiming = 0)
N5.C2: RdCmd2DataValidLatency = 16, (dlyFrmS = 10, clEff = 10, earlyCas = 0, selNTiming = 0)
N7.C0: RdCmd2DataValidLatency = 17, (dlyFrmS = 11, clEff = 10, earlyCas = 0, selNTiming = 0)
N5.C3: RdCmd2DataValidLatency = 16, (dlyFrmS = 10, clEff = 10, earlyCas = 0, selNTiming = 0)
N1.C0: RdCmd2DataValidLatency = 17, (dlyFrmS = 11, clEff = 10, earlyCas = 0, selNTiming = 0)
N7.C1: RdCmd2DataValidLatency = 17, (dlyFrmS = 11, clEff = 10, earlyCas = 0, selNTiming = 0)
N5.C2: AdjustTotalRoundTripTime: SUCCESS - worst rank = 1, host round trip = 73, MXB cmd2dat = 10
N4: DDR Channel Late Configuration
N1.C1: RdCmd2DataValidLatency = 17, (dlyFrmS = 11, clEff = 10, earlyCas = 0, selNTiming = 0)
N4: Parity Checking Enable
N4: Enabling C/A Parity
N4.C0: VmseSetupscrambling: Host push_to_data_delay = 8, host scr_to_data_delay = 8, JCK wpsyncdata = 10, JCK scrsyndata = 10, JCK wpsyncrcven = 5, JCK scrsyncrcven = 5
N4.C0: VmseStartScramblers: Start VMSE scramblers, cmdbit = 0x10, datbit = 0x20, command = 0x60003A, 
N4.C1: VmseSetupscrambling: Host push_to_data_delay = 7, host scr_to_data_delay = 7, JCK wpsyncdata = 10, JCK scrsyndata = 10, JCK wpsyncrcven = 5, JCK scrsyncrcven = 5
N4.C2: VmseStartScramblers: Start VMSE scramblers, cmdbit = 0x10, datbit = 0x20, command = 0x60003A, 
N4: DRAM Maintenance
N4: DRAM Maintenance : Auto Mode
N4: DRAM Maintenance : TRR Mode detected : 0
N4: DRAM Maintenance : TRR Mode detected : 0
N4: DRAM Maintenance : TRR Mode detected : 0
N4: DRAM Maintenance : TRR Mode detected : 0
PTRR Mode Enabled 
N5: DDR Channel Late Configuration
N5: Parity Checking Enable
N5: Enabling C/A Parity
N5.C0: VmseSetupscrambling: Host push_to_data_delay = 7, host scr_to_data_delay = 7, JCK wpsyncdata = 10, JCK scrsyndata = 10, JCK wpsyncrcven = 5, JCK scrsyncrcven = 5
N5.C0: VmseStartScramblers: Start VMSE scramblers, cmdbit = 0x10, datbit = 0x20, command = 0x60003A, 
N5.C1: VmseSetupscrambling: Host push_to_data_delay = 7, host scr_to_data_delay = 7, JCK wpsyncdata = 10, JCK scrsyndata = 10, JCK wpsyncrcven = 5, JCK scrsyncrcven = 5
N5.C2: VmseStartScramblers: Start VMSE scramblers, cmdbit = 0x10, datbit = 0x20, command = 0x60003A, 
N7.C0: RdCmd2DataValidLatency = 16, (dlyFrmS = 10, clEff = 10, earlyCas = 0, selNTiming = 0)
N5: DRAM Maintenance
N5: DRAM Maintenance : Auto Mode
N5: DRAM Maintenance : TRR Mode detected : 0
N5: DRAM Maintenance : TRR Mode detected : 0
N5: DRAM Maintenance : TRR Mode detected : 0
N5: DRAM Maintenance : TRR Mode detected : 0
PTRR Mode Enabled 
N1.C0: RdCmd2DataValidLatency = 16, (dlyFrmS = 10, clEff = 10, earlyCas = 0, selNTiming = 0)
DramMemoryEccInit: rankNodeChEnMap = 0xFE1B8BA0
N5: EnableHostRefresh Start Write Time diff[5]=7860 ns
N5: EnableHostRefresh End Write Time diff[5]=7856 ns
N4.C0.R0: CpgcMemTestRankSetup: colAddressBits = 11, rowAddressBits = 15, bankAddressBits = 3
N4.C1.R0: CpgcMemTestRankSetup: colAddressBits = 11, rowAddressBits = 15, bankAddressBits = 3
N4.C2.R0: CpgcMemTestRankSetup: colAddressBits = 11, rowAddressBits = 15, bankAddressBits = 3
N4.C3.R0: CpgcMemTestRankSetup: colAddressBits = 11, rowAddressBits = 15, bankAddressBits = 3
N5.C0.R0: CpgcMemTestRankSetup: colAddressBits = 11, rowAddressBits = 16, bankAddressBits = 3
N5.C1.R0: CpgcMemTestRankSetup: colAddressBits = 11, rowAddressBits = 16, bankAddressBits = 3
N5.C2.R0: CpgcMemTestRankSetup: colAddressBits = 11, rowAddressBits = 16, bankAddressBits = 3
N5.C3.R0: CpgcMemTestRankSetup: colAddressBits = 11, rowAddressBits = 16, bankAddressBits = 3
N7.C1: RdCmd2DataValidLatency = 16, (dlyFrmS = 10, clEff = 10, earlyCas = 0, selNTiming = 0)
N1.C1: RdCmd2DataValidLatency = 16, (dlyFrmS = 10, clEff = 10, earlyCas = 0, selNTiming = 0)
N7.C0: RdCmd2DataValidLatency = 15, (dlyFrmS = 9, clEff = 10, earlyCas = 0, selNTiming = 0)
N1.C0: RdCmd2DataValidLatency = 15, (dlyFrmS = 9, clEff = 10, earlyCas = 0, selNTiming = 0)
N7.C1: RdCmd2DataValidLatency = 15, (dlyFrmS = 9, clEff = 10, earlyCas = 0, selNTiming = 0)
N1.C1: RdCmd2DataValidLatency = 15, (dlyFrmS = 9, clEff = 10, earlyCas = 0, selNTiming = 0)
N7.C0: RdCmd2DataValidLatency = 14, (dlyFrmS = 8, clEff = 10, earlyCas = 0, selNTiming = 0)
N1.C0: RdCmd2DataValidLatency = 14, (dlyFrmS = 8, clEff = 10, earlyCas = 0, selNTiming = 0)
N7.C1: RdCmd2DataValidLatency = 14, (dlyFrmS = 8, clEff = 10, earlyCas = 0, selNTiming = 0)
N1.C1: RdCmd2DataValidLatency = 14, (dlyFrmS = 8, clEff = 10, earlyCas = 0, selNTiming = 0)
N4.C0.R1: CpgcMemTestRankSetup: colAddressBits = 11, rowAddressBits = 15, bankAddressBits = 3
N4.C1.R1: CpgcMemTestRankSetup: colAddressBits = 11, rowAddressBits = 15, bankAddressBits = 3
N4.C2.R1: CpgcMemTestRankSetup: colAddressBits = 11, rowAddressBits = 15, bankAddressBits = 3
N4.C3.R1: CpgcMemTestRankSetup: colAddressBits = 11, rowAddressBits = 15, bankAddressBits = 3
N5.C0.R1: CpgcMemTestRankSetup: colAddressBits = 11, rowAddressBits = 16, bankAddressBits = 3
N5.C1.R1: CpgcMemTestRankSetup: colAddressBits = 11, rowAddressBits = 16, bankAddressBits = 3
N5.C2.R1: CpgcMemTestRankSetup: colAddressBits = 11, rowAddressBits = 16, bankAddressBits = 3
N5.C3.R1: CpgcMemTestRankSetup: colAddressBits = 11, rowAddressBits = 16, bankAddressBits = 3
N7.C0: RdCmd2DataValidLatency = 16, (dlyFrmS = 10, clEff = 10, earlyCas = 0, selNTiming = 0)
N1.C0: RdCmd2DataValidLatency = 16, (dlyFrmS = 10, clEff = 10, earlyCas = 0, selNTiming = 0)
N7.C1: RdCmd2DataValidLatency = 16, (dlyFrmS = 10, clEff = 10, earlyCas = 0, selNTiming = 0)
N1.C1: RdCmd2DataValidLatency = 16, (dlyFrmS = 10, clEff = 10, earlyCas = 0, selNTiming = 0)
N7.C0: AdjustTotalRoundTripTime: SUCCESS - worst rank = 1, host round trip = 73, MXB cmd2dat = 10
N7.C2: AdjustTotalRoundTripTime
N7.C1: AdjustTotalRoundTripTime: worstRank = 0
N7.C2: AdjustTotalRoundTripTime: worstRank dimm = 0, rank = 0
N7.C3: AdjustTotalRoundTripTime: worstRank dimm = 0, rank = 0
N7.C1: AdjustTotalRoundTripTime: ddrChMask = 0xC
N1.C0: AdjustTotalRoundTripTime: SUCCESS - worst rank = 0, host round trip = 73, MXB cmd2dat = 10
N1.C2: AdjustTotalRoundTripTime
N1.C1: AdjustTotalRoundTripTime: worstRank = 0
N1.C2: AdjustTotalRoundTripTime: worstRank dimm = 0, rank = 0
N7.C2: RdCmd2DataValidLatency = 20, (dlyFrmS = 14, clEff = 10, earlyCas = 0, selNTiming = 0)
N1.C3: AdjustTotalRoundTripTime: worstRank dimm = 0, rank = 0
N1.C1: AdjustTotalRoundTripTime: ddrChMask = 0xC
N1.C2: RdCmd2DataValidLatency = 20, (dlyFrmS = 14, clEff = 10, earlyCas = 0, selNTiming = 0)
N7.C3: RdCmd2DataValidLatency = 20, (dlyFrmS = 14, clEff = 10, earlyCas = 0, selNTiming = 0)
N1.C3: RdCmd2DataValidLatency = 20, (dlyFrmS = 14, clEff = 10, earlyCas = 0, selNTiming = 0)
N7.C2: RdCmd2DataValidLatency = 19, (dlyFrmS = 13, clEff = 10, earlyCas = 0, selNTiming = 0)
N1.C2: RdCmd2DataValidLatency = 19, (dlyFrmS = 13, clEff = 10, earlyCas = 0, selNTiming = 0)
N4.C0.R4: CpgcMemTestRankSetup: colAddressBits = 11, rowAddressBits = 15, bankAddressBits = 3
N4.C1.R4: CpgcMemTestRankSetup: colAddressBits = 11, rowAddressBits = 15, bankAddressBits = 3
N4.C2.R4: CpgcMemTestRankSetup: colAddressBits = 11, rowAddressBits = 15, bankAddressBits = 3
N4.C3.R4: CpgcMemTestRankSetup: colAddressBits = 11, rowAddressBits = 15, bankAddressBits = 3
N7.C3: RdCmd2DataValidLatency = 19, (dlyFrmS = 13, clEff = 10, earlyCas = 0, selNTiming = 0)
N1.C3: RdCmd2DataValidLatency = 19, (dlyFrmS = 13, clEff = 10, earlyCas = 0, selNTiming = 0)
N7.C2: RdCmd2DataValidLatency = 18, (dlyFrmS = 12, clEff = 10, earlyCas = 0, selNTiming = 0)
N1.C2: RdCmd2DataValidLatency = 18, (dlyFrmS = 12, clEff = 10, earlyCas = 0, selNTiming = 0)
N4.C0.R5: CpgcMemTestRankSetup: colAddressBits = 11, rowAddressBits = 15, bankAddressBits = 3
N4.C1.R5: CpgcMemTestRankSetup: colAddressBits = 11, rowAddressBits = 15, bankAddressBits = 3
N4.C2.R5: CpgcMemTestRankSetup: colAddressBits = 11, rowAddressBits = 15, bankAddressBits = 3
N4.C3.R5: CpgcMemTestRankSetup: colAddressBits = 11, rowAddressBits = 15, bankAddressBits = 3
N7.C3: RdCmd2DataValidLatency = 18, (dlyFrmS = 12, clEff = 10, earlyCas = 0, selNTiming = 0)
N1.C3: RdCmd2DataValidLatency = 18, (dlyFrmS = 12, clEff = 10, earlyCas = 0, selNTiming = 0)
N7.C2: RdCmd2DataValidLatency = 17, (dlyFrmS = 11, clEff = 10, earlyCas = 0, selNTiming = 0)
N1.C2: RdCmd2DataValidLatency = 17, (dlyFrmS = 11, clEff = 10, earlyCas = 0, selNTiming = 0)
N7.C3: RdCmd2DataValidLatency = 17, (dlyFrmS = 11, clEff = 10, earlyCas = 0, selNTiming = 0)
N1.C3: RdCmd2DataValidLatency = 17, (dlyFrmS = 11, clEff = 10, earlyCas = 0, selNTiming = 0)

ECC init time = 2876 ms
N4: PcodeRcompEnable
N4: PCU RD CMD Success: MboxStatus = 0x0 Default PCUData Value = 0x9840000
N4: PCU WR CMD Success: MBoxStatus = 0x0 PCU_MISC_CONFIG = 0x8840000
N4: Set rst_cpl2 to enable RCOMP
N4: InitThrottling
N4: Init Throttling

N4: 
::MPM:: 2> dimmInWTTable = 0, WTcurrentDimm.WTLvAndDramDensity = 3,   ddrVoltage = 0

N4: 
::MEM DDR3:: DDR3 Memory detected. Look at DDR3 Power table now...
N4.C0.D0: Init DRAM RAPL

N4.C0.D0: MTS mfgid = 0x5400
N4.C0.D0: MTS did_rid = 0x121
N4.C0.D0: MTS Capabilities = 0xEF00
N4.C0.D0: MTS Current Ambient Temp = 0xF8C1
N4.C0.D0: TCRIT  = 0x690
N4: 
::MPM:: 2> dimmInWTTable = 0, WTcurrentDimm.WTLvAndDramDensity = 3,   ddrVoltage = 0

N4: 
::MEM DDR3:: DDR3 Memory detected. Look at DDR3 Power table now...
N4.C0.D1: Init DRAM RAPL

N4.C0.D1: MTS mfgid = 0x5400
N4.C0.D1: MTS did_rid = 0x121
N4.C0.D1: MTS Capabilities = 0xEF00
N4.C0.D1: MTS Current Ambient Temp = 0xE0C1
N4.C0.D1: TCRIT  = 0x690
N4: 
::MPM:: 2> dimmInWTTable = 0, WTcurrentDimm.WTLvAndDramDensity = 3,   ddrVoltage = 0

N4: 
::MEM DDR3:: DDR3 Memory detected. Look at DDR3 Power table now...
N4.C1.D0: Init DRAM RAPL

N4.C1.D0: MTS mfgid = 0x5400
N4.C1.D0: MTS did_rid = 0x121
N4.C1.D0: MTS Capabilities = 0xEF00
N4.C1.D0: MTS Current Ambient Temp = 0xC2
N4.C1.D0: TCRIT  = 0x690
N4: 
::MPM:: 2> dimmInWTTable = 0, WTcurrentDimm.WTLvAndDramDensity = 3,   ddrVoltage = 0

N4: 
::MEM DDR3:: DDR3 Memory detected. Look at DDR3 Power table now...
N4.C1.D1: Init DRAM RAPL

N4.C1.D1: MTS mfgid = 0x4A10
N4.C1.D1: MTS did_rid = 0x3
N4.C1.D1: MTS Capabilities = 0x6F00
N4.C1.D1: MTS Current Ambient Temp = 0x8C2
N4.C1.D1: TCRIT  = 0x690
N4: SMBCNTL_0 = 0x38000033
N4: 
::MPM:: 2> dimmInWTTable = 0, WTcurrentDimm.WTLvAndDramDensity = 3,   ddrVoltage = 0

N4: 
::MEM DDR3:: DDR3 Memory detected. Look at DDR3 Power table now...
N4.C2.D0: Init DRAM RAPL

N4.C2.D0: MTS mfgid = 0x5400
N4.C2.D0: MTS did_rid = 0x121
N4.C2.D0: MTS Capabilities = 0xEF00
N4.C2.D0: MTS Current Ambient Temp = 0xC8C1
N4.C2.D0: TCRIT  = 0x690
N4: 
::MPM:: 2> dimmInWTTable = 0, WTcurrentDimm.WTLvAndDramDensity = 3,   ddrVoltage = 0

N4: 
::MEM DDR3:: DDR3 Memory detected. Look at DDR3 Power table now...
N4.C2.D1: Init DRAM RAPL

N4.C2.D1: MTS mfgid = 0x5400
N4.C2.D1: MTS did_rid = 0x121
N4.C2.D1: MTS Capabilities = 0xEF00
N4.C2.D1: MTS Current Ambient Temp = 0xB4C1
N4.C2.D1: TCRIT  = 0x690
N4: 
::MPM:: 2> dimmInWTTable = 0, WTcurrentDimm.WTLvAndDramDensity = 3,   ddrVoltage = 0

N4: 
::MEM DDR3:: DDR3 Memory detected. Look at DDR3 Power table now...
N4.C3.D0: Init DRAM RAPL

N4.C3.D0: MTS mfgid = 0x4A10
N4.C3.D0: MTS did_rid = 0x3
N4.C3.D0: MTS Capabilities = 0x6F00
N4.C3.D0: MTS Current Ambient Temp = 0xB4C1
N4.C3.D0: TCRIT  = 0x690
N4: 
::MPM:: 2> dimmInWTTable = 0, WTcurrentDimm.WTLvAndDramDensity = 3,   ddrVoltage = 0

N4: 
::MEM DDR3:: DDR3 Memory detected. Look at DDR3 Power table now...
N4.C3.D1: Init DRAM RAPL

N4.C3.D1: MTS mfgid = 0x4A10
N4.C3.D1: MTS did_rid = 0x3
N4.C3.D1: MTS Capabilities = 0x6F00
N4.C3.D1: MTS Current Ambient Temp = 0xC8C1
N4.C3.D1: TCRIT  = 0x690
N4: SMBCNTL_1 = 0x38000033
N4: 
Init DRAM Phase Shedding
N4: Memory current estimate value 20
N4: Setting Node 0x4 - VR0 Active PSI = PS0
N4: Memory current estimate value 20
N4: Setting Node 0x4 - VR1 Active PSI = PS0
N7.C2: RdCmd2DataValidLatency = 16, (dlyFrmS = 10, clEff = 10, earlyCas = 0, selNTiming = 0)
N1.C2: RdCmd2DataValidLatency = 16, (dlyFrmS = 10, clEff = 10, earlyCas = 0, selNTiming = 0)
N4: SwitchToNormalMode
N4: SetupMiscFeatures
N4: Clear Errors
N5: PcodeRcompEnable
N5: PCU RD CMD Success: MboxStatus = 0x0 Default PCUData Value = 0x8840000
N5: PCU WR CMD Success: MBoxStatus = 0x0 PCU_MISC_CONFIG = 0x8840000
N5: InitThrottling
N5: Init Throttling

N5: 
::MPM:: 2> dimmInWTTable = 0, WTcurrentDimm.WTLvAndDramDensity = 4,   ddrVoltage = 0

N5: 
::MEM DDR3:: DDR3 Memory detected. Look at DDR3 Power table now...
N5.C0.D0: Init DRAM RAPL

N5.C0.D0: MTS mfgid = 0x4A10
N5.C0.D0: MTS did_rid = 0x3
N5.C0.D0: MTS Capabilities = 0x6F00
N5.C0.D0: MTS Current Ambient Temp = 0xC8C1
N5.C0.D0: TCRIT  = 0x690
N5: 
::MPM:: 2> dimmInWTTable = 0, WTcurrentDimm.WTLvAndDramDensity = 4,   ddrVoltage = 0

N5: 
::MEM DDR3:: DDR3 Memory detected. Look at DDR3 Power table now...
N5.C1.D0: Init DRAM RAPL

N5.C1.D0: MTS mfgid = 0x4A10
N5.C1.D0: MTS did_rid = 0x3
N5.C1.D0: MTS Capabilities = 0x6F00
N5.C1.D0: MTS Current Ambient Temp = 0xCCC1
N5.C1.D0: TCRIT  = 0x690
N5: SMBCNTL_0 = 0x38000011
N5: 
::MPM:: 2> dimmInWTTable = 0, WTcurrentDimm.WTLvAndDramDensity = 4,   ddrVoltage = 0

N5: 
::MEM DDR3:: DDR3 Memory detected. Look at DDR3 Power table now...
N5.C2.D0: Init DRAM RAPL

N5.C2.D0: MTS mfgid = 0x4A10
N5.C2.D0: MTS did_rid = 0x3
N5.C2.D0: MTS Capabilities = 0x6F00
N5.C2.D0: MTS Current Ambient Temp = 0xA8C1
N5.C2.D0: TCRIT  = 0x690
N5: 
::MPM:: 2> dimmInWTTable = 0, WTcurrentDimm.WTLvAndDramDensity = 4,   ddrVoltage = 0

N5: 
::MEM DDR3:: DDR3 Memory detected. Look at DDR3 Power table now...
N5.C3.D0: Init DRAM RAPL

N5.C3.D0: MTS mfgid = 0x5400
N5.C3.D0: MTS did_rid = 0x121
N5.C3.D0: MTS Capabilities = 0xEF00
N5.C3.D0: MTS Current Ambient Temp = 0xB0C1
N5.C3.D0: TCRIT  = 0x690
N5: SMBCNTL_1 = 0x38000011
N5: 
Init DRAM Phase Shedding
N5: Memory current estimate value E
N5: Setting Node 0x5 - VR2 Active PSI = PS1
N5: Memory current estimate value E
N5: Setting Node 0x5 - VR3 Active PSI = PS1
N7.C3: RdCmd2DataValidLatency = 16, (dlyFrmS = 10, clEff = 10, earlyCas = 0, selNTiming = 0)
N1.C3: RdCmd2DataValidLatency = 16, (dlyFrmS = 10, clEff = 10, earlyCas = 0, selNTiming = 0)
N5: SwitchToNormalMode
N5: SetupMiscFeatures
N5: Clear Errors
N7.C2: RdCmd2DataValidLatency = 15, (dlyFrmS = 9, clEff = 10, earlyCas = 0, selNTiming = 0)
N1.C2: RdCmd2DataValidLatency = 15, (dlyFrmS = 9, clEff = 10, earlyCas = 0, selNTiming = 0)
N7.C3: RdCmd2DataValidLatency = 15, (dlyFrmS = 9, clEff = 10, earlyCas = 0, selNTiming = 0)
N1.C3: RdCmd2DataValidLatency = 15, (dlyFrmS = 9, clEff = 10, earlyCas = 0, selNTiming = 0)
N7.C2: RdCmd2DataValidLatency = 14, (dlyFrmS = 8, clEff = 10, earlyCas = 0, selNTiming = 0)
N1.C2: RdCmd2DataValidLatency = 14, (dlyFrmS = 8, clEff = 10, earlyCas = 0, selNTiming = 0)
N7.C3: RdCmd2DataValidLatency = 14, (dlyFrmS = 8, clEff = 10, earlyCas = 0, selNTiming = 0)
N1.C3: RdCmd2DataValidLatency = 14, (dlyFrmS = 8, clEff = 10, earlyCas = 0, selNTiming = 0)
N7.C2: RdCmd2DataValidLatency = 16, (dlyFrmS = 10, clEff = 10, earlyCas = 0, selNTiming = 0)
N1.C2: RdCmd2DataValidLatency = 16, (dlyFrmS = 10, clEff = 10, earlyCas = 0, selNTiming = 0)
N7.C3: RdCmd2DataValidLatency = 16, (dlyFrmS = 10, clEff = 10, earlyCas = 0, selNTiming = 0)
N1.C3: RdCmd2DataValidLatency = 16, (dlyFrmS = 10, clEff = 10, earlyCas = 0, selNTiming = 0)
N7.C2: AdjustTotalRoundTripTime: SUCCESS - worst rank = 0, host round trip = 75, MXB cmd2dat = 10
N1.C2: AdjustTotalRoundTripTime: SUCCESS - worst rank = 0, host round trip = 75, MXB cmd2dat = 10
N6: DDR Channel Late Configuration
N0: DDR Channel Late Configuration
N6: Parity Checking Enable
Checkpoint Code: Socket 0, 0xB9, 0x02, 0x0000
N6: Enabling C/A Parity
N0: Parity Checking Enable
N6.C0: VmseSetupscrambling: Host push_to_data_delay = 8, host scr_to_data_delay = 8, JCK wpsyncdata = 10, JCK scrsyndata = 10, JCK wpsyncrcven = 5, JCK scrsyncrcven = 5
N0: Enabling C/A Parity
N6.C0: VmseStartScramblers: Start VMSE scramblers, cmdbit = 0x10, datbit = 0x20, command = 0x60003A, 
N0.C0: VmseSetupscrambling: Host push_to_data_delay = 7, host scr_to_data_delay = 7, JCK wpsyncdata = 10, JCK scrsyndata = 10, JCK wpsyncrcven = 5, JCK scrsyncrcven = 5
N6.C1: VmseSetupscrambling: Host push_to_data_delay = 7, host scr_to_data_delay = 7, JCK wpsyncdata = 10, JCK scrsyndata = 10, JCK wpsyncrcven = 5, JCK scrsyncrcven = 5
N0.C0: VmseStartScramblers: Start VMSE scramblers, cmdbit = 0x10, datbit = 0x20, command = 0x60003A, 
N6.C2: VmseStartScramblers: Start VMSE scramblers, cmdbit = 0x10, datbit = 0x20, command = 0x60003A, 
N0.C1: VmseSetupscrambling: Host push_to_data_delay = 8, host scr_to_data_delay = 8, JCK wpsyncdata = 10, JCK scrsyndata = 10, JCK wpsyncrcven = 5, JCK scrsyncrcven = 5
N6: DRAM Maintenance
N0.C2: VmseStartScramblers: Start VMSE scramblers, cmdbit = 0x10, datbit = 0x20, command = 0x60003A, 
N6: DRAM Maintenance : Auto Mode
N0: DRAM Maintenance
N6: DRAM Maintenance : TRR Mode detected : 0
N0: DRAM Maintenance : Auto Mode
N6: DRAM Maintenance : TRR Mode detected : 0
N0: DRAM Maintenance : TRR Mode detected : 0
N6: DRAM Maintenance : TRR Mode detected : 0
N0: DRAM Maintenance : TRR Mode detected : 0
N6: DRAM Maintenance : TRR Mode detected : 0
N0: DRAM Maintenance : TRR Mode detected : 0
PTRR Mode Enabled 
N0: DRAM Maintenance : TRR Mode detected : 0
N7: DDR Channel Late Configuration
PTRR Mode Enabled 
N7: Parity Checking Enable
N1: DDR Channel Late Configuration
N7: Enabling C/A Parity
Checkpoint Code: Socket 0, 0xB9, 0x02, 0x0000
N7.C0: VmseSetupscrambling: Host push_to_data_delay = 7, host scr_to_data_delay = 7, JCK wpsyncdata = 10, JCK scrsyndata = 10, JCK wpsyncrcven = 5, JCK scrsyncrcven = 5
N1: Parity Checking Enable
N7.C0: VmseStartScramblers: Start VMSE scramblers, cmdbit = 0x10, datbit = 0x20, command = 0x60003A, 
N1: Enabling C/A Parity
N7.C1: VmseSetupscrambling: Host push_to_data_delay = 8, host scr_to_data_delay = 8, JCK wpsyncdata = 10, JCK scrsyndata = 10, JCK wpsyncrcven = 5, JCK scrsyncrcven = 5
N1.C0: VmseSetupscrambling: Host push_to_data_delay = 7, host scr_to_data_delay = 7, JCK wpsyncdata = 10, JCK scrsyndata = 10, JCK wpsyncrcven = 5, JCK scrsyncrcven = 5
N7.C2: VmseStartScramblers: Start VMSE scramblers, cmdbit = 0x10, datbit = 0x20, command = 0x60003A, 
N1.C0: VmseStartScramblers: Start VMSE scramblers, cmdbit = 0x10, datbit = 0x20, command = 0x60003A, 
N7: DRAM Maintenance
N1.C1: VmseSetupscrambling: Host push_to_data_delay = 8, host scr_to_data_delay = 8, JCK wpsyncdata = 10, JCK scrsyndata = 10, JCK wpsyncrcven = 5, JCK scrsyncrcven = 5
N7: DRAM Maintenance : Auto Mode
N1.C2: VmseStartScramblers: Start VMSE scramblers, cmdbit = 0x10, datbit = 0x20, command = 0x60003A, 
N7: DRAM Maintenance : TRR Mode detected : 0
N1: DRAM Maintenance
N7: DRAM Maintenance : TRR Mode detected : 0
N1: DRAM Maintenance : Auto Mode
N7: DRAM Maintenance : TRR Mode detected : 0
N1: DRAM Maintenance : TRR Mode detected : 0
N7: DRAM Maintenance : TRR Mode detected : 0
N1: DRAM Maintenance : TRR Mode detected : 0
PTRR Mode Enabled 
N1: DRAM Maintenance : TRR Mode detected : 0
DramMemoryEccInit: rankNodeChEnMap = 0xFE1B8BA0
N1: DRAM Maintenance : TRR Mode detected : 0
N7: EnableHostRefresh Start Write Time diff[7]=7854 ns
PTRR Mode Enabled 
N7: EnableHostRefresh End Write Time diff[7]=7844 ns
DramMemoryEccInit: rankNodeChEnMap = 0xFE1B8BDC
Checkpoint Code: Socket 0, 0xB9, 0x01, 0x0000
N1: EnableHostRefresh Start Write Time diff[1]=7841 ns
N6.C0.R0: CpgcMemTestRankSetup: colAddressBits = 11, rowAddressBits = 15, bankAddressBits = 3
N1: EnableHostRefresh End Write Time diff[1]=7836 ns
N6.C1.R0: CpgcMemTestRankSetup: colAddressBits = 11, rowAddressBits = 15, bankAddressBits = 3
N6.C2.R0: CpgcMemTestRankSetup: colAddressBits = 11, rowAddressBits = 15, bankAddressBits = 3
N0.C0.R0: CpgcMemTestRankSetup: colAddressBits = 11, rowAddressBits = 15, bankAddressBits = 3
N6.C3.R0: CpgcMemTestRankSetup: colAddressBits = 11, rowAddressBits = 15, bankAddressBits = 3
N0.C1.R0: CpgcMemTestRankSetup: colAddressBits = 11, rowAddressBits = 15, bankAddressBits = 3
N7.C0.R0: CpgcMemTestRankSetup: colAddressBits = 11, rowAddressBits = 16, bankAddressBits = 3
N0.C2.R0: CpgcMemTestRankSetup: colAddressBits = 11, rowAddressBits = 15, bankAddressBits = 3
N7.C1.R0: CpgcMemTestRankSetup: colAddressBits = 11, rowAddressBits = 16, bankAddressBits = 3
N0.C3.R0: CpgcMemTestRankSetup: colAddressBits = 11, rowAddressBits = 15, bankAddressBits = 3
N7.C2.R0: CpgcMemTestRankSetup: colAddressBits = 11, rowAddressBits = 16, bankAddressBits = 3
N1.C0.R0: CpgcMemTestRankSetup: colAddressBits = 11, rowAddressBits = 16, bankAddressBits = 3
N7.C3.R0: CpgcMemTestRankSetup: colAddressBits = 11, rowAddressBits = 16, bankAddressBits = 3
N1.C1.R0: CpgcMemTestRankSetup: colAddressBits = 11, rowAddressBits = 16, bankAddressBits = 3
N1.C2.R0: CpgcMemTestRankSetup: colAddressBits = 11, rowAddressBits = 16, bankAddressBits = 3
N1.C3.R0: CpgcMemTestRankSetup: colAddressBits = 11, rowAddressBits = 16, bankAddressBits = 3
N6.C0.R1: CpgcMemTestRankSetup: colAddressBits = 11, rowAddressBits = 15, bankAddressBits = 3
N6.C1.R1: CpgcMemTestRankSetup: colAddressBits = 11, rowAddressBits = 15, bankAddressBits = 3
N6.C2.R1: CpgcMemTestRankSetup: colAddressBits = 11, rowAddressBits = 15, bankAddressBits = 3
N6.C3.R1: CpgcMemTestRankSetup: colAddressBits = 11, rowAddressBits = 15, bankAddressBits = 3
N0.C0.R1: CpgcMemTestRankSetup: colAddressBits = 11, rowAddressBits = 15, bankAddressBits = 3
N7.C0.R1: CpgcMemTestRankSetup: colAddressBits = 11, rowAddressBits = 16, bankAddressBits = 3
N0.C1.R1: CpgcMemTestRankSetup: colAddressBits = 11, rowAddressBits = 15, bankAddressBits = 3
N7.C1.R1: CpgcMemTestRankSetup: colAddressBits = 11, rowAddressBits = 16, bankAddressBits = 3
N0.C2.R1: CpgcMemTestRankSetup: colAddressBits = 11, rowAddressBits = 15, bankAddressBits = 3
N7.C2.R1: CpgcMemTestRankSetup: colAddressBits = 11, rowAddressBits = 16, bankAddressBits = 3
N0.C3.R1: CpgcMemTestRankSetup: colAddressBits = 11, rowAddressBits = 15, bankAddressBits = 3
N7.C3.R1: CpgcMemTestRankSetup: colAddressBits = 11, rowAddressBits = 16, bankAddressBits = 3
N1.C0.R1: CpgcMemTestRankSetup: colAddressBits = 11, rowAddressBits = 16, bankAddressBits = 3
N1.C1.R1: CpgcMemTestRankSetup: colAddressBits = 11, rowAddressBits = 16, bankAddressBits = 3
N1.C2.R1: CpgcMemTestRankSetup: colAddressBits = 11, rowAddressBits = 16, bankAddressBits = 3
N1.C3.R1: CpgcMemTestRankSetup: colAddressBits = 11, rowAddressBits = 16, bankAddressBits = 3
N6.C0.R4: CpgcMemTestRankSetup: colAddressBits = 11, rowAddressBits = 15, bankAddressBits = 3
N6.C1.R4: CpgcMemTestRankSetup: colAddressBits = 11, rowAddressBits = 15, bankAddressBits = 3
N6.C2.R4: CpgcMemTestRankSetup: colAddressBits = 11, rowAddressBits = 15, bankAddressBits = 3
N6.C3.R4: CpgcMemTestRankSetup: colAddressBits = 11, rowAddressBits = 15, bankAddressBits = 3
N0.C0.R4: CpgcMemTestRankSetup: colAddressBits = 11, rowAddressBits = 15, bankAddressBits = 3
N0.C1.R4: CpgcMemTestRankSetup: colAddressBits = 11, rowAddressBits = 15, bankAddressBits = 3
N0.C2.R4: CpgcMemTestRankSetup: colAddressBits = 11, rowAddressBits = 15, bankAddressBits = 3
N0.C3.R4: CpgcMemTestRankSetup: colAddressBits = 11, rowAddressBits = 15, bankAddressBits = 3
N6.C0.R5: CpgcMemTestRankSetup: colAddressBits = 11, rowAddressBits = 15, bankAddressBits = 3
N6.C1.R5: CpgcMemTestRankSetup: colAddressBits = 11, rowAddressBits = 15, bankAddressBits = 3
N6.C2.R5: CpgcMemTestRankSetup: colAddressBits = 11, rowAddressBits = 15, bankAddressBits = 3
N6.C3.R5: CpgcMemTestRankSetup: colAddressBits = 11, rowAddressBits = 15, bankAddressBits = 3
N0.C0.R5: CpgcMemTestRankSetup: colAddressBits = 11, rowAddressBits = 15, bankAddressBits = 3
N0.C1.R5: CpgcMemTestRankSetup: colAddressBits = 11, rowAddressBits = 15, bankAddressBits = 3
N0.C2.R5: CpgcMemTestRankSetup: colAddressBits = 11, rowAddressBits = 15, bankAddressBits = 3
N0.C3.R5: CpgcMemTestRankSetup: colAddressBits = 11, rowAddressBits = 15, bankAddressBits = 3

ECC init time = 2975 ms

ECC init time = 2992 ms
Checkpoint Code: Socket 0, 0xB9, 0x04, 0x0000
N6: PcodeRcompEnable
N6: PCU RD CMD Success: MboxStatus = 0x0 Default PCUData Value = 0x9840000
N6: PCU WR CMD Success: MBoxStatus = 0x0 PCU_MISC_CONFIG = 0x8840000
N6: Set rst_cpl2 to enable RCOMP
N6: InitThrottling
N6: Init Throttling

N6: 
::MPM:: 2> dimmInWTTable = 0, WTcurrentDimm.WTLvAndDramDensity = 3,   ddrVoltage = 0

N6: 
::MEM DDR3:: DDR3 Memory detected. Look at DDR3 Power table now...
N6.C0.D0: Init DRAM RAPL

N6.C0.D0: MTS mfgid = 0x4A10
N6.C0.D0: MTS did_rid = 0x3
N6.C0.D0: MTS Capabilities = 0x6F00
N6.C0.D0: MTS Current Ambient Temp = 0x18C2
N6.C0.D0: TCRIT  = 0x690
N6: 
::MPM:: 2> dimmInWTTable = 0, WTcurrentDimm.WTLvAndDramDensity = 3,   ddrVoltage = 0

N6: 
::MEM DDR3:: DDR3 Memory detected. Look at DDR3 Power table now...
N6.C0.D1: Init DRAM RAPL

N6.C0.D1: MTS mfgid = 0x4A10
N6.C0.D1: MTS did_rid = 0x3
N6.C0.D1: MTS Capabilities = 0x6F00
N6.C0.D1: MTS Current Ambient Temp = 0xC2
N6.C0.D1: TCRIT  = 0x690
N6: 
::MPM:: 2> dimmInWTTable = 0, WTcurrentDimm.WTLvAndDramDensity = 3,   ddrVoltage = 0

N6: 
::MEM DDR3:: DDR3 Memory detected. Look at DDR3 Power table now...
N6.C1.D0: Init DRAM RAPL

N6.C1.D0: MTS mfgid = 0x4A10
N6.C1.D0: MTS did_rid = 0x3
N6.C1.D0: MTS Capabilities = 0x6F00
N6.C1.D0: MTS Current Ambient Temp = 0x24C2
N6.C1.D0: TCRIT  = 0x690
N6: 
::MPM:: 2> dimmInWTTable = 0, WTcurrentDimm.WTLvAndDramDensity = 3,   ddrVoltage = 0

N6: 
::MEM DDR3:: DDR3 Memory detected. Look at DDR3 Power table now...
N6.C1.D1: Init DRAM RAPL

N6.C1.D1: MTS mfgid = 0x4A10
N6.C1.D1: MTS did_rid = 0x3
N6.C1.D1: MTS Capabilities = 0x6F00
N6.C1.D1: MTS Current Ambient Temp = 0x1CC2
N6.C1.D1: TCRIT  = 0x690
N6: SMBCNTL_0 = 0x38000033
N6: 
::MPM:: 2> dimmInWTTable = 0, WTcurrentDimm.WTLvAndDramDensity = 3,   ddrVoltage = 0

N6: 
::MEM DDR3:: DDR3 Memory detected. Look at DDR3 Power table now...
N6.C2.D0: Init DRAM RAPL

N6.C2.D0: MTS mfgid = 0x4A10
N6.C2.D0: MTS did_rid = 0x3
N6.C2.D0: MTS Capabilities = 0x6F00
N6.C2.D0: MTS Current Ambient Temp = 0xE0C1
N6.C2.D0: TCRIT  = 0x690
N6: 
::MPM:: 2> dimmInWTTable = 0, WTcurrentDimm.WTLvAndDramDensity = 3,   ddrVoltage = 0

N6: 
::MEM DDR3:: DDR3 Memory detected. Look at DDR3 Power table now...
N6.C2.D1: Init DRAM RAPL

N6.C2.D1: MTS mfgid = 0x4A10
N6.C2.D1: MTS did_rid = 0x3
N6.C2.D1: MTS Capabilities = 0x6F00
N6.C2.D1: MTS Current Ambient Temp = 0xD4C1
N6.C2.D1: TCRIT  = 0x690
N6: 
::MPM:: 2> dimmInWTTable = 0, WTcurrentDimm.WTLvAndDramDensity = 3,   ddrVoltage = 0

N6: 
::MEM DDR3:: DDR3 Memory detected. Look at DDR3 Power table now...
N6.C3.D0: Init DRAM RAPL

N6.C3.D0: MTS mfgid = 0x4A10
N6.C3.D0: MTS did_rid = 0x3
N6.C3.D0: MTS Capabilities = 0x6F00
N6.C3.D0: MTS Current Ambient Temp = 0xCCC1
N6.C3.D0: TCRIT  = 0x690
N6: 
::MPM:: 2> dimmInWTTable = 0, WTcurrentDimm.WTLvAndDramDensity = 3,   ddrVoltage = 0

N6: 
::MEM DDR3:: DDR3 Memory detected. Look at DDR3 Power table now...
N6.C3.D1: Init DRAM RAPL

N6.C3.D1: MTS mfgid = 0x4A10
N6.C3.D1: MTS did_rid = 0x3
N6.C3.D1: MTS Capabilities = 0x6F00
N6.C3.D1: MTS Current Ambient Temp = 0xD4C1
N6.C3.D1: TCRIT  = 0x690
N6: SMBCNTL_1 = 0x38000033
N6: 
Init DRAM Phase Shedding
N6: Memory current estimate value 20
N6: Setting Node 0x6 - VR0 Active PSI = PS0
N6: Memory current estimate value 20
N6: Setting Node 0x6 - VR1 Active PSI = PS0
Checkpoint Code: Socket 0, 0xB7, 0x0E, 0x0000
N6: SwitchToNormalMode
N0: PcodeRcompEnable
N6: SetupMiscFeatures
N0: PCU RD CMD Success: MboxStatus = 0x0 Default PCUData Value = 0x9840000
N6: Clear Errors
N0: PCU WR CMD Success: MBoxStatus = 0x0 PCU_MISC_CONFIG = 0x8840000
N7: PcodeRcompEnable
N0: Set rst_cpl2 to enable RCOMP
N7: PCU RD CMD Success: MboxStatus = 0x0 Default PCUData Value = 0x8840000
Checkpoint Code: Socket 0, 0xBB, 0x01, 0x0000
N7: PCU WR CMD Success: MBoxStatus = 0x0 PCU_MISC_CONFIG = 0x8840000
N0: InitThrottling
N7: InitThrottling
N0: Init Throttling

N0: 
::MPM:: 2> dimmInWTTable = 0, WTcurrentDimm.WTLvAndDramDensity = 3,   ddrVoltage = 0

N0: 
::MEM DDR3:: DDR3 Memory detected. Look at DDR3 Power table now...
N0.C0.D0: Init DRAM RAPL

N0.C0.D0: MTS mfgid = 0x5400
N0.C0.D0: MTS did_rid = 0x121
N0.C0.D0: MTS Capabilities = 0xEF00
N0.C0.D0: MTS Current Ambient Temp = 0xF4C1
N0.C0.D0: TCRIT  = 0x690
N0: 
::MPM:: 2> dimmInWTTable = 0, WTcurrentDimm.WTLvAndDramDensity = 3,   ddrVoltage = 0

N0: 
::MEM DDR3:: DDR3 Memory detected. Look at DDR3 Power table now...
N0.C0.D1: Init DRAM RAPL

N0.C0.D1: MTS mfgid = 0x5400
N0.C0.D1: MTS did_rid = 0x121
N0.C0.D1: MTS Capabilities = 0xEF00
N0.C0.D1: MTS Current Ambient Temp = 0xE4C1
N0.C0.D1: TCRIT  = 0x690
N0: 
::MPM:: 2> dimmInWTTable = 0, WTcurrentDimm.WTLvAndDramDensity = 3,   ddrVoltage = 0

N0: 
::MEM DDR3:: DDR3 Memory detected. Look at DDR3 Power table now...
N0.C1.D0: Init DRAM RAPL

N0.C1.D0: MTS mfgid = 0x4A10
N0.C1.D0: MTS did_rid = 0x3
N0.C1.D0: MTS Capabilities = 0x6F00
N0.C1.D0: MTS Current Ambient Temp = 0x8C2
N0.C1.D0: TCRIT  = 0x690
N0: 
::MPM:: 2> dimmInWTTable = 0, WTcurrentDimm.WTLvAndDramDensity = 3,   ddrVoltage = 0

N0: 
::MEM DDR3:: DDR3 Memory detected. Look at DDR3 Power table now...
N0.C1.D1: Init DRAM RAPL

N0.C1.D1: MTS mfgid = 0x5400
N0.C1.D1: MTS did_rid = 0x121
N0.C1.D1: MTS Capabilities = 0xEF00
N0.C1.D1: MTS Current Ambient Temp = 0x4C2
N0.C1.D1: TCRIT  = 0x690
N0: SMBCNTL_0 = 0x38000033
N0: 
::MPM:: 2> dimmInWTTable = 0, WTcurrentDimm.WTLvAndDramDensity = 3,   ddrVoltage = 0

N0: 
::MEM DDR3:: DDR3 Memory detected. Look at DDR3 Power table now...
N0.C2.D0: Init DRAM RAPL

N0.C2.D0: MTS mfgid = 0x4A10
N0.C2.D0: MTS did_rid = 0x3
N0.C2.D0: MTS Capabilities = 0x6F00
N0.C2.D0: MTS Current Ambient Temp = 0xD4C1
N0.C2.D0: TCRIT  = 0x690
N0: 
::MPM:: 2> dimmInWTTable = 0, WTcurrentDimm.WTLvAndDramDensity = 3,   ddrVoltage = 0

N0: 
::MEM DDR3:: DDR3 Memory detected. Look at DDR3 Power table now...
N0.C2.D1: Init DRAM RAPL

N0.C2.D1: MTS mfgid = 0x5400
N0.C2.D1: MTS did_rid = 0x121
N0.C2.D1: MTS Capabilities = 0xEF00
N0.C2.D1: MTS Current Ambient Temp = 0xBCC1
N0.C2.D1: TCRIT  = 0x690
N0: 
::MPM:: 2> dimmInWTTable = 0, WTcurrentDimm.WTLvAndDramDensity = 3,   ddrVoltage = 0

N0: 
::MEM DDR3:: DDR3 Memory detected. Look at DDR3 Power table now...
N0.C3.D0: Init DRAM RAPL

N0.C3.D0: MTS mfgid = 0x5400
N0.C3.D0: MTS did_rid = 0x121
N0.C3.D0: MTS Capabilities = 0xEF00
N0.C3.D0: MTS Current Ambient Temp = 0xB0C1
N0.C3.D0: TCRIT  = 0x690
N0: 
::MPM:: 2> dimmInWTTable = 0, WTcurrentDimm.WTLvAndDramDensity = 3,   ddrVoltage = 0

N0: 
::MEM DDR3:: DDR3 Memory detected. Look at DDR3 Power table now...
N0.C3.D1: Init DRAM RAPL

N0.C3.D1: MTS mfgid = 0x4A10
N0.C3.D1: MTS did_rid = 0x3
N0.C3.D1: MTS Capabilities = 0x6F00
N0.C3.D1: MTS Current Ambient Temp = 0xC4C1
N0.C3.D1: TCRIT  = 0x690
N0: SMBCNTL_1 = 0x38000033
N0: 
Init DRAM Phase Shedding
N0: Memory current estimate value 20
N0: Setting Node 0x0 - VR0 Active PSI = PS0
N0: Memory current estimate value 20
N0: Setting Node 0x0 - VR1 Active PSI = PS0
N7: Init Throttling

N7: 
::MPM:: 2> dimmInWTTable = 0, WTcurrentDimm.WTLvAndDramDensity = 4,   ddrVoltage = 0

N7: 
::MEM DDR3:: DDR3 Memory detected. Look at DDR3 Power table now...
N7.C0.D0: Init DRAM RAPL

N7.C0.D0: MTS mfgid = 0x4A10
N7.C0.D0: MTS did_rid = 0x3
N7.C0.D0: MTS Capabilities = 0x6F00
N7.C0.D0: MTS Current Ambient Temp = 0xD8C1
N7.C0.D0: TCRIT  = 0x690
N7: 
::MPM:: 2> dimmInWTTable = 0, WTcurrentDimm.WTLvAndDramDensity = 4,   ddrVoltage = 0

N7: 
::MEM DDR3:: DDR3 Memory detected. Look at DDR3 Power table now...
N7.C1.D0: Init DRAM RAPL

N7.C1.D0: MTS mfgid = 0x5400
N7.C1.D0: MTS did_rid = 0x121
N7.C1.D0: MTS Capabilities = 0xEF00
N7.C1.D0: MTS Current Ambient Temp = 0xD4C1
N7.C1.D0: TCRIT  = 0x690
N7: SMBCNTL_0 = 0x38000011
N7: 
::MPM:: 2> dimmInWTTable = 0, WTcurrentDimm.WTLvAndDramDensity = 4,   ddrVoltage = 0

N7: 
::MEM DDR3:: DDR3 Memory detected. Look at DDR3 Power table now...
N7.C2.D0: Init DRAM RAPL

N7.C2.D0: MTS mfgid = 0x5400
N7.C2.D0: MTS did_rid = 0x121
N7.C2.D0: MTS Capabilities = 0xEF00
N7.C2.D0: MTS Current Ambient Temp = 0xB8C1
N7.C2.D0: TCRIT  = 0x690
N7: 
::MPM:: 2> dimmInWTTable = 0, WTcurrentDimm.WTLvAndDramDensity = 4,   ddrVoltage = 0

N7: 
::MEM DDR3:: DDR3 Memory detected. Look at DDR3 Power table now...
N7.C3.D0: Init DRAM RAPL

N7.C3.D0: MTS mfgid = 0x5400
N7.C3.D0: MTS did_rid = 0x121
N7.C3.D0: MTS Capabilities = 0xEF00
N7.C3.D0: MTS Current Ambient Temp = 0xC8C1
N7.C3.D0: TCRIT  = 0x690
N7: SMBCNTL_1 = 0x38000011
N7: 
Init DRAM Phase Shedding
N7: Memory current estimate value E
N7: Setting Node 0x7 - VR2 Active PSI = PS1
N7: Memory current estimate value E
N7: Setting Node 0x7 - VR3 Active PSI = PS1
Checkpoint Code: Socket 0, 0xBB, 0x02, 0x0000
N7: SwitchToNormalMode
N0: SwitchToNormalMode
N7: SetupMiscFeatures
Checkpoint Code: Socket 0, 0xBB, 0x04, 0x0000
N7: Clear Errors
N0: SetupMiscFeatures
N0: Clear Errors
N1: PcodeRcompEnable
N1: PCU RD CMD Success: MboxStatus = 0x0 Default PCUData Value = 0x8840000
N1: PCU WR CMD Success: MBoxStatus = 0x0 PCU_MISC_CONFIG = 0x8840000
Checkpoint Code: Socket 0, 0xBB, 0x01, 0x0000
N1: InitThrottling
N1: Init Throttling

N1: 
::MPM:: 2> dimmInWTTable = 0, WTcurrentDimm.WTLvAndDramDensity = 4,   ddrVoltage = 0

N1: 
::MEM DDR3:: DDR3 Memory detected. Look at DDR3 Power table now...
N1.C0.D0: Init DRAM RAPL

N1.C0.D0: MTS mfgid = 0x5400
N1.C0.D0: MTS did_rid = 0x121
N1.C0.D0: MTS Capabilities = 0xEF00
N1.C0.D0: MTS Current Ambient Temp = 0xB8C1
N1.C0.D0: TCRIT  = 0x690
N1: 
::MPM:: 2> dimmInWTTable = 0, WTcurrentDimm.WTLvAndDramDensity = 4,   ddrVoltage = 0

N1: 
::MEM DDR3:: DDR3 Memory detected. Look at DDR3 Power table now...
N1.C1.D0: Init DRAM RAPL

N1.C1.D0: MTS mfgid = 0x5400
N1.C1.D0: MTS did_rid = 0x121
N1.C1.D0: MTS Capabilities = 0xEF00
N1.C1.D0: MTS Current Ambient Temp = 0xC0C1
N1.C1.D0: TCRIT  = 0x690
N1: SMBCNTL_0 = 0x38000011
N1: 
::MPM:: 2> dimmInWTTable = 0, WTcurrentDimm.WTLvAndDramDensity = 4,   ddrVoltage = 0

N1: 
::MEM DDR3:: DDR3 Memory detected. Look at DDR3 Power table now...
N1.C2.D0: Init DRAM RAPL

N1.C2.D0: MTS mfgid = 0x5400
N1.C2.D0: MTS did_rid = 0x121
N1.C2.D0: MTS Capabilities = 0xEF00
N1.C2.D0: MTS Current Ambient Temp = 0xA8C1
N1.C2.D0: TCRIT  = 0x690
N1: 
::MPM:: 2> dimmInWTTable = 0, WTcurrentDimm.WTLvAndDramDensity = 4,   ddrVoltage = 0

N1: 
::MEM DDR3:: DDR3 Memory detected. Look at DDR3 Power table now...
N1.C3.D0: Init DRAM RAPL

N1.C3.D0: MTS mfgid = 0x5400
N1.C3.D0: MTS did_rid = 0x121
N1.C3.D0: MTS Capabilities = 0xEF00
N1.C3.D0: MTS Current Ambient Temp = 0xB4C1
N1.C3.D0: TCRIT  = 0x690
N1: SMBCNTL_1 = 0x38000011
N1: 
Init DRAM Phase Shedding
N1: Memory current estimate value E
N1: Setting Node 0x1 - VR2 Active PSI = PS1
N1: Memory current estimate value E
N1: Setting Node 0x1 - VR3 Active PSI = PS1
Checkpoint Code: Socket 0, 0xBB, 0x02, 0x0000
N1: SwitchToNormalMode
Checkpoint Code: Socket 0, 0xBB, 0x04, 0x0000
N1: SetupMiscFeatures
N1: Clear Errors
No Pending Reset, clearing the ADR status bit
No Pending Reset, clearing the ADR status bit
No Pending Reset, clearing the ADR status bit
No Pending Reset, clearing the ADR status bit
Send NVRAM common data from S1 to S0
Send NVRAM common data from S2 to S0
Send NVRAM common data from S3 to S0
Get NVRAM common data from S1 to S0
Get NVRAM common data from S2 to S0
Get NVRAM common data from S3 to S0

 Node[0] Status = ENABLED  . Encountered Warning/Fatal Errors = 0

 Node[1] Status = ENABLED  . Encountered Warning/Fatal Errors = 0

 Node[2] Status = ENABLED  . Encountered Warning/Fatal Errors = 0

 Node[3] Status = ENABLED  . Encountered Warning/Fatal Errors = 0

 Node[4] Status = ENABLED  . Encountered Warning/Fatal Errors = 0

 Node[5] Status = ENABLED  . Encountered Warning/Fatal Errors = 0

 Node[6] Status = ENABLED  . Encountered Warning/Fatal Errors = 0

 Node[7] Status = ENABLED  . Encountered Warning/Fatal Errors = 0
Checkpoint Code: Socket 0, 0xBC, 0x00, 0x0000
N0: Memory Size = 1024 (64MB units). System Memory Size = 1024 (64MB units)
N1: Memory Size = 1024 (64MB units). System Memory Size = 2048 (64MB units)
N2: Memory Size = 1024 (64MB units). System Memory Size = 3072 (64MB units)
N3: Memory Size = 1024 (64MB units). System Memory Size = 4096 (64MB units)
N4: Memory Size = 1024 (64MB units). System Memory Size = 5120 (64MB units)
N5: Memory Size = 1024 (64MB units). System Memory Size = 6144 (64MB units)
N6: Memory Size = 1024 (64MB units). System Memory Size = 7168 (64MB units)
N7: Memory Size = 1024 (64MB units). System Memory Size = 8192 (64MB units)
128 bytes Address Interleaving.
START SADNuma[2] (TOLM: 00000020 Optimize 2)
SAD 0[HA Limit 820h*(64MB), Ways 2] = 0 4 0 4 0 4 0 4 
SAD 1[HA Limit 1020h*(64MB), Ways 2] = 1 5 1 5 1 5 1 5 
SAD 2[HA Limit 1820h*(64MB), Ways 2] = 2 6 2 6 2 6 2 6 
SAD 3[HA Limit 2020h*(64MB), Ways 2] = 3 7 3 7 3 7 3 7 
TAD Interleave (TOLM: 00000020 Optimize 2)
N8: Adjust Partial Memory Size = 0 (64MB units). System Memory Size = 8192 (64MB units)

		----------- Memory Map Info ----------------
Non-XOR mode
 Node RAS Config = 
Node:0 Channel Independent mode enabled
Node:1 Channel Independent mode enabled
Node:2 Channel Independent mode enabled
Node:3 Channel Independent mode enabled
Node:4 Channel Independent mode enabled
Node:5 Channel Independent mode enabled
Node:6 Channel Independent mode enabled
Node:7 Channel Independent mode enabled
 NUMA Config
 Node Interleave Ways: 2
 System Mem Size (64MB granularity): 8192

 SAD Table
 Rule Enable 	Limit 	Mode 	Ways 	Interleave List(right to left)
-------------------------------------------------------------------
 0		1				2080			1			2			40404040
 1		1				4128			1			2			51515151
 2		1				6176			1			2			62626262
 3		1				8224			1			2			73737373

----------- Node Info ----------------
----------- Node 0 
 Node Enabled
 Node max DIMM pop count = 2
 Node mem size (64MB) = 1024

--------------------- TAD Info ------------------------------

 TAD Table (Node 0)
 Rule 	Enable 	Limit 	Mode 	Ch Ways
---------------------------------------
 Home Agent 0)

 0	1	32	1	4
	TAD Interleave List
	Way 	Target 	Offset 	ChIndex
	0	0	0	0
	1	1	0	0
	2	2	0	0
	3	3	0	0

 1	1	2080	1	4
	TAD Interleave List
	Way 	Target 	Offset 	ChIndex
	0	0	32	0
	1	1	32	0
	2	2	32	0
	3	3	32	0


----------- Channel Info ----------------
----------- Channel 0 
 Channel Enabled
 Channel mem size (64MB) = 256

 --------------------- RIR Info ------------------------------

 RIR Table (Node 0, Channel 0)
----------------------------------------------

 Rule 	Enable 	Limit(Ch Space) 	Ways
 0	1	256			4

	Rank Interleave List
	Way 	Target 	Offset
	0	0	0
	1	4	0
	2	1	0
	3	5	0
	4	0	0
	5	0	0
	6	0	0
	7	0	0

----------- Channel 1 
 Channel Enabled
 Channel mem size (64MB) = 256

 --------------------- RIR Info ------------------------------

 RIR Table (Node 0, Channel 1)
----------------------------------------------

 Rule 	Enable 	Limit(Ch Space) 	Ways
 0	1	256			4

	Rank Interleave List
	Way 	Target 	Offset
	0	0	0
	1	4	0
	2	1	0
	3	5	0
	4	0	0
	5	0	0
	6	0	0
	7	0	0

----------- Channel 2 
 Channel Enabled
 Channel mem size (64MB) = 256

 --------------------- RIR Info ------------------------------

 RIR Table (Node 0, Channel 2)
----------------------------------------------

 Rule 	Enable 	Limit(Ch Space) 	Ways
 0	1	256			4

	Rank Interleave List
	Way 	Target 	Offset
	0	0	0
	1	4	0
	2	1	0
	3	5	0
	4	0	0
	5	0	0
	6	0	0
	7	0	0

----------- Channel 3 
 Channel Enabled
 Channel mem size (64MB) = 256

 --------------------- RIR Info ------------------------------

 RIR Table (Node 0, Channel 3)
----------------------------------------------

 Rule 	Enable 	Limit(Ch Space) 	Ways
 0	1	256			4

	Rank Interleave List
	Way 	Target 	Offset
	0	0	0
	1	4	0
	2	1	0
	3	5	0
	4	0	0
	5	0	0
	6	0	0
	7	0	0

----------- Node 1 
 Node Enabled
 Node max DIMM pop count = 1
 Node mem size (64MB) = 1024

--------------------- TAD Info ------------------------------

 TAD Table (Node 1)
 Rule 	Enable 	Limit 	Mode 	Ch Ways
---------------------------------------
 Home Agent 4)

 0	1	32	1	4
	TAD Interleave List
	Way 	Target 	Offset 	ChIndex
	0	0	0	0
	1	1	0	0
	2	2	0	0
	3	3	0	0

 1	1	2080	1	4
	TAD Interleave List
	Way 	Target 	Offset 	ChIndex
	0	0	32	0
	1	1	32	0
	2	2	32	0
	3	3	32	0


----------- Channel Info ----------------
----------- Channel 0 
 Channel Enabled
 Channel mem size (64MB) = 256

 --------------------- RIR Info ------------------------------

 RIR Table (Node 1, Channel 0)
----------------------------------------------

 Rule 	Enable 	Limit(Ch Space) 	Ways
 0	1	256			2

	Rank Interleave List
	Way 	Target 	Offset
	0	0	0
	1	1	0
	2	0	0
	3	0	0
	4	0	0
	5	0	0
	6	0	0
	7	0	0

----------- Channel 1 
 Channel Enabled
 Channel mem size (64MB) = 256

 --------------------- RIR Info ------------------------------

 RIR Table (Node 1, Channel 1)
----------------------------------------------

 Rule 	Enable 	Limit(Ch Space) 	Ways
 0	1	256			2

	Rank Interleave List
	Way 	Target 	Offset
	0	0	0
	1	1	0
	2	0	0
	3	0	0
	4	0	0
	5	0	0
	6	0	0
	7	0	0

----------- Channel 2 
 Channel Enabled
 Channel mem size (64MB) = 256

 --------------------- RIR Info ------------------------------

 RIR Table (Node 1, Channel 2)
----------------------------------------------

 Rule 	Enable 	Limit(Ch Space) 	Ways
 0	1	256			2

	Rank Interleave List
	Way 	Target 	Offset
	0	0	0
	1	1	0
	2	0	0
	3	0	0
	4	0	0
	5	0	0
	6	0	0
	7	0	0

----------- Channel 3 
 Channel Enabled
 Channel mem size (64MB) = 256

 --------------------- RIR Info ------------------------------

 RIR Table (Node 1, Channel 3)
----------------------------------------------

 Rule 	Enable 	Limit(Ch Space) 	Ways
 0	1	256			2

	Rank Interleave List
	Way 	Target 	Offset
	0	0	0
	1	1	0
	2	0	0
	3	0	0
	4	0	0
	5	0	0
	6	0	0
	7	0	0

----------- Node 2 
 Node Enabled
 Node max DIMM pop count = 2
 Node mem size (64MB) = 1024

--------------------- TAD Info ------------------------------

 TAD Table (Node 2)
 Rule 	Enable 	Limit 	Mode 	Ch Ways
---------------------------------------
 Home Agent 1)

 0	1	4128	1	4
	TAD Interleave List
	Way 	Target 	Offset 	ChIndex
	0	0	2080	0
	1	1	2080	0
	2	2	2080	0
	3	3	2080	0


----------- Channel Info ----------------
----------- Channel 0 
 Channel Enabled
 Channel mem size (64MB) = 256

 --------------------- RIR Info ------------------------------

 RIR Table (Node 2, Channel 0)
----------------------------------------------

 Rule 	Enable 	Limit(Ch Space) 	Ways
 0	1	256			4

	Rank Interleave List
	Way 	Target 	Offset
	0	0	0
	1	4	0
	2	1	0
	3	5	0
	4	0	0
	5	0	0
	6	0	0
	7	0	0

----------- Channel 1 
 Channel Enabled
 Channel mem size (64MB) = 256

 --------------------- RIR Info ------------------------------

 RIR Table (Node 2, Channel 1)
----------------------------------------------

 Rule 	Enable 	Limit(Ch Space) 	Ways
 0	1	256			4

	Rank Interleave List
	Way 	Target 	Offset
	0	0	0
	1	4	0
	2	1	0
	3	5	0
	4	0	0
	5	0	0
	6	0	0
	7	0	0

----------- Channel 2 
 Channel Enabled
 Channel mem size (64MB) = 256

 --------------------- RIR Info ------------------------------

 RIR Table (Node 2, Channel 2)
----------------------------------------------

 Rule 	Enable 	Limit(Ch Space) 	Ways
 0	1	256			4

	Rank Interleave List
	Way 	Target 	Offset
	0	0	0
	1	4	0
	2	1	0
	3	5	0
	4	0	0
	5	0	0
	6	0	0
	7	0	0

----------- Channel 3 
 Channel Enabled
 Channel mem size (64MB) = 256

 --------------------- RIR Info ------------------------------

 RIR Table (Node 2, Channel 3)
----------------------------------------------

 Rule 	Enable 	Limit(Ch Space) 	Ways
 0	1	256			4

	Rank Interleave List
	Way 	Target 	Offset
	0	0	0
	1	4	0
	2	1	0
	3	5	0
	4	0	0
	5	0	0
	6	0	0
	7	0	0

----------- Node 3 
 Node Enabled
 Node max DIMM pop count = 1
 Node mem size (64MB) = 1024

--------------------- TAD Info ------------------------------

 TAD Table (Node 3)
 Rule 	Enable 	Limit 	Mode 	Ch Ways
---------------------------------------
 Home Agent 5)

 0	1	4128	1	4
	TAD Interleave List
	Way 	Target 	Offset 	ChIndex
	0	0	2080	0
	1	1	2080	0
	2	2	2080	0
	3	3	2080	0


----------- Channel Info ----------------
----------- Channel 0 
 Channel Enabled
 Channel mem size (64MB) = 256

 --------------------- RIR Info ------------------------------

 RIR Table (Node 3, Channel 0)
----------------------------------------------

 Rule 	Enable 	Limit(Ch Space) 	Ways
 0	1	256			2

	Rank Interleave List
	Way 	Target 	Offset
	0	0	0
	1	1	0
	2	0	0
	3	0	0
	4	0	0
	5	0	0
	6	0	0
	7	0	0

----------- Channel 1 
 Channel Enabled
 Channel mem size (64MB) = 256

 --------------------- RIR Info ------------------------------

 RIR Table (Node 3, Channel 1)
----------------------------------------------

 Rule 	Enable 	Limit(Ch Space) 	Ways
 0	1	256			2

	Rank Interleave List
	Way 	Target 	Offset
	0	0	0
	1	1	0
	2	0	0
	3	0	0
	4	0	0
	5	0	0
	6	0	0
	7	0	0

----------- Channel 2 
 Channel Enabled
 Channel mem size (64MB) = 256

 --------------------- RIR Info ------------------------------

 RIR Table (Node 3, Channel 2)
----------------------------------------------

 Rule 	Enable 	Limit(Ch Space) 	Ways
 0	1	256			2

	Rank Interleave List
	Way 	Target 	Offset
	0	0	0
	1	1	0
	2	0	0
	3	0	0
	4	0	0
	5	0	0
	6	0	0
	7	0	0

----------- Channel 3 
 Channel Enabled
 Channel mem size (64MB) = 256

 --------------------- RIR Info ------------------------------

 RIR Table (Node 3, Channel 3)
----------------------------------------------

 Rule 	Enable 	Limit(Ch Space) 	Ways
 0	1	256			2

	Rank Interleave List
	Way 	Target 	Offset
	0	0	0
	1	1	0
	2	0	0
	3	0	0
	4	0	0
	5	0	0
	6	0	0
	7	0	0

----------- Node 4 
 Node Enabled
 Node max DIMM pop count = 2
 Node mem size (64MB) = 1024

--------------------- TAD Info ------------------------------

 TAD Table (Node 4)
 Rule 	Enable 	Limit 	Mode 	Ch Ways
---------------------------------------
 Home Agent 2)

 0	1	6176	1	4
	TAD Interleave List
	Way 	Target 	Offset 	ChIndex
	0	0	4128	0
	1	1	4128	0
	2	2	4128	0
	3	3	4128	0


----------- Channel Info ----------------
----------- Channel 0 
 Channel Enabled
 Channel mem size (64MB) = 256

 --------------------- RIR Info ------------------------------

 RIR Table (Node 4, Channel 0)
----------------------------------------------

 Rule 	Enable 	Limit(Ch Space) 	Ways
 0	1	256			4

	Rank Interleave List
	Way 	Target 	Offset
	0	0	0
	1	4	0
	2	1	0
	3	5	0
	4	0	0
	5	0	0
	6	0	0
	7	0	0

----------- Channel 1 
 Channel Enabled
 Channel mem size (64MB) = 256

 --------------------- RIR Info ------------------------------

 RIR Table (Node 4, Channel 1)
----------------------------------------------

 Rule 	Enable 	Limit(Ch Space) 	Ways
 0	1	256			4

	Rank Interleave List
	Way 	Target 	Offset
	0	0	0
	1	4	0
	2	1	0
	3	5	0
	4	0	0
	5	0	0
	6	0	0
	7	0	0

----------- Channel 2 
 Channel Enabled
 Channel mem size (64MB) = 256

 --------------------- RIR Info ------------------------------

 RIR Table (Node 4, Channel 2)
----------------------------------------------

 Rule 	Enable 	Limit(Ch Space) 	Ways
 0	1	256			4

	Rank Interleave List
	Way 	Target 	Offset
	0	0	0
	1	4	0
	2	1	0
	3	5	0
	4	0	0
	5	0	0
	6	0	0
	7	0	0

----------- Channel 3 
 Channel Enabled
 Channel mem size (64MB) = 256

 --------------------- RIR Info ------------------------------

 RIR Table (Node 4, Channel 3)
----------------------------------------------

 Rule 	Enable 	Limit(Ch Space) 	Ways
 0	1	256			4

	Rank Interleave List
	Way 	Target 	Offset
	0	0	0
	1	4	0
	2	1	0
	3	5	0
	4	0	0
	5	0	0
	6	0	0
	7	0	0

----------- Node 5 
 Node Enabled
 Node max DIMM pop count = 1
 Node mem size (64MB) = 1024

--------------------- TAD Info ------------------------------

 TAD Table (Node 5)
 Rule 	Enable 	Limit 	Mode 	Ch Ways
---------------------------------------
 Home Agent 6)

 0	1	6176	1	4
	TAD Interleave List
	Way 	Target 	Offset 	ChIndex
	0	0	4128	0
	1	1	4128	0
	2	2	4128	0
	3	3	4128	0


----------- Channel Info ----------------
----------- Channel 0 
 Channel Enabled
 Channel mem size (64MB) = 256

 --------------------- RIR Info ------------------------------

 RIR Table (Node 5, Channel 0)
----------------------------------------------

 Rule 	Enable 	Limit(Ch Space) 	Ways
 0	1	256			2

	Rank Interleave List
	Way 	Target 	Offset
	0	0	0
	1	1	0
	2	0	0
	3	0	0
	4	0	0
	5	0	0
	6	0	0
	7	0	0

----------- Channel 1 
 Channel Enabled
 Channel mem size (64MB) = 256

 --------------------- RIR Info ------------------------------

 RIR Table (Node 5, Channel 1)
----------------------------------------------

 Rule 	Enable 	Limit(Ch Space) 	Ways
 0	1	256			2

	Rank Interleave List
	Way 	Target 	Offset
	0	0	0
	1	1	0
	2	0	0
	3	0	0
	4	0	0
	5	0	0
	6	0	0
	7	0	0

----------- Channel 2 
 Channel Enabled
 Channel mem size (64MB) = 256

 --------------------- RIR Info ------------------------------

 RIR Table (Node 5, Channel 2)
----------------------------------------------

 Rule 	Enable 	Limit(Ch Space) 	Ways
 0	1	256			2

	Rank Interleave List
	Way 	Target 	Offset
	0	0	0
	1	1	0
	2	0	0
	3	0	0
	4	0	0
	5	0	0
	6	0	0
	7	0	0

----------- Channel 3 
 Channel Enabled
 Channel mem size (64MB) = 256

 --------------------- RIR Info ------------------------------

 RIR Table (Node 5, Channel 3)
----------------------------------------------

 Rule 	Enable 	Limit(Ch Space) 	Ways
 0	1	256			2

	Rank Interleave List
	Way 	Target 	Offset
	0	0	0
	1	1	0
	2	0	0
	3	0	0
	4	0	0
	5	0	0
	6	0	0
	7	0	0

----------- Node 6 
 Node Enabled
 Node max DIMM pop count = 2
 Node mem size (64MB) = 1024

--------------------- TAD Info ------------------------------

 TAD Table (Node 6)
 Rule 	Enable 	Limit 	Mode 	Ch Ways
---------------------------------------
 Home Agent 3)

 0	1	8224	1	4
	TAD Interleave List
	Way 	Target 	Offset 	ChIndex
	0	0	6176	0
	1	1	6176	0
	2	2	6176	0
	3	3	6176	0


----------- Channel Info ----------------
----------- Channel 0 
 Channel Enabled
 Channel mem size (64MB) = 256

 --------------------- RIR Info ------------------------------

 RIR Table (Node 6, Channel 0)
----------------------------------------------

 Rule 	Enable 	Limit(Ch Space) 	Ways
 0	1	256			4

	Rank Interleave List
	Way 	Target 	Offset
	0	0	0
	1	4	0
	2	1	0
	3	5	0
	4	0	0
	5	0	0
	6	0	0
	7	0	0

----------- Channel 1 
 Channel Enabled
 Channel mem size (64MB) = 256

 --------------------- RIR Info ------------------------------

 RIR Table (Node 6, Channel 1)
----------------------------------------------

 Rule 	Enable 	Limit(Ch Space) 	Ways
 0	1	256			4

	Rank Interleave List
	Way 	Target 	Offset
	0	0	0
	1	4	0
	2	1	0
	3	5	0
	4	0	0
	5	0	0
	6	0	0
	7	0	0

----------- Channel 2 
 Channel Enabled
 Channel mem size (64MB) = 256

 --------------------- RIR Info ------------------------------

 RIR Table (Node 6, Channel 2)
----------------------------------------------

 Rule 	Enable 	Limit(Ch Space) 	Ways
 0	1	256			4

	Rank Interleave List
	Way 	Target 	Offset
	0	0	0
	1	4	0
	2	1	0
	3	5	0
	4	0	0
	5	0	0
	6	0	0
	7	0	0

----------- Channel 3 
 Channel Enabled
 Channel mem size (64MB) = 256

 --------------------- RIR Info ------------------------------

 RIR Table (Node 6, Channel 3)
----------------------------------------------

 Rule 	Enable 	Limit(Ch Space) 	Ways
 0	1	256			4

	Rank Interleave List
	Way 	Target 	Offset
	0	0	0
	1	4	0
	2	1	0
	3	5	0
	4	0	0
	5	0	0
	6	0	0
	7	0	0

----------- Node 7 
 Node Enabled
 Node max DIMM pop count = 1
 Node mem size (64MB) = 1024

--------------------- TAD Info ------------------------------

 TAD Table (Node 7)
 Rule 	Enable 	Limit 	Mode 	Ch Ways
---------------------------------------
 Home Agent 7)

 0	1	8224	1	4
	TAD Interleave List
	Way 	Target 	Offset 	ChIndex
	0	0	6176	0
	1	1	6176	0
	2	2	6176	0
	3	3	6176	0


----------- Channel Info ----------------
----------- Channel 0 
 Channel Enabled
 Channel mem size (64MB) = 256

 --------------------- RIR Info ------------------------------

 RIR Table (Node 7, Channel 0)
----------------------------------------------

 Rule 	Enable 	Limit(Ch Space) 	Ways
 0	1	256			2

	Rank Interleave List
	Way 	Target 	Offset
	0	0	0
	1	1	0
	2	0	0
	3	0	0
	4	0	0
	5	0	0
	6	0	0
	7	0	0

----------- Channel 1 
 Channel Enabled
 Channel mem size (64MB) = 256

 --------------------- RIR Info ------------------------------

 RIR Table (Node 7, Channel 1)
----------------------------------------------

 Rule 	Enable 	Limit(Ch Space) 	Ways
 0	1	256			2

	Rank Interleave List
	Way 	Target 	Offset
	0	0	0
	1	1	0
	2	0	0
	3	0	0
	4	0	0
	5	0	0
	6	0	0
	7	0	0

----------- Channel 2 
 Channel Enabled
 Channel mem size (64MB) = 256

 --------------------- RIR Info ------------------------------

 RIR Table (Node 7, Channel 2)
----------------------------------------------

 Rule 	Enable 	Limit(Ch Space) 	Ways
 0	1	256			2

	Rank Interleave List
	Way 	Target 	Offset
	0	0	0
	1	1	0
	2	0	0
	3	0	0
	4	0	0
	5	0	0
	6	0	0
	7	0	0

----------- Channel 3 
 Channel Enabled
 Channel mem size (64MB) = 256

 --------------------- RIR Info ------------------------------

 RIR Table (Node 7, Channel 3)
----------------------------------------------

 Rule 	Enable 	Limit(Ch Space) 	Ways
 0	1	256			2

	Rank Interleave List
	Way 	Target 	Offset
	0	0	0
	1	1	0
	2	0	0
	3	0	0
	4	0	0
	5	0	0
	6	0	0
	7	0	0

highMemBase: 0x40
highMemSize: 0x1FE0
TOLM (64MB): 0x1F
TOHM (64MB): 0x201F
Checkpoint Code: Socket 0, 0xBD, 0x00, 0x0000
Set RAS Config
N0: Independent channel mode enabled
N0: Patrol scrub enable moved to SMM Memras driver.  Not enabled in MRC in regular boot.
N0: Demand scrub enabled
N0: HA CrdtCnt configured, mc Read credits = 48, mc Write credits = 39
N0: Leaky bucket configured
N1: Independent channel mode enabled
N1: Patrol scrub enable moved to SMM Memras driver.  Not enabled in MRC in regular boot.
N1: Demand scrub enabled
N1: HA CrdtCnt configured, mc Read credits = 48, mc Write credits = 39
N1: Leaky bucket configured
N2: Independent channel mode enabled
N2: Patrol scrub enable moved to SMM Memras driver.  Not enabled in MRC in regular boot.
N2: Demand scrub enabled
N2: HA CrdtCnt configured, mc Read credits = 48, mc Write credits = 39
N2: Leaky bucket configured
N3: Independent channel mode enabled
N3: Patrol scrub enable moved to SMM Memras driver.  Not enabled in MRC in regular boot.
N3: Demand scrub enabled
N3: HA CrdtCnt configured, mc Read credits = 48, mc Write credits = 39
N3: Leaky bucket configured
N4: Independent channel mode enabled
N4: Patrol scrub enable moved to SMM Memras driver.  Not enabled in MRC in regular boot.
N4: Demand scrub enabled
N4: HA CrdtCnt configured, mc Read credits = 48, mc Write credits = 39
N4: Leaky bucket configured
N5: Independent channel mode enabled
N5: Patrol scrub enable moved to SMM Memras driver.  Not enabled in MRC in regular boot.
N5: Demand scrub enabled
N5: HA CrdtCnt configured, mc Read credits = 48, mc Write credits = 39
N5: Leaky bucket configured
N6: Independent channel mode enabled
N6: Patrol scrub enable moved to SMM Memras driver.  Not enabled in MRC in regular boot.
N6: Demand scrub enabled
N6: HA CrdtCnt configured, mc Read credits = 48, mc Write credits = 39
N6: Leaky bucket configured
N7: Independent channel mode enabled
N7: Patrol scrub enable moved to SMM Memras driver.  Not enabled in MRC in regular boot.
N7: Demand scrub enabled
N7: HA CrdtCnt configured, mc Read credits = 48, mc Write credits = 39
N7: Leaky bucket configured
ECC enabled
Socket0 IO_SA_CONFIG: tempData = 0x0
Socket1 IO_SA_CONFIG: tempData = 0x0
Socket2 IO_SA_CONFIG: tempData = 0x0
Socket3 IO_SA_CONFIG: tempData = 0x0
N0: Disabling SMB writes
N0: Ddr3CapErrPcodeWA : 
N0: 	 WRITE_PCU_MISC_CONFIG Reg- Write Value = 0x8840000
N1: Disabling SMB writes
N1: Ddr3CapErrPcodeWA : 
N1: 	 WRITE_PCU_MISC_CONFIG Reg- Write Value = 0x8840000
N2: Disabling SMB writes
N2: Ddr3CapErrPcodeWA : 
N2: 	 WRITE_PCU_MISC_CONFIG Reg- Write Value = 0x8840000
N3: Disabling SMB writes
N3: Ddr3CapErrPcodeWA : 
N3: 	 WRITE_PCU_MISC_CONFIG Reg- Write Value = 0x8840000
N4: Disabling SMB writes
N4: Ddr3CapErrPcodeWA : 
N4: 	 WRITE_PCU_MISC_CONFIG Reg- Write Value = 0x8840000
N5: Disabling SMB writes
N5: Ddr3CapErrPcodeWA : 
N5: 	 WRITE_PCU_MISC_CONFIG Reg- Write Value = 0x8840000
N6: Disabling SMB writes
N6: Ddr3CapErrPcodeWA : 
N6: 	 WRITE_PCU_MISC_CONFIG Reg- Write Value = 0x8840000
N7: Disabling SMB writes
N7: Ddr3CapErrPcodeWA : 
N7: 	 WRITE_PCU_MISC_CONFIG Reg- Write Value = 0x8840000

Total MRC latency = 477548 ms

START_DIMMINFO_TABLE

==============================================================================
START_NODE_0_TABLE
PROC Unknown Stepping
==============================================================================
S|    Channel 0     |    Channel 1     |    Channel 2     |    Channel 3     |
==============================================================================
0|      Samsung     |      Samsung     |      Samsung     |      Samsung     |
 |      Samsung     |      Samsung     |      Samsung     |      Samsung     |
 |       Inphi      |       Inphi      |       Inphi      |       Inphi      |
 |    8GB(2Gbx4)    |    8GB(2Gbx4)    |    8GB(2Gbx4)    |    8GB(2Gbx4)    |
 |   RDIMM R/C-E    |   RDIMM R/C-E    |   RDIMM R/C-E    |   RDIMM R/C-E    |
 |    1600 9-9-9    |    1600 9-9-9    |    1600 9-9-9    |    1600 9-9-9    |
 |     ww402012     |     ww162012     |     ww162012     |     ww412012     |
 |M393B1K70DH0-YK0  |M393B1K70DH0-YK0  |M393B1K70DH0-YK0  |M393B1K70DH0-YK0  |
 |                  |                  |                  |                  |
------------------------------------------------------------------------------
1|      Samsung     |      Samsung     |      Samsung     |      Samsung     |
 |      Samsung     |      Samsung     |      Samsung     |      Samsung     |
 |       Inphi      |       Inphi      |       Inphi      |       Inphi      |
 |    8GB(2Gbx4)    |    8GB(2Gbx4)    |    8GB(2Gbx4)    |    8GB(2Gbx4)    |
 |   RDIMM R/C-E    |   RDIMM R/C-E    |   RDIMM R/C-E    |   RDIMM R/C-E    |
 |    1600 9-9-9    |    1600 9-9-9    |    1600 9-9-9    |    1600 9-9-9    |
 |     ww412012     |     ww402012     |     ww402012     |     ww162012     |
 |M393B1K70DH0-YK0  |M393B1K70DH0-YK0  |M393B1K70DH0-YK0  |M393B1K70DH0-YK0  |
 |                  |                  |                  |                  |
------------------------------------------------------------------------------
2|  Not installed   |  Not installed   |  Not installed   |  Not installed   |
 |                  |                  |                  |                  |
 |                  |                  |                  |                  |
 |                  |                  |                  |                  |
 |                  |                  |                  |                  |
 |                  |                  |                  |                  |
 |                  |                  |                  |                  |
 |                  |                  |                  |                  |
 |                  |                  |                  |                  |
------------------------------------------------------------------------------
STOP_NODE_0_TABLE
======================================================================================

==============================================================================
START_NODE_1_TABLE
PROC Unknown Stepping
==============================================================================
S|    Channel 0     |    Channel 1     |    Channel 2     |    Channel 3     |
==============================================================================
0|      Samsung     |      Samsung     |      Samsung     |      Samsung     |
 |      Samsung     |      Samsung     |      Samsung     |      Samsung     |
 |        IDT       |        IDT       |        IDT       |        IDT       |
 |   16GB(4Gbx4)    |   16GB(4Gbx4)    |   16GB(4Gbx4)    |   16GB(4Gbx4)    |
 |   RDIMM R/C-E    |   RDIMM R/C-E    |   RDIMM R/C-E    |   RDIMM R/C-E    |
 |    1600 9-9-9    |    1600 9-9-9    |    1600 9-9-9    |    1600 9-9-9    |
 |     ww232013     |     ww232013     |     ww232013     |     ww232013     |
 |M393B2G70BH0-CK0  |M393B2G70BH0-CK0  |M393B2G70BH0-CK0  |M393B2G70BH0-CK0  |
 |                  |                  |                  |                  |
------------------------------------------------------------------------------
1|  Not installed   |  Not installed   |  Not installed   |  Not installed   |
 |                  |                  |                  |                  |
 |                  |                  |                  |                  |
 |                  |                  |                  |                  |
 |                  |                  |                  |                  |
 |                  |                  |                  |                  |
 |                  |                  |                  |                  |
 |                  |                  |                  |                  |
 |                  |                  |                  |                  |
------------------------------------------------------------------------------
2|  Not installed   |  Not installed   |  Not installed   |  Not installed   |
 |                  |                  |                  |                  |
 |                  |                  |                  |                  |
 |                  |                  |                  |                  |
 |                  |                  |                  |                  |
 |                  |                  |                  |                  |
 |                  |                  |                  |                  |
 |                  |                  |                  |                  |
 |                  |                  |                  |                  |
------------------------------------------------------------------------------
STOP_NODE_1_TABLE
======================================================================================

==============================================================================
START_NODE_2_TABLE
PROC Unknown Stepping
==============================================================================
S|    Channel 0     |    Channel 1     |    Channel 2     |    Channel 3     |
==============================================================================
0|      Samsung     |      Samsung     |      Samsung     |      Samsung     |
 |      Samsung     |      Samsung     |      Samsung     |      Samsung     |
 |       Inphi      |       Inphi      |       Inphi      |       Inphi      |
 |    8GB(2Gbx4)    |    8GB(2Gbx4)    |    8GB(2Gbx4)    |    8GB(2Gbx4)    |
 |   RDIMM R/C-E    |   RDIMM R/C-E    |   RDIMM R/C-E    |   RDIMM R/C-E    |
 |    1333 9-9-9    |    1333 9-9-9    |    1333 9-9-9    |    1333 9-9-9    |
 |     ww232011     |     ww232011     |     ww232011     |     ww232011     |
 |M393B1K70CH0-YH9  |M393B1K70CH0-YH9  |M393B1K70CH0-YH9  |M393B1K70CH0-YH9  |
 |                  |                  |                  |                  |
------------------------------------------------------------------------------
1|      Samsung     |      Samsung     |      Samsung     |      Samsung     |
 |      Samsung     |      Samsung     |      Samsung     |      Samsung     |
 |       Inphi      |       Inphi      |       Inphi      |       Inphi      |
 |    8GB(2Gbx4)    |    8GB(2Gbx4)    |    8GB(2Gbx4)    |    8GB(2Gbx4)    |
 |   RDIMM R/C-E    |   RDIMM R/C-E    |   RDIMM R/C-E    |   RDIMM R/C-E    |
 |    1333 9-9-9    |    1333 9-9-9    |    1333 9-9-9    |    1333 9-9-9    |
 |     ww232011     |     ww232011     |     ww232011     |     ww232011     |
 |M393B1K70CH0-YH9  |M393B1K70CH0-YH9  |M393B1K70CH0-YH9  |M393B1K70CH0-YH9  |
 |                  |                  |                  |                  |
------------------------------------------------------------------------------
2|  Not installed   |  Not installed   |  Not installed   |  Not installed   |
 |                  |                  |                  |                  |
 |                  |                  |                  |                  |
 |                  |                  |                  |                  |
 |                  |                  |                  |                  |
 |                  |                  |                  |                  |
 |                  |                  |                  |                  |
 |                  |                  |                  |                  |
 |                  |                  |                  |                  |
------------------------------------------------------------------------------
STOP_NODE_2_TABLE
======================================================================================

==============================================================================
START_NODE_3_TABLE
PROC Unknown Stepping
==============================================================================
S|    Channel 0     |    Channel 1     |    Channel 2     |    Channel 3     |
==============================================================================
0|      Samsung     |      Samsung     |      Samsung     |      Samsung     |
 |      Samsung     |      Samsung     |      Samsung     |      Samsung     |
 |        IDT       |        IDT       |        IDT       |        IDT       |
 |   16GB(4Gbx4)    |   16GB(4Gbx4)    |   16GB(4Gbx4)    |   16GB(4Gbx4)    |
 |   RDIMM R/C-E    |   RDIMM R/C-E    |   RDIMM R/C-E    |   RDIMM R/C-E    |
 |    1600 9-9-9    |    1600 9-9-9    |    1600 9-9-9    |    1600 9-9-9    |
 |     ww202013     |     ww202013     |     ww202013     |     ww202013     |
 |M393B2G70BH0-CK0  |M393B2G70BH0-CK0  |M393B2G70BH0-CK0  |M393B2G70BH0-CK0  |
 |                  |                  |                  |                  |
------------------------------------------------------------------------------
1|  Not installed   |  Not installed   |  Not installed   |  Not installed   |
 |                  |                  |                  |                  |
 |                  |                  |                  |                  |
 |                  |                  |                  |                  |
 |                  |                  |                  |                  |
 |                  |                  |                  |                  |
 |                  |                  |                  |                  |
 |                  |                  |                  |                  |
 |                  |                  |                  |                  |
------------------------------------------------------------------------------
2|  Not installed   |  Not installed   |  Not installed   |  Not installed   |
 |                  |                  |                  |                  |
 |                  |                  |                  |                  |
 |                  |                  |                  |                  |
 |                  |                  |                  |                  |
 |                  |                  |                  |                  |
 |                  |                  |                  |                  |
 |                  |                  |                  |                  |
 |                  |                  |                  |                  |
------------------------------------------------------------------------------
STOP_NODE_3_TABLE
======================================================================================

==============================================================================
START_NODE_4_TABLE
PROC Unknown Stepping
==============================================================================
S|    Channel 0     |    Channel 1     |    Channel 2     |    Channel 3     |
==============================================================================
0|      Samsung     |      Samsung     |      Samsung     |      Samsung     |
 |      Samsung     |      Samsung     |      Samsung     |      Samsung     |
 |       Inphi      |       Inphi      |       Inphi      |       Inphi      |
 |    8GB(2Gbx4)    |    8GB(2Gbx4)    |    8GB(2Gbx4)    |    8GB(2Gbx4)    |
 |   RDIMM R/C-E    |   RDIMM R/C-E    |   RDIMM R/C-E    |   RDIMM R/C-E    |
 |    1600 9-9-9    |    1600 9-9-9    |    1600 9-9-9    |    1600 9-9-9    |
 |     ww402012     |     ww402012     |     ww402012     |     ww162012     |
 |M393B1K70DH0-YK0  |M393B1K70DH0-YK0  |M393B1K70DH0-YK0  |M393B1K70DH0-YK0  |
 |                  |                  |                  |                  |
------------------------------------------------------------------------------
1|      Samsung     |      Samsung     |      Samsung     |      Samsung     |
 |      Samsung     |      Samsung     |      Samsung     |      Samsung     |
 |       Inphi      |       Inphi      |       Inphi      |       Inphi      |
 |    8GB(2Gbx4)    |    8GB(2Gbx4)    |    8GB(2Gbx4)    |    8GB(2Gbx4)    |
 |   RDIMM R/C-E    |   RDIMM R/C-E    |   RDIMM R/C-E    |   RDIMM R/C-E    |
 |    1600 9-9-9    |    1600 9-9-9    |    1600 9-9-9    |    1600 9-9-9    |
 |     ww402012     |     ww162012     |     ww402012     |     ww162012     |
 |M393B1K70DH0-YK0  |M393B1K70DH0-YK0  |M393B1K70DH0-YK0  |M393B1K70DH0-YK0  |
 |                  |                  |                  |                  |
------------------------------------------------------------------------------
2|  Not installed   |  Not installed   |  Not installed   |  Not installed   |
 |                  |                  |                  |                  |
 |                  |                  |                  |                  |
 |                  |                  |                  |                  |
 |                  |                  |                  |                  |
 |                  |                  |                  |                  |
 |                  |                  |                  |                  |
 |                  |                  |                  |                  |
 |                  |                  |                  |                  |
------------------------------------------------------------------------------
STOP_NODE_4_TABLE
======================================================================================

==============================================================================
START_NODE_5_TABLE
PROC Unknown Stepping
==============================================================================
S|    Channel 0     |    Channel 1     |    Channel 2     |    Channel 3     |
==============================================================================
0|      Samsung     |      Samsung     |      Samsung     |      Samsung     |
 |      Samsung     |      Samsung     |      Samsung     |      Samsung     |
 |        IDT       |        IDT       |        IDT       |        IDT       |
 |   16GB(4Gbx4)    |   16GB(4Gbx4)    |   16GB(4Gbx4)    |   16GB(4Gbx4)    |
 |   RDIMM R/C-E    |   RDIMM R/C-E    |   RDIMM R/C-E    |   RDIMM R/C-E    |
 |    1600 9-9-9    |    1600 9-9-9    |    1600 9-9-9    |    1600 9-9-9    |
 |     ww222013     |     ww222013     |     ww222013     |     ww232013     |
 |M393B2G70BH0-CK0  |M393B2G70BH0-CK0  |M393B2G70BH0-CK0  |M393B2G70BH0-CK0  |
 |                  |                  |                  |                  |
------------------------------------------------------------------------------
1|  Not installed   |  Not installed   |  Not installed   |  Not installed   |
 |                  |                  |                  |                  |
 |                  |                  |                  |                  |
 |                  |                  |                  |                  |
 |                  |                  |                  |                  |
 |                  |                  |                  |                  |
 |                  |                  |                  |                  |
 |                  |                  |                  |                  |
 |                  |                  |                  |                  |
------------------------------------------------------------------------------
2|  Not installed   |  Not installed   |  Not installed   |  Not installed   |
 |                  |                  |                  |                  |
 |                  |                  |                  |                  |
 |                  |                  |                  |                  |
 |                  |                  |                  |                  |
 |                  |                  |                  |                  |
 |                  |                  |                  |                  |
 |                  |                  |                  |                  |
 |                  |                  |                  |                  |
------------------------------------------------------------------------------
STOP_NODE_5_TABLE
======================================================================================

==============================================================================
START_NODE_6_TABLE
PROC Unknown Stepping
==============================================================================
S|    Channel 0     |    Channel 1     |    Channel 2     |    Channel 3     |
==============================================================================
0|      Samsung     |      Samsung     |      Samsung     |      Samsung     |
 |      Samsung     |      Samsung     |      Samsung     |      Samsung     |
 |       Inphi      |       Inphi      |       Inphi      |       Inphi      |
 |    8GB(2Gbx4)    |    8GB(2Gbx4)    |    8GB(2Gbx4)    |    8GB(2Gbx4)    |
 |   RDIMM R/C-E    |   RDIMM R/C-E    |   RDIMM R/C-E    |   RDIMM R/C-E    |
 |    1333 9-9-9    |    1333 9-9-9    |    1333 9-9-9    |    1333 9-9-9    |
 |     ww232011     |     ww232011     |     ww232011     |     ww232011     |
 |M393B1K70CH0-YH9  |M393B1K70CH0-YH9  |M393B1K70CH0-YH9  |M393B1K70CH0-YH9  |
 |                  |                  |                  |                  |
------------------------------------------------------------------------------
1|      Samsung     |      Samsung     |      Samsung     |      Samsung     |
 |      Samsung     |      Samsung     |      Samsung     |      Samsung     |
 |       Inphi      |       Inphi      |       Inphi      |       Inphi      |
 |    8GB(2Gbx4)    |    8GB(2Gbx4)    |    8GB(2Gbx4)    |    8GB(2Gbx4)    |
 |   RDIMM R/C-E    |   RDIMM R/C-E    |   RDIMM R/C-E    |   RDIMM R/C-E    |
 |    1333 9-9-9    |    1333 9-9-9    |    1333 9-9-9    |    1333 9-9-9    |
 |     ww232011     |     ww232011     |     ww232011     |     ww232011     |
 |M393B1K70CH0-YH9  |M393B1K70CH0-YH9  |M393B1K70CH0-YH9  |M393B1K70CH0-YH9  |
 |                  |                  |                  |                  |
------------------------------------------------------------------------------
2|  Not installed   |  Not installed   |  Not installed   |  Not installed   |
 |                  |                  |                  |                  |
 |                  |                  |                  |                  |
 |                  |                  |                  |                  |
 |                  |                  |                  |                  |
 |                  |                  |                  |                  |
 |                  |                  |                  |                  |
 |                  |                  |                  |                  |
 |                  |                  |                  |                  |
------------------------------------------------------------------------------
STOP_NODE_6_TABLE
======================================================================================

==============================================================================
START_NODE_7_TABLE
PROC Unknown Stepping
==============================================================================
S|    Channel 0     |    Channel 1     |    Channel 2     |    Channel 3     |
==============================================================================
0|      Samsung     |      Samsung     |      Samsung     |      Samsung     |
 |      Samsung     |      Samsung     |      Samsung     |      Samsung     |
 |        IDT       |        IDT       |        IDT       |        IDT       |
 |   16GB(4Gbx4)    |   16GB(4Gbx4)    |   16GB(4Gbx4)    |   16GB(4Gbx4)    |
 |   RDIMM R/C-E    |   RDIMM R/C-E    |   RDIMM R/C-E    |   RDIMM R/C-E    |
 |    1600 9-9-9    |    1600 9-9-9    |    1600 9-9-9    |    1600 9-9-9    |
 |     ww202013     |     ww232013     |     ww232013     |     ww232013     |
 |M393B2G70BH0-CK0  |M393B2G70BH0-CK0  |M393B2G70BH0-CK0  |M393B2G70BH0-CK0  |
 |                  |                  |                  |                  |
------------------------------------------------------------------------------
1|  Not installed   |  Not installed   |  Not installed   |  Not installed   |
 |                  |                  |                  |                  |
 |                  |                  |                  |                  |
 |                  |                  |                  |                  |
 |                  |                  |                  |                  |
 |                  |                  |                  |                  |
 |                  |                  |                  |                  |
 |                  |                  |                  |                  |
 |                  |                  |                  |                  |
------------------------------------------------------------------------------
2|  Not installed   |  Not installed   |  Not installed   |  Not installed   |
 |                  |                  |                  |                  |
 |                  |                  |                  |                  |
 |                  |                  |                  |                  |
 |                  |                  |                  |                  |
 |                  |                  |                  |                  |
 |                  |                  |                  |                  |
 |                  |                  |                  |                  |
 |                  |                  |                  |                  |
------------------------------------------------------------------------------
STOP_NODE_7_TABLE
======================================================================================
==========================================================================================================================================
                    |    MC 0    |    MC 1    |    MC 2    |    MC 3    |    MC 4    |    MC 5    |    MC 6    |    MC 7    |   System   |
==========================================================================================================================================
Active Memory       |     64GB   |     64GB   |     64GB   |     64GB   |     64GB   |     64GB   |     64GB   |     64GB   |    512GB   |
DDR3 Freq           |            |            |            |            |            |            |            |            |  DDR3-1333 |
Ch0 CL-RCD-RP-CMD   | 9-9-9-1n   | 9-9-9-1n   | 9-9-9-1n   | 9-9-9-1n   | 9-9-9-1n   | 9-9-9-1n   | 9-9-9-1n   | 9-9-9-1n   |            |
Ch1 CL-RCD-RP-CMD   | 9-9-9-1n   | 9-9-9-1n   | 9-9-9-1n   | 9-9-9-1n   | 9-9-9-1n   | 9-9-9-1n   | 9-9-9-1n   | 9-9-9-1n   |            |
Ch2 CL-RCD-RP-CMD   | 9-9-9-1n   | 9-9-9-1n   | 9-9-9-1n   | 9-9-9-1n   | 9-9-9-1n   | 9-9-9-1n   | 9-9-9-1n   | 9-9-9-1n   |            |
Ch3 CL-RCD-RP-CMD   | 9-9-9-1n   | 9-9-9-1n   | 9-9-9-1n   | 9-9-9-1n   | 9-9-9-1n   | 9-9-9-1n   | 9-9-9-1n   | 9-9-9-1n   |            |
DDR3 Vdd            |            |            |            |            |            |            |            |            |    1.50v    |
ECC Checking        |            |            |            |            |            |            |            |            |     On     |
Patrol/Demand Scrub |            |            |            |            |            |            |            |            | Off /  On  |
RAS Mode            |            |            |            |            |            |            |            |            |   Indep    |
Paging Policy       |            |            |            |            |            |            |            |            |   Closed   |
==========================================================================================================================================

STOP_DIMMINFO_TABLE
Checkpoint Code: Socket 0, 0xBF, 0x00, 0x0000
MRC is done!
Save NVRAM restore data into Hob
MrcSaveS3RestoreDataToHob
Install EFI Memory
InstallEfiMemory()
MRC: lowMemBase:0 lowMemSize:20
MRC: highMemBase:40 highMemSize:1FE0
MRC: TSEG BlockNum:512
Reserve LT Mem[0x7B800000] Size = 0x00000000
PEI_MIN_MEMORY_SIZE:319488KB 
IndexNumber:10 MemoryDataNumber10 
Index[0].Type = 4 .NumberOfPages=0x4E61
Index[1].Type = 9 .NumberOfPages=0x100
Index[2].Type = 10 .NumberOfPages=0x227C
Index[3].Type = 0 .NumberOfPages=0x8F4
Index[4].Type = 5 .NumberOfPages=0x8D
Index[5].Type = 6 .NumberOfPages=0xB4
Index[6].Type = 3 .NumberOfPages=0x693
Index[7].Type = 1 .NumberOfPages=0xEC
Index[8].Type = 2 .NumberOfPages=0x5F
Index[9].Type = 14 .NumberOfPages=0x0
has memory type,  Total platform memory:454592KB 
 RequiredMemSize = 0x83F4000 bytes
Found 0x00000000000A0000 bytes at 0x0000000000000000
Found 0x0000000000060000 bytes at 0x00000000000A0000
Found 0x000000007B700000 bytes at 0x0000000000100000
Found 0x0000000003C00000 bytes at 0x000000007C000000
Found 0x0000000000400000 bytes at 0x000000007FC00000
Found 0x0000000000800000 bytes at 0x000000007B800000
PeiInstallPeiMemory MemoryBegin 0x5FC10000, MemoryLength 0x137FC000
Building RESOURCE_SYSTEM_MEMORY Hob:
 PeiMemoryBaseAddress = 0x5FC10000, PeiMemoryLength = 0x1BBF0000
Untested Main Memory range Base:0x0 Length:0xA0000
Partially tested Main Memory Base:0x100000 Length:0x5FB10000
TOHM:0x0000007F80000000
 MRC Returned Success. Memory Init Complete.
STOP_MRC_RUN
Reset Requested: 0
Pipe Exit starting...Pipe Exit completed! Reset Requested: 0
Checking for Reset Requests ...  None 
Continue with system BIOS POST ...

mmCfgBase  80000000
QPI: IIO[0] busbase = 0 Limit=3F
QPI: IIO[0] IoBase = 0 IoLimit=3FFF
QPI: IIO[0] Mem32Base = 90000000 Mem32Limit=ABFFFFFF
QPI: IIO[0] VtdBarAddress = ABFFC000 RcbaAddress=ABFFE000
PCI: IIO[0] NEW!PciResourceMem32Limit=ABFFBFFF
QPI: CPU[0] bus = 3F
QPI: IIO[0] bus = 0
QPI: IIO[0] IoApicBase = FEC00000 IoApicLimit=FEC3FFFF
QPI: IIO[1] busbase = 40 Limit=7F
QPI: IIO[1] IoBase = 4000 IoLimit=7FFF
QPI: IIO[1] Mem32Base = AC000000 Mem32Limit=C7FFFFFF
QPI: IIO[1] VtdBarAddress = C7FFC000 RcbaAddress=C7FFE000
PCI: IIO[1] NEW!PciResourceMem32Limit=C7FFBFFF
QPI: CPU[1] bus = 7F
QPI: IIO[1] bus = 40
QPI: IIO[1] IoApicBase = FEC40000 IoApicLimit=FEC7FFFF
QPI: IIO[2] busbase = 80 Limit=BF
QPI: IIO[2] IoBase = 8000 IoLimit=BFFF
QPI: IIO[2] Mem32Base = C8000000 Mem32Limit=E3FFFFFF
QPI: IIO[2] VtdBarAddress = E3FFC000 RcbaAddress=E3FFE000
PCI: IIO[2] NEW!PciResourceMem32Limit=E3FFBFFF
QPI: CPU[2] bus = BF
QPI: IIO[2] bus = 80
QPI: IIO[2] IoApicBase = FEC80000 IoApicLimit=FECBFFFF
QPI: IIO[3] busbase = C0 Limit=FF
QPI: IIO[3] IoBase = C000 IoLimit=FFFF
QPI: IIO[3] Mem32Base = E4000000 Mem32Limit=FBFFFFFF
QPI: IIO[3] VtdBarAddress = FBFFC000 RcbaAddress=FBFFE000
PCI: IIO[3] NEW!PciResourceMem32Limit=FBFFBFFF
QPI: CPU[3] bus = FF
QPI: IIO[3] bus = C0
QPI: IIO[3] IoApicBase = FECC0000 IoApicLimit=FECFFFFF
QPI: num of Cpus = 4
QPI: num of IIOs = 4
Var LtEnable = 0
Node:0 BaseAddress:00000000 ElementSize:00000020
Node:0 BaseAddress:00000040 ElementSize:000007E0
Node:2 BaseAddress:00000820 ElementSize:00000800
Node:4 BaseAddress:00001020 ElementSize:00000800
Node:6 BaseAddress:00001820 ElementSize:00000800
Scalable Memory Buffer Device List.
  Node-0, Chan-0 revid=5
  Node-0, Chan-2 revid=5
Scalable Memory Buffer Device List.
  Node-1, Chan-0 revid=5
  Node-1, Chan-2 revid=5
Scalable Memory Buffer Device List.
  Node-2, Chan-0 revid=5
  Node-2, Chan-2 revid=5
Scalable Memory Buffer Device List.
  Node-3, Chan-0 revid=5
  Node-3, Chan-2 revid=5
Scalable Memory Buffer Device List.
  Node-4, Chan-0 revid=5
  Node-4, Chan-2 revid=5
Scalable Memory Buffer Device List.
  Node-5, Chan-0 revid=5
  Node-5, Chan-2 revid=5
Scalable Memory Buffer Device List.
  Node-6, Chan-0 revid=5
  Node-6, Chan-2 revid=5
Scalable Memory Buffer Device List.
  Node-7, Chan-0 revid=5
  Node-7, Chan-2 revid=5
PrevBootErrLog - Num Valid Entries: 0
Temp Stack : BaseAddress=0xFE180000 Length=0x80000
Temp Heap  : BaseAddress=0xFE100000 Length=0x13DA0
Total temporary memory:    1048576 bytes.
  temporary memory stack ever used: 503272 bytes.
  temporary memory heap used:       81312 bytes.
Old Stack size 524288, New stack size 524288
Heap Offset = 0x9E470000 Stack Offset = 0x9E570000
Stack Hob: BaseAddress=0x5FC10000 Length=0x80000
Loading PEIM at 0x00073403000 EntryPoint=0x00073404D70 
Reinstall PPI: 8C8CE578-8A3D-4F1C-9935-896185C32DD3
Reinstall PPI: 5473C07A-3DCB-4DCA-BD6F-1E9689E7349A
Reinstall PPI: B9E0ABFE-5979-4914-977F-6DEE78C278A6
Install PPI: F894643D-C449-42D1-8EA8-85BDD8C65BDE
Notify: PPI Guid: F894643D-C449-42D1-8EA8-85BDD8C65BDE, Peim notify entry point: FFFDD8F7
PchSataInit() - Start
IOBP polling for busy bit.
IOBP polling for busy bit.
IOBP polling for busy bit after transaction.
IOBP polling for busy bit after transaction.
IOBP polling for busy bit.
IOBP polling for busy bit.
IOBP polling for busy bit after transaction.
IOBP polling for busy bit after transaction.
PchSataInit() - End
Notify: PPI Guid: F894643D-C449-42D1-8EA8-85BDD8C65BDE, Peim notify entry point: FFFC3A17
Memory Length (below 4GB) = 7B800000.
Power Of Two Memory Length (below 4GB) = 80000000.
Memory Length (above 4GB) = 7F80000000.
Power Of Two Memory Length (above 4GB) = 8000000000.
=======================
 Boot in Normal mode
=======================
Install PPI: 49EDB1C1-BF21-4761-BB12-EB0031AABB39
Notify: PPI Guid: 49EDB1C1-BF21-4761-BB12-EB0031AABB39, Peim notify entry point: FFFCAEB8
The 2th FV start address is 0x000FF800000, size is 0x00480000, handle is 0xFF800000
Found firmware volume Image File FF800078 in FV[2] FF800000
CpuAddressWidth: 46
Notify: PPI Guid: F894643D-C449-42D1-8EA8-85BDD8C65BDE, Peim notify entry point: FFFD6CB6
Notify: PPI Guid: F894643D-C449-42D1-8EA8-85BDD8C65BDE, Peim notify entry point: FFFE5D3F
IioUds->SystemStatus.IsocEnable = 0
PchDmiGen2Prog() Start
PchDmiGen2Prog() End
Notify: PPI Guid: F894643D-C449-42D1-8EA8-85BDD8C65BDE, Peim notify entry point: FFD5F219
Loading PEIM at 0x00073401000 EntryPoint=0x00073401940 
CpuIO PPI has been loaded into memory.  Reinstalled PPI=0x73401270
Install PPI: 49EDB1C1-BF21-4761-BB12-EB0031AABB39
Notify: PPI Guid: 49EDB1C1-BF21-4761-BB12-EB0031AABB39, Peim notify entry point: FFFCAEB8
The 3th FV start address is 0x000FFD00000, size is 0x00020000, handle is 0xFFD00000
Install PPI: 49EDB1C1-BF21-4761-BB12-EB0031AABB39
Notify: PPI Guid: 49EDB1C1-BF21-4761-BB12-EB0031AABB39, Peim notify entry point: FFFCAEB8
The 4th FV start address is 0x000FFC80000, size is 0x00030000, handle is 0xFFC80000
Install PPI: 49EDB1C1-BF21-4761-BB12-EB0031AABB39
Notify: PPI Guid: 49EDB1C1-BF21-4761-BB12-EB0031AABB39, Peim notify entry point: FFFCAEB8
The 5th FV start address is 0x000FFCB0000, size is 0x00040000, handle is 0xFFCB0000
Loading PEIM at 0x000733FE000 EntryPoint=0x000733FEBB8 
Install PPI: E9DB0D58-D48D-47F6-9C6E-6F40E86C7B41
Register PPI Notify: EF9AEFE5-2BD3-4031-AF7D-5EFE5ABB9A0D
Register PPI Notify: 49EDB1C1-BF21-4761-BB12-EB0031AABB39
Register PPI Notify: 605EA650-C65C-42E1-BA80-91A52AB618C6
Notify: PPI Guid: 49EDB1C1-BF21-4761-BB12-EB0031AABB39, Peim notify entry point: 733FEF5F
The FV which is measured by TcgPei starts at: 0xFFD50000
The FV which is measured by TcgPei has the size: 0x100000
Notify: PPI Guid: 49EDB1C1-BF21-4761-BB12-EB0031AABB39, Peim notify entry point: 733FEF5F
The FV which is measured by TcgPei starts at: 0xFF800000
The FV which is measured by TcgPei has the size: 0x480000
Notify: PPI Guid: 49EDB1C1-BF21-4761-BB12-EB0031AABB39, Peim notify entry point: 733FEF5F
The FV which is measured by TcgPei starts at: 0xFFD00000
The FV which is measured by TcgPei has the size: 0x20000
Notify: PPI Guid: 49EDB1C1-BF21-4761-BB12-EB0031AABB39, Peim notify entry point: 733FEF5F
The FV which is measured by TcgPei starts at: 0xFFC80000
The FV which is measured by TcgPei has the size: 0x30000
Notify: PPI Guid: 49EDB1C1-BF21-4761-BB12-EB0031AABB39, Peim notify entry point: 733FEF5F
The FV which is measured by TcgPei starts at: 0xFFCB0000
The FV which is measured by TcgPei has the size: 0x40000
Loading PEIM at 0x000733F8000 EntryPoint=0x000733F9330 
Install PPI: EE4E5898-3914-4259-9D6E-DC7BD79403CF
Install PPI: A31280AD-481E-41B6-95E8-127F4C984779
Install PPI: 0AE8CE5D-E448-4437-A8D7-EBF5F194F731
Install PPI: 1A36E4E7-FAB6-476A-8E75-695A0576FDD7
Loading PEIM at 0x000733F7000 EntryPoint=0x000733F7788 
Install PPI: EF9AEFE5-2BD3-4031-AF7D-5EFE5ABB9A0D
Notify: PPI Guid: EF9AEFE5-2BD3-4031-AF7D-5EFE5ABB9A0D, Peim notify entry point: 733FEFF8
Customized Guided section Memory Size required is 0xD90010 and address is 0x72655000
Install PPI: 49EDB1C1-BF21-4761-BB12-EB0031AABB39
Notify: PPI Guid: 49EDB1C1-BF21-4761-BB12-EB0031AABB39, Peim notify entry point: FFFCAEB8
The 6th FV start address is 0x000718C4000, size is 0x00D90000, handle is 0x718C4000
Notify: PPI Guid: 49EDB1C1-BF21-4761-BB12-EB0031AABB39, Peim notify entry point: 733FEF5F
DXE IPL Entry
Loading PEIM at 0x000718A7000 EntryPoint=0x000718AC140 
Loading DXE CORE at 0x000718A7000 EntryPoint=0x000718AC140
Install PPI: 605EA650-C65C-42E1-BA80-91A52AB618C6
Notify: PPI Guid: 605EA650-C65C-42E1-BA80-91A52AB618C6, Peim notify entry point: FFFC38F1
Memory TOLM: 80000000
PCIE   BASE: 80000000     Size : 10000000
PCI32  BASE: 90000000     Limit: ABFFFFFF
PCI64  BASE: 380000000000     Limit: 387FFFFFFFFF
UC    START: 380000000000     End  : 388000000000
Notify: PPI Guid: 605EA650-C65C-42E1-BA80-91A52AB618C6, Peim notify entry point: FFD5D7B0
[SPS] Sending ME-BIOS Interface Version request
[HECI] Send msg: 80010020
[HECI]  Got msg: 80050020
[SPS] SPS ME-BIOS interface version is 1.2
      Feature set is 0x0006
[SPS] HOB: features 0x06, flow 1, boot mode 0, cores to disable 0
Notify: PPI Guid: 605EA650-C65C-42E1-BA80-91A52AB618C6, Peim notify entry point: 733FEBD0
InstallProtocolInterface: 5B1B31A1-9562-11D2-8E3F-00A0C969723B 718A8118
InstallProtocolInterface: 5CB5C776-60D5-45EE-883C-452708CD743F 718A80E0
HOBLIST address in DXE = 0x7B7E7018
Memory Allocation 0x00000004 0x71887000 - 0x718A6FFF
Memory Allocation 0x00000004 0x7340B000 - 0x7340BFFF
Memory Allocation 0x00000004 0x73403000 - 0x7340AFFF
Memory Allocation 0x00000004 0x73401000 - 0x73402FFF
Memory Allocation 0x00000004 0x733FE000 - 0x73400FFF
Memory Allocation 0x00000004 0x733F8000 - 0x733FDFFF
Memory Allocation 0x00000004 0x733F7000 - 0x733F7FFF
Memory Allocation 0x00000004 0x733E7000 - 0x733F6FFF
Memory Allocation 0x00000004 0x72655000 - 0x733E6FFF
Memory Allocation 0x00000004 0x718C4000 - 0x72654FFF
Memory Allocation 0x00000004 0x718A7000 - 0x718C3FFF
Memory Allocation 0x00000003 0x718A7000 - 0x718C3FFF
Memory Allocation 0x00000004 0x71887000 - 0x718A6FFF
Memory Allocation 0x00000004 0x61806000 - 0x71886FFF
Memory Allocation 0x00000004 0x5FC10000 - 0x5FC8FFFF
Memory Allocation 0x00000004 0x61805000 - 0x61805FFF
FV Hob            0xFFD00000 - 0xFFD1FFFF
FV Hob            0xFFC80000 - 0xFFCAFFFF
FV Hob            0xFFCB0000 - 0xFFCEFFFF
FV Hob            0x718C4000 - 0x72653FFF
FV2 Hob           0x718C4000 - 0x72653FFF
InstallProtocolInterface: D8117CFE-94A6-11D4-9A3A-0090273FC14D 718A8600
InstallProtocolInterface: 8F644FA9-E850-4DB1-9CE2-0B44698E8DA4 7B7E3D30
InstallProtocolInterface: 09576E91-6D3F-11D2-8E39-00A0C969723B 7B7E4398
InstallProtocolInterface: 8F644FA9-E850-4DB1-9CE2-0B44698E8DA4 7B7E3C30
InstallProtocolInterface: 09576E91-6D3F-11D2-8E39-00A0C969723B 7B7E4018
InstallProtocolInterface: 8F644FA9-E850-4DB1-9CE2-0B44698E8DA4 7B7E3B30
InstallProtocolInterface: 09576E91-6D3F-11D2-8E39-00A0C969723B 7B7E2D18
InstallProtocolInterface: 8F644FA9-E850-4DB1-9CE2-0B44698E8DA4 7B7E3A30
InstallProtocolInterface: 09576E91-6D3F-11D2-8E39-00A0C969723B 7B7E2A98
InstallProtocolInterface: 220E73B6-6BDB-4413-8405-B974B108619A 7B7E3830
InstallProtocolInterface: 220E73B6-6BDB-4413-8405-B974B108619A 7B7E3730
InstallProtocolInterface: 220E73B6-6BDB-4413-8405-B974B108619A 7B7E3630
InstallProtocolInterface: 220E73B6-6BDB-4413-8405-B974B108619A 7B7E3530
InstallProtocolInterface: FC1BCDB0-7D31-49AA-936A-A4600D9DD083 718A76F8
InstallProtocolInterface: A31280AD-481E-41B6-95E8-127F4C984779 718A76F8
Loading driver 80CF7257-87AB-47F9-A3FE-D50B76D89541
InstallProtocolInterface: 5B1B31A1-9562-11D2-8E3F-00A0C969723B 7B7E1E40
Loading driver at 0x00073BE8000 EntryPoint=0x00073BE93C0 
InstallProtocolInterface: BC62157E-3E33-4FEC-9920-2D3B36D750DF 7A565C98
InstallProtocolInterface: 11B34006-D85B-4D0A-A290-D5A571310EF7 73BE8330
InstallProtocolInterface: 13A3F0F6-264A-3EF0-F2E0-DEC512342F34 73BE8430
Loading driver D93CE3D8-A7EB-4730-8C8E-CC466A9ECC3C
InstallProtocolInterface: 5B1B31A1-9562-11D2-8E3F-00A0C969723B 7A54AE40
Loading driver at 0x00073D2B000 EntryPoint=0x00073D2BD80 
InstallProtocolInterface: BC62157E-3E33-4FEC-9920-2D3B36D750DF 7A565598
InstallProtocolInterface: 86212936-0E76-41C8-A03A-2AF2FC1C39E2 73D2B328
InstallProtocolInterface: D2B2B828-0826-48A7-B3DF-983C006024F0 73D2B320
Loading driver 801ADCA0-815E-46A4-84F7-657F53621A57
InstallProtocolInterface: 5B1B31A1-9562-11D2-8E3F-00A0C969723B 7A3F1E40
Loading driver at 0x00073BE5000 EntryPoint=0x00073BE5D70 
InstallProtocolInterface: BC62157E-3E33-4FEC-9920-2D3B36D750DF 7A3F0F18
InstallProtocolInterface: 448F5DA4-6DD7-4FE1-9307-69224192215D 73BE52E0
Loading driver 2E6A521C-F697-402D-9774-98B2B7E140F3
InstallProtocolInterface: 5B1B31A1-9562-11D2-8E3F-00A0C969723B 7A3F1C40
Loading driver at 0x00073BE2000 EntryPoint=0x00073BE2EA0 
InstallProtocolInterface: BC62157E-3E33-4FEC-9920-2D3B36D750DF 7A3F0998
InstallProtocolInterface: A7CED760-C71C-4E1A-ACB1-89604D5216CB 73BE4610
InstallProtocolInterface: A47BCED5-5DBF-43B9-AF78-43C5B23A0FB0 0
Loading driver BAE7599F-3C6B-43B7-BDF0-9CE07AA91AA6
InstallProtocolInterface: 5B1B31A1-9562-11D2-8E3F-00A0C969723B 7A3F1A40
Loading driver at 0x00073D28000 EntryPoint=0x00073D28A90 
InstallProtocolInterface: BC62157E-3E33-4FEC-9920-2D3B36D750DF 7A3F0218
InstallProtocolInterface: B0732526-38C8-4B40-8877-61C7B06AAC45 73D282E0
Loading driver A19B1FE7-C1BC-49F8-875F-54A5D542443F
InstallProtocolInterface: 5B1B31A1-9562-11D2-8E3F-00A0C969723B 7A3F1840
Loading driver at 0x00073BE0000 EntryPoint=0x00073BE09A0 
InstallProtocolInterface: BC62157E-3E33-4FEC-9920-2D3B36D750DF 7A3EBC98
InstallProtocolInterface: AD61F191-AE5F-4C0E-B9FA-E869D288C64F 73BE02E0
Loading driver 348C4D62-BFBD-4882-9ECE-C80BB1C4783B
InstallProtocolInterface: 5B1B31A1-9562-11D2-8E3F-00A0C969723B 7A3F1640
Loading driver at 0x00073BC9000 EntryPoint=0x00073BCB930 
InstallProtocolInterface: BC62157E-3E33-4FEC-9920-2D3B36D750DF 7A3EB718
InstallProtocolInterface: E9CA4775-8657-47FC-97E7-7ED65A084324 73BC93E8
InstallProtocolInterface: 0FD96974-23AA-4CDC-B9CB-98D17750322A 73BC9430
InstallProtocolInterface: EF9FC172-A1B2-4693-B327-6D32FC416042 73BC9458
InstallProtocolInterface: 587E72D7-CC50-4F79-8209-CA291FC1A10F 73BC94B0
InstallProtocolInterface: 31A6406A-6BDF-4E46-B2A2-EBAA89C40920 73BC9408
Loading driver 53BCC14F-C24F-434C-B294-8ED2D4CC1860
InstallProtocolInterface: 5B1B31A1-9562-11D2-8E3F-00A0C969723B 7A3F1440
Loading driver at 0x00073BC6000 EntryPoint=0x00073BC6C00 
InstallProtocolInterface: BC62157E-3E33-4FEC-9920-2D3B36D750DF 7A3E7D98
InstallProtocolInterface: AE80D021-618E-11D4-BCD7-0080C73C8881 73BC81D0
Loading driver 79CA4208-BBA1-4A9A-8456-E1E66A81484E
InstallProtocolInterface: 5B1B31A1-9562-11D2-8E3F-00A0C969723B 7A3F1240
Loading driver at 0x00073BC4000 EntryPoint=0x00073BC47D0 
InstallProtocolInterface: BC62157E-3E33-4FEC-9920-2D3B36D750DF 7A3E7818
InstallProtocolInterface: 38321DBA-4FE0-4E17-8AEC-413055EAEDC1 73BC42F0
Loading driver C8339973-A563-4561-B858-D8476F9DEFC4
InstallProtocolInterface: 5B1B31A1-9562-11D2-8E3F-00A0C969723B 7A3F1040
Loading driver at 0x00073BC2000 EntryPoint=0x00073BC2880 
InstallProtocolInterface: BC62157E-3E33-4FEC-9920-2D3B36D750DF 7A3E7298
InstallProtocolInterface: 26BACCB2-6F42-11D4-BCE7-0080C73C8881 73BC22C0
Loading driver B601F8C4-43B7-4784-95B1-F4226CB40CEE
InstallProtocolInterface: 5B1B31A1-9562-11D2-8E3F-00A0C969723B 7A3EAE40
Loading driver at 0x00073D25000 EntryPoint=0x00073D25A50 
InstallProtocolInterface: BC62157E-3E33-4FEC-9920-2D3B36D750DF 7A3E6D98
InstallProtocolInterface: B7DFB4E1-052F-449F-87BE-9818FC91B733 73D25310
Loading driver 4143C17D-54BC-4903-9958-2454216BB21E
InstallProtocolInterface: 5B1B31A1-9562-11D2-8E3F-00A0C969723B 7A3EAC40
Loading driver at 0x00073BC0000 EntryPoint=0x00073BC0970 
InstallProtocolInterface: BC62157E-3E33-4FEC-9920-2D3B36D750DF 7A3E6898
InstallProtocolInterface: 64021DFE-A62C-42A7-BF46-15078CDF9F89 73BC1710
Loading driver FDDC2E1E-33A9-40A6-A232-21D64B3622E8
InstallProtocolInterface: 5B1B31A1-9562-11D2-8E3F-00A0C969723B 7A3EAA40
Loading driver at 0x00073BBD000 EntryPoint=0x00073BBDC00 
InstallProtocolInterface: BC62157E-3E33-4FEC-9920-2D3B36D750DF 7A3E6318
InstallProtocolInterface: D765BF98-2F0B-4E07-AE77-7E741CB89EFF 73BBF140
Loading driver F80697E9-7FD6-4665-8646-88E33EF71DFC
InstallProtocolInterface: 5B1B31A1-9562-11D2-8E3F-00A0C969723B 7A3EA840
Loading driver at 0x00073BBA000 EntryPoint=0x00073BBAB00 
InstallProtocolInterface: BC62157E-3E33-4FEC-9920-2D3B36D750DF 7A3E8C18
InstallProtocolInterface: 94AB2F58-1438-4EF1-9152-18941A3A0E68 73BBA348
InstallProtocolInterface: A46423E3-4617-49F1-B9FF-D1BFA9115839 73BBA340
Loading driver 2707E46D-DBD7-41C2-9C04-C9FDB8BAD86C
InstallProtocolInterface: 5B1B31A1-9562-11D2-8E3F-00A0C969723B 7A3EA640
Loading driver at 0x00073BB6000 EntryPoint=0x00073BB69C0 
InstallProtocolInterface: BC62157E-3E33-4FEC-9920-2D3B36D750DF 7A3E8698
InstallProtocolInterface: A9396A81-6231-4DD7-BD9B-2E6BF7EC73C2 73BB6310
Loading driver A210F973-229D-4F4D-AA37-9895E6C9EABA
InstallProtocolInterface: 5B1B31A1-9562-11D2-8E3F-00A0C969723B 7A3EA440
Loading driver at 0x00073BB4000 EntryPoint=0x00073BB4A20 
InstallProtocolInterface: BC62157E-3E33-4FEC-9920-2D3B36D750DF 7A3E8118
InstallProtocolInterface: 480F8AE9-0C46-4AA9-BC89-DB9FBA619806 73BB42C0
Loading driver 506533A6-E626-4500-B14F-17939C0E5B60
InstallProtocolInterface: 5B1B31A1-9562-11D2-8E3F-00A0C969723B 7A3EA240
Loading driver at 0x00073BB0000 EntryPoint=0x00073BB0DB0 
InstallProtocolInterface: BC62157E-3E33-4FEC-9920-2D3B36D750DF 7A3E5B98
InstallProtocolInterface: FFE06BDD-6107-46A6-7BB2-5A9C7EC5275C 7A3E9CC0
InstallProtocolInterface: DBFF9D55-89B7-46DA-BDDF-677D3DC0241D 7A3E9CA8
Loading driver 9B680FCE-AD6B-4F3A-B60B-F59899003443
InstallProtocolInterface: 5B1B31A1-9562-11D2-8E3F-00A0C969723B 7A3EA040
Loading driver at 0x00073BA5000 EntryPoint=0x00073BA7E10 
InstallProtocolInterface: BC62157E-3E33-4FEC-9920-2D3B36D750DF 7A3E5518
InstallProtocolInterface: 0379BE4E-D706-437D-B037-EDB82FB772A4 73BA58C0
InstallProtocolInterface: 8B843E20-8132-4852-90CC-551A4E4A7F1C 73BA5900
InstallProtocolInterface: 05C99A21-C70F-4AD2-8A5F-35DF3343F51E 73BA5910
Loading driver 13AC6DD0-73D0-11D4-B06B-00AA00BD6DE7
InstallProtocolInterface: 5B1B31A1-9562-11D2-8E3F-00A0C969723B 7A3E4E40
Loading driver at 0x00073B9F000 EntryPoint=0x00073B9FEC0 
InstallProtocolInterface: BC62157E-3E33-4FEC-9920-2D3B36D750DF 7A3DED98
InstallProtocolInterface: 13AC6DD1-73D0-11D4-B06B-00AA00BD6DE7 7A3DEC18
InstallProtocolInterface: 2755590C-6F3C-42FA-9EA4-A3BA543CDA25 7A3DEA98
InstallProtocolInterface: AAEACCFD-F27B-4C17-B610-75CA1F2DFB52 7A3DE918
Loading driver C1C418F9-591D-461C-82A2-B9CD96DFEA86
InstallProtocolInterface: 5B1B31A1-9562-11D2-8E3F-00A0C969723B 7A3E4C40
Loading driver at 0x00073B9D000 EntryPoint=0x00073B9D8A0 
InstallProtocolInterface: BC62157E-3E33-4FEC-9920-2D3B36D750DF 7A3DE498
InstallProtocolInterface: 31CE593D-108A-485D-ADB2-78F21F2966BE 73B9D2E0
Loading driver FC1B7640-3466-4C06-B1CC-1C935394B5C2
InstallProtocolInterface: 5B1B31A1-9562-11D2-8E3F-00A0C969723B 7A3E4A40
Loading driver at 0x00073B9A000 EntryPoint=0x00073B9AA50 
InstallProtocolInterface: BC62157E-3E33-4FEC-9920-2D3B36D750DF 7A3E3F18
InstallProtocolInterface: F52C3858-5EF8-4D41-834E-C39EEF8A45A3 73C9ECC0
Loading driver 5AAB83E5-F027-4CA7-BFD0-16358CC9E453
InstallProtocolInterface: 5B1B31A1-9562-11D2-8E3F-00A0C969723B 7A3E4840
Loading driver at 0x00073B97000 EntryPoint=0x00073B97C90 
InstallProtocolInterface: BC62157E-3E33-4FEC-9920-2D3B36D750DF 7A3E3998
InstallProtocolInterface: B42B8D12-2ACB-499A-A920-DD5BE6CF09B1 73B97310
Loading driver A5683620-7998-4BB2-A377-1C1E31E1E215
InstallProtocolInterface: 5B1B31A1-9562-11D2-8E3F-00A0C969723B 7A3E4640
Loading driver at 0x00073B90000 EntryPoint=0x00073B91850 
InstallProtocolInterface: BC62157E-3E33-4FEC-9920-2D3B36D750DF 7A3E3498
InstallProtocolInterface: F541796D-A62E-4954-A775-9584F61B9CDD 73B90430
Loading driver F9D88642-0737-49BC-81B5-6889CD57D9EA
InstallProtocolInterface: 5B1B31A1-9562-11D2-8E3F-00A0C969723B 7A3E4440
Loading driver at 0x00073B8D000 EntryPoint=0x00073B8DD40 
InstallProtocolInterface: BC62157E-3E33-4FEC-9920-2D3B36D750DF 7A3E2E98
InstallProtocolInterface: 03583FF6-CB36-4940-947E-B9B39F4AFAF7 73B8FAF0
Loading driver 55E76644-78A5-4A82-A900-7126A5798892
InstallProtocolInterface: 5B1B31A1-9562-11D2-8E3F-00A0C969723B 7A3E4240
Loading driver at 0x00073B89000 EntryPoint=0x00073B89F20 
InstallProtocolInterface: BC62157E-3E33-4FEC-9920-2D3B36D750DF 7A3E2918
InstallProtocolInterface: CFB33810-6E87-4284-B203-A66ABE07F6E8 7A3E9738
Loading driver 44657DE9-F80F-4BBD-BB4F-A04003875AC4
InstallProtocolInterface: 5B1B31A1-9562-11D2-8E3F-00A0C969723B 7A3E4040
Loading driver at 0x00073B87000 EntryPoint=0x00073B87A10 
InstallProtocolInterface: BC62157E-3E33-4FEC-9920-2D3B36D750DF 7A3E2398
Loading driver 6C2004EF-4E0E-4BE4-B14C-340EB4AA5891
InstallProtocolInterface: 5B1B31A1-9562-11D2-8E3F-00A0C969723B 7A3E0E40
Loading driver at 0x00073D21000 EntryPoint=0x00073D22130 
InstallProtocolInterface: BC62157E-3E33-4FEC-9920-2D3B36D750DF 7A3E1D18
Loading driver D9D6BA2A-8225-469B-B36E-3B34EBE805CF
InstallProtocolInterface: 5B1B31A1-9562-11D2-8E3F-00A0C969723B 7A3E0C40
Loading driver at 0x00073D1C000 EntryPoint=0x00073D1D210 
InstallProtocolInterface: BC62157E-3E33-4FEC-9920-2D3B36D750DF 7A3E1918
Loading driver 62D171CB-78CD-4480-8678-C6A2A797A8DE
InstallProtocolInterface: 5B1B31A1-9562-11D2-8E3F-00A0C969723B 7A3E0A40
Loading driver at 0x00073B80000 EntryPoint=0x00073B81970 
InstallProtocolInterface: BC62157E-3E33-4FEC-9920-2D3B36D750DF 7A3E1518
InstallProtocolInterface: 26BACCB1-6F42-11D4-BCE7-0080C73C8881 73B807C0
Loading driver D58EBCE1-AF26-488D-BE66-C164417F8C13
InstallProtocolInterface: 5B1B31A1-9562-11D2-8E3F-00A0C969723B 7A3E0840
Loading driver at 0x00073B79000 EntryPoint=0x00073B7B5B0 
InstallProtocolInterface: BC62157E-3E33-4FEC-9920-2D3B36D750DF 79FCBE18
InstallProtocolInterface: CF8034BE-6768-4D8B-B739-7CCE683A9FBE 7A3DDF48
Address of resource Aperture:  7B7FD798

IIO_resource[0].BusBase:               0
IIO_resource[0].BusLimit:              3F
IIO_resource[0].PciResourceMem32Base:  90000000
IIO_resource[0].PciResourceMem32Limit: ABFFBFFF
IIO_resource[0].PciResourceMem64Base:  380000000000
IIO_resource[0].PciResourceMem64Limit: 381FFFFFFFFF
IIO_resource[0].PciResourceIoBase:     1000
IIO_resource[0].PciResourceIoLimit:    3FFF

InstallProtocolInterface: 09576E91-6D3F-11D2-8E39-00A0C969723B 73B7A150
InstallProtocolInterface: 2F707EBB-4A1A-11D4-9A38-0090273FC14D 7A3DDBD0

IIO_resource[1].BusBase:               40
IIO_resource[1].BusLimit:              7F
IIO_resource[1].PciResourceMem32Base:  AC000000
IIO_resource[1].PciResourceMem32Limit: C7FFBFFF
IIO_resource[1].PciResourceMem64Base:  382000000000
IIO_resource[1].PciResourceMem64Limit: 383FFFFFFFFF
IIO_resource[1].PciResourceIoBase:     4000
IIO_resource[1].PciResourceIoLimit:    7FFF

InstallProtocolInterface: 09576E91-6D3F-11D2-8E39-00A0C969723B 73B7A160
InstallProtocolInterface: 2F707EBB-4A1A-11D4-9A38-0090273FC14D 7A3DD950

IIO_resource[2].BusBase:               80
IIO_resource[2].BusLimit:              BF
IIO_resource[2].PciResourceMem32Base:  C8000000
IIO_resource[2].PciResourceMem32Limit: E3FFBFFF
IIO_resource[2].PciResourceMem64Base:  384000000000
IIO_resource[2].PciResourceMem64Limit: 385FFFFFFFFF
IIO_resource[2].PciResourceIoBase:     8000
IIO_resource[2].PciResourceIoLimit:    BFFF

InstallProtocolInterface: 09576E91-6D3F-11D2-8E39-00A0C969723B 73B7A170
InstallProtocolInterface: 2F707EBB-4A1A-11D4-9A38-0090273FC14D 7A3DD6D0

IIO_resource[3].BusBase:               C0
IIO_resource[3].BusLimit:              FF
IIO_resource[3].PciResourceMem32Base:  E4000000
IIO_resource[3].PciResourceMem32Limit: FBFFBFFF
IIO_resource[3].PciResourceMem64Base:  386000000000
IIO_resource[3].PciResourceMem64Limit: 387FFFFFFFFF
IIO_resource[3].PciResourceIoBase:     C000
IIO_resource[3].PciResourceIoLimit:    FFFF

InstallProtocolInterface: 09576E91-6D3F-11D2-8E39-00A0C969723B 73B7A180
InstallProtocolInterface: 2F707EBB-4A1A-11D4-9A38-0090273FC14D 7A3DD450
Loading driver 6D33944A-EC75-4855-A54D-809C75241F6C
InstallProtocolInterface: 5B1B31A1-9562-11D2-8E3F-00A0C969723B 7A3E0640
Loading driver at 0x00073B5B000 EntryPoint=0x00073B62630 
InstallProtocolInterface: BC62157E-3E33-4FEC-9920-2D3B36D750DF 79FCAA98
InstallProtocolInterface: 665E3FF6-46CC-11D4-9A38-0090273FC14D 73B5C228
Loading driver CA515306-00CE-4032-874E-11B755FF6866
InstallProtocolInterface: 5B1B31A1-9562-11D2-8E3F-00A0C969723B 7A3E0440
Loading driver at 0x00073B59000 EntryPoint=0x00073B59800 
InstallProtocolInterface: BC62157E-3E33-4FEC-9920-2D3B36D750DF 79FCA398
Loading driver BA31025C-4AA8-4CAE-98CA-BA12C6BC7D78
InstallProtocolInterface: 5B1B31A1-9562-11D2-8E3F-00A0C969723B 7A3E0240
Loading driver at 0x00073D19000 EntryPoint=0x00073D19B40 
InstallProtocolInterface: BC62157E-3E33-4FEC-9920-2D3B36D750DF 79FC9F18
InstallProtocolInterface: 843DC720-AB1E-42CB-9357-8A0078F3561B 73D1AF88
Loading driver C194C6EA-B68C-4981-B64B-9BD271474B20
InstallProtocolInterface: 5B1B31A1-9562-11D2-8E3F-00A0C969723B 7A3E0040
Loading driver at 0x00073D13000 EntryPoint=0x00073D14290 
InstallProtocolInterface: BC62157E-3E33-4FEC-9920-2D3B36D750DF 79FC9A18
InstallPchSpi() Start
InstallProtocolInterface: 1156EFC6-EA32-4396-B5D5-26932E83C313 73C9CC28
InstallPchSpi() End
Loading driver BB1FBD4F-2E30-4793-9BED-74F672BC8FFE
InstallProtocolInterface: 5B1B31A1-9562-11D2-8E3F-00A0C969723B 79FC7E40
Loading driver at 0x00073D10000 EntryPoint=0x00073D10B10 
InstallProtocolInterface: BC62157E-3E33-4FEC-9920-2D3B36D750DF 79FC9298
InitializePchReset() Start
InstallProtocolInterface: F0BBFCA0-684E-48B3-BAE2-6C84B89E5339 73C9E6A8
InstallProtocolInterface: 27CFAC88-46CC-11D4-9A38-0090273FC14D 0
InitializePchReset() End
Loading driver EBF342FE-B1D3-4EF8-957C-8048606FF671
InstallProtocolInterface: 5B1B31A1-9562-11D2-8E3F-00A0C969723B 79FC7C40
Loading driver at 0x00073B43000 EntryPoint=0x00073B458D0 
InstallProtocolInterface: BC62157E-3E33-4FEC-9920-2D3B36D750DF 79FC6C18
InstallProtocolInterface: B9D4C360-BCFB-4F9B-9298-53C136982258 73B43410
InstallProtocolInterface: A770C357-B693-4E6D-A6CF-D21C728E550B 73B43440
InstallProtocolInterface: 1F73B18D-4630-43C1-A1DE-6F80855D7DA4 73B43420
Loading driver 06D20D84-A032-4E25-969A-346D255E46D1
InstallProtocolInterface: 5B1B31A1-9562-11D2-8E3F-00A0C969723B 79FC7A40
Loading driver at 0x00073D0B000 EntryPoint=0x00073D0C4A0 
InstallProtocolInterface: BC62157E-3E33-4FEC-9920-2D3B36D750DF 79FC6318
InstallProtocolInterface: 0067835F-9A50-433A-8CBB-852078197814 73D0EF60
Loading driver 4D35A5A7-622E-4955-A5D2-CDA812940D74
InstallProtocolInterface: 5B1B31A1-9562-11D2-8E3F-00A0C969723B 79FC7840
Loading driver at 0x00073D06000 EntryPoint=0x00073D07610 
InstallProtocolInterface: BC62157E-3E33-4FEC-9920-2D3B36D750DF 79FC0D98
