--- a/drivers/net/ethernet/mediatek/mdio_rt2880.c	2016-12-25 13:26:58.456509613 +0100
+++ b/drivers/net/ethernet/mediatek/mdio_rt2880.c	2016-12-25 13:42:08.238633833 +0100
@@ -156,7 +156,7 @@ void rt2880_port_init(struct fe_priv *pr
 	const __be32 *id = of_get_property(np, "reg", NULL);
 	const __be32 *link;
 	int size;
-	int phy_mode;
+	int phy_mode, set_phy_mode = -1;
 
 	if (!id || (be32_to_cpu(*id) != 0)) {
 		pr_err("%s: invalid port id\n", np->name);
@@ -175,10 +175,13 @@ void rt2880_port_init(struct fe_priv *pr
 	phy_mode = of_get_phy_mode(np);
 	switch (phy_mode) {
 	case PHY_INTERFACE_MODE_RGMII:
+		set_phy_mode = 0;
 		break;
 	case PHY_INTERFACE_MODE_MII:
+		set_phy_mode = 1;
 		break;
 	case PHY_INTERFACE_MODE_RMII:
+		set_phy_mode = 2;
 		break;
 	default:
 		if (!priv->phy->phy_fixed[0])
@@ -187,6 +190,18 @@ void rt2880_port_init(struct fe_priv *pr
 		break;
 	}
 
+	if (set_phy_mode != -1) {
+		u32 tmp;
+		u32 ge_offset;
+
+		ge_offset = 12 + id * 2; /* GE1 is at 12-13. GE2 is at 14-15 */
+
+		tmp = rt_sysc_r32(RT3883_SYSC_REG_SYSCFG1);
+		tmp = (t & ~GENMASK(ge_offset + 1, ge_offset)) |
+		    (set_phy_mode << ge_offset);
+		rt_sysc_w32(tmp, RT3883_SYSC_REG_SYSCFG1);
+	}
+
 	priv->phy->phy_node[0] = of_parse_phandle(np, "phy-handle", 0);
 	if (!priv->phy->phy_node[0] && !priv->phy->phy_fixed[0])
 		return;