[LEDE-DEV] [PATCH 2/3] ramips-mt7621: add GPIO-config for Ubiquiti-EdgeRouterX(-SFP)

[Mathias Kresin]

14.05.2017 21:22, Sven Roederer:
> I just gave it another try, as I like the idea of having it in the DTS. As my test ERX is gone I continue testing on ERX-SFP.
> Please se below ...
>
> On Sonntag, 14. Mai 2017 16:24:15 CEST Mathias Kresin wrote:
>>>>
>>>> If you use the gpio-export node in the device tree source file, the gpio
>>>> pin should appear at /sys/class/gpio/. Most likely you have done
>>>> something wrong. Could it be that you used exactly the same gpio pin
>>>> number as you have it in your 03_gpio_export file? You need to decrement
>>>> the gpio pin number by the gpio base as it is done for all gpios in the
>>>> dts.
>>>>
>>> for the "gpio in dts" I used this branch
>>> https://github.com/SvenRoederer/lede-project-source/commits/ERX-SFP_gpio-
>>> in-dts --> see the last 2 commits. Code only changed for ERX for this
>>> test.
>>> Did I miss something?
>>
>> Yes you did. The gpio-export,output value is wrong. It has to be either
>> 0 or 1, similar to the values set for the gpio_switch config in
>> /e/c/system.
>>
>
> I removed the 03_gpio_export and added this to the dts:
> gpio_export {
> 	compatible = "gpio-export";
> 	#size-cells = <0>;
>
> 	poe_passthrough {
> 	    gpio-export,name = "poe_power_port0";
> 	    gpio-export,output = <1>;
> 	    gpios = <&gpio0 496 0>;

Your GPIO number is wrong.

The device tree is some kind of abstraction layer to the hardware and in 
terms of GPIOs you are only using "logical/virtual" GPIO numbers.

The mt7621 has two GPIO banks: gpio0 and gpio1 (yes I know there is a 
gpio2 in the mt7621.dtsi, but the SoC has only 61 GPIOs). Each GPIO bank 
has 32 GPIOs and is exported to the sysfs at /sys/class/gpio/gpiochipNNN.

/sys/class/gpio/gpiochipNNN/base is the first (physical/real) GPIO 
number managed by this chip. If the gpiochips base is 462, &gpio0 0 to 
31 refers to the physical GPIOs 462 to 493. &gpio1 0 to 28 refers to the 
physical GPIOs 494 to 522.

But it is still not the whole story. The pins of the SoC can have 
different functions. Via the pinmux node you specify the purpose of the 
pins[0]. For the ERX the following groups are set to GPIO mode:

uart2: &gpio0 9 to 12
uart3: &gpio0 5 to 8
i2c: &gpio0 3 to 4
pcie: &gpio0 19
rgmii2: &gpio0 22 to 31, &gpio1 0 to 1
jtag: &gpio0 13 to 17

It kinda looks like copy/paste from the MT7621.dts. Most of the GPIOs 
are not used at all.

Mathias

[0] 
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/arch/mips/ralink/mt7621.c