[LEDE-DEV] [PATCH 4/5] ag71xx: Reorder ag71xx struct members for better cache performance

Felix Fietkau nbd at nbd.name
Mon Dec 4 13:59:49 PST 2017


On 2017-12-04 20:40, Rosen Penev wrote:
> Qualcomm claims this improves the D-cache footprint. Origina commit message below:
> 
> From: Ben Menchaca <ben.menchaca at qca.qualcomm.com>
> Date: Fri, 7 Jun 2013 10:57:28 -0500
> Subject: [ag71xx] cluster/align structs for cache perf
> 
> Cluster the frequently used, per-packet structures in ag71xx near
> to each other, and cacheline-align them.  Some other re-ordering
> occurred to move "warmer" structures near the per-packet structures.
> 
> Signed-off-by: Ben Menchaca <ben.menchaca at qca.qualcomm.com>
> Signed-off-by: Rosen Penev <rosenp at gmail.com>
Merged patches 2-4 to my staging tree.

Thanks,

- Felix



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