[LEDE-DEV] jtag on rt5350

[Giuseppe Lippolis]

Thanks to a resistance I had the jtag working properly.
Thanks to the jtag I have now the uboot from the ralink-sdk working properly
in ram (after skipping the init phase).
Now I would like to flash it. I see that the flash image add an header on
the top of the uboot image where are stored also the RAM load address:

00000000: 27051956 3eeb1bce 581ee93c 0001a130  '..V>...X..<...0
00000010: 80200000 80200000 36e07ec3 05050100  . ... ..6.~.....
00000020: 53504920 466c6173 6820496d 61676500  SPI Flash Image.
00000030: 06500000 00000000 00000000 00000000  .P..............

This sound like if the RT5350 doesn't execute the code from flash, but the
internal ROM code copy it in RAM and then execute.
My question then is:
How the ROM code can copy the image in ram if the ram is still not
initialized?

Have someone some tips?
Thanks,
Bye.

> -----Ursprüngliche Nachricht-----
> Von: Giuseppe Lippolis [mailto:giu.lippolis at gmail.com]
> Gesendet: Samstag, 5. November 2016 11:30
> An: lede-dev at lists.infradead.org
> Betreff: jtag on rt5350
> 
> Hi All,
> In ordert o be able to flash properly lede on the DWR-512 most likly I
need to
> change the bootloader with u-boot (see
> http://lists.infradead.org/pipermail/lede-dev/2016-October/003435.html).
> 
> Before to proceed I wold be sure that I'm able to control the target using
the
> jtag.
> On internet I found some tips to create a .cfg file for openocd:
> 
> # FTDI C232HM - USB 2.0 Hi-Speed to MPSSE Cable interface ftdi
ftdi_vid_pid
> 0x0403 0x6014 # 0x000f -> TMS, TCK, TDI, TDO # 0x4000 -> ^LED # 0x0010 ->
> GPIOL0 (grey) # 0x0020 -> GPIOL1 (purpe) # 0x0040 -> GPIOL2 (white) #
> 0x0080 -> GPIOL3 (blue) ftdi_layout_init 0x0008 0x400b ftdi_layout_signal
> nTRST -data 0x0020 -oe 0x0020 jtag_ntrst_delay 100 adapter_khz 100
> reset_config trst_only
> 
> set  _CHIPNAME rt5350
> set  _ENDIAN little
> set _CPUTAPID 0x1535024f
> 
> #daemon configuration
> telnet_port 4444
> 
> #jtag scan chain
> # format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
> jtag newtap $_CHIPNAME cpu -irlen 5  -ircapture 0x1 -irmask 0x3 -expected-
> id $_CPUTAPID
> 
> set _TARGETNAME [format "%s.cpu" $_CHIPNAME] target create
> $_TARGETNAME mips_m4k -endian $_ENDIAN -chain-position
> $_TARGETNAME
> 
> 
> When I run openocd I get:
> Open On-Chip Debugger 0.9.0 (2015-09-02-10:43) Licensed under GNU GPL
> v2 For bug reports, read
>         http://openocd.org/doc/doxygen/bugs.html
> Info : auto-selecting first available session transport "jtag". To
override use
> 'transport select <transport>'.
> jtag_ntrst_delay: 100
> adapter speed: 100 kHz
> trst_only separate trst_push_pull
> Info : clock speed 100 kHz
> Info : JTAG tap: rt5350.cpu tap/device found: 0x1535024f (mfg: 0x127,
part:
> 0x5350, ver: 0x1)
> 
> And using the telnet connection:
> 
> Open On-Chip Debugger
> > targets
>     TargetName         Type       Endian TapName            State
> --  ------------------ ---------- ------ ------------------ ------------
>  0* rt5350.cpu         mips_m4k   little rt5350.cpu         running
> > init
> > halt
> Failed to enter Debug Mode!
> Halt timed out, wake up GDB.
> timed out while waiting for target halted
> 
> because the target is not halted I cannot send read/write command and thus
> I cannot control the target.
> 
> Have someone some tips?
> 
> Thanks,
> Bye.
>