[openwrt/openwrt] mpc85xx: p2020: add support for WatchGuard XTM330 (NC5AE7)
LEDE Commits
lede-commits at lists.infradead.org
Sat Jan 10 12:41:25 PST 2026
hauke pushed a commit to openwrt/openwrt.git, branch main:
https://git.openwrt.org/6150f9ceab7c34360cb877b6b258dc9f1d3e5473
commit 6150f9ceab7c34360cb877b6b258dc9f1d3e5473
Author: Pawel Dembicki <paweldembicki at gmail.com>
AuthorDate: Sun Nov 30 23:50:48 2025 +0100
mpc85xx: p2020: add support for WatchGuard XTM330 (NC5AE7)
Hardware specifications:
- CPU: Freescale/NXP P2020, dual-core PowerPC @ 1 GHz
- RAM: 1 GB DDR3
- Flash: 2 MB NOR, 512 MB NAND
- Networking: 7x Gigabit Ethernet ports (via two Marvell 88E6171
switches, each attached to a different MAC)
- USB: 2x USB 2.0 ports (front panel)
- mini-PCIe slot
- RTC: Ricoh RS5C372A
- 4 buttons (via external MCU)
- 3 LEDs (via external MCU)
- LCD display (via external MCU)
Installation procedure:
1. Obtain the original MAC address table from the stock bootlog, for
example:
setting device eth0 to 00:90:7f:00:00:01
setting device eth1 to 00:90:7f:00:00:02
setting device eth2 to 00:90:7f:00:00:03
setting device eth3 to 00:90:7f:00:00:04
setting device eth4 to 00:90:7f:00:00:05
setting device eth5 to 00:90:7f:00:00:06
setting device eth6 to 00:90:7f:00:00:07
2. Open the case and move jumper JP1 from 2-3 to 1-2 to enter FAILSAFE
mode.
3. Power on the device and interrupt the boot process to access the U-Boot
shell.
4. Program the MAC base address into the EEPROM (text after '#' is a
comment):
mac ports 3
mac 2 00:90:7f:00:00:01 # first MAC address from bootlog
mac save
5. Reset the device and enter the U-Boot console again.
6. Connect a TFTP server to port 6 and boot the initramfs image:
setenv ipaddr 192.168.1.3
setenv serverip 192.168.1.2
setenv loadaddr 1000000
tftpboot $loadaddr openwrt-mpc85xx-p2020-watchguard_xtm330-initramfs-kernel.bin
bootm $loadaddr
7. (Optional) Backup all MTD partitions if you want the ability to restore
stock firmware.
8. Perform a normal sysupgrade from the initramfs environment.
9. Power off the device and move jumper JP1 back to 2-3.
10. The device will now boot OpenWrt.
Known issues:
- LCD, buttons and LEDs are controlled by an external MCU; the protocol is
currently unknown.
- The internal connection between the two Marvell switches is unused by
OpenWrt.
- The stock firmware uses an empty U-Boot environment; saving variables
modifies the environment and prevents a normal boot. FAILSAFE U-Boot
remains functional.
- WatchGuard configuration is encrypted; DSA MAC addresses are stored in
this configuration.
- Failsafe Ethernet works on port1.
Signed-off-by: Pawel Dembicki <paweldembicki at gmail.com>
Link: https://github.com/openwrt/openwrt/pull/21020
Signed-off-by: Hauke Mehrtens <hauke at hauke-m.de>
---
.../boot/uboot-tools/uboot-envtools/files/mpc85xx | 3 +
.../mpc85xx/base-files/etc/board.d/02_network | 3 +
.../lib/preinit/05_set_preinit_iface_mpc85xx | 9 +-
.../mpc85xx/base-files/lib/upgrade/platform.sh | 3 +-
.../mpc85xx/files/arch/powerpc/boot/dts/xtm330.dts | 362 +++++++++++++++++++++
target/linux/mpc85xx/image/p2020.mk | 18 +-
target/linux/mpc85xx/p2020/config-default | 9 +
target/linux/mpc85xx/p2020/target.mk | 1 +
...2-powerpc-85xx-add-zimage-la3000-to-p2020.patch | 10 +
9 files changed, 415 insertions(+), 3 deletions(-)
diff --git a/package/boot/uboot-tools/uboot-envtools/files/mpc85xx b/package/boot/uboot-tools/uboot-envtools/files/mpc85xx
index 70d12bb7ea..757344ecaa 100644
--- a/package/boot/uboot-tools/uboot-envtools/files/mpc85xx
+++ b/package/boot/uboot-tools/uboot-envtools/files/mpc85xx
@@ -24,6 +24,9 @@ watchguard,firebox-t10|\
watchguard,firebox-t15)
ubootenv_add_uci_config "$(find_mtd_part 'u-boot-env')" "0x0" "0x2000" "0x10000"
;;
+watchguard,xtm330)
+ ubootenv_add_uci_config "/dev/mtd4" "0x0" "0x10000" "0x10000"
+ ;;
aerohive,hiveap-330)
ubootenv_add_uci_config "$(find_mtd_part 'u-boot-env')" "0x0" "0x20000" "0x10000"
;;
diff --git a/target/linux/mpc85xx/base-files/etc/board.d/02_network b/target/linux/mpc85xx/base-files/etc/board.d/02_network
index d1ebe806f1..6a18ace0ef 100644
--- a/target/linux/mpc85xx/base-files/etc/board.d/02_network
+++ b/target/linux/mpc85xx/base-files/etc/board.d/02_network
@@ -33,6 +33,9 @@ watchguard,firebox-t10|\
watchguard,firebox-t15)
ucidef_set_interfaces_lan_wan "eth1 eth2" "eth0"
;;
+watchguard,xtm330)
+ ucidef_set_interfaces_lan_wan "port1 port2 port3 port4 port5 port6" "port0"
+ ;;
*)
ucidef_set_interfaces_lan_wan "eth0" "eth1"
;;
diff --git a/target/linux/mpc85xx/base-files/lib/preinit/05_set_preinit_iface_mpc85xx b/target/linux/mpc85xx/base-files/lib/preinit/05_set_preinit_iface_mpc85xx
index be9325589f..d6f0853438 100644
--- a/target/linux/mpc85xx/base-files/lib/preinit/05_set_preinit_iface_mpc85xx
+++ b/target/linux/mpc85xx/base-files/lib/preinit/05_set_preinit_iface_mpc85xx
@@ -3,7 +3,14 @@
#
mpc85xx_set_preinit_iface() {
- ifname=eth0
+ case $(board_name) in
+ watchguard,xtm330)
+ ifname=port1
+ ;;
+ *)
+ ifname=eth0
+ ;;
+ esac
}
boot_hook_add preinit_main mpc85xx_set_preinit_iface
diff --git a/target/linux/mpc85xx/base-files/lib/upgrade/platform.sh b/target/linux/mpc85xx/base-files/lib/upgrade/platform.sh
index f0875388af..021c7e465a 100755
--- a/target/linux/mpc85xx/base-files/lib/upgrade/platform.sh
+++ b/target/linux/mpc85xx/base-files/lib/upgrade/platform.sh
@@ -17,7 +17,8 @@ platform_do_upgrade() {
ocedo,panda|\
sophos,red-15w-rev1|\
watchguard,firebox-t10|\
- watchguard,firebox-t15)
+ watchguard,firebox-t15|\
+ watchguard,xtm330)
nand_do_upgrade "$1"
;;
*)
diff --git a/target/linux/mpc85xx/files/arch/powerpc/boot/dts/xtm330.dts b/target/linux/mpc85xx/files/arch/powerpc/boot/dts/xtm330.dts
new file mode 100644
index 0000000000..79b921118d
--- /dev/null
+++ b/target/linux/mpc85xx/files/arch/powerpc/boot/dts/xtm330.dts
@@ -0,0 +1,362 @@
+// SPDX-License-Identifier: GPL-2.0-or-later or MIT
+/*
+ * WatchGuard XTM 330 (NC5AE7) Device Tree Source File
+ *
+ * Copyright (C) 2025 Pawel Dembicki <paweldembicki at gmail.com>
+ */
+
+/dts-v1/;
+
+/include/ "fsl/p2020si-pre.dtsi"
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+
+/ {
+ model = "WatchGuard XTM 330 (NC5AE7)";
+ compatible = "watchguard,xtm330";
+
+ aliases {
+ ethernet0 = &enet0;
+ ethernet1 = &enet2;
+ serial0 = &serial0;
+ serial1 = &serial1;
+ pci0 = &pci2;
+ };
+
+ chosen {
+ bootargs-override = "console=ttyS0,115200";
+ };
+
+ memory {
+ device_type = "memory";
+ };
+
+ lbc: localbus at ffe05000 {
+ reg = <0 0xffe05000 0 0x1000>;
+
+ /* NOR and NAND Flashes */
+ ranges = < 0x0 0x0 0x0 0xefe00000 0x00200000
+ 0x1 0x0 0x0 0xffa00000 0x00040000 >;
+
+ nor at 0,0 {
+ compatible = "cfi-flash";
+ reg = <0x0 0x0 0x200000>;
+ bank-width = <2>;
+ device-width = <1>;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition at 0 {
+ label = "cfg0";
+ reg = <0x00000000 0x00020000>;
+ };
+
+ partition at 20000 {
+ label = "cfg1";
+ reg = <0x00020000 0x00010000>;
+ };
+
+ partition at 30000 {
+ label = "mfg-data";
+ reg = <0x00030000 0x00010000>;
+ };
+
+ partition at 40000 {
+ label = "bootopt";
+ reg = <0x00040000 0x000b0000>;
+ };
+
+ partition at f0000 {
+ label = "u-boot-env";
+ reg = <0x000f0000 0x00010000>;
+ };
+
+ partition at 100000 {
+ label = "u-boot";
+ reg = <0x00100000 0x00080000>;
+ };
+
+ partition at 180000 {
+ label = "u-boot-failsafe";
+ reg = <0x00180000 0x00080000>;
+ };
+ };
+ };
+
+ nand at 1,0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "fsl,p2020-fcm-nand", "fsl,elbc-fcm-nand";
+ reg = <0x1 0x0 0x40000>;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition at 0 {
+ label = "dtb";
+ reg = <0x00000000 0x00020000>;
+ };
+
+ partition at 20000 {
+ label = "kernel";
+ reg = <0x00020000 0x00500000>;
+ };
+
+ partition at 520000 {
+ label = "ubi";
+ reg = <0x00520000 0x1fae0000>;
+ };
+ };
+ };
+ };
+
+ soc: soc at ffe00000 {
+ ranges = <0x0 0x0 0xffe00000 0x100000>;
+
+ gpio0: gpio-controller at fc00 {
+ usb-hub-reset-hog {
+ gpio-hog;
+ gpios = <12 GPIO_ACTIVE_LOW>;
+ output-high;
+ line-name = "usb-hub-reset";
+ };
+ };
+
+ i2c at 3000 {
+ rtc at 32 {
+ compatible = "ricoh,rs5c372a";
+ reg = <0x32>;
+ };
+
+ hwmon at 2d {
+ compatible = "winbond,w83793";
+ reg = <0x2d>;
+ };
+
+ eeprom at 54 {
+ compatible = "atmel,24c04";
+ reg = <0x54>;
+
+ nvmem-layout {
+ compatible = "fixed-layout";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ mac_addr_0: macaddr at 0 {
+ compatible = "mac-base";
+ reg = <0x4e 0x6>;
+ #nvmem-cell-cells = <1>;
+ };
+ };
+ };
+ };
+
+ usb at 22000 {
+ phy_type = "ulpi";
+ dr_mode = "host";
+ };
+
+ mdio at 24520 {
+ switch at 10 {
+ compatible = "marvell,mv88e6085";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x10>;
+ dsa,member = <0 0>;
+
+ reset-gpios = <&gpio0 13 GPIO_ACTIVE_LOW>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port at 0 {
+ reg = <0>;
+ label = "port0";
+
+ nvmem-cells = <&mac_addr_0 0>;
+ nvmem-cell-names = "mac-address";
+ };
+
+ port at 1 {
+ reg = <1>;
+ label = "port1";
+
+ nvmem-cells = <&mac_addr_0 1>;
+ nvmem-cell-names = "mac-address";
+ };
+
+ port at 2 {
+ reg = <2>;
+ label = "port2";
+
+ nvmem-cells = <&mac_addr_0 2>;
+ nvmem-cell-names = "mac-address";
+ };
+
+ port at 3 {
+ reg = <3>;
+ label = "port3";
+
+ nvmem-cells = <&mac_addr_0 3>;
+ nvmem-cell-names = "mac-address";
+ };
+
+ port at 4 {
+ reg = <4>;
+ label = "internal1";
+ };
+
+ port at 5 {
+ reg = <5>;
+ phy-mode = "rgmii-id";
+ ethernet = <&enet2>;
+ fixed-link {
+ speed = <1000>;
+ full-duplex;
+ };
+ };
+ };
+ };
+
+ switch at 11 {
+ compatible = "marvell,mv88e6085";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x11>;
+ dsa,member = <1 0>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port at 0 {
+ reg = <0>;
+ label = "internal2";
+ };
+
+ port at 1 {
+ reg = <1>;
+ label = "port4";
+
+ nvmem-cells = <&mac_addr_0 4>;
+ nvmem-cell-names = "mac-address";
+ };
+
+ port at 2 {
+ reg = <2>;
+ label = "port5";
+
+ nvmem-cells = <&mac_addr_0 5>;
+ nvmem-cell-names = "mac-address";
+ };
+
+ port at 3 {
+ reg = <3>;
+ label = "port6";
+
+ nvmem-cells = <&mac_addr_0 6>;
+ nvmem-cell-names = "mac-address";
+ };
+
+ port at 5 {
+ reg = <5>;
+ phy-mode = "rgmii-id";
+ ethernet = <&enet0>;
+ fixed-link {
+ speed = <1000>;
+ full-duplex;
+ };
+ };
+ };
+ };
+ };
+
+ mdio at 25520 {
+ status = "disabled";
+ };
+
+ mdio at 26520 {
+ status = "disabled";
+ };
+
+ enet0: ethernet at 24000 {
+ phy-connection-type = "rgmii-id";
+
+ fixed-link {
+ speed = <1000>;
+ full-duplex;
+ };
+ };
+
+ enet1: ethernet at 25000 {
+ status = "disabled";
+ };
+
+ enet2: ethernet at 26000 {
+ phy-connection-type = "rgmii-id";
+
+ fixed-link {
+ speed = <1000>;
+ full-duplex;
+ };
+ };
+ };
+
+ pci0: pcie at ffe08000 {
+ reg = <0 0xffe08000 0 0x1000>;
+ ranges = <0x2000000 0x0 0xc0000000 0x0 0xc0000000 0x0 0x20000000
+ 0x1000000 0x0 0x00000000 0x0 0xffc20000 0x0 0x10000>;
+ status = "disabled";
+
+ pcie at 0 {
+ ranges = < 0x2000000 0x0 0xc0000000
+ 0x2000000 0x0 0xc0000000
+ 0x0 0x20000000
+
+ 0x1000000 0x0 0x0
+ 0x1000000 0x0 0x0
+ 0x0 0x100000>;
+ };
+ };
+
+ pci1: pcie at ffe09000 {
+ reg = <0 0xffe09000 0 0x1000>;
+ ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000
+ 0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x10000>;
+ status = "disabled";
+
+ pcie at 0 {
+ ranges = < 0x2000000 0x0 0xa0000000
+ 0x2000000 0x0 0xa0000000
+ 0x0 0x20000000
+
+ 0x1000000 0x0 0x0
+ 0x1000000 0x0 0x0
+ 0x0 0x100000>;
+ };
+ };
+
+ pci2: pcie at ffe0a000 {
+ reg = <0 0xffe0a000 0 0x1000>;
+ ranges = <0x2000000 0x0 0x80000000 0x0 0x80000000 0x0 0x20000000
+ 0x1000000 0x0 0x00000000 0x0 0xffc00000 0x0 0x10000>;
+ pcie at 0 {
+ ranges = < 0x2000000 0x0 0x80000000
+ 0x2000000 0x0 0x80000000
+ 0x0 0x20000000
+
+ 0x1000000 0x0 0x0
+ 0x1000000 0x0 0x0
+ 0x0 0x10000>;
+ };
+ };
+};
+
+/include/ "fsl/p2020si-post.dtsi"
diff --git a/target/linux/mpc85xx/image/p2020.mk b/target/linux/mpc85xx/image/p2020.mk
index 79b5fa660c..950717270d 100644
--- a/target/linux/mpc85xx/image/p2020.mk
+++ b/target/linux/mpc85xx/image/p2020.mk
@@ -3,7 +3,7 @@ define Device/freescale_p2020rdb
DEVICE_MODEL := P2020RDB
DEVICE_DTS_DIR := $(DTS_DIR)/fsl
DEVICE_PACKAGES := kmod-hwmon-lm90 kmod-rtc-ds1307 \
- kmod-gpio-pca953x kmod-eeprom-at24
+ kmod-gpio-pca953x
BLOCKSIZE := 128k
KERNEL := kernel-bin | gzip | \
fit gzip $$(KDIR)/image-$$(firstword $$(DEVICE_DTS)).dtb
@@ -13,3 +13,19 @@ define Device/freescale_p2020rdb
pad-rootfs $$(BLOCKSIZE) | append-metadata
endef
TARGET_DEVICES += freescale_p2020rdb
+
+define Device/watchguard_xtm330
+ DEVICE_VENDOR := WatchGuard
+ DEVICE_MODEL := XTM 330
+ DEVICE_VARIANT := NC5AE7
+ DEVICE_PACKAGES := kmod-dsa-mv88e6xxx kmod-hwmon-w83793 \
+ kmod-rtc-rs5c372a
+ BLOCKSIZE := 128k
+ KERNEL = kernel-bin | fit none $(KDIR)/image-$$(DEVICE_DTS).dtb
+ KERNEL_NAME := zImage.la3000000
+ KERNEL_ENTRY := 0x3000000
+ KERNEL_LOADADDR := 0x3000000
+ IMAGES := sysupgrade.bin
+ IMAGE/sysupgrade.bin := sysupgrade-tar | append-metadata
+endef
+TARGET_DEVICES += watchguard_xtm330
diff --git a/target/linux/mpc85xx/p2020/config-default b/target/linux/mpc85xx/p2020/config-default
index bfdb48959a..07db6407be 100644
--- a/target/linux/mpc85xx/p2020/config-default
+++ b/target/linux/mpc85xx/p2020/config-default
@@ -1,8 +1,10 @@
CONFIG_BLK_DEV_NVME=y
CONFIG_CONTEXT_TRACKING=y
CONFIG_CONTEXT_TRACKING_IDLE=y
+CONFIG_CMDLINE_OVERRIDE=y
CONFIG_CPU_RMAP=y
CONFIG_DEFAULT_UIMAGE=y
+CONFIG_EEPROM_AT24=y
CONFIG_FSL_ULI1575=y
CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y
CONFIG_GENERIC_IRQ_MIGRATION=y
@@ -16,10 +18,15 @@ CONFIG_MTD_CFI=y
CONFIG_MTD_NAND_FSL_ELBC=y
CONFIG_MTD_PHYSMAP=y
CONFIG_MTD_SPLIT_FIT_FW=y
+CONFIG_MTD_UBI=y
+CONFIG_MTD_UBI_BEB_LIMIT=20
+CONFIG_MTD_UBI_BLOCK=y
+CONFIG_MTD_UBI_WL_THRESHOLD=4096
CONFIG_MUTEX_SPIN_ON_OWNER=y
CONFIG_NEED_DMA_MAP_STATE=y
CONFIG_NET_FLOW_LIMIT=y
CONFIG_NR_CPUS=2
+CONFIG_NVMEM_SYSFS=y
CONFIG_NVME_CORE=y
# CONFIG_NVME_MULTIPATH is not set
CONFIG_PADATA=y
@@ -29,6 +36,7 @@ CONFIG_PCI_MSI_IRQ_DOMAIN=y
CONFIG_PPC_I8259=y
CONFIG_PPC_MSI_BITMAP=y
CONFIG_PPC_P2020=y
+CONFIG_PPC_ZIMAGE_LA3000000=y
CONFIG_REGMAP=y
CONFIG_REGMAP_I2C=y
CONFIG_RFS_ACCEL=y
@@ -42,4 +50,5 @@ CONFIG_TARGET_CPU="8540"
CONFIG_TARGET_CPU_BOOL=y
CONFIG_TREE_RCU=y
CONFIG_TREE_SRCU=y
+CONFIG_UBIFS_FS=y
CONFIG_XPS=y
diff --git a/target/linux/mpc85xx/p2020/target.mk b/target/linux/mpc85xx/p2020/target.mk
index 23aca656b2..6fb5279874 100644
--- a/target/linux/mpc85xx/p2020/target.mk
+++ b/target/linux/mpc85xx/p2020/target.mk
@@ -1,4 +1,5 @@
BOARDNAME:=P2020
+KERNEL_IMAGES:=zImage.la3000000
define Target/Description
Build firmware images for Freescale P2020 based boards.
diff --git a/target/linux/mpc85xx/patches-6.12/112-powerpc-85xx-add-zimage-la3000-to-p2020.patch b/target/linux/mpc85xx/patches-6.12/112-powerpc-85xx-add-zimage-la3000-to-p2020.patch
new file mode 100644
index 0000000000..95716c984f
--- /dev/null
+++ b/target/linux/mpc85xx/patches-6.12/112-powerpc-85xx-add-zimage-la3000-to-p2020.patch
@@ -0,0 +1,10 @@
+--- a/arch/powerpc/platforms/85xx/Kconfig
++++ b/arch/powerpc/platforms/85xx/Kconfig
+@@ -187,6 +187,7 @@ config PPC_P2020
+ default y if MPC85xx_DS || MPC85xx_RDB
+ select DEFAULT_UIMAGE
+ select SWIOTLB
++ select PPC_ZIMAGE_LA3000000
+ imply PPC_I8259
+ imply FSL_ULI1575 if PCI
+ help
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