[openwrt/openwrt] qualcommax: ipq50xx: enable ipq-cmn-pll driver compilation
LEDE Commits
lede-commits at lists.infradead.org
Thu Jan 8 01:41:39 PST 2026
robimarko pushed a commit to openwrt/openwrt.git, branch main:
https://git.openwrt.org/fdce6f99be08eada76eafcb7172701010ad4a859
commit fdce6f99be08eada76eafcb7172701010ad4a859
Author: George Moussalem <george.moussalem at outlook.com>
AuthorDate: Wed Jan 7 17:44:44 2026 +0400
qualcommax: ipq50xx: enable ipq-cmn-pll driver compilation
Add missing dt-bindings/include files needed for compilation of driver.
Enable compilation of the CMN PLL driver by adding the symbols to
Kconfig and Makefile.
Fixes: 468975a985ab ("qualcommax: ipq50xx: backport upstreamed patches for adding ipq5018 CMN PLL support")
Signed-off-by: George Moussalem <george.moussalem at outlook.com>
Link: https://github.com/openwrt/openwrt/pull/21453
Signed-off-by: Robert Marko <robimarko at gmail.com>
---
...s-clock-qcom-Add-CMN-PLL-clock-controller.patch | 132 +++++++++++++++++++++
...-PLL-clock-controller-driver-for-IPQ-SoC.patch} | 38 +++++-
...-qcom-Add-CMN-PLL-support-for-IPQ5424-SoC.patch | 57 +++++++++
...-clk-qcom-cmnpll-Add-IPQ5424-SoC-support.patch} | 0
...qcom-Add-CMN-PLL-support-for-IPQ5018-SoC.patch} | 0
...qcom-ipq-cmn-pll-Add-IPQ5018-SoC-support.patch} | 0
...v6.18-arm64-dts-ipq5018-Add-CMN-PLL-node.patch} | 0
...8-xo_board_clk-to-use-fixed-factor-clock.patch} | 0
...arm64-dts-qcom-ipq5018-add-QUP3-I2C-node.patch} | 0
...m64-dts-qcom-ipq5018-add-QUP1-UART2-node.patch} | 0
10 files changed, 222 insertions(+), 5 deletions(-)
diff --git a/target/linux/qualcommax/patches-6.12/0063-v6.14-dt-bindings-clock-qcom-Add-CMN-PLL-clock-controller.patch b/target/linux/qualcommax/patches-6.12/0063-v6.14-dt-bindings-clock-qcom-Add-CMN-PLL-clock-controller.patch
new file mode 100644
index 0000000000..01312eb5d1
--- /dev/null
+++ b/target/linux/qualcommax/patches-6.12/0063-v6.14-dt-bindings-clock-qcom-Add-CMN-PLL-clock-controller.patch
@@ -0,0 +1,132 @@
+From c0f1cbf795095c21b92a46fa1dc47a7b787ce538 Mon Sep 17 00:00:00 2001
+From: Luo Jie <quic_luoj at quicinc.com>
+Date: Fri, 3 Jan 2025 15:31:34 +0800
+Subject: [PATCH] dt-bindings: clock: qcom: Add CMN PLL clock controller for
+ IPQ SoC
+
+The CMN PLL controller provides clocks to networking hardware blocks
+and to GCC on Qualcomm IPQ9574 SoC. It receives input clock from the
+on-chip Wi-Fi, and produces output clocks at fixed rates. These output
+rates are predetermined, and are unrelated to the input clock rate.
+The primary purpose of CMN PLL is to supply clocks to the networking
+hardware such as PPE (packet process engine), PCS and the externally
+connected switch or PHY device. The CMN PLL block also outputs fixed
+rate clocks to GCC, such as 24 MHZ as XO clock and 32 KHZ as sleep
+clock supplied to GCC.
+
+Signed-off-by: Luo Jie <quic_luoj at quicinc.com>
+Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski at linaro.org>
+Link: https://lore.kernel.org/r/20250103-qcom_ipq_cmnpll-v8-1-c89fb4d4849d@quicinc.com
+Signed-off-by: Bjorn Andersson <andersson at kernel.org>
+---
+ .../bindings/clock/qcom,ipq9574-cmn-pll.yaml | 77 +++++++++++++++++++
+ include/dt-bindings/clock/qcom,ipq-cmn-pll.h | 22 ++++++
+ 2 files changed, 99 insertions(+)
+ create mode 100644 Documentation/devicetree/bindings/clock/qcom,ipq9574-cmn-pll.yaml
+ create mode 100644 include/dt-bindings/clock/qcom,ipq-cmn-pll.h
+
+--- /dev/null
++++ b/Documentation/devicetree/bindings/clock/qcom,ipq9574-cmn-pll.yaml
+@@ -0,0 +1,77 @@
++# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
++%YAML 1.2
++---
++$id: http://devicetree.org/schemas/clock/qcom,ipq9574-cmn-pll.yaml#
++$schema: http://devicetree.org/meta-schemas/core.yaml#
++
++title: Qualcomm CMN PLL Clock Controller on IPQ SoC
++
++maintainers:
++ - Bjorn Andersson <andersson at kernel.org>
++ - Luo Jie <quic_luoj at quicinc.com>
++
++description:
++ The CMN (or common) PLL clock controller expects a reference
++ input clock. This reference clock is from the on-board Wi-Fi.
++ The CMN PLL supplies a number of fixed rate output clocks to
++ the devices providing networking functions and to GCC. These
++ networking hardware include PPE (packet process engine), PCS
++ and the externally connected switch or PHY devices. The CMN
++ PLL block also outputs fixed rate clocks to GCC. The PLL's
++ primary function is to enable fixed rate output clocks for
++ networking hardware functions used with the IPQ SoC.
++
++properties:
++ compatible:
++ enum:
++ - qcom,ipq9574-cmn-pll
++
++ reg:
++ maxItems: 1
++
++ clocks:
++ items:
++ - description: The reference clock. The supported clock rates include
++ 25000000, 31250000, 40000000, 48000000, 50000000 and 96000000 HZ.
++ - description: The AHB clock
++ - description: The SYS clock
++ description:
++ The reference clock is the source clock of CMN PLL, which is from the
++ Wi-Fi. The AHB and SYS clocks must be enabled to access CMN PLL
++ clock registers.
++
++ clock-names:
++ items:
++ - const: ref
++ - const: ahb
++ - const: sys
++
++ "#clock-cells":
++ const: 1
++
++required:
++ - compatible
++ - reg
++ - clocks
++ - clock-names
++ - "#clock-cells"
++
++additionalProperties: false
++
++examples:
++ - |
++ #include <dt-bindings/clock/qcom,ipq-cmn-pll.h>
++ #include <dt-bindings/clock/qcom,ipq9574-gcc.h>
++
++ cmn_pll: clock-controller at 9b000 {
++ compatible = "qcom,ipq9574-cmn-pll";
++ reg = <0x0009b000 0x800>;
++ clocks = <&cmn_pll_ref_clk>,
++ <&gcc GCC_CMN_12GPLL_AHB_CLK>,
++ <&gcc GCC_CMN_12GPLL_SYS_CLK>;
++ clock-names = "ref", "ahb", "sys";
++ #clock-cells = <1>;
++ assigned-clocks = <&cmn_pll CMN_PLL_CLK>;
++ assigned-clock-rates-u64 = /bits/ 64 <12000000000>;
++ };
++...
+--- /dev/null
++++ b/include/dt-bindings/clock/qcom,ipq-cmn-pll.h
+@@ -0,0 +1,22 @@
++/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
++/*
++ * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
++ */
++
++#ifndef _DT_BINDINGS_CLK_QCOM_IPQ_CMN_PLL_H
++#define _DT_BINDINGS_CLK_QCOM_IPQ_CMN_PLL_H
++
++/* CMN PLL core clock. */
++#define CMN_PLL_CLK 0
++
++/* The output clocks from CMN PLL of IPQ9574. */
++#define XO_24MHZ_CLK 1
++#define SLEEP_32KHZ_CLK 2
++#define PCS_31P25MHZ_CLK 3
++#define NSS_1200MHZ_CLK 4
++#define PPE_353MHZ_CLK 5
++#define ETH0_50MHZ_CLK 6
++#define ETH1_50MHZ_CLK 7
++#define ETH2_50MHZ_CLK 8
++#define ETH_25MHZ_CLK 9
++#endif
diff --git a/target/linux/qualcommax/patches-6.12/0063-v6.14-clk-qcom-Add-CMN-PLL-clock-controller-driver-for-IPQ-SoC.patch b/target/linux/qualcommax/patches-6.12/0064-v6.14-clk-qcom-Add-CMN-PLL-clock-controller-driver-for-IPQ-SoC.patch
similarity index 91%
rename from target/linux/qualcommax/patches-6.12/0063-v6.14-clk-qcom-Add-CMN-PLL-clock-controller-driver-for-IPQ-SoC.patch
rename to target/linux/qualcommax/patches-6.12/0064-v6.14-clk-qcom-Add-CMN-PLL-clock-controller-driver-for-IPQ-SoC.patch
index 7317a13edc..350e8eeabb 100644
--- a/target/linux/qualcommax/patches-6.12/0063-v6.14-clk-qcom-Add-CMN-PLL-clock-controller-driver-for-IPQ-SoC.patch
+++ b/target/linux/qualcommax/patches-6.12/0064-v6.14-clk-qcom-Add-CMN-PLL-clock-controller-driver-for-IPQ-SoC.patch
@@ -1,7 +1,7 @@
From f81715a4c87c3b75ca2640bb61b6c66506061a64 Mon Sep 17 00:00:00 2001
From: Luo Jie <quic_luoj at quicinc.com>
Date: Fri, 3 Jan 2025 15:31:35 +0800
-Subject: clk: qcom: Add CMN PLL clock controller driver for IPQ SoC
+Subject: [PATCH] clk: qcom: Add CMN PLL clock controller driver for IPQ SoC
The CMN PLL clock controller supplies clocks to the hardware
blocks that together make up the Ethernet function on Qualcomm
@@ -26,12 +26,40 @@ Acked-by: Konrad Dybcio <konrad.dybcio at oss.qualcomm.com>
Link: https://lore.kernel.org/r/20250103-qcom_ipq_cmnpll-v8-2-c89fb4d4849d@quicinc.com
Signed-off-by: Bjorn Andersson <andersson at kernel.org>
---
- drivers/clk/qcom/ipq-cmn-pll.c | 435 +++++++++++++++++++++++++++++++++++++++++
- 1 file changed, 435 insertions(+)
+ drivers/clk/qcom/Kconfig | 9 +
+ drivers/clk/qcom/Makefile | 1 +
+ drivers/clk/qcom/ipq-cmn-pll.c | 435 +++++++++++++++++++++++++++++++++
+ 3 files changed, 445 insertions(+)
create mode 100644 drivers/clk/qcom/ipq-cmn-pll.c
-(limited to 'drivers/clk/qcom/ipq-cmn-pll.c')
-
+--- a/drivers/clk/qcom/Kconfig
++++ b/drivers/clk/qcom/Kconfig
+@@ -190,6 +190,15 @@ config IPQ_APSS_6018
+ Say Y if you want to support CPU frequency scaling on
+ ipq based devices.
+
++config IPQ_CMN_PLL
++ tristate "IPQ CMN PLL Clock Controller"
++ help
++ Support for CMN PLL clock controller on IPQ platform. The
++ CMN PLL consumes the AHB/SYS clocks from GCC and supplies
++ the output clocks to the networking hardware and GCC blocks.
++ Say Y or M if you want to support CMN PLL clock on the IPQ
++ based devices.
++
+ config IPQ_GCC_4019
+ tristate "IPQ4019 Global Clock Controller"
+ help
+--- a/drivers/clk/qcom/Makefile
++++ b/drivers/clk/qcom/Makefile
+@@ -29,6 +29,7 @@ obj-$(CONFIG_CLK_X1E80100_TCSRCC) += tcs
+ obj-$(CONFIG_CLK_QCM2290_GPUCC) += gpucc-qcm2290.o
+ obj-$(CONFIG_IPQ_APSS_PLL) += apss-ipq-pll.o
+ obj-$(CONFIG_IPQ_APSS_6018) += apss-ipq6018.o
++obj-$(CONFIG_IPQ_CMN_PLL) += ipq-cmn-pll.o
+ obj-$(CONFIG_IPQ_GCC_4019) += gcc-ipq4019.o
+ obj-$(CONFIG_IPQ_GCC_5018) += gcc-ipq5018.o
+ obj-$(CONFIG_IPQ_GCC_5332) += gcc-ipq5332.o
--- /dev/null
+++ b/drivers/clk/qcom/ipq-cmn-pll.c
@@ -0,0 +1,435 @@
diff --git a/target/linux/qualcommax/patches-6.12/0065-v6.17-dt-bindings-clock-qcom-Add-CMN-PLL-support-for-IPQ5424-SoC.patch b/target/linux/qualcommax/patches-6.12/0065-v6.17-dt-bindings-clock-qcom-Add-CMN-PLL-support-for-IPQ5424-SoC.patch
new file mode 100644
index 0000000000..b320963036
--- /dev/null
+++ b/target/linux/qualcommax/patches-6.12/0065-v6.17-dt-bindings-clock-qcom-Add-CMN-PLL-support-for-IPQ5424-SoC.patch
@@ -0,0 +1,57 @@
+From 0c25ae62f5dc6a438b563536b5fe7fb6da3612b8 Mon Sep 17 00:00:00 2001
+From: Luo Jie <quic_luoj at quicinc.com>
+Date: Tue, 10 Jun 2025 18:35:18 +0800
+Subject: [PATCH] dt-bindings: clock: qcom: Add CMN PLL support for IPQ5424 SoC
+
+The CMN PLL block in the IPQ5424 SoC takes 48 MHZ as the reference
+input clock. The output clocks are the same as IPQ9574 SoC, except
+for the clock rate of output clocks to PPE and NSS.
+
+Also, add the new header file to export the CMN PLL output clock
+specifiers for IPQ5424 SoC.
+
+Acked-by: Rob Herring (Arm) <robh at kernel.org>
+Signed-off-by: Luo Jie <quic_luoj at quicinc.com>
+Link: https://lore.kernel.org/r/20250610-qcom_ipq5424_cmnpll-v3-1-ceada8165645@quicinc.com
+Signed-off-by: Bjorn Andersson <andersson at kernel.org>
+---
+ .../bindings/clock/qcom,ipq9574-cmn-pll.yaml | 1 +
+ .../dt-bindings/clock/qcom,ipq5424-cmn-pll.h | 22 +++++++++++++++++++
+ 2 files changed, 23 insertions(+)
+ create mode 100644 include/dt-bindings/clock/qcom,ipq5424-cmn-pll.h
+
+--- a/Documentation/devicetree/bindings/clock/qcom,ipq9574-cmn-pll.yaml
++++ b/Documentation/devicetree/bindings/clock/qcom,ipq9574-cmn-pll.yaml
+@@ -24,6 +24,7 @@ description:
+ properties:
+ compatible:
+ enum:
++ - qcom,ipq5424-cmn-pll
+ - qcom,ipq9574-cmn-pll
+
+ reg:
+--- /dev/null
++++ b/include/dt-bindings/clock/qcom,ipq5424-cmn-pll.h
+@@ -0,0 +1,22 @@
++/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
++/*
++ * Copyright (c) 2025 Qualcomm Innovation Center, Inc. All rights reserved.
++ */
++
++#ifndef _DT_BINDINGS_CLK_QCOM_IPQ5424_CMN_PLL_H
++#define _DT_BINDINGS_CLK_QCOM_IPQ5424_CMN_PLL_H
++
++/* CMN PLL core clock. */
++#define IPQ5424_CMN_PLL_CLK 0
++
++/* The output clocks from CMN PLL of IPQ5424. */
++#define IPQ5424_XO_24MHZ_CLK 1
++#define IPQ5424_SLEEP_32KHZ_CLK 2
++#define IPQ5424_PCS_31P25MHZ_CLK 3
++#define IPQ5424_NSS_300MHZ_CLK 4
++#define IPQ5424_PPE_375MHZ_CLK 5
++#define IPQ5424_ETH0_50MHZ_CLK 6
++#define IPQ5424_ETH1_50MHZ_CLK 7
++#define IPQ5424_ETH2_50MHZ_CLK 8
++#define IPQ5424_ETH_25MHZ_CLK 9
++#endif
diff --git a/target/linux/qualcommax/patches-6.12/0064-v6.17-clk-qcom-cmnpll-Add-IPQ5424-SoC-support.patch b/target/linux/qualcommax/patches-6.12/0066-v6.17-clk-qcom-cmnpll-Add-IPQ5424-SoC-support.patch
similarity index 100%
rename from target/linux/qualcommax/patches-6.12/0064-v6.17-clk-qcom-cmnpll-Add-IPQ5424-SoC-support.patch
rename to target/linux/qualcommax/patches-6.12/0066-v6.17-clk-qcom-cmnpll-Add-IPQ5424-SoC-support.patch
diff --git a/target/linux/qualcommax/patches-6.12/0065-v6.17-dt-bindings-clock-qcom-Add-CMN-PLL-support-for-IPQ5018-SoC.patch b/target/linux/qualcommax/patches-6.12/0067-v6.17-dt-bindings-clock-qcom-Add-CMN-PLL-support-for-IPQ5018-SoC.patch
similarity index 100%
rename from target/linux/qualcommax/patches-6.12/0065-v6.17-dt-bindings-clock-qcom-Add-CMN-PLL-support-for-IPQ5018-SoC.patch
rename to target/linux/qualcommax/patches-6.12/0067-v6.17-dt-bindings-clock-qcom-Add-CMN-PLL-support-for-IPQ5018-SoC.patch
diff --git a/target/linux/qualcommax/patches-6.12/0066-v6.17-clk-qcom-ipq-cmn-pll-Add-IPQ5018-SoC-support.patch b/target/linux/qualcommax/patches-6.12/0068-v6.17-clk-qcom-ipq-cmn-pll-Add-IPQ5018-SoC-support.patch
similarity index 100%
rename from target/linux/qualcommax/patches-6.12/0066-v6.17-clk-qcom-ipq-cmn-pll-Add-IPQ5018-SoC-support.patch
rename to target/linux/qualcommax/patches-6.12/0068-v6.17-clk-qcom-ipq-cmn-pll-Add-IPQ5018-SoC-support.patch
diff --git a/target/linux/qualcommax/patches-6.12/0067-v6.18-arm64-dts-ipq5018-Add-CMN-PLL-node.patch b/target/linux/qualcommax/patches-6.12/0069-v6.18-arm64-dts-ipq5018-Add-CMN-PLL-node.patch
similarity index 100%
rename from target/linux/qualcommax/patches-6.12/0067-v6.18-arm64-dts-ipq5018-Add-CMN-PLL-node.patch
rename to target/linux/qualcommax/patches-6.12/0069-v6.18-arm64-dts-ipq5018-Add-CMN-PLL-node.patch
diff --git a/target/linux/qualcommax/patches-6.12/0068-v6.18-arm64-dts-qcom-Update-IPQ5018-xo_board_clk-to-use-fixed-factor-clock.patch b/target/linux/qualcommax/patches-6.12/0070-v6.18-arm64-dts-qcom-Update-IPQ5018-xo_board_clk-to-use-fixed-factor-clock.patch
similarity index 100%
rename from target/linux/qualcommax/patches-6.12/0068-v6.18-arm64-dts-qcom-Update-IPQ5018-xo_board_clk-to-use-fixed-factor-clock.patch
rename to target/linux/qualcommax/patches-6.12/0070-v6.18-arm64-dts-qcom-Update-IPQ5018-xo_board_clk-to-use-fixed-factor-clock.patch
diff --git a/target/linux/qualcommax/patches-6.12/0069-v6.18-arm64-dts-qcom-ipq5018-add-QUP3-I2C-node.patch b/target/linux/qualcommax/patches-6.12/0071-v6.18-arm64-dts-qcom-ipq5018-add-QUP3-I2C-node.patch
similarity index 100%
rename from target/linux/qualcommax/patches-6.12/0069-v6.18-arm64-dts-qcom-ipq5018-add-QUP3-I2C-node.patch
rename to target/linux/qualcommax/patches-6.12/0071-v6.18-arm64-dts-qcom-ipq5018-add-QUP3-I2C-node.patch
diff --git a/target/linux/qualcommax/patches-6.12/0070-arm64-dts-qcom-ipq5018-add-QUP1-UART2-node.patch b/target/linux/qualcommax/patches-6.12/0072-v6.18-arm64-dts-qcom-ipq5018-add-QUP1-UART2-node.patch
similarity index 100%
rename from target/linux/qualcommax/patches-6.12/0070-arm64-dts-qcom-ipq5018-add-QUP1-UART2-node.patch
rename to target/linux/qualcommax/patches-6.12/0072-v6.18-arm64-dts-qcom-ipq5018-add-QUP1-UART2-node.patch
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