[openwrt/openwrt] realtek: pcs: fix PLL_CML_CTRL for serdes 0/1

[LEDE Commits]

robimarko pushed a commit to openwrt/openwrt.git, branch main:
https://git.openwrt.org/fdc37760684e784d7c305796c7fba4a9ef891f1c

commit fdc37760684e784d7c305796c7fba4a9ef891f1c
Author: Markus Stockhausen <markus.stockhausen at gmx.de>
AuthorDate: Mon Feb 9 20:26:07 2026 +0100

    realtek: pcs: fix PLL_CML_CTRL for serdes 0/1
    
    Setup of register PLL_CML_CTRL has two issues.
    
    - It clears out bits 4-31 due to a wrong mask
    - Setup of bits 0-3 is not generic but depends on the mode of
      serdes 0/1
    
    Fix that by relocating the code and adapting the mask. The error
    exists for longer but it has survived the pcs refactoring. Thus
    blame the corresponding refactoring commit.
    
    Fixes: b670d48 ("realtek: pcs: rtl838x: refactor imported code")
    Signed-off-by: Markus Stockhausen <markus.stockhausen at gmx.de>
    Link: https://github.com/openwrt/openwrt/pull/21956
    Signed-off-by: Robert Marko <robimarko at gmail.com>
---
 target/linux/realtek/files-6.12/drivers/net/pcs/pcs-rtl-otto.c | 10 +++-------
 1 file changed, 3 insertions(+), 7 deletions(-)

diff --git a/target/linux/realtek/files-6.12/drivers/net/pcs/pcs-rtl-otto.c b/target/linux/realtek/files-6.12/drivers/net/pcs/pcs-rtl-otto.c
index 47980913f3..33fc8b218f 100644
--- a/target/linux/realtek/files-6.12/drivers/net/pcs/pcs-rtl-otto.c
+++ b/target/linux/realtek/files-6.12/drivers/net/pcs/pcs-rtl-otto.c
@@ -492,6 +492,9 @@ static void rtpcs_generic_sds_restart_autoneg(struct rtpcs_serdes *sds)
 
 static void rtpcs_838x_sds_patch_01_qsgmii_6275b(struct rtpcs_ctrl *ctrl)
 {
+	/* CKREFBUF_S0S1 for QSGMII */
+	regmap_write_bits(ctrl->map, RTPCS_838X_PLL_CML_CTRL, 0xf, 0xf);
+
 	rtpcs_sds_write(SDS(ctrl, 0), 1, 3, 0xf46f);
 	rtpcs_sds_write(SDS(ctrl, 0), 1, 2, 0x85fa);
 	rtpcs_sds_write(SDS(ctrl, 1), 1, 2, 0x85fa);
@@ -729,18 +732,11 @@ static int rtpcs_838x_sds_patch(struct rtpcs_serdes *sds,
 
 static int rtpcs_838x_init_serdes_common(struct rtpcs_ctrl *ctrl)
 {
-	u32 val;
-
 	dev_dbg(ctrl->dev, "Init RTL838X SerDes common\n");
 
 	/* enable R/W of some protected registers */
 	regmap_write(ctrl->map, RTPCS_838X_INT_RW_CTRL, 0x3);
 
-	regmap_read(ctrl->map, RTPCS_838X_PLL_CML_CTRL, &val);
-	dev_dbg(ctrl->dev, "PLL control register: %x\n", val);
-	regmap_write_bits(ctrl->map, RTPCS_838X_PLL_CML_CTRL, 0xfffffff0,
-			  0xaaaaaaaf & 0xf);
-
 	/* power off and reset all SerDes */
 	regmap_write(ctrl->map, RTPCS_838X_SDS_CFG_REG, 0x3f);
 	regmap_write(ctrl->map, RTPCS_838X_RST_GLB_CTRL_0, 0x10); /* SW_SERDES_RST */