[openwrt/openwrt] mediatek: fix PHY autodetection on Cudy WR3000H

[LEDE Commits]

hauke pushed a commit to openwrt/openwrt.git, branch openwrt-24.10:
https://git.openwrt.org/bed6f08c36f85479448af23a0ce4ca00dd09fa8e

commit bed6f08c36f85479448af23a0ce4ca00dd09fa8e
Author: Jakub Vaněk <linuxtardis at gmail.com>
AuthorDate: Mon Jan 5 00:10:46 2026 +0100

    mediatek: fix PHY autodetection on Cudy WR3000H
    
    Newer Cudy WR3000H units have a Motorcomm YT8821 PHY instead of a
    Realtek PHY on the WAN port. Before this commit, the Motorcomm PHY
    could not be autodetected by the kernel -- the PHY would show up as
    just a generic clause 45 PHY and the proper driver would not be loaded.
    
    The cause of the detection failure likely was that the YT8821 PHY was
    held in reset during PHY detection. To fix this, move the reset GPIO
    definition to the MDIO bus level. This reset line is deasserted before
    the autodetection process, see also [1]. With this change, both Realtek
    and Motorcomm PHYs can be supported with a single device tree.
    
    [1]: https://lore.kernel.org/all/20251119134750.394655-1-horatiu.vultur@microchip.com/
    
    Signed-off-by: Jakub Vaněk <linuxtardis at gmail.com>
    Link: https://github.com/openwrt/openwrt/pull/21399
    (cherry picked from commit 02f0efd60b423b4ce9b996f7c986dd68965a50d4)
    Signed-off-by: Jakub Vaněk <linuxtardis at gmail.com>
    Link: https://github.com/openwrt/openwrt/pull/21531
    Signed-off-by: Hauke Mehrtens <hauke at hauke-m.de>
---
 target/linux/mediatek/dts/mt7981b-cudy-wr3000h-v1.dts | 10 +++++++---
 1 file changed, 7 insertions(+), 3 deletions(-)

diff --git a/target/linux/mediatek/dts/mt7981b-cudy-wr3000h-v1.dts b/target/linux/mediatek/dts/mt7981b-cudy-wr3000h-v1.dts
index 69e1098b43..530748a4c6 100644
--- a/target/linux/mediatek/dts/mt7981b-cudy-wr3000h-v1.dts
+++ b/target/linux/mediatek/dts/mt7981b-cudy-wr3000h-v1.dts
@@ -101,13 +101,17 @@
 };
 
 &mdio_bus {
+	/* We need to have the reset GPIO on the MDIO bus node,
+	 * otherwise the PHY would be held in reset during PHY detection */
+	reset-gpios = <&pio 3 GPIO_ACTIVE_LOW>;
+	reset-delay-us = <100000>;
+	reset-post-delay-us = <100000>;
 
 	phy6: ethernet-phy at 6 {
+		/* Either Realtek RTL8221B-VB-CG or Motorcomm YT8821,
+		 * depending on HW revision */
 		compatible = "ethernet-phy-ieee802.3-c45";
 		reg = <6>;
-		reset-assert-us = <100000>;
-		reset-deassert-us = <100000>;
-		reset-gpios = <&pio 3 GPIO_ACTIVE_LOW>;
 	};
 };