[openwrt/openwrt] kernel: mtd: limit Macronix lock feature to MX25L6405D only
LEDE Commits
lede-commits at lists.infradead.org
Tue Feb 3 15:56:39 PST 2026
hauke pushed a commit to openwrt/openwrt.git, branch main:
https://git.openwrt.org/43068360e6ddcdcef6ab7cee58f356c5383c80f5
commit 43068360e6ddcdcef6ab7cee58f356c5383c80f5
Author: Shiji Yang <yangshiji66 at outlook.com>
AuthorDate: Wed Jan 28 23:15:30 2026 +0800
kernel: mtd: limit Macronix lock feature to MX25L6405D only
Though most Macronix Flash support the lock feature, the generic lock
implementation is not fully compatible with the Macronix series Flash.
Enabling the lock feature globally is unsafe. These hack patches are
used to unlock the Flash of ubnt devices on the ath79 target. Rework
these patches and move it to the ath79 target to prevent the potential
risk.
Signed-off-by: Shiji Yang <yangshiji66 at outlook.com>
Link: https://github.com/openwrt/openwrt/pull/21754
Signed-off-by: Hauke Mehrtens <hauke at hauke-m.de>
---
...-macronix-locking-support-for-mx25l64-ser.patch | 49 ++++++++++++++++++++++
...465-m25p80-mx-disable-software-protection.patch | 18 --------
...td-spi-nor-locking-support-for-MX25L6405D.patch | 32 --------------
...td-spi-nor-disable-16-bit-sr-for-macronix.patch | 30 -------------
4 files changed, 49 insertions(+), 80 deletions(-)
diff --git a/target/linux/ath79/patches-6.12/450-mtd-spi-nor-macronix-locking-support-for-mx25l64-ser.patch b/target/linux/ath79/patches-6.12/450-mtd-spi-nor-macronix-locking-support-for-mx25l64-ser.patch
new file mode 100644
index 0000000000..deefe58fe7
--- /dev/null
+++ b/target/linux/ath79/patches-6.12/450-mtd-spi-nor-macronix-locking-support-for-mx25l64-ser.patch
@@ -0,0 +1,49 @@
+From: Shiji Yang <yangshiji66 at outlook.com>
+Date: Wed, 28 Jan 2026 22:50:18 +0800
+Subject: [PATCH] mtd: spi-nor: macronix: locking support for MX25L6405D
+
+Macronix MX25L6405D supports locking with four block-protection bits.
+The old revision chips only have status register 1. Hence we also have
+to clear the 16BIT_SR flag so that the SR1 can be updated correctly.
+
+Co-authored-by: Nick Hainke <vincent at systemli.org>
+Signed-off-by: Shiji Yang <yangshiji66 at outlook.com>
+---
+ drivers/mtd/spi-nor/macronix.c | 11 +++++++++++
+ 1 file changed, 11 insertions(+)
+
+--- a/drivers/mtd/spi-nor/macronix.c
++++ b/drivers/mtd/spi-nor/macronix.c
+@@ -8,6 +8,11 @@
+
+ #include "core.h"
+
++static void macronix_no_16bit_sr_default_init(struct spi_nor *nor)
++{
++ nor->flags &= ~SNOR_F_HAS_16BIT_SR;
++}
++
+ static int
+ mx25l25635_post_bfpt_fixups(struct spi_nor *nor,
+ const struct sfdp_parameter_header *bfpt_header,
+@@ -28,6 +33,10 @@ mx25l25635_post_bfpt_fixups(struct spi_n
+ return 0;
+ }
+
++static const struct spi_nor_fixups mx25l64_fixups = {
++ .default_init = macronix_no_16bit_sr_default_init,
++};
++
+ static const struct spi_nor_fixups mx25l25635_fixups = {
+ .post_bfpt = mx25l25635_post_bfpt_fixups,
+ };
+@@ -66,7 +75,9 @@ static const struct flash_info macronix_
+ .id = SNOR_ID(0xc2, 0x20, 0x17),
+ .name = "mx25l6405d",
+ .size = SZ_8M,
++ .flags = SPI_NOR_HAS_LOCK | SPI_NOR_4BIT_BP,
+ .no_sfdp_flags = SECT_4K,
++ .fixups = &mx25l64_fixups,
+ }, {
+ .id = SNOR_ID(0xc2, 0x20, 0x18),
+ .name = "mx25l12805d",
diff --git a/target/linux/generic/pending-6.12/465-m25p80-mx-disable-software-protection.patch b/target/linux/generic/pending-6.12/465-m25p80-mx-disable-software-protection.patch
deleted file mode 100644
index 5667e273f1..0000000000
--- a/target/linux/generic/pending-6.12/465-m25p80-mx-disable-software-protection.patch
+++ /dev/null
@@ -1,18 +0,0 @@
-From: Felix Fietkau <nbd at nbd.name>
-Subject: Disable software protection bits for Macronix flashes.
-
-Signed-off-by: Felix Fietkau <nbd at nbd.name>
----
- drivers/mtd/spi-nor/spi-nor.c | 1 +
- 1 file changed, 1 insertion(+)
-
---- a/drivers/mtd/spi-nor/macronix.c
-+++ b/drivers/mtd/spi-nor/macronix.c
-@@ -194,6 +194,7 @@ static int macronix_nor_late_init(struct
- {
- if (!nor->params->set_4byte_addr_mode)
- nor->params->set_4byte_addr_mode = spi_nor_set_4byte_addr_mode_en4b_ex4b;
-+ nor->flags |= SNOR_F_HAS_LOCK;
-
- return 0;
- }
diff --git a/target/linux/generic/pending-6.12/498-mtd-spi-nor-locking-support-for-MX25L6405D.patch b/target/linux/generic/pending-6.12/498-mtd-spi-nor-locking-support-for-MX25L6405D.patch
deleted file mode 100644
index 0cf5b02daf..0000000000
--- a/target/linux/generic/pending-6.12/498-mtd-spi-nor-locking-support-for-MX25L6405D.patch
+++ /dev/null
@@ -1,32 +0,0 @@
-From 8bf2ce6ea4ee840b70f55a27f80e1cd308051b13 Mon Sep 17 00:00:00 2001
-From: Nick Hainke <vincent at systemli.org>
-Date: Mon, 27 Dec 2021 00:38:13 +0100
-Subject: [PATCH 1/2] mtd: spi-nor: locking support for MX25L6405D
-
-Macronix MX25L6405D supports locking with four block-protection bits.
-Currently, the driver only sets three bits. If the bootloader does not
-sustain the flash chip in an unlocked state, the flash might be
-non-writeable. Add the corresponding flag to enable locking support with
-four bits in the status register.
-
-Tested on Nanostation M2 XM.
-
-Similar to commit 7ea40b54e83b ("mtd: spi-nor: enable locking support for
-MX25L12805D")
-
-Signed-off-by: David Bauer <mail at david-bauer.net>
-Signed-off-by: Nick Hainke <vincent at systemli.org>
----
- drivers/mtd/spi-nor/macronix.c | 3 ++-
- 1 file changed, 2 insertions(+), 1 deletion(-)
-
---- a/drivers/mtd/spi-nor/macronix.c
-+++ b/drivers/mtd/spi-nor/macronix.c
-@@ -66,6 +66,7 @@ static const struct flash_info macronix_
- .id = SNOR_ID(0xc2, 0x20, 0x17),
- .name = "mx25l6405d",
- .size = SZ_8M,
-+ .flags = SPI_NOR_HAS_LOCK | SPI_NOR_4BIT_BP,
- .no_sfdp_flags = SECT_4K,
- }, {
- .id = SNOR_ID(0xc2, 0x20, 0x18),
diff --git a/target/linux/generic/pending-6.12/499-mtd-spi-nor-disable-16-bit-sr-for-macronix.patch b/target/linux/generic/pending-6.12/499-mtd-spi-nor-disable-16-bit-sr-for-macronix.patch
deleted file mode 100644
index 5e20ef3296..0000000000
--- a/target/linux/generic/pending-6.12/499-mtd-spi-nor-disable-16-bit-sr-for-macronix.patch
+++ /dev/null
@@ -1,30 +0,0 @@
-From 245224608b5368c10407da07557e546743d3c489 Mon Sep 17 00:00:00 2001
-From: Nick Hainke <vincent at systemli.org>
-Date: Mon, 27 Dec 2021 09:33:13 +0100
-Subject: [PATCH 2/2] mtd: spi-nor: disable 16-bit-sr for macronix
-
-Macronix flash chips seem to consist of only one status register.
-These chips will not work with the "16-bit Write Status (01h) Command".
-Disable SNOR_F_HAS_16BIT_SR for all Macronix chips.
-
-Tested with MX25L6405D.
-
-Fixes: 39d1e3340c73 ("mtd: spi-nor: Fix clearing of QE bit on
-lock()/unlock()")
-
-Signed-off-by: David Bauer <mail at david-bauer.net>
-Signed-off-by: Nick Hainke <vincent at systemli.org>
----
- drivers/mtd/spi-nor/macronix.c | 1 +
- 1 file changed, 1 insertion(+)
-
---- a/drivers/mtd/spi-nor/macronix.c
-+++ b/drivers/mtd/spi-nor/macronix.c
-@@ -195,6 +195,7 @@ static int macronix_nor_late_init(struct
- {
- if (!nor->params->set_4byte_addr_mode)
- nor->params->set_4byte_addr_mode = spi_nor_set_4byte_addr_mode_en4b_ex4b;
-+ nor->flags &= ~SNOR_F_HAS_16BIT_SR;
- nor->flags |= SNOR_F_HAS_LOCK;
-
- return 0;
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