[openwrt/openwrt] mediatek: filogic: add support for AsiaRF AP7986-003
LEDE Commits
lede-commits at lists.infradead.org
Sat Sep 20 10:14:42 PDT 2025
hauke pushed a commit to openwrt/openwrt.git, branch main:
https://git.openwrt.org/8b891001f66b796392cba824fa450c341fa4cbca
commit 8b891001f66b796392cba824fa450c341fa4cbca
Author: Elwin Huang <s09289728096 at gmail.com>
AuthorDate: Wed Sep 17 09:59:46 2025 +0000
mediatek: filogic: add support for AsiaRF AP7986-003
- SoC : MediaTek MT7986AV, Quad-core 2.0 GHz ARM Cortex-A53 CPU
- RAM : DDR3 512 MiB (Micron MT41K256M16TW-107)
- Flash : SPI-NAND 128 MiB (Winbound W25N01GVZEIG)
- Ethernet : 6 ports
- LAN :
5x 10/100/1000 Mbps RJ-45 Port
- WAN :
1x 10/100/1000/2500 Mbps RJ-45 Port (MaxLinear GPY211B1VC-LN8A)
- LED : 19x LEDs (Green)
1x Power
1x Status (PWM-LED)
1x Debug (PWM-LED)
2x WiFi activity
10x Ethernet LAN activity
4x Ethernet WAN activity
- UART : 1x4 pin header on PCB [J1]
- arrangement : 3.3V, RX, TX, GND
- settings : 115200, 8n1
- Button : 3x (Reset, WPS, Power)
- WiFi : 2x
WiFi 6 2.4 Ghz + 5 Ghz (Mediatek MT7975N+MT7975PN)
- Socket :
1x Raspberry header 13x2
1x JTAG 10x2
1x USB-A (USB 3.0)
- Power : 12V DC, 3A
MAC addresses :
WLAN: 00:0A:52:xx:xx:xx (Factory, 0x6)
LAN: 00:0A:52:xx:xx:xx (Factory, 0x24)
WAN: 00:0A:52:xx:xx:xx (Factory, 0x2a)
Flash instruction through LuCI:
This device is flashed OpenWRT base firmware with this target.
The LuCI webpage is integrated in default for upgrading.
Flash instruction through u-boot:
1. Prepare the TFTP server on PC.
2. Connect uart to PC, select "2. Upgrade firmware" in u-boot menu.
3. Select "0 - TFTP client (Default)", input client IP, server IP, IP netmask, flashed bin file path
4. Wait about 20 seconds to complete flashing
Signed-off-by: Elwin Huang <s09289728096 at gmail.com>
Link: https://github.com/openwrt/openwrt/pull/20071
Signed-off-by: Hauke Mehrtens <hauke at hauke-m.de>
---
.../uboot-envtools/files/mediatek_filogic | 1 +
.../mediatek/dts/mt7986a-asiarf-ap7986-003.dts | 427 +++++++++++++++++++++
.../filogic/base-files/etc/board.d/02_network | 1 +
target/linux/mediatek/image/filogic.mk | 18 +
4 files changed, 447 insertions(+)
diff --git a/package/boot/uboot-tools/uboot-envtools/files/mediatek_filogic b/package/boot/uboot-tools/uboot-envtools/files/mediatek_filogic
index 8f75c85915..dd65d68779 100644
--- a/package/boot/uboot-tools/uboot-envtools/files/mediatek_filogic
+++ b/package/boot/uboot-tools/uboot-envtools/files/mediatek_filogic
@@ -85,6 +85,7 @@ comfast,cf-e393ax|\
iptime,ax3000m)
ubootenv_add_uci_config "/dev/mtd1" "0x0" "0x20000" "0x80000"
;;
+asiarf,ap7986-003|\
cetron,ct3003|\
edgecore,eap111|\
netgear,wax220|\
diff --git a/target/linux/mediatek/dts/mt7986a-asiarf-ap7986-003.dts b/target/linux/mediatek/dts/mt7986a-asiarf-ap7986-003.dts
new file mode 100644
index 0000000000..12c0e90c5d
--- /dev/null
+++ b/target/linux/mediatek/dts/mt7986a-asiarf-ap7986-003.dts
@@ -0,0 +1,427 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright (C) 2025 AsiaRF Co., Ltd
+ * Author: Elwin Huang <elwin at asiarf.com>
+ */
+
+/dts-v1/;
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
+#include <dt-bindings/pinctrl/mt65xx.h>
+#include "mt7986a.dtsi"
+
+/ {
+ model = "AsiaRF AP7986-003";
+ compatible = "asiarf,ap7986-003", "mediatek,mt7986a-rfb";
+
+ aliases {
+ serial0 = &uart0;
+ led-boot = &led_status_green;
+ led-failsafe = &led_status_green;
+ led-running = &led_status_green;
+ led-upgrade = &led_status_green;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory at 40000000 {
+ reg = <0 0x40000000 0 0x20000000>;
+ device_type = "memory";
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+
+ reset {
+ label = "reset";
+ linux,code = <KEY_RESTART>;
+ gpios = <&pio 9 GPIO_ACTIVE_LOW>;
+ };
+
+ wps {
+ label = "wps";
+ linux,code = <KEY_WPS_BUTTON>;
+ gpios = <&pio 10 GPIO_ACTIVE_LOW>;
+ };
+ };
+
+ pwm-leds {
+ compatible = "pwm-leds";
+
+ led_status_green: led-0 {
+ color = <LED_COLOR_ID_GREEN>;
+ function = LED_FUNCTION_STATUS;
+ pwms = <&pwm 0 10000>;
+ active-low;
+ };
+
+ led-1 {
+ color = <LED_COLOR_ID_GREEN>;
+ function = LED_FUNCTION_DEBUG;
+ pwms = <&pwm 1 10000>;
+ linux,default-trigger = "pattern";
+ led-pattern = <0 1000 255 1000>;
+ active-low;
+ };
+ };
+
+ reg_1p8v: regulator-1p8v {
+ compatible = "regulator-fixed";
+ regulator-name = "fixed-1.8V";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ reg_3p3v: regulator-3p3v {
+ compatible = "regulator-fixed";
+ regulator-name = "fixed-3.3V";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ reg_5v: regulator-5v {
+ compatible = "regulator-fixed";
+ regulator-name = "fixed-5V";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+};
+
+ð {
+ status = "okay";
+
+ gmac0: mac at 0 {
+ compatible = "mediatek,eth-mac";
+ reg = <0>;
+ phy-mode = "2500base-x";
+ nvmem-cells = <&macaddr_factory_24>;
+ nvmem-cell-names = "mac-address";
+
+ fixed-link {
+ speed = <2500>;
+ full-duplex;
+ pause;
+ };
+ };
+
+ mac at 1 {
+ compatible = "mediatek,eth-mac";
+ reg = <1>;
+ phy-handle = <&phy6>;
+ phy-mode = "2500base-x";
+ nvmem-cells = <&macaddr_factory_2a>;
+ nvmem-cell-names = "mac-address";
+ };
+
+ mdio-bus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ phy6: phy at 6 {
+ compatible = "ethernet-phy-ieee802.3-c45";
+ reg = <6>;
+
+ reset-gpios = <&pio 6 GPIO_ACTIVE_LOW>;
+ reset-deassert-us = <20000>;
+ #interrupt-cells = <1>;
+ interrupt-controller;
+ interrupt-parent = <&pio>;
+ interrupts = <46 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ switch: switch at 1f {
+ compatible = "mediatek,mt7531";
+ reg = <31>;
+ #interrupt-cells = <1>;
+ interrupt-controller;
+ interrupt-parent = <&pio>;
+ interrupts = <66 IRQ_TYPE_LEVEL_HIGH>;
+ reset-gpios = <&pio 5 GPIO_ACTIVE_HIGH>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port at 0 {
+ reg = <0>;
+ label = "lan1";
+ };
+
+ port at 1 {
+ reg = <1>;
+ label = "lan2";
+ };
+
+ port at 2 {
+ reg = <2>;
+ label = "lan3";
+ };
+
+ port at 3 {
+ reg = <3>;
+ label = "lan4";
+ };
+
+ port at 4 {
+ reg = <4>;
+ label = "lan5";
+ };
+
+ port at 6 {
+ reg = <6>;
+ ethernet = <&gmac0>;
+ phy-mode = "2500base-x";
+
+ fixed-link {
+ speed = <2500>;
+ full-duplex;
+ pause;
+ };
+ };
+ };
+ };
+ };
+};
+
+&wifi {
+ pinctrl-names = "default", "dbdc";
+ pinctrl-0 = <&wf_2g_5g_pins>;
+ pinctrl-1 = <&wf_dbdc_pins>;
+ nvmem-cells = <&eeprom_factory_0>;
+ nvmem-cell-names = "eeprom";
+ status = "okay";
+};
+
+&pcie {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pcie_pins>;
+ status = "okay";
+};
+
+&pcie_phy {
+ status = "okay";
+};
+
+&pio {
+ pcie_pins: pcie-pins {
+ mux {
+ function = "pcie";
+ groups = "pcie_clk", "pcie_wake", "pcie_pereset";
+ };
+ };
+
+ pwm_pins: pwm-pins {
+ mux {
+ function = "pwm";
+ groups = "pwm0", "pwm1_0";
+ };
+ };
+
+ spic1_pins: spi-pins-23-to-26 {
+ mux {
+ function = "spi";
+ groups = "spi1_1";
+ };
+ };
+
+ spic2_pins: spi-flash-pins-29-to-32 {
+ mux {
+ function = "spi";
+ groups = "spi1_2";
+ };
+ };
+
+ spi_flash_pins: spi-flash-pins-33-to-38 {
+ mux {
+ function = "spi";
+ groups = "spi0", "spi0_wp_hold";
+ };
+ conf-pu {
+ pins = "SPI2_CS", "SPI2_HOLD", "SPI2_WP";
+ drive-strength = <MTK_DRIVE_8mA>;
+ bias-disable; /* bias-disable */
+ };
+ conf-pd {
+ pins = "SPI2_CLK", "SPI2_MOSI", "SPI2_MISO";
+ drive-strength = <MTK_DRIVE_8mA>;
+ bias-disable; /* bias-disable */
+ };
+ };
+
+ wf_2g_5g_pins: wf_2g_5g-pins {
+ mux {
+ function = "wifi";
+ groups = "wf_2g", "wf_5g";
+ };
+ conf {
+ pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4",
+ "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6",
+ "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10",
+ "WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1",
+ "WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0",
+ "WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8",
+ "WF1_TOP_CLK", "WF1_TOP_DATA";
+ drive-strength = <MTK_DRIVE_4mA>;
+ };
+ };
+
+ wf_dbdc_pins: wf_dbdc-pins {
+ mux {
+ function = "wifi";
+ groups = "wf_dbdc";
+ };
+ conf {
+ pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4",
+ "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6",
+ "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10",
+ "WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1",
+ "WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0",
+ "WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8",
+ "WF1_TOP_CLK", "WF1_TOP_DATA";
+ drive-strength = <MTK_DRIVE_4mA>;
+ };
+ };
+
+ i2c_pins: i2c-pins {
+ mux {
+ function = "i2c";
+ groups = "i2c";
+ };
+ };
+};
+
+&spi0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&spi_flash_pins>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "okay";
+
+ spi_nand at 1 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "spi-nand";
+ reg = <1>;
+ spi-max-frequency = <52000000>;
+ spi-tx-bus-width = <4>;
+ spi-rx-bus-width = <4>;
+
+ mediatek,nmbm;
+ mediatek,bmt-max-ratio = <1>;
+ mediatek,bmt-max-reserved-blocks = <64>;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition at 0 {
+ label = "BL2";
+ reg = <0x00000 0x0100000>;
+ read-only;
+ };
+
+ partition at 100000 {
+ label = "u-boot-env";
+ reg = <0x0100000 0x0080000>;
+ };
+
+ partition at 180000 {
+ label = "Factory";
+ reg = <0x0180000 0x0200000>;
+ read-only;
+
+ nvmem-layout {
+ compatible = "fixed-layout";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ eeprom_factory_0: eeprom at 0 {
+ reg = <0x0 0x1000>;
+ };
+
+ macaddr_factory_24: macaddr at 24 {
+ reg = <0x24 0x6>;
+ };
+
+ macaddr_factory_2a: macaddr at 2a {
+ reg = <0x2a 0x6>;
+ };
+ };
+ };
+
+ partition at 380000 {
+ label = "FIP";
+ reg = <0x0380000 0x0200000>;
+ };
+
+ partition at 580000 {
+ label = "ubi";
+ reg = <0x0580000 0x4000000>; // 64MB
+ };
+
+ partition at 4580000 {
+ label = "User_data";
+ reg = <0x4580000 0x3280000>;
+ };
+ };
+ };
+};
+
+&spi1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&spic1_pins &spic2_pins>;
+ cs-gpios = <&pio 26 GPIO_ACTIVE_LOW>, <&pio 32 GPIO_ACTIVE_LOW>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "okay";
+};
+
+&i2c0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c_pins>;
+ status = "okay";
+};
+
+&uart0 {
+ status = "okay";
+};
+
+&ssusb {
+ phys = <&u3port0 PHY_TYPE_USB3>,
+ <&u2port1 PHY_TYPE_USB2>;
+ vusb33-supply = <®_3p3v>;
+ vbus-supply = <®_5v>;
+ status = "okay";
+};
+
+&usb_phy {
+ status = "okay";
+};
+
+&watchdog {
+ status = "okay";
+};
+
+&trng {
+ status = "okay";
+};
+
+&crypto {
+ status = "okay";
+};
+
+&pwm {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pwm_pins>;
+ status = "okay";
+};
diff --git a/target/linux/mediatek/filogic/base-files/etc/board.d/02_network b/target/linux/mediatek/filogic/base-files/etc/board.d/02_network
index a8c4565af0..a7289b91df 100644
--- a/target/linux/mediatek/filogic/base-files/etc/board.d/02_network
+++ b/target/linux/mediatek/filogic/base-files/etc/board.d/02_network
@@ -68,6 +68,7 @@ mediatek_setup_interfaces()
zbtlink,zbt-z8102ax-v2)
ucidef_set_interfaces_lan_wan "lan1 lan2 lan3 lan4" eth1
;;
+ asiarf,ap7986-003|\
asus,tuf-ax6000|\
glinet,gl-mt6000|\
tplink,tl-xdr4288|\
diff --git a/target/linux/mediatek/image/filogic.mk b/target/linux/mediatek/image/filogic.mk
index 3bdb20c0ea..b97586e094 100644
--- a/target/linux/mediatek/image/filogic.mk
+++ b/target/linux/mediatek/image/filogic.mk
@@ -225,6 +225,24 @@ define Device/acer_vero-w6m
endef
TARGET_DEVICES += acer_vero-w6m
+define Device/asiarf_ap7986-003
+ DEVICE_VENDOR := AsiaRF
+ DEVICE_MODEL := AP7986 003
+ DEVICE_DTS := mt7986a-asiarf-ap7986-003
+ DEVICE_DTS_DIR := ../dts
+ DEVICE_PACKAGES := kmod-usb3 kmod-mt7915e kmod-mt7986-firmware mt7986-wo-firmware
+ UBINIZE_OPTS := -E 5
+ BLOCKSIZE := 128k
+ PAGESIZE := 2048
+ IMAGE_SIZE := 65536k
+ KERNEL_IN_UBI := 1
+ IMAGES += factory.bin
+ IMAGE/factory.bin := append-ubi | check-size $$$$(IMAGE_SIZE)
+ IMAGE/sysupgrade.bin := sysupgrade-tar | append-metadata
+ KERNEL := kernel-bin | lzma | fit lzma $$(KDIR)/image-$$(firstword $$(DEVICE_DTS)).dtb
+endef
+TARGET_DEVICES += asiarf_ap7986-003
+
define Device/adtran_smartrg
DEVICE_VENDOR := Adtran
DEVICE_DTS_DIR := ../dts
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