[openwrt/openwrt] mediatek: add support for AsiaRF AP7622-WH1
LEDE Commits
lede-commits at lists.infradead.org
Thu Sep 18 14:30:02 PDT 2025
hauke pushed a commit to openwrt/openwrt.git, branch main:
https://git.openwrt.org/73e04e24641d7bda62cecc95e9f09e5bf38a67ff
commit 73e04e24641d7bda62cecc95e9f09e5bf38a67ff
Author: Elwin Huang <s09289728096 at gmail.com>
AuthorDate: Fri Sep 5 21:37:32 2025 +0800
mediatek: add support for AsiaRF AP7622-WH1
- SoC : MediaTek MT7622A, dual-core 1.35 Ghz ARM Cortex-A53 CPU
- RAM : DDR3 512 MiB (Nanya NT5CC256M16ER-EKI)
- Flash : SPI-NAND 128 MiB (Winbond W25N01GVZEIG)
- Ethernet : 5 port Switch
- LAN :
4x 10/100/1000 Mbps RJ-45 Port
- WAN :
1x 10/100/1000 Mbps RJ-45 Port
- LED : 10x LEDs
1x Power (Blue, GPIO)
1x WiFi (Green, GPIO)
2x MiniPCIe (Orange)
1x M.2 B Key (Red)
5x Ethernet activity (White)
- UART : 1x4 pin header on PCB [J19]
- arrangement : 3.3V, TX, RX, GND
- settings : 115200, 8n1
- Button : 2x (Reset, WPS)
- GPS : 1x (Quectel L76-L)
- WiFi : 2x
WiFi 4 (MediaTek MT7622A)
WiFI HaLow (AsiaRF MM610X-001)
- BT : BT 4.2/BLE 5.0 (MediaTek MT7622A)
- Socket :
2x MiniPCIe (PCIe Gen2 + USB 2.0) with extra SPI interface (NI)
1x M.2 B key (USB 3.0)
1x SIM Card
1x USB-A (USB 2.0)
- Power : 12V DC, 1A
MAC addresses :
WLAN: 00:0A:52:xx:xx:xx (Factory, 0x6)
LAN: 00:0A:52:xx:xx:xx (Factory, 0x7fff4)
WAN: 00:0A:52:xx:xx:xx (Factory, 0x7fffa)
Note: To use SPI interface on mPCIe slot, weld 4x 0402 0R resistors on [R832-835] or [R960-963]
mPCIe mapping:
45# - SPI_CLK
47# - SPI_MISO
49# - SPI_MOSI
51# - SPI_CSN
Flash instruction through LuCI:
This device is flashed OpenWRT base firmware with this target.
The LuCI webpage is integrated in default for upgrading.
Flash instruction through u-boot:
1. Prepare the TFTP server on PC.
2. Connect uart to PC, select "2. System Load Linux Kernel then write to Flash via TFTP." in u-boot menu.
3. input flashed bin file path, server IP, client IP
4. Wait about 20 seconds to complete flashing
Signed-off-by: Elwin Huang <s09289728096 at gmail.com>
Link: https://github.com/openwrt/openwrt/pull/19962
Signed-off-by: Hauke Mehrtens <hauke at hauke-m.de>
---
.../uboot-envtools/files/mediatek_mt7622 | 3 +
.../mediatek/dts/mt7622-asiarf-ap7622-wh1.dts | 515 +++++++++++++++++++++
target/linux/mediatek/image/mt7622.mk | 19 +
3 files changed, 537 insertions(+)
diff --git a/package/boot/uboot-tools/uboot-envtools/files/mediatek_mt7622 b/package/boot/uboot-tools/uboot-envtools/files/mediatek_mt7622
index 1ba1019fab..8a053e1cad 100644
--- a/package/boot/uboot-tools/uboot-envtools/files/mediatek_mt7622
+++ b/package/boot/uboot-tools/uboot-envtools/files/mediatek_mt7622
@@ -17,6 +17,9 @@ ubootenv_add_mmc_default() {
board=$(board_name)
case "$board" in
+asiarf,ap7622-wh1)
+ ubootenv_add_uci_config "/dev/mtd3" "0x0" "0x1000" "0x10000"
+ ;;
dlink,eagle-pro-ai-m32-a1|\
dlink,eagle-pro-ai-r32-a1)
ubootenv_add_uci_config "/dev/mtd3" "0x0" "0x2000" "0x2000"
diff --git a/target/linux/mediatek/dts/mt7622-asiarf-ap7622-wh1.dts b/target/linux/mediatek/dts/mt7622-asiarf-ap7622-wh1.dts
new file mode 100644
index 0000000000..a6750dbf8c
--- /dev/null
+++ b/target/linux/mediatek/dts/mt7622-asiarf-ap7622-wh1.dts
@@ -0,0 +1,515 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright (C) 2025 AsiaRF Co., Ltd
+ * Author: Elwin Huang <elwin at asiarf.com>
+ */
+
+/dts-v1/;
+#include "mt7622.dtsi"
+#include "mt6380.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
+
+/ {
+ model = "AsiaRF AP7622 WH1";
+ compatible = "asiarf,ap7622-wh1", "mediatek,mt7622";
+
+ aliases {
+ serial0 = &uart0;
+ led-boot = &led_power;
+ led-failsafe = &led_power;
+ led-running = &led_power;
+ led-upgrade = &led_power;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ bootargs = "earlycon=uart8250,mmio32,0x11002000 console=ttyS0,115200n8 swiotlb=512";
+ };
+
+ cpus {
+ cpu at 0 {
+ proc-supply = <&mt6380_vcpu_reg>;
+ sram-supply = <&mt6380_vm_reg>;
+ };
+
+ cpu at 1 {
+ proc-supply = <&mt6380_vcpu_reg>;
+ sram-supply = <&mt6380_vm_reg>;
+ };
+ };
+
+ mmc1_pwrseq: mmc1_pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ reset-gpios = <&pio 97 GPIO_ACTIVE_LOW>;
+ post-power-on-delay-ms = <200>;
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+
+ reset {
+ label = "reset";
+ linux,code = <KEY_RESTART>;
+ gpios = <&pio 0 GPIO_ACTIVE_LOW>;
+ };
+
+ wps {
+ label = "wps";
+ linux,code = <KEY_WPS_BUTTON>;
+ gpios = <&pio 102 GPIO_ACTIVE_LOW>;
+ };
+ };
+
+ memory at 40000000 {
+ reg = <0 0x40000000 0 0x20000000>;// 512MiB
+ device_type = "memory";
+ };
+
+ reg_3p3v: regulator-3p3v {
+ compatible = "regulator-fixed";
+ regulator-name = "fixed-3.3V";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ reg_5v: regulator-5v {
+ compatible = "regulator-fixed";
+ regulator-name = "fixed-5V";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ gpio-leds {
+ compatible = "gpio-leds";
+ status = "okay";
+
+ led_power: power {
+ color = <LED_COLOR_ID_BLUE>;
+ function = LED_FUNCTION_POWER;
+ gpios = <&pio 101 GPIO_ACTIVE_HIGH>;
+ };
+
+ wlan {
+ color = <LED_COLOR_ID_GREEN>;
+ function = LED_FUNCTION_WLAN;
+ gpios = <&pio 85 GPIO_ACTIVE_LOW>;
+ linux,default-trigger = "phy0tpt";
+ };
+ };
+};
+
+&bch {
+ status = "okay";
+};
+
+&rtc {
+ status = "disabled";
+};
+
+ð {
+ pinctrl-names = "default";
+ pinctrl-0 = <ð_pins>;
+ status = "okay";
+
+ gmac0: mac at 0 {
+ compatible = "mediatek,eth-mac";
+ nvmem-cells = <&macaddr_factory_7fff4>;
+ nvmem-cell-names = "mac-address";
+ reg = <0>;
+ phy-mode = "2500base-x";
+
+ fixed-link {
+ speed = <2500>;
+ full-duplex;
+ pause;
+ };
+ };
+
+ mdio-bus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ switch at 1f {
+ compatible = "mediatek,mt7531";
+ reg = <31>;
+ #interrupt-cells = <1>;
+ interrupt-controller;
+ interrupt-parent = <&pio>;
+ interrupts = <53 IRQ_TYPE_LEVEL_HIGH>;
+ reset-gpios = <&pio 54 GPIO_ACTIVE_HIGH>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port at 0 {
+ reg = <0>;
+ label = "lan1";
+ };
+
+ port at 1 {
+ reg = <1>;
+ label = "lan2";
+ };
+
+ port at 2 {
+ reg = <2>;
+ label = "lan3";
+ };
+
+ port at 3 {
+ reg = <3>;
+ label = "lan4";
+ };
+
+ port at 4 {
+ reg = <4>;
+ label = "wan";
+ nvmem-cells = <&macaddr_factory_7fffa>;
+ nvmem-cell-names = "mac-address";
+ };
+
+ port at 6 {
+ reg = <6>;
+ label = "cpu";
+ ethernet = <&gmac0>;
+ phy-mode = "2500base-x";
+
+ fixed-link {
+ speed = <2500>;
+ full-duplex;
+ pause;
+ };
+ };
+ };
+ };
+
+ };
+};
+
+&mmc1 {
+ pinctrl-names = "default", "state_uhs";
+ pinctrl-0 = <&sd0_pins_default>;
+ pinctrl-1 = <&sd0_pins_uhs>;
+ status = "okay";
+ bus-width = <4>;
+ max-frequency = <50000000>;
+ cap-sd-highspeed;
+ vmmc-supply = <®_3p3v>;
+ vqmmc-supply = <®_3p3v>;
+ assigned-clocks = <&topckgen CLK_TOP_MSDC30_1_SEL>;
+ assigned-clock-parents = <&topckgen CLK_TOP_UNIV48M>;
+
+ cap-mmc-highspeed;
+ cap-sdio-irq;
+ non-removable;
+ disable-wp;
+ drv-type = <2>;
+ mmc-pwrseq = <&mmc1_pwrseq>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+ mm6108_sdio at 0 {
+ compatible = "morse,mm610x";
+ reset-gpios = <&pio 97 GPIO_ACTIVE_HIGH>;
+ power-gpios = <&pio 98 GPIO_ACTIVE_HIGH>,
+ <&pio 99 GPIO_ACTIVE_HIGH>;
+ status = "okay";
+ reg = <2>;
+ bus-width = <4>;
+ };
+};
+
+&pcie0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pcie0_pins>;
+ status = "okay";
+};
+
+&pcie1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pcie1_pins>;
+ status = "okay";
+};
+
+&pio {
+ eth_pins: eth-pins {
+ mux {
+ function = "eth";
+ groups = "mdc_mdio", "rgmii_via_gmac2";
+ };
+ };
+
+ pcie0_pins: pcie0-pins {
+ mux {
+ function = "pcie";
+ groups = "pcie0_pad_perst",
+ "pcie0_1_waken",
+ "pcie0_1_clkreq";
+ };
+ };
+
+ pcie1_pins: pcie1-pins {
+ mux {
+ function = "pcie";
+ groups = "pcie1_pad_perst",
+ "pcie1_0_waken",
+ "pcie1_0_clkreq";
+ };
+ };
+
+ pmic_bus_pins: pmic-bus-pins {
+ mux {
+ function = "pmic";
+ groups = "pmic_bus";
+ };
+ };
+
+ wled_pins: wled-pins {
+ mux {
+ function = "led";
+ groups = "wled";
+ };
+ };
+
+ sd0_pins_default: sd0-pins-default {
+ mux {
+ function = "sd";
+ groups = "sd_0";
+ };
+
+ /* "I2S2_OUT, "I2S4_IN"", "I2S3_IN", "I2S2_IN",
+ * "I2S4_OUT", "I2S3_OUT" are used as DAT0, DAT1,
+ * DAT2, DAT3, CMD, CLK for SD respectively.
+ */
+ conf-cmd-data {
+ pins = "I2S2_OUT", "I2S4_IN", "I2S3_IN",
+ "I2S2_IN","I2S4_OUT";
+ input-enable;
+ drive-strength = <8>;
+ bias-pull-up;
+ };
+ conf-clk {
+ pins = "I2S3_OUT";
+ drive-strength = <12>;
+ bias-pull-down;
+ };
+ conf-cd {
+ pins = "TXD3";
+ bias-pull-up;
+ };
+ };
+
+ sd0_pins_uhs: sd0-pins-uhs {
+ mux {
+ function = "sd";
+ groups = "sd_0";
+ };
+
+ conf-cmd-data {
+ pins = "I2S2_OUT", "I2S4_IN", "I2S3_IN",
+ "I2S2_IN","I2S4_OUT";
+ input-enable;
+ bias-pull-up;
+ };
+
+ conf-clk {
+ pins = "I2S3_OUT";
+ bias-pull-down;
+ };
+ };
+
+ /* Serial NAND is shared pin with SPI-NOR */
+ serial_nand_pins: serial-nand-pins {
+ mux {
+ function = "flash";
+ groups = "snfi";
+ };
+ };
+
+ spic0_pins: spic0-pins {
+ mux {
+ function = "spi";
+ groups = "spic0_0";
+ };
+ };
+
+ spic1_pins: spic1-pins {
+ mux {
+ function = "spi";
+ groups = "spic1_0";
+ };
+ };
+
+ uart0_pins: uart0-pins {
+ mux {
+ function = "uart";
+ groups = "uart0_0_tx_rx";
+ };
+ };
+
+ uart2_pins: uart2-pins {
+ mux {
+ function = "uart";
+ groups = "uart2_1_tx_rx";
+ };
+ };
+
+ watchdog_pins: watchdog-pins {
+ mux {
+ function = "watchdog";
+ groups = "watchdog";
+ };
+ };
+};
+
+&pwrap {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pmic_bus_pins>;
+ status = "okay";
+};
+
+&snfi {
+ pinctrl-names = "default";
+ pinctrl-0 = <&serial_nand_pins>;
+ status = "okay";
+
+ flash at 0 {
+ compatible = "spi-nand";
+ mediatek,bmt-table-size = <0x1000>;
+ mediatek,bmt-v2;
+ nand-ecc-engine = <&snfi>;
+ reg = <0>;
+ spi-rx-bus-width = <4>;
+ spi-tx-bus-width = <4>;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition at 0 {
+ label = "Preloader";
+ reg = <0x00000 0x0080000>;
+ read-only;
+ };
+
+ partition at 80000 {
+ label = "ATF";
+ reg = <0x80000 0x0040000>;
+ read-only;
+ };
+
+ partition at c0000 {
+ label = "Bootloader";
+ reg = <0xc0000 0x0080000>;
+ read-only;
+ };
+
+ partition at 140000 {
+ label = "Config";
+ reg = <0x140000 0x0080000>;
+ };
+
+ partition at 1c0000 {
+ label = "Factory";
+ reg = <0x1c0000 0x0100000>;
+ read-only;
+
+ nvmem-layout {
+ compatible = "fixed-layout";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ factory_eeprom: eeprom at 0 {
+ reg = <0x0 0x5000>;
+ };
+
+ macaddr_factory_7fff4: macaddr at 7fff4 {
+ reg = <0x7fff4 0x6>;
+ };
+
+ macaddr_factory_7fffa: macaddr at 7fffa {
+ reg = <0x7fffa 0x6>;
+ };
+ };
+ };
+
+ partition at 2c0000 {
+ label = "firmware";
+ reg = <0x2c0000 0x2000000>;// 32 MiB
+
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition at 0 {
+ label = "kernel";
+ reg = <0x0 0x0800000>;
+ };
+
+ partition at 600000 {
+ label = "ubi";
+ reg = <0x800000 0x1800000>;
+ };
+ };
+
+ partition at 22c0000 {
+ label = "User_data";
+ reg = <0x22c0000 0x5300000>;
+ };
+ };
+ };
+};
+
+&spi0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&spic0_pins>;
+ status = "okay";
+};
+
+&spi1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&spic1_pins>;
+ status = "okay";
+};
+
+&ssusb {
+ vusb33-supply = <®_3p3v>;
+ vbus-supply = <®_5v>;
+ status = "okay";
+};
+
+&u3phy {
+ status = "okay";
+};
+
+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_pins>;
+ status = "okay";
+};
+
+&uart2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart2_pins>;
+ status = "okay";
+};
+
+&watchdog {
+ pinctrl-names = "default";
+ pinctrl-0 = <&watchdog_pins>;
+ status = "okay";
+};
+
+&wmac {
+ nvmem-cells = <&factory_eeprom>;
+ nvmem-cell-names = "eeprom";
+ status = "okay";
+};
diff --git a/target/linux/mediatek/image/mt7622.mk b/target/linux/mediatek/image/mt7622.mk
index f13b7086f1..e45c064046 100644
--- a/target/linux/mediatek/image/mt7622.mk
+++ b/target/linux/mediatek/image/mt7622.mk
@@ -52,6 +52,25 @@ define Build/mt7622-gpt
rm $@.tmp
endef
+define Device/asiarf_ap7622-wh1
+ DEVICE_VENDOR := AsiaRF
+ DEVICE_MODEL := AP7622-WH1
+ DEVICE_DTS := mt7622-asiarf-ap7622-wh1
+ DEVICE_DTS_DIR := ../dts
+ DEVICE_PACKAGES := kmod-ata-ahci-mtk kmod-btmtkuart kmod-usb3
+ BOARD_NAME := asiarf,ap7622-wh1
+ UBINIZE_OPTS := -E 5
+ BLOCKSIZE := 128k
+ PAGESIZE := 2048
+ KERNEL_SIZE := 8192k
+ IMAGE_SIZE := 32768k
+ IMAGES += factory.bin
+ IMAGE/factory.bin := append-kernel | pad-to $$(KERNEL_SIZE) | \
+ append-ubi | check-size
+ IMAGE/sysupgrade.bin := sysupgrade-tar | append-metadata
+endef
+TARGET_DEVICES += asiarf_ap7622-wh1
+
define Device/smartrg_sdg-841-t6
DEVICE_VENDOR := Adtran
DEVICE_DTS_DIR := ../dts
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