[openwrt/openwrt] qualcommax: ipq50xx: backport upstreamed patches for adding ipq5018 GE PHY support
LEDE Commits
lede-commits at lists.infradead.org
Mon Sep 15 01:29:47 PDT 2025
robimarko pushed a commit to openwrt/openwrt.git, branch main:
https://git.openwrt.org/0465daed5d6fe1da96eaa4681f41e522db176a24
commit 0465daed5d6fe1da96eaa4681f41e522db176a24
Author: George Moussalem <george.moussalem at outlook.com>
AuthorDate: Tue Aug 19 16:39:06 2025 +0400
qualcommax: ipq50xx: backport upstreamed patches for adding ipq5018 GE PHY support
Use upstreamed patch for adding driver support and the the mdio and phy
nodes.
Signed-off-by: George Moussalem <george.moussalem at outlook.com>
Link: https://github.com/openwrt/openwrt/pull/19890
Signed-off-by: Robert Marko <robimarko at gmail.com>
---
target/linux/qualcommax/ipq50xx/config-default | 1 -
...17-clk-qcom-gcc-ipq5018-fix-GE-PHY-reset.patch} | 15 +--
...dd-Qualcomm-IPQ5018-Internal-PHY-support.patch} | 104 +++++++--------------
...18-arm64-dts-qcom-ipq5018-Add-MDIO-buses.patch} | 22 ++---
...-ipq5018-Add-GE-PHY-to-internal-mdio-bus.patch} | 26 +++---
.../0306-arm64-dts-qcom-ipq5018-Add-PWM-node.patch | 2 +-
...4-arm64-dts-qcom-ipq5018-Add-crypto-nodes.patch | 2 +-
...0337-arm64-dts-qcom-ipq5018-Add-PRNG-node.patch | 2 +-
...rm64-dts-qcom-ipq5018-Add-QUP1-UART2-node.patch | 2 +-
...-arm64-dts-qcom-ipq5018-Add-QUP3-I2C-node.patch | 2 +-
...-arm64-dts-qcom-ipq5018-Add-SPI-nand-node.patch | 2 +-
...64-dts-qcom-ipq5018-Add-ethernet-cmn-node.patch | 6 +-
12 files changed, 76 insertions(+), 110 deletions(-)
diff --git a/target/linux/qualcommax/ipq50xx/config-default b/target/linux/qualcommax/ipq50xx/config-default
index 95cd5eb88d..ac32263637 100644
--- a/target/linux/qualcommax/ipq50xx/config-default
+++ b/target/linux/qualcommax/ipq50xx/config-default
@@ -1,7 +1,6 @@
CONFIG_GPIO_WATCHDOG=y
# CONFIG_GPIO_WATCHDOG_ARCH_INITCALL is not set
CONFIG_GRO_CELLS=y
-CONFIG_IPQ5018_PHY=y
CONFIG_IPQ_CMN_PLL=y
CONFIG_IPQ_GCC_5018=y
CONFIG_LEDS_PWM=y
diff --git a/target/linux/qualcommax/patches-6.12/0711-clk-qcom-gcc-ipq5018-fix-ge-phy-reset.patch b/target/linux/qualcommax/patches-6.12/0056-v6.17-clk-qcom-gcc-ipq5018-fix-GE-PHY-reset.patch
similarity index 71%
rename from target/linux/qualcommax/patches-6.12/0711-clk-qcom-gcc-ipq5018-fix-ge-phy-reset.patch
rename to target/linux/qualcommax/patches-6.12/0056-v6.17-clk-qcom-gcc-ipq5018-fix-GE-PHY-reset.patch
index 72d86c6783..902ad42515 100644
--- a/target/linux/qualcommax/patches-6.12/0711-clk-qcom-gcc-ipq5018-fix-ge-phy-reset.patch
+++ b/target/linux/qualcommax/patches-6.12/0056-v6.17-clk-qcom-gcc-ipq5018-fix-GE-PHY-reset.patch
@@ -1,11 +1,7 @@
-From 19600588e6403ff9f6c1e985fc025afb9160a56f Mon Sep 17 00:00:00 2001
+From f6a4a55ae5d99f865e106916a9295548e381de47 Mon Sep 17 00:00:00 2001
From: George Moussalem <george.moussalem at outlook.com>
-Date: Wed, 28 May 2025 08:37:25 +0400
-Subject: [PATCH v2 2/5] clk: qcom: gcc-ipq5018: fix GE PHY reset
-MIME-Version: 1.0
-Content-Type: text/plain; charset="utf-8"
-Content-Transfer-Encoding: 7bit
-Message-Id: <20250528-ipq5018-ge-phy-v2-2-68fc3a8248dd at outlook.com>
+Date: Mon, 30 Jun 2025 16:35:00 +0400
+Subject: clk: qcom: gcc-ipq5018: fix GE PHY reset
The MISC reset is supposed to trigger a resets across the MDC, DSP, and
RX & TX clocks of the IPQ5018 internal GE PHY. So let's set the bitmask
@@ -14,11 +10,16 @@ driver.
Link: https://git.codelinaro.org/clo/qsdk/oss/kernel/linux-ipq-5.4/-/commit/00743c3e82fa87cba4460e7a2ba32f473a9ce932
+Reviewed-by: Konrad Dybcio <konrad.dybcio at oss.qualcomm.com>
Signed-off-by: George Moussalem <george.moussalem at outlook.com>
+Link: https://lore.kernel.org/r/20250630-ipq5018-ge-phy-v6-1-01be06378c15@outlook.com
+Signed-off-by: Bjorn Andersson <andersson at kernel.org>
---
drivers/clk/qcom/gcc-ipq5018.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
+(limited to 'drivers/clk/qcom/gcc-ipq5018.c')
+
--- a/drivers/clk/qcom/gcc-ipq5018.c
+++ b/drivers/clk/qcom/gcc-ipq5018.c
@@ -3660,7 +3660,7 @@ static const struct qcom_reset_map gcc_i
diff --git a/target/linux/qualcommax/patches-6.12/0712-net-phy-qcom-at803x-add-qualcomm-ipq5018-internal-phy-support.patch b/target/linux/qualcommax/patches-6.12/0057-v6.17-net-phy-qcom-at803x-Add-Qualcomm-IPQ5018-Internal-PHY-support.patch
similarity index 74%
rename from target/linux/qualcommax/patches-6.12/0712-net-phy-qcom-at803x-add-qualcomm-ipq5018-internal-phy-support.patch
rename to target/linux/qualcommax/patches-6.12/0057-v6.17-net-phy-qcom-at803x-Add-Qualcomm-IPQ5018-Internal-PHY-support.patch
index 394eca19da..006f0b35f5 100644
--- a/target/linux/qualcommax/patches-6.12/0712-net-phy-qcom-at803x-add-qualcomm-ipq5018-internal-phy-support.patch
+++ b/target/linux/qualcommax/patches-6.12/0057-v6.17-net-phy-qcom-at803x-Add-Qualcomm-IPQ5018-Internal-PHY-support.patch
@@ -1,75 +1,39 @@
-From 9a89cb300c1ed5b90bae5684c88c85895a15c849 Mon Sep 17 00:00:00 2001
+From d46502279a11b48ede1d8bf65a229c8231bf0602 Mon Sep 17 00:00:00 2001
From: George Moussalem <george.moussalem at outlook.com>
-Date: Mon, 02 Jun 2025 12:50:39 +0400
-Subject: [PATCH v3 3/5] net: phy: qcom: at803x: Add Qualcomm IPQ5018 Internal PHY support
-MIME-Version: 1.0
-Content-Type: text/plain; charset="utf-8"
-Content-Transfer-Encoding: 7bit
-Message-Id: <20250602-ipq5018-ge-phy-v3-3-0d8f39f402a6 at outlook.com>
+Date: Fri, 13 Jun 2025 05:55:08 +0400
+Subject: net: phy: qcom: at803x: Add Qualcomm IPQ5018 Internal PHY support
The IPQ5018 SoC contains a single internal Gigabit Ethernet PHY which
provides an MDI interface directly to an RJ45 connector or an external
switch over a PHY to PHY link.
-The PHY supports 10/100/1000 mbps link modes, CDT, auto-negotiation and
-802.3az EEE.
+The PHY supports 10BASE-T/100BASE-TX/1000BASE-T link modes in SGMII
+interface mode, CDT, auto-negotiation and 802.3az EEE.
Let's add support for this PHY in the at803x driver as it falls within
the Qualcomm Atheros OUI.
+Reviewed-by: Andrew Lunn <andrew at lunn.ch>
Signed-off-by: George Moussalem <george.moussalem at outlook.com>
+Link: https://patch.msgid.link/20250613-ipq5018-ge-phy-v5-2-9af06e34ea6b@outlook.com
+Signed-off-by: Jakub Kicinski <kuba at kernel.org>
---
- drivers/net/phy/qcom/Kconfig | 2 +-
- drivers/net/phy/qcom/at803x.c | 185 ++++++++++++++++++++++++++++++++++++++++--
- 2 files changed, 178 insertions(+), 9 deletions(-)
+ drivers/net/phy/qcom/at803x.c | 167 ++++++++++++++++++++++++++++++++++++++++++
+ 1 file changed, 167 insertions(+)
+
+(limited to 'drivers/net/phy/qcom/at803x.c')
---- a/drivers/net/phy/qcom/Kconfig
-+++ b/drivers/net/phy/qcom/Kconfig
-@@ -7,7 +7,7 @@ config AT803X_PHY
- select QCOM_NET_PHYLIB
- depends on REGULATOR
- help
-- Currently supports the AR8030, AR8031, AR8033, AR8035 model
-+ Currently supports the AR8030, AR8031, AR8033, AR8035, IPQ5018 model
-
- config QCA83XX_PHY
- tristate "Qualcomm Atheros QCA833x PHYs"
--- a/drivers/net/phy/qcom/at803x.c
+++ b/drivers/net/phy/qcom/at803x.c
-@@ -7,19 +7,24 @@
- * Author: Matus Ujhelyi <ujhelyi.m at gmail.com>
- */
-
--#include <linux/phy.h>
--#include <linux/module.h>
--#include <linux/string.h>
--#include <linux/netdevice.h>
-+#include <linux/bitfield.h>
-+#include <linux/clk.h>
-+#include <linux/clk-provider.h>
- #include <linux/etherdevice.h>
- #include <linux/ethtool_netlink.h>
--#include <linux/bitfield.h>
--#include <linux/regulator/of_regulator.h>
--#include <linux/regulator/driver.h>
--#include <linux/regulator/consumer.h>
-+#include <linux/mfd/syscon.h>
-+#include <linux/module.h>
-+#include <linux/netdevice.h>
+@@ -19,6 +19,7 @@
+ #include <linux/regulator/consumer.h>
#include <linux/of.h>
-+#include <linux/phy.h>
#include <linux/phylink.h>
-+#include <linux/regmap.h>
-+#include <linux/regulator/consumer.h>
-+#include <linux/regulator/driver.h>
-+#include <linux/regulator/of_regulator.h>
+#include <linux/reset.h>
#include <linux/sfp.h>
-+#include <linux/string.h>
#include <dt-bindings/net/qca-ar803x.h>
- #include "qcom.h"
-@@ -93,6 +98,8 @@
+@@ -93,6 +94,8 @@
#define ATH8035_PHY_ID 0x004dd072
#define AT8030_PHY_ID_MASK 0xffffffef
@@ -78,7 +42,7 @@ Signed-off-by: George Moussalem <george.moussalem at outlook.com>
#define QCA9561_PHY_ID 0x004dd042
#define AT803X_PAGE_FIBER 0
-@@ -105,6 +112,50 @@
+@@ -105,6 +108,48 @@
/* disable hibernation mode */
#define AT803X_DISABLE_HIBERNATION_MODE BIT(2)
@@ -95,8 +59,8 @@ Signed-off-by: George Moussalem <george.moussalem at outlook.com>
+
+#define IPQ5018_PHY_MMD1_MSE_THRESH1 0x1000
+#define IPQ5018_PHY_MMD1_MSE_THRESH2 0x1001
-+#define IPQ5018_PHY_PCS_AZ_CTRL1 0x8008
-+#define IPQ5018_PHY_PCS_AZ_CTRL2 0x8009
++#define IPQ5018_PHY_PCS_EEE_TX_TIMER 0x8008
++#define IPQ5018_PHY_PCS_EEE_RX_TIMER 0x8009
+#define IPQ5018_PHY_PCS_CDT_THRESH_CTRL3 0x8074
+#define IPQ5018_PHY_PCS_CDT_THRESH_CTRL4 0x8075
+#define IPQ5018_PHY_PCS_CDT_THRESH_CTRL5 0x8076
@@ -108,8 +72,8 @@ Signed-off-by: George Moussalem <george.moussalem at outlook.com>
+
+#define IPQ5018_PHY_MMD1_MSE_THRESH1_VAL 0xf1
+#define IPQ5018_PHY_MMD1_MSE_THRESH2_VAL 0x1f6
-+#define IPQ5018_PHY_PCS_AZ_CTRL1_VAL 0x7880
-+#define IPQ5018_PHY_PCS_AZ_CTRL2_VAL 0xc8
++#define IPQ5018_PHY_PCS_EEE_TX_TIMER_VAL 0x7880
++#define IPQ5018_PHY_PCS_EEE_RX_TIMER_VAL 0xc8
+#define IPQ5018_PHY_PCS_CDT_THRESH_CTRL3_VAL 0xc040
+#define IPQ5018_PHY_PCS_CDT_THRESH_CTRL4_VAL 0xa060
+#define IPQ5018_PHY_PCS_CDT_THRESH_CTRL5_VAL 0xc040
@@ -123,13 +87,11 @@ Signed-off-by: George Moussalem <george.moussalem at outlook.com>
+#define IPQ5018_PHY_DEBUG_ANA_LDO_EFUSE_MASK GENMASK(7, 4)
+#define IPQ5018_PHY_DEBUG_ANA_LDO_EFUSE_DEFAULT 0x50
+#define IPQ5018_PHY_DEBUG_ANA_DAC_FILTER 0xa080
-+
-+#define IPQ5018_TCSR_ETH_LDO_READY BIT(0)
+
MODULE_DESCRIPTION("Qualcomm Atheros AR803x PHY driver");
MODULE_AUTHOR("Matus Ujhelyi");
MODULE_LICENSE("GPL");
-@@ -130,6 +181,11 @@ struct at803x_context {
+@@ -130,6 +175,11 @@ struct at803x_context {
u16 led_control;
};
@@ -141,7 +103,7 @@ Signed-off-by: George Moussalem <george.moussalem at outlook.com>
static int at803x_write_page(struct phy_device *phydev, int page)
{
int mask;
-@@ -960,6 +1016,105 @@ static int at8035_probe(struct phy_devic
+@@ -960,6 +1010,109 @@ static int at8035_probe(struct phy_devic
return at8035_parse_dt(phydev);
}
@@ -171,7 +133,7 @@ Signed-off-by: George Moussalem <george.moussalem at outlook.com>
+static int ipq5018_config_init(struct phy_device *phydev)
+{
+ struct ipq5018_priv *priv = phydev->priv;
-+ u16 val = 0;
++ u16 val;
+
+ /*
+ * set LDO efuse: first temporarily store ANA_DAC_FILTER value from
@@ -184,11 +146,11 @@ Signed-off-by: George Moussalem <george.moussalem at outlook.com>
+ IPQ5018_PHY_DEBUG_ANA_LDO_EFUSE_DEFAULT);
+ at803x_debug_reg_write(phydev, IPQ5018_PHY_DEBUG_ANA_DAC_FILTER, val);
+
-+ /* set 8023AZ CTRL values */
-+ phy_write_mmd(phydev, MDIO_MMD_PCS, IPQ5018_PHY_PCS_AZ_CTRL1,
-+ IPQ5018_PHY_PCS_AZ_CTRL1_VAL);
-+ phy_write_mmd(phydev, MDIO_MMD_PCS, IPQ5018_PHY_PCS_AZ_CTRL2,
-+ IPQ5018_PHY_PCS_AZ_CTRL2_VAL);
++ /* set 8023AZ EEE TX and RX timer values */
++ phy_write_mmd(phydev, MDIO_MMD_PCS, IPQ5018_PHY_PCS_EEE_TX_TIMER,
++ IPQ5018_PHY_PCS_EEE_TX_TIMER_VAL);
++ phy_write_mmd(phydev, MDIO_MMD_PCS, IPQ5018_PHY_PCS_EEE_RX_TIMER,
++ IPQ5018_PHY_PCS_EEE_RX_TIMER_VAL);
+
+ /* set MSE threshold values */
+ phy_write_mmd(phydev, MDIO_MMD_PMAPMD, IPQ5018_PHY_MMD1_MSE_THRESH1,
@@ -212,6 +174,10 @@ Signed-off-by: George Moussalem <george.moussalem at outlook.com>
+
+static void ipq5018_link_change_notify(struct phy_device *phydev)
+{
++ /*
++ * Reset the FIFO buffer upon link disconnects to clear any residual data
++ * which may cause issues with the FIFO which it cannot recover from.
++ */
+ mdiobus_modify_changed(phydev->mdio.bus, phydev->mdio.addr,
+ IPQ5018_PHY_FIFO_CONTROL, IPQ5018_PHY_FIFO_RESET,
+ phydev->link ? IPQ5018_PHY_FIFO_RESET : 0);
@@ -231,7 +197,7 @@ Signed-off-by: George Moussalem <george.moussalem at outlook.com>
+ "qcom,dac-preset-short-cable");
+
+ priv->rst = devm_reset_control_array_get_exclusive(dev);
-+ if (IS_ERR_OR_NULL(priv->rst))
++ if (IS_ERR(priv->rst))
+ return dev_err_probe(dev, PTR_ERR(priv->rst),
+ "failed to acquire reset\n");
+
@@ -247,7 +213,7 @@ Signed-off-by: George Moussalem <george.moussalem at outlook.com>
static struct phy_driver at803x_driver[] = {
{
/* Qualcomm Atheros AR8035 */
-@@ -1052,6 +1207,19 @@ static struct phy_driver at803x_driver[]
+@@ -1052,6 +1205,19 @@ static struct phy_driver at803x_driver[]
.soft_reset = genphy_soft_reset,
.config_aneg = at803x_config_aneg,
}, {
@@ -267,7 +233,7 @@ Signed-off-by: George Moussalem <george.moussalem at outlook.com>
/* Qualcomm Atheros QCA9561 */
PHY_ID_MATCH_EXACT(QCA9561_PHY_ID),
.name = "Qualcomm Atheros QCA9561 built-in PHY",
-@@ -1077,6 +1245,7 @@ static const struct mdio_device_id __may
+@@ -1077,6 +1243,7 @@ static const struct mdio_device_id __may
{ PHY_ID_MATCH_EXACT(ATH8032_PHY_ID) },
{ PHY_ID_MATCH_EXACT(ATH8035_PHY_ID) },
{ PHY_ID_MATCH_EXACT(ATH9331_PHY_ID) },
diff --git a/target/linux/qualcommax/patches-6.12/0713-arm64-dts-qcom-ipq5018-add-mdio-buses.patch b/target/linux/qualcommax/patches-6.12/0058-v6.18-arm64-dts-qcom-ipq5018-Add-MDIO-buses.patch
similarity index 71%
rename from target/linux/qualcommax/patches-6.12/0713-arm64-dts-qcom-ipq5018-add-mdio-buses.patch
rename to target/linux/qualcommax/patches-6.12/0058-v6.18-arm64-dts-qcom-ipq5018-Add-MDIO-buses.patch
index 81842e0dc5..59f6bc2cc4 100644
--- a/target/linux/qualcommax/patches-6.12/0713-arm64-dts-qcom-ipq5018-add-mdio-buses.patch
+++ b/target/linux/qualcommax/patches-6.12/0058-v6.18-arm64-dts-qcom-ipq5018-Add-MDIO-buses.patch
@@ -1,11 +1,7 @@
-From 97a159dd7747724619e54cb3460d9b8d4ed08be7 Mon Sep 17 00:00:00 2001
+From 1e2261a669a9596ba435c6fe524e026bac0f0e2f Mon Sep 17 00:00:00 2001
From: George Moussalem <george.moussalem at outlook.com>
-Date: Mon, 02 Jun 2025 12:50:40 +0400
-Subject: [PATCH v3 4/5] arm64: dts: qcom: ipq5018: Add MDIO buses
-MIME-Version: 1.0
-Content-Type: text/plain; charset="utf-8"
-Content-Transfer-Encoding: 7bit
-Message-Id: <20250602-ipq5018-ge-phy-v3-4-0d8f39f402a6 at outlook.com>
+Date: Mon, 30 Jun 2025 16:35:01 +0400
+Subject: arm64: dts: qcom: ipq5018: Add MDIO buses
IPQ5018 contains two mdio buses of which one bus is used to control the
SoC's internal GE PHY, while the other bus is connected to external PHYs
@@ -16,13 +12,17 @@ simply add the mdio nodes for them.
Reviewed-by: Konrad Dybcio <konrad.dybcio at oss.qualcomm.com>
Signed-off-by: George Moussalem <george.moussalem at outlook.com>
+Link: https://lore.kernel.org/r/20250630-ipq5018-ge-phy-v6-2-01be06378c15@outlook.com
+Signed-off-by: Bjorn Andersson <andersson at kernel.org>
---
arch/arm64/boot/dts/qcom/ipq5018.dtsi | 24 ++++++++++++++++++++++++
1 file changed, 24 insertions(+)
+(limited to 'arch/arm64/boot/dts/qcom/ipq5018.dtsi')
+
--- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi
-@@ -191,6 +191,30 @@
+@@ -185,6 +185,30 @@
status = "disabled";
};
@@ -50,6 +50,6 @@ Signed-off-by: George Moussalem <george.moussalem at outlook.com>
+ status = "disabled";
+ };
+
- cmn_pll: clock-controller at 9b000 {
- compatible = "qcom,ipq9574-cmn-pll";
- reg = <0x0009b000 0x800>;
+ qfprom: qfprom at a0000 {
+ compatible = "qcom,ipq5018-qfprom", "qcom,qfprom";
+ reg = <0x000a0000 0x1000>;
diff --git a/target/linux/qualcommax/patches-6.12/0714-arm64-dts-qcom-ipq5018-add-ge-phy-to-internal-mdio-bus.patch b/target/linux/qualcommax/patches-6.12/0059-v6.18-arm64-dts-qcom-ipq5018-Add-GE-PHY-to-internal-mdio-bus.patch
similarity index 79%
rename from target/linux/qualcommax/patches-6.12/0714-arm64-dts-qcom-ipq5018-add-ge-phy-to-internal-mdio-bus.patch
rename to target/linux/qualcommax/patches-6.12/0059-v6.18-arm64-dts-qcom-ipq5018-Add-GE-PHY-to-internal-mdio-bus.patch
index 987a84ca2e..e8d96b8e0a 100644
--- a/target/linux/qualcommax/patches-6.12/0714-arm64-dts-qcom-ipq5018-add-ge-phy-to-internal-mdio-bus.patch
+++ b/target/linux/qualcommax/patches-6.12/0059-v6.18-arm64-dts-qcom-ipq5018-Add-GE-PHY-to-internal-mdio-bus.patch
@@ -1,11 +1,7 @@
-From 1b733e878ac1292c6e0f2e9a49685b80c35619b0 Mon Sep 17 00:00:00 2001
+From f5f2b835e316df29b89e28ed7e467df473932e8d Mon Sep 17 00:00:00 2001
From: George Moussalem <george.moussalem at outlook.com>
-Date: Mon, 02 Jun 2025 12:50:41 +0400
-Subject: [PATCH v3 5/5] arm64: dts: qcom: ipq5018: Add GE PHY to internal mdio bus
-MIME-Version: 1.0
-Content-Type: text/plain; charset="utf-8"
-Content-Transfer-Encoding: 7bit
-Message-Id: <20250602-ipq5018-ge-phy-v3-5-0d8f39f402a6 at outlook.com>
+Date: Mon, 30 Jun 2025 16:35:02 +0400
+Subject: arm64: dts: qcom: ipq5018: Add GE PHY to internal mdio bus
The IPQ5018 SoC contains an internal GE PHY, always at phy address 7.
As such, let's add the GE PHY node to the SoC dtsi.
@@ -20,16 +16,20 @@ So let's create two DT fixed clocks and register them in the GCC node.
Reviewed-by: Konrad Dybcio <konrad.dybcio at oss.qualcomm.com>
Signed-off-by: George Moussalem <george.moussalem at outlook.com>
+Link: https://lore.kernel.org/r/20250630-ipq5018-ge-phy-v6-3-01be06378c15@outlook.com
+Signed-off-by: Bjorn Andersson <andersson at kernel.org>
---
arch/arm64/boot/dts/qcom/ipq5018.dtsi | 26 +++++++++++++++++++++++---
1 file changed, 23 insertions(+), 3 deletions(-)
+(limited to 'arch/arm64/boot/dts/qcom/ipq5018.dtsi')
+
--- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi
-@@ -23,6 +23,18 @@
- #clock-cells = <0>;
- };
+@@ -17,6 +17,18 @@
+ #size-cells = <2>;
+ clocks {
+ gephy_rx_clk: gephy-rx-clk {
+ compatible = "fixed-clock";
+ clock-frequency = <125000000>;
@@ -45,7 +45,7 @@ Signed-off-by: George Moussalem <george.moussalem at outlook.com>
sleep_clk: sleep-clk {
compatible = "fixed-clock";
#clock-cells = <0>;
-@@ -193,7 +205,8 @@
+@@ -187,7 +199,8 @@
mdio0: mdio at 88000 {
compatible = "qcom,ipq5018-mdio";
@@ -55,7 +55,7 @@ Signed-off-by: George Moussalem <george.moussalem at outlook.com>
#address-cells = <1>;
#size-cells = <0>;
-@@ -201,6 +214,13 @@
+@@ -195,6 +208,13 @@
clock-names = "gcc_mdio_ahb_clk";
status = "disabled";
@@ -69,7 +69,7 @@ Signed-off-by: George Moussalem <george.moussalem at outlook.com>
};
mdio1: mdio at 90000 {
-@@ -395,8 +415,8 @@
+@@ -346,8 +366,8 @@
<&pcie0_phy>,
<&pcie1_phy>,
<0>,
diff --git a/target/linux/qualcommax/patches-6.12/0306-arm64-dts-qcom-ipq5018-Add-PWM-node.patch b/target/linux/qualcommax/patches-6.12/0306-arm64-dts-qcom-ipq5018-Add-PWM-node.patch
index b72f45ed3f..a0158f6c1e 100644
--- a/target/linux/qualcommax/patches-6.12/0306-arm64-dts-qcom-ipq5018-Add-PWM-node.patch
+++ b/target/linux/qualcommax/patches-6.12/0306-arm64-dts-qcom-ipq5018-Add-PWM-node.patch
@@ -8,7 +8,7 @@ Signed-off-by: George Moussalem <george.moussalem at outlook.com>
---
--- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi
-@@ -341,6 +341,16 @@
+@@ -385,6 +385,16 @@
reg = <0x01937000 0x21000>;
};
diff --git a/target/linux/qualcommax/patches-6.12/0324-arm64-dts-qcom-ipq5018-Add-crypto-nodes.patch b/target/linux/qualcommax/patches-6.12/0324-arm64-dts-qcom-ipq5018-Add-crypto-nodes.patch
index e20bde308d..de06d94244 100644
--- a/target/linux/qualcommax/patches-6.12/0324-arm64-dts-qcom-ipq5018-Add-crypto-nodes.patch
+++ b/target/linux/qualcommax/patches-6.12/0324-arm64-dts-qcom-ipq5018-Add-crypto-nodes.patch
@@ -8,7 +8,7 @@ Signed-off-by: George Moussalem <george.moussalem at outlook.com>
---
--- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi
-@@ -296,6 +296,30 @@
+@@ -340,6 +340,30 @@
#thermal-sensor-cells = <1>;
};
diff --git a/target/linux/qualcommax/patches-6.12/0337-arm64-dts-qcom-ipq5018-Add-PRNG-node.patch b/target/linux/qualcommax/patches-6.12/0337-arm64-dts-qcom-ipq5018-Add-PRNG-node.patch
index 1343a61ea8..f1499158fe 100644
--- a/target/linux/qualcommax/patches-6.12/0337-arm64-dts-qcom-ipq5018-Add-PRNG-node.patch
+++ b/target/linux/qualcommax/patches-6.12/0337-arm64-dts-qcom-ipq5018-Add-PRNG-node.patch
@@ -8,7 +8,7 @@ Signed-off-by: George Moussalem <george.moussalem at outlook.com>
---
--- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi
-@@ -257,6 +257,14 @@
+@@ -301,6 +301,14 @@
};
};
diff --git a/target/linux/qualcommax/patches-6.12/0339-arm64-dts-qcom-ipq5018-Add-QUP1-UART2-node.patch b/target/linux/qualcommax/patches-6.12/0339-arm64-dts-qcom-ipq5018-Add-QUP1-UART2-node.patch
index de1df4579b..4b5fc5d32e 100644
--- a/target/linux/qualcommax/patches-6.12/0339-arm64-dts-qcom-ipq5018-Add-QUP1-UART2-node.patch
+++ b/target/linux/qualcommax/patches-6.12/0339-arm64-dts-qcom-ipq5018-Add-QUP1-UART2-node.patch
@@ -8,7 +8,7 @@ Signed-off-by: George Moussalem <george.moussalem at outlook.com>
---
--- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi
-@@ -420,6 +420,16 @@
+@@ -464,6 +464,16 @@
status = "disabled";
};
diff --git a/target/linux/qualcommax/patches-6.12/0340-arm64-dts-qcom-ipq5018-Add-QUP3-I2C-node.patch b/target/linux/qualcommax/patches-6.12/0340-arm64-dts-qcom-ipq5018-Add-QUP3-I2C-node.patch
index c8802806f5..24acc55cdb 100644
--- a/target/linux/qualcommax/patches-6.12/0340-arm64-dts-qcom-ipq5018-Add-QUP3-I2C-node.patch
+++ b/target/linux/qualcommax/patches-6.12/0340-arm64-dts-qcom-ipq5018-Add-QUP3-I2C-node.patch
@@ -8,7 +8,7 @@ Signed-off-by: George Moussalem <george.moussalem at outlook.com>
---
--- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi
-@@ -444,6 +444,21 @@
+@@ -488,6 +488,21 @@
status = "disabled";
};
diff --git a/target/linux/qualcommax/patches-6.12/0421-arm64-dts-qcom-ipq5018-Add-SPI-nand-node.patch b/target/linux/qualcommax/patches-6.12/0421-arm64-dts-qcom-ipq5018-Add-SPI-nand-node.patch
index cc6df41db5..f7304f25a4 100644
--- a/target/linux/qualcommax/patches-6.12/0421-arm64-dts-qcom-ipq5018-Add-SPI-nand-node.patch
+++ b/target/linux/qualcommax/patches-6.12/0421-arm64-dts-qcom-ipq5018-Add-SPI-nand-node.patch
@@ -13,7 +13,7 @@ Signed-off-by: George Moussalem <george.moussalem at outlook.com>
--- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi
-@@ -459,6 +459,36 @@
+@@ -503,6 +503,36 @@
status = "disabled";
};
diff --git a/target/linux/qualcommax/patches-6.12/0704-arm64-dts-qcom-ipq5018-Add-ethernet-cmn-node.patch b/target/linux/qualcommax/patches-6.12/0704-arm64-dts-qcom-ipq5018-Add-ethernet-cmn-node.patch
index c831080baf..04508da2b7 100644
--- a/target/linux/qualcommax/patches-6.12/0704-arm64-dts-qcom-ipq5018-Add-ethernet-cmn-node.patch
+++ b/target/linux/qualcommax/patches-6.12/0704-arm64-dts-qcom-ipq5018-Add-ethernet-cmn-node.patch
@@ -20,10 +20,10 @@ Signed-off-by: Ziyang Huang <hzyitc at outlook.com>
+ #clock-cells = <0>;
+ };
+
- sleep_clk: sleep-clk {
+ gephy_rx_clk: gephy-rx-clk {
compatible = "fixed-clock";
- #clock-cells = <0>;
-@@ -185,6 +191,17 @@
+ clock-frequency = <125000000>;
+@@ -229,6 +235,17 @@
status = "disabled";
};
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