[openwrt/openwrt] ipq806x: add PCIe bridge node reference labels for ipq8064.dtsi

[LEDE Commits]

ansuel pushed a commit to openwrt/openwrt.git, branch main:
https://git.openwrt.org/7d2fd7d59070f5b3bf93b3e19ef00865546ee23d

commit 7d2fd7d59070f5b3bf93b3e19ef00865546ee23d
Author: Shiji Yang <yangshiji66 at outlook.com>
AuthorDate: Sun Jun 1 12:35:22 2025 +0800

    ipq806x: add PCIe bridge node reference labels for ipq8064.dtsi
    
    Add bridge node labels so that we can insert PCIe peripheral nodes.
    
    Signed-off-by: Shiji Yang <yangshiji66 at outlook.com>
    Link: https://github.com/openwrt/openwrt/pull/18989
    Signed-off-by: Christian Marangi <ansuelsmth at gmail.com>
---
 ...m-ipq8064-add-reference-labels-for-PCIe-b.patch | 41 ++++++++++++++++++++++
 1 file changed, 41 insertions(+)

diff --git a/target/linux/ipq806x/patches-6.12/700-ARM-dts-qcom-ipq8064-add-reference-labels-for-PCIe-b.patch b/target/linux/ipq806x/patches-6.12/700-ARM-dts-qcom-ipq8064-add-reference-labels-for-PCIe-b.patch
new file mode 100644
index 0000000000..acd5cec60c
--- /dev/null
+++ b/target/linux/ipq806x/patches-6.12/700-ARM-dts-qcom-ipq8064-add-reference-labels-for-PCIe-b.patch
@@ -0,0 +1,41 @@
+From: Shiji Yang <yangshiji66 at outlook.com>
+Date: Sun, 1 Jun 2025 11:56:05 +0800
+Subject: [PATCH] ARM: dts: qcom: ipq8064: add reference labels for PCIe bridge
+
+Some devices have ath10k PCIe peripherals. Add node labels so that
+the bridge node can be referenced.
+
+Signed-off-by: Shiji Yang <yangshiji66 at outlook.com>
+---
+ arch/arm/boot/dts/qcom/qcom-ipq8064.dtsi | 6 +++---
+ 1 file changed, 3 insertions(+), 3 deletions(-)
+
+--- a/arch/arm/boot/dts/qcom/qcom-ipq8064.dtsi
++++ b/arch/arm/boot/dts/qcom/qcom-ipq8064.dtsi
+@@ -1257,7 +1257,7 @@
+ 			status = "disabled";
+ 			perst-gpios = <&qcom_pinmux 3 GPIO_ACTIVE_LOW>;
+ 
+-			pcie at 0 {
++			pcie_bridge0: pcie at 0 {
+ 				device_type = "pci";
+ 				reg = <0x0 0x0 0x0 0x0 0x0>;
+ 				bus-range = <0x01 0xff>;
+@@ -1318,7 +1318,7 @@
+ 			status = "disabled";
+ 			perst-gpios = <&qcom_pinmux 48 GPIO_ACTIVE_LOW>;
+ 
+-			pcie at 0 {
++			pcie_bridge1: pcie at 0 {
+ 				device_type = "pci";
+ 				reg = <0x0 0x0 0x0 0x0 0x0>;
+ 				bus-range = <0x01 0xff>;
+@@ -1379,7 +1379,7 @@
+ 			status = "disabled";
+ 			perst-gpios = <&qcom_pinmux 63 GPIO_ACTIVE_LOW>;
+ 
+-			pcie at 0 {
++			pcie_bridge2: pcie at 0 {
+ 				device_type = "pci";
+ 				reg = <0x0 0x0 0x0 0x0 0x0>;
+ 				bus-range = <0x01 0xff>;