[openwrt/openwrt] airoha: an7581: correctly attach the USB2 PHY for 3rd PCIe line

[LEDE Commits]

ansuel pushed a commit to openwrt/openwrt.git, branch openwrt-24.10:
https://git.openwrt.org/b5a66740c28af721cfbea7eb6edfc275cfec1107

commit b5a66740c28af721cfbea7eb6edfc275cfec1107
Author: Christian Marangi <ansuelsmth at gmail.com>
AuthorDate: Tue Oct 28 13:17:38 2025 +0100

    airoha: an7581: correctly attach the USB2 PHY for 3rd PCIe line
    
    The 3rd PCIe line use the USB2 serdes for PCIe operation. Correctly set
    it to the DT node so that the mode can be correctly set in the PHY
    driver.
    
    Signed-off-by: Christian Marangi <ansuelsmth at gmail.com>
    (cherry picked from commit 3ba92e0e3268c07859859968368602d2dc758148)
---
 target/linux/airoha/dts/an7581.dtsi | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/target/linux/airoha/dts/an7581.dtsi b/target/linux/airoha/dts/an7581.dtsi
index 7956d1de3b..880063341f 100644
--- a/target/linux/airoha/dts/an7581.dtsi
+++ b/target/linux/airoha/dts/an7581.dtsi
@@ -780,7 +780,7 @@
 			clocks = <&scuclk EN7523_CLK_PCIE>;
 			clock-names = "sys-ck";
 
-			phys = <&pciephy>;
+			phys = <&usb1_phy PHY_TYPE_USB3>;
 			phy-names = "pcie-phy";
 
 			ranges = <0x02000000 0 0x28000000 0x0 0x28000000 0 0x4000000>;