[openwrt/openwrt] realtek: restructure Zyxel XGS1210-12 device tree files
LEDE Commits
lede-commits at lists.infradead.org
Mon Nov 3 02:07:24 PST 2025
robimarko pushed a commit to openwrt/openwrt.git, branch main:
https://git.openwrt.org/67b687af918ed219f26d366b6640825ed0e697fd
commit 67b687af918ed219f26d366b6640825ed0e697fd
Author: Jan Hoffmann <jan at 3e8.eu>
AuthorDate: Mon Oct 20 15:24:40 2025 +0200
realtek: restructure Zyxel XGS1210-12 device tree files
This is a preparation for adding support for XGS1010-12, which is almost
identical to XGS1210-12, with some small differences (partition layout,
missing reset key).
In addition to moving the common parts to a new file, also simplify the
definition of the 2.5G PHYs to reduce duplication. With this change, the
revision-specific files only have to specify the SMI addresses.
Signed-off-by: Jan Hoffmann <jan at 3e8.eu>
Link: https://github.com/openwrt/openwrt/pull/20469
Signed-off-by: Robert Marko <robimarko at gmail.com>
---
.../realtek/dts/rtl9302_zyxel_xgs1210-12-a1.dts | 39 +---
.../realtek/dts/rtl9302_zyxel_xgs1210-12-b1.dts | 39 +---
.../dts/rtl9302_zyxel_xgs1210-12-common.dtsi | 232 +--------------------
...n.dtsi => rtl9302_zyxel_xgs1x10-12-common.dtsi} | 91 +++-----
4 files changed, 40 insertions(+), 361 deletions(-)
diff --git a/target/linux/realtek/dts/rtl9302_zyxel_xgs1210-12-a1.dts b/target/linux/realtek/dts/rtl9302_zyxel_xgs1210-12-a1.dts
index edd729ddcb..f1aff554df 100644
--- a/target/linux/realtek/dts/rtl9302_zyxel_xgs1210-12-a1.dts
+++ b/target/linux/realtek/dts/rtl9302_zyxel_xgs1210-12-a1.dts
@@ -8,41 +8,10 @@
model = "Zyxel XGS1210-12 A1 Switch";
};
-&mdio_bus0 {
- phy24: ethernet-phy at 24 {
- reg = <24>;
- compatible = "ethernet-phy-ieee802.3-c45";
- rtl9300,smi-address = <1 8>;
- // Disabled because we do not know how to bring up again
- // reset-gpios = <&gpio0 21 GPIO_ACTIVE_LOW>;
- };
-
- phy25: ethernet-phy at 25 {
- reg = <25>;
- compatible = "ethernet-phy-ieee802.3-c45";
- rtl9300,smi-address = <2 9>;
- // Disabled because we do not know how to bring up again
- // reset-gpios = <&gpio0 21 GPIO_ACTIVE_LOW>;
- };
+&phy24 {
+ rtl9300,smi-address = <1 8>;
};
-&switch0 {
- ports {
- port at 24 {
- reg = <24>;
- label = "lan9";
- pcs-handle = <&serdes6>;
- phy-handle = <&phy24>;
- phy-mode = "2500base-x";
- led-set = <1>;
- };
- port at 25 {
- reg = <25>;
- label = "lan10";
- pcs-handle = <&serdes7>;
- phy-handle = <&phy25>;
- phy-mode = "2500base-x";
- led-set = <1>;
- };
- };
+&phy25 {
+ rtl9300,smi-address = <2 9>;
};
diff --git a/target/linux/realtek/dts/rtl9302_zyxel_xgs1210-12-b1.dts b/target/linux/realtek/dts/rtl9302_zyxel_xgs1210-12-b1.dts
index 73b4a081c7..f7567e031b 100644
--- a/target/linux/realtek/dts/rtl9302_zyxel_xgs1210-12-b1.dts
+++ b/target/linux/realtek/dts/rtl9302_zyxel_xgs1210-12-b1.dts
@@ -8,41 +8,10 @@
model = "Zyxel XGS1210-12 B1 Switch";
};
-&mdio_bus0 {
- phy24: ethernet-phy at 24 {
- reg = <24>;
- compatible = "ethernet-phy-ieee802.3-c45";
- rtl9300,smi-address = <1 1>;
- // Disabled because we do not know how to bring up again
- // reset-gpios = <&gpio0 21 GPIO_ACTIVE_LOW>;
- };
-
- phy25: ethernet-phy at 25 {
- reg = <25>;
- compatible = "ethernet-phy-ieee802.3-c45";
- rtl9300,smi-address = <2 2>;
- // Disabled because we do not know how to bring up again
- // reset-gpios = <&gpio0 21 GPIO_ACTIVE_LOW>;
- };
+&phy24 {
+ rtl9300,smi-address = <1 1>;
};
-&switch0 {
- ports {
- port at 24 {
- reg = <24>;
- label = "lan9";
- pcs-handle = <&serdes6>;
- phy-handle = <&phy24>;
- phy-mode = "2500base-x";
- led-set = <1>;
- };
- port at 25 {
- reg = <25>;
- label = "lan10";
- pcs-handle = <&serdes7>;
- phy-handle = <&phy25>;
- phy-mode = "2500base-x";
- led-set = <1>;
- };
- };
+&phy25 {
+ rtl9300,smi-address = <2 2>;
};
diff --git a/target/linux/realtek/dts/rtl9302_zyxel_xgs1210-12-common.dtsi b/target/linux/realtek/dts/rtl9302_zyxel_xgs1210-12-common.dtsi
index 9412d26976..a4e82b5af0 100644
--- a/target/linux/realtek/dts/rtl9302_zyxel_xgs1210-12-common.dtsi
+++ b/target/linux/realtek/dts/rtl9302_zyxel_xgs1210-12-common.dtsi
@@ -1,21 +1,9 @@
// SPDX-License-Identifier: GPL-2.0-or-later
/dts-v1/;
-#include "rtl930x.dtsi"
-
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/leds/common.h>
-#include <dt-bindings/thermal/thermal.h>
+#include "rtl9302_zyxel_xgs1x10-12-common.dtsi"
/ {
- aliases {
- led-boot = &led_pwr_sys;
- led-failsafe = &led_pwr_sys;
- led-running = &led_pwr_sys;
- led-upgrade = &led_pwr_sys;
- };
-
keys {
compatible = "gpio-keys";
@@ -25,76 +13,6 @@
linux,code = <KEY_RESTART>;
};
};
-
- leds {
- compatible = "gpio-leds";
-
- pinctrl-names = "default";
- pinctrl-0 = <&pinmux_disable_sys_led>;
-
- led_pwr_sys: led-0 {
- label = "green:power";
- color = <LED_COLOR_ID_GREEN>;
- function = LED_FUNCTION_POWER;
- gpios = <&gpio0 0 GPIO_ACTIVE_HIGH>;
- };
- };
-
- sfp0: sfp-p11 {
- compatible = "sff,sfp";
- i2c-bus = <&i2c0>;
- los-gpio = <&gpio0 13 GPIO_ACTIVE_HIGH>;
- tx-fault-gpio = <&gpio0 14 GPIO_ACTIVE_HIGH>;
- mod-def0-gpio = <&gpio0 12 GPIO_ACTIVE_LOW>;
- tx-disable-gpio = <&gpio0 11 GPIO_ACTIVE_HIGH>;
- };
-
- sfp1: sfp-p12 {
- compatible = "sff,sfp";
- i2c-bus = <&i2c1>;
- los-gpio = <&gpio0 17 GPIO_ACTIVE_HIGH>;
- tx-fault-gpio = <&gpio0 20 GPIO_ACTIVE_HIGH>;
- mod-def0-gpio = <&gpio0 16 GPIO_ACTIVE_LOW>;
- tx-disable-gpio = <&gpio0 15 GPIO_ACTIVE_HIGH>;
- };
-
- led_set: led_set {
- compatible = "realtek,rtl9300-leds";
- active-low;
-
- // LED set 0:
- // Amber: 100M/10M
- // Yellow: 1G
- led_set0 = <0x0a20 0x0b80>;
-
- // LED set 1:
- // Blue: 2.5G
- // Green: 2.5G
- // Yellow: 1G
- // Amber: 100M/10M
- // (Blue + Green = Cyan)
- led_set1 = <0x0b80 0x0a20 0x0a08 0x0a08>;
-
- // LED set 2:
- // Blue: 10G/5G/2.5G
- // Yellow: 5G/2.5G/1G
- // (Blue + Yellow = Purple)
- led_set2 = <0x0a2a 0x0a0b>;
- };
-};
-
-&i2c_mst1 {
- status = "okay";
-
- /* i2c of the left SFP+ cage seen from the front; port 11 */
- i2c0: i2c at 0 {
- reg = <0>;
- };
-
- /* i2c of the right SFP+ cage seen from the front; port 12 */
- i2c1: i2c at 1 {
- reg = <1>;
- };
};
&spi0 {
@@ -145,151 +63,3 @@
};
};
};
-
-&mdio_bus0 {
- /* External RTL8218D PHY */
- phy0: ethernet-phy at 0 {
- reg = <0>;
- compatible = "ethernet-phy-ieee802.3-c22";
- rtl9300,smi-address = <0 0>;
- // Disabled because we do not know how to bring up again
- // reset-gpios = <&gpio0 21 GPIO_ACTIVE_LOW>;
- };
- phy1: ethernet-phy at 1 {
- reg = <1>;
- compatible = "ethernet-phy-ieee802.3-c22";
- rtl9300,smi-address = <0 1>;
- };
- phy2: ethernet-phy at 2 {
- reg = <2>;
- compatible = "ethernet-phy-ieee802.3-c22";
- rtl9300,smi-address = <0 2>;
- };
- phy3: ethernet-phy at 3 {
- reg = <3>;
- compatible = "ethernet-phy-ieee802.3-c22";
- rtl9300,smi-address = <0 3>;
- };
- phy4: ethernet-phy at 4 {
- reg = <4>;
- compatible = "ethernet-phy-ieee802.3-c22";
- rtl9300,smi-address = <0 4>;
- };
- phy5: ethernet-phy at 5 {
- reg = <5>;
- compatible = "ethernet-phy-ieee802.3-c22";
- rtl9300,smi-address = <0 5>;
- };
- phy6: ethernet-phy at 6 {
- reg = <6>;
- compatible = "ethernet-phy-ieee802.3-c22";
- rtl9300,smi-address = <0 6>;
- };
- phy7: ethernet-phy at 7 {
- reg = <7>;
- compatible = "ethernet-phy-ieee802.3-c22";
- rtl9300,smi-address = <0 7>;
- };
-};
-
-&switch0 {
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port at 0 {
- reg = <0>;
- label = "lan1";
- pcs-handle = <&serdes2>;
- phy-handle = <&phy0>;
- phy-mode = "usxgmii";
- led-set = <0>;
- };
- port at 1 {
- reg = <1>;
- label = "lan2";
- pcs-handle = <&serdes2>;
- phy-handle = <&phy1>;
- phy-mode = "usxgmii";
- led-set = <0>;
- };
- port at 2 {
- reg = <2>;
- label = "lan3";
- pcs-handle = <&serdes2>;
- phy-handle = <&phy2>;
- phy-mode = "usxgmii";
- led-set = <0>;
- };
- port at 3 {
- reg = <3>;
- label = "lan4";
- pcs-handle = <&serdes2>;
- phy-handle = <&phy3>;
- phy-mode = "usxgmii";
- led-set = <0>;
- };
- port at 4 {
- reg = <4>;
- label = "lan5";
- pcs-handle = <&serdes2>;
- phy-handle = <&phy4>;
- phy-mode = "usxgmii";
- led-set = <0>;
- };
- port at 5 {
- reg = <5>;
- label = "lan6";
- pcs-handle = <&serdes2>;
- phy-handle = <&phy5>;
- phy-mode = "usxgmii";
- led-set = <0>;
- };
- port at 6 {
- reg = <6>;
- label = "lan7";
- pcs-handle = <&serdes2>;
- phy-handle = <&phy6>;
- phy-mode = "usxgmii";
- led-set = <0>;
- };
- port at 7 {
- reg = <7>;
- label = "lan8";
- pcs-handle = <&serdes2>;
- phy-handle = <&phy7>;
- phy-mode = "usxgmii";
- led-set = <0>;
- };
-
- port at 26 {
- reg = <26>;
- label = "lan11";
- pcs-handle = <&serdes8>;
- phy-mode = "1000base-x";
- sfp = <&sfp0>;
- led-set = <2>;
- managed = "in-band-status";
- };
-
- port at 27 {
- reg = <27>;
- label = "lan12";
- pcs-handle = <&serdes9>;
- phy-mode = "1000base-x";
- sfp = <&sfp1>;
- led-set = <2>;
- managed = "in-band-status";
- };
-
- port at 28 {
- ethernet = <ðernet0>;
- reg = <28>;
- phy-mode = "internal";
- fixed-link {
- speed = <10000>;
- full-duplex;
- };
- };
- };
-};
diff --git a/target/linux/realtek/dts/rtl9302_zyxel_xgs1210-12-common.dtsi b/target/linux/realtek/dts/rtl9302_zyxel_xgs1x10-12-common.dtsi
similarity index 80%
copy from target/linux/realtek/dts/rtl9302_zyxel_xgs1210-12-common.dtsi
copy to target/linux/realtek/dts/rtl9302_zyxel_xgs1x10-12-common.dtsi
index 9412d26976..5293a5265c 100644
--- a/target/linux/realtek/dts/rtl9302_zyxel_xgs1210-12-common.dtsi
+++ b/target/linux/realtek/dts/rtl9302_zyxel_xgs1x10-12-common.dtsi
@@ -6,7 +6,6 @@
#include <dt-bindings/input/input.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/leds/common.h>
-#include <dt-bindings/thermal/thermal.h>
/ {
aliases {
@@ -16,16 +15,6 @@
led-upgrade = &led_pwr_sys;
};
- keys {
- compatible = "gpio-keys";
-
- mode {
- label = "reset";
- gpios = <&gpio0 22 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_RESTART>;
- };
- };
-
leds {
compatible = "gpio-leds";
@@ -97,55 +86,6 @@
};
};
-&spi0 {
- status = "okay";
- flash at 0 {
- compatible = "jedec,spi-nor";
- reg = <0>;
- spi-max-frequency = <10000000>;
-
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- partition at 0 {
- label = "u-boot";
- reg = <0x0 0xe0000>;
- read-only;
- };
- partition at e0000 {
- label = "u-boot-env";
- reg = <0xe0000 0x10000>;
- };
- partition at f0000 {
- label = "u-boot-env2";
- reg = <0xf0000 0x10000>;
- read-only;
- };
- partition at 100000 {
- label = "jffs2-cfg";
- reg = <0x100000 0x100000>;
- };
- partition at 200000 {
- label = "jffs2-log";
- reg = <0x200000 0x100000>;
- };
- partition at b300000 {
- label = "firmware";
- reg = <0x300000 0xce0000>;
- compatible = "openwrt,uimage", "denx,uimage";
- openwrt,ih-magic = <0x93001210>;
- };
- partition at fe0000 {
- label = "log";
- reg = <0xfe0000 0x20000>;
- read-only;
- };
- };
- };
-};
-
&mdio_bus0 {
/* External RTL8218D PHY */
phy0: ethernet-phy at 0 {
@@ -190,6 +130,20 @@
compatible = "ethernet-phy-ieee802.3-c22";
rtl9300,smi-address = <0 7>;
};
+
+ phy24: ethernet-phy at 24 {
+ reg = <24>;
+ compatible = "ethernet-phy-ieee802.3-c45";
+ // Disabled because we do not know how to bring up again
+ // reset-gpios = <&gpio0 21 GPIO_ACTIVE_LOW>;
+ };
+
+ phy25: ethernet-phy at 25 {
+ reg = <25>;
+ compatible = "ethernet-phy-ieee802.3-c45";
+ // Disabled because we do not know how to bring up again
+ // reset-gpios = <&gpio0 21 GPIO_ACTIVE_LOW>;
+ };
};
&switch0 {
@@ -262,6 +216,23 @@
led-set = <0>;
};
+ port at 24 {
+ reg = <24>;
+ label = "lan9";
+ pcs-handle = <&serdes6>;
+ phy-handle = <&phy24>;
+ phy-mode = "2500base-x";
+ led-set = <1>;
+ };
+ port at 25 {
+ reg = <25>;
+ label = "lan10";
+ pcs-handle = <&serdes7>;
+ phy-handle = <&phy25>;
+ phy-mode = "2500base-x";
+ led-set = <1>;
+ };
+
port at 26 {
reg = <26>;
label = "lan11";
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