[openwrt/openwrt] qualcommax: ipq50xx: use latest v9 PCIe DTS patch
LEDE Commits
lede-commits at lists.infradead.org
Tue May 13 10:58:28 PDT 2025
robimarko pushed a commit to openwrt/openwrt.git, branch main:
https://git.openwrt.org/8aad4cd43dbaf805ef5b6203f3bb00942e75ecfe
commit 8aad4cd43dbaf805ef5b6203f3bb00942e75ecfe
Author: Robert Marko <robimarko at gmail.com>
AuthorDate: Tue May 13 11:44:27 2025 +0200
qualcommax: ipq50xx: use latest v9 PCIe DTS patch
Use the latest v9 PCIe DTS patch that is pending upstream, notable change
being that it includes PCIe bridge nodes.
Link: https://github.com/openwrt/openwrt/pull/18789
Signed-off-by: Robert Marko <robimarko at gmail.com>
---
...4-dts-qcom-IPQ5018-add-PCIe-related-nodes.patch | 216 ------------
...4-dts-qcom-ipq5018-Add-PCIe-related-nodes.patch | 370 +++++++++++++++++++++
...0302-arm64-dts-qcom-IPQ5018-add-TCSR-node.patch | 2 +-
.../0306-arm64-dts-qcom-ipq5018-Add-PWM-node.patch | 2 +-
...4-arm64-dts-qcom-ipq5018-Add-crypto-nodes.patch | 4 +-
...0337-arm64-dts-qcom-ipq5018-Add-PRNG-node.patch | 2 +-
...rm64-dts-qcom-ipq5018-Add-QUP1-UART2-node.patch | 2 +-
...-arm64-dts-qcom-ipq5018-Add-QUP3-I2C-node.patch | 2 +-
...-arm64-dts-qcom-ipq5018-Add-SPI-nand-node.patch | 2 +-
...64-dts-qcom-ipq5018-Add-ethernet-cmn-node.patch | 2 +-
...0712-arm64-dts-qcom-ipq5018-add-mdio-node.patch | 2 +-
...13-arm64-dts-qcom-ipq5018-add-ge_phy-node.patch | 4 +-
...6-arm64-dts-qcom-ipq5018-add-wifi-support.patch | 2 +-
13 files changed, 383 insertions(+), 229 deletions(-)
diff --git a/target/linux/qualcommax/patches-6.6/0162-arm64-dts-qcom-IPQ5018-add-PCIe-related-nodes.patch b/target/linux/qualcommax/patches-6.6/0162-arm64-dts-qcom-IPQ5018-add-PCIe-related-nodes.patch
deleted file mode 100644
index f51d103508..0000000000
--- a/target/linux/qualcommax/patches-6.6/0162-arm64-dts-qcom-IPQ5018-add-PCIe-related-nodes.patch
+++ /dev/null
@@ -1,216 +0,0 @@
-From: Nitheesh Sekar <quic_nsekar at quicinc.com>
-Subject: [PATCH] arm64: dts: qcom: ipq5018: Add PCIe related nodes
-Date: Tue, 3 Oct 2023 17:38:45 +0530
-
-Add phy and controller nodes for PCIe0 and PCIe1.
-PCIe0 is 2-lane Gen2 and PCIe1 is 1-lane Gen2.
-
-Signed-off-by: Nitheesh Sekar <quic_nsekar at quicinc.com>
-Signed-off-by: George Moussalem <george.moussalem at outlook.com>
----
- arch/arm64/boot/dts/qcom/ipq5018.dtsi | 186 +++++++++++++++++++++++++-
- 1 file changed, 184 insertions(+), 2 deletions(-)
-
---- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi
-+++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi
-@@ -149,6 +149,42 @@
- status = "disabled";
- };
-
-+ pcie1_phy: phy at 7e000{
-+ compatible = "qcom,ipq5018-uniphy-pcie-phy";
-+ reg = <0x0007e000 0x800>;
-+
-+ clocks = <&gcc GCC_PCIE1_PIPE_CLK>;
-+
-+ resets = <&gcc GCC_PCIE1_PHY_BCR>,
-+ <&gcc GCC_PCIE1PHY_PHY_BCR>;
-+
-+ #clock-cells = <0>;
-+
-+ #phy-cells = <0>;
-+
-+ num-lanes = <1>;
-+
-+ status = "disabled";
-+ };
-+
-+ pcie0_phy: phy at 86000{
-+ compatible = "qcom,ipq5018-uniphy-pcie-phy";
-+ reg = <0x00086000 0x800>;
-+
-+ clocks = <&gcc GCC_PCIE0_PIPE_CLK>;
-+
-+ resets = <&gcc GCC_PCIE0_PHY_BCR>,
-+ <&gcc GCC_PCIE0PHY_PHY_BCR>;
-+
-+ #clock-cells = <0>;
-+
-+ #phy-cells = <0>;
-+
-+ num-lanes = <2>;
-+
-+ status = "disabled";
-+ };
-+
- qfprom: qfprom at a0000 {
- compatible = "qcom,ipq5018-qfprom", "qcom,qfprom";
- reg = <0xa0000 0x1000>;
-@@ -283,8 +319,8 @@
- reg = <0x01800000 0x80000>;
- clocks = <&xo_board_clk>,
- <&sleep_clk>,
-- <0>,
-- <0>,
-+ <&pcie0_phy>,
-+ <&pcie1_phy>,
- <0>,
- <0>,
- <0>,
-@@ -501,6 +537,146 @@
- status = "disabled";
- };
- };
-+
-+ pcie1: pcie at 80000000 {
-+ compatible = "qcom,pcie-ipq5018";
-+ reg = <0x80000000 0xf1d>,
-+ <0x80000f20 0xa8>,
-+ <0x80001000 0x1000>,
-+ <0x00078000 0x3000>,
-+ <0x80100000 0x1000>;
-+ reg-names = "dbi",
-+ "elbi",
-+ "atu",
-+ "parf",
-+ "config";
-+ device_type = "pci";
-+ linux,pci-domain = <0>;
-+ bus-range = <0x00 0xff>;
-+ num-lanes = <1>;
-+ max-link-speed = <2>;
-+ #address-cells = <3>;
-+ #size-cells = <2>;
-+
-+ phys = <&pcie1_phy>;
-+ phy-names ="pciephy";
-+
-+ ranges = <0x81000000 0 0x80200000 0x80200000 0 0x00100000>, /* I/O */
-+ <0x82000000 0 0x80300000 0x80300000 0 0x10000000>; /* MEM */
-+
-+ #interrupt-cells = <1>;
-+ interrupt-map-mask = <0 0 0 0x7>;
-+ interrupt-map = <0 0 0 1 &intc 0 142 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
-+ <0 0 0 2 &intc 0 143 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
-+ <0 0 0 3 &intc 0 144 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
-+ <0 0 0 4 &intc 0 145 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
-+
-+ interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
-+ interrupt-names = "global_irq";
-+
-+ clocks = <&gcc GCC_SYS_NOC_PCIE1_AXI_CLK>,
-+ <&gcc GCC_PCIE1_AXI_M_CLK>,
-+ <&gcc GCC_PCIE1_AXI_S_CLK>,
-+ <&gcc GCC_PCIE1_AHB_CLK>,
-+ <&gcc GCC_PCIE1_AUX_CLK>,
-+ <&gcc GCC_PCIE1_AXI_S_BRIDGE_CLK>;
-+ clock-names = "iface",
-+ "axi_m",
-+ "axi_s",
-+ "ahb",
-+ "aux",
-+ "axi_bridge";
-+
-+ resets = <&gcc GCC_PCIE1_PIPE_ARES>,
-+ <&gcc GCC_PCIE1_SLEEP_ARES>,
-+ <&gcc GCC_PCIE1_CORE_STICKY_ARES>,
-+ <&gcc GCC_PCIE1_AXI_MASTER_ARES>,
-+ <&gcc GCC_PCIE1_AXI_SLAVE_ARES>,
-+ <&gcc GCC_PCIE1_AHB_ARES>,
-+ <&gcc GCC_PCIE1_AXI_MASTER_STICKY_ARES>,
-+ <&gcc GCC_PCIE1_AXI_SLAVE_STICKY_ARES>;
-+ reset-names = "pipe",
-+ "sleep",
-+ "sticky",
-+ "axi_m",
-+ "axi_s",
-+ "ahb",
-+ "axi_m_sticky",
-+ "axi_s_sticky";
-+
-+ msi-map = <0x0 &v2m0 0x0 0xff8>;
-+ status = "disabled";
-+ };
-+
-+ pcie0: pcie at a0000000 {
-+ compatible = "qcom,pcie-ipq5018";
-+ reg = <0xa0000000 0xf1d>,
-+ <0xa0000f20 0xa8>,
-+ <0xa0001000 0x1000>,
-+ <0x00080000 0x3000>,
-+ <0xa0100000 0x1000>;
-+ reg-names = "dbi",
-+ "elbi",
-+ "atu",
-+ "parf",
-+ "config";
-+ device_type = "pci";
-+ linux,pci-domain = <1>;
-+ bus-range = <0x00 0xff>;
-+ num-lanes = <2>;
-+ max-link-speed = <2>;
-+ #address-cells = <3>;
-+ #size-cells = <2>;
-+
-+ phys = <&pcie0_phy>;
-+ phy-names ="pciephy";
-+
-+ ranges = <0x81000000 0 0xa0200000 0xa0200000 0 0x00100000>, /* I/O */
-+ <0x82000000 0 0xa0300000 0xa0300000 0 0x10000000>; /* MEM */
-+
-+ #interrupt-cells = <1>;
-+ interrupt-map-mask = <0 0 0 0x7>;
-+ interrupt-map = <0 0 0 1 &intc 0 75 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
-+ <0 0 0 2 &intc 0 78 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
-+ <0 0 0 3 &intc 0 79 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
-+ <0 0 0 4 &intc 0 83 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
-+
-+ interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
-+ interrupt-names = "global_irq";
-+
-+ clocks = <&gcc GCC_SYS_NOC_PCIE0_AXI_CLK>,
-+ <&gcc GCC_PCIE0_AXI_M_CLK>,
-+ <&gcc GCC_PCIE0_AXI_S_CLK>,
-+ <&gcc GCC_PCIE0_AHB_CLK>,
-+ <&gcc GCC_PCIE0_AUX_CLK>,
-+ <&gcc GCC_PCIE0_AXI_S_BRIDGE_CLK>;
-+ clock-names = "iface",
-+ "axi_m",
-+ "axi_s",
-+ "ahb",
-+ "aux",
-+ "axi_bridge";
-+
-+ resets = <&gcc GCC_PCIE0_PIPE_ARES>,
-+ <&gcc GCC_PCIE0_SLEEP_ARES>,
-+ <&gcc GCC_PCIE0_CORE_STICKY_ARES>,
-+ <&gcc GCC_PCIE0_AXI_MASTER_ARES>,
-+ <&gcc GCC_PCIE0_AXI_SLAVE_ARES>,
-+ <&gcc GCC_PCIE0_AHB_ARES>,
-+ <&gcc GCC_PCIE0_AXI_MASTER_STICKY_ARES>,
-+ <&gcc GCC_PCIE0_AXI_SLAVE_STICKY_ARES>;
-+ reset-names = "pipe",
-+ "sleep",
-+ "sticky",
-+ "axi_m",
-+ "axi_s",
-+ "ahb",
-+ "axi_m_sticky",
-+ "axi_s_sticky";
-+
-+ msi-map = <0x0 &v2m0 0x0 0xff8>;
-+ status = "disabled";
-+ };
- };
-
- thermal-zones {
diff --git a/target/linux/qualcommax/patches-6.6/0162-arm64-dts-qcom-ipq5018-Add-PCIe-related-nodes.patch b/target/linux/qualcommax/patches-6.6/0162-arm64-dts-qcom-ipq5018-Add-PCIe-related-nodes.patch
new file mode 100644
index 0000000000..d78b05d665
--- /dev/null
+++ b/target/linux/qualcommax/patches-6.6/0162-arm64-dts-qcom-ipq5018-Add-PCIe-related-nodes.patch
@@ -0,0 +1,370 @@
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+ Sat, 26 Apr 2025 08:47:50 +0000 (UTC)
+Date: Sat, 26 Apr 2025 12:47:20 +0400
+Subject: [PATCH v9 1/2] arm64: dts: qcom: ipq5018: Add PCIe related nodes
+Precedence: bulk
+X-Mailing-List: linux-arm-msm at vger.kernel.org
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+In-Reply-To: <20250426-ipq5018-pcie-v9-0-1f0dca6c205b at outlook.com>
+To: Vinod Koul <vkoul at kernel.org>,
+ Kishon Vijay Abraham I <kishon at kernel.org>, Rob Herring <robh at kernel.org>,
+ Krzysztof Kozlowski <krzk+dt at kernel.org>,
+ Conor Dooley <conor+dt at kernel.org>,
+ Nitheesh Sekar <quic_nsekar at quicinc.com>,
+ Varadarajan Narayanan <quic_varada at quicinc.com>,
+ Bjorn Helgaas <bhelgaas at google.com>,
+ Lorenzo Pieralisi <lpieralisi at kernel.org>, =?utf-8?q?Krzysztof_Wilczy?=
+ =?utf-8?q?=C5=84ski?= <kw at linux.com>,
+ Manivannan Sadhasivam <manivannan.sadhasivam at linaro.org>,
+ Bjorn Andersson <andersson at kernel.org>,
+ Konrad Dybcio <konradybcio at kernel.org>,
+ Praveenkumar I <quic_ipkumar at quicinc.com>
+Cc: linux-arm-msm at vger.kernel.org, linux-phy at lists.infradead.org,
+ devicetree at vger.kernel.org, linux-kernel at vger.kernel.org,
+ linux-pci at vger.kernel.org, George Moussalem <george.moussalem at outlook.com>,
+ 20250317100029.881286-1-quic_varada at quicinc.com,
+ 20250317100029.881286-2-quic_varada at quicinc.com,
+ Sricharan R <quic_srichara at quicinc.com>,
+ Dmitry Baryshkov <dmitry.baryshkov at oss.qualcomm.com>,
+ Konrad Dybcio <konrad.dybcio at oss.qualcomm.com>
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+From: George Moussalem <george.moussalem at outlook.com>
+
+From: Nitheesh Sekar <quic_nsekar at quicinc.com>
+
+Add phy and controller nodes for a 2-lane Gen2 and
+a 1-lane Gen2 PCIe bus. IPQ5018 has 8 MSI SPI interrupts and
+one global interrupt.
+
+NOTE: the PCIe controller supports gen3, yet the phy is limited to gen2.
+
+Signed-off-by: Nitheesh Sekar <quic_nsekar at quicinc.com>
+Signed-off-by: Sricharan R <quic_srichara at quicinc.com>
+Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam at linaro.org>
+Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov at oss.qualcomm.com>
+Reviewed-by: Konrad Dybcio <konrad.dybcio at oss.qualcomm.com>
+Signed-off-by: George Moussalem <george.moussalem at outlook.com>
+---
+ arch/arm64/boot/dts/qcom/ipq5018.dtsi | 238 +++++++++++++++++++++++++++++++++-
+ 1 file changed, 236 insertions(+), 2 deletions(-)
+
+--- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi
++++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi
+@@ -260,6 +260,40 @@
+ #thermal-sensor-cells = <1>;
+ };
+
++ pcie1_phy: phy at 7e000 {
++ compatible = "qcom,ipq5018-uniphy-pcie-phy";
++ reg = <0x0007e000 0x800>;
++
++ clocks = <&gcc GCC_PCIE1_PIPE_CLK>;
++
++ resets = <&gcc GCC_PCIE1_PHY_BCR>,
++ <&gcc GCC_PCIE1PHY_PHY_BCR>;
++
++ #clock-cells = <0>;
++ #phy-cells = <0>;
++
++ num-lanes = <1>;
++
++ status = "disabled";
++ };
++
++ pcie0_phy: phy at 86000 {
++ compatible = "qcom,ipq5018-uniphy-pcie-phy";
++ reg = <0x00086000 0x1000>;
++
++ clocks = <&gcc GCC_PCIE0_PIPE_CLK>;
++
++ resets = <&gcc GCC_PCIE0_PHY_BCR>,
++ <&gcc GCC_PCIE0PHY_PHY_BCR>;
++
++ #clock-cells = <0>;
++ #phy-cells = <0>;
++
++ num-lanes = <2>;
++
++ status = "disabled";
++ };
++
+ tlmm: pinctrl at 1000000 {
+ compatible = "qcom,ipq5018-tlmm";
+ reg = <0x01000000 0x300000>;
+@@ -283,8 +317,8 @@
+ reg = <0x01800000 0x80000>;
+ clocks = <&xo_board_clk>,
+ <&sleep_clk>,
+- <0>,
+- <0>,
++ <&pcie0_phy>,
++ <&pcie1_phy>,
+ <0>,
+ <0>,
+ <0>,
+@@ -501,6 +535,206 @@
+ status = "disabled";
+ };
+ };
++
++ pcie1: pcie at 80000000 {
++ compatible = "qcom,pcie-ipq5018";
++ reg = <0x80000000 0xf1d>,
++ <0x80000f20 0xa8>,
++ <0x80001000 0x1000>,
++ <0x00078000 0x3000>,
++ <0x80100000 0x1000>,
++ <0x0007b000 0x1000>;
++ reg-names = "dbi",
++ "elbi",
++ "atu",
++ "parf",
++ "config",
++ "mhi";
++ device_type = "pci";
++ linux,pci-domain = <1>;
++ bus-range = <0x00 0xff>;
++ num-lanes = <1>;
++ #address-cells = <3>;
++ #size-cells = <2>;
++
++ /* The controller supports Gen3, but the connected PHY is Gen2-capable */
++ max-link-speed = <2>;
++
++ phys = <&pcie1_phy>;
++ phy-names ="pciephy";
++
++ ranges = <0x01000000 0 0x00000000 0x80200000 0 0x00100000>,
++ <0x02000000 0 0x80300000 0x80300000 0 0x10000000>;
++
++ msi-map = <0x0 &v2m0 0x0 0xff8>;
++
++ interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
++ <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
++ <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
++ <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
++ <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
++ <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
++ <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
++ <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
++ <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
++ interrupt-names = "msi0",
++ "msi1",
++ "msi2",
++ "msi3",
++ "msi4",
++ "msi5",
++ "msi6",
++ "msi7",
++ "global";
++
++ #interrupt-cells = <1>;
++ interrupt-map-mask = <0 0 0 0x7>;
++ interrupt-map = <0 0 0 1 &intc 0 0 142 IRQ_TYPE_LEVEL_HIGH>,
++ <0 0 0 2 &intc 0 0 143 IRQ_TYPE_LEVEL_HIGH>,
++ <0 0 0 3 &intc 0 0 144 IRQ_TYPE_LEVEL_HIGH>,
++ <0 0 0 4 &intc 0 0 145 IRQ_TYPE_LEVEL_HIGH>;
++
++ clocks = <&gcc GCC_SYS_NOC_PCIE1_AXI_CLK>,
++ <&gcc GCC_PCIE1_AXI_M_CLK>,
++ <&gcc GCC_PCIE1_AXI_S_CLK>,
++ <&gcc GCC_PCIE1_AHB_CLK>,
++ <&gcc GCC_PCIE1_AUX_CLK>,
++ <&gcc GCC_PCIE1_AXI_S_BRIDGE_CLK>;
++ clock-names = "iface",
++ "axi_m",
++ "axi_s",
++ "ahb",
++ "aux",
++ "axi_bridge";
++
++ resets = <&gcc GCC_PCIE1_PIPE_ARES>,
++ <&gcc GCC_PCIE1_SLEEP_ARES>,
++ <&gcc GCC_PCIE1_CORE_STICKY_ARES>,
++ <&gcc GCC_PCIE1_AXI_MASTER_ARES>,
++ <&gcc GCC_PCIE1_AXI_SLAVE_ARES>,
++ <&gcc GCC_PCIE1_AHB_ARES>,
++ <&gcc GCC_PCIE1_AXI_MASTER_STICKY_ARES>,
++ <&gcc GCC_PCIE1_AXI_SLAVE_STICKY_ARES>;
++ reset-names = "pipe",
++ "sleep",
++ "sticky",
++ "axi_m",
++ "axi_s",
++ "ahb",
++ "axi_m_sticky",
++ "axi_s_sticky";
++
++ status = "disabled";
++
++ pcie at 0 {
++ device_type = "pci";
++ reg = <0x0 0x0 0x0 0x0 0x0>;
++
++ #address-cells = <3>;
++ #size-cells = <2>;
++ ranges;
++ };
++ };
++
++ pcie0: pcie at a0000000 {
++ compatible = "qcom,pcie-ipq5018";
++ reg = <0xa0000000 0xf1d>,
++ <0xa0000f20 0xa8>,
++ <0xa0001000 0x1000>,
++ <0x00080000 0x3000>,
++ <0xa0100000 0x1000>,
++ <0x00083000 0x1000>;
++ reg-names = "dbi",
++ "elbi",
++ "atu",
++ "parf",
++ "config",
++ "mhi";
++ device_type = "pci";
++ linux,pci-domain = <0>;
++ bus-range = <0x00 0xff>;
++ num-lanes = <2>;
++ #address-cells = <3>;
++ #size-cells = <2>;
++
++ /* The controller supports Gen3, but the connected PHY is Gen2-capable */
++ max-link-speed = <2>;
++
++ phys = <&pcie0_phy>;
++ phy-names ="pciephy";
++
++ ranges = <0x01000000 0 0x00000000 0xa0200000 0 0x00100000>,
++ <0x02000000 0 0xa0300000 0xa0300000 0 0x10000000>;
++
++ msi-map = <0x0 &v2m0 0x0 0xff8>;
++
++ interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
++ <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
++ <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
++ <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
++ <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
++ <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>,
++ <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
++ <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
++ <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
++ interrupt-names = "msi0",
++ "msi1",
++ "msi2",
++ "msi3",
++ "msi4",
++ "msi5",
++ "msi6",
++ "msi7",
++ "global";
++
++ #interrupt-cells = <1>;
++ interrupt-map-mask = <0 0 0 0x7>;
++ interrupt-map = <0 0 0 1 &intc 0 0 75 IRQ_TYPE_LEVEL_HIGH>,
++ <0 0 0 2 &intc 0 0 78 IRQ_TYPE_LEVEL_HIGH>,
++ <0 0 0 3 &intc 0 0 79 IRQ_TYPE_LEVEL_HIGH>,
++ <0 0 0 4 &intc 0 0 83 IRQ_TYPE_LEVEL_HIGH>;
++
++ clocks = <&gcc GCC_SYS_NOC_PCIE0_AXI_CLK>,
++ <&gcc GCC_PCIE0_AXI_M_CLK>,
++ <&gcc GCC_PCIE0_AXI_S_CLK>,
++ <&gcc GCC_PCIE0_AHB_CLK>,
++ <&gcc GCC_PCIE0_AUX_CLK>,
++ <&gcc GCC_PCIE0_AXI_S_BRIDGE_CLK>;
++ clock-names = "iface",
++ "axi_m",
++ "axi_s",
++ "ahb",
++ "aux",
++ "axi_bridge";
++
++ resets = <&gcc GCC_PCIE0_PIPE_ARES>,
++ <&gcc GCC_PCIE0_SLEEP_ARES>,
++ <&gcc GCC_PCIE0_CORE_STICKY_ARES>,
++ <&gcc GCC_PCIE0_AXI_MASTER_ARES>,
++ <&gcc GCC_PCIE0_AXI_SLAVE_ARES>,
++ <&gcc GCC_PCIE0_AHB_ARES>,
++ <&gcc GCC_PCIE0_AXI_MASTER_STICKY_ARES>,
++ <&gcc GCC_PCIE0_AXI_SLAVE_STICKY_ARES>;
++ reset-names = "pipe",
++ "sleep",
++ "sticky",
++ "axi_m",
++ "axi_s",
++ "ahb",
++ "axi_m_sticky",
++ "axi_s_sticky";
++
++ status = "disabled";
++
++ pcie at 0 {
++ device_type = "pci";
++ reg = <0x0 0x0 0x0 0x0 0x0>;
++
++ #address-cells = <3>;
++ #size-cells = <2>;
++ ranges;
++ };
++ };
+ };
+
+ thermal-zones {
diff --git a/target/linux/qualcommax/patches-6.6/0302-arm64-dts-qcom-IPQ5018-add-TCSR-node.patch b/target/linux/qualcommax/patches-6.6/0302-arm64-dts-qcom-IPQ5018-add-TCSR-node.patch
index 7a0031666d..81c706f966 100644
--- a/target/linux/qualcommax/patches-6.6/0302-arm64-dts-qcom-IPQ5018-add-TCSR-node.patch
+++ b/target/linux/qualcommax/patches-6.6/0302-arm64-dts-qcom-IPQ5018-add-TCSR-node.patch
@@ -8,7 +8,7 @@ Signed-off-by: George Moussalem <george.moussalem at outlook.com>
---
--- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi
-@@ -337,6 +337,11 @@
+@@ -335,6 +335,11 @@
#hwlock-cells = <1>;
};
diff --git a/target/linux/qualcommax/patches-6.6/0306-arm64-dts-qcom-ipq5018-Add-PWM-node.patch b/target/linux/qualcommax/patches-6.6/0306-arm64-dts-qcom-ipq5018-Add-PWM-node.patch
index d60e916971..b72f45ed3f 100644
--- a/target/linux/qualcommax/patches-6.6/0306-arm64-dts-qcom-ipq5018-Add-PWM-node.patch
+++ b/target/linux/qualcommax/patches-6.6/0306-arm64-dts-qcom-ipq5018-Add-PWM-node.patch
@@ -8,7 +8,7 @@ Signed-off-by: George Moussalem <george.moussalem at outlook.com>
---
--- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi
-@@ -343,6 +343,16 @@
+@@ -341,6 +341,16 @@
reg = <0x01937000 0x21000>;
};
diff --git a/target/linux/qualcommax/patches-6.6/0324-arm64-dts-qcom-ipq5018-Add-crypto-nodes.patch b/target/linux/qualcommax/patches-6.6/0324-arm64-dts-qcom-ipq5018-Add-crypto-nodes.patch
index 57d434271f..bd48a87815 100644
--- a/target/linux/qualcommax/patches-6.6/0324-arm64-dts-qcom-ipq5018-Add-crypto-nodes.patch
+++ b/target/linux/qualcommax/patches-6.6/0324-arm64-dts-qcom-ipq5018-Add-crypto-nodes.patch
@@ -8,8 +8,8 @@ Signed-off-by: George Moussalem <george.moussalem at outlook.com>
---
--- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi
-@@ -297,6 +297,30 @@
- #thermal-sensor-cells = <1>;
+@@ -295,6 +295,30 @@
+ status = "disabled";
};
+ cryptobam: dma-controller at 704000 {
diff --git a/target/linux/qualcommax/patches-6.6/0337-arm64-dts-qcom-ipq5018-Add-PRNG-node.patch b/target/linux/qualcommax/patches-6.6/0337-arm64-dts-qcom-ipq5018-Add-PRNG-node.patch
index 87d9bdb270..cbfa401e06 100644
--- a/target/linux/qualcommax/patches-6.6/0337-arm64-dts-qcom-ipq5018-Add-PRNG-node.patch
+++ b/target/linux/qualcommax/patches-6.6/0337-arm64-dts-qcom-ipq5018-Add-PRNG-node.patch
@@ -8,7 +8,7 @@ Signed-off-by: George Moussalem <george.moussalem at outlook.com>
---
--- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi
-@@ -258,6 +258,14 @@
+@@ -222,6 +222,14 @@
};
};
diff --git a/target/linux/qualcommax/patches-6.6/0339-arm64-dts-qcom-ipq5018-Add-QUP1-UART2-node.patch b/target/linux/qualcommax/patches-6.6/0339-arm64-dts-qcom-ipq5018-Add-QUP1-UART2-node.patch
index 72085061f8..de1df4579b 100644
--- a/target/linux/qualcommax/patches-6.6/0339-arm64-dts-qcom-ipq5018-Add-QUP1-UART2-node.patch
+++ b/target/linux/qualcommax/patches-6.6/0339-arm64-dts-qcom-ipq5018-Add-QUP1-UART2-node.patch
@@ -8,7 +8,7 @@ Signed-off-by: George Moussalem <george.moussalem at outlook.com>
---
--- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi
-@@ -422,6 +422,16 @@
+@@ -420,6 +420,16 @@
status = "disabled";
};
diff --git a/target/linux/qualcommax/patches-6.6/0340-arm64-dts-qcom-ipq5018-Add-QUP3-I2C-node.patch b/target/linux/qualcommax/patches-6.6/0340-arm64-dts-qcom-ipq5018-Add-QUP3-I2C-node.patch
index 5447e78fab..c8802806f5 100644
--- a/target/linux/qualcommax/patches-6.6/0340-arm64-dts-qcom-ipq5018-Add-QUP3-I2C-node.patch
+++ b/target/linux/qualcommax/patches-6.6/0340-arm64-dts-qcom-ipq5018-Add-QUP3-I2C-node.patch
@@ -8,7 +8,7 @@ Signed-off-by: George Moussalem <george.moussalem at outlook.com>
---
--- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi
-@@ -446,6 +446,21 @@
+@@ -444,6 +444,21 @@
status = "disabled";
};
diff --git a/target/linux/qualcommax/patches-6.6/0421-arm64-dts-qcom-ipq5018-Add-SPI-nand-node.patch b/target/linux/qualcommax/patches-6.6/0421-arm64-dts-qcom-ipq5018-Add-SPI-nand-node.patch
index 2d4c8c80b6..cc6df41db5 100644
--- a/target/linux/qualcommax/patches-6.6/0421-arm64-dts-qcom-ipq5018-Add-SPI-nand-node.patch
+++ b/target/linux/qualcommax/patches-6.6/0421-arm64-dts-qcom-ipq5018-Add-SPI-nand-node.patch
@@ -13,7 +13,7 @@ Signed-off-by: George Moussalem <george.moussalem at outlook.com>
--- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi
-@@ -461,6 +461,36 @@
+@@ -459,6 +459,36 @@
status = "disabled";
};
diff --git a/target/linux/qualcommax/patches-6.6/0704-arm64-dts-qcom-ipq5018-Add-ethernet-cmn-node.patch b/target/linux/qualcommax/patches-6.6/0704-arm64-dts-qcom-ipq5018-Add-ethernet-cmn-node.patch
index 8127656ddd..6a0e2efdf8 100644
--- a/target/linux/qualcommax/patches-6.6/0704-arm64-dts-qcom-ipq5018-Add-ethernet-cmn-node.patch
+++ b/target/linux/qualcommax/patches-6.6/0704-arm64-dts-qcom-ipq5018-Add-ethernet-cmn-node.patch
@@ -23,7 +23,7 @@ Signed-off-by: Ziyang Huang <hzyitc at outlook.com>
sleep_clk: sleep-clk {
compatible = "fixed-clock";
#clock-cells = <0>;
-@@ -186,6 +192,19 @@
+@@ -150,6 +156,19 @@
status = "disabled";
};
diff --git a/target/linux/qualcommax/patches-6.6/0712-arm64-dts-qcom-ipq5018-add-mdio-node.patch b/target/linux/qualcommax/patches-6.6/0712-arm64-dts-qcom-ipq5018-add-mdio-node.patch
index c431383a8b..2d056b9f3c 100644
--- a/target/linux/qualcommax/patches-6.6/0712-arm64-dts-qcom-ipq5018-add-mdio-node.patch
+++ b/target/linux/qualcommax/patches-6.6/0712-arm64-dts-qcom-ipq5018-add-mdio-node.patch
@@ -14,7 +14,7 @@ Signed-off-by: George Moussalem <george.moussalem at outlook.com>
--- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi
-@@ -192,6 +192,30 @@
+@@ -156,6 +156,30 @@
status = "disabled";
};
diff --git a/target/linux/qualcommax/patches-6.6/0713-arm64-dts-qcom-ipq5018-add-ge_phy-node.patch b/target/linux/qualcommax/patches-6.6/0713-arm64-dts-qcom-ipq5018-add-ge_phy-node.patch
index d72261306d..916bdc4864 100644
--- a/target/linux/qualcommax/patches-6.6/0713-arm64-dts-qcom-ipq5018-add-ge_phy-node.patch
+++ b/target/linux/qualcommax/patches-6.6/0713-arm64-dts-qcom-ipq5018-add-ge_phy-node.patch
@@ -13,7 +13,7 @@ Signed-off-by: George Moussalem <george.moussalem at outlook.com>
--- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi
-@@ -202,6 +202,21 @@
+@@ -166,6 +166,21 @@
clock-names = "gcc_mdio_ahb_clk";
status = "disabled";
@@ -35,7 +35,7 @@ Signed-off-by: George Moussalem <george.moussalem at outlook.com>
};
mdio1: mdio at 90000 {
-@@ -398,8 +413,8 @@
+@@ -396,8 +411,8 @@
<&pcie0_phy>,
<&pcie1_phy>,
<0>,
diff --git a/target/linux/qualcommax/patches-6.6/0816-arm64-dts-qcom-ipq5018-add-wifi-support.patch b/target/linux/qualcommax/patches-6.6/0816-arm64-dts-qcom-ipq5018-add-wifi-support.patch
index 4c766d6e0d..d158688928 100644
--- a/target/linux/qualcommax/patches-6.6/0816-arm64-dts-qcom-ipq5018-add-wifi-support.patch
+++ b/target/linux/qualcommax/patches-6.6/0816-arm64-dts-qcom-ipq5018-add-wifi-support.patch
@@ -13,7 +13,7 @@ Signed-off-by: George Moussalem <george.moussalem at outlook.com>
---
--- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi
-@@ -699,6 +699,225 @@
+@@ -697,6 +697,225 @@
};
};
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