[openwrt/openwrt] qualcommbe: add PCS driver fixes
LEDE Commits
lede-commits at lists.infradead.org
Wed Jun 25 01:20:43 PDT 2025
robimarko pushed a commit to openwrt/openwrt.git, branch main:
https://git.openwrt.org/c88c2d40d0291328a954eb2d418a301eb99a4bad
commit c88c2d40d0291328a954eb2d418a301eb99a4bad
Author: Mantas Pucka <mantas at 8devices.com>
AuthorDate: Thu Jun 5 10:41:20 2025 +0300
qualcommbe: add PCS driver fixes
After update to v6.12 some PCS driver fixes were dropped and additional
are needed due to updated driver.
Signed-off-by: Mantas Pucka <mantas at 8devices.com>
Link: https://github.com/openwrt/openwrt/pull/18435
Signed-off-by: Robert Marko <robimarko at gmail.com>
---
...m64-dts-qcom-ipq9574-add-PCS-uniphy-nodes.patch | 6 +-
...-uniphy-control-MISC2-register-for-2.5G-s.patch | 72 ++++++++++++++++++++++
...-uniphy-keep-autoneg-enabled-in-SGMII-mod.patch | 25 ++++++++
...cs-ipq-uniphy-fix-USXGMII-link-up-failure.patch | 24 ++++++++
4 files changed, 124 insertions(+), 3 deletions(-)
diff --git a/target/linux/qualcommbe/patches-6.12/0322-arm64-dts-qcom-ipq9574-add-PCS-uniphy-nodes.patch b/target/linux/qualcommbe/patches-6.12/0322-arm64-dts-qcom-ipq9574-add-PCS-uniphy-nodes.patch
index e08ab5308d..3d2219813c 100644
--- a/target/linux/qualcommbe/patches-6.12/0322-arm64-dts-qcom-ipq9574-add-PCS-uniphy-nodes.patch
+++ b/target/linux/qualcommbe/patches-6.12/0322-arm64-dts-qcom-ipq9574-add-PCS-uniphy-nodes.patch
@@ -99,10 +99,10 @@ Signed-off-by: Alexandru Gagniuc <mr.nuke.me at gmail.com>
+ };
+ };
+
-+ pcs_uniphy1: ethernet-uniphy at 7a10000 {
++ pcs_uniphy1: ethernet-pcs at 7a10000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
-+ compatible = "qcom,ipq9574-uniphy";
++ compatible = "qcom,ipq9574-pcs";
+ reg = <0x7a10000 0x10000>;
+ clocks = <&gcc GCC_UNIPHY1_SYS_CLK>,
+ <&gcc GCC_UNIPHY1_AHB_CLK>;
@@ -116,7 +116,7 @@ Signed-off-by: Alexandru Gagniuc <mr.nuke.me at gmail.com>
+ "xpcs";
+ #clock-cells = <1>;
+
-+ pcsuniphy1_ch0: uniphy-ch at 0 {
++ pcsuniphy1_ch0: pcs-mii at 0 {
+ reg = <0>;
+ clocks = <&nsscc NSS_CC_UNIPHY_PORT5_RX_CLK>,
+ <&nsscc NSS_CC_UNIPHY_PORT5_TX_CLK>;
diff --git a/target/linux/qualcommbe/patches-6.12/0365-net-pcs-ipq-uniphy-control-MISC2-register-for-2.5G-s.patch b/target/linux/qualcommbe/patches-6.12/0365-net-pcs-ipq-uniphy-control-MISC2-register-for-2.5G-s.patch
new file mode 100644
index 0000000000..b34dd837ab
--- /dev/null
+++ b/target/linux/qualcommbe/patches-6.12/0365-net-pcs-ipq-uniphy-control-MISC2-register-for-2.5G-s.patch
@@ -0,0 +1,72 @@
+From 930203b9bb94dc4ea9342f1ce176851918758ed7 Mon Sep 17 00:00:00 2001
+From: Mantas Pucka <mantas at 8devices.com>
+Date: Mon, 2 Jun 2025 17:18:13 +0300
+Subject: [PATCH] net: pcs: ipq-uniphy: control MISC2 register for 2.5G
+ support
+
+When 2500base-x mode is enabled MISC2 regsister needs to have different
+value than for other 1G modes.
+
+Signed-off-by: Mantas Pucka <mantas at 8devices.com>
+---
+ drivers/net/pcs/pcs-qcom-ipq9574.c | 17 ++++++++++++++++-
+ 1 file changed, 16 insertions(+), 1 deletion(-)
+
+--- a/drivers/net/pcs/pcs-qcom-ipq9574.c
++++ b/drivers/net/pcs/pcs-qcom-ipq9574.c
+@@ -24,6 +24,11 @@
+ #define PCS_CALIBRATION 0x1e0
+ #define PCS_CALIBRATION_DONE BIT(7)
+
++#define PCS_MISC2 0x218
++#define PCS_MISC2_MODE_MASK GENMASK(6, 5)
++#define PCS_MISC2_MODE_SGMII FIELD_PREP(PCS_MISC2_MODE_MASK, 0x1)
++#define PCS_MISC2_MODE_SGMII_PLUS FIELD_PREP(PCS_MISC2_MODE_MASK, 0x2)
++
+ #define PCS_MODE_CTRL 0x46c
+ #define PCS_MODE_SEL_MASK GENMASK(12, 8)
+ #define PCS_MODE_SGMII FIELD_PREP(PCS_MODE_SEL_MASK, 0x4)
+@@ -311,7 +316,7 @@ static int ipq_pcs_config_mode(struct ip
+ phy_interface_t interface)
+ {
+ unsigned long rate = 125000000;
+- unsigned int val, mask = PCS_MODE_SEL_MASK;
++ unsigned int val, misc2 = 0, mask = PCS_MODE_SEL_MASK;
+ int ret;
+
+ /* Assert XPCS reset */
+@@ -321,6 +326,7 @@ static int ipq_pcs_config_mode(struct ip
+ switch (interface) {
+ case PHY_INTERFACE_MODE_SGMII:
+ val = PCS_MODE_SGMII;
++ misc2 = PCS_MISC2_MODE_SGMII;
+ break;
+ case PHY_INTERFACE_MODE_QSGMII:
+ val = PCS_MODE_QSGMII;
+@@ -328,10 +334,12 @@ static int ipq_pcs_config_mode(struct ip
+ case PHY_INTERFACE_MODE_1000BASEX:
+ mask |= PCS_MODE_SGMII_CTRL_MASK;
+ val = PCS_MODE_SGMII | PCS_MODE_SGMII_CTRL_1000BASEX;
++ misc2 = PCS_MISC2_MODE_SGMII;
+ break;
+ case PHY_INTERFACE_MODE_2500BASEX:
+ val = PCS_MODE_SGMII_PLUS;
+ rate = 312500000;
++ misc2 = PCS_MISC2_MODE_SGMII_PLUS;
+ break;
+ case PHY_INTERFACE_MODE_PSGMII:
+ val = PCS_MODE_PSGMII;
+@@ -360,6 +368,13 @@ static int ipq_pcs_config_mode(struct ip
+ if (ret)
+ return ret;
+
++ if (misc2) {
++ ret = regmap_update_bits(qpcs->regmap, PCS_MISC2,
++ PCS_MISC2_MODE_MASK, misc2);
++ if (ret)
++ return ret;
++ }
++
+ /* PCS PLL reset */
+ ret = regmap_clear_bits(qpcs->regmap, PCS_PLL_RESET, PCS_ANA_SW_RESET);
+ if (ret)
diff --git a/target/linux/qualcommbe/patches-6.12/0366-net-pcs-ipq-uniphy-keep-autoneg-enabled-in-SGMII-mod.patch b/target/linux/qualcommbe/patches-6.12/0366-net-pcs-ipq-uniphy-keep-autoneg-enabled-in-SGMII-mod.patch
new file mode 100644
index 0000000000..58e2be35f4
--- /dev/null
+++ b/target/linux/qualcommbe/patches-6.12/0366-net-pcs-ipq-uniphy-keep-autoneg-enabled-in-SGMII-mod.patch
@@ -0,0 +1,25 @@
+From ccdfd293f9e948f0f62ac4e9924d72539a4e81ee Mon Sep 17 00:00:00 2001
+From: Mantas Pucka <mantas at 8devices.com>
+Date: Mon, 2 Jun 2025 17:19:45 +0300
+Subject: [PATCH] net: pcs: ipq-uniphy: keep autoneg enabled in SGMII mode
+
+For PHYs that don't use in-band-status (e.g. 2.5G PHY swiching between
+SGMII and 2500base-x), SGMII autoneg still must be enabled. Only mode
+that should use forced speed is 1000base-x
+
+Signed-off-by: Mantas Pucka <mantas at 8devices.com>
+---
+ drivers/net/pcs/pcs-qcom-ipq9574.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/drivers/net/pcs/pcs-qcom-ipq9574.c
++++ b/drivers/net/pcs/pcs-qcom-ipq9574.c
+@@ -431,7 +431,7 @@ static int ipq_pcs_config_sgmii(struct i
+ /* Nothing to do here as in-band autoneg mode is enabled
+ * by default for each PCS MII port.
+ */
+- if (neg_mode == PHYLINK_PCS_NEG_INBAND_ENABLED)
++ if (interface != PHY_INTERFACE_MODE_1000BASEX)
+ return 0;
+
+ /* Set force speed mode */
diff --git a/target/linux/qualcommbe/patches-6.12/0367-net-pcs-ipq-uniphy-fix-USXGMII-link-up-failure.patch b/target/linux/qualcommbe/patches-6.12/0367-net-pcs-ipq-uniphy-fix-USXGMII-link-up-failure.patch
new file mode 100644
index 0000000000..980b8d0379
--- /dev/null
+++ b/target/linux/qualcommbe/patches-6.12/0367-net-pcs-ipq-uniphy-fix-USXGMII-link-up-failure.patch
@@ -0,0 +1,24 @@
+From 0cff1d9bb695bdc0ad7bad234b92eddf849ce88f Mon Sep 17 00:00:00 2001
+From: Mantas Pucka <mantas at 8devices.com>
+Date: Mon, 2 Jun 2025 17:20:58 +0300
+Subject: [PATCH] net: pcs: ipq-uniphy: fix USXGMII link-up failure
+
+USXGMII link-up may fail due to too short delay after PLL reset.
+Increase the delay to fix this.
+
+Signed-off-by: Mantas Pucka <mantas at 8devices.com>
+---
+ drivers/net/pcs/pcs-qcom-ipq9574.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/drivers/net/pcs/pcs-qcom-ipq9574.c
++++ b/drivers/net/pcs/pcs-qcom-ipq9574.c
+@@ -380,7 +380,7 @@ static int ipq_pcs_config_mode(struct ip
+ if (ret)
+ return ret;
+
+- fsleep(1000);
++ fsleep(20000);
+ ret = regmap_set_bits(qpcs->regmap, PCS_PLL_RESET, PCS_ANA_SW_RESET);
+ if (ret)
+ return ret;
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