[openwrt/openwrt] mvebu: add support for Check Point V-81
LEDE Commits
lede-commits at lists.infradead.org
Sun Jun 22 13:33:02 PDT 2025
hauke pushed a commit to openwrt/openwrt.git, branch main:
https://git.openwrt.org/97af506edfd78cb01055938f0ecc76591e20ff77
commit 97af506edfd78cb01055938f0ecc76591e20ff77
Author: INAGAKI Hiroshi <musashino.open at gmail.com>
AuthorDate: Sun Apr 7 11:53:17 2024 +0900
mvebu: add support for Check Point V-81
Check Point V-80 (Quantum Spark 1590 Appliance) is an Appliance, based
on Armada 8040 (88F8040).
Specification:
- SoC : Marvell Armada 8040 (88F8040)
- RAM : DDR4 2 GiB (4x 512 MiB chip)
- Flash : eMMC 4 GiB
- Ethernet : 10x 10/100/1000 Mbps
- LAN 1-8 : Marvell 88E6393X
- WAN : Marvell 88E1512
- DMZ : Marvell 88E1512 (RJ-45/SFP combo)
- LEDs/Keys (GPIO): 11x/1x
- UART : "CONSOLE" port (USB 1.1 Type-C)
- chip : Silicon Labs CP2102N
- port : ttyS0
- settings : 115200bps 8n1
- HW Monitoring : 2x nuvoTon NCT7802Y
- USB : USB 3.0 Type-A
- Power : 12 VDC, 3.3 A
- plug : DC Plug 2.5/5.5 mm (inner/outer)
Flash instruction (common):
1. Boot V-81 normally
2. Login to the vendor CLI (default: admin/admin) and login to the Linux
CLI by `expert` command
3. Update U-Boot environment variables by the following commands
fw_setenv bootcmd_ow_usb 'usb start; load usb 0:1 ${loadaddr} boot.scr && source ${loadaddr}'
fw_setenv bootcmd_ow_sd 'load mmc 0:1 ${loadaddr} boot.scr && source ${loadaddr}'
fw_setenv bootcmd_ow_emmc 'run set_mmc_internal; mmc read ${loadaddr} ${prim_header_mmc_blk} 4 && source ${loadaddr}'
fw_setenv bootcmd 'run bootcmd_ow_usb; run bootcmd_ow_sd; run bootcmd_ow_emmc; run bootcmd_part${activePartition};'
Attention: don't forget single quatations of values to prevent
expansion of variables
4. Turn off the device
Flash instruction (USB-boot/SD-boot):
1. Extract and burn (squashfs|ext4)-sdcard.img.gz to USB storage or
MicroSD card
2. Connect that storage to V-81
3. Turn on V-81 and it will be booted with OpenWrt in that USB storage
Flash instruction (eMMC-boot):
1. Copy initramfs image, dtb and bootsctipt to the USB storage with
renaming
initramfs.bin -------> Image
dtb -----------------> armada-8040-v-81.dtb
bootscript (.scr) ---> boot.scr
2. Connect that storage to the USB 3.0 port on V-81
3. Turn on V-81 and it will be booted with OpenWrt initramfs image in
that USB storage
4. Upload (squashfs|ext4)-sysupgrade.gz to V-81
5. Perform sysupgrade with the uploaded image
6. Wait ~100 seconds to complete flashing
Reverting to stock firmware:
1. Turn on V-81 and interrupt booting by Ctrl + C
2. Select "4. Restore to Factory Defaults (local)"
3. Wait ~180 seconds to complete restoring and rebooting
Notes:
- The partition table in the internal eMMC has single partition, but
"blkdevparts=" parameter will be passed from the bootloader and that
definition will be used instead.
- The port-side LED pairs of RJ-45/SFP ports on V-81 are switched by a
GPIO pin of pin7 on &cp0_gpio2. (High(1): RJ-45, Low(0): SFP)
This needs to be switched manually.
- The MicroSD card slot is too unstable and the following messages are
printed without "marvell,xenon-phy-slow-mode;" property.
[ 97.060851] mmc0: error -84 whilst initialising SD card
[ 97.137049] mmc0: error -84 whilst initialising SD card
[ 97.214315] mmc0: error -84 whilst initialising SD card
...
- There are no detailed information about maximum power consumption
limit of the SFP port or optional DSL-SFP modules sold officially.
But the power requirement of almost DSL-SFP modules are 3.3V/700mA, so
set the maximum value of the SFP port to 2000 mW (Power Level III).
- Do not insert a MicroSD card before turning of the device when OpenWrt
installation. The stock firmware deletes all files in the first
partition automatically, to use it as a storage for logs.
MAC addresses:
LAN: 00:1C:7F:xx:xx:FA (mmcblk1boot0, ethaddr (text))
WAN: 00:1C:7F:xx:xx:F9 (mmcblk1boot0, eth2addr (text))
DMZ: 00:1C:7F:xx:xx:FB (mmcblk1boot0, eth1addr (text))
Signed-off-by: INAGAKI Hiroshi <musashino.open at gmail.com>
Link: https://github.com/openwrt/openwrt/pull/16904
Signed-off-by: Hauke Mehrtens <hauke at hauke-m.de>
---
.../cortexa72/base-files/etc/board.d/02_network | 3 +
.../cortexa72/base-files/lib/upgrade/platform.sh | 9 +-
.../arm64/boot/dts/marvell/armada-8040-v-81.dts | 514 +++++++++++++++++++++
.../arm64/boot/dts/marvell/armada-8040-v-81.dts | 514 +++++++++++++++++++++
target/linux/mvebu/image/cortexa72.mk | 18 +
5 files changed, 1055 insertions(+), 3 deletions(-)
diff --git a/target/linux/mvebu/cortexa72/base-files/etc/board.d/02_network b/target/linux/mvebu/cortexa72/base-files/etc/board.d/02_network
index 73274744c6..6c8c6c171f 100644
--- a/target/linux/mvebu/cortexa72/base-files/etc/board.d/02_network
+++ b/target/linux/mvebu/cortexa72/base-files/etc/board.d/02_network
@@ -13,6 +13,9 @@ case "$board" in
checkpoint,v-80)
ucidef_set_interfaces_lan_wan "lan1 lan2 lan3 lan4 lan5" "eth1"
;;
+checkpoint,v-81)
+ ucidef_set_interfaces_lan_wan "lan1 lan2 lan3 lan4 lan5 lan6 lan7 lan8" "eth1 eth2"
+ ;;
globalscale,mochabin)
ucidef_set_interfaces_lan_wan "lan0 lan1 lan2 lan3" "eth0 eth2"
;;
diff --git a/target/linux/mvebu/cortexa72/base-files/lib/upgrade/platform.sh b/target/linux/mvebu/cortexa72/base-files/lib/upgrade/platform.sh
index 529ab0a9f5..b88b3c08ec 100755
--- a/target/linux/mvebu/cortexa72/base-files/lib/upgrade/platform.sh
+++ b/target/linux/mvebu/cortexa72/base-files/lib/upgrade/platform.sh
@@ -9,7 +9,8 @@ REQUIRE_IMAGE_METADATA=1
platform_check_image() {
case "$(board_name)" in
- checkpoint,v-80)
+ checkpoint,v-80|\
+ checkpoint,v-81)
local root="$(cmdline_get_var root)"
case "$root" in
PARTUUID=????????-02) # USB or SD
@@ -55,7 +56,8 @@ platform_check_image() {
platform_do_upgrade() {
case "$(board_name)" in
- checkpoint,v-80)
+ checkpoint,v-80|\
+ checkpoint,v-81)
local root="$(cmdline_get_var root)"
case "$root" in
PARTUUID=????????-02) # USB or SD
@@ -91,7 +93,8 @@ platform_do_upgrade() {
}
platform_copy_config() {
case "$(board_name)" in
- checkpoint,v-80)
+ checkpoint,v-80|\
+ checkpoint,v-81)
local root="$(cmdline_get_var root)"
case "$root" in
PARTUUID=????????-02) # USB or SD
diff --git a/target/linux/mvebu/files-6.12/arch/arm64/boot/dts/marvell/armada-8040-v-81.dts b/target/linux/mvebu/files-6.12/arch/arm64/boot/dts/marvell/armada-8040-v-81.dts
new file mode 100644
index 0000000000..a32be5b558
--- /dev/null
+++ b/target/linux/mvebu/files-6.12/arch/arm64/boot/dts/marvell/armada-8040-v-81.dts
@@ -0,0 +1,514 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+
+/dts-v1/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/leds/common.h>
+#include "armada-8040.dtsi"
+
+/ {
+ model = "Check Point V-81";
+ compatible = "checkpoint,v-81", "marvell,armada8040",
+ "marvell,armada-ap806-quad", "marvell,armada-ap806";
+
+ aliases {
+ ethernet0 = &cp0_eth0;
+ ethernet1 = &cp1_eth1;
+ ethernet2 = &cp1_eth2;
+ mmc0 = &ap_sdhci0;
+ mmc1 = &cp0_sdhci0;
+ led-boot = &led_power_blue;
+ led-failsafe = &led_power_red;
+ led-running = &led_power_blue;
+ led-upgrade = &led_power_blue;
+ label-mac-device = &cp1_eth2;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory at 0 {
+ device_type = "memory";
+ reg = <0x00000000 0x00000000 0x00000000 0x80000000>;
+ };
+
+ keys {
+ compatible = "gpio-keys";
+ pinctrl-0 = <&pmx_gpio_keys_pins>;
+ pinctrl-names = "default";
+
+ button-reset {
+ label = "reset";
+ gpios = <&cp1_gpio1 31 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_RESTART>;
+ };
+ };
+
+ leds {
+ compatible = "gpio-leds";
+ pinctrl-0 = <&pmx_gpio_leds_pins>;
+ pinctrl-names = "default";
+
+ led-0 {
+ gpios = <&cp1_gpio1 2 GPIO_ACTIVE_LOW>;
+ color = <LED_COLOR_ID_RED>;
+ function = "management";
+ };
+
+ led-1 {
+ gpios = <&cp1_gpio1 3 GPIO_ACTIVE_LOW>;
+ color = <LED_COLOR_ID_BLUE>;
+ function = "management";
+ };
+
+ led-2 {
+ gpios = <&cp1_gpio1 6 GPIO_ACTIVE_LOW>;
+ color = <LED_COLOR_ID_RED>;
+ function = LED_FUNCTION_WAN_ONLINE;
+ };
+
+ led-3 {
+ gpios = <&cp1_gpio1 7 GPIO_ACTIVE_LOW>;
+ color = <LED_COLOR_ID_BLUE>;
+ function = LED_FUNCTION_WAN_ONLINE;
+ };
+
+ led_power_red: led-4 {
+ gpios = <&cp1_gpio1 11 GPIO_ACTIVE_HIGH>;
+ color = <LED_COLOR_ID_RED>;
+ function = LED_FUNCTION_POWER;
+ };
+
+ /* populated but no hole on the case ("LTE" or "DSL") */
+ led-5 {
+ gpios = <&cp1_gpio1 14 GPIO_ACTIVE_LOW>;
+ color = <LED_COLOR_ID_BLUE>;
+ function = LED_FUNCTION_MOBILE;
+ };
+
+ /* populated but no hole on the case ("LTE" or "DSL") */
+ led-6 {
+ gpios = <&cp1_gpio1 15 GPIO_ACTIVE_LOW>;
+ color = <LED_COLOR_ID_RED>;
+ function = LED_FUNCTION_MOBILE;
+ };
+
+ /* populated but no hole on the case */
+ led-7 {
+ gpios = <&cp1_gpio1 16 GPIO_ACTIVE_HIGH>;
+ color = <LED_COLOR_ID_RED>;
+ function = LED_FUNCTION_WLAN;
+ };
+
+ /* populated but no hole on the case */
+ led-8 {
+ gpios = <&cp1_gpio1 24 GPIO_ACTIVE_HIGH>;
+ color = <LED_COLOR_ID_BLUE>;
+ function = LED_FUNCTION_WLAN;
+ };
+
+ led_power_blue: led-9 {
+ gpios = <&cp1_gpio1 26 GPIO_ACTIVE_HIGH>;
+ color = <LED_COLOR_ID_BLUE>;
+ function = LED_FUNCTION_POWER;
+ };
+
+ /* populated but no hole on the case (unused) */
+ led-10 {
+ gpios = <&gpio5 7 GPIO_ACTIVE_LOW>;
+ color = <LED_COLOR_ID_BLUE>;
+ function = "unused";
+ };
+ };
+
+ regulator-usb-vbus {
+ compatible = "regulator-fixed";
+ regulator-name = "usb-vbus";
+ gpios = <&gpio4 0 GPIO_ACTIVE_HIGH>;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ enable-active-high;
+ regulator-always-on;
+ };
+
+ sfp: sfp {
+ /*
+ * Note: port LEDs on RJ45/SFP are switched
+ * by pin7 on &cp0_gpio2
+ *
+ * - HIGH: RJ45
+ * - LOW : SFP
+ */
+ compatible = "sff,sfp";
+ i2c-bus = <&cp0_i2c1>;
+ los-gpios = <&gpio3 11 GPIO_ACTIVE_HIGH>;
+ mod-def0-gpios = <&gpio3 15 GPIO_ACTIVE_LOW>;
+ tx-disable-gpios = <&gpio3 10 GPIO_ACTIVE_HIGH>;
+ tx-fault-gpios = <&gpio3 14 GPIO_ACTIVE_HIGH>;
+ maximum-power-milliwatt = <2000>;
+ };
+};
+
+/* USB Type-C UART console */
+&uart0 {
+ status = "okay";
+
+ pinctrl-0 = <&uart0_pins>;
+ pinctrl-names = "default";
+};
+
+&ap_pinctrl {
+ pmx_ap_sdhci0_pins: ap-sdhci0-pins {
+ marvell,pins = "mpp12";
+ marvell,function = "gpio";
+ };
+};
+
+/* MicroSD slot */
+&ap_sdhci0 {
+ status = "okay";
+
+ pinctrl-0 = <&pmx_ap_sdhci0_pins>;
+ pinctrl-names = "default";
+ bus-width = <4>;
+ cd-gpios = <&ap_gpio 12 GPIO_ACTIVE_LOW>;
+ /*
+ * Not stable in HS modes - phy needs "more calibration", so add
+ * the "slow-mode" and disable SDR104, SDR50 and DDR50 modes.
+ */
+ marvell,xenon-phy-slow-mode;
+ no-1-8-v;
+};
+
+&cp0_ethernet {
+ status = "okay";
+};
+
+/* LAN1-8 (Switch) */
+&cp0_eth0 {
+ status = "okay";
+
+ phy-connection-type = "10gbase-r";
+ phys = <&cp0_comphy2 0>;
+
+ fixed-link {
+ speed = <10000>;
+ full-duplex;
+ };
+};
+
+/* 2x PCA9555, 2x NCT7802Y, TCA9534A */
+&cp0_i2c0 {
+ status = "okay";
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&pmx_cp0_i2c0_pins>;
+ clock-frequency = <100000>;
+
+ gpio3: gpio at 21 {
+ pinctrl-0 = <&pmx_pca9555_pins>;
+ pinctrl-names = "default";
+ compatible = "nxp,pca9555";
+ reg = <0x21>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-parent = <&cp0_gpio2>;
+ interrupts = <1 IRQ_TYPE_EDGE_FALLING>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio4: gpio at 22 {
+ compatible = "nxp,pca9555";
+ reg = <0x22>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ hwmon at 2b {
+ compatible = "nuvoton,nct7802";
+ reg = <0x2b>;
+ };
+
+ hwmon at 2d {
+ compatible = "nuvoton,nct7802";
+ reg = <0x2d>;
+ };
+
+ /* TI TCA9534A */
+ gpio5: gpio at 3b {
+ compatible = "nxp,pca9534";
+ reg = <0x3b>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+};
+
+/* EEPROM */
+&cp0_i2c1 {
+ status = "okay";
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&pmx_cp0_i2c1_pins>;
+ clock-frequency = <100000>;
+
+ /* Giantec GT24C04A */
+ eeprom at 54 {
+ compatible = "atmel,24c04";
+ reg = <0x54>;
+ wp-gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>;
+ read-only;
+ };
+};
+
+&cp0_mdio {
+ status = "okay";
+
+ pinctrl-0 = <&pmx_cp0_mdio_pins>;
+ pinctrl-names = "default";
+
+ /* Marvell 88E6393X */
+ switch at 0 {
+ compatible = "marvell,mv88e6190";
+ reg = <0x0>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port at 0 {
+ reg = <0>;
+ ethernet = <&cp0_eth0>;
+ phy-connection-type = "10gbase-r";
+
+ fixed-link {
+ speed = <10000>;
+ full-duplex;
+ };
+ };
+
+ swport1: port at 1 {
+ reg = <1>;
+ label = "lan1";
+ phy-handle = <&swphy1>;
+ };
+
+ swport2: port at 2 {
+ reg = <2>;
+ label = "lan2";
+ phy-handle = <&swphy2>;
+ };
+
+ swport3: port at 3 {
+ reg = <3>;
+ label = "lan3";
+ phy-handle = <&swphy3>;
+ };
+
+ swport4: port at 4 {
+ reg = <4>;
+ label = "lan4";
+ phy-handle = <&swphy4>;
+ };
+
+ swport5: port at 5 {
+ reg = <5>;
+ label = "lan5";
+ phy-handle = <&swphy5>;
+ };
+
+ swport6: port at 6 {
+ reg = <6>;
+ label = "lan6";
+ phy-handle = <&swphy6>;
+ };
+
+ swport7: port at 7 {
+ reg = <7>;
+ label = "lan7";
+ phy-handle = <&swphy7>;
+ };
+
+ swport8: port at 8 {
+ reg = <8>;
+ label = "lan8";
+ phy-handle = <&swphy8>;
+ };
+ };
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ swphy1: switch-phy at 1 {
+ reg = <0x1>;
+ };
+
+ swphy2: switch-phy at 2 {
+ reg = <0x2>;
+ };
+
+ swphy3: switch-phy at 3 {
+ reg = <0x3>;
+ };
+
+ swphy4: switch-phy at 4 {
+ reg = <0x4>;
+ };
+
+ swphy5: switch-phy at 5 {
+ reg = <0x5>;
+ };
+
+ swphy6: switch-phy at 6 {
+ reg = <0x6>;
+ };
+
+ swphy7: switch-phy at 7 {
+ reg = <0x7>;
+ };
+
+ swphy8: switch-phy at 8 {
+ reg = <0x8>;
+ };
+ };
+ };
+};
+
+&cp0_pinctrl {
+ pmx_cp0_mdio_pins: cp0-mdio-pins {
+ marvell,pins = "mpp32", "mpp34";
+ marvell,function = "ge";
+ };
+
+ pmx_cp0_spi1_pins: cp0-spi0-pins {
+ marvell,pins = "mpp40", "mpp41", "mpp42", "mpp43";
+ marvell,function = "spi0";
+ };
+
+ pmx_cp0_i2c0_pins: cp0-i2c0-pins {
+ marvell,pins = "mpp37", "mpp38";
+ marvell,function = "i2c0";
+ };
+
+ pmx_cp0_i2c1_pins: cp0-i2c1-pins {
+ marvell,pins = "mpp35", "mpp36";
+ marvell,function = "i2c1";
+ };
+
+ pmx_cp0_sdhci0_pins: cp0-sdhci0-pins {
+ marvell,pins = "mpp56", "mpp57","mpp58", "mpp59", "mpp60", "mpp61";
+ marvell,function = "sdio";
+ };
+
+ pmx_cp1_rgmii1_pins: cp1-rgmii1-pins {
+ marvell,pins = "mpp44", "mpp45", "mpp46", "mpp47", "mpp48", "mpp49",
+ "mpp50", "mpp51", "mpp52", "mpp53", "mpp54", "mpp55";
+ marvell,function = "ge1";
+ };
+
+ pmx_pca9555_pins: pca9555-pins {
+ marvell,pins = "mpp33";
+ marvell,function = "gpio";
+ };
+};
+
+/* eMMC */
+&cp0_sdhci0 {
+ status = "okay";
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&pmx_cp0_sdhci0_pins>;
+ bus-width = <4>;
+ non-removable;
+};
+
+&cp0_utmi {
+ status = "okay";
+};
+
+/* USB 3.0 Type-A */
+&cp0_usb3_0 {
+ status = "okay";
+
+ dr_mode = "host";
+ phys = <&cp0_comphy1 0>, <&cp0_utmi0>;
+ phy-names = "cp0-usb3h0-comphy", "utmi";
+};
+
+&cp1_ethernet {
+ status = "okay";
+
+ pinctrl-0 = <&pmx_cp1_rgmii1_pins>;
+ pinctrl-names = "default";
+};
+
+/* "DMZ" (RJ45/SFP) */
+&cp1_eth1 {
+ status = "okay";
+
+ phy-connection-type = "rgmii-id";
+ phy-handle = <ðphy0>;
+};
+
+/* "WAN" */
+&cp1_eth2 {
+ status = "okay";
+
+ phy-connection-type = "sgmii";
+ phy-handle = <ðphy1>;
+ phys = <&cp1_comphy1 2>;
+};
+
+&cp1_mdio {
+ status = "okay";
+
+ pinctrl-0 = <&pmx_cp1_mdio_pins>;
+ pinctrl-names = "default";
+
+ /* Marvell 88E1512 */
+ ethphy0: ethernet-phy at 0 {
+ compatible = "ethernet-phy-id0141,0dd1",
+ "ethernet-phy-ieee802.3-c22";
+ reg = <0x0>;
+ /*
+ * LED[0] (Green): LINK/ACT
+ * LED[1] (Amber): SPEED 100/1000M
+ */
+ marvell,reg-init = <3 16 0 0x61>;
+ sfp = <&sfp>;
+ };
+
+ /* Marvell 88E1512 */
+ ethphy1: ethernet-phy at 1 {
+ compatible = "ethernet-phy-id0141,0dd1",
+ "ethernet-phy-ieee802.3-c22";
+ reg = <0x1>;
+ /*
+ * LED[0] (Green): LINK/ACT
+ * LED[1] (Amber): SPEED 100/1000M
+ */
+ marvell,reg-init = <3 16 0 0x61>;
+ };
+};
+
+&cp1_pinctrl {
+ pmx_gpio_keys_pins: gpio-keys-pins {
+ marvell,pins = "mpp31";
+ marvell,function = "gpio";
+ };
+
+ pmx_gpio_leds_pins: gpio-leds-pins {
+ marvell,pins = "mpp2", "mpp3", "mpp6", "mpp7", "mpp11", "mpp14",
+ "mpp15", "mpp16", "mpp24", "mpp26";
+ marvell,function = "gpio";
+ };
+
+ pmx_cp1_mdio_pins: mdio-pins {
+ marvell,pins = "mpp4", "mpp5";
+ marvell,function = "ge";
+ };
+};
diff --git a/target/linux/mvebu/files-6.6/arch/arm64/boot/dts/marvell/armada-8040-v-81.dts b/target/linux/mvebu/files-6.6/arch/arm64/boot/dts/marvell/armada-8040-v-81.dts
new file mode 100644
index 0000000000..a32be5b558
--- /dev/null
+++ b/target/linux/mvebu/files-6.6/arch/arm64/boot/dts/marvell/armada-8040-v-81.dts
@@ -0,0 +1,514 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+
+/dts-v1/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/leds/common.h>
+#include "armada-8040.dtsi"
+
+/ {
+ model = "Check Point V-81";
+ compatible = "checkpoint,v-81", "marvell,armada8040",
+ "marvell,armada-ap806-quad", "marvell,armada-ap806";
+
+ aliases {
+ ethernet0 = &cp0_eth0;
+ ethernet1 = &cp1_eth1;
+ ethernet2 = &cp1_eth2;
+ mmc0 = &ap_sdhci0;
+ mmc1 = &cp0_sdhci0;
+ led-boot = &led_power_blue;
+ led-failsafe = &led_power_red;
+ led-running = &led_power_blue;
+ led-upgrade = &led_power_blue;
+ label-mac-device = &cp1_eth2;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory at 0 {
+ device_type = "memory";
+ reg = <0x00000000 0x00000000 0x00000000 0x80000000>;
+ };
+
+ keys {
+ compatible = "gpio-keys";
+ pinctrl-0 = <&pmx_gpio_keys_pins>;
+ pinctrl-names = "default";
+
+ button-reset {
+ label = "reset";
+ gpios = <&cp1_gpio1 31 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_RESTART>;
+ };
+ };
+
+ leds {
+ compatible = "gpio-leds";
+ pinctrl-0 = <&pmx_gpio_leds_pins>;
+ pinctrl-names = "default";
+
+ led-0 {
+ gpios = <&cp1_gpio1 2 GPIO_ACTIVE_LOW>;
+ color = <LED_COLOR_ID_RED>;
+ function = "management";
+ };
+
+ led-1 {
+ gpios = <&cp1_gpio1 3 GPIO_ACTIVE_LOW>;
+ color = <LED_COLOR_ID_BLUE>;
+ function = "management";
+ };
+
+ led-2 {
+ gpios = <&cp1_gpio1 6 GPIO_ACTIVE_LOW>;
+ color = <LED_COLOR_ID_RED>;
+ function = LED_FUNCTION_WAN_ONLINE;
+ };
+
+ led-3 {
+ gpios = <&cp1_gpio1 7 GPIO_ACTIVE_LOW>;
+ color = <LED_COLOR_ID_BLUE>;
+ function = LED_FUNCTION_WAN_ONLINE;
+ };
+
+ led_power_red: led-4 {
+ gpios = <&cp1_gpio1 11 GPIO_ACTIVE_HIGH>;
+ color = <LED_COLOR_ID_RED>;
+ function = LED_FUNCTION_POWER;
+ };
+
+ /* populated but no hole on the case ("LTE" or "DSL") */
+ led-5 {
+ gpios = <&cp1_gpio1 14 GPIO_ACTIVE_LOW>;
+ color = <LED_COLOR_ID_BLUE>;
+ function = LED_FUNCTION_MOBILE;
+ };
+
+ /* populated but no hole on the case ("LTE" or "DSL") */
+ led-6 {
+ gpios = <&cp1_gpio1 15 GPIO_ACTIVE_LOW>;
+ color = <LED_COLOR_ID_RED>;
+ function = LED_FUNCTION_MOBILE;
+ };
+
+ /* populated but no hole on the case */
+ led-7 {
+ gpios = <&cp1_gpio1 16 GPIO_ACTIVE_HIGH>;
+ color = <LED_COLOR_ID_RED>;
+ function = LED_FUNCTION_WLAN;
+ };
+
+ /* populated but no hole on the case */
+ led-8 {
+ gpios = <&cp1_gpio1 24 GPIO_ACTIVE_HIGH>;
+ color = <LED_COLOR_ID_BLUE>;
+ function = LED_FUNCTION_WLAN;
+ };
+
+ led_power_blue: led-9 {
+ gpios = <&cp1_gpio1 26 GPIO_ACTIVE_HIGH>;
+ color = <LED_COLOR_ID_BLUE>;
+ function = LED_FUNCTION_POWER;
+ };
+
+ /* populated but no hole on the case (unused) */
+ led-10 {
+ gpios = <&gpio5 7 GPIO_ACTIVE_LOW>;
+ color = <LED_COLOR_ID_BLUE>;
+ function = "unused";
+ };
+ };
+
+ regulator-usb-vbus {
+ compatible = "regulator-fixed";
+ regulator-name = "usb-vbus";
+ gpios = <&gpio4 0 GPIO_ACTIVE_HIGH>;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ enable-active-high;
+ regulator-always-on;
+ };
+
+ sfp: sfp {
+ /*
+ * Note: port LEDs on RJ45/SFP are switched
+ * by pin7 on &cp0_gpio2
+ *
+ * - HIGH: RJ45
+ * - LOW : SFP
+ */
+ compatible = "sff,sfp";
+ i2c-bus = <&cp0_i2c1>;
+ los-gpios = <&gpio3 11 GPIO_ACTIVE_HIGH>;
+ mod-def0-gpios = <&gpio3 15 GPIO_ACTIVE_LOW>;
+ tx-disable-gpios = <&gpio3 10 GPIO_ACTIVE_HIGH>;
+ tx-fault-gpios = <&gpio3 14 GPIO_ACTIVE_HIGH>;
+ maximum-power-milliwatt = <2000>;
+ };
+};
+
+/* USB Type-C UART console */
+&uart0 {
+ status = "okay";
+
+ pinctrl-0 = <&uart0_pins>;
+ pinctrl-names = "default";
+};
+
+&ap_pinctrl {
+ pmx_ap_sdhci0_pins: ap-sdhci0-pins {
+ marvell,pins = "mpp12";
+ marvell,function = "gpio";
+ };
+};
+
+/* MicroSD slot */
+&ap_sdhci0 {
+ status = "okay";
+
+ pinctrl-0 = <&pmx_ap_sdhci0_pins>;
+ pinctrl-names = "default";
+ bus-width = <4>;
+ cd-gpios = <&ap_gpio 12 GPIO_ACTIVE_LOW>;
+ /*
+ * Not stable in HS modes - phy needs "more calibration", so add
+ * the "slow-mode" and disable SDR104, SDR50 and DDR50 modes.
+ */
+ marvell,xenon-phy-slow-mode;
+ no-1-8-v;
+};
+
+&cp0_ethernet {
+ status = "okay";
+};
+
+/* LAN1-8 (Switch) */
+&cp0_eth0 {
+ status = "okay";
+
+ phy-connection-type = "10gbase-r";
+ phys = <&cp0_comphy2 0>;
+
+ fixed-link {
+ speed = <10000>;
+ full-duplex;
+ };
+};
+
+/* 2x PCA9555, 2x NCT7802Y, TCA9534A */
+&cp0_i2c0 {
+ status = "okay";
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&pmx_cp0_i2c0_pins>;
+ clock-frequency = <100000>;
+
+ gpio3: gpio at 21 {
+ pinctrl-0 = <&pmx_pca9555_pins>;
+ pinctrl-names = "default";
+ compatible = "nxp,pca9555";
+ reg = <0x21>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-parent = <&cp0_gpio2>;
+ interrupts = <1 IRQ_TYPE_EDGE_FALLING>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio4: gpio at 22 {
+ compatible = "nxp,pca9555";
+ reg = <0x22>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ hwmon at 2b {
+ compatible = "nuvoton,nct7802";
+ reg = <0x2b>;
+ };
+
+ hwmon at 2d {
+ compatible = "nuvoton,nct7802";
+ reg = <0x2d>;
+ };
+
+ /* TI TCA9534A */
+ gpio5: gpio at 3b {
+ compatible = "nxp,pca9534";
+ reg = <0x3b>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+};
+
+/* EEPROM */
+&cp0_i2c1 {
+ status = "okay";
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&pmx_cp0_i2c1_pins>;
+ clock-frequency = <100000>;
+
+ /* Giantec GT24C04A */
+ eeprom at 54 {
+ compatible = "atmel,24c04";
+ reg = <0x54>;
+ wp-gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>;
+ read-only;
+ };
+};
+
+&cp0_mdio {
+ status = "okay";
+
+ pinctrl-0 = <&pmx_cp0_mdio_pins>;
+ pinctrl-names = "default";
+
+ /* Marvell 88E6393X */
+ switch at 0 {
+ compatible = "marvell,mv88e6190";
+ reg = <0x0>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port at 0 {
+ reg = <0>;
+ ethernet = <&cp0_eth0>;
+ phy-connection-type = "10gbase-r";
+
+ fixed-link {
+ speed = <10000>;
+ full-duplex;
+ };
+ };
+
+ swport1: port at 1 {
+ reg = <1>;
+ label = "lan1";
+ phy-handle = <&swphy1>;
+ };
+
+ swport2: port at 2 {
+ reg = <2>;
+ label = "lan2";
+ phy-handle = <&swphy2>;
+ };
+
+ swport3: port at 3 {
+ reg = <3>;
+ label = "lan3";
+ phy-handle = <&swphy3>;
+ };
+
+ swport4: port at 4 {
+ reg = <4>;
+ label = "lan4";
+ phy-handle = <&swphy4>;
+ };
+
+ swport5: port at 5 {
+ reg = <5>;
+ label = "lan5";
+ phy-handle = <&swphy5>;
+ };
+
+ swport6: port at 6 {
+ reg = <6>;
+ label = "lan6";
+ phy-handle = <&swphy6>;
+ };
+
+ swport7: port at 7 {
+ reg = <7>;
+ label = "lan7";
+ phy-handle = <&swphy7>;
+ };
+
+ swport8: port at 8 {
+ reg = <8>;
+ label = "lan8";
+ phy-handle = <&swphy8>;
+ };
+ };
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ swphy1: switch-phy at 1 {
+ reg = <0x1>;
+ };
+
+ swphy2: switch-phy at 2 {
+ reg = <0x2>;
+ };
+
+ swphy3: switch-phy at 3 {
+ reg = <0x3>;
+ };
+
+ swphy4: switch-phy at 4 {
+ reg = <0x4>;
+ };
+
+ swphy5: switch-phy at 5 {
+ reg = <0x5>;
+ };
+
+ swphy6: switch-phy at 6 {
+ reg = <0x6>;
+ };
+
+ swphy7: switch-phy at 7 {
+ reg = <0x7>;
+ };
+
+ swphy8: switch-phy at 8 {
+ reg = <0x8>;
+ };
+ };
+ };
+};
+
+&cp0_pinctrl {
+ pmx_cp0_mdio_pins: cp0-mdio-pins {
+ marvell,pins = "mpp32", "mpp34";
+ marvell,function = "ge";
+ };
+
+ pmx_cp0_spi1_pins: cp0-spi0-pins {
+ marvell,pins = "mpp40", "mpp41", "mpp42", "mpp43";
+ marvell,function = "spi0";
+ };
+
+ pmx_cp0_i2c0_pins: cp0-i2c0-pins {
+ marvell,pins = "mpp37", "mpp38";
+ marvell,function = "i2c0";
+ };
+
+ pmx_cp0_i2c1_pins: cp0-i2c1-pins {
+ marvell,pins = "mpp35", "mpp36";
+ marvell,function = "i2c1";
+ };
+
+ pmx_cp0_sdhci0_pins: cp0-sdhci0-pins {
+ marvell,pins = "mpp56", "mpp57","mpp58", "mpp59", "mpp60", "mpp61";
+ marvell,function = "sdio";
+ };
+
+ pmx_cp1_rgmii1_pins: cp1-rgmii1-pins {
+ marvell,pins = "mpp44", "mpp45", "mpp46", "mpp47", "mpp48", "mpp49",
+ "mpp50", "mpp51", "mpp52", "mpp53", "mpp54", "mpp55";
+ marvell,function = "ge1";
+ };
+
+ pmx_pca9555_pins: pca9555-pins {
+ marvell,pins = "mpp33";
+ marvell,function = "gpio";
+ };
+};
+
+/* eMMC */
+&cp0_sdhci0 {
+ status = "okay";
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&pmx_cp0_sdhci0_pins>;
+ bus-width = <4>;
+ non-removable;
+};
+
+&cp0_utmi {
+ status = "okay";
+};
+
+/* USB 3.0 Type-A */
+&cp0_usb3_0 {
+ status = "okay";
+
+ dr_mode = "host";
+ phys = <&cp0_comphy1 0>, <&cp0_utmi0>;
+ phy-names = "cp0-usb3h0-comphy", "utmi";
+};
+
+&cp1_ethernet {
+ status = "okay";
+
+ pinctrl-0 = <&pmx_cp1_rgmii1_pins>;
+ pinctrl-names = "default";
+};
+
+/* "DMZ" (RJ45/SFP) */
+&cp1_eth1 {
+ status = "okay";
+
+ phy-connection-type = "rgmii-id";
+ phy-handle = <ðphy0>;
+};
+
+/* "WAN" */
+&cp1_eth2 {
+ status = "okay";
+
+ phy-connection-type = "sgmii";
+ phy-handle = <ðphy1>;
+ phys = <&cp1_comphy1 2>;
+};
+
+&cp1_mdio {
+ status = "okay";
+
+ pinctrl-0 = <&pmx_cp1_mdio_pins>;
+ pinctrl-names = "default";
+
+ /* Marvell 88E1512 */
+ ethphy0: ethernet-phy at 0 {
+ compatible = "ethernet-phy-id0141,0dd1",
+ "ethernet-phy-ieee802.3-c22";
+ reg = <0x0>;
+ /*
+ * LED[0] (Green): LINK/ACT
+ * LED[1] (Amber): SPEED 100/1000M
+ */
+ marvell,reg-init = <3 16 0 0x61>;
+ sfp = <&sfp>;
+ };
+
+ /* Marvell 88E1512 */
+ ethphy1: ethernet-phy at 1 {
+ compatible = "ethernet-phy-id0141,0dd1",
+ "ethernet-phy-ieee802.3-c22";
+ reg = <0x1>;
+ /*
+ * LED[0] (Green): LINK/ACT
+ * LED[1] (Amber): SPEED 100/1000M
+ */
+ marvell,reg-init = <3 16 0 0x61>;
+ };
+};
+
+&cp1_pinctrl {
+ pmx_gpio_keys_pins: gpio-keys-pins {
+ marvell,pins = "mpp31";
+ marvell,function = "gpio";
+ };
+
+ pmx_gpio_leds_pins: gpio-leds-pins {
+ marvell,pins = "mpp2", "mpp3", "mpp6", "mpp7", "mpp11", "mpp14",
+ "mpp15", "mpp16", "mpp24", "mpp26";
+ marvell,function = "gpio";
+ };
+
+ pmx_cp1_mdio_pins: mdio-pins {
+ marvell,pins = "mpp4", "mpp5";
+ marvell,function = "ge";
+ };
+};
diff --git a/target/linux/mvebu/image/cortexa72.mk b/target/linux/mvebu/image/cortexa72.mk
index b7c633f9a7..a60c3884cd 100644
--- a/target/linux/mvebu/image/cortexa72.mk
+++ b/target/linux/mvebu/image/cortexa72.mk
@@ -33,6 +33,24 @@ define Device/checkpoint_v-80
endef
TARGET_DEVICES += checkpoint_v-80
+define Device/checkpoint_v-81
+ $(call Device/Default-arm64)
+ DEVICE_VENDOR := Check Point
+ DEVICE_MODEL := V-81
+ SOC := armada-8040
+ BOOT_SCRIPT := v-80
+ IMAGES += sysupgrade.gz
+ IMAGE/sysupgrade.gz := boot-scr eMMC | append-bootscript | pad-to 2048 | \
+ append-kernel | \
+ sysupgrade-tar kernel=$$$$@ dtb=$$(KDIR)/image-$$(DEVICE_DTS).dtb | \
+ gzip | append-metadata
+ ARTIFACTS := initramfs.dtb initramfs.scr
+ ARTIFACT/initramfs.dtb := append-dtb
+ ARTIFACT/initramfs.scr := boot-scr INIT | append-bootscript
+ DEVICE_PACKAGES := kmod-dsa-mv88e6xxx kmod-hwmon-nct7802 kmod-rtc-ds1307
+endef
+TARGET_DEVICES += checkpoint_v-81
+
define Device/globalscale_mochabin
$(call Device/Default-arm64)
DEVICE_VENDOR := Globalscale
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