[openwrt/openwrt] realtek: Add support for Zyxel XGS1210-12 Switch
LEDE Commits
lede-commits at lists.infradead.org
Mon Jun 16 04:47:32 PDT 2025
aparcar pushed a commit to openwrt/openwrt.git, branch main:
https://git.openwrt.org/6af9476b8a3c75ce65f17cfa89da7d35360a4756
commit 6af9476b8a3c75ce65f17cfa89da7d35360a4756
Author: Nicolas BERTRAND <nicolasbertrand89 at gmail.com>
AuthorDate: Tue Jun 10 11:09:06 2025 +0200
realtek: Add support for Zyxel XGS1210-12 Switch
The Zyxel XGS1210-12 Switch is a 10 + 2 port multi-GBit switch with
8 x 1000BaseT, 2 x 10/100/1000/2500BaseT Ethernet ports and
2 SFP+ module slot.
Hardware:
- RTL9302B SoC
- Macronix MX25L12833F (16MB flash)
- Nanja NT5CC64M16GP-1 (128MB DDR3 SDRAM)
- RTL8231 GPIO extender to control the port LEDs
- RTL8218D 8x Gigabit PHY
- RTL8226 2x 10m/100m/1/2.5 Gigabit PHY
- SFP+ 2x 10GBit slot
Power is supplied via a 12V 1.5A standard barrel connector. At the
right side behind the grid is UART serial connector. A Serial
header can be connected to from the outside of the switch trough
the airvents with a standard 2.54mm header.
Pins are from top to bottom Vcc(3.3V), TX, RX and GND. Serial
connection is via 115200 baud, 8N1.
A reset button is accessble through a hole in the front panel
At the time of this commit, all ethernet ports work under OpenWrt,
including the various NBaseT modes, SFP+ slots are supported with i2c bus.
Installation
--------------
* Connect serial as per the layout above. Connection parameters: 115200 8N1.
* Navigate to 'Management' in the OEM web interface and click on 'Firmware upgrade'
to the left.
* Upload the OpenWrt initramfs image, and wait till the switch reboots.
* Connect to the device through serial and change the U-boot boot command.
> fw_setenv bootcmd 'rtk network on; boota'
* Reboot, scp the sysupgrade image to /tmp, verify the checksum and flash it:
> sysupgrade openwrt-realtek-rtl930x-Zyxel_xgs1210-12-squashfs-sysupgrade.bin
* Upon reboot, you have a functional OpenWrt installation. Leave the bootcmd
value as is - without 'rtk network on' the switch will fail to initialise
the network.
Debug
------------
* Connect serial as per the layout above. Connection parameters: 115200 8N1.
* A tftp server is requiered, tftpd-hpa works well.
* Power the device, at U-Boot start rapidly hit Esc key to stop autoboot
* Enable network:
> rtk network on
* Change ip address (default is 192.168.1.1):
> setenv ipaddr 192.168.1.6
* Download initramfs:
> tftpboot 0x84f00000 192.168.1.111:openwrt-realtek-rtl930x-Zyxel_xgs1210-12-initramfs-kernel.bin
* Boot loaded file:
> bootm 0x84f00000
This prodecudre also apply to the sock firmware with the file XGS1210-12_V2.00(ABTY.1)C0.bix.
More information can be found on the page of XGS1250-12 as they share the same base.
Signed-off-by: Nicolas BERTRAND <nicolasbertrand89 at gmail.com>
[fixed white space error]
Signed-off-by: Paul Spooren <mail at aparcar.org>
---
.../linux/realtek/dts/rtl9302_zyxel_xgs1210-12.dts | 371 +++++++++++++++++++++
target/linux/realtek/image/rtl930x.mk | 16 +
2 files changed, 387 insertions(+)
diff --git a/target/linux/realtek/dts/rtl9302_zyxel_xgs1210-12.dts b/target/linux/realtek/dts/rtl9302_zyxel_xgs1210-12.dts
new file mode 100644
index 0000000000..11ffbc7827
--- /dev/null
+++ b/target/linux/realtek/dts/rtl9302_zyxel_xgs1210-12.dts
@@ -0,0 +1,371 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/dts-v1/;
+
+#include "rtl930x.dtsi"
+
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/leds/common.h>
+#include <dt-bindings/thermal/thermal.h>
+
+/ {
+ compatible = "zyxel,xgs1210-12", "realtek,rtl838x-soc";
+ model = "Zyxel XGS1210-12 Switch";
+
+ aliases {
+ led-boot = &led_pwr_sys;
+ led-failsafe = &led_pwr_sys;
+ led-running = &led_pwr_sys;
+ led-upgrade = &led_pwr_sys;
+ };
+
+ keys {
+ compatible = "gpio-keys";
+
+ mode {
+ label = "reset";
+ gpios = <&gpio0 22 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_RESTART>;
+ };
+ };
+
+ /* i2c of the SFP cage: port 11 & port 12 */
+ i2c0: i2c-rtl9300 at 1b00036c {
+ compatible = "realtek,rtl9300-i2c";
+ reg = <0x1b00036c 0x3c>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ sda-pin = <9>;
+ scl-pin = <8>;
+ clock-frequency = <100000>;
+ };
+
+ i2cmux {
+ compatible = "realtek,rtl9302-i2c-mux", "realtek,i2c-mux-rtl9300";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ i2c-parent = <&i2c0>;
+
+ /* i2c of the left SFP+ cage as seen from the front: port 11 */
+ i2c0_0: i2c at 0 {
+ reg = <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ sda-pin = <9>;
+ scl-pin = <8>;
+ };
+
+ /* i2c of the right SFP+ cage as seen from the front: port 12 */
+ i2c0_1: i2c at 1 {
+ reg = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ sda-pin = <10>;
+ scl-pin = <8>;
+ };
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinmux_disable_sys_led>;
+
+ led_pwr_sys: led-0 {
+ label = "green:power";
+ color = <LED_COLOR_ID_GREEN>;
+ function = LED_FUNCTION_POWER;
+ gpios = <&gpio0 0 GPIO_ACTIVE_HIGH>;
+ };
+ };
+
+ sfp0: sfp-p11 {
+ compatible = "sff,sfp";
+ i2c-bus = <&i2c0_0>;
+ los-gpio = <&gpio0 13 GPIO_ACTIVE_HIGH>;
+ tx-fault-gpio = <&gpio0 14 GPIO_ACTIVE_HIGH>;
+ mod-def0-gpio = <&gpio0 12 GPIO_ACTIVE_LOW>;
+ tx-disable-gpio = <&gpio0 11 GPIO_ACTIVE_HIGH>;
+ };
+
+ sfp1: sfp-p12 {
+ compatible = "sff,sfp";
+ i2c-bus = <&i2c0_1>;
+ los-gpio = <&gpio0 17 GPIO_ACTIVE_HIGH>;
+ tx-fault-gpio = <&gpio0 20 GPIO_ACTIVE_HIGH>;
+ mod-def0-gpio = <&gpio0 16 GPIO_ACTIVE_LOW>;
+ tx-disable-gpio = <&gpio0 15 GPIO_ACTIVE_HIGH>;
+ };
+
+ led_set: led_set {
+ compatible = "realtek,rtl9300-leds";
+ active-low;
+
+ // LED set 0:
+ // Amber: 100M/10M
+ // Yellow: 1G
+ led_set0 = <0x0a20 0x0b80>;
+
+ // LED set 1:
+ // Blue: 2.5G
+ // Green: 2.5G
+ // Yellow: 1G
+ // Amber: 100M/10M
+ // (Blue + Green = Cyan)
+ led_set1 = <0x0b80 0x0a20 0x0a08 0x0a08>;
+
+ // LED set 2:
+ // Blue: 10G/5G/2.5G
+ // Yellow: 5G/2.5G/1G
+ // (Blue + Yellow = Purple)
+ led_set2 = <0x0a2a 0x0a0b>;
+ };
+};
+
+&spi0 {
+ status = "okay";
+ flash at 0 {
+ compatible = "jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <10000000>;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition at 0 {
+ label = "u-boot";
+ reg = <0x0 0xe0000>;
+ read-only;
+ };
+ partition at e0000 {
+ label = "u-boot-env";
+ reg = <0xe0000 0x10000>;
+ };
+ partition at f0000 {
+ label = "u-boot-env2";
+ reg = <0xf0000 0x10000>;
+ read-only;
+ };
+ partition at 100000 {
+ label = "jffs2-cfg";
+ reg = <0x100000 0x100000>;
+ };
+ partition at 200000 {
+ label = "jffs2-log";
+ reg = <0x200000 0x100000>;
+ };
+ partition at b300000 {
+ label = "firmware";
+ reg = <0x300000 0xce0000>;
+ compatible = "openwrt,uimage", "denx,uimage";
+ openwrt,ih-magic = <0x93001210>;
+ };
+ partition at fe0000 {
+ label = "log";
+ reg = <0xfe0000 0x20000>;
+ read-only;
+ };
+ };
+ };
+};
+
+ðernet0 {
+ mdio: mdio-bus {
+ compatible = "realtek,rtl838x-mdio";
+ regmap = <ðernet0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ /* External RTL8218D PHY */
+ phy0: ethernet-phy at 0 {
+ reg = <0>;
+ compatible = "ethernet-phy-ieee802.3-c22";
+ rtl9300,smi-address = <0 0>;
+ sds = < 2 >;
+ // Disabled because we do not know how to bring up again
+ // reset-gpios = <&gpio0 21 GPIO_ACTIVE_LOW>;
+ };
+ phy1: ethernet-phy at 1 {
+ reg = <1>;
+ compatible = "ethernet-phy-ieee802.3-c22";
+ rtl9300,smi-address = <0 1>;
+ };
+ phy2: ethernet-phy at 2 {
+ reg = <2>;
+ compatible = "ethernet-phy-ieee802.3-c22";
+ rtl9300,smi-address = <0 2>;
+ };
+ phy3: ethernet-phy at 3 {
+ reg = <3>;
+ compatible = "ethernet-phy-ieee802.3-c22";
+ rtl9300,smi-address = <0 3>;
+ };
+ phy4: ethernet-phy at 4 {
+ reg = <4>;
+ compatible = "ethernet-phy-ieee802.3-c22";
+ rtl9300,smi-address = <0 4>;
+ };
+ phy5: ethernet-phy at 5 {
+ reg = <5>;
+ compatible = "ethernet-phy-ieee802.3-c22";
+ rtl9300,smi-address = <0 5>;
+ };
+ phy6: ethernet-phy at 6 {
+ reg = <6>;
+ compatible = "ethernet-phy-ieee802.3-c22";
+ rtl9300,smi-address = <0 6>;
+ };
+ phy7: ethernet-phy at 7 {
+ reg = <7>;
+ compatible = "ethernet-phy-ieee802.3-c22";
+ rtl9300,smi-address = <0 7>;
+ };
+
+ /* External RTL8226 PHYs */
+ phy24: ethernet-phy at 24 {
+ reg = <24>;
+ compatible = "ethernet-phy-ieee802.3-c45";
+ rtl9300,smi-address = <1 8>;
+ sds = < 6 >;
+ // Disabled because we do not know how to bring up again
+ // reset-gpios = <&gpio0 21 GPIO_ACTIVE_LOW>;
+ };
+
+ phy25: ethernet-phy at 25 {
+ reg = <25>;
+ compatible = "ethernet-phy-ieee802.3-c45";
+ rtl9300,smi-address = <2 9>;
+ sds = < 7 >;
+ // Disabled because we do not know how to bring up again
+ // reset-gpios = <&gpio0 21 GPIO_ACTIVE_LOW>;
+ };
+
+ /* SFP0 Ports */
+ phy26: ethernet-phy at 26 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ phy-is-integrated;
+ reg = <26>;
+ sds = < 8 >;
+ };
+
+ /* SFP1 Ports */
+ phy27: ethernet-phy at 27 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ phy-is-integrated;
+ reg = <27>;
+ sds = < 9 >;
+ };
+
+ };
+};
+
+&switch0 {
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port at 0 {
+ reg = <0>;
+ label = "lan1";
+ phy-handle = <&phy0>;
+ phy-mode = "usxgmii";
+ led-set = <0>;
+ };
+ port at 1 {
+ reg = <1>;
+ label = "lan2";
+ phy-handle = <&phy1>;
+ phy-mode = "usxgmii";
+ led-set = <0>;
+ };
+ port at 2 {
+ reg = <2>;
+ label = "lan3";
+ phy-handle = <&phy2>;
+ phy-mode = "usxgmii";
+ led-set = <0>;
+ };
+ port at 3 {
+ reg = <3>;
+ label = "lan4";
+ phy-handle = <&phy3>;
+ phy-mode = "usxgmii";
+ led-set = <0>;
+ };
+ port at 4 {
+ reg = <4>;
+ label = "lan5";
+ phy-handle = <&phy4>;
+ phy-mode = "usxgmii";
+ led-set = <0>;
+ };
+ port at 5 {
+ reg = <5>;
+ label = "lan6";
+ phy-handle = <&phy5>;
+ phy-mode = "usxgmii";
+ led-set = <0>;
+ };
+ port at 6 {
+ reg = <6>;
+ label = "lan7";
+ phy-handle = <&phy6>;
+ phy-mode = "usxgmii";
+ led-set = <0>;
+ };
+ port at 7 {
+ reg = <7>;
+ label = "lan8";
+ phy-handle = <&phy7>;
+ phy-mode = "usxgmii";
+ led-set = <0>;
+ };
+
+ port at 24 {
+ reg = <24>;
+ label = "lan9";
+ phy-mode = "hsgmii";
+ phy-handle = <&phy24>;
+ led-set = <1>;
+ };
+ port at 25 {
+ reg = <25>;
+ label = "lan10";
+ phy-mode = "hsgmii";
+ phy-handle = <&phy25>;
+ led-set = <1>;
+ };
+
+ port at 26 {
+ reg = <26>;
+ label = "lan11";
+ phy-mode = "1000base-x"; //"10gbase-r";
+ pseudo-phy-handle = <&phy26>;
+ sfp = <&sfp0>;
+ led-set = <2>;
+ managed = "in-band-status";
+ };
+
+ port at 27 {
+ reg = <27>;
+ label = "lan12";
+ phy-mode = "1000base-x";
+ pseudo-phy-handle = <&phy27>;
+ sfp = <&sfp1>;
+ led-set = <2>;
+ managed = "in-band-status";
+ };
+
+ port at 28 {
+ ethernet = <ðernet0>;
+ reg = <28>;
+ phy-mode = "internal";
+ fixed-link {
+ speed = <10000>;
+ full-duplex;
+ };
+ };
+ };
+};
diff --git a/target/linux/realtek/image/rtl930x.mk b/target/linux/realtek/image/rtl930x.mk
index 1119cd3f2c..28c17d6c48 100644
--- a/target/linux/realtek/image/rtl930x.mk
+++ b/target/linux/realtek/image/rtl930x.mk
@@ -31,6 +31,22 @@ define Device/xikestor_sks8300-8x
endef
TARGET_DEVICES += xikestor_sks8300-8x
+define Device/zyxel_xgs1210-12
+ SOC := rtl9302
+ UIMAGE_MAGIC := 0x93001210
+ ZYXEL_VERS := ABTY
+ DEVICE_VENDOR := Zyxel
+ DEVICE_MODEL := XGS1210-12
+ IMAGE_SIZE := 13312k
+ KERNEL_INITRAMFS := \
+ kernel-bin | \
+ append-dtb | \
+ gzip | \
+ zyxel-vers | \
+ uImage gzip
+endef
+TARGET_DEVICES += zyxel_xgs1210-12
+
define Device/zyxel_xgs1250-12
SOC := rtl9302
UIMAGE_MAGIC := 0x93001250
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