[openwrt/openwrt] imx: 6-12: refresh patches and kernel configs
LEDE Commits
lede-commits at lists.infradead.org
Fri Jun 6 23:39:21 PDT 2025
nick pushed a commit to openwrt/openwrt.git, branch main:
https://git.openwrt.org/b0d2b33e3c47a9b2d17a9b918f9021b01a68daa4
commit b0d2b33e3c47a9b2d17a9b918f9021b01a68daa4
Author: Tim Harvey <tharvey at gateworks.com>
AuthorDate: Fri Jun 6 09:04:39 2025 -0700
imx: 6-12: refresh patches and kernel configs
patches:
- remove patches from 6.7-6.12 that are now upstream.
- refresh remaining patches
- 502-6.13-arm64-dts-freescale-rename-gw7905-to-gw75xx.patch was
misnamed as that patch went upstream in 6.12 and thus is also removed
- 504-6.13-arm64-dts-imx-Add-i.MX8M-Plus-Gateworks-GW82XX-2X-support.patch
was refreshed to the final version that was accepted upstream
- 600-PCI-imx6-Start-link-at-max-gen-first-for-IMX8MM-and-IMX8MP.patch
was removed while I investigate an upstream approach for the issue
it was working around.
configs:
- config-6.12: unset new configs not needed for all cortexa7/a9/a53
- cortexa53/config-default: added new CONFIG_PCI_IMX6_HOST config for cortexA53 (IMX8M)
Signed-off-by: Tim Harvey <tharvey at gateworks.com>
Link: https://github.com/openwrt/openwrt/pull/19029
Signed-off-by: Nick Hainke <vincent at systemli.org>
---
target/linux/imx/config-6.12 | 11 +
target/linux/imx/cortexa53/config-default | 1 +
...ts-imx8mp-add-imx8mp-venice-gw74xx-imx219.patch | 136 --
...4-dts-imx8mm-venice-gw73xx-add-TPM-device.patch | 39 -
...4-dts-imx8mp-venice-gw73xx-add-TPM-device.patch | 39 -
...4-dts-imx8mm-venice-gw72xx-add-TPM-device.patch | 39 -
...4-dts-imx8mp-venice-gw72xx-add-TPM-device.patch | 39 -
...4-dts-imx8mm-venice-gw71xx-add-TPM-device.patch | 39 -
...4-dts-imx8mp-venice-gw71xx-add-TPM-device.patch | 39 -
...ts-imx8mm-venice-gw7901-add-digital-I-O-d.patch | 34 -
...4-dts-imx8mm-venice-gw7901-add-TPM-device.patch | 45 -
...ts-freescale-imx8mp-venice-gw72xx-2x-fix-.patch | 38 -
...ts-freescale-imx8mp-venice-gw73xx-2x-fix-.patch | 38 -
...dts-imx8mp-venice-gw74xx-add-ADC-rail-for.patch | 30 -
...dts-imx8mp-venice-gw72xx-add-mac-addr-for.patch | 80 --
...dts-imx8mp-venice-gw73xx-add-mac-addr-for.patch | 82 --
...3-arm64-dts-imx8mm-venice-add-RTC-aliases.patch | 22 +-
...mx8mp-venice-gw74xx-add-M2SKT_GPIO10-gpio.patch | 4 +-
...m64-dts-freescale-rename-gw7905-to-gw75xx.patch | 1426 --------------------
...d-i.MX8M-Plus-Gateworks-GW82XX-2X-support.patch | 519 +------
...nk-at-max-gen-first-for-IMX8MM-and-IMX8MP.patch | 121 --
21 files changed, 38 insertions(+), 2783 deletions(-)
diff --git a/target/linux/imx/config-6.12 b/target/linux/imx/config-6.12
index 33478f29b9..a21530e9ad 100644
--- a/target/linux/imx/config-6.12
+++ b/target/linux/imx/config-6.12
@@ -52,11 +52,14 @@ CONFIG_CLKSRC_MMIO=y
# CONFIG_CLK_IMX8MQ is not set
# CONFIG_CLK_IMX8ULP is not set
# CONFIG_CLK_IMX93 is not set
+# CONFIG_CLK_IMX95_BLK_CTL is not set
CONFIG_CLONE_BACKWARDS=y
CONFIG_CLZ_TAB=y
+CONFIG_ARM64_PLATFORM_DEVICES=y
CONFIG_COMMON_CLK=y
CONFIG_COMPACT_UNEVICTABLE_DEFAULT=1
CONFIG_COMPAT_32BIT_TIME=y
+# CONFIG_COMPRESSED_INSTALL is not set
CONFIG_CONTEXT_TRACKING=y
CONFIG_CONTEXT_TRACKING_IDLE=y
CONFIG_CPUFREQ_DT=y
@@ -167,10 +170,13 @@ CONFIG_DMA_OPS=y
CONFIG_DMA_VIRTUAL_CHANNELS=y
# CONFIG_DRM_DW_HDMI_GP_AUDIO is not set
# CONFIG_DRM_FSL_LDB is not set
+# CONFIG_DRM_IMX8MP_DW_HDMI_BRIDGE is not set
+# CONFIG_DRM_IMX8MP_HDMI_PVI is not set
# CONFIG_DRM_IMX8QM_LDB is not set
# CONFIG_DRM_IMX8QXP_LDB is not set
# CONFIG_DRM_IMX8QXP_PIXEL_COMBINER is not set
# CONFIG_DRM_IMX8QXP_PIXEL_LINK_TO_DPI is not set
+# CONFIG_DRM_IMX93_MIPI_DSI is not set
# CONFIG_DRM_IMX_LCDC is not set
CONFIG_DTC=y
CONFIG_EDAC_ATOMIC_SCRUB=y
@@ -348,6 +354,7 @@ CONFIG_PHYLIB=y
CONFIG_PHYLINK=y
CONFIG_PINCTRL=y
# CONFIG_PINCTRL_IMX8ULP is not set
+# CONFIG_PINCTRL_IMX91 is not set
# CONFIG_PINCTRL_IMX93 is not set
# CONFIG_PINCTRL_IMXRT1050 is not set
# CONFIG_PINCTRL_IMXRT1170 is not set
@@ -379,6 +386,10 @@ CONFIG_REGULATOR_ANATOP=y
CONFIG_REGULATOR_FIXED_VOLTAGE=y
CONFIG_REGULATOR_PFUZE100=y
CONFIG_RESET_CONTROLLER=y
+# CONFIG_RESET_IMX7 is not set
+# CONFIG_RESET_IMX8MP_AUDIOMIX is not set
+# CONFIG_PHY_FSL_IMX8QM_HSIO is not set
+# CONFIG_PHY_FSL_SAMSUNG_HDMI_PHY is not set
CONFIG_RFS_ACCEL=y
CONFIG_RPS=y
CONFIG_RTC_CLASS=y
diff --git a/target/linux/imx/cortexa53/config-default b/target/linux/imx/cortexa53/config-default
index ac8e646da4..248baddbf5 100644
--- a/target/linux/imx/cortexa53/config-default
+++ b/target/linux/imx/cortexa53/config-default
@@ -118,6 +118,7 @@ CONFIG_PCIE_PME=y
CONFIG_PCI_DOMAINS=y
CONFIG_PCI_DOMAINS_GENERIC=y
CONFIG_PCI_IMX6=y
+CONFIG_PCI_IMX6_HOST=y
CONFIG_PCI_MSI=y
CONFIG_PCI_MSI_IRQ_DOMAIN=y
CONFIG_PCS_XPCS=y
diff --git a/target/linux/imx/patches-6.12/400-6.7-arm64-dts-imx8mp-add-imx8mp-venice-gw74xx-imx219.patch b/target/linux/imx/patches-6.12/400-6.7-arm64-dts-imx8mp-add-imx8mp-venice-gw74xx-imx219.patch
deleted file mode 100644
index 36025a185c..0000000000
--- a/target/linux/imx/patches-6.12/400-6.7-arm64-dts-imx8mp-add-imx8mp-venice-gw74xx-imx219.patch
+++ /dev/null
@@ -1,136 +0,0 @@
-From 60fd951029603a0a6e019f16d53fb329dbd001f4 Mon Sep 17 00:00:00 2001
-From: Tim Harvey <tharvey at gateworks.com>
-Date: Fri, 7 Jul 2023 16:24:19 -0700
-Subject: [PATCH 400/413] 6.7: arm64: dts: imx8mp: add
- imx8mp-venice-gw74xx-imx219 overlay for rpi v2 camera
-
-Add support for the RaspberryPi Camera v2 which is an IMX219 8MP module:
- - https://datasheets.raspberrypi.com/camera/camera-v2-schematics.pdf
- - has its own on-board 24MHz osc so no clock required from baseboard
- - pin 11 enables 1.8V and 2.8V LDO which is connected to
- GW74xx MIPI_GPIO4 (IMX8MP GPIO1_IO4) so we use this as a gpio
-
-Support is added via a device-tree overlay.
-
-The IMX219 supports RAW8/RAW10 image formats.
-
-Example configuration:
-media-ctl -l "'imx219 3-0010':0->'csis-32e40000.csi':0[1]"
-media-ctl -v -V "'imx219 3-0010':0 [fmt:SRGGB8/640x480 field:none]"
-media-ctl -v -V "'crossbar':0 [fmt:SRGGB8/640x480 field:none]"
-media-ctl -v -V "'mxc_isi.0':0 [fmt:SRGGB8/640x480 field:none]"
-v4l2-ctl --set-fmt-video=width=640,height=480,pixelformat=RGGB
-v4l2-ctl --stream-mmap --stream-to=frame.raw --stream-count=1
-convert -size 640x480 -depth 8 gray:frame.raw frame.png
-gst-launch-1.0 v4l2src ! \
- video/x-bayer,format=rggb,width=640,height=480,framerate=10/1 ! \
- bayer2rgb ! fbdevsink
-
-Signed-off-by: Tim Harvey <tharvey at gateworks.com>
----
- arch/arm64/boot/dts/freescale/Makefile | 2 +
- .../imx8mp-venice-gw74xx-imx219.dtso | 80 +++++++++++++++++++
- 2 files changed, 82 insertions(+)
- create mode 100644 arch/arm64/boot/dts/freescale/imx8mp-venice-gw74xx-imx219.dtso
-
---- a/arch/arm64/boot/dts/freescale/Makefile
-+++ b/arch/arm64/boot/dts/freescale/Makefile
-@@ -159,6 +159,7 @@ imx8mm-venice-gw73xx-0x-rpidsi-dtbs := i
- imx8mm-venice-gw73xx-0x-rs232-rts-dtbs := imx8mm-venice-gw73xx-0x.dtb imx8mm-venice-gw73xx-0x-rs232-rts.dtbo
- imx8mm-venice-gw73xx-0x-rs422-dtbs := imx8mm-venice-gw73xx-0x.dtb imx8mm-venice-gw73xx-0x-rs422.dtbo
- imx8mm-venice-gw73xx-0x-rs485-dtbs := imx8mm-venice-gw73xx-0x.dtb imx8mm-venice-gw73xx-0x-rs485.dtbo
-+imx8mp-venice-gw74xx-imx219-dtbs := imx8mp-venice-gw74xx.dtb imx8mp-venice-gw74xx-imx219.dtbo
- imx8mp-venice-gw74xx-rpidsi-dtbs := imx8mp-venice-gw74xx.dtb imx8mp-venice-gw74xx-rpidsi.dtbo
-
- dtb-$(CONFIG_ARCH_MXC) += imx8mm-venice-gw72xx-0x-imx219.dtb
-@@ -171,6 +172,7 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mm-venice-
- dtb-$(CONFIG_ARCH_MXC) += imx8mm-venice-gw73xx-0x-rs232-rts.dtb
- dtb-$(CONFIG_ARCH_MXC) += imx8mm-venice-gw73xx-0x-rs422.dtb
- dtb-$(CONFIG_ARCH_MXC) += imx8mm-venice-gw73xx-0x-rs485.dtb
-+dtb-$(CONFIG_ARCH_MXC) += imx8mp-venice-gw74xx-imx219.dtb
- dtb-$(CONFIG_ARCH_MXC) += imx8mp-venice-gw74xx-rpidsi.dtb
-
- dtb-$(CONFIG_ARCH_S32) += s32g274a-evb.dtb
---- /dev/null
-+++ b/arch/arm64/boot/dts/freescale/imx8mp-venice-gw74xx-imx219.dtso
-@@ -0,0 +1,80 @@
-+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-+/*
-+ * Copyright 2023 Gateworks Corporation
-+ */
-+
-+#include <dt-bindings/gpio/gpio.h>
-+
-+#include "imx8mp-pinfunc.h"
-+
-+/dts-v1/;
-+/plugin/;
-+
-+&{/} {
-+ compatible = "gw,imx8mp-gw74xx", "fsl,imx8mp";
-+
-+ reg_cam: regulator-cam {
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&pinctrl_reg_cam>;
-+ compatible = "regulator-fixed";
-+ regulator-name = "reg_cam";
-+ gpio = <&gpio1 4 GPIO_ACTIVE_HIGH>;
-+ enable-active-high;
-+ regulator-min-microvolt = <1800000>;
-+ regulator-max-microvolt = <1800000>;
-+ };
-+
-+ cam24m: cam24m {
-+ compatible = "fixed-clock";
-+ #clock-cells = <0>;
-+ clock-frequency = <24000000>;
-+ clock-output-names = "cam24m";
-+ };
-+};
-+
-+&i2c4 {
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+
-+ imx219: sensor at 10 {
-+ compatible = "sony,imx219";
-+ reg = <0x10>;
-+ clocks = <&cam24m>;
-+ VDIG-supply = <®_cam>;
-+
-+ port {
-+ /* MIPI CSI-2 bus endpoint */
-+ imx219_to_mipi_csi2: endpoint {
-+ remote-endpoint = <&mipi_csi_0_in>;
-+ clock-lanes = <0>;
-+ data-lanes = <1 2>;
-+ link-frequencies = /bits/ 64 <456000000>;
-+ };
-+ };
-+ };
-+};
-+
-+&isi_0 {
-+ status = "okay";
-+};
-+
-+&mipi_csi_0 {
-+ status = "okay";
-+
-+ ports {
-+ port at 0 {
-+ mipi_csi_0_in: endpoint {
-+ remote-endpoint = <&imx219_to_mipi_csi2>;
-+ data-lanes = <1 2>;
-+ };
-+ };
-+ };
-+};
-+
-+&iomuxc {
-+ pinctrl_reg_cam: regcamgrp {
-+ fsl,pins = <
-+ MX8MP_IOMUXC_GPIO1_IO04__GPIO1_IO04 0x41
-+ >;
-+ };
-+};
diff --git a/target/linux/imx/patches-6.12/401-6.7-arm64-dts-imx8mm-venice-gw73xx-add-TPM-device.patch b/target/linux/imx/patches-6.12/401-6.7-arm64-dts-imx8mm-venice-gw73xx-add-TPM-device.patch
deleted file mode 100644
index 782573f6d0..0000000000
--- a/target/linux/imx/patches-6.12/401-6.7-arm64-dts-imx8mm-venice-gw73xx-add-TPM-device.patch
+++ /dev/null
@@ -1,39 +0,0 @@
-From 816e40232faaa4aa0364ca8da7f86eaf27b0d9ff Mon Sep 17 00:00:00 2001
-From: Tim Harvey <tharvey at gateworks.com>
-Date: Mon, 26 Jun 2023 11:51:13 -0700
-Subject: [PATCH 401/413] 6.7: arm64: dts: imx8mm-venice-gw73xx: add TPM device
-
-Add the TPM device found on the GW73xx revision F PCB.
-
-Signed-off-by: Tim Harvey <tharvey at gateworks.com>
----
- .../arm64/boot/dts/freescale/imx8mm-venice-gw73xx.dtsi | 10 +++++++++-
- 1 file changed, 9 insertions(+), 1 deletion(-)
-
---- a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx.dtsi
-+++ b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx.dtsi
-@@ -104,8 +104,15 @@
- &ecspi2 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_spi2>;
-- cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;
-+ cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>,
-+ <&gpio1 10 GPIO_ACTIVE_LOW>;
- status = "okay";
-+
-+ tpm at 1 {
-+ compatible = "tcg,tpm_tis-spi";
-+ reg = <0x1>;
-+ spi-max-frequency = <36000000>;
-+ };
- };
-
- &gpio1 {
-@@ -362,6 +369,7 @@
- MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0xd6
- MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0xd6
- MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0xd6
-+ MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0xd6
- >;
- };
-
diff --git a/target/linux/imx/patches-6.12/402-6.7-arm64-dts-imx8mp-venice-gw73xx-add-TPM-device.patch b/target/linux/imx/patches-6.12/402-6.7-arm64-dts-imx8mp-venice-gw73xx-add-TPM-device.patch
deleted file mode 100644
index a106c0bc21..0000000000
--- a/target/linux/imx/patches-6.12/402-6.7-arm64-dts-imx8mp-venice-gw73xx-add-TPM-device.patch
+++ /dev/null
@@ -1,39 +0,0 @@
-From 916ffc08e8cdd3beccd78291eac9dc5592d83de1 Mon Sep 17 00:00:00 2001
-From: Tim Harvey <tharvey at gateworks.com>
-Date: Thu, 24 Aug 2023 11:07:48 -0700
-Subject: [PATCH 402/413] 6.7: arm64: dts: imx8mp-venice-gw73xx: add TPM device
-
-Add the TPM device found on the GW73xx revision F PCB.
-
-Signed-off-by: Tim Harvey <tharvey at gateworks.com>
----
- .../arm64/boot/dts/freescale/imx8mp-venice-gw73xx.dtsi | 10 +++++++++-
- 1 file changed, 9 insertions(+), 1 deletion(-)
-
---- a/arch/arm64/boot/dts/freescale/imx8mp-venice-gw73xx.dtsi
-+++ b/arch/arm64/boot/dts/freescale/imx8mp-venice-gw73xx.dtsi
-@@ -95,8 +95,15 @@
- &ecspi2 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_spi2>;
-- cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;
-+ cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>,
-+ <&gpio1 10 GPIO_ACTIVE_LOW>;
- status = "okay";
-+
-+ tpm at 1 {
-+ compatible = "tcg,tpm_tis-spi";
-+ reg = <0x1>;
-+ spi-max-frequency = <36000000>;
-+ };
- };
-
- &gpio4 {
-@@ -327,6 +334,7 @@
- MX8MP_IOMUXC_ECSPI2_MOSI__ECSPI2_MOSI 0x140
- MX8MP_IOMUXC_ECSPI2_MISO__ECSPI2_MISO 0x140
- MX8MP_IOMUXC_ECSPI2_SS0__GPIO5_IO13 0x140
-+ MX8MP_IOMUXC_GPIO1_IO10__GPIO1_IO10 0x140
- >;
- };
-
diff --git a/target/linux/imx/patches-6.12/403-6.8-arm64-dts-imx8mm-venice-gw72xx-add-TPM-device.patch b/target/linux/imx/patches-6.12/403-6.8-arm64-dts-imx8mm-venice-gw72xx-add-TPM-device.patch
deleted file mode 100644
index 01b79e26e8..0000000000
--- a/target/linux/imx/patches-6.12/403-6.8-arm64-dts-imx8mm-venice-gw72xx-add-TPM-device.patch
+++ /dev/null
@@ -1,39 +0,0 @@
-From 0adf19579692623d9d9202d2868aa7cd81451148 Mon Sep 17 00:00:00 2001
-From: Tim Harvey <tharvey at gateworks.com>
-Date: Thu, 28 Sep 2023 14:10:39 -0700
-Subject: [PATCH 403/413] 6.8: arm64: dts: imx8mm-venice-gw72xx: add TPM device
-
-Add the TPM device found on the GW72xx revision F PCB.
-
-Signed-off-by: Tim Harvey <tharvey at gateworks.com>
----
- .../arm64/boot/dts/freescale/imx8mm-venice-gw72xx.dtsi | 10 +++++++++-
- 1 file changed, 9 insertions(+), 1 deletion(-)
-
---- a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx.dtsi
-+++ b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx.dtsi
-@@ -84,8 +84,15 @@
- &ecspi2 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_spi2>;
-- cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;
-+ cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>,
-+ <&gpio1 10 GPIO_ACTIVE_LOW>;
- status = "okay";
-+
-+ tpm at 1 {
-+ compatible = "tcg,tpm_tis-spi";
-+ reg = <0x1>;
-+ spi-max-frequency = <36000000>;
-+ };
- };
-
- &gpio1 {
-@@ -313,6 +320,7 @@
- MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0xd6
- MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0xd6
- MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0xd6
-+ MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0xd6
- >;
- };
-
diff --git a/target/linux/imx/patches-6.12/404-6.8-arm64-dts-imx8mp-venice-gw72xx-add-TPM-device.patch b/target/linux/imx/patches-6.12/404-6.8-arm64-dts-imx8mp-venice-gw72xx-add-TPM-device.patch
deleted file mode 100644
index 1e399f72f5..0000000000
--- a/target/linux/imx/patches-6.12/404-6.8-arm64-dts-imx8mp-venice-gw72xx-add-TPM-device.patch
+++ /dev/null
@@ -1,39 +0,0 @@
-From 9d3932717327f6086a9a81a41df5bf5250aee782 Mon Sep 17 00:00:00 2001
-From: Tim Harvey <tharvey at gateworks.com>
-Date: Thu, 28 Sep 2023 14:11:01 -0700
-Subject: [PATCH 404/413] 6.8: arm64: dts: imx8mp-venice-gw72xx: add TPM device
-
-Add the TPM device found on the GW72xx revision F PCB.
-
-Signed-off-by: Tim Harvey <tharvey at gateworks.com>
----
- .../arm64/boot/dts/freescale/imx8mp-venice-gw72xx.dtsi | 10 +++++++++-
- 1 file changed, 9 insertions(+), 1 deletion(-)
-
---- a/arch/arm64/boot/dts/freescale/imx8mp-venice-gw72xx.dtsi
-+++ b/arch/arm64/boot/dts/freescale/imx8mp-venice-gw72xx.dtsi
-@@ -83,8 +83,15 @@
- &ecspi2 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_spi2>;
-- cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;
-+ cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>,
-+ <&gpio1 10 GPIO_ACTIVE_LOW>;
- status = "okay";
-+
-+ tpm at 1 {
-+ compatible = "tcg,tpm_tis-spi";
-+ reg = <0x1>;
-+ spi-max-frequency = <36000000>;
-+ };
- };
-
- &gpio4 {
-@@ -286,6 +293,7 @@
- MX8MP_IOMUXC_ECSPI2_MOSI__ECSPI2_MOSI 0x140
- MX8MP_IOMUXC_ECSPI2_MISO__ECSPI2_MISO 0x140
- MX8MP_IOMUXC_ECSPI2_SS0__GPIO5_IO13 0x140
-+ MX8MP_IOMUXC_GPIO1_IO10__GPIO1_IO10 0x140
- >;
- };
-
diff --git a/target/linux/imx/patches-6.12/405-6.9-arm64-dts-imx8mm-venice-gw71xx-add-TPM-device.patch b/target/linux/imx/patches-6.12/405-6.9-arm64-dts-imx8mm-venice-gw71xx-add-TPM-device.patch
deleted file mode 100644
index 57ad826668..0000000000
--- a/target/linux/imx/patches-6.12/405-6.9-arm64-dts-imx8mm-venice-gw71xx-add-TPM-device.patch
+++ /dev/null
@@ -1,39 +0,0 @@
-From 6cea7c46172eca323e9ce7e6aab8f8506eb92b4b Mon Sep 17 00:00:00 2001
-From: Tim Harvey <tharvey at gateworks.com>
-Date: Wed, 29 Nov 2023 09:53:04 -0800
-Subject: [PATCH 405/413] 6.9: arm64: dts: imx8mm-venice-gw71xx: add TPM device
-
-Add the TPM device found on the GW71xx revision E PCB.
-
-Signed-off-by: Tim Harvey <tharvey at gateworks.com>
----
- .../arm64/boot/dts/freescale/imx8mm-venice-gw71xx.dtsi | 10 +++++++++-
- 1 file changed, 9 insertions(+), 1 deletion(-)
-
---- a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw71xx.dtsi
-+++ b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw71xx.dtsi
-@@ -53,8 +53,15 @@
- &ecspi2 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_spi2>;
-- cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;
-+ cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>,
-+ <&gpio1 10 GPIO_ACTIVE_LOW>;
- status = "okay";
-+
-+ tpm at 1 {
-+ compatible = "tcg,tpm_tis-spi";
-+ reg = <0x1>;
-+ spi-max-frequency = <36000000>;
-+ };
- };
-
- &gpio1 {
-@@ -201,6 +208,7 @@
- MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0xd6
- MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0xd6
- MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0xd6
-+ MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0xd6
- >;
- };
-
diff --git a/target/linux/imx/patches-6.12/406-6.9-arm64-dts-imx8mp-venice-gw71xx-add-TPM-device.patch b/target/linux/imx/patches-6.12/406-6.9-arm64-dts-imx8mp-venice-gw71xx-add-TPM-device.patch
deleted file mode 100644
index b96fc907a4..0000000000
--- a/target/linux/imx/patches-6.12/406-6.9-arm64-dts-imx8mp-venice-gw71xx-add-TPM-device.patch
+++ /dev/null
@@ -1,39 +0,0 @@
-From 9095a68c0b7084a7819e697ef38d0c987531c8ab Mon Sep 17 00:00:00 2001
-From: Tim Harvey <tharvey at gateworks.com>
-Date: Wed, 29 Nov 2023 17:11:51 -0800
-Subject: [PATCH 406/413] 6.9: arm64: dts: imx8mp-venice-gw71xx: add TPM device
-
-Add the TPM device found on the GW71xx revision E PCB.
-
-Signed-off-by: Tim Harvey <tharvey at gateworks.com>
----
- .../arm64/boot/dts/freescale/imx8mp-venice-gw71xx.dtsi | 10 +++++++++-
- 1 file changed, 9 insertions(+), 1 deletion(-)
-
---- a/arch/arm64/boot/dts/freescale/imx8mp-venice-gw71xx.dtsi
-+++ b/arch/arm64/boot/dts/freescale/imx8mp-venice-gw71xx.dtsi
-@@ -48,8 +48,15 @@
- &ecspi2 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_spi2>;
-- cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;
-+ cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>,
-+ <&gpio1 10 GPIO_ACTIVE_LOW>;
- status = "okay";
-+
-+ tpm at 1 {
-+ compatible = "tcg,tpm_tis-spi";
-+ reg = <0x1>;
-+ spi-max-frequency = <36000000>;
-+ };
- };
-
- &gpio4 {
-@@ -217,6 +224,7 @@
- MX8MP_IOMUXC_ECSPI2_MOSI__ECSPI2_MOSI 0x140
- MX8MP_IOMUXC_ECSPI2_MISO__ECSPI2_MISO 0x140
- MX8MP_IOMUXC_ECSPI2_SS0__GPIO5_IO13 0x140
-+ MX8MP_IOMUXC_GPIO1_IO10__GPIO1_IO10 0x140
- >;
- };
-
diff --git a/target/linux/imx/patches-6.12/407-6.9-arm64-dts-imx8mm-venice-gw7901-add-digital-I-O-d.patch b/target/linux/imx/patches-6.12/407-6.9-arm64-dts-imx8mm-venice-gw7901-add-digital-I-O-d.patch
deleted file mode 100644
index ebee3c4be1..0000000000
--- a/target/linux/imx/patches-6.12/407-6.9-arm64-dts-imx8mm-venice-gw7901-add-digital-I-O-d.patch
+++ /dev/null
@@ -1,34 +0,0 @@
-From e5bc89e60590581b0d31e8c6c6361c6caf5583bb Mon Sep 17 00:00:00 2001
-From: Tim Harvey <tharvey at gateworks.com>
-Date: Tue, 21 Nov 2023 11:12:24 -0800
-Subject: [PATCH 407/413] 6.9: arm64: dts: imx8mm-venice-gw7901: add digital
- I/O direction control GPIO's
-
-The GW7901 has GPIO's to configure the direction of its isolated
-digital I/O signals. Add the GPIO pinmux and line names.
-
-Signed-off-by: Tim Harvey <tharvey at gateworks.com>
----
- arch/arm64/boot/dts/freescale/imx8mm-venice-gw7901.dts | 4 +++-
- 1 file changed, 3 insertions(+), 1 deletion(-)
-
---- a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7901.dts
-+++ b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7901.dts
-@@ -319,7 +319,7 @@
-
- &gpio4 {
- gpio-line-names = "", "", "", "",
-- "", "", "uart3_rs232#", "uart3_rs422#",
-+ "dig1_ctl", "dig2_ctl", "uart3_rs232#", "uart3_rs422#",
- "uart3_rs485#", "", "", "", "", "", "", "",
- "", "", "", "", "", "", "", "",
- "", "", "", "uart4_rs485#", "", "sim1det#", "sim2det#", "";
-@@ -842,6 +842,8 @@
-
- pinctrl_hog: hoggrp {
- fsl,pins = <
-+ MX8MM_IOMUXC_SAI1_RXD2_GPIO4_IO4 0x40000041 /* DIG1_CTL */
-+ MX8MM_IOMUXC_SAI1_RXD3_GPIO4_IO5 0x40000041 /* DIG2_CTL */
- MX8MM_IOMUXC_SPDIF_TX_GPIO5_IO3 0x40000041 /* DIG2_OUT */
- MX8MM_IOMUXC_SPDIF_RX_GPIO5_IO4 0x40000041 /* DIG2_IN */
- MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x40000041 /* DIG1_IN */
diff --git a/target/linux/imx/patches-6.12/408-6.9-arm64-dts-imx8mm-venice-gw7901-add-TPM-device.patch b/target/linux/imx/patches-6.12/408-6.9-arm64-dts-imx8mm-venice-gw7901-add-TPM-device.patch
deleted file mode 100644
index e86c29fbb8..0000000000
--- a/target/linux/imx/patches-6.12/408-6.9-arm64-dts-imx8mm-venice-gw7901-add-TPM-device.patch
+++ /dev/null
@@ -1,45 +0,0 @@
-From f905e9a03cdf8edf6fa719ba89f37e6138c33834 Mon Sep 17 00:00:00 2001
-From: Tim Harvey <tharvey at gateworks.com>
-Date: Tue, 21 Nov 2023 11:44:38 -0800
-Subject: [PATCH 408/413] 6.9: arm64: dts: imx8mm-venice-gw7901: add TPM device
-
-Add the TPM device found on the GW7901 revision D PCB.
-
-Signed-off-by: Tim Harvey <tharvey at gateworks.com>
----
- arch/arm64/boot/dts/freescale/imx8mm-venice-gw7901.dts | 10 +++++++++-
- 1 file changed, 9 insertions(+), 1 deletion(-)
-
---- a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7901.dts
-+++ b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7901.dts
-@@ -285,7 +285,8 @@
- &ecspi1 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_spi1>;
-- cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>;
-+ cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>,
-+ <&gpio4 24 GPIO_ACTIVE_LOW>;
- status = "okay";
-
- flash at 0 {
-@@ -294,6 +295,12 @@
- spi-max-frequency = <40000000>;
- status = "okay";
- };
-+
-+ tpm at 1 {
-+ compatible = "tcg,tpm_tis-spi";
-+ reg = <0x1>;
-+ spi-max-frequency = <36000000>;
-+ };
- };
-
- &fec1 {
-@@ -989,6 +996,7 @@
- MX8MM_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x82
- MX8MM_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x82
- MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x140
-+ MX8MM_IOMUXC_SAI2_TXFS_GPIO4_IO24 0x140
- >;
- };
-
diff --git a/target/linux/imx/patches-6.12/409-6.9-arm64-dts-freescale-imx8mp-venice-gw72xx-2x-fix-.patch b/target/linux/imx/patches-6.12/409-6.9-arm64-dts-freescale-imx8mp-venice-gw72xx-2x-fix-.patch
deleted file mode 100644
index 2c63d7c339..0000000000
--- a/target/linux/imx/patches-6.12/409-6.9-arm64-dts-freescale-imx8mp-venice-gw72xx-2x-fix-.patch
+++ /dev/null
@@ -1,38 +0,0 @@
-From fddb089c2ccfb8bc4bd3aba605f7eadfd9f36cfd Mon Sep 17 00:00:00 2001
-From: Tim Harvey <tharvey at gateworks.com>
-Date: Wed, 28 Feb 2024 10:22:11 -0800
-Subject: [PATCH 409/413] 6.9: arm64: dts: freescale: imx8mp-venice-gw72xx-2x:
- fix USB vbus regulator
-
-When using usb-conn-gpio to control USB role and VBUS, the vbus-supply
-property must be present in the usb-conn-gpio node. Additionally it
-should not be present in the phy node as that isn't what controls vbus
-and will upset the use count.
-
-This resolves an issue where VBUS is enabled with OTG in peripheral
-mode.
-
-Fixes: 86c43ae03ab9 ("arm64: dts: freescale: Add imx8mp-venice-gw72xx-2x")
-Signed-off-by: Tim Harvey <tharvey at gateworks.com>
----
- arch/arm64/boot/dts/freescale/imx8mp-venice-gw72xx.dtsi | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
---- a/arch/arm64/boot/dts/freescale/imx8mp-venice-gw72xx.dtsi
-+++ b/arch/arm64/boot/dts/freescale/imx8mp-venice-gw72xx.dtsi
-@@ -169,7 +169,6 @@
- };
-
- &usb3_phy0 {
-- vbus-supply = <®_usb1_vbus>;
- status = "okay";
- };
-
-@@ -189,6 +188,7 @@
- pinctrl-0 = <&pinctrl_usbcon1>;
- type = "micro";
- label = "otg";
-+ vbus-supply = <®_usb1_vbus>;
- id-gpios = <&gpio3 21 GPIO_ACTIVE_HIGH>;
- };
- };
diff --git a/target/linux/imx/patches-6.12/410-6.9-arm64-dts-freescale-imx8mp-venice-gw73xx-2x-fix-.patch b/target/linux/imx/patches-6.12/410-6.9-arm64-dts-freescale-imx8mp-venice-gw73xx-2x-fix-.patch
deleted file mode 100644
index 53851b9d1b..0000000000
--- a/target/linux/imx/patches-6.12/410-6.9-arm64-dts-freescale-imx8mp-venice-gw73xx-2x-fix-.patch
+++ /dev/null
@@ -1,38 +0,0 @@
-From 69e3ce6d0c2f518bf9574112f3d4cc619c38602c Mon Sep 17 00:00:00 2001
-From: Tim Harvey <tharvey at gateworks.com>
-Date: Wed, 28 Feb 2024 10:24:19 -0800
-Subject: [PATCH 410/413] 6.9: arm64: dts: freescale: imx8mp-venice-gw73xx-2x:
- fix USB vbus regulator
-
-When using usb-conn-gpio to control USB role and VBUS, the vbus-supply
-property must be present in the usb-conn-gpio node. Additionally it
-should not be present in the phy node as that isn't what controls vbus
-and will upset the use count.
-
-This resolves an issue where VBUS is enabled with OTG in peripheral
-mode.
-
-Fixes: 716ced308234 ("arm64: dts: freescale: Add imx8mp-venice-gw73xx-2x")
-Signed-off-by: Tim Harvey <tharvey at gateworks.com>
----
- arch/arm64/boot/dts/freescale/imx8mp-venice-gw73xx.dtsi | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
---- a/arch/arm64/boot/dts/freescale/imx8mp-venice-gw73xx.dtsi
-+++ b/arch/arm64/boot/dts/freescale/imx8mp-venice-gw73xx.dtsi
-@@ -188,7 +188,6 @@
- };
-
- &usb3_phy0 {
-- vbus-supply = <®_usb1_vbus>;
- status = "okay";
- };
-
-@@ -208,6 +207,7 @@
- pinctrl-0 = <&pinctrl_usbcon1>;
- type = "micro";
- label = "otg";
-+ vbus-supply = <®_usb1_vbus>;
- id-gpios = <&gpio3 21 GPIO_ACTIVE_HIGH>;
- };
- };
diff --git a/target/linux/imx/patches-6.12/411-6.10-arm64-dts-imx8mp-venice-gw74xx-add-ADC-rail-for.patch b/target/linux/imx/patches-6.12/411-6.10-arm64-dts-imx8mp-venice-gw74xx-add-ADC-rail-for.patch
deleted file mode 100644
index afebad1748..0000000000
--- a/target/linux/imx/patches-6.12/411-6.10-arm64-dts-imx8mp-venice-gw74xx-add-ADC-rail-for.patch
+++ /dev/null
@@ -1,30 +0,0 @@
-From 9d75bdd797d32c859d0dd9f54acc30de63831eb1 Mon Sep 17 00:00:00 2001
-From: Tim Harvey <tharvey at gateworks.com>
-Date: Mon, 29 Jan 2024 15:28:39 -0800
-Subject: [PATCH 411/413] 6.10: arm64: dts: imx8mp-venice-gw74xx: add ADC rail
- for VDD_1P0
-
-The imx8mp-venice-gw74xx revB PCB added an ADC rail for
-VDD_1P0. Add it to the GSC ADC rails.
-
-Fixes: 531936b218d8 ("arm64: dts: imx8mp-venice-gw74xx: update to revB PCB")
-Signed-off-by: Tim Harvey <tharvey at gateworks.com>
----
- arch/arm64/boot/dts/freescale/imx8mp-venice-gw74xx.dts | 6 ++++++
- 1 file changed, 6 insertions(+)
-
---- a/arch/arm64/boot/dts/freescale/imx8mp-venice-gw74xx.dts
-+++ b/arch/arm64/boot/dts/freescale/imx8mp-venice-gw74xx.dts
-@@ -391,6 +391,12 @@
- label = "vdd_dram";
- };
-
-+ channel at 9e {
-+ gw,mode = <2>;
-+ reg = <0x9e>;
-+ label = "vdd_1p0";
-+ };
-+
- channel at a2 {
- gw,mode = <2>;
- reg = <0xa2>;
diff --git a/target/linux/imx/patches-6.12/412-6.10-arm64-dts-imx8mp-venice-gw72xx-add-mac-addr-for.patch b/target/linux/imx/patches-6.12/412-6.10-arm64-dts-imx8mp-venice-gw72xx-add-mac-addr-for.patch
deleted file mode 100644
index 567571c15e..0000000000
--- a/target/linux/imx/patches-6.12/412-6.10-arm64-dts-imx8mp-venice-gw72xx-add-mac-addr-for.patch
+++ /dev/null
@@ -1,80 +0,0 @@
-From 482fe0cb90d3376051304531a01edccac9ca1868 Mon Sep 17 00:00:00 2001
-From: Tim Harvey <tharvey at gateworks.com>
-Date: Thu, 29 Feb 2024 10:05:26 -0800
-Subject: [PATCH 412/413] 6.10: arm64: dts: imx8mp-venice-gw72xx: add mac addr
- for eth1
-
-Add the PCI bus topology for eth1 so that boot firmware can set the
-local-mac-address property.
-
-The eth1 device is behind a PCI switch:
- # lspci -n
- 00:00.0 0604: 16c3:abcd (rev 01)
- 01:00.0 0604: 12d8:b404 (rev 01)
- 02:01.0 0604: 12d8:b404 (rev 01)
- 02:02.0 0604: 12d8:b404 (rev 01)
- 02:03.0 0604: 12d8:b404 (rev 01)
- 05:00.0 0200: 11ab:4380
- # lspci -t
- -[0000:00]---00.0-[01-ff]----00.0-[02-05]--+-01.0-[03]--
- +-02.0-[04]--
- \-03.0-[05]----00.0
-
-Signed-off-by: Tim Harvey <tharvey at gateworks.com>
----
- .../dts/freescale/imx8mp-venice-gw72xx.dtsi | 37 +++++++++++++++++++
- 1 file changed, 37 insertions(+)
-
---- a/arch/arm64/boot/dts/freescale/imx8mp-venice-gw72xx.dtsi
-+++ b/arch/arm64/boot/dts/freescale/imx8mp-venice-gw72xx.dtsi
-@@ -8,6 +8,10 @@
- #include <dt-bindings/phy/phy-imx8-pcie.h>
-
- / {
-+ aliases {
-+ ethernet1 = ð1;
-+ };
-+
- led-controller {
- compatible = "gpio-leds";
- pinctrl-names = "default";
-@@ -137,6 +141,39 @@
- pinctrl-0 = <&pinctrl_pcie0>;
- reset-gpio = <&gpio4 29 GPIO_ACTIVE_LOW>;
- status = "okay";
-+
-+ pcie at 0,0 {
-+ reg = <0x0000 0 0 0 0>;
-+ device_type = "pci";
-+ #address-cells = <3>;
-+ #size-cells = <2>;
-+ ranges;
-+
-+ pcie at 0,0 {
-+ reg = <0x0000 0 0 0 0>;
-+ device_type = "pci";
-+ #address-cells = <3>;
-+ #size-cells = <2>;
-+ ranges;
-+
-+ pcie at 3,0 {
-+ reg = <0x1800 0 0 0 0>;
-+ device_type = "pci";
-+ #address-cells = <3>;
-+ #size-cells = <2>;
-+ ranges;
-+
-+ eth1: ethernet at 0,0 {
-+ reg = <0x0000 0 0 0 0>;
-+ #address-cells = <3>;
-+ #size-cells = <2>;
-+ ranges;
-+
-+ local-mac-address = [00 00 00 00 00 00];
-+ };
-+ };
-+ };
-+ };
- };
-
- /* GPS */
diff --git a/target/linux/imx/patches-6.12/413-6.10-arm64-dts-imx8mp-venice-gw73xx-add-mac-addr-for.patch b/target/linux/imx/patches-6.12/413-6.10-arm64-dts-imx8mp-venice-gw73xx-add-mac-addr-for.patch
deleted file mode 100644
index faf9373ec3..0000000000
--- a/target/linux/imx/patches-6.12/413-6.10-arm64-dts-imx8mp-venice-gw73xx-add-mac-addr-for.patch
+++ /dev/null
@@ -1,82 +0,0 @@
-From caac9b614ee63f875b290fda429706f6ef36e2f1 Mon Sep 17 00:00:00 2001
-From: Tim Harvey <tharvey at gateworks.com>
-Date: Thu, 29 Feb 2024 10:12:49 -0800
-Subject: [PATCH 413/413] 6.10: arm64: dts: imx8mp-venice-gw73xx: add mac addr
- for eth1
-
-Add the PCI bus topology for eth1 so that boot firmware can set the
-local-mac-address property.
-
-The eth1 device is behind a PCI switch:
- # lspci -n
- 00:00.0 0604: 16c3:abcd (rev 01)
- 01:00.0 0604: 12d8:2608
- 02:01.0 0604: 12d8:2608
- 02:02.0 0604: 12d8:2608
- 02:03.0 0604: 12d8:2608
- 02:04.0 0604: 12d8:2608
- c0:00.0 0200: 1055:7430 (rev 11)
- # lspci -t
- -[0000:00]---00.0-[01-ff]----00.0-[02-fe]--+-01.0-[03-41]--
- +-02.0-[42-80]--
- +-03.0-[81-bf]--
- \-04.0-[c0-fe]----00.0
-
-Signed-off-by: Tim Harvey <tharvey at gateworks.com>
----
- .../dts/freescale/imx8mp-venice-gw73xx.dtsi | 37 +++++++++++++++++++
- 1 file changed, 37 insertions(+)
-
---- a/arch/arm64/boot/dts/freescale/imx8mp-venice-gw73xx.dtsi
-+++ b/arch/arm64/boot/dts/freescale/imx8mp-venice-gw73xx.dtsi
-@@ -8,6 +8,10 @@
- #include <dt-bindings/phy/phy-imx8-pcie.h>
-
- / {
-+ aliases {
-+ ethernet1 = ð1;
-+ };
-+
- led-controller {
- compatible = "gpio-leds";
- pinctrl-names = "default";
-@@ -149,6 +153,39 @@
- pinctrl-0 = <&pinctrl_pcie0>;
- reset-gpio = <&gpio4 29 GPIO_ACTIVE_LOW>;
- status = "okay";
-+
-+ pcie at 0,0 {
-+ reg = <0x0000 0 0 0 0>;
-+ device_type = "pci";
-+ #address-cells = <3>;
-+ #size-cells = <2>;
-+ ranges;
-+
-+ pcie at 0,0 {
-+ reg = <0x0000 0 0 0 0>;
-+ device_type = "pci";
-+ #address-cells = <3>;
-+ #size-cells = <2>;
-+ ranges;
-+
-+ pcie at 4,0 {
-+ reg = <0x2000 0 0 0 0>;
-+ device_type = "pci";
-+ #address-cells = <3>;
-+ #size-cells = <2>;
-+ ranges;
-+
-+ eth1: ethernet at 0,0 {
-+ reg = <0x0000 0 0 0 0>;
-+ #address-cells = <3>;
-+ #size-cells = <2>;
-+ ranges;
-+
-+ local-mac-address = [00 00 00 00 00 00];
-+ };
-+ };
-+ };
-+ };
- };
-
- /* GPS */
diff --git a/target/linux/imx/patches-6.12/500-6.13-arm64-dts-imx8mm-venice-add-RTC-aliases.patch b/target/linux/imx/patches-6.12/500-6.13-arm64-dts-imx8mm-venice-add-RTC-aliases.patch
index 2d398defc4..f69fea0c89 100644
--- a/target/linux/imx/patches-6.12/500-6.13-arm64-dts-imx8mm-venice-add-RTC-aliases.patch
+++ b/target/linux/imx/patches-6.12/500-6.13-arm64-dts-imx8mm-venice-add-RTC-aliases.patch
@@ -23,7 +23,7 @@ Signed-off-by: Shawn Guo <shawnguo at kernel.org>
--- a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw700x.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw700x.dtsi
-@@ -8,6 +8,11 @@
+@@ -9,6 +9,11 @@
#include <dt-bindings/net/ti-dp83867.h>
/ {
@@ -35,7 +35,7 @@ Signed-off-by: Shawn Guo <shawnguo at kernel.org>
memory at 40000000 {
device_type = "memory";
reg = <0x0 0x40000000 0 0x80000000>;
-@@ -272,7 +277,7 @@
+@@ -292,7 +297,7 @@
pagesize = <16>;
};
@@ -55,7 +55,7 @@ Signed-off-by: Shawn Guo <shawnguo at kernel.org>
usb0 = &usbotg1;
usb1 = &usbotg2;
};
-@@ -495,7 +497,7 @@
+@@ -497,7 +499,7 @@
pagesize = <16>;
};
@@ -75,7 +75,7 @@ Signed-off-by: Shawn Guo <shawnguo at kernel.org>
usb0 = &usbotg1;
usb1 = &usbotg2;
};
-@@ -562,7 +564,7 @@
+@@ -564,7 +566,7 @@
pagesize = <16>;
};
@@ -95,7 +95,7 @@ Signed-off-by: Shawn Guo <shawnguo at kernel.org>
usb0 = &usbotg1;
};
-@@ -392,7 +394,7 @@
+@@ -394,7 +396,7 @@
pagesize = <16>;
};
@@ -118,7 +118,7 @@ Signed-off-by: Shawn Guo <shawnguo at kernel.org>
chosen {
stdout-path = &uart2;
};
-@@ -436,7 +441,7 @@
+@@ -438,7 +443,7 @@
pagesize = <16>;
};
@@ -138,7 +138,7 @@ Signed-off-by: Shawn Guo <shawnguo at kernel.org>
usb0 = &usbotg1;
};
-@@ -560,7 +562,7 @@
+@@ -562,7 +564,7 @@
pagesize = <16>;
};
@@ -149,7 +149,7 @@ Signed-off-by: Shawn Guo <shawnguo at kernel.org>
};
--- a/arch/arm64/boot/dts/freescale/imx8mp-venice-gw702x.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mp-venice-gw702x.dtsi
-@@ -10,6 +10,8 @@
+@@ -11,6 +11,8 @@
/ {
aliases {
ethernet0 = &eqos;
@@ -158,7 +158,7 @@ Signed-off-by: Shawn Guo <shawnguo at kernel.org>
};
memory at 40000000 {
-@@ -260,7 +262,7 @@
+@@ -280,7 +282,7 @@
pagesize = <16>;
};
@@ -169,7 +169,7 @@ Signed-off-by: Shawn Guo <shawnguo at kernel.org>
};
--- a/arch/arm64/boot/dts/freescale/imx8mp-venice-gw74xx.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mp-venice-gw74xx.dts
-@@ -24,6 +24,8 @@
+@@ -25,6 +25,8 @@
ethernet4 = &lan3;
ethernet5 = &lan4;
ethernet6 = &lan5;
@@ -178,7 +178,7 @@ Signed-off-by: Shawn Guo <shawnguo at kernel.org>
};
chosen {
-@@ -444,7 +446,7 @@
+@@ -481,7 +483,7 @@
pagesize = <16>;
};
diff --git a/target/linux/imx/patches-6.12/501-6.13-arm64-dts-imx8mp-venice-gw74xx-add-M2SKT_GPIO10-gpio.patch b/target/linux/imx/patches-6.12/501-6.13-arm64-dts-imx8mp-venice-gw74xx-add-M2SKT_GPIO10-gpio.patch
index 14c8f88e31..dea37cd748 100644
--- a/target/linux/imx/patches-6.12/501-6.13-arm64-dts-imx8mp-venice-gw74xx-add-M2SKT_GPIO10-gpio.patch
+++ b/target/linux/imx/patches-6.12/501-6.13-arm64-dts-imx8mp-venice-gw74xx-add-M2SKT_GPIO10-gpio.patch
@@ -17,7 +17,7 @@ Signed-off-by: Shawn Guo <shawnguo at kernel.org>
--- a/arch/arm64/boot/dts/freescale/imx8mp-venice-gw74xx.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mp-venice-gw74xx.dts
-@@ -264,7 +264,7 @@
+@@ -301,7 +301,7 @@
&gpio3 {
gpio-line-names =
"", "", "", "", "", "", "m2_rst", "",
@@ -26,7 +26,7 @@ Signed-off-by: Shawn Guo <shawnguo at kernel.org>
"", "", "", "", "", "", "", "",
"", "", "", "", "", "", "", "";
};
-@@ -786,6 +786,7 @@
+@@ -818,6 +818,7 @@
MX8MP_IOMUXC_SD2_CMD__GPIO2_IO14 0x40000150 /* PCIE3_WDIS# */
MX8MP_IOMUXC_SD2_DATA3__GPIO2_IO18 0x40000150 /* PCIE2_WDIS# */
MX8MP_IOMUXC_NAND_DATA00__GPIO3_IO06 0x40000040 /* M2SKT_RST# */
diff --git a/target/linux/imx/patches-6.12/502-6.13-arm64-dts-freescale-rename-gw7905-to-gw75xx.patch b/target/linux/imx/patches-6.12/502-6.13-arm64-dts-freescale-rename-gw7905-to-gw75xx.patch
deleted file mode 100644
index 056b85002e..0000000000
--- a/target/linux/imx/patches-6.12/502-6.13-arm64-dts-freescale-rename-gw7905-to-gw75xx.patch
+++ /dev/null
@@ -1,1426 +0,0 @@
-From 14c3de96e14b30b1b83016abe607034a5a7e1c6b Mon Sep 17 00:00:00 2001
-From: Tim Harvey <tharvey at gateworks.com>
-Date: Wed, 24 Jan 2024 10:16:03 -0800
-Subject: [PATCH] arm64: dts: freescale: rename gw7905 to gw75xx
-
-The GW7905 was renamed to GW7500 before production release.
-
-Signed-off-by: Tim Harvey <tharvey at gateworks.com>
----
- Documentation/devicetree/bindings/arm/fsl.yaml | 4 ++--
- arch/arm64/boot/dts/freescale/Makefile | 4 ++--
- ...8mm-venice-gw7905-0x.dts => imx8mm-venice-gw75xx-0x.dts} | 6 +++---
- ...{imx8mm-venice-gw7905.dtsi => imx8mm-venice-gw75xx.dtsi} | 0
- ...8mp-venice-gw7905-2x.dts => imx8mp-venice-gw75xx-2x.dts} | 6 +++---
- ...{imx8mp-venice-gw7905.dtsi => imx8mp-venice-gw75xx.dtsi} | 0
- 6 files changed, 10 insertions(+), 10 deletions(-)
- rename arch/arm64/boot/dts/freescale/{imx8mm-venice-gw7905-0x.dts => imx8mm-venice-gw75xx-0x.dts} (67%)
- rename arch/arm64/boot/dts/freescale/{imx8mm-venice-gw7905.dtsi => imx8mm-venice-gw75xx.dtsi} (100%)
- rename arch/arm64/boot/dts/freescale/{imx8mp-venice-gw7905-2x.dts => imx8mp-venice-gw75xx-2x.dts} (67%)
- rename arch/arm64/boot/dts/freescale/{imx8mp-venice-gw7905.dtsi => imx8mp-venice-gw75xx.dtsi} (100%)
-
---- a/Documentation/devicetree/bindings/arm/fsl.yaml
-+++ b/Documentation/devicetree/bindings/arm/fsl.yaml
-@@ -908,8 +908,8 @@ properties:
- - fsl,imx8mm-ddr4-evk # i.MX8MM DDR4 EVK Board
- - fsl,imx8mm-evk # i.MX8MM EVK Board
- - fsl,imx8mm-evkb # i.MX8MM EVKB Board
-+ - gateworks,imx8mm-gw75xx-0x # i.MX8MM Gateworks Board
- - gateworks,imx8mm-gw7904
-- - gateworks,imx8mm-gw7905-0x # i.MX8MM Gateworks Board
- - gw,imx8mm-gw71xx-0x # i.MX8MM Gateworks Development Kit
- - gw,imx8mm-gw72xx-0x # i.MX8MM Gateworks Development Kit
- - gw,imx8mm-gw73xx-0x # i.MX8MM Gateworks Development Kit
-@@ -1036,7 +1036,7 @@ properties:
- - gateworks,imx8mp-gw72xx-2x # i.MX8MP Gateworks Board
- - gateworks,imx8mp-gw73xx-2x # i.MX8MP Gateworks Board
- - gateworks,imx8mp-gw74xx # i.MX8MP Gateworks Board
-- - gateworks,imx8mp-gw7905-2x # i.MX8MP Gateworks Board
-+ - gateworks,imx8mp-gw75xx-2x # i.MX8MP Gateworks Board
- - toradex,verdin-imx8mp # Verdin iMX8M Plus Modules
- - toradex,verdin-imx8mp-nonwifi # Verdin iMX8M Plus Modules without Wi-Fi / BT
- - toradex,verdin-imx8mp-wifi # Verdin iMX8M Plus Wi-Fi / BT Modules
---- a/arch/arm64/boot/dts/freescale/Makefile
-+++ b/arch/arm64/boot/dts/freescale/Makefile
-@@ -72,11 +72,11 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mm-var-som
- dtb-$(CONFIG_ARCH_MXC) += imx8mm-venice-gw71xx-0x.dtb
- dtb-$(CONFIG_ARCH_MXC) += imx8mm-venice-gw72xx-0x.dtb
- dtb-$(CONFIG_ARCH_MXC) += imx8mm-venice-gw73xx-0x.dtb
-+dtb-$(CONFIG_ARCH_MXC) += imx8mm-venice-gw75xx-0x.dtb
- dtb-$(CONFIG_ARCH_MXC) += imx8mm-venice-gw7901.dtb
- dtb-$(CONFIG_ARCH_MXC) += imx8mm-venice-gw7902.dtb
- dtb-$(CONFIG_ARCH_MXC) += imx8mm-venice-gw7903.dtb
- dtb-$(CONFIG_ARCH_MXC) += imx8mm-venice-gw7904.dtb
--dtb-$(CONFIG_ARCH_MXC) += imx8mm-venice-gw7905-0x.dtb
- dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-nonwifi-dahlia.dtb
- dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-nonwifi-dev.dtb
- dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-nonwifi-yavia.dtb
-@@ -107,7 +107,7 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mp-venice-
- dtb-$(CONFIG_ARCH_MXC) += imx8mp-venice-gw72xx-2x.dtb
- dtb-$(CONFIG_ARCH_MXC) += imx8mp-venice-gw73xx-2x.dtb
- dtb-$(CONFIG_ARCH_MXC) += imx8mp-venice-gw74xx.dtb
--dtb-$(CONFIG_ARCH_MXC) += imx8mp-venice-gw7905-2x.dtb
-+dtb-$(CONFIG_ARCH_MXC) += imx8mp-venice-gw75xx-2x.dtb
- dtb-$(CONFIG_ARCH_MXC) += imx8mp-verdin-nonwifi-dahlia.dtb
- dtb-$(CONFIG_ARCH_MXC) += imx8mp-verdin-nonwifi-dev.dtb
- dtb-$(CONFIG_ARCH_MXC) += imx8mp-verdin-nonwifi-yavia.dtb
---- a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7905-0x.dts
-+++ /dev/null
-@@ -1,28 +0,0 @@
--// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
--/*
-- * Copyright 2023 Gateworks Corporation
-- */
--
--/dts-v1/;
--
--#include "imx8mm.dtsi"
--#include "imx8mm-venice-gw700x.dtsi"
--#include "imx8mm-venice-gw7905.dtsi"
--
--/ {
-- model = "Gateworks Venice GW7905-0x i.MX8MM Development Kit";
-- compatible = "gateworks,imx8mm-gw7905-0x", "fsl,imx8mm";
--
-- chosen {
-- stdout-path = &uart2;
-- };
--};
--
--/* Disable SOM interfaces not used on baseboard */
--&fec1 {
-- status = "disabled";
--};
--
--&usdhc1 {
-- status = "disabled";
--};
---- /dev/null
-+++ b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw75xx-0x.dts
-@@ -0,0 +1,28 @@
-+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-+/*
-+ * Copyright 2023 Gateworks Corporation
-+ */
-+
-+/dts-v1/;
-+
-+#include "imx8mm.dtsi"
-+#include "imx8mm-venice-gw700x.dtsi"
-+#include "imx8mm-venice-gw75xx.dtsi"
-+
-+/ {
-+ model = "Gateworks Venice GW75xx-0x i.MX8MM Development Kit";
-+ compatible = "gateworks,imx8mm-gw75xx-0x", "fsl,imx8mm";
-+
-+ chosen {
-+ stdout-path = &uart2;
-+ };
-+};
-+
-+/* Disable SOM interfaces not used on baseboard */
-+&fec1 {
-+ status = "disabled";
-+};
-+
-+&usdhc1 {
-+ status = "disabled";
-+};
---- a/arch/arm64/boot/dts/freescale/imx8mp-venice-gw7905-2x.dts
-+++ /dev/null
-@@ -1,28 +0,0 @@
--// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
--/*
-- * Copyright 2023 Gateworks Corporation
-- */
--
--/dts-v1/;
--
--#include "imx8mp.dtsi"
--#include "imx8mp-venice-gw702x.dtsi"
--#include "imx8mp-venice-gw7905.dtsi"
--
--/ {
-- model = "Gateworks Venice GW7905-2x i.MX8MP Development Kit";
-- compatible = "gateworks,imx8mp-gw7905-2x", "fsl,imx8mp";
--
-- chosen {
-- stdout-path = &uart2;
-- };
--};
--
--/* Disable SOM interfaces not used on baseboard */
--&eqos {
-- status = "disabled";
--};
--
--&usdhc1 {
-- status = "disabled";
--};
---- /dev/null
-+++ b/arch/arm64/boot/dts/freescale/imx8mp-venice-gw75xx-2x.dts
-@@ -0,0 +1,28 @@
-+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-+/*
-+ * Copyright 2023 Gateworks Corporation
-+ */
-+
-+/dts-v1/;
-+
-+#include "imx8mp.dtsi"
-+#include "imx8mp-venice-gw702x.dtsi"
-+#include "imx8mp-venice-gw75xx.dtsi"
-+
-+/ {
-+ model = "Gateworks Venice GW75xx-2x i.MX8MP Development Kit";
-+ compatible = "gateworks,imx8mp-gw75xx-2x", "fsl,imx8mp";
-+
-+ chosen {
-+ stdout-path = &uart2;
-+ };
-+};
-+
-+/* Disable SOM interfaces not used on baseboard */
-+&eqos {
-+ status = "disabled";
-+};
-+
-+&usdhc1 {
-+ status = "disabled";
-+};
---- /dev/null
-+++ b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw75xx.dtsi
-@@ -0,0 +1,303 @@
-+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-+/*
-+ * Copyright 2023 Gateworks Corporation
-+ */
-+
-+#include <dt-bindings/gpio/gpio.h>
-+#include <dt-bindings/leds/common.h>
-+#include <dt-bindings/phy/phy-imx8-pcie.h>
-+
-+/ {
-+ led-controller {
-+ compatible = "gpio-leds";
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&pinctrl_gpio_leds>;
-+
-+ led-0 {
-+ function = LED_FUNCTION_STATUS;
-+ color = <LED_COLOR_ID_GREEN>;
-+ gpios = <&gpio4 0 GPIO_ACTIVE_HIGH>;
-+ default-state = "on";
-+ linux,default-trigger = "heartbeat";
-+ };
-+
-+ led-1 {
-+ function = LED_FUNCTION_STATUS;
-+ color = <LED_COLOR_ID_RED>;
-+ gpios = <&gpio4 2 GPIO_ACTIVE_HIGH>;
-+ default-state = "off";
-+ };
-+ };
-+
-+ pcie0_refclk: clock-pcie0 {
-+ compatible = "fixed-clock";
-+ #clock-cells = <0>;
-+ clock-frequency = <100000000>;
-+ };
-+
-+ pps {
-+ compatible = "pps-gpio";
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&pinctrl_pps>;
-+ gpios = <&gpio4 5 GPIO_ACTIVE_HIGH>;
-+ status = "okay";
-+ };
-+
-+ reg_usb2_vbus: regulator-usb2-vbus {
-+ compatible = "regulator-fixed";
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&pinctrl_reg_usb2_en>;
-+ regulator-name = "usb2_vbus";
-+ gpio = <&gpio1 8 GPIO_ACTIVE_HIGH>;
-+ enable-active-high;
-+ regulator-min-microvolt = <5000000>;
-+ regulator-max-microvolt = <5000000>;
-+ };
-+
-+ reg_usdhc2_vmmc: regulator-usdhc2 {
-+ compatible = "regulator-fixed";
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
-+ regulator-name = "SD2_3P3V";
-+ regulator-min-microvolt = <3300000>;
-+ regulator-max-microvolt = <3300000>;
-+ gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
-+ enable-active-high;
-+ };
-+};
-+
-+/* off-board header */
-+&ecspi2 {
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&pinctrl_spi2>;
-+ cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;
-+ status = "okay";
-+};
-+
-+&gpio1 {
-+ gpio-line-names =
-+ "", "", "", "",
-+ "", "", "", "",
-+ "", "", "", "",
-+ "", "gpioa", "gpiob", "",
-+ "", "", "", "",
-+ "", "", "", "",
-+ "", "", "", "",
-+ "", "", "", "";
-+};
-+
-+&gpio4 {
-+ gpio-line-names =
-+ "", "", "", "pci_usb_sel",
-+ "", "", "", "pci_wdis#",
-+ "", "", "", "",
-+ "", "", "", "",
-+ "", "", "", "",
-+ "", "", "", "",
-+ "", "", "", "",
-+ "", "", "", "";
-+};
-+
-+&gpio5 {
-+ gpio-line-names =
-+ "", "", "", "",
-+ "gpioc", "gpiod", "", "",
-+ "", "", "", "",
-+ "", "", "", "",
-+ "", "", "", "",
-+ "", "", "", "",
-+ "", "", "", "",
-+ "", "", "", "";
-+};
-+
-+&i2c2 {
-+ clock-frequency = <400000>;
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&pinctrl_i2c2>;
-+ status = "okay";
-+
-+ eeprom at 52 {
-+ compatible = "atmel,24c32";
-+ reg = <0x52>;
-+ pagesize = <32>;
-+ };
-+};
-+
-+/* off-board header */
-+&i2c3 {
-+ clock-frequency = <400000>;
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&pinctrl_i2c3>;
-+ status = "okay";
-+};
-+
-+&pcie_phy {
-+ fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>;
-+ fsl,clkreq-unsupported;
-+ clocks = <&pcie0_refclk>;
-+ clock-names = "ref";
-+ status = "okay";
-+};
-+
-+&pcie0 {
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&pinctrl_pcie0>;
-+ reset-gpio = <&gpio4 6 GPIO_ACTIVE_LOW>;
-+ status = "okay";
-+};
-+
-+/* GPS */
-+&uart1 {
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&pinctrl_uart1>;
-+ status = "okay";
-+};
-+
-+/* USB1 - Type C front panel SINK port J14 */
-+&usbotg1 {
-+ dr_mode = "peripheral";
-+ status = "okay";
-+};
-+
-+/* USB2 4-port USB3.0 HUB:
-+ * P1 - USBC connector (host only)
-+ * P2 - USB2 test connector
-+ * P3 - miniPCIe full card
-+ * P4 - miniPCIe half card
-+ */
-+&usbotg2 {
-+ dr_mode = "host";
-+ vbus-supply = <®_usb2_vbus>;
-+ status = "okay";
-+};
-+
-+/* microSD */
-+&usdhc2 {
-+ pinctrl-names = "default", "state_100mhz", "state_200mhz";
-+ pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
-+ pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
-+ pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
-+ cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
-+ vmmc-supply = <®_usdhc2_vmmc>;
-+ bus-width = <4>;
-+ status = "okay";
-+};
-+
-+&iomuxc {
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&pinctrl_hog>;
-+
-+ pinctrl_hog: hoggrp {
-+ fsl,pins = <
-+ MX8MM_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x40000040 /* GPIOA */
-+ MX8MM_IOMUXC_GPIO1_IO14_GPIO1_IO14 0x40000040 /* GPIOB */
-+ MX8MM_IOMUXC_SAI1_RXD1_GPIO4_IO3 0x40000106 /* PCI_USBSEL */
-+ MX8MM_IOMUXC_SAI1_RXD5_GPIO4_IO7 0x40000106 /* PCIE_WDIS# */
-+ MX8MM_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5 0x40000040 /* GPIOD */
-+ MX8MM_IOMUXC_SPDIF_RX_GPIO5_IO4 0x40000040 /* GPIOC */
-+ >;
-+ };
-+
-+ pinctrl_gpio_leds: gpioledgrp {
-+ fsl,pins = <
-+ MX8MM_IOMUXC_SAI1_RXFS_GPIO4_IO0 0x6 /* LEDG */
-+ MX8MM_IOMUXC_SAI1_RXD0_GPIO4_IO2 0x6 /* LEDR */
-+ >;
-+ };
-+
-+ pinctrl_i2c2: i2c2grp {
-+ fsl,pins = <
-+ MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c2
-+ MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c2
-+ >;
-+ };
-+
-+ pinctrl_i2c3: i2c3grp {
-+ fsl,pins = <
-+ MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c2
-+ MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c2
-+ >;
-+ };
-+
-+ pinctrl_pcie0: pciegrp {
-+ fsl,pins = <
-+ MX8MM_IOMUXC_SAI1_RXD4_GPIO4_IO6 0x106
-+ >;
-+ };
-+
-+ pinctrl_pps: ppsgrp {
-+ fsl,pins = <
-+ MX8MM_IOMUXC_SAI1_RXD3_GPIO4_IO5 0x106
-+ >;
-+ };
-+
-+ pinctrl_reg_usb2_en: regusb2grp {
-+ fsl,pins = <
-+ MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x6 /* USBHUB_RST# (ext p/u) */
-+ >;
-+ };
-+
-+ pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
-+ fsl,pins = <
-+ MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x40
-+ >;
-+ };
-+
-+ pinctrl_spi2: spi2grp {
-+ fsl,pins = <
-+ MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x140
-+ MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x140
-+ MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x140
-+ MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x140
-+ >;
-+ };
-+
-+ pinctrl_uart1: uart1grp {
-+ fsl,pins = <
-+ MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX 0x140
-+ MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX 0x140
-+ >;
-+ };
-+
-+ pinctrl_usdhc2: usdhc2grp {
-+ fsl,pins = <
-+ MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190
-+ MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0
-+ MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0
-+ MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0
-+ MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0
-+ MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0
-+ MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc0
-+ >;
-+ };
-+
-+ pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
-+ fsl,pins = <
-+ MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194
-+ MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4
-+ MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4
-+ MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4
-+ MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4
-+ MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4
-+ MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc0
-+ >;
-+ };
-+
-+ pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
-+ fsl,pins = <
-+ MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196
-+ MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6
-+ MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6
-+ MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6
-+ MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6
-+ MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6
-+ MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc0
-+ >;
-+ };
-+
-+ pinctrl_usdhc2_gpio: usdhc2gpiogrp {
-+ fsl,pins = <
-+ MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x1c4
-+ >;
-+ };
-+};
---- a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7905.dtsi
-+++ /dev/null
-@@ -1,303 +0,0 @@
--// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
--/*
-- * Copyright 2023 Gateworks Corporation
-- */
--
--#include <dt-bindings/gpio/gpio.h>
--#include <dt-bindings/leds/common.h>
--#include <dt-bindings/phy/phy-imx8-pcie.h>
--
--/ {
-- led-controller {
-- compatible = "gpio-leds";
-- pinctrl-names = "default";
-- pinctrl-0 = <&pinctrl_gpio_leds>;
--
-- led-0 {
-- function = LED_FUNCTION_STATUS;
-- color = <LED_COLOR_ID_GREEN>;
-- gpios = <&gpio4 0 GPIO_ACTIVE_HIGH>;
-- default-state = "on";
-- linux,default-trigger = "heartbeat";
-- };
--
-- led-1 {
-- function = LED_FUNCTION_STATUS;
-- color = <LED_COLOR_ID_RED>;
-- gpios = <&gpio4 2 GPIO_ACTIVE_HIGH>;
-- default-state = "off";
-- };
-- };
--
-- pcie0_refclk: clock-pcie0 {
-- compatible = "fixed-clock";
-- #clock-cells = <0>;
-- clock-frequency = <100000000>;
-- };
--
-- pps {
-- compatible = "pps-gpio";
-- pinctrl-names = "default";
-- pinctrl-0 = <&pinctrl_pps>;
-- gpios = <&gpio4 5 GPIO_ACTIVE_HIGH>;
-- status = "okay";
-- };
--
-- reg_usb2_vbus: regulator-usb2-vbus {
-- compatible = "regulator-fixed";
-- pinctrl-names = "default";
-- pinctrl-0 = <&pinctrl_reg_usb2_en>;
-- regulator-name = "usb2_vbus";
-- gpio = <&gpio1 8 GPIO_ACTIVE_HIGH>;
-- enable-active-high;
-- regulator-min-microvolt = <5000000>;
-- regulator-max-microvolt = <5000000>;
-- };
--
-- reg_usdhc2_vmmc: regulator-usdhc2 {
-- compatible = "regulator-fixed";
-- pinctrl-names = "default";
-- pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
-- regulator-name = "SD2_3P3V";
-- regulator-min-microvolt = <3300000>;
-- regulator-max-microvolt = <3300000>;
-- gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
-- enable-active-high;
-- };
--};
--
--/* off-board header */
--&ecspi2 {
-- pinctrl-names = "default";
-- pinctrl-0 = <&pinctrl_spi2>;
-- cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;
-- status = "okay";
--};
--
--&gpio1 {
-- gpio-line-names =
-- "", "", "", "",
-- "", "", "", "",
-- "", "", "", "",
-- "", "gpioa", "gpiob", "",
-- "", "", "", "",
-- "", "", "", "",
-- "", "", "", "",
-- "", "", "", "";
--};
--
--&gpio4 {
-- gpio-line-names =
-- "", "", "", "pci_usb_sel",
-- "", "", "", "pci_wdis#",
-- "", "", "", "",
-- "", "", "", "",
-- "", "", "", "",
-- "", "", "", "",
-- "", "", "", "",
-- "", "", "", "";
--};
--
--&gpio5 {
-- gpio-line-names =
-- "", "", "", "",
-- "gpioc", "gpiod", "", "",
-- "", "", "", "",
-- "", "", "", "",
-- "", "", "", "",
-- "", "", "", "",
-- "", "", "", "",
-- "", "", "", "";
--};
--
--&i2c2 {
-- clock-frequency = <400000>;
-- pinctrl-names = "default";
-- pinctrl-0 = <&pinctrl_i2c2>;
-- status = "okay";
--
-- eeprom at 52 {
-- compatible = "atmel,24c32";
-- reg = <0x52>;
-- pagesize = <32>;
-- };
--};
--
--/* off-board header */
--&i2c3 {
-- clock-frequency = <400000>;
-- pinctrl-names = "default";
-- pinctrl-0 = <&pinctrl_i2c3>;
-- status = "okay";
--};
--
--&pcie_phy {
-- fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>;
-- fsl,clkreq-unsupported;
-- clocks = <&pcie0_refclk>;
-- clock-names = "ref";
-- status = "okay";
--};
--
--&pcie0 {
-- pinctrl-names = "default";
-- pinctrl-0 = <&pinctrl_pcie0>;
-- reset-gpio = <&gpio4 6 GPIO_ACTIVE_LOW>;
-- status = "okay";
--};
--
--/* GPS */
--&uart1 {
-- pinctrl-names = "default";
-- pinctrl-0 = <&pinctrl_uart1>;
-- status = "okay";
--};
--
--/* USB1 - Type C front panel SINK port J14 */
--&usbotg1 {
-- dr_mode = "peripheral";
-- status = "okay";
--};
--
--/* USB2 4-port USB3.0 HUB:
-- * P1 - USBC connector (host only)
-- * P2 - USB2 test connector
-- * P3 - miniPCIe full card
-- * P4 - miniPCIe half card
-- */
--&usbotg2 {
-- dr_mode = "host";
-- vbus-supply = <®_usb2_vbus>;
-- status = "okay";
--};
--
--/* microSD */
--&usdhc2 {
-- pinctrl-names = "default", "state_100mhz", "state_200mhz";
-- pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
-- pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
-- pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
-- cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
-- vmmc-supply = <®_usdhc2_vmmc>;
-- bus-width = <4>;
-- status = "okay";
--};
--
--&iomuxc {
-- pinctrl-names = "default";
-- pinctrl-0 = <&pinctrl_hog>;
--
-- pinctrl_hog: hoggrp {
-- fsl,pins = <
-- MX8MM_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x40000040 /* GPIOA */
-- MX8MM_IOMUXC_GPIO1_IO14_GPIO1_IO14 0x40000040 /* GPIOB */
-- MX8MM_IOMUXC_SAI1_RXD1_GPIO4_IO3 0x40000106 /* PCI_USBSEL */
-- MX8MM_IOMUXC_SAI1_RXD5_GPIO4_IO7 0x40000106 /* PCIE_WDIS# */
-- MX8MM_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5 0x40000040 /* GPIOD */
-- MX8MM_IOMUXC_SPDIF_RX_GPIO5_IO4 0x40000040 /* GPIOC */
-- >;
-- };
--
-- pinctrl_gpio_leds: gpioledgrp {
-- fsl,pins = <
-- MX8MM_IOMUXC_SAI1_RXFS_GPIO4_IO0 0x6 /* LEDG */
-- MX8MM_IOMUXC_SAI1_RXD0_GPIO4_IO2 0x6 /* LEDR */
-- >;
-- };
--
-- pinctrl_i2c2: i2c2grp {
-- fsl,pins = <
-- MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c2
-- MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c2
-- >;
-- };
--
-- pinctrl_i2c3: i2c3grp {
-- fsl,pins = <
-- MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c2
-- MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c2
-- >;
-- };
--
-- pinctrl_pcie0: pciegrp {
-- fsl,pins = <
-- MX8MM_IOMUXC_SAI1_RXD4_GPIO4_IO6 0x106
-- >;
-- };
--
-- pinctrl_pps: ppsgrp {
-- fsl,pins = <
-- MX8MM_IOMUXC_SAI1_RXD3_GPIO4_IO5 0x106
-- >;
-- };
--
-- pinctrl_reg_usb2_en: regusb2grp {
-- fsl,pins = <
-- MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x6 /* USBHUB_RST# (ext p/u) */
-- >;
-- };
--
-- pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
-- fsl,pins = <
-- MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x40
-- >;
-- };
--
-- pinctrl_spi2: spi2grp {
-- fsl,pins = <
-- MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x140
-- MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x140
-- MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x140
-- MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x140
-- >;
-- };
--
-- pinctrl_uart1: uart1grp {
-- fsl,pins = <
-- MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX 0x140
-- MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX 0x140
-- >;
-- };
--
-- pinctrl_usdhc2: usdhc2grp {
-- fsl,pins = <
-- MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190
-- MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0
-- MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0
-- MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0
-- MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0
-- MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0
-- MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc0
-- >;
-- };
--
-- pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
-- fsl,pins = <
-- MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194
-- MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4
-- MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4
-- MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4
-- MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4
-- MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4
-- MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc0
-- >;
-- };
--
-- pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
-- fsl,pins = <
-- MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196
-- MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6
-- MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6
-- MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6
-- MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6
-- MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6
-- MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc0
-- >;
-- };
--
-- pinctrl_usdhc2_gpio: usdhc2gpiogrp {
-- fsl,pins = <
-- MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x1c4
-- >;
-- };
--};
---- /dev/null
-+++ b/arch/arm64/boot/dts/freescale/imx8mp-venice-gw75xx.dtsi
-@@ -0,0 +1,309 @@
-+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-+/*
-+ * Copyright 2023 Gateworks Corporation
-+ */
-+
-+#include <dt-bindings/gpio/gpio.h>
-+#include <dt-bindings/leds/common.h>
-+#include <dt-bindings/phy/phy-imx8-pcie.h>
-+
-+/ {
-+ led-controller {
-+ compatible = "gpio-leds";
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&pinctrl_gpio_leds>;
-+
-+ led-0 {
-+ function = LED_FUNCTION_STATUS;
-+ color = <LED_COLOR_ID_GREEN>;
-+ gpios = <&gpio4 22 GPIO_ACTIVE_HIGH>;
-+ default-state = "on";
-+ linux,default-trigger = "heartbeat";
-+ };
-+
-+ led-1 {
-+ function = LED_FUNCTION_STATUS;
-+ color = <LED_COLOR_ID_RED>;
-+ gpios = <&gpio4 27 GPIO_ACTIVE_HIGH>;
-+ default-state = "off";
-+ };
-+ };
-+
-+ pcie0_refclk: pcie0-refclk {
-+ compatible = "fixed-clock";
-+ #clock-cells = <0>;
-+ clock-frequency = <100000000>;
-+ };
-+
-+ pps {
-+ compatible = "pps-gpio";
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&pinctrl_pps>;
-+ gpios = <&gpio4 21 GPIO_ACTIVE_HIGH>;
-+ status = "okay";
-+ };
-+
-+ reg_usb2_vbus: regulator-usb2-vbus {
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&pinctrl_reg_usb2_en>;
-+ compatible = "regulator-fixed";
-+ regulator-name = "usb2_vbus";
-+ gpio = <&gpio4 12 GPIO_ACTIVE_HIGH>;
-+ enable-active-high;
-+ regulator-min-microvolt = <5000000>;
-+ regulator-max-microvolt = <5000000>;
-+ };
-+
-+ reg_usdhc2_vmmc: regulator-usdhc2 {
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
-+ compatible = "regulator-fixed";
-+ regulator-name = "SD2_3P3V";
-+ regulator-min-microvolt = <3300000>;
-+ regulator-max-microvolt = <3300000>;
-+ gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
-+ enable-active-high;
-+ };
-+};
-+
-+/* off-board header */
-+&ecspi2 {
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&pinctrl_spi2>;
-+ cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;
-+ status = "okay";
-+};
-+
-+&gpio4 {
-+ gpio-line-names =
-+ "", "", "", "",
-+ "", "", "", "",
-+ "", "", "", "",
-+ "", "gpioa", "", "",
-+ "", "", "", "",
-+ "", "", "", "",
-+ "", "", "", "",
-+ "", "", "", "";
-+};
-+
-+&gpio4 {
-+ gpio-line-names =
-+ "", "gpiod", "", "",
-+ "gpiob", "gpioc", "", "",
-+ "", "", "", "",
-+ "", "", "", "",
-+ "", "", "", "",
-+ "", "", "", "",
-+ "", "", "pci_usb_sel", "",
-+ "pci_wdis#", "", "", "";
-+};
-+
-+&i2c2 {
-+ clock-frequency = <400000>;
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&pinctrl_i2c2>;
-+ status = "okay";
-+
-+ eeprom at 52 {
-+ compatible = "atmel,24c32";
-+ reg = <0x52>;
-+ pagesize = <32>;
-+ };
-+};
-+
-+/* off-board header */
-+&i2c3 {
-+ clock-frequency = <400000>;
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&pinctrl_i2c3>;
-+ status = "okay";
-+};
-+
-+&pcie_phy {
-+ fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>;
-+ fsl,clkreq-unsupported;
-+ clocks = <&pcie0_refclk>;
-+ clock-names = "ref";
-+ status = "okay";
-+};
-+
-+&pcie {
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&pinctrl_pcie0>;
-+ reset-gpio = <&gpio4 29 GPIO_ACTIVE_LOW>;
-+ status = "okay";
-+};
-+
-+/* GPS */
-+&uart1 {
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&pinctrl_uart1>;
-+ status = "okay";
-+};
-+
-+/* USB1 - Type C front panel SINK port J14 */
-+&usb3_0 {
-+ status = "okay";
-+};
-+
-+&usb3_phy0 {
-+ status = "okay";
-+};
-+
-+&usb_dwc3_0 {
-+ dr_mode = "peripheral";
-+ status = "okay";
-+};
-+
-+/* USB2 4-port USB3.0 HUB:
-+ * P1 - USBC connector (host only)
-+ * P2 - USB2 test connector
-+ * P3 - miniPCIe full card
-+ * P4 - miniPCIe half card
-+ */
-+&usb3_phy1 {
-+ vbus-supply = <®_usb2_vbus>;
-+ status = "okay";
-+};
-+
-+&usb3_1 {
-+ fsl,permanently-attached;
-+ fsl,disable-port-power-control;
-+ status = "okay";
-+};
-+
-+&usb_dwc3_1 {
-+ dr_mode = "host";
-+ status = "okay";
-+};
-+
-+/* microSD */
-+&usdhc2 {
-+ pinctrl-names = "default", "state_100mhz", "state_200mhz";
-+ pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
-+ pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
-+ pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
-+ cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
-+ vmmc-supply = <®_usdhc2_vmmc>;
-+ bus-width = <4>;
-+ status = "okay";
-+};
-+
-+&iomuxc {
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&pinctrl_hog>;
-+
-+ pinctrl_hog: hoggrp {
-+ fsl,pins = <
-+ MX8MP_IOMUXC_GPIO1_IO13__GPIO1_IO13 0x40000040 /* GPIOA */
-+ MX8MP_IOMUXC_SAI1_RXC__GPIO4_IO01 0x40000040 /* GPIOD */
-+ MX8MP_IOMUXC_SAI1_RXD2__GPIO4_IO04 0x40000040 /* GPIOB */
-+ MX8MP_IOMUXC_SAI1_RXD3__GPIO4_IO05 0x40000040 /* GPIOC */
-+ MX8MP_IOMUXC_SAI2_TXD0__GPIO4_IO26 0x40000106 /* PCI_USBSEL */
-+ MX8MP_IOMUXC_SAI3_RXFS__GPIO4_IO28 0x40000106 /* PCI_WDIS# */
-+ >;
-+ };
-+
-+ pinctrl_gpio_leds: gpioledgrp {
-+ fsl,pins = <
-+ MX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22 0x6 /* LEDG */
-+ MX8MP_IOMUXC_SAI2_MCLK__GPIO4_IO27 0x6 /* LEDR */
-+ >;
-+ };
-+
-+ pinctrl_i2c2: i2c2grp {
-+ fsl,pins = <
-+ MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001c2
-+ MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x400001c2
-+ >;
-+ };
-+
-+ pinctrl_i2c3: i2c3grp {
-+ fsl,pins = <
-+ MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x400001c2
-+ MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x400001c2
-+ >;
-+ };
-+
-+ pinctrl_pcie0: pciegrp {
-+ fsl,pins = <
-+ MX8MP_IOMUXC_SAI3_RXC__GPIO4_IO29 0x106
-+ >;
-+ };
-+
-+ pinctrl_pps: ppsgrp {
-+ fsl,pins = <
-+ MX8MP_IOMUXC_SAI2_RXFS__GPIO4_IO21 0x106
-+ >;
-+ };
-+
-+ pinctrl_reg_usb2_en: regusb2grp {
-+ fsl,pins = <
-+ MX8MP_IOMUXC_SAI1_TXD0__GPIO4_IO12 0x6 /* USBHUB_RST# (ext p/u) */
-+ >;
-+ };
-+
-+ pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
-+ fsl,pins = <
-+ MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x40
-+ >;
-+ };
-+
-+ pinctrl_spi2: spi2grp {
-+ fsl,pins = <
-+ MX8MP_IOMUXC_ECSPI2_SCLK__ECSPI2_SCLK 0x140
-+ MX8MP_IOMUXC_ECSPI2_MOSI__ECSPI2_MOSI 0x140
-+ MX8MP_IOMUXC_ECSPI2_MISO__ECSPI2_MISO 0x140
-+ MX8MP_IOMUXC_ECSPI2_SS0__GPIO5_IO13 0x140
-+ >;
-+ };
-+
-+ pinctrl_uart1: uart1grp {
-+ fsl,pins = <
-+ MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX 0x140
-+ MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX 0x140
-+ >;
-+ };
-+
-+ pinctrl_usdhc2: usdhc2grp {
-+ fsl,pins = <
-+ MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190
-+ MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d0
-+ MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d0
-+ MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0
-+ MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0
-+ MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0
-+ MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0
-+ >;
-+ };
-+
-+ pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
-+ fsl,pins = <
-+ MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194
-+ MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4
-+ MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4
-+ MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4
-+ MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4
-+ MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4
-+ MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0
-+ >;
-+ };
-+
-+ pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
-+ fsl,pins = <
-+ MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x196
-+ MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d6
-+ MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d6
-+ MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6
-+ MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6
-+ MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6
-+ MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0
-+ >;
-+ };
-+
-+ pinctrl_usdhc2_gpio: usdhc2gpiogrp {
-+ fsl,pins = <
-+ MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x1c4
-+ >;
-+ };
-+};
---- a/arch/arm64/boot/dts/freescale/imx8mp-venice-gw7905.dtsi
-+++ /dev/null
-@@ -1,309 +0,0 @@
--// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
--/*
-- * Copyright 2023 Gateworks Corporation
-- */
--
--#include <dt-bindings/gpio/gpio.h>
--#include <dt-bindings/leds/common.h>
--#include <dt-bindings/phy/phy-imx8-pcie.h>
--
--/ {
-- led-controller {
-- compatible = "gpio-leds";
-- pinctrl-names = "default";
-- pinctrl-0 = <&pinctrl_gpio_leds>;
--
-- led-0 {
-- function = LED_FUNCTION_STATUS;
-- color = <LED_COLOR_ID_GREEN>;
-- gpios = <&gpio4 22 GPIO_ACTIVE_HIGH>;
-- default-state = "on";
-- linux,default-trigger = "heartbeat";
-- };
--
-- led-1 {
-- function = LED_FUNCTION_STATUS;
-- color = <LED_COLOR_ID_RED>;
-- gpios = <&gpio4 27 GPIO_ACTIVE_HIGH>;
-- default-state = "off";
-- };
-- };
--
-- pcie0_refclk: pcie0-refclk {
-- compatible = "fixed-clock";
-- #clock-cells = <0>;
-- clock-frequency = <100000000>;
-- };
--
-- pps {
-- compatible = "pps-gpio";
-- pinctrl-names = "default";
-- pinctrl-0 = <&pinctrl_pps>;
-- gpios = <&gpio4 21 GPIO_ACTIVE_HIGH>;
-- status = "okay";
-- };
--
-- reg_usb2_vbus: regulator-usb2-vbus {
-- pinctrl-names = "default";
-- pinctrl-0 = <&pinctrl_reg_usb2_en>;
-- compatible = "regulator-fixed";
-- regulator-name = "usb2_vbus";
-- gpio = <&gpio4 12 GPIO_ACTIVE_HIGH>;
-- enable-active-high;
-- regulator-min-microvolt = <5000000>;
-- regulator-max-microvolt = <5000000>;
-- };
--
-- reg_usdhc2_vmmc: regulator-usdhc2 {
-- pinctrl-names = "default";
-- pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
-- compatible = "regulator-fixed";
-- regulator-name = "SD2_3P3V";
-- regulator-min-microvolt = <3300000>;
-- regulator-max-microvolt = <3300000>;
-- gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
-- enable-active-high;
-- };
--};
--
--/* off-board header */
--&ecspi2 {
-- pinctrl-names = "default";
-- pinctrl-0 = <&pinctrl_spi2>;
-- cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;
-- status = "okay";
--};
--
--&gpio4 {
-- gpio-line-names =
-- "", "", "", "",
-- "", "", "", "",
-- "", "", "", "",
-- "", "gpioa", "", "",
-- "", "", "", "",
-- "", "", "", "",
-- "", "", "", "",
-- "", "", "", "";
--};
--
--&gpio4 {
-- gpio-line-names =
-- "", "gpiod", "", "",
-- "gpiob", "gpioc", "", "",
-- "", "", "", "",
-- "", "", "", "",
-- "", "", "", "",
-- "", "", "", "",
-- "", "", "pci_usb_sel", "",
-- "pci_wdis#", "", "", "";
--};
--
--&i2c2 {
-- clock-frequency = <400000>;
-- pinctrl-names = "default";
-- pinctrl-0 = <&pinctrl_i2c2>;
-- status = "okay";
--
-- eeprom at 52 {
-- compatible = "atmel,24c32";
-- reg = <0x52>;
-- pagesize = <32>;
-- };
--};
--
--/* off-board header */
--&i2c3 {
-- clock-frequency = <400000>;
-- pinctrl-names = "default";
-- pinctrl-0 = <&pinctrl_i2c3>;
-- status = "okay";
--};
--
--&pcie_phy {
-- fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>;
-- fsl,clkreq-unsupported;
-- clocks = <&pcie0_refclk>;
-- clock-names = "ref";
-- status = "okay";
--};
--
--&pcie {
-- pinctrl-names = "default";
-- pinctrl-0 = <&pinctrl_pcie0>;
-- reset-gpio = <&gpio4 29 GPIO_ACTIVE_LOW>;
-- status = "okay";
--};
--
--/* GPS */
--&uart1 {
-- pinctrl-names = "default";
-- pinctrl-0 = <&pinctrl_uart1>;
-- status = "okay";
--};
--
--/* USB1 - Type C front panel SINK port J14 */
--&usb3_0 {
-- status = "okay";
--};
--
--&usb3_phy0 {
-- status = "okay";
--};
--
--&usb_dwc3_0 {
-- dr_mode = "peripheral";
-- status = "okay";
--};
--
--/* USB2 4-port USB3.0 HUB:
-- * P1 - USBC connector (host only)
-- * P2 - USB2 test connector
-- * P3 - miniPCIe full card
-- * P4 - miniPCIe half card
-- */
--&usb3_phy1 {
-- vbus-supply = <®_usb2_vbus>;
-- status = "okay";
--};
--
--&usb3_1 {
-- fsl,permanently-attached;
-- fsl,disable-port-power-control;
-- status = "okay";
--};
--
--&usb_dwc3_1 {
-- dr_mode = "host";
-- status = "okay";
--};
--
--/* microSD */
--&usdhc2 {
-- pinctrl-names = "default", "state_100mhz", "state_200mhz";
-- pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
-- pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
-- pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
-- cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
-- vmmc-supply = <®_usdhc2_vmmc>;
-- bus-width = <4>;
-- status = "okay";
--};
--
--&iomuxc {
-- pinctrl-names = "default";
-- pinctrl-0 = <&pinctrl_hog>;
--
-- pinctrl_hog: hoggrp {
-- fsl,pins = <
-- MX8MP_IOMUXC_GPIO1_IO13__GPIO1_IO13 0x40000040 /* GPIOA */
-- MX8MP_IOMUXC_SAI1_RXC__GPIO4_IO01 0x40000040 /* GPIOD */
-- MX8MP_IOMUXC_SAI1_RXD2__GPIO4_IO04 0x40000040 /* GPIOB */
-- MX8MP_IOMUXC_SAI1_RXD3__GPIO4_IO05 0x40000040 /* GPIOC */
-- MX8MP_IOMUXC_SAI2_TXD0__GPIO4_IO26 0x40000106 /* PCI_USBSEL */
-- MX8MP_IOMUXC_SAI3_RXFS__GPIO4_IO28 0x40000106 /* PCI_WDIS# */
-- >;
-- };
--
-- pinctrl_gpio_leds: gpioledgrp {
-- fsl,pins = <
-- MX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22 0x6 /* LEDG */
-- MX8MP_IOMUXC_SAI2_MCLK__GPIO4_IO27 0x6 /* LEDR */
-- >;
-- };
--
-- pinctrl_i2c2: i2c2grp {
-- fsl,pins = <
-- MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001c2
-- MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x400001c2
-- >;
-- };
--
-- pinctrl_i2c3: i2c3grp {
-- fsl,pins = <
-- MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x400001c2
-- MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x400001c2
-- >;
-- };
--
-- pinctrl_pcie0: pciegrp {
-- fsl,pins = <
-- MX8MP_IOMUXC_SAI3_RXC__GPIO4_IO29 0x106
-- >;
-- };
--
-- pinctrl_pps: ppsgrp {
-- fsl,pins = <
-- MX8MP_IOMUXC_SAI2_RXFS__GPIO4_IO21 0x106
-- >;
-- };
--
-- pinctrl_reg_usb2_en: regusb2grp {
-- fsl,pins = <
-- MX8MP_IOMUXC_SAI1_TXD0__GPIO4_IO12 0x6 /* USBHUB_RST# (ext p/u) */
-- >;
-- };
--
-- pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
-- fsl,pins = <
-- MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x40
-- >;
-- };
--
-- pinctrl_spi2: spi2grp {
-- fsl,pins = <
-- MX8MP_IOMUXC_ECSPI2_SCLK__ECSPI2_SCLK 0x140
-- MX8MP_IOMUXC_ECSPI2_MOSI__ECSPI2_MOSI 0x140
-- MX8MP_IOMUXC_ECSPI2_MISO__ECSPI2_MISO 0x140
-- MX8MP_IOMUXC_ECSPI2_SS0__GPIO5_IO13 0x140
-- >;
-- };
--
-- pinctrl_uart1: uart1grp {
-- fsl,pins = <
-- MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX 0x140
-- MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX 0x140
-- >;
-- };
--
-- pinctrl_usdhc2: usdhc2grp {
-- fsl,pins = <
-- MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190
-- MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d0
-- MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d0
-- MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0
-- MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0
-- MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0
-- MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0
-- >;
-- };
--
-- pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
-- fsl,pins = <
-- MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194
-- MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4
-- MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4
-- MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4
-- MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4
-- MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4
-- MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0
-- >;
-- };
--
-- pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
-- fsl,pins = <
-- MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x196
-- MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d6
-- MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d6
-- MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6
-- MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6
-- MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6
-- MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0
-- >;
-- };
--
-- pinctrl_usdhc2_gpio: usdhc2gpiogrp {
-- fsl,pins = <
-- MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x1c4
-- >;
-- };
--};
diff --git a/target/linux/imx/patches-6.12/504-6.13-arm64-dts-imx-Add-i.MX8M-Plus-Gateworks-GW82XX-2X-support.patch b/target/linux/imx/patches-6.12/504-6.13-arm64-dts-imx-Add-i.MX8M-Plus-Gateworks-GW82XX-2X-support.patch
index 8765474a8a..85f9cc40e9 100644
--- a/target/linux/imx/patches-6.12/504-6.13-arm64-dts-imx-Add-i.MX8M-Plus-Gateworks-GW82XX-2X-support.patch
+++ b/target/linux/imx/patches-6.12/504-6.13-arm64-dts-imx-Add-i.MX8M-Plus-Gateworks-GW82XX-2X-support.patch
@@ -1,11 +1,11 @@
-From a79d2638a7150d1605fcadebb6baa36d27cdc48e Mon Sep 17 00:00:00 2001
+From 71dbcebc0a091cb2130b91a8ccce4bf734bbf6db Mon Sep 17 00:00:00 2001
From: Tim Harvey <tharvey at gateworks.com>
Date: Thu, 30 May 2024 10:21:45 -0700
Subject: [PATCH] arm64: dts: imx: Add i.MX8M Plus Gateworks GW82XX-2X support
The Gateworks GW82XX-2X is an ARM based single board computer (SBC)
-comprised of the i.MX8M Plus based gw702x SoM and the gw82xx
-baseboard featuring:
+comprised of the i.MX8M Plus based gw702x SoM and the gw82xx baseboard
+featuring:
- i.MX8M Plus SoC
- LPDDR4 DRAM
- eMMC FLASH
@@ -30,523 +30,30 @@ baseboard featuring:
Signed-off-by: Tim Harvey <tharvey at gateworks.com>
---
- .../devicetree/bindings/arm/fsl.yaml | 1 +
+v3:
+- use GPIO_ACTIVE_HIGH for regulator and remove unecessary comment
+v2:
+- remove invalid st,drdy-int-pin from LIS2MDL magnetometer
+- remove {adp,hnp,srp}-disable props from USB controller in host mode
+ (these are only applicable if the controller is in OTG/Peripheral mode)
+---
arch/arm64/boot/dts/freescale/Makefile | 1 +
- .../dts/freescale/imx8mm-venice-gw82xx.dtsi | 460 +++++++++++++++
- .../boot/dts/freescale/imx8mp-venice-gw82xx-2 | 19 +
.../dts/freescale/imx8mp-venice-gw82xx-2x.dts | 19 +
.../dts/freescale/imx8mp-venice-gw82xx.dtsi | 533 ++++++++++++++++++
- 6 files changed, 1033 insertions(+)
- create mode 100644 arch/arm64/boot/dts/freescale/imx8mm-venice-gw82xx.dtsi
- create mode 100644 arch/arm64/boot/dts/freescale/imx8mp-venice-gw82xx-2
+ 3 files changed, 553 insertions(+)
create mode 100644 arch/arm64/boot/dts/freescale/imx8mp-venice-gw82xx-2x.dts
create mode 100644 arch/arm64/boot/dts/freescale/imx8mp-venice-gw82xx.dtsi
---- a/Documentation/devicetree/bindings/arm/fsl.yaml
-+++ b/Documentation/devicetree/bindings/arm/fsl.yaml
-@@ -1037,6 +1037,7 @@ properties:
- - gateworks,imx8mp-gw73xx-2x # i.MX8MP Gateworks Board
- - gateworks,imx8mp-gw74xx # i.MX8MP Gateworks Board
- - gateworks,imx8mp-gw75xx-2x # i.MX8MP Gateworks Board
-+ - gateworks,imx8mp-gw82xx-2x # i.MX8MP Gateworks Board
- - toradex,verdin-imx8mp # Verdin iMX8M Plus Modules
- - toradex,verdin-imx8mp-nonwifi # Verdin iMX8M Plus Modules without Wi-Fi / BT
- - toradex,verdin-imx8mp-wifi # Verdin iMX8M Plus Wi-Fi / BT Modules
--- a/arch/arm64/boot/dts/freescale/Makefile
+++ b/arch/arm64/boot/dts/freescale/Makefile
-@@ -108,6 +108,7 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mp-venice-
+@@ -187,6 +187,7 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mp-venice-
dtb-$(CONFIG_ARCH_MXC) += imx8mp-venice-gw73xx-2x.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mp-venice-gw74xx.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mp-venice-gw75xx-2x.dtb
+dtb-$(CONFIG_ARCH_MXC) += imx8mp-venice-gw82xx-2x.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mp-verdin-nonwifi-dahlia.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mp-verdin-nonwifi-dev.dtb
- dtb-$(CONFIG_ARCH_MXC) += imx8mp-verdin-nonwifi-yavia.dtb
---- /dev/null
-+++ b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw82xx.dtsi
-@@ -0,0 +1,460 @@
-+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-+/*
-+ * Copyright 2020 Gateworks Corporation
-+ */
-+
-+#include <dt-bindings/gpio/gpio.h>
-+#include <dt-bindings/leds/common.h>
-+#include <dt-bindings/phy/phy-imx8-pcie.h>
-+
-+/ {
-+ aliases {
-+ ethernet1 = ð1;
-+ usb0 = &usbotg1;
-+ usb1 = &usbotg2;
-+ };
-+
-+ led-controller {
-+ compatible = "gpio-leds";
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&pinctrl_gpio_leds>;
-+
-+ led-0 {
-+ function = LED_FUNCTION_STATUS;
-+ color = <LED_COLOR_ID_GREEN>;
-+ gpios = <&gpio5 5 GPIO_ACTIVE_HIGH>;
-+ default-state = "on";
-+ linux,default-trigger = "heartbeat";
-+ };
-+
-+ led-1 {
-+ function = LED_FUNCTION_STATUS;
-+ color = <LED_COLOR_ID_RED>;
-+ gpios = <&gpio5 4 GPIO_ACTIVE_HIGH>;
-+ default-state = "off";
-+ };
-+ };
-+
-+ pcie0_refclk: pcie0-refclk {
-+ compatible = "fixed-clock";
-+ #clock-cells = <0>;
-+ clock-frequency = <100000000>;
-+ };
-+
-+ pps {
-+ compatible = "pps-gpio";
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&pinctrl_pps>;
-+ gpios = <&gpio1 15 GPIO_ACTIVE_HIGH>;
-+ status = "okay";
-+ };
-+
-+ reg_1p8v: regulator-1p8v {
-+ compatible = "regulator-fixed";
-+ regulator-name = "1P8V";
-+ regulator-min-microvolt = <1800000>;
-+ regulator-max-microvolt = <1800000>;
-+ regulator-always-on;
-+ };
-+
-+ reg_3p3v: regulator-3p3v {
-+ compatible = "regulator-fixed";
-+ regulator-name = "3P3V";
-+ regulator-min-microvolt = <3300000>;
-+ regulator-max-microvolt = <3300000>;
-+ regulator-always-on;
-+ };
-+
-+ reg_usb_otg1_vbus: regulator-usb-otg1 {
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&pinctrl_reg_usb1_en>;
-+ compatible = "regulator-fixed";
-+ regulator-name = "usb_otg1_vbus";
-+ gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>;
-+ enable-active-high;
-+ regulator-min-microvolt = <5000000>;
-+ regulator-max-microvolt = <5000000>;
-+ };
-+
-+ reg_usb_otg2_vbus: regulator-usb-otg2 {
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&pinctrl_reg_usb2_en>;
-+ compatible = "regulator-fixed";
-+ regulator-name = "usb_otg2_vbus";
-+ gpio = <&gpio1 8 GPIO_ACTIVE_HIGH>;
-+ enable-active-high;
-+ regulator-min-microvolt = <5000000>;
-+ regulator-max-microvolt = <5000000>;
-+ };
-+
-+ reg_wifi_en: regulator-wifi-en {
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&pinctrl_reg_wl>;
-+ compatible = "regulator-fixed";
-+ regulator-name = "wl";
-+ gpio = <&gpio1 5 GPIO_ACTIVE_HIGH>;
-+ startup-delay-us = <100>;
-+ enable-active-high;
-+ regulator-min-microvolt = <3300000>;
-+ regulator-max-microvolt = <3300000>;
-+ };
-+};
-+
-+/* off-board header */
-+&ecspi2 {
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&pinctrl_spi2>;
-+ cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>,
-+ <&gpio1 10 GPIO_ACTIVE_LOW>;
-+ status = "okay";
-+
-+ tpm at 1 {
-+ compatible = "atmel,attpm20p", "tcg,tpm_tis-spi";
-+ reg = <0x1>;
-+ spi-max-frequency = <36000000>;
-+ };
-+};
-+
-+&gpio1 {
-+ gpio-line-names = "rs485_term", "mipi_gpio4", "", "",
-+ "", "", "pci_usb_sel", "dio0",
-+ "", "dio1", "", "", "", "", "", "",
-+ "", "", "", "", "", "", "", "",
-+ "", "", "", "", "", "", "", "";
-+};
-+
-+&gpio4 {
-+ gpio-line-names = "rs485_en", "mipi_gpio3", "rs485_hd", "mipi_gpio2",
-+ "mipi_gpio1", "", "", "pci_wdis#",
-+ "", "", "", "", "", "", "", "",
-+ "", "", "", "", "", "", "", "",
-+ "", "", "", "", "", "", "", "";
-+};
-+
-+&i2c2 {
-+ clock-frequency = <400000>;
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&pinctrl_i2c2>;
-+ status = "okay";
-+
-+ accelerometer at 19 {
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&pinctrl_accel>;
-+ compatible = "st,lis2de12";
-+ reg = <0x19>;
-+ st,drdy-int-pin = <1>;
-+ interrupt-parent = <&gpio4>;
-+ interrupts = <5 IRQ_TYPE_LEVEL_LOW>;
-+ };
-+
-+ // TODO: 0x6f PCIe switch
-+};
-+
-+/* off-board header */
-+// TODO: i2c expander
-+&i2c3 {
-+ clock-frequency = <400000>;
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&pinctrl_i2c3>;
-+ status = "okay";
-+};
-+
-+&pcie_phy {
-+ fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>;
-+ fsl,clkreq-unsupported;
-+ clocks = <&pcie0_refclk>;
-+ clock-names = "ref";
-+ status = "okay";
-+};
-+
-+&pcie0 {
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&pinctrl_pcie0>;
-+ reset-gpio = <&gpio4 6 GPIO_ACTIVE_LOW>;
-+ clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&pcie0_refclk>,
-+ <&clk IMX8MM_CLK_PCIE1_AUX>;
-+ assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>,
-+ <&clk IMX8MM_CLK_PCIE1_CTRL>;
-+ assigned-clock-rates = <10000000>, <250000000>;
-+ assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>,
-+ <&clk IMX8MM_SYS_PLL2_250M>;
-+ status = "okay";
-+
-+ // TODO: this changes - new switch
-+ pcie at 0,0 {
-+ reg = <0x0000 0 0 0 0>;
-+ device_type = "pci";
-+ #address-cells = <3>;
-+ #size-cells = <2>;
-+ ranges;
-+
-+ pcie at 0,0 {
-+ reg = <0x0000 0 0 0 0>;
-+ device_type = "pci";
-+ #address-cells = <3>;
-+ #size-cells = <2>;
-+ ranges;
-+
-+ pcie at 4,0 {
-+ reg = <0x2000 0 0 0 0>;
-+ device_type = "pci";
-+ #address-cells = <3>;
-+ #size-cells = <2>;
-+ ranges;
-+
-+ eth1: ethernet at 0,0 {
-+ reg = <0x0000 0 0 0 0>;
-+ #address-cells = <3>;
-+ #size-cells = <2>;
-+ ranges;
-+
-+ local-mac-address = [00 00 00 00 00 00];
-+ };
-+ };
-+ };
-+ };
-+};
-+
-+/* off-board header */
-+&sai3 {
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&pinctrl_sai3>;
-+ assigned-clocks = <&clk IMX8MM_CLK_SAI3>;
-+ assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>;
-+ assigned-clock-rates = <24576000>;
-+ status = "okay";
-+};
-+
-+/* GPS */
-+&uart1 {
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&pinctrl_uart1>;
-+ status = "okay";
-+};
-+
-+/* bluetooth HCI */
-+&uart3 {
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&pinctrl_uart3>, <&pinctrl_bten>;
-+ cts-gpios = <&gpio5 8 GPIO_ACTIVE_LOW>;
-+ rts-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>;
-+ status = "okay";
-+
-+ bluetooth {
-+ compatible = "brcm,bcm4330-bt";
-+ shutdown-gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>;
-+ };
-+};
-+
-+/* RS232 */
-+&uart4 {
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&pinctrl_uart4>;
-+ status = "okay";
-+};
-+
-+&usbotg1 {
-+ dr_mode = "otg";
-+ over-current-active-low;
-+ vbus-supply = <®_usb_otg1_vbus>;
-+ status = "okay";
-+};
-+
-+&usbotg2 {
-+ dr_mode = "host";
-+ disable-over-current;
-+ vbus-supply = <®_usb_otg2_vbus>;
-+ status = "okay";
-+};
-+
-+/* SDIO WiFi */
-+&usdhc1 {
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&pinctrl_usdhc1>;
-+ bus-width = <4>;
-+ non-removable;
-+ vmmc-supply = <®_wifi_en>;
-+ status = "okay";
-+};
-+
-+/* microSD */
-+&usdhc2 {
-+ pinctrl-names = "default", "state_100mhz", "state_200mhz";
-+ pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
-+ pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
-+ pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
-+ cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
-+ bus-width = <4>;
-+ vmmc-supply = <®_3p3v>;
-+ status = "okay";
-+};
-+
-+&iomuxc {
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&pinctrl_hog>;
-+
-+ pinctrl_hog: hoggrp {
-+ fsl,pins = <
-+ MX8MM_IOMUXC_SPDIF_TX_GPIO5_IO3 0x40000041 /* PLUG_TEST */
-+ MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x40000041 /* PCI_USBSEL */
-+ MX8MM_IOMUXC_SAI1_RXD5_GPIO4_IO7 0x40000041 /* PCIE_WDIS# */
-+ MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x40000041 /* DIO0 */
-+ MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x40000041 /* DIO1 */
-+ MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x40000104 /* RS485_TERM */
-+ MX8MM_IOMUXC_SAI1_RXFS_GPIO4_IO0 0x40000104 /* RS485 */
-+ MX8MM_IOMUXC_SAI1_RXD0_GPIO4_IO2 0x40000104 /* RS485_HALF */
-+ >;
-+ };
-+
-+ pinctrl_accel: accelgrp {
-+ fsl,pins = <
-+ MX8MM_IOMUXC_SAI1_RXD3_GPIO4_IO5 0x159
-+ >;
-+ };
-+
-+ pinctrl_bten: btengrp {
-+ fsl,pins = <
-+ MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x41
-+ >;
-+ };
-+
-+ pinctrl_gpio_leds: gpioledgrp {
-+ fsl,pins = <
-+ MX8MM_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5 0x19
-+ MX8MM_IOMUXC_SPDIF_RX_GPIO5_IO4 0x19
-+ >;
-+ };
-+
-+ pinctrl_i2c3: i2c3grp {
-+ fsl,pins = <
-+ MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3
-+ MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3
-+ >;
-+ };
-+
-+ pinctrl_pcie0: pcie0grp {
-+ fsl,pins = <
-+ MX8MM_IOMUXC_SAI1_RXD4_GPIO4_IO6 0x41
-+ >;
-+ };
-+
-+ pinctrl_pps: ppsgrp {
-+ fsl,pins = <
-+ MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x41
-+ >;
-+ };
-+
-+ pinctrl_reg_wl: regwlgrp {
-+ fsl,pins = <
-+ MX8MM_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x41
-+ >;
-+ };
-+
-+ pinctrl_reg_usb1_en: regusb1grp {
-+ fsl,pins = <
-+ MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x41
-+ MX8MM_IOMUXC_GPIO1_IO13_USB1_OTG_OC 0x41
-+ >;
-+ };
-+
-+ pinctrl_reg_usb2_en: regusb2grp {
-+ fsl,pins = <
-+ MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x41
-+ >;
-+ };
-+
-+ pinctrl_sai3: sai3grp {
-+ fsl,pins = <
-+ MX8MM_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0xd6
-+ MX8MM_IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0xd6
-+ MX8MM_IOMUXC_SAI3_MCLK_SAI3_MCLK 0xd6
-+ MX8MM_IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0xd6
-+ MX8MM_IOMUXC_SAI3_RXD_SAI3_RX_DATA0 0xd6
-+ >;
-+ };
-+
-+ pinctrl_spi2: spi2grp {
-+ fsl,pins = <
-+ MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0xd6
-+ MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0xd6
-+ MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0xd6
-+ MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0xd6
-+ MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0xd6
-+ >;
-+ };
-+
-+ pinctrl_uart1: uart1grp {
-+ fsl,pins = <
-+ MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX 0x140
-+ MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX 0x140
-+ >;
-+ };
-+
-+ pinctrl_uart3: uart3grp {
-+ fsl,pins = <
-+ MX8MM_IOMUXC_UART3_RXD_UART3_DCE_RX 0x140
-+ MX8MM_IOMUXC_UART3_TXD_UART3_DCE_TX 0x140
-+ MX8MM_IOMUXC_ECSPI1_MISO_GPIO5_IO8 0x140
-+ MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x140
-+ >;
-+ };
-+
-+ pinctrl_uart4: uart4grp {
-+ fsl,pins = <
-+ MX8MM_IOMUXC_UART4_RXD_UART4_DCE_RX 0x140
-+ MX8MM_IOMUXC_UART4_TXD_UART4_DCE_TX 0x140
-+ >;
-+ };
-+
-+ pinctrl_usdhc1: usdhc1grp {
-+ fsl,pins = <
-+ MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x190
-+ MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d0
-+ MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d0
-+ MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d0
-+ MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d0
-+ MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d0
-+ >;
-+ };
-+
-+ pinctrl_usdhc2: usdhc2grp {
-+ fsl,pins = <
-+ MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190
-+ MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0
-+ MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0
-+ MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0
-+ MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0
-+ MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0
-+ >;
-+ };
-+
-+ pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
-+ fsl,pins = <
-+ MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194
-+ MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4
-+ MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4
-+ MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4
-+ MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4
-+ MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4
-+ >;
-+ };
-+
-+ pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
-+ fsl,pins = <
-+ MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196
-+ MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6
-+ MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6
-+ MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6
-+ MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6
-+ MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6
-+ >;
-+ };
-+
-+ pinctrl_usdhc2_gpio: usdhc2gpiogrp {
-+ fsl,pins = <
-+ MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x1c4
-+ MX8MM_IOMUXC_SD2_RESET_B_USDHC2_RESET_B 0x1d0
-+ MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
-+ >;
-+ };
-+};
---- /dev/null
-+++ b/arch/arm64/boot/dts/freescale/imx8mp-venice-gw82xx-2
-@@ -0,0 +1,19 @@
-+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-+/*
-+ * Copyright 2024 Gateworks Corporation
-+ */
-+
-+/dts-v1/;
-+
-+#include "imx8mm.dtsi"
-+#include "imx8mm-venice-gw700x.dtsi"
-+#include "imx8mm-venice-gw82xx.dtsi"
-+
-+/ {
-+ model = "Gateworks Venice GW82xx-0x i.MX8MM Development Kit";
-+ compatible = "gw,imx8mm-gw82xx-0x", "fsl,imx8mm";
-+
-+ chosen {
-+ stdout-path = &uart2;
-+ };
-+};
+ dtb-$(CONFIG_ARCH_MXC) += imx8mp-verdin-nonwifi-mallow.dtb
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8mp-venice-gw82xx-2x.dts
@@ -0,0 +1,19 @@
diff --git a/target/linux/imx/patches-6.12/600-PCI-imx6-Start-link-at-max-gen-first-for-IMX8MM-and-IMX8MP.patch b/target/linux/imx/patches-6.12/600-PCI-imx6-Start-link-at-max-gen-first-for-IMX8MM-and-IMX8MP.patch
deleted file mode 100644
index d8818369bc..0000000000
--- a/target/linux/imx/patches-6.12/600-PCI-imx6-Start-link-at-max-gen-first-for-IMX8MM-and-IMX8MP.patch
+++ /dev/null
@@ -1,121 +0,0 @@
-From cf983e4a04eecb5be93af7b53cb10805ee448998 Mon Sep 17 00:00:00 2001
-From: Tim Harvey <tharvey at gateworks.com>
-Date: Mon, 21 Aug 2023 09:20:17 -0700
-Subject: [PATCH] PCI: imx6: Start link at max gen first for IMX8MM and IMX8MP
-
-commit fa33a6d87eac ("PCI: imx6: Start link in Gen1 before negotiating
-for Gen2 mode") started link negotiation at Gen1 before attempting
-faster speeds in order to work around an issue with a particular switch
-on an IMX6Q SoC.
-
-This behavior is not the norm for PCI link negotiation and it has been
-found to cause issues in other cases:
-- IMX8MM with PI7C9X2G608GP switch: various endpoints (such as qca988x)
- will fail to link more than 50% of the time
-- IMX8MP with PI7C9X2G608GP switch: occasionally will fail to link with
- switch and cause a CPU hang about 30% of the time
-
-Disable this behavior for IMX8MM and IMX8MP.
-
-Signed-off-by: Tim Harvey <tharvey at gateworks.com>
----
- drivers/pci/controller/dwc/pci-imx6.c | 53 ++++++++++++++-------------
- 1 file changed, 27 insertions(+), 26 deletions(-)
-
---- a/drivers/pci/controller/dwc/pci-imx6.c
-+++ b/drivers/pci/controller/dwc/pci-imx6.c
-@@ -60,6 +60,7 @@ enum imx6_pcie_variants {
- #define IMX6_PCIE_FLAG_IMX6_PHY BIT(0)
- #define IMX6_PCIE_FLAG_IMX6_SPEED_CHANGE BIT(1)
- #define IMX6_PCIE_FLAG_SUPPORTS_SUSPEND BIT(2)
-+#define IMX6_PCIE_FLAG_GEN1_LAST BIT(3)
-
- #define IMX6_PCIE_MAX_CLKS 6
-
-@@ -836,26 +837,28 @@ static int imx6_pcie_start_link(struct d
- u32 tmp;
- int ret;
-
-- /*
-- * Force Gen1 operation when starting the link. In case the link is
-- * started in Gen2 mode, there is a possibility the devices on the
-- * bus will not be detected at all. This happens with PCIe switches.
-- */
-- dw_pcie_dbi_ro_wr_en(pci);
-- tmp = dw_pcie_readl_dbi(pci, offset + PCI_EXP_LNKCAP);
-- tmp &= ~PCI_EXP_LNKCAP_SLS;
-- tmp |= PCI_EXP_LNKCAP_SLS_2_5GB;
-- dw_pcie_writel_dbi(pci, offset + PCI_EXP_LNKCAP, tmp);
-- dw_pcie_dbi_ro_wr_dis(pci);
-+ if (!(imx6_pcie->drvdata->flags & IMX6_PCIE_FLAG_GEN1_LAST)) {
-+ /*
-+ * Force Gen1 operation when starting the link. In case the link is
-+ * started in Gen2 mode, there is a possibility the devices on the
-+ * bus will not be detected at all. This happens with PCIe switches.
-+ */
-+ dw_pcie_dbi_ro_wr_en(pci);
-+ tmp = dw_pcie_readl_dbi(pci, offset + PCI_EXP_LNKCAP);
-+ tmp &= ~PCI_EXP_LNKCAP_SLS;
-+ tmp |= PCI_EXP_LNKCAP_SLS_2_5GB;
-+ dw_pcie_writel_dbi(pci, offset + PCI_EXP_LNKCAP, tmp);
-+ dw_pcie_dbi_ro_wr_dis(pci);
-+ }
-
- /* Start LTSSM. */
- imx6_pcie_ltssm_enable(dev);
-
-- ret = dw_pcie_wait_for_link(pci);
-- if (ret)
-- goto err_reset_phy;
-+ if ((pci->link_gen > 1) && !(imx6_pcie->drvdata->flags & IMX6_PCIE_FLAG_GEN1_LAST)) {
-+ ret = dw_pcie_wait_for_link(pci);
-+ if (ret)
-+ goto err_reset_phy;
-
-- if (pci->link_gen > 1) {
- /* Allow faster modes after the link is up */
- dw_pcie_dbi_ro_wr_en(pci);
- tmp = dw_pcie_readl_dbi(pci, offset + PCI_EXP_LNKCAP);
-@@ -889,18 +892,14 @@ static int imx6_pcie_start_link(struct d
- goto err_reset_phy;
- }
- }
--
-- /* Make sure link training is finished as well! */
-- ret = dw_pcie_wait_for_link(pci);
-- if (ret)
-- goto err_reset_phy;
-- } else {
-- dev_info(dev, "Link: Only Gen1 is enabled\n");
- }
-
-+ ret = dw_pcie_wait_for_link(pci);
-+ if (ret)
-+ goto err_reset_phy;
-+
- imx6_pcie->link_is_up = true;
-- tmp = dw_pcie_readw_dbi(pci, offset + PCI_EXP_LNKSTA);
-- dev_info(dev, "Link up, Gen%i\n", tmp & PCI_EXP_LNKSTA_CLS);
-+
- return 0;
-
- err_reset_phy:
-@@ -1457,14 +1456,16 @@ static const struct imx6_pcie_drvdata dr
- },
- [IMX8MM] = {
- .variant = IMX8MM,
-- .flags = IMX6_PCIE_FLAG_SUPPORTS_SUSPEND,
-+ .flags = IMX6_PCIE_FLAG_SUPPORTS_SUSPEND |
-+ IMX6_PCIE_FLAG_GEN1_LAST,
- .gpr = "fsl,imx8mm-iomuxc-gpr",
- .clk_names = imx8mm_clks,
- .clks_cnt = ARRAY_SIZE(imx8mm_clks),
- },
- [IMX8MP] = {
- .variant = IMX8MP,
-- .flags = IMX6_PCIE_FLAG_SUPPORTS_SUSPEND,
-+ .flags = IMX6_PCIE_FLAG_SUPPORTS_SUSPEND |
-+ IMX6_PCIE_FLAG_GEN1_LAST,
- .gpr = "fsl,imx8mp-iomuxc-gpr",
- .clk_names = imx8mm_clks,
- .clks_cnt = ARRAY_SIZE(imx8mm_clks),
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