[openwrt/openwrt] mediatek: mt7622: fix SATA on BPi-R64

[LEDE Commits]

dangole pushed a commit to openwrt/openwrt.git, branch main:
https://git.openwrt.org/69890e16b37d59b55ba64633522c727f957cb2fd

commit 69890e16b37d59b55ba64633522c727f957cb2fd
Author: Daniel Golle <daniel at makrotopia.org>
AuthorDate: Sat Feb 1 05:03:50 2025 +0000

    mediatek: mt7622: fix SATA on BPi-R64
    
    Two commits which made their way into Linux stable broke the SATA
    support on the BPi-R64.
    
    Fix this by reverting a node rename which broke DT-overlay application
    and import a (still pending) patch re-adding the 'syscon' compatible to
    the pciesys clock-controller which also contains phy-mode bits
    referenced by the ahci_mtk driver expecting to access them using
    syscon_regmap_lookup_by_phandle().
    
    Signed-off-by: Daniel Golle <daniel at makrotopia.org>
---
 ...rt-arm64-dts-mediatek-fix-t-phy-unit-name.patch | 33 ++++++++++++++++++++++
 ...ediatek-mt7622-readd-syscon-to-pciesys-no.patch | 33 ++++++++++++++++++++++
 2 files changed, 66 insertions(+)

diff --git a/target/linux/mediatek/patches-6.6/115-Revert-arm64-dts-mediatek-fix-t-phy-unit-name.patch b/target/linux/mediatek/patches-6.6/115-Revert-arm64-dts-mediatek-fix-t-phy-unit-name.patch
new file mode 100644
index 0000000000..1d53cefd7f
--- /dev/null
+++ b/target/linux/mediatek/patches-6.6/115-Revert-arm64-dts-mediatek-fix-t-phy-unit-name.patch
@@ -0,0 +1,33 @@
+From 4c4baed29b168e9bf39545a945a9523ea280cb44 Mon Sep 17 00:00:00 2001
+From: Daniel Golle <daniel at makrotopia.org>
+Date: Sat, 1 Feb 2025 04:24:17 +0000
+Subject: [PATCH 1/2] Revert "arm64: dts: mediatek: fix t-phy unit name"
+
+This reverts commit 963c3b0c47ec29b4c49c9f45965cd066f419d17f.
+---
+ arch/arm64/boot/dts/mediatek/mt7622.dtsi  | 2 +-
+ arch/arm64/boot/dts/mediatek/mt7986a.dtsi | 2 +-
+ 2 files changed, 2 insertions(+), 2 deletions(-)
+
+--- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi
++++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi
+@@ -908,7 +908,7 @@
+ 		status = "disabled";
+ 	};
+ 
+-	sata_phy: t-phy {
++	sata_phy: t-phy at 1a243000 {
+ 		compatible = "mediatek,mt7622-tphy",
+ 			     "mediatek,generic-tphy-v1";
+ 		#address-cells = <2>;
+--- a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi
++++ b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi
+@@ -428,7 +428,7 @@
+ 			};
+ 		};
+ 
+-		pcie_phy: t-phy {
++		pcie_phy: t-phy at 11c00000 {
+ 			compatible = "mediatek,mt7986-tphy",
+ 				     "mediatek,generic-tphy-v2";
+ 			ranges;
diff --git a/target/linux/mediatek/patches-6.6/116-arm64-dts-mediatek-mt7622-readd-syscon-to-pciesys-no.patch b/target/linux/mediatek/patches-6.6/116-arm64-dts-mediatek-mt7622-readd-syscon-to-pciesys-no.patch
new file mode 100644
index 0000000000..4ae72fd70a
--- /dev/null
+++ b/target/linux/mediatek/patches-6.6/116-arm64-dts-mediatek-mt7622-readd-syscon-to-pciesys-no.patch
@@ -0,0 +1,33 @@
+From 98bc223d174c7f544e8f6c4f0caa8fa144f2f4dc Mon Sep 17 00:00:00 2001
+From: Christian Marangi <ansuelsmth at gmail.com>
+Date: Fri, 28 Jun 2024 12:55:40 +0200
+Subject: [PATCH 2/2] arm64: dts: mediatek: mt7622: readd syscon to pciesys
+ node
+
+Sata node reference the pciesys with the property mediatek,phy-node
+and that is used as a syscon to access the pciesys regs.
+
+Readd the syscon compatible to pciesys node to restore correct
+functionality of the SATA interface.
+
+Fixes: 3ba5a6159434 ("arm64: dts: mediatek: mt7622: fix clock controllers")
+Reported-by: Frank Wunderlich <frank-w at public-files.de>
+Co-developed-by: Frank Wunderlich <frank-w at public-files.de>
+Signed-off-by: Frank Wunderlich <frank-w at public-files.de>
+Signed-off-by: Christian Marangi <ansuelsmth at gmail.com>
+Cc: stable at vger.kernel.org
+---
+ arch/arm64/boot/dts/mediatek/mt7622.dtsi | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi
++++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi
+@@ -798,7 +798,7 @@
+ 	};
+ 
+ 	pciesys: clock-controller at 1a100800 {
+-		compatible = "mediatek,mt7622-pciesys";
++		compatible = "mediatek,mt7622-pciesys", "syscon";
+ 		reg = <0 0x1a100800 0 0x1000>;
+ 		#clock-cells = <1>;
+ 		#reset-cells = <1>;