[openwrt/openwrt] bmips: b53: enable bcm63268 internal PHYs
LEDE Commits
lede-commits at lists.infradead.org
Tue Dec 9 06:13:08 PST 2025
noltari pushed a commit to openwrt/openwrt.git, branch main:
https://git.openwrt.org/c2c38469a8d37c46161076cde873ad50cb5f5e35
commit c2c38469a8d37c46161076cde873ad50cb5f5e35
Author: Kyle Hendry <kylehendrydev at gmail.com>
AuthorDate: Fri Jan 17 12:18:20 2025 -0800
bmips: b53: enable bcm63268 internal PHYs
On the smartrg sr505n the bootloader only sets registers to enable the
PHYs if it's interrupted. When Linux boots this results in a -EINVAL
error when trying to read from the EPHYs and the GPHY doesn't work.
This patch disables low power mode in the GPHY/EPHYs and properly resets
the EPHYs.
Signed-off-by: Kyle Hendry <kylehendrydev at gmail.com>
Link: https://github.com/openwrt/openwrt/pull/17648
Signed-off-by: Álvaro Fernández Rojas <noltari at gmail.com>
---
target/linux/bmips/dts/bcm6318.dtsi | 28 ++++++++++++++++++++++++++++
target/linux/bmips/dts/bcm63268.dtsi | 31 +++++++++++++++++++++++++++++--
target/linux/bmips/dts/bcm6328.dtsi | 28 ++++++++++++++++++++++++++++
target/linux/bmips/dts/bcm6362.dtsi | 28 ++++++++++++++++++++++++++++
target/linux/bmips/dts/bcm6368.dtsi | 28 ++++++++++++++++++++++++++++
5 files changed, 141 insertions(+), 2 deletions(-)
diff --git a/target/linux/bmips/dts/bcm6318.dtsi b/target/linux/bmips/dts/bcm6318.dtsi
index 03fb01bc04..3bd1eeae82 100644
--- a/target/linux/bmips/dts/bcm6318.dtsi
+++ b/target/linux/bmips/dts/bcm6318.dtsi
@@ -260,6 +260,12 @@
pins = "gpio40";
};
};
+
+ ephy_rst: reset-controller at 3c {
+ compatible = "brcm,bcm6345-reset";
+ reg = <0x3c 0x4>;
+ #reset-cells = <1>;
+ };
};
uart0: serial at 10000100 {
@@ -399,6 +405,8 @@
reg = <0x10080000 0x8000>;
big-endian;
+ brcm,gpio-ctrl = <&gpio_cntl>;
+
ports {
#address-cells = <1>;
#size-cells = <0>;
@@ -431,21 +439,41 @@
phy1: ethernet-phy at 1 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <1>;
+
+ resets = <&ephy_rst 0>;
+ reset-names = "phy";
+ reset-assert-us = <2000>;
+ reset-deassert-us = <2000>;
};
phy2: ethernet-phy at 2 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <2>;
+
+ resets = <&ephy_rst 1>;
+ reset-names = "phy";
+ reset-assert-us = <2000>;
+ reset-deassert-us = <2000>;
};
phy3: ethernet-phy at 3 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <3>;
+
+ resets = <&ephy_rst 2>;
+ reset-names = "phy";
+ reset-assert-us = <2000>;
+ reset-deassert-us = <2000>;
};
phy4: ethernet-phy at 4 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <4>;
+
+ resets = <&ephy_rst 3>;
+ reset-names = "phy";
+ reset-assert-us = <2000>;
+ reset-deassert-us = <2000>;
};
};
diff --git a/target/linux/bmips/dts/bcm63268.dtsi b/target/linux/bmips/dts/bcm63268.dtsi
index 5a8cb7193f..1344be2e43 100644
--- a/target/linux/bmips/dts/bcm63268.dtsi
+++ b/target/linux/bmips/dts/bcm63268.dtsi
@@ -288,6 +288,12 @@
pins = "dsl_gpio9";
};
};
+
+ ephy_rst: reset-controller at 3c {
+ compatible = "brcm,bcm6345-reset";
+ reg = <0x3c 0x4>;
+ #reset-cells = <1>;
+ };
};
uart0: serial at 10000180 {
@@ -481,8 +487,7 @@
<&timer_clk BCM63268_TCLK_GPHY1>;
resets = <&periph_rst BCM63268_RST_ENETSW>,
- <&periph_rst BCM63268_RST_EPHY>,
- <&periph_rst BCM63268_RST_GPHY>;
+ <&periph_rst BCM63268_RST_EPHY>;
power-domains = <&periph_pwr BCM63268_POWER_DOMAIN_ROBOSW>;
@@ -532,6 +537,8 @@
reg = <0x10700000 0x8000>;
big-endian;
+ brcm,gpio-ctrl = <&gpio_cntl>;
+
ports {
#address-cells = <1>;
#size-cells = <0>;
@@ -564,21 +571,41 @@
phy1: ethernet-phy at 1 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <1>;
+
+ resets = <&ephy_rst 0>;
+ reset-names = "phy";
+ reset-assert-us = <2000>;
+ reset-deassert-us = <2000>;
};
phy2: ethernet-phy at 2 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <2>;
+
+ resets = <&ephy_rst 1>;
+ reset-names = "phy";
+ reset-assert-us = <2000>;
+ reset-deassert-us = <2000>;
};
phy3: ethernet-phy at 3 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <3>;
+
+ resets = <&ephy_rst 2>;
+ reset-names = "phy";
+ reset-assert-us = <2000>;
+ reset-deassert-us = <2000>;
};
phy4: ethernet-phy at 4 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <4>;
+
+ resets = <&periph_rst BCM63268_RST_GPHY>;
+ reset-names = "phy";
+ reset-assert-us = <2000>;
+ reset-deassert-us = <2000>;
};
};
diff --git a/target/linux/bmips/dts/bcm6328.dtsi b/target/linux/bmips/dts/bcm6328.dtsi
index 52f94950a3..6376bbb8d0 100644
--- a/target/linux/bmips/dts/bcm6328.dtsi
+++ b/target/linux/bmips/dts/bcm6328.dtsi
@@ -248,6 +248,12 @@
pins = "usb_port1";
};
};
+
+ ephy_rst: reset-controller at 3c {
+ compatible = "brcm,bcm6345-reset";
+ reg = <0x3c 0x4>;
+ #reset-cells = <1>;
+ };
};
uart0: serial at 10000100 {
@@ -417,6 +423,8 @@
reg = <0x10e00000 0x8000>;
big-endian;
+ brcm,gpio-ctrl = <&gpio_cntl>;
+
ports {
#address-cells = <1>;
#size-cells = <0>;
@@ -449,21 +457,41 @@
phy1: ethernet-phy at 1 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <1>;
+
+ resets = <&ephy_rst 0>;
+ reset-names = "phy";
+ reset-assert-us = <2000>;
+ reset-deassert-us = <2000>;
};
phy2: ethernet-phy at 2 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <2>;
+
+ resets = <&ephy_rst 1>;
+ reset-names = "phy";
+ reset-assert-us = <2000>;
+ reset-deassert-us = <2000>;
};
phy3: ethernet-phy at 3 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <3>;
+
+ resets = <&ephy_rst 2>;
+ reset-names = "phy";
+ reset-assert-us = <2000>;
+ reset-deassert-us = <2000>;
};
phy4: ethernet-phy at 4 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <4>;
+
+ resets = <&ephy_rst 3>;
+ reset-names = "phy";
+ reset-assert-us = <2000>;
+ reset-deassert-us = <2000>;
};
};
diff --git a/target/linux/bmips/dts/bcm6362.dtsi b/target/linux/bmips/dts/bcm6362.dtsi
index 5722f6e30c..c73b278dc8 100644
--- a/target/linux/bmips/dts/bcm6362.dtsi
+++ b/target/linux/bmips/dts/bcm6362.dtsi
@@ -323,6 +323,12 @@
pins = "nand_grp";
};
};
+
+ ephy_rst: reset-controller at 3c {
+ compatible = "brcm,bcm6345-reset";
+ reg = <0x3c 0x4>;
+ #reset-cells = <1>;
+ };
};
uart0: serial at 10000100 {
@@ -526,6 +532,8 @@
reg = <0x10e00000 0x8000>;
big-endian;
+ brcm,gpio-ctrl = <&gpio_cntl>;
+
ports {
#address-cells = <1>;
#size-cells = <0>;
@@ -558,21 +566,41 @@
phy1: ethernet-phy at 1 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <1>;
+
+ resets = <&ephy_rst 0>;
+ reset-names = "phy";
+ reset-assert-us = <2000>;
+ reset-deassert-us = <2000>;
};
phy2: ethernet-phy at 2 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <2>;
+
+ resets = <&ephy_rst 1>;
+ reset-names = "phy";
+ reset-assert-us = <2000>;
+ reset-deassert-us = <2000>;
};
phy3: ethernet-phy at 3 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <3>;
+
+ resets = <&ephy_rst 2>;
+ reset-names = "phy";
+ reset-assert-us = <2000>;
+ reset-deassert-us = <2000>;
};
phy4: ethernet-phy at 4 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <4>;
+
+ resets = <&ephy_rst 3>;
+ reset-names = "phy";
+ reset-assert-us = <2000>;
+ reset-deassert-us = <2000>;
};
};
diff --git a/target/linux/bmips/dts/bcm6368.dtsi b/target/linux/bmips/dts/bcm6368.dtsi
index a855ab340a..51a59cc8c0 100644
--- a/target/linux/bmips/dts/bcm6368.dtsi
+++ b/target/linux/bmips/dts/bcm6368.dtsi
@@ -337,6 +337,12 @@
pins = "uart1_grp";
};
};
+
+ ephy_rst: reset-controller at 3c {
+ compatible = "brcm,bcm6345-reset";
+ reg = <0x3c 0x4>;
+ #reset-cells = <1>;
+ };
};
leds: led-controller at 100000d0 {
@@ -528,6 +534,8 @@
reg = <0x10f00000 0x8000>;
big-endian;
+ brcm,gpio-ctrl = <&gpio_cntl>;
+
ports {
#address-cells = <1>;
#size-cells = <0>;
@@ -560,21 +568,41 @@
phy1: ethernet-phy at 1 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <1>;
+
+ resets = <&ephy_rst 6>;
+ reset-names = "phy";
+ reset-assert-us = <2000>;
+ reset-deassert-us = <2000>;
};
phy2: ethernet-phy at 2 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <2>;
+
+ resets = <&ephy_rst 7>;
+ reset-names = "phy";
+ reset-assert-us = <2000>;
+ reset-deassert-us = <2000>;
};
phy3: ethernet-phy at 3 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <3>;
+
+ resets = <&ephy_rst 8>;
+ reset-names = "phy";
+ reset-assert-us = <2000>;
+ reset-deassert-us = <2000>;
};
phy4: ethernet-phy at 4 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <4>;
+
+ resets = <&ephy_rst 9>;
+ reset-names = "phy";
+ reset-assert-us = <2000>;
+ reset-deassert-us = <2000>;
};
};
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