[openwrt/openwrt] mediatek: mt7988: add missing clock for PCIe ports

[LEDE Commits]

dangole pushed a commit to openwrt/openwrt.git, branch main:
https://git.openwrt.org/2b25f66d0a61edf7b9411432b6c920ad00f0f28b

commit 2b25f66d0a61edf7b9411432b6c920ad00f0f28b
Author: Daniel Golle <daniel at makrotopia.org>
AuthorDate: Fri Mar 15 14:07:58 2024 +0000

    mediatek: mt7988: add missing clock for PCIe ports
    
    Add missing CLK_TOP_PEXTP_Px_SEL clock for each of the 4 PCIe interfaces
    of the MT7988 SoC. Without that clock PCIe doesn't work reliable.
    
    Signed-off-by: Daniel Golle <daniel at makrotopia.org>
---
 .../arch/arm64/boot/dts/mediatek/mt7988a.dtsi        | 20 ++++++++++++--------
 .../arch/arm64/boot/dts/mediatek/mt7988a.dtsi        | 20 ++++++++++++--------
 2 files changed, 24 insertions(+), 16 deletions(-)

diff --git a/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a.dtsi b/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a.dtsi
index 904339335f..52bfed89ee 100644
--- a/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a.dtsi
+++ b/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a.dtsi
@@ -948,9 +948,10 @@
 			clocks = <&infracfg CLK_INFRA_PCIE_PIPE_P2>,
 				 <&infracfg CLK_INFRA_PCIE_GFMUX_TL_P2>,
 				 <&infracfg CLK_INFRA_PCIE_PERI_26M_CK_P2>,
-				 <&infracfg CLK_INFRA_133M_PCIE_CK_P2>;
+				 <&infracfg CLK_INFRA_133M_PCIE_CK_P2>,
+				 <&topckgen CLK_TOP_PEXTP_P2_SEL>;
 			clock-names = "pl_250m", "tl_26m", "peri_26m",
-				      "top_133m";
+				      "top_133m", "pextp_clk";
 			pinctrl-names = "default";
 			pinctrl-0 = <&pcie2_pins>;
 			phys = <&xphyu3port0 PHY_TYPE_PCIE>;
@@ -989,9 +990,10 @@
 			clocks = <&infracfg CLK_INFRA_PCIE_PIPE_P3>,
 				 <&infracfg CLK_INFRA_PCIE_GFMUX_TL_P3>,
 				 <&infracfg CLK_INFRA_PCIE_PERI_26M_CK_P3>,
-				 <&infracfg CLK_INFRA_133M_PCIE_CK_P3>;
+				 <&infracfg CLK_INFRA_133M_PCIE_CK_P3>,
+				 <&topckgen CLK_TOP_PEXTP_P3_SEL>;
 			clock-names = "pl_250m", "tl_26m", "peri_26m",
-				      "top_133m";
+				      "top_133m", "pextp_clk";
 			pinctrl-names = "default";
 			pinctrl-0 = <&pcie3_pins>;
 			#interrupt-cells = <1>;
@@ -1028,9 +1030,10 @@
 			clocks = <&infracfg CLK_INFRA_PCIE_PIPE_P0>,
 				 <&infracfg CLK_INFRA_PCIE_GFMUX_TL_P0>,
 				 <&infracfg CLK_INFRA_PCIE_PERI_26M_CK_P0>,
-				 <&infracfg CLK_INFRA_133M_PCIE_CK_P0>;
+				 <&infracfg CLK_INFRA_133M_PCIE_CK_P0>,
+				 <&topckgen CLK_TOP_PEXTP_P0_SEL>;
 			clock-names = "pl_250m", "tl_26m", "peri_26m",
-				      "top_133m";
+				      "top_133m", "pextp_clk";
 			pinctrl-names = "default";
 			pinctrl-0 = <&pcie0_pins>;
 			#interrupt-cells = <1>;
@@ -1067,9 +1070,10 @@
 			clocks = <&infracfg CLK_INFRA_PCIE_PIPE_P1>,
 				 <&infracfg CLK_INFRA_PCIE_GFMUX_TL_P1>,
 				 <&infracfg CLK_INFRA_PCIE_PERI_26M_CK_P1>,
-				 <&infracfg CLK_INFRA_133M_PCIE_CK_P1>;
+				 <&infracfg CLK_INFRA_133M_PCIE_CK_P1>,
+				 <&topckgen CLK_TOP_PEXTP_P1_SEL>;
 			clock-names = "pl_250m", "tl_26m", "peri_26m",
-				      "top_133m";
+				      "top_133m", "pextp_clk";
 			pinctrl-names = "default";
 			pinctrl-0 = <&pcie1_pins>;
 			#interrupt-cells = <1>;
diff --git a/target/linux/mediatek/files-6.6/arch/arm64/boot/dts/mediatek/mt7988a.dtsi b/target/linux/mediatek/files-6.6/arch/arm64/boot/dts/mediatek/mt7988a.dtsi
index 904339335f..52bfed89ee 100644
--- a/target/linux/mediatek/files-6.6/arch/arm64/boot/dts/mediatek/mt7988a.dtsi
+++ b/target/linux/mediatek/files-6.6/arch/arm64/boot/dts/mediatek/mt7988a.dtsi
@@ -948,9 +948,10 @@
 			clocks = <&infracfg CLK_INFRA_PCIE_PIPE_P2>,
 				 <&infracfg CLK_INFRA_PCIE_GFMUX_TL_P2>,
 				 <&infracfg CLK_INFRA_PCIE_PERI_26M_CK_P2>,
-				 <&infracfg CLK_INFRA_133M_PCIE_CK_P2>;
+				 <&infracfg CLK_INFRA_133M_PCIE_CK_P2>,
+				 <&topckgen CLK_TOP_PEXTP_P2_SEL>;
 			clock-names = "pl_250m", "tl_26m", "peri_26m",
-				      "top_133m";
+				      "top_133m", "pextp_clk";
 			pinctrl-names = "default";
 			pinctrl-0 = <&pcie2_pins>;
 			phys = <&xphyu3port0 PHY_TYPE_PCIE>;
@@ -989,9 +990,10 @@
 			clocks = <&infracfg CLK_INFRA_PCIE_PIPE_P3>,
 				 <&infracfg CLK_INFRA_PCIE_GFMUX_TL_P3>,
 				 <&infracfg CLK_INFRA_PCIE_PERI_26M_CK_P3>,
-				 <&infracfg CLK_INFRA_133M_PCIE_CK_P3>;
+				 <&infracfg CLK_INFRA_133M_PCIE_CK_P3>,
+				 <&topckgen CLK_TOP_PEXTP_P3_SEL>;
 			clock-names = "pl_250m", "tl_26m", "peri_26m",
-				      "top_133m";
+				      "top_133m", "pextp_clk";
 			pinctrl-names = "default";
 			pinctrl-0 = <&pcie3_pins>;
 			#interrupt-cells = <1>;
@@ -1028,9 +1030,10 @@
 			clocks = <&infracfg CLK_INFRA_PCIE_PIPE_P0>,
 				 <&infracfg CLK_INFRA_PCIE_GFMUX_TL_P0>,
 				 <&infracfg CLK_INFRA_PCIE_PERI_26M_CK_P0>,
-				 <&infracfg CLK_INFRA_133M_PCIE_CK_P0>;
+				 <&infracfg CLK_INFRA_133M_PCIE_CK_P0>,
+				 <&topckgen CLK_TOP_PEXTP_P0_SEL>;
 			clock-names = "pl_250m", "tl_26m", "peri_26m",
-				      "top_133m";
+				      "top_133m", "pextp_clk";
 			pinctrl-names = "default";
 			pinctrl-0 = <&pcie0_pins>;
 			#interrupt-cells = <1>;
@@ -1067,9 +1070,10 @@
 			clocks = <&infracfg CLK_INFRA_PCIE_PIPE_P1>,
 				 <&infracfg CLK_INFRA_PCIE_GFMUX_TL_P1>,
 				 <&infracfg CLK_INFRA_PCIE_PERI_26M_CK_P1>,
-				 <&infracfg CLK_INFRA_133M_PCIE_CK_P1>;
+				 <&infracfg CLK_INFRA_133M_PCIE_CK_P1>,
+				 <&topckgen CLK_TOP_PEXTP_P1_SEL>;
 			clock-names = "pl_250m", "tl_26m", "peri_26m",
-				      "top_133m";
+				      "top_133m", "pextp_clk";
 			pinctrl-names = "default";
 			pinctrl-0 = <&pcie1_pins>;
 			#interrupt-cells = <1>;