[openwrt/openwrt] generic: 5.15: backport upstream Aquantia PHY firmware loader patches
LEDE Commits
lede-commits at lists.infradead.org
Tue Feb 13 01:00:20 PST 2024
rmilecki pushed a commit to openwrt/openwrt.git, branch openwrt-23.05:
https://git.openwrt.org/eda5930d431545bbdcd808657d50de999062fb81
commit eda5930d431545bbdcd808657d50de999062fb81
Author: Christian Marangi <ansuelsmth at gmail.com>
AuthorDate: Sun Nov 19 12:52:55 2023 +0100
generic: 5.15: backport upstream Aquantia PHY firmware loader patches
Backport merged upstream patch that adds support for firmware loader
from NVMEM or attached filesystem for Aquantia PHYs.
Refresh all kernel patches affected by this change.
Also update the path for aquantia .ko that got moved to dedicated
directory upstream.
Signed-off-by: Christian Marangi <ansuelsmth at gmail.com>
[rmilecki: port to 5.15]
Signed-off-by: Rafał Miłecki <rafal at milecki.pl>
(cherry picked from commit 1b3259eb5cdcfecbfae7809b8a9febdbe22ac65f)
---
package/kernel/linux/modules/netdevices.mk | 4 +-
...t-phy-aquantia-move-to-separate-directory.patch | 2310 ++++++++++++++++++++
...y-aquantia-move-MMD_VEND-define-to-header.patch | 183 ++
...et-phy-aquantia-add-firmware-load-support.patch | 504 +++++
...ver-for-Motorcomm-yt8521-gigabit-ethernet.patch | 2 +-
...2-03-net-phy-add-Motorcomm-YT8531S-phy-id.patch | 2 +-
...ver-for-Motorcomm-yt8531-gigabit-ethernet.patch | 2 +-
.../hack-5.15/720-net-phy-add-aqr-phys.patch | 14 +-
...net-phy-aquantia-enable-AQR112-and-AQR412.patch | 14 +-
...-phy-aquantia-fix-system-side-protocol-mi.patch | 8 +-
...et-phy-aquantia-Add-AQR113-driver-support.patch | 10 +-
...-aquantia-add-PHY_IDs-for-AQR112-variants.patch | 10 +-
.../708-net-phy-Add-Qualcom-QCA807x-driver.patch | 4 +-
.../500-gsw-rtl8367s-mt7622-support.patch | 4 +-
...-driver-for-MediaTek-SoC-built-in-GE-PHYs.patch | 4 +-
...-net-phy-add-driver-for-MediaTek-2.5G-PHY.patch | 4 +-
.../realtek/patches-5.15/705-add-rtl-phy.patch | 4 +-
17 files changed, 3040 insertions(+), 43 deletions(-)
diff --git a/package/kernel/linux/modules/netdevices.mk b/package/kernel/linux/modules/netdevices.mk
index b8f2466cb4..2a7cc65d60 100644
--- a/package/kernel/linux/modules/netdevices.mk
+++ b/package/kernel/linux/modules/netdevices.mk
@@ -361,9 +361,9 @@ $(eval $(call KernelPackage,phy-smsc))
define KernelPackage/phy-aquantia
SUBMENU:=$(NETWORK_DEVICES_MENU)
TITLE:=Aquantia Ethernet PHYs
- DEPENDS:=+kmod-libphy +kmod-hwmon-core
+ DEPENDS:=+kmod-libphy +kmod-hwmon-core +kmod-lib-crc-ccitt
KCONFIG:=CONFIG_AQUANTIA_PHY
- FILES:=$(LINUX_DIR)/drivers/net/phy/aquantia.ko
+ FILES:=$(LINUX_DIR)/drivers/net/phy/aquantia/aquantia.ko
AUTOLOAD:=$(call AutoLoad,18,aquantia,1)
endef
diff --git a/target/linux/generic/backport-5.15/737-01-v6.7-net-phy-aquantia-move-to-separate-directory.patch b/target/linux/generic/backport-5.15/737-01-v6.7-net-phy-aquantia-move-to-separate-directory.patch
new file mode 100644
index 0000000000..4bb786e790
--- /dev/null
+++ b/target/linux/generic/backport-5.15/737-01-v6.7-net-phy-aquantia-move-to-separate-directory.patch
@@ -0,0 +1,2310 @@
+From d2213db3f49bce8e7a87c8de05b9a091f78f654e Mon Sep 17 00:00:00 2001
+From: Christian Marangi <ansuelsmth at gmail.com>
+Date: Tue, 14 Nov 2023 15:08:41 +0100
+Subject: [PATCH 1/3] net: phy: aquantia: move to separate directory
+
+Move aquantia PHY driver to separate driectory in preparation for
+firmware loading support to keep things tidy.
+
+Signed-off-by: Christian Marangi <ansuelsmth at gmail.com>
+Reviewed-by: Andrew Lunn <andrew at lunn.ch>
+Signed-off-by: David S. Miller <davem at davemloft.net>
+---
+ drivers/net/phy/Kconfig | 5 +----
+ drivers/net/phy/Makefile | 6 +-----
+ drivers/net/phy/aquantia/Kconfig | 5 +++++
+ drivers/net/phy/aquantia/Makefile | 6 ++++++
+ drivers/net/phy/{ => aquantia}/aquantia.h | 0
+ drivers/net/phy/{ => aquantia}/aquantia_hwmon.c | 0
+ drivers/net/phy/{ => aquantia}/aquantia_main.c | 0
+ 7 files changed, 13 insertions(+), 9 deletions(-)
+ create mode 100644 drivers/net/phy/aquantia/Kconfig
+ create mode 100644 drivers/net/phy/aquantia/Makefile
+ rename drivers/net/phy/{ => aquantia}/aquantia.h (100%)
+ rename drivers/net/phy/{ => aquantia}/aquantia_hwmon.c (100%)
+ rename drivers/net/phy/{ => aquantia}/aquantia_main.c (100%)
+
+--- a/drivers/net/phy/Kconfig
++++ b/drivers/net/phy/Kconfig
+@@ -83,10 +83,7 @@ config ADIN_PHY
+ - ADIN1300 - Robust,Industrial, Low Latency 10/100/1000 Gigabit
+ Ethernet PHY
+
+-config AQUANTIA_PHY
+- tristate "Aquantia PHYs"
+- help
+- Currently supports the Aquantia AQ1202, AQ2104, AQR105, AQR405
++source "drivers/net/phy/aquantia/Kconfig"
+
+ config AX88796B_PHY
+ tristate "Asix PHYs"
+--- a/drivers/net/phy/Makefile
++++ b/drivers/net/phy/Makefile
+@@ -32,11 +32,7 @@ obj-y += $(sfp-obj-y) $(sfp-obj-m)
+
+ obj-$(CONFIG_ADIN_PHY) += adin.o
+ obj-$(CONFIG_AMD_PHY) += amd.o
+-aquantia-objs += aquantia_main.o
+-ifdef CONFIG_HWMON
+-aquantia-objs += aquantia_hwmon.o
+-endif
+-obj-$(CONFIG_AQUANTIA_PHY) += aquantia.o
++obj-$(CONFIG_AQUANTIA_PHY) += aquantia/
+ obj-$(CONFIG_AT803X_PHY) += at803x.o
+ obj-$(CONFIG_AX88796B_PHY) += ax88796b.o
+ obj-$(CONFIG_BCM54140_PHY) += bcm54140.o
+--- /dev/null
++++ b/drivers/net/phy/aquantia/Kconfig
+@@ -0,0 +1,5 @@
++# SPDX-License-Identifier: GPL-2.0-only
++config AQUANTIA_PHY
++ tristate "Aquantia PHYs"
++ help
++ Currently supports the Aquantia AQ1202, AQ2104, AQR105, AQR405
+--- /dev/null
++++ b/drivers/net/phy/aquantia/Makefile
+@@ -0,0 +1,6 @@
++# SPDX-License-Identifier: GPL-2.0
++aquantia-objs += aquantia_main.o
++ifdef CONFIG_HWMON
++aquantia-objs += aquantia_hwmon.o
++endif
++obj-$(CONFIG_AQUANTIA_PHY) += aquantia.o
+--- a/drivers/net/phy/aquantia.h
++++ /dev/null
+@@ -1,16 +0,0 @@
+-/* SPDX-License-Identifier: GPL-2.0 */
+-/* HWMON driver for Aquantia PHY
+- *
+- * Author: Nikita Yushchenko <nikita.yoush at cogentembedded.com>
+- * Author: Andrew Lunn <andrew at lunn.ch>
+- * Author: Heiner Kallweit <hkallweit1 at gmail.com>
+- */
+-
+-#include <linux/device.h>
+-#include <linux/phy.h>
+-
+-#if IS_REACHABLE(CONFIG_HWMON)
+-int aqr_hwmon_probe(struct phy_device *phydev);
+-#else
+-static inline int aqr_hwmon_probe(struct phy_device *phydev) { return 0; }
+-#endif
+--- /dev/null
++++ b/drivers/net/phy/aquantia/aquantia.h
+@@ -0,0 +1,16 @@
++/* SPDX-License-Identifier: GPL-2.0 */
++/* HWMON driver for Aquantia PHY
++ *
++ * Author: Nikita Yushchenko <nikita.yoush at cogentembedded.com>
++ * Author: Andrew Lunn <andrew at lunn.ch>
++ * Author: Heiner Kallweit <hkallweit1 at gmail.com>
++ */
++
++#include <linux/device.h>
++#include <linux/phy.h>
++
++#if IS_REACHABLE(CONFIG_HWMON)
++int aqr_hwmon_probe(struct phy_device *phydev);
++#else
++static inline int aqr_hwmon_probe(struct phy_device *phydev) { return 0; }
++#endif
+--- /dev/null
++++ b/drivers/net/phy/aquantia/aquantia_hwmon.c
+@@ -0,0 +1,250 @@
++// SPDX-License-Identifier: GPL-2.0
++/* HWMON driver for Aquantia PHY
++ *
++ * Author: Nikita Yushchenko <nikita.yoush at cogentembedded.com>
++ * Author: Andrew Lunn <andrew at lunn.ch>
++ * Author: Heiner Kallweit <hkallweit1 at gmail.com>
++ */
++
++#include <linux/phy.h>
++#include <linux/device.h>
++#include <linux/ctype.h>
++#include <linux/hwmon.h>
++
++#include "aquantia.h"
++
++/* Vendor specific 1, MDIO_MMD_VEND2 */
++#define VEND1_THERMAL_PROV_HIGH_TEMP_FAIL 0xc421
++#define VEND1_THERMAL_PROV_LOW_TEMP_FAIL 0xc422
++#define VEND1_THERMAL_PROV_HIGH_TEMP_WARN 0xc423
++#define VEND1_THERMAL_PROV_LOW_TEMP_WARN 0xc424
++#define VEND1_THERMAL_STAT1 0xc820
++#define VEND1_THERMAL_STAT2 0xc821
++#define VEND1_THERMAL_STAT2_VALID BIT(0)
++#define VEND1_GENERAL_STAT1 0xc830
++#define VEND1_GENERAL_STAT1_HIGH_TEMP_FAIL BIT(14)
++#define VEND1_GENERAL_STAT1_LOW_TEMP_FAIL BIT(13)
++#define VEND1_GENERAL_STAT1_HIGH_TEMP_WARN BIT(12)
++#define VEND1_GENERAL_STAT1_LOW_TEMP_WARN BIT(11)
++
++#if IS_REACHABLE(CONFIG_HWMON)
++
++static umode_t aqr_hwmon_is_visible(const void *data,
++ enum hwmon_sensor_types type,
++ u32 attr, int channel)
++{
++ if (type != hwmon_temp)
++ return 0;
++
++ switch (attr) {
++ case hwmon_temp_input:
++ case hwmon_temp_min_alarm:
++ case hwmon_temp_max_alarm:
++ case hwmon_temp_lcrit_alarm:
++ case hwmon_temp_crit_alarm:
++ return 0444;
++ case hwmon_temp_min:
++ case hwmon_temp_max:
++ case hwmon_temp_lcrit:
++ case hwmon_temp_crit:
++ return 0644;
++ default:
++ return 0;
++ }
++}
++
++static int aqr_hwmon_get(struct phy_device *phydev, int reg, long *value)
++{
++ int temp = phy_read_mmd(phydev, MDIO_MMD_VEND1, reg);
++
++ if (temp < 0)
++ return temp;
++
++ /* 16 bit value is 2's complement with LSB = 1/256th degree Celsius */
++ *value = (s16)temp * 1000 / 256;
++
++ return 0;
++}
++
++static int aqr_hwmon_set(struct phy_device *phydev, int reg, long value)
++{
++ int temp;
++
++ if (value >= 128000 || value < -128000)
++ return -ERANGE;
++
++ temp = value * 256 / 1000;
++
++ /* temp is in s16 range and we're interested in lower 16 bits only */
++ return phy_write_mmd(phydev, MDIO_MMD_VEND1, reg, (u16)temp);
++}
++
++static int aqr_hwmon_test_bit(struct phy_device *phydev, int reg, int bit)
++{
++ int val = phy_read_mmd(phydev, MDIO_MMD_VEND1, reg);
++
++ if (val < 0)
++ return val;
++
++ return !!(val & bit);
++}
++
++static int aqr_hwmon_status1(struct phy_device *phydev, int bit, long *value)
++{
++ int val = aqr_hwmon_test_bit(phydev, VEND1_GENERAL_STAT1, bit);
++
++ if (val < 0)
++ return val;
++
++ *value = val;
++
++ return 0;
++}
++
++static int aqr_hwmon_read(struct device *dev, enum hwmon_sensor_types type,
++ u32 attr, int channel, long *value)
++{
++ struct phy_device *phydev = dev_get_drvdata(dev);
++ int reg;
++
++ if (type != hwmon_temp)
++ return -EOPNOTSUPP;
++
++ switch (attr) {
++ case hwmon_temp_input:
++ reg = aqr_hwmon_test_bit(phydev, VEND1_THERMAL_STAT2,
++ VEND1_THERMAL_STAT2_VALID);
++ if (reg < 0)
++ return reg;
++ if (!reg)
++ return -EBUSY;
++
++ return aqr_hwmon_get(phydev, VEND1_THERMAL_STAT1, value);
++
++ case hwmon_temp_lcrit:
++ return aqr_hwmon_get(phydev, VEND1_THERMAL_PROV_LOW_TEMP_FAIL,
++ value);
++ case hwmon_temp_min:
++ return aqr_hwmon_get(phydev, VEND1_THERMAL_PROV_LOW_TEMP_WARN,
++ value);
++ case hwmon_temp_max:
++ return aqr_hwmon_get(phydev, VEND1_THERMAL_PROV_HIGH_TEMP_WARN,
++ value);
++ case hwmon_temp_crit:
++ return aqr_hwmon_get(phydev, VEND1_THERMAL_PROV_HIGH_TEMP_FAIL,
++ value);
++ case hwmon_temp_lcrit_alarm:
++ return aqr_hwmon_status1(phydev,
++ VEND1_GENERAL_STAT1_LOW_TEMP_FAIL,
++ value);
++ case hwmon_temp_min_alarm:
++ return aqr_hwmon_status1(phydev,
++ VEND1_GENERAL_STAT1_LOW_TEMP_WARN,
++ value);
++ case hwmon_temp_max_alarm:
++ return aqr_hwmon_status1(phydev,
++ VEND1_GENERAL_STAT1_HIGH_TEMP_WARN,
++ value);
++ case hwmon_temp_crit_alarm:
++ return aqr_hwmon_status1(phydev,
++ VEND1_GENERAL_STAT1_HIGH_TEMP_FAIL,
++ value);
++ default:
++ return -EOPNOTSUPP;
++ }
++}
++
++static int aqr_hwmon_write(struct device *dev, enum hwmon_sensor_types type,
++ u32 attr, int channel, long value)
++{
++ struct phy_device *phydev = dev_get_drvdata(dev);
++
++ if (type != hwmon_temp)
++ return -EOPNOTSUPP;
++
++ switch (attr) {
++ case hwmon_temp_lcrit:
++ return aqr_hwmon_set(phydev, VEND1_THERMAL_PROV_LOW_TEMP_FAIL,
++ value);
++ case hwmon_temp_min:
++ return aqr_hwmon_set(phydev, VEND1_THERMAL_PROV_LOW_TEMP_WARN,
++ value);
++ case hwmon_temp_max:
++ return aqr_hwmon_set(phydev, VEND1_THERMAL_PROV_HIGH_TEMP_WARN,
++ value);
++ case hwmon_temp_crit:
++ return aqr_hwmon_set(phydev, VEND1_THERMAL_PROV_HIGH_TEMP_FAIL,
++ value);
++ default:
++ return -EOPNOTSUPP;
++ }
++}
++
++static const struct hwmon_ops aqr_hwmon_ops = {
++ .is_visible = aqr_hwmon_is_visible,
++ .read = aqr_hwmon_read,
++ .write = aqr_hwmon_write,
++};
++
++static u32 aqr_hwmon_chip_config[] = {
++ HWMON_C_REGISTER_TZ,
++ 0,
++};
++
++static const struct hwmon_channel_info aqr_hwmon_chip = {
++ .type = hwmon_chip,
++ .config = aqr_hwmon_chip_config,
++};
++
++static u32 aqr_hwmon_temp_config[] = {
++ HWMON_T_INPUT |
++ HWMON_T_MAX | HWMON_T_MIN |
++ HWMON_T_MAX_ALARM | HWMON_T_MIN_ALARM |
++ HWMON_T_CRIT | HWMON_T_LCRIT |
++ HWMON_T_CRIT_ALARM | HWMON_T_LCRIT_ALARM,
++ 0,
++};
++
++static const struct hwmon_channel_info aqr_hwmon_temp = {
++ .type = hwmon_temp,
++ .config = aqr_hwmon_temp_config,
++};
++
++static const struct hwmon_channel_info *aqr_hwmon_info[] = {
++ &aqr_hwmon_chip,
++ &aqr_hwmon_temp,
++ NULL,
++};
++
++static const struct hwmon_chip_info aqr_hwmon_chip_info = {
++ .ops = &aqr_hwmon_ops,
++ .info = aqr_hwmon_info,
++};
++
++int aqr_hwmon_probe(struct phy_device *phydev)
++{
++ struct device *dev = &phydev->mdio.dev;
++ struct device *hwmon_dev;
++ char *hwmon_name;
++ int i, j;
++
++ hwmon_name = devm_kstrdup(dev, dev_name(dev), GFP_KERNEL);
++ if (!hwmon_name)
++ return -ENOMEM;
++
++ for (i = j = 0; hwmon_name[i]; i++) {
++ if (isalnum(hwmon_name[i])) {
++ if (i != j)
++ hwmon_name[j] = hwmon_name[i];
++ j++;
++ }
++ }
++ hwmon_name[j] = '\0';
++
++ hwmon_dev = devm_hwmon_device_register_with_info(dev, hwmon_name,
++ phydev, &aqr_hwmon_chip_info, NULL);
++
++ return PTR_ERR_OR_ZERO(hwmon_dev);
++}
++
++#endif
+--- /dev/null
++++ b/drivers/net/phy/aquantia/aquantia_main.c
+@@ -0,0 +1,844 @@
++// SPDX-License-Identifier: GPL-2.0
++/*
++ * Driver for Aquantia PHY
++ *
++ * Author: Shaohui Xie <Shaohui.Xie at freescale.com>
++ *
++ * Copyright 2015 Freescale Semiconductor, Inc.
++ */
++
++#include <linux/kernel.h>
++#include <linux/module.h>
++#include <linux/delay.h>
++#include <linux/bitfield.h>
++#include <linux/phy.h>
++
++#include "aquantia.h"
++
++#define PHY_ID_AQ1202 0x03a1b445
++#define PHY_ID_AQ2104 0x03a1b460
++#define PHY_ID_AQR105 0x03a1b4a2
++#define PHY_ID_AQR106 0x03a1b4d0
++#define PHY_ID_AQR107 0x03a1b4e0
++#define PHY_ID_AQCS109 0x03a1b5c2
++#define PHY_ID_AQR405 0x03a1b4b0
++#define PHY_ID_AQR113C 0x31c31c12
++
++#define MDIO_PHYXS_VEND_IF_STATUS 0xe812
++#define MDIO_PHYXS_VEND_IF_STATUS_TYPE_MASK GENMASK(7, 3)
++#define MDIO_PHYXS_VEND_IF_STATUS_TYPE_KR 0
++#define MDIO_PHYXS_VEND_IF_STATUS_TYPE_KX 1
++#define MDIO_PHYXS_VEND_IF_STATUS_TYPE_XFI 2
++#define MDIO_PHYXS_VEND_IF_STATUS_TYPE_USXGMII 3
++#define MDIO_PHYXS_VEND_IF_STATUS_TYPE_XAUI 4
++#define MDIO_PHYXS_VEND_IF_STATUS_TYPE_SGMII 6
++#define MDIO_PHYXS_VEND_IF_STATUS_TYPE_RXAUI 7
++#define MDIO_PHYXS_VEND_IF_STATUS_TYPE_OCSGMII 10
++
++#define MDIO_AN_VEND_PROV 0xc400
++#define MDIO_AN_VEND_PROV_1000BASET_FULL BIT(15)
++#define MDIO_AN_VEND_PROV_1000BASET_HALF BIT(14)
++#define MDIO_AN_VEND_PROV_5000BASET_FULL BIT(11)
++#define MDIO_AN_VEND_PROV_2500BASET_FULL BIT(10)
++#define MDIO_AN_VEND_PROV_DOWNSHIFT_EN BIT(4)
++#define MDIO_AN_VEND_PROV_DOWNSHIFT_MASK GENMASK(3, 0)
++#define MDIO_AN_VEND_PROV_DOWNSHIFT_DFLT 4
++
++#define MDIO_AN_TX_VEND_STATUS1 0xc800
++#define MDIO_AN_TX_VEND_STATUS1_RATE_MASK GENMASK(3, 1)
++#define MDIO_AN_TX_VEND_STATUS1_10BASET 0
++#define MDIO_AN_TX_VEND_STATUS1_100BASETX 1
++#define MDIO_AN_TX_VEND_STATUS1_1000BASET 2
++#define MDIO_AN_TX_VEND_STATUS1_10GBASET 3
++#define MDIO_AN_TX_VEND_STATUS1_2500BASET 4
++#define MDIO_AN_TX_VEND_STATUS1_5000BASET 5
++#define MDIO_AN_TX_VEND_STATUS1_FULL_DUPLEX BIT(0)
++
++#define MDIO_AN_TX_VEND_INT_STATUS1 0xcc00
++#define MDIO_AN_TX_VEND_INT_STATUS1_DOWNSHIFT BIT(1)
++
++#define MDIO_AN_TX_VEND_INT_STATUS2 0xcc01
++#define MDIO_AN_TX_VEND_INT_STATUS2_MASK BIT(0)
++
++#define MDIO_AN_TX_VEND_INT_MASK2 0xd401
++#define MDIO_AN_TX_VEND_INT_MASK2_LINK BIT(0)
++
++#define MDIO_AN_RX_LP_STAT1 0xe820
++#define MDIO_AN_RX_LP_STAT1_1000BASET_FULL BIT(15)
++#define MDIO_AN_RX_LP_STAT1_1000BASET_HALF BIT(14)
++#define MDIO_AN_RX_LP_STAT1_SHORT_REACH BIT(13)
++#define MDIO_AN_RX_LP_STAT1_AQRATE_DOWNSHIFT BIT(12)
++#define MDIO_AN_RX_LP_STAT1_AQ_PHY BIT(2)
++
++#define MDIO_AN_RX_LP_STAT4 0xe823
++#define MDIO_AN_RX_LP_STAT4_FW_MAJOR GENMASK(15, 8)
++#define MDIO_AN_RX_LP_STAT4_FW_MINOR GENMASK(7, 0)
++
++#define MDIO_AN_RX_VEND_STAT3 0xe832
++#define MDIO_AN_RX_VEND_STAT3_AFR BIT(0)
++
++/* MDIO_MMD_C22EXT */
++#define MDIO_C22EXT_STAT_SGMII_RX_GOOD_FRAMES 0xd292
++#define MDIO_C22EXT_STAT_SGMII_RX_BAD_FRAMES 0xd294
++#define MDIO_C22EXT_STAT_SGMII_RX_FALSE_CARRIER 0xd297
++#define MDIO_C22EXT_STAT_SGMII_TX_GOOD_FRAMES 0xd313
++#define MDIO_C22EXT_STAT_SGMII_TX_BAD_FRAMES 0xd315
++#define MDIO_C22EXT_STAT_SGMII_TX_FALSE_CARRIER 0xd317
++#define MDIO_C22EXT_STAT_SGMII_TX_COLLISIONS 0xd318
++#define MDIO_C22EXT_STAT_SGMII_TX_LINE_COLLISIONS 0xd319
++#define MDIO_C22EXT_STAT_SGMII_TX_FRAME_ALIGN_ERR 0xd31a
++#define MDIO_C22EXT_STAT_SGMII_TX_RUNT_FRAMES 0xd31b
++
++/* Vendor specific 1, MDIO_MMD_VEND1 */
++#define VEND1_GLOBAL_FW_ID 0x0020
++#define VEND1_GLOBAL_FW_ID_MAJOR GENMASK(15, 8)
++#define VEND1_GLOBAL_FW_ID_MINOR GENMASK(7, 0)
++
++#define VEND1_GLOBAL_GEN_STAT2 0xc831
++#define VEND1_GLOBAL_GEN_STAT2_OP_IN_PROG BIT(15)
++
++/* The following registers all have similar layouts; first the registers... */
++#define VEND1_GLOBAL_CFG_10M 0x0310
++#define VEND1_GLOBAL_CFG_100M 0x031b
++#define VEND1_GLOBAL_CFG_1G 0x031c
++#define VEND1_GLOBAL_CFG_2_5G 0x031d
++#define VEND1_GLOBAL_CFG_5G 0x031e
++#define VEND1_GLOBAL_CFG_10G 0x031f
++/* ...and now the fields */
++#define VEND1_GLOBAL_CFG_RATE_ADAPT GENMASK(8, 7)
++#define VEND1_GLOBAL_CFG_RATE_ADAPT_NONE 0
++#define VEND1_GLOBAL_CFG_RATE_ADAPT_USX 1
++#define VEND1_GLOBAL_CFG_RATE_ADAPT_PAUSE 2
++
++#define VEND1_GLOBAL_RSVD_STAT1 0xc885
++#define VEND1_GLOBAL_RSVD_STAT1_FW_BUILD_ID GENMASK(7, 4)
++#define VEND1_GLOBAL_RSVD_STAT1_PROV_ID GENMASK(3, 0)
++
++#define VEND1_GLOBAL_RSVD_STAT9 0xc88d
++#define VEND1_GLOBAL_RSVD_STAT9_MODE GENMASK(7, 0)
++#define VEND1_GLOBAL_RSVD_STAT9_1000BT2 0x23
++
++#define VEND1_GLOBAL_INT_STD_STATUS 0xfc00
++#define VEND1_GLOBAL_INT_VEND_STATUS 0xfc01
++
++#define VEND1_GLOBAL_INT_STD_MASK 0xff00
++#define VEND1_GLOBAL_INT_STD_MASK_PMA1 BIT(15)
++#define VEND1_GLOBAL_INT_STD_MASK_PMA2 BIT(14)
++#define VEND1_GLOBAL_INT_STD_MASK_PCS1 BIT(13)
++#define VEND1_GLOBAL_INT_STD_MASK_PCS2 BIT(12)
++#define VEND1_GLOBAL_INT_STD_MASK_PCS3 BIT(11)
++#define VEND1_GLOBAL_INT_STD_MASK_PHY_XS1 BIT(10)
++#define VEND1_GLOBAL_INT_STD_MASK_PHY_XS2 BIT(9)
++#define VEND1_GLOBAL_INT_STD_MASK_AN1 BIT(8)
++#define VEND1_GLOBAL_INT_STD_MASK_AN2 BIT(7)
++#define VEND1_GLOBAL_INT_STD_MASK_GBE BIT(6)
++#define VEND1_GLOBAL_INT_STD_MASK_ALL BIT(0)
++
++#define VEND1_GLOBAL_INT_VEND_MASK 0xff01
++#define VEND1_GLOBAL_INT_VEND_MASK_PMA BIT(15)
++#define VEND1_GLOBAL_INT_VEND_MASK_PCS BIT(14)
++#define VEND1_GLOBAL_INT_VEND_MASK_PHY_XS BIT(13)
++#define VEND1_GLOBAL_INT_VEND_MASK_AN BIT(12)
++#define VEND1_GLOBAL_INT_VEND_MASK_GBE BIT(11)
++#define VEND1_GLOBAL_INT_VEND_MASK_GLOBAL1 BIT(2)
++#define VEND1_GLOBAL_INT_VEND_MASK_GLOBAL2 BIT(1)
++#define VEND1_GLOBAL_INT_VEND_MASK_GLOBAL3 BIT(0)
++
++/* Sleep and timeout for checking if the Processor-Intensive
++ * MDIO operation is finished
++ */
++#define AQR107_OP_IN_PROG_SLEEP 1000
++#define AQR107_OP_IN_PROG_TIMEOUT 100000
++
++struct aqr107_hw_stat {
++ const char *name;
++ int reg;
++ int size;
++};
++
++#define SGMII_STAT(n, r, s) { n, MDIO_C22EXT_STAT_SGMII_ ## r, s }
++static const struct aqr107_hw_stat aqr107_hw_stats[] = {
++ SGMII_STAT("sgmii_rx_good_frames", RX_GOOD_FRAMES, 26),
++ SGMII_STAT("sgmii_rx_bad_frames", RX_BAD_FRAMES, 26),
++ SGMII_STAT("sgmii_rx_false_carrier_events", RX_FALSE_CARRIER, 8),
++ SGMII_STAT("sgmii_tx_good_frames", TX_GOOD_FRAMES, 26),
++ SGMII_STAT("sgmii_tx_bad_frames", TX_BAD_FRAMES, 26),
++ SGMII_STAT("sgmii_tx_false_carrier_events", TX_FALSE_CARRIER, 8),
++ SGMII_STAT("sgmii_tx_collisions", TX_COLLISIONS, 8),
++ SGMII_STAT("sgmii_tx_line_collisions", TX_LINE_COLLISIONS, 8),
++ SGMII_STAT("sgmii_tx_frame_alignment_err", TX_FRAME_ALIGN_ERR, 16),
++ SGMII_STAT("sgmii_tx_runt_frames", TX_RUNT_FRAMES, 22),
++};
++#define AQR107_SGMII_STAT_SZ ARRAY_SIZE(aqr107_hw_stats)
++
++struct aqr107_priv {
++ u64 sgmii_stats[AQR107_SGMII_STAT_SZ];
++};
++
++static int aqr107_get_sset_count(struct phy_device *phydev)
++{
++ return AQR107_SGMII_STAT_SZ;
++}
++
++static void aqr107_get_strings(struct phy_device *phydev, u8 *data)
++{
++ int i;
++
++ for (i = 0; i < AQR107_SGMII_STAT_SZ; i++)
++ strscpy(data + i * ETH_GSTRING_LEN, aqr107_hw_stats[i].name,
++ ETH_GSTRING_LEN);
++}
++
++static u64 aqr107_get_stat(struct phy_device *phydev, int index)
++{
++ const struct aqr107_hw_stat *stat = aqr107_hw_stats + index;
++ int len_l = min(stat->size, 16);
++ int len_h = stat->size - len_l;
++ u64 ret;
++ int val;
++
++ val = phy_read_mmd(phydev, MDIO_MMD_C22EXT, stat->reg);
++ if (val < 0)
++ return U64_MAX;
++
++ ret = val & GENMASK(len_l - 1, 0);
++ if (len_h) {
++ val = phy_read_mmd(phydev, MDIO_MMD_C22EXT, stat->reg + 1);
++ if (val < 0)
++ return U64_MAX;
++
++ ret += (val & GENMASK(len_h - 1, 0)) << 16;
++ }
++
++ return ret;
++}
++
++static void aqr107_get_stats(struct phy_device *phydev,
++ struct ethtool_stats *stats, u64 *data)
++{
++ struct aqr107_priv *priv = phydev->priv;
++ u64 val;
++ int i;
++
++ for (i = 0; i < AQR107_SGMII_STAT_SZ; i++) {
++ val = aqr107_get_stat(phydev, i);
++ if (val == U64_MAX)
++ phydev_err(phydev, "Reading HW Statistics failed for %s\n",
++ aqr107_hw_stats[i].name);
++ else
++ priv->sgmii_stats[i] += val;
++
++ data[i] = priv->sgmii_stats[i];
++ }
++}
++
++static int aqr_config_aneg(struct phy_device *phydev)
++{
++ bool changed = false;
++ u16 reg;
++ int ret;
++
++ if (phydev->autoneg == AUTONEG_DISABLE)
++ return genphy_c45_pma_setup_forced(phydev);
++
++ ret = genphy_c45_an_config_aneg(phydev);
++ if (ret < 0)
++ return ret;
++ if (ret > 0)
++ changed = true;
++
++ /* Clause 45 has no standardized support for 1000BaseT, therefore
++ * use vendor registers for this mode.
++ */
++ reg = 0;
++ if (linkmode_test_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT,
++ phydev->advertising))
++ reg |= MDIO_AN_VEND_PROV_1000BASET_FULL;
++
++ if (linkmode_test_bit(ETHTOOL_LINK_MODE_1000baseT_Half_BIT,
++ phydev->advertising))
++ reg |= MDIO_AN_VEND_PROV_1000BASET_HALF;
++
++ /* Handle the case when the 2.5G and 5G speeds are not advertised */
++ if (linkmode_test_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT,
++ phydev->advertising))
++ reg |= MDIO_AN_VEND_PROV_2500BASET_FULL;
++
++ if (linkmode_test_bit(ETHTOOL_LINK_MODE_5000baseT_Full_BIT,
++ phydev->advertising))
++ reg |= MDIO_AN_VEND_PROV_5000BASET_FULL;
++
++ ret = phy_modify_mmd_changed(phydev, MDIO_MMD_AN, MDIO_AN_VEND_PROV,
++ MDIO_AN_VEND_PROV_1000BASET_HALF |
++ MDIO_AN_VEND_PROV_1000BASET_FULL |
++ MDIO_AN_VEND_PROV_2500BASET_FULL |
++ MDIO_AN_VEND_PROV_5000BASET_FULL, reg);
++ if (ret < 0)
++ return ret;
++ if (ret > 0)
++ changed = true;
++
++ return genphy_c45_check_and_restart_aneg(phydev, changed);
++}
++
++static int aqr_config_intr(struct phy_device *phydev)
++{
++ bool en = phydev->interrupts == PHY_INTERRUPT_ENABLED;
++ int err;
++
++ if (en) {
++ /* Clear any pending interrupts before enabling them */
++ err = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_TX_VEND_INT_STATUS2);
++ if (err < 0)
++ return err;
++ }
++
++ err = phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_TX_VEND_INT_MASK2,
++ en ? MDIO_AN_TX_VEND_INT_MASK2_LINK : 0);
++ if (err < 0)
++ return err;
++
++ err = phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_INT_STD_MASK,
++ en ? VEND1_GLOBAL_INT_STD_MASK_ALL : 0);
++ if (err < 0)
++ return err;
++
++ err = phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_INT_VEND_MASK,
++ en ? VEND1_GLOBAL_INT_VEND_MASK_GLOBAL3 |
++ VEND1_GLOBAL_INT_VEND_MASK_AN : 0);
++ if (err < 0)
++ return err;
++
++ if (!en) {
++ /* Clear any pending interrupts after we have disabled them */
++ err = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_TX_VEND_INT_STATUS2);
++ if (err < 0)
++ return err;
++ }
++
++ return 0;
++}
++
++static irqreturn_t aqr_handle_interrupt(struct phy_device *phydev)
++{
++ int irq_status;
++
++ irq_status = phy_read_mmd(phydev, MDIO_MMD_AN,
++ MDIO_AN_TX_VEND_INT_STATUS2);
++ if (irq_status < 0) {
++ phy_error(phydev);
++ return IRQ_NONE;
++ }
++
++ if (!(irq_status & MDIO_AN_TX_VEND_INT_STATUS2_MASK))
++ return IRQ_NONE;
++
++ phy_trigger_machine(phydev);
++
++ return IRQ_HANDLED;
++}
++
++static int aqr_read_status(struct phy_device *phydev)
++{
++ int val;
++
++ if (phydev->autoneg == AUTONEG_ENABLE) {
++ val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_RX_LP_STAT1);
++ if (val < 0)
++ return val;
++
++ linkmode_mod_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT,
++ phydev->lp_advertising,
++ val & MDIO_AN_RX_LP_STAT1_1000BASET_FULL);
++ linkmode_mod_bit(ETHTOOL_LINK_MODE_1000baseT_Half_BIT,
++ phydev->lp_advertising,
++ val & MDIO_AN_RX_LP_STAT1_1000BASET_HALF);
++ }
++
++ return genphy_c45_read_status(phydev);
++}
++
++static int aqr107_read_rate(struct phy_device *phydev)
++{
++ u32 config_reg;
++ int val;
++
++ val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_TX_VEND_STATUS1);
++ if (val < 0)
++ return val;
++
++ if (val & MDIO_AN_TX_VEND_STATUS1_FULL_DUPLEX)
++ phydev->duplex = DUPLEX_FULL;
++ else
++ phydev->duplex = DUPLEX_HALF;
++
++ switch (FIELD_GET(MDIO_AN_TX_VEND_STATUS1_RATE_MASK, val)) {
++ case MDIO_AN_TX_VEND_STATUS1_10BASET:
++ phydev->speed = SPEED_10;
++ config_reg = VEND1_GLOBAL_CFG_10M;
++ break;
++ case MDIO_AN_TX_VEND_STATUS1_100BASETX:
++ phydev->speed = SPEED_100;
++ config_reg = VEND1_GLOBAL_CFG_100M;
++ break;
++ case MDIO_AN_TX_VEND_STATUS1_1000BASET:
++ phydev->speed = SPEED_1000;
++ config_reg = VEND1_GLOBAL_CFG_1G;
++ break;
++ case MDIO_AN_TX_VEND_STATUS1_2500BASET:
++ phydev->speed = SPEED_2500;
++ config_reg = VEND1_GLOBAL_CFG_2_5G;
++ break;
++ case MDIO_AN_TX_VEND_STATUS1_5000BASET:
++ phydev->speed = SPEED_5000;
++ config_reg = VEND1_GLOBAL_CFG_5G;
++ break;
++ case MDIO_AN_TX_VEND_STATUS1_10GBASET:
++ phydev->speed = SPEED_10000;
++ config_reg = VEND1_GLOBAL_CFG_10G;
++ break;
++ default:
++ phydev->speed = SPEED_UNKNOWN;
++ return 0;
++ }
++
++ val = phy_read_mmd(phydev, MDIO_MMD_VEND1, config_reg);
++ if (val < 0)
++ return val;
++
++ if (FIELD_GET(VEND1_GLOBAL_CFG_RATE_ADAPT, val) ==
++ VEND1_GLOBAL_CFG_RATE_ADAPT_PAUSE)
++ phydev->rate_matching = RATE_MATCH_PAUSE;
++ else
++ phydev->rate_matching = RATE_MATCH_NONE;
++
++ return 0;
++}
++
++static int aqr107_read_status(struct phy_device *phydev)
++{
++ int val, ret;
++
++ ret = aqr_read_status(phydev);
++ if (ret)
++ return ret;
++
++ if (!phydev->link || phydev->autoneg == AUTONEG_DISABLE)
++ return 0;
++
++ val = phy_read_mmd(phydev, MDIO_MMD_PHYXS, MDIO_PHYXS_VEND_IF_STATUS);
++ if (val < 0)
++ return val;
++
++ switch (FIELD_GET(MDIO_PHYXS_VEND_IF_STATUS_TYPE_MASK, val)) {
++ case MDIO_PHYXS_VEND_IF_STATUS_TYPE_KR:
++ phydev->interface = PHY_INTERFACE_MODE_10GKR;
++ break;
++ case MDIO_PHYXS_VEND_IF_STATUS_TYPE_KX:
++ phydev->interface = PHY_INTERFACE_MODE_1000BASEKX;
++ break;
++ case MDIO_PHYXS_VEND_IF_STATUS_TYPE_XFI:
++ phydev->interface = PHY_INTERFACE_MODE_10GBASER;
++ break;
++ case MDIO_PHYXS_VEND_IF_STATUS_TYPE_USXGMII:
++ phydev->interface = PHY_INTERFACE_MODE_USXGMII;
++ break;
++ case MDIO_PHYXS_VEND_IF_STATUS_TYPE_XAUI:
++ phydev->interface = PHY_INTERFACE_MODE_XAUI;
++ break;
++ case MDIO_PHYXS_VEND_IF_STATUS_TYPE_SGMII:
++ phydev->interface = PHY_INTERFACE_MODE_SGMII;
++ break;
++ case MDIO_PHYXS_VEND_IF_STATUS_TYPE_RXAUI:
++ phydev->interface = PHY_INTERFACE_MODE_RXAUI;
++ break;
++ case MDIO_PHYXS_VEND_IF_STATUS_TYPE_OCSGMII:
++ phydev->interface = PHY_INTERFACE_MODE_2500BASEX;
++ break;
++ default:
++ phydev->interface = PHY_INTERFACE_MODE_NA;
++ break;
++ }
++
++ /* Read possibly downshifted rate from vendor register */
++ return aqr107_read_rate(phydev);
++}
++
++static int aqr107_get_downshift(struct phy_device *phydev, u8 *data)
++{
++ int val, cnt, enable;
++
++ val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_VEND_PROV);
++ if (val < 0)
++ return val;
++
++ enable = FIELD_GET(MDIO_AN_VEND_PROV_DOWNSHIFT_EN, val);
++ cnt = FIELD_GET(MDIO_AN_VEND_PROV_DOWNSHIFT_MASK, val);
++
++ *data = enable && cnt ? cnt : DOWNSHIFT_DEV_DISABLE;
++
++ return 0;
++}
++
++static int aqr107_set_downshift(struct phy_device *phydev, u8 cnt)
++{
++ int val = 0;
++
++ if (!FIELD_FIT(MDIO_AN_VEND_PROV_DOWNSHIFT_MASK, cnt))
++ return -E2BIG;
++
++ if (cnt != DOWNSHIFT_DEV_DISABLE) {
++ val = MDIO_AN_VEND_PROV_DOWNSHIFT_EN;
++ val |= FIELD_PREP(MDIO_AN_VEND_PROV_DOWNSHIFT_MASK, cnt);
++ }
++
++ return phy_modify_mmd(phydev, MDIO_MMD_AN, MDIO_AN_VEND_PROV,
++ MDIO_AN_VEND_PROV_DOWNSHIFT_EN |
++ MDIO_AN_VEND_PROV_DOWNSHIFT_MASK, val);
++}
++
++static int aqr107_get_tunable(struct phy_device *phydev,
++ struct ethtool_tunable *tuna, void *data)
++{
++ switch (tuna->id) {
++ case ETHTOOL_PHY_DOWNSHIFT:
++ return aqr107_get_downshift(phydev, data);
++ default:
++ return -EOPNOTSUPP;
++ }
++}
++
++static int aqr107_set_tunable(struct phy_device *phydev,
++ struct ethtool_tunable *tuna, const void *data)
++{
++ switch (tuna->id) {
++ case ETHTOOL_PHY_DOWNSHIFT:
++ return aqr107_set_downshift(phydev, *(const u8 *)data);
++ default:
++ return -EOPNOTSUPP;
++ }
++}
++
++/* If we configure settings whilst firmware is still initializing the chip,
++ * then these settings may be overwritten. Therefore make sure chip
++ * initialization has completed. Use presence of the firmware ID as
++ * indicator for initialization having completed.
++ * The chip also provides a "reset completed" bit, but it's cleared after
++ * read. Therefore function would time out if called again.
++ */
++static int aqr107_wait_reset_complete(struct phy_device *phydev)
++{
++ int val;
++
++ return phy_read_mmd_poll_timeout(phydev, MDIO_MMD_VEND1,
++ VEND1_GLOBAL_FW_ID, val, val != 0,
++ 20000, 2000000, false);
++}
++
++static void aqr107_chip_info(struct phy_device *phydev)
++{
++ u8 fw_major, fw_minor, build_id, prov_id;
++ int val;
++
++ val = phy_read_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_FW_ID);
++ if (val < 0)
++ return;
++
++ fw_major = FIELD_GET(VEND1_GLOBAL_FW_ID_MAJOR, val);
++ fw_minor = FIELD_GET(VEND1_GLOBAL_FW_ID_MINOR, val);
++
++ val = phy_read_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_RSVD_STAT1);
++ if (val < 0)
++ return;
++
++ build_id = FIELD_GET(VEND1_GLOBAL_RSVD_STAT1_FW_BUILD_ID, val);
++ prov_id = FIELD_GET(VEND1_GLOBAL_RSVD_STAT1_PROV_ID, val);
++
++ phydev_dbg(phydev, "FW %u.%u, Build %u, Provisioning %u\n",
++ fw_major, fw_minor, build_id, prov_id);
++}
++
++static int aqr107_config_init(struct phy_device *phydev)
++{
++ int ret;
++
++ /* Check that the PHY interface type is compatible */
++ if (phydev->interface != PHY_INTERFACE_MODE_SGMII &&
++ phydev->interface != PHY_INTERFACE_MODE_1000BASEKX &&
++ phydev->interface != PHY_INTERFACE_MODE_2500BASEX &&
++ phydev->interface != PHY_INTERFACE_MODE_XGMII &&
++ phydev->interface != PHY_INTERFACE_MODE_USXGMII &&
++ phydev->interface != PHY_INTERFACE_MODE_10GKR &&
++ phydev->interface != PHY_INTERFACE_MODE_10GBASER &&
++ phydev->interface != PHY_INTERFACE_MODE_XAUI &&
++ phydev->interface != PHY_INTERFACE_MODE_RXAUI)
++ return -ENODEV;
++
++ WARN(phydev->interface == PHY_INTERFACE_MODE_XGMII,
++ "Your devicetree is out of date, please update it. The AQR107 family doesn't support XGMII, maybe you mean USXGMII.\n");
++
++ ret = aqr107_wait_reset_complete(phydev);
++ if (!ret)
++ aqr107_chip_info(phydev);
++
++ return aqr107_set_downshift(phydev, MDIO_AN_VEND_PROV_DOWNSHIFT_DFLT);
++}
++
++static int aqcs109_config_init(struct phy_device *phydev)
++{
++ int ret;
++
++ /* Check that the PHY interface type is compatible */
++ if (phydev->interface != PHY_INTERFACE_MODE_SGMII &&
++ phydev->interface != PHY_INTERFACE_MODE_2500BASEX)
++ return -ENODEV;
++
++ ret = aqr107_wait_reset_complete(phydev);
++ if (!ret)
++ aqr107_chip_info(phydev);
++
++ /* AQCS109 belongs to a chip family partially supporting 10G and 5G.
++ * PMA speed ability bits are the same for all members of the family,
++ * AQCS109 however supports speeds up to 2.5G only.
++ */
++ ret = phy_set_max_speed(phydev, SPEED_2500);
++ if (ret)
++ return ret;
++
++ return aqr107_set_downshift(phydev, MDIO_AN_VEND_PROV_DOWNSHIFT_DFLT);
++}
++
++static void aqr107_link_change_notify(struct phy_device *phydev)
++{
++ u8 fw_major, fw_minor;
++ bool downshift, short_reach, afr;
++ int mode, val;
++
++ if (phydev->state != PHY_RUNNING || phydev->autoneg == AUTONEG_DISABLE)
++ return;
++
++ val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_RX_LP_STAT1);
++ /* call failed or link partner is no Aquantia PHY */
++ if (val < 0 || !(val & MDIO_AN_RX_LP_STAT1_AQ_PHY))
++ return;
++
++ short_reach = val & MDIO_AN_RX_LP_STAT1_SHORT_REACH;
++ downshift = val & MDIO_AN_RX_LP_STAT1_AQRATE_DOWNSHIFT;
++
++ val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_RX_LP_STAT4);
++ if (val < 0)
++ return;
++
++ fw_major = FIELD_GET(MDIO_AN_RX_LP_STAT4_FW_MAJOR, val);
++ fw_minor = FIELD_GET(MDIO_AN_RX_LP_STAT4_FW_MINOR, val);
++
++ val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_RX_VEND_STAT3);
++ if (val < 0)
++ return;
++
++ afr = val & MDIO_AN_RX_VEND_STAT3_AFR;
++
++ phydev_dbg(phydev, "Link partner is Aquantia PHY, FW %u.%u%s%s%s\n",
++ fw_major, fw_minor,
++ short_reach ? ", short reach mode" : "",
++ downshift ? ", fast-retrain downshift advertised" : "",
++ afr ? ", fast reframe advertised" : "");
++
++ val = phy_read_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_RSVD_STAT9);
++ if (val < 0)
++ return;
++
++ mode = FIELD_GET(VEND1_GLOBAL_RSVD_STAT9_MODE, val);
++ if (mode == VEND1_GLOBAL_RSVD_STAT9_1000BT2)
++ phydev_info(phydev, "Aquantia 1000Base-T2 mode active\n");
++}
++
++static int aqr107_wait_processor_intensive_op(struct phy_device *phydev)
++{
++ int val, err;
++
++ /* The datasheet notes to wait at least 1ms after issuing a
++ * processor intensive operation before checking.
++ * We cannot use the 'sleep_before_read' parameter of read_poll_timeout
++ * because that just determines the maximum time slept, not the minimum.
++ */
++ usleep_range(1000, 5000);
++
++ err = phy_read_mmd_poll_timeout(phydev, MDIO_MMD_VEND1,
++ VEND1_GLOBAL_GEN_STAT2, val,
++ !(val & VEND1_GLOBAL_GEN_STAT2_OP_IN_PROG),
++ AQR107_OP_IN_PROG_SLEEP,
++ AQR107_OP_IN_PROG_TIMEOUT, false);
++ if (err) {
++ phydev_err(phydev, "timeout: processor-intensive MDIO operation\n");
++ return err;
++ }
++
++ return 0;
++}
++
++static int aqr107_get_rate_matching(struct phy_device *phydev,
++ phy_interface_t iface)
++{
++ if (iface == PHY_INTERFACE_MODE_10GBASER ||
++ iface == PHY_INTERFACE_MODE_2500BASEX ||
++ iface == PHY_INTERFACE_MODE_NA)
++ return RATE_MATCH_PAUSE;
++ return RATE_MATCH_NONE;
++}
++
++static int aqr107_suspend(struct phy_device *phydev)
++{
++ int err;
++
++ err = phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, MDIO_CTRL1,
++ MDIO_CTRL1_LPOWER);
++ if (err)
++ return err;
++
++ return aqr107_wait_processor_intensive_op(phydev);
++}
++
++static int aqr107_resume(struct phy_device *phydev)
++{
++ int err;
++
++ err = phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MDIO_CTRL1,
++ MDIO_CTRL1_LPOWER);
++ if (err)
++ return err;
++
++ return aqr107_wait_processor_intensive_op(phydev);
++}
++
++static int aqr107_probe(struct phy_device *phydev)
++{
++ phydev->priv = devm_kzalloc(&phydev->mdio.dev,
++ sizeof(struct aqr107_priv), GFP_KERNEL);
++ if (!phydev->priv)
++ return -ENOMEM;
++
++ return aqr_hwmon_probe(phydev);
++}
++
++static struct phy_driver aqr_driver[] = {
++{
++ PHY_ID_MATCH_MODEL(PHY_ID_AQ1202),
++ .name = "Aquantia AQ1202",
++ .config_aneg = aqr_config_aneg,
++ .config_intr = aqr_config_intr,
++ .handle_interrupt = aqr_handle_interrupt,
++ .read_status = aqr_read_status,
++},
++{
++ PHY_ID_MATCH_MODEL(PHY_ID_AQ2104),
++ .name = "Aquantia AQ2104",
++ .config_aneg = aqr_config_aneg,
++ .config_intr = aqr_config_intr,
++ .handle_interrupt = aqr_handle_interrupt,
++ .read_status = aqr_read_status,
++},
++{
++ PHY_ID_MATCH_MODEL(PHY_ID_AQR105),
++ .name = "Aquantia AQR105",
++ .config_aneg = aqr_config_aneg,
++ .config_intr = aqr_config_intr,
++ .handle_interrupt = aqr_handle_interrupt,
++ .read_status = aqr_read_status,
++ .suspend = aqr107_suspend,
++ .resume = aqr107_resume,
++},
++{
++ PHY_ID_MATCH_MODEL(PHY_ID_AQR106),
++ .name = "Aquantia AQR106",
++ .config_aneg = aqr_config_aneg,
++ .config_intr = aqr_config_intr,
++ .handle_interrupt = aqr_handle_interrupt,
++ .read_status = aqr_read_status,
++},
++{
++ PHY_ID_MATCH_MODEL(PHY_ID_AQR107),
++ .name = "Aquantia AQR107",
++ .probe = aqr107_probe,
++ .get_rate_matching = aqr107_get_rate_matching,
++ .config_init = aqr107_config_init,
++ .config_aneg = aqr_config_aneg,
++ .config_intr = aqr_config_intr,
++ .handle_interrupt = aqr_handle_interrupt,
++ .read_status = aqr107_read_status,
++ .get_tunable = aqr107_get_tunable,
++ .set_tunable = aqr107_set_tunable,
++ .suspend = aqr107_suspend,
++ .resume = aqr107_resume,
++ .get_sset_count = aqr107_get_sset_count,
++ .get_strings = aqr107_get_strings,
++ .get_stats = aqr107_get_stats,
++ .link_change_notify = aqr107_link_change_notify,
++},
++{
++ PHY_ID_MATCH_MODEL(PHY_ID_AQCS109),
++ .name = "Aquantia AQCS109",
++ .probe = aqr107_probe,
++ .get_rate_matching = aqr107_get_rate_matching,
++ .config_init = aqcs109_config_init,
++ .config_aneg = aqr_config_aneg,
++ .config_intr = aqr_config_intr,
++ .handle_interrupt = aqr_handle_interrupt,
++ .read_status = aqr107_read_status,
++ .get_tunable = aqr107_get_tunable,
++ .set_tunable = aqr107_set_tunable,
++ .suspend = aqr107_suspend,
++ .resume = aqr107_resume,
++ .get_sset_count = aqr107_get_sset_count,
++ .get_strings = aqr107_get_strings,
++ .get_stats = aqr107_get_stats,
++ .link_change_notify = aqr107_link_change_notify,
++},
++{
++ PHY_ID_MATCH_MODEL(PHY_ID_AQR405),
++ .name = "Aquantia AQR405",
++ .config_aneg = aqr_config_aneg,
++ .config_intr = aqr_config_intr,
++ .handle_interrupt = aqr_handle_interrupt,
++ .read_status = aqr_read_status,
++},
++{
++ PHY_ID_MATCH_MODEL(PHY_ID_AQR113C),
++ .name = "Aquantia AQR113C",
++ .probe = aqr107_probe,
++ .get_rate_matching = aqr107_get_rate_matching,
++ .config_init = aqr107_config_init,
++ .config_aneg = aqr_config_aneg,
++ .config_intr = aqr_config_intr,
++ .handle_interrupt = aqr_handle_interrupt,
++ .read_status = aqr107_read_status,
++ .get_tunable = aqr107_get_tunable,
++ .set_tunable = aqr107_set_tunable,
++ .suspend = aqr107_suspend,
++ .resume = aqr107_resume,
++ .get_sset_count = aqr107_get_sset_count,
++ .get_strings = aqr107_get_strings,
++ .get_stats = aqr107_get_stats,
++ .link_change_notify = aqr107_link_change_notify,
++},
++};
++
++module_phy_driver(aqr_driver);
++
++static struct mdio_device_id __maybe_unused aqr_tbl[] = {
++ { PHY_ID_MATCH_MODEL(PHY_ID_AQ1202) },
++ { PHY_ID_MATCH_MODEL(PHY_ID_AQ2104) },
++ { PHY_ID_MATCH_MODEL(PHY_ID_AQR105) },
++ { PHY_ID_MATCH_MODEL(PHY_ID_AQR106) },
++ { PHY_ID_MATCH_MODEL(PHY_ID_AQR107) },
++ { PHY_ID_MATCH_MODEL(PHY_ID_AQCS109) },
++ { PHY_ID_MATCH_MODEL(PHY_ID_AQR405) },
++ { PHY_ID_MATCH_MODEL(PHY_ID_AQR113C) },
++ { }
++};
++
++MODULE_DEVICE_TABLE(mdio, aqr_tbl);
++
++MODULE_DESCRIPTION("Aquantia PHY driver");
++MODULE_AUTHOR("Shaohui Xie <Shaohui.Xie at freescale.com>");
++MODULE_LICENSE("GPL v2");
+--- a/drivers/net/phy/aquantia_hwmon.c
++++ /dev/null
+@@ -1,250 +0,0 @@
+-// SPDX-License-Identifier: GPL-2.0
+-/* HWMON driver for Aquantia PHY
+- *
+- * Author: Nikita Yushchenko <nikita.yoush at cogentembedded.com>
+- * Author: Andrew Lunn <andrew at lunn.ch>
+- * Author: Heiner Kallweit <hkallweit1 at gmail.com>
+- */
+-
+-#include <linux/phy.h>
+-#include <linux/device.h>
+-#include <linux/ctype.h>
+-#include <linux/hwmon.h>
+-
+-#include "aquantia.h"
+-
+-/* Vendor specific 1, MDIO_MMD_VEND2 */
+-#define VEND1_THERMAL_PROV_HIGH_TEMP_FAIL 0xc421
+-#define VEND1_THERMAL_PROV_LOW_TEMP_FAIL 0xc422
+-#define VEND1_THERMAL_PROV_HIGH_TEMP_WARN 0xc423
+-#define VEND1_THERMAL_PROV_LOW_TEMP_WARN 0xc424
+-#define VEND1_THERMAL_STAT1 0xc820
+-#define VEND1_THERMAL_STAT2 0xc821
+-#define VEND1_THERMAL_STAT2_VALID BIT(0)
+-#define VEND1_GENERAL_STAT1 0xc830
+-#define VEND1_GENERAL_STAT1_HIGH_TEMP_FAIL BIT(14)
+-#define VEND1_GENERAL_STAT1_LOW_TEMP_FAIL BIT(13)
+-#define VEND1_GENERAL_STAT1_HIGH_TEMP_WARN BIT(12)
+-#define VEND1_GENERAL_STAT1_LOW_TEMP_WARN BIT(11)
+-
+-#if IS_REACHABLE(CONFIG_HWMON)
+-
+-static umode_t aqr_hwmon_is_visible(const void *data,
+- enum hwmon_sensor_types type,
+- u32 attr, int channel)
+-{
+- if (type != hwmon_temp)
+- return 0;
+-
+- switch (attr) {
+- case hwmon_temp_input:
+- case hwmon_temp_min_alarm:
+- case hwmon_temp_max_alarm:
+- case hwmon_temp_lcrit_alarm:
+- case hwmon_temp_crit_alarm:
+- return 0444;
+- case hwmon_temp_min:
+- case hwmon_temp_max:
+- case hwmon_temp_lcrit:
+- case hwmon_temp_crit:
+- return 0644;
+- default:
+- return 0;
+- }
+-}
+-
+-static int aqr_hwmon_get(struct phy_device *phydev, int reg, long *value)
+-{
+- int temp = phy_read_mmd(phydev, MDIO_MMD_VEND1, reg);
+-
+- if (temp < 0)
+- return temp;
+-
+- /* 16 bit value is 2's complement with LSB = 1/256th degree Celsius */
+- *value = (s16)temp * 1000 / 256;
+-
+- return 0;
+-}
+-
+-static int aqr_hwmon_set(struct phy_device *phydev, int reg, long value)
+-{
+- int temp;
+-
+- if (value >= 128000 || value < -128000)
+- return -ERANGE;
+-
+- temp = value * 256 / 1000;
+-
+- /* temp is in s16 range and we're interested in lower 16 bits only */
+- return phy_write_mmd(phydev, MDIO_MMD_VEND1, reg, (u16)temp);
+-}
+-
+-static int aqr_hwmon_test_bit(struct phy_device *phydev, int reg, int bit)
+-{
+- int val = phy_read_mmd(phydev, MDIO_MMD_VEND1, reg);
+-
+- if (val < 0)
+- return val;
+-
+- return !!(val & bit);
+-}
+-
+-static int aqr_hwmon_status1(struct phy_device *phydev, int bit, long *value)
+-{
+- int val = aqr_hwmon_test_bit(phydev, VEND1_GENERAL_STAT1, bit);
+-
+- if (val < 0)
+- return val;
+-
+- *value = val;
+-
+- return 0;
+-}
+-
+-static int aqr_hwmon_read(struct device *dev, enum hwmon_sensor_types type,
+- u32 attr, int channel, long *value)
+-{
+- struct phy_device *phydev = dev_get_drvdata(dev);
+- int reg;
+-
+- if (type != hwmon_temp)
+- return -EOPNOTSUPP;
+-
+- switch (attr) {
+- case hwmon_temp_input:
+- reg = aqr_hwmon_test_bit(phydev, VEND1_THERMAL_STAT2,
+- VEND1_THERMAL_STAT2_VALID);
+- if (reg < 0)
+- return reg;
+- if (!reg)
+- return -EBUSY;
+-
+- return aqr_hwmon_get(phydev, VEND1_THERMAL_STAT1, value);
+-
+- case hwmon_temp_lcrit:
+- return aqr_hwmon_get(phydev, VEND1_THERMAL_PROV_LOW_TEMP_FAIL,
+- value);
+- case hwmon_temp_min:
+- return aqr_hwmon_get(phydev, VEND1_THERMAL_PROV_LOW_TEMP_WARN,
+- value);
+- case hwmon_temp_max:
+- return aqr_hwmon_get(phydev, VEND1_THERMAL_PROV_HIGH_TEMP_WARN,
+- value);
+- case hwmon_temp_crit:
+- return aqr_hwmon_get(phydev, VEND1_THERMAL_PROV_HIGH_TEMP_FAIL,
+- value);
+- case hwmon_temp_lcrit_alarm:
+- return aqr_hwmon_status1(phydev,
+- VEND1_GENERAL_STAT1_LOW_TEMP_FAIL,
+- value);
+- case hwmon_temp_min_alarm:
+- return aqr_hwmon_status1(phydev,
+- VEND1_GENERAL_STAT1_LOW_TEMP_WARN,
+- value);
+- case hwmon_temp_max_alarm:
+- return aqr_hwmon_status1(phydev,
+- VEND1_GENERAL_STAT1_HIGH_TEMP_WARN,
+- value);
+- case hwmon_temp_crit_alarm:
+- return aqr_hwmon_status1(phydev,
+- VEND1_GENERAL_STAT1_HIGH_TEMP_FAIL,
+- value);
+- default:
+- return -EOPNOTSUPP;
+- }
+-}
+-
+-static int aqr_hwmon_write(struct device *dev, enum hwmon_sensor_types type,
+- u32 attr, int channel, long value)
+-{
+- struct phy_device *phydev = dev_get_drvdata(dev);
+-
+- if (type != hwmon_temp)
+- return -EOPNOTSUPP;
+-
+- switch (attr) {
+- case hwmon_temp_lcrit:
+- return aqr_hwmon_set(phydev, VEND1_THERMAL_PROV_LOW_TEMP_FAIL,
+- value);
+- case hwmon_temp_min:
+- return aqr_hwmon_set(phydev, VEND1_THERMAL_PROV_LOW_TEMP_WARN,
+- value);
+- case hwmon_temp_max:
+- return aqr_hwmon_set(phydev, VEND1_THERMAL_PROV_HIGH_TEMP_WARN,
+- value);
+- case hwmon_temp_crit:
+- return aqr_hwmon_set(phydev, VEND1_THERMAL_PROV_HIGH_TEMP_FAIL,
+- value);
+- default:
+- return -EOPNOTSUPP;
+- }
+-}
+-
+-static const struct hwmon_ops aqr_hwmon_ops = {
+- .is_visible = aqr_hwmon_is_visible,
+- .read = aqr_hwmon_read,
+- .write = aqr_hwmon_write,
+-};
+-
+-static u32 aqr_hwmon_chip_config[] = {
+- HWMON_C_REGISTER_TZ,
+- 0,
+-};
+-
+-static const struct hwmon_channel_info aqr_hwmon_chip = {
+- .type = hwmon_chip,
+- .config = aqr_hwmon_chip_config,
+-};
+-
+-static u32 aqr_hwmon_temp_config[] = {
+- HWMON_T_INPUT |
+- HWMON_T_MAX | HWMON_T_MIN |
+- HWMON_T_MAX_ALARM | HWMON_T_MIN_ALARM |
+- HWMON_T_CRIT | HWMON_T_LCRIT |
+- HWMON_T_CRIT_ALARM | HWMON_T_LCRIT_ALARM,
+- 0,
+-};
+-
+-static const struct hwmon_channel_info aqr_hwmon_temp = {
+- .type = hwmon_temp,
+- .config = aqr_hwmon_temp_config,
+-};
+-
+-static const struct hwmon_channel_info *aqr_hwmon_info[] = {
+- &aqr_hwmon_chip,
+- &aqr_hwmon_temp,
+- NULL,
+-};
+-
+-static const struct hwmon_chip_info aqr_hwmon_chip_info = {
+- .ops = &aqr_hwmon_ops,
+- .info = aqr_hwmon_info,
+-};
+-
+-int aqr_hwmon_probe(struct phy_device *phydev)
+-{
+- struct device *dev = &phydev->mdio.dev;
+- struct device *hwmon_dev;
+- char *hwmon_name;
+- int i, j;
+-
+- hwmon_name = devm_kstrdup(dev, dev_name(dev), GFP_KERNEL);
+- if (!hwmon_name)
+- return -ENOMEM;
+-
+- for (i = j = 0; hwmon_name[i]; i++) {
+- if (isalnum(hwmon_name[i])) {
+- if (i != j)
+- hwmon_name[j] = hwmon_name[i];
+- j++;
+- }
+- }
+- hwmon_name[j] = '\0';
+-
+- hwmon_dev = devm_hwmon_device_register_with_info(dev, hwmon_name,
+- phydev, &aqr_hwmon_chip_info, NULL);
+-
+- return PTR_ERR_OR_ZERO(hwmon_dev);
+-}
+-
+-#endif
+--- a/drivers/net/phy/aquantia_main.c
++++ /dev/null
+@@ -1,844 +0,0 @@
+-// SPDX-License-Identifier: GPL-2.0
+-/*
+- * Driver for Aquantia PHY
+- *
+- * Author: Shaohui Xie <Shaohui.Xie at freescale.com>
+- *
+- * Copyright 2015 Freescale Semiconductor, Inc.
+- */
+-
+-#include <linux/kernel.h>
+-#include <linux/module.h>
+-#include <linux/delay.h>
+-#include <linux/bitfield.h>
+-#include <linux/phy.h>
+-
+-#include "aquantia.h"
+-
+-#define PHY_ID_AQ1202 0x03a1b445
+-#define PHY_ID_AQ2104 0x03a1b460
+-#define PHY_ID_AQR105 0x03a1b4a2
+-#define PHY_ID_AQR106 0x03a1b4d0
+-#define PHY_ID_AQR107 0x03a1b4e0
+-#define PHY_ID_AQCS109 0x03a1b5c2
+-#define PHY_ID_AQR405 0x03a1b4b0
+-#define PHY_ID_AQR113C 0x31c31c12
+-
+-#define MDIO_PHYXS_VEND_IF_STATUS 0xe812
+-#define MDIO_PHYXS_VEND_IF_STATUS_TYPE_MASK GENMASK(7, 3)
+-#define MDIO_PHYXS_VEND_IF_STATUS_TYPE_KR 0
+-#define MDIO_PHYXS_VEND_IF_STATUS_TYPE_KX 1
+-#define MDIO_PHYXS_VEND_IF_STATUS_TYPE_XFI 2
+-#define MDIO_PHYXS_VEND_IF_STATUS_TYPE_USXGMII 3
+-#define MDIO_PHYXS_VEND_IF_STATUS_TYPE_XAUI 4
+-#define MDIO_PHYXS_VEND_IF_STATUS_TYPE_SGMII 6
+-#define MDIO_PHYXS_VEND_IF_STATUS_TYPE_RXAUI 7
+-#define MDIO_PHYXS_VEND_IF_STATUS_TYPE_OCSGMII 10
+-
+-#define MDIO_AN_VEND_PROV 0xc400
+-#define MDIO_AN_VEND_PROV_1000BASET_FULL BIT(15)
+-#define MDIO_AN_VEND_PROV_1000BASET_HALF BIT(14)
+-#define MDIO_AN_VEND_PROV_5000BASET_FULL BIT(11)
+-#define MDIO_AN_VEND_PROV_2500BASET_FULL BIT(10)
+-#define MDIO_AN_VEND_PROV_DOWNSHIFT_EN BIT(4)
+-#define MDIO_AN_VEND_PROV_DOWNSHIFT_MASK GENMASK(3, 0)
+-#define MDIO_AN_VEND_PROV_DOWNSHIFT_DFLT 4
+-
+-#define MDIO_AN_TX_VEND_STATUS1 0xc800
+-#define MDIO_AN_TX_VEND_STATUS1_RATE_MASK GENMASK(3, 1)
+-#define MDIO_AN_TX_VEND_STATUS1_10BASET 0
+-#define MDIO_AN_TX_VEND_STATUS1_100BASETX 1
+-#define MDIO_AN_TX_VEND_STATUS1_1000BASET 2
+-#define MDIO_AN_TX_VEND_STATUS1_10GBASET 3
+-#define MDIO_AN_TX_VEND_STATUS1_2500BASET 4
+-#define MDIO_AN_TX_VEND_STATUS1_5000BASET 5
+-#define MDIO_AN_TX_VEND_STATUS1_FULL_DUPLEX BIT(0)
+-
+-#define MDIO_AN_TX_VEND_INT_STATUS1 0xcc00
+-#define MDIO_AN_TX_VEND_INT_STATUS1_DOWNSHIFT BIT(1)
+-
+-#define MDIO_AN_TX_VEND_INT_STATUS2 0xcc01
+-#define MDIO_AN_TX_VEND_INT_STATUS2_MASK BIT(0)
+-
+-#define MDIO_AN_TX_VEND_INT_MASK2 0xd401
+-#define MDIO_AN_TX_VEND_INT_MASK2_LINK BIT(0)
+-
+-#define MDIO_AN_RX_LP_STAT1 0xe820
+-#define MDIO_AN_RX_LP_STAT1_1000BASET_FULL BIT(15)
+-#define MDIO_AN_RX_LP_STAT1_1000BASET_HALF BIT(14)
+-#define MDIO_AN_RX_LP_STAT1_SHORT_REACH BIT(13)
+-#define MDIO_AN_RX_LP_STAT1_AQRATE_DOWNSHIFT BIT(12)
+-#define MDIO_AN_RX_LP_STAT1_AQ_PHY BIT(2)
+-
+-#define MDIO_AN_RX_LP_STAT4 0xe823
+-#define MDIO_AN_RX_LP_STAT4_FW_MAJOR GENMASK(15, 8)
+-#define MDIO_AN_RX_LP_STAT4_FW_MINOR GENMASK(7, 0)
+-
+-#define MDIO_AN_RX_VEND_STAT3 0xe832
+-#define MDIO_AN_RX_VEND_STAT3_AFR BIT(0)
+-
+-/* MDIO_MMD_C22EXT */
+-#define MDIO_C22EXT_STAT_SGMII_RX_GOOD_FRAMES 0xd292
+-#define MDIO_C22EXT_STAT_SGMII_RX_BAD_FRAMES 0xd294
+-#define MDIO_C22EXT_STAT_SGMII_RX_FALSE_CARRIER 0xd297
+-#define MDIO_C22EXT_STAT_SGMII_TX_GOOD_FRAMES 0xd313
+-#define MDIO_C22EXT_STAT_SGMII_TX_BAD_FRAMES 0xd315
+-#define MDIO_C22EXT_STAT_SGMII_TX_FALSE_CARRIER 0xd317
+-#define MDIO_C22EXT_STAT_SGMII_TX_COLLISIONS 0xd318
+-#define MDIO_C22EXT_STAT_SGMII_TX_LINE_COLLISIONS 0xd319
+-#define MDIO_C22EXT_STAT_SGMII_TX_FRAME_ALIGN_ERR 0xd31a
+-#define MDIO_C22EXT_STAT_SGMII_TX_RUNT_FRAMES 0xd31b
+-
+-/* Vendor specific 1, MDIO_MMD_VEND1 */
+-#define VEND1_GLOBAL_FW_ID 0x0020
+-#define VEND1_GLOBAL_FW_ID_MAJOR GENMASK(15, 8)
+-#define VEND1_GLOBAL_FW_ID_MINOR GENMASK(7, 0)
+-
+-#define VEND1_GLOBAL_GEN_STAT2 0xc831
+-#define VEND1_GLOBAL_GEN_STAT2_OP_IN_PROG BIT(15)
+-
+-/* The following registers all have similar layouts; first the registers... */
+-#define VEND1_GLOBAL_CFG_10M 0x0310
+-#define VEND1_GLOBAL_CFG_100M 0x031b
+-#define VEND1_GLOBAL_CFG_1G 0x031c
+-#define VEND1_GLOBAL_CFG_2_5G 0x031d
+-#define VEND1_GLOBAL_CFG_5G 0x031e
+-#define VEND1_GLOBAL_CFG_10G 0x031f
+-/* ...and now the fields */
+-#define VEND1_GLOBAL_CFG_RATE_ADAPT GENMASK(8, 7)
+-#define VEND1_GLOBAL_CFG_RATE_ADAPT_NONE 0
+-#define VEND1_GLOBAL_CFG_RATE_ADAPT_USX 1
+-#define VEND1_GLOBAL_CFG_RATE_ADAPT_PAUSE 2
+-
+-#define VEND1_GLOBAL_RSVD_STAT1 0xc885
+-#define VEND1_GLOBAL_RSVD_STAT1_FW_BUILD_ID GENMASK(7, 4)
+-#define VEND1_GLOBAL_RSVD_STAT1_PROV_ID GENMASK(3, 0)
+-
+-#define VEND1_GLOBAL_RSVD_STAT9 0xc88d
+-#define VEND1_GLOBAL_RSVD_STAT9_MODE GENMASK(7, 0)
+-#define VEND1_GLOBAL_RSVD_STAT9_1000BT2 0x23
+-
+-#define VEND1_GLOBAL_INT_STD_STATUS 0xfc00
+-#define VEND1_GLOBAL_INT_VEND_STATUS 0xfc01
+-
+-#define VEND1_GLOBAL_INT_STD_MASK 0xff00
+-#define VEND1_GLOBAL_INT_STD_MASK_PMA1 BIT(15)
+-#define VEND1_GLOBAL_INT_STD_MASK_PMA2 BIT(14)
+-#define VEND1_GLOBAL_INT_STD_MASK_PCS1 BIT(13)
+-#define VEND1_GLOBAL_INT_STD_MASK_PCS2 BIT(12)
+-#define VEND1_GLOBAL_INT_STD_MASK_PCS3 BIT(11)
+-#define VEND1_GLOBAL_INT_STD_MASK_PHY_XS1 BIT(10)
+-#define VEND1_GLOBAL_INT_STD_MASK_PHY_XS2 BIT(9)
+-#define VEND1_GLOBAL_INT_STD_MASK_AN1 BIT(8)
+-#define VEND1_GLOBAL_INT_STD_MASK_AN2 BIT(7)
+-#define VEND1_GLOBAL_INT_STD_MASK_GBE BIT(6)
+-#define VEND1_GLOBAL_INT_STD_MASK_ALL BIT(0)
+-
+-#define VEND1_GLOBAL_INT_VEND_MASK 0xff01
+-#define VEND1_GLOBAL_INT_VEND_MASK_PMA BIT(15)
+-#define VEND1_GLOBAL_INT_VEND_MASK_PCS BIT(14)
+-#define VEND1_GLOBAL_INT_VEND_MASK_PHY_XS BIT(13)
+-#define VEND1_GLOBAL_INT_VEND_MASK_AN BIT(12)
+-#define VEND1_GLOBAL_INT_VEND_MASK_GBE BIT(11)
+-#define VEND1_GLOBAL_INT_VEND_MASK_GLOBAL1 BIT(2)
+-#define VEND1_GLOBAL_INT_VEND_MASK_GLOBAL2 BIT(1)
+-#define VEND1_GLOBAL_INT_VEND_MASK_GLOBAL3 BIT(0)
+-
+-/* Sleep and timeout for checking if the Processor-Intensive
+- * MDIO operation is finished
+- */
+-#define AQR107_OP_IN_PROG_SLEEP 1000
+-#define AQR107_OP_IN_PROG_TIMEOUT 100000
+-
+-struct aqr107_hw_stat {
+- const char *name;
+- int reg;
+- int size;
+-};
+-
+-#define SGMII_STAT(n, r, s) { n, MDIO_C22EXT_STAT_SGMII_ ## r, s }
+-static const struct aqr107_hw_stat aqr107_hw_stats[] = {
+- SGMII_STAT("sgmii_rx_good_frames", RX_GOOD_FRAMES, 26),
+- SGMII_STAT("sgmii_rx_bad_frames", RX_BAD_FRAMES, 26),
+- SGMII_STAT("sgmii_rx_false_carrier_events", RX_FALSE_CARRIER, 8),
+- SGMII_STAT("sgmii_tx_good_frames", TX_GOOD_FRAMES, 26),
+- SGMII_STAT("sgmii_tx_bad_frames", TX_BAD_FRAMES, 26),
+- SGMII_STAT("sgmii_tx_false_carrier_events", TX_FALSE_CARRIER, 8),
+- SGMII_STAT("sgmii_tx_collisions", TX_COLLISIONS, 8),
+- SGMII_STAT("sgmii_tx_line_collisions", TX_LINE_COLLISIONS, 8),
+- SGMII_STAT("sgmii_tx_frame_alignment_err", TX_FRAME_ALIGN_ERR, 16),
+- SGMII_STAT("sgmii_tx_runt_frames", TX_RUNT_FRAMES, 22),
+-};
+-#define AQR107_SGMII_STAT_SZ ARRAY_SIZE(aqr107_hw_stats)
+-
+-struct aqr107_priv {
+- u64 sgmii_stats[AQR107_SGMII_STAT_SZ];
+-};
+-
+-static int aqr107_get_sset_count(struct phy_device *phydev)
+-{
+- return AQR107_SGMII_STAT_SZ;
+-}
+-
+-static void aqr107_get_strings(struct phy_device *phydev, u8 *data)
+-{
+- int i;
+-
+- for (i = 0; i < AQR107_SGMII_STAT_SZ; i++)
+- strscpy(data + i * ETH_GSTRING_LEN, aqr107_hw_stats[i].name,
+- ETH_GSTRING_LEN);
+-}
+-
+-static u64 aqr107_get_stat(struct phy_device *phydev, int index)
+-{
+- const struct aqr107_hw_stat *stat = aqr107_hw_stats + index;
+- int len_l = min(stat->size, 16);
+- int len_h = stat->size - len_l;
+- u64 ret;
+- int val;
+-
+- val = phy_read_mmd(phydev, MDIO_MMD_C22EXT, stat->reg);
+- if (val < 0)
+- return U64_MAX;
+-
+- ret = val & GENMASK(len_l - 1, 0);
+- if (len_h) {
+- val = phy_read_mmd(phydev, MDIO_MMD_C22EXT, stat->reg + 1);
+- if (val < 0)
+- return U64_MAX;
+-
+- ret += (val & GENMASK(len_h - 1, 0)) << 16;
+- }
+-
+- return ret;
+-}
+-
+-static void aqr107_get_stats(struct phy_device *phydev,
+- struct ethtool_stats *stats, u64 *data)
+-{
+- struct aqr107_priv *priv = phydev->priv;
+- u64 val;
+- int i;
+-
+- for (i = 0; i < AQR107_SGMII_STAT_SZ; i++) {
+- val = aqr107_get_stat(phydev, i);
+- if (val == U64_MAX)
+- phydev_err(phydev, "Reading HW Statistics failed for %s\n",
+- aqr107_hw_stats[i].name);
+- else
+- priv->sgmii_stats[i] += val;
+-
+- data[i] = priv->sgmii_stats[i];
+- }
+-}
+-
+-static int aqr_config_aneg(struct phy_device *phydev)
+-{
+- bool changed = false;
+- u16 reg;
+- int ret;
+-
+- if (phydev->autoneg == AUTONEG_DISABLE)
+- return genphy_c45_pma_setup_forced(phydev);
+-
+- ret = genphy_c45_an_config_aneg(phydev);
+- if (ret < 0)
+- return ret;
+- if (ret > 0)
+- changed = true;
+-
+- /* Clause 45 has no standardized support for 1000BaseT, therefore
+- * use vendor registers for this mode.
+- */
+- reg = 0;
+- if (linkmode_test_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT,
+- phydev->advertising))
+- reg |= MDIO_AN_VEND_PROV_1000BASET_FULL;
+-
+- if (linkmode_test_bit(ETHTOOL_LINK_MODE_1000baseT_Half_BIT,
+- phydev->advertising))
+- reg |= MDIO_AN_VEND_PROV_1000BASET_HALF;
+-
+- /* Handle the case when the 2.5G and 5G speeds are not advertised */
+- if (linkmode_test_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT,
+- phydev->advertising))
+- reg |= MDIO_AN_VEND_PROV_2500BASET_FULL;
+-
+- if (linkmode_test_bit(ETHTOOL_LINK_MODE_5000baseT_Full_BIT,
+- phydev->advertising))
+- reg |= MDIO_AN_VEND_PROV_5000BASET_FULL;
+-
+- ret = phy_modify_mmd_changed(phydev, MDIO_MMD_AN, MDIO_AN_VEND_PROV,
+- MDIO_AN_VEND_PROV_1000BASET_HALF |
+- MDIO_AN_VEND_PROV_1000BASET_FULL |
+- MDIO_AN_VEND_PROV_2500BASET_FULL |
+- MDIO_AN_VEND_PROV_5000BASET_FULL, reg);
+- if (ret < 0)
+- return ret;
+- if (ret > 0)
+- changed = true;
+-
+- return genphy_c45_check_and_restart_aneg(phydev, changed);
+-}
+-
+-static int aqr_config_intr(struct phy_device *phydev)
+-{
+- bool en = phydev->interrupts == PHY_INTERRUPT_ENABLED;
+- int err;
+-
+- if (en) {
+- /* Clear any pending interrupts before enabling them */
+- err = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_TX_VEND_INT_STATUS2);
+- if (err < 0)
+- return err;
+- }
+-
+- err = phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_TX_VEND_INT_MASK2,
+- en ? MDIO_AN_TX_VEND_INT_MASK2_LINK : 0);
+- if (err < 0)
+- return err;
+-
+- err = phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_INT_STD_MASK,
+- en ? VEND1_GLOBAL_INT_STD_MASK_ALL : 0);
+- if (err < 0)
+- return err;
+-
+- err = phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_INT_VEND_MASK,
+- en ? VEND1_GLOBAL_INT_VEND_MASK_GLOBAL3 |
+- VEND1_GLOBAL_INT_VEND_MASK_AN : 0);
+- if (err < 0)
+- return err;
+-
+- if (!en) {
+- /* Clear any pending interrupts after we have disabled them */
+- err = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_TX_VEND_INT_STATUS2);
+- if (err < 0)
+- return err;
+- }
+-
+- return 0;
+-}
+-
+-static irqreturn_t aqr_handle_interrupt(struct phy_device *phydev)
+-{
+- int irq_status;
+-
+- irq_status = phy_read_mmd(phydev, MDIO_MMD_AN,
+- MDIO_AN_TX_VEND_INT_STATUS2);
+- if (irq_status < 0) {
+- phy_error(phydev);
+- return IRQ_NONE;
+- }
+-
+- if (!(irq_status & MDIO_AN_TX_VEND_INT_STATUS2_MASK))
+- return IRQ_NONE;
+-
+- phy_trigger_machine(phydev);
+-
+- return IRQ_HANDLED;
+-}
+-
+-static int aqr_read_status(struct phy_device *phydev)
+-{
+- int val;
+-
+- if (phydev->autoneg == AUTONEG_ENABLE) {
+- val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_RX_LP_STAT1);
+- if (val < 0)
+- return val;
+-
+- linkmode_mod_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT,
+- phydev->lp_advertising,
+- val & MDIO_AN_RX_LP_STAT1_1000BASET_FULL);
+- linkmode_mod_bit(ETHTOOL_LINK_MODE_1000baseT_Half_BIT,
+- phydev->lp_advertising,
+- val & MDIO_AN_RX_LP_STAT1_1000BASET_HALF);
+- }
+-
+- return genphy_c45_read_status(phydev);
+-}
+-
+-static int aqr107_read_rate(struct phy_device *phydev)
+-{
+- u32 config_reg;
+- int val;
+-
+- val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_TX_VEND_STATUS1);
+- if (val < 0)
+- return val;
+-
+- if (val & MDIO_AN_TX_VEND_STATUS1_FULL_DUPLEX)
+- phydev->duplex = DUPLEX_FULL;
+- else
+- phydev->duplex = DUPLEX_HALF;
+-
+- switch (FIELD_GET(MDIO_AN_TX_VEND_STATUS1_RATE_MASK, val)) {
+- case MDIO_AN_TX_VEND_STATUS1_10BASET:
+- phydev->speed = SPEED_10;
+- config_reg = VEND1_GLOBAL_CFG_10M;
+- break;
+- case MDIO_AN_TX_VEND_STATUS1_100BASETX:
+- phydev->speed = SPEED_100;
+- config_reg = VEND1_GLOBAL_CFG_100M;
+- break;
+- case MDIO_AN_TX_VEND_STATUS1_1000BASET:
+- phydev->speed = SPEED_1000;
+- config_reg = VEND1_GLOBAL_CFG_1G;
+- break;
+- case MDIO_AN_TX_VEND_STATUS1_2500BASET:
+- phydev->speed = SPEED_2500;
+- config_reg = VEND1_GLOBAL_CFG_2_5G;
+- break;
+- case MDIO_AN_TX_VEND_STATUS1_5000BASET:
+- phydev->speed = SPEED_5000;
+- config_reg = VEND1_GLOBAL_CFG_5G;
+- break;
+- case MDIO_AN_TX_VEND_STATUS1_10GBASET:
+- phydev->speed = SPEED_10000;
+- config_reg = VEND1_GLOBAL_CFG_10G;
+- break;
+- default:
+- phydev->speed = SPEED_UNKNOWN;
+- return 0;
+- }
+-
+- val = phy_read_mmd(phydev, MDIO_MMD_VEND1, config_reg);
+- if (val < 0)
+- return val;
+-
+- if (FIELD_GET(VEND1_GLOBAL_CFG_RATE_ADAPT, val) ==
+- VEND1_GLOBAL_CFG_RATE_ADAPT_PAUSE)
+- phydev->rate_matching = RATE_MATCH_PAUSE;
+- else
+- phydev->rate_matching = RATE_MATCH_NONE;
+-
+- return 0;
+-}
+-
+-static int aqr107_read_status(struct phy_device *phydev)
+-{
+- int val, ret;
+-
+- ret = aqr_read_status(phydev);
+- if (ret)
+- return ret;
+-
+- if (!phydev->link || phydev->autoneg == AUTONEG_DISABLE)
+- return 0;
+-
+- val = phy_read_mmd(phydev, MDIO_MMD_PHYXS, MDIO_PHYXS_VEND_IF_STATUS);
+- if (val < 0)
+- return val;
+-
+- switch (FIELD_GET(MDIO_PHYXS_VEND_IF_STATUS_TYPE_MASK, val)) {
+- case MDIO_PHYXS_VEND_IF_STATUS_TYPE_KR:
+- phydev->interface = PHY_INTERFACE_MODE_10GKR;
+- break;
+- case MDIO_PHYXS_VEND_IF_STATUS_TYPE_KX:
+- phydev->interface = PHY_INTERFACE_MODE_1000BASEKX;
+- break;
+- case MDIO_PHYXS_VEND_IF_STATUS_TYPE_XFI:
+- phydev->interface = PHY_INTERFACE_MODE_10GBASER;
+- break;
+- case MDIO_PHYXS_VEND_IF_STATUS_TYPE_USXGMII:
+- phydev->interface = PHY_INTERFACE_MODE_USXGMII;
+- break;
+- case MDIO_PHYXS_VEND_IF_STATUS_TYPE_XAUI:
+- phydev->interface = PHY_INTERFACE_MODE_XAUI;
+- break;
+- case MDIO_PHYXS_VEND_IF_STATUS_TYPE_SGMII:
+- phydev->interface = PHY_INTERFACE_MODE_SGMII;
+- break;
+- case MDIO_PHYXS_VEND_IF_STATUS_TYPE_RXAUI:
+- phydev->interface = PHY_INTERFACE_MODE_RXAUI;
+- break;
+- case MDIO_PHYXS_VEND_IF_STATUS_TYPE_OCSGMII:
+- phydev->interface = PHY_INTERFACE_MODE_2500BASEX;
+- break;
+- default:
+- phydev->interface = PHY_INTERFACE_MODE_NA;
+- break;
+- }
+-
+- /* Read possibly downshifted rate from vendor register */
+- return aqr107_read_rate(phydev);
+-}
+-
+-static int aqr107_get_downshift(struct phy_device *phydev, u8 *data)
+-{
+- int val, cnt, enable;
+-
+- val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_VEND_PROV);
+- if (val < 0)
+- return val;
+-
+- enable = FIELD_GET(MDIO_AN_VEND_PROV_DOWNSHIFT_EN, val);
+- cnt = FIELD_GET(MDIO_AN_VEND_PROV_DOWNSHIFT_MASK, val);
+-
+- *data = enable && cnt ? cnt : DOWNSHIFT_DEV_DISABLE;
+-
+- return 0;
+-}
+-
+-static int aqr107_set_downshift(struct phy_device *phydev, u8 cnt)
+-{
+- int val = 0;
+-
+- if (!FIELD_FIT(MDIO_AN_VEND_PROV_DOWNSHIFT_MASK, cnt))
+- return -E2BIG;
+-
+- if (cnt != DOWNSHIFT_DEV_DISABLE) {
+- val = MDIO_AN_VEND_PROV_DOWNSHIFT_EN;
+- val |= FIELD_PREP(MDIO_AN_VEND_PROV_DOWNSHIFT_MASK, cnt);
+- }
+-
+- return phy_modify_mmd(phydev, MDIO_MMD_AN, MDIO_AN_VEND_PROV,
+- MDIO_AN_VEND_PROV_DOWNSHIFT_EN |
+- MDIO_AN_VEND_PROV_DOWNSHIFT_MASK, val);
+-}
+-
+-static int aqr107_get_tunable(struct phy_device *phydev,
+- struct ethtool_tunable *tuna, void *data)
+-{
+- switch (tuna->id) {
+- case ETHTOOL_PHY_DOWNSHIFT:
+- return aqr107_get_downshift(phydev, data);
+- default:
+- return -EOPNOTSUPP;
+- }
+-}
+-
+-static int aqr107_set_tunable(struct phy_device *phydev,
+- struct ethtool_tunable *tuna, const void *data)
+-{
+- switch (tuna->id) {
+- case ETHTOOL_PHY_DOWNSHIFT:
+- return aqr107_set_downshift(phydev, *(const u8 *)data);
+- default:
+- return -EOPNOTSUPP;
+- }
+-}
+-
+-/* If we configure settings whilst firmware is still initializing the chip,
+- * then these settings may be overwritten. Therefore make sure chip
+- * initialization has completed. Use presence of the firmware ID as
+- * indicator for initialization having completed.
+- * The chip also provides a "reset completed" bit, but it's cleared after
+- * read. Therefore function would time out if called again.
+- */
+-static int aqr107_wait_reset_complete(struct phy_device *phydev)
+-{
+- int val;
+-
+- return phy_read_mmd_poll_timeout(phydev, MDIO_MMD_VEND1,
+- VEND1_GLOBAL_FW_ID, val, val != 0,
+- 20000, 2000000, false);
+-}
+-
+-static void aqr107_chip_info(struct phy_device *phydev)
+-{
+- u8 fw_major, fw_minor, build_id, prov_id;
+- int val;
+-
+- val = phy_read_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_FW_ID);
+- if (val < 0)
+- return;
+-
+- fw_major = FIELD_GET(VEND1_GLOBAL_FW_ID_MAJOR, val);
+- fw_minor = FIELD_GET(VEND1_GLOBAL_FW_ID_MINOR, val);
+-
+- val = phy_read_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_RSVD_STAT1);
+- if (val < 0)
+- return;
+-
+- build_id = FIELD_GET(VEND1_GLOBAL_RSVD_STAT1_FW_BUILD_ID, val);
+- prov_id = FIELD_GET(VEND1_GLOBAL_RSVD_STAT1_PROV_ID, val);
+-
+- phydev_dbg(phydev, "FW %u.%u, Build %u, Provisioning %u\n",
+- fw_major, fw_minor, build_id, prov_id);
+-}
+-
+-static int aqr107_config_init(struct phy_device *phydev)
+-{
+- int ret;
+-
+- /* Check that the PHY interface type is compatible */
+- if (phydev->interface != PHY_INTERFACE_MODE_SGMII &&
+- phydev->interface != PHY_INTERFACE_MODE_1000BASEKX &&
+- phydev->interface != PHY_INTERFACE_MODE_2500BASEX &&
+- phydev->interface != PHY_INTERFACE_MODE_XGMII &&
+- phydev->interface != PHY_INTERFACE_MODE_USXGMII &&
+- phydev->interface != PHY_INTERFACE_MODE_10GKR &&
+- phydev->interface != PHY_INTERFACE_MODE_10GBASER &&
+- phydev->interface != PHY_INTERFACE_MODE_XAUI &&
+- phydev->interface != PHY_INTERFACE_MODE_RXAUI)
+- return -ENODEV;
+-
+- WARN(phydev->interface == PHY_INTERFACE_MODE_XGMII,
+- "Your devicetree is out of date, please update it. The AQR107 family doesn't support XGMII, maybe you mean USXGMII.\n");
+-
+- ret = aqr107_wait_reset_complete(phydev);
+- if (!ret)
+- aqr107_chip_info(phydev);
+-
+- return aqr107_set_downshift(phydev, MDIO_AN_VEND_PROV_DOWNSHIFT_DFLT);
+-}
+-
+-static int aqcs109_config_init(struct phy_device *phydev)
+-{
+- int ret;
+-
+- /* Check that the PHY interface type is compatible */
+- if (phydev->interface != PHY_INTERFACE_MODE_SGMII &&
+- phydev->interface != PHY_INTERFACE_MODE_2500BASEX)
+- return -ENODEV;
+-
+- ret = aqr107_wait_reset_complete(phydev);
+- if (!ret)
+- aqr107_chip_info(phydev);
+-
+- /* AQCS109 belongs to a chip family partially supporting 10G and 5G.
+- * PMA speed ability bits are the same for all members of the family,
+- * AQCS109 however supports speeds up to 2.5G only.
+- */
+- ret = phy_set_max_speed(phydev, SPEED_2500);
+- if (ret)
+- return ret;
+-
+- return aqr107_set_downshift(phydev, MDIO_AN_VEND_PROV_DOWNSHIFT_DFLT);
+-}
+-
+-static void aqr107_link_change_notify(struct phy_device *phydev)
+-{
+- u8 fw_major, fw_minor;
+- bool downshift, short_reach, afr;
+- int mode, val;
+-
+- if (phydev->state != PHY_RUNNING || phydev->autoneg == AUTONEG_DISABLE)
+- return;
+-
+- val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_RX_LP_STAT1);
+- /* call failed or link partner is no Aquantia PHY */
+- if (val < 0 || !(val & MDIO_AN_RX_LP_STAT1_AQ_PHY))
+- return;
+-
+- short_reach = val & MDIO_AN_RX_LP_STAT1_SHORT_REACH;
+- downshift = val & MDIO_AN_RX_LP_STAT1_AQRATE_DOWNSHIFT;
+-
+- val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_RX_LP_STAT4);
+- if (val < 0)
+- return;
+-
+- fw_major = FIELD_GET(MDIO_AN_RX_LP_STAT4_FW_MAJOR, val);
+- fw_minor = FIELD_GET(MDIO_AN_RX_LP_STAT4_FW_MINOR, val);
+-
+- val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_RX_VEND_STAT3);
+- if (val < 0)
+- return;
+-
+- afr = val & MDIO_AN_RX_VEND_STAT3_AFR;
+-
+- phydev_dbg(phydev, "Link partner is Aquantia PHY, FW %u.%u%s%s%s\n",
+- fw_major, fw_minor,
+- short_reach ? ", short reach mode" : "",
+- downshift ? ", fast-retrain downshift advertised" : "",
+- afr ? ", fast reframe advertised" : "");
+-
+- val = phy_read_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_RSVD_STAT9);
+- if (val < 0)
+- return;
+-
+- mode = FIELD_GET(VEND1_GLOBAL_RSVD_STAT9_MODE, val);
+- if (mode == VEND1_GLOBAL_RSVD_STAT9_1000BT2)
+- phydev_info(phydev, "Aquantia 1000Base-T2 mode active\n");
+-}
+-
+-static int aqr107_wait_processor_intensive_op(struct phy_device *phydev)
+-{
+- int val, err;
+-
+- /* The datasheet notes to wait at least 1ms after issuing a
+- * processor intensive operation before checking.
+- * We cannot use the 'sleep_before_read' parameter of read_poll_timeout
+- * because that just determines the maximum time slept, not the minimum.
+- */
+- usleep_range(1000, 5000);
+-
+- err = phy_read_mmd_poll_timeout(phydev, MDIO_MMD_VEND1,
+- VEND1_GLOBAL_GEN_STAT2, val,
+- !(val & VEND1_GLOBAL_GEN_STAT2_OP_IN_PROG),
+- AQR107_OP_IN_PROG_SLEEP,
+- AQR107_OP_IN_PROG_TIMEOUT, false);
+- if (err) {
+- phydev_err(phydev, "timeout: processor-intensive MDIO operation\n");
+- return err;
+- }
+-
+- return 0;
+-}
+-
+-static int aqr107_get_rate_matching(struct phy_device *phydev,
+- phy_interface_t iface)
+-{
+- if (iface == PHY_INTERFACE_MODE_10GBASER ||
+- iface == PHY_INTERFACE_MODE_2500BASEX ||
+- iface == PHY_INTERFACE_MODE_NA)
+- return RATE_MATCH_PAUSE;
+- return RATE_MATCH_NONE;
+-}
+-
+-static int aqr107_suspend(struct phy_device *phydev)
+-{
+- int err;
+-
+- err = phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, MDIO_CTRL1,
+- MDIO_CTRL1_LPOWER);
+- if (err)
+- return err;
+-
+- return aqr107_wait_processor_intensive_op(phydev);
+-}
+-
+-static int aqr107_resume(struct phy_device *phydev)
+-{
+- int err;
+-
+- err = phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MDIO_CTRL1,
+- MDIO_CTRL1_LPOWER);
+- if (err)
+- return err;
+-
+- return aqr107_wait_processor_intensive_op(phydev);
+-}
+-
+-static int aqr107_probe(struct phy_device *phydev)
+-{
+- phydev->priv = devm_kzalloc(&phydev->mdio.dev,
+- sizeof(struct aqr107_priv), GFP_KERNEL);
+- if (!phydev->priv)
+- return -ENOMEM;
+-
+- return aqr_hwmon_probe(phydev);
+-}
+-
+-static struct phy_driver aqr_driver[] = {
+-{
+- PHY_ID_MATCH_MODEL(PHY_ID_AQ1202),
+- .name = "Aquantia AQ1202",
+- .config_aneg = aqr_config_aneg,
+- .config_intr = aqr_config_intr,
+- .handle_interrupt = aqr_handle_interrupt,
+- .read_status = aqr_read_status,
+-},
+-{
+- PHY_ID_MATCH_MODEL(PHY_ID_AQ2104),
+- .name = "Aquantia AQ2104",
+- .config_aneg = aqr_config_aneg,
+- .config_intr = aqr_config_intr,
+- .handle_interrupt = aqr_handle_interrupt,
+- .read_status = aqr_read_status,
+-},
+-{
+- PHY_ID_MATCH_MODEL(PHY_ID_AQR105),
+- .name = "Aquantia AQR105",
+- .config_aneg = aqr_config_aneg,
+- .config_intr = aqr_config_intr,
+- .handle_interrupt = aqr_handle_interrupt,
+- .read_status = aqr_read_status,
+- .suspend = aqr107_suspend,
+- .resume = aqr107_resume,
+-},
+-{
+- PHY_ID_MATCH_MODEL(PHY_ID_AQR106),
+- .name = "Aquantia AQR106",
+- .config_aneg = aqr_config_aneg,
+- .config_intr = aqr_config_intr,
+- .handle_interrupt = aqr_handle_interrupt,
+- .read_status = aqr_read_status,
+-},
+-{
+- PHY_ID_MATCH_MODEL(PHY_ID_AQR107),
+- .name = "Aquantia AQR107",
+- .probe = aqr107_probe,
+- .get_rate_matching = aqr107_get_rate_matching,
+- .config_init = aqr107_config_init,
+- .config_aneg = aqr_config_aneg,
+- .config_intr = aqr_config_intr,
+- .handle_interrupt = aqr_handle_interrupt,
+- .read_status = aqr107_read_status,
+- .get_tunable = aqr107_get_tunable,
+- .set_tunable = aqr107_set_tunable,
+- .suspend = aqr107_suspend,
+- .resume = aqr107_resume,
+- .get_sset_count = aqr107_get_sset_count,
+- .get_strings = aqr107_get_strings,
+- .get_stats = aqr107_get_stats,
+- .link_change_notify = aqr107_link_change_notify,
+-},
+-{
+- PHY_ID_MATCH_MODEL(PHY_ID_AQCS109),
+- .name = "Aquantia AQCS109",
+- .probe = aqr107_probe,
+- .get_rate_matching = aqr107_get_rate_matching,
+- .config_init = aqcs109_config_init,
+- .config_aneg = aqr_config_aneg,
+- .config_intr = aqr_config_intr,
+- .handle_interrupt = aqr_handle_interrupt,
+- .read_status = aqr107_read_status,
+- .get_tunable = aqr107_get_tunable,
+- .set_tunable = aqr107_set_tunable,
+- .suspend = aqr107_suspend,
+- .resume = aqr107_resume,
+- .get_sset_count = aqr107_get_sset_count,
+- .get_strings = aqr107_get_strings,
+- .get_stats = aqr107_get_stats,
+- .link_change_notify = aqr107_link_change_notify,
+-},
+-{
+- PHY_ID_MATCH_MODEL(PHY_ID_AQR405),
+- .name = "Aquantia AQR405",
+- .config_aneg = aqr_config_aneg,
+- .config_intr = aqr_config_intr,
+- .handle_interrupt = aqr_handle_interrupt,
+- .read_status = aqr_read_status,
+-},
+-{
+- PHY_ID_MATCH_MODEL(PHY_ID_AQR113C),
+- .name = "Aquantia AQR113C",
+- .probe = aqr107_probe,
+- .get_rate_matching = aqr107_get_rate_matching,
+- .config_init = aqr107_config_init,
+- .config_aneg = aqr_config_aneg,
+- .config_intr = aqr_config_intr,
+- .handle_interrupt = aqr_handle_interrupt,
+- .read_status = aqr107_read_status,
+- .get_tunable = aqr107_get_tunable,
+- .set_tunable = aqr107_set_tunable,
+- .suspend = aqr107_suspend,
+- .resume = aqr107_resume,
+- .get_sset_count = aqr107_get_sset_count,
+- .get_strings = aqr107_get_strings,
+- .get_stats = aqr107_get_stats,
+- .link_change_notify = aqr107_link_change_notify,
+-},
+-};
+-
+-module_phy_driver(aqr_driver);
+-
+-static struct mdio_device_id __maybe_unused aqr_tbl[] = {
+- { PHY_ID_MATCH_MODEL(PHY_ID_AQ1202) },
+- { PHY_ID_MATCH_MODEL(PHY_ID_AQ2104) },
+- { PHY_ID_MATCH_MODEL(PHY_ID_AQR105) },
+- { PHY_ID_MATCH_MODEL(PHY_ID_AQR106) },
+- { PHY_ID_MATCH_MODEL(PHY_ID_AQR107) },
+- { PHY_ID_MATCH_MODEL(PHY_ID_AQCS109) },
+- { PHY_ID_MATCH_MODEL(PHY_ID_AQR405) },
+- { PHY_ID_MATCH_MODEL(PHY_ID_AQR113C) },
+- { }
+-};
+-
+-MODULE_DEVICE_TABLE(mdio, aqr_tbl);
+-
+-MODULE_DESCRIPTION("Aquantia PHY driver");
+-MODULE_AUTHOR("Shaohui Xie <Shaohui.Xie at freescale.com>");
+-MODULE_LICENSE("GPL v2");
diff --git a/target/linux/generic/backport-5.15/737-02-v6.7-net-phy-aquantia-move-MMD_VEND-define-to-header.patch b/target/linux/generic/backport-5.15/737-02-v6.7-net-phy-aquantia-move-MMD_VEND-define-to-header.patch
new file mode 100644
index 0000000000..2b94522723
--- /dev/null
+++ b/target/linux/generic/backport-5.15/737-02-v6.7-net-phy-aquantia-move-MMD_VEND-define-to-header.patch
@@ -0,0 +1,183 @@
+From e1fbfa4a995d42e02e22b0dff2f8b4fdee1504b3 Mon Sep 17 00:00:00 2001
+From: Christian Marangi <ansuelsmth at gmail.com>
+Date: Tue, 14 Nov 2023 15:08:42 +0100
+Subject: [PATCH 2/3] net: phy: aquantia: move MMD_VEND define to header
+
+Move MMD_VEND define to header to clean things up and in preparation for
+firmware loading support that require some define placed in
+aquantia_main.
+
+Signed-off-by: Christian Marangi <ansuelsmth at gmail.com>
+Reviewed-by: Andrew Lunn <andrew at lunn.ch>
+Signed-off-by: David S. Miller <davem at davemloft.net>
+---
+ drivers/net/phy/aquantia/aquantia.h | 69 +++++++++++++++++++++++
+ drivers/net/phy/aquantia/aquantia_hwmon.c | 14 -----
+ drivers/net/phy/aquantia/aquantia_main.c | 55 ------------------
+ 3 files changed, 69 insertions(+), 69 deletions(-)
+
+--- a/drivers/net/phy/aquantia/aquantia.h
++++ b/drivers/net/phy/aquantia/aquantia.h
+@@ -9,6 +9,75 @@
+ #include <linux/device.h>
+ #include <linux/phy.h>
+
++/* Vendor specific 1, MDIO_MMD_VEND1 */
++#define VEND1_GLOBAL_FW_ID 0x0020
++#define VEND1_GLOBAL_FW_ID_MAJOR GENMASK(15, 8)
++#define VEND1_GLOBAL_FW_ID_MINOR GENMASK(7, 0)
++
++/* The following registers all have similar layouts; first the registers... */
++#define VEND1_GLOBAL_CFG_10M 0x0310
++#define VEND1_GLOBAL_CFG_100M 0x031b
++#define VEND1_GLOBAL_CFG_1G 0x031c
++#define VEND1_GLOBAL_CFG_2_5G 0x031d
++#define VEND1_GLOBAL_CFG_5G 0x031e
++#define VEND1_GLOBAL_CFG_10G 0x031f
++/* ...and now the fields */
++#define VEND1_GLOBAL_CFG_RATE_ADAPT GENMASK(8, 7)
++#define VEND1_GLOBAL_CFG_RATE_ADAPT_NONE 0
++#define VEND1_GLOBAL_CFG_RATE_ADAPT_USX 1
++#define VEND1_GLOBAL_CFG_RATE_ADAPT_PAUSE 2
++
++/* Vendor specific 1, MDIO_MMD_VEND2 */
++#define VEND1_THERMAL_PROV_HIGH_TEMP_FAIL 0xc421
++#define VEND1_THERMAL_PROV_LOW_TEMP_FAIL 0xc422
++#define VEND1_THERMAL_PROV_HIGH_TEMP_WARN 0xc423
++#define VEND1_THERMAL_PROV_LOW_TEMP_WARN 0xc424
++#define VEND1_THERMAL_STAT1 0xc820
++#define VEND1_THERMAL_STAT2 0xc821
++#define VEND1_THERMAL_STAT2_VALID BIT(0)
++#define VEND1_GENERAL_STAT1 0xc830
++#define VEND1_GENERAL_STAT1_HIGH_TEMP_FAIL BIT(14)
++#define VEND1_GENERAL_STAT1_LOW_TEMP_FAIL BIT(13)
++#define VEND1_GENERAL_STAT1_HIGH_TEMP_WARN BIT(12)
++#define VEND1_GENERAL_STAT1_LOW_TEMP_WARN BIT(11)
++
++#define VEND1_GLOBAL_GEN_STAT2 0xc831
++#define VEND1_GLOBAL_GEN_STAT2_OP_IN_PROG BIT(15)
++
++#define VEND1_GLOBAL_RSVD_STAT1 0xc885
++#define VEND1_GLOBAL_RSVD_STAT1_FW_BUILD_ID GENMASK(7, 4)
++#define VEND1_GLOBAL_RSVD_STAT1_PROV_ID GENMASK(3, 0)
++
++#define VEND1_GLOBAL_RSVD_STAT9 0xc88d
++#define VEND1_GLOBAL_RSVD_STAT9_MODE GENMASK(7, 0)
++#define VEND1_GLOBAL_RSVD_STAT9_1000BT2 0x23
++
++#define VEND1_GLOBAL_INT_STD_STATUS 0xfc00
++#define VEND1_GLOBAL_INT_VEND_STATUS 0xfc01
++
++#define VEND1_GLOBAL_INT_STD_MASK 0xff00
++#define VEND1_GLOBAL_INT_STD_MASK_PMA1 BIT(15)
++#define VEND1_GLOBAL_INT_STD_MASK_PMA2 BIT(14)
++#define VEND1_GLOBAL_INT_STD_MASK_PCS1 BIT(13)
++#define VEND1_GLOBAL_INT_STD_MASK_PCS2 BIT(12)
++#define VEND1_GLOBAL_INT_STD_MASK_PCS3 BIT(11)
++#define VEND1_GLOBAL_INT_STD_MASK_PHY_XS1 BIT(10)
++#define VEND1_GLOBAL_INT_STD_MASK_PHY_XS2 BIT(9)
++#define VEND1_GLOBAL_INT_STD_MASK_AN1 BIT(8)
++#define VEND1_GLOBAL_INT_STD_MASK_AN2 BIT(7)
++#define VEND1_GLOBAL_INT_STD_MASK_GBE BIT(6)
++#define VEND1_GLOBAL_INT_STD_MASK_ALL BIT(0)
++
++#define VEND1_GLOBAL_INT_VEND_MASK 0xff01
++#define VEND1_GLOBAL_INT_VEND_MASK_PMA BIT(15)
++#define VEND1_GLOBAL_INT_VEND_MASK_PCS BIT(14)
++#define VEND1_GLOBAL_INT_VEND_MASK_PHY_XS BIT(13)
++#define VEND1_GLOBAL_INT_VEND_MASK_AN BIT(12)
++#define VEND1_GLOBAL_INT_VEND_MASK_GBE BIT(11)
++#define VEND1_GLOBAL_INT_VEND_MASK_GLOBAL1 BIT(2)
++#define VEND1_GLOBAL_INT_VEND_MASK_GLOBAL2 BIT(1)
++#define VEND1_GLOBAL_INT_VEND_MASK_GLOBAL3 BIT(0)
++
+ #if IS_REACHABLE(CONFIG_HWMON)
+ int aqr_hwmon_probe(struct phy_device *phydev);
+ #else
+--- a/drivers/net/phy/aquantia/aquantia_hwmon.c
++++ b/drivers/net/phy/aquantia/aquantia_hwmon.c
+@@ -13,20 +13,6 @@
+
+ #include "aquantia.h"
+
+-/* Vendor specific 1, MDIO_MMD_VEND2 */
+-#define VEND1_THERMAL_PROV_HIGH_TEMP_FAIL 0xc421
+-#define VEND1_THERMAL_PROV_LOW_TEMP_FAIL 0xc422
+-#define VEND1_THERMAL_PROV_HIGH_TEMP_WARN 0xc423
+-#define VEND1_THERMAL_PROV_LOW_TEMP_WARN 0xc424
+-#define VEND1_THERMAL_STAT1 0xc820
+-#define VEND1_THERMAL_STAT2 0xc821
+-#define VEND1_THERMAL_STAT2_VALID BIT(0)
+-#define VEND1_GENERAL_STAT1 0xc830
+-#define VEND1_GENERAL_STAT1_HIGH_TEMP_FAIL BIT(14)
+-#define VEND1_GENERAL_STAT1_LOW_TEMP_FAIL BIT(13)
+-#define VEND1_GENERAL_STAT1_HIGH_TEMP_WARN BIT(12)
+-#define VEND1_GENERAL_STAT1_LOW_TEMP_WARN BIT(11)
+-
+ #if IS_REACHABLE(CONFIG_HWMON)
+
+ static umode_t aqr_hwmon_is_visible(const void *data,
+--- a/drivers/net/phy/aquantia/aquantia_main.c
++++ b/drivers/net/phy/aquantia/aquantia_main.c
+@@ -89,61 +89,6 @@
+ #define MDIO_C22EXT_STAT_SGMII_TX_FRAME_ALIGN_ERR 0xd31a
+ #define MDIO_C22EXT_STAT_SGMII_TX_RUNT_FRAMES 0xd31b
+
+-/* Vendor specific 1, MDIO_MMD_VEND1 */
+-#define VEND1_GLOBAL_FW_ID 0x0020
+-#define VEND1_GLOBAL_FW_ID_MAJOR GENMASK(15, 8)
+-#define VEND1_GLOBAL_FW_ID_MINOR GENMASK(7, 0)
+-
+-#define VEND1_GLOBAL_GEN_STAT2 0xc831
+-#define VEND1_GLOBAL_GEN_STAT2_OP_IN_PROG BIT(15)
+-
+-/* The following registers all have similar layouts; first the registers... */
+-#define VEND1_GLOBAL_CFG_10M 0x0310
+-#define VEND1_GLOBAL_CFG_100M 0x031b
+-#define VEND1_GLOBAL_CFG_1G 0x031c
+-#define VEND1_GLOBAL_CFG_2_5G 0x031d
+-#define VEND1_GLOBAL_CFG_5G 0x031e
+-#define VEND1_GLOBAL_CFG_10G 0x031f
+-/* ...and now the fields */
+-#define VEND1_GLOBAL_CFG_RATE_ADAPT GENMASK(8, 7)
+-#define VEND1_GLOBAL_CFG_RATE_ADAPT_NONE 0
+-#define VEND1_GLOBAL_CFG_RATE_ADAPT_USX 1
+-#define VEND1_GLOBAL_CFG_RATE_ADAPT_PAUSE 2
+-
+-#define VEND1_GLOBAL_RSVD_STAT1 0xc885
+-#define VEND1_GLOBAL_RSVD_STAT1_FW_BUILD_ID GENMASK(7, 4)
+-#define VEND1_GLOBAL_RSVD_STAT1_PROV_ID GENMASK(3, 0)
+-
+-#define VEND1_GLOBAL_RSVD_STAT9 0xc88d
+-#define VEND1_GLOBAL_RSVD_STAT9_MODE GENMASK(7, 0)
+-#define VEND1_GLOBAL_RSVD_STAT9_1000BT2 0x23
+-
+-#define VEND1_GLOBAL_INT_STD_STATUS 0xfc00
+-#define VEND1_GLOBAL_INT_VEND_STATUS 0xfc01
+-
+-#define VEND1_GLOBAL_INT_STD_MASK 0xff00
+-#define VEND1_GLOBAL_INT_STD_MASK_PMA1 BIT(15)
+-#define VEND1_GLOBAL_INT_STD_MASK_PMA2 BIT(14)
+-#define VEND1_GLOBAL_INT_STD_MASK_PCS1 BIT(13)
+-#define VEND1_GLOBAL_INT_STD_MASK_PCS2 BIT(12)
+-#define VEND1_GLOBAL_INT_STD_MASK_PCS3 BIT(11)
+-#define VEND1_GLOBAL_INT_STD_MASK_PHY_XS1 BIT(10)
+-#define VEND1_GLOBAL_INT_STD_MASK_PHY_XS2 BIT(9)
+-#define VEND1_GLOBAL_INT_STD_MASK_AN1 BIT(8)
+-#define VEND1_GLOBAL_INT_STD_MASK_AN2 BIT(7)
+-#define VEND1_GLOBAL_INT_STD_MASK_GBE BIT(6)
+-#define VEND1_GLOBAL_INT_STD_MASK_ALL BIT(0)
+-
+-#define VEND1_GLOBAL_INT_VEND_MASK 0xff01
+-#define VEND1_GLOBAL_INT_VEND_MASK_PMA BIT(15)
+-#define VEND1_GLOBAL_INT_VEND_MASK_PCS BIT(14)
+-#define VEND1_GLOBAL_INT_VEND_MASK_PHY_XS BIT(13)
+-#define VEND1_GLOBAL_INT_VEND_MASK_AN BIT(12)
+-#define VEND1_GLOBAL_INT_VEND_MASK_GBE BIT(11)
+-#define VEND1_GLOBAL_INT_VEND_MASK_GLOBAL1 BIT(2)
+-#define VEND1_GLOBAL_INT_VEND_MASK_GLOBAL2 BIT(1)
+-#define VEND1_GLOBAL_INT_VEND_MASK_GLOBAL3 BIT(0)
+-
+ /* Sleep and timeout for checking if the Processor-Intensive
+ * MDIO operation is finished
+ */
diff --git a/target/linux/generic/backport-5.15/737-03-v6.7-net-phy-aquantia-add-firmware-load-support.patch b/target/linux/generic/backport-5.15/737-03-v6.7-net-phy-aquantia-add-firmware-load-support.patch
new file mode 100644
index 0000000000..1ae5966df6
--- /dev/null
+++ b/target/linux/generic/backport-5.15/737-03-v6.7-net-phy-aquantia-add-firmware-load-support.patch
@@ -0,0 +1,504 @@
+From e93984ebc1c82bd34f7a1b3391efaceee0a8ae96 Mon Sep 17 00:00:00 2001
+From: Robert Marko <robimarko at gmail.com>
+Date: Tue, 14 Nov 2023 15:08:43 +0100
+Subject: [PATCH 3/3] net: phy: aquantia: add firmware load support
+
+Aquantia PHY-s require firmware to be loaded before they start operating.
+It can be automatically loaded in case when there is a SPI-NOR connected
+to Aquantia PHY-s or can be loaded from the host via MDIO.
+
+This patch adds support for loading the firmware via MDIO as in most cases
+there is no SPI-NOR being used to save on cost.
+Firmware loading code itself is ported from mainline U-boot with cleanups.
+
+The firmware has mixed values both in big and little endian.
+PHY core itself is big-endian but it expects values to be in little-endian.
+The firmware is little-endian but CRC-16 value for it is stored at the end
+of firmware in big-endian.
+
+It seems the PHY does the conversion internally from firmware that is
+little-endian to the PHY that is big-endian on using the mailbox
+but mailbox returns a big-endian CRC-16 to verify the written data
+integrity.
+
+Co-developed-by: Christian Marangi <ansuelsmth at gmail.com>
+Signed-off-by: Robert Marko <robimarko at gmail.com>
+Signed-off-by: Christian Marangi <ansuelsmth at gmail.com>
+Reviewed-by: Andrew Lunn <andrew at lunn.ch>
+Signed-off-by: David S. Miller <davem at davemloft.net>
+---
+ drivers/net/phy/aquantia/Kconfig | 1 +
+ drivers/net/phy/aquantia/Makefile | 2 +-
+ drivers/net/phy/aquantia/aquantia.h | 32 ++
+ drivers/net/phy/aquantia/aquantia_firmware.c | 370 +++++++++++++++++++
+ drivers/net/phy/aquantia/aquantia_main.c | 6 +
+ 5 files changed, 410 insertions(+), 1 deletion(-)
+ create mode 100644 drivers/net/phy/aquantia/aquantia_firmware.c
+
+--- a/drivers/net/phy/aquantia/Kconfig
++++ b/drivers/net/phy/aquantia/Kconfig
+@@ -1,5 +1,6 @@
+ # SPDX-License-Identifier: GPL-2.0-only
+ config AQUANTIA_PHY
+ tristate "Aquantia PHYs"
++ select CRC_CCITT
+ help
+ Currently supports the Aquantia AQ1202, AQ2104, AQR105, AQR405
+--- a/drivers/net/phy/aquantia/Makefile
++++ b/drivers/net/phy/aquantia/Makefile
+@@ -1,5 +1,5 @@
+ # SPDX-License-Identifier: GPL-2.0
+-aquantia-objs += aquantia_main.o
++aquantia-objs += aquantia_main.o aquantia_firmware.o
+ ifdef CONFIG_HWMON
+ aquantia-objs += aquantia_hwmon.o
+ endif
+--- a/drivers/net/phy/aquantia/aquantia.h
++++ b/drivers/net/phy/aquantia/aquantia.h
+@@ -10,10 +10,35 @@
+ #include <linux/phy.h>
+
+ /* Vendor specific 1, MDIO_MMD_VEND1 */
++#define VEND1_GLOBAL_SC 0x0
++#define VEND1_GLOBAL_SC_SOFT_RESET BIT(15)
++#define VEND1_GLOBAL_SC_LOW_POWER BIT(11)
++
+ #define VEND1_GLOBAL_FW_ID 0x0020
+ #define VEND1_GLOBAL_FW_ID_MAJOR GENMASK(15, 8)
+ #define VEND1_GLOBAL_FW_ID_MINOR GENMASK(7, 0)
+
++#define VEND1_GLOBAL_MAILBOX_INTERFACE1 0x0200
++#define VEND1_GLOBAL_MAILBOX_INTERFACE1_EXECUTE BIT(15)
++#define VEND1_GLOBAL_MAILBOX_INTERFACE1_WRITE BIT(14)
++#define VEND1_GLOBAL_MAILBOX_INTERFACE1_CRC_RESET BIT(12)
++#define VEND1_GLOBAL_MAILBOX_INTERFACE1_BUSY BIT(8)
++
++#define VEND1_GLOBAL_MAILBOX_INTERFACE2 0x0201
++#define VEND1_GLOBAL_MAILBOX_INTERFACE3 0x0202
++#define VEND1_GLOBAL_MAILBOX_INTERFACE3_MSW_ADDR_MASK GENMASK(15, 0)
++#define VEND1_GLOBAL_MAILBOX_INTERFACE3_MSW_ADDR(x) FIELD_PREP(VEND1_GLOBAL_MAILBOX_INTERFACE3_MSW_ADDR_MASK, (u16)((x) >> 16))
++#define VEND1_GLOBAL_MAILBOX_INTERFACE4 0x0203
++#define VEND1_GLOBAL_MAILBOX_INTERFACE4_LSW_ADDR_MASK GENMASK(15, 2)
++#define VEND1_GLOBAL_MAILBOX_INTERFACE4_LSW_ADDR(x) FIELD_PREP(VEND1_GLOBAL_MAILBOX_INTERFACE4_LSW_ADDR_MASK, (u16)(x))
++
++#define VEND1_GLOBAL_MAILBOX_INTERFACE5 0x0204
++#define VEND1_GLOBAL_MAILBOX_INTERFACE5_MSW_DATA_MASK GENMASK(15, 0)
++#define VEND1_GLOBAL_MAILBOX_INTERFACE5_MSW_DATA(x) FIELD_PREP(VEND1_GLOBAL_MAILBOX_INTERFACE5_MSW_DATA_MASK, (u16)((x) >> 16))
++#define VEND1_GLOBAL_MAILBOX_INTERFACE6 0x0205
++#define VEND1_GLOBAL_MAILBOX_INTERFACE6_LSW_DATA_MASK GENMASK(15, 0)
++#define VEND1_GLOBAL_MAILBOX_INTERFACE6_LSW_DATA(x) FIELD_PREP(VEND1_GLOBAL_MAILBOX_INTERFACE6_LSW_DATA_MASK, (u16)(x))
++
+ /* The following registers all have similar layouts; first the registers... */
+ #define VEND1_GLOBAL_CFG_10M 0x0310
+ #define VEND1_GLOBAL_CFG_100M 0x031b
+@@ -28,6 +53,11 @@
+ #define VEND1_GLOBAL_CFG_RATE_ADAPT_PAUSE 2
+
+ /* Vendor specific 1, MDIO_MMD_VEND2 */
++#define VEND1_GLOBAL_CONTROL2 0xc001
++#define VEND1_GLOBAL_CONTROL2_UP_RUN_STALL_RST BIT(15)
++#define VEND1_GLOBAL_CONTROL2_UP_RUN_STALL_OVD BIT(6)
++#define VEND1_GLOBAL_CONTROL2_UP_RUN_STALL BIT(0)
++
+ #define VEND1_THERMAL_PROV_HIGH_TEMP_FAIL 0xc421
+ #define VEND1_THERMAL_PROV_LOW_TEMP_FAIL 0xc422
+ #define VEND1_THERMAL_PROV_HIGH_TEMP_WARN 0xc423
+@@ -83,3 +113,5 @@ int aqr_hwmon_probe(struct phy_device *p
+ #else
+ static inline int aqr_hwmon_probe(struct phy_device *phydev) { return 0; }
+ #endif
++
++int aqr_firmware_load(struct phy_device *phydev);
+--- /dev/null
++++ b/drivers/net/phy/aquantia/aquantia_firmware.c
+@@ -0,0 +1,370 @@
++// SPDX-License-Identifier: GPL-2.0
++
++#include <linux/bitfield.h>
++#include <linux/of.h>
++#include <linux/firmware.h>
++#include <linux/crc-ccitt.h>
++#include <linux/nvmem-consumer.h>
++
++#include <asm/unaligned.h>
++
++#include "aquantia.h"
++
++#define UP_RESET_SLEEP 100
++
++/* addresses of memory segments in the phy */
++#define DRAM_BASE_ADDR 0x3FFE0000
++#define IRAM_BASE_ADDR 0x40000000
++
++/* firmware image format constants */
++#define VERSION_STRING_SIZE 0x40
++#define VERSION_STRING_OFFSET 0x0200
++/* primary offset is written at an offset from the start of the fw blob */
++#define PRIMARY_OFFSET_OFFSET 0x8
++/* primary offset needs to be then added to a base offset */
++#define PRIMARY_OFFSET_SHIFT 12
++#define PRIMARY_OFFSET(x) ((x) << PRIMARY_OFFSET_SHIFT)
++#define HEADER_OFFSET 0x300
++
++struct aqr_fw_header {
++ u32 padding;
++ u8 iram_offset[3];
++ u8 iram_size[3];
++ u8 dram_offset[3];
++ u8 dram_size[3];
++} __packed;
++
++enum aqr_fw_src {
++ AQR_FW_SRC_NVMEM = 0,
++ AQR_FW_SRC_FS,
++};
++
++static const char * const aqr_fw_src_string[] = {
++ [AQR_FW_SRC_NVMEM] = "NVMEM",
++ [AQR_FW_SRC_FS] = "FS",
++};
++
++/* AQR firmware doesn't have fixed offsets for iram and dram section
++ * but instead provide an header with the offset to use on reading
++ * and parsing the firmware.
++ *
++ * AQR firmware can't be trusted and each offset is validated to be
++ * not negative and be in the size of the firmware itself.
++ */
++static bool aqr_fw_validate_get(size_t size, size_t offset, size_t get_size)
++{
++ return offset + get_size <= size;
++}
++
++static int aqr_fw_get_be16(const u8 *data, size_t offset, size_t size, u16 *value)
++{
++ if (!aqr_fw_validate_get(size, offset, sizeof(u16)))
++ return -EINVAL;
++
++ *value = get_unaligned_be16(data + offset);
++
++ return 0;
++}
++
++static int aqr_fw_get_le16(const u8 *data, size_t offset, size_t size, u16 *value)
++{
++ if (!aqr_fw_validate_get(size, offset, sizeof(u16)))
++ return -EINVAL;
++
++ *value = get_unaligned_le16(data + offset);
++
++ return 0;
++}
++
++static int aqr_fw_get_le24(const u8 *data, size_t offset, size_t size, u32 *value)
++{
++ if (!aqr_fw_validate_get(size, offset, sizeof(u8) * 3))
++ return -EINVAL;
++
++ *value = get_unaligned_le24(data + offset);
++
++ return 0;
++}
++
++/* load data into the phy's memory */
++static int aqr_fw_load_memory(struct phy_device *phydev, u32 addr,
++ const u8 *data, size_t len)
++{
++ u16 crc = 0, up_crc;
++ size_t pos;
++
++ /* PHY expect addr in LE */
++ addr = (__force u32)cpu_to_le32(addr);
++
++ phy_write_mmd(phydev, MDIO_MMD_VEND1,
++ VEND1_GLOBAL_MAILBOX_INTERFACE1,
++ VEND1_GLOBAL_MAILBOX_INTERFACE1_CRC_RESET);
++ phy_write_mmd(phydev, MDIO_MMD_VEND1,
++ VEND1_GLOBAL_MAILBOX_INTERFACE3,
++ VEND1_GLOBAL_MAILBOX_INTERFACE3_MSW_ADDR(addr));
++ phy_write_mmd(phydev, MDIO_MMD_VEND1,
++ VEND1_GLOBAL_MAILBOX_INTERFACE4,
++ VEND1_GLOBAL_MAILBOX_INTERFACE4_LSW_ADDR(addr));
++
++ /* We assume and enforce the size to be word aligned.
++ * If a firmware that is not word aligned is found, please report upstream.
++ */
++ for (pos = 0; pos < len; pos += sizeof(u32)) {
++ u32 word;
++
++ /* FW data is always stored in little-endian */
++ word = get_unaligned((const u32 *)(data + pos));
++
++ phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_MAILBOX_INTERFACE5,
++ VEND1_GLOBAL_MAILBOX_INTERFACE5_MSW_DATA(word));
++ phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_MAILBOX_INTERFACE6,
++ VEND1_GLOBAL_MAILBOX_INTERFACE6_LSW_DATA(word));
++
++ phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_MAILBOX_INTERFACE1,
++ VEND1_GLOBAL_MAILBOX_INTERFACE1_EXECUTE |
++ VEND1_GLOBAL_MAILBOX_INTERFACE1_WRITE);
++
++ /* calculate CRC as we load data to the mailbox.
++ * We convert word to big-endian as PHY is BE and mailbox will
++ * return a BE CRC.
++ */
++ word = (__force u32)cpu_to_be32(word);
++ crc = crc_ccitt_false(crc, (u8 *)&word, sizeof(word));
++ }
++
++ up_crc = phy_read_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_MAILBOX_INTERFACE2);
++ if (crc != up_crc) {
++ phydev_err(phydev, "CRC mismatch: calculated 0x%04x PHY 0x%04x\n",
++ crc, up_crc);
++ return -EINVAL;
++ }
++
++ return 0;
++}
++
++static int aqr_fw_boot(struct phy_device *phydev, const u8 *data, size_t size,
++ enum aqr_fw_src fw_src)
++{
++ u16 calculated_crc, read_crc, read_primary_offset;
++ u32 iram_offset = 0, iram_size = 0;
++ u32 dram_offset = 0, dram_size = 0;
++ char version[VERSION_STRING_SIZE];
++ u32 primary_offset = 0;
++ int ret;
++
++ /* extract saved CRC at the end of the fw
++ * CRC is saved in big-endian as PHY is BE
++ */
++ ret = aqr_fw_get_be16(data, size - sizeof(u16), size, &read_crc);
++ if (ret) {
++ phydev_err(phydev, "bad firmware CRC in firmware\n");
++ return ret;
++ }
++ calculated_crc = crc_ccitt_false(0, data, size - sizeof(u16));
++ if (read_crc != calculated_crc) {
++ phydev_err(phydev, "bad firmware CRC: file 0x%04x calculated 0x%04x\n",
++ read_crc, calculated_crc);
++ return -EINVAL;
++ }
++
++ /* Get the primary offset to extract DRAM and IRAM sections. */
++ ret = aqr_fw_get_le16(data, PRIMARY_OFFSET_OFFSET, size, &read_primary_offset);
++ if (ret) {
++ phydev_err(phydev, "bad primary offset in firmware\n");
++ return ret;
++ }
++ primary_offset = PRIMARY_OFFSET(read_primary_offset);
++
++ /* Find the DRAM and IRAM sections within the firmware file.
++ * Make sure the fw_header is correctly in the firmware.
++ */
++ if (!aqr_fw_validate_get(size, primary_offset + HEADER_OFFSET,
++ sizeof(struct aqr_fw_header))) {
++ phydev_err(phydev, "bad fw_header in firmware\n");
++ return -EINVAL;
++ }
++
++ /* offset are in LE and values needs to be converted to cpu endian */
++ ret = aqr_fw_get_le24(data, primary_offset + HEADER_OFFSET +
++ offsetof(struct aqr_fw_header, iram_offset),
++ size, &iram_offset);
++ if (ret) {
++ phydev_err(phydev, "bad iram offset in firmware\n");
++ return ret;
++ }
++ ret = aqr_fw_get_le24(data, primary_offset + HEADER_OFFSET +
++ offsetof(struct aqr_fw_header, iram_size),
++ size, &iram_size);
++ if (ret) {
++ phydev_err(phydev, "invalid iram size in firmware\n");
++ return ret;
++ }
++ ret = aqr_fw_get_le24(data, primary_offset + HEADER_OFFSET +
++ offsetof(struct aqr_fw_header, dram_offset),
++ size, &dram_offset);
++ if (ret) {
++ phydev_err(phydev, "bad dram offset in firmware\n");
++ return ret;
++ }
++ ret = aqr_fw_get_le24(data, primary_offset + HEADER_OFFSET +
++ offsetof(struct aqr_fw_header, dram_size),
++ size, &dram_size);
++ if (ret) {
++ phydev_err(phydev, "invalid dram size in firmware\n");
++ return ret;
++ }
++
++ /* Increment the offset with the primary offset.
++ * Validate iram/dram offset and size.
++ */
++ iram_offset += primary_offset;
++ if (iram_size % sizeof(u32)) {
++ phydev_err(phydev, "iram size if not aligned to word size. Please report this upstream!\n");
++ return -EINVAL;
++ }
++ if (!aqr_fw_validate_get(size, iram_offset, iram_size)) {
++ phydev_err(phydev, "invalid iram offset for iram size\n");
++ return -EINVAL;
++ }
++
++ dram_offset += primary_offset;
++ if (dram_size % sizeof(u32)) {
++ phydev_err(phydev, "dram size if not aligned to word size. Please report this upstream!\n");
++ return -EINVAL;
++ }
++ if (!aqr_fw_validate_get(size, dram_offset, dram_size)) {
++ phydev_err(phydev, "invalid iram offset for iram size\n");
++ return -EINVAL;
++ }
++
++ phydev_dbg(phydev, "primary %d IRAM offset=%d size=%d DRAM offset=%d size=%d\n",
++ primary_offset, iram_offset, iram_size, dram_offset, dram_size);
++
++ if (!aqr_fw_validate_get(size, dram_offset + VERSION_STRING_OFFSET,
++ VERSION_STRING_SIZE)) {
++ phydev_err(phydev, "invalid version in firmware\n");
++ return -EINVAL;
++ }
++ strscpy(version, (char *)data + dram_offset + VERSION_STRING_OFFSET,
++ VERSION_STRING_SIZE);
++ if (version[0] == '\0') {
++ phydev_err(phydev, "invalid version in firmware\n");
++ return -EINVAL;
++ }
++ phydev_info(phydev, "loading firmware version '%s' from '%s'\n", version,
++ aqr_fw_src_string[fw_src]);
++
++ /* stall the microcprocessor */
++ phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_CONTROL2,
++ VEND1_GLOBAL_CONTROL2_UP_RUN_STALL | VEND1_GLOBAL_CONTROL2_UP_RUN_STALL_OVD);
++
++ phydev_dbg(phydev, "loading DRAM 0x%08x from offset=%d size=%d\n",
++ DRAM_BASE_ADDR, dram_offset, dram_size);
++ ret = aqr_fw_load_memory(phydev, DRAM_BASE_ADDR, data + dram_offset,
++ dram_size);
++ if (ret)
++ return ret;
++
++ phydev_dbg(phydev, "loading IRAM 0x%08x from offset=%d size=%d\n",
++ IRAM_BASE_ADDR, iram_offset, iram_size);
++ ret = aqr_fw_load_memory(phydev, IRAM_BASE_ADDR, data + iram_offset,
++ iram_size);
++ if (ret)
++ return ret;
++
++ /* make sure soft reset and low power mode are clear */
++ phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_SC,
++ VEND1_GLOBAL_SC_SOFT_RESET | VEND1_GLOBAL_SC_LOW_POWER);
++
++ /* Release the microprocessor. UP_RESET must be held for 100 usec. */
++ phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_CONTROL2,
++ VEND1_GLOBAL_CONTROL2_UP_RUN_STALL |
++ VEND1_GLOBAL_CONTROL2_UP_RUN_STALL_OVD |
++ VEND1_GLOBAL_CONTROL2_UP_RUN_STALL_RST);
++ usleep_range(UP_RESET_SLEEP, UP_RESET_SLEEP * 2);
++
++ phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_CONTROL2,
++ VEND1_GLOBAL_CONTROL2_UP_RUN_STALL_OVD);
++
++ return 0;
++}
++
++static int aqr_firmware_load_nvmem(struct phy_device *phydev)
++{
++ struct nvmem_cell *cell;
++ size_t size;
++ u8 *buf;
++ int ret;
++
++ cell = nvmem_cell_get(&phydev->mdio.dev, "firmware");
++ if (IS_ERR(cell))
++ return PTR_ERR(cell);
++
++ buf = nvmem_cell_read(cell, &size);
++ if (IS_ERR(buf)) {
++ ret = PTR_ERR(buf);
++ goto exit;
++ }
++
++ ret = aqr_fw_boot(phydev, buf, size, AQR_FW_SRC_NVMEM);
++ if (ret)
++ phydev_err(phydev, "firmware loading failed: %d\n", ret);
++
++ kfree(buf);
++exit:
++ nvmem_cell_put(cell);
++
++ return ret;
++}
++
++static int aqr_firmware_load_fs(struct phy_device *phydev)
++{
++ struct device *dev = &phydev->mdio.dev;
++ const struct firmware *fw;
++ const char *fw_name;
++ int ret;
++
++ ret = of_property_read_string(dev->of_node, "firmware-name",
++ &fw_name);
++ if (ret)
++ return ret;
++
++ ret = request_firmware(&fw, fw_name, dev);
++ if (ret) {
++ phydev_err(phydev, "failed to find FW file %s (%d)\n",
++ fw_name, ret);
++ return ret;
++ }
++
++ ret = aqr_fw_boot(phydev, fw->data, fw->size, AQR_FW_SRC_FS);
++ if (ret)
++ phydev_err(phydev, "firmware loading failed: %d\n", ret);
++
++ release_firmware(fw);
++
++ return ret;
++}
++
++int aqr_firmware_load(struct phy_device *phydev)
++{
++ int ret;
++
++ /* Check if the firmware is not already loaded by pooling
++ * the current version returned by the PHY. If 0 is returned,
++ * no firmware is loaded.
++ */
++ ret = phy_read_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_FW_ID);
++ if (ret > 0)
++ goto exit;
++
++ ret = aqr_firmware_load_nvmem(phydev);
++ if (!ret)
++ goto exit;
++
++ ret = aqr_firmware_load_fs(phydev);
++ if (ret)
++ return ret;
++
++exit:
++ return 0;
++}
+--- a/drivers/net/phy/aquantia/aquantia_main.c
++++ b/drivers/net/phy/aquantia/aquantia_main.c
+@@ -658,11 +658,17 @@ static int aqr107_resume(struct phy_devi
+
+ static int aqr107_probe(struct phy_device *phydev)
+ {
++ int ret;
++
+ phydev->priv = devm_kzalloc(&phydev->mdio.dev,
+ sizeof(struct aqr107_priv), GFP_KERNEL);
+ if (!phydev->priv)
+ return -ENOMEM;
+
++ ret = aqr_firmware_load(phydev);
++ if (ret)
++ return ret;
++
+ return aqr_hwmon_probe(phydev);
+ }
+
diff --git a/target/linux/generic/backport-5.15/791-v6.2-01-net-phy-Add-driver-for-Motorcomm-yt8521-gigabit-ethernet.patch b/target/linux/generic/backport-5.15/791-v6.2-01-net-phy-Add-driver-for-Motorcomm-yt8521-gigabit-ethernet.patch
index 7eb097f86d..7c0a490695 100644
--- a/target/linux/generic/backport-5.15/791-v6.2-01-net-phy-Add-driver-for-Motorcomm-yt8521-gigabit-ethernet.patch
+++ b/target/linux/generic/backport-5.15/791-v6.2-01-net-phy-Add-driver-for-Motorcomm-yt8521-gigabit-ethernet.patch
@@ -31,7 +31,7 @@ Signed-off-by: David S. Miller <davem at davemloft.net>
F: drivers/net/phy/motorcomm.c
--- a/drivers/net/phy/Kconfig
+++ b/drivers/net/phy/Kconfig
-@@ -245,7 +245,7 @@ config MOTORCOMM_PHY
+@@ -242,7 +242,7 @@ config MOTORCOMM_PHY
tristate "Motorcomm PHYs"
help
Enables support for Motorcomm network PHYs.
diff --git a/target/linux/generic/backport-5.15/791-v6.2-03-net-phy-add-Motorcomm-YT8531S-phy-id.patch b/target/linux/generic/backport-5.15/791-v6.2-03-net-phy-add-Motorcomm-YT8531S-phy-id.patch
index da60c63905..94d09092cf 100644
--- a/target/linux/generic/backport-5.15/791-v6.2-03-net-phy-add-Motorcomm-YT8531S-phy-id.patch
+++ b/target/linux/generic/backport-5.15/791-v6.2-03-net-phy-add-Motorcomm-YT8531S-phy-id.patch
@@ -22,7 +22,7 @@ Signed-off-by: David S. Miller <davem at davemloft.net>
--- a/drivers/net/phy/Kconfig
+++ b/drivers/net/phy/Kconfig
-@@ -245,7 +245,7 @@ config MOTORCOMM_PHY
+@@ -242,7 +242,7 @@ config MOTORCOMM_PHY
tristate "Motorcomm PHYs"
help
Enables support for Motorcomm network PHYs.
diff --git a/target/linux/generic/backport-5.15/791-v6.3-09-net-phy-Add-driver-for-Motorcomm-yt8531-gigabit-ethernet.patch b/target/linux/generic/backport-5.15/791-v6.3-09-net-phy-Add-driver-for-Motorcomm-yt8531-gigabit-ethernet.patch
index 9dce5a8add..a8b9e3d13b 100644
--- a/target/linux/generic/backport-5.15/791-v6.3-09-net-phy-Add-driver-for-Motorcomm-yt8531-gigabit-ethernet.patch
+++ b/target/linux/generic/backport-5.15/791-v6.3-09-net-phy-Add-driver-for-Motorcomm-yt8531-gigabit-ethernet.patch
@@ -19,7 +19,7 @@ Signed-off-by: David S. Miller <davem at davemloft.net>
--- a/drivers/net/phy/Kconfig
+++ b/drivers/net/phy/Kconfig
-@@ -245,7 +245,7 @@ config MOTORCOMM_PHY
+@@ -242,7 +242,7 @@ config MOTORCOMM_PHY
tristate "Motorcomm PHYs"
help
Enables support for Motorcomm network PHYs.
diff --git a/target/linux/generic/hack-5.15/720-net-phy-add-aqr-phys.patch b/target/linux/generic/hack-5.15/720-net-phy-add-aqr-phys.patch
index d8ec95b374..c4a915956e 100644
--- a/target/linux/generic/hack-5.15/720-net-phy-add-aqr-phys.patch
+++ b/target/linux/generic/hack-5.15/720-net-phy-add-aqr-phys.patch
@@ -7,8 +7,8 @@ PHYs AQR113C and AQR813.
Signed-off-by: Birger Koblitz <git at birger-koblitz.de>
---- a/drivers/net/phy/aquantia_main.c
-+++ b/drivers/net/phy/aquantia_main.c
+--- a/drivers/net/phy/aquantia/aquantia_main.c
++++ b/drivers/net/phy/aquantia/aquantia_main.c
@@ -23,6 +23,7 @@
#define PHY_ID_AQCS109 0x03a1b5c2
#define PHY_ID_AQR405 0x03a1b4b0
@@ -17,7 +17,7 @@ Signed-off-by: Birger Koblitz <git at birger-koblitz.de>
#define MDIO_PHYXS_VEND_IF_STATUS 0xe812
#define MDIO_PHYXS_VEND_IF_STATUS_TYPE_MASK GENMASK(7, 3)
-@@ -415,6 +416,49 @@ static int aqr107_read_rate(struct phy_d
+@@ -360,6 +361,49 @@ static int aqr107_read_rate(struct phy_d
return 0;
}
@@ -67,7 +67,7 @@ Signed-off-by: Birger Koblitz <git at birger-koblitz.de>
static int aqr107_read_status(struct phy_device *phydev)
{
int val, ret;
-@@ -554,7 +598,7 @@ static void aqr107_chip_info(struct phy_
+@@ -499,7 +543,7 @@ static void aqr107_chip_info(struct phy_
build_id = FIELD_GET(VEND1_GLOBAL_RSVD_STAT1_FW_BUILD_ID, val);
prov_id = FIELD_GET(VEND1_GLOBAL_RSVD_STAT1_PROV_ID, val);
@@ -76,7 +76,7 @@ Signed-off-by: Birger Koblitz <git at birger-koblitz.de>
fw_major, fw_minor, build_id, prov_id);
}
-@@ -811,7 +855,7 @@ static struct phy_driver aqr_driver[] =
+@@ -762,7 +806,7 @@ static struct phy_driver aqr_driver[] =
.config_aneg = aqr_config_aneg,
.config_intr = aqr_config_intr,
.handle_interrupt = aqr_handle_interrupt,
@@ -85,7 +85,7 @@ Signed-off-by: Birger Koblitz <git at birger-koblitz.de>
.get_tunable = aqr107_get_tunable,
.set_tunable = aqr107_set_tunable,
.suspend = aqr107_suspend,
-@@ -821,6 +865,24 @@ static struct phy_driver aqr_driver[] =
+@@ -772,6 +816,24 @@ static struct phy_driver aqr_driver[] =
.get_stats = aqr107_get_stats,
.link_change_notify = aqr107_link_change_notify,
},
@@ -110,7 +110,7 @@ Signed-off-by: Birger Koblitz <git at birger-koblitz.de>
};
module_phy_driver(aqr_driver);
-@@ -834,6 +896,7 @@ static struct mdio_device_id __maybe_unu
+@@ -785,6 +847,7 @@ static struct mdio_device_id __maybe_unu
{ PHY_ID_MATCH_MODEL(PHY_ID_AQCS109) },
{ PHY_ID_MATCH_MODEL(PHY_ID_AQR405) },
{ PHY_ID_MATCH_MODEL(PHY_ID_AQR113C) },
diff --git a/target/linux/generic/hack-5.15/722-net-phy-aquantia-enable-AQR112-and-AQR412.patch b/target/linux/generic/hack-5.15/722-net-phy-aquantia-enable-AQR112-and-AQR412.patch
index f80757cae9..6ec0db2526 100644
--- a/target/linux/generic/hack-5.15/722-net-phy-aquantia-enable-AQR112-and-AQR412.patch
+++ b/target/linux/generic/hack-5.15/722-net-phy-aquantia-enable-AQR112-and-AQR412.patch
@@ -10,11 +10,11 @@ different firmware on the PHY.
Signed-off-by: Alex Marginean <alexandru.marginean at nxp.com>
---
- drivers/net/phy/aquantia_main.c | 88 +++++++++++++++++++++++++++++++++++++++++
+ drivers/net/phy/aquantia/aquantia_main.c | 88 +++++++++++++++++++++++++++++++++++++++++
1 file changed, 88 insertions(+)
---- a/drivers/net/phy/aquantia_main.c
-+++ b/drivers/net/phy/aquantia_main.c
+--- a/drivers/net/phy/aquantia/aquantia_main.c
++++ b/drivers/net/phy/aquantia/aquantia_main.c
@@ -24,6 +24,8 @@
#define PHY_ID_AQR405 0x03a1b4b0
#define PHY_ID_AQR113C 0x31c31c12
@@ -24,7 +24,7 @@ Signed-off-by: Alex Marginean <alexandru.marginean at nxp.com>
#define MDIO_PHYXS_VEND_IF_STATUS 0xe812
#define MDIO_PHYXS_VEND_IF_STATUS_TYPE_MASK GENMASK(7, 3)
-@@ -151,6 +153,29 @@
+@@ -96,6 +98,29 @@
#define AQR107_OP_IN_PROG_SLEEP 1000
#define AQR107_OP_IN_PROG_TIMEOUT 100000
@@ -54,7 +54,7 @@ Signed-off-by: Alex Marginean <alexandru.marginean at nxp.com>
struct aqr107_hw_stat {
const char *name;
int reg;
-@@ -282,6 +307,51 @@ static int aqr_config_aneg(struct phy_de
+@@ -227,6 +252,51 @@ static int aqr_config_aneg(struct phy_de
return genphy_c45_check_and_restart_aneg(phydev, changed);
}
@@ -106,7 +106,7 @@ Signed-off-by: Alex Marginean <alexandru.marginean at nxp.com>
static int aqr_config_intr(struct phy_device *phydev)
{
bool en = phydev->interrupts == PHY_INTERRUPT_ENABLED;
-@@ -883,6 +953,30 @@ static struct phy_driver aqr_driver[] =
+@@ -834,6 +904,30 @@ static struct phy_driver aqr_driver[] =
.get_stats = aqr107_get_stats,
.link_change_notify = aqr107_link_change_notify,
},
@@ -137,7 +137,7 @@ Signed-off-by: Alex Marginean <alexandru.marginean at nxp.com>
};
module_phy_driver(aqr_driver);
-@@ -897,6 +991,8 @@ static struct mdio_device_id __maybe_unu
+@@ -848,6 +942,8 @@ static struct mdio_device_id __maybe_unu
{ PHY_ID_MATCH_MODEL(PHY_ID_AQR405) },
{ PHY_ID_MATCH_MODEL(PHY_ID_AQR113C) },
{ PHY_ID_MATCH_MODEL(PHY_ID_AQR813) },
diff --git a/target/linux/generic/hack-5.15/723-net-phy-aquantia-fix-system-side-protocol-mi.patch b/target/linux/generic/hack-5.15/723-net-phy-aquantia-fix-system-side-protocol-mi.patch
index 8e204cb146..33b182eab9 100644
--- a/target/linux/generic/hack-5.15/723-net-phy-aquantia-fix-system-side-protocol-mi.patch
+++ b/target/linux/generic/hack-5.15/723-net-phy-aquantia-fix-system-side-protocol-mi.patch
@@ -9,12 +9,12 @@ these protocols leads to link issues on system side.
Signed-off-by: Alex Marginean <alexandru.marginean at nxp.com>
---
- drivers/net/phy/aquantia_main.c | 8 +++++++-
+ drivers/net/phy/aquantia/aquantia_main.c | 8 +++++++-
1 file changed, 7 insertions(+), 1 deletion(-)
---- a/drivers/net/phy/aquantia_main.c
-+++ b/drivers/net/phy/aquantia_main.c
-@@ -340,10 +340,16 @@ static int aqr_config_aneg_set_prot(stru
+--- a/drivers/net/phy/aquantia/aquantia_main.c
++++ b/drivers/net/phy/aquantia/aquantia_main.c
+@@ -285,10 +285,16 @@ static int aqr_config_aneg_set_prot(stru
phy_write_mmd(phydev, MDIO_MMD_VEND1, AQUANTIA_VND1_GSTART_RATE,
aquantia_syscfg[if_type].start_rate);
diff --git a/target/linux/generic/hack-5.15/724-net-phy-aquantia-Add-AQR113-driver-support.patch b/target/linux/generic/hack-5.15/724-net-phy-aquantia-Add-AQR113-driver-support.patch
index f30e65101a..a31b327f9e 100644
--- a/target/linux/generic/hack-5.15/724-net-phy-aquantia-Add-AQR113-driver-support.patch
+++ b/target/linux/generic/hack-5.15/724-net-phy-aquantia-Add-AQR113-driver-support.patch
@@ -5,11 +5,11 @@ Subject: [PATCH] PONRTSYS-8842: aquantia: Add AQR113 driver support
Add a new entry for AQR113 PHY_ID
---
- drivers/net/phy/aquantia_main.c | 10 ++++++++++
+ drivers/net/phy/aquantia/aquantia_main.c | 10 ++++++++++
1 file changed, 10 insertions(+)
---- a/drivers/net/phy/aquantia_main.c
-+++ b/drivers/net/phy/aquantia_main.c
+--- a/drivers/net/phy/aquantia/aquantia_main.c
++++ b/drivers/net/phy/aquantia/aquantia_main.c
@@ -26,6 +26,7 @@
#define PHY_ID_AQR813 0x31c31cb2
#define PHY_ID_AQR112 0x03a1b662
@@ -18,7 +18,7 @@ Add a new entry for AQR113 PHY_ID
#define MDIO_PHYXS_VEND_IF_STATUS 0xe812
#define MDIO_PHYXS_VEND_IF_STATUS_TYPE_MASK GENMASK(7, 3)
-@@ -972,6 +973,14 @@ static struct phy_driver aqr_driver[] =
+@@ -923,6 +924,14 @@ static struct phy_driver aqr_driver[] =
.get_stats = aqr107_get_stats,
},
{
@@ -33,7 +33,7 @@ Add a new entry for AQR113 PHY_ID
PHY_ID_MATCH_MODEL(PHY_ID_AQR412),
.name = "Aquantia AQR412",
.probe = aqr107_probe,
-@@ -999,6 +1008,7 @@ static struct mdio_device_id __maybe_unu
+@@ -950,6 +959,7 @@ static struct mdio_device_id __maybe_unu
{ PHY_ID_MATCH_MODEL(PHY_ID_AQR813) },
{ PHY_ID_MATCH_MODEL(PHY_ID_AQR112) },
{ PHY_ID_MATCH_MODEL(PHY_ID_AQR412) },
diff --git a/target/linux/generic/hack-5.15/725-net-phy-aquantia-add-PHY_IDs-for-AQR112-variants.patch b/target/linux/generic/hack-5.15/725-net-phy-aquantia-add-PHY_IDs-for-AQR112-variants.patch
index ab674409d6..b2f79f4d58 100644
--- a/target/linux/generic/hack-5.15/725-net-phy-aquantia-add-PHY_IDs-for-AQR112-variants.patch
+++ b/target/linux/generic/hack-5.15/725-net-phy-aquantia-add-PHY_IDs-for-AQR112-variants.patch
@@ -7,11 +7,11 @@ As advised by Ian Chang this PHY is used in Puzzle devices.
Signed-off-by: Daniel Golle <daniel at makrotopia.org>
---
- drivers/net/phy/aquantia_main.c | 10 ++++++++++
+ drivers/net/phy/aquantia/aquantia_main.c | 10 ++++++++++
1 file changed, 10 insertions(+)
---- a/drivers/net/phy/aquantia_main.c
-+++ b/drivers/net/phy/aquantia_main.c
+--- a/drivers/net/phy/aquantia/aquantia_main.c
++++ b/drivers/net/phy/aquantia/aquantia_main.c
@@ -27,6 +27,8 @@
#define PHY_ID_AQR112 0x03a1b662
#define PHY_ID_AQR412 0x03a1b712
@@ -21,7 +21,7 @@ Signed-off-by: Daniel Golle <daniel at makrotopia.org>
#define MDIO_PHYXS_VEND_IF_STATUS 0xe812
#define MDIO_PHYXS_VEND_IF_STATUS_TYPE_MASK GENMASK(7, 3)
-@@ -973,6 +975,30 @@ static struct phy_driver aqr_driver[] =
+@@ -924,6 +926,30 @@ static struct phy_driver aqr_driver[] =
.get_stats = aqr107_get_stats,
},
{
@@ -52,7 +52,7 @@ Signed-off-by: Daniel Golle <daniel at makrotopia.org>
PHY_ID_MATCH_MODEL(PHY_ID_AQR113),
.name = "Aquantia AQR113",
.config_aneg = aqr_config_aneg,
-@@ -1009,6 +1035,8 @@ static struct mdio_device_id __maybe_unu
+@@ -960,6 +986,8 @@ static struct mdio_device_id __maybe_unu
{ PHY_ID_MATCH_MODEL(PHY_ID_AQR112) },
{ PHY_ID_MATCH_MODEL(PHY_ID_AQR412) },
{ PHY_ID_MATCH_MODEL(PHY_ID_AQR113) },
diff --git a/target/linux/ipq40xx/patches-5.15/708-net-phy-Add-Qualcom-QCA807x-driver.patch b/target/linux/ipq40xx/patches-5.15/708-net-phy-Add-Qualcom-QCA807x-driver.patch
index 6a92a103d6..d2179f1900 100644
--- a/target/linux/ipq40xx/patches-5.15/708-net-phy-Add-Qualcom-QCA807x-driver.patch
+++ b/target/linux/ipq40xx/patches-5.15/708-net-phy-Add-Qualcom-QCA807x-driver.patch
@@ -25,7 +25,7 @@ Signed-off-by: Robert Marko <robert.marko at sartura.hr>
--- a/drivers/net/phy/Kconfig
+++ b/drivers/net/phy/Kconfig
-@@ -347,6 +347,12 @@ config AT803X_PHY
+@@ -344,6 +344,12 @@ config AT803X_PHY
Currently supports the AR8030, AR8031, AR8033, AR8035 and internal
QCA8337(Internal qca8k PHY) model
@@ -40,7 +40,7 @@ Signed-off-by: Robert Marko <robert.marko at sartura.hr>
help
--- a/drivers/net/phy/Makefile
+++ b/drivers/net/phy/Makefile
-@@ -92,6 +92,7 @@ obj-$(CONFIG_NATIONAL_PHY) += national.o
+@@ -88,6 +88,7 @@ obj-$(CONFIG_NATIONAL_PHY) += national.o
obj-$(CONFIG_NXP_C45_TJA11XX_PHY) += nxp-c45-tja11xx.o
obj-$(CONFIG_NXP_TJA11XX_PHY) += nxp-tja11xx.o
obj-$(CONFIG_QSEMI_PHY) += qsemi.o
diff --git a/target/linux/mediatek/patches-5.15/500-gsw-rtl8367s-mt7622-support.patch b/target/linux/mediatek/patches-5.15/500-gsw-rtl8367s-mt7622-support.patch
index b8964f4e76..977bdeb5b1 100644
--- a/target/linux/mediatek/patches-5.15/500-gsw-rtl8367s-mt7622-support.patch
+++ b/target/linux/mediatek/patches-5.15/500-gsw-rtl8367s-mt7622-support.patch
@@ -1,6 +1,6 @@
--- a/drivers/net/phy/Kconfig
+++ b/drivers/net/phy/Kconfig
-@@ -367,6 +367,12 @@ config ROCKCHIP_PHY
+@@ -364,6 +364,12 @@ config ROCKCHIP_PHY
help
Currently supports the integrated Ethernet PHY.
@@ -15,7 +15,7 @@
help
--- a/drivers/net/phy/Makefile
+++ b/drivers/net/phy/Makefile
-@@ -95,6 +95,7 @@ obj-$(CONFIG_QSEMI_PHY) += qsemi.o
+@@ -91,6 +91,7 @@ obj-$(CONFIG_QSEMI_PHY) += qsemi.o
obj-$(CONFIG_REALTEK_PHY) += realtek.o
obj-$(CONFIG_RENESAS_PHY) += uPD60620.o
obj-$(CONFIG_ROCKCHIP_PHY) += rockchip.o
diff --git a/target/linux/mediatek/patches-5.15/730-v6.5-net-phy-add-driver-for-MediaTek-SoC-built-in-GE-PHYs.patch b/target/linux/mediatek/patches-5.15/730-v6.5-net-phy-add-driver-for-MediaTek-SoC-built-in-GE-PHYs.patch
index 9da2975582..72ad2a9846 100644
--- a/target/linux/mediatek/patches-5.15/730-v6.5-net-phy-add-driver-for-MediaTek-SoC-built-in-GE-PHYs.patch
+++ b/target/linux/mediatek/patches-5.15/730-v6.5-net-phy-add-driver-for-MediaTek-SoC-built-in-GE-PHYs.patch
@@ -42,7 +42,7 @@ Signed-off-by: David S. Miller <davem at davemloft.net>
L: linux-i2c at vger.kernel.org
--- a/drivers/net/phy/Kconfig
+++ b/drivers/net/phy/Kconfig
-@@ -293,6 +293,18 @@ config MEDIATEK_GE_PHY
+@@ -290,6 +290,18 @@ config MEDIATEK_GE_PHY
help
Supports the MediaTek Gigabit Ethernet PHYs.
@@ -63,7 +63,7 @@ Signed-off-by: David S. Miller <davem at davemloft.net>
help
--- a/drivers/net/phy/Makefile
+++ b/drivers/net/phy/Makefile
-@@ -81,6 +81,7 @@ obj-$(CONFIG_MARVELL_PHY) += marvell.o
+@@ -77,6 +77,7 @@ obj-$(CONFIG_MARVELL_PHY) += marvell.o
obj-$(CONFIG_MARVELL_88X2222_PHY) += marvell-88x2222.o
obj-$(CONFIG_MAXLINEAR_GPHY) += mxl-gpy.o
obj-$(CONFIG_MEDIATEK_GE_PHY) += mediatek-ge.o
diff --git a/target/linux/mediatek/patches-5.15/733-net-phy-add-driver-for-MediaTek-2.5G-PHY.patch b/target/linux/mediatek/patches-5.15/733-net-phy-add-driver-for-MediaTek-2.5G-PHY.patch
index 7151eb35cc..7600819246 100644
--- a/target/linux/mediatek/patches-5.15/733-net-phy-add-driver-for-MediaTek-2.5G-PHY.patch
+++ b/target/linux/mediatek/patches-5.15/733-net-phy-add-driver-for-MediaTek-2.5G-PHY.patch
@@ -13,7 +13,7 @@ Signed-off-by: Daniel Golle <daniel at makrotopia.org>
--- a/drivers/net/phy/Kconfig
+++ b/drivers/net/phy/Kconfig
-@@ -305,6 +305,13 @@ config MEDIATEK_GE_SOC_PHY
+@@ -302,6 +302,13 @@ config MEDIATEK_GE_SOC_PHY
present in the SoCs efuse and will dynamically calibrate VCM
(common-mode voltage) during startup.
@@ -29,7 +29,7 @@ Signed-off-by: Daniel Golle <daniel at makrotopia.org>
help
--- a/drivers/net/phy/Makefile
+++ b/drivers/net/phy/Makefile
-@@ -80,6 +80,7 @@ obj-$(CONFIG_MARVELL_10G_PHY) += marvell
+@@ -76,6 +76,7 @@ obj-$(CONFIG_MARVELL_10G_PHY) += marvell
obj-$(CONFIG_MARVELL_PHY) += marvell.o
obj-$(CONFIG_MARVELL_88X2222_PHY) += marvell-88x2222.o
obj-$(CONFIG_MAXLINEAR_GPHY) += mxl-gpy.o
diff --git a/target/linux/realtek/patches-5.15/705-add-rtl-phy.patch b/target/linux/realtek/patches-5.15/705-add-rtl-phy.patch
index 98c5e714b1..c6f8e6508b 100644
--- a/target/linux/realtek/patches-5.15/705-add-rtl-phy.patch
+++ b/target/linux/realtek/patches-5.15/705-add-rtl-phy.patch
@@ -14,7 +14,7 @@ Submitted-by: Birger Koblitz <mail at birger-koblitz.de>
--- a/drivers/net/phy/Kconfig
+++ b/drivers/net/phy/Kconfig
-@@ -357,6 +357,12 @@ config REALTEK_PHY
+@@ -354,6 +354,12 @@ config REALTEK_PHY
help
Supports the Realtek 821x PHY.
@@ -29,7 +29,7 @@ Submitted-by: Birger Koblitz <mail at birger-koblitz.de>
help
--- a/drivers/net/phy/Makefile
+++ b/drivers/net/phy/Makefile
-@@ -93,6 +93,7 @@ obj-$(CONFIG_NXP_C45_TJA11XX_PHY) += nxp
+@@ -89,6 +89,7 @@ obj-$(CONFIG_NXP_C45_TJA11XX_PHY) += nxp
obj-$(CONFIG_NXP_TJA11XX_PHY) += nxp-tja11xx.o
obj-$(CONFIG_QSEMI_PHY) += qsemi.o
obj-$(CONFIG_REALTEK_PHY) += realtek.o
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