[openwrt/openwrt] rockchip: backport driver updates for rk3588
LEDE Commits
lede-commits at lists.infradead.org
Tue Aug 20 15:12:27 PDT 2024
hauke pushed a commit to openwrt/openwrt.git, branch main:
https://git.openwrt.org/7108f5bd9f6b915ab093c4dda632f4e89fef6040
commit 7108f5bd9f6b915ab093c4dda632f4e89fef6040
Author: Tianling Shen <cnsztl at immortalwrt.org>
AuthorDate: Thu Jun 27 02:29:30 2024 +0800
rockchip: backport driver updates for rk3588
Backport upstreamed clk/mfd/phy/usb updates for rk3588.
Signed-off-by: Tianling Shen <cnsztl at immortalwrt.org>
Link: https://github.com/openwrt/openwrt/pull/16149
Signed-off-by: Hauke Mehrtens <hauke at hauke-m.de>
---
...clk-rockchip-rk3588-fix-CLK_NR_CLKS-usage.patch | 78 +
...dt-bindings-clock-rk3588-drop-CLK_NR_CLKS.patch | 27 +
...ings-clock-rk3588-add-missing-PCLK_VO1GRF.patch | 26 +
...ip-rk3588-fix-pclk_vo0grf-and-pclk_vo1grf.patch | 59 +
...30-05-v6.9-clk-rockchip-rk3588-fix-indent.patch | 26 +
...-rk3588-use-linked-clock-ID-for-GATE_LINK.patch | 78 +
...et-Define-reset-id-used-for-HDMI-Receiver.patch | 24 +
...p-rk3588-Add-reset-line-for-HDMI-Receiver.patch | 25 +
...pport-for-standard-system-power-controlle.patch | 28 +
...mfd-rk8xx-Add-support-for-RK806-power-off.patch | 29 +
...0-phy-rockchip-add-usbdp-combo-phy-driver.patch | 1670 ++++++++++++++++++++
...rockchip-usbdp-fix-uninitialized-variable.patch | 35 +
...-phy-rockchip-fix-CONFIG_TYPEC-dependency.patch | 43 +
...0-phy-rockchip-Fix-typo-in-function-names.patch | 79 +
...0-phy-rockchip-snps-pcie3-add-support-for.patch | 106 ++
...sb-dwc3-add-optional-PHY-interface-clocks.patch | 91 ++
16 files changed, 2424 insertions(+)
diff --git a/target/linux/rockchip/patches-6.6/030-01-v6.9-clk-rockchip-rk3588-fix-CLK_NR_CLKS-usage.patch b/target/linux/rockchip/patches-6.6/030-01-v6.9-clk-rockchip-rk3588-fix-CLK_NR_CLKS-usage.patch
new file mode 100644
index 0000000000..6becaf6e86
--- /dev/null
+++ b/target/linux/rockchip/patches-6.6/030-01-v6.9-clk-rockchip-rk3588-fix-CLK_NR_CLKS-usage.patch
@@ -0,0 +1,78 @@
+From 2dc66a5ab2c6fb532fbb16107ee7efcb0effbfa5 Mon Sep 17 00:00:00 2001
+From: Sebastian Reichel <sebastian.reichel at collabora.com>
+Date: Fri, 26 Jan 2024 19:18:22 +0100
+Subject: [PATCH] clk: rockchip: rk3588: fix CLK_NR_CLKS usage
+
+CLK_NR_CLKS is not part of the DT bindings and needs to be removed
+from it, just like it recently happened for other platforms. This
+takes care of it by introducing a new function identifying the
+maximum used clock ID at runtime.
+
+Signed-off-by: Sebastian Reichel <sebastian.reichel at collabora.com>
+Link: https://lore.kernel.org/r/20240126182919.48402-2-sebastian.reichel@collabora.com
+Signed-off-by: Heiko Stuebner <heiko at sntech.de>
+---
+ drivers/clk/rockchip/clk-rk3588.c | 5 ++++-
+ drivers/clk/rockchip/clk.c | 17 +++++++++++++++++
+ drivers/clk/rockchip/clk.h | 2 ++
+ 3 files changed, 23 insertions(+), 1 deletion(-)
+
+--- a/drivers/clk/rockchip/clk-rk3588.c
++++ b/drivers/clk/rockchip/clk-rk3588.c
+@@ -2458,15 +2458,18 @@ static struct rockchip_clk_branch rk3588
+ static void __init rk3588_clk_init(struct device_node *np)
+ {
+ struct rockchip_clk_provider *ctx;
++ unsigned long clk_nr_clks;
+ void __iomem *reg_base;
+
++ clk_nr_clks = rockchip_clk_find_max_clk_id(rk3588_clk_branches,
++ ARRAY_SIZE(rk3588_clk_branches)) + 1;
+ reg_base = of_iomap(np, 0);
+ if (!reg_base) {
+ pr_err("%s: could not map cru region\n", __func__);
+ return;
+ }
+
+- ctx = rockchip_clk_init(np, reg_base, CLK_NR_CLKS);
++ ctx = rockchip_clk_init(np, reg_base, clk_nr_clks);
+ if (IS_ERR(ctx)) {
+ pr_err("%s: rockchip clk init failed\n", __func__);
+ iounmap(reg_base);
+--- a/drivers/clk/rockchip/clk.c
++++ b/drivers/clk/rockchip/clk.c
+@@ -429,6 +429,23 @@ void rockchip_clk_register_plls(struct r
+ }
+ EXPORT_SYMBOL_GPL(rockchip_clk_register_plls);
+
++unsigned long rockchip_clk_find_max_clk_id(struct rockchip_clk_branch *list,
++ unsigned int nr_clk)
++{
++ unsigned long max = 0;
++ unsigned int idx;
++
++ for (idx = 0; idx < nr_clk; idx++, list++) {
++ if (list->id > max)
++ max = list->id;
++ if (list->child && list->child->id > max)
++ max = list->id;
++ }
++
++ return max;
++}
++EXPORT_SYMBOL_GPL(rockchip_clk_find_max_clk_id);
++
+ void rockchip_clk_register_branches(struct rockchip_clk_provider *ctx,
+ struct rockchip_clk_branch *list,
+ unsigned int nr_clk)
+--- a/drivers/clk/rockchip/clk.h
++++ b/drivers/clk/rockchip/clk.h
+@@ -973,6 +973,8 @@ struct rockchip_clk_provider *rockchip_c
+ void __iomem *base, unsigned long nr_clks);
+ void rockchip_clk_of_add_provider(struct device_node *np,
+ struct rockchip_clk_provider *ctx);
++unsigned long rockchip_clk_find_max_clk_id(struct rockchip_clk_branch *list,
++ unsigned int nr_clk);
+ void rockchip_clk_register_branches(struct rockchip_clk_provider *ctx,
+ struct rockchip_clk_branch *list,
+ unsigned int nr_clk);
diff --git a/target/linux/rockchip/patches-6.6/030-02-v6.9-dt-bindings-clock-rk3588-drop-CLK_NR_CLKS.patch b/target/linux/rockchip/patches-6.6/030-02-v6.9-dt-bindings-clock-rk3588-drop-CLK_NR_CLKS.patch
new file mode 100644
index 0000000000..c8117f08c5
--- /dev/null
+++ b/target/linux/rockchip/patches-6.6/030-02-v6.9-dt-bindings-clock-rk3588-drop-CLK_NR_CLKS.patch
@@ -0,0 +1,27 @@
+From 11a29dc2e41ead2be78cfa9d532edf924b461acc Mon Sep 17 00:00:00 2001
+From: Sebastian Reichel <sebastian.reichel at collabora.com>
+Date: Fri, 26 Jan 2024 19:18:23 +0100
+Subject: [PATCH] dt-bindings: clock: rk3588: drop CLK_NR_CLKS
+
+CLK_NR_CLKS should not be part of the binding. Let's drop it, since
+the kernel code no longer uses it either.
+
+Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski at linaro.org>
+Signed-off-by: Sebastian Reichel <sebastian.reichel at collabora.com>
+Link: https://lore.kernel.org/r/20240126182919.48402-3-sebastian.reichel@collabora.com
+Signed-off-by: Heiko Stuebner <heiko at sntech.de>
+---
+ include/dt-bindings/clock/rockchip,rk3588-cru.h | 2 --
+ 1 file changed, 2 deletions(-)
+
+--- a/include/dt-bindings/clock/rockchip,rk3588-cru.h
++++ b/include/dt-bindings/clock/rockchip,rk3588-cru.h
+@@ -734,8 +734,6 @@
+ #define PCLK_AV1_PRE 719
+ #define HCLK_SDIO_PRE 720
+
+-#define CLK_NR_CLKS (HCLK_SDIO_PRE + 1)
+-
+ /* scmi-clocks indices */
+
+ #define SCMI_CLK_CPUL 0
diff --git a/target/linux/rockchip/patches-6.6/030-03-v6.9-dt-bindings-clock-rk3588-add-missing-PCLK_VO1GRF.patch b/target/linux/rockchip/patches-6.6/030-03-v6.9-dt-bindings-clock-rk3588-add-missing-PCLK_VO1GRF.patch
new file mode 100644
index 0000000000..b960bc6197
--- /dev/null
+++ b/target/linux/rockchip/patches-6.6/030-03-v6.9-dt-bindings-clock-rk3588-add-missing-PCLK_VO1GRF.patch
@@ -0,0 +1,26 @@
+From c81798cf9dd2f324934585b2b52a0398caefb88e Mon Sep 17 00:00:00 2001
+From: Sebastian Reichel <sebastian.reichel at collabora.com>
+Date: Fri, 26 Jan 2024 19:18:24 +0100
+Subject: [PATCH] dt-bindings: clock: rk3588: add missing PCLK_VO1GRF
+
+Add PCLK_VO1GRF to complement PCLK_VO0GRF. This will be needed
+for HDMI support.
+
+Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski at linaro.org>
+Signed-off-by: Sebastian Reichel <sebastian.reichel at collabora.com>
+Link: https://lore.kernel.org/r/20240126182919.48402-4-sebastian.reichel@collabora.com
+Signed-off-by: Heiko Stuebner <heiko at sntech.de>
+---
+ include/dt-bindings/clock/rockchip,rk3588-cru.h | 1 +
+ 1 file changed, 1 insertion(+)
+
+--- a/include/dt-bindings/clock/rockchip,rk3588-cru.h
++++ b/include/dt-bindings/clock/rockchip,rk3588-cru.h
+@@ -733,6 +733,7 @@
+ #define ACLK_AV1_PRE 718
+ #define PCLK_AV1_PRE 719
+ #define HCLK_SDIO_PRE 720
++#define PCLK_VO1GRF 721
+
+ /* scmi-clocks indices */
+
diff --git a/target/linux/rockchip/patches-6.6/030-04-v6.9-clk-rockchip-rk3588-fix-pclk_vo0grf-and-pclk_vo1grf.patch b/target/linux/rockchip/patches-6.6/030-04-v6.9-clk-rockchip-rk3588-fix-pclk_vo0grf-and-pclk_vo1grf.patch
new file mode 100644
index 0000000000..e12b73fb30
--- /dev/null
+++ b/target/linux/rockchip/patches-6.6/030-04-v6.9-clk-rockchip-rk3588-fix-pclk_vo0grf-and-pclk_vo1grf.patch
@@ -0,0 +1,59 @@
+From 326be62eaf2e89767b7b9223f88eaf3c041b98d2 Mon Sep 17 00:00:00 2001
+From: Sebastian Reichel <sebastian.reichel at collabora.com>
+Date: Fri, 26 Jan 2024 19:18:25 +0100
+Subject: [PATCH] clk: rockchip: rk3588: fix pclk_vo0grf and pclk_vo1grf
+
+Currently pclk_vo1grf is not exposed, but it should be referenced
+from the vo1_grf syscon, which needs it enabled. That syscon is
+required for HDMI RX and TX functionality among other things.
+
+Apart from that pclk_vo0grf and pclk_vo1grf are both linked gates
+and need the VO's hclk enabled in addition to their parent clock.
+
+No Fixes tag has been added, since the logic requiring these clocks
+is not yet upstream anyways.
+
+Signed-off-by: Sebastian Reichel <sebastian.reichel at collabora.com>
+Link: https://lore.kernel.org/r/20240126182919.48402-5-sebastian.reichel@collabora.com
+Signed-off-by: Heiko Stuebner <heiko at sntech.de>
+---
+ drivers/clk/rockchip/clk-rk3588.c | 10 ++++------
+ 1 file changed, 4 insertions(+), 6 deletions(-)
+
+--- a/drivers/clk/rockchip/clk-rk3588.c
++++ b/drivers/clk/rockchip/clk-rk3588.c
+@@ -1851,8 +1851,6 @@ static struct rockchip_clk_branch rk3588
+ RK3588_CLKGATE_CON(56), 0, GFLAGS),
+ GATE(PCLK_TRNG0, "pclk_trng0", "pclk_vo0_root", 0,
+ RK3588_CLKGATE_CON(56), 1, GFLAGS),
+- GATE(PCLK_VO0GRF, "pclk_vo0grf", "pclk_vo0_root", CLK_IGNORE_UNUSED,
+- RK3588_CLKGATE_CON(55), 10, GFLAGS),
+ COMPOSITE(CLK_I2S4_8CH_TX_SRC, "clk_i2s4_8ch_tx_src", gpll_aupll_p, 0,
+ RK3588_CLKSEL_CON(118), 5, 1, MFLAGS, 0, 5, DFLAGS,
+ RK3588_CLKGATE_CON(56), 11, GFLAGS),
+@@ -1998,8 +1996,6 @@ static struct rockchip_clk_branch rk3588
+ RK3588_CLKGATE_CON(60), 9, GFLAGS),
+ GATE(PCLK_TRNG1, "pclk_trng1", "pclk_vo1_root", 0,
+ RK3588_CLKGATE_CON(60), 10, GFLAGS),
+- GATE(0, "pclk_vo1grf", "pclk_vo1_root", CLK_IGNORE_UNUSED,
+- RK3588_CLKGATE_CON(59), 12, GFLAGS),
+ GATE(PCLK_S_EDP0, "pclk_s_edp0", "pclk_vo1_s_root", 0,
+ RK3588_CLKGATE_CON(59), 14, GFLAGS),
+ GATE(PCLK_S_EDP1, "pclk_s_edp1", "pclk_vo1_s_root", 0,
+@@ -2447,12 +2443,14 @@ static struct rockchip_clk_branch rk3588
+ GATE_LINK(HCLK_RKVDEC1_PRE, "hclk_rkvdec1_pre", "hclk_rkvdec1_root", "hclk_vdpu_root", 0, RK3588_CLKGATE_CON(41), 4, GFLAGS),
+ GATE_LINK(ACLK_RKVDEC1_PRE, "aclk_rkvdec1_pre", "aclk_rkvdec1_root", "aclk_vdpu_root", 0, RK3588_CLKGATE_CON(41), 5, GFLAGS),
+ GATE_LINK(ACLK_HDCP0_PRE, "aclk_hdcp0_pre", "aclk_vo0_root", "aclk_vop_low_root", 0, RK3588_CLKGATE_CON(55), 9, GFLAGS),
+- GATE_LINK(HCLK_VO0, "hclk_vo0", "hclk_vo0_root", "hclk_vop_root", 0, RK3588_CLKGATE_CON(55), 5, GFLAGS),
++ GATE_LINK(HCLK_VO0, "hclk_vo0", "hclk_vo0_root", "hclk_vop_root", RK3588_LINKED_CLK, RK3588_CLKGATE_CON(55), 5, GFLAGS),
+ GATE_LINK(ACLK_HDCP1_PRE, "aclk_hdcp1_pre", "aclk_hdcp1_root", "aclk_vo1usb_top_root", 0, RK3588_CLKGATE_CON(59), 6, GFLAGS),
+- GATE_LINK(HCLK_VO1, "hclk_vo1", "hclk_vo1_root", "hclk_vo1usb_top_root", 0, RK3588_CLKGATE_CON(59), 9, GFLAGS),
++ GATE_LINK(HCLK_VO1, "hclk_vo1", "hclk_vo1_root", "hclk_vo1usb_top_root", RK3588_LINKED_CLK, RK3588_CLKGATE_CON(59), 9, GFLAGS),
+ GATE_LINK(ACLK_AV1_PRE, "aclk_av1_pre", "aclk_av1_root", "aclk_vdpu_root", 0, RK3588_CLKGATE_CON(68), 1, GFLAGS),
+ GATE_LINK(PCLK_AV1_PRE, "pclk_av1_pre", "pclk_av1_root", "hclk_vdpu_root", 0, RK3588_CLKGATE_CON(68), 4, GFLAGS),
+ GATE_LINK(HCLK_SDIO_PRE, "hclk_sdio_pre", "hclk_sdio_root", "hclk_nvm", 0, RK3588_CLKGATE_CON(75), 1, GFLAGS),
++ GATE_LINK(PCLK_VO0GRF, "pclk_vo0grf", "pclk_vo0_root", "hclk_vo0", CLK_IGNORE_UNUSED, RK3588_CLKGATE_CON(55), 10, GFLAGS),
++ GATE_LINK(PCLK_VO1GRF, "pclk_vo1grf", "pclk_vo1_root", "hclk_vo1", CLK_IGNORE_UNUSED, RK3588_CLKGATE_CON(59), 12, GFLAGS),
+ };
+
+ static void __init rk3588_clk_init(struct device_node *np)
diff --git a/target/linux/rockchip/patches-6.6/030-05-v6.9-clk-rockchip-rk3588-fix-indent.patch b/target/linux/rockchip/patches-6.6/030-05-v6.9-clk-rockchip-rk3588-fix-indent.patch
new file mode 100644
index 0000000000..27aa28edd5
--- /dev/null
+++ b/target/linux/rockchip/patches-6.6/030-05-v6.9-clk-rockchip-rk3588-fix-indent.patch
@@ -0,0 +1,26 @@
+From 2a6e4710672242281347103b64e01693aa823a29 Mon Sep 17 00:00:00 2001
+From: Sebastian Reichel <sebastian.reichel at collabora.com>
+Date: Fri, 26 Jan 2024 19:18:26 +0100
+Subject: [PATCH] clk: rockchip: rk3588: fix indent
+
+pclk_mailbox2 is the only RK3588 clock indented with one tab instead of
+two tabs. Let's fix this.
+
+Signed-off-by: Sebastian Reichel <sebastian.reichel at collabora.com>
+Link: https://lore.kernel.org/r/20240126182919.48402-6-sebastian.reichel@collabora.com
+Signed-off-by: Heiko Stuebner <heiko at sntech.de>
+---
+ drivers/clk/rockchip/clk-rk3588.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/drivers/clk/rockchip/clk-rk3588.c
++++ b/drivers/clk/rockchip/clk-rk3588.c
+@@ -1004,7 +1004,7 @@ static struct rockchip_clk_branch rk3588
+ GATE(PCLK_MAILBOX1, "pclk_mailbox1", "pclk_top_root", 0,
+ RK3588_CLKGATE_CON(16), 12, GFLAGS),
+ GATE(PCLK_MAILBOX2, "pclk_mailbox2", "pclk_top_root", 0,
+- RK3588_CLKGATE_CON(16), 13, GFLAGS),
++ RK3588_CLKGATE_CON(16), 13, GFLAGS),
+ GATE(PCLK_PMU2, "pclk_pmu2", "pclk_top_root", CLK_IS_CRITICAL,
+ RK3588_CLKGATE_CON(19), 3, GFLAGS),
+ GATE(PCLK_PMUCM0_INTMUX, "pclk_pmucm0_intmux", "pclk_top_root", CLK_IS_CRITICAL,
diff --git a/target/linux/rockchip/patches-6.6/030-06-v6.9-clk-rockchip-rk3588-use-linked-clock-ID-for-GATE_LINK.patch b/target/linux/rockchip/patches-6.6/030-06-v6.9-clk-rockchip-rk3588-use-linked-clock-ID-for-GATE_LINK.patch
new file mode 100644
index 0000000000..949041fb9f
--- /dev/null
+++ b/target/linux/rockchip/patches-6.6/030-06-v6.9-clk-rockchip-rk3588-use-linked-clock-ID-for-GATE_LINK.patch
@@ -0,0 +1,78 @@
+From dae3e57000fb2d6f491e3ee2956f5918326d6b72 Mon Sep 17 00:00:00 2001
+From: Sebastian Reichel <sebastian.reichel at collabora.com>
+Date: Fri, 26 Jan 2024 19:18:27 +0100
+Subject: [PATCH] clk: rockchip: rk3588: use linked clock ID for GATE_LINK
+
+In preparation for properly supporting GATE_LINK switch the unused
+linked clock argument from the clock's name to its ID. This allows
+easy and fast lookup of the 'struct clk'.
+
+Signed-off-by: Sebastian Reichel <sebastian.reichel at collabora.com>
+Link: https://lore.kernel.org/r/20240126182919.48402-7-sebastian.reichel@collabora.com
+Signed-off-by: Heiko Stuebner <heiko at sntech.de>
+---
+ drivers/clk/rockchip/clk-rk3588.c | 46 +++++++++++++++----------------
+ 1 file changed, 23 insertions(+), 23 deletions(-)
+
+--- a/drivers/clk/rockchip/clk-rk3588.c
++++ b/drivers/clk/rockchip/clk-rk3588.c
+@@ -29,7 +29,7 @@
+ * power, but avoids leaking implementation details into DT or hanging the
+ * system.
+ */
+-#define GATE_LINK(_id, cname, pname, linkname, f, o, b, gf) \
++#define GATE_LINK(_id, cname, pname, linkedclk, f, o, b, gf) \
+ GATE(_id, cname, pname, f, o, b, gf)
+ #define RK3588_LINKED_CLK CLK_IS_CRITICAL
+
+@@ -2429,28 +2429,28 @@ static struct rockchip_clk_branch rk3588
+ GATE(ACLK_AV1, "aclk_av1", "aclk_av1_pre", 0,
+ RK3588_CLKGATE_CON(68), 2, GFLAGS),
+
+- GATE_LINK(ACLK_ISP1_PRE, "aclk_isp1_pre", "aclk_isp1_root", "aclk_vi_root", 0, RK3588_CLKGATE_CON(26), 6, GFLAGS),
+- GATE_LINK(HCLK_ISP1_PRE, "hclk_isp1_pre", "hclk_isp1_root", "hclk_vi_root", 0, RK3588_CLKGATE_CON(26), 8, GFLAGS),
+- GATE_LINK(HCLK_NVM, "hclk_nvm", "hclk_nvm_root", "aclk_nvm_root", RK3588_LINKED_CLK, RK3588_CLKGATE_CON(31), 2, GFLAGS),
+- GATE_LINK(ACLK_USB, "aclk_usb", "aclk_usb_root", "aclk_vo1usb_top_root", 0, RK3588_CLKGATE_CON(42), 2, GFLAGS),
+- GATE_LINK(HCLK_USB, "hclk_usb", "hclk_usb_root", "hclk_vo1usb_top_root", 0, RK3588_CLKGATE_CON(42), 3, GFLAGS),
+- GATE_LINK(ACLK_JPEG_DECODER_PRE, "aclk_jpeg_decoder_pre", "aclk_jpeg_decoder_root", "aclk_vdpu_root", 0, RK3588_CLKGATE_CON(44), 7, GFLAGS),
+- GATE_LINK(ACLK_VDPU_LOW_PRE, "aclk_vdpu_low_pre", "aclk_vdpu_low_root", "aclk_vdpu_root", 0, RK3588_CLKGATE_CON(44), 5, GFLAGS),
+- GATE_LINK(ACLK_RKVENC1_PRE, "aclk_rkvenc1_pre", "aclk_rkvenc1_root", "aclk_rkvenc0", 0, RK3588_CLKGATE_CON(48), 3, GFLAGS),
+- GATE_LINK(HCLK_RKVENC1_PRE, "hclk_rkvenc1_pre", "hclk_rkvenc1_root", "hclk_rkvenc0", 0, RK3588_CLKGATE_CON(48), 2, GFLAGS),
+- GATE_LINK(HCLK_RKVDEC0_PRE, "hclk_rkvdec0_pre", "hclk_rkvdec0_root", "hclk_vdpu_root", 0, RK3588_CLKGATE_CON(40), 5, GFLAGS),
+- GATE_LINK(ACLK_RKVDEC0_PRE, "aclk_rkvdec0_pre", "aclk_rkvdec0_root", "aclk_vdpu_root", 0, RK3588_CLKGATE_CON(40), 6, GFLAGS),
+- GATE_LINK(HCLK_RKVDEC1_PRE, "hclk_rkvdec1_pre", "hclk_rkvdec1_root", "hclk_vdpu_root", 0, RK3588_CLKGATE_CON(41), 4, GFLAGS),
+- GATE_LINK(ACLK_RKVDEC1_PRE, "aclk_rkvdec1_pre", "aclk_rkvdec1_root", "aclk_vdpu_root", 0, RK3588_CLKGATE_CON(41), 5, GFLAGS),
+- GATE_LINK(ACLK_HDCP0_PRE, "aclk_hdcp0_pre", "aclk_vo0_root", "aclk_vop_low_root", 0, RK3588_CLKGATE_CON(55), 9, GFLAGS),
+- GATE_LINK(HCLK_VO0, "hclk_vo0", "hclk_vo0_root", "hclk_vop_root", RK3588_LINKED_CLK, RK3588_CLKGATE_CON(55), 5, GFLAGS),
+- GATE_LINK(ACLK_HDCP1_PRE, "aclk_hdcp1_pre", "aclk_hdcp1_root", "aclk_vo1usb_top_root", 0, RK3588_CLKGATE_CON(59), 6, GFLAGS),
+- GATE_LINK(HCLK_VO1, "hclk_vo1", "hclk_vo1_root", "hclk_vo1usb_top_root", RK3588_LINKED_CLK, RK3588_CLKGATE_CON(59), 9, GFLAGS),
+- GATE_LINK(ACLK_AV1_PRE, "aclk_av1_pre", "aclk_av1_root", "aclk_vdpu_root", 0, RK3588_CLKGATE_CON(68), 1, GFLAGS),
+- GATE_LINK(PCLK_AV1_PRE, "pclk_av1_pre", "pclk_av1_root", "hclk_vdpu_root", 0, RK3588_CLKGATE_CON(68), 4, GFLAGS),
+- GATE_LINK(HCLK_SDIO_PRE, "hclk_sdio_pre", "hclk_sdio_root", "hclk_nvm", 0, RK3588_CLKGATE_CON(75), 1, GFLAGS),
+- GATE_LINK(PCLK_VO0GRF, "pclk_vo0grf", "pclk_vo0_root", "hclk_vo0", CLK_IGNORE_UNUSED, RK3588_CLKGATE_CON(55), 10, GFLAGS),
+- GATE_LINK(PCLK_VO1GRF, "pclk_vo1grf", "pclk_vo1_root", "hclk_vo1", CLK_IGNORE_UNUSED, RK3588_CLKGATE_CON(59), 12, GFLAGS),
++ GATE_LINK(ACLK_ISP1_PRE, "aclk_isp1_pre", "aclk_isp1_root", ACLK_VI_ROOT, 0, RK3588_CLKGATE_CON(26), 6, GFLAGS),
++ GATE_LINK(HCLK_ISP1_PRE, "hclk_isp1_pre", "hclk_isp1_root", HCLK_VI_ROOT, 0, RK3588_CLKGATE_CON(26), 8, GFLAGS),
++ GATE_LINK(HCLK_NVM, "hclk_nvm", "hclk_nvm_root", ACLK_NVM_ROOT, RK3588_LINKED_CLK, RK3588_CLKGATE_CON(31), 2, GFLAGS),
++ GATE_LINK(ACLK_USB, "aclk_usb", "aclk_usb_root", ACLK_VO1USB_TOP_ROOT, 0, RK3588_CLKGATE_CON(42), 2, GFLAGS),
++ GATE_LINK(HCLK_USB, "hclk_usb", "hclk_usb_root", HCLK_VO1USB_TOP_ROOT, 0, RK3588_CLKGATE_CON(42), 3, GFLAGS),
++ GATE_LINK(ACLK_JPEG_DECODER_PRE, "aclk_jpeg_decoder_pre", "aclk_jpeg_decoder_root", ACLK_VDPU_ROOT, 0, RK3588_CLKGATE_CON(44), 7, GFLAGS),
++ GATE_LINK(ACLK_VDPU_LOW_PRE, "aclk_vdpu_low_pre", "aclk_vdpu_low_root", ACLK_VDPU_ROOT, 0, RK3588_CLKGATE_CON(44), 5, GFLAGS),
++ GATE_LINK(ACLK_RKVENC1_PRE, "aclk_rkvenc1_pre", "aclk_rkvenc1_root", ACLK_RKVENC0, 0, RK3588_CLKGATE_CON(48), 3, GFLAGS),
++ GATE_LINK(HCLK_RKVENC1_PRE, "hclk_rkvenc1_pre", "hclk_rkvenc1_root", HCLK_RKVENC0, 0, RK3588_CLKGATE_CON(48), 2, GFLAGS),
++ GATE_LINK(HCLK_RKVDEC0_PRE, "hclk_rkvdec0_pre", "hclk_rkvdec0_root", HCLK_VDPU_ROOT, 0, RK3588_CLKGATE_CON(40), 5, GFLAGS),
++ GATE_LINK(ACLK_RKVDEC0_PRE, "aclk_rkvdec0_pre", "aclk_rkvdec0_root", ACLK_VDPU_ROOT, 0, RK3588_CLKGATE_CON(40), 6, GFLAGS),
++ GATE_LINK(HCLK_RKVDEC1_PRE, "hclk_rkvdec1_pre", "hclk_rkvdec1_root", HCLK_VDPU_ROOT, 0, RK3588_CLKGATE_CON(41), 4, GFLAGS),
++ GATE_LINK(ACLK_RKVDEC1_PRE, "aclk_rkvdec1_pre", "aclk_rkvdec1_root", ACLK_VDPU_ROOT, 0, RK3588_CLKGATE_CON(41), 5, GFLAGS),
++ GATE_LINK(ACLK_HDCP0_PRE, "aclk_hdcp0_pre", "aclk_vo0_root", ACLK_VOP_LOW_ROOT, 0, RK3588_CLKGATE_CON(55), 9, GFLAGS),
++ GATE_LINK(HCLK_VO0, "hclk_vo0", "hclk_vo0_root", HCLK_VOP_ROOT, RK3588_LINKED_CLK, RK3588_CLKGATE_CON(55), 5, GFLAGS),
++ GATE_LINK(ACLK_HDCP1_PRE, "aclk_hdcp1_pre", "aclk_hdcp1_root", ACLK_VO1USB_TOP_ROOT, 0, RK3588_CLKGATE_CON(59), 6, GFLAGS),
++ GATE_LINK(HCLK_VO1, "hclk_vo1", "hclk_vo1_root", HCLK_VO1USB_TOP_ROOT, RK3588_LINKED_CLK, RK3588_CLKGATE_CON(59), 9, GFLAGS),
++ GATE_LINK(ACLK_AV1_PRE, "aclk_av1_pre", "aclk_av1_root", ACLK_VDPU_ROOT, 0, RK3588_CLKGATE_CON(68), 1, GFLAGS),
++ GATE_LINK(PCLK_AV1_PRE, "pclk_av1_pre", "pclk_av1_root", HCLK_VDPU_ROOT, 0, RK3588_CLKGATE_CON(68), 4, GFLAGS),
++ GATE_LINK(HCLK_SDIO_PRE, "hclk_sdio_pre", "hclk_sdio_root", HCLK_NVM, 0, RK3588_CLKGATE_CON(75), 1, GFLAGS),
++ GATE_LINK(PCLK_VO0GRF, "pclk_vo0grf", "pclk_vo0_root", HCLK_VO0, CLK_IGNORE_UNUSED, RK3588_CLKGATE_CON(55), 10, GFLAGS),
++ GATE_LINK(PCLK_VO1GRF, "pclk_vo1grf", "pclk_vo1_root", HCLK_VO1, CLK_IGNORE_UNUSED, RK3588_CLKGATE_CON(59), 12, GFLAGS),
+ };
+
+ static void __init rk3588_clk_init(struct device_node *np)
diff --git a/target/linux/rockchip/patches-6.6/030-07-v6.10-dt-bindings-reset-Define-reset-id-used-for-HDMI-Receiver.patch b/target/linux/rockchip/patches-6.6/030-07-v6.10-dt-bindings-reset-Define-reset-id-used-for-HDMI-Receiver.patch
new file mode 100644
index 0000000000..0b9082f9b6
--- /dev/null
+++ b/target/linux/rockchip/patches-6.6/030-07-v6.10-dt-bindings-reset-Define-reset-id-used-for-HDMI-Receiver.patch
@@ -0,0 +1,24 @@
+From ca151fd56b5736a7adbdba5675b9d87d70f20b23 Mon Sep 17 00:00:00 2001
+From: Shreeya Patel <shreeya.patel at collabora.com>
+Date: Thu, 28 Mar 2024 04:20:52 +0530
+Subject: [PATCH] dt-bindings: reset: Define reset id used for HDMI Receiver
+
+Add reset id used for HDMI Receiver in RK3588 SoCs
+
+Acked-by: Rob Herring <robh at kernel.org>
+Signed-off-by: Shreeya Patel <shreeya.patel at collabora.com>
+Link: https://lore.kernel.org/r/20240327225057.672304-2-shreeya.patel@collabora.com
+Signed-off-by: Heiko Stuebner <heiko at sntech.de>
+---
+ include/dt-bindings/reset/rockchip,rk3588-cru.h | 2 ++
+ 1 file changed, 2 insertions(+)
+
+--- a/include/dt-bindings/reset/rockchip,rk3588-cru.h
++++ b/include/dt-bindings/reset/rockchip,rk3588-cru.h
+@@ -751,4 +751,6 @@
+ #define SRST_P_TRNG_CHK 658
+ #define SRST_TRNG_S 659
+
++#define SRST_A_HDMIRX_BIU 660
++
+ #endif
diff --git a/target/linux/rockchip/patches-6.6/030-08-v6.10-clk-rockchip-rk3588-Add-reset-line-for-HDMI-Receiver.patch b/target/linux/rockchip/patches-6.6/030-08-v6.10-clk-rockchip-rk3588-Add-reset-line-for-HDMI-Receiver.patch
new file mode 100644
index 0000000000..6aa9c058a3
--- /dev/null
+++ b/target/linux/rockchip/patches-6.6/030-08-v6.10-clk-rockchip-rk3588-Add-reset-line-for-HDMI-Receiver.patch
@@ -0,0 +1,25 @@
+From 7af67019cd78d028ef377df689ac103d51905518 Mon Sep 17 00:00:00 2001
+From: Shreeya Patel <shreeya.patel at collabora.com>
+Date: Thu, 28 Mar 2024 04:20:53 +0530
+Subject: [PATCH] clk: rockchip: rk3588: Add reset line for HDMI Receiver
+
+Export hdmirx_biu reset line required by the Synopsys
+DesignWare HDMIRX Controller.
+
+Signed-off-by: Shreeya Patel <shreeya.patel at collabora.com>
+Link: https://lore.kernel.org/r/20240327225057.672304-3-shreeya.patel@collabora.com
+Signed-off-by: Heiko Stuebner <heiko at sntech.de>
+---
+ drivers/clk/rockchip/rst-rk3588.c | 1 +
+ 1 file changed, 1 insertion(+)
+
+--- a/drivers/clk/rockchip/rst-rk3588.c
++++ b/drivers/clk/rockchip/rst-rk3588.c
+@@ -577,6 +577,7 @@ static const int rk3588_register_offset[
+
+ /* SOFTRST_CON59 */
+ RK3588_CRU_RESET_OFFSET(SRST_A_HDCP1_BIU, 59, 6),
++ RK3588_CRU_RESET_OFFSET(SRST_A_HDMIRX_BIU, 59, 7),
+ RK3588_CRU_RESET_OFFSET(SRST_A_VO1_BIU, 59, 8),
+ RK3588_CRU_RESET_OFFSET(SRST_H_VOP1_BIU, 59, 9),
+ RK3588_CRU_RESET_OFFSET(SRST_H_VOP1_S_BIU, 59, 10),
diff --git a/target/linux/rockchip/patches-6.6/031-01-v6.7-mfd-rk8xx-Add-support-for-standard-system-power-controlle.patch b/target/linux/rockchip/patches-6.6/031-01-v6.7-mfd-rk8xx-Add-support-for-standard-system-power-controlle.patch
new file mode 100644
index 0000000000..94d998fe93
--- /dev/null
+++ b/target/linux/rockchip/patches-6.6/031-01-v6.7-mfd-rk8xx-Add-support-for-standard-system-power-controlle.patch
@@ -0,0 +1,28 @@
+From 2a46cd97f401a669d71b3d36b78bd6653f8424ee Mon Sep 17 00:00:00 2001
+From: Ondrej Jirman <megi at xff.cz>
+Date: Thu, 19 Oct 2023 18:57:25 +0200
+Subject: [PATCH] mfd: rk8xx: Add support for standard system-power-controller
+ property
+
+DT property rockchip,system-power-controller is now deprecated.
+
+Signed-off-by: Ondrej Jirman <megi at xff.cz>
+Reviewed-by: Sebastian Reichel <sebastian.reichel at collabora.com>
+Link: https://lore.kernel.org/r/20231019165732.3818789-4-megi@xff.cz
+Signed-off-by: Lee Jones <lee at kernel.org>
+---
+ drivers/mfd/rk8xx-core.c | 3 ++-
+ 1 file changed, 2 insertions(+), 1 deletion(-)
+
+--- a/drivers/mfd/rk8xx-core.c
++++ b/drivers/mfd/rk8xx-core.c
+@@ -677,7 +677,8 @@ int rk8xx_probe(struct device *dev, int
+ if (ret)
+ return dev_err_probe(dev, ret, "failed to add MFD devices\n");
+
+- if (device_property_read_bool(dev, "rockchip,system-power-controller")) {
++ if (device_property_read_bool(dev, "rockchip,system-power-controller") ||
++ device_property_read_bool(dev, "system-power-controller")) {
+ ret = devm_register_sys_off_handler(dev,
+ SYS_OFF_MODE_POWER_OFF_PREPARE, SYS_OFF_PRIO_HIGH,
+ &rk808_power_off, rk808);
diff --git a/target/linux/rockchip/patches-6.6/031-02-v6.7-mfd-rk8xx-Add-support-for-RK806-power-off.patch b/target/linux/rockchip/patches-6.6/031-02-v6.7-mfd-rk8xx-Add-support-for-RK806-power-off.patch
new file mode 100644
index 0000000000..2ac0ff537e
--- /dev/null
+++ b/target/linux/rockchip/patches-6.6/031-02-v6.7-mfd-rk8xx-Add-support-for-RK806-power-off.patch
@@ -0,0 +1,29 @@
+From b0227e7081404448a0059b8698fdffd2dec280d2 Mon Sep 17 00:00:00 2001
+From: Ondrej Jirman <megi at xff.cz>
+Date: Thu, 19 Oct 2023 18:57:26 +0200
+Subject: [PATCH] mfd: rk8xx: Add support for RK806 power off
+
+Use DEV_OFF bit to power off the RK806 PMIC, when system-power-controller
+is used in DTS.
+
+Signed-off-by: Ondrej Jirman <megi at xff.cz>
+Reviewed-by: Sebastian Reichel <sebastian.reichel at collabora.com>
+Link: https://lore.kernel.org/r/20231019165732.3818789-5-megi@xff.cz
+Signed-off-by: Lee Jones <lee at kernel.org>
+---
+ drivers/mfd/rk8xx-core.c | 4 ++++
+ 1 file changed, 4 insertions(+)
+
+--- a/drivers/mfd/rk8xx-core.c
++++ b/drivers/mfd/rk8xx-core.c
+@@ -517,6 +517,10 @@ static int rk808_power_off(struct sys_of
+ reg = RK805_DEV_CTRL_REG;
+ bit = DEV_OFF;
+ break;
++ case RK806_ID:
++ reg = RK806_SYS_CFG3;
++ bit = DEV_OFF;
++ break;
+ case RK808_ID:
+ reg = RK808_DEVCTRL_REG,
+ bit = DEV_OFF_RST;
diff --git a/target/linux/rockchip/patches-6.6/032-01-v6.10-phy-rockchip-add-usbdp-combo-phy-driver.patch b/target/linux/rockchip/patches-6.6/032-01-v6.10-phy-rockchip-add-usbdp-combo-phy-driver.patch
new file mode 100644
index 0000000000..69b44deba3
--- /dev/null
+++ b/target/linux/rockchip/patches-6.6/032-01-v6.10-phy-rockchip-add-usbdp-combo-phy-driver.patch
@@ -0,0 +1,1670 @@
+From 2f70bbddeb457580cef3ceb574506083b9272188 Mon Sep 17 00:00:00 2001
+From: Sebastian Reichel <sebastian.reichel at collabora.com>
+Date: Tue, 9 Apr 2024 00:50:29 +0200
+Subject: [PATCH] phy: rockchip: add usbdp combo phy driver
+
+This adds a new USBDP combo PHY with Samsung IP block driver.
+
+The driver get lane mux and mapping info in 2 ways, supporting
+DisplayPort alternate mode or parsing from DT. When parsing from DT,
+the property "rockchip,dp-lane-mux" provide the DP mux and mapping
+info. This is needed when the PHY is not used with TypeC Alt-Mode.
+For example if the USB3 interface of the PHY is connected to a USB
+Type A connector and the DP interface is connected to a DisplayPort
+connector.
+
+When do DP link training, need to set lane number, link rate, swing,
+and pre-emphasis via PHY configure interface.
+
+Co-developed-by: Heiko Stuebner <heiko at sntech.de>
+Signed-off-by: Heiko Stuebner <heiko at sntech.de>
+Co-developed-by: Zhang Yubing <yubing.zhang at rock-chips.com>
+Signed-off-by: Zhang Yubing <yubing.zhang at rock-chips.com>
+Co-developed-by: Frank Wang <frank.wang at rock-chips.com>
+Signed-off-by: Frank Wang <frank.wang at rock-chips.com>
+Signed-off-by: Sebastian Reichel <sebastian.reichel at collabora.com>
+Link: https://lore.kernel.org/r/20240408225109.128953-3-sebastian.reichel@collabora.com
+Signed-off-by: Vinod Koul <vkoul at kernel.org>
+---
+ drivers/phy/rockchip/Kconfig | 12 +
+ drivers/phy/rockchip/Makefile | 1 +
+ drivers/phy/rockchip/phy-rockchip-usbdp.c | 1608 +++++++++++++++++++++
+ 3 files changed, 1621 insertions(+)
+ create mode 100644 drivers/phy/rockchip/phy-rockchip-usbdp.c
+
+--- a/drivers/phy/rockchip/Kconfig
++++ b/drivers/phy/rockchip/Kconfig
+@@ -107,3 +107,15 @@ config PHY_ROCKCHIP_USB
+ select GENERIC_PHY
+ help
+ Enable this to support the Rockchip USB 2.0 PHY.
++
++config PHY_ROCKCHIP_USBDP
++ tristate "Rockchip USBDP COMBO PHY Driver"
++ depends on ARCH_ROCKCHIP && OF
++ select GENERIC_PHY
++ select TYPEC
++ help
++ Enable this to support the Rockchip USB3.0/DP combo PHY with
++ Samsung IP block. This is required for USB3 support on RK3588.
++
++ To compile this driver as a module, choose M here: the module
++ will be called phy-rockchip-usbdp
+--- a/drivers/phy/rockchip/Makefile
++++ b/drivers/phy/rockchip/Makefile
+@@ -11,3 +11,4 @@ obj-$(CONFIG_PHY_ROCKCHIP_PCIE) += phy-
+ obj-$(CONFIG_PHY_ROCKCHIP_SNPS_PCIE3) += phy-rockchip-snps-pcie3.o
+ obj-$(CONFIG_PHY_ROCKCHIP_TYPEC) += phy-rockchip-typec.o
+ obj-$(CONFIG_PHY_ROCKCHIP_USB) += phy-rockchip-usb.o
++obj-$(CONFIG_PHY_ROCKCHIP_USBDP) += phy-rockchip-usbdp.o
+--- /dev/null
++++ b/drivers/phy/rockchip/phy-rockchip-usbdp.c
+@@ -0,0 +1,1608 @@
++// SPDX-License-Identifier: GPL-2.0-or-later
++/*
++ * Rockchip USBDP Combo PHY with Samsung IP block driver
++ *
++ * Copyright (C) 2021-2024 Rockchip Electronics Co., Ltd
++ * Copyright (C) 2024 Collabora Ltd
++ */
++
++#include <dt-bindings/phy/phy.h>
++#include <linux/bitfield.h>
++#include <linux/bits.h>
++#include <linux/clk.h>
++#include <linux/delay.h>
++#include <linux/gpio.h>
++#include <linux/mfd/syscon.h>
++#include <linux/mod_devicetable.h>
++#include <linux/module.h>
++#include <linux/mutex.h>
++#include <linux/phy/phy.h>
++#include <linux/platform_device.h>
++#include <linux/property.h>
++#include <linux/regmap.h>
++#include <linux/reset.h>
++#include <linux/usb/ch9.h>
++#include <linux/usb/typec_dp.h>
++#include <linux/usb/typec_mux.h>
++
++/* USBDP PHY Register Definitions */
++#define UDPHY_PCS 0x4000
++#define UDPHY_PMA 0x8000
++
++/* VO0 GRF Registers */
++#define DP_SINK_HPD_CFG BIT(11)
++#define DP_SINK_HPD_SEL BIT(10)
++#define DP_AUX_DIN_SEL BIT(9)
++#define DP_AUX_DOUT_SEL BIT(8)
++#define DP_LANE_SEL_N(n) GENMASK(2 * (n) + 1, 2 * (n))
++#define DP_LANE_SEL_ALL GENMASK(7, 0)
++
++/* PMA CMN Registers */
++#define CMN_LANE_MUX_AND_EN_OFFSET 0x0288 /* cmn_reg00A2 */
++#define CMN_DP_LANE_MUX_N(n) BIT((n) + 4)
++#define CMN_DP_LANE_EN_N(n) BIT(n)
++#define CMN_DP_LANE_MUX_ALL GENMASK(7, 4)
++#define CMN_DP_LANE_EN_ALL GENMASK(3, 0)
++
++#define CMN_DP_LINK_OFFSET 0x28c /* cmn_reg00A3 */
++#define CMN_DP_TX_LINK_BW GENMASK(6, 5)
++#define CMN_DP_TX_LANE_SWAP_EN BIT(2)
++
++#define CMN_SSC_EN_OFFSET 0x2d0 /* cmn_reg00B4 */
++#define CMN_ROPLL_SSC_EN BIT(1)
++#define CMN_LCPLL_SSC_EN BIT(0)
++
++#define CMN_ANA_LCPLL_DONE_OFFSET 0x0350 /* cmn_reg00D4 */
++#define CMN_ANA_LCPLL_LOCK_DONE BIT(7)
++#define CMN_ANA_LCPLL_AFC_DONE BIT(6)
++
++#define CMN_ANA_ROPLL_DONE_OFFSET 0x0354 /* cmn_reg00D5 */
++#define CMN_ANA_ROPLL_LOCK_DONE BIT(1)
++#define CMN_ANA_ROPLL_AFC_DONE BIT(0)
++
++#define CMN_DP_RSTN_OFFSET 0x038c /* cmn_reg00E3 */
++#define CMN_DP_INIT_RSTN BIT(3)
++#define CMN_DP_CMN_RSTN BIT(2)
++#define CMN_CDR_WTCHDG_EN BIT(1)
++#define CMN_CDR_WTCHDG_MSK_CDR_EN BIT(0)
++
++#define TRSV_ANA_TX_CLK_OFFSET_N(n) (0x854 + (n) * 0x800) /* trsv_reg0215 */
++#define LN_ANA_TX_SER_TXCLK_INV BIT(1)
++
++#define TRSV_LN0_MON_RX_CDR_DONE_OFFSET 0x0b84 /* trsv_reg02E1 */
++#define TRSV_LN0_MON_RX_CDR_LOCK_DONE BIT(0)
++
++#define TRSV_LN2_MON_RX_CDR_DONE_OFFSET 0x1b84 /* trsv_reg06E1 */
++#define TRSV_LN2_MON_RX_CDR_LOCK_DONE BIT(0)
++
++#define BIT_WRITEABLE_SHIFT 16
++#define PHY_AUX_DP_DATA_POL_NORMAL 0
++#define PHY_AUX_DP_DATA_POL_INVERT 1
++#define PHY_LANE_MUX_USB 0
++#define PHY_LANE_MUX_DP 1
++
++enum {
++ DP_BW_RBR,
++ DP_BW_HBR,
++ DP_BW_HBR2,
++ DP_BW_HBR3,
++};
++
++enum {
++ UDPHY_MODE_NONE = 0,
++ UDPHY_MODE_USB = BIT(0),
++ UDPHY_MODE_DP = BIT(1),
++ UDPHY_MODE_DP_USB = BIT(1) | BIT(0),
++};
++
++struct rk_udphy_grf_reg {
++ unsigned int offset;
++ unsigned int disable;
++ unsigned int enable;
++};
++
++#define _RK_UDPHY_GEN_GRF_REG(offset, mask, disable, enable) \
++{\
++ offset, \
++ FIELD_PREP_CONST(mask, disable) | (mask << BIT_WRITEABLE_SHIFT), \
++ FIELD_PREP_CONST(mask, enable) | (mask << BIT_WRITEABLE_SHIFT), \
++}
++
++#define RK_UDPHY_GEN_GRF_REG(offset, bitend, bitstart, disable, enable) \
++ _RK_UDPHY_GEN_GRF_REG(offset, GENMASK(bitend, bitstart), disable, enable)
++
++struct rk_udphy_grf_cfg {
++ /* u2phy-grf */
++ struct rk_udphy_grf_reg bvalid_phy_con;
++ struct rk_udphy_grf_reg bvalid_grf_con;
++
++ /* usb-grf */
++ struct rk_udphy_grf_reg usb3otg0_cfg;
++ struct rk_udphy_grf_reg usb3otg1_cfg;
++
++ /* usbdpphy-grf */
++ struct rk_udphy_grf_reg low_pwrn;
++ struct rk_udphy_grf_reg rx_lfps;
++};
++
++struct rk_udphy_vogrf_cfg {
++ /* vo-grf */
++ struct rk_udphy_grf_reg hpd_trigger;
++ u32 dp_lane_reg;
++};
++
++struct rk_udphy_dp_tx_drv_ctrl {
++ u32 trsv_reg0204;
++ u32 trsv_reg0205;
++ u32 trsv_reg0206;
++ u32 trsv_reg0207;
++};
++
++struct rk_udphy_cfg {
++ unsigned int num_phys;
++ unsigned int phy_ids[2];
++ /* resets to be requested */
++ const char * const *rst_list;
++ int num_rsts;
++
++ struct rk_udphy_grf_cfg grfcfg;
++ struct rk_udphy_vogrf_cfg vogrfcfg[2];
++ const struct rk_udphy_dp_tx_drv_ctrl (*dp_tx_ctrl_cfg[4])[4];
++ const struct rk_udphy_dp_tx_drv_ctrl (*dp_tx_ctrl_cfg_typec[4])[4];
++};
++
++struct rk_udphy {
++ struct device *dev;
++ struct regmap *pma_regmap;
++ struct regmap *u2phygrf;
++ struct regmap *udphygrf;
++ struct regmap *usbgrf;
++ struct regmap *vogrf;
++ struct typec_switch_dev *sw;
++ struct typec_mux_dev *mux;
++ struct mutex mutex; /* mutex to protect access to individual PHYs */
++
++ /* clocks and rests */
++ int num_clks;
++ struct clk_bulk_data *clks;
++ struct clk *refclk;
++ int num_rsts;
++ struct reset_control_bulk_data *rsts;
++
++ /* PHY status management */
++ bool flip;
++ bool mode_change;
++ u8 mode;
++ u8 status;
++
++ /* utilized for USB */
++ bool hs; /* flag for high-speed */
++
++ /* utilized for DP */
++ struct gpio_desc *sbu1_dc_gpio;
++ struct gpio_desc *sbu2_dc_gpio;
++ u32 lane_mux_sel[4];
++ u32 dp_lane_sel[4];
++ u32 dp_aux_dout_sel;
++ u32 dp_aux_din_sel;
++ bool dp_sink_hpd_sel;
++ bool dp_sink_hpd_cfg;
++ u8 bw;
++ int id;
++
++ bool dp_in_use;
++
++ /* PHY const config */
++ const struct rk_udphy_cfg *cfgs;
++
++ /* PHY devices */
++ struct phy *phy_dp;
++ struct phy *phy_u3;
++};
++
++static const struct rk_udphy_dp_tx_drv_ctrl rk3588_dp_tx_drv_ctrl_rbr_hbr[4][4] = {
++ /* voltage swing 0, pre-emphasis 0->3 */
++ {
++ { 0x20, 0x10, 0x42, 0xe5 },
++ { 0x26, 0x14, 0x42, 0xe5 },
++ { 0x29, 0x18, 0x42, 0xe5 },
++ { 0x2b, 0x1c, 0x43, 0xe7 },
++ },
++
++ /* voltage swing 1, pre-emphasis 0->2 */
++ {
++ { 0x23, 0x10, 0x42, 0xe7 },
++ { 0x2a, 0x17, 0x43, 0xe7 },
++ { 0x2b, 0x1a, 0x43, 0xe7 },
++ },
++
++ /* voltage swing 2, pre-emphasis 0->1 */
++ {
++ { 0x27, 0x10, 0x42, 0xe7 },
++ { 0x2b, 0x17, 0x43, 0xe7 },
++ },
++
++ /* voltage swing 3, pre-emphasis 0 */
++ {
++ { 0x29, 0x10, 0x43, 0xe7 },
++ },
++};
++
++static const struct rk_udphy_dp_tx_drv_ctrl rk3588_dp_tx_drv_ctrl_rbr_hbr_typec[4][4] = {
++ /* voltage swing 0, pre-emphasis 0->3 */
++ {
++ { 0x20, 0x10, 0x42, 0xe5 },
++ { 0x26, 0x14, 0x42, 0xe5 },
++ { 0x29, 0x18, 0x42, 0xe5 },
++ { 0x2b, 0x1c, 0x43, 0xe7 },
++ },
++
++ /* voltage swing 1, pre-emphasis 0->2 */
++ {
++ { 0x23, 0x10, 0x42, 0xe7 },
++ { 0x2a, 0x17, 0x43, 0xe7 },
++ { 0x2b, 0x1a, 0x43, 0xe7 },
++ },
++
++ /* voltage swing 2, pre-emphasis 0->1 */
++ {
++ { 0x27, 0x10, 0x43, 0x67 },
++ { 0x2b, 0x17, 0x43, 0xe7 },
++ },
++
++ /* voltage swing 3, pre-emphasis 0 */
++ {
++ { 0x29, 0x10, 0x43, 0xe7 },
++ },
++};
++
++static const struct rk_udphy_dp_tx_drv_ctrl rk3588_dp_tx_drv_ctrl_hbr2[4][4] = {
++ /* voltage swing 0, pre-emphasis 0->3 */
++ {
++ { 0x21, 0x10, 0x42, 0xe5 },
++ { 0x26, 0x14, 0x42, 0xe5 },
++ { 0x26, 0x16, 0x43, 0xe5 },
++ { 0x2a, 0x19, 0x43, 0xe7 },
++ },
++
++ /* voltage swing 1, pre-emphasis 0->2 */
++ {
++ { 0x24, 0x10, 0x42, 0xe7 },
++ { 0x2a, 0x17, 0x43, 0xe7 },
++ { 0x2b, 0x1a, 0x43, 0xe7 },
++ },
++
++ /* voltage swing 2, pre-emphasis 0->1 */
++ {
++ { 0x28, 0x10, 0x42, 0xe7 },
++ { 0x2b, 0x17, 0x43, 0xe7 },
++ },
++
++ /* voltage swing 3, pre-emphasis 0 */
++ {
++ { 0x28, 0x10, 0x43, 0xe7 },
++ },
++};
++
++static const struct rk_udphy_dp_tx_drv_ctrl rk3588_dp_tx_drv_ctrl_hbr3[4][4] = {
++ /* voltage swing 0, pre-emphasis 0->3 */
++ {
++ { 0x21, 0x10, 0x42, 0xe5 },
++ { 0x26, 0x14, 0x42, 0xe5 },
++ { 0x26, 0x16, 0x43, 0xe5 },
++ { 0x29, 0x18, 0x43, 0xe7 },
++ },
++
++ /* voltage swing 1, pre-emphasis 0->2 */
++ {
++ { 0x24, 0x10, 0x42, 0xe7 },
++ { 0x2a, 0x18, 0x43, 0xe7 },
++ { 0x2b, 0x1b, 0x43, 0xe7 }
++ },
++
++ /* voltage swing 2, pre-emphasis 0->1 */
++ {
++ { 0x27, 0x10, 0x42, 0xe7 },
++ { 0x2b, 0x18, 0x43, 0xe7 }
++ },
++
++ /* voltage swing 3, pre-emphasis 0 */
++ {
++ { 0x28, 0x10, 0x43, 0xe7 },
++ },
++};
++
++static const struct reg_sequence rk_udphy_24m_refclk_cfg[] = {
++ {0x0090, 0x68}, {0x0094, 0x68},
++ {0x0128, 0x24}, {0x012c, 0x44},
++ {0x0130, 0x3f}, {0x0134, 0x44},
++ {0x015c, 0xa9}, {0x0160, 0x71},
++ {0x0164, 0x71}, {0x0168, 0xa9},
++ {0x0174, 0xa9}, {0x0178, 0x71},
++ {0x017c, 0x71}, {0x0180, 0xa9},
++ {0x018c, 0x41}, {0x0190, 0x00},
++ {0x0194, 0x05}, {0x01ac, 0x2a},
++ {0x01b0, 0x17}, {0x01b4, 0x17},
++ {0x01b8, 0x2a}, {0x01c8, 0x04},
++ {0x01cc, 0x08}, {0x01d0, 0x08},
++ {0x01d4, 0x04}, {0x01d8, 0x20},
++ {0x01dc, 0x01}, {0x01e0, 0x09},
++ {0x01e4, 0x03}, {0x01f0, 0x29},
++ {0x01f4, 0x02}, {0x01f8, 0x02},
++ {0x01fc, 0x29}, {0x0208, 0x2a},
++ {0x020c, 0x17}, {0x0210, 0x17},
++ {0x0214, 0x2a}, {0x0224, 0x20},
++ {0x03f0, 0x0a}, {0x03f4, 0x07},
++ {0x03f8, 0x07}, {0x03fc, 0x0c},
++ {0x0404, 0x12}, {0x0408, 0x1a},
++ {0x040c, 0x1a}, {0x0410, 0x3f},
++ {0x0ce0, 0x68}, {0x0ce8, 0xd0},
++ {0x0cf0, 0x87}, {0x0cf8, 0x70},
++ {0x0d00, 0x70}, {0x0d08, 0xa9},
++ {0x1ce0, 0x68}, {0x1ce8, 0xd0},
++ {0x1cf0, 0x87}, {0x1cf8, 0x70},
++ {0x1d00, 0x70}, {0x1d08, 0xa9},
++ {0x0a3c, 0xd0}, {0x0a44, 0xd0},
++ {0x0a48, 0x01}, {0x0a4c, 0x0d},
++ {0x0a54, 0xe0}, {0x0a5c, 0xe0},
++ {0x0a64, 0xa8}, {0x1a3c, 0xd0},
++ {0x1a44, 0xd0}, {0x1a48, 0x01},
++ {0x1a4c, 0x0d}, {0x1a54, 0xe0},
++ {0x1a5c, 0xe0}, {0x1a64, 0xa8}
++};
++
++static const struct reg_sequence rk_udphy_26m_refclk_cfg[] = {
++ {0x0830, 0x07}, {0x085c, 0x80},
++ {0x1030, 0x07}, {0x105c, 0x80},
++ {0x1830, 0x07}, {0x185c, 0x80},
++ {0x2030, 0x07}, {0x205c, 0x80},
++ {0x0228, 0x38}, {0x0104, 0x44},
++ {0x0248, 0x44}, {0x038c, 0x02},
++ {0x0878, 0x04}, {0x1878, 0x04},
++ {0x0898, 0x77}, {0x1898, 0x77},
++ {0x0054, 0x01}, {0x00e0, 0x38},
++ {0x0060, 0x24}, {0x0064, 0x77},
++ {0x0070, 0x76}, {0x0234, 0xe8},
++ {0x0af4, 0x15}, {0x1af4, 0x15},
++ {0x081c, 0xe5}, {0x181c, 0xe5},
++ {0x099c, 0x48}, {0x199c, 0x48},
++ {0x09a4, 0x07}, {0x09a8, 0x22},
++ {0x19a4, 0x07}, {0x19a8, 0x22},
++ {0x09b8, 0x3e}, {0x19b8, 0x3e},
++ {0x09e4, 0x02}, {0x19e4, 0x02},
++ {0x0a34, 0x1e}, {0x1a34, 0x1e},
++ {0x0a98, 0x2f}, {0x1a98, 0x2f},
++ {0x0c30, 0x0e}, {0x0c48, 0x06},
++ {0x1c30, 0x0e}, {0x1c48, 0x06},
++ {0x028c, 0x18}, {0x0af0, 0x00},
++ {0x1af0, 0x00}
++};
++
++static const struct reg_sequence rk_udphy_init_sequence[] = {
++ {0x0104, 0x44}, {0x0234, 0xe8},
++ {0x0248, 0x44}, {0x028c, 0x18},
++ {0x081c, 0xe5}, {0x0878, 0x00},
++ {0x0994, 0x1c}, {0x0af0, 0x00},
++ {0x181c, 0xe5}, {0x1878, 0x00},
++ {0x1994, 0x1c}, {0x1af0, 0x00},
++ {0x0428, 0x60}, {0x0d58, 0x33},
++ {0x1d58, 0x33}, {0x0990, 0x74},
++ {0x0d64, 0x17}, {0x08c8, 0x13},
++ {0x1990, 0x74}, {0x1d64, 0x17},
++ {0x18c8, 0x13}, {0x0d90, 0x40},
++ {0x0da8, 0x40}, {0x0dc0, 0x40},
++ {0x0dd8, 0x40}, {0x1d90, 0x40},
++ {0x1da8, 0x40}, {0x1dc0, 0x40},
++ {0x1dd8, 0x40}, {0x03c0, 0x30},
++ {0x03c4, 0x06}, {0x0e10, 0x00},
++ {0x1e10, 0x00}, {0x043c, 0x0f},
++ {0x0d2c, 0xff}, {0x1d2c, 0xff},
++ {0x0d34, 0x0f}, {0x1d34, 0x0f},
++ {0x08fc, 0x2a}, {0x0914, 0x28},
++ {0x0a30, 0x03}, {0x0e38, 0x03},
++ {0x0ecc, 0x27}, {0x0ed0, 0x22},
++ {0x0ed4, 0x26}, {0x18fc, 0x2a},
++ {0x1914, 0x28}, {0x1a30, 0x03},
++ {0x1e38, 0x03}, {0x1ecc, 0x27},
++ {0x1ed0, 0x22}, {0x1ed4, 0x26},
++ {0x0048, 0x0f}, {0x0060, 0x3c},
++ {0x0064, 0xf7}, {0x006c, 0x20},
++ {0x0070, 0x7d}, {0x0074, 0x68},
++ {0x0af4, 0x1a}, {0x1af4, 0x1a},
++ {0x0440, 0x3f}, {0x10d4, 0x08},
++ {0x20d4, 0x08}, {0x00d4, 0x30},
++ {0x0024, 0x6e},
++};
++
++static inline int rk_udphy_grfreg_write(struct regmap *base,
++ const struct rk_udphy_grf_reg *reg, bool en)
++{
++ return regmap_write(base, reg->offset, en ? reg->enable : reg->disable);
++}
++
++static int rk_udphy_clk_init(struct rk_udphy *udphy, struct device *dev)
++{
++ int i;
++
++ udphy->num_clks = devm_clk_bulk_get_all(dev, &udphy->clks);
++ if (udphy->num_clks < 1)
++ return -ENODEV;
++
++ /* used for configure phy reference clock frequency */
++ for (i = 0; i < udphy->num_clks; i++) {
++ if (!strncmp(udphy->clks[i].id, "refclk", 6)) {
++ udphy->refclk = udphy->clks[i].clk;
++ break;
++ }
++ }
++
++ if (!udphy->refclk)
++ return dev_err_probe(udphy->dev, -EINVAL, "no refclk found\n");
++
++ return 0;
++}
++
++static int rk_udphy_reset_assert_all(struct rk_udphy *udphy)
++{
++ return reset_control_bulk_assert(udphy->num_rsts, udphy->rsts);
++}
++
++static int rk_udphy_reset_deassert_all(struct rk_udphy *udphy)
++{
++ return reset_control_bulk_deassert(udphy->num_rsts, udphy->rsts);
++}
++
++static int rk_udphy_reset_deassert(struct rk_udphy *udphy, char *name)
++{
++ struct reset_control_bulk_data *list = udphy->rsts;
++ int idx;
++
++ for (idx = 0; idx < udphy->num_rsts; idx++) {
++ if (!strcmp(list[idx].id, name))
++ return reset_control_deassert(list[idx].rstc);
++ }
++
++ return -EINVAL;
++}
++
++static int rk_udphy_reset_init(struct rk_udphy *udphy, struct device *dev)
++{
++ const struct rk_udphy_cfg *cfg = udphy->cfgs;
++ int idx;
++
++ udphy->num_rsts = cfg->num_rsts;
++ udphy->rsts = devm_kcalloc(dev, udphy->num_rsts,
++ sizeof(*udphy->rsts), GFP_KERNEL);
++ if (!udphy->rsts)
++ return -ENOMEM;
++
++ for (idx = 0; idx < cfg->num_rsts; idx++)
++ udphy->rsts[idx].id = cfg->rst_list[idx];
++
++ return devm_reset_control_bulk_get_exclusive(dev, cfg->num_rsts,
++ udphy->rsts);
++}
++
++static void rk_udphy_u3_port_disable(struct rk_udphy *udphy, u8 disable)
++{
++ const struct rk_udphy_cfg *cfg = udphy->cfgs;
++ const struct rk_udphy_grf_reg *preg;
++
++ preg = udphy->id ? &cfg->grfcfg.usb3otg1_cfg : &cfg->grfcfg.usb3otg0_cfg;
++ rk_udphy_grfreg_write(udphy->usbgrf, preg, disable);
++}
++
++static void rk_udphy_usb_bvalid_enable(struct rk_udphy *udphy, u8 enable)
++{
++ const struct rk_udphy_cfg *cfg = udphy->cfgs;
++
++ rk_udphy_grfreg_write(udphy->u2phygrf, &cfg->grfcfg.bvalid_phy_con, enable);
++ rk_udphy_grfreg_write(udphy->u2phygrf, &cfg->grfcfg.bvalid_grf_con, enable);
++}
++
++/*
++ * In usb/dp combo phy driver, here are 2 ways to mapping lanes.
++ *
++ * 1 Type-C Mapping table (DP_Alt_Mode V1.0b remove ABF pin mapping)
++ * ---------------------------------------------------------------------------
++ * Type-C Pin B11-B10 A2-A3 A11-A10 B2-B3
++ * PHY Pad ln0(tx/rx) ln1(tx) ln2(tx/rx) ln3(tx)
++ * C/E(Normal) dpln3 dpln2 dpln0 dpln1
++ * C/E(Flip ) dpln0 dpln1 dpln3 dpln2
++ * D/F(Normal) usbrx usbtx dpln0 dpln1
++ * D/F(Flip ) dpln0 dpln1 usbrx usbtx
++ * A(Normal ) dpln3 dpln1 dpln2 dpln0
++ * A(Flip ) dpln2 dpln0 dpln3 dpln1
++ * B(Normal ) usbrx usbtx dpln1 dpln0
++ * B(Flip ) dpln1 dpln0 usbrx usbtx
++ * ---------------------------------------------------------------------------
++ *
++ * 2 Mapping the lanes in dtsi
++ * if all 4 lane assignment for dp function, define rockchip,dp-lane-mux = <x x x x>;
++ * sample as follow:
++ * ---------------------------------------------------------------------------
++ * B11-B10 A2-A3 A11-A10 B2-B3
++ * rockchip,dp-lane-mux ln0(tx/rx) ln1(tx) ln2(tx/rx) ln3(tx)
++ * <0 1 2 3> dpln0 dpln1 dpln2 dpln3
++ * <2 3 0 1> dpln2 dpln3 dpln0 dpln1
++ * ---------------------------------------------------------------------------
++ * if 2 lane for dp function, 2 lane for usb function, define rockchip,dp-lane-mux = <x x>;
++ * sample as follow:
++ * ---------------------------------------------------------------------------
++ * B11-B10 A2-A3 A11-A10 B2-B3
++ * rockchip,dp-lane-mux ln0(tx/rx) ln1(tx) ln2(tx/rx) ln3(tx)
++ * <0 1> dpln0 dpln1 usbrx usbtx
++ * <2 3> usbrx usbtx dpln0 dpln1
++ * ---------------------------------------------------------------------------
++ */
++
++static void rk_udphy_dplane_select(struct rk_udphy *udphy)
++{
++ const struct rk_udphy_cfg *cfg = udphy->cfgs;
++ u32 value = 0;
++
++ switch (udphy->mode) {
++ case UDPHY_MODE_DP:
++ value |= 2 << udphy->dp_lane_sel[2] * 2;
++ value |= 3 << udphy->dp_lane_sel[3] * 2;
++ fallthrough;
++
++ case UDPHY_MODE_DP_USB:
++ value |= 0 << udphy->dp_lane_sel[0] * 2;
++ value |= 1 << udphy->dp_lane_sel[1] * 2;
++ break;
++
++ case UDPHY_MODE_USB:
++ break;
++
++ default:
++ break;
++ }
++
++ regmap_write(udphy->vogrf, cfg->vogrfcfg[udphy->id].dp_lane_reg,
++ ((DP_AUX_DIN_SEL | DP_AUX_DOUT_SEL | DP_LANE_SEL_ALL) << 16) |
++ FIELD_PREP(DP_AUX_DIN_SEL, udphy->dp_aux_din_sel) |
++ FIELD_PREP(DP_AUX_DOUT_SEL, udphy->dp_aux_dout_sel) | value);
++}
++
++static int rk_udphy_dplane_get(struct rk_udphy *udphy)
++{
++ int dp_lanes;
++
++ switch (udphy->mode) {
++ case UDPHY_MODE_DP:
++ dp_lanes = 4;
++ break;
++
++ case UDPHY_MODE_DP_USB:
++ dp_lanes = 2;
++ break;
++
++ case UDPHY_MODE_USB:
++ default:
++ dp_lanes = 0;
++ break;
++ }
++
++ return dp_lanes;
++}
++
++static void rk_udphy_dplane_enable(struct rk_udphy *udphy, int dp_lanes)
++{
++ u32 val = 0;
++ int i;
++
++ for (i = 0; i < dp_lanes; i++)
++ val |= BIT(udphy->dp_lane_sel[i]);
++
++ regmap_update_bits(udphy->pma_regmap, CMN_LANE_MUX_AND_EN_OFFSET, CMN_DP_LANE_EN_ALL,
++ FIELD_PREP(CMN_DP_LANE_EN_ALL, val));
++
++ if (!dp_lanes)
++ regmap_update_bits(udphy->pma_regmap, CMN_DP_RSTN_OFFSET,
++ CMN_DP_CMN_RSTN, FIELD_PREP(CMN_DP_CMN_RSTN, 0x0));
++}
++
++static void rk_udphy_dp_hpd_event_trigger(struct rk_udphy *udphy, bool hpd)
++{
++ const struct rk_udphy_cfg *cfg = udphy->cfgs;
++
++ udphy->dp_sink_hpd_sel = true;
++ udphy->dp_sink_hpd_cfg = hpd;
++
++ if (!udphy->dp_in_use)
++ return;
++
++ rk_udphy_grfreg_write(udphy->vogrf, &cfg->vogrfcfg[udphy->id].hpd_trigger, hpd);
++}
++
++static void rk_udphy_set_typec_default_mapping(struct rk_udphy *udphy)
++{
++ if (udphy->flip) {
++ udphy->dp_lane_sel[0] = 0;
++ udphy->dp_lane_sel[1] = 1;
++ udphy->dp_lane_sel[2] = 3;
++ udphy->dp_lane_sel[3] = 2;
++ udphy->lane_mux_sel[0] = PHY_LANE_MUX_DP;
++ udphy->lane_mux_sel[1] = PHY_LANE_MUX_DP;
++ udphy->lane_mux_sel[2] = PHY_LANE_MUX_USB;
++ udphy->lane_mux_sel[3] = PHY_LANE_MUX_USB;
++ udphy->dp_aux_dout_sel = PHY_AUX_DP_DATA_POL_INVERT;
++ udphy->dp_aux_din_sel = PHY_AUX_DP_DATA_POL_INVERT;
++ gpiod_set_value_cansleep(udphy->sbu1_dc_gpio, 1);
++ gpiod_set_value_cansleep(udphy->sbu2_dc_gpio, 0);
++ } else {
++ udphy->dp_lane_sel[0] = 2;
++ udphy->dp_lane_sel[1] = 3;
++ udphy->dp_lane_sel[2] = 1;
++ udphy->dp_lane_sel[3] = 0;
++ udphy->lane_mux_sel[0] = PHY_LANE_MUX_USB;
++ udphy->lane_mux_sel[1] = PHY_LANE_MUX_USB;
++ udphy->lane_mux_sel[2] = PHY_LANE_MUX_DP;
++ udphy->lane_mux_sel[3] = PHY_LANE_MUX_DP;
++ udphy->dp_aux_dout_sel = PHY_AUX_DP_DATA_POL_NORMAL;
++ udphy->dp_aux_din_sel = PHY_AUX_DP_DATA_POL_NORMAL;
++ gpiod_set_value_cansleep(udphy->sbu1_dc_gpio, 0);
++ gpiod_set_value_cansleep(udphy->sbu2_dc_gpio, 1);
++ }
++
++ udphy->mode = UDPHY_MODE_DP_USB;
++}
++
++static int rk_udphy_orien_sw_set(struct typec_switch_dev *sw,
++ enum typec_orientation orien)
++{
++ struct rk_udphy *udphy = typec_switch_get_drvdata(sw);
++
++ mutex_lock(&udphy->mutex);
++
++ if (orien == TYPEC_ORIENTATION_NONE) {
++ gpiod_set_value_cansleep(udphy->sbu1_dc_gpio, 0);
++ gpiod_set_value_cansleep(udphy->sbu2_dc_gpio, 0);
++ /* unattached */
++ rk_udphy_usb_bvalid_enable(udphy, false);
++ goto unlock_ret;
++ }
++
++ udphy->flip = (orien == TYPEC_ORIENTATION_REVERSE) ? true : false;
++ rk_udphy_set_typec_default_mapping(udphy);
++ rk_udphy_usb_bvalid_enable(udphy, true);
++
++unlock_ret:
++ mutex_unlock(&udphy->mutex);
++ return 0;
++}
++
++static void rk_udphy_orien_switch_unregister(void *data)
++{
++ struct rk_udphy *udphy = data;
++
++ typec_switch_unregister(udphy->sw);
++}
++
++static int rk_udphy_setup_orien_switch(struct rk_udphy *udphy)
++{
++ struct typec_switch_desc sw_desc = { };
++
++ sw_desc.drvdata = udphy;
++ sw_desc.fwnode = dev_fwnode(udphy->dev);
++ sw_desc.set = rk_udphy_orien_sw_set;
++
++ udphy->sw = typec_switch_register(udphy->dev, &sw_desc);
++ if (IS_ERR(udphy->sw)) {
++ dev_err(udphy->dev, "Error register typec orientation switch: %ld\n",
++ PTR_ERR(udphy->sw));
++ return PTR_ERR(udphy->sw);
++ }
++
++ return devm_add_action_or_reset(udphy->dev,
++ rk_udphy_orien_switch_unregister, udphy);
++}
++
++static int rk_udphy_refclk_set(struct rk_udphy *udphy)
++{
++ unsigned long rate;
++ int ret;
++
++ /* configure phy reference clock */
++ rate = clk_get_rate(udphy->refclk);
++ dev_dbg(udphy->dev, "refclk freq %ld\n", rate);
++
++ switch (rate) {
++ case 24000000:
++ ret = regmap_multi_reg_write(udphy->pma_regmap, rk_udphy_24m_refclk_cfg,
++ ARRAY_SIZE(rk_udphy_24m_refclk_cfg));
++ if (ret)
++ return ret;
++ break;
++
++ case 26000000:
++ /* register default is 26MHz */
++ ret = regmap_multi_reg_write(udphy->pma_regmap, rk_udphy_26m_refclk_cfg,
++ ARRAY_SIZE(rk_udphy_26m_refclk_cfg));
++ if (ret)
++ return ret;
++ break;
++
++ default:
++ dev_err(udphy->dev, "unsupported refclk freq %ld\n", rate);
++ return -EINVAL;
++ }
++
++ return 0;
++}
++
++static int rk_udphy_status_check(struct rk_udphy *udphy)
++{
++ unsigned int val;
++ int ret;
++
++ /* LCPLL check */
++ if (udphy->mode & UDPHY_MODE_USB) {
++ ret = regmap_read_poll_timeout(udphy->pma_regmap, CMN_ANA_LCPLL_DONE_OFFSET,
++ val, (val & CMN_ANA_LCPLL_AFC_DONE) &&
++ (val & CMN_ANA_LCPLL_LOCK_DONE), 200, 100000);
++ if (ret) {
++ dev_err(udphy->dev, "cmn ana lcpll lock timeout\n");
++ /*
++ * If earlier software (U-Boot) enabled USB once already
++ * the PLL may have problems locking on the first try.
++ * It will be successful on the second try, so for the
++ * time being a -EPROBE_DEFER will solve the issue.
++ *
++ * This requires further investigation to understand the
++ * root cause, especially considering that the driver is
++ * asserting all reset lines at probe time.
++ */
++ return -EPROBE_DEFER;
++ }
++
++ if (!udphy->flip) {
++ ret = regmap_read_poll_timeout(udphy->pma_regmap,
++ TRSV_LN0_MON_RX_CDR_DONE_OFFSET, val,
++ val & TRSV_LN0_MON_RX_CDR_LOCK_DONE,
++ 200, 100000);
++ if (ret)
++ dev_err(udphy->dev, "trsv ln0 mon rx cdr lock timeout\n");
++ } else {
++ ret = regmap_read_poll_timeout(udphy->pma_regmap,
++ TRSV_LN2_MON_RX_CDR_DONE_OFFSET, val,
++ val & TRSV_LN2_MON_RX_CDR_LOCK_DONE,
++ 200, 100000);
++ if (ret)
++ dev_err(udphy->dev, "trsv ln2 mon rx cdr lock timeout\n");
++ }
++ }
++
++ return 0;
++}
++
++static int rk_udphy_init(struct rk_udphy *udphy)
++{
++ const struct rk_udphy_cfg *cfg = udphy->cfgs;
++ int ret;
++
++ rk_udphy_reset_assert_all(udphy);
++ usleep_range(10000, 11000);
++
++ /* enable rx lfps for usb */
++ if (udphy->mode & UDPHY_MODE_USB)
++ rk_udphy_grfreg_write(udphy->udphygrf, &cfg->grfcfg.rx_lfps, true);
++
++ /* Step 1: power on pma and deassert apb rstn */
++ rk_udphy_grfreg_write(udphy->udphygrf, &cfg->grfcfg.low_pwrn, true);
++
++ rk_udphy_reset_deassert(udphy, "pma_apb");
++ rk_udphy_reset_deassert(udphy, "pcs_apb");
++
++ /* Step 2: set init sequence and phy refclk */
++ ret = regmap_multi_reg_write(udphy->pma_regmap, rk_udphy_init_sequence,
++ ARRAY_SIZE(rk_udphy_init_sequence));
++ if (ret) {
++ dev_err(udphy->dev, "init sequence set error %d\n", ret);
++ goto assert_resets;
++ }
++
++ ret = rk_udphy_refclk_set(udphy);
++ if (ret) {
++ dev_err(udphy->dev, "refclk set error %d\n", ret);
++ goto assert_resets;
++ }
++
++ /* Step 3: configure lane mux */
++ regmap_update_bits(udphy->pma_regmap, CMN_LANE_MUX_AND_EN_OFFSET,
++ CMN_DP_LANE_MUX_ALL | CMN_DP_LANE_EN_ALL,
++ FIELD_PREP(CMN_DP_LANE_MUX_N(3), udphy->lane_mux_sel[3]) |
++ FIELD_PREP(CMN_DP_LANE_MUX_N(2), udphy->lane_mux_sel[2]) |
++ FIELD_PREP(CMN_DP_LANE_MUX_N(1), udphy->lane_mux_sel[1]) |
++ FIELD_PREP(CMN_DP_LANE_MUX_N(0), udphy->lane_mux_sel[0]) |
++ FIELD_PREP(CMN_DP_LANE_EN_ALL, 0));
++
++ /* Step 4: deassert init rstn and wait for 200ns from datasheet */
++ if (udphy->mode & UDPHY_MODE_USB)
++ rk_udphy_reset_deassert(udphy, "init");
++
++ if (udphy->mode & UDPHY_MODE_DP) {
++ regmap_update_bits(udphy->pma_regmap, CMN_DP_RSTN_OFFSET,
++ CMN_DP_INIT_RSTN,
++ FIELD_PREP(CMN_DP_INIT_RSTN, 0x1));
++ }
++
++ udelay(1);
++
++ /* Step 5: deassert cmn/lane rstn */
++ if (udphy->mode & UDPHY_MODE_USB) {
++ rk_udphy_reset_deassert(udphy, "cmn");
++ rk_udphy_reset_deassert(udphy, "lane");
++ }
++
++ /* Step 6: wait for lock done of pll */
++ ret = rk_udphy_status_check(udphy);
++ if (ret)
++ goto assert_resets;
++
++ return 0;
++
++assert_resets:
++ rk_udphy_reset_assert_all(udphy);
++ return ret;
++}
++
++static int rk_udphy_setup(struct rk_udphy *udphy)
++{
++ int ret;
++
++ ret = clk_bulk_prepare_enable(udphy->num_clks, udphy->clks);
++ if (ret) {
++ dev_err(udphy->dev, "failed to enable clk\n");
++ return ret;
++ }
++
++ ret = rk_udphy_init(udphy);
++ if (ret) {
++ dev_err(udphy->dev, "failed to init combophy\n");
++ clk_bulk_disable_unprepare(udphy->num_clks, udphy->clks);
++ return ret;
++ }
++
++ return 0;
++}
++
++static void rk_udphy_disable(struct rk_udphy *udphy)
++{
++ clk_bulk_disable_unprepare(udphy->num_clks, udphy->clks);
++ rk_udphy_reset_assert_all(udphy);
++}
++
++static int rk_udphy_parse_lane_mux_data(struct rk_udphy *udphy)
++{
++ int ret, i, num_lanes;
++
++ num_lanes = device_property_count_u32(udphy->dev, "rockchip,dp-lane-mux");
++ if (num_lanes < 0) {
++ dev_dbg(udphy->dev, "no dp-lane-mux, following dp alt mode\n");
++ udphy->mode = UDPHY_MODE_USB;
++ return 0;
++ }
++
++ if (num_lanes != 2 && num_lanes != 4)
++ return dev_err_probe(udphy->dev, -EINVAL,
++ "invalid number of lane mux\n");
++
++ ret = device_property_read_u32_array(udphy->dev, "rockchip,dp-lane-mux",
++ udphy->dp_lane_sel, num_lanes);
++ if (ret)
++ return dev_err_probe(udphy->dev, ret, "get dp lane mux failed\n");
++
++ for (i = 0; i < num_lanes; i++) {
++ int j;
++
++ if (udphy->dp_lane_sel[i] > 3)
++ return dev_err_probe(udphy->dev, -EINVAL,
++ "lane mux between 0 and 3, exceeding the range\n");
++
++ udphy->lane_mux_sel[udphy->dp_lane_sel[i]] = PHY_LANE_MUX_DP;
++
++ for (j = i + 1; j < num_lanes; j++) {
++ if (udphy->dp_lane_sel[i] == udphy->dp_lane_sel[j])
++ return dev_err_probe(udphy->dev, -EINVAL,
++ "set repeat lane mux value\n");
++ }
++ }
++
++ udphy->mode = UDPHY_MODE_DP;
++ if (num_lanes == 2) {
++ udphy->mode |= UDPHY_MODE_USB;
++ udphy->flip = (udphy->lane_mux_sel[0] == PHY_LANE_MUX_DP);
++ }
++
++ return 0;
++}
++
++static int rk_udphy_get_initial_status(struct rk_udphy *udphy)
++{
++ int ret;
++ u32 value;
++
++ ret = clk_bulk_prepare_enable(udphy->num_clks, udphy->clks);
++ if (ret) {
++ dev_err(udphy->dev, "failed to enable clk\n");
++ return ret;
++ }
++
++ rk_udphy_reset_deassert_all(udphy);
++
++ regmap_read(udphy->pma_regmap, CMN_LANE_MUX_AND_EN_OFFSET, &value);
++ if (FIELD_GET(CMN_DP_LANE_MUX_ALL, value) && FIELD_GET(CMN_DP_LANE_EN_ALL, value))
++ udphy->status = UDPHY_MODE_DP;
++ else
++ rk_udphy_disable(udphy);
++
++ return 0;
++}
++
++static int rk_udphy_parse_dt(struct rk_udphy *udphy)
++{
++ struct device *dev = udphy->dev;
++ struct device_node *np = dev_of_node(dev);
++ enum usb_device_speed maximum_speed;
++ int ret;
++
++ udphy->u2phygrf = syscon_regmap_lookup_by_phandle(np, "rockchip,u2phy-grf");
++ if (IS_ERR(udphy->u2phygrf))
++ return dev_err_probe(dev, PTR_ERR(udphy->u2phygrf), "failed to get u2phy-grf\n");
++
++ udphy->udphygrf = syscon_regmap_lookup_by_phandle(np, "rockchip,usbdpphy-grf");
++ if (IS_ERR(udphy->udphygrf))
++ return dev_err_probe(dev, PTR_ERR(udphy->udphygrf), "failed to get usbdpphy-grf\n");
++
++ udphy->usbgrf = syscon_regmap_lookup_by_phandle(np, "rockchip,usb-grf");
++ if (IS_ERR(udphy->usbgrf))
++ return dev_err_probe(dev, PTR_ERR(udphy->usbgrf), "failed to get usb-grf\n");
++
++ udphy->vogrf = syscon_regmap_lookup_by_phandle(np, "rockchip,vo-grf");
++ if (IS_ERR(udphy->vogrf))
++ return dev_err_probe(dev, PTR_ERR(udphy->vogrf), "failed to get vo-grf\n");
++
++ ret = rk_udphy_parse_lane_mux_data(udphy);
++ if (ret)
++ return ret;
++
++ udphy->sbu1_dc_gpio = devm_gpiod_get_optional(dev, "sbu1-dc", GPIOD_OUT_LOW);
++ if (IS_ERR(udphy->sbu1_dc_gpio))
++ return PTR_ERR(udphy->sbu1_dc_gpio);
++
++ udphy->sbu2_dc_gpio = devm_gpiod_get_optional(dev, "sbu2-dc", GPIOD_OUT_LOW);
++ if (IS_ERR(udphy->sbu2_dc_gpio))
++ return PTR_ERR(udphy->sbu2_dc_gpio);
++
++ if (device_property_present(dev, "maximum-speed")) {
++ maximum_speed = usb_get_maximum_speed(dev);
++ udphy->hs = maximum_speed <= USB_SPEED_HIGH ? true : false;
++ }
++
++ ret = rk_udphy_clk_init(udphy, dev);
++ if (ret)
++ return ret;
++
++ return rk_udphy_reset_init(udphy, dev);
++}
++
++static int rk_udphy_power_on(struct rk_udphy *udphy, u8 mode)
++{
++ int ret;
++
++ if (!(udphy->mode & mode)) {
++ dev_info(udphy->dev, "mode 0x%02x is not support\n", mode);
++ return 0;
++ }
++
++ if (udphy->status == UDPHY_MODE_NONE) {
++ udphy->mode_change = false;
++ ret = rk_udphy_setup(udphy);
++ if (ret)
++ return ret;
++
++ if (udphy->mode & UDPHY_MODE_USB)
++ rk_udphy_u3_port_disable(udphy, false);
++ } else if (udphy->mode_change) {
++ udphy->mode_change = false;
++ udphy->status = UDPHY_MODE_NONE;
++ if (udphy->mode == UDPHY_MODE_DP)
++ rk_udphy_u3_port_disable(udphy, true);
++
++ rk_udphy_disable(udphy);
++ ret = rk_udphy_setup(udphy);
++ if (ret)
++ return ret;
++ }
++
++ udphy->status |= mode;
++
++ return 0;
++}
++
++static void rk_udphy_power_off(struct rk_udphy *udphy, u8 mode)
++{
++ if (!(udphy->mode & mode)) {
++ dev_info(udphy->dev, "mode 0x%02x is not support\n", mode);
++ return;
++ }
++
++ if (!udphy->status)
++ return;
++
++ udphy->status &= ~mode;
++
++ if (udphy->status == UDPHY_MODE_NONE)
++ rk_udphy_disable(udphy);
++}
++
++static int rk_udphy_dp_phy_init(struct phy *phy)
++{
++ struct rk_udphy *udphy = phy_get_drvdata(phy);
++
++ mutex_lock(&udphy->mutex);
++
++ udphy->dp_in_use = true;
++ rk_udphy_dp_hpd_event_trigger(udphy, udphy->dp_sink_hpd_cfg);
++
++ mutex_unlock(&udphy->mutex);
++
++ return 0;
++}
++
++static int rk_udphy_dp_phy_exit(struct phy *phy)
++{
++ struct rk_udphy *udphy = phy_get_drvdata(phy);
++
++ mutex_lock(&udphy->mutex);
++ udphy->dp_in_use = false;
++ mutex_unlock(&udphy->mutex);
++ return 0;
++}
++
++static int rk_udphy_dp_phy_power_on(struct phy *phy)
++{
++ struct rk_udphy *udphy = phy_get_drvdata(phy);
++ int ret, dp_lanes;
++
++ mutex_lock(&udphy->mutex);
++
++ dp_lanes = rk_udphy_dplane_get(udphy);
++ phy_set_bus_width(phy, dp_lanes);
++
++ ret = rk_udphy_power_on(udphy, UDPHY_MODE_DP);
++ if (ret)
++ goto unlock;
++
++ rk_udphy_dplane_enable(udphy, dp_lanes);
++
++ rk_udphy_dplane_select(udphy);
++
++unlock:
++ mutex_unlock(&udphy->mutex);
++ /*
++ * If data send by aux channel too fast after phy power on,
++ * the aux may be not ready which will cause aux error. Adding
++ * delay to avoid this issue.
++ */
++ usleep_range(10000, 11000);
++ return ret;
++}
++
++static int rk_udphy_dp_phy_power_off(struct phy *phy)
++{
++ struct rk_udphy *udphy = phy_get_drvdata(phy);
++
++ mutex_lock(&udphy->mutex);
++ rk_udphy_dplane_enable(udphy, 0);
++ rk_udphy_power_off(udphy, UDPHY_MODE_DP);
++ mutex_unlock(&udphy->mutex);
++
++ return 0;
++}
++
++static int rk_udphy_dp_phy_verify_link_rate(unsigned int link_rate)
++{
++ switch (link_rate) {
++ case 1620:
++ case 2700:
++ case 5400:
++ case 8100:
++ break;
++
++ default:
++ return -EINVAL;
++ }
++
++ return 0;
++}
++
++static int rk_udphy_dp_phy_verify_config(struct rk_udphy *udphy,
++ struct phy_configure_opts_dp *dp)
++{
++ int i, ret;
++
++ /* If changing link rate was required, verify it's supported. */
++ ret = rk_udphy_dp_phy_verify_link_rate(dp->link_rate);
++ if (ret)
++ return ret;
++
++ /* Verify lane count. */
++ switch (dp->lanes) {
++ case 1:
++ case 2:
++ case 4:
++ /* valid lane count. */
++ break;
++
++ default:
++ return -EINVAL;
++ }
++
++ /*
++ * If changing voltages is required, check swing and pre-emphasis
++ * levels, per-lane.
++ */
++ if (dp->set_voltages) {
++ /* Lane count verified previously. */
++ for (i = 0; i < dp->lanes; i++) {
++ if (dp->voltage[i] > 3 || dp->pre[i] > 3)
++ return -EINVAL;
++
++ /*
++ * Sum of voltage swing and pre-emphasis levels cannot
++ * exceed 3.
++ */
++ if (dp->voltage[i] + dp->pre[i] > 3)
++ return -EINVAL;
++ }
++ }
++
++ return 0;
++}
++
++static void rk_udphy_dp_set_voltage(struct rk_udphy *udphy, u8 bw,
++ u32 voltage, u32 pre, u32 lane)
++{
++ const struct rk_udphy_cfg *cfg = udphy->cfgs;
++ const struct rk_udphy_dp_tx_drv_ctrl (*dp_ctrl)[4];
++ u32 offset = 0x800 * lane;
++ u32 val;
++
++ if (udphy->mux)
++ dp_ctrl = cfg->dp_tx_ctrl_cfg_typec[bw];
++ else
++ dp_ctrl = cfg->dp_tx_ctrl_cfg[bw];
++
++ val = dp_ctrl[voltage][pre].trsv_reg0204;
++ regmap_write(udphy->pma_regmap, 0x0810 + offset, val);
++
++ val = dp_ctrl[voltage][pre].trsv_reg0205;
++ regmap_write(udphy->pma_regmap, 0x0814 + offset, val);
++
++ val = dp_ctrl[voltage][pre].trsv_reg0206;
++ regmap_write(udphy->pma_regmap, 0x0818 + offset, val);
++
++ val = dp_ctrl[voltage][pre].trsv_reg0207;
++ regmap_write(udphy->pma_regmap, 0x081c + offset, val);
++}
++
++static int rk_udphy_dp_phy_configure(struct phy *phy,
++ union phy_configure_opts *opts)
++{
++ struct rk_udphy *udphy = phy_get_drvdata(phy);
++ struct phy_configure_opts_dp *dp = &opts->dp;
++ u32 i, val, lane;
++ int ret;
++
++ ret = rk_udphy_dp_phy_verify_config(udphy, dp);
++ if (ret)
++ return ret;
++
++ if (dp->set_rate) {
++ regmap_update_bits(udphy->pma_regmap, CMN_DP_RSTN_OFFSET,
++ CMN_DP_CMN_RSTN, FIELD_PREP(CMN_DP_CMN_RSTN, 0x0));
++
++ switch (dp->link_rate) {
++ case 1620:
++ udphy->bw = DP_BW_RBR;
++ break;
++
++ case 2700:
++ udphy->bw = DP_BW_HBR;
++ break;
++
++ case 5400:
++ udphy->bw = DP_BW_HBR2;
++ break;
++
++ case 8100:
++ udphy->bw = DP_BW_HBR3;
++ break;
++
++ default:
++ return -EINVAL;
++ }
++
++ regmap_update_bits(udphy->pma_regmap, CMN_DP_LINK_OFFSET, CMN_DP_TX_LINK_BW,
++ FIELD_PREP(CMN_DP_TX_LINK_BW, udphy->bw));
++ regmap_update_bits(udphy->pma_regmap, CMN_SSC_EN_OFFSET, CMN_ROPLL_SSC_EN,
++ FIELD_PREP(CMN_ROPLL_SSC_EN, dp->ssc));
++ regmap_update_bits(udphy->pma_regmap, CMN_DP_RSTN_OFFSET, CMN_DP_CMN_RSTN,
++ FIELD_PREP(CMN_DP_CMN_RSTN, 0x1));
++
++ ret = regmap_read_poll_timeout(udphy->pma_regmap, CMN_ANA_ROPLL_DONE_OFFSET, val,
++ FIELD_GET(CMN_ANA_ROPLL_LOCK_DONE, val) &&
++ FIELD_GET(CMN_ANA_ROPLL_AFC_DONE, val),
++ 0, 1000);
++ if (ret) {
++ dev_err(udphy->dev, "ROPLL is not lock, set_rate failed\n");
++ return ret;
++ }
++ }
++
++ if (dp->set_voltages) {
++ for (i = 0; i < dp->lanes; i++) {
++ lane = udphy->dp_lane_sel[i];
++ switch (dp->link_rate) {
++ case 1620:
++ case 2700:
++ regmap_update_bits(udphy->pma_regmap,
++ TRSV_ANA_TX_CLK_OFFSET_N(lane),
++ LN_ANA_TX_SER_TXCLK_INV,
++ FIELD_PREP(LN_ANA_TX_SER_TXCLK_INV,
++ udphy->lane_mux_sel[lane]));
++ break;
++
++ case 5400:
++ case 8100:
++ regmap_update_bits(udphy->pma_regmap,
++ TRSV_ANA_TX_CLK_OFFSET_N(lane),
++ LN_ANA_TX_SER_TXCLK_INV,
++ FIELD_PREP(LN_ANA_TX_SER_TXCLK_INV, 0x0));
++ break;
++ }
++
++ rk_udphy_dp_set_voltage(udphy, udphy->bw, dp->voltage[i],
++ dp->pre[i], lane);
++ }
++ }
++
++ return 0;
++}
++
++static const struct phy_ops rk_udphy_dp_phy_ops = {
++ .init = rk_udphy_dp_phy_init,
++ .exit = rk_udphy_dp_phy_exit,
++ .power_on = rk_udphy_dp_phy_power_on,
++ .power_off = rk_udphy_dp_phy_power_off,
++ .configure = rk_udphy_dp_phy_configure,
++ .owner = THIS_MODULE,
++};
++
++static int rk_udphy_usb3_phy_init(struct phy *phy)
++{
++ struct rk_udphy *udphy = phy_get_drvdata(phy);
++ int ret;
++
++ mutex_lock(&udphy->mutex);
++ /* DP only or high-speed, disable U3 port */
++ if (!(udphy->mode & UDPHY_MODE_USB) || udphy->hs) {
++ rk_udphy_u3_port_disable(udphy, true);
++ goto unlock;
++ }
++
++ ret = rk_udphy_power_on(udphy, UDPHY_MODE_USB);
++
++unlock:
++ mutex_unlock(&udphy->mutex);
++ return ret;
++}
++
++static int rk_udphy_usb3_phy_exit(struct phy *phy)
++{
++ struct rk_udphy *udphy = phy_get_drvdata(phy);
++
++ mutex_lock(&udphy->mutex);
++ /* DP only or high-speed */
++ if (!(udphy->mode & UDPHY_MODE_USB) || udphy->hs)
++ goto unlock;
++
++ rk_udphy_power_off(udphy, UDPHY_MODE_USB);
++
++unlock:
++ mutex_unlock(&udphy->mutex);
++ return 0;
++}
++
++static const struct phy_ops rk_udphy_usb3_phy_ops = {
++ .init = rk_udphy_usb3_phy_init,
++ .exit = rk_udphy_usb3_phy_exit,
++ .owner = THIS_MODULE,
++};
++
++static int rk_udphy_typec_mux_set(struct typec_mux_dev *mux,
++ struct typec_mux_state *state)
++{
++ struct rk_udphy *udphy = typec_mux_get_drvdata(mux);
++ u8 mode;
++
++ mutex_lock(&udphy->mutex);
++
++ switch (state->mode) {
++ case TYPEC_DP_STATE_C:
++ case TYPEC_DP_STATE_E:
++ udphy->lane_mux_sel[0] = PHY_LANE_MUX_DP;
++ udphy->lane_mux_sel[1] = PHY_LANE_MUX_DP;
++ udphy->lane_mux_sel[2] = PHY_LANE_MUX_DP;
++ udphy->lane_mux_sel[3] = PHY_LANE_MUX_DP;
++ mode = UDPHY_MODE_DP;
++ break;
++
++ case TYPEC_DP_STATE_D:
++ default:
++ if (udphy->flip) {
++ udphy->lane_mux_sel[0] = PHY_LANE_MUX_DP;
++ udphy->lane_mux_sel[1] = PHY_LANE_MUX_DP;
++ udphy->lane_mux_sel[2] = PHY_LANE_MUX_USB;
++ udphy->lane_mux_sel[3] = PHY_LANE_MUX_USB;
++ } else {
++ udphy->lane_mux_sel[0] = PHY_LANE_MUX_USB;
++ udphy->lane_mux_sel[1] = PHY_LANE_MUX_USB;
++ udphy->lane_mux_sel[2] = PHY_LANE_MUX_DP;
++ udphy->lane_mux_sel[3] = PHY_LANE_MUX_DP;
++ }
++ mode = UDPHY_MODE_DP_USB;
++ break;
++ }
++
++ if (state->alt && state->alt->svid == USB_TYPEC_DP_SID) {
++ struct typec_displayport_data *data = state->data;
++
++ if (!data) {
++ rk_udphy_dp_hpd_event_trigger(udphy, false);
++ } else if (data->status & DP_STATUS_IRQ_HPD) {
++ rk_udphy_dp_hpd_event_trigger(udphy, false);
++ usleep_range(750, 800);
++ rk_udphy_dp_hpd_event_trigger(udphy, true);
++ } else if (data->status & DP_STATUS_HPD_STATE) {
++ if (udphy->mode != mode) {
++ udphy->mode = mode;
++ udphy->mode_change = true;
++ }
++ rk_udphy_dp_hpd_event_trigger(udphy, true);
++ } else {
++ rk_udphy_dp_hpd_event_trigger(udphy, false);
++ }
++ }
++
++ mutex_unlock(&udphy->mutex);
++ return 0;
++}
++
++static void rk_udphy_typec_mux_unregister(void *data)
++{
++ struct rk_udphy *udphy = data;
++
++ typec_mux_unregister(udphy->mux);
++}
++
++static int rk_udphy_setup_typec_mux(struct rk_udphy *udphy)
++{
++ struct typec_mux_desc mux_desc = {};
++
++ mux_desc.drvdata = udphy;
++ mux_desc.fwnode = dev_fwnode(udphy->dev);
++ mux_desc.set = rk_udphy_typec_mux_set;
++
++ udphy->mux = typec_mux_register(udphy->dev, &mux_desc);
++ if (IS_ERR(udphy->mux)) {
++ dev_err(udphy->dev, "Error register typec mux: %ld\n",
++ PTR_ERR(udphy->mux));
++ return PTR_ERR(udphy->mux);
++ }
++
++ return devm_add_action_or_reset(udphy->dev, rk_udphy_typec_mux_unregister,
++ udphy);
++}
++
++static const struct regmap_config rk_udphy_pma_regmap_cfg = {
++ .reg_bits = 32,
++ .reg_stride = 4,
++ .val_bits = 32,
++ .fast_io = true,
++ .max_register = 0x20dc,
++};
++
++static struct phy *rk_udphy_phy_xlate(struct device *dev, struct of_phandle_args *args)
++{
++ struct rk_udphy *udphy = dev_get_drvdata(dev);
++
++ if (args->args_count == 0)
++ return ERR_PTR(-EINVAL);
++
++ switch (args->args[0]) {
++ case PHY_TYPE_USB3:
++ return udphy->phy_u3;
++ case PHY_TYPE_DP:
++ return udphy->phy_dp;
++ }
++
++ return ERR_PTR(-EINVAL);
++}
++
++static int rk_udphy_probe(struct platform_device *pdev)
++{
++ struct device *dev = &pdev->dev;
++ struct phy_provider *phy_provider;
++ struct resource *res;
++ struct rk_udphy *udphy;
++ void __iomem *base;
++ int id, ret;
++
++ udphy = devm_kzalloc(dev, sizeof(*udphy), GFP_KERNEL);
++ if (!udphy)
++ return -ENOMEM;
++
++ udphy->cfgs = device_get_match_data(dev);
++ if (!udphy->cfgs)
++ return dev_err_probe(dev, -EINVAL, "missing match data\n");
++
++ base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
++ if (IS_ERR(base))
++ return PTR_ERR(base);
++
++ /* find the phy-id from the io address */
++ udphy->id = -ENODEV;
++ for (id = 0; id < udphy->cfgs->num_phys; id++) {
++ if (res->start == udphy->cfgs->phy_ids[id]) {
++ udphy->id = id;
++ break;
++ }
++ }
++
++ if (udphy->id < 0)
++ return dev_err_probe(dev, -ENODEV, "no matching device found\n");
++
++ udphy->pma_regmap = devm_regmap_init_mmio(dev, base + UDPHY_PMA,
++ &rk_udphy_pma_regmap_cfg);
++ if (IS_ERR(udphy->pma_regmap))
++ return PTR_ERR(udphy->pma_regmap);
++
++ udphy->dev = dev;
++ ret = rk_udphy_parse_dt(udphy);
++ if (ret)
++ return ret;
++
++ ret = rk_udphy_get_initial_status(udphy);
++ if (ret)
++ return ret;
++
++ mutex_init(&udphy->mutex);
++ platform_set_drvdata(pdev, udphy);
++
++ if (device_property_present(dev, "orientation-switch")) {
++ ret = rk_udphy_setup_orien_switch(udphy);
++ if (ret)
++ return ret;
++ }
++
++ if (device_property_present(dev, "mode-switch")) {
++ ret = rk_udphy_setup_typec_mux(udphy);
++ if (ret)
++ return ret;
++ }
++
++ udphy->phy_u3 = devm_phy_create(dev, dev->of_node, &rk_udphy_usb3_phy_ops);
++ if (IS_ERR(udphy->phy_u3)) {
++ ret = PTR_ERR(udphy->phy_u3);
++ return dev_err_probe(dev, ret, "failed to create USB3 phy\n");
++ }
++ phy_set_drvdata(udphy->phy_u3, udphy);
++
++ udphy->phy_dp = devm_phy_create(dev, dev->of_node, &rk_udphy_dp_phy_ops);
++ if (IS_ERR(udphy->phy_dp)) {
++ ret = PTR_ERR(udphy->phy_dp);
++ return dev_err_probe(dev, ret, "failed to create DP phy\n");
++ }
++ phy_set_bus_width(udphy->phy_dp, rk_udphy_dplane_get(udphy));
++ udphy->phy_dp->attrs.max_link_rate = 8100;
++ phy_set_drvdata(udphy->phy_dp, udphy);
++
++ phy_provider = devm_of_phy_provider_register(dev, rk_udphy_phy_xlate);
++ if (IS_ERR(phy_provider)) {
++ ret = PTR_ERR(phy_provider);
++ return dev_err_probe(dev, ret, "failed to register phy provider\n");
++ }
++
++ return 0;
++}
++
++static int __maybe_unused rk_udphy_resume(struct device *dev)
++{
++ struct rk_udphy *udphy = dev_get_drvdata(dev);
++
++ if (udphy->dp_sink_hpd_sel)
++ rk_udphy_dp_hpd_event_trigger(udphy, udphy->dp_sink_hpd_cfg);
++
++ return 0;
++}
++
++static const struct dev_pm_ops rk_udphy_pm_ops = {
++ SET_LATE_SYSTEM_SLEEP_PM_OPS(NULL, rk_udphy_resume)
++};
++
++static const char * const rk_udphy_rst_list[] = {
++ "init", "cmn", "lane", "pcs_apb", "pma_apb"
++};
++
++static const struct rk_udphy_cfg rk3588_udphy_cfgs = {
++ .num_phys = 2,
++ .phy_ids = {
++ 0xfed80000,
++ 0xfed90000,
++ },
++ .num_rsts = ARRAY_SIZE(rk_udphy_rst_list),
++ .rst_list = rk_udphy_rst_list,
++ .grfcfg = {
++ /* u2phy-grf */
++ .bvalid_phy_con = RK_UDPHY_GEN_GRF_REG(0x0008, 1, 0, 0x2, 0x3),
++ .bvalid_grf_con = RK_UDPHY_GEN_GRF_REG(0x0010, 3, 2, 0x2, 0x3),
++
++ /* usb-grf */
++ .usb3otg0_cfg = RK_UDPHY_GEN_GRF_REG(0x001c, 15, 0, 0x1100, 0x0188),
++ .usb3otg1_cfg = RK_UDPHY_GEN_GRF_REG(0x0034, 15, 0, 0x1100, 0x0188),
++
++ /* usbdpphy-grf */
++ .low_pwrn = RK_UDPHY_GEN_GRF_REG(0x0004, 13, 13, 0, 1),
++ .rx_lfps = RK_UDPHY_GEN_GRF_REG(0x0004, 14, 14, 0, 1),
++ },
++ .vogrfcfg = {
++ {
++ .hpd_trigger = RK_UDPHY_GEN_GRF_REG(0x0000, 11, 10, 1, 3),
++ .dp_lane_reg = 0x0000,
++ },
++ {
++ .hpd_trigger = RK_UDPHY_GEN_GRF_REG(0x0008, 11, 10, 1, 3),
++ .dp_lane_reg = 0x0008,
++ },
++ },
++ .dp_tx_ctrl_cfg = {
++ rk3588_dp_tx_drv_ctrl_rbr_hbr,
++ rk3588_dp_tx_drv_ctrl_rbr_hbr,
++ rk3588_dp_tx_drv_ctrl_hbr2,
++ rk3588_dp_tx_drv_ctrl_hbr3,
++ },
++ .dp_tx_ctrl_cfg_typec = {
++ rk3588_dp_tx_drv_ctrl_rbr_hbr_typec,
++ rk3588_dp_tx_drv_ctrl_rbr_hbr_typec,
++ rk3588_dp_tx_drv_ctrl_hbr2,
++ rk3588_dp_tx_drv_ctrl_hbr3,
++ },
++};
++
++static const struct of_device_id rk_udphy_dt_match[] = {
++ {
++ .compatible = "rockchip,rk3588-usbdp-phy",
++ .data = &rk3588_udphy_cfgs
++ },
++ { /* sentinel */ }
++};
++MODULE_DEVICE_TABLE(of, rk_udphy_dt_match);
++
++static struct platform_driver rk_udphy_driver = {
++ .probe = rk_udphy_probe,
++ .driver = {
++ .name = "rockchip-usbdp-phy",
++ .of_match_table = rk_udphy_dt_match,
++ .pm = &rk_udphy_pm_ops,
++ },
++};
++module_platform_driver(rk_udphy_driver);
++
++MODULE_AUTHOR("Frank Wang <frank.wang at rock-chips.com>");
++MODULE_AUTHOR("Zhang Yubing <yubing.zhang at rock-chips.com>");
++MODULE_DESCRIPTION("Rockchip USBDP Combo PHY driver");
++MODULE_LICENSE("GPL");
diff --git a/target/linux/rockchip/patches-6.6/032-02-v6.10-phy-rockchip-usbdp-fix-uninitialized-variable.patch b/target/linux/rockchip/patches-6.6/032-02-v6.10-phy-rockchip-usbdp-fix-uninitialized-variable.patch
new file mode 100644
index 0000000000..65bd8a7ed8
--- /dev/null
+++ b/target/linux/rockchip/patches-6.6/032-02-v6.10-phy-rockchip-usbdp-fix-uninitialized-variable.patch
@@ -0,0 +1,35 @@
+From c9342d1a351ee1249fa98d936f756299a83d5684 Mon Sep 17 00:00:00 2001
+From: Sebastian Reichel <sebastian.reichel at collabora.com>
+Date: Tue, 16 Apr 2024 16:51:23 +0200
+Subject: [PATCH] phy: rockchip: usbdp: fix uninitialized variable
+
+The ret variable may not be initialized in rk_udphy_usb3_phy_init(), if
+the PHY is not using USB3 mode.
+
+Since the DisplayPort part is handled separately and the PHY does not
+support USB2 (which is routed to another PHY on Rockchip RK3588), the
+right exit code for this case is 0. Thus let's initialize the variable
+accordingly.
+
+Fixes: 2f70bbddeb457 ("phy: rockchip: add usbdp combo phy driver")
+Reported-by: kernel test robot <lkp at intel.com>
+Closes: https://lore.kernel.org/oe-kbuild-all/202404141048.qFAYDctQ-lkp@intel.com/
+Signed-off-by: Sebastian Reichel <sebastian.reichel at collabora.com>
+Reviewed-by: Muhammad Usama Anjum <usama.anjum at collabora.com>
+Link: https://lore.kernel.org/r/20240416145233.94687-1-sebastian.reichel@collabora.com
+Signed-off-by: Vinod Koul <vkoul at kernel.org>
+---
+ drivers/phy/rockchip/phy-rockchip-usbdp.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/drivers/phy/rockchip/phy-rockchip-usbdp.c
++++ b/drivers/phy/rockchip/phy-rockchip-usbdp.c
+@@ -1285,7 +1285,7 @@ static const struct phy_ops rk_udphy_dp_
+ static int rk_udphy_usb3_phy_init(struct phy *phy)
+ {
+ struct rk_udphy *udphy = phy_get_drvdata(phy);
+- int ret;
++ int ret = 0;
+
+ mutex_lock(&udphy->mutex);
+ /* DP only or high-speed, disable U3 port */
diff --git a/target/linux/rockchip/patches-6.6/032-03-v6.10-phy-rockchip-fix-CONFIG_TYPEC-dependency.patch b/target/linux/rockchip/patches-6.6/032-03-v6.10-phy-rockchip-fix-CONFIG_TYPEC-dependency.patch
new file mode 100644
index 0000000000..a8b9aa15fc
--- /dev/null
+++ b/target/linux/rockchip/patches-6.6/032-03-v6.10-phy-rockchip-fix-CONFIG_TYPEC-dependency.patch
@@ -0,0 +1,43 @@
+From 9c79b779643e56d4253bd3ba6998c58c819943af Mon Sep 17 00:00:00 2001
+From: Arnd Bergmann <arnd at arndb.de>
+Date: Mon, 15 Apr 2024 19:42:25 +0200
+Subject: [PATCH] phy: rockchip: fix CONFIG_TYPEC dependency
+
+The newly added driver causes a warning about missing dependencies
+by selecting CONFIG_TYPEC unconditionally:
+
+WARNING: unmet direct dependencies detected for TYPEC
+ Depends on [n]: USB_SUPPORT [=n]
+ Selected by [y]:
+ - PHY_ROCKCHIP_USBDP [=y] && ARCH_ROCKCHIP [=y] && OF [=y]
+
+WARNING: unmet direct dependencies detected for USB_COMMON
+ Depends on [n]: USB_SUPPORT [=n]
+ Selected by [y]:
+ - EXTCON_RTK_TYPE_C [=y] && EXTCON [=y] && (ARCH_REALTEK [=y] || COMPILE_TEST [=y]) && TYPEC [=y]
+
+Since that is a user-visible option, it should not really be selected
+in the first place. Replace the 'select' with a 'depends on' as
+we have for similar drivers.
+
+Fixes: 2f70bbddeb45 ("phy: rockchip: add usbdp combo phy driver")
+Signed-off-by: Arnd Bergmann <arnd at arndb.de>
+Reviewed-by: Heiko Stuebner <heiko at sntech.de>
+Link: https://lore.kernel.org/r/20240415174241.77982-1-arnd@kernel.org
+Signed-off-by: Vinod Koul <vkoul at kernel.org>
+---
+ drivers/phy/rockchip/Kconfig | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/drivers/phy/rockchip/Kconfig
++++ b/drivers/phy/rockchip/Kconfig
+@@ -111,8 +111,8 @@ config PHY_ROCKCHIP_USB
+ config PHY_ROCKCHIP_USBDP
+ tristate "Rockchip USBDP COMBO PHY Driver"
+ depends on ARCH_ROCKCHIP && OF
++ depends on TYPEC
+ select GENERIC_PHY
+- select TYPEC
+ help
+ Enable this to support the Rockchip USB3.0/DP combo PHY with
+ Samsung IP block. This is required for USB3 support on RK3588.
diff --git a/target/linux/rockchip/patches-6.6/032-04-v6.10-phy-rockchip-Fix-typo-in-function-names.patch b/target/linux/rockchip/patches-6.6/032-04-v6.10-phy-rockchip-Fix-typo-in-function-names.patch
new file mode 100644
index 0000000000..9495dd2b10
--- /dev/null
+++ b/target/linux/rockchip/patches-6.6/032-04-v6.10-phy-rockchip-Fix-typo-in-function-names.patch
@@ -0,0 +1,79 @@
+From 9b6bfad9070a95d19973be17177e5d9220cbbf1f Mon Sep 17 00:00:00 2001
+From: Rick Wertenbroek <rick.wertenbroek at gmail.com>
+Date: Thu, 7 Mar 2024 10:53:18 +0100
+Subject: [PATCH] phy: rockchip: Fix typo in function names
+
+Several functions had "rochchip" instead of "rockchip" in their name.
+Replace "rochchip" by "rockchip".
+
+Signed-off-By: Rick Wertenbroek <rick.wertenbroek at gmail.com>
+Reviewed-by: Heiko Stuebner <heiko at sntech.de>
+Link: https://lore.kernel.org/r/20240307095318.3651498-1-rick.wertenbroek@gmail.com
+Signed-off-by: Vinod Koul <vkoul at kernel.org>
+---
+ drivers/phy/rockchip/phy-rockchip-naneng-combphy.c | 4 ++--
+ drivers/phy/rockchip/phy-rockchip-snps-pcie3.c | 12 ++++++------
+ 2 files changed, 8 insertions(+), 8 deletions(-)
+
+--- a/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
++++ b/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
+@@ -248,7 +248,7 @@ static int rockchip_combphy_exit(struct
+ return 0;
+ }
+
+-static const struct phy_ops rochchip_combphy_ops = {
++static const struct phy_ops rockchip_combphy_ops = {
+ .init = rockchip_combphy_init,
+ .exit = rockchip_combphy_exit,
+ .owner = THIS_MODULE,
+@@ -364,7 +364,7 @@ static int rockchip_combphy_probe(struct
+ return ret;
+ }
+
+- priv->phy = devm_phy_create(dev, NULL, &rochchip_combphy_ops);
++ priv->phy = devm_phy_create(dev, NULL, &rockchip_combphy_ops);
+ if (IS_ERR(priv->phy)) {
+ dev_err(dev, "failed to create combphy\n");
+ return PTR_ERR(priv->phy);
+--- a/drivers/phy/rockchip/phy-rockchip-snps-pcie3.c
++++ b/drivers/phy/rockchip/phy-rockchip-snps-pcie3.c
+@@ -182,7 +182,7 @@ static const struct rockchip_p3phy_ops r
+ .phy_init = rockchip_p3phy_rk3588_init,
+ };
+
+-static int rochchip_p3phy_init(struct phy *phy)
++static int rockchip_p3phy_init(struct phy *phy)
+ {
+ struct rockchip_p3phy_priv *priv = phy_get_drvdata(phy);
+ int ret;
+@@ -205,7 +205,7 @@ static int rochchip_p3phy_init(struct ph
+ return ret;
+ }
+
+-static int rochchip_p3phy_exit(struct phy *phy)
++static int rockchip_p3phy_exit(struct phy *phy)
+ {
+ struct rockchip_p3phy_priv *priv = phy_get_drvdata(phy);
+
+@@ -214,9 +214,9 @@ static int rochchip_p3phy_exit(struct ph
+ return 0;
+ }
+
+-static const struct phy_ops rochchip_p3phy_ops = {
+- .init = rochchip_p3phy_init,
+- .exit = rochchip_p3phy_exit,
++static const struct phy_ops rockchip_p3phy_ops = {
++ .init = rockchip_p3phy_init,
++ .exit = rockchip_p3phy_exit,
+ .set_mode = rockchip_p3phy_set_mode,
+ .owner = THIS_MODULE,
+ };
+@@ -275,7 +275,7 @@ static int rockchip_p3phy_probe(struct p
+ return priv->num_lanes;
+ }
+
+- priv->phy = devm_phy_create(dev, NULL, &rochchip_p3phy_ops);
++ priv->phy = devm_phy_create(dev, NULL, &rockchip_p3phy_ops);
+ if (IS_ERR(priv->phy)) {
+ dev_err(dev, "failed to create combphy\n");
+ return PTR_ERR(priv->phy);
diff --git a/target/linux/rockchip/patches-6.6/032-05-v6.10-phy-rockchip-snps-pcie3-add-support-for.patch b/target/linux/rockchip/patches-6.6/032-05-v6.10-phy-rockchip-snps-pcie3-add-support-for.patch
new file mode 100644
index 0000000000..61c3e0e53c
--- /dev/null
+++ b/target/linux/rockchip/patches-6.6/032-05-v6.10-phy-rockchip-snps-pcie3-add-support-for.patch
@@ -0,0 +1,106 @@
+From a1fe1eca0d8be69ccc1f3d615e5a529df1c82e66 Mon Sep 17 00:00:00 2001
+From: Niklas Cassel <cassel at kernel.org>
+Date: Fri, 12 Apr 2024 14:58:16 +0200
+Subject: [PATCH] phy: rockchip-snps-pcie3: add support for
+ rockchip,rx-common-refclk-mode
+
+>From the RK3588 Technical Reference Manual, Part1,
+section 6.19 PCIe3PHY_GRF Register Description:
+"rxX_cmn_refclk_mode"
+RX common reference clock mode for lane X. This mode should be enabled
+only when the far-end and near-end devices are running with a common
+reference clock.
+
+The hardware reset value for this field is 0x1 (enabled).
+Note that this register field is only available on RK3588, not on RK3568.
+
+The link training either fails or is highly unstable (link state will jump
+continuously between L0 and recovery) when this mode is enabled while
+using an endpoint running in Separate Reference Clock with No SSC (SRNS)
+mode or Separate Reference Clock with SSC (SRIS) mode.
+(Which is usually the case when using a real SoC as endpoint, e.g. the
+RK3588 PCIe controller can run in both Root Complex and Endpoint mode.)
+
+Add support for the device tree property rockchip,rx-common-refclk-mode,
+such that the PCIe PHY can be used in configurations where the Root
+Complex and Endpoint are not using a common reference clock.
+
+Signed-off-by: Niklas Cassel <cassel at kernel.org>
+Link: https://lore.kernel.org/r/20240412125818.17052-3-cassel@kernel.org
+Signed-off-by: Vinod Koul <vkoul at kernel.org>
+---
+ .../phy/rockchip/phy-rockchip-snps-pcie3.c | 37 +++++++++++++++++++
+ 1 file changed, 37 insertions(+)
+
+--- a/drivers/phy/rockchip/phy-rockchip-snps-pcie3.c
++++ b/drivers/phy/rockchip/phy-rockchip-snps-pcie3.c
+@@ -35,11 +35,17 @@
+ #define RK3588_PCIE3PHY_GRF_CMN_CON0 0x0
+ #define RK3588_PCIE3PHY_GRF_PHY0_STATUS1 0x904
+ #define RK3588_PCIE3PHY_GRF_PHY1_STATUS1 0xa04
++#define RK3588_PCIE3PHY_GRF_PHY0_LN0_CON1 0x1004
++#define RK3588_PCIE3PHY_GRF_PHY0_LN1_CON1 0x1104
++#define RK3588_PCIE3PHY_GRF_PHY1_LN0_CON1 0x2004
++#define RK3588_PCIE3PHY_GRF_PHY1_LN1_CON1 0x2104
+ #define RK3588_SRAM_INIT_DONE(reg) (reg & BIT(0))
+
+ #define RK3588_BIFURCATION_LANE_0_1 BIT(0)
+ #define RK3588_BIFURCATION_LANE_2_3 BIT(1)
+ #define RK3588_LANE_AGGREGATION BIT(2)
++#define RK3588_RX_CMN_REFCLK_MODE_EN ((BIT(7) << 16) | BIT(7))
++#define RK3588_RX_CMN_REFCLK_MODE_DIS (BIT(7) << 16)
+ #define RK3588_PCIE1LN_SEL_EN (GENMASK(1, 0) << 16)
+ #define RK3588_PCIE30_PHY_MODE_EN (GENMASK(2, 0) << 16)
+
+@@ -60,6 +66,7 @@ struct rockchip_p3phy_priv {
+ int num_clks;
+ int num_lanes;
+ u32 lanes[4];
++ u32 rx_cmn_refclk_mode[4];
+ };
+
+ struct rockchip_p3phy_ops {
+@@ -137,6 +144,19 @@ static int rockchip_p3phy_rk3588_init(st
+ u8 mode = RK3588_LANE_AGGREGATION; /* default */
+ int ret;
+
++ regmap_write(priv->phy_grf, RK3588_PCIE3PHY_GRF_PHY0_LN0_CON1,
++ priv->rx_cmn_refclk_mode[0] ? RK3588_RX_CMN_REFCLK_MODE_EN :
++ RK3588_RX_CMN_REFCLK_MODE_DIS);
++ regmap_write(priv->phy_grf, RK3588_PCIE3PHY_GRF_PHY0_LN1_CON1,
++ priv->rx_cmn_refclk_mode[1] ? RK3588_RX_CMN_REFCLK_MODE_EN :
++ RK3588_RX_CMN_REFCLK_MODE_DIS);
++ regmap_write(priv->phy_grf, RK3588_PCIE3PHY_GRF_PHY1_LN0_CON1,
++ priv->rx_cmn_refclk_mode[2] ? RK3588_RX_CMN_REFCLK_MODE_EN :
++ RK3588_RX_CMN_REFCLK_MODE_DIS);
++ regmap_write(priv->phy_grf, RK3588_PCIE3PHY_GRF_PHY1_LN1_CON1,
++ priv->rx_cmn_refclk_mode[3] ? RK3588_RX_CMN_REFCLK_MODE_EN :
++ RK3588_RX_CMN_REFCLK_MODE_DIS);
++
+ /* Deassert PCIe PMA output clamp mode */
+ regmap_write(priv->phy_grf, RK3588_PCIE3PHY_GRF_CMN_CON0, BIT(8) | BIT(24));
+
+@@ -275,6 +295,23 @@ static int rockchip_p3phy_probe(struct p
+ return priv->num_lanes;
+ }
+
++ ret = of_property_read_variable_u32_array(dev->of_node,
++ "rockchip,rx-common-refclk-mode",
++ priv->rx_cmn_refclk_mode, 1,
++ ARRAY_SIZE(priv->rx_cmn_refclk_mode));
++ /*
++ * if no rockchip,rx-common-refclk-mode, assume enabled for all lanes in
++ * order to be DT backwards compatible. (Since HW reset val is enabled.)
++ */
++ if (ret == -EINVAL) {
++ for (int i = 0; i < ARRAY_SIZE(priv->rx_cmn_refclk_mode); i++)
++ priv->rx_cmn_refclk_mode[i] = 1;
++ } else if (ret < 0) {
++ dev_err(dev, "failed to read rockchip,rx-common-refclk-mode property %d\n",
++ ret);
++ return ret;
++ }
++
+ priv->phy = devm_phy_create(dev, NULL, &rockchip_p3phy_ops);
+ if (IS_ERR(priv->phy)) {
+ dev_err(dev, "failed to create combphy\n");
diff --git a/target/linux/rockchip/patches-6.6/034-v6.7-usb-dwc3-add-optional-PHY-interface-clocks.patch b/target/linux/rockchip/patches-6.6/034-v6.7-usb-dwc3-add-optional-PHY-interface-clocks.patch
new file mode 100644
index 0000000000..ea40a3c051
--- /dev/null
+++ b/target/linux/rockchip/patches-6.6/034-v6.7-usb-dwc3-add-optional-PHY-interface-clocks.patch
@@ -0,0 +1,91 @@
+From 97789b93b792fc97ad4476b79e0f38ffa8e7e0ee Mon Sep 17 00:00:00 2001
+From: Sebastian Reichel <sebastian.reichel at collabora.com>
+Date: Fri, 20 Oct 2023 16:11:41 +0200
+Subject: [PATCH] usb: dwc3: add optional PHY interface clocks
+
+On Rockchip RK3588 one of the DWC3 cores is integrated weirdly and
+requires two extra clocks to be enabled. Without these extra clocks
+hot-plugging USB devices is broken.
+
+Signed-off-by: Sebastian Reichel <sebastian.reichel at collabora.com>
+Acked-by: Thinh Nguyen <Thinh.Nguyen at synopsys.com>
+Link: https://lore.kernel.org/r/20231020150022.48725-3-sebastian.reichel@collabora.com
+Signed-off-by: Greg Kroah-Hartman <gregkh at linuxfoundation.org>
+---
+ drivers/usb/dwc3/core.c | 28 ++++++++++++++++++++++++++++
+ drivers/usb/dwc3/core.h | 4 ++++
+ 2 files changed, 32 insertions(+)
+
+--- a/drivers/usb/dwc3/core.c
++++ b/drivers/usb/dwc3/core.c
+@@ -818,8 +818,20 @@ static int dwc3_clk_enable(struct dwc3 *
+ if (ret)
+ goto disable_ref_clk;
+
++ ret = clk_prepare_enable(dwc->utmi_clk);
++ if (ret)
++ goto disable_susp_clk;
++
++ ret = clk_prepare_enable(dwc->pipe_clk);
++ if (ret)
++ goto disable_utmi_clk;
++
+ return 0;
+
++disable_utmi_clk:
++ clk_disable_unprepare(dwc->utmi_clk);
++disable_susp_clk:
++ clk_disable_unprepare(dwc->susp_clk);
+ disable_ref_clk:
+ clk_disable_unprepare(dwc->ref_clk);
+ disable_bus_clk:
+@@ -829,6 +841,8 @@ disable_bus_clk:
+
+ static void dwc3_clk_disable(struct dwc3 *dwc)
+ {
++ clk_disable_unprepare(dwc->pipe_clk);
++ clk_disable_unprepare(dwc->utmi_clk);
+ clk_disable_unprepare(dwc->susp_clk);
+ clk_disable_unprepare(dwc->ref_clk);
+ clk_disable_unprepare(dwc->bus_clk);
+@@ -1842,6 +1856,20 @@ static int dwc3_get_clocks(struct dwc3 *
+ }
+ }
+
++ /* specific to Rockchip RK3588 */
++ dwc->utmi_clk = devm_clk_get_optional(dev, "utmi");
++ if (IS_ERR(dwc->utmi_clk)) {
++ return dev_err_probe(dev, PTR_ERR(dwc->utmi_clk),
++ "could not get utmi clock\n");
++ }
++
++ /* specific to Rockchip RK3588 */
++ dwc->pipe_clk = devm_clk_get_optional(dev, "pipe");
++ if (IS_ERR(dwc->pipe_clk)) {
++ return dev_err_probe(dev, PTR_ERR(dwc->pipe_clk),
++ "could not get pipe clock\n");
++ }
++
+ return 0;
+ }
+
+--- a/drivers/usb/dwc3/core.h
++++ b/drivers/usb/dwc3/core.h
+@@ -996,6 +996,8 @@ struct dwc3_scratchpad_array {
+ * @bus_clk: clock for accessing the registers
+ * @ref_clk: reference clock
+ * @susp_clk: clock used when the SS phy is in low power (S3) state
++ * @utmi_clk: clock used for USB2 PHY communication
++ * @pipe_clk: clock used for USB3 PHY communication
+ * @reset: reset control
+ * @regs: base address for our registers
+ * @regs_size: address space size
+@@ -1166,6 +1168,8 @@ struct dwc3 {
+ struct clk *bus_clk;
+ struct clk *ref_clk;
+ struct clk *susp_clk;
++ struct clk *utmi_clk;
++ struct clk *pipe_clk;
+
+ struct reset_control *reset;
+
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