[openwrt/openwrt] uboot-mediatek: backport fix for unstable UART on MT7622

[LEDE Commits]

dangole pushed a commit to openwrt/openwrt.git, branch openwrt-22.03:
https://git.openwrt.org/93e6581b900cfbead7888046c8ff7caa1eb79317

commit 93e6581b900cfbead7888046c8ff7caa1eb79317
Author: Daniel Golle <daniel at makrotopia.org>
AuthorDate: Sat Sep 3 01:57:08 2022 +0100

    uboot-mediatek: backport fix for unstable UART on MT7622
    
    Import pending patch "arm: dts: mt7622: force high-speed mode for uart"
    from Weijie Gao <weijie.gao at mediatek.com> fixing the UART problems on
    MT7622 which made it hard to use the U-Boot menu on devices with this
    SoC.
    
    This patch is also contained in commit
     c09eb08dad ("uboot-mediatek: add support for MT798x platforms")
    in the development branch.
    
    Signed-off-by: Daniel Golle <daniel at makrotopia.org>
---
 ...dts-mt7622-force-high-speed-mode-for-uart.patch | 26 ++++++++++++++++++++++
 1 file changed, 26 insertions(+)

diff --git a/package/boot/uboot-mediatek/patches/002-0011-arm-dts-mt7622-force-high-speed-mode-for-uart.patch b/package/boot/uboot-mediatek/patches/002-0011-arm-dts-mt7622-force-high-speed-mode-for-uart.patch
new file mode 100644
index 0000000000..9bd7a9e64d
--- /dev/null
+++ b/package/boot/uboot-mediatek/patches/002-0011-arm-dts-mt7622-force-high-speed-mode-for-uart.patch
@@ -0,0 +1,26 @@
+From 79786aa175010dde78f95970939e8efadd7a3295 Mon Sep 17 00:00:00 2001
+From: Weijie Gao <weijie.gao at mediatek.com>
+Date: Wed, 31 Aug 2022 19:04:34 +0800
+Subject: [PATCH 11/32] arm: dts: mt7622: force high-speed mode for uart
+
+The input clock for uart is too slow (25MHz) which introduces frequent data
+error on both receiving and transmitting even if the baudrate is 115200.
+
+Using high-speed can significantly solve this issue.
+
+Reviewed-by: Simon Glass <sjg at chromium.org>
+Signed-off-by: Weijie Gao <weijie.gao at mediatek.com>
+---
+ arch/arm/dts/mt7622.dtsi | 1 +
+ 1 file changed, 1 insertion(+)
+
+--- a/arch/arm/dts/mt7622.dtsi
++++ b/arch/arm/dts/mt7622.dtsi
+@@ -191,6 +191,7 @@
+ 		status = "disabled";
+ 		assigned-clocks = <&topckgen CLK_TOP_AXI_SEL>;
+ 		assigned-clock-parents = <&topckgen CLK_TOP_SYSPLL1_D2>;
++		mediatek,force-highspeed;
+ 	};
+ 
+ 	mmc0: mmc at 11230000 {