[openwrt/openwrt] ipq806x: add support for Arris TR4400 v2 / RAC2V1A
LEDE Commits
lede-commits at lists.infradead.org
Wed May 4 17:20:22 PDT 2022
mans0n pushed a commit to openwrt/openwrt.git, branch master:
https://git.openwrt.org/f8b0010dfb548469686049f85076fd6a3a6bca2e
commit f8b0010dfb548469686049f85076fd6a3a6bca2e
Author: Rodrigo Balerdi <lanchon at gmail.com>
AuthorDate: Thu Apr 7 03:18:59 2022 -0300
ipq806x: add support for Arris TR4400 v2 / RAC2V1A
Hardware specs:
SoC: Qualcomm IPQ8065 (dual core Cortex-A15)
RAM: 512 MB DDR3
Flash: 256 MB NAND, 32 MB NOR
WiFi: QCA9983 2.4 GHz, QCA9984 5 GHz
Switch: QCA8337
Ethernet: 5x 10/100/1000 Mbit/s
USB: 1x USB 3.0 Type-A
Buttons: WPS, Reset
Power: 12 VDC, 2.5 A
Ethernet ports:
1x WAN: connected to eth2
4x LAN: connected via the switch to eth0 and eth1
(eth0 is disabled in OEM firmware)
MAC addresses (OEM and OpenWrt):
fw_env @ 0x00 d4:ab:82:??:??:?a LAN (eth1)
fw_env @ 0x06 d4:ab:82:??:??:?b WAN (eth2)
fw_env @ 0x0c d4:ab:82:??:??:?c WLAN 2.4 GHz (ath1)
fw_env @ 0x12 d4:ab:82:??:??:?d WLAN 5 GHz (ath0)
fw_env @ 0x18 d4:ab:82:??:??:?e OEM usage unknown (eth0 in OpenWrt)
OID d4:ab:82 is registered to:
ARRIS Group, Inc., 6450 Sequence Drive, San Diego CA 92121, US
More info:
https://openwrt.org/inbox/toh/arris/tr4400_v2
IMPORTANT:
This port requires moving the 'fw_env' partition prior to first boot to
consolidate 70% of the usable space in flash into a contiguous partition.
'fw_env' contains factory-programmed MAC addresses, SSIDs, and passwords.
Its contents must be copied to 'rootfs_1' prior to booting via initramfs.
Note that the stock 'fw_env' partition will be wiped during sysupgrade.
A writable 'stock_fw_env' partition pointing to the old, stock location
is included in the port to help rolling back this change if desired.
Installation:
- Requires serial access and a TFTP server.
- Fully boot stock, press ENTER, type in:
mtd erase /dev/mtd21
dd if=/dev/mtd22 bs=128K count=1 | mtd write - /dev/mtd21
umount /config && ubidetach -m 23 && mtd erase /dev/mtd23
- Reboot and interrupt U-Boot by pressing a key, type in:
set mtdids 'nand0=nand0'
set mtdparts 'mtdparts=nand0:155M at 0x6500000(mtd_ubi)'
set bootcmd 'ubi part mtd_ubi && ubi read 0x44000000 kernel && bootm'
env save
- Setup TFTP server serving initramfs image as 'recovery.bin', type in:
set ipaddr 192.168.1.1
set serverip 192.168.1.2
tftpboot recovery.bin && bootm
- Use sysupgrade to install squashfs image.
This port is based on work done by AmadeusGhost <amadeus at jmu.edu.cn>.
Signed-off-by: Rodrigo Balerdi <lanchon at gmail.com>
[add 5.15 changes for 0069-arm-boot-add-dts-files.patch]
Signed-off-by: Sungbo Eo <mans0n at gorani.run>
---
package/boot/uboot-envtools/files/ipq806x | 1 +
.../ipq806x/base-files/etc/board.d/02_network | 5 +
.../ipq806x/base-files/lib/upgrade/platform.sh | 1 +
.../arch/arm/boot/dts/qcom-ipq8065-tr4400-v2.dts | 425 +++++++++++++++++++++
target/linux/ipq806x/image/generic.mk | 13 +
.../patches-5.10/0069-arm-boot-add-dts-files.patch | 3 +-
.../patches-5.15/0069-arm-boot-add-dts-files.patch | 5 +-
7 files changed, 450 insertions(+), 3 deletions(-)
diff --git a/package/boot/uboot-envtools/files/ipq806x b/package/boot/uboot-envtools/files/ipq806x
index 7e1d71a7e9..a8285d1452 100644
--- a/package/boot/uboot-envtools/files/ipq806x
+++ b/package/boot/uboot-envtools/files/ipq806x
@@ -30,6 +30,7 @@ ubootenv_mtdinfo () {
}
case "$board" in
+arris,tr4400-v2|\
askey,rt4230w-rev6)
ubootenv_add_uci_config "/dev/mtd9" "0x0" "0x40000" "0x20000"
;;
diff --git a/target/linux/ipq806x/base-files/etc/board.d/02_network b/target/linux/ipq806x/base-files/etc/board.d/02_network
index 4cb691f32e..dc9c11e4ba 100644
--- a/target/linux/ipq806x/base-files/etc/board.d/02_network
+++ b/target/linux/ipq806x/base-files/etc/board.d/02_network
@@ -11,6 +11,11 @@ board_config_update
board=$(board_name)
case "$board" in
+arris,tr4400-v2)
+ ucidef_set_interfaces_lan_wan "eth1" "eth2"
+ ucidef_add_switch "switch0" \
+ "1:lan" "2:lan" "3:lan" "4:lan" "6u at eth1" "0u at eth0"
+ ;;
askey,rt4230w-rev6 |\
asrock,g10 |\
nec,wg2600hp)
diff --git a/target/linux/ipq806x/base-files/lib/upgrade/platform.sh b/target/linux/ipq806x/base-files/lib/upgrade/platform.sh
index 84ffcd8a15..f9e592f4bd 100644
--- a/target/linux/ipq806x/base-files/lib/upgrade/platform.sh
+++ b/target/linux/ipq806x/base-files/lib/upgrade/platform.sh
@@ -10,6 +10,7 @@ platform_check_image() {
platform_do_upgrade() {
case "$(board_name)" in
+ arris,tr4400-v2 |\
askey,rt4230w-rev6 |\
compex,wpq864|\
netgear,d7800 |\
diff --git a/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8065-tr4400-v2.dts b/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8065-tr4400-v2.dts
new file mode 100644
index 0000000000..871cc09502
--- /dev/null
+++ b/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8065-tr4400-v2.dts
@@ -0,0 +1,425 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+
+#include "qcom-ipq8065.dtsi"
+#include <dt-bindings/input/input.h>
+
+/ {
+ model = "Arris TR4400 v2";
+ compatible = "arris,tr4400-v2", "qcom,ipq8065", "qcom,ipq8064";
+
+ memory at 0 {
+ reg = <0x42000000 0x1e000000>;
+ device_type = "memory";
+ };
+
+ aliases {
+ led-boot = &led_status_blue;
+ led-failsafe = &led_status_red;
+ led-running = &led_status_blue;
+ led-upgrade = &led_status_red;
+ };
+
+ chosen {
+ bootargs = "rootfstype=squashfs noinitrd";
+ };
+
+ keys {
+ compatible = "gpio-keys";
+ pinctrl-0 = <&button_pins>;
+ pinctrl-names = "default";
+
+ reset {
+ label = "reset";
+ gpios = <&qcom_pinmux 6 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_RESTART>;
+ debounce-interval = <60>;
+ wakeup-source;
+ };
+
+ wps {
+ label = "wps";
+ gpios = <&qcom_pinmux 54 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_WPS_BUTTON>;
+ debounce-interval = <60>;
+ wakeup-source;
+ };
+ };
+
+ leds {
+ compatible = "gpio-leds";
+ pinctrl-0 = <&led_pins>;
+ pinctrl-names = "default";
+
+ led_status_red: status_red {
+ label = "red:status";
+ gpios = <&qcom_pinmux 7 GPIO_ACTIVE_HIGH>;
+ };
+
+ led_status_blue: status_blue {
+ label = "blue:status";
+ gpios = <&qcom_pinmux 8 GPIO_ACTIVE_HIGH>;
+ };
+ };
+};
+
+&qcom_pinmux {
+ button_pins: button_pins {
+ mux {
+ pins = "gpio6", "gpio54";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+ };
+
+ led_pins: led_pins {
+ mux {
+ pins = "gpio7", "gpio8";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+ };
+
+ rgmii2_pins: rgmii2_pins {
+ tx {
+ pins = "gpio27", "gpio28", "gpio29", "gpio30", "gpio31", "gpio32";
+ input-disable;
+ };
+ };
+
+ spi_pins: spi_pins {
+ cs {
+ pins = "gpio20";
+ drive-strength = <12>;
+ };
+ };
+};
+
+&gsbi5 {
+ qcom,mode = <GSBI_PROT_SPI>;
+ status = "okay";
+
+ spi at 1a280000 {
+ status = "okay";
+
+ pinctrl-0 = <&spi_pins>;
+ pinctrl-names = "default";
+
+ cs-gpios = <&qcom_pinmux 20 GPIO_ACTIVE_HIGH>;
+
+ flash at 0 {
+ compatible = "everspin,mr25h256";
+ spi-max-frequency = <40000000>;
+ reg = <0>;
+ };
+ };
+};
+
+&nand {
+ status = "okay";
+
+ pinctrl-0 = <&nand_pins>;
+ pinctrl-names = "default";
+
+ nand at 0 {
+ reg = <0>;
+ compatible = "qcom,nandcs";
+
+ nand-ecc-strength = <4>;
+ nand-bus-width = <8>;
+ nand-ecc-step-size = <512>;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition at 0 {
+ label = "0:SBL1";
+ reg = <0x0000000 0x0040000>;
+ read-only;
+ };
+ partition at 40000 {
+ label = "0:MIBIB";
+ reg = <0x0040000 0x0140000>;
+ read-only;
+ };
+ partition at 180000 {
+ label = "0:SBL2";
+ reg = <0x0180000 0x0140000>;
+ read-only;
+ };
+ partition at 2c0000 {
+ label = "0:SBL3";
+ reg = <0x02c0000 0x0280000>;
+ read-only;
+ };
+ partition at 540000 {
+ label = "0:DDRCONFIG";
+ reg = <0x0540000 0x0120000>;
+ read-only;
+ };
+ partition at 660000 {
+ label = "0:SSD";
+ reg = <0x0660000 0x0120000>;
+ read-only;
+ };
+ partition at 780000 {
+ label = "0:TZ";
+ reg = <0x0780000 0x0280000>;
+ read-only;
+ };
+ partition at a00000 {
+ label = "0:RPM";
+ reg = <0x0a00000 0x0280000>;
+ read-only;
+ };
+ partition at c80000 {
+ label = "0:APPSBL";
+ reg = <0x0c80000 0x0500000>;
+ read-only;
+ };
+ partition at 1180000 {
+ label = "0:APPSBLENV";
+ reg = <0x1180000 0x0080000>;
+ };
+ partition at 1200000 {
+ label = "0:ART";
+ reg = <0x1200000 0x0140000>;
+ read-only;
+
+ compatible = "nvmem-cells";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ precal_ART_1000: precal at 1000 {
+ reg = <0x1000 0x2f20>;
+ };
+ precal_ART_5000: precal at 5000 {
+ reg = <0x5000 0x2f20>;
+ };
+ };
+ stock_partition at 1340000 {
+ label = "stock_rootfs";
+ reg = <0x1340000 0x4000000>;
+ };
+ partition at 5340000 {
+ label = "0:BOOTCONFIG";
+ reg = <0x5340000 0x0060000>;
+ read-only;
+ };
+ partition at 53a0000 {
+ label = "0:SBL2_1";
+ reg = <0x53a0000 0x0140000>;
+ read-only;
+ };
+ partition at 54e0000 {
+ label = "0:SBL3_1";
+ reg = <0x54e0000 0x0280000>;
+ read-only;
+ };
+ partition at 5760000 {
+ label = "0:DDRCONFIG_1";
+ reg = <0x5760000 0x0120000>;
+ read-only;
+ };
+ partition at 5880000 {
+ label = "0:SSD_1";
+ reg = <0x5880000 0x0120000>;
+ read-only;
+ };
+ partition at 59a0000 {
+ label = "0:TZ_1";
+ reg = <0x59a0000 0x0280000>;
+ read-only;
+ };
+ partition at 5c20000 {
+ label = "0:RPM_1";
+ reg = <0x5c20000 0x0280000>;
+ read-only;
+ };
+ partition at 5ea0000 {
+ label = "0:BOOTCONFIG1";
+ reg = <0x5ea0000 0x0060000>;
+ read-only;
+ };
+ partition at 5f00000 {
+ label = "0:APPSBL_1";
+ reg = <0x5f00000 0x0500000>;
+ read-only;
+ };
+ stock_partition at 6400000 {
+ label = "stock_rootfs_1";
+ reg = <0x6400000 0x4000000>;
+ };
+ stock_partition at a400000 {
+ label = "stock_fw_env";
+ reg = <0xa400000 0x0100000>;
+ };
+ stock_partition at a500000 {
+ label = "stock_config";
+ reg = <0xa500000 0x0800000>;
+ };
+ stock_partition at ad00000 {
+ label = "stock_PKI";
+ reg = <0xad00000 0x0200000>;
+ };
+ stock_partition at af00000 {
+ label = "stock_scfgmgr";
+ reg = <0xaf00000 0x0100000>;
+ };
+
+ partition at 6400000 {
+ label = "fw_env";
+ reg = <0x6400000 0x0100000>;
+
+ compatible = "nvmem-cells";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ macaddr_fw_env_0: macaddr at 0 {
+ reg = <0x00 0x6>;
+ };
+ macaddr_fw_env_6: macaddr at 6 {
+ reg = <0x06 0x6>;
+ };
+ macaddr_fw_env_c: macaddr at c {
+ reg = <0x0c 0x6>;
+ };
+ macaddr_fw_env_12: macaddr at 12 {
+ reg = <0x12 0x6>;
+ };
+ macaddr_fw_env_18: macaddr at 18 {
+ reg = <0x18 0x6>;
+ };
+ };
+ partition at 6500000 {
+ label = "ubi";
+ reg = <0x6500000 0x9b00000>;
+ };
+ partition at 1340000 {
+ label = "extra";
+ reg = <0x1340000 0x4000000>;
+ };
+ };
+ };
+};
+
+&mdio0 {
+ status = "okay";
+
+ pinctrl-0 = <&mdio0_pins>;
+ pinctrl-names = "default";
+
+ ethernet-phy at 0 {
+ reg = <0x0>;
+ qca,ar8327-initvals = <
+ 0x00004 0x7600000 /* PAD0_MODE */
+ 0x00008 0x1000000 /* PAD5_MODE */
+ 0x0000c 0x80 /* PAD6_MODE */
+ 0x000e4 0xaa545 /* MAC_POWER_SEL */
+ 0x000e0 0xc74164de /* SGMII_CTRL */
+ 0x0007c 0x4e /* PORT0_STATUS */
+ 0x00094 0x4e /* PORT6_STATUS */
+ >;
+ };
+
+ phy7: ethernet-phy at 7 {
+ reg = <7>;
+ };
+};
+
+&gmac0 {
+ status = "okay";
+ phy-mode = "rgmii";
+ qcom,id = <0>;
+
+ nvmem-cells = <&macaddr_fw_env_18>;
+ nvmem-cell-names = "mac-address";
+
+ pinctrl-0 = <&rgmii2_pins>;
+ pinctrl-names = "default";
+
+ fixed-link {
+ speed = <1000>;
+ full-duplex;
+ };
+};
+
+&gmac1 {
+ status = "okay";
+ phy-mode = "sgmii";
+ qcom,id = <1>;
+
+ nvmem-cells = <&macaddr_fw_env_0>;
+ nvmem-cell-names = "mac-address";
+
+ fixed-link {
+ speed = <1000>;
+ full-duplex;
+ };
+};
+
+&gmac3 {
+ status = "okay";
+ phy-mode = "sgmii";
+ qcom,id = <3>;
+ phy-handle = <&phy7>;
+
+ nvmem-cells = <&macaddr_fw_env_6>;
+ nvmem-cell-names = "mac-address";
+};
+
+&adm_dma {
+ status = "okay";
+};
+
+&usb3_1 {
+ status = "okay";
+};
+
+&pcie0 {
+ status = "okay";
+ reset-gpio = <&qcom_pinmux 3 GPIO_ACTIVE_HIGH>;
+ pinctrl-0 = <&pcie0_pins>;
+ pinctrl-names = "default";
+
+ bridge at 0,0 {
+ reg = <0x00000000 0 0 0 0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges;
+
+ wifi0: wifi at 1,0 {
+ compatible = "pci168c,0046";
+ reg = <0x00010000 0 0 0 0>;
+
+ nvmem-cells = <&precal_ART_1000>, <&macaddr_fw_env_12>;
+ nvmem-cell-names = "pre-calibration", "mac-address";
+ };
+ };
+};
+
+&pcie1 {
+ status = "okay";
+ reset-gpio = <&qcom_pinmux 48 GPIO_ACTIVE_HIGH>;
+ pinctrl-0 = <&pcie1_pins>;
+ pinctrl-names = "default";
+ max-link-speed = <1>;
+
+ bridge at 0,0 {
+ reg = <0x00000000 0 0 0 0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges;
+
+ wifi1: wifi at 1,0 {
+ compatible = "pci168c,0040";
+ reg = <0x00010000 0 0 0 0>;
+
+ nvmem-cells = <&precal_ART_5000>, <&macaddr_fw_env_c>;
+ nvmem-cell-names = "pre-calibration", "mac-address";
+ };
+ };
+};
diff --git a/target/linux/ipq806x/image/generic.mk b/target/linux/ipq806x/image/generic.mk
index 819c73d338..469f2c654e 100644
--- a/target/linux/ipq806x/image/generic.mk
+++ b/target/linux/ipq806x/image/generic.mk
@@ -65,6 +65,19 @@ define Device/ZyXELImage
append-metadata
endef
+define Device/arris_tr4400-v2
+ $(call Device/LegacyImage)
+ DEVICE_VENDOR := Arris
+ DEVICE_MODEL := TR4400
+ DEVICE_VARIANT := v2
+ SOC := qcom-ipq8065
+ BLOCKSIZE := 128k
+ PAGESIZE := 2048
+ DEVICE_PACKAGES := ath10k-firmware-qca9984-ct ath10k-firmware-qca99x0-ct
+ KERNEL_IN_UBI := 1
+endef
+TARGET_DEVICES += arris_tr4400-v2
+
define Device/askey_rt4230w-rev6
$(call Device/LegacyImage)
DEVICE_VENDOR := Askey
diff --git a/target/linux/ipq806x/patches-5.10/0069-arm-boot-add-dts-files.patch b/target/linux/ipq806x/patches-5.10/0069-arm-boot-add-dts-files.patch
index 275b960c18..a7eacf311b 100644
--- a/target/linux/ipq806x/patches-5.10/0069-arm-boot-add-dts-files.patch
+++ b/target/linux/ipq806x/patches-5.10/0069-arm-boot-add-dts-files.patch
@@ -10,7 +10,7 @@ Signed-off-by: John Crispin <john at phrozen.org>
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
-@@ -908,8 +908,29 @@ dtb-$(CONFIG_ARCH_QCOM) += \
+@@ -908,8 +908,30 @@ dtb-$(CONFIG_ARCH_QCOM) += \
qcom-ipq4019-ap.dk04.1-c3.dtb \
qcom-ipq4019-ap.dk07.1-c1.dtb \
qcom-ipq4019-ap.dk07.1-c2.dtb \
@@ -33,6 +33,7 @@ Signed-off-by: John Crispin <john at phrozen.org>
+ qcom-ipq8065-nbg6817.dtb \
+ qcom-ipq8065-r7800.dtb \
+ qcom-ipq8065-rt4230w-rev6.dtb \
++ qcom-ipq8065-tr4400-v2.dtb \
+ qcom-ipq8065-xr500.dtb \
+ qcom-ipq8068-ecw5410.dtb \
+ qcom-ipq8068-mr42.dtb \
diff --git a/target/linux/ipq806x/patches-5.15/0069-arm-boot-add-dts-files.patch b/target/linux/ipq806x/patches-5.15/0069-arm-boot-add-dts-files.patch
index db12b32d94..05f39f6465 100644
--- a/target/linux/ipq806x/patches-5.15/0069-arm-boot-add-dts-files.patch
+++ b/target/linux/ipq806x/patches-5.15/0069-arm-boot-add-dts-files.patch
@@ -10,7 +10,7 @@ Signed-off-by: John Crispin <john at phrozen.org>
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
-@@ -956,8 +956,29 @@ dtb-$(CONFIG_ARCH_QCOM) += \
+@@ -956,8 +956,30 @@ dtb-$(CONFIG_ARCH_QCOM) += \
qcom-ipq4019-ap.dk04.1-c3.dtb \
qcom-ipq4019-ap.dk07.1-c1.dtb \
qcom-ipq4019-ap.dk07.1-c2.dtb \
@@ -32,8 +32,9 @@ Signed-off-by: John Crispin <john at phrozen.org>
+ qcom-ipq8064-wxr-2533dhp.dtb \
+ qcom-ipq8065-nbg6817.dtb \
+ qcom-ipq8065-r7800.dtb \
-+ qcom-ipq8065-xr500.dtb \
+ qcom-ipq8065-rt4230w-rev6.dtb \
++ qcom-ipq8065-tr4400-v2.dtb \
++ qcom-ipq8065-xr500.dtb \
+ qcom-ipq8068-ecw5410.dtb \
+ qcom-ipq8068-mr42.dtb \
+ qcom-ipq8068-mr52.dtb \
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