[openwrt/openwrt] sunxi: cortexa7: fix ethernet link detection on a20-olinuxino-lime2

[LEDE Commits]

ynezz pushed a commit to openwrt/openwrt.git, branch master:
https://git.openwrt.org/ffa1088f63267f817a3adf34c84b8e8089b1a938

commit ffa1088f63267f817a3adf34c84b8e8089b1a938
Author: Petr Štetiar <ynezz at true.cz>
AuthorDate: Tue Mar 8 10:41:24 2022 +0100

    sunxi: cortexa7: fix ethernet link detection on a20-olinuxino-lime2
    
    a20-olinuxino-lime2 is currently having hard time with link detection of
    certain 1000Mbit partners due to usage of generic PHY driver, probably
    due to following missing workaround introduced in upstream in commit
    3aed3e2a143c ("net: phy: micrel: add Asym Pause workaround"):
    
     The Micrel KSZ9031 PHY may fail to establish a link when the Asymmetric
     Pause capability is set. This issue is described in a Silicon Errata
     (DS80000691D or DS80000692D), which advises to always disable the
     capability. This patch implements the workaround by defining a KSZ9031
     specific get_feature callback to force the Asymmetric Pause capability
     bit to be cleared.
    
     This fixes issues where the link would not come up at boot time, or when
     the Asym Pause bit was set later on.
    
    As a20-olinuxino-lime2 has Micrel KSZ9031RNXCC-TR Gigabit PHY since
    revision H, so we need to use Micrel PHY driver on those devices.
    
    Signed-off-by: Petr Štetiar <ynezz at true.cz>
---
 target/linux/sunxi/cortexa7/config-5.10 | 1 +
 1 file changed, 1 insertion(+)

diff --git a/target/linux/sunxi/cortexa7/config-5.10 b/target/linux/sunxi/cortexa7/config-5.10
index e77f4d872f..c3ceb99c3d 100644
--- a/target/linux/sunxi/cortexa7/config-5.10
+++ b/target/linux/sunxi/cortexa7/config-5.10
@@ -5,6 +5,7 @@ CONFIG_GRO_CELLS=y
 # CONFIG_MACH_SUN4I is not set
 # CONFIG_MACH_SUN5I is not set
 CONFIG_MDIO_BUS_MUX=y
+CONFIG_MICREL_PHY=y
 CONFIG_MUSB_PIO_ONLY=y
 CONFIG_NET_DEVLINK=y
 CONFIG_NET_DSA=y