[openwrt/openwrt] ltq-deu: set correct control register for AES

[LEDE Commits]

hauke pushed a commit to openwrt/openwrt.git, branch master:
https://git.openwrt.org/c8967d6d12b25cf50b7e060485004c1332a40367

commit c8967d6d12b25cf50b7e060485004c1332a40367
Author: Daniel Kestrel <kestrel1974 at t-online.de>
AuthorDate: Mon May 31 14:13:42 2021 +0200

    ltq-deu: set correct control register for AES
    
    Some devices initialize AES during boot and AES works out of the box
    and the correct endianess is set.
    NDC means (No Danube Compatibility Mode) and the endianess setting has
    no effect if its set to 0.
    NDC 0: OFF ENDI bit cannot be written as in Danube
    To make it work for other devices, the NDC control register needs to
    be set to 1.
    
    Signed-off-by: Daniel Kestrel <kestrel1974 at t-online.de>
---
 package/kernel/lantiq/ltq-deu/src/ifxmips_deu_vr9.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/package/kernel/lantiq/ltq-deu/src/ifxmips_deu_vr9.c b/package/kernel/lantiq/ltq-deu/src/ifxmips_deu_vr9.c
index aaa7bce237..8063672613 100644
--- a/package/kernel/lantiq/ltq-deu/src/ifxmips_deu_vr9.c
+++ b/package/kernel/lantiq/ltq-deu/src/ifxmips_deu_vr9.c
@@ -107,7 +107,7 @@ void aes_chip_init (void)
 
     // start crypto engine with write to ILR
     aes->controlr.SM = 1;
-    aes->controlr.NDC = 0;
+    aes->controlr.NDC = 1;
     asm("sync");
     aes->controlr.ENDI = 1;
     asm("sync");