[openwrt/openwrt] mediatek: enable sel_clk for spi-mt65xx

[LEDE Commits]

981213 pushed a commit to openwrt/openwrt.git, branch master:
https://git.openwrt.org/335c1e7cfdfd477a1106ca05c96ff8949ecd953f

commit 335c1e7cfdfd477a1106ca05c96ff8949ecd953f
Author: Furong Xu <xfr at outlook.com>
AuthorDate: Fri Dec 16 21:13:37 2022 +0800

    mediatek: enable sel_clk for spi-mt65xx
    
    Without explicitly enabling sel_clk, clk_disable_unused() will disable
    it when boot is done, causing CPU hang on SPI1 register access on MT7986.
    Explicitly enable sel_clk to make SPI1 functional.
    
    Signed-off-by: Furong Xu <xfr at outlook.com>
    Signed-off-by: Chuanhong Guo <gch981213 at gmail.com>
---
 .../930-spi-mt65xx-enable-sel-clk.patch            | 29 ++++++++++++++++++++++
 1 file changed, 29 insertions(+)

diff --git a/target/linux/mediatek/patches-5.15/930-spi-mt65xx-enable-sel-clk.patch b/target/linux/mediatek/patches-5.15/930-spi-mt65xx-enable-sel-clk.patch
new file mode 100644
index 0000000000..904f2ef3a2
--- /dev/null
+++ b/target/linux/mediatek/patches-5.15/930-spi-mt65xx-enable-sel-clk.patch
@@ -0,0 +1,29 @@
+--- a/drivers/spi/spi-mt65xx.c
++++ b/drivers/spi/spi-mt65xx.c
+@@ -1223,10 +1223,16 @@ static int mtk_spi_probe(struct platform
+ 		goto err_disable_spi_hclk;
+ 	}
+ 
++	ret = clk_prepare_enable(mdata->sel_clk);
++	if (ret < 0) {
++		dev_err(&pdev->dev, "failed to enable sel_clk (%d)\n", ret);
++		goto err_disable_spi_clk;
++	}
++
+ 	ret = clk_set_parent(mdata->sel_clk, mdata->parent_clk);
+ 	if (ret < 0) {
+ 		dev_err(&pdev->dev, "failed to clk_set_parent (%d)\n", ret);
+-		goto err_disable_spi_clk;
++		goto err_disable_spi_sel_clk;
+ 	}
+ 
+ 	mdata->spi_clk_hz = clk_get_rate(mdata->spi_clk);
+@@ -1277,6 +1283,8 @@ static int mtk_spi_probe(struct platform
+ 
+ err_disable_runtime_pm:
+ 	pm_runtime_disable(&pdev->dev);
++err_disable_spi_sel_clk:
++	clk_disable_unprepare(mdata->sel_clk);
+ err_disable_spi_clk:
+ 	clk_disable_unprepare(mdata->spi_clk);
+ err_disable_spi_hclk: