[openwrt/openwrt] realtek: fix PLL register inconsistencies

[LEDE Commits]

hauke pushed a commit to openwrt/openwrt.git, branch master:
https://git.openwrt.org/6ff21c436dd93646f924efdd73c4b3fc59501ad3

commit 6ff21c436dd93646f924efdd73c4b3fc59501ad3
Author: Markus Stockhausen <markus.stockhausen at gmx.de>
AuthorDate: Tue Aug 30 16:44:02 2022 +0200

    realtek: fix PLL register inconsistencies
    
    Some devices have wrong/empty values in the PLL registers. Work
    around that by reporting the default values.
    
    Signed-off-by: Markus Stockhausen <markus.stockhausen at gmx.de>
---
 target/linux/realtek/files-5.10/drivers/clk/realtek/clk-rtl83xx.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/target/linux/realtek/files-5.10/drivers/clk/realtek/clk-rtl83xx.c b/target/linux/realtek/files-5.10/drivers/clk/realtek/clk-rtl83xx.c
index c3eb270f6e..9b8183fbeb 100644
--- a/target/linux/realtek/files-5.10/drivers/clk/realtek/clk-rtl83xx.c
+++ b/target/linux/realtek/files-5.10/drivers/clk/realtek/clk-rtl83xx.c
@@ -366,6 +366,9 @@ static unsigned long rtcl_recalc_rate(struct clk_hw *hw, unsigned long parent_ra
 
 	switch (rtcl_ccu->soc) {
 	case SOC_RTL838X:
+		if ((ctrl0 == 0) && (ctrl1 == 0) && (clk->idx == CLK_LXB))
+			return 200000000;
+
 		cmu_divn2_selb = RTL838X_PLL_CTRL1_CMU_DIVN2_SELB(ctrl1);
 		cmu_divn3_sel = rtcl_divn3[RTL838X_PLL_CTRL1_CMU_DIVN3_SEL(ctrl1)];
 		break;