[openwrt/openwrt] mediatek: mt7622: provide power on mPCIe in SATA mode

LEDE Commits lede-commits at lists.infradead.org
Thu Sep 30 14:56:21 PDT 2021


dangole pushed a commit to openwrt/openwrt.git, branch master:
https://git.openwrt.org/0d9aae10e4f8821bfe583eb95e1c53aeba34bedb

commit 0d9aae10e4f8821bfe583eb95e1c53aeba34bedb
Author: Daniel Golle <daniel at makrotopia.org>
AuthorDate: Thu Sep 16 21:04:14 2021 +0100

    mediatek: mt7622: provide power on mPCIe in SATA mode
    
    User reported that R64 doesn't provide power to the mPCIe slot in case
    the PCIe port is disabled as it is when selecting the SATA
    configuration. As users may still want to use USB-connected mPCIe
    modules in CN8 slot.
    
    Signed-off-by: Daniel Golle <daniel at makrotopia.org>
---
 ...900-dts-mt7622-bpi-r64-aliases-for-dtoverlay.patch | 19 ++-----------------
 1 file changed, 2 insertions(+), 17 deletions(-)

diff --git a/target/linux/mediatek/patches-5.10/900-dts-mt7622-bpi-r64-aliases-for-dtoverlay.patch b/target/linux/mediatek/patches-5.10/900-dts-mt7622-bpi-r64-aliases-for-dtoverlay.patch
index 7e539be30d..0701182219 100644
--- a/target/linux/mediatek/patches-5.10/900-dts-mt7622-bpi-r64-aliases-for-dtoverlay.patch
+++ b/target/linux/mediatek/patches-5.10/900-dts-mt7622-bpi-r64-aliases-for-dtoverlay.patch
@@ -1,14 +1,6 @@
 --- a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
 +++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
-@@ -297,14 +297,14 @@
- &pcie1 {
- 	pinctrl-names = "default";
- 	pinctrl-0 = <&pcie1_pins>;
--	status = "okay";
-+	status = "disabled";
- };
- 
- &pio {
+@@ -304,7 +304,7 @@
  	/* Attention: GPIO 90 is used to switch between PCIe at 1,0 and
  	 * SATA functions. i.e. output-high: PCIe, output-low: SATA
  	 */
@@ -53,7 +45,7 @@
 +};
 --- /dev/null
 +++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64-pcie1.dts
-@@ -0,0 +1,24 @@
+@@ -0,0 +1,17 @@
 +/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */
 +
 +#include <dt-bindings/gpio/gpio.h>
@@ -70,11 +62,4 @@
 +			gpios = <90 GPIO_ACTIVE_HIGH>;
 +		};
 +	};
-+
-+	fragment at 1 {
-+		target = <&pcie1>;
-+		__overlay__ {
-+			status = "okay";
-+		};
-+	};
 +};



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