[openwrt/openwrt] mvebu: backport CN9130 dts necessary files changes to 5.4
LEDE Commits
lede-commits at lists.infradead.org
Thu Sep 9 14:59:00 PDT 2021
hauke pushed a commit to openwrt/openwrt.git, branch master:
https://git.openwrt.org/c98ddf0f019986bbb4c868bfcaf97e0d1f4ee2dc
commit c98ddf0f019986bbb4c868bfcaf97e0d1f4ee2dc
Author: Ian Chang <ianchang at ieiworld.com>
AuthorDate: Thu Sep 2 17:47:01 2021 +0800
mvebu: backport CN9130 dts necessary files changes to 5.4
1. Add support for Marvell CN9130 SoC
2. Add support for CP115,and create an armada-cp11x.dtsi file which will be used to instantiate both CP110 and CP115
3. Add support for AP807/AP807-quad,AP807 is a major component of CN9130 SoC series
4. Drop PCIe I/O ranges from CP11x file and externalize PCIe macros from CP11x file
Signed-off-by: Ian Chang <ianchang at ieiworld.com>
---
...arvell-Add-support-for-Marvell-CN9130-SoC.patch | 55 +
...5-arm64-dts-marvell-Add-support-for-CP115.patch | 30 +
...marvell-Prepare-the-introduction-of-CP115.patch | 1318 ++++++++++++++++++++
...-marvell-Add-support-for-AP807-AP807-quad.patch | 102 ++
...-marvell-Add-AP807-quad-cache-description.patch | 87 ++
...arvell-Drop-PCIe-I-O-ranges-from-CP11x-fi.patch | 135 ++
...arvell-Externalize-PCIe-macros-from-CP11x.patch | 129 ++
...-marvell-Enumerate-the-first-AP806-syscon.patch | 25 +
...arvell-Prepare-the-introduction-of-AP807-.patch | 937 ++++++++++++++
...arvell-Move-clocks-to-AP806-specific-file.patch | 65 +
10 files changed, 2883 insertions(+)
diff --git a/target/linux/mvebu/patches-5.4/000-v5.5-arm64-dts-marvell-Add-support-for-Marvell-CN9130-SoC.patch b/target/linux/mvebu/patches-5.4/000-v5.5-arm64-dts-marvell-Add-support-for-Marvell-CN9130-SoC.patch
new file mode 100644
index 0000000000..0f4d14188d
--- /dev/null
+++ b/target/linux/mvebu/patches-5.4/000-v5.5-arm64-dts-marvell-Add-support-for-Marvell-CN9130-SoC.patch
@@ -0,0 +1,55 @@
+From 6b8970bd8d7a17a648e31f3996d9b21336b4a2cf Mon Sep 17 00:00:00 2001
+From: Miquel Raynal <miquel.raynal at bootlin.com>
+Date: Fri, 4 Oct 2019 16:27:35 +0200
+Subject: [PATCH] arm64: dts: marvell: Add support for Marvell CN9130 SoC
+ support
+
+A CN9130 SoC has one AP807 and one internal CP115.
+
+Signed-off-by: Miquel Raynal <miquel.raynal at bootlin.com>
+Signed-off-by: Gregory CLEMENT <gregory.clement at bootlin.com>
+---
+ arch/arm64/boot/dts/marvell/cn9130.dtsi | 37 +++++++++++++++++++++++++
+ 1 file changed, 37 insertions(+)
+ create mode 100644 arch/arm64/boot/dts/marvell/cn9130.dtsi
+
+--- /dev/null
++++ b/arch/arm64/boot/dts/marvell/cn9130.dtsi
+@@ -0,0 +1,37 @@
++// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
++/*
++ * Copyright (C) 2019 Marvell International Ltd.
++ *
++ * Device tree for the CN9130 SoC.
++ */
++
++#include "armada-ap807-quad.dtsi"
++
++/ {
++ model = "Marvell Armada CN9130 SoC";
++ compatible = "marvell,cn9130", "marvell,armada-ap807-quad",
++ "marvell,armada-ap807";
++};
++
++/*
++ * Instantiate the internal CP115
++ */
++
++#define CP11X_NAME cp0
++#define CP11X_BASE f2000000
++#define CP11X_PCIEx_MEM_BASE(iface) ((iface == 0) ? 0xc0000000 : \
++ 0xe0000000 + ((iface - 1) * 0x1000000))
++#define CP11X_PCIEx_MEM_SIZE(iface) ((iface == 0) ? 0x1ff00000 : 0xf00000)
++#define CP11X_PCIE0_BASE f2600000
++#define CP11X_PCIE1_BASE f2620000
++#define CP11X_PCIE2_BASE f2640000
++
++#include "armada-cp115.dtsi"
++
++#undef CP11X_NAME
++#undef CP11X_BASE
++#undef CP11X_PCIEx_MEM_BASE
++#undef CP11X_PCIEx_MEM_SIZE
++#undef CP11X_PCIE0_BASE
++#undef CP11X_PCIE1_BASE
++#undef CP11X_PCIE2_BASE
diff --git a/target/linux/mvebu/patches-5.4/001-v5.5-arm64-dts-marvell-Add-support-for-CP115.patch b/target/linux/mvebu/patches-5.4/001-v5.5-arm64-dts-marvell-Add-support-for-CP115.patch
new file mode 100644
index 0000000000..1ef87ed227
--- /dev/null
+++ b/target/linux/mvebu/patches-5.4/001-v5.5-arm64-dts-marvell-Add-support-for-CP115.patch
@@ -0,0 +1,30 @@
+From 96bb4b31aa660e39fca2bb464b9a9f399bd5b71c Mon Sep 17 00:00:00 2001
+From: Miquel Raynal <miquel.raynal at bootlin.com>
+Date: Fri, 4 Oct 2019 16:27:32 +0200
+Subject: [PATCH] arm64: dts: marvell: Add support for CP115
+
+Create a DTSI file based on the CP11x one. Differences will be
+described in the near future.
+
+Signed-off-by: Miquel Raynal <miquel.raynal at bootlin.com>
+Signed-off-by: Gregory CLEMENT <gregory.clement at bootlin.com>
+---
+ arch/arm64/boot/dts/marvell/armada-cp115.dtsi | 12 ++++++++++++
+ 1 file changed, 12 insertions(+)
+ create mode 100644 arch/arm64/boot/dts/marvell/armada-cp115.dtsi
+
+--- /dev/null
++++ b/arch/arm64/boot/dts/marvell/armada-cp115.dtsi
+@@ -0,0 +1,12 @@
++// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
++/*
++ * Copyright (C) 2019 Marvell Technology Group Ltd.
++ *
++ * Device Tree file for Marvell Armada CP115.
++ */
++
++#define CP11X_TYPE cp115
++
++#include "armada-cp11x.dtsi"
++
++#undef CP11X_TYPE
diff --git a/target/linux/mvebu/patches-5.4/002-v5.5-arm64-dts-marvell-Prepare-the-introduction-of-CP115.patch b/target/linux/mvebu/patches-5.4/002-v5.5-arm64-dts-marvell-Prepare-the-introduction-of-CP115.patch
new file mode 100644
index 0000000000..5e41f548d6
--- /dev/null
+++ b/target/linux/mvebu/patches-5.4/002-v5.5-arm64-dts-marvell-Prepare-the-introduction-of-CP115.patch
@@ -0,0 +1,1318 @@
+From 47cf40af64c35a69ef6a193c47768ad1bda29db2 Mon Sep 17 00:00:00 2001
+From: Miquel Raynal <miquel.raynal at bootlin.com>
+Date: Fri, 4 Oct 2019 16:27:29 +0200
+Subject: [PATCH] arm64: dts: marvell: Prepare the introduction of CP115
+
+CP110 and CP115 are almost the same in terms of features and have a
+very limited set of differences. Let's create an armada-cp11x.dtsi
+file which will be used to instantiate both CP110 and CP115
+nodes.
+
+The only changes between the two armada-cp11{0,x}.dtsi files are the
+following naming in macros: s/CP110/CP11X/.
+
+Signed-off-by: Miquel Raynal <miquel.raynal at bootlin.com>
+Signed-off-by: Gregory CLEMENT <gregory.clement at bootlin.com>
+---
+ arch/arm64/boot/dts/marvell/armada-70x0.dtsi | 28 +-
+ arch/arm64/boot/dts/marvell/armada-80x0.dtsi | 56 +-
+ .../arm64/boot/dts/marvell/armada-common.dtsi | 4 +-
+ arch/arm64/boot/dts/marvell/armada-cp110.dtsi | 575 +----------------
+ arch/arm64/boot/dts/marvell/armada-cp11x.dtsi | 579 ++++++++++++++++++
+ 5 files changed, 627 insertions(+), 615 deletions(-)
+ create mode 100644 arch/arm64/boot/dts/marvell/armada-cp11x.dtsi
+
+--- a/arch/arm64/boot/dts/marvell/armada-70x0.dtsi
++++ b/arch/arm64/boot/dts/marvell/armada-70x0.dtsi
+@@ -17,23 +17,23 @@
+ /*
+ * Instantiate the CP110
+ */
+-#define CP110_NAME cp0
+-#define CP110_BASE f2000000
+-#define CP110_PCIE_IO_BASE 0xf9000000
+-#define CP110_PCIE_MEM_BASE 0xf6000000
+-#define CP110_PCIE0_BASE f2600000
+-#define CP110_PCIE1_BASE f2620000
+-#define CP110_PCIE2_BASE f2640000
++#define CP11X_NAME cp0
++#define CP11X_BASE f2000000
++#define CP11X_PCIE_IO_BASE 0xf9000000
++#define CP11X_PCIE_MEM_BASE 0xf6000000
++#define CP11X_PCIE0_BASE f2600000
++#define CP11X_PCIE1_BASE f2620000
++#define CP11X_PCIE2_BASE f2640000
+
+ #include "armada-cp110.dtsi"
+
+-#undef CP110_NAME
+-#undef CP110_BASE
+-#undef CP110_PCIE_IO_BASE
+-#undef CP110_PCIE_MEM_BASE
+-#undef CP110_PCIE0_BASE
+-#undef CP110_PCIE1_BASE
+-#undef CP110_PCIE2_BASE
++#undef CP11X_NAME
++#undef CP11X_BASE
++#undef CP11X_PCIE_IO_BASE
++#undef CP11X_PCIE_MEM_BASE
++#undef CP11X_PCIE0_BASE
++#undef CP11X_PCIE1_BASE
++#undef CP11X_PCIE2_BASE
+
+ &cp0_gpio1 {
+ status = "okay";
+--- a/arch/arm64/boot/dts/marvell/armada-80x0.dtsi
++++ b/arch/arm64/boot/dts/marvell/armada-80x0.dtsi
+@@ -19,44 +19,44 @@
+ /*
+ * Instantiate the master CP110
+ */
+-#define CP110_NAME cp0
+-#define CP110_BASE f2000000
+-#define CP110_PCIE_IO_BASE 0xf9000000
+-#define CP110_PCIE_MEM_BASE 0xf6000000
+-#define CP110_PCIE0_BASE f2600000
+-#define CP110_PCIE1_BASE f2620000
+-#define CP110_PCIE2_BASE f2640000
++#define CP11X_NAME cp0
++#define CP11X_BASE f2000000
++#define CP11X_PCIE_IO_BASE 0xf9000000
++#define CP11X_PCIE_MEM_BASE 0xf6000000
++#define CP11X_PCIE0_BASE f2600000
++#define CP11X_PCIE1_BASE f2620000
++#define CP11X_PCIE2_BASE f2640000
+
+ #include "armada-cp110.dtsi"
+
+-#undef CP110_NAME
+-#undef CP110_BASE
+-#undef CP110_PCIE_IO_BASE
+-#undef CP110_PCIE_MEM_BASE
+-#undef CP110_PCIE0_BASE
+-#undef CP110_PCIE1_BASE
+-#undef CP110_PCIE2_BASE
++#undef CP11X_NAME
++#undef CP11X_BASE
++#undef CP11X_PCIE_IO_BASE
++#undef CP11X_PCIE_MEM_BASE
++#undef CP11X_PCIE0_BASE
++#undef CP11X_PCIE1_BASE
++#undef CP11X_PCIE2_BASE
+
+ /*
+ * Instantiate the slave CP110
+ */
+-#define CP110_NAME cp1
+-#define CP110_BASE f4000000
+-#define CP110_PCIE_IO_BASE 0xfd000000
+-#define CP110_PCIE_MEM_BASE 0xfa000000
+-#define CP110_PCIE0_BASE f4600000
+-#define CP110_PCIE1_BASE f4620000
+-#define CP110_PCIE2_BASE f4640000
++#define CP11X_NAME cp1
++#define CP11X_BASE f4000000
++#define CP11X_PCIE_IO_BASE 0xfd000000
++#define CP11X_PCIE_MEM_BASE 0xfa000000
++#define CP11X_PCIE0_BASE f4600000
++#define CP11X_PCIE1_BASE f4620000
++#define CP11X_PCIE2_BASE f4640000
+
+ #include "armada-cp110.dtsi"
+
+-#undef CP110_NAME
+-#undef CP110_BASE
+-#undef CP110_PCIE_IO_BASE
+-#undef CP110_PCIE_MEM_BASE
+-#undef CP110_PCIE0_BASE
+-#undef CP110_PCIE1_BASE
+-#undef CP110_PCIE2_BASE
++#undef CP11X_NAME
++#undef CP11X_BASE
++#undef CP11X_PCIE_IO_BASE
++#undef CP11X_PCIE_MEM_BASE
++#undef CP11X_PCIE0_BASE
++#undef CP11X_PCIE1_BASE
++#undef CP11X_PCIE2_BASE
+
+ /* The 80x0 has two CP blocks, but uses only one block from each. */
+ &cp1_gpio1 {
+--- a/arch/arm64/boot/dts/marvell/armada-common.dtsi
++++ b/arch/arm64/boot/dts/marvell/armada-common.dtsi
+@@ -6,6 +6,6 @@
+ /* Common definitions used by Armada 7K/8K DTs */
+ #define PASTER(x, y) x ## y
+ #define EVALUATOR(x, y) PASTER(x, y)
+-#define CP110_LABEL(name) EVALUATOR(CP110_NAME, EVALUATOR(_, name))
+-#define CP110_NODE_NAME(name) EVALUATOR(CP110_NAME, EVALUATOR(-, name))
++#define CP11X_LABEL(name) EVALUATOR(CP11X_NAME, EVALUATOR(_, name))
++#define CP11X_NODE_NAME(name) EVALUATOR(CP11X_NAME, EVALUATOR(-, name))
+ #define ADDRESSIFY(addr) EVALUATOR(0x, addr)
+--- a/arch/arm64/boot/dts/marvell/armada-cp110.dtsi
++++ b/arch/arm64/boot/dts/marvell/armada-cp110.dtsi
+@@ -1,579 +1,12 @@
+ // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+ /*
+- * Copyright (C) 2016 Marvell Technology Group Ltd.
++ * Copyright (C) 2019 Marvell Technology Group Ltd.
+ *
+ * Device Tree file for Marvell Armada CP110.
+ */
+
+-#include <dt-bindings/interrupt-controller/mvebu-icu.h>
+-#include <dt-bindings/thermal/thermal.h>
++#define CP11X_TYPE cp110
+
+-#include "armada-common.dtsi"
++#include "armada-cp11x.dtsi"
+
+-#define CP110_PCIEx_IO_BASE(iface) (CP110_PCIE_IO_BASE + (iface * 0x10000))
+-#define CP110_PCIEx_MEM_BASE(iface) (CP110_PCIE_MEM_BASE + (iface * 0x1000000))
+-#define CP110_PCIEx_CONF_BASE(iface) (CP110_PCIEx_MEM_BASE(iface) + 0xf00000)
+-
+-/ {
+- /*
+- * The contents of the node are defined below, in order to
+- * save one indentation level
+- */
+- CP110_NAME: CP110_NAME { };
+-
+- /*
+- * CPs only have one sensor in the thermal IC.
+- *
+- * The cooling maps are empty as there are no cooling devices.
+- */
+- thermal-zones {
+- CP110_LABEL(thermal_ic): CP110_NODE_NAME(thermal-ic) {
+- polling-delay-passive = <0>; /* Interrupt driven */
+- polling-delay = <0>; /* Interrupt driven */
+-
+- thermal-sensors = <&CP110_LABEL(thermal) 0>;
+-
+- trips {
+- CP110_LABEL(crit): crit {
+- temperature = <100000>; /* mC degrees */
+- hysteresis = <2000>; /* mC degrees */
+- type = "critical";
+- };
+- };
+-
+- cooling-maps { };
+- };
+- };
+-};
+-
+-&CP110_NAME {
+- #address-cells = <2>;
+- #size-cells = <2>;
+- compatible = "simple-bus";
+- interrupt-parent = <&CP110_LABEL(icu_nsr)>;
+- ranges;
+-
+- config-space at CP110_BASE {
+- #address-cells = <1>;
+- #size-cells = <1>;
+- compatible = "simple-bus";
+- ranges = <0x0 0x0 ADDRESSIFY(CP110_BASE) 0x2000000>;
+-
+- CP110_LABEL(ethernet): ethernet at 0 {
+- compatible = "marvell,armada-7k-pp22";
+- reg = <0x0 0x100000>, <0x129000 0xb000>;
+- clocks = <&CP110_LABEL(clk) 1 3>, <&CP110_LABEL(clk) 1 9>,
+- <&CP110_LABEL(clk) 1 5>, <&CP110_LABEL(clk) 1 6>,
+- <&CP110_LABEL(clk) 1 18>;
+- clock-names = "pp_clk", "gop_clk",
+- "mg_clk", "mg_core_clk", "axi_clk";
+- marvell,system-controller = <&CP110_LABEL(syscon0)>;
+- status = "disabled";
+- dma-coherent;
+-
+- CP110_LABEL(eth0): eth0 {
+- interrupts = <39 IRQ_TYPE_LEVEL_HIGH>,
+- <43 IRQ_TYPE_LEVEL_HIGH>,
+- <47 IRQ_TYPE_LEVEL_HIGH>,
+- <51 IRQ_TYPE_LEVEL_HIGH>,
+- <55 IRQ_TYPE_LEVEL_HIGH>,
+- <59 IRQ_TYPE_LEVEL_HIGH>,
+- <63 IRQ_TYPE_LEVEL_HIGH>,
+- <67 IRQ_TYPE_LEVEL_HIGH>,
+- <71 IRQ_TYPE_LEVEL_HIGH>,
+- <129 IRQ_TYPE_LEVEL_HIGH>;
+- interrupt-names = "hif0", "hif1", "hif2",
+- "hif3", "hif4", "hif5", "hif6", "hif7",
+- "hif8", "link";
+- port-id = <0>;
+- gop-port-id = <0>;
+- status = "disabled";
+- };
+-
+- CP110_LABEL(eth1): eth1 {
+- interrupts = <40 IRQ_TYPE_LEVEL_HIGH>,
+- <44 IRQ_TYPE_LEVEL_HIGH>,
+- <48 IRQ_TYPE_LEVEL_HIGH>,
+- <52 IRQ_TYPE_LEVEL_HIGH>,
+- <56 IRQ_TYPE_LEVEL_HIGH>,
+- <60 IRQ_TYPE_LEVEL_HIGH>,
+- <64 IRQ_TYPE_LEVEL_HIGH>,
+- <68 IRQ_TYPE_LEVEL_HIGH>,
+- <72 IRQ_TYPE_LEVEL_HIGH>,
+- <128 IRQ_TYPE_LEVEL_HIGH>;
+- interrupt-names = "hif0", "hif1", "hif2",
+- "hif3", "hif4", "hif5", "hif6", "hif7",
+- "hif8", "link";
+- port-id = <1>;
+- gop-port-id = <2>;
+- status = "disabled";
+- };
+-
+- CP110_LABEL(eth2): eth2 {
+- interrupts = <41 IRQ_TYPE_LEVEL_HIGH>,
+- <45 IRQ_TYPE_LEVEL_HIGH>,
+- <49 IRQ_TYPE_LEVEL_HIGH>,
+- <53 IRQ_TYPE_LEVEL_HIGH>,
+- <57 IRQ_TYPE_LEVEL_HIGH>,
+- <61 IRQ_TYPE_LEVEL_HIGH>,
+- <65 IRQ_TYPE_LEVEL_HIGH>,
+- <69 IRQ_TYPE_LEVEL_HIGH>,
+- <73 IRQ_TYPE_LEVEL_HIGH>,
+- <127 IRQ_TYPE_LEVEL_HIGH>;
+- interrupt-names = "hif0", "hif1", "hif2",
+- "hif3", "hif4", "hif5", "hif6", "hif7",
+- "hif8", "link";
+- port-id = <2>;
+- gop-port-id = <3>;
+- status = "disabled";
+- };
+- };
+-
+- CP110_LABEL(comphy): phy at 120000 {
+- compatible = "marvell,comphy-cp110";
+- reg = <0x120000 0x6000>;
+- marvell,system-controller = <&CP110_LABEL(syscon0)>;
+- clocks = <&CP110_LABEL(clk) 1 5>, <&CP110_LABEL(clk) 1 6>,
+- <&CP110_LABEL(clk) 1 18>;
+- clock-names = "mg_clk", "mg_core_clk", "axi_clk";
+- #address-cells = <1>;
+- #size-cells = <0>;
+-
+- CP110_LABEL(comphy0): phy at 0 {
+- reg = <0>;
+- #phy-cells = <1>;
+- };
+-
+- CP110_LABEL(comphy1): phy at 1 {
+- reg = <1>;
+- #phy-cells = <1>;
+- };
+-
+- CP110_LABEL(comphy2): phy at 2 {
+- reg = <2>;
+- #phy-cells = <1>;
+- };
+-
+- CP110_LABEL(comphy3): phy at 3 {
+- reg = <3>;
+- #phy-cells = <1>;
+- };
+-
+- CP110_LABEL(comphy4): phy at 4 {
+- reg = <4>;
+- #phy-cells = <1>;
+- };
+-
+- CP110_LABEL(comphy5): phy at 5 {
+- reg = <5>;
+- #phy-cells = <1>;
+- };
+- };
+-
+- CP110_LABEL(mdio): mdio at 12a200 {
+- #address-cells = <1>;
+- #size-cells = <0>;
+- compatible = "marvell,orion-mdio";
+- reg = <0x12a200 0x10>;
+- clocks = <&CP110_LABEL(clk) 1 9>, <&CP110_LABEL(clk) 1 5>,
+- <&CP110_LABEL(clk) 1 6>, <&CP110_LABEL(clk) 1 18>;
+- status = "disabled";
+- };
+-
+- CP110_LABEL(xmdio): mdio at 12a600 {
+- #address-cells = <1>;
+- #size-cells = <0>;
+- compatible = "marvell,xmdio";
+- reg = <0x12a600 0x10>;
+- clocks = <&CP110_LABEL(clk) 1 5>,
+- <&CP110_LABEL(clk) 1 6>, <&CP110_LABEL(clk) 1 18>;
+- status = "disabled";
+- };
+-
+- CP110_LABEL(icu): interrupt-controller at 1e0000 {
+- compatible = "marvell,cp110-icu";
+- reg = <0x1e0000 0x440>;
+- #address-cells = <1>;
+- #size-cells = <1>;
+-
+- CP110_LABEL(icu_nsr): interrupt-controller at 10 {
+- compatible = "marvell,cp110-icu-nsr";
+- reg = <0x10 0x20>;
+- #interrupt-cells = <2>;
+- interrupt-controller;
+- msi-parent = <&gicp>;
+- };
+-
+- CP110_LABEL(icu_sei): interrupt-controller at 50 {
+- compatible = "marvell,cp110-icu-sei";
+- reg = <0x50 0x10>;
+- #interrupt-cells = <2>;
+- interrupt-controller;
+- msi-parent = <&sei>;
+- };
+- };
+-
+- CP110_LABEL(rtc): rtc at 284000 {
+- compatible = "marvell,armada-8k-rtc";
+- reg = <0x284000 0x20>, <0x284080 0x24>;
+- reg-names = "rtc", "rtc-soc";
+- interrupts = <77 IRQ_TYPE_LEVEL_HIGH>;
+- };
+-
+- CP110_LABEL(syscon0): system-controller at 440000 {
+- compatible = "syscon", "simple-mfd";
+- reg = <0x440000 0x2000>;
+-
+- CP110_LABEL(clk): clock {
+- compatible = "marvell,cp110-clock";
+- #clock-cells = <2>;
+- };
+-
+- CP110_LABEL(gpio1): gpio at 100 {
+- compatible = "marvell,armada-8k-gpio";
+- offset = <0x100>;
+- ngpios = <32>;
+- gpio-controller;
+- #gpio-cells = <2>;
+- gpio-ranges = <&CP110_LABEL(pinctrl) 0 0 32>;
+- interrupt-controller;
+- interrupts = <86 IRQ_TYPE_LEVEL_HIGH>,
+- <85 IRQ_TYPE_LEVEL_HIGH>,
+- <84 IRQ_TYPE_LEVEL_HIGH>,
+- <83 IRQ_TYPE_LEVEL_HIGH>;
+- #interrupt-cells = <2>;
+- status = "disabled";
+- };
+-
+- CP110_LABEL(gpio2): gpio at 140 {
+- compatible = "marvell,armada-8k-gpio";
+- offset = <0x140>;
+- ngpios = <31>;
+- gpio-controller;
+- #gpio-cells = <2>;
+- gpio-ranges = <&CP110_LABEL(pinctrl) 0 32 31>;
+- interrupt-controller;
+- interrupts = <82 IRQ_TYPE_LEVEL_HIGH>,
+- <81 IRQ_TYPE_LEVEL_HIGH>,
+- <80 IRQ_TYPE_LEVEL_HIGH>,
+- <79 IRQ_TYPE_LEVEL_HIGH>;
+- #interrupt-cells = <2>;
+- status = "disabled";
+- };
+- };
+-
+- CP110_LABEL(syscon1): system-controller at 400000 {
+- compatible = "syscon", "simple-mfd";
+- reg = <0x400000 0x1000>;
+- #address-cells = <1>;
+- #size-cells = <1>;
+-
+- CP110_LABEL(thermal): thermal-sensor at 70 {
+- compatible = "marvell,armada-cp110-thermal";
+- reg = <0x70 0x10>;
+- interrupts-extended =
+- <&CP110_LABEL(icu_sei) 116 IRQ_TYPE_LEVEL_HIGH>;
+- #thermal-sensor-cells = <1>;
+- };
+- };
+-
+- CP110_LABEL(usb3_0): usb3 at 500000 {
+- compatible = "marvell,armada-8k-xhci",
+- "generic-xhci";
+- reg = <0x500000 0x4000>;
+- dma-coherent;
+- interrupts = <106 IRQ_TYPE_LEVEL_HIGH>;
+- clock-names = "core", "reg";
+- clocks = <&CP110_LABEL(clk) 1 22>,
+- <&CP110_LABEL(clk) 1 16>;
+- status = "disabled";
+- };
+-
+- CP110_LABEL(usb3_1): usb3 at 510000 {
+- compatible = "marvell,armada-8k-xhci",
+- "generic-xhci";
+- reg = <0x510000 0x4000>;
+- dma-coherent;
+- interrupts = <105 IRQ_TYPE_LEVEL_HIGH>;
+- clock-names = "core", "reg";
+- clocks = <&CP110_LABEL(clk) 1 23>,
+- <&CP110_LABEL(clk) 1 16>;
+- status = "disabled";
+- };
+-
+- CP110_LABEL(sata0): sata at 540000 {
+- compatible = "marvell,armada-8k-ahci",
+- "generic-ahci";
+- reg = <0x540000 0x30000>;
+- dma-coherent;
+- interrupts = <107 IRQ_TYPE_LEVEL_HIGH>;
+- clocks = <&CP110_LABEL(clk) 1 15>,
+- <&CP110_LABEL(clk) 1 16>;
+- #address-cells = <1>;
+- #size-cells = <0>;
+- status = "disabled";
+-
+- sata-port at 0 {
+- reg = <0>;
+- };
+-
+- sata-port at 1 {
+- reg = <1>;
+- };
+- };
+-
+- CP110_LABEL(xor0): xor at 6a0000 {
+- compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
+- reg = <0x6a0000 0x1000>, <0x6b0000 0x1000>;
+- dma-coherent;
+- msi-parent = <&gic_v2m0>;
+- clock-names = "core", "reg";
+- clocks = <&CP110_LABEL(clk) 1 8>,
+- <&CP110_LABEL(clk) 1 14>;
+- };
+-
+- CP110_LABEL(xor1): xor at 6c0000 {
+- compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
+- reg = <0x6c0000 0x1000>, <0x6d0000 0x1000>;
+- dma-coherent;
+- msi-parent = <&gic_v2m0>;
+- clock-names = "core", "reg";
+- clocks = <&CP110_LABEL(clk) 1 7>,
+- <&CP110_LABEL(clk) 1 14>;
+- };
+-
+- CP110_LABEL(spi0): spi at 700600 {
+- compatible = "marvell,armada-380-spi";
+- reg = <0x700600 0x50>;
+- #address-cells = <0x1>;
+- #size-cells = <0x0>;
+- clock-names = "core", "axi";
+- clocks = <&CP110_LABEL(clk) 1 21>,
+- <&CP110_LABEL(clk) 1 17>;
+- status = "disabled";
+- };
+-
+- CP110_LABEL(spi1): spi at 700680 {
+- compatible = "marvell,armada-380-spi";
+- reg = <0x700680 0x50>;
+- #address-cells = <1>;
+- #size-cells = <0>;
+- clock-names = "core", "axi";
+- clocks = <&CP110_LABEL(clk) 1 21>,
+- <&CP110_LABEL(clk) 1 17>;
+- status = "disabled";
+- };
+-
+- CP110_LABEL(i2c0): i2c at 701000 {
+- compatible = "marvell,mv78230-i2c";
+- reg = <0x701000 0x20>;
+- #address-cells = <1>;
+- #size-cells = <0>;
+- interrupts = <120 IRQ_TYPE_LEVEL_HIGH>;
+- clock-names = "core", "reg";
+- clocks = <&CP110_LABEL(clk) 1 21>,
+- <&CP110_LABEL(clk) 1 17>;
+- status = "disabled";
+- };
+-
+- CP110_LABEL(i2c1): i2c at 701100 {
+- compatible = "marvell,mv78230-i2c";
+- reg = <0x701100 0x20>;
+- #address-cells = <1>;
+- #size-cells = <0>;
+- interrupts = <121 IRQ_TYPE_LEVEL_HIGH>;
+- clock-names = "core", "reg";
+- clocks = <&CP110_LABEL(clk) 1 21>,
+- <&CP110_LABEL(clk) 1 17>;
+- status = "disabled";
+- };
+-
+- CP110_LABEL(uart0): serial at 702000 {
+- compatible = "snps,dw-apb-uart";
+- reg = <0x702000 0x100>;
+- reg-shift = <2>;
+- interrupts = <122 IRQ_TYPE_LEVEL_HIGH>;
+- reg-io-width = <1>;
+- clock-names = "baudclk", "apb_pclk";
+- clocks = <&CP110_LABEL(clk) 1 21>,
+- <&CP110_LABEL(clk) 1 17>;
+- status = "disabled";
+- };
+-
+- CP110_LABEL(uart1): serial at 702100 {
+- compatible = "snps,dw-apb-uart";
+- reg = <0x702100 0x100>;
+- reg-shift = <2>;
+- interrupts = <123 IRQ_TYPE_LEVEL_HIGH>;
+- reg-io-width = <1>;
+- clock-names = "baudclk", "apb_pclk";
+- clocks = <&CP110_LABEL(clk) 1 21>,
+- <&CP110_LABEL(clk) 1 17>;
+- status = "disabled";
+- };
+-
+- CP110_LABEL(uart2): serial at 702200 {
+- compatible = "snps,dw-apb-uart";
+- reg = <0x702200 0x100>;
+- reg-shift = <2>;
+- interrupts = <124 IRQ_TYPE_LEVEL_HIGH>;
+- reg-io-width = <1>;
+- clock-names = "baudclk", "apb_pclk";
+- clocks = <&CP110_LABEL(clk) 1 21>,
+- <&CP110_LABEL(clk) 1 17>;
+- status = "disabled";
+- };
+-
+- CP110_LABEL(uart3): serial at 702300 {
+- compatible = "snps,dw-apb-uart";
+- reg = <0x702300 0x100>;
+- reg-shift = <2>;
+- interrupts = <125 IRQ_TYPE_LEVEL_HIGH>;
+- reg-io-width = <1>;
+- clock-names = "baudclk", "apb_pclk";
+- clocks = <&CP110_LABEL(clk) 1 21>,
+- <&CP110_LABEL(clk) 1 17>;
+- status = "disabled";
+- };
+-
+- CP110_LABEL(nand_controller): nand at 720000 {
+- /*
+- * Due to the limitation of the pins available
+- * this controller is only usable on the CPM
+- * for A7K and on the CPS for A8K.
+- */
+- compatible = "marvell,armada-8k-nand-controller",
+- "marvell,armada370-nand-controller";
+- reg = <0x720000 0x54>;
+- #address-cells = <1>;
+- #size-cells = <0>;
+- interrupts = <115 IRQ_TYPE_LEVEL_HIGH>;
+- clock-names = "core", "reg";
+- clocks = <&CP110_LABEL(clk) 1 2>,
+- <&CP110_LABEL(clk) 1 17>;
+- marvell,system-controller = <&CP110_LABEL(syscon0)>;
+- status = "disabled";
+- };
+-
+- CP110_LABEL(trng): trng at 760000 {
+- compatible = "marvell,armada-8k-rng",
+- "inside-secure,safexcel-eip76";
+- reg = <0x760000 0x7d>;
+- interrupts = <95 IRQ_TYPE_LEVEL_HIGH>;
+- clock-names = "core", "reg";
+- clocks = <&CP110_LABEL(clk) 1 25>,
+- <&CP110_LABEL(clk) 1 17>;
+- status = "okay";
+- };
+-
+- CP110_LABEL(sdhci0): sdhci at 780000 {
+- compatible = "marvell,armada-cp110-sdhci";
+- reg = <0x780000 0x300>;
+- interrupts = <27 IRQ_TYPE_LEVEL_HIGH>;
+- clock-names = "core", "axi";
+- clocks = <&CP110_LABEL(clk) 1 4>, <&CP110_LABEL(clk) 1 18>;
+- dma-coherent;
+- status = "disabled";
+- };
+-
+- CP110_LABEL(crypto): crypto at 800000 {
+- compatible = "inside-secure,safexcel-eip197b";
+- reg = <0x800000 0x200000>;
+- interrupts = <87 IRQ_TYPE_LEVEL_HIGH>,
+- <88 IRQ_TYPE_LEVEL_HIGH>,
+- <89 IRQ_TYPE_LEVEL_HIGH>,
+- <90 IRQ_TYPE_LEVEL_HIGH>,
+- <91 IRQ_TYPE_LEVEL_HIGH>,
+- <92 IRQ_TYPE_LEVEL_HIGH>;
+- interrupt-names = "mem", "ring0", "ring1",
+- "ring2", "ring3", "eip";
+- clock-names = "core", "reg";
+- clocks = <&CP110_LABEL(clk) 1 26>,
+- <&CP110_LABEL(clk) 1 17>;
+- dma-coherent;
+- };
+- };
+-
+- CP110_LABEL(pcie0): pcie at CP110_PCIE0_BASE {
+- compatible = "marvell,armada8k-pcie", "snps,dw-pcie";
+- reg = <0 ADDRESSIFY(CP110_PCIE0_BASE) 0 0x10000>,
+- <0 CP110_PCIEx_CONF_BASE(0) 0 0x80000>;
+- reg-names = "ctrl", "config";
+- #address-cells = <3>;
+- #size-cells = <2>;
+- #interrupt-cells = <1>;
+- device_type = "pci";
+- dma-coherent;
+- msi-parent = <&gic_v2m0>;
+-
+- bus-range = <0 0xff>;
+- ranges =
+- /* downstream I/O */
+- <0x81000000 0 CP110_PCIEx_IO_BASE(0) 0 CP110_PCIEx_IO_BASE(0) 0 0x10000
+- /* non-prefetchable memory */
+- 0x82000000 0 CP110_PCIEx_MEM_BASE(0) 0 CP110_PCIEx_MEM_BASE(0) 0 0xf00000>;
+- interrupt-map-mask = <0 0 0 0>;
+- interrupt-map = <0 0 0 0 &CP110_LABEL(icu_nsr) 22 IRQ_TYPE_LEVEL_HIGH>;
+- interrupts = <22 IRQ_TYPE_LEVEL_HIGH>;
+- num-lanes = <1>;
+- clock-names = "core", "reg";
+- clocks = <&CP110_LABEL(clk) 1 13>, <&CP110_LABEL(clk) 1 14>;
+- status = "disabled";
+- };
+-
+- CP110_LABEL(pcie1): pcie at CP110_PCIE1_BASE {
+- compatible = "marvell,armada8k-pcie", "snps,dw-pcie";
+- reg = <0 ADDRESSIFY(CP110_PCIE1_BASE) 0 0x10000>,
+- <0 CP110_PCIEx_CONF_BASE(1) 0 0x80000>;
+- reg-names = "ctrl", "config";
+- #address-cells = <3>;
+- #size-cells = <2>;
+- #interrupt-cells = <1>;
+- device_type = "pci";
+- dma-coherent;
+- msi-parent = <&gic_v2m0>;
+-
+- bus-range = <0 0xff>;
+- ranges =
+- /* downstream I/O */
+- <0x81000000 0 CP110_PCIEx_IO_BASE(1) 0 CP110_PCIEx_IO_BASE(1) 0 0x10000
+- /* non-prefetchable memory */
+- 0x82000000 0 CP110_PCIEx_MEM_BASE(1) 0 CP110_PCIEx_MEM_BASE(1) 0 0xf00000>;
+- interrupt-map-mask = <0 0 0 0>;
+- interrupt-map = <0 0 0 0 &CP110_LABEL(icu_nsr) 24 IRQ_TYPE_LEVEL_HIGH>;
+- interrupts = <24 IRQ_TYPE_LEVEL_HIGH>;
+-
+- num-lanes = <1>;
+- clock-names = "core", "reg";
+- clocks = <&CP110_LABEL(clk) 1 11>, <&CP110_LABEL(clk) 1 14>;
+- status = "disabled";
+- };
+-
+- CP110_LABEL(pcie2): pcie at CP110_PCIE2_BASE {
+- compatible = "marvell,armada8k-pcie", "snps,dw-pcie";
+- reg = <0 ADDRESSIFY(CP110_PCIE2_BASE) 0 0x10000>,
+- <0 CP110_PCIEx_CONF_BASE(2) 0 0x80000>;
+- reg-names = "ctrl", "config";
+- #address-cells = <3>;
+- #size-cells = <2>;
+- #interrupt-cells = <1>;
+- device_type = "pci";
+- dma-coherent;
+- msi-parent = <&gic_v2m0>;
+-
+- bus-range = <0 0xff>;
+- ranges =
+- /* downstream I/O */
+- <0x81000000 0 CP110_PCIEx_IO_BASE(2) 0 CP110_PCIEx_IO_BASE(2) 0 0x10000
+- /* non-prefetchable memory */
+- 0x82000000 0 CP110_PCIEx_MEM_BASE(2) 0 CP110_PCIEx_MEM_BASE(2) 0 0xf00000>;
+- interrupt-map-mask = <0 0 0 0>;
+- interrupt-map = <0 0 0 0 &CP110_LABEL(icu_nsr) 23 IRQ_TYPE_LEVEL_HIGH>;
+- interrupts = <23 IRQ_TYPE_LEVEL_HIGH>;
+-
+- num-lanes = <1>;
+- clock-names = "core", "reg";
+- clocks = <&CP110_LABEL(clk) 1 12>, <&CP110_LABEL(clk) 1 14>;
+- status = "disabled";
+- };
+-};
++#undef CP11X_TYPE
+--- /dev/null
++++ b/arch/arm64/boot/dts/marvell/armada-cp11x.dtsi
+@@ -0,0 +1,579 @@
++// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
++/*
++ * Copyright (C) 2016 Marvell Technology Group Ltd.
++ *
++ * Device Tree file for Marvell Armada CP11x.
++ */
++
++#include <dt-bindings/interrupt-controller/mvebu-icu.h>
++#include <dt-bindings/thermal/thermal.h>
++
++#include "armada-common.dtsi"
++
++#define CP11X_PCIEx_IO_BASE(iface) (CP11X_PCIE_IO_BASE + (iface * 0x10000))
++#define CP11X_PCIEx_MEM_BASE(iface) (CP11X_PCIE_MEM_BASE + (iface * 0x1000000))
++#define CP11X_PCIEx_CONF_BASE(iface) (CP11X_PCIEx_MEM_BASE(iface) + 0xf00000)
++
++/ {
++ /*
++ * The contents of the node are defined below, in order to
++ * save one indentation level
++ */
++ CP11X_NAME: CP11X_NAME { };
++
++ /*
++ * CPs only have one sensor in the thermal IC.
++ *
++ * The cooling maps are empty as there are no cooling devices.
++ */
++ thermal-zones {
++ CP11X_LABEL(thermal_ic): CP11X_NODE_NAME(thermal-ic) {
++ polling-delay-passive = <0>; /* Interrupt driven */
++ polling-delay = <0>; /* Interrupt driven */
++
++ thermal-sensors = <&CP11X_LABEL(thermal) 0>;
++
++ trips {
++ CP11X_LABEL(crit): crit {
++ temperature = <100000>; /* mC degrees */
++ hysteresis = <2000>; /* mC degrees */
++ type = "critical";
++ };
++ };
++
++ cooling-maps { };
++ };
++ };
++};
++
++&CP11X_NAME {
++ #address-cells = <2>;
++ #size-cells = <2>;
++ compatible = "simple-bus";
++ interrupt-parent = <&CP11X_LABEL(icu_nsr)>;
++ ranges;
++
++ config-space at CP11X_BASE {
++ #address-cells = <1>;
++ #size-cells = <1>;
++ compatible = "simple-bus";
++ ranges = <0x0 0x0 ADDRESSIFY(CP11X_BASE) 0x2000000>;
++
++ CP11X_LABEL(ethernet): ethernet at 0 {
++ compatible = "marvell,armada-7k-pp22";
++ reg = <0x0 0x100000>, <0x129000 0xb000>;
++ clocks = <&CP11X_LABEL(clk) 1 3>, <&CP11X_LABEL(clk) 1 9>,
++ <&CP11X_LABEL(clk) 1 5>, <&CP11X_LABEL(clk) 1 6>,
++ <&CP11X_LABEL(clk) 1 18>;
++ clock-names = "pp_clk", "gop_clk",
++ "mg_clk", "mg_core_clk", "axi_clk";
++ marvell,system-controller = <&CP11X_LABEL(syscon0)>;
++ status = "disabled";
++ dma-coherent;
++
++ CP11X_LABEL(eth0): eth0 {
++ interrupts = <39 IRQ_TYPE_LEVEL_HIGH>,
++ <43 IRQ_TYPE_LEVEL_HIGH>,
++ <47 IRQ_TYPE_LEVEL_HIGH>,
++ <51 IRQ_TYPE_LEVEL_HIGH>,
++ <55 IRQ_TYPE_LEVEL_HIGH>,
++ <59 IRQ_TYPE_LEVEL_HIGH>,
++ <63 IRQ_TYPE_LEVEL_HIGH>,
++ <67 IRQ_TYPE_LEVEL_HIGH>,
++ <71 IRQ_TYPE_LEVEL_HIGH>,
++ <129 IRQ_TYPE_LEVEL_HIGH>;
++ interrupt-names = "hif0", "hif1", "hif2",
++ "hif3", "hif4", "hif5", "hif6", "hif7",
++ "hif8", "link";
++ port-id = <0>;
++ gop-port-id = <0>;
++ status = "disabled";
++ };
++
++ CP11X_LABEL(eth1): eth1 {
++ interrupts = <40 IRQ_TYPE_LEVEL_HIGH>,
++ <44 IRQ_TYPE_LEVEL_HIGH>,
++ <48 IRQ_TYPE_LEVEL_HIGH>,
++ <52 IRQ_TYPE_LEVEL_HIGH>,
++ <56 IRQ_TYPE_LEVEL_HIGH>,
++ <60 IRQ_TYPE_LEVEL_HIGH>,
++ <64 IRQ_TYPE_LEVEL_HIGH>,
++ <68 IRQ_TYPE_LEVEL_HIGH>,
++ <72 IRQ_TYPE_LEVEL_HIGH>,
++ <128 IRQ_TYPE_LEVEL_HIGH>;
++ interrupt-names = "hif0", "hif1", "hif2",
++ "hif3", "hif4", "hif5", "hif6", "hif7",
++ "hif8", "link";
++ port-id = <1>;
++ gop-port-id = <2>;
++ status = "disabled";
++ };
++
++ CP11X_LABEL(eth2): eth2 {
++ interrupts = <41 IRQ_TYPE_LEVEL_HIGH>,
++ <45 IRQ_TYPE_LEVEL_HIGH>,
++ <49 IRQ_TYPE_LEVEL_HIGH>,
++ <53 IRQ_TYPE_LEVEL_HIGH>,
++ <57 IRQ_TYPE_LEVEL_HIGH>,
++ <61 IRQ_TYPE_LEVEL_HIGH>,
++ <65 IRQ_TYPE_LEVEL_HIGH>,
++ <69 IRQ_TYPE_LEVEL_HIGH>,
++ <73 IRQ_TYPE_LEVEL_HIGH>,
++ <127 IRQ_TYPE_LEVEL_HIGH>;
++ interrupt-names = "hif0", "hif1", "hif2",
++ "hif3", "hif4", "hif5", "hif6", "hif7",
++ "hif8", "link";
++ port-id = <2>;
++ gop-port-id = <3>;
++ status = "disabled";
++ };
++ };
++
++ CP11X_LABEL(comphy): phy at 120000 {
++ compatible = "marvell,comphy-cp110";
++ reg = <0x120000 0x6000>;
++ marvell,system-controller = <&CP11X_LABEL(syscon0)>;
++ clocks = <&CP11X_LABEL(clk) 1 5>, <&CP11X_LABEL(clk) 1 6>,
++ <&CP11X_LABEL(clk) 1 18>;
++ clock-names = "mg_clk", "mg_core_clk", "axi_clk";
++ #address-cells = <1>;
++ #size-cells = <0>;
++
++ CP11X_LABEL(comphy0): phy at 0 {
++ reg = <0>;
++ #phy-cells = <1>;
++ };
++
++ CP11X_LABEL(comphy1): phy at 1 {
++ reg = <1>;
++ #phy-cells = <1>;
++ };
++
++ CP11X_LABEL(comphy2): phy at 2 {
++ reg = <2>;
++ #phy-cells = <1>;
++ };
++
++ CP11X_LABEL(comphy3): phy at 3 {
++ reg = <3>;
++ #phy-cells = <1>;
++ };
++
++ CP11X_LABEL(comphy4): phy at 4 {
++ reg = <4>;
++ #phy-cells = <1>;
++ };
++
++ CP11X_LABEL(comphy5): phy at 5 {
++ reg = <5>;
++ #phy-cells = <1>;
++ };
++ };
++
++ CP11X_LABEL(mdio): mdio at 12a200 {
++ #address-cells = <1>;
++ #size-cells = <0>;
++ compatible = "marvell,orion-mdio";
++ reg = <0x12a200 0x10>;
++ clocks = <&CP11X_LABEL(clk) 1 9>, <&CP11X_LABEL(clk) 1 5>,
++ <&CP11X_LABEL(clk) 1 6>, <&CP11X_LABEL(clk) 1 18>;
++ status = "disabled";
++ };
++
++ CP11X_LABEL(xmdio): mdio at 12a600 {
++ #address-cells = <1>;
++ #size-cells = <0>;
++ compatible = "marvell,xmdio";
++ reg = <0x12a600 0x10>;
++ clocks = <&CP11X_LABEL(clk) 1 5>,
++ <&CP11X_LABEL(clk) 1 6>, <&CP11X_LABEL(clk) 1 18>;
++ status = "disabled";
++ };
++
++ CP11X_LABEL(icu): interrupt-controller at 1e0000 {
++ compatible = "marvell,cp110-icu";
++ reg = <0x1e0000 0x440>;
++ #address-cells = <1>;
++ #size-cells = <1>;
++
++ CP11X_LABEL(icu_nsr): interrupt-controller at 10 {
++ compatible = "marvell,cp110-icu-nsr";
++ reg = <0x10 0x20>;
++ #interrupt-cells = <2>;
++ interrupt-controller;
++ msi-parent = <&gicp>;
++ };
++
++ CP11X_LABEL(icu_sei): interrupt-controller at 50 {
++ compatible = "marvell,cp110-icu-sei";
++ reg = <0x50 0x10>;
++ #interrupt-cells = <2>;
++ interrupt-controller;
++ msi-parent = <&sei>;
++ };
++ };
++
++ CP11X_LABEL(rtc): rtc at 284000 {
++ compatible = "marvell,armada-8k-rtc";
++ reg = <0x284000 0x20>, <0x284080 0x24>;
++ reg-names = "rtc", "rtc-soc";
++ interrupts = <77 IRQ_TYPE_LEVEL_HIGH>;
++ };
++
++ CP11X_LABEL(syscon0): system-controller at 440000 {
++ compatible = "syscon", "simple-mfd";
++ reg = <0x440000 0x2000>;
++
++ CP11X_LABEL(clk): clock {
++ compatible = "marvell,cp110-clock";
++ #clock-cells = <2>;
++ };
++
++ CP11X_LABEL(gpio1): gpio at 100 {
++ compatible = "marvell,armada-8k-gpio";
++ offset = <0x100>;
++ ngpios = <32>;
++ gpio-controller;
++ #gpio-cells = <2>;
++ gpio-ranges = <&CP11X_LABEL(pinctrl) 0 0 32>;
++ interrupt-controller;
++ interrupts = <86 IRQ_TYPE_LEVEL_HIGH>,
++ <85 IRQ_TYPE_LEVEL_HIGH>,
++ <84 IRQ_TYPE_LEVEL_HIGH>,
++ <83 IRQ_TYPE_LEVEL_HIGH>;
++ #interrupt-cells = <2>;
++ status = "disabled";
++ };
++
++ CP11X_LABEL(gpio2): gpio at 140 {
++ compatible = "marvell,armada-8k-gpio";
++ offset = <0x140>;
++ ngpios = <31>;
++ gpio-controller;
++ #gpio-cells = <2>;
++ gpio-ranges = <&CP11X_LABEL(pinctrl) 0 32 31>;
++ interrupt-controller;
++ interrupts = <82 IRQ_TYPE_LEVEL_HIGH>,
++ <81 IRQ_TYPE_LEVEL_HIGH>,
++ <80 IRQ_TYPE_LEVEL_HIGH>,
++ <79 IRQ_TYPE_LEVEL_HIGH>;
++ #interrupt-cells = <2>;
++ status = "disabled";
++ };
++ };
++
++ CP11X_LABEL(syscon1): system-controller at 400000 {
++ compatible = "syscon", "simple-mfd";
++ reg = <0x400000 0x1000>;
++ #address-cells = <1>;
++ #size-cells = <1>;
++
++ CP11X_LABEL(thermal): thermal-sensor at 70 {
++ compatible = "marvell,armada-cp110-thermal";
++ reg = <0x70 0x10>;
++ interrupts-extended =
++ <&CP11X_LABEL(icu_sei) 116 IRQ_TYPE_LEVEL_HIGH>;
++ #thermal-sensor-cells = <1>;
++ };
++ };
++
++ CP11X_LABEL(usb3_0): usb3 at 500000 {
++ compatible = "marvell,armada-8k-xhci",
++ "generic-xhci";
++ reg = <0x500000 0x4000>;
++ dma-coherent;
++ interrupts = <106 IRQ_TYPE_LEVEL_HIGH>;
++ clock-names = "core", "reg";
++ clocks = <&CP11X_LABEL(clk) 1 22>,
++ <&CP11X_LABEL(clk) 1 16>;
++ status = "disabled";
++ };
++
++ CP11X_LABEL(usb3_1): usb3 at 510000 {
++ compatible = "marvell,armada-8k-xhci",
++ "generic-xhci";
++ reg = <0x510000 0x4000>;
++ dma-coherent;
++ interrupts = <105 IRQ_TYPE_LEVEL_HIGH>;
++ clock-names = "core", "reg";
++ clocks = <&CP11X_LABEL(clk) 1 23>,
++ <&CP11X_LABEL(clk) 1 16>;
++ status = "disabled";
++ };
++
++ CP11X_LABEL(sata0): sata at 540000 {
++ compatible = "marvell,armada-8k-ahci",
++ "generic-ahci";
++ reg = <0x540000 0x30000>;
++ dma-coherent;
++ interrupts = <107 IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&CP11X_LABEL(clk) 1 15>,
++ <&CP11X_LABEL(clk) 1 16>;
++ #address-cells = <1>;
++ #size-cells = <0>;
++ status = "disabled";
++
++ sata-port at 0 {
++ reg = <0>;
++ };
++
++ sata-port at 1 {
++ reg = <1>;
++ };
++ };
++
++ CP11X_LABEL(xor0): xor at 6a0000 {
++ compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
++ reg = <0x6a0000 0x1000>, <0x6b0000 0x1000>;
++ dma-coherent;
++ msi-parent = <&gic_v2m0>;
++ clock-names = "core", "reg";
++ clocks = <&CP11X_LABEL(clk) 1 8>,
++ <&CP11X_LABEL(clk) 1 14>;
++ };
++
++ CP11X_LABEL(xor1): xor at 6c0000 {
++ compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
++ reg = <0x6c0000 0x1000>, <0x6d0000 0x1000>;
++ dma-coherent;
++ msi-parent = <&gic_v2m0>;
++ clock-names = "core", "reg";
++ clocks = <&CP11X_LABEL(clk) 1 7>,
++ <&CP11X_LABEL(clk) 1 14>;
++ };
++
++ CP11X_LABEL(spi0): spi at 700600 {
++ compatible = "marvell,armada-380-spi";
++ reg = <0x700600 0x50>;
++ #address-cells = <0x1>;
++ #size-cells = <0x0>;
++ clock-names = "core", "axi";
++ clocks = <&CP11X_LABEL(clk) 1 21>,
++ <&CP11X_LABEL(clk) 1 17>;
++ status = "disabled";
++ };
++
++ CP11X_LABEL(spi1): spi at 700680 {
++ compatible = "marvell,armada-380-spi";
++ reg = <0x700680 0x50>;
++ #address-cells = <1>;
++ #size-cells = <0>;
++ clock-names = "core", "axi";
++ clocks = <&CP11X_LABEL(clk) 1 21>,
++ <&CP11X_LABEL(clk) 1 17>;
++ status = "disabled";
++ };
++
++ CP11X_LABEL(i2c0): i2c at 701000 {
++ compatible = "marvell,mv78230-i2c";
++ reg = <0x701000 0x20>;
++ #address-cells = <1>;
++ #size-cells = <0>;
++ interrupts = <120 IRQ_TYPE_LEVEL_HIGH>;
++ clock-names = "core", "reg";
++ clocks = <&CP11X_LABEL(clk) 1 21>,
++ <&CP11X_LABEL(clk) 1 17>;
++ status = "disabled";
++ };
++
++ CP11X_LABEL(i2c1): i2c at 701100 {
++ compatible = "marvell,mv78230-i2c";
++ reg = <0x701100 0x20>;
++ #address-cells = <1>;
++ #size-cells = <0>;
++ interrupts = <121 IRQ_TYPE_LEVEL_HIGH>;
++ clock-names = "core", "reg";
++ clocks = <&CP11X_LABEL(clk) 1 21>,
++ <&CP11X_LABEL(clk) 1 17>;
++ status = "disabled";
++ };
++
++ CP11X_LABEL(uart0): serial at 702000 {
++ compatible = "snps,dw-apb-uart";
++ reg = <0x702000 0x100>;
++ reg-shift = <2>;
++ interrupts = <122 IRQ_TYPE_LEVEL_HIGH>;
++ reg-io-width = <1>;
++ clock-names = "baudclk", "apb_pclk";
++ clocks = <&CP11X_LABEL(clk) 1 21>,
++ <&CP11X_LABEL(clk) 1 17>;
++ status = "disabled";
++ };
++
++ CP11X_LABEL(uart1): serial at 702100 {
++ compatible = "snps,dw-apb-uart";
++ reg = <0x702100 0x100>;
++ reg-shift = <2>;
++ interrupts = <123 IRQ_TYPE_LEVEL_HIGH>;
++ reg-io-width = <1>;
++ clock-names = "baudclk", "apb_pclk";
++ clocks = <&CP11X_LABEL(clk) 1 21>,
++ <&CP11X_LABEL(clk) 1 17>;
++ status = "disabled";
++ };
++
++ CP11X_LABEL(uart2): serial at 702200 {
++ compatible = "snps,dw-apb-uart";
++ reg = <0x702200 0x100>;
++ reg-shift = <2>;
++ interrupts = <124 IRQ_TYPE_LEVEL_HIGH>;
++ reg-io-width = <1>;
++ clock-names = "baudclk", "apb_pclk";
++ clocks = <&CP11X_LABEL(clk) 1 21>,
++ <&CP11X_LABEL(clk) 1 17>;
++ status = "disabled";
++ };
++
++ CP11X_LABEL(uart3): serial at 702300 {
++ compatible = "snps,dw-apb-uart";
++ reg = <0x702300 0x100>;
++ reg-shift = <2>;
++ interrupts = <125 IRQ_TYPE_LEVEL_HIGH>;
++ reg-io-width = <1>;
++ clock-names = "baudclk", "apb_pclk";
++ clocks = <&CP11X_LABEL(clk) 1 21>,
++ <&CP11X_LABEL(clk) 1 17>;
++ status = "disabled";
++ };
++
++ CP11X_LABEL(nand_controller): nand at 720000 {
++ /*
++ * Due to the limitation of the pins available
++ * this controller is only usable on the CPM
++ * for A7K and on the CPS for A8K.
++ */
++ compatible = "marvell,armada-8k-nand-controller",
++ "marvell,armada370-nand-controller";
++ reg = <0x720000 0x54>;
++ #address-cells = <1>;
++ #size-cells = <0>;
++ interrupts = <115 IRQ_TYPE_LEVEL_HIGH>;
++ clock-names = "core", "reg";
++ clocks = <&CP11X_LABEL(clk) 1 2>,
++ <&CP11X_LABEL(clk) 1 17>;
++ marvell,system-controller = <&CP11X_LABEL(syscon0)>;
++ status = "disabled";
++ };
++
++ CP11X_LABEL(trng): trng at 760000 {
++ compatible = "marvell,armada-8k-rng",
++ "inside-secure,safexcel-eip76";
++ reg = <0x760000 0x7d>;
++ interrupts = <95 IRQ_TYPE_LEVEL_HIGH>;
++ clock-names = "core", "reg";
++ clocks = <&CP11X_LABEL(clk) 1 25>,
++ <&CP11X_LABEL(clk) 1 17>;
++ status = "okay";
++ };
++
++ CP11X_LABEL(sdhci0): sdhci at 780000 {
++ compatible = "marvell,armada-cp110-sdhci";
++ reg = <0x780000 0x300>;
++ interrupts = <27 IRQ_TYPE_LEVEL_HIGH>;
++ clock-names = "core", "axi";
++ clocks = <&CP11X_LABEL(clk) 1 4>, <&CP11X_LABEL(clk) 1 18>;
++ dma-coherent;
++ status = "disabled";
++ };
++
++ CP11X_LABEL(crypto): crypto at 800000 {
++ compatible = "inside-secure,safexcel-eip197b";
++ reg = <0x800000 0x200000>;
++ interrupts = <87 IRQ_TYPE_LEVEL_HIGH>,
++ <88 IRQ_TYPE_LEVEL_HIGH>,
++ <89 IRQ_TYPE_LEVEL_HIGH>,
++ <90 IRQ_TYPE_LEVEL_HIGH>,
++ <91 IRQ_TYPE_LEVEL_HIGH>,
++ <92 IRQ_TYPE_LEVEL_HIGH>;
++ interrupt-names = "mem", "ring0", "ring1",
++ "ring2", "ring3", "eip";
++ clock-names = "core", "reg";
++ clocks = <&CP11X_LABEL(clk) 1 26>,
++ <&CP11X_LABEL(clk) 1 17>;
++ dma-coherent;
++ };
++ };
++
++ CP11X_LABEL(pcie0): pcie at CP11X_PCIE0_BASE {
++ compatible = "marvell,armada8k-pcie", "snps,dw-pcie";
++ reg = <0 ADDRESSIFY(CP11X_PCIE0_BASE) 0 0x10000>,
++ <0 CP11X_PCIEx_CONF_BASE(0) 0 0x80000>;
++ reg-names = "ctrl", "config";
++ #address-cells = <3>;
++ #size-cells = <2>;
++ #interrupt-cells = <1>;
++ device_type = "pci";
++ dma-coherent;
++ msi-parent = <&gic_v2m0>;
++
++ bus-range = <0 0xff>;
++ ranges =
++ /* downstream I/O */
++ <0x81000000 0 CP11X_PCIEx_IO_BASE(0) 0 CP11X_PCIEx_IO_BASE(0) 0 0x10000
++ /* non-prefetchable memory */
++ 0x82000000 0 CP11X_PCIEx_MEM_BASE(0) 0 CP11X_PCIEx_MEM_BASE(0) 0 0xf00000>;
++ interrupt-map-mask = <0 0 0 0>;
++ interrupt-map = <0 0 0 0 &CP11X_LABEL(icu_nsr) 22 IRQ_TYPE_LEVEL_HIGH>;
++ interrupts = <22 IRQ_TYPE_LEVEL_HIGH>;
++ num-lanes = <1>;
++ clock-names = "core", "reg";
++ clocks = <&CP11X_LABEL(clk) 1 13>, <&CP11X_LABEL(clk) 1 14>;
++ status = "disabled";
++ };
++
++ CP11X_LABEL(pcie1): pcie at CP11X_PCIE1_BASE {
++ compatible = "marvell,armada8k-pcie", "snps,dw-pcie";
++ reg = <0 ADDRESSIFY(CP11X_PCIE1_BASE) 0 0x10000>,
++ <0 CP11X_PCIEx_CONF_BASE(1) 0 0x80000>;
++ reg-names = "ctrl", "config";
++ #address-cells = <3>;
++ #size-cells = <2>;
++ #interrupt-cells = <1>;
++ device_type = "pci";
++ dma-coherent;
++ msi-parent = <&gic_v2m0>;
++
++ bus-range = <0 0xff>;
++ ranges =
++ /* downstream I/O */
++ <0x81000000 0 CP11X_PCIEx_IO_BASE(1) 0 CP11X_PCIEx_IO_BASE(1) 0 0x10000
++ /* non-prefetchable memory */
++ 0x82000000 0 CP11X_PCIEx_MEM_BASE(1) 0 CP11X_PCIEx_MEM_BASE(1) 0 0xf00000>;
++ interrupt-map-mask = <0 0 0 0>;
++ interrupt-map = <0 0 0 0 &CP11X_LABEL(icu_nsr) 24 IRQ_TYPE_LEVEL_HIGH>;
++ interrupts = <24 IRQ_TYPE_LEVEL_HIGH>;
++
++ num-lanes = <1>;
++ clock-names = "core", "reg";
++ clocks = <&CP11X_LABEL(clk) 1 11>, <&CP11X_LABEL(clk) 1 14>;
++ status = "disabled";
++ };
++
++ CP11X_LABEL(pcie2): pcie at CP11X_PCIE2_BASE {
++ compatible = "marvell,armada8k-pcie", "snps,dw-pcie";
++ reg = <0 ADDRESSIFY(CP11X_PCIE2_BASE) 0 0x10000>,
++ <0 CP11X_PCIEx_CONF_BASE(2) 0 0x80000>;
++ reg-names = "ctrl", "config";
++ #address-cells = <3>;
++ #size-cells = <2>;
++ #interrupt-cells = <1>;
++ device_type = "pci";
++ dma-coherent;
++ msi-parent = <&gic_v2m0>;
++
++ bus-range = <0 0xff>;
++ ranges =
++ /* downstream I/O */
++ <0x81000000 0 CP11X_PCIEx_IO_BASE(2) 0 CP11X_PCIEx_IO_BASE(2) 0 0x10000
++ /* non-prefetchable memory */
++ 0x82000000 0 CP11X_PCIEx_MEM_BASE(2) 0 CP11X_PCIEx_MEM_BASE(2) 0 0xf00000>;
++ interrupt-map-mask = <0 0 0 0>;
++ interrupt-map = <0 0 0 0 &CP11X_LABEL(icu_nsr) 23 IRQ_TYPE_LEVEL_HIGH>;
++ interrupts = <23 IRQ_TYPE_LEVEL_HIGH>;
++
++ num-lanes = <1>;
++ clock-names = "core", "reg";
++ clocks = <&CP11X_LABEL(clk) 1 12>, <&CP11X_LABEL(clk) 1 14>;
++ status = "disabled";
++ };
++};
diff --git a/target/linux/mvebu/patches-5.4/003-v5.5-arm64-dts-marvell-Add-support-for-AP807-AP807-quad.patch b/target/linux/mvebu/patches-5.4/003-v5.5-arm64-dts-marvell-Add-support-for-AP807-AP807-quad.patch
new file mode 100644
index 0000000000..72b46f51a7
--- /dev/null
+++ b/target/linux/mvebu/patches-5.4/003-v5.5-arm64-dts-marvell-Add-support-for-AP807-AP807-quad.patch
@@ -0,0 +1,102 @@
+From cbafcad0641e99831ff7c57ac8f79aed502f33e5 Mon Sep 17 00:00:00 2001
+From: Miquel Raynal <miquel.raynal at bootlin.com>
+Date: Fri, 4 Oct 2019 16:27:24 +0200
+Subject: [PATCH] arm64: dts: marvell: Add support for AP807/AP807-quad
+
+Describe AP807 and AP807-quad support.
+
+Signed-off-by: Miquel Raynal <miquel.raynal at bootlin.com>
+Signed-off-by: Gregory CLEMENT <gregory.clement at bootlin.com>
+---
+ .../boot/dts/marvell/armada-ap807-quad.dtsi | 51 +++++++++++++++++++
+ arch/arm64/boot/dts/marvell/armada-ap807.dtsi | 29 +++++++++++
+ 2 files changed, 80 insertions(+)
+ create mode 100644 arch/arm64/boot/dts/marvell/armada-ap807-quad.dtsi
+ create mode 100644 arch/arm64/boot/dts/marvell/armada-ap807.dtsi
+
+--- /dev/null
++++ b/arch/arm64/boot/dts/marvell/armada-ap807-quad.dtsi
+@@ -0,0 +1,51 @@
++// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
++/*
++ * Device Tree file for Marvell Armada AP807 Quad
++ *
++ * Copyright (C) 2019 Marvell Technology Group Ltd.
++ */
++
++#include "armada-ap807.dtsi"
++
++/ {
++ model = "Marvell Armada AP807 Quad";
++ compatible = "marvell,armada-ap807-quad", "marvell,armada-ap807";
++
++ cpus {
++ #address-cells = <1>;
++ #size-cells = <0>;
++
++ cpu0: cpu at 0 {
++ device_type = "cpu";
++ compatible = "arm,cortex-a72", "arm,armv8";
++ reg = <0x000>;
++ enable-method = "psci";
++ #cooling-cells = <2>;
++ clocks = <&cpu_clk 0>;
++ };
++ cpu1: cpu at 1 {
++ device_type = "cpu";
++ compatible = "arm,cortex-a72", "arm,armv8";
++ reg = <0x001>;
++ enable-method = "psci";
++ #cooling-cells = <2>;
++ clocks = <&cpu_clk 0>;
++ };
++ cpu2: cpu at 100 {
++ device_type = "cpu";
++ compatible = "arm,cortex-a72", "arm,armv8";
++ reg = <0x100>;
++ enable-method = "psci";
++ #cooling-cells = <2>;
++ clocks = <&cpu_clk 1>;
++ };
++ cpu3: cpu at 101 {
++ device_type = "cpu";
++ compatible = "arm,cortex-a72", "arm,armv8";
++ reg = <0x101>;
++ enable-method = "psci";
++ #cooling-cells = <2>;
++ clocks = <&cpu_clk 1>;
++ };
++ };
++};
+--- /dev/null
++++ b/arch/arm64/boot/dts/marvell/armada-ap807.dtsi
+@@ -0,0 +1,29 @@
++// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
++/*
++ * Device Tree file for Marvell Armada AP807
++ *
++ * Copyright (C) 2019 Marvell Technology Group Ltd.
++ */
++
++#define AP_NAME ap807
++#include "armada-ap80x.dtsi"
++
++/ {
++ model = "Marvell Armada AP807";
++ compatible = "marvell,armada-ap807";
++};
++
++&ap_syscon0 {
++ ap_clk: clock {
++ compatible = "marvell,ap807-clock";
++ #clock-cells = <1>;
++ };
++};
++
++&ap_syscon1 {
++ cpu_clk: clock-cpu {
++ compatible = "marvell,ap807-cpu-clock";
++ clocks = <&ap_clk 0>, <&ap_clk 1>;
++ #clock-cells = <1>;
++ };
++};
diff --git a/target/linux/mvebu/patches-5.4/004-v5.5-arm64-dts-marvell-Add-AP807-quad-cache-description.patch b/target/linux/mvebu/patches-5.4/004-v5.5-arm64-dts-marvell-Add-AP807-quad-cache-description.patch
new file mode 100644
index 0000000000..6192f5f202
--- /dev/null
+++ b/target/linux/mvebu/patches-5.4/004-v5.5-arm64-dts-marvell-Add-AP807-quad-cache-description.patch
@@ -0,0 +1,87 @@
+From 30d53abdc60a6515f02f181e7c39b7b23d5fb3aa Mon Sep 17 00:00:00 2001
+From: Grzegorz Jaszczyk <jaz at semihalf.com>
+Date: Fri, 4 Oct 2019 16:27:27 +0200
+Subject: [PATCH] arm64: dts: marvell: Add AP807-quad cache description
+
+Adding appropriate entries to device-tree allows the cache description
+to show up in sysfs under: /sys/devices/system/cpu/cpuX/cache/.
+
+Signed-off-by: Grzegorz Jaszczyk <jaz at semihalf.com>
+Signed-off-by: Miquel Raynal <miquel.raynal at bootlin.com>
+Signed-off-by: Gregory CLEMENT <gregory.clement at bootlin.com>
+---
+ .../boot/dts/marvell/armada-ap807-quad.dtsi | 42 +++++++++++++++++++
+ 1 file changed, 42 insertions(+)
+
+--- a/arch/arm64/boot/dts/marvell/armada-ap807-quad.dtsi
++++ b/arch/arm64/boot/dts/marvell/armada-ap807-quad.dtsi
+@@ -22,6 +22,13 @@
+ enable-method = "psci";
+ #cooling-cells = <2>;
+ clocks = <&cpu_clk 0>;
++ i-cache-size = <0xc000>;
++ i-cache-line-size = <64>;
++ i-cache-sets = <256>;
++ d-cache-size = <0x8000>;
++ d-cache-line-size = <64>;
++ d-cache-sets = <256>;
++ next-level-cache = <&l2_0>;
+ };
+ cpu1: cpu at 1 {
+ device_type = "cpu";
+@@ -30,6 +37,13 @@
+ enable-method = "psci";
+ #cooling-cells = <2>;
+ clocks = <&cpu_clk 0>;
++ i-cache-size = <0xc000>;
++ i-cache-line-size = <64>;
++ i-cache-sets = <256>;
++ d-cache-size = <0x8000>;
++ d-cache-line-size = <64>;
++ d-cache-sets = <256>;
++ next-level-cache = <&l2_0>;
+ };
+ cpu2: cpu at 100 {
+ device_type = "cpu";
+@@ -38,6 +52,13 @@
+ enable-method = "psci";
+ #cooling-cells = <2>;
+ clocks = <&cpu_clk 1>;
++ i-cache-size = <0xc000>;
++ i-cache-line-size = <64>;
++ i-cache-sets = <256>;
++ d-cache-size = <0x8000>;
++ d-cache-line-size = <64>;
++ d-cache-sets = <256>;
++ next-level-cache = <&l2_1>;
+ };
+ cpu3: cpu at 101 {
+ device_type = "cpu";
+@@ -46,6 +67,27 @@
+ enable-method = "psci";
+ #cooling-cells = <2>;
+ clocks = <&cpu_clk 1>;
++ i-cache-size = <0xc000>;
++ i-cache-line-size = <64>;
++ i-cache-sets = <256>;
++ d-cache-size = <0x8000>;
++ d-cache-line-size = <64>;
++ d-cache-sets = <256>;
++ next-level-cache = <&l2_1>;
++ };
++
++ l2_0: l2-cache0 {
++ compatible = "cache";
++ cache-size = <0x80000>;
++ cache-line-size = <64>;
++ cache-sets = <512>;
++ };
++
++ l2_1: l2-cache1 {
++ compatible = "cache";
++ cache-size = <0x80000>;
++ cache-line-size = <64>;
++ cache-sets = <512>;
+ };
+ };
+ };
diff --git a/target/linux/mvebu/patches-5.4/005-v5.5-arm64-dts-marvell-Drop-PCIe-I-O-ranges-from-CP11x-fi.patch b/target/linux/mvebu/patches-5.4/005-v5.5-arm64-dts-marvell-Drop-PCIe-I-O-ranges-from-CP11x-fi.patch
new file mode 100644
index 0000000000..e06928d130
--- /dev/null
+++ b/target/linux/mvebu/patches-5.4/005-v5.5-arm64-dts-marvell-Drop-PCIe-I-O-ranges-from-CP11x-fi.patch
@@ -0,0 +1,135 @@
+From 1399672e48b573f6526b9ac78cfd50314f0b01a6 Mon Sep 17 00:00:00 2001
+From: Miquel Raynal <miquel.raynal at bootlin.com>
+Date: Fri, 4 Oct 2019 16:27:30 +0200
+Subject: [PATCH] arm64: dts: marvell: Drop PCIe I/O ranges from CP11x file
+
+As an example, Armada 70x0 and 80x0 SoC 0xf9000000 region points to
+RUNIT/SPICS0 while it is referenced in the DT as PCIe I/O memory
+range. This shows that I/O memory has never been used/working on the
+old SoCs despite the region being advertised. As PCIe I/O ranges will
+not be supported in newer SoCs using CP11x co-processors, let's
+simply drop them. It is not harmful in any case as PCIe device drivers
+can do it all with the regular mapped memory anyway.
+
+Signed-off-by: Miquel Raynal <miquel.raynal at bootlin.com>
+Signed-off-by: Gregory CLEMENT <gregory.clement at bootlin.com>
+---
+ arch/arm64/boot/dts/marvell/armada-70x0.dtsi | 2 --
+ .../boot/dts/marvell/armada-8040-mcbin.dtsi | 3 +--
+ arch/arm64/boot/dts/marvell/armada-80x0.dtsi | 4 ----
+ arch/arm64/boot/dts/marvell/armada-cp11x.dtsi | 16 +++-------------
+ 4 files changed, 4 insertions(+), 21 deletions(-)
+
+--- a/arch/arm64/boot/dts/marvell/armada-70x0.dtsi
++++ b/arch/arm64/boot/dts/marvell/armada-70x0.dtsi
+@@ -19,7 +19,6 @@
+ */
+ #define CP11X_NAME cp0
+ #define CP11X_BASE f2000000
+-#define CP11X_PCIE_IO_BASE 0xf9000000
+ #define CP11X_PCIE_MEM_BASE 0xf6000000
+ #define CP11X_PCIE0_BASE f2600000
+ #define CP11X_PCIE1_BASE f2620000
+@@ -29,7 +28,6 @@
+
+ #undef CP11X_NAME
+ #undef CP11X_BASE
+-#undef CP11X_PCIE_IO_BASE
+ #undef CP11X_PCIE_MEM_BASE
+ #undef CP11X_PCIE0_BASE
+ #undef CP11X_PCIE1_BASE
+--- a/arch/arm64/boot/dts/marvell/armada-8040-mcbin.dtsi
++++ b/arch/arm64/boot/dts/marvell/armada-8040-mcbin.dtsi
+@@ -179,8 +179,7 @@
+ num-lanes = <4>;
+ num-viewport = <8>;
+ reset-gpios = <&cp0_gpio2 20 GPIO_ACTIVE_LOW>;
+- ranges = <0x81000000 0x0 0xf9010000 0x0 0xf9010000 0x0 0x10000
+- 0x82000000 0x0 0xc0000000 0x0 0xc0000000 0x0 0x20000000>;
++ ranges = <0x82000000 0x0 0xc0000000 0x0 0xc0000000 0x0 0x20000000>;
+ phys = <&cp0_comphy0 0>, <&cp0_comphy1 0>,
+ <&cp0_comphy2 0>, <&cp0_comphy3 0>;
+ phy-names = "cp0-pcie0-x4-lane0-phy", "cp0-pcie0-x4-lane1-phy",
+--- a/arch/arm64/boot/dts/marvell/armada-80x0.dtsi
++++ b/arch/arm64/boot/dts/marvell/armada-80x0.dtsi
+@@ -21,7 +21,6 @@
+ */
+ #define CP11X_NAME cp0
+ #define CP11X_BASE f2000000
+-#define CP11X_PCIE_IO_BASE 0xf9000000
+ #define CP11X_PCIE_MEM_BASE 0xf6000000
+ #define CP11X_PCIE0_BASE f2600000
+ #define CP11X_PCIE1_BASE f2620000
+@@ -31,7 +30,6 @@
+
+ #undef CP11X_NAME
+ #undef CP11X_BASE
+-#undef CP11X_PCIE_IO_BASE
+ #undef CP11X_PCIE_MEM_BASE
+ #undef CP11X_PCIE0_BASE
+ #undef CP11X_PCIE1_BASE
+@@ -42,7 +40,6 @@
+ */
+ #define CP11X_NAME cp1
+ #define CP11X_BASE f4000000
+-#define CP11X_PCIE_IO_BASE 0xfd000000
+ #define CP11X_PCIE_MEM_BASE 0xfa000000
+ #define CP11X_PCIE0_BASE f4600000
+ #define CP11X_PCIE1_BASE f4620000
+@@ -52,7 +49,6 @@
+
+ #undef CP11X_NAME
+ #undef CP11X_BASE
+-#undef CP11X_PCIE_IO_BASE
+ #undef CP11X_PCIE_MEM_BASE
+ #undef CP11X_PCIE0_BASE
+ #undef CP11X_PCIE1_BASE
+--- a/arch/arm64/boot/dts/marvell/armada-cp11x.dtsi
++++ b/arch/arm64/boot/dts/marvell/armada-cp11x.dtsi
+@@ -10,7 +10,6 @@
+
+ #include "armada-common.dtsi"
+
+-#define CP11X_PCIEx_IO_BASE(iface) (CP11X_PCIE_IO_BASE + (iface * 0x10000))
+ #define CP11X_PCIEx_MEM_BASE(iface) (CP11X_PCIE_MEM_BASE + (iface * 0x1000000))
+ #define CP11X_PCIEx_CONF_BASE(iface) (CP11X_PCIEx_MEM_BASE(iface) + 0xf00000)
+
+@@ -507,11 +506,8 @@
+ msi-parent = <&gic_v2m0>;
+
+ bus-range = <0 0xff>;
+- ranges =
+- /* downstream I/O */
+- <0x81000000 0 CP11X_PCIEx_IO_BASE(0) 0 CP11X_PCIEx_IO_BASE(0) 0 0x10000
+ /* non-prefetchable memory */
+- 0x82000000 0 CP11X_PCIEx_MEM_BASE(0) 0 CP11X_PCIEx_MEM_BASE(0) 0 0xf00000>;
++ ranges = <0x82000000 0 CP11X_PCIEx_MEM_BASE(0) 0 CP11X_PCIEx_MEM_BASE(0) 0 0xf00000>;
+ interrupt-map-mask = <0 0 0 0>;
+ interrupt-map = <0 0 0 0 &CP11X_LABEL(icu_nsr) 22 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <22 IRQ_TYPE_LEVEL_HIGH>;
+@@ -534,11 +530,8 @@
+ msi-parent = <&gic_v2m0>;
+
+ bus-range = <0 0xff>;
+- ranges =
+- /* downstream I/O */
+- <0x81000000 0 CP11X_PCIEx_IO_BASE(1) 0 CP11X_PCIEx_IO_BASE(1) 0 0x10000
+ /* non-prefetchable memory */
+- 0x82000000 0 CP11X_PCIEx_MEM_BASE(1) 0 CP11X_PCIEx_MEM_BASE(1) 0 0xf00000>;
++ ranges = <0x82000000 0 CP11X_PCIEx_MEM_BASE(1) 0 CP11X_PCIEx_MEM_BASE(1) 0 0xf00000>;
+ interrupt-map-mask = <0 0 0 0>;
+ interrupt-map = <0 0 0 0 &CP11X_LABEL(icu_nsr) 24 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <24 IRQ_TYPE_LEVEL_HIGH>;
+@@ -562,11 +555,8 @@
+ msi-parent = <&gic_v2m0>;
+
+ bus-range = <0 0xff>;
+- ranges =
+- /* downstream I/O */
+- <0x81000000 0 CP11X_PCIEx_IO_BASE(2) 0 CP11X_PCIEx_IO_BASE(2) 0 0x10000
+ /* non-prefetchable memory */
+- 0x82000000 0 CP11X_PCIEx_MEM_BASE(2) 0 CP11X_PCIEx_MEM_BASE(2) 0 0xf00000>;
++ ranges = <0x82000000 0 CP11X_PCIEx_MEM_BASE(2) 0 CP11X_PCIEx_MEM_BASE(2) 0 0xf00000>;
+ interrupt-map-mask = <0 0 0 0>;
+ interrupt-map = <0 0 0 0 &CP11X_LABEL(icu_nsr) 23 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <23 IRQ_TYPE_LEVEL_HIGH>;
diff --git a/target/linux/mvebu/patches-5.4/006-v5.5-arm64-dts-marvell-Externalize-PCIe-macros-from-CP11x.patch b/target/linux/mvebu/patches-5.4/006-v5.5-arm64-dts-marvell-Externalize-PCIe-macros-from-CP11x.patch
new file mode 100644
index 0000000000..0dd9e8f90f
--- /dev/null
+++ b/target/linux/mvebu/patches-5.4/006-v5.5-arm64-dts-marvell-Externalize-PCIe-macros-from-CP11x.patch
@@ -0,0 +1,129 @@
+From 5f07b26e85dc86f017833ea745ff4e5b420280cd Mon Sep 17 00:00:00 2001
+From: Miquel Raynal <miquel.raynal at bootlin.com>
+Date: Fri, 4 Oct 2019 16:27:31 +0200
+Subject: [PATCH] arm64: dts: marvell: Externalize PCIe macros from CP11x file
+
+PCIe macros are specific to CP110 and will not fit CP115
+constraints. To keep the same way the files are organized, just move
+some macros out of the CP11x generic file and define them directly in
+SoC DTSI, instead of defining single addresses in the SoC DTSI and
+reusing them in macros.
+
+In the end:
+* CP11X_PCIE_MEM_BASE SoC define is dropped
+* CP11X_PCIEx_MEM_BASE is moved out of the generic DT to be put in the
+ SoC files as it replaces the above definition.
+* As the CP11X_PCIEx_MEM_SIZE macro is also subject to change with
+ newer SoCs, we put it in the SoC files as well.
+
+Signed-off-by: Miquel Raynal <miquel.raynal at bootlin.com>
+Signed-off-by: Gregory CLEMENT <gregory.clement at bootlin.com>
+---
+ arch/arm64/boot/dts/marvell/armada-70x0.dtsi | 6 ++++--
+ arch/arm64/boot/dts/marvell/armada-80x0.dtsi | 12 ++++++++----
+ arch/arm64/boot/dts/marvell/armada-cp11x.dtsi | 9 ++++-----
+ 3 files changed, 16 insertions(+), 11 deletions(-)
+
+--- a/arch/arm64/boot/dts/marvell/armada-70x0.dtsi
++++ b/arch/arm64/boot/dts/marvell/armada-70x0.dtsi
+@@ -19,7 +19,8 @@
+ */
+ #define CP11X_NAME cp0
+ #define CP11X_BASE f2000000
+-#define CP11X_PCIE_MEM_BASE 0xf6000000
++#define CP11X_PCIEx_MEM_BASE(iface) (0xf6000000 + (iface * 0x1000000))
++#define CP11X_PCIEx_MEM_SIZE(iface) 0xf00000
+ #define CP11X_PCIE0_BASE f2600000
+ #define CP11X_PCIE1_BASE f2620000
+ #define CP11X_PCIE2_BASE f2640000
+@@ -28,7 +29,8 @@
+
+ #undef CP11X_NAME
+ #undef CP11X_BASE
+-#undef CP11X_PCIE_MEM_BASE
++#undef CP11X_PCIEx_MEM_BASE
++#undef CP11X_PCIEx_MEM_SIZE
+ #undef CP11X_PCIE0_BASE
+ #undef CP11X_PCIE1_BASE
+ #undef CP11X_PCIE2_BASE
+--- a/arch/arm64/boot/dts/marvell/armada-80x0.dtsi
++++ b/arch/arm64/boot/dts/marvell/armada-80x0.dtsi
+@@ -21,7 +21,8 @@
+ */
+ #define CP11X_NAME cp0
+ #define CP11X_BASE f2000000
+-#define CP11X_PCIE_MEM_BASE 0xf6000000
++#define CP11X_PCIEx_MEM_BASE(iface) (0xf6000000 + (iface * 0x1000000))
++#define CP11X_PCIEx_MEM_SIZE(iface) 0xf00000
+ #define CP11X_PCIE0_BASE f2600000
+ #define CP11X_PCIE1_BASE f2620000
+ #define CP11X_PCIE2_BASE f2640000
+@@ -30,7 +31,8 @@
+
+ #undef CP11X_NAME
+ #undef CP11X_BASE
+-#undef CP11X_PCIE_MEM_BASE
++#undef CP11X_PCIEx_MEM_BASE
++#undef CP11X_PCIEx_MEM_SIZE
+ #undef CP11X_PCIE0_BASE
+ #undef CP11X_PCIE1_BASE
+ #undef CP11X_PCIE2_BASE
+@@ -40,7 +42,8 @@
+ */
+ #define CP11X_NAME cp1
+ #define CP11X_BASE f4000000
+-#define CP11X_PCIE_MEM_BASE 0xfa000000
++#define CP11X_PCIEx_MEM_BASE(iface) (0xfa000000 + (iface * 0x1000000))
++#define CP11X_PCIEx_MEM_SIZE(iface) 0xf00000
+ #define CP11X_PCIE0_BASE f4600000
+ #define CP11X_PCIE1_BASE f4620000
+ #define CP11X_PCIE2_BASE f4640000
+@@ -49,7 +52,8 @@
+
+ #undef CP11X_NAME
+ #undef CP11X_BASE
+-#undef CP11X_PCIE_MEM_BASE
++#undef CP11X_PCIEx_MEM_BASE
++#undef CP11X_PCIEx_MEM_SIZE
+ #undef CP11X_PCIE0_BASE
+ #undef CP11X_PCIE1_BASE
+ #undef CP11X_PCIE2_BASE
+--- a/arch/arm64/boot/dts/marvell/armada-cp11x.dtsi
++++ b/arch/arm64/boot/dts/marvell/armada-cp11x.dtsi
+@@ -10,8 +10,7 @@
+
+ #include "armada-common.dtsi"
+
+-#define CP11X_PCIEx_MEM_BASE(iface) (CP11X_PCIE_MEM_BASE + (iface * 0x1000000))
+-#define CP11X_PCIEx_CONF_BASE(iface) (CP11X_PCIEx_MEM_BASE(iface) + 0xf00000)
++#define CP11X_PCIEx_CONF_BASE(iface) (CP11X_PCIEx_MEM_BASE(iface) + CP11X_PCIEx_MEM_SIZE(iface))
+
+ / {
+ /*
+@@ -507,7 +506,7 @@
+
+ bus-range = <0 0xff>;
+ /* non-prefetchable memory */
+- ranges = <0x82000000 0 CP11X_PCIEx_MEM_BASE(0) 0 CP11X_PCIEx_MEM_BASE(0) 0 0xf00000>;
++ ranges = <0x82000000 0 CP11X_PCIEx_MEM_BASE(0) 0 CP11X_PCIEx_MEM_BASE(0) 0 CP11X_PCIEx_MEM_SIZE(0)>;
+ interrupt-map-mask = <0 0 0 0>;
+ interrupt-map = <0 0 0 0 &CP11X_LABEL(icu_nsr) 22 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <22 IRQ_TYPE_LEVEL_HIGH>;
+@@ -531,7 +530,7 @@
+
+ bus-range = <0 0xff>;
+ /* non-prefetchable memory */
+- ranges = <0x82000000 0 CP11X_PCIEx_MEM_BASE(1) 0 CP11X_PCIEx_MEM_BASE(1) 0 0xf00000>;
++ ranges = <0x82000000 0 CP11X_PCIEx_MEM_BASE(1) 0 CP11X_PCIEx_MEM_BASE(1) 0 CP11X_PCIEx_MEM_SIZE(1)>;
+ interrupt-map-mask = <0 0 0 0>;
+ interrupt-map = <0 0 0 0 &CP11X_LABEL(icu_nsr) 24 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <24 IRQ_TYPE_LEVEL_HIGH>;
+@@ -556,7 +555,7 @@
+
+ bus-range = <0 0xff>;
+ /* non-prefetchable memory */
+- ranges = <0x82000000 0 CP11X_PCIEx_MEM_BASE(2) 0 CP11X_PCIEx_MEM_BASE(2) 0 0xf00000>;
++ ranges = <0x82000000 0 CP11X_PCIEx_MEM_BASE(2) 0 CP11X_PCIEx_MEM_BASE(2) 0 CP11X_PCIEx_MEM_SIZE(2)>;
+ interrupt-map-mask = <0 0 0 0>;
+ interrupt-map = <0 0 0 0 &CP11X_LABEL(icu_nsr) 23 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <23 IRQ_TYPE_LEVEL_HIGH>;
diff --git a/target/linux/mvebu/patches-5.4/007-v5.5-arm64-dts-marvell-Enumerate-the-first-AP806-syscon.patch b/target/linux/mvebu/patches-5.4/007-v5.5-arm64-dts-marvell-Enumerate-the-first-AP806-syscon.patch
new file mode 100644
index 0000000000..c191b3f7df
--- /dev/null
+++ b/target/linux/mvebu/patches-5.4/007-v5.5-arm64-dts-marvell-Enumerate-the-first-AP806-syscon.patch
@@ -0,0 +1,25 @@
+From 2d6ebaa98be1dd265aa6d99a00c150f1f9f2ea66 Mon Sep 17 00:00:00 2001
+From: Miquel Raynal <miquel.raynal at bootlin.com>
+Date: Fri, 4 Oct 2019 16:27:18 +0200
+Subject: [PATCH] arm64: dts: marvell: Enumerate the first AP806 syscon
+
+There are two system controllers in the AP80x, like for ap_syscon1,
+enumerate the first one by renaming it s/ap_syscon/ap_syscon0/.
+
+Signed-off-by: Miquel Raynal <miquel.raynal at bootlin.com>
+Signed-off-by: Gregory CLEMENT <gregory.clement at bootlin.com>
+---
+ arch/arm64/boot/dts/marvell/armada-ap806.dtsi | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/arch/arm64/boot/dts/marvell/armada-ap806.dtsi
++++ b/arch/arm64/boot/dts/marvell/armada-ap806.dtsi
+@@ -246,7 +246,7 @@
+ status = "disabled";
+ };
+
+- ap_syscon: system-controller at 6f4000 {
++ ap_syscon0: system-controller at 6f4000 {
+ compatible = "syscon", "simple-mfd";
+ reg = <0x6f4000 0x2000>;
+
diff --git a/target/linux/mvebu/patches-5.4/008-v5.5-arm64-dts-marvell-Prepare-the-introduction-of-AP807-.patch b/target/linux/mvebu/patches-5.4/008-v5.5-arm64-dts-marvell-Prepare-the-introduction-of-AP807-.patch
new file mode 100644
index 0000000000..bb7863cb5f
--- /dev/null
+++ b/target/linux/mvebu/patches-5.4/008-v5.5-arm64-dts-marvell-Prepare-the-introduction-of-AP807-.patch
@@ -0,0 +1,937 @@
+From 7409b155562cc19b929b57692b334c5758ffc75d Mon Sep 17 00:00:00 2001
+From: Konstantin Porotchkin <kostap at marvell.com>
+Date: Fri, 4 Oct 2019 16:27:22 +0200
+Subject: [PATCH] arm64: dts: marvell: Prepare the introduction of AP807 based
+ SoCs
+
+Prepare the support for Marvell AP807 die. This die is very similar to
+AP806 but uses different DDR PHY. AP807 is a major component of CN9130
+SoC series.
+
+Signed-off-by: Konstantin Porotchkin <kostap at marvell.com>
+Signed-off-by: Miquel Raynal <miquel.raynal at bootlin.com>
+Signed-off-by: Gregory CLEMENT <gregory.clement at bootlin.com>
+---
+ arch/arm64/boot/dts/marvell/armada-ap806.dtsi | 448 +----------------
+ arch/arm64/boot/dts/marvell/armada-ap80x.dtsi | 456 ++++++++++++++++++
+ 2 files changed, 458 insertions(+), 446 deletions(-)
+ create mode 100644 arch/arm64/boot/dts/marvell/armada-ap80x.dtsi
+
+--- a/arch/arm64/boot/dts/marvell/armada-ap806.dtsi
++++ b/arch/arm64/boot/dts/marvell/armada-ap806.dtsi
+@@ -5,454 +5,10 @@
+ * Device Tree file for Marvell Armada AP806.
+ */
+
+-#include <dt-bindings/interrupt-controller/arm-gic.h>
+-#include <dt-bindings/thermal/thermal.h>
+-
+-/dts-v1/;
++#define AP_NAME ap806
++#include "armada-ap80x.dtsi"
+
+ / {
+ model = "Marvell Armada AP806";
+ compatible = "marvell,armada-ap806";
+- #address-cells = <2>;
+- #size-cells = <2>;
+-
+- aliases {
+- serial0 = &uart0;
+- serial1 = &uart1;
+- gpio0 = &ap_gpio;
+- spi0 = &spi0;
+- };
+-
+- psci {
+- compatible = "arm,psci-0.2";
+- method = "smc";
+- };
+-
+- reserved-memory {
+- #address-cells = <2>;
+- #size-cells = <2>;
+- ranges;
+-
+- /*
+- * This area matches the mapping done with a
+- * mainline U-Boot, and should be updated by the
+- * bootloader.
+- */
+-
+- psci-area at 4000000 {
+- reg = <0x0 0x4000000 0x0 0x200000>;
+- no-map;
+- };
+- };
+-
+- ap806 {
+- #address-cells = <2>;
+- #size-cells = <2>;
+- compatible = "simple-bus";
+- interrupt-parent = <&gic>;
+- ranges;
+-
+- config-space at f0000000 {
+- #address-cells = <1>;
+- #size-cells = <1>;
+- compatible = "simple-bus";
+- ranges = <0x0 0x0 0xf0000000 0x1000000>;
+-
+- gic: interrupt-controller at 210000 {
+- compatible = "arm,gic-400";
+- #interrupt-cells = <3>;
+- #address-cells = <1>;
+- #size-cells = <1>;
+- ranges;
+- interrupt-controller;
+- interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
+- reg = <0x210000 0x10000>,
+- <0x220000 0x20000>,
+- <0x240000 0x20000>,
+- <0x260000 0x20000>;
+-
+- gic_v2m0: v2m at 280000 {
+- compatible = "arm,gic-v2m-frame";
+- msi-controller;
+- reg = <0x280000 0x1000>;
+- arm,msi-base-spi = <160>;
+- arm,msi-num-spis = <32>;
+- };
+- gic_v2m1: v2m at 290000 {
+- compatible = "arm,gic-v2m-frame";
+- msi-controller;
+- reg = <0x290000 0x1000>;
+- arm,msi-base-spi = <192>;
+- arm,msi-num-spis = <32>;
+- };
+- gic_v2m2: v2m at 2a0000 {
+- compatible = "arm,gic-v2m-frame";
+- msi-controller;
+- reg = <0x2a0000 0x1000>;
+- arm,msi-base-spi = <224>;
+- arm,msi-num-spis = <32>;
+- };
+- gic_v2m3: v2m at 2b0000 {
+- compatible = "arm,gic-v2m-frame";
+- msi-controller;
+- reg = <0x2b0000 0x1000>;
+- arm,msi-base-spi = <256>;
+- arm,msi-num-spis = <32>;
+- };
+- };
+-
+- timer {
+- compatible = "arm,armv8-timer";
+- interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+- <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+- <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+- <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
+- };
+-
+- pmu {
+- compatible = "arm,cortex-a72-pmu";
+- interrupt-parent = <&pic>;
+- interrupts = <17>;
+- };
+-
+- odmi: odmi at 300000 {
+- compatible = "marvell,odmi-controller";
+- interrupt-controller;
+- msi-controller;
+- marvell,odmi-frames = <4>;
+- reg = <0x300000 0x4000>,
+- <0x304000 0x4000>,
+- <0x308000 0x4000>,
+- <0x30C000 0x4000>;
+- marvell,spi-base = <128>, <136>, <144>, <152>;
+- };
+-
+- gicp: gicp at 3f0040 {
+- compatible = "marvell,ap806-gicp";
+- reg = <0x3f0040 0x10>;
+- marvell,spi-ranges = <64 64>, <288 64>;
+- msi-controller;
+- };
+-
+- pic: interrupt-controller at 3f0100 {
+- compatible = "marvell,armada-8k-pic";
+- reg = <0x3f0100 0x10>;
+- #interrupt-cells = <1>;
+- interrupt-controller;
+- interrupts = <GIC_PPI 15 IRQ_TYPE_LEVEL_HIGH>;
+- };
+-
+- sei: interrupt-controller at 3f0200 {
+- compatible = "marvell,ap806-sei";
+- reg = <0x3f0200 0x40>;
+- interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
+- #interrupt-cells = <1>;
+- interrupt-controller;
+- msi-controller;
+- };
+-
+- xor at 400000 {
+- compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
+- reg = <0x400000 0x1000>,
+- <0x410000 0x1000>;
+- msi-parent = <&gic_v2m0>;
+- clocks = <&ap_clk 3>;
+- dma-coherent;
+- };
+-
+- xor at 420000 {
+- compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
+- reg = <0x420000 0x1000>,
+- <0x430000 0x1000>;
+- msi-parent = <&gic_v2m0>;
+- clocks = <&ap_clk 3>;
+- dma-coherent;
+- };
+-
+- xor at 440000 {
+- compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
+- reg = <0x440000 0x1000>,
+- <0x450000 0x1000>;
+- msi-parent = <&gic_v2m0>;
+- clocks = <&ap_clk 3>;
+- dma-coherent;
+- };
+-
+- xor at 460000 {
+- compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
+- reg = <0x460000 0x1000>,
+- <0x470000 0x1000>;
+- msi-parent = <&gic_v2m0>;
+- clocks = <&ap_clk 3>;
+- dma-coherent;
+- };
+-
+- spi0: spi at 510600 {
+- compatible = "marvell,armada-380-spi";
+- reg = <0x510600 0x50>;
+- #address-cells = <1>;
+- #size-cells = <0>;
+- interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
+- clocks = <&ap_clk 3>;
+- status = "disabled";
+- };
+-
+- i2c0: i2c at 511000 {
+- compatible = "marvell,mv78230-i2c";
+- reg = <0x511000 0x20>;
+- #address-cells = <1>;
+- #size-cells = <0>;
+- interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
+- timeout-ms = <1000>;
+- clocks = <&ap_clk 3>;
+- status = "disabled";
+- };
+-
+- uart0: serial at 512000 {
+- compatible = "snps,dw-apb-uart";
+- reg = <0x512000 0x100>;
+- reg-shift = <2>;
+- interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
+- reg-io-width = <1>;
+- clocks = <&ap_clk 3>;
+- status = "disabled";
+- };
+-
+- uart1: serial at 512100 {
+- compatible = "snps,dw-apb-uart";
+- reg = <0x512100 0x100>;
+- reg-shift = <2>;
+- interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
+- reg-io-width = <1>;
+- clocks = <&ap_clk 3>;
+- status = "disabled";
+-
+- };
+-
+- watchdog: watchdog at 610000 {
+- compatible = "arm,sbsa-gwdt";
+- reg = <0x610000 0x1000>, <0x600000 0x1000>;
+- interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
+- };
+-
+- ap_sdhci0: sdhci at 6e0000 {
+- compatible = "marvell,armada-ap806-sdhci";
+- reg = <0x6e0000 0x300>;
+- interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
+- clock-names = "core";
+- clocks = <&ap_clk 4>;
+- dma-coherent;
+- marvell,xenon-phy-slow-mode;
+- status = "disabled";
+- };
+-
+- ap_syscon0: system-controller at 6f4000 {
+- compatible = "syscon", "simple-mfd";
+- reg = <0x6f4000 0x2000>;
+-
+- ap_clk: clock {
+- compatible = "marvell,ap806-clock";
+- #clock-cells = <1>;
+- };
+-
+- ap_pinctrl: pinctrl {
+- compatible = "marvell,ap806-pinctrl";
+-
+- uart0_pins: uart0-pins {
+- marvell,pins = "mpp11", "mpp19";
+- marvell,function = "uart0";
+- };
+- };
+-
+- ap_gpio: gpio at 1040 {
+- compatible = "marvell,armada-8k-gpio";
+- offset = <0x1040>;
+- ngpios = <20>;
+- gpio-controller;
+- #gpio-cells = <2>;
+- gpio-ranges = <&ap_pinctrl 0 0 20>;
+- };
+- };
+-
+- ap_syscon1: system-controller at 6f8000 {
+- compatible = "syscon", "simple-mfd";
+- reg = <0x6f8000 0x1000>;
+- #address-cells = <1>;
+- #size-cells = <1>;
+-
+- cpu_clk: clock-cpu at 278 {
+- compatible = "marvell,ap806-cpu-clock";
+- clocks = <&ap_clk 0>, <&ap_clk 1>;
+- #clock-cells = <1>;
+- reg = <0x278 0xa30>;
+- };
+-
+- ap_thermal: thermal-sensor at 80 {
+- compatible = "marvell,armada-ap806-thermal";
+- reg = <0x80 0x10>;
+- interrupt-parent = <&sei>;
+- interrupts = <18>;
+- #thermal-sensor-cells = <1>;
+- };
+- };
+- };
+- };
+-
+- /*
+- * The thermal IP features one internal sensor plus, if applicable, one
+- * remote channel wired to one sensor per CPU.
+- *
+- * Only one thermal zone per AP/CP may trigger interrupts at a time, the
+- * first one that will have a critical trip point will be chosen.
+- */
+- thermal-zones {
+- ap_thermal_ic: ap-thermal-ic {
+- polling-delay-passive = <0>; /* Interrupt driven */
+- polling-delay = <0>; /* Interrupt driven */
+-
+- thermal-sensors = <&ap_thermal 0>;
+-
+- trips {
+- ap_crit: ap-crit {
+- temperature = <100000>; /* mC degrees */
+- hysteresis = <2000>; /* mC degrees */
+- type = "critical";
+- };
+- };
+-
+- cooling-maps { };
+- };
+-
+- ap_thermal_cpu0: ap-thermal-cpu0 {
+- polling-delay-passive = <1000>;
+- polling-delay = <1000>;
+-
+- thermal-sensors = <&ap_thermal 1>;
+-
+- trips {
+- cpu0_hot: cpu0-hot {
+- temperature = <85000>;
+- hysteresis = <2000>;
+- type = "passive";
+- };
+- cpu0_emerg: cpu0-emerg {
+- temperature = <95000>;
+- hysteresis = <2000>;
+- type = "passive";
+- };
+- };
+-
+- cooling-maps {
+- map0_hot: map0-hot {
+- trip = <&cpu0_hot>;
+- cooling-device = <&cpu0 1 2>,
+- <&cpu1 1 2>;
+- };
+- map0_emerg: map0-ermerg {
+- trip = <&cpu0_emerg>;
+- cooling-device = <&cpu0 3 3>,
+- <&cpu1 3 3>;
+- };
+- };
+- };
+-
+- ap_thermal_cpu1: ap-thermal-cpu1 {
+- polling-delay-passive = <1000>;
+- polling-delay = <1000>;
+-
+- thermal-sensors = <&ap_thermal 2>;
+-
+- trips {
+- cpu1_hot: cpu1-hot {
+- temperature = <85000>;
+- hysteresis = <2000>;
+- type = "passive";
+- };
+- cpu1_emerg: cpu1-emerg {
+- temperature = <95000>;
+- hysteresis = <2000>;
+- type = "passive";
+- };
+- };
+-
+- cooling-maps {
+- map1_hot: map1-hot {
+- trip = <&cpu1_hot>;
+- cooling-device = <&cpu0 1 2>,
+- <&cpu1 1 2>;
+- };
+- map1_emerg: map1-emerg {
+- trip = <&cpu1_emerg>;
+- cooling-device = <&cpu0 3 3>,
+- <&cpu1 3 3>;
+- };
+- };
+- };
+-
+- ap_thermal_cpu2: ap-thermal-cpu2 {
+- polling-delay-passive = <1000>;
+- polling-delay = <1000>;
+-
+- thermal-sensors = <&ap_thermal 3>;
+-
+- trips {
+- cpu2_hot: cpu2-hot {
+- temperature = <85000>;
+- hysteresis = <2000>;
+- type = "passive";
+- };
+- cpu2_emerg: cpu2-emerg {
+- temperature = <95000>;
+- hysteresis = <2000>;
+- type = "passive";
+- };
+- };
+-
+- cooling-maps {
+- map2_hot: map2-hot {
+- trip = <&cpu2_hot>;
+- cooling-device = <&cpu2 1 2>,
+- <&cpu3 1 2>;
+- };
+- map2_emerg: map2-emerg {
+- trip = <&cpu2_emerg>;
+- cooling-device = <&cpu2 3 3>,
+- <&cpu3 3 3>;
+- };
+- };
+- };
+-
+- ap_thermal_cpu3: ap-thermal-cpu3 {
+- polling-delay-passive = <1000>;
+- polling-delay = <1000>;
+-
+- thermal-sensors = <&ap_thermal 4>;
+-
+- trips {
+- cpu3_hot: cpu3-hot {
+- temperature = <85000>;
+- hysteresis = <2000>;
+- type = "passive";
+- };
+- cpu3_emerg: cpu3-emerg {
+- temperature = <95000>;
+- hysteresis = <2000>;
+- type = "passive";
+- };
+- };
+-
+- cooling-maps {
+- map3_hot: map3-bhot {
+- trip = <&cpu3_hot>;
+- cooling-device = <&cpu2 1 2>,
+- <&cpu3 1 2>;
+- };
+- map3_emerg: map3-emerg {
+- trip = <&cpu3_emerg>;
+- cooling-device = <&cpu2 3 3>,
+- <&cpu3 3 3>;
+- };
+- };
+- };
+- };
+ };
+--- /dev/null
++++ b/arch/arm64/boot/dts/marvell/armada-ap80x.dtsi
+@@ -0,0 +1,456 @@
++// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
++/*
++ * Copyright (C) 2019 Marvell Technology Group Ltd.
++ *
++ * Device Tree file for Marvell Armada AP80x.
++ */
++
++#include <dt-bindings/interrupt-controller/arm-gic.h>
++#include <dt-bindings/thermal/thermal.h>
++
++/dts-v1/;
++
++/ {
++ #address-cells = <2>;
++ #size-cells = <2>;
++
++ aliases {
++ serial0 = &uart0;
++ serial1 = &uart1;
++ gpio0 = &ap_gpio;
++ spi0 = &spi0;
++ };
++
++ psci {
++ compatible = "arm,psci-0.2";
++ method = "smc";
++ };
++
++ reserved-memory {
++ #address-cells = <2>;
++ #size-cells = <2>;
++ ranges;
++
++ /*
++ * This area matches the mapping done with a
++ * mainline U-Boot, and should be updated by the
++ * bootloader.
++ */
++
++ psci-area at 4000000 {
++ reg = <0x0 0x4000000 0x0 0x200000>;
++ no-map;
++ };
++ };
++
++ AP_NAME {
++ #address-cells = <2>;
++ #size-cells = <2>;
++ compatible = "simple-bus";
++ interrupt-parent = <&gic>;
++ ranges;
++
++ config-space at f0000000 {
++ #address-cells = <1>;
++ #size-cells = <1>;
++ compatible = "simple-bus";
++ ranges = <0x0 0x0 0xf0000000 0x1000000>;
++
++ gic: interrupt-controller at 210000 {
++ compatible = "arm,gic-400";
++ #interrupt-cells = <3>;
++ #address-cells = <1>;
++ #size-cells = <1>;
++ ranges;
++ interrupt-controller;
++ interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
++ reg = <0x210000 0x10000>,
++ <0x220000 0x20000>,
++ <0x240000 0x20000>,
++ <0x260000 0x20000>;
++
++ gic_v2m0: v2m at 280000 {
++ compatible = "arm,gic-v2m-frame";
++ msi-controller;
++ reg = <0x280000 0x1000>;
++ arm,msi-base-spi = <160>;
++ arm,msi-num-spis = <32>;
++ };
++ gic_v2m1: v2m at 290000 {
++ compatible = "arm,gic-v2m-frame";
++ msi-controller;
++ reg = <0x290000 0x1000>;
++ arm,msi-base-spi = <192>;
++ arm,msi-num-spis = <32>;
++ };
++ gic_v2m2: v2m at 2a0000 {
++ compatible = "arm,gic-v2m-frame";
++ msi-controller;
++ reg = <0x2a0000 0x1000>;
++ arm,msi-base-spi = <224>;
++ arm,msi-num-spis = <32>;
++ };
++ gic_v2m3: v2m at 2b0000 {
++ compatible = "arm,gic-v2m-frame";
++ msi-controller;
++ reg = <0x2b0000 0x1000>;
++ arm,msi-base-spi = <256>;
++ arm,msi-num-spis = <32>;
++ };
++ };
++
++ timer {
++ compatible = "arm,armv8-timer";
++ interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
++ <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
++ <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
++ <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
++ };
++
++ pmu {
++ compatible = "arm,cortex-a72-pmu";
++ interrupt-parent = <&pic>;
++ interrupts = <17>;
++ };
++
++ odmi: odmi at 300000 {
++ compatible = "marvell,odmi-controller";
++ interrupt-controller;
++ msi-controller;
++ marvell,odmi-frames = <4>;
++ reg = <0x300000 0x4000>,
++ <0x304000 0x4000>,
++ <0x308000 0x4000>,
++ <0x30C000 0x4000>;
++ marvell,spi-base = <128>, <136>, <144>, <152>;
++ };
++
++ gicp: gicp at 3f0040 {
++ compatible = "marvell,ap806-gicp";
++ reg = <0x3f0040 0x10>;
++ marvell,spi-ranges = <64 64>, <288 64>;
++ msi-controller;
++ };
++
++ pic: interrupt-controller at 3f0100 {
++ compatible = "marvell,armada-8k-pic";
++ reg = <0x3f0100 0x10>;
++ #interrupt-cells = <1>;
++ interrupt-controller;
++ interrupts = <GIC_PPI 15 IRQ_TYPE_LEVEL_HIGH>;
++ };
++
++ sei: interrupt-controller at 3f0200 {
++ compatible = "marvell,ap806-sei";
++ reg = <0x3f0200 0x40>;
++ interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
++ #interrupt-cells = <1>;
++ interrupt-controller;
++ msi-controller;
++ };
++
++ xor at 400000 {
++ compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
++ reg = <0x400000 0x1000>,
++ <0x410000 0x1000>;
++ msi-parent = <&gic_v2m0>;
++ clocks = <&ap_clk 3>;
++ dma-coherent;
++ };
++
++ xor at 420000 {
++ compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
++ reg = <0x420000 0x1000>,
++ <0x430000 0x1000>;
++ msi-parent = <&gic_v2m0>;
++ clocks = <&ap_clk 3>;
++ dma-coherent;
++ };
++
++ xor at 440000 {
++ compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
++ reg = <0x440000 0x1000>,
++ <0x450000 0x1000>;
++ msi-parent = <&gic_v2m0>;
++ clocks = <&ap_clk 3>;
++ dma-coherent;
++ };
++
++ xor at 460000 {
++ compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
++ reg = <0x460000 0x1000>,
++ <0x470000 0x1000>;
++ msi-parent = <&gic_v2m0>;
++ clocks = <&ap_clk 3>;
++ dma-coherent;
++ };
++
++ spi0: spi at 510600 {
++ compatible = "marvell,armada-380-spi";
++ reg = <0x510600 0x50>;
++ #address-cells = <1>;
++ #size-cells = <0>;
++ interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&ap_clk 3>;
++ status = "disabled";
++ };
++
++ i2c0: i2c at 511000 {
++ compatible = "marvell,mv78230-i2c";
++ reg = <0x511000 0x20>;
++ #address-cells = <1>;
++ #size-cells = <0>;
++ interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
++ timeout-ms = <1000>;
++ clocks = <&ap_clk 3>;
++ status = "disabled";
++ };
++
++ uart0: serial at 512000 {
++ compatible = "snps,dw-apb-uart";
++ reg = <0x512000 0x100>;
++ reg-shift = <2>;
++ interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
++ reg-io-width = <1>;
++ clocks = <&ap_clk 3>;
++ status = "disabled";
++ };
++
++ uart1: serial at 512100 {
++ compatible = "snps,dw-apb-uart";
++ reg = <0x512100 0x100>;
++ reg-shift = <2>;
++ interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
++ reg-io-width = <1>;
++ clocks = <&ap_clk 3>;
++ status = "disabled";
++
++ };
++
++ watchdog: watchdog at 610000 {
++ compatible = "arm,sbsa-gwdt";
++ reg = <0x610000 0x1000>, <0x600000 0x1000>;
++ interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
++ };
++
++ ap_sdhci0: sdhci at 6e0000 {
++ compatible = "marvell,armada-ap806-sdhci";
++ reg = <0x6e0000 0x300>;
++ interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
++ clock-names = "core";
++ clocks = <&ap_clk 4>;
++ dma-coherent;
++ marvell,xenon-phy-slow-mode;
++ status = "disabled";
++ };
++
++ ap_syscon0: system-controller at 6f4000 {
++ compatible = "syscon", "simple-mfd";
++ reg = <0x6f4000 0x2000>;
++
++ ap_clk: clock {
++ compatible = "marvell,ap806-clock";
++ #clock-cells = <1>;
++ };
++
++ ap_pinctrl: pinctrl {
++ compatible = "marvell,ap806-pinctrl";
++
++ uart0_pins: uart0-pins {
++ marvell,pins = "mpp11", "mpp19";
++ marvell,function = "uart0";
++ };
++ };
++
++ ap_gpio: gpio at 1040 {
++ compatible = "marvell,armada-8k-gpio";
++ offset = <0x1040>;
++ ngpios = <20>;
++ gpio-controller;
++ #gpio-cells = <2>;
++ gpio-ranges = <&ap_pinctrl 0 0 20>;
++ };
++ };
++
++ ap_syscon1: system-controller at 6f8000 {
++ compatible = "syscon", "simple-mfd";
++ reg = <0x6f8000 0x1000>;
++ #address-cells = <1>;
++ #size-cells = <1>;
++
++ cpu_clk: clock-cpu at 278 {
++ compatible = "marvell,ap806-cpu-clock";
++ clocks = <&ap_clk 0>, <&ap_clk 1>;
++ #clock-cells = <1>;
++ reg = <0x278 0xa30>;
++ };
++
++ ap_thermal: thermal-sensor at 80 {
++ compatible = "marvell,armada-ap806-thermal";
++ reg = <0x80 0x10>;
++ interrupt-parent = <&sei>;
++ interrupts = <18>;
++ #thermal-sensor-cells = <1>;
++ };
++ };
++ };
++ };
++
++ /*
++ * The thermal IP features one internal sensor plus, if applicable, one
++ * remote channel wired to one sensor per CPU.
++ *
++ * Only one thermal zone per AP/CP may trigger interrupts at a time, the
++ * first one that will have a critical trip point will be chosen.
++ */
++ thermal-zones {
++ ap_thermal_ic: ap-thermal-ic {
++ polling-delay-passive = <0>; /* Interrupt driven */
++ polling-delay = <0>; /* Interrupt driven */
++
++ thermal-sensors = <&ap_thermal 0>;
++
++ trips {
++ ap_crit: ap-crit {
++ temperature = <100000>; /* mC degrees */
++ hysteresis = <2000>; /* mC degrees */
++ type = "critical";
++ };
++ };
++
++ cooling-maps { };
++ };
++
++ ap_thermal_cpu0: ap-thermal-cpu0 {
++ polling-delay-passive = <1000>;
++ polling-delay = <1000>;
++
++ thermal-sensors = <&ap_thermal 1>;
++
++ trips {
++ cpu0_hot: cpu0-hot {
++ temperature = <85000>;
++ hysteresis = <2000>;
++ type = "passive";
++ };
++ cpu0_emerg: cpu0-emerg {
++ temperature = <95000>;
++ hysteresis = <2000>;
++ type = "passive";
++ };
++ };
++
++ cooling-maps {
++ map0_hot: map0-hot {
++ trip = <&cpu0_hot>;
++ cooling-device = <&cpu0 1 2>,
++ <&cpu1 1 2>;
++ };
++ map0_emerg: map0-ermerg {
++ trip = <&cpu0_emerg>;
++ cooling-device = <&cpu0 3 3>,
++ <&cpu1 3 3>;
++ };
++ };
++ };
++
++ ap_thermal_cpu1: ap-thermal-cpu1 {
++ polling-delay-passive = <1000>;
++ polling-delay = <1000>;
++
++ thermal-sensors = <&ap_thermal 2>;
++
++ trips {
++ cpu1_hot: cpu1-hot {
++ temperature = <85000>;
++ hysteresis = <2000>;
++ type = "passive";
++ };
++ cpu1_emerg: cpu1-emerg {
++ temperature = <95000>;
++ hysteresis = <2000>;
++ type = "passive";
++ };
++ };
++
++ cooling-maps {
++ map1_hot: map1-hot {
++ trip = <&cpu1_hot>;
++ cooling-device = <&cpu0 1 2>,
++ <&cpu1 1 2>;
++ };
++ map1_emerg: map1-emerg {
++ trip = <&cpu1_emerg>;
++ cooling-device = <&cpu0 3 3>,
++ <&cpu1 3 3>;
++ };
++ };
++ };
++
++ ap_thermal_cpu2: ap-thermal-cpu2 {
++ polling-delay-passive = <1000>;
++ polling-delay = <1000>;
++
++ thermal-sensors = <&ap_thermal 3>;
++
++ trips {
++ cpu2_hot: cpu2-hot {
++ temperature = <85000>;
++ hysteresis = <2000>;
++ type = "passive";
++ };
++ cpu2_emerg: cpu2-emerg {
++ temperature = <95000>;
++ hysteresis = <2000>;
++ type = "passive";
++ };
++ };
++
++ cooling-maps {
++ map2_hot: map2-hot {
++ trip = <&cpu2_hot>;
++ cooling-device = <&cpu2 1 2>,
++ <&cpu3 1 2>;
++ };
++ map2_emerg: map2-emerg {
++ trip = <&cpu2_emerg>;
++ cooling-device = <&cpu2 3 3>,
++ <&cpu3 3 3>;
++ };
++ };
++ };
++
++ ap_thermal_cpu3: ap-thermal-cpu3 {
++ polling-delay-passive = <1000>;
++ polling-delay = <1000>;
++
++ thermal-sensors = <&ap_thermal 4>;
++
++ trips {
++ cpu3_hot: cpu3-hot {
++ temperature = <85000>;
++ hysteresis = <2000>;
++ type = "passive";
++ };
++ cpu3_emerg: cpu3-emerg {
++ temperature = <95000>;
++ hysteresis = <2000>;
++ type = "passive";
++ };
++ };
++
++ cooling-maps {
++ map3_hot: map3-bhot {
++ trip = <&cpu3_hot>;
++ cooling-device = <&cpu2 1 2>,
++ <&cpu3 1 2>;
++ };
++ map3_emerg: map3-emerg {
++ trip = <&cpu3_emerg>;
++ cooling-device = <&cpu2 3 3>,
++ <&cpu3 3 3>;
++ };
++ };
++ };
++ };
++};
diff --git a/target/linux/mvebu/patches-5.4/009-v5.5-arm64-dts-marvell-Move-clocks-to-AP806-specific-file.patch b/target/linux/mvebu/patches-5.4/009-v5.5-arm64-dts-marvell-Move-clocks-to-AP806-specific-file.patch
new file mode 100644
index 0000000000..38965dd9e5
--- /dev/null
+++ b/target/linux/mvebu/patches-5.4/009-v5.5-arm64-dts-marvell-Move-clocks-to-AP806-specific-file.patch
@@ -0,0 +1,65 @@
+From 4f267f2a806b556678b84c4d80c2f4bff8d000d9 Mon Sep 17 00:00:00 2001
+From: Miquel Raynal <miquel.raynal at bootlin.com>
+Date: Fri, 4 Oct 2019 16:27:23 +0200
+Subject: [PATCH] arm64: dts: marvell: Move clocks to AP806 specific file
+
+Regular clocks and CPU clocks are specific to AP806, move them out of
+the generic AP80x file so that AP807 can use its own clocks.
+
+Signed-off-by: Miquel Raynal <miquel.raynal at bootlin.com>
+Signed-off-by: Gregory CLEMENT <gregory.clement at bootlin.com>
+---
+ arch/arm64/boot/dts/marvell/armada-ap806.dtsi | 16 ++++++++++++++++
+ arch/arm64/boot/dts/marvell/armada-ap80x.dtsi | 12 ------------
+ 2 files changed, 16 insertions(+), 12 deletions(-)
+
+--- a/arch/arm64/boot/dts/marvell/armada-ap806.dtsi
++++ b/arch/arm64/boot/dts/marvell/armada-ap806.dtsi
+@@ -12,3 +12,19 @@
+ model = "Marvell Armada AP806";
+ compatible = "marvell,armada-ap806";
+ };
++
++&ap_syscon0 {
++ ap_clk: clock {
++ compatible = "marvell,ap806-clock";
++ #clock-cells = <1>;
++ };
++};
++
++&ap_syscon1 {
++ cpu_clk: clock-cpu at 278 {
++ compatible = "marvell,ap806-cpu-clock";
++ clocks = <&ap_clk 0>, <&ap_clk 1>;
++ #clock-cells = <1>;
++ reg = <0x278 0xa30>;
++ };
++};
+--- a/arch/arm64/boot/dts/marvell/armada-ap80x.dtsi
++++ b/arch/arm64/boot/dts/marvell/armada-ap80x.dtsi
+@@ -248,11 +248,6 @@
+ compatible = "syscon", "simple-mfd";
+ reg = <0x6f4000 0x2000>;
+
+- ap_clk: clock {
+- compatible = "marvell,ap806-clock";
+- #clock-cells = <1>;
+- };
+-
+ ap_pinctrl: pinctrl {
+ compatible = "marvell,ap806-pinctrl";
+
+@@ -278,13 +273,6 @@
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+- cpu_clk: clock-cpu at 278 {
+- compatible = "marvell,ap806-cpu-clock";
+- clocks = <&ap_clk 0>, <&ap_clk 1>;
+- #clock-cells = <1>;
+- reg = <0x278 0xa30>;
+- };
+-
+ ap_thermal: thermal-sensor at 80 {
+ compatible = "marvell,armada-ap806-thermal";
+ reg = <0x80 0x10>;
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