[openwrt/openwrt] mvebu: add Globalscale MOCHAbin
LEDE Commits
lede-commits at lists.infradead.org
Sat Oct 2 08:40:29 PDT 2021
hauke pushed a commit to openwrt/openwrt.git, branch master:
https://git.openwrt.org/78cf3e53b1f4ea6428925302d78f743a693d5fb1
commit 78cf3e53b1f4ea6428925302d78f743a693d5fb1
Author: Robert Marko <robert.marko at sartura.hr>
AuthorDate: Mon Sep 27 23:14:51 2021 +0200
mvebu: add Globalscale MOCHAbin
Globalscale MOCHAbin is a Armada 7040 based development board.
Specifications:
* Armada 7040 Quad core ARMv8 Cortex A-72 @ 1.4GHz
* 2 / 4 / 8 GB of DDR4 DRAM
* 16 GB eMMC
* 4MB SPI-NOR (Bootloader)
* 1x M.2-2280 B-key socket (for SSD expansion, SATA3 only)
* 1x M.2-2250 B-key socket (for modems, USB2.0 and I2C only)
* 1x Mini-PCIe 3.0 (x1, USB2.0 and I2C)
* 1x SATA 7+15 socket (SATA3)
* 1x 16-pin (2×8) MikroBus Connector
* 1x SIM card slot (Connected to the mini-PCIe and both M.2 slots)
* 2x USB3.0 Type-A ports via SMSC USB5434B hub
* Cortex 2x5 JTAG
* microUSB port for UART (PL2303GL/PL2303SA onboard)
* 1x 10G SFP+
* 1x 1G SFP (Connected to 88E1512 PHY)
* 1x 1G RJ45 with PoE PD (Connected to 88E1512 PHY)
* 4x 1G RJ45 ports via Topaz 88E6141 switch
* RTC with battery holder (SoC provided, requires CR2032 battery)
* 1x 12V DC IN
* 1x Power switch
* 1x 12V fan header (3-pin, power only)
* 1x mini-PCIe LED header (2x0.1" pins)
* 1x M.2-2280 LED header (2x0.1" pins)
* 6x Bootstrap jumpers
* 1x Power LED (Green)
* 3x Tri-color RGB LEDs (Controllable)
* 1x Microchip ATECC608B secure element
Note that 1G SFP and 1G WAN cannot be used at the same time as they are in
parallel connected to the same PHY.
Installation:
Copy dtb from build_dir to bin/ and run tftpserver there:
$ cp ./build_dir/target-aarch64_cortex-a72_musl/linux-mvebu_cortexa72/image-armada-7040-mochabin.dtb bin/targets/mvebu/cortexa72/
$ in.tftpd -L -s bin/targets/mvebu/cortexa72/
Connect to the device UART via microUSB port and power on the device.
Power on the device and hit any key to stop the autoboot.
Set serverip (host IP) and ipaddr (any free IP address on the same subnet), e.g:
$ setenv serverip 192.168.1.10 # Host
$ setenv ipaddr 192.168.1.15 # Device
Set the ethernet device (Example for the 1G WAN):
$ setenv ethact mvpp2-2
Ping server to confirm network is working:
$ ping $serverip
Using mvpp2-2 device
host 192.168.1.15 is alive
Tftpboot the firmware:
$ tftpboot $kernel_addr_r openwrt-mvebu-cortexa72-globalscale_mochabin-initramfs-kernel.bin
$ tftpboot $fdt_addr_r image-armada-7040-mochabin.dtb
Boot the image:
$ booti $kernel_addr_r - $fdt_addr_r
Once the initramfs is booted, transfer openwrt-mvebu-cortexa72-globalscale_mochabin-squashfs-sdcard.img.gz
to /tmp dir on the device.
Gunzip and dd the image:
$ gunzip /tmp/openwrt-mvebu-cortexa72-globalscale_mochabin-squashfs-sdcard.img.gz
$ dd if=/tmp/openwrt-mvebu-cortexa72-globalscale_mochabin-squashfs-sdcard.img of=/dev/mmcblk0 && sync
Reboot the device.
Hit any key to stop the autoboot.
Reset U-boot env and set the bootcmd:
$ env default -a
$ setenv bootcmd 'load mmc 0 ${loadaddr} boot.scr && source ${loadaddr}'
Optionally I would advise to edit the console env variable to remove earlycon as that
causes the kernel to never use the driver for the serial console.
Earlycon should be used only for debugging before the kernel can configure the console
and will otherwise cause various issues with the console.
$ setenv console 'console=ttyS0,115200'
Save and reset
$ saveenv
$ reset
OpenWrt should boot from eMMC now.
Signed-off-by: Robert Marko <robert.marko at sartura.hr>
---
package/boot/uboot-envtools/files/mvebu | 3 +-
.../cortexa72/base-files/etc/board.d/02_network | 3 +
.../cortexa72/base-files/lib/upgrade/platform.sh | 3 +
target/linux/mvebu/cortexa72/config-5.10 | 7 +
.../boot/dts/marvell/armada-7040-mochabin.dts | 448 +++++++++++++++++++++
target/linux/mvebu/image/cortexa72.mk | 8 +
6 files changed, 471 insertions(+), 1 deletion(-)
diff --git a/package/boot/uboot-envtools/files/mvebu b/package/boot/uboot-envtools/files/mvebu
index 7136d5b4cd..cffd396ae1 100644
--- a/package/boot/uboot-envtools/files/mvebu
+++ b/package/boot/uboot-envtools/files/mvebu
@@ -33,7 +33,8 @@ globalscale,espressobin|\
globalscale,espressobin-emmc|\
globalscale,espressobin-ultra|\
globalscale,espressobin-v7|\
-globalscale,espressobin-v7-emmc)
+globalscale,espressobin-v7-emmc|\
+globalscale,mochabin)
idx="$(find_mtd_index u-boot-env)"
if [ -n "$idx" ]; then
ubootenv_add_uci_config "/dev/mtd$idx" "0x0" "0x10000" "0x10000" "1"
diff --git a/target/linux/mvebu/cortexa72/base-files/etc/board.d/02_network b/target/linux/mvebu/cortexa72/base-files/etc/board.d/02_network
index f185a88347..24a72f336a 100755
--- a/target/linux/mvebu/cortexa72/base-files/etc/board.d/02_network
+++ b/target/linux/mvebu/cortexa72/base-files/etc/board.d/02_network
@@ -10,6 +10,9 @@ board_config_update
board=$(board_name)
case "$board" in
+globalscale,mochabin)
+ ucidef_set_interfaces_lan_wan "lan0 lan1 lan2 lan3" "eth0 eth2"
+ ;;
iei,puzzle-m901)
ucidef_set_interfaces_lan_wan "eth1 eth2 eth3 eth4 eth5" "eth0"
;;
diff --git a/target/linux/mvebu/cortexa72/base-files/lib/upgrade/platform.sh b/target/linux/mvebu/cortexa72/base-files/lib/upgrade/platform.sh
index f5eb261d99..18fdb01959 100755
--- a/target/linux/mvebu/cortexa72/base-files/lib/upgrade/platform.sh
+++ b/target/linux/mvebu/cortexa72/base-files/lib/upgrade/platform.sh
@@ -9,6 +9,7 @@ REQUIRE_IMAGE_METADATA=1
platform_check_image() {
case "$(board_name)" in
+ globalscale,mochabin|\
iei,puzzle-m901|\
iei,puzzle-m902|\
marvell,armada8040-mcbin-doubleshot|\
@@ -27,6 +28,7 @@ platform_do_upgrade() {
iei,puzzle-m902)
platform_do_upgrade_emmc "$1"
;;
+ globalscale,mochabin|\
marvell,armada8040-mcbin-doubleshot|\
marvell,armada8040-mcbin-singleshot)
legacy_sdcard_do_upgrade "$1"
@@ -38,6 +40,7 @@ platform_do_upgrade() {
}
platform_copy_config() {
case "$(board_name)" in
+ globalscale,mochabin|\
iei,puzzle-m901|\
iei,puzzle-m902|\
marvell,armada8040-mcbin-doubleshot|\
diff --git a/target/linux/mvebu/cortexa72/config-5.10 b/target/linux/mvebu/cortexa72/config-5.10
index 1d8affc290..c8b216fca5 100644
--- a/target/linux/mvebu/cortexa72/config-5.10
+++ b/target/linux/mvebu/cortexa72/config-5.10
@@ -33,6 +33,8 @@ CONFIG_ARM_PSCI_FW=y
CONFIG_AUDIT_ARCH_COMPAT_GENERIC=y
# CONFIG_CAVIUM_TX2_ERRATUM_219 is not set
CONFIG_CC_HAVE_STACKPROTECTOR_SYSREG=y
+CONFIG_CRYPTO_GF128MUL=y
+CONFIG_CRYPTO_ZSTD=y
CONFIG_DMA_DIRECT_REMAP=y
# CONFIG_FLATMEM_MANUAL is not set
CONFIG_FRAME_POINTER=y
@@ -44,7 +46,9 @@ CONFIG_GENERIC_PINCONF=y
CONFIG_HOLES_IN_ZONE=y
CONFIG_HW_RANDOM_OMAP=y
CONFIG_ILLEGAL_POINTER_VALUE=0xdead000000000000
+CONFIG_LEDS_IS31FL319X=y
CONFIG_MARVELL_10G_PHY=y
+CONFIG_MDIO_DEVRES=y
CONFIG_MFD_SYSCON=y
CONFIG_MMC_SDHCI_XENON=y
CONFIG_MODULES_USE_ELF_RELA=y
@@ -87,4 +91,7 @@ CONFIG_SYS_SUPPORTS_HUGETLBFS=y
CONFIG_THREAD_INFO_IN_TASK=y
CONFIG_UNMAP_KERNEL_AT_EL0=y
CONFIG_VMAP_STACK=y
+CONFIG_XXHASH=y
CONFIG_ZONE_DMA32=y
+CONFIG_ZSTD_COMPRESS=y
+CONFIG_ZSTD_DECOMPRESS=y
diff --git a/target/linux/mvebu/files/arch/arm64/boot/dts/marvell/armada-7040-mochabin.dts b/target/linux/mvebu/files/arch/arm64/boot/dts/marvell/armada-7040-mochabin.dts
new file mode 100644
index 0000000000..63f4fd5a69
--- /dev/null
+++ b/target/linux/mvebu/files/arch/arm64/boot/dts/marvell/armada-7040-mochabin.dts
@@ -0,0 +1,448 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/*
+ * Device Tree file for Globalscale MOCHAbin
+ * Copyright (C) 2019 Globalscale technologies, Inc.
+ * Copyright (C) 2021 Sartura Ltd.
+ *
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include "armada-7040.dtsi"
+
+/ {
+ model = "Globalscale MOCHAbin";
+ compatible = "globalscale,mochabin", "marvell,armada7040",
+ "marvell,armada-ap806-quad", "marvell,armada-ap806";
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ aliases {
+ ethernet0 = &cp0_eth0;
+ ethernet1 = &cp0_eth1;
+ ethernet2 = &cp0_eth2;
+ ethernet3 = &swport1;
+ ethernet4 = &swport2;
+ ethernet5 = &swport3;
+ ethernet6 = &swport4;
+ };
+
+ /* SFP+ 10G */
+ sfp_eth0: sfp-eth0 {
+ compatible = "sff,sfp";
+ i2c-bus = <&cp0_i2c1>;
+ los-gpio = <&sfp_gpio 3 GPIO_ACTIVE_HIGH>;
+ mod-def0-gpio = <&sfp_gpio 2 GPIO_ACTIVE_LOW>;
+ tx-disable-gpio = <&sfp_gpio 1 GPIO_ACTIVE_HIGH>;
+ tx-fault-gpio = <&sfp_gpio 0 GPIO_ACTIVE_HIGH>;
+ };
+
+ /* SFP 1G */
+ sfp_eth2: sfp-eth2 {
+ compatible = "sff,sfp";
+ i2c-bus = <&cp0_i2c0>;
+ los-gpio = <&sfp_gpio 7 GPIO_ACTIVE_HIGH>;
+ mod-def0-gpio = <&sfp_gpio 6 GPIO_ACTIVE_LOW>;
+ tx-disable-gpio = <&sfp_gpio 5 GPIO_ACTIVE_HIGH>;
+ tx-fault-gpio = <&sfp_gpio 4 GPIO_ACTIVE_HIGH>;
+ };
+};
+
+/* microUSB UART console */
+&uart0 {
+ status = "okay";
+
+ pinctrl-0 = <&uart0_pins>;
+ pinctrl-names = "default";
+};
+
+/* eMMC */
+&ap_sdhci0 {
+ status = "okay";
+
+ bus-width = <4>;
+ non-removable;
+ /delete-property/ marvell,xenon-phy-slow-mode;
+ no-1-8-v;
+};
+
+&cp0_pinctrl {
+ cp0_uart0_pins: cp0-uart0-pins {
+ marvell,pins = "mpp6", "mpp7";
+ marvell,function = "uart0";
+ };
+
+ cp0_spi0_pins: cp0-spi0-pins {
+ marvell,pins = "mpp56", "mpp57", "mpp58", "mpp59";
+ marvell,function = "spi0";
+ };
+
+ cp0_spi1_pins: cp0-spi1-pins {
+ marvell,pins = "mpp13", "mpp14", "mpp15", "mpp16";
+ marvell,function = "spi1";
+ };
+
+ cp0_i2c0_pins: cp0-i2c0-pins {
+ marvell,pins = "mpp37", "mpp38";
+ marvell,function = "i2c0";
+ };
+
+ cp0_i2c1_pins: cp0-i2c1-pins {
+ marvell,pins = "mpp2", "mpp3";
+ marvell,function = "i2c1";
+ };
+
+ pca9554_int_pins: pca9554-int-pins {
+ marvell,pins = "mpp27";
+ marvell,function = "gpio";
+ };
+
+ cp0_rgmii1_pins: cp0-rgmii1-pins {
+ marvell,pins = "mpp44", "mpp45", "mpp46", "mpp47", "mpp48", "mpp49",
+ "mpp50", "mpp51", "mpp52", "mpp53", "mpp54", "mpp55";
+ marvell,function = "ge1";
+ };
+
+ is31_sdb_pins: is31-sdb-pins {
+ marvell,pins = "mpp30";
+ marvell,function = "gpio";
+ };
+
+ cp0_pcie_reset_pins: cp0-pcie-reset-pins {
+ marvell,pins = "mpp9";
+ marvell,function = "gpio";
+ };
+
+ cp0_switch_pins: cp0-switch-pins {
+ marvell,pins = "mpp0", "mpp1";
+ marvell,function = "gpio";
+ };
+
+ cp0_phy_pins: cp0-phy-pins {
+ marvell,pins = "mpp12";
+ marvell,function = "gpio";
+ };
+};
+
+/* mikroBUS UART */
+&cp0_uart0 {
+ status = "okay";
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&cp0_uart0_pins>;
+};
+
+/* mikroBUS SPI */
+&cp0_spi0 {
+ status = "okay";
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&cp0_spi0_pins>;
+};
+
+/* SPI-NOR */
+&cp0_spi1{
+ status = "okay";
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&cp0_spi1_pins>;
+
+ spi-flash at 0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <20000000>;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition at 0 {
+ label = "u-boot";
+ reg = <0x0 0x3e0000>;
+ read-only;
+ };
+
+ partition at 3e0000 {
+ label = "hw-info";
+ reg = <0x3e0000 0x10000>;
+ read-only;
+ };
+
+ partition at 3f0000 {
+ label = "u-boot-env";
+ reg = <0x3f0000 0x10000>;
+ };
+ };
+ };
+};
+
+/* mikroBUS, 1G SFP and GPIO expander */
+&cp0_i2c0 {
+ status = "okay";
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&cp0_i2c0_pins>;
+ clock-frequency = <100000>;
+
+ sfp_gpio: pca9554 at 39 {
+ compatible = "nxp,pca9554";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pca9554_int_pins>;
+ reg = <0x39>;
+
+ interrupt-parent = <&cp0_gpio1>;
+ interrupts = <27 IRQ_TYPE_LEVEL_LOW>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ /*
+ * IO0_0: SFP+_TX_FAULT
+ * IO0_1: SFP+_TX_DISABLE
+ * IO0_2: SFP+_PRSNT
+ * IO0_3: SFP+_LOSS
+ * IO0_4: SFP_TX_FAULT
+ * IO0_5: SFP_TX_DISABLE
+ * IO0_6: SFP_PRSNT
+ * IO0_7: SFP_LOSS
+ */
+ };
+};
+
+/* IS31FL3199, mini-PCIe and 10G SFP+ */
+&cp0_i2c1 {
+ status = "okay";
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&cp0_i2c1_pins>;
+ clock-frequency = <100000>;
+
+ leds at 64 {
+ compatible = "issi,is31fl3199";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&is31_sdb_pins>;
+ shutdown-gpios = <&cp0_gpio1 30 GPIO_ACTIVE_HIGH>;
+ reg = <0x64>;
+
+ led1_red: led at 1 {
+ label = "led1:red";
+ reg = <1>;
+ led-max-microamp = <20000>;
+ };
+
+ led1_green: led at 2 {
+ label = "led1:green";
+ reg = <2>;
+ };
+
+ led1_blue: led at 3 {
+ label = "led1:blue";
+ reg = <3>;
+ };
+
+ led2_red: led at 4 {
+ label = "led2:red";
+ reg = <4>;
+ };
+
+ led2_green: led at 5 {
+ label = "led2:green";
+ reg = <5>;
+ };
+
+ led2_blue: led at 6 {
+ label = "led2:blue";
+ reg = <6>;
+ };
+
+ led3_red: led at 7 {
+ label = "led3:red";
+ reg = <7>;
+ };
+
+ led3_green: led at 8 {
+ label = "led3:green";
+ reg = <8>;
+ };
+
+ led3_blue: led at 9 {
+ label = "led3:blue";
+ reg = <9>;
+ };
+ };
+};
+
+&cp0_mdio {
+ status = "okay";
+
+ /* 88E1512 PHY */
+ eth2phy: ethernet-phy at 1 {
+ reg = <1>;
+ sfp = <&sfp_eth2>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&cp0_phy_pins>;
+ reset-gpios = <&cp0_gpio1 12 GPIO_ACTIVE_LOW>;
+ };
+
+ /* 88E6141 Topaz switch */
+ switch: switch at 3 {
+ compatible = "marvell,mv88e6085";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <3>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&cp0_switch_pins>;
+ reset-gpios = <&cp0_gpio1 0 GPIO_ACTIVE_LOW>;
+
+ interrupt-parent = <&cp0_gpio1>;
+ interrupts = <1 IRQ_TYPE_LEVEL_LOW>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ swport1: port at 1 {
+ reg = <1>;
+ label = "lan0";
+ phy-handle = <&swphy1>;
+ };
+
+ swport2: port at 2 {
+ reg = <2>;
+ label = "lan1";
+ phy-handle = <&swphy2>;
+ };
+
+ swport3: port at 3 {
+ reg = <3>;
+ label = "lan2";
+ phy-handle = <&swphy3>;
+ };
+
+ swport4: port at 4 {
+ reg = <4>;
+ label = "lan3";
+ phy-handle = <&swphy4>;
+ };
+
+ port at 5 {
+ reg = <5>;
+ label = "cpu";
+ ethernet = <&cp0_eth1>;
+ phy-mode = "2500base-x";
+ managed = "in-band-status";
+ };
+ };
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ swphy1: swphy1 at 17 {
+ reg = <17>;
+ };
+
+ swphy2: swphy2 at 18 {
+ reg = <18>;
+ };
+
+ swphy3: swphy3 at 19 {
+ reg = <19>;
+ };
+
+ swphy4: swphy4 at 20 {
+ reg = <20>;
+ };
+ };
+ };
+};
+
+&cp0_ethernet {
+ status = "okay";
+};
+
+/* 10G SFP+ */
+&cp0_eth0 {
+ status = "okay";
+
+ phy-mode = "10gbase-r";
+ phys = <&cp0_comphy4 0>;
+ managed = "in-band-status";
+ sfp = <&sfp_eth0>;
+};
+
+/* Topaz switch uplink */
+&cp0_eth1 {
+ status = "okay";
+
+ phy-mode = "2500base-x";
+ phys = <&cp0_comphy0 1>;
+
+ fixed-link {
+ speed = <2500>;
+ full-duplex;
+ };
+};
+
+/* 1G SFP or 1G RJ45 */
+&cp0_eth2 {
+ status = "okay";
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&cp0_rgmii1_pins>;
+
+ phy = <ð2phy>;
+ phy-mode = "rgmii-id";
+};
+
+/* SMSC USB5434B hub */
+&cp0_usb3_0 {
+ status = "okay";
+
+ phys = <&cp0_comphy1 0>;
+ phy-names = "cp0-usb3h0-comphy";
+};
+
+/* miniPCI-E USB */
+&cp0_usb3_1 {
+ status = "okay";
+};
+
+&cp0_sata0 {
+ status = "okay";
+
+ /* 7 + 12 SATA connector (J24) */
+ sata-port at 0 {
+ phys = <&cp0_comphy2 0>;
+ phy-names = "cp0-sata0-0-phy";
+ };
+
+ /* M.2-2250 B-key (J39) */
+ sata-port at 1 {
+ phys = <&cp0_comphy3 1>;
+ phy-names = "cp0-sata0-1-phy";
+ };
+};
+
+/* miniPCI-E (J5) */
+&cp0_pcie2 {
+ status = "okay";
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&cp0_pcie_reset_pins>;
+ phys = <&cp0_comphy5 2>;
+ phy-names = "cp0-pcie2-x1-phy";
+ reset-gpio = <&cp0_gpio1 9 GPIO_ACTIVE_LOW>;
+};
diff --git a/target/linux/mvebu/image/cortexa72.mk b/target/linux/mvebu/image/cortexa72.mk
index 29727f8b9d..f95ce533ea 100644
--- a/target/linux/mvebu/image/cortexa72.mk
+++ b/target/linux/mvebu/image/cortexa72.mk
@@ -1,3 +1,11 @@
+define Device/globalscale_mochabin
+ $(call Device/Default-arm64)
+ DEVICE_VENDOR := Globalscale
+ DEVICE_MODEL := MOCHAbin
+ SOC := armada-7040
+endef
+TARGET_DEVICES += globalscale_mochabin
+
define Device/marvell_armada7040-db
$(call Device/Default-arm64)
DEVICE_VENDOR := Marvell
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