[openwrt/openwrt] ipq806x: add GSBI nodes to ipq8064-dtsi-addidions
LEDE Commits
lede-commits at lists.infradead.org
Sun Nov 28 09:48:31 PST 2021
hauke pushed a commit to openwrt/openwrt.git, branch master:
https://git.openwrt.org/cef420e8f75206725d94723e0b8a9d14f2a55a20
commit cef420e8f75206725d94723e0b8a9d14f2a55a20
Author: Matthew Hagan <mnhagan88 at gmail.com>
AuthorDate: Thu May 20 20:55:06 2021 +0100
ipq806x: add GSBI nodes to ipq8064-dtsi-addidions
Rather than having separate patches for each GSBI node added, this patch
consolidates the existing GSBI1 patch into
083-ipq8064-dtsi-additions.patch. In addition, GSBI6 and GSBI7 I2C nodes,
required for the MR42 and MR52 respectively, are added.
Signed-off-by: Matthew Hagan <mnhagan88 at gmail.com>
---
.../patches-5.10/083-ipq8064-dtsi-additions.patch | 97 +++++++++++++++++++++-
...03-ARM-dts-qcom-reduce-pci-IO-size-to-64K.patch | 6 +-
.../ipq806x/patches-5.10/851-add-gsbi1-dts.patch | 44 ----------
3 files changed, 96 insertions(+), 51 deletions(-)
diff --git a/target/linux/ipq806x/patches-5.10/083-ipq8064-dtsi-additions.patch b/target/linux/ipq806x/patches-5.10/083-ipq8064-dtsi-additions.patch
index 1ebce10600..e6f2027e22 100644
--- a/target/linux/ipq806x/patches-5.10/083-ipq8064-dtsi-additions.patch
+++ b/target/linux/ipq806x/patches-5.10/083-ipq8064-dtsi-additions.patch
@@ -563,7 +563,7 @@
saw0: regulator at 2089000 {
compatible = "qcom,saw2", "qcom,apq8064-saw2-v1.1-cpu", "syscon";
reg = <0x02089000 0x1000>, <0x02009000 0x1000>;
-@@ -243,6 +739,17 @@
+@@ -243,6 +739,52 @@
regulator;
};
@@ -577,11 +577,100 @@
+ compatible = "syscon";
+ reg = <0x12100000 0x10000>;
+ };
++
++ gsbi1: gsbi at 12440000 {
++ compatible = "qcom,gsbi-v1.0.0";
++ cell-index = <1>;
++ reg = <0x12440000 0x100>;
++ clocks = <&gcc GSBI1_H_CLK>;
++ clock-names = "iface";
++ #address-cells = <1>;
++ #size-cells = <1>;
++ ranges;
++ status = "disabled";
++
++ syscon-tcsr = <&tcsr>;
++
++ gsbi1_serial: serial at 12450000 {
++ compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
++ reg = <0x12450000 0x100>,
++ <0x12400000 0x03>;
++ interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&gcc GSBI1_UART_CLK>, <&gcc GSBI1_H_CLK>;
++ clock-names = "core", "iface";
++ status = "disabled";
++ };
++
++ gsbi1_i2c: i2c at 12460000 {
++ compatible = "qcom,i2c-qup-v1.1.1";
++ reg = <0x12460000 0x1000>;
++ interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&gcc GSBI1_QUP_CLK>, <&gcc GSBI1_H_CLK>;
++ clock-names = "core", "iface";
++ #address-cells = <1>;
++ #size-cells = <0>;
++ status = "disabled";
++ };
++ };
+
gsbi2: gsbi at 12480000 {
compatible = "qcom,gsbi-v1.0.0";
cell-index = <2>;
-@@ -478,6 +985,95 @@
+@@ -368,6 +910,33 @@
+ };
+ };
+
++ gsbi6: gsbi at 16500000 {
++ status = "disabled";
++ compatible = "qcom,gsbi-v1.0.0";
++ cell-index = <6>;
++ reg = <0x16500000 0x100>;
++ clocks = <&gcc GSBI6_H_CLK>;
++ clock-names = "iface";
++ #address-cells = <1>;
++ #size-cells = <1>;
++ ranges;
++
++ syscon-tcsr = <&tcsr>;
++
++ gsbi6_i2c: i2c at 16580000 {
++ compatible = "qcom,i2c-qup-v1.1.1";
++ reg = <0x16580000 0x1000>;
++ interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
++
++ clocks = <&gcc GSBI6_QUP_CLK>, <&gcc GSBI6_H_CLK>;
++ clock-names = "core", "iface";
++ status = "disabled";
++
++ #address-cells = <1>;
++ #size-cells = <0>;
++ };
++ };
++
+ gsbi7: gsbi at 16600000 {
+ status = "disabled";
+ compatible = "qcom,gsbi-v1.0.0";
+@@ -389,6 +958,19 @@
+ clock-names = "core", "iface";
+ status = "disabled";
+ };
++
++ gsbi7_i2c: i2c at 16680000 {
++ compatible = "qcom,i2c-qup-v1.1.1";
++ reg = <0x16680000 0x1000>;
++ interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
++
++ clocks = <&gcc GSBI7_QUP_CLK>, <&gcc GSBI7_H_CLK>;
++ clock-names = "core", "iface";
++ status = "disabled";
++
++ #address-cells = <1>;
++ #size-cells = <0>;
++ };
+ };
+
+ sata_phy: sata-phy at 1b400000 {
+@@ -478,6 +1060,95 @@
#reset-cells = <1>;
};
@@ -677,7 +766,7 @@
pcie0: pci at 1b500000 {
compatible = "qcom,pcie-ipq8064";
reg = <0x1b500000 0x1000
-@@ -739,6 +1335,59 @@
+@@ -739,6 +1410,59 @@
status = "disabled";
};
@@ -737,7 +826,7 @@
vsdcc_fixed: vsdcc-regulator {
compatible = "regulator-fixed";
regulator-name = "SDCC Power";
-@@ -814,4 +1463,17 @@
+@@ -814,4 +1538,17 @@
};
};
};
diff --git a/target/linux/ipq806x/patches-5.10/103-ARM-dts-qcom-reduce-pci-IO-size-to-64K.patch b/target/linux/ipq806x/patches-5.10/103-ARM-dts-qcom-reduce-pci-IO-size-to-64K.patch
index 4020d9d2de..75b53234ab 100644
--- a/target/linux/ipq806x/patches-5.10/103-ARM-dts-qcom-reduce-pci-IO-size-to-64K.patch
+++ b/target/linux/ipq806x/patches-5.10/103-ARM-dts-qcom-reduce-pci-IO-size-to-64K.patch
@@ -17,7 +17,7 @@ Signed-off-by: Ansuel Smith <ansuelsmth at gmail.com>
--- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
-@@ -1088,7 +1088,7 @@
+@@ -1163,7 +1163,7 @@
#address-cells = <3>;
#size-cells = <2>;
@@ -26,7 +26,7 @@ Signed-off-by: Ansuel Smith <ansuelsmth at gmail.com>
0x82000000 0 0x08000000 0x08000000 0 0x07e00000>; /* non-prefetchable memory */
interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
-@@ -1139,7 +1139,7 @@
+@@ -1214,7 +1214,7 @@
#address-cells = <3>;
#size-cells = <2>;
@@ -35,7 +35,7 @@ Signed-off-by: Ansuel Smith <ansuelsmth at gmail.com>
0x82000000 0 0x2e000000 0x2e000000 0 0x03e00000>; /* non-prefetchable memory */
interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
-@@ -1190,7 +1190,7 @@
+@@ -1265,7 +1265,7 @@
#address-cells = <3>;
#size-cells = <2>;
diff --git a/target/linux/ipq806x/patches-5.10/851-add-gsbi1-dts.patch b/target/linux/ipq806x/patches-5.10/851-add-gsbi1-dts.patch
deleted file mode 100644
index e6ee9a93fc..0000000000
--- a/target/linux/ipq806x/patches-5.10/851-add-gsbi1-dts.patch
+++ /dev/null
@@ -1,44 +0,0 @@
---- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
-+++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
-@@ -750,6 +750,41 @@
- reg = <0x12100000 0x10000>;
- };
-
-+ gsbi1: gsbi at 12440000 {
-+ compatible = "qcom,gsbi-v1.0.0";
-+ cell-index = <1>;
-+ reg = <0x12440000 0x100>;
-+ clocks = <&gcc GSBI1_H_CLK>;
-+ clock-names = "iface";
-+ #address-cells = <1>;
-+ #size-cells = <1>;
-+ ranges;
-+ status = "disabled";
-+
-+ syscon-tcsr = <&tcsr>;
-+
-+ gsbi1_serial: serial at 12450000 {
-+ compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
-+ reg = <0x12450000 0x100>,
-+ <0x12400000 0x03>;
-+ interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
-+ clocks = <&gcc GSBI1_UART_CLK>, <&gcc GSBI1_H_CLK>;
-+ clock-names = "core", "iface";
-+ status = "disabled";
-+ };
-+
-+ gsbi1_i2c: i2c at 12460000 {
-+ compatible = "qcom,i2c-qup-v1.1.1";
-+ reg = <0x12460000 0x1000>;
-+ interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>;
-+ clocks = <&gcc GSBI1_QUP_CLK>, <&gcc GSBI1_H_CLK>;
-+ clock-names = "core", "iface";
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+ status = "disabled";
-+ };
-+ };
-+
- gsbi2: gsbi at 12480000 {
- compatible = "qcom,gsbi-v1.0.0";
- cell-index = <2>;
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