[openwrt/openwrt] uboot-rockchip: update to v2021.01
LEDE Commits
lede-commits at lists.infradead.org
Wed Jan 13 19:04:54 EST 2021
blocktrron pushed a commit to openwrt/openwrt.git, branch master:
https://git.openwrt.org/d567a24200fcc08c251d4ff801accdb5bf6519a1
commit d567a24200fcc08c251d4ff801accdb5bf6519a1
Author: Marty Jones <mj8263788 at gmail.com>
AuthorDate: Mon Jan 11 18:35:29 2021 -0500
uboot-rockchip: update to v2021.01
Update the U-Boot to version v2021.01.
Run-tested: FriendlyARM NanoPi R2S
Radxa Rock Pi 4
Pine64 RockPro64
Signed-off-by: Marty Jones <mj8263788 at gmail.com>
[format commit message]
Signed-off-by: David Bauer <mail at david-bauer.net>
---
package/boot/uboot-rockchip/Makefile | 6 +-
.../002-spl-remove-dtoc-of-pdata-generation.patch | 2 +-
...3328-Add-support-for-FriendlyARM-NanoPi-R.patch | 2 +-
.../of-platdata/nanopi-r2s-rk3328/dt-platdata.c | 181 ++++++++++++---------
.../of-platdata/nanopi-r2s-rk3328/dt-structs-gen.h | 47 +++---
5 files changed, 127 insertions(+), 111 deletions(-)
diff --git a/package/boot/uboot-rockchip/Makefile b/package/boot/uboot-rockchip/Makefile
index 944c942efc..393e8c3a9f 100644
--- a/package/boot/uboot-rockchip/Makefile
+++ b/package/boot/uboot-rockchip/Makefile
@@ -5,10 +5,10 @@
include $(TOPDIR)/rules.mk
include $(INCLUDE_DIR)/kernel.mk
-PKG_VERSION:=2020.07
-PKG_RELEASE:=3
+PKG_VERSION:=2021.01
+PKG_RELEASE:=1
-PKG_HASH:=c1f5bf9ee6bb6e648edbf19ce2ca9452f614b08a9f886f1a566aa42e8cf05f6a
+PKG_HASH:=b407e1510a74e863b8b5cb42a24625344f0e0c2fc7582d8c866bd899367d0454
PKG_MAINTAINER:=Tobias Maedel <openwrt at tbspace.de>
diff --git a/package/boot/uboot-rockchip/patches/002-spl-remove-dtoc-of-pdata-generation.patch b/package/boot/uboot-rockchip/patches/002-spl-remove-dtoc-of-pdata-generation.patch
index 4161c46ce2..bd401103ea 100644
--- a/package/boot/uboot-rockchip/patches/002-spl-remove-dtoc-of-pdata-generation.patch
+++ b/package/boot/uboot-rockchip/patches/002-spl-remove-dtoc-of-pdata-generation.patch
@@ -17,7 +17,7 @@ Signed-off-by: David Bauer <mail at david-bauer.net>
--- a/scripts/Makefile.spl
+++ b/scripts/Makefile.spl
-@@ -320,12 +320,6 @@ PHONY += dts_dir
+@@ -321,12 +321,6 @@ PHONY += dts_dir
dts_dir:
$(shell [ -d $(obj)/dts ] || mkdir -p $(obj)/dts)
diff --git a/package/boot/uboot-rockchip/patches/100-rockchip-rk3328-Add-support-for-FriendlyARM-NanoPi-R.patch b/package/boot/uboot-rockchip/patches/100-rockchip-rk3328-Add-support-for-FriendlyARM-NanoPi-R.patch
index bc65fb69ef..f2f63d8e36 100644
--- a/package/boot/uboot-rockchip/patches/100-rockchip-rk3328-Add-support-for-FriendlyARM-NanoPi-R.patch
+++ b/package/boot/uboot-rockchip/patches/100-rockchip-rk3328-Add-support-for-FriendlyARM-NanoPi-R.patch
@@ -28,7 +28,7 @@ Signed-off-by: David Bauer <mail at david-bauer.net>
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
-@@ -106,6 +106,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3308) += \
+@@ -110,6 +110,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3308) += \
dtb-$(CONFIG_ROCKCHIP_RK3328) += \
rk3328-evb.dtb \
diff --git a/package/boot/uboot-rockchip/src/of-platdata/nanopi-r2s-rk3328/dt-platdata.c b/package/boot/uboot-rockchip/src/of-platdata/nanopi-r2s-rk3328/dt-platdata.c
index fa42c1a760..cf9411116b 100644
--- a/package/boot/uboot-rockchip/src/of-platdata/nanopi-r2s-rk3328/dt-platdata.c
+++ b/package/boot/uboot-rockchip/src/of-platdata/nanopi-r2s-rk3328/dt-platdata.c
@@ -4,20 +4,15 @@
* This file was generated by dtoc from a .dtb (device tree binary) file.
*/
+/* Allow use of U_BOOT_DEVICE() in this file */
+#define DT_PLATDATA_C
+
#include <common.h>
#include <dm.h>
#include <dt-structs.h>
-static const struct dtd_rockchip_rk3328_grf dtv_syscon_at_ff100000 = {
- .reg = {0xff100000, 0x1000},
-};
-U_BOOT_DEVICE(syscon_at_ff100000) = {
- .name = "rockchip_rk3328_grf",
- .platdata = &dtv_syscon_at_ff100000,
- .platdata_size = sizeof(dtv_syscon_at_ff100000),
-};
-
-static const struct dtd_rockchip_rk3328_cru dtv_clock_controller_at_ff440000 = {
+/* Node /clock-controller at ff440000 index 0 */
+static struct dtd_rockchip_rk3328_cru dtv_clock_controller_at_ff440000 = {
.reg = {0xff440000, 0x1000},
.rockchip_grf = 0x3a,
};
@@ -25,37 +20,72 @@ U_BOOT_DEVICE(clock_controller_at_ff440000) = {
.name = "rockchip_rk3328_cru",
.platdata = &dtv_clock_controller_at_ff440000,
.platdata_size = sizeof(dtv_clock_controller_at_ff440000),
+ .parent_idx = -1,
};
-static const struct dtd_rockchip_rk3328_uart dtv_serial_at_ff130000 = {
- .clock_frequency = 0x16e3600,
+/* Node /dmc index 1 */
+static struct dtd_rockchip_rk3328_dmc dtv_dmc = {
+ .reg = {0xff400000, 0x1000, 0xff780000, 0x3000, 0xff100000, 0x1000, 0xff440000, 0x1000,
+ 0xff720000, 0x1000, 0xff798000, 0x1000},
+ .rockchip_sdram_params = {0x1, 0xa, 0x2, 0x1, 0x0, 0x0, 0x11, 0x0,
+ 0x11, 0x0, 0x0, 0x94291288, 0x0, 0x27, 0x462, 0x15,
+ 0x242, 0xff, 0x14d, 0x0, 0x1, 0x0, 0x0, 0x0,
+ 0x43049010, 0x64, 0x28003b, 0xd0, 0x20053, 0xd4, 0x220000, 0xd8,
+ 0x100, 0xdc, 0x40000, 0xe0, 0x0, 0xe4, 0x110000, 0xe8,
+ 0x420, 0xec, 0x400, 0xf4, 0xf011f, 0x100, 0x9060b06, 0x104,
+ 0x20209, 0x108, 0x505040a, 0x10c, 0x40400c, 0x110, 0x5030206, 0x114,
+ 0x3030202, 0x120, 0x3030b03, 0x124, 0x20208, 0x180, 0x1000040, 0x184,
+ 0x0, 0x190, 0x7030003, 0x198, 0x5001100, 0x1a0, 0xc0400003, 0x240,
+ 0x6000604, 0x244, 0x201, 0x250, 0xf00, 0x490, 0x1, 0xffffffff,
+ 0xffffffff, 0xffffffff, 0xffffffff, 0x4, 0xc, 0x28, 0xa, 0x2c,
+ 0x0, 0x30, 0x9, 0xffffffff, 0xffffffff, 0x77, 0x88, 0x79,
+ 0x79, 0x87, 0x97, 0x87, 0x78, 0x77, 0x78, 0x87,
+ 0x88, 0x87, 0x87, 0x77, 0x78, 0x78, 0x78, 0x78,
+ 0x78, 0x78, 0x78, 0x78, 0x78, 0x69, 0x9, 0x77,
+ 0x78, 0x77, 0x78, 0x77, 0x78, 0x77, 0x78, 0x77,
+ 0x79, 0x9, 0x78, 0x78, 0x78, 0x78, 0x78, 0x78,
+ 0x78, 0x78, 0x78, 0x69, 0x9, 0x77, 0x78, 0x77,
+ 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x79, 0x9,
+ 0x78, 0x78, 0x78, 0x78, 0x78, 0x78, 0x78, 0x78,
+ 0x78, 0x69, 0x9, 0x77, 0x78, 0x77, 0x78, 0x77,
+ 0x78, 0x77, 0x78, 0x77, 0x79, 0x9, 0x78, 0x78,
+ 0x78, 0x78, 0x78, 0x78, 0x78, 0x78, 0x78, 0x69,
+ 0x9, 0x77, 0x78, 0x77, 0x77, 0x77, 0x77, 0x77,
+ 0x77, 0x77, 0x79, 0x9},
+};
+U_BOOT_DEVICE(dmc) = {
+ .name = "rockchip_rk3328_dmc",
+ .platdata = &dtv_dmc,
+ .platdata_size = sizeof(dtv_dmc),
+ .parent_idx = -1,
+};
+
+/* Node /pinctrl/gpio0 at ff210000 index 2 */
+static struct dtd_rockchip_gpio_bank dtv_gpio0_at_ff210000 = {
.clocks = {
- {&dtv_clock_controller_at_ff440000, {40}},
- {&dtv_clock_controller_at_ff440000, {212}},},
- .dma_names = {"tx", "rx"},
- .dmas = {0x10, 0x6, 0x10, 0x7},
- .interrupts = {0x0, 0x39, 0x4},
- .pinctrl_0 = 0x26,
- .pinctrl_names = "default",
- .reg = {0xff130000, 0x100},
- .reg_io_width = 0x4,
- .reg_shift = 0x2,
+ {0, {200}},},
+ .gpio_controller = true,
+ .interrupt_controller = true,
+ .interrupts = {0x0, 0x33, 0x4},
+ .reg = {0xff210000, 0x100},
};
-U_BOOT_DEVICE(serial_at_ff130000) = {
- .name = "rockchip_rk3328_uart",
- .platdata = &dtv_serial_at_ff130000,
- .platdata_size = sizeof(dtv_serial_at_ff130000),
+U_BOOT_DEVICE(gpio0_at_ff210000) = {
+ .name = "rockchip_gpio_bank",
+ .platdata = &dtv_gpio0_at_ff210000,
+ .platdata_size = sizeof(dtv_gpio0_at_ff210000),
+ .parent_idx = 4,
};
-static const struct dtd_rockchip_rk3328_dw_mshc dtv_mmc_at_ff500000 = {
+/* Node /mmc at ff500000 index 3 */
+static struct dtd_rockchip_rk3288_dw_mshc dtv_mmc_at_ff500000 = {
.bus_width = 0x4,
.cap_mmc_highspeed = true,
.cap_sd_highspeed = true,
.clocks = {
- {&dtv_clock_controller_at_ff440000, {317}},
- {&dtv_clock_controller_at_ff440000, {33}},
- {&dtv_clock_controller_at_ff440000, {74}},
- {&dtv_clock_controller_at_ff440000, {78}},},
+ {0, {317}},
+ {0, {33}},
+ {0, {74}},
+ {0, {78}},},
.disable_wp = true,
.fifo_depth = 0x100,
.interrupts = {0x0, 0xc, 0x4},
@@ -68,12 +98,14 @@ static const struct dtd_rockchip_rk3328_dw_mshc dtv_mmc_at_ff500000 = {
.vqmmc_supply = 0x1e,
};
U_BOOT_DEVICE(mmc_at_ff500000) = {
- .name = "rockchip_rk3328_dw_mshc",
+ .name = "rockchip_rk3288_dw_mshc",
.platdata = &dtv_mmc_at_ff500000,
.platdata_size = sizeof(dtv_mmc_at_ff500000),
+ .parent_idx = -1,
};
-static const struct dtd_rockchip_rk3328_pinctrl dtv_pinctrl = {
+/* Node /pinctrl index 4 */
+static struct dtd_rockchip_rk3328_pinctrl dtv_pinctrl = {
.ranges = true,
.rockchip_grf = 0x3a,
};
@@ -81,23 +113,11 @@ U_BOOT_DEVICE(pinctrl) = {
.name = "rockchip_rk3328_pinctrl",
.platdata = &dtv_pinctrl,
.platdata_size = sizeof(dtv_pinctrl),
+ .parent_idx = -1,
};
-static const struct dtd_rockchip_gpio_bank dtv_gpio0_at_ff210000 = {
- .clocks = {
- {&dtv_clock_controller_at_ff440000, {200}},},
- .gpio_controller = true,
- .interrupt_controller = true,
- .interrupts = {0x0, 0x33, 0x4},
- .reg = {0xff210000, 0x100},
-};
-U_BOOT_DEVICE(gpio0_at_ff210000) = {
- .name = "rockchip_gpio_bank",
- .platdata = &dtv_gpio0_at_ff210000,
- .platdata_size = sizeof(dtv_gpio0_at_ff210000),
-};
-
-static const struct dtd_regulator_fixed dtv_sdmmc_regulator = {
+/* Node /sdmmc-regulator index 5 */
+static struct dtd_regulator_fixed dtv_sdmmc_regulator = {
.gpio = {0x60, 0x1e, 0x1},
.pinctrl_0 = 0x61,
.pinctrl_names = "default",
@@ -110,40 +130,41 @@ U_BOOT_DEVICE(sdmmc_regulator) = {
.name = "regulator_fixed",
.platdata = &dtv_sdmmc_regulator,
.platdata_size = sizeof(dtv_sdmmc_regulator),
+ .parent_idx = -1,
};
-static const struct dtd_rockchip_rk3328_dmc dtv_dmc = {
- .reg = {0xff400000, 0x1000, 0xff780000, 0x3000, 0xff100000, 0x1000, 0xff440000, 0x1000,
- 0xff720000, 0x1000, 0xff798000, 0x1000},
- .rockchip_sdram_params = {0x1, 0xa, 0x2, 0x1, 0x0, 0x0, 0x11, 0x0,
- 0x11, 0x0, 0x0, 0x94291288, 0x0, 0x27, 0x462, 0x15,
- 0x242, 0xff, 0x14d, 0x0, 0x1, 0x0, 0x0, 0x0,
- 0x43049010, 0x64, 0x28003b, 0xd0, 0x20053, 0xd4, 0x220000, 0xd8,
- 0x100, 0xdc, 0x40000, 0xe0, 0x0, 0xe4, 0x110000, 0xe8,
- 0x420, 0xec, 0x400, 0xf4, 0xf011f, 0x100, 0x9060b06, 0x104,
- 0x20209, 0x108, 0x505040a, 0x10c, 0x40400c, 0x110, 0x5030206, 0x114,
- 0x3030202, 0x120, 0x3030b03, 0x124, 0x20208, 0x180, 0x1000040, 0x184,
- 0x0, 0x190, 0x7030003, 0x198, 0x5001100, 0x1a0, 0xc0400003, 0x240,
- 0x6000604, 0x244, 0x201, 0x250, 0xf00, 0x490, 0x1, 0xffffffff,
- 0xffffffff, 0xffffffff, 0xffffffff, 0x4, 0xc, 0x28, 0xa, 0x2c,
- 0x0, 0x30, 0x9, 0xffffffff, 0xffffffff, 0x77, 0x88, 0x79,
- 0x79, 0x87, 0x97, 0x87, 0x78, 0x77, 0x78, 0x87,
- 0x88, 0x87, 0x87, 0x77, 0x78, 0x78, 0x78, 0x78,
- 0x78, 0x78, 0x78, 0x78, 0x78, 0x69, 0x9, 0x77,
- 0x78, 0x77, 0x78, 0x77, 0x78, 0x77, 0x78, 0x77,
- 0x79, 0x9, 0x78, 0x78, 0x78, 0x78, 0x78, 0x78,
- 0x78, 0x78, 0x78, 0x69, 0x9, 0x77, 0x78, 0x77,
- 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x79, 0x9,
- 0x78, 0x78, 0x78, 0x78, 0x78, 0x78, 0x78, 0x78,
- 0x78, 0x69, 0x9, 0x77, 0x78, 0x77, 0x78, 0x77,
- 0x78, 0x77, 0x78, 0x77, 0x79, 0x9, 0x78, 0x78,
- 0x78, 0x78, 0x78, 0x78, 0x78, 0x78, 0x78, 0x69,
- 0x9, 0x77, 0x78, 0x77, 0x77, 0x77, 0x77, 0x77,
- 0x77, 0x77, 0x79, 0x9},
+/* Node /serial at ff130000 index 6 */
+static struct dtd_ns16550_serial dtv_serial_at_ff130000 = {
+ .clock_frequency = 0x16e3600,
+ .clocks = {
+ {0, {40}},
+ {0, {212}},},
+ .dma_names = {"tx", "rx"},
+ .dmas = {0x10, 0x6, 0x10, 0x7},
+ .interrupts = {0x0, 0x39, 0x4},
+ .pinctrl_0 = 0x26,
+ .pinctrl_names = "default",
+ .reg = {0xff130000, 0x100},
+ .reg_io_width = 0x4,
+ .reg_shift = 0x2,
};
-U_BOOT_DEVICE(dmc) = {
- .name = "rockchip_rk3328_dmc",
- .platdata = &dtv_dmc,
- .platdata_size = sizeof(dtv_dmc),
+U_BOOT_DEVICE(serial_at_ff130000) = {
+ .name = "ns16550_serial",
+ .platdata = &dtv_serial_at_ff130000,
+ .platdata_size = sizeof(dtv_serial_at_ff130000),
+ .parent_idx = -1,
+};
+
+/* Node /syscon at ff100000 index 7 */
+static struct dtd_rockchip_rk3328_grf dtv_syscon_at_ff100000 = {
+ .reg = {0xff100000, 0x1000},
+};
+U_BOOT_DEVICE(syscon_at_ff100000) = {
+ .name = "rockchip_rk3328_grf",
+ .platdata = &dtv_syscon_at_ff100000,
+ .platdata_size = sizeof(dtv_syscon_at_ff100000),
+ .parent_idx = -1,
};
+void dm_populate_phandle_data(void) {
+}
diff --git a/package/boot/uboot-rockchip/src/of-platdata/nanopi-r2s-rk3328/dt-structs-gen.h b/package/boot/uboot-rockchip/src/of-platdata/nanopi-r2s-rk3328/dt-structs-gen.h
index 88291627b8..6dcb4c1f1b 100644
--- a/package/boot/uboot-rockchip/src/of-platdata/nanopi-r2s-rk3328/dt-structs-gen.h
+++ b/package/boot/uboot-rockchip/src/of-platdata/nanopi-r2s-rk3328/dt-structs-gen.h
@@ -6,6 +6,18 @@
#include <stdbool.h>
#include <linux/libfdt.h>
+struct dtd_ns16550_serial {
+ fdt32_t clock_frequency;
+ struct phandle_1_arg clocks[2];
+ const char * dma_names[2];
+ fdt32_t dmas[4];
+ fdt32_t interrupts[3];
+ fdt32_t pinctrl_0;
+ const char * pinctrl_names;
+ fdt64_t reg[2];
+ fdt32_t reg_io_width;
+ fdt32_t reg_shift;
+};
struct dtd_regulator_fixed {
fdt32_t gpio[3];
fdt32_t pinctrl_0;
@@ -22,15 +34,7 @@ struct dtd_rockchip_gpio_bank {
fdt32_t interrupts[3];
fdt64_t reg[2];
};
-struct dtd_rockchip_rk3328_cru {
- fdt64_t reg[2];
- fdt32_t rockchip_grf;
-};
-struct dtd_rockchip_rk3328_dmc {
- fdt64_t reg[12];
- fdt32_t rockchip_sdram_params[196];
-};
-struct dtd_rockchip_rk3328_dw_mshc {
+struct dtd_rockchip_rk3288_dw_mshc {
fdt32_t bus_width;
bool cap_mmc_highspeed;
bool cap_sd_highspeed;
@@ -46,6 +50,14 @@ struct dtd_rockchip_rk3328_dw_mshc {
fdt32_t vmmc_supply;
fdt32_t vqmmc_supply;
};
+struct dtd_rockchip_rk3328_cru {
+ fdt64_t reg[2];
+ fdt32_t rockchip_grf;
+};
+struct dtd_rockchip_rk3328_dmc {
+ fdt64_t reg[12];
+ fdt32_t rockchip_sdram_params[196];
+};
struct dtd_rockchip_rk3328_grf {
fdt64_t reg[2];
};
@@ -53,20 +65,3 @@ struct dtd_rockchip_rk3328_pinctrl {
bool ranges;
fdt32_t rockchip_grf;
};
-struct dtd_rockchip_rk3328_uart {
- fdt32_t clock_frequency;
- struct phandle_1_arg clocks[2];
- const char * dma_names[2];
- fdt32_t dmas[4];
- fdt32_t interrupts[3];
- fdt32_t pinctrl_0;
- const char * pinctrl_names;
- fdt64_t reg[2];
- fdt32_t reg_io_width;
- fdt32_t reg_shift;
-};
-#define dtd_syscon dtd_rockchip_rk3328_cru
-#define dtd_simple_mfd dtd_rockchip_rk3328_grf
-#define dtd_snps_dw_apb_uart dtd_rockchip_rk3328_uart
-#define dtd_rockchip_cru dtd_rockchip_rk3328_cru
-#define dtd_rockchip_rk3288_dw_mshc dtd_rockchip_rk3328_dw_mshc
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