[openwrt/openwrt] mediatek: mt7622-bananapi-bpi-r64-rootdisk rebase to upstream dts
LEDE Commits
lede-commits at lists.infradead.org
Wed Feb 24 15:23:13 EST 2021
dangole pushed a commit to openwrt/openwrt.git, branch master:
https://git.openwrt.org/f0818706eb599dae33232e6e9489695223a9880c
commit f0818706eb599dae33232e6e9489695223a9880c
Author: Oskari Lemmela <oskari at lemmela.net>
AuthorDate: Wed Feb 24 21:10:38 2021 +0200
mediatek: mt7622-bananapi-bpi-r64-rootdisk rebase to upstream dts
simplify maintaining mt7622-bananapi-bpi-r64-rootdisk.dts by
storing only differences between upstream dts
Signed-off-by: Oskari Lemmela <oskari at lemmela.net>
---
.../dts/mt7622-bananapi-bpi-r64-rootdisk.dts | 574 +--------------------
1 file changed, 1 insertion(+), 573 deletions(-)
diff --git a/target/linux/mediatek/dts/mt7622-bananapi-bpi-r64-rootdisk.dts b/target/linux/mediatek/dts/mt7622-bananapi-bpi-r64-rootdisk.dts
index 428777e3f7..911b3dd5b4 100644
--- a/target/linux/mediatek/dts/mt7622-bananapi-bpi-r64-rootdisk.dts
+++ b/target/linux/mediatek/dts/mt7622-bananapi-bpi-r64-rootdisk.dts
@@ -5,586 +5,14 @@
*/
/dts-v1/;
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/gpio/gpio.h>
-
-#include "mt7622.dtsi"
-#include "mt6380.dtsi"
+#include "mt7622-bananapi-bpi-r64.dts"
/ {
model = "Bananapi BPI-R64";
compatible = "bananapi,bpi-r64-rootdisk", "mediatek,mt7622";
- aliases {
- serial0 = &uart0;
- };
-
chosen {
stdout-path = "serial0:115200n8";
bootargs = "earlycon=uart8250,mmio32,0x11002000 console=ttyS0,115200n1 swiotlb=512 root=/dev/mmcblk0p7 rootfstype=squashfs,f2fs";
};
-
- cpus {
- cpu at 0 {
- proc-supply = <&mt6380_vcpu_reg>;
- sram-supply = <&mt6380_vm_reg>;
- };
-
- cpu at 1 {
- proc-supply = <&mt6380_vcpu_reg>;
- sram-supply = <&mt6380_vm_reg>;
- };
- };
-
- gpio-keys {
- compatible = "gpio-keys";
-
- factory {
- label = "factory";
- linux,code = <BTN_0>;
- gpios = <&pio 0 GPIO_ACTIVE_HIGH>;
- };
-
- wps {
- label = "wps";
- linux,code = <KEY_WPS_BUTTON>;
- gpios = <&pio 102 GPIO_ACTIVE_HIGH>;
- };
- };
-
- leds {
- compatible = "gpio-leds";
-
- green {
- label = "bpi-r64:pio:green";
- gpios = <&pio 89 GPIO_ACTIVE_HIGH>;
- };
-
- red {
- label = "bpi-r64:pio:red";
- gpios = <&pio 88 GPIO_ACTIVE_HIGH>;
- };
- };
-
- memory {
- reg = <0 0x40000000 0 0x40000000>;
- };
-
- reg_1p8v: regulator-1p8v {
- compatible = "regulator-fixed";
- regulator-name = "fixed-1.8V";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-always-on;
- };
-
- reg_3p3v: regulator-3p3v {
- compatible = "regulator-fixed";
- regulator-name = "fixed-3.3V";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-boot-on;
- regulator-always-on;
- };
-
- reg_5v: regulator-5v {
- compatible = "regulator-fixed";
- regulator-name = "fixed-5V";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- regulator-boot-on;
- regulator-always-on;
- };
-};
-
-&bch {
- status = "disabled";
-};
-
-&btif {
- status = "okay";
-};
-
-&cir {
- pinctrl-names = "default";
- pinctrl-0 = <&irrx_pins>;
- status = "okay";
-};
-
-ð {
- status = "okay";
- gmac0: mac at 0 {
- compatible = "mediatek,eth-mac";
- reg = <0>;
- phy-mode = "2500base-x";
-
- fixed-link {
- speed = <2500>;
- full-duplex;
- pause;
- };
- };
-
- gmac1: mac at 1 {
- compatible = "mediatek,eth-mac";
- reg = <1>;
- phy-mode = "rgmii";
-
- fixed-link {
- speed = <1000>;
- full-duplex;
- pause;
- };
- };
-
- mdio: mdio-bus {
- #address-cells = <1>;
- #size-cells = <0>;
-
- switch at 1f {
- compatible = "mediatek,mt7531";
- reg = <0x1f>;
- reset-gpios = <&pio 54 0>;
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- wan: port at 0 {
- reg = <0>;
- label = "wan";
- };
-
- port at 1 {
- reg = <1>;
- label = "lan0";
- };
-
- port at 2 {
- reg = <2>;
- label = "lan1";
- };
-
- port at 3 {
- reg = <3>;
- label = "lan2";
- };
-
- port at 4 {
- reg = <4>;
- label = "lan3";
- };
-
- port at 6 {
- reg = <6>;
- label = "cpu";
- ethernet = <&gmac0>;
- phy-mode = "2500base-x";
-
- fixed-link {
- speed = <2500>;
- full-duplex;
- pause;
- };
- };
- };
- };
-
- };
-};
-
-&i2c1 {
- pinctrl-names = "default";
- pinctrl-0 = <&i2c1_pins>;
- status = "okay";
-};
-
-&i2c2 {
- pinctrl-names = "default";
- pinctrl-0 = <&i2c2_pins>;
- status = "okay";
-};
-
-&mmc0 {
- pinctrl-names = "default", "state_uhs";
- pinctrl-0 = <&emmc_pins_default>;
- pinctrl-1 = <&emmc_pins_uhs>;
- status = "okay";
- bus-width = <8>;
- max-frequency = <50000000>;
- cap-mmc-highspeed;
- mmc-hs200-1_8v;
- vmmc-supply = <®_3p3v>;
- vqmmc-supply = <®_1p8v>;
- assigned-clocks = <&topckgen CLK_TOP_MSDC30_0_SEL>;
- assigned-clock-parents = <&topckgen CLK_TOP_UNIV48M>;
- non-removable;
-};
-
-&mmc1 {
- pinctrl-names = "default", "state_uhs";
- pinctrl-0 = <&sd0_pins_default>;
- pinctrl-1 = <&sd0_pins_uhs>;
- status = "okay";
- bus-width = <4>;
- max-frequency = <50000000>;
- cap-sd-highspeed;
- r_smpl = <1>;
- cd-gpios = <&pio 81 GPIO_ACTIVE_LOW>;
- vmmc-supply = <®_3p3v>;
- vqmmc-supply = <®_3p3v>;
- assigned-clocks = <&topckgen CLK_TOP_MSDC30_1_SEL>;
- assigned-clock-parents = <&topckgen CLK_TOP_UNIV48M>;
-};
-
-&nandc {
- pinctrl-names = "default";
- pinctrl-0 = <¶llel_nand_pins>;
- status = "disabled";
-};
-
-&nor_flash {
- pinctrl-names = "default";
- pinctrl-0 = <&spi_nor_pins>;
- status = "disabled";
-
- flash at 0 {
- compatible = "jedec,spi-nor";
- reg = <0>;
- };
-};
-
-&pcie0 {
- pinctrl-names = "default";
- pinctrl-0 = <&pcie0_pins>;
- status = "okay";
-};
-
-&pcie1 {
- pinctrl-names = "default";
- pinctrl-0 = <&pcie1_pins>;
- status = "okay";
-};
-
-&pio {
- /* Attention: GPIO 90 is used to switch between PCIe at 1,0 and
- * SATA functions. i.e. output-high: PCIe, output-low: SATA
- */
- asm_sel {
- gpio-hog;
- gpios = <90 GPIO_ACTIVE_HIGH>;
- output-high;
- };
-
- /* eMMC is shared pin with parallel NAND */
- emmc_pins_default: emmc-pins-default {
- mux {
- function = "emmc", "emmc_rst";
- groups = "emmc";
- };
-
- /* "NDL0","NDL1","NDL2","NDL3","NDL4","NDL5","NDL6","NDL7",
- * "NRB","NCLE" pins are used as DAT0,DAT1,DAT2,DAT3,DAT4,
- * DAT5,DAT6,DAT7,CMD,CLK for eMMC respectively
- */
- conf-cmd-dat {
- pins = "NDL0", "NDL1", "NDL2",
- "NDL3", "NDL4", "NDL5",
- "NDL6", "NDL7", "NRB";
- input-enable;
- bias-pull-up;
- };
-
- conf-clk {
- pins = "NCLE";
- bias-pull-down;
- };
- };
-
- emmc_pins_uhs: emmc-pins-uhs {
- mux {
- function = "emmc";
- groups = "emmc";
- };
-
- conf-cmd-dat {
- pins = "NDL0", "NDL1", "NDL2",
- "NDL3", "NDL4", "NDL5",
- "NDL6", "NDL7", "NRB";
- input-enable;
- drive-strength = <4>;
- bias-pull-up;
- };
-
- conf-clk {
- pins = "NCLE";
- drive-strength = <4>;
- bias-pull-down;
- };
- };
-
- eth_pins: eth-pins {
- mux {
- function = "eth";
- groups = "mdc_mdio", "rgmii_via_gmac2";
- };
- };
-
- i2c1_pins: i2c1-pins {
- mux {
- function = "i2c";
- groups = "i2c1_0";
- };
- };
-
- i2c2_pins: i2c2-pins {
- mux {
- function = "i2c";
- groups = "i2c2_0";
- };
- };
-
- i2s1_pins: i2s1-pins {
- mux {
- function = "i2s";
- groups = "i2s_out_mclk_bclk_ws",
- "i2s1_in_data",
- "i2s1_out_data";
- };
-
- conf {
- pins = "I2S1_IN", "I2S1_OUT", "I2S_BCLK",
- "I2S_WS", "I2S_MCLK";
- drive-strength = <12>;
- bias-pull-down;
- };
- };
-
- irrx_pins: irrx-pins {
- mux {
- function = "ir";
- groups = "ir_1_rx";
- };
- };
-
- irtx_pins: irtx-pins {
- mux {
- function = "ir";
- groups = "ir_1_tx";
- };
- };
-
- /* Parallel nand is shared pin with eMMC */
- parallel_nand_pins: parallel-nand-pins {
- mux {
- function = "flash";
- groups = "par_nand";
- };
- };
-
- pcie0_pins: pcie0-pins {
- mux {
- function = "pcie";
- groups = "pcie0_pad_perst",
- "pcie0_1_waken",
- "pcie0_1_clkreq";
- };
- };
-
- pcie1_pins: pcie1-pins {
- mux {
- function = "pcie";
- groups = "pcie1_pad_perst",
- "pcie1_0_waken",
- "pcie1_0_clkreq";
- };
- };
-
- pmic_bus_pins: pmic-bus-pins {
- mux {
- function = "pmic";
- groups = "pmic_bus";
- };
- };
-
- pwm7_pins: pwm1-2-pins {
- mux {
- function = "pwm";
- groups = "pwm_ch7_2";
- };
- };
-
- wled_pins: wled-pins {
- mux {
- function = "led";
- groups = "wled";
- };
- };
-
- sd0_pins_default: sd0-pins-default {
- mux {
- function = "sd";
- groups = "sd_0";
- };
-
- /* "I2S2_OUT, "I2S4_IN"", "I2S3_IN", "I2S2_IN",
- * "I2S4_OUT", "I2S3_OUT" are used as DAT0, DAT1,
- * DAT2, DAT3, CMD, CLK for SD respectively.
- */
- conf-cmd-data {
- pins = "I2S2_OUT", "I2S4_IN", "I2S3_IN",
- "I2S2_IN","I2S4_OUT";
- input-enable;
- drive-strength = <8>;
- bias-pull-up;
- };
- conf-clk {
- pins = "I2S3_OUT";
- drive-strength = <12>;
- bias-pull-down;
- };
- conf-cd {
- pins = "TXD3";
- bias-pull-up;
- };
- };
-
- sd0_pins_uhs: sd0-pins-uhs {
- mux {
- function = "sd";
- groups = "sd_0";
- };
-
- conf-cmd-data {
- pins = "I2S2_OUT", "I2S4_IN", "I2S3_IN",
- "I2S2_IN","I2S4_OUT";
- input-enable;
- bias-pull-up;
- };
-
- conf-clk {
- pins = "I2S3_OUT";
- bias-pull-down;
- };
- };
-
- /* Serial NAND is shared pin with SPI-NOR */
- serial_nand_pins: serial-nand-pins {
- mux {
- function = "flash";
- groups = "snfi";
- };
- };
-
- spic0_pins: spic0-pins {
- mux {
- function = "spi";
- groups = "spic0_0";
- };
- };
-
- spic1_pins: spic1-pins {
- mux {
- function = "spi";
- groups = "spic1_0";
- };
- };
-
- /* SPI-NOR is shared pin with serial NAND */
- spi_nor_pins: spi-nor-pins {
- mux {
- function = "flash";
- groups = "spi_nor";
- };
- };
-
- /* serial NAND is shared pin with SPI-NOR */
- serial_nand_pins: serial-nand-pins {
- mux {
- function = "flash";
- groups = "snfi";
- };
- };
-
- uart0_pins: uart0-pins {
- mux {
- function = "uart";
- groups = "uart0_0_tx_rx" ;
- };
- };
-
- uart2_pins: uart2-pins {
- mux {
- function = "uart";
- groups = "uart2_1_tx_rx" ;
- };
- };
-
- watchdog_pins: watchdog-pins {
- mux {
- function = "watchdog";
- groups = "watchdog";
- };
- };
-};
-
-&pwm {
- pinctrl-names = "default";
- pinctrl-0 = <&pwm7_pins>;
- status = "okay";
-};
-
-&pwrap {
- pinctrl-names = "default";
- pinctrl-0 = <&pmic_bus_pins>;
-
- status = "okay";
-};
-
-&sata {
- status = "disable";
-};
-
-&sata_phy {
- status = "disable";
-};
-
-&spi0 {
- pinctrl-names = "default";
- pinctrl-0 = <&spic0_pins>;
- status = "okay";
-};
-
-&spi1 {
- pinctrl-names = "default";
- pinctrl-0 = <&spic1_pins>;
- status = "okay";
-};
-
-&ssusb {
- vusb33-supply = <®_3p3v>;
- vbus-supply = <®_5v>;
- status = "okay";
-};
-
-&u3phy {
- status = "okay";
-};
-
-&uart0 {
- pinctrl-names = "default";
- pinctrl-0 = <&uart0_pins>;
- status = "okay";
-};
-
-&uart2 {
- pinctrl-names = "default";
- pinctrl-0 = <&uart2_pins>;
- status = "okay";
-};
-
-&watchdog {
- pinctrl-names = "default";
- pinctrl-0 = <&watchdog_pins>;
- status = "okay";
};
More information about the lede-commits
mailing list