[openwrt/openwrt] mediatek: replace patch with version sent upstream
LEDE Commits
lede-commits at lists.infradead.org
Mon Dec 27 08:25:09 PST 2021
dangole pushed a commit to openwrt/openwrt.git, branch master:
https://git.openwrt.org/c555c34dd15c11a901ea4dfcadbcc0e4f3072160
commit c555c34dd15c11a901ea4dfcadbcc0e4f3072160
Author: Daniel Golle <daniel at makrotopia.org>
AuthorDate: Mon Dec 27 15:26:18 2021 +0000
mediatek: replace patch with version sent upstream
Replace recently added patch
701-net-ethernet-mtk_eth_soc-add-support-for-clause-45-mdio.patch
with version sent upstream
701-net-ethernet-mtk_eth_soc-implement-Clause-45-MDIO-access.patch
Signed-off-by: Daniel Golle <daniel at makrotopia.org>
---
...tk_eth_soc-add-support-for-clause-45-mdio.patch | 94 ------------
...k_eth_soc-implement-Clause-45-MDIO-access.patch | 166 +++++++++++++++++++++
2 files changed, 166 insertions(+), 94 deletions(-)
diff --git a/target/linux/mediatek/patches-5.10/701-net-ethernet-mtk_eth_soc-add-support-for-clause-45-mdio.patch b/target/linux/mediatek/patches-5.10/701-net-ethernet-mtk_eth_soc-add-support-for-clause-45-mdio.patch
deleted file mode 100644
index 242e39421e..0000000000
--- a/target/linux/mediatek/patches-5.10/701-net-ethernet-mtk_eth_soc-add-support-for-clause-45-mdio.patch
+++ /dev/null
@@ -1,94 +0,0 @@
---- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
-+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
-@@ -103,10 +103,30 @@ static u32 _mtk_mdio_write(struct mtk_et
-
- write_data &= 0xffff;
-
-- mtk_w32(eth, PHY_IAC_ACCESS | PHY_IAC_START | PHY_IAC_WRITE |
-- (phy_register << PHY_IAC_REG_SHIFT) |
-- (phy_addr << PHY_IAC_ADDR_SHIFT) | write_data,
-- MTK_PHY_IAC);
-+ if (phy_register & MII_ADDR_C45) {
-+ u8 dev_num = (phy_register >> 16) & 0x1f;
-+ u16 reg = (u16)(phy_register & 0xffff);
-+
-+ mtk_w32(eth, PHY_IAC_ACCESS | PHY_IAC_START_C45 | PHY_IAC_SET_ADDR |
-+ (phy_addr << PHY_IAC_ADDR_SHIFT) |
-+ (dev_num << PHY_IAC_REG_SHIFT) |
-+ reg,
-+ MTK_PHY_IAC);
-+
-+ if (mtk_mdio_busy_wait(eth))
-+ return 0xffff;
-+
-+ mtk_w32(eth, PHY_IAC_ACCESS | PHY_IAC_START_C45 | PHY_IAC_WRITE |
-+ (phy_addr << PHY_IAC_ADDR_SHIFT) |
-+ (dev_num << PHY_IAC_REG_SHIFT) |
-+ write_data,
-+ MTK_PHY_IAC);
-+ } else {
-+ mtk_w32(eth, PHY_IAC_ACCESS | PHY_IAC_START | PHY_IAC_WRITE |
-+ (phy_register << PHY_IAC_REG_SHIFT) |
-+ (phy_addr << PHY_IAC_ADDR_SHIFT) | write_data,
-+ MTK_PHY_IAC);
-+ }
-
- if (mtk_mdio_busy_wait(eth))
- return -1;
-@@ -121,10 +141,29 @@ static u32 _mtk_mdio_read(struct mtk_eth
- if (mtk_mdio_busy_wait(eth))
- return 0xffff;
-
-- mtk_w32(eth, PHY_IAC_ACCESS | PHY_IAC_START | PHY_IAC_READ |
-- (phy_reg << PHY_IAC_REG_SHIFT) |
-- (phy_addr << PHY_IAC_ADDR_SHIFT),
-- MTK_PHY_IAC);
-+ if (phy_reg & MII_ADDR_C45) {
-+ u8 dev_num = (phy_reg >> 16) & 0x1f;
-+ u16 reg = (u16)(phy_reg & 0xffff);
-+
-+ mtk_w32(eth, PHY_IAC_ACCESS | PHY_IAC_START_C45 | PHY_IAC_SET_ADDR |
-+ (phy_addr << PHY_IAC_ADDR_SHIFT) |
-+ (dev_num << PHY_IAC_REG_SHIFT) |
-+ reg,
-+ MTK_PHY_IAC);
-+
-+ if (mtk_mdio_busy_wait(eth))
-+ return 0xffff;
-+
-+ mtk_w32(eth, PHY_IAC_ACCESS | PHY_IAC_START_C45 | PHY_IAC_READ_C45 |
-+ (phy_addr << PHY_IAC_ADDR_SHIFT) |
-+ (dev_num << PHY_IAC_REG_SHIFT),
-+ MTK_PHY_IAC);
-+ } else {
-+ mtk_w32(eth, PHY_IAC_ACCESS | PHY_IAC_START | PHY_IAC_READ |
-+ (phy_reg << PHY_IAC_REG_SHIFT) |
-+ (phy_addr << PHY_IAC_ADDR_SHIFT),
-+ MTK_PHY_IAC);
-+ }
-
- if (mtk_mdio_busy_wait(eth))
- return 0xffff;
-@@ -584,6 +623,7 @@ static int mtk_mdio_init(struct mtk_eth
- eth->mii_bus->name = "mdio";
- eth->mii_bus->read = mtk_mdio_read;
- eth->mii_bus->write = mtk_mdio_write;
-+ eth->mii_bus->probe_capabilities = MDIOBUS_C22_C45;
- eth->mii_bus->priv = eth;
- eth->mii_bus->parent = eth->dev;
-
---- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h
-+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
-@@ -340,9 +340,12 @@
- /* PHY Indirect Access Control registers */
- #define MTK_PHY_IAC 0x10004
- #define PHY_IAC_ACCESS BIT(31)
-+#define PHY_IAC_SET_ADDR 0
- #define PHY_IAC_READ BIT(19)
-+#define PHY_IAC_READ_C45 (BIT(18) | BIT(19))
- #define PHY_IAC_WRITE BIT(18)
- #define PHY_IAC_START BIT(16)
-+#define PHY_IAC_START_C45 0
- #define PHY_IAC_ADDR_SHIFT 20
- #define PHY_IAC_REG_SHIFT 25
- #define PHY_IAC_TIMEOUT HZ
diff --git a/target/linux/mediatek/patches-5.10/701-net-ethernet-mtk_eth_soc-implement-Clause-45-MDIO-access.patch b/target/linux/mediatek/patches-5.10/701-net-ethernet-mtk_eth_soc-implement-Clause-45-MDIO-access.patch
new file mode 100644
index 0000000000..78e1a626d5
--- /dev/null
+++ b/target/linux/mediatek/patches-5.10/701-net-ethernet-mtk_eth_soc-implement-Clause-45-MDIO-access.patch
@@ -0,0 +1,166 @@
+From patchwork Mon Dec 27 16:09:22 2021
+Content-Type: text/plain; charset="utf-8"
+MIME-Version: 1.0
+Content-Transfer-Encoding: 7bit
+X-Patchwork-Submitter: Daniel Golle <daniel at makrotopia.org>
+X-Patchwork-Id: 12699860
+X-Patchwork-Delegate: kuba at kernel.org
+Date: Mon, 27 Dec 2021 16:09:22 +0000
+From: Daniel Golle <daniel at makrotopia.org>
+To: linux-mediatek at lists.infradead.org, netdev at vger.kernel.org,
+ linux-arm-kernel at lists.infradead.org, linux-kernel at vger.kernel.org
+Cc: Felix Fietkau <nbd at nbd.name>, John Crispin <john at phrozen.org>,
+ Sean Wang <sean.wang at mediatek.com>,
+ Mark Lee <Mark-MC.Lee at mediatek.com>,
+ "David S. Miller" <davem at davemloft.net>,
+ Jakub Kicinski <kuba at kernel.org>,
+ Matthias Brugger <matthias.bgg at gmail.com>,
+ Russell King <linux at armlinux.org.uk>,
+ Andrew Lunn <andrew at lunn.ch>
+Subject: [PATCH v3] net: ethernet: mtk_eth_soc: implement Clause 45 MDIO
+ access
+Message-ID: <YcnlMtninjjjPhjI at makrotopia.org>
+References: <YcjsFnbg87o45ltd at lunn.ch>
+ <YcjjzNJ159Bo1xk7 at lunn.ch>
+ <YcjlMCacTTJ4RsSA at shell.armlinux.org.uk>
+ <YcjepQ2fmkPZ2+pE at makrotopia.org>
+MIME-Version: 1.0
+Content-Disposition: inline
+In-Reply-To: <YcjsFnbg87o45ltd at lunn.ch>
+ <YcjjzNJ159Bo1xk7 at lunn.ch>
+ <YcjlMCacTTJ4RsSA at shell.armlinux.org.uk>
+ <YcjepQ2fmkPZ2+pE at makrotopia.org>
+Precedence: bulk
+List-ID: <netdev.vger.kernel.org>
+X-Mailing-List: netdev at vger.kernel.org
+X-Patchwork-Delegate: kuba at kernel.org
+
+Implement read and write access to IEEE 802.3 Clause 45 Ethernet
+phy registers.
+Tested on the Ubiquiti UniFi 6 LR access point featuring
+MediaTek MT7622BV WiSoC with Aquantia AQR112C.
+
+Signed-off-by: Daniel Golle <daniel at makrotopia.org>
+---
+v3: return -1 instead of 0xffff on error in _mtk_mdio_write
+v2: use MII_DEVADDR_C45_SHIFT and MII_REGADDR_C45_MASK to extract
+ device id and register address. Unify read and write functions to
+ have identical types and parameter names where possible as we are
+ anyway already replacing both function bodies.
+
+ drivers/net/ethernet/mediatek/mtk_eth_soc.c | 62 +++++++++++++++++----
+ drivers/net/ethernet/mediatek/mtk_eth_soc.h | 3 +
+ 2 files changed, 54 insertions(+), 11 deletions(-)
+
+--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
++++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
+@@ -95,18 +95,38 @@ static int mtk_mdio_busy_wait(struct mtk
+ return -1;
+ }
+
+-static u32 _mtk_mdio_write(struct mtk_eth *eth, u32 phy_addr,
+- u32 phy_register, u32 write_data)
++static u32 _mtk_mdio_write(struct mtk_eth *eth, u32 phy_addr, u32 phy_reg,
++ u32 write_data)
+ {
+ if (mtk_mdio_busy_wait(eth))
+ return -1;
+
+ write_data &= 0xffff;
+
+- mtk_w32(eth, PHY_IAC_ACCESS | PHY_IAC_START | PHY_IAC_WRITE |
+- (phy_register << PHY_IAC_REG_SHIFT) |
+- (phy_addr << PHY_IAC_ADDR_SHIFT) | write_data,
+- MTK_PHY_IAC);
++ if (phy_reg & MII_ADDR_C45) {
++ u8 dev_num = (phy_reg >> MII_DEVADDR_C45_SHIFT) & GENMASK(4, 0);
++ u16 reg = (u16)(phy_reg & MII_REGADDR_C45_MASK);
++
++ mtk_w32(eth, PHY_IAC_ACCESS | PHY_IAC_START_C45 | PHY_IAC_SET_ADDR |
++ (phy_addr << PHY_IAC_ADDR_SHIFT) |
++ (dev_num << PHY_IAC_REG_SHIFT) |
++ reg,
++ MTK_PHY_IAC);
++
++ if (mtk_mdio_busy_wait(eth))
++ return -1;
++
++ mtk_w32(eth, PHY_IAC_ACCESS | PHY_IAC_START_C45 | PHY_IAC_WRITE |
++ (phy_addr << PHY_IAC_ADDR_SHIFT) |
++ (dev_num << PHY_IAC_REG_SHIFT) |
++ write_data,
++ MTK_PHY_IAC);
++ } else {
++ mtk_w32(eth, PHY_IAC_ACCESS | PHY_IAC_START | PHY_IAC_WRITE |
++ (phy_reg << PHY_IAC_REG_SHIFT) |
++ (phy_addr << PHY_IAC_ADDR_SHIFT) | write_data,
++ MTK_PHY_IAC);
++ }
+
+ if (mtk_mdio_busy_wait(eth))
+ return -1;
+@@ -114,17 +134,36 @@ static u32 _mtk_mdio_write(struct mtk_et
+ return 0;
+ }
+
+-static u32 _mtk_mdio_read(struct mtk_eth *eth, int phy_addr, int phy_reg)
++static u32 _mtk_mdio_read(struct mtk_eth *eth, u32 phy_addr, u32 phy_reg)
+ {
+ u32 d;
+
+ if (mtk_mdio_busy_wait(eth))
+ return 0xffff;
+
+- mtk_w32(eth, PHY_IAC_ACCESS | PHY_IAC_START | PHY_IAC_READ |
+- (phy_reg << PHY_IAC_REG_SHIFT) |
+- (phy_addr << PHY_IAC_ADDR_SHIFT),
+- MTK_PHY_IAC);
++ if (phy_reg & MII_ADDR_C45) {
++ u8 dev_num = (phy_reg >> MII_DEVADDR_C45_SHIFT) & GENMASK(4, 0);
++ u16 reg = (u16)(phy_reg & MII_REGADDR_C45_MASK);
++
++ mtk_w32(eth, PHY_IAC_ACCESS | PHY_IAC_START_C45 | PHY_IAC_SET_ADDR |
++ (phy_addr << PHY_IAC_ADDR_SHIFT) |
++ (dev_num << PHY_IAC_REG_SHIFT) |
++ reg,
++ MTK_PHY_IAC);
++
++ if (mtk_mdio_busy_wait(eth))
++ return 0xffff;
++
++ mtk_w32(eth, PHY_IAC_ACCESS | PHY_IAC_START_C45 | PHY_IAC_READ_C45 |
++ (phy_addr << PHY_IAC_ADDR_SHIFT) |
++ (dev_num << PHY_IAC_REG_SHIFT),
++ MTK_PHY_IAC);
++ } else {
++ mtk_w32(eth, PHY_IAC_ACCESS | PHY_IAC_START | PHY_IAC_READ |
++ (phy_reg << PHY_IAC_REG_SHIFT) |
++ (phy_addr << PHY_IAC_ADDR_SHIFT),
++ MTK_PHY_IAC);
++ }
+
+ if (mtk_mdio_busy_wait(eth))
+ return 0xffff;
+@@ -584,6 +623,7 @@ static int mtk_mdio_init(struct mtk_eth
+ eth->mii_bus->name = "mdio";
+ eth->mii_bus->read = mtk_mdio_read;
+ eth->mii_bus->write = mtk_mdio_write;
++ eth->mii_bus->probe_capabilities = MDIOBUS_C22_C45;
+ eth->mii_bus->priv = eth;
+ eth->mii_bus->parent = eth->dev;
+
+--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h
++++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
+@@ -340,9 +340,12 @@
+ /* PHY Indirect Access Control registers */
+ #define MTK_PHY_IAC 0x10004
+ #define PHY_IAC_ACCESS BIT(31)
++#define PHY_IAC_SET_ADDR 0
+ #define PHY_IAC_READ BIT(19)
++#define PHY_IAC_READ_C45 (BIT(18) | BIT(19))
+ #define PHY_IAC_WRITE BIT(18)
+ #define PHY_IAC_START BIT(16)
++#define PHY_IAC_START_C45 0
+ #define PHY_IAC_ADDR_SHIFT 20
+ #define PHY_IAC_REG_SHIFT 25
+ #define PHY_IAC_TIMEOUT HZ
More information about the lede-commits
mailing list