[openwrt/openwrt] mediatek: backport latest pci/e driver from upstream
LEDE Commits
lede-commits at lists.infradead.org
Thu Jul 16 03:18:54 EDT 2020
blogic pushed a commit to openwrt/openwrt.git, branch master:
https://git.openwrt.org/eff87b8f9350ee49c572b1b048f1361e8ff23fef
commit eff87b8f9350ee49c572b1b048f1361e8ff23fef
Author: John Crispin <john at phrozen.org>
AuthorDate: Thu Jul 16 09:18:28 2020 +0200
mediatek: backport latest pci/e driver from upstream
Signed-off-by: John Crispin <john at phrozen.org>
---
.../mediatek/mt7622-bananapi-bpi-r64-rootdisk.dts | 20 +-
.../dts/mediatek/mt7622-elecom-wrc-2533gent.dts | 21 +-
...pi-bpi-r64-rootdisk.dts => mt7622-rfb1-ubi.dts} | 177 ++++++---
...bindings-PCI-Mediatek-Update-PCIe-binding.patch | 420 ++++++++++++++++++++
...ek-Use-regmap-to-get-shared-pcie-cfg-base.patch | 219 +++++++++++
...ediatek-Split-PCIe-node-for-MT2712-MT7622.patch | 423 +++++++++++++++++++++
...-ARM-dts-mediatek-Update-mt7629-PCIe-node.patch | 207 ++++++++++
7 files changed, 1400 insertions(+), 87 deletions(-)
diff --git a/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64-rootdisk.dts b/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64-rootdisk.dts
index 6a14ef369b..1638867604 100644
--- a/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64-rootdisk.dts
+++ b/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64-rootdisk.dts
@@ -257,18 +257,16 @@
};
};
-&pcie {
- pinctrl-names = "default";
- pinctrl-0 = <&pcie0_pins>, <&pcie1_pins>;
- status = "okay";
-
- pcie at 0,0 {
- status = "okay";
- };
+&pcie0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pcie0_pins>;
+ status = "okay";
+};
- pcie at 1,0 {
- status = "okay";
- };
+&pcie1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pcie1_pins>;
+ status = "okay";
};
&pio {
diff --git a/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7622-elecom-wrc-2533gent.dts b/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7622-elecom-wrc-2533gent.dts
index 224214e083..d905edc94f 100644
--- a/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7622-elecom-wrc-2533gent.dts
+++ b/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7622-elecom-wrc-2533gent.dts
@@ -165,19 +165,14 @@
};
};
-&pcie {
- pinctrl-names = "default", "pcie1_pins";
- pinctrl-0 = <&pcie0_pins>;
- pinctrl-1 = <&pcie1_pins>;
- status = "okay";
-
- pcie at 0,0 {
- status = "okay";
- mt7615 at 0,0 {
- reg = <0x0000 0 0 0 0>;
- mediatek,mtd-eeprom = <&factory 0x05000>;
- };
- };
+&pcie0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pcie0_pins>;
+ status = "okay";
+ mt7615 at 0,0 {
+ reg = <0x0000 0 0 0 0>;
+ mediatek,mtd-eeprom = <&factory 0x05000>;
+ };
};
&pio {
diff --git a/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64-rootdisk.dts b/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7622-rfb1-ubi.dts
similarity index 79%
copy from target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64-rootdisk.dts
copy to target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7622-rfb1-ubi.dts
index 6a14ef369b..f64a882370 100644
--- a/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64-rootdisk.dts
+++ b/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7622-rfb1-ubi.dts
@@ -13,8 +13,8 @@
#include "mt6380.dtsi"
/ {
- model = "Bananapi BPI-R64";
- compatible = "bananapi,bpi-r64-rootdisk", "mediatek,mt7622";
+ model = "MT7622_MT7531 RFB";
+ compatible = "mediatek,mt7622,ubi";
aliases {
serial0 = &uart0;
@@ -22,7 +22,7 @@
chosen {
stdout-path = "serial0:115200n8";
- bootargs = "earlycon=uart8250,mmio32,0x11002000 console=ttyS0,115200n1 swiotlb=512 root=/dev/mmcblk0p7 rootfstype=squashfs,f2fs";
+ bootargs = "earlycon=uart8250,mmio32,0x11002000 console=ttyS0,115200n1 swiotlb=512";
};
cpus {
@@ -53,6 +53,13 @@
};
};
+ gsw: gsw at 0 {
+ compatible = "mediatek,mt753x";
+ mediatek,ethsys = <ðsys>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
leds {
compatible = "gpio-leds";
@@ -101,7 +108,7 @@
};
&bch {
- status = "disabled";
+ status = "okay";
};
&btif {
@@ -143,59 +150,39 @@
mdio: mdio-bus {
#address-cells = <1>;
#size-cells = <0>;
-
- switch at 1f {
- compatible = "mediatek,mt7531";
- reg = <0x1f>;
- reset-gpios = <&pio 54 0>;
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- wan: port at 0 {
- reg = <0>;
- label = "wan";
- };
-
- port at 1 {
- reg = <1>;
- label = "lan0";
- };
-
- port at 2 {
- reg = <2>;
- label = "lan1";
- };
-
- port at 3 {
- reg = <3>;
- label = "lan2";
- };
-
- port at 4 {
- reg = <4>;
- label = "lan3";
- };
-
- port at 6 {
- reg = <6>;
- label = "cpu";
- ethernet = <&gmac0>;
- phy-mode = "2500base-x";
-
- fixed-link {
- speed = <2500>;
- full-duplex;
- pause;
- };
- };
- };
- };
-
};
};
+&gsw {
+ mediatek,mdio = <&mdio>;
+ mediatek,portmap = "llllw";
+ mediatek,mdio_master_pinmux = <0>;
+ reset-gpios = <&pio 54 0>;
+ interrupt-parent = <&pio>;
+ interrupts = <53 IRQ_TYPE_LEVEL_HIGH>;
+ status = "okay";
+
+ port5: port at 5 {
+ compatible = "mediatek,mt753x-port";
+ reg = <5>;
+ phy-mode = "rgmii";
+ fixed-link {
+ speed = <1000>;
+ full-duplex;
+ };
+ };
+
+ port6: port at 6 {
+ compatible = "mediatek,mt753x-port";
+ reg = <6>;
+ phy-mode = "sgmii";
+ fixed-link {
+ speed = <2500>;
+ full-duplex;
+ };
+ };
+};
+
&i2c1 {
pinctrl-names = "default";
pinctrl-0 = <&i2c1_pins>;
@@ -257,18 +244,16 @@
};
};
-&pcie {
+&pcie0 {
pinctrl-names = "default";
- pinctrl-0 = <&pcie0_pins>, <&pcie1_pins>;
+ pinctrl-0 = <&pcie0_pins>;
status = "okay";
+};
- pcie at 0,0 {
- status = "okay";
- };
-
- pcie at 1,0 {
- status = "okay";
- };
+&pcie1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pcie1_pins>;
+ status = "okay";
};
&pio {
@@ -554,6 +539,67 @@
status = "disable";
};
+&snfi {
+ pinctrl-names = "default";
+ pinctrl-0 = <&serial_nand_pins>;
+ status = "okay";
+
+ spi_nand at 0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "spi-nand";
+ spi-max-frequency = <104000000>;
+ reg = <0>;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition at 0 {
+ label = "Preloader";
+ reg = <0x00000 0x0080000>;
+ read-only;
+ };
+
+ partition at 80000 {
+ label = "ATF";
+ reg = <0x80000 0x0040000>;
+ };
+
+ partition at c0000 {
+ label = "Bootloader";
+ reg = <0xc0000 0x0080000>;
+ };
+
+ partition at 140000 {
+ label = "Config";
+ reg = <0x140000 0x0080000>;
+ };
+
+ factory: partition at 1c0000 {
+ label = "Factory";
+ reg = <0x1c0000 0x0040000>;
+ };
+
+ partition at 200000 {
+ label = "kernel";
+ reg = <0x200000 0x400000>;
+ };
+
+ partition at 600000 {
+ label = "ubi";
+ reg = <0x600000 0x1C00000>;
+ };
+
+ partition at 2200000 {
+ label = "User_data";
+ reg = <0x2200000 0x4000000>;
+ };
+ };
+ };
+};
+
&spi0 {
pinctrl-names = "default";
pinctrl-0 = <&spic0_pins>;
@@ -593,3 +639,8 @@
pinctrl-0 = <&watchdog_pins>;
status = "okay";
};
+
+&wmac {
+ mediatek,mtd-eeprom = <&factory 0x0000>;
+ status = "okay";
+};
diff --git a/target/linux/mediatek/patches-5.4/0991-dt-bindings-PCI-Mediatek-Update-PCIe-binding.patch b/target/linux/mediatek/patches-5.4/0991-dt-bindings-PCI-Mediatek-Update-PCIe-binding.patch
new file mode 100755
index 0000000000..2c7e311836
--- /dev/null
+++ b/target/linux/mediatek/patches-5.4/0991-dt-bindings-PCI-Mediatek-Update-PCIe-binding.patch
@@ -0,0 +1,420 @@
+From patchwork Thu May 28 06:16:45 2020
+Content-Type: text/plain; charset="utf-8"
+MIME-Version: 1.0
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+X-Patchwork-Submitter: Chuanjia Liu <chuanjia.liu at mediatek.com>
+X-Patchwork-Id: 11574793
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+From: <chuanjia.liu at mediatek.com>
+To: <robh+dt at kernel.org>, <ryder.lee at mediatek.com>, <matthias.bgg at gmail.com>
+Subject: [PATCH v2 1/4] dt-bindings: PCI: Mediatek: Update PCIe binding
+Date: Thu, 28 May 2020 14:16:45 +0800
+Message-ID: <20200528061648.32078-2-chuanjia.liu at mediatek.com>
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+ srv_heupstream at mediatek.com, "chuanjia.liu" <Chuanjia.Liu at mediatek.com>,
+ linux-pci at vger.kernel.org, linux-kernel at vger.kernel.org,
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+
+From: "chuanjia.liu" <Chuanjia.Liu at mediatek.com>
+
+There are two independent PCIe controllers in MT2712/MT7622 platform,
+and each of them should contain an independent MSI domain.
+
+In current architecture, MSI domain will be inherited from the root
+bridge, and all of the devices will share the same MSI domain.
+Hence that, the PCIe devices will not work properly if the irq number
+which required is more than 32.
+
+Split the PCIe node for MT2712/MT7622 platform to fix MSI issue and
+comply with the hardware design.
+
+Signed-off-by: chuanjia.liu <Chuanjia.Liu at mediatek.com>
+---
+ .../bindings/pci/mediatek-pcie-cfg.yaml | 38 +++++
+ .../devicetree/bindings/pci/mediatek-pcie.txt | 144 +++++++++++-------
+ 2 files changed, 129 insertions(+), 53 deletions(-)
+ create mode 100644 Documentation/devicetree/bindings/pci/mediatek-pcie-cfg.yaml
+
+diff --git a/Documentation/devicetree/bindings/pci/mediatek-pcie-cfg.yaml b/Documentation/devicetree/bindings/pci/mediatek-pcie-cfg.yaml
+new file mode 100644
+index 000000000000..4d2835ab4858
+--- /dev/null
++++ b/Documentation/devicetree/bindings/pci/mediatek-pcie-cfg.yaml
+@@ -0,0 +1,38 @@
++# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
++%YAML 1.2
++---
++$id: http://devicetree.org/schemas/pci/mediatek-pcie-cfg.yaml#
++$schema: http://devicetree.org/meta-schemas/core.yaml#
++
++title: Mediatek PCIECFG controller
++
++maintainers:
++ - Chuanjia Liu <chuanjia.liu at mediatek.com>
++ - Jianjun Wang <jianjun.wang at mediatek.com>
++
++description: |
++ The MediaTek PCIECFG controller controls some feature about
++ LTSSM, ASPM and so on.
++
++properties:
++ compatible:
++ items:
++ - enum:
++ - mediatek,mt7622-pciecfg
++ - mediatek,mt7629-pciecfg
++ - const: syscon
++
++ reg:
++ maxItems: 1
++
++required:
++ - compatible
++ - reg
++
++examples:
++ - |
++ pciecfg: pciecfg at 1a140000 {
++ compatible = "mediatek,mt7622-pciecfg", "syscon";
++ reg = <0 0x1a140000 0 0x1000>;
++ };
++...
+diff --git a/Documentation/devicetree/bindings/pci/mediatek-pcie.txt b/Documentation/devicetree/bindings/pci/mediatek-pcie.txt
+index 7468d666763a..ddae110d4379 100644
+--- a/Documentation/devicetree/bindings/pci/mediatek-pcie.txt
++++ b/Documentation/devicetree/bindings/pci/mediatek-pcie.txt
+@@ -8,7 +8,7 @@ Required properties:
+ "mediatek,mt7623-pcie"
+ "mediatek,mt7629-pcie"
+ - device_type: Must be "pci"
+-- reg: Base addresses and lengths of the PCIe subsys and root ports.
++- reg: Base addresses and lengths of the root ports.
+ - reg-names: Names of the above areas to use during resource lookup.
+ - #address-cells: Address representation for root ports (must be 3)
+ - #size-cells: Size representation for root ports (must be 2)
+@@ -19,10 +19,10 @@ Required properties:
+ - sys_ckN :transaction layer and data link layer clock
+ Required entries for MT2701/MT7623:
+ - free_ck :for reference clock of PCIe subsys
+- Required entries for MT2712/MT7622:
++ Required entries for MT2712/MT7622/MT7629:
+ - ahb_ckN :AHB slave interface operating clock for CSR access and RC
+ initiated MMIO access
+- Required entries for MT7622:
++ Required entries for MT7622/MT7629:
+ - axi_ckN :application layer MMIO channel operating clock
+ - aux_ckN :pe2_mac_bridge and pe2_mac_core operating clock when
+ pcie_mac_ck/pcie_pipe_ck is turned off
+@@ -47,10 +47,13 @@ Required properties for MT7623/MT2701:
+ - reset-names: Must be "pcie-rst0", "pcie-rst1", "pcie-rstN".. based on the
+ number of root ports.
+
+-Required properties for MT2712/MT7622:
++Required properties for MT2712/MT7622/MT7629:
+ -interrupts: A list of interrupt outputs of the controller, must have one
+ entry for each PCIe port
+
++Required properties for MT7622/MT7629:
++- mediatek,pcie-subsys: Should be a phandle of the pciecfg node.
++
+ In addition, the device tree node must have sub-nodes describing each
+ PCIe port interface, having the following mandatory properties:
+
+@@ -143,56 +146,73 @@ Examples for MT7623:
+
+ Examples for MT2712:
+
+- pcie: pcie at 11700000 {
++ pcie1: pcie at 112ff000 {
+ compatible = "mediatek,mt2712-pcie";
+ device_type = "pci";
+- reg = <0 0x11700000 0 0x1000>,
+- <0 0x112ff000 0 0x1000>;
+- reg-names = "port0", "port1";
++ reg = <0 0x112ff000 0 0x1000>;
++ reg-names = "port1";
+ #address-cells = <3>;
+ #size-cells = <2>;
+- interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
+- <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
+- clocks = <&topckgen CLK_TOP_PE2_MAC_P0_SEL>,
+- <&topckgen CLK_TOP_PE2_MAC_P1_SEL>,
+- <&pericfg CLK_PERI_PCIE0>,
++ interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
++ interrupt-names = "pcie_irq";
++ clocks = <&topckgen CLK_TOP_PE2_MAC_P1_SEL>,
+ <&pericfg CLK_PERI_PCIE1>;
+- clock-names = "sys_ck0", "sys_ck1", "ahb_ck0", "ahb_ck1";
+- phys = <&pcie0_phy PHY_TYPE_PCIE>, <&pcie1_phy PHY_TYPE_PCIE>;
+- phy-names = "pcie-phy0", "pcie-phy1";
++ clock-names = "sys_ck1", "ahb_ck1";
++ phys = <&u3port1 PHY_TYPE_PCIE>;
++ phy-names = "pcie-phy1";
+ bus-range = <0x00 0xff>;
+- ranges = <0x82000000 0 0x20000000 0x0 0x20000000 0 0x10000000>;
++ ranges = <0x82000000 0 0x11400000 0x0 0x11400000 0 0x300000>;
++ status = "disabled";
+
+- pcie0: pcie at 0,0 {
+- reg = <0x0000 0 0 0 0>;
++ slot1: pcie at 1,0 {
++ reg = <0x0800 0 0 0 0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ #interrupt-cells = <1>;
+ ranges;
+ interrupt-map-mask = <0 0 0 7>;
+- interrupt-map = <0 0 0 1 &pcie_intc0 0>,
+- <0 0 0 2 &pcie_intc0 1>,
+- <0 0 0 3 &pcie_intc0 2>,
+- <0 0 0 4 &pcie_intc0 3>;
+- pcie_intc0: interrupt-controller {
++ interrupt-map = <0 0 0 1 &pcie_intc1 0>,
++ <0 0 0 2 &pcie_intc1 1>,
++ <0 0 0 3 &pcie_intc1 2>,
++ <0 0 0 4 &pcie_intc1 3>;
++ pcie_intc1: interrupt-controller {
+ interrupt-controller;
+ #address-cells = <0>;
+ #interrupt-cells = <1>;
+ };
+ };
++ };
+
+- pcie1: pcie at 1,0 {
+- reg = <0x0800 0 0 0 0>;
++ pcie0: pcie at 11700000 {
++ compatible = "mediatek,mt2712-pcie";
++ device_type = "pci";
++ reg = <0 0x11700000 0 0x1000>;
++ reg-names = "port0";
++ #address-cells = <3>;
++ #size-cells = <2>;
++ interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
++ interrupt-names = "pcie_irq";
++ clocks = <&topckgen CLK_TOP_PE2_MAC_P0_SEL>,
++ <&pericfg CLK_PERI_PCIE0>;
++ clock-names = "sys_ck0", "ahb_ck0";
++ phys = <&u3port0 PHY_TYPE_PCIE>;
++ phy-names = "pcie-phy0";
++ bus-range = <0x00 0xff>;
++ ranges = <0x82000000 0 0x20000000 0x0 0x20000000 0 0x10000000>;
++ status = "disabled";
++
++ slot0: pcie at 0,0 {
++ reg = <0x0000 0 0 0 0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ #interrupt-cells = <1>;
+ ranges;
+ interrupt-map-mask = <0 0 0 7>;
+- interrupt-map = <0 0 0 1 &pcie_intc1 0>,
+- <0 0 0 2 &pcie_intc1 1>,
+- <0 0 0 3 &pcie_intc1 2>,
+- <0 0 0 4 &pcie_intc1 3>;
+- pcie_intc1: interrupt-controller {
++ interrupt-map = <0 0 0 1 &pcie_intc0 0>,
++ <0 0 0 2 &pcie_intc0 1>,
++ <0 0 0 3 &pcie_intc0 2>,
++ <0 0 0 4 &pcie_intc0 3>;
++ pcie_intc0: interrupt-controller {
+ interrupt-controller;
+ #address-cells = <0>;
+ #interrupt-cells = <1>;
+@@ -202,39 +222,31 @@ Examples for MT2712:
+
+ Examples for MT7622:
+
+- pcie: pcie at 1a140000 {
++ pcie0: pcie at 1a143000 {
+ compatible = "mediatek,mt7622-pcie";
+ device_type = "pci";
+- reg = <0 0x1a140000 0 0x1000>,
+- <0 0x1a143000 0 0x1000>,
+- <0 0x1a145000 0 0x1000>;
+- reg-names = "subsys", "port0", "port1";
++ reg = <0 0x1a143000 0 0x1000>;
++ reg-names = "port0";
++ mediatek,pcie-cfg = <&pciecfg>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+- interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_LOW>,
+- <GIC_SPI 229 IRQ_TYPE_LEVEL_LOW>;
++ interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_LOW>;
++ interrupt-names = "pcie_irq";
+ clocks = <&pciesys CLK_PCIE_P0_MAC_EN>,
+- <&pciesys CLK_PCIE_P1_MAC_EN>,
+ <&pciesys CLK_PCIE_P0_AHB_EN>,
+- <&pciesys CLK_PCIE_P1_AHB_EN>,
+ <&pciesys CLK_PCIE_P0_AUX_EN>,
+- <&pciesys CLK_PCIE_P1_AUX_EN>,
+ <&pciesys CLK_PCIE_P0_AXI_EN>,
+- <&pciesys CLK_PCIE_P1_AXI_EN>,
+ <&pciesys CLK_PCIE_P0_OBFF_EN>,
+- <&pciesys CLK_PCIE_P1_OBFF_EN>,
+- <&pciesys CLK_PCIE_P0_PIPE_EN>,
+- <&pciesys CLK_PCIE_P1_PIPE_EN>;
+- clock-names = "sys_ck0", "sys_ck1", "ahb_ck0", "ahb_ck1",
+- "aux_ck0", "aux_ck1", "axi_ck0", "axi_ck1",
+- "obff_ck0", "obff_ck1", "pipe_ck0", "pipe_ck1";
+- phys = <&pcie0_phy PHY_TYPE_PCIE>, <&pcie1_phy PHY_TYPE_PCIE>;
+- phy-names = "pcie-phy0", "pcie-phy1";
++ <&pciesys CLK_PCIE_P0_PIPE_EN>;
++ clock-names = "sys_ck0", "ahb_ck0", "aux_ck0",
++ "axi_ck0", "obff_ck0", "pipe_ck0";
++
+ power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF0>;
+ bus-range = <0x00 0xff>;
+- ranges = <0x82000000 0 0x20000000 0x0 0x20000000 0 0x10000000>;
++ ranges = <0x82000000 0 0x20000000 0 0x20000000 0 0x8000000>;
++ status = "disabled";
+
+- pcie0: pcie at 0,0 {
++ slot0: pcie at 0,0 {
+ reg = <0x0000 0 0 0 0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+@@ -251,8 +263,34 @@ Examples for MT7622:
+ #interrupt-cells = <1>;
+ };
+ };
++ };
++
++ pcie1: pcie at 1a145000 {
++ compatible = "mediatek,mt7622-pcie";
++ device_type = "pci";
++ reg = <0 0x1a145000 0 0x1000>;
++ reg-names = "port1";
++ mediatek,pcie-cfg = <&pciecfg>;
++ #address-cells = <3>;
++ #size-cells = <2>;
++ interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_LOW>;
++ interrupt-names = "pcie_irq";
++ clocks = <&pciesys CLK_PCIE_P1_MAC_EN>,
++ /* designer has connect RC1 with p0_ahb clock */
++ <&pciesys CLK_PCIE_P0_AHB_EN>,
++ <&pciesys CLK_PCIE_P1_AUX_EN>,
++ <&pciesys CLK_PCIE_P1_AXI_EN>,
++ <&pciesys CLK_PCIE_P1_OBFF_EN>,
++ <&pciesys CLK_PCIE_P1_PIPE_EN>;
++ clock-names = "sys_ck1", "ahb_ck1", "aux_ck1",
++ "axi_ck1", "obff_ck1", "pipe_ck1";
++
++ power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF0>;
++ bus-range = <0x00 0xff>;
++ ranges = <0x82000000 0 0x28000000 0 0x28000000 0 0x8000000>;
++ status = "disabled";
+
+- pcie1: pcie at 1,0 {
++ slot1: pcie at 1,0 {
+ reg = <0x0800 0 0 0 0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
diff --git a/target/linux/mediatek/patches-5.4/0992-PCI-mediatek-Use-regmap-to-get-shared-pcie-cfg-base.patch b/target/linux/mediatek/patches-5.4/0992-PCI-mediatek-Use-regmap-to-get-shared-pcie-cfg-base.patch
new file mode 100755
index 0000000000..e773e2e676
--- /dev/null
+++ b/target/linux/mediatek/patches-5.4/0992-PCI-mediatek-Use-regmap-to-get-shared-pcie-cfg-base.patch
@@ -0,0 +1,219 @@
+From patchwork Thu May 28 06:16:46 2020
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+From: <chuanjia.liu at mediatek.com>
+To: <robh+dt at kernel.org>, <ryder.lee at mediatek.com>, <matthias.bgg at gmail.com>
+Subject: [PATCH v2 2/4] PCI: mediatek: Use regmap to get shared pcie-cfg base
+Date: Thu, 28 May 2020 14:16:46 +0800
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+From: "chuanjia.liu" <Chuanjia.Liu at mediatek.com>
+
+Use regmap to get shared pcie-cfg base and change
+the method to get pcie irq.
+
+Signed-off-by: chuanjia.liu <Chuanjia.Liu at mediatek.com>
+---
+ drivers/pci/controller/pcie-mediatek.c | 25 ++++++++++++++++++-------
+ 1 file changed, 18 insertions(+), 7 deletions(-)
+
+diff --git a/drivers/pci/controller/pcie-mediatek.c b/drivers/pci/controller/pcie-mediatek.c
+index cb982891b22b..2268d6073eb6 100644
+--- a/drivers/pci/controller/pcie-mediatek.c
++++ b/drivers/pci/controller/pcie-mediatek.c
+@@ -14,6 +14,7 @@
+ #include <linux/irqchip/chained_irq.h>
+ #include <linux/irqdomain.h>
+ #include <linux/kernel.h>
++#include <linux/mfd/syscon.h>
+ #include <linux/msi.h>
+ #include <linux/module.h>
+ #include <linux/of_address.h>
+@@ -23,6 +24,7 @@
+ #include <linux/phy/phy.h>
+ #include <linux/platform_device.h>
+ #include <linux/pm_runtime.h>
++#include <linux/regmap.h>
+ #include <linux/reset.h>
+
+ #include "../pci.h"
+@@ -205,6 +207,7 @@ struct mtk_pcie_port {
+ * struct mtk_pcie - PCIe host information
+ * @dev: pointer to PCIe device
+ * @base: IO mapped register base
++ * @cfg: IO mapped register map for PCIe config
+ * @free_ck: free-run reference clock
+ * @mem: non-prefetchable memory resource
+ * @ports: pointer to PCIe port information
+@@ -214,6 +217,7 @@ struct mtk_pcie_port {
+ struct mtk_pcie {
+ struct device *dev;
+ void __iomem *base;
++ struct regmap *cfg;
+ struct clk *free_ck;
+
+ struct list_head ports;
+@@ -650,7 +654,7 @@ static int mtk_pcie_setup_irq(struct mtk_pcie_port *port,
+ return err;
+ }
+
+- port->irq = platform_get_irq(pdev, port->slot);
++ port->irq = platform_get_irq_byname(pdev, "pcie_irq");
+ irq_set_chained_handler_and_data(port->irq,
+ mtk_pcie_intr_handler, port);
+
+@@ -673,12 +677,11 @@ static int mtk_pcie_startup_port_v2(struct mtk_pcie_port *port)
+ if (!mem)
+ return -EINVAL;
+
+- /* MT7622 platforms need to enable LTSSM and ASPM from PCIe subsys */
+- if (pcie->base) {
+- val = readl(pcie->base + PCIE_SYS_CFG_V2);
+- val |= PCIE_CSR_LTSSM_EN(port->slot) |
+- PCIE_CSR_ASPM_L1_EN(port->slot);
+- writel(val, pcie->base + PCIE_SYS_CFG_V2);
++ /* MT7622/MT7629 platforms need to enable LTSSM and ASPM. */
++ if (pcie->cfg) {
++ val = PCIE_CSR_LTSSM_EN(port->slot) |
++ PCIE_CSR_ASPM_L1_EN(port->slot);
++ regmap_update_bits(pcie->cfg, PCIE_SYS_CFG_V2, val, val);
+ }
+
+ /* Assert all reset signals */
+@@ -984,6 +987,7 @@ static int mtk_pcie_subsys_powerup(struct mtk_pcie *pcie)
+ struct device *dev = pcie->dev;
+ struct platform_device *pdev = to_platform_device(dev);
+ struct resource *regs;
++ struct device_node *cfg_node;
+ int err;
+
+ /* get shared registers, which are optional */
+@@ -996,6 +1000,13 @@ static int mtk_pcie_subsys_powerup(struct mtk_pcie *pcie)
+ }
+ }
+
++ cfg_node = of_parse_phandle(dev->of_node, "mediatek,pcie-cfg", 0);
++ if (cfg_node) {
++ pcie->cfg = syscon_node_to_regmap(cfg_node);
++ if (IS_ERR(pcie->cfg))
++ return PTR_ERR(pcie->cfg);
++ }
++
+ pcie->free_ck = devm_clk_get(dev, "free_ck");
+ if (IS_ERR(pcie->free_ck)) {
+ if (PTR_ERR(pcie->free_ck) == -EPROBE_DEFER)
diff --git a/target/linux/mediatek/patches-5.4/0993-arm64-dts-mediatek-Split-PCIe-node-for-MT2712-MT7622.patch b/target/linux/mediatek/patches-5.4/0993-arm64-dts-mediatek-Split-PCIe-node-for-MT2712-MT7622.patch
new file mode 100755
index 0000000000..7d3c55c0e4
--- /dev/null
+++ b/target/linux/mediatek/patches-5.4/0993-arm64-dts-mediatek-Split-PCIe-node-for-MT2712-MT7622.patch
@@ -0,0 +1,423 @@
+From patchwork Thu May 28 06:16:47 2020
+Content-Type: text/plain; charset="utf-8"
+MIME-Version: 1.0
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+From: <chuanjia.liu at mediatek.com>
+To: <robh+dt at kernel.org>, <ryder.lee at mediatek.com>, <matthias.bgg at gmail.com>
+Subject: [PATCH v2 3/4] arm64: dts: mediatek: Split PCIe node for
+ MT2712/MT7622
+Date: Thu, 28 May 2020 14:16:47 +0800
+Message-ID: <20200528061648.32078-4-chuanjia.liu at mediatek.com>
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+ srv_heupstream at mediatek.com, "chuanjia.liu" <Chuanjia.Liu at mediatek.com>,
+ linux-pci at vger.kernel.org, linux-kernel at vger.kernel.org,
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+
+From: "chuanjia.liu" <Chuanjia.Liu at mediatek.com>
+
+There are two independent PCIe controllers in MT2712/MT7622 platform,
+and each of them should contain an independent MSI domain.
+
+In current architecture, MSI domain will be inherited from the root
+bridge, and all of the devices will share the same MSI domain.
+Hence that, the PCIe devices will not work properly if the irq number
+which required is more than 32.
+
+Split the PCIe node for MT2712/MT7622 platform to fix MSI issue and
+comply with the hardware design.
+
+Signed-off-by: chuanjia.liu <Chuanjia.Liu at mediatek.com>
+---
+ arch/arm64/boot/dts/mediatek/mt2712e.dtsi | 75 +++++++++++--------
+ .../dts/mediatek/mt7622-bananapi-bpi-r64.dts | 16 ++--
+ arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts | 6 +-
+ arch/arm64/boot/dts/mediatek/mt7622.dtsi | 68 +++++++++++------
+ 4 files changed, 96 insertions(+), 69 deletions(-)
+
+diff --git a/arch/arm64/boot/dts/mediatek/mt2712e.dtsi b/arch/arm64/boot/dts/mediatek/mt2712e.dtsi
+index 2cd8b33886e5..ab27ff4a869e 100644
+--- a/arch/arm64/boot/dts/mediatek/mt2712e.dtsi
++++ b/arch/arm64/boot/dts/mediatek/mt2712e.dtsi
+@@ -797,60 +797,73 @@
+ };
+ };
+
+- pcie: pcie at 11700000 {
++ pcie1: pcie at 112ff000 {
+ compatible = "mediatek,mt2712-pcie";
+ device_type = "pci";
+- reg = <0 0x11700000 0 0x1000>,
+- <0 0x112ff000 0 0x1000>;
+- reg-names = "port0", "port1";
++ reg = <0 0x112ff000 0 0x1000>;
++ reg-names = "port1";
+ #address-cells = <3>;
+ #size-cells = <2>;
+- interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
+- <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
+- clocks = <&topckgen CLK_TOP_PE2_MAC_P0_SEL>,
+- <&topckgen CLK_TOP_PE2_MAC_P1_SEL>,
+- <&pericfg CLK_PERI_PCIE0>,
++ interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
++ interrupt-names = "pcie_irq";
++ clocks = <&topckgen CLK_TOP_PE2_MAC_P1_SEL>,
+ <&pericfg CLK_PERI_PCIE1>;
+- clock-names = "sys_ck0", "sys_ck1", "ahb_ck0", "ahb_ck1";
+- phys = <&u3port0 PHY_TYPE_PCIE>, <&u3port1 PHY_TYPE_PCIE>;
+- phy-names = "pcie-phy0", "pcie-phy1";
++ clock-names = "sys_ck1", "ahb_ck1";
++ phys = <&u3port1 PHY_TYPE_PCIE>;
++ phy-names = "pcie-phy1";
+ bus-range = <0x00 0xff>;
+- ranges = <0x82000000 0 0x20000000 0x0 0x20000000 0 0x10000000>;
++ ranges = <0x82000000 0 0x11400000 0x0 0x11400000 0 0x300000>;
++ status = "disabled";
+
+- pcie0: pcie at 0,0 {
+- device_type = "pci";
+- status = "disabled";
+- reg = <0x0000 0 0 0 0>;
++ slot1: pcie at 1,0 {
++ reg = <0x0800 0 0 0 0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ #interrupt-cells = <1>;
+ ranges;
+ interrupt-map-mask = <0 0 0 7>;
+- interrupt-map = <0 0 0 1 &pcie_intc0 0>,
+- <0 0 0 2 &pcie_intc0 1>,
+- <0 0 0 3 &pcie_intc0 2>,
+- <0 0 0 4 &pcie_intc0 3>;
+- pcie_intc0: interrupt-controller {
++ interrupt-map = <0 0 0 1 &pcie_intc1 0>,
++ <0 0 0 2 &pcie_intc1 1>,
++ <0 0 0 3 &pcie_intc1 2>,
++ <0 0 0 4 &pcie_intc1 3>;
++ pcie_intc1: interrupt-controller {
+ interrupt-controller;
+ #address-cells = <0>;
+ #interrupt-cells = <1>;
+ };
+ };
++ };
+
+- pcie1: pcie at 1,0 {
+- device_type = "pci";
+- status = "disabled";
+- reg = <0x0800 0 0 0 0>;
++ pcie0: pcie at 11700000 {
++ compatible = "mediatek,mt2712-pcie";
++ device_type = "pci";
++ reg = <0 0x11700000 0 0x1000>;
++ reg-names = "port0";
++ #address-cells = <3>;
++ #size-cells = <2>;
++ interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
++ interrupt-names = "pcie_irq";
++ clocks = <&topckgen CLK_TOP_PE2_MAC_P0_SEL>,
++ <&pericfg CLK_PERI_PCIE0>;
++ clock-names = "sys_ck0", "ahb_ck0";
++ phys = <&u3port0 PHY_TYPE_PCIE>;
++ phy-names = "pcie-phy0";
++ bus-range = <0x00 0xff>;
++ ranges = <0x82000000 0 0x20000000 0x0 0x20000000 0 0x10000000>;
++ status = "disabled";
++
++ slot0: pcie at 0,0 {
++ reg = <0x0000 0 0 0 0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ #interrupt-cells = <1>;
+ ranges;
+ interrupt-map-mask = <0 0 0 7>;
+- interrupt-map = <0 0 0 1 &pcie_intc1 0>,
+- <0 0 0 2 &pcie_intc1 1>,
+- <0 0 0 3 &pcie_intc1 2>,
+- <0 0 0 4 &pcie_intc1 3>;
+- pcie_intc1: interrupt-controller {
++ interrupt-map = <0 0 0 1 &pcie_intc0 0>,
++ <0 0 0 2 &pcie_intc0 1>,
++ <0 0 0 3 &pcie_intc0 2>,
++ <0 0 0 4 &pcie_intc0 3>;
++ pcie_intc0: interrupt-controller {
+ interrupt-controller;
+ #address-cells = <0>;
+ #interrupt-cells = <1>;
+diff --git a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
+index 83e10591e0e5..7574d88cc46a 100644
+--- a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
++++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
+@@ -207,18 +207,16 @@
+ };
+ };
+
+-&pcie {
++&pcie0 {
+ pinctrl-names = "default";
+- pinctrl-0 = <&pcie0_pins>, <&pcie1_pins>;
++ pinctrl-0 = <&pcie0_pins>;
+ status = "okay";
++};
+
+- pcie at 0,0 {
+- status = "okay";
+- };
+-
+- pcie at 1,0 {
+- status = "okay";
+- };
++&pcie1 {
++ pinctrl-names = "default";
++ pinctrl-0 = <&pcie1_pins>;
++ status = "okay";
+ };
+
+ &pio {
+diff --git a/arch/arm64/boot/dts/mediatek/mt7622.dtsi b/arch/arm64/boot/dts/mediatek/mt7622.dtsi
+index 339dc9f88f43..d5131c8b6a79 100644
+--- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi
++++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi
+@@ -766,45 +766,41 @@
+ #reset-cells = <1>;
+ };
+
+- pcie: pcie at 1a140000 {
++ pciecfg: pciecfg at 1a140000 {
++ compatible = "mediatek,mt7622-pciecfg", "syscon";
++ reg = <0 0x1a140000 0 0x1000>;
++ };
++
++ pcie0: pcie at 1a143000 {
+ compatible = "mediatek,mt7622-pcie";
+ device_type = "pci";
+- reg = <0 0x1a140000 0 0x1000>,
+- <0 0x1a143000 0 0x1000>,
+- <0 0x1a145000 0 0x1000>;
+- reg-names = "subsys", "port0", "port1";
++ reg = <0 0x1a143000 0 0x1000>;
++ reg-names = "port0";
++ mediatek,pcie-cfg = <&pciecfg>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+- interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_LOW>,
+- <GIC_SPI 229 IRQ_TYPE_LEVEL_LOW>;
++ interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_LOW>;
++ interrupt-names = "pcie_irq";
+ clocks = <&pciesys CLK_PCIE_P0_MAC_EN>,
+- <&pciesys CLK_PCIE_P1_MAC_EN>,
+- <&pciesys CLK_PCIE_P0_AHB_EN>,
+ <&pciesys CLK_PCIE_P0_AHB_EN>,
+ <&pciesys CLK_PCIE_P0_AUX_EN>,
+- <&pciesys CLK_PCIE_P1_AUX_EN>,
+ <&pciesys CLK_PCIE_P0_AXI_EN>,
+- <&pciesys CLK_PCIE_P1_AXI_EN>,
+ <&pciesys CLK_PCIE_P0_OBFF_EN>,
+- <&pciesys CLK_PCIE_P1_OBFF_EN>,
+- <&pciesys CLK_PCIE_P0_PIPE_EN>,
+- <&pciesys CLK_PCIE_P1_PIPE_EN>;
+- clock-names = "sys_ck0", "sys_ck1", "ahb_ck0", "ahb_ck1",
+- "aux_ck0", "aux_ck1", "axi_ck0", "axi_ck1",
+- "obff_ck0", "obff_ck1", "pipe_ck0", "pipe_ck1";
++ <&pciesys CLK_PCIE_P0_PIPE_EN>;
++ clock-names = "sys_ck0", "ahb_ck0", "aux_ck0",
++ "axi_ck0", "obff_ck0", "pipe_ck0";
++
+ power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF0>;
+ bus-range = <0x00 0xff>;
+- ranges = <0x82000000 0 0x20000000 0x0 0x20000000 0 0x10000000>;
++ ranges = <0x82000000 0 0x20000000 0x0 0x20000000 0 0x8000000>;
+ status = "disabled";
+
+- pcie0: pcie at 0,0 {
++ slot0: pcie at 0,0 {
+ reg = <0x0000 0 0 0 0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ #interrupt-cells = <1>;
+ ranges;
+- status = "disabled";
+-
+ interrupt-map-mask = <0 0 0 7>;
+ interrupt-map = <0 0 0 1 &pcie_intc0 0>,
+ <0 0 0 2 &pcie_intc0 1>,
+@@ -816,15 +812,39 @@
+ #interrupt-cells = <1>;
+ };
+ };
++ };
+
+- pcie1: pcie at 1,0 {
++ pcie1: pcie at 1a145000 {
++ compatible = "mediatek,mt7622-pcie";
++ device_type = "pci";
++ reg = <0 0x1a145000 0 0x1000>;
++ reg-names = "port1";
++ mediatek,pcie-cfg = <&pciecfg>;
++ #address-cells = <3>;
++ #size-cells = <2>;
++ interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_LOW>;
++ interrupt-names = "pcie_irq";
++ clocks = <&pciesys CLK_PCIE_P1_MAC_EN>,
++ /* designer has connect RC1 with p0_ahb clock */
++ <&pciesys CLK_PCIE_P0_AHB_EN>,
++ <&pciesys CLK_PCIE_P1_AUX_EN>,
++ <&pciesys CLK_PCIE_P1_AXI_EN>,
++ <&pciesys CLK_PCIE_P1_OBFF_EN>,
++ <&pciesys CLK_PCIE_P1_PIPE_EN>;
++ clock-names = "sys_ck1", "ahb_ck1", "aux_ck1",
++ "axi_ck1", "obff_ck1", "pipe_ck1";
++
++ power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF0>;
++ bus-range = <0x00 0xff>;
++ ranges = <0x82000000 0 0x28000000 0x0 0x28000000 0 0x8000000>;
++ status = "disabled";
++
++ slot1: pcie at 1,0 {
+ reg = <0x0800 0 0 0 0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ #interrupt-cells = <1>;
+ ranges;
+- status = "disabled";
+-
+ interrupt-map-mask = <0 0 0 7>;
+ interrupt-map = <0 0 0 1 &pcie_intc1 0>,
+ <0 0 0 2 &pcie_intc1 1>,
+--- a/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts 2020-06-15 18:52:25.092948824 +0800
++++ b/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts 2020-06-15 18:52:15.909094229 +0800
+@@ -244,18 +244,16 @@
+ };
+ };
+
+-&pcie {
++&pcie0 {
+ pinctrl-names = "default";
+- pinctrl-0 = <&pcie0_pins>, <&pcie1_pins>;
++ pinctrl-0 = <&pcie0_pins>;
+ status = "okay";
++};
+
+- pcie at 0,0 {
+- status = "okay";
+- };
+-
+- pcie at 1,0 {
+- status = "okay";
+- };
++&pcie1 {
++ pinctrl-names = "default";
++ pinctrl-0 = <&pcie1_pins>;
++ status = "okay";
+ };
+
+ &pio {
diff --git a/target/linux/mediatek/patches-5.4/0994-ARM-dts-mediatek-Update-mt7629-PCIe-node.patch b/target/linux/mediatek/patches-5.4/0994-ARM-dts-mediatek-Update-mt7629-PCIe-node.patch
new file mode 100755
index 0000000000..4ba99d89d0
--- /dev/null
+++ b/target/linux/mediatek/patches-5.4/0994-ARM-dts-mediatek-Update-mt7629-PCIe-node.patch
@@ -0,0 +1,207 @@
+From patchwork Thu May 28 06:16:48 2020
+Content-Type: text/plain; charset="utf-8"
+MIME-Version: 1.0
+Content-Transfer-Encoding: 7bit
+X-Patchwork-Submitter: Chuanjia Liu <chuanjia.liu at mediatek.com>
+X-Patchwork-Id: 11574797
+Return-Path:
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+From: <chuanjia.liu at mediatek.com>
+To: <robh+dt at kernel.org>, <ryder.lee at mediatek.com>, <matthias.bgg at gmail.com>
+Subject: [PATCH v2 4/4] ARM: dts: mediatek: Update mt7629 PCIe node
+Date: Thu, 28 May 2020 14:16:48 +0800
+Message-ID: <20200528061648.32078-5-chuanjia.liu at mediatek.com>
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+From: "chuanjia.liu" <Chuanjia.Liu at mediatek.com>
+
+Remove unused property and add pciecfg node.
+
+Signed-off-by: chuanjia.liu <Chuanjia.Liu at mediatek.com>
+---
+ arch/arm/boot/dts/mt7629-rfb.dts | 3 ++-
+ arch/arm/boot/dts/mt7629.dtsi | 23 +++++++++++++----------
+ 2 files changed, 15 insertions(+), 11 deletions(-)
+
+diff --git a/arch/arm/boot/dts/mt7629-rfb.dts b/arch/arm/boot/dts/mt7629-rfb.dts
+index 9980c10c6e29..eb536cbebd9b 100644
+--- a/arch/arm/boot/dts/mt7629-rfb.dts
++++ b/arch/arm/boot/dts/mt7629-rfb.dts
+@@ -140,9 +140,10 @@
+ };
+ };
+
+-&pcie {
++&pcie1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pcie_pins>;
++ status = "okay";
+ };
+
+ &pciephy1 {
+diff --git a/arch/arm/boot/dts/mt7629.dtsi b/arch/arm/boot/dts/mt7629.dtsi
+index 5cbb3d244c75..94567307b842 100644
+--- a/arch/arm/boot/dts/mt7629.dtsi
++++ b/arch/arm/boot/dts/mt7629.dtsi
+@@ -360,16 +360,21 @@
+ #reset-cells = <1>;
+ };
+
+- pcie: pcie at 1a140000 {
++ pciecfg: pciecfg at 1a140000 {
++ compatible = "mediatek,mt7629-pciecfg", "syscon";
++ reg = <0x1a140000 0x1000>;
++ };
++
++ pcie1: pcie at 1a145000 {
+ compatible = "mediatek,mt7629-pcie";
+ device_type = "pci";
+- reg = <0x1a140000 0x1000>,
+- <0x1a145000 0x1000>;
+- reg-names = "subsys","port1";
++ reg = <0x1a145000 0x1000>;
++ reg-names = "port1";
++ mediatek,pcie-cfg = <&pciecfg>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+- interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_LOW>,
+- <GIC_SPI 229 IRQ_TYPE_LEVEL_LOW>;
++ interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_LOW>;
++ interrupt-names = "pcie_irq";
+ clocks = <&pciesys CLK_PCIE_P1_MAC_EN>,
+ <&pciesys CLK_PCIE_P0_AHB_EN>,
+ <&pciesys CLK_PCIE_P1_AUX_EN>,
+@@ -390,21 +395,19 @@
+ power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF0>;
+ bus-range = <0x00 0xff>;
+ ranges = <0x82000000 0 0x20000000 0x20000000 0 0x10000000>;
++ status = "disabled";
+
+- pcie1: pcie at 1,0 {
+- device_type = "pci";
++ slot1: pcie at 1,0 {
+ reg = <0x0800 0 0 0 0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ #interrupt-cells = <1>;
+ ranges;
+- num-lanes = <1>;
+ interrupt-map-mask = <0 0 0 7>;
+ interrupt-map = <0 0 0 1 &pcie_intc1 0>,
+ <0 0 0 2 &pcie_intc1 1>,
+ <0 0 0 3 &pcie_intc1 2>,
+ <0 0 0 4 &pcie_intc1 3>;
+-
+ pcie_intc1: interrupt-controller {
+ interrupt-controller;
+ #address-cells = <0>;
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