[source] ar71xx: fix ethernet PLL configuration for QCA956x

[LEDE Commits]

nbd pushed a commit to source.git, branch master:
https://git.lede-project.org/72327d1757b53d36e97282451d3c4d10d99adfc8

commit 72327d1757b53d36e97282451d3c4d10d99adfc8
Author: Felix Fietkau <nbd at nbd.name>
AuthorDate: Fri Feb 17 11:51:42 2017 +0100

    ar71xx: fix ethernet PLL configuration for QCA956x
    
    QCA956x is configured like AR934x, not like the older chips.
    Should fix ethernet hangs when using the WAN port without SGMII
    
    Signed-off-by: Felix Fietkau <nbd at nbd.name>
---
 target/linux/ar71xx/files/arch/mips/ath79/dev-eth.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/target/linux/ar71xx/files/arch/mips/ath79/dev-eth.c b/target/linux/ar71xx/files/arch/mips/ath79/dev-eth.c
index 91ff8b2..a8b19b6 100644
--- a/target/linux/ar71xx/files/arch/mips/ath79/dev-eth.c
+++ b/target/linux/ar71xx/files/arch/mips/ath79/dev-eth.c
@@ -1096,7 +1096,7 @@ void __init ath79_register_eth(unsigned int id)
 			if (pdata->phy_if_mode == PHY_INTERFACE_MODE_SGMII)
 				pdata->set_speed = qca956x_set_speed_sgmii;
 			else
-				pdata->set_speed = ath79_set_speed_ge0;
+				pdata->set_speed = ar934x_set_speed_ge0;
 		} else {
 			pdata->reset_bit = QCA955X_RESET_GE1_MAC |
 					   QCA955X_RESET_GE1_MDIO;