[source] layerscape: uboot-layerscape: prefer github over git.freescale.com
LEDE Commits
lede-commits at lists.infradead.org
Mon Dec 12 01:00:41 PST 2016
blogic pushed a commit to source.git, branch master:
https://git.lede-project.org/d5fc7430ca293213dd4f1de7f52446c17d4def6a
commit d5fc7430ca293213dd4f1de7f52446c17d4def6a
Author: Yutang Jiang <yutang.jiang at nxp.com>
AuthorDate: Thu Dec 1 23:01:27 2016 +0800
layerscape: uboot-layerscape: prefer github over git.freescale.com
In order to prevent the impact of the merger of the company and the potential
rebase of the SDK repositories, migrate the u-boot source to github.
Signed-off-by: Yutang Jiang <yutang.jiang at nxp.com>
---
package/boot/uboot-layerscape/Makefile | 15 +-
...rt-loading-32-bit-OS-in-AArch32-execution.patch | 214 -
...2-armv8-SMP-support-for-loading-32-bit-OS.patch | 141 -
...32-Disable-CONFIG_FSL_LS_PPA-for-loading-.patch | 30 -
...rt-loading-32-bit-OS-which-is-not-in-the-.patch | 31 -
...penwrt-lede-default-boot-env-for-ls1043ar.patch | 68 -
...ayerscape-Put-SMMU-config-code-in-SMMU_BA.patch | 37 -
...-layerscape-Avoid-LS1043A-specifc-defines.patch | 44 -
...rmv8-ls1043a-Add-the-OCRAM-initialization.patch | 82 -
...-mtd-spi-Adding-support-for-QSPI-Emulator.patch | 29 -
...ver-mtd-spi-Adding-support-for-QSPI-flash.patch | 45 -
...sl-layerscape-fix-compile-warning-rcw_tmp.patch | 38 -
...-early-and-final-mmu-needs-matching-NS-at.patch | 58 -
...ayerscape-Add-support-of-QorIQ-LS1012A-So.patch | 418 --
...8-ls1012a-Add-support-of-ls1012aqds-board.patch | 1237 ----
...8-ls1012a-Add-support-of-ls1012ardb-board.patch | 634 --
...-ARM-asm-types-Introduce-DMA_ADDR_T_64BIT.patch | 80 -
...layerscape-add-dwc3-gadget-driver-support.patch | 465 --
...12aqds-Enable-SDHC_CD-in-brdcfg10-of-FPGA.patch | 62 -
...2a-Add-CSU-assignment-for-eSDHC2-SAI1-SAI.patch | 50 -
...20-armv8-ls1012a-Update-DDR-init-sequence.patch | 280 -
...e-Uniform-Sector-to-CR3NV-instead-of-CR3V.patch | 26 -
...-Rename-USB-controller-base-address-mappi.patch | 124 -
...23-drivers-usb-fsl-add-USB-ULPI-init-code.patch | 65 -
...12aqds-Add-USB-EHCI-support-for-ls1012aqd.patch | 67 -
...v8-ls1012ardb-Add-qspi-SECURE-BOOT-target.patch | 115 -
...onditionally-compile-IFC-based-qixis-func.patch | 38 -
...ixis-Add-flag-for-LBMAP-brdcfg-reg-offset.patch | 48 -
...12a-qixis-Add-support-for-qixis-subsystem.patch | 80 -
...mv8-ls1012a-Added-CSU-assignment-for-USB2.patch | 37 -
...-Enable-CPUECTLR.SMPEN-for-data-coherency.patch | 32 -
...sf-add-exceed-flash-16MB-support-for-qspi.patch | 308 -
...ver-spi-fsl_qspi-enable-AHB-read-for-qspi.patch | 30 -
..._esdhc-support-two-esdhc-host-controllers.patch | 47 -
...hc-add-workaround-for-non-removable-card-.patch | 57 -
...2a-enable-two-esdhc-host-controllers-supp.patch | 43 -
...-driver-spi-add-exceed-16MB-flash-support.patch | 144 -
...remove-Warning-prints-for-Spansion-FS-S-f.patch | 60 -
.../0038-Shift-board-specific-configurations.patch | 228 -
...-ls1012a-Add-support-of-ls1012afrdm-board.patch | 566 --
.../0040-DNCPE-138-CSU-config-for-PFE.patch | 36 -
.../patches/0041-DNCPE-4-LS1012A-PPFE-driver.patch | 7589 --------------------
.../0042-DNCPE-138-Rest-external-PHYs.patch | 69 -
.../0043-DNCPE-296-PFE-reset-workaround.patch | 334 -
...-layerscape-Add-support-of-GPIO-structure.patch | 48 -
...scale-ls1012afrdm-Add-support-of-Ethernet.patch | 155 -
.../0046-Correcting-address-for-PFE-Driver.patch | 29 -
.../0047-Enable-second-SGMII-1G-interface.patch | 61 -
.../0048-armv8-ls1012a-enable-sdhc2-support.patch | 44 -
.../0049-DNCPE-296-PFE-reset-woraround-fix.patch | 327 -
...8-Rest-external-PHYs-before-driver-starts.patch | 54 -
.../patches/0051-PPFE-warnings-Fix.patch | 283 -
...52-Add-Freescale-Copyright-in-PPFE-driver.patch | 688 --
...v8-arch-fsl-layerscape-Update-name-of-Soc.patch | 40 -
...4-armv8-fsl-layerscape-Update-DDR-timings.patch | 33 -
...5-Add-License-file-for-PPFE-firmware-bins.patch | 101 -
...hc-disable-sdhc2-when-no-card-inserted-fo.patch | 93 -
...Fix-DSPI-bug-after-adding-exceed-16MB-for.patch | 92 -
...hc-disable-sdhc2-when-no-card-inserted-fo.patch | 56 -
...2a-Make-FAT-and-EXT2-commands-support-com.patch | 110 -
.../0060-ls1012-sata-add-sata-support.patch | 58 -
...cale-Consolidate-PPA-flags-under-a-single.patch | 75 -
...Mv8-freescale-Fix-the-address-map-of-SCFG.patch | 27 -
...cale-ls1012a-Enable-secure-DDR-on-LS1012A.patch | 157 -
...cale-ls1012a-Intergrate-and-enable-PPA-on.patch | 64 -
...-ppa-Add-documentation-for-PPA-trusted-FW.patch | 47 -
...nable-UDP-checksum-for-proper-tftp-operat.patch | 113 -
.../0067-armv8-ls1012a-DDR-optmizations.patch | 90 -
...68-driver-pfe_eth-use-ifdef-instead-of-if.patch | 29 -
...rdm-Reset-external-PHYs-before-driver-sta.patch | 43 -
...2afrdm-overwrite-CONFIG_EXTRA_ENV_SETTING.patch | 45 -
...iver-fsl_qspi-disable-AHB-buffer-prefetch.patch | 58 -
...iver-spi-fsl-qspi-remove-compile-Warnings.patch | 44 -
...armv8-pfe-Change-MDIO-HOLDTIME-value-to-5.patch | 28 -
...cale-ls1012a-Intergrate-and-enable-PPA-on.patch | 65 -
...0075-arm-ls1012ardb-add-CONFIG_ARMV8_PSCI.patch | 28 -
...076-arm-ls1012afrdm-add-CONFIG_ARMV8_PSCI.patch | 25 -
...0077-board-ls1012aqds-Avoid-reset-masking.patch | 39 -
...2aqds-Update-LBMAP_MASK-and-RST_CTL_RESET.patch | 37 -
.../0079-armv8-pfe-Update-class-firmware.patch | 38 -
...PPA-Enable-PPA-validation-in-case-of-secu.patch | 54 -
...Update-blob-cmd-to-accept-64bit-addresses.patch | 79 -
.../0082-armv8-ls1012a-Update-DDR-timing.patch | 56 -
...ayerscape-Fix-the-conflict-between-PPA-an.patch | 120 -
...ayerscape-Moving-FSL_LS_PPA-flag-to-EXTRA.patch | 43 -
...ayerscape-Enable-FSL_LS_PPA-in-Secure-boo.patch | 28 -
...add-spansion-s25fs-s-family-protect-unpro.patch | 233 -
.../0087-armv8-ls1012a-Update-bootargs.patch | 30 -
...enable-stm_get_locked_range-for-spansion-.patch | 31 -
.../0089-driver-spi-fix-id-enclosure-error.patch | 27 -
...-add-CONFIG_SYS_FSL_MAX_NUM_OF_SEC-define.patch | 25 -
...ayerscape-ls1012ardb-configs-disable-FSL_.patch | 47 -
...penwrt-lede-default-boot-env-for-ls1012ar.patch | 67 -
...ap.tcl-script-for-uboot-can-run-save-in-q.patch | 70 -
...script-byte_swap.pl-to-replace-tcl-script.patch | 72 -
95 files changed, 9 insertions(+), 18498 deletions(-)
diff --git a/package/boot/uboot-layerscape/Makefile b/package/boot/uboot-layerscape/Makefile
index dd9ade6..17fd7f9 100644
--- a/package/boot/uboot-layerscape/Makefile
+++ b/package/boot/uboot-layerscape/Makefile
@@ -8,14 +8,17 @@
include $(TOPDIR)/rules.mk
include $(INCLUDE_DIR)/image.mk
-PKG_NAME:=fsl-sdk
-PKG_VERSION:=v2.0
+PKG_NAME:=uboot-layerscape
+PKG_VERSION:=v1.0
+PKG_RELEASE:=1
+
+PKG_SOURCE_PROTO:=git
PKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.bz2
-PKG_SOURCE_URL:= \
- http://git.freescale.com/git/cgit.cgi/ppc/sdk/u-boot.git/snapshot
-PKG_MD5SUM:=14f7ccc757bfa71c9b7fd68d24051231
+PKG_SOURCE_SUBDIR:=$(PKG_NAME)-$(PKG_VERSION)
+PKG_SOURCE_URL:=https://github.com/fsl-jyt/u-boot.git
+PKG_SOURCE_VERSION:=aefcbf4c2bb36e1f0ead61181e5fe1119b5683ad
-PKG_BUILD_DIR:=$(BUILD_DIR)/u-boot_$(PKG_NAME)-$(PKG_VERSION)-$(BUILD_VARIANT)/$(PKG_NAME)-$(PKG_VERSION)
+PKG_BUILD_DIR:=$(BUILD_DIR)/$(PKG_NAME)-$(PKG_VERSION)-$(BUILD_VARIANT)/$(PKG_NAME)-$(PKG_VERSION)
PKG_LICENSE:=GPL-2.0 GPL-2.0+
PKG_LICENSE_FILES:=Licenses/README
diff --git a/package/boot/uboot-layerscape/patches/0001-armv8-Support-loading-32-bit-OS-in-AArch32-execution.patch b/package/boot/uboot-layerscape/patches/0001-armv8-Support-loading-32-bit-OS-in-AArch32-execution.patch
deleted file mode 100644
index ace5428..0000000
--- a/package/boot/uboot-layerscape/patches/0001-armv8-Support-loading-32-bit-OS-in-AArch32-execution.patch
+++ /dev/null
@@ -1,214 +0,0 @@
-From e03f571b1e9564ca422134b2013d80c8373c9db2 Mon Sep 17 00:00:00 2001
-From: Alison Wang <b18965 at freescale.com>
-Date: Fri, 13 May 2016 10:19:24 +0800
-Subject: [PATCH 01/93] armv8: Support loading 32-bit OS in AArch32 execution
- state
-
-To support loading a 32-bit OS, the execution state will change from
-AArch64 to AArch32 when jumping to kernel.
-
-The architecture information will be got through checking FIT
-image, then U-Boot will load 32-bit OS or 64-bit OS automatically.
-
-Signed-off-by: Ebony Zhu <ebony.zhu at nxp.com>
-Signed-off-by: Alison Wang <alison.wang at nxp.com>
-Signed-off-by: Chenhui Zhao <chenhui.zhao at nxp.com>
----
- arch/arm/cpu/armv8/transition.S | 100 +++++++++++++++++++++++++++++++++++++++
- arch/arm/include/asm/system.h | 2 +
- arch/arm/lib/bootm.c | 20 +++++++-
- common/image-fit.c | 12 ++++-
- 4 files changed, 131 insertions(+), 3 deletions(-)
-
-diff --git a/arch/arm/cpu/armv8/transition.S b/arch/arm/cpu/armv8/transition.S
-index 253a39b..9d7a17a 100644
---- a/arch/arm/cpu/armv8/transition.S
-+++ b/arch/arm/cpu/armv8/transition.S
-@@ -21,3 +21,103 @@ ENTRY(armv8_switch_to_el1)
- 0: ret
- 1: armv8_switch_to_el1_m x0, x1
- ENDPROC(armv8_switch_to_el1)
-+
-+/*
-+ * x0: kernel entry point
-+ * x1: machine nr
-+ * x2: fdt address
-+ */
-+ENTRY(armv8_switch_to_el2_aarch32)
-+ switch_el x3, 1f, 0f, 0f
-+0: ret
-+1:
-+ mov x7, x0
-+ mov x8, x1
-+ mov x9, x2
-+
-+ /* 32bit EL2 | HCE | SMD | RES1 (Bits[5:4]) | Non-secure EL0/EL1 */
-+ mov x1, 0x1b1
-+ msr scr_el3, x1
-+ msr cptr_el3, xzr /* Disable coprocessor traps to EL3 */
-+ mov x1, 0x33ff
-+ msr cptr_el2, x1 /* Disable coprocessor traps to EL2 */
-+
-+ /* Initialize Generic Timers */
-+ msr cntvoff_el2, xzr
-+
-+ mov x1, #0x0830
-+ movk x1, #0x30c5, lsl #16
-+ msr sctlr_el2, x1
-+
-+ /* Return to AArch32 Hypervisor mode */
-+ mov x1, sp
-+ msr sp_el2, x1
-+ mrs x1, vbar_el3
-+ msr vbar_el2, x1 /* Migrate VBAR */
-+ mov x1, #0x1da
-+ msr spsr_el3, x1
-+ msr elr_el3, x7
-+
-+ mov x0, #0
-+ mov x1, x8
-+ mov x2, x9
-+
-+ eret
-+ENDPROC(armv8_switch_to_el2_aarch32)
-+
-+/*
-+ * x0: kernel entry point
-+ * x1: machine nr
-+ * x2: fdt address
-+ */
-+ENTRY(armv8_switch_to_el1_aarch32)
-+ switch_el x3, 0f, 1f, 0f
-+0: ret
-+1:
-+ mov x7, x0
-+ mov x8, x1
-+ mov x9, x2
-+
-+ /* Initialize Generic Timers */
-+ mrs x0, cnthctl_el2
-+ orr x0, x0, #0x3 /* Enable EL1 access to timers */
-+ msr cnthctl_el2, x0
-+ msr cntvoff_el2, xzr
-+
-+ /* Initialize MPID/MPIDR registers */
-+ mrs x0, midr_el1
-+ mrs x1, mpidr_el1
-+ msr vpidr_el2, x0
-+ msr vmpidr_el2, x1
-+
-+ /* Disable coprocessor traps */
-+ mov x0, #0x33ff
-+ msr cptr_el2, x0 /* Disable coprocessor traps to EL2 */
-+ msr hstr_el2, xzr /* Disable coprocessor traps to EL2 */
-+ mov x0, #3 << 20
-+ msr cpacr_el1, x0 /* Enable FP/SIMD at EL1 */
-+
-+ /* Initialize HCR_EL2 */
-+ mov x0, #(0 << 31) /* 32bit EL1 */
-+ orr x0, x0, #(1 << 29) /* Disable HVC */
-+ msr hcr_el2, x0
-+
-+ mov x0, #0x0800
-+ movk x0, #0x30d0, lsl #16
-+ msr sctlr_el1, x0
-+
-+ /* Return to AArch32 Supervisor mode */
-+ mov x0, sp
-+ msr sp_el1, x0 /* Migrate SP */
-+ mrs x0, vbar_el2
-+ msr vbar_el1, x0 /* Migrate VBAR */
-+ mov x0, #0x1d3
-+ msr spsr_el2, x0
-+ msr elr_el2, x7
-+
-+ mov x0, #0
-+ mov x1, x8
-+ mov x2, x9
-+
-+ eret
-+ENDPROC(armv8_switch_to_el1_aarch32)
-diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h
-index 71b3108..0ecbcf7 100644
---- a/arch/arm/include/asm/system.h
-+++ b/arch/arm/include/asm/system.h
-@@ -81,6 +81,8 @@ int __asm_flush_l3_cache(void);
-
- void armv8_switch_to_el2(void);
- void armv8_switch_to_el1(void);
-+void armv8_switch_to_el2_aarch32(u64 entry_point, u64 mach_nr, u64 fdt_addr);
-+void armv8_switch_to_el1_aarch32(u64 entry_point, u64 mach_nr, u64 fdt_addr);
- void gic_init(void);
- void gic_send_sgi(unsigned long sgino);
- void wait_for_wakeup(void);
-diff --git a/arch/arm/lib/bootm.c b/arch/arm/lib/bootm.c
-index a477cae..36f2cb0 100644
---- a/arch/arm/lib/bootm.c
-+++ b/arch/arm/lib/bootm.c
-@@ -276,8 +276,24 @@ static void boot_jump_linux(bootm_headers_t *images, int flag)
- announce_and_cleanup(fake);
-
- if (!fake) {
-- do_nonsec_virt_switch();
-- kernel_entry(images->ft_addr, NULL, NULL, NULL);
-+ if ((IH_ARCH_DEFAULT == IH_ARCH_ARM64) &&
-+ (images->os.arch == IH_ARCH_ARM)) {
-+ smp_kick_all_cpus();
-+ dcache_disable();
-+#ifdef CONFIG_ARMV8_SWITCH_TO_EL1
-+ armv8_switch_to_el2();
-+ armv8_switch_to_el1_aarch32((u64)images->ep,
-+ (u64)gd->bd->bi_arch_number,
-+ (u64)images->ft_addr);
-+#else
-+ armv8_switch_to_el2_aarch32((u64)images->ep,
-+ (u64)gd->bd->bi_arch_number,
-+ (u64)images->ft_addr);
-+#endif
-+ } else {
-+ do_nonsec_virt_switch();
-+ kernel_entry(images->ft_addr, NULL, NULL, NULL);
-+ }
- }
- #else
- unsigned long machid = gd->bd->bi_arch_number;
-diff --git a/common/image-fit.c b/common/image-fit.c
-index c531ee7..0d54f71 100644
---- a/common/image-fit.c
-+++ b/common/image-fit.c
-@@ -1144,7 +1144,8 @@ int fit_image_check_arch(const void *fit, int noffset, uint8_t arch)
- if (fit_image_get_arch(fit, noffset, &image_arch))
- return 0;
- return (arch == image_arch) ||
-- (arch == IH_ARCH_I386 && image_arch == IH_ARCH_X86_64);
-+ (arch == IH_ARCH_I386 && image_arch == IH_ARCH_X86_64) ||
-+ (arch == IH_ARCH_ARM64 && image_arch == IH_ARCH_ARM);
- }
-
- /**
-@@ -1567,6 +1568,9 @@ int fit_image_load(bootm_headers_t *images, ulong addr,
- int type_ok, os_ok;
- ulong load, data, len;
- uint8_t os;
-+#ifndef USE_HOSTCC
-+ uint8_t os_arch;
-+#endif
- const char *prop_name;
- int ret;
-
-@@ -1650,6 +1654,12 @@ int fit_image_load(bootm_headers_t *images, ulong addr,
- return -ENOEXEC;
- }
- #endif
-+
-+#ifndef USE_HOSTCC
-+ fit_image_get_arch(fit, noffset, &os_arch);
-+ images->os.arch = os_arch;
-+#endif
-+
- if (image_type == IH_TYPE_FLATDT &&
- !fit_image_check_comp(fit, noffset, IH_COMP_NONE)) {
- puts("FDT image is compressed");
---
-1.7.9.5
-
diff --git a/package/boot/uboot-layerscape/patches/0002-armv8-SMP-support-for-loading-32-bit-OS.patch b/package/boot/uboot-layerscape/patches/0002-armv8-SMP-support-for-loading-32-bit-OS.patch
deleted file mode 100644
index b24bc18..0000000
--- a/package/boot/uboot-layerscape/patches/0002-armv8-SMP-support-for-loading-32-bit-OS.patch
+++ /dev/null
@@ -1,141 +0,0 @@
-From 014f9196e18f4157232d0521f3a7502e7dbbb974 Mon Sep 17 00:00:00 2001
-From: Alison Wang <b18965 at freescale.com>
-Date: Fri, 13 May 2016 13:28:07 +0800
-Subject: [PATCH 02/93] armv8: SMP support for loading 32-bit OS
-
-Spin-table method is used for secondary cores to load 32-bit OS. The
-architecture information will be got through checking FIT image and
-saved in the os_arch element of spin-table, then the secondary cores
-will check os_arch and jump to 32-bit OS or 64-bit OS automatically.
-
-Signed-off-by: Alison Wang <alison.wang at nxp.com>
-Signed-off-by: Chenhui Zhao <chenhui.zhao at nxp.com>
----
- arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S | 21 +++++++++++++++++++++
- arch/arm/cpu/armv8/fsl-layerscape/mp.c | 10 ++++++++++
- arch/arm/include/asm/arch-fsl-layerscape/mp.h | 6 ++++++
- arch/arm/lib/bootm.c | 5 +++++
- 4 files changed, 42 insertions(+)
-
-diff --git a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S
-index 9c69ed1..93f4a65 100644
---- a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S
-+++ b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S
-@@ -13,6 +13,7 @@
- #ifdef CONFIG_MP
- #include <asm/arch/mp.h>
- #endif
-+#include <asm/u-boot.h>
-
- ENTRY(lowlevel_init)
- mov x29, lr /* Save LR */
-@@ -320,6 +321,11 @@ ENTRY(secondary_boot_func)
- gic_wait_for_interrupt_m x0, w1
- #endif
-
-+ ldr x5, [x11, #24]
-+ ldr x6, =IH_ARCH_DEFAULT
-+ cmp x6, x5
-+ b.ne slave_cpu
-+
- bl secondary_switch_to_el2
- #ifdef CONFIG_ARMV8_SWITCH_TO_EL1
- bl secondary_switch_to_el1
-@@ -337,6 +343,21 @@ slave_cpu:
- tbz x1, #25, cpu_is_le
- rev x0, x0 /* BE to LE conversion */
- cpu_is_le:
-+
-+ ldr x5, [x11, #24]
-+ ldr x6, =IH_ARCH_DEFAULT
-+ cmp x6, x5
-+ b.eq 1f
-+
-+#ifdef CONFIG_ARMV8_SWITCH_TO_EL1
-+ bl secondary_switch_to_el2
-+ ldr x0, [x11]
-+ bl armv8_switch_to_el1_aarch32
-+#else
-+ bl armv8_switch_to_el2_aarch32
-+#endif
-+
-+1:
- br x0 /* branch to the given address */
- ENDPROC(secondary_boot_func)
-
-diff --git a/arch/arm/cpu/armv8/fsl-layerscape/mp.c b/arch/arm/cpu/armv8/fsl-layerscape/mp.c
-index df7ffb8..dd91550 100644
---- a/arch/arm/cpu/armv8/fsl-layerscape/mp.c
-+++ b/arch/arm/cpu/armv8/fsl-layerscape/mp.c
-@@ -22,6 +22,16 @@ phys_addr_t determine_mp_bootpg(void)
- return (phys_addr_t)&secondary_boot_code;
- }
-
-+void update_os_arch_secondary_cores(uint8_t os_arch)
-+{
-+ u64 *table = get_spin_tbl_addr();
-+ int i;
-+
-+ for (i = 1; i < CONFIG_MAX_CPUS; i++)
-+ table[i * WORDS_PER_SPIN_TABLE_ENTRY +
-+ SPIN_TABLE_ELEM_OS_ARCH_IDX] = os_arch;
-+}
-+
- int fsl_layerscape_wake_seconday_cores(void)
- {
- struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
-diff --git a/arch/arm/include/asm/arch-fsl-layerscape/mp.h b/arch/arm/include/asm/arch-fsl-layerscape/mp.h
-index e46e076..55f0e0c 100644
---- a/arch/arm/include/asm/arch-fsl-layerscape/mp.h
-+++ b/arch/arm/include/asm/arch-fsl-layerscape/mp.h
-@@ -13,6 +13,7 @@
- * uint64_t entry_addr;
- * uint64_t status;
- * uint64_t lpid;
-+* uint64_t os_arch;
- * };
- * we pad this struct to 64 bytes so each entry is in its own cacheline
- * the actual spin table is an array of these structures
-@@ -20,6 +21,7 @@
- #define SPIN_TABLE_ELEM_ENTRY_ADDR_IDX 0
- #define SPIN_TABLE_ELEM_STATUS_IDX 1
- #define SPIN_TABLE_ELEM_LPID_IDX 2
-+#define SPIN_TABLE_ELEM_OS_ARCH_IDX 3
- #define WORDS_PER_SPIN_TABLE_ENTRY 8 /* pad to 64 bytes */
- #define SPIN_TABLE_ELEM_SIZE 64
-
-@@ -35,4 +37,8 @@ phys_addr_t determine_mp_bootpg(void);
- void secondary_boot_func(void);
- int is_core_online(u64 cpu_id);
- #endif
-+
-+#define IH_ARCH_ARM 2 /* ARM */
-+#define IH_ARCH_ARM64 22 /* ARM64 */
-+
- #endif /* _FSL_LAYERSCAPE_MP_H */
-diff --git a/arch/arm/lib/bootm.c b/arch/arm/lib/bootm.c
-index 36f2cb0..aae8c5b 100644
---- a/arch/arm/lib/bootm.c
-+++ b/arch/arm/lib/bootm.c
-@@ -258,6 +258,10 @@ bool armv7_boot_nonsec(void)
- }
- #endif
-
-+__weak void update_os_arch_secondary_cores(uint8_t os_arch)
-+{
-+}
-+
- /* Subcommand: GO */
- static void boot_jump_linux(bootm_headers_t *images, int flag)
- {
-@@ -276,6 +280,7 @@ static void boot_jump_linux(bootm_headers_t *images, int flag)
- announce_and_cleanup(fake);
-
- if (!fake) {
-+ update_os_arch_secondary_cores(images->os.arch);
- if ((IH_ARCH_DEFAULT == IH_ARCH_ARM64) &&
- (images->os.arch == IH_ARCH_ARM)) {
- smp_kick_all_cpus();
---
-1.7.9.5
-
diff --git a/package/boot/uboot-layerscape/patches/0003-armv8-aarch32-Disable-CONFIG_FSL_LS_PPA-for-loading-.patch b/package/boot/uboot-layerscape/patches/0003-armv8-aarch32-Disable-CONFIG_FSL_LS_PPA-for-loading-.patch
deleted file mode 100644
index b309ffe..0000000
--- a/package/boot/uboot-layerscape/patches/0003-armv8-aarch32-Disable-CONFIG_FSL_LS_PPA-for-loading-.patch
+++ /dev/null
@@ -1,30 +0,0 @@
-From f9e93719a99120e93628bf39bd997164a01afda2 Mon Sep 17 00:00:00 2001
-From: Alison Wang <b18965 at freescale.com>
-Date: Fri, 13 May 2016 15:23:27 +0800
-Subject: [PATCH 03/93] armv8: aarch32: Disable CONFIG_FSL_LS_PPA for loading
- 32-bit OS
-
-The current U-Boot doesn't support loading 32-bit OS with PPA, so
-disable CONFIG_FSL_LS_PPA so far.
-
-Signed-off-by: Alison Wang <alison.wang at nxp.com>
----
- include/configs/ls1043ardb.h | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
-diff --git a/include/configs/ls1043ardb.h b/include/configs/ls1043ardb.h
-index c1abc73..af8b441 100644
---- a/include/configs/ls1043ardb.h
-+++ b/include/configs/ls1043ardb.h
-@@ -9,7 +9,7 @@
-
- #include "ls1043a_common.h"
-
--#define CONFIG_FSL_LS_PPA
-+#undef CONFIG_FSL_LS_PPA
- #if defined(CONFIG_FSL_LS_PPA)
- #define CONFIG_ARMV8_PSCI
- #define CONFIG_SYS_LS_PPA_DRAM_BLOCK_MIN_SIZE (1UL * 1024 * 1024)
---
-1.7.9.5
-
diff --git a/package/boot/uboot-layerscape/patches/0004-armv8-Support-loading-32-bit-OS-which-is-not-in-the-.patch b/package/boot/uboot-layerscape/patches/0004-armv8-Support-loading-32-bit-OS-which-is-not-in-the-.patch
deleted file mode 100644
index 8f5dc28..0000000
--- a/package/boot/uboot-layerscape/patches/0004-armv8-Support-loading-32-bit-OS-which-is-not-in-the-.patch
+++ /dev/null
@@ -1,31 +0,0 @@
-From cb5a037831053d22ce260dbec6b378f532bd2c6c Mon Sep 17 00:00:00 2001
-From: Alison Wang <b18965 at freescale.com>
-Date: Tue, 21 Jun 2016 17:14:35 +0800
-Subject: [PATCH 04/93] armv8: Support loading 32-bit OS which is not in the
- form of FIT
-
-As only FIT image is supported now, this patch is to support loading
-32-bit uImage, dtb and rootfs separately.
-
-Signed-off-by: Alison Wang <alison.wang at nxp.com>
----
- include/image.h | 3 ++-
- 1 file changed, 2 insertions(+), 1 deletion(-)
-
-diff --git a/include/image.h b/include/image.h
-index 299d6d2..0ea5f8e 100644
---- a/include/image.h
-+++ b/include/image.h
-@@ -694,7 +694,8 @@ static inline int image_check_type(const image_header_t *hdr, uint8_t type)
- }
- static inline int image_check_arch(const image_header_t *hdr, uint8_t arch)
- {
-- return (image_get_arch(hdr) == arch);
-+ return (image_get_arch(hdr) == arch) ||
-+ (image_get_arch(hdr) == IH_ARCH_ARM && arch == IH_ARCH_ARM64);
- }
- static inline int image_check_os(const image_header_t *hdr, uint8_t os)
- {
---
-1.7.9.5
-
diff --git a/package/boot/uboot-layerscape/patches/0005-armv8-set-openwrt-lede-default-boot-env-for-ls1043ar.patch b/package/boot/uboot-layerscape/patches/0005-armv8-set-openwrt-lede-default-boot-env-for-ls1043ar.patch
deleted file mode 100644
index 2754859..0000000
--- a/package/boot/uboot-layerscape/patches/0005-armv8-set-openwrt-lede-default-boot-env-for-ls1043ar.patch
+++ /dev/null
@@ -1,68 +0,0 @@
-From 3c22f3fcbdb9f919ebdfa87a2ec237ac2abb7e03 Mon Sep 17 00:00:00 2001
-From: Yutang Jiang <yutang.jiang at nxp.com>
-Date: Thu, 27 Oct 2016 23:45:45 +0800
-Subject: [PATCH 05/93] armv8: set openwrt/lede default boot env for
- ls1043ardb
-
-Signed-off-by: Yutang Jiang <yutang.jiang at nxp.com>
----
- include/configs/ls1043a_common.h | 28 +++++++++++++++++++++++++---
- 1 file changed, 25 insertions(+), 3 deletions(-)
-
-diff --git a/include/configs/ls1043a_common.h b/include/configs/ls1043a_common.h
-index 68678f3..1db05bb 100644
---- a/include/configs/ls1043a_common.h
-+++ b/include/configs/ls1043a_common.h
-@@ -273,6 +273,16 @@
- "5m(kernel),1m(dtb),9m(file_system)"
- #endif
-
-+#define WRTBOOT_DEFAULT "setenv bootargs root=/dev/mtdblock6 " \
-+ "rootfstype=squashfs,jffs2 noinitrd earlycon=uart8250,mmio,0x21c0500 " \
-+ "console=ttyS0,115200 mtdparts=60000000.nor:1M(rcw),1M(u-boot)," \
-+ "1M(u-boot-env),1M(fman),1M(dtb),5M(kernel),54M(rootfs),64M(otherbank)" \
-+ " && cp.b 60400000 $fdtaddr 100000 && cp.b 60500000 $loadaddr 500000" \
-+ " && bootm $loadaddr - $fdtaddr"
-+#define WRTUPDATE_DEFAULT "tftp a0000000 <tftp_folder>/" \
-+ "lede-layerscape-64b-ls1043ardb-squashfs-firmware.bin && protect off all" \
-+ " && erase 60000000 +4000000 && cp.b a0000000 60000000 $filesize && reset"
-+
- /* Initial environment variables */
- #define CONFIG_EXTRA_ENV_SETTINGS \
- "hwconfig=fsl_ddr:bank_intlv=auto\0" \
-@@ -286,6 +296,19 @@
- "kernel_load=0xa0000000\0" \
- "kernel_size=0x2800000\0" \
- "console=ttyAMA0,38400n8\0" \
-+ "ethaddr=00:e0:0c:00:77:00\0" \
-+ "eth1addr=00:e0:0c:00:77:01\0" \
-+ "eth2addr=00:e0:0c:00:77:02\0" \
-+ "eth3addr=00:e0:0c:00:77:03\0" \
-+ "eth4addr=00:e0:0c:00:77:04\0" \
-+ "eth5addr=00:e0:0c:00:77:05\0" \
-+ "eth6addr=00:e0:0c:00:77:06\0" \
-+ "ethact=FM1 at DTSEC2\0" \
-+ "loadaddr=82000000\0" \
-+ "ramdiskaddr=88000000\0" \
-+ "fdtaddr=8f000000\0" \
-+ "wrtboot=" WRTBOOT_DEFAULT "\0" \
-+ "wrtupdate=" WRTUPDATE_DEFAULT "\0" \
- "mtdparts=" MTDPARTS_DEFAULT "\0"
-
- #define CONFIG_BOOTARGS "console=ttyS0,115200 root=/dev/ram0 " \
-@@ -296,10 +319,9 @@
- #define CONFIG_BOOTCOMMAND "sf probe && sf read $kernel_load " \
- "e0000 f00000 && bootm $kernel_load"
- #else
--#define CONFIG_BOOTCOMMAND "cp.b $kernel_start $kernel_load " \
-- "$kernel_size && bootm $kernel_load"
-+#define CONFIG_BOOTCOMMAND "run wrtboot"
- #endif
--#define CONFIG_BOOTDELAY 10
-+#define CONFIG_BOOTDELAY 3
-
- /* Monitor Command Prompt */
- #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
---
-1.7.9.5
-
diff --git a/package/boot/uboot-layerscape/patches/0006-armv8-fsl-layerscape-Put-SMMU-config-code-in-SMMU_BA.patch b/package/boot/uboot-layerscape/patches/0006-armv8-fsl-layerscape-Put-SMMU-config-code-in-SMMU_BA.patch
deleted file mode 100644
index a8a9aa3..0000000
--- a/package/boot/uboot-layerscape/patches/0006-armv8-fsl-layerscape-Put-SMMU-config-code-in-SMMU_BA.patch
+++ /dev/null
@@ -1,37 +0,0 @@
-From be06181f45695ce71536ecb461615ebf6f18011e Mon Sep 17 00:00:00 2001
-From: Prabhakar Kushwaha <prabhakar.kushwaha at nxp.com>
-Date: Tue, 15 Mar 2016 13:40:07 +0530
-Subject: [PATCH 06/93] armv8: fsl-layerscape: Put SMMU config code in
- SMMU_BASE
-
-It is not mandatory for Layerscape SoCs to have SMMU. SoCs like
-LS1012A are layerscape SoC without SMMU IP.
-
-So put SMMU configuration code under SMMU_BASE.
-
-Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha at nxp.com>
----
- arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S | 2 ++
- 1 file changed, 2 insertions(+)
-
-diff --git a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S
-index 93f4a65..5f5bfb9 100644
---- a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S
-+++ b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S
-@@ -95,11 +95,13 @@ ENTRY(lowlevel_init)
- bl ccn504_set_qos
- #endif
-
-+#ifdef SMMU_BASE
- /* Set the SMMU page size in the sACR register */
- ldr x1, =SMMU_BASE
- ldr w0, [x1, #0x10]
- orr w0, w0, #1 << 16 /* set sACR.pagesize to indicate 64K page */
- str w0, [x1, #0x10]
-+#endif
-
- /* Initialize GIC Secure Bank Status */
- #if defined(CONFIG_GICV2) || defined(CONFIG_GICV3)
---
-1.7.9.5
-
diff --git a/package/boot/uboot-layerscape/patches/0007-armv8-fsl-layerscape-Avoid-LS1043A-specifc-defines.patch b/package/boot/uboot-layerscape/patches/0007-armv8-fsl-layerscape-Avoid-LS1043A-specifc-defines.patch
deleted file mode 100644
index 6cb1847..0000000
--- a/package/boot/uboot-layerscape/patches/0007-armv8-fsl-layerscape-Avoid-LS1043A-specifc-defines.patch
+++ /dev/null
@@ -1,44 +0,0 @@
-From 825d623c913c63b1f00c42f27ef0916b11d9f09f Mon Sep 17 00:00:00 2001
-From: Prabhakar Kushwaha <prabhakar.kushwaha at nxp.com>
-Date: Tue, 15 Mar 2016 13:40:22 +0530
-Subject: [PATCH 07/93] armv8: fsl-layerscape: Avoid LS1043A specifc defines
-
-Other than LS1043A, LS1012A also Chassis Gen2 Architecture compliant.
-
-So Avoid LS1043A specific defines in arch/arm
-
-Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha at nxp.com>
----
- arch/arm/cpu/armv8/fsl-layerscape/soc.c | 2 +-
- .../include/asm/arch-fsl-layerscape/fsl_serdes.h | 2 +-
- 2 files changed, 2 insertions(+), 2 deletions(-)
-
-diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
-index 92dcb72..23f0c88 100644
---- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
-+++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
-@@ -314,7 +314,7 @@ int sata_init(void)
- }
- #endif
-
--#elif defined(CONFIG_LS1043A)
-+#elif defined(CONFIG_FSL_LSCH2)
- #ifdef CONFIG_SCSI_AHCI_PLAT
- int sata_init(void)
- {
-diff --git a/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h b/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h
-index d1fbde7..7096dac 100644
---- a/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h
-+++ b/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h
-@@ -55,7 +55,7 @@ enum srds {
- FSL_SRDS_1 = 0,
- FSL_SRDS_2 = 1,
- };
--#elif defined(CONFIG_LS1043A)
-+#elif defined(CONFIG_FSL_LSCH2)
- enum srds_prtcl {
- NONE = 0,
- PCIE1,
---
-1.7.9.5
-
diff --git a/package/boot/uboot-layerscape/patches/0008-armv8-ls1043a-Add-the-OCRAM-initialization.patch b/package/boot/uboot-layerscape/patches/0008-armv8-ls1043a-Add-the-OCRAM-initialization.patch
deleted file mode 100644
index 5715a22..0000000
--- a/package/boot/uboot-layerscape/patches/0008-armv8-ls1043a-Add-the-OCRAM-initialization.patch
+++ /dev/null
@@ -1,82 +0,0 @@
-From b3bbf1aeb0245a0f5565f669dd4b2f5f5be40d8a Mon Sep 17 00:00:00 2001
-From: Prabhakar Kushwaha <prabhakar.kushwaha at nxp.com>
-Date: Wed, 16 Mar 2016 08:43:55 +0530
-Subject: [PATCH 08/93] armv8/ls1043a: Add the OCRAM initialization
-
-Clear the content to zero and the ECC error bit of OCRAM1/2.
-
-The OCRAM must be initialized to ZERO by the unit of 8-Byte before
-accessing it, or else it will generate ECC error. And the IBR has
-accessed the OCRAM before this initialization, so the ECC error
-status bit should to be cleared.
-
-Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou at freescale.com>
-Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha at nxp.com>
----
- arch/arm/cpu/armv8/start.S | 39 +++++++++++++++++++++++++++++++++++++++
- 1 file changed, 39 insertions(+)
-
-diff --git a/arch/arm/cpu/armv8/start.S b/arch/arm/cpu/armv8/start.S
-index dd583c9..235213f 100644
---- a/arch/arm/cpu/armv8/start.S
-+++ b/arch/arm/cpu/armv8/start.S
-@@ -11,6 +11,9 @@
- #include <asm/macro.h>
- #include <asm/armv8/mmu.h>
-
-+#define DCSR_SYS_DCFG_SBEESR2 0x20140534
-+#define DCSR_SYS_DCFG_MBEESR2 0x20140544
-+
- /*************************************************************************
- *
- * Startup Code (reset vector)
-@@ -215,10 +218,46 @@ WEAK(lowlevel_init)
- #endif /* CONFIG_ARMV8_MULTIENTRY */
-
- 2:
-+#if defined(CONFIG_FSL_LSCH2) && !defined(CONFIG_SPL_BUILD)
-+ bl fsl_ocram_init
-+#endif
- mov lr, x29 /* Restore LR */
- ret
- ENDPROC(lowlevel_init)
-
-+#if defined(CONFIG_FSL_LSCH2) && !defined(CONFIG_SPL_BUILD)
-+ENTRY(fsl_ocram_init)
-+ mov x28, lr /* Save LR */
-+ bl fsl_clear_ocram
-+ bl fsl_ocram_clear_ecc_err
-+ mov lr, x28 /* Restore LR */
-+ ret
-+ENDPROC(fsl_ocram_init)
-+
-+ENTRY(fsl_clear_ocram)
-+/* Clear OCRAM */
-+ ldr x0, =CONFIG_SYS_FSL_OCRAM_BASE
-+ ldr x1, =(CONFIG_SYS_FSL_OCRAM_BASE + CONFIG_SYS_FSL_OCRAM_SIZE)
-+ mov x2, #0
-+clear_loop:
-+ str x2, [x0]
-+ add x0, x0, #8
-+ cmp x0, x1
-+ b.lo clear_loop
-+ ret
-+ENDPROC(fsl_clear_ocram)
-+
-+ENTRY(fsl_ocram_clear_ecc_err)
-+ /* OCRAM1/2 ECC status bit */
-+ mov w1, #0x60
-+ ldr x0, =DCSR_SYS_DCFG_SBEESR2
-+ str w1, [x0]
-+ ldr x0, =DCSR_SYS_DCFG_MBEESR2
-+ str w1, [x0]
-+ ret
-+ENDPROC(fsl_ocram_init)
-+#endif
-+
- WEAK(smp_kick_all_cpus)
- /* Kick secondary cpus up by SGI 0 interrupt */
- mov x29, lr /* Save LR */
---
-1.7.9.5
-
diff --git a/package/boot/uboot-layerscape/patches/0009-driver-mtd-spi-Adding-support-for-QSPI-Emulator.patch b/package/boot/uboot-layerscape/patches/0009-driver-mtd-spi-Adding-support-for-QSPI-Emulator.patch
deleted file mode 100644
index f0b65a1..0000000
--- a/package/boot/uboot-layerscape/patches/0009-driver-mtd-spi-Adding-support-for-QSPI-Emulator.patch
+++ /dev/null
@@ -1,29 +0,0 @@
-From f022d8d9dc505ee917fef6c7109d67cc015a98fa Mon Sep 17 00:00:00 2001
-From: Prabhakar Kushwaha <prabhakar.kushwaha at nxp.com>
-Date: Mon, 25 Apr 2016 16:05:36 +0530
-Subject: [PATCH 09/93] driver: mtd: spi: Adding support for QSPI Emulator
-
-Serial number and vendor id are added for The QSPI Emulator
-
-Signed-off-by: Pratiyush Mohan Srivastava <pratiyush.srivastava at nxp.com>
-Signed-off-by: Calvin Johnson <calvin.johnson at nxp.com>
-Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha at nxp.com>
----
- drivers/mtd/spi/sf_params.c | 1 +
- 1 file changed, 1 insertion(+)
-
-diff --git a/drivers/mtd/spi/sf_params.c b/drivers/mtd/spi/sf_params.c
-index 4f37e33..1424f2a 100644
---- a/drivers/mtd/spi/sf_params.c
-+++ b/drivers/mtd/spi/sf_params.c
-@@ -67,6 +67,7 @@ const struct spi_flash_params spi_flash_params_table[] = {
- {"S25FL128S_64K", 0x012018, 0x4d01, 64 * 1024, 256, RD_FULL, WR_QPP},
- {"S25FL256S_256K", 0x010219, 0x4d00, 256 * 1024, 128, RD_FULL, WR_QPP},
- {"S25FL256S_64K", 0x010219, 0x4d01, 64 * 1024, 512, RD_FULL, WR_QPP},
-+ {"S25FS512S", 0x010220, 0x0102, 256 * 1024, 256, RD_FULL, WR_QPP},
- {"S25FL512S_256K", 0x010220, 0x4d00, 256 * 1024, 256, RD_FULL, WR_QPP},
- {"S25FL512S_64K", 0x010220, 0x4d01, 64 * 1024, 1024, RD_FULL, WR_QPP},
- {"S25FL512S_512K", 0x010220, 0x4f00, 256 * 1024, 256, RD_FULL, WR_QPP},
---
-1.7.9.5
-
diff --git a/package/boot/uboot-layerscape/patches/0010-driver-mtd-spi-Adding-support-for-QSPI-flash.patch b/package/boot/uboot-layerscape/patches/0010-driver-mtd-spi-Adding-support-for-QSPI-flash.patch
deleted file mode 100644
index 01ace8f..0000000
--- a/package/boot/uboot-layerscape/patches/0010-driver-mtd-spi-Adding-support-for-QSPI-flash.patch
+++ /dev/null
@@ -1,45 +0,0 @@
-From 27d1d5620ae352d230189fbea364198398065ae2 Mon Sep 17 00:00:00 2001
-From: Prabhakar Kushwaha <prabhakar.kushwaha at nxp.com>
-Date: Mon, 25 Apr 2016 16:06:48 +0530
-Subject: [PATCH 10/93] driver: mtd: spi: Adding support for QSPI flash
-
-Serial number and vendor id are added for QSPI flash
-common on both LS1012AQDS and LS1012ARDB.
-
-Signed-off-by: Pratiyush Mohan Srivastava <pratiyush.srivastava at nxp.com>
-Signed-off-by: Calvin Johnson <calvin.johnson at nxp.com>
-Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha at nxp.com>
----
- drivers/mtd/spi/sf_params.c | 1 +
- drivers/mtd/spi/spi_flash.c | 3 ++-
- 2 files changed, 3 insertions(+), 1 deletion(-)
-
-diff --git a/drivers/mtd/spi/sf_params.c b/drivers/mtd/spi/sf_params.c
-index 1424f2a..1afb8b3 100644
---- a/drivers/mtd/spi/sf_params.c
-+++ b/drivers/mtd/spi/sf_params.c
-@@ -68,6 +68,7 @@ const struct spi_flash_params spi_flash_params_table[] = {
- {"S25FL256S_256K", 0x010219, 0x4d00, 256 * 1024, 128, RD_FULL, WR_QPP},
- {"S25FL256S_64K", 0x010219, 0x4d01, 64 * 1024, 512, RD_FULL, WR_QPP},
- {"S25FS512S", 0x010220, 0x0102, 256 * 1024, 256, RD_FULL, WR_QPP},
-+ {"S25FS512S_256K", 0x010220, 0x4D00, 128 * 1024, 512, RD_FULL, WR_QPP},
- {"S25FL512S_256K", 0x010220, 0x4d00, 256 * 1024, 256, RD_FULL, WR_QPP},
- {"S25FL512S_64K", 0x010220, 0x4d01, 64 * 1024, 1024, RD_FULL, WR_QPP},
- {"S25FL512S_512K", 0x010220, 0x4f00, 256 * 1024, 256, RD_FULL, WR_QPP},
-diff --git a/drivers/mtd/spi/spi_flash.c b/drivers/mtd/spi/spi_flash.c
-index 2d23aee..865e929 100644
---- a/drivers/mtd/spi/spi_flash.c
-+++ b/drivers/mtd/spi/spi_flash.c
-@@ -1033,7 +1033,8 @@ int spi_flash_scan(struct spi_flash *flash)
- * sector that is not overlaid by the parameter sectors.
- * The uniform sector erase command has no effect on parameter sectors.
- */
-- if (jedec == 0x0219 && (ext_jedec & 0xff00) == 0x4d00) {
-+ if ((jedec == 0x0219 || (jedec == 0x0220)) &&
-+ (ext_jedec & 0xff00) == 0x4d00) {
- int ret;
- u8 id[6];
-
---
-1.7.9.5
-
diff --git a/package/boot/uboot-layerscape/patches/0011-armv8-fsl-layerscape-fix-compile-warning-rcw_tmp.patch b/package/boot/uboot-layerscape/patches/0011-armv8-fsl-layerscape-fix-compile-warning-rcw_tmp.patch
deleted file mode 100644
index 6448acb..0000000
--- a/package/boot/uboot-layerscape/patches/0011-armv8-fsl-layerscape-fix-compile-warning-rcw_tmp.patch
+++ /dev/null
@@ -1,38 +0,0 @@
-From 5a5108627b16ab33fb82c16e49ac926ef3a901b8 Mon Sep 17 00:00:00 2001
-From: Prabhakar Kushwaha <prabhakar.kushwaha at nxp.com>
-Date: Wed, 6 Apr 2016 17:44:22 +0530
-Subject: [PATCH 11/93] armv8: fsl-layerscape: fix compile warning "rcw_tmp"
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c: In function
-‘get_sys_info’:
-arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c:29:6: warning:
-unused variable ‘rcw_tmp’ [-Wunused-variable]
- u32 rcw_tmp;
-
-Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha at nxp.com>
----
- .../arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c | 5 ++++-
- 1 file changed, 4 insertions(+), 1 deletion(-)
-
-diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c
-index d301fff..078b087 100644
---- a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c
-+++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c
-@@ -25,7 +25,10 @@ void get_sys_info(struct sys_info *sys_info)
- struct fsl_ifc ifc_regs = {(void *)CONFIG_SYS_IFC_ADDR, (void *)NULL};
- u32 ccr;
- #endif
--#if defined(CONFIG_FSL_ESDHC) || defined(CONFIG_SYS_DPAA_FMAN)
-+#if (defined(CONFIG_FSL_ESDHC) &&\
-+ defined(CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK)) ||\
-+ defined(CONFIG_SYS_DPAA_FMAN)
-+
- u32 rcw_tmp;
- #endif
- struct ccsr_clk *clk = (void *)(CONFIG_SYS_FSL_CLK_ADDR);
---
-1.7.9.5
-
diff --git a/package/boot/uboot-layerscape/patches/0012-armv8-LSCH2-early-and-final-mmu-needs-matching-NS-at.patch b/package/boot/uboot-layerscape/patches/0012-armv8-LSCH2-early-and-final-mmu-needs-matching-NS-at.patch
deleted file mode 100644
index 33c3a57..0000000
--- a/package/boot/uboot-layerscape/patches/0012-armv8-LSCH2-early-and-final-mmu-needs-matching-NS-at.patch
+++ /dev/null
@@ -1,58 +0,0 @@
-From edc5b23b8dd04980e0fa48fe79ba811b775cd2c2 Mon Sep 17 00:00:00 2001
-From: Prabhakar Kushwaha <prabhakar.kushwaha at nxp.com>
-Date: Sat, 23 Apr 2016 12:34:59 +0530
-Subject: [PATCH 12/93] armv8: LSCH2 early and final mmu needs matching NS
- attribute
-
-When switching between the early and final mmu tables, the stack will
-get corrupted if the Non-Secure attribute is different. For ls1043a,
-this issue is currently masked because flush_dcache_all is called
-before the switch when CONFIG_SYS_DPAA_FMAN is defined.
-
-Signed-off-by: Ed Swarthout <Ed.Swarthout at nxp.com>
-Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha at nxp.com>
----
- arch/arm/include/asm/arch-fsl-layerscape/cpu.h | 12 ++++++++----
- 1 file changed, 8 insertions(+), 4 deletions(-)
-
-diff --git a/arch/arm/include/asm/arch-fsl-layerscape/cpu.h b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h
-index a9dadfa..a7522da 100644
---- a/arch/arm/include/asm/arch-fsl-layerscape/cpu.h
-+++ b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h
-@@ -159,9 +159,11 @@ static const struct sys_mmu_table early_mmu_table[] = {
- { CONFIG_SYS_FSL_IFC_BASE, CONFIG_SYS_FSL_IFC_BASE,
- CONFIG_SYS_FSL_IFC_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
- { CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1,
-- CONFIG_SYS_FSL_DRAM_SIZE1, MT_NORMAL, PMD_SECT_OUTER_SHARE },
-+ CONFIG_SYS_FSL_DRAM_SIZE1, MT_NORMAL,
-+ PMD_SECT_OUTER_SHARE | PMD_SECT_NS },
- { CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2,
-- CONFIG_SYS_FSL_DRAM_SIZE2, MT_NORMAL, PMD_SECT_OUTER_SHARE },
-+ CONFIG_SYS_FSL_DRAM_SIZE2, MT_NORMAL,
-+ PMD_SECT_OUTER_SHARE | PMD_SECT_NS},
- #endif
- };
-
-@@ -249,7 +251,8 @@ static const struct sys_mmu_table final_mmu_table[] = {
- CONFIG_SYS_FSL_QBMAN_SIZE, MT_DEVICE_NGNRNE,
- PMD_SECT_NON_SHARE | PMD_SECT_PXN | PMD_SECT_UXN },
- { CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2,
-- CONFIG_SYS_FSL_DRAM_SIZE2, MT_NORMAL, PMD_SECT_OUTER_SHARE },
-+ CONFIG_SYS_FSL_DRAM_SIZE2, MT_NORMAL,
-+ PMD_SECT_OUTER_SHARE | PMD_SECT_NS},
- { CONFIG_SYS_PCIE1_PHYS_ADDR, CONFIG_SYS_PCIE1_PHYS_ADDR,
- CONFIG_SYS_PCIE1_PHYS_SIZE, MT_DEVICE_NGNRNE,
- PMD_SECT_NON_SHARE | PMD_SECT_PXN | PMD_SECT_UXN },
-@@ -260,7 +263,8 @@ static const struct sys_mmu_table final_mmu_table[] = {
- CONFIG_SYS_PCIE3_PHYS_SIZE, MT_DEVICE_NGNRNE,
- PMD_SECT_NON_SHARE | PMD_SECT_PXN | PMD_SECT_UXN },
- { CONFIG_SYS_FSL_DRAM_BASE3, CONFIG_SYS_FSL_DRAM_BASE3,
-- CONFIG_SYS_FSL_DRAM_SIZE3, MT_NORMAL, PMD_SECT_OUTER_SHARE },
-+ CONFIG_SYS_FSL_DRAM_SIZE3, MT_NORMAL,
-+ PMD_SECT_OUTER_SHARE | PMD_SECT_NS },
- #endif
- };
- #endif
---
-1.7.9.5
-
diff --git a/package/boot/uboot-layerscape/patches/0013-armv8-fsl-layerscape-Add-support-of-QorIQ-LS1012A-So.patch b/package/boot/uboot-layerscape/patches/0013-armv8-fsl-layerscape-Add-support-of-QorIQ-LS1012A-So.patch
deleted file mode 100644
index ea7ab96..0000000
--- a/package/boot/uboot-layerscape/patches/0013-armv8-fsl-layerscape-Add-support-of-QorIQ-LS1012A-So.patch
+++ /dev/null
@@ -1,418 +0,0 @@
-From 53ffd67d944fa23037e7f97e583fae300d4367f7 Mon Sep 17 00:00:00 2001
-From: Prabhakar Kushwaha <prabhakar.kushwaha at nxp.com>
-Date: Sat, 23 Apr 2016 15:23:52 +0530
-Subject: [PATCH 13/93] armv8: fsl-layerscape: Add support of QorIQ LS1012A
- SoC
-
-[context adjustment]
-
-The QorIQ LS1012A processor, optimized for battery-backed or
-USB-powered, integrates a single ARM Cortex-A53 core with a hardware
-packet forwarding engine and high-speed interfaces to deliver
-line-rate networking performance.
-
-This patch add support of LS1012A SoC along with
- - Update platform & DDR clock read logic as per SVR
- - Define MMDC controller register set.
- - Update LUT base address for PCIe
- - Avoid L3 platform cache compilation
- - Update USB address, errata
- - SerDes table
-
-Signed-off-by: Rajat Srivastava <rajat.srivastava at nxp.com>
-Signed-off-by: Rajesh Bhagat <rajesh.bhagat at nxp.com>
-Signed-off-by: Calvin Johnson <calvin.johnson at nxp.com>
-Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha at nxp.com>
-Integrated-by: Jiang Yutang <yutang.jiang at nxp.com>
----
- arch/arm/cpu/armv8/fsl-layerscape/Makefile | 4 ++
- .../arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c | 24 +++++--
- arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S | 2 +
- arch/arm/cpu/armv8/fsl-layerscape/ls1012a_serdes.c | 74 ++++++++++++++++++++
- arch/arm/cpu/armv8/fsl-layerscape/soc.c | 6 +-
- arch/arm/include/asm/arch-fsl-layerscape/config.h | 32 +++++++++
- arch/arm/include/asm/arch-fsl-layerscape/cpu.h | 1 +
- .../include/asm/arch-fsl-layerscape/fsl_serdes.h | 1 +
- .../include/asm/arch-fsl-layerscape/immap_lsch2.h | 4 ++
- arch/arm/include/asm/arch-fsl-layerscape/soc.h | 1 +
- include/fsl_mmdc.h | 53 ++++++++++++++
- include/linux/usb/xhci-fsl.h | 4 ++
- 12 files changed, 199 insertions(+), 7 deletions(-)
- create mode 100644 arch/arm/cpu/armv8/fsl-layerscape/ls1012a_serdes.c
- create mode 100644 include/fsl_mmdc.h
-
-diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Makefile b/arch/arm/cpu/armv8/fsl-layerscape/Makefile
-index 27bfeb1..03f73d1 100644
---- a/arch/arm/cpu/armv8/fsl-layerscape/Makefile
-+++ b/arch/arm/cpu/armv8/fsl-layerscape/Makefile
-@@ -33,3 +33,7 @@ endif
- ifneq ($(CONFIG_LS1043A),)
- obj-$(CONFIG_SYS_HAS_SERDES) += ls1043a_serdes.o
- endif
-+
-+ifneq ($(CONFIG_LS1012A),)
-+obj-$(CONFIG_SYS_HAS_SERDES) += ls1012a_serdes.o
-+endif
-diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c
-index 078b087..63e5bed 100644
---- a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c
-+++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c
-@@ -33,6 +33,7 @@ void get_sys_info(struct sys_info *sys_info)
- #endif
- struct ccsr_clk *clk = (void *)(CONFIG_SYS_FSL_CLK_ADDR);
- unsigned int cpu;
-+ unsigned int svr, ver;
- const u8 core_cplx_pll[8] = {
- [0] = 0, /* CC1 PPL / 1 */
- [1] = 0, /* CC1 PPL / 2 */
-@@ -59,12 +60,20 @@ void get_sys_info(struct sys_info *sys_info)
- sys_info->freq_ddrbus = sysclk;
- #endif
-
-- sys_info->freq_systembus *= (gur_in32(&gur->rcwsr[0]) >>
-- FSL_CHASSIS2_RCWSR0_SYS_PLL_RAT_SHIFT) &
-- FSL_CHASSIS2_RCWSR0_SYS_PLL_RAT_MASK;
-- sys_info->freq_ddrbus *= (gur_in32(&gur->rcwsr[0]) >>
-- FSL_CHASSIS2_RCWSR0_MEM_PLL_RAT_SHIFT) &
-- FSL_CHASSIS2_RCWSR0_MEM_PLL_RAT_MASK;
-+ svr = gur_in32(&gur->svr);
-+ ver = SVR_SOC_VER(svr);
-+ if (ver == SVR_LS1012) {
-+ sys_info->freq_ddrbus *= (gur_in32(&gur->rcwsr[0]) >>
-+ FSL_CHASSIS2_RCWSR0_SYS_PLL_RAT_SHIFT) &
-+ FSL_CHASSIS2_RCWSR0_SYS_PLL_RAT_MASK;
-+ } else {
-+ sys_info->freq_systembus *= (gur_in32(&gur->rcwsr[0]) >>
-+ FSL_CHASSIS2_RCWSR0_SYS_PLL_RAT_SHIFT) &
-+ FSL_CHASSIS2_RCWSR0_SYS_PLL_RAT_MASK;
-+ sys_info->freq_ddrbus *= (gur_in32(&gur->rcwsr[0]) >>
-+ FSL_CHASSIS2_RCWSR0_MEM_PLL_RAT_SHIFT) &
-+ FSL_CHASSIS2_RCWSR0_MEM_PLL_RAT_MASK;
-+ }
-
- for (i = 0; i < CONFIG_SYS_FSL_NUM_CC_PLLS; i++) {
- ratio[i] = (in_be32(&clk->pllcgsr[i].pllcngsr) >> 1) & 0xff;
-@@ -83,6 +92,9 @@ void get_sys_info(struct sys_info *sys_info)
- freq_c_pll[cplx_pll] / core_cplx_pll_div[c_pll_sel];
- }
-
-+ if (ver == SVR_LS1012)
-+ sys_info->freq_systembus = sys_info->freq_ddrbus / 2;
-+
- #define HWA_CGA_M1_CLK_SEL 0xe0000000
- #define HWA_CGA_M1_CLK_SHIFT 29
- #ifdef CONFIG_SYS_DPAA_FMAN
-diff --git a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S
-index 5f5bfb9..b40834a 100644
---- a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S
-+++ b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S
-@@ -184,6 +184,7 @@ ENTRY(lowlevel_init)
- ret
- ENDPROC(lowlevel_init)
-
-+#ifdef CONFIG_FSL_LSCH3
- hnf_pstate_poll:
- /* x0 has the desired status, return 0 for success, 1 for timeout
- * clobber x1, x2, x3, x4, x6, x7
-@@ -261,6 +262,7 @@ ENTRY(__asm_flush_l3_cache)
- mov lr, x29
- ret
- ENDPROC(__asm_flush_l3_cache)
-+#endif
-
- #ifdef CONFIG_MP
- /* Keep literals not used by the secondary boot code outside it */
-diff --git a/arch/arm/cpu/armv8/fsl-layerscape/ls1012a_serdes.c b/arch/arm/cpu/armv8/fsl-layerscape/ls1012a_serdes.c
-new file mode 100644
-index 0000000..ff0903c
---- /dev/null
-+++ b/arch/arm/cpu/armv8/fsl-layerscape/ls1012a_serdes.c
-@@ -0,0 +1,74 @@
-+/*
-+ * Copyright 2016 Freescale Semiconductor, Inc.
-+ *
-+ * SPDX-License-Identifier: GPL-2.0+
-+ */
-+
-+#include <common.h>
-+#include <asm/arch/fsl_serdes.h>
-+#include <asm/arch/immap_lsch2.h>
-+
-+struct serdes_config {
-+ u32 protocol;
-+ u8 lanes[SRDS_MAX_LANES];
-+};
-+
-+static struct serdes_config serdes1_cfg_tbl[] = {
-+ {0x2208, {SGMII_2500_FM1_DTSEC1, SGMII_2500_FM1_DTSEC2, NONE, SATA1} },
-+ {0x0008, {NONE, NONE, NONE, SATA1} },
-+ {0x3508, {SGMII_FM1_DTSEC1, PCIE1, NONE, SATA1} },
-+ {0x3305, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, NONE, PCIE1} },
-+ {0x2205, {SGMII_2500_FM1_DTSEC1, SGMII_2500_FM1_DTSEC2, NONE, PCIE1} },
-+ {0x2305, {SGMII_2500_FM1_DTSEC1, SGMII_FM1_DTSEC2, NONE, PCIE1} },
-+ {0x9508, {TX_CLK, PCIE1, NONE, SATA1} },
-+ {0x3905, {SGMII_FM1_DTSEC1, TX_CLK, NONE, PCIE1} },
-+ {0x9305, {TX_CLK, SGMII_FM1_DTSEC2, NONE, PCIE1} },
-+ {}
-+};
-+
-+static struct serdes_config *serdes_cfg_tbl[] = {
-+ serdes1_cfg_tbl,
-+};
-+
-+enum srds_prtcl serdes_get_prtcl(int serdes, int cfg, int lane)
-+{
-+ struct serdes_config *ptr;
-+
-+ if (serdes >= ARRAY_SIZE(serdes_cfg_tbl))
-+ return 0;
-+
-+ ptr = serdes_cfg_tbl[serdes];
-+ while (ptr->protocol) {
-+ if (ptr->protocol == cfg)
-+ return ptr->lanes[lane];
-+ ptr++;
-+ }
-+
-+ return 0;
-+}
-+
-+int is_serdes_prtcl_valid(int serdes, u32 prtcl)
-+{
-+ int i;
-+ struct serdes_config *ptr;
-+
-+ if (serdes >= ARRAY_SIZE(serdes_cfg_tbl))
-+ return 0;
-+
-+ ptr = serdes_cfg_tbl[serdes];
-+ while (ptr->protocol) {
-+ if (ptr->protocol == prtcl)
-+ break;
-+ ptr++;
-+ }
-+
-+ if (!ptr->protocol)
-+ return 0;
-+
-+ for (i = 0; i < SRDS_MAX_LANES; i++) {
-+ if (ptr->lanes[i] != NONE)
-+ return 1;
-+ }
-+
-+ return 0;
-+}
-diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
-index 23f0c88..ec561a7 100644
---- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
-+++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
-@@ -12,8 +12,10 @@
- #include <asm/io.h>
- #include <asm/global_data.h>
- #include <asm/arch-fsl-layerscape/config.h>
-+#ifdef CONFIG_SYS_FSL_DDR
- #include <fsl_ddr_sdram.h>
- #include <fsl_ddr.h>
-+#endif
- #ifdef CONFIG_CHAIN_OF_TRUST
- #include <fsl_validate.h>
- #endif
-@@ -46,14 +48,16 @@ static void erratum_a009008(void)
- static void erratum_a009798(void)
- {
- #ifdef CONFIG_SYS_FSL_ERRATUM_A009798
--#if defined(CONFIG_LS1043A)
-+#if defined(CONFIG_LS1043A) || defined(CONFIG_LS1012A)
- u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE;
- u32 val = scfg_in32(scfg + SCFG_USB3PRM1CR_USB1 / 4);
- scfg_out32(scfg + SCFG_USB3PRM1CR_USB1 / 4 , val & USB_SQRXTUNE);
-+#if defined(CONFIG_LS1043A)
- val = gur_in32(scfg + SCFG_USB3PRM1CR_USB2 / 4);
- scfg_out32(scfg + SCFG_USB3PRM1CR_USB2 / 4 , val & USB_SQRXTUNE);
- val = scfg_in32(scfg + SCFG_USB3PRM1CR_USB3 / 4);
- scfg_out32(scfg + SCFG_USB3PRM1CR_USB3 / 4 , val & USB_SQRXTUNE);
-+#endif
- #elif defined(CONFIG_LS2080A) || defined(CONFIG_LS2085A)
- u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE;
- u32 val = scfg_in32(scfg + SCFG_USB3PRM1CR / 4);
-diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h b/arch/arm/include/asm/arch-fsl-layerscape/config.h
-index f876c56..6ea4e8e 100644
---- a/arch/arm/include/asm/arch-fsl-layerscape/config.h
-+++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h
-@@ -14,8 +14,11 @@
- #else
- #define CONFIG_SYS_FSL_DDRC_ARM_GEN3 /* Enable Freescale ARM DDR3 driver */
- #endif
-+
-+#ifndef CONFIG_LS1012A
- #define CONFIG_SYS_FSL_DDR /* Freescale DDR driver */
- #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_5_0
-+#endif
-
- /*
- * Reserve secure memory
-@@ -205,6 +208,35 @@
- #define CONFIG_SYS_FSL_ERRATUM_A008997
- #define CONFIG_SYS_FSL_ERRATUM_A009007
- #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1
-+#elif defined(CONFIG_LS1012A)
-+#define CONFIG_MAX_CPUS 1
-+#define CONFIG_SYS_CACHELINE_SIZE 64
-+#define CONFIG_NUM_DDR_CONTROLLERS 1
-+#define CONFIG_SYS_CCSRBAR_DEFAULT 0x01000000
-+#define CONFIG_SYS_FSL_SEC_COMPAT 5
-+#undef CONFIG_SYS_FSL_DDRC_ARM_GEN3
-+
-+#define CONFIG_SYS_FSL_OCRAM_BASE 0x10000000 /* initial RAM */
-+#define CONFIG_SYS_FSL_OCRAM_SIZE 0x200000 /* 2 MiB */
-+
-+#define GICD_BASE 0x01401000
-+#define GICC_BASE 0x01402000
-+
-+#define CONFIG_SYS_FSL_CCSR_GUR_BE
-+#define CONFIG_SYS_FSL_CCSR_SCFG_BE
-+#define CONFIG_SYS_FSL_ESDHC_BE
-+#define CONFIG_SYS_FSL_WDOG_BE
-+#define CONFIG_SYS_FSL_DSPI_BE
-+#define CONFIG_SYS_FSL_QSPI_BE
-+#define CONFIG_SYS_FSL_PEX_LUT_BE
-+
-+#define SRDS_MAX_LANES 4
-+#define CONFIG_SYS_FSL_SRDS_1
-+#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4"
-+#define CONFIG_SYS_FSL_SEC_BE
-+
-+#define CONFIG_SYS_FSL_ERRATUM_A009798
-+
- #else
- #error SoC not defined
- #endif
-diff --git a/arch/arm/include/asm/arch-fsl-layerscape/cpu.h b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h
-index a7522da..e4ff990 100644
---- a/arch/arm/include/asm/arch-fsl-layerscape/cpu.h
-+++ b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h
-@@ -14,6 +14,7 @@ static struct cpu_type cpu_type_list[] = {
- CPU_TYPE_ENTRY(LS1043, LS1043, 4),
- CPU_TYPE_ENTRY(LS1023, LS1023, 2),
- CPU_TYPE_ENTRY(LS2040, LS2040, 4),
-+ CPU_TYPE_ENTRY(LS1012, LS1012, 1),
- };
-
- #ifndef CONFIG_SYS_DCACHE_OFF
-diff --git a/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h b/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h
-index 7096dac..4a3f4f3 100644
---- a/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h
-+++ b/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h
-@@ -134,6 +134,7 @@ enum srds_prtcl {
- SGMII_2500_FM2_DTSEC6,
- SGMII_2500_FM2_DTSEC9,
- SGMII_2500_FM2_DTSEC10,
-+ TX_CLK,
- SERDES_PRCTL_COUNT
- };
-
-diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
-index 2852f9c..5b026f8 100644
---- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
-+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
-@@ -62,7 +62,11 @@
- #define CONFIG_SYS_PCIE2_PHYS_ADDR 0x4800000000ULL
- #define CONFIG_SYS_PCIE3_PHYS_ADDR 0x5000000000ULL
- /* LUT registers */
-+#ifdef CONFIG_LS1012A
-+#define PCIE_LUT_BASE 0xC0000
-+#else
- #define PCIE_LUT_BASE 0x10000
-+#endif
- #define PCIE_LUT_LCTRL0 0x7F8
- #define PCIE_LUT_DBG 0x7FC
-
-diff --git a/arch/arm/include/asm/arch-fsl-layerscape/soc.h b/arch/arm/include/asm/arch-fsl-layerscape/soc.h
-index 56989e1..0822b49 100644
---- a/arch/arm/include/asm/arch-fsl-layerscape/soc.h
-+++ b/arch/arm/include/asm/arch-fsl-layerscape/soc.h
-@@ -41,6 +41,7 @@ struct cpu_type {
- { .name = #n, .soc_ver = SVR_##v, .num_cores = (nc)}
-
- #define SVR_WO_E 0xFFFFFE
-+#define SVR_LS1012 0x870400
- #define SVR_LS1043 0x879200
- #define SVR_LS1023 0x879208
- #define SVR_LS2045 0x870120
-diff --git a/include/fsl_mmdc.h b/include/fsl_mmdc.h
-new file mode 100644
-index 0000000..3df822e
---- /dev/null
-+++ b/include/fsl_mmdc.h
-@@ -0,0 +1,53 @@
-+/*
-+ * Copyright 2015 Freescale Semiconductor, Inc.
-+ *
-+ * SPDX-License-Identifier: GPL-2.0+
-+ */
-+
-+#ifndef FSL_MMDC_H
-+#define FSL_MMDC_H
-+
-+/* MMDC Registers */
-+struct mmdc_p_regs {
-+ u32 mdctl;
-+ u32 mdpdc;
-+ u32 mdotc;
-+ u32 mdcfg0;
-+ u32 mdcfg1;
-+ u32 mdcfg2;
-+ u32 mdmisc;
-+ u32 mdscr;
-+ u32 mdref;
-+ u32 res1[2];
-+ u32 mdrwd;
-+ u32 mdor;
-+ u32 mdmrr;
-+ u32 mdcfg3lp;
-+ u32 mdmr4;
-+ u32 mdasp;
-+ u32 res3[239];
-+ u32 maarcr;
-+ u32 mapsr;
-+ u32 res4[254];
-+ u32 mpzqhwctrl;
-+ u32 res5[2];
-+ u32 mpwldectrl0;
-+ u32 mpwldectrl1;
-+ u32 res6;
-+ u32 mpodtctrl;
-+ u32 mprddqby0dl;
-+ u32 mprddqby1dl;
-+ u32 mprddqby2dl;
-+ u32 mprddqby3dl;
-+ u32 res7[4];
-+ u32 mpdgctrl0;
-+ u32 mpdgctrl1;
-+ u32 res8;
-+ u32 mprddlctl;
-+ u32 res9;
-+ u32 mpwrdlctl;
-+ u32 res10[25];
-+ u32 mpmur0;
-+};
-+
-+#endif /* FSL_MMDC_H */
-diff --git a/include/linux/usb/xhci-fsl.h b/include/linux/usb/xhci-fsl.h
-index 4966608..72a5d5b 100644
---- a/include/linux/usb/xhci-fsl.h
-+++ b/include/linux/usb/xhci-fsl.h
-@@ -66,6 +66,10 @@ struct fsl_xhci {
- #define CONFIG_SYS_FSL_XHCI_USB1_ADDR CONFIG_SYS_LS1043A_XHCI_USB1_ADDR
- #define CONFIG_SYS_FSL_XHCI_USB2_ADDR CONFIG_SYS_LS1043A_XHCI_USB2_ADDR
- #define CONFIG_SYS_FSL_XHCI_USB3_ADDR CONFIG_SYS_LS1043A_XHCI_USB3_ADDR
-+#elif defined(CONFIG_LS1012A)
-+#define CONFIG_SYS_FSL_XHCI_USB1_ADDR CONFIG_SYS_LS1043A_XHCI_USB1_ADDR
-+#define CONFIG_SYS_FSL_XHCI_USB2_ADDR 0
-+#define CONFIG_SYS_FSL_XHCI_USB3_ADDR 0
- #endif
-
- #define FSL_USB_XHCI_ADDR {CONFIG_SYS_FSL_XHCI_USB1_ADDR, \
---
-1.7.9.5
-
diff --git a/package/boot/uboot-layerscape/patches/0014-armv8-ls1012a-Add-support-of-ls1012aqds-board.patch b/package/boot/uboot-layerscape/patches/0014-armv8-ls1012a-Add-support-of-ls1012aqds-board.patch
deleted file mode 100644
index 4a9ebfa..0000000
--- a/package/boot/uboot-layerscape/patches/0014-armv8-ls1012a-Add-support-of-ls1012aqds-board.patch
+++ /dev/null
@@ -1,1237 +0,0 @@
-From faf0aac702a2253471f98687ed40138e514e38ab Mon Sep 17 00:00:00 2001
-From: Prabhakar Kushwaha <prabhakar.kushwaha at nxp.com>
-Date: Mon, 25 Apr 2016 14:36:16 +0530
-Subject: [PATCH 14/93] armv8: ls1012a: Add support of ls1012aqds board
-
-QorIQ LS1012A Development System (LS1012AQDS) is a high-performance
-development platform, with a complete debugging environment.
-The LS1012AQDS board supports the QorIQ LS1012A processor and is
-optimized to support the high-bandwidth DDR3L memory and
-a full complement of high-speed SerDes ports.
-
-Signed-off-by: Calvin Johnson <calvin.johnson at nxp.com>
-Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha at nxp.com>
----
- arch/arm/Kconfig | 10 ++
- arch/arm/dts/Makefile | 3 +-
- arch/arm/dts/fsl-ls1012a-qds.dts | 14 ++
- arch/arm/dts/fsl-ls1012a-qds.dtsi | 123 +++++++++++++
- arch/arm/dts/fsl-ls1012a.dtsi | 119 ++++++++++++
- board/freescale/ls1012aqds/Kconfig | 15 ++
- board/freescale/ls1012aqds/MAINTAINERS | 6 +
- board/freescale/ls1012aqds/Makefile | 7 +
- board/freescale/ls1012aqds/README | 94 ++++++++++
- board/freescale/ls1012aqds/ls1012aqds.c | 199 ++++++++++++++++++++
- board/freescale/ls1012aqds/ls1012aqds_qixis.h | 35 ++++
- configs/ls1012aqds_qspi_defconfig | 10 ++
- include/configs/ls1012a_common.h | 239 +++++++++++++++++++++++++
- include/configs/ls1012aqds.h | 133 ++++++++++++++
- include/fsl_mmdc.h | 57 +++++-
- 15 files changed, 1055 insertions(+), 9 deletions(-)
- create mode 100644 arch/arm/dts/fsl-ls1012a-qds.dts
- create mode 100644 arch/arm/dts/fsl-ls1012a-qds.dtsi
- create mode 100644 arch/arm/dts/fsl-ls1012a.dtsi
- create mode 100644 board/freescale/ls1012aqds/Kconfig
- create mode 100644 board/freescale/ls1012aqds/MAINTAINERS
- create mode 100644 board/freescale/ls1012aqds/Makefile
- create mode 100644 board/freescale/ls1012aqds/README
- create mode 100644 board/freescale/ls1012aqds/ls1012aqds.c
- create mode 100644 board/freescale/ls1012aqds/ls1012aqds_qixis.h
- create mode 100644 configs/ls1012aqds_qspi_defconfig
- create mode 100644 include/configs/ls1012a_common.h
- create mode 100644 include/configs/ls1012aqds.h
-
-diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
-index 9bd6cf1..f5033db 100644
---- a/arch/arm/Kconfig
-+++ b/arch/arm/Kconfig
-@@ -647,6 +647,15 @@ config TARGET_HIKEY
- Support for HiKey 96boards platform. It features a HI6220
- SoC, with 8xA53 CPU, mali450 gpu, and 1GB RAM.
-
-+config TARGET_LS1012AQDS
-+ bool "Support ls1012aqds"
-+ select ARM64
-+ help
-+ Support for Freescale LS1012AQDS platform.
-+ The LS1012A Development System (QDS) is a high-performance
-+ development platform that supports the QorIQ LS1012A
-+ Layerscape Architecture processor.
-+
- config TARGET_LS1021AQDS
- bool "Support ls1021aqds"
- select CPU_V7
-@@ -792,6 +801,7 @@ source "board/freescale/ls1021aqds/Kconfig"
- source "board/freescale/ls1043aqds/Kconfig"
- source "board/freescale/ls1021atwr/Kconfig"
- source "board/freescale/ls1043ardb/Kconfig"
-+source "board/freescale/ls1012aqds/Kconfig"
- source "board/freescale/mx23evk/Kconfig"
- source "board/freescale/mx25pdk/Kconfig"
- source "board/freescale/mx28evk/Kconfig"
-diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
-index c1c81e4..ed5eb38 100644
---- a/arch/arm/dts/Makefile
-+++ b/arch/arm/dts/Makefile
-@@ -94,7 +94,8 @@ dtb-$(CONFIG_FSL_LSCH3) += fsl-ls2080a-qds.dtb \
- fsl-ls2080a-rdb.dtb
- dtb-$(CONFIG_FSL_LSCH2) += fsl-ls1043a-qds-duart.dtb \
- fsl-ls1043a-qds-lpuart.dtb \
-- fsl-ls1043a-rdb.dtb
-+ fsl-ls1043a-rdb.dtb \
-+ fsl-ls1012a-qds.dtb
-
- dtb-$(CONFIG_MACH_SUN4I) += \
- sun4i-a10-a1000.dtb \
-diff --git a/arch/arm/dts/fsl-ls1012a-qds.dts b/arch/arm/dts/fsl-ls1012a-qds.dts
-new file mode 100644
-index 0000000..ef6de34
---- /dev/null
-+++ b/arch/arm/dts/fsl-ls1012a-qds.dts
-@@ -0,0 +1,14 @@
-+/*
-+ * Copyright (C) 2016 Freescale Semiconductor
-+ *
-+ * SPDX-License-Identifier: GPL-2.0+
-+ */
-+
-+/dts-v1/;
-+#include "fsl-ls1012a-qds.dtsi"
-+
-+/ {
-+ chosen {
-+ stdout-path = &duart0;
-+ };
-+};
-diff --git a/arch/arm/dts/fsl-ls1012a-qds.dtsi b/arch/arm/dts/fsl-ls1012a-qds.dtsi
-new file mode 100644
-index 0000000..a32a84a
---- /dev/null
-+++ b/arch/arm/dts/fsl-ls1012a-qds.dtsi
-@@ -0,0 +1,123 @@
-+/*
-+ * Copyright (C) 2016 Freescale Semiconductor
-+ *
-+ * SPDX-License-Identifier: GPL-2.0+
-+ */
-+
-+/include/ "fsl-ls1012a.dtsi"
-+
-+/ {
-+ model = "LS1012A QDS Board";
-+ aliases {
-+ spi0 = &qspi;
-+ spi1 = &dspi0;
-+ };
-+};
-+
-+&dspi0 {
-+ bus-num = <0>;
-+ status = "okay";
-+
-+ dflash0: n25q128a {
-+ #address-cells = <1>;
-+ #size-cells = <1>;
-+ compatible = "spi-flash";
-+ reg = <0>;
-+ spi-max-frequency = <1000000>; /* input clock */
-+ };
-+
-+ dflash1: sst25wf040b {
-+ #address-cells = <1>;
-+ #size-cells = <1>;
-+ compatible = "spi-flash";
-+ spi-max-frequency = <3500000>;
-+ reg = <1>;
-+ };
-+
-+ dflash2: en25s64 {
-+ #address-cells = <1>;
-+ #size-cells = <1>;
-+ compatible = "spi-flash";
-+ spi-max-frequency = <3500000>;
-+ reg = <2>;
-+ };
-+};
-+
-+&qspi {
-+ bus-num = <0>;
-+ status = "okay";
-+
-+ qflash0: s25fl128s at 0 {
-+ #address-cells = <1>;
-+ #size-cells = <1>;
-+ compatible = "spi-flash";
-+ spi-max-frequency = <20000000>;
-+ reg = <0>;
-+ };
-+};
-+
-+&i2c0 {
-+ status = "okay";
-+ pca9547 at 77 {
-+ compatible = "philips,pca9547";
-+ reg = <0x77>;
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+
-+ i2c at 0 {
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+ reg = <0x0>;
-+
-+ rtc at 68 {
-+ compatible = "dallas,ds3232";
-+ reg = <0x68>;
-+ /* IRQ10_B */
-+ interrupts = <0 150 0x4>;
-+ };
-+ };
-+
-+ i2c at 2 {
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+ reg = <0x2>;
-+
-+ ina220 at 40 {
-+ compatible = "ti,ina220";
-+ reg = <0x40>;
-+ shunt-resistor = <1000>;
-+ };
-+
-+ ina220 at 41 {
-+ compatible = "ti,ina220";
-+ reg = <0x41>;
-+ shunt-resistor = <1000>;
-+ };
-+ };
-+
-+ i2c at 3 {
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+ reg = <0x3>;
-+
-+ eeprom at 56 {
-+ compatible = "at24,24c512";
-+ reg = <0x56>;
-+ };
-+
-+ eeprom at 57 {
-+ compatible = "at24,24c512";
-+ reg = <0x57>;
-+ };
-+
-+ adt7461a at 4c {
-+ compatible = "adt7461a";
-+ reg = <0x4c>;
-+ };
-+ };
-+ };
-+};
-+
-+&duart0 {
-+ status = "okay";
-+};
-diff --git a/arch/arm/dts/fsl-ls1012a.dtsi b/arch/arm/dts/fsl-ls1012a.dtsi
-new file mode 100644
-index 0000000..87a287a
---- /dev/null
-+++ b/arch/arm/dts/fsl-ls1012a.dtsi
-@@ -0,0 +1,119 @@
-+/*
-+ * Copyright (C) 2016 Freescale Semiconductor
-+ *
-+ * SPDX-License-Identifier: GPL-2.0+
-+ */
-+
-+/include/ "skeleton64.dtsi"
-+
-+/ {
-+ compatible = "fsl,ls1012a";
-+ interrupt-parent = <&gic>;
-+ cpus {
-+ #address-cells = <2>;
-+ #size-cells = <0>;
-+
-+ cpu0: cpu at 0 {
-+ device_type = "cpu";
-+ compatible = "arm,cortex-a53";
-+ reg = <0x0 0x0>;
-+ clocks = <&clockgen 1 0>;
-+ };
-+
-+ };
-+
-+ sysclk: sysclk {
-+ compatible = "fixed-clock";
-+ #clock-cells = <0>;
-+ clock-frequency = <100000000>;
-+ clock-output-names = "sysclk";
-+ };
-+
-+ gic: interrupt-controller at 1400000 {
-+ compatible = "arm,gic-400";
-+ #interrupt-cells = <3>;
-+ interrupt-controller;
-+ reg = <0x0 0x1401000 0 0x1000>, /* GICD */
-+ <0x0 0x1402000 0 0x2000>, /* GICC */
-+ <0x0 0x1404000 0 0x2000>, /* GICH */
-+ <0x0 0x1406000 0 0x2000>; /* GICV */
-+ interrupts = <1 9 0xf08>;
-+ };
-+
-+ soc {
-+ compatible = "simple-bus";
-+ #address-cells = <2>;
-+ #size-cells = <2>;
-+ ranges;
-+
-+ clockgen: clocking at 1ee1000 {
-+ compatible = "fsl,ls1012a-clockgen";
-+ reg = <0x0 0x1ee1000 0x0 0x1000>;
-+ #clock-cells = <2>;
-+ clocks = <&sysclk>;
-+ };
-+
-+ dspi0: dspi at 2100000 {
-+ compatible = "fsl,vf610-dspi";
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+ reg = <0x0 0x2100000 0x0 0x10000>;
-+ interrupts = <0 64 0x4>;
-+ clock-names = "dspi";
-+ clocks = <&clockgen 4 0>;
-+ num-cs = <6>;
-+ big-endian;
-+ status = "disabled";
-+ };
-+
-+
-+ i2c0: i2c at 2180000 {
-+ compatible = "fsl,vf610-i2c";
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+ reg = <0x0 0x2180000 0x0 0x10000>;
-+ interrupts = <0 56 0x4>;
-+ clock-names = "i2c";
-+ clocks = <&clockgen 4 0>;
-+ status = "disabled";
-+ };
-+
-+ i2c1: i2c at 2190000 {
-+ compatible = "fsl,vf610-i2c";
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+ reg = <0x0 0x2190000 0x0 0x10000>;
-+ interrupts = <0 57 0x4>;
-+ clock-names = "i2c";
-+ clocks = <&clockgen 4 0>;
-+ status = "disabled";
-+ };
-+
-+ duart0: serial at 21c0500 {
-+ compatible = "fsl,ns16550", "ns16550a";
-+ reg = <0x00 0x21c0500 0x0 0x100>;
-+ interrupts = <0 54 0x4>;
-+ clocks = <&clockgen 4 0>;
-+ };
-+
-+ duart1: serial at 21c0600 {
-+ compatible = "fsl,ns16550", "ns16550a";
-+ reg = <0x00 0x21c0600 0x0 0x100>;
-+ interrupts = <0 54 0x4>;
-+ clocks = <&clockgen 4 0>;
-+ };
-+
-+ qspi: quadspi at 1550000 {
-+ compatible = "fsl,vf610-qspi";
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+ reg = <0x0 0x1550000 0x0 0x10000>,
-+ <0x0 0x40000000 0x0 0x4000000>;
-+ reg-names = "QuadSPI", "QuadSPI-memory";
-+ num-cs = <2>;
-+ big-endian;
-+ status = "disabled";
-+ };
-+
-+ };
-+};
-diff --git a/board/freescale/ls1012aqds/Kconfig b/board/freescale/ls1012aqds/Kconfig
-new file mode 100644
-index 0000000..1257ec8
---- /dev/null
-+++ b/board/freescale/ls1012aqds/Kconfig
-@@ -0,0 +1,15 @@
-+if TARGET_LS1012AQDS
-+
-+config SYS_BOARD
-+ default "ls1012aqds"
-+
-+config SYS_VENDOR
-+ default "freescale"
-+
-+config SYS_SOC
-+ default "fsl-layerscape"
-+
-+config SYS_CONFIG_NAME
-+ default "ls1012aqds"
-+
-+endif
-diff --git a/board/freescale/ls1012aqds/MAINTAINERS b/board/freescale/ls1012aqds/MAINTAINERS
-new file mode 100644
-index 0000000..3c01df6
---- /dev/null
-+++ b/board/freescale/ls1012aqds/MAINTAINERS
-@@ -0,0 +1,6 @@
-+LS1012AQDS BOARD
-+M:
-+S: Maintained
-+F: board/freescale/ls1012aqds/
-+F: include/configs/ls1012aqds.h
-+F: configs/ls1012aqds_defconfig
-diff --git a/board/freescale/ls1012aqds/Makefile b/board/freescale/ls1012aqds/Makefile
-new file mode 100644
-index 0000000..0b813f9
---- /dev/null
-+++ b/board/freescale/ls1012aqds/Makefile
-@@ -0,0 +1,7 @@
-+#
-+# Copyright 2016 Freescale Semiconductor, Inc.
-+#
-+# SPDX-License-Identifier: GPL-2.0+
-+#
-+
-+obj-y += ls1012aqds.o
-diff --git a/board/freescale/ls1012aqds/README b/board/freescale/ls1012aqds/README
-new file mode 100644
-index 0000000..e94a267
---- /dev/null
-+++ b/board/freescale/ls1012aqds/README
-@@ -0,0 +1,94 @@
-+Overview
-+--------
-+The LS1012AQDS power supplies (PS) provide all the voltages necessary
-+for the correct operation of the LS1012A processor, DDR3L, QSPI memory,
-+and other onboard peripherals.
-+
-+LS1012A SoC Overview
-+--------------------
-+The LS1012A features an advanced 64-bit ARM v8 Cortex-
-+A53 processor, with 32 KB of parity protected L1-I cache,
-+32 KB of ECC protected L1-D cache, as well as 256 KB of
-+ECC protected L2 cache.
-+
-+The LS1012A SoC includes the following function and features:
-+ - One 64-bit ARM v8 Cortex-A53 core with the following capabilities:
-+ - ARM v8 cryptography extensions
-+ - One 16-bit DDR3L SDRAM memory controller, Up to 1.0 GT/s, Supports
-+ 16-/8-bit operation (no ECC support)
-+ - ARM core-link CCI-400 cache coherent interconnect
-+ - Packet Forwarding Engine (PFE)
-+ - Cryptography acceleration (SEC)
-+ - Ethernet interfaces supported by PFE:
-+ - One Configurable x3 SerDes:
-+ Two Serdes PLLs supported for usage by any SerDes data lane
-+ Support for up to 6 GBaud operation
-+ - High-speed peripheral interfaces:
-+ - One PCI Express Gen2 controller, supporting x1 operation
-+ - One serial ATA (SATA Gen 3.0) controller
-+ - One USB 3.0/2.0 controller with integrated PHY
-+ - One USB 2.0 controller with ULPI interface. .
-+ - Additional peripheral interfaces:
-+ - One quad serial peripheral interface (QuadSPI) controller
-+ - One serial peripheral interface (SPI) controller
-+ - Two enhanced secure digital host controllers
-+ - Two I2C controllers
-+ - One 16550 compliant DUART (two UART interfaces)
-+ - Two general purpose IOs (GPIO)
-+ - Two FlexTimers
-+ - Five synchronous audio interfaces (SAI)
-+ - Pre-boot loader (PBL) provides pre-boot initialization and RCW loading
-+ - Single-source clocking solution enabling generation of core, platform,
-+ DDR, SerDes, and USB clocks from a single external crystal and internal
-+ crystaloscillator
-+ - Thermal monitor unit (TMU) with +/- 3C accuracy
-+ - Two WatchDog timers
-+ - ARM generic timer
-+ - QorIQ platform's trust architecture 2.1
-+
-+ LS1012AQDS board Overview
-+ -----------------------
-+ - SERDES Connections, 4 lanes supporting:
-+ - PCI Express - 3.0
-+ - SGMII, SGMII 2.5
-+ - SATA 3.0
-+ - DDR Controller
-+ - 6-bit, 1 GB DDR3L SDRAM memory, running at data rates up to 1 GT/s
-+ - QSPI Controller
-+ - A dual 1:3 switch, NX3L4357GM,115 (U35) drives the QSPI chip-select
-+ signals to QSPI NOR flash memory (2 virtual banks) and the QSPI
-+ emulator
-+ - USB 3.0
-+ - One USB 3.0 controller with integrated PHY
-+ - One high-speed USB 3.0 port
-+ - USB 2.0
-+ - One USB 2.0 controller with ULPI interface
-+ - Two enhanced secure digital host controllers:
-+ - SDHC1 controller can be connected to onboard SDHC connector
-+ - SDHC2 controller: 1-/4-bit SD/MMC card supporting 1.8 V devices
-+ - 2 I2C controllers
-+ - One SATA onboard connectors
-+ - UART
-+ - 5 SAI
-+ - One SAI port with audio codec SGTL5000:
-+ • Provides MIC bias
-+ • Provides headphone and line output
-+ - One SAI port terminated at 2x6 header
-+ - Three SAI Tx/Rx ports terminated at 2x3 headers
-+ - ARM JTAG support
-+
-+Booting Options
-+---------------
-+a) QSPI Flash Emu Boot
-+b) QSPI Flash 1
-+c) QSPI Flash 2
-+
-+QSPI flash map
-+--------------
-+Images | Size |QSPI Flash Address
-+------------------------------------------
-+RCW + PBI | 1MB | 0x4000_0000
-+U-boot | 1MB | 0x4010_0000
-+U-boot Env | 1MB | 0x4020_0000
-+PPA FIT image | 2MB | 0x4050_0000
-+Linux ITB | ~53MB | 0x40A0_0000
-diff --git a/board/freescale/ls1012aqds/ls1012aqds.c b/board/freescale/ls1012aqds/ls1012aqds.c
-new file mode 100644
-index 0000000..ffcd0d8
---- /dev/null
-+++ b/board/freescale/ls1012aqds/ls1012aqds.c
-@@ -0,0 +1,199 @@
-+/*
-+ * Copyright 2016 Freescale Semiconductor, Inc.
-+ *
-+ * SPDX-License-Identifier: GPL-2.0+
-+ */
-+
-+#include <common.h>
-+#include <i2c.h>
-+#include <fdt_support.h>
-+#include <asm/io.h>
-+#include <asm/arch/clock.h>
-+#include <asm/arch/fsl_serdes.h>
-+#include <asm/arch/fdt.h>
-+#include <asm/arch/soc.h>
-+#include <ahci.h>
-+#include <hwconfig.h>
-+#include <mmc.h>
-+#include <scsi.h>
-+#include <fm_eth.h>
-+#include <fsl_csu.h>
-+#include <fsl_esdhc.h>
-+#include <fsl_mmdc.h>
-+#include <spl.h>
-+#include <netdev.h>
-+
-+#include "../common/qixis.h"
-+#include "ls1012aqds_qixis.h"
-+
-+DECLARE_GLOBAL_DATA_PTR;
-+
-+int checkboard(void)
-+{
-+ puts("Board: LS1012AQDS\n");
-+
-+ return 0;
-+}
-+
-+void mmdc_init(void)
-+{
-+ struct mmdc_p_regs *mmdc =
-+ (struct mmdc_p_regs *)CONFIG_SYS_FSL_DDR_ADDR;
-+
-+ /* Set MMDC_MDSCR[CON_REQ] */
-+ out_be32(&mmdc->mdscr, 0x00008000);
-+
-+ /* configure timing parms */
-+ out_be32(&mmdc->mdotc, 0x12554000);
-+ out_be32(&mmdc->mdcfg0, 0xbabf7954);
-+ out_be32(&mmdc->mdcfg1, 0xff328f64);
-+ out_be32(&mmdc->mdcfg2, 0x01ff00db);
-+
-+ /* other parms */
-+ out_be32(&mmdc->mdmisc, 0x00000680);
-+ out_be32(&mmdc->mpmur0, 0x00000800);
-+ out_be32(&mmdc->mdrwd, 0x00002000);
-+ out_be32(&mmdc->mpodtctrl, 0x0000022a);
-+
-+ /* out of reset delays */
-+ out_be32(&mmdc->mdor, 0x00bf1023);
-+
-+ /* physical parms */
-+ out_be32(&mmdc->mdctl, 0x05180000);
-+ out_be32(&mmdc->mdasp, 0x0000007f);
-+
-+ /* Enable MMDC */
-+ out_be32(&mmdc->mdctl, 0x85180000);
-+
-+ /* dram init sequence: update MRs */
-+ out_be32(&mmdc->mdscr, 0x00088032);
-+ out_be32(&mmdc->mdscr, 0x00008033);
-+ out_be32(&mmdc->mdscr, 0x00048031);
-+ out_be32(&mmdc->mdscr, 0x19308030);
-+
-+ /* dram init sequence: ZQCL */
-+ out_be32(&mmdc->mdscr, 0x04008040);
-+ out_be32(&mmdc->mpzqhwctrl, 0xa1390003);
-+
-+ mdelay(100);
-+
-+ /* Calibrations now: wr lvl */
-+ out_be32(&mmdc->mdscr, 0x00848031);
-+ out_be32(&mmdc->mdscr, 0x00008200);
-+ out_be32(&mmdc->mpwlgcr, 0x00000001);
-+
-+ mdelay(100);
-+
-+ out_be32(&mmdc->mdscr, 0x00048031);
-+ out_be32(&mmdc->mdscr, 0x00008000);
-+
-+ /* manual_refresh */
-+ out_be32(&mmdc->mdscr, 0x00008020);
-+
-+ mdelay(100);
-+
-+ /* Calibrations now: Read DQS gating calibration */
-+ out_be32(&mmdc->mdscr, 0x04008050);
-+ out_be32(&mmdc->mdscr, 0x00048033);
-+ out_be32(&mmdc->mppdcmpr2, 0x00000001);
-+ out_be32(&mmdc->mprddlctl, 0x40404040);
-+ out_be32(&mmdc->mpdgctrl0, 0x10000000);
-+
-+ mdelay(100);
-+
-+ out_be32(&mmdc->mdscr, 0x00008033);
-+
-+ /* manual_refresh */
-+ out_be32(&mmdc->mdscr, 0x00008020);
-+
-+ mdelay(100);
-+
-+ /* Calibrations now: Read calibration */
-+ out_be32(&mmdc->mdscr, 0x04008050);
-+ out_be32(&mmdc->mdscr, 0x00048033);
-+ out_be32(&mmdc->mppdcmpr2, 0x00000001);
-+ out_be32(&mmdc->mprddlhwctl, 0x00000010);
-+
-+ mdelay(400);
-+
-+ out_be32(&mmdc->mdscr, 0x00008033);
-+
-+ /* manual_refresh */
-+ out_be32(&mmdc->mdscr, 0x00008020);
-+
-+ mdelay(100);
-+
-+ /* PD, SR */
-+ out_be32(&mmdc->mdpdc, 0x00030035);
-+ out_be32(&mmdc->mapsr, 0x00001067);
-+
-+ /* refresh scheme */
-+ out_be32(&mmdc->mdref, 0x103e8000);
-+
-+ mdelay(400);
-+
-+ /* disable CON_REQ */
-+ out_be32(&mmdc->mdscr, 0x0);
-+
-+ mdelay(50);
-+}
-+
-+int dram_init(void)
-+{
-+ mmdc_init();
-+
-+ gd->ram_size = 0x40000000;
-+
-+ return 0;
-+}
-+
-+int board_early_init_f(void)
-+{
-+ fsl_lsch2_early_init_f();
-+
-+ return 0;
-+}
-+
-+int board_init(void)
-+{
-+ struct ccsr_cci400 *cci = (struct ccsr_cci400 *)
-+ CONFIG_SYS_CCI400_ADDR;
-+
-+ /* Set CCI-400 control override register to enable barrier
-+ * transaction */
-+ out_le32(&cci->ctrl_ord,
-+ CCI400_CTRLORD_EN_BARRIER);
-+
-+#ifdef CONFIG_LAYERSCAPE_NS_ACCESS
-+ enable_layerscape_ns_access();
-+#endif
-+
-+#ifdef CONFIG_ENV_IS_NOWHERE
-+ gd->env_addr = (ulong)&default_environment[0];
-+#endif
-+ return 0;
-+}
-+
-+int board_eth_init(bd_t *bis)
-+{
-+ return pci_eth_init(bis);
-+}
-+
-+#ifdef CONFIG_OF_BOARD_SETUP
-+int ft_board_setup(void *blob, bd_t *bd)
-+{
-+ u64 base[CONFIG_NR_DRAM_BANKS];
-+ u64 size[CONFIG_NR_DRAM_BANKS];
-+
-+ /* fixup DT for the two DDR banks */
-+ base[0] = gd->bd->bi_dram[0].start;
-+ size[0] = gd->bd->bi_dram[0].size;
-+ base[1] = gd->bd->bi_dram[1].start;
-+ size[1] = gd->bd->bi_dram[1].size;
-+
-+ fdt_fixup_memory_banks(blob, base, size, 2);
-+ ft_cpu_setup(blob, bd);
-+
-+ return 0;
-+}
-+#endif
-diff --git a/board/freescale/ls1012aqds/ls1012aqds_qixis.h b/board/freescale/ls1012aqds/ls1012aqds_qixis.h
-new file mode 100644
-index 0000000..584f604
---- /dev/null
-+++ b/board/freescale/ls1012aqds/ls1012aqds_qixis.h
-@@ -0,0 +1,35 @@
-+/*
-+ * Copyright 2016 Freescale Semiconductor, Inc.
-+ *
-+ * SPDX-License-Identifier: GPL-2.0+
-+ */
-+
-+#ifndef __LS1043AQDS_QIXIS_H__
-+#define __LS1043AQDS_QIXIS_H__
-+
-+/* Definitions of QIXIS Registers for LS1043AQDS */
-+
-+/* BRDCFG4[4:7] select EC1 and EC2 as a pair */
-+#define BRDCFG4_EMISEL_MASK 0xe0
-+#define BRDCFG4_EMISEL_SHIFT 5
-+
-+/* SYSCLK */
-+#define QIXIS_SYSCLK_66 0x0
-+#define QIXIS_SYSCLK_83 0x1
-+#define QIXIS_SYSCLK_100 0x2
-+#define QIXIS_SYSCLK_125 0x3
-+#define QIXIS_SYSCLK_133 0x4
-+
-+/* DDRCLK */
-+#define QIXIS_DDRCLK_66 0x0
-+#define QIXIS_DDRCLK_100 0x1
-+#define QIXIS_DDRCLK_125 0x2
-+#define QIXIS_DDRCLK_133 0x3
-+
-+/* BRDCFG2 - SD clock*/
-+#define QIXIS_SDCLK1_100 0x0
-+#define QIXIS_SDCLK1_125 0x1
-+#define QIXIS_SDCLK1_165 0x2
-+#define QIXIS_SDCLK1_100_SP 0x3
-+
-+#endif
-diff --git a/configs/ls1012aqds_qspi_defconfig b/configs/ls1012aqds_qspi_defconfig
-new file mode 100644
-index 0000000..ef2c0ad
---- /dev/null
-+++ b/configs/ls1012aqds_qspi_defconfig
-@@ -0,0 +1,10 @@
-+CONFIG_ARM=y
-+CONFIG_TARGET_LS1012AQDS=y
-+CONFIG_SYS_EXTRA_OPTIONS="QSPI_BOOT"
-+# CONFIG_CMD_IMLS is not set
-+CONFIG_SYS_NS16550=y
-+CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1012a-qds"
-+CONFIG_OF_CONTROL=y
-+CONFIG_DM=y
-+CONFIG_SPI_FLASH=y
-+CONFIG_DM_SPI=y
-diff --git a/include/configs/ls1012a_common.h b/include/configs/ls1012a_common.h
-new file mode 100644
-index 0000000..9ed04f9
---- /dev/null
-+++ b/include/configs/ls1012a_common.h
-@@ -0,0 +1,239 @@
-+/*
-+ * Copyright (C) 2015 Freescale Semiconductor
-+ *
-+ * SPDX-License-Identifier: GPL-2.0+
-+ */
-+
-+#ifndef __LS1012A_COMMON_H
-+#define __LS1012A_COMMON_H
-+
-+#define CONFIG_FSL_LAYERSCAPE
-+#define CONFIG_FSL_LSCH2
-+#define CONFIG_LS1012A
-+#define CONFIG_GICV2
-+
-+#define CONFIG_SYS_HAS_SERDES
-+
-+#include <asm/arch/config.h>
-+#define CONFIG_SYS_NO_FLASH
-+
-+#define CONFIG_SUPPORT_RAW_INITRD
-+
-+#define CONFIG_DISPLAY_BOARDINFO_LATE
-+
-+#define CONFIG_SYS_TEXT_BASE 0x40100000
-+
-+#define CONFIG_SYS_FSL_CLK
-+#define CONFIG_SYS_CLK_FREQ 100000000
-+#define CONFIG_DDR_CLK_FREQ 125000000
-+
-+#define CONFIG_SKIP_LOWLEVEL_INIT
-+#define CONFIG_BOARD_EARLY_INIT_F 1
-+
-+#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0)
-+#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000)
-+
-+#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000
-+#define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0
-+#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
-+
-+/* Generic Timer Definitions */
-+#define COUNTER_FREQUENCY 25000000 /* 12MHz */
-+
-+/* CSU */
-+#define CONFIG_LAYERSCAPE_NS_ACCESS
-+
-+/* Size of malloc() pool */
-+#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128 * 1024)
-+
-+/*SPI device */
-+#ifdef CONFIG_QSPI_BOOT
-+#define CONFIG_SYS_QE_FW_IN_SPIFLASH
-+#define CONFIG_SYS_FMAN_FW_ADDR 0x400d0000
-+#define CONFIG_ENV_SPI_BUS 0
-+#define CONFIG_ENV_SPI_CS 0
-+#define CONFIG_ENV_SPI_MAX_HZ 1000000
-+#define CONFIG_ENV_SPI_MODE 0x03
-+#define CONFIG_CMD_SF
-+#define CONFIG_SPI_FLASH_SPANSION
-+#define CONFIG_SPI_FLASH_ATMEL
-+#define CONFIG_FSL_SPI_INTERFACE
-+#define CONFIG_SF_DATAFLASH
-+
-+#define CONFIG_FSL_QSPI
-+#define QSPI0_AMBA_BASE 0x40000000
-+#define CONFIG_SPI_FLASH_SPANSION
-+#define CONFIG_DM_SPI_FLASH
-+#define CONFIG_SPI_FLASH_BAR
-+
-+#define FSL_QSPI_FLASH_SIZE (1 << 24)
-+#define FSL_QSPI_FLASH_NUM 2
-+
-+/*
-+ * Environment
-+ */
-+#define CONFIG_ENV_OVERWRITE
-+
-+#define CONFIG_ENV_IS_IN_SPI_FLASH
-+#define CONFIG_ENV_SIZE 0x40000 /* 256KB */
-+#define CONFIG_ENV_OFFSET 0x200000 /* 2MB */
-+#define CONFIG_ENV_SECT_SIZE 0x40000
-+#endif
-+
-+/* I2C */
-+#if !defined(CONFIG_EMU)
-+#define CONFIG_CMD_I2C
-+#define CONFIG_SYS_I2C
-+#define CONFIG_SYS_I2C_MXC
-+#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
-+#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
-+#endif /* CONFIG_EMU */
-+
-+/* MMC */
-+#if !defined(CONFIG_EMU)
-+#define CONFIG_MMC
-+#ifdef CONFIG_MMC
-+#define CONFIG_CMD_MMC
-+#define CONFIG_FSL_ESDHC
-+#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
-+#define CONFIG_GENERIC_MMC
-+#define CONFIG_CMD_FAT
-+#define CONFIG_DOS_PARTITION
-+#endif
-+#endif /* CONFIG_EMU */
-+
-+/* SATA */
-+#if !defined(CONFIG_EMU)
-+#define CONFIG_LIBATA
-+#define CONFIG_SCSI_AHCI
-+#define CONFIG_SCSI_AHCI_PLAT
-+#define CONFIG_CMD_SCSI
-+#define CONFIG_CMD_FAT
-+#define CONFIG_CMD_EXT2
-+#define CONFIG_DOS_PARTITION
-+#define CONFIG_BOARD_LATE_INIT
-+
-+#define CONFIG_SYS_SATA AHCI_BASE_ADDR
-+
-+#define CONFIG_SYS_SCSI_MAX_SCSI_ID 1
-+#define CONFIG_SYS_SCSI_MAX_LUN 1
-+#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
-+ CONFIG_SYS_SCSI_MAX_LUN)
-+
-+#define CONFIG_PCI /* Enable PCI/PCIE */
-+#define CONFIG_PCIE1 /* PCIE controller 1 */
-+#define CONFIG_PCIE_LAYERSCAPE /* Use common FSL Layerscape PCIe code */
-+#define FSL_PCIE_COMPAT "fsl,ls1043a-pcie"
-+
-+#define CONFIG_SYS_PCI_64BIT
-+
-+#define CONFIG_SYS_PCIE_CFG0_PHYS_OFF 0x00000000
-+#define CONFIG_SYS_PCIE_CFG0_SIZE 0x00001000 /* 4k */
-+#define CONFIG_SYS_PCIE_CFG1_PHYS_OFF 0x00001000
-+#define CONFIG_SYS_PCIE_CFG1_SIZE 0x00001000 /* 4k */
-+
-+#define CONFIG_SYS_PCIE_IO_BUS 0x00000000
-+#define CONFIG_SYS_PCIE_IO_PHYS_OFF 0x00010000
-+#define CONFIG_SYS_PCIE_IO_SIZE 0x00010000 /* 64k */
-+
-+#define CONFIG_SYS_PCIE_MEM_BUS 0x08000000
-+#define CONFIG_SYS_PCIE_MEM_PHYS_OFF 0x04000000
-+#define CONFIG_SYS_PCIE_MEM_SIZE 0x80000000 /* 128M */
-+
-+#define CONFIG_NET_MULTI
-+#define CONFIG_PCI_PNP
-+#define CONFIG_E1000
-+#define CONFIG_PCI_SCAN_SHOW
-+#define CONFIG_CMD_PCI
-+#endif
-+
-+#define CONFIG_CONS_INDEX 1
-+#define CONFIG_SYS_NS16550_SERIAL
-+#define CONFIG_SYS_NS16550_REG_SIZE 1
-+#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
-+
-+#ifdef CONFIG_EMU
-+#define CONFIG_BAUDRATE 3000
-+#else
-+#define CONFIG_BAUDRATE 115200
-+#endif
-+#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
-+
-+/* Command line configuration */
-+#define CONFIG_CMD_CACHE
-+#define CONFIG_CMD_DHCP
-+#define CONFIG_CMD_ENV
-+#define CONFIG_CMD_GREPENV
-+#define CONFIG_CMD_MII
-+#define CONFIG_CMD_PING
-+#undef CONFIG_CMD_IMLS
-+
-+
-+#define CONFIG_ARCH_EARLY_INIT_R
-+
-+#define CONFIG_SYS_HZ 1000
-+
-+#define CONFIG_HWCONFIG
-+#define HWCONFIG_BUFFER_SIZE 128
-+
-+#define CONFIG_DISPLAY_CPUINFO
-+
-+/* Initial environment variables */
-+#define CONFIG_EXTRA_ENV_SETTINGS \
-+ "initrd_high=0xffffffff\0" \
-+ "verify=no\0" \
-+ "hwconfig=fsl_ddr:bank_intlv=auto\0" \
-+ "loadaddr=0x80100000\0" \
-+ "kernel_addr=0x100000\0" \
-+ "ramdisk_addr=0x800000\0" \
-+ "ramdisk_size=0x2000000\0" \
-+ "fdt_high=0xffffffffffffffff\0" \
-+ "initrd_high=0xffffffffffffffff\0" \
-+ "kernel_start=0xa00000\0" \
-+ "kernel_load=0xa0000000\0" \
-+ "kernel_size=0x2800000\0" \
-+ "console=ttyAMA0,38400n8\0"
-+
-+#ifdef CONFIG_EMU
-+#define CONFIG_BOOTARGS "console=ttyS2,115200 root=/dev/ram0 " \
-+ "earlycon=uart8250,mmio,0x21d0500,115200n8"
-+/* Kernel image should be pre-loaded to address kernel_load */
-+#define CONFIG_BOOTCOMMAND "bootm $kernel_load"
-+#else
-+#define CONFIG_BOOTARGS "console=ttyS0,115200 root=/dev/ram0 " \
-+ "earlycon=uart8250,mmio,0x21c0500"
-+#define CONFIG_BOOTCOMMAND "sf probe 0:0; sf read $kernel_load "\
-+ "$kernel_start $kernel_size && "\
-+ "bootm $kernel_load"
-+#endif
-+#define CONFIG_BOOTDELAY 10
-+
-+/* Monitor Command Prompt */
-+#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
-+#define CONFIG_SYS_PROMPT "=> "
-+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
-+ sizeof(CONFIG_SYS_PROMPT) + 16)
-+#define CONFIG_SYS_HUSH_PARSER
-+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
-+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot args buffer */
-+#define CONFIG_SYS_LONGHELP
-+#define CONFIG_CMDLINE_EDITING 1
-+#define CONFIG_AUTO_COMPLETE
-+#define CONFIG_SYS_MAXARGS 64 /* max command args */
-+
-+#define CONFIG_PANIC_HANG
-+#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
-+
-+/* Flat Device Tree Definitions */
-+#define CONFIG_OF_LIBFDT
-+#define CONFIG_OF_BOARD_SETUP
-+
-+/* new uImage format support */
-+#define CONFIG_FIT
-+#define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */
-+#define CONFIG_CMD_BOOTZ
-+#define CONFIG_CMDLINE_TAG
-+
-+#include <asm/fsl_secure_boot.h>
-+
-+#endif /* __LS1012A_COMMON_H */
-diff --git a/include/configs/ls1012aqds.h b/include/configs/ls1012aqds.h
-new file mode 100644
-index 0000000..6346d3e
---- /dev/null
-+++ b/include/configs/ls1012aqds.h
-@@ -0,0 +1,133 @@
-+/*
-+ * Copyright 2016 Freescale Semiconductor, Inc.
-+ *
-+ * SPDX-License-Identifier: GPL-2.0+
-+ */
-+
-+#ifndef __LS1012AQDS_H__
-+#define __LS1012AQDS_H__
-+
-+#include "ls1012a_common.h"
-+
-+
-+#define CONFIG_DIMM_SLOTS_PER_CTLR 1
-+#define CONFIG_CHIP_SELECTS_PER_CTRL 1
-+#define CONFIG_NR_DRAM_BANKS 2
-+
-+#ifdef CONFIG_SYS_DPAA_FMAN
-+#define CONFIG_FMAN_ENET
-+#define CONFIG_PHYLIB
-+#define CONFIG_PHY_VITESSE
-+#define CONFIG_PHY_REALTEK
-+#define RGMII_PHY1_ADDR 0x1
-+#define SGMII_CARD_PORT1_PHY_ADDR 0x1C
-+#define SGMII_CARD_PORT2_PHY_ADDR 0x1D
-+#define SGMII_CARD_PORT3_PHY_ADDR 0x1E
-+#define SGMII_CARD_PORT4_PHY_ADDR 0x1F
-+#endif
-+
-+#define CONFIG_QIXIS_I2C_ACCESS
-+
-+/*
-+ * I2C bus multiplexer
-+ */
-+#define I2C_MUX_PCA_ADDR_PRI 0x77
-+#define I2C_MUX_PCA_ADDR_SEC 0x76 /* Secondary multiplexer */
-+#define I2C_RETIMER_ADDR 0x18
-+#define I2C_MUX_CH_DEFAULT 0x8
-+#define I2C_MUX_CH_CH7301 0xC
-+#define I2C_MUX_CH5 0xD
-+#define I2C_MUX_CH7 0xF
-+
-+#define I2C_MUX_CH_VOL_MONITOR 0xa
-+
-+/*
-+* RTC configuration
-+*/
-+#define RTC
-+#define CONFIG_RTC_PCF8563 1
-+#define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* Channel 3*/
-+#define CONFIG_CMD_DATE
-+
-+/* EEPROM */
-+#define CONFIG_ID_EEPROM
-+#define CONFIG_CMD_EEPROM
-+#define CONFIG_SYS_I2C_EEPROM_NXID
-+#define CONFIG_SYS_EEPROM_BUS_NUM 0
-+#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
-+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
-+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
-+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
-+
-+
-+/* Voltage monitor on channel 2*/
-+#define I2C_VOL_MONITOR_ADDR 0x40
-+#define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2
-+#define I2C_VOL_MONITOR_BUS_V_OVF 0x1
-+#define I2C_VOL_MONITOR_BUS_V_SHIFT 3
-+
-+/* DSPI */
-+#define CONFIG_FSL_DSPI
-+#define CONFIG_FSL_DSPI1
-+#define CONFIG_DEFAULT_SPI_BUS 1
-+
-+#define CONFIG_CMD_SPI
-+#define MMAP_DSPI DSPI1_BASE_ADDR
-+
-+#define CONFIG_SYS_DSPI_CTAR0 1
-+
-+#define CONFIG_SYS_DSPI_CTAR1 (DSPI_CTAR_TRSZ(7) | DSPI_CTAR_PCSSCK_1CLK |\
-+ DSPI_CTAR_PASC(0) | DSPI_CTAR_PDT(0) | \
-+ DSPI_CTAR_CSSCK(2) | DSPI_CTAR_ASC(0) | \
-+ DSPI_CTAR_DT(0))
-+#define CONFIG_SPI_FLASH_SST /* cs1 */
-+
-+#define CONFIG_SYS_DSPI_CTAR2 (DSPI_CTAR_TRSZ(7) | DSPI_CTAR_PCSSCK_1CLK |\
-+ DSPI_CTAR_PASC(0) | DSPI_CTAR_PDT(0) | \
-+ DSPI_CTAR_CSSCK(0) | DSPI_CTAR_ASC(0) | \
-+ DSPI_CTAR_DT(0))
-+#define CONFIG_SPI_FLASH_STMICRO /* cs2 */
-+
-+#define CONFIG_SYS_DSPI_CTAR3 (DSPI_CTAR_TRSZ(7) | DSPI_CTAR_PCSSCK_1CLK |\
-+ DSPI_CTAR_PASC(0) | DSPI_CTAR_PDT(0) | \
-+ DSPI_CTAR_CSSCK(2) | DSPI_CTAR_ASC(0) | \
-+ DSPI_CTAR_DT(0))
-+#define CONFIG_SPI_FLASH_EON /* cs3 */
-+
-+#define CONFIG_SF_DEFAULT_SPEED 10000000
-+#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
-+#define CONFIG_SF_DEFAULT_BUS 1
-+#define CONFIG_SF_DEFAULT_CS 0
-+
-+/*
-+* USB
-+*/
-+/* EHCI Support - disbaled by default */
-+/*#define CONFIG_HAS_FSL_DR_USB*/
-+
-+#ifdef CONFIG_HAS_FSL_DR_USB
-+#define CONFIG_USB_EHCI
-+#define CONFIG_USB_EHCI_FSL
-+#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
-+#endif
-+
-+/*XHCI Support - enabled by default*/
-+#define CONFIG_HAS_FSL_XHCI_USB
-+
-+#ifdef CONFIG_HAS_FSL_XHCI_USB
-+#define CONFIG_USB_XHCI
-+#define CONFIG_USB_XHCI_FSL
-+#define CONFIG_USB_XHCI_DWC3
-+#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
-+#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2
-+#define CONFIG_CMD_USB
-+#define CONFIG_USB_STORAGE
-+#define CONFIG_CMD_EXT2
-+#endif
-+
-+#define CONFIG_CMD_MEMINFO
-+#define CONFIG_CMD_MEMTEST
-+#define CONFIG_SYS_MEMTEST_START 0x80000000
-+#define CONFIG_SYS_MEMTEST_END 0x9fffffff
-+
-+#endif /* __LS1012AQDS_H__ */
-diff --git a/include/fsl_mmdc.h b/include/fsl_mmdc.h
-index 3df822e..d47e625 100644
---- a/include/fsl_mmdc.h
-+++ b/include/fsl_mmdc.h
-@@ -25,29 +25,70 @@ struct mmdc_p_regs {
- u32 mdcfg3lp;
- u32 mdmr4;
- u32 mdasp;
-- u32 res3[239];
-+ u32 res2[239];
- u32 maarcr;
- u32 mapsr;
-- u32 res4[254];
-+ u32 maexidr0;
-+ u32 maexidr1;
-+ u32 madpcr0;
-+ u32 madpcr1;
-+ u32 madpsr0;
-+ u32 madpsr1;
-+ u32 madpsr2;
-+ u32 madpsr3;
-+ u32 madpsr4;
-+ u32 madpsr5;
-+ u32 masbs0;
-+ u32 masbs1;
-+ u32 res3[2];
-+ u32 magenp;
-+ u32 res4[239];
- u32 mpzqhwctrl;
-- u32 res5[2];
-+ u32 mpzqswctrl;
-+ u32 mpwlgcr;
- u32 mpwldectrl0;
- u32 mpwldectrl1;
-- u32 res6;
-+ u32 mpwldlst;
- u32 mpodtctrl;
- u32 mprddqby0dl;
- u32 mprddqby1dl;
- u32 mprddqby2dl;
- u32 mprddqby3dl;
-- u32 res7[4];
-+ u32 res5[4];
- u32 mpdgctrl0;
- u32 mpdgctrl1;
-- u32 res8;
-+ u32 mpdgdlst0;
- u32 mprddlctl;
-- u32 res9;
-+ u32 mprddlst;
- u32 mpwrdlctl;
-- u32 res10[25];
-+ u32 mpwrdlst;
-+ u32 mpsdctrl;
-+ u32 mpzqlp2ctl;
-+ u32 mprddlhwctl;
-+ u32 mpwrdlhwctl;
-+ u32 mprddlhwst0;
-+ u32 mprddlhwst1;
-+ u32 mpwrdlhwst0;
-+ u32 mpwrdlhwst1;
-+ u32 mpwlhwerr;
-+ u32 mpdghwst0;
-+ u32 mpdghwst1;
-+ u32 mpdghwst2;
-+ u32 mpdghwst3;
-+ u32 mppdcmpr1;
-+ u32 mppdcmpr2;
-+ u32 mpswdar0;
-+ u32 mpswdrdr0;
-+ u32 mpswdrdr1;
-+ u32 mpswdrdr2;
-+ u32 mpswdrdr3;
-+ u32 mpswdrdr4;
-+ u32 mpswdrdr5;
-+ u32 mpswdrdr6;
-+ u32 mpswdrdr7;
- u32 mpmur0;
-+ u32 mpwrcadl;
-+ u32 mpdccr;
- };
-
- #endif /* FSL_MMDC_H */
---
-1.7.9.5
-
diff --git a/package/boot/uboot-layerscape/patches/0015-armv8-ls1012a-Add-support-of-ls1012ardb-board.patch b/package/boot/uboot-layerscape/patches/0015-armv8-ls1012a-Add-support-of-ls1012ardb-board.patch
deleted file mode 100644
index 1c23602..0000000
--- a/package/boot/uboot-layerscape/patches/0015-armv8-ls1012a-Add-support-of-ls1012ardb-board.patch
+++ /dev/null
@@ -1,634 +0,0 @@
-From 4bb641f4d28053bd1ff4af73dc0a63be2151f851 Mon Sep 17 00:00:00 2001
-From: Prabhakar Kushwaha <prabhakar.kushwaha at nxp.com>
-Date: Mon, 25 Apr 2016 14:37:33 +0530
-Subject: [PATCH 15/93] armv8: ls1012a: Add support of ls1012ardb board
-
-QorIQ LS1012A Reference Design System (LS1012ARDB) is a high-performance
-development platform, with a complete debugging environment.
-The LS1012ARDB board supports the QorIQ LS1012A processor and is
-optimized to support the high-bandwidth DDR3L memory and
-a full complement of high-speed SerDes ports.
-
-Signed-off-by: Calvin Johnson <calvin.johnson at nxp.com>
-Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha at nxp.com>
----
- arch/arm/Kconfig | 10 ++
- arch/arm/dts/Makefile | 3 +-
- arch/arm/dts/fsl-ls1012a-rdb.dts | 16 +++
- arch/arm/dts/fsl-ls1012a-rdb.dtsi | 39 ++++++
- board/freescale/ls1012ardb/Kconfig | 15 +++
- board/freescale/ls1012ardb/MAINTAINERS | 6 +
- board/freescale/ls1012ardb/Makefile | 7 +
- board/freescale/ls1012ardb/README | 89 +++++++++++++
- board/freescale/ls1012ardb/ls1012ardb.c | 220 +++++++++++++++++++++++++++++++
- configs/ls1012ardb_qspi_defconfig | 10 ++
- include/configs/ls1012a_common.h | 3 +-
- include/configs/ls1012ardb.h | 61 +++++++++
- include/linux/usb/xhci-fsl.h | 2 +-
- 13 files changed, 477 insertions(+), 4 deletions(-)
- create mode 100644 arch/arm/dts/fsl-ls1012a-rdb.dts
- create mode 100644 arch/arm/dts/fsl-ls1012a-rdb.dtsi
- create mode 100644 board/freescale/ls1012ardb/Kconfig
- create mode 100644 board/freescale/ls1012ardb/MAINTAINERS
- create mode 100644 board/freescale/ls1012ardb/Makefile
- create mode 100644 board/freescale/ls1012ardb/README
- create mode 100644 board/freescale/ls1012ardb/ls1012ardb.c
- create mode 100644 configs/ls1012ardb_qspi_defconfig
- create mode 100644 include/configs/ls1012ardb.h
-
-diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
-index f5033db..5c20801 100644
---- a/arch/arm/Kconfig
-+++ b/arch/arm/Kconfig
-@@ -656,6 +656,15 @@ config TARGET_LS1012AQDS
- development platform that supports the QorIQ LS1012A
- Layerscape Architecture processor.
-
-+config TARGET_LS1012ARDB
-+ bool "Support ls1012ardb"
-+ select ARM64
-+ help
-+ Support for Freescale LS1012ARDB platform.
-+ The LS1012A Reference design board (RDB) is a high-performance
-+ development platform that supports the QorIQ LS1012A
-+ Layerscape Architecture processor.
-+
- config TARGET_LS1021AQDS
- bool "Support ls1021aqds"
- select CPU_V7
-@@ -802,6 +811,7 @@ source "board/freescale/ls1043aqds/Kconfig"
- source "board/freescale/ls1021atwr/Kconfig"
- source "board/freescale/ls1043ardb/Kconfig"
- source "board/freescale/ls1012aqds/Kconfig"
-+source "board/freescale/ls1012ardb/Kconfig"
- source "board/freescale/mx23evk/Kconfig"
- source "board/freescale/mx25pdk/Kconfig"
- source "board/freescale/mx28evk/Kconfig"
-diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
-index ed5eb38..9e8137b 100644
---- a/arch/arm/dts/Makefile
-+++ b/arch/arm/dts/Makefile
-@@ -95,7 +95,8 @@ dtb-$(CONFIG_FSL_LSCH3) += fsl-ls2080a-qds.dtb \
- dtb-$(CONFIG_FSL_LSCH2) += fsl-ls1043a-qds-duart.dtb \
- fsl-ls1043a-qds-lpuart.dtb \
- fsl-ls1043a-rdb.dtb \
-- fsl-ls1012a-qds.dtb
-+ fsl-ls1012a-qds.dtb \
-+ fsl-ls1012a-rdb.dtb
-
- dtb-$(CONFIG_MACH_SUN4I) += \
- sun4i-a10-a1000.dtb \
-diff --git a/arch/arm/dts/fsl-ls1012a-rdb.dts b/arch/arm/dts/fsl-ls1012a-rdb.dts
-new file mode 100644
-index 0000000..4ec9786
---- /dev/null
-+++ b/arch/arm/dts/fsl-ls1012a-rdb.dts
-@@ -0,0 +1,16 @@
-+/*
-+ * Device Tree file for Freescale Layerscape-1012A family SoC.
-+ *
-+ * Copyright (C) 2016, Freescale Semiconductor
-+ *
-+ * SPDX-License-Identifier: GPL-2.0+
-+ */
-+
-+/dts-v1/;
-+#include "fsl-ls1012a-rdb.dtsi"
-+
-+/ {
-+ chosen {
-+ stdout-path = &duart0;
-+ };
-+};
-diff --git a/arch/arm/dts/fsl-ls1012a-rdb.dtsi b/arch/arm/dts/fsl-ls1012a-rdb.dtsi
-new file mode 100644
-index 0000000..71aba78
---- /dev/null
-+++ b/arch/arm/dts/fsl-ls1012a-rdb.dtsi
-@@ -0,0 +1,39 @@
-+/*
-+ * Device Tree Include file for Freescale Layerscape-1012A family SoC.
-+ *
-+ * Copyright (C) 2016, Freescale Semiconductor
-+ *
-+ * This file is licensed under the terms of the GNU General Public
-+ * License version 2. This program is licensed "as is" without any
-+ * warranty of any kind, whether express or implied.
-+ */
-+
-+/include/ "fsl-ls1012a.dtsi"
-+
-+/ {
-+ model = "LS1012A RDB Board";
-+ aliases {
-+ spi0 = &qspi;
-+ };
-+};
-+
-+&qspi {
-+ bus-num = <0>;
-+ status = "okay";
-+
-+ qflash0: s25fl128s at 0 {
-+ #address-cells = <1>;
-+ #size-cells = <1>;
-+ compatible = "spi-flash";
-+ spi-max-frequency = <20000000>;
-+ reg = <0>;
-+ };
-+};
-+
-+&i2c0 {
-+ status = "okay";
-+};
-+
-+&duart0 {
-+ status = "okay";
-+};
-diff --git a/board/freescale/ls1012ardb/Kconfig b/board/freescale/ls1012ardb/Kconfig
-new file mode 100644
-index 0000000..3f67c28
---- /dev/null
-+++ b/board/freescale/ls1012ardb/Kconfig
-@@ -0,0 +1,15 @@
-+if TARGET_LS1012ARDB
-+
-+config SYS_BOARD
-+ default "ls1012ardb"
-+
-+config SYS_VENDOR
-+ default "freescale"
-+
-+config SYS_SOC
-+ default "fsl-layerscape"
-+
-+config SYS_CONFIG_NAME
-+ default "ls1012ardb"
-+
-+endif
-diff --git a/board/freescale/ls1012ardb/MAINTAINERS b/board/freescale/ls1012ardb/MAINTAINERS
-new file mode 100644
-index 0000000..757e810
---- /dev/null
-+++ b/board/freescale/ls1012ardb/MAINTAINERS
-@@ -0,0 +1,6 @@
-+LS1012ARDB BOARD
-+M:
-+S: Maintained
-+F: board/freescale/ls1012ardb/
-+F: include/configs/ls1012ardb.h
-+F: configs/ls1012ardb_defconfig
-diff --git a/board/freescale/ls1012ardb/Makefile b/board/freescale/ls1012ardb/Makefile
-new file mode 100644
-index 0000000..05fa9d9
---- /dev/null
-+++ b/board/freescale/ls1012ardb/Makefile
-@@ -0,0 +1,7 @@
-+#
-+# Copyright 2016 Freescale Semiconductor, Inc.
-+#
-+# SPDX-License-Identifier: GPL-2.0+
-+#
-+
-+obj-y += ls1012ardb.o
-diff --git a/board/freescale/ls1012ardb/README b/board/freescale/ls1012ardb/README
-new file mode 100644
-index 0000000..cda03f6
---- /dev/null
-+++ b/board/freescale/ls1012ardb/README
-@@ -0,0 +1,89 @@
-+Overview
-+--------
-+The LS1012ARDB power supplies (PS) provide all the voltages necessary
-+for the correct operation of the LS1012A processor, DDR3L, QSPI memory,
-+and other onboard peripherals.
-+
-+LS1012A SoC Overview
-+--------------------
-+The LS1012A features an advanced 64-bit ARM v8 Cortex-
-+A53 processor, with 32 KB of parity protected L1-I cache,
-+32 KB of ECC protected L1-D cache, as well as 256 KB of
-+ECC protected L2 cache.
-+
-+The LS1012A SoC includes the following function and features:
-+ - One 64-bit ARM v8 Cortex-A53 core with the following capabilities:
-+ - ARM v8 cryptography extensions
-+ - One 16-bit DDR3L SDRAM memory controller, Up to 1.0 GT/s, Supports
-+ 16-/8-bit operation (no ECC support)
-+ - ARM core-link CCI-400 cache coherent interconnect
-+ - Packet Forwarding Engine (PFE)
-+ - Cryptography acceleration (SEC)
-+ - Ethernet interfaces supported by PFE:
-+ - One Configurable x3 SerDes:
-+ Two Serdes PLLs supported for usage by any SerDes data lane
-+ Support for up to 6 GBaud operation
-+ - High-speed peripheral interfaces:
-+ - One PCI Express Gen2 controller, supporting x1 operation
-+ - One serial ATA (SATA Gen 3.0) controller
-+ - One USB 3.0/2.0 controller with integrated PHY
-+ - One USB 2.0 controller with ULPI interface. .
-+ - Additional peripheral interfaces:
-+ - One quad serial peripheral interface (QuadSPI) controller
-+ - One serial peripheral interface (SPI) controller
-+ - Two enhanced secure digital host controllers
-+ - Two I2C controllers
-+ - One 16550 compliant DUART (two UART interfaces)
-+ - Two general purpose IOs (GPIO)
-+ - Two FlexTimers
-+ - Five synchronous audio interfaces (SAI)
-+ - Pre-boot loader (PBL) provides pre-boot initialization and RCW loading
-+ - Single-source clocking solution enabling generation of core, platform,
-+ DDR, SerDes, and USB clocks from a single external crystal and internal
-+ crystaloscillator
-+ - Thermal monitor unit (TMU) with +/- 3C accuracy
-+ - Two WatchDog timers
-+ - ARM generic timer
-+ - QorIQ platform's trust architecture 2.1
-+
-+ LS1012ARDB board Overview
-+ -----------------------
-+ - SERDES Connections, 4 lanes supporting:
-+ - PCI Express - 3.0
-+ - SGMII, SGMII 2.5
-+ - SATA 3.0
-+ - DDR Controller
-+ - 6-bit, 1 GB DDR3L SDRAM memory, running at data rates up to 1 GT/s
-+ -QSPI: A dual 1:3 switch, NX3L4357GM,115 (U35) drives the QSPI chip-select
-+ signals to
-+ - QSPI NOR flash memory (2 virtual banks)
-+ - the QSPI emulator.s
-+ - USB 3.0
-+ - one high-speed USB 2.0/3.0 port.
-+ - Two enhanced secure digital host controllers:
-+ - SDHC1 controller can be connected to onboard SDHC connector
-+ - SDHC2 controller: Three dual 1:4 mux/demux devices,
-+ 74CBTLV3253DS (U30, U31, U33) drive the SDHC2 signals to eMMC,
-+ SDIO WiFi, SPI, and Ardiuno shield
-+ - 2 I2C controllers
-+ - One SATA onboard connectors
-+ - UART
-+ - The LS1012A processor consists of two UART controllers,
-+ out of which only UART1 is used on RDB.
-+ - ARM JTAG support
-+
-+Booting Options
-+---------------
-+a) QSPI Flash Emu Boot
-+b) QSPI Flash 1
-+c) QSPI Flash 2
-+
-+QSPI flash map
-+--------------
-+Images | Size |QSPI Flash Address
-+------------------------------------------
-+RCW + PBI | 1MB | 0x4000_0000
-+U-boot | 1MB | 0x4010_0000
-+U-boot Env | 1MB | 0x4020_0000
-+PPA FIT image | 2MB | 0x4050_0000
-+Linux ITB | ~53MB | 0x40A0_0000
-diff --git a/board/freescale/ls1012ardb/ls1012ardb.c b/board/freescale/ls1012ardb/ls1012ardb.c
-new file mode 100644
-index 0000000..4a7aaaa
---- /dev/null
-+++ b/board/freescale/ls1012ardb/ls1012ardb.c
-@@ -0,0 +1,220 @@
-+/*
-+ * Copyright 2016 Freescale Semiconductor, Inc.
-+ *
-+ * SPDX-License-Identifier: GPL-2.0+
-+ */
-+
-+#include <common.h>
-+#include <i2c.h>
-+#include <asm/io.h>
-+#include <asm/arch/clock.h>
-+#include <asm/arch/fsl_serdes.h>
-+#include <asm/arch/ppa.h>
-+#include <asm/arch/soc.h>
-+#include <hwconfig.h>
-+#include <ahci.h>
-+#include <mmc.h>
-+#include <scsi.h>
-+#include <fsl_csu.h>
-+#include <fsl_esdhc.h>
-+#include <environment.h>
-+#include <fsl_mmdc.h>
-+#include <netdev.h>
-+
-+DECLARE_GLOBAL_DATA_PTR;
-+
-+int checkboard(void)
-+{
-+ u8 in1;
-+
-+ puts("Board: LS1012ARDB ");
-+
-+ /* Initialize i2c early for Serial flash bank information */
-+ i2c_set_bus_num(0);
-+
-+ if (i2c_read(I2C_MUX_IO1_ADDR, 1, 1, &in1, 1) < 0) {
-+ printf("Error reading i2c boot information!\n");
-+ return 0; /* Don't want to hang() on this error */
-+ }
-+
-+ puts("Version");
-+ if ((in1 & (~__SW_REV_MASK)) == __SW_REV_A)
-+ puts(": RevA");
-+ else if ((in1 & (~__SW_REV_MASK)) == __SW_REV_B)
-+ puts(": RevB");
-+ else
-+ puts(": unknown");
-+
-+ printf(", boot from QSPI");
-+ if ((in1 & (~__SW_BOOT_MASK)) == __SW_BOOT_EMU)
-+ puts(": emu\n");
-+ else if ((in1 & (~__SW_BOOT_MASK)) == __SW_BOOT_BANK1)
-+ puts(": bank1\n");
-+ else if ((in1 & (~__SW_BOOT_MASK)) == __SW_BOOT_BANK2)
-+ puts(": bank2\n");
-+ else
-+ puts("unknown\n");
-+
-+ return 0;
-+}
-+
-+void mmdc_init(void)
-+{
-+ struct mmdc_p_regs *mmdc =
-+ (struct mmdc_p_regs *)CONFIG_SYS_FSL_DDR_ADDR;
-+
-+ /* Set MMDC_MDSCR[CON_REQ] */
-+ out_be32(&mmdc->mdscr, 0x00008000);
-+
-+ /* configure timing parms */
-+ out_be32(&mmdc->mdotc, 0x12554000);
-+ out_be32(&mmdc->mdcfg0, 0xbabf7954);
-+ out_be32(&mmdc->mdcfg1, 0xff328f64);
-+ out_be32(&mmdc->mdcfg2, 0x01ff00db);
-+
-+ /* other parms */
-+ out_be32(&mmdc->mdmisc, 0x00000680);
-+ out_be32(&mmdc->mpmur0, 0x00000800);
-+ out_be32(&mmdc->mdrwd, 0x00002000);
-+ out_be32(&mmdc->mpodtctrl, 0x0000022a);
-+
-+ /* out of reset delays */
-+ out_be32(&mmdc->mdor, 0x00bf1023);
-+
-+ /* physical parms */
-+ out_be32(&mmdc->mdctl, 0x05180000);
-+ out_be32(&mmdc->mdasp, 0x0000007f);
-+
-+ /* Enable MMDC */
-+ out_be32(&mmdc->mdctl, 0x85180000);
-+
-+ /* dram init sequence: update MRs */
-+ out_be32(&mmdc->mdscr, 0x00088032);
-+ out_be32(&mmdc->mdscr, 0x00008033);
-+ out_be32(&mmdc->mdscr, 0x00048031);
-+ out_be32(&mmdc->mdscr, 0x19308030);
-+
-+ /* dram init sequence: ZQCL */
-+ out_be32(&mmdc->mdscr, 0x04008040);
-+ out_be32(&mmdc->mpzqhwctrl, 0xa1390003);
-+
-+ mdelay(100);
-+
-+ /* Calibrations now: wr lvl */
-+ out_be32(&mmdc->mdscr, 0x00848031);
-+ out_be32(&mmdc->mdscr, 0x00008200);
-+ out_be32(&mmdc->mpwlgcr, 0x00000001);
-+
-+ mdelay(100);
-+
-+ out_be32(&mmdc->mdscr, 0x00048031);
-+ out_be32(&mmdc->mdscr, 0x00008000);
-+
-+ /* manual_refresh */
-+ out_be32(&mmdc->mdscr, 0x00008020);
-+
-+ mdelay(100);
-+
-+ /* Calibrations now: Read DQS gating calibration */
-+ out_be32(&mmdc->mdscr, 0x04008050);
-+ out_be32(&mmdc->mdscr, 0x00048033);
-+ out_be32(&mmdc->mppdcmpr2, 0x00000001);
-+ out_be32(&mmdc->mprddlctl, 0x40404040);
-+ out_be32(&mmdc->mpdgctrl0, 0x10000000);
-+
-+ mdelay(100);
-+
-+ out_be32(&mmdc->mdscr, 0x00008033);
-+
-+ /* manual_refresh */
-+ out_be32(&mmdc->mdscr, 0x00008020);
-+
-+ mdelay(100);
-+
-+ /* Calibrations now: Read calibration */
-+ out_be32(&mmdc->mdscr, 0x04008050);
-+ out_be32(&mmdc->mdscr, 0x00048033);
-+ out_be32(&mmdc->mppdcmpr2, 0x00000001);
-+ out_be32(&mmdc->mprddlhwctl, 0x00000010);
-+
-+ mdelay(400);
-+
-+ out_be32(&mmdc->mdscr, 0x00008033);
-+
-+ /* manual_refresh */
-+ out_be32(&mmdc->mdscr, 0x00008020);
-+
-+ mdelay(100);
-+
-+ /* PD, SR */
-+ out_be32(&mmdc->mdpdc, 0x00030035);
-+ out_be32(&mmdc->mapsr, 0x00001067);
-+
-+ /* refresh scheme */
-+ out_be32(&mmdc->mdref, 0x103e8000);
-+
-+ mdelay(400);
-+
-+ /* disable CON_REQ */
-+ out_be32(&mmdc->mdscr, 0x0);
-+
-+ mdelay(50);
-+}
-+
-+int dram_init(void)
-+{
-+ mmdc_init();
-+
-+ gd->ram_size = 0x40000000;
-+
-+ return 0;
-+}
-+
-+int board_eth_init(bd_t *bis)
-+{
-+ return pci_eth_init(bis);
-+}
-+
-+int board_early_init_f(void)
-+{
-+ fsl_lsch2_early_init_f();
-+
-+ return 0;
-+}
-+
-+int board_init(void)
-+{
-+ struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
-+ /*
-+ * Set CCI-400 control override register to enable barrier
-+ * transaction
-+ */
-+ out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER);
-+
-+#ifdef CONFIG_ENV_IS_NOWHERE
-+ gd->env_addr = (ulong)&default_environment[0];
-+#endif
-+
-+#ifdef CONFIG_LAYERSCAPE_NS_ACCESS
-+ enable_layerscape_ns_access();
-+#endif
-+
-+ return 0;
-+}
-+
-+int ft_board_setup(void *blob, bd_t *bd)
-+{
-+ u64 base[CONFIG_NR_DRAM_BANKS];
-+ u64 size[CONFIG_NR_DRAM_BANKS];
-+
-+ /* fixup DT for the two DDR banks */
-+ base[0] = gd->bd->bi_dram[0].start;
-+ size[0] = gd->bd->bi_dram[0].size;
-+ base[1] = gd->bd->bi_dram[1].start;
-+ size[1] = gd->bd->bi_dram[1].size;
-+
-+ fdt_fixup_memory_banks(blob, base, size, 2);
-+ ft_cpu_setup(blob, bd);
-+
-+ return 0;
-+}
-diff --git a/configs/ls1012ardb_qspi_defconfig b/configs/ls1012ardb_qspi_defconfig
-new file mode 100644
-index 0000000..f819038
---- /dev/null
-+++ b/configs/ls1012ardb_qspi_defconfig
-@@ -0,0 +1,10 @@
-+CONFIG_ARM=y
-+CONFIG_TARGET_LS1012ARDB=y
-+CONFIG_SYS_EXTRA_OPTIONS="QSPI_BOOT"
-+# CONFIG_CMD_IMLS is not set
-+CONFIG_SYS_NS16550=y
-+CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1012a-rdb"
-+CONFIG_OF_CONTROL=y
-+CONFIG_DM=y
-+CONFIG_SPI_FLASH=y
-+CONFIG_DM_SPI=y
-diff --git a/include/configs/ls1012a_common.h b/include/configs/ls1012a_common.h
-index 9ed04f9..3fd360a 100644
---- a/include/configs/ls1012a_common.h
-+++ b/include/configs/ls1012a_common.h
-@@ -12,7 +12,7 @@
- #define CONFIG_LS1012A
- #define CONFIG_GICV2
-
--#define CONFIG_SYS_HAS_SERDES
-+#define CONFIG_SYS_HAS_SERDES
-
- #include <asm/arch/config.h>
- #define CONFIG_SYS_NO_FLASH
-@@ -56,7 +56,6 @@
- #define CONFIG_ENV_SPI_MODE 0x03
- #define CONFIG_CMD_SF
- #define CONFIG_SPI_FLASH_SPANSION
--#define CONFIG_SPI_FLASH_ATMEL
- #define CONFIG_FSL_SPI_INTERFACE
- #define CONFIG_SF_DATAFLASH
-
-diff --git a/include/configs/ls1012ardb.h b/include/configs/ls1012ardb.h
-new file mode 100644
-index 0000000..9ff5935
---- /dev/null
-+++ b/include/configs/ls1012ardb.h
-@@ -0,0 +1,61 @@
-+/*
-+ * Copyright 2016 Freescale Semiconductor, Inc.
-+ *
-+ * SPDX-License-Identifier: GPL-2.0+
-+ */
-+
-+#ifndef __LS1012ARDB_H__
-+#define __LS1012ARDB_H__
-+
-+#include "ls1012a_common.h"
-+
-+
-+#define CONFIG_DIMM_SLOTS_PER_CTLR 1
-+#define CONFIG_CHIP_SELECTS_PER_CTRL 1
-+#define CONFIG_NR_DRAM_BANKS 2
-+
-+#define CONFIG_CMD_MEMINFO
-+#define CONFIG_CMD_MEMTEST
-+#define CONFIG_SYS_MEMTEST_START 0x80000000
-+#define CONFIG_SYS_MEMTEST_END 0x9fffffff
-+
-+#define CONFIG_PHYLIB
-+#define CONFIG_PHY_REALTEK
-+#define SGMII_PHY1_ADDR 0x0
-+#define RGMII_PHY2_ADDR 0x1
-+
-+/*
-+* USB
-+*/
-+#define CONFIG_HAS_FSL_XHCI_USB
-+
-+#ifdef CONFIG_HAS_FSL_XHCI_USB
-+#define CONFIG_USB_XHCI
-+#define CONFIG_USB_XHCI_FSL
-+#define CONFIG_USB_XHCI_DWC3
-+#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
-+#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2
-+#define CONFIG_CMD_USB
-+#define CONFIG_USB_STORAGE
-+#define CONFIG_CMD_EXT2
-+#endif
-+
-+/*
-+ * I2C IO expander
-+ */
-+
-+#define I2C_MUX_IO1_ADDR 0x24
-+#define __SW_BOOT_MASK 0xFC
-+#define __SW_BOOT_EMU 0x10
-+#define __SW_BOOT_BANK1 0x00
-+#define __SW_BOOT_BANK2 0x01
-+#define __SW_REV_MASK 0x07
-+#define __SW_REV_A 0xF8
-+#define __SW_REV_B 0xF0
-+
-+#define CONFIG_CMD_MEMINFO
-+#define CONFIG_CMD_MEMTEST
-+#define CONFIG_SYS_MEMTEST_START 0x80000000
-+#define CONFIG_SYS_MEMTEST_END 0x9fffffff
-+
-+#endif /* __LS1012ARDB_H__ */
-diff --git a/include/linux/usb/xhci-fsl.h b/include/linux/usb/xhci-fsl.h
-index 72a5d5b..7ab88c3 100644
---- a/include/linux/usb/xhci-fsl.h
-+++ b/include/linux/usb/xhci-fsl.h
-@@ -62,7 +62,7 @@ struct fsl_xhci {
- #define CONFIG_SYS_FSL_XHCI_USB1_ADDR CONFIG_SYS_LS2080A_XHCI_USB1_ADDR
- #define CONFIG_SYS_FSL_XHCI_USB2_ADDR CONFIG_SYS_LS2080A_XHCI_USB2_ADDR
- #define CONFIG_SYS_FSL_XHCI_USB3_ADDR 0
--#elif defined(CONFIG_LS1043A)
-+#elif defined(CONFIG_LS1043A) || defined(CONFIG_LS1012A)
- #define CONFIG_SYS_FSL_XHCI_USB1_ADDR CONFIG_SYS_LS1043A_XHCI_USB1_ADDR
- #define CONFIG_SYS_FSL_XHCI_USB2_ADDR CONFIG_SYS_LS1043A_XHCI_USB2_ADDR
- #define CONFIG_SYS_FSL_XHCI_USB3_ADDR CONFIG_SYS_LS1043A_XHCI_USB3_ADDR
---
-1.7.9.5
-
diff --git a/package/boot/uboot-layerscape/patches/0016-ARM-asm-types-Introduce-DMA_ADDR_T_64BIT.patch b/package/boot/uboot-layerscape/patches/0016-ARM-asm-types-Introduce-DMA_ADDR_T_64BIT.patch
deleted file mode 100644
index 7f39efc..0000000
--- a/package/boot/uboot-layerscape/patches/0016-ARM-asm-types-Introduce-DMA_ADDR_T_64BIT.patch
+++ /dev/null
@@ -1,80 +0,0 @@
-From 4aa3d79020aeca3780ea113a495d18662d593761 Mon Sep 17 00:00:00 2001
-From: Lokesh Vutla <lokeshvutla at ti.com>
-Date: Thu, 24 Mar 2016 16:02:00 +0530
-Subject: [PATCH 16/93] ARM: asm: types: Introduce DMA_ADDR_T_64BIT
-
-dma_addr_t holds any valid DMA address. If the DMA API only uses 32-bit
-addresses, dma_addr_t need only be 32 bits wide. Bus addresses, e.g., PCI BARs,
-may be wider than 32 bits, but drivers do memory-mapped I/O to ioremapped
-kernel virtual addresses, so they don't care about the size of the actual
-bus addresses.
-Also 32 bit ARM systems with LPAE enabled can use 64bit address space, but
-DMA still use 32bit address like in case of DRA7 and Keystone platforms.
-
-This is inspired from the Linux kernel types implementation[1]
-
-[1] https://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/tree/include/linux/types.h#n142
-
-Acked-by: Lukasz Majewski <l.majewski at samsung.com>
-Signed-off-by: Lokesh Vutla <lokeshvutla at ti.com>
-Reviewed-by: Tom Rini <trini at konsulko.com>
-Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha at nxp.com>
----
- arch/arm/Kconfig | 4 ++++
- arch/arm/include/asm/types.h | 17 +++++++++++++++--
- 2 files changed, 19 insertions(+), 2 deletions(-)
-
-diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
-index 5c20801..b536684 100644
---- a/arch/arm/Kconfig
-+++ b/arch/arm/Kconfig
-@@ -7,6 +7,10 @@ config SYS_ARCH
- config ARM64
- bool
-
-+config DMA_ADDR_T_64BIT
-+ bool
-+ default y if ARM64
-+
- config HAS_VBAR
- bool
-
-diff --git a/arch/arm/include/asm/types.h b/arch/arm/include/asm/types.h
-index 388058e..d108915 100644
---- a/arch/arm/include/asm/types.h
-+++ b/arch/arm/include/asm/types.h
-@@ -46,16 +46,29 @@ typedef unsigned long long u64;
- #endif /* CONFIG_ARM64 */
-
- #ifdef CONFIG_PHYS_64BIT
--typedef unsigned long long dma_addr_t;
- typedef unsigned long long phys_addr_t;
- typedef unsigned long long phys_size_t;
- #else
- /* DMA addresses are 32-bits wide */
--typedef u32 dma_addr_t;
- typedef unsigned long phys_addr_t;
- typedef unsigned long phys_size_t;
- #endif
-
-+/*
-+ * A dma_addr_t can hold any valid DMA address, i.e., any address returned
-+ * by the DMA API.
-+ *
-+ * If the DMA API only uses 32-bit addresses, dma_addr_t need only be 32
-+ * bits wide. Bus addresses, e.g., PCI BARs, may be wider than 32 bits,
-+ * but drivers do memory-mapped I/O to ioremapped kernel virtual addresses,
-+ * so they don't care about the size of the actual bus addresses.
-+ */
-+#ifdef CONFIG_DMA_ADDR_T_64BIT
-+typedef unsigned long long dma_addr_t;
-+#else
-+typedef u32 dma_addr_t;
-+#endif
-+
- #endif /* __KERNEL__ */
-
- typedef unsigned long resource_size_t;
---
-1.7.9.5
-
diff --git a/package/boot/uboot-layerscape/patches/0017-armv8-fsl-layerscape-add-dwc3-gadget-driver-support.patch b/package/boot/uboot-layerscape/patches/0017-armv8-fsl-layerscape-add-dwc3-gadget-driver-support.patch
deleted file mode 100644
index 6095082..0000000
--- a/package/boot/uboot-layerscape/patches/0017-armv8-fsl-layerscape-add-dwc3-gadget-driver-support.patch
+++ /dev/null
@@ -1,465 +0,0 @@
-From f160c56c71c59d2d865142fdeb3040e9cc4b6a77 Mon Sep 17 00:00:00 2001
-From: Prabhakar Kushwaha <prabhakar.kushwaha at nxp.com>
-Date: Mon, 25 Apr 2016 17:14:25 +0530
-Subject: [PATCH 17/93] armv8/fsl-layerscape: add dwc3 gadget driver support
-
-Implements the dwc3 gadget driver support for LS1043
-and LS1012 platform.
-
-NOTE: Do not upstream this patch.It needs rework for open source
-submission.
-
-Signed-off-by: Rajat Srivastava <rajat.srivastava at nxp.com>
-Signed-off-by: Rajesh Bhagat <rajesh.bhagat at nxp.com>
-Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha at nxp.com>
----
- arch/arm/cpu/armv8/fsl-layerscape/soc.c | 98 +++++++++++++++++++-
- .../include/asm/arch-fsl-layerscape/immap_lsch2.h | 6 ++
- .../include/asm/arch-fsl-layerscape/sys_proto.h | 10 ++
- common/cmd_usb_mass_storage.c | 2 +-
- drivers/usb/dwc3/core.c | 12 +++
- drivers/usb/dwc3/ep0.c | 10 +-
- drivers/usb/dwc3/gadget.c | 11 ++-
- drivers/usb/dwc3/io.h | 8 +-
- drivers/usb/gadget/f_mass_storage.c | 10 +-
- include/configs/ls1012aqds.h | 15 +++
- include/configs/ls1012ardb.h | 15 +++
- include/configs/ls1043aqds.h | 15 +++
- 12 files changed, 197 insertions(+), 15 deletions(-)
- create mode 100644 arch/arm/include/asm/arch-fsl-layerscape/sys_proto.h
-
-diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
-index ec561a7..0a170eb 100644
---- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
-+++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
-@@ -19,6 +19,10 @@
- #ifdef CONFIG_CHAIN_OF_TRUST
- #include <fsl_validate.h>
- #endif
-+#include <usb.h>
-+#include <dwc3-uboot.h>
-+#include <linux/usb/xhci-fsl.h>
-+
-
- DECLARE_GLOBAL_DATA_PTR;
-
-@@ -406,9 +410,19 @@ void fsl_lsch2_early_init_f(void)
- #if defined(CONFIG_FSL_QSPI) && !defined(CONFIG_QSPI_BOOT)
- out_be32(&scfg->qspi_cfg, SCFG_QSPI_CLKSEL);
- #endif
-- /* Make SEC reads and writes snoopable */
-+
-+#if defined(CONFIG_LS1043A)
-+ /* Make SEC and USB reads and writes snoopable */
- setbits_be32(&scfg->snpcnfgcr, SCFG_SNPCNFGCR_SECRDSNP |
-- SCFG_SNPCNFGCR_SECWRSNP);
-+ SCFG_SNPCNFGCR_SECWRSNP | SCFG_SNPCNFGCR_USB1RDSNP |
-+ SCFG_SNPCNFGCR_USB1WRSNP | SCFG_SNPCNFGCR_USB2RDSNP |
-+ SCFG_SNPCNFGCR_USB2WRSNP | SCFG_SNPCNFGCR_USB3RDSNP |
-+ SCFG_SNPCNFGCR_USB3WRSNP);
-+#elif defined(CONFIG_LS1012A)
-+ /* Make SEC and reads and writes snoopable */
-+ setbits_be32(&scfg->snpcnfgcr, SCFG_SNPCNFGCR_SECRDSNP | SCFG_SNPCNFGCR_SECWRSNP |
-+ SCFG_SNPCNFGCR_USB1RDSNP | SCFG_SNPCNFGCR_USB1WRSNP);
-+#endif
-
- /*
- * Enable snoop requests and DVM message requests for
-@@ -428,6 +442,86 @@ void fsl_lsch2_early_init_f(void)
- }
- #endif
-
-+#ifdef CONFIG_USB_DWC3
-+
-+#if defined(CONFIG_LS1043A) || defined(CONFIG_LS1012A)
-+static struct dwc3_device dwc3_device_data0 = {
-+ .maximum_speed = USB_SPEED_HIGH,
-+ .base = CONFIG_SYS_FSL_XHCI_USB1_ADDR,
-+ .dr_mode = USB_DR_MODE_PERIPHERAL,
-+ .index = 0,
-+};
-+
-+#if defined(CONFIG_LS1043A)
-+static struct dwc3_device dwc3_device_data1 = {
-+ .maximum_speed = USB_SPEED_HIGH,
-+ .base = CONFIG_SYS_FSL_XHCI_USB2_ADDR,
-+ .dr_mode = USB_DR_MODE_PERIPHERAL,
-+ .index = 1,
-+};
-+
-+static struct dwc3_device dwc3_device_data2 = {
-+ .maximum_speed = USB_SPEED_HIGH,
-+ .base = CONFIG_SYS_FSL_XHCI_USB3_ADDR,
-+ .dr_mode = USB_DR_MODE_PERIPHERAL,
-+ .index = 2,
-+};
-+#endif
-+
-+int usb_gadget_handle_interrupts(int index)
-+{
-+ dwc3_uboot_handle_interrupt(index);
-+ return 0;
-+}
-+#endif
-+
-+int board_usb_init(int index, enum usb_init_type init)
-+{
-+ switch (init) {
-+ case USB_INIT_DEVICE:
-+ switch (index) {
-+#if defined(CONFIG_LS1043A) || defined(CONFIG_LS1012A)
-+ case 0:
-+ dwc3_uboot_init(&dwc3_device_data0);
-+ break;
-+
-+#if defined(CONFIG_LS1043A)
-+ case 1:
-+ dwc3_uboot_init(&dwc3_device_data1);
-+ break;
-+ case 2:
-+ dwc3_uboot_init(&dwc3_device_data2);
-+ break;
-+#endif
-+#endif
-+ default:
-+ printf("Invalid Controller Index\n");
-+ return -1;
-+ }
-+ break;
-+ default:
-+ break;
-+ }
-+ return 0;
-+}
-+
-+int board_usb_cleanup(int index, enum usb_init_type init)
-+{
-+ switch (init) {
-+ case USB_INIT_DEVICE:
-+#if defined(CONFIG_LS1043A) || defined(CONFIG_LS1012A)
-+ dwc3_uboot_exit(index);
-+#endif
-+ break;
-+ default:
-+ break;
-+ }
-+ return 0;
-+}
-+#endif
-+
-+
-+
- #ifdef CONFIG_BOARD_LATE_INIT
- int board_late_init(void)
- {
-diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
-index 5b026f8..414a222 100644
---- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
-+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
-@@ -355,6 +355,12 @@ struct ccsr_gur {
-
- #define SCFG_SNPCNFGCR_SECRDSNP 0x80000000
- #define SCFG_SNPCNFGCR_SECWRSNP 0x40000000
-+#define SCFG_SNPCNFGCR_USB1RDSNP 0x00200000
-+#define SCFG_SNPCNFGCR_USB1WRSNP 0x00100000
-+#define SCFG_SNPCNFGCR_USB2RDSNP 0x00008000
-+#define SCFG_SNPCNFGCR_USB2WRSNP 0x00010000
-+#define SCFG_SNPCNFGCR_USB3RDSNP 0x00002000
-+#define SCFG_SNPCNFGCR_USB3WRSNP 0x00004000
-
- /* Supplemental Configuration Unit */
- struct ccsr_scfg {
-diff --git a/arch/arm/include/asm/arch-fsl-layerscape/sys_proto.h b/arch/arm/include/asm/arch-fsl-layerscape/sys_proto.h
-new file mode 100644
-index 0000000..1e31d3d
---- /dev/null
-+++ b/arch/arm/include/asm/arch-fsl-layerscape/sys_proto.h
-@@ -0,0 +1,10 @@
-+/*
-+ * Copyright 2015 Freescale Semiconductor
-+ *
-+ * SPDX-License-Identifier: GPL-2.0+
-+ */
-+
-+#ifndef _ASM_ARMV8_FSL_LAYERSCAPE_SYS_PROTO_H_
-+#define _ASM_ARMV8_FSL_LAYERSCAPE_SYS_PROTO_H_
-+
-+#endif /* _ASM_ARMV8_FSL_LAYERSCAPE_SYS_PROTO_H_ */
-diff --git a/common/cmd_usb_mass_storage.c b/common/cmd_usb_mass_storage.c
-index 0407389..7d507b5 100644
---- a/common/cmd_usb_mass_storage.c
-+++ b/common/cmd_usb_mass_storage.c
-@@ -140,7 +140,7 @@ int do_usb_mass_storage(cmd_tbl_t *cmdtp, int flag,
- while (1) {
- usb_gadget_handle_interrupts(controller_index);
-
-- rc = fsg_main_thread(NULL);
-+ rc = fsg_main_thread(&controller_index);
- if (rc) {
- /* Check I/O error */
- if (rc == -EIO)
-diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
-index 85cc96a..b8e4066 100644
---- a/drivers/usb/dwc3/core.c
-+++ b/drivers/usb/dwc3/core.c
-@@ -690,6 +690,18 @@ int dwc3_uboot_init(struct dwc3_device *dwc3_dev)
- return -ENOMEM;
- }
-
-+#if defined(CONFIG_LS1043A) || defined(CONFIG_LS1012A)
-+ /* Change burst beat and outstanding pipelined transfers requests */
-+ dwc3_writel(dwc->regs, DWC3_GSBUSCFG0,
-+ (dwc3_readl(dwc->regs, DWC3_GSBUSCFG0) & ~0xff) | 0xf);
-+ dwc3_writel(dwc->regs, DWC3_GSBUSCFG1,
-+ dwc3_readl(dwc->regs, DWC3_GSBUSCFG1) | 0xf00);
-+
-+ /* Enable snooping */
-+ dwc3_writel(dwc->regs, DWC3_GSBUSCFG0,
-+ dwc3_readl(dwc->regs, DWC3_GSBUSCFG0) | 0x22220000);
-+#endif
-+
- if (IS_ENABLED(CONFIG_USB_DWC3_HOST))
- dwc->dr_mode = USB_DR_MODE_HOST;
- else if (IS_ENABLED(CONFIG_USB_DWC3_GADGET))
-diff --git a/drivers/usb/dwc3/ep0.c b/drivers/usb/dwc3/ep0.c
-index 12b133f..e61d980 100644
---- a/drivers/usb/dwc3/ep0.c
-+++ b/drivers/usb/dwc3/ep0.c
-@@ -81,8 +81,8 @@ static int dwc3_ep0_start_trans(struct dwc3 *dwc, u8 epnum, dma_addr_t buf_dma,
- trb->ctrl |= (DWC3_TRB_CTRL_IOC
- | DWC3_TRB_CTRL_LST);
-
-- dwc3_flush_cache((long)buf_dma, len);
-- dwc3_flush_cache((long)trb, sizeof(*trb));
-+ dwc3_flush_cache((uintptr_t)buf_dma, len);
-+ dwc3_flush_cache((uintptr_t)trb, sizeof(*trb));
-
- if (chain)
- return 0;
-@@ -790,7 +790,7 @@ static void dwc3_ep0_complete_data(struct dwc3 *dwc,
- if (!r)
- return;
-
-- dwc3_flush_cache((long)trb, sizeof(*trb));
-+ dwc3_flush_cache((uintptr_t)trb, sizeof(*trb));
-
- status = DWC3_TRB_SIZE_TRBSTS(trb->size);
- if (status == DWC3_TRBSTS_SETUP_PENDING) {
-@@ -821,7 +821,7 @@ static void dwc3_ep0_complete_data(struct dwc3 *dwc,
- ur->actual += transferred;
-
- trb++;
-- dwc3_flush_cache((long)trb, sizeof(*trb));
-+ dwc3_flush_cache((uintptr_t)trb, sizeof(*trb));
- length = trb->size & DWC3_TRB_SIZE_MASK;
-
- ep0->free_slot = 0;
-@@ -831,7 +831,7 @@ static void dwc3_ep0_complete_data(struct dwc3 *dwc,
- maxp);
- transferred = min_t(u32, ur->length - transferred,
- transfer_size - length);
-- dwc3_flush_cache((long)dwc->ep0_bounce, DWC3_EP0_BOUNCE_SIZE);
-+ dwc3_flush_cache((uintptr_t)dwc->ep0_bounce, DWC3_EP0_BOUNCE_SIZE);
- memcpy(buf, dwc->ep0_bounce, transferred);
- } else {
- transferred = ur->length - length;
-diff --git a/drivers/usb/dwc3/gadget.c b/drivers/usb/dwc3/gadget.c
-index 8ff949d..649f1a4 100644
---- a/drivers/usb/dwc3/gadget.c
-+++ b/drivers/usb/dwc3/gadget.c
-@@ -244,7 +244,7 @@ void dwc3_gadget_giveback(struct dwc3_ep *dep, struct dwc3_request *req,
-
- list_del(&req->list);
- req->trb = NULL;
-- dwc3_flush_cache((long)req->request.dma, req->request.length);
-+ dwc3_flush_cache((uintptr_t)req->request.dma, req->request.length);
-
- if (req->request.status == -EINPROGRESS)
- req->request.status = status;
-@@ -771,8 +771,8 @@ static void dwc3_prepare_one_trb(struct dwc3_ep *dep,
-
- trb->ctrl |= DWC3_TRB_CTRL_HWO;
-
-- dwc3_flush_cache((long)dma, length);
-- dwc3_flush_cache((long)trb, sizeof(*trb));
-+ dwc3_flush_cache((uintptr_t)dma, length);
-+ dwc3_flush_cache((uintptr_t)trb, sizeof(*trb));
- }
-
- /*
-@@ -1769,7 +1769,7 @@ static int dwc3_cleanup_done_reqs(struct dwc3 *dwc, struct dwc3_ep *dep,
- slot %= DWC3_TRB_NUM;
- trb = &dep->trb_pool[slot];
-
-- dwc3_flush_cache((long)trb, sizeof(*trb));
-+ dwc3_flush_cache((uintptr_t)trb, sizeof(*trb));
- __dwc3_cleanup_done_trbs(dwc, dep, req, trb, event, status);
- dwc3_gadget_giveback(dep, req, status);
-
-@@ -2447,6 +2447,7 @@ static irqreturn_t dwc3_process_event_buf(struct dwc3 *dwc, u32 buf)
- int left;
- u32 reg;
-
-+
- evt = dwc->ev_buffs[buf];
- left = evt->count;
-
-@@ -2670,7 +2671,7 @@ void dwc3_gadget_uboot_handle_interrupt(struct dwc3 *dwc)
-
- for (i = 0; i < dwc->num_event_buffers; i++) {
- evt = dwc->ev_buffs[i];
-- dwc3_flush_cache((long)evt->buf, evt->length);
-+ dwc3_flush_cache((uintptr_t)evt->buf, evt->length);
- }
-
- dwc3_thread_interrupt(0, dwc);
-diff --git a/drivers/usb/dwc3/io.h b/drivers/usb/dwc3/io.h
-index 0d9fa22..cab5122 100644
---- a/drivers/usb/dwc3/io.h
-+++ b/drivers/usb/dwc3/io.h
-@@ -48,8 +48,14 @@ static inline void dwc3_writel(void __iomem *base, u32 offset, u32 value)
- writel(value, base + offs);
- }
-
--static inline void dwc3_flush_cache(int addr, int length)
-+static inline void dwc3_flush_cache(uintptr_t addr, int length)
- {
- flush_dcache_range(addr, addr + ROUND(length, CACHELINE_SIZE));
- }
-+
-+static inline void dwc3_inval_cache(uintptr_t addr, int length)
-+{
-+ invalidate_dcache_range(addr, addr + ROUND(length, CACHELINE_SIZE));
-+}
-+
- #endif /* __DRIVERS_USB_DWC3_IO_H */
-diff --git a/drivers/usb/gadget/f_mass_storage.c b/drivers/usb/gadget/f_mass_storage.c
-index ec1f23a..ec0229f 100644
---- a/drivers/usb/gadget/f_mass_storage.c
-+++ b/drivers/usb/gadget/f_mass_storage.c
-@@ -362,6 +362,7 @@ struct fsg_common {
- char inquiry_string[8 + 16 + 4 + 1];
-
- struct kref ref;
-+ unsigned int controller_index;
- };
-
- struct fsg_config {
-@@ -690,7 +691,7 @@ static int sleep_thread(struct fsg_common *common)
- k = 0;
- }
-
-- usb_gadget_handle_interrupts(0);
-+ usb_gadget_handle_interrupts(common->controller_index);
- }
- common->thread_wakeup_needed = 0;
- return rc;
-@@ -2405,6 +2406,11 @@ int fsg_main_thread(void *common_)
- {
- int ret;
- struct fsg_common *common = the_fsg_common;
-+
-+ /* update the controller_index */
-+ if (common_)
-+ common->controller_index = *(unsigned int *)common_;
-+
- /* The main loop */
- do {
- if (exception_in_progress(common)) {
-@@ -2475,6 +2481,7 @@ static struct fsg_common *fsg_common_init(struct fsg_common *common,
-
- common->ops = NULL;
- common->private_data = NULL;
-+ common->controller_index = 0;
-
- common->gadget = gadget;
- common->ep0 = gadget->ep0;
-@@ -2769,6 +2776,7 @@ int fsg_add(struct usb_configuration *c)
-
- fsg_common->ops = NULL;
- fsg_common->private_data = NULL;
-+ fsg_common->controller_index = 0;
-
- the_fsg_common = fsg_common;
-
-diff --git a/include/configs/ls1012aqds.h b/include/configs/ls1012aqds.h
-index 6346d3e..fdada18 100644
---- a/include/configs/ls1012aqds.h
-+++ b/include/configs/ls1012aqds.h
-@@ -123,6 +123,21 @@
- #define CONFIG_CMD_USB
- #define CONFIG_USB_STORAGE
- #define CONFIG_CMD_EXT2
-+
-+#define CONFIG_USB_DWC3
-+#define CONFIG_USB_DWC3_GADGET
-+
-+#define CONFIG_USB_GADGET
-+#define CONFIG_USB_FUNCTION_MASS_STORAGE
-+#define CONFIG_USB_GADGET_DOWNLOAD
-+#define CONFIG_USB_GADGET_VBUS_DRAW 2
-+#define CONFIG_G_DNL_MANUFACTURER "NXP Semiconductor"
-+#define CONFIG_G_DNL_VENDOR_NUM 0x1234
-+#define CONFIG_G_DNL_PRODUCT_NUM 0x1234
-+#define CONFIG_USB_GADGET_DUALSPEED
-+
-+/* USB Gadget ums command */
-+#define CONFIG_CMD_USB_MASS_STORAGE
- #endif
-
- #define CONFIG_CMD_MEMINFO
-diff --git a/include/configs/ls1012ardb.h b/include/configs/ls1012ardb.h
-index 9ff5935..af3d33f 100644
---- a/include/configs/ls1012ardb.h
-+++ b/include/configs/ls1012ardb.h
-@@ -38,6 +38,21 @@
- #define CONFIG_CMD_USB
- #define CONFIG_USB_STORAGE
- #define CONFIG_CMD_EXT2
-+
-+#define CONFIG_USB_DWC3
-+#define CONFIG_USB_DWC3_GADGET
-+
-+#define CONFIG_USB_GADGET
-+#define CONFIG_USB_FUNCTION_MASS_STORAGE
-+#define CONFIG_USB_GADGET_DOWNLOAD
-+#define CONFIG_USB_GADGET_VBUS_DRAW 2
-+#define CONFIG_G_DNL_MANUFACTURER "NXP Semiconductor"
-+#define CONFIG_G_DNL_VENDOR_NUM 0x1234
-+#define CONFIG_G_DNL_PRODUCT_NUM 0x1234
-+#define CONFIG_USB_GADGET_DUALSPEED
-+
-+/* USB Gadget ums command */
-+#define CONFIG_CMD_USB_MASS_STORAGE
- #endif
-
- /*
-diff --git a/include/configs/ls1043aqds.h b/include/configs/ls1043aqds.h
-index 9828360..9e23615 100644
---- a/include/configs/ls1043aqds.h
-+++ b/include/configs/ls1043aqds.h
-@@ -400,6 +400,21 @@ unsigned long get_board_ddr_clk(void);
- #define CONFIG_CMD_USB
- #define CONFIG_USB_STORAGE
- #define CONFIG_CMD_EXT2
-+
-+#define CONFIG_USB_DWC3
-+#define CONFIG_USB_DWC3_GADGET
-+
-+#define CONFIG_USB_GADGET
-+#define CONFIG_USB_FUNCTION_MASS_STORAGE
-+#define CONFIG_USB_GADGET_DOWNLOAD
-+#define CONFIG_USB_GADGET_VBUS_DRAW 2
-+#define CONFIG_G_DNL_MANUFACTURER "NXP Semiconductor"
-+#define CONFIG_G_DNL_VENDOR_NUM 0x1234
-+#define CONFIG_G_DNL_PRODUCT_NUM 0x1234
-+#define CONFIG_USB_GADGET_DUALSPEED
-+
-+/* USB Gadget ums command */
-+#define CONFIG_CMD_USB_MASS_STORAGE
- #endif
-
- /*
---
-1.7.9.5
-
diff --git a/package/boot/uboot-layerscape/patches/0018-boards-ls1012aqds-Enable-SDHC_CD-in-brdcfg10-of-FPGA.patch b/package/boot/uboot-layerscape/patches/0018-boards-ls1012aqds-Enable-SDHC_CD-in-brdcfg10-of-FPGA.patch
deleted file mode 100644
index f46b1b2..0000000
--- a/package/boot/uboot-layerscape/patches/0018-boards-ls1012aqds-Enable-SDHC_CD-in-brdcfg10-of-FPGA.patch
+++ /dev/null
@@ -1,62 +0,0 @@
-From 035a4db85bbf28ba1452c49c9f8d05a085f2544b Mon Sep 17 00:00:00 2001
-From: Prabhakar Kushwaha <prabhakar.kushwaha at nxp.com>
-Date: Tue, 26 Apr 2016 17:40:05 +0530
-Subject: [PATCH 18/93] boards: ls1012aqds: Enable SDHC_CD in brdcfg10 of FPGA
-
-Default configuration of brdcfg10 in FPGA does not enable SDHC_CD
-signal.
-
-Enable SDHC_CD by default during boot sequence.
-
-Signed-off-by: Calvin Johnson <calvin.johnson at nxp.com>
-Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha at nxp.com>
----
- board/freescale/ls1012aqds/ls1012aqds.c | 12 ++++++++++++
- include/configs/ls1012aqds.h | 3 +++
- 2 files changed, 15 insertions(+)
-
-diff --git a/board/freescale/ls1012aqds/ls1012aqds.c b/board/freescale/ls1012aqds/ls1012aqds.c
-index ffcd0d8..6d5fef8 100644
---- a/board/freescale/ls1012aqds/ls1012aqds.c
-+++ b/board/freescale/ls1012aqds/ls1012aqds.c
-@@ -154,6 +154,18 @@ int board_early_init_f(void)
- return 0;
- }
-
-+#ifdef CONFIG_MISC_INIT_R
-+int misc_init_r(void)
-+{
-+ u8 mux_sdhc_cd = 0x80;
-+
-+ i2c_set_bus_num(0);
-+
-+ i2c_write(CONFIG_SYS_I2C_FPGA_ADDR, 0x5a, 1, &mux_sdhc_cd, 1);
-+ return 0;
-+}
-+#endif
-+
- int board_init(void)
- {
- struct ccsr_cci400 *cci = (struct ccsr_cci400 *)
-diff --git a/include/configs/ls1012aqds.h b/include/configs/ls1012aqds.h
-index fdada18..bb433de 100644
---- a/include/configs/ls1012aqds.h
-+++ b/include/configs/ls1012aqds.h
-@@ -27,6 +27,7 @@
- #endif
-
- #define CONFIG_QIXIS_I2C_ACCESS
-+#define CONFIG_SYS_I2C_FPGA_ADDR 0x66
-
- /*
- * I2C bus multiplexer
-@@ -145,4 +146,6 @@
- #define CONFIG_SYS_MEMTEST_START 0x80000000
- #define CONFIG_SYS_MEMTEST_END 0x9fffffff
-
-+#define CONFIG_MISC_INIT_R
-+
- #endif /* __LS1012AQDS_H__ */
---
-1.7.9.5
-
diff --git a/package/boot/uboot-layerscape/patches/0019-armv8-ls1012a-Add-CSU-assignment-for-eSDHC2-SAI1-SAI.patch b/package/boot/uboot-layerscape/patches/0019-armv8-ls1012a-Add-CSU-assignment-for-eSDHC2-SAI1-SAI.patch
deleted file mode 100644
index 9b3219f..0000000
--- a/package/boot/uboot-layerscape/patches/0019-armv8-ls1012a-Add-CSU-assignment-for-eSDHC2-SAI1-SAI.patch
+++ /dev/null
@@ -1,50 +0,0 @@
-From 8aad7c4c5d8becaf6c60e1585c8e70010b3c0ce2 Mon Sep 17 00:00:00 2001
-From: Makarand Pawagi <makarand.pawagi at mindspeed.com>
-Date: Mon, 2 May 2016 09:33:45 +0530
-Subject: [PATCH 19/93] armv8: ls1012a: Add CSU assignment for eSDHC2, SAI1,
- SAI2, SAI3, SAI4
-
- Access settings for different IPs has to be enabled through CSU registers. Following
- IP's are added for LS1012A:
- Added CSU ID for eSDHC-2, reg: CSL40_REG[23:16]
- Added CSU ID for SAI-1, reg: CSL41_REG[7:0]
- Added CSU ID for SAI-2, reg: CSL41_REG[23:16]
- Added CSU ID for SAI-3, reg: CSL42_REG[7:0]
- Added CSU ID for SAI-4, reg: CSL42_REG[23:16
----
- .../include/asm/arch-fsl-layerscape/ns_access.h | 10 ++++++++++
- 1 file changed, 10 insertions(+)
-
-diff --git a/arch/arm/include/asm/arch-fsl-layerscape/ns_access.h b/arch/arm/include/asm/arch-fsl-layerscape/ns_access.h
-index a3ccdb0..d6642a7 100644
---- a/arch/arm/include/asm/arch-fsl-layerscape/ns_access.h
-+++ b/arch/arm/include/asm/arch-fsl-layerscape/ns_access.h
-@@ -69,7 +69,12 @@ enum csu_cslx_ind {
- CSU_CSLX_IIC4 = 77,
- CSU_CSLX_WDT4,
- CSU_CSLX_WDT3,
-+ CSU_CSLX_ESDHC2 = 80,
- CSU_CSLX_WDT5 = 81,
-+ CSU_CSLX_SAI2,
-+ CSU_CSLX_SAI1,
-+ CSU_CSLX_SAI4,
-+ CSU_CSLX_SAI3,
- CSU_CSLX_FTM2 = 86,
- CSU_CSLX_FTM1,
- CSU_CSLX_FTM4,
-@@ -143,7 +148,12 @@ static struct csu_ns_dev ns_dev[] = {
- {CSU_CSLX_IIC4, CSU_ALL_RW},
- {CSU_CSLX_WDT4, CSU_ALL_RW},
- {CSU_CSLX_WDT3, CSU_ALL_RW},
-+ {CSU_CSLX_ESDHC2, CSU_ALL_RW},
- {CSU_CSLX_WDT5, CSU_ALL_RW},
-+ {CSU_CSLX_SAI2, CSU_ALL_RW},
-+ {CSU_CSLX_SAI1, CSU_ALL_RW},
-+ {CSU_CSLX_SAI4, CSU_ALL_RW},
-+ {CSU_CSLX_SAI3, CSU_ALL_RW},
- {CSU_CSLX_FTM2, CSU_ALL_RW},
- {CSU_CSLX_FTM1, CSU_ALL_RW},
- {CSU_CSLX_FTM4, CSU_ALL_RW},
---
-1.7.9.5
-
diff --git a/package/boot/uboot-layerscape/patches/0020-armv8-ls1012a-Update-DDR-init-sequence.patch b/package/boot/uboot-layerscape/patches/0020-armv8-ls1012a-Update-DDR-init-sequence.patch
deleted file mode 100644
index 78a3ba4..0000000
--- a/package/boot/uboot-layerscape/patches/0020-armv8-ls1012a-Update-DDR-init-sequence.patch
+++ /dev/null
@@ -1,280 +0,0 @@
-From e8703a5bba4bc0e9fa6aefe0eae7caf9141b8bdc Mon Sep 17 00:00:00 2001
-From: Prabhakar Kushwaha <prabhakar.kushwaha at nxp.com>
-Date: Mon, 2 May 2016 18:28:16 +0530
-Subject: [PATCH 20/93] armv8: ls1012a: Update DDR init sequence
-
-Current DDR init code uses lots of delay.
-
-Use wait for bit clear instead of delays.
-
-Signed-off-by: Calvin Johnson <calvin.johnson at nxp.com>
-Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha at nxp.com>
----
- board/freescale/ls1012aqds/ls1012aqds.c | 67 +++++++++++++++++--------------
- board/freescale/ls1012ardb/ls1012ardb.c | 54 +++++++++++--------------
- 2 files changed, 60 insertions(+), 61 deletions(-)
-
-diff --git a/board/freescale/ls1012aqds/ls1012aqds.c b/board/freescale/ls1012aqds/ls1012aqds.c
-index 6d5fef8..5cb225f 100644
---- a/board/freescale/ls1012aqds/ls1012aqds.c
-+++ b/board/freescale/ls1012aqds/ls1012aqds.c
-@@ -28,6 +28,20 @@
-
- DECLARE_GLOBAL_DATA_PTR;
-
-+static void set_wait_for_bits_clear(void *ptr, u32 value, u32 bits)
-+{
-+ int timeout = 1000;
-+
-+ out_be32(ptr, value);
-+
-+ while (in_be32(ptr) & bits) {
-+ udelay(100);
-+ timeout--;
-+ }
-+ if (timeout <= 0)
-+ puts("Error: wait for clear timeout.\n");
-+}
-+
- int checkboard(void)
- {
- puts("Board: LS1012AQDS\n");
-@@ -44,7 +58,7 @@ void mmdc_init(void)
- out_be32(&mmdc->mdscr, 0x00008000);
-
- /* configure timing parms */
-- out_be32(&mmdc->mdotc, 0x12554000);
-+ out_be32(&mmdc->mdotc, 0x12554000);
- out_be32(&mmdc->mdcfg0, 0xbabf7954);
- out_be32(&mmdc->mdcfg1, 0xff328f64);
- out_be32(&mmdc->mdcfg2, 0x01ff00db);
-@@ -56,7 +70,7 @@ void mmdc_init(void)
- out_be32(&mmdc->mpodtctrl, 0x0000022a);
-
- /* out of reset delays */
-- out_be32(&mmdc->mdor, 0x00bf1023);
-+ out_be32(&mmdc->mdor, 0x00bf1023);
-
- /* physical parms */
- out_be32(&mmdc->mdctl, 0x05180000);
-@@ -73,69 +87,60 @@ void mmdc_init(void)
-
- /* dram init sequence: ZQCL */
- out_be32(&mmdc->mdscr, 0x04008040);
-- out_be32(&mmdc->mpzqhwctrl, 0xa1390003);
--
-- mdelay(100);
-+ set_wait_for_bits_clear(&mmdc->mpzqhwctrl, 0xa1390003, 0x00010000);
-
- /* Calibrations now: wr lvl */
- out_be32(&mmdc->mdscr, 0x00848031);
- out_be32(&mmdc->mdscr, 0x00008200);
-- out_be32(&mmdc->mpwlgcr, 0x00000001);
-+ set_wait_for_bits_clear(&mmdc->mpwlgcr, 0x00000001, 0x00000001);
-
-- mdelay(100);
-+ mdelay(1);
-
- out_be32(&mmdc->mdscr, 0x00048031);
- out_be32(&mmdc->mdscr, 0x00008000);
-
-- /* manual_refresh */
-- out_be32(&mmdc->mdscr, 0x00008020);
--
-- mdelay(100);
-+ mdelay(1);
-
- /* Calibrations now: Read DQS gating calibration */
- out_be32(&mmdc->mdscr, 0x04008050);
- out_be32(&mmdc->mdscr, 0x00048033);
- out_be32(&mmdc->mppdcmpr2, 0x00000001);
- out_be32(&mmdc->mprddlctl, 0x40404040);
-- out_be32(&mmdc->mpdgctrl0, 0x10000000);
--
-- mdelay(100);
-+ set_wait_for_bits_clear(&mmdc->mpdgctrl0, 0x10000000, 0x10000000);
-
- out_be32(&mmdc->mdscr, 0x00008033);
-
-- /* manual_refresh */
-- out_be32(&mmdc->mdscr, 0x00008020);
--
-- mdelay(100);
-
- /* Calibrations now: Read calibration */
- out_be32(&mmdc->mdscr, 0x04008050);
- out_be32(&mmdc->mdscr, 0x00048033);
- out_be32(&mmdc->mppdcmpr2, 0x00000001);
-- out_be32(&mmdc->mprddlhwctl, 0x00000010);
--
-- mdelay(400);
-+ set_wait_for_bits_clear(&mmdc->mprddlhwctl, 0x00000010, 0x00000010);
-
- out_be32(&mmdc->mdscr, 0x00008033);
-
-- /* manual_refresh */
-- out_be32(&mmdc->mdscr, 0x00008020);
--
-- mdelay(100);
--
- /* PD, SR */
- out_be32(&mmdc->mdpdc, 0x00030035);
- out_be32(&mmdc->mapsr, 0x00001067);
-
- /* refresh scheme */
-- out_be32(&mmdc->mdref, 0x103e8000);
--
-- mdelay(400);
-+ set_wait_for_bits_clear(&mmdc->mdref, 0x103e8000, 0x00000001);
-
- /* disable CON_REQ */
- out_be32(&mmdc->mdscr, 0x0);
-+}
-
-- mdelay(50);
-+int select_i2c_ch_pca9547(u8 ch)
-+{
-+ int ret;
-+
-+ ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
-+ if (ret) {
-+ puts("PCA: failed to select proper channel\n");
-+ return ret;
-+ }
-+
-+ return 0;
- }
-
- int dram_init(void)
-@@ -183,6 +188,8 @@ int board_init(void)
- #ifdef CONFIG_ENV_IS_NOWHERE
- gd->env_addr = (ulong)&default_environment[0];
- #endif
-+ select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
-+
- return 0;
- }
-
-diff --git a/board/freescale/ls1012ardb/ls1012ardb.c b/board/freescale/ls1012ardb/ls1012ardb.c
-index 4a7aaaa..f7b9bce 100644
---- a/board/freescale/ls1012ardb/ls1012ardb.c
-+++ b/board/freescale/ls1012ardb/ls1012ardb.c
-@@ -23,6 +23,20 @@
-
- DECLARE_GLOBAL_DATA_PTR;
-
-+static void set_wait_for_bits_clear(void *ptr, u32 value, u32 bits)
-+{
-+ int timeout = 1000;
-+
-+ out_be32(ptr, value);
-+
-+ while (in_be32(ptr) & bits) {
-+ udelay(100);
-+ timeout--;
-+ }
-+ if (timeout <= 0)
-+ puts("Error: wait for clear timeout.\n");
-+}
-+
- int checkboard(void)
- {
- u8 in1;
-@@ -67,7 +81,7 @@ void mmdc_init(void)
- out_be32(&mmdc->mdscr, 0x00008000);
-
- /* configure timing parms */
-- out_be32(&mmdc->mdotc, 0x12554000);
-+ out_be32(&mmdc->mdotc, 0x12554000);
- out_be32(&mmdc->mdcfg0, 0xbabf7954);
- out_be32(&mmdc->mdcfg1, 0xff328f64);
- out_be32(&mmdc->mdcfg2, 0x01ff00db);
-@@ -79,7 +93,7 @@ void mmdc_init(void)
- out_be32(&mmdc->mpodtctrl, 0x0000022a);
-
- /* out of reset delays */
-- out_be32(&mmdc->mdor, 0x00bf1023);
-+ out_be32(&mmdc->mdor, 0x00bf1023);
-
- /* physical parms */
- out_be32(&mmdc->mdctl, 0x05180000);
-@@ -96,69 +110,47 @@ void mmdc_init(void)
-
- /* dram init sequence: ZQCL */
- out_be32(&mmdc->mdscr, 0x04008040);
-- out_be32(&mmdc->mpzqhwctrl, 0xa1390003);
--
-- mdelay(100);
-+ set_wait_for_bits_clear(&mmdc->mpzqhwctrl, 0xa1390003, 0x00010000);
-
- /* Calibrations now: wr lvl */
- out_be32(&mmdc->mdscr, 0x00848031);
- out_be32(&mmdc->mdscr, 0x00008200);
-- out_be32(&mmdc->mpwlgcr, 0x00000001);
-+ set_wait_for_bits_clear(&mmdc->mpwlgcr, 0x00000001, 0x00000001);
-
-- mdelay(100);
-+ mdelay(1);
-
- out_be32(&mmdc->mdscr, 0x00048031);
- out_be32(&mmdc->mdscr, 0x00008000);
-
-- /* manual_refresh */
-- out_be32(&mmdc->mdscr, 0x00008020);
--
-- mdelay(100);
-+ mdelay(1);
-
- /* Calibrations now: Read DQS gating calibration */
- out_be32(&mmdc->mdscr, 0x04008050);
- out_be32(&mmdc->mdscr, 0x00048033);
- out_be32(&mmdc->mppdcmpr2, 0x00000001);
- out_be32(&mmdc->mprddlctl, 0x40404040);
-- out_be32(&mmdc->mpdgctrl0, 0x10000000);
--
-- mdelay(100);
-+ set_wait_for_bits_clear(&mmdc->mpdgctrl0, 0x10000000, 0x10000000);
-
- out_be32(&mmdc->mdscr, 0x00008033);
-
-- /* manual_refresh */
-- out_be32(&mmdc->mdscr, 0x00008020);
--
-- mdelay(100);
-
- /* Calibrations now: Read calibration */
- out_be32(&mmdc->mdscr, 0x04008050);
- out_be32(&mmdc->mdscr, 0x00048033);
- out_be32(&mmdc->mppdcmpr2, 0x00000001);
-- out_be32(&mmdc->mprddlhwctl, 0x00000010);
--
-- mdelay(400);
-+ set_wait_for_bits_clear(&mmdc->mprddlhwctl, 0x00000010, 0x00000010);
-
- out_be32(&mmdc->mdscr, 0x00008033);
-
-- /* manual_refresh */
-- out_be32(&mmdc->mdscr, 0x00008020);
--
-- mdelay(100);
--
- /* PD, SR */
- out_be32(&mmdc->mdpdc, 0x00030035);
- out_be32(&mmdc->mapsr, 0x00001067);
-
- /* refresh scheme */
-- out_be32(&mmdc->mdref, 0x103e8000);
--
-- mdelay(400);
-+ set_wait_for_bits_clear(&mmdc->mdref, 0x103e8000, 0x00000001);
-
- /* disable CON_REQ */
- out_be32(&mmdc->mdscr, 0x0);
--
-- mdelay(50);
- }
-
- int dram_init(void)
---
-1.7.9.5
-
diff --git a/package/boot/uboot-layerscape/patches/0021-sf-set-the-Uniform-Sector-to-CR3NV-instead-of-CR3V.patch b/package/boot/uboot-layerscape/patches/0021-sf-set-the-Uniform-Sector-to-CR3NV-instead-of-CR3V.patch
deleted file mode 100644
index 079995d..0000000
--- a/package/boot/uboot-layerscape/patches/0021-sf-set-the-Uniform-Sector-to-CR3NV-instead-of-CR3V.patch
+++ /dev/null
@@ -1,26 +0,0 @@
-From 90ded6778736d5a0843d24eb8e5a47db72c05af9 Mon Sep 17 00:00:00 2001
-From: Mingkai Hu <mingkai.hu at nxp.com>
-Date: Mon, 18 Apr 2016 22:44:21 +0800
-Subject: [PATCH 21/93] sf: set the Uniform Sector to CR3NV instead of CR3V
-
-Signed-off-by: Mingkai Hu <mingkai.hu at nxp.com>
----
- drivers/mtd/spi/spi_flash.c | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
-diff --git a/drivers/mtd/spi/spi_flash.c b/drivers/mtd/spi/spi_flash.c
-index 865e929..97e53c7 100644
---- a/drivers/mtd/spi/spi_flash.c
-+++ b/drivers/mtd/spi/spi_flash.c
-@@ -942,7 +942,7 @@ int spi_flash_decode_fdt(const void *blob, struct spi_flash *flash)
- static int spansion_s25fss_disable_4KB_erase(struct spi_slave *spi)
- {
- u8 cmd[4];
-- u32 offset = 0x800004; /* CR3V register offset */
-+ u32 offset = 0x000004; /* CR3NV register offset */
- u8 cr3v;
- int ret;
-
---
-1.7.9.5
-
diff --git a/package/boot/uboot-layerscape/patches/0022-include-usb-Rename-USB-controller-base-address-mappi.patch b/package/boot/uboot-layerscape/patches/0022-include-usb-Rename-USB-controller-base-address-mappi.patch
deleted file mode 100644
index b4d1634..0000000
--- a/package/boot/uboot-layerscape/patches/0022-include-usb-Rename-USB-controller-base-address-mappi.patch
+++ /dev/null
@@ -1,124 +0,0 @@
-From 46c9963880e5cba6390864477f19b25369c6c944 Mon Sep 17 00:00:00 2001
-From: Rajesh Bhagat <rajesh.bhagat at nxp.com>
-Date: Thu, 5 May 2016 15:01:02 +0530
-Subject: [PATCH 22/93] include: usb: Rename USB controller base address
- mapping
-
-[context adjustment]
-
-Remove Soc specific defines and use generic chasis specific defines
-for USB controller base address mapping.
-
-Signed-off-by: Rajesh Bhagat <rajesh.bhagat at nxp.com>
-Integrated-by: Jiang Yutang <yutang.jiang at nxp.com>
----
- .../include/asm/arch-fsl-layerscape/immap_lsch2.h | 6 +++---
- .../include/asm/arch-fsl-layerscape/immap_lsch3.h | 4 ++--
- arch/arm/include/asm/arch-ls102xa/config.h | 6 ++----
- include/linux/usb/xhci-fsl.h | 20 ++++++++------------
- include/usb/ehci-fsl.h | 2 +-
- 5 files changed, 16 insertions(+), 22 deletions(-)
-
-diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
-index 414a222..3e37f00 100644
---- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
-+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
-@@ -33,9 +33,9 @@
- #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x011c0600)
- #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_IMMR + 0x011d0500)
- #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_IMMR + 0x011d0600)
--#define CONFIG_SYS_LS1043A_XHCI_USB1_ADDR (CONFIG_SYS_IMMR + 0x01f00000)
--#define CONFIG_SYS_LS1043A_XHCI_USB2_ADDR (CONFIG_SYS_IMMR + 0x02000000)
--#define CONFIG_SYS_LS1043A_XHCI_USB3_ADDR (CONFIG_SYS_IMMR + 0x02100000)
-+#define CONFIG_SYS_XHCI_USB1_ADDR (CONFIG_SYS_IMMR + 0x01f00000)
-+#define CONFIG_SYS_XHCI_USB2_ADDR (CONFIG_SYS_IMMR + 0x02000000)
-+#define CONFIG_SYS_XHCI_USB3_ADDR (CONFIG_SYS_IMMR + 0x02100000)
- #define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_IMMR + 0x2400000)
- #define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_IMMR + 0x2500000)
- #define CONFIG_SYS_PCIE3_ADDR (CONFIG_SYS_IMMR + 0x2600000)
-diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
-index 0ab709c..cf1f37a 100644
---- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
-+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
-@@ -51,8 +51,8 @@
- #define I2C3_BASE_ADDR (CONFIG_SYS_IMMR + 0x01020000)
- #define I2C4_BASE_ADDR (CONFIG_SYS_IMMR + 0x01030000)
-
--#define CONFIG_SYS_LS2080A_XHCI_USB1_ADDR (CONFIG_SYS_IMMR + 0x02100000)
--#define CONFIG_SYS_LS2080A_XHCI_USB2_ADDR (CONFIG_SYS_IMMR + 0x02110000)
-+#define CONFIG_SYS_XHCI_USB1_ADDR (CONFIG_SYS_IMMR + 0x02100000)
-+#define CONFIG_SYS_XHCI_USB2_ADDR (CONFIG_SYS_IMMR + 0x02110000)
-
- /* TZ Address Space Controller Definitions */
- #define TZASC1_BASE 0x01100000 /* as per CCSR map. */
-diff --git a/arch/arm/include/asm/arch-ls102xa/config.h b/arch/arm/include/asm/arch-ls102xa/config.h
-index 926ac58..05fff80 100644
---- a/arch/arm/include/asm/arch-ls102xa/config.h
-+++ b/arch/arm/include/asm/arch-ls102xa/config.h
-@@ -36,13 +36,11 @@
- #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x011c0500)
- #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x011d0500)
- #define CONFIG_SYS_DCU_ADDR (CONFIG_SYS_IMMR + 0x01ce0000)
--#define CONFIG_SYS_LS102XA_XHCI_USB1_ADDR (CONFIG_SYS_IMMR + 0x02100000)
--#define CONFIG_SYS_LS102XA_USB1_ADDR \
-- (CONFIG_SYS_IMMR + CONFIG_SYS_LS102XA_USB1_OFFSET)
-+#define CONFIG_SYS_XHCI_USB1_ADDR (CONFIG_SYS_IMMR + 0x02100000)
-+#define CONFIG_SYS_EHCI_USB1_ADDR (CONFIG_SYS_IMMR + 0x07600000)
-
- #define CONFIG_SYS_FSL_SEC_OFFSET 0x00700000
- #define CONFIG_SYS_FSL_JR0_OFFSET 0x00710000
--#define CONFIG_SYS_LS102XA_USB1_OFFSET 0x07600000
- #define CONFIG_SYS_TSEC1_OFFSET 0x01d10000
- #define CONFIG_SYS_TSEC2_OFFSET 0x01d50000
- #define CONFIG_SYS_TSEC3_OFFSET 0x01d90000
-diff --git a/include/linux/usb/xhci-fsl.h b/include/linux/usb/xhci-fsl.h
-index 7ab88c3..b2b3264 100644
---- a/include/linux/usb/xhci-fsl.h
-+++ b/include/linux/usb/xhci-fsl.h
-@@ -54,22 +54,18 @@ struct fsl_xhci {
- struct dwc3 *dwc3_reg;
- };
-
--#if defined(CONFIG_LS102XA)
--#define CONFIG_SYS_FSL_XHCI_USB1_ADDR CONFIG_SYS_LS102XA_XHCI_USB1_ADDR
-+#if defined(CONFIG_LS102XA) || defined(CONFIG_LS1012A)
-+#define CONFIG_SYS_FSL_XHCI_USB1_ADDR CONFIG_SYS_XHCI_USB1_ADDR
- #define CONFIG_SYS_FSL_XHCI_USB2_ADDR 0
- #define CONFIG_SYS_FSL_XHCI_USB3_ADDR 0
- #elif defined(CONFIG_LS2080A) || defined(CONFIG_LS2085A)
--#define CONFIG_SYS_FSL_XHCI_USB1_ADDR CONFIG_SYS_LS2080A_XHCI_USB1_ADDR
--#define CONFIG_SYS_FSL_XHCI_USB2_ADDR CONFIG_SYS_LS2080A_XHCI_USB2_ADDR
--#define CONFIG_SYS_FSL_XHCI_USB3_ADDR 0
--#elif defined(CONFIG_LS1043A) || defined(CONFIG_LS1012A)
--#define CONFIG_SYS_FSL_XHCI_USB1_ADDR CONFIG_SYS_LS1043A_XHCI_USB1_ADDR
--#define CONFIG_SYS_FSL_XHCI_USB2_ADDR CONFIG_SYS_LS1043A_XHCI_USB2_ADDR
--#define CONFIG_SYS_FSL_XHCI_USB3_ADDR CONFIG_SYS_LS1043A_XHCI_USB3_ADDR
--#elif defined(CONFIG_LS1012A)
--#define CONFIG_SYS_FSL_XHCI_USB1_ADDR CONFIG_SYS_LS1043A_XHCI_USB1_ADDR
--#define CONFIG_SYS_FSL_XHCI_USB2_ADDR 0
-+#define CONFIG_SYS_FSL_XHCI_USB1_ADDR CONFIG_SYS_XHCI_USB1_ADDR
-+#define CONFIG_SYS_FSL_XHCI_USB2_ADDR CONFIG_SYS_XHCI_USB2_ADDR
- #define CONFIG_SYS_FSL_XHCI_USB3_ADDR 0
-+#elif defined(CONFIG_LS1043A)
-+#define CONFIG_SYS_FSL_XHCI_USB1_ADDR CONFIG_SYS_XHCI_USB1_ADDR
-+#define CONFIG_SYS_FSL_XHCI_USB2_ADDR CONFIG_SYS_XHCI_USB2_ADDR
-+#define CONFIG_SYS_FSL_XHCI_USB3_ADDR CONFIG_SYS_XHCI_USB3_ADDR
- #endif
-
- #define FSL_USB_XHCI_ADDR {CONFIG_SYS_FSL_XHCI_USB1_ADDR, \
-diff --git a/include/usb/ehci-fsl.h b/include/usb/ehci-fsl.h
-index e9349b5..b8d78d0 100644
---- a/include/usb/ehci-fsl.h
-+++ b/include/usb/ehci-fsl.h
-@@ -164,7 +164,7 @@
- #define CONFIG_SYS_FSL_USB1_ADDR CONFIG_SYS_MPC512x_USB1_ADDR
- #define CONFIG_SYS_FSL_USB2_ADDR 0
- #elif defined(CONFIG_LS102XA)
--#define CONFIG_SYS_FSL_USB1_ADDR CONFIG_SYS_LS102XA_USB1_ADDR
-+#define CONFIG_SYS_FSL_USB1_ADDR CONFIG_SYS_EHCI_USB1_ADDR
- #define CONFIG_SYS_FSL_USB2_ADDR 0
- #endif
-
---
-1.7.9.5
-
diff --git a/package/boot/uboot-layerscape/patches/0023-drivers-usb-fsl-add-USB-ULPI-init-code.patch b/package/boot/uboot-layerscape/patches/0023-drivers-usb-fsl-add-USB-ULPI-init-code.patch
deleted file mode 100644
index 61b445d..0000000
--- a/package/boot/uboot-layerscape/patches/0023-drivers-usb-fsl-add-USB-ULPI-init-code.patch
+++ /dev/null
@@ -1,65 +0,0 @@
-From 271adb5c0546b080fb350a41520c600a16739f1a Mon Sep 17 00:00:00 2001
-From: Rajesh Bhagat <rajesh.bhagat at nxp.com>
-Date: Fri, 6 May 2016 09:05:29 +0530
-Subject: [PATCH 23/93] drivers: usb: fsl: add USB ULPI init code
-
-This adds the required code to set up a ULPI USB port, for
-new NXP USB PHY used in QorIQ platforms.
-
-To use this both CONFIG_USB_ULPI and CONFIG_USB_ULPI_VIEWPORT
-have to be set in the board configuration file.
-
-Signed-off-by: Rajesh Bhagat <rajesh.bhagat at nxp.com>
----
- drivers/usb/host/ehci-fsl.c | 21 +++++++++++++++++++++
- 1 file changed, 21 insertions(+)
-
-diff --git a/drivers/usb/host/ehci-fsl.c b/drivers/usb/host/ehci-fsl.c
-index 97b7f14..3f06345 100644
---- a/drivers/usb/host/ehci-fsl.c
-+++ b/drivers/usb/host/ehci-fsl.c
-@@ -16,6 +16,9 @@
- #include <hwconfig.h>
- #include <fsl_usb.h>
- #include <fdt_support.h>
-+#ifdef CONFIG_USB_ULPI
-+#include <usb/ulpi.h>
-+#endif
-
- #include "ehci.h"
-
-@@ -50,6 +53,10 @@ int ehci_hcd_init(int index, enum usb_init_type init,
- const char *phy_type = NULL;
- size_t len;
- char current_usb_controller[5];
-+#ifdef CONFIG_USB_ULPI
-+ int ret;
-+ struct ulpi_viewport ulpi_vp;
-+#endif
- #ifdef CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
- char usb_phy[5];
-
-@@ -126,6 +133,20 @@ int ehci_hcd_init(int index, enum usb_init_type init,
- udelay(1000); /* delay required for PHY Clk to appear */
- if (!usb_phy_clk_valid(ehci))
- return -EINVAL;
-+
-+#ifdef CONFIG_USB_ULPI
-+ ulpi_vp.viewport_addr = (u32)&ehci->ulpi_viewpoint;
-+ ulpi_vp.port_num = 0;
-+
-+ ret = ulpi_init(&ulpi_vp);
-+ if (ret) {
-+ puts("NXP ULPI viewport init failed\n");
-+ return -1;
-+ }
-+
-+ ulpi_set_vbus(&ulpi_vp, 1, 1);
-+ ulpi_set_vbus_indicator(&ulpi_vp, 1, 1, 1);
-+#endif
- out_le32(&(*hcor)->or_portsc[0], PORT_PTS_ULPI);
- }
-
---
-1.7.9.5
-
diff --git a/package/boot/uboot-layerscape/patches/0024-config-ls1012aqds-Add-USB-EHCI-support-for-ls1012aqd.patch b/package/boot/uboot-layerscape/patches/0024-config-ls1012aqds-Add-USB-EHCI-support-for-ls1012aqd.patch
deleted file mode 100644
index 4277f15..0000000
--- a/package/boot/uboot-layerscape/patches/0024-config-ls1012aqds-Add-USB-EHCI-support-for-ls1012aqd.patch
+++ /dev/null
@@ -1,67 +0,0 @@
-From dec7ec15a9c2f2c3e0a09bb9cda8a24e4d469242 Mon Sep 17 00:00:00 2001
-From: Rajesh Bhagat <rajesh.bhagat at nxp.com>
-Date: Fri, 6 May 2016 09:09:32 +0530
-Subject: [PATCH 24/93] config: ls1012aqds: Add USB EHCI support for
- ls1012aqds
-
-Add USB EHCI support for ls1012aqds platform
-
-Signed-off-by: Rajat Srivastava <rajat.srivastava at nxp.com>
-Signed-off-by: Rajesh Bhagat <rajesh.bhagat at nxp.com>
----
- .../include/asm/arch-fsl-layerscape/immap_lsch2.h | 1 +
- include/configs/ls1012aqds.h | 5 +++++
- include/usb/ehci-fsl.h | 2 +-
- 3 files changed, 7 insertions(+), 1 deletion(-)
-
-diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
-index 3e37f00..24add1a 100644
---- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
-+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
-@@ -36,6 +36,7 @@
- #define CONFIG_SYS_XHCI_USB1_ADDR (CONFIG_SYS_IMMR + 0x01f00000)
- #define CONFIG_SYS_XHCI_USB2_ADDR (CONFIG_SYS_IMMR + 0x02000000)
- #define CONFIG_SYS_XHCI_USB3_ADDR (CONFIG_SYS_IMMR + 0x02100000)
-+#define CONFIG_SYS_EHCI_USB1_ADDR (CONFIG_SYS_IMMR + 0x07600000)
- #define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_IMMR + 0x2400000)
- #define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_IMMR + 0x2500000)
- #define CONFIG_SYS_PCIE3_ADDR (CONFIG_SYS_IMMR + 0x2600000)
-diff --git a/include/configs/ls1012aqds.h b/include/configs/ls1012aqds.h
-index bb433de..51ca902 100644
---- a/include/configs/ls1012aqds.h
-+++ b/include/configs/ls1012aqds.h
-@@ -109,6 +109,8 @@
- #ifdef CONFIG_HAS_FSL_DR_USB
- #define CONFIG_USB_EHCI
- #define CONFIG_USB_EHCI_FSL
-+#define CONFIG_USB_ULPI
-+#define CONFIG_USB_ULPI_VIEWPORT
- #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
- #endif
-
-@@ -121,6 +123,9 @@
- #define CONFIG_USB_XHCI_DWC3
- #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
- #define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2
-+#endif
-+
-+#if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_XHCI_USB)
- #define CONFIG_CMD_USB
- #define CONFIG_USB_STORAGE
- #define CONFIG_CMD_EXT2
-diff --git a/include/usb/ehci-fsl.h b/include/usb/ehci-fsl.h
-index b8d78d0..94b1efa 100644
---- a/include/usb/ehci-fsl.h
-+++ b/include/usb/ehci-fsl.h
-@@ -163,7 +163,7 @@
- #elif defined(CONFIG_MPC512X)
- #define CONFIG_SYS_FSL_USB1_ADDR CONFIG_SYS_MPC512x_USB1_ADDR
- #define CONFIG_SYS_FSL_USB2_ADDR 0
--#elif defined(CONFIG_LS102XA)
-+#elif defined(CONFIG_LS102XA) || defined(CONFIG_LS1012A)
- #define CONFIG_SYS_FSL_USB1_ADDR CONFIG_SYS_EHCI_USB1_ADDR
- #define CONFIG_SYS_FSL_USB2_ADDR 0
- #endif
---
-1.7.9.5
-
diff --git a/package/boot/uboot-layerscape/patches/0025-armv8-ls1012ardb-Add-qspi-SECURE-BOOT-target.patch b/package/boot/uboot-layerscape/patches/0025-armv8-ls1012ardb-Add-qspi-SECURE-BOOT-target.patch
deleted file mode 100644
index e42e51e..0000000
--- a/package/boot/uboot-layerscape/patches/0025-armv8-ls1012ardb-Add-qspi-SECURE-BOOT-target.patch
+++ /dev/null
@@ -1,115 +0,0 @@
-From 93a1095c7da7291ffb12116de9122d431b9f6113 Mon Sep 17 00:00:00 2001
-From: Sumit Garg <sumit.garg at nxp.com>
-Date: Fri, 6 May 2016 11:11:58 -0400
-Subject: [PATCH 25/93] armv8: ls1012ardb: Add qspi SECURE BOOT target
-
-Add qspi SECURE BOOT target to enable chain of trust. Also enable
-sec_init in boot sequence.
-
-Signed-off-by: Aneesh Bansal <aneesh.bansal at nxp.com>
-Signed-off-by: Sumit Garg <sumit.garg at nxp.com>
----
- arch/arm/include/asm/arch-fsl-layerscape/config.h | 7 +++++++
- arch/arm/include/asm/fsl_secure_boot.h | 7 ++++++-
- board/freescale/ls1012ardb/ls1012ardb.c | 5 +++++
- configs/ls1012ardb_qspi_SECURE_BOOT_defconfig | 10 ++++++++++
- include/configs/ls1012ardb.h | 2 ++
- 5 files changed, 30 insertions(+), 1 deletion(-)
- create mode 100644 configs/ls1012ardb_qspi_SECURE_BOOT_defconfig
-
-diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h b/arch/arm/include/asm/arch-fsl-layerscape/config.h
-index 6ea4e8e..679be6c 100644
---- a/arch/arm/include/asm/arch-fsl-layerscape/config.h
-+++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h
-@@ -237,6 +237,13 @@
-
- #define CONFIG_SYS_FSL_ERRATUM_A009798
-
-+#define CONFIG_SYS_FSL_SFP_VER_3_2
-+#define CONFIG_SYS_FSL_SEC_MON_BE
-+#define CONFIG_SYS_FSL_SEC_BE
-+#define CONFIG_SYS_FSL_SFP_BE
-+#define CONFIG_SYS_FSL_SRK_LE
-+#define CONFIG_KEY_REVOCATION
-+
- #else
- #error SoC not defined
- #endif
-diff --git a/arch/arm/include/asm/fsl_secure_boot.h b/arch/arm/include/asm/fsl_secure_boot.h
-index c7f8b3e..c973255 100644
---- a/arch/arm/include/asm/fsl_secure_boot.h
-+++ b/arch/arm/include/asm/fsl_secure_boot.h
-@@ -50,7 +50,7 @@
- #endif
-
- #if defined(CONFIG_LS1043A) || defined(CONFIG_LS2080A) ||\
-- defined(CONFIG_LS2085A)
-+ defined(CONFIG_LS2085A) || defined(CONFIG_LS1012A)
- /* For LS1043 (ARMv8), ESBC image Address in Header is 64 bit
- * Similiarly for LS2080 and LS2085
- */
-@@ -81,6 +81,11 @@
- #define CONFIG_BS_ADDR_FLASH 0x583900000
- #define CONFIG_BS_HDR_ADDR_RAM 0xa3920000
- #define CONFIG_BS_ADDR_RAM 0xa3900000
-+#elif defined(CONFIG_LS1012A)
-+#define CONFIG_BS_HDR_ADDR_FLASH 0x400c0000
-+#define CONFIG_BS_ADDR_FLASH 0x40060000
-+#define CONFIG_BS_HDR_ADDR_RAM 0xa0060000
-+#define CONFIG_BS_ADDR_RAM 0xa0060000
- #else
- #define CONFIG_BS_HDR_ADDR_FLASH 0x600a0000
- #define CONFIG_BS_ADDR_FLASH 0x60060000
-diff --git a/board/freescale/ls1012ardb/ls1012ardb.c b/board/freescale/ls1012ardb/ls1012ardb.c
-index f7b9bce..347b8c8 100644
---- a/board/freescale/ls1012ardb/ls1012ardb.c
-+++ b/board/freescale/ls1012ardb/ls1012ardb.c
-@@ -20,6 +20,7 @@
- #include <environment.h>
- #include <fsl_mmdc.h>
- #include <netdev.h>
-+#include <fsl_sec.h>
-
- DECLARE_GLOBAL_DATA_PTR;
-
-@@ -191,6 +192,10 @@ int board_init(void)
- enable_layerscape_ns_access();
- #endif
-
-+#ifdef CONFIG_FSL_CAAM
-+ sec_init();
-+#endif
-+
- return 0;
- }
-
-diff --git a/configs/ls1012ardb_qspi_SECURE_BOOT_defconfig b/configs/ls1012ardb_qspi_SECURE_BOOT_defconfig
-new file mode 100644
-index 0000000..92a95a8
---- /dev/null
-+++ b/configs/ls1012ardb_qspi_SECURE_BOOT_defconfig
-@@ -0,0 +1,10 @@
-+CONFIG_ARM=y
-+CONFIG_TARGET_LS1012ARDB=y
-+CONFIG_SYS_EXTRA_OPTIONS="QSPI_BOOT,SECURE_BOOT"
-+# CONFIG_CMD_IMLS is not set
-+CONFIG_SYS_NS16550=y
-+CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1012a-rdb"
-+CONFIG_OF_CONTROL=y
-+CONFIG_DM=y
-+CONFIG_SPI_FLASH=y
-+CONFIG_DM_SPI=y
-diff --git a/include/configs/ls1012ardb.h b/include/configs/ls1012ardb.h
-index af3d33f..b40e02b 100644
---- a/include/configs/ls1012ardb.h
-+++ b/include/configs/ls1012ardb.h
-@@ -73,4 +73,6 @@
- #define CONFIG_SYS_MEMTEST_START 0x80000000
- #define CONFIG_SYS_MEMTEST_END 0x9fffffff
-
-+#define CONFIG_FSL_CAAM /* Enable CAAM */
-+
- #endif /* __LS1012ARDB_H__ */
---
-1.7.9.5
-
diff --git a/package/boot/uboot-layerscape/patches/0026-fsl-qixis-conditionally-compile-IFC-based-qixis-func.patch b/package/boot/uboot-layerscape/patches/0026-fsl-qixis-conditionally-compile-IFC-based-qixis-func.patch
deleted file mode 100644
index 3d49a2f..0000000
--- a/package/boot/uboot-layerscape/patches/0026-fsl-qixis-conditionally-compile-IFC-based-qixis-func.patch
+++ /dev/null
@@ -1,38 +0,0 @@
-From d99349711fa42b3e401bf9a71e315440b8ed2c17 Mon Sep 17 00:00:00 2001
-From: Abhimanyu Saini <abhimanyu.saini at nxp.com>
-Date: Tue, 10 May 2016 09:21:35 +0530
-Subject: [PATCH 26/93] fsl, qixis: conditionally compile IFC based qixis
- functions
-
-Check if qixis supports memory-mapped read/write
-before compiling IFC based qixis read/write functions.
-
-Signed-off-by: Calvin Johnson <calvin.johnson at nxp.com>
-Signed-off-by: Abhimanyu Saini <abhimanyu.saini at nxp.com>
----
- board/freescale/common/qixis.c | 2 ++
- 1 file changed, 2 insertions(+)
-
-diff --git a/board/freescale/common/qixis.c b/board/freescale/common/qixis.c
-index 113295f..2e35d41 100644
---- a/board/freescale/common/qixis.c
-+++ b/board/freescale/common/qixis.c
-@@ -27,6 +27,7 @@ void qixis_write_i2c(unsigned int reg, u8 value)
- }
- #endif
-
-+#ifdef QIXIS_BASE
- u8 qixis_read(unsigned int reg)
- {
- void *p = (void *)QIXIS_BASE;
-@@ -40,6 +41,7 @@ void qixis_write(unsigned int reg, u8 value)
-
- out_8(p + reg, value);
- }
-+#endif
-
- u16 qixis_read_minor(void)
- {
---
-1.7.9.5
-
diff --git a/package/boot/uboot-layerscape/patches/0027-fsl-qixis-Add-flag-for-LBMAP-brdcfg-reg-offset.patch b/package/boot/uboot-layerscape/patches/0027-fsl-qixis-Add-flag-for-LBMAP-brdcfg-reg-offset.patch
deleted file mode 100644
index a002e1c..0000000
--- a/package/boot/uboot-layerscape/patches/0027-fsl-qixis-Add-flag-for-LBMAP-brdcfg-reg-offset.patch
+++ /dev/null
@@ -1,48 +0,0 @@
-From 34a472a20695cbd6ab1bc2d0686c6f324d8e0d6c Mon Sep 17 00:00:00 2001
-From: Abhimanyu Saini <abhimanyu.saini at nxp.com>
-Date: Tue, 10 May 2016 09:38:46 +0530
-Subject: [PATCH 27/93] fsl, qixis: Add flag for LBMAP brdcfg reg offset
-
-Add QIXIS_LBMAP_BRDCFG_REG to the save offset of LBMAP
-configuration register instead of hardcoding it in
-set_lbmap() function.
-
-Signed-off-by: Calvin Johnson <calvin.johnson at nxp.com>
-Signed-off-by: Abhimanyu Saini <abhimanyu.saini at nxp.com>
----
- board/freescale/common/qixis.c | 11 +++++++++--
- 1 file changed, 9 insertions(+), 2 deletions(-)
-
-diff --git a/board/freescale/common/qixis.c b/board/freescale/common/qixis.c
-index 2e35d41..0db0ed6 100644
---- a/board/freescale/common/qixis.c
-+++ b/board/freescale/common/qixis.c
-@@ -14,6 +14,13 @@
- #include <i2c.h>
- #include "qixis.h"
-
-+#ifndef QIXIS_LBMAP_BRDCFG_REG
-+/*
-+ * For consistency with existing platforms
-+ */
-+#define QIXIS_LBMAP_BRDCFG_REG 0x00
-+#endif
-+
- #ifdef CONFIG_SYS_I2C_FPGA_ADDR
- u8 qixis_read_i2c(unsigned int reg)
- {
-@@ -144,9 +151,9 @@ static void __maybe_unused set_lbmap(int lbmap)
- {
- u8 reg;
-
-- reg = QIXIS_READ(brdcfg[0]);
-+ reg = QIXIS_READ(brdcfg[QIXIS_LBMAP_BRDCFG_REG]);
- reg = (reg & ~QIXIS_LBMAP_MASK) | lbmap;
-- QIXIS_WRITE(brdcfg[0], reg);
-+ QIXIS_WRITE(brdcfg[QIXIS_LBMAP_BRDCFG_REG], reg);
- }
-
- static void __maybe_unused set_rcw_src(int rcw_src)
---
-1.7.9.5
-
diff --git a/package/boot/uboot-layerscape/patches/0028-fsl-ls1012a-qixis-Add-support-for-qixis-subsystem.patch b/package/boot/uboot-layerscape/patches/0028-fsl-ls1012a-qixis-Add-support-for-qixis-subsystem.patch
deleted file mode 100644
index 0604685..0000000
--- a/package/boot/uboot-layerscape/patches/0028-fsl-ls1012a-qixis-Add-support-for-qixis-subsystem.patch
+++ /dev/null
@@ -1,80 +0,0 @@
-From 4fcb1d5141ff6d9527ceac9f391e1da4128f5a60 Mon Sep 17 00:00:00 2001
-From: Abhimanyu Saini <abhimanyu.saini at nxp.com>
-Date: Tue, 10 May 2016 09:54:36 +0530
-Subject: [PATCH 28/93] fsl, ls1012a, qixis: Add support for qixis subsystem
-
-Add support for the printing FPGA build information,
-altbank switching and board reset using qixis subsystem.
-
-Signed-off-by: Calvin Johnson <calvin.johnson at nxp.com>
-Signed-off-by: Abhimanyu Saini <abhimanyu.saini at nxp.com>
----
- board/freescale/ls1012aqds/ls1012aqds.c | 20 +++++++++++++++++++-
- include/configs/ls1012aqds.h | 17 +++++++++++++++++
- 2 files changed, 36 insertions(+), 1 deletion(-)
-
-diff --git a/board/freescale/ls1012aqds/ls1012aqds.c b/board/freescale/ls1012aqds/ls1012aqds.c
-index 5cb225f..446989b 100644
---- a/board/freescale/ls1012aqds/ls1012aqds.c
-+++ b/board/freescale/ls1012aqds/ls1012aqds.c
-@@ -44,8 +44,26 @@ static void set_wait_for_bits_clear(void *ptr, u32 value, u32 bits)
-
- int checkboard(void)
- {
-- puts("Board: LS1012AQDS\n");
-+ char buf[64];
-+ u8 sw;
-
-+ sw = QIXIS_READ(arch);
-+ printf("Board Arch: V%d, ", sw >> 4);
-+ printf("Board version: %c, boot from ", (sw & 0xf) + 'A' - 1);
-+
-+ sw = QIXIS_READ(brdcfg[QIXIS_LBMAP_BRDCFG_REG]);
-+
-+ if (sw & QIXIS_LBMAP_ALTBANK)
-+ printf("flash: 2\n");
-+ else
-+ printf("flash: 1\n");
-+
-+ printf("FPGA: v%d (%s), build %d",
-+ (int)QIXIS_READ(scver), qixis_read_tag(buf),
-+ (int)qixis_read_minor());
-+
-+ /* the timestamp string contains "\n" at the end */
-+ printf(" on %s", qixis_read_time(buf));
- return 0;
- }
-
-diff --git a/include/configs/ls1012aqds.h b/include/configs/ls1012aqds.h
-index 51ca902..de998b8 100644
---- a/include/configs/ls1012aqds.h
-+++ b/include/configs/ls1012aqds.h
-@@ -26,8 +26,25 @@
- #define SGMII_CARD_PORT4_PHY_ADDR 0x1F
- #endif
-
-+/*
-+ * QIXIS Definitions
-+ */
-+#define CONFIG_FSL_QIXIS
-+
-+#ifdef CONFIG_FSL_QIXIS
- #define CONFIG_QIXIS_I2C_ACCESS
- #define CONFIG_SYS_I2C_FPGA_ADDR 0x66
-+#define QIXIS_LBMAP_BRDCFG_REG 0x04
-+#define QIXIS_LBMAP_SWITCH 6
-+#define QIXIS_LBMAP_MASK 0xf7
-+#define QIXIS_LBMAP_SHIFT 0
-+#define QIXIS_LBMAP_DFLTBANK 0x00
-+#define QIXIS_LBMAP_ALTBANK 0x08
-+#define QIXIS_RST_CTL_RESET 0x41
-+#define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
-+#define QIXIS_RCFG_CTL_RECONFIG_START 0x21
-+#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
-+#endif
-
- /*
- * I2C bus multiplexer
---
-1.7.9.5
-
diff --git a/package/boot/uboot-layerscape/patches/0029-armv8-ls1012a-Added-CSU-assignment-for-USB2.patch b/package/boot/uboot-layerscape/patches/0029-armv8-ls1012a-Added-CSU-assignment-for-USB2.patch
deleted file mode 100644
index 228e762..0000000
--- a/package/boot/uboot-layerscape/patches/0029-armv8-ls1012a-Added-CSU-assignment-for-USB2.patch
+++ /dev/null
@@ -1,37 +0,0 @@
-From 57700b94f9111578d0fc05bb8f273c0b29951572 Mon Sep 17 00:00:00 2001
-From: Rajesh Bhagat <rajesh.bhagat at nxp.com>
-Date: Wed, 11 May 2016 14:59:39 +0530
-Subject: [PATCH 29/93] armv8: ls1012a: Added CSU assignment for USB2
-
-Access settings for USB2 IP is added through CSU register.
-
-Added CSU ID for USB2, reg: CSL23_REG[8:0]
-
-Signed-off-by: Rajesh Bhagat <rajesh.bhagat at nxp.com>
----
- .../include/asm/arch-fsl-layerscape/ns_access.h | 2 ++
- 1 file changed, 2 insertions(+)
-
-diff --git a/arch/arm/include/asm/arch-fsl-layerscape/ns_access.h b/arch/arm/include/asm/arch-fsl-layerscape/ns_access.h
-index d6642a7..2fd33e1 100644
---- a/arch/arm/include/asm/arch-fsl-layerscape/ns_access.h
-+++ b/arch/arm/include/asm/arch-fsl-layerscape/ns_access.h
-@@ -38,6 +38,7 @@ enum csu_cslx_ind {
- CSU_CSLX_ESDHC,
- CSU_CSLX_IFC = 45,
- CSU_CSLX_I2C1,
-+ CSU_CSLX_USB_2,
- CSU_CSLX_I2C3 = 48,
- CSU_CSLX_I2C2,
- CSU_CSLX_DUART2 = 50,
-@@ -117,6 +118,7 @@ static struct csu_ns_dev ns_dev[] = {
- {CSU_CSLX_ESDHC, CSU_ALL_RW},
- {CSU_CSLX_IFC, CSU_ALL_RW},
- {CSU_CSLX_I2C1, CSU_ALL_RW},
-+ {CSU_CSLX_USB_2, CSU_ALL_RW},
- {CSU_CSLX_I2C3, CSU_ALL_RW},
- {CSU_CSLX_I2C2, CSU_ALL_RW},
- {CSU_CSLX_DUART2, CSU_ALL_RW},
---
-1.7.9.5
-
diff --git a/package/boot/uboot-layerscape/patches/0030-ARMv8-Enable-CPUECTLR.SMPEN-for-data-coherency.patch b/package/boot/uboot-layerscape/patches/0030-ARMv8-Enable-CPUECTLR.SMPEN-for-data-coherency.patch
deleted file mode 100644
index 33ea668..0000000
--- a/package/boot/uboot-layerscape/patches/0030-ARMv8-Enable-CPUECTLR.SMPEN-for-data-coherency.patch
+++ /dev/null
@@ -1,32 +0,0 @@
-From 367c16da9255dacf6440f3c72c01c197cfb1bbe8 Mon Sep 17 00:00:00 2001
-From: Sumit Garg <sumit.garg at nxp.com>
-Date: Wed, 11 May 2016 12:44:35 -0400
-Subject: [PATCH 30/93] ARMv8: Enable CPUECTLR.SMPEN for data coherency
-
-Data coherency is enabled only when the CPUECTLR.SMPEN bit is set.
-The SMPEN bit should be set before enabling the data cache. If not
-enabled, the cache is not coherent with other cores and data
-corruption could occur. It also enables core level cache snooping.
-
-Signed-off-by: Sumit Garg <sumit.garg at nxp.com>
----
- arch/arm/cpu/armv8/start.S | 3 +++
- 1 file changed, 3 insertions(+)
-
-diff --git a/arch/arm/cpu/armv8/start.S b/arch/arm/cpu/armv8/start.S
-index 235213f..9703f6b 100644
---- a/arch/arm/cpu/armv8/start.S
-+++ b/arch/arm/cpu/armv8/start.S
-@@ -70,6 +70,9 @@ reset:
- mov x0, #3 << 20
- msr cpacr_el1, x0 /* Enable FP/SIMD */
- 0:
-+ /* Enalbe SMPEN bit */
-+ mov x0, #0x40
-+ msr s3_1_c15_c2_1, x0
-
- /* Apply ARM core specific erratas */
- bl apply_core_errata
---
-1.7.9.5
-
diff --git a/package/boot/uboot-layerscape/patches/0031-mtd-sf-add-exceed-flash-16MB-support-for-qspi.patch b/package/boot/uboot-layerscape/patches/0031-mtd-sf-add-exceed-flash-16MB-support-for-qspi.patch
deleted file mode 100644
index aa39699..0000000
--- a/package/boot/uboot-layerscape/patches/0031-mtd-sf-add-exceed-flash-16MB-support-for-qspi.patch
+++ /dev/null
@@ -1,308 +0,0 @@
-From 6cfe5c5e7f6a4b3d46f65967fe10820ee2e3d2fa Mon Sep 17 00:00:00 2001
-From: Yunhui Cui <yunhui.cui at nxp.com>
-Date: Fri, 13 May 2016 16:30:33 +0800
-Subject: [PATCH 31/93] mtd: sf: add exceed flash 16MB support for qspi
-
-spi/spi_flash.c: The flash S25FS512S cannot legacy commands
-such as Bank Address Related Command, So we need add the exceed
-16MB suuport. So we extend the cmd[] size to support 32-bit address,
-what's more, as to spi/fsl_qspi.c need to a flag to pionts the address
-mask, So add the magic num '0xaa' into cmd[].
-
-Signed-off-by: Yunhui Cui <yunhui.cui at nxp.com>
----
- arch/arm/dts/fsl-ls1012a.dtsi | 2 +-
- drivers/mtd/spi/sf_internal.h | 7 ++++
- drivers/mtd/spi/spi_flash.c | 73 ++++++++++++++++++++++++++++++--------
- drivers/spi/fsl_qspi.c | 30 ++++++++++++++--
- include/configs/ls1012a_common.h | 3 +-
- 5 files changed, 95 insertions(+), 20 deletions(-)
-
-diff --git a/arch/arm/dts/fsl-ls1012a.dtsi b/arch/arm/dts/fsl-ls1012a.dtsi
-index 87a287a..2549c91 100644
---- a/arch/arm/dts/fsl-ls1012a.dtsi
-+++ b/arch/arm/dts/fsl-ls1012a.dtsi
-@@ -108,7 +108,7 @@
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <0x0 0x1550000 0x0 0x10000>,
-- <0x0 0x40000000 0x0 0x4000000>;
-+ <0x0 0x40000000 0x0 0x8000000>;
- reg-names = "QuadSPI", "QuadSPI-memory";
- num-cs = <2>;
- big-endian;
-diff --git a/drivers/mtd/spi/sf_internal.h b/drivers/mtd/spi/sf_internal.h
-index c778b60..3c38425 100644
---- a/drivers/mtd/spi/sf_internal.h
-+++ b/drivers/mtd/spi/sf_internal.h
-@@ -57,6 +57,13 @@ enum spi_nor_option_flags {
- #define SPI_FLASH_CMD_LEN (1 + SPI_FLASH_3B_ADDR_LEN)
- #define SPI_FLASH_16MB_BOUN 0x1000000
-
-+#define SPI_FLASH_ADDR_MAGIC 0xaa
-+#define SPI_FLASH_ADDR_MAGIC_LEN 1
-+#define SPI_FLASH_4B_ADDR_LEN 4
-+#define SPI_FLASH_CMD_LEN_EXT (1 + SPI_FLASH_4B_ADDR_LEN + \
-+ SPI_FLASH_ADDR_MAGIC_LEN)
-+#define SPI_FLASH_64MB_BOUN 0x4000000
-+
- /* CFI Manufacture ID's */
- #define SPI_FLASH_CFI_MFR_SPANSION 0x01
- #define SPI_FLASH_CFI_MFR_STMICRO 0x20
-diff --git a/drivers/mtd/spi/spi_flash.c b/drivers/mtd/spi/spi_flash.c
-index 97e53c7..9d61ac0 100644
---- a/drivers/mtd/spi/spi_flash.c
-+++ b/drivers/mtd/spi/spi_flash.c
-@@ -21,12 +21,20 @@
-
- DECLARE_GLOBAL_DATA_PTR;
-
--static void spi_flash_addr(u32 addr, u8 *cmd)
-+static void spi_flash_addr(u32 addr, u8 *cmd, u32 offset_ext)
- {
-- /* cmd[0] is actual command */
-- cmd[1] = addr >> 16;
-- cmd[2] = addr >> 8;
-- cmd[3] = addr >> 0;
-+ if (offset_ext >= SPI_FLASH_16MB_BOUN) {
-+ /* cmd[0] is actual command */
-+ cmd[1] = addr >> 24;
-+ cmd[2] = addr >> 16;
-+ cmd[3] = addr >> 8;
-+ cmd[4] = addr >> 0;
-+ cmd[5] = SPI_FLASH_ADDR_MAGIC;
-+ } else {
-+ cmd[1] = addr >> 16;
-+ cmd[2] = addr >> 8;
-+ cmd[3] = addr >> 0;
-+ }
- }
-
- /* Read commands array */
-@@ -302,9 +310,11 @@ int spi_flash_write_common(struct spi_flash *flash, const u8 *cmd,
- int spi_flash_cmd_erase_ops(struct spi_flash *flash, u32 offset, size_t len)
- {
- u32 erase_size, erase_addr;
-- u8 cmd[SPI_FLASH_CMD_LEN];
-+ u8 *cmd, cmdsz;
- int ret = -1;
-+ u32 offset_ext;
-
-+ offset_ext = offset;
- erase_size = flash->erase_size;
- if (offset % erase_size || len % erase_size) {
- debug("SF: Erase offset/length not multiple of erase size\n");
-@@ -319,7 +329,18 @@ int spi_flash_cmd_erase_ops(struct spi_flash *flash, u32 offset, size_t len)
- }
- }
-
-+ if (offset > SPI_FLASH_16MB_BOUN)
-+ cmdsz = SPI_FLASH_CMD_LEN_EXT + flash->dummy_byte;
-+ else
-+ cmdsz = SPI_FLASH_CMD_LEN + flash->dummy_byte;
-+ cmd = calloc(1, cmdsz);
-+ if (!cmd) {
-+ debug("SF: Failed to allocate cmd\n");
-+ return -ENOMEM;
-+ }
-+ memset(cmd, 0x0, cmdsz);
- cmd[0] = flash->erase_cmd;
-+
- while (len) {
- erase_addr = offset;
-
-@@ -332,7 +353,7 @@ int spi_flash_cmd_erase_ops(struct spi_flash *flash, u32 offset, size_t len)
- if (ret < 0)
- return ret;
- #endif
-- spi_flash_addr(erase_addr, cmd);
-+ spi_flash_addr(erase_addr, cmd, offset_ext);
-
- debug("SF: erase %2x %2x %2x %2x (%x)\n", cmd[0], cmd[1],
- cmd[2], cmd[3], erase_addr);
-@@ -347,6 +368,7 @@ int spi_flash_cmd_erase_ops(struct spi_flash *flash, u32 offset, size_t len)
- len -= erase_size;
- }
-
-+ free(cmd);
- return ret;
- }
-
-@@ -356,9 +378,11 @@ int spi_flash_cmd_write_ops(struct spi_flash *flash, u32 offset,
- unsigned long byte_addr, page_size;
- u32 write_addr;
- size_t chunk_len, actual;
-- u8 cmd[SPI_FLASH_CMD_LEN];
-+ u8 *cmd, cmdsz;
- int ret = -1;
-+ u32 offset_ext;
-
-+ offset_ext = offset;
- page_size = flash->page_size;
-
- if (flash->flash_is_locked) {
-@@ -369,6 +393,16 @@ int spi_flash_cmd_write_ops(struct spi_flash *flash, u32 offset,
- }
- }
-
-+ if (offset > SPI_FLASH_16MB_BOUN)
-+ cmdsz = SPI_FLASH_CMD_LEN_EXT + flash->dummy_byte;
-+ else
-+ cmdsz = SPI_FLASH_CMD_LEN + flash->dummy_byte;
-+ cmd = calloc(1, cmdsz);
-+ if (!cmd) {
-+ debug("SF: Failed to allocate cmd\n");
-+ return -ENOMEM;
-+ }
-+ memset(cmd, 0x0, cmdsz);
- cmd[0] = flash->write_cmd;
- for (actual = 0; actual < len; actual += chunk_len) {
- write_addr = offset;
-@@ -389,7 +423,7 @@ int spi_flash_cmd_write_ops(struct spi_flash *flash, u32 offset,
- chunk_len = min(chunk_len,
- (size_t)flash->spi->max_write_size);
-
-- spi_flash_addr(write_addr, cmd);
-+ spi_flash_addr(write_addr, cmd, offset_ext);
-
- debug("SF: 0x%p => cmd = { 0x%02x 0x%02x%02x%02x } chunk_len = %zu\n",
- buf + actual, cmd[0], cmd[1], cmd[2], cmd[3], chunk_len);
-@@ -404,6 +438,7 @@ int spi_flash_cmd_write_ops(struct spi_flash *flash, u32 offset,
- offset += chunk_len;
- }
-
-+ free(cmd);
- return ret;
- }
-
-@@ -442,6 +477,9 @@ int spi_flash_cmd_read_ops(struct spi_flash *flash, u32 offset,
- u32 remain_len, read_len, read_addr;
- int bank_sel = 0;
- int ret = -1;
-+ u32 offset_ext;
-+
-+ offset_ext = offset;
-
- /* Handle memory-mapped SPI */
- if (flash->memory_map) {
-@@ -456,15 +494,18 @@ int spi_flash_cmd_read_ops(struct spi_flash *flash, u32 offset,
- spi_release_bus(flash->spi);
- return 0;
- }
--
-- cmdsz = SPI_FLASH_CMD_LEN + flash->dummy_byte;
-+ if (offset > SPI_FLASH_16MB_BOUN)
-+ cmdsz = SPI_FLASH_CMD_LEN_EXT + flash->dummy_byte;
-+ else
-+ cmdsz = SPI_FLASH_CMD_LEN + flash->dummy_byte;
- cmd = calloc(1, cmdsz);
- if (!cmd) {
- debug("SF: Failed to allocate cmd\n");
- return -ENOMEM;
- }
--
-+ memset(cmd, 0x0, cmdsz);
- cmd[0] = flash->read_cmd;
-+
- while (len) {
- read_addr = offset;
-
-@@ -478,14 +519,18 @@ int spi_flash_cmd_read_ops(struct spi_flash *flash, u32 offset,
- return ret;
- bank_sel = flash->bank_curr;
- #endif
-- remain_len = ((SPI_FLASH_16MB_BOUN << flash->shift) *
-+ if (offset_ext >= SPI_FLASH_16MB_BOUN) {
-+ remain_len = flash->size - offset;
-+ } else {
-+ remain_len = ((SPI_FLASH_16MB_BOUN << flash->shift) *
- (bank_sel + 1)) - offset;
-+ }
- if (len < remain_len)
- read_len = len;
- else
- read_len = remain_len;
-
-- spi_flash_addr(read_addr, cmd);
-+ spi_flash_addr(read_addr, cmd, offset_ext);
-
- ret = spi_flash_read_common(flash, cmd, cmdsz, data, read_len);
- if (ret < 0) {
-diff --git a/drivers/spi/fsl_qspi.c b/drivers/spi/fsl_qspi.c
-index 2b20038..09759fa 100644
---- a/drivers/spi/fsl_qspi.c
-+++ b/drivers/spi/fsl_qspi.c
-@@ -26,6 +26,9 @@ DECLARE_GLOBAL_DATA_PTR;
- #endif
-
- #define OFFSET_BITS_MASK GENMASK(23, 0)
-+/* the qspi contrller memmap space ,instead of flash space */
-+#define OFFSET_BITS_MASK_QSPI_SPACE GENMASK(27, 0)
-+#define SPI_FLASH_ADDR_EXT_MAGIC 0xaa
-
- #define FLASH_STATUS_WEL 0x02
-
-@@ -757,6 +760,13 @@ int qspi_xfer(struct fsl_qspi_priv *priv, unsigned int bitlen,
- u32 bytes = DIV_ROUND_UP(bitlen, 8);
- static u32 wr_sfaddr;
- u32 txbuf;
-+ u8 offset_ext = 0;
-+ u32 flash_offset;
-+
-+ if (((u8 *)dout)[5] == SPI_FLASH_ADDR_EXT_MAGIC) {
-+ offset_ext = 1;
-+ memcpy(&flash_offset, dout + 1, 4);
-+ }
-
- if (dout) {
- if (flags & SPI_XFER_BEGIN) {
-@@ -772,14 +782,28 @@ int qspi_xfer(struct fsl_qspi_priv *priv, unsigned int bitlen,
-
- if (priv->cur_seqid == QSPI_CMD_FAST_READ ||
- priv->cur_seqid == QSPI_CMD_RDAR) {
-- priv->sf_addr = swab32(txbuf) & OFFSET_BITS_MASK;
-+ if (offset_ext)
-+ priv->sf_addr = swab32(flash_offset) &
-+ OFFSET_BITS_MASK_QSPI_SPACE;
-+ else
-+ priv->sf_addr = swab32(txbuf) &
-+ OFFSET_BITS_MASK;
- } else if ((priv->cur_seqid == QSPI_CMD_SE) ||
- (priv->cur_seqid == QSPI_CMD_BE_4K)) {
-- priv->sf_addr = swab32(txbuf) & OFFSET_BITS_MASK;
-+ if (offset_ext)
-+ priv->sf_addr = swab32(flash_offset) &
-+ OFFSET_BITS_MASK_QSPI_SPACE;
-+ else
-+ priv->sf_addr = swab32(txbuf) &
-+ OFFSET_BITS_MASK;
- qspi_op_erase(priv);
- } else if (priv->cur_seqid == QSPI_CMD_PP ||
- priv->cur_seqid == QSPI_CMD_WRAR) {
-- wr_sfaddr = swab32(txbuf) & OFFSET_BITS_MASK;
-+ if (offset_ext)
-+ wr_sfaddr = swab32(flash_offset) &
-+ OFFSET_BITS_MASK_QSPI_SPACE;
-+ else
-+ wr_sfaddr = swab32(txbuf) & OFFSET_BITS_MASK;
- } else if ((priv->cur_seqid == QSPI_CMD_BRWR) ||
- (priv->cur_seqid == QSPI_CMD_WREAR)) {
- #ifdef CONFIG_SPI_FLASH_BAR
-diff --git a/include/configs/ls1012a_common.h b/include/configs/ls1012a_common.h
-index 3fd360a..150444d 100644
---- a/include/configs/ls1012a_common.h
-+++ b/include/configs/ls1012a_common.h
-@@ -63,9 +63,8 @@
- #define QSPI0_AMBA_BASE 0x40000000
- #define CONFIG_SPI_FLASH_SPANSION
- #define CONFIG_DM_SPI_FLASH
--#define CONFIG_SPI_FLASH_BAR
-
--#define FSL_QSPI_FLASH_SIZE (1 << 24)
-+#define FSL_QSPI_FLASH_SIZE (1 << 26)
- #define FSL_QSPI_FLASH_NUM 2
-
- /*
---
-1.7.9.5
-
diff --git a/package/boot/uboot-layerscape/patches/0032-driver-spi-fsl_qspi-enable-AHB-read-for-qspi.patch b/package/boot/uboot-layerscape/patches/0032-driver-spi-fsl_qspi-enable-AHB-read-for-qspi.patch
deleted file mode 100644
index 31e0a83..0000000
--- a/package/boot/uboot-layerscape/patches/0032-driver-spi-fsl_qspi-enable-AHB-read-for-qspi.patch
+++ /dev/null
@@ -1,30 +0,0 @@
-From c67f214546a9d8ac00b9b947c145f4c032def8e2 Mon Sep 17 00:00:00 2001
-From: Yunhui Cui <yunhui.cui at nxp.com>
-Date: Mon, 16 May 2016 14:39:52 +0800
-Subject: [PATCH 32/93] driver: spi: fsl_qspi: enable AHB read for qspi
-
-If we don't enable the AHB read for ls1012a, input 'md 0x40000000',
-'md 0x41000000','md 0x42000000' address will be overlapped.
-After QSPI controller initialization for AHB, 'md 0x...' will access
-the whole QSPI flash address space.
-
-Signed-off-by: Yunhui Cui <yunhui.cui at nxp.com>
----
- include/configs/ls1012a_common.h | 1 +
- 1 file changed, 1 insertion(+)
-
-diff --git a/include/configs/ls1012a_common.h b/include/configs/ls1012a_common.h
-index 150444d..121824c 100644
---- a/include/configs/ls1012a_common.h
-+++ b/include/configs/ls1012a_common.h
-@@ -66,6 +66,7 @@
-
- #define FSL_QSPI_FLASH_SIZE (1 << 26)
- #define FSL_QSPI_FLASH_NUM 2
-+#define CONFIG_SYS_FSL_QSPI_AHB
-
- /*
- * Environment
---
-1.7.9.5
-
diff --git a/package/boot/uboot-layerscape/patches/0033-mmc-fsl_esdhc-support-two-esdhc-host-controllers.patch b/package/boot/uboot-layerscape/patches/0033-mmc-fsl_esdhc-support-two-esdhc-host-controllers.patch
deleted file mode 100644
index 9cc171c..0000000
--- a/package/boot/uboot-layerscape/patches/0033-mmc-fsl_esdhc-support-two-esdhc-host-controllers.patch
+++ /dev/null
@@ -1,47 +0,0 @@
-From 2daf451df50209e7626c2bf424d50ff23055784a Mon Sep 17 00:00:00 2001
-From: Yangbo Lu <yangbo.lu at nxp.com>
-Date: Wed, 18 May 2016 10:52:38 +0800
-Subject: [PATCH 33/93] mmc: fsl_esdhc: support two esdhc host controllers
-
-This patch is to support two esdhc host controllers with
-the macro CONFIG_FSL_ESDHC_TWO_CONTROLLERS_SUPPORT.
-
-Signed-off-by: Yangbo Lu <yangbo.lu at nxp.com>
----
- drivers/mmc/fsl_esdhc.c | 15 +++++++++++++++
- 1 file changed, 15 insertions(+)
-
-diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c
-index 7cc61a0..cacf879 100644
---- a/drivers/mmc/fsl_esdhc.c
-+++ b/drivers/mmc/fsl_esdhc.c
-@@ -748,11 +748,26 @@ int fsl_esdhc_initialize(bd_t *bis, struct fsl_esdhc_cfg *cfg)
- int fsl_esdhc_mmc_init(bd_t *bis)
- {
- struct fsl_esdhc_cfg *cfg;
-+#ifdef CONFIG_FSL_ESDHC_TWO_CONTROLLERS_SUPPORT
-+ struct fsl_esdhc_cfg *cfg_1;
-+#endif
-
- cfg = calloc(sizeof(struct fsl_esdhc_cfg), 1);
- cfg->esdhc_base = CONFIG_SYS_FSL_ESDHC_ADDR;
- cfg->sdhc_clk = gd->arch.sdhc_clk;
-+#ifdef CONFIG_FSL_ESDHC_TWO_CONTROLLERS_SUPPORT
-+ cfg_1 = calloc(sizeof(struct fsl_esdhc_cfg), 1);
-+ cfg_1->esdhc_base = CONFIG_SYS_FSL_ESDHC_1_ADDR;
-+ cfg_1->sdhc_clk = gd->arch.sdhc_clk;
-+
-+ if (fsl_esdhc_initialize(bis, cfg))
-+ return -1;
-+ if (fsl_esdhc_initialize(bis, cfg_1))
-+ return -1;
-+ return 0;
-+#else
- return fsl_esdhc_initialize(bis, cfg);
-+#endif
- }
-
- #ifdef CONFIG_FSL_ESDHC_ADAPTER_IDENT
---
-1.7.9.5
-
diff --git a/package/boot/uboot-layerscape/patches/0034-mmc-fsl_esdhc-add-workaround-for-non-removable-card-.patch b/package/boot/uboot-layerscape/patches/0034-mmc-fsl_esdhc-add-workaround-for-non-removable-card-.patch
deleted file mode 100644
index 00c4449..0000000
--- a/package/boot/uboot-layerscape/patches/0034-mmc-fsl_esdhc-add-workaround-for-non-removable-card-.patch
+++ /dev/null
@@ -1,57 +0,0 @@
-From e3e641993a1a5148e71bdd3f7b3cb5da695b1632 Mon Sep 17 00:00:00 2001
-From: Yangbo Lu <yangbo.lu at nxp.com>
-Date: Fri, 20 May 2016 11:17:30 +0800
-Subject: [PATCH 34/93] mmc: fsl_esdhc: add workaround for non-removable card
- of esdhc-2
-
-The esdhc-2 usually uses some on-board memory devices such as eMMC
-card or SDIO wifi module, and it doesn't support SDHC_CD_B. So we
-could only assume it always has a card instead of detecting SDHC_CD_B
-status. This patch is to add workaround for these non-removable
-cards which are used by esdhc-2.
-
-Signed-off-by: Yangbo Lu <yangbo.lu at nxp.com>
----
- drivers/mmc/fsl_esdhc.c | 6 +++++-
- include/fsl_esdhc.h | 1 +
- 2 files changed, 6 insertions(+), 1 deletion(-)
-
-diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c
-index cacf879..2c6e175 100644
---- a/drivers/mmc/fsl_esdhc.c
-+++ b/drivers/mmc/fsl_esdhc.c
-@@ -628,6 +628,8 @@ static int esdhc_getcd(struct mmc *mmc)
- struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base;
- int timeout = 1000;
-
-+ if (cfg->non_removable_card)
-+ return 1;
- #ifdef CONFIG_ESDHC_DETECT_QUIRK
- if (CONFIG_ESDHC_DETECT_QUIRK)
- return 1;
-@@ -759,7 +761,9 @@ int fsl_esdhc_mmc_init(bd_t *bis)
- cfg_1 = calloc(sizeof(struct fsl_esdhc_cfg), 1);
- cfg_1->esdhc_base = CONFIG_SYS_FSL_ESDHC_1_ADDR;
- cfg_1->sdhc_clk = gd->arch.sdhc_clk;
--
-+#ifdef CONFIG_FSL_ESDHC_1_NON_REMOVABLE_CARD
-+ cfg_1->non_removable_card = true;
-+#endif
- if (fsl_esdhc_initialize(bis, cfg))
- return -1;
- if (fsl_esdhc_initialize(bis, cfg_1))
-diff --git a/include/fsl_esdhc.h b/include/fsl_esdhc.h
-index 073048f..8335106 100644
---- a/include/fsl_esdhc.h
-+++ b/include/fsl_esdhc.h
-@@ -175,6 +175,7 @@ struct fsl_esdhc_cfg {
- #endif
- u32 sdhc_clk;
- u8 max_bus_width;
-+ bool non_removable_card;
- struct mmc_config cfg;
- };
-
---
-1.7.9.5
-
diff --git a/package/boot/uboot-layerscape/patches/0035-armv8-ls1012a-enable-two-esdhc-host-controllers-supp.patch b/package/boot/uboot-layerscape/patches/0035-armv8-ls1012a-enable-two-esdhc-host-controllers-supp.patch
deleted file mode 100644
index 2099d40..0000000
--- a/package/boot/uboot-layerscape/patches/0035-armv8-ls1012a-enable-two-esdhc-host-controllers-supp.patch
+++ /dev/null
@@ -1,43 +0,0 @@
-From 7d3d85483a6c4085de5c016b86838681e97e6577 Mon Sep 17 00:00:00 2001
-From: Yangbo Lu <yangbo.lu at nxp.com>
-Date: Fri, 20 May 2016 11:31:17 +0800
-Subject: [PATCH 35/93] armv8: ls1012a: enable two esdhc host controllers
- support
-
-LS1012A chip has two esdhc host controllers, and this patch
-is to enable two controllers support for it.
-
-Signed-off-by: Yangbo Lu <yangbo.lu at nxp.com>
----
- .../include/asm/arch-fsl-layerscape/immap_lsch2.h | 1 +
- include/configs/ls1012a_common.h | 2 ++
- 2 files changed, 3 insertions(+)
-
-diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
-index 24add1a..6918757 100644
---- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
-+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
-@@ -19,6 +19,7 @@
- #define CONFIG_SYS_GIC400_ADDR (CONFIG_SYS_IMMR + 0x00400000)
- #define CONFIG_SYS_IFC_ADDR (CONFIG_SYS_IMMR + 0x00530000)
- #define CONFIG_SYS_FSL_ESDHC_ADDR (CONFIG_SYS_IMMR + 0x00560000)
-+#define CONFIG_SYS_FSL_ESDHC_1_ADDR (CONFIG_SYS_IMMR + 0x00580000)
- #define CONFIG_SYS_FSL_CSU_ADDR (CONFIG_SYS_IMMR + 0x00510000)
- #define CONFIG_SYS_FSL_GUTS_ADDR (CONFIG_SYS_IMMR + 0x00ee0000)
- #define CONFIG_SYS_FSL_RST_ADDR (CONFIG_SYS_IMMR + 0x00ee00b0)
-diff --git a/include/configs/ls1012a_common.h b/include/configs/ls1012a_common.h
-index 121824c..89d1370 100644
---- a/include/configs/ls1012a_common.h
-+++ b/include/configs/ls1012a_common.h
-@@ -94,6 +94,8 @@
- #ifdef CONFIG_MMC
- #define CONFIG_CMD_MMC
- #define CONFIG_FSL_ESDHC
-+#define CONFIG_FSL_ESDHC_TWO_CONTROLLERS_SUPPORT
-+#define CONFIG_FSL_ESDHC_1_NON_REMOVABLE_CARD
- #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
- #define CONFIG_GENERIC_MMC
- #define CONFIG_CMD_FAT
---
-1.7.9.5
-
diff --git a/package/boot/uboot-layerscape/patches/0036-driver-spi-add-exceed-16MB-flash-support.patch b/package/boot/uboot-layerscape/patches/0036-driver-spi-add-exceed-16MB-flash-support.patch
deleted file mode 100644
index c43ae97..0000000
--- a/package/boot/uboot-layerscape/patches/0036-driver-spi-add-exceed-16MB-flash-support.patch
+++ /dev/null
@@ -1,144 +0,0 @@
-From e70ae7f7ed00ecdbfa45fac3f342f1130df5029b Mon Sep 17 00:00:00 2001
-From: Yunhui Cui <yunhui.cui at nxp.com>
-Date: Fri, 20 May 2016 16:37:34 +0800
-Subject: [PATCH 36/93] driver: spi: add exceed 16MB flash support
-
-Signed-off-by: Yunhui Cui <yunhui.cui at nxp.com>
----
- drivers/mtd/spi/spi_flash.c | 41 +++++++++++------------------------------
- 1 file changed, 11 insertions(+), 30 deletions(-)
-
-diff --git a/drivers/mtd/spi/spi_flash.c b/drivers/mtd/spi/spi_flash.c
-index 9d61ac0..e9d1c64 100644
---- a/drivers/mtd/spi/spi_flash.c
-+++ b/drivers/mtd/spi/spi_flash.c
-@@ -21,9 +21,9 @@
-
- DECLARE_GLOBAL_DATA_PTR;
-
--static void spi_flash_addr(u32 addr, u8 *cmd, u32 offset_ext)
-+static void spi_flash_addr(u32 addr, u8 *cmd)
- {
-- if (offset_ext >= SPI_FLASH_16MB_BOUN) {
-+ if (addr >= SPI_FLASH_16MB_BOUN) {
- /* cmd[0] is actual command */
- cmd[1] = addr >> 24;
- cmd[2] = addr >> 16;
-@@ -312,9 +312,7 @@ int spi_flash_cmd_erase_ops(struct spi_flash *flash, u32 offset, size_t len)
- u32 erase_size, erase_addr;
- u8 *cmd, cmdsz;
- int ret = -1;
-- u32 offset_ext;
-
-- offset_ext = offset;
- erase_size = flash->erase_size;
- if (offset % erase_size || len % erase_size) {
- debug("SF: Erase offset/length not multiple of erase size\n");
-@@ -329,10 +327,7 @@ int spi_flash_cmd_erase_ops(struct spi_flash *flash, u32 offset, size_t len)
- }
- }
-
-- if (offset > SPI_FLASH_16MB_BOUN)
-- cmdsz = SPI_FLASH_CMD_LEN_EXT + flash->dummy_byte;
-- else
-- cmdsz = SPI_FLASH_CMD_LEN + flash->dummy_byte;
-+ cmdsz = SPI_FLASH_CMD_LEN_EXT + flash->dummy_byte;
- cmd = calloc(1, cmdsz);
- if (!cmd) {
- debug("SF: Failed to allocate cmd\n");
-@@ -353,7 +348,7 @@ int spi_flash_cmd_erase_ops(struct spi_flash *flash, u32 offset, size_t len)
- if (ret < 0)
- return ret;
- #endif
-- spi_flash_addr(erase_addr, cmd, offset_ext);
-+ spi_flash_addr(erase_addr, cmd);
-
- debug("SF: erase %2x %2x %2x %2x (%x)\n", cmd[0], cmd[1],
- cmd[2], cmd[3], erase_addr);
-@@ -380,9 +375,7 @@ int spi_flash_cmd_write_ops(struct spi_flash *flash, u32 offset,
- size_t chunk_len, actual;
- u8 *cmd, cmdsz;
- int ret = -1;
-- u32 offset_ext;
-
-- offset_ext = offset;
- page_size = flash->page_size;
-
- if (flash->flash_is_locked) {
-@@ -393,10 +386,7 @@ int spi_flash_cmd_write_ops(struct spi_flash *flash, u32 offset,
- }
- }
-
-- if (offset > SPI_FLASH_16MB_BOUN)
-- cmdsz = SPI_FLASH_CMD_LEN_EXT + flash->dummy_byte;
-- else
-- cmdsz = SPI_FLASH_CMD_LEN + flash->dummy_byte;
-+ cmdsz = SPI_FLASH_CMD_LEN_EXT + flash->dummy_byte;
- cmd = calloc(1, cmdsz);
- if (!cmd) {
- debug("SF: Failed to allocate cmd\n");
-@@ -423,7 +413,7 @@ int spi_flash_cmd_write_ops(struct spi_flash *flash, u32 offset,
- chunk_len = min(chunk_len,
- (size_t)flash->spi->max_write_size);
-
-- spi_flash_addr(write_addr, cmd, offset_ext);
-+ spi_flash_addr(write_addr, cmd);
-
- debug("SF: 0x%p => cmd = { 0x%02x 0x%02x%02x%02x } chunk_len = %zu\n",
- buf + actual, cmd[0], cmd[1], cmd[2], cmd[3], chunk_len);
-@@ -477,9 +467,6 @@ int spi_flash_cmd_read_ops(struct spi_flash *flash, u32 offset,
- u32 remain_len, read_len, read_addr;
- int bank_sel = 0;
- int ret = -1;
-- u32 offset_ext;
--
-- offset_ext = offset;
-
- /* Handle memory-mapped SPI */
- if (flash->memory_map) {
-@@ -494,10 +481,8 @@ int spi_flash_cmd_read_ops(struct spi_flash *flash, u32 offset,
- spi_release_bus(flash->spi);
- return 0;
- }
-- if (offset > SPI_FLASH_16MB_BOUN)
-- cmdsz = SPI_FLASH_CMD_LEN_EXT + flash->dummy_byte;
-- else
-- cmdsz = SPI_FLASH_CMD_LEN + flash->dummy_byte;
-+
-+ cmdsz = SPI_FLASH_CMD_LEN_EXT + flash->dummy_byte;
- cmd = calloc(1, cmdsz);
- if (!cmd) {
- debug("SF: Failed to allocate cmd\n");
-@@ -508,7 +493,6 @@ int spi_flash_cmd_read_ops(struct spi_flash *flash, u32 offset,
-
- while (len) {
- read_addr = offset;
--
- #ifdef CONFIG_SF_DUAL_FLASH
- if (flash->dual_flash > SF_SINGLE_FLASH)
- spi_flash_dual(flash, &read_addr);
-@@ -519,18 +503,15 @@ int spi_flash_cmd_read_ops(struct spi_flash *flash, u32 offset,
- return ret;
- bank_sel = flash->bank_curr;
- #endif
-- if (offset_ext >= SPI_FLASH_16MB_BOUN) {
-- remain_len = flash->size - offset;
-- } else {
-- remain_len = ((SPI_FLASH_16MB_BOUN << flash->shift) *
-+ remain_len = ((flash->size << flash->shift) *
- (bank_sel + 1)) - offset;
-- }
-+
- if (len < remain_len)
- read_len = len;
- else
- read_len = remain_len;
-
-- spi_flash_addr(read_addr, cmd, offset_ext);
-+ spi_flash_addr(read_addr, cmd);
-
- ret = spi_flash_read_common(flash, cmd, cmdsz, data, read_len);
- if (ret < 0) {
---
-1.7.9.5
-
diff --git a/package/boot/uboot-layerscape/patches/0037-driver-spi-remove-Warning-prints-for-Spansion-FS-S-f.patch b/package/boot/uboot-layerscape/patches/0037-driver-spi-remove-Warning-prints-for-Spansion-FS-S-f.patch
deleted file mode 100644
index 981182b..0000000
--- a/package/boot/uboot-layerscape/patches/0037-driver-spi-remove-Warning-prints-for-Spansion-FS-S-f.patch
+++ /dev/null
@@ -1,60 +0,0 @@
-From 65a6669afc667dacacf24a3a3f340205e38b0c5d Mon Sep 17 00:00:00 2001
-From: Yunhui Cui <yunhui.cui at nxp.com>
-Date: Fri, 27 May 2016 10:25:09 +0800
-Subject: [PATCH 37/93] driver: spi: remove Warning prints for Spansion FS-S
- fmaily
-
-The Spansion flash FS-S family don't support the bank related
-commands, Even if flash size exceed 16MB, we cannot enable the
-macro CONFIG_SPI_FLASH_BAR. Also, we need remove the irrelevant
-warnings:
-"puts("SF: Warning - Only lower 16MiB accessible,"
-"Full access #define CONFIG_SPI_FLASH_BAR"
-
-Signed-off-by: Yunhui Cui <yunhui.cui at nxp.com>
----
- drivers/mtd/spi/spi_flash.c | 13 +++++++++----
- 1 file changed, 9 insertions(+), 4 deletions(-)
-
-diff --git a/drivers/mtd/spi/spi_flash.c b/drivers/mtd/spi/spi_flash.c
-index e9d1c64..b0f09ab 100644
---- a/drivers/mtd/spi/spi_flash.c
-+++ b/drivers/mtd/spi/spi_flash.c
-@@ -1009,6 +1009,9 @@ int spi_flash_scan(struct spi_flash *flash)
- u8 idcode[5];
- u8 cmd;
- int ret;
-+#ifdef CONFIG_SPI_FLASH_SPANSION
-+ u8 id[6];
-+#endif
-
- /* Read the ID codes */
- ret = spi_flash_cmd(spi, CMD_READ_ID, idcode, sizeof(idcode));
-@@ -1062,7 +1065,6 @@ int spi_flash_scan(struct spi_flash *flash)
- if ((jedec == 0x0219 || (jedec == 0x0220)) &&
- (ext_jedec & 0xff00) == 0x4d00) {
- int ret;
-- u8 id[6];
-
- /* Read the ID codes again, 6 bytes */
- ret = spi_flash_cmd(flash->spi, CMD_READ_ID, id, sizeof(id));
-@@ -1253,10 +1255,13 @@ int spi_flash_scan(struct spi_flash *flash)
- #endif
-
- #ifndef CONFIG_SPI_FLASH_BAR
-- if (((flash->dual_flash == SF_SINGLE_FLASH) &&
-- (flash->size > SPI_FLASH_16MB_BOUN)) ||
-+ if ((id[5] != 0x81) &&
-+ /*Spansion FS-S family not support BAR ,
-+ Even if CONFIG_SPI_FLASH_BAR is unable, Need not the Warning prints */
-+ ((((flash->dual_flash == SF_SINGLE_FLASH) &&
-+ (flash->size > SPI_FLASH_16MB_BOUN))) ||
- ((flash->dual_flash > SF_SINGLE_FLASH) &&
-- (flash->size > SPI_FLASH_16MB_BOUN << 1))) {
-+ (flash->size > SPI_FLASH_16MB_BOUN << 1)))) {
- puts("SF: Warning - Only lower 16MiB accessible,");
- puts(" Full access #define CONFIG_SPI_FLASH_BAR\n");
- }
---
-1.7.9.5
-
diff --git a/package/boot/uboot-layerscape/patches/0038-Shift-board-specific-configurations.patch b/package/boot/uboot-layerscape/patches/0038-Shift-board-specific-configurations.patch
deleted file mode 100644
index 1c1cc81..0000000
--- a/package/boot/uboot-layerscape/patches/0038-Shift-board-specific-configurations.patch
+++ /dev/null
@@ -1,228 +0,0 @@
-From 8f096adfd96941e596b5fbf30a21193e32f2c1b0 Mon Sep 17 00:00:00 2001
-From: Pratiyush Mohan Srivastava <pratiyush.srivastava at nxp.com>
-Date: Fri, 27 May 2016 15:10:40 +0530
-Subject: [PATCH 38/93] Shift board specific configurations
-
-Board specific configurations are moved from
-ls1012a_common.h to ls1012aqds.h and ls1012ardb.h
-
-Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha at nxp.com>
-Signed-off-by: Pratiyush Mohan Srivastava <pratiyush.srivastava at nxp.com>
----
- include/configs/ls1012a_common.h | 60 --------------------------------------
- include/configs/ls1012aqds.h | 58 ++++++++++++++++++++++++++++++++++++
- include/configs/ls1012ardb.h | 58 ++++++++++++++++++++++++++++++++++++
- 3 files changed, 116 insertions(+), 60 deletions(-)
-
-diff --git a/include/configs/ls1012a_common.h b/include/configs/ls1012a_common.h
-index 89d1370..07ef7c6 100644
---- a/include/configs/ls1012a_common.h
-+++ b/include/configs/ls1012a_common.h
-@@ -88,66 +88,6 @@
- #define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
- #endif /* CONFIG_EMU */
-
--/* MMC */
--#if !defined(CONFIG_EMU)
--#define CONFIG_MMC
--#ifdef CONFIG_MMC
--#define CONFIG_CMD_MMC
--#define CONFIG_FSL_ESDHC
--#define CONFIG_FSL_ESDHC_TWO_CONTROLLERS_SUPPORT
--#define CONFIG_FSL_ESDHC_1_NON_REMOVABLE_CARD
--#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
--#define CONFIG_GENERIC_MMC
--#define CONFIG_CMD_FAT
--#define CONFIG_DOS_PARTITION
--#endif
--#endif /* CONFIG_EMU */
--
--/* SATA */
--#if !defined(CONFIG_EMU)
--#define CONFIG_LIBATA
--#define CONFIG_SCSI_AHCI
--#define CONFIG_SCSI_AHCI_PLAT
--#define CONFIG_CMD_SCSI
--#define CONFIG_CMD_FAT
--#define CONFIG_CMD_EXT2
--#define CONFIG_DOS_PARTITION
--#define CONFIG_BOARD_LATE_INIT
--
--#define CONFIG_SYS_SATA AHCI_BASE_ADDR
--
--#define CONFIG_SYS_SCSI_MAX_SCSI_ID 1
--#define CONFIG_SYS_SCSI_MAX_LUN 1
--#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
-- CONFIG_SYS_SCSI_MAX_LUN)
--
--#define CONFIG_PCI /* Enable PCI/PCIE */
--#define CONFIG_PCIE1 /* PCIE controller 1 */
--#define CONFIG_PCIE_LAYERSCAPE /* Use common FSL Layerscape PCIe code */
--#define FSL_PCIE_COMPAT "fsl,ls1043a-pcie"
--
--#define CONFIG_SYS_PCI_64BIT
--
--#define CONFIG_SYS_PCIE_CFG0_PHYS_OFF 0x00000000
--#define CONFIG_SYS_PCIE_CFG0_SIZE 0x00001000 /* 4k */
--#define CONFIG_SYS_PCIE_CFG1_PHYS_OFF 0x00001000
--#define CONFIG_SYS_PCIE_CFG1_SIZE 0x00001000 /* 4k */
--
--#define CONFIG_SYS_PCIE_IO_BUS 0x00000000
--#define CONFIG_SYS_PCIE_IO_PHYS_OFF 0x00010000
--#define CONFIG_SYS_PCIE_IO_SIZE 0x00010000 /* 64k */
--
--#define CONFIG_SYS_PCIE_MEM_BUS 0x08000000
--#define CONFIG_SYS_PCIE_MEM_PHYS_OFF 0x04000000
--#define CONFIG_SYS_PCIE_MEM_SIZE 0x80000000 /* 128M */
--
--#define CONFIG_NET_MULTI
--#define CONFIG_PCI_PNP
--#define CONFIG_E1000
--#define CONFIG_PCI_SCAN_SHOW
--#define CONFIG_CMD_PCI
--#endif
--
- #define CONFIG_CONS_INDEX 1
- #define CONFIG_SYS_NS16550_SERIAL
- #define CONFIG_SYS_NS16550_REG_SIZE 1
-diff --git a/include/configs/ls1012aqds.h b/include/configs/ls1012aqds.h
-index de998b8..488811b 100644
---- a/include/configs/ls1012aqds.h
-+++ b/include/configs/ls1012aqds.h
-@@ -26,6 +26,64 @@
- #define SGMII_CARD_PORT4_PHY_ADDR 0x1F
- #endif
-
-+/* MMC */
-+#if !defined(CONFIG_EMU)
-+#define CONFIG_MMC
-+#ifdef CONFIG_MMC
-+#define CONFIG_CMD_MMC
-+#define CONFIG_FSL_ESDHC
-+#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
-+#define CONFIG_GENERIC_MMC
-+#define CONFIG_CMD_FAT
-+#define CONFIG_DOS_PARTITION
-+#endif
-+#endif /* CONFIG_EMU */
-+
-+/* SATA */
-+#if !defined(CONFIG_EMU)
-+#define CONFIG_LIBATA
-+#define CONFIG_SCSI_AHCI
-+#define CONFIG_SCSI_AHCI_PLAT
-+#define CONFIG_CMD_SCSI
-+#define CONFIG_CMD_FAT
-+#define CONFIG_CMD_EXT2
-+#define CONFIG_DOS_PARTITION
-+#define CONFIG_BOARD_LATE_INIT
-+
-+#define CONFIG_SYS_SATA AHCI_BASE_ADDR
-+
-+#define CONFIG_SYS_SCSI_MAX_SCSI_ID 1
-+#define CONFIG_SYS_SCSI_MAX_LUN 1
-+#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
-+ CONFIG_SYS_SCSI_MAX_LUN)
-+
-+#define CONFIG_PCI /* Enable PCI/PCIE */
-+#define CONFIG_PCIE1 /* PCIE controller 1 */
-+#define CONFIG_PCIE_LAYERSCAPE /* Use common FSL Layerscape PCIe code */
-+#define FSL_PCIE_COMPAT "fsl,ls1043a-pcie"
-+
-+#define CONFIG_SYS_PCI_64BIT
-+
-+#define CONFIG_SYS_PCIE_CFG0_PHYS_OFF 0x00000000
-+#define CONFIG_SYS_PCIE_CFG0_SIZE 0x00001000 /* 4k */
-+#define CONFIG_SYS_PCIE_CFG1_PHYS_OFF 0x00001000
-+#define CONFIG_SYS_PCIE_CFG1_SIZE 0x00001000 /* 4k */
-+
-+#define CONFIG_SYS_PCIE_IO_BUS 0x00000000
-+#define CONFIG_SYS_PCIE_IO_PHYS_OFF 0x00010000
-+#define CONFIG_SYS_PCIE_IO_SIZE 0x00010000 /* 64k */
-+
-+#define CONFIG_SYS_PCIE_MEM_BUS 0x08000000
-+#define CONFIG_SYS_PCIE_MEM_PHYS_OFF 0x04000000
-+#define CONFIG_SYS_PCIE_MEM_SIZE 0x80000000 /* 128M */
-+
-+#define CONFIG_NET_MULTI
-+#define CONFIG_PCI_PNP
-+#define CONFIG_E1000
-+#define CONFIG_PCI_SCAN_SHOW
-+#define CONFIG_CMD_PCI
-+#endif
-+
- /*
- * QIXIS Definitions
- */
-diff --git a/include/configs/ls1012ardb.h b/include/configs/ls1012ardb.h
-index b40e02b..1629e19 100644
---- a/include/configs/ls1012ardb.h
-+++ b/include/configs/ls1012ardb.h
-@@ -55,6 +55,64 @@
- #define CONFIG_CMD_USB_MASS_STORAGE
- #endif
-
-+/* MMC */
-+#if !defined(CONFIG_EMU)
-+#define CONFIG_MMC
-+#ifdef CONFIG_MMC
-+#define CONFIG_CMD_MMC
-+#define CONFIG_FSL_ESDHC
-+#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
-+#define CONFIG_GENERIC_MMC
-+#define CONFIG_CMD_FAT
-+#define CONFIG_DOS_PARTITION
-+#endif
-+#endif /* CONFIG_EMU */
-+
-+/* SATA */
-+#if !defined(CONFIG_EMU)
-+#define CONFIG_LIBATA
-+#define CONFIG_SCSI_AHCI
-+#define CONFIG_SCSI_AHCI_PLAT
-+#define CONFIG_CMD_SCSI
-+#define CONFIG_CMD_FAT
-+#define CONFIG_CMD_EXT2
-+#define CONFIG_DOS_PARTITION
-+#define CONFIG_BOARD_LATE_INIT
-+
-+#define CONFIG_SYS_SATA AHCI_BASE_ADDR
-+
-+#define CONFIG_SYS_SCSI_MAX_SCSI_ID 1
-+#define CONFIG_SYS_SCSI_MAX_LUN 1
-+#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
-+ CONFIG_SYS_SCSI_MAX_LUN)
-+
-+#define CONFIG_PCI /* Enable PCI/PCIE */
-+#define CONFIG_PCIE1 /* PCIE controller 1 */
-+#define CONFIG_PCIE_LAYERSCAPE /* Use common FSL Layerscape PCIe code */
-+#define FSL_PCIE_COMPAT "fsl,ls1043a-pcie"
-+
-+#define CONFIG_SYS_PCI_64BIT
-+
-+#define CONFIG_SYS_PCIE_CFG0_PHYS_OFF 0x00000000
-+#define CONFIG_SYS_PCIE_CFG0_SIZE 0x00001000 /* 4k */
-+#define CONFIG_SYS_PCIE_CFG1_PHYS_OFF 0x00001000
-+#define CONFIG_SYS_PCIE_CFG1_SIZE 0x00001000 /* 4k */
-+
-+#define CONFIG_SYS_PCIE_IO_BUS 0x00000000
-+#define CONFIG_SYS_PCIE_IO_PHYS_OFF 0x00010000
-+#define CONFIG_SYS_PCIE_IO_SIZE 0x00010000 /* 64k */
-+
-+#define CONFIG_SYS_PCIE_MEM_BUS 0x08000000
-+#define CONFIG_SYS_PCIE_MEM_PHYS_OFF 0x04000000
-+#define CONFIG_SYS_PCIE_MEM_SIZE 0x80000000 /* 128M */
-+
-+#define CONFIG_NET_MULTI
-+#define CONFIG_PCI_PNP
-+#define CONFIG_E1000
-+#define CONFIG_PCI_SCAN_SHOW
-+#define CONFIG_CMD_PCI
-+#endif
-+
- /*
- * I2C IO expander
- */
---
-1.7.9.5
-
diff --git a/package/boot/uboot-layerscape/patches/0039-armv8-ls1012a-Add-support-of-ls1012afrdm-board.patch b/package/boot/uboot-layerscape/patches/0039-armv8-ls1012a-Add-support-of-ls1012afrdm-board.patch
deleted file mode 100644
index 8df1d91..0000000
--- a/package/boot/uboot-layerscape/patches/0039-armv8-ls1012a-Add-support-of-ls1012afrdm-board.patch
+++ /dev/null
@@ -1,566 +0,0 @@
-From 6aaa5973b9ae8452a546e0666b2389bb163fb949 Mon Sep 17 00:00:00 2001
-From: Pratiyush Mohan Srivastava <pratiyush.srivastava at nxp.com>
-Date: Thu, 19 May 2016 16:45:27 +0530
-Subject: [PATCH 39/93] armv8: ls1012a: Add support of ls1012afrdm board
-
-QorIQ LS1012A FREEDOM (LS1012AFRDM) is a high-performance
-development platform, with a complete debugging environment.
-The LS1012AFRDM board supports the QorIQ LS1012A processor and is
-optimized to support the high-bandwidth DDR3L memory and
-a full complement of high-speed SerDes ports.
-
-Signed-off-by: Shengzhou Liu <Shengzhou.Liu at nxp.com>
-Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha at nxp.com>
-Signed-off-by: Calvin Johnson <calvin.johnson at nxp.com>
-Signed-off-by: Pratiyush Mohan Srivastava <pratiyush.srivastava at nxp.com>
----
- arch/arm/Kconfig | 10 ++
- arch/arm/dts/Makefile | 3 +-
- arch/arm/dts/fsl-ls1012a-frdm.dts | 16 +++
- arch/arm/dts/fsl-ls1012a-frdm.dtsi | 39 ++++++
- board/freescale/ls1012afrdm/Kconfig | 15 +++
- board/freescale/ls1012afrdm/MAINTAINERS | 6 +
- board/freescale/ls1012afrdm/Makefile | 7 ++
- board/freescale/ls1012afrdm/README | 94 +++++++++++++++
- board/freescale/ls1012afrdm/ls1012afrdm.c | 183 +++++++++++++++++++++++++++++
- configs/ls1012afrdm_qspi_defconfig | 10 ++
- include/configs/ls1012afrdm.h | 59 ++++++++++
- 11 files changed, 441 insertions(+), 1 deletion(-)
- create mode 100644 arch/arm/dts/fsl-ls1012a-frdm.dts
- create mode 100644 arch/arm/dts/fsl-ls1012a-frdm.dtsi
- create mode 100644 board/freescale/ls1012afrdm/Kconfig
- create mode 100644 board/freescale/ls1012afrdm/MAINTAINERS
- create mode 100644 board/freescale/ls1012afrdm/Makefile
- create mode 100644 board/freescale/ls1012afrdm/README
- create mode 100644 board/freescale/ls1012afrdm/ls1012afrdm.c
- create mode 100644 configs/ls1012afrdm_qspi_defconfig
- create mode 100644 include/configs/ls1012afrdm.h
-
-diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
-index b536684..23fce38 100644
---- a/arch/arm/Kconfig
-+++ b/arch/arm/Kconfig
-@@ -669,6 +669,15 @@ config TARGET_LS1012ARDB
- development platform that supports the QorIQ LS1012A
- Layerscape Architecture processor.
-
-+config TARGET_LS1012AFRDM
-+ bool "Support ls1012afrdm"
-+ select ARM64
-+ help
-+ Support for Freescale LS1012AFRDM platform.
-+ The LS1012A Freedom board (FRDM) is a high-performance
-+ development platform that supports the QorIQ LS1012A
-+ Layerscape Architecture processor.
-+
- config TARGET_LS1021AQDS
- bool "Support ls1021aqds"
- select CPU_V7
-@@ -816,6 +825,7 @@ source "board/freescale/ls1021atwr/Kconfig"
- source "board/freescale/ls1043ardb/Kconfig"
- source "board/freescale/ls1012aqds/Kconfig"
- source "board/freescale/ls1012ardb/Kconfig"
-+source "board/freescale/ls1012afrdm/Kconfig"
- source "board/freescale/mx23evk/Kconfig"
- source "board/freescale/mx25pdk/Kconfig"
- source "board/freescale/mx28evk/Kconfig"
-diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
-index 9e8137b..de023b4 100644
---- a/arch/arm/dts/Makefile
-+++ b/arch/arm/dts/Makefile
-@@ -96,7 +96,8 @@ dtb-$(CONFIG_FSL_LSCH2) += fsl-ls1043a-qds-duart.dtb \
- fsl-ls1043a-qds-lpuart.dtb \
- fsl-ls1043a-rdb.dtb \
- fsl-ls1012a-qds.dtb \
-- fsl-ls1012a-rdb.dtb
-+ fsl-ls1012a-rdb.dtb \
-+ fsl-ls1012a-frdm.dtb
-
- dtb-$(CONFIG_MACH_SUN4I) += \
- sun4i-a10-a1000.dtb \
-diff --git a/arch/arm/dts/fsl-ls1012a-frdm.dts b/arch/arm/dts/fsl-ls1012a-frdm.dts
-new file mode 100644
-index 0000000..3a06c0a
---- /dev/null
-+++ b/arch/arm/dts/fsl-ls1012a-frdm.dts
-@@ -0,0 +1,16 @@
-+/*
-+ * Device Tree file for Freescale Layerscape-1012A family SoC.
-+ *
-+ * Copyright (C) 2016, Freescale Semiconductor
-+ *
-+ * SPDX-License-Identifier: GPL-2.0+
-+ */
-+
-+/dts-v1/;
-+#include "fsl-ls1012a-frdm.dtsi"
-+
-+/ {
-+ chosen {
-+ stdout-path = &duart0;
-+ };
-+};
-diff --git a/arch/arm/dts/fsl-ls1012a-frdm.dtsi b/arch/arm/dts/fsl-ls1012a-frdm.dtsi
-new file mode 100644
-index 0000000..9f0db91
---- /dev/null
-+++ b/arch/arm/dts/fsl-ls1012a-frdm.dtsi
-@@ -0,0 +1,39 @@
-+/*
-+ * Device Tree Include file for Freescale Layerscape-1012A family SoC.
-+ *
-+ * Copyright (C) 2016, Freescale Semiconductor
-+ *
-+ * This file is licensed under the terms of the GNU General Public
-+ * License version 2. This program is licensed "as is" without any
-+ * warranty of any kind, whether express or implied.
-+ */
-+
-+/include/ "fsl-ls1012a.dtsi"
-+
-+/ {
-+ model = "LS1012A FREEDOM Board";
-+ aliases {
-+ spi0 = &qspi;
-+ };
-+};
-+
-+&qspi {
-+ bus-num = <0>;
-+ status = "okay";
-+
-+ qflash0: s25fl128s at 0 {
-+ #address-cells = <1>;
-+ #size-cells = <1>;
-+ compatible = "spi-flash";
-+ spi-max-frequency = <20000000>;
-+ reg = <0>;
-+ };
-+};
-+
-+&i2c0 {
-+ status = "okay";
-+};
-+
-+&duart0 {
-+ status = "okay";
-+};
-diff --git a/board/freescale/ls1012afrdm/Kconfig b/board/freescale/ls1012afrdm/Kconfig
-new file mode 100644
-index 0000000..a34521c
---- /dev/null
-+++ b/board/freescale/ls1012afrdm/Kconfig
-@@ -0,0 +1,15 @@
-+if TARGET_LS1012AFRDM
-+
-+config SYS_BOARD
-+ default "ls1012afrdm"
-+
-+config SYS_VENDOR
-+ default "freescale"
-+
-+config SYS_SOC
-+ default "fsl-layerscape"
-+
-+config SYS_CONFIG_NAME
-+ default "ls1012afrdm"
-+
-+endif
-diff --git a/board/freescale/ls1012afrdm/MAINTAINERS b/board/freescale/ls1012afrdm/MAINTAINERS
-new file mode 100644
-index 0000000..2f31d0f
---- /dev/null
-+++ b/board/freescale/ls1012afrdm/MAINTAINERS
-@@ -0,0 +1,6 @@
-+LS1012AFRDM BOARD
-+M: Prabhakar Kushwaha <prabhakar.kushwaha at nxp.com>
-+S: Maintained
-+F: board/freescale/ls1012afrdm/
-+F: include/configs/ls1012afrdm.h
-+F: configs/ls1012afrdm_defconfig
-diff --git a/board/freescale/ls1012afrdm/Makefile b/board/freescale/ls1012afrdm/Makefile
-new file mode 100644
-index 0000000..dbfa2ce
---- /dev/null
-+++ b/board/freescale/ls1012afrdm/Makefile
-@@ -0,0 +1,7 @@
-+#
-+# Copyright 2016 Freescale Semiconductor, Inc.
-+#
-+# SPDX-License-Identifier: GPL-2.0+
-+#
-+
-+obj-y += ls1012afrdm.o
-diff --git a/board/freescale/ls1012afrdm/README b/board/freescale/ls1012afrdm/README
-new file mode 100644
-index 0000000..0aadbb1
---- /dev/null
-+++ b/board/freescale/ls1012afrdm/README
-@@ -0,0 +1,94 @@
-+Overview
-+--------
-+The LS1012AFRDM power supplies (PS) provide all the voltages necessary
-+for the correct operation of the LS1012A processor, DDR3L, QSPI memory,
-+and other onboard peripherals.
-+
-+LS1012A SoC Overview
-+--------------------
-+The LS1012A features an advanced 64-bit ARM v8 Cortex-
-+A53 processor, with 32 KB of parity protected L1-I cache,
-+32 KB of ECC protected L1-D cache, as well as 256 KB of
-+ECC protected L2 cache.
-+
-+The LS1012A SoC includes the following function and features:
-+ - One 64-bit ARM v8 Cortex-A53 core with the following capabilities:
-+ - ARM v8 cryptography extensions
-+ - One 16-bit DDR3L SDRAM memory controller, Up to 1.0 GT/s, Supports
-+ 16-/8-bit operation (no ECC support)
-+ - ARM core-link CCI-400 cache coherent interconnect
-+ - Packet Forwarding Engine (PFE)
-+ - Cryptography acceleration (SEC)
-+ - Ethernet interfaces supported by PFE:
-+ - One Configurable x3 SerDes:
-+ Two Serdes PLLs supported for usage by any SerDes data lane
-+ Support for up to 6 GBaud operation
-+ - High-speed peripheral interfaces:
-+ - One PCI Express Gen2 controller, supporting x1 operation
-+ - One serial ATA (SATA Gen 3.0) controller
-+ - One USB 3.0/2.0 controller with integrated PHY
-+ - One USB 2.0 controller with ULPI interface. .
-+ - Additional peripheral interfaces:
-+ - One quad serial peripheral interface (QuadSPI) controller
-+ - One serial peripheral interface (SPI) controller
-+ - Two enhanced secure digital host controllers
-+ - Two I2C controllers
-+ - One 16550 compliant DUART (two UART interfaces)
-+ - Two general purpose IOs (GPIO)
-+ - Two FlexTimers
-+ - Five synchronous audio interfaces (SAI)
-+ - Pre-boot loader (PBL) provides pre-boot initialization and RCW loading
-+ - Single-source clocking solution enabling generation of core, platform,
-+ DDR, SerDes, and USB clocks from a single external crystal and internal
-+ crystaloscillator
-+ - Thermal monitor unit (TMU) with +/- 3C accuracy
-+ - Two WatchDog timers
-+ - ARM generic timer
-+ - QorIQ platform's trust architecture 2.1
-+
-+ LS1012AFRDM board Overview
-+ -----------------------
-+ - SERDES Connections, 2 lanes supportingspeeds upto 1 Gbit/s
-+ - 2 SGMII 1G PHYs
-+ - DDR Controller
-+ - 4 Gb DDR3L SDRAM memory, running at data rates up to 1 GT/s
-+ operating at 1.35 V
-+ - QSPI
-+ - Onboard 512 Mbit QSPI flash memory running at speed up
-+ to 108/54 MHz
-+ - One high-speed USB 2.0/3.0 port, one USB 2.0 port
-+ - USB 2.0/3.0 port is configured as On-The-Go (OTG) with a
-+ Micro-AB connector.
-+ - USB 2.0 port is a debug port (CMSIS DAP) and is configured
-+ as a Micro-AB device.
-+ - I2C controller
-+ - One I2C bus with connectivity to Arduino headers
-+ - UART
-+ - UART (Console): UART1 (Without flow control) for console
-+ - ARM JTAG support
-+ - ARM Cortex® 10-pin JTAG connector for LS1012A
-+ - CMSIS DAP through K20 microcontroller
-+ - SAI Audio interface
-+ - One SAI port, SAI 2 with full duplex support
-+ - Clocks
-+ - 25 MHz crystal for LS1012A
-+ - 8 MHz Crystal for K20
-+ - 24 MHz for SC16IS740IPW SPI to Dual UART bridge
-+ - Power Supplies
-+ - 5 V input supply from USB
-+ - 0.9 V, 1.35 V, and 1.8 V for VDD/Core, DDR, I/O, and
-+ other board interfaces
-+
-+Booting Options
-+---------------
-+a) QSPI Flash 1
-+
-+QSPI flash map
-+--------------
-+Images | Size |QSPI Flash Address
-+------------------------------------------
-+RCW + PBI | 1MB | 0x4000_0000
-+U-boot | 1MB | 0x4010_0000
-+U-boot Env | 1MB | 0x4020_0000
-+PPA FIT image | 2MB | 0x4050_0000
-+Linux ITB | ~53MB | 0x40A0_0000
-diff --git a/board/freescale/ls1012afrdm/ls1012afrdm.c b/board/freescale/ls1012afrdm/ls1012afrdm.c
-new file mode 100644
-index 0000000..6be8951
---- /dev/null
-+++ b/board/freescale/ls1012afrdm/ls1012afrdm.c
-@@ -0,0 +1,183 @@
-+/*
-+ * Copyright 2016 Freescale Semiconductor, Inc.
-+ *
-+ * SPDX-License-Identifier: GPL-2.0+
-+ */
-+
-+#include <common.h>
-+#include <i2c.h>
-+#include <asm/io.h>
-+#include <asm/arch/clock.h>
-+#include <asm/arch/fsl_serdes.h>
-+#include <asm/arch/ppa.h>
-+#include <asm/arch/soc.h>
-+#include <hwconfig.h>
-+#include <ahci.h>
-+#include <mmc.h>
-+#include <scsi.h>
-+#include <fsl_csu.h>
-+#include <fsl_esdhc.h>
-+#include <environment.h>
-+#include <fsl_mmdc.h>
-+#include <netdev.h>
-+
-+DECLARE_GLOBAL_DATA_PTR;
-+
-+static void set_wait_for_bits_clear(void *ptr, u32 value, u32 bits)
-+{
-+ int timeout = 1000;
-+
-+ out_be32(ptr, value);
-+
-+ while (in_be32(ptr) & bits) {
-+ udelay(100);
-+ timeout--;
-+ }
-+ if (timeout <= 0)
-+ puts("Error: wait for clear timeout.\n");
-+}
-+
-+int checkboard(void)
-+{
-+ puts("Board: LS1012AFRDM ");
-+
-+ return 0;
-+}
-+
-+void mmdc_init(void)
-+{
-+ struct mmdc_p_regs *mmdc =
-+ (struct mmdc_p_regs *)CONFIG_SYS_FSL_DDR_ADDR;
-+
-+ /* Set MMDC_MDSCR[CON_REQ] */
-+ out_be32(&mmdc->mdscr, 0x00008000);
-+
-+ /* configure timing parms */
-+ out_be32(&mmdc->mdotc, 0x12554000);
-+ out_be32(&mmdc->mdcfg0, 0xbabf7954);
-+ out_be32(&mmdc->mdcfg1, 0xff328f64);
-+ out_be32(&mmdc->mdcfg2, 0x01ff00db);
-+
-+ /* other parms */
-+ out_be32(&mmdc->mdmisc, 0x00000680);
-+ out_be32(&mmdc->mpmur0, 0x00000800);
-+ out_be32(&mmdc->mdrwd, 0x00002000);
-+ out_be32(&mmdc->mpodtctrl, 0x0000022a);
-+
-+ /* out of reset delays */
-+ out_be32(&mmdc->mdor, 0x00bf1023);
-+
-+ /* physical parms */
-+ out_be32(&mmdc->mdctl, 0x04180000);
-+ out_be32(&mmdc->mdasp, 0x0000007f);
-+
-+ /* Enable MMDC */
-+ out_be32(&mmdc->mdctl, 0x84180000);
-+
-+ /* dram init sequence: update MRs */
-+ out_be32(&mmdc->mdscr, 0x00088032);
-+ out_be32(&mmdc->mdscr, 0x00008033);
-+ out_be32(&mmdc->mdscr, 0x00048031);
-+ out_be32(&mmdc->mdscr, 0x19308030);
-+
-+ /* dram init sequence: ZQCL */
-+ out_be32(&mmdc->mdscr, 0x04008040);
-+ set_wait_for_bits_clear(&mmdc->mpzqhwctrl, 0xa1390003, 0x00010000);
-+
-+ /* Calibrations now: wr lvl */
-+ out_be32(&mmdc->mdscr, 0x00848031);
-+ out_be32(&mmdc->mdscr, 0x00008200);
-+ set_wait_for_bits_clear(&mmdc->mpwlgcr, 0x00000001, 0x00000001);
-+
-+ mdelay(1);
-+
-+ out_be32(&mmdc->mdscr, 0x00048031);
-+ out_be32(&mmdc->mdscr, 0x00008000);
-+
-+ mdelay(1);
-+
-+ /* Calibrations now: Read DQS gating calibration */
-+ out_be32(&mmdc->mdscr, 0x04008050);
-+ out_be32(&mmdc->mdscr, 0x00048033);
-+ out_be32(&mmdc->mppdcmpr2, 0x00000001);
-+ out_be32(&mmdc->mprddlctl, 0x40404040);
-+ set_wait_for_bits_clear(&mmdc->mpdgctrl0, 0x10000000, 0x10000000);
-+
-+ out_be32(&mmdc->mdscr, 0x00008033);
-+
-+ /* Calibrations now: Read calibration */
-+ out_be32(&mmdc->mdscr, 0x04008050);
-+ out_be32(&mmdc->mdscr, 0x00048033);
-+ out_be32(&mmdc->mppdcmpr2, 0x00000001);
-+ set_wait_for_bits_clear(&mmdc->mprddlhwctl, 0x00000010, 0x00000010);
-+
-+ out_be32(&mmdc->mdscr, 0x00008033);
-+
-+ /* PD, SR */
-+ out_be32(&mmdc->mdpdc, 0x00030035);
-+ out_be32(&mmdc->mapsr, 0x00001067);
-+
-+ /* refresh scheme */
-+ set_wait_for_bits_clear(&mmdc->mdref, 0x103e8000, 0x00000001);
-+
-+ /* disable CON_REQ */
-+ out_be32(&mmdc->mdscr, 0x0);
-+}
-+
-+int dram_init(void)
-+{
-+ mmdc_init();
-+
-+ gd->ram_size = 0x20000000;
-+
-+ return 0;
-+}
-+
-+int board_eth_init(bd_t *bis)
-+{
-+ return pci_eth_init(bis);
-+}
-+
-+int board_early_init_f(void)
-+{
-+ fsl_lsch2_early_init_f();
-+
-+ return 0;
-+}
-+
-+int board_init(void)
-+{
-+ struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
-+ /*
-+ * Set CCI-400 control override register to enable barrier
-+ * transaction
-+ */
-+ out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER);
-+
-+#ifdef CONFIG_ENV_IS_NOWHERE
-+ gd->env_addr = (ulong)&default_environment[0];
-+#endif
-+
-+#ifdef CONFIG_LAYERSCAPE_NS_ACCESS
-+ enable_layerscape_ns_access();
-+#endif
-+
-+ return 0;
-+}
-+
-+int ft_board_setup(void *blob, bd_t *bd)
-+{
-+ u64 base[CONFIG_NR_DRAM_BANKS];
-+ u64 size[CONFIG_NR_DRAM_BANKS];
-+
-+ /* fixup DT for the two DDR banks */
-+ base[0] = gd->bd->bi_dram[0].start;
-+ size[0] = gd->bd->bi_dram[0].size;
-+ base[1] = gd->bd->bi_dram[1].start;
-+ size[1] = gd->bd->bi_dram[1].size;
-+
-+ fdt_fixup_memory_banks(blob, base, size, 2);
-+ ft_cpu_setup(blob, bd);
-+
-+ return 0;
-+}
-diff --git a/configs/ls1012afrdm_qspi_defconfig b/configs/ls1012afrdm_qspi_defconfig
-new file mode 100644
-index 0000000..e27181c
---- /dev/null
-+++ b/configs/ls1012afrdm_qspi_defconfig
-@@ -0,0 +1,10 @@
-+CONFIG_ARM=y
-+CONFIG_TARGET_LS1012AFRDM=y
-+CONFIG_SYS_EXTRA_OPTIONS="QSPI_BOOT"
-+# CONFIG_CMD_IMLS is not set
-+CONFIG_SYS_NS16550=y
-+CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1012a-frdm"
-+CONFIG_OF_CONTROL=y
-+CONFIG_DM=y
-+CONFIG_SPI_FLASH=y
-+CONFIG_DM_SPI=y
-diff --git a/include/configs/ls1012afrdm.h b/include/configs/ls1012afrdm.h
-new file mode 100644
-index 0000000..3231ab7
---- /dev/null
-+++ b/include/configs/ls1012afrdm.h
-@@ -0,0 +1,59 @@
-+/*
-+ * Copyright 2016 Freescale Semiconductor, Inc.
-+ *
-+ * SPDX-License-Identifier: GPL-2.0+
-+ */
-+
-+#ifndef __LS1012ARDB_H__
-+#define __LS1012ARDB_H__
-+
-+#include "ls1012a_common.h"
-+
-+#define CONFIG_DIMM_SLOTS_PER_CTLR 1
-+#define CONFIG_CHIP_SELECTS_PER_CTRL 1
-+#define CONFIG_NR_DRAM_BANKS 2
-+
-+#define CONFIG_CMD_MEMINFO
-+#define CONFIG_CMD_MEMTEST
-+#define CONFIG_SYS_MEMTEST_START 0x80000000
-+#define CONFIG_SYS_MEMTEST_END 0x9fffffff
-+
-+#define CONFIG_PHYLIB
-+#define CONFIG_PHY_REALTEK
-+/*
-+* USB
-+*/
-+#define CONFIG_HAS_FSL_XHCI_USB
-+
-+#ifdef CONFIG_HAS_FSL_XHCI_USB
-+#define CONFIG_USB_XHCI
-+#define CONFIG_USB_XHCI_FSL
-+#define CONFIG_USB_XHCI_DWC3
-+#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
-+#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2
-+#define CONFIG_CMD_USB
-+#define CONFIG_USB_STORAGE
-+#define CONFIG_CMD_EXT2
-+
-+#define CONFIG_USB_DWC3
-+#define CONFIG_USB_DWC3_GADGET
-+
-+#define CONFIG_USB_GADGET
-+#define CONFIG_USB_FUNCTION_MASS_STORAGE
-+#define CONFIG_USB_GADGET_DOWNLOAD
-+#define CONFIG_USB_GADGET_VBUS_DRAW 2
-+#define CONFIG_G_DNL_MANUFACTURER "NXP Semiconductor"
-+#define CONFIG_G_DNL_VENDOR_NUM 0x1234
-+#define CONFIG_G_DNL_PRODUCT_NUM 0x1234
-+#define CONFIG_USB_GADGET_DUALSPEED
-+
-+/* USB Gadget ums command */
-+#define CONFIG_CMD_USB_MASS_STORAGE
-+#endif
-+
-+#define CONFIG_CMD_MEMINFO
-+#define CONFIG_CMD_MEMTEST
-+#define CONFIG_SYS_MEMTEST_START 0x80000000
-+#define CONFIG_SYS_MEMTEST_END 0x9fffffff
-+
-+#endif /* __LS1012ARDB_H__ */
---
-1.7.9.5
-
diff --git a/package/boot/uboot-layerscape/patches/0040-DNCPE-138-CSU-config-for-PFE.patch b/package/boot/uboot-layerscape/patches/0040-DNCPE-138-CSU-config-for-PFE.patch
deleted file mode 100644
index f77f8fa..0000000
--- a/package/boot/uboot-layerscape/patches/0040-DNCPE-138-CSU-config-for-PFE.patch
+++ /dev/null
@@ -1,36 +0,0 @@
-From 0bfcfaafa23af0e8c9ae9df3236831fcaaa597b8 Mon Sep 17 00:00:00 2001
-From: Anji J <anji.jagarlmudi at freescale.com>
-Date: Mon, 4 Apr 2016 15:07:47 +0530
-Subject: [PATCH 40/93] DNCPE-138 CSU config for PFE
-
-Configure PFE for NS access.
-
-Signed-off-by: Anjaneyulu Jagarlmudi <anji.jagarlmudi at nxp.com>>
-Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha at nxp.com>
----
- .../include/asm/arch-fsl-layerscape/ns_access.h | 2 ++
- 1 file changed, 2 insertions(+)
-
-diff --git a/arch/arm/include/asm/arch-fsl-layerscape/ns_access.h b/arch/arm/include/asm/arch-fsl-layerscape/ns_access.h
-index 2fd33e1..5250ac7 100644
---- a/arch/arm/include/asm/arch-fsl-layerscape/ns_access.h
-+++ b/arch/arm/include/asm/arch-fsl-layerscape/ns_access.h
-@@ -25,6 +25,7 @@ enum csu_cslx_ind {
- CSU_CSLX_PCIE3_IO,
- CSU_CSLX_USB3 = 20,
- CSU_CSLX_USB2,
-+ CSU_CSLX_PFE = 23,
- CSU_CSLX_SERDES = 32,
- CSU_CSLX_QDMA,
- CSU_CSLX_LPUART2,
-@@ -105,6 +106,7 @@ static struct csu_ns_dev ns_dev[] = {
- {CSU_CSLX_PCIE3_IO, CSU_ALL_RW},
- {CSU_CSLX_USB3, CSU_ALL_RW},
- {CSU_CSLX_USB2, CSU_ALL_RW},
-+ {CSU_CSLX_PFE, CSU_ALL_RW},
- {CSU_CSLX_SERDES, CSU_ALL_RW},
- {CSU_CSLX_QDMA, CSU_ALL_RW},
- {CSU_CSLX_LPUART2, CSU_ALL_RW},
---
-1.7.9.5
-
diff --git a/package/boot/uboot-layerscape/patches/0041-DNCPE-4-LS1012A-PPFE-driver.patch b/package/boot/uboot-layerscape/patches/0041-DNCPE-4-LS1012A-PPFE-driver.patch
deleted file mode 100644
index f2b157c..0000000
--- a/package/boot/uboot-layerscape/patches/0041-DNCPE-4-LS1012A-PPFE-driver.patch
+++ /dev/null
@@ -1,7589 +0,0 @@
-From 487b9b2e5c767ee2110cce57539f0ebeb5a74872 Mon Sep 17 00:00:00 2001
-From: Prabhakar Kushwaha <prabhakar.kushwaha at nxp.com>
-Date: Tue, 24 May 2016 14:05:18 +0530
-Subject: [PATCH 41/93] DNCPE-4: LS1012A PPFE driver
-
-[context adjustment]
-
-- Ported PFE driver from LS1024
-- Did changes for GEMAC/MDIO/PHY
-- LS1012A address translation changes
-- Added pfe command to the U-boot.
-- Added gemac_stat command
-- Added config PFE_START to conditionally start pfe on bootup time.
-- Change Rx packet ack model
-- Class firmware changes to ignore Rx error status
-
-- SCFG changes for pfe
-- Configure CCI-400 QoS settings
-- Configure transaction attributes
-- Configure RGMII port config
-
-Testing status on board
-
-RGMII - Works fine, can download file through tftp.
-SGMII - CRC errors are seen, but basic rx/tx works.
-
-Signed-off-by: Anjaneyulu Jagarlmudi <anji.jagarlmudi at nxp.com>>
-Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha at nxp.com>
-Integrated-by: Jiang Yutang <yutang.jiang at nxp.com>
----
- arch/arm/cpu/armv8/fsl-layerscape/cpu.c | 5 +
- .../include/asm/arch-fsl-layerscape/immap_lsch2.h | 42 +-
- board/freescale/ls1012aqds/Makefile | 1 +
- board/freescale/ls1012aqds/eth.c | 199 +++
- board/freescale/ls1012aqds/ls1012aqds.c | 5 -
- board/freescale/ls1012aqds/ls1012aqds.h | 149 ++
- board/freescale/ls1012aqds/ls1012aqds_qixis.h | 2 +-
- board/freescale/ls1012ardb/Makefile | 1 +
- board/freescale/ls1012ardb/eth.c | 68 +
- board/freescale/ls1012ardb/ls1012ardb.c | 4 -
- common/Makefile | 2 +
- common/cmd_gemac_stat.c | 147 ++
- common/cmd_pfe_commands.c | 983 ++++++++++++
- drivers/net/Makefile | 1 +
- drivers/net/pfe_eth/Makefile | 1 +
- drivers/net/pfe_eth/class_sbl_elf.fw | 1 +
- drivers/net/pfe_eth/hal.h | 64 +
- drivers/net/pfe_eth/pfe.c | 1677 ++++++++++++++++++++
- drivers/net/pfe_eth/pfe/cbus.h | 74 +
- drivers/net/pfe_eth/pfe/cbus/bmu.h | 37 +
- drivers/net/pfe_eth/pfe/cbus/class_csr.h | 206 +++
- drivers/net/pfe_eth/pfe/cbus/emac.h | 232 +++
- drivers/net/pfe_eth/pfe/cbus/gpi.h | 60 +
- drivers/net/pfe_eth/pfe/cbus/gpt.h | 11 +
- drivers/net/pfe_eth/pfe/cbus/hif.h | 62 +
- drivers/net/pfe_eth/pfe/cbus/hif_nocpy.h | 33 +
- drivers/net/pfe_eth/pfe/cbus/tmu_csr.h | 102 ++
- drivers/net/pfe_eth/pfe/cbus/util_csr.h | 43 +
- drivers/net/pfe_eth/pfe/class.h | 142 ++
- drivers/net/pfe_eth/pfe/class/ccu.h | 10 +
- drivers/net/pfe_eth/pfe/class/efet.h | 21 +
- drivers/net/pfe_eth/pfe/class/mac_hash.h | 28 +
- drivers/net/pfe_eth/pfe/class/perg.h | 21 +
- drivers/net/pfe_eth/pfe/class/vlan_hash.h | 28 +
- drivers/net/pfe_eth/pfe/gpt.h | 11 +
- drivers/net/pfe_eth/pfe/pe.h | 147 ++
- drivers/net/pfe_eth/pfe/pfe.h | 250 +++
- drivers/net/pfe_eth/pfe/tmu.h | 48 +
- drivers/net/pfe_eth/pfe/tmu/phy_queue.h | 31 +
- drivers/net/pfe_eth/pfe/tmu/sched.h | 47 +
- drivers/net/pfe_eth/pfe/tmu/shaper.h | 19 +
- drivers/net/pfe_eth/pfe/uart.h | 13 +
- drivers/net/pfe_eth/pfe/util.h | 30 +
- drivers/net/pfe_eth/pfe/util/eape.h | 10 +
- drivers/net/pfe_eth/pfe/util/efet.h | 20 +
- drivers/net/pfe_eth/pfe/util/inq.h | 10 +
- drivers/net/pfe_eth/pfe_driver.c | 710 +++++++++
- drivers/net/pfe_eth/pfe_driver.h | 141 ++
- drivers/net/pfe_eth/pfe_eth.c | 521 ++++++
- drivers/net/pfe_eth/pfe_eth.h | 161 ++
- drivers/net/pfe_eth/pfe_firmware.c | 193 +++
- drivers/net/pfe_eth/pfe_firmware.h | 20 +
- drivers/net/pfe_eth/pfe_mod.h | 140 ++
- drivers/net/pfe_eth/tmu_sbl_elf.fw | 1 +
- drivers/net/pfe_eth/util_sbl_elf.fw | 1 +
- include/configs/ls1012a_common.h | 10 +
- include/configs/ls1012aqds.h | 13 +-
- include/configs/ls1012ardb.h | 6 +-
- 58 files changed, 6994 insertions(+), 21 deletions(-)
- create mode 100644 board/freescale/ls1012aqds/eth.c
- create mode 100644 board/freescale/ls1012aqds/ls1012aqds.h
- create mode 100644 board/freescale/ls1012ardb/eth.c
- create mode 100644 common/cmd_gemac_stat.c
- create mode 100644 common/cmd_pfe_commands.c
- create mode 100644 drivers/net/pfe_eth/Makefile
- create mode 100644 drivers/net/pfe_eth/class_sbl_elf.fw
- create mode 100644 drivers/net/pfe_eth/hal.h
- create mode 100644 drivers/net/pfe_eth/pfe.c
- create mode 100644 drivers/net/pfe_eth/pfe/cbus.h
- create mode 100644 drivers/net/pfe_eth/pfe/cbus/bmu.h
- create mode 100644 drivers/net/pfe_eth/pfe/cbus/class_csr.h
- create mode 100644 drivers/net/pfe_eth/pfe/cbus/emac.h
- create mode 100644 drivers/net/pfe_eth/pfe/cbus/gpi.h
- create mode 100644 drivers/net/pfe_eth/pfe/cbus/gpt.h
- create mode 100644 drivers/net/pfe_eth/pfe/cbus/hif.h
- create mode 100644 drivers/net/pfe_eth/pfe/cbus/hif_nocpy.h
- create mode 100644 drivers/net/pfe_eth/pfe/cbus/tmu_csr.h
- create mode 100644 drivers/net/pfe_eth/pfe/cbus/util_csr.h
- create mode 100644 drivers/net/pfe_eth/pfe/class.h
- create mode 100644 drivers/net/pfe_eth/pfe/class/ccu.h
- create mode 100644 drivers/net/pfe_eth/pfe/class/efet.h
- create mode 100644 drivers/net/pfe_eth/pfe/class/mac_hash.h
- create mode 100644 drivers/net/pfe_eth/pfe/class/perg.h
- create mode 100644 drivers/net/pfe_eth/pfe/class/vlan_hash.h
- create mode 100644 drivers/net/pfe_eth/pfe/gpt.h
- create mode 100644 drivers/net/pfe_eth/pfe/pe.h
- create mode 100644 drivers/net/pfe_eth/pfe/pfe.h
- create mode 100644 drivers/net/pfe_eth/pfe/tmu.h
- create mode 100644 drivers/net/pfe_eth/pfe/tmu/phy_queue.h
- create mode 100644 drivers/net/pfe_eth/pfe/tmu/sched.h
- create mode 100644 drivers/net/pfe_eth/pfe/tmu/shaper.h
- create mode 100644 drivers/net/pfe_eth/pfe/uart.h
- create mode 100644 drivers/net/pfe_eth/pfe/util.h
- create mode 100644 drivers/net/pfe_eth/pfe/util/eape.h
- create mode 100644 drivers/net/pfe_eth/pfe/util/efet.h
- create mode 100644 drivers/net/pfe_eth/pfe/util/inq.h
- create mode 100644 drivers/net/pfe_eth/pfe_driver.c
- create mode 100644 drivers/net/pfe_eth/pfe_driver.h
- create mode 100644 drivers/net/pfe_eth/pfe_eth.c
- create mode 100644 drivers/net/pfe_eth/pfe_eth.h
- create mode 100644 drivers/net/pfe_eth/pfe_firmware.c
- create mode 100644 drivers/net/pfe_eth/pfe_firmware.h
- create mode 100644 drivers/net/pfe_eth/pfe_mod.h
- create mode 100644 drivers/net/pfe_eth/tmu_sbl_elf.fw
- create mode 100644 drivers/net/pfe_eth/util_sbl_elf.fw
-
-diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
-index 340d9f9..8f59577 100644
---- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
-+++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
-@@ -573,6 +573,11 @@ int cpu_eth_init(bd_t *bis)
- {
- int error = 0;
-
-+#if defined(CONFIG_FSL_PPFE) && !defined(CONFIG_CMD_PFE_START)
-+ ls1012a_gemac_initialize(bis, 0 , "pfe_eth0");
-+ ls1012a_gemac_initialize(bis, 1 , "pfe_eth1");
-+#endif
-+
- #ifdef CONFIG_FSL_MC_ENET
- error = fsl_mc_ldpaa_init(bis);
- #endif
-diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
-index 6918757..a264f9a 100644
---- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
-+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
-@@ -41,6 +41,7 @@
- #define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_IMMR + 0x2400000)
- #define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_IMMR + 0x2500000)
- #define CONFIG_SYS_PCIE3_ADDR (CONFIG_SYS_IMMR + 0x2600000)
-+#define CONFIG_SYS_PPFE_ADDR (CONFIG_SYS_IMMR + 0x3000000)
- #define CONFIG_SYS_SEC_MON_ADDR (CONFIG_SYS_IMMR + 0xe90000)
- #define CONFIG_SYS_SFP_ADDR (CONFIG_SYS_IMMR + 0xe80200)
-
-@@ -364,6 +365,24 @@ struct ccsr_gur {
- #define SCFG_SNPCNFGCR_USB3RDSNP 0x00002000
- #define SCFG_SNPCNFGCR_USB3WRSNP 0x00004000
-
-+/* RGMIIPCR bit definitions*/
-+#define SCFG_RGMIIPCR_EN_AUTO (0x00000008)
-+#define SCFG_RGMIIPCR_SETSP_1000M (0x00000004)
-+#define SCFG_RGMIIPCR_SETSP_100M (0x00000000)
-+#define SCFG_RGMIIPCR_SETSP_10M (0x00000002)
-+#define SCFG_RGMIIPCR_SETFD (0x00000001)
-+
-+/*PFEASBCR bit definitions */
-+#define SCFG_PPFEASBCR_ARCACHE0 (0x80000000)
-+#define SCFG_PPFEASBCR_AWCACHE0 (0x40000000)
-+#define SCFG_PPFEASBCR_ARCACHE1 (0x20000000)
-+#define SCFG_PPFEASBCR_AWCACHE1 (0x10000000)
-+#define SCFG_PPFEASBCR_ARSNP (0x08000000)
-+#define SCFG_PPFEASBCR_AWSNP (0x04000000)
-+
-+
-+
-+
- /* Supplemental Configuration Unit */
- struct ccsr_scfg {
- u8 res_000[0x100-0x000];
-@@ -381,7 +400,12 @@ struct ccsr_scfg {
- u8 res_140[0x158-0x140];
- u32 altcbar;
- u32 qspi_cfg;
-- u8 res_160[0x180-0x160];
-+ u8 res_160[0x164-0x160];
-+ u32 wr_qos1;
-+ u32 wr_qos2;
-+ u32 rd_qos1;
-+ u32 rd_qos2;
-+ u8 res_174[0x180-0x174];
- u32 dmamcr;
- u8 res_184[0x18c-0x184];
- u32 debug_icid;
-@@ -411,7 +435,21 @@ struct ccsr_scfg {
- u32 usb_refclk_selcr1;
- u32 usb_refclk_selcr2;
- u32 usb_refclk_selcr3;
-- u8 res_424[0x600-0x424];
-+ u8 res_424[0x434-0x424];
-+ u32 rgmiipcr;
-+ u32 res_438;
-+ u32 rgmiipsr;
-+ u32 pfepfcssr1;
-+ u32 pfeintencr1;
-+ u32 pfepfcssr2;
-+ u32 pfeintencr2;
-+ u32 pfeerrcr;
-+ u32 pfeeerrintencr;
-+ u32 pfeasbcr;
-+ u32 pfebsbcr;
-+ u8 res_460[0x484-0x460];
-+ u32 mdioselcr;
-+ u8 res_468[0x600-0x468];
- u32 scratchrw[4];
- u8 res_610[0x680-0x610];
- u32 corebcr;
-diff --git a/board/freescale/ls1012aqds/Makefile b/board/freescale/ls1012aqds/Makefile
-index 0b813f9..b18494a 100644
---- a/board/freescale/ls1012aqds/Makefile
-+++ b/board/freescale/ls1012aqds/Makefile
-@@ -5,3 +5,4 @@
- #
-
- obj-y += ls1012aqds.o
-+obj-y += eth.o
-diff --git a/board/freescale/ls1012aqds/eth.c b/board/freescale/ls1012aqds/eth.c
-new file mode 100644
-index 0000000..1bd7c9d
---- /dev/null
-+++ b/board/freescale/ls1012aqds/eth.c
-@@ -0,0 +1,199 @@
-+/*
-+ * Copyright 2016 Freescale Semiconductor, Inc.
-+ *
-+ * SPDX-License-Identifier: GPL-2.0+
-+ */
-+
-+#include <common.h>
-+#include <asm/io.h>
-+#include <netdev.h>
-+#include <fm_eth.h>
-+#include <fsl_mdio.h>
-+#include <malloc.h>
-+#include <fsl_dtsec.h>
-+#include <asm/arch/soc.h>
-+#include <asm/arch-fsl-layerscape/config.h>
-+#include <asm/arch/fsl_serdes.h>
-+
-+#include "../common/qixis.h"
-+#include "../../../drivers/net/pfe_eth/pfe_eth.h"
-+#include "ls1012aqds_qixis.h"
-+#include <asm/arch-fsl-layerscape/immap_lsch2.h>
-+
-+#define EMI_NONE 0xFF
-+#define EMI1_RGMII 1
-+#define EMI1_SLOT1 2
-+#define EMI1_SLOT2 3
-+
-+#define DEFAULT_PFE_MDIO_NAME "PFE_MDIO"
-+
-+static int mdio_mux[NUM_FM_PORTS];
-+
-+static const char * const mdio_names[] = {
-+ "NULL",
-+ "LS1012AQDS_MDIO_RGMII",
-+ "LS1012AQDS_MDIO_SLOT1",
-+ "LS1012AQDS_MDIO_SLOT2",
-+ "NULL",
-+};
-+
-+static const char *ls1012aqds_mdio_name_for_muxval(u8 muxval)
-+{
-+ return mdio_names[muxval];
-+}
-+
-+struct ls1012aqds_mdio {
-+ u8 muxval;
-+ struct mii_dev *realbus;
-+};
-+
-+static void ls1012aqds_mux_mdio(u8 muxval)
-+{
-+ u8 brdcfg4;
-+
-+ if (muxval < 7) {
-+ brdcfg4 = QIXIS_READ(brdcfg[4]);
-+ brdcfg4 &= ~BRDCFG4_EMISEL_MASK;
-+ brdcfg4 |= (muxval << BRDCFG4_EMISEL_SHIFT);
-+ QIXIS_WRITE(brdcfg[4], brdcfg4);
-+ }
-+}
-+
-+static int ls1012aqds_mdio_read(struct mii_dev *bus, int addr, int devad,
-+ int regnum)
-+{
-+ struct ls1012aqds_mdio *priv = bus->priv;
-+
-+ ls1012aqds_mux_mdio(priv->muxval);
-+
-+ return priv->realbus->read(priv->realbus, addr, devad, regnum);
-+}
-+
-+static int ls1012aqds_mdio_write(struct mii_dev *bus, int addr, int devad,
-+ int regnum, u16 value)
-+{
-+ struct ls1012aqds_mdio *priv = bus->priv;
-+
-+ ls1012aqds_mux_mdio(priv->muxval);
-+
-+ return priv->realbus->write(priv->realbus, addr, devad, regnum, value);
-+}
-+
-+static int ls1012aqds_mdio_reset(struct mii_dev *bus)
-+{
-+ struct ls1012aqds_mdio *priv = bus->priv;
-+
-+ if(priv->realbus->reset)
-+ return priv->realbus->reset(priv->realbus);
-+}
-+
-+static int ls1012aqds_mdio_init(char *realbusname, u8 muxval)
-+{
-+ struct ls1012aqds_mdio *pmdio;
-+ struct mii_dev *bus = mdio_alloc();
-+
-+ if (!bus) {
-+ printf("Failed to allocate ls1012aqds MDIO bus\n");
-+ return -1;
-+ }
-+
-+ pmdio = malloc(sizeof(*pmdio));
-+ if (!pmdio) {
-+ printf("Failed to allocate ls1012aqds private data\n");
-+ free(bus);
-+ return -1;
-+ }
-+
-+ bus->read = ls1012aqds_mdio_read;
-+ bus->write = ls1012aqds_mdio_write;
-+ bus->reset = ls1012aqds_mdio_reset;
-+ sprintf(bus->name, ls1012aqds_mdio_name_for_muxval(muxval));
-+
-+ pmdio->realbus = miiphy_get_dev_by_name(realbusname);
-+
-+ if (!pmdio->realbus) {
-+ printf("No bus with name %s\n", realbusname);
-+ free(bus);
-+ free(pmdio);
-+ return -1;
-+ }
-+
-+ pmdio->muxval = muxval;
-+ bus->priv = pmdio;
-+ return mdio_register(bus);
-+}
-+
-+int board_eth_init(bd_t *bis)
-+{
-+#ifdef CONFIG_FSL_PPFE
-+ struct mii_dev *bus;
-+ struct mdio_info mac1_mdio_info;
-+ struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
-+ u8 data8;
-+
-+
-+ /*TODO Following config should be done for all boards, where is the right place to put this */
-+ out_be32(&scfg->pfeasbcr, in_be32(&scfg->pfeasbcr) | SCFG_PPFEASBCR_AWCACHE0);
-+ out_be32(&scfg->pfebsbcr, in_be32(&scfg->pfebsbcr) | SCFG_PPFEASBCR_AWCACHE0);
-+
-+ /*CCI-400 QoS settings for PFE */
-+ out_be32(&scfg->wr_qos1, 0x0ff00000);
-+ out_be32(&scfg->rd_qos1, 0x0ff00000);
-+
-+ /* Set RGMII into 1G + Full duplex mode */
-+ out_be32(&scfg->rgmiipcr, in_be32(&scfg->rgmiipcr) | (SCFG_RGMIIPCR_SETSP_1000M | SCFG_RGMIIPCR_SETFD));
-+
-+ out_be32((CONFIG_SYS_DCSR_DCFG_ADDR + 0x520), 0xFFFFFFFF);
-+ out_be32((CONFIG_SYS_DCSR_DCFG_ADDR + 0x524), 0xFFFFFFFF);
-+
-+ ls1012aqds_mux_mdio(2);
-+
-+#ifdef RGMII_RESET_WA
-+ /* Work around for FPGA registers initialization
-+ * This is needed for RGMII to work */
-+ printf("Reset RGMII WA....\n");
-+ data8 = QIXIS_READ(rst_frc[0]);
-+ data8 |= 0x2;
-+ QIXIS_WRITE(rst_frc[0], data8);
-+ data8 = QIXIS_READ(rst_frc[0]);
-+
-+ data8 = QIXIS_READ(res8[6]);
-+ data8 |= 0xff;
-+ QIXIS_WRITE(res8[6], data8);
-+ data8 = QIXIS_READ(res8[6]);
-+
-+#endif
-+
-+ mac1_mdio_info.reg_base = (void *)0x04200000; /*EMAC1_BASE_ADDR*/
-+ mac1_mdio_info.name = DEFAULT_PFE_MDIO_NAME;
-+
-+ bus = ls1012a_mdio_init(&mac1_mdio_info);
-+ if(!bus)
-+ {
-+ printf("Failed to register mdio \n");
-+ return -1;
-+ }
-+
-+ /*Based on RCW config initialize correctly */
-+ /*MAC2 */
-+ if(ls1012aqds_mdio_init(DEFAULT_PFE_MDIO_NAME, EMI1_RGMII) < 0)
-+ {
-+ printf("Failed to register mdio for %s\n", ls1012aqds_mdio_name_for_muxval(EMI1_RGMII));
-+ return -1;
-+ }
-+ ls1012a_set_mdio(1, miiphy_get_dev_by_name(ls1012aqds_mdio_name_for_muxval(EMI1_RGMII)));
-+ ls1012a_set_phy_address_mode(1, EMAC2_PHY_ADDR, PHY_INTERFACE_MODE_RGMII);
-+
-+ /*MAC1 */
-+ if(ls1012aqds_mdio_init(DEFAULT_PFE_MDIO_NAME, EMI1_SLOT1) < 0)
-+ {
-+ printf("Failed to register mdio for %s\n", ls1012aqds_mdio_name_for_muxval(EMI1_SLOT1));
-+ return -1;
-+ }
-+ ls1012a_set_mdio(0, miiphy_get_dev_by_name(ls1012aqds_mdio_name_for_muxval(EMI1_SLOT1)));
-+ ls1012a_set_phy_address_mode(0, EMAC1_PHY_ADDR, PHY_INTERFACE_MODE_SGMII);
-+
-+ cpu_eth_init(bis);
-+#endif
-+ return pci_eth_init(bis);
-+}
-diff --git a/board/freescale/ls1012aqds/ls1012aqds.c b/board/freescale/ls1012aqds/ls1012aqds.c
-index 446989b..b7365e8 100644
---- a/board/freescale/ls1012aqds/ls1012aqds.c
-+++ b/board/freescale/ls1012aqds/ls1012aqds.c
-@@ -211,11 +211,6 @@ int board_init(void)
- return 0;
- }
-
--int board_eth_init(bd_t *bis)
--{
-- return pci_eth_init(bis);
--}
--
- #ifdef CONFIG_OF_BOARD_SETUP
- int ft_board_setup(void *blob, bd_t *bd)
- {
-diff --git a/board/freescale/ls1012aqds/ls1012aqds.h b/board/freescale/ls1012aqds/ls1012aqds.h
-new file mode 100644
-index 0000000..42e10f5
---- /dev/null
-+++ b/board/freescale/ls1012aqds/ls1012aqds.h
-@@ -0,0 +1,149 @@
-+/*
-+ * Copyright 2016 Freescale Semiconductor, Inc.
-+ *
-+ * SPDX-License-Identifier: GPL-2.0+
-+ */
-+
-+#ifndef __LS1012AQDS_H__
-+#define __LS1012AQDS_H__
-+
-+#include "ls1012a_common.h"
-+
-+
-+#define CONFIG_DIMM_SLOTS_PER_CTLR 1
-+#define CONFIG_CHIP_SELECTS_PER_CTRL 1
-+#define CONFIG_NR_DRAM_BANKS 2
-+
-+#ifdef CONFIG_FSL_PPFE
-+/*#define CONFIG_CMD_PFE_START */
-+#define EMAC1_PHY_ADDR 0x1e
-+#define EMAC2_PHY_ADDR 0x1
-+#define CONFIG_PHYLIB
-+#define CONFIG_PHY_VITESSE
-+#define CONFIG_PHY_REALTEK
-+#endif
-+
-+#define CONFIG_QIXIS_I2C_ACCESS
-+#define CONFIG_SYS_I2C_FPGA_ADDR 0x66
-+
-+/*
-+ * I2C bus multiplexer
-+ */
-+#define I2C_MUX_PCA_ADDR_PRI 0x77
-+#define I2C_MUX_PCA_ADDR_SEC 0x76 /* Secondary multiplexer */
-+#define I2C_RETIMER_ADDR 0x18
-+#define I2C_MUX_CH_DEFAULT 0x8
-+#define I2C_MUX_CH_CH7301 0xC
-+#define I2C_MUX_CH5 0xD
-+#define I2C_MUX_CH7 0xF
-+
-+#define I2C_MUX_CH_VOL_MONITOR 0xa
-+
-+/*
-+* RTC configuration
-+*/
-+#define RTC
-+#define CONFIG_RTC_PCF8563 1
-+#define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* Channel 3*/
-+#define CONFIG_CMD_DATE
-+
-+/* EEPROM */
-+#define CONFIG_ID_EEPROM
-+#define CONFIG_CMD_EEPROM
-+#define CONFIG_SYS_I2C_EEPROM_NXID
-+#define CONFIG_SYS_EEPROM_BUS_NUM 0
-+#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
-+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
-+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
-+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
-+
-+
-+/* Voltage monitor on channel 2*/
-+#define I2C_VOL_MONITOR_ADDR 0x40
-+#define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2
-+#define I2C_VOL_MONITOR_BUS_V_OVF 0x1
-+#define I2C_VOL_MONITOR_BUS_V_SHIFT 3
-+
-+
-+/* DSPI */
-+#define CONFIG_FSL_DSPI
-+#define CONFIG_FSL_DSPI1
-+#define CONFIG_DEFAULT_SPI_BUS 1
-+
-+#define CONFIG_CMD_SPI
-+#define MMAP_DSPI DSPI1_BASE_ADDR
-+
-+#define CONFIG_SYS_DSPI_CTAR0 1
-+
-+#define CONFIG_SYS_DSPI_CTAR1 (DSPI_CTAR_TRSZ(7) | DSPI_CTAR_PCSSCK_1CLK |\
-+ DSPI_CTAR_PASC(0) | DSPI_CTAR_PDT(0) | \
-+ DSPI_CTAR_CSSCK(2) | DSPI_CTAR_ASC(0) | \
-+ DSPI_CTAR_DT(0))
-+#define CONFIG_SPI_FLASH_SST /* cs1 */
-+
-+#define CONFIG_SYS_DSPI_CTAR2 (DSPI_CTAR_TRSZ(7) | DSPI_CTAR_PCSSCK_1CLK |\
-+ DSPI_CTAR_PASC(0) | DSPI_CTAR_PDT(0) | \
-+ DSPI_CTAR_CSSCK(0) | DSPI_CTAR_ASC(0) | \
-+ DSPI_CTAR_DT(0))
-+#define CONFIG_SPI_FLASH_STMICRO /* cs2 */
-+
-+#define CONFIG_SYS_DSPI_CTAR3 (DSPI_CTAR_TRSZ(7) | DSPI_CTAR_PCSSCK_1CLK |\
-+ DSPI_CTAR_PASC(0) | DSPI_CTAR_PDT(0) | \
-+ DSPI_CTAR_CSSCK(2) | DSPI_CTAR_ASC(0) | \
-+ DSPI_CTAR_DT(0))
-+#define CONFIG_SPI_FLASH_EON /* cs3 */
-+
-+#define CONFIG_SF_DEFAULT_SPEED 10000000
-+#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
-+#define CONFIG_SF_DEFAULT_BUS 1
-+#define CONFIG_SF_DEFAULT_CS 0
-+
-+/*
-+* USB
-+*/
-+/* EHCI Support - disbaled by default */
-+/*#define CONFIG_HAS_FSL_DR_USB*/
-+
-+#ifdef CONFIG_HAS_FSL_DR_USB
-+#define CONFIG_USB_EHCI
-+#define CONFIG_USB_EHCI_FSL
-+#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
-+#endif
-+
-+/*XHCI Support - enabled by default*/
-+#define CONFIG_HAS_FSL_XHCI_USB
-+
-+#ifdef CONFIG_HAS_FSL_XHCI_USB
-+#define CONFIG_USB_XHCI
-+#define CONFIG_USB_XHCI_FSL
-+#define CONFIG_USB_XHCI_DWC3
-+#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
-+#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2
-+#define CONFIG_CMD_USB
-+#define CONFIG_USB_STORAGE
-+#define CONFIG_CMD_EXT2
-+
-+#define CONFIG_USB_DWC3
-+#define CONFIG_USB_DWC3_GADGET
-+
-+#define CONFIG_USB_GADGET
-+#define CONFIG_USB_FUNCTION_MASS_STORAGE
-+#define CONFIG_USB_GADGET_DOWNLOAD
-+#define CONFIG_USB_GADGET_VBUS_DRAW 2
-+#define CONFIG_G_DNL_MANUFACTURER "NXP Semiconductor"
-+#define CONFIG_G_DNL_VENDOR_NUM 0x1234
-+#define CONFIG_G_DNL_PRODUCT_NUM 0x1234
-+#define CONFIG_USB_GADGET_DUALSPEED
-+
-+/* USB Gadget ums command */
-+#define CONFIG_CMD_USB_MASS_STORAGE
-+#endif
-+
-+#define CONFIG_CMD_MEMINFO
-+#define CONFIG_CMD_MEMTEST
-+#define CONFIG_SYS_MEMTEST_START 0x80000000
-+#define CONFIG_SYS_MEMTEST_END 0x9fffffff
-+
-+#define CONFIG_MISC_INIT_R
-+
-+#endif /* __LS1012AQDS_H__ */
-diff --git a/board/freescale/ls1012aqds/ls1012aqds_qixis.h b/board/freescale/ls1012aqds/ls1012aqds_qixis.h
-index 584f604..7a1ba3d 100644
---- a/board/freescale/ls1012aqds/ls1012aqds_qixis.h
-+++ b/board/freescale/ls1012aqds/ls1012aqds_qixis.h
-@@ -11,7 +11,7 @@
-
- /* BRDCFG4[4:7] select EC1 and EC2 as a pair */
- #define BRDCFG4_EMISEL_MASK 0xe0
--#define BRDCFG4_EMISEL_SHIFT 5
-+#define BRDCFG4_EMISEL_SHIFT 6
-
- /* SYSCLK */
- #define QIXIS_SYSCLK_66 0x0
-diff --git a/board/freescale/ls1012ardb/Makefile b/board/freescale/ls1012ardb/Makefile
-index 05fa9d9..bd80ce5 100644
---- a/board/freescale/ls1012ardb/Makefile
-+++ b/board/freescale/ls1012ardb/Makefile
-@@ -5,3 +5,4 @@
- #
-
- obj-y += ls1012ardb.o
-+obj-y += eth.o
-diff --git a/board/freescale/ls1012ardb/eth.c b/board/freescale/ls1012ardb/eth.c
-new file mode 100644
-index 0000000..29830e8
---- /dev/null
-+++ b/board/freescale/ls1012ardb/eth.c
-@@ -0,0 +1,68 @@
-+/*
-+ * Copyright 2016 Freescale Semiconductor, Inc.
-+ *
-+ * SPDX-License-Identifier: GPL-2.0+
-+ */
-+
-+#include <common.h>
-+#include <asm/io.h>
-+#include <netdev.h>
-+#include <fm_eth.h>
-+#include <fsl_mdio.h>
-+#include <malloc.h>
-+#include <fsl_dtsec.h>
-+#include <asm/arch/soc.h>
-+#include <asm/arch-fsl-layerscape/config.h>
-+#include <asm/arch/fsl_serdes.h>
-+
-+#include "../../../drivers/net/pfe_eth/pfe_eth.h"
-+#include <asm/arch-fsl-layerscape/immap_lsch2.h>
-+
-+#define DEFAULT_PFE_MDIO_NAME "PFE_MDIO"
-+
-+int board_eth_init(bd_t *bis)
-+{
-+#ifdef CONFIG_FSL_PPFE
-+ struct mii_dev *bus;
-+ struct mdio_info mac1_mdio_info;
-+ struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
-+
-+
-+ /*TODO Following config should be done for all boards, where is the right place to put this */
-+ out_be32(&scfg->pfeasbcr, in_be32(&scfg->pfeasbcr) | SCFG_PPFEASBCR_AWCACHE0);
-+ out_be32(&scfg->pfebsbcr, in_be32(&scfg->pfebsbcr) | SCFG_PPFEASBCR_AWCACHE0);
-+
-+ /*CCI-400 QoS settings for PFE */
-+ out_be32(&scfg->wr_qos1, 0x0ff00000);
-+ out_be32(&scfg->rd_qos1, 0x0ff00000);
-+
-+ /* Set RGMII into 1G + Full duplex mode */
-+ out_be32(&scfg->rgmiipcr, in_be32(&scfg->rgmiipcr) | (SCFG_RGMIIPCR_SETSP_1000M | SCFG_RGMIIPCR_SETFD));
-+
-+
-+ out_be32((CONFIG_SYS_DCSR_DCFG_ADDR + 0x520), 0xFFFFFFFF);
-+ out_be32((CONFIG_SYS_DCSR_DCFG_ADDR + 0x524), 0xFFFFFFFF);
-+
-+ mac1_mdio_info.reg_base = (void *)0x04200000; /*EMAC1_BASE_ADDR*/
-+ mac1_mdio_info.name = DEFAULT_PFE_MDIO_NAME;
-+
-+ bus = ls1012a_mdio_init(&mac1_mdio_info);
-+ if(!bus)
-+ {
-+ printf("Failed to register mdio \n");
-+ return -1;
-+ }
-+
-+ /*MAC1 */
-+ ls1012a_set_mdio(0, miiphy_get_dev_by_name(DEFAULT_PFE_MDIO_NAME));
-+ ls1012a_set_phy_address_mode(0, EMAC1_PHY_ADDR, PHY_INTERFACE_MODE_SGMII);
-+
-+ /*MAC2 */
-+ ls1012a_set_mdio(1, miiphy_get_dev_by_name(DEFAULT_PFE_MDIO_NAME));
-+ ls1012a_set_phy_address_mode(1, EMAC2_PHY_ADDR, PHY_INTERFACE_MODE_RGMII);
-+
-+
-+ cpu_eth_init(bis);
-+#endif
-+ return pci_eth_init(bis);
-+}
-diff --git a/board/freescale/ls1012ardb/ls1012ardb.c b/board/freescale/ls1012ardb/ls1012ardb.c
-index 347b8c8..90cbd5e 100644
---- a/board/freescale/ls1012ardb/ls1012ardb.c
-+++ b/board/freescale/ls1012ardb/ls1012ardb.c
-@@ -163,10 +163,6 @@ int dram_init(void)
- return 0;
- }
-
--int board_eth_init(bd_t *bis)
--{
-- return pci_eth_init(bis);
--}
-
- int board_early_init_f(void)
- {
-diff --git a/common/Makefile b/common/Makefile
-index 2a1d9f8..f5db77e 100644
---- a/common/Makefile
-+++ b/common/Makefile
-@@ -136,6 +136,8 @@ obj-$(CONFIG_CMD_MII) += cmd_mii.o
- ifdef CONFIG_PHYLIB
- obj-$(CONFIG_CMD_MII) += cmd_mdio.o
- endif
-+obj-$(CONFIG_CMD_PFE_COMMANDS) += cmd_pfe_commands.o
-+obj-$(CONFIG_CMD_PFE_COMMANDS) += cmd_gemac_stat.o
- obj-$(CONFIG_CMD_MISC) += cmd_misc.o
- obj-$(CONFIG_CMD_MMC) += cmd_mmc.o
- obj-$(CONFIG_CMD_MMC_SPI) += cmd_mmc_spi.o
-diff --git a/common/cmd_gemac_stat.c b/common/cmd_gemac_stat.c
-new file mode 100644
-index 0000000..49bb1aa
---- /dev/null
-+++ b/common/cmd_gemac_stat.c
-@@ -0,0 +1,147 @@
-+/*
-+ * (C) Copyright 2003
-+ * Author : Laurent Brando (Mindspeed Technologies)
-+ *
-+ * See file CREDITS for list of people who contributed to this
-+ * project.
-+ *
-+ * This program is free software; you can redistribute it and/or
-+ * modify it under the terms of the GNU General Public License as
-+ * published by the Free Software Foundation; either version 2 of
-+ * the License, or (at your option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program; if not, write to the Free Software
-+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-+ * MA 02111-1307 USA
-+ */
-+
-+/**
-+ * @file
-+ * @brief Retrieve GEMAC Statistics
-+ */
-+
-+#include <common.h>
-+#include <command.h>
-+#include "../drivers/net/pfe_eth/pfe_eth.h"
-+#include "../drivers/net/pfe_eth/pfe/pfe.h"
-+#include "../drivers/net/pfe_eth/pfe_firmware.h"
-+#include "../drivers/net/pfe_eth/pfe/cbus.h"
-+#include "../drivers/net/pfe_eth/pfe/cbus/class_csr.h"
-+#include "../drivers/net/pfe_eth/pfe/cbus/emac.h"
-+
-+#define ETH_GSTRING_LEN 32 /* from linux/include/ethtool.h */
-+
-+static const struct fec_stat {
-+ char name[ETH_GSTRING_LEN];
-+ u16 offset;
-+} fec_stats[] = {
-+ /* RMON TX */
-+ { "tx_dropped", RMON_T_DROP },
-+ { "tx_packets", RMON_T_PACKETS },
-+ { "tx_broadcast", RMON_T_BC_PKT },
-+ { "tx_multicast", RMON_T_MC_PKT },
-+ { "tx_crc_errors", RMON_T_CRC_ALIGN },
-+ { "tx_undersize", RMON_T_UNDERSIZE },
-+ { "tx_oversize", RMON_T_OVERSIZE },
-+ { "tx_fragment", RMON_T_FRAG },
-+ { "tx_jabber", RMON_T_JAB },
-+ { "tx_collision", RMON_T_COL },
-+ { "tx_64byte", RMON_T_P64 },
-+ { "tx_65to127byte", RMON_T_P65TO127 },
-+ { "tx_128to255byte", RMON_T_P128TO255 },
-+ { "tx_256to511byte", RMON_T_P256TO511 },
-+ { "tx_512to1023byte", RMON_T_P512TO1023 },
-+ { "tx_1024to2047byte", RMON_T_P1024TO2047 },
-+ { "tx_GTE2048byte", RMON_T_P_GTE2048 },
-+ { "tx_octets", RMON_T_OCTETS },
-+
-+ /* IEEE TX */
-+ { "IEEE_tx_drop", IEEE_T_DROP },
-+ { "IEEE_tx_frame_ok", IEEE_T_FRAME_OK },
-+ { "IEEE_tx_1col", IEEE_T_1COL },
-+ { "IEEE_tx_mcol", IEEE_T_MCOL },
-+ { "IEEE_tx_def", IEEE_T_DEF },
-+ { "IEEE_tx_lcol", IEEE_T_LCOL },
-+ { "IEEE_tx_excol", IEEE_T_EXCOL },
-+ { "IEEE_tx_macerr", IEEE_T_MACERR },
-+ { "IEEE_tx_cserr", IEEE_T_CSERR },
-+ { "IEEE_tx_sqe", IEEE_T_SQE },
-+ { "IEEE_tx_fdxfc", IEEE_T_FDXFC },
-+ { "IEEE_tx_octets_ok", IEEE_T_OCTETS_OK },
-+
-+ /* RMON RX */
-+ { "rx_packets", RMON_R_PACKETS },
-+ { "rx_broadcast", RMON_R_BC_PKT },
-+ { "rx_multicast", RMON_R_MC_PKT },
-+ { "rx_crc_errors", RMON_R_CRC_ALIGN },
-+ { "rx_undersize", RMON_R_UNDERSIZE },
-+ { "rx_oversize", RMON_R_OVERSIZE },
-+ { "rx_fragment", RMON_R_FRAG },
-+ { "rx_jabber", RMON_R_JAB },
-+ { "rx_64byte", RMON_R_P64 },
-+ { "rx_65to127byte", RMON_R_P65TO127 },
-+ { "rx_128to255byte", RMON_R_P128TO255 },
-+ { "rx_256to511byte", RMON_R_P256TO511 },
-+ { "rx_512to1023byte", RMON_R_P512TO1023 },
-+ { "rx_1024to2047byte", RMON_R_P1024TO2047 },
-+ { "rx_GTE2048byte", RMON_R_P_GTE2048 },
-+ { "rx_octets", RMON_R_OCTETS },
-+
-+ /* IEEE RX */
-+ { "IEEE_rx_drop", IEEE_R_DROP },
-+ { "IEEE_rx_frame_ok", IEEE_R_FRAME_OK },
-+ { "IEEE_rx_crc", IEEE_R_CRC },
-+ { "IEEE_rx_align", IEEE_R_ALIGN },
-+ { "IEEE_rx_macerr", IEEE_R_MACERR },
-+ { "IEEE_rx_fdxfc", IEEE_R_FDXFC },
-+ { "IEEE_rx_octets_ok", IEEE_R_OCTETS_OK },
-+};
-+
-+static void ls1012a_emac_print_stats(void *base)
-+{
-+ int i;
-+
-+ for (i = 0; i < ARRAY_SIZE(fec_stats); i++)
-+ printf("%s: %d\n", fec_stats[i].name, readl(base + fec_stats[i].offset));
-+}
-+
-+static int gemac_stats(cmd_tbl_t *cmdtp, int flag, int argc,
-+ char * const argv[])
-+{
-+ void *gemac_base = NULL;
-+
-+ if (argc != 2) {
-+ printf("Usage: \n" "gemac_stat [ethx]\n");
-+ return CMD_RET_SUCCESS;
-+ }
-+
-+ if ( strcmp(argv[1], "eth0") == 0)
-+ gemac_base = (void *)EMAC1_BASE_ADDR;
-+ else if ( strcmp(argv[1], "eth1") == 0)
-+ gemac_base = (void *)EMAC2_BASE_ADDR;
-+
-+ if (gemac_base)
-+ {
-+ ls1012a_emac_print_stats(gemac_base);
-+ }
-+ else
-+ {
-+ printf("no such net device: %s\n", argv[1]);
-+ return 1;
-+ }
-+
-+ return 0;
-+}
-+
-+U_BOOT_CMD(
-+ gemac_stat, 2, 1, gemac_stats,
-+ "retrieve GEMAC statistics",
-+ "Usage: \n"
-+ "gemac_stat [ethx]\n"
-+);
-diff --git a/common/cmd_pfe_commands.c b/common/cmd_pfe_commands.c
-new file mode 100644
-index 0000000..f9f92c7
---- /dev/null
-+++ b/common/cmd_pfe_commands.c
-@@ -0,0 +1,983 @@
-+/*
-+ * (C) Copyright 2012
-+ * Author : Bill Westland (Mindspeed Technologies)
-+ *
-+ * See file CREDITS for list of people who contributed to this
-+ * project.
-+ *
-+ * This program is free software; you can redistribute it and/or
-+ * modify it under the terms of the GNU General Public License as
-+ * published by the Free Software Foundation; either version 2 of
-+ * the License, or (at your option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program; if not, write to the Free Software
-+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-+ * MA 02111-1307 USA
-+ */
-+
-+/**
-+ * @file
-+ * @brief PFE utility commands
-+ */
-+
-+#include <common.h>
-+#include <command.h>
-+#include "../drivers/net/pfe_eth/pfe_eth.h"
-+#include "../drivers/net/pfe_eth/pfe/pfe.h"
-+#include "../drivers/net/pfe_eth/pfe_firmware.h"
-+#include "../drivers/net/pfe_eth/pfe/cbus/class_csr.h"
-+#include "../drivers/net/pfe_eth/pfe/cbus/gpi.h"
-+DECLARE_GLOBAL_DATA_PTR;
-+
-+int pfe_load_elf(int pe_mask, const struct firmware *fw);
-+int ls1012a_gemac_initialize(bd_t * bis, int dev_id, char *devname);
-+
-+static void pfe_command_help(void)
-+{
-+ printf("Usage: pfe [start | firmware | load | lib | pe | gemac | gem | gpi | class | tmu | util | hif | status | expt | fftest] <options>\n");
-+}
-+
-+static void pfe_command_firmware(int argc, char * const argv[])
-+{
-+ if (argc == 3 && strcmp(argv[2], "init") == 0)
-+ {
-+ pfe_firmware_init((u8 *)0x80100000, (u8 *)0x80180000, (u8 *)0x80200000);
-+ }
-+ else if (argc == 3 && strcmp(argv[2], "exit") == 0)
-+ {
-+ pfe_firmware_exit();
-+ }
-+ else
-+ {
-+ if (argc >= 3 && strcmp(argv[2], "help") != 0)
-+ {
-+ printf("Unknown option: %s\n", argv[2]);
-+ }
-+ printf("Usage: pfe firmware [init | exit]\n");
-+ }
-+}
-+
-+static void pfe_command_load(int argc, char * const argv[])
-+{
-+ if (argc >= 3 && strcmp(argv[2], "elf") == 0)
-+ {
-+ if (argc == 5)
-+ {
-+ u32 mask;
-+ unsigned long image_start;
-+ struct firmware fw;
-+ mask = simple_strtoul(argv[3], NULL, 0);
-+ image_start = simple_strtoul(argv[4], NULL, 16);
-+ fw.data = (u8 *)image_start;
-+ pfe_load_elf(mask, &fw);
-+ }
-+ else
-+ {
-+ printf("Usage: pfe load elf <pe_mask> <image_start>\n");
-+ }
-+ }
-+ else
-+ {
-+ if (argc >= 3 && strcmp(argv[2], "help") != 0)
-+ {
-+ printf("Unknown option: %s\n", argv[2]);
-+ }
-+ printf("Usage: pfe load elf <parameters>\n");
-+ }
-+}
-+#if 0
-+static void pfe_command_lib(int argc, char *argv[])
-+{
-+ if (argc >= 3 && strcmp(argv[2], "init") == 0)
-+ {
-+ if (argc == 3)
-+ pfe_lib_init((void *)COMCERTO_AXI_HFE_CFG_BASE, (void *)CONFIG_DDR_BASEADDR, CONFIG_DDR_PHYS_BASEADDR);
-+ else if (argc == 6)
-+ {
-+ u32 cbus_base;
-+ u32 ddr_base;
-+ u32 ddr_phys_base;
-+ cbus_base = simple_strtoul(argv[3], NULL, 16);
-+ ddr_base = simple_strtoul(argv[4], NULL, 16);
-+ ddr_phys_base = simple_strtoul(argv[5], NULL, 16);
-+ pfe_lib_init((void *)cbus_base, (void *)ddr_base, ddr_phys_base);
-+ }
-+ else
-+ {
-+ printf("Usage: pfe lib init [<cbus_base> <ddr_base> <ddr_phys_base>]\n");
-+ }
-+ }
-+ else
-+ {
-+ if (argc >= 3 && strcmp(argv[2], "help") != 0)
-+ {
-+ printf("Unknown option: %s\n", argv[2]);
-+ }
-+ printf("Usage: pfe lib init <parameters>\n");
-+ }
-+}
-+#endif
-+static void pfe_command_pe(int argc, char * const argv[])
-+{
-+ if (argc >= 3 && strcmp(argv[2], "pmem") == 0)
-+ {
-+ if (argc >= 4 && strcmp(argv[3], "read") == 0)
-+ {
-+ int i;
-+ int num;
-+ int id;
-+ u32 addr;
-+ u32 size;
-+ u32 val;
-+ if (argc == 7)
-+ num = simple_strtoul(argv[6], NULL, 0);
-+ else if (argc == 6)
-+ num = 1;
-+ else
-+ {
-+ printf("Usage: pfe pe pmem read <id> <addr> [<num>]\n");
-+ return;
-+ }
-+ id = simple_strtoul(argv[4], NULL, 0);
-+ addr = simple_strtoul(argv[5], NULL, 16);
-+ size = 4;
-+ for (i = 0; i < num; i++, addr += 4)
-+ {
-+ val = pe_pmem_read(id, addr, size);
-+ val = be32_to_cpu(val);
-+ if(!(i&3)) printf("%08x: ", addr);
-+ printf("%08x%s", val, i == num - 1 || (i & 3) == 3 ? "\n" : " ");
-+ }
-+ }
-+ else
-+ {
-+ printf("Usage: pfe pe pmem read <parameters>\n");
-+ }
-+ }
-+ else if (argc >= 3 && strcmp(argv[2], "dmem") == 0)
-+ {
-+ if (argc >= 4 && strcmp(argv[3], "read") == 0)
-+ {
-+ int i;
-+ int num;
-+ int id;
-+ u32 addr;
-+ u32 size;
-+ u32 val;
-+ if (argc == 7)
-+ num = simple_strtoul(argv[6], NULL, 0);
-+ else if (argc == 6)
-+ num = 1;
-+ else
-+ {
-+ printf("Usage: pfe pe dmem read <id> <addr> [<num>]\n");
-+ return;
-+ }
-+ id = simple_strtoul(argv[4], NULL, 0);
-+ addr = simple_strtoul(argv[5], NULL, 16);
-+ size = 4;
-+ for (i = 0; i < num; i++, addr += 4)
-+ {
-+ val = pe_dmem_read(id, addr, size);
-+ val = be32_to_cpu(val);
-+ if(!(i&3)) printf("%08x: ", addr);
-+ printf("%08x%s", val, i == num - 1 || (i & 3) == 3 ? "\n" : " ");
-+ }
-+ }
-+ else if (argc >= 4 && strcmp(argv[3], "write") == 0)
-+ {
-+ int id;
-+ u32 val;
-+ u32 addr;
-+ u32 size;
-+ if (argc != 7)
-+ {
-+ printf("Usage: pfe pe dmem write <id> <val> <addr>\n");
-+ return;
-+ }
-+ id = simple_strtoul(argv[4], NULL, 0);
-+ val = simple_strtoul(argv[5], NULL, 16);
-+ val = cpu_to_be32(val);
-+ addr = simple_strtoul(argv[6], NULL, 16);
-+ size = 4;
-+ pe_dmem_write(id, val, addr, size);
-+ }
-+ else
-+ {
-+ printf("Usage: pfe pe dmem [read | write] <parameters>\n");
-+ }
-+ }
-+ else if (argc >= 3 && strcmp(argv[2], "lmem") == 0)
-+ {
-+ if (argc >= 4 && strcmp(argv[3], "read") == 0)
-+ {
-+ int i;
-+ int num;
-+ u32 val;
-+ u32 offset;
-+ if (argc == 6)
-+ num = simple_strtoul(argv[5], NULL, 0);
-+ else if (argc == 5)
-+ num = 1;
-+ else
-+ {
-+ printf("Usage: pfe pe lmem read <offset> [<num>]\n");
-+ return;
-+ }
-+ offset = simple_strtoul(argv[4], NULL, 16);
-+ for (i = 0; i < num; i++, offset += 4)
-+ {
-+ pe_lmem_read(&val, 4, offset);
-+ val = be32_to_cpu(val);
-+ printf("%08x%s", val, i == num - 1 || (i & 7) == 7 ? "\n" : " ");
-+ }
-+ }
-+ else if (argc >= 4 && strcmp(argv[3], "write") == 0)
-+ {
-+ u32 val;
-+ u32 offset;
-+ if (argc != 6)
-+ {
-+ printf("Usage: pfe pe lmem write <val> <offset>\n");
-+ return;
-+ }
-+ val = simple_strtoul(argv[4], NULL, 16);
-+ val = cpu_to_be32(val);
-+ offset = simple_strtoul(argv[5], NULL, 16);
-+ pe_lmem_write(&val, 4, offset);
-+ }
-+ else
-+ {
-+ printf("Usage: pfe pe lmem [read | write] <parameters>\n");
-+ }
-+ }
-+ else
-+ {
-+ if (strcmp(argv[2], "help") != 0)
-+ {
-+ printf("Unknown option: %s\n", argv[2]);
-+ }
-+ printf("Usage: pfe pe <parameters>\n");
-+ }
-+ //void pe_mem_memcpy_to32(int id, u32 mem_access_addr, const void *src, unsigned int len)
-+ //void pe_dmem_memcpy_to32(int id, u32 dst, const void *src, unsigned int len)
-+ //void pe_pmem_memcpy_to32(int id, u32 dst, const void *src, unsigned int len)
-+ //int pe_load_elf_section(int id, const void *data, Elf32_Shdr *shdr)
-+}
-+
-+#if 0
-+static void pfe_command_gemac(int argc, char *argv[])
-+{
-+void gemac_init(void *base, void *cfg)
-+void gemac_set_speed(void *base, MAC_SPEED gem_speed)
-+void gemac_set_duplex(void *base, int duplex)
-+void gemac_set_mode(void *base, int mode)
-+void gemac_reset(void *base)
-+void gemac_enable(void *base)
-+void gemac_disable(void *base)
-+void gemac_set_address(void *base, SPEC_ADDR *addr)
-+SPEC_ADDR gemac_get_address(void *base)
-+void gemac_set_laddr1(void *base, MAC_ADDR *address)
-+void gemac_set_laddr2(void *base, MAC_ADDR *address)
-+void gemac_set_laddr3(void *base, MAC_ADDR *address)
-+void gemac_set_laddr4(void *base, MAC_ADDR *address)
-+void gemac_set_laddrN(void *base, MAC_ADDR *address, unsigned int entry_index)
-+void gemac_allow_broadcast(void *base)
-+void gemac_no_broadcast(void *base)
-+void gemac_enable_unicast(void *base)
-+void gemac_disable_unicast(void *base)
-+void gemac_enable_multicast(void *base)
-+void gemac_disable_multicast(void *base)
-+void gemac_enable_fcs_rx(void *base)
-+void gemac_disable_fcs_rx(void *base)
-+void gemac_enable_1536_rx(void *base)
-+void gemac_disable_1536_rx(void *base)
-+void gemac_enable_pause_rx(void *base)
-+void gemac_disable_pause_rx(void *base)
-+void gemac_set_config(void *base, GEMAC_CFG *cfg)
-+unsigned int * gemac_get_stats(void *base)
-+}
-+#endif
-+
-+#if 0
-+static void pfe_command_gem(int argc, char *argv[])
-+{
-+MAC_ADDR gem_get_laddr1(void *base)
-+MAC_ADDR gem_get_laddr2(void *base)
-+MAC_ADDR gem_get_laddr3(void *base)
-+MAC_ADDR gem_get_laddr4(void *base)
-+MAC_ADDR gem_get_laddrN(void *base, unsigned int entry_index)
-+}
-+#endif
-+
-+#if 0
-+static void pfe_command_gpi(int argc, char *argv[])
-+{
-+void gpi_init(void *base, GPI_CFG *cfg)
-+void gpi_reset(void *base)
-+void gpi_enable(void *base)
-+void gpi_disable(void *base)
-+void gpi_set_config(void *base, GPI_CFG *cfg)
-+}
-+#endif
-+
-+#if 1
-+static void pfe_command_class(int argc, char * const argv[])
-+{
-+ if (argc >= 3 && strcmp(argv[2], "init") == 0)
-+ {
-+ CLASS_CFG cfg;
-+ if (argc == 3)
-+ {
-+#define CONFIG_DDR_PHYS_BASEADDR 0x03800000
-+ cfg.route_table_hash_bits = ROUTE_TABLE_HASH_BITS;
-+ cfg.route_table_baseaddr = CONFIG_DDR_PHYS_BASEADDR + ROUTE_TABLE_BASEADDR;
-+ }
-+ else if (argc == 5)
-+ {
-+ cfg.route_table_hash_bits = simple_strtoul(argv[3], NULL, 16);
-+ cfg.route_table_baseaddr = simple_strtoul(argv[4], NULL, 16);
-+ }
-+ else
-+ {
-+ printf("Usage: pfe class init <route_table_hash_bits> <route_table_baseaddr>\n");
-+ }
-+ class_init(&cfg);
-+ }
-+ else if (argc == 3 && strcmp(argv[2], "reset") == 0)
-+ {
-+ class_reset();
-+ }
-+ else if (argc == 3 && strcmp(argv[2], "enable") == 0)
-+ {
-+ class_enable();
-+ }
-+ else if (argc == 3 && strcmp(argv[2], "disable") == 0)
-+ {
-+ class_disable();
-+ }
-+ else if (argc >= 3 && strcmp(argv[2], "config") == 0)
-+ {
-+ CLASS_CFG cfg;
-+ if (argc == 3)
-+ {
-+ cfg.route_table_hash_bits = ROUTE_TABLE_HASH_BITS;
-+ cfg.route_table_baseaddr = CONFIG_DDR_PHYS_BASEADDR + ROUTE_TABLE_BASEADDR;
-+ }
-+ else if (argc == 5)
-+ {
-+ cfg.route_table_hash_bits = simple_strtoul(argv[3], NULL, 16);
-+ cfg.route_table_baseaddr = simple_strtoul(argv[4], NULL, 16);
-+ }
-+ else
-+ {
-+ printf("Usage: pfe class config <route_table_hash_bits> <route_table_baseaddr>\n");
-+ }
-+ class_set_config(&cfg);
-+ }
-+ else if (argc >= 3 && strcmp(argv[2], "bus") == 0)
-+ {
-+ if (argc >= 4 && strcmp(argv[3], "read") == 0)
-+ {
-+ u32 addr;
-+ u32 size;
-+ u32 val;
-+ if (argc != 6)
-+ {
-+ printf("Usage: pfe class bus read <addr> <size>\n");
-+ return;
-+ }
-+ addr = simple_strtoul(argv[4], NULL, 16);
-+ size = simple_strtoul(argv[5], NULL, 16);
-+ val = class_bus_read(addr, size);
-+ printf("%08x\n", val);
-+ }
-+ else if (argc >= 4 && strcmp(argv[3], "write") == 0)
-+ {
-+ u32 val;
-+ u32 addr;
-+ u32 size;
-+ if (argc != 7)
-+ {
-+ printf("Usage: pfe class bus write <val> <addr> <size>\n");
-+ return;
-+ }
-+ val = simple_strtoul(argv[4], NULL, 16);
-+ addr = simple_strtoul(argv[5], NULL, 16);
-+ size = simple_strtoul(argv[6], NULL, 16);
-+ class_bus_write(val, addr, size);
-+ }
-+ else
-+ {
-+ printf("Usage: pfe class bus [read | write] <parameters>\n");
-+ }
-+ }
-+ else
-+ {
-+ if (argc >= 3 && strcmp(argv[2], "help") != 0)
-+ {
-+ printf("Unknown option: %s\n", argv[2]);
-+ }
-+ printf("Usage: pfe class [init | reset | enable | disable | config | bus] <parameters>\n");
-+ }
-+}
-+
-+static void pfe_command_tmu(int argc, char * const argv[])
-+{
-+ if (argc >= 3 && strcmp(argv[2], "init") == 0)
-+ {
-+ if (argc == 5)
-+ {
-+ TMU_CFG cfg;
-+ cfg.llm_base_addr = simple_strtoul(argv[3], NULL, 16);
-+ cfg.llm_queue_len = simple_strtoul(argv[4], NULL, 16);
-+ tmu_init(&cfg);
-+ }
-+ else
-+ {
-+ printf("Usage: pfe tmu init <llm_base_addr> <llm_queue_len>\n");
-+ }
-+ }
-+ else if (argc >= 3 && strcmp(argv[2], "enable") == 0)
-+ {
-+ if (argc == 4)
-+ {
-+ u32 mask;
-+ mask = simple_strtoul(argv[3], NULL, 16);
-+ tmu_enable(mask);
-+ }
-+ else
-+ {
-+ printf("Usage: pfe tmu enable <pe_mask>\n");
-+ }
-+ }
-+ else if (argc >= 3 && strcmp(argv[2], "disable") == 0)
-+ {
-+ if (argc == 4)
-+ {
-+ u32 mask;
-+ mask = simple_strtoul(argv[3], NULL, 16);
-+ tmu_disable(mask);
-+ }
-+ else
-+ {
-+ printf("Usage: pfe tmu disable <pe_mask>\n");
-+ }
-+ }
-+ else
-+ {
-+ if (argc >= 3 && strcmp(argv[2], "help") != 0)
-+ {
-+ printf("Unknown option: %s\n", argv[2]);
-+ }
-+ printf("Usage: pfe tmu [init | enable | disable] <parameters>\n");
-+ }
-+}
-+#endif
-+
-+/** qm_read_drop_stat
-+ * This function is used to read the drop statistics from the TMU
-+ * hw drop counter. Since the hw counter is always cleared afer
-+ * reading, this function maintains the previous drop count, and
-+ * adds the new value to it. That value can be retrieved by
-+ * passing a pointer to it with the total_drops arg.
-+ *
-+ * @param tmu TMU number (0 - 3)
-+ * @param queue queue number (0 - 15)
-+ * @param total_drops pointer to location to store total drops (or NULL)
-+ * @param do_reset if TRUE, clear total drops after updating
-+ *
-+ */
-+
-+u32 qm_read_drop_stat(u32 tmu, u32 queue, u32 *total_drops, int do_reset)
-+{
-+#define NUM_QUEUES 16
-+ static u32 qtotal[TMU_MAX_ID + 1][NUM_QUEUES];
-+ u32 val;
-+ writel((tmu << 8) | queue, TMU_TEQ_CTRL);
-+ writel((tmu << 8) | queue, TMU_LLM_CTRL);
-+ val = readl(TMU_TEQ_DROP_STAT);
-+ qtotal[tmu][queue] += val;
-+ if (total_drops)
-+ *total_drops = qtotal[tmu][queue];
-+ if (do_reset)
-+ qtotal[tmu][queue] = 0;
-+ return val;
-+}
-+
-+static ssize_t tmu_queue_stats(char *buf, int tmu, int queue)
-+{
-+ ssize_t len = 0;
-+ u32 drops;
-+
-+ printf("%d-%02d, ", tmu, queue);
-+
-+ drops = qm_read_drop_stat(tmu, queue, NULL, 0);
-+
-+ /* Select queue */
-+ writel((tmu << 8) | queue, TMU_TEQ_CTRL);
-+ writel((tmu << 8) | queue, TMU_LLM_CTRL);
-+
-+ printf("(teq) drop: %10u, tx: %10u (llm) head: %08x, tail: %08x, drop: %10u\n",
-+ drops, readl(TMU_TEQ_TRANS_STAT),
-+ readl(TMU_LLM_QUE_HEADPTR), readl(TMU_LLM_QUE_TAILPTR),
-+ readl(TMU_LLM_QUE_DROPCNT));
-+
-+ return len;
-+}
-+
-+
-+static ssize_t tmu_queues(char *buf, int tmu)
-+{
-+ ssize_t len = 0;
-+ int queue;
-+
-+ for (queue = 0; queue < 16; queue++)
-+ len += tmu_queue_stats(buf + len, tmu, queue);
-+
-+ return len;
-+}
-+
-+void hif_status(void)
-+{
-+ printf("hif:\n");
-+
-+ printf(" tx curr bd: %x\n", readl(HIF_TX_CURR_BD_ADDR));
-+ printf(" tx status: %x\n", readl(HIF_TX_STATUS));
-+ printf(" tx dma status: %x\n", readl(HIF_TX_DMA_STATUS));
-+
-+ printf(" rx curr bd: %x\n", readl(HIF_RX_CURR_BD_ADDR));
-+ printf(" rx status: %x\n", readl(HIF_RX_STATUS));
-+ printf(" rx dma status: %x\n", readl(HIF_RX_DMA_STATUS));
-+
-+ printf("hif nocopy:\n");
-+
-+ printf(" tx curr bd: %x\n", readl(HIF_NOCPY_TX_CURR_BD_ADDR));
-+ printf(" tx status: %x\n", readl(HIF_NOCPY_TX_STATUS));
-+ printf(" tx dma status: %x\n", readl(HIF_NOCPY_TX_DMA_STATUS));
-+
-+ printf(" rx curr bd: %x\n", readl(HIF_NOCPY_RX_CURR_BD_ADDR));
-+ printf(" rx status: %x\n", readl(HIF_NOCPY_RX_STATUS));
-+ printf(" rx dma status: %x\n", readl(HIF_NOCPY_RX_DMA_STATUS));
-+}
-+
-+static void gpi(int id, void *base)
-+{
-+ u32 val;
-+
-+ printf("gpi%d:\n ", id);
-+
-+ printf(" tx under stick: %x\n", readl(base + GPI_FIFO_STATUS));
-+ val = readl(base + GPI_FIFO_DEBUG);
-+ printf(" tx pkts: %x\n", (val >> 23) & 0x3f);
-+ printf(" rx pkts: %x\n", (val >> 18) & 0x3f);
-+ printf(" tx bytes: %x\n", (val >> 9) & 0x1ff);
-+ printf(" rx bytes: %x\n", (val >> 0) & 0x1ff);
-+ printf(" overrun: %x\n", readl(base + GPI_OVERRUN_DROPCNT));
-+}
-+
-+void bmu(int id, void *base)
-+{
-+ printf("bmu: %d\n", id);
-+ printf(" buf size: %x\n", (1 << readl(base + BMU_BUF_SIZE)));
-+ printf(" buf count: %x\n", readl(base + BMU_BUF_CNT));
-+ printf(" buf rem: %x\n", readl(base + BMU_REM_BUF_CNT));
-+ printf(" buf curr: %x\n", readl(base + BMU_CURR_BUF_CNT));
-+ printf(" free err: %x\n", readl(base + BMU_FREE_ERR_ADDR));
-+}
-+
-+#define PESTATUS_ADDR_CLASS 0x800
-+#define PESTATUS_ADDR_TMU 0x80
-+#define PESTATUS_ADDR_UTIL 0x0
-+
-+static void pfe_pe_status(int argc, char * const argv[])
-+{
-+ int do_clear = 0;
-+ int j;
-+ u32 id;
-+ u32 dmem_addr;
-+ u32 cpu_state;
-+ u32 activity_counter;
-+ u32 rx;
-+ u32 tx;
-+ u32 drop;
-+ char statebuf[5];
-+ u32 class_debug_reg = 0;
-+ u32 debug_indicator;
-+ u32 debug[16];
-+
-+ if (argc == 4 && strcmp(argv[3], "clear") == 0)
-+ do_clear = 1;
-+
-+ for (id = CLASS0_ID; id < MAX_PE; id++)
-+ {
-+#if !defined(CONFIG_UTIL_PE_DISABLED)
-+ if (id == UTIL_ID)
-+ {
-+ printf("util:\n");
-+ dmem_addr = PESTATUS_ADDR_UTIL;
-+ }
-+ else if (id >= TMU0_ID)
-+#else
-+ if (id >= TMU0_ID)
-+#endif
-+ {
-+ if (id == TMU2_ID)
-+ continue;
-+ if (id == TMU0_ID)
-+ printf("tmu:\n");
-+ dmem_addr = PESTATUS_ADDR_TMU;
-+ }
-+ else
-+ {
-+ if (id == CLASS0_ID)
-+ printf("class:\n");
-+ dmem_addr = PESTATUS_ADDR_CLASS;
-+ class_debug_reg = readl(CLASS_PE0_DEBUG + id * 4);
-+ }
-+ cpu_state = pe_dmem_read(id, dmem_addr, 4);
-+ dmem_addr += 4;
-+ memcpy(statebuf, (char *)&cpu_state, 4);
-+ statebuf[4] = '\0';
-+ activity_counter = pe_dmem_read(id, dmem_addr, 4);
-+ dmem_addr += 4;
-+ rx = pe_dmem_read(id, dmem_addr, 4);
-+ if (do_clear)
-+ pe_dmem_write(id, 0, dmem_addr, 4);
-+ dmem_addr += 4;
-+ tx = pe_dmem_read(id, dmem_addr, 4);
-+ if (do_clear)
-+ pe_dmem_write(id, 0, dmem_addr, 4);
-+ dmem_addr += 4;
-+ drop = pe_dmem_read(id, dmem_addr, 4);
-+ if (do_clear)
-+ pe_dmem_write(id, 0, dmem_addr, 4);
-+ dmem_addr += 4;
-+#if !defined(CONFIG_UTIL_PE_DISABLED)
-+ if (id == UTIL_ID)
-+ {
-+ printf("state=%4s ctr=%08x rx=%x tx=%x\n",
-+ statebuf, cpu_to_be32(activity_counter),
-+ cpu_to_be32(rx), cpu_to_be32(tx));
-+ }
-+ else
-+#endif
-+ if (id >= TMU0_ID)
-+ {
-+ printf("%d: state=%4s ctr=%08x rx=%x qstatus=%x\n",
-+ id - TMU0_ID, statebuf, cpu_to_be32(activity_counter),
-+ cpu_to_be32(rx), cpu_to_be32(tx));
-+ }
-+ else
-+ {
-+ printf("%d: pc=1%04x ldst=%04x state=%4s ctr=%08x rx=%x tx=%x drop=%x\n",
-+ id - CLASS0_ID, class_debug_reg & 0xFFFF, class_debug_reg >> 16,
-+ statebuf, cpu_to_be32(activity_counter),
-+ cpu_to_be32(rx), cpu_to_be32(tx), cpu_to_be32(drop));
-+ }
-+ debug_indicator = pe_dmem_read(id, dmem_addr, 4);
-+ dmem_addr += 4;
-+ if (debug_indicator == cpu_to_be32('DBUG'))
-+ {
-+ int last = 0;
-+ for (j = 0; j < 16; j++)
-+ {
-+ debug[j] = pe_dmem_read(id, dmem_addr, 4);
-+ if (debug[j])
-+ {
-+ last = j + 1;
-+ if (do_clear)
-+ pe_dmem_write(id, 0, dmem_addr, 4);
-+ }
-+ dmem_addr += 4;
-+ }
-+ for (j = 0; j < last; j++)
-+ {
-+ printf("%08x%s", cpu_to_be32(debug[j]), (j & 0x7) == 0x7 || j == last - 1 ? "\n" : " ");
-+ }
-+ }
-+ }
-+
-+}
-+
-+static void pfe_command_status(int argc, char * const argv[])
-+{
-+
-+ if (argc >= 3 && strcmp(argv[2], "pe") == 0)
-+ {
-+ pfe_pe_status(argc, argv);
-+ }
-+ else if (argc == 3 && strcmp(argv[2], "bmu") == 0)
-+ {
-+ bmu(1, BMU1_BASE_ADDR);
-+ bmu(2, BMU2_BASE_ADDR);
-+ }
-+ else if (argc == 3 && strcmp(argv[2], "hif") == 0)
-+ {
-+ hif_status();
-+ }
-+ else if (argc == 3 && strcmp(argv[2], "gpi") == 0)
-+ {
-+ gpi(0, EGPI1_BASE_ADDR);
-+ gpi(1, EGPI2_BASE_ADDR);
-+ gpi(3, HGPI_BASE_ADDR);
-+ }
-+ else if (argc == 3 && strcmp(argv[2], "tmu0_queues") == 0)
-+ {
-+ tmu_queues(NULL, 0);
-+ }
-+ else if (argc == 3 && strcmp(argv[2], "tmu1_queues") == 0)
-+ {
-+ tmu_queues(NULL, 1);
-+ }
-+ else if (argc == 3 && strcmp(argv[2], "tmu3_queues") == 0)
-+ {
-+ tmu_queues(NULL, 3);
-+ }
-+ else
-+ printf("Usage: pfe status [pe <clear> | bmu | gpi | hif | tmuX_queues ]\n");
-+
-+ return;
-+}
-+
-+
-+#define EXPT_DUMP_ADDR 0x1fa8
-+#define EXPT_REG_COUNT 20
-+static const char *register_names[EXPT_REG_COUNT] = {
-+ " pc", "ECAS", " EID", " ED",
-+ " sp", " r1", " r2", " r3",
-+ " r4", " r5", " r6", " r7",
-+ " r8", " r9", " r10", " r11",
-+ " r12", " r13", " r14", " r15"
-+};
-+
-+static void pfe_command_expt(int argc, char * const argv[])
-+{
-+ unsigned int id, i, val, addr;
-+
-+ if (argc == 3)
-+ {
-+ id = simple_strtoul(argv[2], NULL, 0);
-+ addr = EXPT_DUMP_ADDR;
-+ printf("Exception information for PE %d:\n", id);
-+ for (i = 0; i < EXPT_REG_COUNT; i++)
-+ {
-+ val = pe_dmem_read(id, addr, 4);
-+ val = be32_to_cpu(val);
-+ printf("%s:%08x%s", register_names[i], val, (i & 3) == 3 ? "\n" : " ");
-+ addr += 4;
-+ }
-+ }
-+ else
-+ {
-+ printf("Usage: pfe expt <id>\n");
-+ }
-+}
-+
-+static void pfe_command_util(int argc, char * const argv[])
-+{
-+ if (argc == 3 && strcmp(argv[2], "init") == 0)
-+ {
-+ UTIL_CFG cfg;
-+ util_init(&cfg);
-+ }
-+ else if (argc == 3 && strcmp(argv[2], "reset") == 0)
-+ {
-+ util_reset();
-+ }
-+ else if (argc == 3 && strcmp(argv[2], "enable") == 0)
-+ {
-+ util_enable();
-+ }
-+ else if (argc == 3 && strcmp(argv[2], "disable") == 0)
-+ {
-+ util_disable();
-+ }
-+ else if (argc >= 3 && strcmp(argv[2], "bus") == 0)
-+ {
-+ if (argc >= 4 && strcmp(argv[3], "read") == 0)
-+ {
-+ u32 addr;
-+ u32 size;
-+ u32 val;
-+ if (argc != 6)
-+ {
-+ printf("Usage: pfe util bus read <addr> <size>\n");
-+ return;
-+ }
-+ addr = simple_strtoul(argv[4], NULL, 16);
-+ size = simple_strtoul(argv[5], NULL, 16);
-+ val = util_bus_read(addr, size);
-+ printf("%08x\n", val);
-+ }
-+ else if (argc >= 4 && strcmp(argv[3], "write") == 0)
-+ {
-+ u32 val;
-+ u32 addr;
-+ u32 size;
-+ if (argc != 7)
-+ {
-+ printf("Usage: pfe util bus write <val> <addr> <size>\n");
-+ return;
-+ }
-+ val = simple_strtoul(argv[4], NULL, 16);
-+ addr = simple_strtoul(argv[5], NULL, 16);
-+ size = simple_strtoul(argv[6], NULL, 16);
-+ util_bus_write(val, addr, size);
-+ }
-+ else
-+ {
-+ printf("Usage: pfe util bus [read | write] <parameters>\n");
-+ }
-+ }
-+ else
-+ {
-+ if (argc >= 3 && strcmp(argv[2], "help") != 0)
-+ {
-+ printf("Unknown option: %s\n", argv[2]);
-+ }
-+ printf("Usage: pfe util [init | reset | enable | disable | bus] <parameters>\n");
-+ }
-+}
-+
-+#if 0
-+static void pfe_command_hif(int argc, char *argv[])
-+{
-+void hif_nocpy_init(void)
-+void hif_init(void)
-+void hif_tx_enable(void)
-+void hif_tx_disable(void)
-+void hif_rx_enable(void)
-+void hif_rx_disable(void)
-+}
-+#endif
-+
-+#define ROUTE_TABLE_START (CONFIG_DDR_PHYS_BASEADDR+ROUTE_TABLE_BASEADDR)
-+static void pfe_command_fftest(int argc, char * const argv[])
-+{
-+ bd_t *bd = gd->bd;
-+ struct eth_device *edev_eth0;
-+ struct eth_device *edev_eth1;
-+
-+
-+ // open eth0 and eth1
-+ edev_eth0 = eth_get_dev_by_name("pfe_eth0");
-+ if (!edev_eth0)
-+ {
-+ printf("Cannot access eth0\n");
-+ return;
-+ }
-+
-+ if (eth_write_hwaddr(edev_eth0, "eth", edev_eth0->index))
-+ puts("\nWarning: failed to set MAC address for c2000_gemac0\n");
-+
-+ if (edev_eth0->state != ETH_STATE_ACTIVE)
-+ {
-+ if (edev_eth0->init(edev_eth0, bd) < 0) {
-+ printf("eth0 init failed\n");
-+ return;
-+ }
-+ edev_eth0->state = ETH_STATE_ACTIVE;
-+ }
-+
-+ edev_eth1 = eth_get_dev_by_name("pfe_eth1");
-+ if (!edev_eth1)
-+ {
-+ printf("Cannot access eth1\n");
-+ return;
-+ }
-+
-+ if (eth_write_hwaddr(edev_eth1, "eth", edev_eth1->index))
-+ puts("\nWarning: failed to set MAC address for c2000_gemac1\n");
-+
-+ if (edev_eth1->state != ETH_STATE_ACTIVE)
-+ {
-+ if (edev_eth1->init(edev_eth1, bd) < 0) {
-+ printf("eth1 init failed\n");
-+ return;
-+ }
-+ edev_eth1->state = ETH_STATE_ACTIVE;
-+ }
-+
-+}
-+
-+#ifdef CONFIG_CMD_PFE_START
-+static void pfe_command_start(int argc, char * const argv[])
-+{
-+ printf("Starting PFE \n");
-+ ls1012a_gemac_initialize(gd->bd, 0 , "pfe_eth0");
-+ ls1012a_gemac_initialize(gd->bd, 1 , "pfe_eth1");
-+}
-+#endif
-+
-+
-+static int pfe_command(cmd_tbl_t *cmdtp, int flag, int argc,
-+ char * const argv[])
-+{
-+ if (argc == 1 || strcmp(argv[1], "help") == 0)
-+ {
-+ pfe_command_help();
-+ return CMD_RET_SUCCESS;
-+ }
-+ if (strcmp(argv[1], "firmware") == 0)
-+ pfe_command_firmware(argc, argv);
-+ else if (strcmp(argv[1], "load") == 0)
-+ pfe_command_load(argc, argv);
-+#if 0
-+ else if (strcmp(argv[1], "lib") == 0)
-+ pfe_command_lib(argc, argv);
-+#endif
-+ else if (strcmp(argv[1], "pe") == 0)
-+ pfe_command_pe(argc, argv);
-+#if 0
-+ else if (strcmp(argv[1], "gemac") == 0)
-+ pfe_command_gemac(argc, argv);
-+ else if (strcmp(argv[1], "gem") == 0)
-+ pfe_command_gem(argc, argv);
-+ else if (strcmp(argv[1], "gpi") == 0)
-+ pfe_command_gpi(argc, argv);
-+#endif
-+#if 1
-+ else if (strcmp(argv[1], "class") == 0)
-+ pfe_command_class(argc, argv);
-+ else if (strcmp(argv[1], "tmu") == 0)
-+ pfe_command_tmu(argc, argv);
-+#endif
-+ else if (strcmp(argv[1], "status") == 0)
-+ pfe_command_status(argc, argv);
-+ else if (strcmp(argv[1], "expt") == 0)
-+ pfe_command_expt(argc, argv);
-+ else if (strcmp(argv[1], "util") == 0)
-+ pfe_command_util(argc, argv);
-+#if 0
-+ else if (strcmp(argv[1], "hif") == 0)
-+ pfe_command_hif(argc, argv);
-+#endif
-+ else if (strcmp(argv[1], "fftest") == 0)
-+ pfe_command_fftest(argc, argv);
-+#ifdef CONFIG_CMD_PFE_START
-+ else if (strcmp(argv[1], "start") == 0)
-+ pfe_command_start(argc, argv);
-+#endif
-+ else
-+ {
-+ printf("Unknown option: %s\n", argv[1]);
-+ pfe_command_help();
-+ return CMD_RET_FAILURE;
-+ }
-+ return CMD_RET_SUCCESS;
-+}
-+
-+
-+U_BOOT_CMD(
-+ pfe, 7, 1, pfe_command,
-+ "Performs PFE lib utility functions",
-+ "Usage: \n"
-+ "pfe <options>"
-+);
-diff --git a/drivers/net/Makefile b/drivers/net/Makefile
-index 150470c..c683b8f 100644
---- a/drivers/net/Makefile
-+++ b/drivers/net/Makefile
-@@ -72,3 +72,4 @@ obj-$(CONFIG_FSL_MC_ENET) += fsl-mc/
- obj-$(CONFIG_FSL_MC_ENET) += ldpaa_eth/
- obj-$(CONFIG_FSL_MEMAC) += fm/memac_phy.o
- obj-$(CONFIG_VSC9953) += vsc9953.o
-+obj-$(CONFIG_FSL_PPFE) += pfe_eth/
-diff --git a/drivers/net/pfe_eth/Makefile b/drivers/net/pfe_eth/Makefile
-new file mode 100644
-index 0000000..1af837d
---- /dev/null
-+++ b/drivers/net/pfe_eth/Makefile
-@@ -0,0 +1 @@
-+obj-y += pfe_eth.o pfe_firmware.o pfe.o pfe_driver.o
-diff --git a/drivers/net/pfe_eth/class_sbl_elf.fw b/drivers/net/pfe_eth/class_sbl_elf.fw
-new file mode 100644
-index 0000000..3745d9a
---- /dev/null
-+++ b/drivers/net/pfe_eth/class_sbl_elf.fw
-@@ -0,0 +1 @@
-+0x7f,0x45,0x4c,0x46,0x01,0x02,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x02,0x00,0x6f,0x00,0x00,0x00,0x01,0x00,0x01,0x02,0x4c,0x00,0x00,0x00,0x34,0x00,0x00,0x13,0x14,0x00,0x04,0x00,0x05,0x00,0x34,0x00,0x20,0x00,0x04,0x00,0x28,0x00,0x0d,0x00,0x0c,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x08,0x90,0x00,0x00,0x08,0x98,0x00,0x00,0x00,0x06,0x00,0x00,0x10,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x08,0x98,0x00,0x00,0x08,0x98,0x00,0x00,0 [...]
-\ No newline at end of file
-diff --git a/drivers/net/pfe_eth/hal.h b/drivers/net/pfe_eth/hal.h
-new file mode 100644
-index 0000000..e795fe6
---- /dev/null
-+++ b/drivers/net/pfe_eth/hal.h
-@@ -0,0 +1,64 @@
-+/*
-+ * (C) Copyright 2011
-+ * Author : Mindspeed Technologes
-+ *
-+ * See file CREDITS for list of people who contributed to this
-+ * project.
-+ *
-+ * This program is free software; you can redistribute it and/or
-+ * modify it under the terms of the GNU General Public License as
-+ * published by the Free Software Foundation; either version 2 of
-+ * the License, or (at your option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program; if not, write to the Free Software
-+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-+ * MA 02111-1307 USA
-+ * */
-+
-+#ifndef _HAL_H_
-+#define _HAL_H_
-+
-+#if defined(CONFIG_PLATFORM_PCI)
-+/* For ChipIT */
-+
-+#include <linux/types.h>
-+#include <linux/elf.h>
-+#include <linux/errno.h>
-+#include <linux/pci.h>
-+#include <asm/io.h>
-+#include <linux/slab.h>
-+#include <linux/firmware.h>
-+
-+
-+#define free(x) kfree(x)
-+#define xzalloc(x) kmalloc(x, GFP_DMA)
-+#define printf printk
-+
-+//#define dprint(fmt, arg...) printk(fmt, ##arg)
-+#define dprint(fmt, arg...)
-+
-+#else
-+
-+#include <linux/types.h>
-+#include <elf.h>
-+#include <common.h>
-+//#include <errno.h>
-+#include <asm/byteorder.h>
-+#include <miiphy.h>
-+#include <malloc.h>
-+#include <asm/io.h>
-+
-+
-+#include "pfe_eth.h"
-+
-+#endif
-+
-+
-+#endif /* _HAL_H_ */
-+
-diff --git a/drivers/net/pfe_eth/pfe.c b/drivers/net/pfe_eth/pfe.c
-new file mode 100644
-index 0000000..3b5570a
---- /dev/null
-+++ b/drivers/net/pfe_eth/pfe.c
-@@ -0,0 +1,1677 @@
-+#include "hal.h"
-+#include "pfe/pfe.h"
-+
-+void *cbus_base_addr;
-+void *ddr_base_addr;
-+unsigned long ddr_phys_base_addr;
-+#if 0
-+#define dprintf(fmt, arg...) printf(fmt, ##arg)
-+#else
-+#define dprintf(fmt, arg...)
-+#endif
-+static struct pe_info pe[MAX_PE];
-+
-+/** Initializes the PFE library.
-+* Must be called before using any of the library functions.
-+*
-+* @param[in] cbus_base CBUS virtual base address (as mapped in the host CPU address space)
-+* @param[in] ddr_base DDR virtual base address (as mapped in the host CPU address space)
-+* @param[in] ddr_phys_base DDR physical base address (as mapped in platform)
-+*/
-+void pfe_lib_init(void *cbus_base, void *ddr_base, unsigned long ddr_phys_base)
-+{
-+ cbus_base_addr = cbus_base;
-+ ddr_base_addr = ddr_base;
-+ ddr_phys_base_addr = ddr_phys_base;
-+
-+ pe[CLASS0_ID].dmem_base_addr = (u32)CLASS_DMEM_BASE_ADDR(0);
-+ pe[CLASS0_ID].pmem_base_addr = (u32)CLASS_IMEM_BASE_ADDR(0);
-+ pe[CLASS0_ID].pmem_size = (u32)CLASS_IMEM_SIZE;
-+ pe[CLASS0_ID].mem_access_wdata = (void *)CLASS_MEM_ACCESS_WDATA;
-+ pe[CLASS0_ID].mem_access_addr = (void *)CLASS_MEM_ACCESS_ADDR;
-+ pe[CLASS0_ID].mem_access_rdata = (void *)CLASS_MEM_ACCESS_RDATA;
-+
-+ pe[CLASS1_ID].dmem_base_addr = (u32)CLASS_DMEM_BASE_ADDR(1);
-+ pe[CLASS1_ID].pmem_base_addr = (u32)CLASS_IMEM_BASE_ADDR(1);
-+ pe[CLASS1_ID].pmem_size = (u32)CLASS_IMEM_SIZE;
-+ pe[CLASS1_ID].mem_access_wdata = (void *)CLASS_MEM_ACCESS_WDATA;
-+ pe[CLASS1_ID].mem_access_addr = (void *)CLASS_MEM_ACCESS_ADDR;
-+ pe[CLASS1_ID].mem_access_rdata = (void *)CLASS_MEM_ACCESS_RDATA;
-+
-+ pe[CLASS2_ID].dmem_base_addr = (u32)CLASS_DMEM_BASE_ADDR(2);
-+ pe[CLASS2_ID].pmem_base_addr = (u32)CLASS_IMEM_BASE_ADDR(2);
-+ pe[CLASS2_ID].pmem_size = (u32)CLASS_IMEM_SIZE;
-+ pe[CLASS2_ID].mem_access_wdata = (void *)CLASS_MEM_ACCESS_WDATA;
-+ pe[CLASS2_ID].mem_access_addr = (void *)CLASS_MEM_ACCESS_ADDR;
-+ pe[CLASS2_ID].mem_access_rdata = (void *)CLASS_MEM_ACCESS_RDATA;
-+
-+ pe[CLASS3_ID].dmem_base_addr = (u32)CLASS_DMEM_BASE_ADDR(3);
-+ pe[CLASS3_ID].pmem_base_addr = (u32)CLASS_IMEM_BASE_ADDR(3);
-+ pe[CLASS3_ID].pmem_size = (u32)CLASS_IMEM_SIZE;
-+ pe[CLASS3_ID].mem_access_wdata = (void *)CLASS_MEM_ACCESS_WDATA;
-+ pe[CLASS3_ID].mem_access_addr = (void *)CLASS_MEM_ACCESS_ADDR;
-+ pe[CLASS3_ID].mem_access_rdata = (void *)CLASS_MEM_ACCESS_RDATA;
-+
-+#if !defined(CONFIG_PLATFORM_PCI)
-+ pe[CLASS4_ID].dmem_base_addr = (u32)CLASS_DMEM_BASE_ADDR(4);
-+ pe[CLASS4_ID].pmem_base_addr = (u32)CLASS_IMEM_BASE_ADDR(4);
-+ pe[CLASS4_ID].pmem_size = (u32)CLASS_IMEM_SIZE;
-+ pe[CLASS4_ID].mem_access_wdata = (void *)CLASS_MEM_ACCESS_WDATA;
-+ pe[CLASS4_ID].mem_access_addr = (void *)CLASS_MEM_ACCESS_ADDR;
-+ pe[CLASS4_ID].mem_access_rdata = (void *)CLASS_MEM_ACCESS_RDATA;
-+
-+ pe[CLASS5_ID].dmem_base_addr = (u32)CLASS_DMEM_BASE_ADDR(5);
-+ pe[CLASS5_ID].pmem_base_addr = (u32)CLASS_IMEM_BASE_ADDR(5);
-+ pe[CLASS5_ID].pmem_size = (u32)CLASS_IMEM_SIZE;
-+ pe[CLASS5_ID].mem_access_wdata = (void *)CLASS_MEM_ACCESS_WDATA;
-+ pe[CLASS5_ID].mem_access_addr = (void *)CLASS_MEM_ACCESS_ADDR;
-+ pe[CLASS5_ID].mem_access_rdata = (void *)CLASS_MEM_ACCESS_RDATA;
-+#endif
-+ pe[TMU0_ID].dmem_base_addr = (u32)TMU_DMEM_BASE_ADDR(0);
-+ pe[TMU0_ID].pmem_base_addr = (u32)TMU_IMEM_BASE_ADDR(0);
-+ pe[TMU0_ID].pmem_size = (u32)TMU_IMEM_SIZE;
-+ pe[TMU0_ID].mem_access_wdata = (void *)TMU_MEM_ACCESS_WDATA;
-+ pe[TMU0_ID].mem_access_addr = (void *)TMU_MEM_ACCESS_ADDR;
-+ pe[TMU0_ID].mem_access_rdata = (void *)TMU_MEM_ACCESS_RDATA;
-+
-+#if !defined(CONFIG_TMU_DUMMY)
-+ pe[TMU1_ID].dmem_base_addr = (u32)TMU_DMEM_BASE_ADDR(1);
-+ pe[TMU1_ID].pmem_base_addr = (u32)TMU_IMEM_BASE_ADDR(1);
-+ pe[TMU1_ID].pmem_size = (u32)TMU_IMEM_SIZE;
-+ pe[TMU1_ID].mem_access_wdata = (void *)TMU_MEM_ACCESS_WDATA;
-+ pe[TMU1_ID].mem_access_addr = (void *)TMU_MEM_ACCESS_ADDR;
-+ pe[TMU1_ID].mem_access_rdata = (void *)TMU_MEM_ACCESS_RDATA;
-+
-+#if !defined(CONFIG_LS1012A)
-+ pe[TMU2_ID].dmem_base_addr = (u32)TMU_DMEM_BASE_ADDR(2);
-+ pe[TMU2_ID].pmem_base_addr = (u32)TMU_IMEM_BASE_ADDR(2);
-+ pe[TMU2_ID].pmem_size = (u32)TMU_IMEM_SIZE;
-+ pe[TMU2_ID].mem_access_wdata = (void *)TMU_MEM_ACCESS_WDATA;
-+ pe[TMU2_ID].mem_access_addr = (void *)TMU_MEM_ACCESS_ADDR;
-+ pe[TMU2_ID].mem_access_rdata = (void *)TMU_MEM_ACCESS_RDATA;
-+#endif
-+
-+ pe[TMU3_ID].dmem_base_addr = (u32)TMU_DMEM_BASE_ADDR(3);
-+ pe[TMU3_ID].pmem_base_addr = (u32)TMU_IMEM_BASE_ADDR(3);
-+ pe[TMU3_ID].pmem_size = (u32)TMU_IMEM_SIZE;
-+ pe[TMU3_ID].mem_access_wdata = (void *)TMU_MEM_ACCESS_WDATA;
-+ pe[TMU3_ID].mem_access_addr = (void *)TMU_MEM_ACCESS_ADDR;
-+ pe[TMU3_ID].mem_access_rdata = (void *)TMU_MEM_ACCESS_RDATA;
-+#endif
-+
-+#if !defined(CONFIG_UTIL_PE_DISABLED)
-+ pe[UTIL_ID].dmem_base_addr = (u32)UTIL_DMEM_BASE_ADDR;
-+ pe[UTIL_ID].mem_access_wdata = (void *)UTIL_MEM_ACCESS_WDATA;
-+ pe[UTIL_ID].mem_access_addr = (void *)UTIL_MEM_ACCESS_ADDR;
-+ pe[UTIL_ID].mem_access_rdata = (void *)UTIL_MEM_ACCESS_RDATA;
-+#endif
-+}
-+
-+
-+/** Writes a buffer to PE internal memory from the host
-+ * through indirect access registers.
-+ *
-+ * @param[in] id PE identification (CLASS0_ID, ..., TMU0_ID, ..., UTIL_ID)
-+ * @param[in] src Buffer source address
-+ * @param[in] mem_access_addr DMEM destination address (must be 32bit aligned)
-+ * @param[in] len Number of bytes to copy
-+ */
-+void pe_mem_memcpy_to32(int id, u32 mem_access_addr, const void *src, unsigned int len)
-+{
-+ u32 offset = 0, val, addr;
-+ unsigned int len32 = len >> 2;
-+ int i;
-+
-+ addr = mem_access_addr | PE_MEM_ACCESS_WRITE | PE_MEM_ACCESS_BYTE_ENABLE(0, 4);
-+
-+ for (i = 0; i < len32; i++, offset += 4, src += 4) {
-+ val = *(u32 *)src;
-+ writel(cpu_to_be32(val), pe[id].mem_access_wdata);
-+ writel(addr + offset, pe[id].mem_access_addr);
-+ }
-+
-+ if ((len = (len & 0x3))) {
-+ val = 0;
-+
-+ addr = (mem_access_addr | PE_MEM_ACCESS_WRITE | PE_MEM_ACCESS_BYTE_ENABLE(0, len)) + offset;
-+
-+ for (i = 0; i < len; i++, src++)
-+ val |= (*(u8 *)src) << (8 * i);
-+
-+ writel(cpu_to_be32(val), pe[id].mem_access_wdata);
-+ writel(addr, pe[id].mem_access_addr);
-+ }
-+}
-+
-+/** Writes a buffer to PE internal data memory (DMEM) from the host
-+ * through indirect access registers.
-+ * @param[in] id PE identification (CLASS0_ID, ..., TMU0_ID, ..., UTIL_ID)
-+ * @param[in] src Buffer source address
-+ * @param[in] dst DMEM destination address (must be 32bit aligned)
-+ * @param[in] len Number of bytes to copy
-+ */
-+void pe_dmem_memcpy_to32(int id, u32 dst, const void *src, unsigned int len)
-+{
-+ pe_mem_memcpy_to32(id, pe[id].dmem_base_addr | dst | PE_MEM_ACCESS_DMEM, src, len);
-+}
-+
-+
-+/** Writes a buffer to PE internal program memory (PMEM) from the host
-+ * through indirect access registers.
-+ * @param[in] id PE identification (CLASS0_ID, ..., TMU0_ID, ..., TMU3_ID)
-+ * @param[in] src Buffer source address
-+ * @param[in] dst PMEM destination address (must be 32bit aligned)
-+ * @param[in] len Number of bytes to copy
-+ */
-+void pe_pmem_memcpy_to32(int id, u32 dst, const void *src, unsigned int len)
-+{
-+ pe_mem_memcpy_to32(id, pe[id].pmem_base_addr | (dst & (pe[id].pmem_size - 1)) | PE_MEM_ACCESS_IMEM, src, len);
-+}
-+
-+
-+/** Reads PE internal program memory (IMEM) from the host
-+ * through indirect access registers.
-+ * @param[in] id PE identification (CLASS0_ID, ..., TMU0_ID, ..., TMU3_ID)
-+ * @param[in] addr PMEM read address (must be aligned on size)
-+ * @param[in] size Number of bytes to read (maximum 4, must not cross 32bit boundaries)
-+ * @return the data read (in PE endianess, i.e BE).
-+ */
-+u32 pe_pmem_read(int id, u32 addr, u8 size)
-+{
-+ u32 offset = addr & 0x3;
-+ u32 mask = 0xffffffff >> ((4 - size) << 3);
-+ u32 val;
-+
-+ addr = pe[id].pmem_base_addr | ((addr & ~0x3) & (pe[id].pmem_size - 1)) | PE_MEM_ACCESS_READ | PE_MEM_ACCESS_IMEM | PE_MEM_ACCESS_BYTE_ENABLE(offset, size);
-+
-+ writel(addr, pe[id].mem_access_addr);
-+ val = be32_to_cpu(readl(pe[id].mem_access_rdata));
-+
-+ return (val >> (offset << 3)) & mask;
-+}
-+
-+
-+/** Writes PE internal data memory (DMEM) from the host
-+ * through indirect access registers.
-+ * @param[in] id PE identification (CLASS0_ID, ..., TMU0_ID, ..., UTIL_ID)
-+ * @param[in] addr DMEM write address (must be aligned on size)
-+ * @param[in] val Value to write (in PE endianess, i.e BE)
-+ * @param[in] size Number of bytes to write (maximum 4, must not cross 32bit boundaries)
-+ */
-+void pe_dmem_write(int id, u32 val, u32 addr, u8 size)
-+{
-+ u32 offset = addr & 0x3;
-+
-+ addr = pe[id].dmem_base_addr | (addr & ~0x3) | PE_MEM_ACCESS_WRITE | PE_MEM_ACCESS_DMEM | PE_MEM_ACCESS_BYTE_ENABLE(offset, size);
-+
-+ /* Indirect access interface is byte swapping data being written */
-+ writel(cpu_to_be32(val << (offset << 3)), pe[id].mem_access_wdata);
-+ writel(addr, pe[id].mem_access_addr);
-+}
-+
-+
-+/** Reads PE internal data memory (DMEM) from the host
-+ * through indirect access registers.
-+ * @param[in] id PE identification (CLASS0_ID, ..., TMU0_ID, ..., UTIL_ID)
-+ * @param[in] addr DMEM read address (must be aligned on size)
-+ * @param[in] size Number of bytes to read (maximum 4, must not cross 32bit boundaries)
-+ * @return the data read (in PE endianess, i.e BE).
-+ */
-+u32 pe_dmem_read(int id, u32 addr, u8 size)
-+{
-+ u32 offset = addr & 0x3;
-+ u32 mask = 0xffffffff >> ((4 - size) << 3);
-+ u32 val;
-+
-+ addr = pe[id].dmem_base_addr | (addr & ~0x3) | PE_MEM_ACCESS_READ | PE_MEM_ACCESS_DMEM | PE_MEM_ACCESS_BYTE_ENABLE(offset, size);
-+
-+ writel(addr, pe[id].mem_access_addr);
-+
-+ /* Indirect access interface is byte swapping data being read */
-+ val = be32_to_cpu(readl(pe[id].mem_access_rdata));
-+
-+ return (val >> (offset << 3)) & mask;
-+}
-+
-+/** This function is used to write to CLASS internal bus peripherals (ccu, pe-lem) from the host
-+* through indirect access registers.
-+* @param[in] val value to write
-+* @param[in] addr Address to write to (must be aligned on size)
-+* @param[in] size Number of bytes to write (1, 2 or 4)
-+*
-+*/
-+void class_bus_write(u32 val, u32 addr, u8 size)
-+{
-+ u32 offset = addr & 0x3;
-+
-+ writel((addr & CLASS_BUS_ACCESS_BASE_MASK), CLASS_BUS_ACCESS_BASE);
-+
-+ addr = (addr & ~CLASS_BUS_ACCESS_BASE_MASK) | PE_MEM_ACCESS_WRITE | (size << 24);
-+
-+ writel(cpu_to_be32(val << (offset << 3)), CLASS_BUS_ACCESS_WDATA);
-+ writel(addr, CLASS_BUS_ACCESS_ADDR);
-+}
-+
-+
-+/** Reads from CLASS internal bus peripherals (ccu, pe-lem) from the host
-+* through indirect access registers.
-+* @param[in] addr Address to read from (must be aligned on size)
-+* @param[in] size Number of bytes to read (1, 2 or 4)
-+* @return the read data
-+*
-+*/
-+u32 class_bus_read(u32 addr, u8 size)
-+{
-+ u32 offset = addr & 0x3;
-+ u32 mask = 0xffffffff >> ((4 - size) << 3);
-+ u32 val;
-+
-+ writel((addr & CLASS_BUS_ACCESS_BASE_MASK), CLASS_BUS_ACCESS_BASE);
-+
-+ addr = (addr & ~CLASS_BUS_ACCESS_BASE_MASK) | (size << 24);
-+
-+ writel(addr, CLASS_BUS_ACCESS_ADDR);
-+ val = be32_to_cpu(readl(CLASS_BUS_ACCESS_RDATA));
-+
-+ return (val >> (offset << 3)) & mask;
-+}
-+
-+/** Writes data to the cluster memory (PE_LMEM)
-+* @param[in] dst PE LMEM destination address (must be 32bit aligned)
-+* @param[in] src Buffer source address
-+* @param[in] len Number of bytes to copy
-+*/
-+void class_pe_lmem_memcpy_to32(u32 dst, const void *src, unsigned int len)
-+{
-+ u32 len32 = len >> 2;
-+ int i;
-+
-+ for (i = 0; i < len32; i++, src += 4, dst += 4)
-+ class_bus_write(*(u32 *)src, dst, 4);
-+
-+ if (len & 0x2)
-+ {
-+ class_bus_write(*(u16 *)src, dst, 2);
-+ src += 2;
-+ dst += 2;
-+ }
-+
-+ if (len & 0x1)
-+ {
-+ class_bus_write(*(u8 *)src, dst, 1);
-+ src++;
-+ dst++;
-+ }
-+}
-+
-+/** Writes value to the cluster memory (PE_LMEM)
-+* @param[in] dst PE LMEM destination address (must be 32bit aligned)
-+* @param[in] val Value to write
-+* @param[in] len Number of bytes to write
-+*/
-+void class_pe_lmem_memset(u32 dst, int val, unsigned int len)
-+{
-+ u32 len32 = len >> 2;
-+ int i;
-+
-+ val = val | (val << 8) | (val << 16) | (val << 24);
-+
-+ for (i = 0; i < len32; i++, dst += 4)
-+ class_bus_write(val, dst, 4);
-+
-+ if (len & 0x2)
-+ {
-+ class_bus_write(val, dst, 2);
-+ dst += 2;
-+ }
-+
-+ if (len & 0x1)
-+ {
-+ class_bus_write(val, dst, 1);
-+ dst++;
-+ }
-+}
-+
-+/** Reads data from the cluster memory (PE_LMEM)
-+* @param[out] dst pointer to the source buffer data are copied to
-+* @param[in] len length in bytes of the amount of data to read from cluster memory
-+* @param[in] offset offset in bytes in the cluster memory where data are read from
-+*/
-+void pe_lmem_read(u32 *dst, u32 len, u32 offset)
-+{
-+ u32 len32 = len >> 2;
-+ int i = 0;
-+
-+ for (i = 0; i < len32; dst++, i++, offset += 4)
-+ *dst = class_bus_read(PE_LMEM_BASE_ADDR + offset, 4);
-+
-+ /* FIXME we may have an out of bounds access on dst */
-+ if (len & 0x03)
-+ *dst = class_bus_read(PE_LMEM_BASE_ADDR + offset, (len & 0x03));
-+}
-+
-+/** Writes data to the cluster memory (PE_LMEM)
-+* @param[in] src pointer to the source buffer data are copied from
-+* @param[in] len length in bytes of the amount of data to write to the cluster memory
-+* @param[in] offset offset in bytes in the cluster memory where data are written to
-+*/
-+void pe_lmem_write(u32 *src, u32 len, u32 offset)
-+{
-+ u32 len32 = len >> 2;
-+ int i = 0;
-+
-+ for (i = 0; i < len32; src++, i++, offset += 4)
-+ class_bus_write(*src, PE_LMEM_BASE_ADDR + offset, 4);
-+
-+ /* FIXME we may have an out of bounds access on src */
-+ if (len & 0x03)
-+ class_bus_write(*src, PE_LMEM_BASE_ADDR + offset, (len & 0x03));
-+}
-+
-+/** Writes UTIL program memory (DDR) from the host.
-+ *
-+ * @param[in] addr Address to write (virtual, must be aligned on size)
-+ * @param[in] val Value to write (in PE endianess, i.e BE)
-+ * @param[in] size Number of bytes to write (2 or 4)
-+ */
-+static void util_pmem_write(u32 val, void *addr, u8 size)
-+{
-+ void *addr64 = (void *)((unsigned long)addr & ~0x7);
-+ unsigned long off = 8 - ((unsigned long)addr & 0x7) - size;
-+
-+ //IMEM should be loaded as a 64bit swapped value in a 64bit aligned location
-+ if (size == 4)
-+ writel(be32_to_cpu(val), addr64 + off);
-+ else
-+ writew(be16_to_cpu((u16)val), addr64 + off);
-+}
-+
-+
-+/** Writes a buffer to UTIL program memory (DDR) from the host.
-+ *
-+ * @param[in] dst Address to write (virtual, must be at least 16bit aligned)
-+ * @param[in] src Buffer to write (in PE endianess, i.e BE, must have same alignment as dst)
-+ * @param[in] len Number of bytes to write (must be at least 16bit aligned)
-+ */
-+static void util_pmem_memcpy(void *dst, const void *src, unsigned int len)
-+{
-+ unsigned int len32;
-+ int i;
-+
-+ if ((unsigned long)src & 0x2) {
-+ util_pmem_write(*(u16 *)src, dst, 2);
-+ src += 2;
-+ dst += 2;
-+ len -= 2;
-+ }
-+
-+ len32 = len >> 2;
-+
-+ for (i = 0; i < len32; i++, dst += 4, src += 4)
-+ util_pmem_write(*(u32 *)src, dst, 4);
-+
-+ if (len & 0x2)
-+ util_pmem_write(*(u16 *)src, dst, len & 0x2);
-+}
-+
-+
-+/** Loads an elf section into pmem
-+ * Code needs to be at least 16bit aligned and only PROGBITS sections are supported
-+ *
-+ * @param[in] id PE identification (CLASS0_ID, ..., TMU0_ID, ..., TMU3_ID)
-+ * @param[in] data pointer to the elf firmware
-+ * @param[in] shdr pointer to the elf section header
-+ *
-+ */
-+static int pe_load_pmem_section(int id, const void *data, Elf32_Shdr *shdr)
-+{
-+ u32 offset = be32_to_cpu(shdr->sh_offset);
-+ u32 addr = be32_to_cpu(shdr->sh_addr);
-+ u32 size = be32_to_cpu(shdr->sh_size);
-+ u32 type = be32_to_cpu(shdr->sh_type);
-+
-+#if !defined(CONFIG_UTIL_PE_DISABLED)
-+ if (id == UTIL_ID)
-+ {
-+ printf("%s: unsuported pmem section for UTIL\n", __func__);
-+ return -1;
-+ }
-+#endif
-+
-+ if (((unsigned long)(data + offset) & 0x3) != (addr & 0x3))
-+ {
-+ printf("%s: load address(%x) and elf file address(%lx) don't have the same alignment\n",
-+ __func__, addr, (unsigned long) data + offset);
-+
-+ return -1;
-+ }
-+
-+ if (addr & 0x1)
-+ {
-+ printf("%s: load address(%x) is not 16bit aligned\n", __func__, addr);
-+ return -1;
-+ }
-+
-+ if (size & 0x1)
-+ {
-+ printf("%s: load size(%x) is not 16bit aligned\n", __func__, size);
-+ return -1;
-+ }
-+
-+ dprintf("pmem pe%d @%x len %d\n",id, addr, size);
-+ switch (type)
-+ {
-+ case SHT_PROGBITS:
-+ pe_pmem_memcpy_to32(id, addr, data + offset, size);
-+ break;
-+
-+ default:
-+ printf("%s: unsuported section type(%x)\n", __func__, type);
-+ return -1;
-+ break;
-+ }
-+
-+ return 0;
-+}
-+
-+
-+/** Loads an elf section into dmem
-+ * Data needs to be at least 32bit aligned, NOBITS sections are correctly initialized to 0
-+ *
-+ * @param[in] id PE identification (CLASS0_ID, ..., TMU0_ID, ..., UTIL_ID)
-+ * @param[in] data pointer to the elf firmware
-+ * @param[in] shdr pointer to the elf section header
-+ *
-+ */
-+static int pe_load_dmem_section(int id, const void *data, Elf32_Shdr *shdr)
-+{
-+ u32 offset = be32_to_cpu(shdr->sh_offset);
-+ u32 addr = be32_to_cpu(shdr->sh_addr);
-+ u32 size = be32_to_cpu(shdr->sh_size);
-+ u32 type = be32_to_cpu(shdr->sh_type);
-+ u32 size32 = size >> 2;
-+ int i;
-+
-+ if (((unsigned long)(data + offset) & 0x3) != (addr & 0x3))
-+ {
-+ printf("%s: load address(%x) and elf file address(%lx) don't have the same alignment\n",
-+ __func__, addr, (unsigned long)data + offset);
-+
-+ return -1;
-+ }
-+
-+ if (addr & 0x3)
-+ {
-+ printf("%s: load address(%x) is not 32bit aligned\n", __func__, addr);
-+ return -1;
-+ }
-+
-+ switch (type)
-+ {
-+ case SHT_PROGBITS:
-+ dprintf("dmem pe%d @%x len %d\n",id, addr, size);
-+ pe_dmem_memcpy_to32(id, addr, data + offset, size);
-+ break;
-+
-+ case SHT_NOBITS:
-+ dprintf("dmem zero pe%d @%x len %d\n",id, addr, size);
-+ for (i = 0; i < size32; i++, addr += 4)
-+ pe_dmem_write(id, 0, addr, 4);
-+
-+ if (size & 0x3)
-+ pe_dmem_write(id, 0, addr, size & 0x3);
-+
-+ break;
-+
-+ default:
-+ printf("%s: unsuported section type(%x)\n", __func__, type);
-+ return -1;
-+ break;
-+ }
-+
-+ return 0;
-+}
-+
-+
-+/** Loads an elf section into DDR
-+ * Data needs to be at least 32bit aligned, NOBITS sections are correctly initialized to 0
-+ *
-+ * @param[in] id PE identification (CLASS0_ID, ..., TMU0_ID, ..., UTIL_ID)
-+ * @param[in] data pointer to the elf firmware
-+ * @param[in] shdr pointer to the elf section header
-+ *
-+ */
-+static int pe_load_ddr_section(int id, const void *data, Elf32_Shdr *shdr)
-+{
-+ u32 offset = be32_to_cpu(shdr->sh_offset);
-+ u32 addr = be32_to_cpu(shdr->sh_addr);
-+ u32 size = be32_to_cpu(shdr->sh_size);
-+ u32 type = be32_to_cpu(shdr->sh_type);
-+ u32 flags = be32_to_cpu(shdr->sh_flags);
-+
-+ switch (type)
-+ {
-+ case SHT_PROGBITS:
-+ dprintf("ddr pe%d @%x len %d\n",id, addr, size);
-+ if (flags & SHF_EXECINSTR)
-+ {
-+ if (id <= CLASS_MAX_ID)
-+ {
-+ /* DO the loading only once in DDR */
-+ if (id == CLASS0_ID)
-+ {
-+ dprintf("%s: load address(%x) and elf file address(%lx) rcvd\n", __func__, addr, (unsigned long)data + offset);
-+ if (((unsigned long)(data + offset) & 0x3) != (addr & 0x3))
-+ {
-+ printf("%s: load address(%x) and elf file address(%lx) don't have the same alignment\n",
-+ __func__, addr, (unsigned long)data + offset);
-+
-+ return -1;
-+ }
-+
-+ if (addr & 0x1)
-+ {
-+ printf("%s: load address(%x) is not 16bit aligned\n", __func__, addr);
-+ return -1;
-+ }
-+
-+ if (size & 0x1)
-+ {
-+ printf("%s: load length(%x) is not 16bit aligned\n", __func__, size);
-+ return -1;
-+ }
-+
-+ memcpy(DDR_PFE_TO_VIRT(addr), data + offset, size);
-+ }
-+ }
-+
-+#if !defined(CONFIG_UTIL_PE_DISABLED)
-+ else if (id == UTIL_ID)
-+ {
-+ if (((unsigned long)(data + offset) & 0x3) != (addr & 0x3))
-+ {
-+ printf("%s: load address(%x) and elf file address(%lx) don't have the same alignment\n",
-+ __func__, addr, (unsigned long)data + offset);
-+
-+ return -1;
-+ }
-+
-+ if (addr & 0x1)
-+ {
-+ printf("%s: load address(%x) is not 16bit aligned\n", __func__, addr);
-+ return -1;
-+ }
-+
-+ if (size & 0x1)
-+ {
-+ printf("%s: load length(%x) is not 16bit aligned\n", __func__, size);
-+ return -1;
-+ }
-+
-+ util_pmem_memcpy((void *)DDR_PFE_TO_VIRT(addr), data + offset, size);
-+ }
-+#endif
-+ else
-+ {
-+ printf("%s: unsuported ddr section type(%x) for PE(%d)\n", __func__, type, id);
-+ return -1;
-+ }
-+
-+ }
-+ else
-+ {
-+ memcpy(DDR_PFE_TO_VIRT(addr), data + offset, size);
-+ }
-+
-+ break;
-+
-+ case SHT_NOBITS:
-+ dprintf("ddr zero pe%d @%x len %d\n",id, addr, size);
-+ memset((void *)DDR_PFE_TO_VIRT(addr), 0, size);
-+
-+ break;
-+
-+ default:
-+ printf("%s: unsuported section type(%x)\n", __func__, type);
-+ return -1;
-+ break;
-+ }
-+
-+ return 0;
-+}
-+
-+/** Loads an elf section into pe lmem
-+ * Data needs to be at least 32bit aligned, NOBITS sections are correctly initialized to 0
-+ *
-+ * @param[in] id PE identification (CLASS0_ID,..., CLASS5_ID)
-+ * @param[in] data pointer to the elf firmware
-+ * @param[in] shdr pointer to the elf section header
-+ *
-+ */
-+static int pe_load_pe_lmem_section(int id, const void *data, Elf32_Shdr *shdr)
-+{
-+ u32 offset = be32_to_cpu(shdr->sh_offset);
-+ u32 addr = be32_to_cpu(shdr->sh_addr);
-+ u32 size = be32_to_cpu(shdr->sh_size);
-+ u32 type = be32_to_cpu(shdr->sh_type);
-+
-+ if (id > CLASS_MAX_ID)
-+ {
-+ printf("%s: unsuported pe-lmem section type(%x) for PE(%d)\n", __func__, type, id);
-+ return -1;
-+ }
-+
-+ if (((unsigned long)(data + offset) & 0x3) != (addr & 0x3))
-+ {
-+ printf("%s: load address(%x) and elf file address(%lx) don't have the same alignment\n",
-+ __func__, addr, (unsigned long)data + offset);
-+
-+ return -1;
-+ }
-+
-+ if (addr & 0x3)
-+ {
-+ printf("%s: load address(%x) is not 32bit aligned\n", __func__, addr);
-+ return -1;
-+ }
-+ dprintf("lmem pe%d @%x len %d\n",id, addr, size);
-+ switch (type)
-+ {
-+ case SHT_PROGBITS:
-+ class_pe_lmem_memcpy_to32(addr, data + offset, size);
-+ break;
-+
-+ case SHT_NOBITS:
-+ class_pe_lmem_memset(addr, 0, size);
-+ break;
-+
-+ default:
-+ printf("%s: unsuported section type(%x)\n", __func__, type);
-+ return -1;
-+ break;
-+ }
-+
-+ return 0;
-+}
-+
-+
-+/** Loads an elf section into a PE
-+ * For now only supports loading a section to dmem (all PE's), pmem (class and tmu PE's),
-+ * DDDR (util PE code)
-+ *
-+ * @param[in] id PE identification (CLASS0_ID, ..., TMU0_ID, ..., UTIL_ID)
-+ * @param[in] data pointer to the elf firmware
-+ * @param[in] shdr pointer to the elf section header
-+ *
-+ */
-+int pe_load_elf_section(int id, const void *data, Elf32_Shdr *shdr)
-+{
-+ u32 addr = be32_to_cpu(shdr->sh_addr);
-+ u32 size = be32_to_cpu(shdr->sh_size);
-+
-+ //printf(".");
-+ if (IS_DMEM(addr, size))
-+ return pe_load_dmem_section(id, data, shdr);
-+ else if (IS_PMEM(addr, size))
-+ return pe_load_pmem_section(id, data, shdr);
-+ else if (IS_PFE_LMEM(addr, size))
-+ return 0; /* FIXME */
-+ else if (IS_PHYS_DDR(addr, size))
-+ return pe_load_ddr_section(id, data, shdr);
-+ else if (IS_PE_LMEM(addr, size))
-+ return pe_load_pe_lmem_section(id, data, shdr);
-+ else {
-+ printf("%s: unsuported memory range(%x)\n", __func__, addr);
-+ /*FIXME this should be remove after testing UTIL from 0x20000 */
-+ //printf("loading DDR section \n");
-+ //return pe_load_ddr_section(id, data, shdr);
-+// return -1;
-+ }
-+
-+ return 0;
-+}
-+
-+/** This function is used to write to UTIL internal bus peripherals from the host
-+* through indirect access registers.
-+* @param[in] val 32bits value to write
-+* @param[in] addr Address to write to
-+* @param[in] size Number of bytes to write
-+*
-+*/
-+void util_bus_write(u32 val, u32 addr, u8 size)
-+{
-+ u32 offset = addr & 0x3;
-+ u32 access_addr;
-+
-+ access_addr = ((addr & ~0x3) & CLASS_BUS_ACCESS_ADDR_MASK) | PE_MEM_ACCESS_WRITE | PE_MEM_ACCESS_BYTE_ENABLE(offset, size);
-+
-+// writel((addr & CLASS_BUS_ACCESS_BASE_MASK), CLASS_BUS_ACCESS_BASE);
-+
-+ writel(cpu_to_be32(val << (offset << 3)), UTIL_BUS_ACCESS_WDATA);
-+ writel(access_addr, UTIL_BUS_ACCESS_ADDR);
-+}
-+
-+
-+/** Reads from UTIL internal bus peripherals from the host
-+* through indirect access registers.
-+* @param[in] addr Address to read from
-+* @param[in] size Number of bytes to read
-+* @return the read data
-+*
-+*/
-+u32 util_bus_read(u32 addr, u8 size)
-+{
-+ u32 offset = addr & 0x3;
-+ u32 mask = 0xffffffff >> ((4 - size) << 3);
-+ u32 access_addr, val;
-+
-+ access_addr = ((addr & ~0x3) & CLASS_BUS_ACCESS_ADDR_MASK) | PE_MEM_ACCESS_READ | PE_MEM_ACCESS_BYTE_ENABLE(offset, size);
-+
-+// writel((addr & CLASS_BUS_ACCESS_BASE_MASK), CLASS_BUS_ACCESS_BASE);
-+
-+ writel(access_addr, UTIL_BUS_ACCESS_ADDR);
-+ val = be32_to_cpu(readl(UTIL_BUS_ACCESS_RDATA));
-+
-+ return (val >> (offset << 3)) & mask;
-+}
-+
-+
-+
-+/**************************** BMU ***************************/
-+
-+/** Initializes a BMU block.
-+* @param[in] base BMU block base address
-+* @param[in] cfg BMU configuration
-+*/
-+void bmu_init(void *base, BMU_CFG *cfg)
-+{
-+
-+ bmu_disable(base);
-+
-+ bmu_set_config(base, cfg);
-+
-+ bmu_reset(base);
-+}
-+
-+/** Resets a BMU block.
-+* @param[in] base BMU block base address
-+*/
-+void bmu_reset(void *base)
-+{
-+ writel(CORE_SW_RESET, base + BMU_CTRL);
-+
-+ /* Wait for self clear */
-+ while (readl(base + BMU_CTRL) & CORE_SW_RESET) ;
-+}
-+
-+/** Enabled a BMU block.
-+* @param[in] base BMU block base address
-+*/
-+void bmu_enable(void *base)
-+{
-+ writel (CORE_ENABLE, base + BMU_CTRL);
-+}
-+
-+/** Disables a BMU block.
-+* @param[in] base BMU block base address
-+*/
-+void bmu_disable(void *base)
-+{
-+ writel (CORE_DISABLE, base + BMU_CTRL);
-+}
-+
-+/** Sets the configuration of a BMU block.
-+* @param[in] base BMU block base address
-+* @param[in] cfg BMU configuration
-+*/
-+void bmu_set_config(void *base, BMU_CFG *cfg)
-+{
-+ writel (cfg->baseaddr, base + BMU_UCAST_BASE_ADDR);
-+ writel (cfg->count & 0xffff, base + BMU_UCAST_CONFIG);
-+ writel (cfg->size & 0xffff, base + BMU_BUF_SIZE);
-+// writel (BMU1_THRES_CNT, base + BMU_THRES);
-+
-+ /* Interrupts are never used */
-+// writel (0x0, base + BMU_INT_SRC);
-+ writel (0x0, base + BMU_INT_ENABLE);
-+}
-+
-+
-+#if 0 //These are LS1012A functions
-+/**************************** GEMAC ***************************/
-+
-+/** GEMAC block initialization.
-+* @param[in] base GEMAC base address (GEMAC0, GEMAC1, GEMAC2)
-+* @param[in] cfg GEMAC configuration
-+*/
-+void gemac_init(void *base, void *cfg)
-+{
-+ gemac_set_config(base, cfg);
-+ gemac_set_bus_width(base, 64);
-+}
-+
-+/** GEMAC set speed.
-+* @param[in] base GEMAC base address
-+* @param[in] speed GEMAC speed (10, 100 or 1000 Mbps)
-+*/
-+void gemac_set_speed(void *base, MAC_SPEED gem_speed)
-+{
-+ u32 val = readl(base + EMAC_NETWORK_CONFIG);
-+
-+ val = val & ~EMAC_SPEED_MASK;
-+
-+ switch (gem_speed)
-+ {
-+ case SPEED_10M:
-+ val &= (~EMAC_PCS_ENABLE);
-+ break;
-+
-+ case SPEED_100M:
-+ val = val | EMAC_SPEED_100;
-+ val &= (~EMAC_PCS_ENABLE);
-+ break;
-+
-+ case SPEED_1000M:
-+ val = val | EMAC_SPEED_1000;
-+ val &= (~EMAC_PCS_ENABLE);
-+ break;
-+
-+ case SPEED_1000M_PCS:
-+ val = val | EMAC_SPEED_1000;
-+ val |= EMAC_PCS_ENABLE;
-+ break;
-+
-+ default:
-+ val = val | EMAC_SPEED_100;
-+ val &= (~EMAC_PCS_ENABLE);
-+ break;
-+ }
-+
-+ writel (val, base + EMAC_NETWORK_CONFIG);
-+}
-+
-+/** GEMAC set duplex.
-+* @param[in] base GEMAC base address
-+* @param[in] duplex GEMAC duplex mode (Full, Half)
-+*/
-+void gemac_set_duplex(void *base, int duplex)
-+{
-+ u32 val = readl(base + EMAC_NETWORK_CONFIG);
-+
-+ if (duplex == DUPLEX_HALF)
-+ val = (val & ~EMAC_DUPLEX_MASK) | EMAC_HALF_DUP;
-+ else
-+ val = (val & ~EMAC_DUPLEX_MASK) | EMAC_FULL_DUP;
-+
-+ writel (val, base + EMAC_NETWORK_CONFIG);
-+}
-+
-+/** GEMAC set mode.
-+* @param[in] base GEMAC base address
-+* @param[in] mode GEMAC operation mode (MII, RMII, RGMII, SGMII)
-+*/
-+void gemac_set_mode(void *base, int mode)
-+{
-+ switch (mode)
-+ {
-+ case GMII:
-+ writel ((readl(base + EMAC_CONTROL) & ~EMAC_MODE_MASK) | EMAC_GMII_MODE_ENABLE, base + EMAC_CONTROL);
-+ writel (readl(base + EMAC_NETWORK_CONFIG) & (~EMAC_SGMII_MODE_ENABLE), base + EMAC_NETWORK_CONFIG);
-+ break;
-+
-+ case RGMII:
-+ writel ((readl(base + EMAC_CONTROL) & ~EMAC_MODE_MASK) | EMAC_RGMII_MODE_ENABLE, base + EMAC_CONTROL);
-+ writel (readl(base + EMAC_NETWORK_CONFIG) & (~EMAC_SGMII_MODE_ENABLE), base + EMAC_NETWORK_CONFIG);
-+ break;
-+
-+ case RMII:
-+ writel ((readl(base + EMAC_CONTROL) & ~EMAC_MODE_MASK) | EMAC_RMII_MODE_ENABLE, base + EMAC_CONTROL);
-+ writel (readl(base + EMAC_NETWORK_CONFIG) & (~EMAC_SGMII_MODE_ENABLE), base + EMAC_NETWORK_CONFIG);
-+ break;
-+
-+ case MII:
-+ writel ((readl(base + EMAC_CONTROL) & ~EMAC_MODE_MASK) | EMAC_MII_MODE_ENABLE, base + EMAC_CONTROL);
-+ writel (readl(base + EMAC_NETWORK_CONFIG) & (~EMAC_SGMII_MODE_ENABLE), base + EMAC_NETWORK_CONFIG);
-+ break;
-+
-+ case SGMII:
-+ writel ((readl(base + EMAC_CONTROL) & ~EMAC_MODE_MASK) | (EMAC_RMII_MODE_DISABLE | EMAC_RGMII_MODE_DISABLE), base + EMAC_CONTROL);
-+ writel (readl(base + EMAC_NETWORK_CONFIG) | EMAC_SGMII_MODE_ENABLE, base + EMAC_NETWORK_CONFIG);
-+ break;
-+
-+ default:
-+ writel ((readl(base + EMAC_CONTROL) & ~EMAC_MODE_MASK) | EMAC_MII_MODE_ENABLE, base + EMAC_CONTROL);
-+ writel (readl(base + EMAC_NETWORK_CONFIG) & (~EMAC_SGMII_MODE_ENABLE), base + EMAC_NETWORK_CONFIG);
-+ break;
-+ }
-+}
-+
-+/** GEMAC Enable MDIO: Activate the Management interface. This is required to program the PHY
-+ * @param[in] base GEMAC base address
-+ */
-+void gemac_enable_mdio(void *base)
-+{
-+ u32 data;
-+
-+ data = readl(base + EMAC_NETWORK_CONTROL);
-+ data |= EMAC_MDIO_EN;
-+ writel(data, base + EMAC_NETWORK_CONTROL);
-+}
-+
-+/** GEMAC Disable MDIO: Disable the Management interface.
-+ * @param[in] base GEMAC base address
-+ */
-+void gemac_disable_mdio(void *base)
-+{
-+ u32 data;
-+
-+ data = readl(base + EMAC_NETWORK_CONTROL);
-+ data &= ~EMAC_MDIO_EN;
-+ writel(data, base + EMAC_NETWORK_CONTROL);
-+}
-+
-+/** GEMAC Set MDC clock division
-+ * @param[in] base GEMAC base address
-+ * @param[in] base MDC divider value
-+ */
-+void gemac_set_mdc_div(void *base, MAC_MDC_DIV gem_mdcdiv)
-+{
-+ u32 data;
-+
-+ data = readl(base + EMAC_NETWORK_CONFIG);
-+ data &= ~(MDC_DIV_MASK << MDC_DIV_SHIFT);
-+ data |= (gem_mdcdiv & MDC_DIV_MASK) << MDC_DIV_SHIFT;
-+ writel(data, base + EMAC_NETWORK_CONFIG);
-+}
-+
-+/** GEMAC reset function.
-+* @param[in] base GEMAC base address
-+*/
-+void gemac_reset(void *base)
-+{
-+}
-+
-+/** GEMAC enable function.
-+* @param[in] base GEMAC base address
-+*/
-+void gemac_enable(void *base)
-+{
-+ writel (readl(base + EMAC_NETWORK_CONTROL) | EMAC_TX_ENABLE | EMAC_RX_ENABLE, base + EMAC_NETWORK_CONTROL);
-+}
-+
-+/** GEMAC disable function.
-+* @param[in] base GEMAC base address
-+*/
-+void gemac_disable(void *base)
-+{
-+ writel (readl(base + EMAC_NETWORK_CONTROL) & ~(EMAC_TX_ENABLE | EMAC_RX_ENABLE), base + EMAC_NETWORK_CONTROL);
-+}
-+
-+/** GEMAC set mac address configuration.
-+* @param[in] base GEMAC base address
-+* @param[in] addr MAC address to be configured
-+*/
-+void gemac_set_address(void *base, SPEC_ADDR *addr)
-+{
-+ writel(addr->one.bottom, base + EMAC_SPEC1_ADD_BOT);
-+ writel(addr->one.top, base + EMAC_SPEC1_ADD_TOP);
-+ writel(addr->two.bottom, base + EMAC_SPEC2_ADD_BOT);
-+ writel(addr->two.top, base + EMAC_SPEC2_ADD_TOP);
-+ writel(addr->three.bottom, base + EMAC_SPEC3_ADD_BOT);
-+ writel(addr->three.top, base + EMAC_SPEC3_ADD_TOP);
-+ writel(addr->four.bottom, base + EMAC_SPEC4_ADD_BOT);
-+ writel(addr->four.top, base + EMAC_SPEC4_ADD_TOP);
-+}
-+
-+/** GEMAC get mac address configuration.
-+* @param[in] base GEMAC base address
-+*
-+* @return MAC addresses configured
-+*/
-+SPEC_ADDR gemac_get_address(void *base)
-+{
-+ SPEC_ADDR addr;
-+
-+ addr.one.bottom = readl(base + EMAC_SPEC1_ADD_BOT);
-+ addr.one.top = readl(base + EMAC_SPEC1_ADD_TOP);
-+ addr.two.bottom = readl(base + EMAC_SPEC2_ADD_BOT);
-+ addr.two.top = readl(base + EMAC_SPEC2_ADD_TOP);
-+ addr.three.bottom = readl(base + EMAC_SPEC3_ADD_BOT);
-+ addr.three.top = readl(base + EMAC_SPEC3_ADD_TOP);
-+ addr.four.bottom = readl(base + EMAC_SPEC4_ADD_BOT);
-+ addr.four.top = readl(base + EMAC_SPEC4_ADD_TOP);
-+
-+ return addr;
-+}
-+
-+/** GEMAC set specific local addresses of the MAC.
-+* Rather than setting up all four specific addresses, this function sets them up individually.
-+*
-+* @param[in] base GEMAC base address
-+* @param[in] addr MAC address to be configured
-+*/
-+void gemac_set_laddr1(void *base, MAC_ADDR *address)
-+{
-+ writel(address->bottom, base + EMAC_SPEC1_ADD_BOT);
-+ writel(address->top, base + EMAC_SPEC1_ADD_TOP);
-+}
-+
-+
-+void gemac_set_laddr2(void *base, MAC_ADDR *address)
-+{
-+ writel(address->bottom, base + EMAC_SPEC2_ADD_BOT);
-+ writel(address->top, base + EMAC_SPEC2_ADD_TOP);
-+}
-+
-+
-+void gemac_set_laddr3(void *base, MAC_ADDR *address)
-+{
-+ writel(address->bottom, base + EMAC_SPEC3_ADD_BOT);
-+ writel(address->top, base + EMAC_SPEC3_ADD_TOP);
-+}
-+
-+
-+void gemac_set_laddr4(void *base, MAC_ADDR *address)
-+{
-+ writel(address->bottom, base + EMAC_SPEC4_ADD_BOT);
-+ writel(address->top, base + EMAC_SPEC4_ADD_TOP);
-+}
-+
-+void gemac_set_laddrN(void *base, MAC_ADDR *address, unsigned int entry_index)
-+{
-+ if (entry_index < 5)
-+ {
-+ writel(address->bottom, base + (entry_index * 8) + EMAC_SPEC1_ADD_BOT);
-+ writel(address->top, base + (entry_index * 8) + EMAC_SPEC1_ADD_TOP);
-+ }
-+ else
-+ {
-+ writel(address->bottom, base + ((entry_index - 5) * 8) + EMAC_SPEC5_ADD_BOT);
-+ writel(address->top, base + ((entry_index - 5) * 8) + EMAC_SPEC5_ADD_TOP);
-+ }
-+}
-+
-+/** Get specific local addresses of the MAC.
-+* This allows returning of a single specific address stored in the MAC.
-+* @param[in] base GEMAC base address
-+*
-+* @return Specific MAC address 1
-+*
-+*/
-+MAC_ADDR gem_get_laddr1(void *base)
-+{
-+ MAC_ADDR addr;
-+ addr.bottom = readl(base + EMAC_SPEC1_ADD_BOT);
-+ addr.top = readl(base + EMAC_SPEC1_ADD_TOP);
-+ return addr;
-+}
-+
-+
-+MAC_ADDR gem_get_laddr2(void *base)
-+{
-+ MAC_ADDR addr;
-+ addr.bottom = readl(base + EMAC_SPEC2_ADD_BOT);
-+ addr.top = readl(base + EMAC_SPEC2_ADD_TOP);
-+ return addr;
-+}
-+
-+
-+MAC_ADDR gem_get_laddr3(void *base)
-+{
-+ MAC_ADDR addr;
-+ addr.bottom = readl(base + EMAC_SPEC3_ADD_BOT);
-+ addr.top = readl(base + EMAC_SPEC3_ADD_TOP);
-+ return addr;
-+}
-+
-+
-+MAC_ADDR gem_get_laddr4(void *base)
-+{
-+ MAC_ADDR addr;
-+ addr.bottom = readl(base + EMAC_SPEC4_ADD_BOT);
-+ addr.top = readl(base + EMAC_SPEC4_ADD_TOP);
-+ return addr;
-+}
-+
-+
-+MAC_ADDR gem_get_laddrN(void *base, unsigned int entry_index)
-+{
-+ MAC_ADDR addr;
-+
-+ if (entry_index < 5)
-+ {
-+ addr.bottom = readl(base + (entry_index * 8) + EMAC_SPEC1_ADD_BOT);
-+ addr.top = readl(base + (entry_index * 8) + EMAC_SPEC1_ADD_TOP);
-+ }
-+ else
-+ {
-+ addr.bottom = readl(base + ((entry_index - 5) * 8) + EMAC_SPEC5_ADD_BOT);
-+ addr.top = readl(base + ((entry_index - 5) * 8) + EMAC_SPEC5_ADD_TOP);
-+ }
-+
-+ return addr;
-+}
-+
-+/** GEMAC allow frames
-+* @param[in] base GEMAC base address
-+*/
-+void gemac_enable_copy_all(void *base)
-+{
-+ writel (readl(base + EMAC_NETWORK_CONFIG) & EMAC_ENABLE_COPY_ALL, base + EMAC_NETWORK_CONFIG);
-+}
-+
-+/** GEMAC do not allow frames
-+* @param[in] base GEMAC base address
-+*/
-+void gemac_disable_copy_all(void *base)
-+{
-+ writel (readl(base + EMAC_NETWORK_CONFIG) & ~EMAC_ENABLE_COPY_ALL, base + EMAC_NETWORK_CONFIG);
-+}
-+
-+
-+
-+/** GEMAC allow broadcast function.
-+* @param[in] base GEMAC base address
-+*/
-+void gemac_allow_broadcast(void *base)
-+{
-+ writel (readl(base + EMAC_NETWORK_CONFIG) & ~EMAC_NO_BROADCAST, base + EMAC_NETWORK_CONFIG);
-+}
-+
-+/** GEMAC no broadcast function.
-+* @param[in] base GEMAC base address
-+*/
-+void gemac_no_broadcast(void *base)
-+{
-+ writel (readl(base + EMAC_NETWORK_CONFIG) | EMAC_NO_BROADCAST, base + EMAC_NETWORK_CONFIG);
-+}
-+
-+/** GEMAC enable unicast function.
-+* @param[in] base GEMAC base address
-+*/
-+void gemac_enable_unicast(void *base)
-+{
-+ writel (readl(base + EMAC_NETWORK_CONFIG) | EMAC_ENABLE_UNICAST, base + EMAC_NETWORK_CONFIG);
-+}
-+
-+/** GEMAC disable unicast function.
-+* @param[in] base GEMAC base address
-+*/
-+void gemac_disable_unicast(void *base)
-+{
-+ writel (readl(base + EMAC_NETWORK_CONFIG) & ~EMAC_ENABLE_UNICAST, base + EMAC_NETWORK_CONFIG);
-+}
-+
-+/** GEMAC enable multicast function.
-+* @param[in] base GEMAC base address
-+*/
-+void gemac_enable_multicast(void *base)
-+{
-+ writel (readl(base + EMAC_NETWORK_CONFIG) | EMAC_ENABLE_MULTICAST, base + EMAC_NETWORK_CONFIG);
-+}
-+
-+/** GEMAC disable multicast function.
-+* @param[in] base GEMAC base address
-+*/
-+void gemac_disable_multicast(void *base)
-+{
-+ writel (readl(base + EMAC_NETWORK_CONFIG) & ~EMAC_ENABLE_MULTICAST, base + EMAC_NETWORK_CONFIG);
-+}
-+
-+/** GEMAC enable fcs rx function.
-+* @param[in] base GEMAC base address
-+*/
-+void gemac_enable_fcs_rx(void *base)
-+{
-+ writel (readl(base + EMAC_NETWORK_CONFIG) | EMAC_ENABLE_FCS_RX, base + EMAC_NETWORK_CONFIG);
-+}
-+
-+/** GEMAC disable fcs rx function.
-+* @param[in] base GEMAC base address
-+*/
-+void gemac_disable_fcs_rx(void *base)
-+{
-+ writel (readl(base + EMAC_NETWORK_CONFIG) & ~EMAC_ENABLE_FCS_RX, base + EMAC_NETWORK_CONFIG);
-+}
-+
-+/** GEMAC enable 1536 rx function.
-+* @param[in] base GEMAC base address
-+*/
-+void gemac_enable_1536_rx(void *base)
-+{
-+ writel (readl(base + EMAC_NETWORK_CONFIG) | EMAC_ENABLE_1536_RX, base + EMAC_NETWORK_CONFIG);
-+}
-+
-+/** GEMAC disable 1536 rx function.
-+* @param[in] base GEMAC base address
-+*/
-+void gemac_disable_1536_rx(void *base)
-+{
-+ writel (readl(base + EMAC_NETWORK_CONFIG) & ~EMAC_ENABLE_1536_RX, base + EMAC_NETWORK_CONFIG);
-+}
-+
-+/** GEMAC enable pause rx function.
-+* @param[in] base GEMAC base address
-+*/
-+void gemac_enable_pause_rx(void *base)
-+{
-+ writel (readl(base + EMAC_NETWORK_CONFIG) | EMAC_ENABLE_PAUSE_RX, base + EMAC_NETWORK_CONFIG);
-+}
-+
-+/** GEMAC disable pause rx function.
-+* @param[in] base GEMAC base address
-+*/
-+void gemac_disable_pause_rx(void *base)
-+{
-+ writel (readl(base + EMAC_NETWORK_CONFIG) & ~EMAC_ENABLE_PAUSE_RX, base + EMAC_NETWORK_CONFIG);
-+}
-+
-+/** GEMAC enable rx checksum offload function.
-+* @param[in] base GEMAC base address
-+*/
-+void gemac_enable_rx_checksum_offload(void *base)
-+{
-+ writel(readl(base + EMAC_NETWORK_CONFIG) | EMAC_ENABLE_CHKSUM_RX, base + EMAC_NETWORK_CONFIG);
-+ writel(readl(CLASS_L4_CHKSUM_ADDR) | IPV4_CHKSUM_DROP, CLASS_L4_CHKSUM_ADDR);
-+}
-+
-+/** GEMAC disable rx checksum offload function.
-+* @param[in] base GEMAC base address
-+*/
-+void gemac_disable_rx_checksum_offload(void *base)
-+{
-+ writel(readl(base + EMAC_NETWORK_CONFIG) & ~EMAC_ENABLE_CHKSUM_RX, base + EMAC_NETWORK_CONFIG);
-+ writel(readl(CLASS_L4_CHKSUM_ADDR) & ~IPV4_CHKSUM_DROP, CLASS_L4_CHKSUM_ADDR);
-+}
-+
-+/** Sets Gemac bus width to 64bit
-+ * @param[in] base GEMAC base address
-+ * @param[in] width gemac bus width to be set possible values are 32/64/128
-+ * */
-+void gemac_set_bus_width(void *base, int width)
-+{
-+ u32 val = readl(base + EMAC_NETWORK_CONFIG);
-+ switch(width)
-+ {
-+ case 32:
-+ val = (val & ~EMAC_DATA_BUS_WIDTH_MASK) | EMAC_DATA_BUS_WIDTH_32;
-+ case 128:
-+ val = (val & ~EMAC_DATA_BUS_WIDTH_MASK) | EMAC_DATA_BUS_WIDTH_128;
-+ case 64:
-+ default:
-+ val = (val & ~EMAC_DATA_BUS_WIDTH_MASK) | EMAC_DATA_BUS_WIDTH_64;
-+
-+ }
-+ writel (val, base + EMAC_NETWORK_CONFIG);
-+}
-+
-+/** Sets Gemac configuration.
-+* @param[in] base GEMAC base address
-+* @param[in] cfg GEMAC configuration
-+*/
-+void gemac_set_config(void *base, GEMAC_CFG *cfg)
-+{
-+ gemac_set_mode(base, cfg->mode);
-+
-+ gemac_set_speed(base, cfg->speed);
-+
-+ gemac_set_duplex(base,cfg->duplex);
-+}
-+#endif
-+
-+/**************************** GPI ***************************/
-+
-+/** Initializes a GPI block.
-+* @param[in] base GPI base address
-+* @param[in] cfg GPI configuration
-+*/
-+void gpi_init(void *base, GPI_CFG *cfg)
-+{
-+ gpi_reset(base);
-+
-+ gpi_disable(base);
-+
-+ gpi_set_config(base, cfg);
-+}
-+
-+/** Resets a GPI block.
-+* @param[in] base GPI base address
-+*/
-+void gpi_reset(void *base)
-+{
-+ writel (CORE_SW_RESET, base + GPI_CTRL);
-+}
-+
-+/** Enables a GPI block.
-+* @param[in] base GPI base address
-+*/
-+void gpi_enable(void *base)
-+{
-+ writel (CORE_ENABLE, base + GPI_CTRL);
-+}
-+
-+/** Disables a GPI block.
-+* @param[in] base GPI base address
-+*/
-+void gpi_disable(void *base)
-+{
-+ writel (CORE_DISABLE, base + GPI_CTRL);
-+}
-+
-+
-+/** Sets the configuration of a GPI block.
-+* @param[in] base GPI base address
-+* @param[in] cfg GPI configuration
-+*/
-+void gpi_set_config(void *base, GPI_CFG *cfg)
-+{
-+ writel (CBUS_VIRT_TO_PFE(BMU1_BASE_ADDR + BMU_ALLOC_CTRL), base + GPI_LMEM_ALLOC_ADDR);
-+ writel (CBUS_VIRT_TO_PFE(BMU1_BASE_ADDR + BMU_FREE_CTRL), base + GPI_LMEM_FREE_ADDR);
-+ writel (CBUS_VIRT_TO_PFE(BMU2_BASE_ADDR + BMU_ALLOC_CTRL), base + GPI_DDR_ALLOC_ADDR);
-+ writel (CBUS_VIRT_TO_PFE(BMU2_BASE_ADDR + BMU_FREE_CTRL), base + GPI_DDR_FREE_ADDR);
-+ writel (CBUS_VIRT_TO_PFE(CLASS_INQ_PKTPTR), base + GPI_CLASS_ADDR);
-+ writel (DDR_HDR_SIZE, base + GPI_DDR_DATA_OFFSET);
-+ writel (LMEM_HDR_SIZE, base + GPI_LMEM_DATA_OFFSET);
-+ writel (0, base + GPI_LMEM_SEC_BUF_DATA_OFFSET);
-+ writel (0, base + GPI_DDR_SEC_BUF_DATA_OFFSET);
-+ writel ((DDR_HDR_SIZE << 16) | LMEM_HDR_SIZE, base + GPI_HDR_SIZE);
-+ writel ((DDR_BUF_SIZE << 16) | LMEM_BUF_SIZE, base + GPI_BUF_SIZE);
-+
-+ writel (((cfg->lmem_rtry_cnt << 16) | (GPI_DDR_BUF_EN << 1) | GPI_LMEM_BUF_EN), base + GPI_RX_CONFIG);
-+ writel (cfg->tmlf_txthres, base + GPI_TMLF_TX);
-+ writel (cfg->aseq_len, base + GPI_DTX_ASEQ);
-+}
-+
-+/**************************** CLASSIFIER ***************************/
-+
-+/** Initializes CLASSIFIER block.
-+* @param[in] cfg CLASSIFIER configuration
-+*/
-+void class_init(CLASS_CFG *cfg)
-+{
-+ class_reset();
-+
-+ class_disable();
-+
-+ class_set_config(cfg);
-+}
-+
-+/** Resets CLASSIFIER block.
-+*
-+*/
-+void class_reset(void)
-+{
-+ writel(CORE_SW_RESET, CLASS_TX_CTRL);
-+}
-+
-+/** Enables all CLASS-PE's cores.
-+*
-+*/
-+void class_enable(void)
-+{
-+ writel(CORE_ENABLE, CLASS_TX_CTRL);
-+}
-+
-+/** Disables all CLASS-PE's cores.
-+*
-+*/
-+void class_disable(void)
-+{
-+ writel(CORE_DISABLE, CLASS_TX_CTRL);
-+}
-+
-+/** Sets the configuration of the CLASSIFIER block.
-+* @param[in] cfg CLASSIFIER configuration
-+*/
-+void class_set_config(CLASS_CFG *cfg)
-+{
-+ if (PLL_CLK_EN == 0)
-+ writel(0x0, CLASS_PE_SYS_CLK_RATIO); // Clock ratio: for 1:1 the value is 0
-+ else
-+ writel(0x1, CLASS_PE_SYS_CLK_RATIO); // Clock ratio: for 1:2 the value is 1
-+
-+ writel((DDR_HDR_SIZE << 16) | LMEM_HDR_SIZE, CLASS_HDR_SIZE);
-+ writel(LMEM_BUF_SIZE, CLASS_LMEM_BUF_SIZE);
-+ writel(CLASS_ROUTE_ENTRY_SIZE(CLASS_ROUTE_SIZE) | CLASS_ROUTE_HASH_SIZE(cfg->route_table_hash_bits), CLASS_ROUTE_HASH_ENTRY_SIZE);
-+ writel(HASH_CRC_PORT_IP | QB2BUS_LE, CLASS_ROUTE_MULTI);
-+
-+ writel(cfg->route_table_baseaddr, CLASS_ROUTE_TABLE_BASE);
-+ memset((void *)DDR_PFE_TO_VIRT(cfg->route_table_baseaddr), 0, ROUTE_TABLE_SIZE);
-+
-+ writel(CLASS_PE0_RO_DM_ADDR0_VAL, CLASS_PE0_RO_DM_ADDR0);
-+ writel(CLASS_PE0_RO_DM_ADDR1_VAL, CLASS_PE0_RO_DM_ADDR1);
-+ writel(CLASS_PE0_QB_DM_ADDR0_VAL, CLASS_PE0_QB_DM_ADDR0);
-+ writel(CLASS_PE0_QB_DM_ADDR1_VAL, CLASS_PE0_QB_DM_ADDR1);
-+ writel(CBUS_VIRT_TO_PFE(TMU_PHY_INQ_PKTPTR), CLASS_TM_INQ_ADDR);
-+
-+ writel(23, CLASS_AFULL_THRES);
-+ writel(23, CLASS_TSQ_FIFO_THRES);
-+
-+ writel(24, CLASS_MAX_BUF_CNT);
-+ writel(24, CLASS_TSQ_MAX_CNT);
-+ //writel(1, CLASS_USE_TMU_INQ);
-+}
-+
-+/**************************** TMU ***************************/
-+
-+void tmu_reset(void)
-+{
-+ writel(SW_RESET, TMU_CTRL);
-+}
-+
-+/** Initializes TMU block.
-+* @param[in] cfg TMU configuration
-+*/
-+void tmu_init(TMU_CFG *cfg)
-+{
-+ int q, phyno;
-+
-+ /* keep in soft reset */
-+ writel(SW_RESET, TMU_CTRL);
-+
-+ /* enable EMAC PHY ports */
-+ writel(0x3, TMU_SYS_GENERIC_CONTROL);
-+
-+ writel(750, TMU_INQ_WATERMARK);
-+ writel(CBUS_VIRT_TO_PFE(EGPI1_BASE_ADDR + GPI_INQ_PKTPTR), TMU_PHY0_INQ_ADDR);
-+ writel(CBUS_VIRT_TO_PFE(EGPI2_BASE_ADDR + GPI_INQ_PKTPTR), TMU_PHY1_INQ_ADDR);
-+#if !defined(CONFIG_LS1012A)
-+ writel(CBUS_VIRT_TO_PFE(EGPI3_BASE_ADDR + GPI_INQ_PKTPTR), TMU_PHY2_INQ_ADDR);
-+#endif
-+ writel(CBUS_VIRT_TO_PFE(HGPI_BASE_ADDR + GPI_INQ_PKTPTR), TMU_PHY3_INQ_ADDR);
-+ writel(CBUS_VIRT_TO_PFE(HIF_NOCPY_RX_INQ0_PKTPTR), TMU_PHY4_INQ_ADDR);
-+ writel(CBUS_VIRT_TO_PFE(UTIL_INQ_PKTPTR), TMU_PHY5_INQ_ADDR);
-+ writel(CBUS_VIRT_TO_PFE(BMU2_BASE_ADDR + BMU_FREE_CTRL), TMU_BMU_INQ_ADDR);
-+
-+ writel(0x3FF, TMU_TDQ0_SCH_CTRL); // enabling all 10 schedulers [9:0] of each TDQ
-+ writel(0x3FF, TMU_TDQ1_SCH_CTRL);
-+#if !defined(CONFIG_LS1012A)
-+ writel(0x3FF, TMU_TDQ2_SCH_CTRL);
-+#endif
-+ writel(0x3FF, TMU_TDQ3_SCH_CTRL);
-+
-+
-+ if (PLL_CLK_EN == 0)
-+ writel(0x0, TMU_PE_SYS_CLK_RATIO); // Clock ratio: for 1:1 the value is 0
-+ else
-+ writel(0x1, TMU_PE_SYS_CLK_RATIO); // Clock ratio: for 1:2 the value is 1
-+
-+ //printf("TMU_LLM_BASE_ADDR %x\n", cfg->llm_base_addr);
-+ writel(cfg->llm_base_addr, TMU_LLM_BASE_ADDR); // Extra packet pointers will be stored from this address onwards
-+
-+ //printf("TMU_LLM_QUE_LEN %x\n", cfg->llm_queue_len);
-+ writel(cfg->llm_queue_len, TMU_LLM_QUE_LEN);
-+ writel(5, TMU_TDQ_IIFG_CFG);
-+ writel(DDR_BUF_SIZE, TMU_BMU_BUF_SIZE);
-+
-+ writel(0x0, TMU_CTRL);
-+
-+ /* MEM init */
-+ //printf("%s: mem init\n", __func__);
-+ writel(MEM_INIT, TMU_CTRL);
-+
-+ while(!(readl(TMU_CTRL) & MEM_INIT_DONE))
-+ ;
-+
-+ /* LLM init */
-+ //printf("%s: lmem init\n", __func__);
-+ writel(LLM_INIT, TMU_CTRL);
-+
-+ while(!(readl(TMU_CTRL) & LLM_INIT_DONE))
-+ ;
-+
-+ // set up each queue for tail drop
-+ for (phyno = 0; phyno < 4; phyno++)
-+ {
-+#if !defined(CONFIG_LS1012A)
-+ if(phyno = 2) continue;
-+#endif
-+ for (q = 0; q < 16; q++)
-+ {
-+ u32 qmax;
-+ writel((phyno << 8) | q, TMU_TEQ_CTRL);
-+ writel(1 << 22, TMU_TEQ_QCFG);
-+ qmax = ((phyno == 3) || (q < 8)) ? 255 : 127;
-+ writel(qmax << 18, TMU_TEQ_HW_PROB_CFG2);
-+ writel(qmax >> 14, TMU_TEQ_HW_PROB_CFG3);
-+ }
-+ }
-+ writel(0x05, TMU_TEQ_DISABLE_DROPCHK);
-+ writel(0, TMU_CTRL);
-+}
-+
-+/** Enables TMU-PE cores.
-+* @param[in] pe_mask TMU PE mask
-+*/
-+void tmu_enable(u32 pe_mask)
-+{
-+ writel(readl(TMU_TX_CTRL) | (pe_mask & 0xF), TMU_TX_CTRL);
-+}
-+
-+/** Disables TMU cores.
-+* @param[in] pe_mask TMU PE mask
-+*/
-+void tmu_disable(u32 pe_mask)
-+{
-+ writel(readl(TMU_TX_CTRL) & ~(pe_mask & 0xF), TMU_TX_CTRL);
-+}
-+
-+/**************************** UTIL ***************************/
-+
-+/** Resets UTIL block.
-+*/
-+void util_reset(void)
-+{
-+ writel(CORE_SW_RESET, UTIL_TX_CTRL);
-+}
-+
-+/** Initializes UTIL block.
-+* @param[in] cfg UTIL configuration
-+*/
-+void util_init(UTIL_CFG *cfg)
-+{
-+
-+ //writel(0x1, UTIL_MISC_REG);
-+
-+ if (PLL_CLK_EN == 0)
-+ writel(0x0, UTIL_PE_SYS_CLK_RATIO); // Clock ratio: for 1:1 the value is 0
-+ else
-+ writel(0x1, UTIL_PE_SYS_CLK_RATIO); // Clock ratio: for 1:2 the value is 1
-+}
-+
-+/** Enables UTIL-PE core.
-+*
-+*/
-+void util_enable(void)
-+{
-+ writel(CORE_ENABLE, UTIL_TX_CTRL);
-+}
-+
-+/** Disables UTIL-PE core.
-+*
-+*/
-+void util_disable(void)
-+{
-+ writel(CORE_DISABLE, UTIL_TX_CTRL);
-+}
-+
-+#if 0
-+/** GEMAC PHY Statistics - This function return address of the first statistics register
-+* @param[in] base GEMAC base address
-+*/
-+unsigned int * gemac_get_stats(void *base)
-+{
-+ return (unsigned int *)(base + EMAC_OCT_TX_BOT);
-+}
-+#endif
-+
-+/**************************** HIF ***************************/
-+
-+/** Initializes HIF no copy block.
-+*
-+*/
-+void hif_nocpy_init(void)
-+{
-+ writel(4, HIF_NOCPY_TX_PORT_NO);
-+ writel(CBUS_VIRT_TO_PFE(BMU1_BASE_ADDR + BMU_ALLOC_CTRL), HIF_NOCPY_LMEM_ALLOC_ADDR);
-+ writel(CBUS_VIRT_TO_PFE(CLASS_INQ_PKTPTR), HIF_NOCPY_CLASS_ADDR);
-+ writel(CBUS_VIRT_TO_PFE(TMU_PHY_INQ_PKTPTR), HIF_NOCPY_TMU_PORT0_ADDR);
-+}
-+
-+/** Initializes HIF copy block.
-+*
-+*/
-+void hif_init(void)
-+{
-+ /*Initialize HIF registers*/
-+ writel(HIF_RX_POLL_CTRL_CYCLE<<16|HIF_TX_POLL_CTRL_CYCLE, HIF_POLL_CTRL);
-+}
-+
-+/** Enable hif tx DMA and interrupt
-+*
-+*/
-+void hif_tx_enable(void)
-+{
-+ /*TODO not sure poll_cntrl_en is required or not */
-+ writel( HIF_CTRL_DMA_EN, HIF_TX_CTRL);
-+ //writel((readl(HIF_INT_ENABLE) | HIF_INT_EN | HIF_TXPKT_INT_EN), HIF_INT_ENABLE);
-+}
-+
-+/** Disable hif tx DMA and interrupt
-+*
-+*/
-+void hif_tx_disable(void)
-+{
-+ u32 hif_int;
-+
-+ writel(0, HIF_TX_CTRL);
-+
-+ hif_int = readl(HIF_INT_ENABLE);
-+ hif_int &= HIF_TXPKT_INT_EN;
-+ writel(hif_int, HIF_INT_ENABLE);
-+}
-+
-+/** Enable hif rx DMA and interrupt
-+*
-+*/
-+void hif_rx_enable(void)
-+{
-+ /*TODO not sure poll_cntrl_en is required or not */
-+ writel((HIF_CTRL_DMA_EN | HIF_CTRL_BDP_CH_START_WSTB), HIF_RX_CTRL);
-+ //writel((readl(HIF_INT_ENABLE) | HIF_INT_EN | HIF_RXPKT_INT_EN), HIF_INT_ENABLE);
-+}
-+
-+/** Disable hif rx DMA and interrupt
-+*
-+*/
-+void hif_rx_disable(void)
-+{
-+ u32 hif_int;
-+
-+ writel(0, HIF_RX_CTRL);
-+
-+ hif_int = readl(HIF_INT_ENABLE);
-+ hif_int &= HIF_RXPKT_INT_EN;
-+ writel(hif_int, HIF_INT_ENABLE);
-+
-+}
-diff --git a/drivers/net/pfe_eth/pfe/cbus.h b/drivers/net/pfe_eth/pfe/cbus.h
-new file mode 100644
-index 0000000..778fe45
---- /dev/null
-+++ b/drivers/net/pfe_eth/pfe/cbus.h
-@@ -0,0 +1,74 @@
-+#ifndef _CBUS_H_
-+#define _CBUS_H_
-+
-+#define EMAC1_BASE_ADDR (CBUS_BASE_ADDR + 0x200000)
-+#define EGPI1_BASE_ADDR (CBUS_BASE_ADDR + 0x210000)
-+#define EMAC2_BASE_ADDR (CBUS_BASE_ADDR + 0x220000)
-+#define EGPI2_BASE_ADDR (CBUS_BASE_ADDR + 0x230000)
-+#define BMU1_BASE_ADDR (CBUS_BASE_ADDR + 0x240000)
-+#define BMU2_BASE_ADDR (CBUS_BASE_ADDR + 0x250000)
-+#define ARB_BASE_ADDR (CBUS_BASE_ADDR + 0x260000) /* FIXME not documented */
-+#define DDR_CONFIG_BASE_ADDR (CBUS_BASE_ADDR + 0x270000) /* FIXME not documented */
-+#define HIF_BASE_ADDR (CBUS_BASE_ADDR + 0x280000)
-+#define HGPI_BASE_ADDR (CBUS_BASE_ADDR + 0x290000)
-+#define LMEM_BASE_ADDR (CBUS_BASE_ADDR + 0x300000)
-+#define LMEM_SIZE 0x10000
-+#define LMEM_END (LMEM_BASE_ADDR + LMEM_SIZE)
-+#define TMU_CSR_BASE_ADDR (CBUS_BASE_ADDR + 0x310000)
-+#define CLASS_CSR_BASE_ADDR (CBUS_BASE_ADDR + 0x320000)
-+#if !defined(CONFIG_LS1012A)
-+#define EMAC3_BASE_ADDR (CBUS_BASE_ADDR + 0x330000)
-+#define EGPI3_BASE_ADDR (CBUS_BASE_ADDR + 0x340000)
-+#endif
-+#define HIF_NOCPY_BASE_ADDR (CBUS_BASE_ADDR + 0x350000)
-+#define UTIL_CSR_BASE_ADDR (CBUS_BASE_ADDR + 0x360000)
-+#define CBUS_GPT_BASE_ADDR (CBUS_BASE_ADDR + 0x370000)
-+
-+#define IS_LMEM(addr, len) (((unsigned long)(addr) >= LMEM_BASE_ADDR) && (((unsigned long)(addr) + (len)) <= LMEM_END))
-+
-+/**
-+* \defgroup XXX_MEM_ACCESS_ADDR PE memory access through CSR
-+* XXX_MEM_ACCESS_ADDR register bit definitions.
-+* @{
-+*/
-+#define PE_MEM_ACCESS_WRITE (1<<31) /**< Internal Memory Write. */
-+#define PE_MEM_ACCESS_READ (0<<31) /**< Internal Memory Read. */
-+#define PE_MEM_ACCESS_IMEM (1<<15)
-+#define PE_MEM_ACCESS_DMEM (1<<16)
-+#define PE_MEM_ACCESS_BYTE_ENABLE(offset,size) (((((1 << (size)) - 1) << (4 - (offset) - (size))) & 0xf) << 24) /**< Byte Enables of the Internal memory access. These are interpred in BE */
-+// @}
-+#include "cbus/emac.h"
-+#include "cbus/gpi.h"
-+#include "cbus/bmu.h"
-+#include "cbus/hif.h"
-+#include "cbus/tmu_csr.h"
-+#include "cbus/class_csr.h"
-+#include "cbus/hif_nocpy.h"
-+#include "cbus/util_csr.h"
-+#include "cbus/gpt.h"
-+
-+
-+/* PFE cores states */
-+#define CORE_DISABLE 0x00000000
-+#define CORE_ENABLE 0x00000001
-+#define CORE_SW_RESET 0x00000002
-+
-+/* LMEM defines */
-+#define LMEM_HDR_SIZE 0x0010
-+#define LMEM_BUF_SIZE_LN2 0x7
-+#define LMEM_BUF_SIZE (1 << LMEM_BUF_SIZE_LN2)
-+
-+/* DDR defines */
-+#define DDR_HDR_SIZE 0x0100
-+#define DDR_BUF_SIZE_LN2 0xb
-+#define DDR_BUF_SIZE (1 << DDR_BUF_SIZE_LN2)
-+
-+
-+/* Clock generation through PLL */
-+#if defined(CONFIG_PLATFORM_PCI)
-+#define PLL_CLK_EN 0
-+#else
-+#define PLL_CLK_EN 1
-+#endif
-+
-+#endif /* _CBUS_H_ */
-diff --git a/drivers/net/pfe_eth/pfe/cbus/bmu.h b/drivers/net/pfe_eth/pfe/cbus/bmu.h
-new file mode 100644
-index 0000000..f3e5e6d
---- /dev/null
-+++ b/drivers/net/pfe_eth/pfe/cbus/bmu.h
-@@ -0,0 +1,37 @@
-+#ifndef _BMU_H_
-+#define _BMU_H_
-+
-+#define BMU_VERSION 0x000
-+#define BMU_CTRL 0x004
-+#define BMU_UCAST_CONFIG 0x008
-+#define BMU_UCAST_BASE_ADDR 0x00c
-+#define BMU_BUF_SIZE 0x010
-+#define BMU_BUF_CNT 0x014
-+#define BMU_THRES 0x018
-+#define BMU_INT_SRC 0x020
-+#define BMU_INT_ENABLE 0x024
-+#define BMU_ALLOC_CTRL 0x030
-+#define BMU_FREE_CTRL 0x034
-+#define BMU_FREE_ERR_ADDR 0x038
-+#define BMU_CURR_BUF_CNT 0x03c
-+#define BMU_MCAST_CNT 0x040
-+#define BMU_MCAST_ALLOC_CTRL 0x044
-+#define BMU_REM_BUF_CNT 0x048
-+#define BMU_LOW_WATERMARK 0x050
-+#define BMU_HIGH_WATERMARK 0x054
-+#define BMU_INT_MEM_ACCESS 0x100
-+
-+typedef struct {
-+ u32 baseaddr;
-+ u32 count;
-+ u32 size;
-+} BMU_CFG;
-+
-+
-+#define BMU1_BUF_SIZE LMEM_BUF_SIZE_LN2
-+#define BMU2_BUF_SIZE DDR_BUF_SIZE_LN2
-+
-+#define BMU2_MCAST_ALLOC_CTRL BMU2_BASE_ADDR + BMU_MCAST_ALLOC_CTRL
-+
-+#endif /* _BMU_H_ */
-+
-diff --git a/drivers/net/pfe_eth/pfe/cbus/class_csr.h b/drivers/net/pfe_eth/pfe/cbus/class_csr.h
-new file mode 100644
-index 0000000..f3151ec
---- /dev/null
-+++ b/drivers/net/pfe_eth/pfe/cbus/class_csr.h
-@@ -0,0 +1,206 @@
-+#ifndef _CLASS_CSR_H_
-+#define _CLASS_CSR_H_
-+
-+/** @file class_csr.h.
-+ * class_csr - block containing all the classifier control and status register. Mapped on CBUS and accessible from all PE's and ARM.
-+ */
-+
-+
-+#define CLASS_VERSION (CLASS_CSR_BASE_ADDR + 0x000)
-+#define CLASS_TX_CTRL (CLASS_CSR_BASE_ADDR + 0x004)
-+#define CLASS_INQ_PKTPTR (CLASS_CSR_BASE_ADDR + 0x010)
-+#define CLASS_HDR_SIZE (CLASS_CSR_BASE_ADDR + 0x014) /**< (ddr_hdr_size[24:16], lmem_hdr_size[5:0]) */
-+#define CLASS_HDR_SIZE_LMEM(off) ((off) & 0x3f) /**< LMEM header size for the Classifier block.\ Data in the LMEM is written from this offset. */
-+#define CLASS_HDR_SIZE_DDR(off) (((off) & 0x1ff) << 16) /**< DDR header size for the Classifier block.\ Data in the DDR is written from this offset. */
-+
-+#define CLASS_PE0_QB_DM_ADDR0 (CLASS_CSR_BASE_ADDR + 0x020) /**< DMEM address of first [15:0] and second [31:16] buffers on QB side. */
-+#define CLASS_PE0_QB_DM_ADDR1 (CLASS_CSR_BASE_ADDR + 0x024) /**< DMEM address of third [15:0] and fourth [31:16] buffers on QB side. */
-+
-+#define CLASS_PE0_RO_DM_ADDR0 (CLASS_CSR_BASE_ADDR + 0x060) /**< DMEM address of first [15:0] and second [31:16] buffers on RO side. */
-+#define CLASS_PE0_RO_DM_ADDR1 (CLASS_CSR_BASE_ADDR + 0x064) /**< DMEM address of third [15:0] and fourth [31:16] buffers on RO side. */
-+
-+/** @name Class PE memory access. Allows external PE's and HOST to read/write PMEM/DMEM memory ranges for each classifier PE.
-+ */
-+//@{
-+#define CLASS_MEM_ACCESS_ADDR (CLASS_CSR_BASE_ADDR + 0x100) /**< {sr_pe_mem_cmd[31], csr_pe_mem_wren[27:24], csr_pe_mem_addr[23:0]}, See \ref XXX_MEM_ACCESS_ADDR for details. */
-+#define CLASS_MEM_ACCESS_WDATA (CLASS_CSR_BASE_ADDR + 0x104) /**< Internal Memory Access Write Data [31:0] */
-+#define CLASS_MEM_ACCESS_RDATA (CLASS_CSR_BASE_ADDR + 0x108) /**< Internal Memory Access Read Data [31:0] */
-+//@}
-+#define CLASS_TM_INQ_ADDR (CLASS_CSR_BASE_ADDR + 0x114)
-+#define CLASS_PE_STATUS (CLASS_CSR_BASE_ADDR + 0x118)
-+
-+#define CLASS_PHY1_RX_PKTS (CLASS_CSR_BASE_ADDR + 0x11c)
-+#define CLASS_PHY1_TX_PKTS (CLASS_CSR_BASE_ADDR + 0x120)
-+#define CLASS_PHY1_LP_FAIL_PKTS (CLASS_CSR_BASE_ADDR + 0x124)
-+#define CLASS_PHY1_INTF_FAIL_PKTS (CLASS_CSR_BASE_ADDR + 0x128)
-+#define CLASS_PHY1_INTF_MATCH_PKTS (CLASS_CSR_BASE_ADDR + 0x12c)
-+#define CLASS_PHY1_L3_FAIL_PKTS (CLASS_CSR_BASE_ADDR + 0x130)
-+#define CLASS_PHY1_V4_PKTS (CLASS_CSR_BASE_ADDR + 0x134)
-+#define CLASS_PHY1_V6_PKTS (CLASS_CSR_BASE_ADDR + 0x138)
-+#define CLASS_PHY1_CHKSUM_ERR_PKTS (CLASS_CSR_BASE_ADDR + 0x13c)
-+#define CLASS_PHY1_TTL_ERR_PKTS (CLASS_CSR_BASE_ADDR + 0x140)
-+#define CLASS_PHY2_RX_PKTS (CLASS_CSR_BASE_ADDR + 0x144)
-+#define CLASS_PHY2_TX_PKTS (CLASS_CSR_BASE_ADDR + 0x148)
-+#define CLASS_PHY2_LP_FAIL_PKTS (CLASS_CSR_BASE_ADDR + 0x14c)
-+#define CLASS_PHY2_INTF_FAIL_PKTS (CLASS_CSR_BASE_ADDR + 0x150)
-+#define CLASS_PHY2_INTF_MATCH_PKTS (CLASS_CSR_BASE_ADDR + 0x154)
-+#define CLASS_PHY2_L3_FAIL_PKTS (CLASS_CSR_BASE_ADDR + 0x158)
-+#define CLASS_PHY2_V4_PKTS (CLASS_CSR_BASE_ADDR + 0x15c)
-+#define CLASS_PHY2_V6_PKTS (CLASS_CSR_BASE_ADDR + 0x160)
-+#define CLASS_PHY2_CHKSUM_ERR_PKTS (CLASS_CSR_BASE_ADDR + 0x164)
-+#define CLASS_PHY2_TTL_ERR_PKTS (CLASS_CSR_BASE_ADDR + 0x168)
-+#define CLASS_PHY3_RX_PKTS (CLASS_CSR_BASE_ADDR + 0x16c)
-+#define CLASS_PHY3_TX_PKTS (CLASS_CSR_BASE_ADDR + 0x170)
-+#define CLASS_PHY3_LP_FAIL_PKTS (CLASS_CSR_BASE_ADDR + 0x174)
-+#define CLASS_PHY3_INTF_FAIL_PKTS (CLASS_CSR_BASE_ADDR + 0x178)
-+#define CLASS_PHY3_INTF_MATCH_PKTS (CLASS_CSR_BASE_ADDR + 0x17c)
-+#define CLASS_PHY3_L3_FAIL_PKTS (CLASS_CSR_BASE_ADDR + 0x180)
-+#define CLASS_PHY3_V4_PKTS (CLASS_CSR_BASE_ADDR + 0x184)
-+#define CLASS_PHY3_V6_PKTS (CLASS_CSR_BASE_ADDR + 0x188)
-+#define CLASS_PHY3_CHKSUM_ERR_PKTS (CLASS_CSR_BASE_ADDR + 0x18c)
-+#define CLASS_PHY3_TTL_ERR_PKTS (CLASS_CSR_BASE_ADDR + 0x190)
-+#define CLASS_PHY1_ICMP_PKTS (CLASS_CSR_BASE_ADDR + 0x194)
-+#define CLASS_PHY1_IGMP_PKTS (CLASS_CSR_BASE_ADDR + 0x198)
-+#define CLASS_PHY1_TCP_PKTS (CLASS_CSR_BASE_ADDR + 0x19c)
-+#define CLASS_PHY1_UDP_PKTS (CLASS_CSR_BASE_ADDR + 0x1a0)
-+#define CLASS_PHY2_ICMP_PKTS (CLASS_CSR_BASE_ADDR + 0x1a4)
-+#define CLASS_PHY2_IGMP_PKTS (CLASS_CSR_BASE_ADDR + 0x1a8)
-+#define CLASS_PHY2_TCP_PKTS (CLASS_CSR_BASE_ADDR + 0x1ac)
-+#define CLASS_PHY2_UDP_PKTS (CLASS_CSR_BASE_ADDR + 0x1b0)
-+#define CLASS_PHY3_ICMP_PKTS (CLASS_CSR_BASE_ADDR + 0x1b4)
-+#define CLASS_PHY3_IGMP_PKTS (CLASS_CSR_BASE_ADDR + 0x1b8)
-+#define CLASS_PHY3_TCP_PKTS (CLASS_CSR_BASE_ADDR + 0x1bc)
-+#define CLASS_PHY3_UDP_PKTS (CLASS_CSR_BASE_ADDR + 0x1c0)
-+#define CLASS_PHY4_ICMP_PKTS (CLASS_CSR_BASE_ADDR + 0x1c4)
-+#define CLASS_PHY4_IGMP_PKTS (CLASS_CSR_BASE_ADDR + 0x1c8)
-+#define CLASS_PHY4_TCP_PKTS (CLASS_CSR_BASE_ADDR + 0x1cc)
-+#define CLASS_PHY4_UDP_PKTS (CLASS_CSR_BASE_ADDR + 0x1d0)
-+#define CLASS_PHY4_RX_PKTS (CLASS_CSR_BASE_ADDR + 0x1d4)
-+#define CLASS_PHY4_TX_PKTS (CLASS_CSR_BASE_ADDR + 0x1d8)
-+#define CLASS_PHY4_LP_FAIL_PKTS (CLASS_CSR_BASE_ADDR + 0x1dc)
-+#define CLASS_PHY4_INTF_FAIL_PKTS (CLASS_CSR_BASE_ADDR + 0x1e0)
-+#define CLASS_PHY4_INTF_MATCH_PKTS (CLASS_CSR_BASE_ADDR + 0x1e4)
-+#define CLASS_PHY4_L3_FAIL_PKTS (CLASS_CSR_BASE_ADDR + 0x1e8)
-+#define CLASS_PHY4_V4_PKTS (CLASS_CSR_BASE_ADDR + 0x1ec)
-+#define CLASS_PHY4_V6_PKTS (CLASS_CSR_BASE_ADDR + 0x1f0)
-+#define CLASS_PHY4_CHKSUM_ERR_PKTS (CLASS_CSR_BASE_ADDR + 0x1f4)
-+#define CLASS_PHY4_TTL_ERR_PKTS (CLASS_CSR_BASE_ADDR + 0x1f8)
-+
-+#define CLASS_PE_SYS_CLK_RATIO (CLASS_CSR_BASE_ADDR + 0x200)
-+#define CLASS_AFULL_THRES (CLASS_CSR_BASE_ADDR + 0x204)
-+#define CLASS_GAP_BETWEEN_READS (CLASS_CSR_BASE_ADDR + 0x208)
-+#define CLASS_MAX_BUF_CNT (CLASS_CSR_BASE_ADDR + 0x20c)
-+#define CLASS_TSQ_FIFO_THRES (CLASS_CSR_BASE_ADDR + 0x210)
-+#define CLASS_TSQ_MAX_CNT (CLASS_CSR_BASE_ADDR + 0x214)
-+#define CLASS_IRAM_DATA_0 (CLASS_CSR_BASE_ADDR + 0x218)
-+#define CLASS_IRAM_DATA_1 (CLASS_CSR_BASE_ADDR + 0x21c)
-+#define CLASS_IRAM_DATA_2 (CLASS_CSR_BASE_ADDR + 0x220)
-+#define CLASS_IRAM_DATA_3 (CLASS_CSR_BASE_ADDR + 0x224)
-+
-+#define CLASS_BUS_ACCESS_ADDR (CLASS_CSR_BASE_ADDR + 0x228)
-+#define CLASS_BUS_ACCESS_ADDR_MASK (0x0001FFFF) //bit 23:0 of PE peripheral address are stored in CLASS_BUS_ACCESS_ADDR
-+
-+#define CLASS_BUS_ACCESS_WDATA (CLASS_CSR_BASE_ADDR + 0x22c)
-+#define CLASS_BUS_ACCESS_RDATA (CLASS_CSR_BASE_ADDR + 0x230)
-+
-+#define CLASS_ROUTE_HASH_ENTRY_SIZE (CLASS_CSR_BASE_ADDR + 0x234) /**< (route_entry_size[9:0], route_hash_size[23:16] (this is actually ln2(size))) */
-+#define CLASS_ROUTE_ENTRY_SIZE(size) ((size) & 0x1ff)
-+#define CLASS_ROUTE_HASH_SIZE(hash_bits) (((hash_bits) & 0xff) << 16)
-+
-+#define CLASS_ROUTE_TABLE_BASE (CLASS_CSR_BASE_ADDR + 0x238)
-+
-+#define CLASS_ROUTE_MULTI (CLASS_CSR_BASE_ADDR + 0x23c)
-+#define CLASS_SMEM_OFFSET (CLASS_CSR_BASE_ADDR + 0x240)
-+#define CLASS_LMEM_BUF_SIZE (CLASS_CSR_BASE_ADDR + 0x244)
-+#define CLASS_VLAN_ID (CLASS_CSR_BASE_ADDR + 0x248)
-+#define CLASS_BMU1_BUF_FREE (CLASS_CSR_BASE_ADDR + 0x24c)
-+#define CLASS_USE_TMU_INQ (CLASS_CSR_BASE_ADDR + 0x250)
-+#define CLASS_VLAN_ID1 (CLASS_CSR_BASE_ADDR + 0x254)
-+
-+#define CLASS_BUS_ACCESS_BASE (CLASS_CSR_BASE_ADDR + 0x258)
-+#define CLASS_BUS_ACCESS_BASE_MASK (0xFF000000) //bit 31:24 of PE peripheral address are stored in CLASS_BUS_ACCESS_BASE
-+
-+#define CLASS_HIF_PARSE (CLASS_CSR_BASE_ADDR + 0x25c)
-+
-+#define CLASS_HOST_PE0_GP (CLASS_CSR_BASE_ADDR + 0x260)
-+#define CLASS_PE0_GP (CLASS_CSR_BASE_ADDR + 0x264)
-+#define CLASS_HOST_PE1_GP (CLASS_CSR_BASE_ADDR + 0x268)
-+#define CLASS_PE1_GP (CLASS_CSR_BASE_ADDR + 0x26c)
-+#define CLASS_HOST_PE2_GP (CLASS_CSR_BASE_ADDR + 0x270)
-+#define CLASS_PE2_GP (CLASS_CSR_BASE_ADDR + 0x274)
-+#define CLASS_HOST_PE3_GP (CLASS_CSR_BASE_ADDR + 0x278)
-+#define CLASS_PE3_GP (CLASS_CSR_BASE_ADDR + 0x27c)
-+#define CLASS_HOST_PE4_GP (CLASS_CSR_BASE_ADDR + 0x280)
-+#define CLASS_PE4_GP (CLASS_CSR_BASE_ADDR + 0x284)
-+#define CLASS_HOST_PE5_GP (CLASS_CSR_BASE_ADDR + 0x288)
-+#define CLASS_PE5_GP (CLASS_CSR_BASE_ADDR + 0x28c)
-+
-+#define CLASS_PE_INT_SRC (CLASS_CSR_BASE_ADDR + 0x290)
-+#define CLASS_PE_INT_ENABLE (CLASS_CSR_BASE_ADDR + 0x294)
-+
-+#define CLASS_TPID0_TPID1 (CLASS_CSR_BASE_ADDR + 0x298)
-+#define CLASS_TPID2 (CLASS_CSR_BASE_ADDR + 0x29c)
-+
-+#define CLASS_L4_CHKSUM_ADDR (CLASS_CSR_BASE_ADDR + 0x2a0)
-+
-+#define CLASS_PE0_DEBUG (CLASS_CSR_BASE_ADDR + 0x2a4)
-+#define CLASS_PE1_DEBUG (CLASS_CSR_BASE_ADDR + 0x2a8)
-+#define CLASS_PE2_DEBUG (CLASS_CSR_BASE_ADDR + 0x2ac)
-+#define CLASS_PE3_DEBUG (CLASS_CSR_BASE_ADDR + 0x2b0)
-+#define CLASS_PE4_DEBUG (CLASS_CSR_BASE_ADDR + 0x2b4)
-+#define CLASS_PE5_DEBUG (CLASS_CSR_BASE_ADDR + 0x2b8)
-+
-+#define CLASS_STATE (CLASS_CSR_BASE_ADDR + 0x2bc)
-+
-+/* CLASS defines */
-+#define CLASS_PBUF_SIZE 0x100 /* Fixed by hardware */
-+#define CLASS_PBUF_HEADER_OFFSET 0x80 /* Can be configured */
-+
-+#define CLASS_PBUF0_BASE_ADDR 0x000 /* Can be configured */
-+#define CLASS_PBUF1_BASE_ADDR (CLASS_PBUF0_BASE_ADDR + CLASS_PBUF_SIZE) /* Can be configured */
-+#define CLASS_PBUF2_BASE_ADDR (CLASS_PBUF1_BASE_ADDR + CLASS_PBUF_SIZE) /* Can be configured */
-+#define CLASS_PBUF3_BASE_ADDR (CLASS_PBUF2_BASE_ADDR + CLASS_PBUF_SIZE) /* Can be configured */
-+
-+#define CLASS_PBUF0_HEADER_BASE_ADDR (CLASS_PBUF0_BASE_ADDR + CLASS_PBUF_HEADER_OFFSET)
-+#define CLASS_PBUF1_HEADER_BASE_ADDR (CLASS_PBUF1_BASE_ADDR + CLASS_PBUF_HEADER_OFFSET)
-+#define CLASS_PBUF2_HEADER_BASE_ADDR (CLASS_PBUF2_BASE_ADDR + CLASS_PBUF_HEADER_OFFSET)
-+#define CLASS_PBUF3_HEADER_BASE_ADDR (CLASS_PBUF3_BASE_ADDR + CLASS_PBUF_HEADER_OFFSET)
-+
-+#define CLASS_PE0_RO_DM_ADDR0_VAL ((CLASS_PBUF1_BASE_ADDR << 16) | CLASS_PBUF0_BASE_ADDR)
-+#define CLASS_PE0_RO_DM_ADDR1_VAL ((CLASS_PBUF3_BASE_ADDR << 16) | CLASS_PBUF2_BASE_ADDR)
-+
-+#define CLASS_PE0_QB_DM_ADDR0_VAL ((CLASS_PBUF1_HEADER_BASE_ADDR << 16) | CLASS_PBUF0_HEADER_BASE_ADDR)
-+#define CLASS_PE0_QB_DM_ADDR1_VAL ((CLASS_PBUF3_HEADER_BASE_ADDR << 16) | CLASS_PBUF2_HEADER_BASE_ADDR)
-+
-+#define CLASS_ROUTE_SIZE 128
-+#define CLASS_ROUTE_HASH_BITS 20
-+#define CLASS_ROUTE_HASH_MASK ((1 << CLASS_ROUTE_HASH_BITS) - 1)
-+
-+#define CLASS_ROUTE0_BASE_ADDR 0x400 /* Can be configured */
-+#define CLASS_ROUTE1_BASE_ADDR (CLASS_ROUTE0_BASE_ADDR + CLASS_ROUTE_SIZE) /* Can be configured */
-+#define CLASS_ROUTE2_BASE_ADDR (CLASS_ROUTE1_BASE_ADDR + CLASS_ROUTE_SIZE) /* Can be configured */
-+#define CLASS_ROUTE3_BASE_ADDR (CLASS_ROUTE2_BASE_ADDR + CLASS_ROUTE_SIZE) /* Can be configured */
-+
-+#define TWO_LEVEL_ROUTE (1 << 0)
-+#define PHYNO_IN_HASH (1 << 1)
-+#define HW_ROUTE_FETCH (1 << 3)
-+#define HW_BRIDGE_FETCH (1 << 5)
-+#define IP_ALIGNED (1 << 6)
-+#define ARC_HIT_CHECK_EN (1 << 7)
-+#define CLASS_TOE (1 << 11)
-+#define HASH_NORMAL (0 << 12)
-+#define HASH_CRC_PORT (1 << 12)
-+#define HASH_CRC_IP (2 << 12)
-+#define HASH_CRC_PORT_IP (3 << 12)
-+#define QB2BUS_LE (1 << 15)
-+
-+#define TCP_CHKSUM_DROP (1 << 0)
-+#define UDP_CHKSUM_DROP (1 << 1)
-+#define IPV4_CHKSUM_DROP (1 << 9)
-+
-+typedef struct {
-+ u32 route_table_baseaddr;
-+ u32 route_table_hash_bits;
-+} CLASS_CFG;
-+
-+#endif /* _CLASS_CSR_H_ */
-diff --git a/drivers/net/pfe_eth/pfe/cbus/emac.h b/drivers/net/pfe_eth/pfe/cbus/emac.h
-new file mode 100644
-index 0000000..1f308ce
---- /dev/null
-+++ b/drivers/net/pfe_eth/pfe/cbus/emac.h
-@@ -0,0 +1,232 @@
-+#ifndef _EMAC_H_
-+#define _EMAC_H_
-+
-+#define EMAC_IEVENT_REG 0x004
-+#define EMAC_IMASK_REG 0x008
-+#define EMAC_R_DES_ACTIVE_REG 0x010
-+#define EMAC_X_DES_ACTIVE_REG 0x014
-+#define EMAC_ECNTRL_REG 0x024
-+#define EMAC_MII_DATA_REG 0x040
-+#define EMAC_MII_CTRL_REG 0x044
-+#define EMAC_MIB_CTRL_STS_REG 0x064
-+#define EMAC_RCNTRL_REG 0x084
-+#define EMAC_TCNTRL_REG 0x0C4
-+#define EMAC_PHY_ADDR_LOW 0x0E4
-+#define EMAC_PHY_ADDR_HIGH 0x0E8
-+#define EMAC_TFWR_STR_FWD 0x144
-+#define EMAC_RX_SECTIOM_FULL 0x190
-+#define EMAC_TX_SECTION_EMPTY 0x1A0
-+#define EMAC_TRUNC_FL 0x1B0
-+
-+#define RMON_T_DROP 0x200 /* Count of frames not cntd correctly */
-+#define RMON_T_PACKETS 0x204 /* RMON TX packet count */
-+#define RMON_T_BC_PKT 0x208 /* RMON TX broadcast pkts */
-+#define RMON_T_MC_PKT 0x20c /* RMON TX multicast pkts */
-+#define RMON_T_CRC_ALIGN 0x210 /* RMON TX pkts with CRC align err */
-+#define RMON_T_UNDERSIZE 0x214 /* RMON TX pkts < 64 bytes, good CRC */
-+#define RMON_T_OVERSIZE 0x218 /* RMON TX pkts > MAX_FL bytes good CRC */
-+#define RMON_T_FRAG 0x21c /* RMON TX pkts < 64 bytes, bad CRC */
-+#define RMON_T_JAB 0x220 /* RMON TX pkts > MAX_FL bytes, bad CRC */
-+#define RMON_T_COL 0x224 /* RMON TX collision count */
-+#define RMON_T_P64 0x228 /* RMON TX 64 byte pkts */
-+#define RMON_T_P65TO127 0x22c /* RMON TX 65 to 127 byte pkts */
-+#define RMON_T_P128TO255 0x230 /* RMON TX 128 to 255 byte pkts */
-+#define RMON_T_P256TO511 0x234 /* RMON TX 256 to 511 byte pkts */
-+#define RMON_T_P512TO1023 0x238 /* RMON TX 512 to 1023 byte pkts */
-+#define RMON_T_P1024TO2047 0x23c /* RMON TX 1024 to 2047 byte pkts */
-+#define RMON_T_P_GTE2048 0x240 /* RMON TX pkts > 2048 bytes */
-+#define RMON_T_OCTETS 0x244 /* RMON TX octets */
-+#define IEEE_T_DROP 0x248 /* Count of frames not counted crtly */
-+#define IEEE_T_FRAME_OK 0x24c /* Frames tx'd OK */
-+#define IEEE_T_1COL 0x250 /* Frames tx'd with single collision */
-+#define IEEE_T_MCOL 0x254 /* Frames tx'd with multiple collision */
-+#define IEEE_T_DEF 0x258 /* Frames tx'd after deferral delay */
-+#define IEEE_T_LCOL 0x25c /* Frames tx'd with late collision */
-+#define IEEE_T_EXCOL 0x260 /* Frames tx'd with excesv collisions */
-+#define IEEE_T_MACERR 0x264 /* Frames tx'd with TX FIFO underrun */
-+#define IEEE_T_CSERR 0x268 /* Frames tx'd with carrier sense err */
-+#define IEEE_T_SQE 0x26c /* Frames tx'd with SQE err */
-+#define IEEE_T_FDXFC 0x270 /* Flow control pause frames tx'd */
-+#define IEEE_T_OCTETS_OK 0x274 /* Octet count for frames tx'd w/o err */
-+#define RMON_R_PACKETS 0x284 /* RMON RX packet count */
-+#define RMON_R_BC_PKT 0x288 /* RMON RX broadcast pkts */
-+#define RMON_R_MC_PKT 0x28c /* RMON RX multicast pkts */
-+#define RMON_R_CRC_ALIGN 0x290 /* RMON RX pkts with CRC alignment err */
-+#define RMON_R_UNDERSIZE 0x294 /* RMON RX pkts < 64 bytes, good CRC */
-+#define RMON_R_OVERSIZE 0x298 /* RMON RX pkts > MAX_FL bytes good CRC */
-+#define RMON_R_FRAG 0x29c /* RMON RX pkts < 64 bytes, bad CRC */
-+#define RMON_R_JAB 0x2a0 /* RMON RX pkts > MAX_FL bytes, bad CRC */
-+#define RMON_R_RESVD_O 0x2a4 /* Reserved */
-+#define RMON_R_P64 0x2a8 /* RMON RX 64 byte pkts */
-+#define RMON_R_P65TO127 0x2ac /* RMON RX 65 to 127 byte pkts */
-+#define RMON_R_P128TO255 0x2b0 /* RMON RX 128 to 255 byte pkts */
-+#define RMON_R_P256TO511 0x2b4 /* RMON RX 256 to 511 byte pkts */
-+#define RMON_R_P512TO1023 0x2b8 /* RMON RX 512 to 1023 byte pkts */
-+#define RMON_R_P1024TO2047 0x2bc /* RMON RX 1024 to 2047 byte pkts */
-+#define RMON_R_P_GTE2048 0x2c0 /* RMON RX pkts > 2048 bytes */
-+#define RMON_R_OCTETS 0x2c4 /* RMON RX octets */
-+#define IEEE_R_DROP 0x2c8 /* Count frames not counted correctly */
-+#define IEEE_R_FRAME_OK 0x2cc /* Frames rx'd OK */
-+#define IEEE_R_CRC 0x2d0 /* Frames rx'd with CRC err */
-+#define IEEE_R_ALIGN 0x2d4 /* Frames rx'd with alignment err */
-+#define IEEE_R_MACERR 0x2d8 /* Receive FIFO overflow count */
-+#define IEEE_R_FDXFC 0x2dc /* Flow control pause frames rx'd */
-+#define IEEE_R_OCTETS_OK 0x2e0 /* Octet cnt for frames rx'd w/o err */
-+
-+
-+/* GEMAC definitions and settings */
-+
-+#define EMAC_PORT_0 0
-+#define EMAC_PORT_1 1
-+
-+/* GEMAC Bit definitions */
-+#define EMAC_IEVENT_HBERR 0x80000000
-+#define EMAC_IEVENT_BABR 0x40000000
-+#define EMAC_IEVENT_BABT 0x20000000
-+#define EMAC_IEVENT_GRA 0x10000000
-+#define EMAC_IEVENT_TXF 0x08000000
-+#define EMAC_IEVENT_TXB 0x04000000
-+#define EMAC_IEVENT_RXF 0x02000000
-+#define EMAC_IEVENT_RXB 0x01000000
-+#define EMAC_IEVENT_MII 0x00800000
-+#define EMAC_IEVENT_EBERR 0x00400000
-+#define EMAC_IEVENT_LC 0x00200000
-+#define EMAC_IEVENT_RL 0x00100000
-+#define EMAC_IEVENT_UN 0x00080000
-+
-+#define EMAC_IMASK_HBERR 0x80000000
-+#define EMAC_IMASK_BABR 0x40000000
-+#define EMAC_IMASKT_BABT 0x20000000
-+#define EMAC_IMASK_GRA 0x10000000
-+#define EMAC_IMASKT_TXF 0x08000000
-+#define EMAC_IMASK_TXB 0x04000000
-+#define EMAC_IMASKT_RXF 0x02000000
-+#define EMAC_IMASK_RXB 0x01000000
-+#define EMAC_IMASK_MII 0x00800000
-+#define EMAC_IMASK_EBERR 0x00400000
-+#define EMAC_IMASK_LC 0x00200000
-+#define EMAC_IMASKT_RL 0x00100000
-+#define EMAC_IMASK_UN 0x00080000
-+
-+#define EMAC_RCNTRL_MAX_FL_SHIFT 16
-+#define EMAC_RCNTRL_LOOP 0x00000001
-+#define EMAC_RCNTRL_DRT 0x00000002
-+#define EMAC_RCNTRL_MII_MODE 0x00000004
-+#define EMAC_RCNTRL_PROM 0x00000008
-+#define EMAC_RCNTRL_BC_REJ 0x00000010
-+#define EMAC_RCNTRL_FCE 0x00000020
-+#define EMAC_RCNTRL_RGMII 0x00000040
-+#define EMAC_RCNTRL_SGMII 0x00000080
-+#define EMAC_RCNTRL_RMII 0x00000100
-+#define EMAC_RCNTRL_RMII_10T 0x00000200
-+#define EMAC_RCNTRL_CRC_FWD 0x00004000
-+
-+#define EMAC_TCNTRL_GTS 0x00000001
-+#define EMAC_TCNTRL_HBC 0x00000002
-+#define EMAC_TCNTRL_FDEN 0x00000004
-+#define EMAC_TCNTRL_TFC_PAUSE 0x00000008
-+#define EMAC_TCNTRL_RFC_PAUSE 0x00000010
-+
-+#define EMAC_ECNTRL_RESET 0x00000001 /* reset the EMAC */
-+#define EMAC_ECNTRL_ETHER_EN 0x00000002 /* enable the EMAC */
-+#define EMAC_ECNTRL_SPEED 0x00000020
-+#define EMAC_ECNTRL_DBSWAP 0x00000100
-+
-+#define EMAC_X_WMRK_STRFWD 0x00000100
-+
-+#define EMAC_X_DES_ACTIVE_TDAR 0x01000000
-+#define EMAC_R_DES_ACTIVE_RDAR 0x01000000
-+
-+
-+
-+/* The possible operating speeds of the MAC, currently supporting 10, 100 and
-+ * 1000Mb modes.
-+ */
-+typedef enum {SPEED_10M, SPEED_100M, SPEED_1000M, SPEED_1000M_PCS} MAC_SPEED;
-+
-+#define GMII 1
-+#define MII 2
-+#define RMII 3
-+#define RGMII 4
-+#define SGMII 5
-+
-+#define DUPLEX_HALF 0x00
-+#define DUPLEX_FULL 0x01
-+
-+
-+/* Default configuration */
-+#define EMAC0_DEFAULT_DUPLEX_MODE FULLDUPLEX
-+#define EMAC0_DEFAULT_EMAC_MODE RGMII
-+#define EMAC0_DEFAULT_EMAC_SPEED SPEED_1000M
-+
-+#define EMAC1_DEFAULT_DUPLEX_MODE FULLDUPLEX
-+#define EMAC1_DEFAULT_EMAC_MODE SGMII
-+#define EMAC1_DEFAULT_EMAC_SPEED SPEED_1000M
-+
-+/* MII-related definitios */
-+#define EMAC_MII_DATA_ST 0x40000000 /* Start of frame delimiter */
-+#define EMAC_MII_DATA_OP_RD 0x20000000 /* Perform a read operation */
-+#define EMAC_MII_DATA_OP_WR 0x10000000 /* Perform a write operation */
-+#define EMAC_MII_DATA_PA_MSK 0x0f800000 /* PHY Address field mask */
-+#define EMAC_MII_DATA_RA_MSK 0x007c0000 /* PHY Register field mask */
-+#define EMAC_MII_DATA_TA 0x00020000 /* Turnaround */
-+#define EMAC_MII_DATA_DATAMSK 0x0000ffff /* PHY data field */
-+
-+#define EMAC_MII_DATA_RA_SHIFT 18 /* MII Register address bits */
-+#define EMAC_MII_DATA_RA_MASK 0x1F /* MII Register address mask */
-+#define EMAC_MII_DATA_PA_SHIFT 23 /* MII PHY address bits */
-+#define EMAC_MII_DATA_PA_MASK 0x1F /* MII PHY address mask */
-+
-+#define EMAC_MII_DATA_RA(v) ((v & EMAC_MII_DATA_RA_MASK) << EMAC_MII_DATA_RA_SHIFT)
-+#define EMAC_MII_DATA_PA(v) ((v & EMAC_MII_DATA_RA_MASK) << EMAC_MII_DATA_PA_SHIFT)
-+#define EMAC_MII_DATA(v) (v & 0xffff)
-+
-+#define EMAC_MII_SPEED_SHIFT 1
-+#define EMAC_HOLDTIME_SHIFT 8
-+#define EMAC_HOLDTIME_MASK 0x7
-+#define EMAC_HOLDTIME(v) ((v & EMAC_HOLDTIME_MASK) << EMAC_HOLDTIME_SHIFT)
-+
-+/* The Address organisation for the MAC device. All addresses are split into
-+ * two 32-bit register fields. The first one (bottom) is the lower 32-bits of
-+ * the address and the other field are the high order bits - this may be 16-bits
-+ * in the case of MAC addresses, or 32-bits for the hash address.
-+ * In terms of memory storage, the first item (bottom) is assumed to be at a
-+ * lower address location than 'top'. i.e. top should be at address location of
-+ * 'bottom' + 4 bytes.
-+ */
-+typedef struct {
-+ u32 bottom; /* Lower 32-bits of address. */
-+ u32 top; /* Upper 32-bits of address. */
-+} MAC_ADDR;
-+
-+
-+/* The following is the organisation of the address filters section of the MAC
-+ * registers. The Cadence MAC contains four possible specific address match
-+ * addresses, if an incoming frame corresponds to any one of these four
-+ * addresses then the frame will be copied to memory.
-+ * It is not necessary for all four of the address match registers to be
-+ * programmed, this is application dependant.
-+ */
-+typedef struct {
-+ MAC_ADDR one; /* Specific address register 1. */
-+ MAC_ADDR two; /* Specific address register 2. */
-+ MAC_ADDR three; /* Specific address register 3. */
-+ MAC_ADDR four; /* Specific address register 4. */
-+} SPEC_ADDR;
-+
-+typedef struct {
-+ u32 mode;
-+ u32 speed;
-+ u32 duplex;
-+} GEMAC_CFG;
-+
-+/* Internal PHY Registers - SGMII */
-+#define PHY_SGMII_CR_PHY_RESET 0x8000
-+#define PHY_SGMII_CR_RESET_AN 0x0200
-+#define PHY_SGMII_CR_DEF_VAL 0x1140
-+#define PHY_SGMII_DEV_ABILITY_SGMII 0x4001
-+#define PHY_SGMII_IF_MODE_AN 0x0002
-+#define PHY_SGMII_IF_MODE_SGMII 0x0001
-+
-+
-+#endif /* _EMAC_H_ */
-diff --git a/drivers/net/pfe_eth/pfe/cbus/gpi.h b/drivers/net/pfe_eth/pfe/cbus/gpi.h
-new file mode 100644
-index 0000000..d2d165f
---- /dev/null
-+++ b/drivers/net/pfe_eth/pfe/cbus/gpi.h
-@@ -0,0 +1,60 @@
-+#ifndef _GPI_H_
-+#define _GPI_H_
-+
-+#define GPI_VERSION 0x00
-+#define GPI_CTRL 0x04
-+#define GPI_RX_CONFIG 0x08
-+#define GPI_HDR_SIZE 0x0c
-+#define GPI_BUF_SIZE 0x10
-+#define GPI_LMEM_ALLOC_ADDR 0x14
-+#define GPI_LMEM_FREE_ADDR 0x18
-+#define GPI_DDR_ALLOC_ADDR 0x1c
-+#define GPI_DDR_FREE_ADDR 0x20
-+#define GPI_CLASS_ADDR 0x24
-+#define GPI_DRX_FIFO 0x28
-+#define GPI_TRX_FIFO 0x2c
-+#define GPI_INQ_PKTPTR 0x30
-+#define GPI_DDR_DATA_OFFSET 0x34
-+#define GPI_LMEM_DATA_OFFSET 0x38
-+#define GPI_TMLF_TX 0x4c
-+#define GPI_DTX_ASEQ 0x50
-+#define GPI_FIFO_STATUS 0x54
-+#define GPI_FIFO_DEBUG 0x58
-+#define GPI_TX_PAUSE_TIME 0x5c
-+#define GPI_LMEM_SEC_BUF_DATA_OFFSET 0x60
-+#define GPI_DDR_SEC_BUF_DATA_OFFSET 0x64
-+#define GPI_TOE_CHKSUM_EN 0x68
-+#define GPI_OVERRUN_DROPCNT 0x6c
-+
-+typedef struct {
-+ u32 lmem_rtry_cnt;
-+ u32 tmlf_txthres;
-+ u32 aseq_len;
-+} GPI_CFG;
-+
-+
-+/* GPI commons defines */
-+#define GPI_LMEM_BUF_EN 0x1
-+#define GPI_DDR_BUF_EN 0x1
-+
-+/* EGPI 1 defines */
-+#define EGPI1_LMEM_RTRY_CNT 0x40
-+#define EGPI1_TMLF_TXTHRES 0xBC
-+#define EGPI1_ASEQ_LEN 0x50
-+
-+/* EGPI 2 defines */
-+#define EGPI2_LMEM_RTRY_CNT 0x40
-+#define EGPI2_TMLF_TXTHRES 0xBC
-+#define EGPI2_ASEQ_LEN 0x40
-+
-+/* EGPI 3 defines */
-+#define EGPI3_LMEM_RTRY_CNT 0x40
-+#define EGPI3_TMLF_TXTHRES 0xBC
-+#define EGPI3_ASEQ_LEN 0x40
-+
-+/* HGPI defines */
-+#define HGPI_LMEM_RTRY_CNT 0x40
-+#define HGPI_TMLF_TXTHRES 0xBC
-+#define HGPI_ASEQ_LEN 0x40
-+
-+#endif /* _GPI_H_ */
-diff --git a/drivers/net/pfe_eth/pfe/cbus/gpt.h b/drivers/net/pfe_eth/pfe/cbus/gpt.h
-new file mode 100644
-index 0000000..f8c114b
---- /dev/null
-+++ b/drivers/net/pfe_eth/pfe/cbus/gpt.h
-@@ -0,0 +1,11 @@
-+#ifndef _CBUS_GPT_H_
-+#define _CBUS_GPT_H_
-+
-+#define CBUS_GPT_VERSION (CBUS_GPT_BASE_ADDR + 0x00)
-+#define CBUS_GPT_STATUS (CBUS_GPT_BASE_ADDR + 0x04)
-+#define CBUS_GPT_CONFIG (CBUS_GPT_BASE_ADDR + 0x08)
-+#define CBUS_GPT_COUNTER (CBUS_GPT_BASE_ADDR + 0x0c)
-+#define CBUS_GPT_PERIOD (CBUS_GPT_BASE_ADDR + 0x10)
-+#define CBUS_GPT_WIDTH (CBUS_GPT_BASE_ADDR + 0x14)
-+
-+#endif /* _CBUS_GPT_H_ */
-diff --git a/drivers/net/pfe_eth/pfe/cbus/hif.h b/drivers/net/pfe_eth/pfe/cbus/hif.h
-new file mode 100644
-index 0000000..a4dd7c2
---- /dev/null
-+++ b/drivers/net/pfe_eth/pfe/cbus/hif.h
-@@ -0,0 +1,62 @@
-+#ifndef _HIF_H_
-+#define _HIF_H_
-+
-+/** @file hif.h.
-+ * hif - PFE hif block control and status register. Mapped on CBUS and accessible from all PE's and ARM.
-+ */
-+#define HIF_VERSION (HIF_BASE_ADDR + 0x00)
-+#define HIF_TX_CTRL (HIF_BASE_ADDR + 0x04)
-+#define HIF_TX_CURR_BD_ADDR (HIF_BASE_ADDR + 0x08)
-+#define HIF_TX_ALLOC (HIF_BASE_ADDR + 0x0c)
-+#define HIF_TX_BDP_ADDR (HIF_BASE_ADDR + 0x10)
-+#define HIF_TX_STATUS (HIF_BASE_ADDR + 0x14)
-+#define HIF_RX_CTRL (HIF_BASE_ADDR + 0x20)
-+#define HIF_RX_BDP_ADDR (HIF_BASE_ADDR + 0x24)
-+#define HIF_RX_STATUS (HIF_BASE_ADDR + 0x30)
-+#define HIF_INT_SRC (HIF_BASE_ADDR + 0x34)
-+#define HIF_INT_ENABLE (HIF_BASE_ADDR + 0x38)
-+#define HIF_POLL_CTRL (HIF_BASE_ADDR + 0x3c)
-+#define HIF_RX_CURR_BD_ADDR (HIF_BASE_ADDR + 0x40)
-+#define HIF_RX_ALLOC (HIF_BASE_ADDR + 0x44)
-+#define HIF_TX_DMA_STATUS (HIF_BASE_ADDR + 0x48)
-+#define HIF_RX_DMA_STATUS (HIF_BASE_ADDR + 0x4c)
-+#define HIF_INT_COAL (HIF_BASE_ADDR + 0x50)
-+
-+/*HIF_INT_SRC/ HIF_INT_ENABLE control bits */
-+#define HIF_INT (1 << 0)
-+#define HIF_RXBD_INT (1 << 1)
-+#define HIF_RXPKT_INT (1 << 2)
-+#define HIF_TXBD_INT (1 << 3)
-+#define HIF_TXPKT_INT (1 << 4)
-+
-+/*HIF_TX_CTRL bits */
-+#define HIF_CTRL_DMA_EN (1<<0)
-+#define HIF_CTRL_BDP_POLL_CTRL_EN (1<<1)
-+#define HIF_CTRL_BDP_CH_START_WSTB (1<<2)
-+
-+/*HIF_INT_ENABLE bits */
-+#define HIF_INT_EN (1 << 0)
-+#define HIF_RXBD_INT_EN (1 << 1)
-+#define HIF_RXPKT_INT_EN (1 << 2)
-+#define HIF_TXBD_INT_EN (1 << 3)
-+#define HIF_TXPKT_INT_EN (1 << 4)
-+
-+/*HIF_POLL_CTRL bits*/
-+#define HIF_RX_POLL_CTRL_CYCLE 0x0400
-+#define HIF_TX_POLL_CTRL_CYCLE 0x0400
-+
-+/*Buffer descriptor control bits */
-+#define BD_CTRL_BUFLEN_MASK (0xffff)
-+#define BD_BUF_LEN(x) (x & BD_CTRL_BUFLEN_MASK)
-+#define BD_CTRL_CBD_INT_EN (1 << 16)
-+#define BD_CTRL_PKT_INT_EN (1 << 17)
-+#define BD_CTRL_LIFM (1 << 18)
-+#define BD_CTRL_LAST_BD (1 << 19)
-+#define BD_CTRL_DIR (1 << 20)
-+#define BD_CTRL_PKT_XFER (1 << 24)
-+#define BD_CTRL_DESC_EN (1 << 31)
-+#define BD_CTRL_PARSE_DISABLE (1 << 25)
-+#define BD_CTRL_BRFETCH_DISABLE (1 << 26)
-+#define BD_CTRL_RTFETCH_DISABLE (1 << 27)
-+
-+#endif /* _HIF_H_ */
-diff --git a/drivers/net/pfe_eth/pfe/cbus/hif_nocpy.h b/drivers/net/pfe_eth/pfe/cbus/hif_nocpy.h
-new file mode 100644
-index 0000000..93cb946
---- /dev/null
-+++ b/drivers/net/pfe_eth/pfe/cbus/hif_nocpy.h
-@@ -0,0 +1,33 @@
-+#ifndef _HIF_NOCPY_H_
-+#define _HIF_NOCPY_H_
-+
-+#define HIF_NOCPY_VERSION (HIF_NOCPY_BASE_ADDR + 0x00)
-+#define HIF_NOCPY_TX_CTRL (HIF_NOCPY_BASE_ADDR + 0x04)
-+#define HIF_NOCPY_TX_CURR_BD_ADDR (HIF_NOCPY_BASE_ADDR + 0x08)
-+#define HIF_NOCPY_TX_ALLOC (HIF_NOCPY_BASE_ADDR + 0x0c)
-+#define HIF_NOCPY_TX_BDP_ADDR (HIF_NOCPY_BASE_ADDR + 0x10)
-+#define HIF_NOCPY_TX_STATUS (HIF_NOCPY_BASE_ADDR + 0x14)
-+#define HIF_NOCPY_RX_CTRL (HIF_NOCPY_BASE_ADDR + 0x20)
-+#define HIF_NOCPY_RX_BDP_ADDR (HIF_NOCPY_BASE_ADDR + 0x24)
-+#define HIF_NOCPY_RX_STATUS (HIF_NOCPY_BASE_ADDR + 0x30)
-+#define HIF_NOCPY_INT_SRC (HIF_NOCPY_BASE_ADDR + 0x34)
-+#define HIF_NOCPY_INT_ENABLE (HIF_NOCPY_BASE_ADDR + 0x38)
-+#define HIF_NOCPY_POLL_CTRL (HIF_NOCPY_BASE_ADDR + 0x3c)
-+#define HIF_NOCPY_RX_CURR_BD_ADDR (HIF_NOCPY_BASE_ADDR + 0x40)
-+#define HIF_NOCPY_RX_ALLOC (HIF_NOCPY_BASE_ADDR + 0x44)
-+#define HIF_NOCPY_TX_DMA_STATUS (HIF_NOCPY_BASE_ADDR + 0x48)
-+#define HIF_NOCPY_RX_DMA_STATUS (HIF_NOCPY_BASE_ADDR + 0x4c)
-+#define HIF_NOCPY_RX_INQ0_PKTPTR (HIF_NOCPY_BASE_ADDR + 0x50)
-+#define HIF_NOCPY_RX_INQ1_PKTPTR (HIF_NOCPY_BASE_ADDR + 0x54)
-+#define HIF_NOCPY_TX_PORT_NO (HIF_NOCPY_BASE_ADDR + 0x60)
-+#define HIF_NOCPY_LMEM_ALLOC_ADDR (HIF_NOCPY_BASE_ADDR + 0x64)
-+#define HIF_NOCPY_CLASS_ADDR (HIF_NOCPY_BASE_ADDR + 0x68)
-+#define HIF_NOCPY_TMU_PORT0_ADDR (HIF_NOCPY_BASE_ADDR + 0x70)
-+#define HIF_NOCPY_TMU_PORT1_ADDR (HIF_NOCPY_BASE_ADDR + 0x74)
-+#define HIF_NOCPY_TMU_PORT2_ADDR (HIF_NOCPY_BASE_ADDR + 0x7c)
-+#define HIF_NOCPY_TMU_PORT3_ADDR (HIF_NOCPY_BASE_ADDR + 0x80)
-+#define HIF_NOCPY_TMU_PORT4_ADDR (HIF_NOCPY_BASE_ADDR + 0x84)
-+#define HIF_NOCPY_INT_COAL (HIF_NOCPY_BASE_ADDR + 0x90)
-+
-+
-+#endif /* _HIF_NOCPY_H_ */
-diff --git a/drivers/net/pfe_eth/pfe/cbus/tmu_csr.h b/drivers/net/pfe_eth/pfe/cbus/tmu_csr.h
-new file mode 100644
-index 0000000..cbcbb1f
---- /dev/null
-+++ b/drivers/net/pfe_eth/pfe/cbus/tmu_csr.h
-@@ -0,0 +1,102 @@
-+#ifndef _TMU_CSR_H_
-+#define _TMU_CSR_H_
-+
-+#define TMU_VERSION (TMU_CSR_BASE_ADDR + 0x000)
-+#define TMU_INQ_WATERMARK (TMU_CSR_BASE_ADDR + 0x004)
-+#define TMU_PHY_INQ_PKTPTR (TMU_CSR_BASE_ADDR + 0x008)
-+#define TMU_PHY_INQ_PKTINFO (TMU_CSR_BASE_ADDR + 0x00c)
-+#define TMU_PHY_INQ_FIFO_CNT (TMU_CSR_BASE_ADDR + 0x010)
-+#define TMU_SYS_GENERIC_CONTROL (TMU_CSR_BASE_ADDR + 0x014)
-+#define TMU_SYS_GENERIC_STATUS (TMU_CSR_BASE_ADDR + 0x018)
-+#define TMU_SYS_GEN_CON0 (TMU_CSR_BASE_ADDR + 0x01c)
-+#define TMU_SYS_GEN_CON1 (TMU_CSR_BASE_ADDR + 0x020)
-+#define TMU_SYS_GEN_CON2 (TMU_CSR_BASE_ADDR + 0x024)
-+#define TMU_SYS_GEN_CON3 (TMU_CSR_BASE_ADDR + 0x028)
-+#define TMU_SYS_GEN_CON4 (TMU_CSR_BASE_ADDR + 0x02c)
-+#define TMU_TEQ_DISABLE_DROPCHK (TMU_CSR_BASE_ADDR + 0x030)
-+#define TMU_TEQ_CTRL (TMU_CSR_BASE_ADDR + 0x034)
-+#define TMU_TEQ_QCFG (TMU_CSR_BASE_ADDR + 0x038)
-+#define TMU_TEQ_DROP_STAT (TMU_CSR_BASE_ADDR + 0x03c)
-+#define TMU_TEQ_QAVG (TMU_CSR_BASE_ADDR + 0x040)
-+#define TMU_TEQ_WREG_PROB (TMU_CSR_BASE_ADDR + 0x044)
-+#define TMU_TEQ_TRANS_STAT (TMU_CSR_BASE_ADDR + 0x048)
-+#define TMU_TEQ_HW_PROB_CFG0 (TMU_CSR_BASE_ADDR + 0x04c)
-+#define TMU_TEQ_HW_PROB_CFG1 (TMU_CSR_BASE_ADDR + 0x050)
-+#define TMU_TEQ_HW_PROB_CFG2 (TMU_CSR_BASE_ADDR + 0x054)
-+#define TMU_TEQ_HW_PROB_CFG3 (TMU_CSR_BASE_ADDR + 0x058)
-+#define TMU_TEQ_HW_PROB_CFG4 (TMU_CSR_BASE_ADDR + 0x05c)
-+#define TMU_TEQ_HW_PROB_CFG5 (TMU_CSR_BASE_ADDR + 0x060)
-+#define TMU_TEQ_HW_PROB_CFG6 (TMU_CSR_BASE_ADDR + 0x064)
-+#define TMU_TEQ_HW_PROB_CFG7 (TMU_CSR_BASE_ADDR + 0x068)
-+#define TMU_TEQ_HW_PROB_CFG8 (TMU_CSR_BASE_ADDR + 0x06c)
-+#define TMU_TEQ_HW_PROB_CFG9 (TMU_CSR_BASE_ADDR + 0x070)
-+#define TMU_TEQ_HW_PROB_CFG10 (TMU_CSR_BASE_ADDR + 0x074)
-+#define TMU_TEQ_HW_PROB_CFG11 (TMU_CSR_BASE_ADDR + 0x078)
-+#define TMU_TEQ_HW_PROB_CFG12 (TMU_CSR_BASE_ADDR + 0x07c)
-+#define TMU_TEQ_HW_PROB_CFG13 (TMU_CSR_BASE_ADDR + 0x080)
-+#define TMU_TEQ_HW_PROB_CFG14 (TMU_CSR_BASE_ADDR + 0x084)
-+#define TMU_TEQ_HW_PROB_CFG15 (TMU_CSR_BASE_ADDR + 0x088)
-+#define TMU_TEQ_HW_PROB_CFG16 (TMU_CSR_BASE_ADDR + 0x08c)
-+#define TMU_TEQ_HW_PROB_CFG17 (TMU_CSR_BASE_ADDR + 0x090)
-+#define TMU_TEQ_HW_PROB_CFG18 (TMU_CSR_BASE_ADDR + 0x094)
-+#define TMU_TEQ_HW_PROB_CFG19 (TMU_CSR_BASE_ADDR + 0x098)
-+#define TMU_TEQ_HW_PROB_CFG20 (TMU_CSR_BASE_ADDR + 0x09c)
-+#define TMU_TEQ_HW_PROB_CFG21 (TMU_CSR_BASE_ADDR + 0x0a0)
-+#define TMU_TEQ_HW_PROB_CFG22 (TMU_CSR_BASE_ADDR + 0x0a4)
-+#define TMU_TEQ_HW_PROB_CFG23 (TMU_CSR_BASE_ADDR + 0x0a8)
-+#define TMU_TEQ_HW_PROB_CFG24 (TMU_CSR_BASE_ADDR + 0x0ac)
-+#define TMU_TEQ_HW_PROB_CFG25 (TMU_CSR_BASE_ADDR + 0x0b0)
-+#define TMU_TDQ_IIFG_CFG (TMU_CSR_BASE_ADDR + 0x0b4)
-+#define TMU_TDQ0_SCH_CTRL (TMU_CSR_BASE_ADDR + 0x0b8) /**< [9:0] Scheduler Enable for each of the scheduler in the TDQ. This is a global Enable for all schedulers in PHY0 */
-+#define TMU_LLM_CTRL (TMU_CSR_BASE_ADDR + 0x0bc)
-+#define TMU_LLM_BASE_ADDR (TMU_CSR_BASE_ADDR + 0x0c0)
-+#define TMU_LLM_QUE_LEN (TMU_CSR_BASE_ADDR + 0x0c4)
-+#define TMU_LLM_QUE_HEADPTR (TMU_CSR_BASE_ADDR + 0x0c8)
-+#define TMU_LLM_QUE_TAILPTR (TMU_CSR_BASE_ADDR + 0x0cc)
-+#define TMU_LLM_QUE_DROPCNT (TMU_CSR_BASE_ADDR + 0x0d0)
-+#define TMU_INT_EN (TMU_CSR_BASE_ADDR + 0x0d4)
-+#define TMU_INT_SRC (TMU_CSR_BASE_ADDR + 0x0d8)
-+#define TMU_INQ_STAT (TMU_CSR_BASE_ADDR + 0x0dc)
-+#define TMU_CTRL (TMU_CSR_BASE_ADDR + 0x0e0)
-+
-+#define TMU_MEM_ACCESS_ADDR (TMU_CSR_BASE_ADDR + 0x0e4) /**< [31] Mem Access Command. 0 = Internal Memory Read, 1 = Internal memory Write [27:24] Byte Enables of the Internal memory access [23:0] Address of the internal memory. This address is used to access both the PM and DM of all the PE's */
-+#define TMU_MEM_ACCESS_WDATA (TMU_CSR_BASE_ADDR + 0x0e8) /**< Internal Memory Access Write Data */
-+#define TMU_MEM_ACCESS_RDATA (TMU_CSR_BASE_ADDR + 0x0ec) /**< Internal Memory Access Read Data. The commands are blocked at the mem_access only */
-+
-+#define TMU_PHY0_INQ_ADDR (TMU_CSR_BASE_ADDR + 0x0f0) /**< [31:0] PHY0 in queue address (must be initialized with one of the xxx_INQ_PKTPTR cbus addresses) */
-+#define TMU_PHY1_INQ_ADDR (TMU_CSR_BASE_ADDR + 0x0f4) /**< [31:0] PHY1 in queue address (must be initialized with one of the xxx_INQ_PKTPTR cbus addresses) */
-+#define TMU_PHY2_INQ_ADDR (TMU_CSR_BASE_ADDR + 0x0f8) /**< [31:0] PHY2 in queue address (must be initialized with one of the xxx_INQ_PKTPTR cbus addresses) */
-+#define TMU_PHY3_INQ_ADDR (TMU_CSR_BASE_ADDR + 0x0fc) /**< [31:0] PHY3 in queue address (must be initialized with one of the xxx_INQ_PKTPTR cbus addresses) */
-+#define TMU_BMU_INQ_ADDR (TMU_CSR_BASE_ADDR + 0x100)
-+#define TMU_TX_CTRL (TMU_CSR_BASE_ADDR + 0x104)
-+
-+#define TMU_BUS_ACCESS_WDATA (TMU_CSR_BASE_ADDR + 0x108)
-+#define TMU_BUS_ACCESS (TMU_CSR_BASE_ADDR + 0x10c)
-+#define TMU_BUS_ACCESS_RDATA (TMU_CSR_BASE_ADDR + 0x110)
-+
-+#define TMU_PE_SYS_CLK_RATIO (TMU_CSR_BASE_ADDR + 0x114)
-+#define TMU_PE_STATUS (TMU_CSR_BASE_ADDR + 0x118)
-+#define TMU_TEQ_MAX_THRESHOLD (TMU_CSR_BASE_ADDR + 0x11c)
-+#define TMU_PHY4_INQ_ADDR (TMU_CSR_BASE_ADDR + 0x134) /**< [31:0] PHY4 in queue address (must be initialized with one of the xxx_INQ_PKTPTR cbus addresses) */
-+#define TMU_TDQ1_SCH_CTRL (TMU_CSR_BASE_ADDR + 0x138) /**< [9:0] Scheduler Enable for each of the scheduler in the TDQ. This is a global Enable for all schedulers in PHY1 */
-+#define TMU_TDQ2_SCH_CTRL (TMU_CSR_BASE_ADDR + 0x13c) /**< [9:0] Scheduler Enable for each of the scheduler in the TDQ. This is a global Enable for all schedulers in PHY2 */
-+#define TMU_TDQ3_SCH_CTRL (TMU_CSR_BASE_ADDR + 0x140) /**< [9:0] Scheduler Enable for each of the scheduler in the TDQ. This is a global Enable for all schedulers in PHY3 */
-+#define TMU_BMU_BUF_SIZE (TMU_CSR_BASE_ADDR + 0x144)
-+#define TMU_PHY5_INQ_ADDR (TMU_CSR_BASE_ADDR + 0x148) /**< [31:0] PHY5 in queue address (must be initialized with one of the xxx_INQ_PKTPTR cbus addresses) */
-+
-+#define SW_RESET (1 << 0) /**< Global software reset */
-+#define INQ_RESET (1 << 2)
-+#define TEQ_RESET (1 << 3)
-+#define TDQ_RESET (1 << 4)
-+#define PE_RESET (1 << 5)
-+#define MEM_INIT (1 << 6)
-+#define MEM_INIT_DONE (1 << 7)
-+#define LLM_INIT (1 << 8)
-+#define LLM_INIT_DONE (1 << 9)
-+
-+typedef struct {
-+ u32 llm_base_addr;
-+ u32 llm_queue_len;
-+} TMU_CFG;
-+
-+#endif /* _TMU_CSR_H_ */
-diff --git a/drivers/net/pfe_eth/pfe/cbus/util_csr.h b/drivers/net/pfe_eth/pfe/cbus/util_csr.h
-new file mode 100644
-index 0000000..d67e849
---- /dev/null
-+++ b/drivers/net/pfe_eth/pfe/cbus/util_csr.h
-@@ -0,0 +1,43 @@
-+#ifndef _UTIL_CSR_H_
-+#define _UTIL_CSR_H_
-+
-+#define UTIL_VERSION (UTIL_CSR_BASE_ADDR + 0x000)
-+#define UTIL_TX_CTRL (UTIL_CSR_BASE_ADDR + 0x004)
-+#define UTIL_INQ_PKTPTR (UTIL_CSR_BASE_ADDR + 0x010)
-+
-+#define UTIL_HDR_SIZE (UTIL_CSR_BASE_ADDR + 0x014)
-+
-+#define UTIL_PE0_QB_DM_ADDR0 (UTIL_CSR_BASE_ADDR + 0x020)
-+#define UTIL_PE0_QB_DM_ADDR1 (UTIL_CSR_BASE_ADDR + 0x024)
-+#define UTIL_PE0_RO_DM_ADDR0 (UTIL_CSR_BASE_ADDR + 0x060)
-+#define UTIL_PE0_RO_DM_ADDR1 (UTIL_CSR_BASE_ADDR + 0x064)
-+
-+#define UTIL_MEM_ACCESS_ADDR (UTIL_CSR_BASE_ADDR + 0x100)
-+#define UTIL_MEM_ACCESS_WDATA (UTIL_CSR_BASE_ADDR + 0x104)
-+#define UTIL_MEM_ACCESS_RDATA (UTIL_CSR_BASE_ADDR + 0x108)
-+
-+#define UTIL_TM_INQ_ADDR (UTIL_CSR_BASE_ADDR + 0x114)
-+#define UTIL_PE_STATUS (UTIL_CSR_BASE_ADDR + 0x118)
-+
-+#define UTIL_PE_SYS_CLK_RATIO (UTIL_CSR_BASE_ADDR + 0x200)
-+#define UTIL_AFULL_THRES (UTIL_CSR_BASE_ADDR + 0x204)
-+#define UTIL_GAP_BETWEEN_READS (UTIL_CSR_BASE_ADDR + 0x208)
-+#define UTIL_MAX_BUF_CNT (UTIL_CSR_BASE_ADDR + 0x20c)
-+#define UTIL_TSQ_FIFO_THRES (UTIL_CSR_BASE_ADDR + 0x210)
-+#define UTIL_TSQ_MAX_CNT (UTIL_CSR_BASE_ADDR + 0x214)
-+#define UTIL_IRAM_DATA_0 (UTIL_CSR_BASE_ADDR + 0x218)
-+#define UTIL_IRAM_DATA_1 (UTIL_CSR_BASE_ADDR + 0x21c)
-+#define UTIL_IRAM_DATA_2 (UTIL_CSR_BASE_ADDR + 0x220)
-+#define UTIL_IRAM_DATA_3 (UTIL_CSR_BASE_ADDR + 0x224)
-+
-+#define UTIL_BUS_ACCESS_ADDR (UTIL_CSR_BASE_ADDR + 0x228)
-+#define UTIL_BUS_ACCESS_WDATA (UTIL_CSR_BASE_ADDR + 0x22c)
-+#define UTIL_BUS_ACCESS_RDATA (UTIL_CSR_BASE_ADDR + 0x230)
-+
-+#define UTIL_INQ_AFULL_THRES (UTIL_CSR_BASE_ADDR + 0x234)
-+#define UTIL_MISC_REG (UTIL_CSR_BASE_ADDR + 0x240)
-+
-+typedef struct {
-+} UTIL_CFG;
-+
-+#endif /* _UTIL_CSR_H_ */
-diff --git a/drivers/net/pfe_eth/pfe/class.h b/drivers/net/pfe_eth/pfe/class.h
-new file mode 100644
-index 0000000..33ad826
---- /dev/null
-+++ b/drivers/net/pfe_eth/pfe/class.h
-@@ -0,0 +1,142 @@
-+#ifndef _CLASS_H_
-+#define _CLASS_H_
-+
-+#define CLASS_DMEM_BASE_ADDR 0x00000000
-+#define CLASS_DMEM_SIZE 0x2000
-+#define CLASS_DMEM_END (CLASS_DMEM_BASE_ADDR + CLASS_DMEM_SIZE)
-+#define CLASS_PMEM_BASE_ADDR 0x00010000
-+
-+#define CBUS_BASE_ADDR 0xc0000000
-+#define CLASS_APB_BASE_ADDR 0xc1000000
-+#define CLASS_AHB1_BASE_ADDR 0xc2000000
-+#define CLASS_AHB2_BASE_ADDR 0xc3000000
-+
-+#include "cbus.h"
-+
-+#define GPT_BASE_ADDR (CLASS_APB_BASE_ADDR + 0x00000)
-+#define UART_BASE_ADDR (CLASS_APB_BASE_ADDR + 0x10000)
-+#define PERG_BASE_ADDR (CLASS_APB_BASE_ADDR + 0x20000)
-+#define EFET_BASE_ADDR (CLASS_APB_BASE_ADDR + 0x40000)
-+
-+#define MAC_HASH_BASE_ADDR (CLASS_AHB1_BASE_ADDR + 0x30000)
-+#define VLAN_HASH_BASE_ADDR (CLASS_AHB1_BASE_ADDR + 0x50000)
-+
-+#define PE_LMEM_BASE_ADDR (CLASS_AHB2_BASE_ADDR + 0x10000)
-+#define PE_LMEM_SIZE 0x8000
-+#define PE_LMEM_END (PE_LMEM_BASE_ADDR + PE_LMEM_SIZE)
-+#define CCU_BASE_ADDR (CLASS_AHB2_BASE_ADDR + 0x20000)
-+
-+#define IS_DMEM(addr, len) (((unsigned long)(addr) >= CLASS_DMEM_BASE_ADDR) && (((unsigned long)(addr) + (len)) <= CLASS_DMEM_END))
-+#define IS_PE_LMEM(addr, len) (((unsigned long)(addr) >= PE_LMEM_BASE_ADDR) && (((unsigned long)(addr) + (len)) <= PE_LMEM_END))
-+
-+
-+#include "gpt.h"
-+#include "uart.h"
-+#include "class/perg.h"
-+#include "class/efet.h"
-+#include "class/mac_hash.h"
-+#include "class/vlan_hash.h"
-+#include "class/ccu.h"
-+
-+
-+#define CLASS_MAX_PBUFFERS 4
-+
-+#define PBUF_HWPARSE_OFFSET 0x10 /* Fixed by hardware */
-+
-+#define PAYLOAD_DMEM_MAX_SIZE (CLASS_PBUF_SIZE - CLASS_PBUF_HEADER_OFFSET - sizeof(class_rx_hdr_t))
-+
-+#define PHYPORT_0 0x0
-+#define PHYPORT_1 0x1
-+#define HOST_PORT_NO 0x3
-+
-+#define ACT_SRC_MAC_REPLACE (1 << (4+0))
-+#define ACT_VLAN_REPLACE (1 << (4+3))
-+#define ACT_TCPCHKSUM_REPLACE (1 << (4+2))
-+#define ACT_VLAN_ADD (1 << (4+1))
-+
-+#define MIN_PKT_SIZE 56
-+
-+#define PARSE_ETH_TYPE (1 << 0)
-+#define PARSE_VLAN_TYPE (1 << 1)
-+#define PARSE_PPPOE_TYPE (1 << 2)
-+#define PARSE_ARP_TYPE (1 << 3)
-+#define PARSE_MCAST_TYPE (1 << 4)
-+#define PARSE_IP_TYPE (1 << 5)
-+#define PARSE_IPV6_TYPE (1 << 6)
-+#define PARSE_IPV4_TYPE (1 << 7)
-+
-+#define PARSE_IPX_TYPE (1 << 9)
-+
-+#define PARSE_UDP_FLOW (1 << 11)
-+#define PARSE_TCP_FLOW (1 << 12)
-+#define PARSE_ICMP_FLOW (1 << 13)
-+#define PARSE_IGMP_FLOW (1 << 14)
-+#define PARSE_FRAG_FLOW (1 << 15)
-+
-+#define PARSE_HIF_PKT (1 << 23)
-+#define PARSE_ARC_HIT (1 << 24)
-+#define PARSE_PKT_OVERFLOW (1 << 25)
-+
-+#define PARSE_PROTO_MISMATCH (1 << 28)
-+#define PARSE_L3_MISMATCH (1 << 29)
-+#define PARSE_L2_MISMATCH (1 << 30)
-+#define PARSE_INCOMPLETE (1 << 31)
-+
-+
-+typedef struct _hwparse_t {
-+ u16 sid;
-+ u16 connid;
-+ u8 toevec;
-+ u8 pLayer2Hdr;
-+ u8 pLayer3Hdr;
-+ u8 pLayer4Hdr;
-+ u16 vlanid;
-+ u16 ifParseFlags;
-+ u32 parseFlags;
-+ u16 srcport;
-+ u16 dstport;
-+ u32 proto:8;
-+ u32 port:4;
-+ u32 hash:20;
-+ u64 rte_res_valid:1;
-+ u64 vlan_res_valid:1;
-+ u64 dst_res_valid:1;
-+ u64 src_res_valid:1;
-+ u64 vlan_lookup:20;
-+ u64 dst_lookup:20;
-+ u64 src_lookup:20;
-+} hwparse_t;
-+
-+
-+typedef struct {
-+ u32 next_ptr; /* ptr to the start of the first DDR buffer */
-+ u16 length; /* total packet length */
-+ u16 phyno; /* input physical port number */
-+ u32 status; /* gemac status bits */
-+ u32 res; /* reserved for software usage */
-+} class_rx_hdr_t;
-+
-+
-+typedef struct {
-+ u8 num_cpy; /* no of copies to send out from RO block, for each there must be a corresponding tx pre-header */
-+ u8 dma_len; /* len to be DMAed to DDR mem, including all tx pre-headers */
-+ u16 src_addr; /* class dmem source address, pointing to first tx pre-header */
-+ u32 dst_addr; /* DDR memory destination address of first tx pre-header, must be so packet data is continuous in DDR */
-+ u32 res1; /* reserved for software usage - queue number? */
-+ u16 res2; /* reserved for software usage */
-+ u16 tsv; /* time stamp val */
-+} class_tx_desc_t;
-+
-+
-+typedef struct {
-+ u8 start_data_off; /* packet data start offset, relative to start of this tx pre-header */
-+ u8 start_buf_off; /* this tx pre-header start offset, relative to start of DDR buffer */
-+ u16 pkt_length; /* total packet lenght */
-+ u8 act_phyno; /* action phy number */
-+ u8 queueno; /* queueno */
-+ u16 src_mac_msb; /* indicates src_mac 47:32 */
-+ u32 src_mac_lsb; /* indicates src_mac 31:0 */
-+ u32 vlanid; /* vlanid */
-+} class_tx_hdr_t;
-+
-+#endif /* _CLASS_H_ */
-diff --git a/drivers/net/pfe_eth/pfe/class/ccu.h b/drivers/net/pfe_eth/pfe/class/ccu.h
-new file mode 100644
-index 0000000..2c43d97
---- /dev/null
-+++ b/drivers/net/pfe_eth/pfe/class/ccu.h
-@@ -0,0 +1,10 @@
-+#ifndef _CCU_H_
-+#define _CCU_H_
-+
-+#define CCU_ADDR (CCU_BASE_ADDR + 0x00)
-+#define CCU_CNT (CCU_BASE_ADDR + 0x04)
-+#define CCU_STATUS (CCU_BASE_ADDR + 0x08)
-+#define CCU_VAL (CCU_BASE_ADDR + 0x0c)
-+
-+#endif /* _CCU_H_ */
-+
-diff --git a/drivers/net/pfe_eth/pfe/class/efet.h b/drivers/net/pfe_eth/pfe/class/efet.h
-new file mode 100644
-index 0000000..4f3cc25
---- /dev/null
-+++ b/drivers/net/pfe_eth/pfe/class/efet.h
-@@ -0,0 +1,21 @@
-+#ifndef _CLASS_EFET_H_
-+#define _CLASS_EFET_H_
-+
-+#define CLASS_EFET_ENTRY_ADDR (EFET_BASE_ADDR + 0x00)
-+#define CLASS_EFET_ENTRY_SIZE (EFET_BASE_ADDR + 0x04)
-+#define CLASS_EFET_ENTRY_DMEM_ADDR (EFET_BASE_ADDR + 0x08)
-+#define CLASS_EFET_ENTRY_STATUS (EFET_BASE_ADDR + 0x0c)
-+#define CLASS_EFET_ENTRY_ENDIAN (EFET_BASE_ADDR + 0x10)
-+
-+#define CBUS2DMEM 0
-+#define DMEM2CBUS 1
-+
-+#define EFET2BUS_LE (1 << 0)
-+#define PE2BUS_LE (1 << 1)
-+
-+void class_efet(u32 cbus_addr, u32 dmem_addr, u32 len, u32 dir);
-+void class_efet_wait(void);
-+void class_efet_sync(u32 cbus_addr, u32 dmem_addr, u32 len, u32 dir);
-+
-+#endif /* _CLASS_EFET_H_ */
-+
-diff --git a/drivers/net/pfe_eth/pfe/class/mac_hash.h b/drivers/net/pfe_eth/pfe/class/mac_hash.h
-new file mode 100644
-index 0000000..68023b4
---- /dev/null
-+++ b/drivers/net/pfe_eth/pfe/class/mac_hash.h
-@@ -0,0 +1,28 @@
-+#ifndef _MAC_HASH_H_
-+#define _MAC_HASH_H_
-+
-+#define MAC_HASH_REQ1_BASE_ADDR (MAC_HASH_BASE_ADDR + 0x000)
-+#define MAC_HASH_REQ2_BASE_ADDR (MAC_HASH_BASE_ADDR + 0x020)
-+#define MAC_HASH_REQ3_BASE_ADDR (MAC_HASH_BASE_ADDR + 0x040)
-+#define MAC_HASH_REQ4_BASE_ADDR (MAC_HASH_BASE_ADDR + 0x060)
-+#define MAC_HASH_REQ5_BASE_ADDR (MAC_HASH_BASE_ADDR + 0x080)
-+#define MAC_HASH_REQ6_BASE_ADDR (MAC_HASH_BASE_ADDR + 0x0a0)
-+#define MAC_HASH_REQ7_BASE_ADDR (MAC_HASH_BASE_ADDR + 0x0c0)
-+#define MAC_HASH_REQ8_BASE_ADDR (MAC_HASH_BASE_ADDR + 0x0e0)
-+
-+#define MAC_HASH_REQ_CMD(i) (MAC_HASH_REQ##i##_BASE_ADDR + 0x000)
-+#define MAC_HASH_REQ_MAC1_ADDR(i) (MAC_HASH_REQ##i##_BASE_ADDR + 0x004)
-+#define MAC_HASH_REQ_MAC2_ADDR(i) (MAC_HASH_REQ##i##_BASE_ADDR + 0x008)
-+#define MAC_HASH_REQ_MASK1_ADDR(i) (MAC_HASH_REQ##i##_BASE_ADDR + 0x00c)
-+#define MAC_HASH_REQ_MASK2_ADDR(i) (MAC_HASH_REQ##i##_BASE_ADDR + 0x010)
-+#define MAC_HASH_REQ_ENTRY(i) (MAC_HASH_REQ##i##_BASE_ADDR + 0x014)
-+#define MAC_HASH_REQ_STATUS(i) (MAC_HASH_REQ##i##_BASE_ADDR + 0x018)
-+#define MAC_HASH_REQ_ENTRY_MAYCH(i) (MAC_HASH_REQ##i##_BASE_ADDR + 0x01c)
-+
-+
-+#define MAC_HASH_FREELIST_PTR_HEAD (MAC_HASH_BASE_ADDR + 0x100)
-+#define MAC_HASH_FREELIST_PTR_TAIL (MAC_HASH_BASE_ADDR + 0x104)
-+#define MAC_HASH_FREELIST_ENTRIES_ADDR (MAC_HASH_BASE_ADDR + 0x108)
-+
-+#endif /* _MAC_HASH_H_ */
-+
-diff --git a/drivers/net/pfe_eth/pfe/class/perg.h b/drivers/net/pfe_eth/pfe/class/perg.h
-new file mode 100644
-index 0000000..7297171
---- /dev/null
-+++ b/drivers/net/pfe_eth/pfe/class/perg.h
-@@ -0,0 +1,21 @@
-+#ifndef _PERG_H_
-+#define _PERG_H_
-+
-+#define PERG_QB_BUF_STATUS (PERG_BASE_ADDR + 0x00)
-+#define PERG_RO_BUF_STATUS (PERG_BASE_ADDR + 0x04)
-+#define PERG_CLR_QB_BUF_STATUS (PERG_BASE_ADDR + 0x08)
-+#define PERG_SET_RO_BUF_STATUS (PERG_BASE_ADDR + 0x0c)
-+#define PERG_CLR_RO_ERR_PKT (PERG_BASE_ADDR + 0x10)
-+#define PERG_CLR_BMU2_ERR_PKT (PERG_BASE_ADDR + 0x14)
-+
-+#define PERG_ID (PERG_BASE_ADDR + 0x18)
-+#define PERG_TIMER1 (PERG_BASE_ADDR + 0x1c)
-+#define PERG_TIMER2 (PERG_BASE_ADDR + 0x20)
-+#define PERG_BUF1 (PERG_BASE_ADDR + 0x24)
-+#define PERG_BUF2 (PERG_BASE_ADDR + 0x28)
-+#define PERG_HOST_GP (PERG_BASE_ADDR + 0x2c)
-+#define PERG_PE_GP (PERG_BASE_ADDR + 0x30)
-+#define PERG_INT_ENABLE (PERG_BASE_ADDR + 0x34)
-+#define PERG_INT_SRC (PERG_BASE_ADDR + 0x38)
-+
-+#endif /* _PERG_H_ */
-diff --git a/drivers/net/pfe_eth/pfe/class/vlan_hash.h b/drivers/net/pfe_eth/pfe/class/vlan_hash.h
-new file mode 100644
-index 0000000..a54ac19
---- /dev/null
-+++ b/drivers/net/pfe_eth/pfe/class/vlan_hash.h
-@@ -0,0 +1,28 @@
-+#ifndef _VLAN_HASH_H_
-+#define _VLAN_HASH_H_
-+
-+#define VLAN_HASH_REQ1_BASE_ADDR (VLAN_HASH_BASE_ADDR + 0x000)
-+#define VLAN_HASH_REQ2_BASE_ADDR (VLAN_HASH_BASE_ADDR + 0x020)
-+#define VLAN_HASH_REQ3_BASE_ADDR (VLAN_HASH_BASE_ADDR + 0x040)
-+#define VLAN_HASH_REQ4_BASE_ADDR (VLAN_HASH_BASE_ADDR + 0x060)
-+#define VLAN_HASH_REQ5_BASE_ADDR (VLAN_HASH_BASE_ADDR + 0x080)
-+#define VLAN_HASH_REQ6_BASE_ADDR (VLAN_HASH_BASE_ADDR + 0x0a0)
-+#define VLAN_HASH_REQ7_BASE_ADDR (VLAN_HASH_BASE_ADDR + 0x0c0)
-+#define VLAN_HASH_REQ8_BASE_ADDR (VLAN_HASH_BASE_ADDR + 0x0e0)
-+
-+#define VLAN_HASH_REQ_CMD(i) (VLAN_HASH_REQ##i##_BASE_ADDR + 0x000)
-+#define VLAN_HASH_REQ_MAC1_ADDR(i) (VLAN_HASH_REQ##i##_BASE_ADDR + 0x004)
-+#define VLAN_HASH_REQ_MAC2_ADDR(i) (VLAN_HASH_REQ##i##_BASE_ADDR + 0x008)
-+#define VLAN_HASH_REQ_MASK1_ADDR(i) (VLAN_HASH_REQ##i##_BASE_ADDR + 0x00c)
-+#define VLAN_HASH_REQ_MASK2_ADDR(i) (VLAN_HASH_REQ##i##_BASE_ADDR + 0x010)
-+#define VLAN_HASH_REQ_ENTRY(i) (VLAN_HASH_REQ##i##_BASE_ADDR + 0x014)
-+#define VLAN_HASH_REQ_STATUS(i) (VLAN_HASH_REQ##i##_BASE_ADDR + 0x018)
-+#define VLAN_HASH_REQ_ENTRY_MAYCH(i) (VLAN_HASH_REQ##i##_BASE_ADDR + 0x01c)
-+
-+
-+#define VLAN_HASH_FREELIST_PTR_HEAD (VLAN_HASH_BASE_ADDR + 0x100)
-+#define VLAN_HASH_FREELIST_PTR_TAIL (VLAN_HASH_BASE_ADDR + 0x104)
-+#define VLAN_HASH_FREELIST_ENTRIES_ADDR (VLAN_HASH_BASE_ADDR + 0x108)
-+
-+#endif /* _VLAN_HASH_H_ */
-+
-diff --git a/drivers/net/pfe_eth/pfe/gpt.h b/drivers/net/pfe_eth/pfe/gpt.h
-new file mode 100644
-index 0000000..d820277
---- /dev/null
-+++ b/drivers/net/pfe_eth/pfe/gpt.h
-@@ -0,0 +1,11 @@
-+#ifndef _GPT_H_
-+#define _GPT_H_
-+
-+#define GPT_VERSION (GPT_BASE_ADDR + 0x00)
-+#define GPT_STATUS (GPT_BASE_ADDR + 0x04)
-+#define GPT_CONFIG (GPT_BASE_ADDR + 0x08)
-+#define GPT_COUNTER (GPT_BASE_ADDR + 0x0c)
-+#define GPT_PERIOD (GPT_BASE_ADDR + 0x10)
-+#define GPT_WIDTH (GPT_BASE_ADDR + 0x14)
-+
-+#endif /* _GPT_H_ */
-diff --git a/drivers/net/pfe_eth/pfe/pe.h b/drivers/net/pfe_eth/pfe/pe.h
-new file mode 100644
-index 0000000..a3838f5
---- /dev/null
-+++ b/drivers/net/pfe_eth/pfe/pe.h
-@@ -0,0 +1,147 @@
-+#ifndef _PE_H_
-+#define _PE_H_
-+
-+#include "hal.h"
-+
-+#define DDR_BASE_ADDR 0x00020000
-+#define DDR_END 0x86000000 /* This includes ACP and IRAM areas */
-+#define IRAM_BASE_ADDR 0x83000000
-+
-+#define IS_DDR(addr, len) (((unsigned long)(addr) >= DDR_BASE_ADDR) && (((unsigned long)(addr) + (len)) <= DDR_END))
-+
-+typedef struct {
-+
-+} ddr_rx_hdr_t;
-+
-+typedef struct {
-+
-+} lmem_rx_hdr_t;
-+
-+
-+typedef struct {
-+
-+} tmu_rx_hdr_t;
-+
-+typedef struct {
-+
-+} tmu_tx_hdr_t;
-+
-+typedef struct {
-+
-+} util_rx_hdr_t;
-+
-+
-+struct pe_sync_mailbox
-+{
-+ u32 stop;
-+ u32 stopped;
-+};
-+
-+struct pe_msg_mailbox
-+{
-+ u32 dst;
-+ u32 src;
-+ u32 len;
-+ u32 request;
-+};
-+
-+/** Basic busy loop delay function
-+*
-+* @param cycles Number of cycles to delay (actual cpu cycles should be close to 3 x cycles)
-+*
-+*/
-+static inline void delay(u32 cycles)
-+{
-+ volatile int i;
-+
-+ for (i = 0; i < cycles; i++);
-+}
-+
-+
-+/** Read PE id
-+*
-+* @return PE id (0 - 5 for CLASS-PE's, 6 - 9 for TMU-PE's, 10 for UTIL-PE)
-+*
-+*/
-+static inline u32 esi_get_mpid(void)
-+{
-+ u32 mpid;
-+
-+ asm ("rcsr %0, Configuration, MPID" : "=d" (mpid));
-+
-+ return mpid;
-+}
-+
-+/** 64bit aligned memory copy using efet.
-+* Either the source or destination address must be in DMEM, the other address can be in LMEM or DDR.
-+* Source, destination addresses and len must all be 64bit aligned.
-+* Uses efet synchronous interface to copy the data.
-+*
-+* @param dst Destination address to write to (must be 64bit aligned)
-+* @param src Source address to read from (must be 64bit aligned)
-+* @param len Number of bytes to copy (must be 64bit aligned)
-+*
-+*/
-+void efet_memcpy64(void *dst, void *src, unsigned int len);
-+
-+
-+/** Aligned memory copy using efet.
-+* Either the source or destination address must be in DMEM, the other address can be in LMEM or DDR.
-+* Both the source and destination must have the same 64bit alignment, there is no restriction on length.
-+*
-+* @param dst Destination address to write to (must have the same 64bit alignment as src)
-+* @param src Source address to read from (must have the same 64bit alignment as dst)
-+* @param len Number of bytes to copy
-+*
-+*/
-+void efet_memcpy(void *dst, void *src, unsigned int len);
-+
-+
-+/** 32bit aligned memory copy.
-+* Source and destination addresses must be 32bit aligned, there is no restriction on the length.
-+*
-+* @param dst Destination address (must be 32bit aligned)
-+* @param src Source address (must be 32bit aligned)
-+* @param len Number of bytes to copy
-+*
-+*/
-+void memcpy_aligned32(void *dst, void *src, unsigned int len);
-+
-+/** Aligned memory copy.
-+* Source and destination addresses must have the same alignment
-+* relative to 32bit boundaries (but otherwsie may have any alignment),
-+* there is no restriction on the length.
-+*
-+* @param dst Destination address
-+* @param src Source address (must have same 32bit alignment as dst)
-+* @param len Number of bytes to copy
-+*
-+*/
-+void memcpy_aligned(void *dst, void *src, unsigned int len);
-+
-+
-+/** Generic memory set.
-+* Implements a generic memory set. Not very optimal (uses byte writes for the entire range)
-+*
-+*
-+* @param dst Destination address
-+* @param val Value to set memory to
-+* @param len Number of bytes to set
-+*
-+*/
-+void memset(void *dst, u8 val, unsigned int len);
-+
-+/** Generic memory copy.
-+* Implements generic memory copy. If source and destination have the same
-+* alignment memcpy_aligned() is used, otherwise, we first align the destination
-+* to a 32bit boundary (using byte copies) then the src, and finally use a loop
-+* of read, shift, write
-+*
-+* @param dst Destination address
-+* @param src Source address
-+* @param len Number of bytes to copy
-+*
-+*/
-+void memcpy(void *dst, void *src, unsigned int len);
-+
-+#endif /* _PE_H_ */
-diff --git a/drivers/net/pfe_eth/pfe/pfe.h b/drivers/net/pfe_eth/pfe/pfe.h
-new file mode 100644
-index 0000000..e8e2221
---- /dev/null
-+++ b/drivers/net/pfe_eth/pfe/pfe.h
-@@ -0,0 +1,250 @@
-+#ifndef _PFE_H_
-+#define _PFE_H_
-+
-+#define CLASS_DMEM_BASE_ADDR(i) (0x00000000 | ((i) << 20))
-+#define CLASS_IMEM_BASE_ADDR(i) (0x00000000 | ((i) << 20)) /* Only valid for mem access register interface */
-+#define CLASS_DMEM_SIZE 0x00002000
-+#define CLASS_IMEM_SIZE 0x00008000
-+
-+#define TMU_DMEM_BASE_ADDR(i) (0x00000000 + ((i) << 20))
-+#define TMU_IMEM_BASE_ADDR(i) (0x00000000 + ((i) << 20)) /* Only valid for mem access register interface */
-+#define TMU_DMEM_SIZE 0x00000800
-+#define TMU_IMEM_SIZE 0x00002000
-+
-+#define UTIL_DMEM_BASE_ADDR 0x00000000
-+#define UTIL_DMEM_SIZE 0x00002000
-+
-+#define PE_LMEM_BASE_ADDR 0xc3010000
-+#define PE_LMEM_SIZE 0x8000
-+#define PE_LMEM_END (PE_LMEM_BASE_ADDR + PE_LMEM_SIZE)
-+
-+#define DMEM_BASE_ADDR 0x00000000
-+#define DMEM_SIZE 0x2000 /**< TMU has less... */
-+#define DMEM_END (DMEM_BASE_ADDR + DMEM_SIZE)
-+
-+#define PMEM_BASE_ADDR 0x00010000
-+#define PMEM_SIZE 0x8000 /**< TMU has less... */
-+#define PMEM_END (PMEM_BASE_ADDR + PMEM_SIZE)
-+
-+
-+/* Memory ranges check from PE point of view/memory map */
-+#define IS_DMEM(addr, len) (((unsigned long)(addr) >= DMEM_BASE_ADDR) && (((unsigned long)(addr) + (len)) <= DMEM_END))
-+#define IS_PMEM(addr, len) (((unsigned long)(addr) >= PMEM_BASE_ADDR) && (((unsigned long)(addr) + (len)) <= PMEM_END))
-+#define IS_PE_LMEM(addr, len) (((unsigned long)(addr) >= PE_LMEM_BASE_ADDR) && (((unsigned long)(addr) + (len)) <= PE_LMEM_END))
-+
-+#define IS_PFE_LMEM(addr, len) (((unsigned long)(addr) >= CBUS_VIRT_TO_PFE(LMEM_BASE_ADDR)) && (((unsigned long)(addr) + (len)) <= CBUS_VIRT_TO_PFE(LMEM_END)))
-+#define IS_PHYS_DDR(addr, len) (((unsigned long)(addr) >= PFE_DDR_PHYS_BASE_ADDR) && (((unsigned long)(addr) + (len)) <= PFE_DDR_PHYS_END))
-+
-+/* Host View Address */
-+extern void *cbus_base_addr;
-+extern void *ddr_base_addr;
-+#define CBUS_BASE_ADDR cbus_base_addr
-+#define DDR_BASE_ADDR ddr_base_addr
-+
-+/* PFE View Address */
-+#define PFE_DDR_PHYS_BASE_ADDR 0x03800000 /**< DDR physical base address as seen by PE's. */
-+#define PFE_DDR_PHYS_SIZE 0xC000000
-+#define PFE_DDR_PHYS_END (PFE_DDR_PHYS_BASE_ADDR + PFE_DDR_PHYS_SIZE)
-+#define PFE_CBUS_PHYS_BASE_ADDR 0xc0000000 /**< CBUS physical base address as seen by PE's. */
-+
-+/* Host<->PFE Mapping */
-+#define DDR_PFE_TO_VIRT(p) ((p ) + 0x80000000)
-+#define CBUS_VIRT_TO_PFE(v) (((v) - CBUS_BASE_ADDR) + PFE_CBUS_PHYS_BASE_ADDR)
-+#define CBUS_PFE_TO_VIRT(p) (((p) - PFE_CBUS_PHYS_BASE_ADDR) + CBUS_BASE_ADDR)
-+
-+#include "cbus.h"
-+
-+enum {
-+ CLASS0_ID = 0,
-+ CLASS1_ID,
-+ CLASS2_ID,
-+ CLASS3_ID,
-+#if !defined(CONFIG_PLATFORM_PCI)
-+ CLASS4_ID,
-+ CLASS5_ID,
-+#endif
-+#if !defined(CONFIG_TMU_DUMMY)
-+ TMU0_ID,
-+ TMU1_ID,
-+ TMU2_ID,
-+ TMU3_ID,
-+#else
-+ TMU0_ID,
-+#endif
-+#if !defined(CONFIG_UTIL_PE_DISABLED)
-+ UTIL_ID,
-+#endif
-+ MAX_PE
-+};
-+
-+#if !defined(CONFIG_PLATFORM_PCI)
-+#define CLASS_MASK ((1 << CLASS0_ID) | (1 << CLASS1_ID) | (1 << CLASS2_ID) | (1 << CLASS3_ID) | (1 << CLASS4_ID) | (1 << CLASS5_ID))
-+#define CLASS_MAX_ID CLASS5_ID
-+#else
-+#define CLASS_MASK ((1 << CLASS0_ID) | (1 << CLASS1_ID) | (1 << CLASS2_ID) | (1 << CLASS3_ID))
-+#define CLASS_MAX_ID CLASS3_ID
-+#endif
-+
-+#if !defined(CONFIG_TMU_DUMMY)
-+#if defined(CONFIG_LS1012A)
-+#define TMU_MASK ((1 << TMU0_ID) | (1 << TMU1_ID) | (1 << TMU3_ID))
-+#else
-+#define TMU_MASK ((1 << TMU0_ID) | (1 << TMU1_ID) | (1 << TMU2_ID) | (1 << TMU3_ID))
-+#endif
-+#define TMU_MAX_ID TMU3_ID
-+#else
-+#define TMU_MASK (1 << TMU0_ID)
-+#define TMU_MAX_ID TMU0_ID
-+#endif
-+
-+#if !defined(CONFIG_UTIL_PE_DISABLED)
-+#define UTIL_MASK (1 << UTIL_ID)
-+#endif
-+
-+struct pe_sync_mailbox
-+{
-+ u32 stop;
-+ u32 stopped;
-+};
-+
-+struct pe_msg_mailbox
-+{
-+ u32 dst;
-+ u32 src;
-+ u32 len;
-+ u32 request;
-+};
-+
-+/** PE information.
-+ * Structure containing PE's specific information. It is used to create
-+ * generic C functions common to all PE's.
-+ * Before using the library functions this structure needs to be initialized with the different registers virtual addresses
-+ * (according to the ARM MMU mmaping). The default initialization supports a virtual == physical mapping.
-+ *
-+ */
-+struct pe_info
-+{
-+ u32 dmem_base_addr; /**< PE's dmem base address */
-+ u32 pmem_base_addr; /**< PE's pmem base address */
-+ u32 pmem_size; /**< PE's pmem size */
-+
-+ void *mem_access_wdata; /**< PE's _MEM_ACCESS_WDATA register address */
-+ void *mem_access_addr; /**< PE's _MEM_ACCESS_ADDR register address */
-+ void *mem_access_rdata; /**< PE's _MEM_ACCESS_RDATA register address */
-+};
-+
-+
-+void pe_lmem_read(u32 *dst, u32 len, u32 offset);
-+void pe_lmem_write(u32 *src, u32 len, u32 offset);
-+
-+void pe_dmem_memcpy_to32(int id, u32 dst, const void *src, unsigned int len);
-+void pe_pmem_memcpy_to32(int id, u32 dst, const void *src, unsigned int len);
-+
-+u32 pe_pmem_read(int id, u32 addr, u8 size);
-+
-+void pe_dmem_write(int id, u32 val, u32 addr, u8 size);
-+u32 pe_dmem_read(int id, u32 addr, u8 size);
-+void class_bus_write(u32 val, u32 addr, u8 size);
-+u32 class_bus_read(u32 addr, u8 size);
-+void util_bus_write(u32 val, u32 addr, u8 size);
-+u32 util_bus_read(u32 addr, u8 size);
-+
-+#define class_bus_readl(addr) class_bus_read(addr, 4)
-+#define class_bus_readw(addr) class_bus_read(addr, 2)
-+#define class_bus_readb(addr) class_bus_read(addr, 1)
-+
-+#define class_bus_writel(val, addr) class_bus_write(val, addr, 4)
-+#define class_bus_writew(val, addr) class_bus_write(val, addr, 2)
-+#define class_bus_writeb(val, addr) class_bus_write(val, addr, 1)
-+
-+#define pe_mem_readl(id, addr) pe_mem_read(id, addr, 4)
-+#define pe_mem_readw(id, addr) pe_mem_read(id, addr, 2)
-+#define pe_mem_readb(id, addr) pe_mem_read(id, addr, 1)
-+
-+#define pe_mem_writel(id, val, addr) pe_mem_write(id, val, addr, 4)
-+#define pe_mem_writew(id, val, addr) pe_mem_write(id, val, addr, 2)
-+#define pe_mem_writeb(id, val, addr) pe_mem_write(id, val, addr, 1)
-+
-+int pe_load_elf_section(int id, const void *data, Elf32_Shdr *shdr);
-+
-+void pfe_lib_init(void *cbus_base, void *ddr_base, unsigned long ddr_phys_base);
-+void bmu_init(void *base, BMU_CFG *cfg);
-+void bmu_reset(void *base);
-+void bmu_enable(void *base);
-+void bmu_disable(void *base);
-+void bmu_set_config(void *base, BMU_CFG *cfg);
-+
-+#if 0
-+void gemac_init(void *base, void *config);
-+void gemac_set_speed(void *base, MAC_SPEED gem_speed);
-+void gemac_set_duplex(void *base, int duplex);
-+void gemac_set_mode(void *base, int mode);
-+void gemac_enable_mdio(void *base);
-+void gemac_disable_mdio(void *base);
-+void gemac_set_mdc_div(void *base, MAC_MDC_DIV gem_mdcdiv);
-+void gemac_enable(void *base);
-+void gemac_disable(void *base);
-+void gemac_enable_mdio(void *base);
-+void gemac_disable_mdio(void *base);
-+void gemac_reset(void *base);
-+void gemac_set_address(void *base, SPEC_ADDR *addr);
-+SPEC_ADDR gemac_get_address(void *base);
-+void gemac_set_laddr1(void *base, MAC_ADDR *address);
-+void gemac_set_laddr2(void *base, MAC_ADDR *address);
-+void gemac_set_laddr3(void *base, MAC_ADDR *address);
-+void gemac_set_laddr4(void *base, MAC_ADDR *address);
-+void gemac_set_laddrN(void *base, MAC_ADDR *address, unsigned int entry_index);
-+MAC_ADDR gem_get_laddr1(void *base);
-+MAC_ADDR gem_get_laddr2(void *base);
-+MAC_ADDR gem_get_laddr3(void *base);
-+MAC_ADDR gem_get_laddr4(void *base);
-+MAC_ADDR gem_get_laddrN(void *base, unsigned int entry_index);
-+void gemac_set_config(void *base, GEMAC_CFG *cfg);
-+void gemac_enable_copy_all(void *base);
-+void gemac_disable_copy_all(void *base);
-+void gemac_allow_broadcast(void *base);
-+void gemac_no_broadcast(void *base);
-+void gemac_enable_unicast(void *base);
-+void gemac_disable_unicast(void *base);
-+void gemac_enable_multicast(void *base);
-+void gemac_disable_multicast(void *base);
-+void gemac_enable_fcs_rx(void *base);
-+void gemac_disable_fcs_rx(void *base);
-+void gemac_enable_1536_rx(void *base);
-+void gemac_disable_1536_rx(void *base);
-+void gemac_enable_pause_rx(void *base);
-+void gemac_disable_pause_rx(void *base);
-+void gemac_enable_rx_checksum_offload(void *base);
-+void gemac_disable_rx_checksum_offload(void *base);
-+unsigned int * gemac_get_stats(void *base);
-+void gemac_set_bus_width(void *base, int width);
-+#endif
-+
-+void gpi_init(void *base, GPI_CFG *cfg);
-+void gpi_reset(void *base);
-+void gpi_enable(void *base);
-+void gpi_disable(void *base);
-+void gpi_set_config(void *base, GPI_CFG *cfg);
-+
-+void class_init(CLASS_CFG *cfg);
-+void class_reset(void);
-+void class_enable(void);
-+void class_disable(void);
-+void class_set_config(CLASS_CFG *cfg);
-+
-+void tmu_init(TMU_CFG *cfg);
-+void tmu_enable(u32 pe_mask);
-+void tmu_disable(u32 pe_mask);
-+
-+void util_init(UTIL_CFG *cfg);
-+void util_reset(void);
-+void util_enable(void);
-+void util_disable(void);
-+
-+void hif_init(void);
-+void hif_tx_enable(void);
-+void hif_tx_disable(void);
-+void hif_rx_enable(void);
-+void hif_rx_disable(void);
-+
-+#endif /* _PFE_H_ */
-diff --git a/drivers/net/pfe_eth/pfe/tmu.h b/drivers/net/pfe_eth/pfe/tmu.h
-new file mode 100644
-index 0000000..12eaf12
---- /dev/null
-+++ b/drivers/net/pfe_eth/pfe/tmu.h
-@@ -0,0 +1,48 @@
-+#ifndef _TMU_H_
-+#define _TMU_H_
-+
-+#define TMU_DMEM_BASE_ADDR 0x00000000
-+#define TMU_PMEM_BASE_ADDR 0x00010000
-+
-+
-+#define CBUS_BASE_ADDR 0xc0000000
-+#define TMU_APB_BASE_ADDR 0xc1000000
-+
-+#include "cbus.h"
-+
-+#define GPT_BASE_ADDR (TMU_APB_BASE_ADDR + 0x00000)
-+#define UART_BASE_ADDR (TMU_APB_BASE_ADDR + 0x10000)
-+
-+
-+#define SHAPER0_BASE_ADDR (TMU_APB_BASE_ADDR + 0x020000)
-+#define SHAPER1_BASE_ADDR (TMU_APB_BASE_ADDR + 0x030000)
-+#define SHAPER2_BASE_ADDR (TMU_APB_BASE_ADDR + 0x040000)
-+#define SHAPER3_BASE_ADDR (TMU_APB_BASE_ADDR + 0x050000)
-+#define SHAPER4_BASE_ADDR (TMU_APB_BASE_ADDR + 0x060000)
-+#define SHAPER5_BASE_ADDR (TMU_APB_BASE_ADDR + 0x070000)
-+#define SHAPER6_BASE_ADDR (TMU_APB_BASE_ADDR + 0x080000)
-+#define SHAPER7_BASE_ADDR (TMU_APB_BASE_ADDR + 0x090000)
-+#define SHAPER8_BASE_ADDR (TMU_APB_BASE_ADDR + 0x0a0000)
-+#define SHAPER9_BASE_ADDR (TMU_APB_BASE_ADDR + 0x0b0000)
-+
-+#define SCHED0_BASE_ADDR (TMU_APB_BASE_ADDR + 0x1c0000)
-+#define SCHED1_BASE_ADDR (TMU_APB_BASE_ADDR + 0x1d0000)
-+#define SCHED2_BASE_ADDR (TMU_APB_BASE_ADDR + 0x1e0000)
-+#define SCHED3_BASE_ADDR (TMU_APB_BASE_ADDR + 0x1f0000)
-+#define SCHED4_BASE_ADDR (TMU_APB_BASE_ADDR + 0x200000)
-+#define SCHED5_BASE_ADDR (TMU_APB_BASE_ADDR + 0x210000)
-+#define SCHED6_BASE_ADDR (TMU_APB_BASE_ADDR + 0x220000)
-+#define SCHED7_BASE_ADDR (TMU_APB_BASE_ADDR + 0x230000)
-+
-+
-+#define PHY_QUEUE_BASE_ADDR (TMU_APB_BASE_ADDR + 0x260000)
-+#define SHAPER_STATUS (TMU_APB_BASE_ADDR + 0x270000) /**< [9:0] bitmask of shapers that have positive credit */
-+
-+
-+#include "gpt.h"
-+#include "uart.h"
-+#include "tmu/shaper.h"
-+#include "tmu/sched.h"
-+#include "tmu/phy_queue.h"
-+
-+#endif /* _TMU_H_ */
-diff --git a/drivers/net/pfe_eth/pfe/tmu/phy_queue.h b/drivers/net/pfe_eth/pfe/tmu/phy_queue.h
-new file mode 100644
-index 0000000..9eef9a9
---- /dev/null
-+++ b/drivers/net/pfe_eth/pfe/tmu/phy_queue.h
-@@ -0,0 +1,31 @@
-+#ifndef _PHY_QUEUE_H_
-+#define _PHY_QUEUE_H_
-+
-+#define PHY_QUEUE_SHAPER_STATUS (PHY_QUEUE_BASE_ADDR + 0x00) /**< [28:19] same as SHAPER_STATUS, [18:3] same as QUEUE_STATUS, [2:0] must be zero before a new packet may be dequeued */
-+#define QUEUE_STATUS (PHY_QUEUE_BASE_ADDR + 0x04) /**< [15:0] bit mask of input queues with pending packets */
-+
-+#define QUEUE0_PKT_LEN (PHY_QUEUE_BASE_ADDR + 0x08)
-+#define QUEUE1_PKT_LEN (PHY_QUEUE_BASE_ADDR + 0x0c)
-+#define QUEUE2_PKT_LEN (PHY_QUEUE_BASE_ADDR + 0x10)
-+#define QUEUE3_PKT_LEN (PHY_QUEUE_BASE_ADDR + 0x14)
-+#define QUEUE4_PKT_LEN (PHY_QUEUE_BASE_ADDR + 0x18)
-+#define QUEUE5_PKT_LEN (PHY_QUEUE_BASE_ADDR + 0x1c)
-+#define QUEUE6_PKT_LEN (PHY_QUEUE_BASE_ADDR + 0x20)
-+#define QUEUE7_PKT_LEN (PHY_QUEUE_BASE_ADDR + 0x24)
-+#define QUEUE8_PKT_LEN (PHY_QUEUE_BASE_ADDR + 0x28)
-+#define QUEUE9_PKT_LEN (PHY_QUEUE_BASE_ADDR + 0x2c)
-+#define QUEUE10_PKT_LEN (PHY_QUEUE_BASE_ADDR + 0x30)
-+#define QUEUE11_PKT_LEN (PHY_QUEUE_BASE_ADDR + 0x34)
-+#define QUEUE12_PKT_LEN (PHY_QUEUE_BASE_ADDR + 0x38)
-+#define QUEUE13_PKT_LEN (PHY_QUEUE_BASE_ADDR + 0x3c)
-+#define QUEUE14_PKT_LEN (PHY_QUEUE_BASE_ADDR + 0x40)
-+#define QUEUE15_PKT_LEN (PHY_QUEUE_BASE_ADDR + 0x44)
-+#define QUEUE_RESULT0 (PHY_QUEUE_BASE_ADDR + 0x48) /**< [7] set to one to indicate output PHY (TMU0->PHY0, TMU1->PHY1, TMU2->PHY2, TMU3->PHY3), [6:0] winner input queue number */
-+#define QUEUE_RESULT1 (PHY_QUEUE_BASE_ADDR + 0x4c) /**< [7] set to one to indicate output PHY (TMU0->PHY0, TMU1->PHY1, TMU2->PHY2, TMU3->PHY4), [6:0] winner input queue number */
-+#define QUEUE_RESULT2 (PHY_QUEUE_BASE_ADDR + 0x50) /**< [7] set to one to indicate output PHY (TMU0->PHY0, TMU1->PHY1, TMU2->PHY2, TMU3->PHY5), [6:0] winner input queue number */
-+#define QUEUE_GBL_PKTLEN (PHY_QUEUE_BASE_ADDR + 0x5c)
-+#define QUEUE_GBL_PKTLEN_MASK (PHY_QUEUE_BASE_ADDR + 0x60)
-+
-+
-+
-+#endif /* _PHY_QUEUE_H_ */
-diff --git a/drivers/net/pfe_eth/pfe/tmu/sched.h b/drivers/net/pfe_eth/pfe/tmu/sched.h
-new file mode 100644
-index 0000000..0c741cc
---- /dev/null
-+++ b/drivers/net/pfe_eth/pfe/tmu/sched.h
-@@ -0,0 +1,47 @@
-+#ifndef _SCHED_H_
-+#define _SCHED_H_
-+
-+/* Offsets from SCHEDx_BASE_ADDR */
-+#define SCHED_CTRL 0x00
-+#define SCHED_SLOT_TIME 0x04
-+#define SCHED_RES 0x08
-+#define SCHED_QUEUE_ALLOC0 0x0c
-+#define SCHED_QUEUE_ALLOC1 0x10
-+#define SCHED_BW 0x14
-+#define SCHED_GUR_DEF_CTR 0x18
-+#define SCHED_AVL_CTR 0x1c
-+#define SCHED_QU0_WGHT 0x20
-+#define SCHED_QU1_WGHT 0x24
-+#define SCHED_QU2_WGHT 0x28
-+#define SCHED_QU3_WGHT 0x2c
-+#define SCHED_QU4_WGHT 0x30
-+#define SCHED_QU5_WGHT 0x34
-+#define SCHED_QU6_WGHT 0x38
-+#define SCHED_QU7_WGHT 0x3c
-+#define SCHED_QUE0_DEFICIT_CNT 0x40
-+#define SCHED_QUE1_DEFICIT_CNT 0x44
-+#define SCHED_QUE2_DEFICIT_CNT 0x48
-+#define SCHED_QUE3_DEFICIT_CNT 0x4c
-+#define SCHED_QUE4_DEFICIT_CNT 0x50
-+#define SCHED_QUE5_DEFICIT_CNT 0x54
-+#define SCHED_QUE6_DEFICIT_CNT 0x58
-+#define SCHED_QUE7_DEFICIT_CNT 0x5c
-+#define SCHED_PKT_LEN 0x60
-+
-+#define SCHED_CTRL_ALGOTYPE(x) (((x) & 0xf) << 0)
-+#define SCHED_CTRL_CALQUOTA(x) (((x) & 0x1) << 4)
-+#define SCHED_CTRL_ACTIVE_Q(x) (((x) & 0xff) << 8)
-+#define SCHED_CTRL_SHARE_BW(x) (((x) & 0xff) << 16)
-+#define SCHED_CTRL_BARROW_BW(x) (((x) & 0xff) << 24)
-+
-+#define SCHED_QUEUE_ALLOC0_QUEUEA(x) (((x) & 0x1f) << 0)
-+#define SCHED_QUEUE_ALLOC0_QUEUEB(x) (((x) & 0x1f) << 8)
-+#define SCHED_QUEUE_ALLOC0_QUEUEC(x) (((x) & 0x1f) << 16)
-+#define SCHED_QUEUE_ALLOC0_QUEUED(x) (((x) & 0x1f) << 24)
-+
-+#define SCHED_QUEUE_ALLOC0_RES0(x) (((x) & 0x7) << 5)
-+#define SCHED_QUEUE_ALLOC0_RES1(x) (((x) & 0x7) << 13)
-+#define SCHED_QUEUE_ALLOC0_RES2(x) (((x) & 0x7) << 21)
-+#define SCHED_QUEUE_ALLOC0_RES3(x) (((x) & 0x7) << 29)
-+
-+#endif /* _SCHED_H_ */
-diff --git a/drivers/net/pfe_eth/pfe/tmu/shaper.h b/drivers/net/pfe_eth/pfe/tmu/shaper.h
-new file mode 100644
-index 0000000..76315f3
---- /dev/null
-+++ b/drivers/net/pfe_eth/pfe/tmu/shaper.h
-@@ -0,0 +1,19 @@
-+#ifndef _SHAPER_H_
-+#define _SHAPER_H_
-+
-+/* Offsets from SHAPPERx_BASE_ADDR */
-+#define SHAPER_CTRL 0x00
-+#define SHAPER_WEIGHT 0x04
-+#define SHAPER_PKT_LEN 0x08
-+
-+#define SHAPER_CTRL_ENABLE(x) (((x) & 0x1) << 0)
-+#define SHAPER_CTRL_QNO(x) (((x) & 0x3f) << 1)
-+#define SHAPER_CTRL_CLKDIV(x) (((x) & 0xffff) << 16)
-+
-+#define SHAPER_WEIGHT_FRACWT(x) (((x) & 0xff) << 0)
-+#define SHAPER_WEIGHT_INTWT(x) (((x) & 0x3) << 8)
-+#define SHAPER_WEIGHT_MAXCREDIT(x) (((x) & 0x3fffff) << 10)
-+
-+#define PORT_SHAPER_MASK (1 << 0)
-+
-+#endif /* _SHAPER_H_ */
-diff --git a/drivers/net/pfe_eth/pfe/uart.h b/drivers/net/pfe_eth/pfe/uart.h
-new file mode 100644
-index 0000000..483d446
---- /dev/null
-+++ b/drivers/net/pfe_eth/pfe/uart.h
-@@ -0,0 +1,13 @@
-+#ifndef _UART_H_
-+#define _UART_H_
-+
-+#define UART_THR (UART_BASE_ADDR + 0x00)
-+#define UART_IER (UART_BASE_ADDR + 0x04)
-+#define UART_IIR (UART_BASE_ADDR + 0x08)
-+#define UART_LCR (UART_BASE_ADDR + 0x0c)
-+#define UART_MCR (UART_BASE_ADDR + 0x10)
-+#define UART_LSR (UART_BASE_ADDR + 0x14)
-+#define UART_MDR (UART_BASE_ADDR + 0x18)
-+#define UART_SCRATCH (UART_BASE_ADDR + 0x1c)
-+
-+#endif /* _UART_H_ */
-diff --git a/drivers/net/pfe_eth/pfe/util.h b/drivers/net/pfe_eth/pfe/util.h
-new file mode 100644
-index 0000000..fb2417c
---- /dev/null
-+++ b/drivers/net/pfe_eth/pfe/util.h
-@@ -0,0 +1,30 @@
-+#ifndef _UTIL_H_
-+#define _UTIL_H_
-+
-+#define UTIL_DMEM_BASE_ADDR 0x00000000
-+#define UTIL_DMEM_SIZE 0x00002000
-+#define UTIL_DMEM_END (UTIL_DMEM_BASE_ADDR + UTIL_DMEM_SIZE)
-+
-+#define IS_DMEM(addr, len) (((unsigned long)(addr) >= UTIL_DMEM_BASE_ADDR) && (((unsigned long)(addr) + (len)) <= UTIL_DMEM_END))
-+
-+#define CBUS_BASE_ADDR 0xc0000000
-+#define UTIL_APB_BASE_ADDR 0xc1000000
-+
-+#include "cbus.h"
-+
-+#define GPT_BASE_ADDR (UTIL_APB_BASE_ADDR + 0x00000)
-+#define UART_BASE_ADDR (UTIL_APB_BASE_ADDR + 0x10000)
-+#define EAPE_BASE_ADDR (UTIL_APB_BASE_ADDR + 0x20000)
-+#define INQ_BASE_ADDR (UTIL_APB_BASE_ADDR + 0x30000)
-+#define EFET1_BASE_ADDR (UTIL_APB_BASE_ADDR + 0x40000)
-+#define EFET2_BASE_ADDR (UTIL_APB_BASE_ADDR + 0x50000)
-+#define EFET3_BASE_ADDR (UTIL_APB_BASE_ADDR + 0x60000)
-+
-+
-+#include "gpt.h"
-+#include "uart.h"
-+#include "util/eape.h"
-+#include "util/inq.h"
-+#include "util/efet.h"
-+
-+#endif /* _UTIL_H_ */
-diff --git a/drivers/net/pfe_eth/pfe/util/eape.h b/drivers/net/pfe_eth/pfe/util/eape.h
-new file mode 100644
-index 0000000..07344dc
---- /dev/null
-+++ b/drivers/net/pfe_eth/pfe/util/eape.h
-@@ -0,0 +1,10 @@
-+#ifndef _EAPE_H_
-+#define _EAPE_H_
-+
-+#define EAPE_STATUS (EAPE_BASE_ADDR + 0x0)
-+#define EAPE_INT_ENABLE (EAPE_BASE_ADDR + 0x4)
-+#define EAPE_INT_SRC (EAPE_BASE_ADDR + 0x8)
-+#define EAPE_HOST_INT_ENABLE (EAPE_BASE_ADDR + 0xc)
-+
-+
-+#endif /* _EAPE_H_ */
-diff --git a/drivers/net/pfe_eth/pfe/util/efet.h b/drivers/net/pfe_eth/pfe/util/efet.h
-new file mode 100644
-index 0000000..12d0310
---- /dev/null
-+++ b/drivers/net/pfe_eth/pfe/util/efet.h
-@@ -0,0 +1,20 @@
-+#ifndef _UTIL_EFET_H_
-+#define _UTIL_EFET_H_
-+
-+#define EFET_ENTRY_ADDR 0x00
-+#define EFET_ENTRY_SIZE 0x04
-+#define EFET_ENTRY_DMEM_ADDR 0x08
-+#define EFET_ENTRY_STATUS 0x0c
-+#define EFET_ENTRY_ENDIAN 0x10
-+
-+#define CBUS2DMEM 0
-+#define DMEM2CBUS 1
-+
-+#define EFET2BUS_LE (1 << 0)
-+
-+void util_efet(int i, u32 cbus_addr, u32 dmem_addr, u32 len, u8 dir);
-+void util_efet_wait(int i);
-+void util_efet_sync(int i, u32 cbus_addr, u32 dmem_addr, u32 len, u8 dir);
-+
-+#endif /* _UTIL_EFET_H_ */
-+
-diff --git a/drivers/net/pfe_eth/pfe/util/inq.h b/drivers/net/pfe_eth/pfe/util/inq.h
-new file mode 100644
-index 0000000..73d1acb
---- /dev/null
-+++ b/drivers/net/pfe_eth/pfe/util/inq.h
-@@ -0,0 +1,10 @@
-+#ifndef _INQ_H_
-+#define _INQ_H_
-+
-+#define INQ_HOST_GP (INQ_BASE_ADDR + 0x00) /* FIXME what are these for ? */
-+#define INQ_UPE_GP (INQ_BASE_ADDR + 0x04) /* FIXME what are these for ? */
-+
-+#define INQ_QB_PKTPTR (INQ_BASE_ADDR + 0x08)
-+#define INQ_FIFO_CNT (INQ_BASE_ADDR + 0x0c)
-+
-+#endif /* _INQ_H_ */
-diff --git a/drivers/net/pfe_eth/pfe_driver.c b/drivers/net/pfe_eth/pfe_driver.c
-new file mode 100644
-index 0000000..ca00e98
---- /dev/null
-+++ b/drivers/net/pfe_eth/pfe_driver.c
-@@ -0,0 +1,710 @@
-+/*
-+ * (C) Copyright 2011
-+ * Author : Mindspeed Technologes
-+ *
-+ * See file CREDITS for list of people who contributed to this
-+ * project.
-+ *
-+ * This program is free software; you can redistribute it and/or
-+ * modify it under the terms of the GNU General Public License as
-+ * published by the Free Software Foundation; either version 2 of
-+ * the License, or (at your option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program; if not, write to the Free Software
-+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-+ * MA 02111-1307 USA
-+ * */
-+
-+
-+#include "hal.h"
-+#include "pfe/pfe.h"
-+#include "pfe_driver.h"
-+#include "pfe_firmware.h"
-+
-+
-+static struct tx_desc_s *g_tx_desc = NULL;
-+static struct rx_desc_s *g_rx_desc = NULL;
-+
-+#define wmb() asm volatile("dsb st" : : : "memory")
-+
-+/** HIF Rx interface function
-+ * Reads the rx descriptor from the current location (rxToRead).
-+ * - If the descriptor has a valid data/pkt, then get the data pointer
-+ * - check for the input rx phy number
-+ * - increments the rx data pointer by pkt_head_room_size
-+ * - decrements the data length by pkt_head_room_size
-+ * - handover the packet to caller.
-+ *
-+ * @param[out] pkt_ptr Pointer to store rx packet pointer
-+ * @param[out] phy_port Pointer to store recv phy port
-+ *
-+ * @return -1 if no packet, else returns length of packet.
-+ */
-+int pfe_recv(unsigned int *pkt_ptr, int *phy_port)
-+{
-+ struct rx_desc_s *rx_desc = g_rx_desc;
-+ struct bufDesc *bd;
-+ int len = -1;
-+ //volatile u32 ctrl;
-+ struct hif_header_s *hif_header;
-+
-+ bd = rx_desc->rxBase + rx_desc->rxToRead;
-+
-+ if (bd->ctrl & BD_CTRL_DESC_EN)
-+ return len; //No pending Rx packet
-+
-+ /* this len include hif_header(8bytes) */
-+ len = bd->ctrl & 0xFFFF;
-+
-+ hif_header = (struct hif_header_s *)DDR_PFE_TO_VIRT(bd->data);
-+
-+
-+ /* Get the recive port info from the packet */
-+ dprint("Pkt recv'd: Pkt ptr(%p), len(%d), gemac_port(%d) status(%08x)\n",
-+ hif_header, len, hif_header->port_no, bd->status);
-+
-+#if 0
-+ {
-+ int i;
-+ unsigned char *p = (unsigned char *)hif_header;
-+ for(i=0; i < len; i++) {
-+ if(!(i % 16))
-+ printf("\n");
-+ printf(" %02x", p[i]);
-+ }
-+ printf("\n");
-+ }
-+#endif
-+
-+ *pkt_ptr = (unsigned int )(hif_header + 1);
-+ *phy_port = hif_header->port_no;
-+ len -= sizeof(struct hif_header_s);
-+#if 0
-+ /* reset bd control field */
-+ ctrl = (MAX_FRAME_SIZE | BD_CTRL_DESC_EN | BD_CTRL_DIR);
-+ bd->ctrl = ctrl;
-+ bd->status = 0;
-+
-+ rx_desc->rxToRead = (rx_desc->rxToRead + 1) & (rx_desc->rxRingSize - 1);
-+
-+ /* Give START_STROBE to BDP to fetch the descriptor __NOW__,
-+ * BDP need not to wait for rx_poll_cycle time to fetch the descriptor,
-+ * In idle state (ie., no rx pkt), BDP will not fetch
-+ * the descriptor even if strobe is given(I think) */
-+ writel((readl(HIF_RX_CTRL) | HIF_CTRL_BDP_CH_START_WSTB), HIF_RX_CTRL);
-+#endif
-+ return len;
-+}
-+
-+void pfe_recv_ack(void)
-+{
-+ struct rx_desc_s *rx_desc = g_rx_desc;
-+ struct bufDesc *bd;
-+ volatile u32 ctrl;
-+
-+ bd = rx_desc->rxBase + rx_desc->rxToRead;
-+
-+ /* reset bd control field */
-+ ctrl = (MAX_FRAME_SIZE | BD_CTRL_DESC_EN | BD_CTRL_DIR);
-+ bd->ctrl = ctrl;
-+ bd->status = 0;
-+
-+ rx_desc->rxToRead = (rx_desc->rxToRead + 1) & (rx_desc->rxRingSize - 1);
-+
-+ /* Give START_STROBE to BDP to fetch the descriptor __NOW__,
-+ * BDP need not to wait for rx_poll_cycle time to fetch the descriptor,
-+ * In idle state (ie., no rx pkt), BDP will not fetch
-+ * the descriptor even if strobe is given(I think) */
-+ writel((readl(HIF_RX_CTRL) | HIF_CTRL_BDP_CH_START_WSTB), HIF_RX_CTRL);
-+ return;
-+}
-+
-+
-+/** HIF Tx interface function
-+ * This function sends a single packet to PFE from HIF interface.
-+ * - No interrupt indication on tx completion.
-+ * - After tx descriptor is updated and TX DMA is enabled.
-+ * - To support both chipit and read c2k environment, data is copied to
-+ * tx buffers. After verification this copied can be avoided.
-+ *
-+ * @param[in] phy_port Phy port number to send out this packet
-+ * @param[in] data Pointer to the data
-+ * @param[in] length Length of the ethernet packet to be transfered.
-+ *
-+ * @return -1 if tx Q is full, else returns the tx location where the pkt is placed.
-+ */
-+int pfe_send(int phy_port, void *data, int length)
-+{
-+ struct tx_desc_s *tx_desc = g_tx_desc;
-+ struct bufDesc *bd;
-+ struct hif_header_s hif_header;
-+ u8 *tx_buf_va;
-+ volatile u32 ctrl_word;
-+
-+ dprint("%s:pkt: %p, len: %d, txBase: %p, txToSend: %d\n", __func__,
-+ data, length, tx_desc->txBase, tx_desc->txToSend);
-+
-+ bd = tx_desc->txBase + tx_desc->txToSend;
-+
-+ /* check queue-full condition */
-+ if (bd->ctrl & BD_CTRL_DESC_EN) {
-+ printf("Tx queue full\n");
-+ return -1;
-+ }
-+
-+ /* PFE checks for min pkt size */
-+ if (length < MIN_PKT_SIZE) {
-+ length = MIN_PKT_SIZE;
-+ }
-+
-+ tx_buf_va = (u8 *)DDR_PFE_TO_VIRT(bd->data);
-+ dprint("%s: tx_buf_va: %p, tx_buf_pa: %08x\n", __func__, tx_buf_va, bd->data);
-+
-+ /* Fill the gemac/phy port number to send this packet out */
-+ memset(&hif_header, 0 , sizeof(struct hif_header_s));
-+ hif_header.port_no = phy_port;
-+
-+ memcpy(tx_buf_va, (u8 *)&hif_header, sizeof(struct hif_header_s));
-+ memcpy(tx_buf_va + sizeof(struct hif_header_s), data, length);
-+ length += sizeof(struct hif_header_s);
-+
-+#if 0
-+ {
-+ int i;
-+ unsigned char *p = (unsigned char *)tx_buf_va;
-+ for(i=0; i < length; i++) {
-+ if (!(i % 16)) printf("\n");
-+ printf("%02x ", p[i]);
-+ }
-+ }
-+#endif
-+
-+ dprint("before0: Tx Done, status: %08x, ctrl: %08x\n", bd->status, bd->ctrl);
-+
-+ /* fill the tx desc */
-+ ctrl_word = (u32)(BD_CTRL_DESC_EN | BD_CTRL_LIFM | (length & 0xFFFF));
-+ bd->ctrl = ctrl_word;
-+ bd->status = 0;
-+
-+ /* NOTE: This code can be removed after verification */
-+#if 1 //SRAM_RETENTION_BUG
-+ ctrl_word = 0;
-+ bd->status = 0xF0;
-+ ctrl_word = bd->ctrl;
-+ //printf("0: contrl word: %08x\n", ctrl_word);
-+#endif
-+ wmb();
-+
-+ /* Indicate Tx DMA to start fetching the Tx Descriptor,
-+ * set START_STOBE */
-+ //writel((readl(HIF_TX_CTRL) | HIF_TX_BDP_CH_START_WSTB), HIF_TX_CTRL);
-+ //writel((readl(HIF_TX_CTRL) | (HIF_TX_DMA_EN | HIF_TX_BDP_CH_START_WSTB)), HIF_TX_CTRL);
-+ writel((HIF_CTRL_DMA_EN | HIF_CTRL_BDP_CH_START_WSTB), HIF_TX_CTRL);
-+
-+ udelay(100);
-+
-+ return tx_desc->txToSend;
-+}
-+
-+/** HIF to check the Tx done
-+ * This function will chceck the tx done indication of the current txToSend locations
-+ * if success, moves the txToSend to next location.
-+ *
-+ * @return -1 if TX ownership bit is not cleared by hw.
-+ else on success (tx done copletion) returns zero.
-+ */
-+int pfe_tx_done(void)
-+{
-+ struct tx_desc_s *tx_desc = g_tx_desc;
-+ struct bufDesc *bd;
-+ volatile u32 ctrl_word;
-+
-+ dprint("%s:txBase: %p, txToSend: %d\n", __func__, tx_desc->txBase, tx_desc->txToSend);
-+
-+ bd = tx_desc->txBase + tx_desc->txToSend;
-+
-+ /* check queue-full condition */
-+ ctrl_word = bd->ctrl;
-+ if (ctrl_word & BD_CTRL_DESC_EN)
-+ return -1;
-+
-+ /* reset the control field */
-+ bd->ctrl = 0;
-+ //bd->data = (u32)NULL;
-+ bd->status = 0;
-+
-+ dprint("Tx Done : status: %08x, ctrl: %08x\n", bd->status, bd->ctrl);
-+
-+ /* increment the txtosend index to next location */
-+ tx_desc->txToSend = (tx_desc->txToSend + 1) & (tx_desc->txRingSize - 1);
-+
-+ dprint("Tx next pkt location: %d\n", tx_desc->txToSend);
-+
-+ return 0;
-+}
-+#if defined CONFIG_LS1024A
-+/** GEMAC initialization
-+ * Initializes the GEMAC registers.
-+ *
-+ * @param[in] gemac_base Pointer to GEMAC reg base
-+ * @param[in] mode GEMAC mode to configure (MII config)
-+ * @param[in] speed GEMAC speed
-+ * @param[in] duplex
-+ */
-+void pfe_gemac_init(void *gemac_base, u32 mode, u32 speed, u32 duplex)
-+{
-+ GEMAC_CFG gemac_cfg = {
-+ .mode = mode,
-+ .speed = speed,
-+ .duplex = duplex,
-+ };
-+
-+ dprint("%s: gemac_base=%p\n", __func__, gemac_base);
-+
-+ gemac_init(gemac_base, &gemac_cfg);
-+
-+ //gemac_set_loop(gemac_base, LB_NONE);
-+ //gemac_disable_copy_all(gemac_base);
-+ //gemac_disable_rx_checksum_offload(gemac_base);
-+
-+ gemac_allow_broadcast(gemac_base);
-+ gemac_disable_unicast(gemac_base); /* unicast hash disabled */
-+ gemac_disable_multicast(gemac_base); /* multicast hash disabled */
-+ gemac_disable_fcs_rx(gemac_base);
-+ gemac_disable_1536_rx(gemac_base);
-+ gemac_enable_pause_rx(gemac_base);
-+ gemac_enable_rx_checksum_offload(gemac_base);
-+}
-+#endif
-+/** Helper function to dump Rx descriptors.
-+ */
-+void hif_rx_desc_dump(void)
-+{
-+ struct bufDesc *bd_va;
-+ int i;
-+ struct rx_desc_s *rx_desc;
-+
-+ if (g_rx_desc == NULL) {
-+ printf("%s: HIF Rx desc no init \n", __func__);
-+ return;
-+ }
-+
-+ rx_desc = g_rx_desc;
-+ bd_va = rx_desc->rxBase;
-+
-+ printf("HIF rx desc: base_va: %p, base_pa: %08x\n", rx_desc->rxBase, rx_desc->rxBase_pa);
-+ for (i=0; i < rx_desc->rxRingSize; i++) {
-+// printf("status: %08x, ctrl: %08x, data: %08x, next: %p\n",
-+// bd_va->status, bd_va->ctrl, bd_va->data, bd_va->next);
-+ bd_va++;
-+ }
-+}
-+
-+/** HIF Rx Desc initialization function.
-+ */
-+static int hif_rx_desc_init(struct pfe *pfe)
-+{
-+ u32 ctrl;
-+ struct bufDesc *bd_va;
-+ struct bufDesc *bd_pa;
-+ struct rx_desc_s *rx_desc;
-+ u32 rx_buf_pa;
-+ int i;
-+
-+ /* sanity check */
-+ if (g_rx_desc) {
-+ printf("%s: HIF Rx desc re-init request\n", __func__);
-+ return 0;
-+ }
-+
-+ rx_desc = (struct rx_desc_s *)malloc(sizeof(struct rx_desc_s));
-+ if (rx_desc == NULL) {
-+ printf("%s:%d:Memory allocation failure\n", __func__, __LINE__);
-+ return -1;
-+ }
-+ memset(rx_desc, 0 , sizeof(struct rx_desc_s));
-+
-+ /* init: Rx ring buffer */
-+ rx_desc->rxRingSize = HIF_RX_DESC_NT;
-+
-+ /* NOTE: must be 64bit aligned */
-+ bd_va = (struct bufDesc *)(pfe->ddr_baseaddr + RX_BD_BASEADDR);
-+ bd_pa = (struct bufDesc *)(pfe->ddr_phys_baseaddr + RX_BD_BASEADDR);
-+
-+ rx_desc->rxBase = bd_va;
-+ rx_desc->rxBase_pa = (unsigned long)bd_pa;
-+
-+ rx_buf_pa = pfe->ddr_phys_baseaddr + HIF_RX_PKT_DDR_BASEADDR;
-+
-+
-+ printf("%s: Rx desc base: %p, base_pa: %08x, desc_count: %d\n",
-+ __func__, rx_desc->rxBase, rx_desc->rxBase_pa, rx_desc->rxRingSize);
-+
-+ memset(bd_va, 0, sizeof(struct bufDesc) * rx_desc->rxRingSize);
-+
-+ ctrl = (MAX_FRAME_SIZE | BD_CTRL_DESC_EN | BD_CTRL_DIR | BD_CTRL_LIFM);
-+ for (i=0; i < rx_desc->rxRingSize; i++) {
-+ bd_va->next = (u32 )(bd_pa + 1);
-+ bd_va->ctrl = ctrl;
-+ bd_va->data = rx_buf_pa + (i * MAX_FRAME_SIZE);
-+// printf("status: %08x, ctrl: %08x, data: %08x, next: %p\n",
-+// bd_va->status, bd_va->ctrl, bd_va->data, bd_va->next);
-+ bd_va++;
-+ bd_pa++;
-+ }
-+ --bd_va;
-+ bd_va->next = (u32 )rx_desc->rxBase_pa;
-+
-+ /* !!! This is a redundent information for h/w as we are also
-+ maintaining next address in the buffer descriptor
-+ Posedge: reference code does not using this bit to go back to base address */
-+ //bd->ctrl |= BD_CTRL_LAST_BD;
-+
-+ writel(rx_desc->rxBase_pa, HIF_RX_BDP_ADDR);
-+ writel((readl(HIF_RX_CTRL) | HIF_CTRL_BDP_CH_START_WSTB), HIF_RX_CTRL);
-+
-+ g_rx_desc = rx_desc;
-+
-+ return 0;
-+}
-+
-+/** Helper function to dump Tx Descriptors.
-+ */
-+void hif_tx_desc_dump(void)
-+{
-+ struct tx_desc_s *tx_desc;
-+ int i;
-+ struct bufDesc *bd_va;
-+
-+ if (g_tx_desc == NULL) {
-+ printf("%s: HIF Tx desc no init \n", __func__);
-+ return;
-+ }
-+
-+ tx_desc = g_tx_desc;
-+ bd_va = tx_desc->txBase;
-+
-+ printf("HIF tx desc: base_va: %p, base_pa: %08x\n", tx_desc->txBase, tx_desc->txBase_pa);
-+ for (i=0; i < tx_desc->txRingSize; i++) {
-+// printf("status: %08x, ctrl: %08x, data: %08x, next: %p\n",
-+// bd_va->status, bd_va->ctrl, bd_va->data, bd_va->next);
-+ bd_va++;
-+ }
-+}
-+
-+/** HIF Tx descriptor initialization function.
-+ */
-+static int hif_tx_desc_init(struct pfe *pfe)
-+{
-+ struct bufDesc *bd_va;
-+ struct bufDesc *bd_pa;
-+ int i;
-+ struct tx_desc_s *tx_desc;
-+ u32 tx_buf_pa;
-+
-+ /* sanity check */
-+ if (g_tx_desc) {
-+ printf("%s: HIF Tx desc re-init request\n", __func__);
-+ return 0;
-+ }
-+
-+ tx_desc = (struct tx_desc_s *)malloc(sizeof(struct tx_desc_s));
-+ if (tx_desc == NULL) {
-+ printf("%s:%d:Memory allocation failure\n", __func__, __LINE__);
-+ return -1;
-+ }
-+ memset(tx_desc, 0 , sizeof(struct tx_desc_s));
-+
-+ /* init: Tx ring buffer */
-+ tx_desc->txRingSize = HIF_TX_DESC_NT;
-+ /* NOTE: must be 64bit aligned */
-+ bd_va = (struct bufDesc *)(pfe->ddr_baseaddr + TX_BD_BASEADDR);
-+ bd_pa = (struct bufDesc *)(pfe->ddr_phys_baseaddr + TX_BD_BASEADDR);
-+
-+ tx_desc->txBase_pa = (unsigned long)bd_pa;
-+ tx_desc->txBase = bd_va;
-+
-+ printf("%s: Tx desc_base: %p, base_pa: %08x, desc_count: %d\n",
-+ __func__, tx_desc->txBase, tx_desc->txBase_pa, tx_desc->txRingSize);
-+
-+ memset(bd_va, 0, sizeof(struct bufDesc) * tx_desc->txRingSize);
-+
-+ tx_buf_pa = pfe->ddr_phys_baseaddr + HIF_TX_PKT_DDR_BASEADDR;
-+
-+ for (i=0; i < tx_desc->txRingSize; i++) {
-+ bd_va->next = (u32 )(bd_pa + 1);
-+ bd_va->data = tx_buf_pa + (i * MAX_FRAME_SIZE);
-+// printf("status: %08x, ctrl: %08x, data: %08x, next: %p\n",
-+// bd_va->status, bd_va->ctrl, bd_va->data, bd_va->next);
-+ bd_va++;
-+ bd_pa++;
-+ }
-+ --bd_va;
-+ bd_va->next = (u32 )tx_desc->txBase_pa;
-+// printf("status: %08x, ctrl: %08x, data: %08x, next: %p\n",
-+// bd_va->status, bd_va->ctrl, bd_va->data, bd_va->next);
-+
-+ /* !!! This is a redundent information for h/w as we are also
-+ maintaining next address in the buffer descriptor,
-+ Posedge: reference code does not using LAST_BD for moving back to base address */
-+ //bd->ctrl |= BD_CTRL_LAST_BD;
-+
-+ writel(tx_desc->txBase_pa, HIF_TX_BDP_ADDR);
-+
-+ g_tx_desc = tx_desc;
-+
-+ return 0;
-+}
-+
-+/** PFE/Class initialization.
-+ */
-+static void pfe_class_init(struct pfe *pfe)
-+{
-+ CLASS_CFG class_cfg = {
-+ .route_table_baseaddr = pfe->ddr_phys_baseaddr + ROUTE_TABLE_BASEADDR,
-+ .route_table_hash_bits = ROUTE_TABLE_HASH_BITS,
-+ };
-+
-+ class_init(&class_cfg);
-+ printf("class init complete\n");
-+}
-+
-+/** PFE/TMU initialization.
-+ */
-+static void pfe_tmu_init(struct pfe *pfe)
-+{
-+ TMU_CFG tmu_cfg = {
-+ .llm_base_addr = pfe->ddr_phys_baseaddr + TMU_LLM_BASEADDR,
-+ .llm_queue_len = TMU_LLM_QUEUE_LEN,
-+ };
-+
-+ tmu_init(&tmu_cfg);
-+ printf("tmu init complete\n");
-+}
-+
-+/** PFE/BMU (both BMU1 & BMU2) initialization.
-+ */
-+static void pfe_bmu_init(struct pfe *pfe)
-+{
-+ BMU_CFG bmu1_cfg = {
-+ .baseaddr = CBUS_VIRT_TO_PFE(LMEM_BASE_ADDR + BMU1_LMEM_BASEADDR),
-+ .count = BMU1_BUF_COUNT,
-+ .size = BMU1_BUF_SIZE,
-+ };
-+
-+ BMU_CFG bmu2_cfg = {
-+ .baseaddr = pfe->ddr_phys_baseaddr + BMU2_DDR_BASEADDR,
-+ .count = BMU2_BUF_COUNT,
-+ .size = BMU2_BUF_SIZE,
-+ };
-+
-+ bmu_init(BMU1_BASE_ADDR, &bmu1_cfg);
-+ printf("bmu1 init: done\n");
-+
-+ bmu_init(BMU2_BASE_ADDR, &bmu2_cfg);
-+ printf("bmu2 init: done\n");
-+}
-+
-+#if !defined(CONFIG_UTIL_PE_DISABLED)
-+/** PFE/Util initialization function.
-+ */
-+static void pfe_util_init(struct pfe *pfe)
-+{
-+ UTIL_CFG util_cfg = { };
-+
-+ util_init(&util_cfg);
-+ printf("util init complete\n");
-+}
-+#endif
-+
-+/** PFE/GPI initialization function.
-+ * - egpi1, egpi2, egpi3, hgpi
-+ */
-+static void pfe_gpi_init(struct pfe *pfe)
-+{
-+ GPI_CFG egpi1_cfg = {
-+ .lmem_rtry_cnt = EGPI1_LMEM_RTRY_CNT,
-+ .tmlf_txthres = EGPI1_TMLF_TXTHRES,
-+ .aseq_len = EGPI1_ASEQ_LEN,
-+ };
-+
-+ GPI_CFG egpi2_cfg = {
-+ .lmem_rtry_cnt = EGPI2_LMEM_RTRY_CNT,
-+ .tmlf_txthres = EGPI2_TMLF_TXTHRES,
-+ .aseq_len = EGPI2_ASEQ_LEN,
-+ };
-+
-+#if 0
-+ GPI_CFG egpi3_cfg = {
-+ .lmem_rtry_cnt = EGPI3_LMEM_RTRY_CNT,
-+ .tmlf_txthres = EGPI3_TMLF_TXTHRES,
-+ .aseq_len = EGPI3_ASEQ_LEN,
-+ };
-+#endif
-+
-+ GPI_CFG hgpi_cfg = {
-+ .lmem_rtry_cnt = HGPI_LMEM_RTRY_CNT,
-+ .tmlf_txthres = HGPI_TMLF_TXTHRES,
-+ .aseq_len = HGPI_ASEQ_LEN,
-+ };
-+
-+ gpi_init(EGPI1_BASE_ADDR, &egpi1_cfg);
-+ printf("GPI1 init complete\n");
-+
-+ gpi_init(EGPI2_BASE_ADDR, &egpi2_cfg);
-+ printf("GPI2 init complete\n");
-+
-+#if 0
-+ gpi_init(EGPI3_BASE_ADDR, &egpi3_cfg);
-+#endif
-+
-+ gpi_init(HGPI_BASE_ADDR, &hgpi_cfg);
-+ printf("HGPI init complete\n");
-+}
-+
-+
-+/** PFE/HIF initialization function.
-+ */
-+static void pfe_hif_init(struct pfe *pfe)
-+{
-+ hif_tx_disable();
-+ hif_rx_disable();
-+
-+ hif_tx_desc_init(pfe);
-+ hif_rx_desc_init(pfe);
-+
-+ hif_init();
-+
-+ hif_tx_enable();
-+ hif_rx_enable();
-+
-+ hif_rx_desc_dump();
-+ hif_tx_desc_dump();
-+
-+ printf("HIF init complete\n");
-+}
-+
-+/** PFE initialization
-+ * - Firmware loading (CLASS-PE and TMU-PE)
-+ * - BMU1 and BMU2 init
-+ * - GEMAC init
-+ * - GPI init
-+ * - CLASS-PE init
-+ * - TMU-PE init
-+ * - HIF tx and rx descriptors init
-+ *
-+ * @param[in] edev Pointer to eth device structure.
-+ *
-+ * @return 0, on success.
-+ */
-+static int pfe_hw_init(struct pfe *pfe)
-+{
-+
-+ dprint("%s: start \n", __func__);
-+#if defined (CONFIG_LS1012A)
-+ /*This clock workaround needed for LS1012 */
-+ writel(0x3, CLASS_PE_SYS_CLK_RATIO);
-+ writel(0x3, TMU_PE_SYS_CLK_RATIO);
-+ writel(0x3, UTIL_PE_SYS_CLK_RATIO);
-+ udelay(10);
-+#endif
-+
-+ pfe_class_init(pfe);
-+
-+ pfe_tmu_init(pfe);
-+
-+ pfe_bmu_init(pfe);
-+
-+#if !defined(CONFIG_UTIL_PE_DISABLED)
-+ pfe_util_init(pfe);
-+#endif
-+
-+ pfe_gpi_init(pfe);
-+
-+ pfe_hif_init(pfe);
-+
-+ bmu_enable(BMU1_BASE_ADDR);
-+ printf("bmu1 enabled\n");
-+
-+ bmu_enable(BMU2_BASE_ADDR);
-+ printf("bmu2 enabled\n");
-+
-+ printf("%s: done\n", __func__);
-+
-+ /* NOTE: Load PE specific data (if any) */
-+
-+ return 0;
-+}
-+
-+
-+/** PFE probe function.
-+ * - Initializes pfe_lib
-+ * - pfe hw init
-+ * - fw loading and enables PEs
-+ * - should be executed once.
-+ *
-+ * @param[in] pfe Pointer the pfe control block
-+ */
-+int pfe_probe(struct pfe *pfe)
-+{
-+ static int init_done = 0;
-+
-+ if (init_done)
-+ return 0;
-+
-+ printf("cbus_baseaddr: %p, ddr_baseaddr: %p, ddr_phys_baseaddr: %08x\n",
-+ pfe->cbus_baseaddr, pfe->ddr_baseaddr, (u32)pfe->ddr_phys_baseaddr);
-+
-+ pfe_lib_init(pfe->cbus_baseaddr, pfe->ddr_baseaddr, pfe->ddr_phys_baseaddr);
-+
-+
-+ pfe_hw_init(pfe);
-+
-+ /* Load the class,TM, Util fw
-+ * by now pfe is,
-+ * - out of reset + disabled + configured,
-+ * Fw loading should be done after pfe_hw_init() */
-+#ifdef CONFIG_CMD_PFE_START
-+ /* It loads firmware from DDR locations Class at 0x100000 TMU at 0x180000 UTIL at 200000*/
-+ //For this firmware should be preloaded in DDR
-+ //pfe_firmware_init((u8 *)0x80100000, (u8 *)0x80180000, 0x80200000);
-+ pfe_firmware_init(NULL, NULL, NULL);
-+#else
-+ /*It loads default inbuilt sbl firmware */
-+ pfe_firmware_init(NULL, NULL, NULL);
-+#endif
-+
-+ init_done = 1;
-+
-+ return 0;
-+}
-+
-+
-+/** PFE remove function
-+ * - stopes PEs
-+ * - frees tx/rx descriptor resources
-+ * - should be called once.
-+ *
-+ * @param[in] pfe Pointer to pfe control block.
-+ */
-+int pfe_remove(struct pfe *pfe)
-+{
-+ if (g_tx_desc) {
-+ free(g_tx_desc);
-+ }
-+
-+ if (g_rx_desc) {
-+ free(g_rx_desc);
-+ }
-+
-+ pfe_firmware_exit();
-+
-+ return 0;
-+}
-+
-diff --git a/drivers/net/pfe_eth/pfe_driver.h b/drivers/net/pfe_eth/pfe_driver.h
-new file mode 100644
-index 0000000..4d2e8b6
---- /dev/null
-+++ b/drivers/net/pfe_eth/pfe_driver.h
-@@ -0,0 +1,141 @@
-+/*
-+ * (C) Copyright 2011
-+ * Author : Mindspeed Technologes
-+ *
-+ * See file CREDITS for list of people who contributed to this
-+ * project.
-+ *
-+ * This program is free software; you can redistribute it and/or
-+ * modify it under the terms of the GNU General Public License as
-+ * published by the Free Software Foundation; either version 2 of
-+ * the License, or (at your option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program; if not, write to the Free Software
-+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-+ * MA 02111-1307 USA
-+ * */
-+
-+#ifndef __PFE_DRIVER_H__
-+#define __PFE_DRIVER_H__
-+
-+#include "hal.h"
-+
-+#include "pfe/pfe.h"
-+#include "pfe/cbus.h"
-+#include "pfe/cbus/bmu.h"
-+
-+
-+
-+typedef struct bufDesc {
-+ volatile u32 ctrl;
-+ volatile u32 status;
-+ volatile u32 data;
-+ volatile u32 next;
-+ // struct bufDesc *next;
-+}__attribute__((packed)) bufDesc_t;
-+
-+#if defined(CONFIG_PLATFORM_PCI)
-+#define HIF_RX_DESC_NT 4
-+#define HIF_TX_DESC_NT 4
-+#else
-+#define HIF_RX_DESC_NT 64
-+#define HIF_TX_DESC_NT 64
-+#endif
-+#define RX_BD_BASEADDR (HIF_DESC_BASEADDR)
-+#define TX_BD_BASEADDR (HIF_DESC_BASEADDR + HIF_TX_DESC_SIZE)
-+
-+#define MIN_PKT_SIZE 56
-+#define MAX_FRAME_SIZE 2048
-+
-+
-+typedef struct hif_header_s {
-+ u8 port_no; //Carries input port no for host rx packets and output port no for tx pkts
-+ u8 reserved0;
-+ u32 reserved2;
-+} __attribute__((packed)) hif_header_t;
-+
-+
-+typedef struct rx_desc_s {
-+ struct bufDesc *rxBase;
-+ unsigned int rxBase_pa;
-+ int rxToRead;
-+ int rxRingSize;
-+}rx_desc_t;
-+
-+typedef struct tx_desc_s {
-+ struct bufDesc *txBase;
-+ unsigned int txBase_pa;
-+ int txToSend;
-+ int txRingSize;
-+}tx_desc_t;
-+
-+
-+/* The set of statistics registers implemented in the Cadence MAC.
-+ * The statistics registers implemented are a subset of all the statistics
-+ * available, but contains all the compulsory ones.
-+ */
-+typedef struct gem_stats{
-+ u32 octets_tx_bot; /* Lower 32-bits for number of octets tx'd */
-+ u32 octets_tx_top; /* Upper 16-bits for number of octets tx'd */
-+ u32 frames_tx; /* Number of frames transmitted OK */
-+ u32 broadcast_tx; /* Number of broadcast frames transmitted */
-+ u32 multicast_tx; /* Number of multicast frames transmitted */
-+ u32 pause_tx; /* Number of pause frames transmitted. */
-+ u32 frame64_tx; /* Number of 64byte frames transmitted */
-+ u32 frame65_127_tx; /* Number of 65-127 byte frames transmitted */
-+ u32 frame128_255_tx; /* Number of 128-255 byte frames transmitted */
-+ u32 frame256_511_tx; /* Number of 256-511 byte frames transmitted */
-+ u32 frame512_1023_tx; /* Number of 512-1023 byte frames transmitted */
-+ u32 frame1024_1518_tx; /* Number of 1024-1518 byte frames transmitted*/
-+ u32 frame1519_tx; /* Number of frames greater than 1518 bytes tx*/
-+ u32 tx_urun; /* Transmit underrun errors due to DMA */
-+ u32 single_col; /* Number of single collision frames */
-+ u32 multi_col; /* Number of multi collision frames */
-+ u32 excess_col; /* Number of excessive collision frames. */
-+ u32 late_col; /* Collisions occuring after slot time */
-+ u32 def_tx; /* Frames deferred due to crs */
-+ u32 crs_errors; /* Errors caused by crs not being asserted. */
-+ u32 octets_rx_bot; /* Lower 32-bits for number of octets rx'd */
-+ u32 octets_rx_top; /* Upper 16-bits for number of octets rx'd */
-+ u32 frames_rx; /* Number of frames received OK */
-+ u32 broadcast_rx; /* Number of broadcast frames received */
-+ u32 multicast_rx; /* Number of multicast frames received */
-+ u32 pause_rx; /* Number of pause frames received. */
-+ u32 frame64_rx; /* Number of 64byte frames received */
-+ u32 frame65_127_rx; /* Number of 65-127 byte frames received */
-+ u32 frame128_255_rx; /* Number of 128-255 byte frames received */
-+ u32 frame256_511_rx; /* Number of 256-511 byte frames received */
-+ u32 frame512_1023_rx; /* Number of 512-1023 byte frames received */
-+ u32 frame1024_1518_rx; /* Number of 1024-1518 byte frames received*/
-+ u32 frame1519_rx; /* Number of frames greater than 1518 bytes rx*/
-+ u32 usize_frames; /* Frames received less than min of 64 bytes */
-+ u32 excess_length; /* Number of excessive length frames rx */
-+ u32 jabbers; /* Excessive length + crc or align errors. */
-+ u32 fcs_errors; /* Number of frames received with crc errors */
-+ u32 length_check_errors;/* Number of frames with incorrect length */
-+ u32 rx_symbol_errors; /* Number of times rx_er asserted during rx */
-+ u32 align_errors; /* Frames received without integer no. bytes */
-+ u32 rx_res_errors; /* Number of times buffers ran out during rx */
-+ u32 rx_orun; /* Receive overrun errors due to DMA */
-+ u32 ip_cksum; /* IP header checksum errors */
-+ u32 tcp_cksum; /* TCP checksum errors */
-+ u32 udp_cksum; /* UDP checksum errors */
-+} volatile GEM_STATS;
-+
-+
-+int pfe_send(int phy_port, void *data, int length);
-+int pfe_recv(unsigned int *pkt_ptr, int *phy_port);
-+void pfe_recv_ack(void);
-+int pfe_tx_done(void);
-+void pfe_gem_enable_all(void);
-+void pfe_gemac_init(void *gemac_base, u32 mode, u32 speed, u32 duplex);
-+
-+
-+#endif
-+
-diff --git a/drivers/net/pfe_eth/pfe_eth.c b/drivers/net/pfe_eth/pfe_eth.c
-new file mode 100644
-index 0000000..40ac095
---- /dev/null
-+++ b/drivers/net/pfe_eth/pfe_eth.c
-@@ -0,0 +1,521 @@
-+#include <common.h>
-+#include <config.h>
-+//#include <asm/arch/hardware.h>
-+#include <asm/byteorder.h>
-+#include <net.h>
-+#include <command.h>
-+#include <miiphy.h>
-+#include "pfe_eth.h"
-+
-+struct gemac_s gem_info[] = {
-+ /* PORT_0 configuration */
-+ {
-+ /* GEMAC config */
-+ .gemac_mode = GMII,
-+ .gemac_speed = SPEED_1000M,
-+ .gemac_duplex = DUPLEX_FULL,
-+
-+ /* phy iface */
-+ .phy_address = EMAC1_PHY_ADDR,
-+ .phy_mode = PHY_INTERFACE_MODE_SGMII,
-+ },
-+ /* PORT_1 configuration */
-+ {
-+ /* GEMAC config */
-+ .gemac_mode = GMII,
-+ .gemac_speed = SPEED_1000M,
-+ .gemac_duplex = DUPLEX_FULL,
-+
-+ /* phy iface */
-+ .phy_address = EMAC2_PHY_ADDR,
-+ .phy_mode = PHY_INTERFACE_MODE_RGMII,
-+ },
-+};
-+
-+#define MAX_GEMACS 2
-+
-+static struct ls1012a_eth_dev *gemac_list[MAX_GEMACS];
-+
-+/* Max MII register/address (we support) */
-+#define MII_REGISTER_MAX 31
-+#define MII_ADDRESS_MAX 31
-+
-+#define MDIO_TIMEOUT 5000
-+
-+
-+static void ls1012a_gemac_enable(void *gemac_base)
-+{
-+ writel(readl(gemac_base + EMAC_ECNTRL_REG) | EMAC_ECNTRL_ETHER_EN, gemac_base + EMAC_ECNTRL_REG);
-+}
-+
-+static void ls1012a_gemac_dsable(void *gemac_base)
-+{
-+ writel(readl(gemac_base + EMAC_ECNTRL_REG) & ~EMAC_ECNTRL_ETHER_EN, gemac_base + EMAC_ECNTRL_REG);
-+}
-+
-+static void ls1012a_gemac_set_mode(void *gemac_base, u32 mode)
-+{
-+}
-+
-+static void ls1012a_gemac_set_speed(void *gemac_base, u32 speed)
-+{
-+ struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
-+ u32 ecr = readl(gemac_base + EMAC_ECNTRL_REG) & ~EMAC_ECNTRL_SPEED;
-+ u32 rcr = readl(gemac_base + EMAC_RCNTRL_REG) & ~EMAC_RCNTRL_RMII_10T;
-+ u32 rgmii_pcr = in_be32(&scfg->rgmiipcr) & ~(SCFG_RGMIIPCR_SETSP_1000M|SCFG_RGMIIPCR_SETSP_10M);
-+
-+ if (speed == _1000BASET) {
-+ ecr |= EMAC_ECNTRL_SPEED;
-+ rgmii_pcr |= SCFG_RGMIIPCR_SETSP_1000M;
-+ }
-+ else if (speed != _100BASET){
-+ rcr |= EMAC_RCNTRL_RMII_10T;
-+ rgmii_pcr |= SCFG_RGMIIPCR_SETSP_10M;
-+ }
-+
-+ writel(ecr, gemac_base + EMAC_ECNTRL_REG);
-+ out_be32(&scfg->rgmiipcr, rgmii_pcr | SCFG_RGMIIPCR_SETFD);
-+
-+ /* remove loop back */
-+ rcr &= ~EMAC_RCNTRL_LOOP;
-+ /* enable flow control */
-+ rcr |= EMAC_RCNTRL_FCE;
-+
-+ /* Enable MII mode */
-+ rcr |= EMAC_RCNTRL_MII_MODE;
-+
-+ /* CRC field is stripped from the frame */
-+ //rcr |= EMAC_RCNTRL_CRC_FWD;
-+
-+ /* Enable promiscuous mode
-+ FIXME should be removed later*/
-+ //rcr |= EMAC_RCNTRL_PROM;
-+ writel(rcr, gemac_base + EMAC_RCNTRL_REG);
-+
-+ /*Enable Tx full duplex */
-+ writel(readl(gemac_base + EMAC_TCNTRL_REG ) | EMAC_TCNTRL_FDEN, gemac_base + EMAC_TCNTRL_REG);
-+
-+}
-+
-+static void ls1012a_gemac_set_ethaddr(void *gemac_base, uchar *mac)
-+{
-+ writel((mac[0] << 24) + (mac[1] << 16) + (mac[2] << 8) + mac[3], gemac_base + EMAC_PHY_ADDR_LOW);
-+ writel((mac[4] << 24) + (mac[5] << 16) + 0x8808, gemac_base + EMAC_PHY_ADDR_HIGH);
-+}
-+
-+/** Stops or Disables GEMAC pointing to this eth iface.
-+ *
-+ * @param[in] edev Pointer to eth device structure.
-+ *
-+ * @return none
-+ */
-+static void ls1012a_eth_halt(struct eth_device *edev)
-+{
-+ struct ls1012a_eth_dev *priv = (struct ls1012a_eth_dev *)edev->priv;
-+
-+ ls1012a_gemac_enable(priv->gem->gemac_base);
-+
-+ gpi_disable(priv->gem->egpi_base);
-+
-+ return;
-+}
-+
-+static int ls1012a_eth_init(struct eth_device *dev, bd_t * bd)
-+{
-+ struct ls1012a_eth_dev *priv = (struct ls1012a_eth_dev *)dev->priv;
-+ struct gemac_s *gem = priv->gem;
-+ int speed;
-+ int tmp;
-+
-+ /* set ethernet mac address */
-+ ls1012a_gemac_set_ethaddr(gem->gemac_base, dev->enetaddr);
-+
-+ //MAC will be always in GMII mode, it doesn't change with the link speed.
-+ //ls1012a_gemac_set_mode(gem->gemac_base, gem->gemac_mode);
-+
-+ writel(0x00000004, gem->gemac_base + EMAC_TFWR_STR_FWD);
-+ writel(0x00000005, gem->gemac_base + EMAC_RX_SECTIOM_FULL);
-+ writel(0x00003fff, gem->gemac_base + EMAC_TRUNC_FL);
-+ writel(0x00000030, gem->gemac_base + EMAC_TX_SECTION_EMPTY);
-+ writel(0x00000000, gem->gemac_base + EMAC_MIB_CTRL_STS_REG);
-+
-+#ifndef CONFIG_EMU
-+#ifdef CONFIG_PHYLIB
-+ /* Start up the PHY */
-+ //if(gem->phy_mode != PHY_INTERFACE_MODE_SGMII) {
-+ if (phy_startup(priv->phydev)) {
-+ printf("Could not initialize PHY %s\n",
-+ priv->phydev->dev->name);
-+ return -1;
-+ }
-+ speed = priv->phydev->speed;
-+ printf("Speed detected %x\n", speed);
-+ if(priv->phydev->duplex == DUPLEX_HALF) {
-+ printf("Half duplex not supported \n");
-+ return -1;
-+ }
-+#endif
-+#else
-+ /*in emulator it is always 1000Mbps */
-+ speed = _1000BASET;
-+#endif
-+ ls1012a_gemac_set_speed(gem->gemac_base, speed);
-+
-+ /* Enable GPI */
-+ gpi_enable(gem->egpi_base);
-+
-+ /* Enable GEMAC */
-+ ls1012a_gemac_enable(gem->gemac_base);
-+
-+ return 0;
-+
-+}
-+
-+static int ls1012a_eth_send(struct eth_device *dev, void *data, int length)
-+{
-+ struct ls1012a_eth_dev *priv = (struct ls1012a_eth_dev *)dev->priv;
-+
-+ int rc;
-+ int i=0;
-+
-+ rc = pfe_send(priv->gemac_port, data, length);
-+
-+ if (rc < 0) {
-+ printf("Tx Q full\n");
-+ return 0;
-+ }
-+
-+ while (1) {
-+ rc = pfe_tx_done();
-+ if (rc == 0)
-+ break;
-+
-+ udelay(100);
-+ i++;
-+ if(i == 30000)
-+ printf("Tx timeout, send failed\n");
-+ break;
-+
-+ }
-+
-+ return 0;
-+}
-+
-+static int ls1012a_eth_recv(struct eth_device *dev)
-+{
-+ struct ls1012a_eth_dev *priv = (struct ls1012a_eth_dev *)dev->priv;
-+ u32 pkt_buf;
-+ int len;
-+ int phy_port;
-+
-+ len = pfe_recv(&pkt_buf, &phy_port);
-+
-+ if (len < 0)
-+ return 0; //no packet in rx
-+
-+ dprint("Rx pkt: pkt_buf(%08x), phy_port(%d), len(%d)\n", pkt_buf, phy_port, len);
-+ if (phy_port != priv->gemac_port) {
-+ printf("Rx pkt not on expected port\n");
-+ pfe_recv_ack();
-+ return 0;
-+ }
-+
-+ // Pass the packet up to the protocol layers.
-+ net_process_received_packet((uchar *)pkt_buf, len);
-+
-+ pfe_recv_ack();
-+ return 0;
-+}
-+
-+#if defined(CONFIG_PHYLIB)
-+
-+#define MDIO_TIMEOUT 5000
-+static int ls1012a_phy_read(struct mii_dev *bus, int phy_addr, int dev_addr, int reg_addr)
-+{
-+ void *reg_base = bus->priv;
-+ u32 reg;
-+ u32 phy;
-+ u32 reg_data;
-+ u16 val;
-+ int timeout = MDIO_TIMEOUT;
-+
-+ reg = ((reg_addr & EMAC_MII_DATA_RA_MASK) << EMAC_MII_DATA_RA_SHIFT);
-+ phy = ((phy_addr & EMAC_MII_DATA_PA_MASK) << EMAC_MII_DATA_PA_SHIFT);
-+
-+ reg_data = (EMAC_MII_DATA_ST | EMAC_MII_DATA_OP_RD | EMAC_MII_DATA_TA | phy | reg );
-+
-+ //dprint("%s write data %x %x %x\n", __func__, reg_data, reg_addr, phy_addr);
-+ writel(reg_data, reg_base + EMAC_MII_DATA_REG);
-+
-+ /*
-+ * wait for the MII interrupt
-+ */
-+ while(!(readl(reg_base + EMAC_IEVENT_REG) & EMAC_IEVENT_MII))
-+ {
-+ if (timeout-- <= 0) {
-+ printf("Phy MDIO read/write timeout\n");
-+ return -1;
-+ }
-+ }
-+
-+ /*
-+ * clear MII interrupt
-+ */
-+ writel(EMAC_IEVENT_MII, reg_base + EMAC_IEVENT_REG);
-+
-+ /*
-+ * it's now safe to read the PHY's register
-+ */
-+ val = (u16)readl(reg_base + EMAC_MII_DATA_REG);
-+ dprint("%s: %x phy: %02x reg:%02x val:%#x\n", __func__, reg_base, phy_addr, reg_addr, val);
-+
-+ return val;
-+}
-+
-+static int ls1012a_phy_write(struct mii_dev *bus, int phy_addr, int dev_addr, int reg_addr, u16 data)
-+{
-+ void *reg_base = bus->priv;
-+ u32 reg;
-+ u32 phy;
-+ u32 reg_data;
-+ int timeout = MDIO_TIMEOUT;
-+ int val;
-+
-+ reg = ((reg_addr & EMAC_MII_DATA_RA_MASK) << EMAC_MII_DATA_RA_SHIFT);
-+ phy = ((phy_addr & EMAC_MII_DATA_PA_MASK) << EMAC_MII_DATA_PA_SHIFT);
-+
-+ reg_data = (EMAC_MII_DATA_ST | EMAC_MII_DATA_OP_WR | EMAC_MII_DATA_TA | phy | reg | data);
-+
-+ //dprint("%s write data %x\n", __func__, reg_data);
-+ writel(reg_data, reg_base + EMAC_MII_DATA_REG);
-+
-+ /*
-+ * wait for the MII interrupt
-+ */
-+ while(!(readl(reg_base + EMAC_IEVENT_REG) & EMAC_IEVENT_MII))
-+ {
-+ if (timeout-- <= 0) {
-+ printf("Phy MDIO read/write timeout\n");
-+ return -1;
-+ }
-+ }
-+
-+ /*
-+ * clear MII interrupt
-+ */
-+ writel(EMAC_IEVENT_MII, reg_base + EMAC_IEVENT_REG);
-+
-+ dprint("%s: phy: %02x reg:%02x val:%#x\n", __func__, phy_addr, reg_addr, data);
-+
-+ return val;
-+}
-+
-+
-+struct mii_dev *ls1012a_mdio_init(struct mdio_info *mdio_info)
-+{
-+ struct mii_dev *bus;
-+ int ret;
-+ u32 mdio_speed;
-+ u32 pclk = 250000000;
-+
-+ bus = mdio_alloc();
-+ if (!bus) {
-+ printf("mdio_alloc failed\n");
-+ return NULL;
-+ }
-+ bus->read = ls1012a_phy_read;
-+ bus->write = ls1012a_phy_write;
-+ /* MAC1 MDIO used to communicate with external PHYS */
-+ bus->priv = mdio_info->reg_base;
-+ sprintf(bus->name, mdio_info->name);
-+
-+ /*configure mdio speed */
-+ mdio_speed = (DIV_ROUND_UP(pclk, 4000000) << EMAC_MII_SPEED_SHIFT);
-+ mdio_speed |= EMAC_HOLDTIME(0x4);
-+ writel(mdio_speed, mdio_info->reg_base + EMAC_MII_CTRL_REG);
-+
-+ ret = mdio_register(bus);
-+ if (ret) {
-+ printf("mdio_register failed\n");
-+ free(bus);
-+ return NULL;
-+ }
-+ return bus;
-+}
-+
-+static void ls1012a_configure_serdes(struct ls1012a_eth_dev *priv)
-+{
-+ struct mii_dev bus;
-+ int value,sgmii_2500=0;
-+
-+ printf("%s %d\n", __func__, priv->gemac_port);
-+ /* PCS configuration done with corresponding GEMAC */
-+ bus.priv = priv->gem->gemac_base;
-+
-+ ls1012a_phy_read(&bus, 0, MDIO_DEVAD_NONE, 0x0);
-+ ls1012a_phy_read(&bus, 0, MDIO_DEVAD_NONE, 0x1);
-+ ls1012a_phy_read(&bus, 0, MDIO_DEVAD_NONE, 0x2);
-+ ls1012a_phy_read(&bus, 0, MDIO_DEVAD_NONE, 0x3);
-+#if 0
-+ /*These settings taken from validtion team */
-+ ls1012a_phy_write(&bus, 0, MDIO_DEVAD_NONE, 0x0, 0x8000);
-+ ls1012a_phy_write(&bus, 0, MDIO_DEVAD_NONE, 0x14, 0xb); //3 in case our code
-+ ls1012a_phy_write(&bus, 0, MDIO_DEVAD_NONE, 0x4, 0x1a1);
-+ ls1012a_phy_write(&bus, 0, MDIO_DEVAD_NONE, 0x12, 0x400);
-+ ls1012a_phy_write(&bus, 0, MDIO_DEVAD_NONE, 0x13, 0x0);
-+ ls1012a_phy_write(&bus, 0, MDIO_DEVAD_NONE, 0x0, 0x1140);
-+ return;
-+#endif
-+
-+ /*Reset serdes */
-+ ls1012a_phy_write(&bus, 0, MDIO_DEVAD_NONE, 0x0, 0x8000);
-+
-+ /* SGMII IF mode + AN enable only for 1G SGMII, not for 2.5G */
-+ value = PHY_SGMII_IF_MODE_SGMII;
-+ if (!sgmii_2500)
-+ value |= PHY_SGMII_IF_MODE_AN;
-+
-+ ls1012a_phy_write(&bus, 0, MDIO_DEVAD_NONE, 0x14, value);
-+
-+ /* Dev ability according to SGMII specification */
-+ value = PHY_SGMII_DEV_ABILITY_SGMII;
-+ ls1012a_phy_write(&bus, 0, MDIO_DEVAD_NONE, 0x4, value);
-+
-+ /* Adjust link timer for SGMII -
-+ 1.6 ms in units of 8 ns = 2 * 10^5 = 0x30d40 */
-+ //ls1012a_phy_write(&bus, 0, MDIO_DEVAD_NONE, 0x13, 0x3);
-+ //ls1012a_phy_write(&bus, 0, MDIO_DEVAD_NONE, 0x12, 0xd40);
-+
-+ //These values taken from validation team
-+ ls1012a_phy_write(&bus, 0, MDIO_DEVAD_NONE, 0x13, 0x0);
-+ ls1012a_phy_write(&bus, 0, MDIO_DEVAD_NONE, 0x12, 0x400);
-+
-+ /* Restart AN */
-+ value = PHY_SGMII_CR_DEF_VAL;
-+ if (!sgmii_2500)
-+ value |= PHY_SGMII_CR_RESET_AN;
-+ ls1012a_phy_write(&bus, 0, MDIO_DEVAD_NONE, 0, value);
-+
-+
-+}
-+
-+void ls1012a_set_mdio(int dev_id, struct mii_dev *bus)
-+{
-+ gem_info[dev_id].bus = bus;
-+}
-+
-+void ls1012a_set_phy_address_mode(int dev_id, int phy_id, int phy_mode)
-+{
-+ gem_info[dev_id].phy_address = phy_id;
-+ gem_info[dev_id].phy_mode = phy_mode;
-+}
-+
-+int ls1012a_phy_configure(struct ls1012a_eth_dev *priv, int dev_id, int phy_id)
-+{
-+ struct phy_device *phydev = NULL;
-+ struct eth_device *dev = priv->dev;
-+ struct gemac_s *gem = priv->gem;
-+ struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
-+
-+ //Configure SGMII PCS
-+ if(gem->phy_mode == PHY_INTERFACE_MODE_SGMII ||
-+ gem->phy_mode == PHY_INTERFACE_MODE_SGMII_2500)
-+ {
-+ //printf("Select MDIO from serdes\n");
-+ out_be32(&scfg->mdioselcr, 0x00000000);
-+ ls1012a_configure_serdes(priv);
-+ }
-+
-+ /*By this time on-chip SGMII initialization is done
-+ * we can swith mdio interface to external PHYs */
-+ //printf("Select MDIO from PAD\n");
-+ out_be32(&scfg->mdioselcr, 0x80000000);
-+
-+ if(! gem->bus) return -1;
-+ phydev = phy_connect(gem->bus, phy_id, dev, gem->phy_mode);
-+ if (!phydev) {
-+ printf("phy_connect failed\n");
-+ return -1;
-+ }
-+
-+ phy_config(phydev);
-+
-+ priv->phydev = phydev;
-+
-+ return 0;
-+}
-+#endif
-+
-+int ls1012a_gemac_initialize(bd_t * bis, int dev_id, char *devname)
-+{
-+ struct eth_device *dev;
-+ struct ls1012a_eth_dev *priv;
-+ struct pfe *pfe;
-+ int i;
-+
-+ if(dev_id > 1)
-+ {
-+ printf("Invalid port\n");
-+ return -1;
-+ }
-+
-+ dev = (struct eth_device *)malloc(sizeof(struct eth_device));
-+ if (!dev)
-+ return -1;
-+
-+ memset(dev, 0, sizeof(struct eth_device));
-+
-+ priv = (struct ls1012a_eth_dev *)malloc(sizeof(struct ls1012a_eth_dev));
-+ if (!priv)
-+ return -1;
-+
-+ gemac_list[dev_id] = priv;
-+ priv->gemac_port = dev_id;
-+ priv->gem = &gem_info[priv->gemac_port];
-+ priv->dev = dev;
-+
-+ pfe = &priv->pfe;
-+
-+ pfe->cbus_baseaddr = (void *)CONFIG_SYS_PPFE_ADDR;
-+ pfe->ddr_baseaddr = (void *)CONFIG_DDR_PPFE_BASEADDR;
-+ pfe->ddr_phys_baseaddr = (unsigned long)CONFIG_DDR_PPFE_PHYS_BASEADDR;
-+
-+ sprintf(dev->name, devname);
-+ dev->priv = priv;
-+ dev->init = ls1012a_eth_init;
-+ dev->halt = ls1012a_eth_halt;
-+ dev->send = ls1012a_eth_send;
-+ dev->recv = ls1012a_eth_recv;
-+
-+ /* Tell u-boot to get the addr from the env */
-+ for (i = 0; i < 6; i++)
-+ dev->enetaddr[i] = 0;
-+
-+ pfe_probe(pfe);
-+
-+ switch(priv->gemac_port) {
-+ case EMAC_PORT_0:
-+ default:
-+ priv->gem->gemac_base = EMAC1_BASE_ADDR;
-+ priv->gem->egpi_base = EGPI1_BASE_ADDR;
-+ break;
-+ case EMAC_PORT_1:
-+ priv->gem->gemac_base = EMAC2_BASE_ADDR;
-+ priv->gem->egpi_base = EGPI2_BASE_ADDR;
-+ break;
-+ }
-+
-+
-+#ifndef CONFIG_EMU
-+#if defined(CONFIG_PHYLIB)
-+ if(ls1012a_phy_configure(priv, dev_id, gem_info[priv->gemac_port].phy_address))
-+ return -1;
-+#else
-+ #error ("Please enable CONFIG_PHYLIB")
-+#endif
-+#endif
-+
-+ eth_register(dev);
-+
-+ return 0;
-+}
-diff --git a/drivers/net/pfe_eth/pfe_eth.h b/drivers/net/pfe_eth/pfe_eth.h
-new file mode 100644
-index 0000000..dfcc00e
---- /dev/null
-+++ b/drivers/net/pfe_eth/pfe_eth.h
-@@ -0,0 +1,161 @@
-+/*
-+ * (C) Copyright 2011
-+ * Author : Mindspeed Technologes
-+ *
-+ * See file CREDITS for list of people who contributed to this
-+ * project.
-+ *
-+ * This program is free software; you can redistribute it and/or
-+ * modify it under the terms of the GNU General Public License as
-+ * published by the Free Software Foundation; either version 2 of
-+ * the License, or (at your option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program; if not, write to the Free Software
-+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-+ * MA 02111-1307 USA
-+ * */
-+
-+#ifndef _LS1012a_ETH_H_
-+#define _LS1012a_ETH_H_
-+
-+
-+#include "pfe_driver.h"
-+
-+#ifndef SZ_1K
-+#define SZ_1K 1024
-+#endif
-+
-+#ifndef SZ_1M
-+#define SZ_1M (1024 * 1024)
-+#endif
-+
-+#define BMU2_DDR_BASEADDR 0
-+#define BMU2_BUF_COUNT (3 * SZ_1K)
-+#define BMU2_DDR_SIZE (DDR_BUF_SIZE * BMU2_BUF_COUNT)
-+
-+#define TMU_LLM_BASEADDR (BMU2_DDR_BASEADDR + BMU2_DDR_SIZE)
-+#define TMU_LLM_QUEUE_LEN (16 * 256) /**< Must be power of two and at least 16 * 8 = 128 bytes */
-+#define TMU_LLM_SIZE (4 * 16 * TMU_LLM_QUEUE_LEN) /**< (4 TMU's x 16 queues x queue_len) */
-+
-+#define HIF_RX_PKT_DDR_BASEADDR (TMU_LLM_BASEADDR + TMU_LLM_SIZE)
-+#define HIF_RX_PKT_DDR_SIZE (HIF_RX_DESC_NT * DDR_BUF_SIZE)
-+#define HIF_TX_PKT_DDR_BASEADDR (HIF_RX_PKT_DDR_BASEADDR + HIF_RX_PKT_DDR_SIZE)
-+#define HIF_TX_PKT_DDR_SIZE (HIF_TX_DESC_NT * DDR_BUF_SIZE)
-+
-+#define HIF_DESC_BASEADDR (HIF_TX_PKT_DDR_BASEADDR + HIF_TX_PKT_DDR_SIZE)
-+#define HIF_RX_DESC_SIZE (16*HIF_RX_DESC_NT)
-+#define HIF_TX_DESC_SIZE (16*HIF_TX_DESC_NT)
-+#define HIF_DESC_SIZE (HIF_RX_DESC_SIZE + HIF_TX_DESC_SIZE)
-+
-+//#define FPPDIAG_CTL_BASE_ADDR (HIF_DESC_BASEADDR + HIF_DESC_SIZE)
-+#define FPPDIAG_CTL_BASE_ADDR 0x700000
-+#define FPPDIAG_CTL_SIZE 256 /**< Must be at least 11*8 bytes */
-+#define FPPDIAG_PAGE_BASE_ADDR (FPPDIAG_CTL_BASE_ADDR + FPPDIAG_CTL_SIZE)
-+#define FPPDIAG_PAGE_TOTAL_SIZE (11 * 256) /**< 256 bytes per PE, 11 PEs */
-+
-+//#define UTIL_CODE_BASEADDR (FPPDIAG_PAGE_BASE_ADDR + FPPDIAG_PAGE_TOTAL_SIZE)
-+#define UTIL_CODE_BASEADDR 0x780000
-+#define UTIL_CODE_SIZE (128 * SZ_1K)
-+
-+#define UTIL_DDR_DATA_BASEADDR (UTIL_CODE_BASEADDR + UTIL_CODE_SIZE)
-+#define UTIL_DDR_DATA_SIZE (64 * SZ_1K)
-+
-+#define CLASS_DDR_DATA_BASEADDR (UTIL_DDR_DATA_BASEADDR + UTIL_DDR_DATA_SIZE)
-+#define CLASS_DDR_DATA_SIZE (32 * SZ_1K)
-+
-+#define TMU_DDR_DATA_BASEADDR (CLASS_DDR_DATA_BASEADDR + CLASS_DDR_DATA_SIZE)
-+#define TMU_DDR_DATA_SIZE (32 * SZ_1K)
-+
-+//#define ROUTE_TABLE_BASEADDR (TMU_DDR_DATA_BASEADDR + TMU_DDR_DATA_SIZE)
-+#define ROUTE_TABLE_BASEADDR 0x800000
-+#define ROUTE_TABLE_HASH_BITS_MAX 15 /**< 32K entries */
-+#define ROUTE_TABLE_HASH_BITS 8 /**< 256 entries */
-+#define ROUTE_TABLE_SIZE ((1 << ROUTE_TABLE_HASH_BITS_MAX) * CLASS_ROUTE_SIZE)
-+
-+#define PFE_TOTAL_DATA_SIZE (ROUTE_TABLE_BASEADDR + ROUTE_TABLE_SIZE)
-+
-+#if PFE_TOTAL_DATA_SIZE > (12 * SZ_1M)
-+#error DDR mapping above 12MiB
-+#endif
-+
-+/* LMEM Mapping */
-+#define BMU1_LMEM_BASEADDR 0
-+#define BMU1_BUF_COUNT 256
-+#define BMU1_LMEM_SIZE (LMEM_BUF_SIZE * BMU1_BUF_COUNT)
-+
-+
-+#define CONFIG_DDR_PPFE_PHYS_BASEADDR 0x03800000
-+#define CONFIG_DDR_PPFE_BASEADDR 0x83800000
-+
-+
-+#define GEMAC_NO_PHY 1
-+#define GEMAC_HAVE_SWITCH_PHY 2
-+#define GEMAC_HAVE_SWITCH 4
-+
-+
-+typedef struct gemac_s {
-+
-+ void *gemac_base;
-+ void *egpi_base;
-+
-+ /* GEMAC config */
-+ int gemac_mode;
-+ int gemac_speed;
-+ int gemac_duplex;
-+ int flags;
-+ /* phy iface */
-+ int phy_address;
-+ int phy_mode;
-+ struct mii_dev *bus;
-+
-+} gemac_t;
-+
-+struct mdio_info {
-+ void *reg_base;
-+ char *name;
-+};
-+
-+
-+struct pfe {
-+ unsigned long ddr_phys_baseaddr;
-+ void *ddr_baseaddr;
-+ void *cbus_baseaddr;
-+};
-+
-+
-+typedef struct ls1012a_eth_dev {
-+
-+ int gemac_port;
-+
-+ struct gemac_s *gem;
-+ struct pfe pfe;
-+
-+ struct eth_device *dev;
-+#ifdef CONFIG_PHYLIB
-+ struct phy_device *phydev;
-+#endif
-+} ls1012a_eth_dev_t;
-+
-+
-+struct firmware {
-+ u8 *data;
-+};
-+
-+
-+int pfe_probe(struct pfe *pfe);
-+int pfe_remove(struct pfe *pfe);
-+
-+
-+//#define dprint(fmt, arg...) printf(fmt, ##arg)
-+#define dprint(fmt, arg...)
-+//#define dprint printf
-+
-+
-+#endif //_LS1012a_ETH_H_
-+
-diff --git a/drivers/net/pfe_eth/pfe_firmware.c b/drivers/net/pfe_eth/pfe_firmware.c
-new file mode 100644
-index 0000000..165eb3c
---- /dev/null
-+++ b/drivers/net/pfe_eth/pfe_firmware.c
-@@ -0,0 +1,193 @@
-+
-+
-+/** @file
-+ * Contains all the functions to handle parsing and loading of PE firmware files.
-+ */
-+
-+#include "hal.h"
-+#include "pfe_firmware.h"
-+#include "pfe/pfe.h"
-+
-+
-+/* CLASS-PE ELF file content */
-+unsigned char class_fw_data[] __attribute__((aligned(sizeof(int)))) = {
-+#include CLASS_FIRMWARE_FILENAME
-+};
-+
-+/* TMU-PE ELF file content */
-+unsigned char tmu_fw_data[] __attribute__((aligned(sizeof(int)))) = {
-+#include TMU_FIRMWARE_FILENAME
-+};
-+
-+#if !defined(CONFIG_UTIL_PE_DISABLED)
-+unsigned char util_fw_data[] = {
-+#include UTIL_FIRMWARE_FILENAME
-+};
-+#endif
-+
-+/** PFE elf firmware loader.
-+* Loads an elf firmware image into a list of PE's (specified using a bitmask)
-+*
-+* @param pe_mask Mask of PE id's to load firmware to
-+* @param fw Pointer to the firmware image
-+*
-+* @return 0 on sucess, a negative value on error
-+*
-+*/
-+int pfe_load_elf(int pe_mask, const struct firmware *fw)
-+{
-+ Elf32_Ehdr *elf_hdr = (Elf32_Ehdr *)fw->data;
-+ Elf32_Half sections = be16_to_cpu(elf_hdr->e_shnum);
-+ Elf32_Shdr *shdr = (Elf32_Shdr *) (fw->data + be32_to_cpu(elf_hdr->e_shoff));
-+ int id, section;
-+ int rc;
-+
-+ printf("%s: no of sections: %d\n", __func__, sections);
-+
-+ /* Some sanity checks */
-+ if (strncmp(&elf_hdr->e_ident[EI_MAG0], ELFMAG, SELFMAG))
-+ {
-+ printf("%s: incorrect elf magic number\n", __func__);
-+ return -1;
-+ }
-+
-+ if (elf_hdr->e_ident[EI_CLASS] != ELFCLASS32)
-+ {
-+ printf("%s: incorrect elf class(%x)\n", __func__, elf_hdr->e_ident[EI_CLASS]);
-+ return -1;
-+ }
-+
-+ if (elf_hdr->e_ident[EI_DATA] != ELFDATA2MSB)
-+ {
-+ printf("%s: incorrect elf data(%x)\n", __func__, elf_hdr->e_ident[EI_DATA]);
-+ return -1;
-+ }
-+
-+ if (be16_to_cpu(elf_hdr->e_type) != ET_EXEC)
-+ {
-+ printf("%s: incorrect elf file type(%x)\n", __func__, be16_to_cpu(elf_hdr->e_type));
-+ return -1;
-+ }
-+
-+ for (section = 0; section < sections; section++, shdr++)
-+ {
-+ if (!(be32_to_cpu(shdr->sh_flags) & (SHF_WRITE | SHF_ALLOC | SHF_EXECINSTR)))
-+ continue;
-+ for (id = 0; id < MAX_PE; id++)
-+ if (pe_mask & (1 << id))
-+ {
-+ rc = pe_load_elf_section(id, fw->data, shdr);
-+ if (rc < 0)
-+ goto err;
-+ }
-+ //printf("\n");
-+ }
-+
-+ return 0;
-+
-+err:
-+ return rc;
-+}
-+
-+/** PFE firmware initialization.
-+* Loads different firmware files from filesystem.
-+* Initializes PE IMEM/DMEM and UTIL-PE DDR
-+* Initializes control path symbol addresses (by looking them up in the elf firmware files
-+* Takes PE's out of reset
-+*
-+* @return 0 on sucess, a negative value on error
-+*
-+*/
-+int pfe_firmware_init(u8 *class_fw_loc, u8 *tmu_fw_loc, u8 *util_fw_loc)
-+{
-+ struct firmware class_fw, tmu_fw;
-+#if !defined(CONFIG_UTIL_PE_DISABLED)
-+ struct firmware util_fw;
-+#endif
-+ int rc = 0;
-+
-+ printf("%s\n", __func__);
-+#if 0
-+ /*This testing purpose only */
-+ printf("Copying default fw \n");
-+ memcpy(class_fw_loc, class_fw_data, sizeof(class_fw_data));
-+ memcpy(tmu_fw_loc, tmu_fw_data, sizeof(tmu_fw_data));
-+ memcpy(util_fw_loc, util_fw_data, sizeof(util_fw_data));
-+#endif
-+
-+ if (class_fw_loc)
-+ class_fw.data = class_fw_loc;
-+ else
-+ class_fw.data = class_fw_data;
-+
-+ if (tmu_fw_loc)
-+ tmu_fw.data = tmu_fw_loc;
-+ else
-+ tmu_fw.data = tmu_fw_data;
-+
-+#if !defined(CONFIG_UTIL_PE_DISABLED)
-+ if (util_fw_loc)
-+ util_fw.data = util_fw_loc;
-+ else
-+ util_fw.data = util_fw_data;
-+#endif
-+
-+ rc = pfe_load_elf(CLASS_MASK, &class_fw);
-+ if (rc < 0) {
-+ printf("%s: class firmware load failed\n", __func__);
-+ goto err3;
-+ }
-+
-+ printf("%s: class firmware loaded\n", __func__);
-+
-+ rc = pfe_load_elf(TMU_MASK, &tmu_fw);
-+ if (rc < 0) {
-+ printf("%s: tmu firmware load failed\n", __func__);
-+ goto err3;
-+ }
-+
-+ printf("%s: tmu firmware loaded\n", __func__);
-+
-+#if !defined(CONFIG_UTIL_PE_DISABLED)
-+ rc = pfe_load_elf(UTIL_MASK, &util_fw);
-+ if (rc < 0) {
-+ printf("%s: util firmware load failed\n", __func__);
-+ goto err3;
-+ }
-+
-+ printf("%s: util firmware loaded\n", __func__);
-+
-+ util_enable();
-+#endif
-+
-+#if defined(CONFIG_LS1012A)
-+ tmu_enable(0xb);
-+#else
-+ tmu_enable(0xf);
-+#endif
-+ class_enable();
-+
-+ gpi_enable(HGPI_BASE_ADDR);
-+
-+
-+err3:
-+ return rc;
-+}
-+
-+/** PFE firmware cleanup
-+* Puts PE's in reset
-+*
-+*
-+*/
-+void pfe_firmware_exit(void)
-+{
-+ printf("%s\n", __func__);
-+
-+ class_disable();
-+ tmu_disable(0xf);
-+#if !defined(CONFIG_UTIL_PE_DISABLED)
-+ util_disable();
-+#endif
-+ hif_tx_disable();
-+ hif_rx_disable();
-+}
-diff --git a/drivers/net/pfe_eth/pfe_firmware.h b/drivers/net/pfe_eth/pfe_firmware.h
-new file mode 100644
-index 0000000..2823162
---- /dev/null
-+++ b/drivers/net/pfe_eth/pfe_firmware.h
-@@ -0,0 +1,20 @@
-+
-+
-+/** @file
-+ * Contains all the defines to handle parsing and loading of PE firmware files.
-+ */
-+
-+#ifndef __PFE_FIRMWARE_H__
-+#define __PFE_FIRMWARE_H__
-+
-+
-+#define CLASS_FIRMWARE_FILENAME "class_sbl_elf.fw"
-+#define TMU_FIRMWARE_FILENAME "tmu_sbl_elf.fw"
-+#define UTIL_FIRMWARE_FILENAME "util_sbl_elf.fw"
-+
-+
-+int pfe_firmware_init(u8 * clasS_fw_loc, u8 *tmu_fw_loc, u8 *util_fw_loc);
-+void pfe_firmware_exit(void);
-+
-+
-+#endif
-diff --git a/drivers/net/pfe_eth/pfe_mod.h b/drivers/net/pfe_eth/pfe_mod.h
-new file mode 100644
-index 0000000..9436b72
---- /dev/null
-+++ b/drivers/net/pfe_eth/pfe_mod.h
-@@ -0,0 +1,140 @@
-+/*
-+ * (C) Copyright 2011
-+ * Author : Mindspeed Technologes
-+ *
-+ * See file CREDITS for list of people who contributed to this
-+ * project.
-+ *
-+ * This program is free software; you can redistribute it and/or
-+ * modify it under the terms of the GNU General Public License as
-+ * published by the Free Software Foundation; either version 2 of
-+ * the License, or (at your option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program; if not, write to the Free Software
-+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-+ * MA 02111-1307 USA
-+ * */
-+
-+
-+#ifndef _PFE_MOD_H_
-+#define _PFE_MOD_H_
-+
-+#include <linux/device.h>
-+
-+#include "pfe/pfe.h"
-+#include "pfe/cbus.h"
-+#include "pfe/cbus/bmu.h"
-+
-+#include "pfe_driver.h"
-+
-+struct pfe;
-+
-+
-+struct pfe {
-+ unsigned long ddr_phys_baseaddr;
-+ void *ddr_baseaddr;
-+ void *cbus_baseaddr;
-+ void *apb_baseaddr;
-+ void *iram_baseaddr;
-+ int hif_irq;
-+ struct device *dev;
-+ struct pci_dev *pdev;
-+
-+#if 0
-+ struct pfe_ctrl ctrl;
-+ struct pfe_hif hif;
-+ struct pfe_eth eth;
-+#endif
-+};
-+
-+extern struct pfe *pfe;
-+
-+int pfe_probe(struct pfe *pfe);
-+int pfe_remove(struct pfe *pfe);
-+
-+#ifndef SZ_1K
-+#define SZ_1K 1024
-+#endif
-+
-+#ifndef SZ_1M
-+#define SZ_1M (1024 * 1024)
-+#endif
-+
-+/* DDR Mapping */
-+#if !defined(CONFIG_PLATFORM_PCI)
-+#define UTIL_CODE_BASEADDR 0
-+#define UTIL_CODE_SIZE (128 * SZ_1K)
-+#define UTIL_DDR_DATA_BASEADDR (UTIL_CODE_BASEADDR + UTIL_CODE_SIZE)
-+#define UTIL_DDR_DATA_SIZE (64 * SZ_1K)
-+#define CLASS_DDR_DATA_BASEADDR (UTIL_DDR_DATA_BASEADDR + UTIL_DDR_DATA_SIZE)
-+#define CLASS_DDR_DATA_SIZE (32 * SZ_1K)
-+#define TMU_DDR_DATA_BASEADDR (CLASS_DDR_DATA_BASEADDR + CLASS_DDR_DATA_SIZE)
-+#define TMU_DDR_DATA_SIZE (32 * SZ_1K)
-+#define ROUTE_TABLE_BASEADDR (TMU_DDR_DATA_BASEADDR + TMU_DDR_DATA_SIZE)
-+#define ROUTE_TABLE_HASH_BITS 15 /**< 32K entries */
-+#define ROUTE_TABLE_SIZE ((1 << ROUTE_TABLE_HASH_BITS) * CLASS_ROUTE_SIZE)
-+#define BMU2_DDR_BASEADDR (ROUTE_TABLE_BASEADDR + ROUTE_TABLE_SIZE)
-+#define BMU2_BUF_COUNT (4096 - 256) /**< This is to get a total DDR size of 12MiB */
-+#define BMU2_DDR_SIZE (DDR_BUF_SIZE * BMU2_BUF_COUNT)
-+#define TMU_LLM_BASEADDR (BMU2_DDR_BASEADDR + BMU2_DDR_SIZE)
-+#define TMU_LLM_QUEUE_LEN (16 * 256) /**< Must be power of two and at least 16 * 8 = 128 bytes */
-+#define TMU_LLM_SIZE (4 * 16 * TMU_LLM_QUEUE_LEN) /**< (4 TMU's x 16 queues x queue_len) */
-+
-+#if (TMU_LLM_BASEADDR + TMU_LLM_SIZE) > 0xC00000
-+#error DDR mapping above 12MiB
-+#endif
-+
-+#else
-+
-+#define UTIL_CODE_BASEADDR 0
-+#if defined(CONFIG_UTIL_PE_DISABLED)
-+#define UTIL_CODE_SIZE (0 * SZ_1K)
-+#else
-+#define UTIL_CODE_SIZE (8 * SZ_1K)
-+#endif
-+#define UTIL_DDR_DATA_BASEADDR (UTIL_CODE_BASEADDR + UTIL_CODE_SIZE)
-+#define UTIL_DDR_DATA_SIZE (0 * SZ_1K)
-+#define CLASS_DDR_DATA_BASEADDR (UTIL_DDR_DATA_BASEADDR + UTIL_DDR_DATA_SIZE)
-+#define CLASS_DDR_DATA_SIZE (0 * SZ_1K)
-+#define TMU_DDR_DATA_BASEADDR (CLASS_DDR_DATA_BASEADDR + CLASS_DDR_DATA_SIZE)
-+#define TMU_DDR_DATA_SIZE (0 * SZ_1K)
-+#define ROUTE_TABLE_BASEADDR (TMU_DDR_DATA_BASEADDR + TMU_DDR_DATA_SIZE)
-+#define ROUTE_TABLE_HASH_BITS 5 /**< 32 entries */
-+#define ROUTE_TABLE_SIZE ((1 << ROUTE_TABLE_HASH_BITS) * CLASS_ROUTE_SIZE)
-+#define BMU2_DDR_BASEADDR (ROUTE_TABLE_BASEADDR + ROUTE_TABLE_SIZE)
-+#define BMU2_BUF_COUNT 8
-+#define BMU2_DDR_SIZE (DDR_BUF_SIZE * BMU2_BUF_COUNT)
-+#define TMU_LLM_BASEADDR (BMU2_DDR_BASEADDR + BMU2_DDR_SIZE)
-+#define TMU_LLM_QUEUE_LEN (16 * 8) /**< Must be power of two and at least 16 * 8 = 128 bytes */
-+#define TMU_LLM_SIZE (4 * 16 * TMU_LLM_QUEUE_LEN) /**< (4 TMU's x 16 queues x queue_len) */
-+#define HIF_DESC_BASEADDR (TMU_LLM_BASEADDR + TMU_LLM_SIZE)
-+#define HIF_RX_DESC_SIZE (16*HIF_RX_DESC_NT)
-+#define HIF_TX_DESC_SIZE (16*HIF_TX_DESC_NT)
-+#define HIF_DESC_SIZE (HIF_RX_DESC_SIZE + HIF_TX_DESC_SIZE)
-+#define HIF_RX_PKT_DDR_BASEADDR (HIF_DESC_BASEADDR + HIF_DESC_SIZE)
-+#define HIF_RX_PKT_DDR_SIZE (HIF_RX_DESC_NT * DDR_BUF_SIZE)
-+#define HIF_TX_PKT_DDR_BASEADDR (HIF_RX_PKT_DDR_BASEADDR + HIF_RX_PKT_DDR_SIZE)
-+#define HIF_TX_PKT_DDR_SIZE (HIF_TX_DESC_NT * DDR_BUF_SIZE)
-+#define ROUTE_BASEADDR (HIF_TX_PKT_DDR_BASEADDR + HIF_TX_PKT_DDR_SIZE)
-+#define ROUTE_SIZE (2 * CLASS_ROUTE_SIZE)
-+
-+#if (ROUTE_BASEADDR + ROUTE_SIZE) > 0x10000
-+#error DDR mapping above 64KiB
-+#endif
-+
-+#define PFE_HOST_TO_PCI(addr) (((u32)addr)- ((u32)DDR_BASE_ADDR))
-+#define PFE_PCI_TO_HOST(addr) (((u32)addr)+ ((u32)DDR_BASE_ADDR))
-+#endif
-+
-+/* LMEM Mapping */
-+#define BMU1_LMEM_BASEADDR 0
-+#define BMU1_BUF_COUNT 256
-+#define BMU1_LMEM_SIZE (LMEM_BUF_SIZE * BMU1_BUF_COUNT)
-+
-+#endif /* _PFE_MOD_H */
-diff --git a/drivers/net/pfe_eth/tmu_sbl_elf.fw b/drivers/net/pfe_eth/tmu_sbl_elf.fw
-new file mode 100644
-index 0000000..d9e8409
---- /dev/null
-+++ b/drivers/net/pfe_eth/tmu_sbl_elf.fw
-@@ -0,0 +1 @@
-+0x7f,0x45,0x4c,0x46,0x01,0x02,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x02,0x00,0x6f,0x00,0x00,0x00,0x01,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x34,0x00,0x00,0x25,0x80,0x00,0x04,0x00,0x05,0x00,0x34,0x00,0x20,0x00,0x04,0x00,0x28,0x00,0x0a,0x00,0x09,0x00,0x00,0x00,0x01,0x00,0x00,0x10,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x28,0x00,0x00,0x00,0x28,0x00,0x00,0x00,0x04,0x00,0x00,0x10,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x10,0x80,0x00,0x00,0x00,0x80,0x00,0x00,0 [...]
-\ No newline at end of file
-diff --git a/drivers/net/pfe_eth/util_sbl_elf.fw b/drivers/net/pfe_eth/util_sbl_elf.fw
-new file mode 100644
-index 0000000..7a34b86
---- /dev/null
-+++ b/drivers/net/pfe_eth/util_sbl_elf.fw
-@@ -0,0 +1 @@
-+0x7f,0x45,0x4c,0x46,0x01,0x02,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x02,0x00,0x6f,0x00,0x00,0x00,0x01,0x03,0xf8,0x00,0x00,0x00,0x00,0x00,0x34,0x00,0x00,0x2c,0xd4,0x00,0x04,0x00,0x05,0x00,0x34,0x00,0x20,0x00,0x04,0x00,0x28,0x00,0x0c,0x00,0x0b,0x00,0x00,0x00,0x01,0x00,0x00,0x10,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x5c,0x00,0x00,0x03,0xb4,0x00,0x00,0x00,0x06,0x00,0x00,0x10,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x13,0xb4,0x00,0x00,0x03,0xb4,0x00,0x00,0 [...]
-\ No newline at end of file
-diff --git a/include/configs/ls1012a_common.h b/include/configs/ls1012a_common.h
-index 07ef7c6..3c4ab6c 100644
---- a/include/configs/ls1012a_common.h
-+++ b/include/configs/ls1012a_common.h
-@@ -109,6 +109,16 @@
- #define CONFIG_CMD_PING
- #undef CONFIG_CMD_IMLS
-
-+/* PPFE */
-+#define CONFIG_FSL_PPFE
-+
-+#ifdef CONFIG_FSL_PPFE
-+#define CONFIG_CMD_PFE_START
-+#define CONFIG_CMD_PFE_COMMANDS
-+#define CONFIG_UTIL_PE_DISABLED
-+
-+#endif
-+
-
- #define CONFIG_ARCH_EARLY_INIT_R
-
-diff --git a/include/configs/ls1012aqds.h b/include/configs/ls1012aqds.h
-index 488811b..1fa7b6f 100644
---- a/include/configs/ls1012aqds.h
-+++ b/include/configs/ls1012aqds.h
-@@ -14,16 +14,14 @@
- #define CONFIG_CHIP_SELECTS_PER_CTRL 1
- #define CONFIG_NR_DRAM_BANKS 2
-
--#ifdef CONFIG_SYS_DPAA_FMAN
--#define CONFIG_FMAN_ENET
-+#ifdef CONFIG_FSL_PPFE
-+/*#define CONFIG_CMD_PFE_START */
-+#define EMAC1_PHY_ADDR 0x1e
-+#define EMAC2_PHY_ADDR 0x1
- #define CONFIG_PHYLIB
- #define CONFIG_PHY_VITESSE
- #define CONFIG_PHY_REALTEK
--#define RGMII_PHY1_ADDR 0x1
--#define SGMII_CARD_PORT1_PHY_ADDR 0x1C
--#define SGMII_CARD_PORT2_PHY_ADDR 0x1D
--#define SGMII_CARD_PORT3_PHY_ADDR 0x1E
--#define SGMII_CARD_PORT4_PHY_ADDR 0x1F
-+#define RGMII_RESET_WA
- #endif
-
- /* MMC */
-@@ -142,6 +140,7 @@
- #define I2C_VOL_MONITOR_BUS_V_OVF 0x1
- #define I2C_VOL_MONITOR_BUS_V_SHIFT 3
-
-+
- /* DSPI */
- #define CONFIG_FSL_DSPI
- #define CONFIG_FSL_DSPI1
-diff --git a/include/configs/ls1012ardb.h b/include/configs/ls1012ardb.h
-index 1629e19..1b72bf1 100644
---- a/include/configs/ls1012ardb.h
-+++ b/include/configs/ls1012ardb.h
-@@ -19,10 +19,12 @@
- #define CONFIG_SYS_MEMTEST_START 0x80000000
- #define CONFIG_SYS_MEMTEST_END 0x9fffffff
-
-+#ifdef CONFIG_FSL_PPFE
-+#define EMAC1_PHY_ADDR 0x2
-+#define EMAC2_PHY_ADDR 0x1
- #define CONFIG_PHYLIB
- #define CONFIG_PHY_REALTEK
--#define SGMII_PHY1_ADDR 0x0
--#define RGMII_PHY2_ADDR 0x1
-+#endif
-
- /*
- * USB
---
-1.7.9.5
-
diff --git a/package/boot/uboot-layerscape/patches/0042-DNCPE-138-Rest-external-PHYs.patch b/package/boot/uboot-layerscape/patches/0042-DNCPE-138-Rest-external-PHYs.patch
deleted file mode 100644
index 17542dd..0000000
--- a/package/boot/uboot-layerscape/patches/0042-DNCPE-138-Rest-external-PHYs.patch
+++ /dev/null
@@ -1,69 +0,0 @@
-From 63acb257c32bd86abbad5abcc002d6c78b72f0ab Mon Sep 17 00:00:00 2001
-From: Anji J <anji.jagarlmudi at freescale.com>
-Date: Mon, 16 May 2016 20:21:38 +0530
-Subject: [PATCH 42/93] DNCPE-138 Rest external PHYs
-
-Need to reset external PHYs through IO expander for proper function.
-
-Signed-off-by: Anjaneyulu Jagarlmudi <anji.jagarlmudi at nxp.com>>
-Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha at nxp.com>
----
- board/freescale/ls1012ardb/eth.c | 14 ++++++++++++++
- include/configs/ls1012ardb.h | 9 +++++++++
- 2 files changed, 23 insertions(+)
-
-diff --git a/board/freescale/ls1012ardb/eth.c b/board/freescale/ls1012ardb/eth.c
-index 29830e8..24fdd83 100644
---- a/board/freescale/ls1012ardb/eth.c
-+++ b/board/freescale/ls1012ardb/eth.c
-@@ -20,6 +20,20 @@
-
- #define DEFAULT_PFE_MDIO_NAME "PFE_MDIO"
-
-+
-+void reset_phy(void)
-+{
-+
-+ /*Through reset IO expander reset both RGMII and SGMII PHYs */
-+ i2c_reg_write(CONFIG_SYS_I2C_RESET_IO_EXPANDER, 6, __PHY_MASK);
-+ i2c_reg_write(CONFIG_SYS_I2C_RESET_IO_EXPANDER, 2, __PHY_ETH2_MASK);
-+ mdelay(10);
-+ i2c_reg_write(CONFIG_SYS_I2C_RESET_IO_EXPANDER, 2, __PHY_ETH1_MASK);
-+ mdelay(10);
-+ i2c_reg_write(CONFIG_SYS_I2C_RESET_IO_EXPANDER, 2, 0xFF);
-+ mdelay(50);
-+}
-+
- int board_eth_init(bd_t *bis)
- {
- #ifdef CONFIG_FSL_PPFE
-diff --git a/include/configs/ls1012ardb.h b/include/configs/ls1012ardb.h
-index 1b72bf1..23722e0 100644
---- a/include/configs/ls1012ardb.h
-+++ b/include/configs/ls1012ardb.h
-@@ -24,6 +24,7 @@
- #define EMAC2_PHY_ADDR 0x1
- #define CONFIG_PHYLIB
- #define CONFIG_PHY_REALTEK
-+#define CONFIG_RESET_PHY_R
- #endif
-
- /*
-@@ -128,6 +129,14 @@
- #define __SW_REV_A 0xF8
- #define __SW_REV_B 0xF0
-
-+/*
-+ *I2C RESET expander
-+ */
-+#define CONFIG_SYS_I2C_RESET_IO_EXPANDER 0x25
-+#define __PHY_MASK 0xF9
-+#define __PHY_ETH2_MASK 0xFB
-+#define __PHY_ETH1_MASK 0xFD
-+
- #define CONFIG_CMD_MEMINFO
- #define CONFIG_CMD_MEMTEST
- #define CONFIG_SYS_MEMTEST_START 0x80000000
---
-1.7.9.5
-
diff --git a/package/boot/uboot-layerscape/patches/0043-DNCPE-296-PFE-reset-workaround.patch b/package/boot/uboot-layerscape/patches/0043-DNCPE-296-PFE-reset-workaround.patch
deleted file mode 100644
index b87336e..0000000
--- a/package/boot/uboot-layerscape/patches/0043-DNCPE-296-PFE-reset-workaround.patch
+++ /dev/null
@@ -1,334 +0,0 @@
-From b17d75d2c1dc6cd1d55bcddbf7d3d4242e85e88e Mon Sep 17 00:00:00 2001
-From: Anji J <anji.jagarlmudi at freescale.com>
-Date: Fri, 20 May 2016 15:25:12 +0530
-Subject: [PATCH 43/93] DNCPE-296 PFE reset workaround
-
-LS1012A PFE doesn't have global reset control.
-Due to this Linux pfe doesn't work when it was started at U-boot
-This patch provides U-boot command to stop pfe, that should be used before starting Linux.
-
-Signed-off-by: Anjaneyulu Jagarlmudi <anji.jagarlmudi at nxp.com>>
-Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha at nxp.com>
----
- common/cmd_pfe_commands.c | 83 +++++++++++++++++++++++++++++++++++-
- drivers/net/pfe_eth/pfe/cbus/hif.h | 3 ++
- drivers/net/pfe_eth/pfe/pfe.h | 2 +
- drivers/net/pfe_eth/pfe_driver.c | 58 ++++++++++++++++++++-----
- drivers/net/pfe_eth/pfe_eth.c | 6 +--
- 5 files changed, 136 insertions(+), 16 deletions(-)
-
-diff --git a/common/cmd_pfe_commands.c b/common/cmd_pfe_commands.c
-index f9f92c7..0e22097 100644
---- a/common/cmd_pfe_commands.c
-+++ b/common/cmd_pfe_commands.c
-@@ -35,6 +35,7 @@
- #include "../drivers/net/pfe_eth/pfe/cbus/gpi.h"
- DECLARE_GLOBAL_DATA_PTR;
-
-+void hif_rx_desc_disable(void);
- int pfe_load_elf(int pe_mask, const struct firmware *fw);
- int ls1012a_gemac_initialize(bd_t * bis, int dev_id, char *devname);
-
-@@ -593,7 +594,9 @@ void bmu(int id, void *base)
- }
-
- #define PESTATUS_ADDR_CLASS 0x800
-+#define PEMBOX_ADDR_CLASS 0x890
- #define PESTATUS_ADDR_TMU 0x80
-+#define PEMBOX_ADDR_TMU 0x290
- #define PESTATUS_ADDR_UTIL 0x0
-
- static void pfe_pe_status(int argc, char * const argv[])
-@@ -857,7 +860,6 @@ void hif_rx_enable(void)
- void hif_rx_disable(void)
- }
- #endif
--
- #define ROUTE_TABLE_START (CONFIG_DDR_PHYS_BASEADDR+ROUTE_TABLE_BASEADDR)
- static void pfe_command_fftest(int argc, char * const argv[])
- {
-@@ -865,7 +867,6 @@ static void pfe_command_fftest(int argc, char * const argv[])
- struct eth_device *edev_eth0;
- struct eth_device *edev_eth1;
-
--
- // open eth0 and eth1
- edev_eth0 = eth_get_dev_by_name("pfe_eth0");
- if (!edev_eth0)
-@@ -916,6 +917,80 @@ static void pfe_command_start(int argc, char * const argv[])
- }
- #endif
-
-+#ifdef PFE_LS1012A_RESET_WA
-+/*This function sends a dummy packet to HIF through TMU3 */
-+static void send_dummy_pkt_to_hif(void)
-+{
-+ u32 buf;
-+ static u32 dummy_pkt[] = {
-+ 0x4200800a, 0x01000003, 0x00018100, 0x00000000,
-+ 0x33221100, 0x2b785544, 0xd73093cb, 0x01000608,
-+ 0x04060008, 0x2b780200, 0xd73093cb, 0x0a01a8c0,
-+ 0x33221100, 0xa8c05544, 0x00000301, 0x00000000,
-+ 0x00000000, 0x00000000, 0x00000000, 0xbe86c51f };
-+
-+ /*Allocate BMU2 buffer */
-+ buf = readl(BMU2_BASE_ADDR + BMU_ALLOC_CTRL);
-+
-+ printf("Sending a dummy pkt to HIF %x\n", buf);
-+ buf += 0x80;
-+ memcpy((void *)DDR_PFE_TO_VIRT(buf), dummy_pkt, sizeof(dummy_pkt));
-+ /*Write length and pkt to TMU*/
-+ writel(0x03000042, TMU_PHY_INQ_PKTPTR);
-+ writel(buf, TMU_PHY_INQ_PKTINFO);
-+
-+}
-+
-+static void pfe_command_stop(int argc, char * const argv[])
-+{
-+ int id;
-+ u32 rx_status;
-+ printf("Stopping PFE \n");
-+
-+ /*Mark all descriptors as LAST_BD */
-+ hif_rx_desc_disable();
-+
-+ /*If HIF Rx BDP is busy send a dummy packet */
-+ rx_status = readl(HIF_RX_STATUS);
-+ printf("rx_status %x %x\n",rx_status, BDP_CSR_RX_DMA_ACTV);
-+ if(rx_status & BDP_CSR_RX_DMA_ACTV)
-+ send_dummy_pkt_to_hif();
-+ udelay(10);
-+
-+ if(readl(HIF_RX_STATUS) & BDP_CSR_RX_DMA_ACTV)
-+ printf("Unable to stop HIF\n");
-+
-+ /*Disable Class PEs */
-+
-+ for (id = CLASS0_ID; id <= CLASS_MAX_ID; id++)
-+ {
-+ printf("Stop %d\n", id);
-+ /*Inform PE to stop */
-+ pe_dmem_write(id, cpu_to_be32(1), PEMBOX_ADDR_CLASS, 4);
-+ udelay(10);
-+
-+ printf("Reading %d\n", id);
-+ /*Read status */
-+ if(!pe_dmem_read(id, PEMBOX_ADDR_CLASS+4, 4))
-+ printf("Failed to stop PE%d\n", id);
-+ }
-+ /*Disable TMU PEs */
-+ for (id = TMU0_ID; id <= TMU_MAX_ID; id++)
-+ {
-+ if(id == TMU2_ID) continue;
-+
-+ printf("Stop %d\n", id);
-+ /*Inform PE to stop */
-+ pe_dmem_write(id, 1, PEMBOX_ADDR_TMU, 4);
-+ udelay(10);
-+
-+ printf("Reading %d\n", id);
-+ /*Read status */
-+ if(!pe_dmem_read(id, PEMBOX_ADDR_TMU+4, 4))
-+ printf("Failed to stop PE%d\n", id);
-+ }
-+}
-+#endif
-
- static int pfe_command(cmd_tbl_t *cmdtp, int flag, int argc,
- char * const argv[])
-@@ -965,6 +1040,10 @@ static int pfe_command(cmd_tbl_t *cmdtp, int flag, int argc,
- else if (strcmp(argv[1], "start") == 0)
- pfe_command_start(argc, argv);
- #endif
-+#ifdef PFE_LS1012A_RESET_WA
-+ else if (strcmp(argv[1], "stop") == 0)
-+ pfe_command_stop(argc, argv);
-+#endif
- else
- {
- printf("Unknown option: %s\n", argv[1]);
-diff --git a/drivers/net/pfe_eth/pfe/cbus/hif.h b/drivers/net/pfe_eth/pfe/cbus/hif.h
-index a4dd7c2..2329faa 100644
---- a/drivers/net/pfe_eth/pfe/cbus/hif.h
-+++ b/drivers/net/pfe_eth/pfe/cbus/hif.h
-@@ -34,6 +34,9 @@
- #define HIF_CTRL_BDP_POLL_CTRL_EN (1<<1)
- #define HIF_CTRL_BDP_CH_START_WSTB (1<<2)
-
-+/*HIF_RX_STATUS bits */
-+#define BDP_CSR_RX_DMA_ACTV (1<<16)
-+
- /*HIF_INT_ENABLE bits */
- #define HIF_INT_EN (1 << 0)
- #define HIF_RXBD_INT_EN (1 << 1)
-diff --git a/drivers/net/pfe_eth/pfe/pfe.h b/drivers/net/pfe_eth/pfe/pfe.h
-index e8e2221..6994a20 100644
---- a/drivers/net/pfe_eth/pfe/pfe.h
-+++ b/drivers/net/pfe_eth/pfe/pfe.h
-@@ -1,6 +1,8 @@
- #ifndef _PFE_H_
- #define _PFE_H_
-
-+#define PFE_LS1012A_RESET_WA
-+
- #define CLASS_DMEM_BASE_ADDR(i) (0x00000000 | ((i) << 20))
- #define CLASS_IMEM_BASE_ADDR(i) (0x00000000 | ((i) << 20)) /* Only valid for mem access register interface */
- #define CLASS_DMEM_SIZE 0x00002000
-diff --git a/drivers/net/pfe_eth/pfe_driver.c b/drivers/net/pfe_eth/pfe_driver.c
-index ca00e98..b06a352 100644
---- a/drivers/net/pfe_eth/pfe_driver.c
-+++ b/drivers/net/pfe_eth/pfe_driver.c
-@@ -51,13 +51,18 @@ int pfe_recv(unsigned int *pkt_ptr, int *phy_port)
- struct rx_desc_s *rx_desc = g_rx_desc;
- struct bufDesc *bd;
- int len = -1;
-- //volatile u32 ctrl;
-+ volatile u32 ctrl;
- struct hif_header_s *hif_header;
-
- bd = rx_desc->rxBase + rx_desc->rxToRead;
-
-- if (bd->ctrl & BD_CTRL_DESC_EN)
-+ if (bd->ctrl & BD_CTRL_DESC_EN) {
-+ if(!(readl(HIF_RX_STATUS) & BDP_CSR_RX_DMA_ACTV)){
-+ /*If BDP is not active give write strobe */
-+ writel((readl(HIF_RX_CTRL) | HIF_CTRL_BDP_CH_START_WSTB), HIF_RX_CTRL);
-+ }
- return len; //No pending Rx packet
-+ }
-
- /* this len include hif_header(8bytes) */
- len = bd->ctrl & 0xFFFF;
-@@ -69,7 +74,7 @@ int pfe_recv(unsigned int *pkt_ptr, int *phy_port)
- dprint("Pkt recv'd: Pkt ptr(%p), len(%d), gemac_port(%d) status(%08x)\n",
- hif_header, len, hif_header->port_no, bd->status);
-
--#if 0
-+#if DEBUG
- {
- int i;
- unsigned char *p = (unsigned char *)hif_header;
-@@ -85,20 +90,26 @@ int pfe_recv(unsigned int *pkt_ptr, int *phy_port)
- *pkt_ptr = (unsigned int )(hif_header + 1);
- *phy_port = hif_header->port_no;
- len -= sizeof(struct hif_header_s);
--#if 0
-+
-+#if defined(PFE_LS1012A_RESET_WA)
- /* reset bd control field */
-- ctrl = (MAX_FRAME_SIZE | BD_CTRL_DESC_EN | BD_CTRL_DIR);
-+ ctrl = (MAX_FRAME_SIZE | BD_CTRL_LAST_BD | BD_CTRL_LIFM | BD_CTRL_DESC_EN | BD_CTRL_DIR);
-+#else
-+ /* reset bd control field */
-+ ctrl = (MAX_FRAME_SIZE | BD_CTRL_LIFM | BD_CTRL_DESC_EN | BD_CTRL_DIR);
-+ /* If we use BD_CTRL_LAST_BD, rxToRead never changes */
-+ rx_desc->rxToRead = (rx_desc->rxToRead + 1) & (rx_desc->rxRingSize - 1);
-+#endif
- bd->ctrl = ctrl;
- bd->status = 0;
-
-- rx_desc->rxToRead = (rx_desc->rxToRead + 1) & (rx_desc->rxRingSize - 1);
-
- /* Give START_STROBE to BDP to fetch the descriptor __NOW__,
- * BDP need not to wait for rx_poll_cycle time to fetch the descriptor,
- * In idle state (ie., no rx pkt), BDP will not fetch
- * the descriptor even if strobe is given(I think) */
- writel((readl(HIF_RX_CTRL) | HIF_CTRL_BDP_CH_START_WSTB), HIF_RX_CTRL);
--#endif
-+
- return len;
- }
-
-@@ -298,14 +309,37 @@ void hif_rx_desc_dump(void)
- rx_desc = g_rx_desc;
- bd_va = rx_desc->rxBase;
-
-- printf("HIF rx desc: base_va: %p, base_pa: %08x\n", rx_desc->rxBase, rx_desc->rxBase_pa);
-+ dprint("HIF rx desc: base_va: %p, base_pa: %08x\n", rx_desc->rxBase, rx_desc->rxBase_pa);
- for (i=0; i < rx_desc->rxRingSize; i++) {
--// printf("status: %08x, ctrl: %08x, data: %08x, next: %p\n",
--// bd_va->status, bd_va->ctrl, bd_va->data, bd_va->next);
-+ dprint("status: %08x, ctrl: %08x, data: %08x, next: %p\n",
-+ bd_va->status, bd_va->ctrl, bd_va->data, bd_va->next);
-+ bd_va++;
-+ }
-+}
-+
-+/** This function mark all Rx descriptors as LAST_BD.
-+ */
-+void hif_rx_desc_disable(void)
-+{
-+ int i;
-+ struct rx_desc_s *rx_desc;
-+ struct bufDesc *bd_va;
-+
-+ if (g_rx_desc == NULL) {
-+ printf("%s: HIF Rx desc not initialized \n", __func__);
-+ return;
-+ }
-+
-+ rx_desc = g_rx_desc;
-+ bd_va = rx_desc->rxBase;
-+
-+ for (i=0; i < rx_desc->rxRingSize; i++) {
-+ bd_va->ctrl |= BD_CTRL_LAST_BD;
- bd_va++;
- }
- }
-
-+
- /** HIF Rx Desc initialization function.
- */
- static int hif_rx_desc_init(struct pfe *pfe)
-@@ -348,7 +382,11 @@ static int hif_rx_desc_init(struct pfe *pfe)
-
- memset(bd_va, 0, sizeof(struct bufDesc) * rx_desc->rxRingSize);
-
-+#if defined(PFE_LS1012A_RESET_WA)
-+ ctrl = (MAX_FRAME_SIZE | BD_CTRL_LAST_BD | BD_CTRL_DESC_EN | BD_CTRL_DIR | BD_CTRL_LIFM);
-+#else
- ctrl = (MAX_FRAME_SIZE | BD_CTRL_DESC_EN | BD_CTRL_DIR | BD_CTRL_LIFM);
-+#endif
- for (i=0; i < rx_desc->rxRingSize; i++) {
- bd_va->next = (u32 )(bd_pa + 1);
- bd_va->ctrl = ctrl;
-diff --git a/drivers/net/pfe_eth/pfe_eth.c b/drivers/net/pfe_eth/pfe_eth.c
-index 40ac095..40f2c39 100644
---- a/drivers/net/pfe_eth/pfe_eth.c
-+++ b/drivers/net/pfe_eth/pfe_eth.c
-@@ -48,7 +48,7 @@ static void ls1012a_gemac_enable(void *gemac_base)
- writel(readl(gemac_base + EMAC_ECNTRL_REG) | EMAC_ECNTRL_ETHER_EN, gemac_base + EMAC_ECNTRL_REG);
- }
-
--static void ls1012a_gemac_dsable(void *gemac_base)
-+static void ls1012a_gemac_disable(void *gemac_base)
- {
- writel(readl(gemac_base + EMAC_ECNTRL_REG) & ~EMAC_ECNTRL_ETHER_EN, gemac_base + EMAC_ECNTRL_REG);
- }
-@@ -113,7 +113,7 @@ static void ls1012a_eth_halt(struct eth_device *edev)
- {
- struct ls1012a_eth_dev *priv = (struct ls1012a_eth_dev *)edev->priv;
-
-- ls1012a_gemac_enable(priv->gem->gemac_base);
-+ ls1012a_gemac_disable(priv->gem->gemac_base);
-
- gpi_disable(priv->gem->egpi_base);
-
-@@ -216,14 +216,12 @@ static int ls1012a_eth_recv(struct eth_device *dev)
- dprint("Rx pkt: pkt_buf(%08x), phy_port(%d), len(%d)\n", pkt_buf, phy_port, len);
- if (phy_port != priv->gemac_port) {
- printf("Rx pkt not on expected port\n");
-- pfe_recv_ack();
- return 0;
- }
-
- // Pass the packet up to the protocol layers.
- net_process_received_packet((uchar *)pkt_buf, len);
-
-- pfe_recv_ack();
- return 0;
- }
-
---
-1.7.9.5
-
diff --git a/package/boot/uboot-layerscape/patches/0044-armv8-fsl-layerscape-Add-support-of-GPIO-structure.patch b/package/boot/uboot-layerscape/patches/0044-armv8-fsl-layerscape-Add-support-of-GPIO-structure.patch
deleted file mode 100644
index 67af942..0000000
--- a/package/boot/uboot-layerscape/patches/0044-armv8-fsl-layerscape-Add-support-of-GPIO-structure.patch
+++ /dev/null
@@ -1,48 +0,0 @@
-From fe0ffa96c83e318d6b99fe31b5d121bdb05247f7 Mon Sep 17 00:00:00 2001
-From: Prabhakar Kushwaha <prabhakar.kushwaha at nxp.com>
-Date: Tue, 24 May 2016 14:52:59 +0530
-Subject: [PATCH 44/93] armv8: fsl-layerscape: Add support of GPIO structure
-
-[context adjustment]
-
-Layerscape supports GPIO registers to conrol GPIO singals.
-
-Add support of GPIO structure to enable GPIO access.
-
-Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha at nxp.com>
-Integrated-by: Jiang Yutang <yutang.jiang at nxp.com>
----
- .../include/asm/arch-fsl-layerscape/immap_lsch2.h | 10 ++++++++++
- 1 file changed, 10 insertions(+)
-
-diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
-index a264f9a..58c7205 100644
---- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
-+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
-@@ -44,6 +44,7 @@
- #define CONFIG_SYS_PPFE_ADDR (CONFIG_SYS_IMMR + 0x3000000)
- #define CONFIG_SYS_SEC_MON_ADDR (CONFIG_SYS_IMMR + 0xe90000)
- #define CONFIG_SYS_SFP_ADDR (CONFIG_SYS_IMMR + 0xe80200)
-+#define CONFIG_SYS_GPIO1_ADDR (CONFIG_SYS_IMMR + 0x300000)
-
- #define CONFIG_SYS_FSL_TIMER_ADDR 0x02b00000
-
-@@ -650,6 +651,15 @@ struct ccsr_cci400 {
- u8 res_e004[0x10000 - 0xe004];
- };
-
-+typedef struct ccsr_gpio {
-+ u32 gpdir;
-+ u32 gpodr;
-+ u32 gpdat;
-+ u32 gpier;
-+ u32 gpimr;
-+ u32 gpicr;
-+} ccsr_gpio_t;
-+
- /* MMU 500 */
- #define SMMU_SCR0 (SMMU_BASE + 0x0)
- #define SMMU_SCR1 (SMMU_BASE + 0x4)
---
-1.7.9.5
-
diff --git a/package/boot/uboot-layerscape/patches/0045-board-freescale-ls1012afrdm-Add-support-of-Ethernet.patch b/package/boot/uboot-layerscape/patches/0045-board-freescale-ls1012afrdm-Add-support-of-Ethernet.patch
deleted file mode 100644
index 0b993cb..0000000
--- a/package/boot/uboot-layerscape/patches/0045-board-freescale-ls1012afrdm-Add-support-of-Ethernet.patch
+++ /dev/null
@@ -1,155 +0,0 @@
-From 691deae097b2583a4e9890307c684ce9f58aca78 Mon Sep 17 00:00:00 2001
-From: Prabhakar Kushwaha <prabhakar.kushwaha at nxp.com>
-Date: Tue, 24 May 2016 15:03:33 +0530
-Subject: [PATCH 45/93] board/freescale/ls1012afrdm: Add support of Ethernet
-
-Add support of SGMII Ethernet present on FRDM board.
-Also add support of PHY reset.
-
-Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha at nxp.com>
----
- board/freescale/ls1012afrdm/Makefile | 1 +
- board/freescale/ls1012afrdm/eth.c | 86 +++++++++++++++++++++++++++++
- board/freescale/ls1012afrdm/ls1012afrdm.c | 5 --
- include/configs/ls1012afrdm.h | 5 ++
- 4 files changed, 92 insertions(+), 5 deletions(-)
- create mode 100644 board/freescale/ls1012afrdm/eth.c
-
-diff --git a/board/freescale/ls1012afrdm/Makefile b/board/freescale/ls1012afrdm/Makefile
-index dbfa2ce..1364f22 100644
---- a/board/freescale/ls1012afrdm/Makefile
-+++ b/board/freescale/ls1012afrdm/Makefile
-@@ -5,3 +5,4 @@
- #
-
- obj-y += ls1012afrdm.o
-+obj-y += eth.o
-diff --git a/board/freescale/ls1012afrdm/eth.c b/board/freescale/ls1012afrdm/eth.c
-new file mode 100644
-index 0000000..8ae3f45
---- /dev/null
-+++ b/board/freescale/ls1012afrdm/eth.c
-@@ -0,0 +1,86 @@
-+/*
-+ * Copyright 2016 Freescale Semiconductor, Inc.
-+ *
-+ * SPDX-License-Identifier: GPL-2.0+
-+ */
-+
-+#include <common.h>
-+#include <asm/io.h>
-+#include <netdev.h>
-+#include <fm_eth.h>
-+#include <fsl_mdio.h>
-+#include <malloc.h>
-+#include <fsl_dtsec.h>
-+#include <asm/arch/soc.h>
-+#include <asm/arch-fsl-layerscape/config.h>
-+#include <asm/arch/fsl_serdes.h>
-+
-+#include "../../../drivers/net/pfe_eth/pfe_eth.h"
-+#include <asm/arch-fsl-layerscape/immap_lsch2.h>
-+
-+#define DEFAULT_PFE_MDIO_NAME "PFE_MDIO"
-+
-+#define MASK_ETH_PHY_RST 0x00000100
-+
-+void reset_phy(void)
-+{
-+ unsigned int val;
-+ ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_GPIO1_ADDR);
-+
-+ setbits_be32(&pgpio->gpdir, MASK_ETH_PHY_RST);
-+
-+ val = in_be32(&pgpio->gpdat);
-+ setbits_be32(&pgpio->gpdat, val & ~MASK_ETH_PHY_RST);
-+ mdelay(10);
-+
-+ val = in_be32(&pgpio->gpdat);
-+ setbits_be32(&pgpio->gpdat, val | MASK_ETH_PHY_RST);
-+ mdelay(50);
-+}
-+
-+int board_eth_init(bd_t *bis)
-+{
-+#ifdef CONFIG_FSL_PPFE
-+ struct mii_dev *bus;
-+ struct mdio_info mac1_mdio_info;
-+ struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
-+
-+
-+ /*TODO Following config should be done for all boards, where is the right place to put this */
-+ out_be32(&scfg->pfeasbcr, in_be32(&scfg->pfeasbcr) | SCFG_PPFEASBCR_AWCACHE0);
-+ out_be32(&scfg->pfebsbcr, in_be32(&scfg->pfebsbcr) | SCFG_PPFEASBCR_AWCACHE0);
-+
-+ /*CCI-400 QoS settings for PFE */
-+ out_be32(&scfg->wr_qos1, 0x0ff00000);
-+ out_be32(&scfg->rd_qos1, 0x0ff00000);
-+
-+ /* Set RGMII into 1G + Full duplex mode */
-+ out_be32(&scfg->rgmiipcr, in_be32(&scfg->rgmiipcr) | (SCFG_RGMIIPCR_SETSP_1000M | SCFG_RGMIIPCR_SETFD));
-+
-+
-+ out_be32((CONFIG_SYS_DCSR_DCFG_ADDR + 0x520), 0xFFFFFFFF);
-+ out_be32((CONFIG_SYS_DCSR_DCFG_ADDR + 0x524), 0xFFFFFFFF);
-+
-+ mac1_mdio_info.reg_base = (void *)0x04200000; /*EMAC1_BASE_ADDR*/
-+ mac1_mdio_info.name = DEFAULT_PFE_MDIO_NAME;
-+
-+ bus = ls1012a_mdio_init(&mac1_mdio_info);
-+ if(!bus)
-+ {
-+ printf("Failed to register mdio \n");
-+ return -1;
-+ }
-+
-+ /*MAC1 */
-+ ls1012a_set_mdio(0, miiphy_get_dev_by_name(DEFAULT_PFE_MDIO_NAME));
-+ ls1012a_set_phy_address_mode(0, EMAC1_PHY_ADDR, PHY_INTERFACE_MODE_SGMII);
-+
-+ /*MAC2 */
-+ ls1012a_set_mdio(1, miiphy_get_dev_by_name(DEFAULT_PFE_MDIO_NAME));
-+ ls1012a_set_phy_address_mode(1, EMAC2_PHY_ADDR, PHY_INTERFACE_MODE_SGMII);
-+
-+
-+ cpu_eth_init(bis);
-+#endif
-+ return pci_eth_init(bis);
-+}
-diff --git a/board/freescale/ls1012afrdm/ls1012afrdm.c b/board/freescale/ls1012afrdm/ls1012afrdm.c
-index 6be8951..6856250 100644
---- a/board/freescale/ls1012afrdm/ls1012afrdm.c
-+++ b/board/freescale/ls1012afrdm/ls1012afrdm.c
-@@ -133,11 +133,6 @@ int dram_init(void)
- return 0;
- }
-
--int board_eth_init(bd_t *bis)
--{
-- return pci_eth_init(bis);
--}
--
- int board_early_init_f(void)
- {
- fsl_lsch2_early_init_f();
-diff --git a/include/configs/ls1012afrdm.h b/include/configs/ls1012afrdm.h
-index 3231ab7..5e619c1 100644
---- a/include/configs/ls1012afrdm.h
-+++ b/include/configs/ls1012afrdm.h
-@@ -18,8 +18,13 @@
- #define CONFIG_SYS_MEMTEST_START 0x80000000
- #define CONFIG_SYS_MEMTEST_END 0x9fffffff
-
-+#ifdef CONFIG_FSL_PPFE
-+#define EMAC1_PHY_ADDR 0x2
-+#define EMAC2_PHY_ADDR 0x1
- #define CONFIG_PHYLIB
- #define CONFIG_PHY_REALTEK
-+#define CONFIG_RESET_PHY_R
-+#endif
- /*
- * USB
- */
---
-1.7.9.5
-
diff --git a/package/boot/uboot-layerscape/patches/0046-Correcting-address-for-PFE-Driver.patch b/package/boot/uboot-layerscape/patches/0046-Correcting-address-for-PFE-Driver.patch
deleted file mode 100644
index 3514579..0000000
--- a/package/boot/uboot-layerscape/patches/0046-Correcting-address-for-PFE-Driver.patch
+++ /dev/null
@@ -1,29 +0,0 @@
-From ff5e4bb56636eb807f653a0e1ce5c7c721543e01 Mon Sep 17 00:00:00 2001
-From: Pratiyush Mohan Srivastava <pratiyush.srivastava at nxp.com>
-Date: Wed, 25 May 2016 17:57:25 +0530
-Subject: [PATCH 46/93] Correcting address for PFE Driver
-
-[context adjustment]
-
-Signed-off-by: Pratiyush Mohan Srivastava <pratiyush.srivastava at nxp.com>
-Integrated-by: Jiang Yutang <yutang.jiang at nxp.com>
----
- .../include/asm/arch-fsl-layerscape/immap_lsch2.h | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
-diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
-index 58c7205..a7bc2a4 100644
---- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
-+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
-@@ -44,7 +44,7 @@
- #define CONFIG_SYS_PPFE_ADDR (CONFIG_SYS_IMMR + 0x3000000)
- #define CONFIG_SYS_SEC_MON_ADDR (CONFIG_SYS_IMMR + 0xe90000)
- #define CONFIG_SYS_SFP_ADDR (CONFIG_SYS_IMMR + 0xe80200)
--#define CONFIG_SYS_GPIO1_ADDR (CONFIG_SYS_IMMR + 0x300000)
-+#define CONFIG_SYS_GPIO1_ADDR (CONFIG_SYS_IMMR + 0x1300000)
-
- #define CONFIG_SYS_FSL_TIMER_ADDR 0x02b00000
-
---
-1.7.9.5
-
diff --git a/package/boot/uboot-layerscape/patches/0047-Enable-second-SGMII-1G-interface.patch b/package/boot/uboot-layerscape/patches/0047-Enable-second-SGMII-1G-interface.patch
deleted file mode 100644
index 79e3f40..0000000
--- a/package/boot/uboot-layerscape/patches/0047-Enable-second-SGMII-1G-interface.patch
+++ /dev/null
@@ -1,61 +0,0 @@
-From 61bb1dceefdb4c08ff69e7e40a766a404421206f Mon Sep 17 00:00:00 2001
-From: Pratiyush Mohan Srivastava <pratiyush.srivastava at nxp.com>
-Date: Fri, 27 May 2016 13:16:43 +0530
-Subject: [PATCH 47/93] Enable second SGMII 1G interface
-
-Enable second SGMII 1G interface on LS1012A Freedom Board
-
-Signed-off-by: Pratiyush Mohan Srivastava <pratiyush.srivastava at nxp.com>
----
- board/freescale/ls1012afrdm/eth.c | 14 ++++++++++++++
- drivers/net/pfe_eth/pfe_eth.c | 2 +-
- 2 files changed, 15 insertions(+), 1 deletion(-)
-
-diff --git a/board/freescale/ls1012afrdm/eth.c b/board/freescale/ls1012afrdm/eth.c
-index 8ae3f45..90ed66b 100644
---- a/board/freescale/ls1012afrdm/eth.c
-+++ b/board/freescale/ls1012afrdm/eth.c
-@@ -19,6 +19,7 @@
- #include <asm/arch-fsl-layerscape/immap_lsch2.h>
-
- #define DEFAULT_PFE_MDIO_NAME "PFE_MDIO"
-+#define DEFAULT_PFE_MDIO1_NAME "PFE_MDIO1"
-
- #define MASK_ETH_PHY_RST 0x00000100
-
-@@ -71,6 +72,19 @@ int board_eth_init(bd_t *bis)
- return -1;
- }
-
-+ /*We don't really need this MDIO bus,
-+ * this is called just to initialize EMAC2 MDIO interface*/
-+ mac1_mdio_info.reg_base = (void *)0x04220000; /*EMAC2_BASE_ADDR*/
-+ mac1_mdio_info.name = DEFAULT_PFE_MDIO1_NAME;
-+
-+ bus = ls1012a_mdio_init(&mac1_mdio_info);
-+ if(!bus)
-+ {
-+ printf("Failed to register mdio \n");
-+ return -1;
-+ }
-+
-+
- /*MAC1 */
- ls1012a_set_mdio(0, miiphy_get_dev_by_name(DEFAULT_PFE_MDIO_NAME));
- ls1012a_set_phy_address_mode(0, EMAC1_PHY_ADDR, PHY_INTERFACE_MODE_SGMII);
-diff --git a/drivers/net/pfe_eth/pfe_eth.c b/drivers/net/pfe_eth/pfe_eth.c
-index 40f2c39..4aa318d 100644
---- a/drivers/net/pfe_eth/pfe_eth.c
-+++ b/drivers/net/pfe_eth/pfe_eth.c
-@@ -348,7 +348,7 @@ static void ls1012a_configure_serdes(struct ls1012a_eth_dev *priv)
-
- printf("%s %d\n", __func__, priv->gemac_port);
- /* PCS configuration done with corresponding GEMAC */
-- bus.priv = priv->gem->gemac_base;
-+ bus.priv = gem_info[priv->gemac_port].gemac_base;
-
- ls1012a_phy_read(&bus, 0, MDIO_DEVAD_NONE, 0x0);
- ls1012a_phy_read(&bus, 0, MDIO_DEVAD_NONE, 0x1);
---
-1.7.9.5
-
diff --git a/package/boot/uboot-layerscape/patches/0048-armv8-ls1012a-enable-sdhc2-support.patch b/package/boot/uboot-layerscape/patches/0048-armv8-ls1012a-enable-sdhc2-support.patch
deleted file mode 100644
index 5076153..0000000
--- a/package/boot/uboot-layerscape/patches/0048-armv8-ls1012a-enable-sdhc2-support.patch
+++ /dev/null
@@ -1,44 +0,0 @@
-From a75fda9a1a7d635d1714df52068cc9fb7988e2c7 Mon Sep 17 00:00:00 2001
-From: Yangbo Lu <yangbo.lu at nxp.com>
-Date: Fri, 3 Jun 2016 11:40:09 +0800
-Subject: [PATCH 48/93] armv8: ls1012a: enable sdhc2 support
-
-A previous patch shifting board specific configurations missed
-the sdhc2 support. This patch is to fix it.
-
-Fixes: df5f76d71e30 ("Shift board specific configurations")
-Signed-off-by: Yangbo Lu <yangbo.lu at nxp.com>
----
- include/configs/ls1012aqds.h | 2 ++
- include/configs/ls1012ardb.h | 2 ++
- 2 files changed, 4 insertions(+)
-
-diff --git a/include/configs/ls1012aqds.h b/include/configs/ls1012aqds.h
-index 1fa7b6f..cc8e0fc 100644
---- a/include/configs/ls1012aqds.h
-+++ b/include/configs/ls1012aqds.h
-@@ -30,6 +30,8 @@
- #ifdef CONFIG_MMC
- #define CONFIG_CMD_MMC
- #define CONFIG_FSL_ESDHC
-+#define CONFIG_FSL_ESDHC_TWO_CONTROLLERS_SUPPORT
-+#define CONFIG_FSL_ESDHC_1_NON_REMOVABLE_CARD
- #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
- #define CONFIG_GENERIC_MMC
- #define CONFIG_CMD_FAT
-diff --git a/include/configs/ls1012ardb.h b/include/configs/ls1012ardb.h
-index 23722e0..2eee84a 100644
---- a/include/configs/ls1012ardb.h
-+++ b/include/configs/ls1012ardb.h
-@@ -64,6 +64,8 @@
- #ifdef CONFIG_MMC
- #define CONFIG_CMD_MMC
- #define CONFIG_FSL_ESDHC
-+#define CONFIG_FSL_ESDHC_TWO_CONTROLLERS_SUPPORT
-+#define CONFIG_FSL_ESDHC_1_NON_REMOVABLE_CARD
- #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
- #define CONFIG_GENERIC_MMC
- #define CONFIG_CMD_FAT
---
-1.7.9.5
-
diff --git a/package/boot/uboot-layerscape/patches/0049-DNCPE-296-PFE-reset-woraround-fix.patch b/package/boot/uboot-layerscape/patches/0049-DNCPE-296-PFE-reset-woraround-fix.patch
deleted file mode 100644
index 0a4e80c..0000000
--- a/package/boot/uboot-layerscape/patches/0049-DNCPE-296-PFE-reset-woraround-fix.patch
+++ /dev/null
@@ -1,327 +0,0 @@
-From 1b9cf577511123dd05e1d3b1fe7fd5db43b6097f Mon Sep 17 00:00:00 2001
-From: Anji J <anji.jagarlmudi at freescale.com>
-Date: Wed, 25 May 2016 13:40:13 +0530
-Subject: [PATCH 49/93] DNCPE-296 PFE reset woraround fix
-
-- Linux driver depends on U-boot TMU initialization,
- but U-boot tmu initialization is not as expected by Linux driver.
-- Align U-boot TMU initialization with Linux driver
-- LLM base address in DDR changed to match with Linux driver expectation.
-- Remove unwanted pfe_mod.h
-- Start PFE/network at bootup time.
----
- common/cmd_pfe_commands.c | 9 +-
- drivers/net/pfe_eth/pfe.c | 16 ++--
- drivers/net/pfe_eth/pfe/cbus/tmu_csr.h | 7 ++
- drivers/net/pfe_eth/pfe_eth.h | 9 +-
- drivers/net/pfe_eth/pfe_mod.h | 140 --------------------------------
- include/configs/ls1012a_common.h | 1 -
- 6 files changed, 24 insertions(+), 158 deletions(-)
- delete mode 100644 drivers/net/pfe_eth/pfe_mod.h
-
-diff --git a/common/cmd_pfe_commands.c b/common/cmd_pfe_commands.c
-index 0e22097..ca479d7 100644
---- a/common/cmd_pfe_commands.c
-+++ b/common/cmd_pfe_commands.c
-@@ -932,7 +932,7 @@ static void send_dummy_pkt_to_hif(void)
- /*Allocate BMU2 buffer */
- buf = readl(BMU2_BASE_ADDR + BMU_ALLOC_CTRL);
-
-- printf("Sending a dummy pkt to HIF %x\n", buf);
-+ debug("Sending a dummy pkt to HIF %x\n", buf);
- buf += 0x80;
- memcpy((void *)DDR_PFE_TO_VIRT(buf), dummy_pkt, sizeof(dummy_pkt));
- /*Write length and pkt to TMU*/
-@@ -945,14 +945,13 @@ static void pfe_command_stop(int argc, char * const argv[])
- {
- int id;
- u32 rx_status;
-- printf("Stopping PFE \n");
-+ printf("Stopping PFE... \n");
-
- /*Mark all descriptors as LAST_BD */
- hif_rx_desc_disable();
-
- /*If HIF Rx BDP is busy send a dummy packet */
- rx_status = readl(HIF_RX_STATUS);
-- printf("rx_status %x %x\n",rx_status, BDP_CSR_RX_DMA_ACTV);
- if(rx_status & BDP_CSR_RX_DMA_ACTV)
- send_dummy_pkt_to_hif();
- udelay(10);
-@@ -964,12 +963,10 @@ static void pfe_command_stop(int argc, char * const argv[])
-
- for (id = CLASS0_ID; id <= CLASS_MAX_ID; id++)
- {
-- printf("Stop %d\n", id);
- /*Inform PE to stop */
- pe_dmem_write(id, cpu_to_be32(1), PEMBOX_ADDR_CLASS, 4);
- udelay(10);
-
-- printf("Reading %d\n", id);
- /*Read status */
- if(!pe_dmem_read(id, PEMBOX_ADDR_CLASS+4, 4))
- printf("Failed to stop PE%d\n", id);
-@@ -979,12 +976,10 @@ static void pfe_command_stop(int argc, char * const argv[])
- {
- if(id == TMU2_ID) continue;
-
-- printf("Stop %d\n", id);
- /*Inform PE to stop */
- pe_dmem_write(id, 1, PEMBOX_ADDR_TMU, 4);
- udelay(10);
-
-- printf("Reading %d\n", id);
- /*Read status */
- if(!pe_dmem_read(id, PEMBOX_ADDR_TMU+4, 4))
- printf("Failed to stop PE%d\n", id);
-diff --git a/drivers/net/pfe_eth/pfe.c b/drivers/net/pfe_eth/pfe.c
-index 3b5570a..2c31cad 100644
---- a/drivers/net/pfe_eth/pfe.c
-+++ b/drivers/net/pfe_eth/pfe.c
-@@ -1489,17 +1489,16 @@ void tmu_init(TMU_CFG *cfg)
- writel(0x3FF, TMU_TDQ2_SCH_CTRL);
- #endif
- writel(0x3FF, TMU_TDQ3_SCH_CTRL);
--
--
-+
- if (PLL_CLK_EN == 0)
- writel(0x0, TMU_PE_SYS_CLK_RATIO); // Clock ratio: for 1:1 the value is 0
- else
- writel(0x1, TMU_PE_SYS_CLK_RATIO); // Clock ratio: for 1:2 the value is 1
-
-- //printf("TMU_LLM_BASE_ADDR %x\n", cfg->llm_base_addr);
-+ debug("TMU_LLM_BASE_ADDR %x\n", cfg->llm_base_addr);
- writel(cfg->llm_base_addr, TMU_LLM_BASE_ADDR); // Extra packet pointers will be stored from this address onwards
--
-- //printf("TMU_LLM_QUE_LEN %x\n", cfg->llm_queue_len);
-+
-+ debug("TMU_LLM_QUE_LEN %x\n", cfg->llm_queue_len);
- writel(cfg->llm_queue_len, TMU_LLM_QUE_LEN);
- writel(5, TMU_TDQ_IIFG_CFG);
- writel(DDR_BUF_SIZE, TMU_BMU_BUF_SIZE);
-@@ -1531,7 +1530,12 @@ void tmu_init(TMU_CFG *cfg)
- u32 qmax;
- writel((phyno << 8) | q, TMU_TEQ_CTRL);
- writel(1 << 22, TMU_TEQ_QCFG);
-- qmax = ((phyno == 3) || (q < 8)) ? 255 : 127;
-+
-+ if (phyno == 3)
-+ qmax = DEFAULT_TMU3_QDEPTH;
-+ else
-+ qmax = (q == 0) ? DEFAULT_Q0_QDEPTH : DEFAULT_MAX_QDEPTH;
-+
- writel(qmax << 18, TMU_TEQ_HW_PROB_CFG2);
- writel(qmax >> 14, TMU_TEQ_HW_PROB_CFG3);
- }
-diff --git a/drivers/net/pfe_eth/pfe/cbus/tmu_csr.h b/drivers/net/pfe_eth/pfe/cbus/tmu_csr.h
-index cbcbb1f..64fad04 100644
---- a/drivers/net/pfe_eth/pfe/cbus/tmu_csr.h
-+++ b/drivers/net/pfe_eth/pfe/cbus/tmu_csr.h
-@@ -93,10 +93,17 @@
- #define MEM_INIT_DONE (1 << 7)
- #define LLM_INIT (1 << 8)
- #define LLM_INIT_DONE (1 << 9)
-+#define ECC_MEM_INIT_DONE (1<<10)
-
- typedef struct {
- u32 llm_base_addr;
- u32 llm_queue_len;
- } TMU_CFG;
-
-+/* Not HW related for pfe_ctrl / pfe common defines */
-+#define DEFAULT_MAX_QDEPTH 80
-+#define DEFAULT_Q0_QDEPTH 511 //We keep one large queue for host tx qos
-+#define DEFAULT_TMU3_QDEPTH 127
-+
-+
- #endif /* _TMU_CSR_H_ */
-diff --git a/drivers/net/pfe_eth/pfe_eth.h b/drivers/net/pfe_eth/pfe_eth.h
-index dfcc00e..c16b8c0 100644
---- a/drivers/net/pfe_eth/pfe_eth.h
-+++ b/drivers/net/pfe_eth/pfe_eth.h
-@@ -39,11 +39,8 @@
- #define BMU2_BUF_COUNT (3 * SZ_1K)
- #define BMU2_DDR_SIZE (DDR_BUF_SIZE * BMU2_BUF_COUNT)
-
--#define TMU_LLM_BASEADDR (BMU2_DDR_BASEADDR + BMU2_DDR_SIZE)
--#define TMU_LLM_QUEUE_LEN (16 * 256) /**< Must be power of two and at least 16 * 8 = 128 bytes */
--#define TMU_LLM_SIZE (4 * 16 * TMU_LLM_QUEUE_LEN) /**< (4 TMU's x 16 queues x queue_len) */
-
--#define HIF_RX_PKT_DDR_BASEADDR (TMU_LLM_BASEADDR + TMU_LLM_SIZE)
-+#define HIF_RX_PKT_DDR_BASEADDR (BMU2_DDR_BASEADDR + BMU2_DDR_SIZE)
- #define HIF_RX_PKT_DDR_SIZE (HIF_RX_DESC_NT * DDR_BUF_SIZE)
- #define HIF_TX_PKT_DDR_BASEADDR (HIF_RX_PKT_DDR_BASEADDR + HIF_RX_PKT_DDR_SIZE)
- #define HIF_TX_PKT_DDR_SIZE (HIF_TX_DESC_NT * DDR_BUF_SIZE)
-@@ -72,6 +69,10 @@
- #define TMU_DDR_DATA_BASEADDR (CLASS_DDR_DATA_BASEADDR + CLASS_DDR_DATA_SIZE)
- #define TMU_DDR_DATA_SIZE (32 * SZ_1K)
-
-+#define TMU_LLM_BASEADDR (TMU_DDR_DATA_BASEADDR + TMU_DDR_DATA_SIZE)
-+#define TMU_LLM_QUEUE_LEN (16 * 256) /**< Must be power of two and at least 16 * 8 = 128 bytes */
-+#define TMU_LLM_SIZE (4 * 16 * TMU_LLM_QUEUE_LEN) /**< (4 TMU's x 16 queues x queue_len) */
-+
- //#define ROUTE_TABLE_BASEADDR (TMU_DDR_DATA_BASEADDR + TMU_DDR_DATA_SIZE)
- #define ROUTE_TABLE_BASEADDR 0x800000
- #define ROUTE_TABLE_HASH_BITS_MAX 15 /**< 32K entries */
-diff --git a/drivers/net/pfe_eth/pfe_mod.h b/drivers/net/pfe_eth/pfe_mod.h
-deleted file mode 100644
-index 9436b72..0000000
---- a/drivers/net/pfe_eth/pfe_mod.h
-+++ /dev/null
-@@ -1,140 +0,0 @@
--/*
-- * (C) Copyright 2011
-- * Author : Mindspeed Technologes
-- *
-- * See file CREDITS for list of people who contributed to this
-- * project.
-- *
-- * This program is free software; you can redistribute it and/or
-- * modify it under the terms of the GNU General Public License as
-- * published by the Free Software Foundation; either version 2 of
-- * the License, or (at your option) any later version.
-- *
-- * This program is distributed in the hope that it will be useful,
-- * but WITHOUT ANY WARRANTY; without even the implied warranty of
-- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- * GNU General Public License for more details.
-- *
-- * You should have received a copy of the GNU General Public License
-- * along with this program; if not, write to the Free Software
-- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-- * MA 02111-1307 USA
-- * */
--
--
--#ifndef _PFE_MOD_H_
--#define _PFE_MOD_H_
--
--#include <linux/device.h>
--
--#include "pfe/pfe.h"
--#include "pfe/cbus.h"
--#include "pfe/cbus/bmu.h"
--
--#include "pfe_driver.h"
--
--struct pfe;
--
--
--struct pfe {
-- unsigned long ddr_phys_baseaddr;
-- void *ddr_baseaddr;
-- void *cbus_baseaddr;
-- void *apb_baseaddr;
-- void *iram_baseaddr;
-- int hif_irq;
-- struct device *dev;
-- struct pci_dev *pdev;
--
--#if 0
-- struct pfe_ctrl ctrl;
-- struct pfe_hif hif;
-- struct pfe_eth eth;
--#endif
--};
--
--extern struct pfe *pfe;
--
--int pfe_probe(struct pfe *pfe);
--int pfe_remove(struct pfe *pfe);
--
--#ifndef SZ_1K
--#define SZ_1K 1024
--#endif
--
--#ifndef SZ_1M
--#define SZ_1M (1024 * 1024)
--#endif
--
--/* DDR Mapping */
--#if !defined(CONFIG_PLATFORM_PCI)
--#define UTIL_CODE_BASEADDR 0
--#define UTIL_CODE_SIZE (128 * SZ_1K)
--#define UTIL_DDR_DATA_BASEADDR (UTIL_CODE_BASEADDR + UTIL_CODE_SIZE)
--#define UTIL_DDR_DATA_SIZE (64 * SZ_1K)
--#define CLASS_DDR_DATA_BASEADDR (UTIL_DDR_DATA_BASEADDR + UTIL_DDR_DATA_SIZE)
--#define CLASS_DDR_DATA_SIZE (32 * SZ_1K)
--#define TMU_DDR_DATA_BASEADDR (CLASS_DDR_DATA_BASEADDR + CLASS_DDR_DATA_SIZE)
--#define TMU_DDR_DATA_SIZE (32 * SZ_1K)
--#define ROUTE_TABLE_BASEADDR (TMU_DDR_DATA_BASEADDR + TMU_DDR_DATA_SIZE)
--#define ROUTE_TABLE_HASH_BITS 15 /**< 32K entries */
--#define ROUTE_TABLE_SIZE ((1 << ROUTE_TABLE_HASH_BITS) * CLASS_ROUTE_SIZE)
--#define BMU2_DDR_BASEADDR (ROUTE_TABLE_BASEADDR + ROUTE_TABLE_SIZE)
--#define BMU2_BUF_COUNT (4096 - 256) /**< This is to get a total DDR size of 12MiB */
--#define BMU2_DDR_SIZE (DDR_BUF_SIZE * BMU2_BUF_COUNT)
--#define TMU_LLM_BASEADDR (BMU2_DDR_BASEADDR + BMU2_DDR_SIZE)
--#define TMU_LLM_QUEUE_LEN (16 * 256) /**< Must be power of two and at least 16 * 8 = 128 bytes */
--#define TMU_LLM_SIZE (4 * 16 * TMU_LLM_QUEUE_LEN) /**< (4 TMU's x 16 queues x queue_len) */
--
--#if (TMU_LLM_BASEADDR + TMU_LLM_SIZE) > 0xC00000
--#error DDR mapping above 12MiB
--#endif
--
--#else
--
--#define UTIL_CODE_BASEADDR 0
--#if defined(CONFIG_UTIL_PE_DISABLED)
--#define UTIL_CODE_SIZE (0 * SZ_1K)
--#else
--#define UTIL_CODE_SIZE (8 * SZ_1K)
--#endif
--#define UTIL_DDR_DATA_BASEADDR (UTIL_CODE_BASEADDR + UTIL_CODE_SIZE)
--#define UTIL_DDR_DATA_SIZE (0 * SZ_1K)
--#define CLASS_DDR_DATA_BASEADDR (UTIL_DDR_DATA_BASEADDR + UTIL_DDR_DATA_SIZE)
--#define CLASS_DDR_DATA_SIZE (0 * SZ_1K)
--#define TMU_DDR_DATA_BASEADDR (CLASS_DDR_DATA_BASEADDR + CLASS_DDR_DATA_SIZE)
--#define TMU_DDR_DATA_SIZE (0 * SZ_1K)
--#define ROUTE_TABLE_BASEADDR (TMU_DDR_DATA_BASEADDR + TMU_DDR_DATA_SIZE)
--#define ROUTE_TABLE_HASH_BITS 5 /**< 32 entries */
--#define ROUTE_TABLE_SIZE ((1 << ROUTE_TABLE_HASH_BITS) * CLASS_ROUTE_SIZE)
--#define BMU2_DDR_BASEADDR (ROUTE_TABLE_BASEADDR + ROUTE_TABLE_SIZE)
--#define BMU2_BUF_COUNT 8
--#define BMU2_DDR_SIZE (DDR_BUF_SIZE * BMU2_BUF_COUNT)
--#define TMU_LLM_BASEADDR (BMU2_DDR_BASEADDR + BMU2_DDR_SIZE)
--#define TMU_LLM_QUEUE_LEN (16 * 8) /**< Must be power of two and at least 16 * 8 = 128 bytes */
--#define TMU_LLM_SIZE (4 * 16 * TMU_LLM_QUEUE_LEN) /**< (4 TMU's x 16 queues x queue_len) */
--#define HIF_DESC_BASEADDR (TMU_LLM_BASEADDR + TMU_LLM_SIZE)
--#define HIF_RX_DESC_SIZE (16*HIF_RX_DESC_NT)
--#define HIF_TX_DESC_SIZE (16*HIF_TX_DESC_NT)
--#define HIF_DESC_SIZE (HIF_RX_DESC_SIZE + HIF_TX_DESC_SIZE)
--#define HIF_RX_PKT_DDR_BASEADDR (HIF_DESC_BASEADDR + HIF_DESC_SIZE)
--#define HIF_RX_PKT_DDR_SIZE (HIF_RX_DESC_NT * DDR_BUF_SIZE)
--#define HIF_TX_PKT_DDR_BASEADDR (HIF_RX_PKT_DDR_BASEADDR + HIF_RX_PKT_DDR_SIZE)
--#define HIF_TX_PKT_DDR_SIZE (HIF_TX_DESC_NT * DDR_BUF_SIZE)
--#define ROUTE_BASEADDR (HIF_TX_PKT_DDR_BASEADDR + HIF_TX_PKT_DDR_SIZE)
--#define ROUTE_SIZE (2 * CLASS_ROUTE_SIZE)
--
--#if (ROUTE_BASEADDR + ROUTE_SIZE) > 0x10000
--#error DDR mapping above 64KiB
--#endif
--
--#define PFE_HOST_TO_PCI(addr) (((u32)addr)- ((u32)DDR_BASE_ADDR))
--#define PFE_PCI_TO_HOST(addr) (((u32)addr)+ ((u32)DDR_BASE_ADDR))
--#endif
--
--/* LMEM Mapping */
--#define BMU1_LMEM_BASEADDR 0
--#define BMU1_BUF_COUNT 256
--#define BMU1_LMEM_SIZE (LMEM_BUF_SIZE * BMU1_BUF_COUNT)
--
--#endif /* _PFE_MOD_H */
-diff --git a/include/configs/ls1012a_common.h b/include/configs/ls1012a_common.h
-index 3c4ab6c..57fc057 100644
---- a/include/configs/ls1012a_common.h
-+++ b/include/configs/ls1012a_common.h
-@@ -113,7 +113,6 @@
- #define CONFIG_FSL_PPFE
-
- #ifdef CONFIG_FSL_PPFE
--#define CONFIG_CMD_PFE_START
- #define CONFIG_CMD_PFE_COMMANDS
- #define CONFIG_UTIL_PE_DISABLED
-
---
-1.7.9.5
-
diff --git a/package/boot/uboot-layerscape/patches/0050-DNCPE-138-Rest-external-PHYs-before-driver-starts.patch b/package/boot/uboot-layerscape/patches/0050-DNCPE-138-Rest-external-PHYs-before-driver-starts.patch
deleted file mode 100644
index 0694f6f..0000000
--- a/package/boot/uboot-layerscape/patches/0050-DNCPE-138-Rest-external-PHYs-before-driver-starts.patch
+++ /dev/null
@@ -1,54 +0,0 @@
-From 101bee08b8441f279df657d4a45868de3f976c0c Mon Sep 17 00:00:00 2001
-From: Anji J <anji.jagarlmudi at freescale.com>
-Date: Thu, 26 May 2016 15:58:48 +0530
-Subject: [PATCH 50/93] DNCPE-138 Rest external PHYs before driver starts
-
-- Disable CONFIG_RESET_PHY_R, it is resetting PHYs after driver started.
-- Call reset_phy() before driver initialization.
-- Update bootcmd to stop pfe before kernel starts.
----
- board/freescale/ls1012ardb/eth.c | 1 +
- include/configs/ls1012a_common.h | 2 +-
- include/configs/ls1012ardb.h | 1 -
- 3 files changed, 2 insertions(+), 2 deletions(-)
-
-diff --git a/board/freescale/ls1012ardb/eth.c b/board/freescale/ls1012ardb/eth.c
-index 24fdd83..638db95 100644
---- a/board/freescale/ls1012ardb/eth.c
-+++ b/board/freescale/ls1012ardb/eth.c
-@@ -41,6 +41,7 @@ int board_eth_init(bd_t *bis)
- struct mdio_info mac1_mdio_info;
- struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
-
-+ reset_phy();
-
- /*TODO Following config should be done for all boards, where is the right place to put this */
- out_be32(&scfg->pfeasbcr, in_be32(&scfg->pfeasbcr) | SCFG_PPFEASBCR_AWCACHE0);
-diff --git a/include/configs/ls1012a_common.h b/include/configs/ls1012a_common.h
-index 57fc057..2895e7a 100644
---- a/include/configs/ls1012a_common.h
-+++ b/include/configs/ls1012a_common.h
-@@ -152,7 +152,7 @@
- #else
- #define CONFIG_BOOTARGS "console=ttyS0,115200 root=/dev/ram0 " \
- "earlycon=uart8250,mmio,0x21c0500"
--#define CONFIG_BOOTCOMMAND "sf probe 0:0; sf read $kernel_load "\
-+#define CONFIG_BOOTCOMMAND "pfe stop; sf probe 0:0; sf read $kernel_load "\
- "$kernel_start $kernel_size && "\
- "bootm $kernel_load"
- #endif
-diff --git a/include/configs/ls1012ardb.h b/include/configs/ls1012ardb.h
-index 2eee84a..e94df74 100644
---- a/include/configs/ls1012ardb.h
-+++ b/include/configs/ls1012ardb.h
-@@ -24,7 +24,6 @@
- #define EMAC2_PHY_ADDR 0x1
- #define CONFIG_PHYLIB
- #define CONFIG_PHY_REALTEK
--#define CONFIG_RESET_PHY_R
- #endif
-
- /*
---
-1.7.9.5
-
diff --git a/package/boot/uboot-layerscape/patches/0051-PPFE-warnings-Fix.patch b/package/boot/uboot-layerscape/patches/0051-PPFE-warnings-Fix.patch
deleted file mode 100644
index 5397616..0000000
--- a/package/boot/uboot-layerscape/patches/0051-PPFE-warnings-Fix.patch
+++ /dev/null
@@ -1,283 +0,0 @@
-From 4332e5748301df5b608f894e451999f873bda307 Mon Sep 17 00:00:00 2001
-From: Bhaskar Upadhaya <Bhaskar.Upadhaya at freescale.com>
-Date: Wed, 1 Jun 2016 05:18:38 +0530
-Subject: [PATCH 51/93] PPFE warnings Fix
-
-Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya at freescale.com>
----
- Makefile | 1 +
- arch/arm/cpu/armv8/fsl-layerscape/cpu.c | 1 +
- board/freescale/ls1012aqds/eth.c | 4 ++--
- board/freescale/ls1012ardb/eth.c | 1 +
- common/cmd_pfe_commands.c | 7 +++++--
- drivers/net/pfe_eth/pfe.c | 7 ++++---
- drivers/net/pfe_eth/pfe/pfe.h | 2 +-
- drivers/net/pfe_eth/pfe_driver.c | 8 ++++----
- drivers/net/pfe_eth/pfe_eth.c | 7 +------
- drivers/net/pfe_eth/pfe_eth.h | 6 +++++-
- drivers/net/pfe_eth/pfe_firmware.c | 2 +-
- 11 files changed, 26 insertions(+), 20 deletions(-)
-
-diff --git a/Makefile b/Makefile
-index 100de92..1c2818c 100644
---- a/Makefile
-+++ b/Makefile
-@@ -612,6 +612,7 @@ UBOOTINCLUDE := \
- $(if $(CONFIG_SYS_THUMB_BUILD), $(if $(CONFIG_HAS_THUMB2),, \
- -I$(srctree)/arch/$(ARCH)/thumb1/include),) \
- -I$(srctree)/arch/$(ARCH)/include \
-+ -I$(srctree)/drivers/net/pfe_eth \
- -include $(srctree)/include/linux/kconfig.h
-
- NOSTDINC_FLAGS += -nostdinc -isystem $(shell $(CC) -print-file-name=include)
-diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
-index 8f59577..bfd7078 100644
---- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
-+++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
-@@ -20,6 +20,7 @@
- #include <fm_eth.h>
- #include <fsl_debug_server.h>
- #include <fsl-mc/fsl_mc.h>
-+#include <pfe_eth.h>
- #ifdef CONFIG_FSL_ESDHC
- #include <fsl_esdhc.h>
- #endif
-diff --git a/board/freescale/ls1012aqds/eth.c b/board/freescale/ls1012aqds/eth.c
-index 1bd7c9d..6fbbdbe 100644
---- a/board/freescale/ls1012aqds/eth.c
-+++ b/board/freescale/ls1012aqds/eth.c
-@@ -27,8 +27,6 @@
-
- #define DEFAULT_PFE_MDIO_NAME "PFE_MDIO"
-
--static int mdio_mux[NUM_FM_PORTS];
--
- static const char * const mdio_names[] = {
- "NULL",
- "LS1012AQDS_MDIO_RGMII",
-@@ -85,6 +83,8 @@ static int ls1012aqds_mdio_reset(struct mii_dev *bus)
-
- if(priv->realbus->reset)
- return priv->realbus->reset(priv->realbus);
-+ else
-+ return -1;
- }
-
- static int ls1012aqds_mdio_init(char *realbusname, u8 muxval)
-diff --git a/board/freescale/ls1012ardb/eth.c b/board/freescale/ls1012ardb/eth.c
-index 638db95..7b0e450 100644
---- a/board/freescale/ls1012ardb/eth.c
-+++ b/board/freescale/ls1012ardb/eth.c
-@@ -17,6 +17,7 @@
-
- #include "../../../drivers/net/pfe_eth/pfe_eth.h"
- #include <asm/arch-fsl-layerscape/immap_lsch2.h>
-+#include <i2c.h>
-
- #define DEFAULT_PFE_MDIO_NAME "PFE_MDIO"
-
-diff --git a/common/cmd_pfe_commands.c b/common/cmd_pfe_commands.c
-index ca479d7..84999a6 100644
---- a/common/cmd_pfe_commands.c
-+++ b/common/cmd_pfe_commands.c
-@@ -602,7 +602,6 @@ void bmu(int id, void *base)
- static void pfe_pe_status(int argc, char * const argv[])
- {
- int do_clear = 0;
-- int j;
- u32 id;
- u32 dmem_addr;
- u32 cpu_state;
-@@ -612,9 +611,11 @@ static void pfe_pe_status(int argc, char * const argv[])
- u32 drop;
- char statebuf[5];
- u32 class_debug_reg = 0;
-+#ifdef CONFIG_PFE_WARN_WA
- u32 debug_indicator;
- u32 debug[16];
--
-+ int j;
-+#endif
- if (argc == 4 && strcmp(argv[3], "clear") == 0)
- do_clear = 1;
-
-@@ -684,6 +685,7 @@ static void pfe_pe_status(int argc, char * const argv[])
- statebuf, cpu_to_be32(activity_counter),
- cpu_to_be32(rx), cpu_to_be32(tx), cpu_to_be32(drop));
- }
-+#ifdef CONFIG_PFE_WARN_WA
- debug_indicator = pe_dmem_read(id, dmem_addr, 4);
- dmem_addr += 4;
- if (debug_indicator == cpu_to_be32('DBUG'))
-@@ -705,6 +707,7 @@ static void pfe_pe_status(int argc, char * const argv[])
- printf("%08x%s", cpu_to_be32(debug[j]), (j & 0x7) == 0x7 || j == last - 1 ? "\n" : " ");
- }
- }
-+#endif
- }
-
- }
-diff --git a/drivers/net/pfe_eth/pfe.c b/drivers/net/pfe_eth/pfe.c
-index 2c31cad..94cfe4e 100644
---- a/drivers/net/pfe_eth/pfe.c
-+++ b/drivers/net/pfe_eth/pfe.c
-@@ -368,6 +368,7 @@ void pe_lmem_write(u32 *src, u32 len, u32 offset)
- class_bus_write(*src, PE_LMEM_BASE_ADDR + offset, (len & 0x03));
- }
-
-+#if !defined(CONFIG_UTIL_PE_DISABLED)
- /** Writes UTIL program memory (DDR) from the host.
- *
- * @param[in] addr Address to write (virtual, must be aligned on size)
-@@ -413,7 +414,7 @@ static void util_pmem_memcpy(void *dst, const void *src, unsigned int len)
- if (len & 0x2)
- util_pmem_write(*(u16 *)src, dst, len & 0x2);
- }
--
-+#endif
-
- /** Loads an elf section into pmem
- * Code needs to be at least 16bit aligned and only PROGBITS sections are supported
-@@ -581,7 +582,7 @@ static int pe_load_ddr_section(int id, const void *data, Elf32_Shdr *shdr)
- return -1;
- }
-
-- memcpy(DDR_PFE_TO_VIRT(addr), data + offset, size);
-+ memcpy((void *)DDR_PFE_TO_VIRT(addr), data + offset, size);
- }
- }
-
-@@ -620,7 +621,7 @@ static int pe_load_ddr_section(int id, const void *data, Elf32_Shdr *shdr)
- }
- else
- {
-- memcpy(DDR_PFE_TO_VIRT(addr), data + offset, size);
-+ memcpy((void *)DDR_PFE_TO_VIRT(addr), data + offset, size);
- }
-
- break;
-diff --git a/drivers/net/pfe_eth/pfe/pfe.h b/drivers/net/pfe_eth/pfe/pfe.h
-index 6994a20..9445155 100644
---- a/drivers/net/pfe_eth/pfe/pfe.h
-+++ b/drivers/net/pfe_eth/pfe/pfe.h
-@@ -50,7 +50,7 @@ extern void *ddr_base_addr;
- #define PFE_CBUS_PHYS_BASE_ADDR 0xc0000000 /**< CBUS physical base address as seen by PE's. */
-
- /* Host<->PFE Mapping */
--#define DDR_PFE_TO_VIRT(p) ((p ) + 0x80000000)
-+#define DDR_PFE_TO_VIRT(p) ((unsigned long int)((p ) + 0x80000000))
- #define CBUS_VIRT_TO_PFE(v) (((v) - CBUS_BASE_ADDR) + PFE_CBUS_PHYS_BASE_ADDR)
- #define CBUS_PFE_TO_VIRT(p) (((p) - PFE_CBUS_PHYS_BASE_ADDR) + CBUS_BASE_ADDR)
-
-diff --git a/drivers/net/pfe_eth/pfe_driver.c b/drivers/net/pfe_eth/pfe_driver.c
-index b06a352..2f4c385 100644
---- a/drivers/net/pfe_eth/pfe_driver.c
-+++ b/drivers/net/pfe_eth/pfe_driver.c
-@@ -87,7 +87,7 @@ int pfe_recv(unsigned int *pkt_ptr, int *phy_port)
- }
- #endif
-
-- *pkt_ptr = (unsigned int )(hif_header + 1);
-+ *pkt_ptr = (unsigned long)(hif_header + 1);
- *phy_port = hif_header->port_no;
- len -= sizeof(struct hif_header_s);
-
-@@ -174,7 +174,7 @@ int pfe_send(int phy_port, void *data, int length)
- length = MIN_PKT_SIZE;
- }
-
-- tx_buf_va = (u8 *)DDR_PFE_TO_VIRT(bd->data);
-+ tx_buf_va = (void *)DDR_PFE_TO_VIRT(bd->data);
- dprint("%s: tx_buf_va: %p, tx_buf_pa: %08x\n", __func__, tx_buf_va, bd->data);
-
- /* Fill the gemac/phy port number to send this packet out */
-@@ -388,7 +388,7 @@ static int hif_rx_desc_init(struct pfe *pfe)
- ctrl = (MAX_FRAME_SIZE | BD_CTRL_DESC_EN | BD_CTRL_DIR | BD_CTRL_LIFM);
- #endif
- for (i=0; i < rx_desc->rxRingSize; i++) {
-- bd_va->next = (u32 )(bd_pa + 1);
-+ bd_va->next = (unsigned long)(bd_pa + 1);
- bd_va->ctrl = ctrl;
- bd_va->data = rx_buf_pa + (i * MAX_FRAME_SIZE);
- // printf("status: %08x, ctrl: %08x, data: %08x, next: %p\n",
-@@ -476,7 +476,7 @@ static int hif_tx_desc_init(struct pfe *pfe)
- tx_buf_pa = pfe->ddr_phys_baseaddr + HIF_TX_PKT_DDR_BASEADDR;
-
- for (i=0; i < tx_desc->txRingSize; i++) {
-- bd_va->next = (u32 )(bd_pa + 1);
-+ bd_va->next = (unsigned long)(bd_pa + 1);
- bd_va->data = tx_buf_pa + (i * MAX_FRAME_SIZE);
- // printf("status: %08x, ctrl: %08x, data: %08x, next: %p\n",
- // bd_va->status, bd_va->ctrl, bd_va->data, bd_va->next);
-diff --git a/drivers/net/pfe_eth/pfe_eth.c b/drivers/net/pfe_eth/pfe_eth.c
-index 4aa318d..4a935ca 100644
---- a/drivers/net/pfe_eth/pfe_eth.c
-+++ b/drivers/net/pfe_eth/pfe_eth.c
-@@ -53,10 +53,6 @@ static void ls1012a_gemac_disable(void *gemac_base)
- writel(readl(gemac_base + EMAC_ECNTRL_REG) & ~EMAC_ECNTRL_ETHER_EN, gemac_base + EMAC_ECNTRL_REG);
- }
-
--static void ls1012a_gemac_set_mode(void *gemac_base, u32 mode)
--{
--}
--
- static void ls1012a_gemac_set_speed(void *gemac_base, u32 speed)
- {
- struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
-@@ -125,7 +121,6 @@ static int ls1012a_eth_init(struct eth_device *dev, bd_t * bd)
- struct ls1012a_eth_dev *priv = (struct ls1012a_eth_dev *)dev->priv;
- struct gemac_s *gem = priv->gem;
- int speed;
-- int tmp;
-
- /* set ethernet mac address */
- ls1012a_gemac_set_ethaddr(gem->gemac_base, dev->enetaddr);
-@@ -220,7 +215,7 @@ static int ls1012a_eth_recv(struct eth_device *dev)
- }
-
- // Pass the packet up to the protocol layers.
-- net_process_received_packet((uchar *)pkt_buf, len);
-+ net_process_received_packet((void *)(long int)pkt_buf, len);
-
- return 0;
- }
-diff --git a/drivers/net/pfe_eth/pfe_eth.h b/drivers/net/pfe_eth/pfe_eth.h
-index c16b8c0..af6191d 100644
---- a/drivers/net/pfe_eth/pfe_eth.h
-+++ b/drivers/net/pfe_eth/pfe_eth.h
-@@ -26,6 +26,7 @@
-
-
- #include "pfe_driver.h"
-+#include <phy.h>
-
- #ifndef SZ_1K
- #define SZ_1K 1024
-@@ -151,7 +152,10 @@ struct firmware {
-
- int pfe_probe(struct pfe *pfe);
- int pfe_remove(struct pfe *pfe);
--
-+struct mii_dev *ls1012a_mdio_init(struct mdio_info *mdio_info);
-+void ls1012a_set_mdio(int dev_id, struct mii_dev *bus);
-+void ls1012a_set_phy_address_mode(int dev_id, int phy_id, int phy_mode);
-+int ls1012a_gemac_initialize(bd_t * bis, int dev_id, char *devname);
-
- //#define dprint(fmt, arg...) printf(fmt, ##arg)
- #define dprint(fmt, arg...)
-diff --git a/drivers/net/pfe_eth/pfe_firmware.c b/drivers/net/pfe_eth/pfe_firmware.c
-index 165eb3c..5957afd 100644
---- a/drivers/net/pfe_eth/pfe_firmware.c
-+++ b/drivers/net/pfe_eth/pfe_firmware.c
-@@ -45,7 +45,7 @@ int pfe_load_elf(int pe_mask, const struct firmware *fw)
- printf("%s: no of sections: %d\n", __func__, sections);
-
- /* Some sanity checks */
-- if (strncmp(&elf_hdr->e_ident[EI_MAG0], ELFMAG, SELFMAG))
-+ if (strncmp((char *)&elf_hdr->e_ident[EI_MAG0], ELFMAG, SELFMAG))
- {
- printf("%s: incorrect elf magic number\n", __func__);
- return -1;
---
-1.7.9.5
-
diff --git a/package/boot/uboot-layerscape/patches/0052-Add-Freescale-Copyright-in-PPFE-driver.patch b/package/boot/uboot-layerscape/patches/0052-Add-Freescale-Copyright-in-PPFE-driver.patch
deleted file mode 100644
index 854e39b..0000000
--- a/package/boot/uboot-layerscape/patches/0052-Add-Freescale-Copyright-in-PPFE-driver.patch
+++ /dev/null
@@ -1,688 +0,0 @@
-From e6ab05ee921fe2c8ae2dabdd5c1f27e2ff2446cb Mon Sep 17 00:00:00 2001
-From: Bhaskar Upadhaya <Bhaskar.Upadhaya at freescale.com>
-Date: Mon, 13 Jun 2016 07:37:52 +0530
-Subject: [PATCH 52/93] Add Freescale Copyright in PPFE driver
-
-Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya at freescale.com>
----
- board/freescale/ls1012ardb/eth.c | 2 +-
- common/cmd_gemac_stat.c | 25 ++++---------------------
- common/cmd_pfe_commands.c | 25 ++++---------------------
- drivers/net/pfe_eth/Makefile | 4 ++++
- drivers/net/pfe_eth/hal.h | 26 ++++----------------------
- drivers/net/pfe_eth/pfe.c | 5 +++++
- drivers/net/pfe_eth/pfe/cbus.h | 5 +++++
- drivers/net/pfe_eth/pfe/cbus/bmu.h | 5 +++++
- drivers/net/pfe_eth/pfe/cbus/class_csr.h | 5 +++++
- drivers/net/pfe_eth/pfe/cbus/emac.h | 5 +++++
- drivers/net/pfe_eth/pfe/cbus/gpi.h | 5 +++++
- drivers/net/pfe_eth/pfe/cbus/gpt.h | 5 +++++
- drivers/net/pfe_eth/pfe/cbus/hif.h | 5 +++++
- drivers/net/pfe_eth/pfe/cbus/hif_nocpy.h | 5 +++++
- drivers/net/pfe_eth/pfe/cbus/tmu_csr.h | 5 +++++
- drivers/net/pfe_eth/pfe/cbus/util_csr.h | 5 +++++
- drivers/net/pfe_eth/pfe/class.h | 5 +++++
- drivers/net/pfe_eth/pfe/class/ccu.h | 5 +++++
- drivers/net/pfe_eth/pfe/class/efet.h | 5 +++++
- drivers/net/pfe_eth/pfe/class/mac_hash.h | 5 +++++
- drivers/net/pfe_eth/pfe/class/perg.h | 5 +++++
- drivers/net/pfe_eth/pfe/class/vlan_hash.h | 5 +++++
- drivers/net/pfe_eth/pfe/gpt.h | 5 +++++
- drivers/net/pfe_eth/pfe/pe.h | 5 +++++
- drivers/net/pfe_eth/pfe/pfe.h | 5 +++++
- drivers/net/pfe_eth/pfe/tmu.h | 5 +++++
- drivers/net/pfe_eth/pfe/tmu/phy_queue.h | 5 +++++
- drivers/net/pfe_eth/pfe/tmu/sched.h | 5 +++++
- drivers/net/pfe_eth/pfe/tmu/shaper.h | 5 +++++
- drivers/net/pfe_eth/pfe/uart.h | 5 +++++
- drivers/net/pfe_eth/pfe/util/eape.h | 5 +++++
- drivers/net/pfe_eth/pfe/util/efet.h | 5 +++++
- drivers/net/pfe_eth/pfe/util/inq.h | 5 +++++
- drivers/net/pfe_eth/pfe_driver.c | 27 ++++-----------------------
- drivers/net/pfe_eth/pfe_driver.h | 26 ++++----------------------
- drivers/net/pfe_eth/pfe_eth.c | 5 +++++
- drivers/net/pfe_eth/pfe_eth.h | 26 ++++----------------------
- drivers/net/pfe_eth/pfe_firmware.c | 6 +++++-
- drivers/net/pfe_eth/pfe_firmware.h | 6 +++++-
- 39 files changed, 184 insertions(+), 134 deletions(-)
-
-diff --git a/board/freescale/ls1012ardb/eth.c b/board/freescale/ls1012ardb/eth.c
-index 7b0e450..34ba56d 100644
---- a/board/freescale/ls1012ardb/eth.c
-+++ b/board/freescale/ls1012ardb/eth.c
-@@ -1,7 +1,7 @@
- /*
- * Copyright 2016 Freescale Semiconductor, Inc.
- *
-- * SPDX-License-Identifier: GPL-2.0+
-+ * SPDX-License-Identifier:GPL-2.0+
- */
-
- #include <common.h>
-diff --git a/common/cmd_gemac_stat.c b/common/cmd_gemac_stat.c
-index 49bb1aa..fb621a2 100644
---- a/common/cmd_gemac_stat.c
-+++ b/common/cmd_gemac_stat.c
-@@ -1,25 +1,8 @@
- /*
-- * (C) Copyright 2003
-- * Author : Laurent Brando (Mindspeed Technologies)
-- *
-- * See file CREDITS for list of people who contributed to this
-- * project.
-- *
-- * This program is free software; you can redistribute it and/or
-- * modify it under the terms of the GNU General Public License as
-- * published by the Free Software Foundation; either version 2 of
-- * the License, or (at your option) any later version.
-- *
-- * This program is distributed in the hope that it will be useful,
-- * but WITHOUT ANY WARRANTY; without even the implied warranty of
-- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- * GNU General Public License for more details.
-- *
-- * You should have received a copy of the GNU General Public License
-- * along with this program; if not, write to the Free Software
-- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-- * MA 02111-1307 USA
-- */
-+* Copyright (C) 2016 Freescale Semiconductor Inc.
-+*
-+* SPDX-License-Identifier:GPL-2.0+
-+*/
-
- /**
- * @file
-diff --git a/common/cmd_pfe_commands.c b/common/cmd_pfe_commands.c
-index 84999a6..92917e0 100644
---- a/common/cmd_pfe_commands.c
-+++ b/common/cmd_pfe_commands.c
-@@ -1,25 +1,8 @@
- /*
-- * (C) Copyright 2012
-- * Author : Bill Westland (Mindspeed Technologies)
-- *
-- * See file CREDITS for list of people who contributed to this
-- * project.
-- *
-- * This program is free software; you can redistribute it and/or
-- * modify it under the terms of the GNU General Public License as
-- * published by the Free Software Foundation; either version 2 of
-- * the License, or (at your option) any later version.
-- *
-- * This program is distributed in the hope that it will be useful,
-- * but WITHOUT ANY WARRANTY; without even the implied warranty of
-- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- * GNU General Public License for more details.
-- *
-- * You should have received a copy of the GNU General Public License
-- * along with this program; if not, write to the Free Software
-- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-- * MA 02111-1307 USA
-- */
-+* Copyright (C) 2016 Freescale Semiconductor Inc.
-+*
-+* SPDX-License-Identifier:GPL-2.0+
-+*/
-
- /**
- * @file
-diff --git a/drivers/net/pfe_eth/Makefile b/drivers/net/pfe_eth/Makefile
-index 1af837d..bc45d8f 100644
---- a/drivers/net/pfe_eth/Makefile
-+++ b/drivers/net/pfe_eth/Makefile
-@@ -1 +1,5 @@
-+# Copyright (C) 2016 Freescale Semiconductor Inc.
-+#
-+# SPDX-License-Identifier:GPL-2.0+
-+
- obj-y += pfe_eth.o pfe_firmware.o pfe.o pfe_driver.o
-diff --git a/drivers/net/pfe_eth/hal.h b/drivers/net/pfe_eth/hal.h
-index e795fe6..ff510ac 100644
---- a/drivers/net/pfe_eth/hal.h
-+++ b/drivers/net/pfe_eth/hal.h
-@@ -1,26 +1,8 @@
- /*
-- * (C) Copyright 2011
-- * Author : Mindspeed Technologes
-- *
-- * See file CREDITS for list of people who contributed to this
-- * project.
-- *
-- * This program is free software; you can redistribute it and/or
-- * modify it under the terms of the GNU General Public License as
-- * published by the Free Software Foundation; either version 2 of
-- * the License, or (at your option) any later version.
-- *
-- * This program is distributed in the hope that it will be useful,
-- * but WITHOUT ANY WARRANTY; without even the implied warranty of
-- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- * GNU General Public License for more details.
-- *
-- * You should have received a copy of the GNU General Public License
-- * along with this program; if not, write to the Free Software
-- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-- * MA 02111-1307 USA
-- * */
--
-+* Copyright (C) 2016 Freescale Semiconductor Inc.
-+*
-+* SPDX-License-Identifier:GPL-2.0+
-+*/
- #ifndef _HAL_H_
- #define _HAL_H_
-
-diff --git a/drivers/net/pfe_eth/pfe.c b/drivers/net/pfe_eth/pfe.c
-index 94cfe4e..68cf23a 100644
---- a/drivers/net/pfe_eth/pfe.c
-+++ b/drivers/net/pfe_eth/pfe.c
-@@ -1,3 +1,8 @@
-+/*
-+* Copyright (C) 2016 Freescale Semiconductor Inc.
-+*
-+* SPDX-License-Identifier:GPL-2.0+
-+*/
- #include "hal.h"
- #include "pfe/pfe.h"
-
-diff --git a/drivers/net/pfe_eth/pfe/cbus.h b/drivers/net/pfe_eth/pfe/cbus.h
-index 778fe45..d46a765 100644
---- a/drivers/net/pfe_eth/pfe/cbus.h
-+++ b/drivers/net/pfe_eth/pfe/cbus.h
-@@ -1,3 +1,8 @@
-+/*
-+* Copyright (C) 2016 Freescale Semiconductor Inc.
-+*
-+* SPDX-License-Identifier:GPL-2.0+
-+*/
- #ifndef _CBUS_H_
- #define _CBUS_H_
-
-diff --git a/drivers/net/pfe_eth/pfe/cbus/bmu.h b/drivers/net/pfe_eth/pfe/cbus/bmu.h
-index f3e5e6d..fd37570 100644
---- a/drivers/net/pfe_eth/pfe/cbus/bmu.h
-+++ b/drivers/net/pfe_eth/pfe/cbus/bmu.h
-@@ -1,3 +1,8 @@
-+/*
-+* Copyright (C) 2016 Freescale Semiconductor Inc.
-+*
-+* SPDX-License-Identifier:GPL-2.0+
-+*/
- #ifndef _BMU_H_
- #define _BMU_H_
-
-diff --git a/drivers/net/pfe_eth/pfe/cbus/class_csr.h b/drivers/net/pfe_eth/pfe/cbus/class_csr.h
-index f3151ec..4c2c3fa 100644
---- a/drivers/net/pfe_eth/pfe/cbus/class_csr.h
-+++ b/drivers/net/pfe_eth/pfe/cbus/class_csr.h
-@@ -1,3 +1,8 @@
-+/*
-+* Copyright (C) 2016 Freescale Semiconductor Inc.
-+*
-+* SPDX-License-Identifier:GPL-2.0+
-+*/
- #ifndef _CLASS_CSR_H_
- #define _CLASS_CSR_H_
-
-diff --git a/drivers/net/pfe_eth/pfe/cbus/emac.h b/drivers/net/pfe_eth/pfe/cbus/emac.h
-index 1f308ce..aead064 100644
---- a/drivers/net/pfe_eth/pfe/cbus/emac.h
-+++ b/drivers/net/pfe_eth/pfe/cbus/emac.h
-@@ -1,3 +1,8 @@
-+/*
-+* Copyright (C) 2016 Freescale Semiconductor Inc.
-+*
-+* SPDX-License-Identifier:GPL-2.0+
-+*/
- #ifndef _EMAC_H_
- #define _EMAC_H_
-
-diff --git a/drivers/net/pfe_eth/pfe/cbus/gpi.h b/drivers/net/pfe_eth/pfe/cbus/gpi.h
-index d2d165f..7792d6c 100644
---- a/drivers/net/pfe_eth/pfe/cbus/gpi.h
-+++ b/drivers/net/pfe_eth/pfe/cbus/gpi.h
-@@ -1,3 +1,8 @@
-+/*
-+* Copyright (C) 2016 Freescale Semiconductor Inc.
-+*
-+* SPDX-License-Identifier:GPL-2.0+
-+*/
- #ifndef _GPI_H_
- #define _GPI_H_
-
-diff --git a/drivers/net/pfe_eth/pfe/cbus/gpt.h b/drivers/net/pfe_eth/pfe/cbus/gpt.h
-index f8c114b..0ec5fdc 100644
---- a/drivers/net/pfe_eth/pfe/cbus/gpt.h
-+++ b/drivers/net/pfe_eth/pfe/cbus/gpt.h
-@@ -1,3 +1,8 @@
-+/*
-+* Copyright (C) 2016 Freescale Semiconductor Inc.
-+*
-+* SPDX-License-Identifier:GPL-2.0+
-+*/
- #ifndef _CBUS_GPT_H_
- #define _CBUS_GPT_H_
-
-diff --git a/drivers/net/pfe_eth/pfe/cbus/hif.h b/drivers/net/pfe_eth/pfe/cbus/hif.h
-index 2329faa..45bc0b2 100644
---- a/drivers/net/pfe_eth/pfe/cbus/hif.h
-+++ b/drivers/net/pfe_eth/pfe/cbus/hif.h
-@@ -1,3 +1,8 @@
-+/*
-+* Copyright (C) 2016 Freescale Semiconductor Inc.
-+*
-+* SPDX-License-Identifier:GPL-2.0+
-+*/
- #ifndef _HIF_H_
- #define _HIF_H_
-
-diff --git a/drivers/net/pfe_eth/pfe/cbus/hif_nocpy.h b/drivers/net/pfe_eth/pfe/cbus/hif_nocpy.h
-index 93cb946..55ddc8c 100644
---- a/drivers/net/pfe_eth/pfe/cbus/hif_nocpy.h
-+++ b/drivers/net/pfe_eth/pfe/cbus/hif_nocpy.h
-@@ -1,3 +1,8 @@
-+/*
-+* Copyright (C) 2016 Freescale Semiconductor Inc.
-+*
-+* SPDX-License-Identifier:GPL-2.0+
-+*/
- #ifndef _HIF_NOCPY_H_
- #define _HIF_NOCPY_H_
-
-diff --git a/drivers/net/pfe_eth/pfe/cbus/tmu_csr.h b/drivers/net/pfe_eth/pfe/cbus/tmu_csr.h
-index 64fad04..058874e 100644
---- a/drivers/net/pfe_eth/pfe/cbus/tmu_csr.h
-+++ b/drivers/net/pfe_eth/pfe/cbus/tmu_csr.h
-@@ -1,3 +1,8 @@
-+/*
-+* Copyright (C) 2016 Freescale Semiconductor Inc.
-+*
-+* SPDX-License-Identifier:GPL-2.0+
-+*/
- #ifndef _TMU_CSR_H_
- #define _TMU_CSR_H_
-
-diff --git a/drivers/net/pfe_eth/pfe/cbus/util_csr.h b/drivers/net/pfe_eth/pfe/cbus/util_csr.h
-index d67e849..14079db 100644
---- a/drivers/net/pfe_eth/pfe/cbus/util_csr.h
-+++ b/drivers/net/pfe_eth/pfe/cbus/util_csr.h
-@@ -1,3 +1,8 @@
-+/*
-+* Copyright (C) 2016 Freescale Semiconductor Inc.
-+*
-+* SPDX-License-Identifier:GPL-2.0+
-+*/
- #ifndef _UTIL_CSR_H_
- #define _UTIL_CSR_H_
-
-diff --git a/drivers/net/pfe_eth/pfe/class.h b/drivers/net/pfe_eth/pfe/class.h
-index 33ad826..87b1399 100644
---- a/drivers/net/pfe_eth/pfe/class.h
-+++ b/drivers/net/pfe_eth/pfe/class.h
-@@ -1,3 +1,8 @@
-+/*
-+* Copyright (C) 2016 Freescale Semiconductor Inc.
-+*
-+* SPDX-License-Identifier:GPL-2.0+
-+*/
- #ifndef _CLASS_H_
- #define _CLASS_H_
-
-diff --git a/drivers/net/pfe_eth/pfe/class/ccu.h b/drivers/net/pfe_eth/pfe/class/ccu.h
-index 2c43d97..605ac16 100644
---- a/drivers/net/pfe_eth/pfe/class/ccu.h
-+++ b/drivers/net/pfe_eth/pfe/class/ccu.h
-@@ -1,3 +1,8 @@
-+/*
-+* Copyright (C) 2016 Freescale Semiconductor Inc.
-+*
-+* SPDX-License-Identifier:GPL-2.0+
-+*/
- #ifndef _CCU_H_
- #define _CCU_H_
-
-diff --git a/drivers/net/pfe_eth/pfe/class/efet.h b/drivers/net/pfe_eth/pfe/class/efet.h
-index 4f3cc25..7ef2978 100644
---- a/drivers/net/pfe_eth/pfe/class/efet.h
-+++ b/drivers/net/pfe_eth/pfe/class/efet.h
-@@ -1,3 +1,8 @@
-+/*
-+* Copyright (C) 2016 Freescale Semiconductor Inc.
-+*
-+* SPDX-License-Identifier:GPL-2.0+
-+*/
- #ifndef _CLASS_EFET_H_
- #define _CLASS_EFET_H_
-
-diff --git a/drivers/net/pfe_eth/pfe/class/mac_hash.h b/drivers/net/pfe_eth/pfe/class/mac_hash.h
-index 68023b4..ca24ca5 100644
---- a/drivers/net/pfe_eth/pfe/class/mac_hash.h
-+++ b/drivers/net/pfe_eth/pfe/class/mac_hash.h
-@@ -1,3 +1,8 @@
-+/*
-+* Copyright (C) 2016 Freescale Semiconductor Inc.
-+*
-+* SPDX-License-Identifier:GPL-2.0+
-+*/
- #ifndef _MAC_HASH_H_
- #define _MAC_HASH_H_
-
-diff --git a/drivers/net/pfe_eth/pfe/class/perg.h b/drivers/net/pfe_eth/pfe/class/perg.h
-index 7297171..dbb5a3b 100644
---- a/drivers/net/pfe_eth/pfe/class/perg.h
-+++ b/drivers/net/pfe_eth/pfe/class/perg.h
-@@ -1,3 +1,8 @@
-+/*
-+* Copyright (C) 2016 Freescale Semiconductor Inc.
-+*
-+* SPDX-License-Identifier:GPL-2.0+
-+*/
- #ifndef _PERG_H_
- #define _PERG_H_
-
-diff --git a/drivers/net/pfe_eth/pfe/class/vlan_hash.h b/drivers/net/pfe_eth/pfe/class/vlan_hash.h
-index a54ac19..cdad97c 100644
---- a/drivers/net/pfe_eth/pfe/class/vlan_hash.h
-+++ b/drivers/net/pfe_eth/pfe/class/vlan_hash.h
-@@ -1,3 +1,8 @@
-+/*
-+* Copyright (C) 2016 Freescale Semiconductor Inc.
-+*
-+* SPDX-License-Identifier:GPL-2.0+
-+*/
- #ifndef _VLAN_HASH_H_
- #define _VLAN_HASH_H_
-
-diff --git a/drivers/net/pfe_eth/pfe/gpt.h b/drivers/net/pfe_eth/pfe/gpt.h
-index d820277..6fce042 100644
---- a/drivers/net/pfe_eth/pfe/gpt.h
-+++ b/drivers/net/pfe_eth/pfe/gpt.h
-@@ -1,3 +1,8 @@
-+/*
-+* Copyright (C) 2016 Freescale Semiconductor Inc.
-+*
-+* SPDX-License-Identifier:GPL-2.0+
-+*/
- #ifndef _GPT_H_
- #define _GPT_H_
-
-diff --git a/drivers/net/pfe_eth/pfe/pe.h b/drivers/net/pfe_eth/pfe/pe.h
-index a3838f5..ac8cbf2 100644
---- a/drivers/net/pfe_eth/pfe/pe.h
-+++ b/drivers/net/pfe_eth/pfe/pe.h
-@@ -1,3 +1,8 @@
-+/*
-+* Copyright (C) 2016 Freescale Semiconductor Inc.
-+*
-+* SPDX-License-Identifier:GPL-2.0+
-+*/
- #ifndef _PE_H_
- #define _PE_H_
-
-diff --git a/drivers/net/pfe_eth/pfe/pfe.h b/drivers/net/pfe_eth/pfe/pfe.h
-index 9445155..ac1ecb8 100644
---- a/drivers/net/pfe_eth/pfe/pfe.h
-+++ b/drivers/net/pfe_eth/pfe/pfe.h
-@@ -1,3 +1,8 @@
-+/*
-+* Copyright (C) 2016 Freescale Semiconductor Inc.
-+*
-+* SPDX-License-Identifier:GPL-2.0+
-+*/
- #ifndef _PFE_H_
- #define _PFE_H_
-
-diff --git a/drivers/net/pfe_eth/pfe/tmu.h b/drivers/net/pfe_eth/pfe/tmu.h
-index 12eaf12..dd697be 100644
---- a/drivers/net/pfe_eth/pfe/tmu.h
-+++ b/drivers/net/pfe_eth/pfe/tmu.h
-@@ -1,3 +1,8 @@
-+/*
-+* Copyright (C) 2016 Freescale Semiconductor Inc.
-+*
-+* SPDX-License-Identifier:GPL-2.0+
-+*/
- #ifndef _TMU_H_
- #define _TMU_H_
-
-diff --git a/drivers/net/pfe_eth/pfe/tmu/phy_queue.h b/drivers/net/pfe_eth/pfe/tmu/phy_queue.h
-index 9eef9a9..b9a0925 100644
---- a/drivers/net/pfe_eth/pfe/tmu/phy_queue.h
-+++ b/drivers/net/pfe_eth/pfe/tmu/phy_queue.h
-@@ -1,3 +1,8 @@
-+/*
-+* Copyright (C) 2016 Freescale Semiconductor Inc.
-+*
-+* SPDX-License-Identifier:GPL-2.0+
-+*/
- #ifndef _PHY_QUEUE_H_
- #define _PHY_QUEUE_H_
-
-diff --git a/drivers/net/pfe_eth/pfe/tmu/sched.h b/drivers/net/pfe_eth/pfe/tmu/sched.h
-index 0c741cc..954dc8f 100644
---- a/drivers/net/pfe_eth/pfe/tmu/sched.h
-+++ b/drivers/net/pfe_eth/pfe/tmu/sched.h
-@@ -1,3 +1,8 @@
-+/*
-+* Copyright (C) 2016 Freescale Semiconductor Inc.
-+*
-+* SPDX-License-Identifier:GPL-2.0+
-+*/
- #ifndef _SCHED_H_
- #define _SCHED_H_
-
-diff --git a/drivers/net/pfe_eth/pfe/tmu/shaper.h b/drivers/net/pfe_eth/pfe/tmu/shaper.h
-index 76315f3..81c367d 100644
---- a/drivers/net/pfe_eth/pfe/tmu/shaper.h
-+++ b/drivers/net/pfe_eth/pfe/tmu/shaper.h
-@@ -1,3 +1,8 @@
-+/*
-+* Copyright (C) 2016 Freescale Semiconductor Inc.
-+*
-+* SPDX-License-Identifier:GPL-2.0+
-+*/
- #ifndef _SHAPER_H_
- #define _SHAPER_H_
-
-diff --git a/drivers/net/pfe_eth/pfe/uart.h b/drivers/net/pfe_eth/pfe/uart.h
-index 483d446..2268430 100644
---- a/drivers/net/pfe_eth/pfe/uart.h
-+++ b/drivers/net/pfe_eth/pfe/uart.h
-@@ -1,3 +1,8 @@
-+/*
-+* Copyright (C) 2016 Freescale Semiconductor Inc.
-+*
-+* SPDX-License-Identifier:GPL-2.0+
-+*/
- #ifndef _UART_H_
- #define _UART_H_
-
-diff --git a/drivers/net/pfe_eth/pfe/util/eape.h b/drivers/net/pfe_eth/pfe/util/eape.h
-index 07344dc..77af2d4 100644
---- a/drivers/net/pfe_eth/pfe/util/eape.h
-+++ b/drivers/net/pfe_eth/pfe/util/eape.h
-@@ -1,3 +1,8 @@
-+/*
-+* Copyright (C) 2016 Freescale Semiconductor Inc.
-+*
-+* SPDX-License-Identifier:GPL-2.0+
-+*/
- #ifndef _EAPE_H_
- #define _EAPE_H_
-
-diff --git a/drivers/net/pfe_eth/pfe/util/efet.h b/drivers/net/pfe_eth/pfe/util/efet.h
-index 12d0310..eed87fe 100644
---- a/drivers/net/pfe_eth/pfe/util/efet.h
-+++ b/drivers/net/pfe_eth/pfe/util/efet.h
-@@ -1,3 +1,8 @@
-+/*
-+* Copyright (C) 2016 Freescale Semiconductor Inc.
-+*
-+* SPDX-License-Identifier:GPL-2.0+
-+*/
- #ifndef _UTIL_EFET_H_
- #define _UTIL_EFET_H_
-
-diff --git a/drivers/net/pfe_eth/pfe/util/inq.h b/drivers/net/pfe_eth/pfe/util/inq.h
-index 73d1acb..7ee008b 100644
---- a/drivers/net/pfe_eth/pfe/util/inq.h
-+++ b/drivers/net/pfe_eth/pfe/util/inq.h
-@@ -1,3 +1,8 @@
-+/*
-+* Copyright (C) 2016 Freescale Semiconductor Inc.
-+*
-+* SPDX-License-Identifier:GPL-2.0+
-+*/
- #ifndef _INQ_H_
- #define _INQ_H_
-
-diff --git a/drivers/net/pfe_eth/pfe_driver.c b/drivers/net/pfe_eth/pfe_driver.c
-index 2f4c385..e252fcf 100644
---- a/drivers/net/pfe_eth/pfe_driver.c
-+++ b/drivers/net/pfe_eth/pfe_driver.c
-@@ -1,27 +1,8 @@
- /*
-- * (C) Copyright 2011
-- * Author : Mindspeed Technologes
-- *
-- * See file CREDITS for list of people who contributed to this
-- * project.
-- *
-- * This program is free software; you can redistribute it and/or
-- * modify it under the terms of the GNU General Public License as
-- * published by the Free Software Foundation; either version 2 of
-- * the License, or (at your option) any later version.
-- *
-- * This program is distributed in the hope that it will be useful,
-- * but WITHOUT ANY WARRANTY; without even the implied warranty of
-- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- * GNU General Public License for more details.
-- *
-- * You should have received a copy of the GNU General Public License
-- * along with this program; if not, write to the Free Software
-- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-- * MA 02111-1307 USA
-- * */
--
--
-+* Copyright (C) 2016 Freescale Semiconductor Inc.
-+*
-+* SPDX-License-Identifier:GPL-2.0+
-+*/
- #include "hal.h"
- #include "pfe/pfe.h"
- #include "pfe_driver.h"
-diff --git a/drivers/net/pfe_eth/pfe_driver.h b/drivers/net/pfe_eth/pfe_driver.h
-index 4d2e8b6..2ef8e5c 100644
---- a/drivers/net/pfe_eth/pfe_driver.h
-+++ b/drivers/net/pfe_eth/pfe_driver.h
-@@ -1,26 +1,8 @@
- /*
-- * (C) Copyright 2011
-- * Author : Mindspeed Technologes
-- *
-- * See file CREDITS for list of people who contributed to this
-- * project.
-- *
-- * This program is free software; you can redistribute it and/or
-- * modify it under the terms of the GNU General Public License as
-- * published by the Free Software Foundation; either version 2 of
-- * the License, or (at your option) any later version.
-- *
-- * This program is distributed in the hope that it will be useful,
-- * but WITHOUT ANY WARRANTY; without even the implied warranty of
-- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- * GNU General Public License for more details.
-- *
-- * You should have received a copy of the GNU General Public License
-- * along with this program; if not, write to the Free Software
-- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-- * MA 02111-1307 USA
-- * */
--
-+* Copyright (C) 2016 Freescale Semiconductor Inc.
-+*
-+* SPDX-License-Identifier:GPL-2.0+
-+*/
- #ifndef __PFE_DRIVER_H__
- #define __PFE_DRIVER_H__
-
-diff --git a/drivers/net/pfe_eth/pfe_eth.c b/drivers/net/pfe_eth/pfe_eth.c
-index 4a935ca..528ede9 100644
---- a/drivers/net/pfe_eth/pfe_eth.c
-+++ b/drivers/net/pfe_eth/pfe_eth.c
-@@ -1,3 +1,8 @@
-+/*
-+* Copyright (C) 2016 Freescale Semiconductor Inc.
-+*
-+* SPDX-License-Identifier:GPL-2.0+
-+*/
- #include <common.h>
- #include <config.h>
- //#include <asm/arch/hardware.h>
-diff --git a/drivers/net/pfe_eth/pfe_eth.h b/drivers/net/pfe_eth/pfe_eth.h
-index af6191d..358fa58 100644
---- a/drivers/net/pfe_eth/pfe_eth.h
-+++ b/drivers/net/pfe_eth/pfe_eth.h
-@@ -1,26 +1,8 @@
- /*
-- * (C) Copyright 2011
-- * Author : Mindspeed Technologes
-- *
-- * See file CREDITS for list of people who contributed to this
-- * project.
-- *
-- * This program is free software; you can redistribute it and/or
-- * modify it under the terms of the GNU General Public License as
-- * published by the Free Software Foundation; either version 2 of
-- * the License, or (at your option) any later version.
-- *
-- * This program is distributed in the hope that it will be useful,
-- * but WITHOUT ANY WARRANTY; without even the implied warranty of
-- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- * GNU General Public License for more details.
-- *
-- * You should have received a copy of the GNU General Public License
-- * along with this program; if not, write to the Free Software
-- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-- * MA 02111-1307 USA
-- * */
--
-+* Copyright (C) 2016 Freescale Semiconductor Inc.
-+*
-+* SPDX-License-Identifier:GPL-2.0+
-+*/
- #ifndef _LS1012a_ETH_H_
- #define _LS1012a_ETH_H_
-
-diff --git a/drivers/net/pfe_eth/pfe_firmware.c b/drivers/net/pfe_eth/pfe_firmware.c
-index 5957afd..e190514 100644
---- a/drivers/net/pfe_eth/pfe_firmware.c
-+++ b/drivers/net/pfe_eth/pfe_firmware.c
-@@ -1,4 +1,8 @@
--
-+/*
-+* Copyright (C) 2016 Freescale Semiconductor Inc.
-+*
-+* SPDX-License-Identifier:GPL-2.0+
-+*/
-
- /** @file
- * Contains all the functions to handle parsing and loading of PE firmware files.
-diff --git a/drivers/net/pfe_eth/pfe_firmware.h b/drivers/net/pfe_eth/pfe_firmware.h
-index 2823162..ecae3e3 100644
---- a/drivers/net/pfe_eth/pfe_firmware.h
-+++ b/drivers/net/pfe_eth/pfe_firmware.h
-@@ -1,4 +1,8 @@
--
-+/*
-+* Copyright (C) 2016 Freescale Semiconductor Inc.
-+*
-+* SPDX-License-Identifier:GPL-2.0+
-+*/
-
- /** @file
- * Contains all the defines to handle parsing and loading of PE firmware files.
---
-1.7.9.5
-
diff --git a/package/boot/uboot-layerscape/patches/0053-armv8-arch-fsl-layerscape-Update-name-of-Soc.patch b/package/boot/uboot-layerscape/patches/0053-armv8-arch-fsl-layerscape-Update-name-of-Soc.patch
deleted file mode 100644
index 3714694..0000000
--- a/package/boot/uboot-layerscape/patches/0053-armv8-arch-fsl-layerscape-Update-name-of-Soc.patch
+++ /dev/null
@@ -1,40 +0,0 @@
-From 9722009432a5553b11c8e0a04a275654de11dbc4 Mon Sep 17 00:00:00 2001
-From: Pratiyush Mohan Srivastava <pratiyush.srivastava at nxp.com>
-Date: Mon, 13 Jun 2016 16:33:06 +0530
-Subject: [PATCH 53/93] armv8: arch-fsl-layerscape: Update name of Soc
-
-Update the name of the Soc.
-
-Signed-off-by: Pratiyush Mohan Srivastava <pratiyush.srivastava at nxp.com>
----
- arch/arm/include/asm/arch-fsl-layerscape/cpu.h | 14 +++++++-------
- 1 file changed, 7 insertions(+), 7 deletions(-)
-
-diff --git a/arch/arm/include/asm/arch-fsl-layerscape/cpu.h b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h
-index e4ff990..7a943be 100644
---- a/arch/arm/include/asm/arch-fsl-layerscape/cpu.h
-+++ b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h
-@@ -8,13 +8,13 @@
- #define _FSL_LAYERSCAPE_CPU_H
-
- static struct cpu_type cpu_type_list[] = {
-- CPU_TYPE_ENTRY(LS2080, LS2080, 8),
-- CPU_TYPE_ENTRY(LS2085, LS2085, 8),
-- CPU_TYPE_ENTRY(LS2045, LS2045, 4),
-- CPU_TYPE_ENTRY(LS1043, LS1043, 4),
-- CPU_TYPE_ENTRY(LS1023, LS1023, 2),
-- CPU_TYPE_ENTRY(LS2040, LS2040, 4),
-- CPU_TYPE_ENTRY(LS1012, LS1012, 1),
-+ CPU_TYPE_ENTRY(LS2080A, LS2080, 8),
-+ CPU_TYPE_ENTRY(LS2085A, LS2085, 8),
-+ CPU_TYPE_ENTRY(LS2045A, LS2045, 4),
-+ CPU_TYPE_ENTRY(LS1043A, LS1043, 4),
-+ CPU_TYPE_ENTRY(LS1023A, LS1023, 2),
-+ CPU_TYPE_ENTRY(LS2040A, LS2040, 4),
-+ CPU_TYPE_ENTRY(LS1012A, LS1012, 1),
- };
-
- #ifndef CONFIG_SYS_DCACHE_OFF
---
-1.7.9.5
-
diff --git a/package/boot/uboot-layerscape/patches/0054-armv8-fsl-layerscape-Update-DDR-timings.patch b/package/boot/uboot-layerscape/patches/0054-armv8-fsl-layerscape-Update-DDR-timings.patch
deleted file mode 100644
index 76fb0b0..0000000
--- a/package/boot/uboot-layerscape/patches/0054-armv8-fsl-layerscape-Update-DDR-timings.patch
+++ /dev/null
@@ -1,33 +0,0 @@
-From 0ecab71ba6f860a831288337d96b0f4b0fbf12c6 Mon Sep 17 00:00:00 2001
-From: Pratiyush Mohan Srivastava <pratiyush.srivastava at nxp.com>
-Date: Mon, 13 Jun 2016 17:29:59 +0530
-Subject: [PATCH 54/93] armv8: fsl-layerscape: Update DDR timings
-
-DDR timigs displayed for LS1012A were half of true value.
-Updated DDR value to 1000 MT/s.
-
-Signed-off-by: Pratiyush Mohan Srivastava <pratiyush.srivastava at nxp.com>
----
- .../arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c | 5 +++--
- 1 file changed, 3 insertions(+), 2 deletions(-)
-
-diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c
-index 63e5bed..a4dde5b 100644
---- a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c
-+++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c
-@@ -92,9 +92,10 @@ void get_sys_info(struct sys_info *sys_info)
- freq_c_pll[cplx_pll] / core_cplx_pll_div[c_pll_sel];
- }
-
-- if (ver == SVR_LS1012)
-+ if (ver == SVR_LS1012){
- sys_info->freq_systembus = sys_info->freq_ddrbus / 2;
--
-+ sys_info->freq_ddrbus *=2;
-+ }
- #define HWA_CGA_M1_CLK_SEL 0xe0000000
- #define HWA_CGA_M1_CLK_SHIFT 29
- #ifdef CONFIG_SYS_DPAA_FMAN
---
-1.7.9.5
-
diff --git a/package/boot/uboot-layerscape/patches/0055-Add-License-file-for-PPFE-firmware-bins.patch b/package/boot/uboot-layerscape/patches/0055-Add-License-file-for-PPFE-firmware-bins.patch
deleted file mode 100644
index 12fbf74..0000000
--- a/package/boot/uboot-layerscape/patches/0055-Add-License-file-for-PPFE-firmware-bins.patch
+++ /dev/null
@@ -1,101 +0,0 @@
-From 0431dc26df78b00cef190f45f203a1598b4ba428 Mon Sep 17 00:00:00 2001
-From: Bhaskar Upadhaya <Bhaskar.Upadhaya at freescale.com>
-Date: Tue, 14 Jun 2016 10:07:41 +0530
-Subject: [PATCH 55/93] Add License file for PPFE firmware bins
-
-Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya at freescale.com>
-Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha at nxp.com>
----
- drivers/net/pfe_eth/Freescale-Binary-EULA.txt | 80 +++++++++++++++++++++++++
- 1 file changed, 80 insertions(+)
- create mode 100644 drivers/net/pfe_eth/Freescale-Binary-EULA.txt
-
-diff --git a/drivers/net/pfe_eth/Freescale-Binary-EULA.txt b/drivers/net/pfe_eth/Freescale-Binary-EULA.txt
-new file mode 100644
-index 0000000..628fa93
---- /dev/null
-+++ b/drivers/net/pfe_eth/Freescale-Binary-EULA.txt
-@@ -0,0 +1,80 @@
-+Copyright © 2016, Freescale Semiconductor, Inc. All rights reserved.
-+
-+Software License Agreement (.Agreement.)
-+
-+ANY USE, REPRODUCTION, OR DISTRIBUTION OF THE ACCOMPANYING BINARY SOFTWARE
-+CONSTITUTES LICENSEE'S ACCEPTANCE OF THE TERMS AND CONDITIONS OF THIS
-+AGREEMENT.
-+
-+Licensed Software. .Binary Software. means software in binary form specified
-+in ANNEX A Subject to the terms and conditions of this Agreement, Freescale
-+Semiconductor, Inc., a 100% affiliated company of NXP Semiconductors N.V.
-+which will be renamed in due course ("NXP"), grants to Licensee a worldwide,
-+non-exclusive, and royalty-free license to use, reproduce, and distribute the
-+Binary Software in its complete and unmodified binary form as provided by NXP.
-+
-+Restrictions. Licensee must reproduce the NXP copyright notice above with each
-+binary copy of the Binary Software. Licensee must not reverse engineer,
-+decompile, disassemble or modify in any way the Binary Software. Licensee must
-+not use the Binary Software in violation of any applicable law or regulation.
-+This Agreement shall automatically terminate upon Licensee's breach of any
-+term or condition of this Agreement in which case, Licensee shall destroy all
-+copies of the Binary Software.
-+
-+Warranty Disclaimer. TO THE MAXIMUM EXTENT PERMITTED BY LAW, NXP EXPRESSLY
-+DISCLAIMS ANY WARRANTY FOR THE BINARY SOFTWARE. THE BINARY SOFTWARE IS
-+PROVIDED .AS IS., WITHOUT WARRANTY OF ANY KIND, EITHER EXPRESS OR IMPLIED,
-+INCLUDING WITHOUT LIMITATION THE IMPLIED WARRANTIES OF MERCHANTABILITY,
-+FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT. LICENSEE ASSUMES
-+THE ENTIRE RISK ARISING OUT OF THE USE OR PERFORMANCE OF THE BINARY SOFTWARE,
-+OR ANY SYSTEMS LICENSEE DESIGNS USING THE BINARY SOFTWARE (IF ANY). WITHOUT
-+LIMITING THE GENERALITY OF THE FOREGOING, NXP DOES NOT WARRANT THAT THE BINARY
-+SOFTWARE IS ERROR-FREE OR WILL OPERATE WITHOUT INTERRUPTION, AND NXP GRANTS
-+NO WARRANTY REGARDING ITS USE OR THE RESULTS THEREFROM, INCLUDING ITS
-+CORRECTNESS, ACCURACY, OR RELIABILITY.
-+
-+Limitation of Liability. IN NO EVENT WILL NXP, OR ANY OF NXP'S LICENSORS HAVE
-+ANY LIABILITY HEREUNDER FOR ANY INDIRECT, SPECIAL, OR CONSEQUENTIAL DAMAGES,
-+HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER FOR BREACH OF CONTRACT,
-+TORT (INCLUDING NEGLIGENCE), OR OTHERWISE, ARISING OUT OF THIS AGREEMENT,
-+ INCLUDING DAMAGES FOR LOSS OF PROFITS, OR THE COST OF PROCUREMENT OF
-+ SUBSTITUTE GOODS, EVEN IF SUCH PARTY HAS BEEN ADVISED OF THE POSSIBILITY OF
-+ SUCH DAMAGES. NXP.S TOTAL LIABILITY FOR ALL COSTS, DAMAGES, CLAIMS, OR LOSSES
-+ WHATSOEVER ARISING OUT OF OR IN CONNECTION WITH THIS AGREEMENT OR THE BINARY
-+ SOFTWARE SUPPLIED UNDER THIS AGREEMENT IS LIMITED TO THE AGGREGATE AMOUNT PAID
-+ BY LICENSEE TO NXP IN CONNECTION WITH THE BINARY SOFTWARE TO WHICH LOSSES OR
-+ DAMAGES ARE CLAIMED.
-+
-+Trade Compliance. Licensee shall comply with all applicable export and import
-+ control laws and regulations including but not limited to the US Export
-+ Administration Regulation (including prohibited party lists issued by other
-+ federal governments), Catch-all regulations and all national and international
-+ embargoes. Licensee will not knowingly transfer, divert, export or re-export,
-+ directly or indirectly, any product, software, including software source code,
-+ or technology restricted by such regulations or by other applicable national
-+ regulations, received from the other party under this Agreement, or any direct
-+ product of such software or technical data to any person, firm, entity, country
-+ or destination to which such transfer, diversion, export or re-export is
-+ restricted or prohibited, without obtaining prior written authorization from
-+ the applicable competent government authorities to the extent required by
-+ those laws.
-+
-+Restrictions, Warranty Disclaimer, Limitation of Liability, Trade Compliance,
-+ and Governing Law shall survive termination or expiration of this Agreement.
-+
-+Governing Law. This Agreement will be governed by, construed, and enforced in
-+ accordance with the laws of the State of Texas, USA, without regard to
-+ conflicts of laws principles, will apply to all matters relating to this
-+ Agreement or the binary software, and Licensee agrees that any litigation will
-+ be subject to the exclusive jurisdiction of the state or federal courts Texas,
-+ USA. The United Nations Convention on Contracts for the International Sale of
-+ Goods will not apply to this Agreement.
-+
-+
-+ANNEX A
-+BINARY SOFTWARE
-+Only software in binary form may be provided under this Agreement
-+Here is a list of software covered by this Agreement:
-+class_sbl_elf.fw
-+tmu_sbl_elf.fw
-+util_sbl_elf.fw
---
-1.7.9.5
-
diff --git a/package/boot/uboot-layerscape/patches/0056-mmc-fsl_esdhc-disable-sdhc2-when-no-card-inserted-fo.patch b/package/boot/uboot-layerscape/patches/0056-mmc-fsl_esdhc-disable-sdhc2-when-no-card-inserted-fo.patch
deleted file mode 100644
index c95639f..0000000
--- a/package/boot/uboot-layerscape/patches/0056-mmc-fsl_esdhc-disable-sdhc2-when-no-card-inserted-fo.patch
+++ /dev/null
@@ -1,93 +0,0 @@
-From 22424b4b25faefec704556d47751ad54c811ee09 Mon Sep 17 00:00:00 2001
-From: Yangbo Lu <yangbo.lu at nxp.com>
-Date: Wed, 15 Jun 2016 15:45:12 +0800
-Subject: [PATCH 56/93] mmc: fsl_esdhc: disable sdhc2 when no card inserted
- for ls1012aqds
-
-This is a temporary workaround patch for ls1012aqds becasue there
-was host controller hardware issue found on some QDS boards when
-there was no eMMC adapter card inserted. This would cause below
-continious error messages in linux. So this patch is to disable
-sdhc2 when finding there isn't card inserted.
-"mmc1: Controller never released inhibit bit(s)."
-
-Signed-off-by: Yangbo Lu <yangbo.lu at nxp.com>
----
- board/freescale/ls1012aqds/ls1012aqds.c | 11 +++++++++++
- drivers/mmc/fsl_esdhc.c | 9 +++++++++
- include/fdt_support.h | 4 +++-
- 3 files changed, 23 insertions(+), 1 deletion(-)
-
-diff --git a/board/freescale/ls1012aqds/ls1012aqds.c b/board/freescale/ls1012aqds/ls1012aqds.c
-index b7365e8..56004ea 100644
---- a/board/freescale/ls1012aqds/ls1012aqds.c
-+++ b/board/freescale/ls1012aqds/ls1012aqds.c
-@@ -161,6 +161,17 @@ int select_i2c_ch_pca9547(u8 ch)
- return 0;
- }
-
-+int mmc_check_sdhc2_card(void)
-+{
-+ u8 card_id;
-+
-+ card_id = (QIXIS_READ(present2) & 0xe0) >> 5;
-+ if (card_id == 0x7)
-+ return 0;
-+ else
-+ return 1;
-+}
-+
- int dram_init(void)
- {
- mmdc_init();
-diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c
-index 2c6e175..98f3cca 100644
---- a/drivers/mmc/fsl_esdhc.c
-+++ b/drivers/mmc/fsl_esdhc.c
-@@ -774,6 +774,11 @@ int fsl_esdhc_mmc_init(bd_t *bis)
- #endif
- }
-
-+__weak int mmc_check_sdhc2_card(void)
-+{
-+ return 1;
-+}
-+
- #ifdef CONFIG_FSL_ESDHC_ADAPTER_IDENT
- void mmc_adapter_card_type_ident(void)
- {
-@@ -817,6 +822,7 @@ void mmc_adapter_card_type_ident(void)
- void fdt_fixup_esdhc(void *blob, bd_t *bd)
- {
- const char *compat = "fsl,esdhc";
-+ const char *compat1 = "fsl,ls1012a-esdhc1";
-
- #ifdef CONFIG_FSL_ESDHC_PIN_MUX
- if (!hwconfig("esdhc")) {
-@@ -839,5 +845,8 @@ void fdt_fixup_esdhc(void *blob, bd_t *bd)
- #endif
- do_fixup_by_compat(blob, compat, "status", "okay",
- 4 + 1, 1);
-+ if (!mmc_check_sdhc2_card())
-+ do_fixup_by_compat(blob, compat1, "status", "disabled",
-+ 4 + 1, 1);
- }
- #endif
-diff --git a/include/fdt_support.h b/include/fdt_support.h
-index 296add0..2e66eb1 100644
---- a/include/fdt_support.h
-+++ b/include/fdt_support.h
-@@ -240,7 +240,9 @@ int arch_fixup_memory_node(void *blob);
-
- int fdt_setup_simplefb_node(void *fdt, int node, u64 base_address, u32 width,
- u32 height, u32 stride, const char *format);
--
-+#ifdef CONFIG_FSL_ESDHC
-+int mmc_check_sdhc2_card(void);
-+#endif
- #endif /* ifdef CONFIG_OF_LIBFDT */
-
- #ifdef USE_HOSTCC
---
-1.7.9.5
-
diff --git a/package/boot/uboot-layerscape/patches/0057-driver-spi-Fix-DSPI-bug-after-adding-exceed-16MB-for.patch b/package/boot/uboot-layerscape/patches/0057-driver-spi-Fix-DSPI-bug-after-adding-exceed-16MB-for.patch
deleted file mode 100644
index 661243f..0000000
--- a/package/boot/uboot-layerscape/patches/0057-driver-spi-Fix-DSPI-bug-after-adding-exceed-16MB-for.patch
+++ /dev/null
@@ -1,92 +0,0 @@
-From 0ff26c3761e5a17d21e7ee0bd9a2068f55c84d55 Mon Sep 17 00:00:00 2001
-From: Yunhui Cui <yunhui.cui at nxp.com>
-Date: Wed, 15 Jun 2016 14:57:08 +0800
-Subject: [PATCH 57/93] driver: spi: Fix DSPI bug after adding exceed 16MB for
- QSPI
-
-=> sf probe 1:0
-SF: Detected N25Q128A with page size 256 Bytes, erase size 64 KiB, total
-16 MiB
-=> mw.l 80000000 55555555 1100
-=> mw.l 80020000 aaaaaaaa 1100
-=> sf erase 0 +1100
-SF: 65536 bytes @ 0x0 Erased: OK
-=> sf write 80020000 0 1100
-device 0 offset 0x0, size 0x1100
-SF: 4352 bytes @ 0x0 Written: OK
-=> sf read 80000000 0 1100
-device 0 offset 0x0, size 0x1100
-SF: 4352 bytes @ 0x0 Read: OK
-=> cmp.b 80000000 80020000 1100
-byte at 0x00000000800010fe (0xff) != byte at 0x00000000800210fe (0xaa)
-Total of 4350 byte(s) were the same
-
-Signed-off-by: Yunhui Cui <yunhui.cui at nxp.com>
----
- drivers/mtd/spi/spi_flash.c | 21 +++++++++++++++------
- 1 file changed, 15 insertions(+), 6 deletions(-)
-
-diff --git a/drivers/mtd/spi/spi_flash.c b/drivers/mtd/spi/spi_flash.c
-index b0f09ab..e04bd55 100644
---- a/drivers/mtd/spi/spi_flash.c
-+++ b/drivers/mtd/spi/spi_flash.c
-@@ -326,8 +326,11 @@ int spi_flash_cmd_erase_ops(struct spi_flash *flash, u32 offset, size_t len)
- return -EINVAL;
- }
- }
-+ if (flash->size > SPI_FLASH_16MB_BOUN)
-+ cmdsz = SPI_FLASH_CMD_LEN_EXT + flash->dummy_byte;
-+ else
-+ cmdsz = SPI_FLASH_CMD_LEN;
-
-- cmdsz = SPI_FLASH_CMD_LEN_EXT + flash->dummy_byte;
- cmd = calloc(1, cmdsz);
- if (!cmd) {
- debug("SF: Failed to allocate cmd\n");
-@@ -353,7 +356,7 @@ int spi_flash_cmd_erase_ops(struct spi_flash *flash, u32 offset, size_t len)
- debug("SF: erase %2x %2x %2x %2x (%x)\n", cmd[0], cmd[1],
- cmd[2], cmd[3], erase_addr);
-
-- ret = spi_flash_write_common(flash, cmd, sizeof(cmd), NULL, 0);
-+ ret = spi_flash_write_common(flash, cmd, cmdsz, NULL, 0);
- if (ret < 0) {
- debug("SF: erase failed\n");
- break;
-@@ -385,8 +388,10 @@ int spi_flash_cmd_write_ops(struct spi_flash *flash, u32 offset,
- return -EINVAL;
- }
- }
--
-- cmdsz = SPI_FLASH_CMD_LEN_EXT + flash->dummy_byte;
-+ if (flash->size > SPI_FLASH_16MB_BOUN)
-+ cmdsz = SPI_FLASH_CMD_LEN_EXT + flash->dummy_byte;
-+ else
-+ cmdsz = SPI_FLASH_CMD_LEN;
- cmd = calloc(1, cmdsz);
- if (!cmd) {
- debug("SF: Failed to allocate cmd\n");
-@@ -418,7 +423,7 @@ int spi_flash_cmd_write_ops(struct spi_flash *flash, u32 offset,
- debug("SF: 0x%p => cmd = { 0x%02x 0x%02x%02x%02x } chunk_len = %zu\n",
- buf + actual, cmd[0], cmd[1], cmd[2], cmd[3], chunk_len);
-
-- ret = spi_flash_write_common(flash, cmd, sizeof(cmd),
-+ ret = spi_flash_write_common(flash, cmd, cmdsz,
- buf + actual, chunk_len);
- if (ret < 0) {
- debug("SF: write failed\n");
-@@ -482,7 +487,11 @@ int spi_flash_cmd_read_ops(struct spi_flash *flash, u32 offset,
- return 0;
- }
-
-- cmdsz = SPI_FLASH_CMD_LEN_EXT + flash->dummy_byte;
-+ if (flash->size > SPI_FLASH_16MB_BOUN)
-+ cmdsz = SPI_FLASH_CMD_LEN_EXT + flash->dummy_byte;
-+ else
-+ cmdsz = SPI_FLASH_CMD_LEN + flash->dummy_byte;
-+
- cmd = calloc(1, cmdsz);
- if (!cmd) {
- debug("SF: Failed to allocate cmd\n");
---
-1.7.9.5
-
diff --git a/package/boot/uboot-layerscape/patches/0058-mmc-fsl_esdhc-disable-sdhc2-when-no-card-inserted-fo.patch b/package/boot/uboot-layerscape/patches/0058-mmc-fsl_esdhc-disable-sdhc2-when-no-card-inserted-fo.patch
deleted file mode 100644
index 45366ca..0000000
--- a/package/boot/uboot-layerscape/patches/0058-mmc-fsl_esdhc-disable-sdhc2-when-no-card-inserted-fo.patch
+++ /dev/null
@@ -1,56 +0,0 @@
-From 0499ca266f668c9d72217631151f3b6e15350134 Mon Sep 17 00:00:00 2001
-From: Prabhakar Kushwaha <prabhakar.kushwaha at nxp.com>
-Date: Wed, 15 Jun 2016 17:42:51 +0530
-Subject: [PATCH 58/93] mmc: fsl_esdhc: disable sdhc2 when no card inserted
- for ls1012ardb
-
-This is a temporary workaround patch for ls1012ardb becasue there
-was host controller hardware issue found on some RDB boards when
-there was no eMMC adapter card inserted. This would cause below
-continious error messages in linux. So this patch is to disable
-sdhc2 when finding there isn't card inserted.
-"mmc1: Controller never released inhibit bit(s)."
-
-Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha at nxp.com>
----
- board/freescale/ls1012ardb/ls1012ardb.c | 24 ++++++++++++++++++++++++
- 1 file changed, 24 insertions(+)
-
-diff --git a/board/freescale/ls1012ardb/ls1012ardb.c b/board/freescale/ls1012ardb/ls1012ardb.c
-index 90cbd5e..ad4d8ee 100644
---- a/board/freescale/ls1012ardb/ls1012ardb.c
-+++ b/board/freescale/ls1012ardb/ls1012ardb.c
-@@ -171,6 +171,30 @@ int board_early_init_f(void)
- return 0;
- }
-
-+int mmc_check_sdhc2_card(void)
-+{
-+ u8 io = 0;
-+ u8 is_card = 0;
-+
-+ /* Initialize i2c early for Serial flash bank information */
-+ i2c_set_bus_num(0);
-+
-+ if (i2c_read(I2C_MUX_IO1_ADDR, 0, 1, &io, 1) < 0) {
-+ printf("Error reading i2c boot information!\n");
-+ return 0; /* Don't want to hang() on this error */
-+ }
-+
-+ io = io & 0x0c;
-+
-+ switch (io) {
-+ case 0:
-+ case 8:
-+ is_card = 1;
-+ }
-+
-+ return is_card;
-+}
-+
- int board_init(void)
- {
- struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
---
-1.7.9.5
-
diff --git a/package/boot/uboot-layerscape/patches/0059-armv8-ls1012a-Make-FAT-and-EXT2-commands-support-com.patch b/package/boot/uboot-layerscape/patches/0059-armv8-ls1012a-Make-FAT-and-EXT2-commands-support-com.patch
deleted file mode 100644
index 3ce873b..0000000
--- a/package/boot/uboot-layerscape/patches/0059-armv8-ls1012a-Make-FAT-and-EXT2-commands-support-com.patch
+++ /dev/null
@@ -1,110 +0,0 @@
-From 4df84c450d7ce450986e5f1dc5e7ab164b9e0e32 Mon Sep 17 00:00:00 2001
-From: Rajesh Bhagat <rajesh.bhagat at nxp.com>
-Date: Fri, 17 Jun 2016 10:04:34 +0530
-Subject: [PATCH 59/93] armv8: ls1012a: Make FAT and EXT2 commands support
- common
-
-Makes FAT and EXT2 commands support common for LS1012A QDS,
-RDB and FRDM.
-
-Signed-off-by: Rajesh Bhagat <rajesh.bhagat at nxp.com>
----
- include/configs/ls1012a_common.h | 5 +++++
- include/configs/ls1012afrdm.h | 1 -
- include/configs/ls1012aqds.h | 6 ------
- include/configs/ls1012ardb.h | 6 ------
- 4 files changed, 5 insertions(+), 13 deletions(-)
-
-diff --git a/include/configs/ls1012a_common.h b/include/configs/ls1012a_common.h
-index 2895e7a..7c0e64f 100644
---- a/include/configs/ls1012a_common.h
-+++ b/include/configs/ls1012a_common.h
-@@ -184,6 +184,11 @@
- #define CONFIG_CMD_BOOTZ
- #define CONFIG_CMDLINE_TAG
-
-+/* Used by SCSI, MMC and USB */
-+#define CONFIG_CMD_FAT
-+#define CONFIG_DOS_PARTITION
-+#define CONFIG_CMD_EXT2
-+
- #include <asm/fsl_secure_boot.h>
-
- #endif /* __LS1012A_COMMON_H */
-diff --git a/include/configs/ls1012afrdm.h b/include/configs/ls1012afrdm.h
-index 5e619c1..432317d 100644
---- a/include/configs/ls1012afrdm.h
-+++ b/include/configs/ls1012afrdm.h
-@@ -38,7 +38,6 @@
- #define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2
- #define CONFIG_CMD_USB
- #define CONFIG_USB_STORAGE
--#define CONFIG_CMD_EXT2
-
- #define CONFIG_USB_DWC3
- #define CONFIG_USB_DWC3_GADGET
-diff --git a/include/configs/ls1012aqds.h b/include/configs/ls1012aqds.h
-index cc8e0fc..c06cfbd 100644
---- a/include/configs/ls1012aqds.h
-+++ b/include/configs/ls1012aqds.h
-@@ -34,8 +34,6 @@
- #define CONFIG_FSL_ESDHC_1_NON_REMOVABLE_CARD
- #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
- #define CONFIG_GENERIC_MMC
--#define CONFIG_CMD_FAT
--#define CONFIG_DOS_PARTITION
- #endif
- #endif /* CONFIG_EMU */
-
-@@ -45,9 +43,6 @@
- #define CONFIG_SCSI_AHCI
- #define CONFIG_SCSI_AHCI_PLAT
- #define CONFIG_CMD_SCSI
--#define CONFIG_CMD_FAT
--#define CONFIG_CMD_EXT2
--#define CONFIG_DOS_PARTITION
- #define CONFIG_BOARD_LATE_INIT
-
- #define CONFIG_SYS_SATA AHCI_BASE_ADDR
-@@ -204,7 +199,6 @@
- #if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_XHCI_USB)
- #define CONFIG_CMD_USB
- #define CONFIG_USB_STORAGE
--#define CONFIG_CMD_EXT2
-
- #define CONFIG_USB_DWC3
- #define CONFIG_USB_DWC3_GADGET
-diff --git a/include/configs/ls1012ardb.h b/include/configs/ls1012ardb.h
-index e94df74..f6b3f28 100644
---- a/include/configs/ls1012ardb.h
-+++ b/include/configs/ls1012ardb.h
-@@ -39,7 +39,6 @@
- #define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2
- #define CONFIG_CMD_USB
- #define CONFIG_USB_STORAGE
--#define CONFIG_CMD_EXT2
-
- #define CONFIG_USB_DWC3
- #define CONFIG_USB_DWC3_GADGET
-@@ -67,8 +66,6 @@
- #define CONFIG_FSL_ESDHC_1_NON_REMOVABLE_CARD
- #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
- #define CONFIG_GENERIC_MMC
--#define CONFIG_CMD_FAT
--#define CONFIG_DOS_PARTITION
- #endif
- #endif /* CONFIG_EMU */
-
-@@ -78,9 +75,6 @@
- #define CONFIG_SCSI_AHCI
- #define CONFIG_SCSI_AHCI_PLAT
- #define CONFIG_CMD_SCSI
--#define CONFIG_CMD_FAT
--#define CONFIG_CMD_EXT2
--#define CONFIG_DOS_PARTITION
- #define CONFIG_BOARD_LATE_INIT
-
- #define CONFIG_SYS_SATA AHCI_BASE_ADDR
---
-1.7.9.5
-
diff --git a/package/boot/uboot-layerscape/patches/0060-ls1012-sata-add-sata-support.patch b/package/boot/uboot-layerscape/patches/0060-ls1012-sata-add-sata-support.patch
deleted file mode 100644
index eabbbff..0000000
--- a/package/boot/uboot-layerscape/patches/0060-ls1012-sata-add-sata-support.patch
+++ /dev/null
@@ -1,58 +0,0 @@
-From 4733ade3cdc2b2fcc960d72b6ad9009a3ada38cf Mon Sep 17 00:00:00 2001
-From: Tang Yuantian <Yuantian.Tang at nxp.com>
-Date: Fri, 24 Jun 2016 10:59:46 +0800
-Subject: [PATCH 60/93] ls1012: sata: add sata support
-
-So add sata configuation for ls1012 soc.
-
-Signed-off-by: Tang Yuantian <yuantian.tang at nxp.com>
----
- arch/arm/cpu/armv8/fsl-layerscape/soc.c | 9 +++++++++
- arch/arm/include/asm/arch-fsl-layerscape/soc.h | 7 +++++++
- 2 files changed, 16 insertions(+)
-
-diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
-index 0a170eb..ab902ce 100644
---- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
-+++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
-@@ -328,10 +328,19 @@ int sata_init(void)
- {
- struct ccsr_ahci __iomem *ccsr_ahci = (void *)CONFIG_SYS_SATA;
-
-+#if defined(CONFIG_LS1043A)
- out_le32(&ccsr_ahci->ppcfg, AHCI_PORT_PHY_1_CFG);
- out_le32(&ccsr_ahci->pp2c, AHCI_PORT_PHY_2_CFG);
- out_le32(&ccsr_ahci->pp3c, AHCI_PORT_PHY_3_CFG);
- out_le32(&ccsr_ahci->ptc, AHCI_PORT_TRANS_CFG);
-+#elif defined(CONFIG_LS1012A)
-+ out_le32(&ccsr_ahci->ppcfg, LS1012A_PORT_PHY1);
-+ out_le32(&ccsr_ahci->pp2c, LS1012A_PORT_PHY2);
-+ out_le32(&ccsr_ahci->pp3c, LS1012A_PORT_PHY3);
-+ out_le32(&ccsr_ahci->pp4c, LS1012A_PORT_PHY4);
-+ out_le32(&ccsr_ahci->pp5c, LS1012A_PORT_PHY5);
-+ out_le32(&ccsr_ahci->ptc, LS1012A_PORT_TRANS);
-+#endif
-
- ahci_init((void __iomem *)CONFIG_SYS_SATA);
- scsi_scan(0);
-diff --git a/arch/arm/include/asm/arch-fsl-layerscape/soc.h b/arch/arm/include/asm/arch-fsl-layerscape/soc.h
-index 0822b49..8071114 100644
---- a/arch/arm/include/asm/arch-fsl-layerscape/soc.h
-+++ b/arch/arm/include/asm/arch-fsl-layerscape/soc.h
-@@ -60,6 +60,13 @@ struct cpu_type {
- #define AHCI_PORT_PHY_3_CFG 0x0e081509
- #define AHCI_PORT_TRANS_CFG 0x08000029
-
-+#define LS1012A_PORT_PHY1 0xa003fffe
-+#define LS1012A_PORT_PHY2 0x28184d1b
-+#define LS1012A_PORT_PHY3 0x0e081906
-+#define LS1012A_PORT_PHY4 0x064a0813
-+#define LS1012A_PORT_PHY5 0x3ffc96a4
-+#define LS1012A_PORT_TRANS 0x08000029
-+
- /* AHCI (sata) register map */
- struct ccsr_ahci {
- u32 res1[0xa4/4]; /* 0x0 - 0xa4 */
---
-1.7.9.5
-
diff --git a/package/boot/uboot-layerscape/patches/0061-ARMv8-freescale-Consolidate-PPA-flags-under-a-single.patch b/package/boot/uboot-layerscape/patches/0061-ARMv8-freescale-Consolidate-PPA-flags-under-a-single.patch
deleted file mode 100644
index 9f47de9..0000000
--- a/package/boot/uboot-layerscape/patches/0061-ARMv8-freescale-Consolidate-PPA-flags-under-a-single.patch
+++ /dev/null
@@ -1,75 +0,0 @@
-From e84c8c3f444aae4359cd4d60fabd3d2145d011b5 Mon Sep 17 00:00:00 2001
-From: Abhimanyu Saini <abhimanyu.saini at nxp.com>
-Date: Fri, 24 Jun 2016 11:03:38 +0530
-Subject: [PATCH 61/93] ARMv8: freescale: Consolidate PPA flags under a single
- flag
-
-[context adjustment]
-
-LS1012A places PPA binary on QSPI flash instead of NOR.
-So, depricating CONFIG_SYS_LS_PPA_FW_IN_NOR in favour of
-CONFIG_SYS_LS_PPA_FW_IN_XIP to prevent fragmentation of code
-by addition of a new QSPI specific flag.
-
-Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou at nxp.com>
-Signed-off-by: Abhimanyu Saini <abhimanyu.saini at nxp.com>
-Integrated-by: Jiang Yutang <yutang.jiang at nxp.com>
----
- arch/arm/cpu/armv8/fsl-layerscape/ppa.c | 4 ++--
- arch/arm/include/asm/fsl_secure_boot.h | 2 +-
- include/configs/ls1043ardb.h | 4 ++--
- 3 files changed, 5 insertions(+), 5 deletions(-)
-
-diff --git a/arch/arm/cpu/armv8/fsl-layerscape/ppa.c b/arch/arm/cpu/armv8/fsl-layerscape/ppa.c
-index 116e164..8986260 100644
---- a/arch/arm/cpu/armv8/fsl-layerscape/ppa.c
-+++ b/arch/arm/cpu/armv8/fsl-layerscape/ppa.c
-@@ -163,7 +163,7 @@ static int ppa_parse_firmware_fit_image(const void **raw_image_addr,
- void *ppa_addr;
- int ret;
-
--#ifdef CONFIG_SYS_LS_PPA_FW_IN_NOR
-+#ifdef CONFIG_SYS_LS_PPA_FW_IN_XIP
- ppa_addr = (void *)CONFIG_SYS_LS_PPA_FW_ADDR;
- #else
- #error "No CONFIG_SYS_LS_PPA_FW_IN_xxx defined"
-@@ -197,7 +197,7 @@ int sec_firmware_validate(void)
- {
- void *ppa_addr;
-
--#ifdef CONFIG_SYS_LS_PPA_FW_IN_NOR
-+#ifdef CONFIG_SYS_LS_PPA_FW_IN_XIP
- ppa_addr = (void *)CONFIG_SYS_LS_PPA_FW_ADDR;
- #else
- #error "No CONFIG_SYS_LS_PPA_FW_IN_xxx defined"
-diff --git a/arch/arm/include/asm/fsl_secure_boot.h b/arch/arm/include/asm/fsl_secure_boot.h
-index c973255..b2e9105 100644
---- a/arch/arm/include/asm/fsl_secure_boot.h
-+++ b/arch/arm/include/asm/fsl_secure_boot.h
-@@ -104,7 +104,7 @@
- #endif
-
- #ifdef CONFIG_FSL_LS_PPA
--#ifdef CONFIG_SYS_LS_PPA_FW_IN_NOR
-+#ifdef CONFIG_SYS_LS_PPA_FW_IN_XIP
- #ifdef CONFIG_LS1043A
- #define CONFIG_SYS_LS_PPA_ESBC_ADDR 0x600c0000
- #endif
-diff --git a/include/configs/ls1043ardb.h b/include/configs/ls1043ardb.h
-index af8b441..46818e8 100644
---- a/include/configs/ls1043ardb.h
-+++ b/include/configs/ls1043ardb.h
-@@ -14,8 +14,8 @@
- #define CONFIG_ARMV8_PSCI
- #define CONFIG_SYS_LS_PPA_DRAM_BLOCK_MIN_SIZE (1UL * 1024 * 1024)
-
--#define CONFIG_SYS_LS_PPA_FW_IN_NOR
--#ifdef CONFIG_SYS_LS_PPA_FW_IN_NOR
-+#define CONFIG_SYS_LS_PPA_FW_IN_XIP
-+#ifdef CONFIG_SYS_LS_PPA_FW_IN_XIP
- #define CONFIG_SYS_LS_PPA_FW_ADDR 0x60500000
- #endif
- #endif
---
-1.7.9.5
-
diff --git a/package/boot/uboot-layerscape/patches/0062-ARMv8-freescale-Fix-the-address-map-of-SCFG.patch b/package/boot/uboot-layerscape/patches/0062-ARMv8-freescale-Fix-the-address-map-of-SCFG.patch
deleted file mode 100644
index 384e7ae..0000000
--- a/package/boot/uboot-layerscape/patches/0062-ARMv8-freescale-Fix-the-address-map-of-SCFG.patch
+++ /dev/null
@@ -1,27 +0,0 @@
-From f1b3374b2f99b30795423a4ae514e634bb84a1d9 Mon Sep 17 00:00:00 2001
-From: Abhimanyu Saini <abhimanyu.saini at nxp.com>
-Date: Fri, 24 Jun 2016 10:32:59 +0530
-Subject: [PATCH 62/93] ARMv8: freescale: Fix the address map of SCFG
-
-Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou at nxp.com>
-Signed-off-by: Abhimanyu Saini <abhimanyu.saini at nxp.com>
----
- .../include/asm/arch-fsl-layerscape/immap_lsch2.h | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
-diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
-index a7bc2a4..696d0a3 100644
---- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
-+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
-@@ -450,7 +450,7 @@ struct ccsr_scfg {
- u32 pfebsbcr;
- u8 res_460[0x484-0x460];
- u32 mdioselcr;
-- u8 res_468[0x600-0x468];
-+ u8 res_488[0x600-0x488];
- u32 scratchrw[4];
- u8 res_610[0x680-0x610];
- u32 corebcr;
---
-1.7.9.5
-
diff --git a/package/boot/uboot-layerscape/patches/0063-board-freescale-ls1012a-Enable-secure-DDR-on-LS1012A.patch b/package/boot/uboot-layerscape/patches/0063-board-freescale-ls1012a-Enable-secure-DDR-on-LS1012A.patch
deleted file mode 100644
index 52bc555..0000000
--- a/package/boot/uboot-layerscape/patches/0063-board-freescale-ls1012a-Enable-secure-DDR-on-LS1012A.patch
+++ /dev/null
@@ -1,157 +0,0 @@
-From 1882af9f2c7533c6cd2dea5811b4e69f9a151f29 Mon Sep 17 00:00:00 2001
-From: Abhimanyu Saini <abhimanyu.saini at nxp.com>
-Date: Fri, 24 Jun 2016 10:45:39 +0530
-Subject: [PATCH 63/93] board: freescale: ls1012a: Enable secure DDR on
- LS1012A platforms
-
-PPA binary needs to be relocated on secure DDR, hence marking out
-a portion of DDR as secure if CONFIG_SYS_MEM_RESERVE_SECURE flag
-is set
-
-Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou at nxp.com>
-Signed-off-by: Abhimanyu Saini <abhimanyu.saini at nxp.com>
----
- arch/arm/include/asm/arch-fsl-layerscape/config.h | 3 +++
- board/freescale/ls1012afrdm/ls1012afrdm.c | 28 +++++++++++++++++++++
- board/freescale/ls1012aqds/ls1012aqds.c | 28 +++++++++++++++++++++
- board/freescale/ls1012ardb/ls1012ardb.c | 28 +++++++++++++++++++++
- include/configs/ls1012a_common.h | 1 +
- 5 files changed, 88 insertions(+)
-
-diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h b/arch/arm/include/asm/arch-fsl-layerscape/config.h
-index 679be6c..efaa79a 100644
---- a/arch/arm/include/asm/arch-fsl-layerscape/config.h
-+++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h
-@@ -222,6 +222,9 @@
- #define GICD_BASE 0x01401000
- #define GICC_BASE 0x01402000
-
-+#define CONFIG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30)
-+#define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_DDR_BLOCK1_SIZE
-+
- #define CONFIG_SYS_FSL_CCSR_GUR_BE
- #define CONFIG_SYS_FSL_CCSR_SCFG_BE
- #define CONFIG_SYS_FSL_ESDHC_BE
-diff --git a/board/freescale/ls1012afrdm/ls1012afrdm.c b/board/freescale/ls1012afrdm/ls1012afrdm.c
-index 6856250..c691a76 100644
---- a/board/freescale/ls1012afrdm/ls1012afrdm.c
-+++ b/board/freescale/ls1012afrdm/ls1012afrdm.c
-@@ -176,3 +176,31 @@ int ft_board_setup(void *blob, bd_t *bd)
-
- return 0;
- }
-+
-+void dram_init_banksize(void)
-+{
-+ /*
-+ * gd->secure_ram tracks the location of secure memory.
-+ * It was set as if the memory starts from 0.
-+ * The address needs to add the offset of its bank.
-+ */
-+ gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
-+ if (gd->ram_size > CONFIG_SYS_DDR_BLOCK1_SIZE) {
-+ gd->bd->bi_dram[0].size = CONFIG_SYS_DDR_BLOCK1_SIZE;
-+ gd->bd->bi_dram[1].start = CONFIG_SYS_DDR_BLOCK2_BASE;
-+ gd->bd->bi_dram[1].size = gd->ram_size -
-+ CONFIG_SYS_DDR_BLOCK1_SIZE;
-+#ifdef CONFIG_SYS_MEM_RESERVE_SECURE
-+ gd->secure_ram = gd->bd->bi_dram[1].start +
-+ gd->secure_ram -
-+ CONFIG_SYS_DDR_BLOCK1_SIZE;
-+ gd->secure_ram |= MEM_RESERVE_SECURE_MAINTAINED;
-+#endif
-+ } else {
-+ gd->bd->bi_dram[0].size = gd->ram_size;
-+#ifdef CONFIG_SYS_MEM_RESERVE_SECURE
-+ gd->secure_ram = gd->bd->bi_dram[0].start + gd->secure_ram;
-+ gd->secure_ram |= MEM_RESERVE_SECURE_MAINTAINED;
-+#endif
-+ }
-+}
-diff --git a/board/freescale/ls1012aqds/ls1012aqds.c b/board/freescale/ls1012aqds/ls1012aqds.c
-index 56004ea..516f0c3 100644
---- a/board/freescale/ls1012aqds/ls1012aqds.c
-+++ b/board/freescale/ls1012aqds/ls1012aqds.c
-@@ -240,3 +240,31 @@ int ft_board_setup(void *blob, bd_t *bd)
- return 0;
- }
- #endif
-+
-+void dram_init_banksize(void)
-+{
-+ /*
-+ * gd->secure_ram tracks the location of secure memory.
-+ * It was set as if the memory starts from 0.
-+ * The address needs to add the offset of its bank.
-+ */
-+ gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
-+ if (gd->ram_size > CONFIG_SYS_DDR_BLOCK1_SIZE) {
-+ gd->bd->bi_dram[0].size = CONFIG_SYS_DDR_BLOCK1_SIZE;
-+ gd->bd->bi_dram[1].start = CONFIG_SYS_DDR_BLOCK2_BASE;
-+ gd->bd->bi_dram[1].size = gd->ram_size -
-+ CONFIG_SYS_DDR_BLOCK1_SIZE;
-+#ifdef CONFIG_SYS_MEM_RESERVE_SECURE
-+ gd->secure_ram = gd->bd->bi_dram[1].start +
-+ gd->secure_ram -
-+ CONFIG_SYS_DDR_BLOCK1_SIZE;
-+ gd->secure_ram |= MEM_RESERVE_SECURE_MAINTAINED;
-+#endif
-+ } else {
-+ gd->bd->bi_dram[0].size = gd->ram_size;
-+#ifdef CONFIG_SYS_MEM_RESERVE_SECURE
-+ gd->secure_ram = gd->bd->bi_dram[0].start + gd->secure_ram;
-+ gd->secure_ram |= MEM_RESERVE_SECURE_MAINTAINED;
-+#endif
-+ }
-+}
-diff --git a/board/freescale/ls1012ardb/ls1012ardb.c b/board/freescale/ls1012ardb/ls1012ardb.c
-index ad4d8ee..8340f14 100644
---- a/board/freescale/ls1012ardb/ls1012ardb.c
-+++ b/board/freescale/ls1012ardb/ls1012ardb.c
-@@ -235,3 +235,31 @@ int ft_board_setup(void *blob, bd_t *bd)
-
- return 0;
- }
-+
-+void dram_init_banksize(void)
-+{
-+ /*
-+ * gd->secure_ram tracks the location of secure memory.
-+ * It was set as if the memory starts from 0.
-+ * The address needs to add the offset of its bank.
-+ */
-+ gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
-+ if (gd->ram_size > CONFIG_SYS_DDR_BLOCK1_SIZE) {
-+ gd->bd->bi_dram[0].size = CONFIG_SYS_DDR_BLOCK1_SIZE;
-+ gd->bd->bi_dram[1].start = CONFIG_SYS_DDR_BLOCK2_BASE;
-+ gd->bd->bi_dram[1].size = gd->ram_size -
-+ CONFIG_SYS_DDR_BLOCK1_SIZE;
-+#ifdef CONFIG_SYS_MEM_RESERVE_SECURE
-+ gd->secure_ram = gd->bd->bi_dram[1].start +
-+ gd->secure_ram -
-+ CONFIG_SYS_DDR_BLOCK1_SIZE;
-+ gd->secure_ram |= MEM_RESERVE_SECURE_MAINTAINED;
-+#endif
-+ } else {
-+ gd->bd->bi_dram[0].size = gd->ram_size;
-+#ifdef CONFIG_SYS_MEM_RESERVE_SECURE
-+ gd->secure_ram = gd->bd->bi_dram[0].start + gd->secure_ram;
-+ gd->secure_ram |= MEM_RESERVE_SECURE_MAINTAINED;
-+#endif
-+ }
-+}
-diff --git a/include/configs/ls1012a_common.h b/include/configs/ls1012a_common.h
-index 7c0e64f..4c7c697 100644
---- a/include/configs/ls1012a_common.h
-+++ b/include/configs/ls1012a_common.h
-@@ -36,6 +36,7 @@
- #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000
- #define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0
- #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
-+#define CONFIG_SYS_DDR_BLOCK2_BASE 0x880000000ULL
-
- /* Generic Timer Definitions */
- #define COUNTER_FREQUENCY 25000000 /* 12MHz */
---
-1.7.9.5
-
diff --git a/package/boot/uboot-layerscape/patches/0064-board-freescale-ls1012a-Intergrate-and-enable-PPA-on.patch b/package/boot/uboot-layerscape/patches/0064-board-freescale-ls1012a-Intergrate-and-enable-PPA-on.patch
deleted file mode 100644
index eaff510..0000000
--- a/package/boot/uboot-layerscape/patches/0064-board-freescale-ls1012a-Intergrate-and-enable-PPA-on.patch
+++ /dev/null
@@ -1,64 +0,0 @@
-From 31f17073ffb1501574ad4cb8dffd507dee40e69a Mon Sep 17 00:00:00 2001
-From: Abhimanyu Saini <abhimanyu.saini at nxp.com>
-Date: Thu, 16 Jun 2016 13:49:17 +0530
-Subject: [PATCH 64/93] board: freescale: ls1012a: Intergrate and enable PPA
- on LS1012ARDB
-
-Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou at nxp.com>
-Signed-off-by: Abhimanyu Saini <abhimanyu.saini at nxp.com>
----
- board/freescale/ls1012ardb/ls1012ardb.c | 10 ++++++++++
- include/configs/ls1012ardb.h | 9 +++++++++
- 2 files changed, 19 insertions(+)
-
-diff --git a/board/freescale/ls1012ardb/ls1012ardb.c b/board/freescale/ls1012ardb/ls1012ardb.c
-index 8340f14..7f7503c 100644
---- a/board/freescale/ls1012ardb/ls1012ardb.c
-+++ b/board/freescale/ls1012ardb/ls1012ardb.c
-@@ -198,6 +198,9 @@ int mmc_check_sdhc2_card(void)
- int board_init(void)
- {
- struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
-+#ifdef CONFIG_FSL_LS_PPA
-+ u64 ppa_entry;
-+#endif
- /*
- * Set CCI-400 control override register to enable barrier
- * transaction
-@@ -216,6 +219,13 @@ int board_init(void)
- sec_init();
- #endif
-
-+#ifdef CONFIG_FSL_LS_PPA
-+ ppa_init_pre(&ppa_entry);
-+
-+ if (ppa_entry)
-+ ppa_init_entry((void *)ppa_entry);
-+#endif
-+
- return 0;
- }
-
-diff --git a/include/configs/ls1012ardb.h b/include/configs/ls1012ardb.h
-index f6b3f28..fdaea3e 100644
---- a/include/configs/ls1012ardb.h
-+++ b/include/configs/ls1012ardb.h
-@@ -9,6 +9,15 @@
-
- #include "ls1012a_common.h"
-
-+#define CONFIG_FSL_LS_PPA
-+#if defined(CONFIG_FSL_LS_PPA)
-+#define CONFIG_SYS_LS_PPA_DRAM_BLOCK_MIN_SIZE (1UL * 1024 * 1024)
-+
-+#define CONFIG_SYS_LS_PPA_FW_IN_XIP
-+#ifdef CONFIG_SYS_LS_PPA_FW_IN_XIP
-+#define CONFIG_SYS_LS_PPA_FW_ADDR 0x40500000
-+#endif
-+#endif
-
- #define CONFIG_DIMM_SLOTS_PER_CTLR 1
- #define CONFIG_CHIP_SELECTS_PER_CTRL 1
---
-1.7.9.5
-
diff --git a/package/boot/uboot-layerscape/patches/0065-docs-fsl-ppa-Add-documentation-for-PPA-trusted-FW.patch b/package/boot/uboot-layerscape/patches/0065-docs-fsl-ppa-Add-documentation-for-PPA-trusted-FW.patch
deleted file mode 100644
index e8dc6eb..0000000
--- a/package/boot/uboot-layerscape/patches/0065-docs-fsl-ppa-Add-documentation-for-PPA-trusted-FW.patch
+++ /dev/null
@@ -1,47 +0,0 @@
-From 39f95bb22c03b18ac6c4ef1b4485414dd4a303cb Mon Sep 17 00:00:00 2001
-From: Abhimanyu Saini <abhimanyu.saini at nxp.com>
-Date: Fri, 24 Jun 2016 14:37:42 +0530
-Subject: [PATCH 65/93] docs: fsl-ppa: Add documentation for PPA trusted FW
-
-Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou at nxp.com>
-Signed-off-by: Abhimanyu Saini <abhimanyu.saini at nxp.com>
----
- doc/README.fsl-ppa | 26 ++++++++++++++++++++++++++
- 1 file changed, 26 insertions(+)
- create mode 100644 doc/README.fsl-ppa
-
-diff --git a/doc/README.fsl-ppa b/doc/README.fsl-ppa
-new file mode 100644
-index 0000000..76cd01f
---- /dev/null
-+++ b/doc/README.fsl-ppa
-@@ -0,0 +1,26 @@
-+PPA FW for U-boot
-+
-+Summary
-+=======
-+PPA is a trusted firmware for ARMv8 , that handles smc calls from lower
-+exception levels, like power state co-ordination interface call or
-+smc calls to trusted OS from the Linux kernel.
-+
-+Notes
-+=====
-+
-+1. Currenly, u-boot run at the highest exception level processor
-+ supported, which is EL3 in case of ARMv8, if PPA FW is incorporated
-+ U-boot copies it to secure location in DDR.
-+2. During init U-boot passes control to PPA FW and before returning
-+ the core jumps to EL2.
-+
-+Using PPA
-+=========
-+1. Ensure CONFIG_FSL_LS_PPA is set for your platform
-+2. Program PPA binary on address CONFIG_SYS_LS_PPA_FW_ADDR on flash
-+
-+Contributors
-+============
-+ Hou Zhiqiang <Zhiqiang.Hou at nxp.com>
-+ Abhimanyu Saini <abhimanyu.saini at nxp.com>
---
-1.7.9.5
-
diff --git a/package/boot/uboot-layerscape/patches/0066-armv8-pfe-Enable-UDP-checksum-for-proper-tftp-operat.patch b/package/boot/uboot-layerscape/patches/0066-armv8-pfe-Enable-UDP-checksum-for-proper-tftp-operat.patch
deleted file mode 100644
index b375cf7..0000000
--- a/package/boot/uboot-layerscape/patches/0066-armv8-pfe-Enable-UDP-checksum-for-proper-tftp-operat.patch
+++ /dev/null
@@ -1,113 +0,0 @@
-From 35efc0f34b56ca9d5fb5d080d5de0833ded7e3b8 Mon Sep 17 00:00:00 2001
-From: Anji J <anji.jagarlmudi at freescale.com>
-Date: Tue, 21 Jun 2016 13:25:12 +0530
-Subject: [PATCH 66/93] armv8:pfe Enable UDP checksum for proper tftp
- operation
-
-1. Add CONFIG_UDP_CHECKSUM flag to perform UDP checksum in S/W
- instead of hardware
-2. Rx descriptor model changed back to original
- removed strobe mode
-3. Send more than one dummy packets to bring HIF BD to idle state
-
-Signed-off-by: Anji J <anji.jagarlmudi at freescale.com>
----
- common/cmd_pfe_commands.c | 12 +++++++-----
- drivers/net/pfe_eth/pfe_driver.c | 19 +++----------------
- include/configs/ls1012a_common.h | 1 +
- 3 files changed, 11 insertions(+), 21 deletions(-)
-
-diff --git a/common/cmd_pfe_commands.c b/common/cmd_pfe_commands.c
-index 92917e0..3575ad4 100644
---- a/common/cmd_pfe_commands.c
-+++ b/common/cmd_pfe_commands.c
-@@ -929,7 +929,7 @@ static void send_dummy_pkt_to_hif(void)
-
- static void pfe_command_stop(int argc, char * const argv[])
- {
-- int id;
-+ int id, hif_stop_loop = 10;
- u32 rx_status;
- printf("Stopping PFE... \n");
-
-@@ -937,10 +937,12 @@ static void pfe_command_stop(int argc, char * const argv[])
- hif_rx_desc_disable();
-
- /*If HIF Rx BDP is busy send a dummy packet */
-- rx_status = readl(HIF_RX_STATUS);
-- if(rx_status & BDP_CSR_RX_DMA_ACTV)
-- send_dummy_pkt_to_hif();
-- udelay(10);
-+ do {
-+ rx_status = readl(HIF_RX_STATUS);
-+ if (rx_status & BDP_CSR_RX_DMA_ACTV)
-+ send_dummy_pkt_to_hif();
-+ udelay(10);
-+ } while (hif_stop_loop--);
-
- if(readl(HIF_RX_STATUS) & BDP_CSR_RX_DMA_ACTV)
- printf("Unable to stop HIF\n");
-diff --git a/drivers/net/pfe_eth/pfe_driver.c b/drivers/net/pfe_eth/pfe_driver.c
-index e252fcf..6774fb4 100644
---- a/drivers/net/pfe_eth/pfe_driver.c
-+++ b/drivers/net/pfe_eth/pfe_driver.c
-@@ -37,13 +37,8 @@ int pfe_recv(unsigned int *pkt_ptr, int *phy_port)
-
- bd = rx_desc->rxBase + rx_desc->rxToRead;
-
-- if (bd->ctrl & BD_CTRL_DESC_EN) {
-- if(!(readl(HIF_RX_STATUS) & BDP_CSR_RX_DMA_ACTV)){
-- /*If BDP is not active give write strobe */
-- writel((readl(HIF_RX_CTRL) | HIF_CTRL_BDP_CH_START_WSTB), HIF_RX_CTRL);
-- }
-+ if (bd->ctrl & BD_CTRL_DESC_EN)
- return len; //No pending Rx packet
-- }
-
- /* this len include hif_header(8bytes) */
- len = bd->ctrl & 0xFFFF;
-@@ -72,15 +67,10 @@ int pfe_recv(unsigned int *pkt_ptr, int *phy_port)
- *phy_port = hif_header->port_no;
- len -= sizeof(struct hif_header_s);
-
--#if defined(PFE_LS1012A_RESET_WA)
-- /* reset bd control field */
-- ctrl = (MAX_FRAME_SIZE | BD_CTRL_LAST_BD | BD_CTRL_LIFM | BD_CTRL_DESC_EN | BD_CTRL_DIR);
--#else
- /* reset bd control field */
- ctrl = (MAX_FRAME_SIZE | BD_CTRL_LIFM | BD_CTRL_DESC_EN | BD_CTRL_DIR);
-- /* If we use BD_CTRL_LAST_BD, rxToRead never changes */
- rx_desc->rxToRead = (rx_desc->rxToRead + 1) & (rx_desc->rxRingSize - 1);
--#endif
-+
- bd->ctrl = ctrl;
- bd->status = 0;
-
-@@ -363,11 +353,8 @@ static int hif_rx_desc_init(struct pfe *pfe)
-
- memset(bd_va, 0, sizeof(struct bufDesc) * rx_desc->rxRingSize);
-
--#if defined(PFE_LS1012A_RESET_WA)
-- ctrl = (MAX_FRAME_SIZE | BD_CTRL_LAST_BD | BD_CTRL_DESC_EN | BD_CTRL_DIR | BD_CTRL_LIFM);
--#else
- ctrl = (MAX_FRAME_SIZE | BD_CTRL_DESC_EN | BD_CTRL_DIR | BD_CTRL_LIFM);
--#endif
-+
- for (i=0; i < rx_desc->rxRingSize; i++) {
- bd_va->next = (unsigned long)(bd_pa + 1);
- bd_va->ctrl = ctrl;
-diff --git a/include/configs/ls1012a_common.h b/include/configs/ls1012a_common.h
-index 4c7c697..47b8ec3 100644
---- a/include/configs/ls1012a_common.h
-+++ b/include/configs/ls1012a_common.h
-@@ -116,6 +116,7 @@
- #ifdef CONFIG_FSL_PPFE
- #define CONFIG_CMD_PFE_COMMANDS
- #define CONFIG_UTIL_PE_DISABLED
-+#define CONFIG_UDP_CHECKSUM
-
- #endif
-
---
-1.7.9.5
-
diff --git a/package/boot/uboot-layerscape/patches/0067-armv8-ls1012a-DDR-optmizations.patch b/package/boot/uboot-layerscape/patches/0067-armv8-ls1012a-DDR-optmizations.patch
deleted file mode 100644
index 7c532fb..0000000
--- a/package/boot/uboot-layerscape/patches/0067-armv8-ls1012a-DDR-optmizations.patch
+++ /dev/null
@@ -1,90 +0,0 @@
-From 8b6c309e5e55670f429730449d9921987636c8ec Mon Sep 17 00:00:00 2001
-From: Calvin Johnson <calvin.johnson at freescale.com>
-Date: Wed, 8 Jun 2016 17:04:58 +0530
-Subject: [PATCH 67/93] armv8: ls1012a: DDR optmizations
-
-Enable DDR row-bank-column decoding. DDR address will
-be decoded as row-bank-column instead of bank-row-column.
-This will improve performance of serial data transfers.
-
-Refresh cycle value must be selected based on the frequency
-of DDR. tREFI = 7.8 us as per JEDEC. The value for MDREF[REF_CNT]
-should be based on round up (tREFI/tCK) formula. For 500MHz, mdref
-value should be 0x0f3c8000.
-
-Signed-off-by: Calvin Johnson <calvin.johnson at nxp.com>
----
- board/freescale/ls1012afrdm/ls1012afrdm.c | 4 ++--
- board/freescale/ls1012aqds/ls1012aqds.c | 4 ++--
- board/freescale/ls1012ardb/ls1012ardb.c | 4 ++--
- 3 files changed, 6 insertions(+), 6 deletions(-)
-
-diff --git a/board/freescale/ls1012afrdm/ls1012afrdm.c b/board/freescale/ls1012afrdm/ls1012afrdm.c
-index c691a76..4b7902a 100644
---- a/board/freescale/ls1012afrdm/ls1012afrdm.c
-+++ b/board/freescale/ls1012afrdm/ls1012afrdm.c
-@@ -59,7 +59,7 @@ void mmdc_init(void)
- out_be32(&mmdc->mdcfg2, 0x01ff00db);
-
- /* other parms */
-- out_be32(&mmdc->mdmisc, 0x00000680);
-+ out_be32(&mmdc->mdmisc, 0x00001680);
- out_be32(&mmdc->mpmur0, 0x00000800);
- out_be32(&mmdc->mdrwd, 0x00002000);
- out_be32(&mmdc->mpodtctrl, 0x0000022a);
-@@ -118,7 +118,7 @@ void mmdc_init(void)
- out_be32(&mmdc->mapsr, 0x00001067);
-
- /* refresh scheme */
-- set_wait_for_bits_clear(&mmdc->mdref, 0x103e8000, 0x00000001);
-+ set_wait_for_bits_clear(&mmdc->mdref, 0x0f3c8000, 0x00000001);
-
- /* disable CON_REQ */
- out_be32(&mmdc->mdscr, 0x0);
-diff --git a/board/freescale/ls1012aqds/ls1012aqds.c b/board/freescale/ls1012aqds/ls1012aqds.c
-index 516f0c3..4ae8def 100644
---- a/board/freescale/ls1012aqds/ls1012aqds.c
-+++ b/board/freescale/ls1012aqds/ls1012aqds.c
-@@ -82,7 +82,7 @@ void mmdc_init(void)
- out_be32(&mmdc->mdcfg2, 0x01ff00db);
-
- /* other parms */
-- out_be32(&mmdc->mdmisc, 0x00000680);
-+ out_be32(&mmdc->mdmisc, 0x00001680);
- out_be32(&mmdc->mpmur0, 0x00000800);
- out_be32(&mmdc->mdrwd, 0x00002000);
- out_be32(&mmdc->mpodtctrl, 0x0000022a);
-@@ -142,7 +142,7 @@ void mmdc_init(void)
- out_be32(&mmdc->mapsr, 0x00001067);
-
- /* refresh scheme */
-- set_wait_for_bits_clear(&mmdc->mdref, 0x103e8000, 0x00000001);
-+ set_wait_for_bits_clear(&mmdc->mdref, 0x0f3c8000, 0x00000001);
-
- /* disable CON_REQ */
- out_be32(&mmdc->mdscr, 0x0);
-diff --git a/board/freescale/ls1012ardb/ls1012ardb.c b/board/freescale/ls1012ardb/ls1012ardb.c
-index 7f7503c..06e1f6b 100644
---- a/board/freescale/ls1012ardb/ls1012ardb.c
-+++ b/board/freescale/ls1012ardb/ls1012ardb.c
-@@ -88,7 +88,7 @@ void mmdc_init(void)
- out_be32(&mmdc->mdcfg2, 0x01ff00db);
-
- /* other parms */
-- out_be32(&mmdc->mdmisc, 0x00000680);
-+ out_be32(&mmdc->mdmisc, 0x00001680);
- out_be32(&mmdc->mpmur0, 0x00000800);
- out_be32(&mmdc->mdrwd, 0x00002000);
- out_be32(&mmdc->mpodtctrl, 0x0000022a);
-@@ -148,7 +148,7 @@ void mmdc_init(void)
- out_be32(&mmdc->mapsr, 0x00001067);
-
- /* refresh scheme */
-- set_wait_for_bits_clear(&mmdc->mdref, 0x103e8000, 0x00000001);
-+ set_wait_for_bits_clear(&mmdc->mdref, 0x0f3c8000, 0x00000001);
-
- /* disable CON_REQ */
- out_be32(&mmdc->mdscr, 0x0);
---
-1.7.9.5
-
diff --git a/package/boot/uboot-layerscape/patches/0068-driver-pfe_eth-use-ifdef-instead-of-if.patch b/package/boot/uboot-layerscape/patches/0068-driver-pfe_eth-use-ifdef-instead-of-if.patch
deleted file mode 100644
index 84a29ed..0000000
--- a/package/boot/uboot-layerscape/patches/0068-driver-pfe_eth-use-ifdef-instead-of-if.patch
+++ /dev/null
@@ -1,29 +0,0 @@
-From 7715b8d4b833dfe3d997f21c8055d33975ed84c8 Mon Sep 17 00:00:00 2001
-From: Calvin Johnson <calvin.johnson at nxp.com>
-Date: Wed, 29 Jun 2016 16:03:33 +0530
-Subject: [PATCH 68/93] driver: pfe_eth: use #ifdef instead of #if
-
-There is no need of checking the value of DEBUG,
-so use #ifdef preprocessor directive instead of #if.
-
-Signed-off-by: Calvin Johnson <calvin.johnson at nxp.com>
----
- drivers/net/pfe_eth/pfe_driver.c | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
-diff --git a/drivers/net/pfe_eth/pfe_driver.c b/drivers/net/pfe_eth/pfe_driver.c
-index 6774fb4..a3a3e49 100644
---- a/drivers/net/pfe_eth/pfe_driver.c
-+++ b/drivers/net/pfe_eth/pfe_driver.c
-@@ -50,7 +50,7 @@ int pfe_recv(unsigned int *pkt_ptr, int *phy_port)
- dprint("Pkt recv'd: Pkt ptr(%p), len(%d), gemac_port(%d) status(%08x)\n",
- hif_header, len, hif_header->port_no, bd->status);
-
--#if DEBUG
-+#ifdef DEBUG
- {
- int i;
- unsigned char *p = (unsigned char *)hif_header;
---
-1.7.9.5
-
diff --git a/package/boot/uboot-layerscape/patches/0069-armv8-pfe-frdm-Reset-external-PHYs-before-driver-sta.patch b/package/boot/uboot-layerscape/patches/0069-armv8-pfe-frdm-Reset-external-PHYs-before-driver-sta.patch
deleted file mode 100644
index ea67c6f..0000000
--- a/package/boot/uboot-layerscape/patches/0069-armv8-pfe-frdm-Reset-external-PHYs-before-driver-sta.patch
+++ /dev/null
@@ -1,43 +0,0 @@
-From 4f217aaf4bca500f13b4c560a6bbb3708c8e5dc2 Mon Sep 17 00:00:00 2001
-From: Bhaskar Upadhaya <Bhaskar.Upadhaya at nxp.com>
-Date: Fri, 1 Jul 2016 04:37:53 +0530
-Subject: [PATCH 69/93] armv8:pfe:frdm Reset external PHYs before driver
- starts
-
-- Disable CONFIG_RESET_PHY_R, it is resetting PHYs after driver started
-- Call reset_phy() before driver initialization
-
-Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya at nxp.com>
-Signed-off-by: Anji J <anji.jagarlmudi at freescale.com>
----
- board/freescale/ls1012afrdm/eth.c | 1 +
- include/configs/ls1012afrdm.h | 1 -
- 2 files changed, 1 insertion(+), 1 deletion(-)
-
-diff --git a/board/freescale/ls1012afrdm/eth.c b/board/freescale/ls1012afrdm/eth.c
-index 90ed66b..be17310 100644
---- a/board/freescale/ls1012afrdm/eth.c
-+++ b/board/freescale/ls1012afrdm/eth.c
-@@ -46,6 +46,7 @@ int board_eth_init(bd_t *bis)
- struct mdio_info mac1_mdio_info;
- struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
-
-+ reset_phy();
-
- /*TODO Following config should be done for all boards, where is the right place to put this */
- out_be32(&scfg->pfeasbcr, in_be32(&scfg->pfeasbcr) | SCFG_PPFEASBCR_AWCACHE0);
-diff --git a/include/configs/ls1012afrdm.h b/include/configs/ls1012afrdm.h
-index 432317d..3de0cea 100644
---- a/include/configs/ls1012afrdm.h
-+++ b/include/configs/ls1012afrdm.h
-@@ -23,7 +23,6 @@
- #define EMAC2_PHY_ADDR 0x1
- #define CONFIG_PHYLIB
- #define CONFIG_PHY_REALTEK
--#define CONFIG_RESET_PHY_R
- #endif
- /*
- * USB
---
-1.7.9.5
-
diff --git a/package/boot/uboot-layerscape/patches/0070-board-ls1012afrdm-overwrite-CONFIG_EXTRA_ENV_SETTING.patch b/package/boot/uboot-layerscape/patches/0070-board-ls1012afrdm-overwrite-CONFIG_EXTRA_ENV_SETTING.patch
deleted file mode 100644
index 6343545..0000000
--- a/package/boot/uboot-layerscape/patches/0070-board-ls1012afrdm-overwrite-CONFIG_EXTRA_ENV_SETTING.patch
+++ /dev/null
@@ -1,45 +0,0 @@
-From 3df085e06da99123410e2394c8c6764ab0e98f3a Mon Sep 17 00:00:00 2001
-From: Prabhakar Kushwaha <prabhakar.kushwaha at nxp.com>
-Date: Mon, 11 Jul 2016 16:18:28 +0530
-Subject: [PATCH 70/93] board: ls1012afrdm: overwrite
- CONFIG_EXTRA_ENV_SETTINGS
-
-Kernel load address for ls1012afrdm is 0x96000000 because it has
-512MB of DDR.
-
-So overwrite CONFIG_EXTRA_ENV_SETTINGS with updated kernel_load
-address.
-
-Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha at nxp.com>
----
- include/configs/ls1012afrdm.h | 16 ++++++++++++++++
- 1 file changed, 16 insertions(+)
-
-diff --git a/include/configs/ls1012afrdm.h b/include/configs/ls1012afrdm.h
-index 3de0cea..622c774 100644
---- a/include/configs/ls1012afrdm.h
-+++ b/include/configs/ls1012afrdm.h
-@@ -59,4 +59,20 @@
- #define CONFIG_SYS_MEMTEST_START 0x80000000
- #define CONFIG_SYS_MEMTEST_END 0x9fffffff
-
-+#undef CONFIG_EXTRA_ENV_SETTINGS
-+#define CONFIG_EXTRA_ENV_SETTINGS \
-+ "initrd_high=0xffffffff\0" \
-+ "verify=no\0" \
-+ "hwconfig=fsl_ddr:bank_intlv=auto\0" \
-+ "loadaddr=0x80100000\0" \
-+ "kernel_addr=0x100000\0" \
-+ "ramdisk_addr=0x800000\0" \
-+ "ramdisk_size=0x2000000\0" \
-+ "fdt_high=0xffffffffffffffff\0" \
-+ "initrd_high=0xffffffffffffffff\0" \
-+ "kernel_start=0xa00000\0" \
-+ "kernel_load=0x96000000\0" \
-+ "kernel_size=0x2800000\0" \
-+ "console=ttyAMA0,38400n8\0"
-+
- #endif /* __LS1012ARDB_H__ */
---
-1.7.9.5
-
diff --git a/package/boot/uboot-layerscape/patches/0071-driver-fsl_qspi-disable-AHB-buffer-prefetch.patch b/package/boot/uboot-layerscape/patches/0071-driver-fsl_qspi-disable-AHB-buffer-prefetch.patch
deleted file mode 100644
index a7cb7b4..0000000
--- a/package/boot/uboot-layerscape/patches/0071-driver-fsl_qspi-disable-AHB-buffer-prefetch.patch
+++ /dev/null
@@ -1,58 +0,0 @@
-From e2a5bba97cd6e42b2b631bd17012aa26ffdb5f67 Mon Sep 17 00:00:00 2001
-From: Yunhui Cui <yunhui.cui at nxp.com>
-Date: Tue, 12 Jul 2016 10:30:08 +0800
-Subject: [PATCH 71/93] driver: fsl_qspi: disable AHB buffer prefetch
-
-Errata: A-009282: QuadSPI data pre-fetch can result in incorrect data
-When we enable the CONFIG_SYS_FSL_QSPI_AHB, we need this errata workaround.
-
-Signed-off-by: Yunhui Cui <yunhui.cui at nxp.com>
----
- drivers/spi/fsl_qspi.c | 12 +++++++++++-
- include/configs/ls1012a_common.h | 1 +
- 2 files changed, 12 insertions(+), 1 deletion(-)
-
-diff --git a/drivers/spi/fsl_qspi.c b/drivers/spi/fsl_qspi.c
-index 09759fa..f1c87f5 100644
---- a/drivers/spi/fsl_qspi.c
-+++ b/drivers/spi/fsl_qspi.c
-@@ -441,13 +441,23 @@ static void qspi_enable_ddr_mode(struct fsl_qspi_priv *priv)
- static void qspi_init_ahb_read(struct fsl_qspi_priv *priv)
- {
- struct fsl_qspi_regs *regs = priv->regs;
-+ int rx_size = 0x80;
-
- /* AHB configuration for access buffer 0/1/2 .*/
- qspi_write32(priv->flags, ®s->buf0cr, QSPI_BUFXCR_INVALID_MSTRID);
- qspi_write32(priv->flags, ®s->buf1cr, QSPI_BUFXCR_INVALID_MSTRID);
- qspi_write32(priv->flags, ®s->buf2cr, QSPI_BUFXCR_INVALID_MSTRID);
-+
-+#ifdef CONFIG_SYS_FSL_ERRATUM_A009282
-+ /*A-009282: QuadSPI data pre-fetch can result in incorrect data
-+ *Workaround: Keep the read data size to 64 bits (8 Bytes), which
-+ *disables the prefetch on the AHB buffer,and prevents this issue
-+ *from occurring.
-+ */
-+ rx_size = 0x1;
-+#endif
- qspi_write32(priv->flags, ®s->buf3cr, QSPI_BUF3CR_ALLMST_MASK |
-- (0x80 << QSPI_BUF3CR_ADATSZ_SHIFT));
-+ (rx_size << QSPI_BUF3CR_ADATSZ_SHIFT));
-
- /* We only use the buffer3 */
- qspi_write32(priv->flags, ®s->buf0ind, 0);
-diff --git a/include/configs/ls1012a_common.h b/include/configs/ls1012a_common.h
-index 47b8ec3..f0ae355 100644
---- a/include/configs/ls1012a_common.h
-+++ b/include/configs/ls1012a_common.h
-@@ -68,6 +68,7 @@
- #define FSL_QSPI_FLASH_SIZE (1 << 26)
- #define FSL_QSPI_FLASH_NUM 2
- #define CONFIG_SYS_FSL_QSPI_AHB
-+#define CONFIG_SYS_FSL_ERRATUM_A009282
-
- /*
- * Environment
---
-1.7.9.5
-
diff --git a/package/boot/uboot-layerscape/patches/0072-driver-spi-fsl-qspi-remove-compile-Warnings.patch b/package/boot/uboot-layerscape/patches/0072-driver-spi-fsl-qspi-remove-compile-Warnings.patch
deleted file mode 100644
index beffb2a..0000000
--- a/package/boot/uboot-layerscape/patches/0072-driver-spi-fsl-qspi-remove-compile-Warnings.patch
+++ /dev/null
@@ -1,44 +0,0 @@
-From 31d5393ea4defd3872dc07264912f60ad627782b Mon Sep 17 00:00:00 2001
-From: Yunhui Cui <yunhui.cui at nxp.com>
-Date: Tue, 12 Jul 2016 11:29:52 +0800
-Subject: [PATCH 72/93] driver: spi: fsl-qspi: remove compile Warnings
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-Warnins log:
-drivers/spi/fsl_qspi.c: In function ‘qspi_ahb_read’:
-drivers/spi/fsl_qspi.c:400:16: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast]
- memcpy(rxbuf, (u8 *)(priv->cur_amba_base + priv->sf_addr), len);
-
-Signed-off-by: Yunhui Cui <yunhui.cui at nxp.com>
----
- drivers/spi/fsl_qspi.c | 4 +++-
- 1 file changed, 3 insertions(+), 1 deletion(-)
-
-diff --git a/drivers/spi/fsl_qspi.c b/drivers/spi/fsl_qspi.c
-index f1c87f5..f521fe2 100644
---- a/drivers/spi/fsl_qspi.c
-+++ b/drivers/spi/fsl_qspi.c
-@@ -389,6 +389,7 @@ static inline void qspi_ahb_read(struct fsl_qspi_priv *priv, u8 *rxbuf, int len)
- {
- struct fsl_qspi_regs *regs = priv->regs;
- u32 mcr_reg;
-+ void *rx_addr = NULL;
-
- mcr_reg = qspi_read32(priv->flags, ®s->mcr);
-
-@@ -396,8 +397,9 @@ static inline void qspi_ahb_read(struct fsl_qspi_priv *priv, u8 *rxbuf, int len)
- QSPI_MCR_CLR_RXF_MASK | QSPI_MCR_CLR_TXF_MASK |
- QSPI_MCR_RESERVED_MASK | QSPI_MCR_END_CFD_LE);
-
-+ rx_addr += priv->cur_amba_base + priv->sf_addr;
- /* Read out the data directly from the AHB buffer. */
-- memcpy(rxbuf, (u8 *)(priv->cur_amba_base + priv->sf_addr), len);
-+ memcpy(rxbuf, rx_addr, len);
-
- qspi_write32(priv->flags, ®s->mcr, mcr_reg);
- }
---
-1.7.9.5
-
diff --git a/package/boot/uboot-layerscape/patches/0073-armv8-pfe-Change-MDIO-HOLDTIME-value-to-5.patch b/package/boot/uboot-layerscape/patches/0073-armv8-pfe-Change-MDIO-HOLDTIME-value-to-5.patch
deleted file mode 100644
index a99b846..0000000
--- a/package/boot/uboot-layerscape/patches/0073-armv8-pfe-Change-MDIO-HOLDTIME-value-to-5.patch
+++ /dev/null
@@ -1,28 +0,0 @@
-From 3c41e8827ddcff313a518de19d630a42bbdca3b1 Mon Sep 17 00:00:00 2001
-From: Anji J <anji.jagarlmudi at freescale.com>
-Date: Fri, 8 Jul 2016 20:05:37 +0530
-Subject: [PATCH 73/93] armv8:pfe Change MDIO HOLDTIME value to 5
-
-Per design/validation team suggestion use HOLDTIME value as 5.
-
-Signed-off-by: Anji J <anji.jagarlmudi at freescale.com>
----
- drivers/net/pfe_eth/pfe_eth.c | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
-diff --git a/drivers/net/pfe_eth/pfe_eth.c b/drivers/net/pfe_eth/pfe_eth.c
-index 528ede9..9a90b38 100644
---- a/drivers/net/pfe_eth/pfe_eth.c
-+++ b/drivers/net/pfe_eth/pfe_eth.c
-@@ -329,7 +329,7 @@ struct mii_dev *ls1012a_mdio_init(struct mdio_info *mdio_info)
-
- /*configure mdio speed */
- mdio_speed = (DIV_ROUND_UP(pclk, 4000000) << EMAC_MII_SPEED_SHIFT);
-- mdio_speed |= EMAC_HOLDTIME(0x4);
-+ mdio_speed |= EMAC_HOLDTIME(0x5);
- writel(mdio_speed, mdio_info->reg_base + EMAC_MII_CTRL_REG);
-
- ret = mdio_register(bus);
---
-1.7.9.5
-
diff --git a/package/boot/uboot-layerscape/patches/0074-board-freescale-ls1012a-Intergrate-and-enable-PPA-on.patch b/package/boot/uboot-layerscape/patches/0074-board-freescale-ls1012a-Intergrate-and-enable-PPA-on.patch
deleted file mode 100644
index 8c633cc..0000000
--- a/package/boot/uboot-layerscape/patches/0074-board-freescale-ls1012a-Intergrate-and-enable-PPA-on.patch
+++ /dev/null
@@ -1,65 +0,0 @@
-From f95f8ebd8d55ccc27e1615b251450915a1c14315 Mon Sep 17 00:00:00 2001
-From: Abhimanyu Saini <abhimanyu.saini at nxp.com>
-Date: Tue, 12 Jul 2016 14:17:17 +0530
-Subject: [PATCH 74/93] board: freescale: ls1012a: Intergrate and enable PPA
- on LS1012AFRDM
-
-Signed-off-by: Abhimanyu Saini <abhimanyu.saini at nxp.com>
----
- board/freescale/ls1012afrdm/ls1012afrdm.c | 9 +++++++++
- include/configs/ls1012afrdm.h | 12 ++++++++++++
- 2 files changed, 21 insertions(+)
-
-diff --git a/board/freescale/ls1012afrdm/ls1012afrdm.c b/board/freescale/ls1012afrdm/ls1012afrdm.c
-index 4b7902a..04f8f9a 100644
---- a/board/freescale/ls1012afrdm/ls1012afrdm.c
-+++ b/board/freescale/ls1012afrdm/ls1012afrdm.c
-@@ -143,6 +143,9 @@ int board_early_init_f(void)
- int board_init(void)
- {
- struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
-+#ifdef CONFIG_FSL_LS_PPA
-+ u64 ppa_entry;
-+#endif
- /*
- * Set CCI-400 control override register to enable barrier
- * transaction
-@@ -157,6 +160,12 @@ int board_init(void)
- enable_layerscape_ns_access();
- #endif
-
-+#ifdef CONFIG_FSL_LS_PPA
-+ ppa_init_pre(&ppa_entry);
-+
-+ if (ppa_entry)
-+ ppa_init_entry((void *)ppa_entry);
-+#endif
- return 0;
- }
-
-diff --git a/include/configs/ls1012afrdm.h b/include/configs/ls1012afrdm.h
-index 622c774..26e3640 100644
---- a/include/configs/ls1012afrdm.h
-+++ b/include/configs/ls1012afrdm.h
-@@ -9,6 +9,18 @@
-
- #include "ls1012a_common.h"
-
-+#ifndef CONFIG_SECURE_BOOT
-+#define CONFIG_FSL_LS_PPA
-+#if defined(CONFIG_FSL_LS_PPA)
-+#define CONFIG_SYS_LS_PPA_DRAM_BLOCK_MIN_SIZE (1UL * 1024 * 1024)
-+
-+#define CONFIG_SYS_LS_PPA_FW_IN_XIP
-+#ifdef CONFIG_SYS_LS_PPA_FW_IN_XIP
-+#define CONFIG_SYS_LS_PPA_FW_ADDR 0x40500000
-+#endif
-+#endif
-+#endif
-+
- #define CONFIG_DIMM_SLOTS_PER_CTLR 1
- #define CONFIG_CHIP_SELECTS_PER_CTRL 1
- #define CONFIG_NR_DRAM_BANKS 2
---
-1.7.9.5
-
diff --git a/package/boot/uboot-layerscape/patches/0075-arm-ls1012ardb-add-CONFIG_ARMV8_PSCI.patch b/package/boot/uboot-layerscape/patches/0075-arm-ls1012ardb-add-CONFIG_ARMV8_PSCI.patch
deleted file mode 100644
index 0fec498..0000000
--- a/package/boot/uboot-layerscape/patches/0075-arm-ls1012ardb-add-CONFIG_ARMV8_PSCI.patch
+++ /dev/null
@@ -1,28 +0,0 @@
-From d2effd68c77b4965d74ac2a6154d668e24a6dd9f Mon Sep 17 00:00:00 2001
-From: Chenhui Zhao <chenhui.zhao at nxp.com>
-Date: Fri, 8 Jul 2016 16:01:31 +0800
-Subject: [PATCH 75/93] arm: ls1012ardb: add CONFIG_ARMV8_PSCI
-
-[context adjustment]
-
-Signed-off-by: Chenhui Zhao <chenhui.zhao at nxp.com>
-Integrated-by: Jiang Yutang <yutang.jiang at nxp.com>
----
- include/configs/ls1012ardb.h | 1 +
- 1 file changed, 1 insertion(+)
-
-diff --git a/include/configs/ls1012ardb.h b/include/configs/ls1012ardb.h
-index fdaea3e..e97c1f9 100644
---- a/include/configs/ls1012ardb.h
-+++ b/include/configs/ls1012ardb.h
-@@ -11,6 +11,7 @@
-
- #define CONFIG_FSL_LS_PPA
- #if defined(CONFIG_FSL_LS_PPA)
-+#define CONFIG_ARMV8_PSCI
- #define CONFIG_SYS_LS_PPA_DRAM_BLOCK_MIN_SIZE (1UL * 1024 * 1024)
-
- #define CONFIG_SYS_LS_PPA_FW_IN_XIP
---
-1.7.9.5
-
diff --git a/package/boot/uboot-layerscape/patches/0076-arm-ls1012afrdm-add-CONFIG_ARMV8_PSCI.patch b/package/boot/uboot-layerscape/patches/0076-arm-ls1012afrdm-add-CONFIG_ARMV8_PSCI.patch
deleted file mode 100644
index b08ae86..0000000
--- a/package/boot/uboot-layerscape/patches/0076-arm-ls1012afrdm-add-CONFIG_ARMV8_PSCI.patch
+++ /dev/null
@@ -1,25 +0,0 @@
-From ed6728fa22b4f09f6083d4c8b135f4b89487fee6 Mon Sep 17 00:00:00 2001
-From: Chenhui Zhao <chenhui.zhao at nxp.com>
-Date: Wed, 13 Jul 2016 13:05:19 +0800
-Subject: [PATCH 76/93] arm: ls1012afrdm: add CONFIG_ARMV8_PSCI
-
-Signed-off-by: Chenhui Zhao <chenhui.zhao at nxp.com>
----
- include/configs/ls1012afrdm.h | 1 +
- 1 file changed, 1 insertion(+)
-
-diff --git a/include/configs/ls1012afrdm.h b/include/configs/ls1012afrdm.h
-index 26e3640..0e35fe9 100644
---- a/include/configs/ls1012afrdm.h
-+++ b/include/configs/ls1012afrdm.h
-@@ -12,6 +12,7 @@
- #ifndef CONFIG_SECURE_BOOT
- #define CONFIG_FSL_LS_PPA
- #if defined(CONFIG_FSL_LS_PPA)
-+#define CONFIG_ARMV8_PSCI
- #define CONFIG_SYS_LS_PPA_DRAM_BLOCK_MIN_SIZE (1UL * 1024 * 1024)
-
- #define CONFIG_SYS_LS_PPA_FW_IN_XIP
---
-1.7.9.5
-
diff --git a/package/boot/uboot-layerscape/patches/0077-board-ls1012aqds-Avoid-reset-masking.patch b/package/boot/uboot-layerscape/patches/0077-board-ls1012aqds-Avoid-reset-masking.patch
deleted file mode 100644
index 7f6a65b..0000000
--- a/package/boot/uboot-layerscape/patches/0077-board-ls1012aqds-Avoid-reset-masking.patch
+++ /dev/null
@@ -1,39 +0,0 @@
-From 2203e9045d8d113e1ecceddcbebcf78c66af557f Mon Sep 17 00:00:00 2001
-From: Prabhakar Kushwaha <prabhakar.kushwaha at nxp.com>
-Date: Wed, 13 Jul 2016 15:49:12 +0530
-Subject: [PATCH 77/93] board: ls1012aqds: Avoid reset masking
-
-FPGA regiser RST_MASK1 control reset masking for I2C, USB,
-Mem and EPHY1.
-
-This register was being masked during initial debugging of
-RGMII. It is not required
-
-So avoid masking of these device to send reset signals during
-soft-reset.
-
-Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha at nxp.com>
----
- board/freescale/ls1012aqds/eth.c | 6 ------
- 1 file changed, 6 deletions(-)
-
-diff --git a/board/freescale/ls1012aqds/eth.c b/board/freescale/ls1012aqds/eth.c
-index 6fbbdbe..04d621c 100644
---- a/board/freescale/ls1012aqds/eth.c
-+++ b/board/freescale/ls1012aqds/eth.c
-@@ -156,12 +156,6 @@ int board_eth_init(bd_t *bis)
- data8 |= 0x2;
- QIXIS_WRITE(rst_frc[0], data8);
- data8 = QIXIS_READ(rst_frc[0]);
--
-- data8 = QIXIS_READ(res8[6]);
-- data8 |= 0xff;
-- QIXIS_WRITE(res8[6], data8);
-- data8 = QIXIS_READ(res8[6]);
--
- #endif
-
- mac1_mdio_info.reg_base = (void *)0x04200000; /*EMAC1_BASE_ADDR*/
---
-1.7.9.5
-
diff --git a/package/boot/uboot-layerscape/patches/0078-board-ls1012aqds-Update-LBMAP_MASK-and-RST_CTL_RESET.patch b/package/boot/uboot-layerscape/patches/0078-board-ls1012aqds-Update-LBMAP_MASK-and-RST_CTL_RESET.patch
deleted file mode 100644
index b7fb4e7..0000000
--- a/package/boot/uboot-layerscape/patches/0078-board-ls1012aqds-Update-LBMAP_MASK-and-RST_CTL_RESET.patch
+++ /dev/null
@@ -1,37 +0,0 @@
-From 50450fdcc39c3863351d52c290e77b664df33ed6 Mon Sep 17 00:00:00 2001
-From: Prabhakar Kushwaha <prabhakar.kushwaha at nxp.com>
-Date: Wed, 13 Jul 2016 15:49:22 +0530
-Subject: [PATCH 78/93] board: ls1012aqds: Update LBMAP_MASK and RST_CTL_RESET
-
-~QIXIS_LBMAP_MASK is being used in code. So define inverse value
-LBMAP_MASK.
-
-Aslo, update QIXIS_RST_CTL_RESET value to keep RST_CTL[REQ_MOD]
-as 0b11 i.e. PORESET.
-
-Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha at nxp.com>
----
- include/configs/ls1012aqds.h | 4 ++--
- 1 file changed, 2 insertions(+), 2 deletions(-)
-
-diff --git a/include/configs/ls1012aqds.h b/include/configs/ls1012aqds.h
-index c06cfbd..418bd54 100644
---- a/include/configs/ls1012aqds.h
-+++ b/include/configs/ls1012aqds.h
-@@ -89,11 +89,11 @@
- #define CONFIG_SYS_I2C_FPGA_ADDR 0x66
- #define QIXIS_LBMAP_BRDCFG_REG 0x04
- #define QIXIS_LBMAP_SWITCH 6
--#define QIXIS_LBMAP_MASK 0xf7
-+#define QIXIS_LBMAP_MASK 0x08
- #define QIXIS_LBMAP_SHIFT 0
- #define QIXIS_LBMAP_DFLTBANK 0x00
- #define QIXIS_LBMAP_ALTBANK 0x08
--#define QIXIS_RST_CTL_RESET 0x41
-+#define QIXIS_RST_CTL_RESET 0x31
- #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
- #define QIXIS_RCFG_CTL_RECONFIG_START 0x21
- #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
---
-1.7.9.5
-
diff --git a/package/boot/uboot-layerscape/patches/0079-armv8-pfe-Update-class-firmware.patch b/package/boot/uboot-layerscape/patches/0079-armv8-pfe-Update-class-firmware.patch
deleted file mode 100644
index 487a152..0000000
--- a/package/boot/uboot-layerscape/patches/0079-armv8-pfe-Update-class-firmware.patch
+++ /dev/null
@@ -1,38 +0,0 @@
-From 908e56f27baaad552e82f4e670108be9b4db67b6 Mon Sep 17 00:00:00 2001
-From: Anji J <anji.jagarlmudi at freescale.com>
-Date: Thu, 7 Jul 2016 12:53:15 +0530
-Subject: [PATCH 79/93] armv8:pfe Update class firmware
-
-This class firmware does the UDP/TCP checksum validation.
-Remove CONFIG_UDP_CHECKSUM
-
-Signed-off-by: Anji J <anji.jagarlmudi at freescale.com>
----
- drivers/net/pfe_eth/class_sbl_elf.fw | 2 +-
- include/configs/ls1012a_common.h | 1 -
- 2 files changed, 1 insertion(+), 2 deletions(-)
-
-diff --git a/drivers/net/pfe_eth/class_sbl_elf.fw b/drivers/net/pfe_eth/class_sbl_elf.fw
-index 3745d9a..10418ed 100644
---- a/drivers/net/pfe_eth/class_sbl_elf.fw
-+++ b/drivers/net/pfe_eth/class_sbl_elf.fw
-@@ -1 +1 @@
--0x7f,0x45,0x4c,0x46,0x01,0x02,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x02,0x00,0x6f,0x00,0x00,0x00,0x01,0x00,0x01,0x02,0x4c,0x00,0x00,0x00,0x34,0x00,0x00,0x13,0x14,0x00,0x04,0x00,0x05,0x00,0x34,0x00,0x20,0x00,0x04,0x00,0x28,0x00,0x0d,0x00,0x0c,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x08,0x90,0x00,0x00,0x08,0x98,0x00,0x00,0x00,0x06,0x00,0x00,0x10,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x08,0x98,0x00,0x00,0x08,0x98,0x00,0x00,0 [...]
-\ No newline at end of file
-+0x7f,0x45,0x4c,0x46,0x01,0x02,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x02,0x00,0x6f,0x00,0x00,0x00,0x01,0x00,0x01,0x02,0x68,0x00,0x00,0x00,0x34,0x00,0x00,0x13,0x30,0x00,0x04,0x00,0x05,0x00,0x34,0x00,0x20,0x00,0x04,0x00,0x28,0x00,0x0d,0x00,0x0c,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x08,0x90,0x00,0x00,0x08,0x98,0x00,0x00,0x00,0x06,0x00,0x00,0x10,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x08,0x98,0x00,0x00,0x08,0x98,0x00,0x00,0 [...]
-\ No newline at end of file
-diff --git a/include/configs/ls1012a_common.h b/include/configs/ls1012a_common.h
-index f0ae355..0d64889 100644
---- a/include/configs/ls1012a_common.h
-+++ b/include/configs/ls1012a_common.h
-@@ -117,7 +117,6 @@
- #ifdef CONFIG_FSL_PPFE
- #define CONFIG_CMD_PFE_COMMANDS
- #define CONFIG_UTIL_PE_DISABLED
--#define CONFIG_UDP_CHECKSUM
-
- #endif
-
---
-1.7.9.5
-
diff --git a/package/boot/uboot-layerscape/patches/0080-ls1012ardb-PPA-Enable-PPA-validation-in-case-of-secu.patch b/package/boot/uboot-layerscape/patches/0080-ls1012ardb-PPA-Enable-PPA-validation-in-case-of-secu.patch
deleted file mode 100644
index 9c072f0..0000000
--- a/package/boot/uboot-layerscape/patches/0080-ls1012ardb-PPA-Enable-PPA-validation-in-case-of-secu.patch
+++ /dev/null
@@ -1,54 +0,0 @@
-From b43d6d42d734e78bd9b805a62f2a64933c144a41 Mon Sep 17 00:00:00 2001
-From: Sumit Garg <sumit.garg at nxp.com>
-Date: Thu, 14 Jul 2016 07:20:02 -0400
-Subject: [PATCH 80/93] ls1012ardb: PPA: Enable PPA validation in case of
- secure boot
-
-As part of Secure Boot Chain of trust, enable validation of PPA image
-before the image is started.
-
-Signed-off-by: Sumit Garg <sumit.garg at nxp.com>
----
- arch/arm/include/asm/fsl_secure_boot.h | 2 ++
- include/configs/ls1012a_common.h | 2 --
- include/configs/ls1012ardb.h | 2 ++
- 3 files changed, 4 insertions(+), 2 deletions(-)
-
-diff --git a/arch/arm/include/asm/fsl_secure_boot.h b/arch/arm/include/asm/fsl_secure_boot.h
-index b2e9105..0580fcd 100644
---- a/arch/arm/include/asm/fsl_secure_boot.h
-+++ b/arch/arm/include/asm/fsl_secure_boot.h
-@@ -107,6 +107,8 @@
- #ifdef CONFIG_SYS_LS_PPA_FW_IN_XIP
- #ifdef CONFIG_LS1043A
- #define CONFIG_SYS_LS_PPA_ESBC_ADDR 0x600c0000
-+#else
-+#define CONFIG_SYS_LS_PPA_ESBC_ADDR 0x40480000
- #endif
- #else
- #error "No CONFIG_SYS_LS_PPA_FW_IN_xxx defined"
-diff --git a/include/configs/ls1012a_common.h b/include/configs/ls1012a_common.h
-index 0d64889..7e935ad 100644
---- a/include/configs/ls1012a_common.h
-+++ b/include/configs/ls1012a_common.h
-@@ -191,6 +191,4 @@
- #define CONFIG_DOS_PARTITION
- #define CONFIG_CMD_EXT2
-
--#include <asm/fsl_secure_boot.h>
--
- #endif /* __LS1012A_COMMON_H */
-diff --git a/include/configs/ls1012ardb.h b/include/configs/ls1012ardb.h
-index e97c1f9..d78edd2 100644
---- a/include/configs/ls1012ardb.h
-+++ b/include/configs/ls1012ardb.h
-@@ -149,4 +149,6 @@
-
- #define CONFIG_FSL_CAAM /* Enable CAAM */
-
-+#include <asm/fsl_secure_boot.h>
-+
- #endif /* __LS1012ARDB_H__ */
---
-1.7.9.5
-
diff --git a/package/boot/uboot-layerscape/patches/0081-crypto-fsl-Update-blob-cmd-to-accept-64bit-addresses.patch b/package/boot/uboot-layerscape/patches/0081-crypto-fsl-Update-blob-cmd-to-accept-64bit-addresses.patch
deleted file mode 100644
index 9a34203..0000000
--- a/package/boot/uboot-layerscape/patches/0081-crypto-fsl-Update-blob-cmd-to-accept-64bit-addresses.patch
+++ /dev/null
@@ -1,79 +0,0 @@
-From 5d4a46fe8847d26112764c5768ff00f839fb3810 Mon Sep 17 00:00:00 2001
-From: Sumit Garg <sumit.garg at nxp.com>
-Date: Tue, 12 Jul 2016 14:05:34 -0400
-Subject: [PATCH 81/93] crypto/fsl: Update blob cmd to accept 64bit addresses
-
-Update blob cmd to accept 64bit source, key modifier and destination
-addresses. Also correct output result print format for fsl specific
-implementation of blob cmd.
-
-Signed-off-by: Sumit Garg <sumit.garg at nxp.com>
----
- common/cmd_blob.c | 2 +-
- drivers/crypto/fsl/fsl_blob.c | 13 ++++++++++---
- 2 files changed, 11 insertions(+), 4 deletions(-)
-
-diff --git a/common/cmd_blob.c b/common/cmd_blob.c
-index ac8b268..bdd4cfd 100644
---- a/common/cmd_blob.c
-+++ b/common/cmd_blob.c
-@@ -54,7 +54,7 @@ __weak int blob_encap(u8 *key_mod, u8 *src, u8 *dst, u32 len)
- */
- static int do_blob(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
- {
-- uint32_t key_addr, src_addr, dst_addr, len;
-+ ulong key_addr, src_addr, dst_addr, len;
- uint8_t *km_ptr, *src_ptr, *dst_ptr;
- int enc, ret = 0;
-
-diff --git a/drivers/crypto/fsl/fsl_blob.c b/drivers/crypto/fsl/fsl_blob.c
-index 8b25921..d24b8fc 100644
---- a/drivers/crypto/fsl/fsl_blob.c
-+++ b/drivers/crypto/fsl/fsl_blob.c
-@@ -18,7 +18,7 @@ int blob_decap(u8 *key_mod, u8 *src, u8 *dst, u32 len)
- int ret, i = 0;
- u32 *desc;
-
-- printf("\nDecapsulating data to form blob\n");
-+ printf("\nDecapsulating blob to get data\n");
- desc = malloc(sizeof(int) * MAX_CAAM_DESCSIZE);
- if (!desc) {
- debug("Not enough memory for descriptor allocation\n");
-@@ -27,12 +27,15 @@ int blob_decap(u8 *key_mod, u8 *src, u8 *dst, u32 len)
-
- inline_cnstr_jobdesc_blob_decap(desc, key_mod, src, dst, len);
-
-+ debug("Descriptor dump:\n");
- for (i = 0; i < 14; i++)
-- printf("%x\n", *(desc + i));
-+ debug("Word[%d]: %08x\n", i, *(desc + i));
- ret = run_descriptor_jr(desc);
-
- if (ret)
- printf("Error in Decapsulation %d\n", ret);
-+ else
-+ printf("Decapsulation Success\n");
-
- free(desc);
- return ret;
-@@ -51,12 +54,16 @@ int blob_encap(u8 *key_mod, u8 *src, u8 *dst, u32 len)
- }
-
- inline_cnstr_jobdesc_blob_encap(desc, key_mod, src, dst, len);
-+
-+ debug("Descriptor dump:\n");
- for (i = 0; i < 14; i++)
-- printf("%x\n", *(desc + i));
-+ debug("Word[%d]: %08x\n", i, *(desc + i));
- ret = run_descriptor_jr(desc);
-
- if (ret)
- printf("Error in Encapsulation %d\n", ret);
-+ else
-+ printf("Encapsulation Success\n");
-
- free(desc);
- return ret;
---
-1.7.9.5
-
diff --git a/package/boot/uboot-layerscape/patches/0082-armv8-ls1012a-Update-DDR-timing.patch b/package/boot/uboot-layerscape/patches/0082-armv8-ls1012a-Update-DDR-timing.patch
deleted file mode 100644
index 8edc4a5..0000000
--- a/package/boot/uboot-layerscape/patches/0082-armv8-ls1012a-Update-DDR-timing.patch
+++ /dev/null
@@ -1,56 +0,0 @@
-From 9e157635c191762624c066d14e360e972aa1ad0f Mon Sep 17 00:00:00 2001
-From: Shengzhou Liu <Shengzhou.Liu at nxp.com>
-Date: Wed, 20 Jul 2016 15:44:58 +0800
-Subject: [PATCH 82/93] armv8: ls1012a: Update DDR timing
-
-Update MMDC timing CL-tRCD-tRP to 7-7-7.
-
-Signed-off-by: Shengzhou Liu <Shengzhou.Liu at nxp.com>
----
- board/freescale/ls1012afrdm/ls1012afrdm.c | 2 +-
- board/freescale/ls1012aqds/ls1012aqds.c | 2 +-
- board/freescale/ls1012ardb/ls1012ardb.c | 2 +-
- 3 files changed, 3 insertions(+), 3 deletions(-)
-
-diff --git a/board/freescale/ls1012afrdm/ls1012afrdm.c b/board/freescale/ls1012afrdm/ls1012afrdm.c
-index 04f8f9a..a152a18 100644
---- a/board/freescale/ls1012afrdm/ls1012afrdm.c
-+++ b/board/freescale/ls1012afrdm/ls1012afrdm.c
-@@ -55,7 +55,7 @@ void mmdc_init(void)
- /* configure timing parms */
- out_be32(&mmdc->mdotc, 0x12554000);
- out_be32(&mmdc->mdcfg0, 0xbabf7954);
-- out_be32(&mmdc->mdcfg1, 0xff328f64);
-+ out_be32(&mmdc->mdcfg1, 0xdb328f64);
- out_be32(&mmdc->mdcfg2, 0x01ff00db);
-
- /* other parms */
-diff --git a/board/freescale/ls1012aqds/ls1012aqds.c b/board/freescale/ls1012aqds/ls1012aqds.c
-index 4ae8def..7bdb591 100644
---- a/board/freescale/ls1012aqds/ls1012aqds.c
-+++ b/board/freescale/ls1012aqds/ls1012aqds.c
-@@ -78,7 +78,7 @@ void mmdc_init(void)
- /* configure timing parms */
- out_be32(&mmdc->mdotc, 0x12554000);
- out_be32(&mmdc->mdcfg0, 0xbabf7954);
-- out_be32(&mmdc->mdcfg1, 0xff328f64);
-+ out_be32(&mmdc->mdcfg1, 0xdb328f64);
- out_be32(&mmdc->mdcfg2, 0x01ff00db);
-
- /* other parms */
-diff --git a/board/freescale/ls1012ardb/ls1012ardb.c b/board/freescale/ls1012ardb/ls1012ardb.c
-index 06e1f6b..ac51d56 100644
---- a/board/freescale/ls1012ardb/ls1012ardb.c
-+++ b/board/freescale/ls1012ardb/ls1012ardb.c
-@@ -84,7 +84,7 @@ void mmdc_init(void)
- /* configure timing parms */
- out_be32(&mmdc->mdotc, 0x12554000);
- out_be32(&mmdc->mdcfg0, 0xbabf7954);
-- out_be32(&mmdc->mdcfg1, 0xff328f64);
-+ out_be32(&mmdc->mdcfg1, 0xdb328f64);
- out_be32(&mmdc->mdcfg2, 0x01ff00db);
-
- /* other parms */
---
-1.7.9.5
-
diff --git a/package/boot/uboot-layerscape/patches/0083-armv8-fsl-layerscape-Fix-the-conflict-between-PPA-an.patch b/package/boot/uboot-layerscape/patches/0083-armv8-fsl-layerscape-Fix-the-conflict-between-PPA-an.patch
deleted file mode 100644
index e085a87..0000000
--- a/package/boot/uboot-layerscape/patches/0083-armv8-fsl-layerscape-Fix-the-conflict-between-PPA-an.patch
+++ /dev/null
@@ -1,120 +0,0 @@
-From db48271175c0566bb5e59776a23297d64aec9fcd Mon Sep 17 00:00:00 2001
-From: Alison Wang <b18965 at freescale.com>
-Date: Thu, 21 Jul 2016 18:13:29 +0800
-Subject: [PATCH 83/93] armv8: fsl-layerscape: Fix the conflict between PPA
- and AArch32 support
-
-As there is conflict between PPA and AArch32 support, this patch is to
-add a new defconfig for AArch32 support and move the definition for PPA
-to the board defconfig.
-
-Signed-off-by: Alison Wang <alison.wang at nxp.com>
----
- configs/ls1012afrdm_aarch32_qspi_defconfig | 11 +++++++++++
- configs/ls1012afrdm_qspi_defconfig | 1 +
- configs/ls1012ardb_aarch32_qspi_defconfig | 11 +++++++++++
- configs/ls1012ardb_qspi_SECURE_BOOT_defconfig | 1 +
- configs/ls1012ardb_qspi_defconfig | 1 +
- include/configs/ls1012afrdm.h | 1 -
- include/configs/ls1012ardb.h | 1 -
- 7 files changed, 25 insertions(+), 2 deletions(-)
- create mode 100644 configs/ls1012afrdm_aarch32_qspi_defconfig
- create mode 100644 configs/ls1012ardb_aarch32_qspi_defconfig
-
-diff --git a/configs/ls1012afrdm_aarch32_qspi_defconfig b/configs/ls1012afrdm_aarch32_qspi_defconfig
-new file mode 100644
-index 0000000..1bb9080
---- /dev/null
-+++ b/configs/ls1012afrdm_aarch32_qspi_defconfig
-@@ -0,0 +1,11 @@
-+CONFIG_ARM=y
-+CONFIG_TARGET_LS1012AFRDM=y
-+CONFIG_SYS_EXTRA_OPTIONS="QSPI_BOOT"
-+# CONFIG_CMD_IMLS is not set
-+# CONFIG_FSL_LS_PPA is not set
-+CONFIG_SYS_NS16550=y
-+CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1012a-frdm"
-+CONFIG_OF_CONTROL=y
-+CONFIG_DM=y
-+CONFIG_SPI_FLASH=y
-+CONFIG_DM_SPI=y
-diff --git a/configs/ls1012afrdm_qspi_defconfig b/configs/ls1012afrdm_qspi_defconfig
-index e27181c..1f69db7 100644
---- a/configs/ls1012afrdm_qspi_defconfig
-+++ b/configs/ls1012afrdm_qspi_defconfig
-@@ -2,6 +2,7 @@ CONFIG_ARM=y
- CONFIG_TARGET_LS1012AFRDM=y
- CONFIG_SYS_EXTRA_OPTIONS="QSPI_BOOT"
- # CONFIG_CMD_IMLS is not set
-+CONFIG_FSL_LS_PPA=y
- CONFIG_SYS_NS16550=y
- CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1012a-frdm"
- CONFIG_OF_CONTROL=y
-diff --git a/configs/ls1012ardb_aarch32_qspi_defconfig b/configs/ls1012ardb_aarch32_qspi_defconfig
-new file mode 100644
-index 0000000..df16f3b
---- /dev/null
-+++ b/configs/ls1012ardb_aarch32_qspi_defconfig
-@@ -0,0 +1,11 @@
-+CONFIG_ARM=y
-+CONFIG_TARGET_LS1012ARDB=y
-+CONFIG_SYS_EXTRA_OPTIONS="QSPI_BOOT"
-+# CONFIG_CMD_IMLS is not set
-+# CONFIG_FSL_LS_PPA is not set
-+CONFIG_SYS_NS16550=y
-+CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1012a-rdb"
-+CONFIG_OF_CONTROL=y
-+CONFIG_DM=y
-+CONFIG_SPI_FLASH=y
-+CONFIG_DM_SPI=y
-diff --git a/configs/ls1012ardb_qspi_SECURE_BOOT_defconfig b/configs/ls1012ardb_qspi_SECURE_BOOT_defconfig
-index 92a95a8..4091503 100644
---- a/configs/ls1012ardb_qspi_SECURE_BOOT_defconfig
-+++ b/configs/ls1012ardb_qspi_SECURE_BOOT_defconfig
-@@ -2,6 +2,7 @@ CONFIG_ARM=y
- CONFIG_TARGET_LS1012ARDB=y
- CONFIG_SYS_EXTRA_OPTIONS="QSPI_BOOT,SECURE_BOOT"
- # CONFIG_CMD_IMLS is not set
-+# CONFIG_FSL_LS_PPA is not set
- CONFIG_SYS_NS16550=y
- CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1012a-rdb"
- CONFIG_OF_CONTROL=y
-diff --git a/configs/ls1012ardb_qspi_defconfig b/configs/ls1012ardb_qspi_defconfig
-index f819038..e025247 100644
---- a/configs/ls1012ardb_qspi_defconfig
-+++ b/configs/ls1012ardb_qspi_defconfig
-@@ -2,6 +2,7 @@ CONFIG_ARM=y
- CONFIG_TARGET_LS1012ARDB=y
- CONFIG_SYS_EXTRA_OPTIONS="QSPI_BOOT"
- # CONFIG_CMD_IMLS is not set
-+CONFIG_FSL_LS_PPA=y
- CONFIG_SYS_NS16550=y
- CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1012a-rdb"
- CONFIG_OF_CONTROL=y
-diff --git a/include/configs/ls1012afrdm.h b/include/configs/ls1012afrdm.h
-index 0e35fe9..a736687 100644
---- a/include/configs/ls1012afrdm.h
-+++ b/include/configs/ls1012afrdm.h
-@@ -10,7 +10,6 @@
- #include "ls1012a_common.h"
-
- #ifndef CONFIG_SECURE_BOOT
--#define CONFIG_FSL_LS_PPA
- #if defined(CONFIG_FSL_LS_PPA)
- #define CONFIG_ARMV8_PSCI
- #define CONFIG_SYS_LS_PPA_DRAM_BLOCK_MIN_SIZE (1UL * 1024 * 1024)
-diff --git a/include/configs/ls1012ardb.h b/include/configs/ls1012ardb.h
-index d78edd2..400fa61 100644
---- a/include/configs/ls1012ardb.h
-+++ b/include/configs/ls1012ardb.h
-@@ -9,7 +9,6 @@
-
- #include "ls1012a_common.h"
-
--#define CONFIG_FSL_LS_PPA
- #if defined(CONFIG_FSL_LS_PPA)
- #define CONFIG_ARMV8_PSCI
- #define CONFIG_SYS_LS_PPA_DRAM_BLOCK_MIN_SIZE (1UL * 1024 * 1024)
---
-1.7.9.5
-
diff --git a/package/boot/uboot-layerscape/patches/0084-armv8-fsl-layerscape-Moving-FSL_LS_PPA-flag-to-EXTRA.patch b/package/boot/uboot-layerscape/patches/0084-armv8-fsl-layerscape-Moving-FSL_LS_PPA-flag-to-EXTRA.patch
deleted file mode 100644
index ae80732..0000000
--- a/package/boot/uboot-layerscape/patches/0084-armv8-fsl-layerscape-Moving-FSL_LS_PPA-flag-to-EXTRA.patch
+++ /dev/null
@@ -1,43 +0,0 @@
-From 257802b8b8640e58e4a2001031f18facf056908e Mon Sep 17 00:00:00 2001
-From: Abhimanyu Saini <abhimanyu.saini at nxp.com>
-Date: Mon, 25 Jul 2016 16:41:24 +0530
-Subject: [PATCH 84/93] armv8: fsl-layerscape: Moving FSL_LS_PPA flag to
- EXTRA_OPTIONS
-
-Signed-off-by: Abhimanyu Saini <abhimanyu.saini at nxp.com>
----
- configs/ls1012afrdm_qspi_defconfig | 3 +--
- configs/ls1012ardb_qspi_defconfig | 3 +--
- 2 files changed, 2 insertions(+), 4 deletions(-)
-
-diff --git a/configs/ls1012afrdm_qspi_defconfig b/configs/ls1012afrdm_qspi_defconfig
-index 1f69db7..0d1b0f3 100644
---- a/configs/ls1012afrdm_qspi_defconfig
-+++ b/configs/ls1012afrdm_qspi_defconfig
-@@ -1,8 +1,7 @@
- CONFIG_ARM=y
- CONFIG_TARGET_LS1012AFRDM=y
--CONFIG_SYS_EXTRA_OPTIONS="QSPI_BOOT"
-+CONFIG_SYS_EXTRA_OPTIONS="QSPI_BOOT, FSL_LS_PPA"
- # CONFIG_CMD_IMLS is not set
--CONFIG_FSL_LS_PPA=y
- CONFIG_SYS_NS16550=y
- CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1012a-frdm"
- CONFIG_OF_CONTROL=y
-diff --git a/configs/ls1012ardb_qspi_defconfig b/configs/ls1012ardb_qspi_defconfig
-index e025247..00e4dd2 100644
---- a/configs/ls1012ardb_qspi_defconfig
-+++ b/configs/ls1012ardb_qspi_defconfig
-@@ -1,8 +1,7 @@
- CONFIG_ARM=y
- CONFIG_TARGET_LS1012ARDB=y
--CONFIG_SYS_EXTRA_OPTIONS="QSPI_BOOT"
-+CONFIG_SYS_EXTRA_OPTIONS="QSPI_BOOT, FSL_LS_PPA"
- # CONFIG_CMD_IMLS is not set
--CONFIG_FSL_LS_PPA=y
- CONFIG_SYS_NS16550=y
- CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1012a-rdb"
- CONFIG_OF_CONTROL=y
---
-1.7.9.5
-
diff --git a/package/boot/uboot-layerscape/patches/0085-armv8-fsl-layerscape-Enable-FSL_LS_PPA-in-Secure-boo.patch b/package/boot/uboot-layerscape/patches/0085-armv8-fsl-layerscape-Enable-FSL_LS_PPA-in-Secure-boo.patch
deleted file mode 100644
index 5bc5935..0000000
--- a/package/boot/uboot-layerscape/patches/0085-armv8-fsl-layerscape-Enable-FSL_LS_PPA-in-Secure-boo.patch
+++ /dev/null
@@ -1,28 +0,0 @@
-From 0d3ccab8ba94f0cb1f5cb1c1391a79619c040f1c Mon Sep 17 00:00:00 2001
-From: Sumit Garg <sumit.garg at nxp.com>
-Date: Tue, 26 Jul 2016 07:43:41 -0400
-Subject: [PATCH 85/93] armv8: fsl-layerscape: Enable FSL_LS_PPA in Secure
- boot target
-
-Signed-off-by: Sumit Garg <sumit.garg at nxp.com>
----
- configs/ls1012ardb_qspi_SECURE_BOOT_defconfig | 3 +--
- 1 file changed, 1 insertion(+), 2 deletions(-)
-
-diff --git a/configs/ls1012ardb_qspi_SECURE_BOOT_defconfig b/configs/ls1012ardb_qspi_SECURE_BOOT_defconfig
-index 4091503..bb9099b 100644
---- a/configs/ls1012ardb_qspi_SECURE_BOOT_defconfig
-+++ b/configs/ls1012ardb_qspi_SECURE_BOOT_defconfig
-@@ -1,8 +1,7 @@
- CONFIG_ARM=y
- CONFIG_TARGET_LS1012ARDB=y
--CONFIG_SYS_EXTRA_OPTIONS="QSPI_BOOT,SECURE_BOOT"
-+CONFIG_SYS_EXTRA_OPTIONS="QSPI_BOOT, FSL_LS_PPA, SECURE_BOOT"
- # CONFIG_CMD_IMLS is not set
--# CONFIG_FSL_LS_PPA is not set
- CONFIG_SYS_NS16550=y
- CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1012a-rdb"
- CONFIG_OF_CONTROL=y
---
-1.7.9.5
-
diff --git a/package/boot/uboot-layerscape/patches/0086-driver-spi-add-spansion-s25fs-s-family-protect-unpro.patch b/package/boot/uboot-layerscape/patches/0086-driver-spi-add-spansion-s25fs-s-family-protect-unpro.patch
deleted file mode 100644
index 008b601..0000000
--- a/package/boot/uboot-layerscape/patches/0086-driver-spi-add-spansion-s25fs-s-family-protect-unpro.patch
+++ /dev/null
@@ -1,233 +0,0 @@
-From 986172ece10eee928ce66597d76f3f40ac3d25f7 Mon Sep 17 00:00:00 2001
-From: Yunhui Cui <yunhui.cui at nxp.com>
-Date: Mon, 8 Aug 2016 14:24:13 +0800
-Subject: [PATCH 86/93] driver: spi: add spansion s25fs-s family
- protect/unprotect
-
-In order to support spansion s25fs512s flash protect/unprotect:
-
-[1] Fill callbak flash->lock/unlock/is_locked by spansion_lock/
-unlock/is_locked.
-
-[2] Achieve protect/unprotected by operating sr1nv, cr1nv.
-
-Signed-off-by: Yunhui Cui <yunhui.cui at nxp.com>
----
- drivers/mtd/spi/spi_flash.c | 194 +++++++++++++++++++++++++++++++++++++++++++
- 1 file changed, 194 insertions(+)
-
-diff --git a/drivers/mtd/spi/spi_flash.c b/drivers/mtd/spi/spi_flash.c
-index e04bd55..87a92e9 100644
---- a/drivers/mtd/spi/spi_flash.c
-+++ b/drivers/mtd/spi/spi_flash.c
-@@ -877,6 +877,193 @@ int stm_unlock(struct spi_flash *flash, u32 ofs, size_t len)
- }
- #endif
-
-+#if defined(CONFIG_SPI_FLASH_SPANSION)
-+/*
-+ * Return 1 if the entire region is locked, 0 otherwise
-+ */
-+static int spansion_is_locked_sr(struct spi_flash *flash, u32 ofs, u32 len,
-+ u8 sr)
-+{
-+ loff_t lock_offs;
-+ u32 lock_len;
-+
-+ stm_get_locked_range(flash, sr, &lock_offs, &lock_len);
-+
-+ return (ofs + len <= lock_offs + lock_len) && (ofs >= lock_offs);
-+}
-+
-+/*
-+ * Check if a region of the flash is (completely) locked. See spansion_lock() for
-+ * more info.
-+ *
-+ * Returns 1 if entire region is locked, 0 if any portion is unlocked, and
-+ * negative on errors.
-+ */
-+int spansion_is_locked(struct spi_flash *flash, u32 ofs, size_t len)
-+{
-+ u8 cmd[4];
-+ u32 sr1nv_offset = 0x0;
-+ u8 sr1nv;
-+ int ret;
-+
-+ cmd[0] = CMD_SPANSION_RDAR;
-+ cmd[1] = sr1nv_offset >> 16;
-+ cmd[2] = sr1nv_offset >> 8;
-+ cmd[3] = sr1nv_offset >> 0;
-+
-+ ret = spi_flash_cmd_read(flash->spi, cmd, 4, &sr1nv, 1);
-+ if (ret)
-+ return -EIO;
-+
-+ return spansion_is_locked_sr(flash, ofs, len, sr1nv);
-+}
-+
-+/*
-+ * Lock a region of the flash. Compatible with Spansion s25fs-s family flash.
-+ * Supports only the block protection bits BP{0,1,2} in the Status Register-1
-+ * Non-Volatile(SR1NV).
-+ *
-+ * Sample table portion for 64MB flash (S25FS512S):
-+ * Configuration Register-1 Non-Volatile(CR1NV[5])== 0
-+ *
-+ * | BP2 | BP1 | BP0 | Prot Length | Protected Portion
-+ * ------------------------------------------------------------
-+ * | 0 | 0 | 0 | NONE | NONE
-+ * | 0 | 0 | 1 | 1 MB | Upper 1/64
-+ * | 0 | 1 | 0 | 2 MB | Upper 1/32
-+ * | 0 | 1 | 1 | 4 MB | Upper 1/16
-+ * | 1 | 0 | 0 | 8 MB | Upper 1/8
-+ * | 1 | 0 | 1 | 16 MB | Upper 1/4
-+ * | 1 | 1 | 0 | 32 MB | Upper 1/2
-+ * | 1 | 1 | 1 | 64 MB | ALL
-+ *
-+ * When CR1NV[5] == 1, the Lower memory array are protected.
-+ *
-+ * Returns negative on errors, 0 on success.
-+ */
-+int spansion_lock(struct spi_flash *flash, u32 ofs, size_t len)
-+{
-+ u8 status_old, status_new;
-+ u8 mask = SR_BP2 | SR_BP1 | SR_BP0;
-+ u8 shift = ffs(mask) - 1, pow, val;
-+ int ret;
-+ u8 cmd[4];
-+ u32 sr1nv_offset = 0x0;
-+ u8 sr1nv;
-+
-+ cmd[0] = CMD_SPANSION_RDAR;
-+ cmd[1] = sr1nv_offset >> 16;
-+ cmd[2] = sr1nv_offset >> 8;
-+ cmd[3] = sr1nv_offset >> 0;
-+
-+ ret = spi_flash_cmd_read(flash->spi, cmd, 4, &sr1nv, 1);
-+ if (ret)
-+ return -EIO;
-+ status_old = sr1nv;
-+
-+ /* SPI NOR always locks to the end */
-+ if (ofs + len != flash->size) {
-+ /* Does combined region extend to end? */
-+ if (!stm_is_locked_sr(flash, ofs + len, flash->size - ofs - len,
-+ status_old))
-+ return -EINVAL;
-+ len = flash->size - ofs;
-+ }
-+
-+ /*
-+ * Need smallest pow such that:
-+ *
-+ * 1 / (2^pow) <= (len / size)
-+ *
-+ * so (assuming power-of-2 size) we do:
-+ *
-+ * pow = ceil(log2(size / len)) = log2(size) - floor(log2(len))
-+ */
-+ pow = ilog2(flash->size) - ilog2(len);
-+ val = mask - (pow << shift);
-+ if (val & ~mask)
-+ return -EINVAL;
-+
-+ /* Don't "lock" with no region! */
-+ if (!(val & mask))
-+ return -EINVAL;
-+
-+ status_new = (status_old & ~mask) | val;
-+
-+ /* Only modify protection if it will not unlock other areas */
-+ if ((status_new & mask) <= (status_old & mask))
-+ return -EINVAL;
-+
-+ cmd[0] = CMD_SPANSION_WRAR;
-+ ret = spi_flash_cmd_write(flash->spi, cmd, 4, &status_new, 1);
-+ if (ret)
-+ return -EIO;
-+
-+ return 0;
-+}
-+
-+/*
-+ * Unlock a region of the flash. See spansion_lock() for more info
-+ *
-+ * Returns negative on errors, 0 on success.
-+ */
-+int spansion_unlock(struct spi_flash *flash, u32 ofs, size_t len)
-+{
-+ uint8_t status_old, status_new;
-+ u8 mask = SR_BP2 | SR_BP1 | SR_BP0;
-+ u8 shift = ffs(mask) - 1, pow, val;
-+ int ret;
-+
-+ u8 cmd[4];
-+ u32 sr1nv_offset = 0x0;
-+ u8 sr1nv;
-+
-+ cmd[0] = CMD_SPANSION_RDAR;
-+ cmd[1] = sr1nv_offset >> 16;
-+ cmd[2] = sr1nv_offset >> 8;
-+ cmd[3] = sr1nv_offset >> 0;
-+
-+ ret = spi_flash_cmd_read(flash->spi, cmd, 4, &sr1nv, 1);
-+ if (ret)
-+ return -EIO;
-+ status_old = sr1nv;
-+
-+ /* Cannot unlock; would unlock larger region than requested */
-+ if (spansion_is_locked_sr(flash, ofs - flash->erase_size, flash->erase_size,
-+ status_old))
-+ return -EINVAL;
-+ /*
-+ * Need largest pow such that:
-+ *
-+ * 1 / (2^pow) >= (len / size)
-+ *
-+ * so (assuming power-of-2 size) we do:
-+ *
-+ * pow = floor(log2(size / len)) = log2(size) - ceil(log2(len))
-+ */
-+ pow = ilog2(flash->size) - order_base_2(flash->size - (ofs + len));
-+ if (ofs + len == flash->size) {
-+ val = 0; /* fully unlocked */
-+ } else {
-+ val = mask - (pow << shift);
-+ /* Some power-of-two sizes are not supported */
-+ if (val & ~mask)
-+ return -EINVAL;
-+ }
-+ status_new = (status_old & ~mask) | val;
-+
-+ /* Only modify protection if it will not lock other areas */
-+ if ((status_new & mask) >= (status_old & mask))
-+ return -EINVAL;
-+
-+ cmd[0] = CMD_SPANSION_WRAR;
-+ ret = spi_flash_cmd_write(flash->spi, cmd, 4, &status_new, 1);
-+ if (ret)
-+ return -EIO;
-+
-+ return 0;
-+}
-+#endif
-
- #ifdef CONFIG_SPI_FLASH_MACRONIX
- static int spi_flash_set_qeb_mxic(struct spi_flash *flash)
-@@ -1132,6 +1319,13 @@ int spi_flash_scan(struct spi_flash *flash)
- flash->flash_is_locked = stm_is_locked;
- #endif
- break;
-+#if defined(CONFIG_SPI_FLASH_SPANSION)
-+ case SPI_FLASH_CFI_MFR_SPANSION:
-+ flash->flash_lock = spansion_lock;
-+ flash->flash_unlock = spansion_unlock;
-+ flash->flash_is_locked = spansion_is_locked;
-+#endif
-+ break;
- default:
- debug("SF: Lock ops not supported for %02x flash\n", idcode[0]);
- }
---
-1.7.9.5
-
diff --git a/package/boot/uboot-layerscape/patches/0087-armv8-ls1012a-Update-bootargs.patch b/package/boot/uboot-layerscape/patches/0087-armv8-ls1012a-Update-bootargs.patch
deleted file mode 100644
index e6c73a7..0000000
--- a/package/boot/uboot-layerscape/patches/0087-armv8-ls1012a-Update-bootargs.patch
+++ /dev/null
@@ -1,30 +0,0 @@
-From 5610e5d9a759ecf48eccc1271aea8f8bc3399b50 Mon Sep 17 00:00:00 2001
-From: Pratiyush Mohan Srivastava <pratiyush.srivastava at nxp.com>
-Date: Wed, 17 Aug 2016 18:31:53 +0530
-Subject: [PATCH 87/93] armv8/ls1012a: Update bootargs
-
-Add optimization parameters like "quiet" in bootargs to reduce the system
-boot time
-
-Signed-off-by: Pratiyush Mohan Srivastava <pratiyush.srivastava at nxp.com>
-Signed-off-by: Harninder Rai <harninder.rai at nxp.com>
----
- include/configs/ls1012a_common.h | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
-diff --git a/include/configs/ls1012a_common.h b/include/configs/ls1012a_common.h
-index 7e935ad..0489492 100644
---- a/include/configs/ls1012a_common.h
-+++ b/include/configs/ls1012a_common.h
-@@ -153,7 +153,7 @@
- #define CONFIG_BOOTCOMMAND "bootm $kernel_load"
- #else
- #define CONFIG_BOOTARGS "console=ttyS0,115200 root=/dev/ram0 " \
-- "earlycon=uart8250,mmio,0x21c0500"
-+ "earlycon=uart8250,mmio,0x21c0500 quiet lpj=250000"
- #define CONFIG_BOOTCOMMAND "pfe stop; sf probe 0:0; sf read $kernel_load "\
- "$kernel_start $kernel_size && "\
- "bootm $kernel_load"
---
-1.7.9.5
-
diff --git a/package/boot/uboot-layerscape/patches/0088-driver-spi-enable-stm_get_locked_range-for-spansion-.patch b/package/boot/uboot-layerscape/patches/0088-driver-spi-enable-stm_get_locked_range-for-spansion-.patch
deleted file mode 100644
index 46efca7..0000000
--- a/package/boot/uboot-layerscape/patches/0088-driver-spi-enable-stm_get_locked_range-for-spansion-.patch
+++ /dev/null
@@ -1,31 +0,0 @@
-From b045189aef457833face5d7c4506e908289d2bfe Mon Sep 17 00:00:00 2001
-From: Yunhui Cui <yunhui.cui at nxp.com>
-Date: Thu, 18 Aug 2016 11:24:46 +0800
-Subject: [PATCH 88/93] driver: spi: enable stm_get_locked_range() for
- spansion flash
-
-stm_get_locked_range() is also applicable for spansion flash, So we can
-share it.
-
-Signed-off-by: Yunhui Cui <yunhui.cui at nxp.com>
----
- drivers/mtd/spi/spi_flash.c | 3 ++-
- 1 file changed, 2 insertions(+), 1 deletion(-)
-
-diff --git a/drivers/mtd/spi/spi_flash.c b/drivers/mtd/spi/spi_flash.c
-index 87a92e9..d69d2c3 100644
---- a/drivers/mtd/spi/spi_flash.c
-+++ b/drivers/mtd/spi/spi_flash.c
-@@ -702,7 +702,8 @@ int sst_write_bp(struct spi_flash *flash, u32 offset, size_t len,
- }
- #endif
-
--#if defined(CONFIG_SPI_FLASH_STMICRO) || defined(CONFIG_SPI_FLASH_SST)
-+#if defined(CONFIG_SPI_FLASH_STMICRO) || defined(CONFIG_SPI_FLASH_SST) || \
-+ defined(CONFIG_SPI_FLASH_SPANSION)
- static void stm_get_locked_range(struct spi_flash *flash, u8 sr, loff_t *ofs,
- u32 *len)
- {
---
-1.7.9.5
-
diff --git a/package/boot/uboot-layerscape/patches/0089-driver-spi-fix-id-enclosure-error.patch b/package/boot/uboot-layerscape/patches/0089-driver-spi-fix-id-enclosure-error.patch
deleted file mode 100644
index d75a8d9..0000000
--- a/package/boot/uboot-layerscape/patches/0089-driver-spi-fix-id-enclosure-error.patch
+++ /dev/null
@@ -1,27 +0,0 @@
-From 17c9f2a306b56d5ec5e5c54ce9abba6926831c46 Mon Sep 17 00:00:00 2001
-From: Yutang Jiang <yutang.jiang at nxp.com>
-Date: Fri, 23 Sep 2016 04:21:38 +0800
-Subject: [PATCH 89/93] driver: spi: fix id enclosure error
-
-Signed-off-by: Yutang Jiang <yutang.jiang at nxp.com>
----
- drivers/mtd/spi/spi_flash.c | 2 --
- 1 file changed, 2 deletions(-)
-
-diff --git a/drivers/mtd/spi/spi_flash.c b/drivers/mtd/spi/spi_flash.c
-index d69d2c3..dcb1628 100644
---- a/drivers/mtd/spi/spi_flash.c
-+++ b/drivers/mtd/spi/spi_flash.c
-@@ -1206,9 +1206,7 @@ int spi_flash_scan(struct spi_flash *flash)
- u8 idcode[5];
- u8 cmd;
- int ret;
--#ifdef CONFIG_SPI_FLASH_SPANSION
- u8 id[6];
--#endif
-
- /* Read the ID codes */
- ret = spi_flash_cmd(spi, CMD_READ_ID, idcode, sizeof(idcode));
---
-1.7.9.5
-
diff --git a/package/boot/uboot-layerscape/patches/0090-ls1012-add-CONFIG_SYS_FSL_MAX_NUM_OF_SEC-define.patch b/package/boot/uboot-layerscape/patches/0090-ls1012-add-CONFIG_SYS_FSL_MAX_NUM_OF_SEC-define.patch
deleted file mode 100644
index d514913..0000000
--- a/package/boot/uboot-layerscape/patches/0090-ls1012-add-CONFIG_SYS_FSL_MAX_NUM_OF_SEC-define.patch
+++ /dev/null
@@ -1,25 +0,0 @@
-From 0a8ebc8b855275b5fa035f33a964316d2b7b9a9e Mon Sep 17 00:00:00 2001
-From: Yutang Jiang <yutang.jiang at nxp.com>
-Date: Fri, 23 Sep 2016 04:34:29 +0800
-Subject: [PATCH 90/93] ls1012: add CONFIG_SYS_FSL_MAX_NUM_OF_SEC define
-
-Signed-off-by: Yutang Jiang <yutang.jiang at nxp.com>
----
- arch/arm/include/asm/arch-fsl-layerscape/config.h | 1 +
- 1 file changed, 1 insertion(+)
-
-diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h b/arch/arm/include/asm/arch-fsl-layerscape/config.h
-index efaa79a..f1eb0d7 100644
---- a/arch/arm/include/asm/arch-fsl-layerscape/config.h
-+++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h
-@@ -246,6 +246,7 @@
- #define CONFIG_SYS_FSL_SFP_BE
- #define CONFIG_SYS_FSL_SRK_LE
- #define CONFIG_KEY_REVOCATION
-+#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1
-
- #else
- #error SoC not defined
---
-1.7.9.5
-
diff --git a/package/boot/uboot-layerscape/patches/0091-armv8-fsl-layerscape-ls1012ardb-configs-disable-FSL_.patch b/package/boot/uboot-layerscape/patches/0091-armv8-fsl-layerscape-ls1012ardb-configs-disable-FSL_.patch
deleted file mode 100644
index 62fc1b8..0000000
--- a/package/boot/uboot-layerscape/patches/0091-armv8-fsl-layerscape-ls1012ardb-configs-disable-FSL_.patch
+++ /dev/null
@@ -1,47 +0,0 @@
-From da79bd42be7226c6db58b21b1fed595587d8dcaa Mon Sep 17 00:00:00 2001
-From: Yutang Jiang <yutang.jiang at nxp.com>
-Date: Tue, 18 Oct 2016 18:44:23 +0800
-Subject: [PATCH 91/93] armv8: fsl-layerscape: ls1012ardb: configs: disable
- FSL_LS_PPA and remove aarch32 config
-
-Signed-off-by: Yutang Jiang <yutang.jiang at nxp.com>
----
- configs/ls1012ardb_aarch32_qspi_defconfig | 11 -----------
- configs/ls1012ardb_qspi_defconfig | 3 ++-
- 2 files changed, 2 insertions(+), 12 deletions(-)
- delete mode 100644 configs/ls1012ardb_aarch32_qspi_defconfig
-
-diff --git a/configs/ls1012ardb_aarch32_qspi_defconfig b/configs/ls1012ardb_aarch32_qspi_defconfig
-deleted file mode 100644
-index df16f3b..0000000
---- a/configs/ls1012ardb_aarch32_qspi_defconfig
-+++ /dev/null
-@@ -1,11 +0,0 @@
--CONFIG_ARM=y
--CONFIG_TARGET_LS1012ARDB=y
--CONFIG_SYS_EXTRA_OPTIONS="QSPI_BOOT"
--# CONFIG_CMD_IMLS is not set
--# CONFIG_FSL_LS_PPA is not set
--CONFIG_SYS_NS16550=y
--CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1012a-rdb"
--CONFIG_OF_CONTROL=y
--CONFIG_DM=y
--CONFIG_SPI_FLASH=y
--CONFIG_DM_SPI=y
-diff --git a/configs/ls1012ardb_qspi_defconfig b/configs/ls1012ardb_qspi_defconfig
-index 00e4dd2..df16f3b 100644
---- a/configs/ls1012ardb_qspi_defconfig
-+++ b/configs/ls1012ardb_qspi_defconfig
-@@ -1,7 +1,8 @@
- CONFIG_ARM=y
- CONFIG_TARGET_LS1012ARDB=y
--CONFIG_SYS_EXTRA_OPTIONS="QSPI_BOOT, FSL_LS_PPA"
-+CONFIG_SYS_EXTRA_OPTIONS="QSPI_BOOT"
- # CONFIG_CMD_IMLS is not set
-+# CONFIG_FSL_LS_PPA is not set
- CONFIG_SYS_NS16550=y
- CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1012a-rdb"
- CONFIG_OF_CONTROL=y
---
-1.7.9.5
-
diff --git a/package/boot/uboot-layerscape/patches/0092-armv8-set-openwrt-lede-default-boot-env-for-ls1012ar.patch b/package/boot/uboot-layerscape/patches/0092-armv8-set-openwrt-lede-default-boot-env-for-ls1012ar.patch
deleted file mode 100644
index aee81f4..0000000
--- a/package/boot/uboot-layerscape/patches/0092-armv8-set-openwrt-lede-default-boot-env-for-ls1012ar.patch
+++ /dev/null
@@ -1,67 +0,0 @@
-From b0f227f32f898bdf52f4ecafc83d1e2f1d6ee6ec Mon Sep 17 00:00:00 2001
-From: Yutang Jiang <yutang.jiang at nxp.com>
-Date: Thu, 27 Oct 2016 23:47:43 +0800
-Subject: [PATCH 92/93] armv8: set openwrt/lede default boot env for
- ls1012ardb
-
-Signed-off-by: Yutang Jiang <yutang.jiang at nxp.com>
----
- include/configs/ls1012a_common.h | 28 +++++++++++++++++++++++++++-
- 1 file changed, 27 insertions(+), 1 deletion(-)
-
-diff --git a/include/configs/ls1012a_common.h b/include/configs/ls1012a_common.h
-index 0489492..b23ba4f 100644
---- a/include/configs/ls1012a_common.h
-+++ b/include/configs/ls1012a_common.h
-@@ -130,6 +130,24 @@
-
- #define CONFIG_DISPLAY_CPUINFO
-
-+#define WRTBOOT_DEFAULT "pfe stop && sf probe 0:0 && setenv bootargs " \
-+ "root=/dev/mtdblock5 rootfstype=squashfs,jffs2 noinitrd console=ttyS0,115200 " \
-+ "earlycon=uart8250,mmio,0x21c0500 mtdparts=1550000.quadspi:1M(rcw)," \
-+ "1M(u-boot),1M(u-boot-env),1M(dtb),5M(kernel),23M(rootfs),32M(user)" \
-+ " && sf read $fdtaddr 0x300000 100000 && " \
-+ "sf read $loadaddr 0x400000 500000 && bootm $loadaddr - $fdtaddr"
-+
-+#define WRTBOOT_EXT4RFS "pfe stop && sf probe 0:0 && setenv bootargs " \
-+ "root=/dev/mtdblock5 rootfstype=ext4 noinitrd console=ttyS0,115200 " \
-+ "earlycon=uart8250,mmio,0x21c0500 mtdparts=1550000.quadspi:1M(rcw)," \
-+ "1M(u-boot),1M(u-boot-env),1M(dtb),5M(kernel),23M(ext4rfs),32M(user)" \
-+ " && sf read $fdtaddr 0x300000 100000 && " \
-+ "sf read $loadaddr 0x400000 500000 && bootm $loadaddr - $fdtaddr"
-+
-+#define WRTUPDATE_DEFAULT " sf probe 0:0 && tftp 0xa0000000 <tftp_folder>/" \
-+ "lede-layerscape-64b-ls1012ardb-squashfs-firmware.ext4.bin && protect off all" \
-+ " && sf erase 0 $filesize && sf write 0xa0000000 0 $filesize; reset"
-+
- /* Initial environment variables */
- #define CONFIG_EXTRA_ENV_SETTINGS \
- "initrd_high=0xffffffff\0" \
-@@ -144,6 +162,12 @@
- "kernel_start=0xa00000\0" \
- "kernel_load=0xa0000000\0" \
- "kernel_size=0x2800000\0" \
-+ "loadaddr=82000000\0" \
-+ "ramdiskaddr=88000000\0" \
-+ "fdtaddr=8f000000\0" \
-+ "wrtboot=" WRTBOOT_DEFAULT "\0" \
-+ "wrtboot_ext4rfs=" WRTBOOT_EXT4RFS "\0" \
-+ "wrtupdate=" WRTUPDATE_DEFAULT "\0" \
- "console=ttyAMA0,38400n8\0"
-
- #ifdef CONFIG_EMU
-@@ -158,7 +182,9 @@
- "$kernel_start $kernel_size && "\
- "bootm $kernel_load"
- #endif
--#define CONFIG_BOOTDELAY 10
-+#define CONFIG_BOOTDELAY 3
-+#undef CONFIG_BOOTCOMMAND
-+#define CONFIG_BOOTCOMMAND "run wrtboot_ext4rfs"
-
- /* Monitor Command Prompt */
- #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
---
-1.7.9.5
-
diff --git a/package/boot/uboot-layerscape/patches/0093-add-byte_swap.tcl-script-for-uboot-can-run-save-in-q.patch b/package/boot/uboot-layerscape/patches/0093-add-byte_swap.tcl-script-for-uboot-can-run-save-in-q.patch
deleted file mode 100644
index 5bcdd81..0000000
--- a/package/boot/uboot-layerscape/patches/0093-add-byte_swap.tcl-script-for-uboot-can-run-save-in-q.patch
+++ /dev/null
@@ -1,70 +0,0 @@
-From f13ff4fe020c9018eb5a472b7c8a69a54e45ce29 Mon Sep 17 00:00:00 2001
-From: Yutang Jiang <yutang.jiang at nxp.com>
-Date: Tue, 18 Oct 2016 22:37:17 +0800
-Subject: [PATCH 93/93] add byte_swap.tcl script for uboot can run/save in
- qspi flash
-
-Signed-off-by: Yutang Jiang <yutang.jiang at nxp.com>
----
- Makefile | 1 +
- byte_swap.tcl | 36 ++++++++++++++++++++++++++++++++++++
- 2 files changed, 37 insertions(+)
- create mode 100755 byte_swap.tcl
-
-diff --git a/Makefile b/Makefile
-index 1c2818c..b73375f 100644
---- a/Makefile
-+++ b/Makefile
-@@ -836,6 +836,7 @@ dtbs dts/dt.dtb: checkdtc u-boot
-
- u-boot-dtb.bin: u-boot.bin dts/dt.dtb FORCE
- $(call if_changed,cat)
-+ tclsh byte_swap.tcl u-boot-dtb.bin u-boot-swap.bin 8
-
- %.imx: %.bin
- $(Q)$(MAKE) $(build)=arch/arm/imx-common $@
-diff --git a/byte_swap.tcl b/byte_swap.tcl
-new file mode 100755
-index 0000000..a4e8008
---- /dev/null
-+++ b/byte_swap.tcl
-@@ -0,0 +1,36 @@
-+puts $argv
-+set i_file [lindex $argv 0]
-+set o_file [lindex $argv 1]
-+set num_b [lindex $argv 2]
-+puts ""
-+
-+set fileid_i [open $i_file "r"]
-+set fileid_o [open $o_file "w+"]
-+fconfigure $fileid_i -translation {binary binary}
-+fconfigure $fileid_o -translation {binary binary}
-+
-+set old_bin [read $fileid_i]
-+set new_bin {}
-+set old_length [string length $old_bin]
-+set old_rem [expr $old_length % $num_b]
-+if {$old_rem != 0} {
-+ for {set i 0} {$i< [expr $num_b - $old_rem]} {incr i 1} {
-+ append old_bin y
-+ }
-+}
-+for {set i 0} {$i<[string length $old_bin]} {incr i $num_b} {
-+ for {set j $num_b} {$j>0} {incr j -1} {
-+ append new_bin [string index $old_bin [expr $i+($j-1)]]
-+ }
-+}
-+
-+for {set i 0} {$i<[string length $old_bin]} {incr i $num_b} {
-+ set binValue [string range $old_bin [expr $i+0] [expr $i+($num_b-1)]]
-+ binary scan $binValue H[expr $num_b*2] hexValue
-+
-+ set binValue [string range $new_bin [expr $i+0] [expr $i+($num_b-1)]]
-+ binary scan $binValue H[expr $num_b*2] hexValue
-+}
-+
-+puts -nonewline $fileid_o $new_bin
-+close $fileid_o
---
-1.7.9.5
-
diff --git a/package/boot/uboot-layerscape/patches/0094-using-perl-script-byte_swap.pl-to-replace-tcl-script.patch b/package/boot/uboot-layerscape/patches/0094-using-perl-script-byte_swap.pl-to-replace-tcl-script.patch
deleted file mode 100644
index 8040ad2..0000000
--- a/package/boot/uboot-layerscape/patches/0094-using-perl-script-byte_swap.pl-to-replace-tcl-script.patch
+++ /dev/null
@@ -1,72 +0,0 @@
-From 61cf7655f6f165645d1659c7b256be4397d67572 Mon Sep 17 00:00:00 2001
-From: Yutang Jiang <yutang.jiang at nxp.com>
-Date: Tue, 15 Nov 2016 20:57:37 +0800
-Subject: [PATCH 94/94] using perl script:byte_swap.pl to replace tcl
- script:byte_swap.tcl
-
-Signed-off-by: Yutang Jiang <yutang.jiang at nxp.com>
----
- Makefile | 2 +-
- byte_swap.pl | 37 +++++++++++++++++++++++++++++++++++++
- 2 files changed, 38 insertions(+), 1 deletion(-)
- create mode 100755 byte_swap.pl
-
-diff --git a/Makefile b/Makefile
-index b73375f..5293bc5 100644
---- a/Makefile
-+++ b/Makefile
-@@ -836,7 +836,7 @@ dtbs dts/dt.dtb: checkdtc u-boot
-
- u-boot-dtb.bin: u-boot.bin dts/dt.dtb FORCE
- $(call if_changed,cat)
-- tclsh byte_swap.tcl u-boot-dtb.bin u-boot-swap.bin 8
-+ perl byte_swap.pl u-boot-dtb.bin u-boot-swap.bin 8
-
- %.imx: %.bin
- $(Q)$(MAKE) $(build)=arch/arm/imx-common $@
-diff --git a/byte_swap.pl b/byte_swap.pl
-new file mode 100755
-index 0000000..1707139
---- /dev/null
-+++ b/byte_swap.pl
-@@ -0,0 +1,37 @@
-+#!/usr/bin/perl
-+#
-+# Copyright (C) 2016 Jiang Yutang <jiangyutang1978 at gmail.com>
-+#
-+# This is free software, licensed under the GNU General Public License v2.
-+# See /LICENSE for more information.
-+#
-+open F_I, '<', $ARGV[0] or die "Error:$!\n";
-+open F_O, '>', $ARGV[1] or die "Error:$!\n";
-+$i_size = (stat $ARGV[0])[7];
-+
-+undef $/;
-+$str_i=<F_I>;
-+(@ary_i)=unpack("C$i_size", $str_i);
-+
-+if ( ($i_size % $ARGV[2]) != 0 )
-+{
-+ for ($i=0; $i<$ARGV[2] - ($i_size % $ARGV[2]); $i++)
-+ {
-+ $ary_i[$i_size + $i]=0;
-+ }
-+ $i_size=$i_size + ($ARGV[2] - ($i_size % $ARGV[2]));
-+}
-+
-+for ($i=0; $i<$i_size; $i += $ARGV[2])
-+{
-+ for ($j=0; $j<$ARGV[2]; $j++)
-+ {
-+ $ary_o[$i+$j]=$ary_i[$i+$ARGV[2]-$j-1];
-+ }
-+}
-+
-+binmode F_O;
-+print(F_O pack("C$i_size", @ary_o));
-+
-+close F_I;
-+close F_O;
---
-1.7.9.5
-
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