[source] lantiq: add FRITZ7360SL phy reset gpios

[LEDE Commits]

mkresin pushed a commit to source.git, branch master:
https://git.lede-project.org/7dd42d610dcd6f9271d5d44edff52caf633b8abf

commit 7dd42d610dcd6f9271d5d44edff52caf633b8abf
Author: Mathias Kresin <dev at kresin.me>
AuthorDate: Wed Dec 21 09:59:29 2016 +0100

    lantiq: add FRITZ7360SL phy reset gpios
    
    Due to a hardware bug of Atheros 8030 phys, the driver need to reset
    the phys on link state change.
    
    Use the correct compatible string for the at903x phys connected to
    switch port 0 and 1.
    
    Fix the pinmux of the gpio lines connected to the reset pin of the phys
    and define the reset-pins to let the driver do the fixups.
    
    Fixes FS#343
    
    Signed-off-by: Mathias Kresin <dev at kresin.me>
---
 target/linux/lantiq/dts/FRITZ7360SL.dts | 10 +++++-----
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/target/linux/lantiq/dts/FRITZ7360SL.dts b/target/linux/lantiq/dts/FRITZ7360SL.dts
index b3cb1c5..0caea7f 100644
--- a/target/linux/lantiq/dts/FRITZ7360SL.dts
+++ b/target/linux/lantiq/dts/FRITZ7360SL.dts
@@ -70,7 +70,7 @@
 				};
 				phy-rst {
 					lantiq,pins = "io37", "io44";
-					lantiq,pull = <2>;
+					lantiq,pull = <0>;
 					lantiq,open-drain;
 					lantiq,output = <1>;
 				};
@@ -160,14 +160,12 @@
 			reg = <0>;
 			phy-mode = "rmii";
 			phy-handle = <&phy0>;
-			// gpios = <&gpio 37 GPIO_ACTIVE_LOW>;
 		};
 		ethernet at 1 {
 			compatible = "lantiq,xrx200-pdi-port";
 			reg = <1>;
 			phy-mode = "rmii";
 			phy-handle = <&phy1>;
-			// gpios = <&gpio 44 GPIO_ACTIVE_LOW>;
 		};
 		ethernet at 2 {
 			compatible = "lantiq,xrx200-pdi-port";
@@ -189,11 +187,13 @@
 		compatible = "lantiq,xrx200-mdio";
 		phy0: ethernet-phy at 0 {
 			reg = <0x00>;
-			compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22";
+			compatible = "ethernet-phy-id004d.d076", "ethernet-phy-ieee802.3-c22";
+			reset-gpios = <&gpio 37 GPIO_ACTIVE_LOW>;
 		};
 		phy1: ethernet-phy at 1 {
 			reg = <0x01>;
-			compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22";
+			compatible = "ethernet-phy-id004d.d076", "ethernet-phy-ieee802.3-c22";
+			reset-gpios = <&gpio 44 GPIO_ACTIVE_LOW>;
 		};
 		phy11: ethernet-phy at 11 {
 			reg = <0x11>;