[FS#992] bad system clock on MT7620A

[LEDE Bugs]

The following task has a new comment added:

FS#992 - bad system clock on MT7620A
User who did this - Mathias Kresin (mkresin)

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Come on! Have a look at the mt7620 datasheet, the DRAM CLK divider is kind of fixed.

Pin Name: {SPI_WP, SPI_HOLD}
Boot Strapping Signal Name: DRAM_TYPE
Description:

  * 1: DDR1 (CPU/3) TSOP Package
  * 2: DDR2 (CPU/3) FBGA Package
  * 3: SDRAM (CPU/5) (LVTTL 3.3 V) TSOP Package

If you increase the CPU clock the DRAM CLK will be higher. Nevertheless, 193.33MHz is the correct DDR2 clock for a CPU running at 580MHz.
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More information can be found at the following URL:
https://bugs.lede-project.org/index.php?do=details&task_id=992#comment3370