[RFC PATCH v5 09/10] iommu/riscv: Add dirty tracking support for second-stage domains

[Nutty.Liu]

On 10/20/2026 5:41 PM, fangyu.yu at linux.alibaba.com wrote:
> From: Fangyu Yu <fangyu.yu at linux.alibaba.com>
>
> Add hardware dirty tracking support for second-stage (iohgatp) domains
> used in KVM VFIO device pass-through.
>
> The RISC-V IOMMU can automatically set the dirty bit in PTEs on write
> access when DC.tc.GADE is set and the hardware has AMO_HWAD capability.
> Wire this up to the iommufd dirty tracking interface:
>
>    - riscv_iommu_set_dirty_tracking(): Always enabled dirty tracking for
>      second-stage domain.
>
>    - riscv_iommu_dirty_ops: Exposes set_dirty_tracking and the generic
>      page-table read_and_clear_dirty via IOMMU_PT_DIRTY_OPS(riscv_64).
>
>    - domain_alloc_paging_flags: Assigns dirty_ops to second-stage domains
>      when AMO_HWAD is advertised in hardware capabilities.
>
>    - riscv_iommu_capable: Reports IOMMU_CAP_DIRTY_TRACKING when
>      AMO_HWAD is present.
>
> Signed-off-by: Fangyu Yu <fangyu.yu at linux.alibaba.com>
Reviewed-by: Nutty Liu <nutty.liu at hotmail.com>

Thanks,
Nutty
> ---
>   drivers/iommu/riscv/iommu.c | 21 +++++++++++++++++++++
>   1 file changed, 21 insertions(+)
>
> diff --git a/drivers/iommu/riscv/iommu.c b/drivers/iommu/riscv/iommu.c
> index 9310b818c038..e3791e912af3 100644
> --- a/drivers/iommu/riscv/iommu.c
> +++ b/drivers/iommu/riscv/iommu.c
> @@ -1376,6 +1376,21 @@ static int riscv_iommu_attach_paging_domain(struct iommu_domain *iommu_domain,
>   	return 0;
>   }
>   
> +static int riscv_iommu_set_dirty_tracking(struct iommu_domain *iommu_domain,
> +					  bool enable)
> +{
> +	/*
> +	 * Always enabled and the dirty bitmap is cleared prior to
> +	 * set_dirty_tracking().
> +	 */
> +	return 0;
> +}
> +
> +static const struct iommu_dirty_ops riscv_iommu_dirty_ops = {
> +	IOMMU_PT_DIRTY_OPS(riscv_64),
> +	.set_dirty_tracking = riscv_iommu_set_dirty_tracking,
> +};
> +
>   static const struct iommu_domain_ops riscv_iommu_paging_domain_ops = {
>   	IOMMU_PT_DOMAIN_OPS(riscv_64),
>   	.attach_dev = riscv_iommu_attach_paging_domain,
> @@ -1466,6 +1481,8 @@ riscv_iommu_domain_alloc_paging_flags(struct device *dev, u32 flags,
>   			goto err_free;
>   		}
>   		cfg.common.features |= BIT(PT_FEAT_RISCV_S2);
> +		if (iommu->caps & RISCV_IOMMU_CAPABILITIES_AMO_HWAD)
> +			domain->domain.dirty_ops = &riscv_iommu_dirty_ops;
>   		break;
>   	default:
>   		ret = -EOPNOTSUPP;
> @@ -1541,9 +1558,13 @@ static struct iommu_group *riscv_iommu_device_group(struct device *dev)
>   
>   static bool riscv_iommu_capable(struct device *dev, enum iommu_cap cap)
>   {
> +	struct riscv_iommu_device *iommu = dev_to_iommu(dev);
> +
>   	switch (cap) {
>   	case IOMMU_CAP_CACHE_COHERENCY:
>   		return true;
> +	case IOMMU_CAP_DIRTY_TRACKING:
> +		return !!(iommu->caps & RISCV_IOMMU_CAPABILITIES_AMO_HWAD);
>   	default:
>   		return false;
>   	}