[RFC PATCH 03/12] iommufd: Add RISC-V IOMMU cache invalidation data type
Gong Shuai
gong.shuai at sanechips.com.cn
Wed Oct 14 23:52:23 PDT 2026
From: Wu Fei <wu.fei9 at sanechips.com.cn>
Add IOMMU_VIOMMU_INVALIDATE_DATA_RISCV and the matching
struct iommu_viommu_riscv_invalidate, so user space can pass RISC-V
IOMMU IOTINVAL commands to the vIOMMU cache invalidation path using a
payload layout that is shared with the kernel, instead of relying on the
driver internal struct riscv_iommu_command.
Signed-off-by: Wu Fei <wu.fei9 at sanechips.com.cn>
Co-developed-by: Gong Shuai <gong.shuai at sanechips.com.cn>
Signed-off-by: Gong Shuai <gong.shuai at sanechips.com.cn>
---
include/uapi/linux/iommufd.h | 27 +++++++++++++++++++++++++++
1 file changed, 27 insertions(+)
diff --git a/include/uapi/linux/iommufd.h b/include/uapi/linux/iommufd.h
index 7458878386c5..36e6187bb34b 100644
--- a/include/uapi/linux/iommufd.h
+++ b/include/uapi/linux/iommufd.h
@@ -903,10 +903,12 @@ struct iommu_hwpt_get_dirty_bitmap {
* Data Type
* @IOMMU_HWPT_INVALIDATE_DATA_VTD_S1: Invalidation data for VTD_S1
* @IOMMU_VIOMMU_INVALIDATE_DATA_ARM_SMMUV3: Invalidation data for ARM SMMUv3
+ * @IOMMU_VIOMMU_INVALIDATE_DATA_RISCV: Invalidation data for RISC-V IOMMU
*/
enum iommu_hwpt_invalidate_data_type {
IOMMU_HWPT_INVALIDATE_DATA_VTD_S1 = 0,
IOMMU_VIOMMU_INVALIDATE_DATA_ARM_SMMUV3 = 1,
+ IOMMU_VIOMMU_INVALIDATE_DATA_RISCV = 2,
};
/**
@@ -967,6 +969,31 @@ struct iommu_viommu_arm_smmuv3_invalidate {
__aligned_le64 cmd[2];
};
+/**
+ * struct iommu_viommu_riscv_invalidate - RISC-V IOMMU cache invalidation
+ * (IOMMU_VIOMMU_INVALIDATE_DATA_RISCV)
+ * @cmd: 128-bit cache invalidation command that runs in the IOMMU command
+ * queue, in the format defined by the "IOMMU Page-table cache
+ * invalidation" section of the RISC-V IOMMU specification. Must be
+ * little-endian.
+ *
+ * Supported command list only when passing in a vIOMMU via @hwpt_id:
+ * IOTINVAL.VMA
+ *
+ * The isolation operands are owned by the kernel, which overwrites them
+ * before the command is issued:
+ * GV = 1 and GSCID = the GSCID assigned to the vIOMMU
+ * PSCV = 1 and PSCID = 0
+ *
+ * All other reserved bits must be 0.
+ *
+ * -EIO will be returned if the command is not supported, -EINVAL if it is
+ * malformed.
+ */
+struct iommu_viommu_riscv_invalidate {
+ __aligned_le64 cmd[2];
+};
+
/**
* struct iommu_hwpt_invalidate - ioctl(IOMMU_HWPT_INVALIDATE)
* @size: sizeof(struct iommu_hwpt_invalidate)
--
2.53.0
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